OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000116ac 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000498 08011950 08011950 00012950 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 08011de8 08011de8 00012de8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 08011df0 08011df0 00012df0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 08011df4 08011df4 00012df4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 00000210 24000000 08011df8 00013000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 000130c4 24000220 08012008 00013220 2**5 ALLOC 8 ._user_heap_stack 00000604 240132e4 08012008 000132e4 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 00013210 2**0 CONTENTS, READONLY 10 .debug_info 0004a7ba 00000000 00000000 0001323e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 00007f45 00000000 00000000 0005d9f8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00002078 00000000 00000000 00065940 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0004021d 00000000 00000000 000679b8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 0004687b 00000000 00000000 000a7bd5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 0018947f 00000000 00000000 000ee450 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 002778cf 2**0 CONTENTS, READONLY 17 .debug_rnglists 00003ae7 00000000 00000000 00277912 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 00007014 00000000 00000000 0027b3fc 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_loclists 0001fff2 00000000 00000000 00282410 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .debug_line_str 00000066 00000000 00000000 002a2402 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 24000220 .word 0x24000220 80002bc: 00000000 .word 0x00000000 80002c0: 08011934 .word 0x08011934 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 24000224 .word 0x24000224 80002dc: 08011934 .word 0x08011934 080002e0 : 80002e0: f001 01ff and.w r1, r1, #255 @ 0xff 80002e4: 2a10 cmp r2, #16 80002e6: db2b blt.n 8000340 80002e8: f010 0f07 tst.w r0, #7 80002ec: d008 beq.n 8000300 80002ee: f810 3b01 ldrb.w r3, [r0], #1 80002f2: 3a01 subs r2, #1 80002f4: 428b cmp r3, r1 80002f6: d02d beq.n 8000354 80002f8: f010 0f07 tst.w r0, #7 80002fc: b342 cbz r2, 8000350 80002fe: d1f6 bne.n 80002ee 8000300: b4f0 push {r4, r5, r6, r7} 8000302: ea41 2101 orr.w r1, r1, r1, lsl #8 8000306: ea41 4101 orr.w r1, r1, r1, lsl #16 800030a: f022 0407 bic.w r4, r2, #7 800030e: f07f 0700 mvns.w r7, #0 8000312: 2300 movs r3, #0 8000314: e8f0 5602 ldrd r5, r6, [r0], #8 8000318: 3c08 subs r4, #8 800031a: ea85 0501 eor.w r5, r5, r1 800031e: ea86 0601 eor.w r6, r6, r1 8000322: fa85 f547 uadd8 r5, r5, r7 8000326: faa3 f587 sel r5, r3, r7 800032a: fa86 f647 uadd8 r6, r6, r7 800032e: faa5 f687 sel r6, r5, r7 8000332: b98e cbnz r6, 8000358 8000334: d1ee bne.n 8000314 8000336: bcf0 pop {r4, r5, r6, r7} 8000338: f001 01ff and.w r1, r1, #255 @ 0xff 800033c: f002 0207 and.w r2, r2, #7 8000340: b132 cbz r2, 8000350 8000342: f810 3b01 ldrb.w r3, [r0], #1 8000346: 3a01 subs r2, #1 8000348: ea83 0301 eor.w r3, r3, r1 800034c: b113 cbz r3, 8000354 800034e: d1f8 bne.n 8000342 8000350: 2000 movs r0, #0 8000352: 4770 bx lr 8000354: 3801 subs r0, #1 8000356: 4770 bx lr 8000358: 2d00 cmp r5, #0 800035a: bf06 itte eq 800035c: 4635 moveq r5, r6 800035e: 3803 subeq r0, #3 8000360: 3807 subne r0, #7 8000362: f015 0f01 tst.w r5, #1 8000366: d107 bne.n 8000378 8000368: 3001 adds r0, #1 800036a: f415 7f80 tst.w r5, #256 @ 0x100 800036e: bf02 ittt eq 8000370: 3001 addeq r0, #1 8000372: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000376: 3001 addeq r0, #1 8000378: bcf0 pop {r4, r5, r6, r7} 800037a: 3801 subs r0, #1 800037c: 4770 bx lr 800037e: bf00 nop 08000380 : 8000380: 4603 mov r3, r0 8000382: f813 2b01 ldrb.w r2, [r3], #1 8000386: 2a00 cmp r2, #0 8000388: d1fb bne.n 8000382 800038a: 1a18 subs r0, r3, r0 800038c: 3801 subs r0, #1 800038e: 4770 bx lr 08000390 <__aeabi_uldivmod>: 8000390: b953 cbnz r3, 80003a8 <__aeabi_uldivmod+0x18> 8000392: b94a cbnz r2, 80003a8 <__aeabi_uldivmod+0x18> 8000394: 2900 cmp r1, #0 8000396: bf08 it eq 8000398: 2800 cmpeq r0, #0 800039a: bf1c itt ne 800039c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80003a0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80003a4: f000 b96a b.w 800067c <__aeabi_idiv0> 80003a8: f1ad 0c08 sub.w ip, sp, #8 80003ac: e96d ce04 strd ip, lr, [sp, #-16]! 80003b0: f000 f806 bl 80003c0 <__udivmoddi4> 80003b4: f8dd e004 ldr.w lr, [sp, #4] 80003b8: e9dd 2302 ldrd r2, r3, [sp, #8] 80003bc: b004 add sp, #16 80003be: 4770 bx lr 080003c0 <__udivmoddi4>: 80003c0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80003c4: 9d08 ldr r5, [sp, #32] 80003c6: 460c mov r4, r1 80003c8: 2b00 cmp r3, #0 80003ca: d14e bne.n 800046a <__udivmoddi4+0xaa> 80003cc: 4694 mov ip, r2 80003ce: 458c cmp ip, r1 80003d0: 4686 mov lr, r0 80003d2: fab2 f282 clz r2, r2 80003d6: d962 bls.n 800049e <__udivmoddi4+0xde> 80003d8: b14a cbz r2, 80003ee <__udivmoddi4+0x2e> 80003da: f1c2 0320 rsb r3, r2, #32 80003de: 4091 lsls r1, r2 80003e0: fa20 f303 lsr.w r3, r0, r3 80003e4: fa0c fc02 lsl.w ip, ip, r2 80003e8: 4319 orrs r1, r3 80003ea: fa00 fe02 lsl.w lr, r0, r2 80003ee: ea4f 471c mov.w r7, ip, lsr #16 80003f2: fa1f f68c uxth.w r6, ip 80003f6: fbb1 f4f7 udiv r4, r1, r7 80003fa: ea4f 431e mov.w r3, lr, lsr #16 80003fe: fb07 1114 mls r1, r7, r4, r1 8000402: ea43 4301 orr.w r3, r3, r1, lsl #16 8000406: fb04 f106 mul.w r1, r4, r6 800040a: 4299 cmp r1, r3 800040c: d90a bls.n 8000424 <__udivmoddi4+0x64> 800040e: eb1c 0303 adds.w r3, ip, r3 8000412: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000416: f080 8112 bcs.w 800063e <__udivmoddi4+0x27e> 800041a: 4299 cmp r1, r3 800041c: f240 810f bls.w 800063e <__udivmoddi4+0x27e> 8000420: 3c02 subs r4, #2 8000422: 4463 add r3, ip 8000424: 1a59 subs r1, r3, r1 8000426: fa1f f38e uxth.w r3, lr 800042a: fbb1 f0f7 udiv r0, r1, r7 800042e: fb07 1110 mls r1, r7, r0, r1 8000432: ea43 4301 orr.w r3, r3, r1, lsl #16 8000436: fb00 f606 mul.w r6, r0, r6 800043a: 429e cmp r6, r3 800043c: d90a bls.n 8000454 <__udivmoddi4+0x94> 800043e: eb1c 0303 adds.w r3, ip, r3 8000442: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000446: f080 80fc bcs.w 8000642 <__udivmoddi4+0x282> 800044a: 429e cmp r6, r3 800044c: f240 80f9 bls.w 8000642 <__udivmoddi4+0x282> 8000450: 4463 add r3, ip 8000452: 3802 subs r0, #2 8000454: 1b9b subs r3, r3, r6 8000456: ea40 4004 orr.w r0, r0, r4, lsl #16 800045a: 2100 movs r1, #0 800045c: b11d cbz r5, 8000466 <__udivmoddi4+0xa6> 800045e: 40d3 lsrs r3, r2 8000460: 2200 movs r2, #0 8000462: e9c5 3200 strd r3, r2, [r5] 8000466: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800046a: 428b cmp r3, r1 800046c: d905 bls.n 800047a <__udivmoddi4+0xba> 800046e: b10d cbz r5, 8000474 <__udivmoddi4+0xb4> 8000470: e9c5 0100 strd r0, r1, [r5] 8000474: 2100 movs r1, #0 8000476: 4608 mov r0, r1 8000478: e7f5 b.n 8000466 <__udivmoddi4+0xa6> 800047a: fab3 f183 clz r1, r3 800047e: 2900 cmp r1, #0 8000480: d146 bne.n 8000510 <__udivmoddi4+0x150> 8000482: 42a3 cmp r3, r4 8000484: d302 bcc.n 800048c <__udivmoddi4+0xcc> 8000486: 4290 cmp r0, r2 8000488: f0c0 80f0 bcc.w 800066c <__udivmoddi4+0x2ac> 800048c: 1a86 subs r6, r0, r2 800048e: eb64 0303 sbc.w r3, r4, r3 8000492: 2001 movs r0, #1 8000494: 2d00 cmp r5, #0 8000496: d0e6 beq.n 8000466 <__udivmoddi4+0xa6> 8000498: e9c5 6300 strd r6, r3, [r5] 800049c: e7e3 b.n 8000466 <__udivmoddi4+0xa6> 800049e: 2a00 cmp r2, #0 80004a0: f040 8090 bne.w 80005c4 <__udivmoddi4+0x204> 80004a4: eba1 040c sub.w r4, r1, ip 80004a8: ea4f 481c mov.w r8, ip, lsr #16 80004ac: fa1f f78c uxth.w r7, ip 80004b0: 2101 movs r1, #1 80004b2: fbb4 f6f8 udiv r6, r4, r8 80004b6: ea4f 431e mov.w r3, lr, lsr #16 80004ba: fb08 4416 mls r4, r8, r6, r4 80004be: ea43 4304 orr.w r3, r3, r4, lsl #16 80004c2: fb07 f006 mul.w r0, r7, r6 80004c6: 4298 cmp r0, r3 80004c8: d908 bls.n 80004dc <__udivmoddi4+0x11c> 80004ca: eb1c 0303 adds.w r3, ip, r3 80004ce: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 80004d2: d202 bcs.n 80004da <__udivmoddi4+0x11a> 80004d4: 4298 cmp r0, r3 80004d6: f200 80cd bhi.w 8000674 <__udivmoddi4+0x2b4> 80004da: 4626 mov r6, r4 80004dc: 1a1c subs r4, r3, r0 80004de: fa1f f38e uxth.w r3, lr 80004e2: fbb4 f0f8 udiv r0, r4, r8 80004e6: fb08 4410 mls r4, r8, r0, r4 80004ea: ea43 4304 orr.w r3, r3, r4, lsl #16 80004ee: fb00 f707 mul.w r7, r0, r7 80004f2: 429f cmp r7, r3 80004f4: d908 bls.n 8000508 <__udivmoddi4+0x148> 80004f6: eb1c 0303 adds.w r3, ip, r3 80004fa: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 80004fe: d202 bcs.n 8000506 <__udivmoddi4+0x146> 8000500: 429f cmp r7, r3 8000502: f200 80b0 bhi.w 8000666 <__udivmoddi4+0x2a6> 8000506: 4620 mov r0, r4 8000508: 1bdb subs r3, r3, r7 800050a: ea40 4006 orr.w r0, r0, r6, lsl #16 800050e: e7a5 b.n 800045c <__udivmoddi4+0x9c> 8000510: f1c1 0620 rsb r6, r1, #32 8000514: 408b lsls r3, r1 8000516: fa22 f706 lsr.w r7, r2, r6 800051a: 431f orrs r7, r3 800051c: fa20 fc06 lsr.w ip, r0, r6 8000520: fa04 f301 lsl.w r3, r4, r1 8000524: ea43 030c orr.w r3, r3, ip 8000528: 40f4 lsrs r4, r6 800052a: fa00 f801 lsl.w r8, r0, r1 800052e: 0c38 lsrs r0, r7, #16 8000530: ea4f 4913 mov.w r9, r3, lsr #16 8000534: fbb4 fef0 udiv lr, r4, r0 8000538: fa1f fc87 uxth.w ip, r7 800053c: fb00 441e mls r4, r0, lr, r4 8000540: ea49 4404 orr.w r4, r9, r4, lsl #16 8000544: fb0e f90c mul.w r9, lr, ip 8000548: 45a1 cmp r9, r4 800054a: fa02 f201 lsl.w r2, r2, r1 800054e: d90a bls.n 8000566 <__udivmoddi4+0x1a6> 8000550: 193c adds r4, r7, r4 8000552: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 8000556: f080 8084 bcs.w 8000662 <__udivmoddi4+0x2a2> 800055a: 45a1 cmp r9, r4 800055c: f240 8081 bls.w 8000662 <__udivmoddi4+0x2a2> 8000560: f1ae 0e02 sub.w lr, lr, #2 8000564: 443c add r4, r7 8000566: eba4 0409 sub.w r4, r4, r9 800056a: fa1f f983 uxth.w r9, r3 800056e: fbb4 f3f0 udiv r3, r4, r0 8000572: fb00 4413 mls r4, r0, r3, r4 8000576: ea49 4404 orr.w r4, r9, r4, lsl #16 800057a: fb03 fc0c mul.w ip, r3, ip 800057e: 45a4 cmp ip, r4 8000580: d907 bls.n 8000592 <__udivmoddi4+0x1d2> 8000582: 193c adds r4, r7, r4 8000584: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 8000588: d267 bcs.n 800065a <__udivmoddi4+0x29a> 800058a: 45a4 cmp ip, r4 800058c: d965 bls.n 800065a <__udivmoddi4+0x29a> 800058e: 3b02 subs r3, #2 8000590: 443c add r4, r7 8000592: ea43 400e orr.w r0, r3, lr, lsl #16 8000596: fba0 9302 umull r9, r3, r0, r2 800059a: eba4 040c sub.w r4, r4, ip 800059e: 429c cmp r4, r3 80005a0: 46ce mov lr, r9 80005a2: 469c mov ip, r3 80005a4: d351 bcc.n 800064a <__udivmoddi4+0x28a> 80005a6: d04e beq.n 8000646 <__udivmoddi4+0x286> 80005a8: b155 cbz r5, 80005c0 <__udivmoddi4+0x200> 80005aa: ebb8 030e subs.w r3, r8, lr 80005ae: eb64 040c sbc.w r4, r4, ip 80005b2: fa04 f606 lsl.w r6, r4, r6 80005b6: 40cb lsrs r3, r1 80005b8: 431e orrs r6, r3 80005ba: 40cc lsrs r4, r1 80005bc: e9c5 6400 strd r6, r4, [r5] 80005c0: 2100 movs r1, #0 80005c2: e750 b.n 8000466 <__udivmoddi4+0xa6> 80005c4: f1c2 0320 rsb r3, r2, #32 80005c8: fa20 f103 lsr.w r1, r0, r3 80005cc: fa0c fc02 lsl.w ip, ip, r2 80005d0: fa24 f303 lsr.w r3, r4, r3 80005d4: 4094 lsls r4, r2 80005d6: 430c orrs r4, r1 80005d8: ea4f 481c mov.w r8, ip, lsr #16 80005dc: fa00 fe02 lsl.w lr, r0, r2 80005e0: fa1f f78c uxth.w r7, ip 80005e4: fbb3 f0f8 udiv r0, r3, r8 80005e8: fb08 3110 mls r1, r8, r0, r3 80005ec: 0c23 lsrs r3, r4, #16 80005ee: ea43 4301 orr.w r3, r3, r1, lsl #16 80005f2: fb00 f107 mul.w r1, r0, r7 80005f6: 4299 cmp r1, r3 80005f8: d908 bls.n 800060c <__udivmoddi4+0x24c> 80005fa: eb1c 0303 adds.w r3, ip, r3 80005fe: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 8000602: d22c bcs.n 800065e <__udivmoddi4+0x29e> 8000604: 4299 cmp r1, r3 8000606: d92a bls.n 800065e <__udivmoddi4+0x29e> 8000608: 3802 subs r0, #2 800060a: 4463 add r3, ip 800060c: 1a5b subs r3, r3, r1 800060e: b2a4 uxth r4, r4 8000610: fbb3 f1f8 udiv r1, r3, r8 8000614: fb08 3311 mls r3, r8, r1, r3 8000618: ea44 4403 orr.w r4, r4, r3, lsl #16 800061c: fb01 f307 mul.w r3, r1, r7 8000620: 42a3 cmp r3, r4 8000622: d908 bls.n 8000636 <__udivmoddi4+0x276> 8000624: eb1c 0404 adds.w r4, ip, r4 8000628: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800062c: d213 bcs.n 8000656 <__udivmoddi4+0x296> 800062e: 42a3 cmp r3, r4 8000630: d911 bls.n 8000656 <__udivmoddi4+0x296> 8000632: 3902 subs r1, #2 8000634: 4464 add r4, ip 8000636: 1ae4 subs r4, r4, r3 8000638: ea41 4100 orr.w r1, r1, r0, lsl #16 800063c: e739 b.n 80004b2 <__udivmoddi4+0xf2> 800063e: 4604 mov r4, r0 8000640: e6f0 b.n 8000424 <__udivmoddi4+0x64> 8000642: 4608 mov r0, r1 8000644: e706 b.n 8000454 <__udivmoddi4+0x94> 8000646: 45c8 cmp r8, r9 8000648: d2ae bcs.n 80005a8 <__udivmoddi4+0x1e8> 800064a: ebb9 0e02 subs.w lr, r9, r2 800064e: eb63 0c07 sbc.w ip, r3, r7 8000652: 3801 subs r0, #1 8000654: e7a8 b.n 80005a8 <__udivmoddi4+0x1e8> 8000656: 4631 mov r1, r6 8000658: e7ed b.n 8000636 <__udivmoddi4+0x276> 800065a: 4603 mov r3, r0 800065c: e799 b.n 8000592 <__udivmoddi4+0x1d2> 800065e: 4630 mov r0, r6 8000660: e7d4 b.n 800060c <__udivmoddi4+0x24c> 8000662: 46d6 mov lr, sl 8000664: e77f b.n 8000566 <__udivmoddi4+0x1a6> 8000666: 4463 add r3, ip 8000668: 3802 subs r0, #2 800066a: e74d b.n 8000508 <__udivmoddi4+0x148> 800066c: 4606 mov r6, r0 800066e: 4623 mov r3, r4 8000670: 4608 mov r0, r1 8000672: e70f b.n 8000494 <__udivmoddi4+0xd4> 8000674: 3e02 subs r6, #2 8000676: 4463 add r3, ip 8000678: e730 b.n 80004dc <__udivmoddi4+0x11c> 800067a: bf00 nop 0800067c <__aeabi_idiv0>: 800067c: 4770 bx lr 800067e: bf00 nop 08000680 : void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 8000680: 4770 bx lr 8000682: bf00 nop 08000684 : /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 8000684: 2010 movs r0, #16 8000686: f001 bcb1 b.w 8001fec 800068a: bf00 nop 0800068c : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 800068c: 2104 movs r1, #4 800068e: 4801 ldr r0, [pc, #4] @ (8000694 ) 8000690: f009 bbe2 b.w 8009e58 8000694: 2400054c .word 0x2400054c 08000698 : /* USER CODE END fanTimerCallback */ } /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 8000698: b530 push {r4, r5, lr} /* USER CODE BEGIN motorXTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 800069a: 2400 movs r4, #0 { 800069c: b083 sub sp, #12 MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 800069e: 4d0a ldr r5, [pc, #40] @ (80006c8 ) 80006a0: 2304 movs r3, #4 80006a2: 4622 mov r2, r4 80006a4: 4909 ldr r1, [pc, #36] @ (80006cc ) 80006a6: 4628 mov r0, r5 80006a8: e9cd 4400 strd r4, r4, [sp] 80006ac: f001 fe0c bl 80022c8 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 80006b0: 4621 mov r1, r4 80006b2: 4628 mov r0, r5 80006b4: f009 fbd0 bl 8009e58 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 80006b8: 2104 movs r1, #4 80006ba: 4628 mov r0, r5 /* USER CODE END motorXTimerCallback */ } 80006bc: b003 add sp, #12 80006be: e8bd 4030 ldmia.w sp!, {r4, r5, lr} HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 80006c2: f009 bbc9 b.w 8009e58 80006c6: bf00 nop 80006c8: 24000500 .word 0x24000500 80006cc: 24000290 .word 0x24000290 080006d0 : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 80006d0: b510 push {r4, lr} /* USER CODE BEGIN motorYTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 80006d2: 2000 movs r0, #0 { 80006d4: b082 sub sp, #8 MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 80006d6: 4c0a ldr r4, [pc, #40] @ (8000700 ) 80006d8: 230c movs r3, #12 80006da: 2208 movs r2, #8 80006dc: 4909 ldr r1, [pc, #36] @ (8000704 ) 80006de: e9cd 0000 strd r0, r0, [sp] 80006e2: 4620 mov r0, r4 80006e4: f001 fdf0 bl 80022c8 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 80006e8: 2108 movs r1, #8 80006ea: 4620 mov r0, r4 80006ec: f009 fbb4 bl 8009e58 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 80006f0: 210c movs r1, #12 80006f2: 4620 mov r0, r4 /* USER CODE END motorYTimerCallback */ } 80006f4: b002 add sp, #8 80006f6: e8bd 4010 ldmia.w sp!, {r4, lr} HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 80006fa: f009 bbad b.w 8009e58 80006fe: bf00 nop 8000700: 24000500 .word 0x24000500 8000704: 24000290 .word 0x24000290 08000708 <__io_putchar>: \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 8000708: f04f 4360 mov.w r3, #3758096384 @ 0xe0000000 800070c: f8d3 2e80 ldr.w r2, [r3, #3712] @ 0xe80 8000710: 07d1 lsls r1, r2, #31 8000712: d503 bpl.n 800071c <__io_putchar+0x14> ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 8000714: f8d3 2e00 ldr.w r2, [r3, #3584] @ 0xe00 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 8000718: 07d2 lsls r2, r2, #31 800071a: d401 bmi.n 8000720 <__io_putchar+0x18> } 800071c: 4770 bx lr { while (ITM->PORT[0U].u32 == 0UL) { __NOP(); 800071e: bf00 nop while (ITM->PORT[0U].u32 == 0UL) 8000720: 681a ldr r2, [r3, #0] 8000722: 2a00 cmp r2, #0 8000724: d0fb beq.n 800071e <__io_putchar+0x16> } ITM->PORT[0U].u8 = (uint8_t)ch; 8000726: b2c3 uxtb r3, r0 8000728: f04f 4260 mov.w r2, #3758096384 @ 0xe0000000 800072c: 7013 strb r3, [r2, #0] 800072e: 4770 bx lr 08000730 : if((GPIO_Pin == GPIO_PIN_14) || (GPIO_Pin == GPIO_PIN_15)) 8000730: f5b0 4f80 cmp.w r0, #16384 @ 0x4000 { 8000734: b510 push {r4, lr} 8000736: b082 sub sp, #8 if((GPIO_Pin == GPIO_PIN_14) || (GPIO_Pin == GPIO_PIN_15)) 8000738: d023 beq.n 8000782 800073a: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 800073e: d020 beq.n 8000782 else if ((GPIO_Pin == GPIO_PIN_10) || (GPIO_Pin == GPIO_PIN_11)) 8000740: f5b0 6f80 cmp.w r0, #1024 @ 0x400 8000744: d004 beq.n 8000750 8000746: f5b0 6f00 cmp.w r0, #2048 @ 0x800 800074a: d001 beq.n 8000750 } 800074c: b002 add sp, #8 800074e: bd10 pop {r4, pc} uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8000750: f44f 6100 mov.w r1, #2048 @ 0x800 8000754: 4811 ldr r0, [pc, #68] @ (800079c ) 8000756: f006 fd2b bl 80071b0 800075a: f44f 6180 mov.w r1, #1024 @ 0x400 800075e: 4604 mov r4, r0 8000760: 480e ldr r0, [pc, #56] @ (800079c ) 8000762: f006 fd25 bl 80071b0 osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0); 8000766: 4a0e ldr r2, [pc, #56] @ (80007a0 ) 8000768: 2300 movs r3, #0 uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 800076a: ea40 0444 orr.w r4, r0, r4, lsl #1 osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0); 800076e: a901 add r1, sp, #4 8000770: 6910 ldr r0, [r2, #16] uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8000772: f004 0403 and.w r4, r4, #3 osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0); 8000776: 461a mov r2, r3 uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8000778: 9401 str r4, [sp, #4] osMessageQueuePut(encoderYTaskArg.dataQueue, &pinStates, 0, 0); 800077a: f00b fbc5 bl 800bf08 } 800077e: b002 add sp, #8 8000780: bd10 pop {r4, pc} uint32_t pinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8000782: f44f 4100 mov.w r1, #32768 @ 0x8000 8000786: 4807 ldr r0, [pc, #28] @ (80007a4 ) 8000788: f006 fd12 bl 80071b0 800078c: f44f 4180 mov.w r1, #16384 @ 0x4000 8000790: 4604 mov r4, r0 8000792: 4804 ldr r0, [pc, #16] @ (80007a4 ) 8000794: f006 fd0c bl 80071b0 osMessageQueuePut(encoderXTaskArg.dataQueue, &pinStates, 0, 0); 8000798: 4a03 ldr r2, [pc, #12] @ (80007a8 ) 800079a: e7e5 b.n 8000768 800079c: 58020400 .word 0x58020400 80007a0: 240008c0 .word 0x240008c0 80007a4: 58020c00 .word 0x58020c00 80007a8: 240008e0 .word 0x240008e0 080007ac : void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 80007ac: 4a0c ldr r2, [pc, #48] @ (80007e0 ) 80007ae: 6803 ldr r3, [r0, #0] 80007b0: 4293 cmp r3, r2 80007b2: d012 beq.n 80007da HAL_IncTick(); } /* USER CODE BEGIN Callback 1 */ else if (htim->Instance == TIM4) 80007b4: 4a0b ldr r2, [pc, #44] @ (80007e4 ) 80007b6: 4293 cmp r3, r2 80007b8: d003 beq.n 80007c2 { encoderXChannelA = 0; encoderXChannelB = 0; } else if (htim->Instance == TIM2) 80007ba: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80007be: d006 beq.n 80007ce { encoderYChannelA = 0; encoderYChannelB = 0; } /* USER CODE END Callback 1 */ } 80007c0: 4770 bx lr encoderXChannelA = 0; 80007c2: 2300 movs r3, #0 80007c4: 4908 ldr r1, [pc, #32] @ (80007e8 ) encoderXChannelB = 0; 80007c6: 4a09 ldr r2, [pc, #36] @ (80007ec ) encoderXChannelA = 0; 80007c8: 600b str r3, [r1, #0] encoderXChannelB = 0; 80007ca: 6013 str r3, [r2, #0] 80007cc: 4770 bx lr encoderYChannelA = 0; 80007ce: 2300 movs r3, #0 80007d0: 4907 ldr r1, [pc, #28] @ (80007f0 ) encoderYChannelB = 0; 80007d2: 4a08 ldr r2, [pc, #32] @ (80007f4 ) encoderYChannelA = 0; 80007d4: 600b str r3, [r1, #0] encoderYChannelB = 0; 80007d6: 6013 str r3, [r2, #0] } 80007d8: 4770 bx lr HAL_IncTick(); 80007da: f003 bbed b.w 8003fb8 80007de: bf00 nop 80007e0: 40001000 .word 0x40001000 80007e4: 40000800 .word 0x40000800 80007e8: 2400028c .word 0x2400028c 80007ec: 24000288 .word 0x24000288 80007f0: 24000284 .word 0x24000284 80007f4: 24000280 .word 0x24000280 080007f8 : \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80007f8: b672 cpsid i \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 80007fa: f3bf 8f4f dsb sy (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 80007fe: 4905 ldr r1, [pc, #20] @ (8000814 ) SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000800: 4b05 ldr r3, [pc, #20] @ (8000818 ) (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8000802: 68ca ldr r2, [r1, #12] 8000804: f402 62e0 and.w r2, r2, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000808: 4313 orrs r3, r2 800080a: 60cb str r3, [r1, #12] 800080c: f3bf 8f4f dsb sy __NOP(); 8000810: bf00 nop for(;;) /* wait until reset */ 8000812: e7fd b.n 8000810 8000814: e000ed00 .word 0xe000ed00 8000818: 05fa0004 .word 0x05fa0004 0800081c : { 800081c: b530 push {r4, r5, lr} 800081e: b09f sub sp, #124 @ 0x7c RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000820: 224c movs r2, #76 @ 0x4c 8000822: 2100 movs r1, #0 8000824: a80a add r0, sp, #40 @ 0x28 8000826: f00f f96f bl 800fb08 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 800082a: 2220 movs r2, #32 800082c: 2100 movs r1, #0 800082e: a802 add r0, sp, #8 8000830: f00f f96a bl 800fb08 HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000834: 2002 movs r0, #2 8000836: f006 fd65 bl 8007304 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 800083a: 4b25 ldr r3, [pc, #148] @ (80008d0 ) 800083c: 2100 movs r1, #0 800083e: 4a25 ldr r2, [pc, #148] @ (80008d4 ) 8000840: 9101 str r1, [sp, #4] 8000842: 6ad9 ldr r1, [r3, #44] @ 0x2c 8000844: f021 0101 bic.w r1, r1, #1 8000848: 62d9 str r1, [r3, #44] @ 0x2c 800084a: 6adb ldr r3, [r3, #44] @ 0x2c 800084c: f003 0301 and.w r3, r3, #1 8000850: 9301 str r3, [sp, #4] 8000852: 6993 ldr r3, [r2, #24] 8000854: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8000858: 6193 str r3, [r2, #24] 800085a: 6993 ldr r3, [r2, #24] 800085c: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000860: 9301 str r3, [sp, #4] 8000862: 9b01 ldr r3, [sp, #4] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000864: 6993 ldr r3, [r2, #24] 8000866: 049b lsls r3, r3, #18 8000868: d5fc bpl.n 8000864 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 800086a: 2201 movs r2, #1 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI 800086c: 2029 movs r0, #41 @ 0x29 800086e: f44f 3180 mov.w r1, #65536 @ 0x10000 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000872: 2402 movs r4, #2 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000874: 2300 movs r3, #0 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 8000876: 2508 movs r5, #8 RCC_OscInitStruct.PLL.PLLP = 2; 8000878: 9417 str r4, [sp, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 800087a: 951a str r5, [sp, #104] @ 0x68 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 800087c: e9cd 220f strd r2, r2, [sp, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLM = 5; 8000880: 2205 movs r2, #5 8000882: 9215 str r2, [sp, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLN = 160; 8000884: 22a0 movs r2, #160 @ 0xa0 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI 8000886: e9cd 010a strd r0, r1, [sp, #40] @ 0x28 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800088a: a80a add r0, sp, #40 @ 0x28 RCC_OscInitStruct.PLL.PLLN = 160; 800088c: 9216 str r2, [sp, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 800088e: e9cd 331b strd r3, r3, [sp, #108] @ 0x6c RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000892: e9cd 4413 strd r4, r4, [sp, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLR = 2; 8000896: e9cd 4418 strd r4, r4, [sp, #96] @ 0x60 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800089a: f006 fe17 bl 80074cc 800089e: 4603 mov r3, r0 80008a0: b998 cbnz r0, 80008ca RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80008a2: 223f movs r2, #63 @ 0x3f RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80008a4: 9304 str r3, [sp, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 80008a6: 2340 movs r3, #64 @ 0x40 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80008a8: 4621 mov r1, r4 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80008aa: 9202 str r2, [sp, #8] RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80008ac: 2203 movs r2, #3 RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 80008ae: 9307 str r3, [sp, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80008b0: a802 add r0, sp, #8 RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 80008b2: 9309 str r3, [sp, #36] @ 0x24 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80008b4: 9203 str r2, [sp, #12] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 80008b6: e9cd 5305 strd r5, r3, [sp, #20] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 80008ba: f44f 6380 mov.w r3, #1024 @ 0x400 80008be: 9308 str r3, [sp, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 80008c0: f007 f984 bl 8007bcc 80008c4: b908 cbnz r0, 80008ca } 80008c6: b01f add sp, #124 @ 0x7c 80008c8: bd30 pop {r4, r5, pc} Error_Handler(); 80008ca: f7ff ff95 bl 80007f8 80008ce: bf00 nop 80008d0: 58000400 .word 0x58000400 80008d4: 58024800 .word 0x58024800 080008d8 : { 80008d8: b510 push {r4, lr} 80008da: b0b0 sub sp, #192 @ 0xc0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80008dc: 22a0 movs r2, #160 @ 0xa0 80008de: 2100 movs r1, #0 PeriphClkInitStruct.PLL2.PLL2P = 25; 80008e0: 2419 movs r4, #25 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80008e2: a808 add r0, sp, #32 80008e4: f00f f910 bl 800fb08 PeriphClkInitStruct.PLL2.PLL2M = 5; 80008e8: 2305 movs r3, #5 PeriphClkInitStruct.PLL2.PLL2N = 90; 80008ea: 205a movs r0, #90 @ 0x5a PeriphClkInitStruct.PLL2.PLL2Q = 3; 80008ec: 2103 movs r1, #3 PeriphClkInitStruct.PLL2.PLL2R = 2; 80008ee: 2202 movs r2, #2 PeriphClkInitStruct.PLL2.PLL2M = 5; 80008f0: 9302 str r3, [sp, #8] PeriphClkInitStruct.PLL2.PLL2R = 2; 80008f2: 2380 movs r3, #128 @ 0x80 PeriphClkInitStruct.PLL2.PLL2N = 90; 80008f4: 9003 str r0, [sp, #12] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80008f6: 4668 mov r0, sp PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80008f8: ed9f 7b07 vldr d7, [pc, #28] @ 8000918 PeriphClkInitStruct.PLL2.PLL2Q = 3; 80008fc: e9cd 4104 strd r4, r1, [sp, #16] PeriphClkInitStruct.PLL2.PLL2R = 2; 8000900: e9cd 2306 strd r2, r3, [sp, #24] PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8000904: ed8d 7b00 vstr d7, [sp] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000908: f007 fc6a bl 80081e0 800090c: b908 cbnz r0, 8000912 } 800090e: b030 add sp, #192 @ 0xc0 8000910: bd10 pop {r4, pc} Error_Handler(); 8000912: f7ff ff71 bl 80007f8 8000916: bf00 nop 8000918: 00080000 .word 0x00080000 800091c: 00000000 .word 0x00000000 08000920
: { 8000920: e92d 4880 stmdb sp!, {r7, fp, lr} MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8000924: 2400 movs r4, #0 { 8000926: b0cf sub sp, #316 @ 0x13c MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8000928: 2501 movs r5, #1 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 800092a: e9cd 4443 strd r4, r4, [sp, #268] @ 0x10c 800092e: e9cd 4445 strd r4, r4, [sp, #276] @ 0x114 HAL_MPU_Disable(); 8000932: f004 fb4b bl 8004fcc MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8000936: f248 721f movw r2, #34591 @ 0x871f 800093a: f240 1301 movw r3, #257 @ 0x101 HAL_MPU_ConfigRegion(&MPU_InitStruct); 800093e: a843 add r0, sp, #268 @ 0x10c MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8000940: f8ad 510c strh.w r5, [sp, #268] @ 0x10c MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8000944: 9346 str r3, [sp, #280] @ 0x118 8000946: e9cd 4244 strd r4, r2, [sp, #272] @ 0x110 HAL_MPU_ConfigRegion(&MPU_InitStruct); 800094a: f004 fb5d bl 8005008 MPU_InitStruct.BaseAddress = 0x24020000; 800094e: 4acd ldr r2, [pc, #820] @ (8000c84 ) MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8000950: 4bcd ldr r3, [pc, #820] @ (8000c88 ) HAL_MPU_ConfigRegion(&MPU_InitStruct); 8000952: a843 add r0, sp, #268 @ 0x10c MPU_InitStruct.BaseAddress = 0x24020000; 8000954: 9244 str r2, [sp, #272] @ 0x110 MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8000956: 9345 str r3, [sp, #276] @ 0x114 MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8000958: f88d 510d strb.w r5, [sp, #269] @ 0x10d MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 800095c: f88d 4119 strb.w r4, [sp, #281] @ 0x119 HAL_MPU_ConfigRegion(&MPU_InitStruct); 8000960: f004 fb52 bl 8005008 MPU_InitStruct.BaseAddress = 0x24040000; 8000964: 4bc9 ldr r3, [pc, #804] @ (8000c8c ) MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8000966: 2202 movs r2, #2 HAL_MPU_ConfigRegion(&MPU_InitStruct); 8000968: a843 add r0, sp, #268 @ 0x10c MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 800096a: f88d 4116 strb.w r4, [sp, #278] @ 0x116 MPU_InitStruct.BaseAddress = 0x24040000; 800096e: 9344 str r3, [sp, #272] @ 0x110 MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8000970: 2308 movs r3, #8 MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8000972: f88d 210d strb.w r2, [sp, #269] @ 0x10d MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8000976: f88d 3114 strb.w r3, [sp, #276] @ 0x114 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 800097a: f88d 5119 strb.w r5, [sp, #281] @ 0x119 MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 800097e: f88d 511b strb.w r5, [sp, #283] @ 0x11b HAL_MPU_ConfigRegion(&MPU_InitStruct); 8000982: f004 fb41 bl 8005008 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8000986: 2004 movs r0, #4 8000988: f004 fb2e bl 8004fe8 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 800098c: 4ac0 ldr r2, [pc, #768] @ (8000c90 ) 800098e: 6953 ldr r3, [r2, #20] 8000990: f413 3300 ands.w r3, r3, #131072 @ 0x20000 8000994: d111 bne.n 80009ba 8000996: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 800099a: f3bf 8f6f isb sy SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 800099e: f8c2 3250 str.w r3, [r2, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 80009a2: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 80009a6: f3bf 8f6f isb sy SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 80009aa: 6953 ldr r3, [r2, #20] 80009ac: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80009b0: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 80009b2: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 80009b6: f3bf 8f6f isb sy if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80009ba: 48b5 ldr r0, [pc, #724] @ (8000c90 ) 80009bc: 6943 ldr r3, [r0, #20] 80009be: f413 3380 ands.w r3, r3, #65536 @ 0x10000 80009c2: d126 bne.n 8000a12 SCB->CSSELR = 0U; /* select Level 1 data cache */ 80009c4: f8c0 3084 str.w r3, [r0, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 80009c8: f3bf 8f4f dsb sy ccsidr = SCB->CCSIDR; 80009cc: f8d0 4080 ldr.w r4, [r0, #128] @ 0x80 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80009d0: f643 75e0 movw r5, #16352 @ 0x3fe0 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 80009d4: f3c4 3c4e ubfx ip, r4, #13, #15 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 80009d8: f3c4 04c9 ubfx r4, r4, #3, #10 80009dc: ea4f 1c4c mov.w ip, ip, lsl #5 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80009e0: ea0c 0105 and.w r1, ip, r5 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 80009e4: 4623 mov r3, r4 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80009e6: ea41 7283 orr.w r2, r1, r3, lsl #30 } while (ways-- != 0U); 80009ea: 3b01 subs r3, #1 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80009ec: f8c0 2260 str.w r2, [r0, #608] @ 0x260 } while (ways-- != 0U); 80009f0: 1c5a adds r2, r3, #1 80009f2: d1f8 bne.n 80009e6 } while(sets-- != 0U); 80009f4: f1ac 0c20 sub.w ip, ip, #32 80009f8: f11c 0f20 cmn.w ip, #32 80009fc: d1f0 bne.n 80009e0 80009fe: f3bf 8f4f dsb sy SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 8000a02: 6943 ldr r3, [r0, #20] 8000a04: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000a08: 6143 str r3, [r0, #20] 8000a0a: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 8000a0e: f3bf 8f6f isb sy __HAL_RCC_GPIOH_CLK_ENABLE(); 8000a12: 4ca0 ldr r4, [pc, #640] @ (8000c94 ) GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000a14: 2500 movs r5, #0 HAL_Init(); 8000a16: f003 fa9f bl 8003f58 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000a1a: 2601 movs r6, #1 SystemClock_Config(); 8000a1c: f7ff fefe bl 800081c GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8000a20: f44f 1744 mov.w r7, #3211264 @ 0x310000 PeriphCommonClock_Config(); 8000a24: f7ff ff58 bl 80008d8 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000a28: 9547 str r5, [sp, #284] @ 0x11c HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8000a2a: 462a mov r2, r5 8000a2c: f24e 7180 movw r1, #59264 @ 0xe780 8000a30: 4899 ldr r0, [pc, #612] @ (8000c98 ) GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000a32: e9cd 5543 strd r5, r5, [sp, #268] @ 0x10c 8000a36: e9cd 5545 strd r5, r5, [sp, #276] @ 0x114 __HAL_RCC_GPIOH_CLK_ENABLE(); 8000a3a: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a3e: f043 0380 orr.w r3, r3, #128 @ 0x80 8000a42: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 8000a46: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a4a: f003 0380 and.w r3, r3, #128 @ 0x80 8000a4e: 9301 str r3, [sp, #4] 8000a50: 9b01 ldr r3, [sp, #4] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000a52: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a56: f043 0304 orr.w r3, r3, #4 8000a5a: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 8000a5e: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a62: f003 0304 and.w r3, r3, #4 8000a66: 9302 str r3, [sp, #8] 8000a68: 9b02 ldr r3, [sp, #8] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000a6a: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a6e: f043 0301 orr.w r3, r3, #1 8000a72: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 8000a76: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a7a: f003 0301 and.w r3, r3, #1 8000a7e: 9303 str r3, [sp, #12] 8000a80: 9b03 ldr r3, [sp, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000a82: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a86: f043 0302 orr.w r3, r3, #2 8000a8a: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 8000a8e: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a92: f003 0302 and.w r3, r3, #2 8000a96: 9304 str r3, [sp, #16] 8000a98: 9b04 ldr r3, [sp, #16] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000a9a: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000a9e: f043 0310 orr.w r3, r3, #16 8000aa2: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 8000aa6: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000aaa: f003 0310 and.w r3, r3, #16 8000aae: 9305 str r3, [sp, #20] 8000ab0: 9b05 ldr r3, [sp, #20] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000ab2: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000ab6: f043 0308 orr.w r3, r3, #8 8000aba: f8c4 30e0 str.w r3, [r4, #224] @ 0xe0 8000abe: f8d4 30e0 ldr.w r3, [r4, #224] @ 0xe0 8000ac2: f003 0308 and.w r3, r3, #8 8000ac6: 9306 str r3, [sp, #24] 8000ac8: 9b06 ldr r3, [sp, #24] HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8000aca: f006 fb77 bl 80071bc HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 8000ace: 462a mov r2, r5 8000ad0: 21f0 movs r1, #240 @ 0xf0 8000ad2: 4872 ldr r0, [pc, #456] @ (8000c9c ) 8000ad4: f006 fb72 bl 80071bc GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8000ad8: f24e 7380 movw r3, #59264 @ 0xe780 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000adc: a943 add r1, sp, #268 @ 0x10c 8000ade: 486e ldr r0, [pc, #440] @ (8000c98 ) GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8000ae0: 9343 str r3, [sp, #268] @ 0x10c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000ae2: 9546 str r5, [sp, #280] @ 0x118 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000ae4: e9cd 6544 strd r6, r5, [sp, #272] @ 0x110 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000ae8: f006 fa20 bl 8006f2c GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 8000aec: f44f 6340 mov.w r3, #3072 @ 0xc00 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000af0: a943 add r1, sp, #268 @ 0x10c 8000af2: 486b ldr r0, [pc, #428] @ (8000ca0 ) GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 8000af4: 9343 str r3, [sp, #268] @ 0x10c GPIO_InitStruct.Pull = GPIO_NOPULL; 8000af6: 9545 str r5, [sp, #276] @ 0x114 GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8000af8: 9744 str r7, [sp, #272] @ 0x110 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000afa: f006 fa17 bl 8006f2c GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 8000afe: f643 7308 movw r3, #16136 @ 0x3f08 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000b02: a943 add r1, sp, #268 @ 0x10c 8000b04: 4865 ldr r0, [pc, #404] @ (8000c9c ) GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 8000b06: 9343 str r3, [sp, #268] @ 0x10c GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b08: e9cd 5544 strd r5, r5, [sp, #272] @ 0x110 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000b0c: f006 fa0e bl 8006f2c GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8000b10: f44f 4340 mov.w r3, #49152 @ 0xc000 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000b14: a943 add r1, sp, #268 @ 0x10c 8000b16: 4861 ldr r0, [pc, #388] @ (8000c9c ) GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8000b18: 9343 str r3, [sp, #268] @ 0x10c GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8000b1a: 9744 str r7, [sp, #272] @ 0x110 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b1c: 9545 str r5, [sp, #276] @ 0x114 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000b1e: f006 fa05 bl 8006f2c GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 8000b22: 23f0 movs r3, #240 @ 0xf0 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000b24: a943 add r1, sp, #268 @ 0x10c 8000b26: 485d ldr r0, [pc, #372] @ (8000c9c ) GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 8000b28: 9343 str r3, [sp, #268] @ 0x10c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000b2a: 9546 str r5, [sp, #280] @ 0x118 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b2c: e9cd 6544 strd r6, r5, [sp, #272] @ 0x110 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000b30: f006 f9fc bl 8006f2c HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 8000b34: 462a mov r2, r5 8000b36: 2105 movs r1, #5 8000b38: 2028 movs r0, #40 @ 0x28 8000b3a: f004 f9fd bl 8004f38 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8000b3e: 2028 movs r0, #40 @ 0x28 8000b40: f004 fa36 bl 8004fb0 __HAL_RCC_DMA1_CLK_ENABLE(); 8000b44: f8d4 30d8 ldr.w r3, [r4, #216] @ 0xd8 HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8000b48: 462a mov r2, r5 8000b4a: 2105 movs r1, #5 __HAL_RCC_DMA1_CLK_ENABLE(); 8000b4c: 4333 orrs r3, r6 HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8000b4e: 200b movs r0, #11 __HAL_RCC_DMA1_CLK_ENABLE(); 8000b50: f8c4 30d8 str.w r3, [r4, #216] @ 0xd8 8000b54: f8d4 30d8 ldr.w r3, [r4, #216] @ 0xd8 8000b58: 4033 ands r3, r6 8000b5a: 9300 str r3, [sp, #0] 8000b5c: 9b00 ldr r3, [sp, #0] HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8000b5e: f004 f9eb bl 8004f38 HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8000b62: 200b movs r0, #11 8000b64: f004 fa24 bl 8004fb0 HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 8000b68: 462a mov r2, r5 8000b6a: 2105 movs r1, #5 8000b6c: 200c movs r0, #12 8000b6e: f004 f9e3 bl 8004f38 HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 8000b72: 200c movs r0, #12 8000b74: f004 fa1c bl 8004fb0 HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 8000b78: 462a mov r2, r5 8000b7a: 2105 movs r1, #5 8000b7c: 200d movs r0, #13 8000b7e: f004 f9db bl 8004f38 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8000b82: 200d movs r0, #13 8000b84: f004 fa14 bl 8004fb0 hrng.Instance = RNG; 8000b88: 4846 ldr r0, [pc, #280] @ (8000ca4 ) 8000b8a: 4b47 ldr r3, [pc, #284] @ (8000ca8 ) 8000b8c: e9c0 3500 strd r3, r5, [r0] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000b90: f008 fe1c bl 80097cc 8000b94: 2800 cmp r0, #0 8000b96: f040 8399 bne.w 80012cc huart1.Instance = USART1; 8000b9a: 4c44 ldr r4, [pc, #272] @ (8000cac ) huart1.Init.Mode = UART_MODE_TX_RX; 8000b9c: 250c movs r5, #12 huart1.Instance = USART1; 8000b9e: 4b44 ldr r3, [pc, #272] @ (8000cb0 ) huart1.Init.WordLength = UART_WORDLENGTH_8B; 8000ba0: 60a0 str r0, [r4, #8] huart1.Instance = USART1; 8000ba2: 6023 str r3, [r4, #0] huart1.Init.BaudRate = 115200; 8000ba4: f44f 33e1 mov.w r3, #115200 @ 0x1c200 huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000ba8: 61a0 str r0, [r4, #24] huart1.Init.BaudRate = 115200; 8000baa: 6063 str r3, [r4, #4] huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 8000bac: f44f 3300 mov.w r3, #131072 @ 0x20000 huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000bb0: 6260 str r0, [r4, #36] @ 0x24 huart1.Init.Mode = UART_MODE_TX_RX; 8000bb2: 6165 str r5, [r4, #20] huart1.Init.Parity = UART_PARITY_NONE; 8000bb4: e9c4 0003 strd r0, r0, [r4, #12] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000bb8: e9c4 0007 strd r0, r0, [r4, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8000bbc: 4620 mov r0, r4 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 8000bbe: e9c4 630a strd r6, r3, [r4, #40] @ 0x28 if (HAL_UART_Init(&huart1) != HAL_OK) 8000bc2: f00a fe31 bl 800b828 8000bc6: 4601 mov r1, r0 8000bc8: 2800 cmp r0, #0 8000bca: f040 837f bne.w 80012cc if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000bce: 4620 mov r0, r4 8000bd0: f00a ff20 bl 800ba14 8000bd4: 4601 mov r1, r0 8000bd6: 2800 cmp r0, #0 8000bd8: f040 8378 bne.w 80012cc if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000bdc: 4620 mov r0, r4 8000bde: f00a ff5b bl 800ba98 8000be2: 2800 cmp r0, #0 8000be4: f040 8372 bne.w 80012cc if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 8000be8: 4620 mov r0, r4 8000bea: f00a fef5 bl 800b9d8 8000bee: 2800 cmp r0, #0 8000bf0: f040 836c bne.w 80012cc hadc1.Instance = ADC1; 8000bf4: 4c2f ldr r4, [pc, #188] @ (8000cb4 ) hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000bf6: f44f 6b9c mov.w fp, #1248 @ 0x4e0 hadc1.Instance = ADC1; 8000bfa: 4b2f ldr r3, [pc, #188] @ (8000cb8 ) ADC_MultiModeTypeDef multimode = {0}; 8000bfc: 9010 str r0, [sp, #64] @ 0x40 hadc1.Instance = ADC1; 8000bfe: 6023 str r3, [r4, #0] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000c00: 2308 movs r3, #8 ADC_ChannelConfTypeDef sConfig = {0}; 8000c02: 9033 str r0, [sp, #204] @ 0xcc hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000c04: 6123 str r3, [r4, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 8000c06: f44f 7380 mov.w r3, #256 @ 0x100 hadc1.Init.DiscontinuousConvMode = DISABLE; 8000c0a: 7720 strb r0, [r4, #28] hadc1.Init.LowPowerAutoWait = DISABLE; 8000c0c: 82a3 strh r3, [r4, #20] hadc1.Init.NbrOfConversion = 7; 8000c0e: 2307 movs r3, #7 hadc1.Init.OversamplingMode = DISABLE; 8000c10: f884 0038 strb.w r0, [r4, #56] @ 0x38 hadc1.Init.NbrOfConversion = 7; 8000c14: 61a3 str r3, [r4, #24] hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000c16: f44f 6380 mov.w r3, #1024 @ 0x400 hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000c1a: 60e6 str r6, [r4, #12] hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000c1c: 62e6 str r6, [r4, #44] @ 0x2c ADC_MultiModeTypeDef multimode = {0}; 8000c1e: e9cd 0011 strd r0, r0, [sp, #68] @ 0x44 ADC_ChannelConfTypeDef sConfig = {0}; 8000c22: e9cd 0034 strd r0, r0, [sp, #208] @ 0xd0 8000c26: e9cd 0036 strd r0, r0, [sp, #216] @ 0xd8 8000c2a: e9cd 0038 strd r0, r0, [sp, #224] @ 0xe0 hadc1.Init.Resolution = ADC_RESOLUTION_16B; 8000c2e: e9c4 0001 strd r0, r0, [r4, #4] hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000c32: e9c4 000c strd r0, r0, [r4, #48] @ 0x30 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000c36: 4620 mov r0, r4 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000c38: e9c4 b309 strd fp, r3, [r4, #36] @ 0x24 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000c3c: f003 fe32 bl 80048a4 8000c40: 2800 cmp r0, #0 8000c42: f040 8343 bne.w 80012cc multimode.DualModeData = ADC_DUALMODEDATAFORMAT_32_10_BITS; 8000c46: 2606 movs r6, #6 8000c48: f44f 4300 mov.w r3, #32768 @ 0x8000 multimode.TwoSamplingDelay = ADC_TWOSAMPLINGDELAY_1CYCLE; 8000c4c: 9012 str r0, [sp, #72] @ 0x48 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000c4e: a910 add r1, sp, #64 @ 0x40 8000c50: 4620 mov r0, r4 multimode.DualModeData = ADC_DUALMODEDATAFORMAT_32_10_BITS; 8000c52: e9cd 6310 strd r6, r3, [sp, #64] @ 0x40 if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000c56: f004 f803 bl 8004c60 8000c5a: 2800 cmp r0, #0 8000c5c: f040 8336 bne.w 80012cc sConfig.Channel = ADC_CHANNEL_8; 8000c60: 4b16 ldr r3, [pc, #88] @ (8000cbc ) sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000c62: f240 78ff movw r8, #2047 @ 0x7ff sConfig.Offset = 0; 8000c66: 9038 str r0, [sp, #224] @ 0xe0 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c68: a933 add r1, sp, #204 @ 0xcc sConfig.Channel = ADC_CHANNEL_8; 8000c6a: 9333 str r3, [sp, #204] @ 0xcc sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000c6c: 2304 movs r3, #4 sConfig.OffsetSignedSaturation = DISABLE; 8000c6e: f88d 00e5 strb.w r0, [sp, #229] @ 0xe5 sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8000c72: e9cd 6034 strd r6, r0, [sp, #208] @ 0xd0 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c76: 4620 mov r0, r4 sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000c78: e9cd 8336 strd r8, r3, [sp, #216] @ 0xd8 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000c7c: f003 fa1e bl 80040bc 8000c80: e01e b.n 8000cc0 8000c82: bf00 nop 8000c84: 24020000 .word 0x24020000 8000c88: 03010010 .word 0x03010010 8000c8c: 24040000 .word 0x24040000 8000c90: e000ed00 .word 0xe000ed00 8000c94: 58024400 .word 0x58024400 8000c98: 58021000 .word 0x58021000 8000c9c: 58020c00 .word 0x58020c00 8000ca0: 58020400 .word 0x58020400 8000ca4: 24000598 .word 0x24000598 8000ca8: 48021800 .word 0x48021800 8000cac: 2400038c .word 0x2400038c 8000cb0: 40011000 .word 0x40011000 8000cb4: 24000850 .word 0x24000850 8000cb8: 40022000 .word 0x40022000 8000cbc: 21800100 .word 0x21800100 8000cc0: 2800 cmp r0, #0 8000cc2: f040 8303 bne.w 80012cc sConfig.Channel = ADC_CHANNEL_9; 8000cc6: 4bcc ldr r3, [pc, #816] @ (8000ff8 ) if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cc8: a933 add r1, sp, #204 @ 0xcc 8000cca: 4620 mov r0, r4 sConfig.Rank = ADC_REGULAR_RANK_2; 8000ccc: 9534 str r5, [sp, #208] @ 0xd0 sConfig.Channel = ADC_CHANNEL_9; 8000cce: 9333 str r3, [sp, #204] @ 0xcc if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cd0: f003 f9f4 bl 80040bc 8000cd4: 2800 cmp r0, #0 8000cd6: f040 82f9 bne.w 80012cc sConfig.Channel = ADC_CHANNEL_7; 8000cda: 4ac8 ldr r2, [pc, #800] @ (8000ffc ) sConfig.Rank = ADC_REGULAR_RANK_3; 8000cdc: 2312 movs r3, #18 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cde: 4620 mov r0, r4 8000ce0: a933 add r1, sp, #204 @ 0xcc sConfig.Rank = ADC_REGULAR_RANK_3; 8000ce2: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ce6: f003 f9e9 bl 80040bc 8000cea: 2800 cmp r0, #0 8000cec: f040 82ee bne.w 80012cc sConfig.Channel = ADC_CHANNEL_16; 8000cf0: 4ac3 ldr r2, [pc, #780] @ (8001000 ) sConfig.Rank = ADC_REGULAR_RANK_4; 8000cf2: 2318 movs r3, #24 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cf4: a933 add r1, sp, #204 @ 0xcc 8000cf6: 4620 mov r0, r4 sConfig.Rank = ADC_REGULAR_RANK_4; 8000cf8: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000cfc: f003 f9de bl 80040bc 8000d00: 2800 cmp r0, #0 8000d02: f040 82e3 bne.w 80012cc sConfig.Channel = ADC_CHANNEL_17; 8000d06: 4abf ldr r2, [pc, #764] @ (8001004 ) sConfig.Rank = ADC_REGULAR_RANK_5; 8000d08: f44f 7380 mov.w r3, #256 @ 0x100 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000d0c: a933 add r1, sp, #204 @ 0xcc 8000d0e: 4620 mov r0, r4 sConfig.Rank = ADC_REGULAR_RANK_5; 8000d10: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000d14: f003 f9d2 bl 80040bc 8000d18: 2800 cmp r0, #0 8000d1a: f040 82d7 bne.w 80012cc sConfig.Channel = ADC_CHANNEL_14; 8000d1e: 4aba ldr r2, [pc, #744] @ (8001008 ) sConfig.Rank = ADC_REGULAR_RANK_6; 8000d20: f44f 7383 mov.w r3, #262 @ 0x106 if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000d24: a933 add r1, sp, #204 @ 0xcc 8000d26: 4620 mov r0, r4 sConfig.Rank = ADC_REGULAR_RANK_6; 8000d28: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000d2c: f003 f9c6 bl 80040bc 8000d30: 2800 cmp r0, #0 8000d32: f040 82cb bne.w 80012cc sConfig.Channel = ADC_CHANNEL_15; 8000d36: 4ab5 ldr r2, [pc, #724] @ (800100c ) sConfig.Rank = ADC_REGULAR_RANK_7; 8000d38: f44f 7386 mov.w r3, #268 @ 0x10c if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000d3c: a933 add r1, sp, #204 @ 0xcc 8000d3e: 4620 mov r0, r4 sConfig.Rank = ADC_REGULAR_RANK_7; 8000d40: e9cd 2333 strd r2, r3, [sp, #204] @ 0xcc if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000d44: f003 f9ba bl 80040bc 8000d48: 2800 cmp r0, #0 8000d4a: f040 82bf bne.w 80012cc if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000d4e: f240 72ff movw r2, #2047 @ 0x7ff 8000d52: f04f 1101 mov.w r1, #65537 @ 0x10001 8000d56: 4620 mov r0, r4 8000d58: f003 feb0 bl 8004abc 8000d5c: 4603 mov r3, r0 8000d5e: 2800 cmp r0, #0 8000d60: f040 82b4 bne.w 80012cc huart8.Instance = UART8; 8000d64: 4caa ldr r4, [pc, #680] @ (8001010 ) huart8.Init.BaudRate = 115200; 8000d66: f44f 32e1 mov.w r2, #115200 @ 0x1c200 huart8.Instance = UART8; 8000d6a: 49aa ldr r1, [pc, #680] @ (8001014 ) if (HAL_UART_Init(&huart8) != HAL_OK) 8000d6c: 4620 mov r0, r4 huart8.Init.BaudRate = 115200; 8000d6e: e884 000e stmia.w r4, {r1, r2, r3} huart8.Init.Parity = UART_PARITY_NONE; 8000d72: e9c4 3303 strd r3, r3, [r4, #12] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000d76: e9c4 5305 strd r5, r3, [r4, #20] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8000d7a: e9c4 3307 strd r3, r3, [r4, #28] huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000d7e: e9c4 3309 strd r3, r3, [r4, #36] @ 0x24 if (HAL_UART_Init(&huart8) != HAL_OK) 8000d82: f00a fd51 bl 800b828 8000d86: 4601 mov r1, r0 8000d88: 2800 cmp r0, #0 8000d8a: f040 829f bne.w 80012cc if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000d8e: 4620 mov r0, r4 8000d90: f00a fe40 bl 800ba14 8000d94: 4601 mov r1, r0 8000d96: 2800 cmp r0, #0 8000d98: f040 8298 bne.w 80012cc if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000d9c: 4620 mov r0, r4 8000d9e: f00a fe7b bl 800ba98 8000da2: 2800 cmp r0, #0 8000da4: f040 8292 bne.w 80012cc if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8000da8: 4620 mov r0, r4 8000daa: f00a fe15 bl 800b9d8 8000dae: 4603 mov r3, r0 8000db0: 2800 cmp r0, #0 8000db2: f040 828b bne.w 80012cc hcrc.Instance = CRC; 8000db6: 4898 ldr r0, [pc, #608] @ (8001018 ) hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000db8: 2201 movs r2, #1 hcrc.Instance = CRC; 8000dba: 4998 ldr r1, [pc, #608] @ (800101c ) hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000dbc: 6143 str r3, [r0, #20] hcrc.Instance = CRC; 8000dbe: 6001 str r1, [r0, #0] hcrc.Init.GeneratingPolynomial = 4129; 8000dc0: f241 0121 movw r1, #4129 @ 0x1021 hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000dc4: 6183 str r3, [r0, #24] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000dc6: 2308 movs r3, #8 hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000dc8: 8082 strh r2, [r0, #4] hcrc.Init.GeneratingPolynomial = 4129; 8000dca: 6081 str r1, [r0, #8] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000dcc: 6202 str r2, [r0, #32] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000dce: 60c3 str r3, [r0, #12] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000dd0: f004 f984 bl 80050dc 8000dd4: 2800 cmp r0, #0 8000dd6: f040 8279 bne.w 80012cc ADC_ChannelConfTypeDef sConfig = {0}; 8000dda: 2200 movs r2, #0 hadc2.Instance = ADC2; 8000ddc: f8df 826c ldr.w r8, [pc, #620] @ 800104c hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000de0: 2401 movs r4, #1 hadc2.Instance = ADC2; 8000de2: 498f ldr r1, [pc, #572] @ (8001020 ) hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000de4: f04f 0b08 mov.w fp, #8 hadc2.Init.LowPowerAutoWait = DISABLE; 8000de8: f44f 7a80 mov.w sl, #256 @ 0x100 ADC_ChannelConfTypeDef sConfig = {0}; 8000dec: 922c str r2, [sp, #176] @ 0xb0 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000dee: 4640 mov r0, r8 hadc2.Init.DiscontinuousConvMode = DISABLE; 8000df0: f888 201c strb.w r2, [r8, #28] hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000df4: f8c8 2034 str.w r2, [r8, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000df8: f888 2038 strb.w r2, [r8, #56] @ 0x38 hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000dfc: f8c8 b010 str.w fp, [r8, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000e00: f8a8 a014 strh.w sl, [r8, #20] hadc2.Instance = ADC2; 8000e04: e9c8 1200 strd r1, r2, [r8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000e08: e9c8 2402 strd r2, r4, [r8, #8] hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000e0c: e9c8 420b strd r4, r2, [r8, #44] @ 0x2c ADC_ChannelConfTypeDef sConfig = {0}; 8000e10: e9cd 222d strd r2, r2, [sp, #180] @ 0xb4 8000e14: e9cd 222f strd r2, r2, [sp, #188] @ 0xbc 8000e18: e9cd 2231 strd r2, r2, [sp, #196] @ 0xc4 hadc2.Init.NbrOfConversion = 3; 8000e1c: 2203 movs r2, #3 8000e1e: f8c8 2018 str.w r2, [r8, #24] if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000e22: f003 fd3f bl 80048a4 8000e26: 2800 cmp r0, #0 8000e28: f040 8250 bne.w 80012cc sConfig.Channel = ADC_CHANNEL_3; 8000e2c: 4a7d ldr r2, [pc, #500] @ (8001024 ) sConfig.Rank = ADC_REGULAR_RANK_1; 8000e2e: 4635 mov r5, r6 sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000e30: f04f 0904 mov.w r9, #4 sConfig.Rank = ADC_REGULAR_RANK_1; 8000e34: 962d str r6, [sp, #180] @ 0xb4 sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000e36: f240 76ff movw r6, #2047 @ 0x7ff sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 8000e3a: 902e str r0, [sp, #184] @ 0xb8 sConfig.Offset = 0; 8000e3c: 9031 str r0, [sp, #196] @ 0xc4 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000e3e: a92c add r1, sp, #176 @ 0xb0 sConfig.OffsetSignedSaturation = DISABLE; 8000e40: f88d 00c9 strb.w r0, [sp, #201] @ 0xc9 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000e44: 4640 mov r0, r8 sConfig.Channel = ADC_CHANNEL_3; 8000e46: 922c str r2, [sp, #176] @ 0xb0 sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000e48: e9cd 692f strd r6, r9, [sp, #188] @ 0xbc if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000e4c: f003 f936 bl 80040bc 8000e50: 2800 cmp r0, #0 8000e52: f040 823b bne.w 80012cc sConfig.Rank = ADC_REGULAR_RANK_2; 8000e56: 4a74 ldr r2, [pc, #464] @ (8001028 ) 8000e58: 230c movs r3, #12 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000e5a: a92c add r1, sp, #176 @ 0xb0 8000e5c: 4640 mov r0, r8 sConfig.Rank = ADC_REGULAR_RANK_2; 8000e5e: e9cd 232c strd r2, r3, [sp, #176] @ 0xb0 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000e62: f003 f92b bl 80040bc 8000e66: 2800 cmp r0, #0 8000e68: f040 8230 bne.w 80012cc sConfig.Rank = ADC_REGULAR_RANK_3; 8000e6c: 4a6f ldr r2, [pc, #444] @ (800102c ) 8000e6e: 2712 movs r7, #18 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000e70: a92c add r1, sp, #176 @ 0xb0 8000e72: 4640 mov r0, r8 sConfig.Rank = ADC_REGULAR_RANK_3; 8000e74: e9cd 272c strd r2, r7, [sp, #176] @ 0xb0 if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000e78: f003 f920 bl 80040bc 8000e7c: 2800 cmp r0, #0 8000e7e: f040 8225 bne.w 80012cc if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000e82: 4640 mov r0, r8 8000e84: 4632 mov r2, r6 8000e86: f04f 1101 mov.w r1, #65537 @ 0x10001 8000e8a: f003 fe17 bl 8004abc 8000e8e: 2800 cmp r0, #0 8000e90: f040 821c bne.w 80012cc hadc3.Instance = ADC3; 8000e94: f8df 81b8 ldr.w r8, [pc, #440] @ 8001050 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000e98: f44f 6c9c mov.w ip, #1248 @ 0x4e0 hadc3.Instance = ADC3; 8000e9c: 4a64 ldr r2, [pc, #400] @ (8001030 ) ADC_ChannelConfTypeDef sConfig = {0}; 8000e9e: 902b str r0, [sp, #172] @ 0xac hadc3.Instance = ADC3; 8000ea0: f8c8 2000 str.w r2, [r8] hadc3.Init.NbrOfConversion = 5; 8000ea4: 2205 movs r2, #5 hadc3.Init.DiscontinuousConvMode = DISABLE; 8000ea6: f888 001c strb.w r0, [r8, #28] hadc3.Init.NbrOfConversion = 5; 8000eaa: f8c8 2018 str.w r2, [r8, #24] hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000eae: f44f 6280 mov.w r2, #1024 @ 0x400 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000eb2: f8c8 0034 str.w r0, [r8, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000eb6: f888 0038 strb.w r0, [r8, #56] @ 0x38 hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000eba: f8c8 b010 str.w fp, [r8, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000ebe: f8a8 a014 strh.w sl, [r8, #20] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000ec2: f8c8 400c str.w r4, [r8, #12] ADC_ChannelConfTypeDef sConfig = {0}; 8000ec6: e9cd 0025 strd r0, r0, [sp, #148] @ 0x94 8000eca: e9cd 0027 strd r0, r0, [sp, #156] @ 0x9c 8000ece: e9cd 0029 strd r0, r0, [sp, #164] @ 0xa4 hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000ed2: e9c8 0001 strd r0, r0, [r8, #4] hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000ed6: e9c8 400b strd r4, r0, [r8, #44] @ 0x2c if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000eda: 4640 mov r0, r8 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000edc: e9c8 c209 strd ip, r2, [r8, #36] @ 0x24 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000ee0: f003 fce0 bl 80048a4 8000ee4: 2800 cmp r0, #0 8000ee6: f040 81f1 bne.w 80012cc sConfig.Offset = 0; 8000eea: 902a str r0, [sp, #168] @ 0xa8 if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000eec: a925 add r1, sp, #148 @ 0x94 sConfig.OffsetSignedSaturation = DISABLE; 8000eee: f88d 00ad strb.w r0, [sp, #173] @ 0xad if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ef2: 4640 mov r0, r8 sConfig.Channel = ADC_CHANNEL_0; 8000ef4: 9425 str r4, [sp, #148] @ 0x94 sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000ef6: e9cd 6928 strd r6, r9, [sp, #160] @ 0xa0 sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000efa: e9cd 5526 strd r5, r5, [sp, #152] @ 0x98 if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000efe: f003 f8dd bl 80040bc 8000f02: 2800 cmp r0, #0 8000f04: f040 81e2 bne.w 80012cc sConfig.Rank = ADC_REGULAR_RANK_2; 8000f08: 230c movs r3, #12 sConfig.Channel = ADC_CHANNEL_1; 8000f0a: 4a4a ldr r2, [pc, #296] @ (8001034 ) if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f0c: a925 add r1, sp, #148 @ 0x94 8000f0e: 4640 mov r0, r8 sConfig.Rank = ADC_REGULAR_RANK_2; 8000f10: 9326 str r3, [sp, #152] @ 0x98 sConfig.Channel = ADC_CHANNEL_1; 8000f12: 9225 str r2, [sp, #148] @ 0x94 if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f14: f003 f8d2 bl 80040bc 8000f18: 2800 cmp r0, #0 8000f1a: f040 81d7 bne.w 80012cc sConfig.Channel = ADC_CHANNEL_10; 8000f1e: 4a46 ldr r2, [pc, #280] @ (8001038 ) if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f20: a925 add r1, sp, #148 @ 0x94 8000f22: 4640 mov r0, r8 sConfig.Rank = ADC_REGULAR_RANK_3; 8000f24: 9726 str r7, [sp, #152] @ 0x98 sConfig.Channel = ADC_CHANNEL_10; 8000f26: 9225 str r2, [sp, #148] @ 0x94 if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f28: f003 f8c8 bl 80040bc 8000f2c: 2800 cmp r0, #0 8000f2e: f040 81cd bne.w 80012cc sConfig.Channel = ADC_CHANNEL_11; 8000f32: 4942 ldr r1, [pc, #264] @ (800103c ) sConfig.Rank = ADC_REGULAR_RANK_4; 8000f34: 2218 movs r2, #24 if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f36: 4640 mov r0, r8 sConfig.Rank = ADC_REGULAR_RANK_4; 8000f38: e9cd 1225 strd r1, r2, [sp, #148] @ 0x94 if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f3c: a925 add r1, sp, #148 @ 0x94 8000f3e: f003 f8bd bl 80040bc 8000f42: 2800 cmp r0, #0 8000f44: f040 81c2 bne.w 80012cc sConfig.Channel = ADC_CHANNEL_VREFINT; 8000f48: 4a3d ldr r2, [pc, #244] @ (8001040 ) if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f4a: a925 add r1, sp, #148 @ 0x94 8000f4c: 4640 mov r0, r8 sConfig.Rank = ADC_REGULAR_RANK_5; 8000f4e: e9cd 2a25 strd r2, sl, [sp, #148] @ 0x94 if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000f52: f003 f8b3 bl 80040bc 8000f56: 2800 cmp r0, #0 8000f58: f040 81b8 bne.w 80012cc if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000f5c: 4632 mov r2, r6 8000f5e: f04f 1101 mov.w r1, #65537 @ 0x10001 8000f62: 4640 mov r0, r8 8000f64: f003 fdaa bl 8004abc 8000f68: 4604 mov r4, r0 8000f6a: 2800 cmp r0, #0 8000f6c: f040 81ae bne.w 80012cc htim1.Instance = TIM1; 8000f70: 4e34 ldr r6, [pc, #208] @ (8001044 ) TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000f72: 4601 mov r1, r0 TIM_OC_InitTypeDef sConfigOC = {0}; 8000f74: 901e str r0, [sp, #120] @ 0x78 TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000f76: 222c movs r2, #44 @ 0x2c TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000f78: 900f str r0, [sp, #60] @ 0x3c htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000f7a: f04f 0880 mov.w r8, #128 @ 0x80 htim1.Init.Prescaler = 199; 8000f7e: f04f 0ac7 mov.w sl, #199 @ 0xc7 htim1.Init.Period = 999; 8000f82: f240 39e7 movw r9, #999 @ 0x3e7 TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000f86: e9cd 000d strd r0, r0, [sp, #52] @ 0x34 TIM_OC_InitTypeDef sConfigOC = {0}; 8000f8a: e9cd 001f strd r0, r0, [sp, #124] @ 0x7c 8000f8e: e9cd 0021 strd r0, r0, [sp, #132] @ 0x84 8000f92: e9cd 0023 strd r0, r0, [sp, #140] @ 0x8c TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000f96: a843 add r0, sp, #268 @ 0x10c 8000f98: f00e fdb6 bl 800fb08 htim1.Init.Prescaler = 199; 8000f9c: 4b2a ldr r3, [pc, #168] @ (8001048 ) if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8000f9e: 4630 mov r0, r6 htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000fa0: 60b4 str r4, [r6, #8] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000fa2: f8c6 8018 str.w r8, [r6, #24] htim1.Init.Period = 999; 8000fa6: f8c6 900c str.w r9, [r6, #12] htim1.Init.RepetitionCounter = 0; 8000faa: e9c6 4404 strd r4, r4, [r6, #16] htim1.Init.Prescaler = 199; 8000fae: e9c6 3a00 strd r3, sl, [r6] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8000fb2: f008 fe0b bl 8009bcc 8000fb6: 2800 cmp r0, #0 8000fb8: f040 8188 bne.w 80012cc sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000fbc: 900f str r0, [sp, #60] @ 0x3c if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000fbe: a90d add r1, sp, #52 @ 0x34 sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000fc0: e9cd 000d strd r0, r0, [sp, #52] @ 0x34 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000fc4: 4630 mov r0, r6 8000fc6: f009 fac3 bl 800a550 8000fca: 2800 cmp r0, #0 8000fcc: f040 817e bne.w 80012cc sConfigOC.Pulse = 99; 8000fd0: f04f 0b60 mov.w fp, #96 @ 0x60 8000fd4: 2363 movs r3, #99 @ 0x63 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8000fd6: 9024 str r0, [sp, #144] @ 0x90 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8000fd8: 2204 movs r2, #4 8000fda: a91e add r1, sp, #120 @ 0x78 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8000fdc: e9cd 0020 strd r0, r0, [sp, #128] @ 0x80 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 8000fe0: e9cd 0022 strd r0, r0, [sp, #136] @ 0x88 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8000fe4: 4630 mov r0, r6 sConfigOC.Pulse = 99; 8000fe6: e9cd b31e strd fp, r3, [sp, #120] @ 0x78 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8000fea: f009 f997 bl 800a31c 8000fee: 2800 cmp r0, #0 8000ff0: f040 816c bne.w 80012cc 8000ff4: e02e b.n 8001054 8000ff6: bf00 nop 8000ff8: 25b00200 .word 0x25b00200 8000ffc: 1d500080 .word 0x1d500080 8001000: 43210000 .word 0x43210000 8001004: 47520000 .word 0x47520000 8001008: 3ac04000 .word 0x3ac04000 800100c: 3ef08000 .word 0x3ef08000 8001010: 24000420 .word 0x24000420 8001014: 40007c00 .word 0x40007c00 8001018: 240005d0 .word 0x240005d0 800101c: 58024c00 .word 0x58024c00 8001020: 40022100 .word 0x40022100 8001024: 0c900008 .word 0x0c900008 8001028: 10c00010 .word 0x10c00010 800102c: 14f00020 .word 0x14f00020 8001030: 58026000 .word 0x58026000 8001034: 04300002 .word 0x04300002 8001038: 2a000400 .word 0x2a000400 800103c: 2e300800 .word 0x2e300800 8001040: cfb80000 .word 0xcfb80000 8001044: 2400054c .word 0x2400054c 8001048: 40010000 .word 0x40010000 800104c: 240007ec .word 0x240007ec 8001050: 24000788 .word 0x24000788 sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8001054: f44f 5300 mov.w r3, #8192 @ 0x2000 sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 8001058: 9047 str r0, [sp, #284] @ 0x11c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 800105a: a943 add r1, sp, #268 @ 0x10c sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 800105c: 9348 str r3, [sp, #288] @ 0x120 sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800105e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8001062: e9cd 0043 strd r0, r0, [sp, #268] @ 0x10c sBreakDeadTimeConfig.DeadTime = 0; 8001066: e9cd 0045 strd r0, r0, [sp, #276] @ 0x114 sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 800106a: e9cd 0049 strd r0, r0, [sp, #292] @ 0x124 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 800106e: e9cd 004c strd r0, r0, [sp, #304] @ 0x130 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 8001072: 4630 mov r0, r6 sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 8001074: 934b str r3, [sp, #300] @ 0x12c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 8001076: f009 fac5 bl 800a604 800107a: 4604 mov r4, r0 800107c: 2800 cmp r0, #0 800107e: f040 8125 bne.w 80012cc memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001082: af1e add r7, sp, #120 @ 0x78 8001084: f8df c2b8 ldr.w ip, [pc, #696] @ 8001340 htim3.Instance = TIM3; 8001088: 4d91 ldr r5, [pc, #580] @ (80012d0 ) memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 800108a: cf0f ldmia r7!, {r0, r1, r2, r3} 800108c: e8ac 000f stmia.w ip!, {r0, r1, r2, r3} 8001090: e897 0007 ldmia.w r7, {r0, r1, r2} 8001094: e88c 0007 stmia.w ip, {r0, r1, r2} HAL_TIM_MspPostInit(&htim1); 8001098: 4630 mov r0, r6 800109a: f001 fe51 bl 8002d40 htim3.Instance = TIM3; 800109e: 4b8d ldr r3, [pc, #564] @ (80012d4 ) if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 80010a0: 4628 mov r0, r5 htim3.Init.Prescaler = 199; 80010a2: f8c5 a004 str.w sl, [r5, #4] htim3.Init.Period = 999; 80010a6: f8c5 900c str.w r9, [r5, #12] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80010aa: f8c5 8018 str.w r8, [r5, #24] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010ae: 940c str r4, [sp, #48] @ 0x30 TIM_OC_InitTypeDef sConfigOC = {0}; 80010b0: 941d str r4, [sp, #116] @ 0x74 htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80010b2: 60ac str r4, [r5, #8] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80010b4: 612c str r4, [r5, #16] htim3.Instance = TIM3; 80010b6: 602b str r3, [r5, #0] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010b8: e9cd 440a strd r4, r4, [sp, #40] @ 0x28 TIM_OC_InitTypeDef sConfigOC = {0}; 80010bc: e9cd 4417 strd r4, r4, [sp, #92] @ 0x5c 80010c0: e9cd 4419 strd r4, r4, [sp, #100] @ 0x64 80010c4: e9cd 441b strd r4, r4, [sp, #108] @ 0x6c if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 80010c8: f008 fd80 bl 8009bcc 80010cc: 2800 cmp r0, #0 80010ce: f040 80fd bne.w 80012cc sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80010d2: 900a str r0, [sp, #40] @ 0x28 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80010d4: a90a add r1, sp, #40 @ 0x28 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80010d6: 900c str r0, [sp, #48] @ 0x30 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 80010d8: 4628 mov r0, r5 80010da: f009 fa39 bl 800a550 80010de: 4602 mov r2, r0 80010e0: 2800 cmp r0, #0 80010e2: f040 80f3 bne.w 80012cc sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 80010e6: 4b7c ldr r3, [pc, #496] @ (80012d8 ) if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80010e8: a917 add r1, sp, #92 @ 0x5c sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80010ea: 9019 str r0, [sp, #100] @ 0x64 sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 80010ec: 9317 str r3, [sp, #92] @ 0x5c sConfigOC.Pulse = 500; 80010ee: f44f 73fa mov.w r3, #500 @ 0x1f4 sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80010f2: 901b str r0, [sp, #108] @ 0x6c if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80010f4: 4628 mov r0, r5 sConfigOC.Pulse = 500; 80010f6: 9318 str r3, [sp, #96] @ 0x60 if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80010f8: f009 f910 bl 800a31c 80010fc: 2800 cmp r0, #0 80010fe: f040 80e5 bne.w 80012cc __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 8001102: 6828 ldr r0, [r5, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001104: 2204 movs r2, #4 8001106: a917 add r1, sp, #92 @ 0x5c sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001108: f8cd b05c str.w fp, [sp, #92] @ 0x5c __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 800110c: 6983 ldr r3, [r0, #24] 800110e: f023 0308 bic.w r3, r3, #8 8001112: 6183 str r3, [r0, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001114: 4628 mov r0, r5 8001116: f009 f901 bl 800a31c 800111a: 2800 cmp r0, #0 800111c: f040 80d6 bne.w 80012cc __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 8001120: 6828 ldr r0, [r5, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8001122: 2208 movs r2, #8 8001124: a917 add r1, sp, #92 @ 0x5c __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 8001126: 6983 ldr r3, [r0, #24] 8001128: f423 6300 bic.w r3, r3, #2048 @ 0x800 800112c: 6183 str r3, [r0, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 800112e: 4628 mov r0, r5 8001130: f009 f8f4 bl 800a31c 8001134: 2800 cmp r0, #0 8001136: f040 80c9 bne.w 80012cc __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 800113a: 6828 ldr r0, [r5, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800113c: 220c movs r2, #12 800113e: a917 add r1, sp, #92 @ 0x5c __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 8001140: 69c3 ldr r3, [r0, #28] 8001142: f023 0308 bic.w r3, r3, #8 8001146: 61c3 str r3, [r0, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 8001148: 4628 mov r0, r5 800114a: f009 f8e7 bl 800a31c 800114e: 4607 mov r7, r0 8001150: 2800 cmp r0, #0 8001152: f040 80bb bne.w 80012cc __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 8001156: 682a ldr r2, [r5, #0] memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001158: ac17 add r4, sp, #92 @ 0x5c 800115a: 4d60 ldr r5, [pc, #384] @ (80012dc ) __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 800115c: 69d3 ldr r3, [r2, #28] hdac1.Instance = DAC1; 800115e: 4e60 ldr r6, [pc, #384] @ (80012e0 ) __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 8001160: f423 6300 bic.w r3, r3, #2048 @ 0x800 8001164: 61d3 str r3, [r2, #28] memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001166: cc0f ldmia r4!, {r0, r1, r2, r3} 8001168: c50f stmia r5!, {r0, r1, r2, r3} 800116a: e894 0007 ldmia.w r4, {r0, r1, r2} 800116e: e885 0007 stmia.w r5, {r0, r1, r2} HAL_TIM_MspPostInit(&htim3); 8001172: 4857 ldr r0, [pc, #348] @ (80012d0 ) 8001174: f001 fde4 bl 8002d40 DAC_ChannelConfTypeDef sConfig = {0}; 8001178: 2224 movs r2, #36 @ 0x24 800117a: 4639 mov r1, r7 800117c: a83a add r0, sp, #232 @ 0xe8 800117e: f00e fcc3 bl 800fb08 hdac1.Instance = DAC1; 8001182: 4b58 ldr r3, [pc, #352] @ (80012e4 ) if (HAL_DAC_Init(&hdac1) != HAL_OK) 8001184: 4630 mov r0, r6 hdac1.Instance = DAC1; 8001186: 6033 str r3, [r6, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8001188: f004 f85e bl 8005248 800118c: 4602 mov r2, r0 800118e: 2800 cmp r0, #0 8001190: f040 809c bne.w 80012cc sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8001194: 2301 movs r3, #1 sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 8001196: 903e str r0, [sp, #248] @ 0xf8 if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8001198: a93a add r1, sp, #232 @ 0xe8 sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 800119a: e9cd 003a strd r0, r0, [sp, #232] @ 0xe8 sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 800119e: e9cd 033c strd r0, r3, [sp, #240] @ 0xf0 if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 80011a2: 4630 mov r0, r6 80011a4: f004 f8f0 bl 8005388 80011a8: 2800 cmp r0, #0 80011aa: f040 808f bne.w 80012cc if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 80011ae: 2210 movs r2, #16 80011b0: a93a add r1, sp, #232 @ 0xe8 80011b2: 4630 mov r0, r6 80011b4: f004 f8e8 bl 8005388 80011b8: 4603 mov r3, r0 80011ba: 2800 cmp r0, #0 80011bc: f040 8086 bne.w 80012cc hcomp1.Instance = COMP1; 80011c0: 4849 ldr r0, [pc, #292] @ (80012e8 ) hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 80011c2: f44f 1280 mov.w r2, #1048576 @ 0x100000 hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT; 80011c6: 4949 ldr r1, [pc, #292] @ (80012ec ) hcomp1.Instance = COMP1; 80011c8: 4c49 ldr r4, [pc, #292] @ (80012f0 ) hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 80011ca: 6183 str r3, [r0, #24] hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE; 80011cc: 6143 str r3, [r0, #20] hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 80011ce: 61c3 str r3, [r0, #28] hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 80011d0: 6203 str r3, [r0, #32] hcomp1.Instance = COMP1; 80011d2: 6004 str r4, [r0, #0] hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; 80011d4: e9c0 3301 strd r3, r3, [r0, #4] hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 80011d8: e9c0 2103 strd r2, r1, [r0, #12] if (HAL_COMP_Init(&hcomp1) != HAL_OK) 80011dc: f003 fda2 bl 8004d24 80011e0: 4603 mov r3, r0 80011e2: 2800 cmp r0, #0 80011e4: d172 bne.n 80012cc htim8.Instance = TIM8; 80011e6: 4c43 ldr r4, [pc, #268] @ (80012f4 ) htim8.Init.Period = 1999; 80011e8: f240 72cf movw r2, #1999 @ 0x7cf htim8.Instance = TIM8; 80011ec: 4942 ldr r1, [pc, #264] @ (80012f8 ) TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80011ee: 9013 str r0, [sp, #76] @ 0x4c TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011f0: 9009 str r0, [sp, #36] @ 0x24 htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80011f2: f8c4 8018 str.w r8, [r4, #24] TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80011f6: 9316 str r3, [sp, #88] @ 0x58 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011f8: e9cd 0007 strd r0, r0, [sp, #28] htim8.Init.Prescaler = 0; 80011fc: e9c4 1000 strd r1, r0, [r4] htim8.Init.Period = 1999; 8001200: e9c4 0202 strd r0, r2, [r4, #8] if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 8001204: 4620 mov r0, r4 htim8.Init.RepetitionCounter = 0; 8001206: e9c4 3304 strd r3, r3, [r4, #16] TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800120a: e9cd 3314 strd r3, r3, [sp, #80] @ 0x50 if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 800120e: f008 fb97 bl 8009940 8001212: 2800 cmp r0, #0 8001214: d15a bne.n 80012cc sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001216: f44f 5380 mov.w r3, #4096 @ 0x1000 if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 800121a: a913 add r1, sp, #76 @ 0x4c 800121c: 4620 mov r0, r4 sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800121e: 9313 str r3, [sp, #76] @ 0x4c if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 8001220: f008 fe9a bl 8009f58 8001224: 4603 mov r3, r0 8001226: 2800 cmp r0, #0 8001228: d150 bne.n 80012cc sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 800122a: 2220 movs r2, #32 if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 800122c: 4620 mov r0, r4 800122e: a907 add r1, sp, #28 sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8001230: 9308 str r3, [sp, #32] sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001232: 9207 str r2, [sp, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001234: f8cd 8024 str.w r8, [sp, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 8001238: f009 f98a bl 800a550 800123c: 2800 cmp r0, #0 800123e: d145 bne.n 80012cc hiwdg1.Instance = IWDG1; 8001240: 482e ldr r0, [pc, #184] @ (80012fc ) hiwdg1.Init.Window = 249; 8001242: 23f9 movs r3, #249 @ 0xf9 hiwdg1.Instance = IWDG1; 8001244: 492e ldr r1, [pc, #184] @ (8001300 ) hiwdg1.Init.Prescaler = IWDG_PRESCALER_64; 8001246: 2204 movs r2, #4 hiwdg1.Init.Window = 249; 8001248: 60c3 str r3, [r0, #12] hiwdg1.Init.Reload = 249; 800124a: 6083 str r3, [r0, #8] hiwdg1.Init.Prescaler = IWDG_PRESCALER_64; 800124c: e9c0 1200 strd r1, r2, [r0] if (HAL_IWDG_Init(&hiwdg1) != HAL_OK) 8001250: f005 ffd0 bl 80071f4 8001254: 2800 cmp r0, #0 8001256: d139 bne.n 80012cc HAL_IWDG_Refresh(&hiwdg1); 8001258: 4828 ldr r0, [pc, #160] @ (80012fc ) 800125a: f005 fff9 bl 8007250 debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 800125e: 4c29 ldr r4, [pc, #164] @ (8001304 ) osKernelInitialize(); 8001260: f00a fc98 bl 800bb94 debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 8001264: 2200 movs r2, #0 8001266: 4b28 ldr r3, [pc, #160] @ (8001308 ) 8001268: 4611 mov r1, r2 800126a: 4828 ldr r0, [pc, #160] @ (800130c ) 800126c: f00a fd10 bl 800bc90 fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 8001270: 2200 movs r2, #0 debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 8001272: 6020 str r0, [r4, #0] fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 8001274: 4c26 ldr r4, [pc, #152] @ (8001310 ) 8001276: 4611 mov r1, r2 8001278: 4b26 ldr r3, [pc, #152] @ (8001314 ) 800127a: 4827 ldr r0, [pc, #156] @ (8001318 ) 800127c: f00a fd08 bl 800bc90 8001280: 6020 str r0, [r4, #0] motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 8001282: 4c26 ldr r4, [pc, #152] @ (800131c ) 8001284: 2200 movs r2, #0 8001286: 4b26 ldr r3, [pc, #152] @ (8001320 ) 8001288: 2101 movs r1, #1 800128a: 4826 ldr r0, [pc, #152] @ (8001324 ) 800128c: f00a fd00 bl 800bc90 motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 8001290: 4b25 ldr r3, [pc, #148] @ (8001328 ) motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 8001292: 6020 str r0, [r4, #0] motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 8001294: 2200 movs r2, #0 8001296: 2101 movs r1, #1 8001298: 4824 ldr r0, [pc, #144] @ (800132c ) 800129a: f00a fcf9 bl 800bc90 800129e: 4b24 ldr r3, [pc, #144] @ (8001330 ) 80012a0: 4604 mov r4, r0 defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 80012a2: 2100 movs r1, #0 80012a4: 4a23 ldr r2, [pc, #140] @ (8001334 ) 80012a6: 4824 ldr r0, [pc, #144] @ (8001338 ) motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 80012a8: 601c str r4, [r3, #0] defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 80012aa: f00a fc9f bl 800bbec 80012ae: 4b23 ldr r3, [pc, #140] @ (800133c ) 80012b0: 4602 mov r2, r0 HAL_IWDG_Refresh(&hiwdg1); 80012b2: 4812 ldr r0, [pc, #72] @ (80012fc ) defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 80012b4: 601a str r2, [r3, #0] HAL_IWDG_Refresh(&hiwdg1); 80012b6: f005 ffcb bl 8007250 UartTasksInit(); 80012ba: f002 fd7f bl 8003dbc MeasTasksInit(); 80012be: f000 fda1 bl 8001e04 PositionControlTaskInit(); 80012c2: f001 f99b bl 80025fc osKernelStart(); 80012c6: f00a fc77 bl 800bbb8 while (1) 80012ca: e7fe b.n 80012ca Error_Handler(); 80012cc: f7ff fa94 bl 80007f8 80012d0: 24000500 .word 0x24000500 80012d4: 40000400 .word 0x40000400 80012d8: 00010040 .word 0x00010040 80012dc: 24000290 .word 0x24000290 80012e0: 240005bc .word 0x240005bc 80012e4: 40007400 .word 0x40007400 80012e8: 240005f4 .word 0x240005f4 80012ec: 00020006 .word 0x00020006 80012f0: 5800380c .word 0x5800380c 80012f4: 240004b4 .word 0x240004b4 80012f8: 40010400 .word 0x40010400 80012fc: 240005ac .word 0x240005ac 8001300: 58004800 .word 0x58004800 8001304: 24000384 .word 0x24000384 8001308: 080119d0 .word 0x080119d0 800130c: 08000685 .word 0x08000685 8001310: 24000354 .word 0x24000354 8001314: 080119c0 .word 0x080119c0 8001318: 0800068d .word 0x0800068d 800131c: 24000324 .word 0x24000324 8001320: 080119b0 .word 0x080119b0 8001324: 08000699 .word 0x08000699 8001328: 080119a0 .word 0x080119a0 800132c: 080006d1 .word 0x080006d1 8001330: 240002f4 .word 0x240002f4 8001334: 080119e0 .word 0x080119e0 8001338: 08001401 .word 0x08001401 800133c: 24000388 .word 0x24000388 8001340: 240002ac .word 0x240002ac 08001344 : if(hadc->Instance == ADC1) 8001344: 4a24 ldr r2, [pc, #144] @ (80013d8 ) 8001346: 6803 ldr r3, [r0, #0] 8001348: 4293 cmp r3, r2 { 800134a: b510 push {r4, lr} if(hadc->Instance == ADC1) 800134c: d024 beq.n 8001398 if(hadc->Instance == ADC3) 800134e: 4a23 ldr r2, [pc, #140] @ (80013dc ) 8001350: 4293 cmp r3, r2 8001352: d005 beq.n 8001360 osTimerStop (debugLedTimerHandle); 8001354: 4b22 ldr r3, [pc, #136] @ (80013e0 ) } 8001356: e8bd 4010 ldmia.w sp!, {r4, lr} osTimerStop (debugLedTimerHandle); 800135a: 6818 ldr r0, [r3, #0] 800135c: f00a bcf0 b.w 800bd40 SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 8001360: 4920 ldr r1, [pc, #128] @ (80013e4 ) 8001362: f021 021f bic.w r2, r1, #31 __ASM volatile ("dsb 0xF":::"memory"); 8001366: f3bf 8f4f dsb sy SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 800136a: 4b1f ldr r3, [pc, #124] @ (80013e8 ) 800136c: f8c3 225c str.w r2, [r3, #604] @ 0x25c 8001370: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 8001374: f3bf 8f6f isb sy if(adc3MeasDataQueue != NULL) 8001378: 4b1c ldr r3, [pc, #112] @ (80013ec ) 800137a: 6818 ldr r0, [r3, #0] 800137c: b118 cbz r0, 8001386 osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 800137e: 2300 movs r3, #0 8001380: 461a mov r2, r3 8001382: f00a fdc1 bl 800bf08 if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData*sizeof(uint16_t)) != HAL_OK) 8001386: 220a movs r2, #10 8001388: 4916 ldr r1, [pc, #88] @ (80013e4 ) 800138a: 4819 ldr r0, [pc, #100] @ (80013f0 ) 800138c: f003 f906 bl 800459c 8001390: 2800 cmp r0, #0 8001392: d0df beq.n 8001354 Error_Handler(); 8001394: f7ff fa30 bl 80007f8 DbgLEDToggle(DBG_LED4); 8001398: 4604 mov r4, r0 800139a: 2080 movs r0, #128 @ 0x80 800139c: f000 fe2e bl 8001ffc SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80013a0: 4914 ldr r1, [pc, #80] @ (80013f4 ) 80013a2: f021 021f bic.w r2, r1, #31 __ASM volatile ("dsb 0xF":::"memory"); 80013a6: f3bf 8f4f dsb sy 80013aa: 4b0f ldr r3, [pc, #60] @ (80013e8 ) 80013ac: f8c3 225c str.w r2, [r3, #604] @ 0x25c 80013b0: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 80013b4: f3bf 8f6f isb sy if(adc1MeasDataQueue != NULL) 80013b8: 4b0f ldr r3, [pc, #60] @ (80013f8 ) 80013ba: 6818 ldr r0, [r3, #0] 80013bc: b118 cbz r0, 80013c6 osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 80013be: 2300 movs r3, #0 80013c0: 461a mov r2, r3 80013c2: f00a fda1 bl 800bf08 if(HAL_ADCEx_MultiModeStart_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData*sizeof(uint16_t)) != HAL_OK) 80013c6: 2214 movs r2, #20 80013c8: 490a ldr r1, [pc, #40] @ (80013f4 ) 80013ca: 480c ldr r0, [pc, #48] @ (80013fc ) 80013cc: f003 fbc8 bl 8004b60 80013d0: 2800 cmp r0, #0 80013d2: d1df bne.n 8001394 if(hadc->Instance == ADC3) 80013d4: 6823 ldr r3, [r4, #0] 80013d6: e7ba b.n 800134e 80013d8: 40022000 .word 0x40022000 80013dc: 58026000 .word 0x58026000 80013e0: 24000384 .word 0x24000384 80013e4: 24000240 .word 0x24000240 80013e8: e000ed00 .word 0xe000ed00 80013ec: 2400098c .word 0x2400098c 80013f0: 24000788 .word 0x24000788 80013f4: 24000260 .word 0x24000260 80013f8: 24000994 .word 0x24000994 80013fc: 24000850 .word 0x24000850 08001400 : { 8001400: b580 push {r7, lr} HAL_IWDG_Refresh(&hiwdg1); 8001402: 4839 ldr r0, [pc, #228] @ (80014e8 ) 8001404: f005 ff24 bl 8007250 SelectCurrentSensorGain(CurrentSensorL1, csGain3); 8001408: 2102 movs r1, #2 800140a: 2000 movs r0, #0 800140c: f000 fe04 bl 8002018 SelectCurrentSensorGain(CurrentSensorL2, csGain3); 8001410: 2102 movs r1, #2 8001412: 2001 movs r0, #1 8001414: f000 fe00 bl 8002018 SelectCurrentSensorGain(CurrentSensorL3, csGain3); 8001418: 2102 movs r1, #2 800141a: 4608 mov r0, r1 800141c: f000 fdfc bl 8002018 EnableCurrentSensors(); 8001420: f000 fdf2 bl 8002008 osDelay(pdMS_TO_TICKS(100)); 8001424: 2064 movs r0, #100 @ 0x64 8001426: f00a fc25 bl 800bc74 HAL_IWDG_Refresh(&hiwdg1); 800142a: 482f ldr r0, [pc, #188] @ (80014e8 ) 800142c: f005 ff10 bl 8007250 if(HAL_TIM_Base_Start(&htim8) != HAL_OK) 8001430: 482e ldr r0, [pc, #184] @ (80014ec ) 8001432: f008 fb2b bl 8009a8c 8001436: b928 cbnz r0, 8001444 if(HAL_ADCEx_MultiModeStart_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData*sizeof(uint16_t)) != HAL_OK) 8001438: 2214 movs r2, #20 800143a: 492d ldr r1, [pc, #180] @ (80014f0 ) 800143c: 482d ldr r0, [pc, #180] @ (80014f4 ) 800143e: f003 fb8f bl 8004b60 8001442: b108 cbz r0, 8001448 Error_Handler(); 8001444: f7ff f9d8 bl 80007f8 if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData*sizeof(uint16_t)) != HAL_OK) 8001448: 220a movs r2, #10 800144a: 492b ldr r1, [pc, #172] @ (80014f8 ) 800144c: 482b ldr r0, [pc, #172] @ (80014fc ) 800144e: f003 f8a5 bl 800459c 8001452: 2800 cmp r0, #0 8001454: d1f6 bne.n 8001444 HAL_IWDG_Refresh(&hiwdg1); 8001456: 4d24 ldr r5, [pc, #144] @ (80014e8 ) HAL_COMP_Start(&hcomp1); 8001458: 4829 ldr r0, [pc, #164] @ (8001500 ) 800145a: f003 fd13 bl 8004e84 HAL_IWDG_Refresh(&hiwdg1); 800145e: 4628 mov r0, r5 8001460: 4e28 ldr r6, [pc, #160] @ (8001504 ) 8001462: 4f29 ldr r7, [pc, #164] @ (8001508 ) if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001464: 4c29 ldr r4, [pc, #164] @ (800150c ) HAL_IWDG_Refresh(&hiwdg1); 8001466: f005 fef3 bl 8007250 800146a: e005 b.n 8001478 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 800146c: 2108 movs r1, #8 800146e: 4620 mov r0, r4 8001470: f008 feec bl 800a24c 8001474: 2801 cmp r0, #1 8001476: d023 beq.n 80014c0 osDelay(pdMS_TO_TICKS(100)); 8001478: 2064 movs r0, #100 @ 0x64 800147a: f00a fbfb bl 800bc74 HAL_IWDG_Refresh(&hiwdg1); 800147e: 4628 mov r0, r5 8001480: f005 fee6 bl 8007250 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001484: 2100 movs r1, #0 8001486: 4620 mov r0, r4 8001488: f008 fee0 bl 800a24c 800148c: 2801 cmp r0, #1 800148e: d1ed bne.n 800146c HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001490: 2104 movs r1, #4 8001492: 4620 mov r0, r4 8001494: f008 feda bl 800a24c if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001498: 2801 cmp r0, #1 800149a: d1e7 bne.n 800146c if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 800149c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80014a0: 6830 ldr r0, [r6, #0] 80014a2: f00a fcaf bl 800be04 80014a6: 4603 mov r3, r0 80014a8: 2800 cmp r0, #0 80014aa: d1df bne.n 800146c osMutexRelease(sensorsInfoMutex); 80014ac: 6830 ldr r0, [r6, #0] sensorsInfo.motorXStatus = 0; 80014ae: 753b strb r3, [r7, #20] osMutexRelease(sensorsInfoMutex); 80014b0: f00a fccc bl 800be4c if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 80014b4: 2108 movs r1, #8 80014b6: 4620 mov r0, r4 80014b8: f008 fec8 bl 800a24c 80014bc: 2801 cmp r0, #1 80014be: d1db bne.n 8001478 HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 80014c0: 210c movs r1, #12 80014c2: 4620 mov r0, r4 80014c4: f008 fec2 bl 800a24c if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 80014c8: 2801 cmp r0, #1 80014ca: d1d5 bne.n 8001478 if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 80014cc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80014d0: 6830 ldr r0, [r6, #0] 80014d2: f00a fc97 bl 800be04 80014d6: 4603 mov r3, r0 80014d8: 2800 cmp r0, #0 80014da: d1cd bne.n 8001478 osMutexRelease(sensorsInfoMutex); 80014dc: 6830 ldr r0, [r6, #0] sensorsInfo.motorYStatus = 0; 80014de: 757b strb r3, [r7, #21] osMutexRelease(sensorsInfoMutex); 80014e0: f00a fcb4 bl 800be4c 80014e4: e7c8 b.n 8001478 80014e6: bf00 nop 80014e8: 240005ac .word 0x240005ac 80014ec: 240004b4 .word 0x240004b4 80014f0: 24000260 .word 0x24000260 80014f4: 24000850 .word 0x24000850 80014f8: 24000240 .word 0x24000240 80014fc: 24000788 .word 0x24000788 8001500: 240005f4 .word 0x240005f4 8001504: 24000980 .word 0x24000980 8001508: 24000900 .word 0x24000900 800150c: 24000500 .word 0x24000500 08001510 : osMutexRelease (resMeasurementsMutex); } } } void ADC3MeasTask (void* arg) { 8001510: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8001514: ed2d 8b10 vpush {d8-d15} 8001518: b0cb sub sp, #300 @ 0x12c float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 800151a: 2228 movs r2, #40 @ 0x28 800151c: 2100 movs r1, #0 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; #ifdef PV_BOARD float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; #endif uint32_t circBuffPos = 0; 800151e: 2400 movs r4, #0 float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8001520: a822 add r0, sp, #136 @ 0x88 8001522: f8df b3a8 ldr.w fp, [pc, #936] @ 80018cc 8001526: f00e faef bl 800fb08 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 800152a: 2228 movs r2, #40 @ 0x28 800152c: 2100 movs r1, #0 800152e: a82c add r0, sp, #176 @ 0xb0 8001530: f00e faea bl 800fb08 float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 8001534: 2228 movs r2, #40 @ 0x28 8001536: 2100 movs r1, #0 8001538: a836 add r0, sp, #216 @ 0xd8 800153a: f00e fae5 bl 800fb08 float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800153e: 2228 movs r2, #40 @ 0x28 8001540: 4621 mov r1, r4 8001542: a840 add r0, sp, #256 @ 0x100 8001544: f00e fae0 bl 800fb08 ADC3_Data adcData = { 0 }; 8001548: 2220 movs r2, #32 800154a: 4621 mov r1, r4 800154c: a81a add r0, sp, #104 @ 0x68 800154e: f8df 8380 ldr.w r8, [pc, #896] @ 80018d0 8001552: f00e fad9 bl 800fb08 8001556: 4fd8 ldr r7, [pc, #864] @ (80018b8 ) 8001558: 4dd8 ldr r5, [pc, #864] @ (80018bc ) while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 800155a: f8df a378 ldr.w sl, [pc, #888] @ 80018d4 800155e: e17c b.n 800185a float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; #ifdef PV_BOARD pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8001560: f8bd 3068 ldrh.w r3, [sp, #104] @ 0x68 } motorXAveCurrent /= CIRC_BUFF_LEN; motorYAveCurrent /= CIRC_BUFF_LEN; pvT1AveTemp /= CIRC_BUFF_LEN; pvT2AveTemp /= CIRC_BUFF_LEN; if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001564: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8001568: ee05 3a10 vmov s10, r3 pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 800156c: f8bd 306a ldrh.w r3, [sp, #106] @ 0x6a pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8001570: eeb8 5bc5 vcvt.f64.s32 d5, s10 pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 8001574: ee03 3a10 vmov s6, r3 float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 8001578: f8bd 306c ldrh.w r3, [sp, #108] @ 0x6c pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 800157c: eeb8 3bc3 vcvt.f64.s32 d3, s6 float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 8001580: ee06 3a10 vmov s12, r3 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 8001584: f8bd 306e ldrh.w r3, [sp, #110] @ 0x6e pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8001588: ed9f 2bc5 vldr d2, [pc, #788] @ 80018a0 800158c: ed9f 4bc6 vldr d4, [pc, #792] @ 80018a8 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 8001590: ee07 3a10 vmov s14, r3 float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 8001594: eeb8 6bc6 vcvt.f64.s32 d6, s12 motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 8001598: ab4a add r3, sp, #296 @ 0x128 pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 800159a: eea5 4b02 vfma.f64 d4, d5, d2 motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 800159e: eb03 0384 add.w r3, r3, r4, lsl #2 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 80015a2: eeb8 7bc7 vcvt.f64.s32 d7, s14 pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 80015a6: ed9f 5bc0 vldr d5, [pc, #768] @ 80018a8 80015aa: eea3 5b02 vfma.f64 d5, d3, d2 pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 80015ae: eeb7 4bc4 vcvt.f32.f64 s8, d4 float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80015b2: ed9f 3bbf vldr d3, [pc, #764] @ 80018b0 pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 80015b6: ed03 4a14 vstr s8, [r3, #-80] @ 0xffffffb0 pvT1AveTemp += pvT1CircBuffer[i]; 80015ba: eddd fa38 vldr s31, [sp, #224] @ 0xe0 float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80015be: ee26 6b03 vmul.f64 d6, d6, d3 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 80015c2: ee27 7b03 vmul.f64 d7, d7, d3 float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80015c6: eef7 8bc6 vcvt.f32.f64 s17, d6 pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 80015ca: eeb7 5bc5 vcvt.f32.f64 s10, d5 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 80015ce: eeb7 8bc7 vcvt.f32.f64 s16, d7 motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 80015d2: ed43 8a28 vstr s17, [r3, #-160] @ 0xffffff60 motorXAveCurrent += motorXSensCircBuffer[i]; 80015d6: eddd 7a22 vldr s15, [sp, #136] @ 0x88 pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 80015da: ed03 5a0a vstr s10, [r3, #-40] @ 0xffffffd8 motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 80015de: ed03 8a1e vstr s16, [r3, #-120] @ 0xffffff88 motorXAveCurrent += motorXSensCircBuffer[i]; 80015e2: edcd 7a06 vstr s15, [sp, #24] motorYAveCurrent += motorYSensCircBuffer[i]; 80015e6: eddd 7a2c vldr s15, [sp, #176] @ 0xb0 pvT2AveTemp += pvT2CircBuffer[i]; 80015ea: ed9d fa42 vldr s30, [sp, #264] @ 0x108 motorYAveCurrent += motorYSensCircBuffer[i]; 80015ee: edcd 7a07 vstr s15, [sp, #28] pvT1AveTemp += pvT1CircBuffer[i]; 80015f2: eddd 7a36 vldr s15, [sp, #216] @ 0xd8 80015f6: edcd 7a00 vstr s15, [sp] pvT2AveTemp += pvT2CircBuffer[i]; 80015fa: eddd 7a40 vldr s15, [sp, #256] @ 0x100 80015fe: edcd 7a01 vstr s15, [sp, #4] motorXAveCurrent += motorXSensCircBuffer[i]; 8001602: eddd 7a23 vldr s15, [sp, #140] @ 0x8c 8001606: edcd 7a08 vstr s15, [sp, #32] motorYAveCurrent += motorYSensCircBuffer[i]; 800160a: eddd 7a2d vldr s15, [sp, #180] @ 0xb4 800160e: edcd 7a09 vstr s15, [sp, #36] @ 0x24 pvT1AveTemp += pvT1CircBuffer[i]; 8001612: eddd 7a37 vldr s15, [sp, #220] @ 0xdc 8001616: edcd 7a02 vstr s15, [sp, #8] pvT2AveTemp += pvT2CircBuffer[i]; 800161a: eddd 7a41 vldr s15, [sp, #260] @ 0x104 800161e: edcd 7a03 vstr s15, [sp, #12] motorXAveCurrent += motorXSensCircBuffer[i]; 8001622: eddd 7a24 vldr s15, [sp, #144] @ 0x90 8001626: edcd 7a0a vstr s15, [sp, #40] @ 0x28 motorYAveCurrent += motorYSensCircBuffer[i]; 800162a: eddd 7a2e vldr s15, [sp, #184] @ 0xb8 800162e: edcd 7a0b vstr s15, [sp, #44] @ 0x2c motorXAveCurrent += motorXSensCircBuffer[i]; 8001632: eddd 7a25 vldr s15, [sp, #148] @ 0x94 8001636: edcd 7a0c vstr s15, [sp, #48] @ 0x30 motorYAveCurrent += motorYSensCircBuffer[i]; 800163a: eddd 7a2f vldr s15, [sp, #188] @ 0xbc pvT1AveTemp += pvT1CircBuffer[i]; 800163e: eddd ea39 vldr s29, [sp, #228] @ 0xe4 motorYAveCurrent += motorYSensCircBuffer[i]; 8001642: edcd 7a0d vstr s15, [sp, #52] @ 0x34 motorXAveCurrent += motorXSensCircBuffer[i]; 8001646: eddd 7a26 vldr s15, [sp, #152] @ 0x98 pvT2AveTemp += pvT2CircBuffer[i]; 800164a: ed9d ea43 vldr s28, [sp, #268] @ 0x10c motorXAveCurrent += motorXSensCircBuffer[i]; 800164e: edcd 7a0e vstr s15, [sp, #56] @ 0x38 motorYAveCurrent += motorYSensCircBuffer[i]; 8001652: eddd 7a30 vldr s15, [sp, #192] @ 0xc0 pvT1AveTemp += pvT1CircBuffer[i]; 8001656: eddd da3a vldr s27, [sp, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 800165a: edcd 7a0f vstr s15, [sp, #60] @ 0x3c motorXAveCurrent += motorXSensCircBuffer[i]; 800165e: eddd 7a27 vldr s15, [sp, #156] @ 0x9c pvT2AveTemp += pvT2CircBuffer[i]; 8001662: ed9d da44 vldr s26, [sp, #272] @ 0x110 motorXAveCurrent += motorXSensCircBuffer[i]; 8001666: edcd 7a10 vstr s15, [sp, #64] @ 0x40 motorYAveCurrent += motorYSensCircBuffer[i]; 800166a: eddd 7a31 vldr s15, [sp, #196] @ 0xc4 pvT1AveTemp += pvT1CircBuffer[i]; 800166e: eddd ca3b vldr s25, [sp, #236] @ 0xec motorYAveCurrent += motorYSensCircBuffer[i]; 8001672: edcd 7a11 vstr s15, [sp, #68] @ 0x44 motorXAveCurrent += motorXSensCircBuffer[i]; 8001676: eddd 7a28 vldr s15, [sp, #160] @ 0xa0 pvT2AveTemp += pvT2CircBuffer[i]; 800167a: ed9d ca45 vldr s24, [sp, #276] @ 0x114 motorXAveCurrent += motorXSensCircBuffer[i]; 800167e: edcd 7a12 vstr s15, [sp, #72] @ 0x48 motorYAveCurrent += motorYSensCircBuffer[i]; 8001682: eddd 7a32 vldr s15, [sp, #200] @ 0xc8 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001686: 6838 ldr r0, [r7, #0] motorYAveCurrent += motorYSensCircBuffer[i]; 8001688: edcd 7a13 vstr s15, [sp, #76] @ 0x4c pvT2AveTemp += pvT2CircBuffer[i]; 800168c: eddd 7a46 vldr s15, [sp, #280] @ 0x118 pvT1AveTemp += pvT1CircBuffer[i]; 8001690: eddd ba3c vldr s23, [sp, #240] @ 0xf0 pvT2AveTemp += pvT2CircBuffer[i]; 8001694: edcd 7a04 vstr s15, [sp, #16] motorXAveCurrent += motorXSensCircBuffer[i]; 8001698: eddd 7a29 vldr s15, [sp, #164] @ 0xa4 pvT1AveTemp += pvT1CircBuffer[i]; 800169c: ed9d ba3d vldr s22, [sp, #244] @ 0xf4 motorXAveCurrent += motorXSensCircBuffer[i]; 80016a0: edcd 7a14 vstr s15, [sp, #80] @ 0x50 motorYAveCurrent += motorYSensCircBuffer[i]; 80016a4: eddd 7a33 vldr s15, [sp, #204] @ 0xcc pvT2AveTemp += pvT2CircBuffer[i]; 80016a8: eddd aa47 vldr s21, [sp, #284] @ 0x11c motorYAveCurrent += motorYSensCircBuffer[i]; 80016ac: edcd 7a15 vstr s15, [sp, #84] @ 0x54 motorXAveCurrent += motorXSensCircBuffer[i]; 80016b0: eddd 7a2a vldr s15, [sp, #168] @ 0xa8 80016b4: edcd 7a16 vstr s15, [sp, #88] @ 0x58 motorYAveCurrent += motorYSensCircBuffer[i]; 80016b8: eddd 7a34 vldr s15, [sp, #208] @ 0xd0 pvT1AveTemp += pvT1CircBuffer[i]; 80016bc: ed9d aa3e vldr s20, [sp, #248] @ 0xf8 motorYAveCurrent += motorYSensCircBuffer[i]; 80016c0: edcd 7a17 vstr s15, [sp, #92] @ 0x5c motorXAveCurrent += motorXSensCircBuffer[i]; 80016c4: eddd 7a2b vldr s15, [sp, #172] @ 0xac pvT2AveTemp += pvT2CircBuffer[i]; 80016c8: eddd 9a48 vldr s19, [sp, #288] @ 0x120 motorXAveCurrent += motorXSensCircBuffer[i]; 80016cc: edcd 7a18 vstr s15, [sp, #96] @ 0x60 motorYAveCurrent += motorYSensCircBuffer[i]; 80016d0: eddd 7a35 vldr s15, [sp, #212] @ 0xd4 pvT1AveTemp += pvT1CircBuffer[i]; 80016d4: ed9d 9a3f vldr s18, [sp, #252] @ 0xfc motorYAveCurrent += motorYSensCircBuffer[i]; 80016d8: edcd 7a19 vstr s15, [sp, #100] @ 0x64 pvT2AveTemp += pvT2CircBuffer[i]; 80016dc: eddd 7a49 vldr s15, [sp, #292] @ 0x124 80016e0: edcd 7a05 vstr s15, [sp, #20] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80016e4: f00a fb8e bl 800be04 80016e8: 2800 cmp r0, #0 80016ea: f040 80ad bne.w 8001848 if (sensorsInfo.motorXStatus == 1) { 80016ee: 7d2b ldrb r3, [r5, #20] 80016f0: 2b01 cmp r3, #1 80016f2: d134 bne.n 800175e motorXAveCurrent += motorXSensCircBuffer[i]; 80016f4: ed9d 7a08 vldr s14, [sp, #32] 80016f8: eddd 7a06 vldr s15, [sp, #24] 80016fc: ee77 7a87 vadd.f32 s15, s15, s14 8001700: ed9d 7a0a vldr s14, [sp, #40] @ 0x28 8001704: ee77 7a87 vadd.f32 s15, s15, s14 8001708: ed9d 7a0c vldr s14, [sp, #48] @ 0x30 800170c: ee77 7a87 vadd.f32 s15, s15, s14 8001710: ed9d 7a0e vldr s14, [sp, #56] @ 0x38 8001714: ee77 7a87 vadd.f32 s15, s15, s14 8001718: ed9d 7a10 vldr s14, [sp, #64] @ 0x40 800171c: ee77 7a87 vadd.f32 s15, s15, s14 8001720: ed9d 7a12 vldr s14, [sp, #72] @ 0x48 8001724: ee77 7a87 vadd.f32 s15, s15, s14 8001728: ed9d 7a14 vldr s14, [sp, #80] @ 0x50 800172c: ee77 7a87 vadd.f32 s15, s15, s14 8001730: ed9d 7a16 vldr s14, [sp, #88] @ 0x58 8001734: ee77 7a87 vadd.f32 s15, s15, s14 8001738: ed9d 7a18 vldr s14, [sp, #96] @ 0x60 800173c: ee77 7a87 vadd.f32 s15, s15, s14 motorXAveCurrent /= CIRC_BUFF_LEN; 8001740: ed9f 7a5f vldr s14, [pc, #380] @ 80018c0 8001744: ee67 7a87 vmul.f32 s15, s15, s14 sensorsInfo.motorXAveCurrent = motorXAveCurrent; 8001748: edc5 7a06 vstr s15, [r5, #24] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 800174c: edd5 7a08 vldr s15, [r5, #32] 8001750: eef4 7ae8 vcmpe.f32 s15, s17 8001754: eef1 fa10 vmrs APSR_nzcv, fpscr sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 8001758: bf48 it mi 800175a: edc5 8a08 vstrmi s17, [r5, #32] } } if (sensorsInfo.motorYStatus == 1) { 800175e: 7d6b ldrb r3, [r5, #21] 8001760: 2b01 cmp r3, #1 8001762: d134 bne.n 80017ce motorYAveCurrent += motorYSensCircBuffer[i]; 8001764: ed9d 7a09 vldr s14, [sp, #36] @ 0x24 8001768: eddd 7a07 vldr s15, [sp, #28] sensorsInfo.motorYAveCurrent = motorYAveCurrent; if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 800176c: edd5 6a09 vldr s13, [r5, #36] @ 0x24 motorYAveCurrent += motorYSensCircBuffer[i]; 8001770: ee77 7a87 vadd.f32 s15, s15, s14 8001774: ed9d 7a0b vldr s14, [sp, #44] @ 0x2c if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 8001778: eef4 6ac8 vcmpe.f32 s13, s16 motorYAveCurrent += motorYSensCircBuffer[i]; 800177c: ee77 7a87 vadd.f32 s15, s15, s14 8001780: ed9d 7a0d vldr s14, [sp, #52] @ 0x34 if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 8001784: eef1 fa10 vmrs APSR_nzcv, fpscr motorYAveCurrent += motorYSensCircBuffer[i]; 8001788: ee77 7a87 vadd.f32 s15, s15, s14 800178c: ed9d 7a0f vldr s14, [sp, #60] @ 0x3c sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 8001790: bf48 it mi 8001792: ed85 8a09 vstrmi s16, [r5, #36] @ 0x24 motorYAveCurrent += motorYSensCircBuffer[i]; 8001796: ee77 7a87 vadd.f32 s15, s15, s14 800179a: ed9d 7a11 vldr s14, [sp, #68] @ 0x44 800179e: ee77 7a87 vadd.f32 s15, s15, s14 80017a2: ed9d 7a13 vldr s14, [sp, #76] @ 0x4c 80017a6: ee77 7a87 vadd.f32 s15, s15, s14 80017aa: ed9d 7a15 vldr s14, [sp, #84] @ 0x54 80017ae: ee77 7a87 vadd.f32 s15, s15, s14 80017b2: ed9d 7a17 vldr s14, [sp, #92] @ 0x5c 80017b6: ee77 7a87 vadd.f32 s15, s15, s14 80017ba: ed9d 7a19 vldr s14, [sp, #100] @ 0x64 80017be: ee77 7a87 vadd.f32 s15, s15, s14 motorYAveCurrent /= CIRC_BUFF_LEN; 80017c2: ed9f 7a3f vldr s14, [pc, #252] @ 80018c0 80017c6: ee67 7a87 vmul.f32 s15, s15, s14 sensorsInfo.motorYAveCurrent = motorYAveCurrent; 80017ca: edc5 7a07 vstr s15, [r5, #28] pvT1AveTemp += pvT1CircBuffer[i]; 80017ce: eddd 7a00 vldr s15, [sp] 80017d2: ed9d 7a02 vldr s14, [sp, #8] pvT2AveTemp += pvT2CircBuffer[i]; 80017d6: eddd 6a03 vldr s13, [sp, #12] pvT1AveTemp += pvT1CircBuffer[i]; 80017da: ee37 7a87 vadd.f32 s14, s15, s14 pvT2AveTemp += pvT2CircBuffer[i]; 80017de: eddd 7a01 vldr s15, [sp, #4] } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; sensorsInfo.pvTemperature[1] = pvT2AveTemp; osMutexRelease (sensorsInfoMutex); 80017e2: 6838 ldr r0, [r7, #0] pvT2AveTemp += pvT2CircBuffer[i]; 80017e4: ee77 7aa6 vadd.f32 s15, s15, s13 80017e8: eddd 6a04 vldr s13, [sp, #16] pvT1AveTemp += pvT1CircBuffer[i]; 80017ec: ee37 7a2f vadd.f32 s14, s14, s31 pvT2AveTemp += pvT2CircBuffer[i]; 80017f0: ee77 7a8f vadd.f32 s15, s15, s30 pvT1AveTemp += pvT1CircBuffer[i]; 80017f4: ee37 7a2e vadd.f32 s14, s14, s29 pvT2AveTemp += pvT2CircBuffer[i]; 80017f8: ee77 7a8e vadd.f32 s15, s15, s28 pvT1AveTemp += pvT1CircBuffer[i]; 80017fc: ee37 7a2d vadd.f32 s14, s14, s27 pvT2AveTemp += pvT2CircBuffer[i]; 8001800: ee77 7a8d vadd.f32 s15, s15, s26 pvT1AveTemp += pvT1CircBuffer[i]; 8001804: ee37 7a2c vadd.f32 s14, s14, s25 pvT2AveTemp += pvT2CircBuffer[i]; 8001808: ee77 7a8c vadd.f32 s15, s15, s24 pvT1AveTemp += pvT1CircBuffer[i]; 800180c: ee37 7a2b vadd.f32 s14, s14, s23 pvT2AveTemp += pvT2CircBuffer[i]; 8001810: ee77 7aa6 vadd.f32 s15, s15, s13 8001814: eddd 6a05 vldr s13, [sp, #20] pvT1AveTemp += pvT1CircBuffer[i]; 8001818: ee37 7a0b vadd.f32 s14, s14, s22 pvT2AveTemp += pvT2CircBuffer[i]; 800181c: ee77 7aaa vadd.f32 s15, s15, s21 pvT1AveTemp += pvT1CircBuffer[i]; 8001820: ee37 7a0a vadd.f32 s14, s14, s20 pvT2AveTemp += pvT2CircBuffer[i]; 8001824: ee77 7aa9 vadd.f32 s15, s15, s19 pvT1AveTemp += pvT1CircBuffer[i]; 8001828: ee37 7a09 vadd.f32 s14, s14, s18 pvT2AveTemp += pvT2CircBuffer[i]; 800182c: ee77 7aa6 vadd.f32 s15, s15, s13 pvT1AveTemp /= CIRC_BUFF_LEN; 8001830: eddf 6a23 vldr s13, [pc, #140] @ 80018c0 8001834: ee27 7a26 vmul.f32 s14, s14, s13 pvT2AveTemp /= CIRC_BUFF_LEN; 8001838: ee67 7aa6 vmul.f32 s15, s15, s13 sensorsInfo.pvTemperature[0] = pvT1AveTemp; 800183c: ed85 7a00 vstr s14, [r5] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 8001840: edc5 7a01 vstr s15, [r5, #4] osMutexRelease (sensorsInfoMutex); 8001844: f00a fb02 bl 800be4c } ++circBuffPos; 8001848: 1c63 adds r3, r4, #1 circBuffPos = circBuffPos % CIRC_BUFF_LEN; 800184a: 4c1e ldr r4, [pc, #120] @ (80018c4 ) 800184c: fba4 2403 umull r2, r4, r4, r3 8001850: 08e4 lsrs r4, r4, #3 8001852: eb04 0484 add.w r4, r4, r4, lsl #2 8001856: eba3 0444 sub.w r4, r3, r4, lsl #1 osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 800185a: a91a add r1, sp, #104 @ 0x68 800185c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001860: 2200 movs r2, #0 8001862: f8db 0000 ldr.w r0, [fp] 8001866: f00a fb8b bl 800bf80 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 800186a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800186e: f8d8 0000 ldr.w r0, [r8] uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 8001872: f8ba 6060 ldrh.w r6, [sl, #96] @ 0x60 8001876: f8bd 9070 ldrh.w r9, [sp, #112] @ 0x70 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 800187a: f00a fac3 bl 800be04 800187e: 2800 cmp r0, #0 8001880: f47f ae6e bne.w 8001560 uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 8001884: f640 43e4 movw r3, #3300 @ 0xce4 osMutexRelease (vRefmVMutex); 8001888: f8d8 0000 ldr.w r0, [r8] uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 800188c: fb03 f606 mul.w r6, r3, r6 vRefmV = vRef; 8001890: 4b0d ldr r3, [pc, #52] @ (80018c8 ) uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 8001892: fbb6 f6f9 udiv r6, r6, r9 vRefmV = vRef; 8001896: 601e str r6, [r3, #0] osMutexRelease (vRefmVMutex); 8001898: f00a fad8 bl 800be4c 800189c: e660 b.n 8001560 800189e: bf00 nop 80018a0: 000ba1a8 .word 0x000ba1a8 80018a4: 3f610011 .word 0x3f610011 80018a8: 00000000 .word 0x00000000 80018ac: c04f8000 .word 0xc04f8000 80018b0: 5afd32cf .word 0x5afd32cf 80018b4: 3f0cccea .word 0x3f0cccea 80018b8: 24000980 .word 0x24000980 80018bc: 24000900 .word 0x24000900 80018c0: 3dcccccd .word 0x3dcccccd 80018c4: cccccccd .word 0xcccccccd 80018c8: 24000030 .word 0x24000030 80018cc: 2400098c .word 0x2400098c 80018d0: 24000988 .word 0x24000988 80018d4: 1ff1e800 .word 0x1ff1e800 080018d8 : void ADC1MeasTask (void* arg) { 80018d8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80018dc: ed2d 8b0c vpush {d8-d13} 80018e0: b089 sub sp, #36 @ 0x24 float powerAcc[CHANNELS_COUNT] = { 0 }; 80018e2: eddf aa73 vldr s21, [pc, #460] @ 8001ab0 ADC1_Data adcData = { 0 }; 80018e6: 2220 movs r2, #32 80018e8: 2100 movs r1, #0 80018ea: 4668 mov r0, sp float gainCorrection = 1.0; 80018ec: eeb7 ca00 vmov.f32 s24, #112 @ 0x3f800000 1.0 float currentAcc[CHANNELS_COUNT] = { 0 }; 80018f0: eef0 ba6a vmov.f32 s23, s21 80018f4: f8df a1d4 ldr.w sl, [pc, #468] @ 8001acc float voltageAcc[CHANNELS_COUNT] = { 0 }; 80018f8: eeb0 ba6a vmov.f32 s22, s21 80018fc: f8df 91d0 ldr.w r9, [pc, #464] @ 8001ad0 8001900: f8df 81d0 ldr.w r8, [pc, #464] @ 8001ad4 8001904: 2701 movs r7, #1 gainCorrection = gainCorrection / EXT_VREF_mV; 8001906: ed9f aa6b vldr s20, [pc, #428] @ 8001ab4 800190a: 4c6b ldr r4, [pc, #428] @ (8001ab8 ) 800190c: 4e6b ldr r6, [pc, #428] @ (8001abc ) 800190e: 4d6c ldr r5, [pc, #432] @ (8001ac0 ) float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8001910: ed9f 9b61 vldr d9, [pc, #388] @ 8001a98 float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8001914: ed9f 8b62 vldr d8, [pc, #392] @ 8001aa0 float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8001918: ed9f db63 vldr d13, [pc, #396] @ 8001aa8 ADC1_Data adcData = { 0 }; 800191c: f00e f8f4 bl 800fb08 osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 8001920: 4669 mov r1, sp 8001922: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001926: 2200 movs r2, #0 8001928: f8da 0000 ldr.w r0, [sl] 800192c: f00a fb28 bl 800bf80 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8001930: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001934: f8d9 0000 ldr.w r0, [r9] 8001938: f00a fa64 bl 800be04 800193c: 2800 cmp r0, #0 800193e: f000 80a0 beq.w 8001a82 if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8001942: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001946: f8d8 0000 ldr.w r0, [r8] gainCorrection = gainCorrection / EXT_VREF_mV; 800194a: ee2c ca0a vmul.f32 s24, s24, s20 samplesCounter += 1; 800194e: 46bb mov fp, r7 if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8001950: f00a fa58 bl 800be04 8001954: 2800 cmp r0, #0 8001956: d1e3 bne.n 8001920 float adcVal = (float)adcData.adcDataBuffer[IIL1 + i]; 8001958: f8bd 300e ldrh.w r3, [sp, #14] float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 800195c: eeb7 1acc vcvt.f64.f32 d1, s24 8001960: ed96 3a00 vldr s6, [r6] float adcVal = (float)adcData.adcDataBuffer[IIL1 + i]; 8001964: ee06 3a10 vmov s12, r3 float ref = (float)adcData.adcDataBuffer[IL1Ref + i]; 8001968: f8bd 3006 ldrh.w r3, [sp, #6] float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 800196c: eeb7 3ac3 vcvt.f64.f32 d3, s6 float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8001970: ed95 2a00 vldr s4, [r5] float ref = (float)adcData.adcDataBuffer[IL1Ref + i]; 8001974: ee07 3a90 vmov s15, r3 float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8001978: f8bd 3000 ldrh.w r3, [sp] float adcVal = (float)adcData.adcDataBuffer[IIL1 + i]; 800197c: eeb8 6a46 vcvt.f32.u32 s12, s12 float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8001980: ed96 5a01 vldr s10, [r6, #4] float ref = (float)adcData.adcDataBuffer[IL1Ref + i]; 8001984: eef8 7a67 vcvt.f32.u32 s15, s15 float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8001988: ee04 3a10 vmov s8, r3 800198c: ee23 3b09 vmul.f64 d3, d3, d9 float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8001990: ed95 7a01 vldr s14, [r5, #4] if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) { 8001994: edd4 0a03 vldr s1, [r4, #12] float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8001998: eeb7 2ac2 vcvt.f64.f32 d2, s4 800199c: ee36 6a67 vsub.f32 s12, s12, s15 float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 80019a0: eeb8 4bc4 vcvt.f64.s32 d4, s8 float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 80019a4: ee22 2b08 vmul.f64 d2, d2, d8 float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 80019a8: ee24 4b03 vmul.f64 d4, d4, d3 float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 80019ac: eeb7 6ac6 vcvt.f64.f32 d6, s12 float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 80019b0: eeb7 5ac5 vcvt.f64.f32 d5, s10 float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 80019b4: eeb7 7ac7 vcvt.f64.f32 d7, s14 80019b8: ee26 6b02 vmul.f64 d6, d6, d2 float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 80019bc: eea1 5b04 vfma.f64 d5, d1, d4 float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 80019c0: eea1 7b06 vfma.f64 d7, d1, d6 if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) { 80019c4: eef0 0ae0 vabs.f32 s1, s1 float voltage = adcData.adcDataBuffer[UL1 + i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 80019c8: eeb7 5bc5 vcvt.f32.f64 s10, d5 voltageAcc[i] += voltage * voltage; 80019cc: eea5 ba05 vfma.f32 s22, s10, s10 float current = (adcVal - ref) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 80019d0: eeb7 7bc7 vcvt.f32.f64 s14, d7 if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) { 80019d4: eef0 7ac5 vabs.f32 s15, s10 currentAcc[i] += current * current; 80019d8: eee7 ba07 vfma.f32 s23, s14, s14 if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) { 80019dc: eef4 0ae7 vcmpe.f32 s1, s15 powerAcc[i] += voltage * current; 80019e0: eee5 aa07 vfma.f32 s21, s10, s14 if (fabs (resMeasurements.voltagePeak[i]) < fabs (voltage)) { 80019e4: eef1 fa10 vmrs APSR_nzcv, fpscr 80019e8: d501 bpl.n 80019ee resMeasurements.voltagePeak[i] = voltage; 80019ea: ed84 5a03 vstr s10, [r4, #12] if (fabs (resMeasurements.currentPeak[i]) < fabs (current)) { 80019ee: edd4 6a09 vldr s13, [r4, #36] @ 0x24 80019f2: eef0 7ac7 vabs.f32 s15, s14 if (samplesCounter > 33332) 80019f6: f248 2334 movw r3, #33332 @ 0x8234 if (fabs (resMeasurements.currentPeak[i]) < fabs (current)) { 80019fa: eef0 6ae6 vabs.f32 s13, s13 80019fe: eef4 6ae7 vcmpe.f32 s13, s15 8001a02: eef1 fa10 vmrs APSR_nzcv, fpscr resMeasurements.currentPeak[i] = current; 8001a06: bf48 it mi 8001a08: ed84 7a09 vstrmi s14, [r4, #36] @ 0x24 if (samplesCounter > 33332) 8001a0c: 429f cmp r7, r3 8001a0e: d922 bls.n 8001a56 resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter); 8001a10: ee07 7a90 vmov s15, r7 8001a14: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 DbgLEDToggle(DBG_LED3); 8001a18: 2040 movs r0, #64 @ 0x40 samplesCounter = 0; 8001a1a: f04f 0b00 mov.w fp, #0 resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter); 8001a1e: eeb8 7a67 vcvt.f32.u32 s14, s15 8001a22: eec6 7a87 vdiv.f32 s15, s13, s14 8001a26: ee2b ba27 vmul.f32 s22, s22, s15 resMeasurements.currentRMS[i] = sqrtf(currentAcc[i] / samplesCounter); 8001a2a: ee6b baa7 vmul.f32 s23, s23, s15 resMeasurements.power[i] = powerAcc[i] / samplesCounter; 8001a2e: ee6a 7aa7 vmul.f32 s15, s21, s15 DbgLEDToggle(DBG_LED3); 8001a32: eddf aa1f vldr s21, [pc, #124] @ 8001ab0 resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter); 8001a36: eef1 6acb vsqrt.f32 s13, s22 resMeasurements.power[i] = powerAcc[i] / samplesCounter; 8001a3a: edc4 7a0c vstr s15, [r4, #48] @ 0x30 resMeasurements.currentRMS[i] = sqrtf(currentAcc[i] / samplesCounter); 8001a3e: eeb1 7aeb vsqrt.f32 s14, s23 DbgLEDToggle(DBG_LED3); 8001a42: eeb0 ba6a vmov.f32 s22, s21 8001a46: eef0 ba6a vmov.f32 s23, s21 resMeasurements.voltageRMS[i] = sqrtf(voltageAcc[i] / samplesCounter); 8001a4a: edc4 6a00 vstr s13, [r4] resMeasurements.currentRMS[i] = sqrtf(currentAcc[i] / samplesCounter); 8001a4e: ed84 7a06 vstr s14, [r4, #24] DbgLEDToggle(DBG_LED3); 8001a52: f000 fad3 bl 8001ffc float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8001a56: f8bd 300c ldrh.w r3, [sp, #12] 8001a5a: eeb2 7b08 vmov.f64 d7, #40 @ 0x41400000 12.0 osMutexRelease (resMeasurementsMutex); 8001a5e: f8d8 0000 ldr.w r0, [r8] 8001a62: f10b 0701 add.w r7, fp, #1 float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8001a66: ee06 3a10 vmov s12, r3 8001a6a: 4b16 ldr r3, [pc, #88] @ (8001ac4 ) 8001a6c: eeb8 6bc6 vcvt.f64.s32 d6, s12 8001a70: eea6 7b0d vfma.f64 d7, d6, d13 8001a74: eeb7 7bc7 vcvt.f32.f64 s14, d7 8001a78: ed83 7a02 vstr s14, [r3, #8] osMutexRelease (resMeasurementsMutex); 8001a7c: f00a f9e6 bl 800be4c 8001a80: e74e b.n 8001920 gainCorrection = (float)vRefmV; 8001a82: 4b11 ldr r3, [pc, #68] @ (8001ac8 ) osMutexRelease (vRefmVMutex); 8001a84: f8d9 0000 ldr.w r0, [r9] gainCorrection = (float)vRefmV; 8001a88: ed93 ca00 vldr s24, [r3] 8001a8c: eeb8 ca4c vcvt.f32.u32 s24, s24 osMutexRelease (vRefmVMutex); 8001a90: f00a f9dc bl 800be4c 8001a94: e755 b.n 8001942 8001a96: bf00 nop 8001a98: 7d87690c .word 0x7d87690c 8001a9c: 3f36c535 .word 0x3f36c535 8001aa0: 9d38b97c .word 0x9d38b97c 8001aa4: 3f36ba4d .word 0x3f36ba4d 8001aa8: b34d4ce6 .word 0xb34d4ce6 8001aac: bf2a19b3 .word 0xbf2a19b3 8001ab0: 00000000 .word 0x00000000 8001ab4: 39aec33e .word 0x39aec33e 8001ab8: 24000940 .word 0x24000940 8001abc: 24000018 .word 0x24000018 8001ac0: 24000000 .word 0x24000000 8001ac4: 24000900 .word 0x24000900 8001ac8: 24000030 .word 0x24000030 8001acc: 24000994 .word 0x24000994 8001ad0: 24000988 .word 0x24000988 8001ad4: 24000984 .word 0x24000984 08001ad8 : } } void LimiterSwitchTask (void* arg) { 8001ad8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} uint8_t limitYSwitchCenterPrevState = 0; uint8_t limitYSwitchUpPrevState = 0; uint8_t pinStates = 0; uint8_t limiterXTriggered = 0; uint8_t limiterYTriggered = 0; if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001adc: f8df a214 ldr.w sl, [pc, #532] @ 8001cf4 8001ae0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff sensorsInfo.positionXWeak = 1; 8001ae4: 4f7a ldr r7, [pc, #488] @ (8001cd0 ) if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001ae6: f8da 0000 ldr.w r0, [sl] void LimiterSwitchTask (void* arg) { 8001aea: ed2d 8b04 vpush {d8-d9} 8001aee: b08d sub sp, #52 @ 0x34 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001af0: f00a f988 bl 800be04 8001af4: 2800 cmp r0, #0 8001af6: f000 80e2 beq.w 8001cbe void LimiterSwitchTask (void* arg) { 8001afa: 2300 movs r3, #0 osMutexRelease (sensorsInfoMutex); } while (pdTRUE) { osDelay (pdMS_TO_TICKS (100)); if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { sensorsInfo.limitXSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_13); 8001afc: 4d75 ldr r5, [pc, #468] @ (8001cd4 ) pinStates = (limitXSwitchDownPrevState << 1) | sensorsInfo.limitXSwitchDown; if ((pinStates & 0x3) == 0x1) { limiterXTriggered = 1; sensorsInfo.currentXPosition = 0; 8001afe: ed9f 9a76 vldr s18, [pc, #472] @ 8001cd8 void LimiterSwitchTask (void* arg) { 8001b02: 461c mov r4, r3 8001b04: 469b mov fp, r3 8001b06: 4698 mov r8, r3 8001b08: 4699 mov r9, r3 sensorsInfo.limitXSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_12); pinStates = (limitXSwitchUpPrevState << 1) | sensorsInfo.limitXSwitchUp; if ((pinStates & 0x3) == 0x1) { limiterXTriggered = 1; sensorsInfo.currentXPosition = 100; 8001b0a: eddf 8a74 vldr s17, [pc, #464] @ 8001cdc limitXSwitchUpPrevState = sensorsInfo.limitXSwitchUp; sensorsInfo.limitXSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_10); pinStates = (limitXSwitchCenterPrevState << 1) | sensorsInfo.limitXSwitchCenter; if ((pinStates & 0x3) == 0x1) { sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE; 8001b0e: ed9f 8a74 vldr s16, [pc, #464] @ 8001ce0 void LimiterSwitchTask (void* arg) { 8001b12: e9cd 3308 strd r3, r3, [sp, #32] osDelay (pdMS_TO_TICKS (100)); 8001b16: 2064 movs r0, #100 @ 0x64 8001b18: f00a f8ac bl 800bc74 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001b1c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001b20: f8da 0000 ldr.w r0, [sl] 8001b24: f00a f96e bl 800be04 8001b28: 4606 mov r6, r0 8001b2a: 2800 cmp r0, #0 8001b2c: d1f3 bne.n 8001b16 sensorsInfo.limitXSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_13); 8001b2e: f44f 5100 mov.w r1, #8192 @ 0x2000 8001b32: 4628 mov r0, r5 8001b34: f005 fb3c bl 80071b0 8001b38: 900a str r0, [sp, #40] @ 0x28 pinStates = (limitXSwitchDownPrevState << 1) | sensorsInfo.limitXSwitchDown; 8001b3a: ea40 0444 orr.w r4, r0, r4, lsl #1 sensorsInfo.limitXSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_13); 8001b3e: f887 0029 strb.w r0, [r7, #41] @ 0x29 if ((pinStates & 0x3) == 0x1) { 8001b42: f004 0303 and.w r3, r4, #3 8001b46: 2b01 cmp r3, #1 8001b48: 9307 str r3, [sp, #28] 8001b4a: f000 80b3 beq.w 8001cb4 8001b4e: 9607 str r6, [sp, #28] sensorsInfo.limitXSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_12); 8001b50: f44f 5180 mov.w r1, #4096 @ 0x1000 8001b54: 4628 mov r0, r5 8001b56: f005 fb2b bl 80071b0 8001b5a: 900b str r0, [sp, #44] @ 0x2c pinStates = (limitXSwitchUpPrevState << 1) | sensorsInfo.limitXSwitchUp; 8001b5c: ea40 0848 orr.w r8, r0, r8, lsl #1 sensorsInfo.limitXSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_12); 8001b60: f887 0028 strb.w r0, [r7, #40] @ 0x28 if ((pinStates & 0x3) == 0x1) { 8001b64: f008 0803 and.w r8, r8, #3 8001b68: f1b8 0f01 cmp.w r8, #1 8001b6c: d106 bne.n 8001b7c sensorsInfo.positionXWeak = 0; 8001b6e: 2300 movs r3, #0 limiterXTriggered = 1; 8001b70: f8cd 801c str.w r8, [sp, #28] sensorsInfo.currentXPosition = 100; 8001b74: edc7 8a0c vstr s17, [r7, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8001b78: f887 3038 strb.w r3, [r7, #56] @ 0x38 sensorsInfo.limitXSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_10); 8001b7c: f44f 6180 mov.w r1, #1024 @ 0x400 8001b80: 4628 mov r0, r5 8001b82: f005 fb15 bl 80071b0 8001b86: 4604 mov r4, r0 pinStates = (limitXSwitchCenterPrevState << 1) | sensorsInfo.limitXSwitchCenter; 8001b88: ea40 0949 orr.w r9, r0, r9, lsl #1 sensorsInfo.limitXSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_10); 8001b8c: f887 002a strb.w r0, [r7, #42] @ 0x2a if ((pinStates & 0x3) == 0x1) { 8001b90: f009 0903 and.w r9, r9, #3 8001b94: f1b9 0f01 cmp.w r9, #1 8001b98: d104 bne.n 8001ba4 sensorsInfo.positionXWeak = 0; 8001b9a: 2300 movs r3, #0 sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE; 8001b9c: ed87 8a0c vstr s16, [r7, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8001ba0: f887 3038 strb.w r3, [r7, #56] @ 0x38 } limitXSwitchCenterPrevState = sensorsInfo.limitXSwitchCenter; sensorsInfo.limitYSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_9); 8001ba4: f44f 7100 mov.w r1, #512 @ 0x200 8001ba8: 4628 mov r0, r5 8001baa: f005 fb01 bl 80071b0 8001bae: 4606 mov r6, r0 pinStates = (limitYSwitchDownPrevState << 1) | sensorsInfo.limitYSwitchDown; 8001bb0: ea40 0b4b orr.w fp, r0, fp, lsl #1 sensorsInfo.limitYSwitchDown = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_9); 8001bb4: f887 002c strb.w r0, [r7, #44] @ 0x2c if ((pinStates & 0x3) == 0x1) { 8001bb8: f00b 0b03 and.w fp, fp, #3 8001bbc: f1bb 0f01 cmp.w fp, #1 8001bc0: d072 beq.n 8001ca8 8001bc2: f04f 0b00 mov.w fp, #0 sensorsInfo.currentYPosition = 0; sensorsInfo.positionYWeak = 0; } limitYSwitchDownPrevState = sensorsInfo.limitYSwitchDown; sensorsInfo.limitYSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_11); 8001bc6: f44f 6100 mov.w r1, #2048 @ 0x800 8001bca: 4628 mov r0, r5 8001bcc: f005 faf0 bl 80071b0 pinStates = (limitYSwitchUpPrevState << 1) | sensorsInfo.limitYSwitchUp; 8001bd0: 9b09 ldr r3, [sp, #36] @ 0x24 sensorsInfo.limitYSwitchUp = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_11); 8001bd2: 4681 mov r9, r0 8001bd4: f887 002b strb.w r0, [r7, #43] @ 0x2b pinStates = (limitYSwitchUpPrevState << 1) | sensorsInfo.limitYSwitchUp; 8001bd8: ea40 0343 orr.w r3, r0, r3, lsl #1 8001bdc: f003 0303 and.w r3, r3, #3 if ((pinStates & 0x3) == 0x1) { 8001be0: 2b01 cmp r3, #1 8001be2: d105 bne.n 8001bf0 limiterYTriggered = 1; 8001be4: 469b mov fp, r3 sensorsInfo.currentYPosition = 100; sensorsInfo.positionYWeak = 0; 8001be6: 2300 movs r3, #0 sensorsInfo.currentYPosition = 100; 8001be8: edc7 8a0d vstr s17, [r7, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8001bec: f887 3039 strb.w r3, [r7, #57] @ 0x39 } limitYSwitchUpPrevState = sensorsInfo.limitYSwitchUp; sensorsInfo.limitYSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_8); 8001bf0: f44f 7180 mov.w r1, #256 @ 0x100 8001bf4: 4628 mov r0, r5 8001bf6: f005 fadb bl 80071b0 pinStates = (limitYSwitchCenterPrevState << 1) | sensorsInfo.limitYSwitchCenter; 8001bfa: 9b08 ldr r3, [sp, #32] sensorsInfo.limitYSwitchCenter = HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_8); 8001bfc: 4680 mov r8, r0 8001bfe: f887 002d strb.w r0, [r7, #45] @ 0x2d pinStates = (limitYSwitchCenterPrevState << 1) | sensorsInfo.limitYSwitchCenter; 8001c02: ea40 0343 orr.w r3, r0, r3, lsl #1 if ((pinStates & 0x3) == 0x1) { 8001c06: f003 0303 and.w r3, r3, #3 8001c0a: 2b01 cmp r3, #1 8001c0c: d104 bne.n 8001c18 sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE; sensorsInfo.positionYWeak = 0; 8001c0e: 2300 movs r3, #0 sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE; 8001c10: ed87 8a0d vstr s16, [r7, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8001c14: f887 3039 strb.w r3, [r7, #57] @ 0x39 } limitYSwitchCenterPrevState = sensorsInfo.limitYSwitchCenter; if (((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) && (limiterXTriggered == 1)) { 8001c18: f897 3029 ldrb.w r3, [r7, #41] @ 0x29 8001c1c: 2b01 cmp r3, #1 8001c1e: d017 beq.n 8001c50 8001c20: f897 2028 ldrb.w r2, [r7, #40] @ 0x28 8001c24: 2a01 cmp r2, #1 8001c26: d013 beq.n 8001c50 sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); } if (((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) && (limiterYTriggered == 1)) { 8001c28: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8001c2c: 2b01 cmp r3, #1 8001c2e: d026 beq.n 8001c7e 8001c30: f897 202b ldrb.w r2, [r7, #43] @ 0x2b 8001c34: 2a01 cmp r2, #1 8001c36: d022 beq.n 8001c7e sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); } limiterXTriggered = 0; limiterYTriggered = 0; osMutexRelease (sensorsInfoMutex); 8001c38: f8da 0000 ldr.w r0, [sl] limitYSwitchDownPrevState = sensorsInfo.limitYSwitchDown; 8001c3c: 46b3 mov fp, r6 limitYSwitchCenterPrevState = sensorsInfo.limitYSwitchCenter; 8001c3e: e9cd 8908 strd r8, r9, [sp, #32] limitXSwitchCenterPrevState = sensorsInfo.limitXSwitchCenter; 8001c42: 46a1 mov r9, r4 limitXSwitchUpPrevState = sensorsInfo.limitXSwitchUp; 8001c44: f8dd 802c ldr.w r8, [sp, #44] @ 0x2c limitXSwitchDownPrevState = sensorsInfo.limitXSwitchDown; 8001c48: 9c0a ldr r4, [sp, #40] @ 0x28 osMutexRelease (sensorsInfoMutex); 8001c4a: f00a f8ff bl 800be4c 8001c4e: e762 b.n 8001b16 if (((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) && (limiterXTriggered == 1)) { 8001c50: 9a07 ldr r2, [sp, #28] 8001c52: 2a01 cmp r2, #1 8001c54: d1e8 bne.n 8001c28 sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8001c56: 9304 str r3, [sp, #16] 8001c58: 2200 movs r2, #0 8001c5a: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 8001c5e: 4921 ldr r1, [pc, #132] @ (8001ce4 ) 8001c60: 9303 str r3, [sp, #12] 8001c62: 4b21 ldr r3, [pc, #132] @ (8001ce8 ) 8001c64: 4821 ldr r0, [pc, #132] @ (8001cec ) 8001c66: e9cd 2201 strd r2, r2, [sp, #4] 8001c6a: 681b ldr r3, [r3, #0] 8001c6c: 9300 str r3, [sp, #0] 8001c6e: 2304 movs r3, #4 8001c70: f000 f9f2 bl 8002058 if (((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) && (limiterYTriggered == 1)) { 8001c74: f897 302c ldrb.w r3, [r7, #44] @ 0x2c sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8001c78: 7538 strb r0, [r7, #20] if (((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) && (limiterYTriggered == 1)) { 8001c7a: 2b01 cmp r3, #1 8001c7c: d1d8 bne.n 8001c30 8001c7e: f1bb 0f01 cmp.w fp, #1 8001c82: d1d9 bne.n 8001c38 sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8001c84: 9304 str r3, [sp, #16] 8001c86: 2208 movs r2, #8 8001c88: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8001c8c: 4915 ldr r1, [pc, #84] @ (8001ce4 ) 8001c8e: 9303 str r3, [sp, #12] 8001c90: 2300 movs r3, #0 8001c92: 4816 ldr r0, [pc, #88] @ (8001cec ) 8001c94: e9cd 3301 strd r3, r3, [sp, #4] 8001c98: 4b15 ldr r3, [pc, #84] @ (8001cf0 ) 8001c9a: 681b ldr r3, [r3, #0] 8001c9c: 9300 str r3, [sp, #0] 8001c9e: 230c movs r3, #12 8001ca0: f000 f9da bl 8002058 8001ca4: 7578 strb r0, [r7, #21] 8001ca6: e7c7 b.n 8001c38 sensorsInfo.positionYWeak = 0; 8001ca8: 2300 movs r3, #0 sensorsInfo.currentYPosition = 0; 8001caa: ed87 9a0d vstr s18, [r7, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8001cae: f887 3039 strb.w r3, [r7, #57] @ 0x39 8001cb2: e788 b.n 8001bc6 sensorsInfo.positionXWeak = 0; 8001cb4: f887 6038 strb.w r6, [r7, #56] @ 0x38 sensorsInfo.currentXPosition = 0; 8001cb8: ed87 9a0c vstr s18, [r7, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8001cbc: e748 b.n 8001b50 sensorsInfo.positionXWeak = 1; 8001cbe: f240 1301 movw r3, #257 @ 0x101 osMutexRelease (sensorsInfoMutex); 8001cc2: f8da 0000 ldr.w r0, [sl] sensorsInfo.positionXWeak = 1; 8001cc6: 873b strh r3, [r7, #56] @ 0x38 osMutexRelease (sensorsInfoMutex); 8001cc8: f00a f8c0 bl 800be4c 8001ccc: e715 b.n 8001afa 8001cce: bf00 nop 8001cd0: 24000900 .word 0x24000900 8001cd4: 58020c00 .word 0x58020c00 8001cd8: 00000000 .word 0x00000000 8001cdc: 42c80000 .word 0x42c80000 8001ce0: 42480000 .word 0x42480000 8001ce4: 24000290 .word 0x24000290 8001ce8: 24000324 .word 0x24000324 8001cec: 24000500 .word 0x24000500 8001cf0: 240002f4 .word 0x240002f4 8001cf4: 24000980 .word 0x24000980 08001cf8 : } } } void EncoderTask (void* arg) { 8001cf8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} // 01 11 10 00 const uint32_t encoderStates[4] = { 0x00, 0x01, 0x03, 0x02 }; 8001cfc: 4b3c ldr r3, [pc, #240] @ (8001df0 ) void EncoderTask (void* arg) { 8001cfe: 4604 mov r4, r0 8001d00: ed2d 8b06 vpush {d8-d10} 8001d04: b086 sub sp, #24 const uint32_t encoderStates[4] = { 0x00, 0x01, 0x03, 0x02 }; 8001d06: cb0f ldmia r3, {r0, r1, r2, r3} 8001d08: ad06 add r5, sp, #24 8001d0a: e905 000f stmdb r5, {r0, r1, r2, r3} uint8_t step = 0; EncoderTaskArg* encoderTaskArg = (EncoderTaskArg*)arg; uint32_t pinStates = encoderTaskArg->initPinStates; 8001d0e: 68e5 ldr r5, [r4, #12] 8001d10: 9501 str r5, [sp, #4] for (uint8_t i = 0; i < 4; i++) { if (pinStates == encoderStates[i]) { 8001d12: b13d cbz r5, 8001d24 8001d14: 2d01 cmp r5, #1 8001d16: d005 beq.n 8001d24 8001d18: 2d03 cmp r5, #3 8001d1a: d063 beq.n 8001de4 for (uint8_t i = 0; i < 4; i++) { 8001d1c: 2d02 cmp r5, #2 8001d1e: bf14 ite ne 8001d20: 2500 movne r5, #0 8001d22: 2503 moveq r5, #3 8001d24: 4e33 ldr r6, [pc, #204] @ (8001df4 ) 8001d26: f105 0801 add.w r8, r5, #1 step--; } else { printf ("Forbidden\n"); } step = step % 4; *encoderTaskArg->pvEncoder = fmodf (encoderValue, 360.0); 8001d2a: eddf 8a33 vldr s17, [pc, #204] @ 8001df8 *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE; 8001d2e: ed9f aa33 vldr s20, [pc, #204] @ 8001dfc encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN; 8001d32: ed9f 9b2d vldr d9, [pc, #180] @ 8001de8 8001d36: e029 b.n 8001d8c } else if (encoderStates[(step - 1) % 4] == pinStates) { 8001d38: f850 3c10 ldr.w r3, [r0, #-16] encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN; 8001d3c: eeb7 7ac8 vcvt.f64.f32 d7, s16 printf ("Forbidden\n"); 8001d40: 482f ldr r0, [pc, #188] @ (8001e00 ) } else if (encoderStates[(step - 1) % 4] == pinStates) { 8001d42: 459c cmp ip, r3 encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN; 8001d44: ee37 7b49 vsub.f64 d7, d7, d9 } else if (encoderStates[(step - 1) % 4] == pinStates) { 8001d48: d149 bne.n 8001dde encoderValue -= 360.0 / ENCODER_X_IMP_PER_TURN; 8001d4a: eeb7 8bc7 vcvt.f32.f64 s16, d7 step = step % 4; 8001d4e: f001 0503 and.w r5, r1, #3 8001d52: f105 0801 add.w r8, r5, #1 if (encoderValue < 0) { 8001d56: eeb5 8ac0 vcmpe.f32 s16, #0.0 8001d5a: eef1 fa10 vmrs APSR_nzcv, fpscr 8001d5e: d501 bpl.n 8001d64 encoderValue = 360.0 + encoderValue; 8001d60: ee38 8a28 vadd.f32 s16, s16, s17 *encoderTaskArg->pvEncoder = fmodf (encoderValue, 360.0); 8001d64: eef0 0a68 vmov.f32 s1, s17 8001d68: eeb0 0a48 vmov.f32 s0, s16 8001d6c: f00f fd40 bl 80117f0 *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE; 8001d70: ee60 7a0a vmul.f32 s15, s0, s20 osMutexRelease (sensorsInfoMutex); 8001d74: 6830 ldr r0, [r6, #0] *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE; 8001d76: e9d4 3201 ldrd r3, r2, [r4, #4] *encoderTaskArg->pvEncoder = fmodf (encoderValue, 360.0); 8001d7a: ed82 0a00 vstr s0, [r2] *encoderTaskArg->currentPosition = 100 * (*encoderTaskArg->pvEncoder) / MAX_X_AXE_ANGLE; 8001d7e: edc3 7a00 vstr s15, [r3] osMutexRelease (sensorsInfoMutex); 8001d82: f00a f863 bl 800be4c } DbgLEDToggle (encoderTaskArg->dbgLed); 8001d86: 7820 ldrb r0, [r4, #0] 8001d88: f000 f938 bl 8001ffc float encoderValue = *encoderTaskArg->pvEncoder; 8001d8c: 68a7 ldr r7, [r4, #8] osMessageQueueGet (encoderTaskArg->dataQueue, &pinStates, 0, osWaitForever); 8001d8e: 2200 movs r2, #0 8001d90: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001d94: a901 add r1, sp, #4 8001d96: 6920 ldr r0, [r4, #16] float encoderValue = *encoderTaskArg->pvEncoder; 8001d98: ed97 8a00 vldr s16, [r7] osMessageQueueGet (encoderTaskArg->dataQueue, &pinStates, 0, osWaitForever); 8001d9c: f00a f8f0 bl 800bf80 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001da0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001da4: 6830 ldr r0, [r6, #0] 8001da6: f00a f82d bl 800be04 if (encoderStates[(step + 1) % 4] == pinStates) { 8001daa: f008 0203 and.w r2, r8, #3 } else if (encoderStates[(step - 1) % 4] == pinStates) { 8001dae: 1e69 subs r1, r5, #1 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8001db0: 2800 cmp r0, #0 8001db2: d1e8 bne.n 8001d86 } else if (encoderStates[(step - 1) % 4] == pinStates) { 8001db4: ab06 add r3, sp, #24 if (encoderStates[(step + 1) % 4] == pinStates) { 8001db6: f8dd c004 ldr.w ip, [sp, #4] } else if (encoderStates[(step - 1) % 4] == pinStates) { 8001dba: eb03 0081 add.w r0, r3, r1, lsl #2 if (encoderStates[(step + 1) % 4] == pinStates) { 8001dbe: eb03 0382 add.w r3, r3, r2, lsl #2 8001dc2: f853 3c10 ldr.w r3, [r3, #-16] 8001dc6: 4563 cmp r3, ip 8001dc8: d1b6 bne.n 8001d38 encoderValue += 360.0 / ENCODER_X_IMP_PER_TURN; 8001dca: eeb7 0ac8 vcvt.f64.f32 d0, s16 step = step % 4; 8001dce: b2d5 uxtb r5, r2 8001dd0: f102 0801 add.w r8, r2, #1 encoderValue += 360.0 / ENCODER_X_IMP_PER_TURN; 8001dd4: ee30 0b09 vadd.f64 d0, d0, d9 8001dd8: eeb7 8bc0 vcvt.f32.f64 s16, d0 8001ddc: e7c2 b.n 8001d64 printf ("Forbidden\n"); 8001dde: f00d fdb3 bl 800f948 8001de2: e7bf b.n 8001d64 for (uint8_t i = 0; i < 4; i++) { 8001de4: 2502 movs r5, #2 8001de6: e79d b.n 8001d24 8001de8: cccccccd .word 0xcccccccd 8001dec: 3fdccccc .word 0x3fdccccc 8001df0: 08011950 .word 0x08011950 8001df4: 24000980 .word 0x24000980 8001df8: 43b40000 .word 0x43b40000 8001dfc: 3e8e38e4 .word 0x3e8e38e4 8001e00: 08011a04 .word 0x08011a04 08001e04 : void MeasTasksInit (void) { 8001e04: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} vRefmVMutex = osMutexNew (NULL); 8001e08: 2000 movs r0, #0 void MeasTasksInit (void) { 8001e0a: b0ab sub sp, #172 @ 0xac vRefmVMutex = osMutexNew (NULL); 8001e0c: f009 ffb8 bl 800bd80 8001e10: 4b5e ldr r3, [pc, #376] @ (8001f8c ) 8001e12: 4602 mov r2, r0 resMeasurementsMutex = osMutexNew (NULL); 8001e14: 2000 movs r0, #0 osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001e16: f04f 0a24 mov.w sl, #36 @ 0x24 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001e1a: 2418 movs r4, #24 vRefmVMutex = osMutexNew (NULL); 8001e1c: 601a str r2, [r3, #0] resMeasurementsMutex = osMutexNew (NULL); 8001e1e: f009 ffaf bl 800bd80 8001e22: 4b5b ldr r3, [pc, #364] @ (8001f90 ) 8001e24: 4602 mov r2, r0 sensorsInfoMutex = osMutexNew (NULL); 8001e26: 2000 movs r0, #0 osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001e28: f44f 6880 mov.w r8, #1024 @ 0x400 resMeasurementsMutex = osMutexNew (NULL); 8001e2c: 601a str r2, [r3, #0] sensorsInfoMutex = osMutexNew (NULL); 8001e2e: f009 ffa7 bl 800bd80 8001e32: 4b58 ldr r3, [pc, #352] @ (8001f94 ) 8001e34: 4602 mov r2, r0 ILxRefMutex = osMutexNew (NULL); 8001e36: 2000 movs r0, #0 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001e38: f04f 0930 mov.w r9, #48 @ 0x30 sensorsInfoMutex = osMutexNew (NULL); 8001e3c: 601a str r2, [r3, #0] ILxRefMutex = osMutexNew (NULL); 8001e3e: f009 ff9f bl 800bd80 8001e42: 4b55 ldr r3, [pc, #340] @ (8001f98 ) adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001e44: 2200 movs r2, #0 8001e46: 2120 movs r1, #32 encoderXTaskArg.dbgLed = DBG_LED2; 8001e48: 4e54 ldr r6, [pc, #336] @ (8001f9c ) ILxRefMutex = osMutexNew (NULL); 8001e4a: 6018 str r0, [r3, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001e4c: 2008 movs r0, #8 8001e4e: f00a f81f bl 800be90 8001e52: 4b53 ldr r3, [pc, #332] @ (8001fa0 ) adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001e54: 2200 movs r2, #0 8001e56: 2120 movs r1, #32 adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001e58: 6018 str r0, [r3, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001e5a: 2008 movs r0, #8 8001e5c: f00a f818 bl 800be90 8001e60: 4b50 ldr r3, [pc, #320] @ (8001fa4 ) adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001e62: 2200 movs r2, #0 8001e64: 2120 movs r1, #32 adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001e66: 6018 str r0, [r3, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001e68: 2008 movs r0, #8 8001e6a: f00a f811 bl 800be90 8001e6e: 4b4e ldr r3, [pc, #312] @ (8001fa8 ) osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001e70: 4652 mov r2, sl 8001e72: 2100 movs r1, #0 adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001e74: 6018 str r0, [r3, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001e76: a806 add r0, sp, #24 8001e78: f00d fe46 bl 800fb08 osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001e7c: 4652 mov r2, sl 8001e7e: 2100 movs r1, #0 8001e80: a80f add r0, sp, #60 @ 0x3c 8001e82: f00d fe41 bl 800fb08 adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001e86: eb0d 0204 add.w r2, sp, r4 8001e8a: 2100 movs r1, #0 8001e8c: 4847 ldr r0, [pc, #284] @ (8001fac ) encoderXTaskArg.pvEncoder = &(sensorsInfo.pvEncoderX); 8001e8e: 4f48 ldr r7, [pc, #288] @ (8001fb0 ) encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8001e90: f8df b144 ldr.w fp, [pc, #324] @ 8001fd8 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001e94: e9cd 8414 strd r8, r4, [sp, #80] @ 0x50 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001e98: e9cd 890b strd r8, r9, [sp, #44] @ 0x2c adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001e9c: f009 fea6 bl 800bbec 8001ea0: 4b44 ldr r3, [pc, #272] @ (8001fb4 ) adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001ea2: aa0f add r2, sp, #60 @ 0x3c 8001ea4: 2100 movs r1, #0 adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001ea6: 6018 str r0, [r3, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001ea8: 4843 ldr r0, [pc, #268] @ (8001fb8 ) 8001eaa: f009 fe9f bl 800bbec 8001eae: 4b43 ldr r3, [pc, #268] @ (8001fbc ) osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001eb0: 4652 mov r2, sl 8001eb2: 2100 movs r1, #0 adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001eb4: 6018 str r0, [r3, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001eb6: a818 add r0, sp, #96 @ 0x60 8001eb8: f00d fe26 bl 800fb08 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001ebc: aa18 add r2, sp, #96 @ 0x60 8001ebe: 2100 movs r1, #0 8001ec0: 483f ldr r0, [pc, #252] @ (8001fc0 ) osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001ec2: 941e str r4, [sp, #120] @ 0x78 osMessageQueueAttr_t encoderMsgQueueAttr = { 0 }; 8001ec4: 2400 movs r4, #0 osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001ec6: f8cd 8074 str.w r8, [sp, #116] @ 0x74 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001eca: f009 fe8f bl 800bbec 8001ece: 4b3d ldr r3, [pc, #244] @ (8001fc4 ) encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001ed0: 466a mov r2, sp 8001ed2: 2104 movs r1, #4 encoderXTaskArg.pvEncoder = &(sensorsInfo.pvEncoderX); 8001ed4: 60b7 str r7, [r6, #8] limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001ed6: 6018 str r0, [r3, #0] encoderXTaskArg.dbgLed = DBG_LED2; 8001ed8: 2320 movs r3, #32 encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001eda: 2010 movs r0, #16 encoderXTaskArg.dbgLed = DBG_LED2; 8001edc: 8033 strh r3, [r6, #0] encoderXTaskArg.currentPosition = &(sensorsInfo.currentXPosition); 8001ede: eb07 030a add.w r3, r7, sl osMessageQueueAttr_t encoderMsgQueueAttr = { 0 }; 8001ee2: e9cd 4400 strd r4, r4, [sp] encoderXTaskArg.currentPosition = &(sensorsInfo.currentXPosition); 8001ee6: 6073 str r3, [r6, #4] osMessageQueueAttr_t encoderMsgQueueAttr = { 0 }; 8001ee8: e9cd 4402 strd r4, r4, [sp, #8] 8001eec: e9cd 4404 strd r4, r4, [sp, #16] encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001ef0: f009 ffce bl 800be90 encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8001ef4: f44f 4100 mov.w r1, #32768 @ 0x8000 encoderXTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001ef8: 6130 str r0, [r6, #16] encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8001efa: 4658 mov r0, fp 8001efc: f005 f958 bl 80071b0 8001f00: 4605 mov r5, r0 8001f02: f44f 4180 mov.w r1, #16384 @ 0x4000 8001f06: 4658 mov r0, fp 8001f08: f005 f952 bl 80071b0 encoderYTaskArg.dbgLed = DBG_LED3; 8001f0c: 2340 movs r3, #64 @ 0x40 encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8001f0e: ea40 0045 orr.w r0, r0, r5, lsl #1 encoderYTaskArg.dbgLed = DBG_LED3; 8001f12: 4d2d ldr r5, [pc, #180] @ (8001fc8 ) encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8001f14: f5ab 6b00 sub.w fp, fp, #2048 @ 0x800 encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001f18: 466a mov r2, sp encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8001f1a: f000 0003 and.w r0, r0, #3 encoderYTaskArg.dbgLed = DBG_LED3; 8001f1e: 802b strh r3, [r5, #0] encoderYTaskArg.pvEncoder = &(sensorsInfo.pvEncoderY); 8001f20: 1d3b adds r3, r7, #4 encoderYTaskArg.currentPosition = &(sensorsInfo.currentYPosition); 8001f22: 3728 adds r7, #40 @ 0x28 encoderXTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_15) << 1) | HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_14)) & 0x3; 8001f24: 60f0 str r0, [r6, #12] encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001f26: 2104 movs r1, #4 8001f28: 2010 movs r0, #16 encoderYTaskArg.pvEncoder = &(sensorsInfo.pvEncoderY); 8001f2a: 60ab str r3, [r5, #8] encoderYTaskArg.currentPosition = &(sensorsInfo.currentYPosition); 8001f2c: 606f str r7, [r5, #4] encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001f2e: f009 ffaf bl 800be90 encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8001f32: f44f 6100 mov.w r1, #2048 @ 0x800 encoderYTaskArg.dataQueue = osMessageQueueNew (16, sizeof (uint32_t), &encoderMsgQueueAttr); 8001f36: 6128 str r0, [r5, #16] encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8001f38: 4658 mov r0, fp 8001f3a: f005 f939 bl 80071b0 8001f3e: 4607 mov r7, r0 8001f40: 4641 mov r1, r8 8001f42: 4658 mov r0, fp 8001f44: f005 f934 bl 80071b0 osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8001f48: 4621 mov r1, r4 encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8001f4a: ea40 0047 orr.w r0, r0, r7, lsl #1 encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask); 8001f4e: 4c1f ldr r4, [pc, #124] @ (8001fcc ) osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8001f50: 4652 mov r2, sl encoderYTaskArg.initPinStates = ((HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_11) << 1) | HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_10)) & 0x3; 8001f52: f000 0003 and.w r0, r0, #3 8001f56: 60e8 str r0, [r5, #12] osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8001f58: a821 add r0, sp, #132 @ 0x84 8001f5a: f00d fdd5 bl 800fb08 encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask); 8001f5e: 4631 mov r1, r6 8001f60: aa21 add r2, sp, #132 @ 0x84 8001f62: 4620 mov r0, r4 osThreadAttrEncoderTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f64: f8cd 8098 str.w r8, [sp, #152] @ 0x98 osThreadAttrEncoderTask.priority = (osPriority_t)osPriorityRealtime; 8001f68: f8cd 909c str.w r9, [sp, #156] @ 0x9c encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask); 8001f6c: f009 fe3e bl 800bbec 8001f70: 4b17 ldr r3, [pc, #92] @ (8001fd0 ) 8001f72: 4606 mov r6, r0 encoderYTaskHandle = osThreadNew (EncoderTask, &encoderYTaskArg, &osThreadAttrEncoderTask); 8001f74: aa21 add r2, sp, #132 @ 0x84 8001f76: 4629 mov r1, r5 8001f78: 4620 mov r0, r4 encoderXTaskHandle = osThreadNew (EncoderTask, &encoderXTaskArg, &osThreadAttrEncoderTask); 8001f7a: 601e str r6, [r3, #0] encoderYTaskHandle = osThreadNew (EncoderTask, &encoderYTaskArg, &osThreadAttrEncoderTask); 8001f7c: f009 fe36 bl 800bbec 8001f80: 4b14 ldr r3, [pc, #80] @ (8001fd4 ) 8001f82: 6018 str r0, [r3, #0] } 8001f84: b02b add sp, #172 @ 0xac 8001f86: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8001f8a: bf00 nop 8001f8c: 24000988 .word 0x24000988 8001f90: 24000984 .word 0x24000984 8001f94: 24000980 .word 0x24000980 8001f98: 2400097c .word 0x2400097c 8001f9c: 240008e0 .word 0x240008e0 8001fa0: 24000994 .word 0x24000994 8001fa4: 24000990 .word 0x24000990 8001fa8: 2400098c .word 0x2400098c 8001fac: 080018d9 .word 0x080018d9 8001fb0: 2400090c .word 0x2400090c 8001fb4: 240009a8 .word 0x240009a8 8001fb8: 08001511 .word 0x08001511 8001fbc: 240009a4 .word 0x240009a4 8001fc0: 08001ad9 .word 0x08001ad9 8001fc4: 240009a0 .word 0x240009a0 8001fc8: 240008c0 .word 0x240008c0 8001fcc: 08001cf9 .word 0x08001cf9 8001fd0: 2400099c .word 0x2400099c 8001fd4: 24000998 .word 0x24000998 8001fd8: 58020c00 .word 0x58020c00 08001fdc : #include #include "peripherial.h" void DbgLEDOn (uint8_t ledNumber) { 8001fdc: 4601 mov r1, r0 HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET); 8001fde: 2201 movs r2, #1 8001fe0: 4801 ldr r0, [pc, #4] @ (8001fe8 ) 8001fe2: f005 b8eb b.w 80071bc 8001fe6: bf00 nop 8001fe8: 58020c00 .word 0x58020c00 08001fec : } void DbgLEDOff (uint8_t ledNumber) { 8001fec: 4601 mov r1, r0 HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET); 8001fee: 2200 movs r2, #0 8001ff0: 4801 ldr r0, [pc, #4] @ (8001ff8 ) 8001ff2: f005 b8e3 b.w 80071bc 8001ff6: bf00 nop 8001ff8: 58020c00 .word 0x58020c00 08001ffc : } void DbgLEDToggle (uint8_t ledNumber) { 8001ffc: 4601 mov r1, r0 HAL_GPIO_TogglePin (GPIOD, ledNumber); 8001ffe: 4801 ldr r0, [pc, #4] @ (8002004 ) 8002000: f005 b8e0 b.w 80071c4 8002004: 58020c00 .word 0x58020c00 08002008 : } void EnableCurrentSensors (void) { HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 8002008: 2201 movs r2, #1 800200a: f44f 4100 mov.w r1, #32768 @ 0x8000 800200e: 4801 ldr r0, [pc, #4] @ (8002014 ) 8002010: f005 b8d4 b.w 80071bc 8002014: 58021000 .word 0x58021000 08002018 : HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { uint8_t gpioOffset = 0; switch (sensor) { 8002018: 2802 cmp r0, #2 800201a: d900 bls.n 800201e 800201c: 4770 bx lr case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; } if (gpioOffset > 0) { uint16_t gain0Gpio = 1 << gpioOffset; 800201e: 4b0c ldr r3, [pc, #48] @ (8002050 ) void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { 8002020: b570 push {r4, r5, r6, lr} uint16_t gain0Gpio = 1 << gpioOffset; 8002022: 2501 movs r5, #1 8002024: 5c1e ldrb r6, [r3, r0] uint16_t gain1Gpio = 1 << (gpioOffset + 1); uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8002026: 460c mov r4, r1 HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 8002028: 480a ldr r0, [pc, #40] @ (8002054 ) uint16_t gain0Gpio = 1 << gpioOffset; 800202a: fa05 f106 lsl.w r1, r5, r6 uint16_t gain1Gpio = 1 << (gpioOffset + 1); 800202e: 442e add r6, r5 HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 8002030: ea04 0205 and.w r2, r4, r5 8002034: b289 uxth r1, r1 8002036: f005 f8c1 bl 80071bc uint16_t gain1Gpio = 1 << (gpioOffset + 1); 800203a: fa05 f106 lsl.w r1, r5, r6 gpioState = (((uint16_t)gain) >> 1) & 0x0001; HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 800203e: f3c4 0240 ubfx r2, r4, #1, #1 8002042: 4804 ldr r0, [pc, #16] @ (8002054 ) 8002044: b289 uxth r1, r1 } } 8002046: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 800204a: f005 b8b7 b.w 80071bc 800204e: bf00 nop 8002050: 08011a10 .word 0x08011a10 8002054: 58021000 .word 0x58021000 08002058 : uint8_t MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8002058: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 800205c: 461f mov r7, r3 800205e: 4604 mov r4, r0 8002060: f8dd 9030 ldr.w r9, [sp, #48] @ 0x30 8002064: 460d mov r5, r1 uint32_t motorStatus = 0; MotorDriverState setMotorState = HiZ; HAL_TIM_PWM_Stop (htim, channel1); 8002066: 4611 mov r1, r2 MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8002068: 4690 mov r8, r2 800206a: 9e0b ldr r6, [sp, #44] @ 0x2c 800206c: f89d a034 ldrb.w sl, [sp, #52] @ 0x34 8002070: f89d b038 ldrb.w fp, [sp, #56] @ 0x38 HAL_TIM_PWM_Stop (htim, channel1); 8002074: f007 fef0 bl 8009e58 HAL_TIM_PWM_Stop (htim, channel2); 8002078: 4639 mov r1, r7 800207a: 4620 mov r0, r4 800207c: f007 feec bl 8009e58 if (motorTimerPeriod > 0) { 8002080: f1b9 0f00 cmp.w r9, #0 8002084: dd4a ble.n 800211c if (motorPWMPulse > 0) { 8002086: 2e00 cmp r6, #0 8002088: dd20 ble.n 80020cc // Forward if (switchLimiterUpStat == 0) { 800208a: f1ba 0f00 cmp.w sl, #0 800208e: d14f bne.n 8002130 setMotorState = Forward; MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002090: eb06 0686 add.w r6, r6, r6, lsl #2 switch (setState) { case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002094: 4642 mov r2, r8 8002096: 4629 mov r1, r5 8002098: 4620 mov r0, r4 MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800209a: 0076 lsls r6, r6, #1 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800209c: f8c5 a008 str.w sl, [r5, #8] timerConf->Pulse = pulse; 80020a0: 606e str r6, [r5, #4] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80020a2: f008 f93b bl 800a31c 80020a6: 2800 cmp r0, #0 80020a8: f040 80ba bne.w 8002220 Error_Handler (); } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80020ac: 2300 movs r3, #0 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80020ae: 4629 mov r1, r5 80020b0: 463a mov r2, r7 80020b2: 4620 mov r0, r4 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80020b4: 60ab str r3, [r5, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80020b6: f008 f931 bl 800a31c 80020ba: 2800 cmp r0, #0 80020bc: f040 80ad bne.w 800221a HAL_TIM_PWM_Start (htim, channel1); 80020c0: 4641 mov r1, r8 80020c2: 4620 mov r0, r4 80020c4: 2501 movs r5, #1 80020c6: f007 fe27 bl 8009d18 motorStatus = 1; 80020ca: e036 b.n 800213a } else if (motorPWMPulse < 0) { 80020cc: d066 beq.n 800219c if (switchLimiterDownStat == 0) { 80020ce: f1bb 0f00 cmp.w fp, #0 80020d2: f040 809c bne.w 800220e MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80020d6: f06f 0309 mvn.w r3, #9 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80020da: 4642 mov r2, r8 80020dc: 4629 mov r1, r5 80020de: 4620 mov r0, r4 MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80020e0: fb06 f303 mul.w r3, r6, r3 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80020e4: f8c5 b008 str.w fp, [r5, #8] timerConf->Pulse = pulse; 80020e8: 606b str r3, [r5, #4] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80020ea: f008 f917 bl 800a31c 80020ee: 2800 cmp r0, #0 80020f0: f040 80ce bne.w 8002290 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80020f4: 2300 movs r3, #0 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80020f6: 4629 mov r1, r5 80020f8: 463a mov r2, r7 80020fa: 4620 mov r0, r4 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80020fc: 60ab str r3, [r5, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80020fe: f008 f90d bl 800a31c 8002102: 2800 cmp r0, #0 8002104: f040 80c1 bne.w 800228a HAL_TIM_PWM_Start (htim, channel2); 8002108: 2501 movs r5, #1 800210a: 4639 mov r1, r7 800210c: 4620 mov r0, r4 800210e: f007 fe03 bl 8009d18 HAL_TIM_PWM_Stop (htim, channel1); 8002112: 4641 mov r1, r8 8002114: 4620 mov r0, r4 8002116: f007 fe9f bl 8009e58 800211a: e012 b.n 8002142 } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 800211c: ea59 0306 orrs.w r3, r9, r6 8002120: d059 beq.n 80021d6 } else if (motorTimerPeriod == -1) { 8002122: f1b9 3fff cmp.w r9, #4294967295 @ 0xffffffff 8002126: d016 beq.n 8002156 HAL_TIM_PWM_Stop (htim, channel2); 8002128: 2500 movs r5, #0 } 800212a: 4628 mov r0, r5 800212c: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} HAL_TIM_PWM_Stop (htim, channel1); 8002130: 2500 movs r5, #0 8002132: 4641 mov r1, r8 8002134: 4620 mov r0, r4 8002136: f007 fe8f bl 8009e58 HAL_TIM_PWM_Stop (htim, channel2); 800213a: 4639 mov r1, r7 800213c: 4620 mov r0, r4 800213e: f007 fe8b bl 8009e58 osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 8002142: f44f 717a mov.w r1, #1000 @ 0x3e8 8002146: 980a ldr r0, [sp, #40] @ 0x28 8002148: fb01 f109 mul.w r1, r1, r9 800214c: f009 fde0 bl 800bd10 } 8002150: 4628 mov r0, r5 8002152: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} if (motorPWMPulse > 0) { 8002156: 2e00 cmp r6, #0 8002158: dd75 ble.n 8002246 if (switchLimiterUpStat == 0) { 800215a: f1ba 0f00 cmp.w sl, #0 800215e: d162 bne.n 8002226 MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002160: eb06 0686 add.w r6, r6, r6, lsl #2 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002164: 4642 mov r2, r8 8002166: 4629 mov r1, r5 8002168: 4620 mov r0, r4 MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800216a: 0076 lsls r6, r6, #1 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800216c: f8c5 a008 str.w sl, [r5, #8] timerConf->Pulse = pulse; 8002170: 606e str r6, [r5, #4] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002172: f008 f8d3 bl 800a31c 8002176: 2800 cmp r0, #0 8002178: f040 809c bne.w 80022b4 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800217c: 2300 movs r3, #0 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 800217e: 463a mov r2, r7 8002180: 4629 mov r1, r5 8002182: 4620 mov r0, r4 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002184: 60ab str r3, [r5, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002186: f008 f8c9 bl 800a31c 800218a: 2800 cmp r0, #0 800218c: f040 808f bne.w 80022ae HAL_TIM_PWM_Start (htim, channel1); 8002190: 4641 mov r1, r8 8002192: 4620 mov r0, r4 8002194: 2501 movs r5, #1 8002196: f007 fdbf bl 8009d18 motorStatus = 1; 800219a: e049 b.n 8002230 timerConf->Pulse = pulse; 800219c: 2302 movs r3, #2 Error_Handler (); } break; case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800219e: 4642 mov r2, r8 80021a0: 4629 mov r1, r5 80021a2: 4620 mov r0, r4 timerConf->Pulse = pulse; 80021a4: 606e str r6, [r5, #4] 80021a6: 60ab str r3, [r5, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80021a8: f008 f8b8 bl 800a31c 80021ac: 2800 cmp r0, #0 80021ae: d175 bne.n 800229c Error_Handler (); } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80021b0: 2302 movs r3, #2 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80021b2: 4629 mov r1, r5 80021b4: 463a mov r2, r7 80021b6: 4620 mov r0, r4 timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80021b8: 60ab str r3, [r5, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80021ba: f008 f8af bl 800a31c 80021be: 2800 cmp r0, #0 80021c0: d169 bne.n 8002296 HAL_TIM_PWM_Start (htim, channel1); 80021c2: 4641 mov r1, r8 80021c4: 4620 mov r0, r4 80021c6: f007 fda7 bl 8009d18 HAL_TIM_PWM_Start (htim, channel2); 80021ca: 4639 mov r1, r7 80021cc: 4620 mov r0, r4 80021ce: 2500 movs r5, #0 80021d0: f007 fda2 bl 8009d18 motorStatus = 0; 80021d4: e7b5 b.n 8002142 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80021d6: 4642 mov r2, r8 80021d8: 4629 mov r1, r5 80021da: 4620 mov r0, r4 timerConf->Pulse = pulse; 80021dc: e9c5 3301 strd r3, r3, [r5, #4] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80021e0: f008 f89c bl 800a31c 80021e4: bb60 cbnz r0, 8002240 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80021e6: 2300 movs r3, #0 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80021e8: 463a mov r2, r7 80021ea: 4629 mov r1, r5 80021ec: 4620 mov r0, r4 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80021ee: 60ab str r3, [r5, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80021f0: f008 f894 bl 800a31c 80021f4: bb08 cbnz r0, 800223a HAL_TIM_PWM_Stop (htim, channel1); 80021f6: 4641 mov r1, r8 80021f8: 4620 mov r0, r4 80021fa: f007 fe2d bl 8009e58 HAL_TIM_PWM_Stop (htim, channel2); 80021fe: 4639 mov r1, r7 8002200: 4620 mov r0, r4 8002202: f007 fe29 bl 8009e58 osTimerStop (motorTimerHandle); 8002206: 980a ldr r0, [sp, #40] @ 0x28 8002208: f009 fd9a bl 800bd40 motorStatus = 0; 800220c: e78c b.n 8002128 HAL_TIM_PWM_Stop (htim, channel2); 800220e: 4639 mov r1, r7 8002210: 4620 mov r0, r4 8002212: 2500 movs r5, #0 8002214: f007 fe20 bl 8009e58 8002218: e77b b.n 8002112 Error_Handler (); 800221a: f7fe faed bl 80007f8 800221e: e74f b.n 80020c0 Error_Handler (); 8002220: f7fe faea bl 80007f8 8002224: e742 b.n 80020ac HAL_TIM_PWM_Stop (htim, channel1); 8002226: 4641 mov r1, r8 8002228: 4620 mov r0, r4 800222a: 2500 movs r5, #0 800222c: f007 fe14 bl 8009e58 HAL_TIM_PWM_Stop (htim, channel2); 8002230: 4639 mov r1, r7 8002232: 4620 mov r0, r4 8002234: f007 fe10 bl 8009e58 8002238: e777 b.n 800212a Error_Handler (); 800223a: f7fe fadd bl 80007f8 800223e: e7da b.n 80021f6 Error_Handler (); 8002240: f7fe fada bl 80007f8 8002244: e7cf b.n 80021e6 if (switchLimiterDownStat == 0) { 8002246: f1bb 0f00 cmp.w fp, #0 800224a: d12a bne.n 80022a2 MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800224c: f06f 0309 mvn.w r3, #9 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002250: 4642 mov r2, r8 8002252: 4629 mov r1, r5 8002254: 4620 mov r0, r4 MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 8002256: fb03 f606 mul.w r6, r3, r6 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800225a: f8c5 b008 str.w fp, [r5, #8] timerConf->Pulse = pulse; 800225e: 606e str r6, [r5, #4] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8002260: f008 f85c bl 800a31c 8002264: bb60 cbnz r0, 80022c0 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002266: 2300 movs r3, #0 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002268: 463a mov r2, r7 800226a: 4629 mov r1, r5 800226c: 4620 mov r0, r4 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800226e: 60ab str r3, [r5, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002270: f008 f854 bl 800a31c 8002274: bb08 cbnz r0, 80022ba HAL_TIM_PWM_Start (htim, channel2); 8002276: 4639 mov r1, r7 8002278: 4620 mov r0, r4 800227a: 2501 movs r5, #1 800227c: f007 fd4c bl 8009d18 HAL_TIM_PWM_Stop (htim, channel1); 8002280: 4641 mov r1, r8 8002282: 4620 mov r0, r4 8002284: f007 fde8 bl 8009e58 8002288: e74f b.n 800212a Error_Handler (); 800228a: f7fe fab5 bl 80007f8 800228e: e73b b.n 8002108 Error_Handler (); 8002290: f7fe fab2 bl 80007f8 8002294: e72e b.n 80020f4 Error_Handler (); 8002296: f7fe faaf bl 80007f8 800229a: e792 b.n 80021c2 Error_Handler (); 800229c: f7fe faac bl 80007f8 80022a0: e786 b.n 80021b0 HAL_TIM_PWM_Stop (htim, channel2); 80022a2: 4639 mov r1, r7 80022a4: 4620 mov r0, r4 80022a6: 2500 movs r5, #0 80022a8: f007 fdd6 bl 8009e58 80022ac: e7e8 b.n 8002280 Error_Handler (); 80022ae: f7fe faa3 bl 80007f8 80022b2: e76d b.n 8002190 Error_Handler (); 80022b4: f7fe faa0 bl 80007f8 80022b8: e760 b.n 800217c Error_Handler (); 80022ba: f7fe fa9d bl 80007f8 80022be: e7da b.n 8002276 Error_Handler (); 80022c0: f7fe fa9a bl 80007f8 80022c4: e7cf b.n 8002266 80022c6: bf00 nop 080022c8 : void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 80022c8: b570 push {r4, r5, r6, lr} 80022ca: f89d c010 ldrb.w ip, [sp, #16] 80022ce: 461d mov r5, r3 timerConf->Pulse = pulse; 80022d0: 9b05 ldr r3, [sp, #20] void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 80022d2: 4606 mov r6, r0 switch (setState) { 80022d4: f1bc 0f02 cmp.w ip, #2 void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 80022d8: 460c mov r4, r1 timerConf->Pulse = pulse; 80022da: 604b str r3, [r1, #4] switch (setState) { 80022dc: d913 bls.n 8002306 80022de: f1bc 0f03 cmp.w ip, #3 80022e2: d110 bne.n 8002306 timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80022e4: 2302 movs r3, #2 80022e6: 608b str r3, [r1, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80022e8: f008 f818 bl 800a31c 80022ec: b9e8 cbnz r0, 800232a timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80022ee: 2302 movs r3, #2 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80022f0: 462a mov r2, r5 80022f2: 4621 mov r1, r4 80022f4: 4630 mov r0, r6 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80022f6: 60a3 str r3, [r4, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80022f8: f008 f810 bl 800a31c 80022fc: b188 cbz r0, 8002322 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { Error_Handler (); } break; } } 80022fe: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} Error_Handler (); 8002302: f7fe ba79 b.w 80007f8 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002306: 2300 movs r3, #0 8002308: 60a3 str r3, [r4, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800230a: f008 f807 bl 800a31c 800230e: b948 cbnz r0, 8002324 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002310: 2300 movs r3, #0 if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8002312: 462a mov r2, r5 8002314: 4621 mov r1, r4 8002316: 4630 mov r0, r6 timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8002318: 60a3 str r3, [r4, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 800231a: f007 ffff bl 800a31c 800231e: 2800 cmp r0, #0 8002320: d1ed bne.n 80022fe } 8002322: bd70 pop {r4, r5, r6, pc} Error_Handler (); 8002324: f7fe fa68 bl 80007f8 8002328: e7f2 b.n 8002310 Error_Handler (); 800232a: f7fe fa65 bl 80007f8 timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 800232e: 2302 movs r3, #2 8002330: e7de b.n 80022f0 8002332: bf00 nop 08002334 : positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); } void PositionControlTask (void* argument) { 8002334: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8002338: ed2d 8b04 vpush {d8-d9} 800233c: b091 sub sp, #68 @ 0x44 const int32_t PositionControlTaskTimeOut = 100; PositionControlTaskInitArg* posCtrlTaskArg = (PositionControlTaskInitArg*)argument; PositionControlTaskData posCtrlData __attribute__ ((aligned (32))) = { 0 }; 800233e: eddf 7aac vldr s15, [pc, #688] @ 80025f0 int32_t sign = 0; MovementPhases movementPhase = idlePhase; float startPosition = 0; float prevPosition = 0; int32_t timeLeftMS = 0; int32_t moveCmdTimeoutCounter = 0; 8002342: f04f 0800 mov.w r8, #0 int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE; 8002346: 233c movs r3, #60 @ 0x3c void PositionControlTask (void* argument) { 8002348: f10d 043f add.w r4, sp, #63 @ 0x3f float prevPosition = 0; 800234c: eeb0 9a67 vmov.f32 s18, s15 float startPosition = 0; 8002350: eeb0 8a67 vmov.f32 s16, s15 int32_t timeLeftMS = 0; 8002354: 46c2 mov sl, r8 void PositionControlTask (void* argument) { 8002356: f024 041f bic.w r4, r4, #31 800235a: 4605 mov r5, r0 MovementPhases movementPhase = idlePhase; 800235c: 4647 mov r7, r8 int32_t sign = 0; 800235e: 46c3 mov fp, r8 8002360: 4ea4 ldr r6, [pc, #656] @ (80025f4 ) 8002362: f8df 9294 ldr.w r9, [pc, #660] @ 80025f8 PositionControlTaskData posCtrlData __attribute__ ((aligned (32))) = { 0 }; 8002366: edc4 7a00 vstr s15, [r4] int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE; 800236a: 9307 str r3, [sp, #28] while (pdTRUE) { queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 800236c: 2364 movs r3, #100 @ 0x64 800236e: 2200 movs r2, #0 8002370: 4621 mov r1, r4 8002372: 6928 ldr r0, [r5, #16] 8002374: f009 fe04 bl 800bf80 if (queueSatus == osOK) { 8002378: bb28 cbnz r0, 80023c6 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800237a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800237e: 6830 ldr r0, [r6, #0] 8002380: f009 fd40 bl 800be04 8002384: 2800 cmp r0, #0 8002386: d1f1 bne.n 800236c float posDiff = posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition; 8002388: 6a2b ldr r3, [r5, #32] 800238a: edd4 7a00 vldr s15, [r4] 800238e: ed93 7a00 vldr s14, [r3] 8002392: ee77 7ac7 vsub.f32 s15, s15, s14 if (posDiff != 0) { 8002396: eef5 7a40 vcmp.f32 s15, #0.0 800239a: eef1 fa10 vmrs APSR_nzcv, fpscr 800239e: d00a beq.n 80023b6 sign = posDiff > 0 ? 1 : -1; 80023a0: eef5 7ac0 vcmpe.f32 s15, #0.0 startPosition = *posCtrlTaskArg->currentPosition; movementPhase = startPhase; moveCmdTimeoutCounter = 0; 80023a4: 4680 mov r8, r0 sign = posDiff > 0 ? 1 : -1; 80023a6: eef1 fa10 vmrs APSR_nzcv, fpscr 80023aa: dd4a ble.n 8002442 movementPhase = startPhase; 80023ac: 2701 movs r7, #1 startPosition = *posCtrlTaskArg->currentPosition; 80023ae: eeb0 8a47 vmov.f32 s16, s14 timeLeftMS = 0; 80023b2: 4682 mov sl, r0 sign = posDiff > 0 ? 1 : -1; 80023b4: 46bb mov fp, r7 #ifdef DBG_POSITION printf ("Axe %c start phase\n", posCtrlTaskArg->axe); #endif } osMutexRelease (sensorsInfoMutex); 80023b6: 6830 ldr r0, [r6, #0] 80023b8: f009 fd48 bl 800be4c // if (osMutexAcquire (positionSettingMutex, osWaitForever) == osOK) { *positionXControlTaskInitArg.positionSetting = posCtrlData.positionSettingValue; 80023bc: 6822 ldr r2, [r4, #0] 80023be: f8d9 3024 ldr.w r3, [r9, #36] @ 0x24 80023c2: 601a str r2, [r3, #0] 80023c4: e7d2 b.n 800236c // osMutexRelease (positionSettingMutex); // } } } else if (queueSatus == osErrorTimeout) { 80023c6: 3002 adds r0, #2 80023c8: d1d0 bne.n 800236c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80023ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80023ce: 6830 ldr r0, [r6, #0] 80023d0: f009 fd18 bl 800be04 80023d4: 2800 cmp r0, #0 80023d6: d1c9 bne.n 800236c if (((*posCtrlTaskArg->motorStatus != 0) && (movementPhase != idlePhase)) || (movementPhase == startPhase) ) { 80023d8: 6aab ldr r3, [r5, #40] @ 0x28 80023da: 781b ldrb r3, [r3, #0] 80023dc: 2b00 cmp r3, #0 80023de: d037 beq.n 8002450 80023e0: b35f cbz r7, 800243a if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 80023e2: e9d5 1c05 ldrd r1, ip, [r5, #20] 80023e6: f89c 2000 ldrb.w r2, [ip] 80023ea: 780b ldrb r3, [r1, #0] 80023ec: 2a01 cmp r2, #1 80023ee: d03d beq.n 800246c 80023f0: 2b01 cmp r3, #1 80023f2: d061 beq.n 80024b8 #endif } timeLeftMS += PositionControlTaskTimeOut; if (prevPosition == *posCtrlTaskArg->currentPosition) { 80023f4: 6a28 ldr r0, [r5, #32] timeLeftMS += PositionControlTaskTimeOut; 80023f6: f10a 0a64 add.w sl, sl, #100 @ 0x64 if (prevPosition == *posCtrlTaskArg->currentPosition) { 80023fa: edd0 8a00 vldr s17, [r0] 80023fe: eef4 8a49 vcmp.f32 s17, s18 8002402: eef1 fa10 vmrs APSR_nzcv, fpscr 8002406: d127 bne.n 8002458 moveCmdTimeoutCounter += PositionControlTaskTimeOut; 8002408: f108 0864 add.w r8, r8, #100 @ 0x64 } else { moveCmdTimeoutCounter = 0; } prevPosition = *posCtrlTaskArg->currentPosition; if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 800240c: f241 3088 movw r0, #5000 @ 0x1388 8002410: 4580 cmp r8, r0 8002412: f340 80dd ble.w 80025d0 movementPhase = idlePhase; motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8002416: f89c 3000 ldrb.w r3, [ip] 800241a: 9304 str r3, [sp, #16] 800241c: 780b ldrb r3, [r1, #0] 800241e: 9303 str r3, [sp, #12] #endif break; case stopPhase: float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue; if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8002420: 2700 movs r7, #0 8002422: e9cd 7701 strd r7, r7, [sp, #4] 8002426: 68eb ldr r3, [r5, #12] 8002428: 9300 str r3, [sp, #0] 800242a: 7a6b ldrb r3, [r5, #9] 800242c: 7a2a ldrb r2, [r5, #8] 800242e: e9d5 0100 ldrd r0, r1, [r5] 8002432: f7ff fe11 bl 8002058 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); *posCtrlTaskArg->motorStatus = motorStatus; 8002436: 6aab ldr r3, [r5, #40] @ 0x28 8002438: 7018 strb r0, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } } osMutexRelease (sensorsInfoMutex); 800243a: 6830 ldr r0, [r6, #0] 800243c: f009 fd06 bl 800be4c 8002440: e794 b.n 800236c startPosition = *posCtrlTaskArg->currentPosition; 8002442: eeb0 8a47 vmov.f32 s16, s14 movementPhase = startPhase; 8002446: 2701 movs r7, #1 sign = posDiff > 0 ? 1 : -1; 8002448: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff timeLeftMS = 0; 800244c: 4682 mov sl, r0 800244e: e7b2 b.n 80023b6 if (((*posCtrlTaskArg->motorStatus != 0) && (movementPhase != idlePhase)) || (movementPhase == startPhase) ) { 8002450: 2f01 cmp r7, #1 8002452: d0c6 beq.n 80023e2 movementPhase = idlePhase; 8002454: 2700 movs r7, #0 8002456: e7f0 b.n 800243a moveCmdTimeoutCounter = 0; 8002458: f04f 0800 mov.w r8, #0 switch (movementPhase) { 800245c: 1e79 subs r1, r7, #1 800245e: 2904 cmp r1, #4 8002460: d842 bhi.n 80024e8 8002462: e8df f001 tbb [pc, r1] 8002466: 6e95 .short 0x6e95 8002468: 445e .short 0x445e 800246a: 2e .byte 0x2e 800246b: 00 .byte 0x00 if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 800246c: 2b01 cmp r3, #1 800246e: d1c1 bne.n 80023f4 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8002470: 2700 movs r7, #0 timeLeftMS += PositionControlTaskTimeOut; 8002472: f10a 0a64 add.w sl, sl, #100 @ 0x64 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8002476: e9cd 3203 strd r3, r2, [sp, #12] 800247a: e9cd 7701 strd r7, r7, [sp, #4] 800247e: 68eb ldr r3, [r5, #12] 8002480: 9300 str r3, [sp, #0] 8002482: 7a6b ldrb r3, [r5, #9] 8002484: 7a2a ldrb r2, [r5, #8] 8002486: e9d5 0100 ldrd r0, r1, [r5] 800248a: f7ff fde5 bl 8002058 *posCtrlTaskArg->motorStatus = motorStatus; 800248e: 6aab ldr r3, [r5, #40] @ 0x28 8002490: 7018 strb r0, [r3, #0] if (prevPosition == *posCtrlTaskArg->currentPosition) { 8002492: 6a2b ldr r3, [r5, #32] 8002494: edd3 7a00 vldr s15, [r3] 8002498: eeb4 9a67 vcmp.f32 s18, s15 800249c: eef1 fa10 vmrs APSR_nzcv, fpscr 80024a0: f040 8099 bne.w 80025d6 moveCmdTimeoutCounter += PositionControlTaskTimeOut; 80024a4: f108 0864 add.w r8, r8, #100 @ 0x64 if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 80024a8: f241 3388 movw r3, #5000 @ 0x1388 80024ac: 4598 cmp r8, r3 80024ae: f340 8096 ble.w 80025de 80024b2: e9d5 1c05 ldrd r1, ip, [r5, #20] 80024b6: e7ae b.n 8002416 ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 80024b8: 69e8 ldr r0, [r5, #28] 80024ba: 7800 ldrb r0, [r0, #0] 80024bc: 2801 cmp r0, #1 80024be: d199 bne.n 80023f4 80024c0: e7d6 b.n 8002470 float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue; 80024c2: edd4 7a00 vldr s15, [r4] 80024c6: f1bb 0f01 cmp.w fp, #1 80024ca: bf0c ite eq 80024cc: ee77 7ae8 vsubeq.f32 s15, s15, s17 80024d0: ee78 7ae7 vsubne.f32 s15, s17, s15 if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 80024d4: eef5 7ac0 vcmpe.f32 s15, #0.0 80024d8: eef1 fa10 vmrs APSR_nzcv, fpscr 80024dc: f240 8082 bls.w 80025e4 80024e0: f241 3187 movw r1, #4999 @ 0x1387 80024e4: 458a cmp sl, r1 80024e6: dc7d bgt.n 80025e4 80024e8: eeb0 9a68 vmov.f32 s18, s17 80024ec: e7a5 b.n 800243a motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80024ee: e9cd 3203 strd r3, r2, [sp, #12] 80024f2: 68ea ldr r2, [r5, #12] 80024f4: 233c movs r3, #60 @ 0x3c break; 80024f6: eeb0 9a68 vmov.f32 s18, s17 timeLeftMS = 0; 80024fa: f04f 0a00 mov.w sl, #0 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80024fe: 9200 str r2, [sp, #0] 8002500: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff pwmValue = MOTOR_START_STOP_PWM_VALUE; 8002504: 9307 str r3, [sp, #28] movementPhase = stopPhase; 8002506: 2705 movs r7, #5 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8002508: 9202 str r2, [sp, #8] 800250a: fb03 f20b mul.w r2, r3, fp 800250e: 9201 str r2, [sp, #4] 8002510: 7a6b ldrb r3, [r5, #9] 8002512: 7a2a ldrb r2, [r5, #8] 8002514: e9d5 0100 ldrd r0, r1, [r5] 8002518: f7ff fd9e bl 8002058 *posCtrlTaskArg->motorStatus = motorStatus; 800251c: 6aab ldr r3, [r5, #40] @ 0x28 800251e: 7018 strb r0, [r3, #0] break; 8002520: e78b b.n 800243a if (abs (*posCtrlTaskArg->currentPosition - *posCtrlTaskArg->positionSetting) <= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) { 8002522: 6a6b ldr r3, [r5, #36] @ 0x24 8002524: eeb0 9a68 vmov.f32 s18, s17 8002528: edd3 7a00 vldr s15, [r3] 800252c: ee78 8ae7 vsub.f32 s17, s17, s15 8002530: eefd 8ae8 vcvt.s32.f32 s17, s17 8002534: ee18 3a90 vmov r3, s17 8002538: 3305 adds r3, #5 800253a: 2b0b cmp r3, #11 800253c: bf38 it cc 800253e: 2704 movcc r7, #4 8002540: e77b b.n 800243a if ((abs (*posCtrlTaskArg->currentPosition - startPosition) >= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 8002542: ee78 7ac8 vsub.f32 s15, s17, s16 8002546: eefd 7ae7 vcvt.s32.f32 s15, s15 800254a: ee17 1a90 vmov r1, s15 800254e: 2900 cmp r1, #0 8002550: bfb8 it lt 8002552: 4249 neglt r1, r1 8002554: 2904 cmp r1, #4 8002556: dc03 bgt.n 8002560 8002558: f241 3187 movw r1, #4999 @ 0x1387 800255c: 458a cmp sl, r1 800255e: ddc3 ble.n 80024e8 *posCtrlTaskArg->motorStatus = motorStatus; 8002560: eeb0 9a68 vmov.f32 s18, s17 movementPhase = movePhase; 8002564: 2703 movs r7, #3 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8002566: e9cd 3203 strd r3, r2, [sp, #12] 800256a: 68ea ldr r2, [r5, #12] 800256c: 2364 movs r3, #100 @ 0x64 800256e: 9200 str r2, [sp, #0] 8002570: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff pwmValue = MOTOR_HIGH_SPEED_PWM_VALUE; 8002574: 9307 str r3, [sp, #28] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8002576: 9202 str r2, [sp, #8] 8002578: fb03 f20b mul.w r2, r3, fp 800257c: 9201 str r2, [sp, #4] 800257e: 7a6b ldrb r3, [r5, #9] 8002580: 7a2a ldrb r2, [r5, #8] 8002582: e9d5 0100 ldrd r0, r1, [r5] 8002586: f7ff fd67 bl 8002058 *posCtrlTaskArg->motorStatus = motorStatus; 800258a: 6aab ldr r3, [r5, #40] @ 0x28 800258c: 7018 strb r0, [r3, #0] movementPhase = movePhase; 800258e: e754 b.n 800243a motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8002590: e9cd 3203 strd r3, r2, [sp, #12] 8002594: 68eb ldr r3, [r5, #12] 8002596: eeb0 9a68 vmov.f32 s18, s17 800259a: 9300 str r3, [sp, #0] 800259c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80025a0: 9302 str r3, [sp, #8] 80025a2: 9b07 ldr r3, [sp, #28] 80025a4: fb0b f303 mul.w r3, fp, r3 80025a8: 9301 str r3, [sp, #4] 80025aa: 7a6b ldrb r3, [r5, #9] 80025ac: 7a2a ldrb r2, [r5, #8] 80025ae: e9d5 0100 ldrd r0, r1, [r5] 80025b2: f7ff fd51 bl 8002058 *posCtrlTaskArg->motorStatus = motorStatus; 80025b6: 6aab ldr r3, [r5, #40] @ 0x28 if (motorStatus == 1) { 80025b8: 2801 cmp r0, #1 *posCtrlTaskArg->motorStatus = motorStatus; 80025ba: 7018 strb r0, [r3, #0] if (motorStatus == 1) { 80025bc: f47f af4a bne.w 8002454 *posCtrlTaskArg->motorPeakCurrent = 0.0; 80025c0: 6aeb ldr r3, [r5, #44] @ 0x2c 80025c2: 2200 movs r2, #0 moveCmdTimeoutCounter = 0; 80025c4: f04f 0800 mov.w r8, #0 movementPhase = speedUpPhase; 80025c8: 2702 movs r7, #2 *posCtrlTaskArg->motorPeakCurrent = 0.0; 80025ca: 601a str r2, [r3, #0] timeLeftMS = 0; 80025cc: 46c2 mov sl, r8 80025ce: e734 b.n 800243a 80025d0: eef0 8a49 vmov.f32 s17, s18 80025d4: e742 b.n 800245c if (prevPosition == *posCtrlTaskArg->currentPosition) { 80025d6: eeb0 9a67 vmov.f32 s18, s15 moveCmdTimeoutCounter = 0; 80025da: 46b8 mov r8, r7 80025dc: e72d b.n 800243a if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 80025de: eeb0 9a67 vmov.f32 s18, s15 80025e2: e72a b.n 800243a *posCtrlTaskArg->motorStatus = motorStatus; 80025e4: eeb0 9a68 vmov.f32 s18, s17 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80025e8: e9cd 3203 strd r3, r2, [sp, #12] 80025ec: e718 b.n 8002420 80025ee: bf00 nop 80025f0: 00000000 .word 0x00000000 80025f4: 24000980 .word 0x24000980 80025f8: 24000a00 .word 0x24000a00 080025fc : void PositionControlTaskInit (void) { 80025fc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8002600: b08a sub sp, #40 @ 0x28 osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 8002602: 2224 movs r2, #36 @ 0x24 8002604: 2100 movs r1, #0 positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1; 8002606: 4c30 ldr r4, [pc, #192] @ (80026c8 ) osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 8002608: a801 add r0, sp, #4 positionXControlTaskInitArg.htim = &htim3; 800260a: f8df 80e8 ldr.w r8, [pc, #232] @ 80026f4 osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 800260e: f00d fa7b bl 800fb08 positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 8002612: 4a2e ldr r2, [pc, #184] @ (80026cc ) osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8002614: f44f 6380 mov.w r3, #1024 @ 0x400 positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8002618: 4f2d ldr r7, [pc, #180] @ (80026d0 ) positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 800261a: 6812 ldr r2, [r2, #0] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 800261c: 2104 movs r1, #4 osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2; 800261e: 9306 str r3, [sp, #24] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002620: 2010 movs r0, #16 positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1; 8002622: 8123 strh r3, [r4, #8] osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal; 8002624: 2318 movs r3, #24 positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 8002626: 60e2 str r2, [r4, #12] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002628: 2200 movs r2, #0 positionXControlTaskInitArg.htim = &htim3; 800262a: f8c4 8000 str.w r8, [r4] positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 800262e: 6067 str r7, [r4, #4] osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal; 8002630: 9307 str r3, [sp, #28] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002632: f009 fc2d bl 800be90 positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 8002636: 4b27 ldr r3, [pc, #156] @ (80026d4 ) positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002638: 2200 movs r2, #0 positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 800263a: 4e27 ldr r6, [pc, #156] @ (80026d8 ) positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 800263c: 2104 movs r1, #4 positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter); 800263e: 4d27 ldr r5, [pc, #156] @ (80026dc ) positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 8002640: 681b ldr r3, [r3, #0] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002642: 6120 str r0, [r4, #16] positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002644: 2010 movs r0, #16 positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 8002646: 60f3 str r3, [r6, #12] positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp); 8002648: 1eab subs r3, r5, #2 positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter); 800264a: 61e5 str r5, [r4, #28] positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp); 800264c: 6163 str r3, [r4, #20] positionXControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitXSwitchDown); 800264e: 1e6b subs r3, r5, #1 8002650: 61a3 str r3, [r4, #24] positionXControlTaskInitArg.currentPosition = &(sensorsInfo.currentXPosition); 8002652: 1dab adds r3, r5, #6 8002654: 6223 str r3, [r4, #32] positionXControlTaskInitArg.motorStatus = &(sensorsInfo.motorXStatus); 8002656: f1a5 0316 sub.w r3, r5, #22 800265a: 62a3 str r3, [r4, #40] @ 0x28 positionXControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorXPeakCurrent); 800265c: f1a5 030a sub.w r3, r5, #10 8002660: 62e3 str r3, [r4, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionXSetting; 8002662: 4b1f ldr r3, [pc, #124] @ (80026e0 ) 8002664: 6263 str r3, [r4, #36] @ 0x24 positionXControlTaskInitArg.axe = 'X'; 8002666: 2358 movs r3, #88 @ 0x58 8002668: f884 3030 strb.w r3, [r4, #48] @ 0x30 positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 800266c: f640 4308 movw r3, #3080 @ 0xc08 positionYControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8002670: e9c6 8700 strd r8, r7, [r6] positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 8002674: 8133 strh r3, [r6, #8] positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002676: f009 fc0b bl 800be90 positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter); 800267a: 1ceb adds r3, r5, #3 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 800267c: 4f19 ldr r7, [pc, #100] @ (80026e4 ) 800267e: 4621 mov r1, r4 8002680: aa01 add r2, sp, #4 positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter); 8002682: 61f3 str r3, [r6, #28] positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp); 8002684: 1c6b adds r3, r5, #1 positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8002686: 6130 str r0, [r6, #16] positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 8002688: 4638 mov r0, r7 positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp); 800268a: 6173 str r3, [r6, #20] positionYControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitYSwitchDown); 800268c: 1cab adds r3, r5, #2 800268e: 61b3 str r3, [r6, #24] positionYControlTaskInitArg.currentPosition = &(sensorsInfo.currentYPosition); 8002690: f105 030a add.w r3, r5, #10 8002694: 6233 str r3, [r6, #32] positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus); 8002696: f1a5 0315 sub.w r3, r5, #21 positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent); 800269a: 3d06 subs r5, #6 positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus); 800269c: 62b3 str r3, [r6, #40] @ 0x28 positionXControlTaskInitArg.positionSetting = &positionYSetting; 800269e: 4b12 ldr r3, [pc, #72] @ (80026e8 ) positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent); 80026a0: 62f5 str r5, [r6, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionYSetting; 80026a2: 6263 str r3, [r4, #36] @ 0x24 positionYControlTaskInitArg.axe = 'Y'; 80026a4: 2359 movs r3, #89 @ 0x59 80026a6: f886 3030 strb.w r3, [r6, #48] @ 0x30 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 80026aa: f009 fa9f bl 800bbec 80026ae: 4b0f ldr r3, [pc, #60] @ (80026ec ) 80026b0: 4604 mov r4, r0 positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); 80026b2: aa01 add r2, sp, #4 80026b4: 4631 mov r1, r6 80026b6: 4638 mov r0, r7 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 80026b8: 601c str r4, [r3, #0] positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); 80026ba: f009 fa97 bl 800bbec 80026be: 4b0c ldr r3, [pc, #48] @ (80026f0 ) 80026c0: 6018 str r0, [r3, #0] } 80026c2: b00a add sp, #40 @ 0x28 80026c4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80026c8: 24000a00 .word 0x24000a00 80026cc: 24000324 .word 0x24000324 80026d0: 24000290 .word 0x24000290 80026d4: 240002f4 .word 0x240002f4 80026d8: 240009c0 .word 0x240009c0 80026dc: 2400092a .word 0x2400092a 80026e0: 24000a60 .word 0x24000a60 80026e4: 08002335 .word 0x08002335 80026e8: 24000a40 .word 0x24000a40 80026ec: 24000a38 .word 0x24000a38 80026f0: 24000a34 .word 0x24000a34 80026f4: 24000500 .word 0x24000500 080026f8 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 80026f8: b570 push {r4, r5, r6, lr} uint32_t* uDataPtr = data; uint32_t uData = *uDataPtr; 80026fa: 6816 ldr r6, [r2, #0] uint8_t i = 0; uint8_t newBuffPos = *buffPos; 80026fc: 780a ldrb r2, [r1, #0] for (i = 0; i < dataSize; i++) { 80026fe: b18b cbz r3, 8002724 8002700: 4413 add r3, r2 8002702: f04f 0c00 mov.w ip, #0 8002706: fa5f fe83 uxtb.w lr, r3 buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 800270a: 1c55 adds r5, r2, #1 800270c: 4614 mov r4, r2 800270e: fa26 f30c lsr.w r3, r6, ip 8002712: f10c 0c08 add.w ip, ip, #8 8002716: b2ea uxtb r2, r5 8002718: 5503 strb r3, [r0, r4] for (i = 0; i < dataSize; i++) { 800271a: 4572 cmp r2, lr 800271c: d1f5 bne.n 800270a } *buffPos = newBuffPos; 800271e: f8a1 e000 strh.w lr, [r1] } 8002722: bd70 pop {r4, r5, r6, pc} uint8_t newBuffPos = *buffPos; 8002724: 4696 mov lr, r2 *buffPos = newBuffPos; 8002726: f8a1 e000 strh.w lr, [r1] } 800272a: bd70 pop {r4, r5, r6, pc} 0800272c : void ReadFloatFromBuffer(uint8_t* buff, uint16_t* buffPos, float* data) { uint32_t* word = (uint32_t *)data; *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 800272c: 880b ldrh r3, [r1, #0] 800272e: eb00 0c03 add.w ip, r0, r3 { 8002732: b510 push {r4, lr} *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8002734: f810 e003 ldrb.w lr, [r0, r3] *buffPos += sizeof(float); 8002738: 1d18 adds r0, r3, #4 *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 800273a: f89c 3002 ldrb.w r3, [ip, #2] 800273e: f89c 4003 ldrb.w r4, [ip, #3] 8002742: 041b lsls r3, r3, #16 8002744: f89c c001 ldrb.w ip, [ip, #1] 8002748: ea43 6304 orr.w r3, r3, r4, lsl #24 800274c: ea43 030e orr.w r3, r3, lr 8002750: ea43 230c orr.w r3, r3, ip, lsl #8 8002754: 6013 str r3, [r2, #0] *buffPos += sizeof(float); 8002756: 8008 strh r0, [r1, #0] } 8002758: bd10 pop {r4, pc} 800275a: bf00 nop 0800275c : { *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) 800275c: 880b ldrh r3, [r1, #0] 800275e: eb00 0c03 add.w ip, r0, r3 8002762: b510 push {r4, lr} 8002764: f810 e003 ldrb.w lr, [r0, r3] 8002768: 1d18 adds r0, r3, #4 800276a: f89c 3002 ldrb.w r3, [ip, #2] 800276e: f89c 4003 ldrb.w r4, [ip, #3] 8002772: 041b lsls r3, r3, #16 8002774: f89c c001 ldrb.w ip, [ip, #1] 8002778: ea43 6304 orr.w r3, r3, r4, lsl #24 800277c: ea43 030e orr.w r3, r3, lr 8002780: ea43 230c orr.w r3, r3, ip, lsl #8 8002784: 6013 str r3, [r2, #0] 8002786: 8008 strh r0, [r1, #0] 8002788: bd10 pop {r4, pc} 800278a: bf00 nop 0800278c : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 800278c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8002790: f8bd 501c ldrh.w r5, [sp, #28] 8002794: 460e mov r6, r1 8002796: 4690 mov r8, r2 uint16_t crc = 0; uint16_t txBufferPos = 0; uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response memset (txBuffer, 0x00, dataLength); 8002798: 2100 movs r1, #0 800279a: 462a mov r2, r5 uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 800279c: 4604 mov r4, r0 800279e: 461f mov r7, r3 memset (txBuffer, 0x00, dataLength); 80027a0: f00d f9b2 bl 800fb08 txBuffer[txBufferPos++] = FRAME_INDICATOR; txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 80027a4: 2380 movs r3, #128 @ 0x80 txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 80027a6: 7066 strb r6, [r4, #1] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 80027a8: 0a36 lsrs r6, r6, #8 txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 80027aa: f884 8003 strb.w r8, [r4, #3] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 80027ae: 7123 strb r3, [r4, #4] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 80027b0: 0a2b lsrs r3, r5, #8 txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 80027b2: 70a6 strb r6, [r4, #2] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 80027b4: 71a3 strb r3, [r4, #6] txBuffer[txBufferPos++] = FRAME_INDICATOR; 80027b6: 23aa movs r3, #170 @ 0xaa txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 80027b8: 7165 strb r5, [r4, #5] txBuffer[txBufferPos++] = (uint8_t)respStatus; 80027ba: 71e7 strb r7, [r4, #7] txBuffer[txBufferPos++] = FRAME_INDICATOR; 80027bc: 7023 strb r3, [r4, #0] if (dataLength > 0) { 80027be: b97d cbnz r5, 80027e0 80027c0: 250a movs r5, #10 80027c2: 2709 movs r7, #9 80027c4: 2608 movs r6, #8 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); txBufferPos += dataLength; } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 80027c6: 4632 mov r2, r6 80027c8: 4621 mov r1, r4 80027ca: 480d ldr r0, [pc, #52] @ (8002800 ) 80027cc: f002 fcc4 bl 8005158 80027d0: 4603 mov r3, r0 txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } 80027d2: 4628 mov r0, r5 txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 80027d4: 55a3 strb r3, [r4, r6] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 80027d6: f3c3 2307 ubfx r3, r3, #8, #8 80027da: 55e3 strb r3, [r4, r7] } 80027dc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 80027e0: 462a mov r2, r5 txBufferPos += dataLength; 80027e2: f105 0608 add.w r6, r5, #8 txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 80027e6: f105 0709 add.w r7, r5, #9 txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 80027ea: 350a adds r5, #10 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 80027ec: 9906 ldr r1, [sp, #24] 80027ee: f104 0008 add.w r0, r4, #8 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 80027f2: b2b6 uxth r6, r6 txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 80027f4: b2bf uxth r7, r7 80027f6: b2ad uxth r5, r5 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 80027f8: f00d fa5b bl 800fcb2 txBufferPos += dataLength; 80027fc: e7e3 b.n 80027c6 80027fe: bf00 nop 8002800: 240005d0 .word 0x240005d0 08002804 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8002804: b530 push {r4, r5, lr} /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; PWR_PVDTypeDef sConfigPVD = {0}; __HAL_RCC_SYSCFG_CLK_ENABLE(); 8002806: 4c23 ldr r4, [pc, #140] @ (8002894 ) { 8002808: b087 sub sp, #28 PWREx_AVDTypeDef sConfigAVD = {0}; 800280a: 2500 movs r5, #0 /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 800280c: 210f movs r1, #15 800280e: f06f 0001 mvn.w r0, #1 PWREx_AVDTypeDef sConfigAVD = {0}; 8002812: 9502 str r5, [sp, #8] HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8002814: 462a mov r2, r5 PWR_PVDTypeDef sConfigPVD = {0}; 8002816: 9505 str r5, [sp, #20] PWREx_AVDTypeDef sConfigAVD = {0}; 8002818: e9cd 5503 strd r5, r5, [sp, #12] __HAL_RCC_SYSCFG_CLK_ENABLE(); 800281c: f8d4 30f4 ldr.w r3, [r4, #244] @ 0xf4 8002820: f043 0302 orr.w r3, r3, #2 8002824: f8c4 30f4 str.w r3, [r4, #244] @ 0xf4 8002828: f8d4 30f4 ldr.w r3, [r4, #244] @ 0xf4 800282c: f003 0302 and.w r3, r3, #2 8002830: 9300 str r3, [sp, #0] 8002832: 9b00 ldr r3, [sp, #0] HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8002834: f002 fb80 bl 8004f38 /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8002838: 2105 movs r1, #5 800283a: 462a mov r2, r5 800283c: 4608 mov r0, r1 800283e: f002 fb7b bl 8004f38 HAL_NVIC_EnableIRQ(RCC_IRQn); 8002842: 2005 movs r0, #5 8002844: f002 fbb4 bl 8004fb0 /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 8002848: f44f 22c0 mov.w r2, #393216 @ 0x60000 800284c: 2300 movs r3, #0 sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; HAL_PWREx_ConfigAVD(&sConfigAVD); 800284e: a802 add r0, sp, #8 sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 8002850: e9cd 2302 strd r2, r3, [sp, #8] HAL_PWREx_ConfigAVD(&sConfigAVD); 8002854: f004 fd7a bl 800734c /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 8002858: f004 fdbe bl 80073d8 /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 800285c: 22c0 movs r2, #192 @ 0xc0 800285e: 2300 movs r3, #0 sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; HAL_PWR_ConfigPVD(&sConfigPVD); 8002860: a804 add r0, sp, #16 sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 8002862: e9cd 2304 strd r2, r3, [sp, #16] HAL_PWR_ConfigPVD(&sConfigPVD); 8002866: f004 fcfb bl 8007260 /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 800286a: f004 fd43 bl 80072f4 /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 800286e: f8d4 30f4 ldr.w r3, [r4, #244] @ 0xf4 8002872: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8002876: f8c4 30f4 str.w r3, [r4, #244] @ 0xf4 800287a: f8d4 30f4 ldr.w r3, [r4, #244] @ 0xf4 800287e: f403 4300 and.w r3, r3, #32768 @ 0x8000 8002882: 9301 str r3, [sp, #4] 8002884: 9b01 ldr r3, [sp, #4] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 8002886: f001 fbb9 bl 8003ffc /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 800288a: 2002 movs r0, #2 800288c: f001 fbac bl 8003fe8 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8002890: b007 add sp, #28 8002892: bd30 pop {r4, r5, pc} 8002894: 58024400 .word 0x58024400 08002898 : * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hadc->Instance==ADC1) 8002898: 4a95 ldr r2, [pc, #596] @ (8002af0 ) 800289a: 6803 ldr r3, [r0, #0] { 800289c: b570 push {r4, r5, r6, lr} if(hadc->Instance==ADC1) 800289e: 4293 cmp r3, r2 { 80028a0: b090 sub sp, #64 @ 0x40 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80028a2: f04f 0400 mov.w r4, #0 { 80028a6: 4605 mov r5, r0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80028a8: e9cd 440a strd r4, r4, [sp, #40] @ 0x28 80028ac: 940c str r4, [sp, #48] @ 0x30 80028ae: e9cd 440d strd r4, r4, [sp, #52] @ 0x34 if(hadc->Instance==ADC1) 80028b2: d06b beq.n 800298c /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ } else if(hadc->Instance==ADC2) 80028b4: 4a8f ldr r2, [pc, #572] @ (8002af4 ) 80028b6: 4293 cmp r3, r2 80028b8: d005 beq.n 80028c6 /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } else if(hadc->Instance==ADC3) 80028ba: 4a8f ldr r2, [pc, #572] @ (8002af8 ) 80028bc: 4293 cmp r3, r2 80028be: f000 80ce beq.w 8002a5e /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 80028c2: b010 add sp, #64 @ 0x40 80028c4: bd70 pop {r4, r5, r6, pc} HAL_RCC_ADC12_CLK_ENABLED++; 80028c6: 4a8d ldr r2, [pc, #564] @ (8002afc ) 80028c8: 6813 ldr r3, [r2, #0] 80028ca: 3301 adds r3, #1 if(HAL_RCC_ADC12_CLK_ENABLED==1){ 80028cc: 2b01 cmp r3, #1 HAL_RCC_ADC12_CLK_ENABLED++; 80028ce: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 80028d0: f000 80b4 beq.w 8002a3c __HAL_RCC_GPIOA_CLK_ENABLE(); 80028d4: 4b8a ldr r3, [pc, #552] @ (8002b00 ) HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80028d6: a90a add r1, sp, #40 @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 80028d8: 2600 movs r6, #0 hdma_adc2.Instance = DMA1_Stream1; 80028da: 4c8a ldr r4, [pc, #552] @ (8002b04 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 80028dc: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 80028e0: f042 0201 orr.w r2, r2, #1 80028e4: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 80028e8: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 80028ec: f002 0201 and.w r2, r2, #1 80028f0: 9205 str r2, [sp, #20] 80028f2: 9a05 ldr r2, [sp, #20] __HAL_RCC_GPIOC_CLK_ENABLE(); 80028f4: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 80028f8: f042 0204 orr.w r2, r2, #4 80028fc: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 8002900: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002904: f002 0204 and.w r2, r2, #4 8002908: 9206 str r2, [sp, #24] 800290a: 9a06 ldr r2, [sp, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 800290c: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002910: f042 0202 orr.w r2, r2, #2 8002914: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 GPIO_InitStruct.Pin = GPIO_PIN_6; 8002918: 2240 movs r2, #64 @ 0x40 __HAL_RCC_GPIOB_CLK_ENABLE(); 800291a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800291e: f003 0302 and.w r3, r3, #2 8002922: 9307 str r3, [sp, #28] GPIO_InitStruct.Pin = GPIO_PIN_6; 8002924: 2303 movs r3, #3 __HAL_RCC_GPIOB_CLK_ENABLE(); 8002926: 9807 ldr r0, [sp, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002928: 4877 ldr r0, [pc, #476] @ (8002b08 ) GPIO_InitStruct.Pin = GPIO_PIN_6; 800292a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800292e: f004 fafd bl 8006f2c GPIO_InitStruct.Pin = GPIO_PIN_4; 8002932: 2210 movs r2, #16 8002934: 2303 movs r3, #3 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002936: a90a add r1, sp, #40 @ 0x28 8002938: 4874 ldr r0, [pc, #464] @ (8002b0c ) GPIO_InitStruct.Pull = GPIO_NOPULL; 800293a: 960c str r6, [sp, #48] @ 0x30 GPIO_InitStruct.Pin = GPIO_PIN_4; 800293c: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002940: f004 faf4 bl 8006f2c GPIO_InitStruct.Pin = GPIO_PIN_1; 8002944: 2202 movs r2, #2 8002946: 2303 movs r3, #3 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002948: a90a add r1, sp, #40 @ 0x28 800294a: 4871 ldr r0, [pc, #452] @ (8002b10 ) GPIO_InitStruct.Pull = GPIO_NOPULL; 800294c: 960c str r6, [sp, #48] @ 0x30 GPIO_InitStruct.Pin = GPIO_PIN_1; 800294e: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002952: f004 faeb bl 8006f2c hdma_adc2.Instance = DMA1_Stream1; 8002956: 4a6f ldr r2, [pc, #444] @ (8002b14 ) hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8002958: 230a movs r3, #10 800295a: 6063 str r3, [r4, #4] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800295c: f44f 6300 mov.w r3, #2048 @ 0x800 hdma_adc2.Instance = DMA1_Stream1; 8002960: 6022 str r2, [r4, #0] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8002962: f44f 6280 mov.w r2, #1024 @ 0x400 hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8002966: 6163 str r3, [r4, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8002968: f44f 5300 mov.w r3, #8192 @ 0x2000 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 800296c: 4620 mov r0, r4 hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 800296e: 60a6 str r6, [r4, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8002970: 60e6 str r6, [r4, #12] hdma_adc2.Init.Mode = DMA_NORMAL; 8002972: 61e6 str r6, [r4, #28] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8002974: 6122 str r2, [r4, #16] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8002976: 6226 str r6, [r4, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8002978: 6266 str r6, [r4, #36] @ 0x24 hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 800297a: 61a3 str r3, [r4, #24] if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 800297c: f002 fe98 bl 80056b0 8002980: 2800 cmp r0, #0 8002982: d169 bne.n 8002a58 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8002984: 64ec str r4, [r5, #76] @ 0x4c 8002986: 63a5 str r5, [r4, #56] @ 0x38 } 8002988: b010 add sp, #64 @ 0x40 800298a: bd70 pop {r4, r5, r6, pc} HAL_RCC_ADC12_CLK_ENABLED++; 800298c: 4a5b ldr r2, [pc, #364] @ (8002afc ) 800298e: 6813 ldr r3, [r2, #0] 8002990: 3301 adds r3, #1 if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8002992: 2b01 cmp r3, #1 HAL_RCC_ADC12_CLK_ENABLED++; 8002994: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8002996: d043 beq.n 8002a20 __HAL_RCC_GPIOA_CLK_ENABLE(); 8002998: 4b59 ldr r3, [pc, #356] @ (8002b00 ) HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800299a: a90a add r1, sp, #40 @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 800299c: 2600 movs r6, #0 hdma_adc1.Instance = DMA1_Stream0; 800299e: 4c5e ldr r4, [pc, #376] @ (8002b18 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 80029a0: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 80029a4: f042 0201 orr.w r2, r2, #1 80029a8: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 80029ac: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 80029b0: f002 0201 and.w r2, r2, #1 80029b4: 9201 str r2, [sp, #4] 80029b6: 9a01 ldr r2, [sp, #4] __HAL_RCC_GPIOC_CLK_ENABLE(); 80029b8: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 80029bc: f042 0204 orr.w r2, r2, #4 80029c0: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 80029c4: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 80029c8: f002 0204 and.w r2, r2, #4 80029cc: 9202 str r2, [sp, #8] 80029ce: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 80029d0: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 80029d4: f042 0202 orr.w r2, r2, #2 80029d8: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 80029dc: 228f movs r2, #143 @ 0x8f __HAL_RCC_GPIOB_CLK_ENABLE(); 80029de: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80029e2: f003 0302 and.w r3, r3, #2 80029e6: 9303 str r3, [sp, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 80029e8: 2303 movs r3, #3 __HAL_RCC_GPIOB_CLK_ENABLE(); 80029ea: 9803 ldr r0, [sp, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80029ec: 4846 ldr r0, [pc, #280] @ (8002b08 ) GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 80029ee: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80029f2: f004 fa9b bl 8006f2c GPIO_InitStruct.Pin = GPIO_PIN_5; 80029f6: 2220 movs r2, #32 80029f8: 2303 movs r3, #3 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80029fa: a90a add r1, sp, #40 @ 0x28 80029fc: 4843 ldr r0, [pc, #268] @ (8002b0c ) GPIO_InitStruct.Pull = GPIO_NOPULL; 80029fe: 960c str r6, [sp, #48] @ 0x30 GPIO_InitStruct.Pin = GPIO_PIN_5; 8002a00: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002a04: f004 fa92 bl 8006f2c GPIO_InitStruct.Pin = GPIO_PIN_0; 8002a08: 2201 movs r2, #1 8002a0a: 2303 movs r3, #3 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002a0c: a90a add r1, sp, #40 @ 0x28 8002a0e: 4840 ldr r0, [pc, #256] @ (8002b10 ) GPIO_InitStruct.Pull = GPIO_NOPULL; 8002a10: 960c str r6, [sp, #48] @ 0x30 GPIO_InitStruct.Pin = GPIO_PIN_0; 8002a12: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002a16: f004 fa89 bl 8006f2c hdma_adc1.Instance = DMA1_Stream0; 8002a1a: 4a40 ldr r2, [pc, #256] @ (8002b1c ) hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8002a1c: 2309 movs r3, #9 8002a1e: e79c b.n 800295a __HAL_RCC_ADC12_CLK_ENABLE(); 8002a20: 4b37 ldr r3, [pc, #220] @ (8002b00 ) 8002a22: f8d3 20d8 ldr.w r2, [r3, #216] @ 0xd8 8002a26: f042 0220 orr.w r2, r2, #32 8002a2a: f8c3 20d8 str.w r2, [r3, #216] @ 0xd8 8002a2e: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8002a32: f003 0320 and.w r3, r3, #32 8002a36: 9300 str r3, [sp, #0] 8002a38: 9b00 ldr r3, [sp, #0] 8002a3a: e7ad b.n 8002998 __HAL_RCC_ADC12_CLK_ENABLE(); 8002a3c: 4b30 ldr r3, [pc, #192] @ (8002b00 ) 8002a3e: f8d3 20d8 ldr.w r2, [r3, #216] @ 0xd8 8002a42: f042 0220 orr.w r2, r2, #32 8002a46: f8c3 20d8 str.w r2, [r3, #216] @ 0xd8 8002a4a: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8002a4e: f003 0320 and.w r3, r3, #32 8002a52: 9304 str r3, [sp, #16] 8002a54: 9b04 ldr r3, [sp, #16] 8002a56: e73d b.n 80028d4 Error_Handler(); 8002a58: f7fd fece bl 80007f8 8002a5c: e792 b.n 8002984 __HAL_RCC_ADC3_CLK_ENABLE(); 8002a5e: 4b28 ldr r3, [pc, #160] @ (8002b00 ) HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002a60: a90a add r1, sp, #40 @ 0x28 hdma_adc3.Instance = DMA1_Stream2; 8002a62: 4e2f ldr r6, [pc, #188] @ (8002b20 ) __HAL_RCC_ADC3_CLK_ENABLE(); 8002a64: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002a68: f042 7280 orr.w r2, r2, #16777216 @ 0x1000000 8002a6c: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 8002a70: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002a74: f002 7280 and.w r2, r2, #16777216 @ 0x1000000 8002a78: 9208 str r2, [sp, #32] 8002a7a: 9a08 ldr r2, [sp, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 8002a7c: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002a80: f042 0204 orr.w r2, r2, #4 8002a84: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8002a88: 2203 movs r2, #3 __HAL_RCC_GPIOC_CLK_ENABLE(); 8002a8a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002a8e: f003 0304 and.w r3, r3, #4 8002a92: 9309 str r3, [sp, #36] @ 0x24 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8002a94: 2303 movs r3, #3 __HAL_RCC_GPIOC_CLK_ENABLE(); 8002a96: 9809 ldr r0, [sp, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002a98: 481c ldr r0, [pc, #112] @ (8002b0c ) GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8002a9a: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002a9e: f004 fa45 bl 8006f2c HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 8002aa2: f04f 6180 mov.w r1, #67108864 @ 0x4000000 8002aa6: 4608 mov r0, r1 8002aa8: f001 fab0 bl 800400c HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 8002aac: f04f 6100 mov.w r1, #134217728 @ 0x8000000 8002ab0: 4608 mov r0, r1 8002ab2: f001 faab bl 800400c hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 8002ab6: 2373 movs r3, #115 @ 0x73 hdma_adc3.Instance = DMA1_Stream2; 8002ab8: 4a1a ldr r2, [pc, #104] @ (8002b24 ) if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8002aba: 4630 mov r0, r6 hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 8002abc: 6073 str r3, [r6, #4] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8002abe: f44f 6300 mov.w r3, #2048 @ 0x800 hdma_adc3.Instance = DMA1_Stream2; 8002ac2: 6032 str r2, [r6, #0] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 8002ac4: f44f 6280 mov.w r2, #1024 @ 0x400 hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8002ac8: 6173 str r3, [r6, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8002aca: f44f 5300 mov.w r3, #8192 @ 0x2000 hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8002ace: 60b4 str r4, [r6, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8002ad0: 60f4 str r4, [r6, #12] hdma_adc3.Init.Mode = DMA_NORMAL; 8002ad2: 61f4 str r4, [r6, #28] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 8002ad4: 6132 str r2, [r6, #16] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 8002ad6: 6234 str r4, [r6, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8002ad8: 6274 str r4, [r6, #36] @ 0x24 hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8002ada: 61b3 str r3, [r6, #24] if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8002adc: f002 fde8 bl 80056b0 8002ae0: b910 cbnz r0, 8002ae8 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 8002ae2: 64ee str r6, [r5, #76] @ 0x4c 8002ae4: 63b5 str r5, [r6, #56] @ 0x38 } 8002ae6: e6ec b.n 80028c2 Error_Handler(); 8002ae8: f7fd fe86 bl 80007f8 8002aec: e7f9 b.n 8002ae2 8002aee: bf00 nop 8002af0: 40022000 .word 0x40022000 8002af4: 40022100 .word 0x40022100 8002af8: 58026000 .word 0x58026000 8002afc: 24000a64 .word 0x24000a64 8002b00: 58024400 .word 0x58024400 8002b04: 24000698 .word 0x24000698 8002b08: 58020000 .word 0x58020000 8002b0c: 58020800 .word 0x58020800 8002b10: 58020400 .word 0x58020400 8002b14: 40020028 .word 0x40020028 8002b18: 24000710 .word 0x24000710 8002b1c: 40020010 .word 0x40020010 8002b20: 24000620 .word 0x24000620 8002b24: 40020040 .word 0x40020040 08002b28 : * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hcomp->Instance==COMP1) 8002b28: 4a1b ldr r2, [pc, #108] @ (8002b98 ) GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002b2a: 2300 movs r3, #0 if(hcomp->Instance==COMP1) 8002b2c: 6801 ldr r1, [r0, #0] { 8002b2e: b500 push {lr} if(hcomp->Instance==COMP1) 8002b30: 4291 cmp r1, r2 { 8002b32: b089 sub sp, #36 @ 0x24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002b34: e9cd 3302 strd r3, r3, [sp, #8] 8002b38: e9cd 3304 strd r3, r3, [sp, #16] 8002b3c: 9306 str r3, [sp, #24] if(hcomp->Instance==COMP1) 8002b3e: d002 beq.n 8002b46 /* USER CODE BEGIN COMP1_MspInit 1 */ /* USER CODE END COMP1_MspInit 1 */ } } 8002b40: b009 add sp, #36 @ 0x24 8002b42: f85d fb04 ldr.w pc, [sp], #4 __HAL_RCC_COMP12_CLK_ENABLE(); 8002b46: 4b15 ldr r3, [pc, #84] @ (8002b9c ) HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002b48: a902 add r1, sp, #8 8002b4a: 4815 ldr r0, [pc, #84] @ (8002ba0 ) __HAL_RCC_COMP12_CLK_ENABLE(); 8002b4c: f8d3 20f4 ldr.w r2, [r3, #244] @ 0xf4 8002b50: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8002b54: f8c3 20f4 str.w r2, [r3, #244] @ 0xf4 8002b58: f8d3 20f4 ldr.w r2, [r3, #244] @ 0xf4 8002b5c: f402 4280 and.w r2, r2, #16384 @ 0x4000 8002b60: 9200 str r2, [sp, #0] 8002b62: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002b64: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002b68: f042 0202 orr.w r2, r2, #2 8002b6c: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 8002b70: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002b74: f003 0302 and.w r3, r3, #2 GPIO_InitStruct.Pin = GPIO_PIN_2; 8002b78: ed9f 7b05 vldr d7, [pc, #20] @ 8002b90 __HAL_RCC_GPIOB_CLK_ENABLE(); 8002b7c: 9301 str r3, [sp, #4] 8002b7e: 9b01 ldr r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_2; 8002b80: ed8d 7b02 vstr d7, [sp, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002b84: f004 f9d2 bl 8006f2c } 8002b88: b009 add sp, #36 @ 0x24 8002b8a: f85d fb04 ldr.w pc, [sp], #4 8002b8e: bf00 nop 8002b90: 00000004 .word 0x00000004 8002b94: 00000003 .word 0x00000003 8002b98: 5800380c .word 0x5800380c 8002b9c: 58024400 .word 0x58024400 8002ba0: 58020400 .word 0x58020400 08002ba4 : * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { if(hcrc->Instance==CRC) 8002ba4: 4b0a ldr r3, [pc, #40] @ (8002bd0 ) 8002ba6: 6802 ldr r2, [r0, #0] 8002ba8: 429a cmp r2, r3 8002baa: d000 beq.n 8002bae 8002bac: 4770 bx lr { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8002bae: f5a3 6300 sub.w r3, r3, #2048 @ 0x800 { 8002bb2: b082 sub sp, #8 __HAL_RCC_CRC_CLK_ENABLE(); 8002bb4: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002bb8: f442 2200 orr.w r2, r2, #524288 @ 0x80000 8002bbc: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 8002bc0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002bc4: f403 2300 and.w r3, r3, #524288 @ 0x80000 8002bc8: 9301 str r3, [sp, #4] 8002bca: 9b01 ldr r3, [sp, #4] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 8002bcc: b002 add sp, #8 8002bce: 4770 bx lr 8002bd0: 58024c00 .word 0x58024c00 08002bd4 : * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hdac->Instance==DAC1) 8002bd4: 4b1c ldr r3, [pc, #112] @ (8002c48 ) 8002bd6: 6802 ldr r2, [r0, #0] { 8002bd8: b530 push {r4, r5, lr} if(hdac->Instance==DAC1) 8002bda: 429a cmp r2, r3 { 8002bdc: b089 sub sp, #36 @ 0x24 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002bde: f04f 0400 mov.w r4, #0 8002be2: e9cd 4402 strd r4, r4, [sp, #8] 8002be6: e9cd 4404 strd r4, r4, [sp, #16] 8002bea: 9406 str r4, [sp, #24] if(hdac->Instance==DAC1) 8002bec: d001 beq.n 8002bf2 /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 8002bee: b009 add sp, #36 @ 0x24 8002bf0: bd30 pop {r4, r5, pc} __HAL_RCC_DAC12_CLK_ENABLE(); 8002bf2: 4b16 ldr r3, [pc, #88] @ (8002c4c ) HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002bf4: a902 add r1, sp, #8 8002bf6: 4816 ldr r0, [pc, #88] @ (8002c50 ) __HAL_RCC_DAC12_CLK_ENABLE(); 8002bf8: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8 8002bfc: f042 5200 orr.w r2, r2, #536870912 @ 0x20000000 8002c00: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8 8002c04: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8 8002c08: f002 5200 and.w r2, r2, #536870912 @ 0x20000000 8002c0c: 9200 str r2, [sp, #0] 8002c0e: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002c10: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002c14: f042 0201 orr.w r2, r2, #1 8002c18: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8002c1c: 2230 movs r2, #48 @ 0x30 __HAL_RCC_GPIOA_CLK_ENABLE(); 8002c1e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8002c22: f003 0301 and.w r3, r3, #1 8002c26: 9301 str r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8002c28: 2303 movs r3, #3 __HAL_RCC_GPIOA_CLK_ENABLE(); 8002c2a: 9d01 ldr r5, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 8002c2c: e9cd 2302 strd r2, r3, [sp, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002c30: f004 f97c bl 8006f2c HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 8002c34: 4622 mov r2, r4 8002c36: 2105 movs r1, #5 8002c38: 2036 movs r0, #54 @ 0x36 8002c3a: f002 f97d bl 8004f38 HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8002c3e: 2036 movs r0, #54 @ 0x36 8002c40: f002 f9b6 bl 8004fb0 } 8002c44: b009 add sp, #36 @ 0x24 8002c46: bd30 pop {r4, r5, pc} 8002c48: 40007400 .word 0x40007400 8002c4c: 58024400 .word 0x58024400 8002c50: 58020000 .word 0x58020000 08002c54 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 8002c54: b510 push {r4, lr} 8002c56: b0b2 sub sp, #200 @ 0xc8 8002c58: 4604 mov r4, r0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8002c5a: 22c0 movs r2, #192 @ 0xc0 8002c5c: 2100 movs r1, #0 8002c5e: a802 add r0, sp, #8 8002c60: f00c ff52 bl 800fb08 if(hrng->Instance==RNG) 8002c64: 4b10 ldr r3, [pc, #64] @ (8002ca8 ) 8002c66: 6822 ldr r2, [r4, #0] 8002c68: 429a cmp r2, r3 8002c6a: d001 beq.n 8002c70 /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 8002c6c: b032 add sp, #200 @ 0xc8 8002c6e: bd10 pop {r4, pc} PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 8002c70: f44f 3200 mov.w r2, #131072 @ 0x20000 8002c74: 2300 movs r3, #0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002c76: a802 add r0, sp, #8 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 8002c78: e9cd 2302 strd r2, r3, [sp, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002c7c: f005 fab0 bl 80081e0 8002c80: b970 cbnz r0, 8002ca0 __HAL_RCC_RNG_CLK_ENABLE(); 8002c82: 4b0a ldr r3, [pc, #40] @ (8002cac ) 8002c84: f8d3 20dc ldr.w r2, [r3, #220] @ 0xdc 8002c88: f042 0240 orr.w r2, r2, #64 @ 0x40 8002c8c: f8c3 20dc str.w r2, [r3, #220] @ 0xdc 8002c90: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8002c94: f003 0340 and.w r3, r3, #64 @ 0x40 8002c98: 9301 str r3, [sp, #4] 8002c9a: 9b01 ldr r3, [sp, #4] } 8002c9c: b032 add sp, #200 @ 0xc8 8002c9e: bd10 pop {r4, pc} Error_Handler(); 8002ca0: f7fd fdaa bl 80007f8 8002ca4: e7ed b.n 8002c82 8002ca6: bf00 nop 8002ca8: 48021800 .word 0x48021800 8002cac: 58024400 .word 0x58024400 08002cb0 : * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { if(htim_pwm->Instance==TIM1) 8002cb0: 4a13 ldr r2, [pc, #76] @ (8002d00 ) { 8002cb2: b082 sub sp, #8 if(htim_pwm->Instance==TIM1) 8002cb4: 6803 ldr r3, [r0, #0] 8002cb6: 4293 cmp r3, r2 8002cb8: d013 beq.n 8002ce2 __HAL_RCC_TIM1_CLK_ENABLE(); /* USER CODE BEGIN TIM1_MspInit 1 */ /* USER CODE END TIM1_MspInit 1 */ } else if(htim_pwm->Instance==TIM3) 8002cba: 4a12 ldr r2, [pc, #72] @ (8002d04 ) 8002cbc: 4293 cmp r3, r2 8002cbe: d001 beq.n 8002cc4 /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8002cc0: b002 add sp, #8 8002cc2: 4770 bx lr __HAL_RCC_TIM3_CLK_ENABLE(); 8002cc4: 4b10 ldr r3, [pc, #64] @ (8002d08 ) 8002cc6: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8 8002cca: f042 0202 orr.w r2, r2, #2 8002cce: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8 8002cd2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8002cd6: f003 0302 and.w r3, r3, #2 8002cda: 9301 str r3, [sp, #4] 8002cdc: 9b01 ldr r3, [sp, #4] } 8002cde: b002 add sp, #8 8002ce0: 4770 bx lr __HAL_RCC_TIM1_CLK_ENABLE(); 8002ce2: 4b09 ldr r3, [pc, #36] @ (8002d08 ) 8002ce4: f8d3 20f0 ldr.w r2, [r3, #240] @ 0xf0 8002ce8: f042 0201 orr.w r2, r2, #1 8002cec: f8c3 20f0 str.w r2, [r3, #240] @ 0xf0 8002cf0: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8002cf4: f003 0301 and.w r3, r3, #1 8002cf8: 9300 str r3, [sp, #0] 8002cfa: 9b00 ldr r3, [sp, #0] } 8002cfc: b002 add sp, #8 8002cfe: 4770 bx lr 8002d00: 40010000 .word 0x40010000 8002d04: 40000400 .word 0x40000400 8002d08: 58024400 .word 0x58024400 08002d0c : * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { if(htim_base->Instance==TIM8) 8002d0c: 4b0a ldr r3, [pc, #40] @ (8002d38 ) 8002d0e: 6802 ldr r2, [r0, #0] 8002d10: 429a cmp r2, r3 8002d12: d000 beq.n 8002d16 8002d14: 4770 bx lr { /* USER CODE BEGIN TIM8_MspInit 0 */ /* USER CODE END TIM8_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM8_CLK_ENABLE(); 8002d16: 4b09 ldr r3, [pc, #36] @ (8002d3c ) { 8002d18: b082 sub sp, #8 __HAL_RCC_TIM8_CLK_ENABLE(); 8002d1a: f8d3 20f0 ldr.w r2, [r3, #240] @ 0xf0 8002d1e: f042 0202 orr.w r2, r2, #2 8002d22: f8c3 20f0 str.w r2, [r3, #240] @ 0xf0 8002d26: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8002d2a: f003 0302 and.w r3, r3, #2 8002d2e: 9301 str r3, [sp, #4] 8002d30: 9b01 ldr r3, [sp, #4] /* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE END TIM8_MspInit 1 */ } } 8002d32: b002 add sp, #8 8002d34: 4770 bx lr 8002d36: bf00 nop 8002d38: 40010400 .word 0x40010400 8002d3c: 58024400 .word 0x58024400 08002d40 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(htim->Instance==TIM1) 8002d40: 4925 ldr r1, [pc, #148] @ (8002dd8 ) GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002d42: 2300 movs r3, #0 if(htim->Instance==TIM1) 8002d44: 6802 ldr r2, [r0, #0] { 8002d46: b510 push {r4, lr} if(htim->Instance==TIM1) 8002d48: 428a cmp r2, r1 { 8002d4a: b088 sub sp, #32 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002d4c: e9cd 3302 strd r3, r3, [sp, #8] 8002d50: e9cd 3304 strd r3, r3, [sp, #16] 8002d54: 9306 str r3, [sp, #24] if(htim->Instance==TIM1) 8002d56: d004 beq.n 8002d62 /* USER CODE BEGIN TIM1_MspPostInit 1 */ /* USER CODE END TIM1_MspPostInit 1 */ } else if(htim->Instance==TIM3) 8002d58: 4b20 ldr r3, [pc, #128] @ (8002ddc ) 8002d5a: 429a cmp r2, r3 8002d5c: d018 beq.n 8002d90 /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 8002d5e: b008 add sp, #32 8002d60: bd10 pop {r4, pc} __HAL_RCC_GPIOA_CLK_ENABLE(); 8002d62: 4b1f ldr r3, [pc, #124] @ (8002de0 ) GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 8002d64: 2401 movs r4, #1 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002d66: a902 add r1, sp, #8 8002d68: 481e ldr r0, [pc, #120] @ (8002de4 ) __HAL_RCC_GPIOA_CLK_ENABLE(); 8002d6a: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002d6e: 4322 orrs r2, r4 8002d70: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 8002d74: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 8002d78: 9406 str r4, [sp, #24] __HAL_RCC_GPIOA_CLK_ENABLE(); 8002d7a: 4023 ands r3, r4 GPIO_InitStruct.Pin = GPIO_PIN_9; 8002d7c: ed9f 7b12 vldr d7, [pc, #72] @ 8002dc8 __HAL_RCC_GPIOA_CLK_ENABLE(); 8002d80: 9300 str r3, [sp, #0] 8002d82: 9b00 ldr r3, [sp, #0] GPIO_InitStruct.Pin = GPIO_PIN_9; 8002d84: ed8d 7b02 vstr d7, [sp, #8] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8002d88: f004 f8d0 bl 8006f2c } 8002d8c: b008 add sp, #32 8002d8e: bd10 pop {r4, pc} __HAL_RCC_GPIOC_CLK_ENABLE(); 8002d90: 4b13 ldr r3, [pc, #76] @ (8002de0 ) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8002d92: 2001 movs r0, #1 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002d94: a902 add r1, sp, #8 __HAL_RCC_GPIOC_CLK_ENABLE(); 8002d96: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002d9a: f042 0204 orr.w r2, r2, #4 8002d9e: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8002da2: 2202 movs r2, #2 __HAL_RCC_GPIOC_CLK_ENABLE(); 8002da4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8002da8: 9005 str r0, [sp, #20] __HAL_RCC_GPIOC_CLK_ENABLE(); 8002daa: f003 0304 and.w r3, r3, #4 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002dae: 480e ldr r0, [pc, #56] @ (8002de8 ) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8002db0: 9206 str r2, [sp, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 8002db2: 9301 str r3, [sp, #4] 8002db4: 9b01 ldr r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 8002db6: ed9f 7b06 vldr d7, [pc, #24] @ 8002dd0 8002dba: ed8d 7b02 vstr d7, [sp, #8] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8002dbe: f004 f8b5 bl 8006f2c } 8002dc2: b008 add sp, #32 8002dc4: bd10 pop {r4, pc} 8002dc6: bf00 nop 8002dc8: 00000200 .word 0x00000200 8002dcc: 00000002 .word 0x00000002 8002dd0: 000003c0 .word 0x000003c0 8002dd4: 00000002 .word 0x00000002 8002dd8: 40010000 .word 0x40010000 8002ddc: 40000400 .word 0x40000400 8002de0: 58024400 .word 0x58024400 8002de4: 58020000 .word 0x58020000 8002de8: 58020800 .word 0x58020800 8002dec: 00000000 .word 0x00000000 08002df0 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8002df0: b510 push {r4, lr} 8002df2: b0ba sub sp, #232 @ 0xe8 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002df4: 2100 movs r1, #0 { 8002df6: 4604 mov r4, r0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8002df8: 22c0 movs r2, #192 @ 0xc0 8002dfa: a80a add r0, sp, #40 @ 0x28 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8002dfc: 9108 str r1, [sp, #32] 8002dfe: e9cd 1104 strd r1, r1, [sp, #16] 8002e02: e9cd 1106 strd r1, r1, [sp, #24] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8002e06: f00c fe7f bl 800fb08 if(huart->Instance==UART8) 8002e0a: 6823 ldr r3, [r4, #0] 8002e0c: 4a46 ldr r2, [pc, #280] @ (8002f28 ) 8002e0e: 4293 cmp r3, r2 8002e10: d004 beq.n 8002e1c HAL_NVIC_EnableIRQ(UART8_IRQn); /* USER CODE BEGIN UART8_MspInit 1 */ /* USER CODE END UART8_MspInit 1 */ } else if(huart->Instance==USART1) 8002e12: 4a46 ldr r2, [pc, #280] @ (8002f2c ) 8002e14: 4293 cmp r3, r2 8002e16: d03b beq.n 8002e90 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8002e18: b03a add sp, #232 @ 0xe8 8002e1a: bd10 pop {r4, pc} PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8002e1c: 2202 movs r2, #2 8002e1e: 2300 movs r3, #0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002e20: a80a add r0, sp, #40 @ 0x28 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8002e22: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002e26: f005 f9db bl 80081e0 8002e2a: 2800 cmp r0, #0 8002e2c: d169 bne.n 8002f02 __HAL_RCC_UART8_CLK_ENABLE(); 8002e2e: 4b40 ldr r3, [pc, #256] @ (8002f30 ) GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 8002e30: 2408 movs r4, #8 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8002e32: a904 add r1, sp, #16 8002e34: 483f ldr r0, [pc, #252] @ (8002f34 ) __HAL_RCC_UART8_CLK_ENABLE(); 8002e36: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8 8002e3a: f042 4200 orr.w r2, r2, #2147483648 @ 0x80000000 8002e3e: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8 8002e42: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8 8002e46: f002 4200 and.w r2, r2, #2147483648 @ 0x80000000 8002e4a: 9200 str r2, [sp, #0] 8002e4c: 9a00 ldr r2, [sp, #0] __HAL_RCC_GPIOE_CLK_ENABLE(); 8002e4e: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002e52: f042 0210 orr.w r2, r2, #16 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8002e56: ed9f 7b2e vldr d7, [pc, #184] @ 8002f10 __HAL_RCC_GPIOE_CLK_ENABLE(); 8002e5a: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 8002e5e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 8002e62: 9408 str r4, [sp, #32] __HAL_RCC_GPIOE_CLK_ENABLE(); 8002e64: f003 0310 and.w r3, r3, #16 GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8002e68: ed8d 7b04 vstr d7, [sp, #16] 8002e6c: ed9f 7b2a vldr d7, [pc, #168] @ 8002f18 __HAL_RCC_GPIOE_CLK_ENABLE(); 8002e70: 9301 str r3, [sp, #4] 8002e72: 9b01 ldr r3, [sp, #4] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8002e74: ed8d 7b06 vstr d7, [sp, #24] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8002e78: f004 f858 bl 8006f2c HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 8002e7c: 2200 movs r2, #0 8002e7e: 2105 movs r1, #5 8002e80: 2053 movs r0, #83 @ 0x53 8002e82: f002 f859 bl 8004f38 HAL_NVIC_EnableIRQ(UART8_IRQn); 8002e86: 2053 movs r0, #83 @ 0x53 8002e88: f002 f892 bl 8004fb0 } 8002e8c: b03a add sp, #232 @ 0xe8 8002e8e: bd10 pop {r4, pc} PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8002e90: 2201 movs r2, #1 8002e92: 2300 movs r3, #0 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002e94: a80a add r0, sp, #40 @ 0x28 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8002e96: e9cd 230a strd r2, r3, [sp, #40] @ 0x28 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8002e9a: f005 f9a1 bl 80081e0 8002e9e: bb98 cbnz r0, 8002f08 __HAL_RCC_USART1_CLK_ENABLE(); 8002ea0: 4b23 ldr r3, [pc, #140] @ (8002f30 ) GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 8002ea2: 2404 movs r4, #4 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002ea4: a904 add r1, sp, #16 8002ea6: 4824 ldr r0, [pc, #144] @ (8002f38 ) __HAL_RCC_USART1_CLK_ENABLE(); 8002ea8: f8d3 20f0 ldr.w r2, [r3, #240] @ 0xf0 8002eac: f042 0210 orr.w r2, r2, #16 8002eb0: f8c3 20f0 str.w r2, [r3, #240] @ 0xf0 8002eb4: f8d3 20f0 ldr.w r2, [r3, #240] @ 0xf0 8002eb8: f002 0210 and.w r2, r2, #16 8002ebc: 9202 str r2, [sp, #8] 8002ebe: 9a02 ldr r2, [sp, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002ec0: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0 8002ec4: f042 0202 orr.w r2, r2, #2 GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8002ec8: ed9f 7b15 vldr d7, [pc, #84] @ 8002f20 __HAL_RCC_GPIOB_CLK_ENABLE(); 8002ecc: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0 8002ed0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 8002ed4: 9408 str r4, [sp, #32] __HAL_RCC_GPIOB_CLK_ENABLE(); 8002ed6: f003 0302 and.w r3, r3, #2 GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8002eda: ed8d 7b04 vstr d7, [sp, #16] 8002ede: ed9f 7b0e vldr d7, [pc, #56] @ 8002f18 __HAL_RCC_GPIOB_CLK_ENABLE(); 8002ee2: 9303 str r3, [sp, #12] 8002ee4: 9b03 ldr r3, [sp, #12] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8002ee6: ed8d 7b06 vstr d7, [sp, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8002eea: f004 f81f bl 8006f2c HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 8002eee: 2200 movs r2, #0 8002ef0: 2105 movs r1, #5 8002ef2: 2025 movs r0, #37 @ 0x25 8002ef4: f002 f820 bl 8004f38 HAL_NVIC_EnableIRQ(USART1_IRQn); 8002ef8: 2025 movs r0, #37 @ 0x25 8002efa: f002 f859 bl 8004fb0 } 8002efe: b03a add sp, #232 @ 0xe8 8002f00: bd10 pop {r4, pc} Error_Handler(); 8002f02: f7fd fc79 bl 80007f8 8002f06: e792 b.n 8002e2e Error_Handler(); 8002f08: f7fd fc76 bl 80007f8 8002f0c: e7c8 b.n 8002ea0 8002f0e: bf00 nop 8002f10: 00000003 .word 0x00000003 8002f14: 00000002 .word 0x00000002 ... 8002f20: 0000c000 .word 0x0000c000 8002f24: 00000002 .word 0x00000002 8002f28: 40007c00 .word 0x40007c00 8002f2c: 40011000 .word 0x40011000 8002f30: 58024400 .word 0x58024400 8002f34: 58021000 .word 0x58021000 8002f38: 58020400 .word 0x58020400 08002f3c : uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8002f3c: 280f cmp r0, #15 8002f3e: d901 bls.n 8002f44 HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); uwTickPrio = TickPriority; } else { return HAL_ERROR; 8002f40: 2001 movs r0, #1 return HAL_TIM_Base_Start_IT(&htim6); } /* Return function status */ return HAL_ERROR; } 8002f42: 4770 bx lr { 8002f44: b530 push {r4, r5, lr} HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 8002f46: 4601 mov r1, r0 { 8002f48: b08b sub sp, #44 @ 0x2c HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 8002f4a: 2200 movs r2, #0 8002f4c: 4604 mov r4, r0 8002f4e: 2036 movs r0, #54 @ 0x36 8002f50: f001 fff2 bl 8004f38 HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8002f54: 2036 movs r0, #54 @ 0x36 8002f56: f002 f82b bl 8004fb0 __HAL_RCC_TIM6_CLK_ENABLE(); 8002f5a: 4b1b ldr r3, [pc, #108] @ (8002fc8 ) uwTickPrio = TickPriority; 8002f5c: 4a1b ldr r2, [pc, #108] @ (8002fcc ) HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8002f5e: 4669 mov r1, sp 8002f60: a802 add r0, sp, #8 uwTickPrio = TickPriority; 8002f62: 6014 str r4, [r2, #0] __HAL_RCC_TIM6_CLK_ENABLE(); 8002f64: f8d3 20e8 ldr.w r2, [r3, #232] @ 0xe8 8002f68: f042 0210 orr.w r2, r2, #16 8002f6c: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8 8002f70: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8002f74: f003 0310 and.w r3, r3, #16 8002f78: 9301 str r3, [sp, #4] 8002f7a: 9b01 ldr r3, [sp, #4] HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8002f7c: f005 f820 bl 8007fc0 if (uwAPB1Prescaler == RCC_HCLK_DIV1) 8002f80: 9b07 ldr r3, [sp, #28] 8002f82: b9c3 cbnz r3, 8002fb6 uwTimclock = HAL_RCC_GetPCLK1Freq(); 8002f84: f004 ff8c bl 8007ea0 8002f88: 4603 mov r3, r0 uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8002f8a: 4911 ldr r1, [pc, #68] @ (8002fd0 ) htim6.Init.ClockDivision = 0; 8002f8c: 2200 movs r2, #0 htim6.Instance = TIM6; 8002f8e: 4c11 ldr r4, [pc, #68] @ (8002fd4 ) uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8002f90: fba1 1303 umull r1, r3, r1, r3 htim6.Instance = TIM6; 8002f94: 4d10 ldr r5, [pc, #64] @ (8002fd8 ) htim6.Init.Period = (1000000U / 1000U) - 1U; 8002f96: f240 31e7 movw r1, #999 @ 0x3e7 if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 8002f9a: 4620 mov r0, r4 uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8002f9c: 0c9b lsrs r3, r3, #18 htim6.Instance = TIM6; 8002f9e: 6025 str r5, [r4, #0] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8002fa0: 60a2 str r2, [r4, #8] uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8002fa2: 3b01 subs r3, #1 htim6.Init.Period = (1000000U / 1000U) - 1U; 8002fa4: e9c4 1203 strd r1, r2, [r4, #12] htim6.Init.Prescaler = uwPrescalerValue; 8002fa8: 6063 str r3, [r4, #4] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 8002faa: f006 fcc9 bl 8009940 8002fae: b130 cbz r0, 8002fbe return HAL_ERROR; 8002fb0: 2001 movs r0, #1 } 8002fb2: b00b add sp, #44 @ 0x2c 8002fb4: bd30 pop {r4, r5, pc} uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 8002fb6: f004 ff73 bl 8007ea0 8002fba: 0043 lsls r3, r0, #1 8002fbc: e7e5 b.n 8002f8a return HAL_TIM_Base_Start_IT(&htim6); 8002fbe: 4620 mov r0, r4 8002fc0: f006 fdb2 bl 8009b28 8002fc4: e7f5 b.n 8002fb2 8002fc6: bf00 nop 8002fc8: 58024400 .word 0x58024400 8002fcc: 24000040 .word 0x24000040 8002fd0: 431bde83 .word 0x431bde83 8002fd4: 24000a68 .word 0x24000a68 8002fd8: 40001000 .word 0x40001000 08002fdc : { /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8002fdc: e7fe b.n 8002fdc 8002fde: bf00 nop 08002fe0 : void HardFault_Handler(void) { /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8002fe0: e7fe b.n 8002fe0 8002fe2: bf00 nop 08002fe4 : void MemManage_Handler(void) { /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8002fe4: e7fe b.n 8002fe4 8002fe6: bf00 nop 08002fe8 : void BusFault_Handler(void) { /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8002fe8: e7fe b.n 8002fe8 8002fea: bf00 nop 08002fec : void UsageFault_Handler(void) { /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8002fec: e7fe b.n 8002fec 8002fee: bf00 nop 08002ff0 : /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8002ff0: 4770 bx lr 8002ff2: bf00 nop 08002ff4 : /******************************************************************************/ /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) 8002ff4: 4770 bx lr 8002ff6: bf00 nop 08002ff8 : void DMA1_Stream0_IRQHandler(void) { /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8002ff8: 4801 ldr r0, [pc, #4] @ (8003000 ) 8002ffa: f003 bc43 b.w 8006884 8002ffe: bf00 nop 8003000: 24000710 .word 0x24000710 08003004 : void DMA1_Stream1_IRQHandler(void) { /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 8003004: 4801 ldr r0, [pc, #4] @ (800300c ) 8003006: f003 bc3d b.w 8006884 800300a: bf00 nop 800300c: 24000698 .word 0x24000698 08003010 : void DMA1_Stream2_IRQHandler(void) { /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 8003010: 4801 ldr r0, [pc, #4] @ (8003018 ) 8003012: f003 bc37 b.w 8006884 8003016: bf00 nop 8003018: 24000620 .word 0x24000620 0800301c : void USART1_IRQHandler(void) { /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 800301c: 4801 ldr r0, [pc, #4] @ (8003024 ) 800301e: f007 bc7d b.w 800a91c 8003022: bf00 nop 8003024: 2400038c .word 0x2400038c 08003028 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8003028: b508 push {r3, lr} /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 800302a: f44f 6080 mov.w r0, #1024 @ 0x400 800302e: f004 f8d3 bl 80071d8 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 8003032: f44f 6000 mov.w r0, #2048 @ 0x800 8003036: f004 f8cf bl 80071d8 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); 800303a: f44f 4080 mov.w r0, #16384 @ 0x4000 800303e: f004 f8cb bl 80071d8 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); 8003042: f44f 4000 mov.w r0, #32768 @ 0x8000 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 8003046: e8bd 4008 ldmia.w sp!, {r3, lr} HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); 800304a: f004 b8c5 b.w 80071d8 800304e: bf00 nop 08003050 : void TIM6_DAC_IRQHandler(void) { /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 8003050: 4807 ldr r0, [pc, #28] @ (8003070 ) { 8003052: b508 push {r3, lr} if (hdac1.State != HAL_DAC_STATE_RESET) { 8003054: 7903 ldrb r3, [r0, #4] 8003056: b923 cbnz r3, 8003062 HAL_DAC_IRQHandler(&hdac1); } HAL_TIM_IRQHandler(&htim6); 8003058: 4806 ldr r0, [pc, #24] @ (8003074 ) /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 800305a: e8bd 4008 ldmia.w sp!, {r3, lr} HAL_TIM_IRQHandler(&htim6); 800305e: f007 b849 b.w 800a0f4 HAL_DAC_IRQHandler(&hdac1); 8003062: f002 f95f bl 8005324 HAL_TIM_IRQHandler(&htim6); 8003066: 4803 ldr r0, [pc, #12] @ (8003074 ) } 8003068: e8bd 4008 ldmia.w sp!, {r3, lr} HAL_TIM_IRQHandler(&htim6); 800306c: f007 b842 b.w 800a0f4 8003070: 240005bc .word 0x240005bc 8003074: 24000a68 .word 0x24000a68 08003078 : void UART8_IRQHandler(void) { /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 8003078: 4801 ldr r0, [pc, #4] @ (8003080 ) 800307a: f007 bc4f b.w 800a91c 800307e: bf00 nop 8003080: 24000420 .word 0x24000420 08003084 <_getpid>: } int _getpid(void) { return 1; } 8003084: 2001 movs r0, #1 8003086: 4770 bx lr 08003088 <_kill>: int _kill(int pid, int sig) { 8003088: b508 push {r3, lr} (void)pid; (void)sig; errno = EINVAL; 800308a: f00c fde5 bl 800fc58 <__errno> 800308e: 2216 movs r2, #22 8003090: 4603 mov r3, r0 return -1; } 8003092: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff errno = EINVAL; 8003096: 601a str r2, [r3, #0] } 8003098: bd08 pop {r3, pc} 800309a: bf00 nop 0800309c <_exit>: void _exit (int status) { 800309c: b508 push {r3, lr} errno = EINVAL; 800309e: f00c fddb bl 800fc58 <__errno> 80030a2: 2316 movs r3, #22 80030a4: 6003 str r3, [r0, #0] _kill(status, -1); while (1) {} /* Make sure we hang here */ 80030a6: e7fe b.n 80030a6 <_exit+0xa> 080030a8 <_read>: } __attribute__((weak)) int _read(int file, char *ptr, int len) { 80030a8: b570 push {r4, r5, r6, lr} (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80030aa: 1e16 subs r6, r2, #0 80030ac: dd07 ble.n 80030be <_read+0x16> 80030ae: 460c mov r4, r1 80030b0: 198d adds r5, r1, r6 { *ptr++ = __io_getchar(); 80030b2: f3af 8000 nop.w 80030b6: f804 0b01 strb.w r0, [r4], #1 for (DataIdx = 0; DataIdx < len; DataIdx++) 80030ba: 42a5 cmp r5, r4 80030bc: d1f9 bne.n 80030b2 <_read+0xa> } return len; } 80030be: 4630 mov r0, r6 80030c0: bd70 pop {r4, r5, r6, pc} 80030c2: bf00 nop 080030c4 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 80030c4: b570 push {r4, r5, r6, lr} (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 80030c6: 1e16 subs r6, r2, #0 80030c8: dd07 ble.n 80030da <_write+0x16> 80030ca: 460c mov r4, r1 80030cc: 198d adds r5, r1, r6 { __io_putchar(*ptr++); 80030ce: f814 0b01 ldrb.w r0, [r4], #1 80030d2: f7fd fb19 bl 8000708 <__io_putchar> for (DataIdx = 0; DataIdx < len; DataIdx++) 80030d6: 42ac cmp r4, r5 80030d8: d1f9 bne.n 80030ce <_write+0xa> } return len; } 80030da: 4630 mov r0, r6 80030dc: bd70 pop {r4, r5, r6, pc} 80030de: bf00 nop 080030e0 <_close>: int _close(int file) { (void)file; return -1; } 80030e0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80030e4: 4770 bx lr 80030e6: bf00 nop 080030e8 <_fstat>: int _fstat(int file, struct stat *st) { (void)file; st->st_mode = S_IFCHR; 80030e8: f44f 5300 mov.w r3, #8192 @ 0x2000 return 0; } 80030ec: 2000 movs r0, #0 st->st_mode = S_IFCHR; 80030ee: 604b str r3, [r1, #4] } 80030f0: 4770 bx lr 80030f2: bf00 nop 080030f4 <_isatty>: int _isatty(int file) { (void)file; return 1; } 80030f4: 2001 movs r0, #1 80030f6: 4770 bx lr 080030f8 <_lseek>: { (void)file; (void)ptr; (void)dir; return 0; } 80030f8: 2000 movs r0, #0 80030fa: 4770 bx lr 080030fc <_sbrk>: const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; const uint8_t *max_heap = (uint8_t *)stack_limit; uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 80030fc: 490d ldr r1, [pc, #52] @ (8003134 <_sbrk+0x38>) { 80030fe: 4603 mov r3, r0 const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8003100: 4a0d ldr r2, [pc, #52] @ (8003138 <_sbrk+0x3c>) if (NULL == __sbrk_heap_end) 8003102: 6808 ldr r0, [r1, #0] { 8003104: b510 push {r4, lr} const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8003106: 4c0d ldr r4, [pc, #52] @ (800313c <_sbrk+0x40>) 8003108: 1b12 subs r2, r2, r4 if (NULL == __sbrk_heap_end) 800310a: b120 cbz r0, 8003116 <_sbrk+0x1a> { __sbrk_heap_end = &_end; } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800310c: 4403 add r3, r0 800310e: 4293 cmp r3, r2 8003110: d807 bhi.n 8003122 <_sbrk+0x26> errno = ENOMEM; return (void *)-1; } prev_heap_end = __sbrk_heap_end; __sbrk_heap_end += incr; 8003112: 600b str r3, [r1, #0] return (void *)prev_heap_end; } 8003114: bd10 pop {r4, pc} __sbrk_heap_end = &_end; 8003116: 4c0a ldr r4, [pc, #40] @ (8003140 <_sbrk+0x44>) 8003118: 4620 mov r0, r4 800311a: 600c str r4, [r1, #0] if (__sbrk_heap_end + incr > max_heap) 800311c: 4403 add r3, r0 800311e: 4293 cmp r3, r2 8003120: d9f7 bls.n 8003112 <_sbrk+0x16> errno = ENOMEM; 8003122: f00c fd99 bl 800fc58 <__errno> 8003126: 220c movs r2, #12 8003128: 4603 mov r3, r0 return (void *)-1; 800312a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff errno = ENOMEM; 800312e: 601a str r2, [r3, #0] } 8003130: bd10 pop {r4, pc} 8003132: bf00 nop 8003134: 24000ab4 .word 0x24000ab4 8003138: 24060000 .word 0x24060000 800313c: 00000400 .word 0x00000400 8003140: 240132e8 .word 0x240132e8 08003144 : __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8003144: 4927 ldr r1, [pc, #156] @ (80031e4 ) #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8003146: 4a28 ldr r2, [pc, #160] @ (80031e8 ) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8003148: f8d1 3088 ldr.w r3, [r1, #136] @ 0x88 800314c: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 { 8003150: b410 push {r4} SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8003152: f8c1 3088 str.w r3, [r1, #136] @ 0x88 if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8003156: 6813 ldr r3, [r2, #0] 8003158: f003 030f and.w r3, r3, #15 800315c: 2b06 cmp r3, #6 800315e: d805 bhi.n 800316c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8003160: 6813 ldr r3, [r2, #0] 8003162: f023 030f bic.w r3, r3, #15 8003166: f043 0307 orr.w r3, r3, #7 800316a: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 800316c: 4b1f ldr r3, [pc, #124] @ (80031ec ) /* Reset CFGR register */ RCC->CFGR = 0x00000000; 800316e: 2400 movs r4, #0 /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8003170: 4a1f ldr r2, [pc, #124] @ (80031f0 ) RCC->CR |= RCC_CR_HSION; 8003172: 6819 ldr r1, [r3, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8003174: 481c ldr r0, [pc, #112] @ (80031e8 ) RCC->CR |= RCC_CR_HSION; 8003176: f041 0101 orr.w r1, r1, #1 800317a: 6019 str r1, [r3, #0] RCC->CFGR = 0x00000000; 800317c: 611c str r4, [r3, #16] RCC->CR &= 0xEAF6ED7FU; 800317e: 6819 ldr r1, [r3, #0] 8003180: 400a ands r2, r1 8003182: 601a str r2, [r3, #0] if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8003184: 6803 ldr r3, [r0, #0] 8003186: 071b lsls r3, r3, #28 8003188: d505 bpl.n 8003196 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 800318a: 6803 ldr r3, [r0, #0] 800318c: f023 030f bic.w r3, r3, #15 8003190: f043 0307 orr.w r3, r3, #7 8003194: 6003 str r3, [r0, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 8003196: 4b15 ldr r3, [pc, #84] @ (80031ec ) 8003198: 2200 movs r2, #0 RCC->PLLCKSELR = 0x02020200; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 800319a: 4916 ldr r1, [pc, #88] @ (80031f4 ) RCC->PLLCKSELR = 0x02020200; 800319c: 4c16 ldr r4, [pc, #88] @ (80031f8 ) RCC->PLLCFGR = 0x01FF0000; 800319e: 4817 ldr r0, [pc, #92] @ (80031fc ) RCC->D1CFGR = 0x00000000; 80031a0: 619a str r2, [r3, #24] RCC->D2CFGR = 0x00000000; 80031a2: 61da str r2, [r3, #28] RCC->D3CFGR = 0x00000000; 80031a4: 621a str r2, [r3, #32] RCC->PLLCKSELR = 0x02020200; 80031a6: 629c str r4, [r3, #40] @ 0x28 RCC->PLLCFGR = 0x01FF0000; 80031a8: 62d8 str r0, [r3, #44] @ 0x2c RCC->PLL1DIVR = 0x01010280; 80031aa: 6319 str r1, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 80031ac: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 80031ae: 6399 str r1, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 80031b0: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 80031b2: 6419 str r1, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 80031b4: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 80031b6: 6818 ldr r0, [r3, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 80031b8: 4c11 ldr r4, [pc, #68] @ (8003200 ) RCC->CR &= 0xFFFBFFFFU; 80031ba: f420 2080 bic.w r0, r0, #262144 @ 0x40000 if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 80031be: 4911 ldr r1, [pc, #68] @ (8003204 ) RCC->CR &= 0xFFFBFFFFU; 80031c0: 6018 str r0, [r3, #0] RCC->CIER = 0x00000000; 80031c2: 661a str r2, [r3, #96] @ 0x60 if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 80031c4: 6823 ldr r3, [r4, #0] 80031c6: 4019 ands r1, r3 80031c8: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000 80031cc: d203 bcs.n 80031d6 { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 80031ce: 4b0e ldr r3, [pc, #56] @ (8003208 ) 80031d0: 2201 movs r2, #1 80031d2: f8c3 2108 str.w r2, [r3, #264] @ 0x108 /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 80031d6: 4b0d ldr r3, [pc, #52] @ (800320c ) 80031d8: f243 02d2 movw r2, #12498 @ 0x30d2 #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 80031dc: f85d 4b04 ldr.w r4, [sp], #4 FMC_Bank1_R->BTCR[0] = 0x000030D2; 80031e0: 601a str r2, [r3, #0] } 80031e2: 4770 bx lr 80031e4: e000ed00 .word 0xe000ed00 80031e8: 52002000 .word 0x52002000 80031ec: 58024400 .word 0x58024400 80031f0: eaf6ed7f .word 0xeaf6ed7f 80031f4: 01010280 .word 0x01010280 80031f8: 02020200 .word 0x02020200 80031fc: 01ff0000 .word 0x01ff0000 8003200: 5c001000 .word 0x5c001000 8003204: ffff0000 .word 0xffff0000 8003208: 51008000 .word 0x51008000 800320c: 52004000 .word 0x52004000 08003210 : xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); } void UartRxTask (void* argument) { 8003210: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8003214: b0c9 sub sp, #292 @ 0x124 8003216: 4604 mov r4, r0 UartTaskData* uartTaskData = (UartTaskData*)argument; SerialProtocolFrameData spFrameData = { 0 }; 8003218: f44f 7286 mov.w r2, #268 @ 0x10c 800321c: 2100 movs r1, #0 800321e: a805 add r0, sp, #20 8003220: f8df a2a4 ldr.w sl, [pc, #676] @ 80034c8 8003224: f00c fc70 bl 800fb08 uint32_t bytesRec = 0; 8003228: 2000 movs r0, #0 uint16_t frameTotalLength = 0; uint16_t dataToSend = 0; portBASE_TYPE crcPass = pdFAIL; portBASE_TYPE proceed = pdFALSE; portBASE_TYPE frameTimeout = pdFAIL; enum SerialReceiverStates receverState = srWaitForHeader; 800322a: 4607 mov r7, r0 uint32_t bytesRec = 0; 800322c: 9004 str r0, [sp, #16] uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 800322e: f008 fda7 bl 800bd80 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8003232: 88a2 ldrh r2, [r4, #4] uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8003234: 6220 str r0, [r4, #32] uint16_t frameTotalLength = 0; 8003236: 46b8 mov r8, r7 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8003238: 6821 ldr r1, [r4, #0] while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 800323a: 46b9 mov r9, r7 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 800323c: 6b20 ldr r0, [r4, #48] @ 0x30 portBASE_TYPE crcPass = pdFAIL; 800323e: 9703 str r7, [sp, #12] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8003240: f008 fc6c bl 800bb1c frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8003244: 2100 movs r1, #0 8003246: f44f 63fa mov.w r3, #2000 @ 0x7d0 800324a: aa04 add r2, sp, #16 800324c: 4608 mov r0, r1 800324e: f00a fe5f bl 800df10 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003252: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8003256: 4683 mov fp, r0 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003258: 6a20 ldr r0, [r4, #32] 800325a: f008 fdd3 bl 800be04 frameBytesCount = uartTaskData->frameBytesCount; 800325e: 8ae5 ldrh r5, [r4, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8003260: 6a20 ldr r0, [r4, #32] 8003262: f008 fdf3 bl 800be4c if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8003266: 1e2e subs r6, r5, #0 8003268: bf18 it ne 800326a: 2601 movne r6, #1 800326c: f1bb 0f00 cmp.w fp, #0 8003270: d14d bne.n 800330e 8003272: 2e00 cmp r6, #0 8003274: d048 beq.n 8003308 } receverState = srFinish; break; case srFail: dataToSend = 0; if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8003276: 2d02 cmp r5, #2 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8003278: 68a0 ldr r0, [r4, #8] 800327a: f8bd 1014 ldrh.w r1, [sp, #20] 800327e: f89d 2016 ldrb.w r2, [sp, #22] if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8003282: f200 80f7 bhi.w 8003474 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); #endif } else if (!crcPass) { 8003286: 9b03 ldr r3, [sp, #12] 8003288: 2b00 cmp r3, #0 800328a: f000 8098 beq.w 80033be dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 800328e: f06f 0303 mvn.w r3, #3 8003292: e9cd 9900 strd r9, r9, [sp] 8003296: f7ff fa79 bl 800278c } if (dataToSend > 0) { 800329a: 2800 cmp r0, #0 800329c: f040 809a bne.w 80033d4 #endif receverState = srFinish; break; case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80032a0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80032a4: 6a20 ldr r0, [r4, #32] 80032a6: f008 fdad bl 800be04 uartTaskData->frameBytesCount = 0; osMutexRelease (uartTaskData->rxDataBufferMutex); 80032aa: 6a20 ldr r0, [r4, #32] uartTaskData->frameBytesCount = 0; 80032ac: f8a4 9016 strh.w r9, [r4, #22] spFrameData.frameHeader.frameCommand = spUnknown; 80032b0: 2512 movs r5, #18 osMutexRelease (uartTaskData->rxDataBufferMutex); 80032b2: f008 fdcb bl 800be4c frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 80032b6: 2100 movs r1, #0 80032b8: f44f 63fa mov.w r3, #2000 @ 0x7d0 80032bc: aa04 add r2, sp, #16 80032be: 4608 mov r0, r1 spFrameData.frameHeader.frameCommand = spUnknown; 80032c0: f88d 5016 strb.w r5, [sp, #22] frameTotalLength = 0; outputDataBufferPos = 0; 80032c4: f8aa 9000 strh.w r9, [sl] frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 80032c8: f00a fe22 bl 800df10 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80032cc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 80032d0: 4607 mov r7, r0 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80032d2: 6a20 ldr r0, [r4, #32] 80032d4: f008 fd96 bl 800be04 frameBytesCount = uartTaskData->frameBytesCount; 80032d8: 8ae5 ldrh r5, [r4, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 80032da: 6a20 ldr r0, [r4, #32] 80032dc: f008 fdb6 bl 800be4c if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 80032e0: 1e2e subs r6, r5, #0 80032e2: bf18 it ne 80032e4: 2601 movne r6, #1 80032e6: 2f00 cmp r7, #0 80032e8: d17a bne.n 80033e0 80032ea: 2e00 cmp r6, #0 80032ec: d1c3 bne.n 8003276 if (frameTimeout == pdFALSE) { 80032ee: 2f00 cmp r7, #0 80032f0: d176 bne.n 80033e0 frameTotalLength = 0; 80032f2: 46b8 mov r8, r7 if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 80032f4: 6b20 ldr r0, [r4, #48] @ 0x30 80032f6: f8d0 308c ldr.w r3, [r0, #140] @ 0x8c 80032fa: 2b20 cmp r3, #32 80032fc: d1a2 bne.n 8003244 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 80032fe: 88a2 ldrh r2, [r4, #4] 8003300: 6821 ldr r1, [r4, #0] 8003302: f008 fc0b bl 800bb1c while (proceed) { 8003306: e79d b.n 8003244 if (frameTimeout == pdFALSE) { 8003308: f1bb 0f00 cmp.w fp, #0 800330c: d0f2 beq.n 80032f4 switch (receverState) { 800330e: 2f04 cmp r7, #4 8003310: d8c6 bhi.n 80032a0 8003312: e8df f007 tbb [pc, r7] 8003316: 3867 .short 0x3867 8003318: 130d .short 0x130d 800331a: 32 .byte 0x32 800331b: 00 .byte 0x00 spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 800331c: f8b3 3005 ldrh.w r3, [r3, #5] osMutexRelease (uartTaskData->rxDataBufferMutex); 8003320: 6a20 ldr r0, [r4, #32] spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 8003322: f8ad 3018 strh.w r3, [sp, #24] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8003326: 330a adds r3, #10 8003328: fa1f f883 uxth.w r8, r3 osMutexRelease (uartTaskData->rxDataBufferMutex); 800332c: f008 fd8e bl 800be4c if (frameBytesCount >= frameTotalLength) { 8003330: 45a8 cmp r8, r5 8003332: d928 bls.n 8003386 8003334: 2702 movs r7, #2 8003336: e785 b.n 8003244 crcPass = frameCrc == crc; 8003338: 2301 movs r3, #1 800333a: 9303 str r3, [sp, #12] if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 800333c: 6aa3 ldr r3, [r4, #40] @ 0x28 800333e: 2b00 cmp r3, #0 8003340: f000 8083 beq.w 800344a osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003344: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003348: 6a20 ldr r0, [r4, #32] 800334a: f008 fd5b bl 800be04 memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 800334e: 6921 ldr r1, [r4, #16] 8003350: f8bd 2018 ldrh.w r2, [sp, #24] 8003354: a808 add r0, sp, #32 8003356: 3108 adds r1, #8 8003358: f00c fcab bl 800fcb2 osMutexRelease (uartTaskData->rxDataBufferMutex); 800335c: 6a20 ldr r0, [r4, #32] 800335e: f008 fd75 bl 800be4c if (uartTaskData->processRxDataMsgBuffer != NULL) { 8003362: 6a60 ldr r0, [r4, #36] @ 0x24 8003364: 2800 cmp r0, #0 8003366: d068 beq.n 800343a if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) { 8003368: f8bd 2018 ldrh.w r2, [sp, #24] 800336c: 23c8 movs r3, #200 @ 0xc8 800336e: a905 add r1, sp, #20 8003370: 320c adds r2, #12 8003372: f009 fe73 bl 800d05c 8003376: 2800 cmp r0, #0 8003378: d15f bne.n 800343a dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 800337a: 68a0 ldr r0, [r4, #8] 800337c: f8bd 1014 ldrh.w r1, [sp, #20] 8003380: f89d 2016 ldrb.w r2, [sp, #22] 8003384: e77f b.n 8003286 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003386: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800338a: 6a20 ldr r0, [r4, #32] 800338c: f008 fd3a bl 800be04 frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8003390: 6921 ldr r1, [r4, #16] 8003392: f1a8 0202 sub.w r2, r8, #2 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8003396: 484b ldr r0, [pc, #300] @ (80034c4 ) frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8003398: 4488 add r8, r1 800339a: 5c8e ldrb r6, [r1, r2] 800339c: f818 3c01 ldrb.w r3, [r8, #-1] 80033a0: ea46 2603 orr.w r6, r6, r3, lsl #8 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 80033a4: f001 fed8 bl 8005158 80033a8: 4605 mov r5, r0 osMutexRelease (uartTaskData->rxDataBufferMutex); 80033aa: 6a20 ldr r0, [r4, #32] 80033ac: f008 fd4e bl 800be4c if (crcPass) { 80033b0: 42ae cmp r6, r5 80033b2: d0c1 beq.n 8003338 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 80033b4: 68a0 ldr r0, [r4, #8] 80033b6: f8bd 1014 ldrh.w r1, [sp, #20] 80033ba: f89d 2016 ldrb.w r2, [sp, #22] dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 80033be: f06f 0301 mvn.w r3, #1 80033c2: e9cd 9900 strd r9, r9, [sp] 80033c6: f7ff f9e1 bl 800278c 80033ca: 2300 movs r3, #0 80033cc: 9303 str r3, [sp, #12] if (dataToSend > 0) { 80033ce: 2800 cmp r0, #0 80033d0: f43f af66 beq.w 80032a0 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 80033d4: 4602 mov r2, r0 80033d6: 68a1 ldr r1, [r4, #8] 80033d8: 6b20 ldr r0, [r4, #48] @ 0x30 80033da: f007 fa37 bl 800a84c 80033de: e75f b.n 80032a0 frameTotalLength = 0; 80033e0: f04f 0800 mov.w r8, #0 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80033e4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80033e8: 6a20 ldr r0, [r4, #32] 80033ea: f008 fd0b bl 800be04 if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 80033ee: 6923 ldr r3, [r4, #16] 80033f0: 781a ldrb r2, [r3, #0] 80033f2: 2aaa cmp r2, #170 @ 0xaa 80033f4: d02e beq.n 8003454 osMutexRelease (uartTaskData->rxDataBufferMutex); 80033f6: 6a20 ldr r0, [r4, #32] if (frameBytesCount > 0) { 80033f8: 2e00 cmp r6, #0 80033fa: d142 bne.n 8003482 osMutexRelease (uartTaskData->rxDataBufferMutex); 80033fc: f008 fd26 bl 800be4c frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8003400: f44f 63fa mov.w r3, #2000 @ 0x7d0 8003404: aa04 add r2, sp, #16 8003406: 4631 mov r1, r6 8003408: 4608 mov r0, r1 800340a: f00a fd81 bl 800df10 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 800340e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8003412: 4607 mov r7, r0 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003414: 6a20 ldr r0, [r4, #32] 8003416: f008 fcf5 bl 800be04 frameBytesCount = uartTaskData->frameBytesCount; 800341a: 8ae5 ldrh r5, [r4, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 800341c: 6a20 ldr r0, [r4, #32] 800341e: f008 fd15 bl 800be4c if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8003422: 1e2e subs r6, r5, #0 8003424: bf18 it ne 8003426: 2601 movne r6, #1 8003428: 2f00 cmp r7, #0 800342a: d1db bne.n 80033e4 800342c: 2e00 cmp r6, #0 800342e: f47f af22 bne.w 8003276 if (frameTimeout == pdFALSE) { 8003432: 2f00 cmp r7, #0 8003434: d1d6 bne.n 80033e4 uint16_t frameTotalLength = 0; 8003436: 2700 movs r7, #0 8003438: e75c b.n 80032f4 if (uartTaskData->processDataCb != NULL) { 800343a: 6aa3 ldr r3, [r4, #40] @ 0x28 800343c: 2b00 cmp r3, #0 800343e: f43f af2f beq.w 80032a0 uartTaskData->processDataCb (uartTaskData, &spFrameData); 8003442: a905 add r1, sp, #20 8003444: 4620 mov r0, r4 8003446: 4798 blx r3 switch (receverState) { 8003448: e72a b.n 80032a0 if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 800344a: 6a63 ldr r3, [r4, #36] @ 0x24 800344c: 2b00 cmp r3, #0 800344e: f47f af79 bne.w 8003344 8003452: e725 b.n 80032a0 if (frameBytesCount > FRAME_ID_LENGTH) { 8003454: 2d02 cmp r5, #2 8003456: d81c bhi.n 8003492 osMutexRelease (uartTaskData->rxDataBufferMutex); 8003458: 6a20 ldr r0, [r4, #32] 800345a: f008 fcf7 bl 800be4c frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 800345e: 2100 movs r1, #0 8003460: f44f 63fa mov.w r3, #2000 @ 0x7d0 8003464: aa04 add r2, sp, #16 8003466: 4608 mov r0, r1 8003468: f00a fd52 bl 800df10 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 800346c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8003470: 4607 mov r7, r0 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003472: e7cf b.n 8003414 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8003474: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8003478: e9cd 9900 strd r9, r9, [sp] 800347c: f7ff f986 bl 800278c 8003480: e70b b.n 800329a osMutexRelease (uartTaskData->rxDataBufferMutex); 8003482: f008 fce3 bl 800be4c dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8003486: 68a0 ldr r0, [r4, #8] 8003488: f8bd 1014 ldrh.w r1, [sp, #20] 800348c: f89d 2016 ldrb.w r2, [sp, #22] 8003490: e6f9 b.n 8003286 spFrameData.frameHeader.frameId = 8003492: f8b3 2001 ldrh.w r2, [r3, #1] if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8003496: 2d04 cmp r5, #4 spFrameData.frameHeader.frameId = 8003498: f8ad 2014 strh.w r2, [sp, #20] if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 800349c: d909 bls.n 80034b2 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 800349e: f8b3 2003 ldrh.w r2, [r3, #3] if (frameBytesCount >= FRAME_HEADER_LENGTH) { 80034a2: 2d07 cmp r5, #7 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 80034a4: f88d 2016 strb.w r2, [sp, #22] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 80034a8: ea4f 32d2 mov.w r2, r2, lsr #15 80034ac: 9207 str r2, [sp, #28] if (frameBytesCount >= FRAME_HEADER_LENGTH) { 80034ae: f63f af35 bhi.w 800331c osMutexRelease (uartTaskData->rxDataBufferMutex); 80034b2: 6a20 ldr r0, [r4, #32] 80034b4: f008 fcca bl 800be4c frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 80034b8: 2100 movs r1, #0 80034ba: f44f 63fa mov.w r3, #2000 @ 0x7d0 80034be: aa04 add r2, sp, #16 80034c0: e7a2 b.n 8003408 80034c2: bf00 nop 80034c4: 240005d0 .word 0x240005d0 80034c8: 24000ab8 .word 0x24000ab8 80034cc: 00000000 .word 0x00000000 080034d0 : void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { Uart1ReceivedDataProcessCallback (arg, spFrameData); } void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 80034d0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80034d4: b093 sub sp, #76 @ 0x4c UartTaskData* uartTaskData = (UartTaskData*)arg; uint16_t dataToSend = 0; outputDataBufferPos = 0; 80034d6: 2300 movs r3, #0 80034d8: 4eb9 ldr r6, [pc, #740] @ (80037c0 ) void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 80034da: 460c mov r4, r1 80034dc: f10d 0247 add.w r2, sp, #71 @ 0x47 80034e0: 4605 mov r5, r0 outputDataBufferPos = 0; 80034e2: 8033 strh r3, [r6, #0] void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 80034e4: f022 071f bic.w r7, r2, #31 uint16_t inputDataBufferPos = 0; SerialProtocolRespStatus respStatus = spUnknownCommand; switch (spFrameData->frameHeader.frameCommand) { 80034e8: 788a ldrb r2, [r1, #2] uint16_t inputDataBufferPos = 0; 80034ea: f8ad 301e strh.w r3, [sp, #30] switch (spFrameData->frameHeader.frameCommand) { 80034ee: 2a11 cmp r2, #17 80034f0: f200 8443 bhi.w 8003d7a 80034f4: e8df f012 tbh [pc, r2, lsl #1] 80034f8: 02e8003a .word 0x02e8003a 80034fc: 02870251 .word 0x02870251 8003500: 00e800c8 .word 0x00e800c8 8003504: 03a6011a .word 0x03a6011a 8003508: 020d00a5 .word 0x020d00a5 800350c: 022801ec .word 0x022801ec 8003510: 01920141 .word 0x01920141 8003514: 03d201b2 .word 0x03d201b2 8003518: 001201d2 .word 0x001201d2 ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posXData.positionSettingValue); osMessageQueuePut(positionXControlTaskInitArg.positionSettingQueue, &posXData, 0, 0); } break; case spSetPositonY: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800351c: f8df 82d8 ldr.w r8, [pc, #728] @ 80037f8 8003520: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003524: f8d8 0000 ldr.w r0, [r8] 8003528: f008 fc6c bl 800be04 800352c: 2800 cmp r0, #0 800352e: f000 83fe beq.w 8003d2e sensorsInfo.positionYWeak = 1; osMutexRelease (sensorsInfoMutex); } PositionControlTaskData posYData __attribute__ ((aligned (32))) = { 0 }; 8003532: 2300 movs r3, #0 if (positionYControlTaskInitArg.positionSettingQueue != NULL) 8003534: f8df 82d8 ldr.w r8, [pc, #728] @ 8003810 PositionControlTaskData posYData __attribute__ ((aligned (32))) = { 0 }; 8003538: 603b str r3, [r7, #0] if (positionYControlTaskInitArg.positionSettingQueue != NULL) 800353a: f8d8 3010 ldr.w r3, [r8, #16] 800353e: 2b00 cmp r3, #0 8003540: f000 81c0 beq.w 80038c4 { ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posYData.positionSettingValue); 8003544: 463a mov r2, r7 8003546: f10d 011e add.w r1, sp, #30 800354a: f104 000c add.w r0, r4, #12 800354e: f7ff f8ed bl 800272c osMessageQueuePut(positionYControlTaskInitArg.positionSettingQueue, &posYData, 0, 0); 8003552: 2300 movs r3, #0 8003554: 4639 mov r1, r7 8003556: f8d8 0010 ldr.w r0, [r8, #16] 800355a: 461a mov r2, r3 800355c: 4f99 ldr r7, [pc, #612] @ (80037c4 ) 800355e: f008 fcd3 bl 800bf08 } break; default: respStatus = spUnknownCommand; break; } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003562: 78a2 ldrb r2, [r4, #2] 8003564: 8836 ldrh r6, [r6, #0] SerialProtocolRespStatus respStatus = spUnknownCommand; 8003566: f06f 0302 mvn.w r3, #2 800356a: e0d3 b.n 8003714 if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800356c: f8df 92a4 ldr.w r9, [pc, #676] @ 8003814 8003570: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003574: f8d9 0000 ldr.w r0, [r9] 8003578: f008 fc44 bl 800be04 800357c: 2800 cmp r0, #0 800357e: f040 809d bne.w 80036bc 8003582: f8df 8294 ldr.w r8, [pc, #660] @ 8003818 8003586: 4f8f ldr r7, [pc, #572] @ (80037c4 ) 8003588: f108 0a0c add.w sl, r8, #12 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 800358c: 46bb mov fp, r7 800358e: 4642 mov r2, r8 for (int i = 0; i < 3; i++) { 8003590: f108 0804 add.w r8, r8, #4 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 8003594: 2304 movs r3, #4 8003596: 498a ldr r1, [pc, #552] @ (80037c0 ) 8003598: 4658 mov r0, fp 800359a: f7ff f8ad bl 80026f8 for (int i = 0; i < 3; i++) { 800359e: 45d0 cmp r8, sl 80035a0: d1f5 bne.n 800358e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 80035a2: 2304 movs r3, #4 80035a4: 4a88 ldr r2, [pc, #544] @ (80037c8 ) 80035a6: 4986 ldr r1, [pc, #536] @ (80037c0 ) 80035a8: 4886 ldr r0, [pc, #536] @ (80037c4 ) 80035aa: f7ff f8a5 bl 80026f8 80035ae: 2304 movs r3, #4 80035b0: 4a86 ldr r2, [pc, #536] @ (80037cc ) 80035b2: 4983 ldr r1, [pc, #524] @ (80037c0 ) 80035b4: 4883 ldr r0, [pc, #524] @ (80037c4 ) 80035b6: f7ff f89f bl 80026f8 80035ba: 2304 movs r3, #4 80035bc: 4a84 ldr r2, [pc, #528] @ (80037d0 ) 80035be: 4980 ldr r1, [pc, #512] @ (80037c0 ) 80035c0: 4880 ldr r0, [pc, #512] @ (80037c4 ) 80035c2: f7ff f899 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 80035c6: 2304 movs r3, #4 80035c8: 4a82 ldr r2, [pc, #520] @ (80037d4 ) 80035ca: 497d ldr r1, [pc, #500] @ (80037c0 ) 80035cc: 487d ldr r0, [pc, #500] @ (80037c4 ) 80035ce: f7ff f893 bl 80026f8 80035d2: 2304 movs r3, #4 80035d4: 4a80 ldr r2, [pc, #512] @ (80037d8 ) 80035d6: 497a ldr r1, [pc, #488] @ (80037c0 ) 80035d8: 487a ldr r0, [pc, #488] @ (80037c4 ) 80035da: f7ff f88d bl 80026f8 80035de: 2304 movs r3, #4 80035e0: 4a7e ldr r2, [pc, #504] @ (80037dc ) 80035e2: 4977 ldr r1, [pc, #476] @ (80037c0 ) 80035e4: 4877 ldr r0, [pc, #476] @ (80037c4 ) 80035e6: f7ff f887 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 80035ea: 2304 movs r3, #4 80035ec: 4a7c ldr r2, [pc, #496] @ (80037e0 ) 80035ee: 4974 ldr r1, [pc, #464] @ (80037c0 ) 80035f0: 4874 ldr r0, [pc, #464] @ (80037c4 ) 80035f2: f7ff f881 bl 80026f8 80035f6: 2304 movs r3, #4 80035f8: 4a7a ldr r2, [pc, #488] @ (80037e4 ) 80035fa: 4971 ldr r1, [pc, #452] @ (80037c0 ) 80035fc: 4871 ldr r0, [pc, #452] @ (80037c4 ) 80035fe: f7ff f87b bl 80026f8 8003602: 2304 movs r3, #4 8003604: 4a78 ldr r2, [pc, #480] @ (80037e8 ) 8003606: 496e ldr r1, [pc, #440] @ (80037c0 ) 8003608: 486e ldr r0, [pc, #440] @ (80037c4 ) 800360a: f7ff f875 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 800360e: 2304 movs r3, #4 8003610: 4a76 ldr r2, [pc, #472] @ (80037ec ) 8003612: 496b ldr r1, [pc, #428] @ (80037c0 ) 8003614: 486b ldr r0, [pc, #428] @ (80037c4 ) 8003616: f7ff f86f bl 80026f8 800361a: 2304 movs r3, #4 800361c: 4a74 ldr r2, [pc, #464] @ (80037f0 ) 800361e: 4968 ldr r1, [pc, #416] @ (80037c0 ) 8003620: 4868 ldr r0, [pc, #416] @ (80037c4 ) 8003622: f7ff f869 bl 80026f8 8003626: 2304 movs r3, #4 8003628: 4a72 ldr r2, [pc, #456] @ (80037f4 ) 800362a: 4965 ldr r1, [pc, #404] @ (80037c0 ) 800362c: 4865 ldr r0, [pc, #404] @ (80037c4 ) 800362e: f7ff f863 bl 80026f8 osMutexRelease (resMeasurementsMutex); 8003632: f8d9 0000 ldr.w r0, [r9] 8003636: f008 fc09 bl 800be4c dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 800363a: 78a2 ldrb r2, [r4, #2] 800363c: 8836 ldrh r6, [r6, #0] respStatus = spOK; 800363e: 2300 movs r3, #0 8003640: e068 b.n 8003714 if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8003642: f8df 91d0 ldr.w r9, [pc, #464] @ 8003814 8003646: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800364a: f8d9 0000 ldr.w r0, [r9] 800364e: f008 fbd9 bl 800be04 8003652: 4680 mov r8, r0 8003654: bb90 cbnz r0, 80036bc resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 8003656: f8df c170 ldr.w ip, [pc, #368] @ 80037c8 800365a: 4f5a ldr r7, [pc, #360] @ (80037c4 ) 800365c: f1ac 030c sub.w r3, ip, #12 resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 8003660: f10c 0a0c add.w sl, ip, #12 8003664: f10c 0e18 add.w lr, ip, #24 resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 8003668: e893 0007 ldmia.w r3, {r0, r1, r2} 800366c: e88c 0007 stmia.w ip, {r0, r1, r2} resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 8003670: e89a 0007 ldmia.w sl, {r0, r1, r2} 8003674: e88e 0007 stmia.w lr, {r0, r1, r2} osMutexRelease (resMeasurementsMutex); 8003678: f8d9 0000 ldr.w r0, [r9] 800367c: f008 fbe6 bl 800be4c dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003680: 8836 ldrh r6, [r6, #0] respStatus = spOK; 8003682: 4643 mov r3, r8 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003684: 78a2 ldrb r2, [r4, #2] 8003686: e045 b.n 8003714 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 8003688: f101 070c add.w r7, r1, #12 int32_t motorYPWMPulse = 0; 800368c: 2300 movs r3, #0 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 800368e: aa08 add r2, sp, #32 8003690: f10d 011e add.w r1, sp, #30 8003694: 4638 mov r0, r7 int32_t motorYTimerPeriod = 0; 8003696: e9cd 3308 strd r3, r3, [sp, #32] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 800369a: f7ff f85f bl 800275c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 800369e: 4638 mov r0, r7 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80036a0: 4f55 ldr r7, [pc, #340] @ (80037f8 ) ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 80036a2: f10d 011e add.w r1, sp, #30 80036a6: aa09 add r2, sp, #36 @ 0x24 80036a8: f7ff f858 bl 800275c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80036ac: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80036b0: 6838 ldr r0, [r7, #0] 80036b2: f008 fba7 bl 800be04 80036b6: 2800 cmp r0, #0 80036b8: f000 8310 beq.w 8003cdc dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 80036bc: 78a2 ldrb r2, [r4, #2] respStatus = spInternalError; 80036be: f06f 0303 mvn.w r3, #3 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 80036c2: 8836 ldrh r6, [r6, #0] 80036c4: 4f3f ldr r7, [pc, #252] @ (80037c4 ) 80036c6: e025 b.n 8003714 float motorXMaxCurrent = 0; 80036c8: 2300 movs r3, #0 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 80036ca: aa09 add r2, sp, #36 @ 0x24 80036cc: f10d 011e add.w r1, sp, #30 80036d0: f104 000c add.w r0, r4, #12 float motorXMaxCurrent = 0; 80036d4: 9309 str r3, [sp, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 80036d6: f7ff f841 bl 800275c uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 80036da: ed9d 7a09 vldr s14, [sp, #36] @ 0x24 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 80036de: 2200 movs r2, #0 uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 80036e0: eddf 7a46 vldr s15, [pc, #280] @ 80037fc HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 80036e4: 4611 mov r1, r2 80036e6: 4846 ldr r0, [pc, #280] @ (8003800 ) uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 80036e8: ee27 7a27 vmul.f32 s14, s14, s15 80036ec: ed9f 6b32 vldr d6, [pc, #200] @ 80037b8 80036f0: eeb7 7ac7 vcvt.f64.f32 d7, s14 80036f4: ee27 7b06 vmul.f64 d7, d7, d6 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 80036f8: eefc 7bc7 vcvt.u32.f64 s15, d7 80036fc: ee17 3a90 vmov r3, s15 8003700: f001 fdf0 bl 80052e4 HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 8003704: 2100 movs r1, #0 8003706: 483e ldr r0, [pc, #248] @ (8003800 ) 8003708: f001 fdb4 bl 8005274 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 800370c: 78a2 ldrb r2, [r4, #2] respStatus = spOK; 800370e: 2300 movs r3, #0 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003710: 8836 ldrh r6, [r6, #0] 8003712: 4f2c ldr r7, [pc, #176] @ (80037c4 ) 8003714: 9601 str r6, [sp, #4] 8003716: 8821 ldrh r1, [r4, #0] 8003718: 9700 str r7, [sp, #0] 800371a: 68a8 ldr r0, [r5, #8] 800371c: f7ff f836 bl 800278c if (dataToSend > 0) { 8003720: 2800 cmp r0, #0 8003722: f040 82b3 bne.w 8003c8c HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); #endif } 8003726: b013 add sp, #76 @ 0x4c 8003728: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} float motorYMaxCurrent = 0; 800372c: 2300 movs r3, #0 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 800372e: aa09 add r2, sp, #36 @ 0x24 8003730: f10d 011e add.w r1, sp, #30 8003734: f104 000c add.w r0, r4, #12 float motorYMaxCurrent = 0; 8003738: 9309 str r3, [sp, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 800373a: f7ff f80f bl 800275c uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 800373e: ed9d 7a09 vldr s14, [sp, #36] @ 0x24 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 8003742: 2200 movs r2, #0 uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 8003744: eddf 7a2d vldr s15, [pc, #180] @ 80037fc HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 8003748: 2110 movs r1, #16 800374a: 482d ldr r0, [pc, #180] @ (8003800 ) uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 800374c: ee27 7a27 vmul.f32 s14, s14, s15 8003750: 4f1c ldr r7, [pc, #112] @ (80037c4 ) 8003752: ed9f 6b19 vldr d6, [pc, #100] @ 80037b8 8003756: eeb7 7ac7 vcvt.f64.f32 d7, s14 800375a: ee27 7b06 vmul.f64 d7, d7, d6 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 800375e: eefc 7bc7 vcvt.u32.f64 s15, d7 8003762: ee17 3a90 vmov r3, s15 8003766: f001 fdbd bl 80052e4 HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 800376a: 2110 movs r1, #16 800376c: 4824 ldr r0, [pc, #144] @ (8003800 ) 800376e: f001 fd81 bl 8005274 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003772: 78a2 ldrb r2, [r4, #2] 8003774: 8836 ldrh r6, [r6, #0] respStatus = spOK; 8003776: 2300 movs r3, #0 break; 8003778: e7cc b.n 8003714 if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800377a: f8df a098 ldr.w sl, [pc, #152] @ 8003814 800377e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003782: f8da 0000 ldr.w r0, [sl] 8003786: f008 fb3d bl 800be04 800378a: 4680 mov r8, r0 800378c: 2800 cmp r0, #0 800378e: d195 bne.n 80036bc ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 8003790: f104 090c add.w r9, r4, #12 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset); 8003794: 4a1b ldr r2, [pc, #108] @ (8003804 ) 8003796: f10d 011e add.w r1, sp, #30 800379a: 4f0a ldr r7, [pc, #40] @ (80037c4 ) 800379c: 4648 mov r0, r9 800379e: f7fe ffdd bl 800275c 80037a2: 4a19 ldr r2, [pc, #100] @ (8003808 ) 80037a4: f10d 011e add.w r1, sp, #30 80037a8: 4648 mov r0, r9 80037aa: f7fe ffd7 bl 800275c 80037ae: f10d 011e add.w r1, sp, #30 80037b2: 4648 mov r0, r9 80037b4: 4a15 ldr r2, [pc, #84] @ (800380c ) 80037b6: e0e6 b.n 8003986 80037b8: 55555555 .word 0x55555555 80037bc: 3fd55555 .word 0x3fd55555 80037c0: 24000ab8 .word 0x24000ab8 80037c4: 24000abc .word 0x24000abc 80037c8: 2400094c .word 0x2400094c 80037cc: 24000950 .word 0x24000950 80037d0: 24000954 .word 0x24000954 80037d4: 24000958 .word 0x24000958 80037d8: 2400095c .word 0x2400095c 80037dc: 24000960 .word 0x24000960 80037e0: 24000964 .word 0x24000964 80037e4: 24000968 .word 0x24000968 80037e8: 2400096c .word 0x2400096c 80037ec: 24000970 .word 0x24000970 80037f0: 24000974 .word 0x24000974 80037f4: 24000978 .word 0x24000978 80037f8: 24000980 .word 0x24000980 80037fc: 457ff000 .word 0x457ff000 8003800: 240005bc .word 0x240005bc 8003804: 2400001c .word 0x2400001c 8003808: 24000024 .word 0x24000024 800380c: 2400002c .word 0x2400002c 8003810: 240009c0 .word 0x240009c0 8003814: 24000984 .word 0x24000984 8003818: 24000940 .word 0x24000940 if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800381c: f8df a29c ldr.w sl, [pc, #668] @ 8003abc 8003820: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003824: f8da 0000 ldr.w r0, [sl] 8003828: f008 faec bl 800be04 800382c: 4680 mov r8, r0 800382e: 2800 cmp r0, #0 8003830: f47f af44 bne.w 80036bc ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 8003834: f104 090c add.w r9, r4, #12 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain); 8003838: 4a8f ldr r2, [pc, #572] @ (8003a78 ) 800383a: f10d 011e add.w r1, sp, #30 800383e: 4f8f ldr r7, [pc, #572] @ (8003a7c ) 8003840: 4648 mov r0, r9 8003842: f7fe ff8b bl 800275c 8003846: 4a8e ldr r2, [pc, #568] @ (8003a80 ) 8003848: f10d 011e add.w r1, sp, #30 800384c: 4648 mov r0, r9 800384e: f7fe ff85 bl 800275c 8003852: f10d 011e add.w r1, sp, #30 8003856: 4648 mov r0, r9 8003858: 4a8a ldr r2, [pc, #552] @ (8003a84 ) 800385a: e094 b.n 8003986 if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800385c: f8df a25c ldr.w sl, [pc, #604] @ 8003abc 8003860: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003864: f8da 0000 ldr.w r0, [sl] 8003868: f008 facc bl 800be04 800386c: 4680 mov r8, r0 800386e: 2800 cmp r0, #0 8003870: f47f af24 bne.w 80036bc ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 8003874: f104 090c add.w r9, r4, #12 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 8003878: 4a83 ldr r2, [pc, #524] @ (8003a88 ) 800387a: f10d 011e add.w r1, sp, #30 800387e: 4f7f ldr r7, [pc, #508] @ (8003a7c ) 8003880: 4648 mov r0, r9 8003882: f7fe ff6b bl 800275c 8003886: 4a81 ldr r2, [pc, #516] @ (8003a8c ) 8003888: f10d 011e add.w r1, sp, #30 800388c: 4648 mov r0, r9 800388e: f7fe ff65 bl 800275c 8003892: f10d 011e add.w r1, sp, #30 8003896: 4648 mov r0, r9 8003898: 4a7d ldr r2, [pc, #500] @ (8003a90 ) 800389a: e074 b.n 8003986 PositionControlTaskData posXData __attribute__ ((aligned (32))) = { 0 }; 800389c: 2300 movs r3, #0 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800389e: f8df 820c ldr.w r8, [pc, #524] @ 8003aac 80038a2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80038a6: f8d8 0000 ldr.w r0, [r8] PositionControlTaskData posXData __attribute__ ((aligned (32))) = { 0 }; 80038aa: 603b str r3, [r7, #0] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80038ac: f008 faaa bl 800be04 80038b0: 2800 cmp r0, #0 80038b2: f000 8233 beq.w 8003d1c if (positionXControlTaskInitArg.positionSettingQueue != NULL) 80038b6: f8df 8208 ldr.w r8, [pc, #520] @ 8003ac0 80038ba: f8d8 3010 ldr.w r3, [r8, #16] 80038be: 2b00 cmp r3, #0 80038c0: f47f ae40 bne.w 8003544 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 80038c4: 78a2 ldrb r2, [r4, #2] SerialProtocolRespStatus respStatus = spUnknownCommand; 80038c6: f06f 0302 mvn.w r3, #2 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 80038ca: 8836 ldrh r6, [r6, #0] 80038cc: 4f6b ldr r7, [pc, #428] @ (8003a7c ) 80038ce: e721 b.n 8003714 float enocoderYValue = 0; 80038d0: 2300 movs r3, #0 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80038d2: f8df 81d8 ldr.w r8, [pc, #472] @ 8003aac ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 80038d6: aa09 add r2, sp, #36 @ 0x24 80038d8: f10d 011e add.w r1, sp, #30 80038dc: f104 000c add.w r0, r4, #12 float enocoderYValue = 0; 80038e0: 9309 str r3, [sp, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 80038e2: f7fe ff3b bl 800275c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80038e6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80038ea: f8d8 0000 ldr.w r0, [r8] 80038ee: f008 fa89 bl 800be04 80038f2: 4607 mov r7, r0 80038f4: 2800 cmp r0, #0 80038f6: f47f aee1 bne.w 80036bc sensorsInfo.pvEncoderY = enocoderYValue; 80038fa: 9a09 ldr r2, [sp, #36] @ 0x24 80038fc: 4b65 ldr r3, [pc, #404] @ (8003a94 ) osMutexRelease (sensorsInfoMutex); 80038fe: f8d8 0000 ldr.w r0, [r8] sensorsInfo.pvEncoderY = enocoderYValue; 8003902: 611a str r2, [r3, #16] osMutexRelease (sensorsInfoMutex); 8003904: f008 faa2 bl 800be4c respStatus = spOK; 8003908: 463b mov r3, r7 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 800390a: 78a2 ldrb r2, [r4, #2] 800390c: 8836 ldrh r6, [r6, #0] 800390e: 4f5b ldr r7, [pc, #364] @ (8003a7c ) 8003910: e700 b.n 8003714 float enocoderXValue = 0; 8003912: 2300 movs r3, #0 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003914: f8df 8194 ldr.w r8, [pc, #404] @ 8003aac ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 8003918: aa09 add r2, sp, #36 @ 0x24 800391a: f10d 011e add.w r1, sp, #30 800391e: f104 000c add.w r0, r4, #12 float enocoderXValue = 0; 8003922: 9309 str r3, [sp, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 8003924: f7fe ff1a bl 800275c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003928: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800392c: f8d8 0000 ldr.w r0, [r8] 8003930: f008 fa68 bl 800be04 8003934: 4607 mov r7, r0 8003936: 2800 cmp r0, #0 8003938: f47f aec0 bne.w 80036bc sensorsInfo.pvEncoderX = enocoderXValue; 800393c: 9a09 ldr r2, [sp, #36] @ 0x24 800393e: 4b55 ldr r3, [pc, #340] @ (8003a94 ) osMutexRelease (sensorsInfoMutex); 8003940: f8d8 0000 ldr.w r0, [r8] sensorsInfo.pvEncoderX = enocoderXValue; 8003944: 60da str r2, [r3, #12] osMutexRelease (sensorsInfoMutex); 8003946: e7dd b.n 8003904 if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8003948: f8df a170 ldr.w sl, [pc, #368] @ 8003abc 800394c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003950: f8da 0000 ldr.w r0, [sl] 8003954: f008 fa56 bl 800be04 8003958: 4680 mov r8, r0 800395a: 2800 cmp r0, #0 800395c: f47f aeae bne.w 80036bc ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 8003960: f104 090c add.w r9, r4, #12 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain); 8003964: 4a4c ldr r2, [pc, #304] @ (8003a98 ) 8003966: f10d 011e add.w r1, sp, #30 800396a: 4f44 ldr r7, [pc, #272] @ (8003a7c ) 800396c: 4648 mov r0, r9 800396e: f7fe fef5 bl 800275c 8003972: 4a4a ldr r2, [pc, #296] @ (8003a9c ) 8003974: f10d 011e add.w r1, sp, #30 8003978: 4648 mov r0, r9 800397a: f7fe feef bl 800275c 800397e: f10d 011e add.w r1, sp, #30 8003982: 4648 mov r0, r9 8003984: 4a46 ldr r2, [pc, #280] @ (8003aa0 ) ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 8003986: f7fe fee9 bl 800275c osMutexRelease (resMeasurementsMutex); 800398a: f8da 0000 ldr.w r0, [sl] 800398e: f008 fa5d bl 800be4c dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003992: 8836 ldrh r6, [r6, #0] respStatus = spOK; 8003994: 4643 mov r3, r8 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003996: 78a2 ldrb r2, [r4, #2] 8003998: e6bc b.n 8003714 osTimerStop (fanTimerHandle); 800399a: f8df 8128 ldr.w r8, [pc, #296] @ 8003ac4 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 800399e: f104 070c add.w r7, r4, #12 osTimerStop (fanTimerHandle); 80039a2: f8d8 0000 ldr.w r0, [r8] 80039a6: f008 f9cb bl 800bd40 int32_t fanTimerPeriod = 0; 80039aa: 2300 movs r3, #0 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 80039ac: aa09 add r2, sp, #36 @ 0x24 80039ae: f10d 011e add.w r1, sp, #30 80039b2: 4638 mov r0, r7 uint32_t pulse = 0; 80039b4: e9cd 3308 strd r3, r3, [sp, #32] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 80039b8: f7fe fed0 bl 800275c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 80039bc: f10d 011e add.w r1, sp, #30 80039c0: 4638 mov r0, r7 80039c2: aa08 add r2, sp, #32 80039c4: f7fe feca bl 800275c fanTimerConfigOC.Pulse = pulse * 10; 80039c8: 9b09 ldr r3, [sp, #36] @ 0x24 80039ca: 4936 ldr r1, [pc, #216] @ (8003aa4 ) if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 80039cc: 2204 movs r2, #4 fanTimerConfigOC.Pulse = pulse * 10; 80039ce: eb03 0383 add.w r3, r3, r3, lsl #2 if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 80039d2: 4835 ldr r0, [pc, #212] @ (8003aa8 ) fanTimerConfigOC.Pulse = pulse * 10; 80039d4: 005b lsls r3, r3, #1 80039d6: 604b str r3, [r1, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 80039d8: f006 fca0 bl 800a31c 80039dc: 2800 cmp r0, #0 80039de: f040 81b0 bne.w 8003d42 if (fanTimerPeriod > 0) { 80039e2: 9f08 ldr r7, [sp, #32] 80039e4: 2f00 cmp r7, #0 80039e6: f300 8170 bgt.w 8003cca } else if (fanTimerPeriod == 0) { 80039ea: f000 81ad beq.w 8003d48 } else if (fanTimerPeriod == -1) { 80039ee: 3701 adds r7, #1 80039f0: f47f ae8c bne.w 800370c osTimerStop (fanTimerHandle); 80039f4: f8d8 0000 ldr.w r0, [r8] 80039f8: f008 f9a2 bl 800bd40 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 80039fc: 2104 movs r1, #4 80039fe: 482a ldr r0, [pc, #168] @ (8003aa8 ) 8003a00: f006 f98a bl 8009d18 8003a04: e682 b.n 800370c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 8003a06: f101 070c add.w r7, r1, #12 int32_t motorXPWMPulse = 0; 8003a0a: 2300 movs r3, #0 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 8003a0c: aa08 add r2, sp, #32 8003a0e: f10d 011e add.w r1, sp, #30 8003a12: 4638 mov r0, r7 int32_t motorXTimerPeriod = 0; 8003a14: e9cd 3308 strd r3, r3, [sp, #32] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 8003a18: f7fe fea0 bl 800275c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 8003a1c: 4638 mov r0, r7 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003a1e: 4f23 ldr r7, [pc, #140] @ (8003aac ) ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 8003a20: f10d 011e add.w r1, sp, #30 8003a24: aa09 add r2, sp, #36 @ 0x24 8003a26: f7fe fe99 bl 800275c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003a2a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003a2e: 6838 ldr r0, [r7, #0] 8003a30: f008 f9e8 bl 800be04 8003a34: 2800 cmp r0, #0 8003a36: f47f ae41 bne.w 80036bc MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8003a3a: 4b1d ldr r3, [pc, #116] @ (8003ab0 ) 8003a3c: 4602 mov r2, r0 8003a3e: f8df 8054 ldr.w r8, [pc, #84] @ 8003a94 8003a42: 681b ldr r3, [r3, #0] 8003a44: 491b ldr r1, [pc, #108] @ (8003ab4 ) 8003a46: 9300 str r3, [sp, #0] 8003a48: f898 3029 ldrb.w r3, [r8, #41] @ 0x29 8003a4c: 481a ldr r0, [pc, #104] @ (8003ab8 ) 8003a4e: 9304 str r3, [sp, #16] 8003a50: f898 3028 ldrb.w r3, [r8, #40] @ 0x28 8003a54: 9303 str r3, [sp, #12] 8003a56: 9b09 ldr r3, [sp, #36] @ 0x24 8003a58: 9302 str r3, [sp, #8] 8003a5a: 9b08 ldr r3, [sp, #32] 8003a5c: 9301 str r3, [sp, #4] 8003a5e: 2304 movs r3, #4 8003a60: f7fe fafa bl 8002058 if (motorXStatus == 1) { 8003a64: 2801 cmp r0, #1 sensorsInfo.motorXStatus = motorXStatus; 8003a66: f888 0014 strb.w r0, [r8, #20] if (motorXStatus == 1) { 8003a6a: f040 8153 bne.w 8003d14 sensorsInfo.motorXPeakCurrent = 0.0; 8003a6e: 2300 movs r3, #0 8003a70: f8c8 3020 str.w r3, [r8, #32] 8003a74: e14e b.n 8003d14 8003a76: bf00 nop 8003a78: 24000000 .word 0x24000000 8003a7c: 24000abc .word 0x24000abc 8003a80: 24000008 .word 0x24000008 8003a84: 24000010 .word 0x24000010 8003a88: 24000004 .word 0x24000004 8003a8c: 2400000c .word 0x2400000c 8003a90: 24000014 .word 0x24000014 8003a94: 24000900 .word 0x24000900 8003a98: 24000018 .word 0x24000018 8003a9c: 24000020 .word 0x24000020 8003aa0: 24000028 .word 0x24000028 8003aa4: 240002ac .word 0x240002ac 8003aa8: 2400054c .word 0x2400054c 8003aac: 24000980 .word 0x24000980 8003ab0: 24000324 .word 0x24000324 8003ab4: 24000290 .word 0x24000290 8003ab8: 24000500 .word 0x24000500 8003abc: 24000984 .word 0x24000984 8003ac0: 24000a00 .word 0x24000a00 8003ac4: 24000354 .word 0x24000354 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003ac8: f8df 92e4 ldr.w r9, [pc, #740] @ 8003db0 8003acc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003ad0: f8d9 0000 ldr.w r0, [r9] 8003ad4: f008 f996 bl 800be04 8003ad8: 4607 mov r7, r0 8003ada: 2800 cmp r0, #0 8003adc: f47f adee bne.w 80036bc WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 8003ae0: f8df 82c4 ldr.w r8, [pc, #708] @ 8003da8 8003ae4: 2304 movs r3, #4 8003ae6: 49a7 ldr r1, [pc, #668] @ (8003d84 ) 8003ae8: 48a7 ldr r0, [pc, #668] @ (8003d88 ) 8003aea: 4642 mov r2, r8 8003aec: f7fe fe04 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 8003af0: 2304 movs r3, #4 8003af2: 49a4 ldr r1, [pc, #656] @ (8003d84 ) 8003af4: eb08 0203 add.w r2, r8, r3 8003af8: 48a3 ldr r0, [pc, #652] @ (8003d88 ) 8003afa: f7fe fdfd bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 8003afe: 2304 movs r3, #4 8003b00: f108 0208 add.w r2, r8, #8 8003b04: 499f ldr r1, [pc, #636] @ (8003d84 ) 8003b06: 48a0 ldr r0, [pc, #640] @ (8003d88 ) 8003b08: f7fe fdf6 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float)); 8003b0c: 2304 movs r3, #4 8003b0e: f108 020c add.w r2, r8, #12 8003b12: 499c ldr r1, [pc, #624] @ (8003d84 ) 8003b14: 489c ldr r0, [pc, #624] @ (8003d88 ) 8003b16: f7fe fdef bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float)); 8003b1a: 2304 movs r3, #4 8003b1c: f108 0210 add.w r2, r8, #16 8003b20: 4998 ldr r1, [pc, #608] @ (8003d84 ) 8003b22: 4899 ldr r0, [pc, #612] @ (8003d88 ) 8003b24: f7fe fde8 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 8003b28: 2301 movs r3, #1 8003b2a: f108 0214 add.w r2, r8, #20 8003b2e: 4995 ldr r1, [pc, #596] @ (8003d84 ) 8003b30: 4895 ldr r0, [pc, #596] @ (8003d88 ) 8003b32: f7fe fde1 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 8003b36: 2301 movs r3, #1 8003b38: f108 0215 add.w r2, r8, #21 8003b3c: 4991 ldr r1, [pc, #580] @ (8003d84 ) 8003b3e: 4892 ldr r0, [pc, #584] @ (8003d88 ) 8003b40: f7fe fdda bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 8003b44: 2304 movs r3, #4 8003b46: f108 0218 add.w r2, r8, #24 8003b4a: 498e ldr r1, [pc, #568] @ (8003d84 ) 8003b4c: 488e ldr r0, [pc, #568] @ (8003d88 ) 8003b4e: f7fe fdd3 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 8003b52: 2304 movs r3, #4 8003b54: f108 021c add.w r2, r8, #28 8003b58: 498a ldr r1, [pc, #552] @ (8003d84 ) 8003b5a: 488b ldr r0, [pc, #556] @ (8003d88 ) 8003b5c: f7fe fdcc bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 8003b60: 2304 movs r3, #4 8003b62: f108 0220 add.w r2, r8, #32 8003b66: 4987 ldr r1, [pc, #540] @ (8003d84 ) 8003b68: 4887 ldr r0, [pc, #540] @ (8003d88 ) 8003b6a: f7fe fdc5 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 8003b6e: 2304 movs r3, #4 8003b70: f108 0224 add.w r2, r8, #36 @ 0x24 8003b74: 4983 ldr r1, [pc, #524] @ (8003d84 ) 8003b76: 4884 ldr r0, [pc, #528] @ (8003d88 ) 8003b78: f7fe fdbe bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 8003b7c: 2301 movs r3, #1 8003b7e: f108 0228 add.w r2, r8, #40 @ 0x28 8003b82: 4980 ldr r1, [pc, #512] @ (8003d84 ) 8003b84: 4880 ldr r0, [pc, #512] @ (8003d88 ) 8003b86: f7fe fdb7 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 8003b8a: 2301 movs r3, #1 8003b8c: f108 0229 add.w r2, r8, #41 @ 0x29 8003b90: 497c ldr r1, [pc, #496] @ (8003d84 ) 8003b92: 487d ldr r0, [pc, #500] @ (8003d88 ) 8003b94: f7fe fdb0 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 8003b98: 2301 movs r3, #1 8003b9a: f108 022a add.w r2, r8, #42 @ 0x2a 8003b9e: 4979 ldr r1, [pc, #484] @ (8003d84 ) 8003ba0: 4879 ldr r0, [pc, #484] @ (8003d88 ) 8003ba2: f7fe fda9 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 8003ba6: 2301 movs r3, #1 8003ba8: f108 022b add.w r2, r8, #43 @ 0x2b 8003bac: 4975 ldr r1, [pc, #468] @ (8003d84 ) 8003bae: 4876 ldr r0, [pc, #472] @ (8003d88 ) 8003bb0: f7fe fda2 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 8003bb4: 2301 movs r3, #1 8003bb6: f108 022c add.w r2, r8, #44 @ 0x2c 8003bba: 4972 ldr r1, [pc, #456] @ (8003d84 ) 8003bbc: 4872 ldr r0, [pc, #456] @ (8003d88 ) 8003bbe: f7fe fd9b bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 8003bc2: 2301 movs r3, #1 8003bc4: f108 022d add.w r2, r8, #45 @ 0x2d 8003bc8: 496e ldr r1, [pc, #440] @ (8003d84 ) 8003bca: 486f ldr r0, [pc, #444] @ (8003d88 ) 8003bcc: f7fe fd94 bl 80026f8 uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 8003bd0: 486e ldr r0, [pc, #440] @ (8003d8c ) 8003bd2: f001 f98d bl 8004ef0 8003bd6: 4682 mov sl, r0 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 8003bd8: 2108 movs r1, #8 8003bda: 486d ldr r0, [pc, #436] @ (8003d90 ) uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 8003bdc: f1aa 0a01 sub.w sl, sl, #1 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 8003be0: f003 fae6 bl 80071b0 8003be4: 4642 mov r2, r8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 8003be6: 4967 ldr r1, [pc, #412] @ (8003d84 ) uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 8003be8: faba fa8a clz sl, sl 8003bec: ea4f 1a5a mov.w sl, sl, lsr #5 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 8003bf0: ea40 034a orr.w r3, r0, sl, lsl #1 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 8003bf4: 4864 ldr r0, [pc, #400] @ (8003d88 ) sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 8003bf6: 43db mvns r3, r3 8003bf8: f003 0301 and.w r3, r3, #1 8003bfc: f802 3f2e strb.w r3, [r2, #46]! WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 8003c00: 2301 movs r3, #1 8003c02: f7fe fd79 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentXPosition, sizeof (float)); 8003c06: 2304 movs r3, #4 8003c08: f108 0230 add.w r2, r8, #48 @ 0x30 8003c0c: 495d ldr r1, [pc, #372] @ (8003d84 ) 8003c0e: 485e ldr r0, [pc, #376] @ (8003d88 ) 8003c10: f7fe fd72 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentYPosition, sizeof (float)); 8003c14: 2304 movs r3, #4 8003c16: f108 0234 add.w r2, r8, #52 @ 0x34 8003c1a: 495a ldr r1, [pc, #360] @ (8003d84 ) 8003c1c: 485a ldr r0, [pc, #360] @ (8003d88 ) 8003c1e: f7fe fd6b bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionXWeak, sizeof (uint8_t)); 8003c22: 2301 movs r3, #1 8003c24: f108 0238 add.w r2, r8, #56 @ 0x38 8003c28: 4956 ldr r1, [pc, #344] @ (8003d84 ) 8003c2a: 4857 ldr r0, [pc, #348] @ (8003d88 ) 8003c2c: f7fe fd64 bl 80026f8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionYWeak, sizeof (uint8_t)); 8003c30: 4855 ldr r0, [pc, #340] @ (8003d88 ) 8003c32: f108 0239 add.w r2, r8, #57 @ 0x39 8003c36: 2301 movs r3, #1 8003c38: 4952 ldr r1, [pc, #328] @ (8003d84 ) 8003c3a: f7fe fd5d bl 80026f8 osMutexRelease (sensorsInfoMutex); 8003c3e: f8d9 0000 ldr.w r0, [r9] 8003c42: e65f b.n 8003904 osTimerStop (debugLedTimerHandle); 8003c44: f8df 916c ldr.w r9, [pc, #364] @ 8003db4 int32_t dbgLedTimerPeriod = 0; 8003c48: 2700 movs r7, #0 osTimerStop (debugLedTimerHandle); 8003c4a: f8d9 0000 ldr.w r0, [r9] 8003c4e: f008 f877 bl 800bd40 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 8003c52: aa09 add r2, sp, #36 @ 0x24 8003c54: f10d 011e add.w r1, sp, #30 8003c58: f104 000c add.w r0, r4, #12 int32_t dbgLedTimerPeriod = 0; 8003c5c: 9709 str r7, [sp, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 8003c5e: f7fe fd7d bl 800275c if (dbgLedTimerPeriod > 0) { 8003c62: f8dd 8024 ldr.w r8, [sp, #36] @ 0x24 8003c66: 45b8 cmp r8, r7 8003c68: dc26 bgt.n 8003cb8 } else if (dbgLedTimerPeriod == 0) { 8003c6a: d07a beq.n 8003d62 } else if (dbgLedTimerPeriod == -1) { 8003c6c: f1b8 3fff cmp.w r8, #4294967295 @ 0xffffffff 8003c70: f47f ad4c bne.w 800370c osTimerStop (debugLedTimerHandle); 8003c74: f8d9 0000 ldr.w r0, [r9] 8003c78: f008 f862 bl 800bd40 DbgLEDOn (DBG_LED1); 8003c7c: 2010 movs r0, #16 8003c7e: f7fe f9ad bl 8001fdc respStatus = spOK; 8003c82: 463b mov r3, r7 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003c84: 78a2 ldrb r2, [r4, #2] 8003c86: 8836 ldrh r6, [r6, #0] 8003c88: 4f3f ldr r7, [pc, #252] @ (8003d88 ) 8003c8a: e543 b.n 8003714 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8003c8c: 4602 mov r2, r0 8003c8e: 68a9 ldr r1, [r5, #8] 8003c90: 6b28 ldr r0, [r5, #48] @ 0x30 8003c92: f006 fddb bl 800a84c } 8003c96: b013 add sp, #76 @ 0x4c 8003c98: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} __ASM volatile ("cpsid i" : : : "memory"); 8003c9c: b672 cpsid i __ASM volatile ("dsb 0xF":::"memory"); 8003c9e: f3bf 8f4f dsb sy (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8003ca2: 493c ldr r1, [pc, #240] @ (8003d94 ) SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8003ca4: 4b3c ldr r3, [pc, #240] @ (8003d98 ) (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 8003ca6: 68ca ldr r2, [r1, #12] 8003ca8: f402 62e0 and.w r2, r2, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8003cac: 4313 orrs r3, r2 8003cae: 60cb str r3, [r1, #12] 8003cb0: f3bf 8f4f dsb sy __NOP(); 8003cb4: bf00 nop for(;;) /* wait until reset */ 8003cb6: e7fd b.n 8003cb4 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 8003cb8: f44f 717a mov.w r1, #1000 @ 0x3e8 8003cbc: f8d9 0000 ldr.w r0, [r9] 8003cc0: fb01 f108 mul.w r1, r1, r8 8003cc4: f008 f824 bl 800bd10 DbgLEDOn (DBG_LED1); 8003cc8: e7d8 b.n 8003c7c osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 8003cca: f44f 717a mov.w r1, #1000 @ 0x3e8 8003cce: f8d8 0000 ldr.w r0, [r8] 8003cd2: fb07 f101 mul.w r1, r7, r1 8003cd6: f008 f81b bl 800bd10 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 8003cda: e68f b.n 80039fc MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8003cdc: 4b2f ldr r3, [pc, #188] @ (8003d9c ) 8003cde: 2208 movs r2, #8 8003ce0: f8df 80c4 ldr.w r8, [pc, #196] @ 8003da8 8003ce4: 681b ldr r3, [r3, #0] 8003ce6: 492e ldr r1, [pc, #184] @ (8003da0 ) 8003ce8: 9300 str r3, [sp, #0] 8003cea: f898 302c ldrb.w r3, [r8, #44] @ 0x2c 8003cee: 482d ldr r0, [pc, #180] @ (8003da4 ) 8003cf0: 9304 str r3, [sp, #16] 8003cf2: f898 302b ldrb.w r3, [r8, #43] @ 0x2b 8003cf6: 9303 str r3, [sp, #12] 8003cf8: 9b09 ldr r3, [sp, #36] @ 0x24 8003cfa: 9302 str r3, [sp, #8] 8003cfc: 9b08 ldr r3, [sp, #32] 8003cfe: 9301 str r3, [sp, #4] 8003d00: 230c movs r3, #12 8003d02: f7fe f9a9 bl 8002058 if (motorYStatus == 1) { 8003d06: 2801 cmp r0, #1 sensorsInfo.motorYStatus = motorYStatus; 8003d08: f888 0015 strb.w r0, [r8, #21] if (motorYStatus == 1) { 8003d0c: d102 bne.n 8003d14 sensorsInfo.motorYPeakCurrent = 0.0; 8003d0e: 2300 movs r3, #0 8003d10: f8c8 3024 str.w r3, [r8, #36] @ 0x24 osMutexRelease (sensorsInfoMutex); 8003d14: 6838 ldr r0, [r7, #0] 8003d16: f008 f899 bl 800be4c respStatus = spOK; 8003d1a: e4f7 b.n 800370c sensorsInfo.positionXWeak = 1; 8003d1c: 4b22 ldr r3, [pc, #136] @ (8003da8 ) 8003d1e: 2201 movs r2, #1 osMutexRelease (sensorsInfoMutex); 8003d20: f8d8 0000 ldr.w r0, [r8] sensorsInfo.positionXWeak = 1; 8003d24: f883 2038 strb.w r2, [r3, #56] @ 0x38 osMutexRelease (sensorsInfoMutex); 8003d28: f008 f890 bl 800be4c 8003d2c: e5c3 b.n 80038b6 sensorsInfo.positionYWeak = 1; 8003d2e: 4b1e ldr r3, [pc, #120] @ (8003da8 ) 8003d30: 2201 movs r2, #1 osMutexRelease (sensorsInfoMutex); 8003d32: f8d8 0000 ldr.w r0, [r8] sensorsInfo.positionYWeak = 1; 8003d36: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 8003d3a: f008 f887 bl 800be4c 8003d3e: f7ff bbf8 b.w 8003532 Error_Handler (); 8003d42: f7fc fd59 bl 80007f8 8003d46: e64c b.n 80039e2 osTimerStop (fanTimerHandle); 8003d48: f8d8 0000 ldr.w r0, [r8] 8003d4c: f007 fff8 bl 800bd40 HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 8003d50: 2104 movs r1, #4 8003d52: 4816 ldr r0, [pc, #88] @ (8003dac ) 8003d54: f006 f880 bl 8009e58 respStatus = spOK; 8003d58: 463b mov r3, r7 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003d5a: 78a2 ldrb r2, [r4, #2] 8003d5c: 8836 ldrh r6, [r6, #0] 8003d5e: 4f0a ldr r7, [pc, #40] @ (8003d88 ) 8003d60: e4d8 b.n 8003714 osTimerStop (debugLedTimerHandle); 8003d62: f8d9 0000 ldr.w r0, [r9] 8003d66: f007 ffeb bl 800bd40 DbgLEDOff (DBG_LED1); 8003d6a: 2010 movs r0, #16 8003d6c: f7fe f93e bl 8001fec 8003d70: 4f05 ldr r7, [pc, #20] @ (8003d88 ) dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003d72: 78a2 ldrb r2, [r4, #2] respStatus = spOK; 8003d74: 4643 mov r3, r8 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8003d76: 8836 ldrh r6, [r6, #0] 8003d78: e4cc b.n 8003714 switch (spFrameData->frameHeader.frameCommand) { 8003d7a: 2600 movs r6, #0 8003d7c: f06f 0302 mvn.w r3, #2 8003d80: 4f01 ldr r7, [pc, #4] @ (8003d88 ) 8003d82: e4c7 b.n 8003714 8003d84: 24000ab8 .word 0x24000ab8 8003d88: 24000abc .word 0x24000abc 8003d8c: 240005f4 .word 0x240005f4 8003d90: 58020c00 .word 0x58020c00 8003d94: e000ed00 .word 0xe000ed00 8003d98: 05fa0004 .word 0x05fa0004 8003d9c: 240002f4 .word 0x240002f4 8003da0: 24000290 .word 0x24000290 8003da4: 24000500 .word 0x24000500 8003da8: 24000900 .word 0x24000900 8003dac: 2400054c .word 0x2400054c 8003db0: 24000980 .word 0x24000980 8003db4: 24000384 .word 0x24000384 08003db8 : Uart1ReceivedDataProcessCallback (arg, spFrameData); 8003db8: f7ff bb8a b.w 80034d0 08003dbc : void UartTasksInit (void) { 8003dbc: b510 push {r4, lr} uart1TaskData.uartRxBuffer = uart1RxBuffer; 8003dbe: 4b1b ldr r3, [pc, #108] @ (8003e2c ) uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 8003dc0: f44f 7280 mov.w r2, #256 @ 0x100 uart1TaskData.uartRxBuffer = uart1RxBuffer; 8003dc4: 4c1a ldr r4, [pc, #104] @ (8003e30 ) void UartTasksInit (void) { 8003dc6: b08a sub sp, #40 @ 0x28 uart8TaskData.uartRxBuffer = uart8RxBuffer; 8003dc8: 481a ldr r0, [pc, #104] @ (8003e34 ) uart1TaskData.processRxDataMsgBuffer = NULL; 8003dca: 2100 movs r1, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 8003dcc: 6023 str r3, [r4, #0] uart1TaskData.uartTxBuffer = uart1TxBuffer; 8003dce: 4b1a ldr r3, [pc, #104] @ (8003e38 ) uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 8003dd0: 80a2 strh r2, [r4, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 8003dd2: 60a3 str r3, [r4, #8] uart1TaskData.frameData = uart1TaskFrameData; 8003dd4: 4b19 ldr r3, [pc, #100] @ (8003e3c ) uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 8003dd6: 82a2 strh r2, [r4, #20] uart1TaskData.frameData = uart1TaskFrameData; 8003dd8: 6123 str r3, [r4, #16] uart1TaskData.huart = &huart1; 8003dda: 4b19 ldr r3, [pc, #100] @ (8003e40 ) uart1TaskData.processRxDataMsgBuffer = NULL; 8003ddc: 6261 str r1, [r4, #36] @ 0x24 uart1TaskData.huart = &huart1; 8003dde: 6323 str r3, [r4, #48] @ 0x30 uart1TaskData.uartNumber = 1; 8003de0: 2301 movs r3, #1 8003de2: f884 3034 strb.w r3, [r4, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 8003de6: 4b17 ldr r3, [pc, #92] @ (8003e44 ) 8003de8: 62a3 str r3, [r4, #40] @ 0x28 uart8TaskData.uartRxBuffer = uart8RxBuffer; 8003dea: 4b17 ldr r3, [pc, #92] @ (8003e48 ) uart8TaskData.uartRxBufferLen = UART8_RX_BUFF_SIZE; 8003dec: 809a strh r2, [r3, #4] uart8TaskData.frameDataLen = UART8_RX_BUFF_SIZE; 8003dee: 829a strh r2, [r3, #20] uart8TaskData.huart = &huart8; 8003df0: 4a16 ldr r2, [pc, #88] @ (8003e4c ) uart8TaskData.uartRxBuffer = uart8RxBuffer; 8003df2: 6018 str r0, [r3, #0] uart8TaskData.huart = &huart8; 8003df4: 631a str r2, [r3, #48] @ 0x30 uart8TaskData.uartNumber = 8; 8003df6: 2208 movs r2, #8 uart8TaskData.uartTxBuffer = uart8TxBuffer; 8003df8: 4815 ldr r0, [pc, #84] @ (8003e50 ) uart8TaskData.uartNumber = 8; 8003dfa: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart8TaskData.uartTxBuffer = uart8TxBuffer; 8003dfe: 6098 str r0, [r3, #8] uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; 8003e00: 4a14 ldr r2, [pc, #80] @ (8003e54 ) uart8TaskData.frameData = uart8TaskFrameData; 8003e02: 4815 ldr r0, [pc, #84] @ (8003e58 ) uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; 8003e04: 629a str r2, [r3, #40] @ 0x28 osThreadAttr_t osThreadAttrRxUart = { 0 }; 8003e06: 2224 movs r2, #36 @ 0x24 uart8TaskData.frameData = uart8TaskFrameData; 8003e08: 6118 str r0, [r3, #16] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8003e0a: a801 add r0, sp, #4 uart8TaskData.processRxDataMsgBuffer = NULL; 8003e0c: 6259 str r1, [r3, #36] @ 0x24 osThreadAttr_t osThreadAttrRxUart = { 0 }; 8003e0e: f00b fe7b bl 800fb08 osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 8003e12: 2328 movs r3, #40 @ 0x28 osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8003e14: f44f 6080 mov.w r0, #1024 @ 0x400 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8003e18: aa01 add r2, sp, #4 8003e1a: 4621 mov r1, r4 osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 8003e1c: e9cd 0306 strd r0, r3, [sp, #24] uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8003e20: 480e ldr r0, [pc, #56] @ (8003e5c ) 8003e22: f007 fee3 bl 800bbec 8003e26: 61a0 str r0, [r4, #24] } 8003e28: b00a add sp, #40 @ 0x28 8003e2a: bd10 pop {r4, pc} 8003e2c: 240010ac .word 0x240010ac 8003e30: 24000b74 .word 0x24000b74 8003e34: 24000dac .word 0x24000dac 8003e38: 24000fac .word 0x24000fac 8003e3c: 24000eac .word 0x24000eac 8003e40: 2400038c .word 0x2400038c 8003e44: 080034d1 .word 0x080034d1 8003e48: 24000b3c .word 0x24000b3c 8003e4c: 24000420 .word 0x24000420 8003e50: 24000cac .word 0x24000cac 8003e54: 08003db9 .word 0x08003db9 8003e58: 24000bac .word 0x24000bac 8003e5c: 08003211 .word 0x08003211 08003e60 : void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 8003e60: 4770 bx lr 8003e62: bf00 nop 08003e64 : } 8003e64: 4770 bx lr 8003e66: bf00 nop 08003e68 : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8003e68: b570 push {r4, r5, r6, lr} 8003e6a: 4604 mov r4, r0 8003e6c: b084 sub sp, #16 BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8003e6e: 2600 movs r6, #0 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003e70: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003e74: 6a00 ldr r0, [r0, #32] void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8003e76: 4615 mov r5, r2 BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8003e78: 9603 str r6, [sp, #12] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8003e7a: f007 ffc3 bl 800be04 memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 8003e7e: 8ae3 ldrh r3, [r4, #22] 8003e80: 462a mov r2, r5 8003e82: 6920 ldr r0, [r4, #16] 8003e84: 6821 ldr r1, [r4, #0] 8003e86: 4418 add r0, r3 8003e88: f00b ff13 bl 800fcb2 uartTaskData->frameBytesCount += Size; 8003e8c: 8ae2 ldrh r2, [r4, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8003e8e: 6a20 ldr r0, [r4, #32] uartTaskData->frameBytesCount += Size; 8003e90: 442a add r2, r5 8003e92: 82e2 strh r2, [r4, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8003e94: f007 ffda bl 800be4c xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 8003e98: a803 add r0, sp, #12 8003e9a: 4633 mov r3, r6 8003e9c: 2203 movs r2, #3 8003e9e: 4629 mov r1, r5 8003ea0: 9000 str r0, [sp, #0] 8003ea2: 69a0 ldr r0, [r4, #24] 8003ea4: f00a f928 bl 800e0f8 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8003ea8: 88a2 ldrh r2, [r4, #4] 8003eaa: 6821 ldr r1, [r4, #0] 8003eac: 6b20 ldr r0, [r4, #48] @ 0x30 8003eae: f007 fe35 bl 800bb1c portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8003eb2: 9b03 ldr r3, [sp, #12] 8003eb4: b14b cbz r3, 8003eca 8003eb6: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 8003eba: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8003ebe: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 8003ec2: f3bf 8f4f dsb sy 8003ec6: f3bf 8f6f isb sy } 8003eca: b004 add sp, #16 8003ecc: bd70 pop {r4, r5, r6, pc} 8003ece: bf00 nop 08003ed0 : if (huart->Instance == USART1) { 8003ed0: 4a08 ldr r2, [pc, #32] @ (8003ef4 ) 8003ed2: 6803 ldr r3, [r0, #0] 8003ed4: 4293 cmp r3, r2 8003ed6: d003 beq.n 8003ee0 } else if (huart->Instance == UART8) { 8003ed8: 4a07 ldr r2, [pc, #28] @ (8003ef8 ) 8003eda: 4293 cmp r3, r2 8003edc: d005 beq.n 8003eea } 8003ede: 4770 bx lr HandleUartRxCallback (&uart1TaskData, huart, Size); 8003ee0: 460a mov r2, r1 8003ee2: 4601 mov r1, r0 8003ee4: 4805 ldr r0, [pc, #20] @ (8003efc ) 8003ee6: f7ff bfbf b.w 8003e68 HandleUartRxCallback (&uart8TaskData, huart, Size); 8003eea: 460a mov r2, r1 8003eec: 4601 mov r1, r0 8003eee: 4804 ldr r0, [pc, #16] @ (8003f00 ) 8003ef0: f7ff bfba b.w 8003e68 8003ef4: 40011000 .word 0x40011000 8003ef8: 40007c00 .word 0x40007c00 8003efc: 24000b74 .word 0x24000b74 8003f00: 24000b3c .word 0x24000b3c 08003f04 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8003f04: f8df d034 ldr.w sp, [pc, #52] @ 8003f3c /* Call the clock system initialization function.*/ bl SystemInit 8003f08: f7ff f91c bl 8003144 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8003f0c: 480c ldr r0, [pc, #48] @ (8003f40 ) ldr r1, =_edata 8003f0e: 490d ldr r1, [pc, #52] @ (8003f44 ) ldr r2, =_sidata 8003f10: 4a0d ldr r2, [pc, #52] @ (8003f48 ) movs r3, #0 8003f12: 2300 movs r3, #0 b LoopCopyDataInit 8003f14: e002 b.n 8003f1c 08003f16 : CopyDataInit: ldr r4, [r2, r3] 8003f16: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8003f18: 50c4 str r4, [r0, r3] adds r3, r3, #4 8003f1a: 3304 adds r3, #4 08003f1c : LoopCopyDataInit: adds r4, r0, r3 8003f1c: 18c4 adds r4, r0, r3 cmp r4, r1 8003f1e: 428c cmp r4, r1 bcc CopyDataInit 8003f20: d3f9 bcc.n 8003f16 /* Zero fill the bss segment. */ ldr r2, =_sbss 8003f22: 4a0a ldr r2, [pc, #40] @ (8003f4c ) ldr r4, =_ebss 8003f24: 4c0a ldr r4, [pc, #40] @ (8003f50 ) movs r3, #0 8003f26: 2300 movs r3, #0 b LoopFillZerobss 8003f28: e001 b.n 8003f2e 08003f2a : FillZerobss: str r3, [r2] 8003f2a: 6013 str r3, [r2, #0] adds r2, r2, #4 8003f2c: 3204 adds r2, #4 08003f2e : LoopFillZerobss: cmp r2, r4 8003f2e: 42a2 cmp r2, r4 bcc FillZerobss 8003f30: d3fb bcc.n 8003f2a /* Call static constructors */ bl __libc_init_array 8003f32: f00b fe97 bl 800fc64 <__libc_init_array> /* Call the application's entry point.*/ bl main 8003f36: f7fc fcf3 bl 8000920
bx lr 8003f3a: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8003f3c: 24060000 .word 0x24060000 ldr r0, =_sdata 8003f40: 24000000 .word 0x24000000 ldr r1, =_edata 8003f44: 24000210 .word 0x24000210 ldr r2, =_sidata 8003f48: 08011df8 .word 0x08011df8 ldr r2, =_sbss 8003f4c: 24000220 .word 0x24000220 ldr r4, =_ebss 8003f50: 240132e4 .word 0x240132e4 08003f54 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8003f54: e7fe b.n 8003f54 ... 08003f58 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8003f58: b510 push {r4, lr} __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8003f5a: 2003 movs r0, #3 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003f5c: 4c12 ldr r4, [pc, #72] @ (8003fa8 ) HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8003f5e: f000 ffd9 bl 8004f14 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8003f62: f003 fda5 bl 8007ab0 8003f66: 4b11 ldr r3, [pc, #68] @ (8003fac ) 8003f68: 4911 ldr r1, [pc, #68] @ (8003fb0 ) 8003f6a: 699a ldr r2, [r3, #24] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003f6c: 699b ldr r3, [r3, #24] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8003f6e: f3c2 2203 ubfx r2, r2, #8, #4 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003f72: f003 030f and.w r3, r3, #15 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8003f76: 5c8a ldrb r2, [r1, r2] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003f78: 5ccb ldrb r3, [r1, r3] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8003f7a: f002 021f and.w r2, r2, #31 #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8003f7e: 490d ldr r1, [pc, #52] @ (8003fb4 ) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003f80: f003 031f and.w r3, r3, #31 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8003f84: 40d0 lsrs r0, r2 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003f86: fa20 f303 lsr.w r3, r0, r3 SystemCoreClock = common_system_clock; 8003f8a: 6008 str r0, [r1, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8003f8c: 2005 movs r0, #5 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8003f8e: 6023 str r3, [r4, #0] if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8003f90: f7fe ffd4 bl 8002f3c 8003f94: b110 cbz r0, 8003f9c { return HAL_ERROR; 8003f96: 2401 movs r4, #1 /* Init the low level hardware */ HAL_MspInit(); /* Return function status */ return HAL_OK; } 8003f98: 4620 mov r0, r4 8003f9a: bd10 pop {r4, pc} 8003f9c: 4604 mov r4, r0 HAL_MspInit(); 8003f9e: f7fe fc31 bl 8002804 } 8003fa2: 4620 mov r0, r4 8003fa4: bd10 pop {r4, pc} 8003fa6: bf00 nop 8003fa8: 24000034 .word 0x24000034 8003fac: 58024400 .word 0x58024400 8003fb0: 08011a14 .word 0x08011a14 8003fb4: 24000038 .word 0x24000038 08003fb8 : * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { uwTick += (uint32_t)uwTickFreq; 8003fb8: 4a03 ldr r2, [pc, #12] @ (8003fc8 ) 8003fba: 4b04 ldr r3, [pc, #16] @ (8003fcc ) 8003fbc: 6811 ldr r1, [r2, #0] 8003fbe: 781b ldrb r3, [r3, #0] 8003fc0: 440b add r3, r1 8003fc2: 6013 str r3, [r2, #0] } 8003fc4: 4770 bx lr 8003fc6: bf00 nop 8003fc8: 240011ac .word 0x240011ac 8003fcc: 2400003c .word 0x2400003c 08003fd0 : * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { return uwTick; 8003fd0: 4b01 ldr r3, [pc, #4] @ (8003fd8 ) 8003fd2: 6818 ldr r0, [r3, #0] } 8003fd4: 4770 bx lr 8003fd6: bf00 nop 8003fd8: 240011ac .word 0x240011ac 08003fdc : * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { return((DBGMCU->IDCODE) >> 16); 8003fdc: 4b01 ldr r3, [pc, #4] @ (8003fe4 ) 8003fde: 6818 ldr r0, [r3, #0] } 8003fe0: 0c00 lsrs r0, r0, #16 8003fe2: 4770 bx lr 8003fe4: 5c001000 .word 0x5c001000 08003fe8 : void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 8003fe8: 4a03 ldr r2, [pc, #12] @ (8003ff8 ) 8003fea: 6813 ldr r3, [r2, #0] 8003fec: f023 0302 bic.w r3, r3, #2 8003ff0: 4303 orrs r3, r0 8003ff2: 6013 str r3, [r2, #0] } 8003ff4: 4770 bx lr 8003ff6: bf00 nop 8003ff8: 58003c00 .word 0x58003c00 08003ffc : * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 8003ffc: 4a02 ldr r2, [pc, #8] @ (8004008 ) 8003ffe: 6813 ldr r3, [r2, #0] 8004000: f023 0301 bic.w r3, r3, #1 8004004: 6013 str r3, [r2, #0] } 8004006: 4770 bx lr 8004008: 58003c00 .word 0x58003c00 0800400c : { /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 800400c: 4a03 ldr r2, [pc, #12] @ (800401c ) 800400e: 6853 ldr r3, [r2, #4] 8004010: ea23 0300 bic.w r3, r3, r0 8004014: 430b orrs r3, r1 8004016: 6053 str r3, [r2, #4] } 8004018: 4770 bx lr 800401a: bf00 nop 800401c: 58000400 .word 0x58000400 08004020 : /** * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) 8004020: 4770 bx lr 8004022: bf00 nop 08004024 : /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8004024: 6b80 ldr r0, [r0, #56] @ 0x38 { 8004026: b508 push {r3, lr} HAL_ADC_ConvHalfCpltCallback(hadc); 8004028: f7ff fffa bl 8004020 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800402c: bd08 pop {r3, pc} 800402e: bf00 nop 08004030 : __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) 8004030: 4770 bx lr 8004032: bf00 nop 08004034 : ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8004034: 6b83 ldr r3, [r0, #56] @ 0x38 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8004036: 6d5a ldr r2, [r3, #84] @ 0x54 8004038: f012 0f50 tst.w r2, #80 @ 0x50 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800403c: 6d5a ldr r2, [r3, #84] @ 0x54 { 800403e: b510 push {r4, lr} if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8004040: d11d bne.n 800407e if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8004042: 6819 ldr r1, [r3, #0] SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8004044: f442 7200 orr.w r2, r2, #512 @ 0x200 8004048: 655a str r2, [r3, #84] @ 0x54 if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 800404a: 680a ldr r2, [r1, #0] 800404c: f012 0f08 tst.w r2, #8 * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8004050: 68ca ldr r2, [r1, #12] 8004052: d01b beq.n 800408c 8004054: f412 6f40 tst.w r2, #3072 @ 0xc00 8004058: d10d bne.n 8004076 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 800405a: 68ca ldr r2, [r1, #12] 800405c: 0494 lsls r4, r2, #18 800405e: d40a bmi.n 8004076 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 8004060: 6d5a ldr r2, [r3, #84] @ 0x54 8004062: f422 7280 bic.w r2, r2, #256 @ 0x100 8004066: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8004068: 6d5a ldr r2, [r3, #84] @ 0x54 800406a: 04d1 lsls r1, r2, #19 800406c: d403 bmi.n 8004076 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 800406e: 6d5a ldr r2, [r3, #84] @ 0x54 8004070: f042 0201 orr.w r2, r2, #1 8004074: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_ConvCpltCallback(hadc); 8004076: 4618 mov r0, r3 8004078: f7fd f964 bl 8001344 } 800407c: bd10 pop {r4, pc} if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 800407e: 06d2 lsls r2, r2, #27 8004080: d40a bmi.n 8004098 hadc->DMA_Handle->XferErrorCallback(hdma); 8004082: 6cdb ldr r3, [r3, #76] @ 0x4c } 8004084: e8bd 4010 ldmia.w sp!, {r4, lr} hadc->DMA_Handle->XferErrorCallback(hdma); 8004088: 6cdb ldr r3, [r3, #76] @ 0x4c 800408a: 4718 bx r3 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 800408c: 0790 lsls r0, r2, #30 800408e: d0e7 beq.n 8004060 HAL_ADC_ConvCpltCallback(hadc); 8004090: 4618 mov r0, r3 8004092: f7fd f957 bl 8001344 8004096: e7f1 b.n 800407c HAL_ADC_ErrorCallback(hadc); 8004098: 4618 mov r0, r3 800409a: f7ff ffc9 bl 8004030 } 800409e: bd10 pop {r4, pc} 080040a0 : * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80040a0: 6b80 ldr r0, [r0, #56] @ 0x38 { 80040a2: b508 push {r3, lr} /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 80040a4: 6d43 ldr r3, [r0, #84] @ 0x54 80040a6: f043 0340 orr.w r3, r3, #64 @ 0x40 80040aa: 6543 str r3, [r0, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 80040ac: 6d83 ldr r3, [r0, #88] @ 0x58 80040ae: f043 0304 orr.w r3, r3, #4 80040b2: 6583 str r3, [r0, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 80040b4: f7ff ffbc bl 8004030 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 80040b8: bd08 pop {r3, pc} 80040ba: bf00 nop 080040bc : { 80040bc: b5f0 push {r4, r5, r6, r7, lr} __IO uint32_t wait_loop_index = 0; 80040be: 2200 movs r2, #0 { 80040c0: b083 sub sp, #12 __IO uint32_t wait_loop_index = 0; 80040c2: 9201 str r2, [sp, #4] __HAL_LOCK(hadc); 80040c4: f890 2050 ldrb.w r2, [r0, #80] @ 0x50 80040c8: 2a01 cmp r2, #1 80040ca: f000 8138 beq.w 800433e 80040ce: 2401 movs r4, #1 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 80040d0: 6802 ldr r2, [r0, #0] 80040d2: 4603 mov r3, r0 __HAL_LOCK(hadc); 80040d4: f880 4050 strb.w r4, [r0, #80] @ 0x50 * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80040d8: 6890 ldr r0, [r2, #8] 80040da: 0745 lsls r5, r0, #29 80040dc: d509 bpl.n 80040f2 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80040de: 6d5a ldr r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80040e0: 2001 movs r0, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80040e2: f042 0220 orr.w r2, r2, #32 80040e6: 655a str r2, [r3, #84] @ 0x54 __HAL_UNLOCK(hadc); 80040e8: 2200 movs r2, #0 80040ea: f883 2050 strb.w r2, [r3, #80] @ 0x50 } 80040ee: b003 add sp, #12 80040f0: bdf0 pop {r4, r5, r6, r7, pc} if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 80040f2: 680d ldr r5, [r1, #0] 80040f4: 2d00 cmp r5, #0 hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 80040f6: ea4f 6095 mov.w r0, r5, lsr #26 if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 80040fa: db0d blt.n 8004118 hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 80040fc: f3c5 0613 ubfx r6, r5, #0, #20 8004100: 2e00 cmp r6, #0 8004102: f000 809a beq.w 800423a uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004106: fa95 f5a5 rbit r5, r5 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 800410a: b115 cbz r5, 8004112 { return 32U; } return __builtin_clz(value); 800410c: fab5 f585 clz r5, r5 8004110: 40ac lsls r4, r5 8004112: 69d5 ldr r5, [r2, #28] 8004114: 432c orrs r4, r5 8004116: 61d4 str r4, [r2, #28] LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 8004118: 684c ldr r4, [r1, #4] MODIFY_REG(*preg, 800411a: f04f 0c1f mov.w ip, #31 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 800411e: f102 0e30 add.w lr, r2, #48 @ 0x30 MODIFY_REG(*preg, 8004122: f000 001f and.w r0, r0, #31 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 8004126: 09a5 lsrs r5, r4, #6 MODIFY_REG(*preg, 8004128: ea04 040c and.w r4, r4, ip __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 800412c: f005 050c and.w r5, r5, #12 MODIFY_REG(*preg, 8004130: fa0c fc04 lsl.w ip, ip, r4 8004134: 40a0 lsls r0, r4 8004136: f85e 4005 ldr.w r4, [lr, r5] 800413a: ea24 0c0c bic.w ip, r4, ip 800413e: ea4c 0000 orr.w r0, ip, r0 8004142: f84e 0005 str.w r0, [lr, r5] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8004146: 6890 ldr r0, [r2, #8] 8004148: f010 0f04 tst.w r0, #4 * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 800414c: 6890 ldr r0, [r2, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 800414e: d101 bne.n 8004154 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 8004150: 0700 lsls r0, r0, #28 8004152: d51a bpl.n 800418a return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8004154: 6890 ldr r0, [r2, #8] 8004156: 07c7 lsls r7, r0, #31 8004158: d415 bmi.n 8004186 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 800415a: 68ce ldr r6, [r1, #12] 800415c: 680c ldr r4, [r1, #0] MODIFY_REG(ADCx->DIFSEL, 800415e: f006 0718 and.w r7, r6, #24 8004162: 48bd ldr r0, [pc, #756] @ (8004458 ) 8004164: f8d2 50c0 ldr.w r5, [r2, #192] @ 0xc0 8004168: 40f8 lsrs r0, r7 800416a: f3c4 0713 ubfx r7, r4, #0, #20 800416e: 4020 ands r0, r4 8004170: ea25 0507 bic.w r5, r5, r7 8004174: 4328 orrs r0, r5 8004176: f8c2 00c0 str.w r0, [r2, #192] @ 0xc0 if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 800417a: 48b8 ldr r0, [pc, #736] @ (800445c ) 800417c: 4286 cmp r6, r0 800417e: f000 8091 beq.w 80042a4 if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8004182: 2c00 cmp r4, #0 8004184: db5b blt.n 800423e HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8004186: 2000 movs r0, #0 8004188: e7ae b.n 80040e8 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 800418a: 680c ldr r4, [r1, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 800418c: f102 0c14 add.w ip, r2, #20 MODIFY_REG(*preg, 8004190: f04f 0e07 mov.w lr, #7 8004194: 688e ldr r6, [r1, #8] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8004196: 0de5 lsrs r5, r4, #23 MODIFY_REG(*preg, 8004198: f3c4 5404 ubfx r4, r4, #20, #5 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 800419c: f005 0504 and.w r5, r5, #4 MODIFY_REG(*preg, 80041a0: fa0e fe04 lsl.w lr, lr, r4 80041a4: fa06 f404 lsl.w r4, r6, r4 80041a8: f85c 0005 ldr.w r0, [ip, r5] 80041ac: ea20 000e bic.w r0, r0, lr 80041b0: 4320 orrs r0, r4 80041b2: f84c 0005 str.w r0, [ip, r5] tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 80041b6: 48aa ldr r0, [pc, #680] @ (8004460 ) 80041b8: 694d ldr r5, [r1, #20] 80041ba: 6800 ldr r0, [r0, #0] 80041bc: f000 4070 and.w r0, r0, #4026531840 @ 0xf0000000 80041c0: f1b0 5f80 cmp.w r0, #268435456 @ 0x10000000 80041c4: 68d0 ldr r0, [r2, #12] 80041c6: d068 beq.n 800429a 80041c8: f010 0f10 tst.w r0, #16 80041cc: 68d0 ldr r0, [r2, #12] 80041ce: d064 beq.n 800429a 80041d0: 0840 lsrs r0, r0, #1 80041d2: f000 0008 and.w r0, r0, #8 80041d6: 4085 lsls r5, r0 if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 80041d8: 690e ldr r6, [r1, #16] LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 80041da: 6808 ldr r0, [r1, #0] if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 80041dc: 2e04 cmp r6, #4 80041de: f000 80b1 beq.w 8004344 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80041e2: f102 0c60 add.w ip, r2, #96 @ 0x60 MODIFY_REG(*preg, 80041e6: f000 44f8 and.w r4, r0, #2080374784 @ 0x7c000000 80041ea: f85c 0026 ldr.w r0, [ip, r6, lsl #2] 80041ee: f000 4000 and.w r0, r0, #2147483648 @ 0x80000000 80041f2: 4320 orrs r0, r4 80041f4: 4328 orrs r0, r5 80041f6: f84c 0026 str.w r0, [ip, r6, lsl #2] LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 80041fa: 7e4c ldrb r4, [r1, #25] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80041fc: 690d ldr r5, [r1, #16] 80041fe: f1a4 0401 sub.w r4, r4, #1 MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8004202: f85c 0025 ldr.w r0, [ip, r5, lsl #2] 8004206: fab4 f484 clz r4, r4 800420a: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000 800420e: 0964 lsrs r4, r4, #5 8004210: ea40 70c4 orr.w r0, r0, r4, lsl #31 8004214: f84c 0025 str.w r0, [ip, r5, lsl #2] LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 8004218: 7e08 ldrb r0, [r1, #24] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 800421a: 690d ldr r5, [r1, #16] 800421c: f1a0 0001 sub.w r0, r0, #1 8004220: 6914 ldr r4, [r2, #16] 8004222: f005 051f and.w r5, r5, #31 8004226: fab0 f080 clz r0, r0 800422a: f424 44f0 bic.w r4, r4, #30720 @ 0x7800 800422e: 0940 lsrs r0, r0, #5 8004230: 02c0 lsls r0, r0, #11 8004232: 40a8 lsls r0, r5 8004234: 4320 orrs r0, r4 8004236: 6110 str r0, [r2, #16] } 8004238: e78c b.n 8004154 hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 800423a: 4084 lsls r4, r0 800423c: e769 b.n 8004112 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800423e: 4989 ldr r1, [pc, #548] @ (8004464 ) 8004240: 428a cmp r2, r1 8004242: f000 80be beq.w 80043c2 8004246: f501 7180 add.w r1, r1, #256 @ 0x100 800424a: 428a cmp r2, r1 800424c: f000 80b9 beq.w 80043c2 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8004250: f101 51c0 add.w r1, r1, #402653184 @ 0x18000000 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8004254: 4d84 ldr r5, [pc, #528] @ (8004468 ) return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8004256: f501 4184 add.w r1, r1, #16896 @ 0x4200 800425a: 6888 ldr r0, [r1, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 800425c: 68ae ldr r6, [r5, #8] 800425e: 07f6 lsls r6, r6, #31 8004260: f53f af3d bmi.w 80040de if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8004264: 4e81 ldr r6, [pc, #516] @ (800446c ) return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8004266: f000 77e0 and.w r7, r0, #29360128 @ 0x1c00000 800426a: 42b4 cmp r4, r6 800426c: f000 8106 beq.w 800447c else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8004270: 4e7f ldr r6, [pc, #508] @ (8004470 ) 8004272: 42b4 cmp r4, r6 8004274: f000 80e2 beq.w 800443c else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8004278: 4d7e ldr r5, [pc, #504] @ (8004474 ) 800427a: 42ac cmp r4, r5 800427c: d183 bne.n 8004186 if (ADC_VREFINT_INSTANCE(hadc)) 800427e: 0240 lsls r0, r0, #9 8004280: d481 bmi.n 8004186 8004282: 4879 ldr r0, [pc, #484] @ (8004468 ) 8004284: 4282 cmp r2, r0 8004286: f47f af7e bne.w 8004186 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 800428a: 688a ldr r2, [r1, #8] 800428c: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000 8004290: 433a orrs r2, r7 8004292: f442 0280 orr.w r2, r2, #4194304 @ 0x400000 8004296: 608a str r2, [r1, #8] } 8004298: e775 b.n 8004186 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 800429a: f3c0 0082 ubfx r0, r0, #2, #3 800429e: 0040 lsls r0, r0, #1 80042a0: 4085 lsls r5, r0 80042a2: e799 b.n 80041d8 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 80042a4: 2f00 cmp r7, #0 80042a6: d069 beq.n 800437c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80042a8: fa94 f0a4 rbit r0, r4 if (value == 0U) 80042ac: 2800 cmp r0, #0 80042ae: f000 80a1 beq.w 80043f4 return __builtin_clz(value); 80042b2: fab0 f080 clz r0, r0 LL_ADC_SetChannelSamplingTime(hadc->Instance, 80042b6: 3001 adds r0, #1 80042b8: f000 001f and.w r0, r0, #31 80042bc: 2809 cmp r0, #9 80042be: f240 8099 bls.w 80043f4 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80042c2: fa94 f0a4 rbit r0, r4 if (value == 0U) 80042c6: 2800 cmp r0, #0 80042c8: f000 80fe beq.w 80044c8 return __builtin_clz(value); 80042cc: fab0 f080 clz r0, r0 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 80042d0: 3001 adds r0, #1 80042d2: 0680 lsls r0, r0, #26 80042d4: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80042d8: fa94 f5a4 rbit r5, r4 if (value == 0U) 80042dc: 2d00 cmp r5, #0 80042de: f000 80f1 beq.w 80044c4 return __builtin_clz(value); 80042e2: fab5 f585 clz r5, r5 80042e6: 2601 movs r6, #1 80042e8: 3501 adds r5, #1 80042ea: f005 051f and.w r5, r5, #31 80042ee: fa06 f505 lsl.w r5, r6, r5 80042f2: 4328 orrs r0, r5 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80042f4: fa94 f4a4 rbit r4, r4 if (value == 0U) 80042f8: 2c00 cmp r4, #0 80042fa: f000 80e1 beq.w 80044c0 return __builtin_clz(value); 80042fe: fab4 f484 clz r4, r4 8004302: f06f 061d mvn.w r6, #29 8004306: 1c65 adds r5, r4, #1 8004308: 2403 movs r4, #3 800430a: f005 051f and.w r5, r5, #31 800430e: fb14 6405 smlabb r4, r4, r5, r6 8004312: 0524 lsls r4, r4, #20 8004314: f044 7400 orr.w r4, r4, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8004318: 4320 orrs r0, r4 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 800431a: f102 0614 add.w r6, r2, #20 MODIFY_REG(*preg, 800431e: 2707 movs r7, #7 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8004320: 0dc5 lsrs r5, r0, #23 MODIFY_REG(*preg, 8004322: f3c0 5004 ubfx r0, r0, #20, #5 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8004326: f005 0504 and.w r5, r5, #4 MODIFY_REG(*preg, 800432a: 4087 lsls r7, r0 800432c: 5974 ldr r4, [r6, r5] 800432e: ea24 0407 bic.w r4, r4, r7 8004332: 688f ldr r7, [r1, #8] 8004334: 4087 lsls r7, r0 8004336: 433c orrs r4, r7 8004338: 5174 str r4, [r6, r5] if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 800433a: 680c ldr r4, [r1, #0] } 800433c: e721 b.n 8004182 __HAL_LOCK(hadc); 800433e: 2002 movs r0, #2 } 8004340: b003 add sp, #12 8004342: bdf0 pop {r4, r5, r6, r7, pc} if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8004344: 6e15 ldr r5, [r2, #96] @ 0x60 8004346: 0684 lsls r4, r0, #26 8004348: f005 45f8 and.w r5, r5, #2080374784 @ 0x7c000000 800434c: ebb5 6f80 cmp.w r5, r0, lsl #26 8004350: d032 beq.n 80043b8 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8004352: 6e50 ldr r0, [r2, #100] @ 0x64 8004354: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000 8004358: 4284 cmp r4, r0 800435a: d028 beq.n 80043ae if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 800435c: 6e90 ldr r0, [r2, #104] @ 0x68 800435e: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000 8004362: 4284 cmp r4, r0 8004364: d01e beq.n 80043a4 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8004366: 6ed0 ldr r0, [r2, #108] @ 0x6c 8004368: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000 800436c: 4284 cmp r4, r0 800436e: f47f aef1 bne.w 8004154 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8004372: 6ed0 ldr r0, [r2, #108] @ 0x6c 8004374: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000 8004378: 66d0 str r0, [r2, #108] @ 0x6c 800437a: e6eb b.n 8004154 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 800437c: 0ea4 lsrs r4, r4, #26 800437e: 2001 movs r0, #1 8004380: 3401 adds r4, #1 8004382: f004 051f and.w r5, r4, #31 8004386: 06a4 lsls r4, r4, #26 8004388: 40a8 lsls r0, r5 800438a: f004 44f8 and.w r4, r4, #2080374784 @ 0x7c000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 800438e: 2d09 cmp r5, #9 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8004390: ea40 0004 orr.w r0, r0, r4 8004394: eb05 0445 add.w r4, r5, r5, lsl #1 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8004398: d94e bls.n 8004438 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 800439a: 3c1e subs r4, #30 800439c: 0524 lsls r4, r4, #20 800439e: f044 7400 orr.w r4, r4, #33554432 @ 0x2000000 80043a2: e7b9 b.n 8004318 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 80043a4: 6e90 ldr r0, [r2, #104] @ 0x68 80043a6: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000 80043aa: 6690 str r0, [r2, #104] @ 0x68 80043ac: e7db b.n 8004366 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 80043ae: 6e50 ldr r0, [r2, #100] @ 0x64 80043b0: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000 80043b4: 6650 str r0, [r2, #100] @ 0x64 80043b6: e7d1 b.n 800435c CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 80043b8: 6e10 ldr r0, [r2, #96] @ 0x60 80043ba: f020 4000 bic.w r0, r0, #2147483648 @ 0x80000000 80043be: 6610 str r0, [r2, #96] @ 0x60 80043c0: e7c7 b.n 8004352 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80043c2: 4d28 ldr r5, [pc, #160] @ (8004464 ) return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 80043c4: 492c ldr r1, [pc, #176] @ (8004478 ) return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80043c6: f505 7580 add.w r5, r5, #256 @ 0x100 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 80043ca: 6888 ldr r0, [r1, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80043cc: f855 6cf8 ldr.w r6, [r5, #-248] 80043d0: 68ad ldr r5, [r5, #8] 80043d2: 07ed lsls r5, r5, #31 80043d4: f53f ae83 bmi.w 80040de if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80043d8: 07f7 lsls r7, r6, #31 80043da: f53f ae80 bmi.w 80040de if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 80043de: 4d23 ldr r5, [pc, #140] @ (800446c ) 80043e0: 42ac cmp r4, r5 80043e2: f43f aed0 beq.w 8004186 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 80043e6: 4d22 ldr r5, [pc, #136] @ (8004470 ) 80043e8: 42ac cmp r4, r5 80043ea: f43f aecc beq.w 8004186 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 80043ee: f000 77e0 and.w r7, r0, #29360128 @ 0x1c00000 80043f2: e741 b.n 8004278 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80043f4: fa94 f0a4 rbit r0, r4 if (value == 0U) 80043f8: 2800 cmp r0, #0 80043fa: d06d beq.n 80044d8 return __builtin_clz(value); 80043fc: fab0 f080 clz r0, r0 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8004400: 3001 adds r0, #1 8004402: 0680 lsls r0, r0, #26 8004404: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004408: fa94 f5a4 rbit r5, r4 if (value == 0U) 800440c: 2d00 cmp r5, #0 800440e: d061 beq.n 80044d4 return __builtin_clz(value); 8004410: fab5 f585 clz r5, r5 8004414: 2601 movs r6, #1 8004416: 3501 adds r5, #1 8004418: f005 051f and.w r5, r5, #31 800441c: fa06 f505 lsl.w r5, r6, r5 8004420: 4328 orrs r0, r5 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8004422: fa94 f4a4 rbit r4, r4 if (value == 0U) 8004426: 2c00 cmp r4, #0 8004428: d051 beq.n 80044ce return __builtin_clz(value); 800442a: fab4 f484 clz r4, r4 800442e: 3401 adds r4, #1 8004430: f004 041f and.w r4, r4, #31 8004434: eb04 0444 add.w r4, r4, r4, lsl #1 8004438: 0524 lsls r4, r4, #20 800443a: e76d b.n 8004318 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800443c: 01c4 lsls r4, r0, #7 800443e: f53f aea2 bmi.w 8004186 8004442: 42aa cmp r2, r5 8004444: f47f ae9f bne.w 8004186 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8004448: 688a ldr r2, [r1, #8] 800444a: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000 800444e: 433a orrs r2, r7 8004450: f042 7280 orr.w r2, r2, #16777216 @ 0x1000000 8004454: 608a str r2, [r1, #8] } 8004456: e696 b.n 8004186 8004458: 000fffff .word 0x000fffff 800445c: 47ff0000 .word 0x47ff0000 8004460: 5c001000 .word 0x5c001000 8004464: 40022000 .word 0x40022000 8004468: 58026000 .word 0x58026000 800446c: cb840000 .word 0xcb840000 8004470: c7520000 .word 0xc7520000 8004474: cfb80000 .word 0xcfb80000 8004478: 40022300 .word 0x40022300 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 800447c: 0206 lsls r6, r0, #8 800447e: f53f ae82 bmi.w 8004186 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8004482: 42aa cmp r2, r5 8004484: f47f ae7f bne.w 8004186 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8004488: 688a ldr r2, [r1, #8] wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800448a: 4815 ldr r0, [pc, #84] @ (80044e0 ) 800448c: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000 8004490: 433a orrs r2, r7 8004492: f442 0200 orr.w r2, r2, #8388608 @ 0x800000 8004496: 608a str r2, [r1, #8] 8004498: 6802 ldr r2, [r0, #0] 800449a: 4912 ldr r1, [pc, #72] @ (80044e4 ) 800449c: 0992 lsrs r2, r2, #6 800449e: fba1 1202 umull r1, r2, r1, r2 80044a2: 0992 lsrs r2, r2, #6 80044a4: 3201 adds r2, #1 80044a6: 0052 lsls r2, r2, #1 80044a8: 9201 str r2, [sp, #4] while (wait_loop_index != 0UL) 80044aa: 9a01 ldr r2, [sp, #4] 80044ac: 2a00 cmp r2, #0 80044ae: f43f ae6a beq.w 8004186 wait_loop_index--; 80044b2: 9a01 ldr r2, [sp, #4] 80044b4: 3a01 subs r2, #1 80044b6: 9201 str r2, [sp, #4] while (wait_loop_index != 0UL) 80044b8: 9a01 ldr r2, [sp, #4] 80044ba: 2a00 cmp r2, #0 80044bc: d1f9 bne.n 80044b2 80044be: e662 b.n 8004186 80044c0: 4c09 ldr r4, [pc, #36] @ (80044e8 ) 80044c2: e729 b.n 8004318 80044c4: 2502 movs r5, #2 80044c6: e714 b.n 80042f2 80044c8: f04f 6080 mov.w r0, #67108864 @ 0x4000000 80044cc: e704 b.n 80042d8 80044ce: f44f 1440 mov.w r4, #3145728 @ 0x300000 80044d2: e721 b.n 8004318 80044d4: 2502 movs r5, #2 80044d6: e7a3 b.n 8004420 80044d8: f04f 6080 mov.w r0, #67108864 @ 0x4000000 80044dc: e794 b.n 8004408 80044de: bf00 nop 80044e0: 24000038 .word 0x24000038 80044e4: 053e2d63 .word 0x053e2d63 80044e8: fe500000 .word 0xfe500000 080044ec : if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80044ec: 6803 ldr r3, [r0, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80044ee: 689a ldr r2, [r3, #8] 80044f0: 07d1 lsls r1, r2, #31 80044f2: d501 bpl.n 80044f8 return HAL_OK; 80044f4: 2000 movs r0, #0 } 80044f6: 4770 bx lr if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 80044f8: 6899 ldr r1, [r3, #8] 80044fa: 4a23 ldr r2, [pc, #140] @ (8004588 ) 80044fc: 4211 tst r1, r2 { 80044fe: b570 push {r4, r5, r6, lr} 8004500: 4604 mov r4, r0 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8004502: d12f bne.n 8004564 MODIFY_REG(ADCx->CR, 8004504: 6899 ldr r1, [r3, #8] 8004506: 4a21 ldr r2, [pc, #132] @ (800458c ) 8004508: 400a ands r2, r1 800450a: f042 0201 orr.w r2, r2, #1 800450e: 609a str r2, [r3, #8] tickstart = HAL_GetTick(); 8004510: f7ff fd5e bl 8003fd0 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8004514: 6823 ldr r3, [r4, #0] 8004516: 4a1e ldr r2, [pc, #120] @ (8004590 ) tickstart = HAL_GetTick(); 8004518: 4605 mov r5, r0 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800451a: 4293 cmp r3, r2 800451c: d02c beq.n 8004578 800451e: f502 7280 add.w r2, r2, #256 @ 0x100 8004522: 4293 cmp r3, r2 8004524: d028 beq.n 8004578 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8004526: f102 52c0 add.w r2, r2, #402653184 @ 0x18000000 800452a: f502 4284 add.w r2, r2, #16896 @ 0x4200 800452e: 6892 ldr r2, [r2, #8] while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8004530: 681a ldr r2, [r3, #0] 8004532: 07d2 lsls r2, r2, #31 8004534: d414 bmi.n 8004560 MODIFY_REG(ADCx->CR, 8004536: 4e15 ldr r6, [pc, #84] @ (800458c ) return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8004538: 689a ldr r2, [r3, #8] 800453a: 07d0 lsls r0, r2, #31 800453c: d404 bmi.n 8004548 MODIFY_REG(ADCx->CR, 800453e: 689a ldr r2, [r3, #8] 8004540: 4032 ands r2, r6 8004542: f042 0201 orr.w r2, r2, #1 8004546: 609a str r2, [r3, #8] if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8004548: f7ff fd42 bl 8003fd0 800454c: 1b43 subs r3, r0, r5 800454e: 2b02 cmp r3, #2 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8004550: 6823 ldr r3, [r4, #0] if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8004552: d902 bls.n 800455a if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8004554: 681a ldr r2, [r3, #0] 8004556: 07d1 lsls r1, r2, #31 8004558: d504 bpl.n 8004564 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 800455a: 681a ldr r2, [r3, #0] 800455c: 07d2 lsls r2, r2, #31 800455e: d5eb bpl.n 8004538 return HAL_OK; 8004560: 2000 movs r0, #0 } 8004562: bd70 pop {r4, r5, r6, pc} SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004564: 6d63 ldr r3, [r4, #84] @ 0x54 return HAL_ERROR; 8004566: 2001 movs r0, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004568: f043 0310 orr.w r3, r3, #16 800456c: 6563 str r3, [r4, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800456e: 6da3 ldr r3, [r4, #88] @ 0x58 8004570: f043 0301 orr.w r3, r3, #1 8004574: 65a3 str r3, [r4, #88] @ 0x58 } 8004576: bd70 pop {r4, r5, r6, pc} return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8004578: 4a06 ldr r2, [pc, #24] @ (8004594 ) 800457a: 6892 ldr r2, [r2, #8] || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 800457c: 06d6 lsls r6, r2, #27 800457e: d0d7 beq.n 8004530 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8004580: 4a05 ldr r2, [pc, #20] @ (8004598 ) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8004582: 4293 cmp r3, r2 8004584: d1d4 bne.n 8004530 8004586: e7eb b.n 8004560 8004588: 8000003f .word 0x8000003f 800458c: 7fffffc0 .word 0x7fffffc0 8004590: 40022000 .word 0x40022000 8004594: 40022300 .word 0x40022300 8004598: 40022100 .word 0x40022100 0800459c : { 800459c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 80045a0: 4b3c ldr r3, [pc, #240] @ (8004694 ) { 80045a2: 4604 mov r4, r0 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 80045a4: 6800 ldr r0, [r0, #0] { 80045a6: 460e mov r6, r1 80045a8: 4617 mov r7, r2 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 80045aa: 4298 cmp r0, r3 80045ac: d05f beq.n 800466e 80045ae: f503 7380 add.w r3, r3, #256 @ 0x100 80045b2: 4298 cmp r0, r3 80045b4: d05b beq.n 800466e 80045b6: 4b38 ldr r3, [pc, #224] @ (8004698 ) 80045b8: 689b ldr r3, [r3, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80045ba: 6885 ldr r5, [r0, #8] 80045bc: f015 0504 ands.w r5, r5, #4 80045c0: d15b bne.n 800467a __HAL_LOCK(hadc); 80045c2: f894 2050 ldrb.w r2, [r4, #80] @ 0x50 80045c6: 2a01 cmp r2, #1 80045c8: d057 beq.n 800467a return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 80045ca: f003 081f and.w r8, r3, #31 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80045ce: f240 2321 movw r3, #545 @ 0x221 __HAL_LOCK(hadc); 80045d2: 2001 movs r0, #1 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80045d4: fa23 f308 lsr.w r3, r3, r8 __HAL_LOCK(hadc); 80045d8: f884 0050 strb.w r0, [r4, #80] @ 0x50 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 80045dc: 4003 ands r3, r0 80045de: d053 beq.n 8004688 tmp_hal_status = ADC_Enable(hadc); 80045e0: 4620 mov r0, r4 80045e2: f7ff ff83 bl 80044ec if (tmp_hal_status == HAL_OK) 80045e6: 2800 cmp r0, #0 80045e8: d14a bne.n 8004680 ADC_STATE_CLR_SET(hadc->State, 80045ea: 6d62 ldr r2, [r4, #84] @ 0x54 80045ec: 4b2b ldr r3, [pc, #172] @ (800469c ) if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 80045ee: 6821 ldr r1, [r4, #0] ADC_STATE_CLR_SET(hadc->State, 80045f0: 4013 ands r3, r2 80045f2: f443 7380 orr.w r3, r3, #256 @ 0x100 80045f6: 6563 str r3, [r4, #84] @ 0x54 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80045f8: f1b8 0f00 cmp.w r8, #0 80045fc: d002 beq.n 8004604 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 80045fe: 4b28 ldr r3, [pc, #160] @ (80046a0 ) || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8004600: 4299 cmp r1, r3 8004602: d003 beq.n 800460c CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8004604: 6d63 ldr r3, [r4, #84] @ 0x54 8004606: f423 1380 bic.w r3, r3, #1048576 @ 0x100000 800460a: 6563 str r3, [r4, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 800460c: 6d63 ldr r3, [r4, #84] @ 0x54 800460e: f413 5380 ands.w r3, r3, #4096 @ 0x1000 8004612: d03d beq.n 8004690 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8004614: 6da3 ldr r3, [r4, #88] @ 0x58 8004616: f023 0306 bic.w r3, r3, #6 800461a: 65a3 str r3, [r4, #88] @ 0x58 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 800461c: 6ce0 ldr r0, [r4, #76] @ 0x4c tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800461e: 4632 mov r2, r6 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8004620: 4d20 ldr r5, [pc, #128] @ (80046a4 ) tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8004622: 463b mov r3, r7 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 8004624: 6ae6 ldr r6, [r4, #44] @ 0x2c 8004626: 3140 adds r1, #64 @ 0x40 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8004628: 63c5 str r5, [r0, #60] @ 0x3c hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 800462a: 4d1f ldr r5, [pc, #124] @ (80046a8 ) 800462c: 6405 str r5, [r0, #64] @ 0x40 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800462e: 4d1f ldr r5, [pc, #124] @ (80046ac ) 8004630: 64c5 str r5, [r0, #76] @ 0x4c __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8004632: 251c movs r5, #28 8004634: f841 5c40 str.w r5, [r1, #-64] __HAL_UNLOCK(hadc); 8004638: 2500 movs r5, #0 800463a: f884 5050 strb.w r5, [r4, #80] @ 0x50 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 800463e: f851 5c3c ldr.w r5, [r1, #-60] 8004642: f045 0510 orr.w r5, r5, #16 8004646: f841 5c3c str.w r5, [r1, #-60] 800464a: f851 5c34 ldr.w r5, [r1, #-52] 800464e: f025 0503 bic.w r5, r5, #3 8004652: 4335 orrs r5, r6 8004654: f841 5c34 str.w r5, [r1, #-52] tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8004658: f001 fab0 bl 8005bbc LL_ADC_REG_StartConversion(hadc->Instance); 800465c: 6822 ldr r2, [r4, #0] MODIFY_REG(ADCx->CR, 800465e: 4b14 ldr r3, [pc, #80] @ (80046b0 ) 8004660: 6891 ldr r1, [r2, #8] 8004662: 400b ands r3, r1 8004664: f043 0304 orr.w r3, r3, #4 8004668: 6093 str r3, [r2, #8] } 800466a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800466e: 4b11 ldr r3, [pc, #68] @ (80046b4 ) return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8004670: 689b ldr r3, [r3, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8004672: 6885 ldr r5, [r0, #8] 8004674: f015 0504 ands.w r5, r5, #4 8004678: d0a3 beq.n 80045c2 __HAL_LOCK(hadc); 800467a: 2002 movs r0, #2 } 800467c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_UNLOCK(hadc); 8004680: f884 5050 strb.w r5, [r4, #80] @ 0x50 } 8004684: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __HAL_UNLOCK(hadc); 8004688: f884 3050 strb.w r3, [r4, #80] @ 0x50 } 800468c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} ADC_CLEAR_ERRORCODE(hadc); 8004690: 65a3 str r3, [r4, #88] @ 0x58 8004692: e7c3 b.n 800461c 8004694: 40022000 .word 0x40022000 8004698: 58026300 .word 0x58026300 800469c: fffff0fe .word 0xfffff0fe 80046a0: 40022100 .word 0x40022100 80046a4: 08004035 .word 0x08004035 80046a8: 08004025 .word 0x08004025 80046ac: 080040a1 .word 0x080040a1 80046b0: 7fffffc0 .word 0x7fffffc0 80046b4: 40022300 .word 0x40022300 080046b8 : { 80046b8: b538 push {r3, r4, r5, lr} const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 80046ba: 6803 ldr r3, [r0, #0] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 80046bc: 689a ldr r2, [r3, #8] 80046be: 0795 lsls r5, r2, #30 80046c0: d502 bpl.n 80046c8 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80046c2: 689b ldr r3, [r3, #8] return HAL_OK; 80046c4: 2000 movs r0, #0 } 80046c6: bd38 pop {r3, r4, r5, pc} 80046c8: 689a ldr r2, [r3, #8] 80046ca: 07d4 lsls r4, r2, #31 80046cc: d5fa bpl.n 80046c4 if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 80046ce: 689a ldr r2, [r3, #8] 80046d0: 4604 mov r4, r0 80046d2: f002 020d and.w r2, r2, #13 80046d6: 2a01 cmp r2, #1 80046d8: d009 beq.n 80046ee SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80046da: 6d63 ldr r3, [r4, #84] @ 0x54 return HAL_ERROR; 80046dc: 2001 movs r0, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80046de: f043 0310 orr.w r3, r3, #16 80046e2: 6563 str r3, [r4, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80046e4: 6da3 ldr r3, [r4, #88] @ 0x58 80046e6: f043 0301 orr.w r3, r3, #1 80046ea: 65a3 str r3, [r4, #88] @ 0x58 } 80046ec: bd38 pop {r3, r4, r5, pc} MODIFY_REG(ADCx->CR, 80046ee: 6898 ldr r0, [r3, #8] __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 80046f0: 2103 movs r1, #3 80046f2: 4a0d ldr r2, [pc, #52] @ (8004728 ) 80046f4: 4002 ands r2, r0 80046f6: f042 0202 orr.w r2, r2, #2 80046fa: 609a str r2, [r3, #8] 80046fc: 6019 str r1, [r3, #0] tickstart = HAL_GetTick(); 80046fe: f7ff fc67 bl 8003fd0 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8004702: 6823 ldr r3, [r4, #0] tickstart = HAL_GetTick(); 8004704: 4605 mov r5, r0 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8004706: 689b ldr r3, [r3, #8] 8004708: 07d9 lsls r1, r3, #31 800470a: d403 bmi.n 8004714 800470c: e7da b.n 80046c4 800470e: 689b ldr r3, [r3, #8] 8004710: 07db lsls r3, r3, #31 8004712: d5d7 bpl.n 80046c4 if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8004714: f7ff fc5c bl 8003fd0 8004718: 1b40 subs r0, r0, r5 if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 800471a: 6823 ldr r3, [r4, #0] if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800471c: 2802 cmp r0, #2 800471e: d9f6 bls.n 800470e if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8004720: 689a ldr r2, [r3, #8] 8004722: 07d2 lsls r2, r2, #31 8004724: d5f3 bpl.n 800470e 8004726: e7d8 b.n 80046da 8004728: 7fffffc0 .word 0x7fffffc0 0800472c : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 800472c: b538 push {r3, r4, r5, lr} uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 800472e: 4a56 ldr r2, [pc, #344] @ (8004888 ) { 8004730: 4604 mov r4, r0 if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 8004732: 6803 ldr r3, [r0, #0] 8004734: 4293 cmp r3, r2 8004736: d025 beq.n 8004784 8004738: f502 7280 add.w r2, r2, #256 @ 0x100 800473c: 4293 cmp r3, r2 800473e: d021 beq.n 8004784 8004740: 4b52 ldr r3, [pc, #328] @ (800488c ) 8004742: 689b ldr r3, [r3, #8] 8004744: f413 3f40 tst.w r3, #196608 @ 0x30000 8004748: d021 beq.n 800478e { freq = HAL_RCC_GetHCLKFreq(); 800474a: f003 fb69 bl 8007e20 switch (hadc->Init.ClockPrescaler) 800474e: 6863 ldr r3, [r4, #4] freq = HAL_RCC_GetHCLKFreq(); 8004750: 4605 mov r5, r0 switch (hadc->Init.ClockPrescaler) 8004752: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8004756: f000 8086 beq.w 8004866 800475a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800475e: d06f beq.n 8004840 8004760: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004764: d07f beq.n 8004866 else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 8004766: f7ff fc39 bl 8003fdc 800476a: f241 0303 movw r3, #4099 @ 0x1003 800476e: 4298 cmp r0, r3 8004770: d84b bhi.n 800480a { if (freq > 20000000UL) 8004772: 4a47 ldr r2, [pc, #284] @ (8004890 ) { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 8004774: 6823 ldr r3, [r4, #0] if (freq > 20000000UL) 8004776: 4295 cmp r5, r2 8004778: d92a bls.n 80047d0 SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 800477a: 689a ldr r2, [r3, #8] 800477c: f442 7280 orr.w r2, r2, #256 @ 0x100 8004780: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 8004782: bd38 pop {r3, r4, r5, pc} if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 8004784: 4b43 ldr r3, [pc, #268] @ (8004894 ) 8004786: 689b ldr r3, [r3, #8] 8004788: f413 3f40 tst.w r3, #196608 @ 0x30000 800478c: d1dd bne.n 800474a freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 800478e: f44f 2000 mov.w r0, #524288 @ 0x80000 8004792: 2100 movs r1, #0 8004794: f004 fe52 bl 800943c switch (hadc->Init.ClockPrescaler) 8004798: 6863 ldr r3, [r4, #4] freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 800479a: 4605 mov r5, r0 switch (hadc->Init.ClockPrescaler) 800479c: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 80047a0: d06b beq.n 800487a 80047a2: d808 bhi.n 80047b6 80047a4: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 80047a8: d054 beq.n 8004854 80047aa: d916 bls.n 80047da 80047ac: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80047b0: d1d9 bne.n 8004766 freq /= 32UL; 80047b2: 0945 lsrs r5, r0, #5 break; 80047b4: e7d7 b.n 8004766 switch (hadc->Init.ClockPrescaler) 80047b6: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 80047ba: d049 beq.n 8004850 80047bc: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 80047c0: d1d1 bne.n 8004766 if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 80047c2: f7ff fc0b bl 8003fdc 80047c6: f241 0303 movw r3, #4099 @ 0x1003 80047ca: 4298 cmp r0, r3 80047cc: d82e bhi.n 800482c 80047ce: 6823 ldr r3, [r4, #0] CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80047d0: 689a ldr r2, [r3, #8] 80047d2: f422 7280 bic.w r2, r2, #256 @ 0x100 80047d6: 609a str r2, [r3, #8] } 80047d8: bd38 pop {r3, r4, r5, pc} switch (hadc->Init.ClockPrescaler) 80047da: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80047de: d006 beq.n 80047ee 80047e0: d90a bls.n 80047f8 80047e2: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 80047e6: d002 beq.n 80047ee 80047e8: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 80047ec: d1bb bne.n 8004766 freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 80047ee: 0c9b lsrs r3, r3, #18 80047f0: 005b lsls r3, r3, #1 80047f2: fbb5 f5f3 udiv r5, r5, r3 break; 80047f6: e7b6 b.n 8004766 switch (hadc->Init.ClockPrescaler) 80047f8: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 80047fc: d0f7 beq.n 80047ee 80047fe: f423 2200 bic.w r2, r3, #524288 @ 0x80000 8004802: f5b2 2f80 cmp.w r2, #262144 @ 0x40000 8004806: d0f2 beq.n 80047ee 8004808: e7ad b.n 8004766 if (freq <= 6250000UL) 800480a: 4a23 ldr r2, [pc, #140] @ (8004898 ) SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 800480c: 6823 ldr r3, [r4, #0] if (freq <= 6250000UL) 800480e: 4295 cmp r5, r2 8004810: d911 bls.n 8004836 else if (freq <= 12500000UL) 8004812: 4a22 ldr r2, [pc, #136] @ (800489c ) 8004814: 4295 cmp r5, r2 8004816: d91f bls.n 8004858 else if (freq <= 25000000UL) 8004818: 4a21 ldr r2, [pc, #132] @ (80048a0 ) 800481a: 4295 cmp r5, r2 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 800481c: 689a ldr r2, [r3, #8] else if (freq <= 25000000UL) 800481e: d82e bhi.n 800487e MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 8004820: f422 7240 bic.w r2, r2, #768 @ 0x300 8004824: f442 7200 orr.w r2, r2, #512 @ 0x200 8004828: 609a str r2, [r3, #8] } 800482a: bd38 pop {r3, r4, r5, pc} if (freq <= 6250000UL) 800482c: 4b1a ldr r3, [pc, #104] @ (8004898 ) 800482e: ebb3 2f15 cmp.w r3, r5, lsr #8 8004832: 6823 ldr r3, [r4, #0] 8004834: d310 bcc.n 8004858 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 8004836: 689a ldr r2, [r3, #8] 8004838: f422 7240 bic.w r2, r2, #768 @ 0x300 800483c: 609a str r2, [r3, #8] } 800483e: bd38 pop {r3, r4, r5, pc} freq /= 4UL; 8004840: 0885 lsrs r5, r0, #2 if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 8004842: f7ff fbcb bl 8003fdc 8004846: f241 0303 movw r3, #4099 @ 0x1003 800484a: 4298 cmp r0, r3 800484c: d8dd bhi.n 800480a 800484e: e790 b.n 8004772 freq /= 128UL; 8004850: 09c5 lsrs r5, r0, #7 break; 8004852: e788 b.n 8004766 freq /= 16UL; 8004854: 0905 lsrs r5, r0, #4 break; 8004856: e786 b.n 8004766 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 8004858: 689a ldr r2, [r3, #8] 800485a: f422 7240 bic.w r2, r2, #768 @ 0x300 800485e: f442 7280 orr.w r2, r2, #256 @ 0x100 8004862: 609a str r2, [r3, #8] } 8004864: bd38 pop {r3, r4, r5, pc} freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 8004866: 0c1b lsrs r3, r3, #16 8004868: fbb5 f5f3 udiv r5, r5, r3 if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 800486c: f7ff fbb6 bl 8003fdc 8004870: f241 0303 movw r3, #4099 @ 0x1003 8004874: 4298 cmp r0, r3 8004876: d8c8 bhi.n 800480a 8004878: e77b b.n 8004772 freq /= 64UL; 800487a: 0985 lsrs r5, r0, #6 break; 800487c: e773 b.n 8004766 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 800487e: f442 7240 orr.w r2, r2, #768 @ 0x300 8004882: 609a str r2, [r3, #8] } 8004884: bd38 pop {r3, r4, r5, pc} 8004886: bf00 nop 8004888: 40022000 .word 0x40022000 800488c: 58026300 .word 0x58026300 8004890: 01312d00 .word 0x01312d00 8004894: 40022300 .word 0x40022300 8004898: 00bebc21 .word 0x00bebc21 800489c: 017d7841 .word 0x017d7841 80048a0: 02faf081 .word 0x02faf081 080048a4 : { 80048a4: b570 push {r4, r5, r6, lr} __IO uint32_t wait_loop_index = 0UL; 80048a6: 2300 movs r3, #0 { 80048a8: b082 sub sp, #8 __IO uint32_t wait_loop_index = 0UL; 80048aa: 9301 str r3, [sp, #4] if (hadc == NULL) 80048ac: 2800 cmp r0, #0 80048ae: f000 80a9 beq.w 8004a04 if (hadc->State == HAL_ADC_STATE_RESET) 80048b2: 6d45 ldr r5, [r0, #84] @ 0x54 80048b4: 4604 mov r4, r0 80048b6: 2d00 cmp r5, #0 80048b8: f000 80aa beq.w 8004a10 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 80048bc: 6822 ldr r2, [r4, #0] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 80048be: 6893 ldr r3, [r2, #8] 80048c0: 009e lsls r6, r3, #2 80048c2: d503 bpl.n 80048cc CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 80048c4: 6891 ldr r1, [r2, #8] 80048c6: 4b71 ldr r3, [pc, #452] @ (8004a8c ) 80048c8: 400b ands r3, r1 80048ca: 6093 str r3, [r2, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 80048cc: 6893 ldr r3, [r2, #8] 80048ce: 00dd lsls r5, r3, #3 80048d0: d416 bmi.n 8004900 wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80048d2: 4b6f ldr r3, [pc, #444] @ (8004a90 ) 80048d4: 496f ldr r1, [pc, #444] @ (8004a94 ) 80048d6: 681b ldr r3, [r3, #0] MODIFY_REG(ADCx->CR, 80048d8: 6890 ldr r0, [r2, #8] 80048da: 099b lsrs r3, r3, #6 80048dc: fba1 1303 umull r1, r3, r1, r3 80048e0: 496d ldr r1, [pc, #436] @ (8004a98 ) 80048e2: 099b lsrs r3, r3, #6 80048e4: 4001 ands r1, r0 80048e6: 3301 adds r3, #1 80048e8: f041 5180 orr.w r1, r1, #268435456 @ 0x10000000 80048ec: 6091 str r1, [r2, #8] 80048ee: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 80048f0: 9b01 ldr r3, [sp, #4] 80048f2: b12b cbz r3, 8004900 wait_loop_index--; 80048f4: 9b01 ldr r3, [sp, #4] 80048f6: 3b01 subs r3, #1 80048f8: 9301 str r3, [sp, #4] while (wait_loop_index != 0UL) 80048fa: 9b01 ldr r3, [sp, #4] 80048fc: 2b00 cmp r3, #0 80048fe: d1f9 bne.n 80048f4 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 8004900: 6893 ldr r3, [r2, #8] 8004902: 00d8 lsls r0, r3, #3 8004904: f100 8082 bmi.w 8004a0c SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004908: 6d63 ldr r3, [r4, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 800490a: 2501 movs r5, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800490c: f043 0310 orr.w r3, r3, #16 8004910: 6563 str r3, [r4, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8004912: 6da3 ldr r3, [r4, #88] @ 0x58 8004914: 432b orrs r3, r5 8004916: 65a3 str r3, [r4, #88] @ 0x58 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8004918: 6893 ldr r3, [r2, #8] 800491a: f013 0f04 tst.w r3, #4 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 800491e: 6d63 ldr r3, [r4, #84] @ 0x54 8004920: d16c bne.n 80049fc 8004922: 06d9 lsls r1, r3, #27 8004924: d46a bmi.n 80049fc ADC_STATE_CLR_SET(hadc->State, 8004926: 6d63 ldr r3, [r4, #84] @ 0x54 8004928: f423 7381 bic.w r3, r3, #258 @ 0x102 800492c: f043 0302 orr.w r3, r3, #2 8004930: 6563 str r3, [r4, #84] @ 0x54 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8004932: 6893 ldr r3, [r2, #8] 8004934: 07db lsls r3, r3, #31 8004936: d40c bmi.n 8004952 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8004938: 4b58 ldr r3, [pc, #352] @ (8004a9c ) 800493a: 429a cmp r2, r3 800493c: f000 8081 beq.w 8004a42 8004940: f503 7380 add.w r3, r3, #256 @ 0x100 8004944: 429a cmp r2, r3 8004946: d07c beq.n 8004a42 8004948: 4b55 ldr r3, [pc, #340] @ (8004aa0 ) 800494a: 689b ldr r3, [r3, #8] 800494c: 07d9 lsls r1, r3, #31 800494e: f140 8089 bpl.w 8004a64 if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8004952: f7ff fb43 bl 8003fdc 8004956: f241 0303 movw r3, #4099 @ 0x1003 800495a: 68a1 ldr r1, [r4, #8] 800495c: 4298 cmp r0, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 800495e: 7f23 ldrb r3, [r4, #28] if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8004960: d85c bhi.n 8004a1c tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8004962: f894 c015 ldrb.w ip, [r4, #21] ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8004966: 041a lsls r2, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8004968: 6b20 ldr r0, [r4, #48] @ 0x30 800496a: ea42 324c orr.w r2, r2, ip, lsl #13 800496e: 4302 orrs r2, r0 8004970: 430a orrs r2, r1 if (hadc->Init.DiscontinuousConvMode == ENABLE) 8004972: 2b01 cmp r3, #1 8004974: d103 bne.n 800497e tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8004976: 6a23 ldr r3, [r4, #32] 8004978: 3b01 subs r3, #1 800497a: ea42 4243 orr.w r2, r2, r3, lsl #17 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 800497e: 6a63 ldr r3, [r4, #36] @ 0x24 8004980: b123 cbz r3, 800498c tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8004982: f403 7378 and.w r3, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 8004986: 6aa1 ldr r1, [r4, #40] @ 0x28 8004988: 430b orrs r3, r1 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 800498a: 431a orrs r2, r3 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 800498c: 6823 ldr r3, [r4, #0] 800498e: 4945 ldr r1, [pc, #276] @ (8004aa4 ) 8004990: 68d8 ldr r0, [r3, #12] 8004992: 4001 ands r1, r0 8004994: 4311 orrs r1, r2 8004996: 60d9 str r1, [r3, #12] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8004998: 689a ldr r2, [r3, #8] 800499a: f012 0f04 tst.w r2, #4 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 800499e: 689a ldr r2, [r3, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80049a0: d11c bne.n 80049dc return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 80049a2: 0712 lsls r2, r2, #28 80049a4: d41a bmi.n 80049dc MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 80049a6: 68d8 ldr r0, [r3, #12] 80049a8: 4a3f ldr r2, [pc, #252] @ (8004aa8 ) ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 80049aa: 7d21 ldrb r1, [r4, #20] MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 80049ac: 4002 ands r2, r0 80049ae: ea42 3281 orr.w r2, r2, r1, lsl #14 80049b2: 6ae1 ldr r1, [r4, #44] @ 0x2c 80049b4: 430a orrs r2, r1 80049b6: 60da str r2, [r3, #12] if (hadc->Init.OversamplingMode == ENABLE) 80049b8: f894 2038 ldrb.w r2, [r4, #56] @ 0x38 80049bc: 2a01 cmp r2, #1 80049be: d053 beq.n 8004a68 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 80049c0: 691a ldr r2, [r3, #16] 80049c2: f022 0201 bic.w r2, r2, #1 80049c6: 611a str r2, [r3, #16] MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 80049c8: 691a ldr r2, [r3, #16] ADC_ConfigureBoostMode(hadc); 80049ca: 4620 mov r0, r4 MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 80049cc: 6b61 ldr r1, [r4, #52] @ 0x34 80049ce: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000 80049d2: 430a orrs r2, r1 80049d4: 611a str r2, [r3, #16] ADC_ConfigureBoostMode(hadc); 80049d6: f7ff fea9 bl 800472c MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 80049da: 6823 ldr r3, [r4, #0] if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 80049dc: 68e2 ldr r2, [r4, #12] 80049de: 2a01 cmp r2, #1 80049e0: d027 beq.n 8004a32 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 80049e2: 6b1a ldr r2, [r3, #48] @ 0x30 80049e4: f022 020f bic.w r2, r2, #15 80049e8: 631a str r2, [r3, #48] @ 0x30 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 80049ea: 6d63 ldr r3, [r4, #84] @ 0x54 } 80049ec: 4628 mov r0, r5 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 80049ee: f023 0303 bic.w r3, r3, #3 80049f2: f043 0301 orr.w r3, r3, #1 80049f6: 6563 str r3, [r4, #84] @ 0x54 } 80049f8: b002 add sp, #8 80049fa: bd70 pop {r4, r5, r6, pc} SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80049fc: 6d63 ldr r3, [r4, #84] @ 0x54 80049fe: f043 0310 orr.w r3, r3, #16 8004a02: 6563 str r3, [r4, #84] @ 0x54 return HAL_ERROR; 8004a04: 2501 movs r5, #1 } 8004a06: 4628 mov r0, r5 8004a08: b002 add sp, #8 8004a0a: bd70 pop {r4, r5, r6, pc} HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8004a0c: 2500 movs r5, #0 8004a0e: e783 b.n 8004918 HAL_ADC_MspInit(hadc); 8004a10: f7fd ff42 bl 8002898 ADC_CLEAR_ERRORCODE(hadc); 8004a14: 65a5 str r5, [r4, #88] @ 0x58 hadc->Lock = HAL_UNLOCKED; 8004a16: f884 5050 strb.w r5, [r4, #80] @ 0x50 8004a1a: e74f b.n 80048bc if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8004a1c: 2910 cmp r1, #16 8004a1e: d1a0 bne.n 8004962 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8004a20: 7d61 ldrb r1, [r4, #21] ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8004a22: 041a lsls r2, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8004a24: ea42 3241 orr.w r2, r2, r1, lsl #13 8004a28: 6b21 ldr r1, [r4, #48] @ 0x30 8004a2a: 430a orrs r2, r1 8004a2c: f042 021c orr.w r2, r2, #28 8004a30: e79f b.n 8004972 MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8004a32: 6b19 ldr r1, [r3, #48] @ 0x30 8004a34: 69a2 ldr r2, [r4, #24] 8004a36: f021 010f bic.w r1, r1, #15 8004a3a: 3a01 subs r2, #1 8004a3c: 430a orrs r2, r1 8004a3e: 631a str r2, [r3, #48] @ 0x30 8004a40: e7d3 b.n 80049ea return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8004a42: 4a16 ldr r2, [pc, #88] @ (8004a9c ) 8004a44: 4b19 ldr r3, [pc, #100] @ (8004aac ) 8004a46: 6892 ldr r2, [r2, #8] 8004a48: 689b ldr r3, [r3, #8] 8004a4a: 07de lsls r6, r3, #31 8004a4c: d481 bmi.n 8004952 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8004a4e: 07d0 lsls r0, r2, #31 8004a50: f53f af7f bmi.w 8004952 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 8004a54: 4a16 ldr r2, [pc, #88] @ (8004ab0 ) MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8004a56: 6893 ldr r3, [r2, #8] 8004a58: 6861 ldr r1, [r4, #4] 8004a5a: f423 137c bic.w r3, r3, #4128768 @ 0x3f0000 8004a5e: 430b orrs r3, r1 8004a60: 6093 str r3, [r2, #8] } 8004a62: e776 b.n 8004952 8004a64: 4a13 ldr r2, [pc, #76] @ (8004ab4 ) 8004a66: e7f6 b.n 8004a56 MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 8004a68: e9d4 120f ldrd r1, r2, [r4, #60] @ 0x3c 8004a6c: 6c66 ldr r6, [r4, #68] @ 0x44 8004a6e: 3901 subs r1, #1 8004a70: 6918 ldr r0, [r3, #16] 8004a72: 4332 orrs r2, r6 8004a74: ea42 4201 orr.w r2, r2, r1, lsl #16 8004a78: 6ca1 ldr r1, [r4, #72] @ 0x48 8004a7a: 430a orrs r2, r1 8004a7c: 490e ldr r1, [pc, #56] @ (8004ab8 ) 8004a7e: 4001 ands r1, r0 8004a80: 430a orrs r2, r1 8004a82: f042 0201 orr.w r2, r2, #1 8004a86: 611a str r2, [r3, #16] 8004a88: e79e b.n 80049c8 8004a8a: bf00 nop 8004a8c: 5fffffc0 .word 0x5fffffc0 8004a90: 24000038 .word 0x24000038 8004a94: 053e2d63 .word 0x053e2d63 8004a98: 6fffffc0 .word 0x6fffffc0 8004a9c: 40022000 .word 0x40022000 8004aa0: 58026000 .word 0x58026000 8004aa4: fff0c003 .word 0xfff0c003 8004aa8: ffffbffc .word 0xffffbffc 8004aac: 40022100 .word 0x40022100 8004ab0: 40022300 .word 0x40022300 8004ab4: 58026300 .word 0x58026300 8004ab8: fc00f81e .word 0xfc00f81e 08004abc : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 8004abc: b5f0 push {r4, r5, r6, r7, lr} HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 8004abe: 2300 movs r3, #0 { 8004ac0: b083 sub sp, #12 __IO uint32_t wait_loop_index = 0UL; 8004ac2: 9301 str r3, [sp, #4] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 8004ac4: f890 3050 ldrb.w r3, [r0, #80] @ 0x50 8004ac8: 2b01 cmp r3, #1 8004aca: d040 beq.n 8004b4e 8004acc: 2301 movs r3, #1 8004ace: 4604 mov r4, r0 8004ad0: 460e mov r6, r1 8004ad2: 4615 mov r5, r2 8004ad4: f880 3050 strb.w r3, [r0, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8004ad8: f7ff fdee bl 80046b8 /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8004adc: b9e8 cbnz r0, 8004b1a { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8004ade: 6d67 ldr r7, [r4, #84] @ 0x54 MODIFY_REG(ADCx->CR, 8004ae0: f005 4280 and.w r2, r5, #1073741824 @ 0x40000000 8004ae4: 4b1b ldr r3, [pc, #108] @ (8004b54 ) 8004ae6: f406 3180 and.w r1, r6, #65536 @ 0x10000 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 8004aea: 6825 ldr r5, [r4, #0] ADC_STATE_CLR_SET(hadc->State, 8004aec: 403b ands r3, r7 8004aee: f043 0302 orr.w r3, r3, #2 8004af2: 6563 str r3, [r4, #84] @ 0x54 8004af4: 4b18 ldr r3, [pc, #96] @ (8004b58 ) 8004af6: 68ae ldr r6, [r5, #8] 8004af8: 4033 ands r3, r6 8004afa: 4313 orrs r3, r2 8004afc: 430b orrs r3, r1 8004afe: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8004b02: 60ab str r3, [r5, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8004b04: 68ab ldr r3, [r5, #8] /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { wait_loop_index++; if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8004b06: 4a15 ldr r2, [pc, #84] @ (8004b5c ) 8004b08: 2b00 cmp r3, #0 8004b0a: db0f blt.n 8004b2c return HAL_ERROR; } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8004b0c: 6d63 ldr r3, [r4, #84] @ 0x54 8004b0e: f023 0303 bic.w r3, r3, #3 8004b12: f043 0301 orr.w r3, r3, #1 8004b16: 6563 str r3, [r4, #84] @ 0x54 8004b18: e003 b.n 8004b22 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8004b1a: 6d63 ldr r3, [r4, #84] @ 0x54 8004b1c: f043 0310 orr.w r3, r3, #16 8004b20: 6563 str r3, [r4, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8004b22: 2300 movs r3, #0 8004b24: f884 3050 strb.w r3, [r4, #80] @ 0x50 /* Return function status */ return tmp_hal_status; } 8004b28: b003 add sp, #12 8004b2a: bdf0 pop {r4, r5, r6, r7, pc} wait_loop_index++; 8004b2c: 9b01 ldr r3, [sp, #4] 8004b2e: 3301 adds r3, #1 8004b30: 9301 str r3, [sp, #4] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8004b32: 9b01 ldr r3, [sp, #4] 8004b34: 4293 cmp r3, r2 8004b36: d3e5 bcc.n 8004b04 ADC_STATE_CLR_SET(hadc->State, 8004b38: 6d63 ldr r3, [r4, #84] @ 0x54 __HAL_UNLOCK(hadc); 8004b3a: 2200 movs r2, #0 return HAL_ERROR; 8004b3c: 2001 movs r0, #1 ADC_STATE_CLR_SET(hadc->State, 8004b3e: f023 0312 bic.w r3, r3, #18 __HAL_UNLOCK(hadc); 8004b42: f884 2050 strb.w r2, [r4, #80] @ 0x50 ADC_STATE_CLR_SET(hadc->State, 8004b46: f043 0310 orr.w r3, r3, #16 8004b4a: 6563 str r3, [r4, #84] @ 0x54 return HAL_ERROR; 8004b4c: e7ec b.n 8004b28 __HAL_LOCK(hadc); 8004b4e: 2002 movs r0, #2 } 8004b50: b003 add sp, #12 8004b52: bdf0 pop {r4, r5, r6, r7, pc} 8004b54: ffffeefd .word 0xffffeefd 8004b58: 3ffeffc0 .word 0x3ffeffc0 8004b5c: 25c3f800 .word 0x25c3f800 08004b60 : * @param pData Destination Buffer address. * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 8004b60: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) 8004b64: 6806 ldr r6, [r0, #0] { 8004b66: b09a sub sp, #104 @ 0x68 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8004b68: 68b5 ldr r5, [r6, #8] 8004b6a: f015 0504 ands.w r5, r5, #4 8004b6e: d11c bne.n 8004baa return HAL_BUSY; } else { /* Process locked */ __HAL_LOCK(hadc); 8004b70: f890 3050 ldrb.w r3, [r0, #80] @ 0x50 8004b74: 4604 mov r4, r0 8004b76: 2b01 cmp r3, #1 8004b78: d017 beq.n 8004baa /* Case of ADC slave using its own DMA channel: check whether handle selected corresponds to ADC master or slave instance */ if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance) 8004b7a: 4b2f ldr r3, [pc, #188] @ (8004c38 ) __HAL_LOCK(hadc); 8004b7c: f04f 0c01 mov.w ip, #1 8004b80: 460f mov r7, r1 8004b82: 4690 mov r8, r2 if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance) 8004b84: 429e cmp r6, r3 __HAL_LOCK(hadc); 8004b86: f880 c050 strb.w ip, [r0, #80] @ 0x50 if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance) 8004b8a: d018 beq.n 8004bbe else { tmphadcSlave.State = HAL_ADC_STATE_RESET; tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8004b8c: 4a2b ldr r2, [pc, #172] @ (8004c3c ) tmphadcSlave.State = HAL_ADC_STATE_RESET; 8004b8e: 9516 str r5, [sp, #88] @ 0x58 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8004b90: 4296 cmp r6, r2 tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 8004b92: 9517 str r5, [sp, #92] @ 0x5c ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8004b94: d00d beq.n 8004bb2 if (tmphadcSlave.Instance == NULL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8004b96: 6d43 ldr r3, [r0, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; 8004b98: 4660 mov r0, ip __HAL_UNLOCK(hadc); 8004b9a: f884 5050 strb.w r5, [r4, #80] @ 0x50 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8004b9e: f043 0320 orr.w r3, r3, #32 8004ba2: 6563 str r3, [r4, #84] @ 0x54 } /* Return function status */ return tmp_hal_status; } } 8004ba4: b01a add sp, #104 @ 0x68 8004ba6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} return HAL_BUSY; 8004baa: 2002 movs r0, #2 } 8004bac: b01a add sp, #104 @ 0x68 8004bae: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8004bb2: 9301 str r3, [sp, #4] tmp_hal_status = ADC_Enable(hadc); 8004bb4: f7ff fc9a bl 80044ec if (tmp_hal_status == HAL_OK) 8004bb8: 2800 cmp r0, #0 8004bba: d132 bne.n 8004c22 tmp_hal_status = ADC_Enable(&tmphadcSlave); 8004bbc: a801 add r0, sp, #4 8004bbe: f7ff fc95 bl 80044ec if (tmp_hal_status == HAL_OK) 8004bc2: 2800 cmp r0, #0 8004bc4: d12d bne.n 8004c22 ADC_STATE_CLR_SET(hadc->State, 8004bc6: 6d62 ldr r2, [r4, #84] @ 0x54 8004bc8: 4b1d ldr r3, [pc, #116] @ (8004c40 ) hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8004bca: 6ce6 ldr r6, [r4, #76] @ 0x4c ADC_STATE_CLR_SET(hadc->State, 8004bcc: 4013 ands r3, r2 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8004bce: 6825 ldr r5, [r4, #0] tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); 8004bd0: 463a mov r2, r7 ADC_STATE_CLR_SET(hadc->State, 8004bd2: f443 7380 orr.w r3, r3, #256 @ 0x100 8004bd6: 6563 str r3, [r4, #84] @ 0x54 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8004bd8: 4b1a ldr r3, [pc, #104] @ (8004c44 ) ADC_CLEAR_ERRORCODE(hadc); 8004bda: 65a0 str r0, [r4, #88] @ 0x58 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8004bdc: 63f3 str r3, [r6, #60] @ 0x3c hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8004bde: 4b1a ldr r3, [pc, #104] @ (8004c48 ) 8004be0: 6433 str r3, [r6, #64] @ 0x40 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; 8004be2: 4b1a ldr r3, [pc, #104] @ (8004c4c ) 8004be4: 64f3 str r3, [r6, #76] @ 0x4c __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8004be6: 231c movs r3, #28 8004be8: 602b str r3, [r5, #0] __HAL_UNLOCK(hadc); 8004bea: f884 0050 strb.w r0, [r4, #80] @ 0x50 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 8004bee: 686b ldr r3, [r5, #4] 8004bf0: f043 0310 orr.w r3, r3, #16 8004bf4: 606b str r3, [r5, #4] if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance) 8004bf6: 4b10 ldr r3, [pc, #64] @ (8004c38 ) 8004bf8: 429d cmp r5, r3 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); 8004bfa: 4643 mov r3, r8 if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance) 8004bfc: d017 beq.n 8004c2e tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); 8004bfe: 4630 mov r0, r6 tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 8004c00: 4f0e ldr r7, [pc, #56] @ (8004c3c ) 8004c02: 4913 ldr r1, [pc, #76] @ (8004c50 ) 8004c04: 4e13 ldr r6, [pc, #76] @ (8004c54 ) 8004c06: 42bd cmp r5, r7 8004c08: bf08 it eq 8004c0a: 4631 moveq r1, r6 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); 8004c0c: 310c adds r1, #12 8004c0e: f000 ffd5 bl 8005bbc LL_ADC_REG_StartConversion(hadc->Instance); 8004c12: 6822 ldr r2, [r4, #0] MODIFY_REG(ADCx->CR, 8004c14: 4b10 ldr r3, [pc, #64] @ (8004c58 ) 8004c16: 6891 ldr r1, [r2, #8] 8004c18: 400b ands r3, r1 8004c1a: f043 0304 orr.w r3, r3, #4 8004c1e: 6093 str r3, [r2, #8] } 8004c20: e7c4 b.n 8004bac __HAL_UNLOCK(hadc); 8004c22: 2300 movs r3, #0 8004c24: f884 3050 strb.w r3, [r4, #80] @ 0x50 } 8004c28: b01a add sp, #104 @ 0x68 8004c2a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8004c2e: 490b ldr r1, [pc, #44] @ (8004c5c ) 8004c30: 4630 mov r0, r6 8004c32: f000 ffc3 bl 8005bbc 8004c36: e7b9 b.n 8004bac 8004c38: 40022100 .word 0x40022100 8004c3c: 40022000 .word 0x40022000 8004c40: fffff0fe .word 0xfffff0fe 8004c44: 08004035 .word 0x08004035 8004c48: 08004025 .word 0x08004025 8004c4c: 080040a1 .word 0x080040a1 8004c50: 58026300 .word 0x58026300 8004c54: 40022300 .word 0x40022300 8004c58: 7fffffc0 .word 0x7fffffc0 8004c5c: 40022140 .word 0x40022140 08004c60 : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 8004c60: b4f0 push {r4, r5, r6, r7} assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8004c62: f890 2050 ldrb.w r2, [r0, #80] @ 0x50 { 8004c66: b09a sub sp, #104 @ 0x68 if (multimode->Mode != ADC_MODE_INDEPENDENT) 8004c68: 680e ldr r6, [r1, #0] __HAL_LOCK(hadc); 8004c6a: 2a01 cmp r2, #1 8004c6c: d038 beq.n 8004ce0 8004c6e: 4603 mov r3, r0 tmphadcSlave.State = HAL_ADC_STATE_RESET; tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8004c70: 4d28 ldr r5, [pc, #160] @ (8004d14 ) tmphadcSlave.State = HAL_ADC_STATE_RESET; 8004c72: 2200 movs r2, #0 __HAL_LOCK(hadc); 8004c74: 2001 movs r0, #1 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8004c76: 681c ldr r4, [r3, #0] tmphadcSlave.State = HAL_ADC_STATE_RESET; 8004c78: 9216 str r2, [sp, #88] @ 0x58 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8004c7a: 42ac cmp r4, r5 __HAL_LOCK(hadc); 8004c7c: f883 0050 strb.w r0, [r3, #80] @ 0x50 tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 8004c80: 9217 str r2, [sp, #92] @ 0x5c ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8004c82: d008 beq.n 8004c96 if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8004c84: 6d59 ldr r1, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 8004c86: f883 2050 strb.w r2, [r3, #80] @ 0x50 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8004c8a: f041 0120 orr.w r1, r1, #32 8004c8e: 6559 str r1, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; } 8004c90: b01a add sp, #104 @ 0x68 8004c92: bcf0 pop {r4, r5, r6, r7} 8004c94: 4770 bx lr return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8004c96: 4a20 ldr r2, [pc, #128] @ (8004d18 ) 8004c98: 6890 ldr r0, [r2, #8] 8004c9a: 0740 lsls r0, r0, #29 8004c9c: d50b bpl.n 8004cb6 8004c9e: 68a2 ldr r2, [r4, #8] SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8004ca0: 6d5a ldr r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8004ca2: 2001 movs r0, #1 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8004ca4: f042 0220 orr.w r2, r2, #32 8004ca8: 655a str r2, [r3, #84] @ 0x54 __HAL_UNLOCK(hadc); 8004caa: 2200 movs r2, #0 8004cac: f883 2050 strb.w r2, [r3, #80] @ 0x50 } 8004cb0: b01a add sp, #104 @ 0x68 8004cb2: bcf0 pop {r4, r5, r6, r7} 8004cb4: 4770 bx lr 8004cb6: 68a0 ldr r0, [r4, #8] 8004cb8: 0745 lsls r5, r0, #29 8004cba: d4f1 bmi.n 8004ca0 if (multimode->Mode != ADC_MODE_INDEPENDENT) 8004cbc: b9a6 cbnz r6, 8004ce8 CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 8004cbe: 4917 ldr r1, [pc, #92] @ (8004d1c ) 8004cc0: 6888 ldr r0, [r1, #8] 8004cc2: f420 4040 bic.w r0, r0, #49152 @ 0xc000 8004cc6: 6088 str r0, [r1, #8] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8004cc8: 68a0 ldr r0, [r4, #8] 8004cca: 6892 ldr r2, [r2, #8] 8004ccc: 07d4 lsls r4, r2, #31 8004cce: d405 bmi.n 8004cdc if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8004cd0: 07c5 lsls r5, r0, #31 8004cd2: d403 bmi.n 8004cdc CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 8004cd4: 6888 ldr r0, [r1, #8] 8004cd6: 4a12 ldr r2, [pc, #72] @ (8004d20 ) 8004cd8: 4002 ands r2, r0 8004cda: 608a str r2, [r1, #8] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8004cdc: 2000 movs r0, #0 8004cde: e7e4 b.n 8004caa __HAL_LOCK(hadc); 8004ce0: 2002 movs r0, #2 } 8004ce2: b01a add sp, #104 @ 0x68 8004ce4: bcf0 pop {r4, r5, r6, r7} 8004ce6: 4770 bx lr MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 8004ce8: 4f0c ldr r7, [pc, #48] @ (8004d1c ) 8004cea: 684d ldr r5, [r1, #4] 8004cec: 68b8 ldr r0, [r7, #8] 8004cee: f420 4040 bic.w r0, r0, #49152 @ 0xc000 8004cf2: 4328 orrs r0, r5 8004cf4: 60b8 str r0, [r7, #8] 8004cf6: 68a0 ldr r0, [r4, #8] 8004cf8: 6892 ldr r2, [r2, #8] 8004cfa: 07d4 lsls r4, r2, #31 8004cfc: d4ee bmi.n 8004cdc if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8004cfe: 07c2 lsls r2, r0, #31 8004d00: d4ec bmi.n 8004cdc MODIFY_REG(tmpADC_Common->CCR, 8004d02: 688a ldr r2, [r1, #8] 8004d04: 68b8 ldr r0, [r7, #8] 8004d06: 4906 ldr r1, [pc, #24] @ (8004d20 ) 8004d08: 4332 orrs r2, r6 8004d0a: 4001 ands r1, r0 8004d0c: 430a orrs r2, r1 8004d0e: 60ba str r2, [r7, #8] 8004d10: e7e4 b.n 8004cdc 8004d12: bf00 nop 8004d14: 40022000 .word 0x40022000 8004d18: 40022100 .word 0x40022100 8004d1c: 40022300 .word 0x40022300 8004d20: fffff0e0 .word 0xfffff0e0 08004d24 : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 8004d24: b530 push {r4, r5, lr} uint32_t tmp_csr ; uint32_t exti_line ; uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 8004d26: 2300 movs r3, #0 { 8004d28: b083 sub sp, #12 __IO uint32_t wait_loop_index = 0UL; 8004d2a: 9301 str r3, [sp, #4] HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8004d2c: 2800 cmp r0, #0 8004d2e: d063 beq.n 8004df8 { status = HAL_ERROR; } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8004d30: 6802 ldr r2, [r0, #0] 8004d32: 4604 mov r4, r0 8004d34: 6813 ldr r3, [r2, #0] 8004d36: 2b00 cmp r3, #0 8004d38: db5e blt.n 8004df8 assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) 8004d3a: f890 3025 ldrb.w r3, [r0, #37] @ 0x25 8004d3e: f003 01ff and.w r1, r3, #255 @ 0xff 8004d42: 2b00 cmp r3, #0 8004d44: f000 808e beq.w 8004e64 /* Set HYST bits according to hcomp->Init.Hysteresis value */ /* Set POLARITY bit according to hcomp->Init.OutputPol value */ /* Set POWERMODE bits according to hcomp->Init.Mode value */ tmp_csr = (hcomp->Init.InvertingInput | \ hcomp->Init.NonInvertingInput | \ 8004d48: 69e1 ldr r1, [r4, #28] comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 8004d4a: 6810 ldr r0, [r2, #0] tmp_csr = (hcomp->Init.InvertingInput | \ 8004d4c: e9d4 5303 ldrd r5, r3, [r4, #12] comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 8004d50: f000 0004 and.w r0, r0, #4 tmp_csr = (hcomp->Init.InvertingInput | \ 8004d54: 432b orrs r3, r5 COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST | COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN, tmp_csr ); #else MODIFY_REG(hcomp->Instance->CFGR, 8004d56: 6815 ldr r5, [r2, #0] hcomp->Init.NonInvertingInput | \ 8004d58: 430b orrs r3, r1 hcomp->Init.BlankingSrce | \ 8004d5a: 6961 ldr r1, [r4, #20] 8004d5c: 430b orrs r3, r1 hcomp->Init.Hysteresis | \ 8004d5e: 69a1 ldr r1, [r4, #24] 8004d60: 430b orrs r3, r1 tmp_csr = (hcomp->Init.InvertingInput | \ 8004d62: 68a1 ldr r1, [r4, #8] 8004d64: 430b orrs r3, r1 MODIFY_REG(hcomp->Instance->CFGR, 8004d66: 4943 ldr r1, [pc, #268] @ (8004e74 ) 8004d68: 4029 ands r1, r5 8004d6a: 430b orrs r3, r1 #endif /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 8004d6c: 6861 ldr r1, [r4, #4] MODIFY_REG(hcomp->Instance->CFGR, 8004d6e: 6013 str r3, [r2, #0] if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 8004d70: 2910 cmp r1, #16 { SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8004d72: 6813 ldr r3, [r2, #0] 8004d74: bf0c ite eq 8004d76: f043 0310 orreq.w r3, r3, #16 } else { CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8004d7a: f023 0310 bicne.w r3, r3, #16 8004d7e: 6013 str r3, [r2, #0] } /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) && 8004d80: 6813 ldr r3, [r2, #0] 8004d82: 075d lsls r5, r3, #29 8004d84: d501 bpl.n 8004d8a 8004d86: 2800 cmp r0, #0 8004d88: d156 bne.n 8004e38 wait_loop_index --; } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 8004d8a: 493b ldr r1, [pc, #236] @ (8004e78 ) /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 8004d8c: 6a23 ldr r3, [r4, #32] exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 8004d8e: 428a cmp r2, r1 8004d90: bf15 itete ne 8004d92: f46f 1200 mvnne.w r2, #2097152 @ 0x200000 8004d96: f46f 1280 mvneq.w r2, #1048576 @ 0x100000 8004d9a: f44f 1100 movne.w r1, #2097152 @ 0x200000 8004d9e: f44f 1180 moveq.w r1, #1048576 @ 0x100000 if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 8004da2: 0798 lsls r0, r3, #30 8004da4: d02b beq.n 8004dfe { /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) { SET_BIT(EXTI->RTSR1, exti_line); 8004da6: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000 if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 8004daa: f013 0f10 tst.w r3, #16 SET_BIT(EXTI->RTSR1, exti_line); 8004dae: 6828 ldr r0, [r5, #0] 8004db0: bf14 ite ne 8004db2: 4308 orrne r0, r1 } else { CLEAR_BIT(EXTI->RTSR1, exti_line); 8004db4: 4010 andeq r0, r2 } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 8004db6: f013 0f20 tst.w r3, #32 CLEAR_BIT(EXTI->RTSR1, exti_line); 8004dba: 6028 str r0, [r5, #0] { SET_BIT(EXTI->FTSR1, exti_line); 8004dbc: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000 8004dc0: 6868 ldr r0, [r5, #4] 8004dc2: bf14 ite ne 8004dc4: 4308 orrne r0, r1 } else { CLEAR_BIT(EXTI->FTSR1, exti_line); 8004dc6: 4010 andeq r0, r2 #if !defined (CORE_CM4) /* Clear COMP EXTI pending bit (if any) */ WRITE_REG(EXTI->PR1, exti_line); /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 8004dc8: f013 0f02 tst.w r3, #2 CLEAR_BIT(EXTI->FTSR1, exti_line); 8004dcc: 6068 str r0, [r5, #4] WRITE_REG(EXTI->PR1, exti_line); 8004dce: f04f 40b0 mov.w r0, #1476395008 @ 0x58000000 8004dd2: f8c0 1088 str.w r1, [r0, #136] @ 0x88 { SET_BIT(EXTI->EMR1, exti_line); 8004dd6: f8d0 5084 ldr.w r5, [r0, #132] @ 0x84 8004dda: bf14 ite ne 8004ddc: 430d orrne r5, r1 } else { CLEAR_BIT(EXTI->EMR1, exti_line); 8004dde: 4015 andeq r5, r2 } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 8004de0: 07db lsls r3, r3, #31 CLEAR_BIT(EXTI->EMR1, exti_line); 8004de2: f8c0 5084 str.w r5, [r0, #132] @ 0x84 if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 8004de6: d51f bpl.n 8004e28 { SET_BIT(EXTI->IMR1, exti_line); 8004de8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8004dec: f8d2 3080 ldr.w r3, [r2, #128] @ 0x80 8004df0: 430b orrs r3, r1 8004df2: f8c2 3080 str.w r3, [r2, #128] @ 0x80 8004df6: e00e b.n 8004e16 status = HAL_ERROR; 8004df8: 2001 movs r0, #1 } } return status; } 8004dfa: b003 add sp, #12 8004dfc: bd30 pop {r4, r5, pc} CLEAR_BIT(EXTI->EMR1, exti_line); 8004dfe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8004e02: f8d3 1084 ldr.w r1, [r3, #132] @ 0x84 8004e06: 4011 ands r1, r2 8004e08: f8c3 1084 str.w r1, [r3, #132] @ 0x84 CLEAR_BIT(EXTI->IMR1, exti_line); 8004e0c: f8d3 1080 ldr.w r1, [r3, #128] @ 0x80 8004e10: 400a ands r2, r1 8004e12: f8c3 2080 str.w r2, [r3, #128] @ 0x80 if (hcomp->State == HAL_COMP_STATE_RESET) 8004e16: f894 3025 ldrb.w r3, [r4, #37] @ 0x25 8004e1a: b913 cbnz r3, 8004e22 hcomp->State = HAL_COMP_STATE_READY; 8004e1c: 2301 movs r3, #1 8004e1e: f884 3025 strb.w r3, [r4, #37] @ 0x25 HAL_StatusTypeDef status = HAL_OK; 8004e22: 2000 movs r0, #0 } 8004e24: b003 add sp, #12 8004e26: bd30 pop {r4, r5, pc} CLEAR_BIT(EXTI->IMR1, exti_line); 8004e28: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8004e2c: f8d1 3080 ldr.w r3, [r1, #128] @ 0x80 8004e30: 4013 ands r3, r2 8004e32: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8004e36: e7ee b.n 8004e16 wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8004e38: 4b10 ldr r3, [pc, #64] @ (8004e7c ) 8004e3a: 4911 ldr r1, [pc, #68] @ (8004e80 ) 8004e3c: 681b ldr r3, [r3, #0] 8004e3e: 099b lsrs r3, r3, #6 8004e40: fba1 1303 umull r1, r3, r1, r3 8004e44: 099b lsrs r3, r3, #6 8004e46: 3301 adds r3, #1 8004e48: eb03 0383 add.w r3, r3, r3, lsl #2 8004e4c: 009b lsls r3, r3, #2 8004e4e: 9301 str r3, [sp, #4] while(wait_loop_index != 0UL) 8004e50: 9b01 ldr r3, [sp, #4] 8004e52: 2b00 cmp r3, #0 8004e54: d099 beq.n 8004d8a wait_loop_index --; 8004e56: 9b01 ldr r3, [sp, #4] 8004e58: 3b01 subs r3, #1 8004e5a: 9301 str r3, [sp, #4] while(wait_loop_index != 0UL) 8004e5c: 9b01 ldr r3, [sp, #4] 8004e5e: 2b00 cmp r3, #0 8004e60: d1f9 bne.n 8004e56 8004e62: e792 b.n 8004d8a hcomp->Lock = HAL_UNLOCKED; 8004e64: f880 1024 strb.w r1, [r0, #36] @ 0x24 COMP_CLEAR_ERRORCODE(hcomp); 8004e68: 6281 str r1, [r0, #40] @ 0x28 HAL_COMP_MspInit(hcomp); 8004e6a: f7fd fe5d bl 8002b28 comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 8004e6e: 6822 ldr r2, [r4, #0] 8004e70: e76a b.n 8004d48 8004e72: bf00 nop 8004e74: f0e8cce1 .word 0xf0e8cce1 8004e78: 5800380c .word 0x5800380c 8004e7c: 24000038 .word 0x24000038 8004e80: 053e2d63 .word 0x053e2d63 08004e84 : * @brief Start the comparator. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { 8004e84: b410 push {r4} __IO uint32_t wait_loop_index = 0UL; 8004e86: 2300 movs r3, #0 { 8004e88: b083 sub sp, #12 __IO uint32_t wait_loop_index = 0UL; 8004e8a: 9301 str r3, [sp, #4] HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8004e8c: b138 cbz r0, 8004e9e { status = HAL_ERROR; } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8004e8e: 6803 ldr r3, [r0, #0] 8004e90: 681a ldr r2, [r3, #0] 8004e92: 2a00 cmp r2, #0 8004e94: db03 blt.n 8004e9e else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if(hcomp->State == HAL_COMP_STATE_READY) 8004e96: f890 2025 ldrb.w r2, [r0, #37] @ 0x25 8004e9a: 2a01 cmp r2, #1 8004e9c: d004 beq.n 8004ea8 status = HAL_ERROR; 8004e9e: 2001 movs r0, #1 status = HAL_ERROR; } } return status; } 8004ea0: b003 add sp, #12 8004ea2: f85d 4b04 ldr.w r4, [sp], #4 8004ea6: 4770 bx lr SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 8004ea8: 681a ldr r2, [r3, #0] hcomp->State = HAL_COMP_STATE_BUSY; 8004eaa: f04f 0c02 mov.w ip, #2 wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8004eae: 4c0e ldr r4, [pc, #56] @ (8004ee8 ) SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 8004eb0: f042 0201 orr.w r2, r2, #1 wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8004eb4: 490d ldr r1, [pc, #52] @ (8004eec ) SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 8004eb6: 601a str r2, [r3, #0] wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8004eb8: 6823 ldr r3, [r4, #0] hcomp->State = HAL_COMP_STATE_BUSY; 8004eba: f880 c025 strb.w ip, [r0, #37] @ 0x25 wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8004ebe: 099b lsrs r3, r3, #6 8004ec0: fba1 1303 umull r1, r3, r1, r3 8004ec4: 099b lsrs r3, r3, #6 8004ec6: 3301 adds r3, #1 8004ec8: 00db lsls r3, r3, #3 8004eca: 9301 str r3, [sp, #4] while(wait_loop_index != 0UL) 8004ecc: 9b01 ldr r3, [sp, #4] 8004ece: b12b cbz r3, 8004edc wait_loop_index--; 8004ed0: 9b01 ldr r3, [sp, #4] 8004ed2: 3b01 subs r3, #1 8004ed4: 9301 str r3, [sp, #4] while(wait_loop_index != 0UL) 8004ed6: 9b01 ldr r3, [sp, #4] 8004ed8: 2b00 cmp r3, #0 8004eda: d1f9 bne.n 8004ed0 HAL_StatusTypeDef status = HAL_OK; 8004edc: 2000 movs r0, #0 } 8004ede: b003 add sp, #12 8004ee0: f85d 4b04 ldr.w r4, [sp], #4 8004ee4: 4770 bx lr 8004ee6: bf00 nop 8004ee8: 24000038 .word 0x24000038 8004eec: 053e2d63 .word 0x053e2d63 08004ef0 : uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if (hcomp->Instance == COMP1) 8004ef0: 4b06 ldr r3, [pc, #24] @ (8004f0c ) 8004ef2: 6802 ldr r2, [r0, #0] 8004ef4: 429a cmp r2, r3 8004ef6: d004 beq.n 8004f02 { return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); } else { return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL); 8004ef8: 4b05 ldr r3, [pc, #20] @ (8004f10 ) 8004efa: 6818 ldr r0, [r3, #0] 8004efc: f3c0 0040 ubfx r0, r0, #1, #1 } } 8004f00: 4770 bx lr return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); 8004f02: f853 0c0c ldr.w r0, [r3, #-12] 8004f06: f000 0001 and.w r0, r0, #1 8004f0a: 4770 bx lr 8004f0c: 5800380c .word 0x5800380c 8004f10: 58003800 .word 0x58003800 08004f14 : reg_value = SCB->AIRCR; /* read old register configuration */ 8004f14: 4906 ldr r1, [pc, #24] @ (8004f30 ) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8004f16: f64f 0cff movw ip, #63743 @ 0xf8ff (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8004f1a: 0200 lsls r0, r0, #8 reg_value = (reg_value | 8004f1c: 4b05 ldr r3, [pc, #20] @ (8004f34 ) reg_value = SCB->AIRCR; /* read old register configuration */ 8004f1e: 68ca ldr r2, [r1, #12] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8004f20: f400 60e0 and.w r0, r0, #1792 @ 0x700 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8004f24: ea02 020c and.w r2, r2, ip ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8004f28: 4310 orrs r0, r2 reg_value = (reg_value | 8004f2a: 4303 orrs r3, r0 SCB->AIRCR = reg_value; 8004f2c: 60cb str r3, [r1, #12] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } 8004f2e: 4770 bx lr 8004f30: e000ed00 .word 0xe000ed00 8004f34: 05fa0000 .word 0x05fa0000 08004f38 : return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8004f38: 4b1a ldr r3, [pc, #104] @ (8004fa4 ) 8004f3a: 68db ldr r3, [r3, #12] 8004f3c: f3c3 2302 ubfx r3, r3, #8, #3 * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8004f40: b500 push {lr} PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8004f42: f1c3 0e07 rsb lr, r3, #7 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8004f46: f103 0c04 add.w ip, r3, #4 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8004f4a: f1be 0f04 cmp.w lr, #4 8004f4e: bf28 it cs 8004f50: f04f 0e04 movcs.w lr, #4 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8004f54: f1bc 0f06 cmp.w ip, #6 8004f58: d91a bls.n 8004f90 8004f5a: f1a3 0c03 sub.w ip, r3, #3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8004f5e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8004f62: fa03 f30c lsl.w r3, r3, ip 8004f66: ea22 0203 bic.w r2, r2, r3 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8004f6a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff if ((int32_t)(IRQn) >= 0) 8004f6e: 2800 cmp r0, #0 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8004f70: fa03 f30e lsl.w r3, r3, lr 8004f74: ea21 0303 bic.w r3, r1, r3 8004f78: fa03 f30c lsl.w r3, r3, ip 8004f7c: ea43 0302 orr.w r3, r3, r2 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8004f80: ea4f 1303 mov.w r3, r3, lsl #4 8004f84: b2db uxtb r3, r3 if ((int32_t)(IRQn) >= 0) 8004f86: db06 blt.n 8004f96 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8004f88: 4a07 ldr r2, [pc, #28] @ (8004fa8 ) 8004f8a: 5413 strb r3, [r2, r0] assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } 8004f8c: f85d fb04 ldr.w pc, [sp], #4 8004f90: 2200 movs r2, #0 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8004f92: 4694 mov ip, r2 8004f94: e7e9 b.n 8004f6a SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8004f96: f000 000f and.w r0, r0, #15 8004f9a: 4a04 ldr r2, [pc, #16] @ (8004fac ) 8004f9c: 5413 strb r3, [r2, r0] 8004f9e: f85d fb04 ldr.w pc, [sp], #4 8004fa2: bf00 nop 8004fa4: e000ed00 .word 0xe000ed00 8004fa8: e000e400 .word 0xe000e400 8004fac: e000ed14 .word 0xe000ed14 08004fb0 : if ((int32_t)(IRQn) >= 0) 8004fb0: 2800 cmp r0, #0 8004fb2: db07 blt.n 8004fc4 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8004fb4: 2301 movs r3, #1 8004fb6: f000 011f and.w r1, r0, #31 8004fba: 4a03 ldr r2, [pc, #12] @ (8004fc8 ) 8004fbc: 0940 lsrs r0, r0, #5 8004fbe: 408b lsls r3, r1 8004fc0: f842 3020 str.w r3, [r2, r0, lsl #2] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } 8004fc4: 4770 bx lr 8004fc6: bf00 nop 8004fc8: e000e100 .word 0xe000e100 08004fcc : __ASM volatile ("dmb 0xF":::"memory"); 8004fcc: f3bf 8f5f dmb sy { /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8004fd0: 4b04 ldr r3, [pc, #16] @ (8004fe4 ) /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 8004fd2: 2100 movs r1, #0 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8004fd4: 6a5a ldr r2, [r3, #36] @ 0x24 8004fd6: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8004fda: 625a str r2, [r3, #36] @ 0x24 MPU->CTRL = 0; 8004fdc: f8c3 1094 str.w r1, [r3, #148] @ 0x94 } 8004fe0: 4770 bx lr 8004fe2: bf00 nop 8004fe4: e000ed00 .word 0xe000ed00 08004fe8 : * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8004fe8: 4b06 ldr r3, [pc, #24] @ (8005004 ) 8004fea: f040 0001 orr.w r0, r0, #1 8004fee: f8c3 0094 str.w r0, [r3, #148] @ 0x94 /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 8004ff2: 6a5a ldr r2, [r3, #36] @ 0x24 8004ff4: f442 3280 orr.w r2, r2, #65536 @ 0x10000 8004ff8: 625a str r2, [r3, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 8004ffa: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 8004ffe: f3bf 8f6f isb sy /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8005002: 4770 bx lr 8005004: e000ed00 .word 0xe000ed00 08005008 : assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8005008: 4a16 ldr r2, [pc, #88] @ (8005064 ) 800500a: 7843 ldrb r3, [r0, #1] 800500c: f8c2 3098 str.w r3, [r2, #152] @ 0x98 /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 8005010: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0 8005014: f023 0301 bic.w r3, r3, #1 8005018: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 800501c: 6843 ldr r3, [r0, #4] 800501e: f8c2 309c str.w r3, [r2, #156] @ 0x9c MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8005022: 7ac3 ldrb r3, [r0, #11] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8005024: f890 c00c ldrb.w ip, [r0, #12] ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8005028: 061b lsls r3, r3, #24 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 800502a: 7801 ldrb r1, [r0, #0] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 800502c: ea43 730c orr.w r3, r3, ip, lsl #28 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8005030: f890 c00a ldrb.w ip, [r0, #10] ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8005034: 430b orrs r3, r1 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8005036: 7b41 ldrb r1, [r0, #13] ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8005038: ea43 43cc orr.w r3, r3, ip, lsl #19 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 800503c: f890 c00e ldrb.w ip, [r0, #14] ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8005040: ea43 4381 orr.w r3, r3, r1, lsl #18 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8005044: 7bc1 ldrb r1, [r0, #15] ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8005046: ea43 434c orr.w r3, r3, ip, lsl #17 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 800504a: f890 c009 ldrb.w ip, [r0, #9] ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 800504e: ea43 4301 orr.w r3, r3, r1, lsl #16 8005052: 7a01 ldrb r1, [r0, #8] 8005054: ea43 230c orr.w r3, r3, ip, lsl #8 8005058: ea43 0341 orr.w r3, r3, r1, lsl #1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 800505c: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 } 8005060: 4770 bx lr 8005062: bf00 nop 8005064: e000ed00 .word 0xe000ed00 08005068 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 8005068: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 800506c: 0897 lsrs r7, r2, #2 /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) { if ((BufferLength % 4U) == 1U) { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 800506e: 6805 ldr r5, [r0, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8005070: d016 beq.n 80050a0 8005072: 468c mov ip, r1 8005074: eb01 0687 add.w r6, r1, r7, lsl #2 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8005078: f89c 3001 ldrb.w r3, [ip, #1] for (i = 0U; i < (BufferLength / 4U); i++) 800507c: f10c 0c04 add.w ip, ip, #4 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8005080: f81c 8c04 ldrb.w r8, [ip, #-4] ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8005084: 041b lsls r3, r3, #16 (uint32_t)pBuffer[(4U * i) + 3U]; 8005086: f81c 4c01 ldrb.w r4, [ip, #-1] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 800508a: f81c ec02 ldrb.w lr, [ip, #-2] for (i = 0U; i < (BufferLength / 4U); i++) 800508e: 45b4 cmp ip, r6 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8005090: ea43 6308 orr.w r3, r3, r8, lsl #24 8005094: ea43 0304 orr.w r3, r3, r4 8005098: ea43 230e orr.w r3, r3, lr, lsl #8 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 800509c: 602b str r3, [r5, #0] for (i = 0U; i < (BufferLength / 4U); i++) 800509e: d1eb bne.n 8005078 if ((BufferLength % 4U) != 0U) 80050a0: f012 0203 ands.w r2, r2, #3 80050a4: d00c beq.n 80050c0 if ((BufferLength % 4U) == 1U) 80050a6: 2a01 cmp r2, #1 *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 80050a8: ea4f 0387 mov.w r3, r7, lsl #2 80050ac: f811 4027 ldrb.w r4, [r1, r7, lsl #2] if ((BufferLength % 4U) == 1U) 80050b0: d009 beq.n 80050c6 pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = data; } if ((BufferLength % 4U) == 3U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 80050b2: 4419 add r1, r3 if ((BufferLength % 4U) == 2U) 80050b4: 2a02 cmp r2, #2 data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 80050b6: 784b ldrb r3, [r1, #1] 80050b8: ea43 2304 orr.w r3, r3, r4, lsl #8 *pReg = data; 80050bc: 802b strh r3, [r5, #0] if ((BufferLength % 4U) == 2U) 80050be: d107 bne.n 80050d0 *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ } } /* Return the CRC computed value */ return hcrc->Instance->DR; 80050c0: 6828 ldr r0, [r5, #0] } 80050c2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 80050c6: 702c strb r4, [r5, #0] return hcrc->Instance->DR; 80050c8: 6805 ldr r5, [r0, #0] 80050ca: 6828 ldr r0, [r5, #0] } 80050cc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 80050d0: 788b ldrb r3, [r1, #2] 80050d2: 702b strb r3, [r5, #0] return hcrc->Instance->DR; 80050d4: 6805 ldr r5, [r0, #0] 80050d6: 6828 ldr r0, [r5, #0] } 80050d8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 080050dc : if (hcrc == NULL) 80050dc: 2800 cmp r0, #0 80050de: d036 beq.n 800514e { 80050e0: b510 push {r4, lr} if (hcrc->State == HAL_CRC_STATE_RESET) 80050e2: 7f43 ldrb r3, [r0, #29] 80050e4: 4604 mov r4, r0 80050e6: f003 02ff and.w r2, r3, #255 @ 0xff 80050ea: b363 cbz r3, 8005146 hcrc->State = HAL_CRC_STATE_BUSY; 80050ec: 2202 movs r2, #2 if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 80050ee: 7923 ldrb r3, [r4, #4] hcrc->State = HAL_CRC_STATE_BUSY; 80050f0: 7762 strb r2, [r4, #29] if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 80050f2: b9f3 cbnz r3, 8005132 WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 80050f4: 6823 ldr r3, [r4, #0] 80050f6: 4a17 ldr r2, [pc, #92] @ (8005154 ) 80050f8: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 80050fa: 689a ldr r2, [r3, #8] 80050fc: f022 0218 bic.w r2, r2, #24 8005100: 609a str r2, [r3, #8] if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 8005102: 7962 ldrb r2, [r4, #5] 8005104: b18a cbz r2, 800512a WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 8005106: 6922 ldr r2, [r4, #16] 8005108: 611a str r2, [r3, #16] MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 800510a: 689a ldr r2, [r3, #8] MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 800510c: e9d4 0105 ldrd r0, r1, [r4, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8005110: f022 0260 bic.w r2, r2, #96 @ 0x60 8005114: 4302 orrs r2, r0 return HAL_OK; 8005116: 2000 movs r0, #0 MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8005118: 609a str r2, [r3, #8] MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 800511a: 689a ldr r2, [r3, #8] 800511c: f022 0280 bic.w r2, r2, #128 @ 0x80 8005120: 430a orrs r2, r1 hcrc->State = HAL_CRC_STATE_READY; 8005122: 2101 movs r1, #1 MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 8005124: 609a str r2, [r3, #8] hcrc->State = HAL_CRC_STATE_READY; 8005126: 7761 strb r1, [r4, #29] } 8005128: bd10 pop {r4, pc} WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 800512a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800512e: 611a str r2, [r3, #16] 8005130: e7eb b.n 800510a if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 8005132: e9d4 1202 ldrd r1, r2, [r4, #8] 8005136: 4620 mov r0, r4 8005138: f000 f84e bl 80051d8 800513c: b908 cbnz r0, 8005142 WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 800513e: 6823 ldr r3, [r4, #0] 8005140: e7df b.n 8005102 return HAL_ERROR; 8005142: 2001 movs r0, #1 } 8005144: bd10 pop {r4, pc} hcrc->Lock = HAL_UNLOCKED; 8005146: 7702 strb r2, [r0, #28] HAL_CRC_MspInit(hcrc); 8005148: f7fd fd2c bl 8002ba4 800514c: e7ce b.n 80050ec return HAL_ERROR; 800514e: 2001 movs r0, #1 } 8005150: 4770 bx lr 8005152: bf00 nop 8005154: 04c11db7 .word 0x04c11db7 08005158 : { 8005158: b5f8 push {r3, r4, r5, r6, r7, lr} hcrc->State = HAL_CRC_STATE_BUSY; 800515a: 2302 movs r3, #2 __HAL_CRC_DR_RESET(hcrc); 800515c: 6805 ldr r5, [r0, #0] { 800515e: 4606 mov r6, r0 8005160: 468c mov ip, r1 hcrc->State = HAL_CRC_STATE_BUSY; 8005162: 7743 strb r3, [r0, #29] { 8005164: 4617 mov r7, r2 __HAL_CRC_DR_RESET(hcrc); 8005166: 68ab ldr r3, [r5, #8] 8005168: f043 0301 orr.w r3, r3, #1 800516c: 60ab str r3, [r5, #8] switch (hcrc->InputDataFormat) 800516e: 6a03 ldr r3, [r0, #32] 8005170: 2b02 cmp r3, #2 8005172: d007 beq.n 8005184 8005174: 2b03 cmp r3, #3 8005176: d022 beq.n 80051be 8005178: 2b01 cmp r3, #1 800517a: d01b beq.n 80051b4 hcrc->State = HAL_CRC_STATE_READY; 800517c: 2301 movs r3, #1 switch (hcrc->InputDataFormat) 800517e: 2000 movs r0, #0 hcrc->State = HAL_CRC_STATE_READY; 8005180: 7773 strb r3, [r6, #29] } 8005182: bdf8 pop {r3, r4, r5, r6, r7, pc} __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8005184: 0851 lsrs r1, r2, #1 8005186: d00c beq.n 80051a2 8005188: 2300 movs r3, #0 800518a: f10c 0002 add.w r0, ip, #2 { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 800518e: f83c 2023 ldrh.w r2, [ip, r3, lsl #2] 8005192: f830 4023 ldrh.w r4, [r0, r3, lsl #2] for (i = 0U; i < (BufferLength / 2U); i++) 8005196: 3301 adds r3, #1 hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 8005198: ea44 4402 orr.w r4, r4, r2, lsl #16 for (i = 0U; i < (BufferLength / 2U); i++) 800519c: 428b cmp r3, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 800519e: 602c str r4, [r5, #0] for (i = 0U; i < (BufferLength / 2U); i++) 80051a0: d1f5 bne.n 800518e } if ((BufferLength % 2U) != 0U) 80051a2: 07fb lsls r3, r7, #31 80051a4: d502 bpl.n 80051ac { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = pBuffer[2U * i]; 80051a6: f83c 3021 ldrh.w r3, [ip, r1, lsl #2] 80051aa: 802b strh r3, [r5, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 80051ac: 6828 ldr r0, [r5, #0] hcrc->State = HAL_CRC_STATE_READY; 80051ae: 2301 movs r3, #1 80051b0: 7773 strb r3, [r6, #29] } 80051b2: bdf8 pop {r3, r4, r5, r6, r7, pc} temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 80051b4: f7ff ff58 bl 8005068 hcrc->State = HAL_CRC_STATE_READY; 80051b8: 2301 movs r3, #1 80051ba: 7773 strb r3, [r6, #29] } 80051bc: bdf8 pop {r3, r4, r5, r6, r7, pc} for (index = 0U; index < BufferLength; index++) 80051be: 2a00 cmp r2, #0 80051c0: d0f4 beq.n 80051ac 80051c2: 3904 subs r1, #4 80051c4: eb01 0782 add.w r7, r1, r2, lsl #2 hcrc->Instance->DR = pBuffer[index]; 80051c8: f851 3f04 ldr.w r3, [r1, #4]! for (index = 0U; index < BufferLength; index++) 80051cc: 42b9 cmp r1, r7 hcrc->Instance->DR = pBuffer[index]; 80051ce: 602b str r3, [r5, #0] for (index = 0U; index < BufferLength; index++) 80051d0: d1fa bne.n 80051c8 return hcrc->Instance->DR; 80051d2: 6828 ldr r0, [r5, #0] break; 80051d4: e7eb b.n 80051ae 80051d6: bf00 nop 080051d8 : /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 80051d8: 07cb lsls r3, r1, #31 80051da: d51a bpl.n 8005212 uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 80051dc: 231f movs r3, #31 { 80051de: b410 push {r4} * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 80051e0: 3b01 subs r3, #1 80051e2: 1c5c adds r4, r3, #1 80051e4: fa21 fc03 lsr.w ip, r1, r3 80051e8: d015 beq.n 8005216 80051ea: f01c 0f01 tst.w ip, #1 80051ee: d0f7 beq.n 80051e0 { } switch (PolyLength) 80051f0: 2a18 cmp r2, #24 80051f2: d811 bhi.n 8005218 80051f4: e8df f002 tbb [pc, r2] 80051f8: 10101016 .word 0x10101016 80051fc: 10101010 .word 0x10101010 8005200: 10101024 .word 0x10101024 8005204: 10101010 .word 0x10101010 8005208: 10101021 .word 0x10101021 800520c: 10101010 .word 0x10101010 8005210: 14 .byte 0x14 8005211: 00 .byte 0x00 8005212: 2001 movs r0, #1 /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); } /* Return function status */ return status; } 8005214: 4770 bx lr switch (PolyLength) 8005216: b12a cbz r2, 8005224 8005218: 2001 movs r0, #1 } 800521a: f85d 4b04 ldr.w r4, [sp], #4 800521e: 4770 bx lr if (msb >= HAL_CRC_LENGTH_7B) 8005220: 2b06 cmp r3, #6 8005222: d8f9 bhi.n 8005218 WRITE_REG(hcrc->Instance->POL, Pol); 8005224: 6804 ldr r4, [r0, #0] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 8005226: 2000 movs r0, #0 WRITE_REG(hcrc->Instance->POL, Pol); 8005228: 6161 str r1, [r4, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 800522a: 68a3 ldr r3, [r4, #8] 800522c: f023 0318 bic.w r3, r3, #24 8005230: 4313 orrs r3, r2 8005232: 60a3 str r3, [r4, #8] } 8005234: f85d 4b04 ldr.w r4, [sp], #4 8005238: 4770 bx lr if (msb >= HAL_CRC_LENGTH_8B) 800523a: 2b07 cmp r3, #7 800523c: d9f2 bls.n 8005224 800523e: e7eb b.n 8005218 if (msb >= HAL_CRC_LENGTH_16B) 8005240: 2b0f cmp r3, #15 8005242: d9ef bls.n 8005224 8005244: e7e8 b.n 8005218 8005246: bf00 nop 08005248 : * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { /* Check the DAC peripheral handle */ if (hdac == NULL) 8005248: b188 cbz r0, 800526e { 800524a: b510 push {r4, lr} return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 800524c: 7903 ldrb r3, [r0, #4] 800524e: 4604 mov r4, r0 8005250: f003 02ff and.w r2, r3, #255 @ 0xff 8005254: b13b cbz r3, 8005266 /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 8005256: 2300 movs r3, #0 hdac->State = HAL_DAC_STATE_BUSY; 8005258: 2102 movs r1, #2 /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 800525a: 2201 movs r2, #1 hdac->State = HAL_DAC_STATE_BUSY; 800525c: 7121 strb r1, [r4, #4] /* Return function status */ return HAL_OK; 800525e: 4618 mov r0, r3 hdac->ErrorCode = HAL_DAC_ERROR_NONE; 8005260: 6123 str r3, [r4, #16] hdac->State = HAL_DAC_STATE_READY; 8005262: 7122 strb r2, [r4, #4] } 8005264: bd10 pop {r4, pc} hdac->Lock = HAL_UNLOCKED; 8005266: 7142 strb r2, [r0, #5] HAL_DAC_MspInit(hdac); 8005268: f7fd fcb4 bl 8002bd4 800526c: e7f3 b.n 8005256 return HAL_ERROR; 800526e: 2001 movs r0, #1 } 8005270: 4770 bx lr 8005272: bf00 nop 08005274 : * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the DAC peripheral handle */ if (hdac == NULL) 8005274: b388 cbz r0, 80052da /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8005276: 7942 ldrb r2, [r0, #5] 8005278: 4603 mov r3, r0 800527a: 2a01 cmp r2, #1 800527c: d02f beq.n 80052de /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 800527e: 6800 ldr r0, [r0, #0] hdac->State = HAL_DAC_STATE_BUSY; 8005280: f04f 0c02 mov.w ip, #2 __HAL_DAC_ENABLE(hdac, Channel); 8005284: 2201 movs r2, #1 { 8005286: b510 push {r4, lr} __HAL_DAC_ENABLE(hdac, Channel); 8005288: f001 0e10 and.w lr, r1, #16 hdac->State = HAL_DAC_STATE_BUSY; 800528c: f883 c004 strb.w ip, [r3, #4] __HAL_DAC_ENABLE(hdac, Channel); 8005290: 6804 ldr r4, [r0, #0] 8005292: fa02 f20e lsl.w r2, r2, lr 8005296: 4322 orrs r2, r4 8005298: 6002 str r2, [r0, #0] if (Channel == DAC_CHANNEL_1) { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 800529a: 6802 ldr r2, [r0, #0] if (Channel == DAC_CHANNEL_1) 800529c: b969 cbnz r1, 80052ba if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 800529e: f002 023e and.w r2, r2, #62 @ 0x3e 80052a2: 4562 cmp r2, ip 80052a4: d103 bne.n 80052ae { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 80052a6: 6842 ldr r2, [r0, #4] 80052a8: f042 0201 orr.w r2, r2, #1 80052ac: 6042 str r2, [r0, #4] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); 80052ae: 2200 movs r2, #0 hdac->State = HAL_DAC_STATE_READY; 80052b0: 2101 movs r1, #1 /* Return function status */ return HAL_OK; 80052b2: 4610 mov r0, r2 hdac->State = HAL_DAC_STATE_READY; 80052b4: 7119 strb r1, [r3, #4] __HAL_UNLOCK(hdac); 80052b6: 715a strb r2, [r3, #5] } 80052b8: bd10 pop {r4, pc} if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 80052ba: fa0c fc0e lsl.w ip, ip, lr 80052be: f402 1278 and.w r2, r2, #4063232 @ 0x3e0000 80052c2: 4562 cmp r2, ip 80052c4: d1f3 bne.n 80052ae SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 80052c6: 6842 ldr r2, [r0, #4] hdac->State = HAL_DAC_STATE_READY; 80052c8: 2101 movs r1, #1 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 80052ca: f042 0202 orr.w r2, r2, #2 80052ce: 6042 str r2, [r0, #4] __HAL_UNLOCK(hdac); 80052d0: 2200 movs r2, #0 hdac->State = HAL_DAC_STATE_READY; 80052d2: 7119 strb r1, [r3, #4] return HAL_OK; 80052d4: 4610 mov r0, r2 __HAL_UNLOCK(hdac); 80052d6: 715a strb r2, [r3, #5] } 80052d8: bd10 pop {r4, pc} return HAL_ERROR; 80052da: 2001 movs r0, #1 80052dc: 4770 bx lr __HAL_LOCK(hdac); 80052de: 2002 movs r0, #2 } 80052e0: 4770 bx lr 80052e2: bf00 nop 080052e4 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 80052e4: b410 push {r4} __IO uint32_t tmp = 0UL; 80052e6: 2400 movs r4, #0 { 80052e8: b083 sub sp, #12 __IO uint32_t tmp = 0UL; 80052ea: 9401 str r4, [sp, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 80052ec: b190 cbz r0, 8005314 /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 80052ee: 6800 ldr r0, [r0, #0] 80052f0: 9001 str r0, [sp, #4] if (Channel == DAC_CHANNEL_1) 80052f2: b151 cbz r1, 800530a tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 80052f4: 9901 ldr r1, [sp, #4] 80052f6: 3114 adds r1, #20 80052f8: 440a add r2, r1 80052fa: 9201 str r2, [sp, #4] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 80052fc: 9a01 ldr r2, [sp, #4] /* Return function status */ return HAL_OK; 80052fe: 2000 movs r0, #0 *(__IO uint32_t *) tmp = Data; 8005300: 6013 str r3, [r2, #0] } 8005302: b003 add sp, #12 8005304: f85d 4b04 ldr.w r4, [sp], #4 8005308: 4770 bx lr tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 800530a: 9901 ldr r1, [sp, #4] 800530c: 3108 adds r1, #8 800530e: 440a add r2, r1 8005310: 9201 str r2, [sp, #4] 8005312: e7f3 b.n 80052fc return HAL_ERROR; 8005314: 2001 movs r0, #1 } 8005316: b003 add sp, #12 8005318: f85d 4b04 ldr.w r4, [sp], #4 800531c: 4770 bx lr 800531e: bf00 nop 08005320 : * @brief DMA underrun DAC callback for channel1. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) 8005320: 4770 bx lr 8005322: bf00 nop 08005324 : uint32_t itsource = hdac->Instance->CR; 8005324: 6803 ldr r3, [r0, #0] { 8005326: b570 push {r4, r5, r6, lr} uint32_t itsource = hdac->Instance->CR; 8005328: 681d ldr r5, [r3, #0] { 800532a: 4604 mov r4, r0 uint32_t itflag = hdac->Instance->SR; 800532c: 6b5e ldr r6, [r3, #52] @ 0x34 if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 800532e: 04aa lsls r2, r5, #18 8005330: d501 bpl.n 8005336 if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 8005332: 04b1 lsls r1, r6, #18 8005334: d417 bmi.n 8005366 if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 8005336: 00aa lsls r2, r5, #2 8005338: d501 bpl.n 800533e if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 800533a: 00b3 lsls r3, r6, #2 800533c: d400 bmi.n 8005340 } 800533e: bd70 pop {r4, r5, r6, pc} hdac->State = HAL_DAC_STATE_ERROR; 8005340: 2204 movs r2, #4 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 8005342: 6823 ldr r3, [r4, #0] 8005344: f04f 5100 mov.w r1, #536870912 @ 0x20000000 HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 8005348: 4620 mov r0, r4 hdac->State = HAL_DAC_STATE_ERROR; 800534a: 7122 strb r2, [r4, #4] SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 800534c: 6922 ldr r2, [r4, #16] 800534e: f042 0202 orr.w r2, r2, #2 8005352: 6122 str r2, [r4, #16] __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 8005354: 6359 str r1, [r3, #52] @ 0x34 __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 8005356: 681a ldr r2, [r3, #0] 8005358: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 } 800535c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 8005360: 601a str r2, [r3, #0] HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 8005362: f000 b8bb b.w 80054dc hdac->State = HAL_DAC_STATE_ERROR; 8005366: 2204 movs r2, #4 8005368: 7102 strb r2, [r0, #4] SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 800536a: 6902 ldr r2, [r0, #16] 800536c: f042 0201 orr.w r2, r2, #1 8005370: 6102 str r2, [r0, #16] __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 8005372: f44f 5200 mov.w r2, #8192 @ 0x2000 8005376: 635a str r2, [r3, #52] @ 0x34 __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 8005378: 681a ldr r2, [r3, #0] 800537a: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800537e: 601a str r2, [r3, #0] HAL_DAC_DMAUnderrunCallbackCh1(hdac); 8005380: f7ff ffce bl 8005320 8005384: e7d7 b.n 8005336 8005386: bf00 nop 08005388 : uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 8005388: 2800 cmp r0, #0 800538a: f000 8086 beq.w 800549a { 800538e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8005392: 460d mov r5, r1 if ((hdac == NULL) || (sConfig == NULL)) 8005394: 2900 cmp r1, #0 8005396: d04d beq.n 8005434 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8005398: 7943 ldrb r3, [r0, #5] 800539a: 4604 mov r4, r0 if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) 800539c: 6809 ldr r1, [r1, #0] __HAL_LOCK(hdac); 800539e: 2b01 cmp r3, #1 80053a0: d079 beq.n 8005496 80053a2: 2301 movs r3, #1 /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 80053a4: 2904 cmp r1, #4 80053a6: 4616 mov r6, r2 __HAL_LOCK(hdac); 80053a8: 7143 strb r3, [r0, #5] hdac->State = HAL_DAC_STATE_BUSY; 80053aa: f04f 0302 mov.w r3, #2 80053ae: 7103 strb r3, [r0, #4] if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 80053b0: d043 beq.n 800543a hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 80053b2: f002 0210 and.w r2, r2, #16 if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 80053b6: 6803 ldr r3, [r0, #0] if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 80053b8: 6928 ldr r0, [r5, #16] 80053ba: 2801 cmp r0, #1 80053bc: d108 bne.n 80053d0 /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 80053be: 201f movs r0, #31 tmpreg1 = hdac->Instance->CCR; 80053c0: 6b9e ldr r6, [r3, #56] @ 0x38 tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 80053c2: 4090 lsls r0, r2 80053c4: ea26 0600 bic.w r6, r6, r0 /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80053c8: 6968 ldr r0, [r5, #20] 80053ca: 4090 lsls r0, r2 80053cc: 4330 orrs r0, r6 /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 80053ce: 6398 str r0, [r3, #56] @ 0x38 /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 80053d0: 2007 movs r0, #7 tmpreg1 = hdac->Instance->MCR; 80053d2: 6bde ldr r6, [r3, #60] @ 0x3c tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 80053d4: 4090 lsls r0, r2 80053d6: ea26 0600 bic.w r6, r6, r0 { connectOnChip = DAC_MCR_MODE1_0; } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 80053da: e9d5 7002 ldrd r7, r0, [r5, #8] if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 80053de: 2801 cmp r0, #1 80053e0: d055 beq.n 800548e else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 80053e2: 2802 cmp r0, #2 80053e4: d055 beq.n 8005492 if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 80053e6: fab7 f087 clz r0, r7 80053ea: 0940 lsrs r0, r0, #5 else { connectOnChip = 0x00000000UL; } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 80053ec: 4339 orrs r1, r7 80053ee: 4301 orrs r1, r0 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80053f0: 6868 ldr r0, [r5, #4] CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 80053f2: f44f 4580 mov.w r5, #16384 @ 0x4000 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80053f6: 4091 lsls r1, r2 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80053f8: 4090 lsls r0, r2 CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 80053fa: 4095 lsls r5, r2 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80053fc: 4331 orrs r1, r6 hdac->Instance->CR = tmpreg1; /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 80053fe: 2601 movs r6, #1 hdac->Instance->MCR = tmpreg1; 8005400: 63d9 str r1, [r3, #60] @ 0x3c CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 8005402: 6819 ldr r1, [r3, #0] 8005404: ea21 0105 bic.w r1, r1, r5 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 8005408: f640 75fe movw r5, #4094 @ 0xffe CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 800540c: 6019 str r1, [r3, #0] tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 800540e: 4095 lsls r5, r2 tmpreg1 = hdac->Instance->CR; 8005410: 6819 ldr r1, [r3, #0] tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 8005412: ea21 0105 bic.w r1, r1, r5 /* Process unlocked */ __HAL_UNLOCK(hdac); 8005416: 2500 movs r5, #0 tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8005418: 4301 orrs r1, r0 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 800541a: 20c0 movs r0, #192 @ 0xc0 hdac->Instance->CR = tmpreg1; 800541c: 6019 str r1, [r3, #0] CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 800541e: fa00 f102 lsl.w r1, r0, r2 8005422: 681a ldr r2, [r3, #0] /* Return function status */ return status; 8005424: 4628 mov r0, r5 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 8005426: ea22 0201 bic.w r2, r2, r1 800542a: 601a str r2, [r3, #0] hdac->State = HAL_DAC_STATE_READY; 800542c: 7126 strb r6, [r4, #4] __HAL_UNLOCK(hdac); 800542e: 7165 strb r5, [r4, #5] } 8005430: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} return HAL_ERROR; 8005434: 2001 movs r0, #1 } 8005436: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} tickstart = HAL_GetTick(); 800543a: f7fe fdc9 bl 8003fd0 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800543e: 6823 ldr r3, [r4, #0] tickstart = HAL_GetTick(); 8005440: 4607 mov r7, r0 if (Channel == DAC_CHANNEL_1) 8005442: b9be cbnz r6, 8005474 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8005444: f8df 8090 ldr.w r8, [pc, #144] @ 80054d8 8005448: 6b5a ldr r2, [r3, #52] @ 0x34 800544a: ea12 0f08 tst.w r2, r8 800544e: d026 beq.n 800549e if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8005450: f7fe fdbe bl 8003fd0 8005454: 1bc0 subs r0, r0, r7 if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8005456: 6823 ldr r3, [r4, #0] if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8005458: 2801 cmp r0, #1 800545a: d9f5 bls.n 8005448 if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800545c: 6b5a ldr r2, [r3, #52] @ 0x34 800545e: ea12 0f08 tst.w r2, r8 8005462: d0f1 beq.n 8005448 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8005464: 6923 ldr r3, [r4, #16] hdac->State = HAL_DAC_STATE_TIMEOUT; 8005466: 2203 movs r2, #3 return HAL_TIMEOUT; 8005468: 2003 movs r0, #3 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 800546a: f043 0308 orr.w r3, r3, #8 800546e: 6123 str r3, [r4, #16] hdac->State = HAL_DAC_STATE_TIMEOUT; 8005470: 7122 strb r2, [r4, #4] return HAL_TIMEOUT; 8005472: e7dd b.n 8005430 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8005474: 6b5a ldr r2, [r3, #52] @ 0x34 8005476: 2a00 cmp r2, #0 8005478: da2a bge.n 80054d0 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 800547a: f7fe fda9 bl 8003fd0 800547e: 1bc0 subs r0, r0, r7 if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8005480: 6823 ldr r3, [r4, #0] if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8005482: 2801 cmp r0, #1 8005484: d9f6 bls.n 8005474 if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8005486: 6b5a ldr r2, [r3, #52] @ 0x34 8005488: 2a00 cmp r2, #0 800548a: daf3 bge.n 8005474 800548c: e7ea b.n 8005464 connectOnChip = 0x00000000UL; 800548e: 2000 movs r0, #0 8005490: e7ac b.n 80053ec connectOnChip = DAC_MCR_MODE1_0; 8005492: 2001 movs r0, #1 8005494: e7aa b.n 80053ec __HAL_LOCK(hdac); 8005496: 2002 movs r0, #2 8005498: e7ca b.n 8005430 return HAL_ERROR; 800549a: 2001 movs r0, #1 } 800549c: 4770 bx lr hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 800549e: 69aa ldr r2, [r5, #24] 80054a0: 641a str r2, [r3, #64] @ 0x40 MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 80054a2: f006 0210 and.w r2, r6, #16 80054a6: f240 30ff movw r0, #1023 @ 0x3ff 80054aa: 6c99 ldr r1, [r3, #72] @ 0x48 80054ac: 4090 lsls r0, r2 80054ae: ea21 0100 bic.w r1, r1, r0 80054b2: 69e8 ldr r0, [r5, #28] 80054b4: 4090 lsls r0, r2 80054b6: 4301 orrs r1, r0 MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 80054b8: 20ff movs r0, #255 @ 0xff MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 80054ba: 6499 str r1, [r3, #72] @ 0x48 MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 80054bc: 4090 lsls r0, r2 80054be: 6cd9 ldr r1, [r3, #76] @ 0x4c 80054c0: ea21 0100 bic.w r1, r1, r0 80054c4: 6a28 ldr r0, [r5, #32] 80054c6: 4090 lsls r0, r2 80054c8: 4301 orrs r1, r0 80054ca: 64d9 str r1, [r3, #76] @ 0x4c tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 80054cc: 6829 ldr r1, [r5, #0] 80054ce: e773 b.n 80053b8 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 80054d0: 69aa ldr r2, [r5, #24] 80054d2: 645a str r2, [r3, #68] @ 0x44 80054d4: e7e5 b.n 80054a2 80054d6: bf00 nop 80054d8: 20008000 .word 0x20008000 080054dc : * @brief DMA underrun DAC callback for Channel2. * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) 80054dc: 4770 bx lr 80054de: bf00 nop 080054e0 : * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80054e0: 4936 ldr r1, [pc, #216] @ (80055bc ) { 80054e2: 4602 mov r2, r0 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80054e4: 6803 ldr r3, [r0, #0] 80054e6: 428b cmp r3, r1 80054e8: d033 beq.n 8005552 80054ea: 3118 adds r1, #24 80054ec: 1a59 subs r1, r3, r1 80054ee: fab1 f181 clz r1, r1 80054f2: 0949 lsrs r1, r1, #5 80054f4: bb69 cbnz r1, 8005552 80054f6: 4832 ldr r0, [pc, #200] @ (80055c0 ) 80054f8: 4283 cmp r3, r0 80054fa: d03e beq.n 800557a 80054fc: 3018 adds r0, #24 80054fe: 4283 cmp r3, r0 8005500: d03e beq.n 8005580 8005502: 3018 adds r0, #24 8005504: 4283 cmp r3, r0 8005506: d034 beq.n 8005572 8005508: 3018 adds r0, #24 800550a: 4283 cmp r3, r0 800550c: d03b beq.n 8005586 800550e: 3018 adds r0, #24 8005510: 4283 cmp r3, r0 8005512: d03e beq.n 8005592 8005514: 3018 adds r0, #24 8005516: 4283 cmp r3, r0 8005518: d02a beq.n 8005570 800551a: f500 7056 add.w r0, r0, #856 @ 0x358 800551e: 4283 cmp r3, r0 8005520: d035 beq.n 800558e 8005522: 4928 ldr r1, [pc, #160] @ (80055c4 ) 8005524: 428b cmp r3, r1 8005526: d031 beq.n 800558c 8005528: 3118 adds r1, #24 800552a: 428b cmp r3, r1 800552c: d034 beq.n 8005598 800552e: 3118 adds r1, #24 8005530: 428b cmp r3, r1 8005532: d034 beq.n 800559e 8005534: 3118 adds r1, #24 8005536: 428b cmp r3, r1 8005538: d034 beq.n 80055a4 800553a: 3118 adds r1, #24 800553c: 428b cmp r3, r1 800553e: d034 beq.n 80055aa 8005540: 3118 adds r1, #24 8005542: 428b cmp r3, r1 8005544: d034 beq.n 80055b0 8005546: 3118 adds r1, #24 8005548: 428b cmp r3, r1 800554a: d034 beq.n 80055b6 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 800554c: f023 00ff bic.w r0, r3, #255 @ 0xff 8005550: e011 b.n 8005576 uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8005552: b2db uxtb r3, r3 8005554: 491c ldr r1, [pc, #112] @ (80055c8 ) hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 8005556: 481d ldr r0, [pc, #116] @ (80055cc ) uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8005558: 3b10 subs r3, #16 800555a: fba1 1303 umull r1, r3, r1, r3 { 800555e: b410 push {r4} uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8005560: 091b lsrs r3, r3, #4 hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 8005562: 4c1b ldr r4, [pc, #108] @ (80055d0 ) 8005564: 5ce1 ldrb r1, [r4, r3] } return hdma->StreamBaseAddress; } 8005566: f85d 4b04 ldr.w r4, [sp], #4 hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 800556a: e9c2 0116 strd r0, r1, [r2, #88] @ 0x58 } 800556e: 4770 bx lr 8005570: 2116 movs r1, #22 8005572: 4818 ldr r0, [pc, #96] @ (80055d4 ) hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 8005574: 65d1 str r1, [r2, #92] @ 0x5c hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 8005576: 6590 str r0, [r2, #88] @ 0x58 } 8005578: 4770 bx lr 800557a: 2110 movs r1, #16 800557c: 4813 ldr r0, [pc, #76] @ (80055cc ) 800557e: e7f9 b.n 8005574 8005580: 2116 movs r1, #22 8005582: 4812 ldr r0, [pc, #72] @ (80055cc ) 8005584: e7f6 b.n 8005574 8005586: 2106 movs r1, #6 8005588: 4812 ldr r0, [pc, #72] @ (80055d4 ) 800558a: e7f3 b.n 8005574 800558c: 2106 movs r1, #6 800558e: 4812 ldr r0, [pc, #72] @ (80055d8 ) 8005590: e7f0 b.n 8005574 8005592: 2110 movs r1, #16 8005594: 480f ldr r0, [pc, #60] @ (80055d4 ) 8005596: e7ed b.n 8005574 8005598: 2110 movs r1, #16 800559a: 480f ldr r0, [pc, #60] @ (80055d8 ) 800559c: e7ea b.n 8005574 800559e: 2116 movs r1, #22 80055a0: 480d ldr r0, [pc, #52] @ (80055d8 ) 80055a2: e7e7 b.n 8005574 80055a4: 2100 movs r1, #0 80055a6: 480d ldr r0, [pc, #52] @ (80055dc ) 80055a8: e7e4 b.n 8005574 80055aa: 2106 movs r1, #6 80055ac: 480b ldr r0, [pc, #44] @ (80055dc ) 80055ae: e7e1 b.n 8005574 80055b0: 2110 movs r1, #16 80055b2: 480a ldr r0, [pc, #40] @ (80055dc ) 80055b4: e7de b.n 8005574 80055b6: 2116 movs r1, #22 80055b8: 4808 ldr r0, [pc, #32] @ (80055dc ) 80055ba: e7db b.n 8005574 80055bc: 40020010 .word 0x40020010 80055c0: 40020040 .word 0x40020040 80055c4: 40020428 .word 0x40020428 80055c8: aaaaaaab .word 0xaaaaaaab 80055cc: 40020000 .word 0x40020000 80055d0: 08011a24 .word 0x08011a24 80055d4: 40020004 .word 0x40020004 80055d8: 40020400 .word 0x40020400 80055dc: 40020404 .word 0x40020404 080055e0 : * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 80055e0: 6802 ldr r2, [r0, #0] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80055e2: 4b27 ldr r3, [pc, #156] @ (8005680 ) 80055e4: 4927 ldr r1, [pc, #156] @ (8005684 ) { 80055e6: b430 push {r4, r5} if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80055e8: 4d27 ldr r5, [pc, #156] @ (8005688 ) 80055ea: 4c28 ldr r4, [pc, #160] @ (800568c ) 80055ec: 42aa cmp r2, r5 80055ee: bf18 it ne 80055f0: 429a cmpne r2, r3 80055f2: bf0c ite eq 80055f4: 2301 moveq r3, #1 80055f6: 2300 movne r3, #0 80055f8: 428a cmp r2, r1 80055fa: bf08 it eq 80055fc: f043 0301 orreq.w r3, r3, #1 8005600: 3128 adds r1, #40 @ 0x28 8005602: 42a2 cmp r2, r4 8005604: bf08 it eq 8005606: f043 0301 orreq.w r3, r3, #1 800560a: 3428 adds r4, #40 @ 0x28 800560c: 428a cmp r2, r1 800560e: bf08 it eq 8005610: f043 0301 orreq.w r3, r3, #1 8005614: 3128 adds r1, #40 @ 0x28 8005616: 42a2 cmp r2, r4 8005618: bf08 it eq 800561a: f043 0301 orreq.w r3, r3, #1 800561e: 428a cmp r2, r1 8005620: bf08 it eq 8005622: f043 0301 orreq.w r3, r3, #1 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } else { /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8005626: b2d1 uxtb r1, r2 if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8005628: b913 cbnz r3, 8005630 800562a: 4b19 ldr r3, [pc, #100] @ (8005690 ) 800562c: 429a cmp r2, r3 800562e: d112 bne.n 8005656 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 8005630: f1a1 0308 sub.w r3, r1, #8 8005634: 4917 ldr r1, [pc, #92] @ (8005694 ) hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 8005636: 4a18 ldr r2, [pc, #96] @ (8005698 ) stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 8005638: fba1 1303 umull r1, r3, r1, r3 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800563c: 2101 movs r1, #1 800563e: 4c17 ldr r4, [pc, #92] @ (800569c ) hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 8005640: eb02 1213 add.w r2, r2, r3, lsr #4 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8005644: f3c3 1304 ubfx r3, r3, #4, #5 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 8005648: 0092 lsls r2, r2, #2 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800564a: 4099 lsls r1, r3 800564c: 6681 str r1, [r0, #104] @ 0x68 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800564e: e9c0 2418 strd r2, r4, [r0, #96] @ 0x60 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 8005652: bc30 pop {r4, r5} 8005654: 4770 bx lr stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8005656: f1a1 0310 sub.w r3, r1, #16 if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800565a: 4911 ldr r1, [pc, #68] @ (80056a0 ) stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800565c: 4c11 ldr r4, [pc, #68] @ (80056a4 ) if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800565e: 4411 add r1, r2 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8005660: fba4 4303 umull r4, r3, r4, r3 if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 8005664: 29a8 cmp r1, #168 @ 0xa8 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8005666: ea4f 1313 mov.w r3, r3, lsr #4 if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800566a: d800 bhi.n 800566e stream_number += 8U; 800566c: 3308 adds r3, #8 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800566e: 4a0e ldr r2, [pc, #56] @ (80056a8 ) hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8005670: f003 041f and.w r4, r3, #31 8005674: 2101 movs r1, #1 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 8005676: 441a add r2, r3 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8005678: 40a1 lsls r1, r4 800567a: 4c0c ldr r4, [pc, #48] @ (80056ac ) hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800567c: 0092 lsls r2, r2, #2 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800567e: e7e5 b.n 800564c 8005680: 58025408 .word 0x58025408 8005684: 58025430 .word 0x58025430 8005688: 5802541c .word 0x5802541c 800568c: 58025444 .word 0x58025444 8005690: 58025494 .word 0x58025494 8005694: cccccccd .word 0xcccccccd 8005698: 16009600 .word 0x16009600 800569c: 58025880 .word 0x58025880 80056a0: bffdfbf0 .word 0xbffdfbf0 80056a4: aaaaaaab .word 0xaaaaaaab 80056a8: 10008200 .word 0x10008200 80056ac: 40020880 .word 0x40020880 080056b0 : { 80056b0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80056b4: 4605 mov r5, r0 80056b6: b083 sub sp, #12 uint32_t tickstart = HAL_GetTick(); 80056b8: f7fe fc8a bl 8003fd0 if(hdma == NULL) 80056bc: 2d00 cmp r5, #0 80056be: f000 8203 beq.w 8005ac8 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80056c2: 682c ldr r4, [r5, #0] 80056c4: 4606 mov r6, r0 80056c6: 4b65 ldr r3, [pc, #404] @ (800585c ) 80056c8: 429c cmp r4, r3 80056ca: f000 80bc beq.w 8005846 80056ce: 3318 adds r3, #24 80056d0: 429c cmp r4, r3 80056d2: f000 80b8 beq.w 8005846 80056d6: 3318 adds r3, #24 80056d8: 429c cmp r4, r3 80056da: f000 80b4 beq.w 8005846 80056de: 3318 adds r3, #24 80056e0: 429c cmp r4, r3 80056e2: f000 80b0 beq.w 8005846 80056e6: 3318 adds r3, #24 80056e8: 429c cmp r4, r3 80056ea: f000 80ac beq.w 8005846 80056ee: 3318 adds r3, #24 80056f0: 429c cmp r4, r3 80056f2: f000 80a8 beq.w 8005846 80056f6: 3318 adds r3, #24 80056f8: 429c cmp r4, r3 80056fa: f000 80a4 beq.w 8005846 80056fe: 3318 adds r3, #24 8005700: 429c cmp r4, r3 8005702: f000 80a0 beq.w 8005846 8005706: f503 7356 add.w r3, r3, #856 @ 0x358 800570a: 429c cmp r4, r3 800570c: f000 809b beq.w 8005846 8005710: 3318 adds r3, #24 8005712: 429c cmp r4, r3 8005714: f000 8097 beq.w 8005846 8005718: 3318 adds r3, #24 800571a: 429c cmp r4, r3 800571c: f000 8093 beq.w 8005846 8005720: 3318 adds r3, #24 8005722: 429c cmp r4, r3 8005724: f000 808f beq.w 8005846 8005728: 3318 adds r3, #24 800572a: 429c cmp r4, r3 800572c: f000 808b beq.w 8005846 8005730: 3318 adds r3, #24 8005732: 429c cmp r4, r3 8005734: f000 8087 beq.w 8005846 8005738: 3318 adds r3, #24 800573a: 429c cmp r4, r3 800573c: f000 8083 beq.w 8005846 8005740: 3318 adds r3, #24 8005742: 429c cmp r4, r3 8005744: d07f beq.n 8005846 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8005746: 4946 ldr r1, [pc, #280] @ (8005860 ) 8005748: 4a46 ldr r2, [pc, #280] @ (8005864 ) 800574a: 4b47 ldr r3, [pc, #284] @ (8005868 ) 800574c: eba4 0901 sub.w r9, r4, r1 8005750: 1aa2 subs r2, r4, r2 8005752: 4f46 ldr r7, [pc, #280] @ (800586c ) 8005754: eba4 0803 sub.w r8, r4, r3 8005758: fab9 f989 clz r9, r9 800575c: 3314 adds r3, #20 800575e: fab2 f282 clz r2, r2 8005762: ea4f 1959 mov.w r9, r9, lsr #5 8005766: fab8 f888 clz r8, r8 800576a: eba4 0a03 sub.w sl, r4, r3 800576e: 0952 lsrs r2, r2, #5 8005770: ea4f 1858 mov.w r8, r8, lsr #5 8005774: 1be7 subs r7, r4, r7 8005776: faba fa8a clz sl, sl 800577a: ea49 0102 orr.w r1, r9, r2 800577e: 4e3c ldr r6, [pc, #240] @ (8005870 ) 8005780: fab7 f787 clz r7, r7 8005784: 483b ldr r0, [pc, #236] @ (8005874 ) 8005786: ea4f 1a5a mov.w sl, sl, lsr #5 800578a: ea48 0101 orr.w r1, r8, r1 800578e: 1ba6 subs r6, r4, r6 8005790: eba4 0b00 sub.w fp, r4, r0 8005794: 097f lsrs r7, r7, #5 8005796: ea4a 0101 orr.w r1, sl, r1 800579a: fab6 f686 clz r6, r6 800579e: 3014 adds r0, #20 80057a0: fabb fb8b clz fp, fp 80057a4: 4339 orrs r1, r7 80057a6: 0976 lsrs r6, r6, #5 80057a8: 1a23 subs r3, r4, r0 80057aa: ea4f 1b5b mov.w fp, fp, lsr #5 80057ae: 4331 orrs r1, r6 80057b0: fab3 f383 clz r3, r3 80057b4: ea5b 0101 orrs.w r1, fp, r1 80057b8: ea4f 1353 mov.w r3, r3, lsr #5 80057bc: 9301 str r3, [sp, #4] 80057be: d102 bne.n 80057c6 80057c0: 2b00 cmp r3, #0 80057c2: f000 81d4 beq.w 8005b6e hdma->State = HAL_DMA_STATE_BUSY; 80057c6: 2102 movs r1, #2 registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 80057c8: f8df c0b4 ldr.w ip, [pc, #180] @ 8005880 hdma->State = HAL_DMA_STATE_BUSY; 80057cc: f885 1035 strb.w r1, [r5, #53] @ 0x35 __HAL_UNLOCK(hdma); 80057d0: 2100 movs r1, #0 80057d2: f885 1034 strb.w r1, [r5, #52] @ 0x34 registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 80057d6: 6821 ldr r1, [r4, #0] registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 80057d8: ea01 0c0c and.w ip, r1, ip registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80057dc: 68a9 ldr r1, [r5, #8] 80057de: 2940 cmp r1, #64 @ 0x40 80057e0: f000 81c2 beq.w 8005b68 80057e4: f1a1 0180 sub.w r1, r1, #128 @ 0x80 80057e8: fab1 f181 clz r1, r1 80057ec: 0949 lsrs r1, r1, #5 80057ee: ea4f 3e81 mov.w lr, r1, lsl #14 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80057f2: 6929 ldr r1, [r5, #16] DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 80057f4: 68e8 ldr r0, [r5, #12] DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80057f6: 08c9 lsrs r1, r1, #3 hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 80057f8: 4b1f ldr r3, [pc, #124] @ (8005878 ) 80057fa: 9200 str r2, [sp, #0] 80057fc: ea41 00d0 orr.w r0, r1, r0, lsr #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8005800: 6969 ldr r1, [r5, #20] hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8005802: 4423 add r3, r4 8005804: ea40 00d1 orr.w r0, r0, r1, lsr #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8005808: 69a9 ldr r1, [r5, #24] 800580a: ea40 00d1 orr.w r0, r0, r1, lsr #3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 800580e: 69e9 ldr r1, [r5, #28] 8005810: ea40 00d1 orr.w r0, r0, r1, lsr #3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8005814: 6a29 ldr r1, [r5, #32] 8005816: ea40 1111 orr.w r1, r0, r1, lsr #4 800581a: ea41 010c orr.w r1, r1, ip registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 800581e: ea4e 0101 orr.w r1, lr, r1 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8005822: 6021 str r1, [r4, #0] hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8005824: 4915 ldr r1, [pc, #84] @ (800587c ) 8005826: fba1 0103 umull r0, r1, r1, r3 regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 800582a: 4628 mov r0, r5 hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 800582c: 0909 lsrs r1, r1, #4 800582e: 0089 lsls r1, r1, #2 8005830: 65e9 str r1, [r5, #92] @ 0x5c regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8005832: f7ff fe55 bl 80054e0 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8005836: 6de9 ldr r1, [r5, #92] @ 0x5c 8005838: 9a00 ldr r2, [sp, #0] 800583a: f001 041f and.w r4, r1, #31 800583e: 2101 movs r1, #1 8005840: 40a1 lsls r1, r4 8005842: 6041 str r1, [r0, #4] 8005844: e0e2 b.n 8005a0c hdma->State = HAL_DMA_STATE_BUSY; 8005846: 2302 movs r3, #2 8005848: f885 3035 strb.w r3, [r5, #53] @ 0x35 __HAL_UNLOCK(hdma); 800584c: 2300 movs r3, #0 800584e: f885 3034 strb.w r3, [r5, #52] @ 0x34 __HAL_DMA_DISABLE(hdma); 8005852: 6823 ldr r3, [r4, #0] 8005854: f023 0301 bic.w r3, r3, #1 8005858: 6023 str r3, [r4, #0] 800585a: e01a b.n 8005892 800585c: 40020010 .word 0x40020010 8005860: 58025408 .word 0x58025408 8005864: 5802541c .word 0x5802541c 8005868: 58025430 .word 0x58025430 800586c: 58025458 .word 0x58025458 8005870: 5802546c .word 0x5802546c 8005874: 58025480 .word 0x58025480 8005878: a7fdabf8 .word 0xa7fdabf8 800587c: cccccccd .word 0xcccccccd 8005880: fffe000f .word 0xfffe000f if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8005884: f7fe fba4 bl 8003fd0 8005888: 1b80 subs r0, r0, r6 800588a: 2805 cmp r0, #5 800588c: f200 8117 bhi.w 8005abe while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8005890: 682c ldr r4, [r5, #0] 8005892: 6823 ldr r3, [r4, #0] 8005894: 07df lsls r7, r3, #31 8005896: d4f5 bmi.n 8005884 registerValue |= hdma->Init.Direction | 8005898: e9d5 3002 ldrd r3, r0, [r5, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 800589c: 6929 ldr r1, [r5, #16] registerValue |= hdma->Init.Direction | 800589e: 4303 orrs r3, r0 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80058a0: 69aa ldr r2, [r5, #24] registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 80058a2: 6820 ldr r0, [r4, #0] hdma->Init.PeriphInc | hdma->Init.MemInc | 80058a4: 430b orrs r3, r1 80058a6: 6969 ldr r1, [r5, #20] 80058a8: 430b orrs r3, r1 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 80058aa: 69e9 ldr r1, [r5, #28] 80058ac: 4313 orrs r3, r2 80058ae: 430b orrs r3, r1 registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 80058b0: 49b2 ldr r1, [pc, #712] @ (8005b7c ) 80058b2: 4001 ands r1, r0 hdma->Init.Mode | hdma->Init.Priority; 80058b4: 6a28 ldr r0, [r5, #32] 80058b6: 4303 orrs r3, r0 if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 80058b8: 48b1 ldr r0, [pc, #708] @ (8005b80 ) registerValue |= hdma->Init.Direction | 80058ba: 430b orrs r3, r1 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80058bc: 6a69 ldr r1, [r5, #36] @ 0x24 80058be: 2904 cmp r1, #4 80058c0: f000 8117 beq.w 8005af2 if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 80058c4: 6806 ldr r6, [r0, #0] 80058c6: 48af ldr r0, [pc, #700] @ (8005b84 ) 80058c8: 4030 ands r0, r6 80058ca: f1b0 5f00 cmp.w r0, #536870912 @ 0x20000000 80058ce: f080 80d5 bcs.w 8005a7c ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 80058d2: 6023 str r3, [r4, #0] registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 80058d4: 6963 ldr r3, [r4, #20] registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 80058d6: f023 0307 bic.w r3, r3, #7 registerValue |= hdma->Init.FIFOMode; 80058da: 430b orrs r3, r1 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 80058dc: 6163 str r3, [r4, #20] regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 80058de: 4628 mov r0, r5 80058e0: f7ff fdfe bl 80054e0 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80058e4: 6dea ldr r2, [r5, #92] @ 0x5c 80058e6: 233f movs r3, #63 @ 0x3f if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80058e8: 49a7 ldr r1, [pc, #668] @ (8005b88 ) regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80058ea: f002 021f and.w r2, r2, #31 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80058ee: 4fa7 ldr r7, [pc, #668] @ (8005b8c ) 80058f0: 4ea7 ldr r6, [pc, #668] @ (8005b90 ) regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80058f2: 4093 lsls r3, r2 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80058f4: 4aa7 ldr r2, [pc, #668] @ (8005b94 ) 80058f6: 1be7 subs r7, r4, r7 80058f8: 1ba6 subs r6, r4, r6 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80058fa: 6083 str r3, [r0, #8] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80058fc: eba4 0902 sub.w r9, r4, r2 8005900: 4ba5 ldr r3, [pc, #660] @ (8005b98 ) 8005902: 3214 adds r2, #20 8005904: fab9 f989 clz r9, r9 8005908: 48a4 ldr r0, [pc, #656] @ (8005b9c ) 800590a: eba4 0803 sub.w r8, r4, r3 800590e: 4ba4 ldr r3, [pc, #656] @ (8005ba0 ) 8005910: 1aa2 subs r2, r4, r2 8005912: ea4f 1959 mov.w r9, r9, lsr #5 8005916: 429c cmp r4, r3 8005918: bf18 it ne 800591a: 428c cmpne r4, r1 800591c: f103 0318 add.w r3, r3, #24 8005920: fab2 f282 clz r2, r2 8005924: fab8 f888 clz r8, r8 8005928: bf0c ite eq 800592a: 2101 moveq r1, #1 800592c: 2100 movne r1, #0 800592e: 0952 lsrs r2, r2, #5 8005930: fab7 f787 clz r7, r7 8005934: 429c cmp r4, r3 8005936: bf08 it eq 8005938: f041 0101 orreq.w r1, r1, #1 800593c: 3318 adds r3, #24 800593e: ea4f 1858 mov.w r8, r8, lsr #5 8005942: eba4 0b00 sub.w fp, r4, r0 8005946: 429c cmp r4, r3 8005948: bf08 it eq 800594a: f041 0101 orreq.w r1, r1, #1 800594e: 3318 adds r3, #24 8005950: 097f lsrs r7, r7, #5 8005952: fab6 f686 clz r6, r6 8005956: 429c cmp r4, r3 8005958: bf08 it eq 800595a: f041 0101 orreq.w r1, r1, #1 800595e: 3318 adds r3, #24 8005960: 3014 adds r0, #20 8005962: 0976 lsrs r6, r6, #5 8005964: 429c cmp r4, r3 8005966: bf08 it eq 8005968: f041 0101 orreq.w r1, r1, #1 800596c: 3318 adds r3, #24 800596e: fabb fb8b clz fp, fp 8005972: 429c cmp r4, r3 8005974: bf08 it eq 8005976: f041 0101 orreq.w r1, r1, #1 800597a: 3318 adds r3, #24 800597c: ea4f 1b5b mov.w fp, fp, lsr #5 8005980: 429c cmp r4, r3 8005982: bf08 it eq 8005984: f041 0101 orreq.w r1, r1, #1 8005988: f503 7356 add.w r3, r3, #856 @ 0x358 800598c: 429c cmp r4, r3 800598e: bf08 it eq 8005990: f041 0101 orreq.w r1, r1, #1 8005994: 3318 adds r3, #24 8005996: 429c cmp r4, r3 8005998: bf08 it eq 800599a: f041 0101 orreq.w r1, r1, #1 800599e: 3318 adds r3, #24 80059a0: 429c cmp r4, r3 80059a2: bf08 it eq 80059a4: f041 0101 orreq.w r1, r1, #1 80059a8: 3318 adds r3, #24 80059aa: 429c cmp r4, r3 80059ac: bf08 it eq 80059ae: f041 0101 orreq.w r1, r1, #1 80059b2: 3318 adds r3, #24 80059b4: 429c cmp r4, r3 80059b6: bf08 it eq 80059b8: f041 0101 orreq.w r1, r1, #1 80059bc: 3318 adds r3, #24 80059be: 429c cmp r4, r3 80059c0: bf08 it eq 80059c2: f041 0101 orreq.w r1, r1, #1 80059c6: 3318 adds r3, #24 80059c8: 429c cmp r4, r3 80059ca: bf08 it eq 80059cc: f041 0101 orreq.w r1, r1, #1 80059d0: 3318 adds r3, #24 80059d2: 429c cmp r4, r3 80059d4: bf08 it eq 80059d6: f041 0101 orreq.w r1, r1, #1 80059da: 4b72 ldr r3, [pc, #456] @ (8005ba4 ) 80059dc: ea49 0101 orr.w r1, r9, r1 80059e0: eba4 0a03 sub.w sl, r4, r3 80059e4: 1a23 subs r3, r4, r0 80059e6: 4311 orrs r1, r2 80059e8: faba fa8a clz sl, sl 80059ec: fab3 f383 clz r3, r3 80059f0: ea48 0101 orr.w r1, r8, r1 80059f4: ea4f 1a5a mov.w sl, sl, lsr #5 80059f8: 095b lsrs r3, r3, #5 80059fa: ea4a 0101 orr.w r1, sl, r1 80059fe: 9301 str r3, [sp, #4] 8005a00: 4339 orrs r1, r7 8005a02: 4331 orrs r1, r6 8005a04: ea5b 0101 orrs.w r1, fp, r1 8005a08: d100 bne.n 8005a0c 8005a0a: b37b cbz r3, 8005a6c DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8005a0c: 4628 mov r0, r5 8005a0e: 9200 str r2, [sp, #0] 8005a10: f7ff fde6 bl 80055e0 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8005a14: 68a9 ldr r1, [r5, #8] 8005a16: 9a00 ldr r2, [sp, #0] 8005a18: 2980 cmp r1, #128 @ 0x80 8005a1a: d05e beq.n 8005ada hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8005a1c: 6868 ldr r0, [r5, #4] 8005a1e: 6e2b ldr r3, [r5, #96] @ 0x60 8005a20: b2c4 uxtb r4, r0 if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8005a22: 3801 subs r0, #1 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8005a24: e9d5 c119 ldrd ip, r1, [r5, #100] @ 0x64 if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8005a28: 2807 cmp r0, #7 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8005a2a: 601c str r4, [r3, #0] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8005a2c: f8cc 1004 str.w r1, [ip, #4] if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8005a30: d85a bhi.n 8005ae8 { uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8005a32: ea49 090a orr.w r9, r9, sl 8005a36: 9b01 ldr r3, [sp, #4] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 8005a38: 1e60 subs r0, r4, #1 if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8005a3a: ea48 0809 orr.w r8, r8, r9 8005a3e: ea47 0708 orr.w r7, r7, r8 8005a42: 433e orrs r6, r7 8005a44: ea43 0a06 orr.w sl, r3, r6 8005a48: ea5b 0a0a orrs.w sl, fp, sl 8005a4c: d102 bne.n 8005a54 8005a4e: 2a00 cmp r2, #0 8005a50: f000 8085 beq.w 8005b5e { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 8005a54: 4a54 ldr r2, [pc, #336] @ (8005ba8 ) hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 8005a56: 4955 ldr r1, [pc, #340] @ (8005bac ) hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 8005a58: 4422 add r2, r4 8005a5a: 0092 lsls r2, r2, #2 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 8005a5c: 2301 movs r3, #1 8005a5e: 4083 lsls r3, r0 hdma->DMAmuxRequestGen->RGCR = 0U; 8005a60: 2000 movs r0, #0 8005a62: e9c5 211b strd r2, r1, [r5, #108] @ 0x6c hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 8005a66: 676b str r3, [r5, #116] @ 0x74 hdma->DMAmuxRequestGen->RGCR = 0U; 8005a68: 6010 str r0, [r2, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8005a6a: 604b str r3, [r1, #4] hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8005a6c: 2000 movs r0, #0 hdma->State = HAL_DMA_STATE_READY; 8005a6e: 2301 movs r3, #1 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8005a70: 6568 str r0, [r5, #84] @ 0x54 hdma->State = HAL_DMA_STATE_READY; 8005a72: f885 3035 strb.w r3, [r5, #53] @ 0x35 } 8005a76: b003 add sp, #12 8005a78: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8005a7c: 6868 ldr r0, [r5, #4] 8005a7e: f1a0 0629 sub.w r6, r0, #41 @ 0x29 8005a82: 2e1f cmp r6, #31 8005a84: d924 bls.n 8005ad0 8005a86: 384f subs r0, #79 @ 0x4f 8005a88: 2803 cmp r0, #3 8005a8a: d801 bhi.n 8005a90 registerValue |= DMA_SxCR_TRBUFF; 8005a8c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8005a90: 6023 str r3, [r4, #0] if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8005a92: 2904 cmp r1, #4 registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 8005a94: 6963 ldr r3, [r4, #20] registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8005a96: f023 0307 bic.w r3, r3, #7 registerValue |= hdma->Init.FIFOMode; 8005a9a: ea43 0301 orr.w r3, r3, r1 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8005a9e: f47f af1d bne.w 80058dc 8005aa2: 6ae8 ldr r0, [r5, #44] @ 0x2c registerValue |= hdma->Init.FIFOThreshold; 8005aa4: 6aa9 ldr r1, [r5, #40] @ 0x28 8005aa6: 430b orrs r3, r1 if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8005aa8: 2800 cmp r0, #0 8005aaa: f43f af17 beq.w 80058dc if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 8005aae: bb8a cbnz r2, 8005b14 switch (hdma->Init.FIFOThreshold) 8005ab0: 2901 cmp r1, #1 8005ab2: d04f beq.n 8005b54 8005ab4: f031 0202 bics.w r2, r1, #2 8005ab8: f47f af10 bne.w 80058dc 8005abc: e032 b.n 8005b24 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8005abe: 2220 movs r2, #32 hdma->State = HAL_DMA_STATE_ERROR; 8005ac0: 2303 movs r3, #3 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8005ac2: 656a str r2, [r5, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8005ac4: f885 3035 strb.w r3, [r5, #53] @ 0x35 return HAL_ERROR; 8005ac8: 2001 movs r0, #1 } 8005aca: b003 add sp, #12 8005acc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8005ad0: 4837 ldr r0, [pc, #220] @ (8005bb0 ) 8005ad2: 40f0 lsrs r0, r6 8005ad4: 07c0 lsls r0, r0, #31 8005ad6: d5db bpl.n 8005a90 8005ad8: e7d8 b.n 8005a8c hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8005ada: 2300 movs r3, #0 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8005adc: 6ea9 ldr r1, [r5, #104] @ 0x68 8005ade: e9d5 0218 ldrd r0, r2, [r5, #96] @ 0x60 hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8005ae2: 606b str r3, [r5, #4] hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8005ae4: 6003 str r3, [r0, #0] hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8005ae6: 6051 str r1, [r2, #4] hdma->DMAmuxRequestGen = 0U; 8005ae8: 2300 movs r3, #0 8005aea: e9c5 331b strd r3, r3, [r5, #108] @ 0x6c hdma->DMAmuxRequestGenStatusMask = 0U; 8005aee: 676b str r3, [r5, #116] @ 0x74 8005af0: e7bc b.n 8005a6c if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8005af2: 6807 ldr r7, [r0, #0] registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8005af4: e9d5 060b ldrd r0, r6, [r5, #44] @ 0x2c 8005af8: 4306 orrs r6, r0 8005afa: 4333 orrs r3, r6 if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8005afc: 4e21 ldr r6, [pc, #132] @ (8005b84 ) 8005afe: 403e ands r6, r7 8005b00: f1b6 5f00 cmp.w r6, #536870912 @ 0x20000000 8005b04: d2ba bcs.n 8005a7c ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8005b06: 6023 str r3, [r4, #0] registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 8005b08: 6963 ldr r3, [r4, #20] registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8005b0a: f023 0307 bic.w r3, r3, #7 registerValue |= hdma->Init.FIFOMode; 8005b0e: f043 0304 orr.w r3, r3, #4 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8005b12: e7c7 b.n 8005aa4 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8005b14: f5b2 5f00 cmp.w r2, #8192 @ 0x2000 8005b18: d00d beq.n 8005b36 switch (hdma->Init.FIFOThreshold) 8005b1a: 2902 cmp r1, #2 8005b1c: d905 bls.n 8005b2a 8005b1e: 2903 cmp r1, #3 8005b20: f47f aedc bne.w 80058dc if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8005b24: 01c2 lsls r2, r0, #7 8005b26: f57f aed9 bpl.w 80058dc hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8005b2a: 2240 movs r2, #64 @ 0x40 hdma->State = HAL_DMA_STATE_READY; 8005b2c: 2301 movs r3, #1 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8005b2e: 656a str r2, [r5, #84] @ 0x54 hdma->State = HAL_DMA_STATE_READY; 8005b30: f885 3035 strb.w r3, [r5, #53] @ 0x35 return HAL_ERROR; 8005b34: e7c8 b.n 8005ac8 switch (hdma->Init.FIFOThreshold) 8005b36: 2903 cmp r1, #3 8005b38: f63f aed0 bhi.w 80058dc 8005b3c: a201 add r2, pc, #4 @ (adr r2, 8005b44 ) 8005b3e: f852 f021 ldr.w pc, [r2, r1, lsl #2] 8005b42: bf00 nop 8005b44: 08005b2b .word 0x08005b2b 8005b48: 08005b25 .word 0x08005b25 8005b4c: 08005b2b .word 0x08005b2b 8005b50: 08005b55 .word 0x08005b55 if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8005b54: f1b0 7fc0 cmp.w r0, #25165824 @ 0x1800000 8005b58: f47f aec0 bne.w 80058dc 8005b5c: e7e5 b.n 8005b2a hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8005b5e: 4a15 ldr r2, [pc, #84] @ (8005bb4 ) hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8005b60: 4915 ldr r1, [pc, #84] @ (8005bb8 ) hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 8005b62: 4422 add r2, r4 8005b64: 0092 lsls r2, r2, #2 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 8005b66: e779 b.n 8005a5c registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8005b68: f04f 0e10 mov.w lr, #16 8005b6c: e641 b.n 80057f2 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8005b6e: 2240 movs r2, #64 @ 0x40 hdma->State = HAL_DMA_STATE_ERROR; 8005b70: 2303 movs r3, #3 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8005b72: 656a str r2, [r5, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8005b74: f885 3035 strb.w r3, [r5, #53] @ 0x35 return HAL_ERROR; 8005b78: e7a6 b.n 8005ac8 8005b7a: bf00 nop 8005b7c: fe10803f .word 0xfe10803f 8005b80: 5c001000 .word 0x5c001000 8005b84: ffff0000 .word 0xffff0000 8005b88: 40020010 .word 0x40020010 8005b8c: 58025458 .word 0x58025458 8005b90: 5802546c .word 0x5802546c 8005b94: 58025408 .word 0x58025408 8005b98: 58025430 .word 0x58025430 8005b9c: 58025480 .word 0x58025480 8005ba0: 40020028 .word 0x40020028 8005ba4: 58025444 .word 0x58025444 8005ba8: 1600963f .word 0x1600963f 8005bac: 58025940 .word 0x58025940 8005bb0: c3c0003f .word 0xc3c0003f 8005bb4: 1000823f .word 0x1000823f 8005bb8: 40020940 .word 0x40020940 08005bbc : if(hdma == NULL) 8005bbc: 2800 cmp r0, #0 8005bbe: f000 8232 beq.w 8006026 { 8005bc2: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} __HAL_LOCK(hdma); 8005bc6: f890 4034 ldrb.w r4, [r0, #52] @ 0x34 { 8005bca: b083 sub sp, #12 __HAL_LOCK(hdma); 8005bcc: 2c01 cmp r4, #1 8005bce: f000 8226 beq.w 800601e 8005bd2: 2401 movs r4, #1 8005bd4: f880 4034 strb.w r4, [r0, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8005bd8: f890 4035 ldrb.w r4, [r0, #53] @ 0x35 8005bdc: 2c01 cmp r4, #1 8005bde: d009 beq.n 8005bf4 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8005be0: f44f 6200 mov.w r2, #2048 @ 0x800 __HAL_UNLOCK(hdma); 8005be4: 2300 movs r3, #0 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8005be6: 6542 str r2, [r0, #84] @ 0x54 __HAL_UNLOCK(hdma); 8005be8: f880 3034 strb.w r3, [r0, #52] @ 0x34 return HAL_ERROR; 8005bec: 2001 movs r0, #1 } 8005bee: b003 add sp, #12 8005bf0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} hdma->State = HAL_DMA_STATE_BUSY; 8005bf4: 2402 movs r4, #2 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8005bf6: 4e7d ldr r6, [pc, #500] @ (8005dec ) 8005bf8: f8df 81f8 ldr.w r8, [pc, #504] @ 8005df4 hdma->State = HAL_DMA_STATE_BUSY; 8005bfc: f880 4035 strb.w r4, [r0, #53] @ 0x35 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8005c00: 2400 movs r4, #0 __HAL_DMA_DISABLE(hdma); 8005c02: 4d7b ldr r5, [pc, #492] @ (8005df0 ) hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8005c04: 6544 str r4, [r0, #84] @ 0x54 __HAL_DMA_DISABLE(hdma); 8005c06: 6804 ldr r4, [r0, #0] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8005c08: f8df 91ec ldr.w r9, [pc, #492] @ 8005df8 8005c0c: 4544 cmp r4, r8 8005c0e: bf18 it ne 8005c10: 42b4 cmpne r4, r6 __HAL_DMA_DISABLE(hdma); 8005c12: f8df c1f8 ldr.w ip, [pc, #504] @ 8005e0c DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8005c16: 6d86 ldr r6, [r0, #88] @ 0x58 8005c18: bf0c ite eq 8005c1a: f04f 0b01 moveq.w fp, #1 8005c1e: f04f 0b00 movne.w fp, #0 8005c22: 9601 str r6, [sp, #4] 8005c24: 454c cmp r4, r9 8005c26: bf14 ite ne 8005c28: 46de movne lr, fp 8005c2a: f04b 0e01 orreq.w lr, fp, #1 __HAL_DMA_DISABLE(hdma); 8005c2e: 42ac cmp r4, r5 8005c30: bf18 it ne 8005c32: 4564 cmpne r4, ip 8005c34: bf0c ite eq 8005c36: 2501 moveq r5, #1 8005c38: 2500 movne r5, #0 8005c3a: f040 80e9 bne.w 8005e10 8005c3e: f8d4 c000 ldr.w ip, [r4] 8005c42: f02c 0c01 bic.w ip, ip, #1 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8005c46: e9d0 7619 ldrd r7, r6, [r0, #100] @ 0x64 __HAL_DMA_DISABLE(hdma); 8005c4a: f8c4 c000 str.w ip, [r4] if(hdma->DMAmuxRequestGen != 0U) 8005c4e: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8005c52: 607e str r6, [r7, #4] if(hdma->DMAmuxRequestGen != 0U) 8005c54: f1bc 0f00 cmp.w ip, #0 8005c58: d002 beq.n 8005c60 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8005c5a: e9d0 671c ldrd r6, r7, [r0, #112] @ 0x70 8005c5e: 6077 str r7, [r6, #4] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8005c60: 6dc7 ldr r7, [r0, #92] @ 0x5c 8005c62: f04f 083f mov.w r8, #63 @ 0x3f 8005c66: 9e01 ldr r6, [sp, #4] 8005c68: f007 091f and.w r9, r7, #31 8005c6c: fa08 f809 lsl.w r8, r8, r9 8005c70: f8c6 8008 str.w r8, [r6, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 8005c74: 6827 ldr r7, [r4, #0] 8005c76: f427 2780 bic.w r7, r7, #262144 @ 0x40000 8005c7a: 6027 str r7, [r4, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 8005c7c: 6063 str r3, [r4, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8005c7e: 6883 ldr r3, [r0, #8] 8005c80: 2b40 cmp r3, #64 @ 0x40 8005c82: f000 81d2 beq.w 800602a ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 8005c86: 60a1 str r1, [r4, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 8005c88: 60e2 str r2, [r4, #12] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8005c8a: 2d00 cmp r5, #0 8005c8c: f040 81a2 bne.w 8005fd4 8005c90: 4a58 ldr r2, [pc, #352] @ (8005df4 ) if(hdma->XferHalfCpltCallback != NULL) 8005c92: 6c03 ldr r3, [r0, #64] @ 0x40 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8005c94: 4294 cmp r4, r2 8005c96: f000 8201 beq.w 800609c 8005c9a: 4a57 ldr r2, [pc, #348] @ (8005df8 ) 8005c9c: 4294 cmp r4, r2 8005c9e: f000 8207 beq.w 80060b0 8005ca2: f1bb 0f00 cmp.w fp, #0 8005ca6: f040 81d7 bne.w 8006058 8005caa: 4a54 ldr r2, [pc, #336] @ (8005dfc ) if(hdma->XferHalfCpltCallback != NULL) 8005cac: 4619 mov r1, r3 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8005cae: 4294 cmp r4, r2 8005cb0: f000 821c beq.w 80060ec 8005cb4: 4a52 ldr r2, [pc, #328] @ (8005e00 ) 8005cb6: 4294 cmp r4, r2 8005cb8: f000 824c beq.w 8006154 8005cbc: 3218 adds r2, #24 8005cbe: 4294 cmp r4, r2 8005cc0: f000 8269 beq.w 8006196 8005cc4: f502 7256 add.w r2, r2, #856 @ 0x358 8005cc8: 4294 cmp r4, r2 8005cca: f000 8271 beq.w 80061b0 8005cce: 4b4d ldr r3, [pc, #308] @ (8005e04 ) 8005cd0: 429c cmp r4, r3 8005cd2: f000 82ce beq.w 8006272 8005cd6: 3318 adds r3, #24 8005cd8: 429c cmp r4, r3 8005cda: f000 82d5 beq.w 8006288 8005cde: 3318 adds r3, #24 8005ce0: 429c cmp r4, r3 8005ce2: f000 82e5 beq.w 80062b0 8005ce6: 3318 adds r3, #24 8005ce8: 429c cmp r4, r3 8005cea: f000 82fe beq.w 80062ea 8005cee: 3318 adds r3, #24 8005cf0: 429c cmp r4, r3 8005cf2: f000 830f beq.w 8006314 8005cf6: 3318 adds r3, #24 8005cf8: 429c cmp r4, r3 8005cfa: f000 8321 beq.w 8006340 8005cfe: 3318 adds r3, #24 8005d00: 429c cmp r4, r3 8005d02: f000 8349 beq.w 8006398 MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8005d06: 6823 ldr r3, [r4, #0] 8005d08: f023 030e bic.w r3, r3, #14 8005d0c: f043 030a orr.w r3, r3, #10 8005d10: 6023 str r3, [r4, #0] if(hdma->XferHalfCpltCallback != NULL) 8005d12: b119 cbz r1, 8005d1c ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 8005d14: 6823 ldr r3, [r4, #0] 8005d16: f043 0304 orr.w r3, r3, #4 8005d1a: 6023 str r3, [r4, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8005d1c: 4b38 ldr r3, [pc, #224] @ (8005e00 ) 8005d1e: 4a37 ldr r2, [pc, #220] @ (8005dfc ) 8005d20: 4294 cmp r4, r2 8005d22: bf18 it ne 8005d24: 429c cmpne r4, r3 8005d26: f102 0230 add.w r2, r2, #48 @ 0x30 8005d2a: bf0c ite eq 8005d2c: 2301 moveq r3, #1 8005d2e: 2300 movne r3, #0 8005d30: 4294 cmp r4, r2 8005d32: bf08 it eq 8005d34: f043 0301 orreq.w r3, r3, #1 8005d38: f502 7256 add.w r2, r2, #856 @ 0x358 8005d3c: 4294 cmp r4, r2 8005d3e: bf08 it eq 8005d40: f043 0301 orreq.w r3, r3, #1 8005d44: 3218 adds r2, #24 8005d46: 4294 cmp r4, r2 8005d48: bf08 it eq 8005d4a: f043 0301 orreq.w r3, r3, #1 8005d4e: 3218 adds r2, #24 8005d50: 4294 cmp r4, r2 8005d52: bf08 it eq 8005d54: f043 0301 orreq.w r3, r3, #1 8005d58: 3218 adds r2, #24 8005d5a: 4294 cmp r4, r2 8005d5c: bf08 it eq 8005d5e: f043 0301 orreq.w r3, r3, #1 8005d62: 3218 adds r2, #24 8005d64: 4294 cmp r4, r2 8005d66: bf08 it eq 8005d68: f043 0301 orreq.w r3, r3, #1 8005d6c: 3218 adds r2, #24 8005d6e: 4294 cmp r4, r2 8005d70: bf08 it eq 8005d72: f043 0301 orreq.w r3, r3, #1 8005d76: 3218 adds r2, #24 8005d78: 4294 cmp r4, r2 8005d7a: bf08 it eq 8005d7c: f043 0301 orreq.w r3, r3, #1 8005d80: 3218 adds r2, #24 8005d82: 4294 cmp r4, r2 8005d84: bf08 it eq 8005d86: f043 0301 orreq.w r3, r3, #1 8005d8a: 4a1f ldr r2, [pc, #124] @ (8005e08 ) 8005d8c: 4294 cmp r4, r2 8005d8e: bf08 it eq 8005d90: f043 0301 orreq.w r3, r3, #1 8005d94: 3214 adds r2, #20 8005d96: 4294 cmp r4, r2 8005d98: bf08 it eq 8005d9a: f043 0301 orreq.w r3, r3, #1 8005d9e: 3214 adds r2, #20 8005da0: 4294 cmp r4, r2 8005da2: bf08 it eq 8005da4: f043 0301 orreq.w r3, r3, #1 8005da8: 3214 adds r2, #20 8005daa: 4294 cmp r4, r2 8005dac: bf08 it eq 8005dae: f043 0301 orreq.w r3, r3, #1 8005db2: 3214 adds r2, #20 8005db4: 4294 cmp r4, r2 8005db6: bf08 it eq 8005db8: f043 0301 orreq.w r3, r3, #1 8005dbc: 3214 adds r2, #20 8005dbe: 4294 cmp r4, r2 8005dc0: bf08 it eq 8005dc2: f043 0301 orreq.w r3, r3, #1 8005dc6: 3214 adds r2, #20 8005dc8: 4294 cmp r4, r2 8005dca: bf08 it eq 8005dcc: f043 0301 orreq.w r3, r3, #1 8005dd0: 3214 adds r2, #20 8005dd2: 4294 cmp r4, r2 8005dd4: bf08 it eq 8005dd6: f043 0301 orreq.w r3, r3, #1 8005dda: b91b cbnz r3, 8005de4 8005ddc: f1be 0f00 cmp.w lr, #0 8005de0: f000 8115 beq.w 800600e 8005de4: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c 8005de8: e100 b.n 8005fec 8005dea: bf00 nop 8005dec: 40020070 .word 0x40020070 8005df0: 40020028 .word 0x40020028 8005df4: 40020040 .word 0x40020040 8005df8: 40020058 .word 0x40020058 8005dfc: 40020088 .word 0x40020088 8005e00: 400200a0 .word 0x400200a0 8005e04: 40020428 .word 0x40020428 8005e08: 58025408 .word 0x58025408 8005e0c: 40020010 .word 0x40020010 __HAL_DMA_DISABLE(hdma); 8005e10: 4544 cmp r4, r8 8005e12: f000 812f beq.w 8006074 8005e16: 454c cmp r4, r9 8005e18: f000 8154 beq.w 80060c4 8005e1c: f1bb 0f00 cmp.w fp, #0 8005e20: f040 8106 bne.w 8006030 8005e24: f8df c54c ldr.w ip, [pc, #1356] @ 8006374 8005e28: 4564 cmp r4, ip 8005e2a: f000 816b beq.w 8006104 8005e2e: f10c 0c18 add.w ip, ip, #24 8005e32: 4564 cmp r4, ip 8005e34: f000 817a beq.w 800612c 8005e38: f10c 0c18 add.w ip, ip, #24 8005e3c: 4564 cmp r4, ip 8005e3e: f000 8196 beq.w 800616e 8005e42: f50c 7c56 add.w ip, ip, #856 @ 0x358 8005e46: 4564 cmp r4, ip 8005e48: f000 81bd beq.w 80061c6 8005e4c: f10c 0c18 add.w ip, ip, #24 8005e50: 4564 cmp r4, ip 8005e52: f000 8205 beq.w 8006260 8005e56: f10c 0c18 add.w ip, ip, #24 8005e5a: 4564 cmp r4, ip 8005e5c: f000 821f beq.w 800629e 8005e60: f10c 0c18 add.w ip, ip, #24 8005e64: 4564 cmp r4, ip 8005e66: f000 822e beq.w 80062c6 8005e6a: f10c 0c18 add.w ip, ip, #24 8005e6e: 4564 cmp r4, ip 8005e70: f000 8232 beq.w 80062d8 8005e74: f10c 0c18 add.w ip, ip, #24 8005e78: 4564 cmp r4, ip 8005e7a: f000 8258 beq.w 800632e 8005e7e: f10c 0c18 add.w ip, ip, #24 8005e82: 4564 cmp r4, ip 8005e84: f000 8269 beq.w 800635a 8005e88: f10c 0c18 add.w ip, ip, #24 8005e8c: 4564 cmp r4, ip 8005e8e: f000 8290 beq.w 80063b2 8005e92: f8d4 c000 ldr.w ip, [r4] 8005e96: f02c 0c01 bic.w ip, ip, #1 8005e9a: f8c4 c000 str.w ip, [r4] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8005e9e: f8df c4d8 ldr.w ip, [pc, #1240] @ 8006378 8005ea2: 4564 cmp r4, ip 8005ea4: f040 81a6 bne.w 80061f4 if(hdma->DMAmuxRequestGen != 0U) 8005ea8: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8005eac: e9d0 6719 ldrd r6, r7, [r0, #100] @ 0x64 8005eb0: 6077 str r7, [r6, #4] if(hdma->DMAmuxRequestGen != 0U) 8005eb2: f1bc 0f00 cmp.w ip, #0 8005eb6: f43f aed3 beq.w 8005c60 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8005eba: e9d0 671c ldrd r6, r7, [r0, #112] @ 0x70 8005ebe: 6077 str r7, [r6, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8005ec0: f8df 84b0 ldr.w r8, [pc, #1200] @ 8006374 8005ec4: f8df 94b4 ldr.w r9, [pc, #1204] @ 800637c 8005ec8: 454c cmp r4, r9 8005eca: bf18 it ne 8005ecc: 4544 cmpne r4, r8 8005ece: f109 0918 add.w r9, r9, #24 8005ed2: bf0c ite eq 8005ed4: f04f 0801 moveq.w r8, #1 8005ed8: f04f 0800 movne.w r8, #0 8005edc: 454c cmp r4, r9 8005ede: bf08 it eq 8005ee0: f048 0801 orreq.w r8, r8, #1 8005ee4: f509 7956 add.w r9, r9, #856 @ 0x358 8005ee8: 454c cmp r4, r9 8005eea: bf08 it eq 8005eec: f048 0801 orreq.w r8, r8, #1 8005ef0: f109 0918 add.w r9, r9, #24 8005ef4: 454c cmp r4, r9 8005ef6: bf08 it eq 8005ef8: f048 0801 orreq.w r8, r8, #1 8005efc: f109 0918 add.w r9, r9, #24 8005f00: 454c cmp r4, r9 8005f02: bf08 it eq 8005f04: f048 0801 orreq.w r8, r8, #1 8005f08: f109 0918 add.w r9, r9, #24 8005f0c: 454c cmp r4, r9 8005f0e: bf08 it eq 8005f10: f048 0801 orreq.w r8, r8, #1 8005f14: f109 0918 add.w r9, r9, #24 8005f18: 454c cmp r4, r9 8005f1a: bf08 it eq 8005f1c: f048 0801 orreq.w r8, r8, #1 8005f20: f109 0918 add.w r9, r9, #24 8005f24: 454c cmp r4, r9 8005f26: bf08 it eq 8005f28: f048 0801 orreq.w r8, r8, #1 8005f2c: f109 0918 add.w r9, r9, #24 8005f30: 454c cmp r4, r9 8005f32: bf08 it eq 8005f34: f048 0801 orreq.w r8, r8, #1 8005f38: f1b8 0f00 cmp.w r8, #0 8005f3c: f47f ae90 bne.w 8005c60 8005f40: f8df 843c ldr.w r8, [pc, #1084] @ 8006380 8005f44: 4544 cmp r4, r8 8005f46: f43f ae8b beq.w 8005c60 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8005f4a: f8df 8438 ldr.w r8, [pc, #1080] @ 8006384 8005f4e: f8df 9438 ldr.w r9, [pc, #1080] @ 8006388 8005f52: 454c cmp r4, r9 8005f54: bf18 it ne 8005f56: 4544 cmpne r4, r8 8005f58: f109 0914 add.w r9, r9, #20 8005f5c: bf0c ite eq 8005f5e: f04f 0801 moveq.w r8, #1 8005f62: f04f 0800 movne.w r8, #0 8005f66: 454c cmp r4, r9 8005f68: bf08 it eq 8005f6a: f048 0801 orreq.w r8, r8, #1 8005f6e: f109 0914 add.w r9, r9, #20 8005f72: 454c cmp r4, r9 8005f74: bf08 it eq 8005f76: f048 0801 orreq.w r8, r8, #1 8005f7a: f109 0914 add.w r9, r9, #20 8005f7e: 454c cmp r4, r9 8005f80: bf08 it eq 8005f82: f048 0801 orreq.w r8, r8, #1 8005f86: f109 0914 add.w r9, r9, #20 8005f8a: 454c cmp r4, r9 8005f8c: bf08 it eq 8005f8e: f048 0801 orreq.w r8, r8, #1 8005f92: f109 0914 add.w r9, r9, #20 8005f96: 454c cmp r4, r9 8005f98: bf08 it eq 8005f9a: f048 0801 orreq.w r8, r8, #1 8005f9e: f1b8 0f00 cmp.w r8, #0 8005fa2: d104 bne.n 8005fae 8005fa4: f8df 83e4 ldr.w r8, [pc, #996] @ 800638c 8005fa8: 4544 cmp r4, r8 8005faa: f040 820d bne.w 80063c8 regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8005fae: 6dc6 ldr r6, [r0, #92] @ 0x5c 8005fb0: f04f 0801 mov.w r8, #1 8005fb4: f006 091f and.w r9, r6, #31 8005fb8: 9e01 ldr r6, [sp, #4] 8005fba: fa08 f809 lsl.w r8, r8, r9 8005fbe: f8c6 8004 str.w r8, [r6, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 8005fc2: 6063 str r3, [r4, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 8005fc4: 6883 ldr r3, [r0, #8] 8005fc6: 2b40 cmp r3, #64 @ 0x40 8005fc8: f000 81fc beq.w 80063c4 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 8005fcc: 60a1 str r1, [r4, #8] if(hdma->XferHalfCpltCallback != NULL) 8005fce: 6c03 ldr r3, [r0, #64] @ 0x40 ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 8005fd0: 60e2 str r2, [r4, #12] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8005fd2: e662 b.n 8005c9a MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8005fd4: 6823 ldr r3, [r4, #0] 8005fd6: f023 031e bic.w r3, r3, #30 8005fda: f043 0316 orr.w r3, r3, #22 8005fde: 6023 str r3, [r4, #0] if(hdma->XferHalfCpltCallback != NULL) 8005fe0: 6c03 ldr r3, [r0, #64] @ 0x40 8005fe2: b11b cbz r3, 8005fec ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 8005fe4: 6823 ldr r3, [r4, #0] 8005fe6: f043 0308 orr.w r3, r3, #8 8005fea: 6023 str r3, [r4, #0] if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8005fec: 6e03 ldr r3, [r0, #96] @ 0x60 8005fee: 681a ldr r2, [r3, #0] 8005ff0: 03d2 lsls r2, r2, #15 8005ff2: d503 bpl.n 8005ffc hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8005ff4: 681a ldr r2, [r3, #0] 8005ff6: f442 7280 orr.w r2, r2, #256 @ 0x100 8005ffa: 601a str r2, [r3, #0] if(hdma->DMAmuxRequestGen != 0U) 8005ffc: f1bc 0f00 cmp.w ip, #0 8006000: d005 beq.n 800600e hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8006002: f8dc 3000 ldr.w r3, [ip] 8006006: f443 7380 orr.w r3, r3, #256 @ 0x100 800600a: f8cc 3000 str.w r3, [ip] __HAL_DMA_ENABLE(hdma); 800600e: 6823 ldr r3, [r4, #0] HAL_StatusTypeDef status = HAL_OK; 8006010: 2000 movs r0, #0 __HAL_DMA_ENABLE(hdma); 8006012: f043 0301 orr.w r3, r3, #1 8006016: 6023 str r3, [r4, #0] } 8006018: b003 add sp, #12 800601a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} __HAL_LOCK(hdma); 800601e: 2002 movs r0, #2 } 8006020: b003 add sp, #12 8006022: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} return HAL_ERROR; 8006026: 2001 movs r0, #1 } 8006028: 4770 bx lr ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800602a: 60a2 str r2, [r4, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 800602c: 60e1 str r1, [r4, #12] 800602e: e62c b.n 8005c8a __HAL_DMA_DISABLE(hdma); 8006030: f8df a338 ldr.w sl, [pc, #824] @ 800636c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006034: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64 __HAL_DMA_DISABLE(hdma); 8006038: f8da 8070 ldr.w r8, [sl, #112] @ 0x70 if(hdma->DMAmuxRequestGen != 0U) 800603c: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c __HAL_DMA_DISABLE(hdma); 8006040: f028 0801 bic.w r8, r8, #1 8006044: f8ca 8070 str.w r8, [sl, #112] @ 0x70 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006048: 6e86 ldr r6, [r0, #104] @ 0x68 800604a: f8c9 6004 str.w r6, [r9, #4] if(hdma->DMAmuxRequestGen != 0U) 800604e: f1bc 0f00 cmp.w ip, #0 8006052: f47f ae02 bne.w 8005c5a 8006056: e603 b.n 8005c60 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8006058: 49c4 ldr r1, [pc, #784] @ (800636c ) 800605a: 6f0a ldr r2, [r1, #112] @ 0x70 800605c: f022 021e bic.w r2, r2, #30 8006060: f042 0216 orr.w r2, r2, #22 8006064: 670a str r2, [r1, #112] @ 0x70 if(hdma->XferHalfCpltCallback != NULL) 8006066: 2b00 cmp r3, #0 8006068: d0c0 beq.n 8005fec ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 800606a: 6823 ldr r3, [r4, #0] 800606c: f043 0308 orr.w r3, r3, #8 8006070: 6023 str r3, [r4, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8006072: e653 b.n 8005d1c __HAL_DMA_DISABLE(hdma); 8006074: f8df a2f4 ldr.w sl, [pc, #756] @ 800636c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006078: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64 __HAL_DMA_DISABLE(hdma); 800607c: f8da 8040 ldr.w r8, [sl, #64] @ 0x40 if(hdma->DMAmuxRequestGen != 0U) 8006080: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c __HAL_DMA_DISABLE(hdma); 8006084: f028 0801 bic.w r8, r8, #1 8006088: f8ca 8040 str.w r8, [sl, #64] @ 0x40 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800608c: 6e86 ldr r6, [r0, #104] @ 0x68 800608e: f8c9 6004 str.w r6, [r9, #4] if(hdma->DMAmuxRequestGen != 0U) 8006092: f1bc 0f00 cmp.w ip, #0 8006096: f47f ade0 bne.w 8005c5a 800609a: e5e1 b.n 8005c60 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 800609c: 49b3 ldr r1, [pc, #716] @ (800636c ) 800609e: 6c0a ldr r2, [r1, #64] @ 0x40 80060a0: f022 021e bic.w r2, r2, #30 80060a4: f042 0216 orr.w r2, r2, #22 80060a8: 640a str r2, [r1, #64] @ 0x40 if(hdma->XferHalfCpltCallback != NULL) 80060aa: 2b00 cmp r3, #0 80060ac: d1dd bne.n 800606a 80060ae: e79d b.n 8005fec MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 80060b0: 49ae ldr r1, [pc, #696] @ (800636c ) 80060b2: 6d8a ldr r2, [r1, #88] @ 0x58 80060b4: f022 021e bic.w r2, r2, #30 80060b8: f042 0216 orr.w r2, r2, #22 80060bc: 658a str r2, [r1, #88] @ 0x58 if(hdma->XferHalfCpltCallback != NULL) 80060be: 2b00 cmp r3, #0 80060c0: d1d3 bne.n 800606a 80060c2: e793 b.n 8005fec __HAL_DMA_DISABLE(hdma); 80060c4: f8df a2a4 ldr.w sl, [pc, #676] @ 800636c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80060c8: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64 __HAL_DMA_DISABLE(hdma); 80060cc: f8da 8058 ldr.w r8, [sl, #88] @ 0x58 if(hdma->DMAmuxRequestGen != 0U) 80060d0: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c __HAL_DMA_DISABLE(hdma); 80060d4: f028 0801 bic.w r8, r8, #1 80060d8: f8ca 8058 str.w r8, [sl, #88] @ 0x58 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80060dc: 6e86 ldr r6, [r0, #104] @ 0x68 80060de: f8c9 6004 str.w r6, [r9, #4] if(hdma->DMAmuxRequestGen != 0U) 80060e2: f1bc 0f00 cmp.w ip, #0 80060e6: f47f adb8 bne.w 8005c5a 80060ea: e5b9 b.n 8005c60 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 80060ec: 499f ldr r1, [pc, #636] @ (800636c ) 80060ee: f8d1 2088 ldr.w r2, [r1, #136] @ 0x88 80060f2: f022 021e bic.w r2, r2, #30 80060f6: f042 0216 orr.w r2, r2, #22 80060fa: f8c1 2088 str.w r2, [r1, #136] @ 0x88 if(hdma->XferHalfCpltCallback != NULL) 80060fe: 2b00 cmp r3, #0 8006100: d1b3 bne.n 800606a 8006102: e773 b.n 8005fec __HAL_DMA_DISABLE(hdma); 8006104: f8df a264 ldr.w sl, [pc, #612] @ 800636c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006108: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64 __HAL_DMA_DISABLE(hdma); 800610c: f8da 8088 ldr.w r8, [sl, #136] @ 0x88 if(hdma->DMAmuxRequestGen != 0U) 8006110: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c __HAL_DMA_DISABLE(hdma); 8006114: f028 0801 bic.w r8, r8, #1 8006118: f8ca 8088 str.w r8, [sl, #136] @ 0x88 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800611c: 6e86 ldr r6, [r0, #104] @ 0x68 800611e: f8c9 6004 str.w r6, [r9, #4] if(hdma->DMAmuxRequestGen != 0U) 8006122: f1bc 0f00 cmp.w ip, #0 8006126: f47f aec8 bne.w 8005eba 800612a: e6c9 b.n 8005ec0 __HAL_DMA_DISABLE(hdma); 800612c: f8df a23c ldr.w sl, [pc, #572] @ 800636c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006130: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64 __HAL_DMA_DISABLE(hdma); 8006134: f8da 80a0 ldr.w r8, [sl, #160] @ 0xa0 if(hdma->DMAmuxRequestGen != 0U) 8006138: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c __HAL_DMA_DISABLE(hdma); 800613c: f028 0801 bic.w r8, r8, #1 8006140: f8ca 80a0 str.w r8, [sl, #160] @ 0xa0 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006144: 6e86 ldr r6, [r0, #104] @ 0x68 8006146: f8c9 6004 str.w r6, [r9, #4] if(hdma->DMAmuxRequestGen != 0U) 800614a: f1bc 0f00 cmp.w ip, #0 800614e: f47f aeb4 bne.w 8005eba 8006152: e6b5 b.n 8005ec0 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8006154: 4985 ldr r1, [pc, #532] @ (800636c ) 8006156: f8d1 20a0 ldr.w r2, [r1, #160] @ 0xa0 800615a: f022 021e bic.w r2, r2, #30 800615e: f042 0216 orr.w r2, r2, #22 8006162: f8c1 20a0 str.w r2, [r1, #160] @ 0xa0 if(hdma->XferHalfCpltCallback != NULL) 8006166: 2b00 cmp r3, #0 8006168: f47f af7f bne.w 800606a 800616c: e73e b.n 8005fec __HAL_DMA_DISABLE(hdma); 800616e: f8df a1fc ldr.w sl, [pc, #508] @ 800636c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006172: f8d0 9064 ldr.w r9, [r0, #100] @ 0x64 __HAL_DMA_DISABLE(hdma); 8006176: f8da 80b8 ldr.w r8, [sl, #184] @ 0xb8 if(hdma->DMAmuxRequestGen != 0U) 800617a: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c __HAL_DMA_DISABLE(hdma); 800617e: f028 0801 bic.w r8, r8, #1 8006182: f8ca 80b8 str.w r8, [sl, #184] @ 0xb8 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006186: 6e86 ldr r6, [r0, #104] @ 0x68 8006188: f8c9 6004 str.w r6, [r9, #4] if(hdma->DMAmuxRequestGen != 0U) 800618c: f1bc 0f00 cmp.w ip, #0 8006190: f47f ae93 bne.w 8005eba 8006194: e694 b.n 8005ec0 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8006196: 4975 ldr r1, [pc, #468] @ (800636c ) 8006198: f8d1 20b8 ldr.w r2, [r1, #184] @ 0xb8 800619c: f022 021e bic.w r2, r2, #30 80061a0: f042 0216 orr.w r2, r2, #22 80061a4: f8c1 20b8 str.w r2, [r1, #184] @ 0xb8 if(hdma->XferHalfCpltCallback != NULL) 80061a8: 2b00 cmp r3, #0 80061aa: f47f af5e bne.w 800606a 80061ae: e71d b.n 8005fec MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 80061b0: 496f ldr r1, [pc, #444] @ (8006370 ) 80061b2: 690a ldr r2, [r1, #16] 80061b4: f022 021e bic.w r2, r2, #30 80061b8: f042 0216 orr.w r2, r2, #22 80061bc: 610a str r2, [r1, #16] if(hdma->XferHalfCpltCallback != NULL) 80061be: 2b00 cmp r3, #0 80061c0: f47f af53 bne.w 800606a 80061c4: e712 b.n 8005fec __HAL_DMA_DISABLE(hdma); 80061c6: f8df 81a8 ldr.w r8, [pc, #424] @ 8006370 80061ca: f8d8 c010 ldr.w ip, [r8, #16] 80061ce: f02c 0c01 bic.w ip, ip, #1 80061d2: f8c8 c010 str.w ip, [r8, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80061d6: f8df c1b8 ldr.w ip, [pc, #440] @ 8006390 80061da: 4564 cmp r4, ip 80061dc: f43f ae64 beq.w 8005ea8 80061e0: f10c 0c18 add.w ip, ip, #24 80061e4: 4564 cmp r4, ip 80061e6: f43f ae5f beq.w 8005ea8 80061ea: f10c 0c18 add.w ip, ip, #24 80061ee: 4564 cmp r4, ip 80061f0: f43f ae5a beq.w 8005ea8 80061f4: f8df c19c ldr.w ip, [pc, #412] @ 8006394 80061f8: 4564 cmp r4, ip 80061fa: f43f ae55 beq.w 8005ea8 80061fe: f10c 0c18 add.w ip, ip, #24 8006202: 4564 cmp r4, ip 8006204: f43f ae50 beq.w 8005ea8 8006208: f10c 0c18 add.w ip, ip, #24 800620c: 4564 cmp r4, ip 800620e: f43f ae4b beq.w 8005ea8 8006212: f10c 0c18 add.w ip, ip, #24 8006216: 4564 cmp r4, ip 8006218: f43f ae46 beq.w 8005ea8 800621c: f8df c164 ldr.w ip, [pc, #356] @ 8006384 8006220: 4564 cmp r4, ip 8006222: d06d beq.n 8006300 8006224: f10c 0c14 add.w ip, ip, #20 8006228: 4564 cmp r4, ip 800622a: d069 beq.n 8006300 800622c: f10c 0c14 add.w ip, ip, #20 8006230: 4564 cmp r4, ip 8006232: d065 beq.n 8006300 8006234: f10c 0c14 add.w ip, ip, #20 8006238: 4564 cmp r4, ip 800623a: d061 beq.n 8006300 800623c: f10c 0c14 add.w ip, ip, #20 8006240: 4564 cmp r4, ip 8006242: d05d beq.n 8006300 8006244: f10c 0c14 add.w ip, ip, #20 8006248: 4564 cmp r4, ip 800624a: d059 beq.n 8006300 800624c: f10c 0c14 add.w ip, ip, #20 8006250: 4564 cmp r4, ip 8006252: d055 beq.n 8006300 8006254: f10c 0c14 add.w ip, ip, #20 8006258: 4564 cmp r4, ip 800625a: d051 beq.n 8006300 if(hdma->XferHalfCpltCallback != NULL) 800625c: 6c01 ldr r1, [r0, #64] @ 0x40 800625e: e536 b.n 8005cce __HAL_DMA_DISABLE(hdma); 8006260: f8df 810c ldr.w r8, [pc, #268] @ 8006370 8006264: f8d8 c028 ldr.w ip, [r8, #40] @ 0x28 8006268: f02c 0c01 bic.w ip, ip, #1 800626c: f8c8 c028 str.w ip, [r8, #40] @ 0x28 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8006270: e61a b.n 8005ea8 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8006272: 4a3f ldr r2, [pc, #252] @ (8006370 ) 8006274: 6a93 ldr r3, [r2, #40] @ 0x28 8006276: f023 031e bic.w r3, r3, #30 800627a: f043 0316 orr.w r3, r3, #22 800627e: 6293 str r3, [r2, #40] @ 0x28 if(hdma->XferHalfCpltCallback != NULL) 8006280: 2900 cmp r1, #0 8006282: f47f aef2 bne.w 800606a 8006286: e5ad b.n 8005de4 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8006288: 4a39 ldr r2, [pc, #228] @ (8006370 ) 800628a: 6c13 ldr r3, [r2, #64] @ 0x40 800628c: f023 031e bic.w r3, r3, #30 8006290: f043 0316 orr.w r3, r3, #22 8006294: 6413 str r3, [r2, #64] @ 0x40 if(hdma->XferHalfCpltCallback != NULL) 8006296: 2900 cmp r1, #0 8006298: f47f aee7 bne.w 800606a 800629c: e5a2 b.n 8005de4 __HAL_DMA_DISABLE(hdma); 800629e: f8df 80d0 ldr.w r8, [pc, #208] @ 8006370 80062a2: f8d8 c040 ldr.w ip, [r8, #64] @ 0x40 80062a6: f02c 0c01 bic.w ip, ip, #1 80062aa: f8c8 c040 str.w ip, [r8, #64] @ 0x40 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80062ae: e5fb b.n 8005ea8 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 80062b0: 4a2f ldr r2, [pc, #188] @ (8006370 ) 80062b2: 6d93 ldr r3, [r2, #88] @ 0x58 80062b4: f023 031e bic.w r3, r3, #30 80062b8: f043 0316 orr.w r3, r3, #22 80062bc: 6593 str r3, [r2, #88] @ 0x58 if(hdma->XferHalfCpltCallback != NULL) 80062be: 2900 cmp r1, #0 80062c0: f47f aed3 bne.w 800606a 80062c4: e58e b.n 8005de4 __HAL_DMA_DISABLE(hdma); 80062c6: f8df 80a8 ldr.w r8, [pc, #168] @ 8006370 80062ca: f8d8 c058 ldr.w ip, [r8, #88] @ 0x58 80062ce: f02c 0c01 bic.w ip, ip, #1 80062d2: f8c8 c058 str.w ip, [r8, #88] @ 0x58 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80062d6: e5e2 b.n 8005e9e __HAL_DMA_DISABLE(hdma); 80062d8: f8df 8094 ldr.w r8, [pc, #148] @ 8006370 80062dc: f8d8 c070 ldr.w ip, [r8, #112] @ 0x70 80062e0: f02c 0c01 bic.w ip, ip, #1 80062e4: f8c8 c070 str.w ip, [r8, #112] @ 0x70 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80062e8: e784 b.n 80061f4 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 80062ea: 4a21 ldr r2, [pc, #132] @ (8006370 ) 80062ec: 6f13 ldr r3, [r2, #112] @ 0x70 80062ee: f023 031e bic.w r3, r3, #30 80062f2: f043 0316 orr.w r3, r3, #22 80062f6: 6713 str r3, [r2, #112] @ 0x70 if(hdma->XferHalfCpltCallback != NULL) 80062f8: 2900 cmp r1, #0 80062fa: f47f aeb6 bne.w 800606a 80062fe: e571 b.n 8005de4 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006300: e9d0 6719 ldrd r6, r7, [r0, #100] @ 0x64 if(hdma->DMAmuxRequestGen != 0U) 8006304: f8d0 c06c ldr.w ip, [r0, #108] @ 0x6c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006308: 6077 str r7, [r6, #4] if(hdma->DMAmuxRequestGen != 0U) 800630a: f1bc 0f00 cmp.w ip, #0 800630e: f47f add4 bne.w 8005eba 8006312: e61a b.n 8005f4a MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8006314: 4a16 ldr r2, [pc, #88] @ (8006370 ) 8006316: f8d2 3088 ldr.w r3, [r2, #136] @ 0x88 800631a: f023 031e bic.w r3, r3, #30 800631e: f043 0316 orr.w r3, r3, #22 8006322: f8c2 3088 str.w r3, [r2, #136] @ 0x88 if(hdma->XferHalfCpltCallback != NULL) 8006326: 2900 cmp r1, #0 8006328: f47f ae9f bne.w 800606a 800632c: e55a b.n 8005de4 __HAL_DMA_DISABLE(hdma); 800632e: f8df 8040 ldr.w r8, [pc, #64] @ 8006370 8006332: f8d8 c088 ldr.w ip, [r8, #136] @ 0x88 8006336: f02c 0c01 bic.w ip, ip, #1 800633a: f8c8 c088 str.w ip, [r8, #136] @ 0x88 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800633e: e5ae b.n 8005e9e MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8006340: 4a0b ldr r2, [pc, #44] @ (8006370 ) 8006342: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0 8006346: f023 031e bic.w r3, r3, #30 800634a: f043 0316 orr.w r3, r3, #22 800634e: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 if(hdma->XferHalfCpltCallback != NULL) 8006352: 2900 cmp r1, #0 8006354: f47f ae89 bne.w 800606a 8006358: e544 b.n 8005de4 __HAL_DMA_DISABLE(hdma); 800635a: f8df 8014 ldr.w r8, [pc, #20] @ 8006370 800635e: f8d8 c0a0 ldr.w ip, [r8, #160] @ 0xa0 8006362: f02c 0c01 bic.w ip, ip, #1 8006366: f8c8 c0a0 str.w ip, [r8, #160] @ 0xa0 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800636a: e734 b.n 80061d6 800636c: 40020000 .word 0x40020000 8006370: 40020400 .word 0x40020400 8006374: 40020088 .word 0x40020088 8006378: 40020458 .word 0x40020458 800637c: 400200a0 .word 0x400200a0 8006380: 400204b8 .word 0x400204b8 8006384: 58025408 .word 0x58025408 8006388: 5802541c .word 0x5802541c 800638c: 58025494 .word 0x58025494 8006390: 40020410 .word 0x40020410 8006394: 40020470 .word 0x40020470 MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8006398: 4a0c ldr r2, [pc, #48] @ (80063cc ) 800639a: f8d2 30b8 ldr.w r3, [r2, #184] @ 0xb8 800639e: f023 031e bic.w r3, r3, #30 80063a2: f043 0316 orr.w r3, r3, #22 80063a6: f8c2 30b8 str.w r3, [r2, #184] @ 0xb8 if(hdma->XferHalfCpltCallback != NULL) 80063aa: 2900 cmp r1, #0 80063ac: f47f ae5d bne.w 800606a 80063b0: e518 b.n 8005de4 __HAL_DMA_DISABLE(hdma); 80063b2: f8df 8018 ldr.w r8, [pc, #24] @ 80063cc 80063b6: f8d8 c0b8 ldr.w ip, [r8, #184] @ 0xb8 80063ba: f02c 0c01 bic.w ip, ip, #1 80063be: f8c8 c0b8 str.w ip, [r8, #184] @ 0xb8 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80063c2: e708 b.n 80061d6 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 80063c4: 60a2 str r2, [r4, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 80063c6: 60e1 str r1, [r4, #12] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80063c8: 6c03 ldr r3, [r0, #64] @ 0x40 80063ca: e46e b.n 8005caa 80063cc: 40020400 .word 0x40020400 080063d0 : { 80063d0: b570 push {r4, r5, r6, lr} 80063d2: 4604 mov r4, r0 uint32_t tickstart = HAL_GetTick(); 80063d4: f7fd fdfc bl 8003fd0 if(hdma == NULL) 80063d8: 2c00 cmp r4, #0 80063da: d06b beq.n 80064b4 if(hdma->State != HAL_DMA_STATE_BUSY) 80063dc: f894 3035 ldrb.w r3, [r4, #53] @ 0x35 80063e0: 2b02 cmp r3, #2 80063e2: d162 bne.n 80064aa if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80063e4: 6825 ldr r5, [r4, #0] 80063e6: 4606 mov r6, r0 80063e8: 4ba2 ldr r3, [pc, #648] @ (8006674 ) 80063ea: 429d cmp r5, r3 80063ec: d064 beq.n 80064b8 80063ee: 3318 adds r3, #24 80063f0: 429d cmp r5, r3 80063f2: d061 beq.n 80064b8 80063f4: 3318 adds r3, #24 80063f6: 429d cmp r5, r3 80063f8: f000 80f1 beq.w 80065de 80063fc: 3318 adds r3, #24 80063fe: 429d cmp r5, r3 8006400: f000 8118 beq.w 8006634 8006404: 3318 adds r3, #24 8006406: 429d cmp r5, r3 8006408: f000 8123 beq.w 8006652 800640c: 3318 adds r3, #24 800640e: 429d cmp r5, r3 8006410: f000 80fd beq.w 800660e 8006414: 3318 adds r3, #24 8006416: 429d cmp r5, r3 8006418: f000 8138 beq.w 800668c 800641c: 3318 adds r3, #24 800641e: 429d cmp r5, r3 8006420: f000 8147 beq.w 80066b2 8006424: f503 7356 add.w r3, r3, #856 @ 0x358 8006428: 429d cmp r5, r3 800642a: f000 8155 beq.w 80066d8 800642e: 3318 adds r3, #24 8006430: 429d cmp r5, r3 8006432: f000 8160 beq.w 80066f6 8006436: 3318 adds r3, #24 8006438: 429d cmp r5, r3 800643a: f000 816b beq.w 8006714 800643e: 3318 adds r3, #24 8006440: 429d cmp r5, r3 8006442: f000 8169 beq.w 8006718 8006446: 3318 adds r3, #24 8006448: 429d cmp r5, r3 800644a: f000 8167 beq.w 800671c 800644e: 3318 adds r3, #24 8006450: 429d cmp r5, r3 8006452: f000 8165 beq.w 8006720 8006456: 3318 adds r3, #24 8006458: 429d cmp r5, r3 800645a: f000 8165 beq.w 8006728 800645e: 3318 adds r3, #24 8006460: 429d cmp r5, r3 8006462: f000 815f beq.w 8006724 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8006466: 682b ldr r3, [r5, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8006468: 4a83 ldr r2, [pc, #524] @ (8006678 ) ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 800646a: f023 030e bic.w r3, r3, #14 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800646e: 4295 cmp r5, r2 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8006470: 602b str r3, [r5, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8006472: d014 beq.n 800649e 8006474: 4b81 ldr r3, [pc, #516] @ (800667c ) 8006476: 429d cmp r5, r3 8006478: d011 beq.n 800649e 800647a: 3314 adds r3, #20 800647c: 429d cmp r5, r3 800647e: d00e beq.n 800649e 8006480: 3314 adds r3, #20 8006482: 429d cmp r5, r3 8006484: d00b beq.n 800649e 8006486: 3314 adds r3, #20 8006488: 429d cmp r5, r3 800648a: d008 beq.n 800649e 800648c: 3314 adds r3, #20 800648e: 429d cmp r5, r3 8006490: d005 beq.n 800649e 8006492: 3314 adds r3, #20 8006494: 429d cmp r5, r3 8006496: d002 beq.n 800649e 8006498: 3314 adds r3, #20 800649a: 429d cmp r5, r3 800649c: d119 bne.n 80064d2 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800649e: 6e22 ldr r2, [r4, #96] @ 0x60 80064a0: 6813 ldr r3, [r2, #0] 80064a2: f423 7380 bic.w r3, r3, #256 @ 0x100 80064a6: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 80064a8: e013 b.n 80064d2 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80064aa: 2280 movs r2, #128 @ 0x80 __HAL_UNLOCK(hdma); 80064ac: 2300 movs r3, #0 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80064ae: 6562 str r2, [r4, #84] @ 0x54 __HAL_UNLOCK(hdma); 80064b0: f884 3034 strb.w r3, [r4, #52] @ 0x34 return HAL_ERROR; 80064b4: 2001 movs r0, #1 } 80064b6: bd70 pop {r4, r5, r6, pc} ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80064b8: 682b ldr r3, [r5, #0] hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80064ba: 6e22 ldr r2, [r4, #96] @ 0x60 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80064bc: f023 031e bic.w r3, r3, #30 80064c0: 602b str r3, [r5, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80064c2: 696b ldr r3, [r5, #20] 80064c4: f023 0380 bic.w r3, r3, #128 @ 0x80 80064c8: 616b str r3, [r5, #20] hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80064ca: 6813 ldr r3, [r2, #0] 80064cc: f423 7380 bic.w r3, r3, #256 @ 0x100 80064d0: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 80064d2: 682b ldr r3, [r5, #0] 80064d4: f023 0301 bic.w r3, r3, #1 80064d8: 602b str r3, [r5, #0] 80064da: e005 b.n 80064e8 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80064dc: f7fd fd78 bl 8003fd0 80064e0: 1b83 subs r3, r0, r6 80064e2: 2b05 cmp r3, #5 80064e4: f200 808a bhi.w 80065fc while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80064e8: 682b ldr r3, [r5, #0] 80064ea: 07db lsls r3, r3, #31 80064ec: d4f6 bmi.n 80064dc if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80064ee: 6823 ldr r3, [r4, #0] 80064f0: 4960 ldr r1, [pc, #384] @ (8006674 ) regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80064f2: 6de2 ldr r2, [r4, #92] @ 0x5c if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80064f4: 428b cmp r3, r1 regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80064f6: 6da0 ldr r0, [r4, #88] @ 0x58 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80064f8: f002 021f and.w r2, r2, #31 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80064fc: d05e beq.n 80065bc 80064fe: 3118 adds r1, #24 8006500: 428b cmp r3, r1 8006502: d05b beq.n 80065bc 8006504: 3118 adds r1, #24 8006506: 428b cmp r3, r1 8006508: d058 beq.n 80065bc 800650a: 3118 adds r1, #24 800650c: 428b cmp r3, r1 800650e: d055 beq.n 80065bc 8006510: 3118 adds r1, #24 8006512: 428b cmp r3, r1 8006514: d052 beq.n 80065bc 8006516: 3118 adds r1, #24 8006518: 428b cmp r3, r1 800651a: d04f beq.n 80065bc 800651c: 3118 adds r1, #24 800651e: 428b cmp r3, r1 8006520: d04c beq.n 80065bc 8006522: 3118 adds r1, #24 8006524: 428b cmp r3, r1 8006526: d049 beq.n 80065bc 8006528: f501 7156 add.w r1, r1, #856 @ 0x358 800652c: 428b cmp r3, r1 800652e: d045 beq.n 80065bc 8006530: 3118 adds r1, #24 8006532: 428b cmp r3, r1 8006534: d042 beq.n 80065bc 8006536: 3118 adds r1, #24 8006538: 428b cmp r3, r1 800653a: d03f beq.n 80065bc 800653c: 3118 adds r1, #24 800653e: 428b cmp r3, r1 8006540: d03c beq.n 80065bc 8006542: 3118 adds r1, #24 8006544: 428b cmp r3, r1 8006546: d039 beq.n 80065bc 8006548: 3118 adds r1, #24 800654a: 428b cmp r3, r1 800654c: d036 beq.n 80065bc 800654e: 3118 adds r1, #24 8006550: 428b cmp r3, r1 8006552: d033 beq.n 80065bc 8006554: 3118 adds r1, #24 8006556: 428b cmp r3, r1 8006558: d030 beq.n 80065bc regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800655a: 2101 movs r1, #1 800655c: 4091 lsls r1, r2 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800655e: 4a47 ldr r2, [pc, #284] @ (800667c ) regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8006560: 6041 str r1, [r0, #4] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8006562: 4845 ldr r0, [pc, #276] @ (8006678 ) 8006564: 4946 ldr r1, [pc, #280] @ (8006680 ) 8006566: 4283 cmp r3, r0 8006568: bf18 it ne 800656a: 4293 cmpne r3, r2 800656c: f100 003c add.w r0, r0, #60 @ 0x3c 8006570: bf0c ite eq 8006572: 2201 moveq r2, #1 8006574: 2200 movne r2, #0 8006576: 428b cmp r3, r1 8006578: bf08 it eq 800657a: f042 0201 orreq.w r2, r2, #1 800657e: 3128 adds r1, #40 @ 0x28 8006580: 4283 cmp r3, r0 8006582: bf08 it eq 8006584: f042 0201 orreq.w r2, r2, #1 8006588: 3028 adds r0, #40 @ 0x28 800658a: 428b cmp r3, r1 800658c: bf08 it eq 800658e: f042 0201 orreq.w r2, r2, #1 8006592: 3128 adds r1, #40 @ 0x28 8006594: 4283 cmp r3, r0 8006596: bf08 it eq 8006598: f042 0201 orreq.w r2, r2, #1 800659c: 428b cmp r3, r1 800659e: bf08 it eq 80065a0: f042 0201 orreq.w r2, r2, #1 80065a4: b96a cbnz r2, 80065c2 80065a6: 4a37 ldr r2, [pc, #220] @ (8006684 ) 80065a8: 4293 cmp r3, r2 80065aa: d00a beq.n 80065c2 __HAL_UNLOCK(hdma); 80065ac: 2300 movs r3, #0 hdma->State = HAL_DMA_STATE_READY; 80065ae: 2201 movs r2, #1 return HAL_OK; 80065b0: 4618 mov r0, r3 hdma->State = HAL_DMA_STATE_READY; 80065b2: f884 2035 strb.w r2, [r4, #53] @ 0x35 __HAL_UNLOCK(hdma); 80065b6: f884 3034 strb.w r3, [r4, #52] @ 0x34 } 80065ba: bd70 pop {r4, r5, r6, pc} regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80065bc: 233f movs r3, #63 @ 0x3f 80065be: 4093 lsls r3, r2 80065c0: 6083 str r3, [r0, #8] if(hdma->DMAmuxRequestGen != 0U) 80065c2: 6ee3 ldr r3, [r4, #108] @ 0x6c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80065c4: e9d4 2119 ldrd r2, r1, [r4, #100] @ 0x64 80065c8: 6051 str r1, [r2, #4] if(hdma->DMAmuxRequestGen != 0U) 80065ca: 2b00 cmp r3, #0 80065cc: d0ee beq.n 80065ac hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 80065ce: 681a ldr r2, [r3, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80065d0: e9d4 101c ldrd r1, r0, [r4, #112] @ 0x70 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 80065d4: f422 7280 bic.w r2, r2, #256 @ 0x100 80065d8: 601a str r2, [r3, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80065da: 6048 str r0, [r1, #4] 80065dc: e7e6 b.n 80065ac ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80065de: 4b2a ldr r3, [pc, #168] @ (8006688 ) 80065e0: 6c1a ldr r2, [r3, #64] @ 0x40 80065e2: f022 021e bic.w r2, r2, #30 80065e6: 641a str r2, [r3, #64] @ 0x40 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80065e8: 6d5a ldr r2, [r3, #84] @ 0x54 80065ea: f022 0280 bic.w r2, r2, #128 @ 0x80 80065ee: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80065f0: 6e22 ldr r2, [r4, #96] @ 0x60 80065f2: 6813 ldr r3, [r2, #0] 80065f4: f423 7380 bic.w r3, r3, #256 @ 0x100 80065f8: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 80065fa: e76a b.n 80064d2 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80065fc: 2120 movs r1, #32 hdma->State = HAL_DMA_STATE_ERROR; 80065fe: 2203 movs r2, #3 __HAL_UNLOCK(hdma); 8006600: 2300 movs r3, #0 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8006602: 6561 str r1, [r4, #84] @ 0x54 __HAL_UNLOCK(hdma); 8006604: f884 3034 strb.w r3, [r4, #52] @ 0x34 hdma->State = HAL_DMA_STATE_ERROR; 8006608: f884 2035 strb.w r2, [r4, #53] @ 0x35 return HAL_ERROR; 800660c: e752 b.n 80064b4 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 800660e: 4b1e ldr r3, [pc, #120] @ (8006688 ) 8006610: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 8006614: f022 021e bic.w r2, r2, #30 8006618: f8c3 2088 str.w r2, [r3, #136] @ 0x88 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800661c: f8d3 209c ldr.w r2, [r3, #156] @ 0x9c 8006620: f022 0280 bic.w r2, r2, #128 @ 0x80 8006624: f8c3 209c str.w r2, [r3, #156] @ 0x9c hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8006628: 6e22 ldr r2, [r4, #96] @ 0x60 800662a: 6813 ldr r3, [r2, #0] 800662c: f423 7380 bic.w r3, r3, #256 @ 0x100 8006630: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 8006632: e74e b.n 80064d2 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8006634: 4b14 ldr r3, [pc, #80] @ (8006688 ) 8006636: 6d9a ldr r2, [r3, #88] @ 0x58 8006638: f022 021e bic.w r2, r2, #30 800663c: 659a str r2, [r3, #88] @ 0x58 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800663e: 6eda ldr r2, [r3, #108] @ 0x6c 8006640: f022 0280 bic.w r2, r2, #128 @ 0x80 8006644: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8006646: 6e22 ldr r2, [r4, #96] @ 0x60 8006648: 6813 ldr r3, [r2, #0] 800664a: f423 7380 bic.w r3, r3, #256 @ 0x100 800664e: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 8006650: e73f b.n 80064d2 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8006652: 4b0d ldr r3, [pc, #52] @ (8006688 ) 8006654: 6f1a ldr r2, [r3, #112] @ 0x70 8006656: f022 021e bic.w r2, r2, #30 800665a: 671a str r2, [r3, #112] @ 0x70 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800665c: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8006660: f022 0280 bic.w r2, r2, #128 @ 0x80 8006664: f8c3 2084 str.w r2, [r3, #132] @ 0x84 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8006668: 6e22 ldr r2, [r4, #96] @ 0x60 800666a: 6813 ldr r3, [r2, #0] 800666c: f423 7380 bic.w r3, r3, #256 @ 0x100 8006670: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 8006672: e72e b.n 80064d2 8006674: 40020010 .word 0x40020010 8006678: 58025408 .word 0x58025408 800667c: 5802541c .word 0x5802541c 8006680: 58025430 .word 0x58025430 8006684: 58025494 .word 0x58025494 8006688: 40020000 .word 0x40020000 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 800668c: 4b27 ldr r3, [pc, #156] @ (800672c ) 800668e: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8006692: f022 021e bic.w r2, r2, #30 8006696: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800669a: f8d3 20b4 ldr.w r2, [r3, #180] @ 0xb4 800669e: f022 0280 bic.w r2, r2, #128 @ 0x80 80066a2: f8c3 20b4 str.w r2, [r3, #180] @ 0xb4 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80066a6: 6e22 ldr r2, [r4, #96] @ 0x60 80066a8: 6813 ldr r3, [r2, #0] 80066aa: f423 7380 bic.w r3, r3, #256 @ 0x100 80066ae: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 80066b0: e70f b.n 80064d2 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80066b2: 4b1e ldr r3, [pc, #120] @ (800672c ) 80066b4: f8d3 20b8 ldr.w r2, [r3, #184] @ 0xb8 80066b8: f022 021e bic.w r2, r2, #30 80066bc: f8c3 20b8 str.w r2, [r3, #184] @ 0xb8 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80066c0: f8d3 20cc ldr.w r2, [r3, #204] @ 0xcc 80066c4: f022 0280 bic.w r2, r2, #128 @ 0x80 80066c8: f8c3 20cc str.w r2, [r3, #204] @ 0xcc hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80066cc: 6e22 ldr r2, [r4, #96] @ 0x60 80066ce: 6813 ldr r3, [r2, #0] 80066d0: f423 7380 bic.w r3, r3, #256 @ 0x100 80066d4: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 80066d6: e6fc b.n 80064d2 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80066d8: 4b15 ldr r3, [pc, #84] @ (8006730 ) 80066da: 691a ldr r2, [r3, #16] 80066dc: f022 021e bic.w r2, r2, #30 80066e0: 611a str r2, [r3, #16] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80066e2: 6a5a ldr r2, [r3, #36] @ 0x24 80066e4: f022 0280 bic.w r2, r2, #128 @ 0x80 80066e8: 625a str r2, [r3, #36] @ 0x24 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80066ea: 6e22 ldr r2, [r4, #96] @ 0x60 80066ec: 6813 ldr r3, [r2, #0] 80066ee: f423 7380 bic.w r3, r3, #256 @ 0x100 80066f2: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 80066f4: e6ed b.n 80064d2 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80066f6: 4b0e ldr r3, [pc, #56] @ (8006730 ) 80066f8: 6a9a ldr r2, [r3, #40] @ 0x28 80066fa: f022 021e bic.w r2, r2, #30 80066fe: 629a str r2, [r3, #40] @ 0x28 ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8006700: 6bda ldr r2, [r3, #60] @ 0x3c 8006702: f022 0280 bic.w r2, r2, #128 @ 0x80 8006706: 63da str r2, [r3, #60] @ 0x3c hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8006708: 6e22 ldr r2, [r4, #96] @ 0x60 800670a: 6813 ldr r3, [r2, #0] 800670c: f423 7380 bic.w r3, r3, #256 @ 0x100 8006710: 6013 str r3, [r2, #0] __HAL_DMA_DISABLE(hdma); 8006712: e6de b.n 80064d2 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8006714: 4b06 ldr r3, [pc, #24] @ (8006730 ) 8006716: e763 b.n 80065e0 8006718: 4b05 ldr r3, [pc, #20] @ (8006730 ) 800671a: e78c b.n 8006636 800671c: 4b04 ldr r3, [pc, #16] @ (8006730 ) 800671e: e799 b.n 8006654 8006720: 4b03 ldr r3, [pc, #12] @ (8006730 ) 8006722: e775 b.n 8006610 8006724: 4b02 ldr r3, [pc, #8] @ (8006730 ) 8006726: e7c5 b.n 80066b4 8006728: 4b01 ldr r3, [pc, #4] @ (8006730 ) 800672a: e7b0 b.n 800668e 800672c: 40020000 .word 0x40020000 8006730: 40020400 .word 0x40020400 08006734 : if(hdma == NULL) 8006734: 2800 cmp r0, #0 8006736: f000 8096 beq.w 8006866 { 800673a: b538 push {r3, r4, r5, lr} if(hdma->State != HAL_DMA_STATE_BUSY) 800673c: f890 3035 ldrb.w r3, [r0, #53] @ 0x35 8006740: 2b02 cmp r3, #2 8006742: f040 8083 bne.w 800684c if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8006746: 6803 ldr r3, [r0, #0] 8006748: 4a48 ldr r2, [pc, #288] @ (800686c ) 800674a: 4293 cmp r3, r2 800674c: f000 8082 beq.w 8006854 8006750: 3218 adds r2, #24 8006752: 4293 cmp r3, r2 8006754: d07e beq.n 8006854 8006756: 3218 adds r2, #24 8006758: 4293 cmp r3, r2 800675a: d07b beq.n 8006854 800675c: 3218 adds r2, #24 800675e: 4293 cmp r3, r2 8006760: d078 beq.n 8006854 8006762: 3218 adds r2, #24 8006764: 4293 cmp r3, r2 8006766: d075 beq.n 8006854 8006768: 3218 adds r2, #24 800676a: 4293 cmp r3, r2 800676c: d072 beq.n 8006854 800676e: 3218 adds r2, #24 8006770: 4293 cmp r3, r2 8006772: d06f beq.n 8006854 8006774: 3218 adds r2, #24 8006776: 4293 cmp r3, r2 8006778: d06c beq.n 8006854 800677a: f502 7256 add.w r2, r2, #856 @ 0x358 800677e: 4293 cmp r3, r2 8006780: d068 beq.n 8006854 8006782: 3218 adds r2, #24 8006784: 4293 cmp r3, r2 8006786: d065 beq.n 8006854 8006788: 3218 adds r2, #24 800678a: 4293 cmp r3, r2 800678c: d062 beq.n 8006854 800678e: 3218 adds r2, #24 8006790: 4293 cmp r3, r2 8006792: d05f beq.n 8006854 8006794: 3218 adds r2, #24 8006796: 4293 cmp r3, r2 8006798: d05c beq.n 8006854 800679a: 3218 adds r2, #24 800679c: 4293 cmp r3, r2 800679e: d059 beq.n 8006854 80067a0: 3218 adds r2, #24 80067a2: 4293 cmp r3, r2 80067a4: d056 beq.n 8006854 80067a6: 3218 adds r2, #24 80067a8: 4293 cmp r3, r2 80067aa: d053 beq.n 8006854 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80067ac: 4a30 ldr r2, [pc, #192] @ (8006870 ) 80067ae: 4d31 ldr r5, [pc, #196] @ (8006874 ) ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80067b0: 6819 ldr r1, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80067b2: 42ab cmp r3, r5 80067b4: bf18 it ne 80067b6: 4293 cmpne r3, r2 80067b8: 4c2f ldr r4, [pc, #188] @ (8006878 ) ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80067ba: f021 010e bic.w r1, r1, #14 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80067be: f105 053c add.w r5, r5, #60 @ 0x3c 80067c2: bf0c ite eq 80067c4: 2201 moveq r2, #1 80067c6: 2200 movne r2, #0 ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80067c8: 6019 str r1, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80067ca: 42a3 cmp r3, r4 80067cc: bf08 it eq 80067ce: f042 0201 orreq.w r2, r2, #1 __HAL_DMA_DISABLE(hdma); 80067d2: 6819 ldr r1, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80067d4: 3428 adds r4, #40 @ 0x28 80067d6: 42ab cmp r3, r5 80067d8: bf08 it eq 80067da: f042 0201 orreq.w r2, r2, #1 __HAL_DMA_DISABLE(hdma); 80067de: f021 0101 bic.w r1, r1, #1 if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80067e2: 42a3 cmp r3, r4 80067e4: bf08 it eq 80067e6: f042 0201 orreq.w r2, r2, #1 80067ea: 3414 adds r4, #20 __HAL_DMA_DISABLE(hdma); 80067ec: 6019 str r1, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80067ee: 42a3 cmp r3, r4 80067f0: bf08 it eq 80067f2: f042 0201 orreq.w r2, r2, #1 80067f6: 4921 ldr r1, [pc, #132] @ (800687c ) 80067f8: 428b cmp r3, r1 80067fa: bf08 it eq 80067fc: f042 0201 orreq.w r2, r2, #1 8006800: b912 cbnz r2, 8006808 8006802: 4a1f ldr r2, [pc, #124] @ (8006880 ) 8006804: 4293 cmp r3, r2 8006806: d117 bne.n 8006838 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8006808: 2301 movs r3, #1 regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800680a: 6d84 ldr r4, [r0, #88] @ 0x58 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800680c: e9d0 1517 ldrd r1, r5, [r0, #92] @ 0x5c hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8006810: 682a ldr r2, [r5, #0] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8006812: f001 011f and.w r1, r1, #31 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8006816: f422 7280 bic.w r2, r2, #256 @ 0x100 regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800681a: 408b lsls r3, r1 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800681c: 602a str r2, [r5, #0] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800681e: 6063 str r3, [r4, #4] if(hdma->DMAmuxRequestGen != 0U) 8006820: 6ec3 ldr r3, [r0, #108] @ 0x6c hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8006822: e9d0 2119 ldrd r2, r1, [r0, #100] @ 0x64 8006826: 6051 str r1, [r2, #4] if(hdma->DMAmuxRequestGen != 0U) 8006828: b133 cbz r3, 8006838 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 800682a: 681a ldr r2, [r3, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800682c: e9d0 141c ldrd r1, r4, [r0, #112] @ 0x70 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8006830: f422 7280 bic.w r2, r2, #256 @ 0x100 8006834: 601a str r2, [r3, #0] hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8006836: 604c str r4, [r1, #4] hdma->State = HAL_DMA_STATE_READY; 8006838: 2101 movs r1, #1 __HAL_UNLOCK(hdma); 800683a: 2200 movs r2, #0 if(hdma->XferAbortCallback != NULL) 800683c: 6d03 ldr r3, [r0, #80] @ 0x50 hdma->State = HAL_DMA_STATE_READY; 800683e: f880 1035 strb.w r1, [r0, #53] @ 0x35 __HAL_UNLOCK(hdma); 8006842: f880 2034 strb.w r2, [r0, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8006846: b163 cbz r3, 8006862 hdma->XferAbortCallback(hdma); 8006848: 4798 blx r3 800684a: e00a b.n 8006862 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800684c: 2380 movs r3, #128 @ 0x80 800684e: 6543 str r3, [r0, #84] @ 0x54 return HAL_ERROR; 8006850: 2001 movs r0, #1 } 8006852: bd38 pop {r3, r4, r5, pc} hdma->State = HAL_DMA_STATE_ABORT; 8006854: 2204 movs r2, #4 8006856: f880 2035 strb.w r2, [r0, #53] @ 0x35 __HAL_DMA_DISABLE(hdma); 800685a: 681a ldr r2, [r3, #0] 800685c: f022 0201 bic.w r2, r2, #1 8006860: 601a str r2, [r3, #0] return HAL_OK; 8006862: 2000 movs r0, #0 } 8006864: bd38 pop {r3, r4, r5, pc} return HAL_ERROR; 8006866: 2001 movs r0, #1 } 8006868: 4770 bx lr 800686a: bf00 nop 800686c: 40020010 .word 0x40020010 8006870: 5802541c .word 0x5802541c 8006874: 58025408 .word 0x58025408 8006878: 58025430 .word 0x58025430 800687c: 58025480 .word 0x58025480 8006880: 58025494 .word 0x58025494 08006884 : { 8006884: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} __IO uint32_t count = 0U; 8006888: 2200 movs r2, #0 uint32_t timeout = SystemCoreClock / 9600U; 800688a: 4b46 ldr r3, [pc, #280] @ (80069a4 ) { 800688c: b082 sub sp, #8 DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800688e: 6d84 ldr r4, [r0, #88] @ 0x58 { 8006890: 4606 mov r6, r0 uint32_t timeout = SystemCoreClock / 9600U; 8006892: 681d ldr r5, [r3, #0] __IO uint32_t count = 0U; 8006894: 9201 str r2, [sp, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8006896: 6803 ldr r3, [r0, #0] 8006898: 4a43 ldr r2, [pc, #268] @ (80069a8 ) 800689a: 4844 ldr r0, [pc, #272] @ (80069ac ) tmpisr_dma = regs_dma->ISR; 800689c: 6827 ldr r7, [r4, #0] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800689e: 4293 cmp r3, r2 80068a0: bf18 it ne 80068a2: 4283 cmpne r3, r0 tmpisr_bdma = regs_bdma->ISR; 80068a4: 6821 ldr r1, [r4, #0] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80068a6: bf0c ite eq 80068a8: 2001 moveq r0, #1 80068aa: 2000 movne r0, #0 80068ac: f000 8086 beq.w 80069bc 80068b0: 3218 adds r2, #24 80068b2: 4293 cmp r3, r2 80068b4: f000 827c beq.w 8006db0 80068b8: 3218 adds r2, #24 80068ba: 4293 cmp r3, r2 80068bc: f000 8278 beq.w 8006db0 80068c0: 3218 adds r2, #24 80068c2: 4293 cmp r3, r2 80068c4: f000 8285 beq.w 8006dd2 80068c8: 3218 adds r2, #24 80068ca: 4293 cmp r3, r2 80068cc: f000 8281 beq.w 8006dd2 80068d0: 3218 adds r2, #24 80068d2: 4293 cmp r3, r2 80068d4: f000 827d beq.w 8006dd2 80068d8: 3218 adds r2, #24 80068da: 4293 cmp r3, r2 80068dc: f000 8279 beq.w 8006dd2 80068e0: f502 7256 add.w r2, r2, #856 @ 0x358 80068e4: 4293 cmp r3, r2 80068e6: f000 8274 beq.w 8006dd2 80068ea: 3218 adds r2, #24 80068ec: 4293 cmp r3, r2 80068ee: f000 8270 beq.w 8006dd2 80068f2: 3218 adds r2, #24 80068f4: 4293 cmp r3, r2 80068f6: f000 826c beq.w 8006dd2 80068fa: 3218 adds r2, #24 80068fc: 4293 cmp r3, r2 80068fe: f000 8268 beq.w 8006dd2 8006902: 3218 adds r2, #24 8006904: 4293 cmp r3, r2 8006906: f000 8264 beq.w 8006dd2 800690a: 3218 adds r2, #24 800690c: 4293 cmp r3, r2 800690e: f000 8260 beq.w 8006dd2 8006912: 3218 adds r2, #24 8006914: 4293 cmp r3, r2 8006916: f000 825c beq.w 8006dd2 800691a: 3218 adds r2, #24 800691c: 4293 cmp r3, r2 800691e: f000 8258 beq.w 8006dd2 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8006922: 4a23 ldr r2, [pc, #140] @ (80069b0 ) 8006924: 4823 ldr r0, [pc, #140] @ (80069b4 ) 8006926: 4283 cmp r3, r0 8006928: bf18 it ne 800692a: 4293 cmpne r3, r2 800692c: f100 0014 add.w r0, r0, #20 8006930: bf0c ite eq 8006932: 2201 moveq r2, #1 8006934: 2200 movne r2, #0 8006936: 4283 cmp r3, r0 8006938: bf08 it eq 800693a: f042 0201 orreq.w r2, r2, #1 800693e: 3014 adds r0, #20 8006940: 4283 cmp r3, r0 8006942: bf08 it eq 8006944: f042 0201 orreq.w r2, r2, #1 8006948: 3014 adds r0, #20 800694a: 4283 cmp r3, r0 800694c: bf08 it eq 800694e: f042 0201 orreq.w r2, r2, #1 8006952: 3014 adds r0, #20 8006954: 4283 cmp r3, r0 8006956: bf08 it eq 8006958: f042 0201 orreq.w r2, r2, #1 800695c: 3014 adds r0, #20 800695e: 4283 cmp r3, r0 8006960: bf08 it eq 8006962: f042 0201 orreq.w r2, r2, #1 8006966: b912 cbnz r2, 800696e 8006968: 4a13 ldr r2, [pc, #76] @ (80069b8 ) 800696a: 4293 cmp r3, r2 800696c: d116 bne.n 800699c if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 800696e: 6df0 ldr r0, [r6, #92] @ 0x5c 8006970: 2504 movs r5, #4 ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 8006972: 681a ldr r2, [r3, #0] if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 8006974: f000 001f and.w r0, r0, #31 8006978: 4085 lsls r5, r0 800697a: 420d tst r5, r1 800697c: f000 8283 beq.w 8006e86 8006980: 0757 lsls r7, r2, #29 8006982: f140 8280 bpl.w 8006e86 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8006986: 0410 lsls r0, r2, #16 regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 8006988: 6065 str r5, [r4, #4] if((ccr_reg & BDMA_CCR_DBM) != 0U) 800698a: f140 82af bpl.w 8006eec if((ccr_reg & BDMA_CCR_CT) == 0U) 800698e: 03d1 lsls r1, r2, #15 8006990: f100 82b2 bmi.w 8006ef8 if(hdma->XferM1HalfCpltCallback != NULL) 8006994: 6cb3 ldr r3, [r6, #72] @ 0x48 8006996: 2b00 cmp r3, #0 8006998: f040 81f4 bne.w 8006d84 } 800699c: b002 add sp, #8 800699e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80069a2: bf00 nop 80069a4: 24000038 .word 0x24000038 80069a8: 40020028 .word 0x40020028 80069ac: 40020010 .word 0x40020010 80069b0: 58025408 .word 0x58025408 80069b4: 5802541c .word 0x5802541c 80069b8: 58025494 .word 0x58025494 if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80069bc: f8d6 e05c ldr.w lr, [r6, #92] @ 0x5c 80069c0: f04f 0c08 mov.w ip, #8 80069c4: f00e 021f and.w r2, lr, #31 80069c8: fa0c f102 lsl.w r1, ip, r2 80069cc: 420f tst r7, r1 80069ce: f000 81de beq.w 8006d8e if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 80069d2: f8d3 c000 ldr.w ip, [r3] 80069d6: f01c 0f04 tst.w ip, #4 80069da: d00a beq.n 80069f2 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 80069dc: f8d3 c000 ldr.w ip, [r3] 80069e0: f02c 0c04 bic.w ip, ip, #4 80069e4: f8c3 c000 str.w ip, [r3] regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 80069e8: 60a1 str r1, [r4, #8] hdma->ErrorCode |= HAL_DMA_ERROR_TE; 80069ea: 6d71 ldr r1, [r6, #84] @ 0x54 80069ec: f041 0101 orr.w r1, r1, #1 80069f0: 6571 str r1, [r6, #84] @ 0x54 if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80069f2: fa27 f102 lsr.w r1, r7, r2 80069f6: 07c9 lsls r1, r1, #31 80069f8: d55b bpl.n 8006ab2 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 80069fa: 2800 cmp r0, #0 80069fc: d14f bne.n 8006a9e 80069fe: 49a2 ldr r1, [pc, #648] @ (8006c88 ) 8006a00: f8df c298 ldr.w ip, [pc, #664] @ 8006c9c 8006a04: 4563 cmp r3, ip 8006a06: bf18 it ne 8006a08: 428b cmpne r3, r1 8006a0a: f10c 0c18 add.w ip, ip, #24 8006a0e: bf0c ite eq 8006a10: 2101 moveq r1, #1 8006a12: 2100 movne r1, #0 8006a14: 4563 cmp r3, ip 8006a16: bf08 it eq 8006a18: f041 0101 orreq.w r1, r1, #1 8006a1c: f10c 0c18 add.w ip, ip, #24 8006a20: 4563 cmp r3, ip 8006a22: bf08 it eq 8006a24: f041 0101 orreq.w r1, r1, #1 8006a28: f10c 0c18 add.w ip, ip, #24 8006a2c: 4563 cmp r3, ip 8006a2e: bf08 it eq 8006a30: f041 0101 orreq.w r1, r1, #1 8006a34: f10c 0c18 add.w ip, ip, #24 8006a38: 4563 cmp r3, ip 8006a3a: bf08 it eq 8006a3c: f041 0101 orreq.w r1, r1, #1 8006a40: f50c 7c56 add.w ip, ip, #856 @ 0x358 8006a44: 4563 cmp r3, ip 8006a46: bf08 it eq 8006a48: f041 0101 orreq.w r1, r1, #1 8006a4c: f10c 0c18 add.w ip, ip, #24 8006a50: 4563 cmp r3, ip 8006a52: bf08 it eq 8006a54: f041 0101 orreq.w r1, r1, #1 8006a58: f10c 0c18 add.w ip, ip, #24 8006a5c: 4563 cmp r3, ip 8006a5e: bf08 it eq 8006a60: f041 0101 orreq.w r1, r1, #1 8006a64: f10c 0c18 add.w ip, ip, #24 8006a68: 4563 cmp r3, ip 8006a6a: bf08 it eq 8006a6c: f041 0101 orreq.w r1, r1, #1 8006a70: f10c 0c18 add.w ip, ip, #24 8006a74: 4563 cmp r3, ip 8006a76: bf08 it eq 8006a78: f041 0101 orreq.w r1, r1, #1 8006a7c: f10c 0c18 add.w ip, ip, #24 8006a80: 4563 cmp r3, ip 8006a82: bf08 it eq 8006a84: f041 0101 orreq.w r1, r1, #1 8006a88: f10c 0c18 add.w ip, ip, #24 8006a8c: 4563 cmp r3, ip 8006a8e: bf08 it eq 8006a90: f041 0101 orreq.w r1, r1, #1 8006a94: b919 cbnz r1, 8006a9e 8006a96: 497d ldr r1, [pc, #500] @ (8006c8c ) 8006a98: 428b cmp r3, r1 8006a9a: f040 81e3 bne.w 8006e64 8006a9e: 6959 ldr r1, [r3, #20] 8006aa0: 0609 lsls r1, r1, #24 8006aa2: d506 bpl.n 8006ab2 regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8006aa4: 2101 movs r1, #1 8006aa6: 4091 lsls r1, r2 8006aa8: 60a1 str r1, [r4, #8] hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8006aaa: 6d71 ldr r1, [r6, #84] @ 0x54 8006aac: f041 0102 orr.w r1, r1, #2 8006ab0: 6571 str r1, [r6, #84] @ 0x54 if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006ab2: 2104 movs r1, #4 8006ab4: 4091 lsls r1, r2 8006ab6: 4239 tst r1, r7 8006ab8: d05f beq.n 8006b7a if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8006aba: f8df c1cc ldr.w ip, [pc, #460] @ 8006c88 8006abe: 4563 cmp r3, ip 8006ac0: d051 beq.n 8006b66 8006ac2: 2800 cmp r0, #0 8006ac4: d14f bne.n 8006b66 8006ac6: f10c 0c30 add.w ip, ip, #48 @ 0x30 8006aca: f8df 81d0 ldr.w r8, [pc, #464] @ 8006c9c 8006ace: 4543 cmp r3, r8 8006ad0: bf18 it ne 8006ad2: 4563 cmpne r3, ip 8006ad4: f108 0830 add.w r8, r8, #48 @ 0x30 8006ad8: bf0c ite eq 8006ada: f04f 0c01 moveq.w ip, #1 8006ade: f04f 0c00 movne.w ip, #0 8006ae2: 4543 cmp r3, r8 8006ae4: bf08 it eq 8006ae6: f04c 0c01 orreq.w ip, ip, #1 8006aea: f108 0818 add.w r8, r8, #24 8006aee: 4543 cmp r3, r8 8006af0: bf08 it eq 8006af2: f04c 0c01 orreq.w ip, ip, #1 8006af6: f108 0818 add.w r8, r8, #24 8006afa: 4543 cmp r3, r8 8006afc: bf08 it eq 8006afe: f04c 0c01 orreq.w ip, ip, #1 8006b02: f508 7856 add.w r8, r8, #856 @ 0x358 8006b06: 4543 cmp r3, r8 8006b08: bf08 it eq 8006b0a: f04c 0c01 orreq.w ip, ip, #1 8006b0e: f108 0818 add.w r8, r8, #24 8006b12: 4543 cmp r3, r8 8006b14: bf08 it eq 8006b16: f04c 0c01 orreq.w ip, ip, #1 8006b1a: f108 0818 add.w r8, r8, #24 8006b1e: 4543 cmp r3, r8 8006b20: bf08 it eq 8006b22: f04c 0c01 orreq.w ip, ip, #1 8006b26: f108 0818 add.w r8, r8, #24 8006b2a: 4543 cmp r3, r8 8006b2c: bf08 it eq 8006b2e: f04c 0c01 orreq.w ip, ip, #1 8006b32: f108 0818 add.w r8, r8, #24 8006b36: 4543 cmp r3, r8 8006b38: bf08 it eq 8006b3a: f04c 0c01 orreq.w ip, ip, #1 8006b3e: f108 0818 add.w r8, r8, #24 8006b42: 4543 cmp r3, r8 8006b44: bf08 it eq 8006b46: f04c 0c01 orreq.w ip, ip, #1 8006b4a: f108 0818 add.w r8, r8, #24 8006b4e: 4543 cmp r3, r8 8006b50: bf08 it eq 8006b52: f04c 0c01 orreq.w ip, ip, #1 8006b56: f1bc 0f00 cmp.w ip, #0 8006b5a: d104 bne.n 8006b66 8006b5c: f8df c12c ldr.w ip, [pc, #300] @ 8006c8c 8006b60: 4563 cmp r3, ip 8006b62: f040 8185 bne.w 8006e70 8006b66: f8d3 c000 ldr.w ip, [r3] 8006b6a: f01c 0f02 tst.w ip, #2 8006b6e: d004 beq.n 8006b7a regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8006b70: 60a1 str r1, [r4, #8] hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8006b72: 6d71 ldr r1, [r6, #84] @ 0x54 8006b74: f041 0104 orr.w r1, r1, #4 8006b78: 6571 str r1, [r6, #84] @ 0x54 if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006b7a: 2110 movs r1, #16 8006b7c: fa01 f202 lsl.w r2, r1, r2 8006b80: 423a tst r2, r7 8006b82: d05b beq.n 8006c3c if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8006b84: 4940 ldr r1, [pc, #256] @ (8006c88 ) 8006b86: 428b cmp r3, r1 8006b88: d042 beq.n 8006c10 8006b8a: 2800 cmp r0, #0 8006b8c: d140 bne.n 8006c10 8006b8e: 3118 adds r1, #24 8006b90: 483f ldr r0, [pc, #252] @ (8006c90 ) 8006b92: 4283 cmp r3, r0 8006b94: bf18 it ne 8006b96: 428b cmpne r3, r1 8006b98: f100 0018 add.w r0, r0, #24 8006b9c: bf0c ite eq 8006b9e: 2101 moveq r1, #1 8006ba0: 2100 movne r1, #0 8006ba2: 4283 cmp r3, r0 8006ba4: bf08 it eq 8006ba6: f041 0101 orreq.w r1, r1, #1 8006baa: 3018 adds r0, #24 8006bac: 4283 cmp r3, r0 8006bae: bf08 it eq 8006bb0: f041 0101 orreq.w r1, r1, #1 8006bb4: 3018 adds r0, #24 8006bb6: 4283 cmp r3, r0 8006bb8: bf08 it eq 8006bba: f041 0101 orreq.w r1, r1, #1 8006bbe: f500 7056 add.w r0, r0, #856 @ 0x358 8006bc2: 4283 cmp r3, r0 8006bc4: bf08 it eq 8006bc6: f041 0101 orreq.w r1, r1, #1 8006bca: 3018 adds r0, #24 8006bcc: 4283 cmp r3, r0 8006bce: bf08 it eq 8006bd0: f041 0101 orreq.w r1, r1, #1 8006bd4: 3018 adds r0, #24 8006bd6: 4283 cmp r3, r0 8006bd8: bf08 it eq 8006bda: f041 0101 orreq.w r1, r1, #1 8006bde: 3018 adds r0, #24 8006be0: 4283 cmp r3, r0 8006be2: bf08 it eq 8006be4: f041 0101 orreq.w r1, r1, #1 8006be8: 3018 adds r0, #24 8006bea: 4283 cmp r3, r0 8006bec: bf08 it eq 8006bee: f041 0101 orreq.w r1, r1, #1 8006bf2: 3018 adds r0, #24 8006bf4: 4283 cmp r3, r0 8006bf6: bf08 it eq 8006bf8: f041 0101 orreq.w r1, r1, #1 8006bfc: 3018 adds r0, #24 8006bfe: 4283 cmp r3, r0 8006c00: bf08 it eq 8006c02: f041 0101 orreq.w r1, r1, #1 8006c06: b919 cbnz r1, 8006c10 8006c08: 4920 ldr r1, [pc, #128] @ (8006c8c ) 8006c0a: 428b cmp r3, r1 8006c0c: f040 8137 bne.w 8006e7e 8006c10: 6819 ldr r1, [r3, #0] 8006c12: f3c1 01c0 ubfx r1, r1, #3, #1 8006c16: b189 cbz r1, 8006c3c regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 8006c18: 60a2 str r2, [r4, #8] if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8006c1a: 681a ldr r2, [r3, #0] 8006c1c: 0350 lsls r0, r2, #13 8006c1e: f100 80e7 bmi.w 8006df0 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8006c22: 681a ldr r2, [r3, #0] 8006c24: 05d2 lsls r2, r2, #23 8006c26: d403 bmi.n 8006c30 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8006c28: 681a ldr r2, [r3, #0] 8006c2a: f022 0208 bic.w r2, r2, #8 8006c2e: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8006c30: 6c33 ldr r3, [r6, #64] @ 0x40 8006c32: b11b cbz r3, 8006c3c hdma->XferHalfCpltCallback(hdma); 8006c34: 4630 mov r0, r6 8006c36: 4798 blx r3 8006c38: f8d6 e05c ldr.w lr, [r6, #92] @ 0x5c if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006c3c: f00e 011f and.w r1, lr, #31 8006c40: 2020 movs r0, #32 8006c42: 4088 lsls r0, r1 8006c44: 4238 tst r0, r7 8006c46: d073 beq.n 8006d30 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 8006c48: 6832 ldr r2, [r6, #0] 8006c4a: 4b12 ldr r3, [pc, #72] @ (8006c94 ) 8006c4c: 4f12 ldr r7, [pc, #72] @ (8006c98 ) 8006c4e: 42ba cmp r2, r7 8006c50: bf18 it ne 8006c52: 429a cmpne r2, r3 8006c54: f107 0718 add.w r7, r7, #24 8006c58: bf0c ite eq 8006c5a: 2301 moveq r3, #1 8006c5c: 2300 movne r3, #0 8006c5e: 42ba cmp r2, r7 8006c60: bf08 it eq 8006c62: f043 0301 orreq.w r3, r3, #1 8006c66: 3718 adds r7, #24 8006c68: 42ba cmp r2, r7 8006c6a: bf08 it eq 8006c6c: f043 0301 orreq.w r3, r3, #1 8006c70: 3718 adds r7, #24 8006c72: 42ba cmp r2, r7 8006c74: bf08 it eq 8006c76: f043 0301 orreq.w r3, r3, #1 8006c7a: 3718 adds r7, #24 8006c7c: 42ba cmp r2, r7 8006c7e: bf08 it eq 8006c80: f043 0301 orreq.w r3, r3, #1 8006c84: 3718 adds r7, #24 8006c86: e00b b.n 8006ca0 8006c88: 40020040 .word 0x40020040 8006c8c: 400204b8 .word 0x400204b8 8006c90: 40020070 .word 0x40020070 8006c94: 40020010 .word 0x40020010 8006c98: 40020028 .word 0x40020028 8006c9c: 40020058 .word 0x40020058 8006ca0: 42ba cmp r2, r7 8006ca2: bf08 it eq 8006ca4: f043 0301 orreq.w r3, r3, #1 8006ca8: 3718 adds r7, #24 8006caa: 42ba cmp r2, r7 8006cac: bf08 it eq 8006cae: f043 0301 orreq.w r3, r3, #1 8006cb2: f507 7756 add.w r7, r7, #856 @ 0x358 8006cb6: 42ba cmp r2, r7 8006cb8: bf08 it eq 8006cba: f043 0301 orreq.w r3, r3, #1 8006cbe: 3718 adds r7, #24 8006cc0: 42ba cmp r2, r7 8006cc2: bf08 it eq 8006cc4: f043 0301 orreq.w r3, r3, #1 8006cc8: 3718 adds r7, #24 8006cca: 42ba cmp r2, r7 8006ccc: bf08 it eq 8006cce: f043 0301 orreq.w r3, r3, #1 8006cd2: 3718 adds r7, #24 8006cd4: 42ba cmp r2, r7 8006cd6: bf08 it eq 8006cd8: f043 0301 orreq.w r3, r3, #1 8006cdc: 3718 adds r7, #24 8006cde: 42ba cmp r2, r7 8006ce0: bf08 it eq 8006ce2: f043 0301 orreq.w r3, r3, #1 8006ce6: 3718 adds r7, #24 8006ce8: 42ba cmp r2, r7 8006cea: bf08 it eq 8006cec: f043 0301 orreq.w r3, r3, #1 8006cf0: 3718 adds r7, #24 8006cf2: 42ba cmp r2, r7 8006cf4: bf08 it eq 8006cf6: f043 0301 orreq.w r3, r3, #1 8006cfa: b91b cbnz r3, 8006d04 8006cfc: 4b89 ldr r3, [pc, #548] @ (8006f24 ) 8006cfe: 429a cmp r2, r3 8006d00: f040 80d1 bne.w 8006ea6 8006d04: 6813 ldr r3, [r2, #0] 8006d06: f3c3 1300 ubfx r3, r3, #4, #1 8006d0a: b18b cbz r3, 8006d30 regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 8006d0c: 60a0 str r0, [r4, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8006d0e: f896 3035 ldrb.w r3, [r6, #53] @ 0x35 8006d12: 2b04 cmp r3, #4 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8006d14: 6813 ldr r3, [r2, #0] if(HAL_DMA_STATE_ABORT == hdma->State) 8006d16: d074 beq.n 8006e02 if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8006d18: f413 2f80 tst.w r3, #262144 @ 0x40000 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8006d1c: 6813 ldr r3, [r2, #0] if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8006d1e: f000 808a beq.w 8006e36 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8006d22: 031f lsls r7, r3, #12 8006d24: f140 8095 bpl.w 8006e52 if(hdma->XferCpltCallback != NULL) 8006d28: 6bf3 ldr r3, [r6, #60] @ 0x3c 8006d2a: b10b cbz r3, 8006d30 hdma->XferCpltCallback(hdma); 8006d2c: 4630 mov r0, r6 8006d2e: 4798 blx r3 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 8006d30: 6d73 ldr r3, [r6, #84] @ 0x54 8006d32: 2b00 cmp r3, #0 8006d34: f43f ae32 beq.w 800699c if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 8006d38: 6d73 ldr r3, [r6, #84] @ 0x54 8006d3a: 07dc lsls r4, r3, #31 8006d3c: d51e bpl.n 8006d7c __HAL_DMA_DISABLE(hdma); 8006d3e: 6832 ldr r2, [r6, #0] hdma->State = HAL_DMA_STATE_ABORT; 8006d40: 2104 movs r1, #4 8006d42: f886 1035 strb.w r1, [r6, #53] @ 0x35 uint32_t timeout = SystemCoreClock / 9600U; 8006d46: 4978 ldr r1, [pc, #480] @ (8006f28 ) __HAL_DMA_DISABLE(hdma); 8006d48: 6813 ldr r3, [r2, #0] uint32_t timeout = SystemCoreClock / 9600U; 8006d4a: fba1 5105 umull r5, r1, r1, r5 __HAL_DMA_DISABLE(hdma); 8006d4e: f023 0301 bic.w r3, r3, #1 uint32_t timeout = SystemCoreClock / 9600U; 8006d52: 0a89 lsrs r1, r1, #10 __HAL_DMA_DISABLE(hdma); 8006d54: 6013 str r3, [r2, #0] 8006d56: e002 b.n 8006d5e while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 8006d58: 6813 ldr r3, [r2, #0] 8006d5a: 07d8 lsls r0, r3, #31 8006d5c: d504 bpl.n 8006d68 if (++count > timeout) 8006d5e: 9b01 ldr r3, [sp, #4] 8006d60: 3301 adds r3, #1 8006d62: 428b cmp r3, r1 8006d64: 9301 str r3, [sp, #4] 8006d66: d9f7 bls.n 8006d58 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8006d68: 6813 ldr r3, [r2, #0] 8006d6a: 07db lsls r3, r3, #31 hdma->State = HAL_DMA_STATE_ERROR; 8006d6c: bf4c ite mi 8006d6e: 2303 movmi r3, #3 hdma->State = HAL_DMA_STATE_READY; 8006d70: 2301 movpl r3, #1 8006d72: f886 3035 strb.w r3, [r6, #53] @ 0x35 __HAL_UNLOCK(hdma); 8006d76: 2300 movs r3, #0 8006d78: f886 3034 strb.w r3, [r6, #52] @ 0x34 if(hdma->XferErrorCallback != NULL) 8006d7c: 6cf3 ldr r3, [r6, #76] @ 0x4c 8006d7e: 2b00 cmp r3, #0 8006d80: f43f ae0c beq.w 800699c hdma->XferCpltCallback(hdma); 8006d84: 4630 mov r0, r6 } 8006d86: b002 add sp, #8 8006d88: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} hdma->XferCpltCallback(hdma); 8006d8c: 4718 bx r3 if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006d8e: fa27 f102 lsr.w r1, r7, r2 8006d92: 07c9 lsls r1, r1, #31 8006d94: f53f ae83 bmi.w 8006a9e if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006d98: 2104 movs r1, #4 8006d9a: 4091 lsls r1, r2 8006d9c: 420f tst r7, r1 8006d9e: f47f aee2 bne.w 8006b66 if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006da2: 2110 movs r1, #16 8006da4: fa01 f202 lsl.w r2, r1, r2 8006da8: 4217 tst r7, r2 8006daa: f47f af31 bne.w 8006c10 8006dae: e745 b.n 8006c3c if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006db0: f8d6 e05c ldr.w lr, [r6, #92] @ 0x5c 8006db4: f04f 0c08 mov.w ip, #8 8006db8: f00e 021f and.w r2, lr, #31 8006dbc: fa0c f102 lsl.w r1, ip, r2 8006dc0: 420f tst r7, r1 8006dc2: f47f ae06 bne.w 80069d2 if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006dc6: fa27 f102 lsr.w r1, r7, r2 8006dca: 07c9 lsls r1, r1, #31 8006dcc: f53f ae67 bmi.w 8006a9e 8006dd0: e66f b.n 8006ab2 if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006dd2: f8d6 e05c ldr.w lr, [r6, #92] @ 0x5c 8006dd6: 2108 movs r1, #8 8006dd8: f00e 021f and.w r2, lr, #31 8006ddc: 4091 lsls r1, r2 8006dde: 420f tst r7, r1 8006de0: f47f adf7 bne.w 80069d2 if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006de4: fa27 f102 lsr.w r1, r7, r2 8006de8: 07c9 lsls r1, r1, #31 8006dea: f53f ae58 bmi.w 8006a9e 8006dee: e660 b.n 8006ab2 if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8006df0: 681b ldr r3, [r3, #0] 8006df2: 0319 lsls r1, r3, #12 8006df4: f57f af1c bpl.w 8006c30 if(hdma->XferM1HalfCpltCallback != NULL) 8006df8: 6cb3 ldr r3, [r6, #72] @ 0x48 8006dfa: 2b00 cmp r3, #0 8006dfc: f47f af1a bne.w 8006c34 8006e00: e71c b.n 8006c3c ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 8006e02: f023 0316 bic.w r3, r3, #22 8006e06: 6013 str r3, [r2, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8006e08: 6953 ldr r3, [r2, #20] 8006e0a: f023 0380 bic.w r3, r3, #128 @ 0x80 8006e0e: 6153 str r3, [r2, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8006e10: 6c33 ldr r3, [r6, #64] @ 0x40 8006e12: b31b cbz r3, 8006e5c ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8006e14: 6813 ldr r3, [r2, #0] 8006e16: f023 0308 bic.w r3, r3, #8 8006e1a: 6013 str r3, [r2, #0] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8006e1c: 233f movs r3, #63 @ 0x3f hdma->State = HAL_DMA_STATE_READY; 8006e1e: 2001 movs r0, #1 __HAL_UNLOCK(hdma); 8006e20: 2200 movs r2, #0 regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8006e22: 408b lsls r3, r1 8006e24: 60a3 str r3, [r4, #8] if(hdma->XferAbortCallback != NULL) 8006e26: 6d33 ldr r3, [r6, #80] @ 0x50 hdma->State = HAL_DMA_STATE_READY; 8006e28: f886 0035 strb.w r0, [r6, #53] @ 0x35 __HAL_UNLOCK(hdma); 8006e2c: f886 2034 strb.w r2, [r6, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8006e30: 2b00 cmp r3, #0 8006e32: d1a7 bne.n 8006d84 8006e34: e5b2 b.n 800699c if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8006e36: f413 7380 ands.w r3, r3, #256 @ 0x100 8006e3a: f47f af75 bne.w 8006d28 ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 8006e3e: 6811 ldr r1, [r2, #0] 8006e40: f021 0110 bic.w r1, r1, #16 8006e44: 6011 str r1, [r2, #0] hdma->State = HAL_DMA_STATE_READY; 8006e46: 2201 movs r2, #1 __HAL_UNLOCK(hdma); 8006e48: f886 3034 strb.w r3, [r6, #52] @ 0x34 hdma->State = HAL_DMA_STATE_READY; 8006e4c: f886 2035 strb.w r2, [r6, #53] @ 0x35 __HAL_UNLOCK(hdma); 8006e50: e76a b.n 8006d28 if(hdma->XferM1CpltCallback != NULL) 8006e52: 6c73 ldr r3, [r6, #68] @ 0x44 8006e54: 2b00 cmp r3, #0 8006e56: f47f af69 bne.w 8006d2c 8006e5a: e769 b.n 8006d30 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 8006e5c: 6cb3 ldr r3, [r6, #72] @ 0x48 8006e5e: 2b00 cmp r3, #0 8006e60: d1d8 bne.n 8006e14 8006e62: e7db b.n 8006e1c if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8006e64: 6819 ldr r1, [r3, #0] if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006e66: 2104 movs r1, #4 8006e68: 4091 lsls r1, r2 8006e6a: 4239 tst r1, r7 8006e6c: f43f ae85 beq.w 8006b7a if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8006e70: 6819 ldr r1, [r3, #0] if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8006e72: 2110 movs r1, #16 8006e74: fa01 f202 lsl.w r2, r1, r2 8006e78: 4217 tst r7, r2 8006e7a: f43f aedf beq.w 8006c3c if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8006e7e: 6819 ldr r1, [r3, #0] 8006e80: f3c1 0180 ubfx r1, r1, #2, #1 8006e84: e6c7 b.n 8006c16 else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 8006e86: 2502 movs r5, #2 8006e88: 4085 lsls r5, r0 8006e8a: 420d tst r5, r1 8006e8c: d00f beq.n 8006eae 8006e8e: 0797 lsls r7, r2, #30 8006e90: d50d bpl.n 8006eae if((ccr_reg & BDMA_CCR_DBM) != 0U) 8006e92: 0411 lsls r1, r2, #16 regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 8006e94: 6065 str r5, [r4, #4] if((ccr_reg & BDMA_CCR_DBM) != 0U) 8006e96: d534 bpl.n 8006f02 if((ccr_reg & BDMA_CCR_CT) == 0U) 8006e98: 03d7 lsls r7, r2, #15 8006e9a: d43e bmi.n 8006f1a if(hdma->XferM1CpltCallback != NULL) 8006e9c: 6c73 ldr r3, [r6, #68] @ 0x44 8006e9e: 2b00 cmp r3, #0 8006ea0: f47f af70 bne.w 8006d84 8006ea4: e57a b.n 800699c if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 8006ea6: 6813 ldr r3, [r2, #0] 8006ea8: f3c3 0340 ubfx r3, r3, #1, #1 8006eac: e72d b.n 8006d0a else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 8006eae: 2508 movs r5, #8 8006eb0: 4085 lsls r5, r0 8006eb2: 420d tst r5, r1 8006eb4: f43f ad72 beq.w 800699c 8006eb8: 0715 lsls r5, r2, #28 8006eba: f57f ad6f bpl.w 800699c __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8006ebe: 681a ldr r2, [r3, #0] __HAL_UNLOCK(hdma); 8006ec0: 2100 movs r1, #0 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8006ec2: f022 020e bic.w r2, r2, #14 8006ec6: 601a str r2, [r3, #0] regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8006ec8: 2301 movs r3, #1 if (hdma->XferErrorCallback != NULL) 8006eca: 6cf2 ldr r2, [r6, #76] @ 0x4c regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8006ecc: fa03 f000 lsl.w r0, r3, r0 8006ed0: 6060 str r0, [r4, #4] hdma->ErrorCode = HAL_DMA_ERROR_TE; 8006ed2: 6573 str r3, [r6, #84] @ 0x54 __HAL_UNLOCK(hdma); 8006ed4: f886 1034 strb.w r1, [r6, #52] @ 0x34 hdma->State = HAL_DMA_STATE_READY; 8006ed8: f886 3035 strb.w r3, [r6, #53] @ 0x35 if (hdma->XferErrorCallback != NULL) 8006edc: 2a00 cmp r2, #0 8006ede: f43f ad5d beq.w 800699c hdma->XferErrorCallback(hdma); 8006ee2: 4630 mov r0, r6 } 8006ee4: b002 add sp, #8 8006ee6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} hdma->XferErrorCallback(hdma); 8006eea: 4710 bx r2 if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8006eec: 0692 lsls r2, r2, #26 8006eee: d403 bmi.n 8006ef8 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8006ef0: 681a ldr r2, [r3, #0] 8006ef2: f022 0204 bic.w r2, r2, #4 8006ef6: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8006ef8: 6c33 ldr r3, [r6, #64] @ 0x40 8006efa: 2b00 cmp r3, #0 8006efc: f47f af42 bne.w 8006d84 8006f00: e54c b.n 800699c if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8006f02: f012 0220 ands.w r2, r2, #32 8006f06: d108 bne.n 8006f1a __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8006f08: 6819 ldr r1, [r3, #0] hdma->State = HAL_DMA_STATE_READY; 8006f0a: 2001 movs r0, #1 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8006f0c: f021 010a bic.w r1, r1, #10 8006f10: 6019 str r1, [r3, #0] hdma->State = HAL_DMA_STATE_READY; 8006f12: f886 0035 strb.w r0, [r6, #53] @ 0x35 __HAL_UNLOCK(hdma); 8006f16: f886 2034 strb.w r2, [r6, #52] @ 0x34 if(hdma->XferCpltCallback != NULL) 8006f1a: 6bf3 ldr r3, [r6, #60] @ 0x3c 8006f1c: 2b00 cmp r3, #0 8006f1e: f47f af31 bne.w 8006d84 8006f22: e53b b.n 800699c 8006f24: 400204b8 .word 0x400204b8 8006f28: 1b4e81b5 .word 0x1b4e81b5 08006f2c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8006f2c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 8006f30: 680c ldr r4, [r1, #0] { 8006f32: b085 sub sp, #20 while (((GPIO_Init->Pin) >> position) != 0x00U) 8006f34: 2c00 cmp r4, #0 8006f36: f000 80a5 beq.w 8007084 uint32_t position = 0x00U; 8006f3a: 2300 movs r3, #0 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 8006f3c: f04f 0b01 mov.w fp, #1 temp &= ~(0x0FUL << (4U * (position & 0x03U))); temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2U] = temp; /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8006f40: f04f 4eb0 mov.w lr, #1476395008 @ 0x58000000 temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8006f44: 9100 str r1, [sp, #0] iocurrent = (GPIO_Init->Pin) & (1UL << position); 8006f46: fa0b fc03 lsl.w ip, fp, r3 if (iocurrent != 0x00U) 8006f4a: ea1c 0a04 ands.w sl, ip, r4 8006f4e: f000 8094 beq.w 800707a if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8006f52: 9900 ldr r1, [sp, #0] 8006f54: 005f lsls r7, r3, #1 8006f56: 684d ldr r5, [r1, #4] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8006f58: 2103 movs r1, #3 if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8006f5a: f005 0203 and.w r2, r5, #3 temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8006f5e: fa01 f607 lsl.w r6, r1, r7 if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8006f62: f102 38ff add.w r8, r2, #4294967295 @ 0xffffffff temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8006f66: 43f6 mvns r6, r6 if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 8006f68: f1b8 0f01 cmp.w r8, #1 8006f6c: f240 808d bls.w 800708a if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8006f70: 2a03 cmp r2, #3 8006f72: f040 80cb bne.w 800710c temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8006f76: 40ba lsls r2, r7 temp = GPIOx->MODER; 8006f78: 6807 ldr r7, [r0, #0] if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8006f7a: f415 3f40 tst.w r5, #196608 @ 0x30000 temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 8006f7e: ea06 0607 and.w r6, r6, r7 temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8006f82: ea42 0206 orr.w r2, r2, r6 GPIOx->MODER = temp; 8006f86: 6002 str r2, [r0, #0] if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8006f88: d077 beq.n 800707a __HAL_RCC_SYSCFG_CLK_ENABLE(); 8006f8a: 4e7f ldr r6, [pc, #508] @ (8007188 ) temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8006f8c: f003 0703 and.w r7, r3, #3 8006f90: 210f movs r1, #15 __HAL_RCC_SYSCFG_CLK_ENABLE(); 8006f92: f8d6 20f4 ldr.w r2, [r6, #244] @ 0xf4 temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8006f96: 00bf lsls r7, r7, #2 __HAL_RCC_SYSCFG_CLK_ENABLE(); 8006f98: f042 0202 orr.w r2, r2, #2 temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8006f9c: fa01 fc07 lsl.w ip, r1, r7 temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8006fa0: 497a ldr r1, [pc, #488] @ (800718c ) __HAL_RCC_SYSCFG_CLK_ENABLE(); 8006fa2: f8c6 20f4 str.w r2, [r6, #244] @ 0xf4 8006fa6: f8d6 20f4 ldr.w r2, [r6, #244] @ 0xf4 8006faa: f023 0603 bic.w r6, r3, #3 temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8006fae: 4288 cmp r0, r1 8006fb0: f106 46b0 add.w r6, r6, #1476395008 @ 0x58000000 __HAL_RCC_SYSCFG_CLK_ENABLE(); 8006fb4: f002 0202 and.w r2, r2, #2 8006fb8: f506 6680 add.w r6, r6, #1024 @ 0x400 8006fbc: 9203 str r2, [sp, #12] 8006fbe: 9a03 ldr r2, [sp, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8006fc0: 68b2 ldr r2, [r6, #8] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 8006fc2: ea22 020c bic.w r2, r2, ip temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8006fc6: d031 beq.n 800702c 8006fc8: f501 6180 add.w r1, r1, #1024 @ 0x400 8006fcc: 4288 cmp r0, r1 8006fce: f000 80b0 beq.w 8007132 8006fd2: 496f ldr r1, [pc, #444] @ (8007190 ) 8006fd4: 4288 cmp r0, r1 8006fd6: f000 80b2 beq.w 800713e 8006fda: f8df c1b8 ldr.w ip, [pc, #440] @ 8007194 8006fde: 4560 cmp r0, ip 8006fe0: f000 80a1 beq.w 8007126 8006fe4: f8df c1b0 ldr.w ip, [pc, #432] @ 8007198 8006fe8: 4560 cmp r0, ip 8006fea: f000 80b4 beq.w 8007156 8006fee: f8df c1ac ldr.w ip, [pc, #428] @ 800719c 8006ff2: 4560 cmp r0, ip 8006ff4: f000 80b5 beq.w 8007162 8006ff8: f8df c1a4 ldr.w ip, [pc, #420] @ 80071a0 8006ffc: 4560 cmp r0, ip 8006ffe: f000 80a4 beq.w 800714a 8007002: f8df c1a0 ldr.w ip, [pc, #416] @ 80071a4 8007006: 4560 cmp r0, ip 8007008: f000 80b1 beq.w 800716e 800700c: f8df c198 ldr.w ip, [pc, #408] @ 80071a8 8007010: 4560 cmp r0, ip 8007012: f000 80b2 beq.w 800717a 8007016: f8df c194 ldr.w ip, [pc, #404] @ 80071ac 800701a: 4560 cmp r0, ip 800701c: bf0c ite eq 800701e: f04f 0c09 moveq.w ip, #9 8007022: f04f 0c0a movne.w ip, #10 8007026: fa0c f707 lsl.w r7, ip, r7 800702a: 433a orrs r2, r7 SYSCFG->EXTICR[position >> 2U] = temp; 800702c: 60b2 str r2, [r6, #8] temp &= ~(iocurrent); if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800702e: 02ef lsls r7, r5, #11 temp = EXTI->RTSR1; 8007030: f8de 2000 ldr.w r2, [lr] temp &= ~(iocurrent); 8007034: ea6f 060a mvn.w r6, sl { temp |= iocurrent; 8007038: bf4c ite mi 800703a: ea4a 0202 orrmi.w r2, sl, r2 temp &= ~(iocurrent); 800703e: 4032 andpl r2, r6 } EXTI->RTSR1 = temp; temp = EXTI->FTSR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8007040: 02a9 lsls r1, r5, #10 EXTI->RTSR1 = temp; 8007042: f8ce 2000 str.w r2, [lr] temp = EXTI->FTSR1; 8007046: f8de 2004 ldr.w r2, [lr, #4] temp &= ~(iocurrent); 800704a: bf54 ite pl 800704c: 4032 andpl r2, r6 { temp |= iocurrent; 800704e: ea4a 0202 orrmi.w r2, sl, r2 } EXTI->FTSR1 = temp; temp = EXTI_CurrentCPU->EMR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8007052: 03af lsls r7, r5, #14 EXTI->FTSR1 = temp; 8007054: f8ce 2004 str.w r2, [lr, #4] temp = EXTI_CurrentCPU->EMR1; 8007058: f8de 2084 ldr.w r2, [lr, #132] @ 0x84 temp &= ~(iocurrent); 800705c: bf54 ite pl 800705e: 4032 andpl r2, r6 { temp |= iocurrent; 8007060: ea4a 0202 orrmi.w r2, sl, r2 EXTI_CurrentCPU->EMR1 = temp; /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; temp &= ~(iocurrent); if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8007064: 03e9 lsls r1, r5, #15 EXTI_CurrentCPU->EMR1 = temp; 8007066: f8ce 2084 str.w r2, [lr, #132] @ 0x84 temp = EXTI_CurrentCPU->IMR1; 800706a: f8de 2080 ldr.w r2, [lr, #128] @ 0x80 temp &= ~(iocurrent); 800706e: bf54 ite pl 8007070: 4032 andpl r2, r6 { temp |= iocurrent; 8007072: ea4a 0202 orrmi.w r2, sl, r2 } EXTI_CurrentCPU->IMR1 = temp; 8007076: f8ce 2080 str.w r2, [lr, #128] @ 0x80 } } position++; 800707a: 3301 adds r3, #1 while (((GPIO_Init->Pin) >> position) != 0x00U) 800707c: fa34 f203 lsrs.w r2, r4, r3 8007080: f47f af61 bne.w 8006f46 } } 8007084: b005 add sp, #20 8007086: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} temp |= (GPIO_Init->Speed << (position * 2U)); 800708a: 9900 ldr r1, [sp, #0] if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800708c: 2a02 cmp r2, #2 temp = GPIOx->OSPEEDR; 800708e: f8d0 9008 ldr.w r9, [r0, #8] temp |= (GPIO_Init->Speed << (position * 2U)); 8007092: 68c9 ldr r1, [r1, #12] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 8007094: ea09 0906 and.w r9, r9, r6 temp |= (GPIO_Init->Speed << (position * 2U)); 8007098: fa01 f807 lsl.w r8, r1, r7 temp |= ((GPIO_Init->Pull) << (position * 2U)); 800709c: 9900 ldr r1, [sp, #0] temp |= (GPIO_Init->Speed << (position * 2U)); 800709e: ea48 0809 orr.w r8, r8, r9 temp |= ((GPIO_Init->Pull) << (position * 2U)); 80070a2: 6889 ldr r1, [r1, #8] GPIOx->OSPEEDR = temp; 80070a4: f8c0 8008 str.w r8, [r0, #8] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80070a8: f3c5 1800 ubfx r8, r5, #4, #1 temp = GPIOx->OTYPER; 80070ac: f8d0 9004 ldr.w r9, [r0, #4] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80070b0: fa08 f803 lsl.w r8, r8, r3 temp &= ~(GPIO_OTYPER_OT0 << position) ; 80070b4: ea29 0c0c bic.w ip, r9, ip temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 80070b8: ea48 0c0c orr.w ip, r8, ip GPIOx->OTYPER = temp; 80070bc: f8c0 c004 str.w ip, [r0, #4] temp |= ((GPIO_Init->Pull) << (position * 2U)); 80070c0: fa01 fc07 lsl.w ip, r1, r7 temp = GPIOx->PUPDR; 80070c4: f8d0 800c ldr.w r8, [r0, #12] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 80070c8: ea08 0806 and.w r8, r8, r6 temp |= ((GPIO_Init->Pull) << (position * 2U)); 80070cc: ea4c 0c08 orr.w ip, ip, r8 GPIOx->PUPDR = temp; 80070d0: f8c0 c00c str.w ip, [r0, #12] if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 80070d4: f47f af4f bne.w 8006f76 temp &= ~(0xFU << ((position & 0x07U) * 4U)); 80070d8: f003 0c07 and.w ip, r3, #7 temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 80070dc: 9900 ldr r1, [sp, #0] temp = GPIOx->AFR[position >> 3U]; 80070de: ea4f 08d3 mov.w r8, r3, lsr #3 temp &= ~(0xFU << ((position & 0x07U) * 4U)); 80070e2: ea4f 0c8c mov.w ip, ip, lsl #2 temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 80070e6: 6909 ldr r1, [r1, #16] 80070e8: eb00 0888 add.w r8, r0, r8, lsl #2 80070ec: fa01 f10c lsl.w r1, r1, ip temp = GPIOx->AFR[position >> 3U]; 80070f0: f8d8 9020 ldr.w r9, [r8, #32] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 80070f4: 9101 str r1, [sp, #4] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 80070f6: 210f movs r1, #15 80070f8: fa01 fc0c lsl.w ip, r1, ip temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 80070fc: 9901 ldr r1, [sp, #4] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 80070fe: ea29 090c bic.w r9, r9, ip temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 8007102: ea41 0c09 orr.w ip, r1, r9 GPIOx->AFR[position >> 3U] = temp; 8007106: f8c8 c020 str.w ip, [r8, #32] 800710a: e734 b.n 8006f76 temp |= ((GPIO_Init->Pull) << (position * 2U)); 800710c: 9900 ldr r1, [sp, #0] temp = GPIOx->PUPDR; 800710e: f8d0 800c ldr.w r8, [r0, #12] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8007112: 6889 ldr r1, [r1, #8] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8007114: ea08 0806 and.w r8, r8, r6 temp |= ((GPIO_Init->Pull) << (position * 2U)); 8007118: fa01 fc07 lsl.w ip, r1, r7 800711c: ea4c 0c08 orr.w ip, ip, r8 GPIOx->PUPDR = temp; 8007120: f8c0 c00c str.w ip, [r0, #12] if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8007124: e727 b.n 8006f76 temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8007126: f04f 0c03 mov.w ip, #3 800712a: fa0c f707 lsl.w r7, ip, r7 800712e: 433a orrs r2, r7 8007130: e77c b.n 800702c 8007132: f04f 0c01 mov.w ip, #1 8007136: fa0c f707 lsl.w r7, ip, r7 800713a: 433a orrs r2, r7 800713c: e776 b.n 800702c 800713e: f04f 0c02 mov.w ip, #2 8007142: fa0c f707 lsl.w r7, ip, r7 8007146: 433a orrs r2, r7 8007148: e770 b.n 800702c 800714a: f04f 0c06 mov.w ip, #6 800714e: fa0c f707 lsl.w r7, ip, r7 8007152: 433a orrs r2, r7 8007154: e76a b.n 800702c 8007156: f04f 0c04 mov.w ip, #4 800715a: fa0c f707 lsl.w r7, ip, r7 800715e: 433a orrs r2, r7 8007160: e764 b.n 800702c 8007162: f04f 0c05 mov.w ip, #5 8007166: fa0c f707 lsl.w r7, ip, r7 800716a: 433a orrs r2, r7 800716c: e75e b.n 800702c 800716e: f04f 0c07 mov.w ip, #7 8007172: fa0c f707 lsl.w r7, ip, r7 8007176: 433a orrs r2, r7 8007178: e758 b.n 800702c 800717a: f04f 0c08 mov.w ip, #8 800717e: fa0c f707 lsl.w r7, ip, r7 8007182: 433a orrs r2, r7 8007184: e752 b.n 800702c 8007186: bf00 nop 8007188: 58024400 .word 0x58024400 800718c: 58020000 .word 0x58020000 8007190: 58020800 .word 0x58020800 8007194: 58020c00 .word 0x58020c00 8007198: 58021000 .word 0x58021000 800719c: 58021400 .word 0x58021400 80071a0: 58021800 .word 0x58021800 80071a4: 58021c00 .word 0x58021c00 80071a8: 58022000 .word 0x58022000 80071ac: 58022400 .word 0x58022400 080071b0 : GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 80071b0: 6903 ldr r3, [r0, #16] 80071b2: 4219 tst r1, r3 else { bitstatus = GPIO_PIN_RESET; } return bitstatus; } 80071b4: bf14 ite ne 80071b6: 2001 movne r0, #1 80071b8: 2000 moveq r0, #0 80071ba: 4770 bx lr 080071bc : { /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 80071bc: b902 cbnz r2, 80071c0 { GPIOx->BSRR = GPIO_Pin; } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 80071be: 0409 lsls r1, r1, #16 80071c0: 6181 str r1, [r0, #24] } } 80071c2: 4770 bx lr 080071c4 : /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 80071c4: 6943 ldr r3, [r0, #20] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 80071c6: ea01 0203 and.w r2, r1, r3 80071ca: ea21 0103 bic.w r1, r1, r3 80071ce: ea41 4102 orr.w r1, r1, r2, lsl #16 80071d2: 6181 str r1, [r0, #24] } 80071d4: 4770 bx lr 80071d6: bf00 nop 080071d8 : __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 80071d8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80071dc: f8d2 1088 ldr.w r1, [r2, #136] @ 0x88 80071e0: 4201 tst r1, r0 80071e2: d100 bne.n 80071e6 80071e4: 4770 bx lr { 80071e6: b508 push {r3, lr} { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 80071e8: f8c2 0088 str.w r0, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 80071ec: f7f9 faa0 bl 8000730 } #endif } 80071f0: bd08 pop {r3, pc} 80071f2: bf00 nop 080071f4 : HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) 80071f4: b328 cbz r0, 8007242 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; hiwdg->Instance->RLR = hiwdg->Init.Reload; 80071f6: 6882 ldr r2, [r0, #8] { 80071f8: b538 push {r3, r4, r5, lr} hiwdg->Instance->PR = hiwdg->Init.Prescaler; 80071fa: e9d0 3100 ldrd r3, r1, [r0] 80071fe: 4604 mov r4, r0 __HAL_IWDG_START(hiwdg); 8007200: f64c 40cc movw r0, #52428 @ 0xcccc 8007204: 6018 str r0, [r3, #0] IWDG_ENABLE_WRITE_ACCESS(hiwdg); 8007206: f245 5055 movw r0, #21845 @ 0x5555 800720a: 6018 str r0, [r3, #0] hiwdg->Instance->PR = hiwdg->Init.Prescaler; 800720c: 6059 str r1, [r3, #4] hiwdg->Instance->RLR = hiwdg->Init.Reload; 800720e: 609a str r2, [r3, #8] /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); 8007210: f7fc fede bl 8003fd0 /* Wait for register to be updated */ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 8007214: 6823 ldr r3, [r4, #0] tickstart = HAL_GetTick(); 8007216: 4605 mov r5, r0 while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 8007218: 68da ldr r2, [r3, #12] 800721a: 0751 lsls r1, r2, #29 800721c: d00a beq.n 8007234 { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) 800721e: f7fc fed7 bl 8003fd0 8007222: 1b40 subs r0, r0, r5 { if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 8007224: 6823 ldr r3, [r4, #0] if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) 8007226: 2831 cmp r0, #49 @ 0x31 8007228: d9f6 bls.n 8007218 if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800722a: 68da ldr r2, [r3, #12] 800722c: 0752 lsls r2, r2, #29 800722e: d0f3 beq.n 8007218 { return HAL_TIMEOUT; 8007230: 2003 movs r0, #3 __HAL_IWDG_RELOAD_COUNTER(hiwdg); } /* Return function status */ return HAL_OK; } 8007232: bd38 pop {r3, r4, r5, pc} if (hiwdg->Instance->WINR != hiwdg->Init.Window) 8007234: 6919 ldr r1, [r3, #16] 8007236: 68e2 ldr r2, [r4, #12] 8007238: 4291 cmp r1, r2 800723a: d004 beq.n 8007246 hiwdg->Instance->WINR = hiwdg->Init.Window; 800723c: 611a str r2, [r3, #16] return HAL_OK; 800723e: 2000 movs r0, #0 } 8007240: bd38 pop {r3, r4, r5, pc} return HAL_ERROR; 8007242: 2001 movs r0, #1 } 8007244: 4770 bx lr __HAL_IWDG_RELOAD_COUNTER(hiwdg); 8007246: f64a 22aa movw r2, #43690 @ 0xaaaa 800724a: 601a str r2, [r3, #0] 800724c: e7f7 b.n 800723e 800724e: bf00 nop 08007250 : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { 8007250: 4603 mov r3, r0 /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 8007252: f64a 22aa movw r2, #43690 @ 0xaaaa /* Return function status */ return HAL_OK; } 8007256: 2000 movs r0, #0 __HAL_IWDG_RELOAD_COUNTER(hiwdg); 8007258: 681b ldr r3, [r3, #0] 800725a: 601a str r2, [r3, #0] } 800725c: 4770 bx lr 800725e: bf00 nop 08007260 : * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 8007260: 2800 cmp r0, #0 8007262: d043 beq.n 80072ec /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 8007264: 4922 ldr r1, [pc, #136] @ (80072f0 ) /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 8007266: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800726a: 680a ldr r2, [r1, #0] { 800726c: b410 push {r4} MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800726e: f022 02e0 bic.w r2, r2, #224 @ 0xe0 8007272: 6804 ldr r4, [r0, #0] 8007274: 4322 orrs r2, r4 8007276: 600a str r2, [r1, #0] __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 8007278: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 800727c: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8007280: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 8007284: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007288: f422 3280 bic.w r2, r2, #65536 @ 0x10000 800728c: f8c3 2080 str.w r2, [r3, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 8007290: 681a ldr r2, [r3, #0] 8007292: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8007296: 601a str r2, [r3, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 8007298: 685a ldr r2, [r3, #4] 800729a: f422 3280 bic.w r2, r2, #65536 @ 0x10000 800729e: 605a str r2, [r3, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 80072a0: 6842 ldr r2, [r0, #4] 80072a2: 03d4 lsls r4, r2, #15 80072a4: d505 bpl.n 80072b2 { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 80072a6: f8d3 1080 ldr.w r1, [r3, #128] @ 0x80 80072aa: f441 3180 orr.w r1, r1, #65536 @ 0x10000 80072ae: f8c3 1080 str.w r1, [r3, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 80072b2: 0390 lsls r0, r2, #14 80072b4: d507 bpl.n 80072c6 { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 80072b6: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80072ba: f8d1 3084 ldr.w r3, [r1, #132] @ 0x84 80072be: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80072c2: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 80072c6: 07d1 lsls r1, r2, #31 80072c8: d505 bpl.n 80072d6 { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 80072ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80072ce: 680b ldr r3, [r1, #0] 80072d0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80072d4: 600b str r3, [r1, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 80072d6: 0793 lsls r3, r2, #30 80072d8: d505 bpl.n 80072e6 { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 80072da: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80072de: 6853 ldr r3, [r2, #4] 80072e0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80072e4: 6053 str r3, [r2, #4] } } 80072e6: f85d 4b04 ldr.w r4, [sp], #4 80072ea: 4770 bx lr 80072ec: 4770 bx lr 80072ee: bf00 nop 80072f0: 58024800 .word 0x58024800 080072f4 : * @retval None. */ void HAL_PWR_EnablePVD (void) { /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 80072f4: 4a02 ldr r2, [pc, #8] @ (8007300 ) 80072f6: 6813 ldr r3, [r2, #0] 80072f8: f043 0310 orr.w r3, r3, #16 80072fc: 6013 str r3, [r2, #0] } 80072fe: 4770 bx lr 8007300: 58024800 .word 0x58024800 08007304 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 8007304: b538 push {r3, r4, r5, lr} /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 8007306: 4c10 ldr r4, [pc, #64] @ (8007348 ) 8007308: 68e3 ldr r3, [r4, #12] 800730a: f013 0f04 tst.w r3, #4 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800730e: 68e3 ldr r3, [r4, #12] if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 8007310: d105 bne.n 800731e if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 8007312: f003 0307 and.w r3, r3, #7 8007316: 1a18 subs r0, r3, r0 8007318: bf18 it ne 800731a: 2001 movne r0, #1 } } #endif /* defined (SMPS) */ return HAL_OK; } 800731c: bd38 pop {r3, r4, r5, pc} MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800731e: f023 0307 bic.w r3, r3, #7 8007322: 4303 orrs r3, r0 8007324: 60e3 str r3, [r4, #12] tickstart = HAL_GetTick (); 8007326: f7fc fe53 bl 8003fd0 800732a: 4605 mov r5, r0 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800732c: e005 b.n 800733a if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800732e: f7fc fe4f bl 8003fd0 8007332: 1b40 subs r0, r0, r5 8007334: f5b0 7f7a cmp.w r0, #1000 @ 0x3e8 8007338: d804 bhi.n 8007344 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800733a: 6863 ldr r3, [r4, #4] 800733c: 049b lsls r3, r3, #18 800733e: d5f6 bpl.n 800732e return HAL_OK; 8007340: 2000 movs r0, #0 } 8007342: bd38 pop {r3, r4, r5, pc} return HAL_ERROR; 8007344: 2001 movs r0, #1 } 8007346: bd38 pop {r3, r4, r5, pc} 8007348: 58024800 .word 0x58024800 0800734c : /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800734c: 4921 ldr r1, [pc, #132] @ (80073d4 ) /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800734e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 8007352: 680a ldr r2, [r1, #0] { 8007354: b410 push {r4} MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 8007356: f422 22c0 bic.w r2, r2, #393216 @ 0x60000 800735a: 6804 ldr r4, [r0, #0] 800735c: 4322 orrs r2, r4 800735e: 600a str r2, [r1, #0] __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 8007360: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8007364: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8007368: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800736c: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8007370: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8007374: f8c3 2080 str.w r2, [r3, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 8007378: 681a ldr r2, [r3, #0] 800737a: f422 3280 bic.w r2, r2, #65536 @ 0x10000 800737e: 601a str r2, [r3, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 8007380: 685a ldr r2, [r3, #4] 8007382: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8007386: 605a str r2, [r3, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 8007388: 6842 ldr r2, [r0, #4] 800738a: 03d4 lsls r4, r2, #15 800738c: d505 bpl.n 800739a { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800738e: f8d3 1080 ldr.w r1, [r3, #128] @ 0x80 8007392: f441 3180 orr.w r1, r1, #65536 @ 0x10000 8007396: f8c3 1080 str.w r1, [r3, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800739a: 0390 lsls r0, r2, #14 800739c: d507 bpl.n 80073ae { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800739e: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80073a2: f8d1 3084 ldr.w r3, [r1, #132] @ 0x84 80073a6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80073aa: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 80073ae: 07d1 lsls r1, r2, #31 80073b0: d505 bpl.n 80073be { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 80073b2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80073b6: 680b ldr r3, [r1, #0] 80073b8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80073bc: 600b str r3, [r1, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 80073be: 0793 lsls r3, r2, #30 80073c0: d505 bpl.n 80073ce { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 80073c2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 80073c6: 6853 ldr r3, [r2, #4] 80073c8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80073cc: 6053 str r3, [r2, #4] } } 80073ce: f85d 4b04 ldr.w r4, [sp], #4 80073d2: 4770 bx lr 80073d4: 58024800 .word 0x58024800 080073d8 : * @retval None. */ void HAL_PWREx_EnableAVD (void) { /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 80073d8: 4a02 ldr r2, [pc, #8] @ (80073e4 ) 80073da: 6813 ldr r3, [r2, #0] 80073dc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80073e0: 6013 str r3, [r2, #0] } 80073e2: 4770 bx lr 80073e4: 58024800 .word 0x58024800 080073e8 : case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80073e8: 4b33 ldr r3, [pc, #204] @ (80074b8 ) uint32_t HAL_RCC_GetSysClockFreq(void) 80073ea: b430 push {r4, r5} pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80073ec: 6a9a ldr r2, [r3, #40] @ 0x28 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 80073ee: 6a9c ldr r4, [r3, #40] @ 0x28 pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 80073f0: 6add ldr r5, [r3, #44] @ 0x2c fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); if (pllm != 0U) 80073f2: f414 7f7c tst.w r4, #1008 @ 0x3f0 fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 80073f6: 6b59 ldr r1, [r3, #52] @ 0x34 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 80073f8: f3c4 1005 ubfx r0, r4, #4, #6 if (pllm != 0U) 80073fc: d036 beq.n 800746c fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 80073fe: f3c1 01cc ubfx r1, r1, #3, #13 pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 8007402: f005 0501 and.w r5, r5, #1 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8007406: f002 0203 and.w r2, r2, #3 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800740a: ee07 0a90 vmov s15, r0 fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800740e: fb05 f101 mul.w r1, r5, r1 8007412: 2a01 cmp r2, #1 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007414: eeb8 7ae7 vcvt.f32.s32 s14, s15 8007418: ee06 1a90 vmov s13, r1 800741c: eefa 6ae9 vcvt.f32.s32 s13, s13, #13 8007420: d002 beq.n 8007428 8007422: 2a02 cmp r2, #2 8007424: d042 beq.n 80074ac 8007426: b31a cbz r2, 8007470 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); break; default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007428: eddf 7a24 vldr s15, [pc, #144] @ 80074bc 800742c: ee87 6a87 vdiv.f32 s12, s15, s14 8007430: 6b1b ldr r3, [r3, #48] @ 0x30 8007432: f3c3 0308 ubfx r3, r3, #0, #9 8007436: ee07 3a90 vmov s15, r3 800743a: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 800743e: eef8 7ae7 vcvt.f32.s32 s15, s15 8007442: ee77 7aa5 vadd.f32 s15, s15, s11 8007446: ee77 7aa6 vadd.f32 s15, s15, s13 800744a: ee67 7a86 vmul.f32 s15, s15, s12 break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800744e: 4b1a ldr r3, [pc, #104] @ (80074b8 ) 8007450: 6b1b ldr r3, [r3, #48] @ 0x30 8007452: f3c3 2346 ubfx r3, r3, #9, #7 8007456: 3301 adds r3, #1 sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 8007458: ee07 3a10 vmov s14, r3 800745c: eef8 6ac7 vcvt.f32.s32 s13, s14 8007460: ee87 7aa6 vdiv.f32 s14, s15, s13 8007464: eefc 7ac7 vcvt.u32.f32 s15, s14 8007468: ee17 0a90 vmov r0, s15 sysclockfreq = CSI_VALUE; break; } return sysclockfreq; } 800746c: bc30 pop {r4, r5} 800746e: 4770 bx lr if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007470: 681a ldr r2, [r3, #0] 8007472: 0692 lsls r2, r2, #26 8007474: d51d bpl.n 80074b2 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007476: 6819 ldr r1, [r3, #0] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007478: eef7 7a00 vmov.f32 s15, #112 @ 0x3f800000 1.0 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800747c: 4a10 ldr r2, [pc, #64] @ (80074c0 ) pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800747e: 6b1b ldr r3, [r3, #48] @ 0x30 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007480: f3c1 01c1 ubfx r1, r1, #3, #2 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007484: f3c3 0308 ubfx r3, r3, #0, #9 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007488: 40ca lsrs r2, r1 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800748a: ee06 3a10 vmov s12, r3 800748e: ee05 2a90 vmov s11, r2 8007492: eeb8 6ac6 vcvt.f32.s32 s12, s12 8007496: eef8 5ae5 vcvt.f32.s32 s11, s11 800749a: ee36 6a27 vadd.f32 s12, s12, s15 800749e: eec5 7a87 vdiv.f32 s15, s11, s14 80074a2: ee36 7a26 vadd.f32 s14, s12, s13 80074a6: ee67 7a87 vmul.f32 s15, s15, s14 80074aa: e7d0 b.n 800744e pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80074ac: eddf 7a05 vldr s15, [pc, #20] @ 80074c4 80074b0: e7bc b.n 800742c pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80074b2: eddf 7a05 vldr s15, [pc, #20] @ 80074c8 80074b6: e7b9 b.n 800742c 80074b8: 58024400 .word 0x58024400 80074bc: 4a742400 .word 0x4a742400 80074c0: 03d09000 .word 0x03d09000 80074c4: 4bbebc20 .word 0x4bbebc20 80074c8: 4c742400 .word 0x4c742400 080074cc : if (RCC_OscInitStruct == NULL) 80074cc: 2800 cmp r0, #0 80074ce: f000 82e9 beq.w 8007aa4 { 80074d2: b5f8 push {r3, r4, r5, r6, r7, lr} if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 80074d4: 6803 ldr r3, [r0, #0] 80074d6: 4604 mov r4, r0 80074d8: 07d9 lsls r1, r3, #31 80074da: d52e bpl.n 800753a const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80074dc: 4997 ldr r1, [pc, #604] @ (800773c ) 80074de: 690a ldr r2, [r1, #16] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 80074e0: 6a89 ldr r1, [r1, #40] @ 0x28 const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80074e2: f002 0238 and.w r2, r2, #56 @ 0x38 if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 80074e6: 2a10 cmp r2, #16 80074e8: f000 80ee beq.w 80076c8 80074ec: 2a18 cmp r2, #24 80074ee: f000 80e6 beq.w 80076be __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80074f2: 6863 ldr r3, [r4, #4] 80074f4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80074f8: f000 8111 beq.w 800771e 80074fc: 2b00 cmp r3, #0 80074fe: f000 8167 beq.w 80077d0 8007502: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8007506: 4b8d ldr r3, [pc, #564] @ (800773c ) 8007508: 681a ldr r2, [r3, #0] 800750a: f000 828a beq.w 8007a22 800750e: f422 3280 bic.w r2, r2, #65536 @ 0x10000 8007512: 601a str r2, [r3, #0] 8007514: 681a ldr r2, [r3, #0] 8007516: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800751a: 601a str r2, [r3, #0] tickstart = HAL_GetTick(); 800751c: f7fc fd58 bl 8003fd0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8007520: 4e86 ldr r6, [pc, #536] @ (800773c ) tickstart = HAL_GetTick(); 8007522: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8007524: e005 b.n 8007532 if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8007526: f7fc fd53 bl 8003fd0 800752a: 1b40 subs r0, r0, r5 800752c: 2864 cmp r0, #100 @ 0x64 800752e: f200 814d bhi.w 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8007532: 6833 ldr r3, [r6, #0] 8007534: 039b lsls r3, r3, #14 8007536: d5f6 bpl.n 8007526 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8007538: 6823 ldr r3, [r4, #0] 800753a: 079d lsls r5, r3, #30 800753c: d470 bmi.n 8007620 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800753e: 06d9 lsls r1, r3, #27 8007540: d533 bpl.n 80075aa const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8007542: 4a7e ldr r2, [pc, #504] @ (800773c ) 8007544: 6913 ldr r3, [r2, #16] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8007546: 6a92 ldr r2, [r2, #40] @ 0x28 const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8007548: f003 0338 and.w r3, r3, #56 @ 0x38 if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800754c: 2b08 cmp r3, #8 800754e: f000 80cb beq.w 80076e8 8007552: 2b18 cmp r3, #24 8007554: f000 80c3 beq.w 80076de if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 8007558: 69e3 ldr r3, [r4, #28] __HAL_RCC_CSI_ENABLE(); 800755a: 4d78 ldr r5, [pc, #480] @ (800773c ) if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800755c: 2b00 cmp r3, #0 800755e: f000 816f beq.w 8007840 __HAL_RCC_CSI_ENABLE(); 8007562: 682b ldr r3, [r5, #0] 8007564: f043 0380 orr.w r3, r3, #128 @ 0x80 8007568: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 800756a: f7fc fd31 bl 8003fd0 800756e: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8007570: e005 b.n 800757e if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 8007572: f7fc fd2d bl 8003fd0 8007576: 1b80 subs r0, r0, r6 8007578: 2802 cmp r0, #2 800757a: f200 8127 bhi.w 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800757e: 682b ldr r3, [r5, #0] 8007580: 05db lsls r3, r3, #23 8007582: d5f6 bpl.n 8007572 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 8007584: f7fc fd2a bl 8003fdc 8007588: f241 0303 movw r3, #4099 @ 0x1003 800758c: 4298 cmp r0, r3 800758e: f200 8269 bhi.w 8007a64 8007592: 6a22 ldr r2, [r4, #32] 8007594: 686b ldr r3, [r5, #4] 8007596: 2a20 cmp r2, #32 8007598: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800759c: bf0c ite eq 800759e: f043 4380 orreq.w r3, r3, #1073741824 @ 0x40000000 80075a2: ea43 6382 orrne.w r3, r3, r2, lsl #26 80075a6: 606b str r3, [r5, #4] if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80075a8: 6823 ldr r3, [r4, #0] 80075aa: 071d lsls r5, r3, #28 80075ac: d516 bpl.n 80075dc if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 80075ae: 6963 ldr r3, [r4, #20] __HAL_RCC_LSI_ENABLE(); 80075b0: 4d62 ldr r5, [pc, #392] @ (800773c ) if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 80075b2: 2b00 cmp r3, #0 80075b4: f000 8122 beq.w 80077fc __HAL_RCC_LSI_ENABLE(); 80075b8: 6f6b ldr r3, [r5, #116] @ 0x74 80075ba: f043 0301 orr.w r3, r3, #1 80075be: 676b str r3, [r5, #116] @ 0x74 tickstart = HAL_GetTick(); 80075c0: f7fc fd06 bl 8003fd0 80075c4: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80075c6: e005 b.n 80075d4 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80075c8: f7fc fd02 bl 8003fd0 80075cc: 1b80 subs r0, r0, r6 80075ce: 2802 cmp r0, #2 80075d0: f200 80fc bhi.w 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80075d4: 6f6b ldr r3, [r5, #116] @ 0x74 80075d6: 0798 lsls r0, r3, #30 80075d8: d5f6 bpl.n 80075c8 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 80075da: 6823 ldr r3, [r4, #0] 80075dc: 069a lsls r2, r3, #26 80075de: d516 bpl.n 800760e if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 80075e0: 69a3 ldr r3, [r4, #24] __HAL_RCC_HSI48_ENABLE(); 80075e2: 4d56 ldr r5, [pc, #344] @ (800773c ) if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 80075e4: 2b00 cmp r3, #0 80075e6: f000 811a beq.w 800781e __HAL_RCC_HSI48_ENABLE(); 80075ea: 682b ldr r3, [r5, #0] 80075ec: f443 5380 orr.w r3, r3, #4096 @ 0x1000 80075f0: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 80075f2: f7fc fced bl 8003fd0 80075f6: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 80075f8: e005 b.n 8007606 if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 80075fa: f7fc fce9 bl 8003fd0 80075fe: 1b80 subs r0, r0, r6 8007600: 2802 cmp r0, #2 8007602: f200 80e3 bhi.w 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 8007606: 682b ldr r3, [r5, #0] 8007608: 049f lsls r7, r3, #18 800760a: d5f6 bpl.n 80075fa if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800760c: 6823 ldr r3, [r4, #0] 800760e: 0759 lsls r1, r3, #29 8007610: f100 808b bmi.w 800772a if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8007614: 6a63 ldr r3, [r4, #36] @ 0x24 8007616: 2b00 cmp r3, #0 8007618: f040 80bf bne.w 800779a return HAL_OK; 800761c: 2000 movs r0, #0 } 800761e: bdf8 pop {r3, r4, r5, r6, r7, pc} const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8007620: 4a46 ldr r2, [pc, #280] @ (800773c ) 8007622: 6913 ldr r3, [r2, #16] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8007624: 6a92 ldr r2, [r2, #40] @ 0x28 if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 8007626: f013 0338 ands.w r3, r3, #56 @ 0x38 800762a: d12d bne.n 8007688 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800762c: 4b43 ldr r3, [pc, #268] @ (800773c ) if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800762e: 68e2 ldr r2, [r4, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8007630: 681b ldr r3, [r3, #0] 8007632: 0759 lsls r1, r3, #29 8007634: d501 bpl.n 800763a 8007636: 2a00 cmp r2, #0 8007638: d04f beq.n 80076da __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800763a: 4d40 ldr r5, [pc, #256] @ (800773c ) 800763c: 682b ldr r3, [r5, #0] 800763e: f023 0319 bic.w r3, r3, #25 8007642: 4313 orrs r3, r2 8007644: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 8007646: f7fc fcc3 bl 8003fd0 800764a: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800764c: e005 b.n 800765a if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800764e: f7fc fcbf bl 8003fd0 8007652: 1b80 subs r0, r0, r6 8007654: 2802 cmp r0, #2 8007656: f200 80b9 bhi.w 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800765a: 682b ldr r3, [r5, #0] 800765c: 075b lsls r3, r3, #29 800765e: d5f6 bpl.n 800764e __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8007660: f7fc fcbc bl 8003fdc 8007664: f241 0303 movw r3, #4099 @ 0x1003 8007668: 4298 cmp r0, r3 800766a: f200 8110 bhi.w 800788e 800766e: 6922 ldr r2, [r4, #16] 8007670: 686b ldr r3, [r5, #4] 8007672: 2a40 cmp r2, #64 @ 0x40 8007674: f423 337c bic.w r3, r3, #258048 @ 0x3f000 8007678: bf0c ite eq 800767a: f443 3300 orreq.w r3, r3, #131072 @ 0x20000 800767e: ea43 3302 orrne.w r3, r3, r2, lsl #12 8007682: 606b str r3, [r5, #4] if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8007684: 6823 ldr r3, [r4, #0] 8007686: e75a b.n 800753e if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 8007688: 2b18 cmp r3, #24 800768a: f000 80fc beq.w 8007886 __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800768e: 4d2b ldr r5, [pc, #172] @ (800773c ) if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8007690: 68e2 ldr r2, [r4, #12] __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 8007692: 682b ldr r3, [r5, #0] if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8007694: 2a00 cmp r2, #0 8007696: f000 80e5 beq.w 8007864 __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800769a: f023 0319 bic.w r3, r3, #25 800769e: 4313 orrs r3, r2 80076a0: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 80076a2: f7fc fc95 bl 8003fd0 80076a6: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80076a8: e005 b.n 80076b6 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80076aa: f7fc fc91 bl 8003fd0 80076ae: 1b80 subs r0, r0, r6 80076b0: 2802 cmp r0, #2 80076b2: f200 808b bhi.w 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80076b6: 682b ldr r3, [r5, #0] 80076b8: 075f lsls r7, r3, #29 80076ba: d5f6 bpl.n 80076aa 80076bc: e7d0 b.n 8007660 if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 80076be: f001 0103 and.w r1, r1, #3 80076c2: 2902 cmp r1, #2 80076c4: f47f af15 bne.w 80074f2 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80076c8: 4a1c ldr r2, [pc, #112] @ (800773c ) 80076ca: 6812 ldr r2, [r2, #0] 80076cc: 0392 lsls r2, r2, #14 80076ce: f57f af34 bpl.w 800753a 80076d2: 6862 ldr r2, [r4, #4] 80076d4: 2a00 cmp r2, #0 80076d6: f47f af30 bne.w 800753a return HAL_ERROR; 80076da: 2001 movs r0, #1 } 80076dc: bdf8 pop {r3, r4, r5, r6, r7, pc} if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 80076de: f002 0203 and.w r2, r2, #3 80076e2: 2a01 cmp r2, #1 80076e4: f47f af38 bne.w 8007558 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80076e8: 4b14 ldr r3, [pc, #80] @ (800773c ) 80076ea: 681b ldr r3, [r3, #0] 80076ec: 05da lsls r2, r3, #23 80076ee: d502 bpl.n 80076f6 80076f0: 69e3 ldr r3, [r4, #28] 80076f2: 2b80 cmp r3, #128 @ 0x80 80076f4: d1f1 bne.n 80076da __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80076f6: f7fc fc71 bl 8003fdc 80076fa: f241 0303 movw r3, #4099 @ 0x1003 80076fe: 4298 cmp r0, r3 8007700: f200 80ce bhi.w 80078a0 8007704: 6a22 ldr r2, [r4, #32] 8007706: 2a20 cmp r2, #32 8007708: f000 81bb beq.w 8007a82 800770c: 490b ldr r1, [pc, #44] @ (800773c ) 800770e: 684b ldr r3, [r1, #4] 8007710: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 8007714: ea43 6382 orr.w r3, r3, r2, lsl #26 8007718: 604b str r3, [r1, #4] if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800771a: 6823 ldr r3, [r4, #0] 800771c: e745 b.n 80075aa __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800771e: 4a07 ldr r2, [pc, #28] @ (800773c ) 8007720: 6813 ldr r3, [r2, #0] 8007722: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007726: 6013 str r3, [r2, #0] if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8007728: e6f8 b.n 800751c PWR->CR1 |= PWR_CR1_DBP; 800772a: 4d05 ldr r5, [pc, #20] @ (8007740 ) 800772c: 682b ldr r3, [r5, #0] 800772e: f443 7380 orr.w r3, r3, #256 @ 0x100 8007732: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 8007734: f7fc fc4c bl 8003fd0 8007738: 4606 mov r6, r0 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800773a: e008 b.n 800774e 800773c: 58024400 .word 0x58024400 8007740: 58024800 .word 0x58024800 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8007744: f7fc fc44 bl 8003fd0 8007748: 1b80 subs r0, r0, r6 800774a: 2864 cmp r0, #100 @ 0x64 800774c: d83e bhi.n 80077cc while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800774e: 682b ldr r3, [r5, #0] 8007750: 05da lsls r2, r3, #23 8007752: d5f7 bpl.n 8007744 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8007754: 68a3 ldr r3, [r4, #8] 8007756: 2b01 cmp r3, #1 8007758: f000 818d beq.w 8007a76 800775c: 2b00 cmp r3, #0 800775e: f000 8168 beq.w 8007a32 8007762: 2b05 cmp r3, #5 8007764: 4b85 ldr r3, [pc, #532] @ (800797c ) 8007766: 6f1a ldr r2, [r3, #112] @ 0x70 8007768: f000 8194 beq.w 8007a94 800776c: f022 0201 bic.w r2, r2, #1 8007770: 671a str r2, [r3, #112] @ 0x70 8007772: 6f1a ldr r2, [r3, #112] @ 0x70 8007774: f022 0204 bic.w r2, r2, #4 8007778: 671a str r2, [r3, #112] @ 0x70 tickstart = HAL_GetTick(); 800777a: f7fc fc29 bl 8003fd0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800777e: 4e7f ldr r6, [pc, #508] @ (800797c ) if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007780: f241 3788 movw r7, #5000 @ 0x1388 tickstart = HAL_GetTick(); 8007784: 4605 mov r5, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8007786: e004 b.n 8007792 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007788: f7fc fc22 bl 8003fd0 800778c: 1b40 subs r0, r0, r5 800778e: 42b8 cmp r0, r7 8007790: d81c bhi.n 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8007792: 6f33 ldr r3, [r6, #112] @ 0x70 8007794: 079b lsls r3, r3, #30 8007796: d5f7 bpl.n 8007788 8007798: e73c b.n 8007614 if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800779a: 4d78 ldr r5, [pc, #480] @ (800797c ) 800779c: 692a ldr r2, [r5, #16] 800779e: f002 0238 and.w r2, r2, #56 @ 0x38 80077a2: 2a18 cmp r2, #24 80077a4: f000 80f0 beq.w 8007988 if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80077a8: 2b02 cmp r3, #2 __HAL_RCC_PLL_DISABLE(); 80077aa: 682b ldr r3, [r5, #0] 80077ac: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 80077b0: 602b str r3, [r5, #0] if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80077b2: d07f beq.n 80078b4 tickstart = HAL_GetTick(); 80077b4: f7fc fc0c bl 8003fd0 80077b8: 4604 mov r4, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80077ba: 682b ldr r3, [r5, #0] 80077bc: 019b lsls r3, r3, #6 80077be: f57f af2d bpl.w 800761c if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80077c2: f7fc fc05 bl 8003fd0 80077c6: 1b00 subs r0, r0, r4 80077c8: 2802 cmp r0, #2 80077ca: d9f6 bls.n 80077ba return HAL_TIMEOUT; 80077cc: 2003 movs r0, #3 } 80077ce: bdf8 pop {r3, r4, r5, r6, r7, pc} __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80077d0: 4d6a ldr r5, [pc, #424] @ (800797c ) 80077d2: 682b ldr r3, [r5, #0] 80077d4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80077d8: 602b str r3, [r5, #0] 80077da: 682b ldr r3, [r5, #0] 80077dc: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80077e0: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 80077e2: f7fc fbf5 bl 8003fd0 80077e6: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 80077e8: e004 b.n 80077f4 if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80077ea: f7fc fbf1 bl 8003fd0 80077ee: 1b80 subs r0, r0, r6 80077f0: 2864 cmp r0, #100 @ 0x64 80077f2: d8eb bhi.n 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 80077f4: 682b ldr r3, [r5, #0] 80077f6: 039f lsls r7, r3, #14 80077f8: d4f7 bmi.n 80077ea 80077fa: e69d b.n 8007538 __HAL_RCC_LSI_DISABLE(); 80077fc: 6f6b ldr r3, [r5, #116] @ 0x74 80077fe: f023 0301 bic.w r3, r3, #1 8007802: 676b str r3, [r5, #116] @ 0x74 tickstart = HAL_GetTick(); 8007804: f7fc fbe4 bl 8003fd0 8007808: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800780a: e004 b.n 8007816 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800780c: f7fc fbe0 bl 8003fd0 8007810: 1b80 subs r0, r0, r6 8007812: 2802 cmp r0, #2 8007814: d8da bhi.n 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8007816: 6f6b ldr r3, [r5, #116] @ 0x74 8007818: 0799 lsls r1, r3, #30 800781a: d4f7 bmi.n 800780c 800781c: e6dd b.n 80075da __HAL_RCC_HSI48_DISABLE(); 800781e: 682b ldr r3, [r5, #0] 8007820: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8007824: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 8007826: f7fc fbd3 bl 8003fd0 800782a: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800782c: e004 b.n 8007838 if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800782e: f7fc fbcf bl 8003fd0 8007832: 1b80 subs r0, r0, r6 8007834: 2802 cmp r0, #2 8007836: d8c9 bhi.n 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8007838: 682b ldr r3, [r5, #0] 800783a: 0498 lsls r0, r3, #18 800783c: d4f7 bmi.n 800782e 800783e: e6e5 b.n 800760c __HAL_RCC_CSI_DISABLE(); 8007840: 682b ldr r3, [r5, #0] 8007842: f023 0380 bic.w r3, r3, #128 @ 0x80 8007846: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 8007848: f7fc fbc2 bl 8003fd0 800784c: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800784e: e004 b.n 800785a if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 8007850: f7fc fbbe bl 8003fd0 8007854: 1b80 subs r0, r0, r6 8007856: 2802 cmp r0, #2 8007858: d8b8 bhi.n 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800785a: 682b ldr r3, [r5, #0] 800785c: 05df lsls r7, r3, #23 800785e: d4f7 bmi.n 8007850 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8007860: 6823 ldr r3, [r4, #0] 8007862: e6a2 b.n 80075aa __HAL_RCC_HSI_DISABLE(); 8007864: f023 0301 bic.w r3, r3, #1 8007868: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 800786a: f7fc fbb1 bl 8003fd0 800786e: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8007870: e004 b.n 800787c if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8007872: f7fc fbad bl 8003fd0 8007876: 1b80 subs r0, r0, r6 8007878: 2802 cmp r0, #2 800787a: d8a7 bhi.n 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800787c: 682b ldr r3, [r5, #0] 800787e: 0758 lsls r0, r3, #29 8007880: d4f7 bmi.n 8007872 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8007882: 6823 ldr r3, [r4, #0] 8007884: e65b b.n 800753e if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 8007886: 0790 lsls r0, r2, #30 8007888: f47f af01 bne.w 800768e 800788c: e6ce b.n 800762c __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800788e: 686b ldr r3, [r5, #4] 8007890: 6922 ldr r2, [r4, #16] 8007892: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000 8007896: ea43 6302 orr.w r3, r3, r2, lsl #24 800789a: 606b str r3, [r5, #4] if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800789c: 6823 ldr r3, [r4, #0] 800789e: e64e b.n 800753e __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80078a0: 4a36 ldr r2, [pc, #216] @ (800797c ) 80078a2: 6a21 ldr r1, [r4, #32] 80078a4: 68d3 ldr r3, [r2, #12] 80078a6: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000 80078aa: ea43 6301 orr.w r3, r3, r1, lsl #24 80078ae: 60d3 str r3, [r2, #12] if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80078b0: 6823 ldr r3, [r4, #0] 80078b2: e67a b.n 80075aa tickstart = HAL_GetTick(); 80078b4: f7fc fb8c bl 8003fd0 80078b8: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80078ba: e004 b.n 80078c6 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80078bc: f7fc fb88 bl 8003fd0 80078c0: 1b80 subs r0, r0, r6 80078c2: 2802 cmp r0, #2 80078c4: d882 bhi.n 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 80078c6: 682b ldr r3, [r5, #0] 80078c8: 0199 lsls r1, r3, #6 80078ca: d4f7 bmi.n 80078bc __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80078cc: 6aa9 ldr r1, [r5, #40] @ 0x28 80078ce: 4b2c ldr r3, [pc, #176] @ (8007980 ) 80078d0: 6aa2 ldr r2, [r4, #40] @ 0x28 80078d2: 400b ands r3, r1 __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 80078d4: 492b ldr r1, [pc, #172] @ (8007984 ) while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 80078d6: 4e29 ldr r6, [pc, #164] @ (800797c ) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 80078d8: 4313 orrs r3, r2 80078da: 6ae2 ldr r2, [r4, #44] @ 0x2c 80078dc: ea43 1302 orr.w r3, r3, r2, lsl #4 80078e0: 62ab str r3, [r5, #40] @ 0x28 80078e2: e9d4 320d ldrd r3, r2, [r4, #52] @ 0x34 80078e6: 3b01 subs r3, #1 80078e8: 3a01 subs r2, #1 80078ea: 025b lsls r3, r3, #9 80078ec: 0412 lsls r2, r2, #16 80078ee: b29b uxth r3, r3 80078f0: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000 80078f4: 4313 orrs r3, r2 80078f6: 6b22 ldr r2, [r4, #48] @ 0x30 80078f8: 3a01 subs r2, #1 80078fa: f3c2 0208 ubfx r2, r2, #0, #9 80078fe: 4313 orrs r3, r2 8007900: 6be2 ldr r2, [r4, #60] @ 0x3c 8007902: 3a01 subs r2, #1 8007904: 0612 lsls r2, r2, #24 8007906: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000 800790a: 4313 orrs r3, r2 800790c: 632b str r3, [r5, #48] @ 0x30 __HAL_RCC_PLLFRACN_DISABLE(); 800790e: 6aeb ldr r3, [r5, #44] @ 0x2c 8007910: f023 0301 bic.w r3, r3, #1 8007914: 62eb str r3, [r5, #44] @ 0x2c __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 8007916: 6b6a ldr r2, [r5, #52] @ 0x34 8007918: 6ca3 ldr r3, [r4, #72] @ 0x48 800791a: 4011 ands r1, r2 800791c: ea41 01c3 orr.w r1, r1, r3, lsl #3 8007920: 6369 str r1, [r5, #52] @ 0x34 __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 8007922: 6aeb ldr r3, [r5, #44] @ 0x2c 8007924: 6c22 ldr r2, [r4, #64] @ 0x40 8007926: f023 030c bic.w r3, r3, #12 800792a: 4313 orrs r3, r2 800792c: 62eb str r3, [r5, #44] @ 0x2c __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800792e: 6aeb ldr r3, [r5, #44] @ 0x2c 8007930: 6c62 ldr r2, [r4, #68] @ 0x44 8007932: f023 0302 bic.w r3, r3, #2 8007936: 4313 orrs r3, r2 8007938: 62eb str r3, [r5, #44] @ 0x2c __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800793a: 6aeb ldr r3, [r5, #44] @ 0x2c 800793c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007940: 62eb str r3, [r5, #44] @ 0x2c __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8007942: 6aeb ldr r3, [r5, #44] @ 0x2c 8007944: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8007948: 62eb str r3, [r5, #44] @ 0x2c __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800794a: 6aeb ldr r3, [r5, #44] @ 0x2c 800794c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8007950: 62eb str r3, [r5, #44] @ 0x2c __HAL_RCC_PLLFRACN_ENABLE(); 8007952: 6aeb ldr r3, [r5, #44] @ 0x2c 8007954: f043 0301 orr.w r3, r3, #1 8007958: 62eb str r3, [r5, #44] @ 0x2c __HAL_RCC_PLL_ENABLE(); 800795a: 682b ldr r3, [r5, #0] 800795c: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8007960: 602b str r3, [r5, #0] tickstart = HAL_GetTick(); 8007962: f7fc fb35 bl 8003fd0 8007966: 4604 mov r4, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8007968: 6833 ldr r3, [r6, #0] 800796a: 019a lsls r2, r3, #6 800796c: f53f ae56 bmi.w 800761c if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8007970: f7fc fb2e bl 8003fd0 8007974: 1b00 subs r0, r0, r4 8007976: 2802 cmp r0, #2 8007978: d9f6 bls.n 8007968 800797a: e727 b.n 80077cc 800797c: 58024400 .word 0x58024400 8007980: fffffc0c .word 0xfffffc0c 8007984: ffff0007 .word 0xffff0007 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8007988: 2b01 cmp r3, #1 temp1_pllckcfg = RCC->PLLCKSELR; 800798a: 6aaa ldr r2, [r5, #40] @ 0x28 temp2_pllckcfg = RCC->PLL1DIVR; 800798c: 6b28 ldr r0, [r5, #48] @ 0x30 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800798e: f43f aea4 beq.w 80076da (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8007992: f002 0303 and.w r3, r2, #3 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8007996: 6aa1 ldr r1, [r4, #40] @ 0x28 8007998: 428b cmp r3, r1 800799a: f47f ae9e bne.w 80076da ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800799e: f3c2 1205 ubfx r2, r2, #4, #6 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80079a2: 6ae3 ldr r3, [r4, #44] @ 0x2c 80079a4: 429a cmp r2, r3 80079a6: f47f ae98 bne.w 80076da (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 80079aa: 6b23 ldr r3, [r4, #48] @ 0x30 80079ac: f3c0 0208 ubfx r2, r0, #0, #9 80079b0: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 80079b2: 429a cmp r2, r3 80079b4: f47f ae91 bne.w 80076da ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 80079b8: 6b63 ldr r3, [r4, #52] @ 0x34 80079ba: f3c0 2246 ubfx r2, r0, #9, #7 80079be: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 80079c0: 429a cmp r2, r3 80079c2: f47f ae8a bne.w 80076da ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 80079c6: 6ba3 ldr r3, [r4, #56] @ 0x38 80079c8: f3c0 4206 ubfx r2, r0, #16, #7 80079cc: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 80079ce: 429a cmp r2, r3 80079d0: f47f ae83 bne.w 80076da ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 80079d4: 6be3 ldr r3, [r4, #60] @ 0x3c 80079d6: f3c0 6006 ubfx r0, r0, #24, #7 80079da: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 80079dc: 4298 cmp r0, r3 80079de: f47f ae7c bne.w 80076da temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 80079e2: 6b6b ldr r3, [r5, #52] @ 0x34 if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 80079e4: 6ca2 ldr r2, [r4, #72] @ 0x48 temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 80079e6: f3c3 03cc ubfx r3, r3, #3, #13 if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 80079ea: 429a cmp r2, r3 80079ec: f43f ae16 beq.w 800761c __HAL_RCC_PLLFRACN_DISABLE(); 80079f0: 4a2d ldr r2, [pc, #180] @ (8007aa8 ) 80079f2: 6ad3 ldr r3, [r2, #44] @ 0x2c 80079f4: f023 0301 bic.w r3, r3, #1 80079f8: 62d3 str r3, [r2, #44] @ 0x2c tickstart = HAL_GetTick(); 80079fa: f7fc fae9 bl 8003fd0 80079fe: 4605 mov r5, r0 while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 8007a00: f7fc fae6 bl 8003fd0 8007a04: 42a8 cmp r0, r5 8007a06: d0fb beq.n 8007a00 __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 8007a08: 4a27 ldr r2, [pc, #156] @ (8007aa8 ) 8007a0a: 4b28 ldr r3, [pc, #160] @ (8007aac ) 8007a0c: 6b50 ldr r0, [r2, #52] @ 0x34 8007a0e: 6ca1 ldr r1, [r4, #72] @ 0x48 8007a10: 4003 ands r3, r0 8007a12: ea43 03c1 orr.w r3, r3, r1, lsl #3 8007a16: 6353 str r3, [r2, #52] @ 0x34 __HAL_RCC_PLLFRACN_ENABLE(); 8007a18: 6ad3 ldr r3, [r2, #44] @ 0x2c 8007a1a: f043 0301 orr.w r3, r3, #1 8007a1e: 62d3 str r3, [r2, #44] @ 0x2c 8007a20: e5fc b.n 800761c __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8007a22: f442 2280 orr.w r2, r2, #262144 @ 0x40000 8007a26: 601a str r2, [r3, #0] 8007a28: 681a ldr r2, [r3, #0] 8007a2a: f442 3280 orr.w r2, r2, #65536 @ 0x10000 8007a2e: 601a str r2, [r3, #0] if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8007a30: e574 b.n 800751c __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8007a32: 4d1d ldr r5, [pc, #116] @ (8007aa8 ) if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007a34: f241 3788 movw r7, #5000 @ 0x1388 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8007a38: 6f2b ldr r3, [r5, #112] @ 0x70 8007a3a: f023 0301 bic.w r3, r3, #1 8007a3e: 672b str r3, [r5, #112] @ 0x70 8007a40: 6f2b ldr r3, [r5, #112] @ 0x70 8007a42: f023 0304 bic.w r3, r3, #4 8007a46: 672b str r3, [r5, #112] @ 0x70 tickstart = HAL_GetTick(); 8007a48: f7fc fac2 bl 8003fd0 8007a4c: 4606 mov r6, r0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8007a4e: e005 b.n 8007a5c if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8007a50: f7fc fabe bl 8003fd0 8007a54: 1b80 subs r0, r0, r6 8007a56: 42b8 cmp r0, r7 8007a58: f63f aeb8 bhi.w 80077cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8007a5c: 6f2b ldr r3, [r5, #112] @ 0x70 8007a5e: 0798 lsls r0, r3, #30 8007a60: d4f6 bmi.n 8007a50 8007a62: e5d7 b.n 8007614 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 8007a64: 68eb ldr r3, [r5, #12] 8007a66: 6a22 ldr r2, [r4, #32] 8007a68: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000 8007a6c: ea43 6302 orr.w r3, r3, r2, lsl #24 8007a70: 60eb str r3, [r5, #12] if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8007a72: 6823 ldr r3, [r4, #0] 8007a74: e599 b.n 80075aa __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8007a76: 4a0c ldr r2, [pc, #48] @ (8007aa8 ) 8007a78: 6f13 ldr r3, [r2, #112] @ 0x70 8007a7a: f043 0301 orr.w r3, r3, #1 8007a7e: 6713 str r3, [r2, #112] @ 0x70 if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8007a80: e67b b.n 800777a __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 8007a82: 4a09 ldr r2, [pc, #36] @ (8007aa8 ) 8007a84: 6853 ldr r3, [r2, #4] 8007a86: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 8007a8a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8007a8e: 6053 str r3, [r2, #4] if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8007a90: 6823 ldr r3, [r4, #0] 8007a92: e58a b.n 80075aa __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8007a94: f042 0204 orr.w r2, r2, #4 8007a98: 671a str r2, [r3, #112] @ 0x70 8007a9a: 6f1a ldr r2, [r3, #112] @ 0x70 8007a9c: f042 0201 orr.w r2, r2, #1 8007aa0: 671a str r2, [r3, #112] @ 0x70 if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8007aa2: e66a b.n 800777a return HAL_ERROR; 8007aa4: 2001 movs r0, #1 } 8007aa6: 4770 bx lr 8007aa8: 58024400 .word 0x58024400 8007aac: ffff0007 .word 0xffff0007 08007ab0 : switch (RCC->CFGR & RCC_CFGR_SWS) 8007ab0: 4a3f ldr r2, [pc, #252] @ (8007bb0 ) 8007ab2: 6913 ldr r3, [r2, #16] 8007ab4: f003 0338 and.w r3, r3, #56 @ 0x38 8007ab8: 2b10 cmp r3, #16 8007aba: d004 beq.n 8007ac6 8007abc: 2b18 cmp r3, #24 8007abe: d00d beq.n 8007adc 8007ac0: b11b cbz r3, 8007aca sysclockfreq = CSI_VALUE; 8007ac2: 483c ldr r0, [pc, #240] @ (8007bb4 ) 8007ac4: 4770 bx lr switch (RCC->CFGR & RCC_CFGR_SWS) 8007ac6: 483c ldr r0, [pc, #240] @ (8007bb8 ) 8007ac8: 4770 bx lr if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007aca: 6813 ldr r3, [r2, #0] 8007acc: 0699 lsls r1, r3, #26 8007ace: d548 bpl.n 8007b62 sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007ad0: 6813 ldr r3, [r2, #0] 8007ad2: 483a ldr r0, [pc, #232] @ (8007bbc ) 8007ad4: f3c3 03c1 ubfx r3, r3, #3, #2 8007ad8: 40d8 lsrs r0, r3 8007ada: 4770 bx lr pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8007adc: 6a93 ldr r3, [r2, #40] @ 0x28 { 8007ade: b430 push {r4, r5} pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 8007ae0: 6a94 ldr r4, [r2, #40] @ 0x28 pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 8007ae2: 6ad5 ldr r5, [r2, #44] @ 0x2c if (pllm != 0U) 8007ae4: f414 7f7c tst.w r4, #1008 @ 0x3f0 fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 8007ae8: 6b51 ldr r1, [r2, #52] @ 0x34 pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 8007aea: f3c4 1005 ubfx r0, r4, #4, #6 if (pllm != 0U) 8007aee: d036 beq.n 8007b5e fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 8007af0: f3c1 01cc ubfx r1, r1, #3, #13 pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 8007af4: f005 0501 and.w r5, r5, #1 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8007af8: f003 0303 and.w r3, r3, #3 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007afc: ee07 0a90 vmov s15, r0 fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 8007b00: fb05 f101 mul.w r1, r5, r1 8007b04: 2b01 cmp r3, #1 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007b06: eef8 7ae7 vcvt.f32.s32 s15, s15 8007b0a: ee06 1a90 vmov s13, r1 8007b0e: eefa 6ae9 vcvt.f32.s32 s13, s13, #13 8007b12: d002 beq.n 8007b1a 8007b14: 2b02 cmp r3, #2 8007b16: d026 beq.n 8007b66 8007b18: b343 cbz r3, 8007b6c pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007b1a: ed9f 7a29 vldr s14, [pc, #164] @ 8007bc0 8007b1e: ee87 6a27 vdiv.f32 s12, s14, s15 8007b22: 6b13 ldr r3, [r2, #48] @ 0x30 8007b24: f3c3 0308 ubfx r3, r3, #0, #9 8007b28: ee07 3a10 vmov s14, r3 8007b2c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8007b30: eeb8 7ac7 vcvt.f32.s32 s14, s14 8007b34: ee37 7a25 vadd.f32 s14, s14, s11 8007b38: ee37 7a26 vadd.f32 s14, s14, s13 8007b3c: ee27 7a06 vmul.f32 s14, s14, s12 pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 8007b40: 4b1b ldr r3, [pc, #108] @ (8007bb0 ) 8007b42: 6b1b ldr r3, [r3, #48] @ 0x30 8007b44: f3c3 2346 ubfx r3, r3, #9, #7 8007b48: 3301 adds r3, #1 sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 8007b4a: ee07 3a90 vmov s15, r3 8007b4e: eef8 6ae7 vcvt.f32.s32 s13, s15 8007b52: eec7 7a26 vdiv.f32 s15, s14, s13 8007b56: eefc 7ae7 vcvt.u32.f32 s15, s15 8007b5a: ee17 0a90 vmov r0, s15 } 8007b5e: bc30 pop {r4, r5} 8007b60: 4770 bx lr sysclockfreq = (uint32_t) HSI_VALUE; 8007b62: 4816 ldr r0, [pc, #88] @ (8007bbc ) } 8007b64: 4770 bx lr pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007b66: ed9f 7a17 vldr s14, [pc, #92] @ 8007bc4 8007b6a: e7d8 b.n 8007b1e if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007b6c: 6813 ldr r3, [r2, #0] 8007b6e: 069b lsls r3, r3, #26 8007b70: d51a bpl.n 8007ba8 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007b72: 6810 ldr r0, [r2, #0] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007b74: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8007b78: 6b13 ldr r3, [r2, #48] @ 0x30 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007b7a: 4910 ldr r1, [pc, #64] @ (8007bbc ) 8007b7c: f3c0 02c1 ubfx r2, r0, #3, #2 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007b80: f3c3 0308 ubfx r3, r3, #0, #9 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007b84: 40d1 lsrs r1, r2 pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007b86: ee06 3a10 vmov s12, r3 8007b8a: ee05 1a90 vmov s11, r1 8007b8e: eeb8 6ac6 vcvt.f32.s32 s12, s12 8007b92: eef8 5ae5 vcvt.f32.s32 s11, s11 8007b96: ee36 6a07 vadd.f32 s12, s12, s14 8007b9a: ee85 7aa7 vdiv.f32 s14, s11, s15 8007b9e: ee76 7a26 vadd.f32 s15, s12, s13 8007ba2: ee27 7a27 vmul.f32 s14, s14, s15 8007ba6: e7cb b.n 8007b40 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8007ba8: ed9f 7a07 vldr s14, [pc, #28] @ 8007bc8 8007bac: e7b7 b.n 8007b1e 8007bae: bf00 nop 8007bb0: 58024400 .word 0x58024400 8007bb4: 003d0900 .word 0x003d0900 8007bb8: 017d7840 .word 0x017d7840 8007bbc: 03d09000 .word 0x03d09000 8007bc0: 4a742400 .word 0x4a742400 8007bc4: 4bbebc20 .word 0x4bbebc20 8007bc8: 4c742400 .word 0x4c742400 08007bcc : if (RCC_ClkInitStruct == NULL) 8007bcc: 2800 cmp r0, #0 8007bce: f000 810e beq.w 8007dee if (FLatency > __HAL_FLASH_GET_LATENCY()) 8007bd2: 4a8d ldr r2, [pc, #564] @ (8007e08 ) 8007bd4: 6813 ldr r3, [r2, #0] 8007bd6: f003 030f and.w r3, r3, #15 8007bda: 428b cmp r3, r1 { 8007bdc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8007be0: 4604 mov r4, r0 8007be2: 460d mov r5, r1 if (FLatency > __HAL_FLASH_GET_LATENCY()) 8007be4: d20c bcs.n 8007c00 __HAL_FLASH_SET_LATENCY(FLatency); 8007be6: 6813 ldr r3, [r2, #0] 8007be8: f023 030f bic.w r3, r3, #15 8007bec: 430b orrs r3, r1 8007bee: 6013 str r3, [r2, #0] if (__HAL_FLASH_GET_LATENCY() != FLatency) 8007bf0: 6813 ldr r3, [r2, #0] 8007bf2: f003 030f and.w r3, r3, #15 8007bf6: 428b cmp r3, r1 8007bf8: d002 beq.n 8007c00 return HAL_ERROR; 8007bfa: 2001 movs r0, #1 } 8007bfc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8007c00: 6823 ldr r3, [r4, #0] 8007c02: 0758 lsls r0, r3, #29 8007c04: d50b bpl.n 8007c1e if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8007c06: 4981 ldr r1, [pc, #516] @ (8007e0c ) 8007c08: 6920 ldr r0, [r4, #16] 8007c0a: 698a ldr r2, [r1, #24] 8007c0c: f002 0270 and.w r2, r2, #112 @ 0x70 8007c10: 4290 cmp r0, r2 8007c12: d904 bls.n 8007c1e MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8007c14: 698a ldr r2, [r1, #24] 8007c16: f022 0270 bic.w r2, r2, #112 @ 0x70 8007c1a: 4302 orrs r2, r0 8007c1c: 618a str r2, [r1, #24] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8007c1e: 0719 lsls r1, r3, #28 8007c20: d50b bpl.n 8007c3a if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8007c22: 497a ldr r1, [pc, #488] @ (8007e0c ) 8007c24: 6960 ldr r0, [r4, #20] 8007c26: 69ca ldr r2, [r1, #28] 8007c28: f002 0270 and.w r2, r2, #112 @ 0x70 8007c2c: 4290 cmp r0, r2 8007c2e: d904 bls.n 8007c3a MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8007c30: 69ca ldr r2, [r1, #28] 8007c32: f022 0270 bic.w r2, r2, #112 @ 0x70 8007c36: 4302 orrs r2, r0 8007c38: 61ca str r2, [r1, #28] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8007c3a: 06da lsls r2, r3, #27 8007c3c: d50b bpl.n 8007c56 if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8007c3e: 4973 ldr r1, [pc, #460] @ (8007e0c ) 8007c40: 69a0 ldr r0, [r4, #24] 8007c42: 69ca ldr r2, [r1, #28] 8007c44: f402 62e0 and.w r2, r2, #1792 @ 0x700 8007c48: 4290 cmp r0, r2 8007c4a: d904 bls.n 8007c56 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8007c4c: 69ca ldr r2, [r1, #28] 8007c4e: f422 62e0 bic.w r2, r2, #1792 @ 0x700 8007c52: 4302 orrs r2, r0 8007c54: 61ca str r2, [r1, #28] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8007c56: 069f lsls r7, r3, #26 8007c58: d50b bpl.n 8007c72 if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 8007c5a: 496c ldr r1, [pc, #432] @ (8007e0c ) 8007c5c: 69e0 ldr r0, [r4, #28] 8007c5e: 6a0a ldr r2, [r1, #32] 8007c60: f002 0270 and.w r2, r2, #112 @ 0x70 8007c64: 4290 cmp r0, r2 8007c66: d904 bls.n 8007c72 MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 8007c68: 6a0a ldr r2, [r1, #32] 8007c6a: f022 0270 bic.w r2, r2, #112 @ 0x70 8007c6e: 4302 orrs r2, r0 8007c70: 620a str r2, [r1, #32] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8007c72: 079e lsls r6, r3, #30 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8007c74: f003 0201 and.w r2, r3, #1 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8007c78: f140 80ab bpl.w 8007dd2 if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8007c7c: 4e63 ldr r6, [pc, #396] @ (8007e0c ) 8007c7e: 68e0 ldr r0, [r4, #12] 8007c80: 69b1 ldr r1, [r6, #24] 8007c82: f001 010f and.w r1, r1, #15 8007c86: 4288 cmp r0, r1 8007c88: d904 bls.n 8007c94 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8007c8a: 69b1 ldr r1, [r6, #24] 8007c8c: f021 010f bic.w r1, r1, #15 8007c90: 4301 orrs r1, r0 8007c92: 61b1 str r1, [r6, #24] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8007c94: 2a00 cmp r2, #0 8007c96: d030 beq.n 8007cfa MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 8007c98: 4a5c ldr r2, [pc, #368] @ (8007e0c ) 8007c9a: 68a1 ldr r1, [r4, #8] 8007c9c: 6993 ldr r3, [r2, #24] 8007c9e: f423 6370 bic.w r3, r3, #3840 @ 0xf00 8007ca2: 430b orrs r3, r1 8007ca4: 6193 str r3, [r2, #24] if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8007ca6: 6861 ldr r1, [r4, #4] if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8007ca8: 6813 ldr r3, [r2, #0] if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8007caa: 2902 cmp r1, #2 8007cac: f000 80a1 beq.w 8007df2 else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8007cb0: 2903 cmp r1, #3 8007cb2: f000 8098 beq.w 8007de6 else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 8007cb6: 2901 cmp r1, #1 8007cb8: f000 80a1 beq.w 8007dfe if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8007cbc: 075f lsls r7, r3, #29 8007cbe: d59c bpl.n 8007bfa MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8007cc0: 4e52 ldr r6, [pc, #328] @ (8007e0c ) if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8007cc2: f241 3888 movw r8, #5000 @ 0x1388 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8007cc6: 6933 ldr r3, [r6, #16] 8007cc8: f023 0307 bic.w r3, r3, #7 8007ccc: 430b orrs r3, r1 8007cce: 6133 str r3, [r6, #16] tickstart = HAL_GetTick(); 8007cd0: f7fc f97e bl 8003fd0 8007cd4: 4607 mov r7, r0 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007cd6: e005 b.n 8007ce4 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8007cd8: f7fc f97a bl 8003fd0 8007cdc: 1bc0 subs r0, r0, r7 8007cde: 4540 cmp r0, r8 8007ce0: f200 808b bhi.w 8007dfa while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8007ce4: 6933 ldr r3, [r6, #16] 8007ce6: 6862 ldr r2, [r4, #4] 8007ce8: f003 0338 and.w r3, r3, #56 @ 0x38 8007cec: ebb3 0fc2 cmp.w r3, r2, lsl #3 8007cf0: d1f2 bne.n 8007cd8 if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8007cf2: 6823 ldr r3, [r4, #0] 8007cf4: 079e lsls r6, r3, #30 8007cf6: d506 bpl.n 8007d06 if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8007cf8: 68e0 ldr r0, [r4, #12] 8007cfa: 4944 ldr r1, [pc, #272] @ (8007e0c ) 8007cfc: 698a ldr r2, [r1, #24] 8007cfe: f002 020f and.w r2, r2, #15 8007d02: 4282 cmp r2, r0 8007d04: d869 bhi.n 8007dda if (FLatency < __HAL_FLASH_GET_LATENCY()) 8007d06: 4940 ldr r1, [pc, #256] @ (8007e08 ) 8007d08: 680a ldr r2, [r1, #0] 8007d0a: f002 020f and.w r2, r2, #15 8007d0e: 42aa cmp r2, r5 8007d10: d90a bls.n 8007d28 __HAL_FLASH_SET_LATENCY(FLatency); 8007d12: 680a ldr r2, [r1, #0] 8007d14: f022 020f bic.w r2, r2, #15 8007d18: 432a orrs r2, r5 8007d1a: 600a str r2, [r1, #0] if (__HAL_FLASH_GET_LATENCY() != FLatency) 8007d1c: 680a ldr r2, [r1, #0] 8007d1e: f002 020f and.w r2, r2, #15 8007d22: 42aa cmp r2, r5 8007d24: f47f af69 bne.w 8007bfa if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8007d28: 0758 lsls r0, r3, #29 8007d2a: d50b bpl.n 8007d44 if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8007d2c: 4937 ldr r1, [pc, #220] @ (8007e0c ) 8007d2e: 6920 ldr r0, [r4, #16] 8007d30: 698a ldr r2, [r1, #24] 8007d32: f002 0270 and.w r2, r2, #112 @ 0x70 8007d36: 4290 cmp r0, r2 8007d38: d204 bcs.n 8007d44 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8007d3a: 698a ldr r2, [r1, #24] 8007d3c: f022 0270 bic.w r2, r2, #112 @ 0x70 8007d40: 4302 orrs r2, r0 8007d42: 618a str r2, [r1, #24] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8007d44: 0719 lsls r1, r3, #28 8007d46: d50b bpl.n 8007d60 if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8007d48: 4930 ldr r1, [pc, #192] @ (8007e0c ) 8007d4a: 6960 ldr r0, [r4, #20] 8007d4c: 69ca ldr r2, [r1, #28] 8007d4e: f002 0270 and.w r2, r2, #112 @ 0x70 8007d52: 4290 cmp r0, r2 8007d54: d204 bcs.n 8007d60 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8007d56: 69ca ldr r2, [r1, #28] 8007d58: f022 0270 bic.w r2, r2, #112 @ 0x70 8007d5c: 4302 orrs r2, r0 8007d5e: 61ca str r2, [r1, #28] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8007d60: 06da lsls r2, r3, #27 8007d62: d50b bpl.n 8007d7c if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8007d64: 4929 ldr r1, [pc, #164] @ (8007e0c ) 8007d66: 69a0 ldr r0, [r4, #24] 8007d68: 69ca ldr r2, [r1, #28] 8007d6a: f402 62e0 and.w r2, r2, #1792 @ 0x700 8007d6e: 4290 cmp r0, r2 8007d70: d204 bcs.n 8007d7c MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8007d72: 69ca ldr r2, [r1, #28] 8007d74: f422 62e0 bic.w r2, r2, #1792 @ 0x700 8007d78: 4302 orrs r2, r0 8007d7a: 61ca str r2, [r1, #28] if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8007d7c: 069b lsls r3, r3, #26 8007d7e: d50b bpl.n 8007d98 if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 8007d80: 4a22 ldr r2, [pc, #136] @ (8007e0c ) 8007d82: 69e1 ldr r1, [r4, #28] 8007d84: 6a13 ldr r3, [r2, #32] 8007d86: f003 0370 and.w r3, r3, #112 @ 0x70 8007d8a: 4299 cmp r1, r3 8007d8c: d204 bcs.n 8007d98 MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 8007d8e: 6a13 ldr r3, [r2, #32] 8007d90: f023 0370 bic.w r3, r3, #112 @ 0x70 8007d94: 430b orrs r3, r1 8007d96: 6213 str r3, [r2, #32] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8007d98: f7ff fe8a bl 8007ab0 8007d9c: 4a1b ldr r2, [pc, #108] @ (8007e0c ) 8007d9e: 4603 mov r3, r0 8007da0: 481b ldr r0, [pc, #108] @ (8007e10 ) 8007da2: 6991 ldr r1, [r2, #24] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007da4: 6992 ldr r2, [r2, #24] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8007da6: f3c1 2103 ubfx r1, r1, #8, #4 SystemCoreClock = common_system_clock; 8007daa: 4d1a ldr r5, [pc, #104] @ (8007e14 ) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007dac: f002 020f and.w r2, r2, #15 8007db0: 4c19 ldr r4, [pc, #100] @ (8007e18 ) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8007db2: 5c41 ldrb r1, [r0, r1] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007db4: 5c82 ldrb r2, [r0, r2] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8007db6: f001 011f and.w r1, r1, #31 halstatus = HAL_InitTick(uwTickPrio); 8007dba: 4818 ldr r0, [pc, #96] @ (8007e1c ) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007dbc: f002 021f and.w r2, r2, #31 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8007dc0: 40cb lsrs r3, r1 halstatus = HAL_InitTick(uwTickPrio); 8007dc2: 6800 ldr r0, [r0, #0] SystemCoreClock = common_system_clock; 8007dc4: 602b str r3, [r5, #0] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007dc6: 40d3 lsrs r3, r2 8007dc8: 6023 str r3, [r4, #0] } 8007dca: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} halstatus = HAL_InitTick(uwTickPrio); 8007dce: f7fb b8b5 b.w 8002f3c if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8007dd2: 2a00 cmp r2, #0 8007dd4: f47f af60 bne.w 8007c98 8007dd8: e795 b.n 8007d06 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8007dda: 698a ldr r2, [r1, #24] 8007ddc: f022 020f bic.w r2, r2, #15 8007de0: 4302 orrs r2, r0 8007de2: 618a str r2, [r1, #24] 8007de4: e78f b.n 8007d06 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8007de6: 019a lsls r2, r3, #6 8007de8: f53f af6a bmi.w 8007cc0 8007dec: e705 b.n 8007bfa return HAL_ERROR; 8007dee: 2001 movs r0, #1 } 8007df0: 4770 bx lr if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8007df2: 0398 lsls r0, r3, #14 8007df4: f53f af64 bmi.w 8007cc0 8007df8: e6ff b.n 8007bfa return HAL_TIMEOUT; 8007dfa: 2003 movs r0, #3 8007dfc: e6fe b.n 8007bfc if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8007dfe: 05db lsls r3, r3, #23 8007e00: f53f af5e bmi.w 8007cc0 8007e04: e6f9 b.n 8007bfa 8007e06: bf00 nop 8007e08: 52002000 .word 0x52002000 8007e0c: 58024400 .word 0x58024400 8007e10: 08011a14 .word 0x08011a14 8007e14: 24000038 .word 0x24000038 8007e18: 24000034 .word 0x24000034 8007e1c: 24000040 .word 0x24000040 08007e20 : switch (RCC->CFGR & RCC_CFGR_SWS) 8007e20: 4a18 ldr r2, [pc, #96] @ (8007e84 ) * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8007e22: b538 push {r3, r4, r5, lr} switch (RCC->CFGR & RCC_CFGR_SWS) 8007e24: 6913 ldr r3, [r2, #16] 8007e26: f003 0338 and.w r3, r3, #56 @ 0x38 8007e2a: 2b10 cmp r3, #16 8007e2c: d019 beq.n 8007e62 8007e2e: 2b18 cmp r3, #24 8007e30: d022 beq.n 8007e78 8007e32: b1c3 cbz r3, 8007e66 sysclockfreq = CSI_VALUE; 8007e34: 4b14 ldr r3, [pc, #80] @ (8007e88 ) uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007e36: 4913 ldr r1, [pc, #76] @ (8007e84 ) 8007e38: 4814 ldr r0, [pc, #80] @ (8007e8c ) 8007e3a: 698a ldr r2, [r1, #24] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007e3c: 6989 ldr r1, [r1, #24] common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007e3e: f3c2 2203 ubfx r2, r2, #8, #4 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007e42: 4c13 ldr r4, [pc, #76] @ (8007e90 ) 8007e44: f001 010f and.w r1, r1, #15 #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8007e48: 4d12 ldr r5, [pc, #72] @ (8007e94 ) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007e4a: 5c82 ldrb r2, [r0, r2] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007e4c: 5c40 ldrb r0, [r0, r1] common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007e4e: f002 021f and.w r2, r2, #31 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007e52: f000 001f and.w r0, r0, #31 common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007e56: 40d3 lsrs r3, r2 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007e58: fa23 f000 lsr.w r0, r3, r0 SystemCoreClock = common_system_clock; 8007e5c: 602b str r3, [r5, #0] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007e5e: 6020 str r0, [r4, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; } 8007e60: bd38 pop {r3, r4, r5, pc} switch (RCC->CFGR & RCC_CFGR_SWS) 8007e62: 4b0d ldr r3, [pc, #52] @ (8007e98 ) 8007e64: e7e7 b.n 8007e36 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007e66: 6813 ldr r3, [r2, #0] 8007e68: 069b lsls r3, r3, #26 8007e6a: d509 bpl.n 8007e80 sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007e6c: 6812 ldr r2, [r2, #0] 8007e6e: 4b0b ldr r3, [pc, #44] @ (8007e9c ) 8007e70: f3c2 02c1 ubfx r2, r2, #3, #2 8007e74: 40d3 lsrs r3, r2 8007e76: e7de b.n 8007e36 8007e78: f7ff fab6 bl 80073e8 8007e7c: 4603 mov r3, r0 8007e7e: e7da b.n 8007e36 sysclockfreq = (uint32_t) HSI_VALUE; 8007e80: 4b06 ldr r3, [pc, #24] @ (8007e9c ) 8007e82: e7d8 b.n 8007e36 8007e84: 58024400 .word 0x58024400 8007e88: 003d0900 .word 0x003d0900 8007e8c: 08011a14 .word 0x08011a14 8007e90: 24000034 .word 0x24000034 8007e94: 24000038 .word 0x24000038 8007e98: 017d7840 .word 0x017d7840 8007e9c: 03d09000 .word 0x03d09000 08007ea0 : switch (RCC->CFGR & RCC_CFGR_SWS) 8007ea0: 4a1c ldr r2, [pc, #112] @ (8007f14 ) * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8007ea2: b538 push {r3, r4, r5, lr} switch (RCC->CFGR & RCC_CFGR_SWS) 8007ea4: 6913 ldr r3, [r2, #16] 8007ea6: f003 0338 and.w r3, r3, #56 @ 0x38 8007eaa: 2b10 cmp r3, #16 8007eac: d020 beq.n 8007ef0 8007eae: 2b18 cmp r3, #24 8007eb0: d029 beq.n 8007f06 8007eb2: b1fb cbz r3, 8007ef4 sysclockfreq = CSI_VALUE; 8007eb4: 4b18 ldr r3, [pc, #96] @ (8007f18 ) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007eb6: 4a17 ldr r2, [pc, #92] @ (8007f14 ) 8007eb8: 4918 ldr r1, [pc, #96] @ (8007f1c ) 8007eba: 6990 ldr r0, [r2, #24] SystemCoreClock = common_system_clock; 8007ebc: 4d18 ldr r5, [pc, #96] @ (8007f20 ) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007ebe: f3c0 2003 ubfx r0, r0, #8, #4 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007ec2: 4c18 ldr r4, [pc, #96] @ (8007f24 ) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007ec4: 5c08 ldrb r0, [r1, r0] 8007ec6: f000 001f and.w r0, r0, #31 8007eca: 40c3 lsrs r3, r0 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007ecc: 6990 ldr r0, [r2, #24] 8007ece: f000 000f and.w r0, r0, #15 SystemCoreClock = common_system_clock; 8007ed2: 602b str r3, [r5, #0] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007ed4: 5c08 ldrb r0, [r1, r0] 8007ed6: f000 001f and.w r0, r0, #31 8007eda: 40c3 lsrs r3, r0 8007edc: 6023 str r3, [r4, #0] #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 8007ede: 69d2 ldr r2, [r2, #28] 8007ee0: f3c2 1202 ubfx r2, r2, #4, #3 8007ee4: 5c88 ldrb r0, [r1, r2] 8007ee6: f000 001f and.w r0, r0, #31 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 8007eea: fa23 f000 lsr.w r0, r3, r0 8007eee: bd38 pop {r3, r4, r5, pc} switch (RCC->CFGR & RCC_CFGR_SWS) 8007ef0: 4b0d ldr r3, [pc, #52] @ (8007f28 ) 8007ef2: e7e0 b.n 8007eb6 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007ef4: 6813 ldr r3, [r2, #0] 8007ef6: 069b lsls r3, r3, #26 8007ef8: d509 bpl.n 8007f0e sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007efa: 6812 ldr r2, [r2, #0] 8007efc: 4b0b ldr r3, [pc, #44] @ (8007f2c ) 8007efe: f3c2 02c1 ubfx r2, r2, #3, #2 8007f02: 40d3 lsrs r3, r2 8007f04: e7d7 b.n 8007eb6 8007f06: f7ff fa6f bl 80073e8 8007f0a: 4603 mov r3, r0 8007f0c: e7d3 b.n 8007eb6 sysclockfreq = (uint32_t) HSI_VALUE; 8007f0e: 4b07 ldr r3, [pc, #28] @ (8007f2c ) 8007f10: e7d1 b.n 8007eb6 8007f12: bf00 nop 8007f14: 58024400 .word 0x58024400 8007f18: 003d0900 .word 0x003d0900 8007f1c: 08011a14 .word 0x08011a14 8007f20: 24000038 .word 0x24000038 8007f24: 24000034 .word 0x24000034 8007f28: 017d7840 .word 0x017d7840 8007f2c: 03d09000 .word 0x03d09000 08007f30 : switch (RCC->CFGR & RCC_CFGR_SWS) 8007f30: 4a1c ldr r2, [pc, #112] @ (8007fa4 ) * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8007f32: b538 push {r3, r4, r5, lr} switch (RCC->CFGR & RCC_CFGR_SWS) 8007f34: 6913 ldr r3, [r2, #16] 8007f36: f003 0338 and.w r3, r3, #56 @ 0x38 8007f3a: 2b10 cmp r3, #16 8007f3c: d020 beq.n 8007f80 8007f3e: 2b18 cmp r3, #24 8007f40: d029 beq.n 8007f96 8007f42: b1fb cbz r3, 8007f84 sysclockfreq = CSI_VALUE; 8007f44: 4b18 ldr r3, [pc, #96] @ (8007fa8 ) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007f46: 4a17 ldr r2, [pc, #92] @ (8007fa4 ) 8007f48: 4918 ldr r1, [pc, #96] @ (8007fac ) 8007f4a: 6990 ldr r0, [r2, #24] SystemCoreClock = common_system_clock; 8007f4c: 4d18 ldr r5, [pc, #96] @ (8007fb0 ) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007f4e: f3c0 2003 ubfx r0, r0, #8, #4 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007f52: 4c18 ldr r4, [pc, #96] @ (8007fb4 ) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8007f54: 5c08 ldrb r0, [r1, r0] 8007f56: f000 001f and.w r0, r0, #31 8007f5a: 40c3 lsrs r3, r0 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007f5c: 6990 ldr r0, [r2, #24] 8007f5e: f000 000f and.w r0, r0, #15 SystemCoreClock = common_system_clock; 8007f62: 602b str r3, [r5, #0] SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8007f64: 5c08 ldrb r0, [r1, r0] 8007f66: f000 001f and.w r0, r0, #31 8007f6a: 40c3 lsrs r3, r0 8007f6c: 6023 str r3, [r4, #0] /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 8007f6e: 69d2 ldr r2, [r2, #28] 8007f70: f3c2 2202 ubfx r2, r2, #8, #3 8007f74: 5c88 ldrb r0, [r1, r2] 8007f76: f000 001f and.w r0, r0, #31 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 8007f7a: fa23 f000 lsr.w r0, r3, r0 8007f7e: bd38 pop {r3, r4, r5, pc} switch (RCC->CFGR & RCC_CFGR_SWS) 8007f80: 4b0d ldr r3, [pc, #52] @ (8007fb8 ) 8007f82: e7e0 b.n 8007f46 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007f84: 6813 ldr r3, [r2, #0] 8007f86: 069b lsls r3, r3, #26 8007f88: d509 bpl.n 8007f9e sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007f8a: 6812 ldr r2, [r2, #0] 8007f8c: 4b0b ldr r3, [pc, #44] @ (8007fbc ) 8007f8e: f3c2 02c1 ubfx r2, r2, #3, #2 8007f92: 40d3 lsrs r3, r2 8007f94: e7d7 b.n 8007f46 8007f96: f7ff fa27 bl 80073e8 8007f9a: 4603 mov r3, r0 8007f9c: e7d3 b.n 8007f46 sysclockfreq = (uint32_t) HSI_VALUE; 8007f9e: 4b07 ldr r3, [pc, #28] @ (8007fbc ) 8007fa0: e7d1 b.n 8007f46 8007fa2: bf00 nop 8007fa4: 58024400 .word 0x58024400 8007fa8: 003d0900 .word 0x003d0900 8007fac: 08011a14 .word 0x08011a14 8007fb0: 24000038 .word 0x24000038 8007fb4: 24000034 .word 0x24000034 8007fb8: 017d7840 .word 0x017d7840 8007fbc: 03d09000 .word 0x03d09000 08007fc0 : /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8007fc0: 4b13 ldr r3, [pc, #76] @ (8008010 ) RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 8007fc2: 223f movs r2, #63 @ 0x3f 8007fc4: 6002 str r2, [r0, #0] RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8007fc6: 691a ldr r2, [r3, #16] 8007fc8: f002 0207 and.w r2, r2, #7 8007fcc: 6042 str r2, [r0, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 8007fce: 699a ldr r2, [r3, #24] 8007fd0: f402 6270 and.w r2, r2, #3840 @ 0xf00 8007fd4: 6082 str r2, [r0, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 8007fd6: 699a ldr r2, [r3, #24] 8007fd8: f002 020f and.w r2, r2, #15 8007fdc: 60c2 str r2, [r0, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 8007fde: 699a ldr r2, [r3, #24] 8007fe0: f002 0270 and.w r2, r2, #112 @ 0x70 8007fe4: 6102 str r2, [r0, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 8007fe6: 69da ldr r2, [r3, #28] 8007fe8: f002 0270 and.w r2, r2, #112 @ 0x70 8007fec: 6142 str r2, [r0, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 8007fee: 69da ldr r2, [r3, #28] 8007ff0: f402 62e0 and.w r2, r2, #1792 @ 0x700 8007ff4: 6182 str r2, [r0, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 8007ff6: 6a1b ldr r3, [r3, #32] { 8007ff8: b410 push {r4} RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 8007ffa: f003 0370 and.w r3, r3, #112 @ 0x70 /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 8007ffe: 4c05 ldr r4, [pc, #20] @ (8008014 ) RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 8008000: 61c3 str r3, [r0, #28] *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 8008002: 6823 ldr r3, [r4, #0] } 8008004: f85d 4b04 ldr.w r4, [sp], #4 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 8008008: f003 030f and.w r3, r3, #15 800800c: 600b str r3, [r1, #0] } 800800e: 4770 bx lr 8008010: 58024400 .word 0x58024400 8008014: 52002000 .word 0x52002000 08008018 : * @param Divider divider parameter to be updated * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) 8008018: b5f8 push {r3, r4, r5, r6, r7, lr} else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800801a: 4c36 ldr r4, [pc, #216] @ (80080f4 ) static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) 800801c: 4606 mov r6, r0 800801e: 460f mov r7, r1 __HAL_RCC_PLL2_DISABLE(); 8008020: 6823 ldr r3, [r4, #0] 8008022: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8008026: 6023 str r3, [r4, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8008028: f7fb ffd2 bl 8003fd0 800802c: 4605 mov r5, r0 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800802e: e004 b.n 800803a { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8008030: f7fb ffce bl 8003fd0 8008034: 1b40 subs r0, r0, r5 8008036: 2802 cmp r0, #2 8008038: d856 bhi.n 80080e8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800803a: 6823 ldr r3, [r4, #0] 800803c: 011a lsls r2, r3, #4 800803e: d4f7 bmi.n 8008030 return HAL_TIMEOUT; } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 8008040: 6aa3 ldr r3, [r4, #40] @ 0x28 8008042: 6832 ldr r2, [r6, #0] 8008044: f423 337c bic.w r3, r3, #258048 @ 0x3f000 8008048: ea43 3302 orr.w r3, r3, r2, lsl #12 800804c: 62a3 str r3, [r4, #40] @ 0x28 800804e: e9d6 3202 ldrd r3, r2, [r6, #8] 8008052: 3b01 subs r3, #1 8008054: 3a01 subs r2, #1 8008056: 025b lsls r3, r3, #9 8008058: 0412 lsls r2, r2, #16 800805a: b29b uxth r3, r3 800805c: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000 8008060: 4313 orrs r3, r2 8008062: 6872 ldr r2, [r6, #4] 8008064: 3a01 subs r2, #1 8008066: f3c2 0208 ubfx r2, r2, #0, #9 800806a: 4313 orrs r3, r2 800806c: 6932 ldr r2, [r6, #16] 800806e: 3a01 subs r2, #1 8008070: 0612 lsls r2, r2, #24 8008072: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000 8008076: 4313 orrs r3, r2 8008078: 63a3 str r3, [r4, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800807a: 6ae3 ldr r3, [r4, #44] @ 0x2c 800807c: 6972 ldr r2, [r6, #20] 800807e: f023 03c0 bic.w r3, r3, #192 @ 0xc0 8008082: 4313 orrs r3, r2 8008084: 62e3 str r3, [r4, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8008086: 6ae2 ldr r2, [r4, #44] @ 0x2c 8008088: 69b3 ldr r3, [r6, #24] 800808a: f022 0220 bic.w r2, r2, #32 800808e: 431a orrs r2, r3 /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 8008090: 4b19 ldr r3, [pc, #100] @ (80080f8 ) __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8008092: 62e2 str r2, [r4, #44] @ 0x2c __HAL_RCC_PLL2FRACN_DISABLE(); 8008094: 6ae2 ldr r2, [r4, #44] @ 0x2c 8008096: f022 0210 bic.w r2, r2, #16 800809a: 62e2 str r2, [r4, #44] @ 0x2c __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800809c: 6be1 ldr r1, [r4, #60] @ 0x3c 800809e: 69f2 ldr r2, [r6, #28] 80080a0: 400b ands r3, r1 80080a2: ea43 03c2 orr.w r3, r3, r2, lsl #3 80080a6: 63e3 str r3, [r4, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 80080a8: 6ae3 ldr r3, [r4, #44] @ 0x2c 80080aa: f043 0310 orr.w r3, r3, #16 80080ae: 62e3 str r3, [r4, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 80080b0: 6ae3 ldr r3, [r4, #44] @ 0x2c if (Divider == DIVIDER_P_UPDATE) 80080b2: b1df cbz r7, 80080ec } else if (Divider == DIVIDER_Q_UPDATE) 80080b4: 2f01 cmp r7, #1 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 80080b6: bf0c ite eq 80080b8: f443 1380 orreq.w r3, r3, #1048576 @ 0x100000 } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 80080bc: f443 1300 orrne.w r3, r3, #2097152 @ 0x200000 80080c0: 62e3 str r3, [r4, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 80080c2: 4c0c ldr r4, [pc, #48] @ (80080f4 ) 80080c4: 6823 ldr r3, [r4, #0] 80080c6: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 80080ca: 6023 str r3, [r4, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80080cc: f7fb ff80 bl 8003fd0 80080d0: 4605 mov r5, r0 /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 80080d2: e004 b.n 80080de { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 80080d4: f7fb ff7c bl 8003fd0 80080d8: 1b40 subs r0, r0, r5 80080da: 2802 cmp r0, #2 80080dc: d804 bhi.n 80080e8 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 80080de: 6823 ldr r3, [r4, #0] 80080e0: 011b lsls r3, r3, #4 80080e2: d5f7 bpl.n 80080d4 } } return status; 80080e4: 2000 movs r0, #0 } 80080e6: bdf8 pop {r3, r4, r5, r6, r7, pc} return HAL_TIMEOUT; 80080e8: 2003 movs r0, #3 } 80080ea: bdf8 pop {r3, r4, r5, r6, r7, pc} __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 80080ec: f443 2300 orr.w r3, r3, #524288 @ 0x80000 80080f0: 62e3 str r3, [r4, #44] @ 0x2c 80080f2: e7e6 b.n 80080c2 80080f4: 58024400 .word 0x58024400 80080f8: ffff0007 .word 0xffff0007 080080fc : * @param Divider divider parameter to be updated * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) 80080fc: b5f8 push {r3, r4, r5, r6, r7, lr} else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 80080fe: 4c36 ldr r4, [pc, #216] @ (80081d8 ) static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) 8008100: 4606 mov r6, r0 8008102: 460f mov r7, r1 __HAL_RCC_PLL3_DISABLE(); 8008104: 6823 ldr r3, [r4, #0] 8008106: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800810a: 6023 str r3, [r4, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800810c: f7fb ff60 bl 8003fd0 8008110: 4605 mov r5, r0 /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 8008112: e004 b.n 800811e { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 8008114: f7fb ff5c bl 8003fd0 8008118: 1b40 subs r0, r0, r5 800811a: 2802 cmp r0, #2 800811c: d856 bhi.n 80081cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800811e: 6823 ldr r3, [r4, #0] 8008120: 009a lsls r2, r3, #2 8008122: d4f7 bmi.n 8008114 return HAL_TIMEOUT; } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 8008124: 6aa3 ldr r3, [r4, #40] @ 0x28 8008126: 6832 ldr r2, [r6, #0] 8008128: f023 737c bic.w r3, r3, #66060288 @ 0x3f00000 800812c: ea43 5302 orr.w r3, r3, r2, lsl #20 8008130: 62a3 str r3, [r4, #40] @ 0x28 8008132: e9d6 3202 ldrd r3, r2, [r6, #8] 8008136: 3b01 subs r3, #1 8008138: 3a01 subs r2, #1 800813a: 025b lsls r3, r3, #9 800813c: 0412 lsls r2, r2, #16 800813e: b29b uxth r3, r3 8008140: f402 02fe and.w r2, r2, #8323072 @ 0x7f0000 8008144: 4313 orrs r3, r2 8008146: 6872 ldr r2, [r6, #4] 8008148: 3a01 subs r2, #1 800814a: f3c2 0208 ubfx r2, r2, #0, #9 800814e: 4313 orrs r3, r2 8008150: 6932 ldr r2, [r6, #16] 8008152: 3a01 subs r2, #1 8008154: 0612 lsls r2, r2, #24 8008156: f002 42fe and.w r2, r2, #2130706432 @ 0x7f000000 800815a: 4313 orrs r3, r2 800815c: 6423 str r3, [r4, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800815e: 6ae3 ldr r3, [r4, #44] @ 0x2c 8008160: 6972 ldr r2, [r6, #20] 8008162: f423 6340 bic.w r3, r3, #3072 @ 0xc00 8008166: 4313 orrs r3, r2 8008168: 62e3 str r3, [r4, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800816a: 6ae2 ldr r2, [r4, #44] @ 0x2c 800816c: 69b3 ldr r3, [r6, #24] 800816e: f422 7200 bic.w r2, r2, #512 @ 0x200 8008172: 431a orrs r2, r3 /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 8008174: 4b19 ldr r3, [pc, #100] @ (80081dc ) __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 8008176: 62e2 str r2, [r4, #44] @ 0x2c __HAL_RCC_PLL3FRACN_DISABLE(); 8008178: 6ae2 ldr r2, [r4, #44] @ 0x2c 800817a: f422 7280 bic.w r2, r2, #256 @ 0x100 800817e: 62e2 str r2, [r4, #44] @ 0x2c __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 8008180: 6c61 ldr r1, [r4, #68] @ 0x44 8008182: 69f2 ldr r2, [r6, #28] 8008184: 400b ands r3, r1 8008186: ea43 03c2 orr.w r3, r3, r2, lsl #3 800818a: 6463 str r3, [r4, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800818c: 6ae3 ldr r3, [r4, #44] @ 0x2c 800818e: f443 7380 orr.w r3, r3, #256 @ 0x100 8008192: 62e3 str r3, [r4, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 8008194: 6ae3 ldr r3, [r4, #44] @ 0x2c if (Divider == DIVIDER_P_UPDATE) 8008196: b1df cbz r7, 80081d0 } else if (Divider == DIVIDER_Q_UPDATE) 8008198: 2f01 cmp r7, #1 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800819a: bf0c ite eq 800819c: f443 0300 orreq.w r3, r3, #8388608 @ 0x800000 } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 80081a0: f043 7380 orrne.w r3, r3, #16777216 @ 0x1000000 80081a4: 62e3 str r3, [r4, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 80081a6: 4c0c ldr r4, [pc, #48] @ (80081d8 ) 80081a8: 6823 ldr r3, [r4, #0] 80081aa: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80081ae: 6023 str r3, [r4, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80081b0: f7fb ff0e bl 8003fd0 80081b4: 4605 mov r5, r0 /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 80081b6: e004 b.n 80081c2 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 80081b8: f7fb ff0a bl 8003fd0 80081bc: 1b40 subs r0, r0, r5 80081be: 2802 cmp r0, #2 80081c0: d804 bhi.n 80081cc while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 80081c2: 6823 ldr r3, [r4, #0] 80081c4: 009b lsls r3, r3, #2 80081c6: d5f7 bpl.n 80081b8 } } return status; 80081c8: 2000 movs r0, #0 } 80081ca: bdf8 pop {r3, r4, r5, r6, r7, pc} return HAL_TIMEOUT; 80081cc: 2003 movs r0, #3 } 80081ce: bdf8 pop {r3, r4, r5, r6, r7, pc} __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 80081d0: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 80081d4: 62e3 str r3, [r4, #44] @ 0x2c 80081d6: e7e6 b.n 80081a6 80081d8: 58024400 .word 0x58024400 80081dc: ffff0007 .word 0xffff0007 080081e0 : { 80081e0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80081e4: e9d0 3200 ldrd r3, r2, [r0] { 80081e8: 4604 mov r4, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80081ea: 011d lsls r5, r3, #4 80081ec: f003 6600 and.w r6, r3, #134217728 @ 0x8000000 80081f0: d525 bpl.n 800823e switch (PeriphClkInit->SpdifrxClockSelection) 80081f2: 6e81 ldr r1, [r0, #104] @ 0x68 80081f4: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 80081f8: f000 8652 beq.w 8008ea0 80081fc: d814 bhi.n 8008228 80081fe: 2900 cmp r1, #0 8008200: f000 86ee beq.w 8008fe0 8008204: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 8008208: f040 8456 bne.w 8008ab8 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800820c: 49ad ldr r1, [pc, #692] @ (80084c4 ) 800820e: 6a89 ldr r1, [r1, #40] @ 0x28 8008210: f001 0103 and.w r1, r1, #3 8008214: 2903 cmp r1, #3 8008216: f000 844f beq.w 8008ab8 800821a: 2102 movs r1, #2 800821c: 3008 adds r0, #8 800821e: f7ff fefb bl 8008018 8008222: 4606 mov r6, r0 break; 8008224: f000 be48 b.w 8008eb8 switch (PeriphClkInit->SpdifrxClockSelection) 8008228: f5b1 1f40 cmp.w r1, #3145728 @ 0x300000 800822c: f040 8444 bne.w 8008ab8 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 8008230: 4da4 ldr r5, [pc, #656] @ (80084c4 ) HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8008232: 2600 movs r6, #0 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 8008234: 6d28 ldr r0, [r5, #80] @ 0x50 8008236: f420 1040 bic.w r0, r0, #3145728 @ 0x300000 800823a: 4301 orrs r1, r0 800823c: 6529 str r1, [r5, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800823e: 05d8 lsls r0, r3, #23 8008240: d50a bpl.n 8008258 switch (PeriphClkInit->Sai1ClockSelection) 8008242: 6da1 ldr r1, [r4, #88] @ 0x58 8008244: 2904 cmp r1, #4 8008246: d806 bhi.n 8008256 8008248: e8df f011 tbh [pc, r1, lsl #1] 800824c: 06680484 .word 0x06680484 8008250: 0489067d .word 0x0489067d 8008254: 0489 .short 0x0489 8008256: 2601 movs r6, #1 8008258: 4635 mov r5, r6 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800825a: 0599 lsls r1, r3, #22 800825c: d524 bpl.n 80082a8 switch (PeriphClkInit->Sai23ClockSelection) 800825e: 6de1 ldr r1, [r4, #92] @ 0x5c 8008260: 2980 cmp r1, #128 @ 0x80 8008262: f000 8647 beq.w 8008ef4 8008266: f200 8122 bhi.w 80084ae 800826a: 2900 cmp r1, #0 800826c: f000 8484 beq.w 8008b78 8008270: 2940 cmp r1, #64 @ 0x40 8008272: f040 8123 bne.w 80084bc if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008276: 4993 ldr r1, [pc, #588] @ (80084c4 ) 8008278: 6a89 ldr r1, [r1, #40] @ 0x28 800827a: f001 0103 and.w r1, r1, #3 800827e: 2903 cmp r1, #3 8008280: f000 811c beq.w 80084bc 8008284: 2100 movs r1, #0 8008286: f104 0008 add.w r0, r4, #8 800828a: f7ff fec5 bl 8008018 800828e: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 8008290: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008294: 2d00 cmp r5, #0 8008296: f040 850f bne.w 8008cb8 __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800829a: 4f8a ldr r7, [pc, #552] @ (80084c4 ) 800829c: 6de0 ldr r0, [r4, #92] @ 0x5c 800829e: 6d39 ldr r1, [r7, #80] @ 0x50 80082a0: f421 71e0 bic.w r1, r1, #448 @ 0x1c0 80082a4: 4301 orrs r1, r0 80082a6: 6539 str r1, [r7, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 80082a8: 055f lsls r7, r3, #21 80082aa: d528 bpl.n 80082fe switch (PeriphClkInit->Sai4AClockSelection) 80082ac: f8d4 10a8 ldr.w r1, [r4, #168] @ 0xa8 80082b0: f5b1 0f80 cmp.w r1, #4194304 @ 0x400000 80082b4: f000 85e0 beq.w 8008e78 80082b8: f200 8106 bhi.w 80084c8 80082bc: 2900 cmp r1, #0 80082be: f000 8465 beq.w 8008b8c 80082c2: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 80082c6: f040 8107 bne.w 80084d8 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80082ca: 497e ldr r1, [pc, #504] @ (80084c4 ) 80082cc: 6a89 ldr r1, [r1, #40] @ 0x28 80082ce: f001 0103 and.w r1, r1, #3 80082d2: 2903 cmp r1, #3 80082d4: f000 8100 beq.w 80084d8 80082d8: 2100 movs r1, #0 80082da: f104 0008 add.w r0, r4, #8 80082de: f7ff fe9b bl 8008018 80082e2: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 80082e4: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 80082e8: 2d00 cmp r5, #0 80082ea: f040 84e8 bne.w 8008cbe __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 80082ee: 4f75 ldr r7, [pc, #468] @ (80084c4 ) 80082f0: f8d4 00a8 ldr.w r0, [r4, #168] @ 0xa8 80082f4: 6db9 ldr r1, [r7, #88] @ 0x58 80082f6: f421 0160 bic.w r1, r1, #14680064 @ 0xe00000 80082fa: 4301 orrs r1, r0 80082fc: 65b9 str r1, [r7, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 80082fe: 0518 lsls r0, r3, #20 8008300: d528 bpl.n 8008354 switch (PeriphClkInit->Sai4BClockSelection) 8008302: f8d4 10ac ldr.w r1, [r4, #172] @ 0xac 8008306: f1b1 7f00 cmp.w r1, #33554432 @ 0x2000000 800830a: f000 85df beq.w 8008ecc 800830e: f200 80e6 bhi.w 80084de 8008312: 2900 cmp r1, #0 8008314: f000 8444 beq.w 8008ba0 8008318: f1b1 7f80 cmp.w r1, #16777216 @ 0x1000000 800831c: f040 80e7 bne.w 80084ee if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008320: 4968 ldr r1, [pc, #416] @ (80084c4 ) 8008322: 6a89 ldr r1, [r1, #40] @ 0x28 8008324: f001 0103 and.w r1, r1, #3 8008328: 2903 cmp r1, #3 800832a: f000 80e0 beq.w 80084ee 800832e: 2100 movs r1, #0 8008330: f104 0008 add.w r0, r4, #8 8008334: f7ff fe70 bl 8008018 8008338: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800833a: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 800833e: 2d00 cmp r5, #0 8008340: f040 84c0 bne.w 8008cc4 __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 8008344: 4f5f ldr r7, [pc, #380] @ (80084c4 ) 8008346: f8d4 00ac ldr.w r0, [r4, #172] @ 0xac 800834a: 6db9 ldr r1, [r7, #88] @ 0x58 800834c: f021 61e0 bic.w r1, r1, #117440512 @ 0x7000000 8008350: 4301 orrs r1, r0 8008352: 65b9 str r1, [r7, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 8008354: 0199 lsls r1, r3, #6 8008356: d518 bpl.n 800838a switch (PeriphClkInit->QspiClockSelection) 8008358: 6ce1 ldr r1, [r4, #76] @ 0x4c 800835a: 2920 cmp r1, #32 800835c: f000 84e1 beq.w 8008d22 8008360: f200 80c8 bhi.w 80084f4 8008364: b139 cbz r1, 8008376 8008366: 2910 cmp r1, #16 8008368: f040 80c7 bne.w 80084fa __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800836c: 4855 ldr r0, [pc, #340] @ (80084c4 ) 800836e: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008370: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008374: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008376: 2d00 cmp r5, #0 8008378: f040 849b bne.w 8008cb2 __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800837c: 4f51 ldr r7, [pc, #324] @ (80084c4 ) 800837e: 6ce0 ldr r0, [r4, #76] @ 0x4c 8008380: 6cf9 ldr r1, [r7, #76] @ 0x4c 8008382: f021 0130 bic.w r1, r1, #48 @ 0x30 8008386: 4301 orrs r1, r0 8008388: 64f9 str r1, [r7, #76] @ 0x4c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800838a: 04df lsls r7, r3, #19 800838c: d526 bpl.n 80083dc switch (PeriphClkInit->Spi123ClockSelection) 800838e: 6e21 ldr r1, [r4, #96] @ 0x60 8008390: f5b1 5f00 cmp.w r1, #8192 @ 0x2000 8008394: f000 855c beq.w 8008e50 8008398: f200 80b2 bhi.w 8008500 800839c: 2900 cmp r1, #0 800839e: f000 83d0 beq.w 8008b42 80083a2: f5b1 5f80 cmp.w r1, #4096 @ 0x1000 80083a6: f040 80b3 bne.w 8008510 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80083aa: 4946 ldr r1, [pc, #280] @ (80084c4 ) 80083ac: 6a89 ldr r1, [r1, #40] @ 0x28 80083ae: f001 0103 and.w r1, r1, #3 80083b2: 2903 cmp r1, #3 80083b4: f000 80ac beq.w 8008510 80083b8: 2100 movs r1, #0 80083ba: f104 0008 add.w r0, r4, #8 80083be: f7ff fe2b bl 8008018 80083c2: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 80083c4: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 80083c8: 2d00 cmp r5, #0 80083ca: f040 847e bne.w 8008cca __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 80083ce: 4f3d ldr r7, [pc, #244] @ (80084c4 ) 80083d0: 6e20 ldr r0, [r4, #96] @ 0x60 80083d2: 6d39 ldr r1, [r7, #80] @ 0x50 80083d4: f421 41e0 bic.w r1, r1, #28672 @ 0x7000 80083d8: 4301 orrs r1, r0 80083da: 6539 str r1, [r7, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 80083dc: 0498 lsls r0, r3, #18 80083de: d524 bpl.n 800842a switch (PeriphClkInit->Spi45ClockSelection) 80083e0: 6e61 ldr r1, [r4, #100] @ 0x64 80083e2: f5b1 3f00 cmp.w r1, #131072 @ 0x20000 80083e6: f000 850c beq.w 8008e02 80083ea: f200 8094 bhi.w 8008516 80083ee: b191 cbz r1, 8008416 80083f0: f5b1 3f80 cmp.w r1, #65536 @ 0x10000 80083f4: f040 8099 bne.w 800852a if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80083f8: 4932 ldr r1, [pc, #200] @ (80084c4 ) 80083fa: 6a89 ldr r1, [r1, #40] @ 0x28 80083fc: f001 0103 and.w r1, r1, #3 8008400: 2903 cmp r1, #3 8008402: f000 8092 beq.w 800852a 8008406: 2101 movs r1, #1 8008408: f104 0008 add.w r0, r4, #8 800840c: f7ff fe04 bl 8008018 8008410: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 8008412: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008416: 2d00 cmp r5, #0 8008418: f040 846c bne.w 8008cf4 __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800841c: 4f29 ldr r7, [pc, #164] @ (80084c4 ) 800841e: 6e60 ldr r0, [r4, #100] @ 0x64 8008420: 6d39 ldr r1, [r7, #80] @ 0x50 8008422: f421 21e0 bic.w r1, r1, #458752 @ 0x70000 8008426: 4301 orrs r1, r0 8008428: 6539 str r1, [r7, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800842a: 0459 lsls r1, r3, #17 800842c: d523 bpl.n 8008476 switch (PeriphClkInit->Spi6ClockSelection) 800842e: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0 8008432: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000 8008436: f000 84ac beq.w 8008d92 800843a: d879 bhi.n 8008530 800843c: b181 cbz r1, 8008460 800843e: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000 8008442: d17d bne.n 8008540 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008444: 491f ldr r1, [pc, #124] @ (80084c4 ) 8008446: 6a89 ldr r1, [r1, #40] @ 0x28 8008448: f001 0103 and.w r1, r1, #3 800844c: 2903 cmp r1, #3 800844e: d077 beq.n 8008540 8008450: 2101 movs r1, #1 8008452: f104 0008 add.w r0, r4, #8 8008456: f7ff fddf bl 8008018 800845a: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800845c: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008460: 2d00 cmp r5, #0 8008462: f040 8455 bne.w 8008d10 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 8008466: 4f17 ldr r7, [pc, #92] @ (80084c4 ) 8008468: f8d4 00b0 ldr.w r0, [r4, #176] @ 0xb0 800846c: 6db9 ldr r1, [r7, #88] @ 0x58 800846e: f021 41e0 bic.w r1, r1, #1879048192 @ 0x70000000 8008472: 4301 orrs r1, r0 8008474: 65b9 str r1, [r7, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8008476: 041f lsls r7, r3, #16 8008478: d50d bpl.n 8008496 switch (PeriphClkInit->FdcanClockSelection) 800847a: 6f21 ldr r1, [r4, #112] @ 0x70 800847c: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000 8008480: f000 82d2 beq.w 8008a28 8008484: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000 8008488: f000 83e4 beq.w 8008c54 800848c: 2900 cmp r1, #0 800848e: f000 82d0 beq.w 8008a32 8008492: 2601 movs r6, #1 8008494: 4635 mov r5, r6 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 8008496: 01d8 lsls r0, r3, #7 8008498: d55e bpl.n 8008558 switch (PeriphClkInit->FmcClockSelection) 800849a: 6ca1 ldr r1, [r4, #72] @ 0x48 800849c: 2903 cmp r1, #3 800849e: f200 85c1 bhi.w 8009024 80084a2: e8df f011 tbh [pc, r1, lsl #1] 80084a6: 0055 .short 0x0055 80084a8: 04630050 .word 0x04630050 80084ac: 0055 .short 0x0055 switch (PeriphClkInit->Sai23ClockSelection) 80084ae: 29c0 cmp r1, #192 @ 0xc0 80084b0: f43f aef0 beq.w 8008294 80084b4: f5b1 7f80 cmp.w r1, #256 @ 0x100 80084b8: f43f aeec beq.w 8008294 80084bc: 2601 movs r6, #1 80084be: 4635 mov r5, r6 80084c0: e6f2 b.n 80082a8 80084c2: bf00 nop 80084c4: 58024400 .word 0x58024400 switch (PeriphClkInit->Sai4AClockSelection) 80084c8: f5b1 0fc0 cmp.w r1, #6291456 @ 0x600000 80084cc: f43f af0c beq.w 80082e8 80084d0: f5b1 0f00 cmp.w r1, #8388608 @ 0x800000 80084d4: f43f af08 beq.w 80082e8 80084d8: 2601 movs r6, #1 80084da: 4635 mov r5, r6 80084dc: e70f b.n 80082fe switch (PeriphClkInit->Sai4BClockSelection) 80084de: f1b1 7f40 cmp.w r1, #50331648 @ 0x3000000 80084e2: f43f af2c beq.w 800833e 80084e6: f1b1 6f80 cmp.w r1, #67108864 @ 0x4000000 80084ea: f43f af28 beq.w 800833e 80084ee: 2601 movs r6, #1 80084f0: 4635 mov r5, r6 80084f2: e72f b.n 8008354 switch (PeriphClkInit->QspiClockSelection) 80084f4: 2930 cmp r1, #48 @ 0x30 80084f6: f43f af3e beq.w 8008376 80084fa: 2601 movs r6, #1 80084fc: 4635 mov r5, r6 80084fe: e744 b.n 800838a switch (PeriphClkInit->Spi123ClockSelection) 8008500: f5b1 5f40 cmp.w r1, #12288 @ 0x3000 8008504: f43f af60 beq.w 80083c8 8008508: f5b1 4f80 cmp.w r1, #16384 @ 0x4000 800850c: f43f af5c beq.w 80083c8 8008510: 2601 movs r6, #1 8008512: 4635 mov r5, r6 8008514: e762 b.n 80083dc switch (PeriphClkInit->Spi45ClockSelection) 8008516: f421 3080 bic.w r0, r1, #65536 @ 0x10000 800851a: f5b0 2f80 cmp.w r0, #262144 @ 0x40000 800851e: f43f af7a beq.w 8008416 8008522: f5b1 3f40 cmp.w r1, #196608 @ 0x30000 8008526: f43f af76 beq.w 8008416 800852a: 2601 movs r6, #1 800852c: 4635 mov r5, r6 800852e: e77c b.n 800842a switch (PeriphClkInit->Spi6ClockSelection) 8008530: f021 5080 bic.w r0, r1, #268435456 @ 0x10000000 8008534: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000 8008538: d092 beq.n 8008460 800853a: f1b1 5f40 cmp.w r1, #805306368 @ 0x30000000 800853e: d08f beq.n 8008460 8008540: 2601 movs r6, #1 8008542: 4635 mov r5, r6 8008544: e797 b.n 8008476 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008546: 4837 ldr r0, [pc, #220] @ (8008624 ) 8008548: 6ac1 ldr r1, [r0, #44] @ 0x2c 800854a: f441 3100 orr.w r1, r1, #131072 @ 0x20000 800854e: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008550: 2d00 cmp r5, #0 8008552: f000 83a6 beq.w 8008ca2 8008556: 462e mov r6, r5 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8008558: 0259 lsls r1, r3, #9 800855a: f100 82b0 bmi.w 8008abe if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800855e: 07d8 lsls r0, r3, #31 8008560: d52f bpl.n 80085c2 switch (PeriphClkInit->Usart16ClockSelection) 8008562: 6fe1 ldr r1, [r4, #124] @ 0x7c 8008564: 2928 cmp r1, #40 @ 0x28 8008566: d82a bhi.n 80085be 8008568: e8df f011 tbh [pc, r1, lsl #1] 800856c: 0029029b .word 0x0029029b 8008570: 00290029 .word 0x00290029 8008574: 00290029 .word 0x00290029 8008578: 00290029 .word 0x00290029 800857c: 0029028c .word 0x0029028c 8008580: 00290029 .word 0x00290029 8008584: 00290029 .word 0x00290029 8008588: 00290029 .word 0x00290029 800858c: 00290521 .word 0x00290521 8008590: 00290029 .word 0x00290029 8008594: 00290029 .word 0x00290029 8008598: 00290029 .word 0x00290029 800859c: 0029029b .word 0x0029029b 80085a0: 00290029 .word 0x00290029 80085a4: 00290029 .word 0x00290029 80085a8: 00290029 .word 0x00290029 80085ac: 0029029b .word 0x0029029b 80085b0: 00290029 .word 0x00290029 80085b4: 00290029 .word 0x00290029 80085b8: 00290029 .word 0x00290029 80085bc: 029b .short 0x029b 80085be: 2601 movs r6, #1 80085c0: 4635 mov r5, r6 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 80085c2: 0799 lsls r1, r3, #30 80085c4: d51e bpl.n 8008604 switch (PeriphClkInit->Usart234578ClockSelection) 80085c6: 6fa1 ldr r1, [r4, #120] @ 0x78 80085c8: 2905 cmp r1, #5 80085ca: f200 8510 bhi.w 8008fee 80085ce: e8df f011 tbh [pc, r1, lsl #1] 80085d2: 0015 .short 0x0015 80085d4: 04ca0006 .word 0x04ca0006 80085d8: 00150015 .word 0x00150015 80085dc: 0015 .short 0x0015 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80085de: 4911 ldr r1, [pc, #68] @ (8008624 ) 80085e0: 6a89 ldr r1, [r1, #40] @ 0x28 80085e2: f001 0103 and.w r1, r1, #3 80085e6: 2903 cmp r1, #3 80085e8: f000 8501 beq.w 8008fee 80085ec: 2101 movs r1, #1 80085ee: f104 0008 add.w r0, r4, #8 80085f2: f7ff fd11 bl 8008018 80085f6: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 80085f8: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 80085fc: 2d00 cmp r5, #0 80085fe: f000 836f beq.w 8008ce0 8008602: 462e mov r6, r5 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8008604: 075f lsls r7, r3, #29 8008606: d522 bpl.n 800864e switch (PeriphClkInit->Lpuart1ClockSelection) 8008608: f8d4 1094 ldr.w r1, [r4, #148] @ 0x94 800860c: 2905 cmp r1, #5 800860e: f200 84f2 bhi.w 8008ff6 8008612: e8df f011 tbh [pc, r1, lsl #1] 8008616: 0018 .short 0x0018 8008618: 04ba0009 .word 0x04ba0009 800861c: 00180018 .word 0x00180018 8008620: 0018 .short 0x0018 8008622: bf00 nop 8008624: 58024400 .word 0x58024400 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008628: 49b0 ldr r1, [pc, #704] @ (80088ec ) 800862a: 6a89 ldr r1, [r1, #40] @ 0x28 800862c: f001 0103 and.w r1, r1, #3 8008630: 2903 cmp r1, #3 8008632: f000 84e0 beq.w 8008ff6 8008636: 2101 movs r1, #1 8008638: f104 0008 add.w r0, r4, #8 800863c: f7ff fcec bl 8008018 8008640: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8008642: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008646: 2d00 cmp r5, #0 8008648: f000 8357 beq.w 8008cfa 800864c: 462e mov r6, r5 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800864e: 0698 lsls r0, r3, #26 8008650: d526 bpl.n 80086a0 switch (PeriphClkInit->Lptim1ClockSelection) 8008652: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90 8008656: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000 800865a: f000 83ad beq.w 8008db8 800865e: f200 8182 bhi.w 8008966 8008662: b191 cbz r1, 800868a 8008664: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000 8008668: f040 8187 bne.w 800897a if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800866c: 499f ldr r1, [pc, #636] @ (80088ec ) 800866e: 6a89 ldr r1, [r1, #40] @ 0x28 8008670: f001 0103 and.w r1, r1, #3 8008674: 2903 cmp r1, #3 8008676: f000 8180 beq.w 800897a 800867a: 2100 movs r1, #0 800867c: f104 0008 add.w r0, r4, #8 8008680: f7ff fcca bl 8008018 8008684: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 8008686: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 800868a: 2d00 cmp r5, #0 800868c: f040 8345 bne.w 8008d1a __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 8008690: 4f96 ldr r7, [pc, #600] @ (80088ec ) 8008692: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90 8008696: 6d79 ldr r1, [r7, #84] @ 0x54 8008698: f021 41e0 bic.w r1, r1, #1879048192 @ 0x70000000 800869c: 4301 orrs r1, r0 800869e: 6579 str r1, [r7, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 80086a0: 0659 lsls r1, r3, #25 80086a2: d526 bpl.n 80086f2 switch (PeriphClkInit->Lptim2ClockSelection) 80086a4: f8d4 109c ldr.w r1, [r4, #156] @ 0x9c 80086a8: f5b1 6f00 cmp.w r1, #2048 @ 0x800 80086ac: f000 8396 beq.w 8008ddc 80086b0: f200 8166 bhi.w 8008980 80086b4: b191 cbz r1, 80086dc 80086b6: f5b1 6f80 cmp.w r1, #1024 @ 0x400 80086ba: f040 816b bne.w 8008994 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80086be: 498b ldr r1, [pc, #556] @ (80088ec ) 80086c0: 6a89 ldr r1, [r1, #40] @ 0x28 80086c2: f001 0103 and.w r1, r1, #3 80086c6: 2903 cmp r1, #3 80086c8: f000 8164 beq.w 8008994 80086cc: 2100 movs r1, #0 80086ce: f104 0008 add.w r0, r4, #8 80086d2: f7ff fca1 bl 8008018 80086d6: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 80086d8: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 80086dc: 2d00 cmp r5, #0 80086de: f040 8307 bne.w 8008cf0 __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 80086e2: 4f82 ldr r7, [pc, #520] @ (80088ec ) 80086e4: f8d4 009c ldr.w r0, [r4, #156] @ 0x9c 80086e8: 6db9 ldr r1, [r7, #88] @ 0x58 80086ea: f421 51e0 bic.w r1, r1, #7168 @ 0x1c00 80086ee: 4301 orrs r1, r0 80086f0: 65b9 str r1, [r7, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 80086f2: 061f lsls r7, r3, #24 80086f4: d526 bpl.n 8008744 switch (PeriphClkInit->Lptim345ClockSelection) 80086f6: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0 80086fa: f5b1 4f80 cmp.w r1, #16384 @ 0x4000 80086fe: f000 8394 beq.w 8008e2a 8008702: f200 814a bhi.w 800899a 8008706: b191 cbz r1, 800872e 8008708: f5b1 5f00 cmp.w r1, #8192 @ 0x2000 800870c: f040 814f bne.w 80089ae if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008710: 4976 ldr r1, [pc, #472] @ (80088ec ) 8008712: 6a89 ldr r1, [r1, #40] @ 0x28 8008714: f001 0103 and.w r1, r1, #3 8008718: 2903 cmp r1, #3 800871a: f000 8148 beq.w 80089ae 800871e: 2100 movs r1, #0 8008720: f104 0008 add.w r0, r4, #8 8008724: f7ff fc78 bl 8008018 8008728: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800872a: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 800872e: 2d00 cmp r5, #0 8008730: f040 82ec bne.w 8008d0c __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 8008734: 4f6d ldr r7, [pc, #436] @ (80088ec ) 8008736: f8d4 00a0 ldr.w r0, [r4, #160] @ 0xa0 800873a: 6db9 ldr r1, [r7, #88] @ 0x58 800873c: f421 4160 bic.w r1, r1, #57344 @ 0xe000 8008740: 4301 orrs r1, r0 8008742: 65b9 str r1, [r7, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 8008744: 0718 lsls r0, r3, #28 8008746: d50b bpl.n 8008760 if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 8008748: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84 800874c: f5b0 5f80 cmp.w r0, #4096 @ 0x1000 8008750: f000 8255 beq.w 8008bfe __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 8008754: 4f65 ldr r7, [pc, #404] @ (80088ec ) 8008756: 6d79 ldr r1, [r7, #84] @ 0x54 8008758: f421 5140 bic.w r1, r1, #12288 @ 0x3000 800875c: 4301 orrs r1, r0 800875e: 6579 str r1, [r7, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 8008760: 06d9 lsls r1, r3, #27 8008762: d50b bpl.n 800877c if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 8008764: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98 8008768: f5b0 7f80 cmp.w r0, #256 @ 0x100 800876c: f000 8233 beq.w 8008bd6 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8008770: 4f5e ldr r7, [pc, #376] @ (80088ec ) 8008772: 6db9 ldr r1, [r7, #88] @ 0x58 8008774: f421 7140 bic.w r1, r1, #768 @ 0x300 8008778: 4301 orrs r1, r0 800877a: 65b9 str r1, [r7, #88] @ 0x58 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800877c: 031f lsls r7, r3, #12 800877e: d50e bpl.n 800879e switch (PeriphClkInit->AdcClockSelection) 8008780: f8d4 10a4 ldr.w r1, [r4, #164] @ 0xa4 8008784: f5b1 3f80 cmp.w r1, #65536 @ 0x10000 8008788: f000 815e beq.w 8008a48 800878c: f5b1 3f00 cmp.w r1, #131072 @ 0x20000 8008790: f000 8169 beq.w 8008a66 8008794: 2900 cmp r1, #0 8008796: f000 826e beq.w 8008c76 800879a: 2601 movs r6, #1 800879c: 4635 mov r5, r6 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800879e: 0358 lsls r0, r3, #13 80087a0: d50f bpl.n 80087c2 switch (PeriphClkInit->UsbClockSelection) 80087a2: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88 80087a6: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000 80087aa: f000 82cd beq.w 8008d48 80087ae: f5b1 1f40 cmp.w r1, #3145728 @ 0x300000 80087b2: f000 812d beq.w 8008a10 80087b6: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 80087ba: f000 8124 beq.w 8008a06 80087be: 2601 movs r6, #1 80087c0: 4635 mov r5, r6 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 80087c2: 03d9 lsls r1, r3, #15 80087c4: d520 bpl.n 8008808 switch (PeriphClkInit->SdmmcClockSelection) 80087c6: 6d21 ldr r1, [r4, #80] @ 0x50 80087c8: 2900 cmp r1, #0 80087ca: f000 8236 beq.w 8008c3a 80087ce: f5b1 3f80 cmp.w r1, #65536 @ 0x10000 80087d2: f040 8113 bne.w 80089fc if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80087d6: 4945 ldr r1, [pc, #276] @ (80088ec ) 80087d8: 6a89 ldr r1, [r1, #40] @ 0x28 80087da: f001 0103 and.w r1, r1, #3 80087de: 2903 cmp r1, #3 80087e0: f000 810c beq.w 80089fc 80087e4: 2102 movs r1, #2 80087e6: f104 0008 add.w r0, r4, #8 80087ea: f7ff fc15 bl 8008018 80087ee: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 80087f0: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 80087f4: 2d00 cmp r5, #0 80087f6: f040 8228 bne.w 8008c4a __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 80087fa: 4f3c ldr r7, [pc, #240] @ (80088ec ) 80087fc: 6d20 ldr r0, [r4, #80] @ 0x50 80087fe: 6cf9 ldr r1, [r7, #76] @ 0x4c 8008800: f421 3180 bic.w r1, r1, #65536 @ 0x10000 8008804: 4301 orrs r1, r0 8008806: 64f9 str r1, [r7, #76] @ 0x4c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8008808: 039f lsls r7, r3, #14 800880a: f140 80df bpl.w 80089cc switch (PeriphClkInit->RngClockSelection) 800880e: f8d4 1080 ldr.w r1, [r4, #128] @ 0x80 8008812: f5b1 7f80 cmp.w r1, #256 @ 0x100 8008816: f000 8207 beq.w 8008c28 800881a: f240 80cb bls.w 80089b4 800881e: f421 7080 bic.w r0, r1, #256 @ 0x100 8008822: f5b0 7f00 cmp.w r0, #512 @ 0x200 8008826: f000 80c8 beq.w 80089ba 800882a: 2501 movs r5, #1 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800882c: 02d8 lsls r0, r3, #11 800882e: d506 bpl.n 800883e __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 8008830: 482e ldr r0, [pc, #184] @ (80088ec ) 8008832: 6f66 ldr r6, [r4, #116] @ 0x74 8008834: 6d01 ldr r1, [r0, #80] @ 0x50 8008836: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000 800883a: 4331 orrs r1, r6 800883c: 6501 str r1, [r0, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800883e: 00d9 lsls r1, r3, #3 8008840: d507 bpl.n 8008852 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 8008842: 482a ldr r0, [pc, #168] @ (80088ec ) 8008844: f8d4 60b8 ldr.w r6, [r4, #184] @ 0xb8 8008848: 6901 ldr r1, [r0, #16] 800884a: f421 4180 bic.w r1, r1, #16384 @ 0x4000 800884e: 4331 orrs r1, r6 8008850: 6101 str r1, [r0, #16] if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 8008852: 029f lsls r7, r3, #10 8008854: d506 bpl.n 8008864 __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 8008856: 4825 ldr r0, [pc, #148] @ (80088ec ) 8008858: 6ee6 ldr r6, [r4, #108] @ 0x6c 800885a: 6d01 ldr r1, [r0, #80] @ 0x50 800885c: f021 7180 bic.w r1, r1, #16777216 @ 0x1000000 8008860: 4331 orrs r1, r6 8008862: 6501 str r1, [r0, #80] @ 0x50 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 8008864: 005e lsls r6, r3, #1 8008866: d509 bpl.n 800887c __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8008868: 4920 ldr r1, [pc, #128] @ (80088ec ) 800886a: 6908 ldr r0, [r1, #16] 800886c: f420 4000 bic.w r0, r0, #32768 @ 0x8000 8008870: 6108 str r0, [r1, #16] 8008872: 6908 ldr r0, [r1, #16] 8008874: f8d4 60bc ldr.w r6, [r4, #188] @ 0xbc 8008878: 4330 orrs r0, r6 800887a: 6108 str r0, [r1, #16] if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800887c: 2b00 cmp r3, #0 800887e: da06 bge.n 800888e __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 8008880: 481a ldr r0, [pc, #104] @ (80088ec ) 8008882: 6d66 ldr r6, [r4, #84] @ 0x54 8008884: 6cc1 ldr r1, [r0, #76] @ 0x4c 8008886: f021 5140 bic.w r1, r1, #805306368 @ 0x30000000 800888a: 4331 orrs r1, r6 800888c: 64c1 str r1, [r0, #76] @ 0x4c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800888e: 0218 lsls r0, r3, #8 8008890: d507 bpl.n 80088a2 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 8008892: 4916 ldr r1, [pc, #88] @ (80088ec ) 8008894: f8d4 008c ldr.w r0, [r4, #140] @ 0x8c 8008898: 6d4b ldr r3, [r1, #84] @ 0x54 800889a: f423 0340 bic.w r3, r3, #12582912 @ 0xc00000 800889e: 4303 orrs r3, r0 80088a0: 654b str r3, [r1, #84] @ 0x54 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 80088a2: 07d1 lsls r1, r2, #31 80088a4: d50f bpl.n 80088c6 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80088a6: 4b11 ldr r3, [pc, #68] @ (80088ec ) 80088a8: 6a9b ldr r3, [r3, #40] @ 0x28 80088aa: f003 0303 and.w r3, r3, #3 80088ae: 2b03 cmp r3, #3 80088b0: f000 8184 beq.w 8008bbc 80088b4: 2100 movs r1, #0 80088b6: f104 0008 add.w r0, r4, #8 80088ba: f7ff fbad bl 8008018 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 80088be: 6862 ldr r2, [r4, #4] if (ret == HAL_OK) 80088c0: 2800 cmp r0, #0 80088c2: f040 8205 bne.w 8008cd0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 80088c6: 0793 lsls r3, r2, #30 80088c8: d512 bpl.n 80088f0 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80088ca: 4b08 ldr r3, [pc, #32] @ (80088ec ) 80088cc: 6a9b ldr r3, [r3, #40] @ 0x28 80088ce: f003 0303 and.w r3, r3, #3 80088d2: 2b03 cmp r3, #3 80088d4: f000 8170 beq.w 8008bb8 80088d8: 2101 movs r1, #1 80088da: f104 0008 add.w r0, r4, #8 80088de: f7ff fb9b bl 8008018 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 80088e2: 6862 ldr r2, [r4, #4] if (ret == HAL_OK) 80088e4: 2800 cmp r0, #0 80088e6: f040 81f5 bne.w 8008cd4 80088ea: e001 b.n 80088f0 80088ec: 58024400 .word 0x58024400 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 80088f0: 0757 lsls r7, r2, #29 80088f2: d50f bpl.n 8008914 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80088f4: 4bb2 ldr r3, [pc, #712] @ (8008bc0 ) 80088f6: 6a9b ldr r3, [r3, #40] @ 0x28 80088f8: f003 0303 and.w r3, r3, #3 80088fc: 2b03 cmp r3, #3 80088fe: f000 8168 beq.w 8008bd2 8008902: 2102 movs r1, #2 8008904: f104 0008 add.w r0, r4, #8 8008908: f7ff fb86 bl 8008018 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800890c: 6862 ldr r2, [r4, #4] if (ret == HAL_OK) 800890e: 2800 cmp r0, #0 8008910: f040 81e2 bne.w 8008cd8 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 8008914: 0716 lsls r6, r2, #28 8008916: d50f bpl.n 8008938 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008918: 4ba9 ldr r3, [pc, #676] @ (8008bc0 ) 800891a: 6a9b ldr r3, [r3, #40] @ 0x28 800891c: f003 0303 and.w r3, r3, #3 8008920: 2b03 cmp r3, #3 8008922: f000 8147 beq.w 8008bb4 8008926: 2100 movs r1, #0 8008928: f104 0028 add.w r0, r4, #40 @ 0x28 800892c: f7ff fbe6 bl 80080fc if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 8008930: 6862 ldr r2, [r4, #4] if (ret == HAL_OK) 8008932: 2800 cmp r0, #0 8008934: f040 81d2 bne.w 8008cdc if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 8008938: 06d0 lsls r0, r2, #27 800893a: d54a bpl.n 80089d2 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800893c: 4ba0 ldr r3, [pc, #640] @ (8008bc0 ) ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800893e: f104 0628 add.w r6, r4, #40 @ 0x28 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008942: 6a9b ldr r3, [r3, #40] @ 0x28 8008944: f003 0303 and.w r3, r3, #3 8008948: 2b03 cmp r3, #3 800894a: f000 813d beq.w 8008bc8 800894e: 2101 movs r1, #1 8008950: 4630 mov r0, r6 8008952: f7ff fbd3 bl 80080fc if (ret == HAL_OK) 8008956: 2800 cmp r0, #0 8008958: d03a beq.n 80089d0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800895a: 6863 ldr r3, [r4, #4] 800895c: 069a lsls r2, r3, #26 800895e: f140 808e bpl.w 8008a7e 8008962: 4605 mov r5, r0 8008964: e039 b.n 80089da switch (PeriphClkInit->Lptim1ClockSelection) 8008966: f021 5080 bic.w r0, r1, #268435456 @ 0x10000000 800896a: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000 800896e: f43f ae8c beq.w 800868a 8008972: f1b1 5f40 cmp.w r1, #805306368 @ 0x30000000 8008976: f43f ae88 beq.w 800868a 800897a: 2601 movs r6, #1 800897c: 4635 mov r5, r6 800897e: e68f b.n 80086a0 switch (PeriphClkInit->Lptim2ClockSelection) 8008980: f421 6080 bic.w r0, r1, #1024 @ 0x400 8008984: f5b0 5f80 cmp.w r0, #4096 @ 0x1000 8008988: f43f aea8 beq.w 80086dc 800898c: f5b1 6f40 cmp.w r1, #3072 @ 0xc00 8008990: f43f aea4 beq.w 80086dc 8008994: 2601 movs r6, #1 8008996: 4635 mov r5, r6 8008998: e6ab b.n 80086f2 switch (PeriphClkInit->Lptim345ClockSelection) 800899a: f421 5000 bic.w r0, r1, #8192 @ 0x2000 800899e: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 80089a2: f43f aec4 beq.w 800872e 80089a6: f5b1 4fc0 cmp.w r1, #24576 @ 0x6000 80089aa: f43f aec0 beq.w 800872e 80089ae: 2601 movs r6, #1 80089b0: 4635 mov r5, r6 80089b2: e6c7 b.n 8008744 switch (PeriphClkInit->RngClockSelection) 80089b4: 2900 cmp r1, #0 80089b6: f47f af38 bne.w 800882a if (ret == HAL_OK) 80089ba: 2d00 cmp r5, #0 80089bc: f47f af36 bne.w 800882c __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 80089c0: 4d7f ldr r5, [pc, #508] @ (8008bc0 ) 80089c2: 6d68 ldr r0, [r5, #84] @ 0x54 80089c4: f420 7040 bic.w r0, r0, #768 @ 0x300 80089c8: 4301 orrs r1, r0 80089ca: 6569 str r1, [r5, #84] @ 0x54 switch (PeriphClkInit->SdmmcClockSelection) 80089cc: 4635 mov r5, r6 80089ce: e72d b.n 800882c if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 80089d0: 6862 ldr r2, [r4, #4] 80089d2: 0693 lsls r3, r2, #26 80089d4: d50d bpl.n 80089f2 ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 80089d6: f104 0628 add.w r6, r4, #40 @ 0x28 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 80089da: 4b79 ldr r3, [pc, #484] @ (8008bc0 ) 80089dc: 6a9b ldr r3, [r3, #40] @ 0x28 80089de: f003 0303 and.w r3, r3, #3 80089e2: 2b03 cmp r3, #3 80089e4: d04b beq.n 8008a7e 80089e6: 2102 movs r1, #2 80089e8: 4630 mov r0, r6 80089ea: f7ff fb87 bl 80080fc if (ret == HAL_OK) 80089ee: 2800 cmp r0, #0 80089f0: d145 bne.n 8008a7e if (status == HAL_OK) 80089f2: 1e28 subs r0, r5, #0 80089f4: bf18 it ne 80089f6: 2001 movne r0, #1 } 80089f8: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 80089fc: 2601 movs r6, #1 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 80089fe: 039f lsls r7, r3, #14 8008a00: 4635 mov r5, r6 8008a02: d5e3 bpl.n 80089cc 8008a04: e703 b.n 800880e __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008a06: 486e ldr r0, [pc, #440] @ (8008bc0 ) 8008a08: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008a0a: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008a0e: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008a10: 2d00 cmp r5, #0 8008a12: f040 8144 bne.w 8008c9e __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8008a16: 4f6a ldr r7, [pc, #424] @ (8008bc0 ) 8008a18: f8d4 0088 ldr.w r0, [r4, #136] @ 0x88 8008a1c: 6d79 ldr r1, [r7, #84] @ 0x54 8008a1e: f421 1140 bic.w r1, r1, #3145728 @ 0x300000 8008a22: 4301 orrs r1, r0 8008a24: 6579 str r1, [r7, #84] @ 0x54 8008a26: e6cc b.n 80087c2 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008a28: 4865 ldr r0, [pc, #404] @ (8008bc0 ) 8008a2a: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008a2c: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008a30: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008a32: 2d00 cmp r5, #0 8008a34: f040 8130 bne.w 8008c98 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8008a38: 4f61 ldr r7, [pc, #388] @ (8008bc0 ) 8008a3a: 6f20 ldr r0, [r4, #112] @ 0x70 8008a3c: 6d39 ldr r1, [r7, #80] @ 0x50 8008a3e: f021 5140 bic.w r1, r1, #805306368 @ 0x30000000 8008a42: 4301 orrs r1, r0 8008a44: 6539 str r1, [r7, #80] @ 0x50 8008a46: e526 b.n 8008496 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008a48: 495d ldr r1, [pc, #372] @ (8008bc0 ) 8008a4a: 6a89 ldr r1, [r1, #40] @ 0x28 8008a4c: f001 0103 and.w r1, r1, #3 8008a50: 2903 cmp r1, #3 8008a52: f43f aea2 beq.w 800879a 8008a56: 2102 movs r1, #2 8008a58: f104 0028 add.w r0, r4, #40 @ 0x28 8008a5c: f7ff fb4e bl 80080fc 8008a60: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8008a62: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008a66: 2d00 cmp r5, #0 8008a68: f040 8155 bne.w 8008d16 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8008a6c: 4f54 ldr r7, [pc, #336] @ (8008bc0 ) 8008a6e: f8d4 00a4 ldr.w r0, [r4, #164] @ 0xa4 8008a72: 6db9 ldr r1, [r7, #88] @ 0x58 8008a74: f421 3140 bic.w r1, r1, #196608 @ 0x30000 8008a78: 4301 orrs r1, r0 8008a7a: 65b9 str r1, [r7, #88] @ 0x58 8008a7c: e68f b.n 800879e return HAL_ERROR; 8008a7e: 2001 movs r0, #1 } 8008a80: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008a84: 494e ldr r1, [pc, #312] @ (8008bc0 ) 8008a86: 6a89 ldr r1, [r1, #40] @ 0x28 8008a88: f001 0103 and.w r1, r1, #3 8008a8c: 2903 cmp r1, #3 8008a8e: f43f ad96 beq.w 80085be 8008a92: 2101 movs r1, #1 8008a94: f104 0008 add.w r0, r4, #8 8008a98: f7ff fabe bl 8008018 8008a9c: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8008a9e: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008aa2: 2d00 cmp r5, #0 8008aa4: f040 813b bne.w 8008d1e __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 8008aa8: 4f45 ldr r7, [pc, #276] @ (8008bc0 ) 8008aaa: 6fe0 ldr r0, [r4, #124] @ 0x7c 8008aac: 6d79 ldr r1, [r7, #84] @ 0x54 8008aae: f021 0138 bic.w r1, r1, #56 @ 0x38 8008ab2: 4301 orrs r1, r0 8008ab4: 6579 str r1, [r7, #84] @ 0x54 8008ab6: e584 b.n 80085c2 8008ab8: 2601 movs r6, #1 8008aba: f7ff bbc0 b.w 800823e SET_BIT(PWR->CR1, PWR_CR1_DBP); 8008abe: 4f41 ldr r7, [pc, #260] @ (8008bc4 ) 8008ac0: 683b ldr r3, [r7, #0] 8008ac2: f443 7380 orr.w r3, r3, #256 @ 0x100 8008ac6: 603b str r3, [r7, #0] tickstart = HAL_GetTick(); 8008ac8: f7fb fa82 bl 8003fd0 8008acc: 4680 mov r8, r0 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8008ace: e006 b.n 8008ade if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8008ad0: f7fb fa7e bl 8003fd0 8008ad4: eba0 0008 sub.w r0, r0, r8 8008ad8: 2864 cmp r0, #100 @ 0x64 8008ada: f200 827b bhi.w 8008fd4 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8008ade: 683b ldr r3, [r7, #0] 8008ae0: 05da lsls r2, r3, #23 8008ae2: d5f5 bpl.n 8008ad0 if (ret == HAL_OK) 8008ae4: 2d00 cmp r5, #0 8008ae6: f040 8276 bne.w 8008fd6 if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 8008aea: 4a35 ldr r2, [pc, #212] @ (8008bc0 ) 8008aec: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4 8008af0: 6f11 ldr r1, [r2, #112] @ 0x70 8008af2: 4059 eors r1, r3 8008af4: f411 7f40 tst.w r1, #768 @ 0x300 8008af8: d00b beq.n 8008b12 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8008afa: 6f11 ldr r1, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_FORCE(); 8008afc: 6f10 ldr r0, [r2, #112] @ 0x70 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8008afe: f421 7140 bic.w r1, r1, #768 @ 0x300 __HAL_RCC_BACKUPRESET_FORCE(); 8008b02: f440 3080 orr.w r0, r0, #65536 @ 0x10000 8008b06: 6710 str r0, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 8008b08: 6f10 ldr r0, [r2, #112] @ 0x70 8008b0a: f420 3080 bic.w r0, r0, #65536 @ 0x10000 8008b0e: 6710 str r0, [r2, #112] @ 0x70 RCC->BDCR = tmpreg; 8008b10: 6711 str r1, [r2, #112] @ 0x70 if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 8008b12: f5b3 7f80 cmp.w r3, #256 @ 0x100 8008b16: f000 8289 beq.w 800902c __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8008b1a: f403 7240 and.w r2, r3, #768 @ 0x300 8008b1e: f5b2 7f40 cmp.w r2, #768 @ 0x300 8008b22: f000 8297 beq.w 8009054 8008b26: 4926 ldr r1, [pc, #152] @ (8008bc0 ) 8008b28: 690a ldr r2, [r1, #16] 8008b2a: f422 527c bic.w r2, r2, #16128 @ 0x3f00 8008b2e: 610a str r2, [r1, #16] 8008b30: 4823 ldr r0, [pc, #140] @ (8008bc0 ) 8008b32: f3c3 010b ubfx r1, r3, #0, #12 8008b36: 6f07 ldr r7, [r0, #112] @ 0x70 8008b38: 4339 orrs r1, r7 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 8008b3a: e9d4 3200 ldrd r3, r2, [r4] __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8008b3e: 6701 str r1, [r0, #112] @ 0x70 8008b40: e50d b.n 800855e __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008b42: 481f ldr r0, [pc, #124] @ (8008bc0 ) 8008b44: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008b46: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008b4a: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008b4c: 2d00 cmp r5, #0 8008b4e: f040 80bc bne.w 8008cca 8008b52: e43c b.n 80083ce __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008b54: 481a ldr r0, [pc, #104] @ (8008bc0 ) 8008b56: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008b58: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008b5c: 62c1 str r1, [r0, #44] @ 0x2c break; 8008b5e: 4635 mov r5, r6 if (ret == HAL_OK) 8008b60: 2d00 cmp r5, #0 8008b62: f040 81ed bne.w 8008f40 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8008b66: 4f16 ldr r7, [pc, #88] @ (8008bc0 ) 8008b68: 6da0 ldr r0, [r4, #88] @ 0x58 8008b6a: 6d39 ldr r1, [r7, #80] @ 0x50 8008b6c: f021 0107 bic.w r1, r1, #7 8008b70: 4301 orrs r1, r0 8008b72: 6539 str r1, [r7, #80] @ 0x50 8008b74: f7ff bb71 b.w 800825a __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008b78: 4811 ldr r0, [pc, #68] @ (8008bc0 ) 8008b7a: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008b7c: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008b80: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008b82: 2d00 cmp r5, #0 8008b84: f040 8098 bne.w 8008cb8 8008b88: f7ff bb87 b.w 800829a __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008b8c: 480c ldr r0, [pc, #48] @ (8008bc0 ) 8008b8e: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008b90: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008b94: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008b96: 2d00 cmp r5, #0 8008b98: f040 8091 bne.w 8008cbe 8008b9c: f7ff bba7 b.w 80082ee __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008ba0: 4807 ldr r0, [pc, #28] @ (8008bc0 ) 8008ba2: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008ba4: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008ba8: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008baa: 2d00 cmp r5, #0 8008bac: f040 808a bne.w 8008cc4 8008bb0: f7ff bbc8 b.w 8008344 return HAL_ERROR; 8008bb4: 2501 movs r5, #1 8008bb6: e6bf b.n 8008938 return HAL_ERROR; 8008bb8: 2501 movs r5, #1 8008bba: e699 b.n 80088f0 8008bbc: 2501 movs r5, #1 8008bbe: e682 b.n 80088c6 8008bc0: 58024400 .word 0x58024400 8008bc4: 58024800 .word 0x58024800 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 8008bc8: 0691 lsls r1, r2, #26 8008bca: f57f af58 bpl.w 8008a7e return HAL_ERROR; 8008bce: 2501 movs r5, #1 8008bd0: e703 b.n 80089da return HAL_ERROR; 8008bd2: 2501 movs r5, #1 8008bd4: e69e b.n 8008914 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008bd6: 49bc ldr r1, [pc, #752] @ (8008ec8 ) 8008bd8: 6a89 ldr r1, [r1, #40] @ 0x28 8008bda: f001 0103 and.w r1, r1, #3 8008bde: 2903 cmp r1, #3 8008be0: f000 820d beq.w 8008ffe 8008be4: 2102 movs r1, #2 8008be6: f104 0028 add.w r0, r4, #40 @ 0x28 8008bea: f7ff fa87 bl 80080fc if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 8008bee: 2800 cmp r0, #0 8008bf0: f040 8211 bne.w 8009016 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8008bf4: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8008bf8: e9d4 3200 ldrd r3, r2, [r4] 8008bfc: e5b8 b.n 8008770 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008bfe: 49b2 ldr r1, [pc, #712] @ (8008ec8 ) 8008c00: 6a89 ldr r1, [r1, #40] @ 0x28 8008c02: f001 0103 and.w r1, r1, #3 8008c06: 2903 cmp r1, #3 8008c08: f000 81fc beq.w 8009004 8008c0c: 2102 movs r1, #2 8008c0e: f104 0028 add.w r0, r4, #40 @ 0x28 8008c12: f7ff fa73 bl 80080fc if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 8008c16: 2800 cmp r0, #0 8008c18: f000 81f7 beq.w 800900a __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 8008c1c: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84 status = HAL_ERROR; 8008c20: 2601 movs r6, #1 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 8008c22: e9d4 3200 ldrd r3, r2, [r4] 8008c26: e595 b.n 8008754 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008c28: 4fa7 ldr r7, [pc, #668] @ (8008ec8 ) 8008c2a: 6af8 ldr r0, [r7, #44] @ 0x2c 8008c2c: f440 3000 orr.w r0, r0, #131072 @ 0x20000 8008c30: 62f8 str r0, [r7, #44] @ 0x2c if (ret == HAL_OK) 8008c32: 2d00 cmp r5, #0 8008c34: f47f adfa bne.w 800882c 8008c38: e6c2 b.n 80089c0 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008c3a: 48a3 ldr r0, [pc, #652] @ (8008ec8 ) 8008c3c: 6ac1 ldr r1, [r0, #44] @ 0x2c 8008c3e: f441 3100 orr.w r1, r1, #131072 @ 0x20000 8008c42: 62c1 str r1, [r0, #44] @ 0x2c if (ret == HAL_OK) 8008c44: 2d00 cmp r5, #0 8008c46: f43f add8 beq.w 80087fa if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8008c4a: 039f lsls r7, r3, #14 8008c4c: 462e mov r6, r5 8008c4e: f57f aebd bpl.w 80089cc 8008c52: e5dc b.n 800880e if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008c54: 499c ldr r1, [pc, #624] @ (8008ec8 ) 8008c56: 6a89 ldr r1, [r1, #40] @ 0x28 8008c58: f001 0103 and.w r1, r1, #3 8008c5c: 2903 cmp r1, #3 8008c5e: f43f ac18 beq.w 8008492 8008c62: 2101 movs r1, #1 8008c64: f104 0008 add.w r0, r4, #8 8008c68: f7ff f9d6 bl 8008018 8008c6c: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 8008c6e: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008c72: b98d cbnz r5, 8008c98 8008c74: e6e0 b.n 8008a38 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008c76: 4894 ldr r0, [pc, #592] @ (8008ec8 ) 8008c78: 6a80 ldr r0, [r0, #40] @ 0x28 8008c7a: f000 0003 and.w r0, r0, #3 8008c7e: 2803 cmp r0, #3 8008c80: f43f ad8b beq.w 800879a 8008c84: f104 0008 add.w r0, r4, #8 8008c88: f7ff f9c6 bl 8008018 8008c8c: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8008c8e: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008c92: 2d00 cmp r5, #0 8008c94: d13f bne.n 8008d16 8008c96: e6e9 b.n 8008a6c 8008c98: 462e mov r6, r5 8008c9a: f7ff bbfc b.w 8008496 8008c9e: 462e mov r6, r5 8008ca0: e58f b.n 80087c2 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 8008ca2: 4f89 ldr r7, [pc, #548] @ (8008ec8 ) 8008ca4: 6ca0 ldr r0, [r4, #72] @ 0x48 8008ca6: 6cf9 ldr r1, [r7, #76] @ 0x4c 8008ca8: f021 0103 bic.w r1, r1, #3 8008cac: 4301 orrs r1, r0 8008cae: 64f9 str r1, [r7, #76] @ 0x4c 8008cb0: e452 b.n 8008558 8008cb2: 462e mov r6, r5 8008cb4: f7ff bb69 b.w 800838a 8008cb8: 462e mov r6, r5 8008cba: f7ff baf5 b.w 80082a8 8008cbe: 462e mov r6, r5 8008cc0: f7ff bb1d b.w 80082fe 8008cc4: 462e mov r6, r5 8008cc6: f7ff bb45 b.w 8008354 8008cca: 462e mov r6, r5 8008ccc: f7ff bb86 b.w 80083dc if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 8008cd0: 4605 mov r5, r0 8008cd2: e5f8 b.n 80088c6 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 8008cd4: 4605 mov r5, r0 8008cd6: e60b b.n 80088f0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 8008cd8: 4605 mov r5, r0 8008cda: e61b b.n 8008914 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 8008cdc: 4605 mov r5, r0 8008cde: e62b b.n 8008938 __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 8008ce0: 4f79 ldr r7, [pc, #484] @ (8008ec8 ) 8008ce2: 6fa0 ldr r0, [r4, #120] @ 0x78 8008ce4: 6d79 ldr r1, [r7, #84] @ 0x54 8008ce6: f021 0107 bic.w r1, r1, #7 8008cea: 4301 orrs r1, r0 8008cec: 6579 str r1, [r7, #84] @ 0x54 8008cee: e489 b.n 8008604 8008cf0: 462e mov r6, r5 8008cf2: e4fe b.n 80086f2 8008cf4: 462e mov r6, r5 8008cf6: f7ff bb98 b.w 800842a __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8008cfa: 4f73 ldr r7, [pc, #460] @ (8008ec8 ) 8008cfc: f8d4 0094 ldr.w r0, [r4, #148] @ 0x94 8008d00: 6db9 ldr r1, [r7, #88] @ 0x58 8008d02: f021 0107 bic.w r1, r1, #7 8008d06: 4301 orrs r1, r0 8008d08: 65b9 str r1, [r7, #88] @ 0x58 8008d0a: e4a0 b.n 800864e 8008d0c: 462e mov r6, r5 8008d0e: e519 b.n 8008744 8008d10: 462e mov r6, r5 8008d12: f7ff bbb0 b.w 8008476 8008d16: 462e mov r6, r5 8008d18: e541 b.n 800879e 8008d1a: 462e mov r6, r5 8008d1c: e4c0 b.n 80086a0 8008d1e: 462e mov r6, r5 8008d20: e44f b.n 80085c2 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008d22: 4969 ldr r1, [pc, #420] @ (8008ec8 ) 8008d24: 6a89 ldr r1, [r1, #40] @ 0x28 8008d26: f001 0103 and.w r1, r1, #3 8008d2a: 2903 cmp r1, #3 8008d2c: f43f abe5 beq.w 80084fa 8008d30: 2102 movs r1, #2 8008d32: f104 0008 add.w r0, r4, #8 8008d36: f7ff f96f bl 8008018 8008d3a: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 8008d3c: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008d40: 2d00 cmp r5, #0 8008d42: d1b6 bne.n 8008cb2 8008d44: f7ff bb1a b.w 800837c if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008d48: 495f ldr r1, [pc, #380] @ (8008ec8 ) 8008d4a: 6a89 ldr r1, [r1, #40] @ 0x28 8008d4c: f001 0103 and.w r1, r1, #3 8008d50: 2903 cmp r1, #3 8008d52: f43f ad34 beq.w 80087be 8008d56: 2101 movs r1, #1 8008d58: f104 0028 add.w r0, r4, #40 @ 0x28 8008d5c: f7ff f9ce bl 80080fc 8008d60: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 8008d62: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008d66: 2d00 cmp r5, #0 8008d68: d199 bne.n 8008c9e 8008d6a: e654 b.n 8008a16 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008d6c: 4956 ldr r1, [pc, #344] @ (8008ec8 ) 8008d6e: 6a89 ldr r1, [r1, #40] @ 0x28 8008d70: f001 0103 and.w r1, r1, #3 8008d74: 2903 cmp r1, #3 8008d76: f000 8155 beq.w 8009024 8008d7a: 2102 movs r1, #2 8008d7c: f104 0008 add.w r0, r4, #8 8008d80: f7ff f94a bl 8008018 8008d84: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8008d86: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008d8a: 2d00 cmp r5, #0 8008d8c: f47f abe3 bne.w 8008556 8008d90: e787 b.n 8008ca2 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008d92: 494d ldr r1, [pc, #308] @ (8008ec8 ) 8008d94: 6a89 ldr r1, [r1, #40] @ 0x28 8008d96: f001 0103 and.w r1, r1, #3 8008d9a: 2903 cmp r1, #3 8008d9c: f43f abd0 beq.w 8008540 8008da0: 2101 movs r1, #1 8008da2: f104 0028 add.w r0, r4, #40 @ 0x28 8008da6: f7ff f9a9 bl 80080fc 8008daa: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8008dac: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008db0: 2d00 cmp r5, #0 8008db2: d1ad bne.n 8008d10 8008db4: f7ff bb57 b.w 8008466 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008db8: 4943 ldr r1, [pc, #268] @ (8008ec8 ) 8008dba: 6a89 ldr r1, [r1, #40] @ 0x28 8008dbc: f001 0103 and.w r1, r1, #3 8008dc0: 2903 cmp r1, #3 8008dc2: f43f adda beq.w 800897a 8008dc6: 2102 movs r1, #2 8008dc8: f104 0028 add.w r0, r4, #40 @ 0x28 8008dcc: f7ff f996 bl 80080fc 8008dd0: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 8008dd2: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008dd6: 2d00 cmp r5, #0 8008dd8: d19f bne.n 8008d1a 8008dda: e459 b.n 8008690 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008ddc: 493a ldr r1, [pc, #232] @ (8008ec8 ) 8008dde: 6a89 ldr r1, [r1, #40] @ 0x28 8008de0: f001 0103 and.w r1, r1, #3 8008de4: 2903 cmp r1, #3 8008de6: f43f add5 beq.w 8008994 8008dea: 2102 movs r1, #2 8008dec: f104 0028 add.w r0, r4, #40 @ 0x28 8008df0: f7ff f984 bl 80080fc 8008df4: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 8008df6: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008dfa: 2d00 cmp r5, #0 8008dfc: f47f af78 bne.w 8008cf0 8008e00: e46f b.n 80086e2 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008e02: 4931 ldr r1, [pc, #196] @ (8008ec8 ) 8008e04: 6a89 ldr r1, [r1, #40] @ 0x28 8008e06: f001 0103 and.w r1, r1, #3 8008e0a: 2903 cmp r1, #3 8008e0c: f43f ab8d beq.w 800852a 8008e10: 2101 movs r1, #1 8008e12: f104 0028 add.w r0, r4, #40 @ 0x28 8008e16: f7ff f971 bl 80080fc 8008e1a: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 8008e1c: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008e20: 2d00 cmp r5, #0 8008e22: f47f af67 bne.w 8008cf4 8008e26: f7ff baf9 b.w 800841c if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008e2a: 4927 ldr r1, [pc, #156] @ (8008ec8 ) 8008e2c: 6a89 ldr r1, [r1, #40] @ 0x28 8008e2e: f001 0103 and.w r1, r1, #3 8008e32: 2903 cmp r1, #3 8008e34: f43f adbb beq.w 80089ae 8008e38: 2102 movs r1, #2 8008e3a: f104 0028 add.w r0, r4, #40 @ 0x28 8008e3e: f7ff f95d bl 80080fc 8008e42: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 8008e44: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008e48: 2d00 cmp r5, #0 8008e4a: f47f af5f bne.w 8008d0c 8008e4e: e471 b.n 8008734 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008e50: 491d ldr r1, [pc, #116] @ (8008ec8 ) 8008e52: 6a89 ldr r1, [r1, #40] @ 0x28 8008e54: f001 0103 and.w r1, r1, #3 8008e58: 2903 cmp r1, #3 8008e5a: f43f ab59 beq.w 8008510 8008e5e: 2100 movs r1, #0 8008e60: f104 0028 add.w r0, r4, #40 @ 0x28 8008e64: f7ff f94a bl 80080fc 8008e68: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 8008e6a: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008e6e: 2d00 cmp r5, #0 8008e70: f47f af2b bne.w 8008cca 8008e74: f7ff baab b.w 80083ce if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008e78: 4913 ldr r1, [pc, #76] @ (8008ec8 ) 8008e7a: 6a89 ldr r1, [r1, #40] @ 0x28 8008e7c: f001 0103 and.w r1, r1, #3 8008e80: 2903 cmp r1, #3 8008e82: f43f ab29 beq.w 80084d8 8008e86: 2100 movs r1, #0 8008e88: f104 0028 add.w r0, r4, #40 @ 0x28 8008e8c: f7ff f936 bl 80080fc 8008e90: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 8008e92: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008e96: 2d00 cmp r5, #0 8008e98: f47f af11 bne.w 8008cbe 8008e9c: f7ff ba27 b.w 80082ee if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008ea0: 4909 ldr r1, [pc, #36] @ (8008ec8 ) 8008ea2: 6a89 ldr r1, [r1, #40] @ 0x28 8008ea4: f001 0103 and.w r1, r1, #3 8008ea8: 2903 cmp r1, #3 8008eaa: f43f ae05 beq.w 8008ab8 8008eae: 2102 movs r1, #2 8008eb0: 3028 adds r0, #40 @ 0x28 8008eb2: f7ff f923 bl 80080fc 8008eb6: 4606 mov r6, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 8008eb8: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008ebc: 2e00 cmp r6, #0 8008ebe: f47f a9be bne.w 800823e __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 8008ec2: 6ea1 ldr r1, [r4, #104] @ 0x68 8008ec4: f7ff b9b4 b.w 8008230 8008ec8: 58024400 .word 0x58024400 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008ecc: 4969 ldr r1, [pc, #420] @ (8009074 ) 8008ece: 6a89 ldr r1, [r1, #40] @ 0x28 8008ed0: f001 0103 and.w r1, r1, #3 8008ed4: 2903 cmp r1, #3 8008ed6: f43f ab0a beq.w 80084ee 8008eda: 2100 movs r1, #0 8008edc: f104 0028 add.w r0, r4, #40 @ 0x28 8008ee0: f7ff f90c bl 80080fc 8008ee4: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 8008ee6: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008eea: 2d00 cmp r5, #0 8008eec: f47f aeea bne.w 8008cc4 8008ef0: f7ff ba28 b.w 8008344 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008ef4: 495f ldr r1, [pc, #380] @ (8009074 ) 8008ef6: 6a89 ldr r1, [r1, #40] @ 0x28 8008ef8: f001 0103 and.w r1, r1, #3 8008efc: 2903 cmp r1, #3 8008efe: f43f aadd beq.w 80084bc 8008f02: 2100 movs r1, #0 8008f04: f104 0028 add.w r0, r4, #40 @ 0x28 8008f08: f7ff f8f8 bl 80080fc 8008f0c: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 8008f0e: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008f12: 2d00 cmp r5, #0 8008f14: f47f aed0 bne.w 8008cb8 8008f18: f7ff b9bf b.w 800829a if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008f1c: 4955 ldr r1, [pc, #340] @ (8009074 ) 8008f1e: 6a89 ldr r1, [r1, #40] @ 0x28 8008f20: f001 0103 and.w r1, r1, #3 8008f24: 2903 cmp r1, #3 8008f26: f43f a996 beq.w 8008256 8008f2a: 2100 movs r1, #0 8008f2c: f104 0008 add.w r0, r4, #8 8008f30: f7ff f872 bl 8008018 8008f34: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 8008f36: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008f3a: 2d00 cmp r5, #0 8008f3c: f43f ae13 beq.w 8008b66 8008f40: 462e mov r6, r5 8008f42: f7ff b98a b.w 800825a if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008f46: 494b ldr r1, [pc, #300] @ (8009074 ) 8008f48: 6a89 ldr r1, [r1, #40] @ 0x28 8008f4a: f001 0103 and.w r1, r1, #3 8008f4e: 2903 cmp r1, #3 8008f50: f43f a981 beq.w 8008256 8008f54: 2100 movs r1, #0 8008f56: f104 0028 add.w r0, r4, #40 @ 0x28 8008f5a: f7ff f8cf bl 80080fc 8008f5e: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 8008f60: e9d4 3200 ldrd r3, r2, [r4] break; 8008f64: e5fc b.n 8008b60 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008f66: 4943 ldr r1, [pc, #268] @ (8009074 ) 8008f68: 6a89 ldr r1, [r1, #40] @ 0x28 8008f6a: f001 0103 and.w r1, r1, #3 8008f6e: 2903 cmp r1, #3 8008f70: d03d beq.n 8008fee 8008f72: 2101 movs r1, #1 8008f74: f104 0028 add.w r0, r4, #40 @ 0x28 8008f78: f7ff f8c0 bl 80080fc 8008f7c: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8008f7e: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008f82: 2d00 cmp r5, #0 8008f84: f47f ab3d bne.w 8008602 8008f88: e6aa b.n 8008ce0 if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008f8a: 493a ldr r1, [pc, #232] @ (8009074 ) 8008f8c: 6a89 ldr r1, [r1, #40] @ 0x28 8008f8e: f001 0103 and.w r1, r1, #3 8008f92: 2903 cmp r1, #3 8008f94: d02f beq.n 8008ff6 8008f96: 2101 movs r1, #1 8008f98: f104 0028 add.w r0, r4, #40 @ 0x28 8008f9c: f7ff f8ae bl 80080fc 8008fa0: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8008fa2: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008fa6: 2d00 cmp r5, #0 8008fa8: f47f ab50 bne.w 800864c 8008fac: e6a5 b.n 8008cfa if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008fae: 4931 ldr r1, [pc, #196] @ (8009074 ) 8008fb0: 6a89 ldr r1, [r1, #40] @ 0x28 8008fb2: f001 0103 and.w r1, r1, #3 8008fb6: 2903 cmp r1, #3 8008fb8: f43f ab01 beq.w 80085be 8008fbc: 2101 movs r1, #1 8008fbe: f104 0028 add.w r0, r4, #40 @ 0x28 8008fc2: f7ff f89b bl 80080fc 8008fc6: 4605 mov r5, r0 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8008fc8: e9d4 3200 ldrd r3, r2, [r4] if (ret == HAL_OK) 8008fcc: 2d00 cmp r5, #0 8008fce: f47f aea6 bne.w 8008d1e 8008fd2: e569 b.n 8008aa8 ret = HAL_TIMEOUT; 8008fd4: 2503 movs r5, #3 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 8008fd6: 462e mov r6, r5 8008fd8: e9d4 3200 ldrd r3, r2, [r4] 8008fdc: f7ff babf b.w 800855e __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8008fe0: 4d24 ldr r5, [pc, #144] @ (8009074 ) 8008fe2: 6ae8 ldr r0, [r5, #44] @ 0x2c 8008fe4: f440 3000 orr.w r0, r0, #131072 @ 0x20000 8008fe8: 62e8 str r0, [r5, #44] @ 0x2c if (ret == HAL_OK) 8008fea: f7ff b921 b.w 8008230 8008fee: 2601 movs r6, #1 8008ff0: 4635 mov r5, r6 8008ff2: f7ff bb07 b.w 8008604 8008ff6: 2601 movs r6, #1 8008ff8: 4635 mov r5, r6 8008ffa: f7ff bb28 b.w 800864e status = HAL_ERROR; 8008ffe: 2601 movs r6, #1 8009000: f7ff bbb6 b.w 8008770 status = HAL_ERROR; 8009004: 2601 movs r6, #1 8009006: f7ff bba5 b.w 8008754 __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800900a: f8d4 0084 ldr.w r0, [r4, #132] @ 0x84 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800900e: e9d4 3200 ldrd r3, r2, [r4] 8009012: f7ff bb9f b.w 8008754 __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8009016: f8d4 0098 ldr.w r0, [r4, #152] @ 0x98 status = HAL_ERROR; 800901a: 2601 movs r6, #1 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800901c: e9d4 3200 ldrd r3, r2, [r4] 8009020: f7ff bba6 b.w 8008770 8009024: 2601 movs r6, #1 8009026: 4635 mov r5, r6 8009028: f7ff ba96 b.w 8008558 tickstart = HAL_GetTick(); 800902c: f7fa ffd0 bl 8003fd0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8009030: f8df 8040 ldr.w r8, [pc, #64] @ 8009074 tickstart = HAL_GetTick(); 8009034: 4607 mov r7, r0 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8009036: f241 3988 movw r9, #5000 @ 0x1388 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800903a: e004 b.n 8009046 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800903c: f7fa ffc8 bl 8003fd0 8009040: 1bc0 subs r0, r0, r7 8009042: 4548 cmp r0, r9 8009044: d810 bhi.n 8009068 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8009046: f8d8 3070 ldr.w r3, [r8, #112] @ 0x70 800904a: 079b lsls r3, r3, #30 800904c: d5f6 bpl.n 800903c __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800904e: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4 8009052: e562 b.n 8008b1a 8009054: 4807 ldr r0, [pc, #28] @ (8009074 ) 8009056: 4a08 ldr r2, [pc, #32] @ (8009078 ) 8009058: 6901 ldr r1, [r0, #16] 800905a: ea02 1213 and.w r2, r2, r3, lsr #4 800905e: f421 517c bic.w r1, r1, #16128 @ 0x3f00 8009062: 430a orrs r2, r1 8009064: 6102 str r2, [r0, #16] 8009066: e563 b.n 8008b30 status = ret; 8009068: 2603 movs r6, #3 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800906a: e9d4 3200 ldrd r3, r2, [r4] 800906e: 4635 mov r5, r6 8009070: f7ff ba75 b.w 800855e 8009074: 58024400 .word 0x58024400 8009078: 00ffffcf .word 0x00ffffcf 0800907c : { 800907c: b508 push {r3, lr} return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800907e: f7fe fecf bl 8007e20 8009082: 4b05 ldr r3, [pc, #20] @ (8009098 ) 8009084: 4a05 ldr r2, [pc, #20] @ (800909c ) 8009086: 6a1b ldr r3, [r3, #32] 8009088: f3c3 1302 ubfx r3, r3, #4, #3 800908c: 5cd3 ldrb r3, [r2, r3] 800908e: f003 031f and.w r3, r3, #31 } 8009092: 40d8 lsrs r0, r3 8009094: bd08 pop {r3, pc} 8009096: bf00 nop 8009098: 58024400 .word 0x58024400 800909c: 08011a14 .word 0x08011a14 080090a0 : pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80090a0: 4a47 ldr r2, [pc, #284] @ (80091c0 ) { 80090a2: b470 push {r4, r5, r6} pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80090a4: 6a91 ldr r1, [r2, #40] @ 0x28 pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 80090a6: 6a95 ldr r5, [r2, #40] @ 0x28 pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 80090a8: 6ad6 ldr r6, [r2, #44] @ 0x2c if (pll2m != 0U) 80090aa: f415 3f7c tst.w r5, #258048 @ 0x3f000 pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 80090ae: f3c5 3305 ubfx r3, r5, #12, #6 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 80090b2: 6bd4 ldr r4, [r2, #60] @ 0x3c if (pll2m != 0U) 80090b4: d05b beq.n 800916e fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 80090b6: f3c4 04cc ubfx r4, r4, #3, #13 pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 80090ba: f3c6 1600 ubfx r6, r6, #4, #1 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80090be: f001 0103 and.w r1, r1, #3 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 80090c2: ee07 3a90 vmov s15, r3 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 80090c6: fb06 f404 mul.w r4, r6, r4 switch (pllsource) 80090ca: 2901 cmp r1, #1 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 80090cc: eeb8 7ae7 vcvt.f32.s32 s14, s15 80090d0: ee06 4a90 vmov s13, r4 80090d4: eefa 6ae9 vcvt.f32.s32 s13, s13, #13 switch (pllsource) 80090d8: d003 beq.n 80090e2 80090da: 2902 cmp r1, #2 80090dc: d06a beq.n 80091b4 80090de: 2900 cmp r1, #0 80090e0: d04a beq.n 8009178 pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 80090e2: eddf 7a38 vldr s15, [pc, #224] @ 80091c4 80090e6: ee87 6a87 vdiv.f32 s12, s15, s14 80090ea: 6b93 ldr r3, [r2, #56] @ 0x38 80090ec: f3c3 0308 ubfx r3, r3, #0, #9 80090f0: ee07 3a90 vmov s15, r3 80090f4: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 80090f8: eef8 7ae7 vcvt.f32.s32 s15, s15 80090fc: ee77 7aa5 vadd.f32 s15, s15, s11 8009100: ee77 7aa6 vadd.f32 s15, s15, s13 8009104: ee67 7a86 vmul.f32 s15, s15, s12 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 8009108: 4a2d ldr r2, [pc, #180] @ (80091c0 ) 800910a: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0 800910e: 6b93 ldr r3, [r2, #56] @ 0x38 8009110: f3c3 2346 ubfx r3, r3, #9, #7 8009114: ee07 3a10 vmov s14, r3 8009118: eeb8 7ac7 vcvt.f32.s32 s14, s14 } 800911c: bc70 pop {r4, r5, r6} PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800911e: ee37 7a06 vadd.f32 s14, s14, s12 8009122: eec7 6a87 vdiv.f32 s13, s15, s14 8009126: eefc 6ae6 vcvt.u32.f32 s13, s13 800912a: edc0 6a00 vstr s13, [r0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800912e: 6b93 ldr r3, [r2, #56] @ 0x38 8009130: f3c3 4306 ubfx r3, r3, #16, #7 8009134: ee07 3a10 vmov s14, r3 8009138: eeb8 7ac7 vcvt.f32.s32 s14, s14 800913c: ee37 7a06 vadd.f32 s14, s14, s12 8009140: eec7 6a87 vdiv.f32 s13, s15, s14 8009144: eefc 6ae6 vcvt.u32.f32 s13, s13 8009148: edc0 6a01 vstr s13, [r0, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800914c: 6b93 ldr r3, [r2, #56] @ 0x38 800914e: f3c3 6306 ubfx r3, r3, #24, #7 8009152: ee06 3a90 vmov s13, r3 8009156: eef8 6ae6 vcvt.f32.s32 s13, s13 800915a: ee76 6a86 vadd.f32 s13, s13, s12 800915e: ee87 7aa6 vdiv.f32 s14, s15, s13 8009162: eefc 7ac7 vcvt.u32.f32 s15, s14 8009166: ee17 3a90 vmov r3, s15 800916a: 6083 str r3, [r0, #8] } 800916c: 4770 bx lr 800916e: bc70 pop {r4, r5, r6} PLL2_Clocks->PLL2_P_Frequency = 0U; 8009170: e9c0 3300 strd r3, r3, [r0] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 8009174: 6083 str r3, [r0, #8] } 8009176: 4770 bx lr if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8009178: 6813 ldr r3, [r2, #0] 800917a: 069b lsls r3, r3, #26 800917c: d51d bpl.n 80091ba hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800917e: 6814 ldr r4, [r2, #0] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8009180: eef7 7a00 vmov.f32 s15, #112 @ 0x3f800000 1.0 8009184: 6b93 ldr r3, [r2, #56] @ 0x38 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8009186: 4910 ldr r1, [pc, #64] @ (80091c8 ) 8009188: f3c4 02c1 ubfx r2, r4, #3, #2 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800918c: f3c3 0308 ubfx r3, r3, #0, #9 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8009190: 40d1 lsrs r1, r2 pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8009192: ee06 3a10 vmov s12, r3 8009196: ee05 1a90 vmov s11, r1 800919a: eeb8 6ac6 vcvt.f32.s32 s12, s12 800919e: eef8 5ae5 vcvt.f32.s32 s11, s11 80091a2: ee36 6a27 vadd.f32 s12, s12, s15 80091a6: eec5 7a87 vdiv.f32 s15, s11, s14 80091aa: ee36 7a26 vadd.f32 s14, s12, s13 80091ae: ee67 7a87 vmul.f32 s15, s15, s14 80091b2: e7a9 b.n 8009108 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 80091b4: eddf 7a05 vldr s15, [pc, #20] @ 80091cc 80091b8: e795 b.n 80090e6 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 80091ba: eddf 7a05 vldr s15, [pc, #20] @ 80091d0 80091be: e792 b.n 80090e6 80091c0: 58024400 .word 0x58024400 80091c4: 4a742400 .word 0x4a742400 80091c8: 03d09000 .word 0x03d09000 80091cc: 4bbebc20 .word 0x4bbebc20 80091d0: 4c742400 .word 0x4c742400 080091d4 : pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80091d4: 4a47 ldr r2, [pc, #284] @ (80092f4 ) { 80091d6: b470 push {r4, r5, r6} pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80091d8: 6a91 ldr r1, [r2, #40] @ 0x28 pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 80091da: 6a95 ldr r5, [r2, #40] @ 0x28 pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 80091dc: 6ad6 ldr r6, [r2, #44] @ 0x2c if (pll3m != 0U) 80091de: f015 7f7c tst.w r5, #66060288 @ 0x3f00000 pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 80091e2: f3c5 5305 ubfx r3, r5, #20, #6 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 80091e6: 6c54 ldr r4, [r2, #68] @ 0x44 if (pll3m != 0U) 80091e8: d05b beq.n 80092a2 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 80091ea: f3c4 04cc ubfx r4, r4, #3, #13 pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 80091ee: f3c6 2600 ubfx r6, r6, #8, #1 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80091f2: f001 0103 and.w r1, r1, #3 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80091f6: ee07 3a90 vmov s15, r3 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 80091fa: fb06 f404 mul.w r4, r6, r4 switch (pllsource) 80091fe: 2901 cmp r1, #1 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8009200: eeb8 7ae7 vcvt.f32.s32 s14, s15 8009204: ee06 4a90 vmov s13, r4 8009208: eefa 6ae9 vcvt.f32.s32 s13, s13, #13 switch (pllsource) 800920c: d003 beq.n 8009216 800920e: 2902 cmp r1, #2 8009210: d06a beq.n 80092e8 8009212: 2900 cmp r1, #0 8009214: d04a beq.n 80092ac pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8009216: eddf 7a38 vldr s15, [pc, #224] @ 80092f8 800921a: ee87 6a87 vdiv.f32 s12, s15, s14 800921e: 6c13 ldr r3, [r2, #64] @ 0x40 8009220: f3c3 0308 ubfx r3, r3, #0, #9 8009224: ee07 3a90 vmov s15, r3 8009228: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 800922c: eef8 7ae7 vcvt.f32.s32 s15, s15 8009230: ee77 7aa5 vadd.f32 s15, s15, s11 8009234: ee77 7aa6 vadd.f32 s15, s15, s13 8009238: ee67 7a86 vmul.f32 s15, s15, s12 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800923c: 4a2d ldr r2, [pc, #180] @ (80092f4 ) 800923e: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0 8009242: 6c13 ldr r3, [r2, #64] @ 0x40 8009244: f3c3 2346 ubfx r3, r3, #9, #7 8009248: ee07 3a10 vmov s14, r3 800924c: eeb8 7ac7 vcvt.f32.s32 s14, s14 } 8009250: bc70 pop {r4, r5, r6} PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 8009252: ee37 7a06 vadd.f32 s14, s14, s12 8009256: eec7 6a87 vdiv.f32 s13, s15, s14 800925a: eefc 6ae6 vcvt.u32.f32 s13, s13 800925e: edc0 6a00 vstr s13, [r0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 8009262: 6c13 ldr r3, [r2, #64] @ 0x40 8009264: f3c3 4306 ubfx r3, r3, #16, #7 8009268: ee07 3a10 vmov s14, r3 800926c: eeb8 7ac7 vcvt.f32.s32 s14, s14 8009270: ee37 7a06 vadd.f32 s14, s14, s12 8009274: eec7 6a87 vdiv.f32 s13, s15, s14 8009278: eefc 6ae6 vcvt.u32.f32 s13, s13 800927c: edc0 6a01 vstr s13, [r0, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 8009280: 6c13 ldr r3, [r2, #64] @ 0x40 8009282: f3c3 6306 ubfx r3, r3, #24, #7 8009286: ee06 3a90 vmov s13, r3 800928a: eef8 6ae6 vcvt.f32.s32 s13, s13 800928e: ee76 6a86 vadd.f32 s13, s13, s12 8009292: ee87 7aa6 vdiv.f32 s14, s15, s13 8009296: eefc 7ac7 vcvt.u32.f32 s15, s14 800929a: ee17 3a90 vmov r3, s15 800929e: 6083 str r3, [r0, #8] } 80092a0: 4770 bx lr 80092a2: bc70 pop {r4, r5, r6} PLL3_Clocks->PLL3_P_Frequency = 0U; 80092a4: e9c0 3300 strd r3, r3, [r0] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 80092a8: 6083 str r3, [r0, #8] } 80092aa: 4770 bx lr if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80092ac: 6813 ldr r3, [r2, #0] 80092ae: 069b lsls r3, r3, #26 80092b0: d51d bpl.n 80092ee hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80092b2: 6814 ldr r4, [r2, #0] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80092b4: eef7 7a00 vmov.f32 s15, #112 @ 0x3f800000 1.0 80092b8: 6c13 ldr r3, [r2, #64] @ 0x40 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80092ba: 4910 ldr r1, [pc, #64] @ (80092fc ) 80092bc: f3c4 02c1 ubfx r2, r4, #3, #2 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80092c0: f3c3 0308 ubfx r3, r3, #0, #9 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80092c4: 40d1 lsrs r1, r2 pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80092c6: ee06 3a10 vmov s12, r3 80092ca: ee05 1a90 vmov s11, r1 80092ce: eeb8 6ac6 vcvt.f32.s32 s12, s12 80092d2: eef8 5ae5 vcvt.f32.s32 s11, s11 80092d6: ee36 6a27 vadd.f32 s12, s12, s15 80092da: eec5 7a87 vdiv.f32 s15, s11, s14 80092de: ee36 7a26 vadd.f32 s14, s12, s13 80092e2: ee67 7a87 vmul.f32 s15, s15, s14 80092e6: e7a9 b.n 800923c pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80092e8: eddf 7a05 vldr s15, [pc, #20] @ 8009300 80092ec: e795 b.n 800921a pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 80092ee: eddf 7a05 vldr s15, [pc, #20] @ 8009304 80092f2: e792 b.n 800921a 80092f4: 58024400 .word 0x58024400 80092f8: 4a742400 .word 0x4a742400 80092fc: 03d09000 .word 0x03d09000 8009300: 4bbebc20 .word 0x4bbebc20 8009304: 4c742400 .word 0x4c742400 08009308 : pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8009308: 4a47 ldr r2, [pc, #284] @ (8009428 ) { 800930a: b470 push {r4, r5, r6} pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800930c: 6a91 ldr r1, [r2, #40] @ 0x28 pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800930e: 6a95 ldr r5, [r2, #40] @ 0x28 pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 8009310: 6ad6 ldr r6, [r2, #44] @ 0x2c if (pll1m != 0U) 8009312: f415 7f7c tst.w r5, #1008 @ 0x3f0 pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 8009316: f3c5 1305 ubfx r3, r5, #4, #6 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800931a: 6b54 ldr r4, [r2, #52] @ 0x34 if (pll1m != 0U) 800931c: d05b beq.n 80093d6 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800931e: f3c4 04cc ubfx r4, r4, #3, #13 pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 8009322: f006 0601 and.w r6, r6, #1 pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8009326: f001 0103 and.w r1, r1, #3 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800932a: ee07 3a90 vmov s15, r3 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800932e: fb06 f404 mul.w r4, r6, r4 switch (pllsource) 8009332: 2901 cmp r1, #1 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8009334: eeb8 7ae7 vcvt.f32.s32 s14, s15 8009338: ee06 4a90 vmov s13, r4 800933c: eefa 6ae9 vcvt.f32.s32 s13, s13, #13 switch (pllsource) 8009340: d06f beq.n 8009422 8009342: 2902 cmp r1, #2 8009344: d06a beq.n 800941c 8009346: 2900 cmp r1, #0 8009348: d04a beq.n 80093e0 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800934a: eddf 7a38 vldr s15, [pc, #224] @ 800942c 800934e: ee87 6a87 vdiv.f32 s12, s15, s14 8009352: 6b13 ldr r3, [r2, #48] @ 0x30 8009354: f3c3 0308 ubfx r3, r3, #0, #9 8009358: ee07 3a90 vmov s15, r3 800935c: eef7 5a00 vmov.f32 s11, #112 @ 0x3f800000 1.0 8009360: eef8 7ae7 vcvt.f32.s32 s15, s15 8009364: ee77 7aa5 vadd.f32 s15, s15, s11 8009368: ee77 7aa6 vadd.f32 s15, s15, s13 800936c: ee67 7a86 vmul.f32 s15, s15, s12 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 8009370: 4a2d ldr r2, [pc, #180] @ (8009428 ) 8009372: eeb7 6a00 vmov.f32 s12, #112 @ 0x3f800000 1.0 8009376: 6b13 ldr r3, [r2, #48] @ 0x30 8009378: f3c3 2346 ubfx r3, r3, #9, #7 800937c: ee07 3a10 vmov s14, r3 8009380: eeb8 7ac7 vcvt.f32.s32 s14, s14 } 8009384: bc70 pop {r4, r5, r6} PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 8009386: ee37 7a06 vadd.f32 s14, s14, s12 800938a: eec7 6a87 vdiv.f32 s13, s15, s14 800938e: eefc 6ae6 vcvt.u32.f32 s13, s13 8009392: edc0 6a00 vstr s13, [r0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 8009396: 6b13 ldr r3, [r2, #48] @ 0x30 8009398: f3c3 4306 ubfx r3, r3, #16, #7 800939c: ee07 3a10 vmov s14, r3 80093a0: eeb8 7ac7 vcvt.f32.s32 s14, s14 80093a4: ee37 7a06 vadd.f32 s14, s14, s12 80093a8: eec7 6a87 vdiv.f32 s13, s15, s14 80093ac: eefc 6ae6 vcvt.u32.f32 s13, s13 80093b0: edc0 6a01 vstr s13, [r0, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 80093b4: 6b13 ldr r3, [r2, #48] @ 0x30 80093b6: f3c3 6306 ubfx r3, r3, #24, #7 80093ba: ee06 3a90 vmov s13, r3 80093be: eef8 6ae6 vcvt.f32.s32 s13, s13 80093c2: ee76 6a86 vadd.f32 s13, s13, s12 80093c6: ee87 7aa6 vdiv.f32 s14, s15, s13 80093ca: eefc 7ac7 vcvt.u32.f32 s15, s14 80093ce: ee17 3a90 vmov r3, s15 80093d2: 6083 str r3, [r0, #8] } 80093d4: 4770 bx lr 80093d6: bc70 pop {r4, r5, r6} PLL1_Clocks->PLL1_P_Frequency = 0U; 80093d8: e9c0 3300 strd r3, r3, [r0] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 80093dc: 6083 str r3, [r0, #8] } 80093de: 4770 bx lr if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80093e0: 6813 ldr r3, [r2, #0] 80093e2: 069b lsls r3, r3, #26 80093e4: d5b1 bpl.n 800934a hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80093e6: 6814 ldr r4, [r2, #0] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80093e8: eef7 7a00 vmov.f32 s15, #112 @ 0x3f800000 1.0 80093ec: 6b13 ldr r3, [r2, #48] @ 0x30 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80093ee: 4910 ldr r1, [pc, #64] @ (8009430 ) 80093f0: f3c4 02c1 ubfx r2, r4, #3, #2 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80093f4: f3c3 0308 ubfx r3, r3, #0, #9 hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80093f8: 40d1 lsrs r1, r2 pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80093fa: ee06 3a10 vmov s12, r3 80093fe: ee05 1a90 vmov s11, r1 8009402: eeb8 6ac6 vcvt.f32.s32 s12, s12 8009406: eef8 5ae5 vcvt.f32.s32 s11, s11 800940a: ee36 6a27 vadd.f32 s12, s12, s15 800940e: eec5 7a87 vdiv.f32 s15, s11, s14 8009412: ee36 7a26 vadd.f32 s14, s12, s13 8009416: ee67 7a87 vmul.f32 s15, s15, s14 800941a: e7a9 b.n 8009370 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800941c: eddf 7a05 vldr s15, [pc, #20] @ 8009434 8009420: e795 b.n 800934e pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8009422: eddf 7a05 vldr s15, [pc, #20] @ 8009438 8009426: e792 b.n 800934e 8009428: 58024400 .word 0x58024400 800942c: 4c742400 .word 0x4c742400 8009430: 03d09000 .word 0x03d09000 8009434: 4bbebc20 .word 0x4bbebc20 8009438: 4a742400 .word 0x4a742400 0800943c : if (PeriphClk == RCC_PERIPHCLK_SAI1) 800943c: f5a0 7380 sub.w r3, r0, #256 @ 0x100 8009440: 430b orrs r3, r1 { 8009442: b500 push {lr} 8009444: b085 sub sp, #20 if (PeriphClk == RCC_PERIPHCLK_SAI1) 8009446: f000 8083 beq.w 8009550 else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800944a: f5a0 7300 sub.w r3, r0, #512 @ 0x200 800944e: 430b orrs r3, r1 8009450: d038 beq.n 80094c4 else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 8009452: f5a0 6380 sub.w r3, r0, #1024 @ 0x400 8009456: 430b orrs r3, r1 8009458: f000 80e6 beq.w 8009628 else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800945c: f5a0 6300 sub.w r3, r0, #2048 @ 0x800 8009460: 430b orrs r3, r1 8009462: f000 8089 beq.w 8009578 else if (PeriphClk == RCC_PERIPHCLK_SPI123) 8009466: f5a0 5380 sub.w r3, r0, #4096 @ 0x1000 800946a: 430b orrs r3, r1 800946c: d060 beq.n 8009530 else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800946e: f5a0 5300 sub.w r3, r0, #8192 @ 0x2000 8009472: 430b orrs r3, r1 8009474: f000 8112 beq.w 800969c else if (PeriphClk == RCC_PERIPHCLK_ADC) 8009478: f5a0 2300 sub.w r3, r0, #524288 @ 0x80000 800947c: 430b orrs r3, r1 800947e: f000 80a3 beq.w 80095c8 else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 8009482: f5a0 3380 sub.w r3, r0, #65536 @ 0x10000 8009486: 430b orrs r3, r1 8009488: f000 80fa beq.w 8009680 else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800948c: f5a0 4380 sub.w r3, r0, #16384 @ 0x4000 8009490: 430b orrs r3, r1 8009492: f000 8143 beq.w 800971c else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 8009496: f5a0 4000 sub.w r0, r0, #32768 @ 0x8000 800949a: 4308 orrs r0, r1 800949c: d137 bne.n 800950e srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800949e: 4a9a ldr r2, [pc, #616] @ (8009708 ) 80094a0: 6d13 ldr r3, [r2, #80] @ 0x50 80094a2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 switch (srcclk) 80094a6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80094aa: f000 8084 beq.w 80095b6 80094ae: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80094b2: f000 8157 beq.w 8009764 80094b6: bb53 cbnz r3, 800950e if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 80094b8: 6810 ldr r0, [r2, #0] 80094ba: f410 3000 ands.w r0, r0, #131072 @ 0x20000 80094be: d044 beq.n 800954a frequency = HSE_VALUE; 80094c0: 4892 ldr r0, [pc, #584] @ (800970c ) 80094c2: e042 b.n 800954a saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 80094c4: 4a90 ldr r2, [pc, #576] @ (8009708 ) 80094c6: 6d13 ldr r3, [r2, #80] @ 0x50 80094c8: f403 73e0 and.w r3, r3, #448 @ 0x1c0 switch (saiclocksource) 80094cc: 2b80 cmp r3, #128 @ 0x80 80094ce: f000 80a6 beq.w 800961e 80094d2: d920 bls.n 8009516 80094d4: 2bc0 cmp r3, #192 @ 0xc0 80094d6: d037 beq.n 8009548 80094d8: f5b3 7f80 cmp.w r3, #256 @ 0x100 80094dc: d117 bne.n 800950e ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 80094de: 6cd3 ldr r3, [r2, #76] @ 0x4c if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 80094e0: 6811 ldr r1, [r2, #0] ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 80094e2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 80094e6: 0749 lsls r1, r1, #29 80094e8: d502 bpl.n 80094f0 80094ea: 2b00 cmp r3, #0 80094ec: f000 80c2 beq.w 8009674 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 80094f0: 4a85 ldr r2, [pc, #532] @ (8009708 ) 80094f2: 6812 ldr r2, [r2, #0] 80094f4: 05d0 lsls r0, r2, #23 80094f6: d503 bpl.n 8009500 80094f8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80094fc: f000 8102 beq.w 8009704 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 8009500: 4a81 ldr r2, [pc, #516] @ (8009708 ) 8009502: 6812 ldr r2, [r2, #0] 8009504: 0391 lsls r1, r2, #14 8009506: d502 bpl.n 800950e 8009508: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800950c: d0d8 beq.n 80094c0 frequency = 0; 800950e: 2000 movs r0, #0 } 8009510: b005 add sp, #20 8009512: f85d fb04 ldr.w pc, [sp], #4 switch (saiclocksource) 8009516: 2b00 cmp r3, #0 8009518: d04d beq.n 80095b6 800951a: 2b40 cmp r3, #64 @ 0x40 800951c: d1f7 bne.n 800950e if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800951e: 6810 ldr r0, [r2, #0] 8009520: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 8009524: d011 beq.n 800954a HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009526: a801 add r0, sp, #4 8009528: f7ff fdba bl 80090a0 frequency = pll2_clocks.PLL2_P_Frequency; 800952c: 9801 ldr r0, [sp, #4] 800952e: e00c b.n 800954a srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 8009530: 4a75 ldr r2, [pc, #468] @ (8009708 ) 8009532: 6d13 ldr r3, [r2, #80] @ 0x50 8009534: f403 43e0 and.w r3, r3, #28672 @ 0x7000 switch (srcclk) 8009538: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800953c: d06f beq.n 800961e 800953e: d938 bls.n 80095b2 8009540: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8009544: f040 8088 bne.w 8009658 frequency = EXTERNAL_CLOCK_VALUE; 8009548: 4871 ldr r0, [pc, #452] @ (8009710 ) } 800954a: b005 add sp, #20 800954c: f85d fb04 ldr.w pc, [sp], #4 saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 8009550: 4b6d ldr r3, [pc, #436] @ (8009708 ) 8009552: 6d1b ldr r3, [r3, #80] @ 0x50 8009554: f003 0307 and.w r3, r3, #7 switch (saiclocksource) 8009558: 2b04 cmp r3, #4 800955a: d8d8 bhi.n 800950e 800955c: a201 add r2, pc, #4 @ (adr r2, 8009564 ) 800955e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009562: bf00 nop 8009564: 08009607 .word 0x08009607 8009568: 080095e3 .word 0x080095e3 800956c: 080095f3 .word 0x080095f3 8009570: 08009549 .word 0x08009549 8009574: 080095ef .word 0x080095ef saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 8009578: 4a63 ldr r2, [pc, #396] @ (8009708 ) 800957a: 6d93 ldr r3, [r2, #88] @ 0x58 800957c: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 switch (saiclocksource) 8009580: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 8009584: d04b beq.n 800961e 8009586: d944 bls.n 8009612 8009588: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800958c: d0dc beq.n 8009548 800958e: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8009592: d1bc bne.n 800950e ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8009594: 6cd3 ldr r3, [r2, #76] @ 0x4c if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 8009596: 6812 ldr r2, [r2, #0] ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 8009598: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800959c: 0752 lsls r2, r2, #29 800959e: d5a7 bpl.n 80094f0 80095a0: 2b00 cmp r3, #0 80095a2: d1a5 bne.n 80094f0 frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80095a4: 4b58 ldr r3, [pc, #352] @ (8009708 ) 80095a6: 485b ldr r0, [pc, #364] @ (8009714 ) 80095a8: 681b ldr r3, [r3, #0] 80095aa: f3c3 03c1 ubfx r3, r3, #3, #2 80095ae: 40d8 lsrs r0, r3 80095b0: e7cb b.n 800954a switch (srcclk) 80095b2: 2b00 cmp r3, #0 80095b4: d154 bne.n 8009660 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 80095b6: 6810 ldr r0, [r2, #0] 80095b8: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000 80095bc: d0c5 beq.n 800954a HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 80095be: a801 add r0, sp, #4 80095c0: f7ff fea2 bl 8009308 frequency = pll1_clocks.PLL1_Q_Frequency; 80095c4: 9802 ldr r0, [sp, #8] 80095c6: e7c0 b.n 800954a srcclk = __HAL_RCC_GET_ADC_SOURCE(); 80095c8: 4a4f ldr r2, [pc, #316] @ (8009708 ) 80095ca: 6d93 ldr r3, [r2, #88] @ 0x58 80095cc: f403 3340 and.w r3, r3, #196608 @ 0x30000 switch (srcclk) 80095d0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80095d4: f000 80d0 beq.w 8009778 80095d8: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80095dc: d0da beq.n 8009594 80095de: 2b00 cmp r3, #0 80095e0: d195 bne.n 800950e if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80095e2: 4b49 ldr r3, [pc, #292] @ (8009708 ) 80095e4: 6818 ldr r0, [r3, #0] 80095e6: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 80095ea: d0ae beq.n 800954a 80095ec: e79b b.n 8009526 ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 80095ee: 4a46 ldr r2, [pc, #280] @ (8009708 ) 80095f0: e775 b.n 80094de if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80095f2: 4b45 ldr r3, [pc, #276] @ (8009708 ) 80095f4: 6818 ldr r0, [r3, #0] 80095f6: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 80095fa: d0a6 beq.n 800954a HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80095fc: a801 add r0, sp, #4 80095fe: f7ff fde9 bl 80091d4 frequency = pll3_clocks.PLL3_P_Frequency; 8009602: 9801 ldr r0, [sp, #4] 8009604: e7a1 b.n 800954a if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 8009606: 4b40 ldr r3, [pc, #256] @ (8009708 ) 8009608: 6818 ldr r0, [r3, #0] 800960a: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000 800960e: d09c beq.n 800954a 8009610: e7d5 b.n 80095be switch (saiclocksource) 8009612: 2b00 cmp r3, #0 8009614: d0cf beq.n 80095b6 8009616: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800961a: d080 beq.n 800951e 800961c: e777 b.n 800950e if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800961e: 6810 ldr r0, [r2, #0] 8009620: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 8009624: d091 beq.n 800954a 8009626: e7e9 b.n 80095fc saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 8009628: 4a37 ldr r2, [pc, #220] @ (8009708 ) 800962a: 6d93 ldr r3, [r2, #88] @ 0x58 800962c: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 switch (saiclocksource) 8009630: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8009634: d0f3 beq.n 800961e 8009636: d806 bhi.n 8009646 8009638: 2b00 cmp r3, #0 800963a: d0bc beq.n 80095b6 800963c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8009640: f43f af6d beq.w 800951e 8009644: e763 b.n 800950e 8009646: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800964a: f43f af7d beq.w 8009548 800964e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8009652: f43f af44 beq.w 80094de 8009656: e75a b.n 800950e switch (srcclk) 8009658: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800965c: d09a beq.n 8009594 800965e: e756 b.n 800950e 8009660: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8009664: f43f af5b beq.w 800951e 8009668: e751 b.n 800950e if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800966a: 6810 ldr r0, [r2, #0] 800966c: f010 0004 ands.w r0, r0, #4 8009670: f43f af6b beq.w 800954a frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8009674: 6813 ldr r3, [r2, #0] 8009676: 4827 ldr r0, [pc, #156] @ (8009714 ) 8009678: f3c3 03c1 ubfx r3, r3, #3, #2 800967c: 40d8 lsrs r0, r3 800967e: e764 b.n 800954a srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 8009680: 4b21 ldr r3, [pc, #132] @ (8009708 ) 8009682: 6cda ldr r2, [r3, #76] @ 0x4c switch (srcclk) 8009684: 03d2 lsls r2, r2, #15 8009686: d5bf bpl.n 8009608 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8009688: 6818 ldr r0, [r3, #0] 800968a: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 800968e: f43f af5c beq.w 800954a HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009692: a801 add r0, sp, #4 8009694: f7ff fd04 bl 80090a0 frequency = pll2_clocks.PLL2_R_Frequency; 8009698: 9803 ldr r0, [sp, #12] 800969a: e756 b.n 800954a srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800969c: 4a1a ldr r2, [pc, #104] @ (8009708 ) 800969e: 6d13 ldr r3, [r2, #80] @ 0x50 80096a0: f403 23e0 and.w r3, r3, #458752 @ 0x70000 switch (srcclk) 80096a4: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 80096a8: d0df beq.n 800966a 80096aa: d810 bhi.n 80096ce 80096ac: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80096b0: d058 beq.n 8009764 80096b2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80096b6: d118 bne.n 80096ea if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 80096b8: 4b13 ldr r3, [pc, #76] @ (8009708 ) 80096ba: 6818 ldr r0, [r3, #0] 80096bc: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 80096c0: f43f af43 beq.w 800954a HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80096c4: a801 add r0, sp, #4 80096c6: f7ff fd85 bl 80091d4 frequency = pll3_clocks.PLL3_Q_Frequency; 80096ca: 9802 ldr r0, [sp, #8] 80096cc: e73d b.n 800954a switch (srcclk) 80096ce: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 80096d2: d012 beq.n 80096fa 80096d4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80096d8: f47f af19 bne.w 800950e if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 80096dc: 4b0a ldr r3, [pc, #40] @ (8009708 ) 80096de: 6818 ldr r0, [r3, #0] 80096e0: f410 3000 ands.w r0, r0, #131072 @ 0x20000 80096e4: f43f af31 beq.w 800954a 80096e8: e6ea b.n 80094c0 switch (srcclk) 80096ea: 2b00 cmp r3, #0 80096ec: f47f af0f bne.w 800950e } 80096f0: b005 add sp, #20 80096f2: f85d eb04 ldr.w lr, [sp], #4 frequency = HAL_RCC_GetPCLK1Freq(); 80096f6: f7fe bbd3 b.w 8007ea0 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 80096fa: 6810 ldr r0, [r2, #0] 80096fc: f410 7080 ands.w r0, r0, #256 @ 0x100 8009700: f43f af23 beq.w 800954a frequency = CSI_VALUE; 8009704: 4804 ldr r0, [pc, #16] @ (8009718 ) 8009706: e720 b.n 800954a 8009708: 58024400 .word 0x58024400 800970c: 017d7840 .word 0x017d7840 8009710: 00bb8000 .word 0x00bb8000 8009714: 03d09000 .word 0x03d09000 8009718: 003d0900 .word 0x003d0900 srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800971c: 4b28 ldr r3, [pc, #160] @ (80097c0 ) 800971e: 6d9b ldr r3, [r3, #88] @ 0x58 8009720: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 switch (srcclk) 8009724: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8009728: d037 beq.n 800979a 800972a: d814 bhi.n 8009756 800972c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8009730: d03f beq.n 80097b2 8009732: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8009736: d0bf beq.n 80096b8 8009738: 2b00 cmp r3, #0 800973a: f47f aee8 bne.w 800950e return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800973e: f7fe fb6f bl 8007e20 8009742: 4b1f ldr r3, [pc, #124] @ (80097c0 ) 8009744: 4a1f ldr r2, [pc, #124] @ (80097c4 ) 8009746: 6a1b ldr r3, [r3, #32] 8009748: f3c3 1302 ubfx r3, r3, #4, #3 800974c: 5cd3 ldrb r3, [r2, r3] 800974e: f003 031f and.w r3, r3, #31 8009752: 40d8 lsrs r0, r3 break; 8009754: e6f9 b.n 800954a switch (srcclk) 8009756: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800975a: d017 beq.n 800978c 800975c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8009760: d0bc beq.n 80096dc 8009762: e6d4 b.n 800950e if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 8009764: 6810 ldr r0, [r2, #0] 8009766: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 800976a: f43f aeee beq.w 800954a HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800976e: a801 add r0, sp, #4 8009770: f7ff fc96 bl 80090a0 frequency = pll2_clocks.PLL2_Q_Frequency; 8009774: 9802 ldr r0, [sp, #8] 8009776: e6e8 b.n 800954a if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 8009778: 6810 ldr r0, [r2, #0] 800977a: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000 800977e: f43f aee4 beq.w 800954a HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8009782: a801 add r0, sp, #4 8009784: f7ff fd26 bl 80091d4 frequency = pll3_clocks.PLL3_R_Frequency; 8009788: 9803 ldr r0, [sp, #12] 800978a: e6de b.n 800954a if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800978c: 4b0c ldr r3, [pc, #48] @ (80097c0 ) 800978e: 6818 ldr r0, [r3, #0] 8009790: f410 7080 ands.w r0, r0, #256 @ 0x100 8009794: f43f aed9 beq.w 800954a 8009798: e7b4 b.n 8009704 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800979a: 4b09 ldr r3, [pc, #36] @ (80097c0 ) 800979c: 6818 ldr r0, [r3, #0] 800979e: f010 0004 ands.w r0, r0, #4 80097a2: f43f aed2 beq.w 800954a frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80097a6: 681b ldr r3, [r3, #0] 80097a8: 4807 ldr r0, [pc, #28] @ (80097c8 ) 80097aa: f3c3 03c1 ubfx r3, r3, #3, #2 80097ae: 40d8 lsrs r0, r3 80097b0: e6cb b.n 800954a if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 80097b2: 4b03 ldr r3, [pc, #12] @ (80097c0 ) 80097b4: 6818 ldr r0, [r3, #0] 80097b6: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000 80097ba: f43f aec6 beq.w 800954a 80097be: e7d6 b.n 800976e 80097c0: 58024400 .word 0x58024400 80097c4: 08011a14 .word 0x08011a14 80097c8: 03d09000 .word 0x03d09000 080097cc : */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 80097cc: 2800 cmp r0, #0 80097ce: d038 beq.n 8009842 { 80097d0: b538 push {r3, r4, r5, lr} /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 80097d2: 7a43 ldrb r3, [r0, #9] 80097d4: 4604 mov r4, r0 80097d6: f003 02ff and.w r2, r3, #255 @ 0xff 80097da: b373 cbz r3, 800983a } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 80097dc: 6823 ldr r3, [r4, #0] hrng->State = HAL_RNG_STATE_BUSY; 80097de: 2202 movs r2, #2 MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 80097e0: 6861 ldr r1, [r4, #4] hrng->State = HAL_RNG_STATE_BUSY; 80097e2: 7262 strb r2, [r4, #9] MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 80097e4: 681a ldr r2, [r3, #0] 80097e6: f022 0220 bic.w r2, r2, #32 80097ea: 430a orrs r2, r1 80097ec: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 80097ee: 681a ldr r2, [r3, #0] 80097f0: f042 0204 orr.w r2, r2, #4 80097f4: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 80097f6: 685b ldr r3, [r3, #4] 80097f8: 0658 lsls r0, r3, #25 80097fa: d503 bpl.n 8009804 { hrng->State = HAL_RNG_STATE_ERROR; 80097fc: 2304 movs r3, #4 80097fe: 7263 strb r3, [r4, #9] return HAL_ERROR; 8009800: 2001 movs r0, #1 /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; /* Return function status */ return HAL_OK; } 8009802: bd38 pop {r3, r4, r5, pc} tickstart = HAL_GetTick(); 8009804: f7fa fbe4 bl 8003fd0 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 8009808: 6823 ldr r3, [r4, #0] tickstart = HAL_GetTick(); 800980a: 4605 mov r5, r0 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800980c: 685b ldr r3, [r3, #4] 800980e: 0759 lsls r1, r3, #29 8009810: d50d bpl.n 800982e if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 8009812: f7fa fbdd bl 8003fd0 8009816: 1b40 subs r0, r0, r5 if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 8009818: 6823 ldr r3, [r4, #0] if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800981a: 2802 cmp r0, #2 800981c: d9f6 bls.n 800980c if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800981e: 685a ldr r2, [r3, #4] 8009820: 0752 lsls r2, r2, #29 8009822: d5f3 bpl.n 800980c hrng->State = HAL_RNG_STATE_ERROR; 8009824: 2204 movs r2, #4 hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 8009826: 2302 movs r3, #2 hrng->State = HAL_RNG_STATE_ERROR; 8009828: 7262 strb r2, [r4, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800982a: 60e3 str r3, [r4, #12] return HAL_ERROR; 800982c: e7e8 b.n 8009800 hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800982e: 2300 movs r3, #0 hrng->State = HAL_RNG_STATE_READY; 8009830: 2201 movs r2, #1 return HAL_OK; 8009832: 4618 mov r0, r3 hrng->State = HAL_RNG_STATE_READY; 8009834: 7262 strb r2, [r4, #9] hrng->ErrorCode = HAL_RNG_ERROR_NONE; 8009836: 60e3 str r3, [r4, #12] } 8009838: bd38 pop {r3, r4, r5, pc} hrng->Lock = HAL_UNLOCKED; 800983a: 7202 strb r2, [r0, #8] HAL_RNG_MspInit(hrng); 800983c: f7f9 fa0a bl 8002c54 8009840: e7cc b.n 80097dc return HAL_ERROR; 8009842: 2001 movs r0, #1 } 8009844: 4770 bx lr 8009846: bf00 nop 08009848 : uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8009848: 6a03 ldr r3, [r0, #32] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 800984a: 6a02 ldr r2, [r0, #32] tmpccmrx &= ~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800984c: f023 0302 bic.w r3, r3, #2 TIMx->CCER &= ~TIM_CCER_CC1E; 8009850: f022 0201 bic.w r2, r2, #1 { 8009854: b470 push {r4, r5, r6} TIMx->CCER &= ~TIM_CCER_CC1E; 8009856: 6202 str r2, [r0, #32] tmpccmrx &= ~TIM_CCMR1_CC1S; 8009858: 4a17 ldr r2, [pc, #92] @ (80098b8 ) tmpcr2 = TIMx->CR2; 800985a: 6844 ldr r4, [r0, #4] tmpccmrx = TIMx->CCMR1; 800985c: 6985 ldr r5, [r0, #24] tmpccmrx &= ~TIM_CCMR1_CC1S; 800985e: 402a ands r2, r5 tmpccmrx |= OC_Config->OCMode; 8009860: 680d ldr r5, [r1, #0] 8009862: 432a orrs r2, r5 /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8009864: 688d ldr r5, [r1, #8] 8009866: 432b orrs r3, r5 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8009868: 4d14 ldr r5, [pc, #80] @ (80098bc ) 800986a: 42a8 cmp r0, r5 800986c: d00f beq.n 800988e 800986e: f505 6580 add.w r5, r5, #1024 @ 0x400 8009872: 42a8 cmp r0, r5 8009874: d00b beq.n 800988e 8009876: f505 5570 add.w r5, r5, #15360 @ 0x3c00 800987a: 42a8 cmp r0, r5 800987c: d007 beq.n 800988e 800987e: f505 6580 add.w r5, r5, #1024 @ 0x400 8009882: 42a8 cmp r0, r5 8009884: d003 beq.n 800988e 8009886: f505 6580 add.w r5, r5, #1024 @ 0x400 800988a: 42a8 cmp r0, r5 800988c: d10d bne.n 80098aa assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 800988e: 68cd ldr r5, [r1, #12] tmpccer &= ~TIM_CCER_CC1NP; 8009890: f023 0308 bic.w r3, r3, #8 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; tmpcr2 &= ~TIM_CR2_OIS1N; 8009894: f424 7440 bic.w r4, r4, #768 @ 0x300 tmpccer |= OC_Config->OCNPolarity; 8009898: 432b orrs r3, r5 /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800989a: e9d1 6505 ldrd r6, r5, [r1, #20] tmpccer &= ~TIM_CCER_CC1NE; 800989e: f023 0304 bic.w r3, r3, #4 tmpcr2 |= OC_Config->OCNIdleState; 80098a2: ea46 0c05 orr.w ip, r6, r5 80098a6: ea4c 0404 orr.w r4, ip, r4 /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80098aa: 6849 ldr r1, [r1, #4] TIMx->CR2 = tmpcr2; 80098ac: 6044 str r4, [r0, #4] TIMx->CCMR1 = tmpccmrx; 80098ae: 6182 str r2, [r0, #24] TIMx->CCR1 = OC_Config->Pulse; 80098b0: 6341 str r1, [r0, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80098b2: 6203 str r3, [r0, #32] } 80098b4: bc70 pop {r4, r5, r6} 80098b6: 4770 bx lr 80098b8: fffeff8c .word 0xfffeff8c 80098bc: 40010000 .word 0x40010000 080098c0 : uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80098c0: 6a03 ldr r3, [r0, #32] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 80098c2: 6a02 ldr r2, [r0, #32] tmpccmrx &= ~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 80098c4: f423 7300 bic.w r3, r3, #512 @ 0x200 TIMx->CCER &= ~TIM_CCER_CC3E; 80098c8: f422 7280 bic.w r2, r2, #256 @ 0x100 { 80098cc: b470 push {r4, r5, r6} TIMx->CCER &= ~TIM_CCER_CC3E; 80098ce: 6202 str r2, [r0, #32] tmpccmrx &= ~TIM_CCMR2_CC3S; 80098d0: 4a18 ldr r2, [pc, #96] @ (8009934 ) tmpcr2 = TIMx->CR2; 80098d2: 6844 ldr r4, [r0, #4] tmpccmrx = TIMx->CCMR2; 80098d4: 69c5 ldr r5, [r0, #28] tmpccmrx &= ~TIM_CCMR2_CC3S; 80098d6: 402a ands r2, r5 tmpccmrx |= OC_Config->OCMode; 80098d8: 680d ldr r5, [r1, #0] 80098da: 432a orrs r2, r5 /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 80098dc: 688d ldr r5, [r1, #8] 80098de: ea43 2305 orr.w r3, r3, r5, lsl #8 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 80098e2: 4d15 ldr r5, [pc, #84] @ (8009938 ) 80098e4: 42a8 cmp r0, r5 80098e6: d00f beq.n 8009908 80098e8: f505 6580 add.w r5, r5, #1024 @ 0x400 80098ec: 42a8 cmp r0, r5 80098ee: d00b beq.n 8009908 tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) 80098f0: 4e12 ldr r6, [pc, #72] @ (800993c ) 80098f2: f505 4580 add.w r5, r5, #16384 @ 0x4000 80098f6: 42a8 cmp r0, r5 80098f8: bf18 it ne 80098fa: 42b0 cmpne r0, r6 80098fc: d00b beq.n 8009916 80098fe: f505 6580 add.w r5, r5, #1024 @ 0x400 8009902: 42a8 cmp r0, r5 8009904: d10f bne.n 8009926 8009906: e006 b.n 8009916 tmpccer &= ~TIM_CCER_CC3NP; 8009908: f423 6300 bic.w r3, r3, #2048 @ 0x800 tmpccer |= (OC_Config->OCNPolarity << 8U); 800990c: 68cd ldr r5, [r1, #12] 800990e: ea43 2305 orr.w r3, r3, r5, lsl #8 tmpccer &= ~TIM_CCER_CC3NE; 8009912: f423 6380 bic.w r3, r3, #1024 @ 0x400 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; 8009916: f424 5440 bic.w r4, r4, #12288 @ 0x3000 /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800991a: e9d1 6505 ldrd r6, r5, [r1, #20] 800991e: ea46 0c05 orr.w ip, r6, r5 8009922: ea44 140c orr.w r4, r4, ip, lsl #4 /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8009926: 6849 ldr r1, [r1, #4] TIMx->CR2 = tmpcr2; 8009928: 6044 str r4, [r0, #4] TIMx->CCMR2 = tmpccmrx; 800992a: 61c2 str r2, [r0, #28] TIMx->CCR3 = OC_Config->Pulse; 800992c: 63c1 str r1, [r0, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800992e: 6203 str r3, [r0, #32] } 8009930: bc70 pop {r4, r5, r6} 8009932: 4770 bx lr 8009934: fffeff8c .word 0xfffeff8c 8009938: 40010000 .word 0x40010000 800993c: 40014000 .word 0x40014000 08009940 : if (htim == NULL) 8009940: 2800 cmp r0, #0 8009942: f000 8094 beq.w 8009a6e { 8009946: b5f8 push {r3, r4, r5, r6, r7, lr} if (htim->State == HAL_TIM_STATE_RESET) 8009948: f890 303d ldrb.w r3, [r0, #61] @ 0x3d 800994c: 4604 mov r4, r0 800994e: f003 02ff and.w r2, r3, #255 @ 0xff 8009952: 2b00 cmp r3, #0 8009954: d07b beq.n 8009a4e TIM_Base_SetConfig(htim->Instance, &htim->Init); 8009956: 6823 ldr r3, [r4, #0] htim->State = HAL_TIM_STATE_BUSY; 8009958: 2202 movs r2, #2 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800995a: 4946 ldr r1, [pc, #280] @ (8009a74 ) 800995c: 4846 ldr r0, [pc, #280] @ (8009a78 ) 800995e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8009962: eba3 0101 sub.w r1, r3, r1 htim->State = HAL_TIM_STATE_BUSY; 8009966: f884 203d strb.w r2, [r4, #61] @ 0x3d if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800996a: eba3 0e00 sub.w lr, r3, r0 tmpcr1 = TIMx->CR1; 800996e: 681a ldr r2, [r3, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009970: fab1 f181 clz r1, r1 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8009974: 69a7 ldr r7, [r4, #24] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009976: fabe fe8e clz lr, lr TIMx->PSC = Structure->Prescaler; 800997a: 6865 ldr r5, [r4, #4] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800997c: ea4f 1151 mov.w r1, r1, lsr #5 TIMx->ARR = (uint32_t)Structure->Period ; 8009980: 68e6 ldr r6, [r4, #12] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009982: ea4f 1e5e mov.w lr, lr, lsr #5 8009986: d020 beq.n 80099ca 8009988: b9f9 cbnz r1, 80099ca 800998a: f8df c0fc ldr.w ip, [pc, #252] @ 8009a88 800998e: 4563 cmp r3, ip 8009990: d01b beq.n 80099ca 8009992: f50c 6c80 add.w ip, ip, #1024 @ 0x400 8009996: 4563 cmp r3, ip 8009998: d017 beq.n 80099ca 800999a: f50c 6c80 add.w ip, ip, #1024 @ 0x400 800999e: 4563 cmp r3, ip 80099a0: d013 beq.n 80099ca 80099a2: f1be 0f00 cmp.w lr, #0 80099a6: d110 bne.n 80099ca if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80099a8: 4834 ldr r0, [pc, #208] @ (8009a7c ) 80099aa: 4935 ldr r1, [pc, #212] @ (8009a80 ) 80099ac: 428b cmp r3, r1 80099ae: bf18 it ne 80099b0: 4283 cmpne r3, r0 80099b2: d051 beq.n 8009a58 80099b4: f501 6180 add.w r1, r1, #1024 @ 0x400 80099b8: 428b cmp r3, r1 80099ba: d04d beq.n 8009a58 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80099bc: f022 0280 bic.w r2, r2, #128 @ 0x80 80099c0: 433a orrs r2, r7 TIMx->CR1 = tmpcr1; 80099c2: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 80099c4: 62de str r6, [r3, #44] @ 0x2c TIMx->PSC = Structure->Prescaler; 80099c6: 629d str r5, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80099c8: e01d b.n 8009a06 tmpcr1 |= Structure->CounterMode; 80099ca: 68a0 ldr r0, [r4, #8] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80099cc: f022 0270 bic.w r2, r2, #112 @ 0x70 tmpcr1 |= Structure->CounterMode; 80099d0: 4302 orrs r2, r0 tmpcr1 |= (uint32_t)Structure->ClockDivision; 80099d2: 6920 ldr r0, [r4, #16] tmpcr1 &= ~TIM_CR1_CKD; 80099d4: f422 7240 bic.w r2, r2, #768 @ 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 80099d8: 4302 orrs r2, r0 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80099da: f022 0280 bic.w r2, r2, #128 @ 0x80 80099de: 433a orrs r2, r7 TIMx->CR1 = tmpcr1; 80099e0: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 80099e2: 62de str r6, [r3, #44] @ 0x2c TIMx->PSC = Structure->Prescaler; 80099e4: 629d str r5, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80099e6: b961 cbnz r1, 8009a02 80099e8: f1be 0f00 cmp.w lr, #0 80099ec: d109 bne.n 8009a02 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80099ee: 4925 ldr r1, [pc, #148] @ (8009a84 ) 80099f0: 4a22 ldr r2, [pc, #136] @ (8009a7c ) if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80099f2: 4293 cmp r3, r2 80099f4: bf18 it ne 80099f6: 428b cmpne r3, r1 80099f8: d003 beq.n 8009a02 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80099fa: f502 6280 add.w r2, r2, #1024 @ 0x400 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80099fe: 4293 cmp r3, r2 8009a00: d101 bne.n 8009a06 TIMx->RCR = Structure->RepetitionCounter; 8009a02: 6962 ldr r2, [r4, #20] 8009a04: 631a str r2, [r3, #48] @ 0x30 TIMx->EGR = TIM_EGR_UG; 8009a06: 2201 movs r2, #1 8009a08: 615a str r2, [r3, #20] if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8009a0a: 691a ldr r2, [r3, #16] 8009a0c: 07d2 lsls r2, r2, #31 8009a0e: d503 bpl.n 8009a18 CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8009a10: 691a ldr r2, [r3, #16] 8009a12: f022 0201 bic.w r2, r2, #1 8009a16: 611a str r2, [r3, #16] htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8009a18: 2301 movs r3, #1 return HAL_OK; 8009a1a: 2000 movs r0, #0 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8009a1c: f884 3048 strb.w r3, [r4, #72] @ 0x48 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8009a20: f884 303e strb.w r3, [r4, #62] @ 0x3e 8009a24: f884 303f strb.w r3, [r4, #63] @ 0x3f 8009a28: f884 3040 strb.w r3, [r4, #64] @ 0x40 8009a2c: f884 3041 strb.w r3, [r4, #65] @ 0x41 8009a30: f884 3042 strb.w r3, [r4, #66] @ 0x42 8009a34: f884 3043 strb.w r3, [r4, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8009a38: f884 3044 strb.w r3, [r4, #68] @ 0x44 8009a3c: f884 3045 strb.w r3, [r4, #69] @ 0x45 8009a40: f884 3046 strb.w r3, [r4, #70] @ 0x46 8009a44: f884 3047 strb.w r3, [r4, #71] @ 0x47 htim->State = HAL_TIM_STATE_READY; 8009a48: f884 303d strb.w r3, [r4, #61] @ 0x3d } 8009a4c: bdf8 pop {r3, r4, r5, r6, r7, pc} htim->Lock = HAL_UNLOCKED; 8009a4e: f880 203c strb.w r2, [r0, #60] @ 0x3c HAL_TIM_Base_MspInit(htim); 8009a52: f7f9 f95b bl 8002d0c 8009a56: e77e b.n 8009956 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8009a58: 6921 ldr r1, [r4, #16] tmpcr1 &= ~TIM_CR1_CKD; 8009a5a: f422 7240 bic.w r2, r2, #768 @ 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8009a5e: 430a orrs r2, r1 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8009a60: f022 0280 bic.w r2, r2, #128 @ 0x80 8009a64: 433a orrs r2, r7 TIMx->CR1 = tmpcr1; 8009a66: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 8009a68: 62de str r6, [r3, #44] @ 0x2c TIMx->PSC = Structure->Prescaler; 8009a6a: 629d str r5, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8009a6c: e7bf b.n 80099ee return HAL_ERROR; 8009a6e: 2001 movs r0, #1 } 8009a70: 4770 bx lr 8009a72: bf00 nop 8009a74: 40010000 .word 0x40010000 8009a78: 40010400 .word 0x40010400 8009a7c: 40014000 .word 0x40014000 8009a80: 40014400 .word 0x40014400 8009a84: 40014800 .word 0x40014800 8009a88: 40000400 .word 0x40000400 08009a8c : if (htim->State != HAL_TIM_STATE_READY) 8009a8c: f890 303d ldrb.w r3, [r0, #61] @ 0x3d 8009a90: 2b01 cmp r3, #1 8009a92: d139 bne.n 8009b08 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009a94: 6802 ldr r2, [r0, #0] 8009a96: 4b1d ldr r3, [pc, #116] @ (8009b0c ) 8009a98: 491d ldr r1, [pc, #116] @ (8009b10 ) 8009a9a: f1b2 4f80 cmp.w r2, #1073741824 @ 0x40000000 8009a9e: bf18 it ne 8009aa0: 429a cmpne r2, r3 { 8009aa2: b430 push {r4, r5} if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009aa4: bf0c ite eq 8009aa6: 2301 moveq r3, #1 8009aa8: 2300 movne r3, #0 8009aaa: 4d1a ldr r5, [pc, #104] @ (8009b14 ) htim->State = HAL_TIM_STATE_BUSY; 8009aac: 2402 movs r4, #2 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009aae: 42aa cmp r2, r5 8009ab0: bf08 it eq 8009ab2: f043 0301 orreq.w r3, r3, #1 htim->State = HAL_TIM_STATE_BUSY; 8009ab6: f880 403d strb.w r4, [r0, #61] @ 0x3d if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009aba: 4c17 ldr r4, [pc, #92] @ (8009b18 ) 8009abc: 428a cmp r2, r1 8009abe: bf08 it eq 8009ac0: f043 0301 orreq.w r3, r3, #1 8009ac4: 4815 ldr r0, [pc, #84] @ (8009b1c ) 8009ac6: f501 5180 add.w r1, r1, #4096 @ 0x1000 8009aca: 42a2 cmp r2, r4 8009acc: bf08 it eq 8009ace: f043 0301 orreq.w r3, r3, #1 8009ad2: 4282 cmp r2, r0 8009ad4: bf08 it eq 8009ad6: f043 0301 orreq.w r3, r3, #1 8009ada: 428a cmp r2, r1 8009adc: bf08 it eq 8009ade: f043 0301 orreq.w r3, r3, #1 8009ae2: b913 cbnz r3, 8009aea 8009ae4: 4b0e ldr r3, [pc, #56] @ (8009b20 ) 8009ae6: 429a cmp r2, r3 8009ae8: d107 bne.n 8009afa tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8009aea: 6891 ldr r1, [r2, #8] 8009aec: 4b0d ldr r3, [pc, #52] @ (8009b24 ) 8009aee: 400b ands r3, r1 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8009af0: 2b06 cmp r3, #6 8009af2: d006 beq.n 8009b02 8009af4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8009af8: d003 beq.n 8009b02 __HAL_TIM_ENABLE(htim); 8009afa: 6813 ldr r3, [r2, #0] 8009afc: f043 0301 orr.w r3, r3, #1 8009b00: 6013 str r3, [r2, #0] return HAL_OK; 8009b02: 2000 movs r0, #0 } 8009b04: bc30 pop {r4, r5} 8009b06: 4770 bx lr return HAL_ERROR; 8009b08: 2001 movs r0, #1 } 8009b0a: 4770 bx lr 8009b0c: 40010000 .word 0x40010000 8009b10: 40000800 .word 0x40000800 8009b14: 40000400 .word 0x40000400 8009b18: 40000c00 .word 0x40000c00 8009b1c: 40010400 .word 0x40010400 8009b20: 40014000 .word 0x40014000 8009b24: 00010007 .word 0x00010007 08009b28 : if (htim->State != HAL_TIM_STATE_READY) 8009b28: f890 303d ldrb.w r3, [r0, #61] @ 0x3d 8009b2c: 2b01 cmp r3, #1 8009b2e: d13d bne.n 8009bac __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8009b30: 6802 ldr r2, [r0, #0] htim->State = HAL_TIM_STATE_BUSY; 8009b32: 2102 movs r1, #2 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009b34: 4b1e ldr r3, [pc, #120] @ (8009bb0 ) 8009b36: f1b2 4f80 cmp.w r2, #1073741824 @ 0x40000000 8009b3a: bf18 it ne 8009b3c: 429a cmpne r2, r3 { 8009b3e: b430 push {r4, r5} if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009b40: bf0c ite eq 8009b42: 2301 moveq r3, #1 8009b44: 2300 movne r3, #0 8009b46: 4d1b ldr r5, [pc, #108] @ (8009bb4 ) 8009b48: 4c1b ldr r4, [pc, #108] @ (8009bb8 ) 8009b4a: 42aa cmp r2, r5 8009b4c: bf08 it eq 8009b4e: f043 0301 orreq.w r3, r3, #1 htim->State = HAL_TIM_STATE_BUSY; 8009b52: f880 103d strb.w r1, [r0, #61] @ 0x3d __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8009b56: 68d1 ldr r1, [r2, #12] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009b58: 42a2 cmp r2, r4 8009b5a: bf08 it eq 8009b5c: f043 0301 orreq.w r3, r3, #1 8009b60: f504 6480 add.w r4, r4, #1024 @ 0x400 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8009b64: f041 0101 orr.w r1, r1, #1 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009b68: 4814 ldr r0, [pc, #80] @ (8009bbc ) 8009b6a: 42a2 cmp r2, r4 8009b6c: bf08 it eq 8009b6e: f043 0301 orreq.w r3, r3, #1 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8009b72: 60d1 str r1, [r2, #12] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8009b74: 4282 cmp r2, r0 8009b76: bf08 it eq 8009b78: f043 0301 orreq.w r3, r3, #1 8009b7c: 4910 ldr r1, [pc, #64] @ (8009bc0 ) 8009b7e: 428a cmp r2, r1 8009b80: bf08 it eq 8009b82: f043 0301 orreq.w r3, r3, #1 8009b86: b913 cbnz r3, 8009b8e 8009b88: 4b0e ldr r3, [pc, #56] @ (8009bc4 ) 8009b8a: 429a cmp r2, r3 8009b8c: d107 bne.n 8009b9e tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8009b8e: 6891 ldr r1, [r2, #8] 8009b90: 4b0d ldr r3, [pc, #52] @ (8009bc8 ) 8009b92: 400b ands r3, r1 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8009b94: 2b06 cmp r3, #6 8009b96: d006 beq.n 8009ba6 8009b98: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8009b9c: d003 beq.n 8009ba6 __HAL_TIM_ENABLE(htim); 8009b9e: 6813 ldr r3, [r2, #0] 8009ba0: f043 0301 orr.w r3, r3, #1 8009ba4: 6013 str r3, [r2, #0] return HAL_OK; 8009ba6: 2000 movs r0, #0 } 8009ba8: bc30 pop {r4, r5} 8009baa: 4770 bx lr return HAL_ERROR; 8009bac: 2001 movs r0, #1 } 8009bae: 4770 bx lr 8009bb0: 40010000 .word 0x40010000 8009bb4: 40000400 .word 0x40000400 8009bb8: 40000800 .word 0x40000800 8009bbc: 40010400 .word 0x40010400 8009bc0: 40001800 .word 0x40001800 8009bc4: 40014000 .word 0x40014000 8009bc8: 00010007 .word 0x00010007 08009bcc : if (htim == NULL) 8009bcc: 2800 cmp r0, #0 8009bce: f000 8094 beq.w 8009cfa { 8009bd2: b5f8 push {r3, r4, r5, r6, r7, lr} if (htim->State == HAL_TIM_STATE_RESET) 8009bd4: f890 303d ldrb.w r3, [r0, #61] @ 0x3d 8009bd8: 4604 mov r4, r0 8009bda: f003 02ff and.w r2, r3, #255 @ 0xff 8009bde: 2b00 cmp r3, #0 8009be0: d07b beq.n 8009cda TIM_Base_SetConfig(htim->Instance, &htim->Init); 8009be2: 6823 ldr r3, [r4, #0] htim->State = HAL_TIM_STATE_BUSY; 8009be4: 2202 movs r2, #2 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009be6: 4946 ldr r1, [pc, #280] @ (8009d00 ) 8009be8: 4846 ldr r0, [pc, #280] @ (8009d04 ) 8009bea: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8009bee: eba3 0101 sub.w r1, r3, r1 htim->State = HAL_TIM_STATE_BUSY; 8009bf2: f884 203d strb.w r2, [r4, #61] @ 0x3d if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009bf6: eba3 0e00 sub.w lr, r3, r0 tmpcr1 = TIMx->CR1; 8009bfa: 681a ldr r2, [r3, #0] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009bfc: fab1 f181 clz r1, r1 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8009c00: 69a7 ldr r7, [r4, #24] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009c02: fabe fe8e clz lr, lr TIMx->PSC = Structure->Prescaler; 8009c06: 6865 ldr r5, [r4, #4] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009c08: ea4f 1151 mov.w r1, r1, lsr #5 TIMx->ARR = (uint32_t)Structure->Period ; 8009c0c: 68e6 ldr r6, [r4, #12] if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8009c0e: ea4f 1e5e mov.w lr, lr, lsr #5 8009c12: d020 beq.n 8009c56 8009c14: b9f9 cbnz r1, 8009c56 8009c16: f8df c0fc ldr.w ip, [pc, #252] @ 8009d14 8009c1a: 4563 cmp r3, ip 8009c1c: d01b beq.n 8009c56 8009c1e: f50c 6c80 add.w ip, ip, #1024 @ 0x400 8009c22: 4563 cmp r3, ip 8009c24: d017 beq.n 8009c56 8009c26: f50c 6c80 add.w ip, ip, #1024 @ 0x400 8009c2a: 4563 cmp r3, ip 8009c2c: d013 beq.n 8009c56 8009c2e: f1be 0f00 cmp.w lr, #0 8009c32: d110 bne.n 8009c56 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8009c34: 4834 ldr r0, [pc, #208] @ (8009d08 ) 8009c36: 4935 ldr r1, [pc, #212] @ (8009d0c ) 8009c38: 428b cmp r3, r1 8009c3a: bf18 it ne 8009c3c: 4283 cmpne r3, r0 8009c3e: d051 beq.n 8009ce4 8009c40: f501 6180 add.w r1, r1, #1024 @ 0x400 8009c44: 428b cmp r3, r1 8009c46: d04d beq.n 8009ce4 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8009c48: f022 0280 bic.w r2, r2, #128 @ 0x80 8009c4c: 433a orrs r2, r7 TIMx->CR1 = tmpcr1; 8009c4e: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 8009c50: 62de str r6, [r3, #44] @ 0x2c TIMx->PSC = Structure->Prescaler; 8009c52: 629d str r5, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8009c54: e01d b.n 8009c92 tmpcr1 |= Structure->CounterMode; 8009c56: 68a0 ldr r0, [r4, #8] tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8009c58: f022 0270 bic.w r2, r2, #112 @ 0x70 tmpcr1 |= Structure->CounterMode; 8009c5c: 4302 orrs r2, r0 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8009c5e: 6920 ldr r0, [r4, #16] tmpcr1 &= ~TIM_CR1_CKD; 8009c60: f422 7240 bic.w r2, r2, #768 @ 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8009c64: 4302 orrs r2, r0 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8009c66: f022 0280 bic.w r2, r2, #128 @ 0x80 8009c6a: 433a orrs r2, r7 TIMx->CR1 = tmpcr1; 8009c6c: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 8009c6e: 62de str r6, [r3, #44] @ 0x2c TIMx->PSC = Structure->Prescaler; 8009c70: 629d str r5, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8009c72: b961 cbnz r1, 8009c8e 8009c74: f1be 0f00 cmp.w lr, #0 8009c78: d109 bne.n 8009c8e if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8009c7a: 4925 ldr r1, [pc, #148] @ (8009d10 ) 8009c7c: 4a22 ldr r2, [pc, #136] @ (8009d08 ) if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8009c7e: 4293 cmp r3, r2 8009c80: bf18 it ne 8009c82: 428b cmpne r3, r1 8009c84: d003 beq.n 8009c8e if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8009c86: f502 6280 add.w r2, r2, #1024 @ 0x400 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8009c8a: 4293 cmp r3, r2 8009c8c: d101 bne.n 8009c92 TIMx->RCR = Structure->RepetitionCounter; 8009c8e: 6962 ldr r2, [r4, #20] 8009c90: 631a str r2, [r3, #48] @ 0x30 TIMx->EGR = TIM_EGR_UG; 8009c92: 2201 movs r2, #1 8009c94: 615a str r2, [r3, #20] if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 8009c96: 691a ldr r2, [r3, #16] 8009c98: 07d2 lsls r2, r2, #31 8009c9a: d503 bpl.n 8009ca4 CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 8009c9c: 691a ldr r2, [r3, #16] 8009c9e: f022 0201 bic.w r2, r2, #1 8009ca2: 611a str r2, [r3, #16] htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8009ca4: 2301 movs r3, #1 return HAL_OK; 8009ca6: 2000 movs r0, #0 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8009ca8: f884 3048 strb.w r3, [r4, #72] @ 0x48 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8009cac: f884 303e strb.w r3, [r4, #62] @ 0x3e 8009cb0: f884 303f strb.w r3, [r4, #63] @ 0x3f 8009cb4: f884 3040 strb.w r3, [r4, #64] @ 0x40 8009cb8: f884 3041 strb.w r3, [r4, #65] @ 0x41 8009cbc: f884 3042 strb.w r3, [r4, #66] @ 0x42 8009cc0: f884 3043 strb.w r3, [r4, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8009cc4: f884 3044 strb.w r3, [r4, #68] @ 0x44 8009cc8: f884 3045 strb.w r3, [r4, #69] @ 0x45 8009ccc: f884 3046 strb.w r3, [r4, #70] @ 0x46 8009cd0: f884 3047 strb.w r3, [r4, #71] @ 0x47 htim->State = HAL_TIM_STATE_READY; 8009cd4: f884 303d strb.w r3, [r4, #61] @ 0x3d } 8009cd8: bdf8 pop {r3, r4, r5, r6, r7, pc} htim->Lock = HAL_UNLOCKED; 8009cda: f880 203c strb.w r2, [r0, #60] @ 0x3c HAL_TIM_PWM_MspInit(htim); 8009cde: f7f8 ffe7 bl 8002cb0 8009ce2: e77e b.n 8009be2 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8009ce4: 6921 ldr r1, [r4, #16] tmpcr1 &= ~TIM_CR1_CKD; 8009ce6: f422 7240 bic.w r2, r2, #768 @ 0x300 tmpcr1 |= (uint32_t)Structure->ClockDivision; 8009cea: 430a orrs r2, r1 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8009cec: f022 0280 bic.w r2, r2, #128 @ 0x80 8009cf0: 433a orrs r2, r7 TIMx->CR1 = tmpcr1; 8009cf2: 601a str r2, [r3, #0] TIMx->ARR = (uint32_t)Structure->Period ; 8009cf4: 62de str r6, [r3, #44] @ 0x2c TIMx->PSC = Structure->Prescaler; 8009cf6: 629d str r5, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8009cf8: e7bf b.n 8009c7a return HAL_ERROR; 8009cfa: 2001 movs r0, #1 } 8009cfc: 4770 bx lr 8009cfe: bf00 nop 8009d00: 40010000 .word 0x40010000 8009d04: 40010400 .word 0x40010400 8009d08: 40014000 .word 0x40014000 8009d0c: 40014400 .word 0x40014400 8009d10: 40014800 .word 0x40014800 8009d14: 40000400 .word 0x40000400 08009d18 : HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 8009d18: 2910 cmp r1, #16 8009d1a: d80a bhi.n 8009d32 8009d1c: e8df f001 tbb [pc, r1] 8009d20: 09090919 .word 0x09090919 8009d24: 09090956 .word 0x09090956 8009d28: 0909095e .word 0x0909095e 8009d2c: 09090966 .word 0x09090966 8009d30: 6e .byte 0x6e 8009d31: 00 .byte 0x00 8009d32: f890 3043 ldrb.w r3, [r0, #67] @ 0x43 8009d36: 2b01 cmp r3, #1 8009d38: d171 bne.n 8009e1e 8009d3a: 1f0b subs r3, r1, #4 8009d3c: 2b0c cmp r3, #12 8009d3e: d865 bhi.n 8009e0c 8009d40: e8df f003 tbb [pc, r3] 8009d44: 64646448 .word 0x64646448 8009d48: 64646450 .word 0x64646450 8009d4c: 64646458 .word 0x64646458 8009d50: 60 .byte 0x60 8009d51: 00 .byte 0x00 8009d52: f890 303e ldrb.w r3, [r0, #62] @ 0x3e 8009d56: 2b01 cmp r3, #1 8009d58: d161 bne.n 8009e1e 8009d5a: 2302 movs r3, #2 8009d5c: f880 303e strb.w r3, [r0, #62] @ 0x3e 8009d60: 6803 ldr r3, [r0, #0] 8009d62: f001 011f and.w r1, r1, #31 8009d66: 2201 movs r2, #1 8009d68: 6a18 ldr r0, [r3, #32] 8009d6a: 408a lsls r2, r1 8009d6c: ea20 0002 bic.w r0, r0, r2 8009d70: b410 push {r4} 8009d72: 6218 str r0, [r3, #32] 8009d74: 4c33 ldr r4, [pc, #204] @ (8009e44 ) 8009d76: 6a19 ldr r1, [r3, #32] 8009d78: 42a3 cmp r3, r4 8009d7a: ea42 0201 orr.w r2, r2, r1 8009d7e: 621a str r2, [r3, #32] 8009d80: d048 beq.n 8009e14 8009d82: 4a31 ldr r2, [pc, #196] @ (8009e48 ) 8009d84: 4293 cmp r3, r2 8009d86: d045 beq.n 8009e14 8009d88: f502 5270 add.w r2, r2, #15360 @ 0x3c00 8009d8c: 4293 cmp r3, r2 8009d8e: d041 beq.n 8009e14 8009d90: f502 6280 add.w r2, r2, #1024 @ 0x400 8009d94: 4293 cmp r3, r2 8009d96: d044 beq.n 8009e22 8009d98: f502 6280 add.w r2, r2, #1024 @ 0x400 8009d9c: 4293 cmp r3, r2 8009d9e: d040 beq.n 8009e22 8009da0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8009da4: d002 beq.n 8009dac 8009da6: 4a29 ldr r2, [pc, #164] @ (8009e4c ) 8009da8: 4293 cmp r3, r2 8009daa: d13f bne.n 8009e2c 8009dac: 6899 ldr r1, [r3, #8] 8009dae: 4a28 ldr r2, [pc, #160] @ (8009e50 ) 8009db0: 400a ands r2, r1 8009db2: 2a06 cmp r2, #6 8009db4: d006 beq.n 8009dc4 8009db6: f5b2 3f80 cmp.w r2, #65536 @ 0x10000 8009dba: d003 beq.n 8009dc4 8009dbc: 681a ldr r2, [r3, #0] 8009dbe: f042 0201 orr.w r2, r2, #1 8009dc2: 601a str r2, [r3, #0] 8009dc4: 2000 movs r0, #0 8009dc6: f85d 4b04 ldr.w r4, [sp], #4 8009dca: 4770 bx lr 8009dcc: f890 303f ldrb.w r3, [r0, #63] @ 0x3f 8009dd0: 2b01 cmp r3, #1 8009dd2: d124 bne.n 8009e1e 8009dd4: 2302 movs r3, #2 8009dd6: f880 303f strb.w r3, [r0, #63] @ 0x3f 8009dda: e7c1 b.n 8009d60 8009ddc: f890 3040 ldrb.w r3, [r0, #64] @ 0x40 8009de0: 2b01 cmp r3, #1 8009de2: d11c bne.n 8009e1e 8009de4: 2302 movs r3, #2 8009de6: f880 3040 strb.w r3, [r0, #64] @ 0x40 8009dea: e7b9 b.n 8009d60 8009dec: f890 3041 ldrb.w r3, [r0, #65] @ 0x41 8009df0: 2b01 cmp r3, #1 8009df2: d114 bne.n 8009e1e 8009df4: 2302 movs r3, #2 8009df6: f880 3041 strb.w r3, [r0, #65] @ 0x41 8009dfa: e7b1 b.n 8009d60 8009dfc: f890 3042 ldrb.w r3, [r0, #66] @ 0x42 8009e00: 2b01 cmp r3, #1 8009e02: d10c bne.n 8009e1e 8009e04: 2302 movs r3, #2 8009e06: f880 3042 strb.w r3, [r0, #66] @ 0x42 8009e0a: e7a9 b.n 8009d60 8009e0c: 2302 movs r3, #2 8009e0e: f880 3043 strb.w r3, [r0, #67] @ 0x43 8009e12: e7a5 b.n 8009d60 8009e14: 6c5a ldr r2, [r3, #68] @ 0x44 8009e16: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8009e1a: 645a str r2, [r3, #68] @ 0x44 8009e1c: e7c6 b.n 8009dac 8009e1e: 2001 movs r0, #1 8009e20: 4770 bx lr 8009e22: 6c5a ldr r2, [r3, #68] @ 0x44 8009e24: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8009e28: 645a str r2, [r3, #68] @ 0x44 8009e2a: e7c7 b.n 8009dbc 8009e2c: 4909 ldr r1, [pc, #36] @ (8009e54 ) 8009e2e: f502 6200 add.w r2, r2, #2048 @ 0x800 8009e32: 4293 cmp r3, r2 8009e34: bf18 it ne 8009e36: 428b cmpne r3, r1 8009e38: d0b8 beq.n 8009dac 8009e3a: f502 6240 add.w r2, r2, #3072 @ 0xc00 8009e3e: 4293 cmp r3, r2 8009e40: d1bc bne.n 8009dbc 8009e42: e7b3 b.n 8009dac 8009e44: 40010000 .word 0x40010000 8009e48: 40010400 .word 0x40010400 8009e4c: 40000400 .word 0x40000400 8009e50: 00010007 .word 0x00010007 8009e54: 40000800 .word 0x40000800 08009e58 : HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 8009e58: 6803 ldr r3, [r0, #0] 8009e5a: f001 0c1f and.w ip, r1, #31 8009e5e: 2201 movs r2, #1 8009e60: b410 push {r4} 8009e62: fa02 f20c lsl.w r2, r2, ip 8009e66: 6a1c ldr r4, [r3, #32] 8009e68: ea24 0402 bic.w r4, r4, r2 8009e6c: 4a37 ldr r2, [pc, #220] @ (8009f4c ) 8009e6e: 621c str r4, [r3, #32] 8009e70: 6a1c ldr r4, [r3, #32] 8009e72: 621c str r4, [r3, #32] 8009e74: 4c36 ldr r4, [pc, #216] @ (8009f50 ) 8009e76: 42a3 cmp r3, r4 8009e78: bf18 it ne 8009e7a: 4293 cmpne r3, r2 8009e7c: f504 5470 add.w r4, r4, #15360 @ 0x3c00 8009e80: bf0c ite eq 8009e82: 2201 moveq r2, #1 8009e84: 2200 movne r2, #0 8009e86: 42a3 cmp r3, r4 8009e88: bf08 it eq 8009e8a: f042 0201 orreq.w r2, r2, #1 8009e8e: f504 6480 add.w r4, r4, #1024 @ 0x400 8009e92: 42a3 cmp r3, r4 8009e94: bf08 it eq 8009e96: f042 0201 orreq.w r2, r2, #1 8009e9a: b912 cbnz r2, 8009ea2 8009e9c: 4a2d ldr r2, [pc, #180] @ (8009f54 ) 8009e9e: 4293 cmp r3, r2 8009ea0: d10d bne.n 8009ebe 8009ea2: 6a1c ldr r4, [r3, #32] 8009ea4: f241 1211 movw r2, #4369 @ 0x1111 8009ea8: 4214 tst r4, r2 8009eaa: d108 bne.n 8009ebe 8009eac: 6a1c ldr r4, [r3, #32] 8009eae: f240 4244 movw r2, #1092 @ 0x444 8009eb2: 4214 tst r4, r2 8009eb4: d103 bne.n 8009ebe 8009eb6: 6c5a ldr r2, [r3, #68] @ 0x44 8009eb8: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8009ebc: 645a str r2, [r3, #68] @ 0x44 8009ebe: 6a1c ldr r4, [r3, #32] 8009ec0: f241 1211 movw r2, #4369 @ 0x1111 8009ec4: 4214 tst r4, r2 8009ec6: d104 bne.n 8009ed2 8009ec8: 6a1c ldr r4, [r3, #32] 8009eca: f240 4244 movw r2, #1092 @ 0x444 8009ece: 4214 tst r4, r2 8009ed0: d013 beq.n 8009efa 8009ed2: b931 cbnz r1, 8009ee2 8009ed4: 2301 movs r3, #1 8009ed6: f880 303e strb.w r3, [r0, #62] @ 0x3e 8009eda: 2000 movs r0, #0 8009edc: f85d 4b04 ldr.w r4, [sp], #4 8009ee0: 4770 bx lr 8009ee2: 3904 subs r1, #4 8009ee4: 290c cmp r1, #12 8009ee6: d80d bhi.n 8009f04 8009ee8: e8df f001 tbb [pc, r1] 8009eec: 0c0c0c13 .word 0x0c0c0c13 8009ef0: 0c0c0c1a .word 0x0c0c0c1a 8009ef4: 0c0c0c21 .word 0x0c0c0c21 8009ef8: 28 .byte 0x28 8009ef9: 00 .byte 0x00 8009efa: 681a ldr r2, [r3, #0] 8009efc: f022 0201 bic.w r2, r2, #1 8009f00: 601a str r2, [r3, #0] 8009f02: e7e6 b.n 8009ed2 8009f04: 2301 movs r3, #1 8009f06: f880 3043 strb.w r3, [r0, #67] @ 0x43 8009f0a: 2000 movs r0, #0 8009f0c: f85d 4b04 ldr.w r4, [sp], #4 8009f10: 4770 bx lr 8009f12: 2301 movs r3, #1 8009f14: f880 303f strb.w r3, [r0, #63] @ 0x3f 8009f18: 2000 movs r0, #0 8009f1a: f85d 4b04 ldr.w r4, [sp], #4 8009f1e: 4770 bx lr 8009f20: 2301 movs r3, #1 8009f22: f880 3040 strb.w r3, [r0, #64] @ 0x40 8009f26: 2000 movs r0, #0 8009f28: f85d 4b04 ldr.w r4, [sp], #4 8009f2c: 4770 bx lr 8009f2e: 2301 movs r3, #1 8009f30: f880 3041 strb.w r3, [r0, #65] @ 0x41 8009f34: 2000 movs r0, #0 8009f36: f85d 4b04 ldr.w r4, [sp], #4 8009f3a: 4770 bx lr 8009f3c: 2301 movs r3, #1 8009f3e: f880 3042 strb.w r3, [r0, #66] @ 0x42 8009f42: 2000 movs r0, #0 8009f44: f85d 4b04 ldr.w r4, [sp], #4 8009f48: 4770 bx lr 8009f4a: bf00 nop 8009f4c: 40010000 .word 0x40010000 8009f50: 40010400 .word 0x40010400 8009f54: 40014800 .word 0x40014800 08009f58 : __HAL_LOCK(htim); 8009f58: f890 303c ldrb.w r3, [r0, #60] @ 0x3c 8009f5c: 2b01 cmp r3, #1 8009f5e: d07e beq.n 800a05e 8009f60: 4602 mov r2, r0 htim->State = HAL_TIM_STATE_BUSY; 8009f62: 2302 movs r3, #2 { 8009f64: b430 push {r4, r5} tmpsmcr = htim->Instance->SMCR; 8009f66: 6804 ldr r4, [r0, #0] __HAL_LOCK(htim); 8009f68: 2001 movs r0, #1 htim->State = HAL_TIM_STATE_BUSY; 8009f6a: f882 303d strb.w r3, [r2, #61] @ 0x3d __HAL_LOCK(htim); 8009f6e: f882 003c strb.w r0, [r2, #60] @ 0x3c tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8009f72: 4b58 ldr r3, [pc, #352] @ (800a0d4 ) tmpsmcr = htim->Instance->SMCR; 8009f74: 68a5 ldr r5, [r4, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8009f76: 402b ands r3, r5 htim->Instance->SMCR = tmpsmcr; 8009f78: 60a3 str r3, [r4, #8] switch (sClockSourceConfig->ClockSource) 8009f7a: 680b ldr r3, [r1, #0] 8009f7c: 2b70 cmp r3, #112 @ 0x70 8009f7e: f000 8098 beq.w 800a0b2 8009f82: d825 bhi.n 8009fd0 8009f84: 2b50 cmp r3, #80 @ 0x50 8009f86: d06c beq.n 800a062 8009f88: d938 bls.n 8009ffc 8009f8a: 2b60 cmp r3, #96 @ 0x60 8009f8c: d118 bne.n 8009fc0 sClockSourceConfig->ClockPolarity, 8009f8e: 684b ldr r3, [r1, #4] sClockSourceConfig->ClockFilter); 8009f90: 68cd ldr r5, [r1, #12] { uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8009f92: 6a21 ldr r1, [r4, #32] TIMx->CCER &= ~TIM_CCER_CC2E; 8009f94: 6a20 ldr r0, [r4, #32] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8009f96: f021 01a0 bic.w r1, r1, #160 @ 0xa0 TIMx->CCER &= ~TIM_CCER_CC2E; 8009f9a: f020 0010 bic.w r0, r0, #16 tmpccer |= (TIM_ICPolarity << 4U); 8009f9e: ea41 1103 orr.w r1, r1, r3, lsl #4 uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8009fa2: 4b4d ldr r3, [pc, #308] @ (800a0d8 ) TIMx->CCER &= ~TIM_CCER_CC2E; 8009fa4: 6220 str r0, [r4, #32] tmpccmr1 = TIMx->CCMR1; 8009fa6: 69a0 ldr r0, [r4, #24] tmpccmr1 &= ~TIM_CCMR1_IC2F; 8009fa8: f420 4070 bic.w r0, r0, #61440 @ 0xf000 tmpccmr1 |= (TIM_ICFilter << 12U); 8009fac: ea40 3005 orr.w r0, r0, r5, lsl #12 TIMx->CCMR1 = tmpccmr1 ; 8009fb0: 61a0 str r0, [r4, #24] HAL_StatusTypeDef status = HAL_OK; 8009fb2: 2000 movs r0, #0 TIMx->CCER = tmpccer; 8009fb4: 6221 str r1, [r4, #32] tmpsmcr = TIMx->SMCR; 8009fb6: 68a1 ldr r1, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 8009fb8: 400b ands r3, r1 /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8009fba: f043 0367 orr.w r3, r3, #103 @ 0x67 /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8009fbe: 60a3 str r3, [r4, #8] htim->State = HAL_TIM_STATE_READY; 8009fc0: 2101 movs r1, #1 __HAL_UNLOCK(htim); 8009fc2: 2300 movs r3, #0 htim->State = HAL_TIM_STATE_READY; 8009fc4: f882 103d strb.w r1, [r2, #61] @ 0x3d __HAL_UNLOCK(htim); 8009fc8: f882 303c strb.w r3, [r2, #60] @ 0x3c } 8009fcc: bc30 pop {r4, r5} 8009fce: 4770 bx lr switch (sClockSourceConfig->ClockSource) 8009fd0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8009fd4: d05d beq.n 800a092 8009fd6: d931 bls.n 800a03c 8009fd8: 4940 ldr r1, [pc, #256] @ (800a0dc ) 8009fda: 428b cmp r3, r1 8009fdc: d006 beq.n 8009fec 8009fde: d927 bls.n 800a030 8009fe0: 493f ldr r1, [pc, #252] @ (800a0e0 ) 8009fe2: 428b cmp r3, r1 8009fe4: d002 beq.n 8009fec 8009fe6: 3110 adds r1, #16 8009fe8: 428b cmp r3, r1 8009fea: d1e9 bne.n 8009fc0 tmpsmcr = TIMx->SMCR; 8009fec: 68a0 ldr r0, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 8009fee: 493a ldr r1, [pc, #232] @ (800a0d8 ) 8009ff0: 4001 ands r1, r0 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8009ff2: 4319 orrs r1, r3 8009ff4: f041 0107 orr.w r1, r1, #7 TIMx->SMCR = tmpsmcr; 8009ff8: 60a1 str r1, [r4, #8] } 8009ffa: e022 b.n 800a042 switch (sClockSourceConfig->ClockSource) 8009ffc: 2b40 cmp r3, #64 @ 0x40 8009ffe: d122 bne.n 800a046 tmpccer = TIMx->CCER; 800a000: 6a23 ldr r3, [r4, #32] sClockSourceConfig->ClockPolarity, 800a002: 6848 ldr r0, [r1, #4] sClockSourceConfig->ClockFilter); 800a004: 68cd ldr r5, [r1, #12] tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 800a006: f023 030a bic.w r3, r3, #10 TIMx->CCER &= ~TIM_CCER_CC1E; 800a00a: 6a21 ldr r1, [r4, #32] tmpccer |= TIM_ICPolarity; 800a00c: 4318 orrs r0, r3 tmpsmcr &= ~TIM_SMCR_TS; 800a00e: 4b32 ldr r3, [pc, #200] @ (800a0d8 ) TIMx->CCER &= ~TIM_CCER_CC1E; 800a010: f021 0101 bic.w r1, r1, #1 800a014: 6221 str r1, [r4, #32] tmpccmr1 = TIMx->CCMR1; 800a016: 69a1 ldr r1, [r4, #24] tmpccmr1 &= ~TIM_CCMR1_IC1F; 800a018: f021 01f0 bic.w r1, r1, #240 @ 0xf0 tmpccmr1 |= (TIM_ICFilter << 4U); 800a01c: ea41 1105 orr.w r1, r1, r5, lsl #4 TIMx->CCMR1 = tmpccmr1; 800a020: 61a1 str r1, [r4, #24] TIMx->CCER = tmpccer; 800a022: 6220 str r0, [r4, #32] tmpsmcr = TIMx->SMCR; 800a024: 68a1 ldr r1, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 800a026: 400b ands r3, r1 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 800a028: f043 0347 orr.w r3, r3, #71 @ 0x47 TIMx->SMCR = tmpsmcr; 800a02c: 60a3 str r3, [r4, #8] } 800a02e: e008 b.n 800a042 switch (sClockSourceConfig->ClockSource) 800a030: f023 0110 bic.w r1, r3, #16 800a034: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000 800a038: d1c2 bne.n 8009fc0 800a03a: e7d7 b.n 8009fec 800a03c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800a040: d1be bne.n 8009fc0 HAL_StatusTypeDef status = HAL_OK; 800a042: 2000 movs r0, #0 800a044: e7bc b.n 8009fc0 switch (sClockSourceConfig->ClockSource) 800a046: d8bb bhi.n 8009fc0 800a048: 2b20 cmp r3, #32 800a04a: d0cf beq.n 8009fec 800a04c: d903 bls.n 800a056 800a04e: 2b30 cmp r3, #48 @ 0x30 800a050: d0cc beq.n 8009fec status = HAL_ERROR; 800a052: 2001 movs r0, #1 800a054: e7b4 b.n 8009fc0 switch (sClockSourceConfig->ClockSource) 800a056: f033 0110 bics.w r1, r3, #16 800a05a: d1b1 bne.n 8009fc0 800a05c: e7c6 b.n 8009fec __HAL_LOCK(htim); 800a05e: 2002 movs r0, #2 } 800a060: 4770 bx lr tmpccer = TIMx->CCER; 800a062: 6a23 ldr r3, [r4, #32] sClockSourceConfig->ClockPolarity, 800a064: 6848 ldr r0, [r1, #4] sClockSourceConfig->ClockFilter); 800a066: 68cd ldr r5, [r1, #12] tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 800a068: f023 030a bic.w r3, r3, #10 TIMx->CCER &= ~TIM_CCER_CC1E; 800a06c: 6a21 ldr r1, [r4, #32] tmpccer |= TIM_ICPolarity; 800a06e: 4318 orrs r0, r3 tmpsmcr &= ~TIM_SMCR_TS; 800a070: 4b19 ldr r3, [pc, #100] @ (800a0d8 ) TIMx->CCER &= ~TIM_CCER_CC1E; 800a072: f021 0101 bic.w r1, r1, #1 800a076: 6221 str r1, [r4, #32] tmpccmr1 = TIMx->CCMR1; 800a078: 69a1 ldr r1, [r4, #24] tmpccmr1 &= ~TIM_CCMR1_IC1F; 800a07a: f021 01f0 bic.w r1, r1, #240 @ 0xf0 tmpccmr1 |= (TIM_ICFilter << 4U); 800a07e: ea41 1105 orr.w r1, r1, r5, lsl #4 TIMx->CCMR1 = tmpccmr1; 800a082: 61a1 str r1, [r4, #24] TIMx->CCER = tmpccer; 800a084: 6220 str r0, [r4, #32] tmpsmcr = TIMx->SMCR; 800a086: 68a1 ldr r1, [r4, #8] tmpsmcr &= ~TIM_SMCR_TS; 800a088: 400b ands r3, r1 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 800a08a: f043 0357 orr.w r3, r3, #87 @ 0x57 TIMx->SMCR = tmpsmcr; 800a08e: 60a3 str r3, [r4, #8] } 800a090: e7d7 b.n 800a042 /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800a092: e9d1 5301 ldrd r5, r3, [r1, #4] tmpsmcr = TIMx->SMCR; 800a096: 68a0 ldr r0, [r4, #8] tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800a098: 432b orrs r3, r5 800a09a: 68cd ldr r5, [r1, #12] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800a09c: f420 417f bic.w r1, r0, #65280 @ 0xff00 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800a0a0: ea43 2305 orr.w r3, r3, r5, lsl #8 800a0a4: 430b orrs r3, r1 /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800a0a6: 60a3 str r3, [r4, #8] htim->Instance->SMCR |= TIM_SMCR_ECE; 800a0a8: 68a3 ldr r3, [r4, #8] 800a0aa: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800a0ae: 60a3 str r3, [r4, #8] break; 800a0b0: e7c7 b.n 800a042 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800a0b2: e9d1 5301 ldrd r5, r3, [r1, #4] tmpsmcr = TIMx->SMCR; 800a0b6: 68a0 ldr r0, [r4, #8] tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800a0b8: 432b orrs r3, r5 800a0ba: 68cd ldr r5, [r1, #12] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800a0bc: f420 417f bic.w r1, r0, #65280 @ 0xff00 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800a0c0: ea43 2305 orr.w r3, r3, r5, lsl #8 800a0c4: 430b orrs r3, r1 TIMx->SMCR = tmpsmcr; 800a0c6: 60a3 str r3, [r4, #8] tmpsmcr = htim->Instance->SMCR; 800a0c8: 68a3 ldr r3, [r4, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 800a0ca: f043 0377 orr.w r3, r3, #119 @ 0x77 htim->Instance->SMCR = tmpsmcr; 800a0ce: 60a3 str r3, [r4, #8] break; 800a0d0: e7b7 b.n 800a042 800a0d2: bf00 nop 800a0d4: ffce0088 .word 0xffce0088 800a0d8: ffcfff8f .word 0xffcfff8f 800a0dc: 00100020 .word 0x00100020 800a0e0: 00100030 .word 0x00100030 0800a0e4 : __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) 800a0e4: 4770 bx lr 800a0e6: bf00 nop 0800a0e8 : __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) 800a0e8: 4770 bx lr 800a0ea: bf00 nop 0800a0ec : __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) 800a0ec: 4770 bx lr 800a0ee: bf00 nop 0800a0f0 : __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) 800a0f0: 4770 bx lr 800a0f2: bf00 nop 0800a0f4 : { 800a0f4: b5f8 push {r3, r4, r5, r6, r7, lr} uint32_t itsource = htim->Instance->DIER; 800a0f6: 6803 ldr r3, [r0, #0] { 800a0f8: 4605 mov r5, r0 uint32_t itsource = htim->Instance->DIER; 800a0fa: 68de ldr r6, [r3, #12] uint32_t itflag = htim->Instance->SR; 800a0fc: 691c ldr r4, [r3, #16] if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800a0fe: 07a1 lsls r1, r4, #30 800a100: d501 bpl.n 800a106 if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800a102: 07b2 lsls r2, r6, #30 800a104: d457 bmi.n 800a1b6 if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800a106: 0767 lsls r7, r4, #29 800a108: d501 bpl.n 800a10e if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800a10a: 0770 lsls r0, r6, #29 800a10c: d440 bmi.n 800a190 if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800a10e: 0721 lsls r1, r4, #28 800a110: d501 bpl.n 800a116 if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800a112: 0732 lsls r2, r6, #28 800a114: d42a bmi.n 800a16c if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800a116: 06e7 lsls r7, r4, #27 800a118: d501 bpl.n 800a11e if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800a11a: 06f0 lsls r0, r6, #27 800a11c: d413 bmi.n 800a146 if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800a11e: 07e1 lsls r1, r4, #31 800a120: d501 bpl.n 800a126 if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800a122: 07f2 lsls r2, r6, #31 800a124: d465 bmi.n 800a1f2 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800a126: f414 5f02 tst.w r4, #8320 @ 0x2080 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800a12a: f404 7780 and.w r7, r4, #256 @ 0x100 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800a12e: d052 beq.n 800a1d6 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800a130: 0633 lsls r3, r6, #24 800a132: d466 bmi.n 800a202 if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800a134: 0660 lsls r0, r4, #25 800a136: d501 bpl.n 800a13c if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800a138: 0671 lsls r1, r6, #25 800a13a: d473 bmi.n 800a224 if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800a13c: 06a2 lsls r2, r4, #26 800a13e: d501 bpl.n 800a144 if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800a140: 06b3 lsls r3, r6, #26 800a142: d44d bmi.n 800a1e0 } 800a144: bdf8 pop {r3, r4, r5, r6, r7, pc} __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800a146: 682b ldr r3, [r5, #0] 800a148: f06f 0210 mvn.w r2, #16 HAL_TIM_IC_CaptureCallback(htim); 800a14c: 4628 mov r0, r5 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800a14e: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800a150: 2208 movs r2, #8 800a152: 772a strb r2, [r5, #28] if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800a154: 69db ldr r3, [r3, #28] 800a156: f413 7f40 tst.w r3, #768 @ 0x300 800a15a: d174 bne.n 800a246 HAL_TIM_OC_DelayElapsedCallback(htim); 800a15c: f7ff ffc2 bl 800a0e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800a160: 4628 mov r0, r5 800a162: f7ff ffc3 bl 800a0ec htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800a166: 2300 movs r3, #0 800a168: 772b strb r3, [r5, #28] 800a16a: e7d8 b.n 800a11e __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800a16c: 682b ldr r3, [r5, #0] 800a16e: f06f 0208 mvn.w r2, #8 HAL_TIM_IC_CaptureCallback(htim); 800a172: 4628 mov r0, r5 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800a174: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800a176: 2204 movs r2, #4 800a178: 772a strb r2, [r5, #28] if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800a17a: 69db ldr r3, [r3, #28] 800a17c: 079b lsls r3, r3, #30 800a17e: d15f bne.n 800a240 HAL_TIM_OC_DelayElapsedCallback(htim); 800a180: f7ff ffb0 bl 800a0e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800a184: 4628 mov r0, r5 800a186: f7ff ffb1 bl 800a0ec htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800a18a: 2300 movs r3, #0 800a18c: 772b strb r3, [r5, #28] 800a18e: e7c2 b.n 800a116 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800a190: 682b ldr r3, [r5, #0] 800a192: f06f 0204 mvn.w r2, #4 HAL_TIM_IC_CaptureCallback(htim); 800a196: 4628 mov r0, r5 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800a198: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800a19a: 2202 movs r2, #2 800a19c: 772a strb r2, [r5, #28] if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800a19e: 699b ldr r3, [r3, #24] 800a1a0: f413 7f40 tst.w r3, #768 @ 0x300 800a1a4: d149 bne.n 800a23a HAL_TIM_OC_DelayElapsedCallback(htim); 800a1a6: f7ff ff9d bl 800a0e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800a1aa: 4628 mov r0, r5 800a1ac: f7ff ff9e bl 800a0ec htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800a1b0: 2300 movs r3, #0 800a1b2: 772b strb r3, [r5, #28] 800a1b4: e7ab b.n 800a10e __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800a1b6: f06f 0202 mvn.w r2, #2 800a1ba: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800a1bc: 2201 movs r2, #1 800a1be: 7702 strb r2, [r0, #28] if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800a1c0: 699b ldr r3, [r3, #24] 800a1c2: 079b lsls r3, r3, #30 800a1c4: d136 bne.n 800a234 HAL_TIM_OC_DelayElapsedCallback(htim); 800a1c6: f7ff ff8d bl 800a0e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800a1ca: 4628 mov r0, r5 800a1cc: f7ff ff8e bl 800a0ec htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800a1d0: 2300 movs r3, #0 800a1d2: 772b strb r3, [r5, #28] 800a1d4: e797 b.n 800a106 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800a1d6: 2f00 cmp r7, #0 800a1d8: d0ac beq.n 800a134 if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800a1da: 0637 lsls r7, r6, #24 800a1dc: d41a bmi.n 800a214 800a1de: e7a9 b.n 800a134 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800a1e0: 682b ldr r3, [r5, #0] 800a1e2: f06f 0220 mvn.w r2, #32 HAL_TIMEx_CommutCallback(htim); 800a1e6: 4628 mov r0, r5 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800a1e8: 611a str r2, [r3, #16] } 800a1ea: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr} HAL_TIMEx_CommutCallback(htim); 800a1ee: f000 ba4f b.w 800a690 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800a1f2: 682b ldr r3, [r5, #0] 800a1f4: f06f 0201 mvn.w r2, #1 HAL_TIM_PeriodElapsedCallback(htim); 800a1f8: 4628 mov r0, r5 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800a1fa: 611a str r2, [r3, #16] HAL_TIM_PeriodElapsedCallback(htim); 800a1fc: f7f6 fad6 bl 80007ac 800a200: e791 b.n 800a126 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800a202: 682b ldr r3, [r5, #0] 800a204: f46f 5202 mvn.w r2, #8320 @ 0x2080 HAL_TIMEx_BreakCallback(htim); 800a208: 4628 mov r0, r5 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800a20a: 611a str r2, [r3, #16] HAL_TIMEx_BreakCallback(htim); 800a20c: f000 fa42 bl 800a694 if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800a210: 2f00 cmp r7, #0 800a212: d08f beq.n 800a134 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800a214: 682b ldr r3, [r5, #0] 800a216: f46f 7280 mvn.w r2, #256 @ 0x100 HAL_TIMEx_Break2Callback(htim); 800a21a: 4628 mov r0, r5 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800a21c: 611a str r2, [r3, #16] HAL_TIMEx_Break2Callback(htim); 800a21e: f000 fa3b bl 800a698 800a222: e787 b.n 800a134 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800a224: 682b ldr r3, [r5, #0] 800a226: f06f 0240 mvn.w r2, #64 @ 0x40 HAL_TIM_TriggerCallback(htim); 800a22a: 4628 mov r0, r5 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800a22c: 611a str r2, [r3, #16] HAL_TIM_TriggerCallback(htim); 800a22e: f7ff ff5f bl 800a0f0 800a232: e783 b.n 800a13c HAL_TIM_IC_CaptureCallback(htim); 800a234: f7ff ff58 bl 800a0e8 800a238: e7ca b.n 800a1d0 HAL_TIM_IC_CaptureCallback(htim); 800a23a: f7ff ff55 bl 800a0e8 800a23e: e7b7 b.n 800a1b0 HAL_TIM_IC_CaptureCallback(htim); 800a240: f7ff ff52 bl 800a0e8 800a244: e7a1 b.n 800a18a HAL_TIM_IC_CaptureCallback(htim); 800a246: f7ff ff4f bl 800a0e8 800a24a: e78c b.n 800a166 0800a24c : channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800a24c: 2910 cmp r1, #16 800a24e: d80a bhi.n 800a266 800a250: e8df f001 tbb [pc, r1] 800a254: 0909090d .word 0x0909090d 800a258: 09090911 .word 0x09090911 800a25c: 09090915 .word 0x09090915 800a260: 09090919 .word 0x09090919 800a264: 1d .byte 0x1d 800a265: 00 .byte 0x00 800a266: f890 0043 ldrb.w r0, [r0, #67] @ 0x43 800a26a: b2c0 uxtb r0, r0 } 800a26c: 4770 bx lr channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800a26e: f890 003e ldrb.w r0, [r0, #62] @ 0x3e 800a272: b2c0 uxtb r0, r0 800a274: 4770 bx lr 800a276: f890 003f ldrb.w r0, [r0, #63] @ 0x3f 800a27a: b2c0 uxtb r0, r0 800a27c: 4770 bx lr 800a27e: f890 0040 ldrb.w r0, [r0, #64] @ 0x40 800a282: b2c0 uxtb r0, r0 800a284: 4770 bx lr 800a286: f890 0041 ldrb.w r0, [r0, #65] @ 0x41 800a28a: b2c0 uxtb r0, r0 800a28c: 4770 bx lr 800a28e: f890 0042 ldrb.w r0, [r0, #66] @ 0x42 800a292: b2c0 uxtb r0, r0 800a294: 4770 bx lr 800a296: bf00 nop 0800a298 : tmpccer = TIMx->CCER; 800a298: 6a03 ldr r3, [r0, #32] TIMx->CCER &= ~TIM_CCER_CC2E; 800a29a: 6a02 ldr r2, [r0, #32] tmpccer &= ~TIM_CCER_CC2P; 800a29c: f023 0320 bic.w r3, r3, #32 TIMx->CCER &= ~TIM_CCER_CC2E; 800a2a0: f022 0210 bic.w r2, r2, #16 { 800a2a4: b470 push {r4, r5, r6} TIMx->CCER &= ~TIM_CCER_CC2E; 800a2a6: 6202 str r2, [r0, #32] tmpccmrx &= ~TIM_CCMR1_CC2S; 800a2a8: 4a19 ldr r2, [pc, #100] @ (800a310 ) tmpcr2 = TIMx->CR2; 800a2aa: 6844 ldr r4, [r0, #4] tmpccmrx = TIMx->CCMR1; 800a2ac: 6985 ldr r5, [r0, #24] tmpccmrx &= ~TIM_CCMR1_CC2S; 800a2ae: 402a ands r2, r5 tmpccmrx |= (OC_Config->OCMode << 8U); 800a2b0: 680d ldr r5, [r1, #0] 800a2b2: ea42 2205 orr.w r2, r2, r5, lsl #8 tmpccer |= (OC_Config->OCPolarity << 4U); 800a2b6: 688d ldr r5, [r1, #8] 800a2b8: ea43 1305 orr.w r3, r3, r5, lsl #4 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800a2bc: 4d15 ldr r5, [pc, #84] @ (800a314 ) 800a2be: 42a8 cmp r0, r5 800a2c0: d00f beq.n 800a2e2 800a2c2: f505 6580 add.w r5, r5, #1024 @ 0x400 800a2c6: 42a8 cmp r0, r5 800a2c8: d00b beq.n 800a2e2 if (IS_TIM_BREAK_INSTANCE(TIMx)) 800a2ca: 4e13 ldr r6, [pc, #76] @ (800a318 ) 800a2cc: f505 4580 add.w r5, r5, #16384 @ 0x4000 800a2d0: 42a8 cmp r0, r5 800a2d2: bf18 it ne 800a2d4: 42b0 cmpne r0, r6 800a2d6: d00b beq.n 800a2f0 800a2d8: f505 6580 add.w r5, r5, #1024 @ 0x400 800a2dc: 42a8 cmp r0, r5 800a2de: d10f bne.n 800a300 800a2e0: e006 b.n 800a2f0 tmpccer &= ~TIM_CCER_CC2NP; 800a2e2: f023 0380 bic.w r3, r3, #128 @ 0x80 tmpccer |= (OC_Config->OCNPolarity << 4U); 800a2e6: 68cd ldr r5, [r1, #12] 800a2e8: ea43 1305 orr.w r3, r3, r5, lsl #4 tmpccer &= ~TIM_CCER_CC2NE; 800a2ec: f023 0340 bic.w r3, r3, #64 @ 0x40 tmpcr2 &= ~TIM_CR2_OIS2N; 800a2f0: f424 6440 bic.w r4, r4, #3072 @ 0xc00 tmpcr2 |= (OC_Config->OCNIdleState << 2U); 800a2f4: e9d1 6505 ldrd r6, r5, [r1, #20] 800a2f8: ea46 0c05 orr.w ip, r6, r5 800a2fc: ea44 048c orr.w r4, r4, ip, lsl #2 TIMx->CCR2 = OC_Config->Pulse; 800a300: 6849 ldr r1, [r1, #4] TIMx->CR2 = tmpcr2; 800a302: 6044 str r4, [r0, #4] TIMx->CCMR1 = tmpccmrx; 800a304: 6182 str r2, [r0, #24] TIMx->CCR2 = OC_Config->Pulse; 800a306: 6381 str r1, [r0, #56] @ 0x38 TIMx->CCER = tmpccer; 800a308: 6203 str r3, [r0, #32] } 800a30a: bc70 pop {r4, r5, r6} 800a30c: 4770 bx lr 800a30e: bf00 nop 800a310: feff8cff .word 0xfeff8cff 800a314: 40010000 .word 0x40010000 800a318: 40014000 .word 0x40014000 0800a31c : { 800a31c: b5f8 push {r3, r4, r5, r6, r7, lr} __HAL_LOCK(htim); 800a31e: f890 303c ldrb.w r3, [r0, #60] @ 0x3c 800a322: 2b01 cmp r3, #1 800a324: f000 8107 beq.w 800a536 800a328: 2301 movs r3, #1 800a32a: 4604 mov r4, r0 800a32c: 460d mov r5, r1 800a32e: f880 303c strb.w r3, [r0, #60] @ 0x3c switch (Channel) 800a332: 2a14 cmp r2, #20 800a334: d816 bhi.n 800a364 800a336: e8df f012 tbh [pc, r2, lsl #1] 800a33a: 0056 .short 0x0056 800a33c: 00150015 .word 0x00150015 800a340: 00670015 .word 0x00670015 800a344: 00150015 .word 0x00150015 800a348: 00780015 .word 0x00780015 800a34c: 00150015 .word 0x00150015 800a350: 00880015 .word 0x00880015 800a354: 00150015 .word 0x00150015 800a358: 00c40015 .word 0x00c40015 800a35c: 00150015 .word 0x00150015 800a360: 001a0015 .word 0x001a0015 800a364: 2001 movs r0, #1 __HAL_UNLOCK(htim); 800a366: 2300 movs r3, #0 800a368: f884 303c strb.w r3, [r4, #60] @ 0x3c } 800a36c: bdf8 pop {r3, r4, r5, r6, r7, pc} TIM_OC6_SetConfig(htim->Instance, sConfig); 800a36e: 6803 ldr r3, [r0, #0] tmpccer = TIMx->CCER; 800a370: 6a1a ldr r2, [r3, #32] TIMx->CCER &= ~TIM_CCER_CC6E; 800a372: 6a19 ldr r1, [r3, #32] tmpccer &= (uint32_t)~TIM_CCER_CC6P; 800a374: f422 1200 bic.w r2, r2, #2097152 @ 0x200000 TIMx->CCER &= ~TIM_CCER_CC6E; 800a378: f421 1180 bic.w r1, r1, #1048576 @ 0x100000 800a37c: 6219 str r1, [r3, #32] tmpccmrx &= ~(TIM_CCMR3_OC6M); 800a37e: 496f ldr r1, [pc, #444] @ (800a53c ) tmpcr2 = TIMx->CR2; 800a380: 6858 ldr r0, [r3, #4] tmpccmrx = TIMx->CCMR3; 800a382: 6d5e ldr r6, [r3, #84] @ 0x54 tmpccmrx &= ~(TIM_CCMR3_OC6M); 800a384: 4031 ands r1, r6 tmpccmrx |= (OC_Config->OCMode << 8U); 800a386: 682e ldr r6, [r5, #0] 800a388: ea41 2106 orr.w r1, r1, r6, lsl #8 tmpccer |= (OC_Config->OCPolarity << 20U); 800a38c: 68ae ldr r6, [r5, #8] 800a38e: ea42 5206 orr.w r2, r2, r6, lsl #20 if (IS_TIM_BREAK_INSTANCE(TIMx)) 800a392: 4e6b ldr r6, [pc, #428] @ (800a540 ) 800a394: 42b3 cmp r3, r6 800a396: d00e beq.n 800a3b6 800a398: f506 6680 add.w r6, r6, #1024 @ 0x400 800a39c: 42b3 cmp r3, r6 800a39e: d00a beq.n 800a3b6 800a3a0: 4f68 ldr r7, [pc, #416] @ (800a544 ) 800a3a2: f506 4680 add.w r6, r6, #16384 @ 0x4000 800a3a6: 42b3 cmp r3, r6 800a3a8: bf18 it ne 800a3aa: 42bb cmpne r3, r7 800a3ac: d003 beq.n 800a3b6 800a3ae: f506 6680 add.w r6, r6, #1024 @ 0x400 800a3b2: 42b3 cmp r3, r6 800a3b4: d104 bne.n 800a3c0 tmpcr2 &= ~TIM_CR2_OIS6; 800a3b6: f420 2080 bic.w r0, r0, #262144 @ 0x40000 tmpcr2 |= (OC_Config->OCIdleState << 10U); 800a3ba: 696e ldr r6, [r5, #20] 800a3bc: ea40 2086 orr.w r0, r0, r6, lsl #10 TIMx->CR2 = tmpcr2; 800a3c0: 6058 str r0, [r3, #4] TIMx->CCR6 = OC_Config->Pulse; 800a3c2: 6868 ldr r0, [r5, #4] TIMx->CCMR3 = tmpccmrx; 800a3c4: 6559 str r1, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800a3c6: 6929 ldr r1, [r5, #16] TIMx->CCR6 = OC_Config->Pulse; 800a3c8: 65d8 str r0, [r3, #92] @ 0x5c TIMx->CCER = tmpccer; 800a3ca: 621a str r2, [r3, #32] htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800a3cc: 6d5a ldr r2, [r3, #84] @ 0x54 800a3ce: f442 6200 orr.w r2, r2, #2048 @ 0x800 800a3d2: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 800a3d4: 6d5a ldr r2, [r3, #84] @ 0x54 800a3d6: f422 6280 bic.w r2, r2, #1024 @ 0x400 800a3da: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800a3dc: 6d5a ldr r2, [r3, #84] @ 0x54 800a3de: ea42 2201 orr.w r2, r2, r1, lsl #8 800a3e2: 655a str r2, [r3, #84] @ 0x54 break; 800a3e4: e00e b.n 800a404 TIM_OC1_SetConfig(htim->Instance, sConfig); 800a3e6: 6800 ldr r0, [r0, #0] 800a3e8: f7ff fa2e bl 8009848 htim->Instance->CCMR1 |= sConfig->OCFastMode; 800a3ec: 692a ldr r2, [r5, #16] htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800a3ee: 6983 ldr r3, [r0, #24] 800a3f0: f043 0308 orr.w r3, r3, #8 800a3f4: 6183 str r3, [r0, #24] htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800a3f6: 6983 ldr r3, [r0, #24] 800a3f8: f023 0304 bic.w r3, r3, #4 800a3fc: 6183 str r3, [r0, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800a3fe: 6983 ldr r3, [r0, #24] 800a400: 4313 orrs r3, r2 800a402: 6183 str r3, [r0, #24] HAL_StatusTypeDef status = HAL_OK; 800a404: 2000 movs r0, #0 800a406: e7ae b.n 800a366 TIM_OC2_SetConfig(htim->Instance, sConfig); 800a408: 6800 ldr r0, [r0, #0] 800a40a: f7ff ff45 bl 800a298 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800a40e: 692a ldr r2, [r5, #16] htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800a410: 6983 ldr r3, [r0, #24] 800a412: f443 6300 orr.w r3, r3, #2048 @ 0x800 800a416: 6183 str r3, [r0, #24] htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800a418: 6983 ldr r3, [r0, #24] 800a41a: f423 6380 bic.w r3, r3, #1024 @ 0x400 800a41e: 6183 str r3, [r0, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800a420: 6983 ldr r3, [r0, #24] 800a422: ea43 2302 orr.w r3, r3, r2, lsl #8 800a426: 6183 str r3, [r0, #24] break; 800a428: e7ec b.n 800a404 TIM_OC3_SetConfig(htim->Instance, sConfig); 800a42a: 6800 ldr r0, [r0, #0] 800a42c: f7ff fa48 bl 80098c0 htim->Instance->CCMR2 |= sConfig->OCFastMode; 800a430: 692a ldr r2, [r5, #16] htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800a432: 69c3 ldr r3, [r0, #28] 800a434: f043 0308 orr.w r3, r3, #8 800a438: 61c3 str r3, [r0, #28] htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800a43a: 69c3 ldr r3, [r0, #28] 800a43c: f023 0304 bic.w r3, r3, #4 800a440: 61c3 str r3, [r0, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 800a442: 69c3 ldr r3, [r0, #28] 800a444: 4313 orrs r3, r2 800a446: 61c3 str r3, [r0, #28] break; 800a448: e7dc b.n 800a404 TIM_OC4_SetConfig(htim->Instance, sConfig); 800a44a: 6803 ldr r3, [r0, #0] tmpccer = TIMx->CCER; 800a44c: 6a1a ldr r2, [r3, #32] TIMx->CCER &= ~TIM_CCER_CC4E; 800a44e: 6a19 ldr r1, [r3, #32] tmpccer &= ~TIM_CCER_CC4P; 800a450: f422 5200 bic.w r2, r2, #8192 @ 0x2000 TIMx->CCER &= ~TIM_CCER_CC4E; 800a454: f421 5180 bic.w r1, r1, #4096 @ 0x1000 800a458: 6219 str r1, [r3, #32] tmpccmrx &= ~TIM_CCMR2_CC4S; 800a45a: 493b ldr r1, [pc, #236] @ (800a548 ) tmpcr2 = TIMx->CR2; 800a45c: 6858 ldr r0, [r3, #4] tmpccmrx = TIMx->CCMR2; 800a45e: 69de ldr r6, [r3, #28] tmpccmrx &= ~TIM_CCMR2_CC4S; 800a460: 4031 ands r1, r6 tmpccmrx |= (OC_Config->OCMode << 8U); 800a462: 682e ldr r6, [r5, #0] 800a464: ea41 2106 orr.w r1, r1, r6, lsl #8 tmpccer |= (OC_Config->OCPolarity << 12U); 800a468: 68ae ldr r6, [r5, #8] 800a46a: ea42 3206 orr.w r2, r2, r6, lsl #12 if (IS_TIM_BREAK_INSTANCE(TIMx)) 800a46e: 4e34 ldr r6, [pc, #208] @ (800a540 ) 800a470: 42b3 cmp r3, r6 800a472: d00e beq.n 800a492 800a474: f506 6680 add.w r6, r6, #1024 @ 0x400 800a478: 42b3 cmp r3, r6 800a47a: d00a beq.n 800a492 800a47c: 4f31 ldr r7, [pc, #196] @ (800a544 ) 800a47e: f506 4680 add.w r6, r6, #16384 @ 0x4000 800a482: 42b3 cmp r3, r6 800a484: bf18 it ne 800a486: 42bb cmpne r3, r7 800a488: d003 beq.n 800a492 800a48a: f506 6680 add.w r6, r6, #1024 @ 0x400 800a48e: 42b3 cmp r3, r6 800a490: d104 bne.n 800a49c tmpcr2 &= ~TIM_CR2_OIS4; 800a492: f420 4080 bic.w r0, r0, #16384 @ 0x4000 tmpcr2 |= (OC_Config->OCIdleState << 6U); 800a496: 696e ldr r6, [r5, #20] 800a498: ea40 1086 orr.w r0, r0, r6, lsl #6 TIMx->CR2 = tmpcr2; 800a49c: 6058 str r0, [r3, #4] TIMx->CCR4 = OC_Config->Pulse; 800a49e: 6868 ldr r0, [r5, #4] TIMx->CCMR2 = tmpccmrx; 800a4a0: 61d9 str r1, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800a4a2: 6929 ldr r1, [r5, #16] TIMx->CCR4 = OC_Config->Pulse; 800a4a4: 6418 str r0, [r3, #64] @ 0x40 TIMx->CCER = tmpccer; 800a4a6: 621a str r2, [r3, #32] htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800a4a8: 69da ldr r2, [r3, #28] 800a4aa: f442 6200 orr.w r2, r2, #2048 @ 0x800 800a4ae: 61da str r2, [r3, #28] htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800a4b0: 69da ldr r2, [r3, #28] 800a4b2: f422 6280 bic.w r2, r2, #1024 @ 0x400 800a4b6: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800a4b8: 69da ldr r2, [r3, #28] 800a4ba: ea42 2201 orr.w r2, r2, r1, lsl #8 800a4be: 61da str r2, [r3, #28] break; 800a4c0: e7a0 b.n 800a404 TIM_OC5_SetConfig(htim->Instance, sConfig); 800a4c2: 6803 ldr r3, [r0, #0] tmpccer = TIMx->CCER; 800a4c4: 6a1a ldr r2, [r3, #32] TIMx->CCER &= ~TIM_CCER_CC5E; 800a4c6: 6a19 ldr r1, [r3, #32] tmpccer &= ~TIM_CCER_CC5P; 800a4c8: f422 3200 bic.w r2, r2, #131072 @ 0x20000 TIMx->CCER &= ~TIM_CCER_CC5E; 800a4cc: f421 3180 bic.w r1, r1, #65536 @ 0x10000 800a4d0: 6219 str r1, [r3, #32] tmpccmrx &= ~(TIM_CCMR3_OC5M); 800a4d2: 491e ldr r1, [pc, #120] @ (800a54c ) tmpcr2 = TIMx->CR2; 800a4d4: 6858 ldr r0, [r3, #4] tmpccmrx = TIMx->CCMR3; 800a4d6: 6d5e ldr r6, [r3, #84] @ 0x54 tmpccmrx &= ~(TIM_CCMR3_OC5M); 800a4d8: 4031 ands r1, r6 tmpccmrx |= OC_Config->OCMode; 800a4da: 682e ldr r6, [r5, #0] 800a4dc: 4331 orrs r1, r6 tmpccer |= (OC_Config->OCPolarity << 16U); 800a4de: 68ae ldr r6, [r5, #8] 800a4e0: ea42 4206 orr.w r2, r2, r6, lsl #16 if (IS_TIM_BREAK_INSTANCE(TIMx)) 800a4e4: 4e16 ldr r6, [pc, #88] @ (800a540 ) 800a4e6: 42b3 cmp r3, r6 800a4e8: d00e beq.n 800a508 800a4ea: f506 6680 add.w r6, r6, #1024 @ 0x400 800a4ee: 42b3 cmp r3, r6 800a4f0: d00a beq.n 800a508 800a4f2: 4f14 ldr r7, [pc, #80] @ (800a544 ) 800a4f4: f506 4680 add.w r6, r6, #16384 @ 0x4000 800a4f8: 42b3 cmp r3, r6 800a4fa: bf18 it ne 800a4fc: 42bb cmpne r3, r7 800a4fe: d003 beq.n 800a508 800a500: f506 6680 add.w r6, r6, #1024 @ 0x400 800a504: 42b3 cmp r3, r6 800a506: d104 bne.n 800a512 tmpcr2 &= ~TIM_CR2_OIS5; 800a508: f420 3080 bic.w r0, r0, #65536 @ 0x10000 tmpcr2 |= (OC_Config->OCIdleState << 8U); 800a50c: 696e ldr r6, [r5, #20] 800a50e: ea40 2006 orr.w r0, r0, r6, lsl #8 TIMx->CR2 = tmpcr2; 800a512: 6058 str r0, [r3, #4] TIMx->CCR5 = OC_Config->Pulse; 800a514: 6868 ldr r0, [r5, #4] TIMx->CCMR3 = tmpccmrx; 800a516: 6559 str r1, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800a518: 6929 ldr r1, [r5, #16] TIMx->CCR5 = OC_Config->Pulse; 800a51a: 6598 str r0, [r3, #88] @ 0x58 TIMx->CCER = tmpccer; 800a51c: 621a str r2, [r3, #32] htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 800a51e: 6d5a ldr r2, [r3, #84] @ 0x54 800a520: f042 0208 orr.w r2, r2, #8 800a524: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 800a526: 6d5a ldr r2, [r3, #84] @ 0x54 800a528: f022 0204 bic.w r2, r2, #4 800a52c: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800a52e: 6d5a ldr r2, [r3, #84] @ 0x54 800a530: 430a orrs r2, r1 800a532: 655a str r2, [r3, #84] @ 0x54 break; 800a534: e766 b.n 800a404 __HAL_LOCK(htim); 800a536: 2002 movs r0, #2 } 800a538: bdf8 pop {r3, r4, r5, r6, r7, pc} 800a53a: bf00 nop 800a53c: feff8fff .word 0xfeff8fff 800a540: 40010000 .word 0x40010000 800a544: 40014000 .word 0x40014000 800a548: feff8cff .word 0xfeff8cff 800a54c: fffeff8f .word 0xfffeff8f 0800a550 : assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 800a550: f890 303c ldrb.w r3, [r0, #60] @ 0x3c 800a554: 2b01 cmp r3, #1 800a556: d04b beq.n 800a5f0 /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 800a558: 6803 ldr r3, [r0, #0] 800a55a: 4602 mov r2, r0 htim->State = HAL_TIM_STATE_BUSY; 800a55c: 2002 movs r0, #2 { 800a55e: b430 push {r4, r5} /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800a560: 4d24 ldr r5, [pc, #144] @ (800a5f4 ) htim->State = HAL_TIM_STATE_BUSY; 800a562: f882 003d strb.w r0, [r2, #61] @ 0x3d if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800a566: 42ab cmp r3, r5 tmpcr2 = htim->Instance->CR2; 800a568: 6858 ldr r0, [r3, #4] tmpsmcr = htim->Instance->SMCR; 800a56a: 689c ldr r4, [r3, #8] if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 800a56c: d029 beq.n 800a5c2 800a56e: f505 6580 add.w r5, r5, #1024 @ 0x400 800a572: 42ab cmp r3, r5 800a574: d025 beq.n 800a5c2 tmpcr2 |= sMasterConfig->MasterOutputTrigger; /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800a576: 4d20 ldr r5, [pc, #128] @ (800a5f8 ) tmpcr2 &= ~TIM_CR2_MMS; 800a578: f020 0070 bic.w r0, r0, #112 @ 0x70 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800a57c: 42ab cmp r3, r5 800a57e: bf18 it ne 800a580: f1b3 4f80 cmpne.w r3, #1073741824 @ 0x40000000 800a584: f505 6580 add.w r5, r5, #1024 @ 0x400 800a588: bf0c ite eq 800a58a: f04f 0c01 moveq.w ip, #1 800a58e: f04f 0c00 movne.w ip, #0 800a592: 42ab cmp r3, r5 800a594: bf08 it eq 800a596: f04c 0c01 orreq.w ip, ip, #1 800a59a: f505 6580 add.w r5, r5, #1024 @ 0x400 800a59e: 42ab cmp r3, r5 800a5a0: bf08 it eq 800a5a2: f04c 0c01 orreq.w ip, ip, #1 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800a5a6: 680d ldr r5, [r1, #0] 800a5a8: 4328 orrs r0, r5 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800a5aa: 4d14 ldr r5, [pc, #80] @ (800a5fc ) htim->Instance->CR2 = tmpcr2; 800a5ac: 6058 str r0, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800a5ae: 42ab cmp r3, r5 800a5b0: bf14 ite ne 800a5b2: 4660 movne r0, ip 800a5b4: f04c 0001 orreq.w r0, ip, #1 800a5b8: b960 cbnz r0, 800a5d4 800a5ba: 4811 ldr r0, [pc, #68] @ (800a600 ) 800a5bc: 4283 cmp r3, r0 800a5be: d009 beq.n 800a5d4 800a5c0: e00d b.n 800a5de tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 800a5c2: 684d ldr r5, [r1, #4] tmpcr2 &= ~TIM_CR2_MMS2; 800a5c4: f420 0070 bic.w r0, r0, #15728640 @ 0xf00000 tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 800a5c8: 4328 orrs r0, r5 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800a5ca: 680d ldr r5, [r1, #0] tmpcr2 &= ~TIM_CR2_MMS; 800a5cc: f020 0070 bic.w r0, r0, #112 @ 0x70 tmpcr2 |= sMasterConfig->MasterOutputTrigger; 800a5d0: 4328 orrs r0, r5 htim->Instance->CR2 = tmpcr2; 800a5d2: 6058 str r0, [r3, #4] { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800a5d4: 6889 ldr r1, [r1, #8] tmpsmcr &= ~TIM_SMCR_MSM; 800a5d6: f024 0480 bic.w r4, r4, #128 @ 0x80 tmpsmcr |= sMasterConfig->MasterSlaveMode; 800a5da: 430c orrs r4, r1 /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800a5dc: 609c str r4, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); 800a5de: 2300 movs r3, #0 htim->State = HAL_TIM_STATE_READY; 800a5e0: 2101 movs r1, #1 return HAL_OK; 800a5e2: 4618 mov r0, r3 htim->State = HAL_TIM_STATE_READY; 800a5e4: f882 103d strb.w r1, [r2, #61] @ 0x3d __HAL_UNLOCK(htim); 800a5e8: f882 303c strb.w r3, [r2, #60] @ 0x3c } 800a5ec: bc30 pop {r4, r5} 800a5ee: 4770 bx lr __HAL_LOCK(htim); 800a5f0: 2002 movs r0, #2 } 800a5f2: 4770 bx lr 800a5f4: 40010000 .word 0x40010000 800a5f8: 40000400 .word 0x40000400 800a5fc: 40001800 .word 0x40001800 800a600: 40014000 .word 0x40014000 0800a604 : #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 800a604: f890 303c ldrb.w r3, [r0, #60] @ 0x3c 800a608: 2b01 cmp r3, #1 800a60a: d03d beq.n 800a688 the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 800a60c: 4602 mov r2, r0 800a60e: 6848 ldr r0, [r1, #4] { 800a610: b410 push {r4} MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 800a612: e9d1 4302 ldrd r4, r3, [r1, #8] 800a616: f423 7340 bic.w r3, r3, #768 @ 0x300 800a61a: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 800a61c: 680c ldr r4, [r1, #0] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 800a61e: f423 6380 bic.w r3, r3, #1024 @ 0x400 800a622: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 800a624: 6908 ldr r0, [r1, #16] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 800a626: f423 6300 bic.w r3, r3, #2048 @ 0x800 800a62a: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 800a62c: 694c ldr r4, [r1, #20] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 800a62e: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800a632: 4303 orrs r3, r0 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 800a634: 6a88 ldr r0, [r1, #40] @ 0x28 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 800a636: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800a63a: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 800a63c: 698c ldr r4, [r1, #24] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 800a63e: f423 4380 bic.w r3, r3, #16384 @ 0x4000 800a642: 4303 orrs r3, r0 #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 800a644: 6810 ldr r0, [r2, #0] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 800a646: f423 2370 bic.w r3, r3, #983040 @ 0xf0000 800a64a: ea43 4304 orr.w r3, r3, r4, lsl #16 if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 800a64e: 4c0f ldr r4, [pc, #60] @ (800a68c ) 800a650: 42a0 cmp r0, r4 800a652: d00b beq.n 800a66c 800a654: f504 6480 add.w r4, r4, #1024 @ 0x400 800a658: 42a0 cmp r0, r4 800a65a: d007 beq.n 800a66c } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; __HAL_UNLOCK(htim); 800a65c: 2100 movs r1, #0 htim->Instance->BDTR = tmpbdtr; 800a65e: 6443 str r3, [r0, #68] @ 0x44 __HAL_UNLOCK(htim); 800a660: f882 103c strb.w r1, [r2, #60] @ 0x3c return HAL_OK; 800a664: 4608 mov r0, r1 } 800a666: f85d 4b04 ldr.w r4, [sp], #4 800a66a: 4770 bx lr MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 800a66c: 6a4c ldr r4, [r1, #36] @ 0x24 800a66e: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 800a672: ea43 5304 orr.w r3, r3, r4, lsl #20 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 800a676: e9d1 4107 ldrd r4, r1, [r1, #28] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 800a67a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800a67e: 4323 orrs r3, r4 MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 800a680: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000 800a684: 430b orrs r3, r1 800a686: e7e9 b.n 800a65c __HAL_LOCK(htim); 800a688: 2002 movs r0, #2 } 800a68a: 4770 bx lr 800a68c: 40010000 .word 0x40010000 0800a690 : /** * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) 800a690: 4770 bx lr 800a692: bf00 nop 0800a694 : /** * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) 800a694: 4770 bx lr 800a696: bf00 nop 0800a698 : /** * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) 800a698: 4770 bx lr 800a69a: bf00 nop 0800a69c : static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800a69c: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88 800a6a0: 2b21 cmp r3, #33 @ 0x21 800a6a2: d000 beq.n 800a6a6 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 800a6a4: 4770 bx lr if (huart->TxXferCount == 0U) 800a6a6: f8b0 3056 ldrh.w r3, [r0, #86] @ 0x56 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 800a6aa: 6802 ldr r2, [r0, #0] if (huart->TxXferCount == 0U) 800a6ac: b29b uxth r3, r3 800a6ae: b983 cbnz r3, 800a6d2 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a6b0: e852 3f00 ldrex r3, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 800a6b4: f023 0380 bic.w r3, r3, #128 @ 0x80 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a6b8: e842 3100 strex r1, r3, [r2] 800a6bc: 2900 cmp r1, #0 800a6be: d1f7 bne.n 800a6b0 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a6c0: e852 3f00 ldrex r3, [r2] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a6c4: f043 0340 orr.w r3, r3, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a6c8: e842 3100 strex r1, r3, [r2] 800a6cc: 2900 cmp r1, #0 800a6ce: d1f7 bne.n 800a6c0 800a6d0: 4770 bx lr huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 800a6d2: 6d01 ldr r1, [r0, #80] @ 0x50 800a6d4: f831 3b02 ldrh.w r3, [r1], #2 800a6d8: f3c3 0308 ubfx r3, r3, #0, #9 800a6dc: 6293 str r3, [r2, #40] @ 0x28 huart->TxXferCount--; 800a6de: f8b0 3056 ldrh.w r3, [r0, #86] @ 0x56 huart->pTxBuffPtr += 2U; 800a6e2: 6501 str r1, [r0, #80] @ 0x50 huart->TxXferCount--; 800a6e4: 3b01 subs r3, #1 800a6e6: b29b uxth r3, r3 800a6e8: f8a0 3056 strh.w r3, [r0, #86] @ 0x56 } 800a6ec: 4770 bx lr 800a6ee: bf00 nop 0800a6f0 : { const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800a6f0: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88 800a6f4: 2b21 cmp r3, #33 @ 0x21 800a6f6: d000 beq.n 800a6fa 800a6f8: 4770 bx lr { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a6fa: f8b0 306a ldrh.w r3, [r0, #106] @ 0x6a 800a6fe: 2b00 cmp r3, #0 800a700: d0fa beq.n 800a6f8 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); break; /* force exit loop */ } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 800a702: 6801 ldr r1, [r0, #0] { 800a704: b410 push {r4} if (huart->TxXferCount == 0U) 800a706: f8b0 2056 ldrh.w r2, [r0, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a70a: 3b01 subs r3, #1 if (huart->TxXferCount == 0U) 800a70c: b292 uxth r2, r2 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a70e: b29b uxth r3, r3 if (huart->TxXferCount == 0U) 800a710: b1a2 cbz r2, 800a73c else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 800a712: 69ca ldr r2, [r1, #28] 800a714: 0612 lsls r2, r2, #24 800a716: d50c bpl.n 800a732 { tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 800a718: 6d04 ldr r4, [r0, #80] @ 0x50 800a71a: f834 2b02 ldrh.w r2, [r4], #2 800a71e: f3c2 0208 ubfx r2, r2, #0, #9 800a722: 628a str r2, [r1, #40] @ 0x28 huart->pTxBuffPtr += 2U; huart->TxXferCount--; 800a724: f8b0 2056 ldrh.w r2, [r0, #86] @ 0x56 huart->pTxBuffPtr += 2U; 800a728: 6504 str r4, [r0, #80] @ 0x50 huart->TxXferCount--; 800a72a: 3a01 subs r2, #1 800a72c: b292 uxth r2, r2 800a72e: f8a0 2056 strh.w r2, [r0, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a732: 2b00 cmp r3, #0 800a734: d1e7 bne.n 800a706 { /* Nothing to do */ } } } } 800a736: f85d 4b04 ldr.w r4, [sp], #4 800a73a: 4770 bx lr __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a73c: f101 0308 add.w r3, r1, #8 800a740: e853 3f00 ldrex r3, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 800a744: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a748: f101 0008 add.w r0, r1, #8 800a74c: e840 3200 strex r2, r3, [r0] 800a750: 2a00 cmp r2, #0 800a752: d1f3 bne.n 800a73c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a754: e851 3f00 ldrex r3, [r1] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a758: f043 0340 orr.w r3, r3, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a75c: e841 3200 strex r2, r3, [r1] 800a760: 2a00 cmp r2, #0 800a762: d0e8 beq.n 800a736 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a764: e851 3f00 ldrex r3, [r1] 800a768: f043 0340 orr.w r3, r3, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a76c: e841 3200 strex r2, r3, [r1] 800a770: 2a00 cmp r2, #0 800a772: d1ef bne.n 800a754 800a774: e7df b.n 800a736 800a776: bf00 nop 0800a778 : if (huart->gState == HAL_UART_STATE_BUSY_TX) 800a778: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88 800a77c: 2b21 cmp r3, #33 @ 0x21 800a77e: d000 beq.n 800a782 } 800a780: 4770 bx lr if (huart->TxXferCount == 0U) 800a782: f8b0 3056 ldrh.w r3, [r0, #86] @ 0x56 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 800a786: 6802 ldr r2, [r0, #0] if (huart->TxXferCount == 0U) 800a788: b29b uxth r3, r3 800a78a: b983 cbnz r3, 800a7ae __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a78c: e852 3f00 ldrex r3, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 800a790: f023 0380 bic.w r3, r3, #128 @ 0x80 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a794: e842 3100 strex r1, r3, [r2] 800a798: 2900 cmp r1, #0 800a79a: d1f7 bne.n 800a78c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a79c: e852 3f00 ldrex r3, [r2] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a7a0: f043 0340 orr.w r3, r3, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a7a4: e842 3100 strex r1, r3, [r2] 800a7a8: 2900 cmp r1, #0 800a7aa: d1f7 bne.n 800a79c 800a7ac: 4770 bx lr huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 800a7ae: 6d01 ldr r1, [r0, #80] @ 0x50 800a7b0: f811 3b01 ldrb.w r3, [r1], #1 800a7b4: 6293 str r3, [r2, #40] @ 0x28 huart->TxXferCount--; 800a7b6: f8b0 3056 ldrh.w r3, [r0, #86] @ 0x56 huart->pTxBuffPtr++; 800a7ba: 6501 str r1, [r0, #80] @ 0x50 huart->TxXferCount--; 800a7bc: 3b01 subs r3, #1 800a7be: b29b uxth r3, r3 800a7c0: f8a0 3056 strh.w r3, [r0, #86] @ 0x56 } 800a7c4: 4770 bx lr 800a7c6: bf00 nop 0800a7c8 : if (huart->gState == HAL_UART_STATE_BUSY_TX) 800a7c8: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88 800a7cc: 2b21 cmp r3, #33 @ 0x21 800a7ce: d000 beq.n 800a7d2 800a7d0: 4770 bx lr for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a7d2: f8b0 306a ldrh.w r3, [r0, #106] @ 0x6a 800a7d6: 2b00 cmp r3, #0 800a7d8: d0fa beq.n 800a7d0 else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 800a7da: 6801 ldr r1, [r0, #0] { 800a7dc: b410 push {r4} if (huart->TxXferCount == 0U) 800a7de: f8b0 2056 ldrh.w r2, [r0, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a7e2: 3b01 subs r3, #1 if (huart->TxXferCount == 0U) 800a7e4: b292 uxth r2, r2 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a7e6: b29b uxth r3, r3 if (huart->TxXferCount == 0U) 800a7e8: b192 cbz r2, 800a810 else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 800a7ea: 69ca ldr r2, [r1, #28] 800a7ec: 0612 lsls r2, r2, #24 800a7ee: d50a bpl.n 800a806 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 800a7f0: 6d04 ldr r4, [r0, #80] @ 0x50 800a7f2: f814 2b01 ldrb.w r2, [r4], #1 800a7f6: 628a str r2, [r1, #40] @ 0x28 huart->TxXferCount--; 800a7f8: f8b0 2056 ldrh.w r2, [r0, #86] @ 0x56 huart->pTxBuffPtr++; 800a7fc: 6504 str r4, [r0, #80] @ 0x50 huart->TxXferCount--; 800a7fe: 3a01 subs r2, #1 800a800: b292 uxth r2, r2 800a802: f8a0 2056 strh.w r2, [r0, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a806: 2b00 cmp r3, #0 800a808: d1e9 bne.n 800a7de } 800a80a: f85d 4b04 ldr.w r4, [sp], #4 800a80e: 4770 bx lr __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a810: f101 0308 add.w r3, r1, #8 800a814: e853 3f00 ldrex r3, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 800a818: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a81c: f101 0008 add.w r0, r1, #8 800a820: e840 3200 strex r2, r3, [r0] 800a824: 2a00 cmp r2, #0 800a826: d1f3 bne.n 800a810 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a828: e851 3f00 ldrex r3, [r1] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a82c: f043 0340 orr.w r3, r3, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a830: e841 3200 strex r2, r3, [r1] 800a834: 2a00 cmp r2, #0 800a836: d0e8 beq.n 800a80a __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a838: e851 3f00 ldrex r3, [r1] 800a83c: f043 0340 orr.w r3, r3, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a840: e841 3200 strex r2, r3, [r1] 800a844: 2a00 cmp r2, #0 800a846: d1ef bne.n 800a828 800a848: e7df b.n 800a80a 800a84a: bf00 nop 0800a84c : if (huart->gState == HAL_UART_STATE_READY) 800a84c: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88 800a850: 2b20 cmp r3, #32 800a852: d128 bne.n 800a8a6 if ((pData == NULL) || (Size == 0U)) 800a854: b329 cbz r1, 800a8a2 800a856: fab2 f382 clz r3, r2 800a85a: 095b lsrs r3, r3, #5 800a85c: b30a cbz r2, 800a8a2 { 800a85e: b410 push {r4} huart->pTxBuffPtr = pData; 800a860: 6501 str r1, [r0, #80] @ 0x50 huart->gState = HAL_UART_STATE_BUSY_TX; 800a862: 2421 movs r4, #33 @ 0x21 if (huart->FifoMode == UART_FIFOMODE_ENABLE) 800a864: 6e41 ldr r1, [r0, #100] @ 0x64 huart->TxXferCount = Size; 800a866: f8a0 2056 strh.w r2, [r0, #86] @ 0x56 if (huart->FifoMode == UART_FIFOMODE_ENABLE) 800a86a: f1b1 5f00 cmp.w r1, #536870912 @ 0x20000000 huart->ErrorCode = HAL_UART_ERROR_NONE; 800a86e: f8c0 3090 str.w r3, [r0, #144] @ 0x90 huart->TxXferSize = Size; 800a872: f8a0 2054 strh.w r2, [r0, #84] @ 0x54 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800a876: 6883 ldr r3, [r0, #8] huart->gState = HAL_UART_STATE_BUSY_TX; 800a878: f8c0 4088 str.w r4, [r0, #136] @ 0x88 if (huart->FifoMode == UART_FIFOMODE_ENABLE) 800a87c: d01c beq.n 800a8b8 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800a87e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800a882: d012 beq.n 800a8aa huart->TxISR = UART_TxISR_8BIT; 800a884: 4b1b ldr r3, [pc, #108] @ (800a8f4 ) 800a886: 6802 ldr r2, [r0, #0] 800a888: 6783 str r3, [r0, #120] @ 0x78 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a88a: e852 3f00 ldrex r3, [r2] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 800a88e: f043 0380 orr.w r3, r3, #128 @ 0x80 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a892: e842 3100 strex r1, r3, [r2] 800a896: 2900 cmp r1, #0 800a898: d1f7 bne.n 800a88a return HAL_OK; 800a89a: 2000 movs r0, #0 } 800a89c: f85d 4b04 ldr.w r4, [sp], #4 800a8a0: 4770 bx lr return HAL_ERROR; 800a8a2: 2001 movs r0, #1 } 800a8a4: 4770 bx lr return HAL_BUSY; 800a8a6: 2002 movs r0, #2 800a8a8: 4770 bx lr if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800a8aa: 6901 ldr r1, [r0, #16] huart->TxISR = UART_TxISR_16BIT; 800a8ac: 4b11 ldr r3, [pc, #68] @ (800a8f4 ) 800a8ae: 4a12 ldr r2, [pc, #72] @ (800a8f8 ) 800a8b0: 2900 cmp r1, #0 800a8b2: bf08 it eq 800a8b4: 4613 moveq r3, r2 800a8b6: e7e6 b.n 800a886 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800a8b8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800a8bc: d012 beq.n 800a8e4 huart->TxISR = UART_TxISR_8BIT_FIFOEN; 800a8be: 4b0f ldr r3, [pc, #60] @ (800a8fc ) 800a8c0: 6802 ldr r2, [r0, #0] 800a8c2: 6783 str r3, [r0, #120] @ 0x78 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a8c4: f102 0308 add.w r3, r2, #8 800a8c8: e853 3f00 ldrex r3, [r3] ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 800a8cc: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a8d0: f102 0008 add.w r0, r2, #8 800a8d4: e840 3100 strex r1, r3, [r0] 800a8d8: 2900 cmp r1, #0 800a8da: d1f3 bne.n 800a8c4 return HAL_OK; 800a8dc: 2000 movs r0, #0 } 800a8de: f85d 4b04 ldr.w r4, [sp], #4 800a8e2: 4770 bx lr if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800a8e4: 6901 ldr r1, [r0, #16] huart->TxISR = UART_TxISR_16BIT_FIFOEN; 800a8e6: 4b05 ldr r3, [pc, #20] @ (800a8fc ) 800a8e8: 4a05 ldr r2, [pc, #20] @ (800a900 ) 800a8ea: 2900 cmp r1, #0 800a8ec: bf08 it eq 800a8ee: 4613 moveq r3, r2 800a8f0: e7e6 b.n 800a8c0 800a8f2: bf00 nop 800a8f4: 0800a779 .word 0x0800a779 800a8f8: 0800a69d .word 0x0800a69d 800a8fc: 0800a7c9 .word 0x0800a7c9 800a900: 0800a6f1 .word 0x0800a6f1 0800a904 : __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) 800a904: 4770 bx lr 800a906: bf00 nop 0800a908 : { 800a908: b508 push {r3, lr} UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 800a90a: 6b80 ldr r0, [r0, #56] @ 0x38 huart->RxXferCount = 0U; 800a90c: 2300 movs r3, #0 800a90e: f8a0 305e strh.w r3, [r0, #94] @ 0x5e huart->TxXferCount = 0U; 800a912: f8a0 3056 strh.w r3, [r0, #86] @ 0x56 HAL_UART_ErrorCallback(huart); 800a916: f7ff fff5 bl 800a904 } 800a91a: bd08 pop {r3, pc} 0800a91c : uint32_t isrflags = READ_REG(huart->Instance->ISR); 800a91c: 6803 ldr r3, [r0, #0] errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 800a91e: f640 0c0f movw ip, #2063 @ 0x80f uint32_t isrflags = READ_REG(huart->Instance->ISR); 800a922: 69da ldr r2, [r3, #28] uint32_t cr1its = READ_REG(huart->Instance->CR1); 800a924: 6819 ldr r1, [r3, #0] if (errorflags == 0U) 800a926: ea12 0f0c tst.w r2, ip { 800a92a: b570 push {r4, r5, r6, lr} 800a92c: 4604 mov r4, r0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 800a92e: 689d ldr r5, [r3, #8] if (errorflags == 0U) 800a930: d145 bne.n 800a9be if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 800a932: 0696 lsls r6, r2, #26 800a934: d507 bpl.n 800a946 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 800a936: f001 0c20 and.w ip, r1, #32 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 800a93a: f005 5e80 and.w lr, r5, #268435456 @ 0x10000000 800a93e: ea5c 0c0e orrs.w ip, ip, lr 800a942: f040 813a bne.w 800abba if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800a946: 6ee0 ldr r0, [r4, #108] @ 0x6c 800a948: 2801 cmp r0, #1 800a94a: f000 80d6 beq.w 800aafa if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 800a94e: 02d6 lsls r6, r2, #11 800a950: d41d bmi.n 800a98e if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 800a952: 0616 lsls r6, r2, #24 800a954: d506 bpl.n 800a964 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 800a956: f405 0500 and.w r5, r5, #8388608 @ 0x800000 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 800a95a: f001 0080 and.w r0, r1, #128 @ 0x80 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 800a95e: 4328 orrs r0, r5 800a960: f040 8132 bne.w 800abc8 if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 800a964: 0650 lsls r0, r2, #25 800a966: d51c bpl.n 800a9a2 800a968: 064e lsls r6, r1, #25 800a96a: d51a bpl.n 800a9a2 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a96c: e853 2f00 ldrex r2, [r3] * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a970: f022 0240 bic.w r2, r2, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a974: e843 2100 strex r1, r2, [r3] 800a978: 2900 cmp r1, #0 800a97a: d1f7 bne.n 800a96c /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 800a97c: 2220 movs r2, #32 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 800a97e: 2300 movs r3, #0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 800a980: 4620 mov r0, r4 huart->gState = HAL_UART_STATE_READY; 800a982: f8c4 2088 str.w r2, [r4, #136] @ 0x88 huart->TxISR = NULL; 800a986: 67a3 str r3, [r4, #120] @ 0x78 HAL_UART_TxCpltCallback(huart); 800a988: f7f9 fa6c bl 8003e64 } 800a98c: bd70 pop {r4, r5, r6, pc} if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 800a98e: 0268 lsls r0, r5, #9 800a990: d5df bpl.n 800a952 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 800a992: f44f 1280 mov.w r2, #1048576 @ 0x100000 HAL_UARTEx_WakeupCallback(huart); 800a996: 4620 mov r0, r4 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 800a998: 621a str r2, [r3, #32] } 800a99a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_UARTEx_WakeupCallback(huart); 800a99e: f001 b815 b.w 800b9cc if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 800a9a2: 0215 lsls r5, r2, #8 800a9a4: d502 bpl.n 800a9ac 800a9a6: 0048 lsls r0, r1, #1 800a9a8: f100 8134 bmi.w 800ac14 if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 800a9ac: 01d3 lsls r3, r2, #7 800a9ae: d5ed bpl.n 800a98c 800a9b0: 2900 cmp r1, #0 800a9b2: daeb bge.n 800a98c HAL_UARTEx_RxFifoFullCallback(huart); 800a9b4: 4620 mov r0, r4 } 800a9b6: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_UARTEx_RxFifoFullCallback(huart); 800a9ba: f001 b809 b.w 800b9d0 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 800a9be: 48b6 ldr r0, [pc, #728] @ (800ac98 ) 800a9c0: ea05 0c00 and.w ip, r5, r0 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 800a9c4: 48b5 ldr r0, [pc, #724] @ (800ac9c ) 800a9c6: 4008 ands r0, r1 800a9c8: ea50 000c orrs.w r0, r0, ip 800a9cc: d0bb beq.n 800a946 if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800a9ce: 07d6 lsls r6, r2, #31 800a9d0: d509 bpl.n 800a9e6 800a9d2: 05c8 lsls r0, r1, #23 800a9d4: d507 bpl.n 800a9e6 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 800a9d6: 2001 movs r0, #1 800a9d8: 6218 str r0, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 800a9da: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90 800a9de: f040 0001 orr.w r0, r0, #1 800a9e2: f8c4 0090 str.w r0, [r4, #144] @ 0x90 if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800a9e6: 0796 lsls r6, r2, #30 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800a9e8: f002 0004 and.w r0, r2, #4 if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800a9ec: f140 80de bpl.w 800abac 800a9f0: 07ee lsls r6, r5, #31 800a9f2: d510 bpl.n 800aa16 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 800a9f4: 2602 movs r6, #2 800a9f6: 621e str r6, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 800a9f8: f8d4 6090 ldr.w r6, [r4, #144] @ 0x90 800a9fc: f046 0604 orr.w r6, r6, #4 800aa00: f8c4 6090 str.w r6, [r4, #144] @ 0x90 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800aa04: b138 cbz r0, 800aa16 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 800aa06: 2004 movs r0, #4 800aa08: 6218 str r0, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 800aa0a: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90 800aa0e: f040 0002 orr.w r0, r0, #2 800aa12: f8c4 0090 str.w r0, [r4, #144] @ 0x90 if (((isrflags & USART_ISR_ORE) != 0U) 800aa16: 0716 lsls r6, r2, #28 800aa18: d50c bpl.n 800aa34 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 800aa1a: f001 0020 and.w r0, r1, #32 800aa1e: ea50 000c orrs.w r0, r0, ip 800aa22: d007 beq.n 800aa34 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 800aa24: 2008 movs r0, #8 800aa26: 6218 str r0, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 800aa28: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90 800aa2c: f040 0008 orr.w r0, r0, #8 800aa30: f8c4 0090 str.w r0, [r4, #144] @ 0x90 if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 800aa34: 0510 lsls r0, r2, #20 800aa36: d50a bpl.n 800aa4e 800aa38: 014e lsls r6, r1, #5 800aa3a: d508 bpl.n 800aa4e __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800aa3c: f44f 6000 mov.w r0, #2048 @ 0x800 800aa40: 6218 str r0, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 800aa42: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90 800aa46: f040 0020 orr.w r0, r0, #32 800aa4a: f8c4 0090 str.w r0, [r4, #144] @ 0x90 if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800aa4e: f8d4 0090 ldr.w r0, [r4, #144] @ 0x90 800aa52: 2800 cmp r0, #0 800aa54: d09a beq.n 800a98c if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 800aa56: 0690 lsls r0, r2, #26 800aa58: d506 bpl.n 800aa68 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 800aa5a: f001 0120 and.w r1, r1, #32 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 800aa5e: f005 5580 and.w r5, r5, #268435456 @ 0x10000000 800aa62: 4329 orrs r1, r5 800aa64: f040 80ca bne.w 800abfc errorcode = huart->ErrorCode; 800aa68: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 800aa6c: 689a ldr r2, [r3, #8] ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 800aa6e: f001 0128 and.w r1, r1, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 800aa72: f002 0240 and.w r2, r2, #64 @ 0x40 800aa76: ea52 0501 orrs.w r5, r2, r1 800aa7a: f000 80d0 beq.w 800ac1e __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800aa7e: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800aa82: f422 7290 bic.w r2, r2, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800aa86: e843 2100 strex r1, r2, [r3] 800aa8a: 2900 cmp r1, #0 800aa8c: d1f7 bne.n 800aa7e ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800aa8e: 4884 ldr r0, [pc, #528] @ (800aca0 ) __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800aa90: f103 0208 add.w r2, r3, #8 800aa94: e852 2f00 ldrex r2, [r2] 800aa98: 4002 ands r2, r0 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800aa9a: f103 0508 add.w r5, r3, #8 800aa9e: e845 2100 strex r1, r2, [r5] 800aaa2: 2900 cmp r1, #0 800aaa4: d1f4 bne.n 800aa90 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800aaa6: 6ee2 ldr r2, [r4, #108] @ 0x6c 800aaa8: 2a01 cmp r2, #1 800aaaa: f000 8095 beq.w 800abd8 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800aaae: 2200 movs r2, #0 huart->RxState = HAL_UART_STATE_READY; 800aab0: 2120 movs r1, #32 800aab2: f8c4 108c str.w r1, [r4, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800aab6: 66e2 str r2, [r4, #108] @ 0x6c if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800aab8: 6899 ldr r1, [r3, #8] huart->RxISR = NULL; 800aaba: 6762 str r2, [r4, #116] @ 0x74 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800aabc: 064a lsls r2, r1, #25 800aabe: f140 80a5 bpl.w 800ac0c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800aac2: f103 0208 add.w r2, r3, #8 800aac6: e852 2f00 ldrex r2, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800aaca: f022 0240 bic.w r2, r2, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800aace: f103 0008 add.w r0, r3, #8 800aad2: e840 2100 strex r1, r2, [r0] 800aad6: 2900 cmp r1, #0 800aad8: d1f3 bne.n 800aac2 if (huart->hdmarx != NULL) 800aada: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80 800aade: 2800 cmp r0, #0 800aae0: f000 8094 beq.w 800ac0c huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 800aae4: 4b6f ldr r3, [pc, #444] @ (800aca4 ) 800aae6: 6503 str r3, [r0, #80] @ 0x50 if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 800aae8: f7fb fe24 bl 8006734 800aaec: 2800 cmp r0, #0 800aaee: f43f af4d beq.w 800a98c huart->hdmarx->XferAbortCallback(huart->hdmarx); 800aaf2: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80 800aaf6: 6d03 ldr r3, [r0, #80] @ 0x50 800aaf8: e063 b.n 800abc2 && ((isrflags & USART_ISR_IDLE) != 0U) 800aafa: 06d6 lsls r6, r2, #27 800aafc: f57f af27 bpl.w 800a94e && ((cr1its & USART_ISR_IDLE) != 0U)) 800ab00: 06c8 lsls r0, r1, #27 800ab02: f57f af24 bpl.w 800a94e __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800ab06: 2210 movs r2, #16 800ab08: 621a str r2, [r3, #32] if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 800ab0a: 689a ldr r2, [r3, #8] 800ab0c: 0652 lsls r2, r2, #25 800ab0e: f140 808c bpl.w 800ac2a uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 800ab12: f8d4 0080 ldr.w r0, [r4, #128] @ 0x80 800ab16: 6801 ldr r1, [r0, #0] 800ab18: 684a ldr r2, [r1, #4] 800ab1a: b292 uxth r2, r2 if ((nb_remaining_rx_data > 0U) 800ab1c: 2a00 cmp r2, #0 800ab1e: f43f af35 beq.w 800a98c && (nb_remaining_rx_data < huart->RxXferSize)) 800ab22: f8b4 105c ldrh.w r1, [r4, #92] @ 0x5c 800ab26: 4291 cmp r1, r2 800ab28: f67f af30 bls.w 800a98c huart->RxXferCount = nb_remaining_rx_data; 800ab2c: f8a4 205e strh.w r2, [r4, #94] @ 0x5e if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 800ab30: 69c2 ldr r2, [r0, #28] 800ab32: f5b2 7f80 cmp.w r2, #256 @ 0x100 800ab36: d02f beq.n 800ab98 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ab38: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800ab3c: f422 7280 bic.w r2, r2, #256 @ 0x100 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ab40: e843 2100 strex r1, r2, [r3] 800ab44: 2900 cmp r1, #0 800ab46: d1f7 bne.n 800ab38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ab48: f103 0208 add.w r2, r3, #8 800ab4c: e852 2f00 ldrex r2, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800ab50: f022 0201 bic.w r2, r2, #1 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ab54: f103 0508 add.w r5, r3, #8 800ab58: e845 2100 strex r1, r2, [r5] 800ab5c: 2900 cmp r1, #0 800ab5e: d1f3 bne.n 800ab48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ab60: f103 0208 add.w r2, r3, #8 800ab64: e852 2f00 ldrex r2, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 800ab68: f022 0240 bic.w r2, r2, #64 @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ab6c: f103 0508 add.w r5, r3, #8 800ab70: e845 2100 strex r1, r2, [r5] 800ab74: 2900 cmp r1, #0 800ab76: d1f3 bne.n 800ab60 huart->RxState = HAL_UART_STATE_READY; 800ab78: 2220 movs r2, #32 800ab7a: f8c4 208c str.w r2, [r4, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800ab7e: 66e1 str r1, [r4, #108] @ 0x6c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ab80: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800ab84: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ab88: e843 2100 strex r1, r2, [r3] 800ab8c: 2900 cmp r1, #0 800ab8e: d1f7 bne.n 800ab80 (void)HAL_DMA_Abort(huart->hdmarx); 800ab90: f7fb fc1e bl 80063d0 HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 800ab94: f8b4 105c ldrh.w r1, [r4, #92] @ 0x5c huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800ab98: 2302 movs r3, #2 HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 800ab9a: 4620 mov r0, r4 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800ab9c: 6723 str r3, [r4, #112] @ 0x70 HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 800ab9e: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e 800aba2: 1ac9 subs r1, r1, r3 800aba4: b289 uxth r1, r1 800aba6: f7f9 f993 bl 8003ed0 } 800abaa: bd70 pop {r4, r5, r6, pc} if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800abac: 2800 cmp r0, #0 800abae: f43f af32 beq.w 800aa16 800abb2: 07e8 lsls r0, r5, #31 800abb4: f53f af27 bmi.w 800aa06 800abb8: e72d b.n 800aa16 if (huart->RxISR != NULL) 800abba: 6f43 ldr r3, [r0, #116] @ 0x74 800abbc: 2b00 cmp r3, #0 800abbe: f43f aee5 beq.w 800a98c } 800abc2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} huart->hdmarx->XferAbortCallback(huart->hdmarx); 800abc6: 4718 bx r3 if (huart->TxISR != NULL) 800abc8: 6fa3 ldr r3, [r4, #120] @ 0x78 800abca: 2b00 cmp r3, #0 800abcc: f43f aede beq.w 800a98c huart->TxISR(huart); 800abd0: 4620 mov r0, r4 } 800abd2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} huart->TxISR(huart); 800abd6: 4718 bx r3 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800abd8: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800abdc: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800abe0: e843 2100 strex r1, r2, [r3] 800abe4: 2900 cmp r1, #0 800abe6: f43f af62 beq.w 800aaae __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800abea: e853 2f00 ldrex r2, [r3] 800abee: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800abf2: e843 2100 strex r1, r2, [r3] 800abf6: 2900 cmp r1, #0 800abf8: d1ee bne.n 800abd8 800abfa: e758 b.n 800aaae if (huart->RxISR != NULL) 800abfc: 6f62 ldr r2, [r4, #116] @ 0x74 800abfe: 2a00 cmp r2, #0 800ac00: f43f af32 beq.w 800aa68 huart->RxISR(huart); 800ac04: 4620 mov r0, r4 800ac06: 4790 blx r2 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 800ac08: 6823 ldr r3, [r4, #0] 800ac0a: e72d b.n 800aa68 HAL_UART_ErrorCallback(huart); 800ac0c: 4620 mov r0, r4 800ac0e: f7ff fe79 bl 800a904 } 800ac12: bd70 pop {r4, r5, r6, pc} HAL_UARTEx_TxFifoEmptyCallback(huart); 800ac14: 4620 mov r0, r4 } 800ac16: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} HAL_UARTEx_TxFifoEmptyCallback(huart); 800ac1a: f000 bedb b.w 800b9d4 HAL_UART_ErrorCallback(huart); 800ac1e: 4620 mov r0, r4 800ac20: f7ff fe70 bl 800a904 huart->ErrorCode = HAL_UART_ERROR_NONE; 800ac24: f8c4 5090 str.w r5, [r4, #144] @ 0x90 } 800ac28: bd70 pop {r4, r5, r6, pc} uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 800ac2a: f8b4 005e ldrh.w r0, [r4, #94] @ 0x5e 800ac2e: f8b4 105c ldrh.w r1, [r4, #92] @ 0x5c if ((huart->RxXferCount > 0U) 800ac32: f8b4 205e ldrh.w r2, [r4, #94] @ 0x5e uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 800ac36: 1a09 subs r1, r1, r0 if ((huart->RxXferCount > 0U) 800ac38: b292 uxth r2, r2 uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 800ac3a: b289 uxth r1, r1 && (nb_rx_data > 0U)) 800ac3c: 2a00 cmp r2, #0 800ac3e: f43f aea5 beq.w 800a98c 800ac42: 2900 cmp r1, #0 800ac44: f43f aea2 beq.w 800a98c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ac48: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800ac4c: f422 7290 bic.w r2, r2, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ac50: e843 2000 strex r0, r2, [r3] 800ac54: 2800 cmp r0, #0 800ac56: d1f7 bne.n 800ac48 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800ac58: 4d11 ldr r5, [pc, #68] @ (800aca0 ) __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ac5a: f103 0208 add.w r2, r3, #8 800ac5e: e852 2f00 ldrex r2, [r2] 800ac62: 402a ands r2, r5 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ac64: f103 0608 add.w r6, r3, #8 800ac68: e846 2000 strex r0, r2, [r6] 800ac6c: 2800 cmp r0, #0 800ac6e: d1f4 bne.n 800ac5a huart->RxState = HAL_UART_STATE_READY; 800ac70: 2220 movs r2, #32 huart->RxISR = NULL; 800ac72: 6760 str r0, [r4, #116] @ 0x74 huart->RxState = HAL_UART_STATE_READY; 800ac74: f8c4 208c str.w r2, [r4, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800ac78: 66e0 str r0, [r4, #108] @ 0x6c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ac7a: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800ac7e: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ac82: e843 2000 strex r0, r2, [r3] 800ac86: 2800 cmp r0, #0 800ac88: d1f7 bne.n 800ac7a huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800ac8a: 2302 movs r3, #2 HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 800ac8c: 4620 mov r0, r4 huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800ac8e: 6723 str r3, [r4, #112] @ 0x70 HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 800ac90: f7f9 f91e bl 8003ed0 } 800ac94: bd70 pop {r4, r5, r6, pc} 800ac96: bf00 nop 800ac98: 10000001 .word 0x10000001 800ac9c: 04000120 .word 0x04000120 800aca0: effffffe .word 0xeffffffe 800aca4: 0800a909 .word 0x0800a909 0800aca8 : /** * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) 800aca8: 6803 ldr r3, [r0, #0] 800acaa: b510 push {r4, lr} __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800acac: e853 2f00 ldrex r2, [r3] huart->RxXferCount--; if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800acb0: f422 7290 bic.w r2, r2, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800acb4: e843 2100 strex r1, r2, [r3] 800acb8: 2900 cmp r1, #0 800acba: d1f7 bne.n 800acac __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800acbc: f103 0208 add.w r2, r3, #8 800acc0: e852 2f00 ldrex r2, [r2] /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800acc4: f022 0201 bic.w r2, r2, #1 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800acc8: f103 0408 add.w r4, r3, #8 800accc: e844 2100 strex r1, r2, [r4] 800acd0: 2900 cmp r1, #0 800acd2: d1f3 bne.n 800acbc huart->RxISR = NULL; /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; if (!(IS_LPUART_INSTANCE(huart->Instance))) 800acd4: 4a1a ldr r2, [pc, #104] @ (800ad40 ) huart->RxState = HAL_UART_STATE_READY; 800acd6: 2420 movs r4, #32 huart->RxISR = NULL; 800acd8: 6741 str r1, [r0, #116] @ 0x74 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800acda: 4293 cmp r3, r2 huart->RxState = HAL_UART_STATE_READY; 800acdc: f8c0 408c str.w r4, [r0, #140] @ 0x8c huart->RxEventType = HAL_UART_RXEVENT_TC; 800ace0: 6701 str r1, [r0, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800ace2: d002 beq.n 800acea { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 800ace4: 685a ldr r2, [r3, #4] 800ace6: 0211 lsls r1, r2, #8 800ace8: d416 bmi.n 800ad18 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800acea: 6ec2 ldr r2, [r0, #108] @ 0x6c 800acec: 2a01 cmp r2, #1 800acee: d124 bne.n 800ad3a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800acf0: 2200 movs r2, #0 800acf2: 66c2 str r2, [r0, #108] @ 0x6c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800acf4: e853 2f00 ldrex r2, [r3] /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800acf8: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800acfc: e843 2100 strex r1, r2, [r3] 800ad00: 2900 cmp r1, #0 800ad02: d1f7 bne.n 800acf4 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 800ad04: 69da ldr r2, [r3, #28] 800ad06: 06d2 lsls r2, r2, #27 800ad08: d501 bpl.n 800ad0e { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800ad0a: 2210 movs r2, #16 800ad0c: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800ad0e: f8b0 105c ldrh.w r1, [r0, #92] @ 0x5c 800ad12: f7f9 f8dd bl 8003ed0 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 800ad16: bd10 pop {r4, pc} __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ad18: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800ad1c: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ad20: e843 2100 strex r1, r2, [r3] 800ad24: 2900 cmp r1, #0 800ad26: d0e0 beq.n 800acea __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ad28: e853 2f00 ldrex r2, [r3] 800ad2c: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ad30: e843 2100 strex r1, r2, [r3] 800ad34: 2900 cmp r1, #0 800ad36: d1ef bne.n 800ad18 800ad38: e7d7 b.n 800acea HAL_UART_RxCpltCallback(huart); 800ad3a: f7f9 f891 bl 8003e60 } 800ad3e: bd10 pop {r4, pc} 800ad40: 58000c00 .word 0x58000c00 0800ad44 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 800ad44: b410 push {r4} uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800ad46: f8d0 408c ldr.w r4, [r0, #140] @ 0x8c uint16_t uhMask = huart->Mask; 800ad4a: f8b0 1060 ldrh.w r1, [r0, #96] @ 0x60 if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800ad4e: 2c22 cmp r4, #34 @ 0x22 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800ad50: 6802 ldr r2, [r0, #0] if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800ad52: d006 beq.n 800ad62 } } else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800ad54: 6993 ldr r3, [r2, #24] 800ad56: f043 0308 orr.w r3, r3, #8 800ad5a: 6193 str r3, [r2, #24] } } 800ad5c: f85d 4b04 ldr.w r4, [sp], #4 800ad60: 4770 bx lr uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800ad62: 6a52 ldr r2, [r2, #36] @ 0x24 *tmp = (uint16_t)(uhdata & uhMask); 800ad64: 6d84 ldr r4, [r0, #88] @ 0x58 800ad66: 4011 ands r1, r2 800ad68: f824 1b02 strh.w r1, [r4], #2 huart->RxXferCount--; 800ad6c: f8b0 205e ldrh.w r2, [r0, #94] @ 0x5e huart->pRxBuffPtr += 2U; 800ad70: 6584 str r4, [r0, #88] @ 0x58 huart->RxXferCount--; 800ad72: 3a01 subs r2, #1 800ad74: b292 uxth r2, r2 800ad76: f8a0 205e strh.w r2, [r0, #94] @ 0x5e if (huart->RxXferCount == 0U) 800ad7a: f8b0 305e ldrh.w r3, [r0, #94] @ 0x5e 800ad7e: b29b uxth r3, r3 800ad80: 2b00 cmp r3, #0 800ad82: d1eb bne.n 800ad5c } 800ad84: f85d 4b04 ldr.w r4, [sp], #4 800ad88: f7ff bf8e b.w 800aca8 0800ad8c : if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800ad8c: f8d0 108c ldr.w r1, [r0, #140] @ 0x8c uint16_t uhMask = huart->Mask; 800ad90: f8b0 c060 ldrh.w ip, [r0, #96] @ 0x60 if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800ad94: 2922 cmp r1, #34 @ 0x22 uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800ad96: 6802 ldr r2, [r0, #0] if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800ad98: d004 beq.n 800ada4 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800ad9a: 6993 ldr r3, [r2, #24] 800ad9c: f043 0308 orr.w r3, r3, #8 800ada0: 6193 str r3, [r2, #24] } 800ada2: 4770 bx lr uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800ada4: 6a52 ldr r2, [r2, #36] @ 0x24 *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 800ada6: 6d81 ldr r1, [r0, #88] @ 0x58 800ada8: ea02 020c and.w r2, r2, ip 800adac: 700a strb r2, [r1, #0] huart->RxXferCount--; 800adae: f8b0 205e ldrh.w r2, [r0, #94] @ 0x5e huart->pRxBuffPtr++; 800adb2: 6d81 ldr r1, [r0, #88] @ 0x58 huart->RxXferCount--; 800adb4: 3a01 subs r2, #1 huart->pRxBuffPtr++; 800adb6: 3101 adds r1, #1 huart->RxXferCount--; 800adb8: b292 uxth r2, r2 huart->pRxBuffPtr++; 800adba: 6581 str r1, [r0, #88] @ 0x58 huart->RxXferCount--; 800adbc: f8a0 205e strh.w r2, [r0, #94] @ 0x5e if (huart->RxXferCount == 0U) 800adc0: f8b0 305e ldrh.w r3, [r0, #94] @ 0x5e 800adc4: b29b uxth r3, r3 800adc6: 2b00 cmp r3, #0 800adc8: d1eb bne.n 800ada2 800adca: f7ff bf6d b.w 800aca8 800adce: bf00 nop 0800add0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 800add0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} uint16_t uhMask = huart->Mask; uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 800add4: 6802 ldr r2, [r0, #0] { 800add6: 4604 mov r4, r0 uint16_t uhMask = huart->Mask; 800add8: f8b0 a060 ldrh.w sl, [r0, #96] @ 0x60 uint32_t isrflags = READ_REG(huart->Instance->ISR); 800addc: 69d0 ldr r0, [r2, #28] uint32_t cr1its = READ_REG(huart->Instance->CR1); 800adde: 6816 ldr r6, [r2, #0] uint32_t cr3its = READ_REG(huart->Instance->CR3); 800ade0: 6895 ldr r5, [r2, #8] /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800ade2: f8d4 108c ldr.w r1, [r4, #140] @ 0x8c 800ade6: 2922 cmp r1, #34 @ 0x22 800ade8: d006 beq.n 800adf8 800adea: 4613 mov r3, r2 } } else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800adec: 6992 ldr r2, [r2, #24] 800adee: f042 0208 orr.w r2, r2, #8 800adf2: 619a str r2, [r3, #24] } } 800adf4: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800adf8: f8b4 3068 ldrh.w r3, [r4, #104] @ 0x68 800adfc: 2b00 cmp r3, #0 800adfe: f000 80d4 beq.w 800afaa 800ae02: 0680 lsls r0, r0, #26 800ae04: f140 8088 bpl.w 800af18 if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800ae08: f406 7680 and.w r6, r6, #256 @ 0x100 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ae0c: f005 0501 and.w r5, r5, #1 *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 800ae10: fa5f fa8a uxtb.w sl, sl huart->ErrorCode = HAL_UART_ERROR_NONE; 800ae14: f04f 0800 mov.w r8, #0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800ae18: f8df 919c ldr.w r9, [pc, #412] @ 800afb8 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800ae1c: 4f64 ldr r7, [pc, #400] @ (800afb0 ) uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800ae1e: 6a52 ldr r2, [r2, #36] @ 0x24 *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 800ae20: 6da3 ldr r3, [r4, #88] @ 0x58 800ae22: ea0a 0202 and.w r2, sl, r2 800ae26: 701a strb r2, [r3, #0] huart->RxXferCount--; 800ae28: f8b4 105e ldrh.w r1, [r4, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 800ae2c: 6823 ldr r3, [r4, #0] huart->RxXferCount--; 800ae2e: 3901 subs r1, #1 huart->pRxBuffPtr++; 800ae30: 6da2 ldr r2, [r4, #88] @ 0x58 huart->RxXferCount--; 800ae32: b289 uxth r1, r1 huart->pRxBuffPtr++; 800ae34: 3201 adds r2, #1 huart->RxXferCount--; 800ae36: f8a4 105e strh.w r1, [r4, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 800ae3a: f8d3 b01c ldr.w fp, [r3, #28] huart->pRxBuffPtr++; 800ae3e: 65a2 str r2, [r4, #88] @ 0x58 if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 800ae40: f01b 0f07 tst.w fp, #7 800ae44: d01d beq.n 800ae82 if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800ae46: f01b 0f01 tst.w fp, #1 800ae4a: d008 beq.n 800ae5e 800ae4c: b13e cbz r6, 800ae5e __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 800ae4e: 2201 movs r2, #1 800ae50: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 800ae52: f8d4 2090 ldr.w r2, [r4, #144] @ 0x90 800ae56: f042 0201 orr.w r2, r2, #1 800ae5a: f8c4 2090 str.w r2, [r4, #144] @ 0x90 if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ae5e: f01b 0f02 tst.w fp, #2 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ae62: f00b 0204 and.w r2, fp, #4 if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ae66: d015 beq.n 800ae94 800ae68: b145 cbz r5, 800ae7c __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 800ae6a: 2102 movs r1, #2 800ae6c: 6219 str r1, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 800ae6e: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90 800ae72: f041 0104 orr.w r1, r1, #4 800ae76: f8c4 1090 str.w r1, [r4, #144] @ 0x90 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ae7a: b97a cbnz r2, 800ae9c if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800ae7c: f8d4 3090 ldr.w r3, [r4, #144] @ 0x90 800ae80: b9c3 cbnz r3, 800aeb4 if (huart->RxXferCount == 0U) 800ae82: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e 800ae86: b29b uxth r3, r3 800ae88: b1f3 cbz r3, 800aec8 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800ae8a: f01b 0f20 tst.w fp, #32 800ae8e: d043 beq.n 800af18 uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800ae90: 6822 ldr r2, [r4, #0] 800ae92: e7c4 b.n 800ae1e if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ae94: 2a00 cmp r2, #0 800ae96: d0f1 beq.n 800ae7c 800ae98: 2d00 cmp r5, #0 800ae9a: d0ef beq.n 800ae7c __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 800ae9c: 2204 movs r2, #4 800ae9e: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 800aea0: f8d4 3090 ldr.w r3, [r4, #144] @ 0x90 800aea4: f043 0302 orr.w r3, r3, #2 800aea8: f8c4 3090 str.w r3, [r4, #144] @ 0x90 if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800aeac: f8d4 3090 ldr.w r3, [r4, #144] @ 0x90 800aeb0: 2b00 cmp r3, #0 800aeb2: d0e6 beq.n 800ae82 HAL_UART_ErrorCallback(huart); 800aeb4: 4620 mov r0, r4 800aeb6: f7ff fd25 bl 800a904 huart->ErrorCode = HAL_UART_ERROR_NONE; 800aeba: f8c4 8090 str.w r8, [r4, #144] @ 0x90 if (huart->RxXferCount == 0U) 800aebe: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e 800aec2: b29b uxth r3, r3 800aec4: 2b00 cmp r3, #0 800aec6: d1e0 bne.n 800ae8a 800aec8: 6823 ldr r3, [r4, #0] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800aeca: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800aece: f422 7280 bic.w r2, r2, #256 @ 0x100 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800aed2: e843 2100 strex r1, r2, [r3] 800aed6: 2900 cmp r1, #0 800aed8: d1f7 bne.n 800aeca __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800aeda: f103 0208 add.w r2, r3, #8 800aede: e852 2f00 ldrex r2, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800aee2: ea02 0209 and.w r2, r2, r9 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800aee6: f103 0008 add.w r0, r3, #8 800aeea: e840 2100 strex r1, r2, [r0] 800aeee: 2900 cmp r1, #0 800aef0: d1f3 bne.n 800aeda huart->RxState = HAL_UART_STATE_READY; 800aef2: 2220 movs r2, #32 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800aef4: 42bb cmp r3, r7 huart->RxISR = NULL; 800aef6: 6761 str r1, [r4, #116] @ 0x74 huart->RxState = HAL_UART_STATE_READY; 800aef8: f8c4 208c str.w r2, [r4, #140] @ 0x8c huart->RxEventType = HAL_UART_RXEVENT_TC; 800aefc: 6721 str r1, [r4, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800aefe: d002 beq.n 800af06 if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 800af00: 685a ldr r2, [r3, #4] 800af02: 0211 lsls r1, r2, #8 800af04: d42b bmi.n 800af5e if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800af06: 6ee2 ldr r2, [r4, #108] @ 0x6c 800af08: 2a01 cmp r2, #1 800af0a: d039 beq.n 800af80 HAL_UART_RxCpltCallback(huart); 800af0c: 4620 mov r0, r4 800af0e: f7f8 ffa7 bl 8003e60 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800af12: f01b 0f20 tst.w fp, #32 800af16: d1bb bne.n 800ae90 rxdatacount = huart->RxXferCount; 800af18: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e 800af1c: b29b uxth r3, r3 if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 800af1e: 2b00 cmp r3, #0 800af20: f43f af68 beq.w 800adf4 800af24: f8b4 2068 ldrh.w r2, [r4, #104] @ 0x68 800af28: 429a cmp r2, r3 800af2a: f67f af63 bls.w 800adf4 800af2e: 6823 ldr r3, [r4, #0] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800af30: f103 0208 add.w r2, r3, #8 800af34: e852 2f00 ldrex r2, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 800af38: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800af3c: f103 0008 add.w r0, r3, #8 800af40: e840 2100 strex r1, r2, [r0] 800af44: 2900 cmp r1, #0 800af46: d1f3 bne.n 800af30 huart->RxISR = UART_RxISR_8BIT; 800af48: 4a1a ldr r2, [pc, #104] @ (800afb4 ) 800af4a: 6762 str r2, [r4, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800af4c: e853 2f00 ldrex r2, [r3] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 800af50: f042 0220 orr.w r2, r2, #32 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800af54: e843 2100 strex r1, r2, [r3] 800af58: 2900 cmp r1, #0 800af5a: d1f7 bne.n 800af4c 800af5c: e74a b.n 800adf4 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800af5e: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800af62: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800af66: e843 2100 strex r1, r2, [r3] 800af6a: 2900 cmp r1, #0 800af6c: d0cb beq.n 800af06 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800af6e: e853 2f00 ldrex r2, [r3] 800af72: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800af76: e843 2100 strex r1, r2, [r3] 800af7a: 2900 cmp r1, #0 800af7c: d1ef bne.n 800af5e 800af7e: e7c2 b.n 800af06 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800af80: 2200 movs r2, #0 800af82: 66e2 str r2, [r4, #108] @ 0x6c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800af84: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800af88: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800af8c: e843 2100 strex r1, r2, [r3] 800af90: 2900 cmp r1, #0 800af92: d1f7 bne.n 800af84 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 800af94: 69da ldr r2, [r3, #28] 800af96: 06d2 lsls r2, r2, #27 800af98: d501 bpl.n 800af9e __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800af9a: 2210 movs r2, #16 800af9c: 621a str r2, [r3, #32] HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800af9e: f8b4 105c ldrh.w r1, [r4, #92] @ 0x5c 800afa2: 4620 mov r0, r4 800afa4: f7f8 ff94 bl 8003ed0 800afa8: e76f b.n 800ae8a rxdatacount = huart->RxXferCount; 800afaa: f8b4 305e ldrh.w r3, [r4, #94] @ 0x5e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 800afae: e721 b.n 800adf4 800afb0: 58000c00 .word 0x58000c00 800afb4: 0800ad8d .word 0x0800ad8d 800afb8: effffffe .word 0xeffffffe 0800afbc : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 800afbc: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 800afc0: 6803 ldr r3, [r0, #0] uint16_t uhMask = huart->Mask; 800afc2: f8b0 a060 ldrh.w sl, [r0, #96] @ 0x60 uint32_t isrflags = READ_REG(huart->Instance->ISR); 800afc6: 69d9 ldr r1, [r3, #28] uint32_t cr1its = READ_REG(huart->Instance->CR1); 800afc8: 681e ldr r6, [r3, #0] uint32_t cr3its = READ_REG(huart->Instance->CR3); 800afca: 689d ldr r5, [r3, #8] /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800afcc: f8d0 208c ldr.w r2, [r0, #140] @ 0x8c 800afd0: 2a22 cmp r2, #34 @ 0x22 800afd2: d005 beq.n 800afe0 } } else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800afd4: 699a ldr r2, [r3, #24] 800afd6: f042 0208 orr.w r2, r2, #8 800afda: 619a str r2, [r3, #24] } } 800afdc: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800afe0: f8b0 2068 ldrh.w r2, [r0, #104] @ 0x68 800afe4: 4683 mov fp, r0 800afe6: 2a00 cmp r2, #0 800afe8: f000 80d4 beq.w 800b194 800afec: 0688 lsls r0, r1, #26 800afee: f140 8085 bpl.w 800b0fc if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800aff2: f406 7680 and.w r6, r6, #256 @ 0x100 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800aff6: f005 0501 and.w r5, r5, #1 huart->ErrorCode = HAL_UART_ERROR_NONE; 800affa: f04f 0800 mov.w r8, #0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800affe: f8df 91a4 ldr.w r9, [pc, #420] @ 800b1a4 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800b002: 4f66 ldr r7, [pc, #408] @ (800b19c ) uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800b004: 6a5a ldr r2, [r3, #36] @ 0x24 *tmp = (uint16_t)(uhdata & uhMask); 800b006: f8db 1058 ldr.w r1, [fp, #88] @ 0x58 800b00a: ea0a 0202 and.w r2, sl, r2 800b00e: f821 2b02 strh.w r2, [r1], #2 huart->RxXferCount--; 800b012: f8bb 205e ldrh.w r2, [fp, #94] @ 0x5e huart->pRxBuffPtr += 2U; 800b016: f8cb 1058 str.w r1, [fp, #88] @ 0x58 huart->RxXferCount--; 800b01a: 3a01 subs r2, #1 800b01c: b292 uxth r2, r2 800b01e: f8ab 205e strh.w r2, [fp, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 800b022: 69dc ldr r4, [r3, #28] if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 800b024: 0761 lsls r1, r4, #29 800b026: d01b beq.n 800b060 if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800b028: 07e2 lsls r2, r4, #31 800b02a: d508 bpl.n 800b03e 800b02c: b13e cbz r6, 800b03e __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 800b02e: 2201 movs r2, #1 800b030: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 800b032: f8db 2090 ldr.w r2, [fp, #144] @ 0x90 800b036: f042 0201 orr.w r2, r2, #1 800b03a: f8cb 2090 str.w r2, [fp, #144] @ 0x90 if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800b03e: 07a0 lsls r0, r4, #30 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800b040: f004 0204 and.w r2, r4, #4 if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800b044: d515 bpl.n 800b072 800b046: b145 cbz r5, 800b05a __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 800b048: 2102 movs r1, #2 800b04a: 6219 str r1, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 800b04c: f8db 1090 ldr.w r1, [fp, #144] @ 0x90 800b050: f041 0104 orr.w r1, r1, #4 800b054: f8cb 1090 str.w r1, [fp, #144] @ 0x90 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800b058: b97a cbnz r2, 800b07a if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800b05a: f8db 3090 ldr.w r3, [fp, #144] @ 0x90 800b05e: b9c3 cbnz r3, 800b092 if (huart->RxXferCount == 0U) 800b060: f8bb 305e ldrh.w r3, [fp, #94] @ 0x5e 800b064: b29b uxth r3, r3 800b066: b1f3 cbz r3, 800b0a6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800b068: 06a3 lsls r3, r4, #26 800b06a: d547 bpl.n 800b0fc uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800b06c: f8db 3000 ldr.w r3, [fp] 800b070: e7c8 b.n 800b004 if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800b072: 2a00 cmp r2, #0 800b074: d0f1 beq.n 800b05a 800b076: 2d00 cmp r5, #0 800b078: d0ef beq.n 800b05a __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 800b07a: 2204 movs r2, #4 800b07c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 800b07e: f8db 3090 ldr.w r3, [fp, #144] @ 0x90 800b082: f043 0302 orr.w r3, r3, #2 800b086: f8cb 3090 str.w r3, [fp, #144] @ 0x90 if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800b08a: f8db 3090 ldr.w r3, [fp, #144] @ 0x90 800b08e: 2b00 cmp r3, #0 800b090: d0e6 beq.n 800b060 HAL_UART_ErrorCallback(huart); 800b092: 4658 mov r0, fp 800b094: f7ff fc36 bl 800a904 huart->ErrorCode = HAL_UART_ERROR_NONE; 800b098: f8cb 8090 str.w r8, [fp, #144] @ 0x90 if (huart->RxXferCount == 0U) 800b09c: f8bb 305e ldrh.w r3, [fp, #94] @ 0x5e 800b0a0: b29b uxth r3, r3 800b0a2: 2b00 cmp r3, #0 800b0a4: d1e0 bne.n 800b068 800b0a6: f8db 3000 ldr.w r3, [fp] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b0aa: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800b0ae: f422 7280 bic.w r2, r2, #256 @ 0x100 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b0b2: e843 2100 strex r1, r2, [r3] 800b0b6: 2900 cmp r1, #0 800b0b8: d1f7 bne.n 800b0aa __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b0ba: f103 0208 add.w r2, r3, #8 800b0be: e852 2f00 ldrex r2, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800b0c2: ea02 0209 and.w r2, r2, r9 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b0c6: f103 0008 add.w r0, r3, #8 800b0ca: e840 2100 strex r1, r2, [r0] 800b0ce: 2900 cmp r1, #0 800b0d0: d1f3 bne.n 800b0ba huart->RxState = HAL_UART_STATE_READY; 800b0d2: 2220 movs r2, #32 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800b0d4: 42bb cmp r3, r7 huart->RxISR = NULL; 800b0d6: f8cb 1074 str.w r1, [fp, #116] @ 0x74 huart->RxState = HAL_UART_STATE_READY; 800b0da: f8cb 208c str.w r2, [fp, #140] @ 0x8c huart->RxEventType = HAL_UART_RXEVENT_TC; 800b0de: f8cb 1070 str.w r1, [fp, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800b0e2: d002 beq.n 800b0ea if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 800b0e4: 685a ldr r2, [r3, #4] 800b0e6: 0211 lsls r1, r2, #8 800b0e8: d42d bmi.n 800b146 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800b0ea: f8db 206c ldr.w r2, [fp, #108] @ 0x6c 800b0ee: 2a01 cmp r2, #1 800b0f0: d03a beq.n 800b168 HAL_UART_RxCpltCallback(huart); 800b0f2: 4658 mov r0, fp 800b0f4: f7f8 feb4 bl 8003e60 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800b0f8: 06a3 lsls r3, r4, #26 800b0fa: d4b7 bmi.n 800b06c rxdatacount = huart->RxXferCount; 800b0fc: f8bb 305e ldrh.w r3, [fp, #94] @ 0x5e 800b100: b29b uxth r3, r3 if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 800b102: 2b00 cmp r3, #0 800b104: f43f af6a beq.w 800afdc 800b108: f8bb 2068 ldrh.w r2, [fp, #104] @ 0x68 800b10c: 429a cmp r2, r3 800b10e: f67f af65 bls.w 800afdc 800b112: f8db 3000 ldr.w r3, [fp] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b116: f103 0208 add.w r2, r3, #8 800b11a: e852 2f00 ldrex r2, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 800b11e: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b122: f103 0008 add.w r0, r3, #8 800b126: e840 2100 strex r1, r2, [r0] 800b12a: 2900 cmp r1, #0 800b12c: d1f3 bne.n 800b116 huart->RxISR = UART_RxISR_16BIT; 800b12e: 4a1c ldr r2, [pc, #112] @ (800b1a0 ) 800b130: f8cb 2074 str.w r2, [fp, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b134: e853 2f00 ldrex r2, [r3] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 800b138: f042 0220 orr.w r2, r2, #32 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b13c: e843 2100 strex r1, r2, [r3] 800b140: 2900 cmp r1, #0 800b142: d1f7 bne.n 800b134 800b144: e74a b.n 800afdc __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b146: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800b14a: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b14e: e843 2100 strex r1, r2, [r3] 800b152: 2900 cmp r1, #0 800b154: d0c9 beq.n 800b0ea __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b156: e853 2f00 ldrex r2, [r3] 800b15a: f022 6280 bic.w r2, r2, #67108864 @ 0x4000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b15e: e843 2100 strex r1, r2, [r3] 800b162: 2900 cmp r1, #0 800b164: d1ef bne.n 800b146 800b166: e7c0 b.n 800b0ea huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b168: 2200 movs r2, #0 800b16a: f8cb 206c str.w r2, [fp, #108] @ 0x6c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b16e: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800b172: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b176: e843 2100 strex r1, r2, [r3] 800b17a: 2900 cmp r1, #0 800b17c: d1f7 bne.n 800b16e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 800b17e: 69da ldr r2, [r3, #28] 800b180: 06d2 lsls r2, r2, #27 800b182: d501 bpl.n 800b188 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800b184: 2210 movs r2, #16 800b186: 621a str r2, [r3, #32] HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800b188: f8bb 105c ldrh.w r1, [fp, #92] @ 0x5c 800b18c: 4658 mov r0, fp 800b18e: f7f8 fe9f bl 8003ed0 800b192: e769 b.n 800b068 rxdatacount = huart->RxXferCount; 800b194: f8b0 305e ldrh.w r3, [r0, #94] @ 0x5e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 800b198: e720 b.n 800afdc 800b19a: bf00 nop 800b19c: 58000c00 .word 0x58000c00 800b1a0: 0800ad45 .word 0x0800ad45 800b1a4: effffffe .word 0xeffffffe 0800b1a8 : tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800b1a8: 6901 ldr r1, [r0, #16] 800b1aa: 6882 ldr r2, [r0, #8] if (UART_INSTANCE_LOWPOWER(huart)) 800b1ac: 6803 ldr r3, [r0, #0] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800b1ae: 430a orrs r2, r1 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800b1b0: 49a2 ldr r1, [pc, #648] @ (800b43c ) { 800b1b2: b570 push {r4, r5, r6, lr} tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800b1b4: 6945 ldr r5, [r0, #20] { 800b1b6: 4604 mov r4, r0 tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800b1b8: 69c0 ldr r0, [r0, #28] { 800b1ba: b086 sub sp, #24 tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800b1bc: 432a orrs r2, r5 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800b1be: 681d ldr r5, [r3, #0] tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800b1c0: 4302 orrs r2, r0 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800b1c2: 4029 ands r1, r5 MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800b1c4: 6a65 ldr r5, [r4, #36] @ 0x24 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800b1c6: 430a orrs r2, r1 MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800b1c8: 68e1 ldr r1, [r4, #12] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 800b1ca: 601a str r2, [r3, #0] MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800b1cc: 685a ldr r2, [r3, #4] 800b1ce: f422 5240 bic.w r2, r2, #12288 @ 0x3000 800b1d2: 430a orrs r2, r1 tmpreg = (uint32_t)huart->Init.HwFlowCtl; 800b1d4: 69a1 ldr r1, [r4, #24] MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 800b1d6: 605a str r2, [r3, #4] if (!(UART_INSTANCE_LOWPOWER(huart))) 800b1d8: 4a99 ldr r2, [pc, #612] @ (800b440 ) 800b1da: 4293 cmp r3, r2 800b1dc: f000 8118 beq.w 800b410 tmpreg |= huart->Init.OneBitSampling; 800b1e0: 6a22 ldr r2, [r4, #32] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 800b1e2: 689e ldr r6, [r3, #8] tmpreg |= huart->Init.OneBitSampling; 800b1e4: 4311 orrs r1, r2 MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 800b1e6: 4a97 ldr r2, [pc, #604] @ (800b444 ) 800b1e8: 4032 ands r2, r6 800b1ea: 4311 orrs r1, r2 800b1ec: 6099 str r1, [r3, #8] MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800b1ee: 6ada ldr r2, [r3, #44] @ 0x2c 800b1f0: f022 020f bic.w r2, r2, #15 800b1f4: 432a orrs r2, r5 800b1f6: 62da str r2, [r3, #44] @ 0x2c UART_GETCLOCKSOURCE(huart, clocksource); 800b1f8: 4a93 ldr r2, [pc, #588] @ (800b448 ) 800b1fa: 4293 cmp r3, r2 800b1fc: d028 beq.n 800b250 800b1fe: 4a93 ldr r2, [pc, #588] @ (800b44c ) 800b200: 4293 cmp r3, r2 800b202: d01a beq.n 800b23a 800b204: 4a92 ldr r2, [pc, #584] @ (800b450 ) 800b206: 4293 cmp r3, r2 800b208: d017 beq.n 800b23a 800b20a: 4a92 ldr r2, [pc, #584] @ (800b454 ) 800b20c: 4293 cmp r3, r2 800b20e: d014 beq.n 800b23a 800b210: 4a91 ldr r2, [pc, #580] @ (800b458 ) 800b212: 4293 cmp r3, r2 800b214: d011 beq.n 800b23a 800b216: 4a91 ldr r2, [pc, #580] @ (800b45c ) 800b218: 4293 cmp r3, r2 800b21a: d019 beq.n 800b250 800b21c: 4a90 ldr r2, [pc, #576] @ (800b460 ) 800b21e: 4293 cmp r3, r2 800b220: d00b beq.n 800b23a 800b222: 4a90 ldr r2, [pc, #576] @ (800b464 ) 800b224: 4293 cmp r3, r2 800b226: d008 beq.n 800b23a ret = HAL_ERROR; 800b228: 2001 movs r0, #1 huart->RxISR = NULL; 800b22a: 2300 movs r3, #0 huart->NbRxDataToProcess = 1; 800b22c: f04f 1201 mov.w r2, #65537 @ 0x10001 huart->RxISR = NULL; 800b230: 6763 str r3, [r4, #116] @ 0x74 huart->NbRxDataToProcess = 1; 800b232: 66a2 str r2, [r4, #104] @ 0x68 huart->TxISR = NULL; 800b234: 67a3 str r3, [r4, #120] @ 0x78 } 800b236: b006 add sp, #24 800b238: bd70 pop {r4, r5, r6, pc} UART_GETCLOCKSOURCE(huart, clocksource); 800b23a: 4b8b ldr r3, [pc, #556] @ (800b468 ) 800b23c: 6d5b ldr r3, [r3, #84] @ 0x54 800b23e: f003 0307 and.w r3, r3, #7 800b242: 2b05 cmp r3, #5 800b244: d8f0 bhi.n 800b228 800b246: e8df f003 tbb [pc, r3] 800b24a: 5f9d .short 0x5f9d 800b24c: 977e7169 .word 0x977e7169 800b250: 4b85 ldr r3, [pc, #532] @ (800b468 ) 800b252: 6d5b ldr r3, [r3, #84] @ 0x54 800b254: f003 0338 and.w r3, r3, #56 @ 0x38 800b258: 2b28 cmp r3, #40 @ 0x28 800b25a: d8e5 bhi.n 800b228 800b25c: a201 add r2, pc, #4 @ (adr r2, 800b264 ) 800b25e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800b262: bf00 nop 800b264: 0800b3df .word 0x0800b3df 800b268: 0800b229 .word 0x0800b229 800b26c: 0800b229 .word 0x0800b229 800b270: 0800b229 .word 0x0800b229 800b274: 0800b229 .word 0x0800b229 800b278: 0800b229 .word 0x0800b229 800b27c: 0800b229 .word 0x0800b229 800b280: 0800b229 .word 0x0800b229 800b284: 0800b309 .word 0x0800b309 800b288: 0800b229 .word 0x0800b229 800b28c: 0800b229 .word 0x0800b229 800b290: 0800b229 .word 0x0800b229 800b294: 0800b229 .word 0x0800b229 800b298: 0800b229 .word 0x0800b229 800b29c: 0800b229 .word 0x0800b229 800b2a0: 0800b229 .word 0x0800b229 800b2a4: 0800b31d .word 0x0800b31d 800b2a8: 0800b229 .word 0x0800b229 800b2ac: 0800b229 .word 0x0800b229 800b2b0: 0800b229 .word 0x0800b229 800b2b4: 0800b229 .word 0x0800b229 800b2b8: 0800b229 .word 0x0800b229 800b2bc: 0800b229 .word 0x0800b229 800b2c0: 0800b229 .word 0x0800b229 800b2c4: 0800b32d .word 0x0800b32d 800b2c8: 0800b229 .word 0x0800b229 800b2cc: 0800b229 .word 0x0800b229 800b2d0: 0800b229 .word 0x0800b229 800b2d4: 0800b229 .word 0x0800b229 800b2d8: 0800b229 .word 0x0800b229 800b2dc: 0800b229 .word 0x0800b229 800b2e0: 0800b229 .word 0x0800b229 800b2e4: 0800b347 .word 0x0800b347 800b2e8: 0800b229 .word 0x0800b229 800b2ec: 0800b229 .word 0x0800b229 800b2f0: 0800b229 .word 0x0800b229 800b2f4: 0800b229 .word 0x0800b229 800b2f8: 0800b229 .word 0x0800b229 800b2fc: 0800b229 .word 0x0800b229 800b300: 0800b229 .word 0x0800b229 800b304: 0800b379 .word 0x0800b379 else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800b308: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 800b30c: d040 beq.n 800b390 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800b30e: 4668 mov r0, sp 800b310: f7fd fec6 bl 80090a0 pclk = pll2_clocks.PLL2_Q_Frequency; 800b314: 9801 ldr r0, [sp, #4] if (pclk != 0U) 800b316: b368 cbz r0, 800b374 usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800b318: 6a65 ldr r5, [r4, #36] @ 0x24 800b31a: e018 b.n 800b34e else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800b31c: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 800b320: d06e beq.n 800b400 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800b322: a803 add r0, sp, #12 800b324: f7fd ff56 bl 80091d4 pclk = pll3_clocks.PLL3_Q_Frequency; 800b328: 9804 ldr r0, [sp, #16] break; 800b32a: e7f4 b.n 800b316 else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800b32c: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 800b330: d05b beq.n 800b3ea if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800b332: 4b4d ldr r3, [pc, #308] @ (800b468 ) 800b334: 681a ldr r2, [r3, #0] 800b336: 0692 lsls r2, r2, #26 800b338: d54c bpl.n 800b3d4 pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800b33a: 681b ldr r3, [r3, #0] 800b33c: 484b ldr r0, [pc, #300] @ (800b46c ) 800b33e: f3c3 03c1 ubfx r3, r3, #3, #2 800b342: 40d8 lsrs r0, r3 if (pclk != 0U) 800b344: e003 b.n 800b34e else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800b346: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 pclk = (uint32_t) CSI_VALUE; 800b34a: 4849 ldr r0, [pc, #292] @ (800b470 ) else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800b34c: d027 beq.n 800b39e usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800b34e: 4a49 ldr r2, [pc, #292] @ (800b474 ) 800b350: 6863 ldr r3, [r4, #4] 800b352: f832 1015 ldrh.w r1, [r2, r5, lsl #1] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800b356: f64f 72ef movw r2, #65519 @ 0xffef usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800b35a: fbb0 f0f1 udiv r0, r0, r1 800b35e: eb00 0053 add.w r0, r0, r3, lsr #1 800b362: fbb0 f0f3 udiv r0, r0, r3 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800b366: f1a0 0310 sub.w r3, r0, #16 800b36a: 4293 cmp r3, r2 800b36c: f63f af5c bhi.w 800b228 huart->Instance->BRR = usartdiv; 800b370: 6823 ldr r3, [r4, #0] 800b372: 60d8 str r0, [r3, #12] pclk = (uint32_t) HSI_VALUE; 800b374: 2000 movs r0, #0 800b376: e758 b.n 800b22a else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800b378: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 800b37c: d00f beq.n 800b39e pclk = (uint32_t) LSE_VALUE; 800b37e: f44f 4000 mov.w r0, #32768 @ 0x8000 800b382: e7e4 b.n 800b34e else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800b384: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 800b388: d026 beq.n 800b3d8 pclk = HAL_RCC_GetPCLK1Freq(); 800b38a: f7fc fd89 bl 8007ea0 break; 800b38e: e7c2 b.n 800b316 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800b390: 4668 mov r0, sp 800b392: f7fd fe85 bl 80090a0 pclk = pll2_clocks.PLL2_Q_Frequency; 800b396: 9801 ldr r0, [sp, #4] if (pclk != 0U) 800b398: 2800 cmp r0, #0 800b39a: d0eb beq.n 800b374 usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800b39c: 6a65 ldr r5, [r4, #36] @ 0x24 800b39e: 4b35 ldr r3, [pc, #212] @ (800b474 ) 800b3a0: 6862 ldr r2, [r4, #4] 800b3a2: f833 1015 ldrh.w r1, [r3, r5, lsl #1] 800b3a6: 0853 lsrs r3, r2, #1 800b3a8: fbb0 f0f1 udiv r0, r0, r1 800b3ac: eb03 0340 add.w r3, r3, r0, lsl #1 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800b3b0: f64f 71ef movw r1, #65519 @ 0xffef usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800b3b4: fbb3 f3f2 udiv r3, r3, r2 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 800b3b8: f1a3 0210 sub.w r2, r3, #16 800b3bc: 428a cmp r2, r1 800b3be: f63f af33 bhi.w 800b228 brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 800b3c2: f023 020f bic.w r2, r3, #15 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 800b3c6: f3c3 0342 ubfx r3, r3, #1, #3 huart->Instance->BRR = brrtemp; 800b3ca: 6821 ldr r1, [r4, #0] brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 800b3cc: b292 uxth r2, r2 huart->Instance->BRR = brrtemp; 800b3ce: 4313 orrs r3, r2 800b3d0: 60cb str r3, [r1, #12] 800b3d2: e7cf b.n 800b374 pclk = (uint32_t) HSI_VALUE; 800b3d4: 4825 ldr r0, [pc, #148] @ (800b46c ) 800b3d6: e7ba b.n 800b34e pclk = HAL_RCC_GetPCLK1Freq(); 800b3d8: f7fc fd62 bl 8007ea0 break; 800b3dc: e7dc b.n 800b398 else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800b3de: f5b0 4f00 cmp.w r0, #32768 @ 0x8000 800b3e2: d012 beq.n 800b40a pclk = HAL_RCC_GetPCLK2Freq(); 800b3e4: f7fc fda4 bl 8007f30 break; 800b3e8: e795 b.n 800b316 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800b3ea: 4b1f ldr r3, [pc, #124] @ (800b468 ) 800b3ec: 681a ldr r2, [r3, #0] 800b3ee: 0691 lsls r1, r2, #26 800b3f0: f140 808a bpl.w 800b508 pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800b3f4: 681b ldr r3, [r3, #0] 800b3f6: 481d ldr r0, [pc, #116] @ (800b46c ) 800b3f8: f3c3 03c1 ubfx r3, r3, #3, #2 800b3fc: 40d8 lsrs r0, r3 if (pclk != 0U) 800b3fe: e7ce b.n 800b39e HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800b400: a803 add r0, sp, #12 800b402: f7fd fee7 bl 80091d4 pclk = pll3_clocks.PLL3_Q_Frequency; 800b406: 9804 ldr r0, [sp, #16] break; 800b408: e7c6 b.n 800b398 pclk = HAL_RCC_GetPCLK2Freq(); 800b40a: f7fc fd91 bl 8007f30 break; 800b40e: e7c3 b.n 800b398 MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 800b410: 6898 ldr r0, [r3, #8] 800b412: 4a0c ldr r2, [pc, #48] @ (800b444 ) 800b414: 4002 ands r2, r0 800b416: 430a orrs r2, r1 UART_GETCLOCKSOURCE(huart, clocksource); 800b418: 4913 ldr r1, [pc, #76] @ (800b468 ) MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 800b41a: 609a str r2, [r3, #8] MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800b41c: 6ada ldr r2, [r3, #44] @ 0x2c 800b41e: f022 020f bic.w r2, r2, #15 800b422: 432a orrs r2, r5 800b424: 62da str r2, [r3, #44] @ 0x2c UART_GETCLOCKSOURCE(huart, clocksource); 800b426: 6d8b ldr r3, [r1, #88] @ 0x58 800b428: f003 0307 and.w r3, r3, #7 800b42c: 2b05 cmp r3, #5 800b42e: f63f aefb bhi.w 800b228 800b432: e8df f003 tbb [pc, r3] 800b436: 565b .short 0x565b 800b438: 5e61214d .word 0x5e61214d 800b43c: cfff69f3 .word 0xcfff69f3 800b440: 58000c00 .word 0x58000c00 800b444: 11fff4ff .word 0x11fff4ff 800b448: 40011000 .word 0x40011000 800b44c: 40004400 .word 0x40004400 800b450: 40004800 .word 0x40004800 800b454: 40004c00 .word 0x40004c00 800b458: 40005000 .word 0x40005000 800b45c: 40011400 .word 0x40011400 800b460: 40007800 .word 0x40007800 800b464: 40007c00 .word 0x40007c00 800b468: 58024400 .word 0x58024400 800b46c: 03d09000 .word 0x03d09000 800b470: 003d0900 .word 0x003d0900 800b474: 08011a2c .word 0x08011a2c if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800b478: 4b24 ldr r3, [pc, #144] @ (800b50c ) 800b47a: 681a ldr r2, [r3, #0] 800b47c: 0690 lsls r0, r2, #26 800b47e: d43d bmi.n 800b4fc pclk = (uint32_t) HSI_VALUE; 800b480: 4823 ldr r0, [pc, #140] @ (800b510 ) lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 800b482: 4b24 ldr r3, [pc, #144] @ (800b514 ) if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 800b484: 6866 ldr r6, [r4, #4] lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 800b486: f833 2015 ldrh.w r2, [r3, r5, lsl #1] if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 800b48a: eb06 0146 add.w r1, r6, r6, lsl #1 lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 800b48e: fbb0 f3f2 udiv r3, r0, r2 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 800b492: 4299 cmp r1, r3 800b494: f63f aec8 bhi.w 800b228 800b498: ebb3 3f06 cmp.w r3, r6, lsl #12 800b49c: f63f aec4 bhi.w 800b228 usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800b4a0: 2300 movs r3, #0 800b4a2: 4619 mov r1, r3 800b4a4: f7f4 ff74 bl 8000390 <__aeabi_uldivmod> 800b4a8: 4632 mov r2, r6 800b4aa: 0209 lsls r1, r1, #8 800b4ac: 0203 lsls r3, r0, #8 800b4ae: ea41 6110 orr.w r1, r1, r0, lsr #24 800b4b2: 0870 lsrs r0, r6, #1 800b4b4: 1818 adds r0, r3, r0 800b4b6: f04f 0300 mov.w r3, #0 800b4ba: f141 0100 adc.w r1, r1, #0 800b4be: f7f4 ff67 bl 8000390 <__aeabi_uldivmod> if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 800b4c2: 4b15 ldr r3, [pc, #84] @ (800b518 ) 800b4c4: f5a0 7240 sub.w r2, r0, #768 @ 0x300 800b4c8: 429a cmp r2, r3 800b4ca: f63f aead bhi.w 800b228 800b4ce: e74f b.n 800b370 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800b4d0: a803 add r0, sp, #12 800b4d2: f7fd fe7f bl 80091d4 pclk = pll3_clocks.PLL3_Q_Frequency; 800b4d6: 9804 ldr r0, [sp, #16] if (pclk != 0U) 800b4d8: 2800 cmp r0, #0 800b4da: f43f af4b beq.w 800b374 lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 800b4de: 6a65 ldr r5, [r4, #36] @ 0x24 800b4e0: e7cf b.n 800b482 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800b4e2: 4668 mov r0, sp 800b4e4: f7fd fddc bl 80090a0 pclk = pll2_clocks.PLL2_Q_Frequency; 800b4e8: 9801 ldr r0, [sp, #4] break; 800b4ea: e7f5 b.n 800b4d8 pclk = HAL_RCCEx_GetD3PCLK1Freq(); 800b4ec: f7fd fdc6 bl 800907c break; 800b4f0: e7f2 b.n 800b4d8 pclk = (uint32_t) LSE_VALUE; 800b4f2: f44f 4000 mov.w r0, #32768 @ 0x8000 800b4f6: e7c4 b.n 800b482 pclk = (uint32_t) CSI_VALUE; 800b4f8: 4808 ldr r0, [pc, #32] @ (800b51c ) 800b4fa: e7c2 b.n 800b482 pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800b4fc: 681b ldr r3, [r3, #0] 800b4fe: 4804 ldr r0, [pc, #16] @ (800b510 ) 800b500: f3c3 03c1 ubfx r3, r3, #3, #2 800b504: 40d8 lsrs r0, r3 if (pclk != 0U) 800b506: e7bc b.n 800b482 pclk = (uint32_t) HSI_VALUE; 800b508: 4801 ldr r0, [pc, #4] @ (800b510 ) 800b50a: e748 b.n 800b39e 800b50c: 58024400 .word 0x58024400 800b510: 03d09000 .word 0x03d09000 800b514: 08011a2c .word 0x08011a2c 800b518: 000ffcff .word 0x000ffcff 800b51c: 003d0900 .word 0x003d0900 0800b520 : if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 800b520: 6a83 ldr r3, [r0, #40] @ 0x28 800b522: 071a lsls r2, r3, #28 { 800b524: b410 push {r4} if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 800b526: d506 bpl.n 800b536 MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 800b528: 6801 ldr r1, [r0, #0] 800b52a: 6b84 ldr r4, [r0, #56] @ 0x38 800b52c: 684a ldr r2, [r1, #4] 800b52e: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800b532: 4322 orrs r2, r4 800b534: 604a str r2, [r1, #4] if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800b536: 07dc lsls r4, r3, #31 800b538: d506 bpl.n 800b548 MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 800b53a: 6801 ldr r1, [r0, #0] 800b53c: 6ac4 ldr r4, [r0, #44] @ 0x2c 800b53e: 684a ldr r2, [r1, #4] 800b540: f422 3200 bic.w r2, r2, #131072 @ 0x20000 800b544: 4322 orrs r2, r4 800b546: 604a str r2, [r1, #4] if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 800b548: 0799 lsls r1, r3, #30 800b54a: d506 bpl.n 800b55a MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 800b54c: 6801 ldr r1, [r0, #0] 800b54e: 6b04 ldr r4, [r0, #48] @ 0x30 800b550: 684a ldr r2, [r1, #4] 800b552: f422 3280 bic.w r2, r2, #65536 @ 0x10000 800b556: 4322 orrs r2, r4 800b558: 604a str r2, [r1, #4] if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 800b55a: 075a lsls r2, r3, #29 800b55c: d506 bpl.n 800b56c MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 800b55e: 6801 ldr r1, [r0, #0] 800b560: 6b44 ldr r4, [r0, #52] @ 0x34 800b562: 684a ldr r2, [r1, #4] 800b564: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800b568: 4322 orrs r2, r4 800b56a: 604a str r2, [r1, #4] if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 800b56c: 06dc lsls r4, r3, #27 800b56e: d506 bpl.n 800b57e MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 800b570: 6801 ldr r1, [r0, #0] 800b572: 6bc4 ldr r4, [r0, #60] @ 0x3c 800b574: 688a ldr r2, [r1, #8] 800b576: f422 5280 bic.w r2, r2, #4096 @ 0x1000 800b57a: 4322 orrs r2, r4 800b57c: 608a str r2, [r1, #8] if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 800b57e: 0699 lsls r1, r3, #26 800b580: d506 bpl.n 800b590 MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 800b582: 6801 ldr r1, [r0, #0] 800b584: 6c04 ldr r4, [r0, #64] @ 0x40 800b586: 688a ldr r2, [r1, #8] 800b588: f422 5200 bic.w r2, r2, #8192 @ 0x2000 800b58c: 4322 orrs r2, r4 800b58e: 608a str r2, [r1, #8] if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 800b590: 065a lsls r2, r3, #25 800b592: d50a bpl.n 800b5aa MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 800b594: 6801 ldr r1, [r0, #0] 800b596: 6c44 ldr r4, [r0, #68] @ 0x44 800b598: 684a ldr r2, [r1, #4] if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 800b59a: f5b4 1f80 cmp.w r4, #1048576 @ 0x100000 MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 800b59e: f422 1280 bic.w r2, r2, #1048576 @ 0x100000 800b5a2: ea42 0204 orr.w r2, r2, r4 800b5a6: 604a str r2, [r1, #4] if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 800b5a8: d00b beq.n 800b5c2 if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 800b5aa: 061b lsls r3, r3, #24 800b5ac: d506 bpl.n 800b5bc MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 800b5ae: 6802 ldr r2, [r0, #0] 800b5b0: 6cc1 ldr r1, [r0, #76] @ 0x4c 800b5b2: 6853 ldr r3, [r2, #4] 800b5b4: f423 2300 bic.w r3, r3, #524288 @ 0x80000 800b5b8: 430b orrs r3, r1 800b5ba: 6053 str r3, [r2, #4] } 800b5bc: f85d 4b04 ldr.w r4, [sp], #4 800b5c0: 4770 bx lr MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 800b5c2: 684a ldr r2, [r1, #4] 800b5c4: 6c84 ldr r4, [r0, #72] @ 0x48 800b5c6: f422 02c0 bic.w r2, r2, #6291456 @ 0x600000 800b5ca: 4322 orrs r2, r4 800b5cc: 604a str r2, [r1, #4] 800b5ce: e7ec b.n 800b5aa 0800b5d0 : { 800b5d0: b538 push {r3, r4, r5, lr} huart->ErrorCode = HAL_UART_ERROR_NONE; 800b5d2: 2300 movs r3, #0 { 800b5d4: 4604 mov r4, r0 huart->ErrorCode = HAL_UART_ERROR_NONE; 800b5d6: f8c0 3090 str.w r3, [r0, #144] @ 0x90 tickstart = HAL_GetTick(); 800b5da: f7f8 fcf9 bl 8003fd0 if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 800b5de: 6822 ldr r2, [r4, #0] tickstart = HAL_GetTick(); 800b5e0: 4605 mov r5, r0 if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 800b5e2: 6813 ldr r3, [r2, #0] 800b5e4: 071b lsls r3, r3, #28 800b5e6: d40f bmi.n 800b608 if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 800b5e8: 6813 ldr r3, [r2, #0] 800b5ea: 0759 lsls r1, r3, #29 800b5ec: d431 bmi.n 800b652 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b5ee: 2300 movs r3, #0 huart->gState = HAL_UART_STATE_READY; 800b5f0: 2220 movs r2, #32 return HAL_OK; 800b5f2: 4618 mov r0, r3 huart->gState = HAL_UART_STATE_READY; 800b5f4: f8c4 2088 str.w r2, [r4, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 800b5f8: f8c4 208c str.w r2, [r4, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b5fc: 66e3 str r3, [r4, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 800b5fe: 6723 str r3, [r4, #112] @ 0x70 __HAL_UNLOCK(huart); 800b600: 2300 movs r3, #0 800b602: f884 3084 strb.w r3, [r4, #132] @ 0x84 } 800b606: bd38 pop {r3, r4, r5, pc} while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800b608: 69d3 ldr r3, [r2, #28] 800b60a: 0298 lsls r0, r3, #10 800b60c: d4ec bmi.n 800b5e8 800b60e: e00c b.n 800b62a if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 800b610: 6819 ldr r1, [r3, #0] 800b612: 461a mov r2, r3 800b614: 0749 lsls r1, r1, #29 800b616: d505 bpl.n 800b624 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 800b618: 69d9 ldr r1, [r3, #28] 800b61a: 0708 lsls r0, r1, #28 800b61c: d44a bmi.n 800b6b4 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 800b61e: 69d9 ldr r1, [r3, #28] 800b620: 0509 lsls r1, r1, #20 800b622: d475 bmi.n 800b710 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800b624: 69db ldr r3, [r3, #28] 800b626: 0298 lsls r0, r3, #10 800b628: d4de bmi.n 800b5e8 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800b62a: f7f8 fcd1 bl 8003fd0 800b62e: 1b43 subs r3, r0, r5 800b630: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 800b634: 6823 ldr r3, [r4, #0] if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800b636: d3eb bcc.n 800b610 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b638: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 800b63c: f022 0280 bic.w r2, r2, #128 @ 0x80 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b640: e843 2100 strex r1, r2, [r3] 800b644: 2900 cmp r1, #0 800b646: d1f7 bne.n 800b638 huart->gState = HAL_UART_STATE_READY; 800b648: 2320 movs r3, #32 800b64a: f8c4 3088 str.w r3, [r4, #136] @ 0x88 return HAL_TIMEOUT; 800b64e: 2003 movs r0, #3 800b650: e7d6 b.n 800b600 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800b652: 69d3 ldr r3, [r2, #28] 800b654: 025b lsls r3, r3, #9 800b656: d4ca bmi.n 800b5ee 800b658: e00d b.n 800b676 if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 800b65a: 681a ldr r2, [r3, #0] 800b65c: 0750 lsls r0, r2, #29 800b65e: d507 bpl.n 800b670 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 800b660: 69da ldr r2, [r3, #28] 800b662: 0711 lsls r1, r2, #28 800b664: f100 8082 bmi.w 800b76c if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 800b668: 69da ldr r2, [r3, #28] 800b66a: 0512 lsls r2, r2, #20 800b66c: f100 80ac bmi.w 800b7c8 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 800b670: 69db ldr r3, [r3, #28] 800b672: 025b lsls r3, r3, #9 800b674: d4bb bmi.n 800b5ee if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 800b676: f7f8 fcab bl 8003fd0 800b67a: 1b43 subs r3, r0, r5 800b67c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800b680: 6823 ldr r3, [r4, #0] 800b682: d3ea bcc.n 800b65a __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b684: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800b688: f422 7290 bic.w r2, r2, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b68c: e843 2100 strex r1, r2, [r3] 800b690: 2900 cmp r1, #0 800b692: d1f7 bne.n 800b684 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b694: f103 0208 add.w r2, r3, #8 800b698: e852 2f00 ldrex r2, [r2] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800b69c: f022 0201 bic.w r2, r2, #1 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b6a0: f103 0008 add.w r0, r3, #8 800b6a4: e840 2100 strex r1, r2, [r0] 800b6a8: 2900 cmp r1, #0 800b6aa: d1f3 bne.n 800b694 huart->RxState = HAL_UART_STATE_READY; 800b6ac: 2320 movs r3, #32 800b6ae: f8c4 308c str.w r3, [r4, #140] @ 0x8c return HAL_TIMEOUT; 800b6b2: e7cc b.n 800b64e __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 800b6b4: 2208 movs r2, #8 800b6b6: 621a str r2, [r3, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b6b8: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800b6bc: f422 7290 bic.w r2, r2, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b6c0: e843 2100 strex r1, r2, [r3] 800b6c4: 2900 cmp r1, #0 800b6c6: d1f7 bne.n 800b6b8 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800b6c8: 4856 ldr r0, [pc, #344] @ (800b824 ) __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b6ca: f103 0208 add.w r2, r3, #8 800b6ce: e852 2f00 ldrex r2, [r2] 800b6d2: 4002 ands r2, r0 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b6d4: f103 0508 add.w r5, r3, #8 800b6d8: e845 2100 strex r1, r2, [r5] 800b6dc: 2900 cmp r1, #0 800b6de: d1f4 bne.n 800b6ca if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800b6e0: 6ee2 ldr r2, [r4, #108] @ 0x6c 800b6e2: 2a01 cmp r2, #1 800b6e4: d00b beq.n 800b6fe huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b6e6: 2200 movs r2, #0 huart->RxState = HAL_UART_STATE_READY; 800b6e8: 2020 movs r0, #32 huart->ErrorCode = HAL_UART_ERROR_ORE; 800b6ea: 2108 movs r1, #8 huart->RxState = HAL_UART_STATE_READY; 800b6ec: f8c4 008c str.w r0, [r4, #140] @ 0x8c huart->RxISR = NULL; 800b6f0: 6762 str r2, [r4, #116] @ 0x74 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b6f2: 66e2 str r2, [r4, #108] @ 0x6c __HAL_UNLOCK(huart); 800b6f4: f884 2084 strb.w r2, [r4, #132] @ 0x84 huart->ErrorCode = HAL_UART_ERROR_ORE; 800b6f8: f8c4 1090 str.w r1, [r4, #144] @ 0x90 return HAL_ERROR; 800b6fc: e79c b.n 800b638 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b6fe: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800b702: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b706: e843 2100 strex r1, r2, [r3] 800b70a: 2900 cmp r1, #0 800b70c: d1f7 bne.n 800b6fe 800b70e: e7ea b.n 800b6e6 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800b710: f44f 6200 mov.w r2, #2048 @ 0x800 800b714: 621a str r2, [r3, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b716: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800b71a: f422 7290 bic.w r2, r2, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b71e: e843 2100 strex r1, r2, [r3] 800b722: 2900 cmp r1, #0 800b724: d1f7 bne.n 800b716 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800b726: 483f ldr r0, [pc, #252] @ (800b824 ) __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b728: f103 0208 add.w r2, r3, #8 800b72c: e852 2f00 ldrex r2, [r2] 800b730: 4002 ands r2, r0 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b732: f103 0508 add.w r5, r3, #8 800b736: e845 2100 strex r1, r2, [r5] 800b73a: 2900 cmp r1, #0 800b73c: d1f4 bne.n 800b728 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800b73e: 6ee2 ldr r2, [r4, #108] @ 0x6c 800b740: 2a01 cmp r2, #1 800b742: d00a beq.n 800b75a huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b744: 2200 movs r2, #0 huart->RxState = HAL_UART_STATE_READY; 800b746: 2120 movs r1, #32 huart->RxISR = NULL; 800b748: 6762 str r2, [r4, #116] @ 0x74 huart->RxState = HAL_UART_STATE_READY; 800b74a: f8c4 108c str.w r1, [r4, #140] @ 0x8c __HAL_UNLOCK(huart); 800b74e: f884 2084 strb.w r2, [r4, #132] @ 0x84 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b752: 66e2 str r2, [r4, #108] @ 0x6c huart->ErrorCode = HAL_UART_ERROR_RTO; 800b754: f8c4 1090 str.w r1, [r4, #144] @ 0x90 return HAL_TIMEOUT; 800b758: e76e b.n 800b638 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b75a: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800b75e: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b762: e843 2100 strex r1, r2, [r3] 800b766: 2900 cmp r1, #0 800b768: d1f7 bne.n 800b75a 800b76a: e7eb b.n 800b744 __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 800b76c: 2208 movs r2, #8 800b76e: 621a str r2, [r3, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b770: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800b774: f422 7290 bic.w r2, r2, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b778: e843 2100 strex r1, r2, [r3] 800b77c: 2900 cmp r1, #0 800b77e: d1f7 bne.n 800b770 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800b780: 4828 ldr r0, [pc, #160] @ (800b824 ) __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b782: f103 0208 add.w r2, r3, #8 800b786: e852 2f00 ldrex r2, [r2] 800b78a: 4002 ands r2, r0 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b78c: f103 0508 add.w r5, r3, #8 800b790: e845 2100 strex r1, r2, [r5] 800b794: 2900 cmp r1, #0 800b796: d1f4 bne.n 800b782 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800b798: 6ee2 ldr r2, [r4, #108] @ 0x6c 800b79a: 2a01 cmp r2, #1 800b79c: d00b beq.n 800b7b6 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b79e: 2200 movs r2, #0 huart->RxState = HAL_UART_STATE_READY; 800b7a0: 2020 movs r0, #32 huart->ErrorCode = HAL_UART_ERROR_ORE; 800b7a2: 2108 movs r1, #8 huart->RxState = HAL_UART_STATE_READY; 800b7a4: f8c4 008c str.w r0, [r4, #140] @ 0x8c huart->RxISR = NULL; 800b7a8: 6762 str r2, [r4, #116] @ 0x74 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b7aa: 66e2 str r2, [r4, #108] @ 0x6c __HAL_UNLOCK(huart); 800b7ac: f884 2084 strb.w r2, [r4, #132] @ 0x84 huart->ErrorCode = HAL_UART_ERROR_ORE; 800b7b0: f8c4 1090 str.w r1, [r4, #144] @ 0x90 return HAL_ERROR; 800b7b4: e766 b.n 800b684 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b7b6: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800b7ba: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b7be: e843 2100 strex r1, r2, [r3] 800b7c2: 2900 cmp r1, #0 800b7c4: d1f7 bne.n 800b7b6 800b7c6: e7ea b.n 800b79e __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800b7c8: f44f 6200 mov.w r2, #2048 @ 0x800 800b7cc: 621a str r2, [r3, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b7ce: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800b7d2: f422 7290 bic.w r2, r2, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b7d6: e843 2100 strex r1, r2, [r3] 800b7da: 2900 cmp r1, #0 800b7dc: d1f7 bne.n 800b7ce ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800b7de: 4811 ldr r0, [pc, #68] @ (800b824 ) __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b7e0: f103 0208 add.w r2, r3, #8 800b7e4: e852 2f00 ldrex r2, [r2] 800b7e8: 4002 ands r2, r0 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b7ea: f103 0508 add.w r5, r3, #8 800b7ee: e845 2100 strex r1, r2, [r5] 800b7f2: 2900 cmp r1, #0 800b7f4: d1f4 bne.n 800b7e0 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800b7f6: 6ee2 ldr r2, [r4, #108] @ 0x6c 800b7f8: 2a01 cmp r2, #1 800b7fa: d00a beq.n 800b812 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b7fc: 2200 movs r2, #0 huart->RxState = HAL_UART_STATE_READY; 800b7fe: 2120 movs r1, #32 huart->RxISR = NULL; 800b800: 6762 str r2, [r4, #116] @ 0x74 huart->RxState = HAL_UART_STATE_READY; 800b802: f8c4 108c str.w r1, [r4, #140] @ 0x8c __HAL_UNLOCK(huart); 800b806: f884 2084 strb.w r2, [r4, #132] @ 0x84 huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800b80a: 66e2 str r2, [r4, #108] @ 0x6c huart->ErrorCode = HAL_UART_ERROR_RTO; 800b80c: f8c4 1090 str.w r1, [r4, #144] @ 0x90 return HAL_TIMEOUT; 800b810: e738 b.n 800b684 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b812: e853 2f00 ldrex r2, [r3] ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800b816: f022 0210 bic.w r2, r2, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b81a: e843 2100 strex r1, r2, [r3] 800b81e: 2900 cmp r1, #0 800b820: d1f7 bne.n 800b812 800b822: e7eb b.n 800b7fc 800b824: effffffe .word 0xeffffffe 0800b828 : if (huart == NULL) 800b828: b380 cbz r0, 800b88c if (huart->gState == HAL_UART_STATE_RESET) 800b82a: f8d0 3088 ldr.w r3, [r0, #136] @ 0x88 { 800b82e: b510 push {r4, lr} 800b830: 4604 mov r4, r0 if (huart->gState == HAL_UART_STATE_RESET) 800b832: b333 cbz r3, 800b882 __HAL_UART_DISABLE(huart); 800b834: 6822 ldr r2, [r4, #0] huart->gState = HAL_UART_STATE_BUSY; 800b836: 2324 movs r3, #36 @ 0x24 if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 800b838: 6aa1 ldr r1, [r4, #40] @ 0x28 huart->gState = HAL_UART_STATE_BUSY; 800b83a: f8c4 3088 str.w r3, [r4, #136] @ 0x88 __HAL_UART_DISABLE(huart); 800b83e: 6813 ldr r3, [r2, #0] 800b840: f023 0301 bic.w r3, r3, #1 800b844: 6013 str r3, [r2, #0] if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 800b846: b9c1 cbnz r1, 800b87a if (UART_SetConfig(huart) == HAL_ERROR) 800b848: 4620 mov r0, r4 800b84a: f7ff fcad bl 800b1a8 800b84e: 2801 cmp r0, #1 800b850: d011 beq.n 800b876 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800b852: 6823 ldr r3, [r4, #0] return (UART_CheckIdleState(huart)); 800b854: 4620 mov r0, r4 CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800b856: 685a ldr r2, [r3, #4] 800b858: f422 4290 bic.w r2, r2, #18432 @ 0x4800 800b85c: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 800b85e: 689a ldr r2, [r3, #8] 800b860: f022 022a bic.w r2, r2, #42 @ 0x2a 800b864: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 800b866: 681a ldr r2, [r3, #0] 800b868: f042 0201 orr.w r2, r2, #1 } 800b86c: e8bd 4010 ldmia.w sp!, {r4, lr} __HAL_UART_ENABLE(huart); 800b870: 601a str r2, [r3, #0] return (UART_CheckIdleState(huart)); 800b872: f7ff bead b.w 800b5d0 } 800b876: 2001 movs r0, #1 800b878: bd10 pop {r4, pc} UART_AdvFeatureConfig(huart); 800b87a: 4620 mov r0, r4 800b87c: f7ff fe50 bl 800b520 800b880: e7e2 b.n 800b848 huart->Lock = HAL_UNLOCKED; 800b882: f880 3084 strb.w r3, [r0, #132] @ 0x84 HAL_UART_MspInit(huart); 800b886: f7f7 fab3 bl 8002df0 800b88a: e7d3 b.n 800b834 } 800b88c: 2001 movs r0, #1 800b88e: 4770 bx lr 0800b890 : { 800b890: b430 push {r4, r5} UART_MASK_COMPUTATION(huart); 800b892: 6884 ldr r4, [r0, #8] huart->RxISR = NULL; 800b894: 2300 movs r3, #0 huart->pRxBuffPtr = pData; 800b896: 6581 str r1, [r0, #88] @ 0x58 UART_MASK_COMPUTATION(huart); 800b898: f5b4 5f80 cmp.w r4, #4096 @ 0x1000 huart->RxXferSize = Size; 800b89c: f8a0 205c strh.w r2, [r0, #92] @ 0x5c huart->RxXferCount = Size; 800b8a0: f8a0 205e strh.w r2, [r0, #94] @ 0x5e huart->RxISR = NULL; 800b8a4: 6743 str r3, [r0, #116] @ 0x74 UART_MASK_COMPUTATION(huart); 800b8a6: d04f beq.n 800b948 800b8a8: bb84 cbnz r4, 800b90c 800b8aa: 6903 ldr r3, [r0, #16] 800b8ac: 2b00 cmp r3, #0 800b8ae: bf14 ite ne 800b8b0: 237f movne r3, #127 @ 0x7f 800b8b2: 23ff moveq r3, #255 @ 0xff huart->ErrorCode = HAL_UART_ERROR_NONE; 800b8b4: 2100 movs r1, #0 huart->RxState = HAL_UART_STATE_BUSY_RX; 800b8b6: 2422 movs r4, #34 @ 0x22 UART_MASK_COMPUTATION(huart); 800b8b8: f8a0 3060 strh.w r3, [r0, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 800b8bc: f8c0 1090 str.w r1, [r0, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 800b8c0: 6801 ldr r1, [r0, #0] 800b8c2: f8c0 408c str.w r4, [r0, #140] @ 0x8c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b8c6: f101 0308 add.w r3, r1, #8 800b8ca: e853 3f00 ldrex r3, [r3] ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800b8ce: f043 0301 orr.w r3, r3, #1 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b8d2: f101 0508 add.w r5, r1, #8 800b8d6: e845 3400 strex r4, r3, [r5] 800b8da: 2c00 cmp r4, #0 800b8dc: d1f3 bne.n 800b8c6 if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 800b8de: 6e43 ldr r3, [r0, #100] @ 0x64 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800b8e0: 6885 ldr r5, [r0, #8] if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 800b8e2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800b8e6: 6904 ldr r4, [r0, #16] if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 800b8e8: d035 beq.n 800b956 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800b8ea: f5b5 5f80 cmp.w r5, #4096 @ 0x1000 800b8ee: d016 beq.n 800b91e 800b8f0: 4b32 ldr r3, [pc, #200] @ (800b9bc ) 800b8f2: 6743 str r3, [r0, #116] @ 0x74 if (huart->Init.Parity != UART_PARITY_NONE) 800b8f4: b1bc cbz r4, 800b926 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b8f6: e851 3f00 ldrex r3, [r1] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 800b8fa: f443 7390 orr.w r3, r3, #288 @ 0x120 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b8fe: e841 3200 strex r2, r3, [r1] 800b902: 2a00 cmp r2, #0 800b904: d1f7 bne.n 800b8f6 } 800b906: 2000 movs r0, #0 800b908: bc30 pop {r4, r5} 800b90a: 4770 bx lr UART_MASK_COMPUTATION(huart); 800b90c: f1b4 5f80 cmp.w r4, #268435456 @ 0x10000000 800b910: d1d0 bne.n 800b8b4 800b912: 6903 ldr r3, [r0, #16] 800b914: 2b00 cmp r3, #0 800b916: bf14 ite ne 800b918: 233f movne r3, #63 @ 0x3f 800b91a: 237f moveq r3, #127 @ 0x7f 800b91c: e7ca b.n 800b8b4 if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800b91e: 2c00 cmp r4, #0 800b920: d146 bne.n 800b9b0 800b922: 4b27 ldr r3, [pc, #156] @ (800b9c0 ) 800b924: 6743 str r3, [r0, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b926: e851 3f00 ldrex r3, [r1] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 800b92a: f043 0320 orr.w r3, r3, #32 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b92e: e841 3200 strex r2, r3, [r1] 800b932: 2a00 cmp r2, #0 800b934: d0e7 beq.n 800b906 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b936: e851 3f00 ldrex r3, [r1] 800b93a: f043 0320 orr.w r3, r3, #32 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b93e: e841 3200 strex r2, r3, [r1] 800b942: 2a00 cmp r2, #0 800b944: d1ef bne.n 800b926 800b946: e7de b.n 800b906 UART_MASK_COMPUTATION(huart); 800b948: 6901 ldr r1, [r0, #16] 800b94a: f240 13ff movw r3, #511 @ 0x1ff 800b94e: 2900 cmp r1, #0 800b950: bf18 it ne 800b952: 23ff movne r3, #255 @ 0xff 800b954: e7ae b.n 800b8b4 if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 800b956: f8b0 3068 ldrh.w r3, [r0, #104] @ 0x68 800b95a: 4293 cmp r3, r2 800b95c: d8c5 bhi.n 800b8ea if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800b95e: f5b5 5f80 cmp.w r5, #4096 @ 0x1000 800b962: d011 beq.n 800b988 huart->RxISR = UART_RxISR_8BIT_FIFOEN; 800b964: 4b17 ldr r3, [pc, #92] @ (800b9c4 ) 800b966: 6743 str r3, [r0, #116] @ 0x74 if (huart->Init.Parity != UART_PARITY_NONE) 800b968: b98c cbnz r4, 800b98e __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b96a: f101 0308 add.w r3, r1, #8 800b96e: e853 3f00 ldrex r3, [r3] ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 800b972: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b976: f101 0008 add.w r0, r1, #8 800b97a: e840 3200 strex r2, r3, [r0] 800b97e: 2a00 cmp r2, #0 800b980: d1f3 bne.n 800b96a } 800b982: 2000 movs r0, #0 800b984: bc30 pop {r4, r5} 800b986: 4770 bx lr if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800b988: b1ac cbz r4, 800b9b6 huart->RxISR = UART_RxISR_8BIT_FIFOEN; 800b98a: 4b0e ldr r3, [pc, #56] @ (800b9c4 ) 800b98c: 6743 str r3, [r0, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b98e: e851 3f00 ldrex r3, [r1] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800b992: f443 7380 orr.w r3, r3, #256 @ 0x100 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b996: e841 3200 strex r2, r3, [r1] 800b99a: 2a00 cmp r2, #0 800b99c: d0e5 beq.n 800b96a __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b99e: e851 3f00 ldrex r3, [r1] 800b9a2: f443 7380 orr.w r3, r3, #256 @ 0x100 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b9a6: e841 3200 strex r2, r3, [r1] 800b9aa: 2a00 cmp r2, #0 800b9ac: d1ef bne.n 800b98e 800b9ae: e7dc b.n 800b96a 800b9b0: 4b02 ldr r3, [pc, #8] @ (800b9bc ) 800b9b2: 6743 str r3, [r0, #116] @ 0x74 if (huart->Init.Parity != UART_PARITY_NONE) 800b9b4: e79f b.n 800b8f6 800b9b6: 4b04 ldr r3, [pc, #16] @ (800b9c8 ) 800b9b8: 6743 str r3, [r0, #116] @ 0x74 if (huart->Init.Parity != UART_PARITY_NONE) 800b9ba: e7d6 b.n 800b96a 800b9bc: 0800ad8d .word 0x0800ad8d 800b9c0: 0800ad45 .word 0x0800ad45 800b9c4: 0800add1 .word 0x0800add1 800b9c8: 0800afbd .word 0x0800afbd 0800b9cc : UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 800b9cc: 4770 bx lr 800b9ce: bf00 nop 0800b9d0 : /** * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) 800b9d0: 4770 bx lr 800b9d2: bf00 nop 0800b9d4 : /** * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) 800b9d4: 4770 bx lr 800b9d6: bf00 nop 0800b9d8 : /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 800b9d8: f890 2084 ldrb.w r2, [r0, #132] @ 0x84 800b9dc: 2a01 cmp r2, #1 800b9de: d017 beq.n 800ba10 huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800b9e0: 6802 ldr r2, [r0, #0] 800b9e2: 4603 mov r3, r0 huart->gState = HAL_UART_STATE_BUSY; 800b9e4: 2024 movs r0, #36 @ 0x24 /* Disable UART */ __HAL_UART_DISABLE(huart); /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; 800b9e6: 2100 movs r1, #0 { 800b9e8: b430 push {r4, r5} huart->gState = HAL_UART_STATE_BUSY; 800b9ea: f8c3 0088 str.w r0, [r3, #136] @ 0x88 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); huart->gState = HAL_UART_STATE_READY; 800b9ee: 2520 movs r5, #32 tmpcr1 = READ_REG(huart->Instance->CR1); 800b9f0: 6810 ldr r0, [r2, #0] __HAL_UART_DISABLE(huart); 800b9f2: 6814 ldr r4, [r2, #0] CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 800b9f4: f020 5000 bic.w r0, r0, #536870912 @ 0x20000000 __HAL_UART_DISABLE(huart); 800b9f8: f024 0401 bic.w r4, r4, #1 800b9fc: 6014 str r4, [r2, #0] huart->FifoMode = UART_FIFOMODE_DISABLE; 800b9fe: 6659 str r1, [r3, #100] @ 0x64 WRITE_REG(huart->Instance->CR1, tmpcr1); 800ba00: 6010 str r0, [r2, #0] /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; 800ba02: 4608 mov r0, r1 huart->gState = HAL_UART_STATE_READY; 800ba04: f8c3 5088 str.w r5, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 800ba08: f883 1084 strb.w r1, [r3, #132] @ 0x84 } 800ba0c: bc30 pop {r4, r5} 800ba0e: 4770 bx lr __HAL_LOCK(huart); 800ba10: 2002 movs r0, #2 } 800ba12: 4770 bx lr 0800ba14 : /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800ba14: f890 2084 ldrb.w r2, [r0, #132] @ 0x84 800ba18: 2a01 cmp r2, #1 800ba1a: d037 beq.n 800ba8c huart->gState = HAL_UART_STATE_BUSY; /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800ba1c: 6802 ldr r2, [r0, #0] 800ba1e: 4603 mov r3, r0 huart->gState = HAL_UART_STATE_BUSY; 800ba20: 2024 movs r0, #36 @ 0x24 { 800ba22: b530 push {r4, r5, lr} huart->gState = HAL_UART_STATE_BUSY; 800ba24: f8c3 0088 str.w r0, [r3, #136] @ 0x88 tmpcr1 = READ_REG(huart->Instance->CR1); 800ba28: 6814 ldr r4, [r2, #0] /* Disable UART */ __HAL_UART_DISABLE(huart); 800ba2a: 6810 ldr r0, [r2, #0] 800ba2c: f020 0001 bic.w r0, r0, #1 800ba30: 6010 str r0, [r2, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 800ba32: 6890 ldr r0, [r2, #8] 800ba34: f020 4060 bic.w r0, r0, #3758096384 @ 0xe0000000 800ba38: 4301 orrs r1, r0 uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 800ba3a: 6e58 ldr r0, [r3, #100] @ 0x64 MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 800ba3c: 6091 str r1, [r2, #8] if (huart->FifoMode == UART_FIFOMODE_DISABLE) 800ba3e: b310 cbz r0, 800ba86 } else { rx_fifo_depth = RX_FIFO_DEPTH; tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 800ba40: 6891 ldr r1, [r2, #8] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800ba42: 6890 ldr r0, [r2, #8] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800ba44: f3c1 6c42 ubfx ip, r1, #25, #3 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800ba48: 4911 ldr r1, [pc, #68] @ (800ba90 ) tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800ba4a: ea4f 7e50 mov.w lr, r0, lsr #29 (uint16_t)denominator[tx_fifo_threshold]; 800ba4e: 4d11 ldr r5, [pc, #68] @ (800ba94 ) huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800ba50: f811 000e ldrb.w r0, [r1, lr] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800ba54: f811 100c ldrb.w r1, [r1, ip] (uint16_t)denominator[tx_fifo_threshold]; 800ba58: f815 e00e ldrb.w lr, [r5, lr] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800ba5c: 0100 lsls r0, r0, #4 (uint16_t)denominator[rx_fifo_threshold]; 800ba5e: f815 500c ldrb.w r5, [r5, ip] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800ba62: 0109 lsls r1, r1, #4 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800ba64: fbb0 f0fe udiv r0, r0, lr huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800ba68: fbb1 f1f5 udiv r1, r1, r5 800ba6c: f8a3 1068 strh.w r1, [r3, #104] @ 0x68 huart->gState = HAL_UART_STATE_READY; 800ba70: 2520 movs r5, #32 __HAL_UNLOCK(huart); 800ba72: 2100 movs r1, #0 800ba74: f8a3 006a strh.w r0, [r3, #106] @ 0x6a WRITE_REG(huart->Instance->CR1, tmpcr1); 800ba78: 6014 str r4, [r2, #0] return HAL_OK; 800ba7a: 4608 mov r0, r1 huart->gState = HAL_UART_STATE_READY; 800ba7c: f8c3 5088 str.w r5, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 800ba80: f883 1084 strb.w r1, [r3, #132] @ 0x84 } 800ba84: bd30 pop {r4, r5, pc} huart->NbRxDataToProcess = 1U; 800ba86: 2101 movs r1, #1 huart->NbTxDataToProcess = 1U; 800ba88: 4608 mov r0, r1 800ba8a: e7ef b.n 800ba6c __HAL_LOCK(huart); 800ba8c: 2002 movs r0, #2 } 800ba8e: 4770 bx lr 800ba90: 08011a4c .word 0x08011a4c 800ba94: 08011a44 .word 0x08011a44 0800ba98 : __HAL_LOCK(huart); 800ba98: f890 2084 ldrb.w r2, [r0, #132] @ 0x84 800ba9c: 2a01 cmp r2, #1 800ba9e: d037 beq.n 800bb10 tmpcr1 = READ_REG(huart->Instance->CR1); 800baa0: 6802 ldr r2, [r0, #0] 800baa2: 4603 mov r3, r0 huart->gState = HAL_UART_STATE_BUSY; 800baa4: 2024 movs r0, #36 @ 0x24 { 800baa6: b530 push {r4, r5, lr} huart->gState = HAL_UART_STATE_BUSY; 800baa8: f8c3 0088 str.w r0, [r3, #136] @ 0x88 tmpcr1 = READ_REG(huart->Instance->CR1); 800baac: 6814 ldr r4, [r2, #0] __HAL_UART_DISABLE(huart); 800baae: 6810 ldr r0, [r2, #0] 800bab0: f020 0001 bic.w r0, r0, #1 800bab4: 6010 str r0, [r2, #0] MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800bab6: 6890 ldr r0, [r2, #8] 800bab8: f020 6060 bic.w r0, r0, #234881024 @ 0xe000000 800babc: 4301 orrs r1, r0 if (huart->FifoMode == UART_FIFOMODE_DISABLE) 800babe: 6e58 ldr r0, [r3, #100] @ 0x64 MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800bac0: 6091 str r1, [r2, #8] if (huart->FifoMode == UART_FIFOMODE_DISABLE) 800bac2: b310 cbz r0, 800bb0a rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 800bac4: 6891 ldr r1, [r2, #8] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800bac6: 6890 ldr r0, [r2, #8] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800bac8: f3c1 6c42 ubfx ip, r1, #25, #3 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800bacc: 4911 ldr r1, [pc, #68] @ (800bb14 ) tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800bace: ea4f 7e50 mov.w lr, r0, lsr #29 (uint16_t)denominator[tx_fifo_threshold]; 800bad2: 4d11 ldr r5, [pc, #68] @ (800bb18 ) huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800bad4: f811 000e ldrb.w r0, [r1, lr] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800bad8: f811 100c ldrb.w r1, [r1, ip] (uint16_t)denominator[tx_fifo_threshold]; 800badc: f815 e00e ldrb.w lr, [r5, lr] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800bae0: 0100 lsls r0, r0, #4 (uint16_t)denominator[rx_fifo_threshold]; 800bae2: f815 500c ldrb.w r5, [r5, ip] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800bae6: 0109 lsls r1, r1, #4 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800bae8: fbb0 f0fe udiv r0, r0, lr huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800baec: fbb1 f1f5 udiv r1, r1, r5 800baf0: f8a3 1068 strh.w r1, [r3, #104] @ 0x68 huart->gState = HAL_UART_STATE_READY; 800baf4: 2520 movs r5, #32 __HAL_UNLOCK(huart); 800baf6: 2100 movs r1, #0 800baf8: f8a3 006a strh.w r0, [r3, #106] @ 0x6a WRITE_REG(huart->Instance->CR1, tmpcr1); 800bafc: 6014 str r4, [r2, #0] return HAL_OK; 800bafe: 4608 mov r0, r1 huart->gState = HAL_UART_STATE_READY; 800bb00: f8c3 5088 str.w r5, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 800bb04: f883 1084 strb.w r1, [r3, #132] @ 0x84 } 800bb08: bd30 pop {r4, r5, pc} huart->NbRxDataToProcess = 1U; 800bb0a: 2101 movs r1, #1 huart->NbTxDataToProcess = 1U; 800bb0c: 4608 mov r0, r1 800bb0e: e7ef b.n 800baf0 __HAL_LOCK(huart); 800bb10: 2002 movs r0, #2 } 800bb12: 4770 bx lr 800bb14: 08011a4c .word 0x08011a4c 800bb18: 08011a44 .word 0x08011a44 0800bb1c : { 800bb1c: b570 push {r4, r5, r6, lr} if (huart->RxState == HAL_UART_STATE_READY) 800bb1e: f8d0 608c ldr.w r6, [r0, #140] @ 0x8c 800bb22: 2e20 cmp r6, #32 800bb24: d10f bne.n 800bb46 if ((pData == NULL) || (Size == 0U)) 800bb26: b161 cbz r1, 800bb42 800bb28: fab2 f582 clz r5, r2 800bb2c: 096d lsrs r5, r5, #5 800bb2e: b142 cbz r2, 800bb42 huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 800bb30: 2301 movs r3, #1 800bb32: 4604 mov r4, r0 800bb34: 66c3 str r3, [r0, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 800bb36: 6705 str r5, [r0, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 800bb38: f7ff feaa bl 800b890 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800bb3c: 6ee3 ldr r3, [r4, #108] @ 0x6c 800bb3e: 2b01 cmp r3, #1 800bb40: d003 beq.n 800bb4a return HAL_ERROR; 800bb42: 2001 movs r0, #1 } 800bb44: bd70 pop {r4, r5, r6, pc} return HAL_BUSY; 800bb46: 2002 movs r0, #2 } 800bb48: bd70 pop {r4, r5, r6, pc} __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800bb4a: 6822 ldr r2, [r4, #0] 800bb4c: 2310 movs r3, #16 800bb4e: 6213 str r3, [r2, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800bb50: e852 3f00 ldrex r3, [r2] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800bb54: f043 0310 orr.w r3, r3, #16 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800bb58: e842 3100 strex r1, r3, [r2] 800bb5c: 2900 cmp r1, #0 800bb5e: d1f7 bne.n 800bb50 HAL_StatusTypeDef status = HAL_OK; 800bb60: 2000 movs r0, #0 } 800bb62: bd70 pop {r4, r5, r6, pc} 0800bb64 : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 800bb64: b510 push {r4, lr} TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 800bb66: f002 fe9f bl 800e8a8 if (callb != NULL) { 800bb6a: b120 cbz r0, 800bb76 callb->func (callb->arg); 800bb6c: e9d0 3000 ldrd r3, r0, [r0] } } 800bb70: e8bd 4010 ldmia.w sp!, {r4, lr} callb->func (callb->arg); 800bb74: 4718 bx r3 } 800bb76: bd10 pop {r4, pc} 0800bb78 : void SysTick_Handler (void) { 800bb78: b508 push {r3, lr} SysTick->CTRL; 800bb7a: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800bb7e: 691b ldr r3, [r3, #16] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 800bb80: f002 f8d6 bl 800dd30 800bb84: 2801 cmp r0, #1 800bb86: d100 bne.n 800bb8a } 800bb88: bd08 pop {r3, pc} 800bb8a: e8bd 4008 ldmia.w sp!, {r3, lr} xPortSysTickHandler(); 800bb8e: f002 bf71 b.w 800ea74 800bb92: bf00 nop 0800bb94 : __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800bb94: f3ef 8305 mrs r3, IPSR if (IS_IRQ()) { 800bb98: b92b cbnz r3, 800bba6 if (KernelState == osKernelInactive) { 800bb9a: 4b06 ldr r3, [pc, #24] @ (800bbb4 ) 800bb9c: 6818 ldr r0, [r3, #0] 800bb9e: b928 cbnz r0, 800bbac KernelState = osKernelReady; 800bba0: 2201 movs r2, #1 800bba2: 601a str r2, [r3, #0] stat = osOK; 800bba4: 4770 bx lr stat = osErrorISR; 800bba6: f06f 0005 mvn.w r0, #5 800bbaa: 4770 bx lr stat = osError; 800bbac: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff } 800bbb0: 4770 bx lr 800bbb2: bf00 nop 800bbb4: 24002b00 .word 0x24002b00 0800bbb8 : osStatus_t osKernelStart (void) { 800bbb8: b510 push {r4, lr} 800bbba: f3ef 8405 mrs r4, IPSR if (IS_IRQ()) { 800bbbe: b974 cbnz r4, 800bbde if (KernelState == osKernelReady) { 800bbc0: 4b08 ldr r3, [pc, #32] @ (800bbe4 ) 800bbc2: 681a ldr r2, [r3, #0] 800bbc4: 2a01 cmp r2, #1 800bbc6: d107 bne.n 800bbd8 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800bbc8: 4907 ldr r1, [pc, #28] @ (800bbe8 ) KernelState = osKernelRunning; 800bbca: 2202 movs r2, #2 800bbcc: 77cc strb r4, [r1, #31] 800bbce: 601a str r2, [r3, #0] vTaskStartScheduler(); 800bbd0: f001 fe64 bl 800d89c stat = osOK; 800bbd4: 4620 mov r0, r4 } 800bbd6: bd10 pop {r4, pc} stat = osError; 800bbd8: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff } 800bbdc: bd10 pop {r4, pc} stat = osErrorISR; 800bbde: f06f 0005 mvn.w r0, #5 } 800bbe2: bd10 pop {r4, pc} 800bbe4: 24002b00 .word 0x24002b00 800bbe8: e000ed00 .word 0xe000ed00 0800bbec : osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 800bbec: b5f0 push {r4, r5, r6, r7, lr} hTask = NULL; 800bbee: 2500 movs r5, #0 osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 800bbf0: b087 sub sp, #28 hTask = NULL; 800bbf2: 9505 str r5, [sp, #20] 800bbf4: f3ef 8305 mrs r3, IPSR if (!IS_IRQ() && (func != NULL)) { 800bbf8: b300 cbz r0, 800bc3c 800bbfa: b9fb cbnz r3, 800bc3c if (attr != NULL) { 800bbfc: 4614 mov r4, r2 800bbfe: b302 cbz r2, 800bc42 if (attr->priority != osPriorityNone) { 800bc00: 6996 ldr r6, [r2, #24] 800bc02: b9c6 cbnz r6, 800bc36 800bc04: 2618 movs r6, #24 if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 800bc06: 6863 ldr r3, [r4, #4] 800bc08: 07db lsls r3, r3, #31 800bc0a: d417 bmi.n 800bc3c if (attr->stack_size > 0U) { 800bc0c: 6963 ldr r3, [r4, #20] 800bc0e: b333 cbz r3, 800bc5e stack = attr->stack_size / sizeof(StackType_t); 800bc10: 089a lsrs r2, r3, #2 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 800bc12: 68a5 ldr r5, [r4, #8] if (attr->name != NULL) { 800bc14: f8d4 c000 ldr.w ip, [r4] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 800bc18: 68e7 ldr r7, [r4, #12] 800bc1a: b31d cbz r5, 800bc64 800bc1c: 2fa7 cmp r7, #167 @ 0xa7 800bc1e: d90d bls.n 800bc3c (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 800bc20: 6924 ldr r4, [r4, #16] 800bc22: b15b cbz r3, 800bc3c 800bc24: b154 cbz r4, 800bc3c hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 800bc26: 460b mov r3, r1 800bc28: 9600 str r6, [sp, #0] 800bc2a: 4661 mov r1, ip 800bc2c: e9cd 4501 strd r4, r5, [sp, #4] 800bc30: f001 fd74 bl 800d71c 800bc34: e003 b.n 800bc3e if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 800bc36: 1e72 subs r2, r6, #1 800bc38: 2a37 cmp r2, #55 @ 0x37 800bc3a: d9e4 bls.n 800bc06 return (NULL); 800bc3c: 2000 movs r0, #0 } 800bc3e: b007 add sp, #28 800bc40: bdf0 pop {r4, r5, r6, r7, pc} 800bc42: f44f 7200 mov.w r2, #512 @ 0x200 prio = (UBaseType_t)osPriorityNormal; 800bc46: 2618 movs r6, #24 if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 800bc48: 460b mov r3, r1 800bc4a: 4621 mov r1, r4 800bc4c: ac05 add r4, sp, #20 800bc4e: 9600 str r6, [sp, #0] 800bc50: 9401 str r4, [sp, #4] 800bc52: f001 fd9d bl 800d790 800bc56: 2801 cmp r0, #1 800bc58: d1f0 bne.n 800bc3c return ((osThreadId_t)hTask); 800bc5a: 9805 ldr r0, [sp, #20] 800bc5c: e7ef b.n 800bc3e stack = configMINIMAL_STACK_SIZE; 800bc5e: f44f 7200 mov.w r2, #512 @ 0x200 800bc62: e7d6 b.n 800bc12 if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 800bc64: 2f00 cmp r7, #0 800bc66: d1e9 bne.n 800bc3c 800bc68: 6923 ldr r3, [r4, #16] 800bc6a: 2b00 cmp r3, #0 800bc6c: d1e6 bne.n 800bc3c if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 800bc6e: b292 uxth r2, r2 800bc70: 4664 mov r4, ip 800bc72: e7e9 b.n 800bc48 0800bc74 : 800bc74: f3ef 8205 mrs r2, IPSR if (IS_IRQ()) { 800bc78: b93a cbnz r2, 800bc8a osStatus_t osDelay (uint32_t ticks) { 800bc7a: b508 push {r3, lr} if (ticks != 0U) { 800bc7c: b908 cbnz r0, 800bc82 stat = osOK; 800bc7e: 2000 movs r0, #0 } 800bc80: bd08 pop {r3, pc} vTaskDelay(ticks); 800bc82: f001 fdb5 bl 800d7f0 stat = osOK; 800bc86: 2000 movs r0, #0 } 800bc88: bd08 pop {r3, pc} stat = osErrorISR; 800bc8a: f06f 0005 mvn.w r0, #5 } 800bc8e: 4770 bx lr 0800bc90 : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 800bc90: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800bc94: 461c mov r4, r3 800bc96: b082 sub sp, #8 800bc98: f3ef 8305 mrs r3, IPSR UBaseType_t reload; int32_t mem; hTimer = NULL; if (!IS_IRQ() && (func != NULL)) { 800bc9c: b1b8 cbz r0, 800bcce 800bc9e: b9b3 cbnz r3, 800bcce /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 800bca0: 4605 mov r5, r0 800bca2: 2008 movs r0, #8 800bca4: 460e mov r6, r1 800bca6: 4617 mov r7, r2 800bca8: f002 ffdc bl 800ec64 if (callb != NULL) { 800bcac: 4680 mov r8, r0 800bcae: b170 cbz r0, 800bcce callb->func = func; callb->arg = argument; if (type == osTimerOnce) { 800bcb0: 3e00 subs r6, #0 callb->arg = argument; 800bcb2: e9c0 5700 strd r5, r7, [r0] if (type == osTimerOnce) { 800bcb6: bf18 it ne 800bcb8: 2601 movne r6, #1 } mem = -1; name = NULL; if (attr != NULL) { 800bcba: b1e4 cbz r4, 800bcf6 if (attr->name != NULL) { name = attr->name; } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 800bcbc: 68a3 ldr r3, [r4, #8] if (attr->name != NULL) { 800bcbe: 6820 ldr r0, [r4, #0] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 800bcc0: 68e2 ldr r2, [r4, #12] 800bcc2: b1ab cbz r3, 800bcf0 800bcc4: 2a2b cmp r2, #43 @ 0x2b 800bcc6: d806 bhi.n 800bcd6 #endif } } if ((hTimer == NULL) && (callb != NULL)) { vPortFree (callb); 800bcc8: 4640 mov r0, r8 800bcca: f003 f887 bl 800eddc hTimer = NULL; 800bcce: 2000 movs r0, #0 } } } return ((osTimerId_t)hTimer); } 800bcd0: b002 add sp, #8 800bcd2: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 800bcd6: 4c0d ldr r4, [pc, #52] @ (800bd0c ) 800bcd8: 4632 mov r2, r6 800bcda: 2101 movs r1, #1 800bcdc: e9cd 4300 strd r4, r3, [sp] 800bce0: 4643 mov r3, r8 800bce2: f002 fd15 bl 800e710 if ((hTimer == NULL) && (callb != NULL)) { 800bce6: 2800 cmp r0, #0 800bce8: d0ee beq.n 800bcc8 } 800bcea: b002 add sp, #8 800bcec: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 800bcf0: 2a00 cmp r2, #0 800bcf2: d1e9 bne.n 800bcc8 800bcf4: 4604 mov r4, r0 hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 800bcf6: 4d05 ldr r5, [pc, #20] @ (800bd0c ) 800bcf8: 4643 mov r3, r8 800bcfa: 4632 mov r2, r6 800bcfc: 4620 mov r0, r4 800bcfe: 2101 movs r1, #1 800bd00: 9500 str r5, [sp, #0] 800bd02: f002 fc9d bl 800e640 if ((hTimer == NULL) && (callb != NULL)) { 800bd06: 2800 cmp r0, #0 800bd08: d1ef bne.n 800bcea 800bd0a: e7dd b.n 800bcc8 800bd0c: 0800bb65 .word 0x0800bb65 0800bd10 : 800bd10: f3ef 8305 mrs r3, IPSR osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { TimerHandle_t hTimer = (TimerHandle_t)timer_id; osStatus_t stat; if (IS_IRQ()) { 800bd14: b973 cbnz r3, 800bd34 osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 800bd16: b510 push {r4, lr} 800bd18: b082 sub sp, #8 stat = osErrorISR; } else if (hTimer == NULL) { 800bd1a: b170 cbz r0, 800bd3a stat = osErrorParameter; } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 800bd1c: 460a mov r2, r1 800bd1e: 9300 str r3, [sp, #0] 800bd20: 2104 movs r1, #4 800bd22: f002 fd75 bl 800e810 stat = osOK; 800bd26: 2801 cmp r0, #1 800bd28: bf14 ite ne 800bd2a: f06f 0002 mvnne.w r0, #2 800bd2e: 2000 moveq r0, #0 stat = osErrorResource; } } return (stat); } 800bd30: b002 add sp, #8 800bd32: bd10 pop {r4, pc} stat = osErrorISR; 800bd34: f06f 0005 mvn.w r0, #5 } 800bd38: 4770 bx lr stat = osErrorParameter; 800bd3a: f06f 0003 mvn.w r0, #3 800bd3e: e7f7 b.n 800bd30 0800bd40 : osStatus_t osTimerStop (osTimerId_t timer_id) { 800bd40: b530 push {r4, r5, lr} 800bd42: b083 sub sp, #12 800bd44: f3ef 8505 mrs r5, IPSR TimerHandle_t hTimer = (TimerHandle_t)timer_id; osStatus_t stat; if (IS_IRQ()) { 800bd48: b9a5 cbnz r5, 800bd74 stat = osErrorISR; } else if (hTimer == NULL) { 800bd4a: 4604 mov r4, r0 800bd4c: b1a8 cbz r0, 800bd7a stat = osErrorParameter; } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 800bd4e: f002 fd95 bl 800e87c 800bd52: b160 cbz r0, 800bd6e stat = osErrorResource; } else { if (xTimerStop (hTimer, 0) == pdPASS) { 800bd54: 462b mov r3, r5 800bd56: 462a mov r2, r5 800bd58: 2103 movs r1, #3 800bd5a: 4620 mov r0, r4 800bd5c: 9500 str r5, [sp, #0] 800bd5e: f002 fd57 bl 800e810 800bd62: 3801 subs r0, #1 800bd64: bf18 it ne 800bd66: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff } } } return (stat); } 800bd6a: b003 add sp, #12 800bd6c: bd30 pop {r4, r5, pc} stat = osErrorResource; 800bd6e: f06f 0002 mvn.w r0, #2 return (stat); 800bd72: e7fa b.n 800bd6a stat = osErrorISR; 800bd74: f06f 0005 mvn.w r0, #5 800bd78: e7f7 b.n 800bd6a stat = osErrorParameter; 800bd7a: f06f 0003 mvn.w r0, #3 800bd7e: e7f4 b.n 800bd6a 0800bd80 : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 800bd80: b530 push {r4, r5, lr} 800bd82: b083 sub sp, #12 800bd84: f3ef 8505 mrs r5, IPSR const char *name; #endif hMutex = NULL; if (!IS_IRQ()) { 800bd88: b9bd cbnz r5, 800bdba if (attr != NULL) { 800bd8a: 4604 mov r4, r0 800bd8c: b1c0 cbz r0, 800bdc0 type = attr->attr_bits; 800bd8e: 6845 ldr r5, [r0, #4] rmtx = 1U; } else { rmtx = 0U; } if ((type & osMutexRobust) != osMutexRobust) { 800bd90: 072b lsls r3, r5, #28 800bd92: d412 bmi.n 800bdba mem = -1; if (attr != NULL) { if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 800bd94: 6881 ldr r1, [r0, #8] if ((type & osMutexRecursive) == osMutexRecursive) { 800bd96: f005 0501 and.w r5, r5, #1 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 800bd9a: 68c3 ldr r3, [r0, #12] 800bd9c: b309 cbz r1, 800bde2 800bd9e: 2b4f cmp r3, #79 @ 0x4f 800bda0: d90b bls.n 800bdba mem = 0; } if (mem == 1) { #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 800bda2: b345 cbz r5, 800bdf6 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 800bda4: 2004 movs r0, #4 800bda6: f000 fbf7 bl 800c598 #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 800bdaa: b130 cbz r0, 800bdba if (attr != NULL) { name = attr->name; 800bdac: 6824 ldr r4, [r4, #0] 800bdae: e00c b.n 800bdca hMutex = xSemaphoreCreateRecursiveMutex (); 800bdb0: 2004 movs r0, #4 800bdb2: f000 fc61 bl 800c678 if (hMutex != NULL) { 800bdb6: 2800 cmp r0, #0 800bdb8: d1f8 bne.n 800bdac hMutex = NULL; 800bdba: 2000 movs r0, #0 } } } return ((osMutexId_t)hMutex); } 800bdbc: b003 add sp, #12 800bdbe: bd30 pop {r4, r5, pc} hMutex = xSemaphoreCreateMutex (); 800bdc0: 2001 movs r0, #1 800bdc2: f000 fc59 bl 800c678 if (hMutex != NULL) { 800bdc6: 2800 cmp r0, #0 800bdc8: d0f7 beq.n 800bdba vQueueAddToRegistry (hMutex, name); 800bdca: 4621 mov r1, r4 800bdcc: 9001 str r0, [sp, #4] 800bdce: f001 f87f bl 800ced0 if ((hMutex != NULL) && (rmtx != 0U)) { 800bdd2: 9801 ldr r0, [sp, #4] 800bdd4: f015 0f01 tst.w r5, #1 hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 800bdd8: bf18 it ne 800bdda: f040 0001 orrne.w r0, r0, #1 } 800bdde: b003 add sp, #12 800bde0: bd30 pop {r4, r5, pc} if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 800bde2: 2b00 cmp r3, #0 800bde4: d1e9 bne.n 800bdba if (rmtx != 0U) { 800bde6: 2d00 cmp r5, #0 800bde8: d1e2 bne.n 800bdb0 hMutex = xSemaphoreCreateMutex (); 800bdea: 2001 movs r0, #1 800bdec: f000 fc44 bl 800c678 if (hMutex != NULL) { 800bdf0: 2800 cmp r0, #0 800bdf2: d1db bne.n 800bdac 800bdf4: e7e1 b.n 800bdba hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 800bdf6: 2001 movs r0, #1 800bdf8: f000 fbce bl 800c598 if (hMutex != NULL) { 800bdfc: 2800 cmp r0, #0 800bdfe: d1d5 bne.n 800bdac 800be00: e7db b.n 800bdba 800be02: bf00 nop 0800be04 : 800be04: f3ef 8205 mrs r2, IPSR rmtx = (uint32_t)mutex_id & 1U; stat = osOK; if (IS_IRQ()) { 800be08: b9d2 cbnz r2, 800be40 stat = osErrorISR; } else if (hMutex == NULL) { 800be0a: 2801 cmp r0, #1 osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 800be0c: b538 push {r3, r4, r5, lr} 800be0e: 4603 mov r3, r0 else if (hMutex == NULL) { 800be10: d919 bls.n 800be46 stat = osErrorParameter; } else { if (rmtx != 0U) { 800be12: f003 0501 and.w r5, r3, #1 800be16: 460c mov r4, r1 800be18: f020 0001 bic.w r0, r0, #1 800be1c: b955 cbnz r5, 800be34 } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 800be1e: f000 fe4f bl 800cac0 800be22: 2801 cmp r0, #1 800be24: d00a beq.n 800be3c if (timeout != 0U) { stat = osErrorTimeout; } else { stat = osErrorResource; 800be26: 2c00 cmp r4, #0 800be28: bf14 ite ne 800be2a: f06f 0001 mvnne.w r0, #1 800be2e: f06f 0002 mvneq.w r0, #2 } } } return (stat); } 800be32: bd38 pop {r3, r4, r5, pc} if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 800be34: f000 ffd0 bl 800cdd8 800be38: 2801 cmp r0, #1 800be3a: d1f4 bne.n 800be26 stat = osOK; 800be3c: 2000 movs r0, #0 } 800be3e: bd38 pop {r3, r4, r5, pc} stat = osErrorISR; 800be40: f06f 0005 mvn.w r0, #5 } 800be44: 4770 bx lr stat = osErrorParameter; 800be46: f06f 0003 mvn.w r0, #3 } 800be4a: bd38 pop {r3, r4, r5, pc} 0800be4c : 800be4c: f3ef 8105 mrs r1, IPSR rmtx = (uint32_t)mutex_id & 1U; stat = osOK; if (IS_IRQ()) { 800be50: b9b9 cbnz r1, 800be82 stat = osErrorISR; } else if (hMutex == NULL) { 800be52: 2801 cmp r0, #1 800be54: 4602 mov r2, r0 800be56: d917 bls.n 800be88 stat = osErrorParameter; } else { if (rmtx != 0U) { 800be58: f020 0001 bic.w r0, r0, #1 osStatus_t osMutexRelease (osMutexId_t mutex_id) { 800be5c: b508 push {r3, lr} 800be5e: f002 0301 and.w r3, r2, #1 if (rmtx != 0U) { 800be62: b93b cbnz r3, 800be74 stat = osErrorResource; } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 800be64: 461a mov r2, r3 800be66: 4619 mov r1, r3 800be68: f000 fa14 bl 800c294 800be6c: 2801 cmp r0, #1 800be6e: d105 bne.n 800be7c stat = osOK; 800be70: 2000 movs r0, #0 } } } return (stat); } 800be72: bd08 pop {r3, pc} if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 800be74: f000 fbe0 bl 800c638 800be78: 2801 cmp r0, #1 800be7a: d0f9 beq.n 800be70 stat = osErrorResource; 800be7c: f06f 0002 mvn.w r0, #2 } 800be80: bd08 pop {r3, pc} stat = osErrorISR; 800be82: f06f 0005 mvn.w r0, #5 800be86: 4770 bx lr stat = osErrorParameter; 800be88: f06f 0003 mvn.w r0, #3 } 800be8c: 4770 bx lr 800be8e: bf00 nop 0800be90 : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 800be90: b5f0 push {r4, r5, r6, r7, lr} 800be92: b083 sub sp, #12 800be94: f3ef 8705 mrs r7, IPSR const char *name; #endif hQueue = NULL; if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 800be98: b987 cbnz r7, 800bebc 800be9a: 4605 mov r5, r0 800be9c: b170 cbz r0, 800bebc 800be9e: b169 cbz r1, 800bebc mem = -1; if (attr != NULL) { 800bea0: 4614 mov r4, r2 800bea2: b17a cbz r2, 800bec4 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 800bea4: e9d2 3202 ldrd r3, r2, [r2, #8] 800bea8: b1c3 cbz r3, 800bedc 800beaa: 2a4f cmp r2, #79 @ 0x4f 800beac: d906 bls.n 800bebc (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 800beae: 6922 ldr r2, [r4, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 800beb0: b122 cbz r2, 800bebc (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 800beb2: fb01 f505 mul.w r5, r1, r5 800beb6: 6966 ldr r6, [r4, #20] 800beb8: 42ae cmp r6, r5 800beba: d21e bcs.n 800befa hQueue = NULL; 800bebc: 2500 movs r5, #0 #endif } return ((osMessageQueueId_t)hQueue); } 800bebe: 4628 mov r0, r5 800bec0: b003 add sp, #12 800bec2: bdf0 pop {r4, r5, r6, r7, pc} hQueue = xQueueCreate (msg_count, msg_size); 800bec4: f000 f9a4 bl 800c210 if (hQueue != NULL) { 800bec8: 4605 mov r5, r0 800beca: 2800 cmp r0, #0 800becc: d0f6 beq.n 800bebc vQueueAddToRegistry (hQueue, name); 800bece: 4628 mov r0, r5 800bed0: 4621 mov r1, r4 800bed2: f000 fffd bl 800ced0 } 800bed6: 4628 mov r0, r5 800bed8: b003 add sp, #12 800beda: bdf0 pop {r4, r5, r6, r7, pc} if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 800bedc: 2a00 cmp r2, #0 800bede: d1ed bne.n 800bebc 800bee0: 6923 ldr r3, [r4, #16] 800bee2: 2b00 cmp r3, #0 800bee4: d1ea bne.n 800bebc (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 800bee6: 6962 ldr r2, [r4, #20] 800bee8: 2a00 cmp r2, #0 800beea: d1e7 bne.n 800bebc hQueue = xQueueCreate (msg_count, msg_size); 800beec: f000 f990 bl 800c210 if (hQueue != NULL) { 800bef0: 4605 mov r5, r0 800bef2: 2800 cmp r0, #0 800bef4: d0e2 beq.n 800bebc name = attr->name; 800bef6: 6824 ldr r4, [r4, #0] 800bef8: e7e9 b.n 800bece hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 800befa: 9700 str r7, [sp, #0] 800befc: f000 f91c bl 800c138 if (hQueue != NULL) { 800bf00: 4605 mov r5, r0 800bf02: 2800 cmp r0, #0 800bf04: d1f7 bne.n 800bef6 800bf06: e7d9 b.n 800bebc 0800bf08 : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 800bf08: b560 push {r5, r6, lr} 800bf0a: 461e mov r6, r3 800bf0c: b083 sub sp, #12 800bf0e: f3ef 8205 mrs r2, IPSR (void)msg_prio; /* Message priority is ignored */ stat = osOK; if (IS_IRQ()) { if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 800bf12: fab0 f580 clz r5, r0 800bf16: fab1 f381 clz r3, r1 800bf1a: 096d lsrs r5, r5, #5 800bf1c: 095b lsrs r3, r3, #5 if (IS_IRQ()) { 800bf1e: b1da cbz r2, 800bf58 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 800bf20: 2e00 cmp r6, #0 800bf22: bf18 it ne 800bf24: f043 0301 orrne.w r3, r3, #1 800bf28: bb33 cbnz r3, 800bf78 800bf2a: bb2d cbnz r5, 800bf78 stat = osErrorParameter; } else { yield = pdFALSE; if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 800bf2c: 462b mov r3, r5 800bf2e: aa01 add r2, sp, #4 yield = pdFALSE; 800bf30: 9501 str r5, [sp, #4] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 800bf32: f000 fbd9 bl 800c6e8 800bf36: 2801 cmp r0, #1 800bf38: d11a bne.n 800bf70 stat = osErrorResource; } else { portYIELD_FROM_ISR (yield); 800bf3a: 9b01 ldr r3, [sp, #4] 800bf3c: b14b cbz r3, 800bf52 800bf3e: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800bf42: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800bf46: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800bf4a: f3bf 8f4f dsb sy 800bf4e: f3bf 8f6f isb sy stat = osOK; 800bf52: 2000 movs r0, #0 } } } return (stat); } 800bf54: b003 add sp, #12 800bf56: bd60 pop {r5, r6, pc} if ((hQueue == NULL) || (msg_ptr == NULL)) { 800bf58: b975 cbnz r5, 800bf78 800bf5a: b96b cbnz r3, 800bf78 if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 800bf5c: 4632 mov r2, r6 800bf5e: f000 f999 bl 800c294 800bf62: 2801 cmp r0, #1 800bf64: d0f5 beq.n 800bf52 if (timeout != 0U) { 800bf66: b11e cbz r6, 800bf70 stat = osErrorTimeout; 800bf68: f06f 0001 mvn.w r0, #1 } 800bf6c: b003 add sp, #12 800bf6e: bd60 pop {r5, r6, pc} stat = osErrorResource; 800bf70: f06f 0002 mvn.w r0, #2 } 800bf74: b003 add sp, #12 800bf76: bd60 pop {r5, r6, pc} stat = osErrorParameter; 800bf78: f06f 0003 mvn.w r0, #3 return (stat); 800bf7c: e7ea b.n 800bf54 800bf7e: bf00 nop 0800bf80 : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 800bf80: b570 push {r4, r5, r6, lr} 800bf82: 461e mov r6, r3 800bf84: b082 sub sp, #8 800bf86: f3ef 8305 mrs r3, IPSR (void)msg_prio; /* Message priority is ignored */ stat = osOK; if (IS_IRQ()) { if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 800bf8a: fab0 f580 clz r5, r0 800bf8e: fab1 f481 clz r4, r1 800bf92: 096d lsrs r5, r5, #5 800bf94: 0964 lsrs r4, r4, #5 if (IS_IRQ()) { 800bf96: b1d3 cbz r3, 800bfce if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 800bf98: 2e00 cmp r6, #0 800bf9a: bf18 it ne 800bf9c: f044 0401 orrne.w r4, r4, #1 800bfa0: bb2c cbnz r4, 800bfee 800bfa2: bb25 cbnz r5, 800bfee stat = osErrorParameter; } else { yield = pdFALSE; if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 800bfa4: aa01 add r2, sp, #4 yield = pdFALSE; 800bfa6: 9501 str r5, [sp, #4] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 800bfa8: f000 ff36 bl 800ce18 800bfac: 2801 cmp r0, #1 800bfae: d11a bne.n 800bfe6 stat = osErrorResource; } else { portYIELD_FROM_ISR (yield); 800bfb0: 9b01 ldr r3, [sp, #4] 800bfb2: b14b cbz r3, 800bfc8 800bfb4: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800bfb8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800bfbc: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800bfc0: f3bf 8f4f dsb sy 800bfc4: f3bf 8f6f isb sy stat = osOK; 800bfc8: 2000 movs r0, #0 } } } return (stat); } 800bfca: b002 add sp, #8 800bfcc: bd70 pop {r4, r5, r6, pc} if ((hQueue == NULL) || (msg_ptr == NULL)) { 800bfce: b975 cbnz r5, 800bfee 800bfd0: b96c cbnz r4, 800bfee if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 800bfd2: 4632 mov r2, r6 800bfd4: f000 fbee bl 800c7b4 800bfd8: 2801 cmp r0, #1 800bfda: d0f5 beq.n 800bfc8 if (timeout != 0U) { 800bfdc: b11e cbz r6, 800bfe6 stat = osErrorTimeout; 800bfde: f06f 0001 mvn.w r0, #1 } 800bfe2: b002 add sp, #8 800bfe4: bd70 pop {r4, r5, r6, pc} stat = osErrorResource; 800bfe6: f06f 0002 mvn.w r0, #2 } 800bfea: b002 add sp, #8 800bfec: bd70 pop {r4, r5, r6, pc} stat = osErrorParameter; 800bfee: f06f 0003 mvn.w r0, #3 return (stat); 800bff2: e7ea b.n 800bfca 0800bff4 : __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 800bff4: 4b05 ldr r3, [pc, #20] @ (800c00c ) __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 800bff6: b410 push {r4} *ppxIdleTaskTCBBuffer = &Idle_TCB; 800bff8: 6003 str r3, [r0, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 800bffa: f44f 7300 mov.w r3, #512 @ 0x200 *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 800bffe: 4c04 ldr r4, [pc, #16] @ (800c010 ) 800c000: 600c str r4, [r1, #0] } 800c002: f85d 4b04 ldr.w r4, [sp], #4 *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 800c006: 6013 str r3, [r2, #0] } 800c008: 4770 bx lr 800c00a: bf00 nop 800c00c: 24002a58 .word 0x24002a58 800c010: 24002258 .word 0x24002258 0800c014 : __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 800c014: 4b05 ldr r3, [pc, #20] @ (800c02c ) __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 800c016: b410 push {r4} *ppxTimerTaskTCBBuffer = &Timer_TCB; 800c018: 6003 str r3, [r0, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 800c01a: f44f 6380 mov.w r3, #1024 @ 0x400 *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 800c01e: 4c04 ldr r4, [pc, #16] @ (800c030 ) 800c020: 600c str r4, [r1, #0] } 800c022: f85d 4b04 ldr.w r4, [sp], #4 *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 800c026: 6013 str r3, [r2, #0] } 800c028: 4770 bx lr 800c02a: bf00 nop 800c02c: 240021b0 .word 0x240021b0 800c030: 240011b0 .word 0x240011b0 0800c034 : void vListInitialise( List_t * const pxList ) { /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 800c034: f100 0308 add.w r3, r0, #8 /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 800c038: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 800c03c: 2200 movs r2, #0 pxList->xListEnd.xItemValue = portMAX_DELAY; 800c03e: 6081 str r1, [r0, #8] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 800c040: 6002 str r2, [r0, #0] pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 800c042: 6043 str r3, [r0, #4] pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 800c044: e9c0 3303 strd r3, r3, [r0, #12] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 800c048: 4770 bx lr 800c04a: bf00 nop 0800c04c : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 800c04c: 2300 movs r3, #0 800c04e: 6103 str r3, [r0, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 800c050: 4770 bx lr 800c052: bf00 nop 0800c054 : pxIndex->pxPrevious = pxNewListItem; /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; ( pxList->uxNumberOfItems )++; 800c054: 6803 ldr r3, [r0, #0] ListItem_t * const pxIndex = pxList->pxIndex; 800c056: 6842 ldr r2, [r0, #4] ( pxList->uxNumberOfItems )++; 800c058: 3301 adds r3, #1 { 800c05a: b410 push {r4} pxNewListItem->pxPrevious = pxIndex->pxPrevious; 800c05c: 6894 ldr r4, [r2, #8] 800c05e: e9c1 2401 strd r2, r4, [r1, #4] pxIndex->pxPrevious->pxNext = pxNewListItem; 800c062: 6061 str r1, [r4, #4] pxIndex->pxPrevious = pxNewListItem; 800c064: 6091 str r1, [r2, #8] } 800c066: f85d 4b04 ldr.w r4, [sp], #4 pxNewListItem->pxContainer = pxList; 800c06a: 6108 str r0, [r1, #16] ( pxList->uxNumberOfItems )++; 800c06c: 6003 str r3, [r0, #0] } 800c06e: 4770 bx lr 0800c070 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 800c070: b430 push {r4, r5} ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 800c072: 680d ldr r5, [r1, #0] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 800c074: 1c6b adds r3, r5, #1 800c076: d010 beq.n 800c09a 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 800c078: f100 0308 add.w r3, r0, #8 800c07c: 461c mov r4, r3 800c07e: 685b ldr r3, [r3, #4] 800c080: 681a ldr r2, [r3, #0] 800c082: 42aa cmp r2, r5 800c084: d9fa bls.n 800c07c /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; ( pxList->uxNumberOfItems )++; 800c086: 6802 ldr r2, [r0, #0] pxNewListItem->pxNext = pxIterator->pxNext; 800c088: 604b str r3, [r1, #4] ( pxList->uxNumberOfItems )++; 800c08a: 3201 adds r2, #1 pxNewListItem->pxNext->pxPrevious = pxNewListItem; 800c08c: 6099 str r1, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 800c08e: 608c str r4, [r1, #8] pxIterator->pxNext = pxNewListItem; 800c090: 6061 str r1, [r4, #4] pxNewListItem->pxContainer = pxList; 800c092: 6108 str r0, [r1, #16] ( pxList->uxNumberOfItems )++; 800c094: 6002 str r2, [r0, #0] } 800c096: bc30 pop {r4, r5} 800c098: 4770 bx lr pxIterator = pxList->xListEnd.pxPrevious; 800c09a: 6904 ldr r4, [r0, #16] pxNewListItem->pxNext = pxIterator->pxNext; 800c09c: 6863 ldr r3, [r4, #4] 800c09e: e7f2 b.n 800c086 0800c0a0 : UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 800c0a0: 6903 ldr r3, [r0, #16] { 800c0a2: b410 push {r4} /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 800c0a4: 685c ldr r4, [r3, #4] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 800c0a6: e9d0 1201 ldrd r1, r2, [r0, #4] if( pxList->pxIndex == pxItemToRemove ) 800c0aa: 4284 cmp r4, r0 pxItemToRemove->pxContainer = NULL; ( pxList->uxNumberOfItems )--; return pxList->uxNumberOfItems; } 800c0ac: f85d 4b04 ldr.w r4, [sp], #4 pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 800c0b0: 608a str r2, [r1, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 800c0b2: 6051 str r1, [r2, #4] pxItemToRemove->pxContainer = NULL; 800c0b4: f04f 0100 mov.w r1, #0 pxList->pxIndex = pxItemToRemove->pxPrevious; 800c0b8: bf08 it eq 800c0ba: 605a streq r2, [r3, #4] ( pxList->uxNumberOfItems )--; 800c0bc: 681a ldr r2, [r3, #0] pxItemToRemove->pxContainer = NULL; 800c0be: 6101 str r1, [r0, #16] ( pxList->uxNumberOfItems )--; 800c0c0: 3a01 subs r2, #1 800c0c2: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 800c0c4: 6818 ldr r0, [r3, #0] } 800c0c6: 4770 bx lr 0800c0c8 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 800c0c8: b570 push {r4, r5, r6, lr} 800c0ca: 4616 mov r6, r2 /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 800c0cc: 6c02 ldr r2, [r0, #64] @ 0x40 { 800c0ce: 4604 mov r4, r0 uxMessagesWaiting = pxQueue->uxMessagesWaiting; 800c0d0: 6b85 ldr r5, [r0, #56] @ 0x38 if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 800c0d2: b92a cbnz r2, 800c0e0 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 800c0d4: 6806 ldr r6, [r0, #0] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 800c0d6: 3501 adds r5, #1 if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 800c0d8: b34e cbz r6, 800c12e BaseType_t xReturn = pdFALSE; 800c0da: 4610 mov r0, r2 pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 800c0dc: 63a5 str r5, [r4, #56] @ 0x38 return xReturn; } 800c0de: bd70 pop {r4, r5, r6, pc} else if( xPosition == queueSEND_TO_BACK ) 800c0e0: b97e cbnz r6, 800c102 ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 800c0e2: 6840 ldr r0, [r0, #4] 800c0e4: f003 fde5 bl 800fcb2 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800c0e8: 6863 ldr r3, [r4, #4] 800c0ea: 6c21 ldr r1, [r4, #64] @ 0x40 if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 800c0ec: 68a2 ldr r2, [r4, #8] pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800c0ee: 440b add r3, r1 if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 800c0f0: 4293 cmp r3, r2 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800c0f2: 6063 str r3, [r4, #4] pxQueue->pcWriteTo = pxQueue->pcHead; 800c0f4: bf24 itt cs 800c0f6: 6823 ldrcs r3, [r4, #0] 800c0f8: 6063 strcs r3, [r4, #4] pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 800c0fa: 3501 adds r5, #1 BaseType_t xReturn = pdFALSE; 800c0fc: 2000 movs r0, #0 pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 800c0fe: 63a5 str r5, [r4, #56] @ 0x38 } 800c100: bd70 pop {r4, r5, r6, pc} ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 800c102: 68c0 ldr r0, [r0, #12] 800c104: f003 fdd5 bl 800fcb2 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 800c108: 6c22 ldr r2, [r4, #64] @ 0x40 800c10a: 68e3 ldr r3, [r4, #12] 800c10c: 4251 negs r1, r2 800c10e: 1a9b subs r3, r3, r2 if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 800c110: 6822 ldr r2, [r4, #0] 800c112: 4293 cmp r3, r2 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 800c114: 60e3 str r3, [r4, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 800c116: d202 bcs.n 800c11e pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 800c118: 68a3 ldr r3, [r4, #8] 800c11a: 440b add r3, r1 800c11c: 60e3 str r3, [r4, #12] if( xPosition == queueOVERWRITE ) 800c11e: 2e02 cmp r6, #2 800c120: d1eb bne.n 800c0fa if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 800c122: 2d01 cmp r5, #1 BaseType_t xReturn = pdFALSE; 800c124: f04f 0000 mov.w r0, #0 800c128: bf38 it cc 800c12a: 2501 movcc r5, #1 800c12c: e7d6 b.n 800c0dc xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 800c12e: 6880 ldr r0, [r0, #8] 800c130: f001 fe4e bl 800ddd0 pxQueue->u.xSemaphore.xMutexHolder = NULL; 800c134: 60a6 str r6, [r4, #8] 800c136: e7d1 b.n 800c0dc 0800c138 : { 800c138: b530 push {r4, r5, lr} 800c13a: b083 sub sp, #12 800c13c: f89d 5018 ldrb.w r5, [sp, #24] configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 800c140: b940 cbnz r0, 800c154 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 800c142: f04f 0350 mov.w r3, #80 @ 0x50 800c146: f383 8811 msr BASEPRI, r3 800c14a: f3bf 8f6f isb sy 800c14e: f3bf 8f4f dsb sy 800c152: e7fe b.n 800c152 configASSERT( pxStaticQueue != NULL ); 800c154: 461c mov r4, r3 800c156: b153 cbz r3, 800c16e configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 800c158: b30a cbz r2, 800c19e 800c15a: b989 cbnz r1, 800c180 800c15c: f04f 0350 mov.w r3, #80 @ 0x50 800c160: f383 8811 msr BASEPRI, r3 800c164: f3bf 8f6f isb sy 800c168: f3bf 8f4f dsb sy 800c16c: e7fe b.n 800c16c 800c16e: f04f 0350 mov.w r3, #80 @ 0x50 800c172: f383 8811 msr BASEPRI, r3 800c176: f3bf 8f6f isb sy 800c17a: f3bf 8f4f dsb sy configASSERT( pxStaticQueue != NULL ); 800c17e: e7fe b.n 800c17e configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 800c180: b16a cbz r2, 800c19e volatile size_t xSize = sizeof( StaticQueue_t ); 800c182: 2350 movs r3, #80 @ 0x50 800c184: 9301 str r3, [sp, #4] configASSERT( xSize == sizeof( Queue_t ) ); 800c186: 9b01 ldr r3, [sp, #4] 800c188: 2b50 cmp r3, #80 @ 0x50 800c18a: d013 beq.n 800c1b4 800c18c: f04f 0350 mov.w r3, #80 @ 0x50 800c190: f383 8811 msr BASEPRI, r3 800c194: f3bf 8f6f isb sy 800c198: f3bf 8f4f dsb sy 800c19c: e7fe b.n 800c19c configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 800c19e: 2900 cmp r1, #0 800c1a0: d0ef beq.n 800c182 800c1a2: f04f 0350 mov.w r3, #80 @ 0x50 800c1a6: f383 8811 msr BASEPRI, r3 800c1aa: f3bf 8f6f isb sy 800c1ae: f3bf 8f4f dsb sy 800c1b2: e7fe b.n 800c1b2 pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 800c1b4: 2900 cmp r1, #0 800c1b6: bf08 it eq 800c1b8: 4622 moveq r2, r4 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 800c1ba: 9b01 ldr r3, [sp, #4] pxNewQueue->ucStaticallyAllocated = pdTRUE; 800c1bc: 2301 movs r3, #1 pxNewQueue->uxLength = uxQueueLength; 800c1be: 63e0 str r0, [r4, #60] @ 0x3c 800c1c0: 6022 str r2, [r4, #0] pxNewQueue->uxItemSize = uxItemSize; 800c1c2: 6421 str r1, [r4, #64] @ 0x40 pxNewQueue->ucStaticallyAllocated = pdTRUE; 800c1c4: f884 3046 strb.w r3, [r4, #70] @ 0x46 taskENTER_CRITICAL(); 800c1c8: f002 fbec bl 800e9a4 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c1cc: 6822 ldr r2, [r4, #0] vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800c1ce: f104 0010 add.w r0, r4, #16 pxQueue->pcWriteTo = pxQueue->pcHead; 800c1d2: 6062 str r2, [r4, #4] pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c1d4: e9d4 310f ldrd r3, r1, [r4, #60] @ 0x3c 800c1d8: fb01 f303 mul.w r3, r1, r3 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c1dc: 1a59 subs r1, r3, r1 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c1de: 4413 add r3, r2 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c1e0: 440a add r2, r1 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c1e2: 60a3 str r3, [r4, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 800c1e4: 2100 movs r1, #0 pxQueue->cRxLock = queueUNLOCKED; 800c1e6: 23ff movs r3, #255 @ 0xff pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c1e8: 60e2 str r2, [r4, #12] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 800c1ea: 63a1 str r1, [r4, #56] @ 0x38 pxQueue->cRxLock = queueUNLOCKED; 800c1ec: f884 3044 strb.w r3, [r4, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 800c1f0: f884 3045 strb.w r3, [r4, #69] @ 0x45 vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800c1f4: f7ff ff1e bl 800c034 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 800c1f8: f104 0024 add.w r0, r4, #36 @ 0x24 800c1fc: f7ff ff1a bl 800c034 taskEXIT_CRITICAL(); 800c200: f002 fbf2 bl 800e9e8 } 800c204: 4620 mov r0, r4 pxNewQueue->ucQueueType = ucQueueType; 800c206: f884 504c strb.w r5, [r4, #76] @ 0x4c } 800c20a: b003 add sp, #12 800c20c: bd30 pop {r4, r5, pc} 800c20e: bf00 nop 0800c210 : { 800c210: b5f8 push {r3, r4, r5, r6, r7, lr} configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 800c212: b940 cbnz r0, 800c226 800c214: f04f 0350 mov.w r3, #80 @ 0x50 800c218: f383 8811 msr BASEPRI, r3 800c21c: f3bf 8f6f isb sy 800c220: f3bf 8f4f dsb sy 800c224: e7fe b.n 800c224 800c226: 4605 mov r5, r0 xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800c228: fb01 f000 mul.w r0, r1, r0 800c22c: 460e mov r6, r1 800c22e: 4617 mov r7, r2 pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 800c230: 3050 adds r0, #80 @ 0x50 800c232: f002 fd17 bl 800ec64 if( pxNewQueue != NULL ) 800c236: 4604 mov r4, r0 800c238: b340 cbz r0, 800c28c pxNewQueue->ucStaticallyAllocated = pdFALSE; 800c23a: 2300 movs r3, #0 800c23c: f880 3046 strb.w r3, [r0, #70] @ 0x46 if( uxItemSize == ( UBaseType_t ) 0 ) 800c240: b336 cbz r6, 800c290 pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c242: f100 0350 add.w r3, r0, #80 @ 0x50 pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 800c246: 6023 str r3, [r4, #0] pxNewQueue->uxItemSize = uxItemSize; 800c248: e9c4 560f strd r5, r6, [r4, #60] @ 0x3c taskENTER_CRITICAL(); 800c24c: f002 fbaa bl 800e9a4 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c250: 6822 ldr r2, [r4, #0] vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800c252: f104 0010 add.w r0, r4, #16 pxQueue->pcWriteTo = pxQueue->pcHead; 800c256: 6062 str r2, [r4, #4] pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c258: e9d4 310f ldrd r3, r1, [r4, #60] @ 0x3c 800c25c: fb01 f303 mul.w r3, r1, r3 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c260: 1a59 subs r1, r3, r1 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c262: 4413 add r3, r2 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c264: 440a add r2, r1 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c266: 60a3 str r3, [r4, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 800c268: 2100 movs r1, #0 pxQueue->cRxLock = queueUNLOCKED; 800c26a: 23ff movs r3, #255 @ 0xff pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c26c: 60e2 str r2, [r4, #12] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 800c26e: 63a1 str r1, [r4, #56] @ 0x38 pxQueue->cRxLock = queueUNLOCKED; 800c270: f884 3044 strb.w r3, [r4, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 800c274: f884 3045 strb.w r3, [r4, #69] @ 0x45 vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800c278: f7ff fedc bl 800c034 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 800c27c: f104 0024 add.w r0, r4, #36 @ 0x24 800c280: f7ff fed8 bl 800c034 taskEXIT_CRITICAL(); 800c284: f002 fbb0 bl 800e9e8 pxNewQueue->ucQueueType = ucQueueType; 800c288: f884 704c strb.w r7, [r4, #76] @ 0x4c } 800c28c: 4620 mov r0, r4 800c28e: bdf8 pop {r3, r4, r5, r6, r7, pc} pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 800c290: 4603 mov r3, r0 800c292: e7d8 b.n 800c246 0800c294 : { 800c294: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800c298: b084 sub sp, #16 800c29a: 9201 str r2, [sp, #4] configASSERT( pxQueue ); 800c29c: 2800 cmp r0, #0 800c29e: f000 8103 beq.w 800c4a8 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800c2a2: 4688 mov r8, r1 800c2a4: 4604 mov r4, r0 800c2a6: 461f mov r7, r3 800c2a8: 2900 cmp r1, #0 800c2aa: f000 8097 beq.w 800c3dc configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 800c2ae: 2f02 cmp r7, #2 800c2b0: d10b bne.n 800c2ca 800c2b2: 6be3 ldr r3, [r4, #60] @ 0x3c 800c2b4: 2b01 cmp r3, #1 800c2b6: d008 beq.n 800c2ca 800c2b8: f04f 0350 mov.w r3, #80 @ 0x50 800c2bc: f383 8811 msr BASEPRI, r3 800c2c0: f3bf 8f6f isb sy 800c2c4: f3bf 8f4f dsb sy 800c2c8: e7fe b.n 800c2c8 configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800c2ca: f001 fd31 bl 800dd30 800c2ce: 2800 cmp r0, #0 800c2d0: f000 80f3 beq.w 800c4ba if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 800c2d4: f1a7 0902 sub.w r9, r7, #2 800c2d8: 2500 movs r5, #0 { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c2da: f104 0624 add.w r6, r4, #36 @ 0x24 if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 800c2de: fab9 f989 clz r9, r9 800c2e2: ea4f 1959 mov.w r9, r9, lsr #5 taskENTER_CRITICAL(); 800c2e6: f002 fb5d bl 800e9a4 if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 800c2ea: 6ba2 ldr r2, [r4, #56] @ 0x38 800c2ec: 6be3 ldr r3, [r4, #60] @ 0x3c 800c2ee: 429a cmp r2, r3 800c2f0: f0c0 80f0 bcc.w 800c4d4 800c2f4: f1b9 0f00 cmp.w r9, #0 800c2f8: f040 80ec bne.w 800c4d4 if( xTicksToWait == ( TickType_t ) 0 ) 800c2fc: 9b01 ldr r3, [sp, #4] 800c2fe: 2b00 cmp r3, #0 800c300: f000 8101 beq.w 800c506 else if( xEntryTimeSet == pdFALSE ) 800c304: 2d00 cmp r5, #0 800c306: f000 80cb beq.w 800c4a0 taskEXIT_CRITICAL(); 800c30a: f002 fb6d bl 800e9e8 vTaskSuspendAll(); 800c30e: f001 fb41 bl 800d994 prvLockQueue( pxQueue ); 800c312: f002 fb47 bl 800e9a4 800c316: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800c31a: 2bff cmp r3, #255 @ 0xff 800c31c: d102 bne.n 800c324 800c31e: 2300 movs r3, #0 800c320: f884 3044 strb.w r3, [r4, #68] @ 0x44 800c324: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800c328: 2bff cmp r3, #255 @ 0xff 800c32a: d102 bne.n 800c332 800c32c: 2300 movs r3, #0 800c32e: f884 3045 strb.w r3, [r4, #69] @ 0x45 800c332: f002 fb59 bl 800e9e8 if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 800c336: a901 add r1, sp, #4 800c338: a802 add r0, sp, #8 800c33a: f001 fcab bl 800dc94 800c33e: 2800 cmp r0, #0 800c340: f040 80e5 bne.w 800c50e static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { BaseType_t xReturn; taskENTER_CRITICAL(); 800c344: f002 fb2e bl 800e9a4 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 800c348: 6ba2 ldr r2, [r4, #56] @ 0x38 800c34a: 6be3 ldr r3, [r4, #60] @ 0x3c 800c34c: 429a cmp r2, r3 800c34e: d052 beq.n 800c3f6 else { xReturn = pdFALSE; } } taskEXIT_CRITICAL(); 800c350: f002 fb4a bl 800e9e8 taskENTER_CRITICAL(); 800c354: f002 fb26 bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800c358: f894 2045 ldrb.w r2, [r4, #69] @ 0x45 800c35c: b255 sxtb r5, r2 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c35e: 2d00 cmp r5, #0 800c360: dc04 bgt.n 800c36c 800c362: e011 b.n 800c388 --cTxLock; 800c364: 1e6a subs r2, r5, #1 800c366: b2d3 uxtb r3, r2 800c368: b255 sxtb r5, r2 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c36a: b16b cbz r3, 800c388 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c36c: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c36e: 4630 mov r0, r6 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c370: b153 cbz r3, 800c388 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c372: f001 fc21 bl 800dbb8 800c376: 2800 cmp r0, #0 800c378: d0f4 beq.n 800c364 vTaskMissedYield(); 800c37a: f001 fccd bl 800dd18 --cTxLock; 800c37e: 1e6a subs r2, r5, #1 800c380: b2d3 uxtb r3, r2 800c382: b255 sxtb r5, r2 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c384: 2b00 cmp r3, #0 800c386: d1f1 bne.n 800c36c pxQueue->cTxLock = queueUNLOCKED; 800c388: 23ff movs r3, #255 @ 0xff 800c38a: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800c38e: f002 fb2b bl 800e9e8 taskENTER_CRITICAL(); 800c392: f002 fb07 bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800c396: f894 2044 ldrb.w r2, [r4, #68] @ 0x44 800c39a: b255 sxtb r5, r2 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c39c: 2d00 cmp r5, #0 800c39e: dd14 ble.n 800c3ca if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c3a0: f104 0a10 add.w sl, r4, #16 800c3a4: e003 b.n 800c3ae --cRxLock; 800c3a6: 1e6a subs r2, r5, #1 800c3a8: b2d3 uxtb r3, r2 800c3aa: b255 sxtb r5, r2 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c3ac: b16b cbz r3, 800c3ca if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c3ae: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c3b0: 4650 mov r0, sl if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c3b2: b153 cbz r3, 800c3ca if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c3b4: f001 fc00 bl 800dbb8 800c3b8: 2800 cmp r0, #0 800c3ba: d0f4 beq.n 800c3a6 vTaskMissedYield(); 800c3bc: f001 fcac bl 800dd18 --cRxLock; 800c3c0: 1e6a subs r2, r5, #1 800c3c2: b2d3 uxtb r3, r2 800c3c4: b255 sxtb r5, r2 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c3c6: 2b00 cmp r3, #0 800c3c8: d1f1 bne.n 800c3ae pxQueue->cRxLock = queueUNLOCKED; 800c3ca: 23ff movs r3, #255 @ 0xff 800c3cc: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800c3d0: f002 fb0a bl 800e9e8 ( void ) xTaskResumeAll(); 800c3d4: f001 fae6 bl 800d9a4 if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 800c3d8: 2501 movs r5, #1 800c3da: e784 b.n 800c2e6 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800c3dc: 6c03 ldr r3, [r0, #64] @ 0x40 800c3de: 2b00 cmp r3, #0 800c3e0: f43f af65 beq.w 800c2ae 800c3e4: f04f 0350 mov.w r3, #80 @ 0x50 800c3e8: f383 8811 msr BASEPRI, r3 800c3ec: f3bf 8f6f isb sy 800c3f0: f3bf 8f4f dsb sy 800c3f4: e7fe b.n 800c3f4 vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 800c3f6: f104 0a10 add.w sl, r4, #16 taskEXIT_CRITICAL(); 800c3fa: f002 faf5 bl 800e9e8 vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 800c3fe: 9901 ldr r1, [sp, #4] 800c400: 4650 mov r0, sl 800c402: f001 fb4b bl 800da9c taskENTER_CRITICAL(); 800c406: f002 facd bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800c40a: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800c40e: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c410: 2d00 cmp r5, #0 800c412: dc04 bgt.n 800c41e 800c414: e011 b.n 800c43a --cTxLock; 800c416: 1e6b subs r3, r5, #1 800c418: b2da uxtb r2, r3 800c41a: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c41c: b16a cbz r2, 800c43a if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c41e: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c420: 4630 mov r0, r6 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c422: b153 cbz r3, 800c43a if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c424: f001 fbc8 bl 800dbb8 800c428: 2800 cmp r0, #0 800c42a: d0f4 beq.n 800c416 vTaskMissedYield(); 800c42c: f001 fc74 bl 800dd18 --cTxLock; 800c430: 1e6b subs r3, r5, #1 800c432: b2da uxtb r2, r3 800c434: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c436: 2a00 cmp r2, #0 800c438: d1f1 bne.n 800c41e pxQueue->cTxLock = queueUNLOCKED; 800c43a: 23ff movs r3, #255 @ 0xff 800c43c: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800c440: f002 fad2 bl 800e9e8 taskENTER_CRITICAL(); 800c444: f002 faae bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800c448: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800c44c: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c44e: 2d00 cmp r5, #0 800c450: dc04 bgt.n 800c45c 800c452: e011 b.n 800c478 --cRxLock; 800c454: 1e6b subs r3, r5, #1 800c456: b2da uxtb r2, r3 800c458: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c45a: b16a cbz r2, 800c478 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c45c: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c45e: 4650 mov r0, sl if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c460: b153 cbz r3, 800c478 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c462: f001 fba9 bl 800dbb8 800c466: 2800 cmp r0, #0 800c468: d0f4 beq.n 800c454 vTaskMissedYield(); 800c46a: f001 fc55 bl 800dd18 --cRxLock; 800c46e: 1e6b subs r3, r5, #1 800c470: b2da uxtb r2, r3 800c472: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c474: 2a00 cmp r2, #0 800c476: d1f1 bne.n 800c45c pxQueue->cRxLock = queueUNLOCKED; 800c478: 23ff movs r3, #255 @ 0xff 800c47a: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800c47e: f002 fab3 bl 800e9e8 if( xTaskResumeAll() == pdFALSE ) 800c482: f001 fa8f bl 800d9a4 800c486: 2800 cmp r0, #0 800c488: d1a6 bne.n 800c3d8 portYIELD_WITHIN_API(); 800c48a: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800c48e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800c492: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800c496: f3bf 8f4f dsb sy 800c49a: f3bf 8f6f isb sy 800c49e: e79b b.n 800c3d8 vTaskInternalSetTimeOutState( &xTimeOut ); 800c4a0: a802 add r0, sp, #8 800c4a2: f001 fbeb bl 800dc7c xEntryTimeSet = pdTRUE; 800c4a6: e730 b.n 800c30a 800c4a8: f04f 0350 mov.w r3, #80 @ 0x50 800c4ac: f383 8811 msr BASEPRI, r3 800c4b0: f3bf 8f6f isb sy 800c4b4: f3bf 8f4f dsb sy configASSERT( pxQueue ); 800c4b8: e7fe b.n 800c4b8 configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800c4ba: 9b01 ldr r3, [sp, #4] 800c4bc: 2b00 cmp r3, #0 800c4be: f43f af09 beq.w 800c2d4 800c4c2: f04f 0350 mov.w r3, #80 @ 0x50 800c4c6: f383 8811 msr BASEPRI, r3 800c4ca: f3bf 8f6f isb sy 800c4ce: f3bf 8f4f dsb sy 800c4d2: e7fe b.n 800c4d2 xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 800c4d4: 463a mov r2, r7 800c4d6: 4641 mov r1, r8 800c4d8: 4620 mov r0, r4 800c4da: f7ff fdf5 bl 800c0c8 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c4de: 6a63 ldr r3, [r4, #36] @ 0x24 800c4e0: 2b00 cmp r3, #0 800c4e2: d151 bne.n 800c588 else if( xYieldRequired != pdFALSE ) 800c4e4: b148 cbz r0, 800c4fa queueYIELD_IF_USING_PREEMPTION(); 800c4e6: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800c4ea: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800c4ee: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800c4f2: f3bf 8f4f dsb sy 800c4f6: f3bf 8f6f isb sy taskEXIT_CRITICAL(); 800c4fa: f002 fa75 bl 800e9e8 return pdPASS; 800c4fe: 2001 movs r0, #1 } 800c500: b004 add sp, #16 800c502: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} taskEXIT_CRITICAL(); 800c506: f002 fa6f bl 800e9e8 return errQUEUE_FULL; 800c50a: 2000 movs r0, #0 800c50c: e7f8 b.n 800c500 taskENTER_CRITICAL(); 800c50e: f002 fa49 bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800c512: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800c516: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c518: 2d00 cmp r5, #0 800c51a: dd10 ble.n 800c53e if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c51c: f104 0624 add.w r6, r4, #36 @ 0x24 800c520: e003 b.n 800c52a --cTxLock; 800c522: 1e6b subs r3, r5, #1 800c524: b2da uxtb r2, r3 800c526: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c528: b14a cbz r2, 800c53e if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c52a: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c52c: 4630 mov r0, r6 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c52e: b133 cbz r3, 800c53e if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c530: f001 fb42 bl 800dbb8 800c534: 2800 cmp r0, #0 800c536: d0f4 beq.n 800c522 vTaskMissedYield(); 800c538: f001 fbee bl 800dd18 800c53c: e7f1 b.n 800c522 pxQueue->cTxLock = queueUNLOCKED; 800c53e: 23ff movs r3, #255 @ 0xff 800c540: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800c544: f002 fa50 bl 800e9e8 taskENTER_CRITICAL(); 800c548: f002 fa2c bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800c54c: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800c550: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c552: 2d00 cmp r5, #0 800c554: dd10 ble.n 800c578 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c556: f104 0610 add.w r6, r4, #16 800c55a: e003 b.n 800c564 --cRxLock; 800c55c: 1e6b subs r3, r5, #1 800c55e: b2da uxtb r2, r3 800c560: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c562: b14a cbz r2, 800c578 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c564: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c566: 4630 mov r0, r6 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c568: b133 cbz r3, 800c578 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c56a: f001 fb25 bl 800dbb8 800c56e: 2800 cmp r0, #0 800c570: d0f4 beq.n 800c55c vTaskMissedYield(); 800c572: f001 fbd1 bl 800dd18 800c576: e7f1 b.n 800c55c pxQueue->cRxLock = queueUNLOCKED; 800c578: 23ff movs r3, #255 @ 0xff 800c57a: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800c57e: f002 fa33 bl 800e9e8 ( void ) xTaskResumeAll(); 800c582: f001 fa0f bl 800d9a4 return errQUEUE_FULL; 800c586: e7c0 b.n 800c50a if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c588: f104 0024 add.w r0, r4, #36 @ 0x24 800c58c: f001 fb14 bl 800dbb8 800c590: 2800 cmp r0, #0 800c592: d0b2 beq.n 800c4fa 800c594: e7a7 b.n 800c4e6 800c596: bf00 nop 0800c598 : configASSERT( pxStaticQueue != NULL ); 800c598: b179 cbz r1, 800c5ba volatile size_t xSize = sizeof( StaticQueue_t ); 800c59a: 2350 movs r3, #80 @ 0x50 { 800c59c: b570 push {r4, r5, r6, lr} 800c59e: b082 sub sp, #8 volatile size_t xSize = sizeof( StaticQueue_t ); 800c5a0: 9301 str r3, [sp, #4] configASSERT( xSize == sizeof( Queue_t ) ); 800c5a2: 9b01 ldr r3, [sp, #4] 800c5a4: 2b50 cmp r3, #80 @ 0x50 800c5a6: d011 beq.n 800c5cc 800c5a8: f04f 0350 mov.w r3, #80 @ 0x50 800c5ac: f383 8811 msr BASEPRI, r3 800c5b0: f3bf 8f6f isb sy 800c5b4: f3bf 8f4f dsb sy 800c5b8: e7fe b.n 800c5b8 800c5ba: f04f 0350 mov.w r3, #80 @ 0x50 800c5be: f383 8811 msr BASEPRI, r3 800c5c2: f3bf 8f6f isb sy 800c5c6: f3bf 8f4f dsb sy configASSERT( pxStaticQueue != NULL ); 800c5ca: e7fe b.n 800c5ca pxNewQueue->uxLength = uxQueueLength; 800c5cc: 2600 movs r6, #0 pxNewQueue->ucStaticallyAllocated = pdTRUE; 800c5ce: 2301 movs r3, #1 800c5d0: 460c mov r4, r1 pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 800c5d2: 6009 str r1, [r1, #0] pxNewQueue->ucStaticallyAllocated = pdTRUE; 800c5d4: f881 3046 strb.w r3, [r1, #70] @ 0x46 800c5d8: 4605 mov r5, r0 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 800c5da: 9a01 ldr r2, [sp, #4] pxNewQueue->uxLength = uxQueueLength; 800c5dc: e9c1 360f strd r3, r6, [r1, #60] @ 0x3c taskENTER_CRITICAL(); 800c5e0: f002 f9e0 bl 800e9a4 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c5e4: 6821 ldr r1, [r4, #0] pxQueue->cRxLock = queueUNLOCKED; 800c5e6: 23ff movs r3, #255 @ 0xff pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 800c5e8: 63a6 str r6, [r4, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 800c5ea: 6061 str r1, [r4, #4] pxQueue->cRxLock = queueUNLOCKED; 800c5ec: f884 3044 strb.w r3, [r4, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 800c5f0: f884 3045 strb.w r3, [r4, #69] @ 0x45 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c5f4: e9d4 200f ldrd r2, r0, [r4, #60] @ 0x3c 800c5f8: fb00 f202 mul.w r2, r0, r2 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c5fc: 1a10 subs r0, r2, r0 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c5fe: 440a add r2, r1 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c600: 4401 add r1, r0 vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800c602: f104 0010 add.w r0, r4, #16 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c606: e9c4 2102 strd r2, r1, [r4, #8] vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800c60a: f7ff fd13 bl 800c034 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 800c60e: f104 0024 add.w r0, r4, #36 @ 0x24 800c612: f7ff fd0f bl 800c034 taskEXIT_CRITICAL(); 800c616: f002 f9e7 bl 800e9e8 ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 800c61a: 4633 mov r3, r6 800c61c: 4632 mov r2, r6 800c61e: 4631 mov r1, r6 800c620: 4620 mov r0, r4 pxNewQueue->ucQueueType = ucQueueType; 800c622: f884 504c strb.w r5, [r4, #76] @ 0x4c pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 800c626: 60a6 str r6, [r4, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 800c628: 6026 str r6, [r4, #0] pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 800c62a: 60e6 str r6, [r4, #12] ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 800c62c: f7ff fe32 bl 800c294 } 800c630: 4620 mov r0, r4 800c632: b002 add sp, #8 800c634: bd70 pop {r4, r5, r6, pc} 800c636: bf00 nop 0800c638 : { 800c638: b538 push {r3, r4, r5, lr} configASSERT( pxMutex ); 800c63a: b138 cbz r0, 800c64c if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 800c63c: 6885 ldr r5, [r0, #8] 800c63e: 4604 mov r4, r0 800c640: f001 fb70 bl 800dd24 800c644: 4285 cmp r5, r0 800c646: d00a beq.n 800c65e xReturn = pdFAIL; 800c648: 2000 movs r0, #0 } 800c64a: bd38 pop {r3, r4, r5, pc} 800c64c: f04f 0350 mov.w r3, #80 @ 0x50 800c650: f383 8811 msr BASEPRI, r3 800c654: f3bf 8f6f isb sy 800c658: f3bf 8f4f dsb sy configASSERT( pxMutex ); 800c65c: e7fe b.n 800c65c ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 800c65e: 68e3 ldr r3, [r4, #12] 800c660: 3b01 subs r3, #1 800c662: 60e3 str r3, [r4, #12] if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 800c664: b10b cbz r3, 800c66a xReturn = pdPASS; 800c666: 2001 movs r0, #1 } 800c668: bd38 pop {r3, r4, r5, pc} ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 800c66a: 461a mov r2, r3 800c66c: 4619 mov r1, r3 800c66e: 4620 mov r0, r4 800c670: f7ff fe10 bl 800c294 800c674: e7f7 b.n 800c666 800c676: bf00 nop 0800c678 : { 800c678: b570 push {r4, r5, r6, lr} 800c67a: 4605 mov r5, r0 pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 800c67c: 2050 movs r0, #80 @ 0x50 800c67e: f002 faf1 bl 800ec64 if( pxNewQueue != NULL ) 800c682: 4604 mov r4, r0 800c684: b370 cbz r0, 800c6e4 pxNewQueue->ucStaticallyAllocated = pdFALSE; 800c686: 2600 movs r6, #0 pxNewQueue->uxLength = uxQueueLength; 800c688: 2301 movs r3, #1 pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 800c68a: 6020 str r0, [r4, #0] pxNewQueue->ucStaticallyAllocated = pdFALSE; 800c68c: f880 6046 strb.w r6, [r0, #70] @ 0x46 pxNewQueue->uxLength = uxQueueLength; 800c690: e9c0 360f strd r3, r6, [r0, #60] @ 0x3c taskENTER_CRITICAL(); 800c694: f002 f986 bl 800e9a4 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c698: 6821 ldr r1, [r4, #0] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 800c69a: 63a6 str r6, [r4, #56] @ 0x38 vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800c69c: f104 0010 add.w r0, r4, #16 pxQueue->pcWriteTo = pxQueue->pcHead; 800c6a0: 6061 str r1, [r4, #4] pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c6a2: e9d4 230f ldrd r2, r3, [r4, #60] @ 0x3c 800c6a6: fb03 f202 mul.w r2, r3, r2 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c6aa: 1ad3 subs r3, r2, r3 pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c6ac: 440a add r2, r1 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c6ae: 4419 add r1, r3 pxQueue->cRxLock = queueUNLOCKED; 800c6b0: 23ff movs r3, #255 @ 0xff pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800c6b2: e9c4 2102 strd r2, r1, [r4, #8] pxQueue->cRxLock = queueUNLOCKED; 800c6b6: f884 3044 strb.w r3, [r4, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 800c6ba: f884 3045 strb.w r3, [r4, #69] @ 0x45 vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800c6be: f7ff fcb9 bl 800c034 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 800c6c2: f104 0024 add.w r0, r4, #36 @ 0x24 800c6c6: f7ff fcb5 bl 800c034 taskEXIT_CRITICAL(); 800c6ca: f002 f98d bl 800e9e8 ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 800c6ce: 4633 mov r3, r6 800c6d0: 4632 mov r2, r6 800c6d2: 4631 mov r1, r6 800c6d4: 4620 mov r0, r4 pxNewQueue->ucQueueType = ucQueueType; 800c6d6: f884 504c strb.w r5, [r4, #76] @ 0x4c pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 800c6da: 60a6 str r6, [r4, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 800c6dc: 6026 str r6, [r4, #0] pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 800c6de: 60e6 str r6, [r4, #12] ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 800c6e0: f7ff fdd8 bl 800c294 } 800c6e4: 4620 mov r0, r4 800c6e6: bd70 pop {r4, r5, r6, pc} 0800c6e8 : configASSERT( pxQueue ); 800c6e8: 2800 cmp r0, #0 800c6ea: d04b beq.n 800c784 { 800c6ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800c6f0: 460e mov r6, r1 800c6f2: 4604 mov r4, r0 800c6f4: 4617 mov r7, r2 800c6f6: 461d mov r5, r3 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800c6f8: b339 cbz r1, 800c74a configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 800c6fa: 2d02 cmp r5, #2 800c6fc: d10b bne.n 800c716 800c6fe: 6be3 ldr r3, [r4, #60] @ 0x3c 800c700: 2b01 cmp r3, #1 800c702: d008 beq.n 800c716 800c704: f04f 0350 mov.w r3, #80 @ 0x50 800c708: f383 8811 msr BASEPRI, r3 800c70c: f3bf 8f6f isb sy 800c710: f3bf 8f4f dsb sy 800c714: e7fe b.n 800c714 portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 800c716: f002 fa77 bl 800ec08 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 800c71a: f3ef 8811 mrs r8, BASEPRI 800c71e: f04f 0350 mov.w r3, #80 @ 0x50 800c722: f383 8811 msr BASEPRI, r3 800c726: f3bf 8f6f isb sy 800c72a: f3bf 8f4f dsb sy if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 800c72e: 6ba2 ldr r2, [r4, #56] @ 0x38 800c730: 6be3 ldr r3, [r4, #60] @ 0x3c 800c732: 429a cmp r2, r3 800c734: d315 bcc.n 800c762 800c736: f1a5 0002 sub.w r0, r5, #2 800c73a: fab0 f080 clz r0, r0 800c73e: 0940 lsrs r0, r0, #5 800c740: b978 cbnz r0, 800c762 } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 800c742: f388 8811 msr BASEPRI, r8 } 800c746: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800c74a: 6c03 ldr r3, [r0, #64] @ 0x40 800c74c: 2b00 cmp r3, #0 800c74e: d0d4 beq.n 800c6fa __asm volatile 800c750: f04f 0350 mov.w r3, #80 @ 0x50 800c754: f383 8811 msr BASEPRI, r3 800c758: f3bf 8f6f isb sy 800c75c: f3bf 8f4f dsb sy 800c760: e7fe b.n 800c760 ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 800c762: 462a mov r2, r5 const int8_t cTxLock = pxQueue->cTxLock; 800c764: f894 5045 ldrb.w r5, [r4, #69] @ 0x45 ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 800c768: 4631 mov r1, r6 800c76a: 4620 mov r0, r4 const int8_t cTxLock = pxQueue->cTxLock; 800c76c: b26d sxtb r5, r5 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 800c76e: 6ba3 ldr r3, [r4, #56] @ 0x38 ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 800c770: f7ff fcaa bl 800c0c8 if( cTxLock == queueUNLOCKED ) 800c774: 1c6b adds r3, r5, #1 800c776: d00e beq.n 800c796 pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 800c778: 1c6b adds r3, r5, #1 800c77a: b25b sxtb r3, r3 800c77c: f884 3045 strb.w r3, [r4, #69] @ 0x45 xReturn = pdPASS; 800c780: 2001 movs r0, #1 800c782: e7de b.n 800c742 800c784: f04f 0350 mov.w r3, #80 @ 0x50 800c788: f383 8811 msr BASEPRI, r3 800c78c: f3bf 8f6f isb sy 800c790: f3bf 8f4f dsb sy configASSERT( pxQueue ); 800c794: e7fe b.n 800c794 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c796: 6a63 ldr r3, [r4, #36] @ 0x24 800c798: 2b00 cmp r3, #0 800c79a: d0f1 beq.n 800c780 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c79c: f104 0024 add.w r0, r4, #36 @ 0x24 800c7a0: f001 fa0a bl 800dbb8 if( pxHigherPriorityTaskWoken != NULL ) 800c7a4: 2800 cmp r0, #0 800c7a6: d0eb beq.n 800c780 800c7a8: 2f00 cmp r7, #0 800c7aa: d0e9 beq.n 800c780 *pxHigherPriorityTaskWoken = pdTRUE; 800c7ac: 2301 movs r3, #1 800c7ae: 603b str r3, [r7, #0] 800c7b0: e7e6 b.n 800c780 800c7b2: bf00 nop 0800c7b4 : { 800c7b4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 800c7b8: b085 sub sp, #20 800c7ba: 9201 str r2, [sp, #4] configASSERT( ( pxQueue ) ); 800c7bc: 2800 cmp r0, #0 800c7be: f000 8164 beq.w 800ca8a configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800c7c2: 460f mov r7, r1 800c7c4: 4604 mov r4, r0 800c7c6: 2900 cmp r1, #0 800c7c8: f000 8097 beq.w 800c8fa configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800c7cc: f001 fab0 bl 800dd30 800c7d0: 2800 cmp r0, #0 800c7d2: f000 809f beq.w 800c914 taskENTER_CRITICAL(); 800c7d6: f002 f8e5 bl 800e9a4 const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 800c7da: 6ba5 ldr r5, [r4, #56] @ 0x38 if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 800c7dc: 2d00 cmp r5, #0 800c7de: d175 bne.n 800c8cc if( xTicksToWait == ( TickType_t ) 0 ) 800c7e0: 9b01 ldr r3, [sp, #4] 800c7e2: 2b00 cmp r3, #0 800c7e4: f000 80f4 beq.w 800c9d0 prvLockQueue( pxQueue ); 800c7e8: 46a8 mov r8, r5 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c7ea: f104 0624 add.w r6, r4, #36 @ 0x24 vTaskInternalSetTimeOutState( &xTimeOut ); 800c7ee: a802 add r0, sp, #8 800c7f0: f001 fa44 bl 800dc7c taskEXIT_CRITICAL(); 800c7f4: f002 f8f8 bl 800e9e8 vTaskSuspendAll(); 800c7f8: f001 f8cc bl 800d994 prvLockQueue( pxQueue ); 800c7fc: f002 f8d2 bl 800e9a4 800c800: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800c804: 2bff cmp r3, #255 @ 0xff 800c806: d101 bne.n 800c80c 800c808: f884 8044 strb.w r8, [r4, #68] @ 0x44 800c80c: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800c810: 2bff cmp r3, #255 @ 0xff 800c812: d101 bne.n 800c818 800c814: f884 8045 strb.w r8, [r4, #69] @ 0x45 800c818: f002 f8e6 bl 800e9e8 if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 800c81c: a901 add r1, sp, #4 800c81e: a802 add r0, sp, #8 800c820: f001 fa38 bl 800dc94 800c824: 2800 cmp r0, #0 800c826: f040 8082 bne.w 800c92e taskENTER_CRITICAL(); 800c82a: f002 f8bb bl 800e9a4 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 800c82e: 6ba3 ldr r3, [r4, #56] @ 0x38 800c830: 2b00 cmp r3, #0 800c832: f000 80d3 beq.w 800c9dc taskEXIT_CRITICAL(); 800c836: f002 f8d7 bl 800e9e8 taskENTER_CRITICAL(); 800c83a: f002 f8b3 bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800c83e: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800c842: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c844: 2d00 cmp r5, #0 800c846: dd14 ble.n 800c872 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c848: f104 0924 add.w r9, r4, #36 @ 0x24 800c84c: e003 b.n 800c856 --cTxLock; 800c84e: 1e6b subs r3, r5, #1 800c850: b2da uxtb r2, r3 800c852: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c854: b16a cbz r2, 800c872 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c856: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c858: 4648 mov r0, r9 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c85a: b153 cbz r3, 800c872 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c85c: f001 f9ac bl 800dbb8 800c860: 2800 cmp r0, #0 800c862: d0f4 beq.n 800c84e vTaskMissedYield(); 800c864: f001 fa58 bl 800dd18 --cTxLock; 800c868: 1e6b subs r3, r5, #1 800c86a: b2da uxtb r2, r3 800c86c: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c86e: 2a00 cmp r2, #0 800c870: d1f1 bne.n 800c856 pxQueue->cTxLock = queueUNLOCKED; 800c872: 23ff movs r3, #255 @ 0xff 800c874: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800c878: f002 f8b6 bl 800e9e8 taskENTER_CRITICAL(); 800c87c: f002 f892 bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800c880: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800c884: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c886: 2d00 cmp r5, #0 800c888: dd14 ble.n 800c8b4 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c88a: f104 0910 add.w r9, r4, #16 800c88e: e003 b.n 800c898 --cRxLock; 800c890: 1e6b subs r3, r5, #1 800c892: b2da uxtb r2, r3 800c894: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c896: b16a cbz r2, 800c8b4 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c898: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c89a: 4648 mov r0, r9 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c89c: b153 cbz r3, 800c8b4 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c89e: f001 f98b bl 800dbb8 800c8a2: 2800 cmp r0, #0 800c8a4: d0f4 beq.n 800c890 vTaskMissedYield(); 800c8a6: f001 fa37 bl 800dd18 --cRxLock; 800c8aa: 1e6b subs r3, r5, #1 800c8ac: b2da uxtb r2, r3 800c8ae: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c8b0: 2a00 cmp r2, #0 800c8b2: d1f1 bne.n 800c898 pxQueue->cRxLock = queueUNLOCKED; 800c8b4: 23ff movs r3, #255 @ 0xff 800c8b6: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800c8ba: f002 f895 bl 800e9e8 ( void ) xTaskResumeAll(); 800c8be: f001 f871 bl 800d9a4 taskENTER_CRITICAL(); 800c8c2: f002 f86f bl 800e9a4 const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 800c8c6: 6ba5 ldr r5, [r4, #56] @ 0x38 if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 800c8c8: 2d00 cmp r5, #0 800c8ca: d07d beq.n 800c9c8 if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 800c8cc: 6c22 ldr r2, [r4, #64] @ 0x40 800c8ce: b152 cbz r2, 800c8e6 pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800c8d0: 68e1 ldr r1, [r4, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 800c8d2: 68a3 ldr r3, [r4, #8] pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800c8d4: 4411 add r1, r2 if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 800c8d6: 4299 cmp r1, r3 pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800c8d8: 60e1 str r1, [r4, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 800c8da: d301 bcc.n 800c8e0 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 800c8dc: 6821 ldr r1, [r4, #0] 800c8de: 60e1 str r1, [r4, #12] ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 800c8e0: 4638 mov r0, r7 800c8e2: f003 f9e6 bl 800fcb2 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 800c8e6: 3d01 subs r5, #1 800c8e8: 63a5 str r5, [r4, #56] @ 0x38 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c8ea: 6923 ldr r3, [r4, #16] 800c8ec: 2b00 cmp r3, #0 800c8ee: f040 80d5 bne.w 800ca9c taskEXIT_CRITICAL(); 800c8f2: f002 f879 bl 800e9e8 return pdPASS; 800c8f6: 2001 movs r0, #1 800c8f8: e06d b.n 800c9d6 configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800c8fa: 6c03 ldr r3, [r0, #64] @ 0x40 800c8fc: 2b00 cmp r3, #0 800c8fe: f43f af65 beq.w 800c7cc 800c902: f04f 0350 mov.w r3, #80 @ 0x50 800c906: f383 8811 msr BASEPRI, r3 800c90a: f3bf 8f6f isb sy 800c90e: f3bf 8f4f dsb sy 800c912: e7fe b.n 800c912 configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800c914: 9b01 ldr r3, [sp, #4] 800c916: 2b00 cmp r3, #0 800c918: f43f af5d beq.w 800c7d6 800c91c: f04f 0350 mov.w r3, #80 @ 0x50 800c920: f383 8811 msr BASEPRI, r3 800c924: f3bf 8f6f isb sy 800c928: f3bf 8f4f dsb sy 800c92c: e7fe b.n 800c92c taskENTER_CRITICAL(); 800c92e: f002 f839 bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800c932: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800c936: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c938: 2d00 cmp r5, #0 800c93a: dc04 bgt.n 800c946 800c93c: e011 b.n 800c962 --cTxLock; 800c93e: 1e6b subs r3, r5, #1 800c940: b2da uxtb r2, r3 800c942: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c944: b16a cbz r2, 800c962 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c946: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c948: 4630 mov r0, r6 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c94a: b153 cbz r3, 800c962 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c94c: f001 f934 bl 800dbb8 800c950: 2800 cmp r0, #0 800c952: d0f4 beq.n 800c93e vTaskMissedYield(); 800c954: f001 f9e0 bl 800dd18 --cTxLock; 800c958: 1e6b subs r3, r5, #1 800c95a: b2da uxtb r2, r3 800c95c: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c95e: 2a00 cmp r2, #0 800c960: d1f1 bne.n 800c946 pxQueue->cTxLock = queueUNLOCKED; 800c962: 23ff movs r3, #255 @ 0xff 800c964: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800c968: f002 f83e bl 800e9e8 taskENTER_CRITICAL(); 800c96c: f002 f81a bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800c970: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800c974: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c976: 2d00 cmp r5, #0 800c978: dd14 ble.n 800c9a4 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c97a: f104 0910 add.w r9, r4, #16 800c97e: e003 b.n 800c988 --cRxLock; 800c980: 1e6b subs r3, r5, #1 800c982: b2da uxtb r2, r3 800c984: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c986: b16a cbz r2, 800c9a4 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c988: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c98a: 4648 mov r0, r9 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c98c: b153 cbz r3, 800c9a4 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c98e: f001 f913 bl 800dbb8 800c992: 2800 cmp r0, #0 800c994: d0f4 beq.n 800c980 vTaskMissedYield(); 800c996: f001 f9bf bl 800dd18 --cRxLock; 800c99a: 1e6b subs r3, r5, #1 800c99c: b2da uxtb r2, r3 800c99e: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800c9a0: 2a00 cmp r2, #0 800c9a2: d1f1 bne.n 800c988 pxQueue->cRxLock = queueUNLOCKED; 800c9a4: 23ff movs r3, #255 @ 0xff 800c9a6: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800c9aa: f002 f81d bl 800e9e8 ( void ) xTaskResumeAll(); 800c9ae: f000 fff9 bl 800d9a4 taskENTER_CRITICAL(); 800c9b2: f001 fff7 bl 800e9a4 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 800c9b6: 6ba3 ldr r3, [r4, #56] @ 0x38 800c9b8: b153 cbz r3, 800c9d0 taskEXIT_CRITICAL(); 800c9ba: f002 f815 bl 800e9e8 taskENTER_CRITICAL(); 800c9be: f001 fff1 bl 800e9a4 const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 800c9c2: 6ba5 ldr r5, [r4, #56] @ 0x38 if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 800c9c4: 2d00 cmp r5, #0 800c9c6: d181 bne.n 800c8cc if( xTicksToWait == ( TickType_t ) 0 ) 800c9c8: 9b01 ldr r3, [sp, #4] 800c9ca: 2b00 cmp r3, #0 800c9cc: f47f af12 bne.w 800c7f4 taskEXIT_CRITICAL(); 800c9d0: f002 f80a bl 800e9e8 return errQUEUE_EMPTY; 800c9d4: 2000 movs r0, #0 } 800c9d6: b005 add sp, #20 800c9d8: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 800c9dc: f104 0924 add.w r9, r4, #36 @ 0x24 taskEXIT_CRITICAL(); 800c9e0: f002 f802 bl 800e9e8 vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 800c9e4: 9901 ldr r1, [sp, #4] 800c9e6: 4648 mov r0, r9 800c9e8: f001 f858 bl 800da9c taskENTER_CRITICAL(); 800c9ec: f001 ffda bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800c9f0: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800c9f4: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800c9f6: 2d00 cmp r5, #0 800c9f8: dc04 bgt.n 800ca04 800c9fa: e011 b.n 800ca20 --cTxLock; 800c9fc: 1e6b subs r3, r5, #1 800c9fe: b2da uxtb r2, r3 800ca00: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800ca02: b16a cbz r2, 800ca20 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800ca04: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800ca06: 4648 mov r0, r9 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800ca08: b153 cbz r3, 800ca20 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800ca0a: f001 f8d5 bl 800dbb8 800ca0e: 2800 cmp r0, #0 800ca10: d0f4 beq.n 800c9fc vTaskMissedYield(); 800ca12: f001 f981 bl 800dd18 --cTxLock; 800ca16: 1e6b subs r3, r5, #1 800ca18: b2da uxtb r2, r3 800ca1a: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800ca1c: 2a00 cmp r2, #0 800ca1e: d1f1 bne.n 800ca04 pxQueue->cTxLock = queueUNLOCKED; 800ca20: 23ff movs r3, #255 @ 0xff 800ca22: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800ca26: f001 ffdf bl 800e9e8 taskENTER_CRITICAL(); 800ca2a: f001 ffbb bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800ca2e: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800ca32: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800ca34: 2d00 cmp r5, #0 800ca36: dd14 ble.n 800ca62 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800ca38: f104 0910 add.w r9, r4, #16 800ca3c: e003 b.n 800ca46 --cRxLock; 800ca3e: 1e6b subs r3, r5, #1 800ca40: b2da uxtb r2, r3 800ca42: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800ca44: b16a cbz r2, 800ca62 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800ca46: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800ca48: 4648 mov r0, r9 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800ca4a: b153 cbz r3, 800ca62 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800ca4c: f001 f8b4 bl 800dbb8 800ca50: 2800 cmp r0, #0 800ca52: d0f4 beq.n 800ca3e vTaskMissedYield(); 800ca54: f001 f960 bl 800dd18 --cRxLock; 800ca58: 1e6b subs r3, r5, #1 800ca5a: b2da uxtb r2, r3 800ca5c: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800ca5e: 2a00 cmp r2, #0 800ca60: d1f1 bne.n 800ca46 pxQueue->cRxLock = queueUNLOCKED; 800ca62: 23ff movs r3, #255 @ 0xff 800ca64: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800ca68: f001 ffbe bl 800e9e8 if( xTaskResumeAll() == pdFALSE ) 800ca6c: f000 ff9a bl 800d9a4 800ca70: 2800 cmp r0, #0 800ca72: d1a4 bne.n 800c9be portYIELD_WITHIN_API(); 800ca74: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800ca78: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800ca7c: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800ca80: f3bf 8f4f dsb sy 800ca84: f3bf 8f6f isb sy taskENTER_CRITICAL(); 800ca88: e799 b.n 800c9be 800ca8a: f04f 0350 mov.w r3, #80 @ 0x50 800ca8e: f383 8811 msr BASEPRI, r3 800ca92: f3bf 8f6f isb sy 800ca96: f3bf 8f4f dsb sy configASSERT( ( pxQueue ) ); 800ca9a: e7fe b.n 800ca9a if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800ca9c: f104 0010 add.w r0, r4, #16 800caa0: f001 f88a bl 800dbb8 800caa4: 2800 cmp r0, #0 800caa6: f43f af24 beq.w 800c8f2 queueYIELD_IF_USING_PREEMPTION(); 800caaa: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800caae: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800cab2: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800cab6: f3bf 8f4f dsb sy 800caba: f3bf 8f6f isb sy 800cabe: e718 b.n 800c8f2 0800cac0 : { 800cac0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800cac4: b084 sub sp, #16 800cac6: 9101 str r1, [sp, #4] configASSERT( ( pxQueue ) ); 800cac8: 2800 cmp r0, #0 800caca: d05e beq.n 800cb8a configASSERT( pxQueue->uxItemSize == 0 ); 800cacc: 6c07 ldr r7, [r0, #64] @ 0x40 800cace: 4604 mov r4, r0 800cad0: b147 cbz r7, 800cae4 800cad2: f04f 0350 mov.w r3, #80 @ 0x50 800cad6: f383 8811 msr BASEPRI, r3 800cada: f3bf 8f6f isb sy 800cade: f3bf 8f4f dsb sy 800cae2: e7fe b.n 800cae2 configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800cae4: f001 f924 bl 800dd30 800cae8: 4605 mov r5, r0 800caea: 2800 cmp r0, #0 800caec: d056 beq.n 800cb9c 800caee: 463d mov r5, r7 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800caf0: f104 0624 add.w r6, r4, #36 @ 0x24 taskENTER_CRITICAL(); 800caf4: f001 ff56 bl 800e9a4 const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 800caf8: 6ba3 ldr r3, [r4, #56] @ 0x38 if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 800cafa: 2b00 cmp r3, #0 800cafc: f040 814d bne.w 800cd9a if( xTicksToWait == ( TickType_t ) 0 ) 800cb00: 9b01 ldr r3, [sp, #4] 800cb02: 2b00 cmp r3, #0 800cb04: f000 813e beq.w 800cd84 else if( xEntryTimeSet == pdFALSE ) 800cb08: 2d00 cmp r5, #0 800cb0a: f000 80a3 beq.w 800cc54 taskEXIT_CRITICAL(); 800cb0e: f001 ff6b bl 800e9e8 vTaskSuspendAll(); 800cb12: f000 ff3f bl 800d994 prvLockQueue( pxQueue ); 800cb16: f001 ff45 bl 800e9a4 800cb1a: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800cb1e: 2bff cmp r3, #255 @ 0xff 800cb20: d102 bne.n 800cb28 800cb22: 2300 movs r3, #0 800cb24: f884 3044 strb.w r3, [r4, #68] @ 0x44 800cb28: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800cb2c: 2bff cmp r3, #255 @ 0xff 800cb2e: d102 bne.n 800cb36 800cb30: 2300 movs r3, #0 800cb32: f884 3045 strb.w r3, [r4, #69] @ 0x45 800cb36: f001 ff57 bl 800e9e8 if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 800cb3a: a901 add r1, sp, #4 800cb3c: a802 add r0, sp, #8 800cb3e: f001 f8a9 bl 800dc94 800cb42: 2800 cmp r0, #0 800cb44: d137 bne.n 800cbb6 taskENTER_CRITICAL(); 800cb46: f001 ff2d bl 800e9a4 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 800cb4a: 6ba3 ldr r3, [r4, #56] @ 0x38 800cb4c: 2b00 cmp r3, #0 800cb4e: f000 80ae beq.w 800ccae taskEXIT_CRITICAL(); 800cb52: f001 ff49 bl 800e9e8 taskENTER_CRITICAL(); 800cb56: f001 ff25 bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800cb5a: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800cb5e: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800cb60: 2d00 cmp r5, #0 800cb62: dd7f ble.n 800cc64 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cb64: f104 0824 add.w r8, r4, #36 @ 0x24 800cb68: e004 b.n 800cb74 --cTxLock; 800cb6a: 1e6b subs r3, r5, #1 800cb6c: b2da uxtb r2, r3 800cb6e: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800cb70: 2a00 cmp r2, #0 800cb72: d077 beq.n 800cc64 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800cb74: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cb76: 4640 mov r0, r8 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800cb78: 2b00 cmp r3, #0 800cb7a: d073 beq.n 800cc64 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cb7c: f001 f81c bl 800dbb8 800cb80: 2800 cmp r0, #0 800cb82: d0f2 beq.n 800cb6a vTaskMissedYield(); 800cb84: f001 f8c8 bl 800dd18 800cb88: e7ef b.n 800cb6a 800cb8a: f04f 0350 mov.w r3, #80 @ 0x50 800cb8e: f383 8811 msr BASEPRI, r3 800cb92: f3bf 8f6f isb sy 800cb96: f3bf 8f4f dsb sy configASSERT( ( pxQueue ) ); 800cb9a: e7fe b.n 800cb9a configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800cb9c: 9b01 ldr r3, [sp, #4] 800cb9e: 2b00 cmp r3, #0 800cba0: f000 80d7 beq.w 800cd52 800cba4: f04f 0350 mov.w r3, #80 @ 0x50 800cba8: f383 8811 msr BASEPRI, r3 800cbac: f3bf 8f6f isb sy 800cbb0: f3bf 8f4f dsb sy 800cbb4: e7fe b.n 800cbb4 taskENTER_CRITICAL(); 800cbb6: f001 fef5 bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800cbba: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800cbbe: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800cbc0: 2d00 cmp r5, #0 800cbc2: dc04 bgt.n 800cbce 800cbc4: e011 b.n 800cbea --cTxLock; 800cbc6: 1e6b subs r3, r5, #1 800cbc8: b2da uxtb r2, r3 800cbca: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800cbcc: b16a cbz r2, 800cbea if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800cbce: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cbd0: 4630 mov r0, r6 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800cbd2: b153 cbz r3, 800cbea if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cbd4: f000 fff0 bl 800dbb8 800cbd8: 2800 cmp r0, #0 800cbda: d0f4 beq.n 800cbc6 vTaskMissedYield(); 800cbdc: f001 f89c bl 800dd18 --cTxLock; 800cbe0: 1e6b subs r3, r5, #1 800cbe2: b2da uxtb r2, r3 800cbe4: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800cbe6: 2a00 cmp r2, #0 800cbe8: d1f1 bne.n 800cbce pxQueue->cTxLock = queueUNLOCKED; 800cbea: 23ff movs r3, #255 @ 0xff 800cbec: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800cbf0: f001 fefa bl 800e9e8 taskENTER_CRITICAL(); 800cbf4: f001 fed6 bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800cbf8: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800cbfc: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cbfe: 2d00 cmp r5, #0 800cc00: dd14 ble.n 800cc2c if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cc02: f104 0810 add.w r8, r4, #16 800cc06: e003 b.n 800cc10 --cRxLock; 800cc08: 1e6b subs r3, r5, #1 800cc0a: b2da uxtb r2, r3 800cc0c: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cc0e: b16a cbz r2, 800cc2c if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cc10: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cc12: 4640 mov r0, r8 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cc14: b153 cbz r3, 800cc2c if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cc16: f000 ffcf bl 800dbb8 800cc1a: 2800 cmp r0, #0 800cc1c: d0f4 beq.n 800cc08 vTaskMissedYield(); 800cc1e: f001 f87b bl 800dd18 --cRxLock; 800cc22: 1e6b subs r3, r5, #1 800cc24: b2da uxtb r2, r3 800cc26: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cc28: 2a00 cmp r2, #0 800cc2a: d1f1 bne.n 800cc10 pxQueue->cRxLock = queueUNLOCKED; 800cc2c: 23ff movs r3, #255 @ 0xff 800cc2e: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800cc32: f001 fed9 bl 800e9e8 ( void ) xTaskResumeAll(); 800cc36: f000 feb5 bl 800d9a4 taskENTER_CRITICAL(); 800cc3a: f001 feb3 bl 800e9a4 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 800cc3e: 6ba3 ldr r3, [r4, #56] @ 0x38 800cc40: b963 cbnz r3, 800cc5c taskEXIT_CRITICAL(); 800cc42: f001 fed1 bl 800e9e8 if( xInheritanceOccurred != pdFALSE ) 800cc46: 2f00 cmp r7, #0 800cc48: f040 8085 bne.w 800cd56 return errQUEUE_EMPTY; 800cc4c: 2000 movs r0, #0 } 800cc4e: b004 add sp, #16 800cc50: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} vTaskInternalSetTimeOutState( &xTimeOut ); 800cc54: a802 add r0, sp, #8 800cc56: f001 f811 bl 800dc7c xEntryTimeSet = pdTRUE; 800cc5a: e758 b.n 800cb0e taskEXIT_CRITICAL(); 800cc5c: f001 fec4 bl 800e9e8 return xReturn; 800cc60: 2501 movs r5, #1 800cc62: e747 b.n 800caf4 pxQueue->cTxLock = queueUNLOCKED; 800cc64: 23ff movs r3, #255 @ 0xff 800cc66: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800cc6a: f001 febd bl 800e9e8 taskENTER_CRITICAL(); 800cc6e: f001 fe99 bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800cc72: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800cc76: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cc78: 2d00 cmp r5, #0 800cc7a: dd10 ble.n 800cc9e if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cc7c: f104 0810 add.w r8, r4, #16 800cc80: e003 b.n 800cc8a --cRxLock; 800cc82: 1e6b subs r3, r5, #1 800cc84: b2da uxtb r2, r3 800cc86: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cc88: b14a cbz r2, 800cc9e if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cc8a: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cc8c: 4640 mov r0, r8 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cc8e: b133 cbz r3, 800cc9e if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cc90: f000 ff92 bl 800dbb8 800cc94: 2800 cmp r0, #0 800cc96: d0f4 beq.n 800cc82 vTaskMissedYield(); 800cc98: f001 f83e bl 800dd18 800cc9c: e7f1 b.n 800cc82 pxQueue->cRxLock = queueUNLOCKED; 800cc9e: 23ff movs r3, #255 @ 0xff 800cca0: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800cca4: f001 fea0 bl 800e9e8 ( void ) xTaskResumeAll(); 800cca8: f000 fe7c bl 800d9a4 800ccac: e7d8 b.n 800cc60 taskEXIT_CRITICAL(); 800ccae: f001 fe9b bl 800e9e8 if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 800ccb2: 6823 ldr r3, [r4, #0] 800ccb4: 2b00 cmp r3, #0 800ccb6: d05c beq.n 800cd72 vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 800ccb8: f104 0824 add.w r8, r4, #36 @ 0x24 800ccbc: 9901 ldr r1, [sp, #4] 800ccbe: 4640 mov r0, r8 800ccc0: f000 feec bl 800da9c taskENTER_CRITICAL(); 800ccc4: f001 fe6e bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800ccc8: f894 3045 ldrb.w r3, [r4, #69] @ 0x45 800cccc: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800ccce: 2d00 cmp r5, #0 800ccd0: dc04 bgt.n 800ccdc 800ccd2: e00d b.n 800ccf0 --cTxLock; 800ccd4: 1e6b subs r3, r5, #1 800ccd6: b2da uxtb r2, r3 800ccd8: b25d sxtb r5, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800ccda: b14a cbz r2, 800ccf0 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800ccdc: 6a63 ldr r3, [r4, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800ccde: 4640 mov r0, r8 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800cce0: b133 cbz r3, 800ccf0 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cce2: f000 ff69 bl 800dbb8 800cce6: 2800 cmp r0, #0 800cce8: d0f4 beq.n 800ccd4 vTaskMissedYield(); 800ccea: f001 f815 bl 800dd18 800ccee: e7f1 b.n 800ccd4 pxQueue->cTxLock = queueUNLOCKED; 800ccf0: 23ff movs r3, #255 @ 0xff 800ccf2: f884 3045 strb.w r3, [r4, #69] @ 0x45 taskEXIT_CRITICAL(); 800ccf6: f001 fe77 bl 800e9e8 taskENTER_CRITICAL(); 800ccfa: f001 fe53 bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800ccfe: f894 3044 ldrb.w r3, [r4, #68] @ 0x44 800cd02: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cd04: 2d00 cmp r5, #0 800cd06: dd10 ble.n 800cd2a if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cd08: f104 0810 add.w r8, r4, #16 800cd0c: e003 b.n 800cd16 --cRxLock; 800cd0e: 1e6b subs r3, r5, #1 800cd10: b2da uxtb r2, r3 800cd12: b25d sxtb r5, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cd14: b14a cbz r2, 800cd2a if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cd16: 6923 ldr r3, [r4, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cd18: 4640 mov r0, r8 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cd1a: b133 cbz r3, 800cd2a if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cd1c: f000 ff4c bl 800dbb8 800cd20: 2800 cmp r0, #0 800cd22: d0f4 beq.n 800cd0e vTaskMissedYield(); 800cd24: f000 fff8 bl 800dd18 800cd28: e7f1 b.n 800cd0e pxQueue->cRxLock = queueUNLOCKED; 800cd2a: 23ff movs r3, #255 @ 0xff 800cd2c: f884 3044 strb.w r3, [r4, #68] @ 0x44 taskEXIT_CRITICAL(); 800cd30: f001 fe5a bl 800e9e8 if( xTaskResumeAll() == pdFALSE ) 800cd34: f000 fe36 bl 800d9a4 800cd38: 2800 cmp r0, #0 800cd3a: d191 bne.n 800cc60 portYIELD_WITHIN_API(); 800cd3c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800cd40: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800cd44: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800cd48: f3bf 8f4f dsb sy 800cd4c: f3bf 8f6f isb sy 800cd50: e786 b.n 800cc60 800cd52: 462f mov r7, r5 800cd54: e6cc b.n 800caf0 taskENTER_CRITICAL(); 800cd56: f001 fe25 bl 800e9a4 if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 800cd5a: 6a61 ldr r1, [r4, #36] @ 0x24 800cd5c: b119 cbz r1, 800cd66 uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 800cd5e: 6b23 ldr r3, [r4, #48] @ 0x30 800cd60: 6819 ldr r1, [r3, #0] 800cd62: f1c1 0138 rsb r1, r1, #56 @ 0x38 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 800cd66: 68a0 ldr r0, [r4, #8] 800cd68: f001 f876 bl 800de58 taskEXIT_CRITICAL(); 800cd6c: f001 fe3c bl 800e9e8 800cd70: e76c b.n 800cc4c taskENTER_CRITICAL(); 800cd72: f001 fe17 bl 800e9a4 xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 800cd76: 68a0 ldr r0, [r4, #8] 800cd78: f000 ffea bl 800dd50 800cd7c: 4607 mov r7, r0 taskEXIT_CRITICAL(); 800cd7e: f001 fe33 bl 800e9e8 800cd82: e799 b.n 800ccb8 configASSERT( xInheritanceOccurred == pdFALSE ); 800cd84: 2f00 cmp r7, #0 800cd86: d0f1 beq.n 800cd6c 800cd88: f04f 0350 mov.w r3, #80 @ 0x50 800cd8c: f383 8811 msr BASEPRI, r3 800cd90: f3bf 8f6f isb sy 800cd94: f3bf 8f4f dsb sy 800cd98: e7fe b.n 800cd98 pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 800cd9a: 3b01 subs r3, #1 if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 800cd9c: 6822 ldr r2, [r4, #0] pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 800cd9e: 63a3 str r3, [r4, #56] @ 0x38 if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 800cda0: b12a cbz r2, 800cdae if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cda2: 6923 ldr r3, [r4, #16] 800cda4: b93b cbnz r3, 800cdb6 taskEXIT_CRITICAL(); 800cda6: f001 fe1f bl 800e9e8 return pdPASS; 800cdaa: 2001 movs r0, #1 800cdac: e74f b.n 800cc4e pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 800cdae: f001 f8a3 bl 800def8 800cdb2: 60a0 str r0, [r4, #8] 800cdb4: e7f5 b.n 800cda2 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cdb6: f104 0010 add.w r0, r4, #16 800cdba: f000 fefd bl 800dbb8 800cdbe: 2800 cmp r0, #0 800cdc0: d0f1 beq.n 800cda6 queueYIELD_IF_USING_PREEMPTION(); 800cdc2: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800cdc6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800cdca: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800cdce: f3bf 8f4f dsb sy 800cdd2: f3bf 8f6f isb sy 800cdd6: e7e6 b.n 800cda6 0800cdd8 : configASSERT( pxMutex ); 800cdd8: b1a8 cbz r0, 800ce06 { 800cdda: b570 push {r4, r5, r6, lr} if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 800cddc: 6886 ldr r6, [r0, #8] 800cdde: 4604 mov r4, r0 800cde0: 460d mov r5, r1 800cde2: f000 ff9f bl 800dd24 800cde6: 4286 cmp r6, r0 800cde8: d008 beq.n 800cdfc xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 800cdea: 4629 mov r1, r5 800cdec: 4620 mov r0, r4 800cdee: f7ff fe67 bl 800cac0 if( xReturn != pdFAIL ) 800cdf2: b110 cbz r0, 800cdfa ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 800cdf4: 68e3 ldr r3, [r4, #12] 800cdf6: 3301 adds r3, #1 800cdf8: 60e3 str r3, [r4, #12] } 800cdfa: bd70 pop {r4, r5, r6, pc} ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 800cdfc: 68e3 ldr r3, [r4, #12] xReturn = pdPASS; 800cdfe: 2001 movs r0, #1 ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 800ce00: 4403 add r3, r0 800ce02: 60e3 str r3, [r4, #12] } 800ce04: bd70 pop {r4, r5, r6, pc} 800ce06: f04f 0350 mov.w r3, #80 @ 0x50 800ce0a: f383 8811 msr BASEPRI, r3 800ce0e: f3bf 8f6f isb sy 800ce12: f3bf 8f4f dsb sy configASSERT( pxMutex ); 800ce16: e7fe b.n 800ce16 0800ce18 : { 800ce18: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} configASSERT( pxQueue ); 800ce1c: b310 cbz r0, 800ce64 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800ce1e: 460f mov r7, r1 800ce20: 4604 mov r4, r0 800ce22: 4616 mov r6, r2 800ce24: b191 cbz r1, 800ce4c portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 800ce26: f001 feef bl 800ec08 __asm volatile 800ce2a: f3ef 8911 mrs r9, BASEPRI 800ce2e: f04f 0350 mov.w r3, #80 @ 0x50 800ce32: f383 8811 msr BASEPRI, r3 800ce36: f3bf 8f6f isb sy 800ce3a: f3bf 8f4f dsb sy const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 800ce3e: 6ba5 ldr r5, [r4, #56] @ 0x38 if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 800ce40: b9cd cbnz r5, 800ce76 xReturn = pdFAIL; 800ce42: 4628 mov r0, r5 __asm volatile 800ce44: f389 8811 msr BASEPRI, r9 } 800ce48: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800ce4c: 6c03 ldr r3, [r0, #64] @ 0x40 800ce4e: 2b00 cmp r3, #0 800ce50: d0e9 beq.n 800ce26 __asm volatile 800ce52: f04f 0350 mov.w r3, #80 @ 0x50 800ce56: f383 8811 msr BASEPRI, r3 800ce5a: f3bf 8f6f isb sy 800ce5e: f3bf 8f4f dsb sy 800ce62: e7fe b.n 800ce62 800ce64: f04f 0350 mov.w r3, #80 @ 0x50 800ce68: f383 8811 msr BASEPRI, r3 800ce6c: f3bf 8f6f isb sy 800ce70: f3bf 8f4f dsb sy configASSERT( pxQueue ); 800ce74: e7fe b.n 800ce74 const int8_t cRxLock = pxQueue->cRxLock; 800ce76: f894 8044 ldrb.w r8, [r4, #68] @ 0x44 if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 800ce7a: 6c22 ldr r2, [r4, #64] @ 0x40 const int8_t cRxLock = pxQueue->cRxLock; 800ce7c: fa4f f888 sxtb.w r8, r8 if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 800ce80: b142 cbz r2, 800ce94 pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800ce82: 68e1 ldr r1, [r4, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 800ce84: 68a3 ldr r3, [r4, #8] pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800ce86: 4411 add r1, r2 if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 800ce88: 4299 cmp r1, r3 pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800ce8a: 60e1 str r1, [r4, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 800ce8c: d21c bcs.n 800cec8 ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 800ce8e: 4638 mov r0, r7 800ce90: f002 ff0f bl 800fcb2 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 800ce94: 3d01 subs r5, #1 if( cRxLock == queueUNLOCKED ) 800ce96: f1b8 3fff cmp.w r8, #4294967295 @ 0xffffffff pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 800ce9a: 63a5 str r5, [r4, #56] @ 0x38 if( cRxLock == queueUNLOCKED ) 800ce9c: d006 beq.n 800ceac pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 800ce9e: f108 0301 add.w r3, r8, #1 800cea2: b25b sxtb r3, r3 800cea4: f884 3044 strb.w r3, [r4, #68] @ 0x44 xReturn = pdPASS; 800cea8: 2001 movs r0, #1 800ceaa: e7cb b.n 800ce44 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800ceac: 6923 ldr r3, [r4, #16] 800ceae: 2b00 cmp r3, #0 800ceb0: d0fa beq.n 800cea8 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800ceb2: f104 0010 add.w r0, r4, #16 800ceb6: f000 fe7f bl 800dbb8 if( pxHigherPriorityTaskWoken != NULL ) 800ceba: 2e00 cmp r6, #0 800cebc: d0f4 beq.n 800cea8 800cebe: 2800 cmp r0, #0 800cec0: d0f2 beq.n 800cea8 *pxHigherPriorityTaskWoken = pdTRUE; 800cec2: 2301 movs r3, #1 800cec4: 6033 str r3, [r6, #0] 800cec6: e7ef b.n 800cea8 pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 800cec8: 6821 ldr r1, [r4, #0] 800ceca: 60e1 str r1, [r4, #12] 800cecc: e7df b.n 800ce8e 800cece: bf00 nop 0800ced0 : /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 800ced0: 4b12 ldr r3, [pc, #72] @ (800cf1c ) 800ced2: 681a ldr r2, [r3, #0] 800ced4: b17a cbz r2, 800cef6 800ced6: 689a ldr r2, [r3, #8] 800ced8: b162 cbz r2, 800cef4 800ceda: 691a ldr r2, [r3, #16] 800cedc: b192 cbz r2, 800cf04 800cede: 699a ldr r2, [r3, #24] 800cee0: b192 cbz r2, 800cf08 800cee2: 6a1a ldr r2, [r3, #32] 800cee4: b192 cbz r2, 800cf0c 800cee6: 6a9a ldr r2, [r3, #40] @ 0x28 800cee8: b192 cbz r2, 800cf10 800ceea: 6b1a ldr r2, [r3, #48] @ 0x30 800ceec: b192 cbz r2, 800cf14 800ceee: 6b9a ldr r2, [r3, #56] @ 0x38 800cef0: b192 cbz r2, 800cf18 else { mtCOVERAGE_TEST_MARKER(); } } } 800cef2: 4770 bx lr for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 800cef4: 2201 movs r2, #1 xQueueRegistry[ ux ].xHandle = xQueue; 800cef6: eb03 0cc2 add.w ip, r3, r2, lsl #3 xQueueRegistry[ ux ].pcQueueName = pcQueueName; 800cefa: f843 1032 str.w r1, [r3, r2, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 800cefe: f8cc 0004 str.w r0, [ip, #4] } 800cf02: 4770 bx lr for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 800cf04: 2202 movs r2, #2 800cf06: e7f6 b.n 800cef6 800cf08: 2203 movs r2, #3 800cf0a: e7f4 b.n 800cef6 800cf0c: 2204 movs r2, #4 800cf0e: e7f2 b.n 800cef6 800cf10: 2205 movs r2, #5 800cf12: e7f0 b.n 800cef6 800cf14: 2206 movs r2, #6 800cf16: e7ee b.n 800cef6 800cf18: 2207 movs r2, #7 800cf1a: e7ec b.n 800cef6 800cf1c: 24002b08 .word 0x24002b08 0800cf20 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 800cf20: b570 push {r4, r5, r6, lr} 800cf22: 4605 mov r5, r0 800cf24: 460e mov r6, r1 800cf26: 4614 mov r4, r2 will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 800cf28: f001 fd3c bl 800e9a4 800cf2c: f895 3044 ldrb.w r3, [r5, #68] @ 0x44 800cf30: 2bff cmp r3, #255 @ 0xff 800cf32: d102 bne.n 800cf3a 800cf34: 2300 movs r3, #0 800cf36: f885 3044 strb.w r3, [r5, #68] @ 0x44 800cf3a: f895 3045 ldrb.w r3, [r5, #69] @ 0x45 800cf3e: 2bff cmp r3, #255 @ 0xff 800cf40: d102 bne.n 800cf48 800cf42: 2300 movs r3, #0 800cf44: f885 3045 strb.w r3, [r5, #69] @ 0x45 800cf48: f001 fd4e bl 800e9e8 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 800cf4c: 6bab ldr r3, [r5, #56] @ 0x38 800cf4e: 2b00 cmp r3, #0 800cf50: d043 beq.n 800cfda taskENTER_CRITICAL(); 800cf52: f001 fd27 bl 800e9a4 int8_t cTxLock = pxQueue->cTxLock; 800cf56: f895 3045 ldrb.w r3, [r5, #69] @ 0x45 800cf5a: b25c sxtb r4, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800cf5c: 2c00 cmp r4, #0 800cf5e: dd14 ble.n 800cf8a if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cf60: f105 0624 add.w r6, r5, #36 @ 0x24 800cf64: e003 b.n 800cf6e --cTxLock; 800cf66: 1e63 subs r3, r4, #1 800cf68: b2da uxtb r2, r3 800cf6a: b25c sxtb r4, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800cf6c: b16a cbz r2, 800cf8a if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800cf6e: 6a6b ldr r3, [r5, #36] @ 0x24 if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cf70: 4630 mov r0, r6 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800cf72: b153 cbz r3, 800cf8a if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800cf74: f000 fe20 bl 800dbb8 800cf78: 2800 cmp r0, #0 800cf7a: d0f4 beq.n 800cf66 vTaskMissedYield(); 800cf7c: f000 fecc bl 800dd18 --cTxLock; 800cf80: 1e63 subs r3, r4, #1 800cf82: b2da uxtb r2, r3 800cf84: b25c sxtb r4, r3 while( cTxLock > queueLOCKED_UNMODIFIED ) 800cf86: 2a00 cmp r2, #0 800cf88: d1f1 bne.n 800cf6e pxQueue->cTxLock = queueUNLOCKED; 800cf8a: 23ff movs r3, #255 @ 0xff 800cf8c: f885 3045 strb.w r3, [r5, #69] @ 0x45 taskEXIT_CRITICAL(); 800cf90: f001 fd2a bl 800e9e8 taskENTER_CRITICAL(); 800cf94: f001 fd06 bl 800e9a4 int8_t cRxLock = pxQueue->cRxLock; 800cf98: f895 3044 ldrb.w r3, [r5, #68] @ 0x44 800cf9c: b25c sxtb r4, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cf9e: 2c00 cmp r4, #0 800cfa0: dd14 ble.n 800cfcc if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cfa2: f105 0610 add.w r6, r5, #16 800cfa6: e003 b.n 800cfb0 --cRxLock; 800cfa8: 1e63 subs r3, r4, #1 800cfaa: b2da uxtb r2, r3 800cfac: b25c sxtb r4, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cfae: b16a cbz r2, 800cfcc if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cfb0: 692b ldr r3, [r5, #16] if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cfb2: 4630 mov r0, r6 if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800cfb4: b153 cbz r3, 800cfcc if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800cfb6: f000 fdff bl 800dbb8 800cfba: 2800 cmp r0, #0 800cfbc: d0f4 beq.n 800cfa8 vTaskMissedYield(); 800cfbe: f000 feab bl 800dd18 --cRxLock; 800cfc2: 1e63 subs r3, r4, #1 800cfc4: b2da uxtb r2, r3 800cfc6: b25c sxtb r4, r3 while( cRxLock > queueLOCKED_UNMODIFIED ) 800cfc8: 2a00 cmp r2, #0 800cfca: d1f1 bne.n 800cfb0 pxQueue->cRxLock = queueUNLOCKED; 800cfcc: 23ff movs r3, #255 @ 0xff 800cfce: f885 3044 strb.w r3, [r5, #68] @ 0x44 else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); } 800cfd2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} taskEXIT_CRITICAL(); 800cfd6: f001 bd07 b.w 800e9e8 vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 800cfda: 4622 mov r2, r4 800cfdc: 4631 mov r1, r6 800cfde: f105 0024 add.w r0, r5, #36 @ 0x24 800cfe2: f000 fd9f bl 800db24 800cfe6: e7b4 b.n 800cf52 0800cfe8 : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) 800cfe8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} xNextHead = pxStreamBuffer->xHead; /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 800cfec: 6883 ldr r3, [r0, #8] static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) 800cfee: 4615 mov r5, r2 xNextHead = pxStreamBuffer->xHead; 800cff0: 6847 ldr r7, [r0, #4] xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 800cff2: 1bde subs r6, r3, r7 800cff4: 4296 cmp r6, r2 800cff6: bf28 it cs 800cff8: 4616 movcs r6, r2 /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 800cffa: 19ba adds r2, r7, r6 800cffc: 4293 cmp r3, r2 800cffe: d208 bcs.n 800d012 800d000: f04f 0350 mov.w r3, #80 @ 0x50 800d004: f383 8811 msr BASEPRI, r3 800d008: f3bf 8f6f isb sy 800d00c: f3bf 8f4f dsb sy 800d010: e7fe b.n 800d010 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 800d012: 4604 mov r4, r0 800d014: 6980 ldr r0, [r0, #24] 800d016: 4632 mov r2, r6 800d018: 4688 mov r8, r1 800d01a: 4438 add r0, r7 800d01c: f002 fe49 bl 800fcb2 /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 800d020: 42b5 cmp r5, r6 800d022: d911 bls.n 800d048 { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 800d024: 1baa subs r2, r5, r6 800d026: 68a3 ldr r3, [r4, #8] 800d028: 429a cmp r2, r3 800d02a: d908 bls.n 800d03e 800d02c: f04f 0350 mov.w r3, #80 @ 0x50 800d030: f383 8811 msr BASEPRI, r3 800d034: f3bf 8f6f isb sy 800d038: f3bf 8f4f dsb sy 800d03c: e7fe b.n 800d03c ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 800d03e: eb08 0106 add.w r1, r8, r6 800d042: 69a0 ldr r0, [r4, #24] 800d044: f002 fe35 bl 800fcb2 else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 800d048: 442f add r7, r5 if( xNextHead >= pxStreamBuffer->xLength ) 800d04a: 68a3 ldr r3, [r4, #8] } pxStreamBuffer->xHead = xNextHead; return xCount; } 800d04c: 4628 mov r0, r5 if( xNextHead >= pxStreamBuffer->xLength ) 800d04e: 429f cmp r7, r3 xNextHead -= pxStreamBuffer->xLength; 800d050: bf28 it cs 800d052: 1aff subcs r7, r7, r3 pxStreamBuffer->xHead = xNextHead; 800d054: 6067 str r7, [r4, #4] } 800d056: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800d05a: bf00 nop 0800d05c : { 800d05c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 800d060: b087 sub sp, #28 800d062: 9301 str r3, [sp, #4] configASSERT( pvTxData ); 800d064: 2900 cmp r1, #0 800d066: d062 beq.n 800d12e configASSERT( pxStreamBuffer ); 800d068: 4604 mov r4, r0 800d06a: b188 cbz r0, 800d090 if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 800d06c: 7f03 ldrb r3, [r0, #28] 800d06e: 4617 mov r7, r2 800d070: 460e mov r6, r1 800d072: 07da lsls r2, r3, #31 800d074: d515 bpl.n 800d0a2 xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 800d076: f107 0804 add.w r8, r7, #4 configASSERT( xRequiredSpace > xDataLengthBytes ); 800d07a: 4547 cmp r7, r8 800d07c: d312 bcc.n 800d0a4 800d07e: f04f 0350 mov.w r3, #80 @ 0x50 800d082: f383 8811 msr BASEPRI, r3 800d086: f3bf 8f6f isb sy 800d08a: f3bf 8f4f dsb sy 800d08e: e7fe b.n 800d08e 800d090: f04f 0350 mov.w r3, #80 @ 0x50 800d094: f383 8811 msr BASEPRI, r3 800d098: f3bf 8f6f isb sy 800d09c: f3bf 8f4f dsb sy configASSERT( pxStreamBuffer ); 800d0a0: e7fe b.n 800d0a0 800d0a2: 46b8 mov r8, r7 if( xTicksToWait != ( TickType_t ) 0 ) 800d0a4: 9b01 ldr r3, [sp, #4] 800d0a6: 2b00 cmp r3, #0 800d0a8: d04a beq.n 800d140 vTaskSetTimeOutState( &xTimeOut ); 800d0aa: a804 add r0, sp, #16 800d0ac: f000 fdca bl 800dc44 taskENTER_CRITICAL(); 800d0b0: f001 fc78 bl 800e9a4 xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 800d0b4: 68a3 ldr r3, [r4, #8] 800d0b6: 6825 ldr r5, [r4, #0] ( void ) xTaskNotifyStateClear( NULL ); 800d0b8: 2000 movs r0, #0 xSpace -= pxStreamBuffer->xHead; 800d0ba: 6862 ldr r2, [r4, #4] xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 800d0bc: 441d add r5, r3 800d0be: 3d01 subs r5, #1 xSpace -= ( size_t ) 1; 800d0c0: 1aad subs r5, r5, r2 if( xSpace >= pxStreamBuffer->xLength ) 800d0c2: 42ab cmp r3, r5 xSpace -= pxStreamBuffer->xLength; 800d0c4: bf98 it ls 800d0c6: 1aed subls r5, r5, r3 if( xSpace < xRequiredSpace ) 800d0c8: 45a8 cmp r8, r5 800d0ca: d97a bls.n 800d1c2 ( void ) xTaskNotifyStateClear( NULL ); 800d0cc: f001 f8a8 bl 800e220 configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 800d0d0: f8d4 9014 ldr.w r9, [r4, #20] 800d0d4: f1b9 0f00 cmp.w r9, #0 800d0d8: d16a bne.n 800d1b0 pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 800d0da: f000 fe23 bl 800dd24 800d0de: 6160 str r0, [r4, #20] taskEXIT_CRITICAL(); 800d0e0: f001 fc82 bl 800e9e8 ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 800d0e4: 4649 mov r1, r9 800d0e6: 9b01 ldr r3, [sp, #4] 800d0e8: 464a mov r2, r9 800d0ea: 4648 mov r0, r9 800d0ec: f000 ff10 bl 800df10 } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 800d0f0: a901 add r1, sp, #4 800d0f2: a804 add r0, sp, #16 pxStreamBuffer->xTaskWaitingToSend = NULL; 800d0f4: f8c4 9014 str.w r9, [r4, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 800d0f8: f000 fdcc bl 800dc94 800d0fc: 2800 cmp r0, #0 800d0fe: d0d7 beq.n 800d0b0 if( xSpace == ( size_t ) 0 ) 800d100: b1f5 cbz r5, 800d140 xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 800d102: 9703 str r7, [sp, #12] else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 800d104: 7f23 ldrb r3, [r4, #28] 800d106: 07db lsls r3, r3, #31 800d108: d52b bpl.n 800d162 else if( xSpace >= xRequiredSpace ) 800d10a: 4545 cmp r5, r8 800d10c: d324 bcc.n 800d158 configASSERT( xCount > ( size_t ) 0 ); 800d10e: 2204 movs r2, #4 800d110: a903 add r1, sp, #12 800d112: 4620 mov r0, r4 800d114: f7ff ff68 bl 800cfe8 xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 800d118: 9a03 ldr r2, [sp, #12] configASSERT( xCount > ( size_t ) 0 ); 800d11a: bb42 cbnz r2, 800d16e 800d11c: f04f 0350 mov.w r3, #80 @ 0x50 800d120: f383 8811 msr BASEPRI, r3 800d124: f3bf 8f6f isb sy 800d128: f3bf 8f4f dsb sy 800d12c: e7fe b.n 800d12c 800d12e: f04f 0350 mov.w r3, #80 @ 0x50 800d132: f383 8811 msr BASEPRI, r3 800d136: f3bf 8f6f isb sy 800d13a: f3bf 8f4f dsb sy configASSERT( pvTxData ); 800d13e: e7fe b.n 800d13e xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 800d140: 68a3 ldr r3, [r4, #8] 800d142: 6825 ldr r5, [r4, #0] xSpace -= pxStreamBuffer->xHead; 800d144: 6862 ldr r2, [r4, #4] xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 800d146: 441d add r5, r3 800d148: 9703 str r7, [sp, #12] 800d14a: 3d01 subs r5, #1 xSpace -= ( size_t ) 1; 800d14c: 1aad subs r5, r5, r2 if( xSpace >= pxStreamBuffer->xLength ) 800d14e: 42ab cmp r3, r5 xSpace -= pxStreamBuffer->xLength; 800d150: bf98 it ls 800d152: 1aed subls r5, r5, r3 if( xSpace == ( size_t ) 0 ) 800d154: 2d00 cmp r5, #0 800d156: d1d5 bne.n 800d104 800d158: 2500 movs r5, #0 } 800d15a: 4628 mov r0, r5 800d15c: b007 add sp, #28 800d15e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 800d162: 42bd cmp r5, r7 800d164: 462a mov r2, r5 800d166: bf28 it cs 800d168: 463a movcs r2, r7 800d16a: 9203 str r2, [sp, #12] if( xShouldWrite != pdFALSE ) 800d16c: e7d5 b.n 800d11a 800d16e: 4631 mov r1, r6 800d170: 4620 mov r0, r4 800d172: f7ff ff39 bl 800cfe8 if( xReturn > ( size_t ) 0 ) 800d176: 4605 mov r5, r0 800d178: 2800 cmp r0, #0 800d17a: d0ed beq.n 800d158 static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 800d17c: 68a2 ldr r2, [r4, #8] 800d17e: 6863 ldr r3, [r4, #4] xCount -= pxStreamBuffer->xTail; 800d180: 6821 ldr r1, [r4, #0] xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 800d182: 4413 add r3, r2 xCount -= pxStreamBuffer->xTail; 800d184: 1a5b subs r3, r3, r1 if ( xCount >= pxStreamBuffer->xLength ) 800d186: 429a cmp r2, r3 { xCount -= pxStreamBuffer->xLength; 800d188: bf98 it ls 800d18a: 1a9b subls r3, r3, r2 if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 800d18c: 68e2 ldr r2, [r4, #12] 800d18e: 429a cmp r2, r3 800d190: d8e3 bhi.n 800d15a sbSEND_COMPLETED( pxStreamBuffer ); 800d192: f000 fbff bl 800d994 800d196: 6923 ldr r3, [r4, #16] 800d198: b13b cbz r3, 800d1aa 800d19a: 2300 movs r3, #0 800d19c: 6920 ldr r0, [r4, #16] 800d19e: 461a mov r2, r3 800d1a0: 4619 mov r1, r3 800d1a2: f000 ff2b bl 800dffc 800d1a6: 2300 movs r3, #0 800d1a8: 6123 str r3, [r4, #16] 800d1aa: f000 fbfb bl 800d9a4 return xReturn; 800d1ae: e7d4 b.n 800d15a 800d1b0: f04f 0350 mov.w r3, #80 @ 0x50 800d1b4: f383 8811 msr BASEPRI, r3 800d1b8: f3bf 8f6f isb sy 800d1bc: f3bf 8f4f dsb sy configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 800d1c0: e7fe b.n 800d1c0 taskEXIT_CRITICAL(); 800d1c2: f001 fc11 bl 800e9e8 break; 800d1c6: e79b b.n 800d100 0800d1c8 : } } /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 800d1c8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800d1cc: 4605 mov r5, r0 /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 800d1ce: f001 fbe9 bl 800e9a4 { uxCurrentNumberOfTasks++; 800d1d2: 4a34 ldr r2, [pc, #208] @ (800d2a4 ) if( pxCurrentTCB == NULL ) 800d1d4: 4e34 ldr r6, [pc, #208] @ (800d2a8 ) uxCurrentNumberOfTasks++; 800d1d6: 6813 ldr r3, [r2, #0] 800d1d8: 3301 adds r3, #1 800d1da: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 800d1dc: 6833 ldr r3, [r6, #0] 800d1de: 2b00 cmp r3, #0 800d1e0: d031 beq.n 800d246 else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 800d1e2: 4c32 ldr r4, [pc, #200] @ (800d2ac ) { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 800d1e4: 6ae8 ldr r0, [r5, #44] @ 0x2c if( xSchedulerRunning == pdFALSE ) 800d1e6: 6823 ldr r3, [r4, #0] 800d1e8: b333 cbz r3, 800d238 800d1ea: 4f31 ldr r7, [pc, #196] @ (800d2b0 ) { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 800d1ec: 4a31 ldr r2, [pc, #196] @ (800d2b4 ) pxNewTCB->uxTCBNumber = uxTaskNumber; } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 800d1ee: 4932 ldr r1, [pc, #200] @ (800d2b8 ) uxTaskNumber++; 800d1f0: 6813 ldr r3, [r2, #0] 800d1f2: 3301 adds r3, #1 800d1f4: 6013 str r3, [r2, #0] pxNewTCB->uxTCBNumber = uxTaskNumber; 800d1f6: 646b str r3, [r5, #68] @ 0x44 prvAddTaskToReadyList( pxNewTCB ); 800d1f8: 680b ldr r3, [r1, #0] 800d1fa: 4283 cmp r3, r0 800d1fc: d200 bcs.n 800d200 800d1fe: 6008 str r0, [r1, #0] 800d200: eb00 0080 add.w r0, r0, r0, lsl #2 800d204: 1d29 adds r1, r5, #4 800d206: eb07 0080 add.w r0, r7, r0, lsl #2 800d20a: f7fe ff23 bl 800c054 portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 800d20e: f001 fbeb bl 800e9e8 if( xSchedulerRunning != pdFALSE ) 800d212: 6823 ldr r3, [r4, #0] 800d214: b173 cbz r3, 800d234 { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 800d216: 6832 ldr r2, [r6, #0] 800d218: 6aeb ldr r3, [r5, #44] @ 0x2c 800d21a: 6ad2 ldr r2, [r2, #44] @ 0x2c 800d21c: 429a cmp r2, r3 800d21e: d209 bcs.n 800d234 { taskYIELD_IF_USING_PREEMPTION(); 800d220: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800d224: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800d228: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800d22c: f3bf 8f4f dsb sy 800d230: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 800d234: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 800d238: 6833 ldr r3, [r6, #0] 800d23a: 4f1d ldr r7, [pc, #116] @ (800d2b0 ) 800d23c: 6adb ldr r3, [r3, #44] @ 0x2c 800d23e: 4283 cmp r3, r0 800d240: d8d4 bhi.n 800d1ec pxCurrentTCB = pxNewTCB; 800d242: 6035 str r5, [r6, #0] 800d244: e7d2 b.n 800d1ec pxCurrentTCB = pxNewTCB; 800d246: 6035 str r5, [r6, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 800d248: 6813 ldr r3, [r2, #0] 800d24a: 2b01 cmp r3, #1 800d24c: d003 beq.n 800d256 if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 800d24e: 6ae8 ldr r0, [r5, #44] @ 0x2c 800d250: 4f17 ldr r7, [pc, #92] @ (800d2b0 ) 800d252: 4c16 ldr r4, [pc, #88] @ (800d2ac ) 800d254: e7ca b.n 800d1ec 800d256: 4f16 ldr r7, [pc, #88] @ (800d2b0 ) 800d258: 463c mov r4, r7 800d25a: f507 688c add.w r8, r7, #1120 @ 0x460 { UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 800d25e: 4620 mov r0, r4 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 800d260: 3414 adds r4, #20 vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 800d262: f7fe fee7 bl 800c034 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 800d266: 45a0 cmp r8, r4 800d268: d1f9 bne.n 800d25e } vListInitialise( &xDelayedTaskList1 ); 800d26a: f8df 9064 ldr.w r9, [pc, #100] @ 800d2d0 vListInitialise( &xDelayedTaskList2 ); 800d26e: f8df 8064 ldr.w r8, [pc, #100] @ 800d2d4 vListInitialise( &xDelayedTaskList1 ); 800d272: 4648 mov r0, r9 800d274: 4c0d ldr r4, [pc, #52] @ (800d2ac ) 800d276: f7fe fedd bl 800c034 vListInitialise( &xDelayedTaskList2 ); 800d27a: 4640 mov r0, r8 800d27c: f7fe feda bl 800c034 vListInitialise( &xPendingReadyList ); 800d280: 480e ldr r0, [pc, #56] @ (800d2bc ) 800d282: f7fe fed7 bl 800c034 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 800d286: 480e ldr r0, [pc, #56] @ (800d2c0 ) 800d288: f7fe fed4 bl 800c034 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 800d28c: 480d ldr r0, [pc, #52] @ (800d2c4 ) 800d28e: f7fe fed1 bl 800c034 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 800d292: 4b0d ldr r3, [pc, #52] @ (800d2c8 ) prvAddTaskToReadyList( pxNewTCB ); 800d294: 6ae8 ldr r0, [r5, #44] @ 0x2c pxDelayedTaskList = &xDelayedTaskList1; 800d296: f8c3 9000 str.w r9, [r3] pxOverflowDelayedTaskList = &xDelayedTaskList2; 800d29a: 4b0c ldr r3, [pc, #48] @ (800d2cc ) 800d29c: f8c3 8000 str.w r8, [r3] } 800d2a0: e7a4 b.n 800d1ec 800d2a2: bf00 nop 800d2a4: 24002b6c .word 0x24002b6c 800d2a8: 24003040 .word 0x24003040 800d2ac: 24002b60 .word 0x24002b60 800d2b0: 24002be0 .word 0x24002be0 800d2b4: 24002b50 .word 0x24002b50 800d2b8: 24002b64 .word 0x24002b64 800d2bc: 24002b9c .word 0x24002b9c 800d2c0: 24002b88 .word 0x24002b88 800d2c4: 24002b70 .word 0x24002b70 800d2c8: 24002bb4 .word 0x24002bb4 800d2cc: 24002bb0 .word 0x24002bb0 800d2d0: 24002bcc .word 0x24002bcc 800d2d4: 24002bb8 .word 0x24002bb8 0800d2d8 : static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, 800d2d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800d2dc: 9c0a ldr r4, [sp, #40] @ 0x28 ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 800d2de: 0096 lsls r6, r2, #2 static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, 800d2e0: 4607 mov r7, r0 800d2e2: 460d mov r5, r1 ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 800d2e4: 4632 mov r2, r6 800d2e6: 21a5 movs r1, #165 @ 0xa5 800d2e8: 6b20 ldr r0, [r4, #48] @ 0x30 static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, 800d2ea: 4698 mov r8, r3 800d2ec: f8dd 9024 ldr.w r9, [sp, #36] @ 0x24 pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 800d2f0: 3e04 subs r6, #4 ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 800d2f2: f002 fc09 bl 800fb08 pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 800d2f6: 6b23 ldr r3, [r4, #48] @ 0x30 800d2f8: 441e add r6, r3 pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 800d2fa: f026 0607 bic.w r6, r6, #7 if( pcName != NULL ) 800d2fe: 2d00 cmp r5, #0 800d300: d072 beq.n 800d3e8 pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d302: 782b ldrb r3, [r5, #0] 800d304: f884 3034 strb.w r3, [r4, #52] @ 0x34 if( pcName[ x ] == ( char ) 0x00 ) 800d308: 2b00 cmp r3, #0 800d30a: d036 beq.n 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d30c: 786b ldrb r3, [r5, #1] 800d30e: f884 3035 strb.w r3, [r4, #53] @ 0x35 if( pcName[ x ] == ( char ) 0x00 ) 800d312: b393 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d314: 78ab ldrb r3, [r5, #2] 800d316: f884 3036 strb.w r3, [r4, #54] @ 0x36 if( pcName[ x ] == ( char ) 0x00 ) 800d31a: b373 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d31c: 78eb ldrb r3, [r5, #3] 800d31e: f884 3037 strb.w r3, [r4, #55] @ 0x37 if( pcName[ x ] == ( char ) 0x00 ) 800d322: b353 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d324: 792b ldrb r3, [r5, #4] 800d326: f884 3038 strb.w r3, [r4, #56] @ 0x38 if( pcName[ x ] == ( char ) 0x00 ) 800d32a: b333 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d32c: 796b ldrb r3, [r5, #5] 800d32e: f884 3039 strb.w r3, [r4, #57] @ 0x39 if( pcName[ x ] == ( char ) 0x00 ) 800d332: b313 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d334: 79ab ldrb r3, [r5, #6] 800d336: f884 303a strb.w r3, [r4, #58] @ 0x3a if( pcName[ x ] == ( char ) 0x00 ) 800d33a: b1f3 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d33c: 79eb ldrb r3, [r5, #7] 800d33e: f884 303b strb.w r3, [r4, #59] @ 0x3b if( pcName[ x ] == ( char ) 0x00 ) 800d342: b1d3 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d344: 7a2b ldrb r3, [r5, #8] 800d346: f884 303c strb.w r3, [r4, #60] @ 0x3c if( pcName[ x ] == ( char ) 0x00 ) 800d34a: b1b3 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d34c: 7a6b ldrb r3, [r5, #9] 800d34e: f884 303d strb.w r3, [r4, #61] @ 0x3d if( pcName[ x ] == ( char ) 0x00 ) 800d352: b193 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d354: 7aab ldrb r3, [r5, #10] 800d356: f884 303e strb.w r3, [r4, #62] @ 0x3e if( pcName[ x ] == ( char ) 0x00 ) 800d35a: b173 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d35c: 7aeb ldrb r3, [r5, #11] 800d35e: f884 303f strb.w r3, [r4, #63] @ 0x3f if( pcName[ x ] == ( char ) 0x00 ) 800d362: b153 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d364: 7b2b ldrb r3, [r5, #12] 800d366: f884 3040 strb.w r3, [r4, #64] @ 0x40 if( pcName[ x ] == ( char ) 0x00 ) 800d36a: b133 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d36c: 7b6b ldrb r3, [r5, #13] 800d36e: f884 3041 strb.w r3, [r4, #65] @ 0x41 if( pcName[ x ] == ( char ) 0x00 ) 800d372: b113 cbz r3, 800d37a pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800d374: 7bab ldrb r3, [r5, #14] 800d376: f884 3042 strb.w r3, [r4, #66] @ 0x42 pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 800d37a: 2300 movs r3, #0 800d37c: f884 3043 strb.w r3, [r4, #67] @ 0x43 if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 800d380: 9d08 ldr r5, [sp, #32] pxNewTCB->uxMutexesHeld = 0; 800d382: f04f 0a00 mov.w sl, #0 vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 800d386: 1d20 adds r0, r4, #4 if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 800d388: 2d37 cmp r5, #55 @ 0x37 pxNewTCB->uxMutexesHeld = 0; 800d38a: f8c4 a050 str.w sl, [r4, #80] @ 0x50 if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 800d38e: bf28 it cs 800d390: 2537 movcs r5, #55 @ 0x37 pxNewTCB->uxPriority = uxPriority; 800d392: 62e5 str r5, [r4, #44] @ 0x2c pxNewTCB->uxBasePriority = uxPriority; 800d394: 64e5 str r5, [r4, #76] @ 0x4c listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800d396: f1c5 0538 rsb r5, r5, #56 @ 0x38 vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 800d39a: f7fe fe57 bl 800c04c vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 800d39e: f104 0018 add.w r0, r4, #24 800d3a2: f7fe fe53 bl 800c04c _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 800d3a6: 4651 mov r1, sl 800d3a8: 224c movs r2, #76 @ 0x4c listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800d3aa: 61a5 str r5, [r4, #24] pxNewTCB->ulNotifiedValue = 0; 800d3ac: f8c4 a0a0 str.w sl, [r4, #160] @ 0xa0 _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 800d3b0: f104 0054 add.w r0, r4, #84 @ 0x54 listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 800d3b4: 6124 str r4, [r4, #16] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 800d3b6: 6264 str r4, [r4, #36] @ 0x24 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 800d3b8: f884 a0a4 strb.w sl, [r4, #164] @ 0xa4 _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 800d3bc: f002 fba4 bl 800fb08 800d3c0: 4b0b ldr r3, [pc, #44] @ (800d3f0 ) pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 800d3c2: 4642 mov r2, r8 800d3c4: 4639 mov r1, r7 _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 800d3c6: f103 0568 add.w r5, r3, #104 @ 0x68 800d3ca: 65a3 str r3, [r4, #88] @ 0x58 800d3cc: 33d0 adds r3, #208 @ 0xd0 pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 800d3ce: 4630 mov r0, r6 _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 800d3d0: 65e5 str r5, [r4, #92] @ 0x5c 800d3d2: 6623 str r3, [r4, #96] @ 0x60 pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 800d3d4: f001 faba bl 800e94c 800d3d8: 6020 str r0, [r4, #0] if( pxCreatedTask != NULL ) 800d3da: f1b9 0f00 cmp.w r9, #0 800d3de: d001 beq.n 800d3e4 *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 800d3e0: f8c9 4000 str.w r4, [r9] } 800d3e4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} pxNewTCB->pcTaskName[ 0 ] = 0x00; 800d3e8: f884 5034 strb.w r5, [r4, #52] @ 0x34 800d3ec: e7c8 b.n 800d380 800d3ee: bf00 nop 800d3f0: 24013198 .word 0x24013198 0800d3f4 : { 800d3f4: b580 push {r7, lr} 800d3f6: 4d23 ldr r5, [pc, #140] @ (800d484 ) 800d3f8: 4f23 ldr r7, [pc, #140] @ (800d488 ) 800d3fa: 4e24 ldr r6, [pc, #144] @ (800d48c ) 800d3fc: f8df 8090 ldr.w r8, [pc, #144] @ 800d490 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 800d400: 682b ldr r3, [r5, #0] 800d402: b35b cbz r3, 800d45c { taskENTER_CRITICAL(); 800d404: f001 face bl 800e9a4 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d408: 68fb ldr r3, [r7, #12] 800d40a: 68dc ldr r4, [r3, #12] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d40c: 1d20 adds r0, r4, #4 800d40e: f7fe fe47 bl 800c0a0 --uxCurrentNumberOfTasks; 800d412: 6833 ldr r3, [r6, #0] 800d414: 3b01 subs r3, #1 800d416: 6033 str r3, [r6, #0] --uxDeletedTasksWaitingCleanUp; 800d418: 682b ldr r3, [r5, #0] 800d41a: 3b01 subs r3, #1 800d41c: 602b str r3, [r5, #0] } taskEXIT_CRITICAL(); 800d41e: f001 fae3 bl 800e9e8 to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 800d422: f104 0054 add.w r0, r4, #84 @ 0x54 800d426: f002 fb8b bl 800fb40 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 800d42a: f894 30a5 ldrb.w r3, [r4, #165] @ 0xa5 800d42e: b163 cbz r3, 800d44a /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); vPortFree( pxTCB ); } else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 800d430: 2b01 cmp r3, #1 800d432: d022 beq.n 800d47a } else { /* Neither the stack nor the TCB were allocated dynamically, so nothing needs to be freed. */ configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 800d434: 2b02 cmp r3, #2 800d436: d0e3 beq.n 800d400 800d438: f04f 0350 mov.w r3, #80 @ 0x50 800d43c: f383 8811 msr BASEPRI, r3 800d440: f3bf 8f6f isb sy 800d444: f3bf 8f4f dsb sy 800d448: e7fe b.n 800d448 vPortFree( pxTCB->pxStack ); 800d44a: 6b20 ldr r0, [r4, #48] @ 0x30 800d44c: f001 fcc6 bl 800eddc vPortFree( pxTCB ); 800d450: 4620 mov r0, r4 800d452: f001 fcc3 bl 800eddc while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 800d456: 682b ldr r3, [r5, #0] 800d458: 2b00 cmp r3, #0 800d45a: d1d3 bne.n 800d404 if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 800d45c: f8d8 3000 ldr.w r3, [r8] 800d460: 2b01 cmp r3, #1 800d462: d9cd bls.n 800d400 taskYIELD(); 800d464: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800d468: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800d46c: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800d470: f3bf 8f4f dsb sy 800d474: f3bf 8f6f isb sy 800d478: e7c2 b.n 800d400 vPortFree( pxTCB ); 800d47a: 4620 mov r0, r4 800d47c: f001 fcae bl 800eddc 800d480: e7be b.n 800d400 800d482: bf00 nop 800d484: 24002b84 .word 0x24002b84 800d488: 24002b88 .word 0x24002b88 800d48c: 24002b6c .word 0x24002b6c 800d490: 24002be0 .word 0x24002be0 0800d494 : const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 800d494: 4b49 ldr r3, [pc, #292] @ (800d5bc ) BaseType_t xTaskIncrementTick( void ) 800d496: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 800d49a: 681e ldr r6, [r3, #0] BaseType_t xTaskIncrementTick( void ) 800d49c: b083 sub sp, #12 const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 800d49e: 3601 adds r6, #1 xTickCount = xConstTickCount; 800d4a0: 601e str r6, [r3, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 800d4a2: 2e00 cmp r6, #0 800d4a4: d03e beq.n 800d524 800d4a6: 4b46 ldr r3, [pc, #280] @ (800d5c0 ) 800d4a8: 9301 str r3, [sp, #4] if( xConstTickCount >= xNextTaskUnblockTime ) 800d4aa: 681b ldr r3, [r3, #0] 800d4ac: 429e cmp r6, r3 800d4ae: d346 bcc.n 800d53e if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d4b0: 4f44 ldr r7, [pc, #272] @ (800d5c4 ) 800d4b2: 683b ldr r3, [r7, #0] 800d4b4: 681d ldr r5, [r3, #0] 800d4b6: 2d00 cmp r5, #0 800d4b8: d077 beq.n 800d5aa BaseType_t xSwitchRequired = pdFALSE; 800d4ba: 2500 movs r5, #0 800d4bc: f8df 9114 ldr.w r9, [pc, #276] @ 800d5d4 800d4c0: f8df a114 ldr.w sl, [pc, #276] @ 800d5d8 prvAddTaskToReadyList( pxTCB ); 800d4c4: f8df 8114 ldr.w r8, [pc, #276] @ 800d5dc 800d4c8: e020 b.n 800d50c ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d4ca: f7fe fde9 bl 800c0a0 if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 800d4ce: 6aa3 ldr r3, [r4, #40] @ 0x28 ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 800d4d0: f104 0018 add.w r0, r4, #24 if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 800d4d4: b10b cbz r3, 800d4da ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 800d4d6: f7fe fde3 bl 800c0a0 prvAddTaskToReadyList( pxTCB ); 800d4da: 6ae3 ldr r3, [r4, #44] @ 0x2c 800d4dc: 4659 mov r1, fp 800d4de: f8d8 2000 ldr.w r2, [r8] 800d4e2: eb03 0083 add.w r0, r3, r3, lsl #2 800d4e6: 4293 cmp r3, r2 800d4e8: eb09 0080 add.w r0, r9, r0, lsl #2 800d4ec: d901 bls.n 800d4f2 800d4ee: f8c8 3000 str.w r3, [r8] 800d4f2: f7fe fdaf bl 800c054 if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 800d4f6: f8da 2000 ldr.w r2, [sl] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d4fa: 683b ldr r3, [r7, #0] if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 800d4fc: 6ae1 ldr r1, [r4, #44] @ 0x2c 800d4fe: 6ad2 ldr r2, [r2, #44] @ 0x2c if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d500: 681b ldr r3, [r3, #0] xSwitchRequired = pdTRUE; 800d502: 4291 cmp r1, r2 800d504: bf28 it cs 800d506: 2501 movcs r5, #1 if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d508: 2b00 cmp r3, #0 800d50a: d052 beq.n 800d5b2 pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d50c: 683b ldr r3, [r7, #0] 800d50e: 68db ldr r3, [r3, #12] 800d510: 68dc ldr r4, [r3, #12] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 800d512: 6863 ldr r3, [r4, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d514: f104 0b04 add.w fp, r4, #4 if( xConstTickCount < xItemValue ) 800d518: 429e cmp r6, r3 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d51a: 4658 mov r0, fp if( xConstTickCount < xItemValue ) 800d51c: d2d5 bcs.n 800d4ca xNextTaskUnblockTime = xItemValue; 800d51e: 9a01 ldr r2, [sp, #4] 800d520: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 800d522: e011 b.n 800d548 taskSWITCH_DELAYED_LISTS(); 800d524: 4b27 ldr r3, [pc, #156] @ (800d5c4 ) 800d526: 681a ldr r2, [r3, #0] 800d528: 6812 ldr r2, [r2, #0] 800d52a: b30a cbz r2, 800d570 800d52c: f04f 0350 mov.w r3, #80 @ 0x50 800d530: f383 8811 msr BASEPRI, r3 800d534: f3bf 8f6f isb sy 800d538: f3bf 8f4f dsb sy 800d53c: e7fe b.n 800d53c BaseType_t xSwitchRequired = pdFALSE; 800d53e: 2500 movs r5, #0 800d540: f8df 9090 ldr.w r9, [pc, #144] @ 800d5d4 800d544: f8df a090 ldr.w sl, [pc, #144] @ 800d5d8 if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 800d548: f8da 3000 ldr.w r3, [sl] if( xYieldPending != pdFALSE ) 800d54c: 491e ldr r1, [pc, #120] @ (800d5c8 ) if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 800d54e: 6adb ldr r3, [r3, #44] @ 0x2c 800d550: eb03 0383 add.w r3, r3, r3, lsl #2 800d554: 009b lsls r3, r3, #2 800d556: f859 2003 ldr.w r2, [r9, r3] if( xYieldPending != pdFALSE ) 800d55a: 680b ldr r3, [r1, #0] xSwitchRequired = pdTRUE; 800d55c: 2a02 cmp r2, #2 800d55e: bf28 it cs 800d560: 2501 movcs r5, #1 xSwitchRequired = pdTRUE; 800d562: 2b00 cmp r3, #0 } 800d564: bf0c ite eq 800d566: 4628 moveq r0, r5 800d568: 2001 movne r0, #1 800d56a: b003 add sp, #12 800d56c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} taskSWITCH_DELAYED_LISTS(); 800d570: 4a16 ldr r2, [pc, #88] @ (800d5cc ) 800d572: 6818 ldr r0, [r3, #0] 800d574: 6811 ldr r1, [r2, #0] 800d576: 6019 str r1, [r3, #0] 800d578: 4915 ldr r1, [pc, #84] @ (800d5d0 ) 800d57a: 6010 str r0, [r2, #0] 800d57c: 680a ldr r2, [r1, #0] 800d57e: 3201 adds r2, #1 800d580: 600a str r2, [r1, #0] static void prvResetNextTaskUnblockTime( void ) { TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d582: 681a ldr r2, [r3, #0] 800d584: 6812 ldr r2, [r2, #0] 800d586: b93a cbnz r2, 800d598 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 800d588: 4b0d ldr r3, [pc, #52] @ (800d5c0 ) 800d58a: 461a mov r2, r3 800d58c: 9301 str r3, [sp, #4] 800d58e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d592: 6013 str r3, [r2, #0] 800d594: 4613 mov r3, r2 800d596: e788 b.n 800d4aa { /* The new current delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d598: 681b ldr r3, [r3, #0] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 800d59a: 4a09 ldr r2, [pc, #36] @ (800d5c0 ) ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d59c: 68db ldr r3, [r3, #12] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 800d59e: 9201 str r2, [sp, #4] 800d5a0: 68db ldr r3, [r3, #12] 800d5a2: 685b ldr r3, [r3, #4] 800d5a4: 6013 str r3, [r2, #0] 800d5a6: 4613 mov r3, r2 } } 800d5a8: e77f b.n 800d4aa 800d5aa: f8df 9028 ldr.w r9, [pc, #40] @ 800d5d4 800d5ae: f8df a028 ldr.w sl, [pc, #40] @ 800d5d8 xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800d5b2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d5b6: 9a01 ldr r2, [sp, #4] 800d5b8: 6013 str r3, [r2, #0] break; 800d5ba: e7c5 b.n 800d548 800d5bc: 24002b68 .word 0x24002b68 800d5c0: 24002b4c .word 0x24002b4c 800d5c4: 24002bb4 .word 0x24002bb4 800d5c8: 24002b58 .word 0x24002b58 800d5cc: 24002bb0 .word 0x24002bb0 800d5d0: 24002b54 .word 0x24002b54 800d5d4: 24002be0 .word 0x24002be0 800d5d8: 24003040 .word 0x24003040 800d5dc: 24002b64 .word 0x24002b64 0800d5e0 : BaseType_t xTaskResumeAll( void ) 800d5e0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} --uxSchedulerSuspended; 800d5e4: 4d43 ldr r5, [pc, #268] @ (800d6f4 ) taskENTER_CRITICAL(); 800d5e6: f001 f9dd bl 800e9a4 --uxSchedulerSuspended; 800d5ea: 682b ldr r3, [r5, #0] 800d5ec: 3b01 subs r3, #1 800d5ee: 602b str r3, [r5, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800d5f0: 682b ldr r3, [r5, #0] 800d5f2: 2b00 cmp r3, #0 800d5f4: d168 bne.n 800d6c8 if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 800d5f6: 4b40 ldr r3, [pc, #256] @ (800d6f8 ) 800d5f8: 681b ldr r3, [r3, #0] 800d5fa: 2b00 cmp r3, #0 800d5fc: d064 beq.n 800d6c8 while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 800d5fe: 4e3f ldr r6, [pc, #252] @ (800d6fc ) 800d600: 6833 ldr r3, [r6, #0] 800d602: 2b00 cmp r3, #0 800d604: d073 beq.n 800d6ee 800d606: 4f3e ldr r7, [pc, #248] @ (800d700 ) 800d608: f8df 9104 ldr.w r9, [pc, #260] @ 800d710 800d60c: f8df 8104 ldr.w r8, [pc, #260] @ 800d714 800d610: f8df a104 ldr.w sl, [pc, #260] @ 800d718 pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d614: 68f3 ldr r3, [r6, #12] 800d616: f8d3 b00c ldr.w fp, [r3, #12] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d61a: f10b 0404 add.w r4, fp, #4 ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 800d61e: f10b 0018 add.w r0, fp, #24 800d622: f7fe fd3d bl 800c0a0 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d626: 4620 mov r0, r4 800d628: f7fe fd3a bl 800c0a0 prvAddTaskToReadyList( pxTCB ); 800d62c: f8db 202c ldr.w r2, [fp, #44] @ 0x2c 800d630: 4621 mov r1, r4 800d632: 683c ldr r4, [r7, #0] 800d634: eb02 0082 add.w r0, r2, r2, lsl #2 800d638: 42a2 cmp r2, r4 800d63a: eb09 0080 add.w r0, r9, r0, lsl #2 800d63e: d900 bls.n 800d642 800d640: 603a str r2, [r7, #0] 800d642: f7fe fd07 bl 800c054 if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 800d646: f8d8 1000 ldr.w r1, [r8] 800d64a: f8db 202c ldr.w r2, [fp, #44] @ 0x2c 800d64e: 6acb ldr r3, [r1, #44] @ 0x2c 800d650: 429a cmp r2, r3 800d652: d33f bcc.n 800d6d4 xYieldPending = pdTRUE; 800d654: 2301 movs r3, #1 800d656: f8ca 3000 str.w r3, [sl] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 800d65a: 6833 ldr r3, [r6, #0] 800d65c: 2b00 cmp r3, #0 800d65e: d1d9 bne.n 800d614 if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d660: 4b28 ldr r3, [pc, #160] @ (800d704 ) 800d662: 681a ldr r2, [r3, #0] 800d664: 6812 ldr r2, [r2, #0] 800d666: 2a00 cmp r2, #0 800d668: d03c beq.n 800d6e4 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d66a: 681a ldr r2, [r3, #0] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 800d66c: 4b26 ldr r3, [pc, #152] @ (800d708 ) ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d66e: 68d2 ldr r2, [r2, #12] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 800d670: 68d2 ldr r2, [r2, #12] 800d672: 6852 ldr r2, [r2, #4] 800d674: 601a str r2, [r3, #0] TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 800d676: 4e25 ldr r6, [pc, #148] @ (800d70c ) 800d678: 6834 ldr r4, [r6, #0] if( xPendedCounts > ( TickType_t ) 0U ) 800d67a: b194 cbz r4, 800d6a2 xYieldPending = pdTRUE; 800d67c: 2701 movs r7, #1 800d67e: e006 b.n 800d68e 800d680: f7ff ff08 bl 800d494 if( xTaskIncrementTick() != pdFALSE ) 800d684: b108 cbz r0, 800d68a xYieldPending = pdTRUE; 800d686: f8ca 7000 str.w r7, [sl] } while( xPendedCounts > ( TickType_t ) 0U ); 800d68a: 3c01 subs r4, #1 800d68c: d008 beq.n 800d6a0 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800d68e: 682b ldr r3, [r5, #0] 800d690: 2b00 cmp r3, #0 800d692: d0f5 beq.n 800d680 ++xPendedTicks; 800d694: 6833 ldr r3, [r6, #0] } while( xPendedCounts > ( TickType_t ) 0U ); 800d696: 3c01 subs r4, #1 ++xPendedTicks; 800d698: f103 0301 add.w r3, r3, #1 800d69c: 6033 str r3, [r6, #0] } while( xPendedCounts > ( TickType_t ) 0U ); 800d69e: d1f6 bne.n 800d68e xPendedTicks = 0; 800d6a0: 6034 str r4, [r6, #0] if( xYieldPending != pdFALSE ) 800d6a2: f8da 3000 ldr.w r3, [sl] 800d6a6: b17b cbz r3, 800d6c8 taskYIELD_IF_USING_PREEMPTION(); 800d6a8: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800d6ac: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800d6b0: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800d6b4: f3bf 8f4f dsb sy 800d6b8: f3bf 8f6f isb sy xAlreadyYielded = pdTRUE; 800d6bc: 2401 movs r4, #1 taskEXIT_CRITICAL(); 800d6be: f001 f993 bl 800e9e8 } 800d6c2: 4620 mov r0, r4 800d6c4: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} BaseType_t xAlreadyYielded = pdFALSE; 800d6c8: 2400 movs r4, #0 taskEXIT_CRITICAL(); 800d6ca: f001 f98d bl 800e9e8 } 800d6ce: 4620 mov r0, r4 800d6d0: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 800d6d4: 6833 ldr r3, [r6, #0] 800d6d6: 2b00 cmp r3, #0 800d6d8: d19c bne.n 800d614 if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d6da: 4b0a ldr r3, [pc, #40] @ (800d704 ) 800d6dc: 681a ldr r2, [r3, #0] 800d6de: 6812 ldr r2, [r2, #0] 800d6e0: 2a00 cmp r2, #0 800d6e2: d1c2 bne.n 800d66a xNextTaskUnblockTime = portMAX_DELAY; 800d6e4: 4b08 ldr r3, [pc, #32] @ (800d708 ) 800d6e6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800d6ea: 601a str r2, [r3, #0] 800d6ec: e7c3 b.n 800d676 800d6ee: f8df a028 ldr.w sl, [pc, #40] @ 800d718 800d6f2: e7c0 b.n 800d676 800d6f4: 24002b48 .word 0x24002b48 800d6f8: 24002b6c .word 0x24002b6c 800d6fc: 24002b9c .word 0x24002b9c 800d700: 24002b64 .word 0x24002b64 800d704: 24002bb4 .word 0x24002bb4 800d708: 24002b4c .word 0x24002b4c 800d70c: 24002b5c .word 0x24002b5c 800d710: 24002be0 .word 0x24002be0 800d714: 24003040 .word 0x24003040 800d718: 24002b58 .word 0x24002b58 0800d71c : { 800d71c: b530 push {r4, r5, lr} 800d71e: b087 sub sp, #28 800d720: 9c0b ldr r4, [sp, #44] @ 0x2c configASSERT( puxStackBuffer != NULL ); 800d722: b1c4 cbz r4, 800d756 configASSERT( pxTaskBuffer != NULL ); 800d724: 9d0c ldr r5, [sp, #48] @ 0x30 800d726: b16d cbz r5, 800d744 volatile size_t xSize = sizeof( StaticTask_t ); 800d728: 25a8 movs r5, #168 @ 0xa8 800d72a: 9505 str r5, [sp, #20] configASSERT( xSize == sizeof( TCB_t ) ); 800d72c: 9d05 ldr r5, [sp, #20] 800d72e: 2da8 cmp r5, #168 @ 0xa8 800d730: d01a beq.n 800d768 800d732: f04f 0350 mov.w r3, #80 @ 0x50 800d736: f383 8811 msr BASEPRI, r3 800d73a: f3bf 8f6f isb sy 800d73e: f3bf 8f4f dsb sy 800d742: e7fe b.n 800d742 800d744: f04f 0350 mov.w r3, #80 @ 0x50 800d748: f383 8811 msr BASEPRI, r3 800d74c: f3bf 8f6f isb sy 800d750: f3bf 8f4f dsb sy configASSERT( pxTaskBuffer != NULL ); 800d754: e7fe b.n 800d754 800d756: f04f 0350 mov.w r3, #80 @ 0x50 800d75a: f383 8811 msr BASEPRI, r3 800d75e: f3bf 8f6f isb sy 800d762: f3bf 8f4f dsb sy configASSERT( puxStackBuffer != NULL ); 800d766: e7fe b.n 800d766 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 800d768: 9d0c ldr r5, [sp, #48] @ 0x30 800d76a: 632c str r4, [r5, #48] @ 0x30 pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 800d76c: 2402 movs r4, #2 prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 800d76e: 9502 str r5, [sp, #8] 800d770: 9d0a ldr r5, [sp, #40] @ 0x28 800d772: 9500 str r5, [sp, #0] pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 800d774: 9d0c ldr r5, [sp, #48] @ 0x30 800d776: f885 40a5 strb.w r4, [r5, #165] @ 0xa5 prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 800d77a: ac04 add r4, sp, #16 ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 800d77c: 9d05 ldr r5, [sp, #20] prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 800d77e: 9401 str r4, [sp, #4] 800d780: f7ff fdaa bl 800d2d8 prvAddNewTaskToReadyList( pxNewTCB ); 800d784: 980c ldr r0, [sp, #48] @ 0x30 800d786: f7ff fd1f bl 800d1c8 } 800d78a: 9804 ldr r0, [sp, #16] 800d78c: b007 add sp, #28 800d78e: bd30 pop {r4, r5, pc} 0800d790 : { 800d790: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 800d794: 4607 mov r7, r0 800d796: b085 sub sp, #20 pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 800d798: 0090 lsls r0, r2, #2 { 800d79a: 4615 mov r5, r2 800d79c: 4688 mov r8, r1 800d79e: 4699 mov r9, r3 pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 800d7a0: f001 fa60 bl 800ec64 if( pxStack != NULL ) 800d7a4: b1f0 cbz r0, 800d7e4 pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 800d7a6: 4604 mov r4, r0 800d7a8: 20a8 movs r0, #168 @ 0xa8 800d7aa: f001 fa5b bl 800ec64 if( pxNewTCB != NULL ) 800d7ae: 4606 mov r6, r0 800d7b0: b1a8 cbz r0, 800d7de pxNewTCB->pxStack = pxStack; 800d7b2: 6304 str r4, [r0, #48] @ 0x30 pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 800d7b4: 2400 movs r4, #0 prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 800d7b6: 464b mov r3, r9 800d7b8: 462a mov r2, r5 pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 800d7ba: f886 40a5 strb.w r4, [r6, #165] @ 0xa5 prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 800d7be: 4641 mov r1, r8 800d7c0: 9c0d ldr r4, [sp, #52] @ 0x34 800d7c2: 4638 mov r0, r7 800d7c4: 9602 str r6, [sp, #8] 800d7c6: 9401 str r4, [sp, #4] 800d7c8: 9c0c ldr r4, [sp, #48] @ 0x30 800d7ca: 9400 str r4, [sp, #0] 800d7cc: f7ff fd84 bl 800d2d8 prvAddNewTaskToReadyList( pxNewTCB ); 800d7d0: 4630 mov r0, r6 800d7d2: f7ff fcf9 bl 800d1c8 xReturn = pdPASS; 800d7d6: 2001 movs r0, #1 } 800d7d8: b005 add sp, #20 800d7da: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} vPortFree( pxStack ); 800d7de: 4620 mov r0, r4 800d7e0: f001 fafc bl 800eddc xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 800d7e4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff } 800d7e8: b005 add sp, #20 800d7ea: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 800d7ee: bf00 nop 0800d7f0 : { 800d7f0: b5f8 push {r3, r4, r5, r6, r7, lr} if( xTicksToDelay > ( TickType_t ) 0U ) 800d7f2: b950 cbnz r0, 800d80a portYIELD_WITHIN_API(); 800d7f4: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800d7f8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800d7fc: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800d800: f3bf 8f4f dsb sy 800d804: f3bf 8f6f isb sy } 800d808: bdf8 pop {r3, r4, r5, r6, r7, pc} configASSERT( uxSchedulerSuspended == 0 ); 800d80a: 4d1e ldr r5, [pc, #120] @ (800d884 ) 800d80c: 682b ldr r3, [r5, #0] 800d80e: b143 cbz r3, 800d822 800d810: f04f 0350 mov.w r3, #80 @ 0x50 800d814: f383 8811 msr BASEPRI, r3 800d818: f3bf 8f6f isb sy 800d81c: f3bf 8f4f dsb sy 800d820: e7fe b.n 800d820 ++uxSchedulerSuspended; 800d822: 682b ldr r3, [r5, #0] 800d824: 4604 mov r4, r0 800d826: 3301 adds r3, #1 800d828: 602b str r3, [r5, #0] /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 800d82a: 4b17 ldr r3, [pc, #92] @ (800d888 ) } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800d82c: 4e17 ldr r6, [pc, #92] @ (800d88c ) const TickType_t xConstTickCount = xTickCount; 800d82e: 681f ldr r7, [r3, #0] if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800d830: 6830 ldr r0, [r6, #0] 800d832: 3004 adds r0, #4 800d834: f7fe fc34 bl 800c0a0 else { /* Calculate the time at which the task should be woken if the event does not occur. This may overflow but this doesn't matter, the kernel will manage it correctly. */ xTimeToWake = xConstTickCount + xTicksToWait; 800d838: 19e4 adds r4, r4, r7 /* The list item will be inserted in wake time order. */ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 800d83a: 6833 ldr r3, [r6, #0] 800d83c: 605c str r4, [r3, #4] if( xTimeToWake < xConstTickCount ) 800d83e: d315 bcc.n 800d86c { /* Wake time has overflowed. Place this item in the overflow list. */ vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800d840: 4b13 ldr r3, [pc, #76] @ (800d890 ) 800d842: 6818 ldr r0, [r3, #0] 800d844: 6831 ldr r1, [r6, #0] 800d846: 3104 adds r1, #4 800d848: f7fe fc12 bl 800c070 configASSERT( uxSchedulerSuspended ); 800d84c: 682b ldr r3, [r5, #0] 800d84e: b943 cbnz r3, 800d862 800d850: f04f 0350 mov.w r3, #80 @ 0x50 800d854: f383 8811 msr BASEPRI, r3 800d858: f3bf 8f6f isb sy 800d85c: f3bf 8f4f dsb sy 800d860: e7fe b.n 800d860 800d862: f7ff febd bl 800d5e0 if( xAlreadyYielded == pdFALSE ) 800d866: 2800 cmp r0, #0 800d868: d0c4 beq.n 800d7f4 } 800d86a: bdf8 pop {r3, r4, r5, r6, r7, pc} } else { /* The wake time has not overflowed, so the current block list is used. */ vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800d86c: 4b09 ldr r3, [pc, #36] @ (800d894 ) 800d86e: 6818 ldr r0, [r3, #0] 800d870: 6831 ldr r1, [r6, #0] 800d872: 3104 adds r1, #4 800d874: f7fe fbfc bl 800c070 /* If the task entering the blocked state was placed at the head of the list of blocked tasks then xNextTaskUnblockTime needs to be updated too. */ if( xTimeToWake < xNextTaskUnblockTime ) 800d878: 4b07 ldr r3, [pc, #28] @ (800d898 ) 800d87a: 681a ldr r2, [r3, #0] 800d87c: 4294 cmp r4, r2 800d87e: d2e5 bcs.n 800d84c { xNextTaskUnblockTime = xTimeToWake; 800d880: 601c str r4, [r3, #0] 800d882: e7e3 b.n 800d84c 800d884: 24002b48 .word 0x24002b48 800d888: 24002b68 .word 0x24002b68 800d88c: 24003040 .word 0x24003040 800d890: 24002bb0 .word 0x24002bb0 800d894: 24002bb4 .word 0x24002bb4 800d898: 24002b4c .word 0x24002b4c 0800d89c : { 800d89c: b530 push {r4, r5, lr} 800d89e: b08b sub sp, #44 @ 0x2c StaticTask_t *pxIdleTaskTCBBuffer = NULL; 800d8a0: 2400 movs r4, #0 vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 800d8a2: aa07 add r2, sp, #28 800d8a4: a906 add r1, sp, #24 800d8a6: a805 add r0, sp, #20 StackType_t *pxIdleTaskStackBuffer = NULL; 800d8a8: e9cd 4405 strd r4, r4, [sp, #20] vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 800d8ac: f7fe fba2 bl 800bff4 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 800d8b0: 9d05 ldr r5, [sp, #20] 800d8b2: e9dd 3206 ldrd r3, r2, [sp, #24] configASSERT( puxStackBuffer != NULL ); 800d8b6: b1bb cbz r3, 800d8e8 configASSERT( pxTaskBuffer != NULL ); 800d8b8: b16d cbz r5, 800d8d6 volatile size_t xSize = sizeof( StaticTask_t ); 800d8ba: 21a8 movs r1, #168 @ 0xa8 800d8bc: 9109 str r1, [sp, #36] @ 0x24 configASSERT( xSize == sizeof( TCB_t ) ); 800d8be: 9909 ldr r1, [sp, #36] @ 0x24 800d8c0: 29a8 cmp r1, #168 @ 0xa8 800d8c2: d01a beq.n 800d8fa 800d8c4: f04f 0350 mov.w r3, #80 @ 0x50 800d8c8: f383 8811 msr BASEPRI, r3 800d8cc: f3bf 8f6f isb sy 800d8d0: f3bf 8f4f dsb sy 800d8d4: e7fe b.n 800d8d4 800d8d6: f04f 0350 mov.w r3, #80 @ 0x50 800d8da: f383 8811 msr BASEPRI, r3 800d8de: f3bf 8f6f isb sy 800d8e2: f3bf 8f4f dsb sy configASSERT( pxTaskBuffer != NULL ); 800d8e6: e7fe b.n 800d8e6 800d8e8: f04f 0350 mov.w r3, #80 @ 0x50 800d8ec: f383 8811 msr BASEPRI, r3 800d8f0: f3bf 8f6f isb sy 800d8f4: f3bf 8f4f dsb sy configASSERT( puxStackBuffer != NULL ); 800d8f8: e7fe b.n 800d8f8 pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 800d8fa: 2102 movs r1, #2 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 800d8fc: 632b str r3, [r5, #48] @ 0x30 prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 800d8fe: 481e ldr r0, [pc, #120] @ (800d978 ) pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 800d900: f885 10a5 strb.w r1, [r5, #165] @ 0xa5 prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 800d904: a908 add r1, sp, #32 ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 800d906: 9b09 ldr r3, [sp, #36] @ 0x24 prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 800d908: 4623 mov r3, r4 800d90a: 9400 str r4, [sp, #0] 800d90c: e9cd 1501 strd r1, r5, [sp, #4] 800d910: 491a ldr r1, [pc, #104] @ (800d97c ) 800d912: f7ff fce1 bl 800d2d8 prvAddNewTaskToReadyList( pxNewTCB ); 800d916: 4628 mov r0, r5 800d918: f7ff fc56 bl 800d1c8 return xReturn; 800d91c: 9b08 ldr r3, [sp, #32] if( xIdleTaskHandle != NULL ) 800d91e: b17b cbz r3, 800d940 xReturn = xTimerCreateTimerTask(); 800d920: f000 fe30 bl 800e584 if( xReturn == pdPASS ) 800d924: 2801 cmp r0, #1 xReturn = xTimerCreateTimerTask(); 800d926: 4603 mov r3, r0 if( xReturn == pdPASS ) 800d928: d00c beq.n 800d944 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 800d92a: 3301 adds r3, #1 800d92c: d108 bne.n 800d940 800d92e: f04f 0350 mov.w r3, #80 @ 0x50 800d932: f383 8811 msr BASEPRI, r3 800d936: f3bf 8f6f isb sy 800d93a: f3bf 8f4f dsb sy 800d93e: e7fe b.n 800d93e } 800d940: b00b add sp, #44 @ 0x2c 800d942: bd30 pop {r4, r5, pc} 800d944: f04f 0250 mov.w r2, #80 @ 0x50 800d948: f382 8811 msr BASEPRI, r2 800d94c: f3bf 8f6f isb sy 800d950: f3bf 8f4f dsb sy _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 800d954: 4a0a ldr r2, [pc, #40] @ (800d980 ) 800d956: 490b ldr r1, [pc, #44] @ (800d984 ) 800d958: 6812 ldr r2, [r2, #0] xNextTaskUnblockTime = portMAX_DELAY; 800d95a: 480b ldr r0, [pc, #44] @ (800d988 ) _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 800d95c: 3254 adds r2, #84 @ 0x54 800d95e: 600a str r2, [r1, #0] xNextTaskUnblockTime = portMAX_DELAY; 800d960: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff xSchedulerRunning = pdTRUE; 800d964: 4909 ldr r1, [pc, #36] @ (800d98c ) xNextTaskUnblockTime = portMAX_DELAY; 800d966: 6002 str r2, [r0, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 800d968: 4a09 ldr r2, [pc, #36] @ (800d990 ) xSchedulerRunning = pdTRUE; 800d96a: 600b str r3, [r1, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 800d96c: 6014 str r4, [r2, #0] } 800d96e: b00b add sp, #44 @ 0x2c 800d970: e8bd 4030 ldmia.w sp!, {r4, r5, lr} if( xPortStartScheduler() != pdFALSE ) 800d974: f001 b8a8 b.w 800eac8 800d978: 0800d3f5 .word 0x0800d3f5 800d97c: 08011a54 .word 0x08011a54 800d980: 24003040 .word 0x24003040 800d984: 24000054 .word 0x24000054 800d988: 24002b4c .word 0x24002b4c 800d98c: 24002b60 .word 0x24002b60 800d990: 24002b68 .word 0x24002b68 0800d994 : ++uxSchedulerSuspended; 800d994: 4a02 ldr r2, [pc, #8] @ (800d9a0 ) 800d996: 6813 ldr r3, [r2, #0] 800d998: 3301 adds r3, #1 800d99a: 6013 str r3, [r2, #0] } 800d99c: 4770 bx lr 800d99e: bf00 nop 800d9a0: 24002b48 .word 0x24002b48 0800d9a4 : configASSERT( uxSchedulerSuspended ); 800d9a4: 4b06 ldr r3, [pc, #24] @ (800d9c0 ) 800d9a6: 681b ldr r3, [r3, #0] 800d9a8: b943 cbnz r3, 800d9bc 800d9aa: f04f 0350 mov.w r3, #80 @ 0x50 800d9ae: f383 8811 msr BASEPRI, r3 800d9b2: f3bf 8f6f isb sy 800d9b6: f3bf 8f4f dsb sy 800d9ba: e7fe b.n 800d9ba 800d9bc: f7ff be10 b.w 800d5e0 800d9c0: 24002b48 .word 0x24002b48 0800d9c4 : xTicks = xTickCount; 800d9c4: 4b01 ldr r3, [pc, #4] @ (800d9cc ) 800d9c6: 6818 ldr r0, [r3, #0] } 800d9c8: 4770 bx lr 800d9ca: bf00 nop 800d9cc: 24002b68 .word 0x24002b68 0800d9d0 : if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800d9d0: 4b05 ldr r3, [pc, #20] @ (800d9e8 ) 800d9d2: 681b ldr r3, [r3, #0] 800d9d4: b90b cbnz r3, 800d9da 800d9d6: f7ff bd5d b.w 800d494 ++xPendedTicks; 800d9da: 4a04 ldr r2, [pc, #16] @ (800d9ec ) } 800d9dc: 2000 movs r0, #0 ++xPendedTicks; 800d9de: 6813 ldr r3, [r2, #0] 800d9e0: 3301 adds r3, #1 800d9e2: 6013 str r3, [r2, #0] } 800d9e4: 4770 bx lr 800d9e6: bf00 nop 800d9e8: 24002b48 .word 0x24002b48 800d9ec: 24002b5c .word 0x24002b5c 0800d9f0 : { 800d9f0: b538 push {r3, r4, r5, lr} if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 800d9f2: 4b24 ldr r3, [pc, #144] @ (800da84 ) 800d9f4: 681b ldr r3, [r3, #0] 800d9f6: b11b cbz r3, 800da00 xYieldPending = pdTRUE; 800d9f8: 4b23 ldr r3, [pc, #140] @ (800da88 ) 800d9fa: 2201 movs r2, #1 800d9fc: 601a str r2, [r3, #0] } 800d9fe: bd38 pop {r3, r4, r5, pc} taskCHECK_FOR_STACK_OVERFLOW(); 800da00: 4c22 ldr r4, [pc, #136] @ (800da8c ) xYieldPending = pdFALSE; 800da02: 4a21 ldr r2, [pc, #132] @ (800da88 ) 800da04: 6013 str r3, [r2, #0] taskCHECK_FOR_STACK_OVERFLOW(); 800da06: 6822 ldr r2, [r4, #0] 800da08: 6823 ldr r3, [r4, #0] 800da0a: 6812 ldr r2, [r2, #0] 800da0c: 6b1b ldr r3, [r3, #48] @ 0x30 800da0e: 429a cmp r2, r3 800da10: d92e bls.n 800da70 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800da12: 4d1f ldr r5, [pc, #124] @ (800da90 ) 800da14: 491f ldr r1, [pc, #124] @ (800da94 ) 800da16: 682b ldr r3, [r5, #0] 800da18: eb03 0283 add.w r2, r3, r3, lsl #2 800da1c: 0098 lsls r0, r3, #2 800da1e: 0092 lsls r2, r2, #2 800da20: 588a ldr r2, [r1, r2] 800da22: b942 cbnz r2, 800da36 800da24: b1db cbz r3, 800da5e 800da26: 3b01 subs r3, #1 800da28: eb03 0283 add.w r2, r3, r3, lsl #2 800da2c: 0098 lsls r0, r3, #2 800da2e: f851 2022 ldr.w r2, [r1, r2, lsl #2] 800da32: 2a00 cmp r2, #0 800da34: d0f6 beq.n 800da24 800da36: 4418 add r0, r3 800da38: eb01 0c80 add.w ip, r1, r0, lsl #2 800da3c: f8dc 1004 ldr.w r1, [ip, #4] 800da40: 4662 mov r2, ip 800da42: 6849 ldr r1, [r1, #4] 800da44: 3208 adds r2, #8 800da46: 4291 cmp r1, r2 800da48: f8cc 1004 str.w r1, [ip, #4] 800da4c: d016 beq.n 800da7c 800da4e: 68c9 ldr r1, [r1, #12] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 800da50: 4a11 ldr r2, [pc, #68] @ (800da98 ) taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800da52: 6021 str r1, [r4, #0] 800da54: 602b str r3, [r5, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 800da56: 6823 ldr r3, [r4, #0] 800da58: 3354 adds r3, #84 @ 0x54 800da5a: 6013 str r3, [r2, #0] } 800da5c: bd38 pop {r3, r4, r5, pc} 800da5e: f04f 0350 mov.w r3, #80 @ 0x50 800da62: f383 8811 msr BASEPRI, r3 800da66: f3bf 8f6f isb sy 800da6a: f3bf 8f4f dsb sy configASSERT( pxTaskBuffer != NULL ); 800da6e: e7fe b.n 800da6e taskCHECK_FOR_STACK_OVERFLOW(); 800da70: 6820 ldr r0, [r4, #0] 800da72: 6821 ldr r1, [r4, #0] 800da74: 3134 adds r1, #52 @ 0x34 800da76: f7f2 fe03 bl 8000680 800da7a: e7ca b.n 800da12 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800da7c: 6849 ldr r1, [r1, #4] 800da7e: f8cc 1004 str.w r1, [ip, #4] 800da82: e7e4 b.n 800da4e 800da84: 24002b48 .word 0x24002b48 800da88: 24002b58 .word 0x24002b58 800da8c: 24003040 .word 0x24003040 800da90: 24002b64 .word 0x24002b64 800da94: 24002be0 .word 0x24002be0 800da98: 24000054 .word 0x24000054 0800da9c : configASSERT( pxEventList ); 800da9c: b1f0 cbz r0, 800dadc { 800da9e: b570 push {r4, r5, r6, lr} vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 800daa0: 4d1a ldr r5, [pc, #104] @ (800db0c ) 800daa2: 460c mov r4, r1 800daa4: 6829 ldr r1, [r5, #0] 800daa6: 3118 adds r1, #24 800daa8: f7fe fae2 bl 800c070 const TickType_t xConstTickCount = xTickCount; 800daac: 4b18 ldr r3, [pc, #96] @ (800db10 ) 800daae: 681e ldr r6, [r3, #0] if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800dab0: 6828 ldr r0, [r5, #0] 800dab2: 3004 adds r0, #4 800dab4: f7fe faf4 bl 800c0a0 if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 800dab8: 1c63 adds r3, r4, #1 800daba: d020 beq.n 800dafe xTimeToWake = xConstTickCount + xTicksToWait; 800dabc: 19a4 adds r4, r4, r6 listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 800dabe: 682b ldr r3, [r5, #0] 800dac0: 605c str r4, [r3, #4] if( xTimeToWake < xConstTickCount ) 800dac2: d214 bcs.n 800daee vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800dac4: 4b13 ldr r3, [pc, #76] @ (800db14 ) 800dac6: 6818 ldr r0, [r3, #0] 800dac8: 6829 ldr r1, [r5, #0] 800daca: 3104 adds r1, #4 800dacc: f7fe fad0 bl 800c070 if( xTimeToWake < xNextTaskUnblockTime ) 800dad0: 4b11 ldr r3, [pc, #68] @ (800db18 ) 800dad2: 681a ldr r2, [r3, #0] 800dad4: 4294 cmp r4, r2 800dad6: d200 bcs.n 800dada xNextTaskUnblockTime = xTimeToWake; 800dad8: 601c str r4, [r3, #0] } 800dada: bd70 pop {r4, r5, r6, pc} 800dadc: f04f 0350 mov.w r3, #80 @ 0x50 800dae0: f383 8811 msr BASEPRI, r3 800dae4: f3bf 8f6f isb sy 800dae8: f3bf 8f4f dsb sy configASSERT( pxEventList ); 800daec: e7fe b.n 800daec vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800daee: 4b0b ldr r3, [pc, #44] @ (800db1c ) 800daf0: 6818 ldr r0, [r3, #0] 800daf2: 6829 ldr r1, [r5, #0] } 800daf4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800daf8: 3104 adds r1, #4 800dafa: f7fe bab9 b.w 800c070 vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800dafe: 6829 ldr r1, [r5, #0] 800db00: 4807 ldr r0, [pc, #28] @ (800db20 ) 800db02: 3104 adds r1, #4 } 800db04: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800db08: f7fe baa4 b.w 800c054 800db0c: 24003040 .word 0x24003040 800db10: 24002b68 .word 0x24002b68 800db14: 24002bb4 .word 0x24002bb4 800db18: 24002b4c .word 0x24002b4c 800db1c: 24002bb0 .word 0x24002bb0 800db20: 24002b70 .word 0x24002b70 0800db24 : configASSERT( pxEventList ); 800db24: b358 cbz r0, 800db7e { 800db26: b570 push {r4, r5, r6, lr} vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 800db28: 4e1d ldr r6, [pc, #116] @ (800dba0 ) 800db2a: 460c mov r4, r1 800db2c: 4615 mov r5, r2 800db2e: 6831 ldr r1, [r6, #0] 800db30: 3118 adds r1, #24 800db32: f7fe fa8f bl 800c054 if( xWaitIndefinitely != pdFALSE ) 800db36: b165 cbz r5, 800db52 const TickType_t xConstTickCount = xTickCount; 800db38: 4b1a ldr r3, [pc, #104] @ (800dba4 ) 800db3a: 681b ldr r3, [r3, #0] if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800db3c: 6830 ldr r0, [r6, #0] 800db3e: 3004 adds r0, #4 800db40: f7fe faae bl 800c0a0 vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800db44: 6831 ldr r1, [r6, #0] 800db46: 4818 ldr r0, [pc, #96] @ (800dba8 ) 800db48: 3104 adds r1, #4 } 800db4a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800db4e: f7fe ba81 b.w 800c054 const TickType_t xConstTickCount = xTickCount; 800db52: 4b14 ldr r3, [pc, #80] @ (800dba4 ) 800db54: 681d ldr r5, [r3, #0] if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800db56: 6830 ldr r0, [r6, #0] 800db58: 3004 adds r0, #4 800db5a: f7fe faa1 bl 800c0a0 xTimeToWake = xConstTickCount + xTicksToWait; 800db5e: 1964 adds r4, r4, r5 listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 800db60: 6833 ldr r3, [r6, #0] 800db62: 605c str r4, [r3, #4] if( xTimeToWake < xConstTickCount ) 800db64: d214 bcs.n 800db90 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800db66: 4b11 ldr r3, [pc, #68] @ (800dbac ) 800db68: 6818 ldr r0, [r3, #0] 800db6a: 6831 ldr r1, [r6, #0] 800db6c: 3104 adds r1, #4 800db6e: f7fe fa7f bl 800c070 if( xTimeToWake < xNextTaskUnblockTime ) 800db72: 4b0f ldr r3, [pc, #60] @ (800dbb0 ) 800db74: 681a ldr r2, [r3, #0] 800db76: 4294 cmp r4, r2 800db78: d200 bcs.n 800db7c xNextTaskUnblockTime = xTimeToWake; 800db7a: 601c str r4, [r3, #0] } 800db7c: bd70 pop {r4, r5, r6, pc} 800db7e: f04f 0350 mov.w r3, #80 @ 0x50 800db82: f383 8811 msr BASEPRI, r3 800db86: f3bf 8f6f isb sy 800db8a: f3bf 8f4f dsb sy configASSERT( pxEventList ); 800db8e: e7fe b.n 800db8e vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800db90: 4b08 ldr r3, [pc, #32] @ (800dbb4 ) 800db92: 6818 ldr r0, [r3, #0] 800db94: 6831 ldr r1, [r6, #0] } 800db96: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800db9a: 3104 adds r1, #4 800db9c: f7fe ba68 b.w 800c070 800dba0: 24003040 .word 0x24003040 800dba4: 24002b68 .word 0x24002b68 800dba8: 24002b70 .word 0x24002b70 800dbac: 24002bb4 .word 0x24002bb4 800dbb0: 24002b4c .word 0x24002b4c 800dbb4: 24002bb0 .word 0x24002bb0 0800dbb8 : { 800dbb8: b538 push {r3, r4, r5, lr} pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800dbba: 68c3 ldr r3, [r0, #12] 800dbbc: 68dc ldr r4, [r3, #12] configASSERT( pxUnblockedTCB ); 800dbbe: b34c cbz r4, 800dc14 ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 800dbc0: f104 0518 add.w r5, r4, #24 800dbc4: 4628 mov r0, r5 800dbc6: f7fe fa6b bl 800c0a0 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800dbca: 4b18 ldr r3, [pc, #96] @ (800dc2c ) 800dbcc: 681b ldr r3, [r3, #0] 800dbce: b173 cbz r3, 800dbee vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 800dbd0: 4629 mov r1, r5 800dbd2: 4817 ldr r0, [pc, #92] @ (800dc30 ) 800dbd4: f7fe fa3e bl 800c054 if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 800dbd8: 4b16 ldr r3, [pc, #88] @ (800dc34 ) 800dbda: 6ae2 ldr r2, [r4, #44] @ 0x2c 800dbdc: 681b ldr r3, [r3, #0] 800dbde: 6adb ldr r3, [r3, #44] @ 0x2c 800dbe0: 429a cmp r2, r3 800dbe2: d920 bls.n 800dc26 xYieldPending = pdTRUE; 800dbe4: 2301 movs r3, #1 800dbe6: 4a14 ldr r2, [pc, #80] @ (800dc38 ) xReturn = pdTRUE; 800dbe8: 4618 mov r0, r3 xYieldPending = pdTRUE; 800dbea: 6013 str r3, [r2, #0] } 800dbec: bd38 pop {r3, r4, r5, pc} ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 800dbee: 1d25 adds r5, r4, #4 800dbf0: 4628 mov r0, r5 800dbf2: f7fe fa55 bl 800c0a0 prvAddTaskToReadyList( pxUnblockedTCB ); 800dbf6: 4b11 ldr r3, [pc, #68] @ (800dc3c ) 800dbf8: 6ae0 ldr r0, [r4, #44] @ 0x2c 800dbfa: 681a ldr r2, [r3, #0] 800dbfc: 4290 cmp r0, r2 800dbfe: d900 bls.n 800dc02 800dc00: 6018 str r0, [r3, #0] 800dc02: 4b0f ldr r3, [pc, #60] @ (800dc40 ) 800dc04: eb00 0080 add.w r0, r0, r0, lsl #2 800dc08: 4629 mov r1, r5 800dc0a: eb03 0080 add.w r0, r3, r0, lsl #2 800dc0e: f7fe fa21 bl 800c054 800dc12: e7e1 b.n 800dbd8 800dc14: f04f 0350 mov.w r3, #80 @ 0x50 800dc18: f383 8811 msr BASEPRI, r3 800dc1c: f3bf 8f6f isb sy 800dc20: f3bf 8f4f dsb sy configASSERT( pxUnblockedTCB ); 800dc24: e7fe b.n 800dc24 xReturn = pdFALSE; 800dc26: 2000 movs r0, #0 } 800dc28: bd38 pop {r3, r4, r5, pc} 800dc2a: bf00 nop 800dc2c: 24002b48 .word 0x24002b48 800dc30: 24002b9c .word 0x24002b9c 800dc34: 24003040 .word 0x24003040 800dc38: 24002b58 .word 0x24002b58 800dc3c: 24002b64 .word 0x24002b64 800dc40: 24002be0 .word 0x24002be0 0800dc44 : configASSERT( pxTimeOut ); 800dc44: b168 cbz r0, 800dc62 { 800dc46: b510 push {r4, lr} 800dc48: 4604 mov r4, r0 taskENTER_CRITICAL(); 800dc4a: f000 feab bl 800e9a4 pxTimeOut->xOverflowCount = xNumOfOverflows; 800dc4e: 4a09 ldr r2, [pc, #36] @ (800dc74 ) pxTimeOut->xTimeOnEntering = xTickCount; 800dc50: 4b09 ldr r3, [pc, #36] @ (800dc78 ) pxTimeOut->xOverflowCount = xNumOfOverflows; 800dc52: 6812 ldr r2, [r2, #0] pxTimeOut->xTimeOnEntering = xTickCount; 800dc54: 681b ldr r3, [r3, #0] 800dc56: e9c4 2300 strd r2, r3, [r4] } 800dc5a: e8bd 4010 ldmia.w sp!, {r4, lr} taskEXIT_CRITICAL(); 800dc5e: f000 bec3 b.w 800e9e8 800dc62: f04f 0350 mov.w r3, #80 @ 0x50 800dc66: f383 8811 msr BASEPRI, r3 800dc6a: f3bf 8f6f isb sy 800dc6e: f3bf 8f4f dsb sy configASSERT( pxTimeOut ); 800dc72: e7fe b.n 800dc72 800dc74: 24002b54 .word 0x24002b54 800dc78: 24002b68 .word 0x24002b68 0800dc7c : pxTimeOut->xOverflowCount = xNumOfOverflows; 800dc7c: 4a03 ldr r2, [pc, #12] @ (800dc8c ) pxTimeOut->xTimeOnEntering = xTickCount; 800dc7e: 4b04 ldr r3, [pc, #16] @ (800dc90 ) pxTimeOut->xOverflowCount = xNumOfOverflows; 800dc80: 6812 ldr r2, [r2, #0] pxTimeOut->xTimeOnEntering = xTickCount; 800dc82: 681b ldr r3, [r3, #0] 800dc84: e9c0 2300 strd r2, r3, [r0] } 800dc88: 4770 bx lr 800dc8a: bf00 nop 800dc8c: 24002b54 .word 0x24002b54 800dc90: 24002b68 .word 0x24002b68 0800dc94 : { 800dc94: b5f8 push {r3, r4, r5, r6, r7, lr} configASSERT( pxTimeOut ); 800dc96: b308 cbz r0, 800dcdc configASSERT( pxTicksToWait ); 800dc98: 460d mov r5, r1 800dc9a: b1b1 cbz r1, 800dcca 800dc9c: 4604 mov r4, r0 taskENTER_CRITICAL(); 800dc9e: f000 fe81 bl 800e9a4 if( *pxTicksToWait == portMAX_DELAY ) 800dca2: 682b ldr r3, [r5, #0] const TickType_t xConstTickCount = xTickCount; 800dca4: 4a1a ldr r2, [pc, #104] @ (800dd10 ) if( *pxTicksToWait == portMAX_DELAY ) 800dca6: 1c58 adds r0, r3, #1 const TickType_t xConstTickCount = xTickCount; 800dca8: 6811 ldr r1, [r2, #0] if( *pxTicksToWait == portMAX_DELAY ) 800dcaa: d02c beq.n 800dd06 if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 800dcac: f8df c064 ldr.w ip, [pc, #100] @ 800dd14 800dcb0: 6826 ldr r6, [r4, #0] 800dcb2: f8dc 7000 ldr.w r7, [ip] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 800dcb6: 6860 ldr r0, [r4, #4] if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 800dcb8: 42be cmp r6, r7 800dcba: d018 beq.n 800dcee 800dcbc: 4288 cmp r0, r1 800dcbe: d816 bhi.n 800dcee xReturn = pdTRUE; 800dcc0: 2401 movs r4, #1 taskEXIT_CRITICAL(); 800dcc2: f000 fe91 bl 800e9e8 } 800dcc6: 4620 mov r0, r4 800dcc8: bdf8 pop {r3, r4, r5, r6, r7, pc} 800dcca: f04f 0350 mov.w r3, #80 @ 0x50 800dcce: f383 8811 msr BASEPRI, r3 800dcd2: f3bf 8f6f isb sy 800dcd6: f3bf 8f4f dsb sy configASSERT( pxTicksToWait ); 800dcda: e7fe b.n 800dcda 800dcdc: f04f 0350 mov.w r3, #80 @ 0x50 800dce0: f383 8811 msr BASEPRI, r3 800dce4: f3bf 8f6f isb sy 800dce8: f3bf 8f4f dsb sy configASSERT( pxTimeOut ); 800dcec: e7fe b.n 800dcec const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 800dcee: eba1 0e00 sub.w lr, r1, r0 else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 800dcf2: 4573 cmp r3, lr 800dcf4: d909 bls.n 800dd0a *pxTicksToWait -= xElapsedTime; 800dcf6: 1a5b subs r3, r3, r1 pxTimeOut->xOverflowCount = xNumOfOverflows; 800dcf8: f8dc 1000 ldr.w r1, [ip] pxTimeOut->xTimeOnEntering = xTickCount; 800dcfc: 6812 ldr r2, [r2, #0] *pxTicksToWait -= xElapsedTime; 800dcfe: 4403 add r3, r0 800dd00: 602b str r3, [r5, #0] pxTimeOut->xTimeOnEntering = xTickCount; 800dd02: e9c4 1200 strd r1, r2, [r4] xReturn = pdFALSE; 800dd06: 2400 movs r4, #0 800dd08: e7db b.n 800dcc2 *pxTicksToWait = 0; 800dd0a: 2300 movs r3, #0 800dd0c: 602b str r3, [r5, #0] xReturn = pdTRUE; 800dd0e: e7d7 b.n 800dcc0 800dd10: 24002b68 .word 0x24002b68 800dd14: 24002b54 .word 0x24002b54 0800dd18 : xYieldPending = pdTRUE; 800dd18: 4b01 ldr r3, [pc, #4] @ (800dd20 ) 800dd1a: 2201 movs r2, #1 800dd1c: 601a str r2, [r3, #0] } 800dd1e: 4770 bx lr 800dd20: 24002b58 .word 0x24002b58 0800dd24 : xReturn = pxCurrentTCB; 800dd24: 4b01 ldr r3, [pc, #4] @ (800dd2c ) 800dd26: 6818 ldr r0, [r3, #0] } 800dd28: 4770 bx lr 800dd2a: bf00 nop 800dd2c: 24003040 .word 0x24003040 0800dd30 : if( xSchedulerRunning == pdFALSE ) 800dd30: 4b05 ldr r3, [pc, #20] @ (800dd48 ) 800dd32: 681b ldr r3, [r3, #0] 800dd34: b133 cbz r3, 800dd44 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800dd36: 4b05 ldr r3, [pc, #20] @ (800dd4c ) 800dd38: 6818 ldr r0, [r3, #0] 800dd3a: fab0 f080 clz r0, r0 800dd3e: 0940 lsrs r0, r0, #5 800dd40: 0040 lsls r0, r0, #1 800dd42: 4770 bx lr xReturn = taskSCHEDULER_NOT_STARTED; 800dd44: 2001 movs r0, #1 } 800dd46: 4770 bx lr 800dd48: 24002b60 .word 0x24002b60 800dd4c: 24002b48 .word 0x24002b48 0800dd50 : { 800dd50: b5f8 push {r3, r4, r5, r6, r7, lr} if( pxMutexHolder != NULL ) 800dd52: 4604 mov r4, r0 800dd54: b1c8 cbz r0, 800dd8a if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 800dd56: 4d1b ldr r5, [pc, #108] @ (800ddc4 ) 800dd58: 6ac3 ldr r3, [r0, #44] @ 0x2c 800dd5a: 682a ldr r2, [r5, #0] 800dd5c: 6ad2 ldr r2, [r2, #44] @ 0x2c 800dd5e: 4293 cmp r3, r2 800dd60: d214 bcs.n 800dd8c if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 800dd62: 6982 ldr r2, [r0, #24] 800dd64: 2a00 cmp r2, #0 800dd66: db04 blt.n 800dd72 listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800dd68: 682a ldr r2, [r5, #0] 800dd6a: 6ad2 ldr r2, [r2, #44] @ 0x2c 800dd6c: f1c2 0238 rsb r2, r2, #56 @ 0x38 800dd70: 6182 str r2, [r0, #24] if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 800dd72: eb03 0383 add.w r3, r3, r3, lsl #2 800dd76: 4e14 ldr r6, [pc, #80] @ (800ddc8 ) 800dd78: 6962 ldr r2, [r4, #20] 800dd7a: eb06 0383 add.w r3, r6, r3, lsl #2 800dd7e: 429a cmp r2, r3 800dd80: d00c beq.n 800dd9c pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 800dd82: 682b ldr r3, [r5, #0] 800dd84: 6adb ldr r3, [r3, #44] @ 0x2c 800dd86: 62e3 str r3, [r4, #44] @ 0x2c xReturn = pdTRUE; 800dd88: 2001 movs r0, #1 } 800dd8a: bdf8 pop {r3, r4, r5, r6, r7, pc} if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 800dd8c: 682b ldr r3, [r5, #0] 800dd8e: 6cc0 ldr r0, [r0, #76] @ 0x4c 800dd90: 6adb ldr r3, [r3, #44] @ 0x2c 800dd92: 4298 cmp r0, r3 800dd94: bf2c ite cs 800dd96: 2000 movcs r0, #0 800dd98: 2001 movcc r0, #1 } 800dd9a: bdf8 pop {r3, r4, r5, r6, r7, pc} if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800dd9c: 1d27 adds r7, r4, #4 800dd9e: 4638 mov r0, r7 800dda0: f7fe f97e bl 800c0a0 pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 800dda4: 682a ldr r2, [r5, #0] prvAddTaskToReadyList( pxMutexHolderTCB ); 800dda6: 4b09 ldr r3, [pc, #36] @ (800ddcc ) pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 800dda8: 6ad0 ldr r0, [r2, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 800ddaa: 681a ldr r2, [r3, #0] pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 800ddac: 62e0 str r0, [r4, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 800ddae: 4290 cmp r0, r2 800ddb0: d900 bls.n 800ddb4 800ddb2: 6018 str r0, [r3, #0] 800ddb4: eb00 0080 add.w r0, r0, r0, lsl #2 800ddb8: 4639 mov r1, r7 800ddba: eb06 0080 add.w r0, r6, r0, lsl #2 800ddbe: f7fe f949 bl 800c054 800ddc2: e7e1 b.n 800dd88 800ddc4: 24003040 .word 0x24003040 800ddc8: 24002be0 .word 0x24002be0 800ddcc: 24002b64 .word 0x24002b64 0800ddd0 : if( pxMutexHolder != NULL ) 800ddd0: b308 cbz r0, 800de16 { 800ddd2: b538 push {r3, r4, r5, lr} configASSERT( pxTCB == pxCurrentTCB ); 800ddd4: 4b1d ldr r3, [pc, #116] @ (800de4c ) 800ddd6: 681c ldr r4, [r3, #0] 800ddd8: 4284 cmp r4, r0 800ddda: d008 beq.n 800ddee 800dddc: f04f 0350 mov.w r3, #80 @ 0x50 800dde0: f383 8811 msr BASEPRI, r3 800dde4: f3bf 8f6f isb sy 800dde8: f3bf 8f4f dsb sy 800ddec: e7fe b.n 800ddec configASSERT( pxTCB->uxMutexesHeld ); 800ddee: 6d23 ldr r3, [r4, #80] @ 0x50 800ddf0: b143 cbz r3, 800de04 if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 800ddf2: 6ae1 ldr r1, [r4, #44] @ 0x2c ( pxTCB->uxMutexesHeld )--; 800ddf4: 3b01 subs r3, #1 if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 800ddf6: 6ce2 ldr r2, [r4, #76] @ 0x4c ( pxTCB->uxMutexesHeld )--; 800ddf8: 6523 str r3, [r4, #80] @ 0x50 if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 800ddfa: 4291 cmp r1, r2 800ddfc: d000 beq.n 800de00 800ddfe: b163 cbz r3, 800de1a BaseType_t xReturn = pdFALSE; 800de00: 2000 movs r0, #0 } 800de02: bd38 pop {r3, r4, r5, pc} 800de04: f04f 0350 mov.w r3, #80 @ 0x50 800de08: f383 8811 msr BASEPRI, r3 800de0c: f3bf 8f6f isb sy 800de10: f3bf 8f4f dsb sy configASSERT( pxTCB->uxMutexesHeld ); 800de14: e7fe b.n 800de14 BaseType_t xReturn = pdFALSE; 800de16: 2000 movs r0, #0 } 800de18: 4770 bx lr if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800de1a: 1d25 adds r5, r4, #4 800de1c: 4628 mov r0, r5 800de1e: f7fe f93f bl 800c0a0 pxTCB->uxPriority = pxTCB->uxBasePriority; 800de22: 6ce0 ldr r0, [r4, #76] @ 0x4c prvAddTaskToReadyList( pxTCB ); 800de24: 4b0a ldr r3, [pc, #40] @ (800de50 ) listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800de26: f1c0 0238 rsb r2, r0, #56 @ 0x38 pxTCB->uxPriority = pxTCB->uxBasePriority; 800de2a: 62e0 str r0, [r4, #44] @ 0x2c listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800de2c: 61a2 str r2, [r4, #24] prvAddTaskToReadyList( pxTCB ); 800de2e: 681a ldr r2, [r3, #0] 800de30: 4290 cmp r0, r2 800de32: d900 bls.n 800de36 800de34: 6018 str r0, [r3, #0] 800de36: 4b07 ldr r3, [pc, #28] @ (800de54 ) 800de38: eb00 0080 add.w r0, r0, r0, lsl #2 800de3c: 4629 mov r1, r5 800de3e: eb03 0080 add.w r0, r3, r0, lsl #2 800de42: f7fe f907 bl 800c054 xReturn = pdTRUE; 800de46: 2001 movs r0, #1 } 800de48: bd38 pop {r3, r4, r5, pc} 800de4a: bf00 nop 800de4c: 24003040 .word 0x24003040 800de50: 24002b64 .word 0x24002b64 800de54: 24002be0 .word 0x24002be0 0800de58 : if( pxMutexHolder != NULL ) 800de58: 2800 cmp r0, #0 800de5a: d03c beq.n 800ded6 configASSERT( pxTCB->uxMutexesHeld ); 800de5c: 6d03 ldr r3, [r0, #80] @ 0x50 { 800de5e: b570 push {r4, r5, r6, lr} 800de60: 4604 mov r4, r0 configASSERT( pxTCB->uxMutexesHeld ); 800de62: b14b cbz r3, 800de78 if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 800de64: 6cc0 ldr r0, [r0, #76] @ 0x4c if( pxTCB->uxPriority != uxPriorityToUse ) 800de66: 6ae2 ldr r2, [r4, #44] @ 0x2c 800de68: 4281 cmp r1, r0 800de6a: bf38 it cc 800de6c: 4601 movcc r1, r0 if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 800de6e: 2b01 cmp r3, #1 800de70: d101 bne.n 800de76 800de72: 428a cmp r2, r1 800de74: d109 bne.n 800de8a } 800de76: bd70 pop {r4, r5, r6, pc} 800de78: f04f 0350 mov.w r3, #80 @ 0x50 800de7c: f383 8811 msr BASEPRI, r3 800de80: f3bf 8f6f isb sy 800de84: f3bf 8f4f dsb sy configASSERT( pxTCB->uxMutexesHeld ); 800de88: e7fe b.n 800de88 configASSERT( pxTCB != pxCurrentTCB ); 800de8a: 4b18 ldr r3, [pc, #96] @ (800deec ) 800de8c: 681b ldr r3, [r3, #0] 800de8e: 42a3 cmp r3, r4 800de90: d022 beq.n 800ded8 if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 800de92: 69a3 ldr r3, [r4, #24] pxTCB->uxPriority = uxPriorityToUse; 800de94: 62e1 str r1, [r4, #44] @ 0x2c if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 800de96: 2b00 cmp r3, #0 800de98: db02 blt.n 800dea0 listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800de9a: f1c1 0138 rsb r1, r1, #56 @ 0x38 800de9e: 61a1 str r1, [r4, #24] if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 800dea0: eb02 0282 add.w r2, r2, r2, lsl #2 800dea4: 4d12 ldr r5, [pc, #72] @ (800def0 ) 800dea6: 6961 ldr r1, [r4, #20] 800dea8: eb05 0382 add.w r3, r5, r2, lsl #2 800deac: 4299 cmp r1, r3 800deae: d1e2 bne.n 800de76 if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800deb0: 1d26 adds r6, r4, #4 800deb2: 4630 mov r0, r6 800deb4: f7fe f8f4 bl 800c0a0 prvAddTaskToReadyList( pxTCB ); 800deb8: 4b0e ldr r3, [pc, #56] @ (800def4 ) 800deba: 6ae0 ldr r0, [r4, #44] @ 0x2c 800debc: 681a ldr r2, [r3, #0] 800debe: 4290 cmp r0, r2 800dec0: d900 bls.n 800dec4 800dec2: 6018 str r0, [r3, #0] 800dec4: eb00 0080 add.w r0, r0, r0, lsl #2 800dec8: 4631 mov r1, r6 800deca: eb05 0080 add.w r0, r5, r0, lsl #2 } 800dece: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} prvAddTaskToReadyList( pxTCB ); 800ded2: f7fe b8bf b.w 800c054 800ded6: 4770 bx lr 800ded8: f04f 0350 mov.w r3, #80 @ 0x50 800dedc: f383 8811 msr BASEPRI, r3 800dee0: f3bf 8f6f isb sy 800dee4: f3bf 8f4f dsb sy configASSERT( pxTCB != pxCurrentTCB ); 800dee8: e7fe b.n 800dee8 800deea: bf00 nop 800deec: 24003040 .word 0x24003040 800def0: 24002be0 .word 0x24002be0 800def4: 24002b64 .word 0x24002b64 0800def8 : if( pxCurrentTCB != NULL ) 800def8: 4b04 ldr r3, [pc, #16] @ (800df0c ) 800defa: 681a ldr r2, [r3, #0] 800defc: b11a cbz r2, 800df06 ( pxCurrentTCB->uxMutexesHeld )++; 800defe: 6819 ldr r1, [r3, #0] 800df00: 6d0a ldr r2, [r1, #80] @ 0x50 800df02: 3201 adds r2, #1 800df04: 650a str r2, [r1, #80] @ 0x50 return pxCurrentTCB; 800df06: 6818 ldr r0, [r3, #0] } 800df08: 4770 bx lr 800df0a: bf00 nop 800df0c: 24003040 .word 0x24003040 0800df10 : { 800df10: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 800df14: 4c33 ldr r4, [pc, #204] @ (800dfe4 ) { 800df16: 461d mov r5, r3 800df18: 4606 mov r6, r0 800df1a: 4688 mov r8, r1 800df1c: 4617 mov r7, r2 taskENTER_CRITICAL(); 800df1e: f000 fd41 bl 800e9a4 if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 800df22: 6823 ldr r3, [r4, #0] 800df24: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 800df28: 2b02 cmp r3, #2 800df2a: d00b beq.n 800df44 pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 800df2c: 6822 ldr r2, [r4, #0] pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 800df2e: 2101 movs r1, #1 pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 800df30: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0 800df34: ea23 0306 bic.w r3, r3, r6 800df38: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 800df3c: 6823 ldr r3, [r4, #0] 800df3e: f883 10a4 strb.w r1, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 800df42: b9bd cbnz r5, 800df74 taskEXIT_CRITICAL(); 800df44: f000 fd50 bl 800e9e8 taskENTER_CRITICAL(); 800df48: f000 fd2c bl 800e9a4 if( pulNotificationValue != NULL ) 800df4c: b11f cbz r7, 800df56 *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 800df4e: 6823 ldr r3, [r4, #0] 800df50: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800df54: 603b str r3, [r7, #0] if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 800df56: 6823 ldr r3, [r4, #0] 800df58: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 800df5c: 2b02 cmp r3, #2 800df5e: d026 beq.n 800dfae xReturn = pdFALSE; 800df60: 2500 movs r5, #0 pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 800df62: 6823 ldr r3, [r4, #0] 800df64: 2200 movs r2, #0 800df66: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 taskEXIT_CRITICAL(); 800df6a: f000 fd3d bl 800e9e8 } 800df6e: 4628 mov r0, r5 800df70: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} const TickType_t xConstTickCount = xTickCount; 800df74: 4b1c ldr r3, [pc, #112] @ (800dfe8 ) 800df76: 681e ldr r6, [r3, #0] if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800df78: 6820 ldr r0, [r4, #0] 800df7a: 3004 adds r0, #4 800df7c: f7fe f890 bl 800c0a0 if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 800df80: 1c6b adds r3, r5, #1 800df82: d01d beq.n 800dfc0 xTimeToWake = xConstTickCount + xTicksToWait; 800df84: 19ad adds r5, r5, r6 listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 800df86: 6823 ldr r3, [r4, #0] 800df88: 605d str r5, [r3, #4] if( xTimeToWake < xConstTickCount ) 800df8a: d31f bcc.n 800dfcc vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800df8c: 4b17 ldr r3, [pc, #92] @ (800dfec ) 800df8e: 6818 ldr r0, [r3, #0] 800df90: 6821 ldr r1, [r4, #0] 800df92: 3104 adds r1, #4 800df94: f7fe f86c bl 800c070 portYIELD_WITHIN_API(); 800df98: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800df9c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800dfa0: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800dfa4: f3bf 8f4f dsb sy 800dfa8: f3bf 8f6f isb sy 800dfac: e7ca b.n 800df44 pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 800dfae: 6822 ldr r2, [r4, #0] xReturn = pdTRUE; 800dfb0: 2501 movs r5, #1 pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 800dfb2: f8d2 30a0 ldr.w r3, [r2, #160] @ 0xa0 800dfb6: ea23 0308 bic.w r3, r3, r8 800dfba: f8c2 30a0 str.w r3, [r2, #160] @ 0xa0 xReturn = pdTRUE; 800dfbe: e7d0 b.n 800df62 vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800dfc0: 6821 ldr r1, [r4, #0] 800dfc2: 480b ldr r0, [pc, #44] @ (800dff0 ) 800dfc4: 3104 adds r1, #4 800dfc6: f7fe f845 bl 800c054 /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 800dfca: e7e5 b.n 800df98 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800dfcc: 4b09 ldr r3, [pc, #36] @ (800dff4 ) 800dfce: 6818 ldr r0, [r3, #0] 800dfd0: 6821 ldr r1, [r4, #0] 800dfd2: 3104 adds r1, #4 800dfd4: f7fe f84c bl 800c070 if( xTimeToWake < xNextTaskUnblockTime ) 800dfd8: 4b07 ldr r3, [pc, #28] @ (800dff8 ) 800dfda: 681a ldr r2, [r3, #0] 800dfdc: 4295 cmp r5, r2 800dfde: d2db bcs.n 800df98 xNextTaskUnblockTime = xTimeToWake; 800dfe0: 601d str r5, [r3, #0] 800dfe2: e7d9 b.n 800df98 800dfe4: 24003040 .word 0x24003040 800dfe8: 24002b68 .word 0x24002b68 800dfec: 24002bb0 .word 0x24002bb0 800dff0: 24002b70 .word 0x24002b70 800dff4: 24002bb4 .word 0x24002bb4 800dff8: 24002b4c .word 0x24002b4c 0800dffc : { 800dffc: b5f8 push {r3, r4, r5, r6, r7, lr} configASSERT( xTaskToNotify ); 800dffe: b308 cbz r0, 800e044 pxTCB = xTaskToNotify; 800e000: 461e mov r6, r3 800e002: 460f mov r7, r1 800e004: 4604 mov r4, r0 taskENTER_CRITICAL(); 800e006: 4615 mov r5, r2 800e008: f000 fccc bl 800e9a4 if( pulPreviousNotificationValue != NULL ) 800e00c: b116 cbz r6, 800e014 *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 800e00e: f8d4 30a0 ldr.w r3, [r4, #160] @ 0xa0 800e012: 6033 str r3, [r6, #0] ucOriginalNotifyState = pxTCB->ucNotifyState; 800e014: f894 30a4 ldrb.w r3, [r4, #164] @ 0xa4 pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 800e018: 2202 movs r2, #2 ucOriginalNotifyState = pxTCB->ucNotifyState; 800e01a: b2db uxtb r3, r3 pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 800e01c: f884 20a4 strb.w r2, [r4, #164] @ 0xa4 switch( eAction ) 800e020: 2d04 cmp r5, #4 800e022: d855 bhi.n 800e0d0 800e024: e8df f005 tbb [pc, r5] 800e028: 051d1707 .word 0x051d1707 800e02c: 03 .byte 0x03 800e02d: 00 .byte 0x00 if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 800e02e: 2b02 cmp r3, #2 800e030: d03b beq.n 800e0aa pxTCB->ulNotifiedValue = ulValue; 800e032: f8c4 70a0 str.w r7, [r4, #160] @ 0xa0 if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 800e036: 2b01 cmp r3, #1 800e038: d019 beq.n 800e06e { 800e03a: 2401 movs r4, #1 taskEXIT_CRITICAL(); 800e03c: f000 fcd4 bl 800e9e8 } 800e040: 4620 mov r0, r4 800e042: bdf8 pop {r3, r4, r5, r6, r7, pc} 800e044: f04f 0350 mov.w r3, #80 @ 0x50 800e048: f383 8811 msr BASEPRI, r3 800e04c: f3bf 8f6f isb sy 800e050: f3bf 8f4f dsb sy configASSERT( xTaskToNotify ); 800e054: e7fe b.n 800e054 pxTCB->ulNotifiedValue |= ulValue; 800e056: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0 800e05a: 433a orrs r2, r7 800e05c: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0 break; 800e060: e7e9 b.n 800e036 ( pxTCB->ulNotifiedValue )++; 800e062: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0 800e066: 3201 adds r2, #1 800e068: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0 break; 800e06c: e7e3 b.n 800e036 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800e06e: 1d25 adds r5, r4, #4 800e070: 4628 mov r0, r5 800e072: f7fe f815 bl 800c0a0 prvAddTaskToReadyList( pxTCB ); 800e076: 4b1d ldr r3, [pc, #116] @ (800e0ec ) 800e078: 6ae0 ldr r0, [r4, #44] @ 0x2c 800e07a: 681a ldr r2, [r3, #0] 800e07c: 4290 cmp r0, r2 800e07e: d812 bhi.n 800e0a6 800e080: 4b1b ldr r3, [pc, #108] @ (800e0f0 ) 800e082: eb00 0080 add.w r0, r0, r0, lsl #2 800e086: 4629 mov r1, r5 800e088: eb03 0080 add.w r0, r3, r0, lsl #2 800e08c: f7fd ffe2 bl 800c054 configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 800e090: 6aa3 ldr r3, [r4, #40] @ 0x28 800e092: b163 cbz r3, 800e0ae 800e094: f04f 0350 mov.w r3, #80 @ 0x50 800e098: f383 8811 msr BASEPRI, r3 800e09c: f3bf 8f6f isb sy 800e0a0: f3bf 8f4f dsb sy 800e0a4: e7fe b.n 800e0a4 prvAddTaskToReadyList( pxTCB ); 800e0a6: 6018 str r0, [r3, #0] 800e0a8: e7ea b.n 800e080 xReturn = pdFAIL; 800e0aa: 2400 movs r4, #0 800e0ac: e7c6 b.n 800e03c if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 800e0ae: 4b11 ldr r3, [pc, #68] @ (800e0f4 ) 800e0b0: 6ae2 ldr r2, [r4, #44] @ 0x2c 800e0b2: 681b ldr r3, [r3, #0] 800e0b4: 6adb ldr r3, [r3, #44] @ 0x2c 800e0b6: 429a cmp r2, r3 800e0b8: d9bf bls.n 800e03a taskYIELD_IF_USING_PREEMPTION(); 800e0ba: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800e0be: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800e0c2: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 800e0c6: f3bf 8f4f dsb sy 800e0ca: f3bf 8f6f isb sy 800e0ce: e7b4 b.n 800e03a configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 800e0d0: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0 800e0d4: 3201 adds r2, #1 800e0d6: d0ae beq.n 800e036 800e0d8: f04f 0350 mov.w r3, #80 @ 0x50 800e0dc: f383 8811 msr BASEPRI, r3 800e0e0: f3bf 8f6f isb sy 800e0e4: f3bf 8f4f dsb sy 800e0e8: e7fe b.n 800e0e8 800e0ea: bf00 nop 800e0ec: 24002b64 .word 0x24002b64 800e0f0: 24002be0 .word 0x24002be0 800e0f4: 24003040 .word 0x24003040 0800e0f8 : configASSERT( xTaskToNotify ); 800e0f8: b368 cbz r0, 800e156 { 800e0fa: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800e0fe: 460f mov r7, r1 800e100: 4616 mov r6, r2 800e102: 461d mov r5, r3 800e104: 4604 mov r4, r0 portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 800e106: f000 fd7f bl 800ec08 __asm volatile 800e10a: f3ef 8811 mrs r8, BASEPRI 800e10e: f04f 0350 mov.w r3, #80 @ 0x50 800e112: f383 8811 msr BASEPRI, r3 800e116: f3bf 8f6f isb sy 800e11a: f3bf 8f4f dsb sy if( pulPreviousNotificationValue != NULL ) 800e11e: b115 cbz r5, 800e126 *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 800e120: f8d4 30a0 ldr.w r3, [r4, #160] @ 0xa0 800e124: 602b str r3, [r5, #0] ucOriginalNotifyState = pxTCB->ucNotifyState; 800e126: f894 30a4 ldrb.w r3, [r4, #164] @ 0xa4 pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 800e12a: 2202 movs r2, #2 ucOriginalNotifyState = pxTCB->ucNotifyState; 800e12c: b2db uxtb r3, r3 pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 800e12e: f884 20a4 strb.w r2, [r4, #164] @ 0xa4 switch( eAction ) 800e132: 2e04 cmp r6, #4 800e134: d85b bhi.n 800e1ee 800e136: e8df f006 tbb [pc, r6] 800e13a: 1707 .short 0x1707 800e13c: 051d .short 0x051d 800e13e: 03 .byte 0x03 800e13f: 00 .byte 0x00 if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 800e140: 2b02 cmp r3, #2 800e142: d028 beq.n 800e196 pxTCB->ulNotifiedValue = ulValue; 800e144: f8c4 70a0 str.w r7, [r4, #160] @ 0xa0 if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 800e148: 2b01 cmp r3, #1 800e14a: d019 beq.n 800e180 { 800e14c: 2001 movs r0, #1 __asm volatile 800e14e: f388 8811 msr BASEPRI, r8 } 800e152: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} __asm volatile 800e156: f04f 0350 mov.w r3, #80 @ 0x50 800e15a: f383 8811 msr BASEPRI, r3 800e15e: f3bf 8f6f isb sy 800e162: f3bf 8f4f dsb sy configASSERT( xTaskToNotify ); 800e166: e7fe b.n 800e166 pxTCB->ulNotifiedValue |= ulValue; 800e168: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0 800e16c: 433a orrs r2, r7 800e16e: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0 break; 800e172: e7e9 b.n 800e148 ( pxTCB->ulNotifiedValue )++; 800e174: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0 800e178: 3201 adds r2, #1 800e17a: f8c4 20a0 str.w r2, [r4, #160] @ 0xa0 break; 800e17e: e7e3 b.n 800e148 configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 800e180: 6aa3 ldr r3, [r4, #40] @ 0x28 800e182: b153 cbz r3, 800e19a 800e184: f04f 0350 mov.w r3, #80 @ 0x50 800e188: f383 8811 msr BASEPRI, r3 800e18c: f3bf 8f6f isb sy 800e190: f3bf 8f4f dsb sy 800e194: e7fe b.n 800e194 xReturn = pdFAIL; 800e196: 2000 movs r0, #0 800e198: e7d9 b.n 800e14e if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800e19a: 4b1b ldr r3, [pc, #108] @ (800e208 ) 800e19c: 681b ldr r3, [r3, #0] 800e19e: bb03 cbnz r3, 800e1e2 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800e1a0: 1d25 adds r5, r4, #4 800e1a2: 4628 mov r0, r5 800e1a4: f7fd ff7c bl 800c0a0 prvAddTaskToReadyList( pxTCB ); 800e1a8: 4b18 ldr r3, [pc, #96] @ (800e20c ) 800e1aa: 6ae0 ldr r0, [r4, #44] @ 0x2c 800e1ac: 681a ldr r2, [r3, #0] 800e1ae: 4290 cmp r0, r2 800e1b0: d900 bls.n 800e1b4 800e1b2: 6018 str r0, [r3, #0] 800e1b4: eb00 0080 add.w r0, r0, r0, lsl #2 800e1b8: 4b15 ldr r3, [pc, #84] @ (800e210 ) 800e1ba: 4629 mov r1, r5 800e1bc: eb03 0080 add.w r0, r3, r0, lsl #2 800e1c0: f7fd ff48 bl 800c054 if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 800e1c4: 4b13 ldr r3, [pc, #76] @ (800e214 ) 800e1c6: 6ae2 ldr r2, [r4, #44] @ 0x2c 800e1c8: 681b ldr r3, [r3, #0] 800e1ca: 6adb ldr r3, [r3, #44] @ 0x2c 800e1cc: 429a cmp r2, r3 800e1ce: d9bd bls.n 800e14c if( pxHigherPriorityTaskWoken != NULL ) 800e1d0: 9b06 ldr r3, [sp, #24] 800e1d2: b113 cbz r3, 800e1da 800e1d4: 461a mov r2, r3 *pxHigherPriorityTaskWoken = pdTRUE; 800e1d6: 2301 movs r3, #1 800e1d8: 6013 str r3, [r2, #0] xYieldPending = pdTRUE; 800e1da: 4b0f ldr r3, [pc, #60] @ (800e218 ) 800e1dc: 2201 movs r2, #1 800e1de: 601a str r2, [r3, #0] 800e1e0: e7b4 b.n 800e14c vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 800e1e2: f104 0118 add.w r1, r4, #24 800e1e6: 480d ldr r0, [pc, #52] @ (800e21c ) 800e1e8: f7fd ff34 bl 800c054 800e1ec: e7ea b.n 800e1c4 configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 800e1ee: f8d4 20a0 ldr.w r2, [r4, #160] @ 0xa0 800e1f2: 3201 adds r2, #1 800e1f4: d0a8 beq.n 800e148 800e1f6: f04f 0350 mov.w r3, #80 @ 0x50 800e1fa: f383 8811 msr BASEPRI, r3 800e1fe: f3bf 8f6f isb sy 800e202: f3bf 8f4f dsb sy 800e206: e7fe b.n 800e206 800e208: 24002b48 .word 0x24002b48 800e20c: 24002b64 .word 0x24002b64 800e210: 24002be0 .word 0x24002be0 800e214: 24003040 .word 0x24003040 800e218: 24002b58 .word 0x24002b58 800e21c: 24002b9c .word 0x24002b9c 0800e220 : { 800e220: b538 push {r3, r4, r5, lr} pxTCB = prvGetTCBFromHandle( xTask ); 800e222: b198 cbz r0, 800e24c 800e224: 4604 mov r4, r0 taskENTER_CRITICAL(); 800e226: f000 fbbd bl 800e9a4 if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 800e22a: f894 30a4 ldrb.w r3, [r4, #164] @ 0xa4 800e22e: 2b02 cmp r3, #2 800e230: d004 beq.n 800e23c xReturn = pdFAIL; 800e232: 2500 movs r5, #0 taskEXIT_CRITICAL(); 800e234: f000 fbd8 bl 800e9e8 } 800e238: 4628 mov r0, r5 800e23a: bd38 pop {r3, r4, r5, pc} pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 800e23c: 2300 movs r3, #0 xReturn = pdPASS; 800e23e: 2501 movs r5, #1 pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 800e240: f884 30a4 strb.w r3, [r4, #164] @ 0xa4 taskEXIT_CRITICAL(); 800e244: f000 fbd0 bl 800e9e8 } 800e248: 4628 mov r0, r5 800e24a: bd38 pop {r3, r4, r5, pc} pxTCB = prvGetTCBFromHandle( xTask ); 800e24c: 4b01 ldr r3, [pc, #4] @ (800e254 ) 800e24e: 681c ldr r4, [r3, #0] 800e250: e7e9 b.n 800e226 800e252: bf00 nop 800e254: 24003040 .word 0x24003040 0800e258 : } } /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 800e258: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800e25c: 4e21 ldr r6, [pc, #132] @ (800e2e4 ) 800e25e: b084 sub sp, #16 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 800e260: e00d b.n 800e27e { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 800e262: 68db ldr r3, [r3, #12] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800e264: 68dc ldr r4, [r3, #12] xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 800e266: 681f ldr r7, [r3, #0] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 800e268: 1d25 adds r5, r4, #4 800e26a: 4628 mov r0, r5 800e26c: f7fd ff18 bl 800c0a0 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 800e270: 6a23 ldr r3, [r4, #32] 800e272: 4620 mov r0, r4 800e274: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 800e276: f894 3028 ldrb.w r3, [r4, #40] @ 0x28 800e27a: 075b lsls r3, r3, #29 800e27c: d40a bmi.n 800e294 while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 800e27e: 6833 ldr r3, [r6, #0] 800e280: 681a ldr r2, [r3, #0] 800e282: 2a00 cmp r2, #0 800e284: d1ed bne.n 800e262 mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; pxCurrentTimerList = pxOverflowTimerList; 800e286: 4a18 ldr r2, [pc, #96] @ (800e2e8 ) 800e288: 6811 ldr r1, [r2, #0] pxOverflowTimerList = pxTemp; 800e28a: 6013 str r3, [r2, #0] pxCurrentTimerList = pxOverflowTimerList; 800e28c: 6031 str r1, [r6, #0] } 800e28e: b004 add sp, #16 800e290: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 800e294: 69a3 ldr r3, [r4, #24] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 800e296: 4629 mov r1, r5 if( xTimerQueue != NULL ) 800e298: f8df 8050 ldr.w r8, [pc, #80] @ 800e2ec xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 800e29c: 443b add r3, r7 if( xReloadTime > xNextExpireTime ) 800e29e: 429f cmp r7, r3 800e2a0: d205 bcs.n 800e2ae vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 800e2a2: 6830 ldr r0, [r6, #0] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 800e2a4: 6063 str r3, [r4, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 800e2a6: 6124 str r4, [r4, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 800e2a8: f7fd fee2 bl 800c070 800e2ac: e7e7 b.n 800e27e if( xTimerQueue != NULL ) 800e2ae: f8d8 3000 ldr.w r3, [r8] xMessage.xMessageID = xCommandID; 800e2b2: 2500 movs r5, #0 if( xTimerQueue != NULL ) 800e2b4: b16b cbz r3, 800e2d2 xMessage.u.xTimerParameters.pxTimer = xTimer; 800e2b6: 9402 str r4, [sp, #8] xMessage.xMessageID = xCommandID; 800e2b8: e9cd 5700 strd r5, r7, [sp] if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 800e2bc: f7ff fd38 bl 800dd30 xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 800e2c0: 462b mov r3, r5 800e2c2: 462a mov r2, r5 800e2c4: 4669 mov r1, sp 800e2c6: f8d8 0000 ldr.w r0, [r8] 800e2ca: f7fd ffe3 bl 800c294 configASSERT( xResult ); 800e2ce: 2800 cmp r0, #0 800e2d0: d1d5 bne.n 800e27e 800e2d2: f04f 0350 mov.w r3, #80 @ 0x50 800e2d6: f383 8811 msr BASEPRI, r3 800e2da: f3bf 8f6f isb sy 800e2de: f3bf 8f4f dsb sy 800e2e2: e7fe b.n 800e2e2 800e2e4: 24003144 .word 0x24003144 800e2e8: 24003140 .word 0x24003140 800e2ec: 2400313c .word 0x2400313c 0800e2f0 : { 800e2f0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800e2f4: 4e9f ldr r6, [pc, #636] @ (800e574 ) 800e2f6: b089 sub sp, #36 @ 0x24 800e2f8: 4d9f ldr r5, [pc, #636] @ (800e578 ) portYIELD_WITHIN_API(); 800e2fa: f04f 29e0 mov.w r9, #3758153728 @ 0xe000e000 800e2fe: 4c9f ldr r4, [pc, #636] @ (800e57c ) *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 800e300: 6833 ldr r3, [r6, #0] 800e302: 681f ldr r7, [r3, #0] 800e304: 2f00 cmp r7, #0 800e306: f000 80b2 beq.w 800e46e xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 800e30a: 68db ldr r3, [r3, #12] 800e30c: 681f ldr r7, [r3, #0] vTaskSuspendAll(); 800e30e: f7ff fb41 bl 800d994 xTimeNow = xTaskGetTickCount(); 800e312: f7ff fb57 bl 800d9c4 if( xTimeNow < xLastTime ) 800e316: 682b ldr r3, [r5, #0] xTimeNow = xTaskGetTickCount(); 800e318: 4682 mov sl, r0 if( xTimeNow < xLastTime ) 800e31a: 4298 cmp r0, r3 800e31c: f0c0 80af bcc.w 800e47e if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 800e320: 4287 cmp r7, r0 xLastTime = xTimeNow; 800e322: 6028 str r0, [r5, #0] if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 800e324: f200 80d0 bhi.w 800e4c8 ( void ) xTaskResumeAll(); 800e328: f7ff fb3c bl 800d9a4 Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800e32c: 6833 ldr r3, [r6, #0] 800e32e: 68db ldr r3, [r3, #12] 800e330: f8d3 b00c ldr.w fp, [r3, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 800e334: f10b 0804 add.w r8, fp, #4 800e338: 4640 mov r0, r8 800e33a: f7fd feb1 bl 800c0a0 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 800e33e: f89b 3028 ldrb.w r3, [fp, #40] @ 0x28 800e342: 0758 lsls r0, r3, #29 800e344: f100 80d0 bmi.w 800e4e8 pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 800e348: f023 0301 bic.w r3, r3, #1 800e34c: f88b 3028 strb.w r3, [fp, #40] @ 0x28 pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 800e350: f8db 3020 ldr.w r3, [fp, #32] 800e354: 4658 mov r0, fp 800e356: 4798 blx r3 while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 800e358: 2200 movs r2, #0 800e35a: 4669 mov r1, sp 800e35c: 6820 ldr r0, [r4, #0] 800e35e: f7fe fa29 bl 800c7b4 800e362: 2800 cmp r0, #0 800e364: d0cc beq.n 800e300 if( xMessage.xMessageID < ( BaseType_t ) 0 ) 800e366: 9b00 ldr r3, [sp, #0] pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 800e368: 9802 ldr r0, [sp, #8] if( xMessage.xMessageID < ( BaseType_t ) 0 ) 800e36a: 2b00 cmp r3, #0 800e36c: db77 blt.n 800e45e pxTimer = xMessage.u.xTimerParameters.pxTimer; 800e36e: 9f02 ldr r7, [sp, #8] if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 800e370: 697b ldr r3, [r7, #20] 800e372: b113 cbz r3, 800e37a ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 800e374: 1d38 adds r0, r7, #4 800e376: f7fd fe93 bl 800c0a0 xTimeNow = xTaskGetTickCount(); 800e37a: f7ff fb23 bl 800d9c4 if( xTimeNow < xLastTime ) 800e37e: 682b ldr r3, [r5, #0] xTimeNow = xTaskGetTickCount(); 800e380: 4683 mov fp, r0 if( xTimeNow < xLastTime ) 800e382: 4298 cmp r0, r3 800e384: f0c0 8082 bcc.w 800e48c switch( xMessage.xMessageID ) 800e388: 9b00 ldr r3, [sp, #0] xLastTime = xTimeNow; 800e38a: f8c5 b000 str.w fp, [r5] switch( xMessage.xMessageID ) 800e38e: 2b09 cmp r3, #9 800e390: d8e2 bhi.n 800e358 800e392: e8df f003 tbb [pc, r3] 800e396: 0505 .short 0x0505 800e398: 5b3e5405 .word 0x5b3e5405 800e39c: 3e540505 .word 0x3e540505 pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 800e3a0: f897 2028 ldrb.w r2, [r7, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 800e3a4: 9b01 ldr r3, [sp, #4] pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 800e3a6: f042 0201 orr.w r2, r2, #1 listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 800e3aa: 613f str r7, [r7, #16] pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 800e3ac: f887 2028 strb.w r2, [r7, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 800e3b0: 69ba ldr r2, [r7, #24] 800e3b2: 1899 adds r1, r3, r2 800e3b4: bf2c ite cs 800e3b6: 2001 movcs r0, #1 800e3b8: 2000 movcc r0, #0 if( xNextExpiryTime <= xTimeNow ) 800e3ba: 4559 cmp r1, fp listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 800e3bc: 6079 str r1, [r7, #4] if( xNextExpiryTime <= xTimeNow ) 800e3be: f200 8085 bhi.w 800e4cc if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800e3c2: ebab 0303 sub.w r3, fp, r3 800e3c6: 429a cmp r2, r3 800e3c8: f200 80be bhi.w 800e548 pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 800e3cc: 6a3b ldr r3, [r7, #32] 800e3ce: 4638 mov r0, r7 800e3d0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 800e3d2: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 800e3d6: 0759 lsls r1, r3, #29 800e3d8: d5be bpl.n 800e358 if( xTimerQueue != NULL ) 800e3da: 6821 ldr r1, [r4, #0] xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 800e3dc: 9b01 ldr r3, [sp, #4] 800e3de: 69ba ldr r2, [r7, #24] if( xTimerQueue != NULL ) 800e3e0: b171 cbz r1, 800e400 xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 800e3e2: 4413 add r3, r2 xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 800e3e4: e9cd 3705 strd r3, r7, [sp, #20] xMessage.xMessageID = xCommandID; 800e3e8: 2700 movs r7, #0 800e3ea: 9704 str r7, [sp, #16] if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 800e3ec: f7ff fca0 bl 800dd30 xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 800e3f0: 463b mov r3, r7 800e3f2: 463a mov r2, r7 800e3f4: a904 add r1, sp, #16 800e3f6: 6820 ldr r0, [r4, #0] 800e3f8: f7fd ff4c bl 800c294 configASSERT( xResult ); 800e3fc: 2800 cmp r0, #0 800e3fe: d1ab bne.n 800e358 800e400: f04f 0350 mov.w r3, #80 @ 0x50 800e404: f383 8811 msr BASEPRI, r3 800e408: f3bf 8f6f isb sy 800e40c: f3bf 8f4f dsb sy 800e410: e7fe b.n 800e410 pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 800e412: f897 2028 ldrb.w r2, [r7, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 800e416: 9b01 ldr r3, [sp, #4] pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 800e418: f042 0201 orr.w r2, r2, #1 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 800e41c: 61bb str r3, [r7, #24] pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 800e41e: f887 2028 strb.w r2, [r7, #40] @ 0x28 configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 800e422: 2b00 cmp r3, #0 800e424: f000 809c beq.w 800e560 ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 800e428: 445b add r3, fp ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 800e42a: 1d39 adds r1, r7, #4 listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 800e42c: 613f str r7, [r7, #16] if( xNextExpiryTime <= xTimeNow ) 800e42e: 455b cmp r3, fp listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 800e430: 607b str r3, [r7, #4] if( xNextExpiryTime <= xTimeNow ) 800e432: d855 bhi.n 800e4e0 vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 800e434: 4b52 ldr r3, [pc, #328] @ (800e580 ) 800e436: 6818 ldr r0, [r3, #0] 800e438: f7fd fe1a bl 800c070 800e43c: e78c b.n 800e358 pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 800e43e: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 800e442: f023 0301 bic.w r3, r3, #1 800e446: f887 3028 strb.w r3, [r7, #40] @ 0x28 break; 800e44a: e785 b.n 800e358 if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 800e44c: f897 3028 ldrb.w r3, [r7, #40] @ 0x28 800e450: 079a lsls r2, r3, #30 800e452: d570 bpl.n 800e536 pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 800e454: f023 0301 bic.w r3, r3, #1 800e458: f887 3028 strb.w r3, [r7, #40] @ 0x28 800e45c: e77c b.n 800e358 pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 800e45e: 9b01 ldr r3, [sp, #4] 800e460: 9903 ldr r1, [sp, #12] 800e462: 4798 blx r3 if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 800e464: 9b00 ldr r3, [sp, #0] 800e466: 2b00 cmp r3, #0 800e468: f6ff af76 blt.w 800e358 800e46c: e77f b.n 800e36e vTaskSuspendAll(); 800e46e: f7ff fa91 bl 800d994 xTimeNow = xTaskGetTickCount(); 800e472: f7ff faa7 bl 800d9c4 if( xTimeNow < xLastTime ) 800e476: 682b ldr r3, [r5, #0] xTimeNow = xTaskGetTickCount(); 800e478: 4682 mov sl, r0 if( xTimeNow < xLastTime ) 800e47a: 4298 cmp r0, r3 800e47c: d209 bcs.n 800e492 prvSwitchTimerLists(); 800e47e: f7ff feeb bl 800e258 xLastTime = xTimeNow; 800e482: f8c5 a000 str.w sl, [r5] ( void ) xTaskResumeAll(); 800e486: f7ff fa8d bl 800d9a4 800e48a: e765 b.n 800e358 prvSwitchTimerLists(); 800e48c: f7ff fee4 bl 800e258 *pxTimerListsWereSwitched = pdTRUE; 800e490: e77a b.n 800e388 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 800e492: 4b3b ldr r3, [pc, #236] @ (800e580 ) xLastTime = xTimeNow; 800e494: f8c5 a000 str.w sl, [r5] xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 800e498: 681b ldr r3, [r3, #0] 800e49a: 681a ldr r2, [r3, #0] 800e49c: fab2 f282 clz r2, r2 800e4a0: 0952 lsrs r2, r2, #5 vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 800e4a2: eba7 010a sub.w r1, r7, sl 800e4a6: 6820 ldr r0, [r4, #0] 800e4a8: f7fe fd3a bl 800cf20 if( xTaskResumeAll() == pdFALSE ) 800e4ac: f7ff fa7a bl 800d9a4 800e4b0: 2800 cmp r0, #0 800e4b2: f47f af51 bne.w 800e358 portYIELD_WITHIN_API(); 800e4b6: f04f 5380 mov.w r3, #268435456 @ 0x10000000 800e4ba: f8c9 3d04 str.w r3, [r9, #3332] @ 0xd04 800e4be: f3bf 8f4f dsb sy 800e4c2: f3bf 8f6f isb sy 800e4c6: e747 b.n 800e358 800e4c8: 2200 movs r2, #0 800e4ca: e7ea b.n 800e4a2 if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 800e4cc: 455b cmp r3, fp 800e4ce: d902 bls.n 800e4d6 800e4d0: 2800 cmp r0, #0 800e4d2: f43f af7b beq.w 800e3cc vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 800e4d6: 1d39 adds r1, r7, #4 800e4d8: 6830 ldr r0, [r6, #0] 800e4da: f7fd fdc9 bl 800c070 return xProcessTimerNow; 800e4de: e73b b.n 800e358 vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 800e4e0: 6830 ldr r0, [r6, #0] 800e4e2: f7fd fdc5 bl 800c070 800e4e6: e737 b.n 800e358 if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 800e4e8: f8db 0018 ldr.w r0, [fp, #24] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 800e4ec: f8cb b010 str.w fp, [fp, #16] if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 800e4f0: 183b adds r3, r7, r0 if( xNextExpiryTime <= xTimeNow ) 800e4f2: 459a cmp sl, r3 listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 800e4f4: f8cb 3004 str.w r3, [fp, #4] if( xNextExpiryTime <= xTimeNow ) 800e4f8: d321 bcc.n 800e53e if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800e4fa: ebaa 0a07 sub.w sl, sl, r7 800e4fe: 4550 cmp r0, sl 800e500: d828 bhi.n 800e554 if( xTimerQueue != NULL ) 800e502: 6823 ldr r3, [r4, #0] 800e504: b173 cbz r3, 800e524 xMessage.u.xTimerParameters.pxTimer = xTimer; 800e506: e9cd 7b05 strd r7, fp, [sp, #20] xMessage.xMessageID = xCommandID; 800e50a: 2700 movs r7, #0 800e50c: 9704 str r7, [sp, #16] if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 800e50e: f7ff fc0f bl 800dd30 xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 800e512: 463b mov r3, r7 800e514: 463a mov r2, r7 800e516: a904 add r1, sp, #16 800e518: 6820 ldr r0, [r4, #0] 800e51a: f7fd febb bl 800c294 configASSERT( xResult ); 800e51e: 2800 cmp r0, #0 800e520: f47f af16 bne.w 800e350 800e524: f04f 0350 mov.w r3, #80 @ 0x50 800e528: f383 8811 msr BASEPRI, r3 800e52c: f3bf 8f6f isb sy 800e530: f3bf 8f4f dsb sy 800e534: e7fe b.n 800e534 vPortFree( pxTimer ); 800e536: 4638 mov r0, r7 800e538: f000 fc50 bl 800eddc 800e53c: e70c b.n 800e358 vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 800e53e: 4641 mov r1, r8 800e540: 6830 ldr r0, [r6, #0] 800e542: f7fd fd95 bl 800c070 return xProcessTimerNow; 800e546: e703 b.n 800e350 vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 800e548: 4b0d ldr r3, [pc, #52] @ (800e580 ) 800e54a: 1d39 adds r1, r7, #4 800e54c: 6818 ldr r0, [r3, #0] 800e54e: f7fd fd8f bl 800c070 return xProcessTimerNow; 800e552: e701 b.n 800e358 vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 800e554: 4b0a ldr r3, [pc, #40] @ (800e580 ) 800e556: 4641 mov r1, r8 800e558: 6818 ldr r0, [r3, #0] 800e55a: f7fd fd89 bl 800c070 return xProcessTimerNow; 800e55e: e6f7 b.n 800e350 800e560: f04f 0350 mov.w r3, #80 @ 0x50 800e564: f383 8811 msr BASEPRI, r3 800e568: f3bf 8f6f isb sy 800e56c: f3bf 8f4f dsb sy configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 800e570: e7fe b.n 800e570 800e572: bf00 nop 800e574: 24003144 .word 0x24003144 800e578: 24003134 .word 0x24003134 800e57c: 2400313c .word 0x2400313c 800e580: 24003140 .word 0x24003140 0800e584 : { 800e584: b5f0 push {r4, r5, r6, r7, lr} /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); { if( xTimerQueue == NULL ) 800e586: 4c23 ldr r4, [pc, #140] @ (800e614 ) { 800e588: b089 sub sp, #36 @ 0x24 taskENTER_CRITICAL(); 800e58a: f000 fa0b bl 800e9a4 if( xTimerQueue == NULL ) 800e58e: 6825 ldr r5, [r4, #0] 800e590: b335 cbz r5, 800e5e0 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 800e592: f000 fa29 bl 800e9e8 if( xTimerQueue != NULL ) 800e596: 6823 ldr r3, [r4, #0] 800e598: b1cb cbz r3, 800e5ce StaticTask_t *pxTimerTaskTCBBuffer = NULL; 800e59a: 2400 movs r4, #0 vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 800e59c: aa07 add r2, sp, #28 800e59e: a906 add r1, sp, #24 800e5a0: a805 add r0, sp, #20 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 800e5a2: 2502 movs r5, #2 StackType_t *pxTimerTaskStackBuffer = NULL; 800e5a4: e9cd 4405 strd r4, r4, [sp, #20] vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 800e5a8: f7fd fd34 bl 800c014 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 800e5ac: 4623 mov r3, r4 800e5ae: 9a07 ldr r2, [sp, #28] 800e5b0: 9500 str r5, [sp, #0] 800e5b2: e9dd 0105 ldrd r0, r1, [sp, #20] 800e5b6: e9cd 1001 strd r1, r0, [sp, #4] 800e5ba: 4917 ldr r1, [pc, #92] @ (800e618 ) 800e5bc: 4817 ldr r0, [pc, #92] @ (800e61c ) 800e5be: f7ff f8ad bl 800d71c 800e5c2: 4b17 ldr r3, [pc, #92] @ (800e620 ) 800e5c4: 6018 str r0, [r3, #0] if( xTimerTaskHandle != NULL ) 800e5c6: b110 cbz r0, 800e5ce } 800e5c8: 2001 movs r0, #1 800e5ca: b009 add sp, #36 @ 0x24 800e5cc: bdf0 pop {r4, r5, r6, r7, pc} 800e5ce: f04f 0350 mov.w r3, #80 @ 0x50 800e5d2: f383 8811 msr BASEPRI, r3 800e5d6: f3bf 8f6f isb sy 800e5da: f3bf 8f4f dsb sy configASSERT( xReturn ); 800e5de: e7fe b.n 800e5de vListInitialise( &xActiveTimerList1 ); 800e5e0: 4f10 ldr r7, [pc, #64] @ (800e624 ) vListInitialise( &xActiveTimerList2 ); 800e5e2: 4e11 ldr r6, [pc, #68] @ (800e628 ) vListInitialise( &xActiveTimerList1 ); 800e5e4: 4638 mov r0, r7 800e5e6: f7fd fd25 bl 800c034 vListInitialise( &xActiveTimerList2 ); 800e5ea: 4630 mov r0, r6 800e5ec: f7fd fd22 bl 800c034 pxCurrentTimerList = &xActiveTimerList1; 800e5f0: 4a0e ldr r2, [pc, #56] @ (800e62c ) xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e5f2: 9500 str r5, [sp, #0] 800e5f4: 2110 movs r1, #16 pxCurrentTimerList = &xActiveTimerList1; 800e5f6: 6017 str r7, [r2, #0] xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e5f8: 200a movs r0, #10 pxOverflowTimerList = &xActiveTimerList2; 800e5fa: 4a0d ldr r2, [pc, #52] @ (800e630 ) xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e5fc: 4b0d ldr r3, [pc, #52] @ (800e634 ) pxOverflowTimerList = &xActiveTimerList2; 800e5fe: 6016 str r6, [r2, #0] xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e600: 4a0d ldr r2, [pc, #52] @ (800e638 ) 800e602: f7fd fd99 bl 800c138 800e606: 6020 str r0, [r4, #0] if( xTimerQueue != NULL ) 800e608: 2800 cmp r0, #0 800e60a: d0c2 beq.n 800e592 vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 800e60c: 490b ldr r1, [pc, #44] @ (800e63c ) 800e60e: f7fe fc5f bl 800ced0 800e612: e7be b.n 800e592 800e614: 2400313c .word 0x2400313c 800e618: 08011a64 .word 0x08011a64 800e61c: 0800e2f1 .word 0x0800e2f1 800e620: 24003138 .word 0x24003138 800e624: 2400315c .word 0x2400315c 800e628: 24003148 .word 0x24003148 800e62c: 24003144 .word 0x24003144 800e630: 24003140 .word 0x24003140 800e634: 24003044 .word 0x24003044 800e638: 24003094 .word 0x24003094 800e63c: 08011a5c .word 0x08011a5c 0800e640 : { 800e640: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800e644: 4607 mov r7, r0 800e646: b085 sub sp, #20 pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 800e648: 202c movs r0, #44 @ 0x2c { 800e64a: 4688 mov r8, r1 800e64c: 4616 mov r6, r2 800e64e: 461d mov r5, r3 pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 800e650: f000 fb08 bl 800ec64 if( pxNewTimer != NULL ) 800e654: 4604 mov r4, r0 800e656: b1e8 cbz r0, 800e694 pxNewTimer->ucStatus = 0x00; 800e658: 2300 movs r3, #0 800e65a: f880 3028 strb.w r3, [r0, #40] @ 0x28 configASSERT( ( xTimerPeriodInTicks > 0 ) ); 800e65e: f1b8 0f00 cmp.w r8, #0 800e662: d01b beq.n 800e69c if( xTimerQueue == NULL ) 800e664: f8df 909c ldr.w r9, [pc, #156] @ 800e704 taskENTER_CRITICAL(); 800e668: f000 f99c bl 800e9a4 if( xTimerQueue == NULL ) 800e66c: f8d9 3000 ldr.w r3, [r9] 800e670: b1eb cbz r3, 800e6ae taskEXIT_CRITICAL(); 800e672: f000 f9b9 bl 800e9e8 pxNewTimer->pxCallbackFunction = pxCallbackFunction; 800e676: 9b0e ldr r3, [sp, #56] @ 0x38 vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 800e678: 1d20 adds r0, r4, #4 pxNewTimer->pcTimerName = pcTimerName; 800e67a: 6027 str r7, [r4, #0] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 800e67c: 6223 str r3, [r4, #32] pxNewTimer->pvTimerID = pvTimerID; 800e67e: e9c4 8506 strd r8, r5, [r4, #24] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 800e682: f7fd fce3 bl 800c04c if( uxAutoReload != pdFALSE ) 800e686: b12e cbz r6, 800e694 pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 800e688: f894 3028 ldrb.w r3, [r4, #40] @ 0x28 800e68c: f043 0304 orr.w r3, r3, #4 800e690: f884 3028 strb.w r3, [r4, #40] @ 0x28 } 800e694: 4620 mov r0, r4 800e696: b005 add sp, #20 800e698: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800e69c: f04f 0350 mov.w r3, #80 @ 0x50 800e6a0: f383 8811 msr BASEPRI, r3 800e6a4: f3bf 8f6f isb sy 800e6a8: f3bf 8f4f dsb sy configASSERT( ( xTimerPeriodInTicks > 0 ) ); 800e6ac: e7fe b.n 800e6ac vListInitialise( &xActiveTimerList1 ); 800e6ae: f8df b058 ldr.w fp, [pc, #88] @ 800e708 vListInitialise( &xActiveTimerList2 ); 800e6b2: f8df a058 ldr.w sl, [pc, #88] @ 800e70c vListInitialise( &xActiveTimerList1 ); 800e6b6: 4658 mov r0, fp 800e6b8: 9303 str r3, [sp, #12] 800e6ba: f7fd fcbb bl 800c034 vListInitialise( &xActiveTimerList2 ); 800e6be: 4650 mov r0, sl 800e6c0: f7fd fcb8 bl 800c034 xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e6c4: 9b03 ldr r3, [sp, #12] 800e6c6: 4a0a ldr r2, [pc, #40] @ (800e6f0 ) 800e6c8: 2110 movs r1, #16 800e6ca: 9300 str r3, [sp, #0] 800e6cc: 200a movs r0, #10 pxCurrentTimerList = &xActiveTimerList1; 800e6ce: 4b09 ldr r3, [pc, #36] @ (800e6f4 ) 800e6d0: f8c3 b000 str.w fp, [r3] pxOverflowTimerList = &xActiveTimerList2; 800e6d4: 4b08 ldr r3, [pc, #32] @ (800e6f8 ) 800e6d6: f8c3 a000 str.w sl, [r3] xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e6da: 4b08 ldr r3, [pc, #32] @ (800e6fc ) 800e6dc: f7fd fd2c bl 800c138 800e6e0: f8c9 0000 str.w r0, [r9] if( xTimerQueue != NULL ) 800e6e4: 2800 cmp r0, #0 800e6e6: d0c4 beq.n 800e672 vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 800e6e8: 4905 ldr r1, [pc, #20] @ (800e700 ) 800e6ea: f7fe fbf1 bl 800ced0 800e6ee: e7c0 b.n 800e672 800e6f0: 24003094 .word 0x24003094 800e6f4: 24003144 .word 0x24003144 800e6f8: 24003140 .word 0x24003140 800e6fc: 24003044 .word 0x24003044 800e700: 08011a5c .word 0x08011a5c 800e704: 2400313c .word 0x2400313c 800e708: 2400315c .word 0x2400315c 800e70c: 24003148 .word 0x24003148 0800e710 : { 800e710: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} volatile size_t xSize = sizeof( StaticTimer_t ); 800e714: 242c movs r4, #44 @ 0x2c { 800e716: b085 sub sp, #20 volatile size_t xSize = sizeof( StaticTimer_t ); 800e718: 9403 str r4, [sp, #12] configASSERT( xSize == sizeof( Timer_t ) ); 800e71a: 9c03 ldr r4, [sp, #12] 800e71c: 2c2c cmp r4, #44 @ 0x2c 800e71e: d008 beq.n 800e732 800e720: f04f 0350 mov.w r3, #80 @ 0x50 800e724: f383 8811 msr BASEPRI, r3 800e728: f3bf 8f6f isb sy 800e72c: f3bf 8f4f dsb sy 800e730: e7fe b.n 800e730 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 800e732: 461d mov r5, r3 800e734: 9b03 ldr r3, [sp, #12] configASSERT( pxTimerBuffer ); 800e736: 9b0f ldr r3, [sp, #60] @ 0x3c 800e738: b343 cbz r3, 800e78c pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 800e73a: 4616 mov r6, r2 800e73c: 461a mov r2, r3 800e73e: 2302 movs r3, #2 800e740: 460f mov r7, r1 800e742: f882 3028 strb.w r3, [r2, #40] @ 0x28 configASSERT( ( xTimerPeriodInTicks > 0 ) ); 800e746: b351 cbz r1, 800e79e if( xTimerQueue == NULL ) 800e748: 4c29 ldr r4, [pc, #164] @ (800e7f0 ) 800e74a: 4680 mov r8, r0 taskENTER_CRITICAL(); 800e74c: f000 f92a bl 800e9a4 if( xTimerQueue == NULL ) 800e750: f8d4 b000 ldr.w fp, [r4] 800e754: f1bb 0f00 cmp.w fp, #0 800e758: d02a beq.n 800e7b0 taskEXIT_CRITICAL(); 800e75a: f000 f945 bl 800e9e8 vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 800e75e: 9b0f ldr r3, [sp, #60] @ 0x3c pxNewTimer->pxCallbackFunction = pxCallbackFunction; 800e760: 9a0e ldr r2, [sp, #56] @ 0x38 vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 800e762: 1d18 adds r0, r3, #4 pxNewTimer->pcTimerName = pcTimerName; 800e764: f8c3 8000 str.w r8, [r3] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 800e768: 621a str r2, [r3, #32] pxNewTimer->pvTimerID = pvTimerID; 800e76a: e9c3 7506 strd r7, r5, [r3, #24] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 800e76e: f7fd fc6d bl 800c04c if( uxAutoReload != pdFALSE ) 800e772: b13e cbz r6, 800e784 pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 800e774: 9b0f ldr r3, [sp, #60] @ 0x3c 800e776: 9a0f ldr r2, [sp, #60] @ 0x3c 800e778: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e77c: f043 0304 orr.w r3, r3, #4 800e780: f882 3028 strb.w r3, [r2, #40] @ 0x28 } 800e784: 980f ldr r0, [sp, #60] @ 0x3c 800e786: b005 add sp, #20 800e788: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800e78c: f04f 0350 mov.w r3, #80 @ 0x50 800e790: f383 8811 msr BASEPRI, r3 800e794: f3bf 8f6f isb sy 800e798: f3bf 8f4f dsb sy configASSERT( pxTimerBuffer ); 800e79c: e7fe b.n 800e79c 800e79e: f04f 0350 mov.w r3, #80 @ 0x50 800e7a2: f383 8811 msr BASEPRI, r3 800e7a6: f3bf 8f6f isb sy 800e7aa: f3bf 8f4f dsb sy configASSERT( ( xTimerPeriodInTicks > 0 ) ); 800e7ae: e7fe b.n 800e7ae vListInitialise( &xActiveTimerList1 ); 800e7b0: f8df a054 ldr.w sl, [pc, #84] @ 800e808 vListInitialise( &xActiveTimerList2 ); 800e7b4: f8df 9054 ldr.w r9, [pc, #84] @ 800e80c vListInitialise( &xActiveTimerList1 ); 800e7b8: 4650 mov r0, sl 800e7ba: f7fd fc3b bl 800c034 vListInitialise( &xActiveTimerList2 ); 800e7be: 4648 mov r0, r9 800e7c0: f7fd fc38 bl 800c034 pxCurrentTimerList = &xActiveTimerList1; 800e7c4: 4a0b ldr r2, [pc, #44] @ (800e7f4 ) pxOverflowTimerList = &xActiveTimerList2; 800e7c6: 4b0c ldr r3, [pc, #48] @ (800e7f8 ) xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e7c8: 2110 movs r1, #16 800e7ca: f8cd b000 str.w fp, [sp] 800e7ce: 200a movs r0, #10 pxCurrentTimerList = &xActiveTimerList1; 800e7d0: f8c2 a000 str.w sl, [r2] pxOverflowTimerList = &xActiveTimerList2; 800e7d4: f8c3 9000 str.w r9, [r3] xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e7d8: 4a08 ldr r2, [pc, #32] @ (800e7fc ) 800e7da: 4b09 ldr r3, [pc, #36] @ (800e800 ) 800e7dc: f7fd fcac bl 800c138 800e7e0: 6020 str r0, [r4, #0] if( xTimerQueue != NULL ) 800e7e2: 2800 cmp r0, #0 800e7e4: d0b9 beq.n 800e75a vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 800e7e6: 4907 ldr r1, [pc, #28] @ (800e804 ) 800e7e8: f7fe fb72 bl 800ced0 800e7ec: e7b5 b.n 800e75a 800e7ee: bf00 nop 800e7f0: 2400313c .word 0x2400313c 800e7f4: 24003144 .word 0x24003144 800e7f8: 24003140 .word 0x24003140 800e7fc: 24003094 .word 0x24003094 800e800: 24003044 .word 0x24003044 800e804: 08011a5c .word 0x08011a5c 800e808: 2400315c .word 0x2400315c 800e80c: 24003148 .word 0x24003148 0800e810 : configASSERT( xTimer ); 800e810: b1c8 cbz r0, 800e846 { 800e812: b530 push {r4, r5, lr} if( xTimerQueue != NULL ) 800e814: 4d18 ldr r5, [pc, #96] @ (800e878 ) { 800e816: b085 sub sp, #20 if( xTimerQueue != NULL ) 800e818: 682c ldr r4, [r5, #0] 800e81a: b18c cbz r4, 800e840 if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 800e81c: 2905 cmp r1, #5 xMessage.u.xTimerParameters.pxTimer = xTimer; 800e81e: 9002 str r0, [sp, #8] xMessage.xMessageID = xCommandID; 800e820: e9cd 1200 strd r1, r2, [sp] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 800e824: dc18 bgt.n 800e858 if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 800e826: f7ff fa83 bl 800dd30 800e82a: 2802 cmp r0, #2 xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 800e82c: f04f 0300 mov.w r3, #0 if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 800e830: d01b beq.n 800e86a xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 800e832: 4669 mov r1, sp 800e834: 461a mov r2, r3 800e836: 6828 ldr r0, [r5, #0] 800e838: f7fd fd2c bl 800c294 } 800e83c: b005 add sp, #20 800e83e: bd30 pop {r4, r5, pc} BaseType_t xReturn = pdFAIL; 800e840: 4620 mov r0, r4 } 800e842: b005 add sp, #20 800e844: bd30 pop {r4, r5, pc} 800e846: f04f 0350 mov.w r3, #80 @ 0x50 800e84a: f383 8811 msr BASEPRI, r3 800e84e: f3bf 8f6f isb sy 800e852: f3bf 8f4f dsb sy configASSERT( xTimer ); 800e856: e7fe b.n 800e856 xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 800e858: 469c mov ip, r3 800e85a: 4669 mov r1, sp 800e85c: 2300 movs r3, #0 800e85e: 4620 mov r0, r4 800e860: 4662 mov r2, ip 800e862: f7fd ff41 bl 800c6e8 } 800e866: b005 add sp, #20 800e868: bd30 pop {r4, r5, pc} xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 800e86a: 9a08 ldr r2, [sp, #32] 800e86c: 4669 mov r1, sp 800e86e: 6828 ldr r0, [r5, #0] 800e870: f7fd fd10 bl 800c294 800e874: e7e5 b.n 800e842 800e876: bf00 nop 800e878: 2400313c .word 0x2400313c 0800e87c : BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { BaseType_t xReturn; Timer_t *pxTimer = xTimer; configASSERT( xTimer ); 800e87c: b158 cbz r0, 800e896 { 800e87e: b510 push {r4, lr} 800e880: 4604 mov r4, r0 /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 800e882: f000 f88f bl 800e9a4 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 800e886: f894 4028 ldrb.w r4, [r4, #40] @ 0x28 else { xReturn = pdTRUE; } } taskEXIT_CRITICAL(); 800e88a: f000 f8ad bl 800e9e8 800e88e: f004 0401 and.w r4, r4, #1 return xReturn; } /*lint !e818 Can't be pointer to const due to the typedef. */ 800e892: 4620 mov r0, r4 800e894: bd10 pop {r4, pc} 800e896: f04f 0350 mov.w r3, #80 @ 0x50 800e89a: f383 8811 msr BASEPRI, r3 800e89e: f3bf 8f6f isb sy 800e8a2: f3bf 8f4f dsb sy configASSERT( xTimer ); 800e8a6: e7fe b.n 800e8a6 0800e8a8 : void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { Timer_t * const pxTimer = xTimer; void *pvReturn; configASSERT( xTimer ); 800e8a8: b140 cbz r0, 800e8bc { 800e8aa: b510 push {r4, lr} 800e8ac: 4604 mov r4, r0 taskENTER_CRITICAL(); 800e8ae: f000 f879 bl 800e9a4 { pvReturn = pxTimer->pvTimerID; 800e8b2: 69e4 ldr r4, [r4, #28] } taskEXIT_CRITICAL(); 800e8b4: f000 f898 bl 800e9e8 return pvReturn; } 800e8b8: 4620 mov r0, r4 800e8ba: bd10 pop {r4, pc} 800e8bc: f04f 0350 mov.w r3, #80 @ 0x50 800e8c0: f383 8811 msr BASEPRI, r3 800e8c4: f3bf 8f6f isb sy 800e8c8: f3bf 8f4f dsb sy configASSERT( xTimer ); 800e8cc: e7fe b.n 800e8cc 800e8ce: bf00 nop 0800e8d0 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 800e8d0: 4808 ldr r0, [pc, #32] @ (800e8f4 ) 800e8d2: 6800 ldr r0, [r0, #0] 800e8d4: 6800 ldr r0, [r0, #0] 800e8d6: f380 8808 msr MSP, r0 800e8da: f04f 0000 mov.w r0, #0 800e8de: f380 8814 msr CONTROL, r0 800e8e2: b662 cpsie i 800e8e4: b661 cpsie f 800e8e6: f3bf 8f4f dsb sy 800e8ea: f3bf 8f6f isb sy 800e8ee: df00 svc 0 800e8f0: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 800e8f2: 0000 .short 0x0000 800e8f4: e000ed08 .word 0xe000ed08 0800e8f8 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 800e8f8: f8df 000c ldr.w r0, [pc, #12] @ 800e908 800e8fc: 6801 ldr r1, [r0, #0] 800e8fe: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800e902: 6001 str r1, [r0, #0] 800e904: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 800e906: 0000 .short 0x0000 800e908: e000ed88 .word 0xe000ed88 0800e90c : configASSERT( uxCriticalNesting == ~0UL ); 800e90c: 4b0e ldr r3, [pc, #56] @ (800e948 ) { 800e90e: b082 sub sp, #8 volatile uint32_t ulDummy = 0; 800e910: 2200 movs r2, #0 configASSERT( uxCriticalNesting == ~0UL ); 800e912: 681b ldr r3, [r3, #0] volatile uint32_t ulDummy = 0; 800e914: 9201 str r2, [sp, #4] configASSERT( uxCriticalNesting == ~0UL ); 800e916: 3301 adds r3, #1 800e918: d008 beq.n 800e92c 800e91a: f04f 0350 mov.w r3, #80 @ 0x50 800e91e: f383 8811 msr BASEPRI, r3 800e922: f3bf 8f6f isb sy 800e926: f3bf 8f4f dsb sy 800e92a: e7fe b.n 800e92a 800e92c: f04f 0350 mov.w r3, #80 @ 0x50 800e930: f383 8811 msr BASEPRI, r3 800e934: f3bf 8f6f isb sy 800e938: f3bf 8f4f dsb sy while( ulDummy == 0 ) 800e93c: 9b01 ldr r3, [sp, #4] 800e93e: 2b00 cmp r3, #0 800e940: d0fc beq.n 800e93c } 800e942: b002 add sp, #8 800e944: 4770 bx lr 800e946: bf00 nop 800e948: 24000044 .word 0x24000044 0800e94c : { 800e94c: 4603 mov r3, r0 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 800e94e: f021 0101 bic.w r1, r1, #1 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 800e952: 4809 ldr r0, [pc, #36] @ (800e978 ) { 800e954: b410 push {r4} *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 800e956: f04f 7480 mov.w r4, #16777216 @ 0x1000000 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 800e95a: f843 0c0c str.w r0, [r3, #-12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 800e95e: f843 2c20 str.w r2, [r3, #-32] } 800e962: f1a3 0044 sub.w r0, r3, #68 @ 0x44 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 800e966: e943 1402 strd r1, r4, [r3, #-8] *pxTopOfStack = portINITIAL_EXC_RETURN; 800e96a: f06f 0102 mvn.w r1, #2 } 800e96e: f85d 4b04 ldr.w r4, [sp], #4 *pxTopOfStack = portINITIAL_EXC_RETURN; 800e972: f843 1c24 str.w r1, [r3, #-36] } 800e976: 4770 bx lr 800e978: 0800e90d .word 0x0800e90d 800e97c: 00000000 .word 0x00000000 0800e980 : __asm volatile ( 800e980: 4b07 ldr r3, [pc, #28] @ (800e9a0 ) 800e982: 6819 ldr r1, [r3, #0] 800e984: 6808 ldr r0, [r1, #0] 800e986: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800e98a: f380 8809 msr PSP, r0 800e98e: f3bf 8f6f isb sy 800e992: f04f 0000 mov.w r0, #0 800e996: f380 8811 msr BASEPRI, r0 800e99a: 4770 bx lr 800e99c: f3af 8000 nop.w 0800e9a0 : 800e9a0: 24003040 .word 0x24003040 0800e9a4 : 800e9a4: f04f 0350 mov.w r3, #80 @ 0x50 800e9a8: f383 8811 msr BASEPRI, r3 800e9ac: f3bf 8f6f isb sy 800e9b0: f3bf 8f4f dsb sy uxCriticalNesting++; 800e9b4: 4a0b ldr r2, [pc, #44] @ (800e9e4 ) 800e9b6: 6813 ldr r3, [r2, #0] 800e9b8: 3301 adds r3, #1 if( uxCriticalNesting == 1 ) 800e9ba: 2b01 cmp r3, #1 uxCriticalNesting++; 800e9bc: 6013 str r3, [r2, #0] if( uxCriticalNesting == 1 ) 800e9be: d000 beq.n 800e9c2 } 800e9c0: 4770 bx lr configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 800e9c2: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800e9c6: f8d3 3d04 ldr.w r3, [r3, #3332] @ 0xd04 800e9ca: b2db uxtb r3, r3 800e9cc: 2b00 cmp r3, #0 800e9ce: d0f7 beq.n 800e9c0 800e9d0: f04f 0350 mov.w r3, #80 @ 0x50 800e9d4: f383 8811 msr BASEPRI, r3 800e9d8: f3bf 8f6f isb sy 800e9dc: f3bf 8f4f dsb sy 800e9e0: e7fe b.n 800e9e0 800e9e2: bf00 nop 800e9e4: 24000044 .word 0x24000044 0800e9e8 : configASSERT( uxCriticalNesting ); 800e9e8: 4a08 ldr r2, [pc, #32] @ (800ea0c ) 800e9ea: 6813 ldr r3, [r2, #0] 800e9ec: b943 cbnz r3, 800ea00 800e9ee: f04f 0350 mov.w r3, #80 @ 0x50 800e9f2: f383 8811 msr BASEPRI, r3 800e9f6: f3bf 8f6f isb sy 800e9fa: f3bf 8f4f dsb sy 800e9fe: e7fe b.n 800e9fe uxCriticalNesting--; 800ea00: 3b01 subs r3, #1 800ea02: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 800ea04: b90b cbnz r3, 800ea0a __asm volatile 800ea06: f383 8811 msr BASEPRI, r3 } 800ea0a: 4770 bx lr 800ea0c: 24000044 .word 0x24000044 0800ea10 : __asm volatile 800ea10: f3ef 8009 mrs r0, PSP 800ea14: f3bf 8f6f isb sy 800ea18: 4b15 ldr r3, [pc, #84] @ (800ea70 ) 800ea1a: 681a ldr r2, [r3, #0] 800ea1c: f01e 0f10 tst.w lr, #16 800ea20: bf08 it eq 800ea22: ed20 8a10 vstmdbeq r0!, {s16-s31} 800ea26: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800ea2a: 6010 str r0, [r2, #0] 800ea2c: e92d 0009 stmdb sp!, {r0, r3} 800ea30: f04f 0050 mov.w r0, #80 @ 0x50 800ea34: f380 8811 msr BASEPRI, r0 800ea38: f3bf 8f4f dsb sy 800ea3c: f3bf 8f6f isb sy 800ea40: f7fe ffd6 bl 800d9f0 800ea44: f04f 0000 mov.w r0, #0 800ea48: f380 8811 msr BASEPRI, r0 800ea4c: bc09 pop {r0, r3} 800ea4e: 6819 ldr r1, [r3, #0] 800ea50: 6808 ldr r0, [r1, #0] 800ea52: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800ea56: f01e 0f10 tst.w lr, #16 800ea5a: bf08 it eq 800ea5c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 800ea60: f380 8809 msr PSP, r0 800ea64: f3bf 8f6f isb sy 800ea68: 4770 bx lr 800ea6a: bf00 nop 800ea6c: f3af 8000 nop.w 0800ea70 : 800ea70: 24003040 .word 0x24003040 0800ea74 : { 800ea74: b508 push {r3, lr} __asm volatile 800ea76: f04f 0350 mov.w r3, #80 @ 0x50 800ea7a: f383 8811 msr BASEPRI, r3 800ea7e: f3bf 8f6f isb sy 800ea82: f3bf 8f4f dsb sy if( xTaskIncrementTick() != pdFALSE ) 800ea86: f7fe ffa3 bl 800d9d0 800ea8a: b128 cbz r0, 800ea98 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 800ea8c: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800ea90: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800ea94: f8c3 2d04 str.w r2, [r3, #3332] @ 0xd04 __asm volatile 800ea98: 2300 movs r3, #0 800ea9a: f383 8811 msr BASEPRI, r3 } 800ea9e: bd08 pop {r3, pc} 0800eaa0 : portNVIC_SYSTICK_CTRL_REG = 0UL; 800eaa0: f04f 22e0 mov.w r2, #3758153728 @ 0xe000e000 800eaa4: 2300 movs r3, #0 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 800eaa6: 4806 ldr r0, [pc, #24] @ (800eac0 ) portNVIC_SYSTICK_CTRL_REG = 0UL; 800eaa8: 6113 str r3, [r2, #16] portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 800eaaa: 4906 ldr r1, [pc, #24] @ (800eac4 ) portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 800eaac: 6193 str r3, [r2, #24] portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 800eaae: 6803 ldr r3, [r0, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 800eab0: 2007 movs r0, #7 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 800eab2: fba1 1303 umull r1, r3, r1, r3 800eab6: 099b lsrs r3, r3, #6 800eab8: 3b01 subs r3, #1 800eaba: 6153 str r3, [r2, #20] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 800eabc: 6110 str r0, [r2, #16] } 800eabe: 4770 bx lr 800eac0: 24000038 .word 0x24000038 800eac4: 10624dd3 .word 0x10624dd3 0800eac8 : configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 800eac8: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800eacc: 4a48 ldr r2, [pc, #288] @ (800ebf0 ) 800eace: f8d3 1d00 ldr.w r1, [r3, #3328] @ 0xd00 800ead2: 4291 cmp r1, r2 800ead4: d041 beq.n 800eb5a configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 800ead6: f8d3 2d00 ldr.w r2, [r3, #3328] @ 0xd00 800eada: 4b46 ldr r3, [pc, #280] @ (800ebf4 ) 800eadc: 429a cmp r2, r3 800eade: d033 beq.n 800eb48 ulOriginalPriority = *pucFirstUserPriorityRegister; 800eae0: 4b45 ldr r3, [pc, #276] @ (800ebf8 ) *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 800eae2: f04f 0cff mov.w ip, #255 @ 0xff ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 800eae6: 4845 ldr r0, [pc, #276] @ (800ebfc ) ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 800eae8: 4945 ldr r1, [pc, #276] @ (800ec00 ) { 800eaea: b570 push {r4, r5, r6, lr} ulOriginalPriority = *pucFirstUserPriorityRegister; 800eaec: 781a ldrb r2, [r3, #0] { 800eaee: b084 sub sp, #16 ulOriginalPriority = *pucFirstUserPriorityRegister; 800eaf0: b2d2 uxtb r2, r2 800eaf2: 9202 str r2, [sp, #8] ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 800eaf4: 2207 movs r2, #7 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 800eaf6: f883 c000 strb.w ip, [r3] ucMaxPriorityValue = *pucFirstUserPriorityRegister; 800eafa: 781b ldrb r3, [r3, #0] ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 800eafc: 6002 str r2, [r0, #0] ucMaxPriorityValue = *pucFirstUserPriorityRegister; 800eafe: b2db uxtb r3, r3 800eb00: f88d 3007 strb.w r3, [sp, #7] ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 800eb04: f89d 3007 ldrb.w r3, [sp, #7] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 800eb08: f89d 2007 ldrb.w r2, [sp, #7] ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 800eb0c: f003 0350 and.w r3, r3, #80 @ 0x50 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 800eb10: 0612 lsls r2, r2, #24 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 800eb12: 700b strb r3, [r1, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 800eb14: d50f bpl.n 800eb36 800eb16: 2206 movs r2, #6 ucMaxPriorityValue <<= ( uint8_t ) 0x01; 800eb18: f89d 3007 ldrb.w r3, [sp, #7] 800eb1c: 4611 mov r1, r2 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 800eb1e: 3a01 subs r2, #1 ucMaxPriorityValue <<= ( uint8_t ) 0x01; 800eb20: 005b lsls r3, r3, #1 800eb22: b2db uxtb r3, r3 800eb24: f88d 3007 strb.w r3, [sp, #7] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 800eb28: f89d 3007 ldrb.w r3, [sp, #7] 800eb2c: 061b lsls r3, r3, #24 800eb2e: d4f3 bmi.n 800eb18 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 800eb30: 2903 cmp r1, #3 800eb32: d01b beq.n 800eb6c 800eb34: 6001 str r1, [r0, #0] __asm volatile 800eb36: f04f 0350 mov.w r3, #80 @ 0x50 800eb3a: f383 8811 msr BASEPRI, r3 800eb3e: f3bf 8f6f isb sy 800eb42: f3bf 8f4f dsb sy 800eb46: e7fe b.n 800eb46 800eb48: f04f 0350 mov.w r3, #80 @ 0x50 800eb4c: f383 8811 msr BASEPRI, r3 800eb50: f3bf 8f6f isb sy 800eb54: f3bf 8f4f dsb sy configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 800eb58: e7fe b.n 800eb58 800eb5a: f04f 0350 mov.w r3, #80 @ 0x50 800eb5e: f383 8811 msr BASEPRI, r3 800eb62: f3bf 8f6f isb sy 800eb66: f3bf 8f4f dsb sy configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 800eb6a: e7fe b.n 800eb6a *pucFirstUserPriorityRegister = ulOriginalPriority; 800eb6c: 9b02 ldr r3, [sp, #8] portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 800eb6e: f04f 24e0 mov.w r4, #3758153728 @ 0xe000e000 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 800eb72: f44f 7140 mov.w r1, #768 @ 0x300 *pucFirstUserPriorityRegister = ulOriginalPriority; 800eb76: 4a20 ldr r2, [pc, #128] @ (800ebf8 ) 800eb78: b2db uxtb r3, r3 uxCriticalNesting = 0; 800eb7a: 4e22 ldr r6, [pc, #136] @ (800ec04 ) ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 800eb7c: 6001 str r1, [r0, #0] uxCriticalNesting = 0; 800eb7e: 2500 movs r5, #0 *pucFirstUserPriorityRegister = ulOriginalPriority; 800eb80: 7013 strb r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 800eb82: f8d4 3d20 ldr.w r3, [r4, #3360] @ 0xd20 800eb86: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800eb8a: f8c4 3d20 str.w r3, [r4, #3360] @ 0xd20 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 800eb8e: f8d4 3d20 ldr.w r3, [r4, #3360] @ 0xd20 800eb92: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 800eb96: f8c4 3d20 str.w r3, [r4, #3360] @ 0xd20 vPortSetupTimerInterrupt(); 800eb9a: f7ff ff81 bl 800eaa0 uxCriticalNesting = 0; 800eb9e: 6035 str r5, [r6, #0] vPortEnableVFP(); 800eba0: f7ff feaa bl 800e8f8 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 800eba4: f8d4 3f34 ldr.w r3, [r4, #3892] @ 0xf34 800eba8: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 800ebac: f8c4 3f34 str.w r3, [r4, #3892] @ 0xf34 prvPortStartFirstTask(); 800ebb0: f7ff fe8e bl 800e8d0 vTaskSwitchContext(); 800ebb4: f7fe ff1c bl 800d9f0 configASSERT( uxCriticalNesting == ~0UL ); 800ebb8: 6833 ldr r3, [r6, #0] volatile uint32_t ulDummy = 0; 800ebba: 9503 str r5, [sp, #12] configASSERT( uxCriticalNesting == ~0UL ); 800ebbc: 3301 adds r3, #1 800ebbe: d008 beq.n 800ebd2 800ebc0: f04f 0350 mov.w r3, #80 @ 0x50 800ebc4: f383 8811 msr BASEPRI, r3 800ebc8: f3bf 8f6f isb sy 800ebcc: f3bf 8f4f dsb sy 800ebd0: e7fe b.n 800ebd0 800ebd2: f04f 0350 mov.w r3, #80 @ 0x50 800ebd6: f383 8811 msr BASEPRI, r3 800ebda: f3bf 8f6f isb sy 800ebde: f3bf 8f4f dsb sy while( ulDummy == 0 ) 800ebe2: 9b03 ldr r3, [sp, #12] 800ebe4: 2b00 cmp r3, #0 800ebe6: d0fc beq.n 800ebe2 } 800ebe8: 2000 movs r0, #0 800ebea: b004 add sp, #16 800ebec: bd70 pop {r4, r5, r6, pc} 800ebee: bf00 nop 800ebf0: 410fc271 .word 0x410fc271 800ebf4: 410fc270 .word 0x410fc270 800ebf8: e000e400 .word 0xe000e400 800ebfc: 24003170 .word 0x24003170 800ec00: 24003174 .word 0x24003174 800ec04: 24000044 .word 0x24000044 0800ec08 : { uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 800ec08: f3ef 8305 mrs r3, IPSR /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 800ec0c: 2b0f cmp r3, #15 800ec0e: d90e bls.n 800ec2e { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 800ec10: 4911 ldr r1, [pc, #68] @ (800ec58 ) interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 800ec12: 4a12 ldr r2, [pc, #72] @ (800ec5c ) ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 800ec14: 5c5b ldrb r3, [r3, r1] configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 800ec16: 7812 ldrb r2, [r2, #0] 800ec18: 429a cmp r2, r3 800ec1a: d908 bls.n 800ec2e 800ec1c: f04f 0350 mov.w r3, #80 @ 0x50 800ec20: f383 8811 msr BASEPRI, r3 800ec24: f3bf 8f6f isb sy 800ec28: f3bf 8f4f dsb sy 800ec2c: e7fe b.n 800ec2c configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 800ec2e: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000 800ec32: 4a0b ldr r2, [pc, #44] @ (800ec60 ) 800ec34: f8d3 3d0c ldr.w r3, [r3, #3340] @ 0xd0c 800ec38: 6812 ldr r2, [r2, #0] 800ec3a: f403 63e0 and.w r3, r3, #1792 @ 0x700 800ec3e: 4293 cmp r3, r2 800ec40: d908 bls.n 800ec54 800ec42: f04f 0350 mov.w r3, #80 @ 0x50 800ec46: f383 8811 msr BASEPRI, r3 800ec4a: f3bf 8f6f isb sy 800ec4e: f3bf 8f4f dsb sy 800ec52: e7fe b.n 800ec52 } 800ec54: 4770 bx lr 800ec56: bf00 nop 800ec58: e000e3f0 .word 0xe000e3f0 800ec5c: 24003174 .word 0x24003174 800ec60: 24003170 .word 0x24003170 0800ec64 : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 800ec64: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800ec68: 4604 mov r4, r0 BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; vTaskSuspendAll(); 800ec6a: f7fe fe93 bl 800d994 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 800ec6e: 4a53 ldr r2, [pc, #332] @ (800edbc ) 800ec70: 6815 ldr r5, [r2, #0] 800ec72: 2d00 cmp r5, #0 800ec74: d035 beq.n 800ece2 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 800ec76: 4b52 ldr r3, [pc, #328] @ (800edc0 ) 800ec78: 681e ldr r6, [r3, #0] 800ec7a: 4234 tst r4, r6 800ec7c: d12b bne.n 800ecd6 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 800ec7e: b354 cbz r4, 800ecd6 { xWantedSize += xHeapStructSize; 800ec80: f104 0008 add.w r0, r4, #8 /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 800ec84: 0764 lsls r4, r4, #29 800ec86: d002 beq.n 800ec8e { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 800ec88: f020 0007 bic.w r0, r0, #7 800ec8c: 3008 adds r0, #8 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 800ec8e: b310 cbz r0, 800ecd6 800ec90: f8df e140 ldr.w lr, [pc, #320] @ 800edd4 800ec94: f8de c000 ldr.w ip, [lr] 800ec98: 4584 cmp ip, r0 800ec9a: d31c bcc.n 800ecd6 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; pxBlock = xStart.pxNextFreeBlock; 800ec9c: 4c49 ldr r4, [pc, #292] @ (800edc4 ) 800ec9e: 6823 ldr r3, [r4, #0] while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 800eca0: e003 b.n 800ecaa 800eca2: 681a ldr r2, [r3, #0] 800eca4: b122 cbz r2, 800ecb0 800eca6: 461c mov r4, r3 800eca8: 4613 mov r3, r2 800ecaa: 6859 ldr r1, [r3, #4] 800ecac: 4281 cmp r1, r0 800ecae: d3f8 bcc.n 800eca2 pxBlock = pxBlock->pxNextFreeBlock; } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 800ecb0: 42ab cmp r3, r5 800ecb2: d010 beq.n 800ecd6 BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 800ecb4: 681a ldr r2, [r3, #0] 800ecb6: 6022 str r2, [r4, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 800ecb8: 1a0a subs r2, r1, r0 800ecba: 2a10 cmp r2, #16 800ecbc: d947 bls.n 800ed4e { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 800ecbe: 181c adds r4, r3, r0 configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 800ecc0: 0761 lsls r1, r4, #29 800ecc2: d02d beq.n 800ed20 800ecc4: f04f 0350 mov.w r3, #80 @ 0x50 800ecc8: f383 8811 msr BASEPRI, r3 800eccc: f3bf 8f6f isb sy 800ecd0: f3bf 8f4f dsb sy 800ecd4: e7fe b.n 800ecd4 void *pvReturn = NULL; 800ecd6: 2400 movs r4, #0 mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 800ecd8: f7fe fe64 bl 800d9a4 } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); return pvReturn; } 800ecdc: 4620 mov r0, r4 800ecde: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 800ece2: 4b39 ldr r3, [pc, #228] @ (800edc8 ) /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 800ece4: f04f 4000 mov.w r0, #2147483648 @ 0x80000000 xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 800ece8: 4e36 ldr r6, [pc, #216] @ (800edc4 ) if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 800ecea: 075d lsls r5, r3, #29 uxAddress -= xHeapStructSize; 800ecec: 4d37 ldr r5, [pc, #220] @ (800edcc ) uxAddress += ( portBYTE_ALIGNMENT - 1 ); 800ecee: bf18 it ne 800ecf0: 3307 addne r3, #7 uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 800ecf2: f025 0507 bic.w r5, r5, #7 uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 800ecf6: bf18 it ne 800ecf8: f023 0307 bicne.w r3, r3, #7 pxEnd = ( void * ) uxAddress; 800ecfc: 6015 str r5, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 800ecfe: 2200 movs r2, #0 xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 800ed00: 6033 str r3, [r6, #0] 800ed02: 4619 mov r1, r3 xStart.xBlockSize = ( size_t ) 0; 800ed04: 6072 str r2, [r6, #4] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 800ed06: 1aeb subs r3, r5, r3 } 800ed08: 4606 mov r6, r0 pxEnd->pxNextFreeBlock = NULL; 800ed0a: e9c5 2200 strd r2, r2, [r5] xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 800ed0e: 4a30 ldr r2, [pc, #192] @ (800edd0 ) 800ed10: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 800ed12: 4a30 ldr r2, [pc, #192] @ (800edd4 ) pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 800ed14: e9c1 5300 strd r5, r3, [r1] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 800ed18: 6013 str r3, [r2, #0] xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 800ed1a: 4b29 ldr r3, [pc, #164] @ (800edc0 ) 800ed1c: 6018 str r0, [r3, #0] } 800ed1e: e7ac b.n 800ec7a pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 800ed20: 6062 str r2, [r4, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 800ed22: 4a28 ldr r2, [pc, #160] @ (800edc4 ) pxBlock->xBlockSize = xWantedSize; 800ed24: 6058 str r0, [r3, #4] for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 800ed26: 4617 mov r7, r2 800ed28: 6812 ldr r2, [r2, #0] 800ed2a: 4294 cmp r4, r2 800ed2c: d8fb bhi.n 800ed26 } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 800ed2e: 6879 ldr r1, [r7, #4] { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 800ed30: f8d4 8004 ldr.w r8, [r4, #4] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 800ed34: eb07 0901 add.w r9, r7, r1 800ed38: 454c cmp r4, r9 800ed3a: d028 beq.n 800ed8e } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 800ed3c: eb04 0108 add.w r1, r4, r8 800ed40: 428a cmp r2, r1 800ed42: d02e beq.n 800eda2 pxBlockToInsert->pxNextFreeBlock = pxEnd; } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 800ed44: 4601 mov r1, r0 800ed46: 6022 str r2, [r4, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 800ed48: 42a7 cmp r7, r4 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 800ed4a: bf18 it ne 800ed4c: 603c strne r4, [r7, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 800ed4e: 4820 ldr r0, [pc, #128] @ (800edd0 ) xFreeBytesRemaining -= pxBlock->xBlockSize; 800ed50: ebac 0201 sub.w r2, ip, r1 pxBlock->pxNextFreeBlock = NULL; 800ed54: 2500 movs r5, #0 pxBlock->xBlockSize |= xBlockAllocatedBit; 800ed56: 4331 orrs r1, r6 if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 800ed58: 6804 ldr r4, [r0, #0] xFreeBytesRemaining -= pxBlock->xBlockSize; 800ed5a: f8ce 2000 str.w r2, [lr] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 800ed5e: 42a2 cmp r2, r4 pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 800ed60: f103 0408 add.w r4, r3, #8 pxBlock->xBlockSize |= xBlockAllocatedBit; 800ed64: 6059 str r1, [r3, #4] xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 800ed66: bf38 it cc 800ed68: 6002 strcc r2, [r0, #0] xNumberOfSuccessfulAllocations++; 800ed6a: 481b ldr r0, [pc, #108] @ (800edd8 ) pxBlock->pxNextFreeBlock = NULL; 800ed6c: 601d str r5, [r3, #0] xNumberOfSuccessfulAllocations++; 800ed6e: 6802 ldr r2, [r0, #0] 800ed70: 3201 adds r2, #1 800ed72: 6002 str r2, [r0, #0] ( void ) xTaskResumeAll(); 800ed74: f7fe fe16 bl 800d9a4 configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 800ed78: 0763 lsls r3, r4, #29 800ed7a: d0af beq.n 800ecdc 800ed7c: f04f 0350 mov.w r3, #80 @ 0x50 800ed80: f383 8811 msr BASEPRI, r3 800ed84: f3bf 8f6f isb sy 800ed88: f3bf 8f4f dsb sy 800ed8c: e7fe b.n 800ed8c pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 800ed8e: 4488 add r8, r1 if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 800ed90: eb07 0108 add.w r1, r7, r8 pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 800ed94: f8c7 8004 str.w r8, [r7, #4] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 800ed98: 428a cmp r2, r1 800ed9a: d001 beq.n 800eda0 xFreeBytesRemaining -= pxBlock->xBlockSize; 800ed9c: 6859 ldr r1, [r3, #4] 800ed9e: e7d6 b.n 800ed4e if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 800eda0: 463c mov r4, r7 if( pxIterator->pxNextFreeBlock != pxEnd ) 800eda2: 42aa cmp r2, r5 800eda4: d006 beq.n 800edb4 pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 800eda6: 6851 ldr r1, [r2, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 800eda8: 6812 ldr r2, [r2, #0] pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 800edaa: 4441 add r1, r8 pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 800edac: 6022 str r2, [r4, #0] pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 800edae: 6061 str r1, [r4, #4] xFreeBytesRemaining -= pxBlock->xBlockSize; 800edb0: 6859 ldr r1, [r3, #4] 800edb2: e7c9 b.n 800ed48 800edb4: 6859 ldr r1, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxEnd; 800edb6: 6022 str r2, [r4, #0] 800edb8: e7c6 b.n 800ed48 800edba: bf00 nop 800edbc: 2400318c .word 0x2400318c 800edc0: 24003178 .word 0x24003178 800edc4: 24003190 .word 0x24003190 800edc8: 24003198 .word 0x24003198 800edcc: 24013190 .word 0x24013190 800edd0: 24003184 .word 0x24003184 800edd4: 24003188 .word 0x24003188 800edd8: 24003180 .word 0x24003180 0800eddc : if( pv != NULL ) 800eddc: b1d0 cbz r0, 800ee14 configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 800edde: 4a2d ldr r2, [pc, #180] @ (800ee94 ) 800ede0: f850 3c04 ldr.w r3, [r0, #-4] 800ede4: 6812 ldr r2, [r2, #0] 800ede6: 4213 tst r3, r2 800ede8: d00b beq.n 800ee02 configASSERT( pxLink->pxNextFreeBlock == NULL ); 800edea: f850 1c08 ldr.w r1, [r0, #-8] 800edee: b191 cbz r1, 800ee16 800edf0: f04f 0350 mov.w r3, #80 @ 0x50 800edf4: f383 8811 msr BASEPRI, r3 800edf8: f3bf 8f6f isb sy 800edfc: f3bf 8f4f dsb sy 800ee00: e7fe b.n 800ee00 800ee02: f04f 0350 mov.w r3, #80 @ 0x50 800ee06: f383 8811 msr BASEPRI, r3 800ee0a: f3bf 8f6f isb sy 800ee0e: f3bf 8f4f dsb sy configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 800ee12: e7fe b.n 800ee12 800ee14: 4770 bx lr pxLink->xBlockSize &= ~xBlockAllocatedBit; 800ee16: ea23 0302 bic.w r3, r3, r2 { 800ee1a: b530 push {r4, r5, lr} 800ee1c: b083 sub sp, #12 pxLink->xBlockSize &= ~xBlockAllocatedBit; 800ee1e: f840 3c04 str.w r3, [r0, #-4] puc -= xHeapStructSize; 800ee22: f1a0 0408 sub.w r4, r0, #8 pxLink->xBlockSize &= ~xBlockAllocatedBit; 800ee26: 9001 str r0, [sp, #4] vTaskSuspendAll(); 800ee28: f7fe fdb4 bl 800d994 xFreeBytesRemaining += pxLink->xBlockSize; 800ee2c: 4a1a ldr r2, [pc, #104] @ (800ee98 ) 800ee2e: 9801 ldr r0, [sp, #4] 800ee30: 6813 ldr r3, [r2, #0] 800ee32: f850 1c04 ldr.w r1, [r0, #-4] 800ee36: 440b add r3, r1 800ee38: 6013 str r3, [r2, #0] for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 800ee3a: 4b18 ldr r3, [pc, #96] @ (800ee9c ) 800ee3c: 461a mov r2, r3 800ee3e: 681b ldr r3, [r3, #0] 800ee40: 429c cmp r4, r3 800ee42: d8fb bhi.n 800ee3c if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 800ee44: 6855 ldr r5, [r2, #4] 800ee46: eb02 0e05 add.w lr, r2, r5 800ee4a: 4574 cmp r4, lr 800ee4c: d011 beq.n 800ee72 if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 800ee4e: eb04 0c01 add.w ip, r4, r1 800ee52: 4563 cmp r3, ip 800ee54: d013 beq.n 800ee7e pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 800ee56: f840 3c08 str.w r3, [r0, #-8] if( pxIterator != pxBlockToInsert ) 800ee5a: 42a2 cmp r2, r4 pxIterator->pxNextFreeBlock = pxBlockToInsert; 800ee5c: bf18 it ne 800ee5e: 6014 strne r4, [r2, #0] xNumberOfSuccessfulFrees++; 800ee60: 4a0f ldr r2, [pc, #60] @ (800eea0 ) 800ee62: 6813 ldr r3, [r2, #0] 800ee64: 3301 adds r3, #1 800ee66: 6013 str r3, [r2, #0] } 800ee68: b003 add sp, #12 800ee6a: e8bd 4030 ldmia.w sp!, {r4, r5, lr} ( void ) xTaskResumeAll(); 800ee6e: f7fe bd99 b.w 800d9a4 pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 800ee72: 4429 add r1, r5 if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 800ee74: 1850 adds r0, r2, r1 pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 800ee76: 6051 str r1, [r2, #4] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 800ee78: 4283 cmp r3, r0 800ee7a: d1f1 bne.n 800ee60 800ee7c: 4614 mov r4, r2 if( pxIterator->pxNextFreeBlock != pxEnd ) 800ee7e: 4809 ldr r0, [pc, #36] @ (800eea4 ) 800ee80: 6800 ldr r0, [r0, #0] 800ee82: 4283 cmp r3, r0 800ee84: d003 beq.n 800ee8e pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 800ee86: e9d3 0500 ldrd r0, r5, [r3] pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 800ee8a: 4429 add r1, r5 800ee8c: 6061 str r1, [r4, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 800ee8e: 6020 str r0, [r4, #0] 800ee90: e7e3 b.n 800ee5a 800ee92: bf00 nop 800ee94: 24003178 .word 0x24003178 800ee98: 24003188 .word 0x24003188 800ee9c: 24003190 .word 0x24003190 800eea0: 2400317c .word 0x2400317c 800eea4: 2400318c .word 0x2400318c 0800eea8 <__cvt>: 800eea8: b5f0 push {r4, r5, r6, r7, lr} 800eeaa: ed2d 8b02 vpush {d8} 800eeae: eeb0 8b40 vmov.f64 d8, d0 800eeb2: b085 sub sp, #20 800eeb4: 4617 mov r7, r2 800eeb6: 9d0d ldr r5, [sp, #52] @ 0x34 800eeb8: 9e0c ldr r6, [sp, #48] @ 0x30 800eeba: ee18 2a90 vmov r2, s17 800eebe: f025 0520 bic.w r5, r5, #32 800eec2: 2a00 cmp r2, #0 800eec4: bfb6 itet lt 800eec6: 222d movlt r2, #45 @ 0x2d 800eec8: 2200 movge r2, #0 800eeca: eeb1 8b40 vneglt.f64 d8, d0 800eece: 2d46 cmp r5, #70 @ 0x46 800eed0: 460c mov r4, r1 800eed2: 701a strb r2, [r3, #0] 800eed4: d004 beq.n 800eee0 <__cvt+0x38> 800eed6: 2d45 cmp r5, #69 @ 0x45 800eed8: d100 bne.n 800eedc <__cvt+0x34> 800eeda: 3401 adds r4, #1 800eedc: 2102 movs r1, #2 800eede: e000 b.n 800eee2 <__cvt+0x3a> 800eee0: 2103 movs r1, #3 800eee2: ab03 add r3, sp, #12 800eee4: 9301 str r3, [sp, #4] 800eee6: ab02 add r3, sp, #8 800eee8: 9300 str r3, [sp, #0] 800eeea: 4622 mov r2, r4 800eeec: 4633 mov r3, r6 800eeee: eeb0 0b48 vmov.f64 d0, d8 800eef2: f000 ff75 bl 800fde0 <_dtoa_r> 800eef6: 2d47 cmp r5, #71 @ 0x47 800eef8: d114 bne.n 800ef24 <__cvt+0x7c> 800eefa: 07fb lsls r3, r7, #31 800eefc: d50a bpl.n 800ef14 <__cvt+0x6c> 800eefe: 1902 adds r2, r0, r4 800ef00: eeb5 8b40 vcmp.f64 d8, #0.0 800ef04: eef1 fa10 vmrs APSR_nzcv, fpscr 800ef08: bf08 it eq 800ef0a: 9203 streq r2, [sp, #12] 800ef0c: 2130 movs r1, #48 @ 0x30 800ef0e: 9b03 ldr r3, [sp, #12] 800ef10: 4293 cmp r3, r2 800ef12: d319 bcc.n 800ef48 <__cvt+0xa0> 800ef14: 9b03 ldr r3, [sp, #12] 800ef16: 9a0e ldr r2, [sp, #56] @ 0x38 800ef18: 1a1b subs r3, r3, r0 800ef1a: 6013 str r3, [r2, #0] 800ef1c: b005 add sp, #20 800ef1e: ecbd 8b02 vpop {d8} 800ef22: bdf0 pop {r4, r5, r6, r7, pc} 800ef24: 2d46 cmp r5, #70 @ 0x46 800ef26: eb00 0204 add.w r2, r0, r4 800ef2a: d1e9 bne.n 800ef00 <__cvt+0x58> 800ef2c: 7803 ldrb r3, [r0, #0] 800ef2e: 2b30 cmp r3, #48 @ 0x30 800ef30: d107 bne.n 800ef42 <__cvt+0x9a> 800ef32: eeb5 8b40 vcmp.f64 d8, #0.0 800ef36: eef1 fa10 vmrs APSR_nzcv, fpscr 800ef3a: bf1c itt ne 800ef3c: f1c4 0401 rsbne r4, r4, #1 800ef40: 6034 strne r4, [r6, #0] 800ef42: 6833 ldr r3, [r6, #0] 800ef44: 441a add r2, r3 800ef46: e7db b.n 800ef00 <__cvt+0x58> 800ef48: 1c5c adds r4, r3, #1 800ef4a: 9403 str r4, [sp, #12] 800ef4c: 7019 strb r1, [r3, #0] 800ef4e: e7de b.n 800ef0e <__cvt+0x66> 0800ef50 <__exponent>: 800ef50: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 800ef52: 2900 cmp r1, #0 800ef54: bfba itte lt 800ef56: 4249 neglt r1, r1 800ef58: 232d movlt r3, #45 @ 0x2d 800ef5a: 232b movge r3, #43 @ 0x2b 800ef5c: 2909 cmp r1, #9 800ef5e: 7002 strb r2, [r0, #0] 800ef60: 7043 strb r3, [r0, #1] 800ef62: dd29 ble.n 800efb8 <__exponent+0x68> 800ef64: f10d 0307 add.w r3, sp, #7 800ef68: 461d mov r5, r3 800ef6a: 270a movs r7, #10 800ef6c: 461a mov r2, r3 800ef6e: fbb1 f6f7 udiv r6, r1, r7 800ef72: fb07 1416 mls r4, r7, r6, r1 800ef76: 3430 adds r4, #48 @ 0x30 800ef78: f802 4c01 strb.w r4, [r2, #-1] 800ef7c: 460c mov r4, r1 800ef7e: 2c63 cmp r4, #99 @ 0x63 800ef80: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff 800ef84: 4631 mov r1, r6 800ef86: dcf1 bgt.n 800ef6c <__exponent+0x1c> 800ef88: 3130 adds r1, #48 @ 0x30 800ef8a: 1e94 subs r4, r2, #2 800ef8c: f803 1c01 strb.w r1, [r3, #-1] 800ef90: 1c41 adds r1, r0, #1 800ef92: 4623 mov r3, r4 800ef94: 42ab cmp r3, r5 800ef96: d30a bcc.n 800efae <__exponent+0x5e> 800ef98: f10d 0309 add.w r3, sp, #9 800ef9c: 1a9b subs r3, r3, r2 800ef9e: 42ac cmp r4, r5 800efa0: bf88 it hi 800efa2: 2300 movhi r3, #0 800efa4: 3302 adds r3, #2 800efa6: 4403 add r3, r0 800efa8: 1a18 subs r0, r3, r0 800efaa: b003 add sp, #12 800efac: bdf0 pop {r4, r5, r6, r7, pc} 800efae: f813 6b01 ldrb.w r6, [r3], #1 800efb2: f801 6f01 strb.w r6, [r1, #1]! 800efb6: e7ed b.n 800ef94 <__exponent+0x44> 800efb8: 2330 movs r3, #48 @ 0x30 800efba: 3130 adds r1, #48 @ 0x30 800efbc: 7083 strb r3, [r0, #2] 800efbe: 70c1 strb r1, [r0, #3] 800efc0: 1d03 adds r3, r0, #4 800efc2: e7f1 b.n 800efa8 <__exponent+0x58> 800efc4: 0000 movs r0, r0 ... 0800efc8 <_printf_float>: 800efc8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800efcc: b08d sub sp, #52 @ 0x34 800efce: 460c mov r4, r1 800efd0: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58 800efd4: 4616 mov r6, r2 800efd6: 461f mov r7, r3 800efd8: 4605 mov r5, r0 800efda: f000 fd9d bl 800fb18 <_localeconv_r> 800efde: f8d0 b000 ldr.w fp, [r0] 800efe2: 4658 mov r0, fp 800efe4: f7f1 f9cc bl 8000380 800efe8: 2300 movs r3, #0 800efea: 930a str r3, [sp, #40] @ 0x28 800efec: f8d8 3000 ldr.w r3, [r8] 800eff0: f894 9018 ldrb.w r9, [r4, #24] 800eff4: 6822 ldr r2, [r4, #0] 800eff6: 9005 str r0, [sp, #20] 800eff8: 3307 adds r3, #7 800effa: f023 0307 bic.w r3, r3, #7 800effe: f103 0108 add.w r1, r3, #8 800f002: f8c8 1000 str.w r1, [r8] 800f006: ed93 0b00 vldr d0, [r3] 800f00a: ed9f 6b97 vldr d6, [pc, #604] @ 800f268 <_printf_float+0x2a0> 800f00e: eeb0 7bc0 vabs.f64 d7, d0 800f012: eeb4 7b46 vcmp.f64 d7, d6 800f016: eef1 fa10 vmrs APSR_nzcv, fpscr 800f01a: ed84 0b12 vstr d0, [r4, #72] @ 0x48 800f01e: dd24 ble.n 800f06a <_printf_float+0xa2> 800f020: eeb5 0bc0 vcmpe.f64 d0, #0.0 800f024: eef1 fa10 vmrs APSR_nzcv, fpscr 800f028: d502 bpl.n 800f030 <_printf_float+0x68> 800f02a: 232d movs r3, #45 @ 0x2d 800f02c: f884 3043 strb.w r3, [r4, #67] @ 0x43 800f030: 498f ldr r1, [pc, #572] @ (800f270 <_printf_float+0x2a8>) 800f032: 4b90 ldr r3, [pc, #576] @ (800f274 <_printf_float+0x2ac>) 800f034: f1b9 0f47 cmp.w r9, #71 @ 0x47 800f038: bf94 ite ls 800f03a: 4688 movls r8, r1 800f03c: 4698 movhi r8, r3 800f03e: f022 0204 bic.w r2, r2, #4 800f042: 2303 movs r3, #3 800f044: 6123 str r3, [r4, #16] 800f046: 6022 str r2, [r4, #0] 800f048: f04f 0a00 mov.w sl, #0 800f04c: 9700 str r7, [sp, #0] 800f04e: 4633 mov r3, r6 800f050: aa0b add r2, sp, #44 @ 0x2c 800f052: 4621 mov r1, r4 800f054: 4628 mov r0, r5 800f056: f000 f9d1 bl 800f3fc <_printf_common> 800f05a: 3001 adds r0, #1 800f05c: f040 8089 bne.w 800f172 <_printf_float+0x1aa> 800f060: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800f064: b00d add sp, #52 @ 0x34 800f066: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800f06a: eeb4 0b40 vcmp.f64 d0, d0 800f06e: eef1 fa10 vmrs APSR_nzcv, fpscr 800f072: d709 bvc.n 800f088 <_printf_float+0xc0> 800f074: ee10 3a90 vmov r3, s1 800f078: 2b00 cmp r3, #0 800f07a: bfbc itt lt 800f07c: 232d movlt r3, #45 @ 0x2d 800f07e: f884 3043 strblt.w r3, [r4, #67] @ 0x43 800f082: 497d ldr r1, [pc, #500] @ (800f278 <_printf_float+0x2b0>) 800f084: 4b7d ldr r3, [pc, #500] @ (800f27c <_printf_float+0x2b4>) 800f086: e7d5 b.n 800f034 <_printf_float+0x6c> 800f088: 6863 ldr r3, [r4, #4] 800f08a: 1c59 adds r1, r3, #1 800f08c: f009 0adf and.w sl, r9, #223 @ 0xdf 800f090: d139 bne.n 800f106 <_printf_float+0x13e> 800f092: 2306 movs r3, #6 800f094: 6063 str r3, [r4, #4] 800f096: f442 6280 orr.w r2, r2, #1024 @ 0x400 800f09a: 2300 movs r3, #0 800f09c: 6022 str r2, [r4, #0] 800f09e: 9303 str r3, [sp, #12] 800f0a0: ab0a add r3, sp, #40 @ 0x28 800f0a2: e9cd 9301 strd r9, r3, [sp, #4] 800f0a6: ab09 add r3, sp, #36 @ 0x24 800f0a8: 9300 str r3, [sp, #0] 800f0aa: 6861 ldr r1, [r4, #4] 800f0ac: f10d 0323 add.w r3, sp, #35 @ 0x23 800f0b0: 4628 mov r0, r5 800f0b2: f7ff fef9 bl 800eea8 <__cvt> 800f0b6: f1ba 0f47 cmp.w sl, #71 @ 0x47 800f0ba: 9909 ldr r1, [sp, #36] @ 0x24 800f0bc: 4680 mov r8, r0 800f0be: d129 bne.n 800f114 <_printf_float+0x14c> 800f0c0: 1cc8 adds r0, r1, #3 800f0c2: db02 blt.n 800f0ca <_printf_float+0x102> 800f0c4: 6863 ldr r3, [r4, #4] 800f0c6: 4299 cmp r1, r3 800f0c8: dd41 ble.n 800f14e <_printf_float+0x186> 800f0ca: f1a9 0902 sub.w r9, r9, #2 800f0ce: fa5f f989 uxtb.w r9, r9 800f0d2: 3901 subs r1, #1 800f0d4: 464a mov r2, r9 800f0d6: f104 0050 add.w r0, r4, #80 @ 0x50 800f0da: 9109 str r1, [sp, #36] @ 0x24 800f0dc: f7ff ff38 bl 800ef50 <__exponent> 800f0e0: 9a0a ldr r2, [sp, #40] @ 0x28 800f0e2: 1813 adds r3, r2, r0 800f0e4: 2a01 cmp r2, #1 800f0e6: 4682 mov sl, r0 800f0e8: 6123 str r3, [r4, #16] 800f0ea: dc02 bgt.n 800f0f2 <_printf_float+0x12a> 800f0ec: 6822 ldr r2, [r4, #0] 800f0ee: 07d2 lsls r2, r2, #31 800f0f0: d501 bpl.n 800f0f6 <_printf_float+0x12e> 800f0f2: 3301 adds r3, #1 800f0f4: 6123 str r3, [r4, #16] 800f0f6: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23 800f0fa: 2b00 cmp r3, #0 800f0fc: d0a6 beq.n 800f04c <_printf_float+0x84> 800f0fe: 232d movs r3, #45 @ 0x2d 800f100: f884 3043 strb.w r3, [r4, #67] @ 0x43 800f104: e7a2 b.n 800f04c <_printf_float+0x84> 800f106: f1ba 0f47 cmp.w sl, #71 @ 0x47 800f10a: d1c4 bne.n 800f096 <_printf_float+0xce> 800f10c: 2b00 cmp r3, #0 800f10e: d1c2 bne.n 800f096 <_printf_float+0xce> 800f110: 2301 movs r3, #1 800f112: e7bf b.n 800f094 <_printf_float+0xcc> 800f114: f1b9 0f65 cmp.w r9, #101 @ 0x65 800f118: d9db bls.n 800f0d2 <_printf_float+0x10a> 800f11a: f1b9 0f66 cmp.w r9, #102 @ 0x66 800f11e: d118 bne.n 800f152 <_printf_float+0x18a> 800f120: 2900 cmp r1, #0 800f122: 6863 ldr r3, [r4, #4] 800f124: dd0b ble.n 800f13e <_printf_float+0x176> 800f126: 6121 str r1, [r4, #16] 800f128: b913 cbnz r3, 800f130 <_printf_float+0x168> 800f12a: 6822 ldr r2, [r4, #0] 800f12c: 07d0 lsls r0, r2, #31 800f12e: d502 bpl.n 800f136 <_printf_float+0x16e> 800f130: 3301 adds r3, #1 800f132: 440b add r3, r1 800f134: 6123 str r3, [r4, #16] 800f136: 65a1 str r1, [r4, #88] @ 0x58 800f138: f04f 0a00 mov.w sl, #0 800f13c: e7db b.n 800f0f6 <_printf_float+0x12e> 800f13e: b913 cbnz r3, 800f146 <_printf_float+0x17e> 800f140: 6822 ldr r2, [r4, #0] 800f142: 07d2 lsls r2, r2, #31 800f144: d501 bpl.n 800f14a <_printf_float+0x182> 800f146: 3302 adds r3, #2 800f148: e7f4 b.n 800f134 <_printf_float+0x16c> 800f14a: 2301 movs r3, #1 800f14c: e7f2 b.n 800f134 <_printf_float+0x16c> 800f14e: f04f 0967 mov.w r9, #103 @ 0x67 800f152: 9b0a ldr r3, [sp, #40] @ 0x28 800f154: 4299 cmp r1, r3 800f156: db05 blt.n 800f164 <_printf_float+0x19c> 800f158: 6823 ldr r3, [r4, #0] 800f15a: 6121 str r1, [r4, #16] 800f15c: 07d8 lsls r0, r3, #31 800f15e: d5ea bpl.n 800f136 <_printf_float+0x16e> 800f160: 1c4b adds r3, r1, #1 800f162: e7e7 b.n 800f134 <_printf_float+0x16c> 800f164: 2900 cmp r1, #0 800f166: bfd4 ite le 800f168: f1c1 0202 rsble r2, r1, #2 800f16c: 2201 movgt r2, #1 800f16e: 4413 add r3, r2 800f170: e7e0 b.n 800f134 <_printf_float+0x16c> 800f172: 6823 ldr r3, [r4, #0] 800f174: 055a lsls r2, r3, #21 800f176: d407 bmi.n 800f188 <_printf_float+0x1c0> 800f178: 6923 ldr r3, [r4, #16] 800f17a: 4642 mov r2, r8 800f17c: 4631 mov r1, r6 800f17e: 4628 mov r0, r5 800f180: 47b8 blx r7 800f182: 3001 adds r0, #1 800f184: d12a bne.n 800f1dc <_printf_float+0x214> 800f186: e76b b.n 800f060 <_printf_float+0x98> 800f188: f1b9 0f65 cmp.w r9, #101 @ 0x65 800f18c: f240 80e0 bls.w 800f350 <_printf_float+0x388> 800f190: ed94 7b12 vldr d7, [r4, #72] @ 0x48 800f194: eeb5 7b40 vcmp.f64 d7, #0.0 800f198: eef1 fa10 vmrs APSR_nzcv, fpscr 800f19c: d133 bne.n 800f206 <_printf_float+0x23e> 800f19e: 4a38 ldr r2, [pc, #224] @ (800f280 <_printf_float+0x2b8>) 800f1a0: 2301 movs r3, #1 800f1a2: 4631 mov r1, r6 800f1a4: 4628 mov r0, r5 800f1a6: 47b8 blx r7 800f1a8: 3001 adds r0, #1 800f1aa: f43f af59 beq.w 800f060 <_printf_float+0x98> 800f1ae: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24 800f1b2: 4543 cmp r3, r8 800f1b4: db02 blt.n 800f1bc <_printf_float+0x1f4> 800f1b6: 6823 ldr r3, [r4, #0] 800f1b8: 07d8 lsls r0, r3, #31 800f1ba: d50f bpl.n 800f1dc <_printf_float+0x214> 800f1bc: 9b05 ldr r3, [sp, #20] 800f1be: 465a mov r2, fp 800f1c0: 4631 mov r1, r6 800f1c2: 4628 mov r0, r5 800f1c4: 47b8 blx r7 800f1c6: 3001 adds r0, #1 800f1c8: f43f af4a beq.w 800f060 <_printf_float+0x98> 800f1cc: f04f 0900 mov.w r9, #0 800f1d0: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 800f1d4: f104 0a1a add.w sl, r4, #26 800f1d8: 45c8 cmp r8, r9 800f1da: dc09 bgt.n 800f1f0 <_printf_float+0x228> 800f1dc: 6823 ldr r3, [r4, #0] 800f1de: 079b lsls r3, r3, #30 800f1e0: f100 8107 bmi.w 800f3f2 <_printf_float+0x42a> 800f1e4: 68e0 ldr r0, [r4, #12] 800f1e6: 9b0b ldr r3, [sp, #44] @ 0x2c 800f1e8: 4298 cmp r0, r3 800f1ea: bfb8 it lt 800f1ec: 4618 movlt r0, r3 800f1ee: e739 b.n 800f064 <_printf_float+0x9c> 800f1f0: 2301 movs r3, #1 800f1f2: 4652 mov r2, sl 800f1f4: 4631 mov r1, r6 800f1f6: 4628 mov r0, r5 800f1f8: 47b8 blx r7 800f1fa: 3001 adds r0, #1 800f1fc: f43f af30 beq.w 800f060 <_printf_float+0x98> 800f200: f109 0901 add.w r9, r9, #1 800f204: e7e8 b.n 800f1d8 <_printf_float+0x210> 800f206: 9b09 ldr r3, [sp, #36] @ 0x24 800f208: 2b00 cmp r3, #0 800f20a: dc3b bgt.n 800f284 <_printf_float+0x2bc> 800f20c: 4a1c ldr r2, [pc, #112] @ (800f280 <_printf_float+0x2b8>) 800f20e: 2301 movs r3, #1 800f210: 4631 mov r1, r6 800f212: 4628 mov r0, r5 800f214: 47b8 blx r7 800f216: 3001 adds r0, #1 800f218: f43f af22 beq.w 800f060 <_printf_float+0x98> 800f21c: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24 800f220: ea59 0303 orrs.w r3, r9, r3 800f224: d102 bne.n 800f22c <_printf_float+0x264> 800f226: 6823 ldr r3, [r4, #0] 800f228: 07d9 lsls r1, r3, #31 800f22a: d5d7 bpl.n 800f1dc <_printf_float+0x214> 800f22c: 9b05 ldr r3, [sp, #20] 800f22e: 465a mov r2, fp 800f230: 4631 mov r1, r6 800f232: 4628 mov r0, r5 800f234: 47b8 blx r7 800f236: 3001 adds r0, #1 800f238: f43f af12 beq.w 800f060 <_printf_float+0x98> 800f23c: f04f 0a00 mov.w sl, #0 800f240: f104 0b1a add.w fp, r4, #26 800f244: 9b09 ldr r3, [sp, #36] @ 0x24 800f246: 425b negs r3, r3 800f248: 4553 cmp r3, sl 800f24a: dc01 bgt.n 800f250 <_printf_float+0x288> 800f24c: 464b mov r3, r9 800f24e: e794 b.n 800f17a <_printf_float+0x1b2> 800f250: 2301 movs r3, #1 800f252: 465a mov r2, fp 800f254: 4631 mov r1, r6 800f256: 4628 mov r0, r5 800f258: 47b8 blx r7 800f25a: 3001 adds r0, #1 800f25c: f43f af00 beq.w 800f060 <_printf_float+0x98> 800f260: f10a 0a01 add.w sl, sl, #1 800f264: e7ee b.n 800f244 <_printf_float+0x27c> 800f266: bf00 nop 800f268: ffffffff .word 0xffffffff 800f26c: 7fefffff .word 0x7fefffff 800f270: 08011a6c .word 0x08011a6c 800f274: 08011a70 .word 0x08011a70 800f278: 08011a74 .word 0x08011a74 800f27c: 08011a78 .word 0x08011a78 800f280: 08011a7c .word 0x08011a7c 800f284: 6da3 ldr r3, [r4, #88] @ 0x58 800f286: f8dd a028 ldr.w sl, [sp, #40] @ 0x28 800f28a: 4553 cmp r3, sl 800f28c: bfa8 it ge 800f28e: 4653 movge r3, sl 800f290: 2b00 cmp r3, #0 800f292: 4699 mov r9, r3 800f294: dc37 bgt.n 800f306 <_printf_float+0x33e> 800f296: 2300 movs r3, #0 800f298: 9307 str r3, [sp, #28] 800f29a: ea29 79e9 bic.w r9, r9, r9, asr #31 800f29e: f104 021a add.w r2, r4, #26 800f2a2: 6da3 ldr r3, [r4, #88] @ 0x58 800f2a4: 9907 ldr r1, [sp, #28] 800f2a6: 9306 str r3, [sp, #24] 800f2a8: eba3 0309 sub.w r3, r3, r9 800f2ac: 428b cmp r3, r1 800f2ae: dc31 bgt.n 800f314 <_printf_float+0x34c> 800f2b0: 9b09 ldr r3, [sp, #36] @ 0x24 800f2b2: 459a cmp sl, r3 800f2b4: dc3b bgt.n 800f32e <_printf_float+0x366> 800f2b6: 6823 ldr r3, [r4, #0] 800f2b8: 07da lsls r2, r3, #31 800f2ba: d438 bmi.n 800f32e <_printf_float+0x366> 800f2bc: 9b09 ldr r3, [sp, #36] @ 0x24 800f2be: ebaa 0903 sub.w r9, sl, r3 800f2c2: 9b06 ldr r3, [sp, #24] 800f2c4: ebaa 0303 sub.w r3, sl, r3 800f2c8: 4599 cmp r9, r3 800f2ca: bfa8 it ge 800f2cc: 4699 movge r9, r3 800f2ce: f1b9 0f00 cmp.w r9, #0 800f2d2: dc34 bgt.n 800f33e <_printf_float+0x376> 800f2d4: f04f 0800 mov.w r8, #0 800f2d8: ea29 79e9 bic.w r9, r9, r9, asr #31 800f2dc: f104 0b1a add.w fp, r4, #26 800f2e0: 9b09 ldr r3, [sp, #36] @ 0x24 800f2e2: ebaa 0303 sub.w r3, sl, r3 800f2e6: eba3 0309 sub.w r3, r3, r9 800f2ea: 4543 cmp r3, r8 800f2ec: f77f af76 ble.w 800f1dc <_printf_float+0x214> 800f2f0: 2301 movs r3, #1 800f2f2: 465a mov r2, fp 800f2f4: 4631 mov r1, r6 800f2f6: 4628 mov r0, r5 800f2f8: 47b8 blx r7 800f2fa: 3001 adds r0, #1 800f2fc: f43f aeb0 beq.w 800f060 <_printf_float+0x98> 800f300: f108 0801 add.w r8, r8, #1 800f304: e7ec b.n 800f2e0 <_printf_float+0x318> 800f306: 4642 mov r2, r8 800f308: 4631 mov r1, r6 800f30a: 4628 mov r0, r5 800f30c: 47b8 blx r7 800f30e: 3001 adds r0, #1 800f310: d1c1 bne.n 800f296 <_printf_float+0x2ce> 800f312: e6a5 b.n 800f060 <_printf_float+0x98> 800f314: 2301 movs r3, #1 800f316: 4631 mov r1, r6 800f318: 4628 mov r0, r5 800f31a: 9206 str r2, [sp, #24] 800f31c: 47b8 blx r7 800f31e: 3001 adds r0, #1 800f320: f43f ae9e beq.w 800f060 <_printf_float+0x98> 800f324: 9b07 ldr r3, [sp, #28] 800f326: 9a06 ldr r2, [sp, #24] 800f328: 3301 adds r3, #1 800f32a: 9307 str r3, [sp, #28] 800f32c: e7b9 b.n 800f2a2 <_printf_float+0x2da> 800f32e: 9b05 ldr r3, [sp, #20] 800f330: 465a mov r2, fp 800f332: 4631 mov r1, r6 800f334: 4628 mov r0, r5 800f336: 47b8 blx r7 800f338: 3001 adds r0, #1 800f33a: d1bf bne.n 800f2bc <_printf_float+0x2f4> 800f33c: e690 b.n 800f060 <_printf_float+0x98> 800f33e: 9a06 ldr r2, [sp, #24] 800f340: 464b mov r3, r9 800f342: 4442 add r2, r8 800f344: 4631 mov r1, r6 800f346: 4628 mov r0, r5 800f348: 47b8 blx r7 800f34a: 3001 adds r0, #1 800f34c: d1c2 bne.n 800f2d4 <_printf_float+0x30c> 800f34e: e687 b.n 800f060 <_printf_float+0x98> 800f350: f8dd 9028 ldr.w r9, [sp, #40] @ 0x28 800f354: f1b9 0f01 cmp.w r9, #1 800f358: dc01 bgt.n 800f35e <_printf_float+0x396> 800f35a: 07db lsls r3, r3, #31 800f35c: d536 bpl.n 800f3cc <_printf_float+0x404> 800f35e: 2301 movs r3, #1 800f360: 4642 mov r2, r8 800f362: 4631 mov r1, r6 800f364: 4628 mov r0, r5 800f366: 47b8 blx r7 800f368: 3001 adds r0, #1 800f36a: f43f ae79 beq.w 800f060 <_printf_float+0x98> 800f36e: 9b05 ldr r3, [sp, #20] 800f370: 465a mov r2, fp 800f372: 4631 mov r1, r6 800f374: 4628 mov r0, r5 800f376: 47b8 blx r7 800f378: 3001 adds r0, #1 800f37a: f43f ae71 beq.w 800f060 <_printf_float+0x98> 800f37e: ed94 7b12 vldr d7, [r4, #72] @ 0x48 800f382: eeb5 7b40 vcmp.f64 d7, #0.0 800f386: eef1 fa10 vmrs APSR_nzcv, fpscr 800f38a: f109 39ff add.w r9, r9, #4294967295 @ 0xffffffff 800f38e: d018 beq.n 800f3c2 <_printf_float+0x3fa> 800f390: 464b mov r3, r9 800f392: f108 0201 add.w r2, r8, #1 800f396: 4631 mov r1, r6 800f398: 4628 mov r0, r5 800f39a: 47b8 blx r7 800f39c: 3001 adds r0, #1 800f39e: d10c bne.n 800f3ba <_printf_float+0x3f2> 800f3a0: e65e b.n 800f060 <_printf_float+0x98> 800f3a2: 2301 movs r3, #1 800f3a4: 465a mov r2, fp 800f3a6: 4631 mov r1, r6 800f3a8: 4628 mov r0, r5 800f3aa: 47b8 blx r7 800f3ac: 3001 adds r0, #1 800f3ae: f43f ae57 beq.w 800f060 <_printf_float+0x98> 800f3b2: f108 0801 add.w r8, r8, #1 800f3b6: 45c8 cmp r8, r9 800f3b8: dbf3 blt.n 800f3a2 <_printf_float+0x3da> 800f3ba: 4653 mov r3, sl 800f3bc: f104 0250 add.w r2, r4, #80 @ 0x50 800f3c0: e6dc b.n 800f17c <_printf_float+0x1b4> 800f3c2: f04f 0800 mov.w r8, #0 800f3c6: f104 0b1a add.w fp, r4, #26 800f3ca: e7f4 b.n 800f3b6 <_printf_float+0x3ee> 800f3cc: 2301 movs r3, #1 800f3ce: 4642 mov r2, r8 800f3d0: e7e1 b.n 800f396 <_printf_float+0x3ce> 800f3d2: 2301 movs r3, #1 800f3d4: 464a mov r2, r9 800f3d6: 4631 mov r1, r6 800f3d8: 4628 mov r0, r5 800f3da: 47b8 blx r7 800f3dc: 3001 adds r0, #1 800f3de: f43f ae3f beq.w 800f060 <_printf_float+0x98> 800f3e2: f108 0801 add.w r8, r8, #1 800f3e6: 68e3 ldr r3, [r4, #12] 800f3e8: 990b ldr r1, [sp, #44] @ 0x2c 800f3ea: 1a5b subs r3, r3, r1 800f3ec: 4543 cmp r3, r8 800f3ee: dcf0 bgt.n 800f3d2 <_printf_float+0x40a> 800f3f0: e6f8 b.n 800f1e4 <_printf_float+0x21c> 800f3f2: f04f 0800 mov.w r8, #0 800f3f6: f104 0919 add.w r9, r4, #25 800f3fa: e7f4 b.n 800f3e6 <_printf_float+0x41e> 0800f3fc <_printf_common>: 800f3fc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800f400: 4616 mov r6, r2 800f402: 4698 mov r8, r3 800f404: 688a ldr r2, [r1, #8] 800f406: 690b ldr r3, [r1, #16] 800f408: f8dd 9020 ldr.w r9, [sp, #32] 800f40c: 4293 cmp r3, r2 800f40e: bfb8 it lt 800f410: 4613 movlt r3, r2 800f412: 6033 str r3, [r6, #0] 800f414: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 800f418: 4607 mov r7, r0 800f41a: 460c mov r4, r1 800f41c: b10a cbz r2, 800f422 <_printf_common+0x26> 800f41e: 3301 adds r3, #1 800f420: 6033 str r3, [r6, #0] 800f422: 6823 ldr r3, [r4, #0] 800f424: 0699 lsls r1, r3, #26 800f426: bf42 ittt mi 800f428: 6833 ldrmi r3, [r6, #0] 800f42a: 3302 addmi r3, #2 800f42c: 6033 strmi r3, [r6, #0] 800f42e: 6825 ldr r5, [r4, #0] 800f430: f015 0506 ands.w r5, r5, #6 800f434: d106 bne.n 800f444 <_printf_common+0x48> 800f436: f104 0a19 add.w sl, r4, #25 800f43a: 68e3 ldr r3, [r4, #12] 800f43c: 6832 ldr r2, [r6, #0] 800f43e: 1a9b subs r3, r3, r2 800f440: 42ab cmp r3, r5 800f442: dc26 bgt.n 800f492 <_printf_common+0x96> 800f444: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 800f448: 6822 ldr r2, [r4, #0] 800f44a: 3b00 subs r3, #0 800f44c: bf18 it ne 800f44e: 2301 movne r3, #1 800f450: 0692 lsls r2, r2, #26 800f452: d42b bmi.n 800f4ac <_printf_common+0xb0> 800f454: f104 0243 add.w r2, r4, #67 @ 0x43 800f458: 4641 mov r1, r8 800f45a: 4638 mov r0, r7 800f45c: 47c8 blx r9 800f45e: 3001 adds r0, #1 800f460: d01e beq.n 800f4a0 <_printf_common+0xa4> 800f462: 6823 ldr r3, [r4, #0] 800f464: 6922 ldr r2, [r4, #16] 800f466: f003 0306 and.w r3, r3, #6 800f46a: 2b04 cmp r3, #4 800f46c: bf02 ittt eq 800f46e: 68e5 ldreq r5, [r4, #12] 800f470: 6833 ldreq r3, [r6, #0] 800f472: 1aed subeq r5, r5, r3 800f474: 68a3 ldr r3, [r4, #8] 800f476: bf0c ite eq 800f478: ea25 75e5 biceq.w r5, r5, r5, asr #31 800f47c: 2500 movne r5, #0 800f47e: 4293 cmp r3, r2 800f480: bfc4 itt gt 800f482: 1a9b subgt r3, r3, r2 800f484: 18ed addgt r5, r5, r3 800f486: 2600 movs r6, #0 800f488: 341a adds r4, #26 800f48a: 42b5 cmp r5, r6 800f48c: d11a bne.n 800f4c4 <_printf_common+0xc8> 800f48e: 2000 movs r0, #0 800f490: e008 b.n 800f4a4 <_printf_common+0xa8> 800f492: 2301 movs r3, #1 800f494: 4652 mov r2, sl 800f496: 4641 mov r1, r8 800f498: 4638 mov r0, r7 800f49a: 47c8 blx r9 800f49c: 3001 adds r0, #1 800f49e: d103 bne.n 800f4a8 <_printf_common+0xac> 800f4a0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800f4a4: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800f4a8: 3501 adds r5, #1 800f4aa: e7c6 b.n 800f43a <_printf_common+0x3e> 800f4ac: 18e1 adds r1, r4, r3 800f4ae: 1c5a adds r2, r3, #1 800f4b0: 2030 movs r0, #48 @ 0x30 800f4b2: f881 0043 strb.w r0, [r1, #67] @ 0x43 800f4b6: 4422 add r2, r4 800f4b8: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 800f4bc: f882 1043 strb.w r1, [r2, #67] @ 0x43 800f4c0: 3302 adds r3, #2 800f4c2: e7c7 b.n 800f454 <_printf_common+0x58> 800f4c4: 2301 movs r3, #1 800f4c6: 4622 mov r2, r4 800f4c8: 4641 mov r1, r8 800f4ca: 4638 mov r0, r7 800f4cc: 47c8 blx r9 800f4ce: 3001 adds r0, #1 800f4d0: d0e6 beq.n 800f4a0 <_printf_common+0xa4> 800f4d2: 3601 adds r6, #1 800f4d4: e7d9 b.n 800f48a <_printf_common+0x8e> ... 0800f4d8 <_printf_i>: 800f4d8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 800f4dc: 7e0f ldrb r7, [r1, #24] 800f4de: 9e0c ldr r6, [sp, #48] @ 0x30 800f4e0: 2f78 cmp r7, #120 @ 0x78 800f4e2: 4691 mov r9, r2 800f4e4: 4680 mov r8, r0 800f4e6: 460c mov r4, r1 800f4e8: 469a mov sl, r3 800f4ea: f101 0243 add.w r2, r1, #67 @ 0x43 800f4ee: d807 bhi.n 800f500 <_printf_i+0x28> 800f4f0: 2f62 cmp r7, #98 @ 0x62 800f4f2: d80a bhi.n 800f50a <_printf_i+0x32> 800f4f4: 2f00 cmp r7, #0 800f4f6: f000 80d2 beq.w 800f69e <_printf_i+0x1c6> 800f4fa: 2f58 cmp r7, #88 @ 0x58 800f4fc: f000 80b9 beq.w 800f672 <_printf_i+0x19a> 800f500: f104 0642 add.w r6, r4, #66 @ 0x42 800f504: f884 7042 strb.w r7, [r4, #66] @ 0x42 800f508: e03a b.n 800f580 <_printf_i+0xa8> 800f50a: f1a7 0363 sub.w r3, r7, #99 @ 0x63 800f50e: 2b15 cmp r3, #21 800f510: d8f6 bhi.n 800f500 <_printf_i+0x28> 800f512: a101 add r1, pc, #4 @ (adr r1, 800f518 <_printf_i+0x40>) 800f514: f851 f023 ldr.w pc, [r1, r3, lsl #2] 800f518: 0800f571 .word 0x0800f571 800f51c: 0800f585 .word 0x0800f585 800f520: 0800f501 .word 0x0800f501 800f524: 0800f501 .word 0x0800f501 800f528: 0800f501 .word 0x0800f501 800f52c: 0800f501 .word 0x0800f501 800f530: 0800f585 .word 0x0800f585 800f534: 0800f501 .word 0x0800f501 800f538: 0800f501 .word 0x0800f501 800f53c: 0800f501 .word 0x0800f501 800f540: 0800f501 .word 0x0800f501 800f544: 0800f685 .word 0x0800f685 800f548: 0800f5af .word 0x0800f5af 800f54c: 0800f63f .word 0x0800f63f 800f550: 0800f501 .word 0x0800f501 800f554: 0800f501 .word 0x0800f501 800f558: 0800f6a7 .word 0x0800f6a7 800f55c: 0800f501 .word 0x0800f501 800f560: 0800f5af .word 0x0800f5af 800f564: 0800f501 .word 0x0800f501 800f568: 0800f501 .word 0x0800f501 800f56c: 0800f647 .word 0x0800f647 800f570: 6833 ldr r3, [r6, #0] 800f572: 1d1a adds r2, r3, #4 800f574: 681b ldr r3, [r3, #0] 800f576: 6032 str r2, [r6, #0] 800f578: f104 0642 add.w r6, r4, #66 @ 0x42 800f57c: f884 3042 strb.w r3, [r4, #66] @ 0x42 800f580: 2301 movs r3, #1 800f582: e09d b.n 800f6c0 <_printf_i+0x1e8> 800f584: 6833 ldr r3, [r6, #0] 800f586: 6820 ldr r0, [r4, #0] 800f588: 1d19 adds r1, r3, #4 800f58a: 6031 str r1, [r6, #0] 800f58c: 0606 lsls r6, r0, #24 800f58e: d501 bpl.n 800f594 <_printf_i+0xbc> 800f590: 681d ldr r5, [r3, #0] 800f592: e003 b.n 800f59c <_printf_i+0xc4> 800f594: 0645 lsls r5, r0, #25 800f596: d5fb bpl.n 800f590 <_printf_i+0xb8> 800f598: f9b3 5000 ldrsh.w r5, [r3] 800f59c: 2d00 cmp r5, #0 800f59e: da03 bge.n 800f5a8 <_printf_i+0xd0> 800f5a0: 232d movs r3, #45 @ 0x2d 800f5a2: 426d negs r5, r5 800f5a4: f884 3043 strb.w r3, [r4, #67] @ 0x43 800f5a8: 4859 ldr r0, [pc, #356] @ (800f710 <_printf_i+0x238>) 800f5aa: 230a movs r3, #10 800f5ac: e011 b.n 800f5d2 <_printf_i+0xfa> 800f5ae: 6821 ldr r1, [r4, #0] 800f5b0: 6833 ldr r3, [r6, #0] 800f5b2: 0608 lsls r0, r1, #24 800f5b4: f853 5b04 ldr.w r5, [r3], #4 800f5b8: d402 bmi.n 800f5c0 <_printf_i+0xe8> 800f5ba: 0649 lsls r1, r1, #25 800f5bc: bf48 it mi 800f5be: b2ad uxthmi r5, r5 800f5c0: 2f6f cmp r7, #111 @ 0x6f 800f5c2: 4853 ldr r0, [pc, #332] @ (800f710 <_printf_i+0x238>) 800f5c4: 6033 str r3, [r6, #0] 800f5c6: bf14 ite ne 800f5c8: 230a movne r3, #10 800f5ca: 2308 moveq r3, #8 800f5cc: 2100 movs r1, #0 800f5ce: f884 1043 strb.w r1, [r4, #67] @ 0x43 800f5d2: 6866 ldr r6, [r4, #4] 800f5d4: 60a6 str r6, [r4, #8] 800f5d6: 2e00 cmp r6, #0 800f5d8: bfa2 ittt ge 800f5da: 6821 ldrge r1, [r4, #0] 800f5dc: f021 0104 bicge.w r1, r1, #4 800f5e0: 6021 strge r1, [r4, #0] 800f5e2: b90d cbnz r5, 800f5e8 <_printf_i+0x110> 800f5e4: 2e00 cmp r6, #0 800f5e6: d04b beq.n 800f680 <_printf_i+0x1a8> 800f5e8: 4616 mov r6, r2 800f5ea: fbb5 f1f3 udiv r1, r5, r3 800f5ee: fb03 5711 mls r7, r3, r1, r5 800f5f2: 5dc7 ldrb r7, [r0, r7] 800f5f4: f806 7d01 strb.w r7, [r6, #-1]! 800f5f8: 462f mov r7, r5 800f5fa: 42bb cmp r3, r7 800f5fc: 460d mov r5, r1 800f5fe: d9f4 bls.n 800f5ea <_printf_i+0x112> 800f600: 2b08 cmp r3, #8 800f602: d10b bne.n 800f61c <_printf_i+0x144> 800f604: 6823 ldr r3, [r4, #0] 800f606: 07df lsls r7, r3, #31 800f608: d508 bpl.n 800f61c <_printf_i+0x144> 800f60a: 6923 ldr r3, [r4, #16] 800f60c: 6861 ldr r1, [r4, #4] 800f60e: 4299 cmp r1, r3 800f610: bfde ittt le 800f612: 2330 movle r3, #48 @ 0x30 800f614: f806 3c01 strble.w r3, [r6, #-1] 800f618: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 800f61c: 1b92 subs r2, r2, r6 800f61e: 6122 str r2, [r4, #16] 800f620: f8cd a000 str.w sl, [sp] 800f624: 464b mov r3, r9 800f626: aa03 add r2, sp, #12 800f628: 4621 mov r1, r4 800f62a: 4640 mov r0, r8 800f62c: f7ff fee6 bl 800f3fc <_printf_common> 800f630: 3001 adds r0, #1 800f632: d14a bne.n 800f6ca <_printf_i+0x1f2> 800f634: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800f638: b004 add sp, #16 800f63a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800f63e: 6823 ldr r3, [r4, #0] 800f640: f043 0320 orr.w r3, r3, #32 800f644: 6023 str r3, [r4, #0] 800f646: 4833 ldr r0, [pc, #204] @ (800f714 <_printf_i+0x23c>) 800f648: 2778 movs r7, #120 @ 0x78 800f64a: f884 7045 strb.w r7, [r4, #69] @ 0x45 800f64e: 6823 ldr r3, [r4, #0] 800f650: 6831 ldr r1, [r6, #0] 800f652: 061f lsls r7, r3, #24 800f654: f851 5b04 ldr.w r5, [r1], #4 800f658: d402 bmi.n 800f660 <_printf_i+0x188> 800f65a: 065f lsls r7, r3, #25 800f65c: bf48 it mi 800f65e: b2ad uxthmi r5, r5 800f660: 6031 str r1, [r6, #0] 800f662: 07d9 lsls r1, r3, #31 800f664: bf44 itt mi 800f666: f043 0320 orrmi.w r3, r3, #32 800f66a: 6023 strmi r3, [r4, #0] 800f66c: b11d cbz r5, 800f676 <_printf_i+0x19e> 800f66e: 2310 movs r3, #16 800f670: e7ac b.n 800f5cc <_printf_i+0xf4> 800f672: 4827 ldr r0, [pc, #156] @ (800f710 <_printf_i+0x238>) 800f674: e7e9 b.n 800f64a <_printf_i+0x172> 800f676: 6823 ldr r3, [r4, #0] 800f678: f023 0320 bic.w r3, r3, #32 800f67c: 6023 str r3, [r4, #0] 800f67e: e7f6 b.n 800f66e <_printf_i+0x196> 800f680: 4616 mov r6, r2 800f682: e7bd b.n 800f600 <_printf_i+0x128> 800f684: 6833 ldr r3, [r6, #0] 800f686: 6825 ldr r5, [r4, #0] 800f688: 6961 ldr r1, [r4, #20] 800f68a: 1d18 adds r0, r3, #4 800f68c: 6030 str r0, [r6, #0] 800f68e: 062e lsls r6, r5, #24 800f690: 681b ldr r3, [r3, #0] 800f692: d501 bpl.n 800f698 <_printf_i+0x1c0> 800f694: 6019 str r1, [r3, #0] 800f696: e002 b.n 800f69e <_printf_i+0x1c6> 800f698: 0668 lsls r0, r5, #25 800f69a: d5fb bpl.n 800f694 <_printf_i+0x1bc> 800f69c: 8019 strh r1, [r3, #0] 800f69e: 2300 movs r3, #0 800f6a0: 6123 str r3, [r4, #16] 800f6a2: 4616 mov r6, r2 800f6a4: e7bc b.n 800f620 <_printf_i+0x148> 800f6a6: 6833 ldr r3, [r6, #0] 800f6a8: 1d1a adds r2, r3, #4 800f6aa: 6032 str r2, [r6, #0] 800f6ac: 681e ldr r6, [r3, #0] 800f6ae: 6862 ldr r2, [r4, #4] 800f6b0: 2100 movs r1, #0 800f6b2: 4630 mov r0, r6 800f6b4: f7f0 fe14 bl 80002e0 800f6b8: b108 cbz r0, 800f6be <_printf_i+0x1e6> 800f6ba: 1b80 subs r0, r0, r6 800f6bc: 6060 str r0, [r4, #4] 800f6be: 6863 ldr r3, [r4, #4] 800f6c0: 6123 str r3, [r4, #16] 800f6c2: 2300 movs r3, #0 800f6c4: f884 3043 strb.w r3, [r4, #67] @ 0x43 800f6c8: e7aa b.n 800f620 <_printf_i+0x148> 800f6ca: 6923 ldr r3, [r4, #16] 800f6cc: 4632 mov r2, r6 800f6ce: 4649 mov r1, r9 800f6d0: 4640 mov r0, r8 800f6d2: 47d0 blx sl 800f6d4: 3001 adds r0, #1 800f6d6: d0ad beq.n 800f634 <_printf_i+0x15c> 800f6d8: 6823 ldr r3, [r4, #0] 800f6da: 079b lsls r3, r3, #30 800f6dc: d413 bmi.n 800f706 <_printf_i+0x22e> 800f6de: 68e0 ldr r0, [r4, #12] 800f6e0: 9b03 ldr r3, [sp, #12] 800f6e2: 4298 cmp r0, r3 800f6e4: bfb8 it lt 800f6e6: 4618 movlt r0, r3 800f6e8: e7a6 b.n 800f638 <_printf_i+0x160> 800f6ea: 2301 movs r3, #1 800f6ec: 4632 mov r2, r6 800f6ee: 4649 mov r1, r9 800f6f0: 4640 mov r0, r8 800f6f2: 47d0 blx sl 800f6f4: 3001 adds r0, #1 800f6f6: d09d beq.n 800f634 <_printf_i+0x15c> 800f6f8: 3501 adds r5, #1 800f6fa: 68e3 ldr r3, [r4, #12] 800f6fc: 9903 ldr r1, [sp, #12] 800f6fe: 1a5b subs r3, r3, r1 800f700: 42ab cmp r3, r5 800f702: dcf2 bgt.n 800f6ea <_printf_i+0x212> 800f704: e7eb b.n 800f6de <_printf_i+0x206> 800f706: 2500 movs r5, #0 800f708: f104 0619 add.w r6, r4, #25 800f70c: e7f5 b.n 800f6fa <_printf_i+0x222> 800f70e: bf00 nop 800f710: 08011a7e .word 0x08011a7e 800f714: 08011a8f .word 0x08011a8f 0800f718 : 800f718: 2300 movs r3, #0 800f71a: b510 push {r4, lr} 800f71c: 4604 mov r4, r0 800f71e: e9c0 3300 strd r3, r3, [r0] 800f722: e9c0 3304 strd r3, r3, [r0, #16] 800f726: 6083 str r3, [r0, #8] 800f728: 8181 strh r1, [r0, #12] 800f72a: 6643 str r3, [r0, #100] @ 0x64 800f72c: 81c2 strh r2, [r0, #14] 800f72e: 6183 str r3, [r0, #24] 800f730: 4619 mov r1, r3 800f732: 2208 movs r2, #8 800f734: 305c adds r0, #92 @ 0x5c 800f736: f000 f9e7 bl 800fb08 800f73a: 4b0d ldr r3, [pc, #52] @ (800f770 ) 800f73c: 6263 str r3, [r4, #36] @ 0x24 800f73e: 4b0d ldr r3, [pc, #52] @ (800f774 ) 800f740: 62a3 str r3, [r4, #40] @ 0x28 800f742: 4b0d ldr r3, [pc, #52] @ (800f778 ) 800f744: 62e3 str r3, [r4, #44] @ 0x2c 800f746: 4b0d ldr r3, [pc, #52] @ (800f77c ) 800f748: 6323 str r3, [r4, #48] @ 0x30 800f74a: 4b0d ldr r3, [pc, #52] @ (800f780 ) 800f74c: 6224 str r4, [r4, #32] 800f74e: 429c cmp r4, r3 800f750: d006 beq.n 800f760 800f752: f103 0268 add.w r2, r3, #104 @ 0x68 800f756: 4294 cmp r4, r2 800f758: d002 beq.n 800f760 800f75a: 33d0 adds r3, #208 @ 0xd0 800f75c: 429c cmp r4, r3 800f75e: d105 bne.n 800f76c 800f760: f104 0058 add.w r0, r4, #88 @ 0x58 800f764: e8bd 4010 ldmia.w sp!, {r4, lr} 800f768: f000 baa0 b.w 800fcac <__retarget_lock_init_recursive> 800f76c: bd10 pop {r4, pc} 800f76e: bf00 nop 800f770: 0800f959 .word 0x0800f959 800f774: 0800f97b .word 0x0800f97b 800f778: 0800f9b3 .word 0x0800f9b3 800f77c: 0800f9d7 .word 0x0800f9d7 800f780: 24013198 .word 0x24013198 0800f784 : 800f784: 4a02 ldr r2, [pc, #8] @ (800f790 ) 800f786: 4903 ldr r1, [pc, #12] @ (800f794 ) 800f788: 4803 ldr r0, [pc, #12] @ (800f798 ) 800f78a: f000 b869 b.w 800f860 <_fwalk_sglue> 800f78e: bf00 nop 800f790: 24000048 .word 0x24000048 800f794: 08011299 .word 0x08011299 800f798: 24000058 .word 0x24000058 0800f79c : 800f79c: 6841 ldr r1, [r0, #4] 800f79e: 4b0c ldr r3, [pc, #48] @ (800f7d0 ) 800f7a0: 4299 cmp r1, r3 800f7a2: b510 push {r4, lr} 800f7a4: 4604 mov r4, r0 800f7a6: d001 beq.n 800f7ac 800f7a8: f001 fd76 bl 8011298 <_fflush_r> 800f7ac: 68a1 ldr r1, [r4, #8] 800f7ae: 4b09 ldr r3, [pc, #36] @ (800f7d4 ) 800f7b0: 4299 cmp r1, r3 800f7b2: d002 beq.n 800f7ba 800f7b4: 4620 mov r0, r4 800f7b6: f001 fd6f bl 8011298 <_fflush_r> 800f7ba: 68e1 ldr r1, [r4, #12] 800f7bc: 4b06 ldr r3, [pc, #24] @ (800f7d8 ) 800f7be: 4299 cmp r1, r3 800f7c0: d004 beq.n 800f7cc 800f7c2: 4620 mov r0, r4 800f7c4: e8bd 4010 ldmia.w sp!, {r4, lr} 800f7c8: f001 bd66 b.w 8011298 <_fflush_r> 800f7cc: bd10 pop {r4, pc} 800f7ce: bf00 nop 800f7d0: 24013198 .word 0x24013198 800f7d4: 24013200 .word 0x24013200 800f7d8: 24013268 .word 0x24013268 0800f7dc : 800f7dc: b510 push {r4, lr} 800f7de: 4b0b ldr r3, [pc, #44] @ (800f80c ) 800f7e0: 4c0b ldr r4, [pc, #44] @ (800f810 ) 800f7e2: 4a0c ldr r2, [pc, #48] @ (800f814 ) 800f7e4: 601a str r2, [r3, #0] 800f7e6: 4620 mov r0, r4 800f7e8: 2200 movs r2, #0 800f7ea: 2104 movs r1, #4 800f7ec: f7ff ff94 bl 800f718 800f7f0: f104 0068 add.w r0, r4, #104 @ 0x68 800f7f4: 2201 movs r2, #1 800f7f6: 2109 movs r1, #9 800f7f8: f7ff ff8e bl 800f718 800f7fc: f104 00d0 add.w r0, r4, #208 @ 0xd0 800f800: 2202 movs r2, #2 800f802: e8bd 4010 ldmia.w sp!, {r4, lr} 800f806: 2112 movs r1, #18 800f808: f7ff bf86 b.w 800f718 800f80c: 240132d0 .word 0x240132d0 800f810: 24013198 .word 0x24013198 800f814: 0800f785 .word 0x0800f785 0800f818 <__sfp_lock_acquire>: 800f818: 4801 ldr r0, [pc, #4] @ (800f820 <__sfp_lock_acquire+0x8>) 800f81a: f000 ba48 b.w 800fcae <__retarget_lock_acquire_recursive> 800f81e: bf00 nop 800f820: 240132d9 .word 0x240132d9 0800f824 <__sfp_lock_release>: 800f824: 4801 ldr r0, [pc, #4] @ (800f82c <__sfp_lock_release+0x8>) 800f826: f000 ba43 b.w 800fcb0 <__retarget_lock_release_recursive> 800f82a: bf00 nop 800f82c: 240132d9 .word 0x240132d9 0800f830 <__sinit>: 800f830: b510 push {r4, lr} 800f832: 4604 mov r4, r0 800f834: f7ff fff0 bl 800f818 <__sfp_lock_acquire> 800f838: 6a23 ldr r3, [r4, #32] 800f83a: b11b cbz r3, 800f844 <__sinit+0x14> 800f83c: e8bd 4010 ldmia.w sp!, {r4, lr} 800f840: f7ff bff0 b.w 800f824 <__sfp_lock_release> 800f844: 4b04 ldr r3, [pc, #16] @ (800f858 <__sinit+0x28>) 800f846: 6223 str r3, [r4, #32] 800f848: 4b04 ldr r3, [pc, #16] @ (800f85c <__sinit+0x2c>) 800f84a: 681b ldr r3, [r3, #0] 800f84c: 2b00 cmp r3, #0 800f84e: d1f5 bne.n 800f83c <__sinit+0xc> 800f850: f7ff ffc4 bl 800f7dc 800f854: e7f2 b.n 800f83c <__sinit+0xc> 800f856: bf00 nop 800f858: 0800f79d .word 0x0800f79d 800f85c: 240132d0 .word 0x240132d0 0800f860 <_fwalk_sglue>: 800f860: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800f864: 4607 mov r7, r0 800f866: 4688 mov r8, r1 800f868: 4614 mov r4, r2 800f86a: 2600 movs r6, #0 800f86c: e9d4 9501 ldrd r9, r5, [r4, #4] 800f870: f1b9 0901 subs.w r9, r9, #1 800f874: d505 bpl.n 800f882 <_fwalk_sglue+0x22> 800f876: 6824 ldr r4, [r4, #0] 800f878: 2c00 cmp r4, #0 800f87a: d1f7 bne.n 800f86c <_fwalk_sglue+0xc> 800f87c: 4630 mov r0, r6 800f87e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800f882: 89ab ldrh r3, [r5, #12] 800f884: 2b01 cmp r3, #1 800f886: d907 bls.n 800f898 <_fwalk_sglue+0x38> 800f888: f9b5 300e ldrsh.w r3, [r5, #14] 800f88c: 3301 adds r3, #1 800f88e: d003 beq.n 800f898 <_fwalk_sglue+0x38> 800f890: 4629 mov r1, r5 800f892: 4638 mov r0, r7 800f894: 47c0 blx r8 800f896: 4306 orrs r6, r0 800f898: 3568 adds r5, #104 @ 0x68 800f89a: e7e9 b.n 800f870 <_fwalk_sglue+0x10> 0800f89c <_puts_r>: 800f89c: 6a03 ldr r3, [r0, #32] 800f89e: b570 push {r4, r5, r6, lr} 800f8a0: 6884 ldr r4, [r0, #8] 800f8a2: 4605 mov r5, r0 800f8a4: 460e mov r6, r1 800f8a6: b90b cbnz r3, 800f8ac <_puts_r+0x10> 800f8a8: f7ff ffc2 bl 800f830 <__sinit> 800f8ac: 6e63 ldr r3, [r4, #100] @ 0x64 800f8ae: 07db lsls r3, r3, #31 800f8b0: d405 bmi.n 800f8be <_puts_r+0x22> 800f8b2: 89a3 ldrh r3, [r4, #12] 800f8b4: 0598 lsls r0, r3, #22 800f8b6: d402 bmi.n 800f8be <_puts_r+0x22> 800f8b8: 6da0 ldr r0, [r4, #88] @ 0x58 800f8ba: f000 f9f8 bl 800fcae <__retarget_lock_acquire_recursive> 800f8be: 89a3 ldrh r3, [r4, #12] 800f8c0: 0719 lsls r1, r3, #28 800f8c2: d502 bpl.n 800f8ca <_puts_r+0x2e> 800f8c4: 6923 ldr r3, [r4, #16] 800f8c6: 2b00 cmp r3, #0 800f8c8: d135 bne.n 800f936 <_puts_r+0x9a> 800f8ca: 4621 mov r1, r4 800f8cc: 4628 mov r0, r5 800f8ce: f000 f8c5 bl 800fa5c <__swsetup_r> 800f8d2: b380 cbz r0, 800f936 <_puts_r+0x9a> 800f8d4: f04f 35ff mov.w r5, #4294967295 @ 0xffffffff 800f8d8: 6e63 ldr r3, [r4, #100] @ 0x64 800f8da: 07da lsls r2, r3, #31 800f8dc: d405 bmi.n 800f8ea <_puts_r+0x4e> 800f8de: 89a3 ldrh r3, [r4, #12] 800f8e0: 059b lsls r3, r3, #22 800f8e2: d402 bmi.n 800f8ea <_puts_r+0x4e> 800f8e4: 6da0 ldr r0, [r4, #88] @ 0x58 800f8e6: f000 f9e3 bl 800fcb0 <__retarget_lock_release_recursive> 800f8ea: 4628 mov r0, r5 800f8ec: bd70 pop {r4, r5, r6, pc} 800f8ee: 2b00 cmp r3, #0 800f8f0: da04 bge.n 800f8fc <_puts_r+0x60> 800f8f2: 69a2 ldr r2, [r4, #24] 800f8f4: 429a cmp r2, r3 800f8f6: dc17 bgt.n 800f928 <_puts_r+0x8c> 800f8f8: 290a cmp r1, #10 800f8fa: d015 beq.n 800f928 <_puts_r+0x8c> 800f8fc: 6823 ldr r3, [r4, #0] 800f8fe: 1c5a adds r2, r3, #1 800f900: 6022 str r2, [r4, #0] 800f902: 7019 strb r1, [r3, #0] 800f904: 68a3 ldr r3, [r4, #8] 800f906: f816 1f01 ldrb.w r1, [r6, #1]! 800f90a: 3b01 subs r3, #1 800f90c: 60a3 str r3, [r4, #8] 800f90e: 2900 cmp r1, #0 800f910: d1ed bne.n 800f8ee <_puts_r+0x52> 800f912: 2b00 cmp r3, #0 800f914: da11 bge.n 800f93a <_puts_r+0x9e> 800f916: 4622 mov r2, r4 800f918: 210a movs r1, #10 800f91a: 4628 mov r0, r5 800f91c: f000 f85f bl 800f9de <__swbuf_r> 800f920: 3001 adds r0, #1 800f922: d0d7 beq.n 800f8d4 <_puts_r+0x38> 800f924: 250a movs r5, #10 800f926: e7d7 b.n 800f8d8 <_puts_r+0x3c> 800f928: 4622 mov r2, r4 800f92a: 4628 mov r0, r5 800f92c: f000 f857 bl 800f9de <__swbuf_r> 800f930: 3001 adds r0, #1 800f932: d1e7 bne.n 800f904 <_puts_r+0x68> 800f934: e7ce b.n 800f8d4 <_puts_r+0x38> 800f936: 3e01 subs r6, #1 800f938: e7e4 b.n 800f904 <_puts_r+0x68> 800f93a: 6823 ldr r3, [r4, #0] 800f93c: 1c5a adds r2, r3, #1 800f93e: 6022 str r2, [r4, #0] 800f940: 220a movs r2, #10 800f942: 701a strb r2, [r3, #0] 800f944: e7ee b.n 800f924 <_puts_r+0x88> ... 0800f948 : 800f948: 4b02 ldr r3, [pc, #8] @ (800f954 ) 800f94a: 4601 mov r1, r0 800f94c: 6818 ldr r0, [r3, #0] 800f94e: f7ff bfa5 b.w 800f89c <_puts_r> 800f952: bf00 nop 800f954: 24000054 .word 0x24000054 0800f958 <__sread>: 800f958: b510 push {r4, lr} 800f95a: 460c mov r4, r1 800f95c: f9b1 100e ldrsh.w r1, [r1, #14] 800f960: f000 f956 bl 800fc10 <_read_r> 800f964: 2800 cmp r0, #0 800f966: bfab itete ge 800f968: 6d63 ldrge r3, [r4, #84] @ 0x54 800f96a: 89a3 ldrhlt r3, [r4, #12] 800f96c: 181b addge r3, r3, r0 800f96e: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 800f972: bfac ite ge 800f974: 6563 strge r3, [r4, #84] @ 0x54 800f976: 81a3 strhlt r3, [r4, #12] 800f978: bd10 pop {r4, pc} 0800f97a <__swrite>: 800f97a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800f97e: 461f mov r7, r3 800f980: 898b ldrh r3, [r1, #12] 800f982: 05db lsls r3, r3, #23 800f984: 4605 mov r5, r0 800f986: 460c mov r4, r1 800f988: 4616 mov r6, r2 800f98a: d505 bpl.n 800f998 <__swrite+0x1e> 800f98c: f9b1 100e ldrsh.w r1, [r1, #14] 800f990: 2302 movs r3, #2 800f992: 2200 movs r2, #0 800f994: f000 f92a bl 800fbec <_lseek_r> 800f998: 89a3 ldrh r3, [r4, #12] 800f99a: f9b4 100e ldrsh.w r1, [r4, #14] 800f99e: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800f9a2: 81a3 strh r3, [r4, #12] 800f9a4: 4632 mov r2, r6 800f9a6: 463b mov r3, r7 800f9a8: 4628 mov r0, r5 800f9aa: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800f9ae: f000 b941 b.w 800fc34 <_write_r> 0800f9b2 <__sseek>: 800f9b2: b510 push {r4, lr} 800f9b4: 460c mov r4, r1 800f9b6: f9b1 100e ldrsh.w r1, [r1, #14] 800f9ba: f000 f917 bl 800fbec <_lseek_r> 800f9be: 1c43 adds r3, r0, #1 800f9c0: 89a3 ldrh r3, [r4, #12] 800f9c2: bf15 itete ne 800f9c4: 6560 strne r0, [r4, #84] @ 0x54 800f9c6: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 800f9ca: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 800f9ce: 81a3 strheq r3, [r4, #12] 800f9d0: bf18 it ne 800f9d2: 81a3 strhne r3, [r4, #12] 800f9d4: bd10 pop {r4, pc} 0800f9d6 <__sclose>: 800f9d6: f9b1 100e ldrsh.w r1, [r1, #14] 800f9da: f000 b8a1 b.w 800fb20 <_close_r> 0800f9de <__swbuf_r>: 800f9de: b5f8 push {r3, r4, r5, r6, r7, lr} 800f9e0: 460e mov r6, r1 800f9e2: 4614 mov r4, r2 800f9e4: 4605 mov r5, r0 800f9e6: b118 cbz r0, 800f9f0 <__swbuf_r+0x12> 800f9e8: 6a03 ldr r3, [r0, #32] 800f9ea: b90b cbnz r3, 800f9f0 <__swbuf_r+0x12> 800f9ec: f7ff ff20 bl 800f830 <__sinit> 800f9f0: 69a3 ldr r3, [r4, #24] 800f9f2: 60a3 str r3, [r4, #8] 800f9f4: 89a3 ldrh r3, [r4, #12] 800f9f6: 071a lsls r2, r3, #28 800f9f8: d501 bpl.n 800f9fe <__swbuf_r+0x20> 800f9fa: 6923 ldr r3, [r4, #16] 800f9fc: b943 cbnz r3, 800fa10 <__swbuf_r+0x32> 800f9fe: 4621 mov r1, r4 800fa00: 4628 mov r0, r5 800fa02: f000 f82b bl 800fa5c <__swsetup_r> 800fa06: b118 cbz r0, 800fa10 <__swbuf_r+0x32> 800fa08: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 800fa0c: 4638 mov r0, r7 800fa0e: bdf8 pop {r3, r4, r5, r6, r7, pc} 800fa10: 6823 ldr r3, [r4, #0] 800fa12: 6922 ldr r2, [r4, #16] 800fa14: 1a98 subs r0, r3, r2 800fa16: 6963 ldr r3, [r4, #20] 800fa18: b2f6 uxtb r6, r6 800fa1a: 4283 cmp r3, r0 800fa1c: 4637 mov r7, r6 800fa1e: dc05 bgt.n 800fa2c <__swbuf_r+0x4e> 800fa20: 4621 mov r1, r4 800fa22: 4628 mov r0, r5 800fa24: f001 fc38 bl 8011298 <_fflush_r> 800fa28: 2800 cmp r0, #0 800fa2a: d1ed bne.n 800fa08 <__swbuf_r+0x2a> 800fa2c: 68a3 ldr r3, [r4, #8] 800fa2e: 3b01 subs r3, #1 800fa30: 60a3 str r3, [r4, #8] 800fa32: 6823 ldr r3, [r4, #0] 800fa34: 1c5a adds r2, r3, #1 800fa36: 6022 str r2, [r4, #0] 800fa38: 701e strb r6, [r3, #0] 800fa3a: 6962 ldr r2, [r4, #20] 800fa3c: 1c43 adds r3, r0, #1 800fa3e: 429a cmp r2, r3 800fa40: d004 beq.n 800fa4c <__swbuf_r+0x6e> 800fa42: 89a3 ldrh r3, [r4, #12] 800fa44: 07db lsls r3, r3, #31 800fa46: d5e1 bpl.n 800fa0c <__swbuf_r+0x2e> 800fa48: 2e0a cmp r6, #10 800fa4a: d1df bne.n 800fa0c <__swbuf_r+0x2e> 800fa4c: 4621 mov r1, r4 800fa4e: 4628 mov r0, r5 800fa50: f001 fc22 bl 8011298 <_fflush_r> 800fa54: 2800 cmp r0, #0 800fa56: d0d9 beq.n 800fa0c <__swbuf_r+0x2e> 800fa58: e7d6 b.n 800fa08 <__swbuf_r+0x2a> ... 0800fa5c <__swsetup_r>: 800fa5c: b538 push {r3, r4, r5, lr} 800fa5e: 4b29 ldr r3, [pc, #164] @ (800fb04 <__swsetup_r+0xa8>) 800fa60: 4605 mov r5, r0 800fa62: 6818 ldr r0, [r3, #0] 800fa64: 460c mov r4, r1 800fa66: b118 cbz r0, 800fa70 <__swsetup_r+0x14> 800fa68: 6a03 ldr r3, [r0, #32] 800fa6a: b90b cbnz r3, 800fa70 <__swsetup_r+0x14> 800fa6c: f7ff fee0 bl 800f830 <__sinit> 800fa70: f9b4 300c ldrsh.w r3, [r4, #12] 800fa74: 0719 lsls r1, r3, #28 800fa76: d422 bmi.n 800fabe <__swsetup_r+0x62> 800fa78: 06da lsls r2, r3, #27 800fa7a: d407 bmi.n 800fa8c <__swsetup_r+0x30> 800fa7c: 2209 movs r2, #9 800fa7e: 602a str r2, [r5, #0] 800fa80: f043 0340 orr.w r3, r3, #64 @ 0x40 800fa84: 81a3 strh r3, [r4, #12] 800fa86: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800fa8a: e033 b.n 800faf4 <__swsetup_r+0x98> 800fa8c: 0758 lsls r0, r3, #29 800fa8e: d512 bpl.n 800fab6 <__swsetup_r+0x5a> 800fa90: 6b61 ldr r1, [r4, #52] @ 0x34 800fa92: b141 cbz r1, 800faa6 <__swsetup_r+0x4a> 800fa94: f104 0344 add.w r3, r4, #68 @ 0x44 800fa98: 4299 cmp r1, r3 800fa9a: d002 beq.n 800faa2 <__swsetup_r+0x46> 800fa9c: 4628 mov r0, r5 800fa9e: f000 fef5 bl 801088c <_free_r> 800faa2: 2300 movs r3, #0 800faa4: 6363 str r3, [r4, #52] @ 0x34 800faa6: 89a3 ldrh r3, [r4, #12] 800faa8: f023 0324 bic.w r3, r3, #36 @ 0x24 800faac: 81a3 strh r3, [r4, #12] 800faae: 2300 movs r3, #0 800fab0: 6063 str r3, [r4, #4] 800fab2: 6923 ldr r3, [r4, #16] 800fab4: 6023 str r3, [r4, #0] 800fab6: 89a3 ldrh r3, [r4, #12] 800fab8: f043 0308 orr.w r3, r3, #8 800fabc: 81a3 strh r3, [r4, #12] 800fabe: 6923 ldr r3, [r4, #16] 800fac0: b94b cbnz r3, 800fad6 <__swsetup_r+0x7a> 800fac2: 89a3 ldrh r3, [r4, #12] 800fac4: f403 7320 and.w r3, r3, #640 @ 0x280 800fac8: f5b3 7f00 cmp.w r3, #512 @ 0x200 800facc: d003 beq.n 800fad6 <__swsetup_r+0x7a> 800face: 4621 mov r1, r4 800fad0: 4628 mov r0, r5 800fad2: f001 fc2f bl 8011334 <__smakebuf_r> 800fad6: f9b4 300c ldrsh.w r3, [r4, #12] 800fada: f013 0201 ands.w r2, r3, #1 800fade: d00a beq.n 800faf6 <__swsetup_r+0x9a> 800fae0: 2200 movs r2, #0 800fae2: 60a2 str r2, [r4, #8] 800fae4: 6962 ldr r2, [r4, #20] 800fae6: 4252 negs r2, r2 800fae8: 61a2 str r2, [r4, #24] 800faea: 6922 ldr r2, [r4, #16] 800faec: b942 cbnz r2, 800fb00 <__swsetup_r+0xa4> 800faee: f013 0080 ands.w r0, r3, #128 @ 0x80 800faf2: d1c5 bne.n 800fa80 <__swsetup_r+0x24> 800faf4: bd38 pop {r3, r4, r5, pc} 800faf6: 0799 lsls r1, r3, #30 800faf8: bf58 it pl 800fafa: 6962 ldrpl r2, [r4, #20] 800fafc: 60a2 str r2, [r4, #8] 800fafe: e7f4 b.n 800faea <__swsetup_r+0x8e> 800fb00: 2000 movs r0, #0 800fb02: e7f7 b.n 800faf4 <__swsetup_r+0x98> 800fb04: 24000054 .word 0x24000054 0800fb08 : 800fb08: 4402 add r2, r0 800fb0a: 4603 mov r3, r0 800fb0c: 4293 cmp r3, r2 800fb0e: d100 bne.n 800fb12 800fb10: 4770 bx lr 800fb12: f803 1b01 strb.w r1, [r3], #1 800fb16: e7f9 b.n 800fb0c 0800fb18 <_localeconv_r>: 800fb18: 4800 ldr r0, [pc, #0] @ (800fb1c <_localeconv_r+0x4>) 800fb1a: 4770 bx lr 800fb1c: 24000194 .word 0x24000194 0800fb20 <_close_r>: 800fb20: b538 push {r3, r4, r5, lr} 800fb22: 4d06 ldr r5, [pc, #24] @ (800fb3c <_close_r+0x1c>) 800fb24: 2300 movs r3, #0 800fb26: 4604 mov r4, r0 800fb28: 4608 mov r0, r1 800fb2a: 602b str r3, [r5, #0] 800fb2c: f7f3 fad8 bl 80030e0 <_close> 800fb30: 1c43 adds r3, r0, #1 800fb32: d102 bne.n 800fb3a <_close_r+0x1a> 800fb34: 682b ldr r3, [r5, #0] 800fb36: b103 cbz r3, 800fb3a <_close_r+0x1a> 800fb38: 6023 str r3, [r4, #0] 800fb3a: bd38 pop {r3, r4, r5, pc} 800fb3c: 240132d4 .word 0x240132d4 0800fb40 <_reclaim_reent>: 800fb40: 4b29 ldr r3, [pc, #164] @ (800fbe8 <_reclaim_reent+0xa8>) 800fb42: 681b ldr r3, [r3, #0] 800fb44: 4283 cmp r3, r0 800fb46: b570 push {r4, r5, r6, lr} 800fb48: 4604 mov r4, r0 800fb4a: d04b beq.n 800fbe4 <_reclaim_reent+0xa4> 800fb4c: 69c3 ldr r3, [r0, #28] 800fb4e: b1ab cbz r3, 800fb7c <_reclaim_reent+0x3c> 800fb50: 68db ldr r3, [r3, #12] 800fb52: b16b cbz r3, 800fb70 <_reclaim_reent+0x30> 800fb54: 2500 movs r5, #0 800fb56: 69e3 ldr r3, [r4, #28] 800fb58: 68db ldr r3, [r3, #12] 800fb5a: 5959 ldr r1, [r3, r5] 800fb5c: 2900 cmp r1, #0 800fb5e: d13b bne.n 800fbd8 <_reclaim_reent+0x98> 800fb60: 3504 adds r5, #4 800fb62: 2d80 cmp r5, #128 @ 0x80 800fb64: d1f7 bne.n 800fb56 <_reclaim_reent+0x16> 800fb66: 69e3 ldr r3, [r4, #28] 800fb68: 4620 mov r0, r4 800fb6a: 68d9 ldr r1, [r3, #12] 800fb6c: f000 fe8e bl 801088c <_free_r> 800fb70: 69e3 ldr r3, [r4, #28] 800fb72: 6819 ldr r1, [r3, #0] 800fb74: b111 cbz r1, 800fb7c <_reclaim_reent+0x3c> 800fb76: 4620 mov r0, r4 800fb78: f000 fe88 bl 801088c <_free_r> 800fb7c: 6961 ldr r1, [r4, #20] 800fb7e: b111 cbz r1, 800fb86 <_reclaim_reent+0x46> 800fb80: 4620 mov r0, r4 800fb82: f000 fe83 bl 801088c <_free_r> 800fb86: 69e1 ldr r1, [r4, #28] 800fb88: b111 cbz r1, 800fb90 <_reclaim_reent+0x50> 800fb8a: 4620 mov r0, r4 800fb8c: f000 fe7e bl 801088c <_free_r> 800fb90: 6b21 ldr r1, [r4, #48] @ 0x30 800fb92: b111 cbz r1, 800fb9a <_reclaim_reent+0x5a> 800fb94: 4620 mov r0, r4 800fb96: f000 fe79 bl 801088c <_free_r> 800fb9a: 6b61 ldr r1, [r4, #52] @ 0x34 800fb9c: b111 cbz r1, 800fba4 <_reclaim_reent+0x64> 800fb9e: 4620 mov r0, r4 800fba0: f000 fe74 bl 801088c <_free_r> 800fba4: 6ba1 ldr r1, [r4, #56] @ 0x38 800fba6: b111 cbz r1, 800fbae <_reclaim_reent+0x6e> 800fba8: 4620 mov r0, r4 800fbaa: f000 fe6f bl 801088c <_free_r> 800fbae: 6ca1 ldr r1, [r4, #72] @ 0x48 800fbb0: b111 cbz r1, 800fbb8 <_reclaim_reent+0x78> 800fbb2: 4620 mov r0, r4 800fbb4: f000 fe6a bl 801088c <_free_r> 800fbb8: 6c61 ldr r1, [r4, #68] @ 0x44 800fbba: b111 cbz r1, 800fbc2 <_reclaim_reent+0x82> 800fbbc: 4620 mov r0, r4 800fbbe: f000 fe65 bl 801088c <_free_r> 800fbc2: 6ae1 ldr r1, [r4, #44] @ 0x2c 800fbc4: b111 cbz r1, 800fbcc <_reclaim_reent+0x8c> 800fbc6: 4620 mov r0, r4 800fbc8: f000 fe60 bl 801088c <_free_r> 800fbcc: 6a23 ldr r3, [r4, #32] 800fbce: b14b cbz r3, 800fbe4 <_reclaim_reent+0xa4> 800fbd0: 4620 mov r0, r4 800fbd2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 800fbd6: 4718 bx r3 800fbd8: 680e ldr r6, [r1, #0] 800fbda: 4620 mov r0, r4 800fbdc: f000 fe56 bl 801088c <_free_r> 800fbe0: 4631 mov r1, r6 800fbe2: e7bb b.n 800fb5c <_reclaim_reent+0x1c> 800fbe4: bd70 pop {r4, r5, r6, pc} 800fbe6: bf00 nop 800fbe8: 24000054 .word 0x24000054 0800fbec <_lseek_r>: 800fbec: b538 push {r3, r4, r5, lr} 800fbee: 4d07 ldr r5, [pc, #28] @ (800fc0c <_lseek_r+0x20>) 800fbf0: 4604 mov r4, r0 800fbf2: 4608 mov r0, r1 800fbf4: 4611 mov r1, r2 800fbf6: 2200 movs r2, #0 800fbf8: 602a str r2, [r5, #0] 800fbfa: 461a mov r2, r3 800fbfc: f7f3 fa7c bl 80030f8 <_lseek> 800fc00: 1c43 adds r3, r0, #1 800fc02: d102 bne.n 800fc0a <_lseek_r+0x1e> 800fc04: 682b ldr r3, [r5, #0] 800fc06: b103 cbz r3, 800fc0a <_lseek_r+0x1e> 800fc08: 6023 str r3, [r4, #0] 800fc0a: bd38 pop {r3, r4, r5, pc} 800fc0c: 240132d4 .word 0x240132d4 0800fc10 <_read_r>: 800fc10: b538 push {r3, r4, r5, lr} 800fc12: 4d07 ldr r5, [pc, #28] @ (800fc30 <_read_r+0x20>) 800fc14: 4604 mov r4, r0 800fc16: 4608 mov r0, r1 800fc18: 4611 mov r1, r2 800fc1a: 2200 movs r2, #0 800fc1c: 602a str r2, [r5, #0] 800fc1e: 461a mov r2, r3 800fc20: f7f3 fa42 bl 80030a8 <_read> 800fc24: 1c43 adds r3, r0, #1 800fc26: d102 bne.n 800fc2e <_read_r+0x1e> 800fc28: 682b ldr r3, [r5, #0] 800fc2a: b103 cbz r3, 800fc2e <_read_r+0x1e> 800fc2c: 6023 str r3, [r4, #0] 800fc2e: bd38 pop {r3, r4, r5, pc} 800fc30: 240132d4 .word 0x240132d4 0800fc34 <_write_r>: 800fc34: b538 push {r3, r4, r5, lr} 800fc36: 4d07 ldr r5, [pc, #28] @ (800fc54 <_write_r+0x20>) 800fc38: 4604 mov r4, r0 800fc3a: 4608 mov r0, r1 800fc3c: 4611 mov r1, r2 800fc3e: 2200 movs r2, #0 800fc40: 602a str r2, [r5, #0] 800fc42: 461a mov r2, r3 800fc44: f7f3 fa3e bl 80030c4 <_write> 800fc48: 1c43 adds r3, r0, #1 800fc4a: d102 bne.n 800fc52 <_write_r+0x1e> 800fc4c: 682b ldr r3, [r5, #0] 800fc4e: b103 cbz r3, 800fc52 <_write_r+0x1e> 800fc50: 6023 str r3, [r4, #0] 800fc52: bd38 pop {r3, r4, r5, pc} 800fc54: 240132d4 .word 0x240132d4 0800fc58 <__errno>: 800fc58: 4b01 ldr r3, [pc, #4] @ (800fc60 <__errno+0x8>) 800fc5a: 6818 ldr r0, [r3, #0] 800fc5c: 4770 bx lr 800fc5e: bf00 nop 800fc60: 24000054 .word 0x24000054 0800fc64 <__libc_init_array>: 800fc64: b570 push {r4, r5, r6, lr} 800fc66: 4d0d ldr r5, [pc, #52] @ (800fc9c <__libc_init_array+0x38>) 800fc68: 4c0d ldr r4, [pc, #52] @ (800fca0 <__libc_init_array+0x3c>) 800fc6a: 1b64 subs r4, r4, r5 800fc6c: 10a4 asrs r4, r4, #2 800fc6e: 2600 movs r6, #0 800fc70: 42a6 cmp r6, r4 800fc72: d109 bne.n 800fc88 <__libc_init_array+0x24> 800fc74: 4d0b ldr r5, [pc, #44] @ (800fca4 <__libc_init_array+0x40>) 800fc76: 4c0c ldr r4, [pc, #48] @ (800fca8 <__libc_init_array+0x44>) 800fc78: f001 fe5c bl 8011934 <_init> 800fc7c: 1b64 subs r4, r4, r5 800fc7e: 10a4 asrs r4, r4, #2 800fc80: 2600 movs r6, #0 800fc82: 42a6 cmp r6, r4 800fc84: d105 bne.n 800fc92 <__libc_init_array+0x2e> 800fc86: bd70 pop {r4, r5, r6, pc} 800fc88: f855 3b04 ldr.w r3, [r5], #4 800fc8c: 4798 blx r3 800fc8e: 3601 adds r6, #1 800fc90: e7ee b.n 800fc70 <__libc_init_array+0xc> 800fc92: f855 3b04 ldr.w r3, [r5], #4 800fc96: 4798 blx r3 800fc98: 3601 adds r6, #1 800fc9a: e7f2 b.n 800fc82 <__libc_init_array+0x1e> 800fc9c: 08011df0 .word 0x08011df0 800fca0: 08011df0 .word 0x08011df0 800fca4: 08011df0 .word 0x08011df0 800fca8: 08011df4 .word 0x08011df4 0800fcac <__retarget_lock_init_recursive>: 800fcac: 4770 bx lr 0800fcae <__retarget_lock_acquire_recursive>: 800fcae: 4770 bx lr 0800fcb0 <__retarget_lock_release_recursive>: 800fcb0: 4770 bx lr 0800fcb2 : 800fcb2: 440a add r2, r1 800fcb4: 4291 cmp r1, r2 800fcb6: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800fcba: d100 bne.n 800fcbe 800fcbc: 4770 bx lr 800fcbe: b510 push {r4, lr} 800fcc0: f811 4b01 ldrb.w r4, [r1], #1 800fcc4: f803 4f01 strb.w r4, [r3, #1]! 800fcc8: 4291 cmp r1, r2 800fcca: d1f9 bne.n 800fcc0 800fccc: bd10 pop {r4, pc} 0800fcce : 800fcce: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 800fcd2: 6903 ldr r3, [r0, #16] 800fcd4: 690c ldr r4, [r1, #16] 800fcd6: 42a3 cmp r3, r4 800fcd8: 4607 mov r7, r0 800fcda: db7e blt.n 800fdda 800fcdc: 3c01 subs r4, #1 800fcde: f101 0814 add.w r8, r1, #20 800fce2: 00a3 lsls r3, r4, #2 800fce4: f100 0514 add.w r5, r0, #20 800fce8: 9300 str r3, [sp, #0] 800fcea: eb05 0384 add.w r3, r5, r4, lsl #2 800fcee: 9301 str r3, [sp, #4] 800fcf0: f858 3024 ldr.w r3, [r8, r4, lsl #2] 800fcf4: f855 2024 ldr.w r2, [r5, r4, lsl #2] 800fcf8: 3301 adds r3, #1 800fcfa: 429a cmp r2, r3 800fcfc: eb08 0984 add.w r9, r8, r4, lsl #2 800fd00: fbb2 f6f3 udiv r6, r2, r3 800fd04: d32e bcc.n 800fd64 800fd06: f04f 0a00 mov.w sl, #0 800fd0a: 46c4 mov ip, r8 800fd0c: 46ae mov lr, r5 800fd0e: 46d3 mov fp, sl 800fd10: f85c 3b04 ldr.w r3, [ip], #4 800fd14: b298 uxth r0, r3 800fd16: fb06 a000 mla r0, r6, r0, sl 800fd1a: 0c02 lsrs r2, r0, #16 800fd1c: 0c1b lsrs r3, r3, #16 800fd1e: fb06 2303 mla r3, r6, r3, r2 800fd22: f8de 2000 ldr.w r2, [lr] 800fd26: b280 uxth r0, r0 800fd28: b292 uxth r2, r2 800fd2a: 1a12 subs r2, r2, r0 800fd2c: 445a add r2, fp 800fd2e: f8de 0000 ldr.w r0, [lr] 800fd32: ea4f 4a13 mov.w sl, r3, lsr #16 800fd36: b29b uxth r3, r3 800fd38: ebc3 4322 rsb r3, r3, r2, asr #16 800fd3c: eb03 4310 add.w r3, r3, r0, lsr #16 800fd40: b292 uxth r2, r2 800fd42: ea42 4203 orr.w r2, r2, r3, lsl #16 800fd46: 45e1 cmp r9, ip 800fd48: f84e 2b04 str.w r2, [lr], #4 800fd4c: ea4f 4b23 mov.w fp, r3, asr #16 800fd50: d2de bcs.n 800fd10 800fd52: 9b00 ldr r3, [sp, #0] 800fd54: 58eb ldr r3, [r5, r3] 800fd56: b92b cbnz r3, 800fd64 800fd58: 9b01 ldr r3, [sp, #4] 800fd5a: 3b04 subs r3, #4 800fd5c: 429d cmp r5, r3 800fd5e: 461a mov r2, r3 800fd60: d32f bcc.n 800fdc2 800fd62: 613c str r4, [r7, #16] 800fd64: 4638 mov r0, r7 800fd66: f001 f90b bl 8010f80 <__mcmp> 800fd6a: 2800 cmp r0, #0 800fd6c: db25 blt.n 800fdba 800fd6e: 4629 mov r1, r5 800fd70: 2000 movs r0, #0 800fd72: f858 2b04 ldr.w r2, [r8], #4 800fd76: f8d1 c000 ldr.w ip, [r1] 800fd7a: fa1f fe82 uxth.w lr, r2 800fd7e: fa1f f38c uxth.w r3, ip 800fd82: eba3 030e sub.w r3, r3, lr 800fd86: 4403 add r3, r0 800fd88: 0c12 lsrs r2, r2, #16 800fd8a: ebc2 4223 rsb r2, r2, r3, asr #16 800fd8e: eb02 421c add.w r2, r2, ip, lsr #16 800fd92: b29b uxth r3, r3 800fd94: ea43 4302 orr.w r3, r3, r2, lsl #16 800fd98: 45c1 cmp r9, r8 800fd9a: f841 3b04 str.w r3, [r1], #4 800fd9e: ea4f 4022 mov.w r0, r2, asr #16 800fda2: d2e6 bcs.n 800fd72 800fda4: f855 2024 ldr.w r2, [r5, r4, lsl #2] 800fda8: eb05 0384 add.w r3, r5, r4, lsl #2 800fdac: b922 cbnz r2, 800fdb8 800fdae: 3b04 subs r3, #4 800fdb0: 429d cmp r5, r3 800fdb2: 461a mov r2, r3 800fdb4: d30b bcc.n 800fdce 800fdb6: 613c str r4, [r7, #16] 800fdb8: 3601 adds r6, #1 800fdba: 4630 mov r0, r6 800fdbc: b003 add sp, #12 800fdbe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800fdc2: 6812 ldr r2, [r2, #0] 800fdc4: 3b04 subs r3, #4 800fdc6: 2a00 cmp r2, #0 800fdc8: d1cb bne.n 800fd62 800fdca: 3c01 subs r4, #1 800fdcc: e7c6 b.n 800fd5c 800fdce: 6812 ldr r2, [r2, #0] 800fdd0: 3b04 subs r3, #4 800fdd2: 2a00 cmp r2, #0 800fdd4: d1ef bne.n 800fdb6 800fdd6: 3c01 subs r4, #1 800fdd8: e7ea b.n 800fdb0 800fdda: 2000 movs r0, #0 800fddc: e7ee b.n 800fdbc ... 0800fde0 <_dtoa_r>: 800fde0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800fde4: ed2d 8b02 vpush {d8} 800fde8: 69c7 ldr r7, [r0, #28] 800fdea: b091 sub sp, #68 @ 0x44 800fdec: ed8d 0b02 vstr d0, [sp, #8] 800fdf0: ec55 4b10 vmov r4, r5, d0 800fdf4: 9e1c ldr r6, [sp, #112] @ 0x70 800fdf6: 9107 str r1, [sp, #28] 800fdf8: 4681 mov r9, r0 800fdfa: 9209 str r2, [sp, #36] @ 0x24 800fdfc: 930d str r3, [sp, #52] @ 0x34 800fdfe: b97f cbnz r7, 800fe20 <_dtoa_r+0x40> 800fe00: 2010 movs r0, #16 800fe02: f000 fd8d bl 8010920 800fe06: 4602 mov r2, r0 800fe08: f8c9 001c str.w r0, [r9, #28] 800fe0c: b920 cbnz r0, 800fe18 <_dtoa_r+0x38> 800fe0e: 4ba0 ldr r3, [pc, #640] @ (8010090 <_dtoa_r+0x2b0>) 800fe10: 21ef movs r1, #239 @ 0xef 800fe12: 48a0 ldr r0, [pc, #640] @ (8010094 <_dtoa_r+0x2b4>) 800fe14: f001 fafc bl 8011410 <__assert_func> 800fe18: e9c0 7701 strd r7, r7, [r0, #4] 800fe1c: 6007 str r7, [r0, #0] 800fe1e: 60c7 str r7, [r0, #12] 800fe20: f8d9 301c ldr.w r3, [r9, #28] 800fe24: 6819 ldr r1, [r3, #0] 800fe26: b159 cbz r1, 800fe40 <_dtoa_r+0x60> 800fe28: 685a ldr r2, [r3, #4] 800fe2a: 604a str r2, [r1, #4] 800fe2c: 2301 movs r3, #1 800fe2e: 4093 lsls r3, r2 800fe30: 608b str r3, [r1, #8] 800fe32: 4648 mov r0, r9 800fe34: f000 fe6a bl 8010b0c <_Bfree> 800fe38: f8d9 301c ldr.w r3, [r9, #28] 800fe3c: 2200 movs r2, #0 800fe3e: 601a str r2, [r3, #0] 800fe40: 1e2b subs r3, r5, #0 800fe42: bfbb ittet lt 800fe44: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000 800fe48: 9303 strlt r3, [sp, #12] 800fe4a: 2300 movge r3, #0 800fe4c: 2201 movlt r2, #1 800fe4e: bfac ite ge 800fe50: 6033 strge r3, [r6, #0] 800fe52: 6032 strlt r2, [r6, #0] 800fe54: 4b90 ldr r3, [pc, #576] @ (8010098 <_dtoa_r+0x2b8>) 800fe56: 9e03 ldr r6, [sp, #12] 800fe58: 43b3 bics r3, r6 800fe5a: d110 bne.n 800fe7e <_dtoa_r+0x9e> 800fe5c: 9a0d ldr r2, [sp, #52] @ 0x34 800fe5e: f242 730f movw r3, #9999 @ 0x270f 800fe62: 6013 str r3, [r2, #0] 800fe64: f3c6 0313 ubfx r3, r6, #0, #20 800fe68: 4323 orrs r3, r4 800fe6a: f000 84de beq.w 801082a <_dtoa_r+0xa4a> 800fe6e: 9b1d ldr r3, [sp, #116] @ 0x74 800fe70: 4f8a ldr r7, [pc, #552] @ (801009c <_dtoa_r+0x2bc>) 800fe72: 2b00 cmp r3, #0 800fe74: f000 84e0 beq.w 8010838 <_dtoa_r+0xa58> 800fe78: 1cfb adds r3, r7, #3 800fe7a: f000 bcdb b.w 8010834 <_dtoa_r+0xa54> 800fe7e: ed9d 8b02 vldr d8, [sp, #8] 800fe82: eeb5 8b40 vcmp.f64 d8, #0.0 800fe86: eef1 fa10 vmrs APSR_nzcv, fpscr 800fe8a: d10a bne.n 800fea2 <_dtoa_r+0xc2> 800fe8c: 9a0d ldr r2, [sp, #52] @ 0x34 800fe8e: 2301 movs r3, #1 800fe90: 6013 str r3, [r2, #0] 800fe92: 9b1d ldr r3, [sp, #116] @ 0x74 800fe94: b113 cbz r3, 800fe9c <_dtoa_r+0xbc> 800fe96: 9a1d ldr r2, [sp, #116] @ 0x74 800fe98: 4b81 ldr r3, [pc, #516] @ (80100a0 <_dtoa_r+0x2c0>) 800fe9a: 6013 str r3, [r2, #0] 800fe9c: 4f81 ldr r7, [pc, #516] @ (80100a4 <_dtoa_r+0x2c4>) 800fe9e: f000 bccb b.w 8010838 <_dtoa_r+0xa58> 800fea2: aa0e add r2, sp, #56 @ 0x38 800fea4: a90f add r1, sp, #60 @ 0x3c 800fea6: 4648 mov r0, r9 800fea8: eeb0 0b48 vmov.f64 d0, d8 800feac: f001 f918 bl 80110e0 <__d2b> 800feb0: f3c6 530a ubfx r3, r6, #20, #11 800feb4: 9a0e ldr r2, [sp, #56] @ 0x38 800feb6: 9001 str r0, [sp, #4] 800feb8: 2b00 cmp r3, #0 800feba: d045 beq.n 800ff48 <_dtoa_r+0x168> 800febc: eeb0 7b48 vmov.f64 d7, d8 800fec0: ee18 1a90 vmov r1, s17 800fec4: f3c1 0113 ubfx r1, r1, #0, #20 800fec8: f041 517f orr.w r1, r1, #1069547520 @ 0x3fc00000 800fecc: f441 1140 orr.w r1, r1, #3145728 @ 0x300000 800fed0: f2a3 33ff subw r3, r3, #1023 @ 0x3ff 800fed4: 2500 movs r5, #0 800fed6: ee07 1a90 vmov s15, r1 800feda: eeb7 6b08 vmov.f64 d6, #120 @ 0x3fc00000 1.5 800fede: ed9f 5b66 vldr d5, [pc, #408] @ 8010078 <_dtoa_r+0x298> 800fee2: ee37 7b46 vsub.f64 d7, d7, d6 800fee6: ed9f 6b66 vldr d6, [pc, #408] @ 8010080 <_dtoa_r+0x2a0> 800feea: eea7 6b05 vfma.f64 d6, d7, d5 800feee: ed9f 5b66 vldr d5, [pc, #408] @ 8010088 <_dtoa_r+0x2a8> 800fef2: ee07 3a90 vmov s15, r3 800fef6: eeb8 4be7 vcvt.f64.s32 d4, s15 800fefa: eeb0 7b46 vmov.f64 d7, d6 800fefe: eea4 7b05 vfma.f64 d7, d4, d5 800ff02: eefd 6bc7 vcvt.s32.f64 s13, d7 800ff06: eeb5 7bc0 vcmpe.f64 d7, #0.0 800ff0a: eef1 fa10 vmrs APSR_nzcv, fpscr 800ff0e: ee16 8a90 vmov r8, s13 800ff12: d508 bpl.n 800ff26 <_dtoa_r+0x146> 800ff14: eeb8 6be6 vcvt.f64.s32 d6, s13 800ff18: eeb4 6b47 vcmp.f64 d6, d7 800ff1c: eef1 fa10 vmrs APSR_nzcv, fpscr 800ff20: bf18 it ne 800ff22: f108 38ff addne.w r8, r8, #4294967295 @ 0xffffffff 800ff26: f1b8 0f16 cmp.w r8, #22 800ff2a: d82b bhi.n 800ff84 <_dtoa_r+0x1a4> 800ff2c: 495e ldr r1, [pc, #376] @ (80100a8 <_dtoa_r+0x2c8>) 800ff2e: eb01 01c8 add.w r1, r1, r8, lsl #3 800ff32: ed91 7b00 vldr d7, [r1] 800ff36: eeb4 8bc7 vcmpe.f64 d8, d7 800ff3a: eef1 fa10 vmrs APSR_nzcv, fpscr 800ff3e: d501 bpl.n 800ff44 <_dtoa_r+0x164> 800ff40: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff 800ff44: 2100 movs r1, #0 800ff46: e01e b.n 800ff86 <_dtoa_r+0x1a6> 800ff48: 9b0f ldr r3, [sp, #60] @ 0x3c 800ff4a: 4413 add r3, r2 800ff4c: f203 4132 addw r1, r3, #1074 @ 0x432 800ff50: 2920 cmp r1, #32 800ff52: bfc1 itttt gt 800ff54: f1c1 0140 rsbgt r1, r1, #64 @ 0x40 800ff58: 408e lslgt r6, r1 800ff5a: f203 4112 addwgt r1, r3, #1042 @ 0x412 800ff5e: fa24 f101 lsrgt.w r1, r4, r1 800ff62: bfd6 itet le 800ff64: f1c1 0120 rsble r1, r1, #32 800ff68: 4331 orrgt r1, r6 800ff6a: fa04 f101 lslle.w r1, r4, r1 800ff6e: ee07 1a90 vmov s15, r1 800ff72: eeb8 7b67 vcvt.f64.u32 d7, s15 800ff76: 3b01 subs r3, #1 800ff78: ee17 1a90 vmov r1, s15 800ff7c: 2501 movs r5, #1 800ff7e: f1a1 71f8 sub.w r1, r1, #32505856 @ 0x1f00000 800ff82: e7a8 b.n 800fed6 <_dtoa_r+0xf6> 800ff84: 2101 movs r1, #1 800ff86: 1ad2 subs r2, r2, r3 800ff88: 1e53 subs r3, r2, #1 800ff8a: 9306 str r3, [sp, #24] 800ff8c: bf45 ittet mi 800ff8e: f1c2 0301 rsbmi r3, r2, #1 800ff92: 9305 strmi r3, [sp, #20] 800ff94: 2300 movpl r3, #0 800ff96: 2300 movmi r3, #0 800ff98: bf4c ite mi 800ff9a: 9306 strmi r3, [sp, #24] 800ff9c: 9305 strpl r3, [sp, #20] 800ff9e: f1b8 0f00 cmp.w r8, #0 800ffa2: 910c str r1, [sp, #48] @ 0x30 800ffa4: db18 blt.n 800ffd8 <_dtoa_r+0x1f8> 800ffa6: 9b06 ldr r3, [sp, #24] 800ffa8: f8cd 8028 str.w r8, [sp, #40] @ 0x28 800ffac: 4443 add r3, r8 800ffae: 9306 str r3, [sp, #24] 800ffb0: 2300 movs r3, #0 800ffb2: 9a07 ldr r2, [sp, #28] 800ffb4: 2a09 cmp r2, #9 800ffb6: d849 bhi.n 801004c <_dtoa_r+0x26c> 800ffb8: 2a05 cmp r2, #5 800ffba: bfc4 itt gt 800ffbc: 3a04 subgt r2, #4 800ffbe: 9207 strgt r2, [sp, #28] 800ffc0: 9a07 ldr r2, [sp, #28] 800ffc2: f1a2 0202 sub.w r2, r2, #2 800ffc6: bfcc ite gt 800ffc8: 2400 movgt r4, #0 800ffca: 2401 movle r4, #1 800ffcc: 2a03 cmp r2, #3 800ffce: d848 bhi.n 8010062 <_dtoa_r+0x282> 800ffd0: e8df f002 tbb [pc, r2] 800ffd4: 3a2c2e0b .word 0x3a2c2e0b 800ffd8: 9b05 ldr r3, [sp, #20] 800ffda: 2200 movs r2, #0 800ffdc: eba3 0308 sub.w r3, r3, r8 800ffe0: 9305 str r3, [sp, #20] 800ffe2: 920a str r2, [sp, #40] @ 0x28 800ffe4: f1c8 0300 rsb r3, r8, #0 800ffe8: e7e3 b.n 800ffb2 <_dtoa_r+0x1d2> 800ffea: 2200 movs r2, #0 800ffec: 9208 str r2, [sp, #32] 800ffee: 9a09 ldr r2, [sp, #36] @ 0x24 800fff0: 2a00 cmp r2, #0 800fff2: dc39 bgt.n 8010068 <_dtoa_r+0x288> 800fff4: f04f 0b01 mov.w fp, #1 800fff8: 46da mov sl, fp 800fffa: 465a mov r2, fp 800fffc: f8cd b024 str.w fp, [sp, #36] @ 0x24 8010000: f8d9 701c ldr.w r7, [r9, #28] 8010004: 2100 movs r1, #0 8010006: 2004 movs r0, #4 8010008: f100 0614 add.w r6, r0, #20 801000c: 4296 cmp r6, r2 801000e: d930 bls.n 8010072 <_dtoa_r+0x292> 8010010: 6079 str r1, [r7, #4] 8010012: 4648 mov r0, r9 8010014: 9304 str r3, [sp, #16] 8010016: f000 fd39 bl 8010a8c <_Balloc> 801001a: 9b04 ldr r3, [sp, #16] 801001c: 4607 mov r7, r0 801001e: 2800 cmp r0, #0 8010020: d146 bne.n 80100b0 <_dtoa_r+0x2d0> 8010022: 4b22 ldr r3, [pc, #136] @ (80100ac <_dtoa_r+0x2cc>) 8010024: 4602 mov r2, r0 8010026: f240 11af movw r1, #431 @ 0x1af 801002a: e6f2 b.n 800fe12 <_dtoa_r+0x32> 801002c: 2201 movs r2, #1 801002e: e7dd b.n 800ffec <_dtoa_r+0x20c> 8010030: 2200 movs r2, #0 8010032: 9208 str r2, [sp, #32] 8010034: 9a09 ldr r2, [sp, #36] @ 0x24 8010036: eb08 0b02 add.w fp, r8, r2 801003a: f10b 0a01 add.w sl, fp, #1 801003e: 4652 mov r2, sl 8010040: 2a01 cmp r2, #1 8010042: bfb8 it lt 8010044: 2201 movlt r2, #1 8010046: e7db b.n 8010000 <_dtoa_r+0x220> 8010048: 2201 movs r2, #1 801004a: e7f2 b.n 8010032 <_dtoa_r+0x252> 801004c: 2401 movs r4, #1 801004e: 2200 movs r2, #0 8010050: e9cd 2407 strd r2, r4, [sp, #28] 8010054: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff 8010058: 2100 movs r1, #0 801005a: 46da mov sl, fp 801005c: 2212 movs r2, #18 801005e: 9109 str r1, [sp, #36] @ 0x24 8010060: e7ce b.n 8010000 <_dtoa_r+0x220> 8010062: 2201 movs r2, #1 8010064: 9208 str r2, [sp, #32] 8010066: e7f5 b.n 8010054 <_dtoa_r+0x274> 8010068: f8dd b024 ldr.w fp, [sp, #36] @ 0x24 801006c: 46da mov sl, fp 801006e: 465a mov r2, fp 8010070: e7c6 b.n 8010000 <_dtoa_r+0x220> 8010072: 3101 adds r1, #1 8010074: 0040 lsls r0, r0, #1 8010076: e7c7 b.n 8010008 <_dtoa_r+0x228> 8010078: 636f4361 .word 0x636f4361 801007c: 3fd287a7 .word 0x3fd287a7 8010080: 8b60c8b3 .word 0x8b60c8b3 8010084: 3fc68a28 .word 0x3fc68a28 8010088: 509f79fb .word 0x509f79fb 801008c: 3fd34413 .word 0x3fd34413 8010090: 08011aad .word 0x08011aad 8010094: 08011ac4 .word 0x08011ac4 8010098: 7ff00000 .word 0x7ff00000 801009c: 08011aa9 .word 0x08011aa9 80100a0: 08011a7d .word 0x08011a7d 80100a4: 08011a7c .word 0x08011a7c 80100a8: 08011bc0 .word 0x08011bc0 80100ac: 08011b1c .word 0x08011b1c 80100b0: f8d9 201c ldr.w r2, [r9, #28] 80100b4: f1ba 0f0e cmp.w sl, #14 80100b8: 6010 str r0, [r2, #0] 80100ba: d86f bhi.n 801019c <_dtoa_r+0x3bc> 80100bc: 2c00 cmp r4, #0 80100be: d06d beq.n 801019c <_dtoa_r+0x3bc> 80100c0: f1b8 0f00 cmp.w r8, #0 80100c4: f340 80c2 ble.w 801024c <_dtoa_r+0x46c> 80100c8: 4aca ldr r2, [pc, #808] @ (80103f4 <_dtoa_r+0x614>) 80100ca: f008 010f and.w r1, r8, #15 80100ce: eb02 02c1 add.w r2, r2, r1, lsl #3 80100d2: f418 7f80 tst.w r8, #256 @ 0x100 80100d6: ed92 7b00 vldr d7, [r2] 80100da: ea4f 1128 mov.w r1, r8, asr #4 80100de: f000 80a9 beq.w 8010234 <_dtoa_r+0x454> 80100e2: 4ac5 ldr r2, [pc, #788] @ (80103f8 <_dtoa_r+0x618>) 80100e4: ed92 6b08 vldr d6, [r2, #32] 80100e8: ee88 6b06 vdiv.f64 d6, d8, d6 80100ec: ed8d 6b02 vstr d6, [sp, #8] 80100f0: f001 010f and.w r1, r1, #15 80100f4: 2203 movs r2, #3 80100f6: 48c0 ldr r0, [pc, #768] @ (80103f8 <_dtoa_r+0x618>) 80100f8: 2900 cmp r1, #0 80100fa: f040 809d bne.w 8010238 <_dtoa_r+0x458> 80100fe: ed9d 6b02 vldr d6, [sp, #8] 8010102: ee86 7b07 vdiv.f64 d7, d6, d7 8010106: ed8d 7b02 vstr d7, [sp, #8] 801010a: 990c ldr r1, [sp, #48] @ 0x30 801010c: ed9d 7b02 vldr d7, [sp, #8] 8010110: 2900 cmp r1, #0 8010112: f000 80c1 beq.w 8010298 <_dtoa_r+0x4b8> 8010116: eeb7 6b00 vmov.f64 d6, #112 @ 0x3f800000 1.0 801011a: eeb4 7bc6 vcmpe.f64 d7, d6 801011e: eef1 fa10 vmrs APSR_nzcv, fpscr 8010122: f140 80b9 bpl.w 8010298 <_dtoa_r+0x4b8> 8010126: f1ba 0f00 cmp.w sl, #0 801012a: f000 80b5 beq.w 8010298 <_dtoa_r+0x4b8> 801012e: f1bb 0f00 cmp.w fp, #0 8010132: dd31 ble.n 8010198 <_dtoa_r+0x3b8> 8010134: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 8010138: ee27 7b06 vmul.f64 d7, d7, d6 801013c: ed8d 7b02 vstr d7, [sp, #8] 8010140: f108 31ff add.w r1, r8, #4294967295 @ 0xffffffff 8010144: 9104 str r1, [sp, #16] 8010146: 3201 adds r2, #1 8010148: 465c mov r4, fp 801014a: ed9d 6b02 vldr d6, [sp, #8] 801014e: eeb1 5b0c vmov.f64 d5, #28 @ 0x40e00000 7.0 8010152: ee07 2a90 vmov s15, r2 8010156: eeb8 7be7 vcvt.f64.s32 d7, s15 801015a: eea7 5b06 vfma.f64 d5, d7, d6 801015e: ee15 2a90 vmov r2, s11 8010162: ec51 0b15 vmov r0, r1, d5 8010166: f1a2 7150 sub.w r1, r2, #54525952 @ 0x3400000 801016a: 2c00 cmp r4, #0 801016c: f040 8098 bne.w 80102a0 <_dtoa_r+0x4c0> 8010170: eeb1 7b04 vmov.f64 d7, #20 @ 0x40a00000 5.0 8010174: ee36 6b47 vsub.f64 d6, d6, d7 8010178: ec41 0b17 vmov d7, r0, r1 801017c: eeb4 6bc7 vcmpe.f64 d6, d7 8010180: eef1 fa10 vmrs APSR_nzcv, fpscr 8010184: f300 8261 bgt.w 801064a <_dtoa_r+0x86a> 8010188: eeb1 7b47 vneg.f64 d7, d7 801018c: eeb4 6bc7 vcmpe.f64 d6, d7 8010190: eef1 fa10 vmrs APSR_nzcv, fpscr 8010194: f100 80f5 bmi.w 8010382 <_dtoa_r+0x5a2> 8010198: ed8d 8b02 vstr d8, [sp, #8] 801019c: 9a0f ldr r2, [sp, #60] @ 0x3c 801019e: 2a00 cmp r2, #0 80101a0: f2c0 812c blt.w 80103fc <_dtoa_r+0x61c> 80101a4: f1b8 0f0e cmp.w r8, #14 80101a8: f300 8128 bgt.w 80103fc <_dtoa_r+0x61c> 80101ac: 4b91 ldr r3, [pc, #580] @ (80103f4 <_dtoa_r+0x614>) 80101ae: eb03 03c8 add.w r3, r3, r8, lsl #3 80101b2: ed93 6b00 vldr d6, [r3] 80101b6: 9b09 ldr r3, [sp, #36] @ 0x24 80101b8: 2b00 cmp r3, #0 80101ba: da03 bge.n 80101c4 <_dtoa_r+0x3e4> 80101bc: f1ba 0f00 cmp.w sl, #0 80101c0: f340 80d2 ble.w 8010368 <_dtoa_r+0x588> 80101c4: eeb2 4b04 vmov.f64 d4, #36 @ 0x41200000 10.0 80101c8: ed9d 7b02 vldr d7, [sp, #8] 80101cc: 463e mov r6, r7 80101ce: ee87 5b06 vdiv.f64 d5, d7, d6 80101d2: eebd 5bc5 vcvt.s32.f64 s10, d5 80101d6: ee15 3a10 vmov r3, s10 80101da: 3330 adds r3, #48 @ 0x30 80101dc: f806 3b01 strb.w r3, [r6], #1 80101e0: 1bf3 subs r3, r6, r7 80101e2: 459a cmp sl, r3 80101e4: eeb8 3bc5 vcvt.f64.s32 d3, s10 80101e8: eea3 7b46 vfms.f64 d7, d3, d6 80101ec: f040 80f8 bne.w 80103e0 <_dtoa_r+0x600> 80101f0: ee37 7b07 vadd.f64 d7, d7, d7 80101f4: eeb4 7bc6 vcmpe.f64 d7, d6 80101f8: eef1 fa10 vmrs APSR_nzcv, fpscr 80101fc: f300 80dd bgt.w 80103ba <_dtoa_r+0x5da> 8010200: eeb4 7b46 vcmp.f64 d7, d6 8010204: eef1 fa10 vmrs APSR_nzcv, fpscr 8010208: d104 bne.n 8010214 <_dtoa_r+0x434> 801020a: ee15 3a10 vmov r3, s10 801020e: 07db lsls r3, r3, #31 8010210: f100 80d3 bmi.w 80103ba <_dtoa_r+0x5da> 8010214: 9901 ldr r1, [sp, #4] 8010216: 4648 mov r0, r9 8010218: f000 fc78 bl 8010b0c <_Bfree> 801021c: 2300 movs r3, #0 801021e: 9a0d ldr r2, [sp, #52] @ 0x34 8010220: 7033 strb r3, [r6, #0] 8010222: f108 0301 add.w r3, r8, #1 8010226: 6013 str r3, [r2, #0] 8010228: 9b1d ldr r3, [sp, #116] @ 0x74 801022a: 2b00 cmp r3, #0 801022c: f000 8304 beq.w 8010838 <_dtoa_r+0xa58> 8010230: 601e str r6, [r3, #0] 8010232: e301 b.n 8010838 <_dtoa_r+0xa58> 8010234: 2202 movs r2, #2 8010236: e75e b.n 80100f6 <_dtoa_r+0x316> 8010238: 07cc lsls r4, r1, #31 801023a: d504 bpl.n 8010246 <_dtoa_r+0x466> 801023c: ed90 6b00 vldr d6, [r0] 8010240: 3201 adds r2, #1 8010242: ee27 7b06 vmul.f64 d7, d7, d6 8010246: 1049 asrs r1, r1, #1 8010248: 3008 adds r0, #8 801024a: e755 b.n 80100f8 <_dtoa_r+0x318> 801024c: d022 beq.n 8010294 <_dtoa_r+0x4b4> 801024e: f1c8 0100 rsb r1, r8, #0 8010252: 4a68 ldr r2, [pc, #416] @ (80103f4 <_dtoa_r+0x614>) 8010254: f001 000f and.w r0, r1, #15 8010258: eb02 02c0 add.w r2, r2, r0, lsl #3 801025c: ed92 7b00 vldr d7, [r2] 8010260: ee28 7b07 vmul.f64 d7, d8, d7 8010264: ed8d 7b02 vstr d7, [sp, #8] 8010268: 4863 ldr r0, [pc, #396] @ (80103f8 <_dtoa_r+0x618>) 801026a: 1109 asrs r1, r1, #4 801026c: 2400 movs r4, #0 801026e: 2202 movs r2, #2 8010270: b929 cbnz r1, 801027e <_dtoa_r+0x49e> 8010272: 2c00 cmp r4, #0 8010274: f43f af49 beq.w 801010a <_dtoa_r+0x32a> 8010278: ed8d 7b02 vstr d7, [sp, #8] 801027c: e745 b.n 801010a <_dtoa_r+0x32a> 801027e: 07ce lsls r6, r1, #31 8010280: d505 bpl.n 801028e <_dtoa_r+0x4ae> 8010282: ed90 6b00 vldr d6, [r0] 8010286: 3201 adds r2, #1 8010288: 2401 movs r4, #1 801028a: ee27 7b06 vmul.f64 d7, d7, d6 801028e: 1049 asrs r1, r1, #1 8010290: 3008 adds r0, #8 8010292: e7ed b.n 8010270 <_dtoa_r+0x490> 8010294: 2202 movs r2, #2 8010296: e738 b.n 801010a <_dtoa_r+0x32a> 8010298: f8cd 8010 str.w r8, [sp, #16] 801029c: 4654 mov r4, sl 801029e: e754 b.n 801014a <_dtoa_r+0x36a> 80102a0: 4a54 ldr r2, [pc, #336] @ (80103f4 <_dtoa_r+0x614>) 80102a2: eb02 02c4 add.w r2, r2, r4, lsl #3 80102a6: ed12 4b02 vldr d4, [r2, #-8] 80102aa: 9a08 ldr r2, [sp, #32] 80102ac: ec41 0b17 vmov d7, r0, r1 80102b0: 443c add r4, r7 80102b2: b34a cbz r2, 8010308 <_dtoa_r+0x528> 80102b4: eeb6 3b00 vmov.f64 d3, #96 @ 0x3f000000 0.5 80102b8: eeb7 2b00 vmov.f64 d2, #112 @ 0x3f800000 1.0 80102bc: 463e mov r6, r7 80102be: ee83 5b04 vdiv.f64 d5, d3, d4 80102c2: eeb2 3b04 vmov.f64 d3, #36 @ 0x41200000 10.0 80102c6: ee35 7b47 vsub.f64 d7, d5, d7 80102ca: eefd 4bc6 vcvt.s32.f64 s9, d6 80102ce: ee14 2a90 vmov r2, s9 80102d2: eeb8 5be4 vcvt.f64.s32 d5, s9 80102d6: 3230 adds r2, #48 @ 0x30 80102d8: ee36 6b45 vsub.f64 d6, d6, d5 80102dc: eeb4 6bc7 vcmpe.f64 d6, d7 80102e0: eef1 fa10 vmrs APSR_nzcv, fpscr 80102e4: f806 2b01 strb.w r2, [r6], #1 80102e8: d438 bmi.n 801035c <_dtoa_r+0x57c> 80102ea: ee32 5b46 vsub.f64 d5, d2, d6 80102ee: eeb4 5bc7 vcmpe.f64 d5, d7 80102f2: eef1 fa10 vmrs APSR_nzcv, fpscr 80102f6: d462 bmi.n 80103be <_dtoa_r+0x5de> 80102f8: 42a6 cmp r6, r4 80102fa: f43f af4d beq.w 8010198 <_dtoa_r+0x3b8> 80102fe: ee27 7b03 vmul.f64 d7, d7, d3 8010302: ee26 6b03 vmul.f64 d6, d6, d3 8010306: e7e0 b.n 80102ca <_dtoa_r+0x4ea> 8010308: 4621 mov r1, r4 801030a: 463e mov r6, r7 801030c: ee27 7b04 vmul.f64 d7, d7, d4 8010310: eeb2 3b04 vmov.f64 d3, #36 @ 0x41200000 10.0 8010314: eefd 4bc6 vcvt.s32.f64 s9, d6 8010318: ee14 2a90 vmov r2, s9 801031c: 3230 adds r2, #48 @ 0x30 801031e: f806 2b01 strb.w r2, [r6], #1 8010322: 42a6 cmp r6, r4 8010324: eeb8 5be4 vcvt.f64.s32 d5, s9 8010328: ee36 6b45 vsub.f64 d6, d6, d5 801032c: d119 bne.n 8010362 <_dtoa_r+0x582> 801032e: eeb6 5b00 vmov.f64 d5, #96 @ 0x3f000000 0.5 8010332: ee37 4b05 vadd.f64 d4, d7, d5 8010336: eeb4 6bc4 vcmpe.f64 d6, d4 801033a: eef1 fa10 vmrs APSR_nzcv, fpscr 801033e: dc3e bgt.n 80103be <_dtoa_r+0x5de> 8010340: ee35 5b47 vsub.f64 d5, d5, d7 8010344: eeb4 6bc5 vcmpe.f64 d6, d5 8010348: eef1 fa10 vmrs APSR_nzcv, fpscr 801034c: f57f af24 bpl.w 8010198 <_dtoa_r+0x3b8> 8010350: 460e mov r6, r1 8010352: 3901 subs r1, #1 8010354: f816 3c01 ldrb.w r3, [r6, #-1] 8010358: 2b30 cmp r3, #48 @ 0x30 801035a: d0f9 beq.n 8010350 <_dtoa_r+0x570> 801035c: f8dd 8010 ldr.w r8, [sp, #16] 8010360: e758 b.n 8010214 <_dtoa_r+0x434> 8010362: ee26 6b03 vmul.f64 d6, d6, d3 8010366: e7d5 b.n 8010314 <_dtoa_r+0x534> 8010368: d10b bne.n 8010382 <_dtoa_r+0x5a2> 801036a: eeb1 7b04 vmov.f64 d7, #20 @ 0x40a00000 5.0 801036e: ee26 6b07 vmul.f64 d6, d6, d7 8010372: ed9d 7b02 vldr d7, [sp, #8] 8010376: eeb4 6bc7 vcmpe.f64 d6, d7 801037a: eef1 fa10 vmrs APSR_nzcv, fpscr 801037e: f2c0 8161 blt.w 8010644 <_dtoa_r+0x864> 8010382: 2400 movs r4, #0 8010384: 4625 mov r5, r4 8010386: 9b09 ldr r3, [sp, #36] @ 0x24 8010388: 43db mvns r3, r3 801038a: 9304 str r3, [sp, #16] 801038c: 463e mov r6, r7 801038e: f04f 0800 mov.w r8, #0 8010392: 4621 mov r1, r4 8010394: 4648 mov r0, r9 8010396: f000 fbb9 bl 8010b0c <_Bfree> 801039a: 2d00 cmp r5, #0 801039c: d0de beq.n 801035c <_dtoa_r+0x57c> 801039e: f1b8 0f00 cmp.w r8, #0 80103a2: d005 beq.n 80103b0 <_dtoa_r+0x5d0> 80103a4: 45a8 cmp r8, r5 80103a6: d003 beq.n 80103b0 <_dtoa_r+0x5d0> 80103a8: 4641 mov r1, r8 80103aa: 4648 mov r0, r9 80103ac: f000 fbae bl 8010b0c <_Bfree> 80103b0: 4629 mov r1, r5 80103b2: 4648 mov r0, r9 80103b4: f000 fbaa bl 8010b0c <_Bfree> 80103b8: e7d0 b.n 801035c <_dtoa_r+0x57c> 80103ba: f8cd 8010 str.w r8, [sp, #16] 80103be: 4633 mov r3, r6 80103c0: 461e mov r6, r3 80103c2: f813 2d01 ldrb.w r2, [r3, #-1]! 80103c6: 2a39 cmp r2, #57 @ 0x39 80103c8: d106 bne.n 80103d8 <_dtoa_r+0x5f8> 80103ca: 429f cmp r7, r3 80103cc: d1f8 bne.n 80103c0 <_dtoa_r+0x5e0> 80103ce: 9a04 ldr r2, [sp, #16] 80103d0: 3201 adds r2, #1 80103d2: 9204 str r2, [sp, #16] 80103d4: 2230 movs r2, #48 @ 0x30 80103d6: 703a strb r2, [r7, #0] 80103d8: 781a ldrb r2, [r3, #0] 80103da: 3201 adds r2, #1 80103dc: 701a strb r2, [r3, #0] 80103de: e7bd b.n 801035c <_dtoa_r+0x57c> 80103e0: ee27 7b04 vmul.f64 d7, d7, d4 80103e4: eeb5 7b40 vcmp.f64 d7, #0.0 80103e8: eef1 fa10 vmrs APSR_nzcv, fpscr 80103ec: f47f aeef bne.w 80101ce <_dtoa_r+0x3ee> 80103f0: e710 b.n 8010214 <_dtoa_r+0x434> 80103f2: bf00 nop 80103f4: 08011bc0 .word 0x08011bc0 80103f8: 08011b98 .word 0x08011b98 80103fc: 9908 ldr r1, [sp, #32] 80103fe: 2900 cmp r1, #0 8010400: f000 80e3 beq.w 80105ca <_dtoa_r+0x7ea> 8010404: 9907 ldr r1, [sp, #28] 8010406: 2901 cmp r1, #1 8010408: f300 80c8 bgt.w 801059c <_dtoa_r+0x7bc> 801040c: 2d00 cmp r5, #0 801040e: f000 80c1 beq.w 8010594 <_dtoa_r+0x7b4> 8010412: f202 4233 addw r2, r2, #1075 @ 0x433 8010416: 9e05 ldr r6, [sp, #20] 8010418: 461c mov r4, r3 801041a: 9304 str r3, [sp, #16] 801041c: 9b05 ldr r3, [sp, #20] 801041e: 4413 add r3, r2 8010420: 9305 str r3, [sp, #20] 8010422: 9b06 ldr r3, [sp, #24] 8010424: 2101 movs r1, #1 8010426: 4413 add r3, r2 8010428: 4648 mov r0, r9 801042a: 9306 str r3, [sp, #24] 801042c: f000 fc22 bl 8010c74 <__i2b> 8010430: 9b04 ldr r3, [sp, #16] 8010432: 4605 mov r5, r0 8010434: b166 cbz r6, 8010450 <_dtoa_r+0x670> 8010436: 9a06 ldr r2, [sp, #24] 8010438: 2a00 cmp r2, #0 801043a: dd09 ble.n 8010450 <_dtoa_r+0x670> 801043c: 42b2 cmp r2, r6 801043e: 9905 ldr r1, [sp, #20] 8010440: bfa8 it ge 8010442: 4632 movge r2, r6 8010444: 1a89 subs r1, r1, r2 8010446: 9105 str r1, [sp, #20] 8010448: 9906 ldr r1, [sp, #24] 801044a: 1ab6 subs r6, r6, r2 801044c: 1a8a subs r2, r1, r2 801044e: 9206 str r2, [sp, #24] 8010450: b1fb cbz r3, 8010492 <_dtoa_r+0x6b2> 8010452: 9a08 ldr r2, [sp, #32] 8010454: 2a00 cmp r2, #0 8010456: f000 80bc beq.w 80105d2 <_dtoa_r+0x7f2> 801045a: b19c cbz r4, 8010484 <_dtoa_r+0x6a4> 801045c: 4629 mov r1, r5 801045e: 4622 mov r2, r4 8010460: 4648 mov r0, r9 8010462: 930b str r3, [sp, #44] @ 0x2c 8010464: f000 fcc6 bl 8010df4 <__pow5mult> 8010468: 9a01 ldr r2, [sp, #4] 801046a: 4601 mov r1, r0 801046c: 4605 mov r5, r0 801046e: 4648 mov r0, r9 8010470: f000 fc16 bl 8010ca0 <__multiply> 8010474: 9901 ldr r1, [sp, #4] 8010476: 9004 str r0, [sp, #16] 8010478: 4648 mov r0, r9 801047a: f000 fb47 bl 8010b0c <_Bfree> 801047e: 9a04 ldr r2, [sp, #16] 8010480: 9b0b ldr r3, [sp, #44] @ 0x2c 8010482: 9201 str r2, [sp, #4] 8010484: 1b1a subs r2, r3, r4 8010486: d004 beq.n 8010492 <_dtoa_r+0x6b2> 8010488: 9901 ldr r1, [sp, #4] 801048a: 4648 mov r0, r9 801048c: f000 fcb2 bl 8010df4 <__pow5mult> 8010490: 9001 str r0, [sp, #4] 8010492: 2101 movs r1, #1 8010494: 4648 mov r0, r9 8010496: f000 fbed bl 8010c74 <__i2b> 801049a: 9b0a ldr r3, [sp, #40] @ 0x28 801049c: 4604 mov r4, r0 801049e: 2b00 cmp r3, #0 80104a0: f000 81d0 beq.w 8010844 <_dtoa_r+0xa64> 80104a4: 461a mov r2, r3 80104a6: 4601 mov r1, r0 80104a8: 4648 mov r0, r9 80104aa: f000 fca3 bl 8010df4 <__pow5mult> 80104ae: 9b07 ldr r3, [sp, #28] 80104b0: 2b01 cmp r3, #1 80104b2: 4604 mov r4, r0 80104b4: f300 8095 bgt.w 80105e2 <_dtoa_r+0x802> 80104b8: 9b02 ldr r3, [sp, #8] 80104ba: 2b00 cmp r3, #0 80104bc: f040 808b bne.w 80105d6 <_dtoa_r+0x7f6> 80104c0: 9b03 ldr r3, [sp, #12] 80104c2: f3c3 0213 ubfx r2, r3, #0, #20 80104c6: 2a00 cmp r2, #0 80104c8: f040 8087 bne.w 80105da <_dtoa_r+0x7fa> 80104cc: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 80104d0: 0d12 lsrs r2, r2, #20 80104d2: 0512 lsls r2, r2, #20 80104d4: 2a00 cmp r2, #0 80104d6: f000 8082 beq.w 80105de <_dtoa_r+0x7fe> 80104da: 9b05 ldr r3, [sp, #20] 80104dc: 3301 adds r3, #1 80104de: 9305 str r3, [sp, #20] 80104e0: 9b06 ldr r3, [sp, #24] 80104e2: 3301 adds r3, #1 80104e4: 9306 str r3, [sp, #24] 80104e6: 2301 movs r3, #1 80104e8: 930b str r3, [sp, #44] @ 0x2c 80104ea: 9b0a ldr r3, [sp, #40] @ 0x28 80104ec: 2b00 cmp r3, #0 80104ee: f000 81af beq.w 8010850 <_dtoa_r+0xa70> 80104f2: 6922 ldr r2, [r4, #16] 80104f4: eb04 0282 add.w r2, r4, r2, lsl #2 80104f8: 6910 ldr r0, [r2, #16] 80104fa: f000 fb6f bl 8010bdc <__hi0bits> 80104fe: f1c0 0020 rsb r0, r0, #32 8010502: 9b06 ldr r3, [sp, #24] 8010504: 4418 add r0, r3 8010506: f010 001f ands.w r0, r0, #31 801050a: d076 beq.n 80105fa <_dtoa_r+0x81a> 801050c: f1c0 0220 rsb r2, r0, #32 8010510: 2a04 cmp r2, #4 8010512: dd69 ble.n 80105e8 <_dtoa_r+0x808> 8010514: 9b05 ldr r3, [sp, #20] 8010516: f1c0 001c rsb r0, r0, #28 801051a: 4403 add r3, r0 801051c: 9305 str r3, [sp, #20] 801051e: 9b06 ldr r3, [sp, #24] 8010520: 4406 add r6, r0 8010522: 4403 add r3, r0 8010524: 9306 str r3, [sp, #24] 8010526: 9b05 ldr r3, [sp, #20] 8010528: 2b00 cmp r3, #0 801052a: dd05 ble.n 8010538 <_dtoa_r+0x758> 801052c: 9901 ldr r1, [sp, #4] 801052e: 461a mov r2, r3 8010530: 4648 mov r0, r9 8010532: f000 fcb9 bl 8010ea8 <__lshift> 8010536: 9001 str r0, [sp, #4] 8010538: 9b06 ldr r3, [sp, #24] 801053a: 2b00 cmp r3, #0 801053c: dd05 ble.n 801054a <_dtoa_r+0x76a> 801053e: 4621 mov r1, r4 8010540: 461a mov r2, r3 8010542: 4648 mov r0, r9 8010544: f000 fcb0 bl 8010ea8 <__lshift> 8010548: 4604 mov r4, r0 801054a: 9b0c ldr r3, [sp, #48] @ 0x30 801054c: 2b00 cmp r3, #0 801054e: d056 beq.n 80105fe <_dtoa_r+0x81e> 8010550: 9801 ldr r0, [sp, #4] 8010552: 4621 mov r1, r4 8010554: f000 fd14 bl 8010f80 <__mcmp> 8010558: 2800 cmp r0, #0 801055a: da50 bge.n 80105fe <_dtoa_r+0x81e> 801055c: f108 33ff add.w r3, r8, #4294967295 @ 0xffffffff 8010560: 9304 str r3, [sp, #16] 8010562: 9901 ldr r1, [sp, #4] 8010564: 2300 movs r3, #0 8010566: 220a movs r2, #10 8010568: 4648 mov r0, r9 801056a: f000 faf1 bl 8010b50 <__multadd> 801056e: 9b08 ldr r3, [sp, #32] 8010570: 9001 str r0, [sp, #4] 8010572: 2b00 cmp r3, #0 8010574: f000 816e beq.w 8010854 <_dtoa_r+0xa74> 8010578: 4629 mov r1, r5 801057a: 2300 movs r3, #0 801057c: 220a movs r2, #10 801057e: 4648 mov r0, r9 8010580: f000 fae6 bl 8010b50 <__multadd> 8010584: f1bb 0f00 cmp.w fp, #0 8010588: 4605 mov r5, r0 801058a: dc64 bgt.n 8010656 <_dtoa_r+0x876> 801058c: 9b07 ldr r3, [sp, #28] 801058e: 2b02 cmp r3, #2 8010590: dc3e bgt.n 8010610 <_dtoa_r+0x830> 8010592: e060 b.n 8010656 <_dtoa_r+0x876> 8010594: 9a0e ldr r2, [sp, #56] @ 0x38 8010596: f1c2 0236 rsb r2, r2, #54 @ 0x36 801059a: e73c b.n 8010416 <_dtoa_r+0x636> 801059c: f10a 34ff add.w r4, sl, #4294967295 @ 0xffffffff 80105a0: 42a3 cmp r3, r4 80105a2: bfbf itttt lt 80105a4: 1ae2 sublt r2, r4, r3 80105a6: 9b0a ldrlt r3, [sp, #40] @ 0x28 80105a8: 189b addlt r3, r3, r2 80105aa: 930a strlt r3, [sp, #40] @ 0x28 80105ac: bfae itee ge 80105ae: 1b1c subge r4, r3, r4 80105b0: 4623 movlt r3, r4 80105b2: 2400 movlt r4, #0 80105b4: f1ba 0f00 cmp.w sl, #0 80105b8: bfb5 itete lt 80105ba: 9a05 ldrlt r2, [sp, #20] 80105bc: 9e05 ldrge r6, [sp, #20] 80105be: eba2 060a sublt.w r6, r2, sl 80105c2: 4652 movge r2, sl 80105c4: bfb8 it lt 80105c6: 2200 movlt r2, #0 80105c8: e727 b.n 801041a <_dtoa_r+0x63a> 80105ca: 9e05 ldr r6, [sp, #20] 80105cc: 9d08 ldr r5, [sp, #32] 80105ce: 461c mov r4, r3 80105d0: e730 b.n 8010434 <_dtoa_r+0x654> 80105d2: 461a mov r2, r3 80105d4: e758 b.n 8010488 <_dtoa_r+0x6a8> 80105d6: 2300 movs r3, #0 80105d8: e786 b.n 80104e8 <_dtoa_r+0x708> 80105da: 9b02 ldr r3, [sp, #8] 80105dc: e784 b.n 80104e8 <_dtoa_r+0x708> 80105de: 920b str r2, [sp, #44] @ 0x2c 80105e0: e783 b.n 80104ea <_dtoa_r+0x70a> 80105e2: 2300 movs r3, #0 80105e4: 930b str r3, [sp, #44] @ 0x2c 80105e6: e784 b.n 80104f2 <_dtoa_r+0x712> 80105e8: d09d beq.n 8010526 <_dtoa_r+0x746> 80105ea: 9b05 ldr r3, [sp, #20] 80105ec: 321c adds r2, #28 80105ee: 4413 add r3, r2 80105f0: 9305 str r3, [sp, #20] 80105f2: 9b06 ldr r3, [sp, #24] 80105f4: 4416 add r6, r2 80105f6: 4413 add r3, r2 80105f8: e794 b.n 8010524 <_dtoa_r+0x744> 80105fa: 4602 mov r2, r0 80105fc: e7f5 b.n 80105ea <_dtoa_r+0x80a> 80105fe: f1ba 0f00 cmp.w sl, #0 8010602: f8cd 8010 str.w r8, [sp, #16] 8010606: 46d3 mov fp, sl 8010608: dc21 bgt.n 801064e <_dtoa_r+0x86e> 801060a: 9b07 ldr r3, [sp, #28] 801060c: 2b02 cmp r3, #2 801060e: dd1e ble.n 801064e <_dtoa_r+0x86e> 8010610: f1bb 0f00 cmp.w fp, #0 8010614: f47f aeb7 bne.w 8010386 <_dtoa_r+0x5a6> 8010618: 4621 mov r1, r4 801061a: 465b mov r3, fp 801061c: 2205 movs r2, #5 801061e: 4648 mov r0, r9 8010620: f000 fa96 bl 8010b50 <__multadd> 8010624: 4601 mov r1, r0 8010626: 4604 mov r4, r0 8010628: 9801 ldr r0, [sp, #4] 801062a: f000 fca9 bl 8010f80 <__mcmp> 801062e: 2800 cmp r0, #0 8010630: f77f aea9 ble.w 8010386 <_dtoa_r+0x5a6> 8010634: 463e mov r6, r7 8010636: 2331 movs r3, #49 @ 0x31 8010638: f806 3b01 strb.w r3, [r6], #1 801063c: 9b04 ldr r3, [sp, #16] 801063e: 3301 adds r3, #1 8010640: 9304 str r3, [sp, #16] 8010642: e6a4 b.n 801038e <_dtoa_r+0x5ae> 8010644: f8cd 8010 str.w r8, [sp, #16] 8010648: 4654 mov r4, sl 801064a: 4625 mov r5, r4 801064c: e7f2 b.n 8010634 <_dtoa_r+0x854> 801064e: 9b08 ldr r3, [sp, #32] 8010650: 2b00 cmp r3, #0 8010652: f000 8103 beq.w 801085c <_dtoa_r+0xa7c> 8010656: 2e00 cmp r6, #0 8010658: dd05 ble.n 8010666 <_dtoa_r+0x886> 801065a: 4629 mov r1, r5 801065c: 4632 mov r2, r6 801065e: 4648 mov r0, r9 8010660: f000 fc22 bl 8010ea8 <__lshift> 8010664: 4605 mov r5, r0 8010666: 9b0b ldr r3, [sp, #44] @ 0x2c 8010668: 2b00 cmp r3, #0 801066a: d058 beq.n 801071e <_dtoa_r+0x93e> 801066c: 6869 ldr r1, [r5, #4] 801066e: 4648 mov r0, r9 8010670: f000 fa0c bl 8010a8c <_Balloc> 8010674: 4606 mov r6, r0 8010676: b928 cbnz r0, 8010684 <_dtoa_r+0x8a4> 8010678: 4b82 ldr r3, [pc, #520] @ (8010884 <_dtoa_r+0xaa4>) 801067a: 4602 mov r2, r0 801067c: f240 21ef movw r1, #751 @ 0x2ef 8010680: f7ff bbc7 b.w 800fe12 <_dtoa_r+0x32> 8010684: 692a ldr r2, [r5, #16] 8010686: 3202 adds r2, #2 8010688: 0092 lsls r2, r2, #2 801068a: f105 010c add.w r1, r5, #12 801068e: 300c adds r0, #12 8010690: f7ff fb0f bl 800fcb2 8010694: 2201 movs r2, #1 8010696: 4631 mov r1, r6 8010698: 4648 mov r0, r9 801069a: f000 fc05 bl 8010ea8 <__lshift> 801069e: 1c7b adds r3, r7, #1 80106a0: 9305 str r3, [sp, #20] 80106a2: eb07 030b add.w r3, r7, fp 80106a6: 9309 str r3, [sp, #36] @ 0x24 80106a8: 9b02 ldr r3, [sp, #8] 80106aa: f003 0301 and.w r3, r3, #1 80106ae: 46a8 mov r8, r5 80106b0: 9308 str r3, [sp, #32] 80106b2: 4605 mov r5, r0 80106b4: 9b05 ldr r3, [sp, #20] 80106b6: 9801 ldr r0, [sp, #4] 80106b8: 4621 mov r1, r4 80106ba: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff 80106be: f7ff fb06 bl 800fcce 80106c2: 4641 mov r1, r8 80106c4: 9002 str r0, [sp, #8] 80106c6: f100 0a30 add.w sl, r0, #48 @ 0x30 80106ca: 9801 ldr r0, [sp, #4] 80106cc: f000 fc58 bl 8010f80 <__mcmp> 80106d0: 462a mov r2, r5 80106d2: 9006 str r0, [sp, #24] 80106d4: 4621 mov r1, r4 80106d6: 4648 mov r0, r9 80106d8: f000 fc6e bl 8010fb8 <__mdiff> 80106dc: 68c2 ldr r2, [r0, #12] 80106de: 4606 mov r6, r0 80106e0: b9fa cbnz r2, 8010722 <_dtoa_r+0x942> 80106e2: 4601 mov r1, r0 80106e4: 9801 ldr r0, [sp, #4] 80106e6: f000 fc4b bl 8010f80 <__mcmp> 80106ea: 4602 mov r2, r0 80106ec: 4631 mov r1, r6 80106ee: 4648 mov r0, r9 80106f0: 920a str r2, [sp, #40] @ 0x28 80106f2: f000 fa0b bl 8010b0c <_Bfree> 80106f6: 9b07 ldr r3, [sp, #28] 80106f8: 9a0a ldr r2, [sp, #40] @ 0x28 80106fa: 9e05 ldr r6, [sp, #20] 80106fc: ea43 0102 orr.w r1, r3, r2 8010700: 9b08 ldr r3, [sp, #32] 8010702: 4319 orrs r1, r3 8010704: d10f bne.n 8010726 <_dtoa_r+0x946> 8010706: f1ba 0f39 cmp.w sl, #57 @ 0x39 801070a: d028 beq.n 801075e <_dtoa_r+0x97e> 801070c: 9b06 ldr r3, [sp, #24] 801070e: 2b00 cmp r3, #0 8010710: dd02 ble.n 8010718 <_dtoa_r+0x938> 8010712: 9b02 ldr r3, [sp, #8] 8010714: f103 0a31 add.w sl, r3, #49 @ 0x31 8010718: f88b a000 strb.w sl, [fp] 801071c: e639 b.n 8010392 <_dtoa_r+0x5b2> 801071e: 4628 mov r0, r5 8010720: e7bd b.n 801069e <_dtoa_r+0x8be> 8010722: 2201 movs r2, #1 8010724: e7e2 b.n 80106ec <_dtoa_r+0x90c> 8010726: 9b06 ldr r3, [sp, #24] 8010728: 2b00 cmp r3, #0 801072a: db04 blt.n 8010736 <_dtoa_r+0x956> 801072c: 9907 ldr r1, [sp, #28] 801072e: 430b orrs r3, r1 8010730: 9908 ldr r1, [sp, #32] 8010732: 430b orrs r3, r1 8010734: d120 bne.n 8010778 <_dtoa_r+0x998> 8010736: 2a00 cmp r2, #0 8010738: ddee ble.n 8010718 <_dtoa_r+0x938> 801073a: 9901 ldr r1, [sp, #4] 801073c: 2201 movs r2, #1 801073e: 4648 mov r0, r9 8010740: f000 fbb2 bl 8010ea8 <__lshift> 8010744: 4621 mov r1, r4 8010746: 9001 str r0, [sp, #4] 8010748: f000 fc1a bl 8010f80 <__mcmp> 801074c: 2800 cmp r0, #0 801074e: dc03 bgt.n 8010758 <_dtoa_r+0x978> 8010750: d1e2 bne.n 8010718 <_dtoa_r+0x938> 8010752: f01a 0f01 tst.w sl, #1 8010756: d0df beq.n 8010718 <_dtoa_r+0x938> 8010758: f1ba 0f39 cmp.w sl, #57 @ 0x39 801075c: d1d9 bne.n 8010712 <_dtoa_r+0x932> 801075e: 2339 movs r3, #57 @ 0x39 8010760: f88b 3000 strb.w r3, [fp] 8010764: 4633 mov r3, r6 8010766: 461e mov r6, r3 8010768: 3b01 subs r3, #1 801076a: f816 2c01 ldrb.w r2, [r6, #-1] 801076e: 2a39 cmp r2, #57 @ 0x39 8010770: d053 beq.n 801081a <_dtoa_r+0xa3a> 8010772: 3201 adds r2, #1 8010774: 701a strb r2, [r3, #0] 8010776: e60c b.n 8010392 <_dtoa_r+0x5b2> 8010778: 2a00 cmp r2, #0 801077a: dd07 ble.n 801078c <_dtoa_r+0x9ac> 801077c: f1ba 0f39 cmp.w sl, #57 @ 0x39 8010780: d0ed beq.n 801075e <_dtoa_r+0x97e> 8010782: f10a 0301 add.w r3, sl, #1 8010786: f88b 3000 strb.w r3, [fp] 801078a: e602 b.n 8010392 <_dtoa_r+0x5b2> 801078c: 9b05 ldr r3, [sp, #20] 801078e: 9a05 ldr r2, [sp, #20] 8010790: f803 ac01 strb.w sl, [r3, #-1] 8010794: 9b09 ldr r3, [sp, #36] @ 0x24 8010796: 4293 cmp r3, r2 8010798: d029 beq.n 80107ee <_dtoa_r+0xa0e> 801079a: 9901 ldr r1, [sp, #4] 801079c: 2300 movs r3, #0 801079e: 220a movs r2, #10 80107a0: 4648 mov r0, r9 80107a2: f000 f9d5 bl 8010b50 <__multadd> 80107a6: 45a8 cmp r8, r5 80107a8: 9001 str r0, [sp, #4] 80107aa: f04f 0300 mov.w r3, #0 80107ae: f04f 020a mov.w r2, #10 80107b2: 4641 mov r1, r8 80107b4: 4648 mov r0, r9 80107b6: d107 bne.n 80107c8 <_dtoa_r+0x9e8> 80107b8: f000 f9ca bl 8010b50 <__multadd> 80107bc: 4680 mov r8, r0 80107be: 4605 mov r5, r0 80107c0: 9b05 ldr r3, [sp, #20] 80107c2: 3301 adds r3, #1 80107c4: 9305 str r3, [sp, #20] 80107c6: e775 b.n 80106b4 <_dtoa_r+0x8d4> 80107c8: f000 f9c2 bl 8010b50 <__multadd> 80107cc: 4629 mov r1, r5 80107ce: 4680 mov r8, r0 80107d0: 2300 movs r3, #0 80107d2: 220a movs r2, #10 80107d4: 4648 mov r0, r9 80107d6: f000 f9bb bl 8010b50 <__multadd> 80107da: 4605 mov r5, r0 80107dc: e7f0 b.n 80107c0 <_dtoa_r+0x9e0> 80107de: f1bb 0f00 cmp.w fp, #0 80107e2: bfcc ite gt 80107e4: 465e movgt r6, fp 80107e6: 2601 movle r6, #1 80107e8: 443e add r6, r7 80107ea: f04f 0800 mov.w r8, #0 80107ee: 9901 ldr r1, [sp, #4] 80107f0: 2201 movs r2, #1 80107f2: 4648 mov r0, r9 80107f4: f000 fb58 bl 8010ea8 <__lshift> 80107f8: 4621 mov r1, r4 80107fa: 9001 str r0, [sp, #4] 80107fc: f000 fbc0 bl 8010f80 <__mcmp> 8010800: 2800 cmp r0, #0 8010802: dcaf bgt.n 8010764 <_dtoa_r+0x984> 8010804: d102 bne.n 801080c <_dtoa_r+0xa2c> 8010806: f01a 0f01 tst.w sl, #1 801080a: d1ab bne.n 8010764 <_dtoa_r+0x984> 801080c: 4633 mov r3, r6 801080e: 461e mov r6, r3 8010810: f813 2d01 ldrb.w r2, [r3, #-1]! 8010814: 2a30 cmp r2, #48 @ 0x30 8010816: d0fa beq.n 801080e <_dtoa_r+0xa2e> 8010818: e5bb b.n 8010392 <_dtoa_r+0x5b2> 801081a: 429f cmp r7, r3 801081c: d1a3 bne.n 8010766 <_dtoa_r+0x986> 801081e: 9b04 ldr r3, [sp, #16] 8010820: 3301 adds r3, #1 8010822: 9304 str r3, [sp, #16] 8010824: 2331 movs r3, #49 @ 0x31 8010826: 703b strb r3, [r7, #0] 8010828: e5b3 b.n 8010392 <_dtoa_r+0x5b2> 801082a: 9b1d ldr r3, [sp, #116] @ 0x74 801082c: 4f16 ldr r7, [pc, #88] @ (8010888 <_dtoa_r+0xaa8>) 801082e: b11b cbz r3, 8010838 <_dtoa_r+0xa58> 8010830: f107 0308 add.w r3, r7, #8 8010834: 9a1d ldr r2, [sp, #116] @ 0x74 8010836: 6013 str r3, [r2, #0] 8010838: 4638 mov r0, r7 801083a: b011 add sp, #68 @ 0x44 801083c: ecbd 8b02 vpop {d8} 8010840: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8010844: 9b07 ldr r3, [sp, #28] 8010846: 2b01 cmp r3, #1 8010848: f77f ae36 ble.w 80104b8 <_dtoa_r+0x6d8> 801084c: 9b0a ldr r3, [sp, #40] @ 0x28 801084e: 930b str r3, [sp, #44] @ 0x2c 8010850: 2001 movs r0, #1 8010852: e656 b.n 8010502 <_dtoa_r+0x722> 8010854: f1bb 0f00 cmp.w fp, #0 8010858: f77f aed7 ble.w 801060a <_dtoa_r+0x82a> 801085c: 463e mov r6, r7 801085e: 9801 ldr r0, [sp, #4] 8010860: 4621 mov r1, r4 8010862: f7ff fa34 bl 800fcce 8010866: f100 0a30 add.w sl, r0, #48 @ 0x30 801086a: f806 ab01 strb.w sl, [r6], #1 801086e: 1bf2 subs r2, r6, r7 8010870: 4593 cmp fp, r2 8010872: ddb4 ble.n 80107de <_dtoa_r+0x9fe> 8010874: 9901 ldr r1, [sp, #4] 8010876: 2300 movs r3, #0 8010878: 220a movs r2, #10 801087a: 4648 mov r0, r9 801087c: f000 f968 bl 8010b50 <__multadd> 8010880: 9001 str r0, [sp, #4] 8010882: e7ec b.n 801085e <_dtoa_r+0xa7e> 8010884: 08011b1c .word 0x08011b1c 8010888: 08011aa0 .word 0x08011aa0 0801088c <_free_r>: 801088c: b538 push {r3, r4, r5, lr} 801088e: 4605 mov r5, r0 8010890: 2900 cmp r1, #0 8010892: d041 beq.n 8010918 <_free_r+0x8c> 8010894: f851 3c04 ldr.w r3, [r1, #-4] 8010898: 1f0c subs r4, r1, #4 801089a: 2b00 cmp r3, #0 801089c: bfb8 it lt 801089e: 18e4 addlt r4, r4, r3 80108a0: f000 f8e8 bl 8010a74 <__malloc_lock> 80108a4: 4a1d ldr r2, [pc, #116] @ (801091c <_free_r+0x90>) 80108a6: 6813 ldr r3, [r2, #0] 80108a8: b933 cbnz r3, 80108b8 <_free_r+0x2c> 80108aa: 6063 str r3, [r4, #4] 80108ac: 6014 str r4, [r2, #0] 80108ae: 4628 mov r0, r5 80108b0: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 80108b4: f000 b8e4 b.w 8010a80 <__malloc_unlock> 80108b8: 42a3 cmp r3, r4 80108ba: d908 bls.n 80108ce <_free_r+0x42> 80108bc: 6820 ldr r0, [r4, #0] 80108be: 1821 adds r1, r4, r0 80108c0: 428b cmp r3, r1 80108c2: bf01 itttt eq 80108c4: 6819 ldreq r1, [r3, #0] 80108c6: 685b ldreq r3, [r3, #4] 80108c8: 1809 addeq r1, r1, r0 80108ca: 6021 streq r1, [r4, #0] 80108cc: e7ed b.n 80108aa <_free_r+0x1e> 80108ce: 461a mov r2, r3 80108d0: 685b ldr r3, [r3, #4] 80108d2: b10b cbz r3, 80108d8 <_free_r+0x4c> 80108d4: 42a3 cmp r3, r4 80108d6: d9fa bls.n 80108ce <_free_r+0x42> 80108d8: 6811 ldr r1, [r2, #0] 80108da: 1850 adds r0, r2, r1 80108dc: 42a0 cmp r0, r4 80108de: d10b bne.n 80108f8 <_free_r+0x6c> 80108e0: 6820 ldr r0, [r4, #0] 80108e2: 4401 add r1, r0 80108e4: 1850 adds r0, r2, r1 80108e6: 4283 cmp r3, r0 80108e8: 6011 str r1, [r2, #0] 80108ea: d1e0 bne.n 80108ae <_free_r+0x22> 80108ec: 6818 ldr r0, [r3, #0] 80108ee: 685b ldr r3, [r3, #4] 80108f0: 6053 str r3, [r2, #4] 80108f2: 4408 add r0, r1 80108f4: 6010 str r0, [r2, #0] 80108f6: e7da b.n 80108ae <_free_r+0x22> 80108f8: d902 bls.n 8010900 <_free_r+0x74> 80108fa: 230c movs r3, #12 80108fc: 602b str r3, [r5, #0] 80108fe: e7d6 b.n 80108ae <_free_r+0x22> 8010900: 6820 ldr r0, [r4, #0] 8010902: 1821 adds r1, r4, r0 8010904: 428b cmp r3, r1 8010906: bf04 itt eq 8010908: 6819 ldreq r1, [r3, #0] 801090a: 685b ldreq r3, [r3, #4] 801090c: 6063 str r3, [r4, #4] 801090e: bf04 itt eq 8010910: 1809 addeq r1, r1, r0 8010912: 6021 streq r1, [r4, #0] 8010914: 6054 str r4, [r2, #4] 8010916: e7ca b.n 80108ae <_free_r+0x22> 8010918: bd38 pop {r3, r4, r5, pc} 801091a: bf00 nop 801091c: 240132e0 .word 0x240132e0 08010920 : 8010920: 4b02 ldr r3, [pc, #8] @ (801092c ) 8010922: 4601 mov r1, r0 8010924: 6818 ldr r0, [r3, #0] 8010926: f000 b825 b.w 8010974 <_malloc_r> 801092a: bf00 nop 801092c: 24000054 .word 0x24000054 08010930 : 8010930: b570 push {r4, r5, r6, lr} 8010932: 4e0f ldr r6, [pc, #60] @ (8010970 ) 8010934: 460c mov r4, r1 8010936: 6831 ldr r1, [r6, #0] 8010938: 4605 mov r5, r0 801093a: b911 cbnz r1, 8010942 801093c: f000 fd58 bl 80113f0 <_sbrk_r> 8010940: 6030 str r0, [r6, #0] 8010942: 4621 mov r1, r4 8010944: 4628 mov r0, r5 8010946: f000 fd53 bl 80113f0 <_sbrk_r> 801094a: 1c43 adds r3, r0, #1 801094c: d103 bne.n 8010956 801094e: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8010952: 4620 mov r0, r4 8010954: bd70 pop {r4, r5, r6, pc} 8010956: 1cc4 adds r4, r0, #3 8010958: f024 0403 bic.w r4, r4, #3 801095c: 42a0 cmp r0, r4 801095e: d0f8 beq.n 8010952 8010960: 1a21 subs r1, r4, r0 8010962: 4628 mov r0, r5 8010964: f000 fd44 bl 80113f0 <_sbrk_r> 8010968: 3001 adds r0, #1 801096a: d1f2 bne.n 8010952 801096c: e7ef b.n 801094e 801096e: bf00 nop 8010970: 240132dc .word 0x240132dc 08010974 <_malloc_r>: 8010974: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8010978: 1ccd adds r5, r1, #3 801097a: f025 0503 bic.w r5, r5, #3 801097e: 3508 adds r5, #8 8010980: 2d0c cmp r5, #12 8010982: bf38 it cc 8010984: 250c movcc r5, #12 8010986: 2d00 cmp r5, #0 8010988: 4606 mov r6, r0 801098a: db01 blt.n 8010990 <_malloc_r+0x1c> 801098c: 42a9 cmp r1, r5 801098e: d904 bls.n 801099a <_malloc_r+0x26> 8010990: 230c movs r3, #12 8010992: 6033 str r3, [r6, #0] 8010994: 2000 movs r0, #0 8010996: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 801099a: f8df 80d4 ldr.w r8, [pc, #212] @ 8010a70 <_malloc_r+0xfc> 801099e: f000 f869 bl 8010a74 <__malloc_lock> 80109a2: f8d8 3000 ldr.w r3, [r8] 80109a6: 461c mov r4, r3 80109a8: bb44 cbnz r4, 80109fc <_malloc_r+0x88> 80109aa: 4629 mov r1, r5 80109ac: 4630 mov r0, r6 80109ae: f7ff ffbf bl 8010930 80109b2: 1c43 adds r3, r0, #1 80109b4: 4604 mov r4, r0 80109b6: d158 bne.n 8010a6a <_malloc_r+0xf6> 80109b8: f8d8 4000 ldr.w r4, [r8] 80109bc: 4627 mov r7, r4 80109be: 2f00 cmp r7, #0 80109c0: d143 bne.n 8010a4a <_malloc_r+0xd6> 80109c2: 2c00 cmp r4, #0 80109c4: d04b beq.n 8010a5e <_malloc_r+0xea> 80109c6: 6823 ldr r3, [r4, #0] 80109c8: 4639 mov r1, r7 80109ca: 4630 mov r0, r6 80109cc: eb04 0903 add.w r9, r4, r3 80109d0: f000 fd0e bl 80113f0 <_sbrk_r> 80109d4: 4581 cmp r9, r0 80109d6: d142 bne.n 8010a5e <_malloc_r+0xea> 80109d8: 6821 ldr r1, [r4, #0] 80109da: 1a6d subs r5, r5, r1 80109dc: 4629 mov r1, r5 80109de: 4630 mov r0, r6 80109e0: f7ff ffa6 bl 8010930 80109e4: 3001 adds r0, #1 80109e6: d03a beq.n 8010a5e <_malloc_r+0xea> 80109e8: 6823 ldr r3, [r4, #0] 80109ea: 442b add r3, r5 80109ec: 6023 str r3, [r4, #0] 80109ee: f8d8 3000 ldr.w r3, [r8] 80109f2: 685a ldr r2, [r3, #4] 80109f4: bb62 cbnz r2, 8010a50 <_malloc_r+0xdc> 80109f6: f8c8 7000 str.w r7, [r8] 80109fa: e00f b.n 8010a1c <_malloc_r+0xa8> 80109fc: 6822 ldr r2, [r4, #0] 80109fe: 1b52 subs r2, r2, r5 8010a00: d420 bmi.n 8010a44 <_malloc_r+0xd0> 8010a02: 2a0b cmp r2, #11 8010a04: d917 bls.n 8010a36 <_malloc_r+0xc2> 8010a06: 1961 adds r1, r4, r5 8010a08: 42a3 cmp r3, r4 8010a0a: 6025 str r5, [r4, #0] 8010a0c: bf18 it ne 8010a0e: 6059 strne r1, [r3, #4] 8010a10: 6863 ldr r3, [r4, #4] 8010a12: bf08 it eq 8010a14: f8c8 1000 streq.w r1, [r8] 8010a18: 5162 str r2, [r4, r5] 8010a1a: 604b str r3, [r1, #4] 8010a1c: 4630 mov r0, r6 8010a1e: f000 f82f bl 8010a80 <__malloc_unlock> 8010a22: f104 000b add.w r0, r4, #11 8010a26: 1d23 adds r3, r4, #4 8010a28: f020 0007 bic.w r0, r0, #7 8010a2c: 1ac2 subs r2, r0, r3 8010a2e: bf1c itt ne 8010a30: 1a1b subne r3, r3, r0 8010a32: 50a3 strne r3, [r4, r2] 8010a34: e7af b.n 8010996 <_malloc_r+0x22> 8010a36: 6862 ldr r2, [r4, #4] 8010a38: 42a3 cmp r3, r4 8010a3a: bf0c ite eq 8010a3c: f8c8 2000 streq.w r2, [r8] 8010a40: 605a strne r2, [r3, #4] 8010a42: e7eb b.n 8010a1c <_malloc_r+0xa8> 8010a44: 4623 mov r3, r4 8010a46: 6864 ldr r4, [r4, #4] 8010a48: e7ae b.n 80109a8 <_malloc_r+0x34> 8010a4a: 463c mov r4, r7 8010a4c: 687f ldr r7, [r7, #4] 8010a4e: e7b6 b.n 80109be <_malloc_r+0x4a> 8010a50: 461a mov r2, r3 8010a52: 685b ldr r3, [r3, #4] 8010a54: 42a3 cmp r3, r4 8010a56: d1fb bne.n 8010a50 <_malloc_r+0xdc> 8010a58: 2300 movs r3, #0 8010a5a: 6053 str r3, [r2, #4] 8010a5c: e7de b.n 8010a1c <_malloc_r+0xa8> 8010a5e: 230c movs r3, #12 8010a60: 6033 str r3, [r6, #0] 8010a62: 4630 mov r0, r6 8010a64: f000 f80c bl 8010a80 <__malloc_unlock> 8010a68: e794 b.n 8010994 <_malloc_r+0x20> 8010a6a: 6005 str r5, [r0, #0] 8010a6c: e7d6 b.n 8010a1c <_malloc_r+0xa8> 8010a6e: bf00 nop 8010a70: 240132e0 .word 0x240132e0 08010a74 <__malloc_lock>: 8010a74: 4801 ldr r0, [pc, #4] @ (8010a7c <__malloc_lock+0x8>) 8010a76: f7ff b91a b.w 800fcae <__retarget_lock_acquire_recursive> 8010a7a: bf00 nop 8010a7c: 240132d8 .word 0x240132d8 08010a80 <__malloc_unlock>: 8010a80: 4801 ldr r0, [pc, #4] @ (8010a88 <__malloc_unlock+0x8>) 8010a82: f7ff b915 b.w 800fcb0 <__retarget_lock_release_recursive> 8010a86: bf00 nop 8010a88: 240132d8 .word 0x240132d8 08010a8c <_Balloc>: 8010a8c: b570 push {r4, r5, r6, lr} 8010a8e: 69c6 ldr r6, [r0, #28] 8010a90: 4604 mov r4, r0 8010a92: 460d mov r5, r1 8010a94: b976 cbnz r6, 8010ab4 <_Balloc+0x28> 8010a96: 2010 movs r0, #16 8010a98: f7ff ff42 bl 8010920 8010a9c: 4602 mov r2, r0 8010a9e: 61e0 str r0, [r4, #28] 8010aa0: b920 cbnz r0, 8010aac <_Balloc+0x20> 8010aa2: 4b18 ldr r3, [pc, #96] @ (8010b04 <_Balloc+0x78>) 8010aa4: 4818 ldr r0, [pc, #96] @ (8010b08 <_Balloc+0x7c>) 8010aa6: 216b movs r1, #107 @ 0x6b 8010aa8: f000 fcb2 bl 8011410 <__assert_func> 8010aac: e9c0 6601 strd r6, r6, [r0, #4] 8010ab0: 6006 str r6, [r0, #0] 8010ab2: 60c6 str r6, [r0, #12] 8010ab4: 69e6 ldr r6, [r4, #28] 8010ab6: 68f3 ldr r3, [r6, #12] 8010ab8: b183 cbz r3, 8010adc <_Balloc+0x50> 8010aba: 69e3 ldr r3, [r4, #28] 8010abc: 68db ldr r3, [r3, #12] 8010abe: f853 0025 ldr.w r0, [r3, r5, lsl #2] 8010ac2: b9b8 cbnz r0, 8010af4 <_Balloc+0x68> 8010ac4: 2101 movs r1, #1 8010ac6: fa01 f605 lsl.w r6, r1, r5 8010aca: 1d72 adds r2, r6, #5 8010acc: 0092 lsls r2, r2, #2 8010ace: 4620 mov r0, r4 8010ad0: f000 fcbc bl 801144c <_calloc_r> 8010ad4: b160 cbz r0, 8010af0 <_Balloc+0x64> 8010ad6: e9c0 5601 strd r5, r6, [r0, #4] 8010ada: e00e b.n 8010afa <_Balloc+0x6e> 8010adc: 2221 movs r2, #33 @ 0x21 8010ade: 2104 movs r1, #4 8010ae0: 4620 mov r0, r4 8010ae2: f000 fcb3 bl 801144c <_calloc_r> 8010ae6: 69e3 ldr r3, [r4, #28] 8010ae8: 60f0 str r0, [r6, #12] 8010aea: 68db ldr r3, [r3, #12] 8010aec: 2b00 cmp r3, #0 8010aee: d1e4 bne.n 8010aba <_Balloc+0x2e> 8010af0: 2000 movs r0, #0 8010af2: bd70 pop {r4, r5, r6, pc} 8010af4: 6802 ldr r2, [r0, #0] 8010af6: f843 2025 str.w r2, [r3, r5, lsl #2] 8010afa: 2300 movs r3, #0 8010afc: e9c0 3303 strd r3, r3, [r0, #12] 8010b00: e7f7 b.n 8010af2 <_Balloc+0x66> 8010b02: bf00 nop 8010b04: 08011aad .word 0x08011aad 8010b08: 08011b2d .word 0x08011b2d 08010b0c <_Bfree>: 8010b0c: b570 push {r4, r5, r6, lr} 8010b0e: 69c6 ldr r6, [r0, #28] 8010b10: 4605 mov r5, r0 8010b12: 460c mov r4, r1 8010b14: b976 cbnz r6, 8010b34 <_Bfree+0x28> 8010b16: 2010 movs r0, #16 8010b18: f7ff ff02 bl 8010920 8010b1c: 4602 mov r2, r0 8010b1e: 61e8 str r0, [r5, #28] 8010b20: b920 cbnz r0, 8010b2c <_Bfree+0x20> 8010b22: 4b09 ldr r3, [pc, #36] @ (8010b48 <_Bfree+0x3c>) 8010b24: 4809 ldr r0, [pc, #36] @ (8010b4c <_Bfree+0x40>) 8010b26: 218f movs r1, #143 @ 0x8f 8010b28: f000 fc72 bl 8011410 <__assert_func> 8010b2c: e9c0 6601 strd r6, r6, [r0, #4] 8010b30: 6006 str r6, [r0, #0] 8010b32: 60c6 str r6, [r0, #12] 8010b34: b13c cbz r4, 8010b46 <_Bfree+0x3a> 8010b36: 69eb ldr r3, [r5, #28] 8010b38: 6862 ldr r2, [r4, #4] 8010b3a: 68db ldr r3, [r3, #12] 8010b3c: f853 1022 ldr.w r1, [r3, r2, lsl #2] 8010b40: 6021 str r1, [r4, #0] 8010b42: f843 4022 str.w r4, [r3, r2, lsl #2] 8010b46: bd70 pop {r4, r5, r6, pc} 8010b48: 08011aad .word 0x08011aad 8010b4c: 08011b2d .word 0x08011b2d 08010b50 <__multadd>: 8010b50: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8010b54: 690d ldr r5, [r1, #16] 8010b56: 4607 mov r7, r0 8010b58: 460c mov r4, r1 8010b5a: 461e mov r6, r3 8010b5c: f101 0c14 add.w ip, r1, #20 8010b60: 2000 movs r0, #0 8010b62: f8dc 3000 ldr.w r3, [ip] 8010b66: b299 uxth r1, r3 8010b68: fb02 6101 mla r1, r2, r1, r6 8010b6c: 0c1e lsrs r6, r3, #16 8010b6e: 0c0b lsrs r3, r1, #16 8010b70: fb02 3306 mla r3, r2, r6, r3 8010b74: b289 uxth r1, r1 8010b76: 3001 adds r0, #1 8010b78: eb01 4103 add.w r1, r1, r3, lsl #16 8010b7c: 4285 cmp r5, r0 8010b7e: f84c 1b04 str.w r1, [ip], #4 8010b82: ea4f 4613 mov.w r6, r3, lsr #16 8010b86: dcec bgt.n 8010b62 <__multadd+0x12> 8010b88: b30e cbz r6, 8010bce <__multadd+0x7e> 8010b8a: 68a3 ldr r3, [r4, #8] 8010b8c: 42ab cmp r3, r5 8010b8e: dc19 bgt.n 8010bc4 <__multadd+0x74> 8010b90: 6861 ldr r1, [r4, #4] 8010b92: 4638 mov r0, r7 8010b94: 3101 adds r1, #1 8010b96: f7ff ff79 bl 8010a8c <_Balloc> 8010b9a: 4680 mov r8, r0 8010b9c: b928 cbnz r0, 8010baa <__multadd+0x5a> 8010b9e: 4602 mov r2, r0 8010ba0: 4b0c ldr r3, [pc, #48] @ (8010bd4 <__multadd+0x84>) 8010ba2: 480d ldr r0, [pc, #52] @ (8010bd8 <__multadd+0x88>) 8010ba4: 21ba movs r1, #186 @ 0xba 8010ba6: f000 fc33 bl 8011410 <__assert_func> 8010baa: 6922 ldr r2, [r4, #16] 8010bac: 3202 adds r2, #2 8010bae: f104 010c add.w r1, r4, #12 8010bb2: 0092 lsls r2, r2, #2 8010bb4: 300c adds r0, #12 8010bb6: f7ff f87c bl 800fcb2 8010bba: 4621 mov r1, r4 8010bbc: 4638 mov r0, r7 8010bbe: f7ff ffa5 bl 8010b0c <_Bfree> 8010bc2: 4644 mov r4, r8 8010bc4: eb04 0385 add.w r3, r4, r5, lsl #2 8010bc8: 3501 adds r5, #1 8010bca: 615e str r6, [r3, #20] 8010bcc: 6125 str r5, [r4, #16] 8010bce: 4620 mov r0, r4 8010bd0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 8010bd4: 08011b1c .word 0x08011b1c 8010bd8: 08011b2d .word 0x08011b2d 08010bdc <__hi0bits>: 8010bdc: f5b0 3f80 cmp.w r0, #65536 @ 0x10000 8010be0: 4603 mov r3, r0 8010be2: bf36 itet cc 8010be4: 0403 lslcc r3, r0, #16 8010be6: 2000 movcs r0, #0 8010be8: 2010 movcc r0, #16 8010bea: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8010bee: bf3c itt cc 8010bf0: 021b lslcc r3, r3, #8 8010bf2: 3008 addcc r0, #8 8010bf4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8010bf8: bf3c itt cc 8010bfa: 011b lslcc r3, r3, #4 8010bfc: 3004 addcc r0, #4 8010bfe: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010c02: bf3c itt cc 8010c04: 009b lslcc r3, r3, #2 8010c06: 3002 addcc r0, #2 8010c08: 2b00 cmp r3, #0 8010c0a: db05 blt.n 8010c18 <__hi0bits+0x3c> 8010c0c: f013 4f80 tst.w r3, #1073741824 @ 0x40000000 8010c10: f100 0001 add.w r0, r0, #1 8010c14: bf08 it eq 8010c16: 2020 moveq r0, #32 8010c18: 4770 bx lr 08010c1a <__lo0bits>: 8010c1a: 6803 ldr r3, [r0, #0] 8010c1c: 4602 mov r2, r0 8010c1e: f013 0007 ands.w r0, r3, #7 8010c22: d00b beq.n 8010c3c <__lo0bits+0x22> 8010c24: 07d9 lsls r1, r3, #31 8010c26: d421 bmi.n 8010c6c <__lo0bits+0x52> 8010c28: 0798 lsls r0, r3, #30 8010c2a: bf49 itett mi 8010c2c: 085b lsrmi r3, r3, #1 8010c2e: 089b lsrpl r3, r3, #2 8010c30: 2001 movmi r0, #1 8010c32: 6013 strmi r3, [r2, #0] 8010c34: bf5c itt pl 8010c36: 6013 strpl r3, [r2, #0] 8010c38: 2002 movpl r0, #2 8010c3a: 4770 bx lr 8010c3c: b299 uxth r1, r3 8010c3e: b909 cbnz r1, 8010c44 <__lo0bits+0x2a> 8010c40: 0c1b lsrs r3, r3, #16 8010c42: 2010 movs r0, #16 8010c44: b2d9 uxtb r1, r3 8010c46: b909 cbnz r1, 8010c4c <__lo0bits+0x32> 8010c48: 3008 adds r0, #8 8010c4a: 0a1b lsrs r3, r3, #8 8010c4c: 0719 lsls r1, r3, #28 8010c4e: bf04 itt eq 8010c50: 091b lsreq r3, r3, #4 8010c52: 3004 addeq r0, #4 8010c54: 0799 lsls r1, r3, #30 8010c56: bf04 itt eq 8010c58: 089b lsreq r3, r3, #2 8010c5a: 3002 addeq r0, #2 8010c5c: 07d9 lsls r1, r3, #31 8010c5e: d403 bmi.n 8010c68 <__lo0bits+0x4e> 8010c60: 085b lsrs r3, r3, #1 8010c62: f100 0001 add.w r0, r0, #1 8010c66: d003 beq.n 8010c70 <__lo0bits+0x56> 8010c68: 6013 str r3, [r2, #0] 8010c6a: 4770 bx lr 8010c6c: 2000 movs r0, #0 8010c6e: 4770 bx lr 8010c70: 2020 movs r0, #32 8010c72: 4770 bx lr 08010c74 <__i2b>: 8010c74: b510 push {r4, lr} 8010c76: 460c mov r4, r1 8010c78: 2101 movs r1, #1 8010c7a: f7ff ff07 bl 8010a8c <_Balloc> 8010c7e: 4602 mov r2, r0 8010c80: b928 cbnz r0, 8010c8e <__i2b+0x1a> 8010c82: 4b05 ldr r3, [pc, #20] @ (8010c98 <__i2b+0x24>) 8010c84: 4805 ldr r0, [pc, #20] @ (8010c9c <__i2b+0x28>) 8010c86: f240 1145 movw r1, #325 @ 0x145 8010c8a: f000 fbc1 bl 8011410 <__assert_func> 8010c8e: 2301 movs r3, #1 8010c90: 6144 str r4, [r0, #20] 8010c92: 6103 str r3, [r0, #16] 8010c94: bd10 pop {r4, pc} 8010c96: bf00 nop 8010c98: 08011b1c .word 0x08011b1c 8010c9c: 08011b2d .word 0x08011b2d 08010ca0 <__multiply>: 8010ca0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8010ca4: 4614 mov r4, r2 8010ca6: 690a ldr r2, [r1, #16] 8010ca8: 6923 ldr r3, [r4, #16] 8010caa: 429a cmp r2, r3 8010cac: bfa8 it ge 8010cae: 4623 movge r3, r4 8010cb0: 460f mov r7, r1 8010cb2: bfa4 itt ge 8010cb4: 460c movge r4, r1 8010cb6: 461f movge r7, r3 8010cb8: f8d4 a010 ldr.w sl, [r4, #16] 8010cbc: f8d7 9010 ldr.w r9, [r7, #16] 8010cc0: 68a3 ldr r3, [r4, #8] 8010cc2: 6861 ldr r1, [r4, #4] 8010cc4: eb0a 0609 add.w r6, sl, r9 8010cc8: 42b3 cmp r3, r6 8010cca: b085 sub sp, #20 8010ccc: bfb8 it lt 8010cce: 3101 addlt r1, #1 8010cd0: f7ff fedc bl 8010a8c <_Balloc> 8010cd4: b930 cbnz r0, 8010ce4 <__multiply+0x44> 8010cd6: 4602 mov r2, r0 8010cd8: 4b44 ldr r3, [pc, #272] @ (8010dec <__multiply+0x14c>) 8010cda: 4845 ldr r0, [pc, #276] @ (8010df0 <__multiply+0x150>) 8010cdc: f44f 71b1 mov.w r1, #354 @ 0x162 8010ce0: f000 fb96 bl 8011410 <__assert_func> 8010ce4: f100 0514 add.w r5, r0, #20 8010ce8: eb05 0886 add.w r8, r5, r6, lsl #2 8010cec: 462b mov r3, r5 8010cee: 2200 movs r2, #0 8010cf0: 4543 cmp r3, r8 8010cf2: d321 bcc.n 8010d38 <__multiply+0x98> 8010cf4: f107 0114 add.w r1, r7, #20 8010cf8: f104 0214 add.w r2, r4, #20 8010cfc: eb02 028a add.w r2, r2, sl, lsl #2 8010d00: eb01 0389 add.w r3, r1, r9, lsl #2 8010d04: 9302 str r3, [sp, #8] 8010d06: 1b13 subs r3, r2, r4 8010d08: 3b15 subs r3, #21 8010d0a: f023 0303 bic.w r3, r3, #3 8010d0e: 3304 adds r3, #4 8010d10: f104 0715 add.w r7, r4, #21 8010d14: 42ba cmp r2, r7 8010d16: bf38 it cc 8010d18: 2304 movcc r3, #4 8010d1a: 9301 str r3, [sp, #4] 8010d1c: 9b02 ldr r3, [sp, #8] 8010d1e: 9103 str r1, [sp, #12] 8010d20: 428b cmp r3, r1 8010d22: d80c bhi.n 8010d3e <__multiply+0x9e> 8010d24: 2e00 cmp r6, #0 8010d26: dd03 ble.n 8010d30 <__multiply+0x90> 8010d28: f858 3d04 ldr.w r3, [r8, #-4]! 8010d2c: 2b00 cmp r3, #0 8010d2e: d05b beq.n 8010de8 <__multiply+0x148> 8010d30: 6106 str r6, [r0, #16] 8010d32: b005 add sp, #20 8010d34: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8010d38: f843 2b04 str.w r2, [r3], #4 8010d3c: e7d8 b.n 8010cf0 <__multiply+0x50> 8010d3e: f8b1 a000 ldrh.w sl, [r1] 8010d42: f1ba 0f00 cmp.w sl, #0 8010d46: d024 beq.n 8010d92 <__multiply+0xf2> 8010d48: f104 0e14 add.w lr, r4, #20 8010d4c: 46a9 mov r9, r5 8010d4e: f04f 0c00 mov.w ip, #0 8010d52: f85e 7b04 ldr.w r7, [lr], #4 8010d56: f8d9 3000 ldr.w r3, [r9] 8010d5a: fa1f fb87 uxth.w fp, r7 8010d5e: b29b uxth r3, r3 8010d60: fb0a 330b mla r3, sl, fp, r3 8010d64: ea4f 4b17 mov.w fp, r7, lsr #16 8010d68: f8d9 7000 ldr.w r7, [r9] 8010d6c: 4463 add r3, ip 8010d6e: ea4f 4c17 mov.w ip, r7, lsr #16 8010d72: fb0a c70b mla r7, sl, fp, ip 8010d76: eb07 4713 add.w r7, r7, r3, lsr #16 8010d7a: b29b uxth r3, r3 8010d7c: ea43 4307 orr.w r3, r3, r7, lsl #16 8010d80: 4572 cmp r2, lr 8010d82: f849 3b04 str.w r3, [r9], #4 8010d86: ea4f 4c17 mov.w ip, r7, lsr #16 8010d8a: d8e2 bhi.n 8010d52 <__multiply+0xb2> 8010d8c: 9b01 ldr r3, [sp, #4] 8010d8e: f845 c003 str.w ip, [r5, r3] 8010d92: 9b03 ldr r3, [sp, #12] 8010d94: f8b3 9002 ldrh.w r9, [r3, #2] 8010d98: 3104 adds r1, #4 8010d9a: f1b9 0f00 cmp.w r9, #0 8010d9e: d021 beq.n 8010de4 <__multiply+0x144> 8010da0: 682b ldr r3, [r5, #0] 8010da2: f104 0c14 add.w ip, r4, #20 8010da6: 46ae mov lr, r5 8010da8: f04f 0a00 mov.w sl, #0 8010dac: f8bc b000 ldrh.w fp, [ip] 8010db0: f8be 7002 ldrh.w r7, [lr, #2] 8010db4: fb09 770b mla r7, r9, fp, r7 8010db8: 4457 add r7, sl 8010dba: b29b uxth r3, r3 8010dbc: ea43 4307 orr.w r3, r3, r7, lsl #16 8010dc0: f84e 3b04 str.w r3, [lr], #4 8010dc4: f85c 3b04 ldr.w r3, [ip], #4 8010dc8: ea4f 4a13 mov.w sl, r3, lsr #16 8010dcc: f8be 3000 ldrh.w r3, [lr] 8010dd0: fb09 330a mla r3, r9, sl, r3 8010dd4: eb03 4317 add.w r3, r3, r7, lsr #16 8010dd8: 4562 cmp r2, ip 8010dda: ea4f 4a13 mov.w sl, r3, lsr #16 8010dde: d8e5 bhi.n 8010dac <__multiply+0x10c> 8010de0: 9f01 ldr r7, [sp, #4] 8010de2: 51eb str r3, [r5, r7] 8010de4: 3504 adds r5, #4 8010de6: e799 b.n 8010d1c <__multiply+0x7c> 8010de8: 3e01 subs r6, #1 8010dea: e79b b.n 8010d24 <__multiply+0x84> 8010dec: 08011b1c .word 0x08011b1c 8010df0: 08011b2d .word 0x08011b2d 08010df4 <__pow5mult>: 8010df4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8010df8: 4615 mov r5, r2 8010dfa: f012 0203 ands.w r2, r2, #3 8010dfe: 4607 mov r7, r0 8010e00: 460e mov r6, r1 8010e02: d007 beq.n 8010e14 <__pow5mult+0x20> 8010e04: 4c25 ldr r4, [pc, #148] @ (8010e9c <__pow5mult+0xa8>) 8010e06: 3a01 subs r2, #1 8010e08: 2300 movs r3, #0 8010e0a: f854 2022 ldr.w r2, [r4, r2, lsl #2] 8010e0e: f7ff fe9f bl 8010b50 <__multadd> 8010e12: 4606 mov r6, r0 8010e14: 10ad asrs r5, r5, #2 8010e16: d03d beq.n 8010e94 <__pow5mult+0xa0> 8010e18: 69fc ldr r4, [r7, #28] 8010e1a: b97c cbnz r4, 8010e3c <__pow5mult+0x48> 8010e1c: 2010 movs r0, #16 8010e1e: f7ff fd7f bl 8010920 8010e22: 4602 mov r2, r0 8010e24: 61f8 str r0, [r7, #28] 8010e26: b928 cbnz r0, 8010e34 <__pow5mult+0x40> 8010e28: 4b1d ldr r3, [pc, #116] @ (8010ea0 <__pow5mult+0xac>) 8010e2a: 481e ldr r0, [pc, #120] @ (8010ea4 <__pow5mult+0xb0>) 8010e2c: f240 11b3 movw r1, #435 @ 0x1b3 8010e30: f000 faee bl 8011410 <__assert_func> 8010e34: e9c0 4401 strd r4, r4, [r0, #4] 8010e38: 6004 str r4, [r0, #0] 8010e3a: 60c4 str r4, [r0, #12] 8010e3c: f8d7 801c ldr.w r8, [r7, #28] 8010e40: f8d8 4008 ldr.w r4, [r8, #8] 8010e44: b94c cbnz r4, 8010e5a <__pow5mult+0x66> 8010e46: f240 2171 movw r1, #625 @ 0x271 8010e4a: 4638 mov r0, r7 8010e4c: f7ff ff12 bl 8010c74 <__i2b> 8010e50: 2300 movs r3, #0 8010e52: f8c8 0008 str.w r0, [r8, #8] 8010e56: 4604 mov r4, r0 8010e58: 6003 str r3, [r0, #0] 8010e5a: f04f 0900 mov.w r9, #0 8010e5e: 07eb lsls r3, r5, #31 8010e60: d50a bpl.n 8010e78 <__pow5mult+0x84> 8010e62: 4631 mov r1, r6 8010e64: 4622 mov r2, r4 8010e66: 4638 mov r0, r7 8010e68: f7ff ff1a bl 8010ca0 <__multiply> 8010e6c: 4631 mov r1, r6 8010e6e: 4680 mov r8, r0 8010e70: 4638 mov r0, r7 8010e72: f7ff fe4b bl 8010b0c <_Bfree> 8010e76: 4646 mov r6, r8 8010e78: 106d asrs r5, r5, #1 8010e7a: d00b beq.n 8010e94 <__pow5mult+0xa0> 8010e7c: 6820 ldr r0, [r4, #0] 8010e7e: b938 cbnz r0, 8010e90 <__pow5mult+0x9c> 8010e80: 4622 mov r2, r4 8010e82: 4621 mov r1, r4 8010e84: 4638 mov r0, r7 8010e86: f7ff ff0b bl 8010ca0 <__multiply> 8010e8a: 6020 str r0, [r4, #0] 8010e8c: f8c0 9000 str.w r9, [r0] 8010e90: 4604 mov r4, r0 8010e92: e7e4 b.n 8010e5e <__pow5mult+0x6a> 8010e94: 4630 mov r0, r6 8010e96: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8010e9a: bf00 nop 8010e9c: 08011b88 .word 0x08011b88 8010ea0: 08011aad .word 0x08011aad 8010ea4: 08011b2d .word 0x08011b2d 08010ea8 <__lshift>: 8010ea8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8010eac: 460c mov r4, r1 8010eae: 6849 ldr r1, [r1, #4] 8010eb0: 6923 ldr r3, [r4, #16] 8010eb2: eb03 1862 add.w r8, r3, r2, asr #5 8010eb6: 68a3 ldr r3, [r4, #8] 8010eb8: 4607 mov r7, r0 8010eba: 4691 mov r9, r2 8010ebc: ea4f 1a62 mov.w sl, r2, asr #5 8010ec0: f108 0601 add.w r6, r8, #1 8010ec4: 42b3 cmp r3, r6 8010ec6: db0b blt.n 8010ee0 <__lshift+0x38> 8010ec8: 4638 mov r0, r7 8010eca: f7ff fddf bl 8010a8c <_Balloc> 8010ece: 4605 mov r5, r0 8010ed0: b948 cbnz r0, 8010ee6 <__lshift+0x3e> 8010ed2: 4602 mov r2, r0 8010ed4: 4b28 ldr r3, [pc, #160] @ (8010f78 <__lshift+0xd0>) 8010ed6: 4829 ldr r0, [pc, #164] @ (8010f7c <__lshift+0xd4>) 8010ed8: f44f 71ef mov.w r1, #478 @ 0x1de 8010edc: f000 fa98 bl 8011410 <__assert_func> 8010ee0: 3101 adds r1, #1 8010ee2: 005b lsls r3, r3, #1 8010ee4: e7ee b.n 8010ec4 <__lshift+0x1c> 8010ee6: 2300 movs r3, #0 8010ee8: f100 0114 add.w r1, r0, #20 8010eec: f100 0210 add.w r2, r0, #16 8010ef0: 4618 mov r0, r3 8010ef2: 4553 cmp r3, sl 8010ef4: db33 blt.n 8010f5e <__lshift+0xb6> 8010ef6: 6920 ldr r0, [r4, #16] 8010ef8: ea2a 7aea bic.w sl, sl, sl, asr #31 8010efc: f104 0314 add.w r3, r4, #20 8010f00: f019 091f ands.w r9, r9, #31 8010f04: eb01 018a add.w r1, r1, sl, lsl #2 8010f08: eb03 0c80 add.w ip, r3, r0, lsl #2 8010f0c: d02b beq.n 8010f66 <__lshift+0xbe> 8010f0e: f1c9 0e20 rsb lr, r9, #32 8010f12: 468a mov sl, r1 8010f14: 2200 movs r2, #0 8010f16: 6818 ldr r0, [r3, #0] 8010f18: fa00 f009 lsl.w r0, r0, r9 8010f1c: 4310 orrs r0, r2 8010f1e: f84a 0b04 str.w r0, [sl], #4 8010f22: f853 2b04 ldr.w r2, [r3], #4 8010f26: 459c cmp ip, r3 8010f28: fa22 f20e lsr.w r2, r2, lr 8010f2c: d8f3 bhi.n 8010f16 <__lshift+0x6e> 8010f2e: ebac 0304 sub.w r3, ip, r4 8010f32: 3b15 subs r3, #21 8010f34: f023 0303 bic.w r3, r3, #3 8010f38: 3304 adds r3, #4 8010f3a: f104 0015 add.w r0, r4, #21 8010f3e: 4584 cmp ip, r0 8010f40: bf38 it cc 8010f42: 2304 movcc r3, #4 8010f44: 50ca str r2, [r1, r3] 8010f46: b10a cbz r2, 8010f4c <__lshift+0xa4> 8010f48: f108 0602 add.w r6, r8, #2 8010f4c: 3e01 subs r6, #1 8010f4e: 4638 mov r0, r7 8010f50: 612e str r6, [r5, #16] 8010f52: 4621 mov r1, r4 8010f54: f7ff fdda bl 8010b0c <_Bfree> 8010f58: 4628 mov r0, r5 8010f5a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8010f5e: f842 0f04 str.w r0, [r2, #4]! 8010f62: 3301 adds r3, #1 8010f64: e7c5 b.n 8010ef2 <__lshift+0x4a> 8010f66: 3904 subs r1, #4 8010f68: f853 2b04 ldr.w r2, [r3], #4 8010f6c: f841 2f04 str.w r2, [r1, #4]! 8010f70: 459c cmp ip, r3 8010f72: d8f9 bhi.n 8010f68 <__lshift+0xc0> 8010f74: e7ea b.n 8010f4c <__lshift+0xa4> 8010f76: bf00 nop 8010f78: 08011b1c .word 0x08011b1c 8010f7c: 08011b2d .word 0x08011b2d 08010f80 <__mcmp>: 8010f80: 690a ldr r2, [r1, #16] 8010f82: 4603 mov r3, r0 8010f84: 6900 ldr r0, [r0, #16] 8010f86: 1a80 subs r0, r0, r2 8010f88: b530 push {r4, r5, lr} 8010f8a: d10e bne.n 8010faa <__mcmp+0x2a> 8010f8c: 3314 adds r3, #20 8010f8e: 3114 adds r1, #20 8010f90: eb03 0482 add.w r4, r3, r2, lsl #2 8010f94: eb01 0182 add.w r1, r1, r2, lsl #2 8010f98: f854 5d04 ldr.w r5, [r4, #-4]! 8010f9c: f851 2d04 ldr.w r2, [r1, #-4]! 8010fa0: 4295 cmp r5, r2 8010fa2: d003 beq.n 8010fac <__mcmp+0x2c> 8010fa4: d205 bcs.n 8010fb2 <__mcmp+0x32> 8010fa6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8010faa: bd30 pop {r4, r5, pc} 8010fac: 42a3 cmp r3, r4 8010fae: d3f3 bcc.n 8010f98 <__mcmp+0x18> 8010fb0: e7fb b.n 8010faa <__mcmp+0x2a> 8010fb2: 2001 movs r0, #1 8010fb4: e7f9 b.n 8010faa <__mcmp+0x2a> ... 08010fb8 <__mdiff>: 8010fb8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} 8010fbc: 4689 mov r9, r1 8010fbe: 4606 mov r6, r0 8010fc0: 4611 mov r1, r2 8010fc2: 4648 mov r0, r9 8010fc4: 4614 mov r4, r2 8010fc6: f7ff ffdb bl 8010f80 <__mcmp> 8010fca: 1e05 subs r5, r0, #0 8010fcc: d112 bne.n 8010ff4 <__mdiff+0x3c> 8010fce: 4629 mov r1, r5 8010fd0: 4630 mov r0, r6 8010fd2: f7ff fd5b bl 8010a8c <_Balloc> 8010fd6: 4602 mov r2, r0 8010fd8: b928 cbnz r0, 8010fe6 <__mdiff+0x2e> 8010fda: 4b3f ldr r3, [pc, #252] @ (80110d8 <__mdiff+0x120>) 8010fdc: f240 2137 movw r1, #567 @ 0x237 8010fe0: 483e ldr r0, [pc, #248] @ (80110dc <__mdiff+0x124>) 8010fe2: f000 fa15 bl 8011410 <__assert_func> 8010fe6: 2301 movs r3, #1 8010fe8: e9c0 3504 strd r3, r5, [r0, #16] 8010fec: 4610 mov r0, r2 8010fee: b003 add sp, #12 8010ff0: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8010ff4: bfbc itt lt 8010ff6: 464b movlt r3, r9 8010ff8: 46a1 movlt r9, r4 8010ffa: 4630 mov r0, r6 8010ffc: f8d9 1004 ldr.w r1, [r9, #4] 8011000: bfba itte lt 8011002: 461c movlt r4, r3 8011004: 2501 movlt r5, #1 8011006: 2500 movge r5, #0 8011008: f7ff fd40 bl 8010a8c <_Balloc> 801100c: 4602 mov r2, r0 801100e: b918 cbnz r0, 8011018 <__mdiff+0x60> 8011010: 4b31 ldr r3, [pc, #196] @ (80110d8 <__mdiff+0x120>) 8011012: f240 2145 movw r1, #581 @ 0x245 8011016: e7e3 b.n 8010fe0 <__mdiff+0x28> 8011018: f8d9 7010 ldr.w r7, [r9, #16] 801101c: 6926 ldr r6, [r4, #16] 801101e: 60c5 str r5, [r0, #12] 8011020: f109 0310 add.w r3, r9, #16 8011024: f109 0514 add.w r5, r9, #20 8011028: f104 0e14 add.w lr, r4, #20 801102c: f100 0b14 add.w fp, r0, #20 8011030: eb05 0887 add.w r8, r5, r7, lsl #2 8011034: eb0e 0686 add.w r6, lr, r6, lsl #2 8011038: 9301 str r3, [sp, #4] 801103a: 46d9 mov r9, fp 801103c: f04f 0c00 mov.w ip, #0 8011040: 9b01 ldr r3, [sp, #4] 8011042: f85e 0b04 ldr.w r0, [lr], #4 8011046: f853 af04 ldr.w sl, [r3, #4]! 801104a: 9301 str r3, [sp, #4] 801104c: fa1f f38a uxth.w r3, sl 8011050: 4619 mov r1, r3 8011052: b283 uxth r3, r0 8011054: 1acb subs r3, r1, r3 8011056: 0c00 lsrs r0, r0, #16 8011058: 4463 add r3, ip 801105a: ebc0 401a rsb r0, r0, sl, lsr #16 801105e: eb00 4023 add.w r0, r0, r3, asr #16 8011062: b29b uxth r3, r3 8011064: ea43 4300 orr.w r3, r3, r0, lsl #16 8011068: 4576 cmp r6, lr 801106a: f849 3b04 str.w r3, [r9], #4 801106e: ea4f 4c20 mov.w ip, r0, asr #16 8011072: d8e5 bhi.n 8011040 <__mdiff+0x88> 8011074: 1b33 subs r3, r6, r4 8011076: 3b15 subs r3, #21 8011078: f023 0303 bic.w r3, r3, #3 801107c: 3415 adds r4, #21 801107e: 3304 adds r3, #4 8011080: 42a6 cmp r6, r4 8011082: bf38 it cc 8011084: 2304 movcc r3, #4 8011086: 441d add r5, r3 8011088: 445b add r3, fp 801108a: 461e mov r6, r3 801108c: 462c mov r4, r5 801108e: 4544 cmp r4, r8 8011090: d30e bcc.n 80110b0 <__mdiff+0xf8> 8011092: f108 0103 add.w r1, r8, #3 8011096: 1b49 subs r1, r1, r5 8011098: f021 0103 bic.w r1, r1, #3 801109c: 3d03 subs r5, #3 801109e: 45a8 cmp r8, r5 80110a0: bf38 it cc 80110a2: 2100 movcc r1, #0 80110a4: 440b add r3, r1 80110a6: f853 1d04 ldr.w r1, [r3, #-4]! 80110aa: b191 cbz r1, 80110d2 <__mdiff+0x11a> 80110ac: 6117 str r7, [r2, #16] 80110ae: e79d b.n 8010fec <__mdiff+0x34> 80110b0: f854 1b04 ldr.w r1, [r4], #4 80110b4: 46e6 mov lr, ip 80110b6: 0c08 lsrs r0, r1, #16 80110b8: fa1c fc81 uxtah ip, ip, r1 80110bc: 4471 add r1, lr 80110be: eb00 402c add.w r0, r0, ip, asr #16 80110c2: b289 uxth r1, r1 80110c4: ea41 4100 orr.w r1, r1, r0, lsl #16 80110c8: f846 1b04 str.w r1, [r6], #4 80110cc: ea4f 4c20 mov.w ip, r0, asr #16 80110d0: e7dd b.n 801108e <__mdiff+0xd6> 80110d2: 3f01 subs r7, #1 80110d4: e7e7 b.n 80110a6 <__mdiff+0xee> 80110d6: bf00 nop 80110d8: 08011b1c .word 0x08011b1c 80110dc: 08011b2d .word 0x08011b2d 080110e0 <__d2b>: 80110e0: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} 80110e4: 460f mov r7, r1 80110e6: 2101 movs r1, #1 80110e8: ec59 8b10 vmov r8, r9, d0 80110ec: 4616 mov r6, r2 80110ee: f7ff fccd bl 8010a8c <_Balloc> 80110f2: 4604 mov r4, r0 80110f4: b930 cbnz r0, 8011104 <__d2b+0x24> 80110f6: 4602 mov r2, r0 80110f8: 4b23 ldr r3, [pc, #140] @ (8011188 <__d2b+0xa8>) 80110fa: 4824 ldr r0, [pc, #144] @ (801118c <__d2b+0xac>) 80110fc: f240 310f movw r1, #783 @ 0x30f 8011100: f000 f986 bl 8011410 <__assert_func> 8011104: f3c9 550a ubfx r5, r9, #20, #11 8011108: f3c9 0313 ubfx r3, r9, #0, #20 801110c: b10d cbz r5, 8011112 <__d2b+0x32> 801110e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8011112: 9301 str r3, [sp, #4] 8011114: f1b8 0300 subs.w r3, r8, #0 8011118: d023 beq.n 8011162 <__d2b+0x82> 801111a: 4668 mov r0, sp 801111c: 9300 str r3, [sp, #0] 801111e: f7ff fd7c bl 8010c1a <__lo0bits> 8011122: e9dd 1200 ldrd r1, r2, [sp] 8011126: b1d0 cbz r0, 801115e <__d2b+0x7e> 8011128: f1c0 0320 rsb r3, r0, #32 801112c: fa02 f303 lsl.w r3, r2, r3 8011130: 430b orrs r3, r1 8011132: 40c2 lsrs r2, r0 8011134: 6163 str r3, [r4, #20] 8011136: 9201 str r2, [sp, #4] 8011138: 9b01 ldr r3, [sp, #4] 801113a: 61a3 str r3, [r4, #24] 801113c: 2b00 cmp r3, #0 801113e: bf0c ite eq 8011140: 2201 moveq r2, #1 8011142: 2202 movne r2, #2 8011144: 6122 str r2, [r4, #16] 8011146: b1a5 cbz r5, 8011172 <__d2b+0x92> 8011148: f2a5 4533 subw r5, r5, #1075 @ 0x433 801114c: 4405 add r5, r0 801114e: 603d str r5, [r7, #0] 8011150: f1c0 0035 rsb r0, r0, #53 @ 0x35 8011154: 6030 str r0, [r6, #0] 8011156: 4620 mov r0, r4 8011158: b003 add sp, #12 801115a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 801115e: 6161 str r1, [r4, #20] 8011160: e7ea b.n 8011138 <__d2b+0x58> 8011162: a801 add r0, sp, #4 8011164: f7ff fd59 bl 8010c1a <__lo0bits> 8011168: 9b01 ldr r3, [sp, #4] 801116a: 6163 str r3, [r4, #20] 801116c: 3020 adds r0, #32 801116e: 2201 movs r2, #1 8011170: e7e8 b.n 8011144 <__d2b+0x64> 8011172: eb04 0382 add.w r3, r4, r2, lsl #2 8011176: f2a0 4032 subw r0, r0, #1074 @ 0x432 801117a: 6038 str r0, [r7, #0] 801117c: 6918 ldr r0, [r3, #16] 801117e: f7ff fd2d bl 8010bdc <__hi0bits> 8011182: ebc0 1042 rsb r0, r0, r2, lsl #5 8011186: e7e5 b.n 8011154 <__d2b+0x74> 8011188: 08011b1c .word 0x08011b1c 801118c: 08011b2d .word 0x08011b2d 08011190 <__sflush_r>: 8011190: f9b1 200c ldrsh.w r2, [r1, #12] 8011194: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8011198: 0716 lsls r6, r2, #28 801119a: 4605 mov r5, r0 801119c: 460c mov r4, r1 801119e: d454 bmi.n 801124a <__sflush_r+0xba> 80111a0: 684b ldr r3, [r1, #4] 80111a2: 2b00 cmp r3, #0 80111a4: dc02 bgt.n 80111ac <__sflush_r+0x1c> 80111a6: 6c0b ldr r3, [r1, #64] @ 0x40 80111a8: 2b00 cmp r3, #0 80111aa: dd48 ble.n 801123e <__sflush_r+0xae> 80111ac: 6ae6 ldr r6, [r4, #44] @ 0x2c 80111ae: 2e00 cmp r6, #0 80111b0: d045 beq.n 801123e <__sflush_r+0xae> 80111b2: 2300 movs r3, #0 80111b4: f412 5280 ands.w r2, r2, #4096 @ 0x1000 80111b8: 682f ldr r7, [r5, #0] 80111ba: 6a21 ldr r1, [r4, #32] 80111bc: 602b str r3, [r5, #0] 80111be: d030 beq.n 8011222 <__sflush_r+0x92> 80111c0: 6d62 ldr r2, [r4, #84] @ 0x54 80111c2: 89a3 ldrh r3, [r4, #12] 80111c4: 0759 lsls r1, r3, #29 80111c6: d505 bpl.n 80111d4 <__sflush_r+0x44> 80111c8: 6863 ldr r3, [r4, #4] 80111ca: 1ad2 subs r2, r2, r3 80111cc: 6b63 ldr r3, [r4, #52] @ 0x34 80111ce: b10b cbz r3, 80111d4 <__sflush_r+0x44> 80111d0: 6c23 ldr r3, [r4, #64] @ 0x40 80111d2: 1ad2 subs r2, r2, r3 80111d4: 2300 movs r3, #0 80111d6: 6ae6 ldr r6, [r4, #44] @ 0x2c 80111d8: 6a21 ldr r1, [r4, #32] 80111da: 4628 mov r0, r5 80111dc: 47b0 blx r6 80111de: 1c43 adds r3, r0, #1 80111e0: 89a3 ldrh r3, [r4, #12] 80111e2: d106 bne.n 80111f2 <__sflush_r+0x62> 80111e4: 6829 ldr r1, [r5, #0] 80111e6: 291d cmp r1, #29 80111e8: d82b bhi.n 8011242 <__sflush_r+0xb2> 80111ea: 4a2a ldr r2, [pc, #168] @ (8011294 <__sflush_r+0x104>) 80111ec: 410a asrs r2, r1 80111ee: 07d6 lsls r6, r2, #31 80111f0: d427 bmi.n 8011242 <__sflush_r+0xb2> 80111f2: 2200 movs r2, #0 80111f4: 6062 str r2, [r4, #4] 80111f6: 04d9 lsls r1, r3, #19 80111f8: 6922 ldr r2, [r4, #16] 80111fa: 6022 str r2, [r4, #0] 80111fc: d504 bpl.n 8011208 <__sflush_r+0x78> 80111fe: 1c42 adds r2, r0, #1 8011200: d101 bne.n 8011206 <__sflush_r+0x76> 8011202: 682b ldr r3, [r5, #0] 8011204: b903 cbnz r3, 8011208 <__sflush_r+0x78> 8011206: 6560 str r0, [r4, #84] @ 0x54 8011208: 6b61 ldr r1, [r4, #52] @ 0x34 801120a: 602f str r7, [r5, #0] 801120c: b1b9 cbz r1, 801123e <__sflush_r+0xae> 801120e: f104 0344 add.w r3, r4, #68 @ 0x44 8011212: 4299 cmp r1, r3 8011214: d002 beq.n 801121c <__sflush_r+0x8c> 8011216: 4628 mov r0, r5 8011218: f7ff fb38 bl 801088c <_free_r> 801121c: 2300 movs r3, #0 801121e: 6363 str r3, [r4, #52] @ 0x34 8011220: e00d b.n 801123e <__sflush_r+0xae> 8011222: 2301 movs r3, #1 8011224: 4628 mov r0, r5 8011226: 47b0 blx r6 8011228: 4602 mov r2, r0 801122a: 1c50 adds r0, r2, #1 801122c: d1c9 bne.n 80111c2 <__sflush_r+0x32> 801122e: 682b ldr r3, [r5, #0] 8011230: 2b00 cmp r3, #0 8011232: d0c6 beq.n 80111c2 <__sflush_r+0x32> 8011234: 2b1d cmp r3, #29 8011236: d001 beq.n 801123c <__sflush_r+0xac> 8011238: 2b16 cmp r3, #22 801123a: d11e bne.n 801127a <__sflush_r+0xea> 801123c: 602f str r7, [r5, #0] 801123e: 2000 movs r0, #0 8011240: e022 b.n 8011288 <__sflush_r+0xf8> 8011242: f043 0340 orr.w r3, r3, #64 @ 0x40 8011246: b21b sxth r3, r3 8011248: e01b b.n 8011282 <__sflush_r+0xf2> 801124a: 690f ldr r7, [r1, #16] 801124c: 2f00 cmp r7, #0 801124e: d0f6 beq.n 801123e <__sflush_r+0xae> 8011250: 0793 lsls r3, r2, #30 8011252: 680e ldr r6, [r1, #0] 8011254: bf08 it eq 8011256: 694b ldreq r3, [r1, #20] 8011258: 600f str r7, [r1, #0] 801125a: bf18 it ne 801125c: 2300 movne r3, #0 801125e: eba6 0807 sub.w r8, r6, r7 8011262: 608b str r3, [r1, #8] 8011264: f1b8 0f00 cmp.w r8, #0 8011268: dde9 ble.n 801123e <__sflush_r+0xae> 801126a: 6a21 ldr r1, [r4, #32] 801126c: 6aa6 ldr r6, [r4, #40] @ 0x28 801126e: 4643 mov r3, r8 8011270: 463a mov r2, r7 8011272: 4628 mov r0, r5 8011274: 47b0 blx r6 8011276: 2800 cmp r0, #0 8011278: dc08 bgt.n 801128c <__sflush_r+0xfc> 801127a: f9b4 300c ldrsh.w r3, [r4, #12] 801127e: f043 0340 orr.w r3, r3, #64 @ 0x40 8011282: 81a3 strh r3, [r4, #12] 8011284: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8011288: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 801128c: 4407 add r7, r0 801128e: eba8 0800 sub.w r8, r8, r0 8011292: e7e7 b.n 8011264 <__sflush_r+0xd4> 8011294: dfbffffe .word 0xdfbffffe 08011298 <_fflush_r>: 8011298: b538 push {r3, r4, r5, lr} 801129a: 690b ldr r3, [r1, #16] 801129c: 4605 mov r5, r0 801129e: 460c mov r4, r1 80112a0: b913 cbnz r3, 80112a8 <_fflush_r+0x10> 80112a2: 2500 movs r5, #0 80112a4: 4628 mov r0, r5 80112a6: bd38 pop {r3, r4, r5, pc} 80112a8: b118 cbz r0, 80112b2 <_fflush_r+0x1a> 80112aa: 6a03 ldr r3, [r0, #32] 80112ac: b90b cbnz r3, 80112b2 <_fflush_r+0x1a> 80112ae: f7fe fabf bl 800f830 <__sinit> 80112b2: f9b4 300c ldrsh.w r3, [r4, #12] 80112b6: 2b00 cmp r3, #0 80112b8: d0f3 beq.n 80112a2 <_fflush_r+0xa> 80112ba: 6e62 ldr r2, [r4, #100] @ 0x64 80112bc: 07d0 lsls r0, r2, #31 80112be: d404 bmi.n 80112ca <_fflush_r+0x32> 80112c0: 0599 lsls r1, r3, #22 80112c2: d402 bmi.n 80112ca <_fflush_r+0x32> 80112c4: 6da0 ldr r0, [r4, #88] @ 0x58 80112c6: f7fe fcf2 bl 800fcae <__retarget_lock_acquire_recursive> 80112ca: 4628 mov r0, r5 80112cc: 4621 mov r1, r4 80112ce: f7ff ff5f bl 8011190 <__sflush_r> 80112d2: 6e63 ldr r3, [r4, #100] @ 0x64 80112d4: 07da lsls r2, r3, #31 80112d6: 4605 mov r5, r0 80112d8: d4e4 bmi.n 80112a4 <_fflush_r+0xc> 80112da: 89a3 ldrh r3, [r4, #12] 80112dc: 059b lsls r3, r3, #22 80112de: d4e1 bmi.n 80112a4 <_fflush_r+0xc> 80112e0: 6da0 ldr r0, [r4, #88] @ 0x58 80112e2: f7fe fce5 bl 800fcb0 <__retarget_lock_release_recursive> 80112e6: e7dd b.n 80112a4 <_fflush_r+0xc> 080112e8 <__swhatbuf_r>: 80112e8: b570 push {r4, r5, r6, lr} 80112ea: 460c mov r4, r1 80112ec: f9b1 100e ldrsh.w r1, [r1, #14] 80112f0: 2900 cmp r1, #0 80112f2: b096 sub sp, #88 @ 0x58 80112f4: 4615 mov r5, r2 80112f6: 461e mov r6, r3 80112f8: da0d bge.n 8011316 <__swhatbuf_r+0x2e> 80112fa: 89a3 ldrh r3, [r4, #12] 80112fc: f013 0f80 tst.w r3, #128 @ 0x80 8011300: f04f 0100 mov.w r1, #0 8011304: bf14 ite ne 8011306: 2340 movne r3, #64 @ 0x40 8011308: f44f 6380 moveq.w r3, #1024 @ 0x400 801130c: 2000 movs r0, #0 801130e: 6031 str r1, [r6, #0] 8011310: 602b str r3, [r5, #0] 8011312: b016 add sp, #88 @ 0x58 8011314: bd70 pop {r4, r5, r6, pc} 8011316: 466a mov r2, sp 8011318: f000 f848 bl 80113ac <_fstat_r> 801131c: 2800 cmp r0, #0 801131e: dbec blt.n 80112fa <__swhatbuf_r+0x12> 8011320: 9901 ldr r1, [sp, #4] 8011322: f401 4170 and.w r1, r1, #61440 @ 0xf000 8011326: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 801132a: 4259 negs r1, r3 801132c: 4159 adcs r1, r3 801132e: f44f 6380 mov.w r3, #1024 @ 0x400 8011332: e7eb b.n 801130c <__swhatbuf_r+0x24> 08011334 <__smakebuf_r>: 8011334: 898b ldrh r3, [r1, #12] 8011336: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8011338: 079d lsls r5, r3, #30 801133a: 4606 mov r6, r0 801133c: 460c mov r4, r1 801133e: d507 bpl.n 8011350 <__smakebuf_r+0x1c> 8011340: f104 0347 add.w r3, r4, #71 @ 0x47 8011344: 6023 str r3, [r4, #0] 8011346: 6123 str r3, [r4, #16] 8011348: 2301 movs r3, #1 801134a: 6163 str r3, [r4, #20] 801134c: b003 add sp, #12 801134e: bdf0 pop {r4, r5, r6, r7, pc} 8011350: ab01 add r3, sp, #4 8011352: 466a mov r2, sp 8011354: f7ff ffc8 bl 80112e8 <__swhatbuf_r> 8011358: 9f00 ldr r7, [sp, #0] 801135a: 4605 mov r5, r0 801135c: 4639 mov r1, r7 801135e: 4630 mov r0, r6 8011360: f7ff fb08 bl 8010974 <_malloc_r> 8011364: b948 cbnz r0, 801137a <__smakebuf_r+0x46> 8011366: f9b4 300c ldrsh.w r3, [r4, #12] 801136a: 059a lsls r2, r3, #22 801136c: d4ee bmi.n 801134c <__smakebuf_r+0x18> 801136e: f023 0303 bic.w r3, r3, #3 8011372: f043 0302 orr.w r3, r3, #2 8011376: 81a3 strh r3, [r4, #12] 8011378: e7e2 b.n 8011340 <__smakebuf_r+0xc> 801137a: 89a3 ldrh r3, [r4, #12] 801137c: 6020 str r0, [r4, #0] 801137e: f043 0380 orr.w r3, r3, #128 @ 0x80 8011382: 81a3 strh r3, [r4, #12] 8011384: 9b01 ldr r3, [sp, #4] 8011386: e9c4 0704 strd r0, r7, [r4, #16] 801138a: b15b cbz r3, 80113a4 <__smakebuf_r+0x70> 801138c: f9b4 100e ldrsh.w r1, [r4, #14] 8011390: 4630 mov r0, r6 8011392: f000 f81d bl 80113d0 <_isatty_r> 8011396: b128 cbz r0, 80113a4 <__smakebuf_r+0x70> 8011398: 89a3 ldrh r3, [r4, #12] 801139a: f023 0303 bic.w r3, r3, #3 801139e: f043 0301 orr.w r3, r3, #1 80113a2: 81a3 strh r3, [r4, #12] 80113a4: 89a3 ldrh r3, [r4, #12] 80113a6: 431d orrs r5, r3 80113a8: 81a5 strh r5, [r4, #12] 80113aa: e7cf b.n 801134c <__smakebuf_r+0x18> 080113ac <_fstat_r>: 80113ac: b538 push {r3, r4, r5, lr} 80113ae: 4d07 ldr r5, [pc, #28] @ (80113cc <_fstat_r+0x20>) 80113b0: 2300 movs r3, #0 80113b2: 4604 mov r4, r0 80113b4: 4608 mov r0, r1 80113b6: 4611 mov r1, r2 80113b8: 602b str r3, [r5, #0] 80113ba: f7f1 fe95 bl 80030e8 <_fstat> 80113be: 1c43 adds r3, r0, #1 80113c0: d102 bne.n 80113c8 <_fstat_r+0x1c> 80113c2: 682b ldr r3, [r5, #0] 80113c4: b103 cbz r3, 80113c8 <_fstat_r+0x1c> 80113c6: 6023 str r3, [r4, #0] 80113c8: bd38 pop {r3, r4, r5, pc} 80113ca: bf00 nop 80113cc: 240132d4 .word 0x240132d4 080113d0 <_isatty_r>: 80113d0: b538 push {r3, r4, r5, lr} 80113d2: 4d06 ldr r5, [pc, #24] @ (80113ec <_isatty_r+0x1c>) 80113d4: 2300 movs r3, #0 80113d6: 4604 mov r4, r0 80113d8: 4608 mov r0, r1 80113da: 602b str r3, [r5, #0] 80113dc: f7f1 fe8a bl 80030f4 <_isatty> 80113e0: 1c43 adds r3, r0, #1 80113e2: d102 bne.n 80113ea <_isatty_r+0x1a> 80113e4: 682b ldr r3, [r5, #0] 80113e6: b103 cbz r3, 80113ea <_isatty_r+0x1a> 80113e8: 6023 str r3, [r4, #0] 80113ea: bd38 pop {r3, r4, r5, pc} 80113ec: 240132d4 .word 0x240132d4 080113f0 <_sbrk_r>: 80113f0: b538 push {r3, r4, r5, lr} 80113f2: 4d06 ldr r5, [pc, #24] @ (801140c <_sbrk_r+0x1c>) 80113f4: 2300 movs r3, #0 80113f6: 4604 mov r4, r0 80113f8: 4608 mov r0, r1 80113fa: 602b str r3, [r5, #0] 80113fc: f7f1 fe7e bl 80030fc <_sbrk> 8011400: 1c43 adds r3, r0, #1 8011402: d102 bne.n 801140a <_sbrk_r+0x1a> 8011404: 682b ldr r3, [r5, #0] 8011406: b103 cbz r3, 801140a <_sbrk_r+0x1a> 8011408: 6023 str r3, [r4, #0] 801140a: bd38 pop {r3, r4, r5, pc} 801140c: 240132d4 .word 0x240132d4 08011410 <__assert_func>: 8011410: b51f push {r0, r1, r2, r3, r4, lr} 8011412: 4614 mov r4, r2 8011414: 461a mov r2, r3 8011416: 4b09 ldr r3, [pc, #36] @ (801143c <__assert_func+0x2c>) 8011418: 681b ldr r3, [r3, #0] 801141a: 4605 mov r5, r0 801141c: 68d8 ldr r0, [r3, #12] 801141e: b954 cbnz r4, 8011436 <__assert_func+0x26> 8011420: 4b07 ldr r3, [pc, #28] @ (8011440 <__assert_func+0x30>) 8011422: 461c mov r4, r3 8011424: e9cd 3401 strd r3, r4, [sp, #4] 8011428: 9100 str r1, [sp, #0] 801142a: 462b mov r3, r5 801142c: 4905 ldr r1, [pc, #20] @ (8011444 <__assert_func+0x34>) 801142e: f000 f841 bl 80114b4 8011432: f000 f851 bl 80114d8 8011436: 4b04 ldr r3, [pc, #16] @ (8011448 <__assert_func+0x38>) 8011438: e7f4 b.n 8011424 <__assert_func+0x14> 801143a: bf00 nop 801143c: 24000054 .word 0x24000054 8011440: 08011ccd .word 0x08011ccd 8011444: 08011c9f .word 0x08011c9f 8011448: 08011c92 .word 0x08011c92 0801144c <_calloc_r>: 801144c: b570 push {r4, r5, r6, lr} 801144e: fba1 5402 umull r5, r4, r1, r2 8011452: b93c cbnz r4, 8011464 <_calloc_r+0x18> 8011454: 4629 mov r1, r5 8011456: f7ff fa8d bl 8010974 <_malloc_r> 801145a: 4606 mov r6, r0 801145c: b928 cbnz r0, 801146a <_calloc_r+0x1e> 801145e: 2600 movs r6, #0 8011460: 4630 mov r0, r6 8011462: bd70 pop {r4, r5, r6, pc} 8011464: 220c movs r2, #12 8011466: 6002 str r2, [r0, #0] 8011468: e7f9 b.n 801145e <_calloc_r+0x12> 801146a: 462a mov r2, r5 801146c: 4621 mov r1, r4 801146e: f7fe fb4b bl 800fb08 8011472: e7f5 b.n 8011460 <_calloc_r+0x14> 08011474 <__ascii_mbtowc>: 8011474: b082 sub sp, #8 8011476: b901 cbnz r1, 801147a <__ascii_mbtowc+0x6> 8011478: a901 add r1, sp, #4 801147a: b142 cbz r2, 801148e <__ascii_mbtowc+0x1a> 801147c: b14b cbz r3, 8011492 <__ascii_mbtowc+0x1e> 801147e: 7813 ldrb r3, [r2, #0] 8011480: 600b str r3, [r1, #0] 8011482: 7812 ldrb r2, [r2, #0] 8011484: 1e10 subs r0, r2, #0 8011486: bf18 it ne 8011488: 2001 movne r0, #1 801148a: b002 add sp, #8 801148c: 4770 bx lr 801148e: 4610 mov r0, r2 8011490: e7fb b.n 801148a <__ascii_mbtowc+0x16> 8011492: f06f 0001 mvn.w r0, #1 8011496: e7f8 b.n 801148a <__ascii_mbtowc+0x16> 08011498 <__ascii_wctomb>: 8011498: 4603 mov r3, r0 801149a: 4608 mov r0, r1 801149c: b141 cbz r1, 80114b0 <__ascii_wctomb+0x18> 801149e: 2aff cmp r2, #255 @ 0xff 80114a0: d904 bls.n 80114ac <__ascii_wctomb+0x14> 80114a2: 228a movs r2, #138 @ 0x8a 80114a4: 601a str r2, [r3, #0] 80114a6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80114aa: 4770 bx lr 80114ac: 700a strb r2, [r1, #0] 80114ae: 2001 movs r0, #1 80114b0: 4770 bx lr ... 080114b4 : 80114b4: b40e push {r1, r2, r3} 80114b6: b503 push {r0, r1, lr} 80114b8: 4601 mov r1, r0 80114ba: ab03 add r3, sp, #12 80114bc: 4805 ldr r0, [pc, #20] @ (80114d4 ) 80114be: f853 2b04 ldr.w r2, [r3], #4 80114c2: 6800 ldr r0, [r0, #0] 80114c4: 9301 str r3, [sp, #4] 80114c6: f000 f837 bl 8011538 <_vfiprintf_r> 80114ca: b002 add sp, #8 80114cc: f85d eb04 ldr.w lr, [sp], #4 80114d0: b003 add sp, #12 80114d2: 4770 bx lr 80114d4: 24000054 .word 0x24000054 080114d8 : 80114d8: b508 push {r3, lr} 80114da: 2006 movs r0, #6 80114dc: f000 f96c bl 80117b8 80114e0: 2001 movs r0, #1 80114e2: f7f1 fddb bl 800309c <_exit> 080114e6 <__sfputc_r>: 80114e6: 6893 ldr r3, [r2, #8] 80114e8: 3b01 subs r3, #1 80114ea: 2b00 cmp r3, #0 80114ec: b410 push {r4} 80114ee: 6093 str r3, [r2, #8] 80114f0: da08 bge.n 8011504 <__sfputc_r+0x1e> 80114f2: 6994 ldr r4, [r2, #24] 80114f4: 42a3 cmp r3, r4 80114f6: db01 blt.n 80114fc <__sfputc_r+0x16> 80114f8: 290a cmp r1, #10 80114fa: d103 bne.n 8011504 <__sfputc_r+0x1e> 80114fc: f85d 4b04 ldr.w r4, [sp], #4 8011500: f7fe ba6d b.w 800f9de <__swbuf_r> 8011504: 6813 ldr r3, [r2, #0] 8011506: 1c58 adds r0, r3, #1 8011508: 6010 str r0, [r2, #0] 801150a: 7019 strb r1, [r3, #0] 801150c: 4608 mov r0, r1 801150e: f85d 4b04 ldr.w r4, [sp], #4 8011512: 4770 bx lr 08011514 <__sfputs_r>: 8011514: b5f8 push {r3, r4, r5, r6, r7, lr} 8011516: 4606 mov r6, r0 8011518: 460f mov r7, r1 801151a: 4614 mov r4, r2 801151c: 18d5 adds r5, r2, r3 801151e: 42ac cmp r4, r5 8011520: d101 bne.n 8011526 <__sfputs_r+0x12> 8011522: 2000 movs r0, #0 8011524: e007 b.n 8011536 <__sfputs_r+0x22> 8011526: f814 1b01 ldrb.w r1, [r4], #1 801152a: 463a mov r2, r7 801152c: 4630 mov r0, r6 801152e: f7ff ffda bl 80114e6 <__sfputc_r> 8011532: 1c43 adds r3, r0, #1 8011534: d1f3 bne.n 801151e <__sfputs_r+0xa> 8011536: bdf8 pop {r3, r4, r5, r6, r7, pc} 08011538 <_vfiprintf_r>: 8011538: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801153c: 460d mov r5, r1 801153e: b09d sub sp, #116 @ 0x74 8011540: 4614 mov r4, r2 8011542: 4698 mov r8, r3 8011544: 4606 mov r6, r0 8011546: b118 cbz r0, 8011550 <_vfiprintf_r+0x18> 8011548: 6a03 ldr r3, [r0, #32] 801154a: b90b cbnz r3, 8011550 <_vfiprintf_r+0x18> 801154c: f7fe f970 bl 800f830 <__sinit> 8011550: 6e6b ldr r3, [r5, #100] @ 0x64 8011552: 07d9 lsls r1, r3, #31 8011554: d405 bmi.n 8011562 <_vfiprintf_r+0x2a> 8011556: 89ab ldrh r3, [r5, #12] 8011558: 059a lsls r2, r3, #22 801155a: d402 bmi.n 8011562 <_vfiprintf_r+0x2a> 801155c: 6da8 ldr r0, [r5, #88] @ 0x58 801155e: f7fe fba6 bl 800fcae <__retarget_lock_acquire_recursive> 8011562: 89ab ldrh r3, [r5, #12] 8011564: 071b lsls r3, r3, #28 8011566: d501 bpl.n 801156c <_vfiprintf_r+0x34> 8011568: 692b ldr r3, [r5, #16] 801156a: b99b cbnz r3, 8011594 <_vfiprintf_r+0x5c> 801156c: 4629 mov r1, r5 801156e: 4630 mov r0, r6 8011570: f7fe fa74 bl 800fa5c <__swsetup_r> 8011574: b170 cbz r0, 8011594 <_vfiprintf_r+0x5c> 8011576: 6e6b ldr r3, [r5, #100] @ 0x64 8011578: 07dc lsls r4, r3, #31 801157a: d504 bpl.n 8011586 <_vfiprintf_r+0x4e> 801157c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8011580: b01d add sp, #116 @ 0x74 8011582: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8011586: 89ab ldrh r3, [r5, #12] 8011588: 0598 lsls r0, r3, #22 801158a: d4f7 bmi.n 801157c <_vfiprintf_r+0x44> 801158c: 6da8 ldr r0, [r5, #88] @ 0x58 801158e: f7fe fb8f bl 800fcb0 <__retarget_lock_release_recursive> 8011592: e7f3 b.n 801157c <_vfiprintf_r+0x44> 8011594: 2300 movs r3, #0 8011596: 9309 str r3, [sp, #36] @ 0x24 8011598: 2320 movs r3, #32 801159a: f88d 3029 strb.w r3, [sp, #41] @ 0x29 801159e: f8cd 800c str.w r8, [sp, #12] 80115a2: 2330 movs r3, #48 @ 0x30 80115a4: f8df 81ac ldr.w r8, [pc, #428] @ 8011754 <_vfiprintf_r+0x21c> 80115a8: f88d 302a strb.w r3, [sp, #42] @ 0x2a 80115ac: f04f 0901 mov.w r9, #1 80115b0: 4623 mov r3, r4 80115b2: 469a mov sl, r3 80115b4: f813 2b01 ldrb.w r2, [r3], #1 80115b8: b10a cbz r2, 80115be <_vfiprintf_r+0x86> 80115ba: 2a25 cmp r2, #37 @ 0x25 80115bc: d1f9 bne.n 80115b2 <_vfiprintf_r+0x7a> 80115be: ebba 0b04 subs.w fp, sl, r4 80115c2: d00b beq.n 80115dc <_vfiprintf_r+0xa4> 80115c4: 465b mov r3, fp 80115c6: 4622 mov r2, r4 80115c8: 4629 mov r1, r5 80115ca: 4630 mov r0, r6 80115cc: f7ff ffa2 bl 8011514 <__sfputs_r> 80115d0: 3001 adds r0, #1 80115d2: f000 80a7 beq.w 8011724 <_vfiprintf_r+0x1ec> 80115d6: 9a09 ldr r2, [sp, #36] @ 0x24 80115d8: 445a add r2, fp 80115da: 9209 str r2, [sp, #36] @ 0x24 80115dc: f89a 3000 ldrb.w r3, [sl] 80115e0: 2b00 cmp r3, #0 80115e2: f000 809f beq.w 8011724 <_vfiprintf_r+0x1ec> 80115e6: 2300 movs r3, #0 80115e8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80115ec: e9cd 2305 strd r2, r3, [sp, #20] 80115f0: f10a 0a01 add.w sl, sl, #1 80115f4: 9304 str r3, [sp, #16] 80115f6: 9307 str r3, [sp, #28] 80115f8: f88d 3053 strb.w r3, [sp, #83] @ 0x53 80115fc: 931a str r3, [sp, #104] @ 0x68 80115fe: 4654 mov r4, sl 8011600: 2205 movs r2, #5 8011602: f814 1b01 ldrb.w r1, [r4], #1 8011606: 4853 ldr r0, [pc, #332] @ (8011754 <_vfiprintf_r+0x21c>) 8011608: f7ee fe6a bl 80002e0 801160c: 9a04 ldr r2, [sp, #16] 801160e: b9d8 cbnz r0, 8011648 <_vfiprintf_r+0x110> 8011610: 06d1 lsls r1, r2, #27 8011612: bf44 itt mi 8011614: 2320 movmi r3, #32 8011616: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801161a: 0713 lsls r3, r2, #28 801161c: bf44 itt mi 801161e: 232b movmi r3, #43 @ 0x2b 8011620: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8011624: f89a 3000 ldrb.w r3, [sl] 8011628: 2b2a cmp r3, #42 @ 0x2a 801162a: d015 beq.n 8011658 <_vfiprintf_r+0x120> 801162c: 9a07 ldr r2, [sp, #28] 801162e: 4654 mov r4, sl 8011630: 2000 movs r0, #0 8011632: f04f 0c0a mov.w ip, #10 8011636: 4621 mov r1, r4 8011638: f811 3b01 ldrb.w r3, [r1], #1 801163c: 3b30 subs r3, #48 @ 0x30 801163e: 2b09 cmp r3, #9 8011640: d94b bls.n 80116da <_vfiprintf_r+0x1a2> 8011642: b1b0 cbz r0, 8011672 <_vfiprintf_r+0x13a> 8011644: 9207 str r2, [sp, #28] 8011646: e014 b.n 8011672 <_vfiprintf_r+0x13a> 8011648: eba0 0308 sub.w r3, r0, r8 801164c: fa09 f303 lsl.w r3, r9, r3 8011650: 4313 orrs r3, r2 8011652: 9304 str r3, [sp, #16] 8011654: 46a2 mov sl, r4 8011656: e7d2 b.n 80115fe <_vfiprintf_r+0xc6> 8011658: 9b03 ldr r3, [sp, #12] 801165a: 1d19 adds r1, r3, #4 801165c: 681b ldr r3, [r3, #0] 801165e: 9103 str r1, [sp, #12] 8011660: 2b00 cmp r3, #0 8011662: bfbb ittet lt 8011664: 425b neglt r3, r3 8011666: f042 0202 orrlt.w r2, r2, #2 801166a: 9307 strge r3, [sp, #28] 801166c: 9307 strlt r3, [sp, #28] 801166e: bfb8 it lt 8011670: 9204 strlt r2, [sp, #16] 8011672: 7823 ldrb r3, [r4, #0] 8011674: 2b2e cmp r3, #46 @ 0x2e 8011676: d10a bne.n 801168e <_vfiprintf_r+0x156> 8011678: 7863 ldrb r3, [r4, #1] 801167a: 2b2a cmp r3, #42 @ 0x2a 801167c: d132 bne.n 80116e4 <_vfiprintf_r+0x1ac> 801167e: 9b03 ldr r3, [sp, #12] 8011680: 1d1a adds r2, r3, #4 8011682: 681b ldr r3, [r3, #0] 8011684: 9203 str r2, [sp, #12] 8011686: ea43 73e3 orr.w r3, r3, r3, asr #31 801168a: 3402 adds r4, #2 801168c: 9305 str r3, [sp, #20] 801168e: f8df a0d4 ldr.w sl, [pc, #212] @ 8011764 <_vfiprintf_r+0x22c> 8011692: 7821 ldrb r1, [r4, #0] 8011694: 2203 movs r2, #3 8011696: 4650 mov r0, sl 8011698: f7ee fe22 bl 80002e0 801169c: b138 cbz r0, 80116ae <_vfiprintf_r+0x176> 801169e: 9b04 ldr r3, [sp, #16] 80116a0: eba0 000a sub.w r0, r0, sl 80116a4: 2240 movs r2, #64 @ 0x40 80116a6: 4082 lsls r2, r0 80116a8: 4313 orrs r3, r2 80116aa: 3401 adds r4, #1 80116ac: 9304 str r3, [sp, #16] 80116ae: f814 1b01 ldrb.w r1, [r4], #1 80116b2: 4829 ldr r0, [pc, #164] @ (8011758 <_vfiprintf_r+0x220>) 80116b4: f88d 1028 strb.w r1, [sp, #40] @ 0x28 80116b8: 2206 movs r2, #6 80116ba: f7ee fe11 bl 80002e0 80116be: 2800 cmp r0, #0 80116c0: d03f beq.n 8011742 <_vfiprintf_r+0x20a> 80116c2: 4b26 ldr r3, [pc, #152] @ (801175c <_vfiprintf_r+0x224>) 80116c4: bb1b cbnz r3, 801170e <_vfiprintf_r+0x1d6> 80116c6: 9b03 ldr r3, [sp, #12] 80116c8: 3307 adds r3, #7 80116ca: f023 0307 bic.w r3, r3, #7 80116ce: 3308 adds r3, #8 80116d0: 9303 str r3, [sp, #12] 80116d2: 9b09 ldr r3, [sp, #36] @ 0x24 80116d4: 443b add r3, r7 80116d6: 9309 str r3, [sp, #36] @ 0x24 80116d8: e76a b.n 80115b0 <_vfiprintf_r+0x78> 80116da: fb0c 3202 mla r2, ip, r2, r3 80116de: 460c mov r4, r1 80116e0: 2001 movs r0, #1 80116e2: e7a8 b.n 8011636 <_vfiprintf_r+0xfe> 80116e4: 2300 movs r3, #0 80116e6: 3401 adds r4, #1 80116e8: 9305 str r3, [sp, #20] 80116ea: 4619 mov r1, r3 80116ec: f04f 0c0a mov.w ip, #10 80116f0: 4620 mov r0, r4 80116f2: f810 2b01 ldrb.w r2, [r0], #1 80116f6: 3a30 subs r2, #48 @ 0x30 80116f8: 2a09 cmp r2, #9 80116fa: d903 bls.n 8011704 <_vfiprintf_r+0x1cc> 80116fc: 2b00 cmp r3, #0 80116fe: d0c6 beq.n 801168e <_vfiprintf_r+0x156> 8011700: 9105 str r1, [sp, #20] 8011702: e7c4 b.n 801168e <_vfiprintf_r+0x156> 8011704: fb0c 2101 mla r1, ip, r1, r2 8011708: 4604 mov r4, r0 801170a: 2301 movs r3, #1 801170c: e7f0 b.n 80116f0 <_vfiprintf_r+0x1b8> 801170e: ab03 add r3, sp, #12 8011710: 9300 str r3, [sp, #0] 8011712: 462a mov r2, r5 8011714: 4b12 ldr r3, [pc, #72] @ (8011760 <_vfiprintf_r+0x228>) 8011716: a904 add r1, sp, #16 8011718: 4630 mov r0, r6 801171a: f7fd fc55 bl 800efc8 <_printf_float> 801171e: 4607 mov r7, r0 8011720: 1c78 adds r0, r7, #1 8011722: d1d6 bne.n 80116d2 <_vfiprintf_r+0x19a> 8011724: 6e6b ldr r3, [r5, #100] @ 0x64 8011726: 07d9 lsls r1, r3, #31 8011728: d405 bmi.n 8011736 <_vfiprintf_r+0x1fe> 801172a: 89ab ldrh r3, [r5, #12] 801172c: 059a lsls r2, r3, #22 801172e: d402 bmi.n 8011736 <_vfiprintf_r+0x1fe> 8011730: 6da8 ldr r0, [r5, #88] @ 0x58 8011732: f7fe fabd bl 800fcb0 <__retarget_lock_release_recursive> 8011736: 89ab ldrh r3, [r5, #12] 8011738: 065b lsls r3, r3, #25 801173a: f53f af1f bmi.w 801157c <_vfiprintf_r+0x44> 801173e: 9809 ldr r0, [sp, #36] @ 0x24 8011740: e71e b.n 8011580 <_vfiprintf_r+0x48> 8011742: ab03 add r3, sp, #12 8011744: 9300 str r3, [sp, #0] 8011746: 462a mov r2, r5 8011748: 4b05 ldr r3, [pc, #20] @ (8011760 <_vfiprintf_r+0x228>) 801174a: a904 add r1, sp, #16 801174c: 4630 mov r0, r6 801174e: f7fd fec3 bl 800f4d8 <_printf_i> 8011752: e7e4 b.n 801171e <_vfiprintf_r+0x1e6> 8011754: 08011dcf .word 0x08011dcf 8011758: 08011dd9 .word 0x08011dd9 801175c: 0800efc9 .word 0x0800efc9 8011760: 08011515 .word 0x08011515 8011764: 08011dd5 .word 0x08011dd5 08011768 <_raise_r>: 8011768: 291f cmp r1, #31 801176a: b538 push {r3, r4, r5, lr} 801176c: 4605 mov r5, r0 801176e: 460c mov r4, r1 8011770: d904 bls.n 801177c <_raise_r+0x14> 8011772: 2316 movs r3, #22 8011774: 6003 str r3, [r0, #0] 8011776: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 801177a: bd38 pop {r3, r4, r5, pc} 801177c: 6bc2 ldr r2, [r0, #60] @ 0x3c 801177e: b112 cbz r2, 8011786 <_raise_r+0x1e> 8011780: f852 3021 ldr.w r3, [r2, r1, lsl #2] 8011784: b94b cbnz r3, 801179a <_raise_r+0x32> 8011786: 4628 mov r0, r5 8011788: f000 f830 bl 80117ec <_getpid_r> 801178c: 4622 mov r2, r4 801178e: 4601 mov r1, r0 8011790: 4628 mov r0, r5 8011792: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8011796: f000 b817 b.w 80117c8 <_kill_r> 801179a: 2b01 cmp r3, #1 801179c: d00a beq.n 80117b4 <_raise_r+0x4c> 801179e: 1c59 adds r1, r3, #1 80117a0: d103 bne.n 80117aa <_raise_r+0x42> 80117a2: 2316 movs r3, #22 80117a4: 6003 str r3, [r0, #0] 80117a6: 2001 movs r0, #1 80117a8: e7e7 b.n 801177a <_raise_r+0x12> 80117aa: 2100 movs r1, #0 80117ac: f842 1024 str.w r1, [r2, r4, lsl #2] 80117b0: 4620 mov r0, r4 80117b2: 4798 blx r3 80117b4: 2000 movs r0, #0 80117b6: e7e0 b.n 801177a <_raise_r+0x12> 080117b8 : 80117b8: 4b02 ldr r3, [pc, #8] @ (80117c4 ) 80117ba: 4601 mov r1, r0 80117bc: 6818 ldr r0, [r3, #0] 80117be: f7ff bfd3 b.w 8011768 <_raise_r> 80117c2: bf00 nop 80117c4: 24000054 .word 0x24000054 080117c8 <_kill_r>: 80117c8: b538 push {r3, r4, r5, lr} 80117ca: 4d07 ldr r5, [pc, #28] @ (80117e8 <_kill_r+0x20>) 80117cc: 2300 movs r3, #0 80117ce: 4604 mov r4, r0 80117d0: 4608 mov r0, r1 80117d2: 4611 mov r1, r2 80117d4: 602b str r3, [r5, #0] 80117d6: f7f1 fc57 bl 8003088 <_kill> 80117da: 1c43 adds r3, r0, #1 80117dc: d102 bne.n 80117e4 <_kill_r+0x1c> 80117de: 682b ldr r3, [r5, #0] 80117e0: b103 cbz r3, 80117e4 <_kill_r+0x1c> 80117e2: 6023 str r3, [r4, #0] 80117e4: bd38 pop {r3, r4, r5, pc} 80117e6: bf00 nop 80117e8: 240132d4 .word 0x240132d4 080117ec <_getpid_r>: 80117ec: f7f1 bc4a b.w 8003084 <_getpid> 080117f0 : 80117f0: b508 push {r3, lr} 80117f2: ed2d 8b02 vpush {d8} 80117f6: eef0 8a40 vmov.f32 s17, s0 80117fa: eeb0 8a60 vmov.f32 s16, s1 80117fe: f000 f817 bl 8011830 <__ieee754_fmodf> 8011802: eef4 8a48 vcmp.f32 s17, s16 8011806: eef1 fa10 vmrs APSR_nzcv, fpscr 801180a: d60c bvs.n 8011826 801180c: eddf 8a07 vldr s17, [pc, #28] @ 801182c 8011810: eeb4 8a68 vcmp.f32 s16, s17 8011814: eef1 fa10 vmrs APSR_nzcv, fpscr 8011818: d105 bne.n 8011826 801181a: f7fe fa1d bl 800fc58 <__errno> 801181e: ee88 0aa8 vdiv.f32 s0, s17, s17 8011822: 2321 movs r3, #33 @ 0x21 8011824: 6003 str r3, [r0, #0] 8011826: ecbd 8b02 vpop {d8} 801182a: bd08 pop {r3, pc} 801182c: 00000000 .word 0x00000000 08011830 <__ieee754_fmodf>: 8011830: b5f0 push {r4, r5, r6, r7, lr} 8011832: ee10 5a90 vmov r5, s1 8011836: f025 4000 bic.w r0, r5, #2147483648 @ 0x80000000 801183a: 1e43 subs r3, r0, #1 801183c: f1b3 4fff cmp.w r3, #2139095040 @ 0x7f800000 8011840: d206 bcs.n 8011850 <__ieee754_fmodf+0x20> 8011842: ee10 3a10 vmov r3, s0 8011846: f023 4600 bic.w r6, r3, #2147483648 @ 0x80000000 801184a: f1b6 4fff cmp.w r6, #2139095040 @ 0x7f800000 801184e: d304 bcc.n 801185a <__ieee754_fmodf+0x2a> 8011850: ee60 0a20 vmul.f32 s1, s0, s1 8011854: ee80 0aa0 vdiv.f32 s0, s1, s1 8011858: bdf0 pop {r4, r5, r6, r7, pc} 801185a: 4286 cmp r6, r0 801185c: dbfc blt.n 8011858 <__ieee754_fmodf+0x28> 801185e: f003 4400 and.w r4, r3, #2147483648 @ 0x80000000 8011862: d105 bne.n 8011870 <__ieee754_fmodf+0x40> 8011864: 4b32 ldr r3, [pc, #200] @ (8011930 <__ieee754_fmodf+0x100>) 8011866: eb03 7354 add.w r3, r3, r4, lsr #29 801186a: ed93 0a00 vldr s0, [r3] 801186e: e7f3 b.n 8011858 <__ieee754_fmodf+0x28> 8011870: f013 4fff tst.w r3, #2139095040 @ 0x7f800000 8011874: d140 bne.n 80118f8 <__ieee754_fmodf+0xc8> 8011876: 0232 lsls r2, r6, #8 8011878: f06f 017d mvn.w r1, #125 @ 0x7d 801187c: 2a00 cmp r2, #0 801187e: dc38 bgt.n 80118f2 <__ieee754_fmodf+0xc2> 8011880: f015 4fff tst.w r5, #2139095040 @ 0x7f800000 8011884: d13e bne.n 8011904 <__ieee754_fmodf+0xd4> 8011886: 0207 lsls r7, r0, #8 8011888: f06f 027d mvn.w r2, #125 @ 0x7d 801188c: 2f00 cmp r7, #0 801188e: da36 bge.n 80118fe <__ieee754_fmodf+0xce> 8011890: f111 0f7e cmn.w r1, #126 @ 0x7e 8011894: bfb9 ittee lt 8011896: f06f 037d mvnlt.w r3, #125 @ 0x7d 801189a: 1a5b sublt r3, r3, r1 801189c: f3c3 0316 ubfxge r3, r3, #0, #23 80118a0: f443 0300 orrge.w r3, r3, #8388608 @ 0x800000 80118a4: bfb8 it lt 80118a6: fa06 f303 lsllt.w r3, r6, r3 80118aa: f112 0f7e cmn.w r2, #126 @ 0x7e 80118ae: bfb5 itete lt 80118b0: f06f 057d mvnlt.w r5, #125 @ 0x7d 80118b4: f3c5 0516 ubfxge r5, r5, #0, #23 80118b8: 1aad sublt r5, r5, r2 80118ba: f445 0000 orrge.w r0, r5, #8388608 @ 0x800000 80118be: bfb8 it lt 80118c0: 40a8 lsllt r0, r5 80118c2: 1a89 subs r1, r1, r2 80118c4: 1a1d subs r5, r3, r0 80118c6: bb01 cbnz r1, 801190a <__ieee754_fmodf+0xda> 80118c8: ea13 0325 ands.w r3, r3, r5, asr #32 80118cc: bf38 it cc 80118ce: 462b movcc r3, r5 80118d0: 2b00 cmp r3, #0 80118d2: d0c7 beq.n 8011864 <__ieee754_fmodf+0x34> 80118d4: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 80118d8: db1f blt.n 801191a <__ieee754_fmodf+0xea> 80118da: f112 0f7e cmn.w r2, #126 @ 0x7e 80118de: db1f blt.n 8011920 <__ieee754_fmodf+0xf0> 80118e0: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 80118e4: 327f adds r2, #127 @ 0x7f 80118e6: 4323 orrs r3, r4 80118e8: ea43 53c2 orr.w r3, r3, r2, lsl #23 80118ec: ee00 3a10 vmov s0, r3 80118f0: e7b2 b.n 8011858 <__ieee754_fmodf+0x28> 80118f2: 3901 subs r1, #1 80118f4: 0052 lsls r2, r2, #1 80118f6: e7c1 b.n 801187c <__ieee754_fmodf+0x4c> 80118f8: 15f1 asrs r1, r6, #23 80118fa: 397f subs r1, #127 @ 0x7f 80118fc: e7c0 b.n 8011880 <__ieee754_fmodf+0x50> 80118fe: 3a01 subs r2, #1 8011900: 007f lsls r7, r7, #1 8011902: e7c3 b.n 801188c <__ieee754_fmodf+0x5c> 8011904: 15c2 asrs r2, r0, #23 8011906: 3a7f subs r2, #127 @ 0x7f 8011908: e7c2 b.n 8011890 <__ieee754_fmodf+0x60> 801190a: 2d00 cmp r5, #0 801190c: da02 bge.n 8011914 <__ieee754_fmodf+0xe4> 801190e: 005b lsls r3, r3, #1 8011910: 3901 subs r1, #1 8011912: e7d7 b.n 80118c4 <__ieee754_fmodf+0x94> 8011914: d0a6 beq.n 8011864 <__ieee754_fmodf+0x34> 8011916: 006b lsls r3, r5, #1 8011918: e7fa b.n 8011910 <__ieee754_fmodf+0xe0> 801191a: 005b lsls r3, r3, #1 801191c: 3a01 subs r2, #1 801191e: e7d9 b.n 80118d4 <__ieee754_fmodf+0xa4> 8011920: f1c2 22ff rsb r2, r2, #4278255360 @ 0xff00ff00 8011924: f502 027f add.w r2, r2, #16711680 @ 0xff0000 8011928: 3282 adds r2, #130 @ 0x82 801192a: 4113 asrs r3, r2 801192c: 4323 orrs r3, r4 801192e: e7dd b.n 80118ec <__ieee754_fmodf+0xbc> 8011930: 08011de0 .word 0x08011de0 08011934 <_init>: 8011934: b5f8 push {r3, r4, r5, r6, r7, lr} 8011936: bf00 nop 8011938: bcf8 pop {r3, r4, r5, r6, r7} 801193a: bc08 pop {r3} 801193c: 469e mov lr, r3 801193e: 4770 bx lr 08011940 <_fini>: 8011940: b5f8 push {r3, r4, r5, r6, r7, lr} 8011942: bf00 nop 8011944: bcf8 pop {r3, r4, r5, r6, r7} 8011946: bc08 pop {r3} 8011948: 469e mov lr, r3 801194a: 4770 bx lr