OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 0000fd08 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 0000017c 0800ffa8 0800ffa8 00010fa8 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 08010124 08010124 00011124 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0801012c 0801012c 0001112c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 08010130 08010130 00011130 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 00000070 24000000 08010134 00012000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 00012858 24000070 080101a4 00012070 2**2 ALLOC 8 ._user_heap_stack 00000600 240128c8 080101a4 000128c8 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 00012070 2**0 CONTENTS, READONLY 10 .debug_info 000275d4 00000000 00000000 0001209e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 00004fb6 00000000 00000000 00039672 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00001ca8 00000000 00000000 0003e628 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_rnglists 00001627 00000000 00000000 000402d0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_macro 0003b149 00000000 00000000 000418f7 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_line 00025aeb 00000000 00000000 0007ca40 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_str 0016ddfb 00000000 00000000 000a252b 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .comment 00000043 00000000 00000000 00210326 2**0 CONTENTS, READONLY 18 .debug_frame 00007f70 00000000 00000000 0021036c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 002182dc 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 24000070 .word 0x24000070 80002bc: 00000000 .word 0x00000000 80002c0: 0800ff90 .word 0x0800ff90 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 24000074 .word 0x24000074 80002dc: 0800ff90 .word 0x0800ff90 080002e0 : 80002e0: f001 01ff and.w r1, r1, #255 @ 0xff 80002e4: 2a10 cmp r2, #16 80002e6: db2b blt.n 8000340 80002e8: f010 0f07 tst.w r0, #7 80002ec: d008 beq.n 8000300 80002ee: f810 3b01 ldrb.w r3, [r0], #1 80002f2: 3a01 subs r2, #1 80002f4: 428b cmp r3, r1 80002f6: d02d beq.n 8000354 80002f8: f010 0f07 tst.w r0, #7 80002fc: b342 cbz r2, 8000350 80002fe: d1f6 bne.n 80002ee 8000300: b4f0 push {r4, r5, r6, r7} 8000302: ea41 2101 orr.w r1, r1, r1, lsl #8 8000306: ea41 4101 orr.w r1, r1, r1, lsl #16 800030a: f022 0407 bic.w r4, r2, #7 800030e: f07f 0700 mvns.w r7, #0 8000312: 2300 movs r3, #0 8000314: e8f0 5602 ldrd r5, r6, [r0], #8 8000318: 3c08 subs r4, #8 800031a: ea85 0501 eor.w r5, r5, r1 800031e: ea86 0601 eor.w r6, r6, r1 8000322: fa85 f547 uadd8 r5, r5, r7 8000326: faa3 f587 sel r5, r3, r7 800032a: fa86 f647 uadd8 r6, r6, r7 800032e: faa5 f687 sel r6, r5, r7 8000332: b98e cbnz r6, 8000358 8000334: d1ee bne.n 8000314 8000336: bcf0 pop {r4, r5, r6, r7} 8000338: f001 01ff and.w r1, r1, #255 @ 0xff 800033c: f002 0207 and.w r2, r2, #7 8000340: b132 cbz r2, 8000350 8000342: f810 3b01 ldrb.w r3, [r0], #1 8000346: 3a01 subs r2, #1 8000348: ea83 0301 eor.w r3, r3, r1 800034c: b113 cbz r3, 8000354 800034e: d1f8 bne.n 8000342 8000350: 2000 movs r0, #0 8000352: 4770 bx lr 8000354: 3801 subs r0, #1 8000356: 4770 bx lr 8000358: 2d00 cmp r5, #0 800035a: bf06 itte eq 800035c: 4635 moveq r5, r6 800035e: 3803 subeq r0, #3 8000360: 3807 subne r0, #7 8000362: f015 0f01 tst.w r5, #1 8000366: d107 bne.n 8000378 8000368: 3001 adds r0, #1 800036a: f415 7f80 tst.w r5, #256 @ 0x100 800036e: bf02 ittt eq 8000370: 3001 addeq r0, #1 8000372: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000376: 3001 addeq r0, #1 8000378: bcf0 pop {r4, r5, r6, r7} 800037a: 3801 subs r0, #1 800037c: 4770 bx lr 800037e: bf00 nop 08000380 <__aeabi_uldivmod>: 8000380: b953 cbnz r3, 8000398 <__aeabi_uldivmod+0x18> 8000382: b94a cbnz r2, 8000398 <__aeabi_uldivmod+0x18> 8000384: 2900 cmp r1, #0 8000386: bf08 it eq 8000388: 2800 cmpeq r0, #0 800038a: bf1c itt ne 800038c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000390: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000394: f000 b96a b.w 800066c <__aeabi_idiv0> 8000398: f1ad 0c08 sub.w ip, sp, #8 800039c: e96d ce04 strd ip, lr, [sp, #-16]! 80003a0: f000 f806 bl 80003b0 <__udivmoddi4> 80003a4: f8dd e004 ldr.w lr, [sp, #4] 80003a8: e9dd 2302 ldrd r2, r3, [sp, #8] 80003ac: b004 add sp, #16 80003ae: 4770 bx lr 080003b0 <__udivmoddi4>: 80003b0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80003b4: 9d08 ldr r5, [sp, #32] 80003b6: 460c mov r4, r1 80003b8: 2b00 cmp r3, #0 80003ba: d14e bne.n 800045a <__udivmoddi4+0xaa> 80003bc: 4694 mov ip, r2 80003be: 458c cmp ip, r1 80003c0: 4686 mov lr, r0 80003c2: fab2 f282 clz r2, r2 80003c6: d962 bls.n 800048e <__udivmoddi4+0xde> 80003c8: b14a cbz r2, 80003de <__udivmoddi4+0x2e> 80003ca: f1c2 0320 rsb r3, r2, #32 80003ce: 4091 lsls r1, r2 80003d0: fa20 f303 lsr.w r3, r0, r3 80003d4: fa0c fc02 lsl.w ip, ip, r2 80003d8: 4319 orrs r1, r3 80003da: fa00 fe02 lsl.w lr, r0, r2 80003de: ea4f 471c mov.w r7, ip, lsr #16 80003e2: fa1f f68c uxth.w r6, ip 80003e6: fbb1 f4f7 udiv r4, r1, r7 80003ea: ea4f 431e mov.w r3, lr, lsr #16 80003ee: fb07 1114 mls r1, r7, r4, r1 80003f2: ea43 4301 orr.w r3, r3, r1, lsl #16 80003f6: fb04 f106 mul.w r1, r4, r6 80003fa: 4299 cmp r1, r3 80003fc: d90a bls.n 8000414 <__udivmoddi4+0x64> 80003fe: eb1c 0303 adds.w r3, ip, r3 8000402: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000406: f080 8112 bcs.w 800062e <__udivmoddi4+0x27e> 800040a: 4299 cmp r1, r3 800040c: f240 810f bls.w 800062e <__udivmoddi4+0x27e> 8000410: 3c02 subs r4, #2 8000412: 4463 add r3, ip 8000414: 1a59 subs r1, r3, r1 8000416: fa1f f38e uxth.w r3, lr 800041a: fbb1 f0f7 udiv r0, r1, r7 800041e: fb07 1110 mls r1, r7, r0, r1 8000422: ea43 4301 orr.w r3, r3, r1, lsl #16 8000426: fb00 f606 mul.w r6, r0, r6 800042a: 429e cmp r6, r3 800042c: d90a bls.n 8000444 <__udivmoddi4+0x94> 800042e: eb1c 0303 adds.w r3, ip, r3 8000432: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000436: f080 80fc bcs.w 8000632 <__udivmoddi4+0x282> 800043a: 429e cmp r6, r3 800043c: f240 80f9 bls.w 8000632 <__udivmoddi4+0x282> 8000440: 4463 add r3, ip 8000442: 3802 subs r0, #2 8000444: 1b9b subs r3, r3, r6 8000446: ea40 4004 orr.w r0, r0, r4, lsl #16 800044a: 2100 movs r1, #0 800044c: b11d cbz r5, 8000456 <__udivmoddi4+0xa6> 800044e: 40d3 lsrs r3, r2 8000450: 2200 movs r2, #0 8000452: e9c5 3200 strd r3, r2, [r5] 8000456: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800045a: 428b cmp r3, r1 800045c: d905 bls.n 800046a <__udivmoddi4+0xba> 800045e: b10d cbz r5, 8000464 <__udivmoddi4+0xb4> 8000460: e9c5 0100 strd r0, r1, [r5] 8000464: 2100 movs r1, #0 8000466: 4608 mov r0, r1 8000468: e7f5 b.n 8000456 <__udivmoddi4+0xa6> 800046a: fab3 f183 clz r1, r3 800046e: 2900 cmp r1, #0 8000470: d146 bne.n 8000500 <__udivmoddi4+0x150> 8000472: 42a3 cmp r3, r4 8000474: d302 bcc.n 800047c <__udivmoddi4+0xcc> 8000476: 4290 cmp r0, r2 8000478: f0c0 80f0 bcc.w 800065c <__udivmoddi4+0x2ac> 800047c: 1a86 subs r6, r0, r2 800047e: eb64 0303 sbc.w r3, r4, r3 8000482: 2001 movs r0, #1 8000484: 2d00 cmp r5, #0 8000486: d0e6 beq.n 8000456 <__udivmoddi4+0xa6> 8000488: e9c5 6300 strd r6, r3, [r5] 800048c: e7e3 b.n 8000456 <__udivmoddi4+0xa6> 800048e: 2a00 cmp r2, #0 8000490: f040 8090 bne.w 80005b4 <__udivmoddi4+0x204> 8000494: eba1 040c sub.w r4, r1, ip 8000498: ea4f 481c mov.w r8, ip, lsr #16 800049c: fa1f f78c uxth.w r7, ip 80004a0: 2101 movs r1, #1 80004a2: fbb4 f6f8 udiv r6, r4, r8 80004a6: ea4f 431e mov.w r3, lr, lsr #16 80004aa: fb08 4416 mls r4, r8, r6, r4 80004ae: ea43 4304 orr.w r3, r3, r4, lsl #16 80004b2: fb07 f006 mul.w r0, r7, r6 80004b6: 4298 cmp r0, r3 80004b8: d908 bls.n 80004cc <__udivmoddi4+0x11c> 80004ba: eb1c 0303 adds.w r3, ip, r3 80004be: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 80004c2: d202 bcs.n 80004ca <__udivmoddi4+0x11a> 80004c4: 4298 cmp r0, r3 80004c6: f200 80cd bhi.w 8000664 <__udivmoddi4+0x2b4> 80004ca: 4626 mov r6, r4 80004cc: 1a1c subs r4, r3, r0 80004ce: fa1f f38e uxth.w r3, lr 80004d2: fbb4 f0f8 udiv r0, r4, r8 80004d6: fb08 4410 mls r4, r8, r0, r4 80004da: ea43 4304 orr.w r3, r3, r4, lsl #16 80004de: fb00 f707 mul.w r7, r0, r7 80004e2: 429f cmp r7, r3 80004e4: d908 bls.n 80004f8 <__udivmoddi4+0x148> 80004e6: eb1c 0303 adds.w r3, ip, r3 80004ea: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 80004ee: d202 bcs.n 80004f6 <__udivmoddi4+0x146> 80004f0: 429f cmp r7, r3 80004f2: f200 80b0 bhi.w 8000656 <__udivmoddi4+0x2a6> 80004f6: 4620 mov r0, r4 80004f8: 1bdb subs r3, r3, r7 80004fa: ea40 4006 orr.w r0, r0, r6, lsl #16 80004fe: e7a5 b.n 800044c <__udivmoddi4+0x9c> 8000500: f1c1 0620 rsb r6, r1, #32 8000504: 408b lsls r3, r1 8000506: fa22 f706 lsr.w r7, r2, r6 800050a: 431f orrs r7, r3 800050c: fa20 fc06 lsr.w ip, r0, r6 8000510: fa04 f301 lsl.w r3, r4, r1 8000514: ea43 030c orr.w r3, r3, ip 8000518: 40f4 lsrs r4, r6 800051a: fa00 f801 lsl.w r8, r0, r1 800051e: 0c38 lsrs r0, r7, #16 8000520: ea4f 4913 mov.w r9, r3, lsr #16 8000524: fbb4 fef0 udiv lr, r4, r0 8000528: fa1f fc87 uxth.w ip, r7 800052c: fb00 441e mls r4, r0, lr, r4 8000530: ea49 4404 orr.w r4, r9, r4, lsl #16 8000534: fb0e f90c mul.w r9, lr, ip 8000538: 45a1 cmp r9, r4 800053a: fa02 f201 lsl.w r2, r2, r1 800053e: d90a bls.n 8000556 <__udivmoddi4+0x1a6> 8000540: 193c adds r4, r7, r4 8000542: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 8000546: f080 8084 bcs.w 8000652 <__udivmoddi4+0x2a2> 800054a: 45a1 cmp r9, r4 800054c: f240 8081 bls.w 8000652 <__udivmoddi4+0x2a2> 8000550: f1ae 0e02 sub.w lr, lr, #2 8000554: 443c add r4, r7 8000556: eba4 0409 sub.w r4, r4, r9 800055a: fa1f f983 uxth.w r9, r3 800055e: fbb4 f3f0 udiv r3, r4, r0 8000562: fb00 4413 mls r4, r0, r3, r4 8000566: ea49 4404 orr.w r4, r9, r4, lsl #16 800056a: fb03 fc0c mul.w ip, r3, ip 800056e: 45a4 cmp ip, r4 8000570: d907 bls.n 8000582 <__udivmoddi4+0x1d2> 8000572: 193c adds r4, r7, r4 8000574: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 8000578: d267 bcs.n 800064a <__udivmoddi4+0x29a> 800057a: 45a4 cmp ip, r4 800057c: d965 bls.n 800064a <__udivmoddi4+0x29a> 800057e: 3b02 subs r3, #2 8000580: 443c add r4, r7 8000582: ea43 400e orr.w r0, r3, lr, lsl #16 8000586: fba0 9302 umull r9, r3, r0, r2 800058a: eba4 040c sub.w r4, r4, ip 800058e: 429c cmp r4, r3 8000590: 46ce mov lr, r9 8000592: 469c mov ip, r3 8000594: d351 bcc.n 800063a <__udivmoddi4+0x28a> 8000596: d04e beq.n 8000636 <__udivmoddi4+0x286> 8000598: b155 cbz r5, 80005b0 <__udivmoddi4+0x200> 800059a: ebb8 030e subs.w r3, r8, lr 800059e: eb64 040c sbc.w r4, r4, ip 80005a2: fa04 f606 lsl.w r6, r4, r6 80005a6: 40cb lsrs r3, r1 80005a8: 431e orrs r6, r3 80005aa: 40cc lsrs r4, r1 80005ac: e9c5 6400 strd r6, r4, [r5] 80005b0: 2100 movs r1, #0 80005b2: e750 b.n 8000456 <__udivmoddi4+0xa6> 80005b4: f1c2 0320 rsb r3, r2, #32 80005b8: fa20 f103 lsr.w r1, r0, r3 80005bc: fa0c fc02 lsl.w ip, ip, r2 80005c0: fa24 f303 lsr.w r3, r4, r3 80005c4: 4094 lsls r4, r2 80005c6: 430c orrs r4, r1 80005c8: ea4f 481c mov.w r8, ip, lsr #16 80005cc: fa00 fe02 lsl.w lr, r0, r2 80005d0: fa1f f78c uxth.w r7, ip 80005d4: fbb3 f0f8 udiv r0, r3, r8 80005d8: fb08 3110 mls r1, r8, r0, r3 80005dc: 0c23 lsrs r3, r4, #16 80005de: ea43 4301 orr.w r3, r3, r1, lsl #16 80005e2: fb00 f107 mul.w r1, r0, r7 80005e6: 4299 cmp r1, r3 80005e8: d908 bls.n 80005fc <__udivmoddi4+0x24c> 80005ea: eb1c 0303 adds.w r3, ip, r3 80005ee: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 80005f2: d22c bcs.n 800064e <__udivmoddi4+0x29e> 80005f4: 4299 cmp r1, r3 80005f6: d92a bls.n 800064e <__udivmoddi4+0x29e> 80005f8: 3802 subs r0, #2 80005fa: 4463 add r3, ip 80005fc: 1a5b subs r3, r3, r1 80005fe: b2a4 uxth r4, r4 8000600: fbb3 f1f8 udiv r1, r3, r8 8000604: fb08 3311 mls r3, r8, r1, r3 8000608: ea44 4403 orr.w r4, r4, r3, lsl #16 800060c: fb01 f307 mul.w r3, r1, r7 8000610: 42a3 cmp r3, r4 8000612: d908 bls.n 8000626 <__udivmoddi4+0x276> 8000614: eb1c 0404 adds.w r4, ip, r4 8000618: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800061c: d213 bcs.n 8000646 <__udivmoddi4+0x296> 800061e: 42a3 cmp r3, r4 8000620: d911 bls.n 8000646 <__udivmoddi4+0x296> 8000622: 3902 subs r1, #2 8000624: 4464 add r4, ip 8000626: 1ae4 subs r4, r4, r3 8000628: ea41 4100 orr.w r1, r1, r0, lsl #16 800062c: e739 b.n 80004a2 <__udivmoddi4+0xf2> 800062e: 4604 mov r4, r0 8000630: e6f0 b.n 8000414 <__udivmoddi4+0x64> 8000632: 4608 mov r0, r1 8000634: e706 b.n 8000444 <__udivmoddi4+0x94> 8000636: 45c8 cmp r8, r9 8000638: d2ae bcs.n 8000598 <__udivmoddi4+0x1e8> 800063a: ebb9 0e02 subs.w lr, r9, r2 800063e: eb63 0c07 sbc.w ip, r3, r7 8000642: 3801 subs r0, #1 8000644: e7a8 b.n 8000598 <__udivmoddi4+0x1e8> 8000646: 4631 mov r1, r6 8000648: e7ed b.n 8000626 <__udivmoddi4+0x276> 800064a: 4603 mov r3, r0 800064c: e799 b.n 8000582 <__udivmoddi4+0x1d2> 800064e: 4630 mov r0, r6 8000650: e7d4 b.n 80005fc <__udivmoddi4+0x24c> 8000652: 46d6 mov lr, sl 8000654: e77f b.n 8000556 <__udivmoddi4+0x1a6> 8000656: 4463 add r3, ip 8000658: 3802 subs r0, #2 800065a: e74d b.n 80004f8 <__udivmoddi4+0x148> 800065c: 4606 mov r6, r0 800065e: 4623 mov r3, r4 8000660: 4608 mov r0, r1 8000662: e70f b.n 8000484 <__udivmoddi4+0xd4> 8000664: 3e02 subs r6, #2 8000666: 4463 add r3, ip 8000668: e730 b.n 80004cc <__udivmoddi4+0x11c> 800066a: bf00 nop 0800066c <__aeabi_idiv0>: 800066c: 4770 bx lr 800066e: bf00 nop 08000670 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 8000670: b480 push {r7} 8000672: b083 sub sp, #12 8000674: af00 add r7, sp, #0 8000676: 6078 str r0, [r7, #4] 8000678: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 800067a: bf00 nop 800067c: 370c adds r7, #12 800067e: 46bd mov sp, r7 8000680: f85d 7b04 ldr.w r7, [sp], #4 8000684: 4770 bx lr ... 08000688
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000688: b580 push {r7, lr} 800068a: b084 sub sp, #16 800068c: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 800068e: f000 fa77 bl 8000b80 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 8000692: 4b42 ldr r3, [pc, #264] @ (800079c ) 8000694: 695b ldr r3, [r3, #20] 8000696: f403 3300 and.w r3, r3, #131072 @ 0x20000 800069a: 2b00 cmp r3, #0 800069c: d11b bne.n 80006d6 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800069e: f3bf 8f4f dsb sy } 80006a2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80006a4: f3bf 8f6f isb sy } 80006a8: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 80006aa: 4b3c ldr r3, [pc, #240] @ (800079c ) 80006ac: 2200 movs r2, #0 80006ae: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 80006b2: f3bf 8f4f dsb sy } 80006b6: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80006b8: f3bf 8f6f isb sy } 80006bc: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 80006be: 4b37 ldr r3, [pc, #220] @ (800079c ) 80006c0: 695b ldr r3, [r3, #20] 80006c2: 4a36 ldr r2, [pc, #216] @ (800079c ) 80006c4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80006c8: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 80006ca: f3bf 8f4f dsb sy } 80006ce: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80006d0: f3bf 8f6f isb sy } 80006d4: e000 b.n 80006d8 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80006d6: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80006d8: 4b30 ldr r3, [pc, #192] @ (800079c ) 80006da: 695b ldr r3, [r3, #20] 80006dc: f403 3380 and.w r3, r3, #65536 @ 0x10000 80006e0: 2b00 cmp r3, #0 80006e2: d138 bne.n 8000756 SCB->CSSELR = 0U; /* select Level 1 data cache */ 80006e4: 4b2d ldr r3, [pc, #180] @ (800079c ) 80006e6: 2200 movs r2, #0 80006e8: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 80006ec: f3bf 8f4f dsb sy } 80006f0: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 80006f2: 4b2a ldr r3, [pc, #168] @ (800079c ) 80006f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80006f8: 60fb str r3, [r7, #12] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 80006fa: 68fb ldr r3, [r7, #12] 80006fc: 0b5b lsrs r3, r3, #13 80006fe: f3c3 030e ubfx r3, r3, #0, #15 8000702: 60bb str r3, [r7, #8] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000704: 68fb ldr r3, [r7, #12] 8000706: 08db lsrs r3, r3, #3 8000708: f3c3 0309 ubfx r3, r3, #0, #10 800070c: 607b str r3, [r7, #4] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800070e: 68bb ldr r3, [r7, #8] 8000710: 015a lsls r2, r3, #5 8000712: f643 73e0 movw r3, #16352 @ 0x3fe0 8000716: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 8000718: 687a ldr r2, [r7, #4] 800071a: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 800071c: 491f ldr r1, [pc, #124] @ (800079c ) 800071e: 4313 orrs r3, r2 8000720: f8c1 3260 str.w r3, [r1, #608] @ 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 8000724: 687b ldr r3, [r7, #4] 8000726: 1e5a subs r2, r3, #1 8000728: 607a str r2, [r7, #4] 800072a: 2b00 cmp r3, #0 800072c: d1ef bne.n 800070e } while(sets-- != 0U); 800072e: 68bb ldr r3, [r7, #8] 8000730: 1e5a subs r2, r3, #1 8000732: 60ba str r2, [r7, #8] 8000734: 2b00 cmp r3, #0 8000736: d1e5 bne.n 8000704 __ASM volatile ("dsb 0xF":::"memory"); 8000738: f3bf 8f4f dsb sy } 800073c: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800073e: 4b17 ldr r3, [pc, #92] @ (800079c ) 8000740: 695b ldr r3, [r3, #20] 8000742: 4a16 ldr r2, [pc, #88] @ (800079c ) 8000744: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000748: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800074a: f3bf 8f4f dsb sy } 800074e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000750: f3bf 8f6f isb sy } 8000754: e000 b.n 8000758 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000756: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000758: f001 ff32 bl 80025c0 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 800075c: f000 f826 bl 80007ac /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000760: f000 f9a4 bl 8000aac MX_DMA_Init(); 8000764: f000 f97a bl 8000a5c MX_UART8_Init(); 8000768: f000 f8dc bl 8000924 MX_CRC_Init(); 800076c: f000 f89a bl 80008a4 MX_RNG_Init(); 8000770: f000 f8c2 bl 80008f8 MX_USART1_UART_Init(); 8000774: f000 f922 bl 80009bc /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 8000778: f00a fe68 bl 800b44c /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 800077c: 4a08 ldr r2, [pc, #32] @ (80007a0 ) 800077e: 2100 movs r1, #0 8000780: 4808 ldr r0, [pc, #32] @ (80007a4 ) 8000782: f00a fead bl 800b4e0 8000786: 4603 mov r3, r0 8000788: 4a07 ldr r2, [pc, #28] @ (80007a8 ) 800078a: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ // Uart8TasksInit(); UartTasksInit(); 800078c: f001 f9f0 bl 8001b70 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); 8000790: f000 fa60 bl 8000c54 /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 8000794: f00a fe7e bl 800b494 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 8000798: bf00 nop 800079a: e7fd b.n 8000798 800079c: e000ed00 .word 0xe000ed00 80007a0: 0801008c .word 0x0801008c 80007a4: 08000b6d .word 0x08000b6d 80007a8: 240002dc .word 0x240002dc 080007ac : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80007ac: b580 push {r7, lr} 80007ae: b09c sub sp, #112 @ 0x70 80007b0: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80007b2: f107 0324 add.w r3, r7, #36 @ 0x24 80007b6: 224c movs r2, #76 @ 0x4c 80007b8: 2100 movs r1, #0 80007ba: 4618 mov r0, r3 80007bc: f00e fd6b bl 800f296 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80007c0: 1d3b adds r3, r7, #4 80007c2: 2220 movs r2, #32 80007c4: 2100 movs r1, #0 80007c6: 4618 mov r0, r3 80007c8: f00e fd65 bl 800f296 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 80007cc: 2002 movs r0, #2 80007ce: f004 fe93 bl 80054f8 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 80007d2: 2300 movs r3, #0 80007d4: 603b str r3, [r7, #0] 80007d6: 4b31 ldr r3, [pc, #196] @ (800089c ) 80007d8: 6adb ldr r3, [r3, #44] @ 0x2c 80007da: 4a30 ldr r2, [pc, #192] @ (800089c ) 80007dc: f023 0301 bic.w r3, r3, #1 80007e0: 62d3 str r3, [r2, #44] @ 0x2c 80007e2: 4b2e ldr r3, [pc, #184] @ (800089c ) 80007e4: 6adb ldr r3, [r3, #44] @ 0x2c 80007e6: f003 0301 and.w r3, r3, #1 80007ea: 603b str r3, [r7, #0] 80007ec: 4b2c ldr r3, [pc, #176] @ (80008a0 ) 80007ee: 699b ldr r3, [r3, #24] 80007f0: 4a2b ldr r2, [pc, #172] @ (80008a0 ) 80007f2: f443 4340 orr.w r3, r3, #49152 @ 0xc000 80007f6: 6193 str r3, [r2, #24] 80007f8: 4b29 ldr r3, [pc, #164] @ (80008a0 ) 80007fa: 699b ldr r3, [r3, #24] 80007fc: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000800: 603b str r3, [r7, #0] 8000802: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000804: bf00 nop 8000806: 4b26 ldr r3, [pc, #152] @ (80008a0 ) 8000808: 699b ldr r3, [r3, #24] 800080a: f403 5300 and.w r3, r3, #8192 @ 0x2000 800080e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8000812: d1f8 bne.n 8000806 /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; 8000814: 2321 movs r3, #33 @ 0x21 8000816: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000818: f44f 3380 mov.w r3, #65536 @ 0x10000 800081c: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 800081e: 2301 movs r3, #1 8000820: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000822: 2302 movs r3, #2 8000824: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000826: 2302 movs r3, #2 8000828: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 800082a: 2305 movs r3, #5 800082c: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 800082e: 23a0 movs r3, #160 @ 0xa0 8000830: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 8000832: 2302 movs r3, #2 8000834: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 8000836: 2302 movs r3, #2 8000838: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 800083a: 2302 movs r3, #2 800083c: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 800083e: 2308 movs r3, #8 8000840: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000842: 2300 movs r3, #0 8000844: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 8000846: 2300 movs r3, #0 8000848: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800084a: f107 0324 add.w r3, r7, #36 @ 0x24 800084e: 4618 mov r0, r3 8000850: f004 fe8c bl 800556c 8000854: 4603 mov r3, r0 8000856: 2b00 cmp r3, #0 8000858: d001 beq.n 800085e { Error_Handler(); 800085a: f000 f9f5 bl 8000c48 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800085e: 233f movs r3, #63 @ 0x3f 8000860: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000862: 2303 movs r3, #3 8000864: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 8000866: 2300 movs r3, #0 8000868: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 800086a: 2308 movs r3, #8 800086c: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 800086e: 2340 movs r3, #64 @ 0x40 8000870: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000872: 2340 movs r3, #64 @ 0x40 8000874: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000876: f44f 6380 mov.w r3, #1024 @ 0x400 800087a: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 800087c: 2340 movs r3, #64 @ 0x40 800087e: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8000880: 1d3b adds r3, r7, #4 8000882: 2102 movs r1, #2 8000884: 4618 mov r0, r3 8000886: f005 facb bl 8005e20 800088a: 4603 mov r3, r0 800088c: 2b00 cmp r3, #0 800088e: d001 beq.n 8000894 { Error_Handler(); 8000890: f000 f9da bl 8000c48 } } 8000894: bf00 nop 8000896: 3770 adds r7, #112 @ 0x70 8000898: 46bd mov sp, r7 800089a: bd80 pop {r7, pc} 800089c: 58000400 .word 0x58000400 80008a0: 58024800 .word 0x58024800 080008a4 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 80008a4: b580 push {r7, lr} 80008a6: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 80008a8: 4b11 ldr r3, [pc, #68] @ (80008f0 ) 80008aa: 4a12 ldr r2, [pc, #72] @ (80008f4 ) 80008ac: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 80008ae: 4b10 ldr r3, [pc, #64] @ (80008f0 ) 80008b0: 2201 movs r2, #1 80008b2: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 80008b4: 4b0e ldr r3, [pc, #56] @ (80008f0 ) 80008b6: 2200 movs r2, #0 80008b8: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 80008ba: 4b0d ldr r3, [pc, #52] @ (80008f0 ) 80008bc: f241 0221 movw r2, #4129 @ 0x1021 80008c0: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 80008c2: 4b0b ldr r3, [pc, #44] @ (80008f0 ) 80008c4: 2208 movs r2, #8 80008c6: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 80008c8: 4b09 ldr r3, [pc, #36] @ (80008f0 ) 80008ca: 2200 movs r2, #0 80008cc: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 80008ce: 4b08 ldr r3, [pc, #32] @ (80008f0 ) 80008d0: 2200 movs r2, #0 80008d2: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 80008d4: 4b06 ldr r3, [pc, #24] @ (80008f0 ) 80008d6: 2201 movs r2, #1 80008d8: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 80008da: 4805 ldr r0, [pc, #20] @ (80008f0 ) 80008dc: f002 f830 bl 8002940 80008e0: 4603 mov r3, r0 80008e2: 2b00 cmp r3, #0 80008e4: d001 beq.n 80008ea { Error_Handler(); 80008e6: f000 f9af bl 8000c48 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 80008ea: bf00 nop 80008ec: bd80 pop {r7, pc} 80008ee: bf00 nop 80008f0: 2400008c .word 0x2400008c 80008f4: 58024c00 .word 0x58024c00 080008f8 : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 80008f8: b580 push {r7, lr} 80008fa: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 80008fc: 4b07 ldr r3, [pc, #28] @ (800091c ) 80008fe: 4a08 ldr r2, [pc, #32] @ (8000920 ) 8000900: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 8000902: 4b06 ldr r3, [pc, #24] @ (800091c ) 8000904: 2200 movs r2, #0 8000906: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000908: 4804 ldr r0, [pc, #16] @ (800091c ) 800090a: f007 fc67 bl 80081dc 800090e: 4603 mov r3, r0 8000910: 2b00 cmp r3, #0 8000912: d001 beq.n 8000918 { Error_Handler(); 8000914: f000 f998 bl 8000c48 } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000918: bf00 nop 800091a: bd80 pop {r7, pc} 800091c: 240000b0 .word 0x240000b0 8000920: 48021800 .word 0x48021800 08000924 : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 8000924: b580 push {r7, lr} 8000926: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 8000928: 4b22 ldr r3, [pc, #136] @ (80009b4 ) 800092a: 4a23 ldr r2, [pc, #140] @ (80009b8 ) 800092c: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 800092e: 4b21 ldr r3, [pc, #132] @ (80009b4 ) 8000930: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8000934: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 8000936: 4b1f ldr r3, [pc, #124] @ (80009b4 ) 8000938: 2200 movs r2, #0 800093a: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 800093c: 4b1d ldr r3, [pc, #116] @ (80009b4 ) 800093e: 2200 movs r2, #0 8000940: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 8000942: 4b1c ldr r3, [pc, #112] @ (80009b4 ) 8000944: 2200 movs r2, #0 8000946: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 8000948: 4b1a ldr r3, [pc, #104] @ (80009b4 ) 800094a: 220c movs r2, #12 800094c: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800094e: 4b19 ldr r3, [pc, #100] @ (80009b4 ) 8000950: 2200 movs r2, #0 8000952: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 8000954: 4b17 ldr r3, [pc, #92] @ (80009b4 ) 8000956: 2200 movs r2, #0 8000958: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800095a: 4b16 ldr r3, [pc, #88] @ (80009b4 ) 800095c: 2200 movs r2, #0 800095e: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8000960: 4b14 ldr r3, [pc, #80] @ (80009b4 ) 8000962: 2200 movs r2, #0 8000964: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8000966: 4b13 ldr r3, [pc, #76] @ (80009b4 ) 8000968: 2200 movs r2, #0 800096a: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 800096c: 4811 ldr r0, [pc, #68] @ (80009b4 ) 800096e: f007 ff65 bl 800883c 8000972: 4603 mov r3, r0 8000974: 2b00 cmp r3, #0 8000976: d001 beq.n 800097c { Error_Handler(); 8000978: f000 f966 bl 8000c48 } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 800097c: 2100 movs r1, #0 800097e: 480d ldr r0, [pc, #52] @ (80009b4 ) 8000980: f00a fc05 bl 800b18e 8000984: 4603 mov r3, r0 8000986: 2b00 cmp r3, #0 8000988: d001 beq.n 800098e { Error_Handler(); 800098a: f000 f95d bl 8000c48 } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 800098e: 2100 movs r1, #0 8000990: 4808 ldr r0, [pc, #32] @ (80009b4 ) 8000992: f00a fc3a bl 800b20a 8000996: 4603 mov r3, r0 8000998: 2b00 cmp r3, #0 800099a: d001 beq.n 80009a0 { Error_Handler(); 800099c: f000 f954 bl 8000c48 } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 80009a0: 4804 ldr r0, [pc, #16] @ (80009b4 ) 80009a2: f00a fbbb bl 800b11c 80009a6: 4603 mov r3, r0 80009a8: 2b00 cmp r3, #0 80009aa: d001 beq.n 80009b0 { Error_Handler(); 80009ac: f000 f94c bl 8000c48 } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 80009b0: bf00 nop 80009b2: bd80 pop {r7, pc} 80009b4: 240000c4 .word 0x240000c4 80009b8: 40007c00 .word 0x40007c00 080009bc : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 80009bc: b580 push {r7, lr} 80009be: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80009c0: 4b24 ldr r3, [pc, #144] @ (8000a54 ) 80009c2: 4a25 ldr r2, [pc, #148] @ (8000a58 ) 80009c4: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80009c6: 4b23 ldr r3, [pc, #140] @ (8000a54 ) 80009c8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80009cc: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80009ce: 4b21 ldr r3, [pc, #132] @ (8000a54 ) 80009d0: 2200 movs r2, #0 80009d2: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80009d4: 4b1f ldr r3, [pc, #124] @ (8000a54 ) 80009d6: 2200 movs r2, #0 80009d8: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80009da: 4b1e ldr r3, [pc, #120] @ (8000a54 ) 80009dc: 2200 movs r2, #0 80009de: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80009e0: 4b1c ldr r3, [pc, #112] @ (8000a54 ) 80009e2: 220c movs r2, #12 80009e4: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80009e6: 4b1b ldr r3, [pc, #108] @ (8000a54 ) 80009e8: 2200 movs r2, #0 80009ea: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80009ec: 4b19 ldr r3, [pc, #100] @ (8000a54 ) 80009ee: 2200 movs r2, #0 80009f0: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80009f2: 4b18 ldr r3, [pc, #96] @ (8000a54 ) 80009f4: 2200 movs r2, #0 80009f6: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80009f8: 4b16 ldr r3, [pc, #88] @ (8000a54 ) 80009fa: 2200 movs r2, #0 80009fc: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXINVERT_INIT; 80009fe: 4b15 ldr r3, [pc, #84] @ (8000a54 ) 8000a00: 2202 movs r2, #2 8000a02: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.RxPinLevelInvert = UART_ADVFEATURE_RXINV_ENABLE; 8000a04: 4b13 ldr r3, [pc, #76] @ (8000a54 ) 8000a06: f44f 3280 mov.w r2, #65536 @ 0x10000 8000a0a: 631a str r2, [r3, #48] @ 0x30 if (HAL_UART_Init(&huart1) != HAL_OK) 8000a0c: 4811 ldr r0, [pc, #68] @ (8000a54 ) 8000a0e: f007 ff15 bl 800883c 8000a12: 4603 mov r3, r0 8000a14: 2b00 cmp r3, #0 8000a16: d001 beq.n 8000a1c { Error_Handler(); 8000a18: f000 f916 bl 8000c48 } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8000a1c: 2100 movs r1, #0 8000a1e: 480d ldr r0, [pc, #52] @ (8000a54 ) 8000a20: f00a fbb5 bl 800b18e 8000a24: 4603 mov r3, r0 8000a26: 2b00 cmp r3, #0 8000a28: d001 beq.n 8000a2e { Error_Handler(); 8000a2a: f000 f90d bl 8000c48 } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8000a2e: 2100 movs r1, #0 8000a30: 4808 ldr r0, [pc, #32] @ (8000a54 ) 8000a32: f00a fbea bl 800b20a 8000a36: 4603 mov r3, r0 8000a38: 2b00 cmp r3, #0 8000a3a: d001 beq.n 8000a40 { Error_Handler(); 8000a3c: f000 f904 bl 8000c48 } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 8000a40: 4804 ldr r0, [pc, #16] @ (8000a54 ) 8000a42: f00a fb6b bl 800b11c 8000a46: 4603 mov r3, r0 8000a48: 2b00 cmp r3, #0 8000a4a: d001 beq.n 8000a50 { Error_Handler(); 8000a4c: f000 f8fc bl 8000c48 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8000a50: bf00 nop 8000a52: bd80 pop {r7, pc} 8000a54: 24000158 .word 0x24000158 8000a58: 40011000 .word 0x40011000 08000a5c : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8000a5c: b580 push {r7, lr} 8000a5e: b082 sub sp, #8 8000a60: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA2_CLK_ENABLE(); 8000a62: 4b11 ldr r3, [pc, #68] @ (8000aa8 ) 8000a64: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8000a68: 4a0f ldr r2, [pc, #60] @ (8000aa8 ) 8000a6a: f043 0302 orr.w r3, r3, #2 8000a6e: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8000a72: 4b0d ldr r3, [pc, #52] @ (8000aa8 ) 8000a74: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8000a78: f003 0302 and.w r3, r3, #2 8000a7c: 607b str r3, [r7, #4] 8000a7e: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA2_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); 8000a80: 2200 movs r2, #0 8000a82: 2105 movs r1, #5 8000a84: 2045 movs r0, #69 @ 0x45 8000a86: f001 febb bl 8002800 HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); 8000a8a: 2045 movs r0, #69 @ 0x45 8000a8c: f001 fed2 bl 8002834 /* DMA2_Stream7_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 5, 0); 8000a90: 2200 movs r2, #0 8000a92: 2105 movs r1, #5 8000a94: 2046 movs r0, #70 @ 0x46 8000a96: f001 feb3 bl 8002800 HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); 8000a9a: 2046 movs r0, #70 @ 0x46 8000a9c: f001 feca bl 8002834 } 8000aa0: bf00 nop 8000aa2: 3708 adds r7, #8 8000aa4: 46bd mov sp, r7 8000aa6: bd80 pop {r7, pc} 8000aa8: 58024400 .word 0x58024400 08000aac : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000aac: b580 push {r7, lr} 8000aae: b08a sub sp, #40 @ 0x28 8000ab0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000ab2: f107 0314 add.w r3, r7, #20 8000ab6: 2200 movs r2, #0 8000ab8: 601a str r2, [r3, #0] 8000aba: 605a str r2, [r3, #4] 8000abc: 609a str r2, [r3, #8] 8000abe: 60da str r2, [r3, #12] 8000ac0: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 8000ac2: 4b28 ldr r3, [pc, #160] @ (8000b64 ) 8000ac4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000ac8: 4a26 ldr r2, [pc, #152] @ (8000b64 ) 8000aca: f043 0380 orr.w r3, r3, #128 @ 0x80 8000ace: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000ad2: 4b24 ldr r3, [pc, #144] @ (8000b64 ) 8000ad4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000ad8: f003 0380 and.w r3, r3, #128 @ 0x80 8000adc: 613b str r3, [r7, #16] 8000ade: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000ae0: 4b20 ldr r3, [pc, #128] @ (8000b64 ) 8000ae2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000ae6: 4a1f ldr r2, [pc, #124] @ (8000b64 ) 8000ae8: f043 0302 orr.w r3, r3, #2 8000aec: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000af0: 4b1c ldr r3, [pc, #112] @ (8000b64 ) 8000af2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000af6: f003 0302 and.w r3, r3, #2 8000afa: 60fb str r3, [r7, #12] 8000afc: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000afe: 4b19 ldr r3, [pc, #100] @ (8000b64 ) 8000b00: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000b04: 4a17 ldr r2, [pc, #92] @ (8000b64 ) 8000b06: f043 0301 orr.w r3, r3, #1 8000b0a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000b0e: 4b15 ldr r3, [pc, #84] @ (8000b64 ) 8000b10: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000b14: f003 0301 and.w r3, r3, #1 8000b18: 60bb str r3, [r7, #8] 8000b1a: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000b1c: 4b11 ldr r3, [pc, #68] @ (8000b64 ) 8000b1e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000b22: 4a10 ldr r2, [pc, #64] @ (8000b64 ) 8000b24: f043 0310 orr.w r3, r3, #16 8000b28: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8000b2c: 4b0d ldr r3, [pc, #52] @ (8000b64 ) 8000b2e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8000b32: f003 0310 and.w r3, r3, #16 8000b36: 607b str r3, [r7, #4] 8000b38: 687b ldr r3, [r7, #4] /*Configure GPIO pin : PB8 */ GPIO_InitStruct.Pin = GPIO_PIN_8; 8000b3a: f44f 7380 mov.w r3, #256 @ 0x100 8000b3e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8000b40: 2302 movs r3, #2 8000b42: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000b44: 2300 movs r3, #0 8000b46: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8000b48: 2303 movs r3, #3 8000b4a: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF11_ETH; 8000b4c: 230b movs r3, #11 8000b4e: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8000b50: f107 0314 add.w r3, r7, #20 8000b54: 4619 mov r1, r3 8000b56: 4804 ldr r0, [pc, #16] @ (8000b68 ) 8000b58: f004 fb1e bl 8005198 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000b5c: bf00 nop 8000b5e: 3728 adds r7, #40 @ 0x28 8000b60: 46bd mov sp, r7 8000b62: bd80 pop {r7, pc} 8000b64: 58024400 .word 0x58024400 8000b68: 58020400 .word 0x58020400 08000b6c : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 8000b6c: b580 push {r7, lr} 8000b6e: b082 sub sp, #8 8000b70: af00 add r7, sp, #0 8000b72: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(1000)); 8000b74: f44f 707a mov.w r0, #1000 @ 0x3e8 8000b78: f00a fd45 bl 800b606 8000b7c: e7fa b.n 8000b74 ... 08000b80 : } /* MPU Configuration */ void MPU_Config(void) { 8000b80: b580 push {r7, lr} 8000b82: b084 sub sp, #16 8000b84: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8000b86: 463b mov r3, r7 8000b88: 2200 movs r2, #0 8000b8a: 601a str r2, [r3, #0] 8000b8c: 605a str r2, [r3, #4] 8000b8e: 609a str r2, [r3, #8] 8000b90: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8000b92: f001 fe5d bl 8002850 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8000b96: 2301 movs r3, #1 8000b98: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8000b9a: 2300 movs r3, #0 8000b9c: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8000b9e: 2300 movs r3, #0 8000ba0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8000ba2: 231f movs r3, #31 8000ba4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8000ba6: 2387 movs r3, #135 @ 0x87 8000ba8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8000baa: 2300 movs r3, #0 8000bac: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8000bae: 2300 movs r3, #0 8000bb0: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8000bb2: 2301 movs r3, #1 8000bb4: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8000bb6: 2301 movs r3, #1 8000bb8: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8000bba: 2300 movs r3, #0 8000bbc: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8000bbe: 2300 movs r3, #0 8000bc0: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8000bc2: 463b mov r3, r7 8000bc4: 4618 mov r0, r3 8000bc6: f001 fe7b bl 80028c0 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8000bca: 2301 movs r3, #1 8000bcc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 8000bce: 4b13 ldr r3, [pc, #76] @ (8000c1c ) 8000bd0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8000bd2: 2310 movs r3, #16 8000bd4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 8000bd6: 2300 movs r3, #0 8000bd8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8000bda: 2301 movs r3, #1 8000bdc: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8000bde: 2303 movs r3, #3 8000be0: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8000be2: 2300 movs r3, #0 8000be4: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8000be6: 463b mov r3, r7 8000be8: 4618 mov r0, r3 8000bea: f001 fe69 bl 80028c0 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8000bee: 2302 movs r3, #2 8000bf0: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 8000bf2: 4b0b ldr r3, [pc, #44] @ (8000c20 ) 8000bf4: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8000bf6: 2308 movs r3, #8 8000bf8: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8000bfa: 2300 movs r3, #0 8000bfc: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8000bfe: 2301 movs r3, #1 8000c00: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8000c02: 2301 movs r3, #1 8000c04: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8000c06: 463b mov r3, r7 8000c08: 4618 mov r0, r3 8000c0a: f001 fe59 bl 80028c0 /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8000c0e: 2004 movs r0, #4 8000c10: f001 fe36 bl 8002880 } 8000c14: bf00 nop 8000c16: 3710 adds r7, #16 8000c18: 46bd mov sp, r7 8000c1a: bd80 pop {r7, pc} 8000c1c: 24020000 .word 0x24020000 8000c20: 24040000 .word 0x24040000 08000c24 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8000c24: b580 push {r7, lr} 8000c26: b082 sub sp, #8 8000c28: af00 add r7, sp, #0 8000c2a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8000c2c: 687b ldr r3, [r7, #4] 8000c2e: 681b ldr r3, [r3, #0] 8000c30: 4a04 ldr r2, [pc, #16] @ (8000c44 ) 8000c32: 4293 cmp r3, r2 8000c34: d101 bne.n 8000c3a HAL_IncTick(); 8000c36: f001 fcff bl 8002638 } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } 8000c3a: bf00 nop 8000c3c: 3708 adds r7, #8 8000c3e: 46bd mov sp, r7 8000c40: bd80 pop {r7, pc} 8000c42: bf00 nop 8000c44: 40001000 .word 0x40001000 08000c48 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000c48: b480 push {r7} 8000c4a: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8000c4c: b672 cpsid i } 8000c4e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000c50: bf00 nop 8000c52: e7fd b.n 8000c50 08000c54 : (void)rng; return 0.0; } #endif void MockMeasurmetsTaskInit(void) { 8000c54: b580 push {r7, lr} 8000c56: b08a sub sp, #40 @ 0x28 8000c58: af00 add r7, sp, #0 osThreadAttr_t osThreadAttrMockMeasTask = { 0 }; 8000c5a: 1d3b adds r3, r7, #4 8000c5c: 2224 movs r2, #36 @ 0x24 8000c5e: 2100 movs r1, #0 8000c60: 4618 mov r0, r3 8000c62: f00e fb18 bl 800f296 osThreadAttrMockMeasTask.name = "os_thread_mock_measurmets"; 8000c66: 4b08 ldr r3, [pc, #32] @ (8000c88 ) 8000c68: 607b str r3, [r7, #4] osThreadAttrMockMeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8000c6a: f44f 6380 mov.w r3, #1024 @ 0x400 8000c6e: 61bb str r3, [r7, #24] osThreadAttrMockMeasTask.priority = (osPriority_t)osPriorityNormal; 8000c70: 2318 movs r3, #24 8000c72: 61fb str r3, [r7, #28] osThreadNew (MockMeasurmetsTask, NULL, &osThreadAttrMockMeasTask); 8000c74: 1d3b adds r3, r7, #4 8000c76: 461a mov r2, r3 8000c78: 2100 movs r1, #0 8000c7a: 4804 ldr r0, [pc, #16] @ (8000c8c ) 8000c7c: f00a fc30 bl 800b4e0 } 8000c80: bf00 nop 8000c82: 3728 adds r7, #40 @ 0x28 8000c84: 46bd mov sp, r7 8000c86: bd80 pop {r7, pc} 8000c88: 0800ffb4 .word 0x0800ffb4 8000c8c: 08000c91 .word 0x08000c91 08000c90 : void MockMeasurmetsTask (void* argument) { 8000c90: b580 push {r7, lr} 8000c92: b084 sub sp, #16 8000c94: af00 add r7, sp, #0 8000c96: 6078 str r0, [r7, #4] uint16_t counter = 0; 8000c98: 2300 movs r3, #0 8000c9a: 81fb strh r3, [r7, #14] while (pdTRUE) { osMutexAcquire (resMeasurementsMutex, osWaitForever); 8000c9c: 4bda ldr r3, [pc, #872] @ (8001008 ) 8000c9e: 681b ldr r3, [r3, #0] 8000ca0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8000ca4: 4618 mov r0, r3 8000ca6: f00a fd4f bl 800b748 resMeasurements.voltagePeak[0] = 60 + (0.01 * (counter % 100)); 8000caa: 89fb ldrh r3, [r7, #14] 8000cac: 4ad7 ldr r2, [pc, #860] @ (800100c ) 8000cae: fba2 1203 umull r1, r2, r2, r3 8000cb2: 0952 lsrs r2, r2, #5 8000cb4: 2164 movs r1, #100 @ 0x64 8000cb6: fb01 f202 mul.w r2, r1, r2 8000cba: 1a9b subs r3, r3, r2 8000cbc: b29b uxth r3, r3 8000cbe: ee07 3a90 vmov s15, r3 8000cc2: eeb8 7be7 vcvt.f64.s32 d7, s15 8000cc6: ed9f 6bc0 vldr d6, [pc, #768] @ 8000fc8 8000cca: ee27 7b06 vmul.f64 d7, d7, d6 8000cce: ed9f 6bc0 vldr d6, [pc, #768] @ 8000fd0 8000cd2: ee37 7b06 vadd.f64 d7, d7, d6 8000cd6: eef7 7bc7 vcvt.f32.f64 s15, d7 8000cda: 4bcd ldr r3, [pc, #820] @ (8001010 ) 8000cdc: edc3 7a03 vstr s15, [r3, #12] resMeasurements.voltagePeak[1] = 61 + (0.01 * (counter % 100)); 8000ce0: 89fb ldrh r3, [r7, #14] 8000ce2: 4aca ldr r2, [pc, #808] @ (800100c ) 8000ce4: fba2 1203 umull r1, r2, r2, r3 8000ce8: 0952 lsrs r2, r2, #5 8000cea: 2164 movs r1, #100 @ 0x64 8000cec: fb01 f202 mul.w r2, r1, r2 8000cf0: 1a9b subs r3, r3, r2 8000cf2: b29b uxth r3, r3 8000cf4: ee07 3a90 vmov s15, r3 8000cf8: eeb8 7be7 vcvt.f64.s32 d7, s15 8000cfc: ed9f 6bb2 vldr d6, [pc, #712] @ 8000fc8 8000d00: ee27 7b06 vmul.f64 d7, d7, d6 8000d04: ed9f 6bb4 vldr d6, [pc, #720] @ 8000fd8 8000d08: ee37 7b06 vadd.f64 d7, d7, d6 8000d0c: eef7 7bc7 vcvt.f32.f64 s15, d7 8000d10: 4bbf ldr r3, [pc, #764] @ (8001010 ) 8000d12: edc3 7a04 vstr s15, [r3, #16] resMeasurements.voltagePeak[2] = 62 + (0.01 * (counter % 100)); 8000d16: 89fb ldrh r3, [r7, #14] 8000d18: 4abc ldr r2, [pc, #752] @ (800100c ) 8000d1a: fba2 1203 umull r1, r2, r2, r3 8000d1e: 0952 lsrs r2, r2, #5 8000d20: 2164 movs r1, #100 @ 0x64 8000d22: fb01 f202 mul.w r2, r1, r2 8000d26: 1a9b subs r3, r3, r2 8000d28: b29b uxth r3, r3 8000d2a: ee07 3a90 vmov s15, r3 8000d2e: eeb8 7be7 vcvt.f64.s32 d7, s15 8000d32: ed9f 6ba5 vldr d6, [pc, #660] @ 8000fc8 8000d36: ee27 7b06 vmul.f64 d7, d7, d6 8000d3a: ed9f 6ba9 vldr d6, [pc, #676] @ 8000fe0 8000d3e: ee37 7b06 vadd.f64 d7, d7, d6 8000d42: eef7 7bc7 vcvt.f32.f64 s15, d7 8000d46: 4bb2 ldr r3, [pc, #712] @ (8001010 ) 8000d48: edc3 7a05 vstr s15, [r3, #20] resMeasurements.voltageRMS[0] = 46 + (0.01 * (counter % 100)); 8000d4c: 89fb ldrh r3, [r7, #14] 8000d4e: 4aaf ldr r2, [pc, #700] @ (800100c ) 8000d50: fba2 1203 umull r1, r2, r2, r3 8000d54: 0952 lsrs r2, r2, #5 8000d56: 2164 movs r1, #100 @ 0x64 8000d58: fb01 f202 mul.w r2, r1, r2 8000d5c: 1a9b subs r3, r3, r2 8000d5e: b29b uxth r3, r3 8000d60: ee07 3a90 vmov s15, r3 8000d64: eeb8 7be7 vcvt.f64.s32 d7, s15 8000d68: ed9f 6b97 vldr d6, [pc, #604] @ 8000fc8 8000d6c: ee27 7b06 vmul.f64 d7, d7, d6 8000d70: ed9f 6b9d vldr d6, [pc, #628] @ 8000fe8 8000d74: ee37 7b06 vadd.f64 d7, d7, d6 8000d78: eef7 7bc7 vcvt.f32.f64 s15, d7 8000d7c: 4ba4 ldr r3, [pc, #656] @ (8001010 ) 8000d7e: edc3 7a00 vstr s15, [r3] resMeasurements.voltageRMS[1] = 47 + (0.01 * (counter % 100)); 8000d82: 89fb ldrh r3, [r7, #14] 8000d84: 4aa1 ldr r2, [pc, #644] @ (800100c ) 8000d86: fba2 1203 umull r1, r2, r2, r3 8000d8a: 0952 lsrs r2, r2, #5 8000d8c: 2164 movs r1, #100 @ 0x64 8000d8e: fb01 f202 mul.w r2, r1, r2 8000d92: 1a9b subs r3, r3, r2 8000d94: b29b uxth r3, r3 8000d96: ee07 3a90 vmov s15, r3 8000d9a: eeb8 7be7 vcvt.f64.s32 d7, s15 8000d9e: ed9f 6b8a vldr d6, [pc, #552] @ 8000fc8 8000da2: ee27 7b06 vmul.f64 d7, d7, d6 8000da6: ed9f 6b92 vldr d6, [pc, #584] @ 8000ff0 8000daa: ee37 7b06 vadd.f64 d7, d7, d6 8000dae: eef7 7bc7 vcvt.f32.f64 s15, d7 8000db2: 4b97 ldr r3, [pc, #604] @ (8001010 ) 8000db4: edc3 7a01 vstr s15, [r3, #4] resMeasurements.voltageRMS[2] = 48 + (0.01 * (counter % 100)); 8000db8: 89fb ldrh r3, [r7, #14] 8000dba: 4a94 ldr r2, [pc, #592] @ (800100c ) 8000dbc: fba2 1203 umull r1, r2, r2, r3 8000dc0: 0952 lsrs r2, r2, #5 8000dc2: 2164 movs r1, #100 @ 0x64 8000dc4: fb01 f202 mul.w r2, r1, r2 8000dc8: 1a9b subs r3, r3, r2 8000dca: b29b uxth r3, r3 8000dcc: ee07 3a90 vmov s15, r3 8000dd0: eeb8 7be7 vcvt.f64.s32 d7, s15 8000dd4: ed9f 6b7c vldr d6, [pc, #496] @ 8000fc8 8000dd8: ee27 7b06 vmul.f64 d7, d7, d6 8000ddc: ed9f 6b86 vldr d6, [pc, #536] @ 8000ff8 8000de0: ee37 7b06 vadd.f64 d7, d7, d6 8000de4: eef7 7bc7 vcvt.f32.f64 s15, d7 8000de8: 4b89 ldr r3, [pc, #548] @ (8001010 ) 8000dea: edc3 7a02 vstr s15, [r3, #8] resMeasurements.currentPeak[0] = 3 + (0.01 * (counter % 100)); 8000dee: 89fb ldrh r3, [r7, #14] 8000df0: 4a86 ldr r2, [pc, #536] @ (800100c ) 8000df2: fba2 1203 umull r1, r2, r2, r3 8000df6: 0952 lsrs r2, r2, #5 8000df8: 2164 movs r1, #100 @ 0x64 8000dfa: fb01 f202 mul.w r2, r1, r2 8000dfe: 1a9b subs r3, r3, r2 8000e00: b29b uxth r3, r3 8000e02: ee07 3a90 vmov s15, r3 8000e06: eeb8 7be7 vcvt.f64.s32 d7, s15 8000e0a: ed9f 6b6f vldr d6, [pc, #444] @ 8000fc8 8000e0e: ee27 7b06 vmul.f64 d7, d7, d6 8000e12: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8000e16: ee37 7b06 vadd.f64 d7, d7, d6 8000e1a: eef7 7bc7 vcvt.f32.f64 s15, d7 8000e1e: 4b7c ldr r3, [pc, #496] @ (8001010 ) 8000e20: edc3 7a09 vstr s15, [r3, #36] @ 0x24 resMeasurements.currentPeak[1] = 4 + (0.01 * (counter % 100)); 8000e24: 89fb ldrh r3, [r7, #14] 8000e26: 4a79 ldr r2, [pc, #484] @ (800100c ) 8000e28: fba2 1203 umull r1, r2, r2, r3 8000e2c: 0952 lsrs r2, r2, #5 8000e2e: 2164 movs r1, #100 @ 0x64 8000e30: fb01 f202 mul.w r2, r1, r2 8000e34: 1a9b subs r3, r3, r2 8000e36: b29b uxth r3, r3 8000e38: ee07 3a90 vmov s15, r3 8000e3c: eeb8 7be7 vcvt.f64.s32 d7, s15 8000e40: ed9f 6b61 vldr d6, [pc, #388] @ 8000fc8 8000e44: ee27 7b06 vmul.f64 d7, d7, d6 8000e48: eeb1 6b00 vmov.f64 d6, #16 @ 0x40800000 4.0 8000e4c: ee37 7b06 vadd.f64 d7, d7, d6 8000e50: eef7 7bc7 vcvt.f32.f64 s15, d7 8000e54: 4b6e ldr r3, [pc, #440] @ (8001010 ) 8000e56: edc3 7a0a vstr s15, [r3, #40] @ 0x28 resMeasurements.currentPeak[2] = 5 + (0.01 * (counter % 100)); 8000e5a: 89fb ldrh r3, [r7, #14] 8000e5c: 4a6b ldr r2, [pc, #428] @ (800100c ) 8000e5e: fba2 1203 umull r1, r2, r2, r3 8000e62: 0952 lsrs r2, r2, #5 8000e64: 2164 movs r1, #100 @ 0x64 8000e66: fb01 f202 mul.w r2, r1, r2 8000e6a: 1a9b subs r3, r3, r2 8000e6c: b29b uxth r3, r3 8000e6e: ee07 3a90 vmov s15, r3 8000e72: eeb8 7be7 vcvt.f64.s32 d7, s15 8000e76: ed9f 6b54 vldr d6, [pc, #336] @ 8000fc8 8000e7a: ee27 7b06 vmul.f64 d7, d7, d6 8000e7e: eeb1 6b04 vmov.f64 d6, #20 @ 0x40a00000 5.0 8000e82: ee37 7b06 vadd.f64 d7, d7, d6 8000e86: eef7 7bc7 vcvt.f32.f64 s15, d7 8000e8a: 4b61 ldr r3, [pc, #388] @ (8001010 ) 8000e8c: edc3 7a0b vstr s15, [r3, #44] @ 0x2c resMeasurements.currentRMS[0] = 1 + (0.01 * (counter % 100)); 8000e90: 89fb ldrh r3, [r7, #14] 8000e92: 4a5e ldr r2, [pc, #376] @ (800100c ) 8000e94: fba2 1203 umull r1, r2, r2, r3 8000e98: 0952 lsrs r2, r2, #5 8000e9a: 2164 movs r1, #100 @ 0x64 8000e9c: fb01 f202 mul.w r2, r1, r2 8000ea0: 1a9b subs r3, r3, r2 8000ea2: b29b uxth r3, r3 8000ea4: ee07 3a90 vmov s15, r3 8000ea8: eeb8 7be7 vcvt.f64.s32 d7, s15 8000eac: ed9f 6b46 vldr d6, [pc, #280] @ 8000fc8 8000eb0: ee27 7b06 vmul.f64 d7, d7, d6 8000eb4: eeb7 6b00 vmov.f64 d6, #112 @ 0x3f800000 1.0 8000eb8: ee37 7b06 vadd.f64 d7, d7, d6 8000ebc: eef7 7bc7 vcvt.f32.f64 s15, d7 8000ec0: 4b53 ldr r3, [pc, #332] @ (8001010 ) 8000ec2: edc3 7a06 vstr s15, [r3, #24] resMeasurements.currentRMS[1] = 2 + (0.01 * (counter % 100)); 8000ec6: 89fb ldrh r3, [r7, #14] 8000ec8: 4a50 ldr r2, [pc, #320] @ (800100c ) 8000eca: fba2 1203 umull r1, r2, r2, r3 8000ece: 0952 lsrs r2, r2, #5 8000ed0: 2164 movs r1, #100 @ 0x64 8000ed2: fb01 f202 mul.w r2, r1, r2 8000ed6: 1a9b subs r3, r3, r2 8000ed8: b29b uxth r3, r3 8000eda: ee07 3a90 vmov s15, r3 8000ede: eeb8 7be7 vcvt.f64.s32 d7, s15 8000ee2: ed9f 6b39 vldr d6, [pc, #228] @ 8000fc8 8000ee6: ee27 7b06 vmul.f64 d7, d7, d6 8000eea: eeb0 6b00 vmov.f64 d6, #0 @ 0x40000000 2.0 8000eee: ee37 7b06 vadd.f64 d7, d7, d6 8000ef2: eef7 7bc7 vcvt.f32.f64 s15, d7 8000ef6: 4b46 ldr r3, [pc, #280] @ (8001010 ) 8000ef8: edc3 7a07 vstr s15, [r3, #28] resMeasurements.currentRMS[2] = 3 + (0.01 * (counter % 100)); 8000efc: 89fb ldrh r3, [r7, #14] 8000efe: 4a43 ldr r2, [pc, #268] @ (800100c ) 8000f00: fba2 1203 umull r1, r2, r2, r3 8000f04: 0952 lsrs r2, r2, #5 8000f06: 2164 movs r1, #100 @ 0x64 8000f08: fb01 f202 mul.w r2, r1, r2 8000f0c: 1a9b subs r3, r3, r2 8000f0e: b29b uxth r3, r3 8000f10: ee07 3a90 vmov s15, r3 8000f14: eeb8 7be7 vcvt.f64.s32 d7, s15 8000f18: ed9f 6b2b vldr d6, [pc, #172] @ 8000fc8 8000f1c: ee27 7b06 vmul.f64 d7, d7, d6 8000f20: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8000f24: ee37 7b06 vadd.f64 d7, d7, d6 8000f28: eef7 7bc7 vcvt.f32.f64 s15, d7 8000f2c: 4b38 ldr r3, [pc, #224] @ (8001010 ) 8000f2e: edc3 7a08 vstr s15, [r3, #32] resMeasurements.power[0] = resMeasurements.voltagePeak[0] * resMeasurements.currentRMS[0]; 8000f32: 4b37 ldr r3, [pc, #220] @ (8001010 ) 8000f34: ed93 7a03 vldr s14, [r3, #12] 8000f38: 4b35 ldr r3, [pc, #212] @ (8001010 ) 8000f3a: edd3 7a06 vldr s15, [r3, #24] 8000f3e: ee67 7a27 vmul.f32 s15, s14, s15 8000f42: 4b33 ldr r3, [pc, #204] @ (8001010 ) 8000f44: edc3 7a0c vstr s15, [r3, #48] @ 0x30 resMeasurements.power[1] = resMeasurements.voltagePeak[1] * resMeasurements.currentRMS[1]; 8000f48: 4b31 ldr r3, [pc, #196] @ (8001010 ) 8000f4a: ed93 7a04 vldr s14, [r3, #16] 8000f4e: 4b30 ldr r3, [pc, #192] @ (8001010 ) 8000f50: edd3 7a07 vldr s15, [r3, #28] 8000f54: ee67 7a27 vmul.f32 s15, s14, s15 8000f58: 4b2d ldr r3, [pc, #180] @ (8001010 ) 8000f5a: edc3 7a0d vstr s15, [r3, #52] @ 0x34 resMeasurements.power[2] = resMeasurements.voltagePeak[2] * resMeasurements.currentRMS[2]; 8000f5e: 4b2c ldr r3, [pc, #176] @ (8001010 ) 8000f60: ed93 7a05 vldr s14, [r3, #20] 8000f64: 4b2a ldr r3, [pc, #168] @ (8001010 ) 8000f66: edd3 7a08 vldr s15, [r3, #32] 8000f6a: ee67 7a27 vmul.f32 s15, s14, s15 8000f6e: 4b28 ldr r3, [pc, #160] @ (8001010 ) 8000f70: edc3 7a0e vstr s15, [r3, #56] @ 0x38 osMutexRelease(resMeasurementsMutex); 8000f74: 4b24 ldr r3, [pc, #144] @ (8001008 ) 8000f76: 681b ldr r3, [r3, #0] 8000f78: 4618 mov r0, r3 8000f7a: f00a fc30 bl 800b7de osMutexAcquire (sensorsInfoMutex, osWaitForever); 8000f7e: 4b25 ldr r3, [pc, #148] @ (8001014 ) 8000f80: 681b ldr r3, [r3, #0] 8000f82: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8000f86: 4618 mov r0, r3 8000f88: f00a fbde bl 800b748 sensorsInfo.pvTemperature[0] = 50 + (0.01 * (counter % 100)); 8000f8c: 89fb ldrh r3, [r7, #14] 8000f8e: 4a1f ldr r2, [pc, #124] @ (800100c ) 8000f90: fba2 1203 umull r1, r2, r2, r3 8000f94: 0952 lsrs r2, r2, #5 8000f96: 2164 movs r1, #100 @ 0x64 8000f98: fb01 f202 mul.w r2, r1, r2 8000f9c: 1a9b subs r3, r3, r2 8000f9e: b29b uxth r3, r3 8000fa0: ee07 3a90 vmov s15, r3 8000fa4: eeb8 7be7 vcvt.f64.s32 d7, s15 8000fa8: ed9f 6b07 vldr d6, [pc, #28] @ 8000fc8 8000fac: ee27 7b06 vmul.f64 d7, d7, d6 8000fb0: ed9f 6b13 vldr d6, [pc, #76] @ 8001000 8000fb4: ee37 7b06 vadd.f64 d7, d7, d6 8000fb8: eef7 7bc7 vcvt.f32.f64 s15, d7 8000fbc: 4b16 ldr r3, [pc, #88] @ (8001018 ) 8000fbe: edc3 7a00 vstr s15, [r3] sensorsInfo.pvTemperature[1] = 51 + (0.01 * (counter % 100)); 8000fc2: 89fb ldrh r3, [r7, #14] 8000fc4: e02a b.n 800101c 8000fc6: bf00 nop 8000fc8: 47ae147b .word 0x47ae147b 8000fcc: 3f847ae1 .word 0x3f847ae1 8000fd0: 00000000 .word 0x00000000 8000fd4: 404e0000 .word 0x404e0000 8000fd8: 00000000 .word 0x00000000 8000fdc: 404e8000 .word 0x404e8000 8000fe0: 00000000 .word 0x00000000 8000fe4: 404f0000 .word 0x404f0000 8000fe8: 00000000 .word 0x00000000 8000fec: 40470000 .word 0x40470000 8000ff0: 00000000 .word 0x00000000 8000ff4: 40478000 .word 0x40478000 8000ff8: 00000000 .word 0x00000000 8000ffc: 40480000 .word 0x40480000 8001000: 00000000 .word 0x00000000 8001004: 40490000 .word 0x40490000 8001008: 24000788 .word 0x24000788 800100c: 51eb851f .word 0x51eb851f 8001010: 24000724 .word 0x24000724 8001014: 2400078c .word 0x2400078c 8001018: 24000760 .word 0x24000760 800101c: 4a9a ldr r2, [pc, #616] @ (8001288 ) 800101e: fba2 1203 umull r1, r2, r2, r3 8001022: 0952 lsrs r2, r2, #5 8001024: 2164 movs r1, #100 @ 0x64 8001026: fb01 f202 mul.w r2, r1, r2 800102a: 1a9b subs r3, r3, r2 800102c: b29b uxth r3, r3 800102e: ee07 3a90 vmov s15, r3 8001032: eeb8 7be7 vcvt.f64.s32 d7, s15 8001036: ed9f 6b90 vldr d6, [pc, #576] @ 8001278 800103a: ee27 7b06 vmul.f64 d7, d7, d6 800103e: ed9f 6b90 vldr d6, [pc, #576] @ 8001280 8001042: ee37 7b06 vadd.f64 d7, d7, d6 8001046: eef7 7bc7 vcvt.f32.f64 s15, d7 800104a: 4b90 ldr r3, [pc, #576] @ (800128c ) 800104c: edc3 7a01 vstr s15, [r3, #4] sensorsInfo.fanVoltage = 12 + (0.01 * (counter % 100)); 8001050: 89fb ldrh r3, [r7, #14] 8001052: 4a8d ldr r2, [pc, #564] @ (8001288 ) 8001054: fba2 1203 umull r1, r2, r2, r3 8001058: 0952 lsrs r2, r2, #5 800105a: 2164 movs r1, #100 @ 0x64 800105c: fb01 f202 mul.w r2, r1, r2 8001060: 1a9b subs r3, r3, r2 8001062: b29b uxth r3, r3 8001064: ee07 3a90 vmov s15, r3 8001068: eeb8 7be7 vcvt.f64.s32 d7, s15 800106c: ed9f 6b82 vldr d6, [pc, #520] @ 8001278 8001070: ee27 7b06 vmul.f64 d7, d7, d6 8001074: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 8001078: ee37 7b06 vadd.f64 d7, d7, d6 800107c: eef7 7bc7 vcvt.f32.f64 s15, d7 8001080: 4b82 ldr r3, [pc, #520] @ (800128c ) 8001082: edc3 7a02 vstr s15, [r3, #8] sensorsInfo.pvEncoder = 15 + (0.01 * (counter % 100)); 8001086: 89fb ldrh r3, [r7, #14] 8001088: 4a7f ldr r2, [pc, #508] @ (8001288 ) 800108a: fba2 1203 umull r1, r2, r2, r3 800108e: 0952 lsrs r2, r2, #5 8001090: 2164 movs r1, #100 @ 0x64 8001092: fb01 f202 mul.w r2, r1, r2 8001096: 1a9b subs r3, r3, r2 8001098: b29b uxth r3, r3 800109a: ee07 3a90 vmov s15, r3 800109e: eeb8 7be7 vcvt.f64.s32 d7, s15 80010a2: ed9f 6b75 vldr d6, [pc, #468] @ 8001278 80010a6: ee27 7b06 vmul.f64 d7, d7, d6 80010aa: eeb2 6b0e vmov.f64 d6, #46 @ 0x41700000 15.0 80010ae: ee37 7b06 vadd.f64 d7, d7, d6 80010b2: eef7 7bc7 vcvt.f32.f64 s15, d7 80010b6: 4b75 ldr r3, [pc, #468] @ (800128c ) 80010b8: edc3 7a03 vstr s15, [r3, #12] sensorsInfo.motorXStatus = (counter % 100) > 50 ? 1 : 0; 80010bc: 89fb ldrh r3, [r7, #14] 80010be: 4a72 ldr r2, [pc, #456] @ (8001288 ) 80010c0: fba2 1203 umull r1, r2, r2, r3 80010c4: 0952 lsrs r2, r2, #5 80010c6: 2164 movs r1, #100 @ 0x64 80010c8: fb01 f202 mul.w r2, r1, r2 80010cc: 1a9b subs r3, r3, r2 80010ce: b29b uxth r3, r3 80010d0: 2b32 cmp r3, #50 @ 0x32 80010d2: bf8c ite hi 80010d4: 2301 movhi r3, #1 80010d6: 2300 movls r3, #0 80010d8: b2db uxtb r3, r3 80010da: 461a mov r2, r3 80010dc: 4b6b ldr r3, [pc, #428] @ (800128c ) 80010de: 741a strb r2, [r3, #16] sensorsInfo.motorYStatus = (counter % 100) > 75 ? 1 : 0; 80010e0: 89fb ldrh r3, [r7, #14] 80010e2: 4a69 ldr r2, [pc, #420] @ (8001288 ) 80010e4: fba2 1203 umull r1, r2, r2, r3 80010e8: 0952 lsrs r2, r2, #5 80010ea: 2164 movs r1, #100 @ 0x64 80010ec: fb01 f202 mul.w r2, r1, r2 80010f0: 1a9b subs r3, r3, r2 80010f2: b29b uxth r3, r3 80010f4: 2b4b cmp r3, #75 @ 0x4b 80010f6: bf8c ite hi 80010f8: 2301 movhi r3, #1 80010fa: 2300 movls r3, #0 80010fc: b2db uxtb r3, r3 80010fe: 461a mov r2, r3 8001100: 4b62 ldr r3, [pc, #392] @ (800128c ) 8001102: 745a strb r2, [r3, #17] sensorsInfo.motorXAveCurrent = 3 + (0.01 * (counter % 100)); 8001104: 89fb ldrh r3, [r7, #14] 8001106: 4a60 ldr r2, [pc, #384] @ (8001288 ) 8001108: fba2 1203 umull r1, r2, r2, r3 800110c: 0952 lsrs r2, r2, #5 800110e: 2164 movs r1, #100 @ 0x64 8001110: fb01 f202 mul.w r2, r1, r2 8001114: 1a9b subs r3, r3, r2 8001116: b29b uxth r3, r3 8001118: ee07 3a90 vmov s15, r3 800111c: eeb8 7be7 vcvt.f64.s32 d7, s15 8001120: ed9f 6b55 vldr d6, [pc, #340] @ 8001278 8001124: ee27 7b06 vmul.f64 d7, d7, d6 8001128: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800112c: ee37 7b06 vadd.f64 d7, d7, d6 8001130: eef7 7bc7 vcvt.f32.f64 s15, d7 8001134: 4b55 ldr r3, [pc, #340] @ (800128c ) 8001136: edc3 7a05 vstr s15, [r3, #20] sensorsInfo.motorYAveCurrent = 3 + (0.01 * (counter % 100)); 800113a: 89fb ldrh r3, [r7, #14] 800113c: 4a52 ldr r2, [pc, #328] @ (8001288 ) 800113e: fba2 1203 umull r1, r2, r2, r3 8001142: 0952 lsrs r2, r2, #5 8001144: 2164 movs r1, #100 @ 0x64 8001146: fb01 f202 mul.w r2, r1, r2 800114a: 1a9b subs r3, r3, r2 800114c: b29b uxth r3, r3 800114e: ee07 3a90 vmov s15, r3 8001152: eeb8 7be7 vcvt.f64.s32 d7, s15 8001156: ed9f 6b48 vldr d6, [pc, #288] @ 8001278 800115a: ee27 7b06 vmul.f64 d7, d7, d6 800115e: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8001162: ee37 7b06 vadd.f64 d7, d7, d6 8001166: eef7 7bc7 vcvt.f32.f64 s15, d7 800116a: 4b48 ldr r3, [pc, #288] @ (800128c ) 800116c: edc3 7a06 vstr s15, [r3, #24] sensorsInfo.motorXPeakCurrent = 6 + (0.01 * (counter % 100)); 8001170: 89fb ldrh r3, [r7, #14] 8001172: 4a45 ldr r2, [pc, #276] @ (8001288 ) 8001174: fba2 1203 umull r1, r2, r2, r3 8001178: 0952 lsrs r2, r2, #5 800117a: 2164 movs r1, #100 @ 0x64 800117c: fb01 f202 mul.w r2, r1, r2 8001180: 1a9b subs r3, r3, r2 8001182: b29b uxth r3, r3 8001184: ee07 3a90 vmov s15, r3 8001188: eeb8 7be7 vcvt.f64.s32 d7, s15 800118c: ed9f 6b3a vldr d6, [pc, #232] @ 8001278 8001190: ee27 7b06 vmul.f64 d7, d7, d6 8001194: eeb1 6b08 vmov.f64 d6, #24 @ 0x40c00000 6.0 8001198: ee37 7b06 vadd.f64 d7, d7, d6 800119c: eef7 7bc7 vcvt.f32.f64 s15, d7 80011a0: 4b3a ldr r3, [pc, #232] @ (800128c ) 80011a2: edc3 7a07 vstr s15, [r3, #28] sensorsInfo.motorYPeakCurrent = 6 + (0.01 * (counter % 100)); 80011a6: 89fb ldrh r3, [r7, #14] 80011a8: 4a37 ldr r2, [pc, #220] @ (8001288 ) 80011aa: fba2 1203 umull r1, r2, r2, r3 80011ae: 0952 lsrs r2, r2, #5 80011b0: 2164 movs r1, #100 @ 0x64 80011b2: fb01 f202 mul.w r2, r1, r2 80011b6: 1a9b subs r3, r3, r2 80011b8: b29b uxth r3, r3 80011ba: ee07 3a90 vmov s15, r3 80011be: eeb8 7be7 vcvt.f64.s32 d7, s15 80011c2: ed9f 6b2d vldr d6, [pc, #180] @ 8001278 80011c6: ee27 7b06 vmul.f64 d7, d7, d6 80011ca: eeb1 6b08 vmov.f64 d6, #24 @ 0x40c00000 6.0 80011ce: ee37 7b06 vadd.f64 d7, d7, d6 80011d2: eef7 7bc7 vcvt.f32.f64 s15, d7 80011d6: 4b2d ldr r3, [pc, #180] @ (800128c ) 80011d8: edc3 7a08 vstr s15, [r3, #32] sensorsInfo.limitSwitchUp = (counter % 100) > 50 ? 1 : 0; 80011dc: 89fb ldrh r3, [r7, #14] 80011de: 4a2a ldr r2, [pc, #168] @ (8001288 ) 80011e0: fba2 1203 umull r1, r2, r2, r3 80011e4: 0952 lsrs r2, r2, #5 80011e6: 2164 movs r1, #100 @ 0x64 80011e8: fb01 f202 mul.w r2, r1, r2 80011ec: 1a9b subs r3, r3, r2 80011ee: b29b uxth r3, r3 80011f0: 2b32 cmp r3, #50 @ 0x32 80011f2: bf8c ite hi 80011f4: 2301 movhi r3, #1 80011f6: 2300 movls r3, #0 80011f8: b2db uxtb r3, r3 80011fa: 461a mov r2, r3 80011fc: 4b23 ldr r3, [pc, #140] @ (800128c ) 80011fe: f883 2024 strb.w r2, [r3, #36] @ 0x24 sensorsInfo.limitSwitchDown = (counter % 100) < 25 ? 1 : 0; 8001202: 89fb ldrh r3, [r7, #14] 8001204: 4a20 ldr r2, [pc, #128] @ (8001288 ) 8001206: fba2 1203 umull r1, r2, r2, r3 800120a: 0952 lsrs r2, r2, #5 800120c: 2164 movs r1, #100 @ 0x64 800120e: fb01 f202 mul.w r2, r1, r2 8001212: 1a9b subs r3, r3, r2 8001214: b29b uxth r3, r3 8001216: 2b18 cmp r3, #24 8001218: bf94 ite ls 800121a: 2301 movls r3, #1 800121c: 2300 movhi r3, #0 800121e: b2db uxtb r3, r3 8001220: 461a mov r2, r3 8001222: 4b1a ldr r3, [pc, #104] @ (800128c ) 8001224: f883 2025 strb.w r2, [r3, #37] @ 0x25 sensorsInfo.limitSwitchCenter = (counter % 100) > 35 ? 1 : 0; 8001228: 89fb ldrh r3, [r7, #14] 800122a: 4a17 ldr r2, [pc, #92] @ (8001288 ) 800122c: fba2 1203 umull r1, r2, r2, r3 8001230: 0952 lsrs r2, r2, #5 8001232: 2164 movs r1, #100 @ 0x64 8001234: fb01 f202 mul.w r2, r1, r2 8001238: 1a9b subs r3, r3, r2 800123a: b29b uxth r3, r3 800123c: 2b23 cmp r3, #35 @ 0x23 800123e: bf8c ite hi 8001240: 2301 movhi r3, #1 8001242: 2300 movls r3, #0 8001244: b2db uxtb r3, r3 8001246: 461a mov r2, r3 8001248: 4b10 ldr r3, [pc, #64] @ (800128c ) 800124a: f883 2026 strb.w r2, [r3, #38] @ 0x26 sensorsInfo.powerSupplyFailMask = 0; 800124e: 4b0f ldr r3, [pc, #60] @ (800128c ) 8001250: 2200 movs r2, #0 8001252: f883 2027 strb.w r2, [r3, #39] @ 0x27 osMutexRelease(sensorsInfoMutex); 8001256: 4b0e ldr r3, [pc, #56] @ (8001290 ) 8001258: 681b ldr r3, [r3, #0] 800125a: 4618 mov r0, r3 800125c: f00a fabf bl 800b7de counter++; 8001260: 89fb ldrh r3, [r7, #14] 8001262: 3301 adds r3, #1 8001264: 81fb strh r3, [r7, #14] osDelay (pdMS_TO_TICKS (1000)); 8001266: f44f 707a mov.w r0, #1000 @ 0x3e8 800126a: f00a f9cc bl 800b606 osMutexAcquire (resMeasurementsMutex, osWaitForever); 800126e: bf00 nop 8001270: e514 b.n 8000c9c 8001272: bf00 nop 8001274: f3af 8000 nop.w 8001278: 47ae147b .word 0x47ae147b 800127c: 3f847ae1 .word 0x3f847ae1 8001280: 00000000 .word 0x00000000 8001284: 40498000 .word 0x40498000 8001288: 51eb851f .word 0x51eb851f 800128c: 24000760 .word 0x24000760 8001290: 2400078c .word 0x2400078c 08001294 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 8001294: b480 push {r7} 8001296: b089 sub sp, #36 @ 0x24 8001298: af00 add r7, sp, #0 800129a: 60f8 str r0, [r7, #12] 800129c: 60b9 str r1, [r7, #8] 800129e: 607a str r2, [r7, #4] 80012a0: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 80012a2: 687b ldr r3, [r7, #4] 80012a4: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 80012a6: 69bb ldr r3, [r7, #24] 80012a8: 681b ldr r3, [r3, #0] 80012aa: 617b str r3, [r7, #20] uint8_t i = 0; 80012ac: 2300 movs r3, #0 80012ae: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 80012b0: 68bb ldr r3, [r7, #8] 80012b2: 881b ldrh r3, [r3, #0] 80012b4: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 80012b6: 2300 movs r3, #0 80012b8: 77fb strb r3, [r7, #31] 80012ba: e00e b.n 80012da buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 80012bc: 7ffb ldrb r3, [r7, #31] 80012be: 00db lsls r3, r3, #3 80012c0: 697a ldr r2, [r7, #20] 80012c2: 40da lsrs r2, r3 80012c4: 7fbb ldrb r3, [r7, #30] 80012c6: 1c59 adds r1, r3, #1 80012c8: 77b9 strb r1, [r7, #30] 80012ca: 4619 mov r1, r3 80012cc: 68fb ldr r3, [r7, #12] 80012ce: 440b add r3, r1 80012d0: b2d2 uxtb r2, r2 80012d2: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 80012d4: 7ffb ldrb r3, [r7, #31] 80012d6: 3301 adds r3, #1 80012d8: 77fb strb r3, [r7, #31] 80012da: 7ffa ldrb r2, [r7, #31] 80012dc: 78fb ldrb r3, [r7, #3] 80012de: 429a cmp r2, r3 80012e0: d3ec bcc.n 80012bc } *buffPos = newBuffPos; 80012e2: 7fbb ldrb r3, [r7, #30] 80012e4: b29a uxth r2, r3 80012e6: 68bb ldr r3, [r7, #8] 80012e8: 801a strh r2, [r3, #0] } 80012ea: bf00 nop 80012ec: 3724 adds r7, #36 @ 0x24 80012ee: 46bd mov sp, r7 80012f0: f85d 7b04 ldr.w r7, [sp], #4 80012f4: 4770 bx lr ... 080012f8 : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 80012f8: b580 push {r7, lr} 80012fa: b084 sub sp, #16 80012fc: af00 add r7, sp, #0 80012fe: 6078 str r0, [r7, #4] 8001300: 4608 mov r0, r1 8001302: 4611 mov r1, r2 8001304: 461a mov r2, r3 8001306: 4603 mov r3, r0 8001308: 807b strh r3, [r7, #2] 800130a: 460b mov r3, r1 800130c: 707b strb r3, [r7, #1] 800130e: 4613 mov r3, r2 8001310: 703b strb r3, [r7, #0] uint16_t crc = 0; 8001312: 2300 movs r3, #0 8001314: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 8001316: 2300 movs r3, #0 8001318: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 800131a: 787b ldrb r3, [r7, #1] 800131c: b21a sxth r2, r3 800131e: 4b43 ldr r3, [pc, #268] @ (800142c ) 8001320: 4313 orrs r3, r2 8001322: b21b sxth r3, r3 8001324: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 8001326: 8bbb ldrh r3, [r7, #28] 8001328: 461a mov r2, r3 800132a: 2100 movs r1, #0 800132c: 6878 ldr r0, [r7, #4] 800132e: f00d ffb2 bl 800f296 txBuffer[txBufferPos++] = FRAME_INDICATOR; 8001332: 89fb ldrh r3, [r7, #14] 8001334: 1c5a adds r2, r3, #1 8001336: 81fa strh r2, [r7, #14] 8001338: 461a mov r2, r3 800133a: 687b ldr r3, [r7, #4] 800133c: 4413 add r3, r2 800133e: 22aa movs r2, #170 @ 0xaa 8001340: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 8001342: 89fb ldrh r3, [r7, #14] 8001344: 1c5a adds r2, r3, #1 8001346: 81fa strh r2, [r7, #14] 8001348: 461a mov r2, r3 800134a: 687b ldr r3, [r7, #4] 800134c: 4413 add r3, r2 800134e: 887a ldrh r2, [r7, #2] 8001350: b2d2 uxtb r2, r2 8001352: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 8001354: 887b ldrh r3, [r7, #2] 8001356: 0a1b lsrs r3, r3, #8 8001358: b29a uxth r2, r3 800135a: 89fb ldrh r3, [r7, #14] 800135c: 1c59 adds r1, r3, #1 800135e: 81f9 strh r1, [r7, #14] 8001360: 4619 mov r1, r3 8001362: 687b ldr r3, [r7, #4] 8001364: 440b add r3, r1 8001366: b2d2 uxtb r2, r2 8001368: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 800136a: 89fb ldrh r3, [r7, #14] 800136c: 1c5a adds r2, r3, #1 800136e: 81fa strh r2, [r7, #14] 8001370: 461a mov r2, r3 8001372: 687b ldr r3, [r7, #4] 8001374: 4413 add r3, r2 8001376: 897a ldrh r2, [r7, #10] 8001378: b2d2 uxtb r2, r2 800137a: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 800137c: 897b ldrh r3, [r7, #10] 800137e: 0a1b lsrs r3, r3, #8 8001380: b29a uxth r2, r3 8001382: 89fb ldrh r3, [r7, #14] 8001384: 1c59 adds r1, r3, #1 8001386: 81f9 strh r1, [r7, #14] 8001388: 4619 mov r1, r3 800138a: 687b ldr r3, [r7, #4] 800138c: 440b add r3, r1 800138e: b2d2 uxtb r2, r2 8001390: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 8001392: 89fb ldrh r3, [r7, #14] 8001394: 1c5a adds r2, r3, #1 8001396: 81fa strh r2, [r7, #14] 8001398: 461a mov r2, r3 800139a: 687b ldr r3, [r7, #4] 800139c: 4413 add r3, r2 800139e: 8bba ldrh r2, [r7, #28] 80013a0: b2d2 uxtb r2, r2 80013a2: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 80013a4: 8bbb ldrh r3, [r7, #28] 80013a6: 0a1b lsrs r3, r3, #8 80013a8: b29a uxth r2, r3 80013aa: 89fb ldrh r3, [r7, #14] 80013ac: 1c59 adds r1, r3, #1 80013ae: 81f9 strh r1, [r7, #14] 80013b0: 4619 mov r1, r3 80013b2: 687b ldr r3, [r7, #4] 80013b4: 440b add r3, r1 80013b6: b2d2 uxtb r2, r2 80013b8: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 80013ba: 89fb ldrh r3, [r7, #14] 80013bc: 1c5a adds r2, r3, #1 80013be: 81fa strh r2, [r7, #14] 80013c0: 461a mov r2, r3 80013c2: 687b ldr r3, [r7, #4] 80013c4: 4413 add r3, r2 80013c6: 783a ldrb r2, [r7, #0] 80013c8: 701a strb r2, [r3, #0] if (dataLength > 0) { 80013ca: 8bbb ldrh r3, [r7, #28] 80013cc: 2b00 cmp r3, #0 80013ce: d00b beq.n 80013e8 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 80013d0: 89fb ldrh r3, [r7, #14] 80013d2: 687a ldr r2, [r7, #4] 80013d4: 4413 add r3, r2 80013d6: 8bba ldrh r2, [r7, #28] 80013d8: 69b9 ldr r1, [r7, #24] 80013da: 4618 mov r0, r3 80013dc: f00e f82d bl 800f43a txBufferPos += dataLength; 80013e0: 89fa ldrh r2, [r7, #14] 80013e2: 8bbb ldrh r3, [r7, #28] 80013e4: 4413 add r3, r2 80013e6: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 80013e8: 89fb ldrh r3, [r7, #14] 80013ea: 461a mov r2, r3 80013ec: 6879 ldr r1, [r7, #4] 80013ee: 4810 ldr r0, [pc, #64] @ (8001430 ) 80013f0: f001 fb0a bl 8002a08 80013f4: 4603 mov r3, r0 80013f6: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 80013f8: 89fb ldrh r3, [r7, #14] 80013fa: 1c5a adds r2, r3, #1 80013fc: 81fa strh r2, [r7, #14] 80013fe: 461a mov r2, r3 8001400: 687b ldr r3, [r7, #4] 8001402: 4413 add r3, r2 8001404: 89ba ldrh r2, [r7, #12] 8001406: b2d2 uxtb r2, r2 8001408: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 800140a: 89bb ldrh r3, [r7, #12] 800140c: 0a1b lsrs r3, r3, #8 800140e: b29a uxth r2, r3 8001410: 89fb ldrh r3, [r7, #14] 8001412: 1c59 adds r1, r3, #1 8001414: 81f9 strh r1, [r7, #14] 8001416: 4619 mov r1, r3 8001418: 687b ldr r3, [r7, #4] 800141a: 440b add r3, r1 800141c: b2d2 uxtb r2, r2 800141e: 701a strb r2, [r3, #0] return txBufferPos; 8001420: 89fb ldrh r3, [r7, #14] } 8001422: 4618 mov r0, r3 8001424: 3710 adds r7, #16 8001426: 46bd mov sp, r7 8001428: bd80 pop {r7, pc} 800142a: bf00 nop 800142c: ffff8000 .word 0xffff8000 8001430: 2400008c .word 0x2400008c 08001434 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001434: b580 push {r7, lr} 8001436: b082 sub sp, #8 8001438: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800143a: 4b10 ldr r3, [pc, #64] @ (800147c ) 800143c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8001440: 4a0e ldr r2, [pc, #56] @ (800147c ) 8001442: f043 0302 orr.w r3, r3, #2 8001446: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800144a: 4b0c ldr r3, [pc, #48] @ (800147c ) 800144c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8001450: f003 0302 and.w r3, r3, #2 8001454: 607b str r3, [r7, #4] 8001456: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8001458: 2200 movs r2, #0 800145a: 210f movs r1, #15 800145c: f06f 0001 mvn.w r0, #1 8001460: f001 f9ce bl 8002800 /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8001464: 2200 movs r2, #0 8001466: 2105 movs r1, #5 8001468: 2005 movs r0, #5 800146a: f001 f9c9 bl 8002800 HAL_NVIC_EnableIRQ(RCC_IRQn); 800146e: 2005 movs r0, #5 8001470: f001 f9e0 bl 8002834 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001474: bf00 nop 8001476: 3708 adds r7, #8 8001478: 46bd mov sp, r7 800147a: bd80 pop {r7, pc} 800147c: 58024400 .word 0x58024400 08001480 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 8001480: b480 push {r7} 8001482: b085 sub sp, #20 8001484: af00 add r7, sp, #0 8001486: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8001488: 687b ldr r3, [r7, #4] 800148a: 681b ldr r3, [r3, #0] 800148c: 4a0b ldr r2, [pc, #44] @ (80014bc ) 800148e: 4293 cmp r3, r2 8001490: d10e bne.n 80014b0 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8001492: 4b0b ldr r3, [pc, #44] @ (80014c0 ) 8001494: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001498: 4a09 ldr r2, [pc, #36] @ (80014c0 ) 800149a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800149e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80014a2: 4b07 ldr r3, [pc, #28] @ (80014c0 ) 80014a4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80014a8: f403 2300 and.w r3, r3, #524288 @ 0x80000 80014ac: 60fb str r3, [r7, #12] 80014ae: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 80014b0: bf00 nop 80014b2: 3714 adds r7, #20 80014b4: 46bd mov sp, r7 80014b6: f85d 7b04 ldr.w r7, [sp], #4 80014ba: 4770 bx lr 80014bc: 58024c00 .word 0x58024c00 80014c0: 58024400 .word 0x58024400 080014c4 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 80014c4: b580 push {r7, lr} 80014c6: b0b4 sub sp, #208 @ 0xd0 80014c8: af00 add r7, sp, #0 80014ca: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80014cc: f107 0310 add.w r3, r7, #16 80014d0: 22c0 movs r2, #192 @ 0xc0 80014d2: 2100 movs r1, #0 80014d4: 4618 mov r0, r3 80014d6: f00d fede bl 800f296 if(hrng->Instance==RNG) 80014da: 687b ldr r3, [r7, #4] 80014dc: 681b ldr r3, [r3, #0] 80014de: 4a14 ldr r2, [pc, #80] @ (8001530 ) 80014e0: 4293 cmp r3, r2 80014e2: d121 bne.n 8001528 /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 80014e4: f44f 3200 mov.w r2, #131072 @ 0x20000 80014e8: f04f 0300 mov.w r3, #0 80014ec: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 80014f0: 2300 movs r3, #0 80014f2: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80014f6: f107 0310 add.w r3, r7, #16 80014fa: 4618 mov r0, r3 80014fc: f005 f85e bl 80065bc 8001500: 4603 mov r3, r0 8001502: 2b00 cmp r3, #0 8001504: d001 beq.n 800150a { Error_Handler(); 8001506: f7ff fb9f bl 8000c48 } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 800150a: 4b0a ldr r3, [pc, #40] @ (8001534 ) 800150c: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8001510: 4a08 ldr r2, [pc, #32] @ (8001534 ) 8001512: f043 0340 orr.w r3, r3, #64 @ 0x40 8001516: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 800151a: 4b06 ldr r3, [pc, #24] @ (8001534 ) 800151c: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8001520: f003 0340 and.w r3, r3, #64 @ 0x40 8001524: 60fb str r3, [r7, #12] 8001526: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 8001528: bf00 nop 800152a: 37d0 adds r7, #208 @ 0xd0 800152c: 46bd mov sp, r7 800152e: bd80 pop {r7, pc} 8001530: 48021800 .word 0x48021800 8001534: 58024400 .word 0x58024400 08001538 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8001538: b580 push {r7, lr} 800153a: b0bc sub sp, #240 @ 0xf0 800153c: af00 add r7, sp, #0 800153e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001540: f107 03dc add.w r3, r7, #220 @ 0xdc 8001544: 2200 movs r2, #0 8001546: 601a str r2, [r3, #0] 8001548: 605a str r2, [r3, #4] 800154a: 609a str r2, [r3, #8] 800154c: 60da str r2, [r3, #12] 800154e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8001550: f107 0318 add.w r3, r7, #24 8001554: 22c0 movs r2, #192 @ 0xc0 8001556: 2100 movs r1, #0 8001558: 4618 mov r0, r3 800155a: f00d fe9c bl 800f296 if(huart->Instance==UART8) 800155e: 687b ldr r3, [r7, #4] 8001560: 681b ldr r3, [r3, #0] 8001562: 4a84 ldr r2, [pc, #528] @ (8001774 ) 8001564: 4293 cmp r3, r2 8001566: f040 80ac bne.w 80016c2 /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 800156a: f04f 0202 mov.w r2, #2 800156e: f04f 0300 mov.w r3, #0 8001572: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8001576: 2300 movs r3, #0 8001578: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800157c: f107 0318 add.w r3, r7, #24 8001580: 4618 mov r0, r3 8001582: f005 f81b bl 80065bc 8001586: 4603 mov r3, r0 8001588: 2b00 cmp r3, #0 800158a: d001 beq.n 8001590 { Error_Handler(); 800158c: f7ff fb5c bl 8000c48 } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 8001590: 4b79 ldr r3, [pc, #484] @ (8001778 ) 8001592: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8001596: 4a78 ldr r2, [pc, #480] @ (8001778 ) 8001598: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800159c: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80015a0: 4b75 ldr r3, [pc, #468] @ (8001778 ) 80015a2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80015a6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80015aa: 617b str r3, [r7, #20] 80015ac: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 80015ae: 4b72 ldr r3, [pc, #456] @ (8001778 ) 80015b0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015b4: 4a70 ldr r2, [pc, #448] @ (8001778 ) 80015b6: f043 0310 orr.w r3, r3, #16 80015ba: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80015be: 4b6e ldr r3, [pc, #440] @ (8001778 ) 80015c0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015c4: f003 0310 and.w r3, r3, #16 80015c8: 613b str r3, [r7, #16] 80015ca: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 80015cc: 2303 movs r3, #3 80015ce: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80015d2: 2302 movs r3, #2 80015d4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 80015d8: 2300 movs r3, #0 80015da: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80015de: 2300 movs r3, #0 80015e0: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 80015e4: 2308 movs r3, #8 80015e6: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80015ea: f107 03dc add.w r3, r7, #220 @ 0xdc 80015ee: 4619 mov r1, r3 80015f0: 4862 ldr r0, [pc, #392] @ (800177c ) 80015f2: f003 fdd1 bl 8005198 /* UART8 DMA Init */ /* UART8_RX Init */ hdma_uart8_rx.Instance = DMA2_Stream7; 80015f6: 4b62 ldr r3, [pc, #392] @ (8001780 ) 80015f8: 4a62 ldr r2, [pc, #392] @ (8001784 ) 80015fa: 601a str r2, [r3, #0] hdma_uart8_rx.Init.Request = DMA_REQUEST_UART8_RX; 80015fc: 4b60 ldr r3, [pc, #384] @ (8001780 ) 80015fe: 2251 movs r2, #81 @ 0x51 8001600: 605a str r2, [r3, #4] hdma_uart8_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8001602: 4b5f ldr r3, [pc, #380] @ (8001780 ) 8001604: 2200 movs r2, #0 8001606: 609a str r2, [r3, #8] hdma_uart8_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8001608: 4b5d ldr r3, [pc, #372] @ (8001780 ) 800160a: 2200 movs r2, #0 800160c: 60da str r2, [r3, #12] hdma_uart8_rx.Init.MemInc = DMA_MINC_ENABLE; 800160e: 4b5c ldr r3, [pc, #368] @ (8001780 ) 8001610: f44f 6280 mov.w r2, #1024 @ 0x400 8001614: 611a str r2, [r3, #16] hdma_uart8_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001616: 4b5a ldr r3, [pc, #360] @ (8001780 ) 8001618: 2200 movs r2, #0 800161a: 615a str r2, [r3, #20] hdma_uart8_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800161c: 4b58 ldr r3, [pc, #352] @ (8001780 ) 800161e: 2200 movs r2, #0 8001620: 619a str r2, [r3, #24] hdma_uart8_rx.Init.Mode = DMA_NORMAL; 8001622: 4b57 ldr r3, [pc, #348] @ (8001780 ) 8001624: 2200 movs r2, #0 8001626: 61da str r2, [r3, #28] hdma_uart8_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 8001628: 4b55 ldr r3, [pc, #340] @ (8001780 ) 800162a: f44f 3240 mov.w r2, #196608 @ 0x30000 800162e: 621a str r2, [r3, #32] hdma_uart8_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8001630: 4b53 ldr r3, [pc, #332] @ (8001780 ) 8001632: 2200 movs r2, #0 8001634: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart8_rx) != HAL_OK) 8001636: 4852 ldr r0, [pc, #328] @ (8001780 ) 8001638: f001 fb88 bl 8002d4c 800163c: 4603 mov r3, r0 800163e: 2b00 cmp r3, #0 8001640: d001 beq.n 8001646 { Error_Handler(); 8001642: f7ff fb01 bl 8000c48 } __HAL_LINKDMA(huart,hdmarx,hdma_uart8_rx); 8001646: 687b ldr r3, [r7, #4] 8001648: 4a4d ldr r2, [pc, #308] @ (8001780 ) 800164a: f8c3 2080 str.w r2, [r3, #128] @ 0x80 800164e: 4a4c ldr r2, [pc, #304] @ (8001780 ) 8001650: 687b ldr r3, [r7, #4] 8001652: 6393 str r3, [r2, #56] @ 0x38 /* UART8_TX Init */ hdma_uart8_tx.Instance = DMA2_Stream6; 8001654: 4b4c ldr r3, [pc, #304] @ (8001788 ) 8001656: 4a4d ldr r2, [pc, #308] @ (800178c ) 8001658: 601a str r2, [r3, #0] hdma_uart8_tx.Init.Request = DMA_REQUEST_UART8_TX; 800165a: 4b4b ldr r3, [pc, #300] @ (8001788 ) 800165c: 2252 movs r2, #82 @ 0x52 800165e: 605a str r2, [r3, #4] hdma_uart8_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8001660: 4b49 ldr r3, [pc, #292] @ (8001788 ) 8001662: 2240 movs r2, #64 @ 0x40 8001664: 609a str r2, [r3, #8] hdma_uart8_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8001666: 4b48 ldr r3, [pc, #288] @ (8001788 ) 8001668: 2200 movs r2, #0 800166a: 60da str r2, [r3, #12] hdma_uart8_tx.Init.MemInc = DMA_MINC_ENABLE; 800166c: 4b46 ldr r3, [pc, #280] @ (8001788 ) 800166e: f44f 6280 mov.w r2, #1024 @ 0x400 8001672: 611a str r2, [r3, #16] hdma_uart8_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8001674: 4b44 ldr r3, [pc, #272] @ (8001788 ) 8001676: 2200 movs r2, #0 8001678: 615a str r2, [r3, #20] hdma_uart8_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 800167a: 4b43 ldr r3, [pc, #268] @ (8001788 ) 800167c: 2200 movs r2, #0 800167e: 619a str r2, [r3, #24] hdma_uart8_tx.Init.Mode = DMA_NORMAL; 8001680: 4b41 ldr r3, [pc, #260] @ (8001788 ) 8001682: 2200 movs r2, #0 8001684: 61da str r2, [r3, #28] hdma_uart8_tx.Init.Priority = DMA_PRIORITY_VERY_HIGH; 8001686: 4b40 ldr r3, [pc, #256] @ (8001788 ) 8001688: f44f 3240 mov.w r2, #196608 @ 0x30000 800168c: 621a str r2, [r3, #32] hdma_uart8_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800168e: 4b3e ldr r3, [pc, #248] @ (8001788 ) 8001690: 2200 movs r2, #0 8001692: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_uart8_tx) != HAL_OK) 8001694: 483c ldr r0, [pc, #240] @ (8001788 ) 8001696: f001 fb59 bl 8002d4c 800169a: 4603 mov r3, r0 800169c: 2b00 cmp r3, #0 800169e: d001 beq.n 80016a4 { Error_Handler(); 80016a0: f7ff fad2 bl 8000c48 } __HAL_LINKDMA(huart,hdmatx,hdma_uart8_tx); 80016a4: 687b ldr r3, [r7, #4] 80016a6: 4a38 ldr r2, [pc, #224] @ (8001788 ) 80016a8: 67da str r2, [r3, #124] @ 0x7c 80016aa: 4a37 ldr r2, [pc, #220] @ (8001788 ) 80016ac: 687b ldr r3, [r7, #4] 80016ae: 6393 str r3, [r2, #56] @ 0x38 /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 80016b0: 2200 movs r2, #0 80016b2: 2105 movs r1, #5 80016b4: 2053 movs r0, #83 @ 0x53 80016b6: f001 f8a3 bl 8002800 HAL_NVIC_EnableIRQ(UART8_IRQn); 80016ba: 2053 movs r0, #83 @ 0x53 80016bc: f001 f8ba bl 8002834 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 80016c0: e053 b.n 800176a else if(huart->Instance==USART1) 80016c2: 687b ldr r3, [r7, #4] 80016c4: 681b ldr r3, [r3, #0] 80016c6: 4a32 ldr r2, [pc, #200] @ (8001790 ) 80016c8: 4293 cmp r3, r2 80016ca: d14e bne.n 800176a PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 80016cc: f04f 0201 mov.w r2, #1 80016d0: f04f 0300 mov.w r3, #0 80016d4: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 80016d8: 2300 movs r3, #0 80016da: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80016de: f107 0318 add.w r3, r7, #24 80016e2: 4618 mov r0, r3 80016e4: f004 ff6a bl 80065bc 80016e8: 4603 mov r3, r0 80016ea: 2b00 cmp r3, #0 80016ec: d001 beq.n 80016f2 Error_Handler(); 80016ee: f7ff faab bl 8000c48 __HAL_RCC_USART1_CLK_ENABLE(); 80016f2: 4b21 ldr r3, [pc, #132] @ (8001778 ) 80016f4: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80016f8: 4a1f ldr r2, [pc, #124] @ (8001778 ) 80016fa: f043 0310 orr.w r3, r3, #16 80016fe: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 8001702: 4b1d ldr r3, [pc, #116] @ (8001778 ) 8001704: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8001708: f003 0310 and.w r3, r3, #16 800170c: 60fb str r3, [r7, #12] 800170e: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001710: 4b19 ldr r3, [pc, #100] @ (8001778 ) 8001712: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001716: 4a18 ldr r2, [pc, #96] @ (8001778 ) 8001718: f043 0302 orr.w r3, r3, #2 800171c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001720: 4b15 ldr r3, [pc, #84] @ (8001778 ) 8001722: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001726: f003 0302 and.w r3, r3, #2 800172a: 60bb str r3, [r7, #8] 800172c: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 800172e: f44f 4340 mov.w r3, #49152 @ 0xc000 8001732: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001736: 2302 movs r3, #2 8001738: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800173c: 2300 movs r3, #0 800173e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001742: 2300 movs r3, #0 8001744: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 8001748: 2304 movs r3, #4 800174a: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800174e: f107 03dc add.w r3, r7, #220 @ 0xdc 8001752: 4619 mov r1, r3 8001754: 480f ldr r0, [pc, #60] @ (8001794 ) 8001756: f003 fd1f bl 8005198 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 800175a: 2200 movs r2, #0 800175c: 2105 movs r1, #5 800175e: 2025 movs r0, #37 @ 0x25 8001760: f001 f84e bl 8002800 HAL_NVIC_EnableIRQ(USART1_IRQn); 8001764: 2025 movs r0, #37 @ 0x25 8001766: f001 f865 bl 8002834 } 800176a: bf00 nop 800176c: 37f0 adds r7, #240 @ 0xf0 800176e: 46bd mov sp, r7 8001770: bd80 pop {r7, pc} 8001772: bf00 nop 8001774: 40007c00 .word 0x40007c00 8001778: 58024400 .word 0x58024400 800177c: 58021000 .word 0x58021000 8001780: 240001ec .word 0x240001ec 8001784: 400204b8 .word 0x400204b8 8001788: 24000264 .word 0x24000264 800178c: 400204a0 .word 0x400204a0 8001790: 40011000 .word 0x40011000 8001794: 58020400 .word 0x58020400 08001798 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001798: b580 push {r7, lr} 800179a: b090 sub sp, #64 @ 0x40 800179c: af00 add r7, sp, #0 800179e: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80017a0: 687b ldr r3, [r7, #4] 80017a2: 2b0f cmp r3, #15 80017a4: d827 bhi.n 80017f6 { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 80017a6: 2200 movs r2, #0 80017a8: 6879 ldr r1, [r7, #4] 80017aa: 2036 movs r0, #54 @ 0x36 80017ac: f001 f828 bl 8002800 /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 80017b0: 2036 movs r0, #54 @ 0x36 80017b2: f001 f83f bl 8002834 uwTickPrio = TickPriority; 80017b6: 4a29 ldr r2, [pc, #164] @ (800185c ) 80017b8: 687b ldr r3, [r7, #4] 80017ba: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 80017bc: 4b28 ldr r3, [pc, #160] @ (8001860 ) 80017be: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80017c2: 4a27 ldr r2, [pc, #156] @ (8001860 ) 80017c4: f043 0310 orr.w r3, r3, #16 80017c8: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80017cc: 4b24 ldr r3, [pc, #144] @ (8001860 ) 80017ce: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80017d2: f003 0310 and.w r3, r3, #16 80017d6: 60fb str r3, [r7, #12] 80017d8: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 80017da: f107 0210 add.w r2, r7, #16 80017de: f107 0314 add.w r3, r7, #20 80017e2: 4611 mov r1, r2 80017e4: 4618 mov r0, r3 80017e6: f004 fea7 bl 8006538 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 80017ea: 6abb ldr r3, [r7, #40] @ 0x28 80017ec: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 80017ee: 6bbb ldr r3, [r7, #56] @ 0x38 80017f0: 2b00 cmp r3, #0 80017f2: d106 bne.n 8001802 80017f4: e001 b.n 80017fa return HAL_ERROR; 80017f6: 2301 movs r3, #1 80017f8: e02b b.n 8001852 { uwTimclock = HAL_RCC_GetPCLK1Freq(); 80017fa: f004 fe71 bl 80064e0 80017fe: 63f8 str r0, [r7, #60] @ 0x3c 8001800: e004 b.n 800180c } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 8001802: f004 fe6d bl 80064e0 8001806: 4603 mov r3, r0 8001808: 005b lsls r3, r3, #1 800180a: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 800180c: 6bfb ldr r3, [r7, #60] @ 0x3c 800180e: 4a15 ldr r2, [pc, #84] @ (8001864 ) 8001810: fba2 2303 umull r2, r3, r2, r3 8001814: 0c9b lsrs r3, r3, #18 8001816: 3b01 subs r3, #1 8001818: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 800181a: 4b13 ldr r3, [pc, #76] @ (8001868 ) 800181c: 4a13 ldr r2, [pc, #76] @ (800186c ) 800181e: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 8001820: 4b11 ldr r3, [pc, #68] @ (8001868 ) 8001822: f240 32e7 movw r2, #999 @ 0x3e7 8001826: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8001828: 4a0f ldr r2, [pc, #60] @ (8001868 ) 800182a: 6b7b ldr r3, [r7, #52] @ 0x34 800182c: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 800182e: 4b0e ldr r3, [pc, #56] @ (8001868 ) 8001830: 2200 movs r2, #0 8001832: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8001834: 4b0c ldr r3, [pc, #48] @ (8001868 ) 8001836: 2200 movs r2, #0 8001838: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 800183a: 480b ldr r0, [pc, #44] @ (8001868 ) 800183c: f006 fd30 bl 80082a0 8001840: 4603 mov r3, r0 8001842: 2b00 cmp r3, #0 8001844: d104 bne.n 8001850 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 8001846: 4808 ldr r0, [pc, #32] @ (8001868 ) 8001848: f006 fd8c bl 8008364 800184c: 4603 mov r3, r0 800184e: e000 b.n 8001852 } /* Return function status */ return HAL_ERROR; 8001850: 2301 movs r3, #1 } 8001852: 4618 mov r0, r3 8001854: 3740 adds r7, #64 @ 0x40 8001856: 46bd mov sp, r7 8001858: bd80 pop {r7, pc} 800185a: bf00 nop 800185c: 24000008 .word 0x24000008 8001860: 58024400 .word 0x58024400 8001864: 431bde83 .word 0x431bde83 8001868: 240002e0 .word 0x240002e0 800186c: 40001000 .word 0x40001000 08001870 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001870: b480 push {r7} 8001872: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8001874: bf00 nop 8001876: e7fd b.n 8001874 08001878 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001878: b480 push {r7} 800187a: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 800187c: bf00 nop 800187e: e7fd b.n 800187c 08001880 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001880: b480 push {r7} 8001882: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001884: bf00 nop 8001886: e7fd b.n 8001884 08001888 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8001888: b480 push {r7} 800188a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 800188c: bf00 nop 800188e: e7fd b.n 800188c 08001890 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001890: b480 push {r7} 8001892: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001894: bf00 nop 8001896: e7fd b.n 8001894 08001898 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001898: b480 push {r7} 800189a: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 800189c: bf00 nop 800189e: 46bd mov sp, r7 80018a0: f85d 7b04 ldr.w r7, [sp], #4 80018a4: 4770 bx lr 080018a6 : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 80018a6: b480 push {r7} 80018a8: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 80018aa: bf00 nop 80018ac: 46bd mov sp, r7 80018ae: f85d 7b04 ldr.w r7, [sp], #4 80018b2: 4770 bx lr 080018b4 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 80018b4: b580 push {r7, lr} 80018b6: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 80018b8: 4802 ldr r0, [pc, #8] @ (80018c4 ) 80018ba: f007 f8a3 bl 8008a04 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 80018be: bf00 nop 80018c0: bd80 pop {r7, pc} 80018c2: bf00 nop 80018c4: 24000158 .word 0x24000158 080018c8 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 80018c8: b580 push {r7, lr} 80018ca: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 80018cc: 4802 ldr r0, [pc, #8] @ (80018d8 ) 80018ce: f006 fdc1 bl 8008454 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 80018d2: bf00 nop 80018d4: bd80 pop {r7, pc} 80018d6: bf00 nop 80018d8: 240002e0 .word 0x240002e0 080018dc : /** * @brief This function handles DMA2 stream6 global interrupt. */ void DMA2_Stream6_IRQHandler(void) { 80018dc: b580 push {r7, lr} 80018de: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */ /* USER CODE END DMA2_Stream6_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart8_tx); 80018e0: 4802 ldr r0, [pc, #8] @ (80018ec ) 80018e2: f002 faf3 bl 8003ecc /* USER CODE BEGIN DMA2_Stream6_IRQn 1 */ /* USER CODE END DMA2_Stream6_IRQn 1 */ } 80018e6: bf00 nop 80018e8: bd80 pop {r7, pc} 80018ea: bf00 nop 80018ec: 24000264 .word 0x24000264 080018f0 : /** * @brief This function handles DMA2 stream7 global interrupt. */ void DMA2_Stream7_IRQHandler(void) { 80018f0: b580 push {r7, lr} 80018f2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_uart8_rx); 80018f4: 4802 ldr r0, [pc, #8] @ (8001900 ) 80018f6: f002 fae9 bl 8003ecc /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ } 80018fa: bf00 nop 80018fc: bd80 pop {r7, pc} 80018fe: bf00 nop 8001900: 240001ec .word 0x240001ec 08001904 : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 8001904: b580 push {r7, lr} 8001906: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 8001908: 4802 ldr r0, [pc, #8] @ (8001914 ) 800190a: f007 f87b bl 8008a04 /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 800190e: bf00 nop 8001910: bd80 pop {r7, pc} 8001912: bf00 nop 8001914: 240000c4 .word 0x240000c4 08001918 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8001918: b580 push {r7, lr} 800191a: b086 sub sp, #24 800191c: af00 add r7, sp, #0 800191e: 60f8 str r0, [r7, #12] 8001920: 60b9 str r1, [r7, #8] 8001922: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8001924: 2300 movs r3, #0 8001926: 617b str r3, [r7, #20] 8001928: e00a b.n 8001940 <_read+0x28> { *ptr++ = __io_getchar(); 800192a: f3af 8000 nop.w 800192e: 4601 mov r1, r0 8001930: 68bb ldr r3, [r7, #8] 8001932: 1c5a adds r2, r3, #1 8001934: 60ba str r2, [r7, #8] 8001936: b2ca uxtb r2, r1 8001938: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 800193a: 697b ldr r3, [r7, #20] 800193c: 3301 adds r3, #1 800193e: 617b str r3, [r7, #20] 8001940: 697a ldr r2, [r7, #20] 8001942: 687b ldr r3, [r7, #4] 8001944: 429a cmp r2, r3 8001946: dbf0 blt.n 800192a <_read+0x12> } return len; 8001948: 687b ldr r3, [r7, #4] } 800194a: 4618 mov r0, r3 800194c: 3718 adds r7, #24 800194e: 46bd mov sp, r7 8001950: bd80 pop {r7, pc} 08001952 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 8001952: b580 push {r7, lr} 8001954: b086 sub sp, #24 8001956: af00 add r7, sp, #0 8001958: 60f8 str r0, [r7, #12] 800195a: 60b9 str r1, [r7, #8] 800195c: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 800195e: 2300 movs r3, #0 8001960: 617b str r3, [r7, #20] 8001962: e009 b.n 8001978 <_write+0x26> { __io_putchar(*ptr++); 8001964: 68bb ldr r3, [r7, #8] 8001966: 1c5a adds r2, r3, #1 8001968: 60ba str r2, [r7, #8] 800196a: 781b ldrb r3, [r3, #0] 800196c: 4618 mov r0, r3 800196e: f3af 8000 nop.w for (DataIdx = 0; DataIdx < len; DataIdx++) 8001972: 697b ldr r3, [r7, #20] 8001974: 3301 adds r3, #1 8001976: 617b str r3, [r7, #20] 8001978: 697a ldr r2, [r7, #20] 800197a: 687b ldr r3, [r7, #4] 800197c: 429a cmp r2, r3 800197e: dbf1 blt.n 8001964 <_write+0x12> } return len; 8001980: 687b ldr r3, [r7, #4] } 8001982: 4618 mov r0, r3 8001984: 3718 adds r7, #24 8001986: 46bd mov sp, r7 8001988: bd80 pop {r7, pc} 0800198a <_close>: int _close(int file) { 800198a: b480 push {r7} 800198c: b083 sub sp, #12 800198e: af00 add r7, sp, #0 8001990: 6078 str r0, [r7, #4] (void)file; return -1; 8001992: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 8001996: 4618 mov r0, r3 8001998: 370c adds r7, #12 800199a: 46bd mov sp, r7 800199c: f85d 7b04 ldr.w r7, [sp], #4 80019a0: 4770 bx lr 080019a2 <_fstat>: int _fstat(int file, struct stat *st) { 80019a2: b480 push {r7} 80019a4: b083 sub sp, #12 80019a6: af00 add r7, sp, #0 80019a8: 6078 str r0, [r7, #4] 80019aa: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 80019ac: 683b ldr r3, [r7, #0] 80019ae: f44f 5200 mov.w r2, #8192 @ 0x2000 80019b2: 605a str r2, [r3, #4] return 0; 80019b4: 2300 movs r3, #0 } 80019b6: 4618 mov r0, r3 80019b8: 370c adds r7, #12 80019ba: 46bd mov sp, r7 80019bc: f85d 7b04 ldr.w r7, [sp], #4 80019c0: 4770 bx lr 080019c2 <_isatty>: int _isatty(int file) { 80019c2: b480 push {r7} 80019c4: b083 sub sp, #12 80019c6: af00 add r7, sp, #0 80019c8: 6078 str r0, [r7, #4] (void)file; return 1; 80019ca: 2301 movs r3, #1 } 80019cc: 4618 mov r0, r3 80019ce: 370c adds r7, #12 80019d0: 46bd mov sp, r7 80019d2: f85d 7b04 ldr.w r7, [sp], #4 80019d6: 4770 bx lr 080019d8 <_lseek>: int _lseek(int file, int ptr, int dir) { 80019d8: b480 push {r7} 80019da: b085 sub sp, #20 80019dc: af00 add r7, sp, #0 80019de: 60f8 str r0, [r7, #12] 80019e0: 60b9 str r1, [r7, #8] 80019e2: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 80019e4: 2300 movs r3, #0 } 80019e6: 4618 mov r0, r3 80019e8: 3714 adds r7, #20 80019ea: 46bd mov sp, r7 80019ec: f85d 7b04 ldr.w r7, [sp], #4 80019f0: 4770 bx lr ... 080019f4 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 80019f4: b580 push {r7, lr} 80019f6: b086 sub sp, #24 80019f8: af00 add r7, sp, #0 80019fa: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 80019fc: 4a14 ldr r2, [pc, #80] @ (8001a50 <_sbrk+0x5c>) 80019fe: 4b15 ldr r3, [pc, #84] @ (8001a54 <_sbrk+0x60>) 8001a00: 1ad3 subs r3, r2, r3 8001a02: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8001a04: 697b ldr r3, [r7, #20] 8001a06: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 8001a08: 4b13 ldr r3, [pc, #76] @ (8001a58 <_sbrk+0x64>) 8001a0a: 681b ldr r3, [r3, #0] 8001a0c: 2b00 cmp r3, #0 8001a0e: d102 bne.n 8001a16 <_sbrk+0x22> { __sbrk_heap_end = &_end; 8001a10: 4b11 ldr r3, [pc, #68] @ (8001a58 <_sbrk+0x64>) 8001a12: 4a12 ldr r2, [pc, #72] @ (8001a5c <_sbrk+0x68>) 8001a14: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 8001a16: 4b10 ldr r3, [pc, #64] @ (8001a58 <_sbrk+0x64>) 8001a18: 681a ldr r2, [r3, #0] 8001a1a: 687b ldr r3, [r7, #4] 8001a1c: 4413 add r3, r2 8001a1e: 693a ldr r2, [r7, #16] 8001a20: 429a cmp r2, r3 8001a22: d207 bcs.n 8001a34 <_sbrk+0x40> { errno = ENOMEM; 8001a24: f00d fcdc bl 800f3e0 <__errno> 8001a28: 4603 mov r3, r0 8001a2a: 220c movs r2, #12 8001a2c: 601a str r2, [r3, #0] return (void *)-1; 8001a2e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8001a32: e009 b.n 8001a48 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 8001a34: 4b08 ldr r3, [pc, #32] @ (8001a58 <_sbrk+0x64>) 8001a36: 681b ldr r3, [r3, #0] 8001a38: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 8001a3a: 4b07 ldr r3, [pc, #28] @ (8001a58 <_sbrk+0x64>) 8001a3c: 681a ldr r2, [r3, #0] 8001a3e: 687b ldr r3, [r7, #4] 8001a40: 4413 add r3, r2 8001a42: 4a05 ldr r2, [pc, #20] @ (8001a58 <_sbrk+0x64>) 8001a44: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 8001a46: 68fb ldr r3, [r7, #12] } 8001a48: 4618 mov r0, r3 8001a4a: 3718 adds r7, #24 8001a4c: 46bd mov sp, r7 8001a4e: bd80 pop {r7, pc} 8001a50: 24060000 .word 0x24060000 8001a54: 00000400 .word 0x00000400 8001a58: 2400032c .word 0x2400032c 8001a5c: 240128c8 .word 0x240128c8 08001a60 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8001a60: b480 push {r7} 8001a62: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8001a64: 4b37 ldr r3, [pc, #220] @ (8001b44 ) 8001a66: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8001a6a: 4a36 ldr r2, [pc, #216] @ (8001b44 ) 8001a6c: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8001a70: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8001a74: 4b34 ldr r3, [pc, #208] @ (8001b48 ) 8001a76: 681b ldr r3, [r3, #0] 8001a78: f003 030f and.w r3, r3, #15 8001a7c: 2b06 cmp r3, #6 8001a7e: d807 bhi.n 8001a90 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8001a80: 4b31 ldr r3, [pc, #196] @ (8001b48 ) 8001a82: 681b ldr r3, [r3, #0] 8001a84: f023 030f bic.w r3, r3, #15 8001a88: 4a2f ldr r2, [pc, #188] @ (8001b48 ) 8001a8a: f043 0307 orr.w r3, r3, #7 8001a8e: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8001a90: 4b2e ldr r3, [pc, #184] @ (8001b4c ) 8001a92: 681b ldr r3, [r3, #0] 8001a94: 4a2d ldr r2, [pc, #180] @ (8001b4c ) 8001a96: f043 0301 orr.w r3, r3, #1 8001a9a: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8001a9c: 4b2b ldr r3, [pc, #172] @ (8001b4c ) 8001a9e: 2200 movs r2, #0 8001aa0: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8001aa2: 4b2a ldr r3, [pc, #168] @ (8001b4c ) 8001aa4: 681a ldr r2, [r3, #0] 8001aa6: 4929 ldr r1, [pc, #164] @ (8001b4c ) 8001aa8: 4b29 ldr r3, [pc, #164] @ (8001b50 ) 8001aaa: 4013 ands r3, r2 8001aac: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8001aae: 4b26 ldr r3, [pc, #152] @ (8001b48 ) 8001ab0: 681b ldr r3, [r3, #0] 8001ab2: f003 0308 and.w r3, r3, #8 8001ab6: 2b00 cmp r3, #0 8001ab8: d007 beq.n 8001aca { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8001aba: 4b23 ldr r3, [pc, #140] @ (8001b48 ) 8001abc: 681b ldr r3, [r3, #0] 8001abe: f023 030f bic.w r3, r3, #15 8001ac2: 4a21 ldr r2, [pc, #132] @ (8001b48 ) 8001ac4: f043 0307 orr.w r3, r3, #7 8001ac8: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 8001aca: 4b20 ldr r3, [pc, #128] @ (8001b4c ) 8001acc: 2200 movs r2, #0 8001ace: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 8001ad0: 4b1e ldr r3, [pc, #120] @ (8001b4c ) 8001ad2: 2200 movs r2, #0 8001ad4: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 8001ad6: 4b1d ldr r3, [pc, #116] @ (8001b4c ) 8001ad8: 2200 movs r2, #0 8001ada: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8001adc: 4b1b ldr r3, [pc, #108] @ (8001b4c ) 8001ade: 4a1d ldr r2, [pc, #116] @ (8001b54 ) 8001ae0: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8001ae2: 4b1a ldr r3, [pc, #104] @ (8001b4c ) 8001ae4: 4a1c ldr r2, [pc, #112] @ (8001b58 ) 8001ae6: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8001ae8: 4b18 ldr r3, [pc, #96] @ (8001b4c ) 8001aea: 4a1c ldr r2, [pc, #112] @ (8001b5c ) 8001aec: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 8001aee: 4b17 ldr r3, [pc, #92] @ (8001b4c ) 8001af0: 2200 movs r2, #0 8001af2: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8001af4: 4b15 ldr r3, [pc, #84] @ (8001b4c ) 8001af6: 4a19 ldr r2, [pc, #100] @ (8001b5c ) 8001af8: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 8001afa: 4b14 ldr r3, [pc, #80] @ (8001b4c ) 8001afc: 2200 movs r2, #0 8001afe: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 8001b00: 4b12 ldr r3, [pc, #72] @ (8001b4c ) 8001b02: 4a16 ldr r2, [pc, #88] @ (8001b5c ) 8001b04: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8001b06: 4b11 ldr r3, [pc, #68] @ (8001b4c ) 8001b08: 2200 movs r2, #0 8001b0a: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8001b0c: 4b0f ldr r3, [pc, #60] @ (8001b4c ) 8001b0e: 681b ldr r3, [r3, #0] 8001b10: 4a0e ldr r2, [pc, #56] @ (8001b4c ) 8001b12: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8001b16: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8001b18: 4b0c ldr r3, [pc, #48] @ (8001b4c ) 8001b1a: 2200 movs r2, #0 8001b1c: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 8001b1e: 4b10 ldr r3, [pc, #64] @ (8001b60 ) 8001b20: 681a ldr r2, [r3, #0] 8001b22: 4b10 ldr r3, [pc, #64] @ (8001b64 ) 8001b24: 4013 ands r3, r2 8001b26: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8001b2a: d202 bcs.n 8001b32 { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 8001b2c: 4b0e ldr r3, [pc, #56] @ (8001b68 ) 8001b2e: 2201 movs r2, #1 8001b30: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 8001b32: 4b0e ldr r3, [pc, #56] @ (8001b6c ) 8001b34: f243 02d2 movw r2, #12498 @ 0x30d2 8001b38: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8001b3a: bf00 nop 8001b3c: 46bd mov sp, r7 8001b3e: f85d 7b04 ldr.w r7, [sp], #4 8001b42: 4770 bx lr 8001b44: e000ed00 .word 0xe000ed00 8001b48: 52002000 .word 0x52002000 8001b4c: 58024400 .word 0x58024400 8001b50: eaf6ed7f .word 0xeaf6ed7f 8001b54: 02020200 .word 0x02020200 8001b58: 01ff0000 .word 0x01ff0000 8001b5c: 01010280 .word 0x01010280 8001b60: 5c001000 .word 0x5c001000 8001b64: ffff0000 .word 0xffff0000 8001b68: 51008108 .word 0x51008108 8001b6c: 52004000 .word 0x52004000 08001b70 : osMutexId_t resMeasurementsMutex; osMutexId_t sensorsInfoMutex; extern RNG_HandleTypeDef hrng; void UartTasksInit(void) { 8001b70: b580 push {r7, lr} 8001b72: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 8001b74: 4b13 ldr r3, [pc, #76] @ (8001bc4 ) 8001b76: 4a14 ldr r2, [pc, #80] @ (8001bc8 ) 8001b78: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 8001b7a: 4b12 ldr r3, [pc, #72] @ (8001bc4 ) 8001b7c: f44f 7280 mov.w r2, #256 @ 0x100 8001b80: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 8001b82: 4b10 ldr r3, [pc, #64] @ (8001bc4 ) 8001b84: 4a11 ldr r2, [pc, #68] @ (8001bcc ) 8001b86: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 8001b88: 4b0e ldr r3, [pc, #56] @ (8001bc4 ) 8001b8a: f44f 7280 mov.w r2, #256 @ 0x100 8001b8e: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 8001b90: 4b0c ldr r3, [pc, #48] @ (8001bc4 ) 8001b92: 4a0f ldr r2, [pc, #60] @ (8001bd0 ) 8001b94: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 8001b96: 4b0b ldr r3, [pc, #44] @ (8001bc4 ) 8001b98: f44f 7280 mov.w r2, #256 @ 0x100 8001b9c: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 8001b9e: 4b09 ldr r3, [pc, #36] @ (8001bc4 ) 8001ba0: 4a0c ldr r2, [pc, #48] @ (8001bd4 ) 8001ba2: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 8001ba4: 4b07 ldr r3, [pc, #28] @ (8001bc4 ) 8001ba6: 2201 movs r2, #1 8001ba8: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 8001bac: 4b05 ldr r3, [pc, #20] @ (8001bc4 ) 8001bae: 4a0a ldr r2, [pc, #40] @ (8001bd8 ) 8001bb0: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 8001bb2: 4b04 ldr r3, [pc, #16] @ (8001bc4 ) 8001bb4: 2200 movs r2, #0 8001bb6: 625a str r2, [r3, #36] @ 0x24 // uart8TaskData.huart = &huart8; // uart8TaskData.uartNumber = 8; // uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; // uart8TaskData.processRxDataMsgBuffer = NULL; UartTaskCreate(&uart1TaskData); 8001bb8: 4802 ldr r0, [pc, #8] @ (8001bc4 ) 8001bba: f000 f80f bl 8001bdc // UartTaskCreate(&uart8TaskData); } 8001bbe: bf00 nop 8001bc0: bd80 pop {r7, pc} 8001bc2: bf00 nop 8001bc4: 24000630 .word 0x24000630 8001bc8: 24000330 .word 0x24000330 8001bcc: 24000430 .word 0x24000430 8001bd0: 24000530 .word 0x24000530 8001bd4: 24000158 .word 0x24000158 8001bd8: 080022e1 .word 0x080022e1 08001bdc : void UartTaskCreate (UartTaskData* uartTaskData) { 8001bdc: b580 push {r7, lr} 8001bde: b08c sub sp, #48 @ 0x30 8001be0: af00 add r7, sp, #0 8001be2: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8001be4: f107 030c add.w r3, r7, #12 8001be8: 2224 movs r2, #36 @ 0x24 8001bea: 2100 movs r1, #0 8001bec: 4618 mov r0, r3 8001bee: f00d fb52 bl 800f296 // osThreadAttr_t osThreadAttrTxUart = { 0 }; osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8001bf2: f44f 6380 mov.w r3, #1024 @ 0x400 8001bf6: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 8001bf8: 2328 movs r3, #40 @ 0x28 8001bfa: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8001bfc: f107 030c add.w r3, r7, #12 8001c00: 461a mov r2, r3 8001c02: 6879 ldr r1, [r7, #4] 8001c04: 4804 ldr r0, [pc, #16] @ (8001c18 ) 8001c06: f009 fc6b bl 800b4e0 8001c0a: 4602 mov r2, r0 8001c0c: 687b ldr r3, [r7, #4] 8001c0e: 619a str r2, [r3, #24] // uartTaskData->sendCmdToSlaveQueue = osMessageQueueNew (16, sizeof (InterProcessData), &uartTxMsgQueueAttr); // osThreadAttrTxUart.stack_size = configMINIMAL_STACK_SIZE * 4; // osThreadAttrTxUart.priority = (osPriority_t)osPriorityNormal; // uartTaskData->uartTransmitTaskHandle = osThreadNew (UartTxTask, uartTaskData, &osThreadAttrTxUart); } 8001c10: bf00 nop 8001c12: 3730 adds r7, #48 @ 0x30 8001c14: 46bd mov sp, r7 8001c16: bd80 pop {r7, pc} 8001c18: 08001d31 .word 0x08001d31 08001c1c : // osThreadAttrTxUart.stack_size = configMINIMAL_STACK_SIZE * 4; // osThreadAttrTxUart.priority = (osPriority_t)osPriorityNormal; // uart8TaskData.uartTransmitTaskHandle = osThreadNew (UartTxTask, &uart8TaskData, &osThreadAttrTxUart); } void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 8001c1c: b480 push {r7} 8001c1e: b083 sub sp, #12 8001c20: af00 add r7, sp, #0 8001c22: 6078 str r0, [r7, #4] // osSemaphoreRelease(uart8RxSemaphore); } 8001c24: bf00 nop 8001c26: 370c adds r7, #12 8001c28: 46bd mov sp, r7 8001c2a: f85d 7b04 ldr.w r7, [sp], #4 8001c2e: 4770 bx lr 08001c30 : void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef* huart, uint16_t Size) { 8001c30: b580 push {r7, lr} 8001c32: b082 sub sp, #8 8001c34: af00 add r7, sp, #0 8001c36: 6078 str r0, [r7, #4] 8001c38: 460b mov r3, r1 8001c3a: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 8001c3c: 687b ldr r3, [r7, #4] 8001c3e: 681b ldr r3, [r3, #0] 8001c40: 4a0c ldr r2, [pc, #48] @ (8001c74 ) 8001c42: 4293 cmp r3, r2 8001c44: d106 bne.n 8001c54 HandleUartRxCallback(&uart1TaskData, huart, Size); 8001c46: 887b ldrh r3, [r7, #2] 8001c48: 461a mov r2, r3 8001c4a: 6879 ldr r1, [r7, #4] 8001c4c: 480a ldr r0, [pc, #40] @ (8001c78 ) 8001c4e: f000 f823 bl 8001c98 } else if (huart->Instance == UART8) { HandleUartRxCallback(&uart8TaskData, huart, Size); } } 8001c52: e00a b.n 8001c6a } else if (huart->Instance == UART8) { 8001c54: 687b ldr r3, [r7, #4] 8001c56: 681b ldr r3, [r3, #0] 8001c58: 4a08 ldr r2, [pc, #32] @ (8001c7c ) 8001c5a: 4293 cmp r3, r2 8001c5c: d105 bne.n 8001c6a HandleUartRxCallback(&uart8TaskData, huart, Size); 8001c5e: 887b ldrh r3, [r7, #2] 8001c60: 461a mov r2, r3 8001c62: 6879 ldr r1, [r7, #4] 8001c64: 4806 ldr r0, [pc, #24] @ (8001c80 ) 8001c66: f000 f817 bl 8001c98 } 8001c6a: bf00 nop 8001c6c: 3708 adds r7, #8 8001c6e: 46bd mov sp, r7 8001c70: bd80 pop {r7, pc} 8001c72: bf00 nop 8001c74: 40011000 .word 0x40011000 8001c78: 24000630 .word 0x24000630 8001c7c: 40007c00 .word 0x40007c00 8001c80: 24000668 .word 0x24000668 08001c84 : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 8001c84: b480 push {r7} 8001c86: b083 sub sp, #12 8001c88: af00 add r7, sp, #0 8001c8a: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 8001c8c: bf00 nop 8001c8e: 370c adds r7, #12 8001c90: 46bd mov sp, r7 8001c92: f85d 7b04 ldr.w r7, [sp], #4 8001c96: 4770 bx lr 08001c98 : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8001c98: b580 push {r7, lr} 8001c9a: b088 sub sp, #32 8001c9c: af02 add r7, sp, #8 8001c9e: 60f8 str r0, [r7, #12] 8001ca0: 60b9 str r1, [r7, #8] 8001ca2: 4613 mov r3, r2 8001ca4: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8001ca6: 2300 movs r3, #0 8001ca8: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8001caa: 68fb ldr r3, [r7, #12] 8001cac: 6a1b ldr r3, [r3, #32] 8001cae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001cb2: 4618 mov r0, r3 8001cb4: f009 fd48 bl 800b748 memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 8001cb8: 68fb ldr r3, [r7, #12] 8001cba: 691b ldr r3, [r3, #16] 8001cbc: 68fa ldr r2, [r7, #12] 8001cbe: 8ad2 ldrh r2, [r2, #22] 8001cc0: 1898 adds r0, r3, r2 8001cc2: 68fb ldr r3, [r7, #12] 8001cc4: 681b ldr r3, [r3, #0] 8001cc6: 88fa ldrh r2, [r7, #6] 8001cc8: 4619 mov r1, r3 8001cca: f00d fbb6 bl 800f43a uartTaskData->frameBytesCount += Size; 8001cce: 68fb ldr r3, [r7, #12] 8001cd0: 8ada ldrh r2, [r3, #22] 8001cd2: 88fb ldrh r3, [r7, #6] 8001cd4: 4413 add r3, r2 8001cd6: b29a uxth r2, r3 8001cd8: 68fb ldr r3, [r7, #12] 8001cda: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8001cdc: 68fb ldr r3, [r7, #12] 8001cde: 6a1b ldr r3, [r3, #32] 8001ce0: 4618 mov r0, r3 8001ce2: f009 fd7c bl 800b7de xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 8001ce6: 68fb ldr r3, [r7, #12] 8001ce8: 6998 ldr r0, [r3, #24] 8001cea: 88f9 ldrh r1, [r7, #6] 8001cec: f107 0314 add.w r3, r7, #20 8001cf0: 9300 str r3, [sp, #0] 8001cf2: 2300 movs r3, #0 8001cf4: 2203 movs r2, #3 8001cf6: f00c f8b9 bl 800de6c // HAL_UARTEx_ReceiveToIdle_DMA(huart, uart8RxBuffer, UART8_RX_BUFF_SIZE); // __HAL_DMA_DISABLE_IT(&hdma_uart8_rx, DMA_IT_HT); HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8001cfa: 68fb ldr r3, [r7, #12] 8001cfc: 6b18 ldr r0, [r3, #48] @ 0x30 8001cfe: 68fb ldr r3, [r7, #12] 8001d00: 6819 ldr r1, [r3, #0] 8001d02: 68fb ldr r3, [r7, #12] 8001d04: 889b ldrh r3, [r3, #4] 8001d06: 461a mov r2, r3 8001d08: f009 fabd bl 800b286 portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8001d0c: 697b ldr r3, [r7, #20] 8001d0e: 2b00 cmp r3, #0 8001d10: d007 beq.n 8001d22 8001d12: 4b06 ldr r3, [pc, #24] @ (8001d2c ) 8001d14: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8001d18: 601a str r2, [r3, #0] 8001d1a: f3bf 8f4f dsb sy 8001d1e: f3bf 8f6f isb sy } 8001d22: bf00 nop 8001d24: 3718 adds r7, #24 8001d26: 46bd mov sp, r7 8001d28: bd80 pop {r7, pc} 8001d2a: bf00 nop 8001d2c: e000ed04 .word 0xe000ed04 08001d30 : void UartRxTask (void* argument) { 8001d30: b580 push {r7, lr} 8001d32: b0d2 sub sp, #328 @ 0x148 8001d34: af02 add r7, sp, #8 8001d36: f507 73a0 add.w r3, r7, #320 @ 0x140 8001d3a: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8001d3e: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 8001d40: f507 73a0 add.w r3, r7, #320 @ 0x140 8001d44: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8001d48: 681b ldr r3, [r3, #0] 8001d4a: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 8001d4e: f507 73a0 add.w r3, r7, #320 @ 0x140 8001d52: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8001d56: 4618 mov r0, r3 8001d58: f44f 7386 mov.w r3, #268 @ 0x10c 8001d5c: 461a mov r2, r3 8001d5e: 2100 movs r1, #0 8001d60: f00d fa99 bl 800f296 uint32_t bytesRec = 0; 8001d64: f507 73a0 add.w r3, r7, #320 @ 0x140 8001d68: f5a3 739a sub.w r3, r3, #308 @ 0x134 8001d6c: 2200 movs r2, #0 8001d6e: 601a str r2, [r3, #0] uint32_t crc = 0; 8001d70: 2300 movs r3, #0 8001d72: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 8001d76: 2300 movs r3, #0 8001d78: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 8001d7c: 2300 movs r3, #0 8001d7e: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 8001d82: 2300 movs r3, #0 8001d84: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 8001d88: 2300 movs r3, #0 8001d8a: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 8001d8e: 2300 movs r3, #0 8001d90: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 8001d94: 2300 movs r3, #0 8001d96: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 8001d9a: 2300 movs r3, #0 8001d9c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 8001da0: 2300 movs r3, #0 8001da2: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 8001da6: 2300 movs r3, #0 8001da8: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8001dac: 2000 movs r0, #0 8001dae: f009 fc45 bl 800b63c 8001db2: 4602 mov r2, r0 8001db4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001db8: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8001dba: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001dbe: 6b18 ldr r0, [r3, #48] @ 0x30 8001dc0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001dc4: 6819 ldr r1, [r3, #0] 8001dc6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001dca: 889b ldrh r3, [r3, #4] 8001dcc: 461a mov r2, r3 8001dce: f009 fa5a bl 800b286 // HAL_UARTEx_ReceiveToIdle_DMA(&huart8, uart8RxBuffer, 32); while (pdTRUE) { // HAL_UART_Receive_IT(&huart8, uart8RxBuffer, 1); // if(osSemaphoreAcquire(uart8RxSemaphore, pdMS_TO_TICKS(1000)) != // osOK) if(xTaskNotifyWait(0, 0, &bytesRec, portMAX_DELAY) == pdTrue) frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8001dd2: f107 020c add.w r2, r7, #12 8001dd6: f44f 63fa mov.w r3, #2000 @ 0x7d0 8001dda: 2100 movs r1, #0 8001ddc: 2000 movs r0, #0 8001dde: f00b ff23 bl 800dc28 8001de2: 4603 mov r3, r0 8001de4: 2b00 cmp r3, #0 8001de6: bf0c ite eq 8001de8: 2301 moveq r3, #1 8001dea: 2300 movne r3, #0 8001dec: b2db uxtb r3, r3 8001dee: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8001df2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001df6: 6a1b ldr r3, [r3, #32] 8001df8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001dfc: 4618 mov r0, r3 8001dfe: f009 fca3 bl 800b748 frameBytesCount = uartTaskData->frameBytesCount; 8001e02: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001e06: 8adb ldrh r3, [r3, #22] 8001e08: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8001e0c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001e10: 6a1b ldr r3, [r3, #32] 8001e12: 4618 mov r0, r3 8001e14: f009 fce3 bl 800b7de if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8001e18: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8001e1c: 2b01 cmp r3, #1 8001e1e: d10a bne.n 8001e36 8001e20: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8001e24: 2b00 cmp r3, #0 8001e26: d006 beq.n 8001e36 receverState = srFail; 8001e28: 2304 movs r3, #4 8001e2a: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 8001e2e: 2301 movs r3, #1 8001e30: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8001e34: e029 b.n 8001e8a } else { if (frameTimeout == pdFALSE) { 8001e36: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8001e3a: 2b00 cmp r3, #0 8001e3c: d111 bne.n 8001e62 proceed = pdTRUE; 8001e3e: 2301 movs r3, #1 8001e40: f8c7 3134 str.w r3, [r7, #308] @ 0x134 #if UART_TASK_LOGS printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); 8001e44: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001e48: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8001e4c: 4619 mov r1, r3 8001e4e: f507 73a0 add.w r3, r7, #320 @ 0x140 8001e52: f5a3 739a sub.w r3, r3, #308 @ 0x134 8001e56: 681b ldr r3, [r3, #0] 8001e58: 461a mov r2, r3 8001e5a: 48c1 ldr r0, [pc, #772] @ (8002160 ) 8001e5c: f00d f9c6 bl 800f1ec 8001e60: e22f b.n 80022c2 #endif } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 8001e62: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001e66: 6b1b ldr r3, [r3, #48] @ 0x30 8001e68: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8001e6c: 2b20 cmp r3, #32 8001e6e: f040 8228 bne.w 80022c2 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8001e72: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001e76: 6b18 ldr r0, [r3, #48] @ 0x30 8001e78: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001e7c: 6819 ldr r1, [r3, #0] 8001e7e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001e82: 889b ldrh r3, [r3, #4] 8001e84: 461a mov r2, r3 8001e86: f009 f9fe bl 800b286 } } } while (proceed) { 8001e8a: e21a b.n 80022c2 switch (receverState) { 8001e8c: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 8001e90: 2b04 cmp r3, #4 8001e92: f200 81f1 bhi.w 8002278 8001e96: a201 add r2, pc, #4 @ (adr r2, 8001e9c ) 8001e98: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8001e9c: 08001eb1 .word 0x08001eb1 8001ea0: 08002013 .word 0x08002013 8001ea4: 08001ff7 .word 0x08001ff7 8001ea8: 080020b3 .word 0x080020b3 8001eac: 0800216d .word 0x0800216d case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8001eb0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001eb4: 6a1b ldr r3, [r3, #32] 8001eb6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001eba: 4618 mov r0, r3 8001ebc: f009 fc44 bl 800b748 if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 8001ec0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001ec4: 691b ldr r3, [r3, #16] 8001ec6: 781b ldrb r3, [r3, #0] 8001ec8: 2baa cmp r3, #170 @ 0xaa 8001eca: f040 8082 bne.w 8001fd2 if (frameBytesCount > FRAME_ID_LENGTH) { 8001ece: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8001ed2: 2b02 cmp r3, #2 8001ed4: d914 bls.n 8001f00 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 8001ed6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001eda: 691b ldr r3, [r3, #16] 8001edc: 3302 adds r3, #2 8001ede: 781b ldrb r3, [r3, #0] 8001ee0: 021b lsls r3, r3, #8 8001ee2: b21a sxth r2, r3 8001ee4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001ee8: 691b ldr r3, [r3, #16] 8001eea: 3301 adds r3, #1 8001eec: 781b ldrb r3, [r3, #0] 8001eee: b21b sxth r3, r3 8001ef0: 4313 orrs r3, r2 8001ef2: b21b sxth r3, r3 8001ef4: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 8001ef6: f507 73a0 add.w r3, r7, #320 @ 0x140 8001efa: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8001efe: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8001f00: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8001f04: 2b04 cmp r3, #4 8001f06: d923 bls.n 8001f50 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 8001f08: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001f0c: 691b ldr r3, [r3, #16] 8001f0e: 3304 adds r3, #4 8001f10: 781b ldrb r3, [r3, #0] 8001f12: 021b lsls r3, r3, #8 8001f14: b21a sxth r2, r3 8001f16: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001f1a: 691b ldr r3, [r3, #16] 8001f1c: 3303 adds r3, #3 8001f1e: 781b ldrb r3, [r3, #0] 8001f20: b21b sxth r3, r3 8001f22: 4313 orrs r3, r2 8001f24: b21b sxth r3, r3 8001f26: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 8001f2a: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 8001f2e: b2da uxtb r2, r3 8001f30: f507 73a0 add.w r3, r7, #320 @ 0x140 8001f34: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8001f38: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 8001f3a: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 8001f3e: 13db asrs r3, r3, #15 8001f40: b21b sxth r3, r3 8001f42: f003 0201 and.w r2, r3, #1 8001f46: f507 73a0 add.w r3, r7, #320 @ 0x140 8001f4a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8001f4e: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 8001f50: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8001f54: 2b05 cmp r3, #5 8001f56: d913 bls.n 8001f80 8001f58: f507 73a0 add.w r3, r7, #320 @ 0x140 8001f5c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8001f60: 789b ldrb r3, [r3, #2] 8001f62: f403 4300 and.w r3, r3, #32768 @ 0x8000 8001f66: 2b00 cmp r3, #0 8001f68: d00a beq.n 8001f80 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 8001f6a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001f6e: 691b ldr r3, [r3, #16] 8001f70: 3305 adds r3, #5 8001f72: 781b ldrb r3, [r3, #0] 8001f74: b25a sxtb r2, r3 8001f76: f507 73a0 add.w r3, r7, #320 @ 0x140 8001f7a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8001f7e: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8001f80: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8001f84: 2b07 cmp r3, #7 8001f86: d920 bls.n 8001fca spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 8001f88: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001f8c: 691b ldr r3, [r3, #16] 8001f8e: 3306 adds r3, #6 8001f90: 781b ldrb r3, [r3, #0] 8001f92: 021b lsls r3, r3, #8 8001f94: b21a sxth r2, r3 8001f96: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001f9a: 691b ldr r3, [r3, #16] 8001f9c: 3305 adds r3, #5 8001f9e: 781b ldrb r3, [r3, #0] 8001fa0: b21b sxth r3, r3 8001fa2: 4313 orrs r3, r2 8001fa4: b21b sxth r3, r3 8001fa6: b29a uxth r2, r3 8001fa8: f507 73a0 add.w r3, r7, #320 @ 0x140 8001fac: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8001fb0: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8001fb2: f507 73a0 add.w r3, r7, #320 @ 0x140 8001fb6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8001fba: 889b ldrh r3, [r3, #4] 8001fbc: 330a adds r3, #10 8001fbe: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 8001fc2: 2302 movs r3, #2 8001fc4: f887 3133 strb.w r3, [r7, #307] @ 0x133 8001fc8: e00e b.n 8001fe8 } else { proceed = pdFALSE; 8001fca: 2300 movs r3, #0 8001fcc: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8001fd0: e00a b.n 8001fe8 } } else { if (frameBytesCount > 0) { 8001fd2: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8001fd6: 2b00 cmp r3, #0 8001fd8: d003 beq.n 8001fe2 receverState = srFail; 8001fda: 2304 movs r3, #4 8001fdc: f887 3133 strb.w r3, [r7, #307] @ 0x133 8001fe0: e002 b.n 8001fe8 } else { proceed = pdFALSE; 8001fe2: 2300 movs r3, #0 8001fe4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 8001fe8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8001fec: 6a1b ldr r3, [r3, #32] 8001fee: 4618 mov r0, r3 8001ff0: f009 fbf5 bl 800b7de break; 8001ff4: e165 b.n 80022c2 case srRecieveData: if (frameBytesCount >= frameTotalLength) { 8001ff6: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 8001ffa: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8001ffe: 429a cmp r2, r3 8002000: d303 bcc.n 800200a receverState = srCheckCrc; 8002002: 2301 movs r3, #1 8002004: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 8002008: e15b b.n 80022c2 proceed = pdFALSE; 800200a: 2300 movs r3, #0 800200c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8002010: e157 b.n 80022c2 case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8002012: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002016: 6a1b ldr r3, [r3, #32] 8002018: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800201c: 4618 mov r0, r3 800201e: f009 fb93 bl 800b748 frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8002022: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002026: 691a ldr r2, [r3, #16] 8002028: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 800202c: 3b01 subs r3, #1 800202e: 4413 add r3, r2 8002030: 781b ldrb r3, [r3, #0] 8002032: 021b lsls r3, r3, #8 8002034: b21a sxth r2, r3 8002036: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800203a: 6919 ldr r1, [r3, #16] 800203c: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8002040: 3b02 subs r3, #2 8002042: 440b add r3, r1 8002044: 781b ldrb r3, [r3, #0] 8002046: b21b sxth r3, r3 8002048: 4313 orrs r3, r2 800204a: b21b sxth r3, r3 800204c: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8002050: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002054: 6919 ldr r1, [r3, #16] 8002056: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 800205a: 3b02 subs r3, #2 800205c: 461a mov r2, r3 800205e: 4841 ldr r0, [pc, #260] @ (8002164 ) 8002060: f000 fcd2 bl 8002a08 8002064: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 8002068: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800206c: 6a1b ldr r3, [r3, #32] 800206e: 4618 mov r0, r3 8002070: f009 fbb5 bl 800b7de crcPass = frameCrc == crc; 8002074: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 8002078: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 800207c: 429a cmp r2, r3 800207e: bf0c ite eq 8002080: 2301 moveq r3, #1 8002082: 2300 movne r3, #0 8002084: b2db uxtb r3, r3 8002086: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 800208a: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 800208e: 2b00 cmp r3, #0 8002090: d00b beq.n 80020aa #if UART_TASK_LOGS printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); 8002092: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002096: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 800209a: 4619 mov r1, r3 800209c: 4832 ldr r0, [pc, #200] @ (8002168 ) 800209e: f00d f8a5 bl 800f1ec #endif receverState = srExecuteCmd; 80020a2: 2303 movs r3, #3 80020a4: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 80020a8: e10b b.n 80022c2 receverState = srFail; 80020aa: 2304 movs r3, #4 80020ac: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 80020b0: e107 b.n 80022c2 case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 80020b2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80020b6: 6a9b ldr r3, [r3, #40] @ 0x28 80020b8: 2b00 cmp r3, #0 80020ba: d104 bne.n 80020c6 80020bc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80020c0: 6a5b ldr r3, [r3, #36] @ 0x24 80020c2: 2b00 cmp r3, #0 80020c4: d01e beq.n 8002104 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80020c6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80020ca: 6a1b ldr r3, [r3, #32] 80020cc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80020d0: 4618 mov r0, r3 80020d2: f009 fb39 bl 800b748 memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 80020d6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80020da: 691b ldr r3, [r3, #16] 80020dc: f103 0108 add.w r1, r3, #8 80020e0: f507 73a0 add.w r3, r7, #320 @ 0x140 80020e4: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80020e8: 889b ldrh r3, [r3, #4] 80020ea: 461a mov r2, r3 80020ec: f107 0310 add.w r3, r7, #16 80020f0: 330c adds r3, #12 80020f2: 4618 mov r0, r3 80020f4: f00d f9a1 bl 800f43a osMutexRelease (uartTaskData->rxDataBufferMutex); 80020f8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80020fc: 6a1b ldr r3, [r3, #32] 80020fe: 4618 mov r0, r3 8002100: f009 fb6d bl 800b7de } if (uartTaskData->processRxDataMsgBuffer != NULL) { 8002104: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002108: 6a5b ldr r3, [r3, #36] @ 0x24 800210a: 2b00 cmp r3, #0 800210c: d015 beq.n 800213a if(xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) 800210e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002112: 6a58 ldr r0, [r3, #36] @ 0x24 8002114: f507 73a0 add.w r3, r7, #320 @ 0x140 8002118: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800211c: 889b ldrh r3, [r3, #4] 800211e: f103 020c add.w r2, r3, #12 8002122: f107 0110 add.w r1, r7, #16 8002126: 23c8 movs r3, #200 @ 0xc8 8002128: f00a fbc8 bl 800c8bc 800212c: 4603 mov r3, r0 800212e: 2b00 cmp r3, #0 8002130: d103 bne.n 800213a { receverState = srFail; 8002132: 2304 movs r3, #4 8002134: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8002138: e0c3 b.n 80022c2 } } if (uartTaskData->processDataCb != NULL) { 800213a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800213e: 6a9b ldr r3, [r3, #40] @ 0x28 8002140: 2b00 cmp r3, #0 8002142: d008 beq.n 8002156 uartTaskData->processDataCb (uartTaskData, &spFrameData); 8002144: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002148: 6a9b ldr r3, [r3, #40] @ 0x28 800214a: f107 0210 add.w r2, r7, #16 800214e: 4611 mov r1, r2 8002150: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 8002154: 4798 blx r3 } receverState = srFinish; 8002156: 2305 movs r3, #5 8002158: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 800215c: e0b1 b.n 80022c2 800215e: bf00 nop 8002160: 0800ffe4 .word 0x0800ffe4 8002164: 2400008c .word 0x2400008c 8002168: 08010004 .word 0x08010004 case srFail: dataToSend = 0; 800216c: 2300 movs r3, #0 800216e: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8002172: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8002176: 2b01 cmp r3, #1 8002178: d124 bne.n 80021c4 800217a: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 800217e: 2b02 cmp r3, #2 8002180: d920 bls.n 80021c4 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8002182: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002186: 6898 ldr r0, [r3, #8] 8002188: f507 73a0 add.w r3, r7, #320 @ 0x140 800218c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8002190: 8819 ldrh r1, [r3, #0] 8002192: f507 73a0 add.w r3, r7, #320 @ 0x140 8002196: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800219a: 789a ldrb r2, [r3, #2] 800219c: 2300 movs r3, #0 800219e: 9301 str r3, [sp, #4] 80021a0: 2300 movs r3, #0 80021a2: 9300 str r3, [sp, #0] 80021a4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80021a8: f7ff f8a6 bl 80012f8 80021ac: 4603 mov r3, r0 80021ae: f8a7 313c strh.w r3, [r7, #316] @ 0x13c #if UART_TASK_LOGS printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); 80021b2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80021b6: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 80021ba: 4619 mov r1, r3 80021bc: 4844 ldr r0, [pc, #272] @ (80022d0 ) 80021be: f00d f815 bl 800f1ec 80021c2: e03c b.n 800223e #endif } else if (!crcPass) { 80021c4: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 80021c8: 2b00 cmp r3, #0 80021ca: d120 bne.n 800220e dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 80021cc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80021d0: 6898 ldr r0, [r3, #8] 80021d2: f507 73a0 add.w r3, r7, #320 @ 0x140 80021d6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80021da: 8819 ldrh r1, [r3, #0] 80021dc: f507 73a0 add.w r3, r7, #320 @ 0x140 80021e0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80021e4: 789a ldrb r2, [r3, #2] 80021e6: 2300 movs r3, #0 80021e8: 9301 str r3, [sp, #4] 80021ea: 2300 movs r3, #0 80021ec: 9300 str r3, [sp, #0] 80021ee: f06f 0301 mvn.w r3, #1 80021f2: f7ff f881 bl 80012f8 80021f6: 4603 mov r3, r0 80021f8: f8a7 313c strh.w r3, [r7, #316] @ 0x13c #if UART_TASK_LOGS printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); 80021fc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002200: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8002204: 4619 mov r1, r3 8002206: 4833 ldr r0, [pc, #204] @ (80022d4 ) 8002208: f00c fff0 bl 800f1ec 800220c: e017 b.n 800223e #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 800220e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002212: 6898 ldr r0, [r3, #8] 8002214: f507 73a0 add.w r3, r7, #320 @ 0x140 8002218: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800221c: 8819 ldrh r1, [r3, #0] 800221e: f507 73a0 add.w r3, r7, #320 @ 0x140 8002222: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8002226: 789a ldrb r2, [r3, #2] 8002228: 2300 movs r3, #0 800222a: 9301 str r3, [sp, #4] 800222c: 2300 movs r3, #0 800222e: 9300 str r3, [sp, #0] 8002230: f06f 0302 mvn.w r3, #2 8002234: f7ff f860 bl 80012f8 8002238: 4603 mov r3, r0 800223a: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 800223e: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 8002242: 2b00 cmp r3, #0 8002244: d00a beq.n 800225c HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8002246: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800224a: 6b18 ldr r0, [r3, #48] @ 0x30 800224c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002250: 689b ldr r3, [r3, #8] 8002252: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 8002256: 4619 mov r1, r3 8002258: f006 fb40 bl 80088dc } #if UART_TASK_LOGS printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); 800225c: f8b7 113c ldrh.w r1, [r7, #316] @ 0x13c 8002260: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002264: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8002268: 461a mov r2, r3 800226a: 481b ldr r0, [pc, #108] @ (80022d8 ) 800226c: f00c ffbe bl 800f1ec #endif receverState = srFinish; 8002270: 2305 movs r3, #5 8002272: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8002276: e024 b.n 80022c2 case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8002278: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800227c: 6a1b ldr r3, [r3, #32] 800227e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002282: 4618 mov r0, r3 8002284: f009 fa60 bl 800b748 uartTaskData->frameBytesCount = 0; 8002288: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800228c: 2200 movs r2, #0 800228e: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8002290: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8002294: 6a1b ldr r3, [r3, #32] 8002296: 4618 mov r0, r3 8002298: f009 faa1 bl 800b7de spFrameData.frameHeader.frameCommand = spUnknown; 800229c: f507 73a0 add.w r3, r7, #320 @ 0x140 80022a0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80022a4: 2208 movs r2, #8 80022a6: 709a strb r2, [r3, #2] frameTotalLength = 0; 80022a8: 2300 movs r3, #0 80022aa: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 80022ae: 4b0b ldr r3, [pc, #44] @ (80022dc ) 80022b0: 2200 movs r2, #0 80022b2: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 80022b4: 2300 movs r3, #0 80022b6: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 80022ba: 2300 movs r3, #0 80022bc: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 80022c0: bf00 nop while (proceed) { 80022c2: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 80022c6: 2b00 cmp r3, #0 80022c8: f47f ade0 bne.w 8001e8c frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 80022cc: e581 b.n 8001dd2 80022ce: bf00 nop 80022d0: 0801001c .word 0x0801001c 80022d4: 08010040 .word 0x08010040 80022d8: 08010058 .word 0x08010058 80022dc: 24000720 .word 0x24000720 080022e0 : void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { Uart1ReceivedDataProcessCallback(arg, spFrameData); } void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 80022e0: b580 push {r7, lr} 80022e2: b08c sub sp, #48 @ 0x30 80022e4: af02 add r7, sp, #8 80022e6: 6078 str r0, [r7, #4] 80022e8: 6039 str r1, [r7, #0] UartTaskData* uartTaskData = (UartTaskData*)arg; 80022ea: 687b ldr r3, [r7, #4] 80022ec: 60fb str r3, [r7, #12] uint16_t dataToSend = 0; 80022ee: 2300 movs r3, #0 80022f0: 84fb strh r3, [r7, #38] @ 0x26 outputDataBufferPos = 0; 80022f2: 4b8b ldr r3, [pc, #556] @ (8002520 ) 80022f4: 2200 movs r2, #0 80022f6: 801a strh r2, [r3, #0] switch (spFrameData->frameHeader.frameCommand) { 80022f8: 683b ldr r3, [r7, #0] 80022fa: 789b ldrb r3, [r3, #2] 80022fc: 2b07 cmp r3, #7 80022fe: f200 80e1 bhi.w 80024c4 8002302: a201 add r2, pc, #4 @ (adr r2, 8002308 ) 8002304: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002308: 08002329 .word 0x08002329 800230c: 08002403 .word 0x08002403 8002310: 080024c5 .word 0x080024c5 8002314: 080024c5 .word 0x080024c5 8002318: 080024c5 .word 0x080024c5 800231c: 080024c5 .word 0x080024c5 8002320: 080024c5 .word 0x080024c5 8002324: 080024c5 .word 0x080024c5 case spGetElectricalMeasurments: osMutexAcquire (resMeasurementsMutex, osWaitForever); 8002328: 4b7e ldr r3, [pc, #504] @ (8002524 ) 800232a: 681b ldr r3, [r3, #0] 800232c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002330: 4618 mov r0, r3 8002332: f009 fa09 bl 800b748 for(int i = 0; i < 3; i++) 8002336: 2300 movs r3, #0 8002338: 623b str r3, [r7, #32] 800233a: e00b b.n 8002354 { WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof(float)); 800233c: 6a3b ldr r3, [r7, #32] 800233e: 009b lsls r3, r3, #2 8002340: 4a79 ldr r2, [pc, #484] @ (8002528 ) 8002342: 441a add r2, r3 8002344: 2304 movs r3, #4 8002346: 4976 ldr r1, [pc, #472] @ (8002520 ) 8002348: 4878 ldr r0, [pc, #480] @ (800252c ) 800234a: f7fe ffa3 bl 8001294 for(int i = 0; i < 3; i++) 800234e: 6a3b ldr r3, [r7, #32] 8002350: 3301 adds r3, #1 8002352: 623b str r3, [r7, #32] 8002354: 6a3b ldr r3, [r7, #32] 8002356: 2b02 cmp r3, #2 8002358: ddf0 ble.n 800233c } for(int i = 0; i < 3; i++) 800235a: 2300 movs r3, #0 800235c: 61fb str r3, [r7, #28] 800235e: e00d b.n 800237c { WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof(float)); 8002360: 69fb ldr r3, [r7, #28] 8002362: 3302 adds r3, #2 8002364: 009b lsls r3, r3, #2 8002366: 4a70 ldr r2, [pc, #448] @ (8002528 ) 8002368: 4413 add r3, r2 800236a: 1d1a adds r2, r3, #4 800236c: 2304 movs r3, #4 800236e: 496c ldr r1, [pc, #432] @ (8002520 ) 8002370: 486e ldr r0, [pc, #440] @ (800252c ) 8002372: f7fe ff8f bl 8001294 for(int i = 0; i < 3; i++) 8002376: 69fb ldr r3, [r7, #28] 8002378: 3301 adds r3, #1 800237a: 61fb str r3, [r7, #28] 800237c: 69fb ldr r3, [r7, #28] 800237e: 2b02 cmp r3, #2 8002380: ddee ble.n 8002360 } for(int i = 0; i < 3; i++) 8002382: 2300 movs r3, #0 8002384: 61bb str r3, [r7, #24] 8002386: e00c b.n 80023a2 { WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof(float)); 8002388: 69bb ldr r3, [r7, #24] 800238a: 3306 adds r3, #6 800238c: 009b lsls r3, r3, #2 800238e: 4a66 ldr r2, [pc, #408] @ (8002528 ) 8002390: 441a add r2, r3 8002392: 2304 movs r3, #4 8002394: 4962 ldr r1, [pc, #392] @ (8002520 ) 8002396: 4865 ldr r0, [pc, #404] @ (800252c ) 8002398: f7fe ff7c bl 8001294 for(int i = 0; i < 3; i++) 800239c: 69bb ldr r3, [r7, #24] 800239e: 3301 adds r3, #1 80023a0: 61bb str r3, [r7, #24] 80023a2: 69bb ldr r3, [r7, #24] 80023a4: 2b02 cmp r3, #2 80023a6: ddef ble.n 8002388 } for(int i = 0; i < 3; i++) 80023a8: 2300 movs r3, #0 80023aa: 617b str r3, [r7, #20] 80023ac: e00d b.n 80023ca { WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof(float)); 80023ae: 697b ldr r3, [r7, #20] 80023b0: 3308 adds r3, #8 80023b2: 009b lsls r3, r3, #2 80023b4: 4a5c ldr r2, [pc, #368] @ (8002528 ) 80023b6: 4413 add r3, r2 80023b8: 1d1a adds r2, r3, #4 80023ba: 2304 movs r3, #4 80023bc: 4958 ldr r1, [pc, #352] @ (8002520 ) 80023be: 485b ldr r0, [pc, #364] @ (800252c ) 80023c0: f7fe ff68 bl 8001294 for(int i = 0; i < 3; i++) 80023c4: 697b ldr r3, [r7, #20] 80023c6: 3301 adds r3, #1 80023c8: 617b str r3, [r7, #20] 80023ca: 697b ldr r3, [r7, #20] 80023cc: 2b02 cmp r3, #2 80023ce: ddee ble.n 80023ae } for(int i = 0; i < 3; i++) 80023d0: 2300 movs r3, #0 80023d2: 613b str r3, [r7, #16] 80023d4: e00c b.n 80023f0 { WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof(float)); 80023d6: 693b ldr r3, [r7, #16] 80023d8: 330c adds r3, #12 80023da: 009b lsls r3, r3, #2 80023dc: 4a52 ldr r2, [pc, #328] @ (8002528 ) 80023de: 441a add r2, r3 80023e0: 2304 movs r3, #4 80023e2: 494f ldr r1, [pc, #316] @ (8002520 ) 80023e4: 4851 ldr r0, [pc, #324] @ (800252c ) 80023e6: f7fe ff55 bl 8001294 for(int i = 0; i < 3; i++) 80023ea: 693b ldr r3, [r7, #16] 80023ec: 3301 adds r3, #1 80023ee: 613b str r3, [r7, #16] 80023f0: 693b ldr r3, [r7, #16] 80023f2: 2b02 cmp r3, #2 80023f4: ddef ble.n 80023d6 } osMutexRelease(resMeasurementsMutex); 80023f6: 4b4b ldr r3, [pc, #300] @ (8002524 ) 80023f8: 681b ldr r3, [r3, #0] 80023fa: 4618 mov r0, r3 80023fc: f009 f9ef bl 800b7de break; 8002400: e061 b.n 80024c6 case spGetSensorMeasurments: osMutexAcquire (resMeasurementsMutex, osWaitForever); 8002402: 4b48 ldr r3, [pc, #288] @ (8002524 ) 8002404: 681b ldr r3, [r3, #0] 8002406: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800240a: 4618 mov r0, r3 800240c: f009 f99c bl 800b748 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof(float)); 8002410: 2304 movs r3, #4 8002412: 4a47 ldr r2, [pc, #284] @ (8002530 ) 8002414: 4942 ldr r1, [pc, #264] @ (8002520 ) 8002416: 4845 ldr r0, [pc, #276] @ (800252c ) 8002418: f7fe ff3c bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof(float)); 800241c: 2304 movs r3, #4 800241e: 4a45 ldr r2, [pc, #276] @ (8002534 ) 8002420: 493f ldr r1, [pc, #252] @ (8002520 ) 8002422: 4842 ldr r0, [pc, #264] @ (800252c ) 8002424: f7fe ff36 bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof(float)); 8002428: 2304 movs r3, #4 800242a: 4a43 ldr r2, [pc, #268] @ (8002538 ) 800242c: 493c ldr r1, [pc, #240] @ (8002520 ) 800242e: 483f ldr r0, [pc, #252] @ (800252c ) 8002430: f7fe ff30 bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoder, sizeof(float)); 8002434: 2304 movs r3, #4 8002436: 4a41 ldr r2, [pc, #260] @ (800253c ) 8002438: 4939 ldr r1, [pc, #228] @ (8002520 ) 800243a: 483c ldr r0, [pc, #240] @ (800252c ) 800243c: f7fe ff2a bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof(uint8_t)); 8002440: 2301 movs r3, #1 8002442: 4a3f ldr r2, [pc, #252] @ (8002540 ) 8002444: 4936 ldr r1, [pc, #216] @ (8002520 ) 8002446: 4839 ldr r0, [pc, #228] @ (800252c ) 8002448: f7fe ff24 bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof(uint8_t)); 800244c: 2301 movs r3, #1 800244e: 4a3d ldr r2, [pc, #244] @ (8002544 ) 8002450: 4933 ldr r1, [pc, #204] @ (8002520 ) 8002452: 4836 ldr r0, [pc, #216] @ (800252c ) 8002454: f7fe ff1e bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof(float)); 8002458: 2304 movs r3, #4 800245a: 4a3b ldr r2, [pc, #236] @ (8002548 ) 800245c: 4930 ldr r1, [pc, #192] @ (8002520 ) 800245e: 4833 ldr r0, [pc, #204] @ (800252c ) 8002460: f7fe ff18 bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof(float)); 8002464: 2304 movs r3, #4 8002466: 4a39 ldr r2, [pc, #228] @ (800254c ) 8002468: 492d ldr r1, [pc, #180] @ (8002520 ) 800246a: 4830 ldr r0, [pc, #192] @ (800252c ) 800246c: f7fe ff12 bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof(float)); 8002470: 2304 movs r3, #4 8002472: 4a37 ldr r2, [pc, #220] @ (8002550 ) 8002474: 492a ldr r1, [pc, #168] @ (8002520 ) 8002476: 482d ldr r0, [pc, #180] @ (800252c ) 8002478: f7fe ff0c bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof(float)); 800247c: 2304 movs r3, #4 800247e: 4a35 ldr r2, [pc, #212] @ (8002554 ) 8002480: 4927 ldr r1, [pc, #156] @ (8002520 ) 8002482: 482a ldr r0, [pc, #168] @ (800252c ) 8002484: f7fe ff06 bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitSwitchUp, sizeof(uint8_t)); 8002488: 2301 movs r3, #1 800248a: 4a33 ldr r2, [pc, #204] @ (8002558 ) 800248c: 4924 ldr r1, [pc, #144] @ (8002520 ) 800248e: 4827 ldr r0, [pc, #156] @ (800252c ) 8002490: f7fe ff00 bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitSwitchDown, sizeof(uint8_t)); 8002494: 2301 movs r3, #1 8002496: 4a31 ldr r2, [pc, #196] @ (800255c ) 8002498: 4921 ldr r1, [pc, #132] @ (8002520 ) 800249a: 4824 ldr r0, [pc, #144] @ (800252c ) 800249c: f7fe fefa bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitSwitchCenter, sizeof(uint8_t)); 80024a0: 2301 movs r3, #1 80024a2: 4a2f ldr r2, [pc, #188] @ (8002560 ) 80024a4: 491e ldr r1, [pc, #120] @ (8002520 ) 80024a6: 4821 ldr r0, [pc, #132] @ (800252c ) 80024a8: f7fe fef4 bl 8001294 WriteDataToBuffer(outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof(uint8_t)); 80024ac: 2301 movs r3, #1 80024ae: 4a2d ldr r2, [pc, #180] @ (8002564 ) 80024b0: 491b ldr r1, [pc, #108] @ (8002520 ) 80024b2: 481e ldr r0, [pc, #120] @ (800252c ) 80024b4: f7fe feee bl 8001294 osMutexRelease(resMeasurementsMutex); 80024b8: 4b1a ldr r3, [pc, #104] @ (8002524 ) 80024ba: 681b ldr r3, [r3, #0] 80024bc: 4618 mov r0, r3 80024be: f009 f98e bl 800b7de break; 80024c2: e000 b.n 80024c6 case spSetMotorYOn: break; case spSetDiodeOn: break; case spSetmotorXMaxCurrent: case spSetmotorYMaxCurrent: break; default: break; 80024c4: bf00 nop } if (outputDataBufferPos > 0) { 80024c6: 4b16 ldr r3, [pc, #88] @ (8002520 ) 80024c8: 881b ldrh r3, [r3, #0] 80024ca: 2b00 cmp r3, #0 80024cc: d00f beq.n 80024ee dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, spOK, outputDataBuffer, outputDataBufferPos); 80024ce: 68fb ldr r3, [r7, #12] 80024d0: 6898 ldr r0, [r3, #8] 80024d2: 683b ldr r3, [r7, #0] 80024d4: 8819 ldrh r1, [r3, #0] 80024d6: 683b ldr r3, [r7, #0] 80024d8: 789a ldrb r2, [r3, #2] 80024da: 4b11 ldr r3, [pc, #68] @ (8002520 ) 80024dc: 881b ldrh r3, [r3, #0] 80024de: 9301 str r3, [sp, #4] 80024e0: 4b12 ldr r3, [pc, #72] @ (800252c ) 80024e2: 9300 str r3, [sp, #0] 80024e4: 2300 movs r3, #0 80024e6: f7fe ff07 bl 80012f8 80024ea: 4603 mov r3, r0 80024ec: 84fb strh r3, [r7, #38] @ 0x26 } if (dataToSend > 0) { 80024ee: 8cfb ldrh r3, [r7, #38] @ 0x26 80024f0: 2b00 cmp r3, #0 80024f2: d007 beq.n 8002504 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 80024f4: 68fb ldr r3, [r7, #12] 80024f6: 6b18 ldr r0, [r3, #48] @ 0x30 80024f8: 68fb ldr r3, [r7, #12] 80024fa: 689b ldr r3, [r3, #8] 80024fc: 8cfa ldrh r2, [r7, #38] @ 0x26 80024fe: 4619 mov r1, r3 8002500: f006 f9ec bl 80088dc } #if UART_TASK_LOGS printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); 8002504: 68fb ldr r3, [r7, #12] 8002506: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 800250a: 4619 mov r1, r3 800250c: 8cfb ldrh r3, [r7, #38] @ 0x26 800250e: 461a mov r2, r3 8002510: 4815 ldr r0, [pc, #84] @ (8002568 ) 8002512: f00c fe6b bl 800f1ec #endif } 8002516: bf00 nop 8002518: 3728 adds r7, #40 @ 0x28 800251a: 46bd mov sp, r7 800251c: bd80 pop {r7, pc} 800251e: bf00 nop 8002520: 24000720 .word 0x24000720 8002524: 24000788 .word 0x24000788 8002528: 24000724 .word 0x24000724 800252c: 240006a0 .word 0x240006a0 8002530: 24000760 .word 0x24000760 8002534: 24000764 .word 0x24000764 8002538: 24000768 .word 0x24000768 800253c: 2400076c .word 0x2400076c 8002540: 24000770 .word 0x24000770 8002544: 24000771 .word 0x24000771 8002548: 24000774 .word 0x24000774 800254c: 24000778 .word 0x24000778 8002550: 2400077c .word 0x2400077c 8002554: 24000780 .word 0x24000780 8002558: 24000784 .word 0x24000784 800255c: 24000785 .word 0x24000785 8002560: 24000786 .word 0x24000786 8002564: 24000787 .word 0x24000787 8002568: 08010058 .word 0x08010058 0800256c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 800256c: f8df d034 ldr.w sp, [pc, #52] @ 80025a4 /* Call the clock system initialization function.*/ bl SystemInit 8002570: f7ff fa76 bl 8001a60 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8002574: 480c ldr r0, [pc, #48] @ (80025a8 ) ldr r1, =_edata 8002576: 490d ldr r1, [pc, #52] @ (80025ac ) ldr r2, =_sidata 8002578: 4a0d ldr r2, [pc, #52] @ (80025b0 ) movs r3, #0 800257a: 2300 movs r3, #0 b LoopCopyDataInit 800257c: e002 b.n 8002584 0800257e : CopyDataInit: ldr r4, [r2, r3] 800257e: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8002580: 50c4 str r4, [r0, r3] adds r3, r3, #4 8002582: 3304 adds r3, #4 08002584 : LoopCopyDataInit: adds r4, r0, r3 8002584: 18c4 adds r4, r0, r3 cmp r4, r1 8002586: 428c cmp r4, r1 bcc CopyDataInit 8002588: d3f9 bcc.n 800257e /* Zero fill the bss segment. */ ldr r2, =_sbss 800258a: 4a0a ldr r2, [pc, #40] @ (80025b4 ) ldr r4, =_ebss 800258c: 4c0a ldr r4, [pc, #40] @ (80025b8 ) movs r3, #0 800258e: 2300 movs r3, #0 b LoopFillZerobss 8002590: e001 b.n 8002596 08002592 : FillZerobss: str r3, [r2] 8002592: 6013 str r3, [r2, #0] adds r2, r2, #4 8002594: 3204 adds r2, #4 08002596 : LoopFillZerobss: cmp r2, r4 8002596: 42a2 cmp r2, r4 bcc FillZerobss 8002598: d3fb bcc.n 8002592 /* Call static constructors */ bl __libc_init_array 800259a: f00c ff27 bl 800f3ec <__libc_init_array> /* Call the application's entry point.*/ bl main 800259e: f7fe f873 bl 8000688
bx lr 80025a2: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80025a4: 24060000 .word 0x24060000 ldr r0, =_sdata 80025a8: 24000000 .word 0x24000000 ldr r1, =_edata 80025ac: 24000070 .word 0x24000070 ldr r2, =_sidata 80025b0: 08010134 .word 0x08010134 ldr r2, =_sbss 80025b4: 24000070 .word 0x24000070 ldr r4, =_ebss 80025b8: 240128c8 .word 0x240128c8 080025bc : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80025bc: e7fe b.n 80025bc ... 080025c0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80025c0: b580 push {r7, lr} 80025c2: b082 sub sp, #8 80025c4: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80025c6: 2003 movs r0, #3 80025c8: f000 f90f bl 80027ea /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 80025cc: f003 fdde bl 800618c 80025d0: 4602 mov r2, r0 80025d2: 4b15 ldr r3, [pc, #84] @ (8002628 ) 80025d4: 699b ldr r3, [r3, #24] 80025d6: 0a1b lsrs r3, r3, #8 80025d8: f003 030f and.w r3, r3, #15 80025dc: 4913 ldr r1, [pc, #76] @ (800262c ) 80025de: 5ccb ldrb r3, [r1, r3] 80025e0: f003 031f and.w r3, r3, #31 80025e4: fa22 f303 lsr.w r3, r2, r3 80025e8: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 80025ea: 4b0f ldr r3, [pc, #60] @ (8002628 ) 80025ec: 699b ldr r3, [r3, #24] 80025ee: f003 030f and.w r3, r3, #15 80025f2: 4a0e ldr r2, [pc, #56] @ (800262c ) 80025f4: 5cd3 ldrb r3, [r2, r3] 80025f6: f003 031f and.w r3, r3, #31 80025fa: 687a ldr r2, [r7, #4] 80025fc: fa22 f303 lsr.w r3, r2, r3 8002600: 4a0b ldr r2, [pc, #44] @ (8002630 ) 8002602: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8002604: 4a0b ldr r2, [pc, #44] @ (8002634 ) 8002606: 687b ldr r3, [r7, #4] 8002608: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 800260a: 200f movs r0, #15 800260c: f7ff f8c4 bl 8001798 8002610: 4603 mov r3, r0 8002612: 2b00 cmp r3, #0 8002614: d001 beq.n 800261a { return HAL_ERROR; 8002616: 2301 movs r3, #1 8002618: e002 b.n 8002620 } /* Init the low level hardware */ HAL_MspInit(); 800261a: f7fe ff0b bl 8001434 /* Return function status */ return HAL_OK; 800261e: 2300 movs r3, #0 } 8002620: 4618 mov r0, r3 8002622: 3708 adds r7, #8 8002624: 46bd mov sp, r7 8002626: bd80 pop {r7, pc} 8002628: 58024400 .word 0x58024400 800262c: 080100b0 .word 0x080100b0 8002630: 24000004 .word 0x24000004 8002634: 24000000 .word 0x24000000 08002638 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8002638: b480 push {r7} 800263a: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 800263c: 4b06 ldr r3, [pc, #24] @ (8002658 ) 800263e: 781b ldrb r3, [r3, #0] 8002640: 461a mov r2, r3 8002642: 4b06 ldr r3, [pc, #24] @ (800265c ) 8002644: 681b ldr r3, [r3, #0] 8002646: 4413 add r3, r2 8002648: 4a04 ldr r2, [pc, #16] @ (800265c ) 800264a: 6013 str r3, [r2, #0] } 800264c: bf00 nop 800264e: 46bd mov sp, r7 8002650: f85d 7b04 ldr.w r7, [sp], #4 8002654: 4770 bx lr 8002656: bf00 nop 8002658: 2400000c .word 0x2400000c 800265c: 24000790 .word 0x24000790 08002660 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8002660: b480 push {r7} 8002662: af00 add r7, sp, #0 return uwTick; 8002664: 4b03 ldr r3, [pc, #12] @ (8002674 ) 8002666: 681b ldr r3, [r3, #0] } 8002668: 4618 mov r0, r3 800266a: 46bd mov sp, r7 800266c: f85d 7b04 ldr.w r7, [sp], #4 8002670: 4770 bx lr 8002672: bf00 nop 8002674: 24000790 .word 0x24000790 08002678 : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 8002678: b480 push {r7} 800267a: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 800267c: 4b03 ldr r3, [pc, #12] @ (800268c ) 800267e: 681b ldr r3, [r3, #0] 8002680: 0c1b lsrs r3, r3, #16 } 8002682: 4618 mov r0, r3 8002684: 46bd mov sp, r7 8002686: f85d 7b04 ldr.w r7, [sp], #4 800268a: 4770 bx lr 800268c: 5c001000 .word 0x5c001000 08002690 <__NVIC_SetPriorityGrouping>: { 8002690: b480 push {r7} 8002692: b085 sub sp, #20 8002694: af00 add r7, sp, #0 8002696: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002698: 687b ldr r3, [r7, #4] 800269a: f003 0307 and.w r3, r3, #7 800269e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80026a0: 4b0b ldr r3, [pc, #44] @ (80026d0 <__NVIC_SetPriorityGrouping+0x40>) 80026a2: 68db ldr r3, [r3, #12] 80026a4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80026a6: 68ba ldr r2, [r7, #8] 80026a8: f64f 03ff movw r3, #63743 @ 0xf8ff 80026ac: 4013 ands r3, r2 80026ae: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80026b0: 68fb ldr r3, [r7, #12] 80026b2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80026b4: 68bb ldr r3, [r7, #8] 80026b6: 431a orrs r2, r3 reg_value = (reg_value | 80026b8: 4b06 ldr r3, [pc, #24] @ (80026d4 <__NVIC_SetPriorityGrouping+0x44>) 80026ba: 4313 orrs r3, r2 80026bc: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80026be: 4a04 ldr r2, [pc, #16] @ (80026d0 <__NVIC_SetPriorityGrouping+0x40>) 80026c0: 68bb ldr r3, [r7, #8] 80026c2: 60d3 str r3, [r2, #12] } 80026c4: bf00 nop 80026c6: 3714 adds r7, #20 80026c8: 46bd mov sp, r7 80026ca: f85d 7b04 ldr.w r7, [sp], #4 80026ce: 4770 bx lr 80026d0: e000ed00 .word 0xe000ed00 80026d4: 05fa0000 .word 0x05fa0000 080026d8 <__NVIC_GetPriorityGrouping>: { 80026d8: b480 push {r7} 80026da: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 80026dc: 4b04 ldr r3, [pc, #16] @ (80026f0 <__NVIC_GetPriorityGrouping+0x18>) 80026de: 68db ldr r3, [r3, #12] 80026e0: 0a1b lsrs r3, r3, #8 80026e2: f003 0307 and.w r3, r3, #7 } 80026e6: 4618 mov r0, r3 80026e8: 46bd mov sp, r7 80026ea: f85d 7b04 ldr.w r7, [sp], #4 80026ee: 4770 bx lr 80026f0: e000ed00 .word 0xe000ed00 080026f4 <__NVIC_EnableIRQ>: { 80026f4: b480 push {r7} 80026f6: b083 sub sp, #12 80026f8: af00 add r7, sp, #0 80026fa: 4603 mov r3, r0 80026fc: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 80026fe: f9b7 3006 ldrsh.w r3, [r7, #6] 8002702: 2b00 cmp r3, #0 8002704: db0b blt.n 800271e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8002706: 88fb ldrh r3, [r7, #6] 8002708: f003 021f and.w r2, r3, #31 800270c: 4907 ldr r1, [pc, #28] @ (800272c <__NVIC_EnableIRQ+0x38>) 800270e: f9b7 3006 ldrsh.w r3, [r7, #6] 8002712: 095b lsrs r3, r3, #5 8002714: 2001 movs r0, #1 8002716: fa00 f202 lsl.w r2, r0, r2 800271a: f841 2023 str.w r2, [r1, r3, lsl #2] } 800271e: bf00 nop 8002720: 370c adds r7, #12 8002722: 46bd mov sp, r7 8002724: f85d 7b04 ldr.w r7, [sp], #4 8002728: 4770 bx lr 800272a: bf00 nop 800272c: e000e100 .word 0xe000e100 08002730 <__NVIC_SetPriority>: { 8002730: b480 push {r7} 8002732: b083 sub sp, #12 8002734: af00 add r7, sp, #0 8002736: 4603 mov r3, r0 8002738: 6039 str r1, [r7, #0] 800273a: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 800273c: f9b7 3006 ldrsh.w r3, [r7, #6] 8002740: 2b00 cmp r3, #0 8002742: db0a blt.n 800275a <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8002744: 683b ldr r3, [r7, #0] 8002746: b2da uxtb r2, r3 8002748: 490c ldr r1, [pc, #48] @ (800277c <__NVIC_SetPriority+0x4c>) 800274a: f9b7 3006 ldrsh.w r3, [r7, #6] 800274e: 0112 lsls r2, r2, #4 8002750: b2d2 uxtb r2, r2 8002752: 440b add r3, r1 8002754: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8002758: e00a b.n 8002770 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800275a: 683b ldr r3, [r7, #0] 800275c: b2da uxtb r2, r3 800275e: 4908 ldr r1, [pc, #32] @ (8002780 <__NVIC_SetPriority+0x50>) 8002760: 88fb ldrh r3, [r7, #6] 8002762: f003 030f and.w r3, r3, #15 8002766: 3b04 subs r3, #4 8002768: 0112 lsls r2, r2, #4 800276a: b2d2 uxtb r2, r2 800276c: 440b add r3, r1 800276e: 761a strb r2, [r3, #24] } 8002770: bf00 nop 8002772: 370c adds r7, #12 8002774: 46bd mov sp, r7 8002776: f85d 7b04 ldr.w r7, [sp], #4 800277a: 4770 bx lr 800277c: e000e100 .word 0xe000e100 8002780: e000ed00 .word 0xe000ed00 08002784 : { 8002784: b480 push {r7} 8002786: b089 sub sp, #36 @ 0x24 8002788: af00 add r7, sp, #0 800278a: 60f8 str r0, [r7, #12] 800278c: 60b9 str r1, [r7, #8] 800278e: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8002790: 68fb ldr r3, [r7, #12] 8002792: f003 0307 and.w r3, r3, #7 8002796: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8002798: 69fb ldr r3, [r7, #28] 800279a: f1c3 0307 rsb r3, r3, #7 800279e: 2b04 cmp r3, #4 80027a0: bf28 it cs 80027a2: 2304 movcs r3, #4 80027a4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80027a6: 69fb ldr r3, [r7, #28] 80027a8: 3304 adds r3, #4 80027aa: 2b06 cmp r3, #6 80027ac: d902 bls.n 80027b4 80027ae: 69fb ldr r3, [r7, #28] 80027b0: 3b03 subs r3, #3 80027b2: e000 b.n 80027b6 80027b4: 2300 movs r3, #0 80027b6: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80027b8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80027bc: 69bb ldr r3, [r7, #24] 80027be: fa02 f303 lsl.w r3, r2, r3 80027c2: 43da mvns r2, r3 80027c4: 68bb ldr r3, [r7, #8] 80027c6: 401a ands r2, r3 80027c8: 697b ldr r3, [r7, #20] 80027ca: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80027cc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80027d0: 697b ldr r3, [r7, #20] 80027d2: fa01 f303 lsl.w r3, r1, r3 80027d6: 43d9 mvns r1, r3 80027d8: 687b ldr r3, [r7, #4] 80027da: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80027dc: 4313 orrs r3, r2 } 80027de: 4618 mov r0, r3 80027e0: 3724 adds r7, #36 @ 0x24 80027e2: 46bd mov sp, r7 80027e4: f85d 7b04 ldr.w r7, [sp], #4 80027e8: 4770 bx lr 080027ea : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80027ea: b580 push {r7, lr} 80027ec: b082 sub sp, #8 80027ee: af00 add r7, sp, #0 80027f0: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 80027f2: 6878 ldr r0, [r7, #4] 80027f4: f7ff ff4c bl 8002690 <__NVIC_SetPriorityGrouping> } 80027f8: bf00 nop 80027fa: 3708 adds r7, #8 80027fc: 46bd mov sp, r7 80027fe: bd80 pop {r7, pc} 08002800 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8002800: b580 push {r7, lr} 8002802: b086 sub sp, #24 8002804: af00 add r7, sp, #0 8002806: 4603 mov r3, r0 8002808: 60b9 str r1, [r7, #8] 800280a: 607a str r2, [r7, #4] 800280c: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800280e: f7ff ff63 bl 80026d8 <__NVIC_GetPriorityGrouping> 8002812: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8002814: 687a ldr r2, [r7, #4] 8002816: 68b9 ldr r1, [r7, #8] 8002818: 6978 ldr r0, [r7, #20] 800281a: f7ff ffb3 bl 8002784 800281e: 4602 mov r2, r0 8002820: f9b7 300e ldrsh.w r3, [r7, #14] 8002824: 4611 mov r1, r2 8002826: 4618 mov r0, r3 8002828: f7ff ff82 bl 8002730 <__NVIC_SetPriority> } 800282c: bf00 nop 800282e: 3718 adds r7, #24 8002830: 46bd mov sp, r7 8002832: bd80 pop {r7, pc} 08002834 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8002834: b580 push {r7, lr} 8002836: b082 sub sp, #8 8002838: af00 add r7, sp, #0 800283a: 4603 mov r3, r0 800283c: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800283e: f9b7 3006 ldrsh.w r3, [r7, #6] 8002842: 4618 mov r0, r3 8002844: f7ff ff56 bl 80026f4 <__NVIC_EnableIRQ> } 8002848: bf00 nop 800284a: 3708 adds r7, #8 800284c: 46bd mov sp, r7 800284e: bd80 pop {r7, pc} 08002850 : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 8002850: b480 push {r7} 8002852: af00 add r7, sp, #0 \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __STATIC_FORCEINLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); 8002854: f3bf 8f5f dmb sy } 8002858: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 800285a: 4b07 ldr r3, [pc, #28] @ (8002878 ) 800285c: 6a5b ldr r3, [r3, #36] @ 0x24 800285e: 4a06 ldr r2, [pc, #24] @ (8002878 ) 8002860: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002864: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 8002866: 4b05 ldr r3, [pc, #20] @ (800287c ) 8002868: 2200 movs r2, #0 800286a: 605a str r2, [r3, #4] } 800286c: bf00 nop 800286e: 46bd mov sp, r7 8002870: f85d 7b04 ldr.w r7, [sp], #4 8002874: 4770 bx lr 8002876: bf00 nop 8002878: e000ed00 .word 0xe000ed00 800287c: e000ed90 .word 0xe000ed90 08002880 : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 8002880: b480 push {r7} 8002882: b083 sub sp, #12 8002884: af00 add r7, sp, #0 8002886: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8002888: 4a0b ldr r2, [pc, #44] @ (80028b8 ) 800288a: 687b ldr r3, [r7, #4] 800288c: f043 0301 orr.w r3, r3, #1 8002890: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 8002892: 4b0a ldr r3, [pc, #40] @ (80028bc ) 8002894: 6a5b ldr r3, [r3, #36] @ 0x24 8002896: 4a09 ldr r2, [pc, #36] @ (80028bc ) 8002898: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800289c: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 800289e: f3bf 8f4f dsb sy } 80028a2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80028a4: f3bf 8f6f isb sy } 80028a8: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 80028aa: bf00 nop 80028ac: 370c adds r7, #12 80028ae: 46bd mov sp, r7 80028b0: f85d 7b04 ldr.w r7, [sp], #4 80028b4: 4770 bx lr 80028b6: bf00 nop 80028b8: e000ed90 .word 0xe000ed90 80028bc: e000ed00 .word 0xe000ed00 080028c0 : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 80028c0: b480 push {r7} 80028c2: b083 sub sp, #12 80028c4: af00 add r7, sp, #0 80028c6: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 80028c8: 687b ldr r3, [r7, #4] 80028ca: 785a ldrb r2, [r3, #1] 80028cc: 4b1b ldr r3, [pc, #108] @ (800293c ) 80028ce: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 80028d0: 4b1a ldr r3, [pc, #104] @ (800293c ) 80028d2: 691b ldr r3, [r3, #16] 80028d4: 4a19 ldr r2, [pc, #100] @ (800293c ) 80028d6: f023 0301 bic.w r3, r3, #1 80028da: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 80028dc: 4a17 ldr r2, [pc, #92] @ (800293c ) 80028de: 687b ldr r3, [r7, #4] 80028e0: 685b ldr r3, [r3, #4] 80028e2: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80028e4: 687b ldr r3, [r7, #4] 80028e6: 7b1b ldrb r3, [r3, #12] 80028e8: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 80028ea: 687b ldr r3, [r7, #4] 80028ec: 7adb ldrb r3, [r3, #11] 80028ee: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 80028f0: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 80028f2: 687b ldr r3, [r7, #4] 80028f4: 7a9b ldrb r3, [r3, #10] 80028f6: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 80028f8: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 80028fa: 687b ldr r3, [r7, #4] 80028fc: 7b5b ldrb r3, [r3, #13] 80028fe: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8002900: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8002902: 687b ldr r3, [r7, #4] 8002904: 7b9b ldrb r3, [r3, #14] 8002906: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8002908: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 800290a: 687b ldr r3, [r7, #4] 800290c: 7bdb ldrb r3, [r3, #15] 800290e: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8002910: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8002912: 687b ldr r3, [r7, #4] 8002914: 7a5b ldrb r3, [r3, #9] 8002916: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8002918: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 800291a: 687b ldr r3, [r7, #4] 800291c: 7a1b ldrb r3, [r3, #8] 800291e: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8002920: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 8002922: 687a ldr r2, [r7, #4] 8002924: 7812 ldrb r2, [r2, #0] 8002926: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8002928: 4a04 ldr r2, [pc, #16] @ (800293c ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 800292a: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 800292c: 6113 str r3, [r2, #16] } 800292e: bf00 nop 8002930: 370c adds r7, #12 8002932: 46bd mov sp, r7 8002934: f85d 7b04 ldr.w r7, [sp], #4 8002938: 4770 bx lr 800293a: bf00 nop 800293c: e000ed90 .word 0xe000ed90 08002940 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 8002940: b580 push {r7, lr} 8002942: b082 sub sp, #8 8002944: af00 add r7, sp, #0 8002946: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8002948: 687b ldr r3, [r7, #4] 800294a: 2b00 cmp r3, #0 800294c: d101 bne.n 8002952 { return HAL_ERROR; 800294e: 2301 movs r3, #1 8002950: e054 b.n 80029fc } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 8002952: 687b ldr r3, [r7, #4] 8002954: 7f5b ldrb r3, [r3, #29] 8002956: b2db uxtb r3, r3 8002958: 2b00 cmp r3, #0 800295a: d105 bne.n 8002968 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 800295c: 687b ldr r3, [r7, #4] 800295e: 2200 movs r2, #0 8002960: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 8002962: 6878 ldr r0, [r7, #4] 8002964: f7fe fd8c bl 8001480 } hcrc->State = HAL_CRC_STATE_BUSY; 8002968: 687b ldr r3, [r7, #4] 800296a: 2202 movs r2, #2 800296c: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 800296e: 687b ldr r3, [r7, #4] 8002970: 791b ldrb r3, [r3, #4] 8002972: 2b00 cmp r3, #0 8002974: d10c bne.n 8002990 { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 8002976: 687b ldr r3, [r7, #4] 8002978: 681b ldr r3, [r3, #0] 800297a: 4a22 ldr r2, [pc, #136] @ (8002a04 ) 800297c: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 800297e: 687b ldr r3, [r7, #4] 8002980: 681b ldr r3, [r3, #0] 8002982: 689a ldr r2, [r3, #8] 8002984: 687b ldr r3, [r7, #4] 8002986: 681b ldr r3, [r3, #0] 8002988: f022 0218 bic.w r2, r2, #24 800298c: 609a str r2, [r3, #8] 800298e: e00c b.n 80029aa } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 8002990: 687b ldr r3, [r7, #4] 8002992: 6899 ldr r1, [r3, #8] 8002994: 687b ldr r3, [r7, #4] 8002996: 68db ldr r3, [r3, #12] 8002998: 461a mov r2, r3 800299a: 6878 ldr r0, [r7, #4] 800299c: f000 f948 bl 8002c30 80029a0: 4603 mov r3, r0 80029a2: 2b00 cmp r3, #0 80029a4: d001 beq.n 80029aa { return HAL_ERROR; 80029a6: 2301 movs r3, #1 80029a8: e028 b.n 80029fc } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 80029aa: 687b ldr r3, [r7, #4] 80029ac: 795b ldrb r3, [r3, #5] 80029ae: 2b00 cmp r3, #0 80029b0: d105 bne.n 80029be { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 80029b2: 687b ldr r3, [r7, #4] 80029b4: 681b ldr r3, [r3, #0] 80029b6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80029ba: 611a str r2, [r3, #16] 80029bc: e004 b.n 80029c8 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 80029be: 687b ldr r3, [r7, #4] 80029c0: 681b ldr r3, [r3, #0] 80029c2: 687a ldr r2, [r7, #4] 80029c4: 6912 ldr r2, [r2, #16] 80029c6: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 80029c8: 687b ldr r3, [r7, #4] 80029ca: 681b ldr r3, [r3, #0] 80029cc: 689b ldr r3, [r3, #8] 80029ce: f023 0160 bic.w r1, r3, #96 @ 0x60 80029d2: 687b ldr r3, [r7, #4] 80029d4: 695a ldr r2, [r3, #20] 80029d6: 687b ldr r3, [r7, #4] 80029d8: 681b ldr r3, [r3, #0] 80029da: 430a orrs r2, r1 80029dc: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 80029de: 687b ldr r3, [r7, #4] 80029e0: 681b ldr r3, [r3, #0] 80029e2: 689b ldr r3, [r3, #8] 80029e4: f023 0180 bic.w r1, r3, #128 @ 0x80 80029e8: 687b ldr r3, [r7, #4] 80029ea: 699a ldr r2, [r3, #24] 80029ec: 687b ldr r3, [r7, #4] 80029ee: 681b ldr r3, [r3, #0] 80029f0: 430a orrs r2, r1 80029f2: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 80029f4: 687b ldr r3, [r7, #4] 80029f6: 2201 movs r2, #1 80029f8: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 80029fa: 2300 movs r3, #0 } 80029fc: 4618 mov r0, r3 80029fe: 3708 adds r7, #8 8002a00: 46bd mov sp, r7 8002a02: bd80 pop {r7, pc} 8002a04: 04c11db7 .word 0x04c11db7 08002a08 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 8002a08: b580 push {r7, lr} 8002a0a: b086 sub sp, #24 8002a0c: af00 add r7, sp, #0 8002a0e: 60f8 str r0, [r7, #12] 8002a10: 60b9 str r1, [r7, #8] 8002a12: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 8002a14: 2300 movs r3, #0 8002a16: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 8002a18: 68fb ldr r3, [r7, #12] 8002a1a: 2202 movs r2, #2 8002a1c: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 8002a1e: 68fb ldr r3, [r7, #12] 8002a20: 681b ldr r3, [r3, #0] 8002a22: 689a ldr r2, [r3, #8] 8002a24: 68fb ldr r3, [r7, #12] 8002a26: 681b ldr r3, [r3, #0] 8002a28: f042 0201 orr.w r2, r2, #1 8002a2c: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 8002a2e: 68fb ldr r3, [r7, #12] 8002a30: 6a1b ldr r3, [r3, #32] 8002a32: 2b03 cmp r3, #3 8002a34: d006 beq.n 8002a44 8002a36: 2b03 cmp r3, #3 8002a38: d829 bhi.n 8002a8e 8002a3a: 2b01 cmp r3, #1 8002a3c: d019 beq.n 8002a72 8002a3e: 2b02 cmp r3, #2 8002a40: d01e beq.n 8002a80 /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 8002a42: e024 b.n 8002a8e for (index = 0U; index < BufferLength; index++) 8002a44: 2300 movs r3, #0 8002a46: 617b str r3, [r7, #20] 8002a48: e00a b.n 8002a60 hcrc->Instance->DR = pBuffer[index]; 8002a4a: 697b ldr r3, [r7, #20] 8002a4c: 009b lsls r3, r3, #2 8002a4e: 68ba ldr r2, [r7, #8] 8002a50: 441a add r2, r3 8002a52: 68fb ldr r3, [r7, #12] 8002a54: 681b ldr r3, [r3, #0] 8002a56: 6812 ldr r2, [r2, #0] 8002a58: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 8002a5a: 697b ldr r3, [r7, #20] 8002a5c: 3301 adds r3, #1 8002a5e: 617b str r3, [r7, #20] 8002a60: 697a ldr r2, [r7, #20] 8002a62: 687b ldr r3, [r7, #4] 8002a64: 429a cmp r2, r3 8002a66: d3f0 bcc.n 8002a4a temp = hcrc->Instance->DR; 8002a68: 68fb ldr r3, [r7, #12] 8002a6a: 681b ldr r3, [r3, #0] 8002a6c: 681b ldr r3, [r3, #0] 8002a6e: 613b str r3, [r7, #16] break; 8002a70: e00e b.n 8002a90 temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 8002a72: 687a ldr r2, [r7, #4] 8002a74: 68b9 ldr r1, [r7, #8] 8002a76: 68f8 ldr r0, [r7, #12] 8002a78: f000 f812 bl 8002aa0 8002a7c: 6138 str r0, [r7, #16] break; 8002a7e: e007 b.n 8002a90 temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 8002a80: 687a ldr r2, [r7, #4] 8002a82: 68b9 ldr r1, [r7, #8] 8002a84: 68f8 ldr r0, [r7, #12] 8002a86: f000 f899 bl 8002bbc 8002a8a: 6138 str r0, [r7, #16] break; 8002a8c: e000 b.n 8002a90 break; 8002a8e: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8002a90: 68fb ldr r3, [r7, #12] 8002a92: 2201 movs r2, #1 8002a94: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 8002a96: 693b ldr r3, [r7, #16] } 8002a98: 4618 mov r0, r3 8002a9a: 3718 adds r7, #24 8002a9c: 46bd mov sp, r7 8002a9e: bd80 pop {r7, pc} 08002aa0 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 8002aa0: b480 push {r7} 8002aa2: b089 sub sp, #36 @ 0x24 8002aa4: af00 add r7, sp, #0 8002aa6: 60f8 str r0, [r7, #12] 8002aa8: 60b9 str r1, [r7, #8] 8002aaa: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 8002aac: 2300 movs r3, #0 8002aae: 61fb str r3, [r7, #28] 8002ab0: e023 b.n 8002afa { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8002ab2: 69fb ldr r3, [r7, #28] 8002ab4: 009b lsls r3, r3, #2 8002ab6: 68ba ldr r2, [r7, #8] 8002ab8: 4413 add r3, r2 8002aba: 781b ldrb r3, [r3, #0] 8002abc: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8002abe: 69fb ldr r3, [r7, #28] 8002ac0: 009b lsls r3, r3, #2 8002ac2: 3301 adds r3, #1 8002ac4: 68b9 ldr r1, [r7, #8] 8002ac6: 440b add r3, r1 8002ac8: 781b ldrb r3, [r3, #0] 8002aca: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8002acc: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8002ace: 69fb ldr r3, [r7, #28] 8002ad0: 009b lsls r3, r3, #2 8002ad2: 3302 adds r3, #2 8002ad4: 68b9 ldr r1, [r7, #8] 8002ad6: 440b add r3, r1 8002ad8: 781b ldrb r3, [r3, #0] 8002ada: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8002adc: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 8002ade: 69fb ldr r3, [r7, #28] 8002ae0: 009b lsls r3, r3, #2 8002ae2: 3303 adds r3, #3 8002ae4: 68b9 ldr r1, [r7, #8] 8002ae6: 440b add r3, r1 8002ae8: 781b ldrb r3, [r3, #0] 8002aea: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8002aec: 68fb ldr r3, [r7, #12] 8002aee: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8002af0: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8002af2: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8002af4: 69fb ldr r3, [r7, #28] 8002af6: 3301 adds r3, #1 8002af8: 61fb str r3, [r7, #28] 8002afa: 687b ldr r3, [r7, #4] 8002afc: 089b lsrs r3, r3, #2 8002afe: 69fa ldr r2, [r7, #28] 8002b00: 429a cmp r2, r3 8002b02: d3d6 bcc.n 8002ab2 } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 8002b04: 687b ldr r3, [r7, #4] 8002b06: f003 0303 and.w r3, r3, #3 8002b0a: 2b00 cmp r3, #0 8002b0c: d04d beq.n 8002baa { if ((BufferLength % 4U) == 1U) 8002b0e: 687b ldr r3, [r7, #4] 8002b10: f003 0303 and.w r3, r3, #3 8002b14: 2b01 cmp r3, #1 8002b16: d107 bne.n 8002b28 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 8002b18: 69fb ldr r3, [r7, #28] 8002b1a: 009b lsls r3, r3, #2 8002b1c: 68ba ldr r2, [r7, #8] 8002b1e: 4413 add r3, r2 8002b20: 68fa ldr r2, [r7, #12] 8002b22: 6812 ldr r2, [r2, #0] 8002b24: 781b ldrb r3, [r3, #0] 8002b26: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 8002b28: 687b ldr r3, [r7, #4] 8002b2a: f003 0303 and.w r3, r3, #3 8002b2e: 2b02 cmp r3, #2 8002b30: d116 bne.n 8002b60 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8002b32: 69fb ldr r3, [r7, #28] 8002b34: 009b lsls r3, r3, #2 8002b36: 68ba ldr r2, [r7, #8] 8002b38: 4413 add r3, r2 8002b3a: 781b ldrb r3, [r3, #0] 8002b3c: 021b lsls r3, r3, #8 8002b3e: b21a sxth r2, r3 8002b40: 69fb ldr r3, [r7, #28] 8002b42: 009b lsls r3, r3, #2 8002b44: 3301 adds r3, #1 8002b46: 68b9 ldr r1, [r7, #8] 8002b48: 440b add r3, r1 8002b4a: 781b ldrb r3, [r3, #0] 8002b4c: b21b sxth r3, r3 8002b4e: 4313 orrs r3, r2 8002b50: b21b sxth r3, r3 8002b52: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8002b54: 68fb ldr r3, [r7, #12] 8002b56: 681b ldr r3, [r3, #0] 8002b58: 617b str r3, [r7, #20] *pReg = data; 8002b5a: 697b ldr r3, [r7, #20] 8002b5c: 8b7a ldrh r2, [r7, #26] 8002b5e: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 8002b60: 687b ldr r3, [r7, #4] 8002b62: f003 0303 and.w r3, r3, #3 8002b66: 2b03 cmp r3, #3 8002b68: d11f bne.n 8002baa { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8002b6a: 69fb ldr r3, [r7, #28] 8002b6c: 009b lsls r3, r3, #2 8002b6e: 68ba ldr r2, [r7, #8] 8002b70: 4413 add r3, r2 8002b72: 781b ldrb r3, [r3, #0] 8002b74: 021b lsls r3, r3, #8 8002b76: b21a sxth r2, r3 8002b78: 69fb ldr r3, [r7, #28] 8002b7a: 009b lsls r3, r3, #2 8002b7c: 3301 adds r3, #1 8002b7e: 68b9 ldr r1, [r7, #8] 8002b80: 440b add r3, r1 8002b82: 781b ldrb r3, [r3, #0] 8002b84: b21b sxth r3, r3 8002b86: 4313 orrs r3, r2 8002b88: b21b sxth r3, r3 8002b8a: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8002b8c: 68fb ldr r3, [r7, #12] 8002b8e: 681b ldr r3, [r3, #0] 8002b90: 617b str r3, [r7, #20] *pReg = data; 8002b92: 697b ldr r3, [r7, #20] 8002b94: 8b7a ldrh r2, [r7, #26] 8002b96: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 8002b98: 69fb ldr r3, [r7, #28] 8002b9a: 009b lsls r3, r3, #2 8002b9c: 3302 adds r3, #2 8002b9e: 68ba ldr r2, [r7, #8] 8002ba0: 4413 add r3, r2 8002ba2: 68fa ldr r2, [r7, #12] 8002ba4: 6812 ldr r2, [r2, #0] 8002ba6: 781b ldrb r3, [r3, #0] 8002ba8: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 8002baa: 68fb ldr r3, [r7, #12] 8002bac: 681b ldr r3, [r3, #0] 8002bae: 681b ldr r3, [r3, #0] } 8002bb0: 4618 mov r0, r3 8002bb2: 3724 adds r7, #36 @ 0x24 8002bb4: 46bd mov sp, r7 8002bb6: f85d 7b04 ldr.w r7, [sp], #4 8002bba: 4770 bx lr 08002bbc : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 8002bbc: b480 push {r7} 8002bbe: b087 sub sp, #28 8002bc0: af00 add r7, sp, #0 8002bc2: 60f8 str r0, [r7, #12] 8002bc4: 60b9 str r1, [r7, #8] 8002bc6: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8002bc8: 2300 movs r3, #0 8002bca: 617b str r3, [r7, #20] 8002bcc: e013 b.n 8002bf6 { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 8002bce: 697b ldr r3, [r7, #20] 8002bd0: 009b lsls r3, r3, #2 8002bd2: 68ba ldr r2, [r7, #8] 8002bd4: 4413 add r3, r2 8002bd6: 881b ldrh r3, [r3, #0] 8002bd8: 041a lsls r2, r3, #16 8002bda: 697b ldr r3, [r7, #20] 8002bdc: 009b lsls r3, r3, #2 8002bde: 3302 adds r3, #2 8002be0: 68b9 ldr r1, [r7, #8] 8002be2: 440b add r3, r1 8002be4: 881b ldrh r3, [r3, #0] 8002be6: 4619 mov r1, r3 8002be8: 68fb ldr r3, [r7, #12] 8002bea: 681b ldr r3, [r3, #0] 8002bec: 430a orrs r2, r1 8002bee: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 8002bf0: 697b ldr r3, [r7, #20] 8002bf2: 3301 adds r3, #1 8002bf4: 617b str r3, [r7, #20] 8002bf6: 687b ldr r3, [r7, #4] 8002bf8: 085b lsrs r3, r3, #1 8002bfa: 697a ldr r2, [r7, #20] 8002bfc: 429a cmp r2, r3 8002bfe: d3e6 bcc.n 8002bce } if ((BufferLength % 2U) != 0U) 8002c00: 687b ldr r3, [r7, #4] 8002c02: f003 0301 and.w r3, r3, #1 8002c06: 2b00 cmp r3, #0 8002c08: d009 beq.n 8002c1e { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8002c0a: 68fb ldr r3, [r7, #12] 8002c0c: 681b ldr r3, [r3, #0] 8002c0e: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 8002c10: 697b ldr r3, [r7, #20] 8002c12: 009b lsls r3, r3, #2 8002c14: 68ba ldr r2, [r7, #8] 8002c16: 4413 add r3, r2 8002c18: 881a ldrh r2, [r3, #0] 8002c1a: 693b ldr r3, [r7, #16] 8002c1c: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 8002c1e: 68fb ldr r3, [r7, #12] 8002c20: 681b ldr r3, [r3, #0] 8002c22: 681b ldr r3, [r3, #0] } 8002c24: 4618 mov r0, r3 8002c26: 371c adds r7, #28 8002c28: 46bd mov sp, r7 8002c2a: f85d 7b04 ldr.w r7, [sp], #4 8002c2e: 4770 bx lr 08002c30 : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 8002c30: b480 push {r7} 8002c32: b087 sub sp, #28 8002c34: af00 add r7, sp, #0 8002c36: 60f8 str r0, [r7, #12] 8002c38: 60b9 str r1, [r7, #8] 8002c3a: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8002c3c: 2300 movs r3, #0 8002c3e: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 8002c40: 231f movs r3, #31 8002c42: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 8002c44: 68bb ldr r3, [r7, #8] 8002c46: f003 0301 and.w r3, r3, #1 8002c4a: 2b00 cmp r3, #0 8002c4c: d102 bne.n 8002c54 { status = HAL_ERROR; 8002c4e: 2301 movs r3, #1 8002c50: 75fb strb r3, [r7, #23] 8002c52: e063 b.n 8002d1c * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 8002c54: bf00 nop 8002c56: 693b ldr r3, [r7, #16] 8002c58: 1e5a subs r2, r3, #1 8002c5a: 613a str r2, [r7, #16] 8002c5c: 2b00 cmp r3, #0 8002c5e: d009 beq.n 8002c74 8002c60: 693b ldr r3, [r7, #16] 8002c62: f003 031f and.w r3, r3, #31 8002c66: 68ba ldr r2, [r7, #8] 8002c68: fa22 f303 lsr.w r3, r2, r3 8002c6c: f003 0301 and.w r3, r3, #1 8002c70: 2b00 cmp r3, #0 8002c72: d0f0 beq.n 8002c56 { } switch (PolyLength) 8002c74: 687b ldr r3, [r7, #4] 8002c76: 2b18 cmp r3, #24 8002c78: d846 bhi.n 8002d08 8002c7a: a201 add r2, pc, #4 @ (adr r2, 8002c80 ) 8002c7c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8002c80: 08002d0f .word 0x08002d0f 8002c84: 08002d09 .word 0x08002d09 8002c88: 08002d09 .word 0x08002d09 8002c8c: 08002d09 .word 0x08002d09 8002c90: 08002d09 .word 0x08002d09 8002c94: 08002d09 .word 0x08002d09 8002c98: 08002d09 .word 0x08002d09 8002c9c: 08002d09 .word 0x08002d09 8002ca0: 08002cfd .word 0x08002cfd 8002ca4: 08002d09 .word 0x08002d09 8002ca8: 08002d09 .word 0x08002d09 8002cac: 08002d09 .word 0x08002d09 8002cb0: 08002d09 .word 0x08002d09 8002cb4: 08002d09 .word 0x08002d09 8002cb8: 08002d09 .word 0x08002d09 8002cbc: 08002d09 .word 0x08002d09 8002cc0: 08002cf1 .word 0x08002cf1 8002cc4: 08002d09 .word 0x08002d09 8002cc8: 08002d09 .word 0x08002d09 8002ccc: 08002d09 .word 0x08002d09 8002cd0: 08002d09 .word 0x08002d09 8002cd4: 08002d09 .word 0x08002d09 8002cd8: 08002d09 .word 0x08002d09 8002cdc: 08002d09 .word 0x08002d09 8002ce0: 08002ce5 .word 0x08002ce5 { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 8002ce4: 693b ldr r3, [r7, #16] 8002ce6: 2b06 cmp r3, #6 8002ce8: d913 bls.n 8002d12 { status = HAL_ERROR; 8002cea: 2301 movs r3, #1 8002cec: 75fb strb r3, [r7, #23] } break; 8002cee: e010 b.n 8002d12 case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 8002cf0: 693b ldr r3, [r7, #16] 8002cf2: 2b07 cmp r3, #7 8002cf4: d90f bls.n 8002d16 { status = HAL_ERROR; 8002cf6: 2301 movs r3, #1 8002cf8: 75fb strb r3, [r7, #23] } break; 8002cfa: e00c b.n 8002d16 case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 8002cfc: 693b ldr r3, [r7, #16] 8002cfe: 2b0f cmp r3, #15 8002d00: d90b bls.n 8002d1a { status = HAL_ERROR; 8002d02: 2301 movs r3, #1 8002d04: 75fb strb r3, [r7, #23] } break; 8002d06: e008 b.n 8002d1a case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 8002d08: 2301 movs r3, #1 8002d0a: 75fb strb r3, [r7, #23] break; 8002d0c: e006 b.n 8002d1c break; 8002d0e: bf00 nop 8002d10: e004 b.n 8002d1c break; 8002d12: bf00 nop 8002d14: e002 b.n 8002d1c break; 8002d16: bf00 nop 8002d18: e000 b.n 8002d1c break; 8002d1a: bf00 nop } } if (status == HAL_OK) 8002d1c: 7dfb ldrb r3, [r7, #23] 8002d1e: 2b00 cmp r3, #0 8002d20: d10d bne.n 8002d3e { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 8002d22: 68fb ldr r3, [r7, #12] 8002d24: 681b ldr r3, [r3, #0] 8002d26: 68ba ldr r2, [r7, #8] 8002d28: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 8002d2a: 68fb ldr r3, [r7, #12] 8002d2c: 681b ldr r3, [r3, #0] 8002d2e: 689b ldr r3, [r3, #8] 8002d30: f023 0118 bic.w r1, r3, #24 8002d34: 68fb ldr r3, [r7, #12] 8002d36: 681b ldr r3, [r3, #0] 8002d38: 687a ldr r2, [r7, #4] 8002d3a: 430a orrs r2, r1 8002d3c: 609a str r2, [r3, #8] } /* Return function status */ return status; 8002d3e: 7dfb ldrb r3, [r7, #23] } 8002d40: 4618 mov r0, r3 8002d42: 371c adds r7, #28 8002d44: 46bd mov sp, r7 8002d46: f85d 7b04 ldr.w r7, [sp], #4 8002d4a: 4770 bx lr 08002d4c : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8002d4c: b580 push {r7, lr} 8002d4e: b086 sub sp, #24 8002d50: af00 add r7, sp, #0 8002d52: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 8002d54: f7ff fc84 bl 8002660 8002d58: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8002d5a: 687b ldr r3, [r7, #4] 8002d5c: 2b00 cmp r3, #0 8002d5e: d101 bne.n 8002d64 { return HAL_ERROR; 8002d60: 2301 movs r3, #1 8002d62: e316 b.n 8003392 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8002d64: 687b ldr r3, [r7, #4] 8002d66: 681b ldr r3, [r3, #0] 8002d68: 4a66 ldr r2, [pc, #408] @ (8002f04 ) 8002d6a: 4293 cmp r3, r2 8002d6c: d04a beq.n 8002e04 8002d6e: 687b ldr r3, [r7, #4] 8002d70: 681b ldr r3, [r3, #0] 8002d72: 4a65 ldr r2, [pc, #404] @ (8002f08 ) 8002d74: 4293 cmp r3, r2 8002d76: d045 beq.n 8002e04 8002d78: 687b ldr r3, [r7, #4] 8002d7a: 681b ldr r3, [r3, #0] 8002d7c: 4a63 ldr r2, [pc, #396] @ (8002f0c ) 8002d7e: 4293 cmp r3, r2 8002d80: d040 beq.n 8002e04 8002d82: 687b ldr r3, [r7, #4] 8002d84: 681b ldr r3, [r3, #0] 8002d86: 4a62 ldr r2, [pc, #392] @ (8002f10 ) 8002d88: 4293 cmp r3, r2 8002d8a: d03b beq.n 8002e04 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 681b ldr r3, [r3, #0] 8002d90: 4a60 ldr r2, [pc, #384] @ (8002f14 ) 8002d92: 4293 cmp r3, r2 8002d94: d036 beq.n 8002e04 8002d96: 687b ldr r3, [r7, #4] 8002d98: 681b ldr r3, [r3, #0] 8002d9a: 4a5f ldr r2, [pc, #380] @ (8002f18 ) 8002d9c: 4293 cmp r3, r2 8002d9e: d031 beq.n 8002e04 8002da0: 687b ldr r3, [r7, #4] 8002da2: 681b ldr r3, [r3, #0] 8002da4: 4a5d ldr r2, [pc, #372] @ (8002f1c ) 8002da6: 4293 cmp r3, r2 8002da8: d02c beq.n 8002e04 8002daa: 687b ldr r3, [r7, #4] 8002dac: 681b ldr r3, [r3, #0] 8002dae: 4a5c ldr r2, [pc, #368] @ (8002f20 ) 8002db0: 4293 cmp r3, r2 8002db2: d027 beq.n 8002e04 8002db4: 687b ldr r3, [r7, #4] 8002db6: 681b ldr r3, [r3, #0] 8002db8: 4a5a ldr r2, [pc, #360] @ (8002f24 ) 8002dba: 4293 cmp r3, r2 8002dbc: d022 beq.n 8002e04 8002dbe: 687b ldr r3, [r7, #4] 8002dc0: 681b ldr r3, [r3, #0] 8002dc2: 4a59 ldr r2, [pc, #356] @ (8002f28 ) 8002dc4: 4293 cmp r3, r2 8002dc6: d01d beq.n 8002e04 8002dc8: 687b ldr r3, [r7, #4] 8002dca: 681b ldr r3, [r3, #0] 8002dcc: 4a57 ldr r2, [pc, #348] @ (8002f2c ) 8002dce: 4293 cmp r3, r2 8002dd0: d018 beq.n 8002e04 8002dd2: 687b ldr r3, [r7, #4] 8002dd4: 681b ldr r3, [r3, #0] 8002dd6: 4a56 ldr r2, [pc, #344] @ (8002f30 ) 8002dd8: 4293 cmp r3, r2 8002dda: d013 beq.n 8002e04 8002ddc: 687b ldr r3, [r7, #4] 8002dde: 681b ldr r3, [r3, #0] 8002de0: 4a54 ldr r2, [pc, #336] @ (8002f34 ) 8002de2: 4293 cmp r3, r2 8002de4: d00e beq.n 8002e04 8002de6: 687b ldr r3, [r7, #4] 8002de8: 681b ldr r3, [r3, #0] 8002dea: 4a53 ldr r2, [pc, #332] @ (8002f38 ) 8002dec: 4293 cmp r3, r2 8002dee: d009 beq.n 8002e04 8002df0: 687b ldr r3, [r7, #4] 8002df2: 681b ldr r3, [r3, #0] 8002df4: 4a51 ldr r2, [pc, #324] @ (8002f3c ) 8002df6: 4293 cmp r3, r2 8002df8: d004 beq.n 8002e04 8002dfa: 687b ldr r3, [r7, #4] 8002dfc: 681b ldr r3, [r3, #0] 8002dfe: 4a50 ldr r2, [pc, #320] @ (8002f40 ) 8002e00: 4293 cmp r3, r2 8002e02: d101 bne.n 8002e08 8002e04: 2301 movs r3, #1 8002e06: e000 b.n 8002e0a 8002e08: 2300 movs r3, #0 8002e0a: 2b00 cmp r3, #0 8002e0c: f000 813b beq.w 8003086 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8002e10: 687b ldr r3, [r7, #4] 8002e12: 2202 movs r2, #2 8002e14: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8002e18: 687b ldr r3, [r7, #4] 8002e1a: 2200 movs r2, #0 8002e1c: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8002e20: 687b ldr r3, [r7, #4] 8002e22: 681b ldr r3, [r3, #0] 8002e24: 4a37 ldr r2, [pc, #220] @ (8002f04 ) 8002e26: 4293 cmp r3, r2 8002e28: d04a beq.n 8002ec0 8002e2a: 687b ldr r3, [r7, #4] 8002e2c: 681b ldr r3, [r3, #0] 8002e2e: 4a36 ldr r2, [pc, #216] @ (8002f08 ) 8002e30: 4293 cmp r3, r2 8002e32: d045 beq.n 8002ec0 8002e34: 687b ldr r3, [r7, #4] 8002e36: 681b ldr r3, [r3, #0] 8002e38: 4a34 ldr r2, [pc, #208] @ (8002f0c ) 8002e3a: 4293 cmp r3, r2 8002e3c: d040 beq.n 8002ec0 8002e3e: 687b ldr r3, [r7, #4] 8002e40: 681b ldr r3, [r3, #0] 8002e42: 4a33 ldr r2, [pc, #204] @ (8002f10 ) 8002e44: 4293 cmp r3, r2 8002e46: d03b beq.n 8002ec0 8002e48: 687b ldr r3, [r7, #4] 8002e4a: 681b ldr r3, [r3, #0] 8002e4c: 4a31 ldr r2, [pc, #196] @ (8002f14 ) 8002e4e: 4293 cmp r3, r2 8002e50: d036 beq.n 8002ec0 8002e52: 687b ldr r3, [r7, #4] 8002e54: 681b ldr r3, [r3, #0] 8002e56: 4a30 ldr r2, [pc, #192] @ (8002f18 ) 8002e58: 4293 cmp r3, r2 8002e5a: d031 beq.n 8002ec0 8002e5c: 687b ldr r3, [r7, #4] 8002e5e: 681b ldr r3, [r3, #0] 8002e60: 4a2e ldr r2, [pc, #184] @ (8002f1c ) 8002e62: 4293 cmp r3, r2 8002e64: d02c beq.n 8002ec0 8002e66: 687b ldr r3, [r7, #4] 8002e68: 681b ldr r3, [r3, #0] 8002e6a: 4a2d ldr r2, [pc, #180] @ (8002f20 ) 8002e6c: 4293 cmp r3, r2 8002e6e: d027 beq.n 8002ec0 8002e70: 687b ldr r3, [r7, #4] 8002e72: 681b ldr r3, [r3, #0] 8002e74: 4a2b ldr r2, [pc, #172] @ (8002f24 ) 8002e76: 4293 cmp r3, r2 8002e78: d022 beq.n 8002ec0 8002e7a: 687b ldr r3, [r7, #4] 8002e7c: 681b ldr r3, [r3, #0] 8002e7e: 4a2a ldr r2, [pc, #168] @ (8002f28 ) 8002e80: 4293 cmp r3, r2 8002e82: d01d beq.n 8002ec0 8002e84: 687b ldr r3, [r7, #4] 8002e86: 681b ldr r3, [r3, #0] 8002e88: 4a28 ldr r2, [pc, #160] @ (8002f2c ) 8002e8a: 4293 cmp r3, r2 8002e8c: d018 beq.n 8002ec0 8002e8e: 687b ldr r3, [r7, #4] 8002e90: 681b ldr r3, [r3, #0] 8002e92: 4a27 ldr r2, [pc, #156] @ (8002f30 ) 8002e94: 4293 cmp r3, r2 8002e96: d013 beq.n 8002ec0 8002e98: 687b ldr r3, [r7, #4] 8002e9a: 681b ldr r3, [r3, #0] 8002e9c: 4a25 ldr r2, [pc, #148] @ (8002f34 ) 8002e9e: 4293 cmp r3, r2 8002ea0: d00e beq.n 8002ec0 8002ea2: 687b ldr r3, [r7, #4] 8002ea4: 681b ldr r3, [r3, #0] 8002ea6: 4a24 ldr r2, [pc, #144] @ (8002f38 ) 8002ea8: 4293 cmp r3, r2 8002eaa: d009 beq.n 8002ec0 8002eac: 687b ldr r3, [r7, #4] 8002eae: 681b ldr r3, [r3, #0] 8002eb0: 4a22 ldr r2, [pc, #136] @ (8002f3c ) 8002eb2: 4293 cmp r3, r2 8002eb4: d004 beq.n 8002ec0 8002eb6: 687b ldr r3, [r7, #4] 8002eb8: 681b ldr r3, [r3, #0] 8002eba: 4a21 ldr r2, [pc, #132] @ (8002f40 ) 8002ebc: 4293 cmp r3, r2 8002ebe: d108 bne.n 8002ed2 8002ec0: 687b ldr r3, [r7, #4] 8002ec2: 681b ldr r3, [r3, #0] 8002ec4: 681a ldr r2, [r3, #0] 8002ec6: 687b ldr r3, [r7, #4] 8002ec8: 681b ldr r3, [r3, #0] 8002eca: f022 0201 bic.w r2, r2, #1 8002ece: 601a str r2, [r3, #0] 8002ed0: e007 b.n 8002ee2 8002ed2: 687b ldr r3, [r7, #4] 8002ed4: 681b ldr r3, [r3, #0] 8002ed6: 681a ldr r2, [r3, #0] 8002ed8: 687b ldr r3, [r7, #4] 8002eda: 681b ldr r3, [r3, #0] 8002edc: f022 0201 bic.w r2, r2, #1 8002ee0: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8002ee2: e02f b.n 8002f44 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8002ee4: f7ff fbbc bl 8002660 8002ee8: 4602 mov r2, r0 8002eea: 693b ldr r3, [r7, #16] 8002eec: 1ad3 subs r3, r2, r3 8002eee: 2b05 cmp r3, #5 8002ef0: d928 bls.n 8002f44 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8002ef2: 687b ldr r3, [r7, #4] 8002ef4: 2220 movs r2, #32 8002ef6: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8002ef8: 687b ldr r3, [r7, #4] 8002efa: 2203 movs r2, #3 8002efc: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8002f00: 2301 movs r3, #1 8002f02: e246 b.n 8003392 8002f04: 40020010 .word 0x40020010 8002f08: 40020028 .word 0x40020028 8002f0c: 40020040 .word 0x40020040 8002f10: 40020058 .word 0x40020058 8002f14: 40020070 .word 0x40020070 8002f18: 40020088 .word 0x40020088 8002f1c: 400200a0 .word 0x400200a0 8002f20: 400200b8 .word 0x400200b8 8002f24: 40020410 .word 0x40020410 8002f28: 40020428 .word 0x40020428 8002f2c: 40020440 .word 0x40020440 8002f30: 40020458 .word 0x40020458 8002f34: 40020470 .word 0x40020470 8002f38: 40020488 .word 0x40020488 8002f3c: 400204a0 .word 0x400204a0 8002f40: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8002f44: 687b ldr r3, [r7, #4] 8002f46: 681b ldr r3, [r3, #0] 8002f48: 681b ldr r3, [r3, #0] 8002f4a: f003 0301 and.w r3, r3, #1 8002f4e: 2b00 cmp r3, #0 8002f50: d1c8 bne.n 8002ee4 } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 8002f52: 687b ldr r3, [r7, #4] 8002f54: 681b ldr r3, [r3, #0] 8002f56: 681b ldr r3, [r3, #0] 8002f58: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8002f5a: 697a ldr r2, [r7, #20] 8002f5c: 4b83 ldr r3, [pc, #524] @ (800316c ) 8002f5e: 4013 ands r3, r2 8002f60: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 8002f62: 687b ldr r3, [r7, #4] 8002f64: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8002f66: 687b ldr r3, [r7, #4] 8002f68: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 8002f6a: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8002f6c: 687b ldr r3, [r7, #4] 8002f6e: 691b ldr r3, [r3, #16] 8002f70: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002f72: 687b ldr r3, [r7, #4] 8002f74: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8002f76: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002f78: 687b ldr r3, [r7, #4] 8002f7a: 699b ldr r3, [r3, #24] 8002f7c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8002f7e: 687b ldr r3, [r7, #4] 8002f80: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8002f82: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8002f84: 687b ldr r3, [r7, #4] 8002f86: 6a1b ldr r3, [r3, #32] 8002f88: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 8002f8a: 697a ldr r2, [r7, #20] 8002f8c: 4313 orrs r3, r2 8002f8e: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8002f90: 687b ldr r3, [r7, #4] 8002f92: 6a5b ldr r3, [r3, #36] @ 0x24 8002f94: 2b04 cmp r3, #4 8002f96: d107 bne.n 8002fa8 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8002f98: 687b ldr r3, [r7, #4] 8002f9a: 6ada ldr r2, [r3, #44] @ 0x2c 8002f9c: 687b ldr r3, [r7, #4] 8002f9e: 6b1b ldr r3, [r3, #48] @ 0x30 8002fa0: 4313 orrs r3, r2 8002fa2: 697a ldr r2, [r7, #20] 8002fa4: 4313 orrs r3, r2 8002fa6: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8002fa8: 4b71 ldr r3, [pc, #452] @ (8003170 ) 8002faa: 681a ldr r2, [r3, #0] 8002fac: 4b71 ldr r3, [pc, #452] @ (8003174 ) 8002fae: 4013 ands r3, r2 8002fb0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8002fb4: d328 bcc.n 8003008 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8002fb6: 687b ldr r3, [r7, #4] 8002fb8: 685b ldr r3, [r3, #4] 8002fba: 2b28 cmp r3, #40 @ 0x28 8002fbc: d903 bls.n 8002fc6 8002fbe: 687b ldr r3, [r7, #4] 8002fc0: 685b ldr r3, [r3, #4] 8002fc2: 2b2e cmp r3, #46 @ 0x2e 8002fc4: d917 bls.n 8002ff6 8002fc6: 687b ldr r3, [r7, #4] 8002fc8: 685b ldr r3, [r3, #4] 8002fca: 2b3e cmp r3, #62 @ 0x3e 8002fcc: d903 bls.n 8002fd6 8002fce: 687b ldr r3, [r7, #4] 8002fd0: 685b ldr r3, [r3, #4] 8002fd2: 2b42 cmp r3, #66 @ 0x42 8002fd4: d90f bls.n 8002ff6 8002fd6: 687b ldr r3, [r7, #4] 8002fd8: 685b ldr r3, [r3, #4] 8002fda: 2b46 cmp r3, #70 @ 0x46 8002fdc: d903 bls.n 8002fe6 8002fde: 687b ldr r3, [r7, #4] 8002fe0: 685b ldr r3, [r3, #4] 8002fe2: 2b48 cmp r3, #72 @ 0x48 8002fe4: d907 bls.n 8002ff6 8002fe6: 687b ldr r3, [r7, #4] 8002fe8: 685b ldr r3, [r3, #4] 8002fea: 2b4e cmp r3, #78 @ 0x4e 8002fec: d905 bls.n 8002ffa 8002fee: 687b ldr r3, [r7, #4] 8002ff0: 685b ldr r3, [r3, #4] 8002ff2: 2b52 cmp r3, #82 @ 0x52 8002ff4: d801 bhi.n 8002ffa 8002ff6: 2301 movs r3, #1 8002ff8: e000 b.n 8002ffc 8002ffa: 2300 movs r3, #0 8002ffc: 2b00 cmp r3, #0 8002ffe: d003 beq.n 8003008 { registerValue |= DMA_SxCR_TRBUFF; 8003000: 697b ldr r3, [r7, #20] 8003002: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8003006: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8003008: 687b ldr r3, [r7, #4] 800300a: 681b ldr r3, [r3, #0] 800300c: 697a ldr r2, [r7, #20] 800300e: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 8003010: 687b ldr r3, [r7, #4] 8003012: 681b ldr r3, [r3, #0] 8003014: 695b ldr r3, [r3, #20] 8003016: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8003018: 697b ldr r3, [r7, #20] 800301a: f023 0307 bic.w r3, r3, #7 800301e: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 8003020: 687b ldr r3, [r7, #4] 8003022: 6a5b ldr r3, [r3, #36] @ 0x24 8003024: 697a ldr r2, [r7, #20] 8003026: 4313 orrs r3, r2 8003028: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 800302a: 687b ldr r3, [r7, #4] 800302c: 6a5b ldr r3, [r3, #36] @ 0x24 800302e: 2b04 cmp r3, #4 8003030: d117 bne.n 8003062 { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 8003032: 687b ldr r3, [r7, #4] 8003034: 6a9b ldr r3, [r3, #40] @ 0x28 8003036: 697a ldr r2, [r7, #20] 8003038: 4313 orrs r3, r2 800303a: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 800303c: 687b ldr r3, [r7, #4] 800303e: 6adb ldr r3, [r3, #44] @ 0x2c 8003040: 2b00 cmp r3, #0 8003042: d00e beq.n 8003062 { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8003044: 6878 ldr r0, [r7, #4] 8003046: f001 ff1d bl 8004e84 800304a: 4603 mov r3, r0 800304c: 2b00 cmp r3, #0 800304e: d008 beq.n 8003062 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8003050: 687b ldr r3, [r7, #4] 8003052: 2240 movs r2, #64 @ 0x40 8003054: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003056: 687b ldr r3, [r7, #4] 8003058: 2201 movs r2, #1 800305a: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800305e: 2301 movs r3, #1 8003060: e197 b.n 8003392 } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 8003062: 687b ldr r3, [r7, #4] 8003064: 681b ldr r3, [r3, #0] 8003066: 697a ldr r2, [r7, #20] 8003068: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 800306a: 6878 ldr r0, [r7, #4] 800306c: f001 fe58 bl 8004d20 8003070: 4603 mov r3, r0 8003072: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8003074: 687b ldr r3, [r7, #4] 8003076: 6ddb ldr r3, [r3, #92] @ 0x5c 8003078: f003 031f and.w r3, r3, #31 800307c: 223f movs r2, #63 @ 0x3f 800307e: 409a lsls r2, r3 8003080: 68bb ldr r3, [r7, #8] 8003082: 609a str r2, [r3, #8] 8003084: e0cd b.n 8003222 } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8003086: 687b ldr r3, [r7, #4] 8003088: 681b ldr r3, [r3, #0] 800308a: 4a3b ldr r2, [pc, #236] @ (8003178 ) 800308c: 4293 cmp r3, r2 800308e: d022 beq.n 80030d6 8003090: 687b ldr r3, [r7, #4] 8003092: 681b ldr r3, [r3, #0] 8003094: 4a39 ldr r2, [pc, #228] @ (800317c ) 8003096: 4293 cmp r3, r2 8003098: d01d beq.n 80030d6 800309a: 687b ldr r3, [r7, #4] 800309c: 681b ldr r3, [r3, #0] 800309e: 4a38 ldr r2, [pc, #224] @ (8003180 ) 80030a0: 4293 cmp r3, r2 80030a2: d018 beq.n 80030d6 80030a4: 687b ldr r3, [r7, #4] 80030a6: 681b ldr r3, [r3, #0] 80030a8: 4a36 ldr r2, [pc, #216] @ (8003184 ) 80030aa: 4293 cmp r3, r2 80030ac: d013 beq.n 80030d6 80030ae: 687b ldr r3, [r7, #4] 80030b0: 681b ldr r3, [r3, #0] 80030b2: 4a35 ldr r2, [pc, #212] @ (8003188 ) 80030b4: 4293 cmp r3, r2 80030b6: d00e beq.n 80030d6 80030b8: 687b ldr r3, [r7, #4] 80030ba: 681b ldr r3, [r3, #0] 80030bc: 4a33 ldr r2, [pc, #204] @ (800318c ) 80030be: 4293 cmp r3, r2 80030c0: d009 beq.n 80030d6 80030c2: 687b ldr r3, [r7, #4] 80030c4: 681b ldr r3, [r3, #0] 80030c6: 4a32 ldr r2, [pc, #200] @ (8003190 ) 80030c8: 4293 cmp r3, r2 80030ca: d004 beq.n 80030d6 80030cc: 687b ldr r3, [r7, #4] 80030ce: 681b ldr r3, [r3, #0] 80030d0: 4a30 ldr r2, [pc, #192] @ (8003194 ) 80030d2: 4293 cmp r3, r2 80030d4: d101 bne.n 80030da 80030d6: 2301 movs r3, #1 80030d8: e000 b.n 80030dc 80030da: 2300 movs r3, #0 80030dc: 2b00 cmp r3, #0 80030de: f000 8097 beq.w 8003210 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80030e2: 687b ldr r3, [r7, #4] 80030e4: 681b ldr r3, [r3, #0] 80030e6: 4a24 ldr r2, [pc, #144] @ (8003178 ) 80030e8: 4293 cmp r3, r2 80030ea: d021 beq.n 8003130 80030ec: 687b ldr r3, [r7, #4] 80030ee: 681b ldr r3, [r3, #0] 80030f0: 4a22 ldr r2, [pc, #136] @ (800317c ) 80030f2: 4293 cmp r3, r2 80030f4: d01c beq.n 8003130 80030f6: 687b ldr r3, [r7, #4] 80030f8: 681b ldr r3, [r3, #0] 80030fa: 4a21 ldr r2, [pc, #132] @ (8003180 ) 80030fc: 4293 cmp r3, r2 80030fe: d017 beq.n 8003130 8003100: 687b ldr r3, [r7, #4] 8003102: 681b ldr r3, [r3, #0] 8003104: 4a1f ldr r2, [pc, #124] @ (8003184 ) 8003106: 4293 cmp r3, r2 8003108: d012 beq.n 8003130 800310a: 687b ldr r3, [r7, #4] 800310c: 681b ldr r3, [r3, #0] 800310e: 4a1e ldr r2, [pc, #120] @ (8003188 ) 8003110: 4293 cmp r3, r2 8003112: d00d beq.n 8003130 8003114: 687b ldr r3, [r7, #4] 8003116: 681b ldr r3, [r3, #0] 8003118: 4a1c ldr r2, [pc, #112] @ (800318c ) 800311a: 4293 cmp r3, r2 800311c: d008 beq.n 8003130 800311e: 687b ldr r3, [r7, #4] 8003120: 681b ldr r3, [r3, #0] 8003122: 4a1b ldr r2, [pc, #108] @ (8003190 ) 8003124: 4293 cmp r3, r2 8003126: d003 beq.n 8003130 8003128: 687b ldr r3, [r7, #4] 800312a: 681b ldr r3, [r3, #0] 800312c: 4a19 ldr r2, [pc, #100] @ (8003194 ) 800312e: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8003130: 687b ldr r3, [r7, #4] 8003132: 2202 movs r2, #2 8003134: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8003138: 687b ldr r3, [r7, #4] 800313a: 2200 movs r2, #0 800313c: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 8003140: 687b ldr r3, [r7, #4] 8003142: 681b ldr r3, [r3, #0] 8003144: 681b ldr r3, [r3, #0] 8003146: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8003148: 697a ldr r2, [r7, #20] 800314a: 4b13 ldr r3, [pc, #76] @ (8003198 ) 800314c: 4013 ands r3, r2 800314e: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8003150: 687b ldr r3, [r7, #4] 8003152: 689b ldr r3, [r3, #8] 8003154: 2b40 cmp r3, #64 @ 0x40 8003156: d021 beq.n 800319c 8003158: 687b ldr r3, [r7, #4] 800315a: 689b ldr r3, [r3, #8] 800315c: 2b80 cmp r3, #128 @ 0x80 800315e: d102 bne.n 8003166 8003160: f44f 4380 mov.w r3, #16384 @ 0x4000 8003164: e01b b.n 800319e 8003166: 2300 movs r3, #0 8003168: e019 b.n 800319e 800316a: bf00 nop 800316c: fe10803f .word 0xfe10803f 8003170: 5c001000 .word 0x5c001000 8003174: ffff0000 .word 0xffff0000 8003178: 58025408 .word 0x58025408 800317c: 5802541c .word 0x5802541c 8003180: 58025430 .word 0x58025430 8003184: 58025444 .word 0x58025444 8003188: 58025458 .word 0x58025458 800318c: 5802546c .word 0x5802546c 8003190: 58025480 .word 0x58025480 8003194: 58025494 .word 0x58025494 8003198: fffe000f .word 0xfffe000f 800319c: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 800319e: 687a ldr r2, [r7, #4] 80031a0: 68d2 ldr r2, [r2, #12] 80031a2: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80031a4: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80031a6: 687b ldr r3, [r7, #4] 80031a8: 691b ldr r3, [r3, #16] 80031aa: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 80031ac: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80031ae: 687b ldr r3, [r7, #4] 80031b0: 695b ldr r3, [r3, #20] 80031b2: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80031b4: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80031b6: 687b ldr r3, [r7, #4] 80031b8: 699b ldr r3, [r3, #24] 80031ba: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80031bc: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80031be: 687b ldr r3, [r7, #4] 80031c0: 69db ldr r3, [r3, #28] 80031c2: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80031c4: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 80031c6: 687b ldr r3, [r7, #4] 80031c8: 6a1b ldr r3, [r3, #32] 80031ca: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80031cc: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80031ce: 697a ldr r2, [r7, #20] 80031d0: 4313 orrs r3, r2 80031d2: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 80031d4: 687b ldr r3, [r7, #4] 80031d6: 681b ldr r3, [r3, #0] 80031d8: 697a ldr r2, [r7, #20] 80031da: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 80031dc: 687b ldr r3, [r7, #4] 80031de: 681b ldr r3, [r3, #0] 80031e0: 461a mov r2, r3 80031e2: 4b6e ldr r3, [pc, #440] @ (800339c ) 80031e4: 4413 add r3, r2 80031e6: 4a6e ldr r2, [pc, #440] @ (80033a0 ) 80031e8: fba2 2303 umull r2, r3, r2, r3 80031ec: 091b lsrs r3, r3, #4 80031ee: 009a lsls r2, r3, #2 80031f0: 687b ldr r3, [r7, #4] 80031f2: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 80031f4: 6878 ldr r0, [r7, #4] 80031f6: f001 fd93 bl 8004d20 80031fa: 4603 mov r3, r0 80031fc: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 80031fe: 687b ldr r3, [r7, #4] 8003200: 6ddb ldr r3, [r3, #92] @ 0x5c 8003202: f003 031f and.w r3, r3, #31 8003206: 2201 movs r2, #1 8003208: 409a lsls r2, r3 800320a: 68fb ldr r3, [r7, #12] 800320c: 605a str r2, [r3, #4] 800320e: e008 b.n 8003222 } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8003210: 687b ldr r3, [r7, #4] 8003212: 2240 movs r2, #64 @ 0x40 8003214: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8003216: 687b ldr r3, [r7, #4] 8003218: 2203 movs r2, #3 800321a: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800321e: 2301 movs r3, #1 8003220: e0b7 b.n 8003392 } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8003222: 687b ldr r3, [r7, #4] 8003224: 681b ldr r3, [r3, #0] 8003226: 4a5f ldr r2, [pc, #380] @ (80033a4 ) 8003228: 4293 cmp r3, r2 800322a: d072 beq.n 8003312 800322c: 687b ldr r3, [r7, #4] 800322e: 681b ldr r3, [r3, #0] 8003230: 4a5d ldr r2, [pc, #372] @ (80033a8 ) 8003232: 4293 cmp r3, r2 8003234: d06d beq.n 8003312 8003236: 687b ldr r3, [r7, #4] 8003238: 681b ldr r3, [r3, #0] 800323a: 4a5c ldr r2, [pc, #368] @ (80033ac ) 800323c: 4293 cmp r3, r2 800323e: d068 beq.n 8003312 8003240: 687b ldr r3, [r7, #4] 8003242: 681b ldr r3, [r3, #0] 8003244: 4a5a ldr r2, [pc, #360] @ (80033b0 ) 8003246: 4293 cmp r3, r2 8003248: d063 beq.n 8003312 800324a: 687b ldr r3, [r7, #4] 800324c: 681b ldr r3, [r3, #0] 800324e: 4a59 ldr r2, [pc, #356] @ (80033b4 ) 8003250: 4293 cmp r3, r2 8003252: d05e beq.n 8003312 8003254: 687b ldr r3, [r7, #4] 8003256: 681b ldr r3, [r3, #0] 8003258: 4a57 ldr r2, [pc, #348] @ (80033b8 ) 800325a: 4293 cmp r3, r2 800325c: d059 beq.n 8003312 800325e: 687b ldr r3, [r7, #4] 8003260: 681b ldr r3, [r3, #0] 8003262: 4a56 ldr r2, [pc, #344] @ (80033bc ) 8003264: 4293 cmp r3, r2 8003266: d054 beq.n 8003312 8003268: 687b ldr r3, [r7, #4] 800326a: 681b ldr r3, [r3, #0] 800326c: 4a54 ldr r2, [pc, #336] @ (80033c0 ) 800326e: 4293 cmp r3, r2 8003270: d04f beq.n 8003312 8003272: 687b ldr r3, [r7, #4] 8003274: 681b ldr r3, [r3, #0] 8003276: 4a53 ldr r2, [pc, #332] @ (80033c4 ) 8003278: 4293 cmp r3, r2 800327a: d04a beq.n 8003312 800327c: 687b ldr r3, [r7, #4] 800327e: 681b ldr r3, [r3, #0] 8003280: 4a51 ldr r2, [pc, #324] @ (80033c8 ) 8003282: 4293 cmp r3, r2 8003284: d045 beq.n 8003312 8003286: 687b ldr r3, [r7, #4] 8003288: 681b ldr r3, [r3, #0] 800328a: 4a50 ldr r2, [pc, #320] @ (80033cc ) 800328c: 4293 cmp r3, r2 800328e: d040 beq.n 8003312 8003290: 687b ldr r3, [r7, #4] 8003292: 681b ldr r3, [r3, #0] 8003294: 4a4e ldr r2, [pc, #312] @ (80033d0 ) 8003296: 4293 cmp r3, r2 8003298: d03b beq.n 8003312 800329a: 687b ldr r3, [r7, #4] 800329c: 681b ldr r3, [r3, #0] 800329e: 4a4d ldr r2, [pc, #308] @ (80033d4 ) 80032a0: 4293 cmp r3, r2 80032a2: d036 beq.n 8003312 80032a4: 687b ldr r3, [r7, #4] 80032a6: 681b ldr r3, [r3, #0] 80032a8: 4a4b ldr r2, [pc, #300] @ (80033d8 ) 80032aa: 4293 cmp r3, r2 80032ac: d031 beq.n 8003312 80032ae: 687b ldr r3, [r7, #4] 80032b0: 681b ldr r3, [r3, #0] 80032b2: 4a4a ldr r2, [pc, #296] @ (80033dc ) 80032b4: 4293 cmp r3, r2 80032b6: d02c beq.n 8003312 80032b8: 687b ldr r3, [r7, #4] 80032ba: 681b ldr r3, [r3, #0] 80032bc: 4a48 ldr r2, [pc, #288] @ (80033e0 ) 80032be: 4293 cmp r3, r2 80032c0: d027 beq.n 8003312 80032c2: 687b ldr r3, [r7, #4] 80032c4: 681b ldr r3, [r3, #0] 80032c6: 4a47 ldr r2, [pc, #284] @ (80033e4 ) 80032c8: 4293 cmp r3, r2 80032ca: d022 beq.n 8003312 80032cc: 687b ldr r3, [r7, #4] 80032ce: 681b ldr r3, [r3, #0] 80032d0: 4a45 ldr r2, [pc, #276] @ (80033e8 ) 80032d2: 4293 cmp r3, r2 80032d4: d01d beq.n 8003312 80032d6: 687b ldr r3, [r7, #4] 80032d8: 681b ldr r3, [r3, #0] 80032da: 4a44 ldr r2, [pc, #272] @ (80033ec ) 80032dc: 4293 cmp r3, r2 80032de: d018 beq.n 8003312 80032e0: 687b ldr r3, [r7, #4] 80032e2: 681b ldr r3, [r3, #0] 80032e4: 4a42 ldr r2, [pc, #264] @ (80033f0 ) 80032e6: 4293 cmp r3, r2 80032e8: d013 beq.n 8003312 80032ea: 687b ldr r3, [r7, #4] 80032ec: 681b ldr r3, [r3, #0] 80032ee: 4a41 ldr r2, [pc, #260] @ (80033f4 ) 80032f0: 4293 cmp r3, r2 80032f2: d00e beq.n 8003312 80032f4: 687b ldr r3, [r7, #4] 80032f6: 681b ldr r3, [r3, #0] 80032f8: 4a3f ldr r2, [pc, #252] @ (80033f8 ) 80032fa: 4293 cmp r3, r2 80032fc: d009 beq.n 8003312 80032fe: 687b ldr r3, [r7, #4] 8003300: 681b ldr r3, [r3, #0] 8003302: 4a3e ldr r2, [pc, #248] @ (80033fc ) 8003304: 4293 cmp r3, r2 8003306: d004 beq.n 8003312 8003308: 687b ldr r3, [r7, #4] 800330a: 681b ldr r3, [r3, #0] 800330c: 4a3c ldr r2, [pc, #240] @ (8003400 ) 800330e: 4293 cmp r3, r2 8003310: d101 bne.n 8003316 8003312: 2301 movs r3, #1 8003314: e000 b.n 8003318 8003316: 2300 movs r3, #0 8003318: 2b00 cmp r3, #0 800331a: d032 beq.n 8003382 { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 800331c: 6878 ldr r0, [r7, #4] 800331e: f001 fe2d bl 8004f7c if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8003322: 687b ldr r3, [r7, #4] 8003324: 689b ldr r3, [r3, #8] 8003326: 2b80 cmp r3, #128 @ 0x80 8003328: d102 bne.n 8003330 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 800332a: 687b ldr r3, [r7, #4] 800332c: 2200 movs r2, #0 800332e: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8003330: 687b ldr r3, [r7, #4] 8003332: 685a ldr r2, [r3, #4] 8003334: 687b ldr r3, [r7, #4] 8003336: 6e1b ldr r3, [r3, #96] @ 0x60 8003338: b2d2 uxtb r2, r2 800333a: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800333c: 687b ldr r3, [r7, #4] 800333e: 6e5b ldr r3, [r3, #100] @ 0x64 8003340: 687a ldr r2, [r7, #4] 8003342: 6e92 ldr r2, [r2, #104] @ 0x68 8003344: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8003346: 687b ldr r3, [r7, #4] 8003348: 685b ldr r3, [r3, #4] 800334a: 2b00 cmp r3, #0 800334c: d010 beq.n 8003370 800334e: 687b ldr r3, [r7, #4] 8003350: 685b ldr r3, [r3, #4] 8003352: 2b08 cmp r3, #8 8003354: d80c bhi.n 8003370 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8003356: 6878 ldr r0, [r7, #4] 8003358: f001 feaa bl 80050b0 /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 800335c: 687b ldr r3, [r7, #4] 800335e: 6edb ldr r3, [r3, #108] @ 0x6c 8003360: 2200 movs r2, #0 8003362: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003364: 687b ldr r3, [r7, #4] 8003366: 6f1b ldr r3, [r3, #112] @ 0x70 8003368: 687a ldr r2, [r7, #4] 800336a: 6f52 ldr r2, [r2, #116] @ 0x74 800336c: 605a str r2, [r3, #4] 800336e: e008 b.n 8003382 } else { hdma->DMAmuxRequestGen = 0U; 8003370: 687b ldr r3, [r7, #4] 8003372: 2200 movs r2, #0 8003374: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8003376: 687b ldr r3, [r7, #4] 8003378: 2200 movs r2, #0 800337a: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 800337c: 687b ldr r3, [r7, #4] 800337e: 2200 movs r2, #0 8003380: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8003382: 687b ldr r3, [r7, #4] 8003384: 2200 movs r2, #0 8003386: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003388: 687b ldr r3, [r7, #4] 800338a: 2201 movs r2, #1 800338c: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8003390: 2300 movs r3, #0 } 8003392: 4618 mov r0, r3 8003394: 3718 adds r7, #24 8003396: 46bd mov sp, r7 8003398: bd80 pop {r7, pc} 800339a: bf00 nop 800339c: a7fdabf8 .word 0xa7fdabf8 80033a0: cccccccd .word 0xcccccccd 80033a4: 40020010 .word 0x40020010 80033a8: 40020028 .word 0x40020028 80033ac: 40020040 .word 0x40020040 80033b0: 40020058 .word 0x40020058 80033b4: 40020070 .word 0x40020070 80033b8: 40020088 .word 0x40020088 80033bc: 400200a0 .word 0x400200a0 80033c0: 400200b8 .word 0x400200b8 80033c4: 40020410 .word 0x40020410 80033c8: 40020428 .word 0x40020428 80033cc: 40020440 .word 0x40020440 80033d0: 40020458 .word 0x40020458 80033d4: 40020470 .word 0x40020470 80033d8: 40020488 .word 0x40020488 80033dc: 400204a0 .word 0x400204a0 80033e0: 400204b8 .word 0x400204b8 80033e4: 58025408 .word 0x58025408 80033e8: 5802541c .word 0x5802541c 80033ec: 58025430 .word 0x58025430 80033f0: 58025444 .word 0x58025444 80033f4: 58025458 .word 0x58025458 80033f8: 5802546c .word 0x5802546c 80033fc: 58025480 .word 0x58025480 8003400: 58025494 .word 0x58025494 08003404 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 8003404: b580 push {r7, lr} 8003406: b086 sub sp, #24 8003408: af00 add r7, sp, #0 800340a: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 800340c: f7ff f928 bl 8002660 8003410: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 8003412: 687b ldr r3, [r7, #4] 8003414: 2b00 cmp r3, #0 8003416: d101 bne.n 800341c { return HAL_ERROR; 8003418: 2301 movs r3, #1 800341a: e2dc b.n 80039d6 } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 800341c: 687b ldr r3, [r7, #4] 800341e: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8003422: b2db uxtb r3, r3 8003424: 2b02 cmp r3, #2 8003426: d008 beq.n 800343a { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8003428: 687b ldr r3, [r7, #4] 800342a: 2280 movs r2, #128 @ 0x80 800342c: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800342e: 687b ldr r3, [r7, #4] 8003430: 2200 movs r2, #0 8003432: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8003436: 2301 movs r3, #1 8003438: e2cd b.n 80039d6 } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800343a: 687b ldr r3, [r7, #4] 800343c: 681b ldr r3, [r3, #0] 800343e: 4a76 ldr r2, [pc, #472] @ (8003618 ) 8003440: 4293 cmp r3, r2 8003442: d04a beq.n 80034da 8003444: 687b ldr r3, [r7, #4] 8003446: 681b ldr r3, [r3, #0] 8003448: 4a74 ldr r2, [pc, #464] @ (800361c ) 800344a: 4293 cmp r3, r2 800344c: d045 beq.n 80034da 800344e: 687b ldr r3, [r7, #4] 8003450: 681b ldr r3, [r3, #0] 8003452: 4a73 ldr r2, [pc, #460] @ (8003620 ) 8003454: 4293 cmp r3, r2 8003456: d040 beq.n 80034da 8003458: 687b ldr r3, [r7, #4] 800345a: 681b ldr r3, [r3, #0] 800345c: 4a71 ldr r2, [pc, #452] @ (8003624 ) 800345e: 4293 cmp r3, r2 8003460: d03b beq.n 80034da 8003462: 687b ldr r3, [r7, #4] 8003464: 681b ldr r3, [r3, #0] 8003466: 4a70 ldr r2, [pc, #448] @ (8003628 ) 8003468: 4293 cmp r3, r2 800346a: d036 beq.n 80034da 800346c: 687b ldr r3, [r7, #4] 800346e: 681b ldr r3, [r3, #0] 8003470: 4a6e ldr r2, [pc, #440] @ (800362c ) 8003472: 4293 cmp r3, r2 8003474: d031 beq.n 80034da 8003476: 687b ldr r3, [r7, #4] 8003478: 681b ldr r3, [r3, #0] 800347a: 4a6d ldr r2, [pc, #436] @ (8003630 ) 800347c: 4293 cmp r3, r2 800347e: d02c beq.n 80034da 8003480: 687b ldr r3, [r7, #4] 8003482: 681b ldr r3, [r3, #0] 8003484: 4a6b ldr r2, [pc, #428] @ (8003634 ) 8003486: 4293 cmp r3, r2 8003488: d027 beq.n 80034da 800348a: 687b ldr r3, [r7, #4] 800348c: 681b ldr r3, [r3, #0] 800348e: 4a6a ldr r2, [pc, #424] @ (8003638 ) 8003490: 4293 cmp r3, r2 8003492: d022 beq.n 80034da 8003494: 687b ldr r3, [r7, #4] 8003496: 681b ldr r3, [r3, #0] 8003498: 4a68 ldr r2, [pc, #416] @ (800363c ) 800349a: 4293 cmp r3, r2 800349c: d01d beq.n 80034da 800349e: 687b ldr r3, [r7, #4] 80034a0: 681b ldr r3, [r3, #0] 80034a2: 4a67 ldr r2, [pc, #412] @ (8003640 ) 80034a4: 4293 cmp r3, r2 80034a6: d018 beq.n 80034da 80034a8: 687b ldr r3, [r7, #4] 80034aa: 681b ldr r3, [r3, #0] 80034ac: 4a65 ldr r2, [pc, #404] @ (8003644 ) 80034ae: 4293 cmp r3, r2 80034b0: d013 beq.n 80034da 80034b2: 687b ldr r3, [r7, #4] 80034b4: 681b ldr r3, [r3, #0] 80034b6: 4a64 ldr r2, [pc, #400] @ (8003648 ) 80034b8: 4293 cmp r3, r2 80034ba: d00e beq.n 80034da 80034bc: 687b ldr r3, [r7, #4] 80034be: 681b ldr r3, [r3, #0] 80034c0: 4a62 ldr r2, [pc, #392] @ (800364c ) 80034c2: 4293 cmp r3, r2 80034c4: d009 beq.n 80034da 80034c6: 687b ldr r3, [r7, #4] 80034c8: 681b ldr r3, [r3, #0] 80034ca: 4a61 ldr r2, [pc, #388] @ (8003650 ) 80034cc: 4293 cmp r3, r2 80034ce: d004 beq.n 80034da 80034d0: 687b ldr r3, [r7, #4] 80034d2: 681b ldr r3, [r3, #0] 80034d4: 4a5f ldr r2, [pc, #380] @ (8003654 ) 80034d6: 4293 cmp r3, r2 80034d8: d101 bne.n 80034de 80034da: 2301 movs r3, #1 80034dc: e000 b.n 80034e0 80034de: 2300 movs r3, #0 80034e0: 2b00 cmp r3, #0 80034e2: d013 beq.n 800350c { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80034e4: 687b ldr r3, [r7, #4] 80034e6: 681b ldr r3, [r3, #0] 80034e8: 681a ldr r2, [r3, #0] 80034ea: 687b ldr r3, [r7, #4] 80034ec: 681b ldr r3, [r3, #0] 80034ee: f022 021e bic.w r2, r2, #30 80034f2: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80034f4: 687b ldr r3, [r7, #4] 80034f6: 681b ldr r3, [r3, #0] 80034f8: 695a ldr r2, [r3, #20] 80034fa: 687b ldr r3, [r7, #4] 80034fc: 681b ldr r3, [r3, #0] 80034fe: f022 0280 bic.w r2, r2, #128 @ 0x80 8003502: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 8003504: 687b ldr r3, [r7, #4] 8003506: 681b ldr r3, [r3, #0] 8003508: 617b str r3, [r7, #20] 800350a: e00a b.n 8003522 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 800350c: 687b ldr r3, [r7, #4] 800350e: 681b ldr r3, [r3, #0] 8003510: 681a ldr r2, [r3, #0] 8003512: 687b ldr r3, [r7, #4] 8003514: 681b ldr r3, [r3, #0] 8003516: f022 020e bic.w r2, r2, #14 800351a: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 800351c: 687b ldr r3, [r7, #4] 800351e: 681b ldr r3, [r3, #0] 8003520: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8003522: 687b ldr r3, [r7, #4] 8003524: 681b ldr r3, [r3, #0] 8003526: 4a3c ldr r2, [pc, #240] @ (8003618 ) 8003528: 4293 cmp r3, r2 800352a: d072 beq.n 8003612 800352c: 687b ldr r3, [r7, #4] 800352e: 681b ldr r3, [r3, #0] 8003530: 4a3a ldr r2, [pc, #232] @ (800361c ) 8003532: 4293 cmp r3, r2 8003534: d06d beq.n 8003612 8003536: 687b ldr r3, [r7, #4] 8003538: 681b ldr r3, [r3, #0] 800353a: 4a39 ldr r2, [pc, #228] @ (8003620 ) 800353c: 4293 cmp r3, r2 800353e: d068 beq.n 8003612 8003540: 687b ldr r3, [r7, #4] 8003542: 681b ldr r3, [r3, #0] 8003544: 4a37 ldr r2, [pc, #220] @ (8003624 ) 8003546: 4293 cmp r3, r2 8003548: d063 beq.n 8003612 800354a: 687b ldr r3, [r7, #4] 800354c: 681b ldr r3, [r3, #0] 800354e: 4a36 ldr r2, [pc, #216] @ (8003628 ) 8003550: 4293 cmp r3, r2 8003552: d05e beq.n 8003612 8003554: 687b ldr r3, [r7, #4] 8003556: 681b ldr r3, [r3, #0] 8003558: 4a34 ldr r2, [pc, #208] @ (800362c ) 800355a: 4293 cmp r3, r2 800355c: d059 beq.n 8003612 800355e: 687b ldr r3, [r7, #4] 8003560: 681b ldr r3, [r3, #0] 8003562: 4a33 ldr r2, [pc, #204] @ (8003630 ) 8003564: 4293 cmp r3, r2 8003566: d054 beq.n 8003612 8003568: 687b ldr r3, [r7, #4] 800356a: 681b ldr r3, [r3, #0] 800356c: 4a31 ldr r2, [pc, #196] @ (8003634 ) 800356e: 4293 cmp r3, r2 8003570: d04f beq.n 8003612 8003572: 687b ldr r3, [r7, #4] 8003574: 681b ldr r3, [r3, #0] 8003576: 4a30 ldr r2, [pc, #192] @ (8003638 ) 8003578: 4293 cmp r3, r2 800357a: d04a beq.n 8003612 800357c: 687b ldr r3, [r7, #4] 800357e: 681b ldr r3, [r3, #0] 8003580: 4a2e ldr r2, [pc, #184] @ (800363c ) 8003582: 4293 cmp r3, r2 8003584: d045 beq.n 8003612 8003586: 687b ldr r3, [r7, #4] 8003588: 681b ldr r3, [r3, #0] 800358a: 4a2d ldr r2, [pc, #180] @ (8003640 ) 800358c: 4293 cmp r3, r2 800358e: d040 beq.n 8003612 8003590: 687b ldr r3, [r7, #4] 8003592: 681b ldr r3, [r3, #0] 8003594: 4a2b ldr r2, [pc, #172] @ (8003644 ) 8003596: 4293 cmp r3, r2 8003598: d03b beq.n 8003612 800359a: 687b ldr r3, [r7, #4] 800359c: 681b ldr r3, [r3, #0] 800359e: 4a2a ldr r2, [pc, #168] @ (8003648 ) 80035a0: 4293 cmp r3, r2 80035a2: d036 beq.n 8003612 80035a4: 687b ldr r3, [r7, #4] 80035a6: 681b ldr r3, [r3, #0] 80035a8: 4a28 ldr r2, [pc, #160] @ (800364c ) 80035aa: 4293 cmp r3, r2 80035ac: d031 beq.n 8003612 80035ae: 687b ldr r3, [r7, #4] 80035b0: 681b ldr r3, [r3, #0] 80035b2: 4a27 ldr r2, [pc, #156] @ (8003650 ) 80035b4: 4293 cmp r3, r2 80035b6: d02c beq.n 8003612 80035b8: 687b ldr r3, [r7, #4] 80035ba: 681b ldr r3, [r3, #0] 80035bc: 4a25 ldr r2, [pc, #148] @ (8003654 ) 80035be: 4293 cmp r3, r2 80035c0: d027 beq.n 8003612 80035c2: 687b ldr r3, [r7, #4] 80035c4: 681b ldr r3, [r3, #0] 80035c6: 4a24 ldr r2, [pc, #144] @ (8003658 ) 80035c8: 4293 cmp r3, r2 80035ca: d022 beq.n 8003612 80035cc: 687b ldr r3, [r7, #4] 80035ce: 681b ldr r3, [r3, #0] 80035d0: 4a22 ldr r2, [pc, #136] @ (800365c ) 80035d2: 4293 cmp r3, r2 80035d4: d01d beq.n 8003612 80035d6: 687b ldr r3, [r7, #4] 80035d8: 681b ldr r3, [r3, #0] 80035da: 4a21 ldr r2, [pc, #132] @ (8003660 ) 80035dc: 4293 cmp r3, r2 80035de: d018 beq.n 8003612 80035e0: 687b ldr r3, [r7, #4] 80035e2: 681b ldr r3, [r3, #0] 80035e4: 4a1f ldr r2, [pc, #124] @ (8003664 ) 80035e6: 4293 cmp r3, r2 80035e8: d013 beq.n 8003612 80035ea: 687b ldr r3, [r7, #4] 80035ec: 681b ldr r3, [r3, #0] 80035ee: 4a1e ldr r2, [pc, #120] @ (8003668 ) 80035f0: 4293 cmp r3, r2 80035f2: d00e beq.n 8003612 80035f4: 687b ldr r3, [r7, #4] 80035f6: 681b ldr r3, [r3, #0] 80035f8: 4a1c ldr r2, [pc, #112] @ (800366c ) 80035fa: 4293 cmp r3, r2 80035fc: d009 beq.n 8003612 80035fe: 687b ldr r3, [r7, #4] 8003600: 681b ldr r3, [r3, #0] 8003602: 4a1b ldr r2, [pc, #108] @ (8003670 ) 8003604: 4293 cmp r3, r2 8003606: d004 beq.n 8003612 8003608: 687b ldr r3, [r7, #4] 800360a: 681b ldr r3, [r3, #0] 800360c: 4a19 ldr r2, [pc, #100] @ (8003674 ) 800360e: 4293 cmp r3, r2 8003610: d132 bne.n 8003678 8003612: 2301 movs r3, #1 8003614: e031 b.n 800367a 8003616: bf00 nop 8003618: 40020010 .word 0x40020010 800361c: 40020028 .word 0x40020028 8003620: 40020040 .word 0x40020040 8003624: 40020058 .word 0x40020058 8003628: 40020070 .word 0x40020070 800362c: 40020088 .word 0x40020088 8003630: 400200a0 .word 0x400200a0 8003634: 400200b8 .word 0x400200b8 8003638: 40020410 .word 0x40020410 800363c: 40020428 .word 0x40020428 8003640: 40020440 .word 0x40020440 8003644: 40020458 .word 0x40020458 8003648: 40020470 .word 0x40020470 800364c: 40020488 .word 0x40020488 8003650: 400204a0 .word 0x400204a0 8003654: 400204b8 .word 0x400204b8 8003658: 58025408 .word 0x58025408 800365c: 5802541c .word 0x5802541c 8003660: 58025430 .word 0x58025430 8003664: 58025444 .word 0x58025444 8003668: 58025458 .word 0x58025458 800366c: 5802546c .word 0x5802546c 8003670: 58025480 .word 0x58025480 8003674: 58025494 .word 0x58025494 8003678: 2300 movs r3, #0 800367a: 2b00 cmp r3, #0 800367c: d007 beq.n 800368e { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800367e: 687b ldr r3, [r7, #4] 8003680: 6e1b ldr r3, [r3, #96] @ 0x60 8003682: 681a ldr r2, [r3, #0] 8003684: 687b ldr r3, [r7, #4] 8003686: 6e1b ldr r3, [r3, #96] @ 0x60 8003688: f422 7280 bic.w r2, r2, #256 @ 0x100 800368c: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800368e: 687b ldr r3, [r7, #4] 8003690: 681b ldr r3, [r3, #0] 8003692: 4a6d ldr r2, [pc, #436] @ (8003848 ) 8003694: 4293 cmp r3, r2 8003696: d04a beq.n 800372e 8003698: 687b ldr r3, [r7, #4] 800369a: 681b ldr r3, [r3, #0] 800369c: 4a6b ldr r2, [pc, #428] @ (800384c ) 800369e: 4293 cmp r3, r2 80036a0: d045 beq.n 800372e 80036a2: 687b ldr r3, [r7, #4] 80036a4: 681b ldr r3, [r3, #0] 80036a6: 4a6a ldr r2, [pc, #424] @ (8003850 ) 80036a8: 4293 cmp r3, r2 80036aa: d040 beq.n 800372e 80036ac: 687b ldr r3, [r7, #4] 80036ae: 681b ldr r3, [r3, #0] 80036b0: 4a68 ldr r2, [pc, #416] @ (8003854 ) 80036b2: 4293 cmp r3, r2 80036b4: d03b beq.n 800372e 80036b6: 687b ldr r3, [r7, #4] 80036b8: 681b ldr r3, [r3, #0] 80036ba: 4a67 ldr r2, [pc, #412] @ (8003858 ) 80036bc: 4293 cmp r3, r2 80036be: d036 beq.n 800372e 80036c0: 687b ldr r3, [r7, #4] 80036c2: 681b ldr r3, [r3, #0] 80036c4: 4a65 ldr r2, [pc, #404] @ (800385c ) 80036c6: 4293 cmp r3, r2 80036c8: d031 beq.n 800372e 80036ca: 687b ldr r3, [r7, #4] 80036cc: 681b ldr r3, [r3, #0] 80036ce: 4a64 ldr r2, [pc, #400] @ (8003860 ) 80036d0: 4293 cmp r3, r2 80036d2: d02c beq.n 800372e 80036d4: 687b ldr r3, [r7, #4] 80036d6: 681b ldr r3, [r3, #0] 80036d8: 4a62 ldr r2, [pc, #392] @ (8003864 ) 80036da: 4293 cmp r3, r2 80036dc: d027 beq.n 800372e 80036de: 687b ldr r3, [r7, #4] 80036e0: 681b ldr r3, [r3, #0] 80036e2: 4a61 ldr r2, [pc, #388] @ (8003868 ) 80036e4: 4293 cmp r3, r2 80036e6: d022 beq.n 800372e 80036e8: 687b ldr r3, [r7, #4] 80036ea: 681b ldr r3, [r3, #0] 80036ec: 4a5f ldr r2, [pc, #380] @ (800386c ) 80036ee: 4293 cmp r3, r2 80036f0: d01d beq.n 800372e 80036f2: 687b ldr r3, [r7, #4] 80036f4: 681b ldr r3, [r3, #0] 80036f6: 4a5e ldr r2, [pc, #376] @ (8003870 ) 80036f8: 4293 cmp r3, r2 80036fa: d018 beq.n 800372e 80036fc: 687b ldr r3, [r7, #4] 80036fe: 681b ldr r3, [r3, #0] 8003700: 4a5c ldr r2, [pc, #368] @ (8003874 ) 8003702: 4293 cmp r3, r2 8003704: d013 beq.n 800372e 8003706: 687b ldr r3, [r7, #4] 8003708: 681b ldr r3, [r3, #0] 800370a: 4a5b ldr r2, [pc, #364] @ (8003878 ) 800370c: 4293 cmp r3, r2 800370e: d00e beq.n 800372e 8003710: 687b ldr r3, [r7, #4] 8003712: 681b ldr r3, [r3, #0] 8003714: 4a59 ldr r2, [pc, #356] @ (800387c ) 8003716: 4293 cmp r3, r2 8003718: d009 beq.n 800372e 800371a: 687b ldr r3, [r7, #4] 800371c: 681b ldr r3, [r3, #0] 800371e: 4a58 ldr r2, [pc, #352] @ (8003880 ) 8003720: 4293 cmp r3, r2 8003722: d004 beq.n 800372e 8003724: 687b ldr r3, [r7, #4] 8003726: 681b ldr r3, [r3, #0] 8003728: 4a56 ldr r2, [pc, #344] @ (8003884 ) 800372a: 4293 cmp r3, r2 800372c: d108 bne.n 8003740 800372e: 687b ldr r3, [r7, #4] 8003730: 681b ldr r3, [r3, #0] 8003732: 681a ldr r2, [r3, #0] 8003734: 687b ldr r3, [r7, #4] 8003736: 681b ldr r3, [r3, #0] 8003738: f022 0201 bic.w r2, r2, #1 800373c: 601a str r2, [r3, #0] 800373e: e007 b.n 8003750 8003740: 687b ldr r3, [r7, #4] 8003742: 681b ldr r3, [r3, #0] 8003744: 681a ldr r2, [r3, #0] 8003746: 687b ldr r3, [r7, #4] 8003748: 681b ldr r3, [r3, #0] 800374a: f022 0201 bic.w r2, r2, #1 800374e: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8003750: e013 b.n 800377a { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8003752: f7fe ff85 bl 8002660 8003756: 4602 mov r2, r0 8003758: 693b ldr r3, [r7, #16] 800375a: 1ad3 subs r3, r2, r3 800375c: 2b05 cmp r3, #5 800375e: d90c bls.n 800377a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8003760: 687b ldr r3, [r7, #4] 8003762: 2220 movs r2, #32 8003764: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8003766: 687b ldr r3, [r7, #4] 8003768: 2203 movs r2, #3 800376a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800376e: 687b ldr r3, [r7, #4] 8003770: 2200 movs r2, #0 8003772: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8003776: 2301 movs r3, #1 8003778: e12d b.n 80039d6 while(((*enableRegister) & DMA_SxCR_EN) != 0U) 800377a: 697b ldr r3, [r7, #20] 800377c: 681b ldr r3, [r3, #0] 800377e: f003 0301 and.w r3, r3, #1 8003782: 2b00 cmp r3, #0 8003784: d1e5 bne.n 8003752 } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8003786: 687b ldr r3, [r7, #4] 8003788: 681b ldr r3, [r3, #0] 800378a: 4a2f ldr r2, [pc, #188] @ (8003848 ) 800378c: 4293 cmp r3, r2 800378e: d04a beq.n 8003826 8003790: 687b ldr r3, [r7, #4] 8003792: 681b ldr r3, [r3, #0] 8003794: 4a2d ldr r2, [pc, #180] @ (800384c ) 8003796: 4293 cmp r3, r2 8003798: d045 beq.n 8003826 800379a: 687b ldr r3, [r7, #4] 800379c: 681b ldr r3, [r3, #0] 800379e: 4a2c ldr r2, [pc, #176] @ (8003850 ) 80037a0: 4293 cmp r3, r2 80037a2: d040 beq.n 8003826 80037a4: 687b ldr r3, [r7, #4] 80037a6: 681b ldr r3, [r3, #0] 80037a8: 4a2a ldr r2, [pc, #168] @ (8003854 ) 80037aa: 4293 cmp r3, r2 80037ac: d03b beq.n 8003826 80037ae: 687b ldr r3, [r7, #4] 80037b0: 681b ldr r3, [r3, #0] 80037b2: 4a29 ldr r2, [pc, #164] @ (8003858 ) 80037b4: 4293 cmp r3, r2 80037b6: d036 beq.n 8003826 80037b8: 687b ldr r3, [r7, #4] 80037ba: 681b ldr r3, [r3, #0] 80037bc: 4a27 ldr r2, [pc, #156] @ (800385c ) 80037be: 4293 cmp r3, r2 80037c0: d031 beq.n 8003826 80037c2: 687b ldr r3, [r7, #4] 80037c4: 681b ldr r3, [r3, #0] 80037c6: 4a26 ldr r2, [pc, #152] @ (8003860 ) 80037c8: 4293 cmp r3, r2 80037ca: d02c beq.n 8003826 80037cc: 687b ldr r3, [r7, #4] 80037ce: 681b ldr r3, [r3, #0] 80037d0: 4a24 ldr r2, [pc, #144] @ (8003864 ) 80037d2: 4293 cmp r3, r2 80037d4: d027 beq.n 8003826 80037d6: 687b ldr r3, [r7, #4] 80037d8: 681b ldr r3, [r3, #0] 80037da: 4a23 ldr r2, [pc, #140] @ (8003868 ) 80037dc: 4293 cmp r3, r2 80037de: d022 beq.n 8003826 80037e0: 687b ldr r3, [r7, #4] 80037e2: 681b ldr r3, [r3, #0] 80037e4: 4a21 ldr r2, [pc, #132] @ (800386c ) 80037e6: 4293 cmp r3, r2 80037e8: d01d beq.n 8003826 80037ea: 687b ldr r3, [r7, #4] 80037ec: 681b ldr r3, [r3, #0] 80037ee: 4a20 ldr r2, [pc, #128] @ (8003870 ) 80037f0: 4293 cmp r3, r2 80037f2: d018 beq.n 8003826 80037f4: 687b ldr r3, [r7, #4] 80037f6: 681b ldr r3, [r3, #0] 80037f8: 4a1e ldr r2, [pc, #120] @ (8003874 ) 80037fa: 4293 cmp r3, r2 80037fc: d013 beq.n 8003826 80037fe: 687b ldr r3, [r7, #4] 8003800: 681b ldr r3, [r3, #0] 8003802: 4a1d ldr r2, [pc, #116] @ (8003878 ) 8003804: 4293 cmp r3, r2 8003806: d00e beq.n 8003826 8003808: 687b ldr r3, [r7, #4] 800380a: 681b ldr r3, [r3, #0] 800380c: 4a1b ldr r2, [pc, #108] @ (800387c ) 800380e: 4293 cmp r3, r2 8003810: d009 beq.n 8003826 8003812: 687b ldr r3, [r7, #4] 8003814: 681b ldr r3, [r3, #0] 8003816: 4a1a ldr r2, [pc, #104] @ (8003880 ) 8003818: 4293 cmp r3, r2 800381a: d004 beq.n 8003826 800381c: 687b ldr r3, [r7, #4] 800381e: 681b ldr r3, [r3, #0] 8003820: 4a18 ldr r2, [pc, #96] @ (8003884 ) 8003822: 4293 cmp r3, r2 8003824: d101 bne.n 800382a 8003826: 2301 movs r3, #1 8003828: e000 b.n 800382c 800382a: 2300 movs r3, #0 800382c: 2b00 cmp r3, #0 800382e: d02b beq.n 8003888 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8003830: 687b ldr r3, [r7, #4] 8003832: 6d9b ldr r3, [r3, #88] @ 0x58 8003834: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8003836: 687b ldr r3, [r7, #4] 8003838: 6ddb ldr r3, [r3, #92] @ 0x5c 800383a: f003 031f and.w r3, r3, #31 800383e: 223f movs r2, #63 @ 0x3f 8003840: 409a lsls r2, r3 8003842: 68bb ldr r3, [r7, #8] 8003844: 609a str r2, [r3, #8] 8003846: e02a b.n 800389e 8003848: 40020010 .word 0x40020010 800384c: 40020028 .word 0x40020028 8003850: 40020040 .word 0x40020040 8003854: 40020058 .word 0x40020058 8003858: 40020070 .word 0x40020070 800385c: 40020088 .word 0x40020088 8003860: 400200a0 .word 0x400200a0 8003864: 400200b8 .word 0x400200b8 8003868: 40020410 .word 0x40020410 800386c: 40020428 .word 0x40020428 8003870: 40020440 .word 0x40020440 8003874: 40020458 .word 0x40020458 8003878: 40020470 .word 0x40020470 800387c: 40020488 .word 0x40020488 8003880: 400204a0 .word 0x400204a0 8003884: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8003888: 687b ldr r3, [r7, #4] 800388a: 6d9b ldr r3, [r3, #88] @ 0x58 800388c: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800388e: 687b ldr r3, [r7, #4] 8003890: 6ddb ldr r3, [r3, #92] @ 0x5c 8003892: f003 031f and.w r3, r3, #31 8003896: 2201 movs r2, #1 8003898: 409a lsls r2, r3 800389a: 68fb ldr r3, [r7, #12] 800389c: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800389e: 687b ldr r3, [r7, #4] 80038a0: 681b ldr r3, [r3, #0] 80038a2: 4a4f ldr r2, [pc, #316] @ (80039e0 ) 80038a4: 4293 cmp r3, r2 80038a6: d072 beq.n 800398e 80038a8: 687b ldr r3, [r7, #4] 80038aa: 681b ldr r3, [r3, #0] 80038ac: 4a4d ldr r2, [pc, #308] @ (80039e4 ) 80038ae: 4293 cmp r3, r2 80038b0: d06d beq.n 800398e 80038b2: 687b ldr r3, [r7, #4] 80038b4: 681b ldr r3, [r3, #0] 80038b6: 4a4c ldr r2, [pc, #304] @ (80039e8 ) 80038b8: 4293 cmp r3, r2 80038ba: d068 beq.n 800398e 80038bc: 687b ldr r3, [r7, #4] 80038be: 681b ldr r3, [r3, #0] 80038c0: 4a4a ldr r2, [pc, #296] @ (80039ec ) 80038c2: 4293 cmp r3, r2 80038c4: d063 beq.n 800398e 80038c6: 687b ldr r3, [r7, #4] 80038c8: 681b ldr r3, [r3, #0] 80038ca: 4a49 ldr r2, [pc, #292] @ (80039f0 ) 80038cc: 4293 cmp r3, r2 80038ce: d05e beq.n 800398e 80038d0: 687b ldr r3, [r7, #4] 80038d2: 681b ldr r3, [r3, #0] 80038d4: 4a47 ldr r2, [pc, #284] @ (80039f4 ) 80038d6: 4293 cmp r3, r2 80038d8: d059 beq.n 800398e 80038da: 687b ldr r3, [r7, #4] 80038dc: 681b ldr r3, [r3, #0] 80038de: 4a46 ldr r2, [pc, #280] @ (80039f8 ) 80038e0: 4293 cmp r3, r2 80038e2: d054 beq.n 800398e 80038e4: 687b ldr r3, [r7, #4] 80038e6: 681b ldr r3, [r3, #0] 80038e8: 4a44 ldr r2, [pc, #272] @ (80039fc ) 80038ea: 4293 cmp r3, r2 80038ec: d04f beq.n 800398e 80038ee: 687b ldr r3, [r7, #4] 80038f0: 681b ldr r3, [r3, #0] 80038f2: 4a43 ldr r2, [pc, #268] @ (8003a00 ) 80038f4: 4293 cmp r3, r2 80038f6: d04a beq.n 800398e 80038f8: 687b ldr r3, [r7, #4] 80038fa: 681b ldr r3, [r3, #0] 80038fc: 4a41 ldr r2, [pc, #260] @ (8003a04 ) 80038fe: 4293 cmp r3, r2 8003900: d045 beq.n 800398e 8003902: 687b ldr r3, [r7, #4] 8003904: 681b ldr r3, [r3, #0] 8003906: 4a40 ldr r2, [pc, #256] @ (8003a08 ) 8003908: 4293 cmp r3, r2 800390a: d040 beq.n 800398e 800390c: 687b ldr r3, [r7, #4] 800390e: 681b ldr r3, [r3, #0] 8003910: 4a3e ldr r2, [pc, #248] @ (8003a0c ) 8003912: 4293 cmp r3, r2 8003914: d03b beq.n 800398e 8003916: 687b ldr r3, [r7, #4] 8003918: 681b ldr r3, [r3, #0] 800391a: 4a3d ldr r2, [pc, #244] @ (8003a10 ) 800391c: 4293 cmp r3, r2 800391e: d036 beq.n 800398e 8003920: 687b ldr r3, [r7, #4] 8003922: 681b ldr r3, [r3, #0] 8003924: 4a3b ldr r2, [pc, #236] @ (8003a14 ) 8003926: 4293 cmp r3, r2 8003928: d031 beq.n 800398e 800392a: 687b ldr r3, [r7, #4] 800392c: 681b ldr r3, [r3, #0] 800392e: 4a3a ldr r2, [pc, #232] @ (8003a18 ) 8003930: 4293 cmp r3, r2 8003932: d02c beq.n 800398e 8003934: 687b ldr r3, [r7, #4] 8003936: 681b ldr r3, [r3, #0] 8003938: 4a38 ldr r2, [pc, #224] @ (8003a1c ) 800393a: 4293 cmp r3, r2 800393c: d027 beq.n 800398e 800393e: 687b ldr r3, [r7, #4] 8003940: 681b ldr r3, [r3, #0] 8003942: 4a37 ldr r2, [pc, #220] @ (8003a20 ) 8003944: 4293 cmp r3, r2 8003946: d022 beq.n 800398e 8003948: 687b ldr r3, [r7, #4] 800394a: 681b ldr r3, [r3, #0] 800394c: 4a35 ldr r2, [pc, #212] @ (8003a24 ) 800394e: 4293 cmp r3, r2 8003950: d01d beq.n 800398e 8003952: 687b ldr r3, [r7, #4] 8003954: 681b ldr r3, [r3, #0] 8003956: 4a34 ldr r2, [pc, #208] @ (8003a28 ) 8003958: 4293 cmp r3, r2 800395a: d018 beq.n 800398e 800395c: 687b ldr r3, [r7, #4] 800395e: 681b ldr r3, [r3, #0] 8003960: 4a32 ldr r2, [pc, #200] @ (8003a2c ) 8003962: 4293 cmp r3, r2 8003964: d013 beq.n 800398e 8003966: 687b ldr r3, [r7, #4] 8003968: 681b ldr r3, [r3, #0] 800396a: 4a31 ldr r2, [pc, #196] @ (8003a30 ) 800396c: 4293 cmp r3, r2 800396e: d00e beq.n 800398e 8003970: 687b ldr r3, [r7, #4] 8003972: 681b ldr r3, [r3, #0] 8003974: 4a2f ldr r2, [pc, #188] @ (8003a34 ) 8003976: 4293 cmp r3, r2 8003978: d009 beq.n 800398e 800397a: 687b ldr r3, [r7, #4] 800397c: 681b ldr r3, [r3, #0] 800397e: 4a2e ldr r2, [pc, #184] @ (8003a38 ) 8003980: 4293 cmp r3, r2 8003982: d004 beq.n 800398e 8003984: 687b ldr r3, [r7, #4] 8003986: 681b ldr r3, [r3, #0] 8003988: 4a2c ldr r2, [pc, #176] @ (8003a3c ) 800398a: 4293 cmp r3, r2 800398c: d101 bne.n 8003992 800398e: 2301 movs r3, #1 8003990: e000 b.n 8003994 8003992: 2300 movs r3, #0 8003994: 2b00 cmp r3, #0 8003996: d015 beq.n 80039c4 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003998: 687b ldr r3, [r7, #4] 800399a: 6e5b ldr r3, [r3, #100] @ 0x64 800399c: 687a ldr r2, [r7, #4] 800399e: 6e92 ldr r2, [r2, #104] @ 0x68 80039a0: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 80039a2: 687b ldr r3, [r7, #4] 80039a4: 6edb ldr r3, [r3, #108] @ 0x6c 80039a6: 2b00 cmp r3, #0 80039a8: d00c beq.n 80039c4 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 80039aa: 687b ldr r3, [r7, #4] 80039ac: 6edb ldr r3, [r3, #108] @ 0x6c 80039ae: 681a ldr r2, [r3, #0] 80039b0: 687b ldr r3, [r7, #4] 80039b2: 6edb ldr r3, [r3, #108] @ 0x6c 80039b4: f422 7280 bic.w r2, r2, #256 @ 0x100 80039b8: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80039ba: 687b ldr r3, [r7, #4] 80039bc: 6f1b ldr r3, [r3, #112] @ 0x70 80039be: 687a ldr r2, [r7, #4] 80039c0: 6f52 ldr r2, [r2, #116] @ 0x74 80039c2: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80039c4: 687b ldr r3, [r7, #4] 80039c6: 2201 movs r2, #1 80039c8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80039cc: 687b ldr r3, [r7, #4] 80039ce: 2200 movs r2, #0 80039d0: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 80039d4: 2300 movs r3, #0 } 80039d6: 4618 mov r0, r3 80039d8: 3718 adds r7, #24 80039da: 46bd mov sp, r7 80039dc: bd80 pop {r7, pc} 80039de: bf00 nop 80039e0: 40020010 .word 0x40020010 80039e4: 40020028 .word 0x40020028 80039e8: 40020040 .word 0x40020040 80039ec: 40020058 .word 0x40020058 80039f0: 40020070 .word 0x40020070 80039f4: 40020088 .word 0x40020088 80039f8: 400200a0 .word 0x400200a0 80039fc: 400200b8 .word 0x400200b8 8003a00: 40020410 .word 0x40020410 8003a04: 40020428 .word 0x40020428 8003a08: 40020440 .word 0x40020440 8003a0c: 40020458 .word 0x40020458 8003a10: 40020470 .word 0x40020470 8003a14: 40020488 .word 0x40020488 8003a18: 400204a0 .word 0x400204a0 8003a1c: 400204b8 .word 0x400204b8 8003a20: 58025408 .word 0x58025408 8003a24: 5802541c .word 0x5802541c 8003a28: 58025430 .word 0x58025430 8003a2c: 58025444 .word 0x58025444 8003a30: 58025458 .word 0x58025458 8003a34: 5802546c .word 0x5802546c 8003a38: 58025480 .word 0x58025480 8003a3c: 58025494 .word 0x58025494 08003a40 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8003a40: b580 push {r7, lr} 8003a42: b084 sub sp, #16 8003a44: af00 add r7, sp, #0 8003a46: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8003a48: 687b ldr r3, [r7, #4] 8003a4a: 2b00 cmp r3, #0 8003a4c: d101 bne.n 8003a52 { return HAL_ERROR; 8003a4e: 2301 movs r3, #1 8003a50: e237 b.n 8003ec2 } if(hdma->State != HAL_DMA_STATE_BUSY) 8003a52: 687b ldr r3, [r7, #4] 8003a54: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8003a58: b2db uxtb r3, r3 8003a5a: 2b02 cmp r3, #2 8003a5c: d004 beq.n 8003a68 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8003a5e: 687b ldr r3, [r7, #4] 8003a60: 2280 movs r2, #128 @ 0x80 8003a62: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8003a64: 2301 movs r3, #1 8003a66: e22c b.n 8003ec2 } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8003a68: 687b ldr r3, [r7, #4] 8003a6a: 681b ldr r3, [r3, #0] 8003a6c: 4a5c ldr r2, [pc, #368] @ (8003be0 ) 8003a6e: 4293 cmp r3, r2 8003a70: d04a beq.n 8003b08 8003a72: 687b ldr r3, [r7, #4] 8003a74: 681b ldr r3, [r3, #0] 8003a76: 4a5b ldr r2, [pc, #364] @ (8003be4 ) 8003a78: 4293 cmp r3, r2 8003a7a: d045 beq.n 8003b08 8003a7c: 687b ldr r3, [r7, #4] 8003a7e: 681b ldr r3, [r3, #0] 8003a80: 4a59 ldr r2, [pc, #356] @ (8003be8 ) 8003a82: 4293 cmp r3, r2 8003a84: d040 beq.n 8003b08 8003a86: 687b ldr r3, [r7, #4] 8003a88: 681b ldr r3, [r3, #0] 8003a8a: 4a58 ldr r2, [pc, #352] @ (8003bec ) 8003a8c: 4293 cmp r3, r2 8003a8e: d03b beq.n 8003b08 8003a90: 687b ldr r3, [r7, #4] 8003a92: 681b ldr r3, [r3, #0] 8003a94: 4a56 ldr r2, [pc, #344] @ (8003bf0 ) 8003a96: 4293 cmp r3, r2 8003a98: d036 beq.n 8003b08 8003a9a: 687b ldr r3, [r7, #4] 8003a9c: 681b ldr r3, [r3, #0] 8003a9e: 4a55 ldr r2, [pc, #340] @ (8003bf4 ) 8003aa0: 4293 cmp r3, r2 8003aa2: d031 beq.n 8003b08 8003aa4: 687b ldr r3, [r7, #4] 8003aa6: 681b ldr r3, [r3, #0] 8003aa8: 4a53 ldr r2, [pc, #332] @ (8003bf8 ) 8003aaa: 4293 cmp r3, r2 8003aac: d02c beq.n 8003b08 8003aae: 687b ldr r3, [r7, #4] 8003ab0: 681b ldr r3, [r3, #0] 8003ab2: 4a52 ldr r2, [pc, #328] @ (8003bfc ) 8003ab4: 4293 cmp r3, r2 8003ab6: d027 beq.n 8003b08 8003ab8: 687b ldr r3, [r7, #4] 8003aba: 681b ldr r3, [r3, #0] 8003abc: 4a50 ldr r2, [pc, #320] @ (8003c00 ) 8003abe: 4293 cmp r3, r2 8003ac0: d022 beq.n 8003b08 8003ac2: 687b ldr r3, [r7, #4] 8003ac4: 681b ldr r3, [r3, #0] 8003ac6: 4a4f ldr r2, [pc, #316] @ (8003c04 ) 8003ac8: 4293 cmp r3, r2 8003aca: d01d beq.n 8003b08 8003acc: 687b ldr r3, [r7, #4] 8003ace: 681b ldr r3, [r3, #0] 8003ad0: 4a4d ldr r2, [pc, #308] @ (8003c08 ) 8003ad2: 4293 cmp r3, r2 8003ad4: d018 beq.n 8003b08 8003ad6: 687b ldr r3, [r7, #4] 8003ad8: 681b ldr r3, [r3, #0] 8003ada: 4a4c ldr r2, [pc, #304] @ (8003c0c ) 8003adc: 4293 cmp r3, r2 8003ade: d013 beq.n 8003b08 8003ae0: 687b ldr r3, [r7, #4] 8003ae2: 681b ldr r3, [r3, #0] 8003ae4: 4a4a ldr r2, [pc, #296] @ (8003c10 ) 8003ae6: 4293 cmp r3, r2 8003ae8: d00e beq.n 8003b08 8003aea: 687b ldr r3, [r7, #4] 8003aec: 681b ldr r3, [r3, #0] 8003aee: 4a49 ldr r2, [pc, #292] @ (8003c14 ) 8003af0: 4293 cmp r3, r2 8003af2: d009 beq.n 8003b08 8003af4: 687b ldr r3, [r7, #4] 8003af6: 681b ldr r3, [r3, #0] 8003af8: 4a47 ldr r2, [pc, #284] @ (8003c18 ) 8003afa: 4293 cmp r3, r2 8003afc: d004 beq.n 8003b08 8003afe: 687b ldr r3, [r7, #4] 8003b00: 681b ldr r3, [r3, #0] 8003b02: 4a46 ldr r2, [pc, #280] @ (8003c1c ) 8003b04: 4293 cmp r3, r2 8003b06: d101 bne.n 8003b0c 8003b08: 2301 movs r3, #1 8003b0a: e000 b.n 8003b0e 8003b0c: 2300 movs r3, #0 8003b0e: 2b00 cmp r3, #0 8003b10: f000 8086 beq.w 8003c20 { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8003b14: 687b ldr r3, [r7, #4] 8003b16: 2204 movs r2, #4 8003b18: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8003b1c: 687b ldr r3, [r7, #4] 8003b1e: 681b ldr r3, [r3, #0] 8003b20: 4a2f ldr r2, [pc, #188] @ (8003be0 ) 8003b22: 4293 cmp r3, r2 8003b24: d04a beq.n 8003bbc 8003b26: 687b ldr r3, [r7, #4] 8003b28: 681b ldr r3, [r3, #0] 8003b2a: 4a2e ldr r2, [pc, #184] @ (8003be4 ) 8003b2c: 4293 cmp r3, r2 8003b2e: d045 beq.n 8003bbc 8003b30: 687b ldr r3, [r7, #4] 8003b32: 681b ldr r3, [r3, #0] 8003b34: 4a2c ldr r2, [pc, #176] @ (8003be8 ) 8003b36: 4293 cmp r3, r2 8003b38: d040 beq.n 8003bbc 8003b3a: 687b ldr r3, [r7, #4] 8003b3c: 681b ldr r3, [r3, #0] 8003b3e: 4a2b ldr r2, [pc, #172] @ (8003bec ) 8003b40: 4293 cmp r3, r2 8003b42: d03b beq.n 8003bbc 8003b44: 687b ldr r3, [r7, #4] 8003b46: 681b ldr r3, [r3, #0] 8003b48: 4a29 ldr r2, [pc, #164] @ (8003bf0 ) 8003b4a: 4293 cmp r3, r2 8003b4c: d036 beq.n 8003bbc 8003b4e: 687b ldr r3, [r7, #4] 8003b50: 681b ldr r3, [r3, #0] 8003b52: 4a28 ldr r2, [pc, #160] @ (8003bf4 ) 8003b54: 4293 cmp r3, r2 8003b56: d031 beq.n 8003bbc 8003b58: 687b ldr r3, [r7, #4] 8003b5a: 681b ldr r3, [r3, #0] 8003b5c: 4a26 ldr r2, [pc, #152] @ (8003bf8 ) 8003b5e: 4293 cmp r3, r2 8003b60: d02c beq.n 8003bbc 8003b62: 687b ldr r3, [r7, #4] 8003b64: 681b ldr r3, [r3, #0] 8003b66: 4a25 ldr r2, [pc, #148] @ (8003bfc ) 8003b68: 4293 cmp r3, r2 8003b6a: d027 beq.n 8003bbc 8003b6c: 687b ldr r3, [r7, #4] 8003b6e: 681b ldr r3, [r3, #0] 8003b70: 4a23 ldr r2, [pc, #140] @ (8003c00 ) 8003b72: 4293 cmp r3, r2 8003b74: d022 beq.n 8003bbc 8003b76: 687b ldr r3, [r7, #4] 8003b78: 681b ldr r3, [r3, #0] 8003b7a: 4a22 ldr r2, [pc, #136] @ (8003c04 ) 8003b7c: 4293 cmp r3, r2 8003b7e: d01d beq.n 8003bbc 8003b80: 687b ldr r3, [r7, #4] 8003b82: 681b ldr r3, [r3, #0] 8003b84: 4a20 ldr r2, [pc, #128] @ (8003c08 ) 8003b86: 4293 cmp r3, r2 8003b88: d018 beq.n 8003bbc 8003b8a: 687b ldr r3, [r7, #4] 8003b8c: 681b ldr r3, [r3, #0] 8003b8e: 4a1f ldr r2, [pc, #124] @ (8003c0c ) 8003b90: 4293 cmp r3, r2 8003b92: d013 beq.n 8003bbc 8003b94: 687b ldr r3, [r7, #4] 8003b96: 681b ldr r3, [r3, #0] 8003b98: 4a1d ldr r2, [pc, #116] @ (8003c10 ) 8003b9a: 4293 cmp r3, r2 8003b9c: d00e beq.n 8003bbc 8003b9e: 687b ldr r3, [r7, #4] 8003ba0: 681b ldr r3, [r3, #0] 8003ba2: 4a1c ldr r2, [pc, #112] @ (8003c14 ) 8003ba4: 4293 cmp r3, r2 8003ba6: d009 beq.n 8003bbc 8003ba8: 687b ldr r3, [r7, #4] 8003baa: 681b ldr r3, [r3, #0] 8003bac: 4a1a ldr r2, [pc, #104] @ (8003c18 ) 8003bae: 4293 cmp r3, r2 8003bb0: d004 beq.n 8003bbc 8003bb2: 687b ldr r3, [r7, #4] 8003bb4: 681b ldr r3, [r3, #0] 8003bb6: 4a19 ldr r2, [pc, #100] @ (8003c1c ) 8003bb8: 4293 cmp r3, r2 8003bba: d108 bne.n 8003bce 8003bbc: 687b ldr r3, [r7, #4] 8003bbe: 681b ldr r3, [r3, #0] 8003bc0: 681a ldr r2, [r3, #0] 8003bc2: 687b ldr r3, [r7, #4] 8003bc4: 681b ldr r3, [r3, #0] 8003bc6: f022 0201 bic.w r2, r2, #1 8003bca: 601a str r2, [r3, #0] 8003bcc: e178 b.n 8003ec0 8003bce: 687b ldr r3, [r7, #4] 8003bd0: 681b ldr r3, [r3, #0] 8003bd2: 681a ldr r2, [r3, #0] 8003bd4: 687b ldr r3, [r7, #4] 8003bd6: 681b ldr r3, [r3, #0] 8003bd8: f022 0201 bic.w r2, r2, #1 8003bdc: 601a str r2, [r3, #0] 8003bde: e16f b.n 8003ec0 8003be0: 40020010 .word 0x40020010 8003be4: 40020028 .word 0x40020028 8003be8: 40020040 .word 0x40020040 8003bec: 40020058 .word 0x40020058 8003bf0: 40020070 .word 0x40020070 8003bf4: 40020088 .word 0x40020088 8003bf8: 400200a0 .word 0x400200a0 8003bfc: 400200b8 .word 0x400200b8 8003c00: 40020410 .word 0x40020410 8003c04: 40020428 .word 0x40020428 8003c08: 40020440 .word 0x40020440 8003c0c: 40020458 .word 0x40020458 8003c10: 40020470 .word 0x40020470 8003c14: 40020488 .word 0x40020488 8003c18: 400204a0 .word 0x400204a0 8003c1c: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8003c20: 687b ldr r3, [r7, #4] 8003c22: 681b ldr r3, [r3, #0] 8003c24: 681a ldr r2, [r3, #0] 8003c26: 687b ldr r3, [r7, #4] 8003c28: 681b ldr r3, [r3, #0] 8003c2a: f022 020e bic.w r2, r2, #14 8003c2e: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8003c30: 687b ldr r3, [r7, #4] 8003c32: 681b ldr r3, [r3, #0] 8003c34: 4a6c ldr r2, [pc, #432] @ (8003de8 ) 8003c36: 4293 cmp r3, r2 8003c38: d04a beq.n 8003cd0 8003c3a: 687b ldr r3, [r7, #4] 8003c3c: 681b ldr r3, [r3, #0] 8003c3e: 4a6b ldr r2, [pc, #428] @ (8003dec ) 8003c40: 4293 cmp r3, r2 8003c42: d045 beq.n 8003cd0 8003c44: 687b ldr r3, [r7, #4] 8003c46: 681b ldr r3, [r3, #0] 8003c48: 4a69 ldr r2, [pc, #420] @ (8003df0 ) 8003c4a: 4293 cmp r3, r2 8003c4c: d040 beq.n 8003cd0 8003c4e: 687b ldr r3, [r7, #4] 8003c50: 681b ldr r3, [r3, #0] 8003c52: 4a68 ldr r2, [pc, #416] @ (8003df4 ) 8003c54: 4293 cmp r3, r2 8003c56: d03b beq.n 8003cd0 8003c58: 687b ldr r3, [r7, #4] 8003c5a: 681b ldr r3, [r3, #0] 8003c5c: 4a66 ldr r2, [pc, #408] @ (8003df8 ) 8003c5e: 4293 cmp r3, r2 8003c60: d036 beq.n 8003cd0 8003c62: 687b ldr r3, [r7, #4] 8003c64: 681b ldr r3, [r3, #0] 8003c66: 4a65 ldr r2, [pc, #404] @ (8003dfc ) 8003c68: 4293 cmp r3, r2 8003c6a: d031 beq.n 8003cd0 8003c6c: 687b ldr r3, [r7, #4] 8003c6e: 681b ldr r3, [r3, #0] 8003c70: 4a63 ldr r2, [pc, #396] @ (8003e00 ) 8003c72: 4293 cmp r3, r2 8003c74: d02c beq.n 8003cd0 8003c76: 687b ldr r3, [r7, #4] 8003c78: 681b ldr r3, [r3, #0] 8003c7a: 4a62 ldr r2, [pc, #392] @ (8003e04 ) 8003c7c: 4293 cmp r3, r2 8003c7e: d027 beq.n 8003cd0 8003c80: 687b ldr r3, [r7, #4] 8003c82: 681b ldr r3, [r3, #0] 8003c84: 4a60 ldr r2, [pc, #384] @ (8003e08 ) 8003c86: 4293 cmp r3, r2 8003c88: d022 beq.n 8003cd0 8003c8a: 687b ldr r3, [r7, #4] 8003c8c: 681b ldr r3, [r3, #0] 8003c8e: 4a5f ldr r2, [pc, #380] @ (8003e0c ) 8003c90: 4293 cmp r3, r2 8003c92: d01d beq.n 8003cd0 8003c94: 687b ldr r3, [r7, #4] 8003c96: 681b ldr r3, [r3, #0] 8003c98: 4a5d ldr r2, [pc, #372] @ (8003e10 ) 8003c9a: 4293 cmp r3, r2 8003c9c: d018 beq.n 8003cd0 8003c9e: 687b ldr r3, [r7, #4] 8003ca0: 681b ldr r3, [r3, #0] 8003ca2: 4a5c ldr r2, [pc, #368] @ (8003e14 ) 8003ca4: 4293 cmp r3, r2 8003ca6: d013 beq.n 8003cd0 8003ca8: 687b ldr r3, [r7, #4] 8003caa: 681b ldr r3, [r3, #0] 8003cac: 4a5a ldr r2, [pc, #360] @ (8003e18 ) 8003cae: 4293 cmp r3, r2 8003cb0: d00e beq.n 8003cd0 8003cb2: 687b ldr r3, [r7, #4] 8003cb4: 681b ldr r3, [r3, #0] 8003cb6: 4a59 ldr r2, [pc, #356] @ (8003e1c ) 8003cb8: 4293 cmp r3, r2 8003cba: d009 beq.n 8003cd0 8003cbc: 687b ldr r3, [r7, #4] 8003cbe: 681b ldr r3, [r3, #0] 8003cc0: 4a57 ldr r2, [pc, #348] @ (8003e20 ) 8003cc2: 4293 cmp r3, r2 8003cc4: d004 beq.n 8003cd0 8003cc6: 687b ldr r3, [r7, #4] 8003cc8: 681b ldr r3, [r3, #0] 8003cca: 4a56 ldr r2, [pc, #344] @ (8003e24 ) 8003ccc: 4293 cmp r3, r2 8003cce: d108 bne.n 8003ce2 8003cd0: 687b ldr r3, [r7, #4] 8003cd2: 681b ldr r3, [r3, #0] 8003cd4: 681a ldr r2, [r3, #0] 8003cd6: 687b ldr r3, [r7, #4] 8003cd8: 681b ldr r3, [r3, #0] 8003cda: f022 0201 bic.w r2, r2, #1 8003cde: 601a str r2, [r3, #0] 8003ce0: e007 b.n 8003cf2 8003ce2: 687b ldr r3, [r7, #4] 8003ce4: 681b ldr r3, [r3, #0] 8003ce6: 681a ldr r2, [r3, #0] 8003ce8: 687b ldr r3, [r7, #4] 8003cea: 681b ldr r3, [r3, #0] 8003cec: f022 0201 bic.w r2, r2, #1 8003cf0: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8003cf2: 687b ldr r3, [r7, #4] 8003cf4: 681b ldr r3, [r3, #0] 8003cf6: 4a3c ldr r2, [pc, #240] @ (8003de8 ) 8003cf8: 4293 cmp r3, r2 8003cfa: d072 beq.n 8003de2 8003cfc: 687b ldr r3, [r7, #4] 8003cfe: 681b ldr r3, [r3, #0] 8003d00: 4a3a ldr r2, [pc, #232] @ (8003dec ) 8003d02: 4293 cmp r3, r2 8003d04: d06d beq.n 8003de2 8003d06: 687b ldr r3, [r7, #4] 8003d08: 681b ldr r3, [r3, #0] 8003d0a: 4a39 ldr r2, [pc, #228] @ (8003df0 ) 8003d0c: 4293 cmp r3, r2 8003d0e: d068 beq.n 8003de2 8003d10: 687b ldr r3, [r7, #4] 8003d12: 681b ldr r3, [r3, #0] 8003d14: 4a37 ldr r2, [pc, #220] @ (8003df4 ) 8003d16: 4293 cmp r3, r2 8003d18: d063 beq.n 8003de2 8003d1a: 687b ldr r3, [r7, #4] 8003d1c: 681b ldr r3, [r3, #0] 8003d1e: 4a36 ldr r2, [pc, #216] @ (8003df8 ) 8003d20: 4293 cmp r3, r2 8003d22: d05e beq.n 8003de2 8003d24: 687b ldr r3, [r7, #4] 8003d26: 681b ldr r3, [r3, #0] 8003d28: 4a34 ldr r2, [pc, #208] @ (8003dfc ) 8003d2a: 4293 cmp r3, r2 8003d2c: d059 beq.n 8003de2 8003d2e: 687b ldr r3, [r7, #4] 8003d30: 681b ldr r3, [r3, #0] 8003d32: 4a33 ldr r2, [pc, #204] @ (8003e00 ) 8003d34: 4293 cmp r3, r2 8003d36: d054 beq.n 8003de2 8003d38: 687b ldr r3, [r7, #4] 8003d3a: 681b ldr r3, [r3, #0] 8003d3c: 4a31 ldr r2, [pc, #196] @ (8003e04 ) 8003d3e: 4293 cmp r3, r2 8003d40: d04f beq.n 8003de2 8003d42: 687b ldr r3, [r7, #4] 8003d44: 681b ldr r3, [r3, #0] 8003d46: 4a30 ldr r2, [pc, #192] @ (8003e08 ) 8003d48: 4293 cmp r3, r2 8003d4a: d04a beq.n 8003de2 8003d4c: 687b ldr r3, [r7, #4] 8003d4e: 681b ldr r3, [r3, #0] 8003d50: 4a2e ldr r2, [pc, #184] @ (8003e0c ) 8003d52: 4293 cmp r3, r2 8003d54: d045 beq.n 8003de2 8003d56: 687b ldr r3, [r7, #4] 8003d58: 681b ldr r3, [r3, #0] 8003d5a: 4a2d ldr r2, [pc, #180] @ (8003e10 ) 8003d5c: 4293 cmp r3, r2 8003d5e: d040 beq.n 8003de2 8003d60: 687b ldr r3, [r7, #4] 8003d62: 681b ldr r3, [r3, #0] 8003d64: 4a2b ldr r2, [pc, #172] @ (8003e14 ) 8003d66: 4293 cmp r3, r2 8003d68: d03b beq.n 8003de2 8003d6a: 687b ldr r3, [r7, #4] 8003d6c: 681b ldr r3, [r3, #0] 8003d6e: 4a2a ldr r2, [pc, #168] @ (8003e18 ) 8003d70: 4293 cmp r3, r2 8003d72: d036 beq.n 8003de2 8003d74: 687b ldr r3, [r7, #4] 8003d76: 681b ldr r3, [r3, #0] 8003d78: 4a28 ldr r2, [pc, #160] @ (8003e1c ) 8003d7a: 4293 cmp r3, r2 8003d7c: d031 beq.n 8003de2 8003d7e: 687b ldr r3, [r7, #4] 8003d80: 681b ldr r3, [r3, #0] 8003d82: 4a27 ldr r2, [pc, #156] @ (8003e20 ) 8003d84: 4293 cmp r3, r2 8003d86: d02c beq.n 8003de2 8003d88: 687b ldr r3, [r7, #4] 8003d8a: 681b ldr r3, [r3, #0] 8003d8c: 4a25 ldr r2, [pc, #148] @ (8003e24 ) 8003d8e: 4293 cmp r3, r2 8003d90: d027 beq.n 8003de2 8003d92: 687b ldr r3, [r7, #4] 8003d94: 681b ldr r3, [r3, #0] 8003d96: 4a24 ldr r2, [pc, #144] @ (8003e28 ) 8003d98: 4293 cmp r3, r2 8003d9a: d022 beq.n 8003de2 8003d9c: 687b ldr r3, [r7, #4] 8003d9e: 681b ldr r3, [r3, #0] 8003da0: 4a22 ldr r2, [pc, #136] @ (8003e2c ) 8003da2: 4293 cmp r3, r2 8003da4: d01d beq.n 8003de2 8003da6: 687b ldr r3, [r7, #4] 8003da8: 681b ldr r3, [r3, #0] 8003daa: 4a21 ldr r2, [pc, #132] @ (8003e30 ) 8003dac: 4293 cmp r3, r2 8003dae: d018 beq.n 8003de2 8003db0: 687b ldr r3, [r7, #4] 8003db2: 681b ldr r3, [r3, #0] 8003db4: 4a1f ldr r2, [pc, #124] @ (8003e34 ) 8003db6: 4293 cmp r3, r2 8003db8: d013 beq.n 8003de2 8003dba: 687b ldr r3, [r7, #4] 8003dbc: 681b ldr r3, [r3, #0] 8003dbe: 4a1e ldr r2, [pc, #120] @ (8003e38 ) 8003dc0: 4293 cmp r3, r2 8003dc2: d00e beq.n 8003de2 8003dc4: 687b ldr r3, [r7, #4] 8003dc6: 681b ldr r3, [r3, #0] 8003dc8: 4a1c ldr r2, [pc, #112] @ (8003e3c ) 8003dca: 4293 cmp r3, r2 8003dcc: d009 beq.n 8003de2 8003dce: 687b ldr r3, [r7, #4] 8003dd0: 681b ldr r3, [r3, #0] 8003dd2: 4a1b ldr r2, [pc, #108] @ (8003e40 ) 8003dd4: 4293 cmp r3, r2 8003dd6: d004 beq.n 8003de2 8003dd8: 687b ldr r3, [r7, #4] 8003dda: 681b ldr r3, [r3, #0] 8003ddc: 4a19 ldr r2, [pc, #100] @ (8003e44 ) 8003dde: 4293 cmp r3, r2 8003de0: d132 bne.n 8003e48 8003de2: 2301 movs r3, #1 8003de4: e031 b.n 8003e4a 8003de6: bf00 nop 8003de8: 40020010 .word 0x40020010 8003dec: 40020028 .word 0x40020028 8003df0: 40020040 .word 0x40020040 8003df4: 40020058 .word 0x40020058 8003df8: 40020070 .word 0x40020070 8003dfc: 40020088 .word 0x40020088 8003e00: 400200a0 .word 0x400200a0 8003e04: 400200b8 .word 0x400200b8 8003e08: 40020410 .word 0x40020410 8003e0c: 40020428 .word 0x40020428 8003e10: 40020440 .word 0x40020440 8003e14: 40020458 .word 0x40020458 8003e18: 40020470 .word 0x40020470 8003e1c: 40020488 .word 0x40020488 8003e20: 400204a0 .word 0x400204a0 8003e24: 400204b8 .word 0x400204b8 8003e28: 58025408 .word 0x58025408 8003e2c: 5802541c .word 0x5802541c 8003e30: 58025430 .word 0x58025430 8003e34: 58025444 .word 0x58025444 8003e38: 58025458 .word 0x58025458 8003e3c: 5802546c .word 0x5802546c 8003e40: 58025480 .word 0x58025480 8003e44: 58025494 .word 0x58025494 8003e48: 2300 movs r3, #0 8003e4a: 2b00 cmp r3, #0 8003e4c: d028 beq.n 8003ea0 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8003e4e: 687b ldr r3, [r7, #4] 8003e50: 6e1b ldr r3, [r3, #96] @ 0x60 8003e52: 681a ldr r2, [r3, #0] 8003e54: 687b ldr r3, [r7, #4] 8003e56: 6e1b ldr r3, [r3, #96] @ 0x60 8003e58: f422 7280 bic.w r2, r2, #256 @ 0x100 8003e5c: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8003e5e: 687b ldr r3, [r7, #4] 8003e60: 6d9b ldr r3, [r3, #88] @ 0x58 8003e62: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8003e64: 687b ldr r3, [r7, #4] 8003e66: 6ddb ldr r3, [r3, #92] @ 0x5c 8003e68: f003 031f and.w r3, r3, #31 8003e6c: 2201 movs r2, #1 8003e6e: 409a lsls r2, r3 8003e70: 68fb ldr r3, [r7, #12] 8003e72: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8003e74: 687b ldr r3, [r7, #4] 8003e76: 6e5b ldr r3, [r3, #100] @ 0x64 8003e78: 687a ldr r2, [r7, #4] 8003e7a: 6e92 ldr r2, [r2, #104] @ 0x68 8003e7c: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8003e7e: 687b ldr r3, [r7, #4] 8003e80: 6edb ldr r3, [r3, #108] @ 0x6c 8003e82: 2b00 cmp r3, #0 8003e84: d00c beq.n 8003ea0 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8003e86: 687b ldr r3, [r7, #4] 8003e88: 6edb ldr r3, [r3, #108] @ 0x6c 8003e8a: 681a ldr r2, [r3, #0] 8003e8c: 687b ldr r3, [r7, #4] 8003e8e: 6edb ldr r3, [r3, #108] @ 0x6c 8003e90: f422 7280 bic.w r2, r2, #256 @ 0x100 8003e94: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8003e96: 687b ldr r3, [r7, #4] 8003e98: 6f1b ldr r3, [r3, #112] @ 0x70 8003e9a: 687a ldr r2, [r7, #4] 8003e9c: 6f52 ldr r2, [r2, #116] @ 0x74 8003e9e: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8003ea0: 687b ldr r3, [r7, #4] 8003ea2: 2201 movs r2, #1 8003ea4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8003ea8: 687b ldr r3, [r7, #4] 8003eaa: 2200 movs r2, #0 8003eac: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8003eb0: 687b ldr r3, [r7, #4] 8003eb2: 6d1b ldr r3, [r3, #80] @ 0x50 8003eb4: 2b00 cmp r3, #0 8003eb6: d003 beq.n 8003ec0 { hdma->XferAbortCallback(hdma); 8003eb8: 687b ldr r3, [r7, #4] 8003eba: 6d1b ldr r3, [r3, #80] @ 0x50 8003ebc: 6878 ldr r0, [r7, #4] 8003ebe: 4798 blx r3 } } } return HAL_OK; 8003ec0: 2300 movs r3, #0 } 8003ec2: 4618 mov r0, r3 8003ec4: 3710 adds r7, #16 8003ec6: 46bd mov sp, r7 8003ec8: bd80 pop {r7, pc} 8003eca: bf00 nop 08003ecc : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8003ecc: b580 push {r7, lr} 8003ece: b08a sub sp, #40 @ 0x28 8003ed0: af00 add r7, sp, #0 8003ed2: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8003ed4: 2300 movs r3, #0 8003ed6: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8003ed8: 4b67 ldr r3, [pc, #412] @ (8004078 ) 8003eda: 681b ldr r3, [r3, #0] 8003edc: 4a67 ldr r2, [pc, #412] @ (800407c ) 8003ede: fba2 2303 umull r2, r3, r2, r3 8003ee2: 0a9b lsrs r3, r3, #10 8003ee4: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8003ee6: 687b ldr r3, [r7, #4] 8003ee8: 6d9b ldr r3, [r3, #88] @ 0x58 8003eea: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8003eec: 687b ldr r3, [r7, #4] 8003eee: 6d9b ldr r3, [r3, #88] @ 0x58 8003ef0: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8003ef2: 6a3b ldr r3, [r7, #32] 8003ef4: 681b ldr r3, [r3, #0] 8003ef6: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8003ef8: 69fb ldr r3, [r7, #28] 8003efa: 681b ldr r3, [r3, #0] 8003efc: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8003efe: 687b ldr r3, [r7, #4] 8003f00: 681b ldr r3, [r3, #0] 8003f02: 4a5f ldr r2, [pc, #380] @ (8004080 ) 8003f04: 4293 cmp r3, r2 8003f06: d04a beq.n 8003f9e 8003f08: 687b ldr r3, [r7, #4] 8003f0a: 681b ldr r3, [r3, #0] 8003f0c: 4a5d ldr r2, [pc, #372] @ (8004084 ) 8003f0e: 4293 cmp r3, r2 8003f10: d045 beq.n 8003f9e 8003f12: 687b ldr r3, [r7, #4] 8003f14: 681b ldr r3, [r3, #0] 8003f16: 4a5c ldr r2, [pc, #368] @ (8004088 ) 8003f18: 4293 cmp r3, r2 8003f1a: d040 beq.n 8003f9e 8003f1c: 687b ldr r3, [r7, #4] 8003f1e: 681b ldr r3, [r3, #0] 8003f20: 4a5a ldr r2, [pc, #360] @ (800408c ) 8003f22: 4293 cmp r3, r2 8003f24: d03b beq.n 8003f9e 8003f26: 687b ldr r3, [r7, #4] 8003f28: 681b ldr r3, [r3, #0] 8003f2a: 4a59 ldr r2, [pc, #356] @ (8004090 ) 8003f2c: 4293 cmp r3, r2 8003f2e: d036 beq.n 8003f9e 8003f30: 687b ldr r3, [r7, #4] 8003f32: 681b ldr r3, [r3, #0] 8003f34: 4a57 ldr r2, [pc, #348] @ (8004094 ) 8003f36: 4293 cmp r3, r2 8003f38: d031 beq.n 8003f9e 8003f3a: 687b ldr r3, [r7, #4] 8003f3c: 681b ldr r3, [r3, #0] 8003f3e: 4a56 ldr r2, [pc, #344] @ (8004098 ) 8003f40: 4293 cmp r3, r2 8003f42: d02c beq.n 8003f9e 8003f44: 687b ldr r3, [r7, #4] 8003f46: 681b ldr r3, [r3, #0] 8003f48: 4a54 ldr r2, [pc, #336] @ (800409c ) 8003f4a: 4293 cmp r3, r2 8003f4c: d027 beq.n 8003f9e 8003f4e: 687b ldr r3, [r7, #4] 8003f50: 681b ldr r3, [r3, #0] 8003f52: 4a53 ldr r2, [pc, #332] @ (80040a0 ) 8003f54: 4293 cmp r3, r2 8003f56: d022 beq.n 8003f9e 8003f58: 687b ldr r3, [r7, #4] 8003f5a: 681b ldr r3, [r3, #0] 8003f5c: 4a51 ldr r2, [pc, #324] @ (80040a4 ) 8003f5e: 4293 cmp r3, r2 8003f60: d01d beq.n 8003f9e 8003f62: 687b ldr r3, [r7, #4] 8003f64: 681b ldr r3, [r3, #0] 8003f66: 4a50 ldr r2, [pc, #320] @ (80040a8 ) 8003f68: 4293 cmp r3, r2 8003f6a: d018 beq.n 8003f9e 8003f6c: 687b ldr r3, [r7, #4] 8003f6e: 681b ldr r3, [r3, #0] 8003f70: 4a4e ldr r2, [pc, #312] @ (80040ac ) 8003f72: 4293 cmp r3, r2 8003f74: d013 beq.n 8003f9e 8003f76: 687b ldr r3, [r7, #4] 8003f78: 681b ldr r3, [r3, #0] 8003f7a: 4a4d ldr r2, [pc, #308] @ (80040b0 ) 8003f7c: 4293 cmp r3, r2 8003f7e: d00e beq.n 8003f9e 8003f80: 687b ldr r3, [r7, #4] 8003f82: 681b ldr r3, [r3, #0] 8003f84: 4a4b ldr r2, [pc, #300] @ (80040b4 ) 8003f86: 4293 cmp r3, r2 8003f88: d009 beq.n 8003f9e 8003f8a: 687b ldr r3, [r7, #4] 8003f8c: 681b ldr r3, [r3, #0] 8003f8e: 4a4a ldr r2, [pc, #296] @ (80040b8 ) 8003f90: 4293 cmp r3, r2 8003f92: d004 beq.n 8003f9e 8003f94: 687b ldr r3, [r7, #4] 8003f96: 681b ldr r3, [r3, #0] 8003f98: 4a48 ldr r2, [pc, #288] @ (80040bc ) 8003f9a: 4293 cmp r3, r2 8003f9c: d101 bne.n 8003fa2 8003f9e: 2301 movs r3, #1 8003fa0: e000 b.n 8003fa4 8003fa2: 2300 movs r3, #0 8003fa4: 2b00 cmp r3, #0 8003fa6: f000 842b beq.w 8004800 { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8003faa: 687b ldr r3, [r7, #4] 8003fac: 6ddb ldr r3, [r3, #92] @ 0x5c 8003fae: f003 031f and.w r3, r3, #31 8003fb2: 2208 movs r2, #8 8003fb4: 409a lsls r2, r3 8003fb6: 69bb ldr r3, [r7, #24] 8003fb8: 4013 ands r3, r2 8003fba: 2b00 cmp r3, #0 8003fbc: f000 80a2 beq.w 8004104 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8003fc0: 687b ldr r3, [r7, #4] 8003fc2: 681b ldr r3, [r3, #0] 8003fc4: 4a2e ldr r2, [pc, #184] @ (8004080 ) 8003fc6: 4293 cmp r3, r2 8003fc8: d04a beq.n 8004060 8003fca: 687b ldr r3, [r7, #4] 8003fcc: 681b ldr r3, [r3, #0] 8003fce: 4a2d ldr r2, [pc, #180] @ (8004084 ) 8003fd0: 4293 cmp r3, r2 8003fd2: d045 beq.n 8004060 8003fd4: 687b ldr r3, [r7, #4] 8003fd6: 681b ldr r3, [r3, #0] 8003fd8: 4a2b ldr r2, [pc, #172] @ (8004088 ) 8003fda: 4293 cmp r3, r2 8003fdc: d040 beq.n 8004060 8003fde: 687b ldr r3, [r7, #4] 8003fe0: 681b ldr r3, [r3, #0] 8003fe2: 4a2a ldr r2, [pc, #168] @ (800408c ) 8003fe4: 4293 cmp r3, r2 8003fe6: d03b beq.n 8004060 8003fe8: 687b ldr r3, [r7, #4] 8003fea: 681b ldr r3, [r3, #0] 8003fec: 4a28 ldr r2, [pc, #160] @ (8004090 ) 8003fee: 4293 cmp r3, r2 8003ff0: d036 beq.n 8004060 8003ff2: 687b ldr r3, [r7, #4] 8003ff4: 681b ldr r3, [r3, #0] 8003ff6: 4a27 ldr r2, [pc, #156] @ (8004094 ) 8003ff8: 4293 cmp r3, r2 8003ffa: d031 beq.n 8004060 8003ffc: 687b ldr r3, [r7, #4] 8003ffe: 681b ldr r3, [r3, #0] 8004000: 4a25 ldr r2, [pc, #148] @ (8004098 ) 8004002: 4293 cmp r3, r2 8004004: d02c beq.n 8004060 8004006: 687b ldr r3, [r7, #4] 8004008: 681b ldr r3, [r3, #0] 800400a: 4a24 ldr r2, [pc, #144] @ (800409c ) 800400c: 4293 cmp r3, r2 800400e: d027 beq.n 8004060 8004010: 687b ldr r3, [r7, #4] 8004012: 681b ldr r3, [r3, #0] 8004014: 4a22 ldr r2, [pc, #136] @ (80040a0 ) 8004016: 4293 cmp r3, r2 8004018: d022 beq.n 8004060 800401a: 687b ldr r3, [r7, #4] 800401c: 681b ldr r3, [r3, #0] 800401e: 4a21 ldr r2, [pc, #132] @ (80040a4 ) 8004020: 4293 cmp r3, r2 8004022: d01d beq.n 8004060 8004024: 687b ldr r3, [r7, #4] 8004026: 681b ldr r3, [r3, #0] 8004028: 4a1f ldr r2, [pc, #124] @ (80040a8 ) 800402a: 4293 cmp r3, r2 800402c: d018 beq.n 8004060 800402e: 687b ldr r3, [r7, #4] 8004030: 681b ldr r3, [r3, #0] 8004032: 4a1e ldr r2, [pc, #120] @ (80040ac ) 8004034: 4293 cmp r3, r2 8004036: d013 beq.n 8004060 8004038: 687b ldr r3, [r7, #4] 800403a: 681b ldr r3, [r3, #0] 800403c: 4a1c ldr r2, [pc, #112] @ (80040b0 ) 800403e: 4293 cmp r3, r2 8004040: d00e beq.n 8004060 8004042: 687b ldr r3, [r7, #4] 8004044: 681b ldr r3, [r3, #0] 8004046: 4a1b ldr r2, [pc, #108] @ (80040b4 ) 8004048: 4293 cmp r3, r2 800404a: d009 beq.n 8004060 800404c: 687b ldr r3, [r7, #4] 800404e: 681b ldr r3, [r3, #0] 8004050: 4a19 ldr r2, [pc, #100] @ (80040b8 ) 8004052: 4293 cmp r3, r2 8004054: d004 beq.n 8004060 8004056: 687b ldr r3, [r7, #4] 8004058: 681b ldr r3, [r3, #0] 800405a: 4a18 ldr r2, [pc, #96] @ (80040bc ) 800405c: 4293 cmp r3, r2 800405e: d12f bne.n 80040c0 8004060: 687b ldr r3, [r7, #4] 8004062: 681b ldr r3, [r3, #0] 8004064: 681b ldr r3, [r3, #0] 8004066: f003 0304 and.w r3, r3, #4 800406a: 2b00 cmp r3, #0 800406c: bf14 ite ne 800406e: 2301 movne r3, #1 8004070: 2300 moveq r3, #0 8004072: b2db uxtb r3, r3 8004074: e02e b.n 80040d4 8004076: bf00 nop 8004078: 24000000 .word 0x24000000 800407c: 1b4e81b5 .word 0x1b4e81b5 8004080: 40020010 .word 0x40020010 8004084: 40020028 .word 0x40020028 8004088: 40020040 .word 0x40020040 800408c: 40020058 .word 0x40020058 8004090: 40020070 .word 0x40020070 8004094: 40020088 .word 0x40020088 8004098: 400200a0 .word 0x400200a0 800409c: 400200b8 .word 0x400200b8 80040a0: 40020410 .word 0x40020410 80040a4: 40020428 .word 0x40020428 80040a8: 40020440 .word 0x40020440 80040ac: 40020458 .word 0x40020458 80040b0: 40020470 .word 0x40020470 80040b4: 40020488 .word 0x40020488 80040b8: 400204a0 .word 0x400204a0 80040bc: 400204b8 .word 0x400204b8 80040c0: 687b ldr r3, [r7, #4] 80040c2: 681b ldr r3, [r3, #0] 80040c4: 681b ldr r3, [r3, #0] 80040c6: f003 0308 and.w r3, r3, #8 80040ca: 2b00 cmp r3, #0 80040cc: bf14 ite ne 80040ce: 2301 movne r3, #1 80040d0: 2300 moveq r3, #0 80040d2: b2db uxtb r3, r3 80040d4: 2b00 cmp r3, #0 80040d6: d015 beq.n 8004104 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 80040d8: 687b ldr r3, [r7, #4] 80040da: 681b ldr r3, [r3, #0] 80040dc: 681a ldr r2, [r3, #0] 80040de: 687b ldr r3, [r7, #4] 80040e0: 681b ldr r3, [r3, #0] 80040e2: f022 0204 bic.w r2, r2, #4 80040e6: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 80040e8: 687b ldr r3, [r7, #4] 80040ea: 6ddb ldr r3, [r3, #92] @ 0x5c 80040ec: f003 031f and.w r3, r3, #31 80040f0: 2208 movs r2, #8 80040f2: 409a lsls r2, r3 80040f4: 6a3b ldr r3, [r7, #32] 80040f6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 80040f8: 687b ldr r3, [r7, #4] 80040fa: 6d5b ldr r3, [r3, #84] @ 0x54 80040fc: f043 0201 orr.w r2, r3, #1 8004100: 687b ldr r3, [r7, #4] 8004102: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8004104: 687b ldr r3, [r7, #4] 8004106: 6ddb ldr r3, [r3, #92] @ 0x5c 8004108: f003 031f and.w r3, r3, #31 800410c: 69ba ldr r2, [r7, #24] 800410e: fa22 f303 lsr.w r3, r2, r3 8004112: f003 0301 and.w r3, r3, #1 8004116: 2b00 cmp r3, #0 8004118: d06e beq.n 80041f8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 800411a: 687b ldr r3, [r7, #4] 800411c: 681b ldr r3, [r3, #0] 800411e: 4a69 ldr r2, [pc, #420] @ (80042c4 ) 8004120: 4293 cmp r3, r2 8004122: d04a beq.n 80041ba 8004124: 687b ldr r3, [r7, #4] 8004126: 681b ldr r3, [r3, #0] 8004128: 4a67 ldr r2, [pc, #412] @ (80042c8 ) 800412a: 4293 cmp r3, r2 800412c: d045 beq.n 80041ba 800412e: 687b ldr r3, [r7, #4] 8004130: 681b ldr r3, [r3, #0] 8004132: 4a66 ldr r2, [pc, #408] @ (80042cc ) 8004134: 4293 cmp r3, r2 8004136: d040 beq.n 80041ba 8004138: 687b ldr r3, [r7, #4] 800413a: 681b ldr r3, [r3, #0] 800413c: 4a64 ldr r2, [pc, #400] @ (80042d0 ) 800413e: 4293 cmp r3, r2 8004140: d03b beq.n 80041ba 8004142: 687b ldr r3, [r7, #4] 8004144: 681b ldr r3, [r3, #0] 8004146: 4a63 ldr r2, [pc, #396] @ (80042d4 ) 8004148: 4293 cmp r3, r2 800414a: d036 beq.n 80041ba 800414c: 687b ldr r3, [r7, #4] 800414e: 681b ldr r3, [r3, #0] 8004150: 4a61 ldr r2, [pc, #388] @ (80042d8 ) 8004152: 4293 cmp r3, r2 8004154: d031 beq.n 80041ba 8004156: 687b ldr r3, [r7, #4] 8004158: 681b ldr r3, [r3, #0] 800415a: 4a60 ldr r2, [pc, #384] @ (80042dc ) 800415c: 4293 cmp r3, r2 800415e: d02c beq.n 80041ba 8004160: 687b ldr r3, [r7, #4] 8004162: 681b ldr r3, [r3, #0] 8004164: 4a5e ldr r2, [pc, #376] @ (80042e0 ) 8004166: 4293 cmp r3, r2 8004168: d027 beq.n 80041ba 800416a: 687b ldr r3, [r7, #4] 800416c: 681b ldr r3, [r3, #0] 800416e: 4a5d ldr r2, [pc, #372] @ (80042e4 ) 8004170: 4293 cmp r3, r2 8004172: d022 beq.n 80041ba 8004174: 687b ldr r3, [r7, #4] 8004176: 681b ldr r3, [r3, #0] 8004178: 4a5b ldr r2, [pc, #364] @ (80042e8 ) 800417a: 4293 cmp r3, r2 800417c: d01d beq.n 80041ba 800417e: 687b ldr r3, [r7, #4] 8004180: 681b ldr r3, [r3, #0] 8004182: 4a5a ldr r2, [pc, #360] @ (80042ec ) 8004184: 4293 cmp r3, r2 8004186: d018 beq.n 80041ba 8004188: 687b ldr r3, [r7, #4] 800418a: 681b ldr r3, [r3, #0] 800418c: 4a58 ldr r2, [pc, #352] @ (80042f0 ) 800418e: 4293 cmp r3, r2 8004190: d013 beq.n 80041ba 8004192: 687b ldr r3, [r7, #4] 8004194: 681b ldr r3, [r3, #0] 8004196: 4a57 ldr r2, [pc, #348] @ (80042f4 ) 8004198: 4293 cmp r3, r2 800419a: d00e beq.n 80041ba 800419c: 687b ldr r3, [r7, #4] 800419e: 681b ldr r3, [r3, #0] 80041a0: 4a55 ldr r2, [pc, #340] @ (80042f8 ) 80041a2: 4293 cmp r3, r2 80041a4: d009 beq.n 80041ba 80041a6: 687b ldr r3, [r7, #4] 80041a8: 681b ldr r3, [r3, #0] 80041aa: 4a54 ldr r2, [pc, #336] @ (80042fc ) 80041ac: 4293 cmp r3, r2 80041ae: d004 beq.n 80041ba 80041b0: 687b ldr r3, [r7, #4] 80041b2: 681b ldr r3, [r3, #0] 80041b4: 4a52 ldr r2, [pc, #328] @ (8004300 ) 80041b6: 4293 cmp r3, r2 80041b8: d10a bne.n 80041d0 80041ba: 687b ldr r3, [r7, #4] 80041bc: 681b ldr r3, [r3, #0] 80041be: 695b ldr r3, [r3, #20] 80041c0: f003 0380 and.w r3, r3, #128 @ 0x80 80041c4: 2b00 cmp r3, #0 80041c6: bf14 ite ne 80041c8: 2301 movne r3, #1 80041ca: 2300 moveq r3, #0 80041cc: b2db uxtb r3, r3 80041ce: e003 b.n 80041d8 80041d0: 687b ldr r3, [r7, #4] 80041d2: 681b ldr r3, [r3, #0] 80041d4: 681b ldr r3, [r3, #0] 80041d6: 2300 movs r3, #0 80041d8: 2b00 cmp r3, #0 80041da: d00d beq.n 80041f8 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 80041dc: 687b ldr r3, [r7, #4] 80041de: 6ddb ldr r3, [r3, #92] @ 0x5c 80041e0: f003 031f and.w r3, r3, #31 80041e4: 2201 movs r2, #1 80041e6: 409a lsls r2, r3 80041e8: 6a3b ldr r3, [r7, #32] 80041ea: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 80041ec: 687b ldr r3, [r7, #4] 80041ee: 6d5b ldr r3, [r3, #84] @ 0x54 80041f0: f043 0202 orr.w r2, r3, #2 80041f4: 687b ldr r3, [r7, #4] 80041f6: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80041f8: 687b ldr r3, [r7, #4] 80041fa: 6ddb ldr r3, [r3, #92] @ 0x5c 80041fc: f003 031f and.w r3, r3, #31 8004200: 2204 movs r2, #4 8004202: 409a lsls r2, r3 8004204: 69bb ldr r3, [r7, #24] 8004206: 4013 ands r3, r2 8004208: 2b00 cmp r3, #0 800420a: f000 808f beq.w 800432c { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 800420e: 687b ldr r3, [r7, #4] 8004210: 681b ldr r3, [r3, #0] 8004212: 4a2c ldr r2, [pc, #176] @ (80042c4 ) 8004214: 4293 cmp r3, r2 8004216: d04a beq.n 80042ae 8004218: 687b ldr r3, [r7, #4] 800421a: 681b ldr r3, [r3, #0] 800421c: 4a2a ldr r2, [pc, #168] @ (80042c8 ) 800421e: 4293 cmp r3, r2 8004220: d045 beq.n 80042ae 8004222: 687b ldr r3, [r7, #4] 8004224: 681b ldr r3, [r3, #0] 8004226: 4a29 ldr r2, [pc, #164] @ (80042cc ) 8004228: 4293 cmp r3, r2 800422a: d040 beq.n 80042ae 800422c: 687b ldr r3, [r7, #4] 800422e: 681b ldr r3, [r3, #0] 8004230: 4a27 ldr r2, [pc, #156] @ (80042d0 ) 8004232: 4293 cmp r3, r2 8004234: d03b beq.n 80042ae 8004236: 687b ldr r3, [r7, #4] 8004238: 681b ldr r3, [r3, #0] 800423a: 4a26 ldr r2, [pc, #152] @ (80042d4 ) 800423c: 4293 cmp r3, r2 800423e: d036 beq.n 80042ae 8004240: 687b ldr r3, [r7, #4] 8004242: 681b ldr r3, [r3, #0] 8004244: 4a24 ldr r2, [pc, #144] @ (80042d8 ) 8004246: 4293 cmp r3, r2 8004248: d031 beq.n 80042ae 800424a: 687b ldr r3, [r7, #4] 800424c: 681b ldr r3, [r3, #0] 800424e: 4a23 ldr r2, [pc, #140] @ (80042dc ) 8004250: 4293 cmp r3, r2 8004252: d02c beq.n 80042ae 8004254: 687b ldr r3, [r7, #4] 8004256: 681b ldr r3, [r3, #0] 8004258: 4a21 ldr r2, [pc, #132] @ (80042e0 ) 800425a: 4293 cmp r3, r2 800425c: d027 beq.n 80042ae 800425e: 687b ldr r3, [r7, #4] 8004260: 681b ldr r3, [r3, #0] 8004262: 4a20 ldr r2, [pc, #128] @ (80042e4 ) 8004264: 4293 cmp r3, r2 8004266: d022 beq.n 80042ae 8004268: 687b ldr r3, [r7, #4] 800426a: 681b ldr r3, [r3, #0] 800426c: 4a1e ldr r2, [pc, #120] @ (80042e8 ) 800426e: 4293 cmp r3, r2 8004270: d01d beq.n 80042ae 8004272: 687b ldr r3, [r7, #4] 8004274: 681b ldr r3, [r3, #0] 8004276: 4a1d ldr r2, [pc, #116] @ (80042ec ) 8004278: 4293 cmp r3, r2 800427a: d018 beq.n 80042ae 800427c: 687b ldr r3, [r7, #4] 800427e: 681b ldr r3, [r3, #0] 8004280: 4a1b ldr r2, [pc, #108] @ (80042f0 ) 8004282: 4293 cmp r3, r2 8004284: d013 beq.n 80042ae 8004286: 687b ldr r3, [r7, #4] 8004288: 681b ldr r3, [r3, #0] 800428a: 4a1a ldr r2, [pc, #104] @ (80042f4 ) 800428c: 4293 cmp r3, r2 800428e: d00e beq.n 80042ae 8004290: 687b ldr r3, [r7, #4] 8004292: 681b ldr r3, [r3, #0] 8004294: 4a18 ldr r2, [pc, #96] @ (80042f8 ) 8004296: 4293 cmp r3, r2 8004298: d009 beq.n 80042ae 800429a: 687b ldr r3, [r7, #4] 800429c: 681b ldr r3, [r3, #0] 800429e: 4a17 ldr r2, [pc, #92] @ (80042fc ) 80042a0: 4293 cmp r3, r2 80042a2: d004 beq.n 80042ae 80042a4: 687b ldr r3, [r7, #4] 80042a6: 681b ldr r3, [r3, #0] 80042a8: 4a15 ldr r2, [pc, #84] @ (8004300 ) 80042aa: 4293 cmp r3, r2 80042ac: d12a bne.n 8004304 80042ae: 687b ldr r3, [r7, #4] 80042b0: 681b ldr r3, [r3, #0] 80042b2: 681b ldr r3, [r3, #0] 80042b4: f003 0302 and.w r3, r3, #2 80042b8: 2b00 cmp r3, #0 80042ba: bf14 ite ne 80042bc: 2301 movne r3, #1 80042be: 2300 moveq r3, #0 80042c0: b2db uxtb r3, r3 80042c2: e023 b.n 800430c 80042c4: 40020010 .word 0x40020010 80042c8: 40020028 .word 0x40020028 80042cc: 40020040 .word 0x40020040 80042d0: 40020058 .word 0x40020058 80042d4: 40020070 .word 0x40020070 80042d8: 40020088 .word 0x40020088 80042dc: 400200a0 .word 0x400200a0 80042e0: 400200b8 .word 0x400200b8 80042e4: 40020410 .word 0x40020410 80042e8: 40020428 .word 0x40020428 80042ec: 40020440 .word 0x40020440 80042f0: 40020458 .word 0x40020458 80042f4: 40020470 .word 0x40020470 80042f8: 40020488 .word 0x40020488 80042fc: 400204a0 .word 0x400204a0 8004300: 400204b8 .word 0x400204b8 8004304: 687b ldr r3, [r7, #4] 8004306: 681b ldr r3, [r3, #0] 8004308: 681b ldr r3, [r3, #0] 800430a: 2300 movs r3, #0 800430c: 2b00 cmp r3, #0 800430e: d00d beq.n 800432c { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8004310: 687b ldr r3, [r7, #4] 8004312: 6ddb ldr r3, [r3, #92] @ 0x5c 8004314: f003 031f and.w r3, r3, #31 8004318: 2204 movs r2, #4 800431a: 409a lsls r2, r3 800431c: 6a3b ldr r3, [r7, #32] 800431e: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8004320: 687b ldr r3, [r7, #4] 8004322: 6d5b ldr r3, [r3, #84] @ 0x54 8004324: f043 0204 orr.w r2, r3, #4 8004328: 687b ldr r3, [r7, #4] 800432a: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800432c: 687b ldr r3, [r7, #4] 800432e: 6ddb ldr r3, [r3, #92] @ 0x5c 8004330: f003 031f and.w r3, r3, #31 8004334: 2210 movs r2, #16 8004336: 409a lsls r2, r3 8004338: 69bb ldr r3, [r7, #24] 800433a: 4013 ands r3, r2 800433c: 2b00 cmp r3, #0 800433e: f000 80a6 beq.w 800448e { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 8004342: 687b ldr r3, [r7, #4] 8004344: 681b ldr r3, [r3, #0] 8004346: 4a85 ldr r2, [pc, #532] @ (800455c ) 8004348: 4293 cmp r3, r2 800434a: d04a beq.n 80043e2 800434c: 687b ldr r3, [r7, #4] 800434e: 681b ldr r3, [r3, #0] 8004350: 4a83 ldr r2, [pc, #524] @ (8004560 ) 8004352: 4293 cmp r3, r2 8004354: d045 beq.n 80043e2 8004356: 687b ldr r3, [r7, #4] 8004358: 681b ldr r3, [r3, #0] 800435a: 4a82 ldr r2, [pc, #520] @ (8004564 ) 800435c: 4293 cmp r3, r2 800435e: d040 beq.n 80043e2 8004360: 687b ldr r3, [r7, #4] 8004362: 681b ldr r3, [r3, #0] 8004364: 4a80 ldr r2, [pc, #512] @ (8004568 ) 8004366: 4293 cmp r3, r2 8004368: d03b beq.n 80043e2 800436a: 687b ldr r3, [r7, #4] 800436c: 681b ldr r3, [r3, #0] 800436e: 4a7f ldr r2, [pc, #508] @ (800456c ) 8004370: 4293 cmp r3, r2 8004372: d036 beq.n 80043e2 8004374: 687b ldr r3, [r7, #4] 8004376: 681b ldr r3, [r3, #0] 8004378: 4a7d ldr r2, [pc, #500] @ (8004570 ) 800437a: 4293 cmp r3, r2 800437c: d031 beq.n 80043e2 800437e: 687b ldr r3, [r7, #4] 8004380: 681b ldr r3, [r3, #0] 8004382: 4a7c ldr r2, [pc, #496] @ (8004574 ) 8004384: 4293 cmp r3, r2 8004386: d02c beq.n 80043e2 8004388: 687b ldr r3, [r7, #4] 800438a: 681b ldr r3, [r3, #0] 800438c: 4a7a ldr r2, [pc, #488] @ (8004578 ) 800438e: 4293 cmp r3, r2 8004390: d027 beq.n 80043e2 8004392: 687b ldr r3, [r7, #4] 8004394: 681b ldr r3, [r3, #0] 8004396: 4a79 ldr r2, [pc, #484] @ (800457c ) 8004398: 4293 cmp r3, r2 800439a: d022 beq.n 80043e2 800439c: 687b ldr r3, [r7, #4] 800439e: 681b ldr r3, [r3, #0] 80043a0: 4a77 ldr r2, [pc, #476] @ (8004580 ) 80043a2: 4293 cmp r3, r2 80043a4: d01d beq.n 80043e2 80043a6: 687b ldr r3, [r7, #4] 80043a8: 681b ldr r3, [r3, #0] 80043aa: 4a76 ldr r2, [pc, #472] @ (8004584 ) 80043ac: 4293 cmp r3, r2 80043ae: d018 beq.n 80043e2 80043b0: 687b ldr r3, [r7, #4] 80043b2: 681b ldr r3, [r3, #0] 80043b4: 4a74 ldr r2, [pc, #464] @ (8004588 ) 80043b6: 4293 cmp r3, r2 80043b8: d013 beq.n 80043e2 80043ba: 687b ldr r3, [r7, #4] 80043bc: 681b ldr r3, [r3, #0] 80043be: 4a73 ldr r2, [pc, #460] @ (800458c ) 80043c0: 4293 cmp r3, r2 80043c2: d00e beq.n 80043e2 80043c4: 687b ldr r3, [r7, #4] 80043c6: 681b ldr r3, [r3, #0] 80043c8: 4a71 ldr r2, [pc, #452] @ (8004590 ) 80043ca: 4293 cmp r3, r2 80043cc: d009 beq.n 80043e2 80043ce: 687b ldr r3, [r7, #4] 80043d0: 681b ldr r3, [r3, #0] 80043d2: 4a70 ldr r2, [pc, #448] @ (8004594 ) 80043d4: 4293 cmp r3, r2 80043d6: d004 beq.n 80043e2 80043d8: 687b ldr r3, [r7, #4] 80043da: 681b ldr r3, [r3, #0] 80043dc: 4a6e ldr r2, [pc, #440] @ (8004598 ) 80043de: 4293 cmp r3, r2 80043e0: d10a bne.n 80043f8 80043e2: 687b ldr r3, [r7, #4] 80043e4: 681b ldr r3, [r3, #0] 80043e6: 681b ldr r3, [r3, #0] 80043e8: f003 0308 and.w r3, r3, #8 80043ec: 2b00 cmp r3, #0 80043ee: bf14 ite ne 80043f0: 2301 movne r3, #1 80043f2: 2300 moveq r3, #0 80043f4: b2db uxtb r3, r3 80043f6: e009 b.n 800440c 80043f8: 687b ldr r3, [r7, #4] 80043fa: 681b ldr r3, [r3, #0] 80043fc: 681b ldr r3, [r3, #0] 80043fe: f003 0304 and.w r3, r3, #4 8004402: 2b00 cmp r3, #0 8004404: bf14 ite ne 8004406: 2301 movne r3, #1 8004408: 2300 moveq r3, #0 800440a: b2db uxtb r3, r3 800440c: 2b00 cmp r3, #0 800440e: d03e beq.n 800448e { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 8004410: 687b ldr r3, [r7, #4] 8004412: 6ddb ldr r3, [r3, #92] @ 0x5c 8004414: f003 031f and.w r3, r3, #31 8004418: 2210 movs r2, #16 800441a: 409a lsls r2, r3 800441c: 6a3b ldr r3, [r7, #32] 800441e: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8004420: 687b ldr r3, [r7, #4] 8004422: 681b ldr r3, [r3, #0] 8004424: 681b ldr r3, [r3, #0] 8004426: f403 2380 and.w r3, r3, #262144 @ 0x40000 800442a: 2b00 cmp r3, #0 800442c: d018 beq.n 8004460 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800442e: 687b ldr r3, [r7, #4] 8004430: 681b ldr r3, [r3, #0] 8004432: 681b ldr r3, [r3, #0] 8004434: f403 2300 and.w r3, r3, #524288 @ 0x80000 8004438: 2b00 cmp r3, #0 800443a: d108 bne.n 800444e { if(hdma->XferHalfCpltCallback != NULL) 800443c: 687b ldr r3, [r7, #4] 800443e: 6c1b ldr r3, [r3, #64] @ 0x40 8004440: 2b00 cmp r3, #0 8004442: d024 beq.n 800448e { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8004444: 687b ldr r3, [r7, #4] 8004446: 6c1b ldr r3, [r3, #64] @ 0x40 8004448: 6878 ldr r0, [r7, #4] 800444a: 4798 blx r3 800444c: e01f b.n 800448e } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800444e: 687b ldr r3, [r7, #4] 8004450: 6c9b ldr r3, [r3, #72] @ 0x48 8004452: 2b00 cmp r3, #0 8004454: d01b beq.n 800448e { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 8004456: 687b ldr r3, [r7, #4] 8004458: 6c9b ldr r3, [r3, #72] @ 0x48 800445a: 6878 ldr r0, [r7, #4] 800445c: 4798 blx r3 800445e: e016 b.n 800448e } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8004460: 687b ldr r3, [r7, #4] 8004462: 681b ldr r3, [r3, #0] 8004464: 681b ldr r3, [r3, #0] 8004466: f403 7380 and.w r3, r3, #256 @ 0x100 800446a: 2b00 cmp r3, #0 800446c: d107 bne.n 800447e { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800446e: 687b ldr r3, [r7, #4] 8004470: 681b ldr r3, [r3, #0] 8004472: 681a ldr r2, [r3, #0] 8004474: 687b ldr r3, [r7, #4] 8004476: 681b ldr r3, [r3, #0] 8004478: f022 0208 bic.w r2, r2, #8 800447c: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800447e: 687b ldr r3, [r7, #4] 8004480: 6c1b ldr r3, [r3, #64] @ 0x40 8004482: 2b00 cmp r3, #0 8004484: d003 beq.n 800448e { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8004486: 687b ldr r3, [r7, #4] 8004488: 6c1b ldr r3, [r3, #64] @ 0x40 800448a: 6878 ldr r0, [r7, #4] 800448c: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800448e: 687b ldr r3, [r7, #4] 8004490: 6ddb ldr r3, [r3, #92] @ 0x5c 8004492: f003 031f and.w r3, r3, #31 8004496: 2220 movs r2, #32 8004498: 409a lsls r2, r3 800449a: 69bb ldr r3, [r7, #24] 800449c: 4013 ands r3, r2 800449e: 2b00 cmp r3, #0 80044a0: f000 8110 beq.w 80046c4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 80044a4: 687b ldr r3, [r7, #4] 80044a6: 681b ldr r3, [r3, #0] 80044a8: 4a2c ldr r2, [pc, #176] @ (800455c ) 80044aa: 4293 cmp r3, r2 80044ac: d04a beq.n 8004544 80044ae: 687b ldr r3, [r7, #4] 80044b0: 681b ldr r3, [r3, #0] 80044b2: 4a2b ldr r2, [pc, #172] @ (8004560 ) 80044b4: 4293 cmp r3, r2 80044b6: d045 beq.n 8004544 80044b8: 687b ldr r3, [r7, #4] 80044ba: 681b ldr r3, [r3, #0] 80044bc: 4a29 ldr r2, [pc, #164] @ (8004564 ) 80044be: 4293 cmp r3, r2 80044c0: d040 beq.n 8004544 80044c2: 687b ldr r3, [r7, #4] 80044c4: 681b ldr r3, [r3, #0] 80044c6: 4a28 ldr r2, [pc, #160] @ (8004568 ) 80044c8: 4293 cmp r3, r2 80044ca: d03b beq.n 8004544 80044cc: 687b ldr r3, [r7, #4] 80044ce: 681b ldr r3, [r3, #0] 80044d0: 4a26 ldr r2, [pc, #152] @ (800456c ) 80044d2: 4293 cmp r3, r2 80044d4: d036 beq.n 8004544 80044d6: 687b ldr r3, [r7, #4] 80044d8: 681b ldr r3, [r3, #0] 80044da: 4a25 ldr r2, [pc, #148] @ (8004570 ) 80044dc: 4293 cmp r3, r2 80044de: d031 beq.n 8004544 80044e0: 687b ldr r3, [r7, #4] 80044e2: 681b ldr r3, [r3, #0] 80044e4: 4a23 ldr r2, [pc, #140] @ (8004574 ) 80044e6: 4293 cmp r3, r2 80044e8: d02c beq.n 8004544 80044ea: 687b ldr r3, [r7, #4] 80044ec: 681b ldr r3, [r3, #0] 80044ee: 4a22 ldr r2, [pc, #136] @ (8004578 ) 80044f0: 4293 cmp r3, r2 80044f2: d027 beq.n 8004544 80044f4: 687b ldr r3, [r7, #4] 80044f6: 681b ldr r3, [r3, #0] 80044f8: 4a20 ldr r2, [pc, #128] @ (800457c ) 80044fa: 4293 cmp r3, r2 80044fc: d022 beq.n 8004544 80044fe: 687b ldr r3, [r7, #4] 8004500: 681b ldr r3, [r3, #0] 8004502: 4a1f ldr r2, [pc, #124] @ (8004580 ) 8004504: 4293 cmp r3, r2 8004506: d01d beq.n 8004544 8004508: 687b ldr r3, [r7, #4] 800450a: 681b ldr r3, [r3, #0] 800450c: 4a1d ldr r2, [pc, #116] @ (8004584 ) 800450e: 4293 cmp r3, r2 8004510: d018 beq.n 8004544 8004512: 687b ldr r3, [r7, #4] 8004514: 681b ldr r3, [r3, #0] 8004516: 4a1c ldr r2, [pc, #112] @ (8004588 ) 8004518: 4293 cmp r3, r2 800451a: d013 beq.n 8004544 800451c: 687b ldr r3, [r7, #4] 800451e: 681b ldr r3, [r3, #0] 8004520: 4a1a ldr r2, [pc, #104] @ (800458c ) 8004522: 4293 cmp r3, r2 8004524: d00e beq.n 8004544 8004526: 687b ldr r3, [r7, #4] 8004528: 681b ldr r3, [r3, #0] 800452a: 4a19 ldr r2, [pc, #100] @ (8004590 ) 800452c: 4293 cmp r3, r2 800452e: d009 beq.n 8004544 8004530: 687b ldr r3, [r7, #4] 8004532: 681b ldr r3, [r3, #0] 8004534: 4a17 ldr r2, [pc, #92] @ (8004594 ) 8004536: 4293 cmp r3, r2 8004538: d004 beq.n 8004544 800453a: 687b ldr r3, [r7, #4] 800453c: 681b ldr r3, [r3, #0] 800453e: 4a16 ldr r2, [pc, #88] @ (8004598 ) 8004540: 4293 cmp r3, r2 8004542: d12b bne.n 800459c 8004544: 687b ldr r3, [r7, #4] 8004546: 681b ldr r3, [r3, #0] 8004548: 681b ldr r3, [r3, #0] 800454a: f003 0310 and.w r3, r3, #16 800454e: 2b00 cmp r3, #0 8004550: bf14 ite ne 8004552: 2301 movne r3, #1 8004554: 2300 moveq r3, #0 8004556: b2db uxtb r3, r3 8004558: e02a b.n 80045b0 800455a: bf00 nop 800455c: 40020010 .word 0x40020010 8004560: 40020028 .word 0x40020028 8004564: 40020040 .word 0x40020040 8004568: 40020058 .word 0x40020058 800456c: 40020070 .word 0x40020070 8004570: 40020088 .word 0x40020088 8004574: 400200a0 .word 0x400200a0 8004578: 400200b8 .word 0x400200b8 800457c: 40020410 .word 0x40020410 8004580: 40020428 .word 0x40020428 8004584: 40020440 .word 0x40020440 8004588: 40020458 .word 0x40020458 800458c: 40020470 .word 0x40020470 8004590: 40020488 .word 0x40020488 8004594: 400204a0 .word 0x400204a0 8004598: 400204b8 .word 0x400204b8 800459c: 687b ldr r3, [r7, #4] 800459e: 681b ldr r3, [r3, #0] 80045a0: 681b ldr r3, [r3, #0] 80045a2: f003 0302 and.w r3, r3, #2 80045a6: 2b00 cmp r3, #0 80045a8: bf14 ite ne 80045aa: 2301 movne r3, #1 80045ac: 2300 moveq r3, #0 80045ae: b2db uxtb r3, r3 80045b0: 2b00 cmp r3, #0 80045b2: f000 8087 beq.w 80046c4 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 80045b6: 687b ldr r3, [r7, #4] 80045b8: 6ddb ldr r3, [r3, #92] @ 0x5c 80045ba: f003 031f and.w r3, r3, #31 80045be: 2220 movs r2, #32 80045c0: 409a lsls r2, r3 80045c2: 6a3b ldr r3, [r7, #32] 80045c4: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 80045c6: 687b ldr r3, [r7, #4] 80045c8: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80045cc: b2db uxtb r3, r3 80045ce: 2b04 cmp r3, #4 80045d0: d139 bne.n 8004646 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 80045d2: 687b ldr r3, [r7, #4] 80045d4: 681b ldr r3, [r3, #0] 80045d6: 681a ldr r2, [r3, #0] 80045d8: 687b ldr r3, [r7, #4] 80045da: 681b ldr r3, [r3, #0] 80045dc: f022 0216 bic.w r2, r2, #22 80045e0: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80045e2: 687b ldr r3, [r7, #4] 80045e4: 681b ldr r3, [r3, #0] 80045e6: 695a ldr r2, [r3, #20] 80045e8: 687b ldr r3, [r7, #4] 80045ea: 681b ldr r3, [r3, #0] 80045ec: f022 0280 bic.w r2, r2, #128 @ 0x80 80045f0: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 80045f2: 687b ldr r3, [r7, #4] 80045f4: 6c1b ldr r3, [r3, #64] @ 0x40 80045f6: 2b00 cmp r3, #0 80045f8: d103 bne.n 8004602 80045fa: 687b ldr r3, [r7, #4] 80045fc: 6c9b ldr r3, [r3, #72] @ 0x48 80045fe: 2b00 cmp r3, #0 8004600: d007 beq.n 8004612 { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 8004602: 687b ldr r3, [r7, #4] 8004604: 681b ldr r3, [r3, #0] 8004606: 681a ldr r2, [r3, #0] 8004608: 687b ldr r3, [r7, #4] 800460a: 681b ldr r3, [r3, #0] 800460c: f022 0208 bic.w r2, r2, #8 8004610: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8004612: 687b ldr r3, [r7, #4] 8004614: 6ddb ldr r3, [r3, #92] @ 0x5c 8004616: f003 031f and.w r3, r3, #31 800461a: 223f movs r2, #63 @ 0x3f 800461c: 409a lsls r2, r3 800461e: 6a3b ldr r3, [r7, #32] 8004620: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8004622: 687b ldr r3, [r7, #4] 8004624: 2201 movs r2, #1 8004626: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800462a: 687b ldr r3, [r7, #4] 800462c: 2200 movs r2, #0 800462e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 8004632: 687b ldr r3, [r7, #4] 8004634: 6d1b ldr r3, [r3, #80] @ 0x50 8004636: 2b00 cmp r3, #0 8004638: f000 834a beq.w 8004cd0 { hdma->XferAbortCallback(hdma); 800463c: 687b ldr r3, [r7, #4] 800463e: 6d1b ldr r3, [r3, #80] @ 0x50 8004640: 6878 ldr r0, [r7, #4] 8004642: 4798 blx r3 } return; 8004644: e344 b.n 8004cd0 } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 8004646: 687b ldr r3, [r7, #4] 8004648: 681b ldr r3, [r3, #0] 800464a: 681b ldr r3, [r3, #0] 800464c: f403 2380 and.w r3, r3, #262144 @ 0x40000 8004650: 2b00 cmp r3, #0 8004652: d018 beq.n 8004686 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 8004654: 687b ldr r3, [r7, #4] 8004656: 681b ldr r3, [r3, #0] 8004658: 681b ldr r3, [r3, #0] 800465a: f403 2300 and.w r3, r3, #524288 @ 0x80000 800465e: 2b00 cmp r3, #0 8004660: d108 bne.n 8004674 { if(hdma->XferM1CpltCallback != NULL) 8004662: 687b ldr r3, [r7, #4] 8004664: 6c5b ldr r3, [r3, #68] @ 0x44 8004666: 2b00 cmp r3, #0 8004668: d02c beq.n 80046c4 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 800466a: 687b ldr r3, [r7, #4] 800466c: 6c5b ldr r3, [r3, #68] @ 0x44 800466e: 6878 ldr r0, [r7, #4] 8004670: 4798 blx r3 8004672: e027 b.n 80046c4 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8004674: 687b ldr r3, [r7, #4] 8004676: 6bdb ldr r3, [r3, #60] @ 0x3c 8004678: 2b00 cmp r3, #0 800467a: d023 beq.n 80046c4 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 800467c: 687b ldr r3, [r7, #4] 800467e: 6bdb ldr r3, [r3, #60] @ 0x3c 8004680: 6878 ldr r0, [r7, #4] 8004682: 4798 blx r3 8004684: e01e b.n 80046c4 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8004686: 687b ldr r3, [r7, #4] 8004688: 681b ldr r3, [r3, #0] 800468a: 681b ldr r3, [r3, #0] 800468c: f403 7380 and.w r3, r3, #256 @ 0x100 8004690: 2b00 cmp r3, #0 8004692: d10f bne.n 80046b4 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 8004694: 687b ldr r3, [r7, #4] 8004696: 681b ldr r3, [r3, #0] 8004698: 681a ldr r2, [r3, #0] 800469a: 687b ldr r3, [r7, #4] 800469c: 681b ldr r3, [r3, #0] 800469e: f022 0210 bic.w r2, r2, #16 80046a2: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80046a4: 687b ldr r3, [r7, #4] 80046a6: 2201 movs r2, #1 80046a8: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80046ac: 687b ldr r3, [r7, #4] 80046ae: 2200 movs r2, #0 80046b0: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 80046b4: 687b ldr r3, [r7, #4] 80046b6: 6bdb ldr r3, [r3, #60] @ 0x3c 80046b8: 2b00 cmp r3, #0 80046ba: d003 beq.n 80046c4 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 80046bc: 687b ldr r3, [r7, #4] 80046be: 6bdb ldr r3, [r3, #60] @ 0x3c 80046c0: 6878 ldr r0, [r7, #4] 80046c2: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 80046c4: 687b ldr r3, [r7, #4] 80046c6: 6d5b ldr r3, [r3, #84] @ 0x54 80046c8: 2b00 cmp r3, #0 80046ca: f000 8306 beq.w 8004cda { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 80046ce: 687b ldr r3, [r7, #4] 80046d0: 6d5b ldr r3, [r3, #84] @ 0x54 80046d2: f003 0301 and.w r3, r3, #1 80046d6: 2b00 cmp r3, #0 80046d8: f000 8088 beq.w 80047ec { hdma->State = HAL_DMA_STATE_ABORT; 80046dc: 687b ldr r3, [r7, #4] 80046de: 2204 movs r2, #4 80046e0: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80046e4: 687b ldr r3, [r7, #4] 80046e6: 681b ldr r3, [r3, #0] 80046e8: 4a7a ldr r2, [pc, #488] @ (80048d4 ) 80046ea: 4293 cmp r3, r2 80046ec: d04a beq.n 8004784 80046ee: 687b ldr r3, [r7, #4] 80046f0: 681b ldr r3, [r3, #0] 80046f2: 4a79 ldr r2, [pc, #484] @ (80048d8 ) 80046f4: 4293 cmp r3, r2 80046f6: d045 beq.n 8004784 80046f8: 687b ldr r3, [r7, #4] 80046fa: 681b ldr r3, [r3, #0] 80046fc: 4a77 ldr r2, [pc, #476] @ (80048dc ) 80046fe: 4293 cmp r3, r2 8004700: d040 beq.n 8004784 8004702: 687b ldr r3, [r7, #4] 8004704: 681b ldr r3, [r3, #0] 8004706: 4a76 ldr r2, [pc, #472] @ (80048e0 ) 8004708: 4293 cmp r3, r2 800470a: d03b beq.n 8004784 800470c: 687b ldr r3, [r7, #4] 800470e: 681b ldr r3, [r3, #0] 8004710: 4a74 ldr r2, [pc, #464] @ (80048e4 ) 8004712: 4293 cmp r3, r2 8004714: d036 beq.n 8004784 8004716: 687b ldr r3, [r7, #4] 8004718: 681b ldr r3, [r3, #0] 800471a: 4a73 ldr r2, [pc, #460] @ (80048e8 ) 800471c: 4293 cmp r3, r2 800471e: d031 beq.n 8004784 8004720: 687b ldr r3, [r7, #4] 8004722: 681b ldr r3, [r3, #0] 8004724: 4a71 ldr r2, [pc, #452] @ (80048ec ) 8004726: 4293 cmp r3, r2 8004728: d02c beq.n 8004784 800472a: 687b ldr r3, [r7, #4] 800472c: 681b ldr r3, [r3, #0] 800472e: 4a70 ldr r2, [pc, #448] @ (80048f0 ) 8004730: 4293 cmp r3, r2 8004732: d027 beq.n 8004784 8004734: 687b ldr r3, [r7, #4] 8004736: 681b ldr r3, [r3, #0] 8004738: 4a6e ldr r2, [pc, #440] @ (80048f4 ) 800473a: 4293 cmp r3, r2 800473c: d022 beq.n 8004784 800473e: 687b ldr r3, [r7, #4] 8004740: 681b ldr r3, [r3, #0] 8004742: 4a6d ldr r2, [pc, #436] @ (80048f8 ) 8004744: 4293 cmp r3, r2 8004746: d01d beq.n 8004784 8004748: 687b ldr r3, [r7, #4] 800474a: 681b ldr r3, [r3, #0] 800474c: 4a6b ldr r2, [pc, #428] @ (80048fc ) 800474e: 4293 cmp r3, r2 8004750: d018 beq.n 8004784 8004752: 687b ldr r3, [r7, #4] 8004754: 681b ldr r3, [r3, #0] 8004756: 4a6a ldr r2, [pc, #424] @ (8004900 ) 8004758: 4293 cmp r3, r2 800475a: d013 beq.n 8004784 800475c: 687b ldr r3, [r7, #4] 800475e: 681b ldr r3, [r3, #0] 8004760: 4a68 ldr r2, [pc, #416] @ (8004904 ) 8004762: 4293 cmp r3, r2 8004764: d00e beq.n 8004784 8004766: 687b ldr r3, [r7, #4] 8004768: 681b ldr r3, [r3, #0] 800476a: 4a67 ldr r2, [pc, #412] @ (8004908 ) 800476c: 4293 cmp r3, r2 800476e: d009 beq.n 8004784 8004770: 687b ldr r3, [r7, #4] 8004772: 681b ldr r3, [r3, #0] 8004774: 4a65 ldr r2, [pc, #404] @ (800490c ) 8004776: 4293 cmp r3, r2 8004778: d004 beq.n 8004784 800477a: 687b ldr r3, [r7, #4] 800477c: 681b ldr r3, [r3, #0] 800477e: 4a64 ldr r2, [pc, #400] @ (8004910 ) 8004780: 4293 cmp r3, r2 8004782: d108 bne.n 8004796 8004784: 687b ldr r3, [r7, #4] 8004786: 681b ldr r3, [r3, #0] 8004788: 681a ldr r2, [r3, #0] 800478a: 687b ldr r3, [r7, #4] 800478c: 681b ldr r3, [r3, #0] 800478e: f022 0201 bic.w r2, r2, #1 8004792: 601a str r2, [r3, #0] 8004794: e007 b.n 80047a6 8004796: 687b ldr r3, [r7, #4] 8004798: 681b ldr r3, [r3, #0] 800479a: 681a ldr r2, [r3, #0] 800479c: 687b ldr r3, [r7, #4] 800479e: 681b ldr r3, [r3, #0] 80047a0: f022 0201 bic.w r2, r2, #1 80047a4: 601a str r2, [r3, #0] do { if (++count > timeout) 80047a6: 68fb ldr r3, [r7, #12] 80047a8: 3301 adds r3, #1 80047aa: 60fb str r3, [r7, #12] 80047ac: 6a7a ldr r2, [r7, #36] @ 0x24 80047ae: 429a cmp r2, r3 80047b0: d307 bcc.n 80047c2 { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 80047b2: 687b ldr r3, [r7, #4] 80047b4: 681b ldr r3, [r3, #0] 80047b6: 681b ldr r3, [r3, #0] 80047b8: f003 0301 and.w r3, r3, #1 80047bc: 2b00 cmp r3, #0 80047be: d1f2 bne.n 80047a6 80047c0: e000 b.n 80047c4 break; 80047c2: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80047c4: 687b ldr r3, [r7, #4] 80047c6: 681b ldr r3, [r3, #0] 80047c8: 681b ldr r3, [r3, #0] 80047ca: f003 0301 and.w r3, r3, #1 80047ce: 2b00 cmp r3, #0 80047d0: d004 beq.n 80047dc { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 80047d2: 687b ldr r3, [r7, #4] 80047d4: 2203 movs r2, #3 80047d6: f883 2035 strb.w r2, [r3, #53] @ 0x35 80047da: e003 b.n 80047e4 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 80047dc: 687b ldr r3, [r7, #4] 80047de: 2201 movs r2, #1 80047e0: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 80047e4: 687b ldr r3, [r7, #4] 80047e6: 2200 movs r2, #0 80047e8: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 80047ec: 687b ldr r3, [r7, #4] 80047ee: 6cdb ldr r3, [r3, #76] @ 0x4c 80047f0: 2b00 cmp r3, #0 80047f2: f000 8272 beq.w 8004cda { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 80047f6: 687b ldr r3, [r7, #4] 80047f8: 6cdb ldr r3, [r3, #76] @ 0x4c 80047fa: 6878 ldr r0, [r7, #4] 80047fc: 4798 blx r3 80047fe: e26c b.n 8004cda } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8004800: 687b ldr r3, [r7, #4] 8004802: 681b ldr r3, [r3, #0] 8004804: 4a43 ldr r2, [pc, #268] @ (8004914 ) 8004806: 4293 cmp r3, r2 8004808: d022 beq.n 8004850 800480a: 687b ldr r3, [r7, #4] 800480c: 681b ldr r3, [r3, #0] 800480e: 4a42 ldr r2, [pc, #264] @ (8004918 ) 8004810: 4293 cmp r3, r2 8004812: d01d beq.n 8004850 8004814: 687b ldr r3, [r7, #4] 8004816: 681b ldr r3, [r3, #0] 8004818: 4a40 ldr r2, [pc, #256] @ (800491c ) 800481a: 4293 cmp r3, r2 800481c: d018 beq.n 8004850 800481e: 687b ldr r3, [r7, #4] 8004820: 681b ldr r3, [r3, #0] 8004822: 4a3f ldr r2, [pc, #252] @ (8004920 ) 8004824: 4293 cmp r3, r2 8004826: d013 beq.n 8004850 8004828: 687b ldr r3, [r7, #4] 800482a: 681b ldr r3, [r3, #0] 800482c: 4a3d ldr r2, [pc, #244] @ (8004924 ) 800482e: 4293 cmp r3, r2 8004830: d00e beq.n 8004850 8004832: 687b ldr r3, [r7, #4] 8004834: 681b ldr r3, [r3, #0] 8004836: 4a3c ldr r2, [pc, #240] @ (8004928 ) 8004838: 4293 cmp r3, r2 800483a: d009 beq.n 8004850 800483c: 687b ldr r3, [r7, #4] 800483e: 681b ldr r3, [r3, #0] 8004840: 4a3a ldr r2, [pc, #232] @ (800492c ) 8004842: 4293 cmp r3, r2 8004844: d004 beq.n 8004850 8004846: 687b ldr r3, [r7, #4] 8004848: 681b ldr r3, [r3, #0] 800484a: 4a39 ldr r2, [pc, #228] @ (8004930 ) 800484c: 4293 cmp r3, r2 800484e: d101 bne.n 8004854 8004850: 2301 movs r3, #1 8004852: e000 b.n 8004856 8004854: 2300 movs r3, #0 8004856: 2b00 cmp r3, #0 8004858: f000 823f beq.w 8004cda { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 800485c: 687b ldr r3, [r7, #4] 800485e: 681b ldr r3, [r3, #0] 8004860: 681b ldr r3, [r3, #0] 8004862: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 8004864: 687b ldr r3, [r7, #4] 8004866: 6ddb ldr r3, [r3, #92] @ 0x5c 8004868: f003 031f and.w r3, r3, #31 800486c: 2204 movs r2, #4 800486e: 409a lsls r2, r3 8004870: 697b ldr r3, [r7, #20] 8004872: 4013 ands r3, r2 8004874: 2b00 cmp r3, #0 8004876: f000 80cd beq.w 8004a14 800487a: 693b ldr r3, [r7, #16] 800487c: f003 0304 and.w r3, r3, #4 8004880: 2b00 cmp r3, #0 8004882: f000 80c7 beq.w 8004a14 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 8004886: 687b ldr r3, [r7, #4] 8004888: 6ddb ldr r3, [r3, #92] @ 0x5c 800488a: f003 031f and.w r3, r3, #31 800488e: 2204 movs r2, #4 8004890: 409a lsls r2, r3 8004892: 69fb ldr r3, [r7, #28] 8004894: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004896: 693b ldr r3, [r7, #16] 8004898: f403 4300 and.w r3, r3, #32768 @ 0x8000 800489c: 2b00 cmp r3, #0 800489e: d049 beq.n 8004934 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 80048a0: 693b ldr r3, [r7, #16] 80048a2: f403 3380 and.w r3, r3, #65536 @ 0x10000 80048a6: 2b00 cmp r3, #0 80048a8: d109 bne.n 80048be { if(hdma->XferM1HalfCpltCallback != NULL) 80048aa: 687b ldr r3, [r7, #4] 80048ac: 6c9b ldr r3, [r3, #72] @ 0x48 80048ae: 2b00 cmp r3, #0 80048b0: f000 8210 beq.w 8004cd4 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 80048b4: 687b ldr r3, [r7, #4] 80048b6: 6c9b ldr r3, [r3, #72] @ 0x48 80048b8: 6878 ldr r0, [r7, #4] 80048ba: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80048bc: e20a b.n 8004cd4 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 80048be: 687b ldr r3, [r7, #4] 80048c0: 6c1b ldr r3, [r3, #64] @ 0x40 80048c2: 2b00 cmp r3, #0 80048c4: f000 8206 beq.w 8004cd4 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 80048c8: 687b ldr r3, [r7, #4] 80048ca: 6c1b ldr r3, [r3, #64] @ 0x40 80048cc: 6878 ldr r0, [r7, #4] 80048ce: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 80048d0: e200 b.n 8004cd4 80048d2: bf00 nop 80048d4: 40020010 .word 0x40020010 80048d8: 40020028 .word 0x40020028 80048dc: 40020040 .word 0x40020040 80048e0: 40020058 .word 0x40020058 80048e4: 40020070 .word 0x40020070 80048e8: 40020088 .word 0x40020088 80048ec: 400200a0 .word 0x400200a0 80048f0: 400200b8 .word 0x400200b8 80048f4: 40020410 .word 0x40020410 80048f8: 40020428 .word 0x40020428 80048fc: 40020440 .word 0x40020440 8004900: 40020458 .word 0x40020458 8004904: 40020470 .word 0x40020470 8004908: 40020488 .word 0x40020488 800490c: 400204a0 .word 0x400204a0 8004910: 400204b8 .word 0x400204b8 8004914: 58025408 .word 0x58025408 8004918: 5802541c .word 0x5802541c 800491c: 58025430 .word 0x58025430 8004920: 58025444 .word 0x58025444 8004924: 58025458 .word 0x58025458 8004928: 5802546c .word 0x5802546c 800492c: 58025480 .word 0x58025480 8004930: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8004934: 693b ldr r3, [r7, #16] 8004936: f003 0320 and.w r3, r3, #32 800493a: 2b00 cmp r3, #0 800493c: d160 bne.n 8004a00 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800493e: 687b ldr r3, [r7, #4] 8004940: 681b ldr r3, [r3, #0] 8004942: 4a7f ldr r2, [pc, #508] @ (8004b40 ) 8004944: 4293 cmp r3, r2 8004946: d04a beq.n 80049de 8004948: 687b ldr r3, [r7, #4] 800494a: 681b ldr r3, [r3, #0] 800494c: 4a7d ldr r2, [pc, #500] @ (8004b44 ) 800494e: 4293 cmp r3, r2 8004950: d045 beq.n 80049de 8004952: 687b ldr r3, [r7, #4] 8004954: 681b ldr r3, [r3, #0] 8004956: 4a7c ldr r2, [pc, #496] @ (8004b48 ) 8004958: 4293 cmp r3, r2 800495a: d040 beq.n 80049de 800495c: 687b ldr r3, [r7, #4] 800495e: 681b ldr r3, [r3, #0] 8004960: 4a7a ldr r2, [pc, #488] @ (8004b4c ) 8004962: 4293 cmp r3, r2 8004964: d03b beq.n 80049de 8004966: 687b ldr r3, [r7, #4] 8004968: 681b ldr r3, [r3, #0] 800496a: 4a79 ldr r2, [pc, #484] @ (8004b50 ) 800496c: 4293 cmp r3, r2 800496e: d036 beq.n 80049de 8004970: 687b ldr r3, [r7, #4] 8004972: 681b ldr r3, [r3, #0] 8004974: 4a77 ldr r2, [pc, #476] @ (8004b54 ) 8004976: 4293 cmp r3, r2 8004978: d031 beq.n 80049de 800497a: 687b ldr r3, [r7, #4] 800497c: 681b ldr r3, [r3, #0] 800497e: 4a76 ldr r2, [pc, #472] @ (8004b58 ) 8004980: 4293 cmp r3, r2 8004982: d02c beq.n 80049de 8004984: 687b ldr r3, [r7, #4] 8004986: 681b ldr r3, [r3, #0] 8004988: 4a74 ldr r2, [pc, #464] @ (8004b5c ) 800498a: 4293 cmp r3, r2 800498c: d027 beq.n 80049de 800498e: 687b ldr r3, [r7, #4] 8004990: 681b ldr r3, [r3, #0] 8004992: 4a73 ldr r2, [pc, #460] @ (8004b60 ) 8004994: 4293 cmp r3, r2 8004996: d022 beq.n 80049de 8004998: 687b ldr r3, [r7, #4] 800499a: 681b ldr r3, [r3, #0] 800499c: 4a71 ldr r2, [pc, #452] @ (8004b64 ) 800499e: 4293 cmp r3, r2 80049a0: d01d beq.n 80049de 80049a2: 687b ldr r3, [r7, #4] 80049a4: 681b ldr r3, [r3, #0] 80049a6: 4a70 ldr r2, [pc, #448] @ (8004b68 ) 80049a8: 4293 cmp r3, r2 80049aa: d018 beq.n 80049de 80049ac: 687b ldr r3, [r7, #4] 80049ae: 681b ldr r3, [r3, #0] 80049b0: 4a6e ldr r2, [pc, #440] @ (8004b6c ) 80049b2: 4293 cmp r3, r2 80049b4: d013 beq.n 80049de 80049b6: 687b ldr r3, [r7, #4] 80049b8: 681b ldr r3, [r3, #0] 80049ba: 4a6d ldr r2, [pc, #436] @ (8004b70 ) 80049bc: 4293 cmp r3, r2 80049be: d00e beq.n 80049de 80049c0: 687b ldr r3, [r7, #4] 80049c2: 681b ldr r3, [r3, #0] 80049c4: 4a6b ldr r2, [pc, #428] @ (8004b74 ) 80049c6: 4293 cmp r3, r2 80049c8: d009 beq.n 80049de 80049ca: 687b ldr r3, [r7, #4] 80049cc: 681b ldr r3, [r3, #0] 80049ce: 4a6a ldr r2, [pc, #424] @ (8004b78 ) 80049d0: 4293 cmp r3, r2 80049d2: d004 beq.n 80049de 80049d4: 687b ldr r3, [r7, #4] 80049d6: 681b ldr r3, [r3, #0] 80049d8: 4a68 ldr r2, [pc, #416] @ (8004b7c ) 80049da: 4293 cmp r3, r2 80049dc: d108 bne.n 80049f0 80049de: 687b ldr r3, [r7, #4] 80049e0: 681b ldr r3, [r3, #0] 80049e2: 681a ldr r2, [r3, #0] 80049e4: 687b ldr r3, [r7, #4] 80049e6: 681b ldr r3, [r3, #0] 80049e8: f022 0208 bic.w r2, r2, #8 80049ec: 601a str r2, [r3, #0] 80049ee: e007 b.n 8004a00 80049f0: 687b ldr r3, [r7, #4] 80049f2: 681b ldr r3, [r3, #0] 80049f4: 681a ldr r2, [r3, #0] 80049f6: 687b ldr r3, [r7, #4] 80049f8: 681b ldr r3, [r3, #0] 80049fa: f022 0204 bic.w r2, r2, #4 80049fe: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8004a00: 687b ldr r3, [r7, #4] 8004a02: 6c1b ldr r3, [r3, #64] @ 0x40 8004a04: 2b00 cmp r3, #0 8004a06: f000 8165 beq.w 8004cd4 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8004a0a: 687b ldr r3, [r7, #4] 8004a0c: 6c1b ldr r3, [r3, #64] @ 0x40 8004a0e: 6878 ldr r0, [r7, #4] 8004a10: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004a12: e15f b.n 8004cd4 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 8004a14: 687b ldr r3, [r7, #4] 8004a16: 6ddb ldr r3, [r3, #92] @ 0x5c 8004a18: f003 031f and.w r3, r3, #31 8004a1c: 2202 movs r2, #2 8004a1e: 409a lsls r2, r3 8004a20: 697b ldr r3, [r7, #20] 8004a22: 4013 ands r3, r2 8004a24: 2b00 cmp r3, #0 8004a26: f000 80c5 beq.w 8004bb4 8004a2a: 693b ldr r3, [r7, #16] 8004a2c: f003 0302 and.w r3, r3, #2 8004a30: 2b00 cmp r3, #0 8004a32: f000 80bf beq.w 8004bb4 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 8004a36: 687b ldr r3, [r7, #4] 8004a38: 6ddb ldr r3, [r3, #92] @ 0x5c 8004a3a: f003 031f and.w r3, r3, #31 8004a3e: 2202 movs r2, #2 8004a40: 409a lsls r2, r3 8004a42: 69fb ldr r3, [r7, #28] 8004a44: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004a46: 693b ldr r3, [r7, #16] 8004a48: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004a4c: 2b00 cmp r3, #0 8004a4e: d018 beq.n 8004a82 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 8004a50: 693b ldr r3, [r7, #16] 8004a52: f403 3380 and.w r3, r3, #65536 @ 0x10000 8004a56: 2b00 cmp r3, #0 8004a58: d109 bne.n 8004a6e { if(hdma->XferM1CpltCallback != NULL) 8004a5a: 687b ldr r3, [r7, #4] 8004a5c: 6c5b ldr r3, [r3, #68] @ 0x44 8004a5e: 2b00 cmp r3, #0 8004a60: f000 813a beq.w 8004cd8 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 8004a64: 687b ldr r3, [r7, #4] 8004a66: 6c5b ldr r3, [r3, #68] @ 0x44 8004a68: 6878 ldr r0, [r7, #4] 8004a6a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004a6c: e134 b.n 8004cd8 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8004a6e: 687b ldr r3, [r7, #4] 8004a70: 6bdb ldr r3, [r3, #60] @ 0x3c 8004a72: 2b00 cmp r3, #0 8004a74: f000 8130 beq.w 8004cd8 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 8004a78: 687b ldr r3, [r7, #4] 8004a7a: 6bdb ldr r3, [r3, #60] @ 0x3c 8004a7c: 6878 ldr r0, [r7, #4] 8004a7e: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004a80: e12a b.n 8004cd8 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8004a82: 693b ldr r3, [r7, #16] 8004a84: f003 0320 and.w r3, r3, #32 8004a88: 2b00 cmp r3, #0 8004a8a: f040 8089 bne.w 8004ba0 { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8004a8e: 687b ldr r3, [r7, #4] 8004a90: 681b ldr r3, [r3, #0] 8004a92: 4a2b ldr r2, [pc, #172] @ (8004b40 ) 8004a94: 4293 cmp r3, r2 8004a96: d04a beq.n 8004b2e 8004a98: 687b ldr r3, [r7, #4] 8004a9a: 681b ldr r3, [r3, #0] 8004a9c: 4a29 ldr r2, [pc, #164] @ (8004b44 ) 8004a9e: 4293 cmp r3, r2 8004aa0: d045 beq.n 8004b2e 8004aa2: 687b ldr r3, [r7, #4] 8004aa4: 681b ldr r3, [r3, #0] 8004aa6: 4a28 ldr r2, [pc, #160] @ (8004b48 ) 8004aa8: 4293 cmp r3, r2 8004aaa: d040 beq.n 8004b2e 8004aac: 687b ldr r3, [r7, #4] 8004aae: 681b ldr r3, [r3, #0] 8004ab0: 4a26 ldr r2, [pc, #152] @ (8004b4c ) 8004ab2: 4293 cmp r3, r2 8004ab4: d03b beq.n 8004b2e 8004ab6: 687b ldr r3, [r7, #4] 8004ab8: 681b ldr r3, [r3, #0] 8004aba: 4a25 ldr r2, [pc, #148] @ (8004b50 ) 8004abc: 4293 cmp r3, r2 8004abe: d036 beq.n 8004b2e 8004ac0: 687b ldr r3, [r7, #4] 8004ac2: 681b ldr r3, [r3, #0] 8004ac4: 4a23 ldr r2, [pc, #140] @ (8004b54 ) 8004ac6: 4293 cmp r3, r2 8004ac8: d031 beq.n 8004b2e 8004aca: 687b ldr r3, [r7, #4] 8004acc: 681b ldr r3, [r3, #0] 8004ace: 4a22 ldr r2, [pc, #136] @ (8004b58 ) 8004ad0: 4293 cmp r3, r2 8004ad2: d02c beq.n 8004b2e 8004ad4: 687b ldr r3, [r7, #4] 8004ad6: 681b ldr r3, [r3, #0] 8004ad8: 4a20 ldr r2, [pc, #128] @ (8004b5c ) 8004ada: 4293 cmp r3, r2 8004adc: d027 beq.n 8004b2e 8004ade: 687b ldr r3, [r7, #4] 8004ae0: 681b ldr r3, [r3, #0] 8004ae2: 4a1f ldr r2, [pc, #124] @ (8004b60 ) 8004ae4: 4293 cmp r3, r2 8004ae6: d022 beq.n 8004b2e 8004ae8: 687b ldr r3, [r7, #4] 8004aea: 681b ldr r3, [r3, #0] 8004aec: 4a1d ldr r2, [pc, #116] @ (8004b64 ) 8004aee: 4293 cmp r3, r2 8004af0: d01d beq.n 8004b2e 8004af2: 687b ldr r3, [r7, #4] 8004af4: 681b ldr r3, [r3, #0] 8004af6: 4a1c ldr r2, [pc, #112] @ (8004b68 ) 8004af8: 4293 cmp r3, r2 8004afa: d018 beq.n 8004b2e 8004afc: 687b ldr r3, [r7, #4] 8004afe: 681b ldr r3, [r3, #0] 8004b00: 4a1a ldr r2, [pc, #104] @ (8004b6c ) 8004b02: 4293 cmp r3, r2 8004b04: d013 beq.n 8004b2e 8004b06: 687b ldr r3, [r7, #4] 8004b08: 681b ldr r3, [r3, #0] 8004b0a: 4a19 ldr r2, [pc, #100] @ (8004b70 ) 8004b0c: 4293 cmp r3, r2 8004b0e: d00e beq.n 8004b2e 8004b10: 687b ldr r3, [r7, #4] 8004b12: 681b ldr r3, [r3, #0] 8004b14: 4a17 ldr r2, [pc, #92] @ (8004b74 ) 8004b16: 4293 cmp r3, r2 8004b18: d009 beq.n 8004b2e 8004b1a: 687b ldr r3, [r7, #4] 8004b1c: 681b ldr r3, [r3, #0] 8004b1e: 4a16 ldr r2, [pc, #88] @ (8004b78 ) 8004b20: 4293 cmp r3, r2 8004b22: d004 beq.n 8004b2e 8004b24: 687b ldr r3, [r7, #4] 8004b26: 681b ldr r3, [r3, #0] 8004b28: 4a14 ldr r2, [pc, #80] @ (8004b7c ) 8004b2a: 4293 cmp r3, r2 8004b2c: d128 bne.n 8004b80 8004b2e: 687b ldr r3, [r7, #4] 8004b30: 681b ldr r3, [r3, #0] 8004b32: 681a ldr r2, [r3, #0] 8004b34: 687b ldr r3, [r7, #4] 8004b36: 681b ldr r3, [r3, #0] 8004b38: f022 0214 bic.w r2, r2, #20 8004b3c: 601a str r2, [r3, #0] 8004b3e: e027 b.n 8004b90 8004b40: 40020010 .word 0x40020010 8004b44: 40020028 .word 0x40020028 8004b48: 40020040 .word 0x40020040 8004b4c: 40020058 .word 0x40020058 8004b50: 40020070 .word 0x40020070 8004b54: 40020088 .word 0x40020088 8004b58: 400200a0 .word 0x400200a0 8004b5c: 400200b8 .word 0x400200b8 8004b60: 40020410 .word 0x40020410 8004b64: 40020428 .word 0x40020428 8004b68: 40020440 .word 0x40020440 8004b6c: 40020458 .word 0x40020458 8004b70: 40020470 .word 0x40020470 8004b74: 40020488 .word 0x40020488 8004b78: 400204a0 .word 0x400204a0 8004b7c: 400204b8 .word 0x400204b8 8004b80: 687b ldr r3, [r7, #4] 8004b82: 681b ldr r3, [r3, #0] 8004b84: 681a ldr r2, [r3, #0] 8004b86: 687b ldr r3, [r7, #4] 8004b88: 681b ldr r3, [r3, #0] 8004b8a: f022 020a bic.w r2, r2, #10 8004b8e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8004b90: 687b ldr r3, [r7, #4] 8004b92: 2201 movs r2, #1 8004b94: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004b98: 687b ldr r3, [r7, #4] 8004b9a: 2200 movs r2, #0 8004b9c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 8004ba0: 687b ldr r3, [r7, #4] 8004ba2: 6bdb ldr r3, [r3, #60] @ 0x3c 8004ba4: 2b00 cmp r3, #0 8004ba6: f000 8097 beq.w 8004cd8 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8004baa: 687b ldr r3, [r7, #4] 8004bac: 6bdb ldr r3, [r3, #60] @ 0x3c 8004bae: 6878 ldr r0, [r7, #4] 8004bb0: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004bb2: e091 b.n 8004cd8 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 8004bb4: 687b ldr r3, [r7, #4] 8004bb6: 6ddb ldr r3, [r3, #92] @ 0x5c 8004bb8: f003 031f and.w r3, r3, #31 8004bbc: 2208 movs r2, #8 8004bbe: 409a lsls r2, r3 8004bc0: 697b ldr r3, [r7, #20] 8004bc2: 4013 ands r3, r2 8004bc4: 2b00 cmp r3, #0 8004bc6: f000 8088 beq.w 8004cda 8004bca: 693b ldr r3, [r7, #16] 8004bcc: f003 0308 and.w r3, r3, #8 8004bd0: 2b00 cmp r3, #0 8004bd2: f000 8082 beq.w 8004cda { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8004bd6: 687b ldr r3, [r7, #4] 8004bd8: 681b ldr r3, [r3, #0] 8004bda: 4a41 ldr r2, [pc, #260] @ (8004ce0 ) 8004bdc: 4293 cmp r3, r2 8004bde: d04a beq.n 8004c76 8004be0: 687b ldr r3, [r7, #4] 8004be2: 681b ldr r3, [r3, #0] 8004be4: 4a3f ldr r2, [pc, #252] @ (8004ce4 ) 8004be6: 4293 cmp r3, r2 8004be8: d045 beq.n 8004c76 8004bea: 687b ldr r3, [r7, #4] 8004bec: 681b ldr r3, [r3, #0] 8004bee: 4a3e ldr r2, [pc, #248] @ (8004ce8 ) 8004bf0: 4293 cmp r3, r2 8004bf2: d040 beq.n 8004c76 8004bf4: 687b ldr r3, [r7, #4] 8004bf6: 681b ldr r3, [r3, #0] 8004bf8: 4a3c ldr r2, [pc, #240] @ (8004cec ) 8004bfa: 4293 cmp r3, r2 8004bfc: d03b beq.n 8004c76 8004bfe: 687b ldr r3, [r7, #4] 8004c00: 681b ldr r3, [r3, #0] 8004c02: 4a3b ldr r2, [pc, #236] @ (8004cf0 ) 8004c04: 4293 cmp r3, r2 8004c06: d036 beq.n 8004c76 8004c08: 687b ldr r3, [r7, #4] 8004c0a: 681b ldr r3, [r3, #0] 8004c0c: 4a39 ldr r2, [pc, #228] @ (8004cf4 ) 8004c0e: 4293 cmp r3, r2 8004c10: d031 beq.n 8004c76 8004c12: 687b ldr r3, [r7, #4] 8004c14: 681b ldr r3, [r3, #0] 8004c16: 4a38 ldr r2, [pc, #224] @ (8004cf8 ) 8004c18: 4293 cmp r3, r2 8004c1a: d02c beq.n 8004c76 8004c1c: 687b ldr r3, [r7, #4] 8004c1e: 681b ldr r3, [r3, #0] 8004c20: 4a36 ldr r2, [pc, #216] @ (8004cfc ) 8004c22: 4293 cmp r3, r2 8004c24: d027 beq.n 8004c76 8004c26: 687b ldr r3, [r7, #4] 8004c28: 681b ldr r3, [r3, #0] 8004c2a: 4a35 ldr r2, [pc, #212] @ (8004d00 ) 8004c2c: 4293 cmp r3, r2 8004c2e: d022 beq.n 8004c76 8004c30: 687b ldr r3, [r7, #4] 8004c32: 681b ldr r3, [r3, #0] 8004c34: 4a33 ldr r2, [pc, #204] @ (8004d04 ) 8004c36: 4293 cmp r3, r2 8004c38: d01d beq.n 8004c76 8004c3a: 687b ldr r3, [r7, #4] 8004c3c: 681b ldr r3, [r3, #0] 8004c3e: 4a32 ldr r2, [pc, #200] @ (8004d08 ) 8004c40: 4293 cmp r3, r2 8004c42: d018 beq.n 8004c76 8004c44: 687b ldr r3, [r7, #4] 8004c46: 681b ldr r3, [r3, #0] 8004c48: 4a30 ldr r2, [pc, #192] @ (8004d0c ) 8004c4a: 4293 cmp r3, r2 8004c4c: d013 beq.n 8004c76 8004c4e: 687b ldr r3, [r7, #4] 8004c50: 681b ldr r3, [r3, #0] 8004c52: 4a2f ldr r2, [pc, #188] @ (8004d10 ) 8004c54: 4293 cmp r3, r2 8004c56: d00e beq.n 8004c76 8004c58: 687b ldr r3, [r7, #4] 8004c5a: 681b ldr r3, [r3, #0] 8004c5c: 4a2d ldr r2, [pc, #180] @ (8004d14 ) 8004c5e: 4293 cmp r3, r2 8004c60: d009 beq.n 8004c76 8004c62: 687b ldr r3, [r7, #4] 8004c64: 681b ldr r3, [r3, #0] 8004c66: 4a2c ldr r2, [pc, #176] @ (8004d18 ) 8004c68: 4293 cmp r3, r2 8004c6a: d004 beq.n 8004c76 8004c6c: 687b ldr r3, [r7, #4] 8004c6e: 681b ldr r3, [r3, #0] 8004c70: 4a2a ldr r2, [pc, #168] @ (8004d1c ) 8004c72: 4293 cmp r3, r2 8004c74: d108 bne.n 8004c88 8004c76: 687b ldr r3, [r7, #4] 8004c78: 681b ldr r3, [r3, #0] 8004c7a: 681a ldr r2, [r3, #0] 8004c7c: 687b ldr r3, [r7, #4] 8004c7e: 681b ldr r3, [r3, #0] 8004c80: f022 021c bic.w r2, r2, #28 8004c84: 601a str r2, [r3, #0] 8004c86: e007 b.n 8004c98 8004c88: 687b ldr r3, [r7, #4] 8004c8a: 681b ldr r3, [r3, #0] 8004c8c: 681a ldr r2, [r3, #0] 8004c8e: 687b ldr r3, [r7, #4] 8004c90: 681b ldr r3, [r3, #0] 8004c92: f022 020e bic.w r2, r2, #14 8004c96: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8004c98: 687b ldr r3, [r7, #4] 8004c9a: 6ddb ldr r3, [r3, #92] @ 0x5c 8004c9c: f003 031f and.w r3, r3, #31 8004ca0: 2201 movs r2, #1 8004ca2: 409a lsls r2, r3 8004ca4: 69fb ldr r3, [r7, #28] 8004ca6: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8004ca8: 687b ldr r3, [r7, #4] 8004caa: 2201 movs r2, #1 8004cac: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8004cae: 687b ldr r3, [r7, #4] 8004cb0: 2201 movs r2, #1 8004cb2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004cb6: 687b ldr r3, [r7, #4] 8004cb8: 2200 movs r2, #0 8004cba: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 8004cbe: 687b ldr r3, [r7, #4] 8004cc0: 6cdb ldr r3, [r3, #76] @ 0x4c 8004cc2: 2b00 cmp r3, #0 8004cc4: d009 beq.n 8004cda { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8004cc6: 687b ldr r3, [r7, #4] 8004cc8: 6cdb ldr r3, [r3, #76] @ 0x4c 8004cca: 6878 ldr r0, [r7, #4] 8004ccc: 4798 blx r3 8004cce: e004 b.n 8004cda return; 8004cd0: bf00 nop 8004cd2: e002 b.n 8004cda if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004cd4: bf00 nop 8004cd6: e000 b.n 8004cda if((ccr_reg & BDMA_CCR_DBM) != 0U) 8004cd8: bf00 nop } else { /* Nothing To Do */ } } 8004cda: 3728 adds r7, #40 @ 0x28 8004cdc: 46bd mov sp, r7 8004cde: bd80 pop {r7, pc} 8004ce0: 40020010 .word 0x40020010 8004ce4: 40020028 .word 0x40020028 8004ce8: 40020040 .word 0x40020040 8004cec: 40020058 .word 0x40020058 8004cf0: 40020070 .word 0x40020070 8004cf4: 40020088 .word 0x40020088 8004cf8: 400200a0 .word 0x400200a0 8004cfc: 400200b8 .word 0x400200b8 8004d00: 40020410 .word 0x40020410 8004d04: 40020428 .word 0x40020428 8004d08: 40020440 .word 0x40020440 8004d0c: 40020458 .word 0x40020458 8004d10: 40020470 .word 0x40020470 8004d14: 40020488 .word 0x40020488 8004d18: 400204a0 .word 0x400204a0 8004d1c: 400204b8 .word 0x400204b8 08004d20 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 8004d20: b480 push {r7} 8004d22: b085 sub sp, #20 8004d24: af00 add r7, sp, #0 8004d26: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8004d28: 687b ldr r3, [r7, #4] 8004d2a: 681b ldr r3, [r3, #0] 8004d2c: 4a42 ldr r2, [pc, #264] @ (8004e38 ) 8004d2e: 4293 cmp r3, r2 8004d30: d04a beq.n 8004dc8 8004d32: 687b ldr r3, [r7, #4] 8004d34: 681b ldr r3, [r3, #0] 8004d36: 4a41 ldr r2, [pc, #260] @ (8004e3c ) 8004d38: 4293 cmp r3, r2 8004d3a: d045 beq.n 8004dc8 8004d3c: 687b ldr r3, [r7, #4] 8004d3e: 681b ldr r3, [r3, #0] 8004d40: 4a3f ldr r2, [pc, #252] @ (8004e40 ) 8004d42: 4293 cmp r3, r2 8004d44: d040 beq.n 8004dc8 8004d46: 687b ldr r3, [r7, #4] 8004d48: 681b ldr r3, [r3, #0] 8004d4a: 4a3e ldr r2, [pc, #248] @ (8004e44 ) 8004d4c: 4293 cmp r3, r2 8004d4e: d03b beq.n 8004dc8 8004d50: 687b ldr r3, [r7, #4] 8004d52: 681b ldr r3, [r3, #0] 8004d54: 4a3c ldr r2, [pc, #240] @ (8004e48 ) 8004d56: 4293 cmp r3, r2 8004d58: d036 beq.n 8004dc8 8004d5a: 687b ldr r3, [r7, #4] 8004d5c: 681b ldr r3, [r3, #0] 8004d5e: 4a3b ldr r2, [pc, #236] @ (8004e4c ) 8004d60: 4293 cmp r3, r2 8004d62: d031 beq.n 8004dc8 8004d64: 687b ldr r3, [r7, #4] 8004d66: 681b ldr r3, [r3, #0] 8004d68: 4a39 ldr r2, [pc, #228] @ (8004e50 ) 8004d6a: 4293 cmp r3, r2 8004d6c: d02c beq.n 8004dc8 8004d6e: 687b ldr r3, [r7, #4] 8004d70: 681b ldr r3, [r3, #0] 8004d72: 4a38 ldr r2, [pc, #224] @ (8004e54 ) 8004d74: 4293 cmp r3, r2 8004d76: d027 beq.n 8004dc8 8004d78: 687b ldr r3, [r7, #4] 8004d7a: 681b ldr r3, [r3, #0] 8004d7c: 4a36 ldr r2, [pc, #216] @ (8004e58 ) 8004d7e: 4293 cmp r3, r2 8004d80: d022 beq.n 8004dc8 8004d82: 687b ldr r3, [r7, #4] 8004d84: 681b ldr r3, [r3, #0] 8004d86: 4a35 ldr r2, [pc, #212] @ (8004e5c ) 8004d88: 4293 cmp r3, r2 8004d8a: d01d beq.n 8004dc8 8004d8c: 687b ldr r3, [r7, #4] 8004d8e: 681b ldr r3, [r3, #0] 8004d90: 4a33 ldr r2, [pc, #204] @ (8004e60 ) 8004d92: 4293 cmp r3, r2 8004d94: d018 beq.n 8004dc8 8004d96: 687b ldr r3, [r7, #4] 8004d98: 681b ldr r3, [r3, #0] 8004d9a: 4a32 ldr r2, [pc, #200] @ (8004e64 ) 8004d9c: 4293 cmp r3, r2 8004d9e: d013 beq.n 8004dc8 8004da0: 687b ldr r3, [r7, #4] 8004da2: 681b ldr r3, [r3, #0] 8004da4: 4a30 ldr r2, [pc, #192] @ (8004e68 ) 8004da6: 4293 cmp r3, r2 8004da8: d00e beq.n 8004dc8 8004daa: 687b ldr r3, [r7, #4] 8004dac: 681b ldr r3, [r3, #0] 8004dae: 4a2f ldr r2, [pc, #188] @ (8004e6c ) 8004db0: 4293 cmp r3, r2 8004db2: d009 beq.n 8004dc8 8004db4: 687b ldr r3, [r7, #4] 8004db6: 681b ldr r3, [r3, #0] 8004db8: 4a2d ldr r2, [pc, #180] @ (8004e70 ) 8004dba: 4293 cmp r3, r2 8004dbc: d004 beq.n 8004dc8 8004dbe: 687b ldr r3, [r7, #4] 8004dc0: 681b ldr r3, [r3, #0] 8004dc2: 4a2c ldr r2, [pc, #176] @ (8004e74 ) 8004dc4: 4293 cmp r3, r2 8004dc6: d101 bne.n 8004dcc 8004dc8: 2301 movs r3, #1 8004dca: e000 b.n 8004dce 8004dcc: 2300 movs r3, #0 8004dce: 2b00 cmp r3, #0 8004dd0: d024 beq.n 8004e1c { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 8004dd2: 687b ldr r3, [r7, #4] 8004dd4: 681b ldr r3, [r3, #0] 8004dd6: b2db uxtb r3, r3 8004dd8: 3b10 subs r3, #16 8004dda: 4a27 ldr r2, [pc, #156] @ (8004e78 ) 8004ddc: fba2 2303 umull r2, r3, r2, r3 8004de0: 091b lsrs r3, r3, #4 8004de2: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 8004de4: 68fb ldr r3, [r7, #12] 8004de6: f003 0307 and.w r3, r3, #7 8004dea: 4a24 ldr r2, [pc, #144] @ (8004e7c ) 8004dec: 5cd3 ldrb r3, [r2, r3] 8004dee: 461a mov r2, r3 8004df0: 687b ldr r3, [r7, #4] 8004df2: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 8004df4: 68fb ldr r3, [r7, #12] 8004df6: 2b03 cmp r3, #3 8004df8: d908 bls.n 8004e0c { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 8004dfa: 687b ldr r3, [r7, #4] 8004dfc: 681b ldr r3, [r3, #0] 8004dfe: 461a mov r2, r3 8004e00: 4b1f ldr r3, [pc, #124] @ (8004e80 ) 8004e02: 4013 ands r3, r2 8004e04: 1d1a adds r2, r3, #4 8004e06: 687b ldr r3, [r7, #4] 8004e08: 659a str r2, [r3, #88] @ 0x58 8004e0a: e00d b.n 8004e28 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 8004e0c: 687b ldr r3, [r7, #4] 8004e0e: 681b ldr r3, [r3, #0] 8004e10: 461a mov r2, r3 8004e12: 4b1b ldr r3, [pc, #108] @ (8004e80 ) 8004e14: 4013 ands r3, r2 8004e16: 687a ldr r2, [r7, #4] 8004e18: 6593 str r3, [r2, #88] @ 0x58 8004e1a: e005 b.n 8004e28 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 8004e1c: 687b ldr r3, [r7, #4] 8004e1e: 681b ldr r3, [r3, #0] 8004e20: f023 02ff bic.w r2, r3, #255 @ 0xff 8004e24: 687b ldr r3, [r7, #4] 8004e26: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 8004e28: 687b ldr r3, [r7, #4] 8004e2a: 6d9b ldr r3, [r3, #88] @ 0x58 } 8004e2c: 4618 mov r0, r3 8004e2e: 3714 adds r7, #20 8004e30: 46bd mov sp, r7 8004e32: f85d 7b04 ldr.w r7, [sp], #4 8004e36: 4770 bx lr 8004e38: 40020010 .word 0x40020010 8004e3c: 40020028 .word 0x40020028 8004e40: 40020040 .word 0x40020040 8004e44: 40020058 .word 0x40020058 8004e48: 40020070 .word 0x40020070 8004e4c: 40020088 .word 0x40020088 8004e50: 400200a0 .word 0x400200a0 8004e54: 400200b8 .word 0x400200b8 8004e58: 40020410 .word 0x40020410 8004e5c: 40020428 .word 0x40020428 8004e60: 40020440 .word 0x40020440 8004e64: 40020458 .word 0x40020458 8004e68: 40020470 .word 0x40020470 8004e6c: 40020488 .word 0x40020488 8004e70: 400204a0 .word 0x400204a0 8004e74: 400204b8 .word 0x400204b8 8004e78: aaaaaaab .word 0xaaaaaaab 8004e7c: 080100c0 .word 0x080100c0 8004e80: fffffc00 .word 0xfffffc00 08004e84 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 8004e84: b480 push {r7} 8004e86: b085 sub sp, #20 8004e88: af00 add r7, sp, #0 8004e8a: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8004e8c: 2300 movs r3, #0 8004e8e: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 8004e90: 687b ldr r3, [r7, #4] 8004e92: 699b ldr r3, [r3, #24] 8004e94: 2b00 cmp r3, #0 8004e96: d120 bne.n 8004eda { switch (hdma->Init.FIFOThreshold) 8004e98: 687b ldr r3, [r7, #4] 8004e9a: 6a9b ldr r3, [r3, #40] @ 0x28 8004e9c: 2b03 cmp r3, #3 8004e9e: d858 bhi.n 8004f52 8004ea0: a201 add r2, pc, #4 @ (adr r2, 8004ea8 ) 8004ea2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004ea6: bf00 nop 8004ea8: 08004eb9 .word 0x08004eb9 8004eac: 08004ecb .word 0x08004ecb 8004eb0: 08004eb9 .word 0x08004eb9 8004eb4: 08004f53 .word 0x08004f53 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8004eb8: 687b ldr r3, [r7, #4] 8004eba: 6adb ldr r3, [r3, #44] @ 0x2c 8004ebc: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8004ec0: 2b00 cmp r3, #0 8004ec2: d048 beq.n 8004f56 { status = HAL_ERROR; 8004ec4: 2301 movs r3, #1 8004ec6: 73fb strb r3, [r7, #15] } break; 8004ec8: e045 b.n 8004f56 case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8004eca: 687b ldr r3, [r7, #4] 8004ecc: 6adb ldr r3, [r3, #44] @ 0x2c 8004ece: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 8004ed2: d142 bne.n 8004f5a { status = HAL_ERROR; 8004ed4: 2301 movs r3, #1 8004ed6: 73fb strb r3, [r7, #15] } break; 8004ed8: e03f b.n 8004f5a break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 8004eda: 687b ldr r3, [r7, #4] 8004edc: 699b ldr r3, [r3, #24] 8004ede: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8004ee2: d123 bne.n 8004f2c { switch (hdma->Init.FIFOThreshold) 8004ee4: 687b ldr r3, [r7, #4] 8004ee6: 6a9b ldr r3, [r3, #40] @ 0x28 8004ee8: 2b03 cmp r3, #3 8004eea: d838 bhi.n 8004f5e 8004eec: a201 add r2, pc, #4 @ (adr r2, 8004ef4 ) 8004eee: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004ef2: bf00 nop 8004ef4: 08004f05 .word 0x08004f05 8004ef8: 08004f0b .word 0x08004f0b 8004efc: 08004f05 .word 0x08004f05 8004f00: 08004f1d .word 0x08004f1d { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 8004f04: 2301 movs r3, #1 8004f06: 73fb strb r3, [r7, #15] break; 8004f08: e030 b.n 8004f6c case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8004f0a: 687b ldr r3, [r7, #4] 8004f0c: 6adb ldr r3, [r3, #44] @ 0x2c 8004f0e: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8004f12: 2b00 cmp r3, #0 8004f14: d025 beq.n 8004f62 { status = HAL_ERROR; 8004f16: 2301 movs r3, #1 8004f18: 73fb strb r3, [r7, #15] } break; 8004f1a: e022 b.n 8004f62 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 8004f1c: 687b ldr r3, [r7, #4] 8004f1e: 6adb ldr r3, [r3, #44] @ 0x2c 8004f20: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 8004f24: d11f bne.n 8004f66 { status = HAL_ERROR; 8004f26: 2301 movs r3, #1 8004f28: 73fb strb r3, [r7, #15] } break; 8004f2a: e01c b.n 8004f66 } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 8004f2c: 687b ldr r3, [r7, #4] 8004f2e: 6a9b ldr r3, [r3, #40] @ 0x28 8004f30: 2b02 cmp r3, #2 8004f32: d902 bls.n 8004f3a 8004f34: 2b03 cmp r3, #3 8004f36: d003 beq.n 8004f40 status = HAL_ERROR; } break; default: break; 8004f38: e018 b.n 8004f6c status = HAL_ERROR; 8004f3a: 2301 movs r3, #1 8004f3c: 73fb strb r3, [r7, #15] break; 8004f3e: e015 b.n 8004f6c if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 8004f40: 687b ldr r3, [r7, #4] 8004f42: 6adb ldr r3, [r3, #44] @ 0x2c 8004f44: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8004f48: 2b00 cmp r3, #0 8004f4a: d00e beq.n 8004f6a status = HAL_ERROR; 8004f4c: 2301 movs r3, #1 8004f4e: 73fb strb r3, [r7, #15] break; 8004f50: e00b b.n 8004f6a break; 8004f52: bf00 nop 8004f54: e00a b.n 8004f6c break; 8004f56: bf00 nop 8004f58: e008 b.n 8004f6c break; 8004f5a: bf00 nop 8004f5c: e006 b.n 8004f6c break; 8004f5e: bf00 nop 8004f60: e004 b.n 8004f6c break; 8004f62: bf00 nop 8004f64: e002 b.n 8004f6c break; 8004f66: bf00 nop 8004f68: e000 b.n 8004f6c break; 8004f6a: bf00 nop } } return status; 8004f6c: 7bfb ldrb r3, [r7, #15] } 8004f6e: 4618 mov r0, r3 8004f70: 3714 adds r7, #20 8004f72: 46bd mov sp, r7 8004f74: f85d 7b04 ldr.w r7, [sp], #4 8004f78: 4770 bx lr 8004f7a: bf00 nop 08004f7c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 8004f7c: b480 push {r7} 8004f7e: b085 sub sp, #20 8004f80: af00 add r7, sp, #0 8004f82: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 8004f84: 687b ldr r3, [r7, #4] 8004f86: 681b ldr r3, [r3, #0] 8004f88: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8004f8a: 687b ldr r3, [r7, #4] 8004f8c: 681b ldr r3, [r3, #0] 8004f8e: 4a38 ldr r2, [pc, #224] @ (8005070 ) 8004f90: 4293 cmp r3, r2 8004f92: d022 beq.n 8004fda 8004f94: 687b ldr r3, [r7, #4] 8004f96: 681b ldr r3, [r3, #0] 8004f98: 4a36 ldr r2, [pc, #216] @ (8005074 ) 8004f9a: 4293 cmp r3, r2 8004f9c: d01d beq.n 8004fda 8004f9e: 687b ldr r3, [r7, #4] 8004fa0: 681b ldr r3, [r3, #0] 8004fa2: 4a35 ldr r2, [pc, #212] @ (8005078 ) 8004fa4: 4293 cmp r3, r2 8004fa6: d018 beq.n 8004fda 8004fa8: 687b ldr r3, [r7, #4] 8004faa: 681b ldr r3, [r3, #0] 8004fac: 4a33 ldr r2, [pc, #204] @ (800507c ) 8004fae: 4293 cmp r3, r2 8004fb0: d013 beq.n 8004fda 8004fb2: 687b ldr r3, [r7, #4] 8004fb4: 681b ldr r3, [r3, #0] 8004fb6: 4a32 ldr r2, [pc, #200] @ (8005080 ) 8004fb8: 4293 cmp r3, r2 8004fba: d00e beq.n 8004fda 8004fbc: 687b ldr r3, [r7, #4] 8004fbe: 681b ldr r3, [r3, #0] 8004fc0: 4a30 ldr r2, [pc, #192] @ (8005084 ) 8004fc2: 4293 cmp r3, r2 8004fc4: d009 beq.n 8004fda 8004fc6: 687b ldr r3, [r7, #4] 8004fc8: 681b ldr r3, [r3, #0] 8004fca: 4a2f ldr r2, [pc, #188] @ (8005088 ) 8004fcc: 4293 cmp r3, r2 8004fce: d004 beq.n 8004fda 8004fd0: 687b ldr r3, [r7, #4] 8004fd2: 681b ldr r3, [r3, #0] 8004fd4: 4a2d ldr r2, [pc, #180] @ (800508c ) 8004fd6: 4293 cmp r3, r2 8004fd8: d101 bne.n 8004fde 8004fda: 2301 movs r3, #1 8004fdc: e000 b.n 8004fe0 8004fde: 2300 movs r3, #0 8004fe0: 2b00 cmp r3, #0 8004fe2: d01a beq.n 800501a { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 8004fe4: 687b ldr r3, [r7, #4] 8004fe6: 681b ldr r3, [r3, #0] 8004fe8: b2db uxtb r3, r3 8004fea: 3b08 subs r3, #8 8004fec: 4a28 ldr r2, [pc, #160] @ (8005090 ) 8004fee: fba2 2303 umull r2, r3, r2, r3 8004ff2: 091b lsrs r3, r3, #4 8004ff4: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 8004ff6: 68fa ldr r2, [r7, #12] 8004ff8: 4b26 ldr r3, [pc, #152] @ (8005094 ) 8004ffa: 4413 add r3, r2 8004ffc: 009b lsls r3, r3, #2 8004ffe: 461a mov r2, r3 8005000: 687b ldr r3, [r7, #4] 8005002: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 8005004: 687b ldr r3, [r7, #4] 8005006: 4a24 ldr r2, [pc, #144] @ (8005098 ) 8005008: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800500a: 68fb ldr r3, [r7, #12] 800500c: f003 031f and.w r3, r3, #31 8005010: 2201 movs r2, #1 8005012: 409a lsls r2, r3 8005014: 687b ldr r3, [r7, #4] 8005016: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 8005018: e024 b.n 8005064 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800501a: 687b ldr r3, [r7, #4] 800501c: 681b ldr r3, [r3, #0] 800501e: b2db uxtb r3, r3 8005020: 3b10 subs r3, #16 8005022: 4a1e ldr r2, [pc, #120] @ (800509c ) 8005024: fba2 2303 umull r2, r3, r2, r3 8005028: 091b lsrs r3, r3, #4 800502a: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800502c: 68bb ldr r3, [r7, #8] 800502e: 4a1c ldr r2, [pc, #112] @ (80050a0 ) 8005030: 4293 cmp r3, r2 8005032: d806 bhi.n 8005042 8005034: 68bb ldr r3, [r7, #8] 8005036: 4a1b ldr r2, [pc, #108] @ (80050a4 ) 8005038: 4293 cmp r3, r2 800503a: d902 bls.n 8005042 stream_number += 8U; 800503c: 68fb ldr r3, [r7, #12] 800503e: 3308 adds r3, #8 8005040: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 8005042: 68fa ldr r2, [r7, #12] 8005044: 4b18 ldr r3, [pc, #96] @ (80050a8 ) 8005046: 4413 add r3, r2 8005048: 009b lsls r3, r3, #2 800504a: 461a mov r2, r3 800504c: 687b ldr r3, [r7, #4] 800504e: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8005050: 687b ldr r3, [r7, #4] 8005052: 4a16 ldr r2, [pc, #88] @ (80050ac ) 8005054: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 8005056: 68fb ldr r3, [r7, #12] 8005058: f003 031f and.w r3, r3, #31 800505c: 2201 movs r2, #1 800505e: 409a lsls r2, r3 8005060: 687b ldr r3, [r7, #4] 8005062: 669a str r2, [r3, #104] @ 0x68 } 8005064: bf00 nop 8005066: 3714 adds r7, #20 8005068: 46bd mov sp, r7 800506a: f85d 7b04 ldr.w r7, [sp], #4 800506e: 4770 bx lr 8005070: 58025408 .word 0x58025408 8005074: 5802541c .word 0x5802541c 8005078: 58025430 .word 0x58025430 800507c: 58025444 .word 0x58025444 8005080: 58025458 .word 0x58025458 8005084: 5802546c .word 0x5802546c 8005088: 58025480 .word 0x58025480 800508c: 58025494 .word 0x58025494 8005090: cccccccd .word 0xcccccccd 8005094: 16009600 .word 0x16009600 8005098: 58025880 .word 0x58025880 800509c: aaaaaaab .word 0xaaaaaaab 80050a0: 400204b8 .word 0x400204b8 80050a4: 4002040f .word 0x4002040f 80050a8: 10008200 .word 0x10008200 80050ac: 40020880 .word 0x40020880 080050b0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 80050b0: b480 push {r7} 80050b2: b085 sub sp, #20 80050b4: af00 add r7, sp, #0 80050b6: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 80050b8: 687b ldr r3, [r7, #4] 80050ba: 685b ldr r3, [r3, #4] 80050bc: b2db uxtb r3, r3 80050be: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 80050c0: 68fb ldr r3, [r7, #12] 80050c2: 2b00 cmp r3, #0 80050c4: d04a beq.n 800515c 80050c6: 68fb ldr r3, [r7, #12] 80050c8: 2b08 cmp r3, #8 80050ca: d847 bhi.n 800515c { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80050cc: 687b ldr r3, [r7, #4] 80050ce: 681b ldr r3, [r3, #0] 80050d0: 4a25 ldr r2, [pc, #148] @ (8005168 ) 80050d2: 4293 cmp r3, r2 80050d4: d022 beq.n 800511c 80050d6: 687b ldr r3, [r7, #4] 80050d8: 681b ldr r3, [r3, #0] 80050da: 4a24 ldr r2, [pc, #144] @ (800516c ) 80050dc: 4293 cmp r3, r2 80050de: d01d beq.n 800511c 80050e0: 687b ldr r3, [r7, #4] 80050e2: 681b ldr r3, [r3, #0] 80050e4: 4a22 ldr r2, [pc, #136] @ (8005170 ) 80050e6: 4293 cmp r3, r2 80050e8: d018 beq.n 800511c 80050ea: 687b ldr r3, [r7, #4] 80050ec: 681b ldr r3, [r3, #0] 80050ee: 4a21 ldr r2, [pc, #132] @ (8005174 ) 80050f0: 4293 cmp r3, r2 80050f2: d013 beq.n 800511c 80050f4: 687b ldr r3, [r7, #4] 80050f6: 681b ldr r3, [r3, #0] 80050f8: 4a1f ldr r2, [pc, #124] @ (8005178 ) 80050fa: 4293 cmp r3, r2 80050fc: d00e beq.n 800511c 80050fe: 687b ldr r3, [r7, #4] 8005100: 681b ldr r3, [r3, #0] 8005102: 4a1e ldr r2, [pc, #120] @ (800517c ) 8005104: 4293 cmp r3, r2 8005106: d009 beq.n 800511c 8005108: 687b ldr r3, [r7, #4] 800510a: 681b ldr r3, [r3, #0] 800510c: 4a1c ldr r2, [pc, #112] @ (8005180 ) 800510e: 4293 cmp r3, r2 8005110: d004 beq.n 800511c 8005112: 687b ldr r3, [r7, #4] 8005114: 681b ldr r3, [r3, #0] 8005116: 4a1b ldr r2, [pc, #108] @ (8005184 ) 8005118: 4293 cmp r3, r2 800511a: d101 bne.n 8005120 800511c: 2301 movs r3, #1 800511e: e000 b.n 8005122 8005120: 2300 movs r3, #0 8005122: 2b00 cmp r3, #0 8005124: d00a beq.n 800513c { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 8005126: 68fa ldr r2, [r7, #12] 8005128: 4b17 ldr r3, [pc, #92] @ (8005188 ) 800512a: 4413 add r3, r2 800512c: 009b lsls r3, r3, #2 800512e: 461a mov r2, r3 8005130: 687b ldr r3, [r7, #4] 8005132: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 8005134: 687b ldr r3, [r7, #4] 8005136: 4a15 ldr r2, [pc, #84] @ (800518c ) 8005138: 671a str r2, [r3, #112] @ 0x70 800513a: e009 b.n 8005150 } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800513c: 68fa ldr r2, [r7, #12] 800513e: 4b14 ldr r3, [pc, #80] @ (8005190 ) 8005140: 4413 add r3, r2 8005142: 009b lsls r3, r3, #2 8005144: 461a mov r2, r3 8005146: 687b ldr r3, [r7, #4] 8005148: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800514a: 687b ldr r3, [r7, #4] 800514c: 4a11 ldr r2, [pc, #68] @ (8005194 ) 800514e: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 8005150: 68fb ldr r3, [r7, #12] 8005152: 3b01 subs r3, #1 8005154: 2201 movs r2, #1 8005156: 409a lsls r2, r3 8005158: 687b ldr r3, [r7, #4] 800515a: 675a str r2, [r3, #116] @ 0x74 } } 800515c: bf00 nop 800515e: 3714 adds r7, #20 8005160: 46bd mov sp, r7 8005162: f85d 7b04 ldr.w r7, [sp], #4 8005166: 4770 bx lr 8005168: 58025408 .word 0x58025408 800516c: 5802541c .word 0x5802541c 8005170: 58025430 .word 0x58025430 8005174: 58025444 .word 0x58025444 8005178: 58025458 .word 0x58025458 800517c: 5802546c .word 0x5802546c 8005180: 58025480 .word 0x58025480 8005184: 58025494 .word 0x58025494 8005188: 1600963f .word 0x1600963f 800518c: 58025940 .word 0x58025940 8005190: 1000823f .word 0x1000823f 8005194: 40020940 .word 0x40020940 08005198 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8005198: b480 push {r7} 800519a: b089 sub sp, #36 @ 0x24 800519c: af00 add r7, sp, #0 800519e: 6078 str r0, [r7, #4] 80051a0: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 80051a2: 2300 movs r3, #0 80051a4: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 80051a6: 4b89 ldr r3, [pc, #548] @ (80053cc ) 80051a8: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 80051aa: e194 b.n 80054d6 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 80051ac: 683b ldr r3, [r7, #0] 80051ae: 681a ldr r2, [r3, #0] 80051b0: 2101 movs r1, #1 80051b2: 69fb ldr r3, [r7, #28] 80051b4: fa01 f303 lsl.w r3, r1, r3 80051b8: 4013 ands r3, r2 80051ba: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 80051bc: 693b ldr r3, [r7, #16] 80051be: 2b00 cmp r3, #0 80051c0: f000 8186 beq.w 80054d0 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 80051c4: 683b ldr r3, [r7, #0] 80051c6: 685b ldr r3, [r3, #4] 80051c8: f003 0303 and.w r3, r3, #3 80051cc: 2b01 cmp r3, #1 80051ce: d005 beq.n 80051dc 80051d0: 683b ldr r3, [r7, #0] 80051d2: 685b ldr r3, [r3, #4] 80051d4: f003 0303 and.w r3, r3, #3 80051d8: 2b02 cmp r3, #2 80051da: d130 bne.n 800523e { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80051dc: 687b ldr r3, [r7, #4] 80051de: 689b ldr r3, [r3, #8] 80051e0: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 80051e2: 69fb ldr r3, [r7, #28] 80051e4: 005b lsls r3, r3, #1 80051e6: 2203 movs r2, #3 80051e8: fa02 f303 lsl.w r3, r2, r3 80051ec: 43db mvns r3, r3 80051ee: 69ba ldr r2, [r7, #24] 80051f0: 4013 ands r3, r2 80051f2: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 80051f4: 683b ldr r3, [r7, #0] 80051f6: 68da ldr r2, [r3, #12] 80051f8: 69fb ldr r3, [r7, #28] 80051fa: 005b lsls r3, r3, #1 80051fc: fa02 f303 lsl.w r3, r2, r3 8005200: 69ba ldr r2, [r7, #24] 8005202: 4313 orrs r3, r2 8005204: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8005206: 687b ldr r3, [r7, #4] 8005208: 69ba ldr r2, [r7, #24] 800520a: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800520c: 687b ldr r3, [r7, #4] 800520e: 685b ldr r3, [r3, #4] 8005210: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8005212: 2201 movs r2, #1 8005214: 69fb ldr r3, [r7, #28] 8005216: fa02 f303 lsl.w r3, r2, r3 800521a: 43db mvns r3, r3 800521c: 69ba ldr r2, [r7, #24] 800521e: 4013 ands r3, r2 8005220: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8005222: 683b ldr r3, [r7, #0] 8005224: 685b ldr r3, [r3, #4] 8005226: 091b lsrs r3, r3, #4 8005228: f003 0201 and.w r2, r3, #1 800522c: 69fb ldr r3, [r7, #28] 800522e: fa02 f303 lsl.w r3, r2, r3 8005232: 69ba ldr r2, [r7, #24] 8005234: 4313 orrs r3, r2 8005236: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8005238: 687b ldr r3, [r7, #4] 800523a: 69ba ldr r2, [r7, #24] 800523c: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800523e: 683b ldr r3, [r7, #0] 8005240: 685b ldr r3, [r3, #4] 8005242: f003 0303 and.w r3, r3, #3 8005246: 2b03 cmp r3, #3 8005248: d017 beq.n 800527a { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800524a: 687b ldr r3, [r7, #4] 800524c: 68db ldr r3, [r3, #12] 800524e: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 8005250: 69fb ldr r3, [r7, #28] 8005252: 005b lsls r3, r3, #1 8005254: 2203 movs r2, #3 8005256: fa02 f303 lsl.w r3, r2, r3 800525a: 43db mvns r3, r3 800525c: 69ba ldr r2, [r7, #24] 800525e: 4013 ands r3, r2 8005260: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8005262: 683b ldr r3, [r7, #0] 8005264: 689a ldr r2, [r3, #8] 8005266: 69fb ldr r3, [r7, #28] 8005268: 005b lsls r3, r3, #1 800526a: fa02 f303 lsl.w r3, r2, r3 800526e: 69ba ldr r2, [r7, #24] 8005270: 4313 orrs r3, r2 8005272: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8005274: 687b ldr r3, [r7, #4] 8005276: 69ba ldr r2, [r7, #24] 8005278: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800527a: 683b ldr r3, [r7, #0] 800527c: 685b ldr r3, [r3, #4] 800527e: f003 0303 and.w r3, r3, #3 8005282: 2b02 cmp r3, #2 8005284: d123 bne.n 80052ce /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8005286: 69fb ldr r3, [r7, #28] 8005288: 08da lsrs r2, r3, #3 800528a: 687b ldr r3, [r7, #4] 800528c: 3208 adds r2, #8 800528e: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8005292: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 8005294: 69fb ldr r3, [r7, #28] 8005296: f003 0307 and.w r3, r3, #7 800529a: 009b lsls r3, r3, #2 800529c: 220f movs r2, #15 800529e: fa02 f303 lsl.w r3, r2, r3 80052a2: 43db mvns r3, r3 80052a4: 69ba ldr r2, [r7, #24] 80052a6: 4013 ands r3, r2 80052a8: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 80052aa: 683b ldr r3, [r7, #0] 80052ac: 691a ldr r2, [r3, #16] 80052ae: 69fb ldr r3, [r7, #28] 80052b0: f003 0307 and.w r3, r3, #7 80052b4: 009b lsls r3, r3, #2 80052b6: fa02 f303 lsl.w r3, r2, r3 80052ba: 69ba ldr r2, [r7, #24] 80052bc: 4313 orrs r3, r2 80052be: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 80052c0: 69fb ldr r3, [r7, #28] 80052c2: 08da lsrs r2, r3, #3 80052c4: 687b ldr r3, [r7, #4] 80052c6: 3208 adds r2, #8 80052c8: 69b9 ldr r1, [r7, #24] 80052ca: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 80052ce: 687b ldr r3, [r7, #4] 80052d0: 681b ldr r3, [r3, #0] 80052d2: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 80052d4: 69fb ldr r3, [r7, #28] 80052d6: 005b lsls r3, r3, #1 80052d8: 2203 movs r2, #3 80052da: fa02 f303 lsl.w r3, r2, r3 80052de: 43db mvns r3, r3 80052e0: 69ba ldr r2, [r7, #24] 80052e2: 4013 ands r3, r2 80052e4: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 80052e6: 683b ldr r3, [r7, #0] 80052e8: 685b ldr r3, [r3, #4] 80052ea: f003 0203 and.w r2, r3, #3 80052ee: 69fb ldr r3, [r7, #28] 80052f0: 005b lsls r3, r3, #1 80052f2: fa02 f303 lsl.w r3, r2, r3 80052f6: 69ba ldr r2, [r7, #24] 80052f8: 4313 orrs r3, r2 80052fa: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 80052fc: 687b ldr r3, [r7, #4] 80052fe: 69ba ldr r2, [r7, #24] 8005300: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8005302: 683b ldr r3, [r7, #0] 8005304: 685b ldr r3, [r3, #4] 8005306: f403 3340 and.w r3, r3, #196608 @ 0x30000 800530a: 2b00 cmp r3, #0 800530c: f000 80e0 beq.w 80054d0 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8005310: 4b2f ldr r3, [pc, #188] @ (80053d0 ) 8005312: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8005316: 4a2e ldr r2, [pc, #184] @ (80053d0 ) 8005318: f043 0302 orr.w r3, r3, #2 800531c: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8005320: 4b2b ldr r3, [pc, #172] @ (80053d0 ) 8005322: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8005326: f003 0302 and.w r3, r3, #2 800532a: 60fb str r3, [r7, #12] 800532c: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800532e: 4a29 ldr r2, [pc, #164] @ (80053d4 ) 8005330: 69fb ldr r3, [r7, #28] 8005332: 089b lsrs r3, r3, #2 8005334: 3302 adds r3, #2 8005336: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800533a: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800533c: 69fb ldr r3, [r7, #28] 800533e: f003 0303 and.w r3, r3, #3 8005342: 009b lsls r3, r3, #2 8005344: 220f movs r2, #15 8005346: fa02 f303 lsl.w r3, r2, r3 800534a: 43db mvns r3, r3 800534c: 69ba ldr r2, [r7, #24] 800534e: 4013 ands r3, r2 8005350: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 8005352: 687b ldr r3, [r7, #4] 8005354: 4a20 ldr r2, [pc, #128] @ (80053d8 ) 8005356: 4293 cmp r3, r2 8005358: d052 beq.n 8005400 800535a: 687b ldr r3, [r7, #4] 800535c: 4a1f ldr r2, [pc, #124] @ (80053dc ) 800535e: 4293 cmp r3, r2 8005360: d031 beq.n 80053c6 8005362: 687b ldr r3, [r7, #4] 8005364: 4a1e ldr r2, [pc, #120] @ (80053e0 ) 8005366: 4293 cmp r3, r2 8005368: d02b beq.n 80053c2 800536a: 687b ldr r3, [r7, #4] 800536c: 4a1d ldr r2, [pc, #116] @ (80053e4 ) 800536e: 4293 cmp r3, r2 8005370: d025 beq.n 80053be 8005372: 687b ldr r3, [r7, #4] 8005374: 4a1c ldr r2, [pc, #112] @ (80053e8 ) 8005376: 4293 cmp r3, r2 8005378: d01f beq.n 80053ba 800537a: 687b ldr r3, [r7, #4] 800537c: 4a1b ldr r2, [pc, #108] @ (80053ec ) 800537e: 4293 cmp r3, r2 8005380: d019 beq.n 80053b6 8005382: 687b ldr r3, [r7, #4] 8005384: 4a1a ldr r2, [pc, #104] @ (80053f0 ) 8005386: 4293 cmp r3, r2 8005388: d013 beq.n 80053b2 800538a: 687b ldr r3, [r7, #4] 800538c: 4a19 ldr r2, [pc, #100] @ (80053f4 ) 800538e: 4293 cmp r3, r2 8005390: d00d beq.n 80053ae 8005392: 687b ldr r3, [r7, #4] 8005394: 4a18 ldr r2, [pc, #96] @ (80053f8 ) 8005396: 4293 cmp r3, r2 8005398: d007 beq.n 80053aa 800539a: 687b ldr r3, [r7, #4] 800539c: 4a17 ldr r2, [pc, #92] @ (80053fc ) 800539e: 4293 cmp r3, r2 80053a0: d101 bne.n 80053a6 80053a2: 2309 movs r3, #9 80053a4: e02d b.n 8005402 80053a6: 230a movs r3, #10 80053a8: e02b b.n 8005402 80053aa: 2308 movs r3, #8 80053ac: e029 b.n 8005402 80053ae: 2307 movs r3, #7 80053b0: e027 b.n 8005402 80053b2: 2306 movs r3, #6 80053b4: e025 b.n 8005402 80053b6: 2305 movs r3, #5 80053b8: e023 b.n 8005402 80053ba: 2304 movs r3, #4 80053bc: e021 b.n 8005402 80053be: 2303 movs r3, #3 80053c0: e01f b.n 8005402 80053c2: 2302 movs r3, #2 80053c4: e01d b.n 8005402 80053c6: 2301 movs r3, #1 80053c8: e01b b.n 8005402 80053ca: bf00 nop 80053cc: 58000080 .word 0x58000080 80053d0: 58024400 .word 0x58024400 80053d4: 58000400 .word 0x58000400 80053d8: 58020000 .word 0x58020000 80053dc: 58020400 .word 0x58020400 80053e0: 58020800 .word 0x58020800 80053e4: 58020c00 .word 0x58020c00 80053e8: 58021000 .word 0x58021000 80053ec: 58021400 .word 0x58021400 80053f0: 58021800 .word 0x58021800 80053f4: 58021c00 .word 0x58021c00 80053f8: 58022000 .word 0x58022000 80053fc: 58022400 .word 0x58022400 8005400: 2300 movs r3, #0 8005402: 69fa ldr r2, [r7, #28] 8005404: f002 0203 and.w r2, r2, #3 8005408: 0092 lsls r2, r2, #2 800540a: 4093 lsls r3, r2 800540c: 69ba ldr r2, [r7, #24] 800540e: 4313 orrs r3, r2 8005410: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8005412: 4938 ldr r1, [pc, #224] @ (80054f4 ) 8005414: 69fb ldr r3, [r7, #28] 8005416: 089b lsrs r3, r3, #2 8005418: 3302 adds r3, #2 800541a: 69ba ldr r2, [r7, #24] 800541c: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 8005420: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005424: 681b ldr r3, [r3, #0] 8005426: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8005428: 693b ldr r3, [r7, #16] 800542a: 43db mvns r3, r3 800542c: 69ba ldr r2, [r7, #24] 800542e: 4013 ands r3, r2 8005430: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8005432: 683b ldr r3, [r7, #0] 8005434: 685b ldr r3, [r3, #4] 8005436: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800543a: 2b00 cmp r3, #0 800543c: d003 beq.n 8005446 { temp |= iocurrent; 800543e: 69ba ldr r2, [r7, #24] 8005440: 693b ldr r3, [r7, #16] 8005442: 4313 orrs r3, r2 8005444: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 8005446: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800544a: 69bb ldr r3, [r7, #24] 800544c: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800544e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8005452: 685b ldr r3, [r3, #4] 8005454: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8005456: 693b ldr r3, [r7, #16] 8005458: 43db mvns r3, r3 800545a: 69ba ldr r2, [r7, #24] 800545c: 4013 ands r3, r2 800545e: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8005460: 683b ldr r3, [r7, #0] 8005462: 685b ldr r3, [r3, #4] 8005464: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8005468: 2b00 cmp r3, #0 800546a: d003 beq.n 8005474 { temp |= iocurrent; 800546c: 69ba ldr r2, [r7, #24] 800546e: 693b ldr r3, [r7, #16] 8005470: 4313 orrs r3, r2 8005472: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 8005474: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8005478: 69bb ldr r3, [r7, #24] 800547a: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800547c: 697b ldr r3, [r7, #20] 800547e: 685b ldr r3, [r3, #4] 8005480: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 8005482: 693b ldr r3, [r7, #16] 8005484: 43db mvns r3, r3 8005486: 69ba ldr r2, [r7, #24] 8005488: 4013 ands r3, r2 800548a: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800548c: 683b ldr r3, [r7, #0] 800548e: 685b ldr r3, [r3, #4] 8005490: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005494: 2b00 cmp r3, #0 8005496: d003 beq.n 80054a0 { temp |= iocurrent; 8005498: 69ba ldr r2, [r7, #24] 800549a: 693b ldr r3, [r7, #16] 800549c: 4313 orrs r3, r2 800549e: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 80054a0: 697b ldr r3, [r7, #20] 80054a2: 69ba ldr r2, [r7, #24] 80054a4: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 80054a6: 697b ldr r3, [r7, #20] 80054a8: 681b ldr r3, [r3, #0] 80054aa: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 80054ac: 693b ldr r3, [r7, #16] 80054ae: 43db mvns r3, r3 80054b0: 69ba ldr r2, [r7, #24] 80054b2: 4013 ands r3, r2 80054b4: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 80054b6: 683b ldr r3, [r7, #0] 80054b8: 685b ldr r3, [r3, #4] 80054ba: f403 3380 and.w r3, r3, #65536 @ 0x10000 80054be: 2b00 cmp r3, #0 80054c0: d003 beq.n 80054ca { temp |= iocurrent; 80054c2: 69ba ldr r2, [r7, #24] 80054c4: 693b ldr r3, [r7, #16] 80054c6: 4313 orrs r3, r2 80054c8: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 80054ca: 697b ldr r3, [r7, #20] 80054cc: 69ba ldr r2, [r7, #24] 80054ce: 601a str r2, [r3, #0] } } position++; 80054d0: 69fb ldr r3, [r7, #28] 80054d2: 3301 adds r3, #1 80054d4: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 80054d6: 683b ldr r3, [r7, #0] 80054d8: 681a ldr r2, [r3, #0] 80054da: 69fb ldr r3, [r7, #28] 80054dc: fa22 f303 lsr.w r3, r2, r3 80054e0: 2b00 cmp r3, #0 80054e2: f47f ae63 bne.w 80051ac } } 80054e6: bf00 nop 80054e8: bf00 nop 80054ea: 3724 adds r7, #36 @ 0x24 80054ec: 46bd mov sp, r7 80054ee: f85d 7b04 ldr.w r7, [sp], #4 80054f2: 4770 bx lr 80054f4: 58000400 .word 0x58000400 080054f8 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 80054f8: b580 push {r7, lr} 80054fa: b084 sub sp, #16 80054fc: af00 add r7, sp, #0 80054fe: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 8005500: 4b19 ldr r3, [pc, #100] @ (8005568 ) 8005502: 68db ldr r3, [r3, #12] 8005504: f003 0304 and.w r3, r3, #4 8005508: 2b04 cmp r3, #4 800550a: d00a beq.n 8005522 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800550c: 4b16 ldr r3, [pc, #88] @ (8005568 ) 800550e: 68db ldr r3, [r3, #12] 8005510: f003 0307 and.w r3, r3, #7 8005514: 687a ldr r2, [r7, #4] 8005516: 429a cmp r2, r3 8005518: d001 beq.n 800551e { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800551a: 2301 movs r3, #1 800551c: e01f b.n 800555e else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800551e: 2300 movs r3, #0 8005520: e01d b.n 800555e } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 8005522: 4b11 ldr r3, [pc, #68] @ (8005568 ) 8005524: 68db ldr r3, [r3, #12] 8005526: f023 0207 bic.w r2, r3, #7 800552a: 490f ldr r1, [pc, #60] @ (8005568 ) 800552c: 687b ldr r3, [r7, #4] 800552e: 4313 orrs r3, r2 8005530: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 8005532: f7fd f895 bl 8002660 8005536: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 8005538: e009 b.n 800554e { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800553a: f7fd f891 bl 8002660 800553e: 4602 mov r2, r0 8005540: 68fb ldr r3, [r7, #12] 8005542: 1ad3 subs r3, r2, r3 8005544: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8005548: d901 bls.n 800554e { return HAL_ERROR; 800554a: 2301 movs r3, #1 800554c: e007 b.n 800555e while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800554e: 4b06 ldr r3, [pc, #24] @ (8005568 ) 8005550: 685b ldr r3, [r3, #4] 8005552: f403 5300 and.w r3, r3, #8192 @ 0x2000 8005556: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800555a: d1ee bne.n 800553a } } } #endif /* defined (SMPS) */ return HAL_OK; 800555c: 2300 movs r3, #0 } 800555e: 4618 mov r0, r3 8005560: 3710 adds r7, #16 8005562: 46bd mov sp, r7 8005564: bd80 pop {r7, pc} 8005566: bf00 nop 8005568: 58024800 .word 0x58024800 0800556c : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800556c: b580 push {r7, lr} 800556e: b08c sub sp, #48 @ 0x30 8005570: af00 add r7, sp, #0 8005572: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8005574: 687b ldr r3, [r7, #4] 8005576: 2b00 cmp r3, #0 8005578: d102 bne.n 8005580 { return HAL_ERROR; 800557a: 2301 movs r3, #1 800557c: f000 bc48 b.w 8005e10 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8005580: 687b ldr r3, [r7, #4] 8005582: 681b ldr r3, [r3, #0] 8005584: f003 0301 and.w r3, r3, #1 8005588: 2b00 cmp r3, #0 800558a: f000 8088 beq.w 800569e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800558e: 4b99 ldr r3, [pc, #612] @ (80057f4 ) 8005590: 691b ldr r3, [r3, #16] 8005592: f003 0338 and.w r3, r3, #56 @ 0x38 8005596: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8005598: 4b96 ldr r3, [pc, #600] @ (80057f4 ) 800559a: 6a9b ldr r3, [r3, #40] @ 0x28 800559c: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800559e: 6afb ldr r3, [r7, #44] @ 0x2c 80055a0: 2b10 cmp r3, #16 80055a2: d007 beq.n 80055b4 80055a4: 6afb ldr r3, [r7, #44] @ 0x2c 80055a6: 2b18 cmp r3, #24 80055a8: d111 bne.n 80055ce 80055aa: 6abb ldr r3, [r7, #40] @ 0x28 80055ac: f003 0303 and.w r3, r3, #3 80055b0: 2b02 cmp r3, #2 80055b2: d10c bne.n 80055ce { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80055b4: 4b8f ldr r3, [pc, #572] @ (80057f4 ) 80055b6: 681b ldr r3, [r3, #0] 80055b8: f403 3300 and.w r3, r3, #131072 @ 0x20000 80055bc: 2b00 cmp r3, #0 80055be: d06d beq.n 800569c 80055c0: 687b ldr r3, [r7, #4] 80055c2: 685b ldr r3, [r3, #4] 80055c4: 2b00 cmp r3, #0 80055c6: d169 bne.n 800569c { return HAL_ERROR; 80055c8: 2301 movs r3, #1 80055ca: f000 bc21 b.w 8005e10 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80055ce: 687b ldr r3, [r7, #4] 80055d0: 685b ldr r3, [r3, #4] 80055d2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80055d6: d106 bne.n 80055e6 80055d8: 4b86 ldr r3, [pc, #536] @ (80057f4 ) 80055da: 681b ldr r3, [r3, #0] 80055dc: 4a85 ldr r2, [pc, #532] @ (80057f4 ) 80055de: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80055e2: 6013 str r3, [r2, #0] 80055e4: e02e b.n 8005644 80055e6: 687b ldr r3, [r7, #4] 80055e8: 685b ldr r3, [r3, #4] 80055ea: 2b00 cmp r3, #0 80055ec: d10c bne.n 8005608 80055ee: 4b81 ldr r3, [pc, #516] @ (80057f4 ) 80055f0: 681b ldr r3, [r3, #0] 80055f2: 4a80 ldr r2, [pc, #512] @ (80057f4 ) 80055f4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80055f8: 6013 str r3, [r2, #0] 80055fa: 4b7e ldr r3, [pc, #504] @ (80057f4 ) 80055fc: 681b ldr r3, [r3, #0] 80055fe: 4a7d ldr r2, [pc, #500] @ (80057f4 ) 8005600: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8005604: 6013 str r3, [r2, #0] 8005606: e01d b.n 8005644 8005608: 687b ldr r3, [r7, #4] 800560a: 685b ldr r3, [r3, #4] 800560c: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8005610: d10c bne.n 800562c 8005612: 4b78 ldr r3, [pc, #480] @ (80057f4 ) 8005614: 681b ldr r3, [r3, #0] 8005616: 4a77 ldr r2, [pc, #476] @ (80057f4 ) 8005618: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800561c: 6013 str r3, [r2, #0] 800561e: 4b75 ldr r3, [pc, #468] @ (80057f4 ) 8005620: 681b ldr r3, [r3, #0] 8005622: 4a74 ldr r2, [pc, #464] @ (80057f4 ) 8005624: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005628: 6013 str r3, [r2, #0] 800562a: e00b b.n 8005644 800562c: 4b71 ldr r3, [pc, #452] @ (80057f4 ) 800562e: 681b ldr r3, [r3, #0] 8005630: 4a70 ldr r2, [pc, #448] @ (80057f4 ) 8005632: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8005636: 6013 str r3, [r2, #0] 8005638: 4b6e ldr r3, [pc, #440] @ (80057f4 ) 800563a: 681b ldr r3, [r3, #0] 800563c: 4a6d ldr r2, [pc, #436] @ (80057f4 ) 800563e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8005642: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8005644: 687b ldr r3, [r7, #4] 8005646: 685b ldr r3, [r3, #4] 8005648: 2b00 cmp r3, #0 800564a: d013 beq.n 8005674 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800564c: f7fd f808 bl 8002660 8005650: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8005652: e008 b.n 8005666 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8005654: f7fd f804 bl 8002660 8005658: 4602 mov r2, r0 800565a: 6a7b ldr r3, [r7, #36] @ 0x24 800565c: 1ad3 subs r3, r2, r3 800565e: 2b64 cmp r3, #100 @ 0x64 8005660: d901 bls.n 8005666 { return HAL_TIMEOUT; 8005662: 2303 movs r3, #3 8005664: e3d4 b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8005666: 4b63 ldr r3, [pc, #396] @ (80057f4 ) 8005668: 681b ldr r3, [r3, #0] 800566a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800566e: 2b00 cmp r3, #0 8005670: d0f0 beq.n 8005654 8005672: e014 b.n 800569e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005674: f7fc fff4 bl 8002660 8005678: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800567a: e008 b.n 800568e { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800567c: f7fc fff0 bl 8002660 8005680: 4602 mov r2, r0 8005682: 6a7b ldr r3, [r7, #36] @ 0x24 8005684: 1ad3 subs r3, r2, r3 8005686: 2b64 cmp r3, #100 @ 0x64 8005688: d901 bls.n 800568e { return HAL_TIMEOUT; 800568a: 2303 movs r3, #3 800568c: e3c0 b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800568e: 4b59 ldr r3, [pc, #356] @ (80057f4 ) 8005690: 681b ldr r3, [r3, #0] 8005692: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005696: 2b00 cmp r3, #0 8005698: d1f0 bne.n 800567c 800569a: e000 b.n 800569e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800569c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800569e: 687b ldr r3, [r7, #4] 80056a0: 681b ldr r3, [r3, #0] 80056a2: f003 0302 and.w r3, r3, #2 80056a6: 2b00 cmp r3, #0 80056a8: f000 80ca beq.w 8005840 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 80056ac: 4b51 ldr r3, [pc, #324] @ (80057f4 ) 80056ae: 691b ldr r3, [r3, #16] 80056b0: f003 0338 and.w r3, r3, #56 @ 0x38 80056b4: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 80056b6: 4b4f ldr r3, [pc, #316] @ (80057f4 ) 80056b8: 6a9b ldr r3, [r3, #40] @ 0x28 80056ba: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 80056bc: 6a3b ldr r3, [r7, #32] 80056be: 2b00 cmp r3, #0 80056c0: d007 beq.n 80056d2 80056c2: 6a3b ldr r3, [r7, #32] 80056c4: 2b18 cmp r3, #24 80056c6: d156 bne.n 8005776 80056c8: 69fb ldr r3, [r7, #28] 80056ca: f003 0303 and.w r3, r3, #3 80056ce: 2b00 cmp r3, #0 80056d0: d151 bne.n 8005776 { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 80056d2: 4b48 ldr r3, [pc, #288] @ (80057f4 ) 80056d4: 681b ldr r3, [r3, #0] 80056d6: f003 0304 and.w r3, r3, #4 80056da: 2b00 cmp r3, #0 80056dc: d005 beq.n 80056ea 80056de: 687b ldr r3, [r7, #4] 80056e0: 68db ldr r3, [r3, #12] 80056e2: 2b00 cmp r3, #0 80056e4: d101 bne.n 80056ea { return HAL_ERROR; 80056e6: 2301 movs r3, #1 80056e8: e392 b.n 8005e10 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 80056ea: 4b42 ldr r3, [pc, #264] @ (80057f4 ) 80056ec: 681b ldr r3, [r3, #0] 80056ee: f023 0219 bic.w r2, r3, #25 80056f2: 687b ldr r3, [r7, #4] 80056f4: 68db ldr r3, [r3, #12] 80056f6: 493f ldr r1, [pc, #252] @ (80057f4 ) 80056f8: 4313 orrs r3, r2 80056fa: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80056fc: f7fc ffb0 bl 8002660 8005700: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8005702: e008 b.n 8005716 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005704: f7fc ffac bl 8002660 8005708: 4602 mov r2, r0 800570a: 6a7b ldr r3, [r7, #36] @ 0x24 800570c: 1ad3 subs r3, r2, r3 800570e: 2b02 cmp r3, #2 8005710: d901 bls.n 8005716 { return HAL_TIMEOUT; 8005712: 2303 movs r3, #3 8005714: e37c b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8005716: 4b37 ldr r3, [pc, #220] @ (80057f4 ) 8005718: 681b ldr r3, [r3, #0] 800571a: f003 0304 and.w r3, r3, #4 800571e: 2b00 cmp r3, #0 8005720: d0f0 beq.n 8005704 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005722: f7fc ffa9 bl 8002678 8005726: 4603 mov r3, r0 8005728: f241 0203 movw r2, #4099 @ 0x1003 800572c: 4293 cmp r3, r2 800572e: d817 bhi.n 8005760 8005730: 687b ldr r3, [r7, #4] 8005732: 691b ldr r3, [r3, #16] 8005734: 2b40 cmp r3, #64 @ 0x40 8005736: d108 bne.n 800574a 8005738: 4b2e ldr r3, [pc, #184] @ (80057f4 ) 800573a: 685b ldr r3, [r3, #4] 800573c: f423 337c bic.w r3, r3, #258048 @ 0x3f000 8005740: 4a2c ldr r2, [pc, #176] @ (80057f4 ) 8005742: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8005746: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8005748: e07a b.n 8005840 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800574a: 4b2a ldr r3, [pc, #168] @ (80057f4 ) 800574c: 685b ldr r3, [r3, #4] 800574e: f423 327c bic.w r2, r3, #258048 @ 0x3f000 8005752: 687b ldr r3, [r7, #4] 8005754: 691b ldr r3, [r3, #16] 8005756: 031b lsls r3, r3, #12 8005758: 4926 ldr r1, [pc, #152] @ (80057f4 ) 800575a: 4313 orrs r3, r2 800575c: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800575e: e06f b.n 8005840 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8005760: 4b24 ldr r3, [pc, #144] @ (80057f4 ) 8005762: 685b ldr r3, [r3, #4] 8005764: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8005768: 687b ldr r3, [r7, #4] 800576a: 691b ldr r3, [r3, #16] 800576c: 061b lsls r3, r3, #24 800576e: 4921 ldr r1, [pc, #132] @ (80057f4 ) 8005770: 4313 orrs r3, r2 8005772: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8005774: e064 b.n 8005840 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 8005776: 687b ldr r3, [r7, #4] 8005778: 68db ldr r3, [r3, #12] 800577a: 2b00 cmp r3, #0 800577c: d047 beq.n 800580e { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800577e: 4b1d ldr r3, [pc, #116] @ (80057f4 ) 8005780: 681b ldr r3, [r3, #0] 8005782: f023 0219 bic.w r2, r3, #25 8005786: 687b ldr r3, [r7, #4] 8005788: 68db ldr r3, [r3, #12] 800578a: 491a ldr r1, [pc, #104] @ (80057f4 ) 800578c: 4313 orrs r3, r2 800578e: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005790: f7fc ff66 bl 8002660 8005794: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8005796: e008 b.n 80057aa { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005798: f7fc ff62 bl 8002660 800579c: 4602 mov r2, r0 800579e: 6a7b ldr r3, [r7, #36] @ 0x24 80057a0: 1ad3 subs r3, r2, r3 80057a2: 2b02 cmp r3, #2 80057a4: d901 bls.n 80057aa { return HAL_TIMEOUT; 80057a6: 2303 movs r3, #3 80057a8: e332 b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 80057aa: 4b12 ldr r3, [pc, #72] @ (80057f4 ) 80057ac: 681b ldr r3, [r3, #0] 80057ae: f003 0304 and.w r3, r3, #4 80057b2: 2b00 cmp r3, #0 80057b4: d0f0 beq.n 8005798 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80057b6: f7fc ff5f bl 8002678 80057ba: 4603 mov r3, r0 80057bc: f241 0203 movw r2, #4099 @ 0x1003 80057c0: 4293 cmp r3, r2 80057c2: d819 bhi.n 80057f8 80057c4: 687b ldr r3, [r7, #4] 80057c6: 691b ldr r3, [r3, #16] 80057c8: 2b40 cmp r3, #64 @ 0x40 80057ca: d108 bne.n 80057de 80057cc: 4b09 ldr r3, [pc, #36] @ (80057f4 ) 80057ce: 685b ldr r3, [r3, #4] 80057d0: f423 337c bic.w r3, r3, #258048 @ 0x3f000 80057d4: 4a07 ldr r2, [pc, #28] @ (80057f4 ) 80057d6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80057da: 6053 str r3, [r2, #4] 80057dc: e030 b.n 8005840 80057de: 4b05 ldr r3, [pc, #20] @ (80057f4 ) 80057e0: 685b ldr r3, [r3, #4] 80057e2: f423 327c bic.w r2, r3, #258048 @ 0x3f000 80057e6: 687b ldr r3, [r7, #4] 80057e8: 691b ldr r3, [r3, #16] 80057ea: 031b lsls r3, r3, #12 80057ec: 4901 ldr r1, [pc, #4] @ (80057f4 ) 80057ee: 4313 orrs r3, r2 80057f0: 604b str r3, [r1, #4] 80057f2: e025 b.n 8005840 80057f4: 58024400 .word 0x58024400 80057f8: 4b9a ldr r3, [pc, #616] @ (8005a64 ) 80057fa: 685b ldr r3, [r3, #4] 80057fc: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 8005800: 687b ldr r3, [r7, #4] 8005802: 691b ldr r3, [r3, #16] 8005804: 061b lsls r3, r3, #24 8005806: 4997 ldr r1, [pc, #604] @ (8005a64 ) 8005808: 4313 orrs r3, r2 800580a: 604b str r3, [r1, #4] 800580c: e018 b.n 8005840 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800580e: 4b95 ldr r3, [pc, #596] @ (8005a64 ) 8005810: 681b ldr r3, [r3, #0] 8005812: 4a94 ldr r2, [pc, #592] @ (8005a64 ) 8005814: f023 0301 bic.w r3, r3, #1 8005818: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800581a: f7fc ff21 bl 8002660 800581e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8005820: e008 b.n 8005834 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8005822: f7fc ff1d bl 8002660 8005826: 4602 mov r2, r0 8005828: 6a7b ldr r3, [r7, #36] @ 0x24 800582a: 1ad3 subs r3, r2, r3 800582c: 2b02 cmp r3, #2 800582e: d901 bls.n 8005834 { return HAL_TIMEOUT; 8005830: 2303 movs r3, #3 8005832: e2ed b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 8005834: 4b8b ldr r3, [pc, #556] @ (8005a64 ) 8005836: 681b ldr r3, [r3, #0] 8005838: f003 0304 and.w r3, r3, #4 800583c: 2b00 cmp r3, #0 800583e: d1f0 bne.n 8005822 } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 8005840: 687b ldr r3, [r7, #4] 8005842: 681b ldr r3, [r3, #0] 8005844: f003 0310 and.w r3, r3, #16 8005848: 2b00 cmp r3, #0 800584a: f000 80a9 beq.w 80059a0 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800584e: 4b85 ldr r3, [pc, #532] @ (8005a64 ) 8005850: 691b ldr r3, [r3, #16] 8005852: f003 0338 and.w r3, r3, #56 @ 0x38 8005856: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 8005858: 4b82 ldr r3, [pc, #520] @ (8005a64 ) 800585a: 6a9b ldr r3, [r3, #40] @ 0x28 800585c: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800585e: 69bb ldr r3, [r7, #24] 8005860: 2b08 cmp r3, #8 8005862: d007 beq.n 8005874 8005864: 69bb ldr r3, [r7, #24] 8005866: 2b18 cmp r3, #24 8005868: d13a bne.n 80058e0 800586a: 697b ldr r3, [r7, #20] 800586c: f003 0303 and.w r3, r3, #3 8005870: 2b01 cmp r3, #1 8005872: d135 bne.n 80058e0 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 8005874: 4b7b ldr r3, [pc, #492] @ (8005a64 ) 8005876: 681b ldr r3, [r3, #0] 8005878: f403 7380 and.w r3, r3, #256 @ 0x100 800587c: 2b00 cmp r3, #0 800587e: d005 beq.n 800588c 8005880: 687b ldr r3, [r7, #4] 8005882: 69db ldr r3, [r3, #28] 8005884: 2b80 cmp r3, #128 @ 0x80 8005886: d001 beq.n 800588c { return HAL_ERROR; 8005888: 2301 movs r3, #1 800588a: e2c1 b.n 8005e10 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800588c: f7fc fef4 bl 8002678 8005890: 4603 mov r3, r0 8005892: f241 0203 movw r2, #4099 @ 0x1003 8005896: 4293 cmp r3, r2 8005898: d817 bhi.n 80058ca 800589a: 687b ldr r3, [r7, #4] 800589c: 6a1b ldr r3, [r3, #32] 800589e: 2b20 cmp r3, #32 80058a0: d108 bne.n 80058b4 80058a2: 4b70 ldr r3, [pc, #448] @ (8005a64 ) 80058a4: 685b ldr r3, [r3, #4] 80058a6: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 80058aa: 4a6e ldr r2, [pc, #440] @ (8005a64 ) 80058ac: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80058b0: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80058b2: e075 b.n 80059a0 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80058b4: 4b6b ldr r3, [pc, #428] @ (8005a64 ) 80058b6: 685b ldr r3, [r3, #4] 80058b8: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 80058bc: 687b ldr r3, [r7, #4] 80058be: 6a1b ldr r3, [r3, #32] 80058c0: 069b lsls r3, r3, #26 80058c2: 4968 ldr r1, [pc, #416] @ (8005a64 ) 80058c4: 4313 orrs r3, r2 80058c6: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80058c8: e06a b.n 80059a0 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 80058ca: 4b66 ldr r3, [pc, #408] @ (8005a64 ) 80058cc: 68db ldr r3, [r3, #12] 80058ce: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 80058d2: 687b ldr r3, [r7, #4] 80058d4: 6a1b ldr r3, [r3, #32] 80058d6: 061b lsls r3, r3, #24 80058d8: 4962 ldr r1, [pc, #392] @ (8005a64 ) 80058da: 4313 orrs r3, r2 80058dc: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 80058de: e05f b.n 80059a0 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 80058e0: 687b ldr r3, [r7, #4] 80058e2: 69db ldr r3, [r3, #28] 80058e4: 2b00 cmp r3, #0 80058e6: d042 beq.n 800596e { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 80058e8: 4b5e ldr r3, [pc, #376] @ (8005a64 ) 80058ea: 681b ldr r3, [r3, #0] 80058ec: 4a5d ldr r2, [pc, #372] @ (8005a64 ) 80058ee: f043 0380 orr.w r3, r3, #128 @ 0x80 80058f2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80058f4: f7fc feb4 bl 8002660 80058f8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 80058fa: e008 b.n 800590e { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 80058fc: f7fc feb0 bl 8002660 8005900: 4602 mov r2, r0 8005902: 6a7b ldr r3, [r7, #36] @ 0x24 8005904: 1ad3 subs r3, r2, r3 8005906: 2b02 cmp r3, #2 8005908: d901 bls.n 800590e { return HAL_TIMEOUT; 800590a: 2303 movs r3, #3 800590c: e280 b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800590e: 4b55 ldr r3, [pc, #340] @ (8005a64 ) 8005910: 681b ldr r3, [r3, #0] 8005912: f403 7380 and.w r3, r3, #256 @ 0x100 8005916: 2b00 cmp r3, #0 8005918: d0f0 beq.n 80058fc } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800591a: f7fc fead bl 8002678 800591e: 4603 mov r3, r0 8005920: f241 0203 movw r2, #4099 @ 0x1003 8005924: 4293 cmp r3, r2 8005926: d817 bhi.n 8005958 8005928: 687b ldr r3, [r7, #4] 800592a: 6a1b ldr r3, [r3, #32] 800592c: 2b20 cmp r3, #32 800592e: d108 bne.n 8005942 8005930: 4b4c ldr r3, [pc, #304] @ (8005a64 ) 8005932: 685b ldr r3, [r3, #4] 8005934: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 8005938: 4a4a ldr r2, [pc, #296] @ (8005a64 ) 800593a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800593e: 6053 str r3, [r2, #4] 8005940: e02e b.n 80059a0 8005942: 4b48 ldr r3, [pc, #288] @ (8005a64 ) 8005944: 685b ldr r3, [r3, #4] 8005946: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800594a: 687b ldr r3, [r7, #4] 800594c: 6a1b ldr r3, [r3, #32] 800594e: 069b lsls r3, r3, #26 8005950: 4944 ldr r1, [pc, #272] @ (8005a64 ) 8005952: 4313 orrs r3, r2 8005954: 604b str r3, [r1, #4] 8005956: e023 b.n 80059a0 8005958: 4b42 ldr r3, [pc, #264] @ (8005a64 ) 800595a: 68db ldr r3, [r3, #12] 800595c: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 8005960: 687b ldr r3, [r7, #4] 8005962: 6a1b ldr r3, [r3, #32] 8005964: 061b lsls r3, r3, #24 8005966: 493f ldr r1, [pc, #252] @ (8005a64 ) 8005968: 4313 orrs r3, r2 800596a: 60cb str r3, [r1, #12] 800596c: e018 b.n 80059a0 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800596e: 4b3d ldr r3, [pc, #244] @ (8005a64 ) 8005970: 681b ldr r3, [r3, #0] 8005972: 4a3c ldr r2, [pc, #240] @ (8005a64 ) 8005974: f023 0380 bic.w r3, r3, #128 @ 0x80 8005978: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800597a: f7fc fe71 bl 8002660 800597e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8005980: e008 b.n 8005994 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 8005982: f7fc fe6d bl 8002660 8005986: 4602 mov r2, r0 8005988: 6a7b ldr r3, [r7, #36] @ 0x24 800598a: 1ad3 subs r3, r2, r3 800598c: 2b02 cmp r3, #2 800598e: d901 bls.n 8005994 { return HAL_TIMEOUT; 8005990: 2303 movs r3, #3 8005992: e23d b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 8005994: 4b33 ldr r3, [pc, #204] @ (8005a64 ) 8005996: 681b ldr r3, [r3, #0] 8005998: f403 7380 and.w r3, r3, #256 @ 0x100 800599c: 2b00 cmp r3, #0 800599e: d1f0 bne.n 8005982 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 80059a0: 687b ldr r3, [r7, #4] 80059a2: 681b ldr r3, [r3, #0] 80059a4: f003 0308 and.w r3, r3, #8 80059a8: 2b00 cmp r3, #0 80059aa: d036 beq.n 8005a1a { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 80059ac: 687b ldr r3, [r7, #4] 80059ae: 695b ldr r3, [r3, #20] 80059b0: 2b00 cmp r3, #0 80059b2: d019 beq.n 80059e8 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 80059b4: 4b2b ldr r3, [pc, #172] @ (8005a64 ) 80059b6: 6f5b ldr r3, [r3, #116] @ 0x74 80059b8: 4a2a ldr r2, [pc, #168] @ (8005a64 ) 80059ba: f043 0301 orr.w r3, r3, #1 80059be: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80059c0: f7fc fe4e bl 8002660 80059c4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80059c6: e008 b.n 80059da { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80059c8: f7fc fe4a bl 8002660 80059cc: 4602 mov r2, r0 80059ce: 6a7b ldr r3, [r7, #36] @ 0x24 80059d0: 1ad3 subs r3, r2, r3 80059d2: 2b02 cmp r3, #2 80059d4: d901 bls.n 80059da { return HAL_TIMEOUT; 80059d6: 2303 movs r3, #3 80059d8: e21a b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 80059da: 4b22 ldr r3, [pc, #136] @ (8005a64 ) 80059dc: 6f5b ldr r3, [r3, #116] @ 0x74 80059de: f003 0302 and.w r3, r3, #2 80059e2: 2b00 cmp r3, #0 80059e4: d0f0 beq.n 80059c8 80059e6: e018 b.n 8005a1a } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 80059e8: 4b1e ldr r3, [pc, #120] @ (8005a64 ) 80059ea: 6f5b ldr r3, [r3, #116] @ 0x74 80059ec: 4a1d ldr r2, [pc, #116] @ (8005a64 ) 80059ee: f023 0301 bic.w r3, r3, #1 80059f2: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 80059f4: f7fc fe34 bl 8002660 80059f8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 80059fa: e008 b.n 8005a0e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80059fc: f7fc fe30 bl 8002660 8005a00: 4602 mov r2, r0 8005a02: 6a7b ldr r3, [r7, #36] @ 0x24 8005a04: 1ad3 subs r3, r2, r3 8005a06: 2b02 cmp r3, #2 8005a08: d901 bls.n 8005a0e { return HAL_TIMEOUT; 8005a0a: 2303 movs r3, #3 8005a0c: e200 b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 8005a0e: 4b15 ldr r3, [pc, #84] @ (8005a64 ) 8005a10: 6f5b ldr r3, [r3, #116] @ 0x74 8005a12: f003 0302 and.w r3, r3, #2 8005a16: 2b00 cmp r3, #0 8005a18: d1f0 bne.n 80059fc } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8005a1a: 687b ldr r3, [r7, #4] 8005a1c: 681b ldr r3, [r3, #0] 8005a1e: f003 0320 and.w r3, r3, #32 8005a22: 2b00 cmp r3, #0 8005a24: d039 beq.n 8005a9a { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 8005a26: 687b ldr r3, [r7, #4] 8005a28: 699b ldr r3, [r3, #24] 8005a2a: 2b00 cmp r3, #0 8005a2c: d01c beq.n 8005a68 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8005a2e: 4b0d ldr r3, [pc, #52] @ (8005a64 ) 8005a30: 681b ldr r3, [r3, #0] 8005a32: 4a0c ldr r2, [pc, #48] @ (8005a64 ) 8005a34: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8005a38: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 8005a3a: f7fc fe11 bl 8002660 8005a3e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 8005a40: e008 b.n 8005a54 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8005a42: f7fc fe0d bl 8002660 8005a46: 4602 mov r2, r0 8005a48: 6a7b ldr r3, [r7, #36] @ 0x24 8005a4a: 1ad3 subs r3, r2, r3 8005a4c: 2b02 cmp r3, #2 8005a4e: d901 bls.n 8005a54 { return HAL_TIMEOUT; 8005a50: 2303 movs r3, #3 8005a52: e1dd b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 8005a54: 4b03 ldr r3, [pc, #12] @ (8005a64 ) 8005a56: 681b ldr r3, [r3, #0] 8005a58: f403 5300 and.w r3, r3, #8192 @ 0x2000 8005a5c: 2b00 cmp r3, #0 8005a5e: d0f0 beq.n 8005a42 8005a60: e01b b.n 8005a9a 8005a62: bf00 nop 8005a64: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8005a68: 4b9b ldr r3, [pc, #620] @ (8005cd8 ) 8005a6a: 681b ldr r3, [r3, #0] 8005a6c: 4a9a ldr r2, [pc, #616] @ (8005cd8 ) 8005a6e: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8005a72: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 8005a74: f7fc fdf4 bl 8002660 8005a78: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8005a7a: e008 b.n 8005a8e { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8005a7c: f7fc fdf0 bl 8002660 8005a80: 4602 mov r2, r0 8005a82: 6a7b ldr r3, [r7, #36] @ 0x24 8005a84: 1ad3 subs r3, r2, r3 8005a86: 2b02 cmp r3, #2 8005a88: d901 bls.n 8005a8e { return HAL_TIMEOUT; 8005a8a: 2303 movs r3, #3 8005a8c: e1c0 b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 8005a8e: 4b92 ldr r3, [pc, #584] @ (8005cd8 ) 8005a90: 681b ldr r3, [r3, #0] 8005a92: f403 5300 and.w r3, r3, #8192 @ 0x2000 8005a96: 2b00 cmp r3, #0 8005a98: d1f0 bne.n 8005a7c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8005a9a: 687b ldr r3, [r7, #4] 8005a9c: 681b ldr r3, [r3, #0] 8005a9e: f003 0304 and.w r3, r3, #4 8005aa2: 2b00 cmp r3, #0 8005aa4: f000 8081 beq.w 8005baa { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 8005aa8: 4b8c ldr r3, [pc, #560] @ (8005cdc ) 8005aaa: 681b ldr r3, [r3, #0] 8005aac: 4a8b ldr r2, [pc, #556] @ (8005cdc ) 8005aae: f443 7380 orr.w r3, r3, #256 @ 0x100 8005ab2: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8005ab4: f7fc fdd4 bl 8002660 8005ab8: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8005aba: e008 b.n 8005ace { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8005abc: f7fc fdd0 bl 8002660 8005ac0: 4602 mov r2, r0 8005ac2: 6a7b ldr r3, [r7, #36] @ 0x24 8005ac4: 1ad3 subs r3, r2, r3 8005ac6: 2b64 cmp r3, #100 @ 0x64 8005ac8: d901 bls.n 8005ace { return HAL_TIMEOUT; 8005aca: 2303 movs r3, #3 8005acc: e1a0 b.n 8005e10 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8005ace: 4b83 ldr r3, [pc, #524] @ (8005cdc ) 8005ad0: 681b ldr r3, [r3, #0] 8005ad2: f403 7380 and.w r3, r3, #256 @ 0x100 8005ad6: 2b00 cmp r3, #0 8005ad8: d0f0 beq.n 8005abc } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8005ada: 687b ldr r3, [r7, #4] 8005adc: 689b ldr r3, [r3, #8] 8005ade: 2b01 cmp r3, #1 8005ae0: d106 bne.n 8005af0 8005ae2: 4b7d ldr r3, [pc, #500] @ (8005cd8 ) 8005ae4: 6f1b ldr r3, [r3, #112] @ 0x70 8005ae6: 4a7c ldr r2, [pc, #496] @ (8005cd8 ) 8005ae8: f043 0301 orr.w r3, r3, #1 8005aec: 6713 str r3, [r2, #112] @ 0x70 8005aee: e02d b.n 8005b4c 8005af0: 687b ldr r3, [r7, #4] 8005af2: 689b ldr r3, [r3, #8] 8005af4: 2b00 cmp r3, #0 8005af6: d10c bne.n 8005b12 8005af8: 4b77 ldr r3, [pc, #476] @ (8005cd8 ) 8005afa: 6f1b ldr r3, [r3, #112] @ 0x70 8005afc: 4a76 ldr r2, [pc, #472] @ (8005cd8 ) 8005afe: f023 0301 bic.w r3, r3, #1 8005b02: 6713 str r3, [r2, #112] @ 0x70 8005b04: 4b74 ldr r3, [pc, #464] @ (8005cd8 ) 8005b06: 6f1b ldr r3, [r3, #112] @ 0x70 8005b08: 4a73 ldr r2, [pc, #460] @ (8005cd8 ) 8005b0a: f023 0304 bic.w r3, r3, #4 8005b0e: 6713 str r3, [r2, #112] @ 0x70 8005b10: e01c b.n 8005b4c 8005b12: 687b ldr r3, [r7, #4] 8005b14: 689b ldr r3, [r3, #8] 8005b16: 2b05 cmp r3, #5 8005b18: d10c bne.n 8005b34 8005b1a: 4b6f ldr r3, [pc, #444] @ (8005cd8 ) 8005b1c: 6f1b ldr r3, [r3, #112] @ 0x70 8005b1e: 4a6e ldr r2, [pc, #440] @ (8005cd8 ) 8005b20: f043 0304 orr.w r3, r3, #4 8005b24: 6713 str r3, [r2, #112] @ 0x70 8005b26: 4b6c ldr r3, [pc, #432] @ (8005cd8 ) 8005b28: 6f1b ldr r3, [r3, #112] @ 0x70 8005b2a: 4a6b ldr r2, [pc, #428] @ (8005cd8 ) 8005b2c: f043 0301 orr.w r3, r3, #1 8005b30: 6713 str r3, [r2, #112] @ 0x70 8005b32: e00b b.n 8005b4c 8005b34: 4b68 ldr r3, [pc, #416] @ (8005cd8 ) 8005b36: 6f1b ldr r3, [r3, #112] @ 0x70 8005b38: 4a67 ldr r2, [pc, #412] @ (8005cd8 ) 8005b3a: f023 0301 bic.w r3, r3, #1 8005b3e: 6713 str r3, [r2, #112] @ 0x70 8005b40: 4b65 ldr r3, [pc, #404] @ (8005cd8 ) 8005b42: 6f1b ldr r3, [r3, #112] @ 0x70 8005b44: 4a64 ldr r2, [pc, #400] @ (8005cd8 ) 8005b46: f023 0304 bic.w r3, r3, #4 8005b4a: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8005b4c: 687b ldr r3, [r7, #4] 8005b4e: 689b ldr r3, [r3, #8] 8005b50: 2b00 cmp r3, #0 8005b52: d015 beq.n 8005b80 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005b54: f7fc fd84 bl 8002660 8005b58: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8005b5a: e00a b.n 8005b72 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005b5c: f7fc fd80 bl 8002660 8005b60: 4602 mov r2, r0 8005b62: 6a7b ldr r3, [r7, #36] @ 0x24 8005b64: 1ad3 subs r3, r2, r3 8005b66: f241 3288 movw r2, #5000 @ 0x1388 8005b6a: 4293 cmp r3, r2 8005b6c: d901 bls.n 8005b72 { return HAL_TIMEOUT; 8005b6e: 2303 movs r3, #3 8005b70: e14e b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8005b72: 4b59 ldr r3, [pc, #356] @ (8005cd8 ) 8005b74: 6f1b ldr r3, [r3, #112] @ 0x70 8005b76: f003 0302 and.w r3, r3, #2 8005b7a: 2b00 cmp r3, #0 8005b7c: d0ee beq.n 8005b5c 8005b7e: e014 b.n 8005baa } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005b80: f7fc fd6e bl 8002660 8005b84: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8005b86: e00a b.n 8005b9e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8005b88: f7fc fd6a bl 8002660 8005b8c: 4602 mov r2, r0 8005b8e: 6a7b ldr r3, [r7, #36] @ 0x24 8005b90: 1ad3 subs r3, r2, r3 8005b92: f241 3288 movw r2, #5000 @ 0x1388 8005b96: 4293 cmp r3, r2 8005b98: d901 bls.n 8005b9e { return HAL_TIMEOUT; 8005b9a: 2303 movs r3, #3 8005b9c: e138 b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 8005b9e: 4b4e ldr r3, [pc, #312] @ (8005cd8 ) 8005ba0: 6f1b ldr r3, [r3, #112] @ 0x70 8005ba2: f003 0302 and.w r3, r3, #2 8005ba6: 2b00 cmp r3, #0 8005ba8: d1ee bne.n 8005b88 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8005baa: 687b ldr r3, [r7, #4] 8005bac: 6a5b ldr r3, [r3, #36] @ 0x24 8005bae: 2b00 cmp r3, #0 8005bb0: f000 812d beq.w 8005e0e { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 8005bb4: 4b48 ldr r3, [pc, #288] @ (8005cd8 ) 8005bb6: 691b ldr r3, [r3, #16] 8005bb8: f003 0338 and.w r3, r3, #56 @ 0x38 8005bbc: 2b18 cmp r3, #24 8005bbe: f000 80bd beq.w 8005d3c { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8005bc2: 687b ldr r3, [r7, #4] 8005bc4: 6a5b ldr r3, [r3, #36] @ 0x24 8005bc6: 2b02 cmp r3, #2 8005bc8: f040 809e bne.w 8005d08 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8005bcc: 4b42 ldr r3, [pc, #264] @ (8005cd8 ) 8005bce: 681b ldr r3, [r3, #0] 8005bd0: 4a41 ldr r2, [pc, #260] @ (8005cd8 ) 8005bd2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8005bd6: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005bd8: f7fc fd42 bl 8002660 8005bdc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8005bde: e008 b.n 8005bf2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005be0: f7fc fd3e bl 8002660 8005be4: 4602 mov r2, r0 8005be6: 6a7b ldr r3, [r7, #36] @ 0x24 8005be8: 1ad3 subs r3, r2, r3 8005bea: 2b02 cmp r3, #2 8005bec: d901 bls.n 8005bf2 { return HAL_TIMEOUT; 8005bee: 2303 movs r3, #3 8005bf0: e10e b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8005bf2: 4b39 ldr r3, [pc, #228] @ (8005cd8 ) 8005bf4: 681b ldr r3, [r3, #0] 8005bf6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005bfa: 2b00 cmp r3, #0 8005bfc: d1f0 bne.n 8005be0 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8005bfe: 4b36 ldr r3, [pc, #216] @ (8005cd8 ) 8005c00: 6a9a ldr r2, [r3, #40] @ 0x28 8005c02: 4b37 ldr r3, [pc, #220] @ (8005ce0 ) 8005c04: 4013 ands r3, r2 8005c06: 687a ldr r2, [r7, #4] 8005c08: 6a91 ldr r1, [r2, #40] @ 0x28 8005c0a: 687a ldr r2, [r7, #4] 8005c0c: 6ad2 ldr r2, [r2, #44] @ 0x2c 8005c0e: 0112 lsls r2, r2, #4 8005c10: 430a orrs r2, r1 8005c12: 4931 ldr r1, [pc, #196] @ (8005cd8 ) 8005c14: 4313 orrs r3, r2 8005c16: 628b str r3, [r1, #40] @ 0x28 8005c18: 687b ldr r3, [r7, #4] 8005c1a: 6b1b ldr r3, [r3, #48] @ 0x30 8005c1c: 3b01 subs r3, #1 8005c1e: f3c3 0208 ubfx r2, r3, #0, #9 8005c22: 687b ldr r3, [r7, #4] 8005c24: 6b5b ldr r3, [r3, #52] @ 0x34 8005c26: 3b01 subs r3, #1 8005c28: 025b lsls r3, r3, #9 8005c2a: b29b uxth r3, r3 8005c2c: 431a orrs r2, r3 8005c2e: 687b ldr r3, [r7, #4] 8005c30: 6b9b ldr r3, [r3, #56] @ 0x38 8005c32: 3b01 subs r3, #1 8005c34: 041b lsls r3, r3, #16 8005c36: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 8005c3a: 431a orrs r2, r3 8005c3c: 687b ldr r3, [r7, #4] 8005c3e: 6bdb ldr r3, [r3, #60] @ 0x3c 8005c40: 3b01 subs r3, #1 8005c42: 061b lsls r3, r3, #24 8005c44: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 8005c48: 4923 ldr r1, [pc, #140] @ (8005cd8 ) 8005c4a: 4313 orrs r3, r2 8005c4c: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 8005c4e: 4b22 ldr r3, [pc, #136] @ (8005cd8 ) 8005c50: 6adb ldr r3, [r3, #44] @ 0x2c 8005c52: 4a21 ldr r2, [pc, #132] @ (8005cd8 ) 8005c54: f023 0301 bic.w r3, r3, #1 8005c58: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 8005c5a: 4b1f ldr r3, [pc, #124] @ (8005cd8 ) 8005c5c: 6b5a ldr r2, [r3, #52] @ 0x34 8005c5e: 4b21 ldr r3, [pc, #132] @ (8005ce4 ) 8005c60: 4013 ands r3, r2 8005c62: 687a ldr r2, [r7, #4] 8005c64: 6c92 ldr r2, [r2, #72] @ 0x48 8005c66: 00d2 lsls r2, r2, #3 8005c68: 491b ldr r1, [pc, #108] @ (8005cd8 ) 8005c6a: 4313 orrs r3, r2 8005c6c: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 8005c6e: 4b1a ldr r3, [pc, #104] @ (8005cd8 ) 8005c70: 6adb ldr r3, [r3, #44] @ 0x2c 8005c72: f023 020c bic.w r2, r3, #12 8005c76: 687b ldr r3, [r7, #4] 8005c78: 6c1b ldr r3, [r3, #64] @ 0x40 8005c7a: 4917 ldr r1, [pc, #92] @ (8005cd8 ) 8005c7c: 4313 orrs r3, r2 8005c7e: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 8005c80: 4b15 ldr r3, [pc, #84] @ (8005cd8 ) 8005c82: 6adb ldr r3, [r3, #44] @ 0x2c 8005c84: f023 0202 bic.w r2, r3, #2 8005c88: 687b ldr r3, [r7, #4] 8005c8a: 6c5b ldr r3, [r3, #68] @ 0x44 8005c8c: 4912 ldr r1, [pc, #72] @ (8005cd8 ) 8005c8e: 4313 orrs r3, r2 8005c90: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 8005c92: 4b11 ldr r3, [pc, #68] @ (8005cd8 ) 8005c94: 6adb ldr r3, [r3, #44] @ 0x2c 8005c96: 4a10 ldr r2, [pc, #64] @ (8005cd8 ) 8005c98: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8005c9c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8005c9e: 4b0e ldr r3, [pc, #56] @ (8005cd8 ) 8005ca0: 6adb ldr r3, [r3, #44] @ 0x2c 8005ca2: 4a0d ldr r2, [pc, #52] @ (8005cd8 ) 8005ca4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8005ca8: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 8005caa: 4b0b ldr r3, [pc, #44] @ (8005cd8 ) 8005cac: 6adb ldr r3, [r3, #44] @ 0x2c 8005cae: 4a0a ldr r2, [pc, #40] @ (8005cd8 ) 8005cb0: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8005cb4: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 8005cb6: 4b08 ldr r3, [pc, #32] @ (8005cd8 ) 8005cb8: 6adb ldr r3, [r3, #44] @ 0x2c 8005cba: 4a07 ldr r2, [pc, #28] @ (8005cd8 ) 8005cbc: f043 0301 orr.w r3, r3, #1 8005cc0: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8005cc2: 4b05 ldr r3, [pc, #20] @ (8005cd8 ) 8005cc4: 681b ldr r3, [r3, #0] 8005cc6: 4a04 ldr r2, [pc, #16] @ (8005cd8 ) 8005cc8: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8005ccc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005cce: f7fc fcc7 bl 8002660 8005cd2: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8005cd4: e011 b.n 8005cfa 8005cd6: bf00 nop 8005cd8: 58024400 .word 0x58024400 8005cdc: 58024800 .word 0x58024800 8005ce0: fffffc0c .word 0xfffffc0c 8005ce4: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005ce8: f7fc fcba bl 8002660 8005cec: 4602 mov r2, r0 8005cee: 6a7b ldr r3, [r7, #36] @ 0x24 8005cf0: 1ad3 subs r3, r2, r3 8005cf2: 2b02 cmp r3, #2 8005cf4: d901 bls.n 8005cfa { return HAL_TIMEOUT; 8005cf6: 2303 movs r3, #3 8005cf8: e08a b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8005cfa: 4b47 ldr r3, [pc, #284] @ (8005e18 ) 8005cfc: 681b ldr r3, [r3, #0] 8005cfe: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005d02: 2b00 cmp r3, #0 8005d04: d0f0 beq.n 8005ce8 8005d06: e082 b.n 8005e0e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8005d08: 4b43 ldr r3, [pc, #268] @ (8005e18 ) 8005d0a: 681b ldr r3, [r3, #0] 8005d0c: 4a42 ldr r2, [pc, #264] @ (8005e18 ) 8005d0e: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 8005d12: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005d14: f7fc fca4 bl 8002660 8005d18: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8005d1a: e008 b.n 8005d2e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8005d1c: f7fc fca0 bl 8002660 8005d20: 4602 mov r2, r0 8005d22: 6a7b ldr r3, [r7, #36] @ 0x24 8005d24: 1ad3 subs r3, r2, r3 8005d26: 2b02 cmp r3, #2 8005d28: d901 bls.n 8005d2e { return HAL_TIMEOUT; 8005d2a: 2303 movs r3, #3 8005d2c: e070 b.n 8005e10 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 8005d2e: 4b3a ldr r3, [pc, #232] @ (8005e18 ) 8005d30: 681b ldr r3, [r3, #0] 8005d32: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005d36: 2b00 cmp r3, #0 8005d38: d1f0 bne.n 8005d1c 8005d3a: e068 b.n 8005e0e } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 8005d3c: 4b36 ldr r3, [pc, #216] @ (8005e18 ) 8005d3e: 6a9b ldr r3, [r3, #40] @ 0x28 8005d40: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 8005d42: 4b35 ldr r3, [pc, #212] @ (8005e18 ) 8005d44: 6b1b ldr r3, [r3, #48] @ 0x30 8005d46: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005d48: 687b ldr r3, [r7, #4] 8005d4a: 6a5b ldr r3, [r3, #36] @ 0x24 8005d4c: 2b01 cmp r3, #1 8005d4e: d031 beq.n 8005db4 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005d50: 693b ldr r3, [r7, #16] 8005d52: f003 0203 and.w r2, r3, #3 8005d56: 687b ldr r3, [r7, #4] 8005d58: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8005d5a: 429a cmp r2, r3 8005d5c: d12a bne.n 8005db4 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8005d5e: 693b ldr r3, [r7, #16] 8005d60: 091b lsrs r3, r3, #4 8005d62: f003 023f and.w r2, r3, #63 @ 0x3f 8005d66: 687b ldr r3, [r7, #4] 8005d68: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8005d6a: 429a cmp r2, r3 8005d6c: d122 bne.n 8005db4 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 8005d6e: 68fb ldr r3, [r7, #12] 8005d70: f3c3 0208 ubfx r2, r3, #0, #9 8005d74: 687b ldr r3, [r7, #4] 8005d76: 6b1b ldr r3, [r3, #48] @ 0x30 8005d78: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 8005d7a: 429a cmp r2, r3 8005d7c: d11a bne.n 8005db4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 8005d7e: 68fb ldr r3, [r7, #12] 8005d80: 0a5b lsrs r3, r3, #9 8005d82: f003 027f and.w r2, r3, #127 @ 0x7f 8005d86: 687b ldr r3, [r7, #4] 8005d88: 6b5b ldr r3, [r3, #52] @ 0x34 8005d8a: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 8005d8c: 429a cmp r2, r3 8005d8e: d111 bne.n 8005db4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8005d90: 68fb ldr r3, [r7, #12] 8005d92: 0c1b lsrs r3, r3, #16 8005d94: f003 027f and.w r2, r3, #127 @ 0x7f 8005d98: 687b ldr r3, [r7, #4] 8005d9a: 6b9b ldr r3, [r3, #56] @ 0x38 8005d9c: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 8005d9e: 429a cmp r2, r3 8005da0: d108 bne.n 8005db4 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 8005da2: 68fb ldr r3, [r7, #12] 8005da4: 0e1b lsrs r3, r3, #24 8005da6: f003 027f and.w r2, r3, #127 @ 0x7f 8005daa: 687b ldr r3, [r7, #4] 8005dac: 6bdb ldr r3, [r3, #60] @ 0x3c 8005dae: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 8005db0: 429a cmp r2, r3 8005db2: d001 beq.n 8005db8 { return HAL_ERROR; 8005db4: 2301 movs r3, #1 8005db6: e02b b.n 8005e10 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 8005db8: 4b17 ldr r3, [pc, #92] @ (8005e18 ) 8005dba: 6b5b ldr r3, [r3, #52] @ 0x34 8005dbc: 08db lsrs r3, r3, #3 8005dbe: f3c3 030c ubfx r3, r3, #0, #13 8005dc2: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 8005dc4: 687b ldr r3, [r7, #4] 8005dc6: 6c9b ldr r3, [r3, #72] @ 0x48 8005dc8: 693a ldr r2, [r7, #16] 8005dca: 429a cmp r2, r3 8005dcc: d01f beq.n 8005e0e { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 8005dce: 4b12 ldr r3, [pc, #72] @ (8005e18 ) 8005dd0: 6adb ldr r3, [r3, #44] @ 0x2c 8005dd2: 4a11 ldr r2, [pc, #68] @ (8005e18 ) 8005dd4: f023 0301 bic.w r3, r3, #1 8005dd8: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005dda: f7fc fc41 bl 8002660 8005dde: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 8005de0: bf00 nop 8005de2: f7fc fc3d bl 8002660 8005de6: 4602 mov r2, r0 8005de8: 6a7b ldr r3, [r7, #36] @ 0x24 8005dea: 4293 cmp r3, r2 8005dec: d0f9 beq.n 8005de2 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 8005dee: 4b0a ldr r3, [pc, #40] @ (8005e18 ) 8005df0: 6b5a ldr r2, [r3, #52] @ 0x34 8005df2: 4b0a ldr r3, [pc, #40] @ (8005e1c ) 8005df4: 4013 ands r3, r2 8005df6: 687a ldr r2, [r7, #4] 8005df8: 6c92 ldr r2, [r2, #72] @ 0x48 8005dfa: 00d2 lsls r2, r2, #3 8005dfc: 4906 ldr r1, [pc, #24] @ (8005e18 ) 8005dfe: 4313 orrs r3, r2 8005e00: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 8005e02: 4b05 ldr r3, [pc, #20] @ (8005e18 ) 8005e04: 6adb ldr r3, [r3, #44] @ 0x2c 8005e06: 4a04 ldr r2, [pc, #16] @ (8005e18 ) 8005e08: f043 0301 orr.w r3, r3, #1 8005e0c: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 8005e0e: 2300 movs r3, #0 } 8005e10: 4618 mov r0, r3 8005e12: 3730 adds r7, #48 @ 0x30 8005e14: 46bd mov sp, r7 8005e16: bd80 pop {r7, pc} 8005e18: 58024400 .word 0x58024400 8005e1c: ffff0007 .word 0xffff0007 08005e20 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8005e20: b580 push {r7, lr} 8005e22: b086 sub sp, #24 8005e24: af00 add r7, sp, #0 8005e26: 6078 str r0, [r7, #4] 8005e28: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8005e2a: 687b ldr r3, [r7, #4] 8005e2c: 2b00 cmp r3, #0 8005e2e: d101 bne.n 8005e34 { return HAL_ERROR; 8005e30: 2301 movs r3, #1 8005e32: e19c b.n 800616e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8005e34: 4b8a ldr r3, [pc, #552] @ (8006060 ) 8005e36: 681b ldr r3, [r3, #0] 8005e38: f003 030f and.w r3, r3, #15 8005e3c: 683a ldr r2, [r7, #0] 8005e3e: 429a cmp r2, r3 8005e40: d910 bls.n 8005e64 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8005e42: 4b87 ldr r3, [pc, #540] @ (8006060 ) 8005e44: 681b ldr r3, [r3, #0] 8005e46: f023 020f bic.w r2, r3, #15 8005e4a: 4985 ldr r1, [pc, #532] @ (8006060 ) 8005e4c: 683b ldr r3, [r7, #0] 8005e4e: 4313 orrs r3, r2 8005e50: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8005e52: 4b83 ldr r3, [pc, #524] @ (8006060 ) 8005e54: 681b ldr r3, [r3, #0] 8005e56: f003 030f and.w r3, r3, #15 8005e5a: 683a ldr r2, [r7, #0] 8005e5c: 429a cmp r2, r3 8005e5e: d001 beq.n 8005e64 { return HAL_ERROR; 8005e60: 2301 movs r3, #1 8005e62: e184 b.n 800616e } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8005e64: 687b ldr r3, [r7, #4] 8005e66: 681b ldr r3, [r3, #0] 8005e68: f003 0304 and.w r3, r3, #4 8005e6c: 2b00 cmp r3, #0 8005e6e: d010 beq.n 8005e92 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8005e70: 687b ldr r3, [r7, #4] 8005e72: 691a ldr r2, [r3, #16] 8005e74: 4b7b ldr r3, [pc, #492] @ (8006064 ) 8005e76: 699b ldr r3, [r3, #24] 8005e78: f003 0370 and.w r3, r3, #112 @ 0x70 8005e7c: 429a cmp r2, r3 8005e7e: d908 bls.n 8005e92 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8005e80: 4b78 ldr r3, [pc, #480] @ (8006064 ) 8005e82: 699b ldr r3, [r3, #24] 8005e84: f023 0270 bic.w r2, r3, #112 @ 0x70 8005e88: 687b ldr r3, [r7, #4] 8005e8a: 691b ldr r3, [r3, #16] 8005e8c: 4975 ldr r1, [pc, #468] @ (8006064 ) 8005e8e: 4313 orrs r3, r2 8005e90: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8005e92: 687b ldr r3, [r7, #4] 8005e94: 681b ldr r3, [r3, #0] 8005e96: f003 0308 and.w r3, r3, #8 8005e9a: 2b00 cmp r3, #0 8005e9c: d010 beq.n 8005ec0 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 8005e9e: 687b ldr r3, [r7, #4] 8005ea0: 695a ldr r2, [r3, #20] 8005ea2: 4b70 ldr r3, [pc, #448] @ (8006064 ) 8005ea4: 69db ldr r3, [r3, #28] 8005ea6: f003 0370 and.w r3, r3, #112 @ 0x70 8005eaa: 429a cmp r2, r3 8005eac: d908 bls.n 8005ec0 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 8005eae: 4b6d ldr r3, [pc, #436] @ (8006064 ) 8005eb0: 69db ldr r3, [r3, #28] 8005eb2: f023 0270 bic.w r2, r3, #112 @ 0x70 8005eb6: 687b ldr r3, [r7, #4] 8005eb8: 695b ldr r3, [r3, #20] 8005eba: 496a ldr r1, [pc, #424] @ (8006064 ) 8005ebc: 4313 orrs r3, r2 8005ebe: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8005ec0: 687b ldr r3, [r7, #4] 8005ec2: 681b ldr r3, [r3, #0] 8005ec4: f003 0310 and.w r3, r3, #16 8005ec8: 2b00 cmp r3, #0 8005eca: d010 beq.n 8005eee { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 8005ecc: 687b ldr r3, [r7, #4] 8005ece: 699a ldr r2, [r3, #24] 8005ed0: 4b64 ldr r3, [pc, #400] @ (8006064 ) 8005ed2: 69db ldr r3, [r3, #28] 8005ed4: f403 63e0 and.w r3, r3, #1792 @ 0x700 8005ed8: 429a cmp r2, r3 8005eda: d908 bls.n 8005eee { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 8005edc: 4b61 ldr r3, [pc, #388] @ (8006064 ) 8005ede: 69db ldr r3, [r3, #28] 8005ee0: f423 62e0 bic.w r2, r3, #1792 @ 0x700 8005ee4: 687b ldr r3, [r7, #4] 8005ee6: 699b ldr r3, [r3, #24] 8005ee8: 495e ldr r1, [pc, #376] @ (8006064 ) 8005eea: 4313 orrs r3, r2 8005eec: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 8005eee: 687b ldr r3, [r7, #4] 8005ef0: 681b ldr r3, [r3, #0] 8005ef2: f003 0320 and.w r3, r3, #32 8005ef6: 2b00 cmp r3, #0 8005ef8: d010 beq.n 8005f1c { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 8005efa: 687b ldr r3, [r7, #4] 8005efc: 69da ldr r2, [r3, #28] 8005efe: 4b59 ldr r3, [pc, #356] @ (8006064 ) 8005f00: 6a1b ldr r3, [r3, #32] 8005f02: f003 0370 and.w r3, r3, #112 @ 0x70 8005f06: 429a cmp r2, r3 8005f08: d908 bls.n 8005f1c { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 8005f0a: 4b56 ldr r3, [pc, #344] @ (8006064 ) 8005f0c: 6a1b ldr r3, [r3, #32] 8005f0e: f023 0270 bic.w r2, r3, #112 @ 0x70 8005f12: 687b ldr r3, [r7, #4] 8005f14: 69db ldr r3, [r3, #28] 8005f16: 4953 ldr r1, [pc, #332] @ (8006064 ) 8005f18: 4313 orrs r3, r2 8005f1a: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8005f1c: 687b ldr r3, [r7, #4] 8005f1e: 681b ldr r3, [r3, #0] 8005f20: f003 0302 and.w r3, r3, #2 8005f24: 2b00 cmp r3, #0 8005f26: d010 beq.n 8005f4a { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 8005f28: 687b ldr r3, [r7, #4] 8005f2a: 68da ldr r2, [r3, #12] 8005f2c: 4b4d ldr r3, [pc, #308] @ (8006064 ) 8005f2e: 699b ldr r3, [r3, #24] 8005f30: f003 030f and.w r3, r3, #15 8005f34: 429a cmp r2, r3 8005f36: d908 bls.n 8005f4a { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8005f38: 4b4a ldr r3, [pc, #296] @ (8006064 ) 8005f3a: 699b ldr r3, [r3, #24] 8005f3c: f023 020f bic.w r2, r3, #15 8005f40: 687b ldr r3, [r7, #4] 8005f42: 68db ldr r3, [r3, #12] 8005f44: 4947 ldr r1, [pc, #284] @ (8006064 ) 8005f46: 4313 orrs r3, r2 8005f48: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8005f4a: 687b ldr r3, [r7, #4] 8005f4c: 681b ldr r3, [r3, #0] 8005f4e: f003 0301 and.w r3, r3, #1 8005f52: 2b00 cmp r3, #0 8005f54: d055 beq.n 8006002 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 8005f56: 4b43 ldr r3, [pc, #268] @ (8006064 ) 8005f58: 699b ldr r3, [r3, #24] 8005f5a: f423 6270 bic.w r2, r3, #3840 @ 0xf00 8005f5e: 687b ldr r3, [r7, #4] 8005f60: 689b ldr r3, [r3, #8] 8005f62: 4940 ldr r1, [pc, #256] @ (8006064 ) 8005f64: 4313 orrs r3, r2 8005f66: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8005f68: 687b ldr r3, [r7, #4] 8005f6a: 685b ldr r3, [r3, #4] 8005f6c: 2b02 cmp r3, #2 8005f6e: d107 bne.n 8005f80 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 8005f70: 4b3c ldr r3, [pc, #240] @ (8006064 ) 8005f72: 681b ldr r3, [r3, #0] 8005f74: f403 3300 and.w r3, r3, #131072 @ 0x20000 8005f78: 2b00 cmp r3, #0 8005f7a: d121 bne.n 8005fc0 { return HAL_ERROR; 8005f7c: 2301 movs r3, #1 8005f7e: e0f6 b.n 800616e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8005f80: 687b ldr r3, [r7, #4] 8005f82: 685b ldr r3, [r3, #4] 8005f84: 2b03 cmp r3, #3 8005f86: d107 bne.n 8005f98 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 8005f88: 4b36 ldr r3, [pc, #216] @ (8006064 ) 8005f8a: 681b ldr r3, [r3, #0] 8005f8c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8005f90: 2b00 cmp r3, #0 8005f92: d115 bne.n 8005fc0 { return HAL_ERROR; 8005f94: 2301 movs r3, #1 8005f96: e0ea b.n 800616e } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 8005f98: 687b ldr r3, [r7, #4] 8005f9a: 685b ldr r3, [r3, #4] 8005f9c: 2b01 cmp r3, #1 8005f9e: d107 bne.n 8005fb0 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 8005fa0: 4b30 ldr r3, [pc, #192] @ (8006064 ) 8005fa2: 681b ldr r3, [r3, #0] 8005fa4: f403 7380 and.w r3, r3, #256 @ 0x100 8005fa8: 2b00 cmp r3, #0 8005faa: d109 bne.n 8005fc0 { return HAL_ERROR; 8005fac: 2301 movs r3, #1 8005fae: e0de b.n 800616e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 8005fb0: 4b2c ldr r3, [pc, #176] @ (8006064 ) 8005fb2: 681b ldr r3, [r3, #0] 8005fb4: f003 0304 and.w r3, r3, #4 8005fb8: 2b00 cmp r3, #0 8005fba: d101 bne.n 8005fc0 { return HAL_ERROR; 8005fbc: 2301 movs r3, #1 8005fbe: e0d6 b.n 800616e } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8005fc0: 4b28 ldr r3, [pc, #160] @ (8006064 ) 8005fc2: 691b ldr r3, [r3, #16] 8005fc4: f023 0207 bic.w r2, r3, #7 8005fc8: 687b ldr r3, [r7, #4] 8005fca: 685b ldr r3, [r3, #4] 8005fcc: 4925 ldr r1, [pc, #148] @ (8006064 ) 8005fce: 4313 orrs r3, r2 8005fd0: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005fd2: f7fc fb45 bl 8002660 8005fd6: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8005fd8: e00a b.n 8005ff0 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8005fda: f7fc fb41 bl 8002660 8005fde: 4602 mov r2, r0 8005fe0: 697b ldr r3, [r7, #20] 8005fe2: 1ad3 subs r3, r2, r3 8005fe4: f241 3288 movw r2, #5000 @ 0x1388 8005fe8: 4293 cmp r3, r2 8005fea: d901 bls.n 8005ff0 { return HAL_TIMEOUT; 8005fec: 2303 movs r3, #3 8005fee: e0be b.n 800616e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8005ff0: 4b1c ldr r3, [pc, #112] @ (8006064 ) 8005ff2: 691b ldr r3, [r3, #16] 8005ff4: f003 0238 and.w r2, r3, #56 @ 0x38 8005ff8: 687b ldr r3, [r7, #4] 8005ffa: 685b ldr r3, [r3, #4] 8005ffc: 00db lsls r3, r3, #3 8005ffe: 429a cmp r2, r3 8006000: d1eb bne.n 8005fda } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8006002: 687b ldr r3, [r7, #4] 8006004: 681b ldr r3, [r3, #0] 8006006: f003 0302 and.w r3, r3, #2 800600a: 2b00 cmp r3, #0 800600c: d010 beq.n 8006030 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800600e: 687b ldr r3, [r7, #4] 8006010: 68da ldr r2, [r3, #12] 8006012: 4b14 ldr r3, [pc, #80] @ (8006064 ) 8006014: 699b ldr r3, [r3, #24] 8006016: f003 030f and.w r3, r3, #15 800601a: 429a cmp r2, r3 800601c: d208 bcs.n 8006030 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800601e: 4b11 ldr r3, [pc, #68] @ (8006064 ) 8006020: 699b ldr r3, [r3, #24] 8006022: f023 020f bic.w r2, r3, #15 8006026: 687b ldr r3, [r7, #4] 8006028: 68db ldr r3, [r3, #12] 800602a: 490e ldr r1, [pc, #56] @ (8006064 ) 800602c: 4313 orrs r3, r2 800602e: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8006030: 4b0b ldr r3, [pc, #44] @ (8006060 ) 8006032: 681b ldr r3, [r3, #0] 8006034: f003 030f and.w r3, r3, #15 8006038: 683a ldr r2, [r7, #0] 800603a: 429a cmp r2, r3 800603c: d214 bcs.n 8006068 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800603e: 4b08 ldr r3, [pc, #32] @ (8006060 ) 8006040: 681b ldr r3, [r3, #0] 8006042: f023 020f bic.w r2, r3, #15 8006046: 4906 ldr r1, [pc, #24] @ (8006060 ) 8006048: 683b ldr r3, [r7, #0] 800604a: 4313 orrs r3, r2 800604c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800604e: 4b04 ldr r3, [pc, #16] @ (8006060 ) 8006050: 681b ldr r3, [r3, #0] 8006052: f003 030f and.w r3, r3, #15 8006056: 683a ldr r2, [r7, #0] 8006058: 429a cmp r2, r3 800605a: d005 beq.n 8006068 { return HAL_ERROR; 800605c: 2301 movs r3, #1 800605e: e086 b.n 800616e 8006060: 52002000 .word 0x52002000 8006064: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 8006068: 687b ldr r3, [r7, #4] 800606a: 681b ldr r3, [r3, #0] 800606c: f003 0304 and.w r3, r3, #4 8006070: 2b00 cmp r3, #0 8006072: d010 beq.n 8006096 { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 8006074: 687b ldr r3, [r7, #4] 8006076: 691a ldr r2, [r3, #16] 8006078: 4b3f ldr r3, [pc, #252] @ (8006178 ) 800607a: 699b ldr r3, [r3, #24] 800607c: f003 0370 and.w r3, r3, #112 @ 0x70 8006080: 429a cmp r2, r3 8006082: d208 bcs.n 8006096 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 8006084: 4b3c ldr r3, [pc, #240] @ (8006178 ) 8006086: 699b ldr r3, [r3, #24] 8006088: f023 0270 bic.w r2, r3, #112 @ 0x70 800608c: 687b ldr r3, [r7, #4] 800608e: 691b ldr r3, [r3, #16] 8006090: 4939 ldr r1, [pc, #228] @ (8006178 ) 8006092: 4313 orrs r3, r2 8006094: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8006096: 687b ldr r3, [r7, #4] 8006098: 681b ldr r3, [r3, #0] 800609a: f003 0308 and.w r3, r3, #8 800609e: 2b00 cmp r3, #0 80060a0: d010 beq.n 80060c4 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 80060a2: 687b ldr r3, [r7, #4] 80060a4: 695a ldr r2, [r3, #20] 80060a6: 4b34 ldr r3, [pc, #208] @ (8006178 ) 80060a8: 69db ldr r3, [r3, #28] 80060aa: f003 0370 and.w r3, r3, #112 @ 0x70 80060ae: 429a cmp r2, r3 80060b0: d208 bcs.n 80060c4 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 80060b2: 4b31 ldr r3, [pc, #196] @ (8006178 ) 80060b4: 69db ldr r3, [r3, #28] 80060b6: f023 0270 bic.w r2, r3, #112 @ 0x70 80060ba: 687b ldr r3, [r7, #4] 80060bc: 695b ldr r3, [r3, #20] 80060be: 492e ldr r1, [pc, #184] @ (8006178 ) 80060c0: 4313 orrs r3, r2 80060c2: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 80060c4: 687b ldr r3, [r7, #4] 80060c6: 681b ldr r3, [r3, #0] 80060c8: f003 0310 and.w r3, r3, #16 80060cc: 2b00 cmp r3, #0 80060ce: d010 beq.n 80060f2 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 80060d0: 687b ldr r3, [r7, #4] 80060d2: 699a ldr r2, [r3, #24] 80060d4: 4b28 ldr r3, [pc, #160] @ (8006178 ) 80060d6: 69db ldr r3, [r3, #28] 80060d8: f403 63e0 and.w r3, r3, #1792 @ 0x700 80060dc: 429a cmp r2, r3 80060de: d208 bcs.n 80060f2 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 80060e0: 4b25 ldr r3, [pc, #148] @ (8006178 ) 80060e2: 69db ldr r3, [r3, #28] 80060e4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 80060e8: 687b ldr r3, [r7, #4] 80060ea: 699b ldr r3, [r3, #24] 80060ec: 4922 ldr r1, [pc, #136] @ (8006178 ) 80060ee: 4313 orrs r3, r2 80060f0: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 80060f2: 687b ldr r3, [r7, #4] 80060f4: 681b ldr r3, [r3, #0] 80060f6: f003 0320 and.w r3, r3, #32 80060fa: 2b00 cmp r3, #0 80060fc: d010 beq.n 8006120 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 80060fe: 687b ldr r3, [r7, #4] 8006100: 69da ldr r2, [r3, #28] 8006102: 4b1d ldr r3, [pc, #116] @ (8006178 ) 8006104: 6a1b ldr r3, [r3, #32] 8006106: f003 0370 and.w r3, r3, #112 @ 0x70 800610a: 429a cmp r2, r3 800610c: d208 bcs.n 8006120 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800610e: 4b1a ldr r3, [pc, #104] @ (8006178 ) 8006110: 6a1b ldr r3, [r3, #32] 8006112: f023 0270 bic.w r2, r3, #112 @ 0x70 8006116: 687b ldr r3, [r7, #4] 8006118: 69db ldr r3, [r3, #28] 800611a: 4917 ldr r1, [pc, #92] @ (8006178 ) 800611c: 4313 orrs r3, r2 800611e: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8006120: f000 f834 bl 800618c 8006124: 4602 mov r2, r0 8006126: 4b14 ldr r3, [pc, #80] @ (8006178 ) 8006128: 699b ldr r3, [r3, #24] 800612a: 0a1b lsrs r3, r3, #8 800612c: f003 030f and.w r3, r3, #15 8006130: 4912 ldr r1, [pc, #72] @ (800617c ) 8006132: 5ccb ldrb r3, [r1, r3] 8006134: f003 031f and.w r3, r3, #31 8006138: fa22 f303 lsr.w r3, r2, r3 800613c: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800613e: 4b0e ldr r3, [pc, #56] @ (8006178 ) 8006140: 699b ldr r3, [r3, #24] 8006142: f003 030f and.w r3, r3, #15 8006146: 4a0d ldr r2, [pc, #52] @ (800617c ) 8006148: 5cd3 ldrb r3, [r2, r3] 800614a: f003 031f and.w r3, r3, #31 800614e: 693a ldr r2, [r7, #16] 8006150: fa22 f303 lsr.w r3, r2, r3 8006154: 4a0a ldr r2, [pc, #40] @ (8006180 ) 8006156: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8006158: 4a0a ldr r2, [pc, #40] @ (8006184 ) 800615a: 693b ldr r3, [r7, #16] 800615c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800615e: 4b0a ldr r3, [pc, #40] @ (8006188 ) 8006160: 681b ldr r3, [r3, #0] 8006162: 4618 mov r0, r3 8006164: f7fb fb18 bl 8001798 8006168: 4603 mov r3, r0 800616a: 73fb strb r3, [r7, #15] return halstatus; 800616c: 7bfb ldrb r3, [r7, #15] } 800616e: 4618 mov r0, r3 8006170: 3718 adds r7, #24 8006172: 46bd mov sp, r7 8006174: bd80 pop {r7, pc} 8006176: bf00 nop 8006178: 58024400 .word 0x58024400 800617c: 080100b0 .word 0x080100b0 8006180: 24000004 .word 0x24000004 8006184: 24000000 .word 0x24000000 8006188: 24000008 .word 0x24000008 0800618c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800618c: b480 push {r7} 800618e: b089 sub sp, #36 @ 0x24 8006190: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8006192: 4bb3 ldr r3, [pc, #716] @ (8006460 ) 8006194: 691b ldr r3, [r3, #16] 8006196: f003 0338 and.w r3, r3, #56 @ 0x38 800619a: 2b18 cmp r3, #24 800619c: f200 8155 bhi.w 800644a 80061a0: a201 add r2, pc, #4 @ (adr r2, 80061a8 ) 80061a2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80061a6: bf00 nop 80061a8: 0800620d .word 0x0800620d 80061ac: 0800644b .word 0x0800644b 80061b0: 0800644b .word 0x0800644b 80061b4: 0800644b .word 0x0800644b 80061b8: 0800644b .word 0x0800644b 80061bc: 0800644b .word 0x0800644b 80061c0: 0800644b .word 0x0800644b 80061c4: 0800644b .word 0x0800644b 80061c8: 08006233 .word 0x08006233 80061cc: 0800644b .word 0x0800644b 80061d0: 0800644b .word 0x0800644b 80061d4: 0800644b .word 0x0800644b 80061d8: 0800644b .word 0x0800644b 80061dc: 0800644b .word 0x0800644b 80061e0: 0800644b .word 0x0800644b 80061e4: 0800644b .word 0x0800644b 80061e8: 08006239 .word 0x08006239 80061ec: 0800644b .word 0x0800644b 80061f0: 0800644b .word 0x0800644b 80061f4: 0800644b .word 0x0800644b 80061f8: 0800644b .word 0x0800644b 80061fc: 0800644b .word 0x0800644b 8006200: 0800644b .word 0x0800644b 8006204: 0800644b .word 0x0800644b 8006208: 0800623f .word 0x0800623f { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800620c: 4b94 ldr r3, [pc, #592] @ (8006460 ) 800620e: 681b ldr r3, [r3, #0] 8006210: f003 0320 and.w r3, r3, #32 8006214: 2b00 cmp r3, #0 8006216: d009 beq.n 800622c { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8006218: 4b91 ldr r3, [pc, #580] @ (8006460 ) 800621a: 681b ldr r3, [r3, #0] 800621c: 08db lsrs r3, r3, #3 800621e: f003 0303 and.w r3, r3, #3 8006222: 4a90 ldr r2, [pc, #576] @ (8006464 ) 8006224: fa22 f303 lsr.w r3, r2, r3 8006228: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800622a: e111 b.n 8006450 sysclockfreq = (uint32_t) HSI_VALUE; 800622c: 4b8d ldr r3, [pc, #564] @ (8006464 ) 800622e: 61bb str r3, [r7, #24] break; 8006230: e10e b.n 8006450 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 8006232: 4b8d ldr r3, [pc, #564] @ (8006468 ) 8006234: 61bb str r3, [r7, #24] break; 8006236: e10b b.n 8006450 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8006238: 4b8c ldr r3, [pc, #560] @ (800646c ) 800623a: 61bb str r3, [r7, #24] break; 800623c: e108 b.n 8006450 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800623e: 4b88 ldr r3, [pc, #544] @ (8006460 ) 8006240: 6a9b ldr r3, [r3, #40] @ 0x28 8006242: f003 0303 and.w r3, r3, #3 8006246: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 8006248: 4b85 ldr r3, [pc, #532] @ (8006460 ) 800624a: 6a9b ldr r3, [r3, #40] @ 0x28 800624c: 091b lsrs r3, r3, #4 800624e: f003 033f and.w r3, r3, #63 @ 0x3f 8006252: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 8006254: 4b82 ldr r3, [pc, #520] @ (8006460 ) 8006256: 6adb ldr r3, [r3, #44] @ 0x2c 8006258: f003 0301 and.w r3, r3, #1 800625c: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800625e: 4b80 ldr r3, [pc, #512] @ (8006460 ) 8006260: 6b5b ldr r3, [r3, #52] @ 0x34 8006262: 08db lsrs r3, r3, #3 8006264: f3c3 030c ubfx r3, r3, #0, #13 8006268: 68fa ldr r2, [r7, #12] 800626a: fb02 f303 mul.w r3, r2, r3 800626e: ee07 3a90 vmov s15, r3 8006272: eef8 7a67 vcvt.f32.u32 s15, s15 8006276: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800627a: 693b ldr r3, [r7, #16] 800627c: 2b00 cmp r3, #0 800627e: f000 80e1 beq.w 8006444 8006282: 697b ldr r3, [r7, #20] 8006284: 2b02 cmp r3, #2 8006286: f000 8083 beq.w 8006390 800628a: 697b ldr r3, [r7, #20] 800628c: 2b02 cmp r3, #2 800628e: f200 80a1 bhi.w 80063d4 8006292: 697b ldr r3, [r7, #20] 8006294: 2b00 cmp r3, #0 8006296: d003 beq.n 80062a0 8006298: 697b ldr r3, [r7, #20] 800629a: 2b01 cmp r3, #1 800629c: d056 beq.n 800634c 800629e: e099 b.n 80063d4 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80062a0: 4b6f ldr r3, [pc, #444] @ (8006460 ) 80062a2: 681b ldr r3, [r3, #0] 80062a4: f003 0320 and.w r3, r3, #32 80062a8: 2b00 cmp r3, #0 80062aa: d02d beq.n 8006308 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 80062ac: 4b6c ldr r3, [pc, #432] @ (8006460 ) 80062ae: 681b ldr r3, [r3, #0] 80062b0: 08db lsrs r3, r3, #3 80062b2: f003 0303 and.w r3, r3, #3 80062b6: 4a6b ldr r2, [pc, #428] @ (8006464 ) 80062b8: fa22 f303 lsr.w r3, r2, r3 80062bc: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80062be: 687b ldr r3, [r7, #4] 80062c0: ee07 3a90 vmov s15, r3 80062c4: eef8 6a67 vcvt.f32.u32 s13, s15 80062c8: 693b ldr r3, [r7, #16] 80062ca: ee07 3a90 vmov s15, r3 80062ce: eef8 7a67 vcvt.f32.u32 s15, s15 80062d2: ee86 7aa7 vdiv.f32 s14, s13, s15 80062d6: 4b62 ldr r3, [pc, #392] @ (8006460 ) 80062d8: 6b1b ldr r3, [r3, #48] @ 0x30 80062da: f3c3 0308 ubfx r3, r3, #0, #9 80062de: ee07 3a90 vmov s15, r3 80062e2: eef8 6a67 vcvt.f32.u32 s13, s15 80062e6: ed97 6a02 vldr s12, [r7, #8] 80062ea: eddf 5a61 vldr s11, [pc, #388] @ 8006470 80062ee: eec6 7a25 vdiv.f32 s15, s12, s11 80062f2: ee76 7aa7 vadd.f32 s15, s13, s15 80062f6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80062fa: ee77 7aa6 vadd.f32 s15, s15, s13 80062fe: ee67 7a27 vmul.f32 s15, s14, s15 8006302: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 8006306: e087 b.n 8006418 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8006308: 693b ldr r3, [r7, #16] 800630a: ee07 3a90 vmov s15, r3 800630e: eef8 7a67 vcvt.f32.u32 s15, s15 8006312: eddf 6a58 vldr s13, [pc, #352] @ 8006474 8006316: ee86 7aa7 vdiv.f32 s14, s13, s15 800631a: 4b51 ldr r3, [pc, #324] @ (8006460 ) 800631c: 6b1b ldr r3, [r3, #48] @ 0x30 800631e: f3c3 0308 ubfx r3, r3, #0, #9 8006322: ee07 3a90 vmov s15, r3 8006326: eef8 6a67 vcvt.f32.u32 s13, s15 800632a: ed97 6a02 vldr s12, [r7, #8] 800632e: eddf 5a50 vldr s11, [pc, #320] @ 8006470 8006332: eec6 7a25 vdiv.f32 s15, s12, s11 8006336: ee76 7aa7 vadd.f32 s15, s13, s15 800633a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800633e: ee77 7aa6 vadd.f32 s15, s15, s13 8006342: ee67 7a27 vmul.f32 s15, s14, s15 8006346: edc7 7a07 vstr s15, [r7, #28] break; 800634a: e065 b.n 8006418 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800634c: 693b ldr r3, [r7, #16] 800634e: ee07 3a90 vmov s15, r3 8006352: eef8 7a67 vcvt.f32.u32 s15, s15 8006356: eddf 6a48 vldr s13, [pc, #288] @ 8006478 800635a: ee86 7aa7 vdiv.f32 s14, s13, s15 800635e: 4b40 ldr r3, [pc, #256] @ (8006460 ) 8006360: 6b1b ldr r3, [r3, #48] @ 0x30 8006362: f3c3 0308 ubfx r3, r3, #0, #9 8006366: ee07 3a90 vmov s15, r3 800636a: eef8 6a67 vcvt.f32.u32 s13, s15 800636e: ed97 6a02 vldr s12, [r7, #8] 8006372: eddf 5a3f vldr s11, [pc, #252] @ 8006470 8006376: eec6 7a25 vdiv.f32 s15, s12, s11 800637a: ee76 7aa7 vadd.f32 s15, s13, s15 800637e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8006382: ee77 7aa6 vadd.f32 s15, s15, s13 8006386: ee67 7a27 vmul.f32 s15, s14, s15 800638a: edc7 7a07 vstr s15, [r7, #28] break; 800638e: e043 b.n 8006418 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 8006390: 693b ldr r3, [r7, #16] 8006392: ee07 3a90 vmov s15, r3 8006396: eef8 7a67 vcvt.f32.u32 s15, s15 800639a: eddf 6a38 vldr s13, [pc, #224] @ 800647c 800639e: ee86 7aa7 vdiv.f32 s14, s13, s15 80063a2: 4b2f ldr r3, [pc, #188] @ (8006460 ) 80063a4: 6b1b ldr r3, [r3, #48] @ 0x30 80063a6: f3c3 0308 ubfx r3, r3, #0, #9 80063aa: ee07 3a90 vmov s15, r3 80063ae: eef8 6a67 vcvt.f32.u32 s13, s15 80063b2: ed97 6a02 vldr s12, [r7, #8] 80063b6: eddf 5a2e vldr s11, [pc, #184] @ 8006470 80063ba: eec6 7a25 vdiv.f32 s15, s12, s11 80063be: ee76 7aa7 vadd.f32 s15, s13, s15 80063c2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 80063c6: ee77 7aa6 vadd.f32 s15, s15, s13 80063ca: ee67 7a27 vmul.f32 s15, s14, s15 80063ce: edc7 7a07 vstr s15, [r7, #28] break; 80063d2: e021 b.n 8006418 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 80063d4: 693b ldr r3, [r7, #16] 80063d6: ee07 3a90 vmov s15, r3 80063da: eef8 7a67 vcvt.f32.u32 s15, s15 80063de: eddf 6a26 vldr s13, [pc, #152] @ 8006478 80063e2: ee86 7aa7 vdiv.f32 s14, s13, s15 80063e6: 4b1e ldr r3, [pc, #120] @ (8006460 ) 80063e8: 6b1b ldr r3, [r3, #48] @ 0x30 80063ea: f3c3 0308 ubfx r3, r3, #0, #9 80063ee: ee07 3a90 vmov s15, r3 80063f2: eef8 6a67 vcvt.f32.u32 s13, s15 80063f6: ed97 6a02 vldr s12, [r7, #8] 80063fa: eddf 5a1d vldr s11, [pc, #116] @ 8006470 80063fe: eec6 7a25 vdiv.f32 s15, s12, s11 8006402: ee76 7aa7 vadd.f32 s15, s13, s15 8006406: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800640a: ee77 7aa6 vadd.f32 s15, s15, s13 800640e: ee67 7a27 vmul.f32 s15, s14, s15 8006412: edc7 7a07 vstr s15, [r7, #28] break; 8006416: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 8006418: 4b11 ldr r3, [pc, #68] @ (8006460 ) 800641a: 6b1b ldr r3, [r3, #48] @ 0x30 800641c: 0a5b lsrs r3, r3, #9 800641e: f003 037f and.w r3, r3, #127 @ 0x7f 8006422: 3301 adds r3, #1 8006424: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 8006426: 683b ldr r3, [r7, #0] 8006428: ee07 3a90 vmov s15, r3 800642c: eeb8 7a67 vcvt.f32.u32 s14, s15 8006430: edd7 6a07 vldr s13, [r7, #28] 8006434: eec6 7a87 vdiv.f32 s15, s13, s14 8006438: eefc 7ae7 vcvt.u32.f32 s15, s15 800643c: ee17 3a90 vmov r3, s15 8006440: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 8006442: e005 b.n 8006450 sysclockfreq = 0U; 8006444: 2300 movs r3, #0 8006446: 61bb str r3, [r7, #24] break; 8006448: e002 b.n 8006450 default: sysclockfreq = CSI_VALUE; 800644a: 4b07 ldr r3, [pc, #28] @ (8006468 ) 800644c: 61bb str r3, [r7, #24] break; 800644e: bf00 nop } return sysclockfreq; 8006450: 69bb ldr r3, [r7, #24] } 8006452: 4618 mov r0, r3 8006454: 3724 adds r7, #36 @ 0x24 8006456: 46bd mov sp, r7 8006458: f85d 7b04 ldr.w r7, [sp], #4 800645c: 4770 bx lr 800645e: bf00 nop 8006460: 58024400 .word 0x58024400 8006464: 03d09000 .word 0x03d09000 8006468: 003d0900 .word 0x003d0900 800646c: 017d7840 .word 0x017d7840 8006470: 46000000 .word 0x46000000 8006474: 4c742400 .word 0x4c742400 8006478: 4a742400 .word 0x4a742400 800647c: 4bbebc20 .word 0x4bbebc20 08006480 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8006480: b580 push {r7, lr} 8006482: b082 sub sp, #8 8006484: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 8006486: f7ff fe81 bl 800618c 800648a: 4602 mov r2, r0 800648c: 4b10 ldr r3, [pc, #64] @ (80064d0 ) 800648e: 699b ldr r3, [r3, #24] 8006490: 0a1b lsrs r3, r3, #8 8006492: f003 030f and.w r3, r3, #15 8006496: 490f ldr r1, [pc, #60] @ (80064d4 ) 8006498: 5ccb ldrb r3, [r1, r3] 800649a: f003 031f and.w r3, r3, #31 800649e: fa22 f303 lsr.w r3, r2, r3 80064a2: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 80064a4: 4b0a ldr r3, [pc, #40] @ (80064d0 ) 80064a6: 699b ldr r3, [r3, #24] 80064a8: f003 030f and.w r3, r3, #15 80064ac: 4a09 ldr r2, [pc, #36] @ (80064d4 ) 80064ae: 5cd3 ldrb r3, [r2, r3] 80064b0: f003 031f and.w r3, r3, #31 80064b4: 687a ldr r2, [r7, #4] 80064b6: fa22 f303 lsr.w r3, r2, r3 80064ba: 4a07 ldr r2, [pc, #28] @ (80064d8 ) 80064bc: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 80064be: 4a07 ldr r2, [pc, #28] @ (80064dc ) 80064c0: 687b ldr r3, [r7, #4] 80064c2: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 80064c4: 4b04 ldr r3, [pc, #16] @ (80064d8 ) 80064c6: 681b ldr r3, [r3, #0] } 80064c8: 4618 mov r0, r3 80064ca: 3708 adds r7, #8 80064cc: 46bd mov sp, r7 80064ce: bd80 pop {r7, pc} 80064d0: 58024400 .word 0x58024400 80064d4: 080100b0 .word 0x080100b0 80064d8: 24000004 .word 0x24000004 80064dc: 24000000 .word 0x24000000 080064e0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 80064e0: b580 push {r7, lr} 80064e2: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 80064e4: f7ff ffcc bl 8006480 80064e8: 4602 mov r2, r0 80064ea: 4b06 ldr r3, [pc, #24] @ (8006504 ) 80064ec: 69db ldr r3, [r3, #28] 80064ee: 091b lsrs r3, r3, #4 80064f0: f003 0307 and.w r3, r3, #7 80064f4: 4904 ldr r1, [pc, #16] @ (8006508 ) 80064f6: 5ccb ldrb r3, [r1, r3] 80064f8: f003 031f and.w r3, r3, #31 80064fc: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 8006500: 4618 mov r0, r3 8006502: bd80 pop {r7, pc} 8006504: 58024400 .word 0x58024400 8006508: 080100b0 .word 0x080100b0 0800650c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800650c: b580 push {r7, lr} 800650e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 8006510: f7ff ffb6 bl 8006480 8006514: 4602 mov r2, r0 8006516: 4b06 ldr r3, [pc, #24] @ (8006530 ) 8006518: 69db ldr r3, [r3, #28] 800651a: 0a1b lsrs r3, r3, #8 800651c: f003 0307 and.w r3, r3, #7 8006520: 4904 ldr r1, [pc, #16] @ (8006534 ) 8006522: 5ccb ldrb r3, [r1, r3] 8006524: f003 031f and.w r3, r3, #31 8006528: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800652c: 4618 mov r0, r3 800652e: bd80 pop {r7, pc} 8006530: 58024400 .word 0x58024400 8006534: 080100b0 .word 0x080100b0 08006538 : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8006538: b480 push {r7} 800653a: b083 sub sp, #12 800653c: af00 add r7, sp, #0 800653e: 6078 str r0, [r7, #4] 8006540: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 8006542: 687b ldr r3, [r7, #4] 8006544: 223f movs r2, #63 @ 0x3f 8006546: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8006548: 4b1a ldr r3, [pc, #104] @ (80065b4 ) 800654a: 691b ldr r3, [r3, #16] 800654c: f003 0207 and.w r2, r3, #7 8006550: 687b ldr r3, [r7, #4] 8006552: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 8006554: 4b17 ldr r3, [pc, #92] @ (80065b4 ) 8006556: 699b ldr r3, [r3, #24] 8006558: f403 6270 and.w r2, r3, #3840 @ 0xf00 800655c: 687b ldr r3, [r7, #4] 800655e: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 8006560: 4b14 ldr r3, [pc, #80] @ (80065b4 ) 8006562: 699b ldr r3, [r3, #24] 8006564: f003 020f and.w r2, r3, #15 8006568: 687b ldr r3, [r7, #4] 800656a: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800656c: 4b11 ldr r3, [pc, #68] @ (80065b4 ) 800656e: 699b ldr r3, [r3, #24] 8006570: f003 0270 and.w r2, r3, #112 @ 0x70 8006574: 687b ldr r3, [r7, #4] 8006576: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 8006578: 4b0e ldr r3, [pc, #56] @ (80065b4 ) 800657a: 69db ldr r3, [r3, #28] 800657c: f003 0270 and.w r2, r3, #112 @ 0x70 8006580: 687b ldr r3, [r7, #4] 8006582: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 8006584: 4b0b ldr r3, [pc, #44] @ (80065b4 ) 8006586: 69db ldr r3, [r3, #28] 8006588: f403 62e0 and.w r2, r3, #1792 @ 0x700 800658c: 687b ldr r3, [r7, #4] 800658e: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 8006590: 4b08 ldr r3, [pc, #32] @ (80065b4 ) 8006592: 6a1b ldr r3, [r3, #32] 8006594: f003 0270 and.w r2, r3, #112 @ 0x70 8006598: 687b ldr r3, [r7, #4] 800659a: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800659c: 4b06 ldr r3, [pc, #24] @ (80065b8 ) 800659e: 681b ldr r3, [r3, #0] 80065a0: f003 020f and.w r2, r3, #15 80065a4: 683b ldr r3, [r7, #0] 80065a6: 601a str r2, [r3, #0] } 80065a8: bf00 nop 80065aa: 370c adds r7, #12 80065ac: 46bd mov sp, r7 80065ae: f85d 7b04 ldr.w r7, [sp], #4 80065b2: 4770 bx lr 80065b4: 58024400 .word 0x58024400 80065b8: 52002000 .word 0x52002000 080065bc : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 80065bc: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 80065c0: b0c8 sub sp, #288 @ 0x120 80065c2: af00 add r7, sp, #0 80065c4: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 80065c8: 2300 movs r3, #0 80065ca: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 80065ce: 2300 movs r3, #0 80065d0: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 80065d4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80065d8: e9d3 2300 ldrd r2, r3, [r3] 80065dc: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 80065e0: 2500 movs r5, #0 80065e2: ea54 0305 orrs.w r3, r4, r5 80065e6: d049 beq.n 800667c { switch (PeriphClkInit->SpdifrxClockSelection) 80065e8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80065ec: 6e9b ldr r3, [r3, #104] @ 0x68 80065ee: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 80065f2: d02f beq.n 8006654 80065f4: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 80065f8: d828 bhi.n 800664c 80065fa: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80065fe: d01a beq.n 8006636 8006600: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006604: d822 bhi.n 800664c 8006606: 2b00 cmp r3, #0 8006608: d003 beq.n 8006612 800660a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800660e: d007 beq.n 8006620 8006610: e01c b.n 800664c { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006612: 4bb8 ldr r3, [pc, #736] @ (80068f4 ) 8006614: 6adb ldr r3, [r3, #44] @ 0x2c 8006616: 4ab7 ldr r2, [pc, #732] @ (80068f4 ) 8006618: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800661c: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800661e: e01a b.n 8006656 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8006620: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006624: 3308 adds r3, #8 8006626: 2102 movs r1, #2 8006628: 4618 mov r0, r3 800662a: f001 fc73 bl 8007f14 800662e: 4603 mov r3, r0 8006630: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 8006634: e00f b.n 8006656 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8006636: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800663a: 3328 adds r3, #40 @ 0x28 800663c: 2102 movs r1, #2 800663e: 4618 mov r0, r3 8006640: f001 fd1a bl 8008078 8006644: 4603 mov r3, r0 8006646: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800664a: e004 b.n 8006656 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800664c: 2301 movs r3, #1 800664e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006652: e000 b.n 8006656 break; 8006654: bf00 nop } if (ret == HAL_OK) 8006656: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800665a: 2b00 cmp r3, #0 800665c: d10a bne.n 8006674 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800665e: 4ba5 ldr r3, [pc, #660] @ (80068f4 ) 8006660: 6d1b ldr r3, [r3, #80] @ 0x50 8006662: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 8006666: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800666a: 6e9b ldr r3, [r3, #104] @ 0x68 800666c: 4aa1 ldr r2, [pc, #644] @ (80068f4 ) 800666e: 430b orrs r3, r1 8006670: 6513 str r3, [r2, #80] @ 0x50 8006672: e003 b.n 800667c } else { /* set overall return value */ status = ret; 8006674: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006678: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800667c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006680: e9d3 2300 ldrd r2, r3, [r3] 8006684: f402 7880 and.w r8, r2, #256 @ 0x100 8006688: f04f 0900 mov.w r9, #0 800668c: ea58 0309 orrs.w r3, r8, r9 8006690: d047 beq.n 8006722 { switch (PeriphClkInit->Sai1ClockSelection) 8006692: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006696: 6d9b ldr r3, [r3, #88] @ 0x58 8006698: 2b04 cmp r3, #4 800669a: d82a bhi.n 80066f2 800669c: a201 add r2, pc, #4 @ (adr r2, 80066a4 ) 800669e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80066a2: bf00 nop 80066a4: 080066b9 .word 0x080066b9 80066a8: 080066c7 .word 0x080066c7 80066ac: 080066dd .word 0x080066dd 80066b0: 080066fb .word 0x080066fb 80066b4: 080066fb .word 0x080066fb { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80066b8: 4b8e ldr r3, [pc, #568] @ (80068f4 ) 80066ba: 6adb ldr r3, [r3, #44] @ 0x2c 80066bc: 4a8d ldr r2, [pc, #564] @ (80068f4 ) 80066be: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80066c2: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 80066c4: e01a b.n 80066fc case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80066c6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80066ca: 3308 adds r3, #8 80066cc: 2100 movs r1, #0 80066ce: 4618 mov r0, r3 80066d0: f001 fc20 bl 8007f14 80066d4: 4603 mov r3, r0 80066d6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 80066da: e00f b.n 80066fc case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 80066dc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80066e0: 3328 adds r3, #40 @ 0x28 80066e2: 2100 movs r1, #0 80066e4: 4618 mov r0, r3 80066e6: f001 fcc7 bl 8008078 80066ea: 4603 mov r3, r0 80066ec: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 80066f0: e004 b.n 80066fc /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80066f2: 2301 movs r3, #1 80066f4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 80066f8: e000 b.n 80066fc break; 80066fa: bf00 nop } if (ret == HAL_OK) 80066fc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006700: 2b00 cmp r3, #0 8006702: d10a bne.n 800671a { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 8006704: 4b7b ldr r3, [pc, #492] @ (80068f4 ) 8006706: 6d1b ldr r3, [r3, #80] @ 0x50 8006708: f023 0107 bic.w r1, r3, #7 800670c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006710: 6d9b ldr r3, [r3, #88] @ 0x58 8006712: 4a78 ldr r2, [pc, #480] @ (80068f4 ) 8006714: 430b orrs r3, r1 8006716: 6513 str r3, [r2, #80] @ 0x50 8006718: e003 b.n 8006722 } else { /* set overall return value */ status = ret; 800671a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800671e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 8006722: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006726: e9d3 2300 ldrd r2, r3, [r3] 800672a: f402 7a00 and.w sl, r2, #512 @ 0x200 800672e: f04f 0b00 mov.w fp, #0 8006732: ea5a 030b orrs.w r3, sl, fp 8006736: d04c beq.n 80067d2 { switch (PeriphClkInit->Sai23ClockSelection) 8006738: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800673c: 6ddb ldr r3, [r3, #92] @ 0x5c 800673e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006742: d030 beq.n 80067a6 8006744: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006748: d829 bhi.n 800679e 800674a: 2bc0 cmp r3, #192 @ 0xc0 800674c: d02d beq.n 80067aa 800674e: 2bc0 cmp r3, #192 @ 0xc0 8006750: d825 bhi.n 800679e 8006752: 2b80 cmp r3, #128 @ 0x80 8006754: d018 beq.n 8006788 8006756: 2b80 cmp r3, #128 @ 0x80 8006758: d821 bhi.n 800679e 800675a: 2b00 cmp r3, #0 800675c: d002 beq.n 8006764 800675e: 2b40 cmp r3, #64 @ 0x40 8006760: d007 beq.n 8006772 8006762: e01c b.n 800679e { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006764: 4b63 ldr r3, [pc, #396] @ (80068f4 ) 8006766: 6adb ldr r3, [r3, #44] @ 0x2c 8006768: 4a62 ldr r2, [pc, #392] @ (80068f4 ) 800676a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800676e: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 8006770: e01c b.n 80067ac case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006772: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006776: 3308 adds r3, #8 8006778: 2100 movs r1, #0 800677a: 4618 mov r0, r3 800677c: f001 fbca bl 8007f14 8006780: 4603 mov r3, r0 8006782: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 8006786: e011 b.n 80067ac case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 8006788: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800678c: 3328 adds r3, #40 @ 0x28 800678e: 2100 movs r1, #0 8006790: 4618 mov r0, r3 8006792: f001 fc71 bl 8008078 8006796: 4603 mov r3, r0 8006798: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800679c: e006 b.n 80067ac /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800679e: 2301 movs r3, #1 80067a0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 80067a4: e002 b.n 80067ac break; 80067a6: bf00 nop 80067a8: e000 b.n 80067ac break; 80067aa: bf00 nop } if (ret == HAL_OK) 80067ac: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80067b0: 2b00 cmp r3, #0 80067b2: d10a bne.n 80067ca { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 80067b4: 4b4f ldr r3, [pc, #316] @ (80068f4 ) 80067b6: 6d1b ldr r3, [r3, #80] @ 0x50 80067b8: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 80067bc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80067c0: 6ddb ldr r3, [r3, #92] @ 0x5c 80067c2: 4a4c ldr r2, [pc, #304] @ (80068f4 ) 80067c4: 430b orrs r3, r1 80067c6: 6513 str r3, [r2, #80] @ 0x50 80067c8: e003 b.n 80067d2 } else { /* set overall return value */ status = ret; 80067ca: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80067ce: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 80067d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80067d6: e9d3 2300 ldrd r2, r3, [r3] 80067da: f402 6380 and.w r3, r2, #1024 @ 0x400 80067de: f8c7 3100 str.w r3, [r7, #256] @ 0x100 80067e2: 2300 movs r3, #0 80067e4: f8c7 3104 str.w r3, [r7, #260] @ 0x104 80067e8: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 80067ec: 460b mov r3, r1 80067ee: 4313 orrs r3, r2 80067f0: d053 beq.n 800689a { switch (PeriphClkInit->Sai4AClockSelection) 80067f2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80067f6: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 80067fa: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 80067fe: d035 beq.n 800686c 8006800: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 8006804: d82e bhi.n 8006864 8006806: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800680a: d031 beq.n 8006870 800680c: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 8006810: d828 bhi.n 8006864 8006812: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8006816: d01a beq.n 800684e 8006818: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800681c: d822 bhi.n 8006864 800681e: 2b00 cmp r3, #0 8006820: d003 beq.n 800682a 8006822: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006826: d007 beq.n 8006838 8006828: e01c b.n 8006864 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800682a: 4b32 ldr r3, [pc, #200] @ (80068f4 ) 800682c: 6adb ldr r3, [r3, #44] @ 0x2c 800682e: 4a31 ldr r2, [pc, #196] @ (80068f4 ) 8006830: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8006834: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8006836: e01c b.n 8006872 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006838: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800683c: 3308 adds r3, #8 800683e: 2100 movs r1, #0 8006840: 4618 mov r0, r3 8006842: f001 fb67 bl 8007f14 8006846: 4603 mov r3, r0 8006848: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800684c: e011 b.n 8006872 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800684e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006852: 3328 adds r3, #40 @ 0x28 8006854: 2100 movs r1, #0 8006856: 4618 mov r0, r3 8006858: f001 fc0e bl 8008078 800685c: 4603 mov r3, r0 800685e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 8006862: e006 b.n 8006872 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 8006864: 2301 movs r3, #1 8006866: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800686a: e002 b.n 8006872 break; 800686c: bf00 nop 800686e: e000 b.n 8006872 break; 8006870: bf00 nop } if (ret == HAL_OK) 8006872: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006876: 2b00 cmp r3, #0 8006878: d10b bne.n 8006892 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800687a: 4b1e ldr r3, [pc, #120] @ (80068f4 ) 800687c: 6d9b ldr r3, [r3, #88] @ 0x58 800687e: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 8006882: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006886: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800688a: 4a1a ldr r2, [pc, #104] @ (80068f4 ) 800688c: 430b orrs r3, r1 800688e: 6593 str r3, [r2, #88] @ 0x58 8006890: e003 b.n 800689a } else { /* set overall return value */ status = ret; 8006892: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006896: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800689a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800689e: e9d3 2300 ldrd r2, r3, [r3] 80068a2: f402 6300 and.w r3, r2, #2048 @ 0x800 80068a6: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 80068aa: 2300 movs r3, #0 80068ac: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 80068b0: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 80068b4: 460b mov r3, r1 80068b6: 4313 orrs r3, r2 80068b8: d056 beq.n 8006968 { switch (PeriphClkInit->Sai4BClockSelection) 80068ba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80068be: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 80068c2: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 80068c6: d038 beq.n 800693a 80068c8: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 80068cc: d831 bhi.n 8006932 80068ce: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 80068d2: d034 beq.n 800693e 80068d4: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 80068d8: d82b bhi.n 8006932 80068da: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80068de: d01d beq.n 800691c 80068e0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80068e4: d825 bhi.n 8006932 80068e6: 2b00 cmp r3, #0 80068e8: d006 beq.n 80068f8 80068ea: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80068ee: d00a beq.n 8006906 80068f0: e01f b.n 8006932 80068f2: bf00 nop 80068f4: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80068f8: 4ba2 ldr r3, [pc, #648] @ (8006b84 ) 80068fa: 6adb ldr r3, [r3, #44] @ 0x2c 80068fc: 4aa1 ldr r2, [pc, #644] @ (8006b84 ) 80068fe: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8006902: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 8006904: e01c b.n 8006940 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006906: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800690a: 3308 adds r3, #8 800690c: 2100 movs r1, #0 800690e: 4618 mov r0, r3 8006910: f001 fb00 bl 8007f14 8006914: 4603 mov r3, r0 8006916: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800691a: e011 b.n 8006940 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800691c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006920: 3328 adds r3, #40 @ 0x28 8006922: 2100 movs r1, #0 8006924: 4618 mov r0, r3 8006926: f001 fba7 bl 8008078 800692a: 4603 mov r3, r0 800692c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 8006930: e006 b.n 8006940 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 8006932: 2301 movs r3, #1 8006934: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006938: e002 b.n 8006940 break; 800693a: bf00 nop 800693c: e000 b.n 8006940 break; 800693e: bf00 nop } if (ret == HAL_OK) 8006940: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006944: 2b00 cmp r3, #0 8006946: d10b bne.n 8006960 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 8006948: 4b8e ldr r3, [pc, #568] @ (8006b84 ) 800694a: 6d9b ldr r3, [r3, #88] @ 0x58 800694c: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 8006950: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006954: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 8006958: 4a8a ldr r2, [pc, #552] @ (8006b84 ) 800695a: 430b orrs r3, r1 800695c: 6593 str r3, [r2, #88] @ 0x58 800695e: e003 b.n 8006968 } else { /* set overall return value */ status = ret; 8006960: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006964: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 8006968: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800696c: e9d3 2300 ldrd r2, r3, [r3] 8006970: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 8006974: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 8006978: 2300 movs r3, #0 800697a: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800697e: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 8006982: 460b mov r3, r1 8006984: 4313 orrs r3, r2 8006986: d03a beq.n 80069fe { switch (PeriphClkInit->QspiClockSelection) 8006988: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800698c: 6cdb ldr r3, [r3, #76] @ 0x4c 800698e: 2b30 cmp r3, #48 @ 0x30 8006990: d01f beq.n 80069d2 8006992: 2b30 cmp r3, #48 @ 0x30 8006994: d819 bhi.n 80069ca 8006996: 2b20 cmp r3, #32 8006998: d00c beq.n 80069b4 800699a: 2b20 cmp r3, #32 800699c: d815 bhi.n 80069ca 800699e: 2b00 cmp r3, #0 80069a0: d019 beq.n 80069d6 80069a2: 2b10 cmp r3, #16 80069a4: d111 bne.n 80069ca { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80069a6: 4b77 ldr r3, [pc, #476] @ (8006b84 ) 80069a8: 6adb ldr r3, [r3, #44] @ 0x2c 80069aa: 4a76 ldr r2, [pc, #472] @ (8006b84 ) 80069ac: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80069b0: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 80069b2: e011 b.n 80069d8 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 80069b4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80069b8: 3308 adds r3, #8 80069ba: 2102 movs r1, #2 80069bc: 4618 mov r0, r3 80069be: f001 faa9 bl 8007f14 80069c2: 4603 mov r3, r0 80069c4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 80069c8: e006 b.n 80069d8 case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 80069ca: 2301 movs r3, #1 80069cc: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 80069d0: e002 b.n 80069d8 break; 80069d2: bf00 nop 80069d4: e000 b.n 80069d8 break; 80069d6: bf00 nop } if (ret == HAL_OK) 80069d8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80069dc: 2b00 cmp r3, #0 80069de: d10a bne.n 80069f6 { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 80069e0: 4b68 ldr r3, [pc, #416] @ (8006b84 ) 80069e2: 6cdb ldr r3, [r3, #76] @ 0x4c 80069e4: f023 0130 bic.w r1, r3, #48 @ 0x30 80069e8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80069ec: 6cdb ldr r3, [r3, #76] @ 0x4c 80069ee: 4a65 ldr r2, [pc, #404] @ (8006b84 ) 80069f0: 430b orrs r3, r1 80069f2: 64d3 str r3, [r2, #76] @ 0x4c 80069f4: e003 b.n 80069fe } else { /* set overall return value */ status = ret; 80069f6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80069fa: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 80069fe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006a02: e9d3 2300 ldrd r2, r3, [r3] 8006a06: f402 5380 and.w r3, r2, #4096 @ 0x1000 8006a0a: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8006a0e: 2300 movs r3, #0 8006a10: f8c7 30ec str.w r3, [r7, #236] @ 0xec 8006a14: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 8006a18: 460b mov r3, r1 8006a1a: 4313 orrs r3, r2 8006a1c: d051 beq.n 8006ac2 { switch (PeriphClkInit->Spi123ClockSelection) 8006a1e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006a22: 6e1b ldr r3, [r3, #96] @ 0x60 8006a24: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8006a28: d035 beq.n 8006a96 8006a2a: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8006a2e: d82e bhi.n 8006a8e 8006a30: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8006a34: d031 beq.n 8006a9a 8006a36: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 8006a3a: d828 bhi.n 8006a8e 8006a3c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8006a40: d01a beq.n 8006a78 8006a42: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8006a46: d822 bhi.n 8006a8e 8006a48: 2b00 cmp r3, #0 8006a4a: d003 beq.n 8006a54 8006a4c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8006a50: d007 beq.n 8006a62 8006a52: e01c b.n 8006a8e { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006a54: 4b4b ldr r3, [pc, #300] @ (8006b84 ) 8006a56: 6adb ldr r3, [r3, #44] @ 0x2c 8006a58: 4a4a ldr r2, [pc, #296] @ (8006b84 ) 8006a5a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8006a5e: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8006a60: e01c b.n 8006a9c case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8006a62: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006a66: 3308 adds r3, #8 8006a68: 2100 movs r1, #0 8006a6a: 4618 mov r0, r3 8006a6c: f001 fa52 bl 8007f14 8006a70: 4603 mov r3, r0 8006a72: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8006a76: e011 b.n 8006a9c case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 8006a78: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006a7c: 3328 adds r3, #40 @ 0x28 8006a7e: 2100 movs r1, #0 8006a80: 4618 mov r0, r3 8006a82: f001 faf9 bl 8008078 8006a86: 4603 mov r3, r0 8006a88: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 8006a8c: e006 b.n 8006a9c /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006a8e: 2301 movs r3, #1 8006a90: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006a94: e002 b.n 8006a9c break; 8006a96: bf00 nop 8006a98: e000 b.n 8006a9c break; 8006a9a: bf00 nop } if (ret == HAL_OK) 8006a9c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006aa0: 2b00 cmp r3, #0 8006aa2: d10a bne.n 8006aba { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 8006aa4: 4b37 ldr r3, [pc, #220] @ (8006b84 ) 8006aa6: 6d1b ldr r3, [r3, #80] @ 0x50 8006aa8: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 8006aac: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006ab0: 6e1b ldr r3, [r3, #96] @ 0x60 8006ab2: 4a34 ldr r2, [pc, #208] @ (8006b84 ) 8006ab4: 430b orrs r3, r1 8006ab6: 6513 str r3, [r2, #80] @ 0x50 8006ab8: e003 b.n 8006ac2 } else { /* set overall return value */ status = ret; 8006aba: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006abe: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 8006ac2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006ac6: e9d3 2300 ldrd r2, r3, [r3] 8006aca: f402 5300 and.w r3, r2, #8192 @ 0x2000 8006ace: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8006ad2: 2300 movs r3, #0 8006ad4: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8006ad8: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 8006adc: 460b mov r3, r1 8006ade: 4313 orrs r3, r2 8006ae0: d056 beq.n 8006b90 { switch (PeriphClkInit->Spi45ClockSelection) 8006ae2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006ae6: 6e5b ldr r3, [r3, #100] @ 0x64 8006ae8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8006aec: d033 beq.n 8006b56 8006aee: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 8006af2: d82c bhi.n 8006b4e 8006af4: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8006af8: d02f beq.n 8006b5a 8006afa: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8006afe: d826 bhi.n 8006b4e 8006b00: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006b04: d02b beq.n 8006b5e 8006b06: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006b0a: d820 bhi.n 8006b4e 8006b0c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006b10: d012 beq.n 8006b38 8006b12: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 8006b16: d81a bhi.n 8006b4e 8006b18: 2b00 cmp r3, #0 8006b1a: d022 beq.n 8006b62 8006b1c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8006b20: d115 bne.n 8006b4e /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8006b22: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006b26: 3308 adds r3, #8 8006b28: 2101 movs r1, #1 8006b2a: 4618 mov r0, r3 8006b2c: f001 f9f2 bl 8007f14 8006b30: 4603 mov r3, r0 8006b32: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 8006b36: e015 b.n 8006b64 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8006b38: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006b3c: 3328 adds r3, #40 @ 0x28 8006b3e: 2101 movs r1, #1 8006b40: 4618 mov r0, r3 8006b42: f001 fa99 bl 8008078 8006b46: 4603 mov r3, r0 8006b48: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 8006b4c: e00a b.n 8006b64 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006b4e: 2301 movs r3, #1 8006b50: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006b54: e006 b.n 8006b64 break; 8006b56: bf00 nop 8006b58: e004 b.n 8006b64 break; 8006b5a: bf00 nop 8006b5c: e002 b.n 8006b64 break; 8006b5e: bf00 nop 8006b60: e000 b.n 8006b64 break; 8006b62: bf00 nop } if (ret == HAL_OK) 8006b64: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006b68: 2b00 cmp r3, #0 8006b6a: d10d bne.n 8006b88 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 8006b6c: 4b05 ldr r3, [pc, #20] @ (8006b84 ) 8006b6e: 6d1b ldr r3, [r3, #80] @ 0x50 8006b70: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 8006b74: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006b78: 6e5b ldr r3, [r3, #100] @ 0x64 8006b7a: 4a02 ldr r2, [pc, #8] @ (8006b84 ) 8006b7c: 430b orrs r3, r1 8006b7e: 6513 str r3, [r2, #80] @ 0x50 8006b80: e006 b.n 8006b90 8006b82: bf00 nop 8006b84: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 8006b88: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006b8c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 8006b90: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006b94: e9d3 2300 ldrd r2, r3, [r3] 8006b98: f402 4380 and.w r3, r2, #16384 @ 0x4000 8006b9c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8006ba0: 2300 movs r3, #0 8006ba2: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 8006ba6: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8006baa: 460b mov r3, r1 8006bac: 4313 orrs r3, r2 8006bae: d055 beq.n 8006c5c { switch (PeriphClkInit->Spi6ClockSelection) 8006bb0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006bb4: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 8006bb8: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8006bbc: d033 beq.n 8006c26 8006bbe: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8006bc2: d82c bhi.n 8006c1e 8006bc4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006bc8: d02f beq.n 8006c2a 8006bca: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8006bce: d826 bhi.n 8006c1e 8006bd0: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8006bd4: d02b beq.n 8006c2e 8006bd6: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 8006bda: d820 bhi.n 8006c1e 8006bdc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006be0: d012 beq.n 8006c08 8006be2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006be6: d81a bhi.n 8006c1e 8006be8: 2b00 cmp r3, #0 8006bea: d022 beq.n 8006c32 8006bec: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8006bf0: d115 bne.n 8006c1e /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8006bf2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006bf6: 3308 adds r3, #8 8006bf8: 2101 movs r1, #1 8006bfa: 4618 mov r0, r3 8006bfc: f001 f98a bl 8007f14 8006c00: 4603 mov r3, r0 8006c02: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 8006c06: e015 b.n 8006c34 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8006c08: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006c0c: 3328 adds r3, #40 @ 0x28 8006c0e: 2101 movs r1, #1 8006c10: 4618 mov r0, r3 8006c12: f001 fa31 bl 8008078 8006c16: 4603 mov r3, r0 8006c18: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 8006c1c: e00a b.n 8006c34 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 8006c1e: 2301 movs r3, #1 8006c20: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006c24: e006 b.n 8006c34 break; 8006c26: bf00 nop 8006c28: e004 b.n 8006c34 break; 8006c2a: bf00 nop 8006c2c: e002 b.n 8006c34 break; 8006c2e: bf00 nop 8006c30: e000 b.n 8006c34 break; 8006c32: bf00 nop } if (ret == HAL_OK) 8006c34: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006c38: 2b00 cmp r3, #0 8006c3a: d10b bne.n 8006c54 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 8006c3c: 4ba3 ldr r3, [pc, #652] @ (8006ecc ) 8006c3e: 6d9b ldr r3, [r3, #88] @ 0x58 8006c40: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 8006c44: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006c48: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 8006c4c: 4a9f ldr r2, [pc, #636] @ (8006ecc ) 8006c4e: 430b orrs r3, r1 8006c50: 6593 str r3, [r2, #88] @ 0x58 8006c52: e003 b.n 8006c5c } else { /* set overall return value */ status = ret; 8006c54: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006c58: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 8006c5c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006c60: e9d3 2300 ldrd r2, r3, [r3] 8006c64: f402 4300 and.w r3, r2, #32768 @ 0x8000 8006c68: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8006c6c: 2300 movs r3, #0 8006c6e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 8006c72: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 8006c76: 460b mov r3, r1 8006c78: 4313 orrs r3, r2 8006c7a: d037 beq.n 8006cec { switch (PeriphClkInit->FdcanClockSelection) 8006c7c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006c80: 6f1b ldr r3, [r3, #112] @ 0x70 8006c82: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006c86: d00e beq.n 8006ca6 8006c88: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006c8c: d816 bhi.n 8006cbc 8006c8e: 2b00 cmp r3, #0 8006c90: d018 beq.n 8006cc4 8006c92: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8006c96: d111 bne.n 8006cbc { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006c98: 4b8c ldr r3, [pc, #560] @ (8006ecc ) 8006c9a: 6adb ldr r3, [r3, #44] @ 0x2c 8006c9c: 4a8b ldr r2, [pc, #556] @ (8006ecc ) 8006c9e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8006ca2: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 8006ca4: e00f b.n 8006cc6 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8006ca6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006caa: 3308 adds r3, #8 8006cac: 2101 movs r1, #1 8006cae: 4618 mov r0, r3 8006cb0: f001 f930 bl 8007f14 8006cb4: 4603 mov r3, r0 8006cb6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 8006cba: e004 b.n 8006cc6 /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006cbc: 2301 movs r3, #1 8006cbe: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006cc2: e000 b.n 8006cc6 break; 8006cc4: bf00 nop } if (ret == HAL_OK) 8006cc6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006cca: 2b00 cmp r3, #0 8006ccc: d10a bne.n 8006ce4 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 8006cce: 4b7f ldr r3, [pc, #508] @ (8006ecc ) 8006cd0: 6d1b ldr r3, [r3, #80] @ 0x50 8006cd2: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 8006cd6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006cda: 6f1b ldr r3, [r3, #112] @ 0x70 8006cdc: 4a7b ldr r2, [pc, #492] @ (8006ecc ) 8006cde: 430b orrs r3, r1 8006ce0: 6513 str r3, [r2, #80] @ 0x50 8006ce2: e003 b.n 8006cec } else { /* set overall return value */ status = ret; 8006ce4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006ce8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 8006cec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006cf0: e9d3 2300 ldrd r2, r3, [r3] 8006cf4: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 8006cf8: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8006cfc: 2300 movs r3, #0 8006cfe: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8006d02: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 8006d06: 460b mov r3, r1 8006d08: 4313 orrs r3, r2 8006d0a: d039 beq.n 8006d80 { switch (PeriphClkInit->FmcClockSelection) 8006d0c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006d10: 6c9b ldr r3, [r3, #72] @ 0x48 8006d12: 2b03 cmp r3, #3 8006d14: d81c bhi.n 8006d50 8006d16: a201 add r2, pc, #4 @ (adr r2, 8006d1c ) 8006d18: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006d1c: 08006d59 .word 0x08006d59 8006d20: 08006d2d .word 0x08006d2d 8006d24: 08006d3b .word 0x08006d3b 8006d28: 08006d59 .word 0x08006d59 { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8006d2c: 4b67 ldr r3, [pc, #412] @ (8006ecc ) 8006d2e: 6adb ldr r3, [r3, #44] @ 0x2c 8006d30: 4a66 ldr r2, [pc, #408] @ (8006ecc ) 8006d32: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8006d36: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 8006d38: e00f b.n 8006d5a case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8006d3a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006d3e: 3308 adds r3, #8 8006d40: 2102 movs r1, #2 8006d42: 4618 mov r0, r3 8006d44: f001 f8e6 bl 8007f14 8006d48: 4603 mov r3, r0 8006d4a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 8006d4e: e004 b.n 8006d5a case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 8006d50: 2301 movs r3, #1 8006d52: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006d56: e000 b.n 8006d5a break; 8006d58: bf00 nop } if (ret == HAL_OK) 8006d5a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006d5e: 2b00 cmp r3, #0 8006d60: d10a bne.n 8006d78 { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 8006d62: 4b5a ldr r3, [pc, #360] @ (8006ecc ) 8006d64: 6cdb ldr r3, [r3, #76] @ 0x4c 8006d66: f023 0103 bic.w r1, r3, #3 8006d6a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006d6e: 6c9b ldr r3, [r3, #72] @ 0x48 8006d70: 4a56 ldr r2, [pc, #344] @ (8006ecc ) 8006d72: 430b orrs r3, r1 8006d74: 64d3 str r3, [r2, #76] @ 0x4c 8006d76: e003 b.n 8006d80 } else { /* set overall return value */ status = ret; 8006d78: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006d7c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8006d80: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006d84: e9d3 2300 ldrd r2, r3, [r3] 8006d88: f402 0380 and.w r3, r2, #4194304 @ 0x400000 8006d8c: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8006d90: 2300 movs r3, #0 8006d92: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8006d96: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8006d9a: 460b mov r3, r1 8006d9c: 4313 orrs r3, r2 8006d9e: f000 809f beq.w 8006ee0 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8006da2: 4b4b ldr r3, [pc, #300] @ (8006ed0 ) 8006da4: 681b ldr r3, [r3, #0] 8006da6: 4a4a ldr r2, [pc, #296] @ (8006ed0 ) 8006da8: f443 7380 orr.w r3, r3, #256 @ 0x100 8006dac: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8006dae: f7fb fc57 bl 8002660 8006db2: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8006db6: e00b b.n 8006dd0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8006db8: f7fb fc52 bl 8002660 8006dbc: 4602 mov r2, r0 8006dbe: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 8006dc2: 1ad3 subs r3, r2, r3 8006dc4: 2b64 cmp r3, #100 @ 0x64 8006dc6: d903 bls.n 8006dd0 { ret = HAL_TIMEOUT; 8006dc8: 2303 movs r3, #3 8006dca: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006dce: e005 b.n 8006ddc while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 8006dd0: 4b3f ldr r3, [pc, #252] @ (8006ed0 ) 8006dd2: 681b ldr r3, [r3, #0] 8006dd4: f403 7380 and.w r3, r3, #256 @ 0x100 8006dd8: 2b00 cmp r3, #0 8006dda: d0ed beq.n 8006db8 } } if (ret == HAL_OK) 8006ddc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006de0: 2b00 cmp r3, #0 8006de2: d179 bne.n 8006ed8 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 8006de4: 4b39 ldr r3, [pc, #228] @ (8006ecc ) 8006de6: 6f1a ldr r2, [r3, #112] @ 0x70 8006de8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006dec: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 8006df0: 4053 eors r3, r2 8006df2: f403 7340 and.w r3, r3, #768 @ 0x300 8006df6: 2b00 cmp r3, #0 8006df8: d015 beq.n 8006e26 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 8006dfa: 4b34 ldr r3, [pc, #208] @ (8006ecc ) 8006dfc: 6f1b ldr r3, [r3, #112] @ 0x70 8006dfe: f423 7340 bic.w r3, r3, #768 @ 0x300 8006e02: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8006e06: 4b31 ldr r3, [pc, #196] @ (8006ecc ) 8006e08: 6f1b ldr r3, [r3, #112] @ 0x70 8006e0a: 4a30 ldr r2, [pc, #192] @ (8006ecc ) 8006e0c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8006e10: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 8006e12: 4b2e ldr r3, [pc, #184] @ (8006ecc ) 8006e14: 6f1b ldr r3, [r3, #112] @ 0x70 8006e16: 4a2d ldr r2, [pc, #180] @ (8006ecc ) 8006e18: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8006e1c: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 8006e1e: 4a2b ldr r2, [pc, #172] @ (8006ecc ) 8006e20: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 8006e24: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 8006e26: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006e2a: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 8006e2e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8006e32: d118 bne.n 8006e66 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8006e34: f7fb fc14 bl 8002660 8006e38: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8006e3c: e00d b.n 8006e5a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8006e3e: f7fb fc0f bl 8002660 8006e42: 4602 mov r2, r0 8006e44: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 8006e48: 1ad2 subs r2, r2, r3 8006e4a: f241 3388 movw r3, #5000 @ 0x1388 8006e4e: 429a cmp r2, r3 8006e50: d903 bls.n 8006e5a { ret = HAL_TIMEOUT; 8006e52: 2303 movs r3, #3 8006e54: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006e58: e005 b.n 8006e66 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 8006e5a: 4b1c ldr r3, [pc, #112] @ (8006ecc ) 8006e5c: 6f1b ldr r3, [r3, #112] @ 0x70 8006e5e: f003 0302 and.w r3, r3, #2 8006e62: 2b00 cmp r3, #0 8006e64: d0eb beq.n 8006e3e } } } if (ret == HAL_OK) 8006e66: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006e6a: 2b00 cmp r3, #0 8006e6c: d129 bne.n 8006ec2 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8006e6e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006e72: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 8006e76: f403 7340 and.w r3, r3, #768 @ 0x300 8006e7a: f5b3 7f40 cmp.w r3, #768 @ 0x300 8006e7e: d10e bne.n 8006e9e 8006e80: 4b12 ldr r3, [pc, #72] @ (8006ecc ) 8006e82: 691b ldr r3, [r3, #16] 8006e84: f423 517c bic.w r1, r3, #16128 @ 0x3f00 8006e88: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006e8c: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 8006e90: 091a lsrs r2, r3, #4 8006e92: 4b10 ldr r3, [pc, #64] @ (8006ed4 ) 8006e94: 4013 ands r3, r2 8006e96: 4a0d ldr r2, [pc, #52] @ (8006ecc ) 8006e98: 430b orrs r3, r1 8006e9a: 6113 str r3, [r2, #16] 8006e9c: e005 b.n 8006eaa 8006e9e: 4b0b ldr r3, [pc, #44] @ (8006ecc ) 8006ea0: 691b ldr r3, [r3, #16] 8006ea2: 4a0a ldr r2, [pc, #40] @ (8006ecc ) 8006ea4: f423 537c bic.w r3, r3, #16128 @ 0x3f00 8006ea8: 6113 str r3, [r2, #16] 8006eaa: 4b08 ldr r3, [pc, #32] @ (8006ecc ) 8006eac: 6f19 ldr r1, [r3, #112] @ 0x70 8006eae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006eb2: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 8006eb6: f3c3 030b ubfx r3, r3, #0, #12 8006eba: 4a04 ldr r2, [pc, #16] @ (8006ecc ) 8006ebc: 430b orrs r3, r1 8006ebe: 6713 str r3, [r2, #112] @ 0x70 8006ec0: e00e b.n 8006ee0 } else { /* set overall return value */ status = ret; 8006ec2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006ec6: f887 311e strb.w r3, [r7, #286] @ 0x11e 8006eca: e009 b.n 8006ee0 8006ecc: 58024400 .word 0x58024400 8006ed0: 58024800 .word 0x58024800 8006ed4: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 8006ed8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006edc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 8006ee0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006ee4: e9d3 2300 ldrd r2, r3, [r3] 8006ee8: f002 0301 and.w r3, r2, #1 8006eec: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8006ef0: 2300 movs r3, #0 8006ef2: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 8006ef6: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 8006efa: 460b mov r3, r1 8006efc: 4313 orrs r3, r2 8006efe: f000 8089 beq.w 8007014 { switch (PeriphClkInit->Usart16ClockSelection) 8006f02: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006f06: 6fdb ldr r3, [r3, #124] @ 0x7c 8006f08: 2b28 cmp r3, #40 @ 0x28 8006f0a: d86b bhi.n 8006fe4 8006f0c: a201 add r2, pc, #4 @ (adr r2, 8006f14 ) 8006f0e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8006f12: bf00 nop 8006f14: 08006fed .word 0x08006fed 8006f18: 08006fe5 .word 0x08006fe5 8006f1c: 08006fe5 .word 0x08006fe5 8006f20: 08006fe5 .word 0x08006fe5 8006f24: 08006fe5 .word 0x08006fe5 8006f28: 08006fe5 .word 0x08006fe5 8006f2c: 08006fe5 .word 0x08006fe5 8006f30: 08006fe5 .word 0x08006fe5 8006f34: 08006fb9 .word 0x08006fb9 8006f38: 08006fe5 .word 0x08006fe5 8006f3c: 08006fe5 .word 0x08006fe5 8006f40: 08006fe5 .word 0x08006fe5 8006f44: 08006fe5 .word 0x08006fe5 8006f48: 08006fe5 .word 0x08006fe5 8006f4c: 08006fe5 .word 0x08006fe5 8006f50: 08006fe5 .word 0x08006fe5 8006f54: 08006fcf .word 0x08006fcf 8006f58: 08006fe5 .word 0x08006fe5 8006f5c: 08006fe5 .word 0x08006fe5 8006f60: 08006fe5 .word 0x08006fe5 8006f64: 08006fe5 .word 0x08006fe5 8006f68: 08006fe5 .word 0x08006fe5 8006f6c: 08006fe5 .word 0x08006fe5 8006f70: 08006fe5 .word 0x08006fe5 8006f74: 08006fed .word 0x08006fed 8006f78: 08006fe5 .word 0x08006fe5 8006f7c: 08006fe5 .word 0x08006fe5 8006f80: 08006fe5 .word 0x08006fe5 8006f84: 08006fe5 .word 0x08006fe5 8006f88: 08006fe5 .word 0x08006fe5 8006f8c: 08006fe5 .word 0x08006fe5 8006f90: 08006fe5 .word 0x08006fe5 8006f94: 08006fed .word 0x08006fed 8006f98: 08006fe5 .word 0x08006fe5 8006f9c: 08006fe5 .word 0x08006fe5 8006fa0: 08006fe5 .word 0x08006fe5 8006fa4: 08006fe5 .word 0x08006fe5 8006fa8: 08006fe5 .word 0x08006fe5 8006fac: 08006fe5 .word 0x08006fe5 8006fb0: 08006fe5 .word 0x08006fe5 8006fb4: 08006fed .word 0x08006fed case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8006fb8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006fbc: 3308 adds r3, #8 8006fbe: 2101 movs r1, #1 8006fc0: 4618 mov r0, r3 8006fc2: f000 ffa7 bl 8007f14 8006fc6: 4603 mov r3, r0 8006fc8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 8006fcc: e00f b.n 8006fee case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8006fce: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8006fd2: 3328 adds r3, #40 @ 0x28 8006fd4: 2101 movs r1, #1 8006fd6: 4618 mov r0, r3 8006fd8: f001 f84e bl 8008078 8006fdc: 4603 mov r3, r0 8006fde: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 8006fe2: e004 b.n 8006fee /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8006fe4: 2301 movs r3, #1 8006fe6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8006fea: e000 b.n 8006fee break; 8006fec: bf00 nop } if (ret == HAL_OK) 8006fee: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8006ff2: 2b00 cmp r3, #0 8006ff4: d10a bne.n 800700c { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 8006ff6: 4bbf ldr r3, [pc, #764] @ (80072f4 ) 8006ff8: 6d5b ldr r3, [r3, #84] @ 0x54 8006ffa: f023 0138 bic.w r1, r3, #56 @ 0x38 8006ffe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007002: 6fdb ldr r3, [r3, #124] @ 0x7c 8007004: 4abb ldr r2, [pc, #748] @ (80072f4 ) 8007006: 430b orrs r3, r1 8007008: 6553 str r3, [r2, #84] @ 0x54 800700a: e003 b.n 8007014 } else { /* set overall return value */ status = ret; 800700c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007010: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 8007014: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007018: e9d3 2300 ldrd r2, r3, [r3] 800701c: f002 0302 and.w r3, r2, #2 8007020: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8007024: 2300 movs r3, #0 8007026: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800702a: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800702e: 460b mov r3, r1 8007030: 4313 orrs r3, r2 8007032: d041 beq.n 80070b8 { switch (PeriphClkInit->Usart234578ClockSelection) 8007034: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007038: 6f9b ldr r3, [r3, #120] @ 0x78 800703a: 2b05 cmp r3, #5 800703c: d824 bhi.n 8007088 800703e: a201 add r2, pc, #4 @ (adr r2, 8007044 ) 8007040: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007044: 08007091 .word 0x08007091 8007048: 0800705d .word 0x0800705d 800704c: 08007073 .word 0x08007073 8007050: 08007091 .word 0x08007091 8007054: 08007091 .word 0x08007091 8007058: 08007091 .word 0x08007091 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800705c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007060: 3308 adds r3, #8 8007062: 2101 movs r1, #1 8007064: 4618 mov r0, r3 8007066: f000 ff55 bl 8007f14 800706a: 4603 mov r3, r0 800706c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8007070: e00f b.n 8007092 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8007072: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007076: 3328 adds r3, #40 @ 0x28 8007078: 2101 movs r1, #1 800707a: 4618 mov r0, r3 800707c: f000 fffc bl 8008078 8007080: 4603 mov r3, r0 8007082: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 8007086: e004 b.n 8007092 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007088: 2301 movs r3, #1 800708a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800708e: e000 b.n 8007092 break; 8007090: bf00 nop } if (ret == HAL_OK) 8007092: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007096: 2b00 cmp r3, #0 8007098: d10a bne.n 80070b0 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800709a: 4b96 ldr r3, [pc, #600] @ (80072f4 ) 800709c: 6d5b ldr r3, [r3, #84] @ 0x54 800709e: f023 0107 bic.w r1, r3, #7 80070a2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80070a6: 6f9b ldr r3, [r3, #120] @ 0x78 80070a8: 4a92 ldr r2, [pc, #584] @ (80072f4 ) 80070aa: 430b orrs r3, r1 80070ac: 6553 str r3, [r2, #84] @ 0x54 80070ae: e003 b.n 80070b8 } else { /* set overall return value */ status = ret; 80070b0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80070b4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 80070b8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80070bc: e9d3 2300 ldrd r2, r3, [r3] 80070c0: f002 0304 and.w r3, r2, #4 80070c4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 80070c8: 2300 movs r3, #0 80070ca: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80070ce: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 80070d2: 460b mov r3, r1 80070d4: 4313 orrs r3, r2 80070d6: d044 beq.n 8007162 { switch (PeriphClkInit->Lpuart1ClockSelection) 80070d8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80070dc: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 80070e0: 2b05 cmp r3, #5 80070e2: d825 bhi.n 8007130 80070e4: a201 add r2, pc, #4 @ (adr r2, 80070ec ) 80070e6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80070ea: bf00 nop 80070ec: 08007139 .word 0x08007139 80070f0: 08007105 .word 0x08007105 80070f4: 0800711b .word 0x0800711b 80070f8: 08007139 .word 0x08007139 80070fc: 08007139 .word 0x08007139 8007100: 08007139 .word 0x08007139 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8007104: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007108: 3308 adds r3, #8 800710a: 2101 movs r1, #1 800710c: 4618 mov r0, r3 800710e: f000 ff01 bl 8007f14 8007112: 4603 mov r3, r0 8007114: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 8007118: e00f b.n 800713a case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800711a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800711e: 3328 adds r3, #40 @ 0x28 8007120: 2101 movs r1, #1 8007122: 4618 mov r0, r3 8007124: f000 ffa8 bl 8008078 8007128: 4603 mov r3, r0 800712a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800712e: e004 b.n 800713a /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007130: 2301 movs r3, #1 8007132: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8007136: e000 b.n 800713a break; 8007138: bf00 nop } if (ret == HAL_OK) 800713a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800713e: 2b00 cmp r3, #0 8007140: d10b bne.n 800715a { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8007142: 4b6c ldr r3, [pc, #432] @ (80072f4 ) 8007144: 6d9b ldr r3, [r3, #88] @ 0x58 8007146: f023 0107 bic.w r1, r3, #7 800714a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800714e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 8007152: 4a68 ldr r2, [pc, #416] @ (80072f4 ) 8007154: 430b orrs r3, r1 8007156: 6593 str r3, [r2, #88] @ 0x58 8007158: e003 b.n 8007162 } else { /* set overall return value */ status = ret; 800715a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800715e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 8007162: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007166: e9d3 2300 ldrd r2, r3, [r3] 800716a: f002 0320 and.w r3, r2, #32 800716e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8007172: 2300 movs r3, #0 8007174: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 8007178: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800717c: 460b mov r3, r1 800717e: 4313 orrs r3, r2 8007180: d055 beq.n 800722e { switch (PeriphClkInit->Lptim1ClockSelection) 8007182: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007186: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800718a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800718e: d033 beq.n 80071f8 8007190: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 8007194: d82c bhi.n 80071f0 8007196: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800719a: d02f beq.n 80071fc 800719c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80071a0: d826 bhi.n 80071f0 80071a2: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 80071a6: d02b beq.n 8007200 80071a8: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 80071ac: d820 bhi.n 80071f0 80071ae: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80071b2: d012 beq.n 80071da 80071b4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80071b8: d81a bhi.n 80071f0 80071ba: 2b00 cmp r3, #0 80071bc: d022 beq.n 8007204 80071be: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80071c2: d115 bne.n 80071f0 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80071c4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80071c8: 3308 adds r3, #8 80071ca: 2100 movs r1, #0 80071cc: 4618 mov r0, r3 80071ce: f000 fea1 bl 8007f14 80071d2: 4603 mov r3, r0 80071d4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 80071d8: e015 b.n 8007206 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 80071da: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80071de: 3328 adds r3, #40 @ 0x28 80071e0: 2102 movs r1, #2 80071e2: 4618 mov r0, r3 80071e4: f000 ff48 bl 8008078 80071e8: 4603 mov r3, r0 80071ea: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 80071ee: e00a b.n 8007206 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80071f0: 2301 movs r3, #1 80071f2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 80071f6: e006 b.n 8007206 break; 80071f8: bf00 nop 80071fa: e004 b.n 8007206 break; 80071fc: bf00 nop 80071fe: e002 b.n 8007206 break; 8007200: bf00 nop 8007202: e000 b.n 8007206 break; 8007204: bf00 nop } if (ret == HAL_OK) 8007206: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800720a: 2b00 cmp r3, #0 800720c: d10b bne.n 8007226 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800720e: 4b39 ldr r3, [pc, #228] @ (80072f4 ) 8007210: 6d5b ldr r3, [r3, #84] @ 0x54 8007212: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 8007216: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800721a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800721e: 4a35 ldr r2, [pc, #212] @ (80072f4 ) 8007220: 430b orrs r3, r1 8007222: 6553 str r3, [r2, #84] @ 0x54 8007224: e003 b.n 800722e } else { /* set overall return value */ status = ret; 8007226: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800722a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800722e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007232: e9d3 2300 ldrd r2, r3, [r3] 8007236: f002 0340 and.w r3, r2, #64 @ 0x40 800723a: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800723e: 2300 movs r3, #0 8007240: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8007244: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 8007248: 460b mov r3, r1 800724a: 4313 orrs r3, r2 800724c: d058 beq.n 8007300 { switch (PeriphClkInit->Lptim2ClockSelection) 800724e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007252: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 8007256: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800725a: d033 beq.n 80072c4 800725c: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 8007260: d82c bhi.n 80072bc 8007262: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8007266: d02f beq.n 80072c8 8007268: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800726c: d826 bhi.n 80072bc 800726e: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8007272: d02b beq.n 80072cc 8007274: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 8007278: d820 bhi.n 80072bc 800727a: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800727e: d012 beq.n 80072a6 8007280: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8007284: d81a bhi.n 80072bc 8007286: 2b00 cmp r3, #0 8007288: d022 beq.n 80072d0 800728a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800728e: d115 bne.n 80072bc /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8007290: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007294: 3308 adds r3, #8 8007296: 2100 movs r1, #0 8007298: 4618 mov r0, r3 800729a: f000 fe3b bl 8007f14 800729e: 4603 mov r3, r0 80072a0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 80072a4: e015 b.n 80072d2 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 80072a6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80072aa: 3328 adds r3, #40 @ 0x28 80072ac: 2102 movs r1, #2 80072ae: 4618 mov r0, r3 80072b0: f000 fee2 bl 8008078 80072b4: 4603 mov r3, r0 80072b6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 80072ba: e00a b.n 80072d2 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80072bc: 2301 movs r3, #1 80072be: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 80072c2: e006 b.n 80072d2 break; 80072c4: bf00 nop 80072c6: e004 b.n 80072d2 break; 80072c8: bf00 nop 80072ca: e002 b.n 80072d2 break; 80072cc: bf00 nop 80072ce: e000 b.n 80072d2 break; 80072d0: bf00 nop } if (ret == HAL_OK) 80072d2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80072d6: 2b00 cmp r3, #0 80072d8: d10e bne.n 80072f8 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 80072da: 4b06 ldr r3, [pc, #24] @ (80072f4 ) 80072dc: 6d9b ldr r3, [r3, #88] @ 0x58 80072de: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 80072e2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80072e6: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 80072ea: 4a02 ldr r2, [pc, #8] @ (80072f4 ) 80072ec: 430b orrs r3, r1 80072ee: 6593 str r3, [r2, #88] @ 0x58 80072f0: e006 b.n 8007300 80072f2: bf00 nop 80072f4: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 80072f8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80072fc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 8007300: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007304: e9d3 2300 ldrd r2, r3, [r3] 8007308: f002 0380 and.w r3, r2, #128 @ 0x80 800730c: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8007310: 2300 movs r3, #0 8007312: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8007316: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800731a: 460b mov r3, r1 800731c: 4313 orrs r3, r2 800731e: d055 beq.n 80073cc { switch (PeriphClkInit->Lptim345ClockSelection) 8007320: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007324: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8007328: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800732c: d033 beq.n 8007396 800732e: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 8007332: d82c bhi.n 800738e 8007334: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8007338: d02f beq.n 800739a 800733a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800733e: d826 bhi.n 800738e 8007340: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 8007344: d02b beq.n 800739e 8007346: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800734a: d820 bhi.n 800738e 800734c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8007350: d012 beq.n 8007378 8007352: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 8007356: d81a bhi.n 800738e 8007358: 2b00 cmp r3, #0 800735a: d022 beq.n 80073a2 800735c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8007360: d115 bne.n 800738e case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8007362: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007366: 3308 adds r3, #8 8007368: 2100 movs r1, #0 800736a: 4618 mov r0, r3 800736c: f000 fdd2 bl 8007f14 8007370: 4603 mov r3, r0 8007372: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 8007376: e015 b.n 80073a4 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8007378: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800737c: 3328 adds r3, #40 @ 0x28 800737e: 2102 movs r1, #2 8007380: 4618 mov r0, r3 8007382: f000 fe79 bl 8008078 8007386: 4603 mov r3, r0 8007388: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800738c: e00a b.n 80073a4 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800738e: 2301 movs r3, #1 8007390: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8007394: e006 b.n 80073a4 break; 8007396: bf00 nop 8007398: e004 b.n 80073a4 break; 800739a: bf00 nop 800739c: e002 b.n 80073a4 break; 800739e: bf00 nop 80073a0: e000 b.n 80073a4 break; 80073a2: bf00 nop } if (ret == HAL_OK) 80073a4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80073a8: 2b00 cmp r3, #0 80073aa: d10b bne.n 80073c4 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 80073ac: 4bbb ldr r3, [pc, #748] @ (800769c ) 80073ae: 6d9b ldr r3, [r3, #88] @ 0x58 80073b0: f423 4160 bic.w r1, r3, #57344 @ 0xe000 80073b4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80073b8: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 80073bc: 4ab7 ldr r2, [pc, #732] @ (800769c ) 80073be: 430b orrs r3, r1 80073c0: 6593 str r3, [r2, #88] @ 0x58 80073c2: e003 b.n 80073cc } else { /* set overall return value */ status = ret; 80073c4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80073c8: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 80073cc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80073d0: e9d3 2300 ldrd r2, r3, [r3] 80073d4: f002 0308 and.w r3, r2, #8 80073d8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80073dc: 2300 movs r3, #0 80073de: f8c7 308c str.w r3, [r7, #140] @ 0x8c 80073e2: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 80073e6: 460b mov r3, r1 80073e8: 4313 orrs r3, r2 80073ea: d01e beq.n 800742a { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 80073ec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80073f0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 80073f4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80073f8: d10c bne.n 8007414 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 80073fa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80073fe: 3328 adds r3, #40 @ 0x28 8007400: 2102 movs r1, #2 8007402: 4618 mov r0, r3 8007404: f000 fe38 bl 8008078 8007408: 4603 mov r3, r0 800740a: 2b00 cmp r3, #0 800740c: d002 beq.n 8007414 { status = HAL_ERROR; 800740e: 2301 movs r3, #1 8007410: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 8007414: 4ba1 ldr r3, [pc, #644] @ (800769c ) 8007416: 6d5b ldr r3, [r3, #84] @ 0x54 8007418: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800741c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007420: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8007424: 4a9d ldr r2, [pc, #628] @ (800769c ) 8007426: 430b orrs r3, r1 8007428: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800742a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800742e: e9d3 2300 ldrd r2, r3, [r3] 8007432: f002 0310 and.w r3, r2, #16 8007436: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800743a: 2300 movs r3, #0 800743c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8007440: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 8007444: 460b mov r3, r1 8007446: 4313 orrs r3, r2 8007448: d01e beq.n 8007488 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800744a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800744e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8007452: f5b3 7f80 cmp.w r3, #256 @ 0x100 8007456: d10c bne.n 8007472 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 8007458: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800745c: 3328 adds r3, #40 @ 0x28 800745e: 2102 movs r1, #2 8007460: 4618 mov r0, r3 8007462: f000 fe09 bl 8008078 8007466: 4603 mov r3, r0 8007468: 2b00 cmp r3, #0 800746a: d002 beq.n 8007472 { status = HAL_ERROR; 800746c: 2301 movs r3, #1 800746e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 8007472: 4b8a ldr r3, [pc, #552] @ (800769c ) 8007474: 6d9b ldr r3, [r3, #88] @ 0x58 8007476: f423 7140 bic.w r1, r3, #768 @ 0x300 800747a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800747e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 8007482: 4a86 ldr r2, [pc, #536] @ (800769c ) 8007484: 430b orrs r3, r1 8007486: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 8007488: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800748c: e9d3 2300 ldrd r2, r3, [r3] 8007490: f402 2300 and.w r3, r2, #524288 @ 0x80000 8007494: 67bb str r3, [r7, #120] @ 0x78 8007496: 2300 movs r3, #0 8007498: 67fb str r3, [r7, #124] @ 0x7c 800749a: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800749e: 460b mov r3, r1 80074a0: 4313 orrs r3, r2 80074a2: d03e beq.n 8007522 { switch (PeriphClkInit->AdcClockSelection) 80074a4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80074a8: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 80074ac: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80074b0: d022 beq.n 80074f8 80074b2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80074b6: d81b bhi.n 80074f0 80074b8: 2b00 cmp r3, #0 80074ba: d003 beq.n 80074c4 80074bc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80074c0: d00b beq.n 80074da 80074c2: e015 b.n 80074f0 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 80074c4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80074c8: 3308 adds r3, #8 80074ca: 2100 movs r1, #0 80074cc: 4618 mov r0, r3 80074ce: f000 fd21 bl 8007f14 80074d2: 4603 mov r3, r0 80074d4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 80074d8: e00f b.n 80074fa case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 80074da: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80074de: 3328 adds r3, #40 @ 0x28 80074e0: 2102 movs r1, #2 80074e2: 4618 mov r0, r3 80074e4: f000 fdc8 bl 8008078 80074e8: 4603 mov r3, r0 80074ea: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 80074ee: e004 b.n 80074fa /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 80074f0: 2301 movs r3, #1 80074f2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 80074f6: e000 b.n 80074fa break; 80074f8: bf00 nop } if (ret == HAL_OK) 80074fa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80074fe: 2b00 cmp r3, #0 8007500: d10b bne.n 800751a { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8007502: 4b66 ldr r3, [pc, #408] @ (800769c ) 8007504: 6d9b ldr r3, [r3, #88] @ 0x58 8007506: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800750a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800750e: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 8007512: 4a62 ldr r2, [pc, #392] @ (800769c ) 8007514: 430b orrs r3, r1 8007516: 6593 str r3, [r2, #88] @ 0x58 8007518: e003 b.n 8007522 } else { /* set overall return value */ status = ret; 800751a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800751e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 8007522: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007526: e9d3 2300 ldrd r2, r3, [r3] 800752a: f402 2380 and.w r3, r2, #262144 @ 0x40000 800752e: 673b str r3, [r7, #112] @ 0x70 8007530: 2300 movs r3, #0 8007532: 677b str r3, [r7, #116] @ 0x74 8007534: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 8007538: 460b mov r3, r1 800753a: 4313 orrs r3, r2 800753c: d03b beq.n 80075b6 { switch (PeriphClkInit->UsbClockSelection) 800753e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007542: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8007546: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800754a: d01f beq.n 800758c 800754c: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 8007550: d818 bhi.n 8007584 8007552: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8007556: d003 beq.n 8007560 8007558: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800755c: d007 beq.n 800756e 800755e: e011 b.n 8007584 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 8007560: 4b4e ldr r3, [pc, #312] @ (800769c ) 8007562: 6adb ldr r3, [r3, #44] @ 0x2c 8007564: 4a4d ldr r2, [pc, #308] @ (800769c ) 8007566: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800756a: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800756c: e00f b.n 800758e case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800756e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007572: 3328 adds r3, #40 @ 0x28 8007574: 2101 movs r1, #1 8007576: 4618 mov r0, r3 8007578: f000 fd7e bl 8008078 800757c: 4603 mov r3, r0 800757e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 8007582: e004 b.n 800758e /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 8007584: 2301 movs r3, #1 8007586: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800758a: e000 b.n 800758e break; 800758c: bf00 nop } if (ret == HAL_OK) 800758e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007592: 2b00 cmp r3, #0 8007594: d10b bne.n 80075ae { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 8007596: 4b41 ldr r3, [pc, #260] @ (800769c ) 8007598: 6d5b ldr r3, [r3, #84] @ 0x54 800759a: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800759e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80075a2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80075a6: 4a3d ldr r2, [pc, #244] @ (800769c ) 80075a8: 430b orrs r3, r1 80075aa: 6553 str r3, [r2, #84] @ 0x54 80075ac: e003 b.n 80075b6 } else { /* set overall return value */ status = ret; 80075ae: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80075b2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 80075b6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80075ba: e9d3 2300 ldrd r2, r3, [r3] 80075be: f402 3380 and.w r3, r2, #65536 @ 0x10000 80075c2: 66bb str r3, [r7, #104] @ 0x68 80075c4: 2300 movs r3, #0 80075c6: 66fb str r3, [r7, #108] @ 0x6c 80075c8: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 80075cc: 460b mov r3, r1 80075ce: 4313 orrs r3, r2 80075d0: d031 beq.n 8007636 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 80075d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80075d6: 6d1b ldr r3, [r3, #80] @ 0x50 80075d8: 2b00 cmp r3, #0 80075da: d003 beq.n 80075e4 80075dc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80075e0: d007 beq.n 80075f2 80075e2: e011 b.n 8007608 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 80075e4: 4b2d ldr r3, [pc, #180] @ (800769c ) 80075e6: 6adb ldr r3, [r3, #44] @ 0x2c 80075e8: 4a2c ldr r2, [pc, #176] @ (800769c ) 80075ea: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80075ee: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 80075f0: e00e b.n 8007610 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 80075f2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80075f6: 3308 adds r3, #8 80075f8: 2102 movs r1, #2 80075fa: 4618 mov r0, r3 80075fc: f000 fc8a bl 8007f14 8007600: 4603 mov r3, r0 8007602: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 8007606: e003 b.n 8007610 default: ret = HAL_ERROR; 8007608: 2301 movs r3, #1 800760a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800760e: bf00 nop } if (ret == HAL_OK) 8007610: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007614: 2b00 cmp r3, #0 8007616: d10a bne.n 800762e { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 8007618: 4b20 ldr r3, [pc, #128] @ (800769c ) 800761a: 6cdb ldr r3, [r3, #76] @ 0x4c 800761c: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8007620: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007624: 6d1b ldr r3, [r3, #80] @ 0x50 8007626: 4a1d ldr r2, [pc, #116] @ (800769c ) 8007628: 430b orrs r3, r1 800762a: 64d3 str r3, [r2, #76] @ 0x4c 800762c: e003 b.n 8007636 } else { /* set overall return value */ status = ret; 800762e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007632: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 8007636: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800763a: e9d3 2300 ldrd r2, r3, [r3] 800763e: f402 3300 and.w r3, r2, #131072 @ 0x20000 8007642: 663b str r3, [r7, #96] @ 0x60 8007644: 2300 movs r3, #0 8007646: 667b str r3, [r7, #100] @ 0x64 8007648: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800764c: 460b mov r3, r1 800764e: 4313 orrs r3, r2 8007650: d03b beq.n 80076ca { switch (PeriphClkInit->RngClockSelection) 8007652: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007656: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800765a: f5b3 7f40 cmp.w r3, #768 @ 0x300 800765e: d018 beq.n 8007692 8007660: f5b3 7f40 cmp.w r3, #768 @ 0x300 8007664: d811 bhi.n 800768a 8007666: f5b3 7f00 cmp.w r3, #512 @ 0x200 800766a: d014 beq.n 8007696 800766c: f5b3 7f00 cmp.w r3, #512 @ 0x200 8007670: d80b bhi.n 800768a 8007672: 2b00 cmp r3, #0 8007674: d014 beq.n 80076a0 8007676: f5b3 7f80 cmp.w r3, #256 @ 0x100 800767a: d106 bne.n 800768a { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800767c: 4b07 ldr r3, [pc, #28] @ (800769c ) 800767e: 6adb ldr r3, [r3, #44] @ 0x2c 8007680: 4a06 ldr r2, [pc, #24] @ (800769c ) 8007682: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8007686: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 8007688: e00b b.n 80076a2 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800768a: 2301 movs r3, #1 800768c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 8007690: e007 b.n 80076a2 break; 8007692: bf00 nop 8007694: e005 b.n 80076a2 break; 8007696: bf00 nop 8007698: e003 b.n 80076a2 800769a: bf00 nop 800769c: 58024400 .word 0x58024400 break; 80076a0: bf00 nop } if (ret == HAL_OK) 80076a2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80076a6: 2b00 cmp r3, #0 80076a8: d10b bne.n 80076c2 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 80076aa: 4bba ldr r3, [pc, #744] @ (8007994 ) 80076ac: 6d5b ldr r3, [r3, #84] @ 0x54 80076ae: f423 7140 bic.w r1, r3, #768 @ 0x300 80076b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80076b6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80076ba: 4ab6 ldr r2, [pc, #728] @ (8007994 ) 80076bc: 430b orrs r3, r1 80076be: 6553 str r3, [r2, #84] @ 0x54 80076c0: e003 b.n 80076ca } else { /* set overall return value */ status = ret; 80076c2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80076c6: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 80076ca: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80076ce: e9d3 2300 ldrd r2, r3, [r3] 80076d2: f402 1380 and.w r3, r2, #1048576 @ 0x100000 80076d6: 65bb str r3, [r7, #88] @ 0x58 80076d8: 2300 movs r3, #0 80076da: 65fb str r3, [r7, #92] @ 0x5c 80076dc: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 80076e0: 460b mov r3, r1 80076e2: 4313 orrs r3, r2 80076e4: d009 beq.n 80076fa { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 80076e6: 4bab ldr r3, [pc, #684] @ (8007994 ) 80076e8: 6d1b ldr r3, [r3, #80] @ 0x50 80076ea: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 80076ee: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80076f2: 6f5b ldr r3, [r3, #116] @ 0x74 80076f4: 4aa7 ldr r2, [pc, #668] @ (8007994 ) 80076f6: 430b orrs r3, r1 80076f8: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 80076fa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80076fe: e9d3 2300 ldrd r2, r3, [r3] 8007702: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 8007706: 653b str r3, [r7, #80] @ 0x50 8007708: 2300 movs r3, #0 800770a: 657b str r3, [r7, #84] @ 0x54 800770c: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 8007710: 460b mov r3, r1 8007712: 4313 orrs r3, r2 8007714: d00a beq.n 800772c { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 8007716: 4b9f ldr r3, [pc, #636] @ (8007994 ) 8007718: 691b ldr r3, [r3, #16] 800771a: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800771e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007722: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 8007726: 4a9b ldr r2, [pc, #620] @ (8007994 ) 8007728: 430b orrs r3, r1 800772a: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800772c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007730: e9d3 2300 ldrd r2, r3, [r3] 8007734: f402 1300 and.w r3, r2, #2097152 @ 0x200000 8007738: 64bb str r3, [r7, #72] @ 0x48 800773a: 2300 movs r3, #0 800773c: 64fb str r3, [r7, #76] @ 0x4c 800773e: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 8007742: 460b mov r3, r1 8007744: 4313 orrs r3, r2 8007746: d009 beq.n 800775c { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 8007748: 4b92 ldr r3, [pc, #584] @ (8007994 ) 800774a: 6d1b ldr r3, [r3, #80] @ 0x50 800774c: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 8007750: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007754: 6edb ldr r3, [r3, #108] @ 0x6c 8007756: 4a8f ldr r2, [pc, #572] @ (8007994 ) 8007758: 430b orrs r3, r1 800775a: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800775c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007760: e9d3 2300 ldrd r2, r3, [r3] 8007764: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 8007768: 643b str r3, [r7, #64] @ 0x40 800776a: 2300 movs r3, #0 800776c: 647b str r3, [r7, #68] @ 0x44 800776e: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 8007772: 460b mov r3, r1 8007774: 4313 orrs r3, r2 8007776: d00e beq.n 8007796 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8007778: 4b86 ldr r3, [pc, #536] @ (8007994 ) 800777a: 691b ldr r3, [r3, #16] 800777c: 4a85 ldr r2, [pc, #532] @ (8007994 ) 800777e: f423 4300 bic.w r3, r3, #32768 @ 0x8000 8007782: 6113 str r3, [r2, #16] 8007784: 4b83 ldr r3, [pc, #524] @ (8007994 ) 8007786: 6919 ldr r1, [r3, #16] 8007788: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800778c: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 8007790: 4a80 ldr r2, [pc, #512] @ (8007994 ) 8007792: 430b orrs r3, r1 8007794: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 8007796: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800779a: e9d3 2300 ldrd r2, r3, [r3] 800779e: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 80077a2: 63bb str r3, [r7, #56] @ 0x38 80077a4: 2300 movs r3, #0 80077a6: 63fb str r3, [r7, #60] @ 0x3c 80077a8: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 80077ac: 460b mov r3, r1 80077ae: 4313 orrs r3, r2 80077b0: d009 beq.n 80077c6 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 80077b2: 4b78 ldr r3, [pc, #480] @ (8007994 ) 80077b4: 6cdb ldr r3, [r3, #76] @ 0x4c 80077b6: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 80077ba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80077be: 6d5b ldr r3, [r3, #84] @ 0x54 80077c0: 4a74 ldr r2, [pc, #464] @ (8007994 ) 80077c2: 430b orrs r3, r1 80077c4: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 80077c6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80077ca: e9d3 2300 ldrd r2, r3, [r3] 80077ce: f402 0300 and.w r3, r2, #8388608 @ 0x800000 80077d2: 633b str r3, [r7, #48] @ 0x30 80077d4: 2300 movs r3, #0 80077d6: 637b str r3, [r7, #52] @ 0x34 80077d8: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 80077dc: 460b mov r3, r1 80077de: 4313 orrs r3, r2 80077e0: d00a beq.n 80077f8 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 80077e2: 4b6c ldr r3, [pc, #432] @ (8007994 ) 80077e4: 6d5b ldr r3, [r3, #84] @ 0x54 80077e6: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 80077ea: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80077ee: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80077f2: 4a68 ldr r2, [pc, #416] @ (8007994 ) 80077f4: 430b orrs r3, r1 80077f6: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 80077f8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80077fc: e9d3 2300 ldrd r2, r3, [r3] 8007800: 2100 movs r1, #0 8007802: 62b9 str r1, [r7, #40] @ 0x28 8007804: f003 0301 and.w r3, r3, #1 8007808: 62fb str r3, [r7, #44] @ 0x2c 800780a: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800780e: 460b mov r3, r1 8007810: 4313 orrs r3, r2 8007812: d011 beq.n 8007838 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 8007814: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007818: 3308 adds r3, #8 800781a: 2100 movs r1, #0 800781c: 4618 mov r0, r3 800781e: f000 fb79 bl 8007f14 8007822: 4603 mov r3, r0 8007824: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 8007828: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800782c: 2b00 cmp r3, #0 800782e: d003 beq.n 8007838 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8007830: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007834: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 8007838: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800783c: e9d3 2300 ldrd r2, r3, [r3] 8007840: 2100 movs r1, #0 8007842: 6239 str r1, [r7, #32] 8007844: f003 0302 and.w r3, r3, #2 8007848: 627b str r3, [r7, #36] @ 0x24 800784a: e9d7 1208 ldrd r1, r2, [r7, #32] 800784e: 460b mov r3, r1 8007850: 4313 orrs r3, r2 8007852: d011 beq.n 8007878 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 8007854: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007858: 3308 adds r3, #8 800785a: 2101 movs r1, #1 800785c: 4618 mov r0, r3 800785e: f000 fb59 bl 8007f14 8007862: 4603 mov r3, r0 8007864: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 8007868: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800786c: 2b00 cmp r3, #0 800786e: d003 beq.n 8007878 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8007870: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007874: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 8007878: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800787c: e9d3 2300 ldrd r2, r3, [r3] 8007880: 2100 movs r1, #0 8007882: 61b9 str r1, [r7, #24] 8007884: f003 0304 and.w r3, r3, #4 8007888: 61fb str r3, [r7, #28] 800788a: e9d7 1206 ldrd r1, r2, [r7, #24] 800788e: 460b mov r3, r1 8007890: 4313 orrs r3, r2 8007892: d011 beq.n 80078b8 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 8007894: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007898: 3308 adds r3, #8 800789a: 2102 movs r1, #2 800789c: 4618 mov r0, r3 800789e: f000 fb39 bl 8007f14 80078a2: 4603 mov r3, r0 80078a4: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 80078a8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80078ac: 2b00 cmp r3, #0 80078ae: d003 beq.n 80078b8 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 80078b0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80078b4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 80078b8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80078bc: e9d3 2300 ldrd r2, r3, [r3] 80078c0: 2100 movs r1, #0 80078c2: 6139 str r1, [r7, #16] 80078c4: f003 0308 and.w r3, r3, #8 80078c8: 617b str r3, [r7, #20] 80078ca: e9d7 1204 ldrd r1, r2, [r7, #16] 80078ce: 460b mov r3, r1 80078d0: 4313 orrs r3, r2 80078d2: d011 beq.n 80078f8 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 80078d4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80078d8: 3328 adds r3, #40 @ 0x28 80078da: 2100 movs r1, #0 80078dc: 4618 mov r0, r3 80078de: f000 fbcb bl 8008078 80078e2: 4603 mov r3, r0 80078e4: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 80078e8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80078ec: 2b00 cmp r3, #0 80078ee: d003 beq.n 80078f8 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 80078f0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 80078f4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 80078f8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 80078fc: e9d3 2300 ldrd r2, r3, [r3] 8007900: 2100 movs r1, #0 8007902: 60b9 str r1, [r7, #8] 8007904: f003 0310 and.w r3, r3, #16 8007908: 60fb str r3, [r7, #12] 800790a: e9d7 1202 ldrd r1, r2, [r7, #8] 800790e: 460b mov r3, r1 8007910: 4313 orrs r3, r2 8007912: d011 beq.n 8007938 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 8007914: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007918: 3328 adds r3, #40 @ 0x28 800791a: 2101 movs r1, #1 800791c: 4618 mov r0, r3 800791e: f000 fbab bl 8008078 8007922: 4603 mov r3, r0 8007924: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 8007928: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800792c: 2b00 cmp r3, #0 800792e: d003 beq.n 8007938 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8007930: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007934: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 8007938: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800793c: e9d3 2300 ldrd r2, r3, [r3] 8007940: 2100 movs r1, #0 8007942: 6039 str r1, [r7, #0] 8007944: f003 0320 and.w r3, r3, #32 8007948: 607b str r3, [r7, #4] 800794a: e9d7 1200 ldrd r1, r2, [r7] 800794e: 460b mov r3, r1 8007950: 4313 orrs r3, r2 8007952: d011 beq.n 8007978 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 8007954: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 8007958: 3328 adds r3, #40 @ 0x28 800795a: 2102 movs r1, #2 800795c: 4618 mov r0, r3 800795e: f000 fb8b bl 8008078 8007962: 4603 mov r3, r0 8007964: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 8007968: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800796c: 2b00 cmp r3, #0 800796e: d003 beq.n 8007978 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 8007970: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 8007974: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 8007978: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800797c: 2b00 cmp r3, #0 800797e: d101 bne.n 8007984 { return HAL_OK; 8007980: 2300 movs r3, #0 8007982: e000 b.n 8007986 } return HAL_ERROR; 8007984: 2301 movs r3, #1 } 8007986: 4618 mov r0, r3 8007988: f507 7790 add.w r7, r7, #288 @ 0x120 800798c: 46bd mov sp, r7 800798e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8007992: bf00 nop 8007994: 58024400 .word 0x58024400 08007998 : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 8007998: b580 push {r7, lr} 800799a: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800799c: f7fe fd70 bl 8006480 80079a0: 4602 mov r2, r0 80079a2: 4b06 ldr r3, [pc, #24] @ (80079bc ) 80079a4: 6a1b ldr r3, [r3, #32] 80079a6: 091b lsrs r3, r3, #4 80079a8: f003 0307 and.w r3, r3, #7 80079ac: 4904 ldr r1, [pc, #16] @ (80079c0 ) 80079ae: 5ccb ldrb r3, [r1, r3] 80079b0: f003 031f and.w r3, r3, #31 80079b4: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 80079b8: 4618 mov r0, r3 80079ba: bd80 pop {r7, pc} 80079bc: 58024400 .word 0x58024400 80079c0: 080100b0 .word 0x080100b0 080079c4 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 80079c4: b480 push {r7} 80079c6: b089 sub sp, #36 @ 0x24 80079c8: af00 add r7, sp, #0 80079ca: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 80079cc: 4ba1 ldr r3, [pc, #644] @ (8007c54 ) 80079ce: 6a9b ldr r3, [r3, #40] @ 0x28 80079d0: f003 0303 and.w r3, r3, #3 80079d4: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 80079d6: 4b9f ldr r3, [pc, #636] @ (8007c54 ) 80079d8: 6a9b ldr r3, [r3, #40] @ 0x28 80079da: 0b1b lsrs r3, r3, #12 80079dc: f003 033f and.w r3, r3, #63 @ 0x3f 80079e0: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 80079e2: 4b9c ldr r3, [pc, #624] @ (8007c54 ) 80079e4: 6adb ldr r3, [r3, #44] @ 0x2c 80079e6: 091b lsrs r3, r3, #4 80079e8: f003 0301 and.w r3, r3, #1 80079ec: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 80079ee: 4b99 ldr r3, [pc, #612] @ (8007c54 ) 80079f0: 6bdb ldr r3, [r3, #60] @ 0x3c 80079f2: 08db lsrs r3, r3, #3 80079f4: f3c3 030c ubfx r3, r3, #0, #13 80079f8: 693a ldr r2, [r7, #16] 80079fa: fb02 f303 mul.w r3, r2, r3 80079fe: ee07 3a90 vmov s15, r3 8007a02: eef8 7a67 vcvt.f32.u32 s15, s15 8007a06: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 8007a0a: 697b ldr r3, [r7, #20] 8007a0c: 2b00 cmp r3, #0 8007a0e: f000 8111 beq.w 8007c34 { switch (pllsource) 8007a12: 69bb ldr r3, [r7, #24] 8007a14: 2b02 cmp r3, #2 8007a16: f000 8083 beq.w 8007b20 8007a1a: 69bb ldr r3, [r7, #24] 8007a1c: 2b02 cmp r3, #2 8007a1e: f200 80a1 bhi.w 8007b64 8007a22: 69bb ldr r3, [r7, #24] 8007a24: 2b00 cmp r3, #0 8007a26: d003 beq.n 8007a30 8007a28: 69bb ldr r3, [r7, #24] 8007a2a: 2b01 cmp r3, #1 8007a2c: d056 beq.n 8007adc 8007a2e: e099 b.n 8007b64 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007a30: 4b88 ldr r3, [pc, #544] @ (8007c54 ) 8007a32: 681b ldr r3, [r3, #0] 8007a34: f003 0320 and.w r3, r3, #32 8007a38: 2b00 cmp r3, #0 8007a3a: d02d beq.n 8007a98 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007a3c: 4b85 ldr r3, [pc, #532] @ (8007c54 ) 8007a3e: 681b ldr r3, [r3, #0] 8007a40: 08db lsrs r3, r3, #3 8007a42: f003 0303 and.w r3, r3, #3 8007a46: 4a84 ldr r2, [pc, #528] @ (8007c58 ) 8007a48: fa22 f303 lsr.w r3, r2, r3 8007a4c: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8007a4e: 68bb ldr r3, [r7, #8] 8007a50: ee07 3a90 vmov s15, r3 8007a54: eef8 6a67 vcvt.f32.u32 s13, s15 8007a58: 697b ldr r3, [r7, #20] 8007a5a: ee07 3a90 vmov s15, r3 8007a5e: eef8 7a67 vcvt.f32.u32 s15, s15 8007a62: ee86 7aa7 vdiv.f32 s14, s13, s15 8007a66: 4b7b ldr r3, [pc, #492] @ (8007c54 ) 8007a68: 6b9b ldr r3, [r3, #56] @ 0x38 8007a6a: f3c3 0308 ubfx r3, r3, #0, #9 8007a6e: ee07 3a90 vmov s15, r3 8007a72: eef8 6a67 vcvt.f32.u32 s13, s15 8007a76: ed97 6a03 vldr s12, [r7, #12] 8007a7a: eddf 5a78 vldr s11, [pc, #480] @ 8007c5c 8007a7e: eec6 7a25 vdiv.f32 s15, s12, s11 8007a82: ee76 7aa7 vadd.f32 s15, s13, s15 8007a86: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007a8a: ee77 7aa6 vadd.f32 s15, s15, s13 8007a8e: ee67 7a27 vmul.f32 s15, s14, s15 8007a92: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 8007a96: e087 b.n 8007ba8 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8007a98: 697b ldr r3, [r7, #20] 8007a9a: ee07 3a90 vmov s15, r3 8007a9e: eef8 7a67 vcvt.f32.u32 s15, s15 8007aa2: eddf 6a6f vldr s13, [pc, #444] @ 8007c60 8007aa6: ee86 7aa7 vdiv.f32 s14, s13, s15 8007aaa: 4b6a ldr r3, [pc, #424] @ (8007c54 ) 8007aac: 6b9b ldr r3, [r3, #56] @ 0x38 8007aae: f3c3 0308 ubfx r3, r3, #0, #9 8007ab2: ee07 3a90 vmov s15, r3 8007ab6: eef8 6a67 vcvt.f32.u32 s13, s15 8007aba: ed97 6a03 vldr s12, [r7, #12] 8007abe: eddf 5a67 vldr s11, [pc, #412] @ 8007c5c 8007ac2: eec6 7a25 vdiv.f32 s15, s12, s11 8007ac6: ee76 7aa7 vadd.f32 s15, s13, s15 8007aca: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007ace: ee77 7aa6 vadd.f32 s15, s15, s13 8007ad2: ee67 7a27 vmul.f32 s15, s14, s15 8007ad6: edc7 7a07 vstr s15, [r7, #28] break; 8007ada: e065 b.n 8007ba8 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8007adc: 697b ldr r3, [r7, #20] 8007ade: ee07 3a90 vmov s15, r3 8007ae2: eef8 7a67 vcvt.f32.u32 s15, s15 8007ae6: eddf 6a5f vldr s13, [pc, #380] @ 8007c64 8007aea: ee86 7aa7 vdiv.f32 s14, s13, s15 8007aee: 4b59 ldr r3, [pc, #356] @ (8007c54 ) 8007af0: 6b9b ldr r3, [r3, #56] @ 0x38 8007af2: f3c3 0308 ubfx r3, r3, #0, #9 8007af6: ee07 3a90 vmov s15, r3 8007afa: eef8 6a67 vcvt.f32.u32 s13, s15 8007afe: ed97 6a03 vldr s12, [r7, #12] 8007b02: eddf 5a56 vldr s11, [pc, #344] @ 8007c5c 8007b06: eec6 7a25 vdiv.f32 s15, s12, s11 8007b0a: ee76 7aa7 vadd.f32 s15, s13, s15 8007b0e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007b12: ee77 7aa6 vadd.f32 s15, s15, s13 8007b16: ee67 7a27 vmul.f32 s15, s14, s15 8007b1a: edc7 7a07 vstr s15, [r7, #28] break; 8007b1e: e043 b.n 8007ba8 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8007b20: 697b ldr r3, [r7, #20] 8007b22: ee07 3a90 vmov s15, r3 8007b26: eef8 7a67 vcvt.f32.u32 s15, s15 8007b2a: eddf 6a4f vldr s13, [pc, #316] @ 8007c68 8007b2e: ee86 7aa7 vdiv.f32 s14, s13, s15 8007b32: 4b48 ldr r3, [pc, #288] @ (8007c54 ) 8007b34: 6b9b ldr r3, [r3, #56] @ 0x38 8007b36: f3c3 0308 ubfx r3, r3, #0, #9 8007b3a: ee07 3a90 vmov s15, r3 8007b3e: eef8 6a67 vcvt.f32.u32 s13, s15 8007b42: ed97 6a03 vldr s12, [r7, #12] 8007b46: eddf 5a45 vldr s11, [pc, #276] @ 8007c5c 8007b4a: eec6 7a25 vdiv.f32 s15, s12, s11 8007b4e: ee76 7aa7 vadd.f32 s15, s13, s15 8007b52: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007b56: ee77 7aa6 vadd.f32 s15, s15, s13 8007b5a: ee67 7a27 vmul.f32 s15, s14, s15 8007b5e: edc7 7a07 vstr s15, [r7, #28] break; 8007b62: e021 b.n 8007ba8 default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 8007b64: 697b ldr r3, [r7, #20] 8007b66: ee07 3a90 vmov s15, r3 8007b6a: eef8 7a67 vcvt.f32.u32 s15, s15 8007b6e: eddf 6a3d vldr s13, [pc, #244] @ 8007c64 8007b72: ee86 7aa7 vdiv.f32 s14, s13, s15 8007b76: 4b37 ldr r3, [pc, #220] @ (8007c54 ) 8007b78: 6b9b ldr r3, [r3, #56] @ 0x38 8007b7a: f3c3 0308 ubfx r3, r3, #0, #9 8007b7e: ee07 3a90 vmov s15, r3 8007b82: eef8 6a67 vcvt.f32.u32 s13, s15 8007b86: ed97 6a03 vldr s12, [r7, #12] 8007b8a: eddf 5a34 vldr s11, [pc, #208] @ 8007c5c 8007b8e: eec6 7a25 vdiv.f32 s15, s12, s11 8007b92: ee76 7aa7 vadd.f32 s15, s13, s15 8007b96: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007b9a: ee77 7aa6 vadd.f32 s15, s15, s13 8007b9e: ee67 7a27 vmul.f32 s15, s14, s15 8007ba2: edc7 7a07 vstr s15, [r7, #28] break; 8007ba6: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 8007ba8: 4b2a ldr r3, [pc, #168] @ (8007c54 ) 8007baa: 6b9b ldr r3, [r3, #56] @ 0x38 8007bac: 0a5b lsrs r3, r3, #9 8007bae: f003 037f and.w r3, r3, #127 @ 0x7f 8007bb2: ee07 3a90 vmov s15, r3 8007bb6: eef8 7a67 vcvt.f32.u32 s15, s15 8007bba: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8007bbe: ee37 7a87 vadd.f32 s14, s15, s14 8007bc2: edd7 6a07 vldr s13, [r7, #28] 8007bc6: eec6 7a87 vdiv.f32 s15, s13, s14 8007bca: eefc 7ae7 vcvt.u32.f32 s15, s15 8007bce: ee17 2a90 vmov r2, s15 8007bd2: 687b ldr r3, [r7, #4] 8007bd4: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 8007bd6: 4b1f ldr r3, [pc, #124] @ (8007c54 ) 8007bd8: 6b9b ldr r3, [r3, #56] @ 0x38 8007bda: 0c1b lsrs r3, r3, #16 8007bdc: f003 037f and.w r3, r3, #127 @ 0x7f 8007be0: ee07 3a90 vmov s15, r3 8007be4: eef8 7a67 vcvt.f32.u32 s15, s15 8007be8: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8007bec: ee37 7a87 vadd.f32 s14, s15, s14 8007bf0: edd7 6a07 vldr s13, [r7, #28] 8007bf4: eec6 7a87 vdiv.f32 s15, s13, s14 8007bf8: eefc 7ae7 vcvt.u32.f32 s15, s15 8007bfc: ee17 2a90 vmov r2, s15 8007c00: 687b ldr r3, [r7, #4] 8007c02: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 8007c04: 4b13 ldr r3, [pc, #76] @ (8007c54 ) 8007c06: 6b9b ldr r3, [r3, #56] @ 0x38 8007c08: 0e1b lsrs r3, r3, #24 8007c0a: f003 037f and.w r3, r3, #127 @ 0x7f 8007c0e: ee07 3a90 vmov s15, r3 8007c12: eef8 7a67 vcvt.f32.u32 s15, s15 8007c16: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8007c1a: ee37 7a87 vadd.f32 s14, s15, s14 8007c1e: edd7 6a07 vldr s13, [r7, #28] 8007c22: eec6 7a87 vdiv.f32 s15, s13, s14 8007c26: eefc 7ae7 vcvt.u32.f32 s15, s15 8007c2a: ee17 2a90 vmov r2, s15 8007c2e: 687b ldr r3, [r7, #4] 8007c30: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 8007c32: e008 b.n 8007c46 PLL2_Clocks->PLL2_P_Frequency = 0U; 8007c34: 687b ldr r3, [r7, #4] 8007c36: 2200 movs r2, #0 8007c38: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 8007c3a: 687b ldr r3, [r7, #4] 8007c3c: 2200 movs r2, #0 8007c3e: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 8007c40: 687b ldr r3, [r7, #4] 8007c42: 2200 movs r2, #0 8007c44: 609a str r2, [r3, #8] } 8007c46: bf00 nop 8007c48: 3724 adds r7, #36 @ 0x24 8007c4a: 46bd mov sp, r7 8007c4c: f85d 7b04 ldr.w r7, [sp], #4 8007c50: 4770 bx lr 8007c52: bf00 nop 8007c54: 58024400 .word 0x58024400 8007c58: 03d09000 .word 0x03d09000 8007c5c: 46000000 .word 0x46000000 8007c60: 4c742400 .word 0x4c742400 8007c64: 4a742400 .word 0x4a742400 8007c68: 4bbebc20 .word 0x4bbebc20 08007c6c : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 8007c6c: b480 push {r7} 8007c6e: b089 sub sp, #36 @ 0x24 8007c70: af00 add r7, sp, #0 8007c72: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 8007c74: 4ba1 ldr r3, [pc, #644] @ (8007efc ) 8007c76: 6a9b ldr r3, [r3, #40] @ 0x28 8007c78: f003 0303 and.w r3, r3, #3 8007c7c: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 8007c7e: 4b9f ldr r3, [pc, #636] @ (8007efc ) 8007c80: 6a9b ldr r3, [r3, #40] @ 0x28 8007c82: 0d1b lsrs r3, r3, #20 8007c84: f003 033f and.w r3, r3, #63 @ 0x3f 8007c88: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 8007c8a: 4b9c ldr r3, [pc, #624] @ (8007efc ) 8007c8c: 6adb ldr r3, [r3, #44] @ 0x2c 8007c8e: 0a1b lsrs r3, r3, #8 8007c90: f003 0301 and.w r3, r3, #1 8007c94: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 8007c96: 4b99 ldr r3, [pc, #612] @ (8007efc ) 8007c98: 6c5b ldr r3, [r3, #68] @ 0x44 8007c9a: 08db lsrs r3, r3, #3 8007c9c: f3c3 030c ubfx r3, r3, #0, #13 8007ca0: 693a ldr r2, [r7, #16] 8007ca2: fb02 f303 mul.w r3, r2, r3 8007ca6: ee07 3a90 vmov s15, r3 8007caa: eef8 7a67 vcvt.f32.u32 s15, s15 8007cae: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 8007cb2: 697b ldr r3, [r7, #20] 8007cb4: 2b00 cmp r3, #0 8007cb6: f000 8111 beq.w 8007edc { switch (pllsource) 8007cba: 69bb ldr r3, [r7, #24] 8007cbc: 2b02 cmp r3, #2 8007cbe: f000 8083 beq.w 8007dc8 8007cc2: 69bb ldr r3, [r7, #24] 8007cc4: 2b02 cmp r3, #2 8007cc6: f200 80a1 bhi.w 8007e0c 8007cca: 69bb ldr r3, [r7, #24] 8007ccc: 2b00 cmp r3, #0 8007cce: d003 beq.n 8007cd8 8007cd0: 69bb ldr r3, [r7, #24] 8007cd2: 2b01 cmp r3, #1 8007cd4: d056 beq.n 8007d84 8007cd6: e099 b.n 8007e0c { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8007cd8: 4b88 ldr r3, [pc, #544] @ (8007efc ) 8007cda: 681b ldr r3, [r3, #0] 8007cdc: f003 0320 and.w r3, r3, #32 8007ce0: 2b00 cmp r3, #0 8007ce2: d02d beq.n 8007d40 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 8007ce4: 4b85 ldr r3, [pc, #532] @ (8007efc ) 8007ce6: 681b ldr r3, [r3, #0] 8007ce8: 08db lsrs r3, r3, #3 8007cea: f003 0303 and.w r3, r3, #3 8007cee: 4a84 ldr r2, [pc, #528] @ (8007f00 ) 8007cf0: fa22 f303 lsr.w r3, r2, r3 8007cf4: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8007cf6: 68bb ldr r3, [r7, #8] 8007cf8: ee07 3a90 vmov s15, r3 8007cfc: eef8 6a67 vcvt.f32.u32 s13, s15 8007d00: 697b ldr r3, [r7, #20] 8007d02: ee07 3a90 vmov s15, r3 8007d06: eef8 7a67 vcvt.f32.u32 s15, s15 8007d0a: ee86 7aa7 vdiv.f32 s14, s13, s15 8007d0e: 4b7b ldr r3, [pc, #492] @ (8007efc ) 8007d10: 6c1b ldr r3, [r3, #64] @ 0x40 8007d12: f3c3 0308 ubfx r3, r3, #0, #9 8007d16: ee07 3a90 vmov s15, r3 8007d1a: eef8 6a67 vcvt.f32.u32 s13, s15 8007d1e: ed97 6a03 vldr s12, [r7, #12] 8007d22: eddf 5a78 vldr s11, [pc, #480] @ 8007f04 8007d26: eec6 7a25 vdiv.f32 s15, s12, s11 8007d2a: ee76 7aa7 vadd.f32 s15, s13, s15 8007d2e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007d32: ee77 7aa6 vadd.f32 s15, s15, s13 8007d36: ee67 7a27 vmul.f32 s15, s14, s15 8007d3a: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 8007d3e: e087 b.n 8007e50 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8007d40: 697b ldr r3, [r7, #20] 8007d42: ee07 3a90 vmov s15, r3 8007d46: eef8 7a67 vcvt.f32.u32 s15, s15 8007d4a: eddf 6a6f vldr s13, [pc, #444] @ 8007f08 8007d4e: ee86 7aa7 vdiv.f32 s14, s13, s15 8007d52: 4b6a ldr r3, [pc, #424] @ (8007efc ) 8007d54: 6c1b ldr r3, [r3, #64] @ 0x40 8007d56: f3c3 0308 ubfx r3, r3, #0, #9 8007d5a: ee07 3a90 vmov s15, r3 8007d5e: eef8 6a67 vcvt.f32.u32 s13, s15 8007d62: ed97 6a03 vldr s12, [r7, #12] 8007d66: eddf 5a67 vldr s11, [pc, #412] @ 8007f04 8007d6a: eec6 7a25 vdiv.f32 s15, s12, s11 8007d6e: ee76 7aa7 vadd.f32 s15, s13, s15 8007d72: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007d76: ee77 7aa6 vadd.f32 s15, s15, s13 8007d7a: ee67 7a27 vmul.f32 s15, s14, s15 8007d7e: edc7 7a07 vstr s15, [r7, #28] break; 8007d82: e065 b.n 8007e50 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8007d84: 697b ldr r3, [r7, #20] 8007d86: ee07 3a90 vmov s15, r3 8007d8a: eef8 7a67 vcvt.f32.u32 s15, s15 8007d8e: eddf 6a5f vldr s13, [pc, #380] @ 8007f0c 8007d92: ee86 7aa7 vdiv.f32 s14, s13, s15 8007d96: 4b59 ldr r3, [pc, #356] @ (8007efc ) 8007d98: 6c1b ldr r3, [r3, #64] @ 0x40 8007d9a: f3c3 0308 ubfx r3, r3, #0, #9 8007d9e: ee07 3a90 vmov s15, r3 8007da2: eef8 6a67 vcvt.f32.u32 s13, s15 8007da6: ed97 6a03 vldr s12, [r7, #12] 8007daa: eddf 5a56 vldr s11, [pc, #344] @ 8007f04 8007dae: eec6 7a25 vdiv.f32 s15, s12, s11 8007db2: ee76 7aa7 vadd.f32 s15, s13, s15 8007db6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007dba: ee77 7aa6 vadd.f32 s15, s15, s13 8007dbe: ee67 7a27 vmul.f32 s15, s14, s15 8007dc2: edc7 7a07 vstr s15, [r7, #28] break; 8007dc6: e043 b.n 8007e50 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8007dc8: 697b ldr r3, [r7, #20] 8007dca: ee07 3a90 vmov s15, r3 8007dce: eef8 7a67 vcvt.f32.u32 s15, s15 8007dd2: eddf 6a4f vldr s13, [pc, #316] @ 8007f10 8007dd6: ee86 7aa7 vdiv.f32 s14, s13, s15 8007dda: 4b48 ldr r3, [pc, #288] @ (8007efc ) 8007ddc: 6c1b ldr r3, [r3, #64] @ 0x40 8007dde: f3c3 0308 ubfx r3, r3, #0, #9 8007de2: ee07 3a90 vmov s15, r3 8007de6: eef8 6a67 vcvt.f32.u32 s13, s15 8007dea: ed97 6a03 vldr s12, [r7, #12] 8007dee: eddf 5a45 vldr s11, [pc, #276] @ 8007f04 8007df2: eec6 7a25 vdiv.f32 s15, s12, s11 8007df6: ee76 7aa7 vadd.f32 s15, s13, s15 8007dfa: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007dfe: ee77 7aa6 vadd.f32 s15, s15, s13 8007e02: ee67 7a27 vmul.f32 s15, s14, s15 8007e06: edc7 7a07 vstr s15, [r7, #28] break; 8007e0a: e021 b.n 8007e50 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 8007e0c: 697b ldr r3, [r7, #20] 8007e0e: ee07 3a90 vmov s15, r3 8007e12: eef8 7a67 vcvt.f32.u32 s15, s15 8007e16: eddf 6a3d vldr s13, [pc, #244] @ 8007f0c 8007e1a: ee86 7aa7 vdiv.f32 s14, s13, s15 8007e1e: 4b37 ldr r3, [pc, #220] @ (8007efc ) 8007e20: 6c1b ldr r3, [r3, #64] @ 0x40 8007e22: f3c3 0308 ubfx r3, r3, #0, #9 8007e26: ee07 3a90 vmov s15, r3 8007e2a: eef8 6a67 vcvt.f32.u32 s13, s15 8007e2e: ed97 6a03 vldr s12, [r7, #12] 8007e32: eddf 5a34 vldr s11, [pc, #208] @ 8007f04 8007e36: eec6 7a25 vdiv.f32 s15, s12, s11 8007e3a: ee76 7aa7 vadd.f32 s15, s13, s15 8007e3e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 8007e42: ee77 7aa6 vadd.f32 s15, s15, s13 8007e46: ee67 7a27 vmul.f32 s15, s14, s15 8007e4a: edc7 7a07 vstr s15, [r7, #28] break; 8007e4e: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 8007e50: 4b2a ldr r3, [pc, #168] @ (8007efc ) 8007e52: 6c1b ldr r3, [r3, #64] @ 0x40 8007e54: 0a5b lsrs r3, r3, #9 8007e56: f003 037f and.w r3, r3, #127 @ 0x7f 8007e5a: ee07 3a90 vmov s15, r3 8007e5e: eef8 7a67 vcvt.f32.u32 s15, s15 8007e62: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8007e66: ee37 7a87 vadd.f32 s14, s15, s14 8007e6a: edd7 6a07 vldr s13, [r7, #28] 8007e6e: eec6 7a87 vdiv.f32 s15, s13, s14 8007e72: eefc 7ae7 vcvt.u32.f32 s15, s15 8007e76: ee17 2a90 vmov r2, s15 8007e7a: 687b ldr r3, [r7, #4] 8007e7c: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 8007e7e: 4b1f ldr r3, [pc, #124] @ (8007efc ) 8007e80: 6c1b ldr r3, [r3, #64] @ 0x40 8007e82: 0c1b lsrs r3, r3, #16 8007e84: f003 037f and.w r3, r3, #127 @ 0x7f 8007e88: ee07 3a90 vmov s15, r3 8007e8c: eef8 7a67 vcvt.f32.u32 s15, s15 8007e90: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8007e94: ee37 7a87 vadd.f32 s14, s15, s14 8007e98: edd7 6a07 vldr s13, [r7, #28] 8007e9c: eec6 7a87 vdiv.f32 s15, s13, s14 8007ea0: eefc 7ae7 vcvt.u32.f32 s15, s15 8007ea4: ee17 2a90 vmov r2, s15 8007ea8: 687b ldr r3, [r7, #4] 8007eaa: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 8007eac: 4b13 ldr r3, [pc, #76] @ (8007efc ) 8007eae: 6c1b ldr r3, [r3, #64] @ 0x40 8007eb0: 0e1b lsrs r3, r3, #24 8007eb2: f003 037f and.w r3, r3, #127 @ 0x7f 8007eb6: ee07 3a90 vmov s15, r3 8007eba: eef8 7a67 vcvt.f32.u32 s15, s15 8007ebe: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 8007ec2: ee37 7a87 vadd.f32 s14, s15, s14 8007ec6: edd7 6a07 vldr s13, [r7, #28] 8007eca: eec6 7a87 vdiv.f32 s15, s13, s14 8007ece: eefc 7ae7 vcvt.u32.f32 s15, s15 8007ed2: ee17 2a90 vmov r2, s15 8007ed6: 687b ldr r3, [r7, #4] 8007ed8: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 8007eda: e008 b.n 8007eee PLL3_Clocks->PLL3_P_Frequency = 0U; 8007edc: 687b ldr r3, [r7, #4] 8007ede: 2200 movs r2, #0 8007ee0: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 8007ee2: 687b ldr r3, [r7, #4] 8007ee4: 2200 movs r2, #0 8007ee6: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 8007ee8: 687b ldr r3, [r7, #4] 8007eea: 2200 movs r2, #0 8007eec: 609a str r2, [r3, #8] } 8007eee: bf00 nop 8007ef0: 3724 adds r7, #36 @ 0x24 8007ef2: 46bd mov sp, r7 8007ef4: f85d 7b04 ldr.w r7, [sp], #4 8007ef8: 4770 bx lr 8007efa: bf00 nop 8007efc: 58024400 .word 0x58024400 8007f00: 03d09000 .word 0x03d09000 8007f04: 46000000 .word 0x46000000 8007f08: 4c742400 .word 0x4c742400 8007f0c: 4a742400 .word 0x4a742400 8007f10: 4bbebc20 .word 0x4bbebc20 08007f14 : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 8007f14: b580 push {r7, lr} 8007f16: b084 sub sp, #16 8007f18: af00 add r7, sp, #0 8007f1a: 6078 str r0, [r7, #4] 8007f1c: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8007f1e: 2300 movs r3, #0 8007f20: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8007f22: 4b53 ldr r3, [pc, #332] @ (8008070 ) 8007f24: 6a9b ldr r3, [r3, #40] @ 0x28 8007f26: f003 0303 and.w r3, r3, #3 8007f2a: 2b03 cmp r3, #3 8007f2c: d101 bne.n 8007f32 { return HAL_ERROR; 8007f2e: 2301 movs r3, #1 8007f30: e099 b.n 8008066 else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 8007f32: 4b4f ldr r3, [pc, #316] @ (8008070 ) 8007f34: 681b ldr r3, [r3, #0] 8007f36: 4a4e ldr r2, [pc, #312] @ (8008070 ) 8007f38: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8007f3c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8007f3e: f7fa fb8f bl 8002660 8007f42: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 8007f44: e008 b.n 8007f58 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8007f46: f7fa fb8b bl 8002660 8007f4a: 4602 mov r2, r0 8007f4c: 68bb ldr r3, [r7, #8] 8007f4e: 1ad3 subs r3, r2, r3 8007f50: 2b02 cmp r3, #2 8007f52: d901 bls.n 8007f58 { return HAL_TIMEOUT; 8007f54: 2303 movs r3, #3 8007f56: e086 b.n 8008066 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 8007f58: 4b45 ldr r3, [pc, #276] @ (8008070 ) 8007f5a: 681b ldr r3, [r3, #0] 8007f5c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8007f60: 2b00 cmp r3, #0 8007f62: d1f0 bne.n 8007f46 } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 8007f64: 4b42 ldr r3, [pc, #264] @ (8008070 ) 8007f66: 6a9b ldr r3, [r3, #40] @ 0x28 8007f68: f423 327c bic.w r2, r3, #258048 @ 0x3f000 8007f6c: 687b ldr r3, [r7, #4] 8007f6e: 681b ldr r3, [r3, #0] 8007f70: 031b lsls r3, r3, #12 8007f72: 493f ldr r1, [pc, #252] @ (8008070 ) 8007f74: 4313 orrs r3, r2 8007f76: 628b str r3, [r1, #40] @ 0x28 8007f78: 687b ldr r3, [r7, #4] 8007f7a: 685b ldr r3, [r3, #4] 8007f7c: 3b01 subs r3, #1 8007f7e: f3c3 0208 ubfx r2, r3, #0, #9 8007f82: 687b ldr r3, [r7, #4] 8007f84: 689b ldr r3, [r3, #8] 8007f86: 3b01 subs r3, #1 8007f88: 025b lsls r3, r3, #9 8007f8a: b29b uxth r3, r3 8007f8c: 431a orrs r2, r3 8007f8e: 687b ldr r3, [r7, #4] 8007f90: 68db ldr r3, [r3, #12] 8007f92: 3b01 subs r3, #1 8007f94: 041b lsls r3, r3, #16 8007f96: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 8007f9a: 431a orrs r2, r3 8007f9c: 687b ldr r3, [r7, #4] 8007f9e: 691b ldr r3, [r3, #16] 8007fa0: 3b01 subs r3, #1 8007fa2: 061b lsls r3, r3, #24 8007fa4: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 8007fa8: 4931 ldr r1, [pc, #196] @ (8008070 ) 8007faa: 4313 orrs r3, r2 8007fac: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 8007fae: 4b30 ldr r3, [pc, #192] @ (8008070 ) 8007fb0: 6adb ldr r3, [r3, #44] @ 0x2c 8007fb2: f023 02c0 bic.w r2, r3, #192 @ 0xc0 8007fb6: 687b ldr r3, [r7, #4] 8007fb8: 695b ldr r3, [r3, #20] 8007fba: 492d ldr r1, [pc, #180] @ (8008070 ) 8007fbc: 4313 orrs r3, r2 8007fbe: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 8007fc0: 4b2b ldr r3, [pc, #172] @ (8008070 ) 8007fc2: 6adb ldr r3, [r3, #44] @ 0x2c 8007fc4: f023 0220 bic.w r2, r3, #32 8007fc8: 687b ldr r3, [r7, #4] 8007fca: 699b ldr r3, [r3, #24] 8007fcc: 4928 ldr r1, [pc, #160] @ (8008070 ) 8007fce: 4313 orrs r3, r2 8007fd0: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 8007fd2: 4b27 ldr r3, [pc, #156] @ (8008070 ) 8007fd4: 6adb ldr r3, [r3, #44] @ 0x2c 8007fd6: 4a26 ldr r2, [pc, #152] @ (8008070 ) 8007fd8: f023 0310 bic.w r3, r3, #16 8007fdc: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 8007fde: 4b24 ldr r3, [pc, #144] @ (8008070 ) 8007fe0: 6bda ldr r2, [r3, #60] @ 0x3c 8007fe2: 4b24 ldr r3, [pc, #144] @ (8008074 ) 8007fe4: 4013 ands r3, r2 8007fe6: 687a ldr r2, [r7, #4] 8007fe8: 69d2 ldr r2, [r2, #28] 8007fea: 00d2 lsls r2, r2, #3 8007fec: 4920 ldr r1, [pc, #128] @ (8008070 ) 8007fee: 4313 orrs r3, r2 8007ff0: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 8007ff2: 4b1f ldr r3, [pc, #124] @ (8008070 ) 8007ff4: 6adb ldr r3, [r3, #44] @ 0x2c 8007ff6: 4a1e ldr r2, [pc, #120] @ (8008070 ) 8007ff8: f043 0310 orr.w r3, r3, #16 8007ffc: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 8007ffe: 683b ldr r3, [r7, #0] 8008000: 2b00 cmp r3, #0 8008002: d106 bne.n 8008012 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 8008004: 4b1a ldr r3, [pc, #104] @ (8008070 ) 8008006: 6adb ldr r3, [r3, #44] @ 0x2c 8008008: 4a19 ldr r2, [pc, #100] @ (8008070 ) 800800a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800800e: 62d3 str r3, [r2, #44] @ 0x2c 8008010: e00f b.n 8008032 } else if (Divider == DIVIDER_Q_UPDATE) 8008012: 683b ldr r3, [r7, #0] 8008014: 2b01 cmp r3, #1 8008016: d106 bne.n 8008026 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 8008018: 4b15 ldr r3, [pc, #84] @ (8008070 ) 800801a: 6adb ldr r3, [r3, #44] @ 0x2c 800801c: 4a14 ldr r2, [pc, #80] @ (8008070 ) 800801e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8008022: 62d3 str r3, [r2, #44] @ 0x2c 8008024: e005 b.n 8008032 } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 8008026: 4b12 ldr r3, [pc, #72] @ (8008070 ) 8008028: 6adb ldr r3, [r3, #44] @ 0x2c 800802a: 4a11 ldr r2, [pc, #68] @ (8008070 ) 800802c: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 8008030: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 8008032: 4b0f ldr r3, [pc, #60] @ (8008070 ) 8008034: 681b ldr r3, [r3, #0] 8008036: 4a0e ldr r2, [pc, #56] @ (8008070 ) 8008038: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800803c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800803e: f7fa fb0f bl 8002660 8008042: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 8008044: e008 b.n 8008058 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 8008046: f7fa fb0b bl 8002660 800804a: 4602 mov r2, r0 800804c: 68bb ldr r3, [r7, #8] 800804e: 1ad3 subs r3, r2, r3 8008050: 2b02 cmp r3, #2 8008052: d901 bls.n 8008058 { return HAL_TIMEOUT; 8008054: 2303 movs r3, #3 8008056: e006 b.n 8008066 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 8008058: 4b05 ldr r3, [pc, #20] @ (8008070 ) 800805a: 681b ldr r3, [r3, #0] 800805c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8008060: 2b00 cmp r3, #0 8008062: d0f0 beq.n 8008046 } } return status; 8008064: 7bfb ldrb r3, [r7, #15] } 8008066: 4618 mov r0, r3 8008068: 3710 adds r7, #16 800806a: 46bd mov sp, r7 800806c: bd80 pop {r7, pc} 800806e: bf00 nop 8008070: 58024400 .word 0x58024400 8008074: ffff0007 .word 0xffff0007 08008078 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 8008078: b580 push {r7, lr} 800807a: b084 sub sp, #16 800807c: af00 add r7, sp, #0 800807e: 6078 str r0, [r7, #4] 8008080: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 8008082: 2300 movs r3, #0 8008084: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 8008086: 4b53 ldr r3, [pc, #332] @ (80081d4 ) 8008088: 6a9b ldr r3, [r3, #40] @ 0x28 800808a: f003 0303 and.w r3, r3, #3 800808e: 2b03 cmp r3, #3 8008090: d101 bne.n 8008096 { return HAL_ERROR; 8008092: 2301 movs r3, #1 8008094: e099 b.n 80081ca else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 8008096: 4b4f ldr r3, [pc, #316] @ (80081d4 ) 8008098: 681b ldr r3, [r3, #0] 800809a: 4a4e ldr r2, [pc, #312] @ (80081d4 ) 800809c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80080a0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80080a2: f7fa fadd bl 8002660 80080a6: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 80080a8: e008 b.n 80080bc { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 80080aa: f7fa fad9 bl 8002660 80080ae: 4602 mov r2, r0 80080b0: 68bb ldr r3, [r7, #8] 80080b2: 1ad3 subs r3, r2, r3 80080b4: 2b02 cmp r3, #2 80080b6: d901 bls.n 80080bc { return HAL_TIMEOUT; 80080b8: 2303 movs r3, #3 80080ba: e086 b.n 80081ca while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 80080bc: 4b45 ldr r3, [pc, #276] @ (80081d4 ) 80080be: 681b ldr r3, [r3, #0] 80080c0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80080c4: 2b00 cmp r3, #0 80080c6: d1f0 bne.n 80080aa } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 80080c8: 4b42 ldr r3, [pc, #264] @ (80081d4 ) 80080ca: 6a9b ldr r3, [r3, #40] @ 0x28 80080cc: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 80080d0: 687b ldr r3, [r7, #4] 80080d2: 681b ldr r3, [r3, #0] 80080d4: 051b lsls r3, r3, #20 80080d6: 493f ldr r1, [pc, #252] @ (80081d4 ) 80080d8: 4313 orrs r3, r2 80080da: 628b str r3, [r1, #40] @ 0x28 80080dc: 687b ldr r3, [r7, #4] 80080de: 685b ldr r3, [r3, #4] 80080e0: 3b01 subs r3, #1 80080e2: f3c3 0208 ubfx r2, r3, #0, #9 80080e6: 687b ldr r3, [r7, #4] 80080e8: 689b ldr r3, [r3, #8] 80080ea: 3b01 subs r3, #1 80080ec: 025b lsls r3, r3, #9 80080ee: b29b uxth r3, r3 80080f0: 431a orrs r2, r3 80080f2: 687b ldr r3, [r7, #4] 80080f4: 68db ldr r3, [r3, #12] 80080f6: 3b01 subs r3, #1 80080f8: 041b lsls r3, r3, #16 80080fa: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 80080fe: 431a orrs r2, r3 8008100: 687b ldr r3, [r7, #4] 8008102: 691b ldr r3, [r3, #16] 8008104: 3b01 subs r3, #1 8008106: 061b lsls r3, r3, #24 8008108: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800810c: 4931 ldr r1, [pc, #196] @ (80081d4 ) 800810e: 4313 orrs r3, r2 8008110: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 8008112: 4b30 ldr r3, [pc, #192] @ (80081d4 ) 8008114: 6adb ldr r3, [r3, #44] @ 0x2c 8008116: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800811a: 687b ldr r3, [r7, #4] 800811c: 695b ldr r3, [r3, #20] 800811e: 492d ldr r1, [pc, #180] @ (80081d4 ) 8008120: 4313 orrs r3, r2 8008122: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 8008124: 4b2b ldr r3, [pc, #172] @ (80081d4 ) 8008126: 6adb ldr r3, [r3, #44] @ 0x2c 8008128: f423 7200 bic.w r2, r3, #512 @ 0x200 800812c: 687b ldr r3, [r7, #4] 800812e: 699b ldr r3, [r3, #24] 8008130: 4928 ldr r1, [pc, #160] @ (80081d4 ) 8008132: 4313 orrs r3, r2 8008134: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 8008136: 4b27 ldr r3, [pc, #156] @ (80081d4 ) 8008138: 6adb ldr r3, [r3, #44] @ 0x2c 800813a: 4a26 ldr r2, [pc, #152] @ (80081d4 ) 800813c: f423 7380 bic.w r3, r3, #256 @ 0x100 8008140: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 8008142: 4b24 ldr r3, [pc, #144] @ (80081d4 ) 8008144: 6c5a ldr r2, [r3, #68] @ 0x44 8008146: 4b24 ldr r3, [pc, #144] @ (80081d8 ) 8008148: 4013 ands r3, r2 800814a: 687a ldr r2, [r7, #4] 800814c: 69d2 ldr r2, [r2, #28] 800814e: 00d2 lsls r2, r2, #3 8008150: 4920 ldr r1, [pc, #128] @ (80081d4 ) 8008152: 4313 orrs r3, r2 8008154: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 8008156: 4b1f ldr r3, [pc, #124] @ (80081d4 ) 8008158: 6adb ldr r3, [r3, #44] @ 0x2c 800815a: 4a1e ldr r2, [pc, #120] @ (80081d4 ) 800815c: f443 7380 orr.w r3, r3, #256 @ 0x100 8008160: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 8008162: 683b ldr r3, [r7, #0] 8008164: 2b00 cmp r3, #0 8008166: d106 bne.n 8008176 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 8008168: 4b1a ldr r3, [pc, #104] @ (80081d4 ) 800816a: 6adb ldr r3, [r3, #44] @ 0x2c 800816c: 4a19 ldr r2, [pc, #100] @ (80081d4 ) 800816e: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8008172: 62d3 str r3, [r2, #44] @ 0x2c 8008174: e00f b.n 8008196 } else if (Divider == DIVIDER_Q_UPDATE) 8008176: 683b ldr r3, [r7, #0] 8008178: 2b01 cmp r3, #1 800817a: d106 bne.n 800818a { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800817c: 4b15 ldr r3, [pc, #84] @ (80081d4 ) 800817e: 6adb ldr r3, [r3, #44] @ 0x2c 8008180: 4a14 ldr r2, [pc, #80] @ (80081d4 ) 8008182: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8008186: 62d3 str r3, [r2, #44] @ 0x2c 8008188: e005 b.n 8008196 } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800818a: 4b12 ldr r3, [pc, #72] @ (80081d4 ) 800818c: 6adb ldr r3, [r3, #44] @ 0x2c 800818e: 4a11 ldr r2, [pc, #68] @ (80081d4 ) 8008190: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8008194: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 8008196: 4b0f ldr r3, [pc, #60] @ (80081d4 ) 8008198: 681b ldr r3, [r3, #0] 800819a: 4a0e ldr r2, [pc, #56] @ (80081d4 ) 800819c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80081a0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80081a2: f7fa fa5d bl 8002660 80081a6: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 80081a8: e008 b.n 80081bc { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 80081aa: f7fa fa59 bl 8002660 80081ae: 4602 mov r2, r0 80081b0: 68bb ldr r3, [r7, #8] 80081b2: 1ad3 subs r3, r2, r3 80081b4: 2b02 cmp r3, #2 80081b6: d901 bls.n 80081bc { return HAL_TIMEOUT; 80081b8: 2303 movs r3, #3 80081ba: e006 b.n 80081ca while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 80081bc: 4b05 ldr r3, [pc, #20] @ (80081d4 ) 80081be: 681b ldr r3, [r3, #0] 80081c0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80081c4: 2b00 cmp r3, #0 80081c6: d0f0 beq.n 80081aa } } return status; 80081c8: 7bfb ldrb r3, [r7, #15] } 80081ca: 4618 mov r0, r3 80081cc: 3710 adds r7, #16 80081ce: 46bd mov sp, r7 80081d0: bd80 pop {r7, pc} 80081d2: bf00 nop 80081d4: 58024400 .word 0x58024400 80081d8: ffff0007 .word 0xffff0007 080081dc : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 80081dc: b580 push {r7, lr} 80081de: b084 sub sp, #16 80081e0: af00 add r7, sp, #0 80081e2: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 80081e4: 687b ldr r3, [r7, #4] 80081e6: 2b00 cmp r3, #0 80081e8: d101 bne.n 80081ee { return HAL_ERROR; 80081ea: 2301 movs r3, #1 80081ec: e054 b.n 8008298 /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 80081ee: 687b ldr r3, [r7, #4] 80081f0: 7a5b ldrb r3, [r3, #9] 80081f2: b2db uxtb r3, r3 80081f4: 2b00 cmp r3, #0 80081f6: d105 bne.n 8008204 { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 80081f8: 687b ldr r3, [r7, #4] 80081fa: 2200 movs r2, #0 80081fc: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 80081fe: 6878 ldr r0, [r7, #4] 8008200: f7f9 f960 bl 80014c4 } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 8008204: 687b ldr r3, [r7, #4] 8008206: 2202 movs r2, #2 8008208: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800820a: 687b ldr r3, [r7, #4] 800820c: 681b ldr r3, [r3, #0] 800820e: 681b ldr r3, [r3, #0] 8008210: f023 0120 bic.w r1, r3, #32 8008214: 687b ldr r3, [r7, #4] 8008216: 685a ldr r2, [r3, #4] 8008218: 687b ldr r3, [r7, #4] 800821a: 681b ldr r3, [r3, #0] 800821c: 430a orrs r2, r1 800821e: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 8008220: 687b ldr r3, [r7, #4] 8008222: 681b ldr r3, [r3, #0] 8008224: 681a ldr r2, [r3, #0] 8008226: 687b ldr r3, [r7, #4] 8008228: 681b ldr r3, [r3, #0] 800822a: f042 0204 orr.w r2, r2, #4 800822e: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 8008230: 687b ldr r3, [r7, #4] 8008232: 681b ldr r3, [r3, #0] 8008234: 685b ldr r3, [r3, #4] 8008236: f003 0340 and.w r3, r3, #64 @ 0x40 800823a: 2b40 cmp r3, #64 @ 0x40 800823c: d104 bne.n 8008248 { hrng->State = HAL_RNG_STATE_ERROR; 800823e: 687b ldr r3, [r7, #4] 8008240: 2204 movs r2, #4 8008242: 725a strb r2, [r3, #9] return HAL_ERROR; 8008244: 2301 movs r3, #1 8008246: e027 b.n 8008298 } /* Get tick */ tickstart = HAL_GetTick(); 8008248: f7fa fa0a bl 8002660 800824c: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800824e: e015 b.n 800827c { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 8008250: f7fa fa06 bl 8002660 8008254: 4602 mov r2, r0 8008256: 68fb ldr r3, [r7, #12] 8008258: 1ad3 subs r3, r2, r3 800825a: 2b02 cmp r3, #2 800825c: d90e bls.n 800827c { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800825e: 687b ldr r3, [r7, #4] 8008260: 681b ldr r3, [r3, #0] 8008262: 685b ldr r3, [r3, #4] 8008264: f003 0304 and.w r3, r3, #4 8008268: 2b04 cmp r3, #4 800826a: d107 bne.n 800827c { hrng->State = HAL_RNG_STATE_ERROR; 800826c: 687b ldr r3, [r7, #4] 800826e: 2204 movs r2, #4 8008270: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 8008272: 687b ldr r3, [r7, #4] 8008274: 2202 movs r2, #2 8008276: 60da str r2, [r3, #12] return HAL_ERROR; 8008278: 2301 movs r3, #1 800827a: e00d b.n 8008298 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800827c: 687b ldr r3, [r7, #4] 800827e: 681b ldr r3, [r3, #0] 8008280: 685b ldr r3, [r3, #4] 8008282: f003 0304 and.w r3, r3, #4 8008286: 2b04 cmp r3, #4 8008288: d0e2 beq.n 8008250 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800828a: 687b ldr r3, [r7, #4] 800828c: 2201 movs r2, #1 800828e: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 8008290: 687b ldr r3, [r7, #4] 8008292: 2200 movs r2, #0 8008294: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 8008296: 2300 movs r3, #0 } 8008298: 4618 mov r0, r3 800829a: 3710 adds r7, #16 800829c: 46bd mov sp, r7 800829e: bd80 pop {r7, pc} 080082a0 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 80082a0: b580 push {r7, lr} 80082a2: b082 sub sp, #8 80082a4: af00 add r7, sp, #0 80082a6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80082a8: 687b ldr r3, [r7, #4] 80082aa: 2b00 cmp r3, #0 80082ac: d101 bne.n 80082b2 { return HAL_ERROR; 80082ae: 2301 movs r3, #1 80082b0: e049 b.n 8008346 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80082b2: 687b ldr r3, [r7, #4] 80082b4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80082b8: b2db uxtb r3, r3 80082ba: 2b00 cmp r3, #0 80082bc: d106 bne.n 80082cc { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80082be: 687b ldr r3, [r7, #4] 80082c0: 2200 movs r2, #0 80082c2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 80082c6: 6878 ldr r0, [r7, #4] 80082c8: f000 f841 bl 800834e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80082cc: 687b ldr r3, [r7, #4] 80082ce: 2202 movs r2, #2 80082d0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80082d4: 687b ldr r3, [r7, #4] 80082d6: 681a ldr r2, [r3, #0] 80082d8: 687b ldr r3, [r7, #4] 80082da: 3304 adds r3, #4 80082dc: 4619 mov r1, r3 80082de: 4610 mov r0, r2 80082e0: f000 f9e8 bl 80086b4 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 80082e4: 687b ldr r3, [r7, #4] 80082e6: 2201 movs r2, #1 80082e8: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80082ec: 687b ldr r3, [r7, #4] 80082ee: 2201 movs r2, #1 80082f0: f883 203e strb.w r2, [r3, #62] @ 0x3e 80082f4: 687b ldr r3, [r7, #4] 80082f6: 2201 movs r2, #1 80082f8: f883 203f strb.w r2, [r3, #63] @ 0x3f 80082fc: 687b ldr r3, [r7, #4] 80082fe: 2201 movs r2, #1 8008300: f883 2040 strb.w r2, [r3, #64] @ 0x40 8008304: 687b ldr r3, [r7, #4] 8008306: 2201 movs r2, #1 8008308: f883 2041 strb.w r2, [r3, #65] @ 0x41 800830c: 687b ldr r3, [r7, #4] 800830e: 2201 movs r2, #1 8008310: f883 2042 strb.w r2, [r3, #66] @ 0x42 8008314: 687b ldr r3, [r7, #4] 8008316: 2201 movs r2, #1 8008318: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800831c: 687b ldr r3, [r7, #4] 800831e: 2201 movs r2, #1 8008320: f883 2044 strb.w r2, [r3, #68] @ 0x44 8008324: 687b ldr r3, [r7, #4] 8008326: 2201 movs r2, #1 8008328: f883 2045 strb.w r2, [r3, #69] @ 0x45 800832c: 687b ldr r3, [r7, #4] 800832e: 2201 movs r2, #1 8008330: f883 2046 strb.w r2, [r3, #70] @ 0x46 8008334: 687b ldr r3, [r7, #4] 8008336: 2201 movs r2, #1 8008338: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800833c: 687b ldr r3, [r7, #4] 800833e: 2201 movs r2, #1 8008340: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8008344: 2300 movs r3, #0 } 8008346: 4618 mov r0, r3 8008348: 3708 adds r7, #8 800834a: 46bd mov sp, r7 800834c: bd80 pop {r7, pc} 0800834e : * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { 800834e: b480 push {r7} 8008350: b083 sub sp, #12 8008352: af00 add r7, sp, #0 8008354: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } 8008356: bf00 nop 8008358: 370c adds r7, #12 800835a: 46bd mov sp, r7 800835c: f85d 7b04 ldr.w r7, [sp], #4 8008360: 4770 bx lr ... 08008364 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8008364: b480 push {r7} 8008366: b085 sub sp, #20 8008368: af00 add r7, sp, #0 800836a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800836c: 687b ldr r3, [r7, #4] 800836e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8008372: b2db uxtb r3, r3 8008374: 2b01 cmp r3, #1 8008376: d001 beq.n 800837c { return HAL_ERROR; 8008378: 2301 movs r3, #1 800837a: e054 b.n 8008426 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800837c: 687b ldr r3, [r7, #4] 800837e: 2202 movs r2, #2 8008380: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8008384: 687b ldr r3, [r7, #4] 8008386: 681b ldr r3, [r3, #0] 8008388: 68da ldr r2, [r3, #12] 800838a: 687b ldr r3, [r7, #4] 800838c: 681b ldr r3, [r3, #0] 800838e: f042 0201 orr.w r2, r2, #1 8008392: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8008394: 687b ldr r3, [r7, #4] 8008396: 681b ldr r3, [r3, #0] 8008398: 4a26 ldr r2, [pc, #152] @ (8008434 ) 800839a: 4293 cmp r3, r2 800839c: d022 beq.n 80083e4 800839e: 687b ldr r3, [r7, #4] 80083a0: 681b ldr r3, [r3, #0] 80083a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80083a6: d01d beq.n 80083e4 80083a8: 687b ldr r3, [r7, #4] 80083aa: 681b ldr r3, [r3, #0] 80083ac: 4a22 ldr r2, [pc, #136] @ (8008438 ) 80083ae: 4293 cmp r3, r2 80083b0: d018 beq.n 80083e4 80083b2: 687b ldr r3, [r7, #4] 80083b4: 681b ldr r3, [r3, #0] 80083b6: 4a21 ldr r2, [pc, #132] @ (800843c ) 80083b8: 4293 cmp r3, r2 80083ba: d013 beq.n 80083e4 80083bc: 687b ldr r3, [r7, #4] 80083be: 681b ldr r3, [r3, #0] 80083c0: 4a1f ldr r2, [pc, #124] @ (8008440 ) 80083c2: 4293 cmp r3, r2 80083c4: d00e beq.n 80083e4 80083c6: 687b ldr r3, [r7, #4] 80083c8: 681b ldr r3, [r3, #0] 80083ca: 4a1e ldr r2, [pc, #120] @ (8008444 ) 80083cc: 4293 cmp r3, r2 80083ce: d009 beq.n 80083e4 80083d0: 687b ldr r3, [r7, #4] 80083d2: 681b ldr r3, [r3, #0] 80083d4: 4a1c ldr r2, [pc, #112] @ (8008448 ) 80083d6: 4293 cmp r3, r2 80083d8: d004 beq.n 80083e4 80083da: 687b ldr r3, [r7, #4] 80083dc: 681b ldr r3, [r3, #0] 80083de: 4a1b ldr r2, [pc, #108] @ (800844c ) 80083e0: 4293 cmp r3, r2 80083e2: d115 bne.n 8008410 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80083e4: 687b ldr r3, [r7, #4] 80083e6: 681b ldr r3, [r3, #0] 80083e8: 689a ldr r2, [r3, #8] 80083ea: 4b19 ldr r3, [pc, #100] @ (8008450 ) 80083ec: 4013 ands r3, r2 80083ee: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80083f0: 68fb ldr r3, [r7, #12] 80083f2: 2b06 cmp r3, #6 80083f4: d015 beq.n 8008422 80083f6: 68fb ldr r3, [r7, #12] 80083f8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80083fc: d011 beq.n 8008422 { __HAL_TIM_ENABLE(htim); 80083fe: 687b ldr r3, [r7, #4] 8008400: 681b ldr r3, [r3, #0] 8008402: 681a ldr r2, [r3, #0] 8008404: 687b ldr r3, [r7, #4] 8008406: 681b ldr r3, [r3, #0] 8008408: f042 0201 orr.w r2, r2, #1 800840c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800840e: e008 b.n 8008422 } } else { __HAL_TIM_ENABLE(htim); 8008410: 687b ldr r3, [r7, #4] 8008412: 681b ldr r3, [r3, #0] 8008414: 681a ldr r2, [r3, #0] 8008416: 687b ldr r3, [r7, #4] 8008418: 681b ldr r3, [r3, #0] 800841a: f042 0201 orr.w r2, r2, #1 800841e: 601a str r2, [r3, #0] 8008420: e000 b.n 8008424 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8008422: bf00 nop } /* Return function status */ return HAL_OK; 8008424: 2300 movs r3, #0 } 8008426: 4618 mov r0, r3 8008428: 3714 adds r7, #20 800842a: 46bd mov sp, r7 800842c: f85d 7b04 ldr.w r7, [sp], #4 8008430: 4770 bx lr 8008432: bf00 nop 8008434: 40010000 .word 0x40010000 8008438: 40000400 .word 0x40000400 800843c: 40000800 .word 0x40000800 8008440: 40000c00 .word 0x40000c00 8008444: 40010400 .word 0x40010400 8008448: 40001800 .word 0x40001800 800844c: 40014000 .word 0x40014000 8008450: 00010007 .word 0x00010007 08008454 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8008454: b580 push {r7, lr} 8008456: b084 sub sp, #16 8008458: af00 add r7, sp, #0 800845a: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800845c: 687b ldr r3, [r7, #4] 800845e: 681b ldr r3, [r3, #0] 8008460: 68db ldr r3, [r3, #12] 8008462: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8008464: 687b ldr r3, [r7, #4] 8008466: 681b ldr r3, [r3, #0] 8008468: 691b ldr r3, [r3, #16] 800846a: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800846c: 68bb ldr r3, [r7, #8] 800846e: f003 0302 and.w r3, r3, #2 8008472: 2b00 cmp r3, #0 8008474: d020 beq.n 80084b8 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8008476: 68fb ldr r3, [r7, #12] 8008478: f003 0302 and.w r3, r3, #2 800847c: 2b00 cmp r3, #0 800847e: d01b beq.n 80084b8 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8008480: 687b ldr r3, [r7, #4] 8008482: 681b ldr r3, [r3, #0] 8008484: f06f 0202 mvn.w r2, #2 8008488: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800848a: 687b ldr r3, [r7, #4] 800848c: 2201 movs r2, #1 800848e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8008490: 687b ldr r3, [r7, #4] 8008492: 681b ldr r3, [r3, #0] 8008494: 699b ldr r3, [r3, #24] 8008496: f003 0303 and.w r3, r3, #3 800849a: 2b00 cmp r3, #0 800849c: d003 beq.n 80084a6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800849e: 6878 ldr r0, [r7, #4] 80084a0: f000 f8e9 bl 8008676 80084a4: e005 b.n 80084b2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80084a6: 6878 ldr r0, [r7, #4] 80084a8: f000 f8db bl 8008662 HAL_TIM_PWM_PulseFinishedCallback(htim); 80084ac: 6878 ldr r0, [r7, #4] 80084ae: f000 f8ec bl 800868a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80084b2: 687b ldr r3, [r7, #4] 80084b4: 2200 movs r2, #0 80084b6: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 80084b8: 68bb ldr r3, [r7, #8] 80084ba: f003 0304 and.w r3, r3, #4 80084be: 2b00 cmp r3, #0 80084c0: d020 beq.n 8008504 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 80084c2: 68fb ldr r3, [r7, #12] 80084c4: f003 0304 and.w r3, r3, #4 80084c8: 2b00 cmp r3, #0 80084ca: d01b beq.n 8008504 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 80084cc: 687b ldr r3, [r7, #4] 80084ce: 681b ldr r3, [r3, #0] 80084d0: f06f 0204 mvn.w r2, #4 80084d4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80084d6: 687b ldr r3, [r7, #4] 80084d8: 2202 movs r2, #2 80084da: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80084dc: 687b ldr r3, [r7, #4] 80084de: 681b ldr r3, [r3, #0] 80084e0: 699b ldr r3, [r3, #24] 80084e2: f403 7340 and.w r3, r3, #768 @ 0x300 80084e6: 2b00 cmp r3, #0 80084e8: d003 beq.n 80084f2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80084ea: 6878 ldr r0, [r7, #4] 80084ec: f000 f8c3 bl 8008676 80084f0: e005 b.n 80084fe { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80084f2: 6878 ldr r0, [r7, #4] 80084f4: f000 f8b5 bl 8008662 HAL_TIM_PWM_PulseFinishedCallback(htim); 80084f8: 6878 ldr r0, [r7, #4] 80084fa: f000 f8c6 bl 800868a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80084fe: 687b ldr r3, [r7, #4] 8008500: 2200 movs r2, #0 8008502: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8008504: 68bb ldr r3, [r7, #8] 8008506: f003 0308 and.w r3, r3, #8 800850a: 2b00 cmp r3, #0 800850c: d020 beq.n 8008550 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800850e: 68fb ldr r3, [r7, #12] 8008510: f003 0308 and.w r3, r3, #8 8008514: 2b00 cmp r3, #0 8008516: d01b beq.n 8008550 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8008518: 687b ldr r3, [r7, #4] 800851a: 681b ldr r3, [r3, #0] 800851c: f06f 0208 mvn.w r2, #8 8008520: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8008522: 687b ldr r3, [r7, #4] 8008524: 2204 movs r2, #4 8008526: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8008528: 687b ldr r3, [r7, #4] 800852a: 681b ldr r3, [r3, #0] 800852c: 69db ldr r3, [r3, #28] 800852e: f003 0303 and.w r3, r3, #3 8008532: 2b00 cmp r3, #0 8008534: d003 beq.n 800853e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8008536: 6878 ldr r0, [r7, #4] 8008538: f000 f89d bl 8008676 800853c: e005 b.n 800854a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800853e: 6878 ldr r0, [r7, #4] 8008540: f000 f88f bl 8008662 HAL_TIM_PWM_PulseFinishedCallback(htim); 8008544: 6878 ldr r0, [r7, #4] 8008546: f000 f8a0 bl 800868a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800854a: 687b ldr r3, [r7, #4] 800854c: 2200 movs r2, #0 800854e: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8008550: 68bb ldr r3, [r7, #8] 8008552: f003 0310 and.w r3, r3, #16 8008556: 2b00 cmp r3, #0 8008558: d020 beq.n 800859c { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800855a: 68fb ldr r3, [r7, #12] 800855c: f003 0310 and.w r3, r3, #16 8008560: 2b00 cmp r3, #0 8008562: d01b beq.n 800859c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8008564: 687b ldr r3, [r7, #4] 8008566: 681b ldr r3, [r3, #0] 8008568: f06f 0210 mvn.w r2, #16 800856c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800856e: 687b ldr r3, [r7, #4] 8008570: 2208 movs r2, #8 8008572: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8008574: 687b ldr r3, [r7, #4] 8008576: 681b ldr r3, [r3, #0] 8008578: 69db ldr r3, [r3, #28] 800857a: f403 7340 and.w r3, r3, #768 @ 0x300 800857e: 2b00 cmp r3, #0 8008580: d003 beq.n 800858a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8008582: 6878 ldr r0, [r7, #4] 8008584: f000 f877 bl 8008676 8008588: e005 b.n 8008596 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800858a: 6878 ldr r0, [r7, #4] 800858c: f000 f869 bl 8008662 HAL_TIM_PWM_PulseFinishedCallback(htim); 8008590: 6878 ldr r0, [r7, #4] 8008592: f000 f87a bl 800868a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8008596: 687b ldr r3, [r7, #4] 8008598: 2200 movs r2, #0 800859a: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800859c: 68bb ldr r3, [r7, #8] 800859e: f003 0301 and.w r3, r3, #1 80085a2: 2b00 cmp r3, #0 80085a4: d00c beq.n 80085c0 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 80085a6: 68fb ldr r3, [r7, #12] 80085a8: f003 0301 and.w r3, r3, #1 80085ac: 2b00 cmp r3, #0 80085ae: d007 beq.n 80085c0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 80085b0: 687b ldr r3, [r7, #4] 80085b2: 681b ldr r3, [r3, #0] 80085b4: f06f 0201 mvn.w r2, #1 80085b8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80085ba: 6878 ldr r0, [r7, #4] 80085bc: f7f8 fb32 bl 8000c24 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 80085c0: 68bb ldr r3, [r7, #8] 80085c2: f003 0380 and.w r3, r3, #128 @ 0x80 80085c6: 2b00 cmp r3, #0 80085c8: d104 bne.n 80085d4 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 80085ca: 68bb ldr r3, [r7, #8] 80085cc: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 80085d0: 2b00 cmp r3, #0 80085d2: d00c beq.n 80085ee { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 80085d4: 68fb ldr r3, [r7, #12] 80085d6: f003 0380 and.w r3, r3, #128 @ 0x80 80085da: 2b00 cmp r3, #0 80085dc: d007 beq.n 80085ee { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 80085de: 687b ldr r3, [r7, #4] 80085e0: 681b ldr r3, [r3, #0] 80085e2: f46f 5202 mvn.w r2, #8320 @ 0x2080 80085e6: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80085e8: 6878 ldr r0, [r7, #4] 80085ea: f000 f913 bl 8008814 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 80085ee: 68bb ldr r3, [r7, #8] 80085f0: f403 7380 and.w r3, r3, #256 @ 0x100 80085f4: 2b00 cmp r3, #0 80085f6: d00c beq.n 8008612 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 80085f8: 68fb ldr r3, [r7, #12] 80085fa: f003 0380 and.w r3, r3, #128 @ 0x80 80085fe: 2b00 cmp r3, #0 8008600: d007 beq.n 8008612 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 8008602: 687b ldr r3, [r7, #4] 8008604: 681b ldr r3, [r3, #0] 8008606: f46f 7280 mvn.w r2, #256 @ 0x100 800860a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800860c: 6878 ldr r0, [r7, #4] 800860e: f000 f90b bl 8008828 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8008612: 68bb ldr r3, [r7, #8] 8008614: f003 0340 and.w r3, r3, #64 @ 0x40 8008618: 2b00 cmp r3, #0 800861a: d00c beq.n 8008636 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800861c: 68fb ldr r3, [r7, #12] 800861e: f003 0340 and.w r3, r3, #64 @ 0x40 8008622: 2b00 cmp r3, #0 8008624: d007 beq.n 8008636 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8008626: 687b ldr r3, [r7, #4] 8008628: 681b ldr r3, [r3, #0] 800862a: f06f 0240 mvn.w r2, #64 @ 0x40 800862e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8008630: 6878 ldr r0, [r7, #4] 8008632: f000 f834 bl 800869e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8008636: 68bb ldr r3, [r7, #8] 8008638: f003 0320 and.w r3, r3, #32 800863c: 2b00 cmp r3, #0 800863e: d00c beq.n 800865a { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8008640: 68fb ldr r3, [r7, #12] 8008642: f003 0320 and.w r3, r3, #32 8008646: 2b00 cmp r3, #0 8008648: d007 beq.n 800865a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800864a: 687b ldr r3, [r7, #4] 800864c: 681b ldr r3, [r3, #0] 800864e: f06f 0220 mvn.w r2, #32 8008652: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8008654: 6878 ldr r0, [r7, #4] 8008656: f000 f8d3 bl 8008800 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800865a: bf00 nop 800865c: 3710 adds r7, #16 800865e: 46bd mov sp, r7 8008660: bd80 pop {r7, pc} 08008662 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8008662: b480 push {r7} 8008664: b083 sub sp, #12 8008666: af00 add r7, sp, #0 8008668: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800866a: bf00 nop 800866c: 370c adds r7, #12 800866e: 46bd mov sp, r7 8008670: f85d 7b04 ldr.w r7, [sp], #4 8008674: 4770 bx lr 08008676 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8008676: b480 push {r7} 8008678: b083 sub sp, #12 800867a: af00 add r7, sp, #0 800867c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 800867e: bf00 nop 8008680: 370c adds r7, #12 8008682: 46bd mov sp, r7 8008684: f85d 7b04 ldr.w r7, [sp], #4 8008688: 4770 bx lr 0800868a : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800868a: b480 push {r7} 800868c: b083 sub sp, #12 800868e: af00 add r7, sp, #0 8008690: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8008692: bf00 nop 8008694: 370c adds r7, #12 8008696: 46bd mov sp, r7 8008698: f85d 7b04 ldr.w r7, [sp], #4 800869c: 4770 bx lr 0800869e : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800869e: b480 push {r7} 80086a0: b083 sub sp, #12 80086a2: af00 add r7, sp, #0 80086a4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80086a6: bf00 nop 80086a8: 370c adds r7, #12 80086aa: 46bd mov sp, r7 80086ac: f85d 7b04 ldr.w r7, [sp], #4 80086b0: 4770 bx lr ... 080086b4 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 80086b4: b480 push {r7} 80086b6: b085 sub sp, #20 80086b8: af00 add r7, sp, #0 80086ba: 6078 str r0, [r7, #4] 80086bc: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80086be: 687b ldr r3, [r7, #4] 80086c0: 681b ldr r3, [r3, #0] 80086c2: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80086c4: 687b ldr r3, [r7, #4] 80086c6: 4a46 ldr r2, [pc, #280] @ (80087e0 ) 80086c8: 4293 cmp r3, r2 80086ca: d013 beq.n 80086f4 80086cc: 687b ldr r3, [r7, #4] 80086ce: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80086d2: d00f beq.n 80086f4 80086d4: 687b ldr r3, [r7, #4] 80086d6: 4a43 ldr r2, [pc, #268] @ (80087e4 ) 80086d8: 4293 cmp r3, r2 80086da: d00b beq.n 80086f4 80086dc: 687b ldr r3, [r7, #4] 80086de: 4a42 ldr r2, [pc, #264] @ (80087e8 ) 80086e0: 4293 cmp r3, r2 80086e2: d007 beq.n 80086f4 80086e4: 687b ldr r3, [r7, #4] 80086e6: 4a41 ldr r2, [pc, #260] @ (80087ec ) 80086e8: 4293 cmp r3, r2 80086ea: d003 beq.n 80086f4 80086ec: 687b ldr r3, [r7, #4] 80086ee: 4a40 ldr r2, [pc, #256] @ (80087f0 ) 80086f0: 4293 cmp r3, r2 80086f2: d108 bne.n 8008706 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80086f4: 68fb ldr r3, [r7, #12] 80086f6: f023 0370 bic.w r3, r3, #112 @ 0x70 80086fa: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80086fc: 683b ldr r3, [r7, #0] 80086fe: 685b ldr r3, [r3, #4] 8008700: 68fa ldr r2, [r7, #12] 8008702: 4313 orrs r3, r2 8008704: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8008706: 687b ldr r3, [r7, #4] 8008708: 4a35 ldr r2, [pc, #212] @ (80087e0 ) 800870a: 4293 cmp r3, r2 800870c: d01f beq.n 800874e 800870e: 687b ldr r3, [r7, #4] 8008710: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8008714: d01b beq.n 800874e 8008716: 687b ldr r3, [r7, #4] 8008718: 4a32 ldr r2, [pc, #200] @ (80087e4 ) 800871a: 4293 cmp r3, r2 800871c: d017 beq.n 800874e 800871e: 687b ldr r3, [r7, #4] 8008720: 4a31 ldr r2, [pc, #196] @ (80087e8 ) 8008722: 4293 cmp r3, r2 8008724: d013 beq.n 800874e 8008726: 687b ldr r3, [r7, #4] 8008728: 4a30 ldr r2, [pc, #192] @ (80087ec ) 800872a: 4293 cmp r3, r2 800872c: d00f beq.n 800874e 800872e: 687b ldr r3, [r7, #4] 8008730: 4a2f ldr r2, [pc, #188] @ (80087f0 ) 8008732: 4293 cmp r3, r2 8008734: d00b beq.n 800874e 8008736: 687b ldr r3, [r7, #4] 8008738: 4a2e ldr r2, [pc, #184] @ (80087f4 ) 800873a: 4293 cmp r3, r2 800873c: d007 beq.n 800874e 800873e: 687b ldr r3, [r7, #4] 8008740: 4a2d ldr r2, [pc, #180] @ (80087f8 ) 8008742: 4293 cmp r3, r2 8008744: d003 beq.n 800874e 8008746: 687b ldr r3, [r7, #4] 8008748: 4a2c ldr r2, [pc, #176] @ (80087fc ) 800874a: 4293 cmp r3, r2 800874c: d108 bne.n 8008760 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800874e: 68fb ldr r3, [r7, #12] 8008750: f423 7340 bic.w r3, r3, #768 @ 0x300 8008754: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8008756: 683b ldr r3, [r7, #0] 8008758: 68db ldr r3, [r3, #12] 800875a: 68fa ldr r2, [r7, #12] 800875c: 4313 orrs r3, r2 800875e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8008760: 68fb ldr r3, [r7, #12] 8008762: f023 0280 bic.w r2, r3, #128 @ 0x80 8008766: 683b ldr r3, [r7, #0] 8008768: 695b ldr r3, [r3, #20] 800876a: 4313 orrs r3, r2 800876c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800876e: 687b ldr r3, [r7, #4] 8008770: 68fa ldr r2, [r7, #12] 8008772: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8008774: 683b ldr r3, [r7, #0] 8008776: 689a ldr r2, [r3, #8] 8008778: 687b ldr r3, [r7, #4] 800877a: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800877c: 683b ldr r3, [r7, #0] 800877e: 681a ldr r2, [r3, #0] 8008780: 687b ldr r3, [r7, #4] 8008782: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8008784: 687b ldr r3, [r7, #4] 8008786: 4a16 ldr r2, [pc, #88] @ (80087e0 ) 8008788: 4293 cmp r3, r2 800878a: d00f beq.n 80087ac 800878c: 687b ldr r3, [r7, #4] 800878e: 4a18 ldr r2, [pc, #96] @ (80087f0 ) 8008790: 4293 cmp r3, r2 8008792: d00b beq.n 80087ac 8008794: 687b ldr r3, [r7, #4] 8008796: 4a17 ldr r2, [pc, #92] @ (80087f4 ) 8008798: 4293 cmp r3, r2 800879a: d007 beq.n 80087ac 800879c: 687b ldr r3, [r7, #4] 800879e: 4a16 ldr r2, [pc, #88] @ (80087f8 ) 80087a0: 4293 cmp r3, r2 80087a2: d003 beq.n 80087ac 80087a4: 687b ldr r3, [r7, #4] 80087a6: 4a15 ldr r2, [pc, #84] @ (80087fc ) 80087a8: 4293 cmp r3, r2 80087aa: d103 bne.n 80087b4 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80087ac: 683b ldr r3, [r7, #0] 80087ae: 691a ldr r2, [r3, #16] 80087b0: 687b ldr r3, [r7, #4] 80087b2: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80087b4: 687b ldr r3, [r7, #4] 80087b6: 2201 movs r2, #1 80087b8: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 80087ba: 687b ldr r3, [r7, #4] 80087bc: 691b ldr r3, [r3, #16] 80087be: f003 0301 and.w r3, r3, #1 80087c2: 2b01 cmp r3, #1 80087c4: d105 bne.n 80087d2 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80087c6: 687b ldr r3, [r7, #4] 80087c8: 691b ldr r3, [r3, #16] 80087ca: f023 0201 bic.w r2, r3, #1 80087ce: 687b ldr r3, [r7, #4] 80087d0: 611a str r2, [r3, #16] } } 80087d2: bf00 nop 80087d4: 3714 adds r7, #20 80087d6: 46bd mov sp, r7 80087d8: f85d 7b04 ldr.w r7, [sp], #4 80087dc: 4770 bx lr 80087de: bf00 nop 80087e0: 40010000 .word 0x40010000 80087e4: 40000400 .word 0x40000400 80087e8: 40000800 .word 0x40000800 80087ec: 40000c00 .word 0x40000c00 80087f0: 40010400 .word 0x40010400 80087f4: 40014000 .word 0x40014000 80087f8: 40014400 .word 0x40014400 80087fc: 40014800 .word 0x40014800 08008800 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8008800: b480 push {r7} 8008802: b083 sub sp, #12 8008804: af00 add r7, sp, #0 8008806: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8008808: bf00 nop 800880a: 370c adds r7, #12 800880c: 46bd mov sp, r7 800880e: f85d 7b04 ldr.w r7, [sp], #4 8008812: 4770 bx lr 08008814 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8008814: b480 push {r7} 8008816: b083 sub sp, #12 8008818: af00 add r7, sp, #0 800881a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 800881c: bf00 nop 800881e: 370c adds r7, #12 8008820: 46bd mov sp, r7 8008822: f85d 7b04 ldr.w r7, [sp], #4 8008826: 4770 bx lr 08008828 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8008828: b480 push {r7} 800882a: b083 sub sp, #12 800882c: af00 add r7, sp, #0 800882e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8008830: bf00 nop 8008832: 370c adds r7, #12 8008834: 46bd mov sp, r7 8008836: f85d 7b04 ldr.w r7, [sp], #4 800883a: 4770 bx lr 0800883c : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 800883c: b580 push {r7, lr} 800883e: b082 sub sp, #8 8008840: af00 add r7, sp, #0 8008842: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8008844: 687b ldr r3, [r7, #4] 8008846: 2b00 cmp r3, #0 8008848: d101 bne.n 800884e { return HAL_ERROR; 800884a: 2301 movs r3, #1 800884c: e042 b.n 80088d4 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 800884e: 687b ldr r3, [r7, #4] 8008850: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8008854: 2b00 cmp r3, #0 8008856: d106 bne.n 8008866 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8008858: 687b ldr r3, [r7, #4] 800885a: 2200 movs r2, #0 800885c: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8008860: 6878 ldr r0, [r7, #4] 8008862: f7f8 fe69 bl 8001538 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8008866: 687b ldr r3, [r7, #4] 8008868: 2224 movs r2, #36 @ 0x24 800886a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 800886e: 687b ldr r3, [r7, #4] 8008870: 681b ldr r3, [r3, #0] 8008872: 681a ldr r2, [r3, #0] 8008874: 687b ldr r3, [r7, #4] 8008876: 681b ldr r3, [r3, #0] 8008878: f022 0201 bic.w r2, r2, #1 800887c: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 800887e: 687b ldr r3, [r7, #4] 8008880: 6a9b ldr r3, [r3, #40] @ 0x28 8008882: 2b00 cmp r3, #0 8008884: d002 beq.n 800888c { UART_AdvFeatureConfig(huart); 8008886: 6878 ldr r0, [r7, #4] 8008888: f001 f9e8 bl 8009c5c } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 800888c: 6878 ldr r0, [r7, #4] 800888e: f000 fc7d bl 800918c 8008892: 4603 mov r3, r0 8008894: 2b01 cmp r3, #1 8008896: d101 bne.n 800889c { return HAL_ERROR; 8008898: 2301 movs r3, #1 800889a: e01b b.n 80088d4 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 800889c: 687b ldr r3, [r7, #4] 800889e: 681b ldr r3, [r3, #0] 80088a0: 685a ldr r2, [r3, #4] 80088a2: 687b ldr r3, [r7, #4] 80088a4: 681b ldr r3, [r3, #0] 80088a6: f422 4290 bic.w r2, r2, #18432 @ 0x4800 80088aa: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 80088ac: 687b ldr r3, [r7, #4] 80088ae: 681b ldr r3, [r3, #0] 80088b0: 689a ldr r2, [r3, #8] 80088b2: 687b ldr r3, [r7, #4] 80088b4: 681b ldr r3, [r3, #0] 80088b6: f022 022a bic.w r2, r2, #42 @ 0x2a 80088ba: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 80088bc: 687b ldr r3, [r7, #4] 80088be: 681b ldr r3, [r3, #0] 80088c0: 681a ldr r2, [r3, #0] 80088c2: 687b ldr r3, [r7, #4] 80088c4: 681b ldr r3, [r3, #0] 80088c6: f042 0201 orr.w r2, r2, #1 80088ca: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 80088cc: 6878 ldr r0, [r7, #4] 80088ce: f001 fa67 bl 8009da0 80088d2: 4603 mov r3, r0 } 80088d4: 4618 mov r0, r3 80088d6: 3708 adds r7, #8 80088d8: 46bd mov sp, r7 80088da: bd80 pop {r7, pc} 080088dc : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 80088dc: b480 push {r7} 80088de: b091 sub sp, #68 @ 0x44 80088e0: af00 add r7, sp, #0 80088e2: 60f8 str r0, [r7, #12] 80088e4: 60b9 str r1, [r7, #8] 80088e6: 4613 mov r3, r2 80088e8: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 80088ea: 68fb ldr r3, [r7, #12] 80088ec: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80088f0: 2b20 cmp r3, #32 80088f2: d178 bne.n 80089e6 { if ((pData == NULL) || (Size == 0U)) 80088f4: 68bb ldr r3, [r7, #8] 80088f6: 2b00 cmp r3, #0 80088f8: d002 beq.n 8008900 80088fa: 88fb ldrh r3, [r7, #6] 80088fc: 2b00 cmp r3, #0 80088fe: d101 bne.n 8008904 { return HAL_ERROR; 8008900: 2301 movs r3, #1 8008902: e071 b.n 80089e8 } huart->pTxBuffPtr = pData; 8008904: 68fb ldr r3, [r7, #12] 8008906: 68ba ldr r2, [r7, #8] 8008908: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 800890a: 68fb ldr r3, [r7, #12] 800890c: 88fa ldrh r2, [r7, #6] 800890e: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8008912: 68fb ldr r3, [r7, #12] 8008914: 88fa ldrh r2, [r7, #6] 8008916: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 800891a: 68fb ldr r3, [r7, #12] 800891c: 2200 movs r2, #0 800891e: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 8008920: 68fb ldr r3, [r7, #12] 8008922: 2200 movs r2, #0 8008924: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 8008928: 68fb ldr r3, [r7, #12] 800892a: 2221 movs r2, #33 @ 0x21 800892c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 8008930: 68fb ldr r3, [r7, #12] 8008932: 6e5b ldr r3, [r3, #100] @ 0x64 8008934: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8008938: d12a bne.n 8008990 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800893a: 68fb ldr r3, [r7, #12] 800893c: 689b ldr r3, [r3, #8] 800893e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8008942: d107 bne.n 8008954 8008944: 68fb ldr r3, [r7, #12] 8008946: 691b ldr r3, [r3, #16] 8008948: 2b00 cmp r3, #0 800894a: d103 bne.n 8008954 { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 800894c: 68fb ldr r3, [r7, #12] 800894e: 4a29 ldr r2, [pc, #164] @ (80089f4 ) 8008950: 679a str r2, [r3, #120] @ 0x78 8008952: e002 b.n 800895a } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 8008954: 68fb ldr r3, [r7, #12] 8008956: 4a28 ldr r2, [pc, #160] @ (80089f8 ) 8008958: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 800895a: 68fb ldr r3, [r7, #12] 800895c: 681b ldr r3, [r3, #0] 800895e: 3308 adds r3, #8 8008960: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8008962: 6abb ldr r3, [r7, #40] @ 0x28 8008964: e853 3f00 ldrex r3, [r3] 8008968: 627b str r3, [r7, #36] @ 0x24 return(result); 800896a: 6a7b ldr r3, [r7, #36] @ 0x24 800896c: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8008970: 63bb str r3, [r7, #56] @ 0x38 8008972: 68fb ldr r3, [r7, #12] 8008974: 681b ldr r3, [r3, #0] 8008976: 3308 adds r3, #8 8008978: 6bba ldr r2, [r7, #56] @ 0x38 800897a: 637a str r2, [r7, #52] @ 0x34 800897c: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800897e: 6b39 ldr r1, [r7, #48] @ 0x30 8008980: 6b7a ldr r2, [r7, #52] @ 0x34 8008982: e841 2300 strex r3, r2, [r1] 8008986: 62fb str r3, [r7, #44] @ 0x2c return(result); 8008988: 6afb ldr r3, [r7, #44] @ 0x2c 800898a: 2b00 cmp r3, #0 800898c: d1e5 bne.n 800895a 800898e: e028 b.n 80089e2 } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8008990: 68fb ldr r3, [r7, #12] 8008992: 689b ldr r3, [r3, #8] 8008994: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8008998: d107 bne.n 80089aa 800899a: 68fb ldr r3, [r7, #12] 800899c: 691b ldr r3, [r3, #16] 800899e: 2b00 cmp r3, #0 80089a0: d103 bne.n 80089aa { huart->TxISR = UART_TxISR_16BIT; 80089a2: 68fb ldr r3, [r7, #12] 80089a4: 4a15 ldr r2, [pc, #84] @ (80089fc ) 80089a6: 679a str r2, [r3, #120] @ 0x78 80089a8: e002 b.n 80089b0 } else { huart->TxISR = UART_TxISR_8BIT; 80089aa: 68fb ldr r3, [r7, #12] 80089ac: 4a14 ldr r2, [pc, #80] @ (8008a00 ) 80089ae: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 80089b0: 68fb ldr r3, [r7, #12] 80089b2: 681b ldr r3, [r3, #0] 80089b4: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80089b6: 697b ldr r3, [r7, #20] 80089b8: e853 3f00 ldrex r3, [r3] 80089bc: 613b str r3, [r7, #16] return(result); 80089be: 693b ldr r3, [r7, #16] 80089c0: f043 0380 orr.w r3, r3, #128 @ 0x80 80089c4: 63fb str r3, [r7, #60] @ 0x3c 80089c6: 68fb ldr r3, [r7, #12] 80089c8: 681b ldr r3, [r3, #0] 80089ca: 461a mov r2, r3 80089cc: 6bfb ldr r3, [r7, #60] @ 0x3c 80089ce: 623b str r3, [r7, #32] 80089d0: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80089d2: 69f9 ldr r1, [r7, #28] 80089d4: 6a3a ldr r2, [r7, #32] 80089d6: e841 2300 strex r3, r2, [r1] 80089da: 61bb str r3, [r7, #24] return(result); 80089dc: 69bb ldr r3, [r7, #24] 80089de: 2b00 cmp r3, #0 80089e0: d1e6 bne.n 80089b0 } return HAL_OK; 80089e2: 2300 movs r3, #0 80089e4: e000 b.n 80089e8 } else { return HAL_BUSY; 80089e6: 2302 movs r3, #2 } } 80089e8: 4618 mov r0, r3 80089ea: 3744 adds r7, #68 @ 0x44 80089ec: 46bd mov sp, r7 80089ee: f85d 7b04 ldr.w r7, [sp], #4 80089f2: 4770 bx lr 80089f4: 0800a567 .word 0x0800a567 80089f8: 0800a487 .word 0x0800a487 80089fc: 0800a3c5 .word 0x0800a3c5 8008a00: 0800a30d .word 0x0800a30d 08008a04 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8008a04: b580 push {r7, lr} 8008a06: b0ba sub sp, #232 @ 0xe8 8008a08: af00 add r7, sp, #0 8008a0a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8008a0c: 687b ldr r3, [r7, #4] 8008a0e: 681b ldr r3, [r3, #0] 8008a10: 69db ldr r3, [r3, #28] 8008a12: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8008a16: 687b ldr r3, [r7, #4] 8008a18: 681b ldr r3, [r3, #0] 8008a1a: 681b ldr r3, [r3, #0] 8008a1c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8008a20: 687b ldr r3, [r7, #4] 8008a22: 681b ldr r3, [r3, #0] 8008a24: 689b ldr r3, [r3, #8] 8008a26: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 8008a2a: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 8008a2e: f640 030f movw r3, #2063 @ 0x80f 8008a32: 4013 ands r3, r2 8008a34: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 8008a38: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8008a3c: 2b00 cmp r3, #0 8008a3e: d11b bne.n 8008a78 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8008a40: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8008a44: f003 0320 and.w r3, r3, #32 8008a48: 2b00 cmp r3, #0 8008a4a: d015 beq.n 8008a78 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8008a4c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8008a50: f003 0320 and.w r3, r3, #32 8008a54: 2b00 cmp r3, #0 8008a56: d105 bne.n 8008a64 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8008a58: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8008a5c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8008a60: 2b00 cmp r3, #0 8008a62: d009 beq.n 8008a78 { if (huart->RxISR != NULL) 8008a64: 687b ldr r3, [r7, #4] 8008a66: 6f5b ldr r3, [r3, #116] @ 0x74 8008a68: 2b00 cmp r3, #0 8008a6a: f000 8377 beq.w 800915c { huart->RxISR(huart); 8008a6e: 687b ldr r3, [r7, #4] 8008a70: 6f5b ldr r3, [r3, #116] @ 0x74 8008a72: 6878 ldr r0, [r7, #4] 8008a74: 4798 blx r3 } return; 8008a76: e371 b.n 800915c } } /* If some errors occur */ if ((errorflags != 0U) 8008a78: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8008a7c: 2b00 cmp r3, #0 8008a7e: f000 8123 beq.w 8008cc8 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 8008a82: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8008a86: 4b8d ldr r3, [pc, #564] @ (8008cbc ) 8008a88: 4013 ands r3, r2 8008a8a: 2b00 cmp r3, #0 8008a8c: d106 bne.n 8008a9c || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8008a8e: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 8008a92: 4b8b ldr r3, [pc, #556] @ (8008cc0 ) 8008a94: 4013 ands r3, r2 8008a96: 2b00 cmp r3, #0 8008a98: f000 8116 beq.w 8008cc8 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8008a9c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8008aa0: f003 0301 and.w r3, r3, #1 8008aa4: 2b00 cmp r3, #0 8008aa6: d011 beq.n 8008acc 8008aa8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8008aac: f403 7380 and.w r3, r3, #256 @ 0x100 8008ab0: 2b00 cmp r3, #0 8008ab2: d00b beq.n 8008acc { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8008ab4: 687b ldr r3, [r7, #4] 8008ab6: 681b ldr r3, [r3, #0] 8008ab8: 2201 movs r2, #1 8008aba: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8008abc: 687b ldr r3, [r7, #4] 8008abe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8008ac2: f043 0201 orr.w r2, r3, #1 8008ac6: 687b ldr r3, [r7, #4] 8008ac8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8008acc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8008ad0: f003 0302 and.w r3, r3, #2 8008ad4: 2b00 cmp r3, #0 8008ad6: d011 beq.n 8008afc 8008ad8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8008adc: f003 0301 and.w r3, r3, #1 8008ae0: 2b00 cmp r3, #0 8008ae2: d00b beq.n 8008afc { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8008ae4: 687b ldr r3, [r7, #4] 8008ae6: 681b ldr r3, [r3, #0] 8008ae8: 2202 movs r2, #2 8008aea: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8008aec: 687b ldr r3, [r7, #4] 8008aee: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8008af2: f043 0204 orr.w r2, r3, #4 8008af6: 687b ldr r3, [r7, #4] 8008af8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8008afc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8008b00: f003 0304 and.w r3, r3, #4 8008b04: 2b00 cmp r3, #0 8008b06: d011 beq.n 8008b2c 8008b08: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8008b0c: f003 0301 and.w r3, r3, #1 8008b10: 2b00 cmp r3, #0 8008b12: d00b beq.n 8008b2c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8008b14: 687b ldr r3, [r7, #4] 8008b16: 681b ldr r3, [r3, #0] 8008b18: 2204 movs r2, #4 8008b1a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8008b1c: 687b ldr r3, [r7, #4] 8008b1e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8008b22: f043 0202 orr.w r2, r3, #2 8008b26: 687b ldr r3, [r7, #4] 8008b28: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 8008b2c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8008b30: f003 0308 and.w r3, r3, #8 8008b34: 2b00 cmp r3, #0 8008b36: d017 beq.n 8008b68 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8008b38: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8008b3c: f003 0320 and.w r3, r3, #32 8008b40: 2b00 cmp r3, #0 8008b42: d105 bne.n 8008b50 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 8008b44: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8008b48: 4b5c ldr r3, [pc, #368] @ (8008cbc ) 8008b4a: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8008b4c: 2b00 cmp r3, #0 8008b4e: d00b beq.n 8008b68 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8008b50: 687b ldr r3, [r7, #4] 8008b52: 681b ldr r3, [r3, #0] 8008b54: 2208 movs r2, #8 8008b56: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 8008b58: 687b ldr r3, [r7, #4] 8008b5a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8008b5e: f043 0208 orr.w r2, r3, #8 8008b62: 687b ldr r3, [r7, #4] 8008b64: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 8008b68: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8008b6c: f403 6300 and.w r3, r3, #2048 @ 0x800 8008b70: 2b00 cmp r3, #0 8008b72: d012 beq.n 8008b9a 8008b74: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8008b78: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8008b7c: 2b00 cmp r3, #0 8008b7e: d00c beq.n 8008b9a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8008b80: 687b ldr r3, [r7, #4] 8008b82: 681b ldr r3, [r3, #0] 8008b84: f44f 6200 mov.w r2, #2048 @ 0x800 8008b88: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8008b8a: 687b ldr r3, [r7, #4] 8008b8c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8008b90: f043 0220 orr.w r2, r3, #32 8008b94: 687b ldr r3, [r7, #4] 8008b96: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8008b9a: 687b ldr r3, [r7, #4] 8008b9c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8008ba0: 2b00 cmp r3, #0 8008ba2: f000 82dd beq.w 8009160 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8008ba6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8008baa: f003 0320 and.w r3, r3, #32 8008bae: 2b00 cmp r3, #0 8008bb0: d013 beq.n 8008bda && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8008bb2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8008bb6: f003 0320 and.w r3, r3, #32 8008bba: 2b00 cmp r3, #0 8008bbc: d105 bne.n 8008bca || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8008bbe: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8008bc2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8008bc6: 2b00 cmp r3, #0 8008bc8: d007 beq.n 8008bda { if (huart->RxISR != NULL) 8008bca: 687b ldr r3, [r7, #4] 8008bcc: 6f5b ldr r3, [r3, #116] @ 0x74 8008bce: 2b00 cmp r3, #0 8008bd0: d003 beq.n 8008bda { huart->RxISR(huart); 8008bd2: 687b ldr r3, [r7, #4] 8008bd4: 6f5b ldr r3, [r3, #116] @ 0x74 8008bd6: 6878 ldr r0, [r7, #4] 8008bd8: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 8008bda: 687b ldr r3, [r7, #4] 8008bdc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8008be0: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8008be4: 687b ldr r3, [r7, #4] 8008be6: 681b ldr r3, [r3, #0] 8008be8: 689b ldr r3, [r3, #8] 8008bea: f003 0340 and.w r3, r3, #64 @ 0x40 8008bee: 2b40 cmp r3, #64 @ 0x40 8008bf0: d005 beq.n 8008bfe ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8008bf2: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8008bf6: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8008bfa: 2b00 cmp r3, #0 8008bfc: d054 beq.n 8008ca8 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8008bfe: 6878 ldr r0, [r7, #4] 8008c00: f001 fb08 bl 800a214 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008c04: 687b ldr r3, [r7, #4] 8008c06: 681b ldr r3, [r3, #0] 8008c08: 689b ldr r3, [r3, #8] 8008c0a: f003 0340 and.w r3, r3, #64 @ 0x40 8008c0e: 2b40 cmp r3, #64 @ 0x40 8008c10: d146 bne.n 8008ca0 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8008c12: 687b ldr r3, [r7, #4] 8008c14: 681b ldr r3, [r3, #0] 8008c16: 3308 adds r3, #8 8008c18: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8008c1c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8008c20: e853 3f00 ldrex r3, [r3] 8008c24: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8008c28: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8008c2c: f023 0340 bic.w r3, r3, #64 @ 0x40 8008c30: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8008c34: 687b ldr r3, [r7, #4] 8008c36: 681b ldr r3, [r3, #0] 8008c38: 3308 adds r3, #8 8008c3a: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8008c3e: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8008c42: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8008c46: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8008c4a: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8008c4e: e841 2300 strex r3, r2, [r1] 8008c52: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8008c56: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8008c5a: 2b00 cmp r3, #0 8008c5c: d1d9 bne.n 8008c12 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8008c5e: 687b ldr r3, [r7, #4] 8008c60: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008c64: 2b00 cmp r3, #0 8008c66: d017 beq.n 8008c98 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8008c68: 687b ldr r3, [r7, #4] 8008c6a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008c6e: 4a15 ldr r2, [pc, #84] @ (8008cc4 ) 8008c70: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8008c72: 687b ldr r3, [r7, #4] 8008c74: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008c78: 4618 mov r0, r3 8008c7a: f7fa fee1 bl 8003a40 8008c7e: 4603 mov r3, r0 8008c80: 2b00 cmp r3, #0 8008c82: d019 beq.n 8008cb8 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8008c84: 687b ldr r3, [r7, #4] 8008c86: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008c8a: 6d1b ldr r3, [r3, #80] @ 0x50 8008c8c: 687a ldr r2, [r7, #4] 8008c8e: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 8008c92: 4610 mov r0, r2 8008c94: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008c96: e00f b.n 8008cb8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008c98: 6878 ldr r0, [r7, #4] 8008c9a: f000 fa6d bl 8009178 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008c9e: e00b b.n 8008cb8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008ca0: 6878 ldr r0, [r7, #4] 8008ca2: f000 fa69 bl 8009178 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008ca6: e007 b.n 8008cb8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8008ca8: 6878 ldr r0, [r7, #4] 8008caa: f000 fa65 bl 8009178 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8008cae: 687b ldr r3, [r7, #4] 8008cb0: 2200 movs r2, #0 8008cb2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 8008cb6: e253 b.n 8009160 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008cb8: bf00 nop return; 8008cba: e251 b.n 8009160 8008cbc: 10000001 .word 0x10000001 8008cc0: 04000120 .word 0x04000120 8008cc4: 0800a2e1 .word 0x0800a2e1 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8008cc8: 687b ldr r3, [r7, #4] 8008cca: 6edb ldr r3, [r3, #108] @ 0x6c 8008ccc: 2b01 cmp r3, #1 8008cce: f040 81e7 bne.w 80090a0 && ((isrflags & USART_ISR_IDLE) != 0U) 8008cd2: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8008cd6: f003 0310 and.w r3, r3, #16 8008cda: 2b00 cmp r3, #0 8008cdc: f000 81e0 beq.w 80090a0 && ((cr1its & USART_ISR_IDLE) != 0U)) 8008ce0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8008ce4: f003 0310 and.w r3, r3, #16 8008ce8: 2b00 cmp r3, #0 8008cea: f000 81d9 beq.w 80090a0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8008cee: 687b ldr r3, [r7, #4] 8008cf0: 681b ldr r3, [r3, #0] 8008cf2: 2210 movs r2, #16 8008cf4: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8008cf6: 687b ldr r3, [r7, #4] 8008cf8: 681b ldr r3, [r3, #0] 8008cfa: 689b ldr r3, [r3, #8] 8008cfc: f003 0340 and.w r3, r3, #64 @ 0x40 8008d00: 2b40 cmp r3, #64 @ 0x40 8008d02: f040 8151 bne.w 8008fa8 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8008d06: 687b ldr r3, [r7, #4] 8008d08: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d0c: 681b ldr r3, [r3, #0] 8008d0e: 4a96 ldr r2, [pc, #600] @ (8008f68 ) 8008d10: 4293 cmp r3, r2 8008d12: d068 beq.n 8008de6 8008d14: 687b ldr r3, [r7, #4] 8008d16: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d1a: 681b ldr r3, [r3, #0] 8008d1c: 4a93 ldr r2, [pc, #588] @ (8008f6c ) 8008d1e: 4293 cmp r3, r2 8008d20: d061 beq.n 8008de6 8008d22: 687b ldr r3, [r7, #4] 8008d24: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d28: 681b ldr r3, [r3, #0] 8008d2a: 4a91 ldr r2, [pc, #580] @ (8008f70 ) 8008d2c: 4293 cmp r3, r2 8008d2e: d05a beq.n 8008de6 8008d30: 687b ldr r3, [r7, #4] 8008d32: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d36: 681b ldr r3, [r3, #0] 8008d38: 4a8e ldr r2, [pc, #568] @ (8008f74 ) 8008d3a: 4293 cmp r3, r2 8008d3c: d053 beq.n 8008de6 8008d3e: 687b ldr r3, [r7, #4] 8008d40: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d44: 681b ldr r3, [r3, #0] 8008d46: 4a8c ldr r2, [pc, #560] @ (8008f78 ) 8008d48: 4293 cmp r3, r2 8008d4a: d04c beq.n 8008de6 8008d4c: 687b ldr r3, [r7, #4] 8008d4e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d52: 681b ldr r3, [r3, #0] 8008d54: 4a89 ldr r2, [pc, #548] @ (8008f7c ) 8008d56: 4293 cmp r3, r2 8008d58: d045 beq.n 8008de6 8008d5a: 687b ldr r3, [r7, #4] 8008d5c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d60: 681b ldr r3, [r3, #0] 8008d62: 4a87 ldr r2, [pc, #540] @ (8008f80 ) 8008d64: 4293 cmp r3, r2 8008d66: d03e beq.n 8008de6 8008d68: 687b ldr r3, [r7, #4] 8008d6a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d6e: 681b ldr r3, [r3, #0] 8008d70: 4a84 ldr r2, [pc, #528] @ (8008f84 ) 8008d72: 4293 cmp r3, r2 8008d74: d037 beq.n 8008de6 8008d76: 687b ldr r3, [r7, #4] 8008d78: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d7c: 681b ldr r3, [r3, #0] 8008d7e: 4a82 ldr r2, [pc, #520] @ (8008f88 ) 8008d80: 4293 cmp r3, r2 8008d82: d030 beq.n 8008de6 8008d84: 687b ldr r3, [r7, #4] 8008d86: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d8a: 681b ldr r3, [r3, #0] 8008d8c: 4a7f ldr r2, [pc, #508] @ (8008f8c ) 8008d8e: 4293 cmp r3, r2 8008d90: d029 beq.n 8008de6 8008d92: 687b ldr r3, [r7, #4] 8008d94: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008d98: 681b ldr r3, [r3, #0] 8008d9a: 4a7d ldr r2, [pc, #500] @ (8008f90 ) 8008d9c: 4293 cmp r3, r2 8008d9e: d022 beq.n 8008de6 8008da0: 687b ldr r3, [r7, #4] 8008da2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008da6: 681b ldr r3, [r3, #0] 8008da8: 4a7a ldr r2, [pc, #488] @ (8008f94 ) 8008daa: 4293 cmp r3, r2 8008dac: d01b beq.n 8008de6 8008dae: 687b ldr r3, [r7, #4] 8008db0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008db4: 681b ldr r3, [r3, #0] 8008db6: 4a78 ldr r2, [pc, #480] @ (8008f98 ) 8008db8: 4293 cmp r3, r2 8008dba: d014 beq.n 8008de6 8008dbc: 687b ldr r3, [r7, #4] 8008dbe: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008dc2: 681b ldr r3, [r3, #0] 8008dc4: 4a75 ldr r2, [pc, #468] @ (8008f9c ) 8008dc6: 4293 cmp r3, r2 8008dc8: d00d beq.n 8008de6 8008dca: 687b ldr r3, [r7, #4] 8008dcc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008dd0: 681b ldr r3, [r3, #0] 8008dd2: 4a73 ldr r2, [pc, #460] @ (8008fa0 ) 8008dd4: 4293 cmp r3, r2 8008dd6: d006 beq.n 8008de6 8008dd8: 687b ldr r3, [r7, #4] 8008dda: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008dde: 681b ldr r3, [r3, #0] 8008de0: 4a70 ldr r2, [pc, #448] @ (8008fa4 ) 8008de2: 4293 cmp r3, r2 8008de4: d106 bne.n 8008df4 8008de6: 687b ldr r3, [r7, #4] 8008de8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008dec: 681b ldr r3, [r3, #0] 8008dee: 685b ldr r3, [r3, #4] 8008df0: b29b uxth r3, r3 8008df2: e005 b.n 8008e00 8008df4: 687b ldr r3, [r7, #4] 8008df6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008dfa: 681b ldr r3, [r3, #0] 8008dfc: 685b ldr r3, [r3, #4] 8008dfe: b29b uxth r3, r3 8008e00: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8008e04: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8008e08: 2b00 cmp r3, #0 8008e0a: f000 81ab beq.w 8009164 && (nb_remaining_rx_data < huart->RxXferSize)) 8008e0e: 687b ldr r3, [r7, #4] 8008e10: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8008e14: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8008e18: 429a cmp r2, r3 8008e1a: f080 81a3 bcs.w 8009164 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8008e1e: 687b ldr r3, [r7, #4] 8008e20: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8008e24: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8008e28: 687b ldr r3, [r7, #4] 8008e2a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008e2e: 69db ldr r3, [r3, #28] 8008e30: f5b3 7f80 cmp.w r3, #256 @ 0x100 8008e34: f000 8087 beq.w 8008f46 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8008e38: 687b ldr r3, [r7, #4] 8008e3a: 681b ldr r3, [r3, #0] 8008e3c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8008e40: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8008e44: e853 3f00 ldrex r3, [r3] 8008e48: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8008e4c: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8008e50: f423 7380 bic.w r3, r3, #256 @ 0x100 8008e54: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8008e58: 687b ldr r3, [r7, #4] 8008e5a: 681b ldr r3, [r3, #0] 8008e5c: 461a mov r2, r3 8008e5e: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 8008e62: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8008e66: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8008e6a: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 8008e6e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8008e72: e841 2300 strex r3, r2, [r1] 8008e76: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8008e7a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8008e7e: 2b00 cmp r3, #0 8008e80: d1da bne.n 8008e38 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8008e82: 687b ldr r3, [r7, #4] 8008e84: 681b ldr r3, [r3, #0] 8008e86: 3308 adds r3, #8 8008e88: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8008e8a: 6f7b ldr r3, [r7, #116] @ 0x74 8008e8c: e853 3f00 ldrex r3, [r3] 8008e90: 673b str r3, [r7, #112] @ 0x70 return(result); 8008e92: 6f3b ldr r3, [r7, #112] @ 0x70 8008e94: f023 0301 bic.w r3, r3, #1 8008e98: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8008e9c: 687b ldr r3, [r7, #4] 8008e9e: 681b ldr r3, [r3, #0] 8008ea0: 3308 adds r3, #8 8008ea2: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8008ea6: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8008eaa: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8008eac: 6ff9 ldr r1, [r7, #124] @ 0x7c 8008eae: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8008eb2: e841 2300 strex r3, r2, [r1] 8008eb6: 67bb str r3, [r7, #120] @ 0x78 return(result); 8008eb8: 6fbb ldr r3, [r7, #120] @ 0x78 8008eba: 2b00 cmp r3, #0 8008ebc: d1e1 bne.n 8008e82 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8008ebe: 687b ldr r3, [r7, #4] 8008ec0: 681b ldr r3, [r3, #0] 8008ec2: 3308 adds r3, #8 8008ec4: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8008ec6: 6e3b ldr r3, [r7, #96] @ 0x60 8008ec8: e853 3f00 ldrex r3, [r3] 8008ecc: 65fb str r3, [r7, #92] @ 0x5c return(result); 8008ece: 6dfb ldr r3, [r7, #92] @ 0x5c 8008ed0: f023 0340 bic.w r3, r3, #64 @ 0x40 8008ed4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8008ed8: 687b ldr r3, [r7, #4] 8008eda: 681b ldr r3, [r3, #0] 8008edc: 3308 adds r3, #8 8008ede: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8008ee2: 66fa str r2, [r7, #108] @ 0x6c 8008ee4: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8008ee6: 6eb9 ldr r1, [r7, #104] @ 0x68 8008ee8: 6efa ldr r2, [r7, #108] @ 0x6c 8008eea: e841 2300 strex r3, r2, [r1] 8008eee: 667b str r3, [r7, #100] @ 0x64 return(result); 8008ef0: 6e7b ldr r3, [r7, #100] @ 0x64 8008ef2: 2b00 cmp r3, #0 8008ef4: d1e3 bne.n 8008ebe /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8008ef6: 687b ldr r3, [r7, #4] 8008ef8: 2220 movs r2, #32 8008efa: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8008efe: 687b ldr r3, [r7, #4] 8008f00: 2200 movs r2, #0 8008f02: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8008f04: 687b ldr r3, [r7, #4] 8008f06: 681b ldr r3, [r3, #0] 8008f08: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8008f0a: 6cfb ldr r3, [r7, #76] @ 0x4c 8008f0c: e853 3f00 ldrex r3, [r3] 8008f10: 64bb str r3, [r7, #72] @ 0x48 return(result); 8008f12: 6cbb ldr r3, [r7, #72] @ 0x48 8008f14: f023 0310 bic.w r3, r3, #16 8008f18: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8008f1c: 687b ldr r3, [r7, #4] 8008f1e: 681b ldr r3, [r3, #0] 8008f20: 461a mov r2, r3 8008f22: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8008f26: 65bb str r3, [r7, #88] @ 0x58 8008f28: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8008f2a: 6d79 ldr r1, [r7, #84] @ 0x54 8008f2c: 6dba ldr r2, [r7, #88] @ 0x58 8008f2e: e841 2300 strex r3, r2, [r1] 8008f32: 653b str r3, [r7, #80] @ 0x50 return(result); 8008f34: 6d3b ldr r3, [r7, #80] @ 0x50 8008f36: 2b00 cmp r3, #0 8008f38: d1e4 bne.n 8008f04 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8008f3a: 687b ldr r3, [r7, #4] 8008f3c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8008f40: 4618 mov r0, r3 8008f42: f7fa fa5f bl 8003404 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8008f46: 687b ldr r3, [r7, #4] 8008f48: 2202 movs r2, #2 8008f4a: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8008f4c: 687b ldr r3, [r7, #4] 8008f4e: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8008f52: 687b ldr r3, [r7, #4] 8008f54: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8008f58: b29b uxth r3, r3 8008f5a: 1ad3 subs r3, r2, r3 8008f5c: b29b uxth r3, r3 8008f5e: 4619 mov r1, r3 8008f60: 6878 ldr r0, [r7, #4] 8008f62: f7f8 fe65 bl 8001c30 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8008f66: e0fd b.n 8009164 8008f68: 40020010 .word 0x40020010 8008f6c: 40020028 .word 0x40020028 8008f70: 40020040 .word 0x40020040 8008f74: 40020058 .word 0x40020058 8008f78: 40020070 .word 0x40020070 8008f7c: 40020088 .word 0x40020088 8008f80: 400200a0 .word 0x400200a0 8008f84: 400200b8 .word 0x400200b8 8008f88: 40020410 .word 0x40020410 8008f8c: 40020428 .word 0x40020428 8008f90: 40020440 .word 0x40020440 8008f94: 40020458 .word 0x40020458 8008f98: 40020470 .word 0x40020470 8008f9c: 40020488 .word 0x40020488 8008fa0: 400204a0 .word 0x400204a0 8008fa4: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8008fa8: 687b ldr r3, [r7, #4] 8008faa: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8008fae: 687b ldr r3, [r7, #4] 8008fb0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8008fb4: b29b uxth r3, r3 8008fb6: 1ad3 subs r3, r2, r3 8008fb8: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8008fbc: 687b ldr r3, [r7, #4] 8008fbe: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8008fc2: b29b uxth r3, r3 8008fc4: 2b00 cmp r3, #0 8008fc6: f000 80cf beq.w 8009168 && (nb_rx_data > 0U)) 8008fca: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8008fce: 2b00 cmp r3, #0 8008fd0: f000 80ca beq.w 8009168 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8008fd4: 687b ldr r3, [r7, #4] 8008fd6: 681b ldr r3, [r3, #0] 8008fd8: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8008fda: 6bbb ldr r3, [r7, #56] @ 0x38 8008fdc: e853 3f00 ldrex r3, [r3] 8008fe0: 637b str r3, [r7, #52] @ 0x34 return(result); 8008fe2: 6b7b ldr r3, [r7, #52] @ 0x34 8008fe4: f423 7390 bic.w r3, r3, #288 @ 0x120 8008fe8: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8008fec: 687b ldr r3, [r7, #4] 8008fee: 681b ldr r3, [r3, #0] 8008ff0: 461a mov r2, r3 8008ff2: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8008ff6: 647b str r3, [r7, #68] @ 0x44 8008ff8: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8008ffa: 6c39 ldr r1, [r7, #64] @ 0x40 8008ffc: 6c7a ldr r2, [r7, #68] @ 0x44 8008ffe: e841 2300 strex r3, r2, [r1] 8009002: 63fb str r3, [r7, #60] @ 0x3c return(result); 8009004: 6bfb ldr r3, [r7, #60] @ 0x3c 8009006: 2b00 cmp r3, #0 8009008: d1e4 bne.n 8008fd4 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800900a: 687b ldr r3, [r7, #4] 800900c: 681b ldr r3, [r3, #0] 800900e: 3308 adds r3, #8 8009010: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009012: 6a7b ldr r3, [r7, #36] @ 0x24 8009014: e853 3f00 ldrex r3, [r3] 8009018: 623b str r3, [r7, #32] return(result); 800901a: 6a3a ldr r2, [r7, #32] 800901c: 4b55 ldr r3, [pc, #340] @ (8009174 ) 800901e: 4013 ands r3, r2 8009020: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8009024: 687b ldr r3, [r7, #4] 8009026: 681b ldr r3, [r3, #0] 8009028: 3308 adds r3, #8 800902a: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 800902e: 633a str r2, [r7, #48] @ 0x30 8009030: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8009032: 6af9 ldr r1, [r7, #44] @ 0x2c 8009034: 6b3a ldr r2, [r7, #48] @ 0x30 8009036: e841 2300 strex r3, r2, [r1] 800903a: 62bb str r3, [r7, #40] @ 0x28 return(result); 800903c: 6abb ldr r3, [r7, #40] @ 0x28 800903e: 2b00 cmp r3, #0 8009040: d1e3 bne.n 800900a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8009042: 687b ldr r3, [r7, #4] 8009044: 2220 movs r2, #32 8009046: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800904a: 687b ldr r3, [r7, #4] 800904c: 2200 movs r2, #0 800904e: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8009050: 687b ldr r3, [r7, #4] 8009052: 2200 movs r2, #0 8009054: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8009056: 687b ldr r3, [r7, #4] 8009058: 681b ldr r3, [r3, #0] 800905a: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800905c: 693b ldr r3, [r7, #16] 800905e: e853 3f00 ldrex r3, [r3] 8009062: 60fb str r3, [r7, #12] return(result); 8009064: 68fb ldr r3, [r7, #12] 8009066: f023 0310 bic.w r3, r3, #16 800906a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800906e: 687b ldr r3, [r7, #4] 8009070: 681b ldr r3, [r3, #0] 8009072: 461a mov r2, r3 8009074: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8009078: 61fb str r3, [r7, #28] 800907a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800907c: 69b9 ldr r1, [r7, #24] 800907e: 69fa ldr r2, [r7, #28] 8009080: e841 2300 strex r3, r2, [r1] 8009084: 617b str r3, [r7, #20] return(result); 8009086: 697b ldr r3, [r7, #20] 8009088: 2b00 cmp r3, #0 800908a: d1e4 bne.n 8009056 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 800908c: 687b ldr r3, [r7, #4] 800908e: 2202 movs r2, #2 8009090: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8009092: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8009096: 4619 mov r1, r3 8009098: 6878 ldr r0, [r7, #4] 800909a: f7f8 fdc9 bl 8001c30 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 800909e: e063 b.n 8009168 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 80090a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80090a4: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80090a8: 2b00 cmp r3, #0 80090aa: d00e beq.n 80090ca 80090ac: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80090b0: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80090b4: 2b00 cmp r3, #0 80090b6: d008 beq.n 80090ca { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 80090b8: 687b ldr r3, [r7, #4] 80090ba: 681b ldr r3, [r3, #0] 80090bc: f44f 1280 mov.w r2, #1048576 @ 0x100000 80090c0: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 80090c2: 6878 ldr r0, [r7, #4] 80090c4: f002 f80c bl 800b0e0 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 80090c8: e051 b.n 800916e } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 80090ca: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80090ce: f003 0380 and.w r3, r3, #128 @ 0x80 80090d2: 2b00 cmp r3, #0 80090d4: d014 beq.n 8009100 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 80090d6: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80090da: f003 0380 and.w r3, r3, #128 @ 0x80 80090de: 2b00 cmp r3, #0 80090e0: d105 bne.n 80090ee || ((cr3its & USART_CR3_TXFTIE) != 0U))) 80090e2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80090e6: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80090ea: 2b00 cmp r3, #0 80090ec: d008 beq.n 8009100 { if (huart->TxISR != NULL) 80090ee: 687b ldr r3, [r7, #4] 80090f0: 6f9b ldr r3, [r3, #120] @ 0x78 80090f2: 2b00 cmp r3, #0 80090f4: d03a beq.n 800916c { huart->TxISR(huart); 80090f6: 687b ldr r3, [r7, #4] 80090f8: 6f9b ldr r3, [r3, #120] @ 0x78 80090fa: 6878 ldr r0, [r7, #4] 80090fc: 4798 blx r3 } return; 80090fe: e035 b.n 800916c } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8009100: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009104: f003 0340 and.w r3, r3, #64 @ 0x40 8009108: 2b00 cmp r3, #0 800910a: d009 beq.n 8009120 800910c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8009110: f003 0340 and.w r3, r3, #64 @ 0x40 8009114: 2b00 cmp r3, #0 8009116: d003 beq.n 8009120 { UART_EndTransmit_IT(huart); 8009118: 6878 ldr r0, [r7, #4] 800911a: f001 fa99 bl 800a650 return; 800911e: e026 b.n 800916e } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8009120: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009124: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8009128: 2b00 cmp r3, #0 800912a: d009 beq.n 8009140 800912c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8009130: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8009134: 2b00 cmp r3, #0 8009136: d003 beq.n 8009140 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 8009138: 6878 ldr r0, [r7, #4] 800913a: f001 ffe5 bl 800b108 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 800913e: e016 b.n 800916e } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8009140: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8009144: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8009148: 2b00 cmp r3, #0 800914a: d010 beq.n 800916e 800914c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8009150: 2b00 cmp r3, #0 8009152: da0c bge.n 800916e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8009154: 6878 ldr r0, [r7, #4] 8009156: f001 ffcd bl 800b0f4 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 800915a: e008 b.n 800916e return; 800915c: bf00 nop 800915e: e006 b.n 800916e return; 8009160: bf00 nop 8009162: e004 b.n 800916e return; 8009164: bf00 nop 8009166: e002 b.n 800916e return; 8009168: bf00 nop 800916a: e000 b.n 800916e return; 800916c: bf00 nop } } 800916e: 37e8 adds r7, #232 @ 0xe8 8009170: 46bd mov sp, r7 8009172: bd80 pop {r7, pc} 8009174: effffffe .word 0xeffffffe 08009178 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8009178: b480 push {r7} 800917a: b083 sub sp, #12 800917c: af00 add r7, sp, #0 800917e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8009180: bf00 nop 8009182: 370c adds r7, #12 8009184: 46bd mov sp, r7 8009186: f85d 7b04 ldr.w r7, [sp], #4 800918a: 4770 bx lr 0800918c : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 800918c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8009190: b092 sub sp, #72 @ 0x48 8009192: af00 add r7, sp, #0 8009194: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8009196: 2300 movs r3, #0 8009198: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 800919c: 697b ldr r3, [r7, #20] 800919e: 689a ldr r2, [r3, #8] 80091a0: 697b ldr r3, [r7, #20] 80091a2: 691b ldr r3, [r3, #16] 80091a4: 431a orrs r2, r3 80091a6: 697b ldr r3, [r7, #20] 80091a8: 695b ldr r3, [r3, #20] 80091aa: 431a orrs r2, r3 80091ac: 697b ldr r3, [r7, #20] 80091ae: 69db ldr r3, [r3, #28] 80091b0: 4313 orrs r3, r2 80091b2: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 80091b4: 697b ldr r3, [r7, #20] 80091b6: 681b ldr r3, [r3, #0] 80091b8: 681a ldr r2, [r3, #0] 80091ba: 4bbe ldr r3, [pc, #760] @ (80094b4 ) 80091bc: 4013 ands r3, r2 80091be: 697a ldr r2, [r7, #20] 80091c0: 6812 ldr r2, [r2, #0] 80091c2: 6c79 ldr r1, [r7, #68] @ 0x44 80091c4: 430b orrs r3, r1 80091c6: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 80091c8: 697b ldr r3, [r7, #20] 80091ca: 681b ldr r3, [r3, #0] 80091cc: 685b ldr r3, [r3, #4] 80091ce: f423 5140 bic.w r1, r3, #12288 @ 0x3000 80091d2: 697b ldr r3, [r7, #20] 80091d4: 68da ldr r2, [r3, #12] 80091d6: 697b ldr r3, [r7, #20] 80091d8: 681b ldr r3, [r3, #0] 80091da: 430a orrs r2, r1 80091dc: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 80091de: 697b ldr r3, [r7, #20] 80091e0: 699b ldr r3, [r3, #24] 80091e2: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 80091e4: 697b ldr r3, [r7, #20] 80091e6: 681b ldr r3, [r3, #0] 80091e8: 4ab3 ldr r2, [pc, #716] @ (80094b8 ) 80091ea: 4293 cmp r3, r2 80091ec: d004 beq.n 80091f8 { tmpreg |= huart->Init.OneBitSampling; 80091ee: 697b ldr r3, [r7, #20] 80091f0: 6a1b ldr r3, [r3, #32] 80091f2: 6c7a ldr r2, [r7, #68] @ 0x44 80091f4: 4313 orrs r3, r2 80091f6: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 80091f8: 697b ldr r3, [r7, #20] 80091fa: 681b ldr r3, [r3, #0] 80091fc: 689a ldr r2, [r3, #8] 80091fe: 4baf ldr r3, [pc, #700] @ (80094bc ) 8009200: 4013 ands r3, r2 8009202: 697a ldr r2, [r7, #20] 8009204: 6812 ldr r2, [r2, #0] 8009206: 6c79 ldr r1, [r7, #68] @ 0x44 8009208: 430b orrs r3, r1 800920a: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 800920c: 697b ldr r3, [r7, #20] 800920e: 681b ldr r3, [r3, #0] 8009210: 6adb ldr r3, [r3, #44] @ 0x2c 8009212: f023 010f bic.w r1, r3, #15 8009216: 697b ldr r3, [r7, #20] 8009218: 6a5a ldr r2, [r3, #36] @ 0x24 800921a: 697b ldr r3, [r7, #20] 800921c: 681b ldr r3, [r3, #0] 800921e: 430a orrs r2, r1 8009220: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8009222: 697b ldr r3, [r7, #20] 8009224: 681b ldr r3, [r3, #0] 8009226: 4aa6 ldr r2, [pc, #664] @ (80094c0 ) 8009228: 4293 cmp r3, r2 800922a: d177 bne.n 800931c 800922c: 4ba5 ldr r3, [pc, #660] @ (80094c4 ) 800922e: 6d5b ldr r3, [r3, #84] @ 0x54 8009230: f003 0338 and.w r3, r3, #56 @ 0x38 8009234: 2b28 cmp r3, #40 @ 0x28 8009236: d86d bhi.n 8009314 8009238: a201 add r2, pc, #4 @ (adr r2, 8009240 ) 800923a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800923e: bf00 nop 8009240: 080092e5 .word 0x080092e5 8009244: 08009315 .word 0x08009315 8009248: 08009315 .word 0x08009315 800924c: 08009315 .word 0x08009315 8009250: 08009315 .word 0x08009315 8009254: 08009315 .word 0x08009315 8009258: 08009315 .word 0x08009315 800925c: 08009315 .word 0x08009315 8009260: 080092ed .word 0x080092ed 8009264: 08009315 .word 0x08009315 8009268: 08009315 .word 0x08009315 800926c: 08009315 .word 0x08009315 8009270: 08009315 .word 0x08009315 8009274: 08009315 .word 0x08009315 8009278: 08009315 .word 0x08009315 800927c: 08009315 .word 0x08009315 8009280: 080092f5 .word 0x080092f5 8009284: 08009315 .word 0x08009315 8009288: 08009315 .word 0x08009315 800928c: 08009315 .word 0x08009315 8009290: 08009315 .word 0x08009315 8009294: 08009315 .word 0x08009315 8009298: 08009315 .word 0x08009315 800929c: 08009315 .word 0x08009315 80092a0: 080092fd .word 0x080092fd 80092a4: 08009315 .word 0x08009315 80092a8: 08009315 .word 0x08009315 80092ac: 08009315 .word 0x08009315 80092b0: 08009315 .word 0x08009315 80092b4: 08009315 .word 0x08009315 80092b8: 08009315 .word 0x08009315 80092bc: 08009315 .word 0x08009315 80092c0: 08009305 .word 0x08009305 80092c4: 08009315 .word 0x08009315 80092c8: 08009315 .word 0x08009315 80092cc: 08009315 .word 0x08009315 80092d0: 08009315 .word 0x08009315 80092d4: 08009315 .word 0x08009315 80092d8: 08009315 .word 0x08009315 80092dc: 08009315 .word 0x08009315 80092e0: 0800930d .word 0x0800930d 80092e4: 2301 movs r3, #1 80092e6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80092ea: e222 b.n 8009732 80092ec: 2304 movs r3, #4 80092ee: f887 3043 strb.w r3, [r7, #67] @ 0x43 80092f2: e21e b.n 8009732 80092f4: 2308 movs r3, #8 80092f6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80092fa: e21a b.n 8009732 80092fc: 2310 movs r3, #16 80092fe: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009302: e216 b.n 8009732 8009304: 2320 movs r3, #32 8009306: f887 3043 strb.w r3, [r7, #67] @ 0x43 800930a: e212 b.n 8009732 800930c: 2340 movs r3, #64 @ 0x40 800930e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009312: e20e b.n 8009732 8009314: 2380 movs r3, #128 @ 0x80 8009316: f887 3043 strb.w r3, [r7, #67] @ 0x43 800931a: e20a b.n 8009732 800931c: 697b ldr r3, [r7, #20] 800931e: 681b ldr r3, [r3, #0] 8009320: 4a69 ldr r2, [pc, #420] @ (80094c8 ) 8009322: 4293 cmp r3, r2 8009324: d130 bne.n 8009388 8009326: 4b67 ldr r3, [pc, #412] @ (80094c4 ) 8009328: 6d5b ldr r3, [r3, #84] @ 0x54 800932a: f003 0307 and.w r3, r3, #7 800932e: 2b05 cmp r3, #5 8009330: d826 bhi.n 8009380 8009332: a201 add r2, pc, #4 @ (adr r2, 8009338 ) 8009334: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009338: 08009351 .word 0x08009351 800933c: 08009359 .word 0x08009359 8009340: 08009361 .word 0x08009361 8009344: 08009369 .word 0x08009369 8009348: 08009371 .word 0x08009371 800934c: 08009379 .word 0x08009379 8009350: 2300 movs r3, #0 8009352: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009356: e1ec b.n 8009732 8009358: 2304 movs r3, #4 800935a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800935e: e1e8 b.n 8009732 8009360: 2308 movs r3, #8 8009362: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009366: e1e4 b.n 8009732 8009368: 2310 movs r3, #16 800936a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800936e: e1e0 b.n 8009732 8009370: 2320 movs r3, #32 8009372: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009376: e1dc b.n 8009732 8009378: 2340 movs r3, #64 @ 0x40 800937a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800937e: e1d8 b.n 8009732 8009380: 2380 movs r3, #128 @ 0x80 8009382: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009386: e1d4 b.n 8009732 8009388: 697b ldr r3, [r7, #20] 800938a: 681b ldr r3, [r3, #0] 800938c: 4a4f ldr r2, [pc, #316] @ (80094cc ) 800938e: 4293 cmp r3, r2 8009390: d130 bne.n 80093f4 8009392: 4b4c ldr r3, [pc, #304] @ (80094c4 ) 8009394: 6d5b ldr r3, [r3, #84] @ 0x54 8009396: f003 0307 and.w r3, r3, #7 800939a: 2b05 cmp r3, #5 800939c: d826 bhi.n 80093ec 800939e: a201 add r2, pc, #4 @ (adr r2, 80093a4 ) 80093a0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80093a4: 080093bd .word 0x080093bd 80093a8: 080093c5 .word 0x080093c5 80093ac: 080093cd .word 0x080093cd 80093b0: 080093d5 .word 0x080093d5 80093b4: 080093dd .word 0x080093dd 80093b8: 080093e5 .word 0x080093e5 80093bc: 2300 movs r3, #0 80093be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80093c2: e1b6 b.n 8009732 80093c4: 2304 movs r3, #4 80093c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80093ca: e1b2 b.n 8009732 80093cc: 2308 movs r3, #8 80093ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 80093d2: e1ae b.n 8009732 80093d4: 2310 movs r3, #16 80093d6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80093da: e1aa b.n 8009732 80093dc: 2320 movs r3, #32 80093de: f887 3043 strb.w r3, [r7, #67] @ 0x43 80093e2: e1a6 b.n 8009732 80093e4: 2340 movs r3, #64 @ 0x40 80093e6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80093ea: e1a2 b.n 8009732 80093ec: 2380 movs r3, #128 @ 0x80 80093ee: f887 3043 strb.w r3, [r7, #67] @ 0x43 80093f2: e19e b.n 8009732 80093f4: 697b ldr r3, [r7, #20] 80093f6: 681b ldr r3, [r3, #0] 80093f8: 4a35 ldr r2, [pc, #212] @ (80094d0 ) 80093fa: 4293 cmp r3, r2 80093fc: d130 bne.n 8009460 80093fe: 4b31 ldr r3, [pc, #196] @ (80094c4 ) 8009400: 6d5b ldr r3, [r3, #84] @ 0x54 8009402: f003 0307 and.w r3, r3, #7 8009406: 2b05 cmp r3, #5 8009408: d826 bhi.n 8009458 800940a: a201 add r2, pc, #4 @ (adr r2, 8009410 ) 800940c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009410: 08009429 .word 0x08009429 8009414: 08009431 .word 0x08009431 8009418: 08009439 .word 0x08009439 800941c: 08009441 .word 0x08009441 8009420: 08009449 .word 0x08009449 8009424: 08009451 .word 0x08009451 8009428: 2300 movs r3, #0 800942a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800942e: e180 b.n 8009732 8009430: 2304 movs r3, #4 8009432: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009436: e17c b.n 8009732 8009438: 2308 movs r3, #8 800943a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800943e: e178 b.n 8009732 8009440: 2310 movs r3, #16 8009442: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009446: e174 b.n 8009732 8009448: 2320 movs r3, #32 800944a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800944e: e170 b.n 8009732 8009450: 2340 movs r3, #64 @ 0x40 8009452: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009456: e16c b.n 8009732 8009458: 2380 movs r3, #128 @ 0x80 800945a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800945e: e168 b.n 8009732 8009460: 697b ldr r3, [r7, #20] 8009462: 681b ldr r3, [r3, #0] 8009464: 4a1b ldr r2, [pc, #108] @ (80094d4 ) 8009466: 4293 cmp r3, r2 8009468: d142 bne.n 80094f0 800946a: 4b16 ldr r3, [pc, #88] @ (80094c4 ) 800946c: 6d5b ldr r3, [r3, #84] @ 0x54 800946e: f003 0307 and.w r3, r3, #7 8009472: 2b05 cmp r3, #5 8009474: d838 bhi.n 80094e8 8009476: a201 add r2, pc, #4 @ (adr r2, 800947c ) 8009478: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800947c: 08009495 .word 0x08009495 8009480: 0800949d .word 0x0800949d 8009484: 080094a5 .word 0x080094a5 8009488: 080094ad .word 0x080094ad 800948c: 080094d9 .word 0x080094d9 8009490: 080094e1 .word 0x080094e1 8009494: 2300 movs r3, #0 8009496: f887 3043 strb.w r3, [r7, #67] @ 0x43 800949a: e14a b.n 8009732 800949c: 2304 movs r3, #4 800949e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80094a2: e146 b.n 8009732 80094a4: 2308 movs r3, #8 80094a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80094aa: e142 b.n 8009732 80094ac: 2310 movs r3, #16 80094ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80094b2: e13e b.n 8009732 80094b4: cfff69f3 .word 0xcfff69f3 80094b8: 58000c00 .word 0x58000c00 80094bc: 11fff4ff .word 0x11fff4ff 80094c0: 40011000 .word 0x40011000 80094c4: 58024400 .word 0x58024400 80094c8: 40004400 .word 0x40004400 80094cc: 40004800 .word 0x40004800 80094d0: 40004c00 .word 0x40004c00 80094d4: 40005000 .word 0x40005000 80094d8: 2320 movs r3, #32 80094da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80094de: e128 b.n 8009732 80094e0: 2340 movs r3, #64 @ 0x40 80094e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80094e6: e124 b.n 8009732 80094e8: 2380 movs r3, #128 @ 0x80 80094ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80094ee: e120 b.n 8009732 80094f0: 697b ldr r3, [r7, #20] 80094f2: 681b ldr r3, [r3, #0] 80094f4: 4acb ldr r2, [pc, #812] @ (8009824 ) 80094f6: 4293 cmp r3, r2 80094f8: d176 bne.n 80095e8 80094fa: 4bcb ldr r3, [pc, #812] @ (8009828 ) 80094fc: 6d5b ldr r3, [r3, #84] @ 0x54 80094fe: f003 0338 and.w r3, r3, #56 @ 0x38 8009502: 2b28 cmp r3, #40 @ 0x28 8009504: d86c bhi.n 80095e0 8009506: a201 add r2, pc, #4 @ (adr r2, 800950c ) 8009508: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800950c: 080095b1 .word 0x080095b1 8009510: 080095e1 .word 0x080095e1 8009514: 080095e1 .word 0x080095e1 8009518: 080095e1 .word 0x080095e1 800951c: 080095e1 .word 0x080095e1 8009520: 080095e1 .word 0x080095e1 8009524: 080095e1 .word 0x080095e1 8009528: 080095e1 .word 0x080095e1 800952c: 080095b9 .word 0x080095b9 8009530: 080095e1 .word 0x080095e1 8009534: 080095e1 .word 0x080095e1 8009538: 080095e1 .word 0x080095e1 800953c: 080095e1 .word 0x080095e1 8009540: 080095e1 .word 0x080095e1 8009544: 080095e1 .word 0x080095e1 8009548: 080095e1 .word 0x080095e1 800954c: 080095c1 .word 0x080095c1 8009550: 080095e1 .word 0x080095e1 8009554: 080095e1 .word 0x080095e1 8009558: 080095e1 .word 0x080095e1 800955c: 080095e1 .word 0x080095e1 8009560: 080095e1 .word 0x080095e1 8009564: 080095e1 .word 0x080095e1 8009568: 080095e1 .word 0x080095e1 800956c: 080095c9 .word 0x080095c9 8009570: 080095e1 .word 0x080095e1 8009574: 080095e1 .word 0x080095e1 8009578: 080095e1 .word 0x080095e1 800957c: 080095e1 .word 0x080095e1 8009580: 080095e1 .word 0x080095e1 8009584: 080095e1 .word 0x080095e1 8009588: 080095e1 .word 0x080095e1 800958c: 080095d1 .word 0x080095d1 8009590: 080095e1 .word 0x080095e1 8009594: 080095e1 .word 0x080095e1 8009598: 080095e1 .word 0x080095e1 800959c: 080095e1 .word 0x080095e1 80095a0: 080095e1 .word 0x080095e1 80095a4: 080095e1 .word 0x080095e1 80095a8: 080095e1 .word 0x080095e1 80095ac: 080095d9 .word 0x080095d9 80095b0: 2301 movs r3, #1 80095b2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80095b6: e0bc b.n 8009732 80095b8: 2304 movs r3, #4 80095ba: f887 3043 strb.w r3, [r7, #67] @ 0x43 80095be: e0b8 b.n 8009732 80095c0: 2308 movs r3, #8 80095c2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80095c6: e0b4 b.n 8009732 80095c8: 2310 movs r3, #16 80095ca: f887 3043 strb.w r3, [r7, #67] @ 0x43 80095ce: e0b0 b.n 8009732 80095d0: 2320 movs r3, #32 80095d2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80095d6: e0ac b.n 8009732 80095d8: 2340 movs r3, #64 @ 0x40 80095da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80095de: e0a8 b.n 8009732 80095e0: 2380 movs r3, #128 @ 0x80 80095e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80095e6: e0a4 b.n 8009732 80095e8: 697b ldr r3, [r7, #20] 80095ea: 681b ldr r3, [r3, #0] 80095ec: 4a8f ldr r2, [pc, #572] @ (800982c ) 80095ee: 4293 cmp r3, r2 80095f0: d130 bne.n 8009654 80095f2: 4b8d ldr r3, [pc, #564] @ (8009828 ) 80095f4: 6d5b ldr r3, [r3, #84] @ 0x54 80095f6: f003 0307 and.w r3, r3, #7 80095fa: 2b05 cmp r3, #5 80095fc: d826 bhi.n 800964c 80095fe: a201 add r2, pc, #4 @ (adr r2, 8009604 ) 8009600: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009604: 0800961d .word 0x0800961d 8009608: 08009625 .word 0x08009625 800960c: 0800962d .word 0x0800962d 8009610: 08009635 .word 0x08009635 8009614: 0800963d .word 0x0800963d 8009618: 08009645 .word 0x08009645 800961c: 2300 movs r3, #0 800961e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009622: e086 b.n 8009732 8009624: 2304 movs r3, #4 8009626: f887 3043 strb.w r3, [r7, #67] @ 0x43 800962a: e082 b.n 8009732 800962c: 2308 movs r3, #8 800962e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009632: e07e b.n 8009732 8009634: 2310 movs r3, #16 8009636: f887 3043 strb.w r3, [r7, #67] @ 0x43 800963a: e07a b.n 8009732 800963c: 2320 movs r3, #32 800963e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009642: e076 b.n 8009732 8009644: 2340 movs r3, #64 @ 0x40 8009646: f887 3043 strb.w r3, [r7, #67] @ 0x43 800964a: e072 b.n 8009732 800964c: 2380 movs r3, #128 @ 0x80 800964e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009652: e06e b.n 8009732 8009654: 697b ldr r3, [r7, #20] 8009656: 681b ldr r3, [r3, #0] 8009658: 4a75 ldr r2, [pc, #468] @ (8009830 ) 800965a: 4293 cmp r3, r2 800965c: d130 bne.n 80096c0 800965e: 4b72 ldr r3, [pc, #456] @ (8009828 ) 8009660: 6d5b ldr r3, [r3, #84] @ 0x54 8009662: f003 0307 and.w r3, r3, #7 8009666: 2b05 cmp r3, #5 8009668: d826 bhi.n 80096b8 800966a: a201 add r2, pc, #4 @ (adr r2, 8009670 ) 800966c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009670: 08009689 .word 0x08009689 8009674: 08009691 .word 0x08009691 8009678: 08009699 .word 0x08009699 800967c: 080096a1 .word 0x080096a1 8009680: 080096a9 .word 0x080096a9 8009684: 080096b1 .word 0x080096b1 8009688: 2300 movs r3, #0 800968a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800968e: e050 b.n 8009732 8009690: 2304 movs r3, #4 8009692: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009696: e04c b.n 8009732 8009698: 2308 movs r3, #8 800969a: f887 3043 strb.w r3, [r7, #67] @ 0x43 800969e: e048 b.n 8009732 80096a0: 2310 movs r3, #16 80096a2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80096a6: e044 b.n 8009732 80096a8: 2320 movs r3, #32 80096aa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80096ae: e040 b.n 8009732 80096b0: 2340 movs r3, #64 @ 0x40 80096b2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80096b6: e03c b.n 8009732 80096b8: 2380 movs r3, #128 @ 0x80 80096ba: f887 3043 strb.w r3, [r7, #67] @ 0x43 80096be: e038 b.n 8009732 80096c0: 697b ldr r3, [r7, #20] 80096c2: 681b ldr r3, [r3, #0] 80096c4: 4a5b ldr r2, [pc, #364] @ (8009834 ) 80096c6: 4293 cmp r3, r2 80096c8: d130 bne.n 800972c 80096ca: 4b57 ldr r3, [pc, #348] @ (8009828 ) 80096cc: 6d9b ldr r3, [r3, #88] @ 0x58 80096ce: f003 0307 and.w r3, r3, #7 80096d2: 2b05 cmp r3, #5 80096d4: d826 bhi.n 8009724 80096d6: a201 add r2, pc, #4 @ (adr r2, 80096dc ) 80096d8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80096dc: 080096f5 .word 0x080096f5 80096e0: 080096fd .word 0x080096fd 80096e4: 08009705 .word 0x08009705 80096e8: 0800970d .word 0x0800970d 80096ec: 08009715 .word 0x08009715 80096f0: 0800971d .word 0x0800971d 80096f4: 2302 movs r3, #2 80096f6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80096fa: e01a b.n 8009732 80096fc: 2304 movs r3, #4 80096fe: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009702: e016 b.n 8009732 8009704: 2308 movs r3, #8 8009706: f887 3043 strb.w r3, [r7, #67] @ 0x43 800970a: e012 b.n 8009732 800970c: 2310 movs r3, #16 800970e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009712: e00e b.n 8009732 8009714: 2320 movs r3, #32 8009716: f887 3043 strb.w r3, [r7, #67] @ 0x43 800971a: e00a b.n 8009732 800971c: 2340 movs r3, #64 @ 0x40 800971e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8009722: e006 b.n 8009732 8009724: 2380 movs r3, #128 @ 0x80 8009726: f887 3043 strb.w r3, [r7, #67] @ 0x43 800972a: e002 b.n 8009732 800972c: 2380 movs r3, #128 @ 0x80 800972e: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 8009732: 697b ldr r3, [r7, #20] 8009734: 681b ldr r3, [r3, #0] 8009736: 4a3f ldr r2, [pc, #252] @ (8009834 ) 8009738: 4293 cmp r3, r2 800973a: f040 80f8 bne.w 800992e { /* Retrieve frequency clock */ switch (clocksource) 800973e: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8009742: 2b20 cmp r3, #32 8009744: dc46 bgt.n 80097d4 8009746: 2b02 cmp r3, #2 8009748: f2c0 8082 blt.w 8009850 800974c: 3b02 subs r3, #2 800974e: 2b1e cmp r3, #30 8009750: d87e bhi.n 8009850 8009752: a201 add r2, pc, #4 @ (adr r2, 8009758 ) 8009754: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009758: 080097db .word 0x080097db 800975c: 08009851 .word 0x08009851 8009760: 080097e3 .word 0x080097e3 8009764: 08009851 .word 0x08009851 8009768: 08009851 .word 0x08009851 800976c: 08009851 .word 0x08009851 8009770: 080097f3 .word 0x080097f3 8009774: 08009851 .word 0x08009851 8009778: 08009851 .word 0x08009851 800977c: 08009851 .word 0x08009851 8009780: 08009851 .word 0x08009851 8009784: 08009851 .word 0x08009851 8009788: 08009851 .word 0x08009851 800978c: 08009851 .word 0x08009851 8009790: 08009803 .word 0x08009803 8009794: 08009851 .word 0x08009851 8009798: 08009851 .word 0x08009851 800979c: 08009851 .word 0x08009851 80097a0: 08009851 .word 0x08009851 80097a4: 08009851 .word 0x08009851 80097a8: 08009851 .word 0x08009851 80097ac: 08009851 .word 0x08009851 80097b0: 08009851 .word 0x08009851 80097b4: 08009851 .word 0x08009851 80097b8: 08009851 .word 0x08009851 80097bc: 08009851 .word 0x08009851 80097c0: 08009851 .word 0x08009851 80097c4: 08009851 .word 0x08009851 80097c8: 08009851 .word 0x08009851 80097cc: 08009851 .word 0x08009851 80097d0: 08009843 .word 0x08009843 80097d4: 2b40 cmp r3, #64 @ 0x40 80097d6: d037 beq.n 8009848 80097d8: e03a b.n 8009850 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 80097da: f7fe f8dd bl 8007998 80097de: 63f8 str r0, [r7, #60] @ 0x3c break; 80097e0: e03c b.n 800985c case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80097e2: f107 0324 add.w r3, r7, #36 @ 0x24 80097e6: 4618 mov r0, r3 80097e8: f7fe f8ec bl 80079c4 pclk = pll2_clocks.PLL2_Q_Frequency; 80097ec: 6abb ldr r3, [r7, #40] @ 0x28 80097ee: 63fb str r3, [r7, #60] @ 0x3c break; 80097f0: e034 b.n 800985c case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80097f2: f107 0318 add.w r3, r7, #24 80097f6: 4618 mov r0, r3 80097f8: f7fe fa38 bl 8007c6c pclk = pll3_clocks.PLL3_Q_Frequency; 80097fc: 69fb ldr r3, [r7, #28] 80097fe: 63fb str r3, [r7, #60] @ 0x3c break; 8009800: e02c b.n 800985c case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8009802: 4b09 ldr r3, [pc, #36] @ (8009828 ) 8009804: 681b ldr r3, [r3, #0] 8009806: f003 0320 and.w r3, r3, #32 800980a: 2b00 cmp r3, #0 800980c: d016 beq.n 800983c { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 800980e: 4b06 ldr r3, [pc, #24] @ (8009828 ) 8009810: 681b ldr r3, [r3, #0] 8009812: 08db lsrs r3, r3, #3 8009814: f003 0303 and.w r3, r3, #3 8009818: 4a07 ldr r2, [pc, #28] @ (8009838 ) 800981a: fa22 f303 lsr.w r3, r2, r3 800981e: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8009820: e01c b.n 800985c 8009822: bf00 nop 8009824: 40011400 .word 0x40011400 8009828: 58024400 .word 0x58024400 800982c: 40007800 .word 0x40007800 8009830: 40007c00 .word 0x40007c00 8009834: 58000c00 .word 0x58000c00 8009838: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 800983c: 4b9d ldr r3, [pc, #628] @ (8009ab4 ) 800983e: 63fb str r3, [r7, #60] @ 0x3c break; 8009840: e00c b.n 800985c case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8009842: 4b9d ldr r3, [pc, #628] @ (8009ab8 ) 8009844: 63fb str r3, [r7, #60] @ 0x3c break; 8009846: e009 b.n 800985c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8009848: f44f 4300 mov.w r3, #32768 @ 0x8000 800984c: 63fb str r3, [r7, #60] @ 0x3c break; 800984e: e005 b.n 800985c default: pclk = 0U; 8009850: 2300 movs r3, #0 8009852: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8009854: 2301 movs r3, #1 8009856: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 800985a: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 800985c: 6bfb ldr r3, [r7, #60] @ 0x3c 800985e: 2b00 cmp r3, #0 8009860: f000 81de beq.w 8009c20 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 8009864: 697b ldr r3, [r7, #20] 8009866: 6a5b ldr r3, [r3, #36] @ 0x24 8009868: 4a94 ldr r2, [pc, #592] @ (8009abc ) 800986a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 800986e: 461a mov r2, r3 8009870: 6bfb ldr r3, [r7, #60] @ 0x3c 8009872: fbb3 f3f2 udiv r3, r3, r2 8009876: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8009878: 697b ldr r3, [r7, #20] 800987a: 685a ldr r2, [r3, #4] 800987c: 4613 mov r3, r2 800987e: 005b lsls r3, r3, #1 8009880: 4413 add r3, r2 8009882: 6b3a ldr r2, [r7, #48] @ 0x30 8009884: 429a cmp r2, r3 8009886: d305 bcc.n 8009894 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8009888: 697b ldr r3, [r7, #20] 800988a: 685b ldr r3, [r3, #4] 800988c: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 800988e: 6b3a ldr r2, [r7, #48] @ 0x30 8009890: 429a cmp r2, r3 8009892: d903 bls.n 800989c { ret = HAL_ERROR; 8009894: 2301 movs r3, #1 8009896: f887 3042 strb.w r3, [r7, #66] @ 0x42 800989a: e1c1 b.n 8009c20 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 800989c: 6bfb ldr r3, [r7, #60] @ 0x3c 800989e: 2200 movs r2, #0 80098a0: 60bb str r3, [r7, #8] 80098a2: 60fa str r2, [r7, #12] 80098a4: 697b ldr r3, [r7, #20] 80098a6: 6a5b ldr r3, [r3, #36] @ 0x24 80098a8: 4a84 ldr r2, [pc, #528] @ (8009abc ) 80098aa: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80098ae: b29b uxth r3, r3 80098b0: 2200 movs r2, #0 80098b2: 603b str r3, [r7, #0] 80098b4: 607a str r2, [r7, #4] 80098b6: e9d7 2300 ldrd r2, r3, [r7] 80098ba: e9d7 0102 ldrd r0, r1, [r7, #8] 80098be: f7f6 fd5f bl 8000380 <__aeabi_uldivmod> 80098c2: 4602 mov r2, r0 80098c4: 460b mov r3, r1 80098c6: 4610 mov r0, r2 80098c8: 4619 mov r1, r3 80098ca: f04f 0200 mov.w r2, #0 80098ce: f04f 0300 mov.w r3, #0 80098d2: 020b lsls r3, r1, #8 80098d4: ea43 6310 orr.w r3, r3, r0, lsr #24 80098d8: 0202 lsls r2, r0, #8 80098da: 6979 ldr r1, [r7, #20] 80098dc: 6849 ldr r1, [r1, #4] 80098de: 0849 lsrs r1, r1, #1 80098e0: 2000 movs r0, #0 80098e2: 460c mov r4, r1 80098e4: 4605 mov r5, r0 80098e6: eb12 0804 adds.w r8, r2, r4 80098ea: eb43 0905 adc.w r9, r3, r5 80098ee: 697b ldr r3, [r7, #20] 80098f0: 685b ldr r3, [r3, #4] 80098f2: 2200 movs r2, #0 80098f4: 469a mov sl, r3 80098f6: 4693 mov fp, r2 80098f8: 4652 mov r2, sl 80098fa: 465b mov r3, fp 80098fc: 4640 mov r0, r8 80098fe: 4649 mov r1, r9 8009900: f7f6 fd3e bl 8000380 <__aeabi_uldivmod> 8009904: 4602 mov r2, r0 8009906: 460b mov r3, r1 8009908: 4613 mov r3, r2 800990a: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 800990c: 6bbb ldr r3, [r7, #56] @ 0x38 800990e: f5b3 7f40 cmp.w r3, #768 @ 0x300 8009912: d308 bcc.n 8009926 8009914: 6bbb ldr r3, [r7, #56] @ 0x38 8009916: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800991a: d204 bcs.n 8009926 { huart->Instance->BRR = usartdiv; 800991c: 697b ldr r3, [r7, #20] 800991e: 681b ldr r3, [r3, #0] 8009920: 6bba ldr r2, [r7, #56] @ 0x38 8009922: 60da str r2, [r3, #12] 8009924: e17c b.n 8009c20 } else { ret = HAL_ERROR; 8009926: 2301 movs r3, #1 8009928: f887 3042 strb.w r3, [r7, #66] @ 0x42 800992c: e178 b.n 8009c20 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 800992e: 697b ldr r3, [r7, #20] 8009930: 69db ldr r3, [r3, #28] 8009932: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8009936: f040 80c5 bne.w 8009ac4 { switch (clocksource) 800993a: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 800993e: 2b20 cmp r3, #32 8009940: dc48 bgt.n 80099d4 8009942: 2b00 cmp r3, #0 8009944: db7b blt.n 8009a3e 8009946: 2b20 cmp r3, #32 8009948: d879 bhi.n 8009a3e 800994a: a201 add r2, pc, #4 @ (adr r2, 8009950 ) 800994c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009950: 080099db .word 0x080099db 8009954: 080099e3 .word 0x080099e3 8009958: 08009a3f .word 0x08009a3f 800995c: 08009a3f .word 0x08009a3f 8009960: 080099eb .word 0x080099eb 8009964: 08009a3f .word 0x08009a3f 8009968: 08009a3f .word 0x08009a3f 800996c: 08009a3f .word 0x08009a3f 8009970: 080099fb .word 0x080099fb 8009974: 08009a3f .word 0x08009a3f 8009978: 08009a3f .word 0x08009a3f 800997c: 08009a3f .word 0x08009a3f 8009980: 08009a3f .word 0x08009a3f 8009984: 08009a3f .word 0x08009a3f 8009988: 08009a3f .word 0x08009a3f 800998c: 08009a3f .word 0x08009a3f 8009990: 08009a0b .word 0x08009a0b 8009994: 08009a3f .word 0x08009a3f 8009998: 08009a3f .word 0x08009a3f 800999c: 08009a3f .word 0x08009a3f 80099a0: 08009a3f .word 0x08009a3f 80099a4: 08009a3f .word 0x08009a3f 80099a8: 08009a3f .word 0x08009a3f 80099ac: 08009a3f .word 0x08009a3f 80099b0: 08009a3f .word 0x08009a3f 80099b4: 08009a3f .word 0x08009a3f 80099b8: 08009a3f .word 0x08009a3f 80099bc: 08009a3f .word 0x08009a3f 80099c0: 08009a3f .word 0x08009a3f 80099c4: 08009a3f .word 0x08009a3f 80099c8: 08009a3f .word 0x08009a3f 80099cc: 08009a3f .word 0x08009a3f 80099d0: 08009a31 .word 0x08009a31 80099d4: 2b40 cmp r3, #64 @ 0x40 80099d6: d02e beq.n 8009a36 80099d8: e031 b.n 8009a3e { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80099da: f7fc fd81 bl 80064e0 80099de: 63f8 str r0, [r7, #60] @ 0x3c break; 80099e0: e033 b.n 8009a4a case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 80099e2: f7fc fd93 bl 800650c 80099e6: 63f8 str r0, [r7, #60] @ 0x3c break; 80099e8: e02f b.n 8009a4a case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80099ea: f107 0324 add.w r3, r7, #36 @ 0x24 80099ee: 4618 mov r0, r3 80099f0: f7fd ffe8 bl 80079c4 pclk = pll2_clocks.PLL2_Q_Frequency; 80099f4: 6abb ldr r3, [r7, #40] @ 0x28 80099f6: 63fb str r3, [r7, #60] @ 0x3c break; 80099f8: e027 b.n 8009a4a case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 80099fa: f107 0318 add.w r3, r7, #24 80099fe: 4618 mov r0, r3 8009a00: f7fe f934 bl 8007c6c pclk = pll3_clocks.PLL3_Q_Frequency; 8009a04: 69fb ldr r3, [r7, #28] 8009a06: 63fb str r3, [r7, #60] @ 0x3c break; 8009a08: e01f b.n 8009a4a case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8009a0a: 4b2d ldr r3, [pc, #180] @ (8009ac0 ) 8009a0c: 681b ldr r3, [r3, #0] 8009a0e: f003 0320 and.w r3, r3, #32 8009a12: 2b00 cmp r3, #0 8009a14: d009 beq.n 8009a2a { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8009a16: 4b2a ldr r3, [pc, #168] @ (8009ac0 ) 8009a18: 681b ldr r3, [r3, #0] 8009a1a: 08db lsrs r3, r3, #3 8009a1c: f003 0303 and.w r3, r3, #3 8009a20: 4a24 ldr r2, [pc, #144] @ (8009ab4 ) 8009a22: fa22 f303 lsr.w r3, r2, r3 8009a26: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8009a28: e00f b.n 8009a4a pclk = (uint32_t) HSI_VALUE; 8009a2a: 4b22 ldr r3, [pc, #136] @ (8009ab4 ) 8009a2c: 63fb str r3, [r7, #60] @ 0x3c break; 8009a2e: e00c b.n 8009a4a case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8009a30: 4b21 ldr r3, [pc, #132] @ (8009ab8 ) 8009a32: 63fb str r3, [r7, #60] @ 0x3c break; 8009a34: e009 b.n 8009a4a case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8009a36: f44f 4300 mov.w r3, #32768 @ 0x8000 8009a3a: 63fb str r3, [r7, #60] @ 0x3c break; 8009a3c: e005 b.n 8009a4a default: pclk = 0U; 8009a3e: 2300 movs r3, #0 8009a40: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8009a42: 2301 movs r3, #1 8009a44: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8009a48: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8009a4a: 6bfb ldr r3, [r7, #60] @ 0x3c 8009a4c: 2b00 cmp r3, #0 8009a4e: f000 80e7 beq.w 8009c20 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8009a52: 697b ldr r3, [r7, #20] 8009a54: 6a5b ldr r3, [r3, #36] @ 0x24 8009a56: 4a19 ldr r2, [pc, #100] @ (8009abc ) 8009a58: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8009a5c: 461a mov r2, r3 8009a5e: 6bfb ldr r3, [r7, #60] @ 0x3c 8009a60: fbb3 f3f2 udiv r3, r3, r2 8009a64: 005a lsls r2, r3, #1 8009a66: 697b ldr r3, [r7, #20] 8009a68: 685b ldr r3, [r3, #4] 8009a6a: 085b lsrs r3, r3, #1 8009a6c: 441a add r2, r3 8009a6e: 697b ldr r3, [r7, #20] 8009a70: 685b ldr r3, [r3, #4] 8009a72: fbb2 f3f3 udiv r3, r2, r3 8009a76: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8009a78: 6bbb ldr r3, [r7, #56] @ 0x38 8009a7a: 2b0f cmp r3, #15 8009a7c: d916 bls.n 8009aac 8009a7e: 6bbb ldr r3, [r7, #56] @ 0x38 8009a80: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8009a84: d212 bcs.n 8009aac { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8009a86: 6bbb ldr r3, [r7, #56] @ 0x38 8009a88: b29b uxth r3, r3 8009a8a: f023 030f bic.w r3, r3, #15 8009a8e: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8009a90: 6bbb ldr r3, [r7, #56] @ 0x38 8009a92: 085b lsrs r3, r3, #1 8009a94: b29b uxth r3, r3 8009a96: f003 0307 and.w r3, r3, #7 8009a9a: b29a uxth r2, r3 8009a9c: 8efb ldrh r3, [r7, #54] @ 0x36 8009a9e: 4313 orrs r3, r2 8009aa0: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 8009aa2: 697b ldr r3, [r7, #20] 8009aa4: 681b ldr r3, [r3, #0] 8009aa6: 8efa ldrh r2, [r7, #54] @ 0x36 8009aa8: 60da str r2, [r3, #12] 8009aaa: e0b9 b.n 8009c20 } else { ret = HAL_ERROR; 8009aac: 2301 movs r3, #1 8009aae: f887 3042 strb.w r3, [r7, #66] @ 0x42 8009ab2: e0b5 b.n 8009c20 8009ab4: 03d09000 .word 0x03d09000 8009ab8: 003d0900 .word 0x003d0900 8009abc: 080100c8 .word 0x080100c8 8009ac0: 58024400 .word 0x58024400 } } } else { switch (clocksource) 8009ac4: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8009ac8: 2b20 cmp r3, #32 8009aca: dc49 bgt.n 8009b60 8009acc: 2b00 cmp r3, #0 8009ace: db7c blt.n 8009bca 8009ad0: 2b20 cmp r3, #32 8009ad2: d87a bhi.n 8009bca 8009ad4: a201 add r2, pc, #4 @ (adr r2, 8009adc ) 8009ad6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8009ada: bf00 nop 8009adc: 08009b67 .word 0x08009b67 8009ae0: 08009b6f .word 0x08009b6f 8009ae4: 08009bcb .word 0x08009bcb 8009ae8: 08009bcb .word 0x08009bcb 8009aec: 08009b77 .word 0x08009b77 8009af0: 08009bcb .word 0x08009bcb 8009af4: 08009bcb .word 0x08009bcb 8009af8: 08009bcb .word 0x08009bcb 8009afc: 08009b87 .word 0x08009b87 8009b00: 08009bcb .word 0x08009bcb 8009b04: 08009bcb .word 0x08009bcb 8009b08: 08009bcb .word 0x08009bcb 8009b0c: 08009bcb .word 0x08009bcb 8009b10: 08009bcb .word 0x08009bcb 8009b14: 08009bcb .word 0x08009bcb 8009b18: 08009bcb .word 0x08009bcb 8009b1c: 08009b97 .word 0x08009b97 8009b20: 08009bcb .word 0x08009bcb 8009b24: 08009bcb .word 0x08009bcb 8009b28: 08009bcb .word 0x08009bcb 8009b2c: 08009bcb .word 0x08009bcb 8009b30: 08009bcb .word 0x08009bcb 8009b34: 08009bcb .word 0x08009bcb 8009b38: 08009bcb .word 0x08009bcb 8009b3c: 08009bcb .word 0x08009bcb 8009b40: 08009bcb .word 0x08009bcb 8009b44: 08009bcb .word 0x08009bcb 8009b48: 08009bcb .word 0x08009bcb 8009b4c: 08009bcb .word 0x08009bcb 8009b50: 08009bcb .word 0x08009bcb 8009b54: 08009bcb .word 0x08009bcb 8009b58: 08009bcb .word 0x08009bcb 8009b5c: 08009bbd .word 0x08009bbd 8009b60: 2b40 cmp r3, #64 @ 0x40 8009b62: d02e beq.n 8009bc2 8009b64: e031 b.n 8009bca { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8009b66: f7fc fcbb bl 80064e0 8009b6a: 63f8 str r0, [r7, #60] @ 0x3c break; 8009b6c: e033 b.n 8009bd6 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8009b6e: f7fc fccd bl 800650c 8009b72: 63f8 str r0, [r7, #60] @ 0x3c break; 8009b74: e02f b.n 8009bd6 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8009b76: f107 0324 add.w r3, r7, #36 @ 0x24 8009b7a: 4618 mov r0, r3 8009b7c: f7fd ff22 bl 80079c4 pclk = pll2_clocks.PLL2_Q_Frequency; 8009b80: 6abb ldr r3, [r7, #40] @ 0x28 8009b82: 63fb str r3, [r7, #60] @ 0x3c break; 8009b84: e027 b.n 8009bd6 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8009b86: f107 0318 add.w r3, r7, #24 8009b8a: 4618 mov r0, r3 8009b8c: f7fe f86e bl 8007c6c pclk = pll3_clocks.PLL3_Q_Frequency; 8009b90: 69fb ldr r3, [r7, #28] 8009b92: 63fb str r3, [r7, #60] @ 0x3c break; 8009b94: e01f b.n 8009bd6 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8009b96: 4b2d ldr r3, [pc, #180] @ (8009c4c ) 8009b98: 681b ldr r3, [r3, #0] 8009b9a: f003 0320 and.w r3, r3, #32 8009b9e: 2b00 cmp r3, #0 8009ba0: d009 beq.n 8009bb6 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8009ba2: 4b2a ldr r3, [pc, #168] @ (8009c4c ) 8009ba4: 681b ldr r3, [r3, #0] 8009ba6: 08db lsrs r3, r3, #3 8009ba8: f003 0303 and.w r3, r3, #3 8009bac: 4a28 ldr r2, [pc, #160] @ (8009c50 ) 8009bae: fa22 f303 lsr.w r3, r2, r3 8009bb2: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8009bb4: e00f b.n 8009bd6 pclk = (uint32_t) HSI_VALUE; 8009bb6: 4b26 ldr r3, [pc, #152] @ (8009c50 ) 8009bb8: 63fb str r3, [r7, #60] @ 0x3c break; 8009bba: e00c b.n 8009bd6 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8009bbc: 4b25 ldr r3, [pc, #148] @ (8009c54 ) 8009bbe: 63fb str r3, [r7, #60] @ 0x3c break; 8009bc0: e009 b.n 8009bd6 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8009bc2: f44f 4300 mov.w r3, #32768 @ 0x8000 8009bc6: 63fb str r3, [r7, #60] @ 0x3c break; 8009bc8: e005 b.n 8009bd6 default: pclk = 0U; 8009bca: 2300 movs r3, #0 8009bcc: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8009bce: 2301 movs r3, #1 8009bd0: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8009bd4: bf00 nop } if (pclk != 0U) 8009bd6: 6bfb ldr r3, [r7, #60] @ 0x3c 8009bd8: 2b00 cmp r3, #0 8009bda: d021 beq.n 8009c20 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8009bdc: 697b ldr r3, [r7, #20] 8009bde: 6a5b ldr r3, [r3, #36] @ 0x24 8009be0: 4a1d ldr r2, [pc, #116] @ (8009c58 ) 8009be2: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8009be6: 461a mov r2, r3 8009be8: 6bfb ldr r3, [r7, #60] @ 0x3c 8009bea: fbb3 f2f2 udiv r2, r3, r2 8009bee: 697b ldr r3, [r7, #20] 8009bf0: 685b ldr r3, [r3, #4] 8009bf2: 085b lsrs r3, r3, #1 8009bf4: 441a add r2, r3 8009bf6: 697b ldr r3, [r7, #20] 8009bf8: 685b ldr r3, [r3, #4] 8009bfa: fbb2 f3f3 udiv r3, r2, r3 8009bfe: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8009c00: 6bbb ldr r3, [r7, #56] @ 0x38 8009c02: 2b0f cmp r3, #15 8009c04: d909 bls.n 8009c1a 8009c06: 6bbb ldr r3, [r7, #56] @ 0x38 8009c08: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8009c0c: d205 bcs.n 8009c1a { huart->Instance->BRR = (uint16_t)usartdiv; 8009c0e: 6bbb ldr r3, [r7, #56] @ 0x38 8009c10: b29a uxth r2, r3 8009c12: 697b ldr r3, [r7, #20] 8009c14: 681b ldr r3, [r3, #0] 8009c16: 60da str r2, [r3, #12] 8009c18: e002 b.n 8009c20 } else { ret = HAL_ERROR; 8009c1a: 2301 movs r3, #1 8009c1c: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8009c20: 697b ldr r3, [r7, #20] 8009c22: 2201 movs r2, #1 8009c24: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 8009c28: 697b ldr r3, [r7, #20] 8009c2a: 2201 movs r2, #1 8009c2c: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 8009c30: 697b ldr r3, [r7, #20] 8009c32: 2200 movs r2, #0 8009c34: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8009c36: 697b ldr r3, [r7, #20] 8009c38: 2200 movs r2, #0 8009c3a: 679a str r2, [r3, #120] @ 0x78 return ret; 8009c3c: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 8009c40: 4618 mov r0, r3 8009c42: 3748 adds r7, #72 @ 0x48 8009c44: 46bd mov sp, r7 8009c46: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8009c4a: bf00 nop 8009c4c: 58024400 .word 0x58024400 8009c50: 03d09000 .word 0x03d09000 8009c54: 003d0900 .word 0x003d0900 8009c58: 080100c8 .word 0x080100c8 08009c5c : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8009c5c: b480 push {r7} 8009c5e: b083 sub sp, #12 8009c60: af00 add r7, sp, #0 8009c62: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8009c64: 687b ldr r3, [r7, #4] 8009c66: 6a9b ldr r3, [r3, #40] @ 0x28 8009c68: f003 0308 and.w r3, r3, #8 8009c6c: 2b00 cmp r3, #0 8009c6e: d00a beq.n 8009c86 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8009c70: 687b ldr r3, [r7, #4] 8009c72: 681b ldr r3, [r3, #0] 8009c74: 685b ldr r3, [r3, #4] 8009c76: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8009c7a: 687b ldr r3, [r7, #4] 8009c7c: 6b9a ldr r2, [r3, #56] @ 0x38 8009c7e: 687b ldr r3, [r7, #4] 8009c80: 681b ldr r3, [r3, #0] 8009c82: 430a orrs r2, r1 8009c84: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8009c86: 687b ldr r3, [r7, #4] 8009c88: 6a9b ldr r3, [r3, #40] @ 0x28 8009c8a: f003 0301 and.w r3, r3, #1 8009c8e: 2b00 cmp r3, #0 8009c90: d00a beq.n 8009ca8 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8009c92: 687b ldr r3, [r7, #4] 8009c94: 681b ldr r3, [r3, #0] 8009c96: 685b ldr r3, [r3, #4] 8009c98: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8009c9c: 687b ldr r3, [r7, #4] 8009c9e: 6ada ldr r2, [r3, #44] @ 0x2c 8009ca0: 687b ldr r3, [r7, #4] 8009ca2: 681b ldr r3, [r3, #0] 8009ca4: 430a orrs r2, r1 8009ca6: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8009ca8: 687b ldr r3, [r7, #4] 8009caa: 6a9b ldr r3, [r3, #40] @ 0x28 8009cac: f003 0302 and.w r3, r3, #2 8009cb0: 2b00 cmp r3, #0 8009cb2: d00a beq.n 8009cca { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8009cb4: 687b ldr r3, [r7, #4] 8009cb6: 681b ldr r3, [r3, #0] 8009cb8: 685b ldr r3, [r3, #4] 8009cba: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8009cbe: 687b ldr r3, [r7, #4] 8009cc0: 6b1a ldr r2, [r3, #48] @ 0x30 8009cc2: 687b ldr r3, [r7, #4] 8009cc4: 681b ldr r3, [r3, #0] 8009cc6: 430a orrs r2, r1 8009cc8: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8009cca: 687b ldr r3, [r7, #4] 8009ccc: 6a9b ldr r3, [r3, #40] @ 0x28 8009cce: f003 0304 and.w r3, r3, #4 8009cd2: 2b00 cmp r3, #0 8009cd4: d00a beq.n 8009cec { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8009cd6: 687b ldr r3, [r7, #4] 8009cd8: 681b ldr r3, [r3, #0] 8009cda: 685b ldr r3, [r3, #4] 8009cdc: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: 6b5a ldr r2, [r3, #52] @ 0x34 8009ce4: 687b ldr r3, [r7, #4] 8009ce6: 681b ldr r3, [r3, #0] 8009ce8: 430a orrs r2, r1 8009cea: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8009cec: 687b ldr r3, [r7, #4] 8009cee: 6a9b ldr r3, [r3, #40] @ 0x28 8009cf0: f003 0310 and.w r3, r3, #16 8009cf4: 2b00 cmp r3, #0 8009cf6: d00a beq.n 8009d0e { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8009cf8: 687b ldr r3, [r7, #4] 8009cfa: 681b ldr r3, [r3, #0] 8009cfc: 689b ldr r3, [r3, #8] 8009cfe: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8009d02: 687b ldr r3, [r7, #4] 8009d04: 6bda ldr r2, [r3, #60] @ 0x3c 8009d06: 687b ldr r3, [r7, #4] 8009d08: 681b ldr r3, [r3, #0] 8009d0a: 430a orrs r2, r1 8009d0c: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8009d0e: 687b ldr r3, [r7, #4] 8009d10: 6a9b ldr r3, [r3, #40] @ 0x28 8009d12: f003 0320 and.w r3, r3, #32 8009d16: 2b00 cmp r3, #0 8009d18: d00a beq.n 8009d30 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8009d1a: 687b ldr r3, [r7, #4] 8009d1c: 681b ldr r3, [r3, #0] 8009d1e: 689b ldr r3, [r3, #8] 8009d20: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8009d24: 687b ldr r3, [r7, #4] 8009d26: 6c1a ldr r2, [r3, #64] @ 0x40 8009d28: 687b ldr r3, [r7, #4] 8009d2a: 681b ldr r3, [r3, #0] 8009d2c: 430a orrs r2, r1 8009d2e: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8009d30: 687b ldr r3, [r7, #4] 8009d32: 6a9b ldr r3, [r3, #40] @ 0x28 8009d34: f003 0340 and.w r3, r3, #64 @ 0x40 8009d38: 2b00 cmp r3, #0 8009d3a: d01a beq.n 8009d72 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8009d3c: 687b ldr r3, [r7, #4] 8009d3e: 681b ldr r3, [r3, #0] 8009d40: 685b ldr r3, [r3, #4] 8009d42: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 8009d46: 687b ldr r3, [r7, #4] 8009d48: 6c5a ldr r2, [r3, #68] @ 0x44 8009d4a: 687b ldr r3, [r7, #4] 8009d4c: 681b ldr r3, [r3, #0] 8009d4e: 430a orrs r2, r1 8009d50: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8009d52: 687b ldr r3, [r7, #4] 8009d54: 6c5b ldr r3, [r3, #68] @ 0x44 8009d56: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8009d5a: d10a bne.n 8009d72 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8009d5c: 687b ldr r3, [r7, #4] 8009d5e: 681b ldr r3, [r3, #0] 8009d60: 685b ldr r3, [r3, #4] 8009d62: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 8009d66: 687b ldr r3, [r7, #4] 8009d68: 6c9a ldr r2, [r3, #72] @ 0x48 8009d6a: 687b ldr r3, [r7, #4] 8009d6c: 681b ldr r3, [r3, #0] 8009d6e: 430a orrs r2, r1 8009d70: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8009d72: 687b ldr r3, [r7, #4] 8009d74: 6a9b ldr r3, [r3, #40] @ 0x28 8009d76: f003 0380 and.w r3, r3, #128 @ 0x80 8009d7a: 2b00 cmp r3, #0 8009d7c: d00a beq.n 8009d94 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8009d7e: 687b ldr r3, [r7, #4] 8009d80: 681b ldr r3, [r3, #0] 8009d82: 685b ldr r3, [r3, #4] 8009d84: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8009d88: 687b ldr r3, [r7, #4] 8009d8a: 6cda ldr r2, [r3, #76] @ 0x4c 8009d8c: 687b ldr r3, [r7, #4] 8009d8e: 681b ldr r3, [r3, #0] 8009d90: 430a orrs r2, r1 8009d92: 605a str r2, [r3, #4] } } 8009d94: bf00 nop 8009d96: 370c adds r7, #12 8009d98: 46bd mov sp, r7 8009d9a: f85d 7b04 ldr.w r7, [sp], #4 8009d9e: 4770 bx lr 08009da0 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8009da0: b580 push {r7, lr} 8009da2: b098 sub sp, #96 @ 0x60 8009da4: af02 add r7, sp, #8 8009da6: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8009da8: 687b ldr r3, [r7, #4] 8009daa: 2200 movs r2, #0 8009dac: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8009db0: f7f8 fc56 bl 8002660 8009db4: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8009db6: 687b ldr r3, [r7, #4] 8009db8: 681b ldr r3, [r3, #0] 8009dba: 681b ldr r3, [r3, #0] 8009dbc: f003 0308 and.w r3, r3, #8 8009dc0: 2b08 cmp r3, #8 8009dc2: d12f bne.n 8009e24 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8009dc4: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8009dc8: 9300 str r3, [sp, #0] 8009dca: 6d7b ldr r3, [r7, #84] @ 0x54 8009dcc: 2200 movs r2, #0 8009dce: f44f 1100 mov.w r1, #2097152 @ 0x200000 8009dd2: 6878 ldr r0, [r7, #4] 8009dd4: f000 f88e bl 8009ef4 8009dd8: 4603 mov r3, r0 8009dda: 2b00 cmp r3, #0 8009ddc: d022 beq.n 8009e24 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8009dde: 687b ldr r3, [r7, #4] 8009de0: 681b ldr r3, [r3, #0] 8009de2: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009de4: 6bbb ldr r3, [r7, #56] @ 0x38 8009de6: e853 3f00 ldrex r3, [r3] 8009dea: 637b str r3, [r7, #52] @ 0x34 return(result); 8009dec: 6b7b ldr r3, [r7, #52] @ 0x34 8009dee: f023 0380 bic.w r3, r3, #128 @ 0x80 8009df2: 653b str r3, [r7, #80] @ 0x50 8009df4: 687b ldr r3, [r7, #4] 8009df6: 681b ldr r3, [r3, #0] 8009df8: 461a mov r2, r3 8009dfa: 6d3b ldr r3, [r7, #80] @ 0x50 8009dfc: 647b str r3, [r7, #68] @ 0x44 8009dfe: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8009e00: 6c39 ldr r1, [r7, #64] @ 0x40 8009e02: 6c7a ldr r2, [r7, #68] @ 0x44 8009e04: e841 2300 strex r3, r2, [r1] 8009e08: 63fb str r3, [r7, #60] @ 0x3c return(result); 8009e0a: 6bfb ldr r3, [r7, #60] @ 0x3c 8009e0c: 2b00 cmp r3, #0 8009e0e: d1e6 bne.n 8009dde huart->gState = HAL_UART_STATE_READY; 8009e10: 687b ldr r3, [r7, #4] 8009e12: 2220 movs r2, #32 8009e14: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8009e18: 687b ldr r3, [r7, #4] 8009e1a: 2200 movs r2, #0 8009e1c: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8009e20: 2303 movs r3, #3 8009e22: e063 b.n 8009eec } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8009e24: 687b ldr r3, [r7, #4] 8009e26: 681b ldr r3, [r3, #0] 8009e28: 681b ldr r3, [r3, #0] 8009e2a: f003 0304 and.w r3, r3, #4 8009e2e: 2b04 cmp r3, #4 8009e30: d149 bne.n 8009ec6 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8009e32: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8009e36: 9300 str r3, [sp, #0] 8009e38: 6d7b ldr r3, [r7, #84] @ 0x54 8009e3a: 2200 movs r2, #0 8009e3c: f44f 0180 mov.w r1, #4194304 @ 0x400000 8009e40: 6878 ldr r0, [r7, #4] 8009e42: f000 f857 bl 8009ef4 8009e46: 4603 mov r3, r0 8009e48: 2b00 cmp r3, #0 8009e4a: d03c beq.n 8009ec6 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8009e4c: 687b ldr r3, [r7, #4] 8009e4e: 681b ldr r3, [r3, #0] 8009e50: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009e52: 6a7b ldr r3, [r7, #36] @ 0x24 8009e54: e853 3f00 ldrex r3, [r3] 8009e58: 623b str r3, [r7, #32] return(result); 8009e5a: 6a3b ldr r3, [r7, #32] 8009e5c: f423 7390 bic.w r3, r3, #288 @ 0x120 8009e60: 64fb str r3, [r7, #76] @ 0x4c 8009e62: 687b ldr r3, [r7, #4] 8009e64: 681b ldr r3, [r3, #0] 8009e66: 461a mov r2, r3 8009e68: 6cfb ldr r3, [r7, #76] @ 0x4c 8009e6a: 633b str r3, [r7, #48] @ 0x30 8009e6c: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8009e6e: 6af9 ldr r1, [r7, #44] @ 0x2c 8009e70: 6b3a ldr r2, [r7, #48] @ 0x30 8009e72: e841 2300 strex r3, r2, [r1] 8009e76: 62bb str r3, [r7, #40] @ 0x28 return(result); 8009e78: 6abb ldr r3, [r7, #40] @ 0x28 8009e7a: 2b00 cmp r3, #0 8009e7c: d1e6 bne.n 8009e4c ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8009e7e: 687b ldr r3, [r7, #4] 8009e80: 681b ldr r3, [r3, #0] 8009e82: 3308 adds r3, #8 8009e84: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8009e86: 693b ldr r3, [r7, #16] 8009e88: e853 3f00 ldrex r3, [r3] 8009e8c: 60fb str r3, [r7, #12] return(result); 8009e8e: 68fb ldr r3, [r7, #12] 8009e90: f023 0301 bic.w r3, r3, #1 8009e94: 64bb str r3, [r7, #72] @ 0x48 8009e96: 687b ldr r3, [r7, #4] 8009e98: 681b ldr r3, [r3, #0] 8009e9a: 3308 adds r3, #8 8009e9c: 6cba ldr r2, [r7, #72] @ 0x48 8009e9e: 61fa str r2, [r7, #28] 8009ea0: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8009ea2: 69b9 ldr r1, [r7, #24] 8009ea4: 69fa ldr r2, [r7, #28] 8009ea6: e841 2300 strex r3, r2, [r1] 8009eaa: 617b str r3, [r7, #20] return(result); 8009eac: 697b ldr r3, [r7, #20] 8009eae: 2b00 cmp r3, #0 8009eb0: d1e5 bne.n 8009e7e huart->RxState = HAL_UART_STATE_READY; 8009eb2: 687b ldr r3, [r7, #4] 8009eb4: 2220 movs r2, #32 8009eb6: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8009eba: 687b ldr r3, [r7, #4] 8009ebc: 2200 movs r2, #0 8009ebe: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8009ec2: 2303 movs r3, #3 8009ec4: e012 b.n 8009eec } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8009ec6: 687b ldr r3, [r7, #4] 8009ec8: 2220 movs r2, #32 8009eca: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8009ece: 687b ldr r3, [r7, #4] 8009ed0: 2220 movs r2, #32 8009ed2: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8009ed6: 687b ldr r3, [r7, #4] 8009ed8: 2200 movs r2, #0 8009eda: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8009edc: 687b ldr r3, [r7, #4] 8009ede: 2200 movs r2, #0 8009ee0: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8009ee2: 687b ldr r3, [r7, #4] 8009ee4: 2200 movs r2, #0 8009ee6: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8009eea: 2300 movs r3, #0 } 8009eec: 4618 mov r0, r3 8009eee: 3758 adds r7, #88 @ 0x58 8009ef0: 46bd mov sp, r7 8009ef2: bd80 pop {r7, pc} 08009ef4 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8009ef4: b580 push {r7, lr} 8009ef6: b084 sub sp, #16 8009ef8: af00 add r7, sp, #0 8009efa: 60f8 str r0, [r7, #12] 8009efc: 60b9 str r1, [r7, #8] 8009efe: 603b str r3, [r7, #0] 8009f00: 4613 mov r3, r2 8009f02: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8009f04: e04f b.n 8009fa6 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8009f06: 69bb ldr r3, [r7, #24] 8009f08: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8009f0c: d04b beq.n 8009fa6 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8009f0e: f7f8 fba7 bl 8002660 8009f12: 4602 mov r2, r0 8009f14: 683b ldr r3, [r7, #0] 8009f16: 1ad3 subs r3, r2, r3 8009f18: 69ba ldr r2, [r7, #24] 8009f1a: 429a cmp r2, r3 8009f1c: d302 bcc.n 8009f24 8009f1e: 69bb ldr r3, [r7, #24] 8009f20: 2b00 cmp r3, #0 8009f22: d101 bne.n 8009f28 { return HAL_TIMEOUT; 8009f24: 2303 movs r3, #3 8009f26: e04e b.n 8009fc6 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8009f28: 68fb ldr r3, [r7, #12] 8009f2a: 681b ldr r3, [r3, #0] 8009f2c: 681b ldr r3, [r3, #0] 8009f2e: f003 0304 and.w r3, r3, #4 8009f32: 2b00 cmp r3, #0 8009f34: d037 beq.n 8009fa6 8009f36: 68bb ldr r3, [r7, #8] 8009f38: 2b80 cmp r3, #128 @ 0x80 8009f3a: d034 beq.n 8009fa6 8009f3c: 68bb ldr r3, [r7, #8] 8009f3e: 2b40 cmp r3, #64 @ 0x40 8009f40: d031 beq.n 8009fa6 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8009f42: 68fb ldr r3, [r7, #12] 8009f44: 681b ldr r3, [r3, #0] 8009f46: 69db ldr r3, [r3, #28] 8009f48: f003 0308 and.w r3, r3, #8 8009f4c: 2b08 cmp r3, #8 8009f4e: d110 bne.n 8009f72 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8009f50: 68fb ldr r3, [r7, #12] 8009f52: 681b ldr r3, [r3, #0] 8009f54: 2208 movs r2, #8 8009f56: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8009f58: 68f8 ldr r0, [r7, #12] 8009f5a: f000 f95b bl 800a214 huart->ErrorCode = HAL_UART_ERROR_ORE; 8009f5e: 68fb ldr r3, [r7, #12] 8009f60: 2208 movs r2, #8 8009f62: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8009f66: 68fb ldr r3, [r7, #12] 8009f68: 2200 movs r2, #0 8009f6a: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8009f6e: 2301 movs r3, #1 8009f70: e029 b.n 8009fc6 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8009f72: 68fb ldr r3, [r7, #12] 8009f74: 681b ldr r3, [r3, #0] 8009f76: 69db ldr r3, [r3, #28] 8009f78: f403 6300 and.w r3, r3, #2048 @ 0x800 8009f7c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8009f80: d111 bne.n 8009fa6 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8009f82: 68fb ldr r3, [r7, #12] 8009f84: 681b ldr r3, [r3, #0] 8009f86: f44f 6200 mov.w r2, #2048 @ 0x800 8009f8a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8009f8c: 68f8 ldr r0, [r7, #12] 8009f8e: f000 f941 bl 800a214 huart->ErrorCode = HAL_UART_ERROR_RTO; 8009f92: 68fb ldr r3, [r7, #12] 8009f94: 2220 movs r2, #32 8009f96: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8009f9a: 68fb ldr r3, [r7, #12] 8009f9c: 2200 movs r2, #0 8009f9e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8009fa2: 2303 movs r3, #3 8009fa4: e00f b.n 8009fc6 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8009fa6: 68fb ldr r3, [r7, #12] 8009fa8: 681b ldr r3, [r3, #0] 8009faa: 69da ldr r2, [r3, #28] 8009fac: 68bb ldr r3, [r7, #8] 8009fae: 4013 ands r3, r2 8009fb0: 68ba ldr r2, [r7, #8] 8009fb2: 429a cmp r2, r3 8009fb4: bf0c ite eq 8009fb6: 2301 moveq r3, #1 8009fb8: 2300 movne r3, #0 8009fba: b2db uxtb r3, r3 8009fbc: 461a mov r2, r3 8009fbe: 79fb ldrb r3, [r7, #7] 8009fc0: 429a cmp r2, r3 8009fc2: d0a0 beq.n 8009f06 } } } } return HAL_OK; 8009fc4: 2300 movs r3, #0 } 8009fc6: 4618 mov r0, r3 8009fc8: 3710 adds r7, #16 8009fca: 46bd mov sp, r7 8009fcc: bd80 pop {r7, pc} ... 08009fd0 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8009fd0: b480 push {r7} 8009fd2: b0a3 sub sp, #140 @ 0x8c 8009fd4: af00 add r7, sp, #0 8009fd6: 60f8 str r0, [r7, #12] 8009fd8: 60b9 str r1, [r7, #8] 8009fda: 4613 mov r3, r2 8009fdc: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8009fde: 68fb ldr r3, [r7, #12] 8009fe0: 68ba ldr r2, [r7, #8] 8009fe2: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8009fe4: 68fb ldr r3, [r7, #12] 8009fe6: 88fa ldrh r2, [r7, #6] 8009fe8: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 8009fec: 68fb ldr r3, [r7, #12] 8009fee: 88fa ldrh r2, [r7, #6] 8009ff0: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8009ff4: 68fb ldr r3, [r7, #12] 8009ff6: 2200 movs r2, #0 8009ff8: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 8009ffa: 68fb ldr r3, [r7, #12] 8009ffc: 689b ldr r3, [r3, #8] 8009ffe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800a002: d10e bne.n 800a022 800a004: 68fb ldr r3, [r7, #12] 800a006: 691b ldr r3, [r3, #16] 800a008: 2b00 cmp r3, #0 800a00a: d105 bne.n 800a018 800a00c: 68fb ldr r3, [r7, #12] 800a00e: f240 12ff movw r2, #511 @ 0x1ff 800a012: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 800a016: e02d b.n 800a074 800a018: 68fb ldr r3, [r7, #12] 800a01a: 22ff movs r2, #255 @ 0xff 800a01c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 800a020: e028 b.n 800a074 800a022: 68fb ldr r3, [r7, #12] 800a024: 689b ldr r3, [r3, #8] 800a026: 2b00 cmp r3, #0 800a028: d10d bne.n 800a046 800a02a: 68fb ldr r3, [r7, #12] 800a02c: 691b ldr r3, [r3, #16] 800a02e: 2b00 cmp r3, #0 800a030: d104 bne.n 800a03c 800a032: 68fb ldr r3, [r7, #12] 800a034: 22ff movs r2, #255 @ 0xff 800a036: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 800a03a: e01b b.n 800a074 800a03c: 68fb ldr r3, [r7, #12] 800a03e: 227f movs r2, #127 @ 0x7f 800a040: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 800a044: e016 b.n 800a074 800a046: 68fb ldr r3, [r7, #12] 800a048: 689b ldr r3, [r3, #8] 800a04a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800a04e: d10d bne.n 800a06c 800a050: 68fb ldr r3, [r7, #12] 800a052: 691b ldr r3, [r3, #16] 800a054: 2b00 cmp r3, #0 800a056: d104 bne.n 800a062 800a058: 68fb ldr r3, [r7, #12] 800a05a: 227f movs r2, #127 @ 0x7f 800a05c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 800a060: e008 b.n 800a074 800a062: 68fb ldr r3, [r7, #12] 800a064: 223f movs r2, #63 @ 0x3f 800a066: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 800a06a: e003 b.n 800a074 800a06c: 68fb ldr r3, [r7, #12] 800a06e: 2200 movs r2, #0 800a070: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 800a074: 68fb ldr r3, [r7, #12] 800a076: 2200 movs r2, #0 800a078: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 800a07c: 68fb ldr r3, [r7, #12] 800a07e: 2222 movs r2, #34 @ 0x22 800a080: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 800a084: 68fb ldr r3, [r7, #12] 800a086: 681b ldr r3, [r3, #0] 800a088: 3308 adds r3, #8 800a08a: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a08c: 6e7b ldr r3, [r7, #100] @ 0x64 800a08e: e853 3f00 ldrex r3, [r3] 800a092: 663b str r3, [r7, #96] @ 0x60 return(result); 800a094: 6e3b ldr r3, [r7, #96] @ 0x60 800a096: f043 0301 orr.w r3, r3, #1 800a09a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800a09e: 68fb ldr r3, [r7, #12] 800a0a0: 681b ldr r3, [r3, #0] 800a0a2: 3308 adds r3, #8 800a0a4: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 800a0a8: 673a str r2, [r7, #112] @ 0x70 800a0aa: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a0ac: 6ef9 ldr r1, [r7, #108] @ 0x6c 800a0ae: 6f3a ldr r2, [r7, #112] @ 0x70 800a0b0: e841 2300 strex r3, r2, [r1] 800a0b4: 66bb str r3, [r7, #104] @ 0x68 return(result); 800a0b6: 6ebb ldr r3, [r7, #104] @ 0x68 800a0b8: 2b00 cmp r3, #0 800a0ba: d1e3 bne.n 800a084 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 800a0bc: 68fb ldr r3, [r7, #12] 800a0be: 6e5b ldr r3, [r3, #100] @ 0x64 800a0c0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800a0c4: d14f bne.n 800a166 800a0c6: 68fb ldr r3, [r7, #12] 800a0c8: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 800a0cc: 88fa ldrh r2, [r7, #6] 800a0ce: 429a cmp r2, r3 800a0d0: d349 bcc.n 800a166 { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800a0d2: 68fb ldr r3, [r7, #12] 800a0d4: 689b ldr r3, [r3, #8] 800a0d6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800a0da: d107 bne.n 800a0ec 800a0dc: 68fb ldr r3, [r7, #12] 800a0de: 691b ldr r3, [r3, #16] 800a0e0: 2b00 cmp r3, #0 800a0e2: d103 bne.n 800a0ec { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 800a0e4: 68fb ldr r3, [r7, #12] 800a0e6: 4a47 ldr r2, [pc, #284] @ (800a204 ) 800a0e8: 675a str r2, [r3, #116] @ 0x74 800a0ea: e002 b.n 800a0f2 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 800a0ec: 68fb ldr r3, [r7, #12] 800a0ee: 4a46 ldr r2, [pc, #280] @ (800a208 ) 800a0f0: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 800a0f2: 68fb ldr r3, [r7, #12] 800a0f4: 691b ldr r3, [r3, #16] 800a0f6: 2b00 cmp r3, #0 800a0f8: d01a beq.n 800a130 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800a0fa: 68fb ldr r3, [r7, #12] 800a0fc: 681b ldr r3, [r3, #0] 800a0fe: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a100: 6d3b ldr r3, [r7, #80] @ 0x50 800a102: e853 3f00 ldrex r3, [r3] 800a106: 64fb str r3, [r7, #76] @ 0x4c return(result); 800a108: 6cfb ldr r3, [r7, #76] @ 0x4c 800a10a: f443 7380 orr.w r3, r3, #256 @ 0x100 800a10e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800a112: 68fb ldr r3, [r7, #12] 800a114: 681b ldr r3, [r3, #0] 800a116: 461a mov r2, r3 800a118: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800a11c: 65fb str r3, [r7, #92] @ 0x5c 800a11e: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a120: 6db9 ldr r1, [r7, #88] @ 0x58 800a122: 6dfa ldr r2, [r7, #92] @ 0x5c 800a124: e841 2300 strex r3, r2, [r1] 800a128: 657b str r3, [r7, #84] @ 0x54 return(result); 800a12a: 6d7b ldr r3, [r7, #84] @ 0x54 800a12c: 2b00 cmp r3, #0 800a12e: d1e4 bne.n 800a0fa } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 800a130: 68fb ldr r3, [r7, #12] 800a132: 681b ldr r3, [r3, #0] 800a134: 3308 adds r3, #8 800a136: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a138: 6bfb ldr r3, [r7, #60] @ 0x3c 800a13a: e853 3f00 ldrex r3, [r3] 800a13e: 63bb str r3, [r7, #56] @ 0x38 return(result); 800a140: 6bbb ldr r3, [r7, #56] @ 0x38 800a142: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800a146: 67fb str r3, [r7, #124] @ 0x7c 800a148: 68fb ldr r3, [r7, #12] 800a14a: 681b ldr r3, [r3, #0] 800a14c: 3308 adds r3, #8 800a14e: 6ffa ldr r2, [r7, #124] @ 0x7c 800a150: 64ba str r2, [r7, #72] @ 0x48 800a152: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a154: 6c79 ldr r1, [r7, #68] @ 0x44 800a156: 6cba ldr r2, [r7, #72] @ 0x48 800a158: e841 2300 strex r3, r2, [r1] 800a15c: 643b str r3, [r7, #64] @ 0x40 return(result); 800a15e: 6c3b ldr r3, [r7, #64] @ 0x40 800a160: 2b00 cmp r3, #0 800a162: d1e5 bne.n 800a130 800a164: e046 b.n 800a1f4 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 800a166: 68fb ldr r3, [r7, #12] 800a168: 689b ldr r3, [r3, #8] 800a16a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800a16e: d107 bne.n 800a180 800a170: 68fb ldr r3, [r7, #12] 800a172: 691b ldr r3, [r3, #16] 800a174: 2b00 cmp r3, #0 800a176: d103 bne.n 800a180 { huart->RxISR = UART_RxISR_16BIT; 800a178: 68fb ldr r3, [r7, #12] 800a17a: 4a24 ldr r2, [pc, #144] @ (800a20c ) 800a17c: 675a str r2, [r3, #116] @ 0x74 800a17e: e002 b.n 800a186 } else { huart->RxISR = UART_RxISR_8BIT; 800a180: 68fb ldr r3, [r7, #12] 800a182: 4a23 ldr r2, [pc, #140] @ (800a210 ) 800a184: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 800a186: 68fb ldr r3, [r7, #12] 800a188: 691b ldr r3, [r3, #16] 800a18a: 2b00 cmp r3, #0 800a18c: d019 beq.n 800a1c2 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 800a18e: 68fb ldr r3, [r7, #12] 800a190: 681b ldr r3, [r3, #0] 800a192: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a194: 6abb ldr r3, [r7, #40] @ 0x28 800a196: e853 3f00 ldrex r3, [r3] 800a19a: 627b str r3, [r7, #36] @ 0x24 return(result); 800a19c: 6a7b ldr r3, [r7, #36] @ 0x24 800a19e: f443 7390 orr.w r3, r3, #288 @ 0x120 800a1a2: 677b str r3, [r7, #116] @ 0x74 800a1a4: 68fb ldr r3, [r7, #12] 800a1a6: 681b ldr r3, [r3, #0] 800a1a8: 461a mov r2, r3 800a1aa: 6f7b ldr r3, [r7, #116] @ 0x74 800a1ac: 637b str r3, [r7, #52] @ 0x34 800a1ae: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a1b0: 6b39 ldr r1, [r7, #48] @ 0x30 800a1b2: 6b7a ldr r2, [r7, #52] @ 0x34 800a1b4: e841 2300 strex r3, r2, [r1] 800a1b8: 62fb str r3, [r7, #44] @ 0x2c return(result); 800a1ba: 6afb ldr r3, [r7, #44] @ 0x2c 800a1bc: 2b00 cmp r3, #0 800a1be: d1e6 bne.n 800a18e 800a1c0: e018 b.n 800a1f4 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 800a1c2: 68fb ldr r3, [r7, #12] 800a1c4: 681b ldr r3, [r3, #0] 800a1c6: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a1c8: 697b ldr r3, [r7, #20] 800a1ca: e853 3f00 ldrex r3, [r3] 800a1ce: 613b str r3, [r7, #16] return(result); 800a1d0: 693b ldr r3, [r7, #16] 800a1d2: f043 0320 orr.w r3, r3, #32 800a1d6: 67bb str r3, [r7, #120] @ 0x78 800a1d8: 68fb ldr r3, [r7, #12] 800a1da: 681b ldr r3, [r3, #0] 800a1dc: 461a mov r2, r3 800a1de: 6fbb ldr r3, [r7, #120] @ 0x78 800a1e0: 623b str r3, [r7, #32] 800a1e2: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a1e4: 69f9 ldr r1, [r7, #28] 800a1e6: 6a3a ldr r2, [r7, #32] 800a1e8: e841 2300 strex r3, r2, [r1] 800a1ec: 61bb str r3, [r7, #24] return(result); 800a1ee: 69bb ldr r3, [r7, #24] 800a1f0: 2b00 cmp r3, #0 800a1f2: d1e6 bne.n 800a1c2 } } return HAL_OK; 800a1f4: 2300 movs r3, #0 } 800a1f6: 4618 mov r0, r3 800a1f8: 378c adds r7, #140 @ 0x8c 800a1fa: 46bd mov sp, r7 800a1fc: f85d 7b04 ldr.w r7, [sp], #4 800a200: 4770 bx lr 800a202: bf00 nop 800a204: 0800ad79 .word 0x0800ad79 800a208: 0800aa19 .word 0x0800aa19 800a20c: 0800a861 .word 0x0800a861 800a210: 0800a6a9 .word 0x0800a6a9 0800a214 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 800a214: b480 push {r7} 800a216: b095 sub sp, #84 @ 0x54 800a218: af00 add r7, sp, #0 800a21a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800a21c: 687b ldr r3, [r7, #4] 800a21e: 681b ldr r3, [r3, #0] 800a220: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a222: 6b7b ldr r3, [r7, #52] @ 0x34 800a224: e853 3f00 ldrex r3, [r3] 800a228: 633b str r3, [r7, #48] @ 0x30 return(result); 800a22a: 6b3b ldr r3, [r7, #48] @ 0x30 800a22c: f423 7390 bic.w r3, r3, #288 @ 0x120 800a230: 64fb str r3, [r7, #76] @ 0x4c 800a232: 687b ldr r3, [r7, #4] 800a234: 681b ldr r3, [r3, #0] 800a236: 461a mov r2, r3 800a238: 6cfb ldr r3, [r7, #76] @ 0x4c 800a23a: 643b str r3, [r7, #64] @ 0x40 800a23c: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a23e: 6bf9 ldr r1, [r7, #60] @ 0x3c 800a240: 6c3a ldr r2, [r7, #64] @ 0x40 800a242: e841 2300 strex r3, r2, [r1] 800a246: 63bb str r3, [r7, #56] @ 0x38 return(result); 800a248: 6bbb ldr r3, [r7, #56] @ 0x38 800a24a: 2b00 cmp r3, #0 800a24c: d1e6 bne.n 800a21c ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800a24e: 687b ldr r3, [r7, #4] 800a250: 681b ldr r3, [r3, #0] 800a252: 3308 adds r3, #8 800a254: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a256: 6a3b ldr r3, [r7, #32] 800a258: e853 3f00 ldrex r3, [r3] 800a25c: 61fb str r3, [r7, #28] return(result); 800a25e: 69fa ldr r2, [r7, #28] 800a260: 4b1e ldr r3, [pc, #120] @ (800a2dc ) 800a262: 4013 ands r3, r2 800a264: 64bb str r3, [r7, #72] @ 0x48 800a266: 687b ldr r3, [r7, #4] 800a268: 681b ldr r3, [r3, #0] 800a26a: 3308 adds r3, #8 800a26c: 6cba ldr r2, [r7, #72] @ 0x48 800a26e: 62fa str r2, [r7, #44] @ 0x2c 800a270: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a272: 6ab9 ldr r1, [r7, #40] @ 0x28 800a274: 6afa ldr r2, [r7, #44] @ 0x2c 800a276: e841 2300 strex r3, r2, [r1] 800a27a: 627b str r3, [r7, #36] @ 0x24 return(result); 800a27c: 6a7b ldr r3, [r7, #36] @ 0x24 800a27e: 2b00 cmp r3, #0 800a280: d1e5 bne.n 800a24e /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800a282: 687b ldr r3, [r7, #4] 800a284: 6edb ldr r3, [r3, #108] @ 0x6c 800a286: 2b01 cmp r3, #1 800a288: d118 bne.n 800a2bc { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800a28a: 687b ldr r3, [r7, #4] 800a28c: 681b ldr r3, [r3, #0] 800a28e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a290: 68fb ldr r3, [r7, #12] 800a292: e853 3f00 ldrex r3, [r3] 800a296: 60bb str r3, [r7, #8] return(result); 800a298: 68bb ldr r3, [r7, #8] 800a29a: f023 0310 bic.w r3, r3, #16 800a29e: 647b str r3, [r7, #68] @ 0x44 800a2a0: 687b ldr r3, [r7, #4] 800a2a2: 681b ldr r3, [r3, #0] 800a2a4: 461a mov r2, r3 800a2a6: 6c7b ldr r3, [r7, #68] @ 0x44 800a2a8: 61bb str r3, [r7, #24] 800a2aa: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a2ac: 6979 ldr r1, [r7, #20] 800a2ae: 69ba ldr r2, [r7, #24] 800a2b0: e841 2300 strex r3, r2, [r1] 800a2b4: 613b str r3, [r7, #16] return(result); 800a2b6: 693b ldr r3, [r7, #16] 800a2b8: 2b00 cmp r3, #0 800a2ba: d1e6 bne.n 800a28a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800a2bc: 687b ldr r3, [r7, #4] 800a2be: 2220 movs r2, #32 800a2c0: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800a2c4: 687b ldr r3, [r7, #4] 800a2c6: 2200 movs r2, #0 800a2c8: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 800a2ca: 687b ldr r3, [r7, #4] 800a2cc: 2200 movs r2, #0 800a2ce: 675a str r2, [r3, #116] @ 0x74 } 800a2d0: bf00 nop 800a2d2: 3754 adds r7, #84 @ 0x54 800a2d4: 46bd mov sp, r7 800a2d6: f85d 7b04 ldr.w r7, [sp], #4 800a2da: 4770 bx lr 800a2dc: effffffe .word 0xeffffffe 0800a2e0 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 800a2e0: b580 push {r7, lr} 800a2e2: b084 sub sp, #16 800a2e4: af00 add r7, sp, #0 800a2e6: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 800a2e8: 687b ldr r3, [r7, #4] 800a2ea: 6b9b ldr r3, [r3, #56] @ 0x38 800a2ec: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 800a2ee: 68fb ldr r3, [r7, #12] 800a2f0: 2200 movs r2, #0 800a2f2: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 800a2f6: 68fb ldr r3, [r7, #12] 800a2f8: 2200 movs r2, #0 800a2fa: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800a2fe: 68f8 ldr r0, [r7, #12] 800a300: f7fe ff3a bl 8009178 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800a304: bf00 nop 800a306: 3710 adds r7, #16 800a308: 46bd mov sp, r7 800a30a: bd80 pop {r7, pc} 0800a30c : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 800a30c: b480 push {r7} 800a30e: b08f sub sp, #60 @ 0x3c 800a310: af00 add r7, sp, #0 800a312: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800a314: 687b ldr r3, [r7, #4] 800a316: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800a31a: 2b21 cmp r3, #33 @ 0x21 800a31c: d14c bne.n 800a3b8 { if (huart->TxXferCount == 0U) 800a31e: 687b ldr r3, [r7, #4] 800a320: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800a324: b29b uxth r3, r3 800a326: 2b00 cmp r3, #0 800a328: d132 bne.n 800a390 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 800a32a: 687b ldr r3, [r7, #4] 800a32c: 681b ldr r3, [r3, #0] 800a32e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a330: 6a3b ldr r3, [r7, #32] 800a332: e853 3f00 ldrex r3, [r3] 800a336: 61fb str r3, [r7, #28] return(result); 800a338: 69fb ldr r3, [r7, #28] 800a33a: f023 0380 bic.w r3, r3, #128 @ 0x80 800a33e: 637b str r3, [r7, #52] @ 0x34 800a340: 687b ldr r3, [r7, #4] 800a342: 681b ldr r3, [r3, #0] 800a344: 461a mov r2, r3 800a346: 6b7b ldr r3, [r7, #52] @ 0x34 800a348: 62fb str r3, [r7, #44] @ 0x2c 800a34a: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a34c: 6ab9 ldr r1, [r7, #40] @ 0x28 800a34e: 6afa ldr r2, [r7, #44] @ 0x2c 800a350: e841 2300 strex r3, r2, [r1] 800a354: 627b str r3, [r7, #36] @ 0x24 return(result); 800a356: 6a7b ldr r3, [r7, #36] @ 0x24 800a358: 2b00 cmp r3, #0 800a35a: d1e6 bne.n 800a32a /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a35c: 687b ldr r3, [r7, #4] 800a35e: 681b ldr r3, [r3, #0] 800a360: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a362: 68fb ldr r3, [r7, #12] 800a364: e853 3f00 ldrex r3, [r3] 800a368: 60bb str r3, [r7, #8] return(result); 800a36a: 68bb ldr r3, [r7, #8] 800a36c: f043 0340 orr.w r3, r3, #64 @ 0x40 800a370: 633b str r3, [r7, #48] @ 0x30 800a372: 687b ldr r3, [r7, #4] 800a374: 681b ldr r3, [r3, #0] 800a376: 461a mov r2, r3 800a378: 6b3b ldr r3, [r7, #48] @ 0x30 800a37a: 61bb str r3, [r7, #24] 800a37c: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a37e: 6979 ldr r1, [r7, #20] 800a380: 69ba ldr r2, [r7, #24] 800a382: e841 2300 strex r3, r2, [r1] 800a386: 613b str r3, [r7, #16] return(result); 800a388: 693b ldr r3, [r7, #16] 800a38a: 2b00 cmp r3, #0 800a38c: d1e6 bne.n 800a35c huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 800a38e: e013 b.n 800a3b8 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 800a390: 687b ldr r3, [r7, #4] 800a392: 6d1b ldr r3, [r3, #80] @ 0x50 800a394: 781a ldrb r2, [r3, #0] 800a396: 687b ldr r3, [r7, #4] 800a398: 681b ldr r3, [r3, #0] 800a39a: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 800a39c: 687b ldr r3, [r7, #4] 800a39e: 6d1b ldr r3, [r3, #80] @ 0x50 800a3a0: 1c5a adds r2, r3, #1 800a3a2: 687b ldr r3, [r7, #4] 800a3a4: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 800a3a6: 687b ldr r3, [r7, #4] 800a3a8: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800a3ac: b29b uxth r3, r3 800a3ae: 3b01 subs r3, #1 800a3b0: b29a uxth r2, r3 800a3b2: 687b ldr r3, [r7, #4] 800a3b4: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 800a3b8: bf00 nop 800a3ba: 373c adds r7, #60 @ 0x3c 800a3bc: 46bd mov sp, r7 800a3be: f85d 7b04 ldr.w r7, [sp], #4 800a3c2: 4770 bx lr 0800a3c4 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 800a3c4: b480 push {r7} 800a3c6: b091 sub sp, #68 @ 0x44 800a3c8: af00 add r7, sp, #0 800a3ca: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800a3cc: 687b ldr r3, [r7, #4] 800a3ce: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800a3d2: 2b21 cmp r3, #33 @ 0x21 800a3d4: d151 bne.n 800a47a { if (huart->TxXferCount == 0U) 800a3d6: 687b ldr r3, [r7, #4] 800a3d8: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800a3dc: b29b uxth r3, r3 800a3de: 2b00 cmp r3, #0 800a3e0: d132 bne.n 800a448 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 800a3e2: 687b ldr r3, [r7, #4] 800a3e4: 681b ldr r3, [r3, #0] 800a3e6: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a3e8: 6a7b ldr r3, [r7, #36] @ 0x24 800a3ea: e853 3f00 ldrex r3, [r3] 800a3ee: 623b str r3, [r7, #32] return(result); 800a3f0: 6a3b ldr r3, [r7, #32] 800a3f2: f023 0380 bic.w r3, r3, #128 @ 0x80 800a3f6: 63bb str r3, [r7, #56] @ 0x38 800a3f8: 687b ldr r3, [r7, #4] 800a3fa: 681b ldr r3, [r3, #0] 800a3fc: 461a mov r2, r3 800a3fe: 6bbb ldr r3, [r7, #56] @ 0x38 800a400: 633b str r3, [r7, #48] @ 0x30 800a402: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a404: 6af9 ldr r1, [r7, #44] @ 0x2c 800a406: 6b3a ldr r2, [r7, #48] @ 0x30 800a408: e841 2300 strex r3, r2, [r1] 800a40c: 62bb str r3, [r7, #40] @ 0x28 return(result); 800a40e: 6abb ldr r3, [r7, #40] @ 0x28 800a410: 2b00 cmp r3, #0 800a412: d1e6 bne.n 800a3e2 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a414: 687b ldr r3, [r7, #4] 800a416: 681b ldr r3, [r3, #0] 800a418: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a41a: 693b ldr r3, [r7, #16] 800a41c: e853 3f00 ldrex r3, [r3] 800a420: 60fb str r3, [r7, #12] return(result); 800a422: 68fb ldr r3, [r7, #12] 800a424: f043 0340 orr.w r3, r3, #64 @ 0x40 800a428: 637b str r3, [r7, #52] @ 0x34 800a42a: 687b ldr r3, [r7, #4] 800a42c: 681b ldr r3, [r3, #0] 800a42e: 461a mov r2, r3 800a430: 6b7b ldr r3, [r7, #52] @ 0x34 800a432: 61fb str r3, [r7, #28] 800a434: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a436: 69b9 ldr r1, [r7, #24] 800a438: 69fa ldr r2, [r7, #28] 800a43a: e841 2300 strex r3, r2, [r1] 800a43e: 617b str r3, [r7, #20] return(result); 800a440: 697b ldr r3, [r7, #20] 800a442: 2b00 cmp r3, #0 800a444: d1e6 bne.n 800a414 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 800a446: e018 b.n 800a47a tmp = (const uint16_t *) huart->pTxBuffPtr; 800a448: 687b ldr r3, [r7, #4] 800a44a: 6d1b ldr r3, [r3, #80] @ 0x50 800a44c: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 800a44e: 6bfb ldr r3, [r7, #60] @ 0x3c 800a450: 881b ldrh r3, [r3, #0] 800a452: 461a mov r2, r3 800a454: 687b ldr r3, [r7, #4] 800a456: 681b ldr r3, [r3, #0] 800a458: f3c2 0208 ubfx r2, r2, #0, #9 800a45c: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 800a45e: 687b ldr r3, [r7, #4] 800a460: 6d1b ldr r3, [r3, #80] @ 0x50 800a462: 1c9a adds r2, r3, #2 800a464: 687b ldr r3, [r7, #4] 800a466: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 800a468: 687b ldr r3, [r7, #4] 800a46a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800a46e: b29b uxth r3, r3 800a470: 3b01 subs r3, #1 800a472: b29a uxth r2, r3 800a474: 687b ldr r3, [r7, #4] 800a476: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 800a47a: bf00 nop 800a47c: 3744 adds r7, #68 @ 0x44 800a47e: 46bd mov sp, r7 800a480: f85d 7b04 ldr.w r7, [sp], #4 800a484: 4770 bx lr 0800a486 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 800a486: b480 push {r7} 800a488: b091 sub sp, #68 @ 0x44 800a48a: af00 add r7, sp, #0 800a48c: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800a48e: 687b ldr r3, [r7, #4] 800a490: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800a494: 2b21 cmp r3, #33 @ 0x21 800a496: d160 bne.n 800a55a { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a498: 687b ldr r3, [r7, #4] 800a49a: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 800a49e: 87fb strh r3, [r7, #62] @ 0x3e 800a4a0: e057 b.n 800a552 { if (huart->TxXferCount == 0U) 800a4a2: 687b ldr r3, [r7, #4] 800a4a4: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800a4a8: b29b uxth r3, r3 800a4aa: 2b00 cmp r3, #0 800a4ac: d133 bne.n 800a516 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 800a4ae: 687b ldr r3, [r7, #4] 800a4b0: 681b ldr r3, [r3, #0] 800a4b2: 3308 adds r3, #8 800a4b4: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a4b6: 6a7b ldr r3, [r7, #36] @ 0x24 800a4b8: e853 3f00 ldrex r3, [r3] 800a4bc: 623b str r3, [r7, #32] return(result); 800a4be: 6a3b ldr r3, [r7, #32] 800a4c0: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 800a4c4: 63bb str r3, [r7, #56] @ 0x38 800a4c6: 687b ldr r3, [r7, #4] 800a4c8: 681b ldr r3, [r3, #0] 800a4ca: 3308 adds r3, #8 800a4cc: 6bba ldr r2, [r7, #56] @ 0x38 800a4ce: 633a str r2, [r7, #48] @ 0x30 800a4d0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a4d2: 6af9 ldr r1, [r7, #44] @ 0x2c 800a4d4: 6b3a ldr r2, [r7, #48] @ 0x30 800a4d6: e841 2300 strex r3, r2, [r1] 800a4da: 62bb str r3, [r7, #40] @ 0x28 return(result); 800a4dc: 6abb ldr r3, [r7, #40] @ 0x28 800a4de: 2b00 cmp r3, #0 800a4e0: d1e5 bne.n 800a4ae /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a4e2: 687b ldr r3, [r7, #4] 800a4e4: 681b ldr r3, [r3, #0] 800a4e6: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a4e8: 693b ldr r3, [r7, #16] 800a4ea: e853 3f00 ldrex r3, [r3] 800a4ee: 60fb str r3, [r7, #12] return(result); 800a4f0: 68fb ldr r3, [r7, #12] 800a4f2: f043 0340 orr.w r3, r3, #64 @ 0x40 800a4f6: 637b str r3, [r7, #52] @ 0x34 800a4f8: 687b ldr r3, [r7, #4] 800a4fa: 681b ldr r3, [r3, #0] 800a4fc: 461a mov r2, r3 800a4fe: 6b7b ldr r3, [r7, #52] @ 0x34 800a500: 61fb str r3, [r7, #28] 800a502: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a504: 69b9 ldr r1, [r7, #24] 800a506: 69fa ldr r2, [r7, #28] 800a508: e841 2300 strex r3, r2, [r1] 800a50c: 617b str r3, [r7, #20] return(result); 800a50e: 697b ldr r3, [r7, #20] 800a510: 2b00 cmp r3, #0 800a512: d1e6 bne.n 800a4e2 break; /* force exit loop */ 800a514: e021 b.n 800a55a } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 800a516: 687b ldr r3, [r7, #4] 800a518: 681b ldr r3, [r3, #0] 800a51a: 69db ldr r3, [r3, #28] 800a51c: f003 0380 and.w r3, r3, #128 @ 0x80 800a520: 2b00 cmp r3, #0 800a522: d013 beq.n 800a54c { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 800a524: 687b ldr r3, [r7, #4] 800a526: 6d1b ldr r3, [r3, #80] @ 0x50 800a528: 781a ldrb r2, [r3, #0] 800a52a: 687b ldr r3, [r7, #4] 800a52c: 681b ldr r3, [r3, #0] 800a52e: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 800a530: 687b ldr r3, [r7, #4] 800a532: 6d1b ldr r3, [r3, #80] @ 0x50 800a534: 1c5a adds r2, r3, #1 800a536: 687b ldr r3, [r7, #4] 800a538: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 800a53a: 687b ldr r3, [r7, #4] 800a53c: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800a540: b29b uxth r3, r3 800a542: 3b01 subs r3, #1 800a544: b29a uxth r2, r3 800a546: 687b ldr r3, [r7, #4] 800a548: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a54c: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a54e: 3b01 subs r3, #1 800a550: 87fb strh r3, [r7, #62] @ 0x3e 800a552: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a554: 2b00 cmp r3, #0 800a556: d1a4 bne.n 800a4a2 { /* Nothing to do */ } } } } 800a558: e7ff b.n 800a55a 800a55a: bf00 nop 800a55c: 3744 adds r7, #68 @ 0x44 800a55e: 46bd mov sp, r7 800a560: f85d 7b04 ldr.w r7, [sp], #4 800a564: 4770 bx lr 0800a566 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 800a566: b480 push {r7} 800a568: b091 sub sp, #68 @ 0x44 800a56a: af00 add r7, sp, #0 800a56c: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 800a56e: 687b ldr r3, [r7, #4] 800a570: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800a574: 2b21 cmp r3, #33 @ 0x21 800a576: d165 bne.n 800a644 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a578: 687b ldr r3, [r7, #4] 800a57a: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 800a57e: 87fb strh r3, [r7, #62] @ 0x3e 800a580: e05c b.n 800a63c { if (huart->TxXferCount == 0U) 800a582: 687b ldr r3, [r7, #4] 800a584: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800a588: b29b uxth r3, r3 800a58a: 2b00 cmp r3, #0 800a58c: d133 bne.n 800a5f6 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 800a58e: 687b ldr r3, [r7, #4] 800a590: 681b ldr r3, [r3, #0] 800a592: 3308 adds r3, #8 800a594: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a596: 6a3b ldr r3, [r7, #32] 800a598: e853 3f00 ldrex r3, [r3] 800a59c: 61fb str r3, [r7, #28] return(result); 800a59e: 69fb ldr r3, [r7, #28] 800a5a0: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 800a5a4: 637b str r3, [r7, #52] @ 0x34 800a5a6: 687b ldr r3, [r7, #4] 800a5a8: 681b ldr r3, [r3, #0] 800a5aa: 3308 adds r3, #8 800a5ac: 6b7a ldr r2, [r7, #52] @ 0x34 800a5ae: 62fa str r2, [r7, #44] @ 0x2c 800a5b0: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a5b2: 6ab9 ldr r1, [r7, #40] @ 0x28 800a5b4: 6afa ldr r2, [r7, #44] @ 0x2c 800a5b6: e841 2300 strex r3, r2, [r1] 800a5ba: 627b str r3, [r7, #36] @ 0x24 return(result); 800a5bc: 6a7b ldr r3, [r7, #36] @ 0x24 800a5be: 2b00 cmp r3, #0 800a5c0: d1e5 bne.n 800a58e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a5c2: 687b ldr r3, [r7, #4] 800a5c4: 681b ldr r3, [r3, #0] 800a5c6: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a5c8: 68fb ldr r3, [r7, #12] 800a5ca: e853 3f00 ldrex r3, [r3] 800a5ce: 60bb str r3, [r7, #8] return(result); 800a5d0: 68bb ldr r3, [r7, #8] 800a5d2: f043 0340 orr.w r3, r3, #64 @ 0x40 800a5d6: 633b str r3, [r7, #48] @ 0x30 800a5d8: 687b ldr r3, [r7, #4] 800a5da: 681b ldr r3, [r3, #0] 800a5dc: 461a mov r2, r3 800a5de: 6b3b ldr r3, [r7, #48] @ 0x30 800a5e0: 61bb str r3, [r7, #24] 800a5e2: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a5e4: 6979 ldr r1, [r7, #20] 800a5e6: 69ba ldr r2, [r7, #24] 800a5e8: e841 2300 strex r3, r2, [r1] 800a5ec: 613b str r3, [r7, #16] return(result); 800a5ee: 693b ldr r3, [r7, #16] 800a5f0: 2b00 cmp r3, #0 800a5f2: d1e6 bne.n 800a5c2 break; /* force exit loop */ 800a5f4: e026 b.n 800a644 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 800a5f6: 687b ldr r3, [r7, #4] 800a5f8: 681b ldr r3, [r3, #0] 800a5fa: 69db ldr r3, [r3, #28] 800a5fc: f003 0380 and.w r3, r3, #128 @ 0x80 800a600: 2b00 cmp r3, #0 800a602: d018 beq.n 800a636 { tmp = (const uint16_t *) huart->pTxBuffPtr; 800a604: 687b ldr r3, [r7, #4] 800a606: 6d1b ldr r3, [r3, #80] @ 0x50 800a608: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 800a60a: 6bbb ldr r3, [r7, #56] @ 0x38 800a60c: 881b ldrh r3, [r3, #0] 800a60e: 461a mov r2, r3 800a610: 687b ldr r3, [r7, #4] 800a612: 681b ldr r3, [r3, #0] 800a614: f3c2 0208 ubfx r2, r2, #0, #9 800a618: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 800a61a: 687b ldr r3, [r7, #4] 800a61c: 6d1b ldr r3, [r3, #80] @ 0x50 800a61e: 1c9a adds r2, r3, #2 800a620: 687b ldr r3, [r7, #4] 800a622: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 800a624: 687b ldr r3, [r7, #4] 800a626: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 800a62a: b29b uxth r3, r3 800a62c: 3b01 subs r3, #1 800a62e: b29a uxth r2, r3 800a630: 687b ldr r3, [r7, #4] 800a632: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 800a636: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a638: 3b01 subs r3, #1 800a63a: 87fb strh r3, [r7, #62] @ 0x3e 800a63c: 8ffb ldrh r3, [r7, #62] @ 0x3e 800a63e: 2b00 cmp r3, #0 800a640: d19f bne.n 800a582 { /* Nothing to do */ } } } } 800a642: e7ff b.n 800a644 800a644: bf00 nop 800a646: 3744 adds r7, #68 @ 0x44 800a648: 46bd mov sp, r7 800a64a: f85d 7b04 ldr.w r7, [sp], #4 800a64e: 4770 bx lr 0800a650 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 800a650: b580 push {r7, lr} 800a652: b088 sub sp, #32 800a654: af00 add r7, sp, #0 800a656: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 800a658: 687b ldr r3, [r7, #4] 800a65a: 681b ldr r3, [r3, #0] 800a65c: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a65e: 68fb ldr r3, [r7, #12] 800a660: e853 3f00 ldrex r3, [r3] 800a664: 60bb str r3, [r7, #8] return(result); 800a666: 68bb ldr r3, [r7, #8] 800a668: f023 0340 bic.w r3, r3, #64 @ 0x40 800a66c: 61fb str r3, [r7, #28] 800a66e: 687b ldr r3, [r7, #4] 800a670: 681b ldr r3, [r3, #0] 800a672: 461a mov r2, r3 800a674: 69fb ldr r3, [r7, #28] 800a676: 61bb str r3, [r7, #24] 800a678: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a67a: 6979 ldr r1, [r7, #20] 800a67c: 69ba ldr r2, [r7, #24] 800a67e: e841 2300 strex r3, r2, [r1] 800a682: 613b str r3, [r7, #16] return(result); 800a684: 693b ldr r3, [r7, #16] 800a686: 2b00 cmp r3, #0 800a688: d1e6 bne.n 800a658 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 800a68a: 687b ldr r3, [r7, #4] 800a68c: 2220 movs r2, #32 800a68e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 800a692: 687b ldr r3, [r7, #4] 800a694: 2200 movs r2, #0 800a696: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 800a698: 6878 ldr r0, [r7, #4] 800a69a: f7f7 faf3 bl 8001c84 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 800a69e: bf00 nop 800a6a0: 3720 adds r7, #32 800a6a2: 46bd mov sp, r7 800a6a4: bd80 pop {r7, pc} ... 0800a6a8 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 800a6a8: b580 push {r7, lr} 800a6aa: b09c sub sp, #112 @ 0x70 800a6ac: af00 add r7, sp, #0 800a6ae: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 800a6b0: 687b ldr r3, [r7, #4] 800a6b2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 800a6b6: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800a6ba: 687b ldr r3, [r7, #4] 800a6bc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800a6c0: 2b22 cmp r3, #34 @ 0x22 800a6c2: f040 80be bne.w 800a842 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800a6c6: 687b ldr r3, [r7, #4] 800a6c8: 681b ldr r3, [r3, #0] 800a6ca: 6a5b ldr r3, [r3, #36] @ 0x24 800a6cc: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 800a6d0: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 800a6d4: b2d9 uxtb r1, r3 800a6d6: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 800a6da: b2da uxtb r2, r3 800a6dc: 687b ldr r3, [r7, #4] 800a6de: 6d9b ldr r3, [r3, #88] @ 0x58 800a6e0: 400a ands r2, r1 800a6e2: b2d2 uxtb r2, r2 800a6e4: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 800a6e6: 687b ldr r3, [r7, #4] 800a6e8: 6d9b ldr r3, [r3, #88] @ 0x58 800a6ea: 1c5a adds r2, r3, #1 800a6ec: 687b ldr r3, [r7, #4] 800a6ee: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 800a6f0: 687b ldr r3, [r7, #4] 800a6f2: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800a6f6: b29b uxth r3, r3 800a6f8: 3b01 subs r3, #1 800a6fa: b29a uxth r2, r3 800a6fc: 687b ldr r3, [r7, #4] 800a6fe: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 800a702: 687b ldr r3, [r7, #4] 800a704: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800a708: b29b uxth r3, r3 800a70a: 2b00 cmp r3, #0 800a70c: f040 80a1 bne.w 800a852 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800a710: 687b ldr r3, [r7, #4] 800a712: 681b ldr r3, [r3, #0] 800a714: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a716: 6cfb ldr r3, [r7, #76] @ 0x4c 800a718: e853 3f00 ldrex r3, [r3] 800a71c: 64bb str r3, [r7, #72] @ 0x48 return(result); 800a71e: 6cbb ldr r3, [r7, #72] @ 0x48 800a720: f423 7390 bic.w r3, r3, #288 @ 0x120 800a724: 66bb str r3, [r7, #104] @ 0x68 800a726: 687b ldr r3, [r7, #4] 800a728: 681b ldr r3, [r3, #0] 800a72a: 461a mov r2, r3 800a72c: 6ebb ldr r3, [r7, #104] @ 0x68 800a72e: 65bb str r3, [r7, #88] @ 0x58 800a730: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a732: 6d79 ldr r1, [r7, #84] @ 0x54 800a734: 6dba ldr r2, [r7, #88] @ 0x58 800a736: e841 2300 strex r3, r2, [r1] 800a73a: 653b str r3, [r7, #80] @ 0x50 return(result); 800a73c: 6d3b ldr r3, [r7, #80] @ 0x50 800a73e: 2b00 cmp r3, #0 800a740: d1e6 bne.n 800a710 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800a742: 687b ldr r3, [r7, #4] 800a744: 681b ldr r3, [r3, #0] 800a746: 3308 adds r3, #8 800a748: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a74a: 6bbb ldr r3, [r7, #56] @ 0x38 800a74c: e853 3f00 ldrex r3, [r3] 800a750: 637b str r3, [r7, #52] @ 0x34 return(result); 800a752: 6b7b ldr r3, [r7, #52] @ 0x34 800a754: f023 0301 bic.w r3, r3, #1 800a758: 667b str r3, [r7, #100] @ 0x64 800a75a: 687b ldr r3, [r7, #4] 800a75c: 681b ldr r3, [r3, #0] 800a75e: 3308 adds r3, #8 800a760: 6e7a ldr r2, [r7, #100] @ 0x64 800a762: 647a str r2, [r7, #68] @ 0x44 800a764: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a766: 6c39 ldr r1, [r7, #64] @ 0x40 800a768: 6c7a ldr r2, [r7, #68] @ 0x44 800a76a: e841 2300 strex r3, r2, [r1] 800a76e: 63fb str r3, [r7, #60] @ 0x3c return(result); 800a770: 6bfb ldr r3, [r7, #60] @ 0x3c 800a772: 2b00 cmp r3, #0 800a774: d1e5 bne.n 800a742 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800a776: 687b ldr r3, [r7, #4] 800a778: 2220 movs r2, #32 800a77a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 800a77e: 687b ldr r3, [r7, #4] 800a780: 2200 movs r2, #0 800a782: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800a784: 687b ldr r3, [r7, #4] 800a786: 2200 movs r2, #0 800a788: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800a78a: 687b ldr r3, [r7, #4] 800a78c: 681b ldr r3, [r3, #0] 800a78e: 4a33 ldr r2, [pc, #204] @ (800a85c ) 800a790: 4293 cmp r3, r2 800a792: d01f beq.n 800a7d4 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 800a794: 687b ldr r3, [r7, #4] 800a796: 681b ldr r3, [r3, #0] 800a798: 685b ldr r3, [r3, #4] 800a79a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800a79e: 2b00 cmp r3, #0 800a7a0: d018 beq.n 800a7d4 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800a7a2: 687b ldr r3, [r7, #4] 800a7a4: 681b ldr r3, [r3, #0] 800a7a6: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a7a8: 6a7b ldr r3, [r7, #36] @ 0x24 800a7aa: e853 3f00 ldrex r3, [r3] 800a7ae: 623b str r3, [r7, #32] return(result); 800a7b0: 6a3b ldr r3, [r7, #32] 800a7b2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800a7b6: 663b str r3, [r7, #96] @ 0x60 800a7b8: 687b ldr r3, [r7, #4] 800a7ba: 681b ldr r3, [r3, #0] 800a7bc: 461a mov r2, r3 800a7be: 6e3b ldr r3, [r7, #96] @ 0x60 800a7c0: 633b str r3, [r7, #48] @ 0x30 800a7c2: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a7c4: 6af9 ldr r1, [r7, #44] @ 0x2c 800a7c6: 6b3a ldr r2, [r7, #48] @ 0x30 800a7c8: e841 2300 strex r3, r2, [r1] 800a7cc: 62bb str r3, [r7, #40] @ 0x28 return(result); 800a7ce: 6abb ldr r3, [r7, #40] @ 0x28 800a7d0: 2b00 cmp r3, #0 800a7d2: d1e6 bne.n 800a7a2 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800a7d4: 687b ldr r3, [r7, #4] 800a7d6: 6edb ldr r3, [r3, #108] @ 0x6c 800a7d8: 2b01 cmp r3, #1 800a7da: d12e bne.n 800a83a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800a7dc: 687b ldr r3, [r7, #4] 800a7de: 2200 movs r2, #0 800a7e0: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800a7e2: 687b ldr r3, [r7, #4] 800a7e4: 681b ldr r3, [r3, #0] 800a7e6: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a7e8: 693b ldr r3, [r7, #16] 800a7ea: e853 3f00 ldrex r3, [r3] 800a7ee: 60fb str r3, [r7, #12] return(result); 800a7f0: 68fb ldr r3, [r7, #12] 800a7f2: f023 0310 bic.w r3, r3, #16 800a7f6: 65fb str r3, [r7, #92] @ 0x5c 800a7f8: 687b ldr r3, [r7, #4] 800a7fa: 681b ldr r3, [r3, #0] 800a7fc: 461a mov r2, r3 800a7fe: 6dfb ldr r3, [r7, #92] @ 0x5c 800a800: 61fb str r3, [r7, #28] 800a802: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a804: 69b9 ldr r1, [r7, #24] 800a806: 69fa ldr r2, [r7, #28] 800a808: e841 2300 strex r3, r2, [r1] 800a80c: 617b str r3, [r7, #20] return(result); 800a80e: 697b ldr r3, [r7, #20] 800a810: 2b00 cmp r3, #0 800a812: d1e6 bne.n 800a7e2 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 800a814: 687b ldr r3, [r7, #4] 800a816: 681b ldr r3, [r3, #0] 800a818: 69db ldr r3, [r3, #28] 800a81a: f003 0310 and.w r3, r3, #16 800a81e: 2b10 cmp r3, #16 800a820: d103 bne.n 800a82a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800a822: 687b ldr r3, [r7, #4] 800a824: 681b ldr r3, [r3, #0] 800a826: 2210 movs r2, #16 800a828: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800a82a: 687b ldr r3, [r7, #4] 800a82c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800a830: 4619 mov r1, r3 800a832: 6878 ldr r0, [r7, #4] 800a834: f7f7 f9fc bl 8001c30 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 800a838: e00b b.n 800a852 HAL_UART_RxCpltCallback(huart); 800a83a: 6878 ldr r0, [r7, #4] 800a83c: f7f7 f9ee bl 8001c1c } 800a840: e007 b.n 800a852 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800a842: 687b ldr r3, [r7, #4] 800a844: 681b ldr r3, [r3, #0] 800a846: 699a ldr r2, [r3, #24] 800a848: 687b ldr r3, [r7, #4] 800a84a: 681b ldr r3, [r3, #0] 800a84c: f042 0208 orr.w r2, r2, #8 800a850: 619a str r2, [r3, #24] } 800a852: bf00 nop 800a854: 3770 adds r7, #112 @ 0x70 800a856: 46bd mov sp, r7 800a858: bd80 pop {r7, pc} 800a85a: bf00 nop 800a85c: 58000c00 .word 0x58000c00 0800a860 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 800a860: b580 push {r7, lr} 800a862: b09c sub sp, #112 @ 0x70 800a864: af00 add r7, sp, #0 800a866: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 800a868: 687b ldr r3, [r7, #4] 800a86a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 800a86e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800a872: 687b ldr r3, [r7, #4] 800a874: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800a878: 2b22 cmp r3, #34 @ 0x22 800a87a: f040 80be bne.w 800a9fa { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800a87e: 687b ldr r3, [r7, #4] 800a880: 681b ldr r3, [r3, #0] 800a882: 6a5b ldr r3, [r3, #36] @ 0x24 800a884: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 800a888: 687b ldr r3, [r7, #4] 800a88a: 6d9b ldr r3, [r3, #88] @ 0x58 800a88c: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 800a88e: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 800a892: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 800a896: 4013 ands r3, r2 800a898: b29a uxth r2, r3 800a89a: 6ebb ldr r3, [r7, #104] @ 0x68 800a89c: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 800a89e: 687b ldr r3, [r7, #4] 800a8a0: 6d9b ldr r3, [r3, #88] @ 0x58 800a8a2: 1c9a adds r2, r3, #2 800a8a4: 687b ldr r3, [r7, #4] 800a8a6: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 800a8a8: 687b ldr r3, [r7, #4] 800a8aa: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800a8ae: b29b uxth r3, r3 800a8b0: 3b01 subs r3, #1 800a8b2: b29a uxth r2, r3 800a8b4: 687b ldr r3, [r7, #4] 800a8b6: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 800a8ba: 687b ldr r3, [r7, #4] 800a8bc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800a8c0: b29b uxth r3, r3 800a8c2: 2b00 cmp r3, #0 800a8c4: f040 80a1 bne.w 800aa0a { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 800a8c8: 687b ldr r3, [r7, #4] 800a8ca: 681b ldr r3, [r3, #0] 800a8cc: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a8ce: 6cbb ldr r3, [r7, #72] @ 0x48 800a8d0: e853 3f00 ldrex r3, [r3] 800a8d4: 647b str r3, [r7, #68] @ 0x44 return(result); 800a8d6: 6c7b ldr r3, [r7, #68] @ 0x44 800a8d8: f423 7390 bic.w r3, r3, #288 @ 0x120 800a8dc: 667b str r3, [r7, #100] @ 0x64 800a8de: 687b ldr r3, [r7, #4] 800a8e0: 681b ldr r3, [r3, #0] 800a8e2: 461a mov r2, r3 800a8e4: 6e7b ldr r3, [r7, #100] @ 0x64 800a8e6: 657b str r3, [r7, #84] @ 0x54 800a8e8: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a8ea: 6d39 ldr r1, [r7, #80] @ 0x50 800a8ec: 6d7a ldr r2, [r7, #84] @ 0x54 800a8ee: e841 2300 strex r3, r2, [r1] 800a8f2: 64fb str r3, [r7, #76] @ 0x4c return(result); 800a8f4: 6cfb ldr r3, [r7, #76] @ 0x4c 800a8f6: 2b00 cmp r3, #0 800a8f8: d1e6 bne.n 800a8c8 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 800a8fa: 687b ldr r3, [r7, #4] 800a8fc: 681b ldr r3, [r3, #0] 800a8fe: 3308 adds r3, #8 800a900: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a902: 6b7b ldr r3, [r7, #52] @ 0x34 800a904: e853 3f00 ldrex r3, [r3] 800a908: 633b str r3, [r7, #48] @ 0x30 return(result); 800a90a: 6b3b ldr r3, [r7, #48] @ 0x30 800a90c: f023 0301 bic.w r3, r3, #1 800a910: 663b str r3, [r7, #96] @ 0x60 800a912: 687b ldr r3, [r7, #4] 800a914: 681b ldr r3, [r3, #0] 800a916: 3308 adds r3, #8 800a918: 6e3a ldr r2, [r7, #96] @ 0x60 800a91a: 643a str r2, [r7, #64] @ 0x40 800a91c: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a91e: 6bf9 ldr r1, [r7, #60] @ 0x3c 800a920: 6c3a ldr r2, [r7, #64] @ 0x40 800a922: e841 2300 strex r3, r2, [r1] 800a926: 63bb str r3, [r7, #56] @ 0x38 return(result); 800a928: 6bbb ldr r3, [r7, #56] @ 0x38 800a92a: 2b00 cmp r3, #0 800a92c: d1e5 bne.n 800a8fa /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800a92e: 687b ldr r3, [r7, #4] 800a930: 2220 movs r2, #32 800a932: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 800a936: 687b ldr r3, [r7, #4] 800a938: 2200 movs r2, #0 800a93a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800a93c: 687b ldr r3, [r7, #4] 800a93e: 2200 movs r2, #0 800a940: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800a942: 687b ldr r3, [r7, #4] 800a944: 681b ldr r3, [r3, #0] 800a946: 4a33 ldr r2, [pc, #204] @ (800aa14 ) 800a948: 4293 cmp r3, r2 800a94a: d01f beq.n 800a98c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 800a94c: 687b ldr r3, [r7, #4] 800a94e: 681b ldr r3, [r3, #0] 800a950: 685b ldr r3, [r3, #4] 800a952: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800a956: 2b00 cmp r3, #0 800a958: d018 beq.n 800a98c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800a95a: 687b ldr r3, [r7, #4] 800a95c: 681b ldr r3, [r3, #0] 800a95e: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a960: 6a3b ldr r3, [r7, #32] 800a962: e853 3f00 ldrex r3, [r3] 800a966: 61fb str r3, [r7, #28] return(result); 800a968: 69fb ldr r3, [r7, #28] 800a96a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800a96e: 65fb str r3, [r7, #92] @ 0x5c 800a970: 687b ldr r3, [r7, #4] 800a972: 681b ldr r3, [r3, #0] 800a974: 461a mov r2, r3 800a976: 6dfb ldr r3, [r7, #92] @ 0x5c 800a978: 62fb str r3, [r7, #44] @ 0x2c 800a97a: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a97c: 6ab9 ldr r1, [r7, #40] @ 0x28 800a97e: 6afa ldr r2, [r7, #44] @ 0x2c 800a980: e841 2300 strex r3, r2, [r1] 800a984: 627b str r3, [r7, #36] @ 0x24 return(result); 800a986: 6a7b ldr r3, [r7, #36] @ 0x24 800a988: 2b00 cmp r3, #0 800a98a: d1e6 bne.n 800a95a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800a98c: 687b ldr r3, [r7, #4] 800a98e: 6edb ldr r3, [r3, #108] @ 0x6c 800a990: 2b01 cmp r3, #1 800a992: d12e bne.n 800a9f2 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800a994: 687b ldr r3, [r7, #4] 800a996: 2200 movs r2, #0 800a998: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800a99a: 687b ldr r3, [r7, #4] 800a99c: 681b ldr r3, [r3, #0] 800a99e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800a9a0: 68fb ldr r3, [r7, #12] 800a9a2: e853 3f00 ldrex r3, [r3] 800a9a6: 60bb str r3, [r7, #8] return(result); 800a9a8: 68bb ldr r3, [r7, #8] 800a9aa: f023 0310 bic.w r3, r3, #16 800a9ae: 65bb str r3, [r7, #88] @ 0x58 800a9b0: 687b ldr r3, [r7, #4] 800a9b2: 681b ldr r3, [r3, #0] 800a9b4: 461a mov r2, r3 800a9b6: 6dbb ldr r3, [r7, #88] @ 0x58 800a9b8: 61bb str r3, [r7, #24] 800a9ba: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800a9bc: 6979 ldr r1, [r7, #20] 800a9be: 69ba ldr r2, [r7, #24] 800a9c0: e841 2300 strex r3, r2, [r1] 800a9c4: 613b str r3, [r7, #16] return(result); 800a9c6: 693b ldr r3, [r7, #16] 800a9c8: 2b00 cmp r3, #0 800a9ca: d1e6 bne.n 800a99a if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 800a9cc: 687b ldr r3, [r7, #4] 800a9ce: 681b ldr r3, [r3, #0] 800a9d0: 69db ldr r3, [r3, #28] 800a9d2: f003 0310 and.w r3, r3, #16 800a9d6: 2b10 cmp r3, #16 800a9d8: d103 bne.n 800a9e2 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800a9da: 687b ldr r3, [r7, #4] 800a9dc: 681b ldr r3, [r3, #0] 800a9de: 2210 movs r2, #16 800a9e0: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800a9e2: 687b ldr r3, [r7, #4] 800a9e4: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800a9e8: 4619 mov r1, r3 800a9ea: 6878 ldr r0, [r7, #4] 800a9ec: f7f7 f920 bl 8001c30 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 800a9f0: e00b b.n 800aa0a HAL_UART_RxCpltCallback(huart); 800a9f2: 6878 ldr r0, [r7, #4] 800a9f4: f7f7 f912 bl 8001c1c } 800a9f8: e007 b.n 800aa0a __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800a9fa: 687b ldr r3, [r7, #4] 800a9fc: 681b ldr r3, [r3, #0] 800a9fe: 699a ldr r2, [r3, #24] 800aa00: 687b ldr r3, [r7, #4] 800aa02: 681b ldr r3, [r3, #0] 800aa04: f042 0208 orr.w r2, r2, #8 800aa08: 619a str r2, [r3, #24] } 800aa0a: bf00 nop 800aa0c: 3770 adds r7, #112 @ 0x70 800aa0e: 46bd mov sp, r7 800aa10: bd80 pop {r7, pc} 800aa12: bf00 nop 800aa14: 58000c00 .word 0x58000c00 0800aa18 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 800aa18: b580 push {r7, lr} 800aa1a: b0ac sub sp, #176 @ 0xb0 800aa1c: af00 add r7, sp, #0 800aa1e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 800aa20: 687b ldr r3, [r7, #4] 800aa22: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 800aa26: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 800aa2a: 687b ldr r3, [r7, #4] 800aa2c: 681b ldr r3, [r3, #0] 800aa2e: 69db ldr r3, [r3, #28] 800aa30: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 800aa34: 687b ldr r3, [r7, #4] 800aa36: 681b ldr r3, [r3, #0] 800aa38: 681b ldr r3, [r3, #0] 800aa3a: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 800aa3e: 687b ldr r3, [r7, #4] 800aa40: 681b ldr r3, [r3, #0] 800aa42: 689b ldr r3, [r3, #8] 800aa44: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800aa48: 687b ldr r3, [r7, #4] 800aa4a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800aa4e: 2b22 cmp r3, #34 @ 0x22 800aa50: f040 8180 bne.w 800ad54 { nb_rx_data = huart->NbRxDataToProcess; 800aa54: 687b ldr r3, [r7, #4] 800aa56: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 800aa5a: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800aa5e: e123 b.n 800aca8 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800aa60: 687b ldr r3, [r7, #4] 800aa62: 681b ldr r3, [r3, #0] 800aa64: 6a5b ldr r3, [r3, #36] @ 0x24 800aa66: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 800aa6a: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 800aa6e: b2d9 uxtb r1, r3 800aa70: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 800aa74: b2da uxtb r2, r3 800aa76: 687b ldr r3, [r7, #4] 800aa78: 6d9b ldr r3, [r3, #88] @ 0x58 800aa7a: 400a ands r2, r1 800aa7c: b2d2 uxtb r2, r2 800aa7e: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 800aa80: 687b ldr r3, [r7, #4] 800aa82: 6d9b ldr r3, [r3, #88] @ 0x58 800aa84: 1c5a adds r2, r3, #1 800aa86: 687b ldr r3, [r7, #4] 800aa88: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 800aa8a: 687b ldr r3, [r7, #4] 800aa8c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800aa90: b29b uxth r3, r3 800aa92: 3b01 subs r3, #1 800aa94: b29a uxth r2, r3 800aa96: 687b ldr r3, [r7, #4] 800aa98: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 800aa9c: 687b ldr r3, [r7, #4] 800aa9e: 681b ldr r3, [r3, #0] 800aaa0: 69db ldr r3, [r3, #28] 800aaa2: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 800aaa6: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800aaaa: f003 0307 and.w r3, r3, #7 800aaae: 2b00 cmp r3, #0 800aab0: d053 beq.n 800ab5a { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800aab2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800aab6: f003 0301 and.w r3, r3, #1 800aaba: 2b00 cmp r3, #0 800aabc: d011 beq.n 800aae2 800aabe: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 800aac2: f403 7380 and.w r3, r3, #256 @ 0x100 800aac6: 2b00 cmp r3, #0 800aac8: d00b beq.n 800aae2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 800aaca: 687b ldr r3, [r7, #4] 800aacc: 681b ldr r3, [r3, #0] 800aace: 2201 movs r2, #1 800aad0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 800aad2: 687b ldr r3, [r7, #4] 800aad4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800aad8: f043 0201 orr.w r2, r3, #1 800aadc: 687b ldr r3, [r7, #4] 800aade: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800aae2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800aae6: f003 0302 and.w r3, r3, #2 800aaea: 2b00 cmp r3, #0 800aaec: d011 beq.n 800ab12 800aaee: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800aaf2: f003 0301 and.w r3, r3, #1 800aaf6: 2b00 cmp r3, #0 800aaf8: d00b beq.n 800ab12 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 800aafa: 687b ldr r3, [r7, #4] 800aafc: 681b ldr r3, [r3, #0] 800aafe: 2202 movs r2, #2 800ab00: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 800ab02: 687b ldr r3, [r7, #4] 800ab04: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ab08: f043 0204 orr.w r2, r3, #4 800ab0c: 687b ldr r3, [r7, #4] 800ab0e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ab12: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800ab16: f003 0304 and.w r3, r3, #4 800ab1a: 2b00 cmp r3, #0 800ab1c: d011 beq.n 800ab42 800ab1e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800ab22: f003 0301 and.w r3, r3, #1 800ab26: 2b00 cmp r3, #0 800ab28: d00b beq.n 800ab42 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 800ab2a: 687b ldr r3, [r7, #4] 800ab2c: 681b ldr r3, [r3, #0] 800ab2e: 2204 movs r2, #4 800ab30: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 800ab32: 687b ldr r3, [r7, #4] 800ab34: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ab38: f043 0202 orr.w r2, r3, #2 800ab3c: 687b ldr r3, [r7, #4] 800ab3e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800ab42: 687b ldr r3, [r7, #4] 800ab44: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ab48: 2b00 cmp r3, #0 800ab4a: d006 beq.n 800ab5a #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800ab4c: 6878 ldr r0, [r7, #4] 800ab4e: f7fe fb13 bl 8009178 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800ab52: 687b ldr r3, [r7, #4] 800ab54: 2200 movs r2, #0 800ab56: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 800ab5a: 687b ldr r3, [r7, #4] 800ab5c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800ab60: b29b uxth r3, r3 800ab62: 2b00 cmp r3, #0 800ab64: f040 80a0 bne.w 800aca8 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800ab68: 687b ldr r3, [r7, #4] 800ab6a: 681b ldr r3, [r3, #0] 800ab6c: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ab6e: 6f3b ldr r3, [r7, #112] @ 0x70 800ab70: e853 3f00 ldrex r3, [r3] 800ab74: 66fb str r3, [r7, #108] @ 0x6c return(result); 800ab76: 6efb ldr r3, [r7, #108] @ 0x6c 800ab78: f423 7380 bic.w r3, r3, #256 @ 0x100 800ab7c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800ab80: 687b ldr r3, [r7, #4] 800ab82: 681b ldr r3, [r3, #0] 800ab84: 461a mov r2, r3 800ab86: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 800ab8a: 67fb str r3, [r7, #124] @ 0x7c 800ab8c: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ab8e: 6fb9 ldr r1, [r7, #120] @ 0x78 800ab90: 6ffa ldr r2, [r7, #124] @ 0x7c 800ab92: e841 2300 strex r3, r2, [r1] 800ab96: 677b str r3, [r7, #116] @ 0x74 return(result); 800ab98: 6f7b ldr r3, [r7, #116] @ 0x74 800ab9a: 2b00 cmp r3, #0 800ab9c: d1e4 bne.n 800ab68 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800ab9e: 687b ldr r3, [r7, #4] 800aba0: 681b ldr r3, [r3, #0] 800aba2: 3308 adds r3, #8 800aba4: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800aba6: 6dfb ldr r3, [r7, #92] @ 0x5c 800aba8: e853 3f00 ldrex r3, [r3] 800abac: 65bb str r3, [r7, #88] @ 0x58 return(result); 800abae: 6dba ldr r2, [r7, #88] @ 0x58 800abb0: 4b6e ldr r3, [pc, #440] @ (800ad6c ) 800abb2: 4013 ands r3, r2 800abb4: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800abb8: 687b ldr r3, [r7, #4] 800abba: 681b ldr r3, [r3, #0] 800abbc: 3308 adds r3, #8 800abbe: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 800abc2: 66ba str r2, [r7, #104] @ 0x68 800abc4: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800abc6: 6e79 ldr r1, [r7, #100] @ 0x64 800abc8: 6eba ldr r2, [r7, #104] @ 0x68 800abca: e841 2300 strex r3, r2, [r1] 800abce: 663b str r3, [r7, #96] @ 0x60 return(result); 800abd0: 6e3b ldr r3, [r7, #96] @ 0x60 800abd2: 2b00 cmp r3, #0 800abd4: d1e3 bne.n 800ab9e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800abd6: 687b ldr r3, [r7, #4] 800abd8: 2220 movs r2, #32 800abda: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 800abde: 687b ldr r3, [r7, #4] 800abe0: 2200 movs r2, #0 800abe2: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800abe4: 687b ldr r3, [r7, #4] 800abe6: 2200 movs r2, #0 800abe8: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800abea: 687b ldr r3, [r7, #4] 800abec: 681b ldr r3, [r3, #0] 800abee: 4a60 ldr r2, [pc, #384] @ (800ad70 ) 800abf0: 4293 cmp r3, r2 800abf2: d021 beq.n 800ac38 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 800abf4: 687b ldr r3, [r7, #4] 800abf6: 681b ldr r3, [r3, #0] 800abf8: 685b ldr r3, [r3, #4] 800abfa: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800abfe: 2b00 cmp r3, #0 800ac00: d01a beq.n 800ac38 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800ac02: 687b ldr r3, [r7, #4] 800ac04: 681b ldr r3, [r3, #0] 800ac06: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ac08: 6cbb ldr r3, [r7, #72] @ 0x48 800ac0a: e853 3f00 ldrex r3, [r3] 800ac0e: 647b str r3, [r7, #68] @ 0x44 return(result); 800ac10: 6c7b ldr r3, [r7, #68] @ 0x44 800ac12: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800ac16: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800ac1a: 687b ldr r3, [r7, #4] 800ac1c: 681b ldr r3, [r3, #0] 800ac1e: 461a mov r2, r3 800ac20: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800ac24: 657b str r3, [r7, #84] @ 0x54 800ac26: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ac28: 6d39 ldr r1, [r7, #80] @ 0x50 800ac2a: 6d7a ldr r2, [r7, #84] @ 0x54 800ac2c: e841 2300 strex r3, r2, [r1] 800ac30: 64fb str r3, [r7, #76] @ 0x4c return(result); 800ac32: 6cfb ldr r3, [r7, #76] @ 0x4c 800ac34: 2b00 cmp r3, #0 800ac36: d1e4 bne.n 800ac02 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800ac38: 687b ldr r3, [r7, #4] 800ac3a: 6edb ldr r3, [r3, #108] @ 0x6c 800ac3c: 2b01 cmp r3, #1 800ac3e: d130 bne.n 800aca2 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800ac40: 687b ldr r3, [r7, #4] 800ac42: 2200 movs r2, #0 800ac44: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800ac46: 687b ldr r3, [r7, #4] 800ac48: 681b ldr r3, [r3, #0] 800ac4a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ac4c: 6b7b ldr r3, [r7, #52] @ 0x34 800ac4e: e853 3f00 ldrex r3, [r3] 800ac52: 633b str r3, [r7, #48] @ 0x30 return(result); 800ac54: 6b3b ldr r3, [r7, #48] @ 0x30 800ac56: f023 0310 bic.w r3, r3, #16 800ac5a: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800ac5e: 687b ldr r3, [r7, #4] 800ac60: 681b ldr r3, [r3, #0] 800ac62: 461a mov r2, r3 800ac64: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800ac68: 643b str r3, [r7, #64] @ 0x40 800ac6a: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ac6c: 6bf9 ldr r1, [r7, #60] @ 0x3c 800ac6e: 6c3a ldr r2, [r7, #64] @ 0x40 800ac70: e841 2300 strex r3, r2, [r1] 800ac74: 63bb str r3, [r7, #56] @ 0x38 return(result); 800ac76: 6bbb ldr r3, [r7, #56] @ 0x38 800ac78: 2b00 cmp r3, #0 800ac7a: d1e4 bne.n 800ac46 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 800ac7c: 687b ldr r3, [r7, #4] 800ac7e: 681b ldr r3, [r3, #0] 800ac80: 69db ldr r3, [r3, #28] 800ac82: f003 0310 and.w r3, r3, #16 800ac86: 2b10 cmp r3, #16 800ac88: d103 bne.n 800ac92 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800ac8a: 687b ldr r3, [r7, #4] 800ac8c: 681b ldr r3, [r3, #0] 800ac8e: 2210 movs r2, #16 800ac90: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800ac92: 687b ldr r3, [r7, #4] 800ac94: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800ac98: 4619 mov r1, r3 800ac9a: 6878 ldr r0, [r7, #4] 800ac9c: f7f6 ffc8 bl 8001c30 800aca0: e002 b.n 800aca8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 800aca2: 6878 ldr r0, [r7, #4] 800aca4: f7f6 ffba bl 8001c1c while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800aca8: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 800acac: 2b00 cmp r3, #0 800acae: d006 beq.n 800acbe 800acb0: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800acb4: f003 0320 and.w r3, r3, #32 800acb8: 2b00 cmp r3, #0 800acba: f47f aed1 bne.w 800aa60 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 800acbe: 687b ldr r3, [r7, #4] 800acc0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800acc4: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 800acc8: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 800accc: 2b00 cmp r3, #0 800acce: d049 beq.n 800ad64 800acd0: 687b ldr r3, [r7, #4] 800acd2: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 800acd6: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 800acda: 429a cmp r2, r3 800acdc: d242 bcs.n 800ad64 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 800acde: 687b ldr r3, [r7, #4] 800ace0: 681b ldr r3, [r3, #0] 800ace2: 3308 adds r3, #8 800ace4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ace6: 6a3b ldr r3, [r7, #32] 800ace8: e853 3f00 ldrex r3, [r3] 800acec: 61fb str r3, [r7, #28] return(result); 800acee: 69fb ldr r3, [r7, #28] 800acf0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800acf4: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800acf8: 687b ldr r3, [r7, #4] 800acfa: 681b ldr r3, [r3, #0] 800acfc: 3308 adds r3, #8 800acfe: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 800ad02: 62fa str r2, [r7, #44] @ 0x2c 800ad04: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ad06: 6ab9 ldr r1, [r7, #40] @ 0x28 800ad08: 6afa ldr r2, [r7, #44] @ 0x2c 800ad0a: e841 2300 strex r3, r2, [r1] 800ad0e: 627b str r3, [r7, #36] @ 0x24 return(result); 800ad10: 6a7b ldr r3, [r7, #36] @ 0x24 800ad12: 2b00 cmp r3, #0 800ad14: d1e3 bne.n 800acde /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 800ad16: 687b ldr r3, [r7, #4] 800ad18: 4a16 ldr r2, [pc, #88] @ (800ad74 ) 800ad1a: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 800ad1c: 687b ldr r3, [r7, #4] 800ad1e: 681b ldr r3, [r3, #0] 800ad20: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800ad22: 68fb ldr r3, [r7, #12] 800ad24: e853 3f00 ldrex r3, [r3] 800ad28: 60bb str r3, [r7, #8] return(result); 800ad2a: 68bb ldr r3, [r7, #8] 800ad2c: f043 0320 orr.w r3, r3, #32 800ad30: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800ad34: 687b ldr r3, [r7, #4] 800ad36: 681b ldr r3, [r3, #0] 800ad38: 461a mov r2, r3 800ad3a: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800ad3e: 61bb str r3, [r7, #24] 800ad40: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800ad42: 6979 ldr r1, [r7, #20] 800ad44: 69ba ldr r2, [r7, #24] 800ad46: e841 2300 strex r3, r2, [r1] 800ad4a: 613b str r3, [r7, #16] return(result); 800ad4c: 693b ldr r3, [r7, #16] 800ad4e: 2b00 cmp r3, #0 800ad50: d1e4 bne.n 800ad1c else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 800ad52: e007 b.n 800ad64 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800ad54: 687b ldr r3, [r7, #4] 800ad56: 681b ldr r3, [r3, #0] 800ad58: 699a ldr r2, [r3, #24] 800ad5a: 687b ldr r3, [r7, #4] 800ad5c: 681b ldr r3, [r3, #0] 800ad5e: f042 0208 orr.w r2, r2, #8 800ad62: 619a str r2, [r3, #24] } 800ad64: bf00 nop 800ad66: 37b0 adds r7, #176 @ 0xb0 800ad68: 46bd mov sp, r7 800ad6a: bd80 pop {r7, pc} 800ad6c: effffffe .word 0xeffffffe 800ad70: 58000c00 .word 0x58000c00 800ad74: 0800a6a9 .word 0x0800a6a9 0800ad78 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 800ad78: b580 push {r7, lr} 800ad7a: b0ae sub sp, #184 @ 0xb8 800ad7c: af00 add r7, sp, #0 800ad7e: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 800ad80: 687b ldr r3, [r7, #4] 800ad82: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 800ad86: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 800ad8a: 687b ldr r3, [r7, #4] 800ad8c: 681b ldr r3, [r3, #0] 800ad8e: 69db ldr r3, [r3, #28] 800ad90: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 800ad94: 687b ldr r3, [r7, #4] 800ad96: 681b ldr r3, [r3, #0] 800ad98: 681b ldr r3, [r3, #0] 800ad9a: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 800ad9e: 687b ldr r3, [r7, #4] 800ada0: 681b ldr r3, [r3, #0] 800ada2: 689b ldr r3, [r3, #8] 800ada4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 800ada8: 687b ldr r3, [r7, #4] 800adaa: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800adae: 2b22 cmp r3, #34 @ 0x22 800adb0: f040 8184 bne.w 800b0bc { nb_rx_data = huart->NbRxDataToProcess; 800adb4: 687b ldr r3, [r7, #4] 800adb6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 800adba: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800adbe: e127 b.n 800b010 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 800adc0: 687b ldr r3, [r7, #4] 800adc2: 681b ldr r3, [r3, #0] 800adc4: 6a5b ldr r3, [r3, #36] @ 0x24 800adc6: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 800adca: 687b ldr r3, [r7, #4] 800adcc: 6d9b ldr r3, [r3, #88] @ 0x58 800adce: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 800add2: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 800add6: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 800adda: 4013 ands r3, r2 800addc: b29a uxth r2, r3 800adde: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 800ade2: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 800ade4: 687b ldr r3, [r7, #4] 800ade6: 6d9b ldr r3, [r3, #88] @ 0x58 800ade8: 1c9a adds r2, r3, #2 800adea: 687b ldr r3, [r7, #4] 800adec: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 800adee: 687b ldr r3, [r7, #4] 800adf0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800adf4: b29b uxth r3, r3 800adf6: 3b01 subs r3, #1 800adf8: b29a uxth r2, r3 800adfa: 687b ldr r3, [r7, #4] 800adfc: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 800ae00: 687b ldr r3, [r7, #4] 800ae02: 681b ldr r3, [r3, #0] 800ae04: 69db ldr r3, [r3, #28] 800ae06: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 800ae0a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800ae0e: f003 0307 and.w r3, r3, #7 800ae12: 2b00 cmp r3, #0 800ae14: d053 beq.n 800aebe { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 800ae16: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800ae1a: f003 0301 and.w r3, r3, #1 800ae1e: 2b00 cmp r3, #0 800ae20: d011 beq.n 800ae46 800ae22: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 800ae26: f403 7380 and.w r3, r3, #256 @ 0x100 800ae2a: 2b00 cmp r3, #0 800ae2c: d00b beq.n 800ae46 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 800ae2e: 687b ldr r3, [r7, #4] 800ae30: 681b ldr r3, [r3, #0] 800ae32: 2201 movs r2, #1 800ae34: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 800ae36: 687b ldr r3, [r7, #4] 800ae38: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ae3c: f043 0201 orr.w r2, r3, #1 800ae40: 687b ldr r3, [r7, #4] 800ae42: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ae46: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800ae4a: f003 0302 and.w r3, r3, #2 800ae4e: 2b00 cmp r3, #0 800ae50: d011 beq.n 800ae76 800ae52: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800ae56: f003 0301 and.w r3, r3, #1 800ae5a: 2b00 cmp r3, #0 800ae5c: d00b beq.n 800ae76 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 800ae5e: 687b ldr r3, [r7, #4] 800ae60: 681b ldr r3, [r3, #0] 800ae62: 2202 movs r2, #2 800ae64: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 800ae66: 687b ldr r3, [r7, #4] 800ae68: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ae6c: f043 0204 orr.w r2, r3, #4 800ae70: 687b ldr r3, [r7, #4] 800ae72: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 800ae76: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800ae7a: f003 0304 and.w r3, r3, #4 800ae7e: 2b00 cmp r3, #0 800ae80: d011 beq.n 800aea6 800ae82: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 800ae86: f003 0301 and.w r3, r3, #1 800ae8a: 2b00 cmp r3, #0 800ae8c: d00b beq.n 800aea6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 800ae8e: 687b ldr r3, [r7, #4] 800ae90: 681b ldr r3, [r3, #0] 800ae92: 2204 movs r2, #4 800ae94: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 800ae96: 687b ldr r3, [r7, #4] 800ae98: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ae9c: f043 0202 orr.w r2, r3, #2 800aea0: 687b ldr r3, [r7, #4] 800aea2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 800aea6: 687b ldr r3, [r7, #4] 800aea8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800aeac: 2b00 cmp r3, #0 800aeae: d006 beq.n 800aebe #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 800aeb0: 6878 ldr r0, [r7, #4] 800aeb2: f7fe f961 bl 8009178 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 800aeb6: 687b ldr r3, [r7, #4] 800aeb8: 2200 movs r2, #0 800aeba: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 800aebe: 687b ldr r3, [r7, #4] 800aec0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800aec4: b29b uxth r3, r3 800aec6: 2b00 cmp r3, #0 800aec8: f040 80a2 bne.w 800b010 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800aecc: 687b ldr r3, [r7, #4] 800aece: 681b ldr r3, [r3, #0] 800aed0: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800aed2: 6f7b ldr r3, [r7, #116] @ 0x74 800aed4: e853 3f00 ldrex r3, [r3] 800aed8: 673b str r3, [r7, #112] @ 0x70 return(result); 800aeda: 6f3b ldr r3, [r7, #112] @ 0x70 800aedc: f423 7380 bic.w r3, r3, #256 @ 0x100 800aee0: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800aee4: 687b ldr r3, [r7, #4] 800aee6: 681b ldr r3, [r3, #0] 800aee8: 461a mov r2, r3 800aeea: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 800aeee: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800aef2: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800aef4: 6ff9 ldr r1, [r7, #124] @ 0x7c 800aef6: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 800aefa: e841 2300 strex r3, r2, [r1] 800aefe: 67bb str r3, [r7, #120] @ 0x78 return(result); 800af00: 6fbb ldr r3, [r7, #120] @ 0x78 800af02: 2b00 cmp r3, #0 800af04: d1e2 bne.n 800aecc /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 800af06: 687b ldr r3, [r7, #4] 800af08: 681b ldr r3, [r3, #0] 800af0a: 3308 adds r3, #8 800af0c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800af0e: 6e3b ldr r3, [r7, #96] @ 0x60 800af10: e853 3f00 ldrex r3, [r3] 800af14: 65fb str r3, [r7, #92] @ 0x5c return(result); 800af16: 6dfa ldr r2, [r7, #92] @ 0x5c 800af18: 4b6e ldr r3, [pc, #440] @ (800b0d4 ) 800af1a: 4013 ands r3, r2 800af1c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800af20: 687b ldr r3, [r7, #4] 800af22: 681b ldr r3, [r3, #0] 800af24: 3308 adds r3, #8 800af26: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 800af2a: 66fa str r2, [r7, #108] @ 0x6c 800af2c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800af2e: 6eb9 ldr r1, [r7, #104] @ 0x68 800af30: 6efa ldr r2, [r7, #108] @ 0x6c 800af32: e841 2300 strex r3, r2, [r1] 800af36: 667b str r3, [r7, #100] @ 0x64 return(result); 800af38: 6e7b ldr r3, [r7, #100] @ 0x64 800af3a: 2b00 cmp r3, #0 800af3c: d1e3 bne.n 800af06 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800af3e: 687b ldr r3, [r7, #4] 800af40: 2220 movs r2, #32 800af42: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 800af46: 687b ldr r3, [r7, #4] 800af48: 2200 movs r2, #0 800af4a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800af4c: 687b ldr r3, [r7, #4] 800af4e: 2200 movs r2, #0 800af50: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 800af52: 687b ldr r3, [r7, #4] 800af54: 681b ldr r3, [r3, #0] 800af56: 4a60 ldr r2, [pc, #384] @ (800b0d8 ) 800af58: 4293 cmp r3, r2 800af5a: d021 beq.n 800afa0 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 800af5c: 687b ldr r3, [r7, #4] 800af5e: 681b ldr r3, [r3, #0] 800af60: 685b ldr r3, [r3, #4] 800af62: f403 0300 and.w r3, r3, #8388608 @ 0x800000 800af66: 2b00 cmp r3, #0 800af68: d01a beq.n 800afa0 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 800af6a: 687b ldr r3, [r7, #4] 800af6c: 681b ldr r3, [r3, #0] 800af6e: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800af70: 6cfb ldr r3, [r7, #76] @ 0x4c 800af72: e853 3f00 ldrex r3, [r3] 800af76: 64bb str r3, [r7, #72] @ 0x48 return(result); 800af78: 6cbb ldr r3, [r7, #72] @ 0x48 800af7a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800af7e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800af82: 687b ldr r3, [r7, #4] 800af84: 681b ldr r3, [r3, #0] 800af86: 461a mov r2, r3 800af88: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 800af8c: 65bb str r3, [r7, #88] @ 0x58 800af8e: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800af90: 6d79 ldr r1, [r7, #84] @ 0x54 800af92: 6dba ldr r2, [r7, #88] @ 0x58 800af94: e841 2300 strex r3, r2, [r1] 800af98: 653b str r3, [r7, #80] @ 0x50 return(result); 800af9a: 6d3b ldr r3, [r7, #80] @ 0x50 800af9c: 2b00 cmp r3, #0 800af9e: d1e4 bne.n 800af6a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800afa0: 687b ldr r3, [r7, #4] 800afa2: 6edb ldr r3, [r3, #108] @ 0x6c 800afa4: 2b01 cmp r3, #1 800afa6: d130 bne.n 800b00a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 800afa8: 687b ldr r3, [r7, #4] 800afaa: 2200 movs r2, #0 800afac: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800afae: 687b ldr r3, [r7, #4] 800afb0: 681b ldr r3, [r3, #0] 800afb2: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800afb4: 6bbb ldr r3, [r7, #56] @ 0x38 800afb6: e853 3f00 ldrex r3, [r3] 800afba: 637b str r3, [r7, #52] @ 0x34 return(result); 800afbc: 6b7b ldr r3, [r7, #52] @ 0x34 800afbe: f023 0310 bic.w r3, r3, #16 800afc2: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800afc6: 687b ldr r3, [r7, #4] 800afc8: 681b ldr r3, [r3, #0] 800afca: 461a mov r2, r3 800afcc: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 800afd0: 647b str r3, [r7, #68] @ 0x44 800afd2: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800afd4: 6c39 ldr r1, [r7, #64] @ 0x40 800afd6: 6c7a ldr r2, [r7, #68] @ 0x44 800afd8: e841 2300 strex r3, r2, [r1] 800afdc: 63fb str r3, [r7, #60] @ 0x3c return(result); 800afde: 6bfb ldr r3, [r7, #60] @ 0x3c 800afe0: 2b00 cmp r3, #0 800afe2: d1e4 bne.n 800afae if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 800afe4: 687b ldr r3, [r7, #4] 800afe6: 681b ldr r3, [r3, #0] 800afe8: 69db ldr r3, [r3, #28] 800afea: f003 0310 and.w r3, r3, #16 800afee: 2b10 cmp r3, #16 800aff0: d103 bne.n 800affa { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800aff2: 687b ldr r3, [r7, #4] 800aff4: 681b ldr r3, [r3, #0] 800aff6: 2210 movs r2, #16 800aff8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 800affa: 687b ldr r3, [r7, #4] 800affc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 800b000: 4619 mov r1, r3 800b002: 6878 ldr r0, [r7, #4] 800b004: f7f6 fe14 bl 8001c30 800b008: e002 b.n 800b010 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 800b00a: 6878 ldr r0, [r7, #4] 800b00c: f7f6 fe06 bl 8001c1c while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 800b010: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 800b014: 2b00 cmp r3, #0 800b016: d006 beq.n 800b026 800b018: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 800b01c: f003 0320 and.w r3, r3, #32 800b020: 2b00 cmp r3, #0 800b022: f47f aecd bne.w 800adc0 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 800b026: 687b ldr r3, [r7, #4] 800b028: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 800b02c: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 800b030: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 800b034: 2b00 cmp r3, #0 800b036: d049 beq.n 800b0cc 800b038: 687b ldr r3, [r7, #4] 800b03a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 800b03e: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 800b042: 429a cmp r2, r3 800b044: d242 bcs.n 800b0cc { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 800b046: 687b ldr r3, [r7, #4] 800b048: 681b ldr r3, [r3, #0] 800b04a: 3308 adds r3, #8 800b04c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b04e: 6a7b ldr r3, [r7, #36] @ 0x24 800b050: e853 3f00 ldrex r3, [r3] 800b054: 623b str r3, [r7, #32] return(result); 800b056: 6a3b ldr r3, [r7, #32] 800b058: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800b05c: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800b060: 687b ldr r3, [r7, #4] 800b062: 681b ldr r3, [r3, #0] 800b064: 3308 adds r3, #8 800b066: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 800b06a: 633a str r2, [r7, #48] @ 0x30 800b06c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b06e: 6af9 ldr r1, [r7, #44] @ 0x2c 800b070: 6b3a ldr r2, [r7, #48] @ 0x30 800b072: e841 2300 strex r3, r2, [r1] 800b076: 62bb str r3, [r7, #40] @ 0x28 return(result); 800b078: 6abb ldr r3, [r7, #40] @ 0x28 800b07a: 2b00 cmp r3, #0 800b07c: d1e3 bne.n 800b046 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 800b07e: 687b ldr r3, [r7, #4] 800b080: 4a16 ldr r2, [pc, #88] @ (800b0dc ) 800b082: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 800b084: 687b ldr r3, [r7, #4] 800b086: 681b ldr r3, [r3, #0] 800b088: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b08a: 693b ldr r3, [r7, #16] 800b08c: e853 3f00 ldrex r3, [r3] 800b090: 60fb str r3, [r7, #12] return(result); 800b092: 68fb ldr r3, [r7, #12] 800b094: f043 0320 orr.w r3, r3, #32 800b098: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800b09c: 687b ldr r3, [r7, #4] 800b09e: 681b ldr r3, [r3, #0] 800b0a0: 461a mov r2, r3 800b0a2: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800b0a6: 61fb str r3, [r7, #28] 800b0a8: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b0aa: 69b9 ldr r1, [r7, #24] 800b0ac: 69fa ldr r2, [r7, #28] 800b0ae: e841 2300 strex r3, r2, [r1] 800b0b2: 617b str r3, [r7, #20] return(result); 800b0b4: 697b ldr r3, [r7, #20] 800b0b6: 2b00 cmp r3, #0 800b0b8: d1e4 bne.n 800b084 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 800b0ba: e007 b.n 800b0cc __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 800b0bc: 687b ldr r3, [r7, #4] 800b0be: 681b ldr r3, [r3, #0] 800b0c0: 699a ldr r2, [r3, #24] 800b0c2: 687b ldr r3, [r7, #4] 800b0c4: 681b ldr r3, [r3, #0] 800b0c6: f042 0208 orr.w r2, r2, #8 800b0ca: 619a str r2, [r3, #24] } 800b0cc: bf00 nop 800b0ce: 37b8 adds r7, #184 @ 0xb8 800b0d0: 46bd mov sp, r7 800b0d2: bd80 pop {r7, pc} 800b0d4: effffffe .word 0xeffffffe 800b0d8: 58000c00 .word 0x58000c00 800b0dc: 0800a861 .word 0x0800a861 0800b0e0 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 800b0e0: b480 push {r7} 800b0e2: b083 sub sp, #12 800b0e4: af00 add r7, sp, #0 800b0e6: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 800b0e8: bf00 nop 800b0ea: 370c adds r7, #12 800b0ec: 46bd mov sp, r7 800b0ee: f85d 7b04 ldr.w r7, [sp], #4 800b0f2: 4770 bx lr 0800b0f4 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 800b0f4: b480 push {r7} 800b0f6: b083 sub sp, #12 800b0f8: af00 add r7, sp, #0 800b0fa: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 800b0fc: bf00 nop 800b0fe: 370c adds r7, #12 800b100: 46bd mov sp, r7 800b102: f85d 7b04 ldr.w r7, [sp], #4 800b106: 4770 bx lr 0800b108 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 800b108: b480 push {r7} 800b10a: b083 sub sp, #12 800b10c: af00 add r7, sp, #0 800b10e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 800b110: bf00 nop 800b112: 370c adds r7, #12 800b114: 46bd mov sp, r7 800b116: f85d 7b04 ldr.w r7, [sp], #4 800b11a: 4770 bx lr 0800b11c : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 800b11c: b480 push {r7} 800b11e: b085 sub sp, #20 800b120: af00 add r7, sp, #0 800b122: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 800b124: 687b ldr r3, [r7, #4] 800b126: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800b12a: 2b01 cmp r3, #1 800b12c: d101 bne.n 800b132 800b12e: 2302 movs r3, #2 800b130: e027 b.n 800b182 800b132: 687b ldr r3, [r7, #4] 800b134: 2201 movs r2, #1 800b136: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800b13a: 687b ldr r3, [r7, #4] 800b13c: 2224 movs r2, #36 @ 0x24 800b13e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800b142: 687b ldr r3, [r7, #4] 800b144: 681b ldr r3, [r3, #0] 800b146: 681b ldr r3, [r3, #0] 800b148: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800b14a: 687b ldr r3, [r7, #4] 800b14c: 681b ldr r3, [r3, #0] 800b14e: 681a ldr r2, [r3, #0] 800b150: 687b ldr r3, [r7, #4] 800b152: 681b ldr r3, [r3, #0] 800b154: f022 0201 bic.w r2, r2, #1 800b158: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 800b15a: 68fb ldr r3, [r7, #12] 800b15c: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 800b160: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 800b162: 687b ldr r3, [r7, #4] 800b164: 2200 movs r2, #0 800b166: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800b168: 687b ldr r3, [r7, #4] 800b16a: 681b ldr r3, [r3, #0] 800b16c: 68fa ldr r2, [r7, #12] 800b16e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800b170: 687b ldr r3, [r7, #4] 800b172: 2220 movs r2, #32 800b174: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800b178: 687b ldr r3, [r7, #4] 800b17a: 2200 movs r2, #0 800b17c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 800b180: 2300 movs r3, #0 } 800b182: 4618 mov r0, r3 800b184: 3714 adds r7, #20 800b186: 46bd mov sp, r7 800b188: f85d 7b04 ldr.w r7, [sp], #4 800b18c: 4770 bx lr 0800b18e : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800b18e: b580 push {r7, lr} 800b190: b084 sub sp, #16 800b192: af00 add r7, sp, #0 800b194: 6078 str r0, [r7, #4] 800b196: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800b198: 687b ldr r3, [r7, #4] 800b19a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800b19e: 2b01 cmp r3, #1 800b1a0: d101 bne.n 800b1a6 800b1a2: 2302 movs r3, #2 800b1a4: e02d b.n 800b202 800b1a6: 687b ldr r3, [r7, #4] 800b1a8: 2201 movs r2, #1 800b1aa: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800b1ae: 687b ldr r3, [r7, #4] 800b1b0: 2224 movs r2, #36 @ 0x24 800b1b2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800b1b6: 687b ldr r3, [r7, #4] 800b1b8: 681b ldr r3, [r3, #0] 800b1ba: 681b ldr r3, [r3, #0] 800b1bc: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800b1be: 687b ldr r3, [r7, #4] 800b1c0: 681b ldr r3, [r3, #0] 800b1c2: 681a ldr r2, [r3, #0] 800b1c4: 687b ldr r3, [r7, #4] 800b1c6: 681b ldr r3, [r3, #0] 800b1c8: f022 0201 bic.w r2, r2, #1 800b1cc: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 800b1ce: 687b ldr r3, [r7, #4] 800b1d0: 681b ldr r3, [r3, #0] 800b1d2: 689b ldr r3, [r3, #8] 800b1d4: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 800b1d8: 687b ldr r3, [r7, #4] 800b1da: 681b ldr r3, [r3, #0] 800b1dc: 683a ldr r2, [r7, #0] 800b1de: 430a orrs r2, r1 800b1e0: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800b1e2: 6878 ldr r0, [r7, #4] 800b1e4: f000 f8a0 bl 800b328 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800b1e8: 687b ldr r3, [r7, #4] 800b1ea: 681b ldr r3, [r3, #0] 800b1ec: 68fa ldr r2, [r7, #12] 800b1ee: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800b1f0: 687b ldr r3, [r7, #4] 800b1f2: 2220 movs r2, #32 800b1f4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800b1f8: 687b ldr r3, [r7, #4] 800b1fa: 2200 movs r2, #0 800b1fc: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 800b200: 2300 movs r3, #0 } 800b202: 4618 mov r0, r3 800b204: 3710 adds r7, #16 800b206: 46bd mov sp, r7 800b208: bd80 pop {r7, pc} 0800b20a : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 800b20a: b580 push {r7, lr} 800b20c: b084 sub sp, #16 800b20e: af00 add r7, sp, #0 800b210: 6078 str r0, [r7, #4] 800b212: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 800b214: 687b ldr r3, [r7, #4] 800b216: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 800b21a: 2b01 cmp r3, #1 800b21c: d101 bne.n 800b222 800b21e: 2302 movs r3, #2 800b220: e02d b.n 800b27e 800b222: 687b ldr r3, [r7, #4] 800b224: 2201 movs r2, #1 800b226: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 800b22a: 687b ldr r3, [r7, #4] 800b22c: 2224 movs r2, #36 @ 0x24 800b22e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 800b232: 687b ldr r3, [r7, #4] 800b234: 681b ldr r3, [r3, #0] 800b236: 681b ldr r3, [r3, #0] 800b238: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 800b23a: 687b ldr r3, [r7, #4] 800b23c: 681b ldr r3, [r3, #0] 800b23e: 681a ldr r2, [r3, #0] 800b240: 687b ldr r3, [r7, #4] 800b242: 681b ldr r3, [r3, #0] 800b244: f022 0201 bic.w r2, r2, #1 800b248: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 800b24a: 687b ldr r3, [r7, #4] 800b24c: 681b ldr r3, [r3, #0] 800b24e: 689b ldr r3, [r3, #8] 800b250: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 800b254: 687b ldr r3, [r7, #4] 800b256: 681b ldr r3, [r3, #0] 800b258: 683a ldr r2, [r7, #0] 800b25a: 430a orrs r2, r1 800b25c: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 800b25e: 6878 ldr r0, [r7, #4] 800b260: f000 f862 bl 800b328 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 800b264: 687b ldr r3, [r7, #4] 800b266: 681b ldr r3, [r3, #0] 800b268: 68fa ldr r2, [r7, #12] 800b26a: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 800b26c: 687b ldr r3, [r7, #4] 800b26e: 2220 movs r2, #32 800b270: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 800b274: 687b ldr r3, [r7, #4] 800b276: 2200 movs r2, #0 800b278: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 800b27c: 2300 movs r3, #0 } 800b27e: 4618 mov r0, r3 800b280: 3710 adds r7, #16 800b282: 46bd mov sp, r7 800b284: bd80 pop {r7, pc} 0800b286 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 800b286: b580 push {r7, lr} 800b288: b08c sub sp, #48 @ 0x30 800b28a: af00 add r7, sp, #0 800b28c: 60f8 str r0, [r7, #12] 800b28e: 60b9 str r1, [r7, #8] 800b290: 4613 mov r3, r2 800b292: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 800b294: 2300 movs r3, #0 800b296: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 800b29a: 68fb ldr r3, [r7, #12] 800b29c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800b2a0: 2b20 cmp r3, #32 800b2a2: d13b bne.n 800b31c { if ((pData == NULL) || (Size == 0U)) 800b2a4: 68bb ldr r3, [r7, #8] 800b2a6: 2b00 cmp r3, #0 800b2a8: d002 beq.n 800b2b0 800b2aa: 88fb ldrh r3, [r7, #6] 800b2ac: 2b00 cmp r3, #0 800b2ae: d101 bne.n 800b2b4 { return HAL_ERROR; 800b2b0: 2301 movs r3, #1 800b2b2: e034 b.n 800b31e } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 800b2b4: 68fb ldr r3, [r7, #12] 800b2b6: 2201 movs r2, #1 800b2b8: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 800b2ba: 68fb ldr r3, [r7, #12] 800b2bc: 2200 movs r2, #0 800b2be: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 800b2c0: 88fb ldrh r3, [r7, #6] 800b2c2: 461a mov r2, r3 800b2c4: 68b9 ldr r1, [r7, #8] 800b2c6: 68f8 ldr r0, [r7, #12] 800b2c8: f7fe fe82 bl 8009fd0 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 800b2cc: 68fb ldr r3, [r7, #12] 800b2ce: 6edb ldr r3, [r3, #108] @ 0x6c 800b2d0: 2b01 cmp r3, #1 800b2d2: d11d bne.n 800b310 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 800b2d4: 68fb ldr r3, [r7, #12] 800b2d6: 681b ldr r3, [r3, #0] 800b2d8: 2210 movs r2, #16 800b2da: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 800b2dc: 68fb ldr r3, [r7, #12] 800b2de: 681b ldr r3, [r3, #0] 800b2e0: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 800b2e2: 69bb ldr r3, [r7, #24] 800b2e4: e853 3f00 ldrex r3, [r3] 800b2e8: 617b str r3, [r7, #20] return(result); 800b2ea: 697b ldr r3, [r7, #20] 800b2ec: f043 0310 orr.w r3, r3, #16 800b2f0: 62bb str r3, [r7, #40] @ 0x28 800b2f2: 68fb ldr r3, [r7, #12] 800b2f4: 681b ldr r3, [r3, #0] 800b2f6: 461a mov r2, r3 800b2f8: 6abb ldr r3, [r7, #40] @ 0x28 800b2fa: 627b str r3, [r7, #36] @ 0x24 800b2fc: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 800b2fe: 6a39 ldr r1, [r7, #32] 800b300: 6a7a ldr r2, [r7, #36] @ 0x24 800b302: e841 2300 strex r3, r2, [r1] 800b306: 61fb str r3, [r7, #28] return(result); 800b308: 69fb ldr r3, [r7, #28] 800b30a: 2b00 cmp r3, #0 800b30c: d1e6 bne.n 800b2dc 800b30e: e002 b.n 800b316 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 800b310: 2301 movs r3, #1 800b312: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 800b316: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 800b31a: e000 b.n 800b31e } else { return HAL_BUSY; 800b31c: 2302 movs r3, #2 } } 800b31e: 4618 mov r0, r3 800b320: 3730 adds r7, #48 @ 0x30 800b322: 46bd mov sp, r7 800b324: bd80 pop {r7, pc} ... 0800b328 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 800b328: b480 push {r7} 800b32a: b085 sub sp, #20 800b32c: af00 add r7, sp, #0 800b32e: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 800b330: 687b ldr r3, [r7, #4] 800b332: 6e5b ldr r3, [r3, #100] @ 0x64 800b334: 2b00 cmp r3, #0 800b336: d108 bne.n 800b34a { huart->NbTxDataToProcess = 1U; 800b338: 687b ldr r3, [r7, #4] 800b33a: 2201 movs r2, #1 800b33c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 800b340: 687b ldr r3, [r7, #4] 800b342: 2201 movs r2, #1 800b344: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 800b348: e031 b.n 800b3ae rx_fifo_depth = RX_FIFO_DEPTH; 800b34a: 2310 movs r3, #16 800b34c: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 800b34e: 2310 movs r3, #16 800b350: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 800b352: 687b ldr r3, [r7, #4] 800b354: 681b ldr r3, [r3, #0] 800b356: 689b ldr r3, [r3, #8] 800b358: 0e5b lsrs r3, r3, #25 800b35a: b2db uxtb r3, r3 800b35c: f003 0307 and.w r3, r3, #7 800b360: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 800b362: 687b ldr r3, [r7, #4] 800b364: 681b ldr r3, [r3, #0] 800b366: 689b ldr r3, [r3, #8] 800b368: 0f5b lsrs r3, r3, #29 800b36a: b2db uxtb r3, r3 800b36c: f003 0307 and.w r3, r3, #7 800b370: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800b372: 7bbb ldrb r3, [r7, #14] 800b374: 7b3a ldrb r2, [r7, #12] 800b376: 4911 ldr r1, [pc, #68] @ (800b3bc ) 800b378: 5c8a ldrb r2, [r1, r2] 800b37a: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 800b37e: 7b3a ldrb r2, [r7, #12] 800b380: 490f ldr r1, [pc, #60] @ (800b3c0 ) 800b382: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 800b384: fb93 f3f2 sdiv r3, r3, r2 800b388: b29a uxth r2, r3 800b38a: 687b ldr r3, [r7, #4] 800b38c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800b390: 7bfb ldrb r3, [r7, #15] 800b392: 7b7a ldrb r2, [r7, #13] 800b394: 4909 ldr r1, [pc, #36] @ (800b3bc ) 800b396: 5c8a ldrb r2, [r1, r2] 800b398: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 800b39c: 7b7a ldrb r2, [r7, #13] 800b39e: 4908 ldr r1, [pc, #32] @ (800b3c0 ) 800b3a0: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 800b3a2: fb93 f3f2 sdiv r3, r3, r2 800b3a6: b29a uxth r2, r3 800b3a8: 687b ldr r3, [r7, #4] 800b3aa: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 800b3ae: bf00 nop 800b3b0: 3714 adds r7, #20 800b3b2: 46bd mov sp, r7 800b3b4: f85d 7b04 ldr.w r7, [sp], #4 800b3b8: 4770 bx lr 800b3ba: bf00 nop 800b3bc: 080100e0 .word 0x080100e0 800b3c0: 080100e8 .word 0x080100e8 0800b3c4 <__NVIC_SetPriority>: { 800b3c4: b480 push {r7} 800b3c6: b083 sub sp, #12 800b3c8: af00 add r7, sp, #0 800b3ca: 4603 mov r3, r0 800b3cc: 6039 str r1, [r7, #0] 800b3ce: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 800b3d0: f9b7 3006 ldrsh.w r3, [r7, #6] 800b3d4: 2b00 cmp r3, #0 800b3d6: db0a blt.n 800b3ee <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800b3d8: 683b ldr r3, [r7, #0] 800b3da: b2da uxtb r2, r3 800b3dc: 490c ldr r1, [pc, #48] @ (800b410 <__NVIC_SetPriority+0x4c>) 800b3de: f9b7 3006 ldrsh.w r3, [r7, #6] 800b3e2: 0112 lsls r2, r2, #4 800b3e4: b2d2 uxtb r2, r2 800b3e6: 440b add r3, r1 800b3e8: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 800b3ec: e00a b.n 800b404 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800b3ee: 683b ldr r3, [r7, #0] 800b3f0: b2da uxtb r2, r3 800b3f2: 4908 ldr r1, [pc, #32] @ (800b414 <__NVIC_SetPriority+0x50>) 800b3f4: 88fb ldrh r3, [r7, #6] 800b3f6: f003 030f and.w r3, r3, #15 800b3fa: 3b04 subs r3, #4 800b3fc: 0112 lsls r2, r2, #4 800b3fe: b2d2 uxtb r2, r2 800b400: 440b add r3, r1 800b402: 761a strb r2, [r3, #24] } 800b404: bf00 nop 800b406: 370c adds r7, #12 800b408: 46bd mov sp, r7 800b40a: f85d 7b04 ldr.w r7, [sp], #4 800b40e: 4770 bx lr 800b410: e000e100 .word 0xe000e100 800b414: e000ed00 .word 0xe000ed00 0800b418 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 800b418: b580 push {r7, lr} 800b41a: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 800b41c: 4b05 ldr r3, [pc, #20] @ (800b434 ) 800b41e: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 800b420: f002 fa74 bl 800d90c 800b424: 4603 mov r3, r0 800b426: 2b01 cmp r3, #1 800b428: d001 beq.n 800b42e /* Call tick handler */ xPortSysTickHandler(); 800b42a: f003 fb9d bl 800eb68 } } 800b42e: bf00 nop 800b430: bd80 pop {r7, pc} 800b432: bf00 nop 800b434: e000e010 .word 0xe000e010 0800b438 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 800b438: b580 push {r7, lr} 800b43a: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 800b43c: 2100 movs r1, #0 800b43e: f06f 0004 mvn.w r0, #4 800b442: f7ff ffbf bl 800b3c4 <__NVIC_SetPriority> #endif } 800b446: bf00 nop 800b448: bd80 pop {r7, pc} ... 0800b44c : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 800b44c: b480 push {r7} 800b44e: b083 sub sp, #12 800b450: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800b452: f3ef 8305 mrs r3, IPSR 800b456: 603b str r3, [r7, #0] return(result); 800b458: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 800b45a: 2b00 cmp r3, #0 800b45c: d003 beq.n 800b466 stat = osErrorISR; 800b45e: f06f 0305 mvn.w r3, #5 800b462: 607b str r3, [r7, #4] 800b464: e00c b.n 800b480 } else { if (KernelState == osKernelInactive) { 800b466: 4b0a ldr r3, [pc, #40] @ (800b490 ) 800b468: 681b ldr r3, [r3, #0] 800b46a: 2b00 cmp r3, #0 800b46c: d105 bne.n 800b47a EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 800b46e: 4b08 ldr r3, [pc, #32] @ (800b490 ) 800b470: 2201 movs r2, #1 800b472: 601a str r2, [r3, #0] stat = osOK; 800b474: 2300 movs r3, #0 800b476: 607b str r3, [r7, #4] 800b478: e002 b.n 800b480 } else { stat = osError; 800b47a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b47e: 607b str r3, [r7, #4] } } return (stat); 800b480: 687b ldr r3, [r7, #4] } 800b482: 4618 mov r0, r3 800b484: 370c adds r7, #12 800b486: 46bd mov sp, r7 800b488: f85d 7b04 ldr.w r7, [sp], #4 800b48c: 4770 bx lr 800b48e: bf00 nop 800b490: 24000794 .word 0x24000794 0800b494 : } return (state); } osStatus_t osKernelStart (void) { 800b494: b580 push {r7, lr} 800b496: b082 sub sp, #8 800b498: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800b49a: f3ef 8305 mrs r3, IPSR 800b49e: 603b str r3, [r7, #0] return(result); 800b4a0: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 800b4a2: 2b00 cmp r3, #0 800b4a4: d003 beq.n 800b4ae stat = osErrorISR; 800b4a6: f06f 0305 mvn.w r3, #5 800b4aa: 607b str r3, [r7, #4] 800b4ac: e010 b.n 800b4d0 } else { if (KernelState == osKernelReady) { 800b4ae: 4b0b ldr r3, [pc, #44] @ (800b4dc ) 800b4b0: 681b ldr r3, [r3, #0] 800b4b2: 2b01 cmp r3, #1 800b4b4: d109 bne.n 800b4ca /* Ensure SVC priority is at the reset value */ SVC_Setup(); 800b4b6: f7ff ffbf bl 800b438 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 800b4ba: 4b08 ldr r3, [pc, #32] @ (800b4dc ) 800b4bc: 2202 movs r2, #2 800b4be: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 800b4c0: f001 fd7a bl 800cfb8 stat = osOK; 800b4c4: 2300 movs r3, #0 800b4c6: 607b str r3, [r7, #4] 800b4c8: e002 b.n 800b4d0 } else { stat = osError; 800b4ca: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b4ce: 607b str r3, [r7, #4] } } return (stat); 800b4d0: 687b ldr r3, [r7, #4] } 800b4d2: 4618 mov r0, r3 800b4d4: 3708 adds r7, #8 800b4d6: 46bd mov sp, r7 800b4d8: bd80 pop {r7, pc} 800b4da: bf00 nop 800b4dc: 24000794 .word 0x24000794 0800b4e0 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 800b4e0: b580 push {r7, lr} 800b4e2: b08e sub sp, #56 @ 0x38 800b4e4: af04 add r7, sp, #16 800b4e6: 60f8 str r0, [r7, #12] 800b4e8: 60b9 str r1, [r7, #8] 800b4ea: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 800b4ec: 2300 movs r3, #0 800b4ee: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800b4f0: f3ef 8305 mrs r3, IPSR 800b4f4: 617b str r3, [r7, #20] return(result); 800b4f6: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 800b4f8: 2b00 cmp r3, #0 800b4fa: d17f bne.n 800b5fc 800b4fc: 68fb ldr r3, [r7, #12] 800b4fe: 2b00 cmp r3, #0 800b500: d07c beq.n 800b5fc stack = configMINIMAL_STACK_SIZE; 800b502: f44f 7300 mov.w r3, #512 @ 0x200 800b506: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 800b508: 2318 movs r3, #24 800b50a: 61fb str r3, [r7, #28] name = NULL; 800b50c: 2300 movs r3, #0 800b50e: 627b str r3, [r7, #36] @ 0x24 mem = -1; 800b510: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b514: 61bb str r3, [r7, #24] if (attr != NULL) { 800b516: 687b ldr r3, [r7, #4] 800b518: 2b00 cmp r3, #0 800b51a: d045 beq.n 800b5a8 if (attr->name != NULL) { 800b51c: 687b ldr r3, [r7, #4] 800b51e: 681b ldr r3, [r3, #0] 800b520: 2b00 cmp r3, #0 800b522: d002 beq.n 800b52a name = attr->name; 800b524: 687b ldr r3, [r7, #4] 800b526: 681b ldr r3, [r3, #0] 800b528: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 800b52a: 687b ldr r3, [r7, #4] 800b52c: 699b ldr r3, [r3, #24] 800b52e: 2b00 cmp r3, #0 800b530: d002 beq.n 800b538 prio = (UBaseType_t)attr->priority; 800b532: 687b ldr r3, [r7, #4] 800b534: 699b ldr r3, [r3, #24] 800b536: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 800b538: 69fb ldr r3, [r7, #28] 800b53a: 2b00 cmp r3, #0 800b53c: d008 beq.n 800b550 800b53e: 69fb ldr r3, [r7, #28] 800b540: 2b38 cmp r3, #56 @ 0x38 800b542: d805 bhi.n 800b550 800b544: 687b ldr r3, [r7, #4] 800b546: 685b ldr r3, [r3, #4] 800b548: f003 0301 and.w r3, r3, #1 800b54c: 2b00 cmp r3, #0 800b54e: d001 beq.n 800b554 return (NULL); 800b550: 2300 movs r3, #0 800b552: e054 b.n 800b5fe } if (attr->stack_size > 0U) { 800b554: 687b ldr r3, [r7, #4] 800b556: 695b ldr r3, [r3, #20] 800b558: 2b00 cmp r3, #0 800b55a: d003 beq.n 800b564 /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 800b55c: 687b ldr r3, [r7, #4] 800b55e: 695b ldr r3, [r3, #20] 800b560: 089b lsrs r3, r3, #2 800b562: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 800b564: 687b ldr r3, [r7, #4] 800b566: 689b ldr r3, [r3, #8] 800b568: 2b00 cmp r3, #0 800b56a: d00e beq.n 800b58a 800b56c: 687b ldr r3, [r7, #4] 800b56e: 68db ldr r3, [r3, #12] 800b570: 2ba7 cmp r3, #167 @ 0xa7 800b572: d90a bls.n 800b58a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 800b574: 687b ldr r3, [r7, #4] 800b576: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 800b578: 2b00 cmp r3, #0 800b57a: d006 beq.n 800b58a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 800b57c: 687b ldr r3, [r7, #4] 800b57e: 695b ldr r3, [r3, #20] 800b580: 2b00 cmp r3, #0 800b582: d002 beq.n 800b58a mem = 1; 800b584: 2301 movs r3, #1 800b586: 61bb str r3, [r7, #24] 800b588: e010 b.n 800b5ac } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 800b58a: 687b ldr r3, [r7, #4] 800b58c: 689b ldr r3, [r3, #8] 800b58e: 2b00 cmp r3, #0 800b590: d10c bne.n 800b5ac 800b592: 687b ldr r3, [r7, #4] 800b594: 68db ldr r3, [r3, #12] 800b596: 2b00 cmp r3, #0 800b598: d108 bne.n 800b5ac 800b59a: 687b ldr r3, [r7, #4] 800b59c: 691b ldr r3, [r3, #16] 800b59e: 2b00 cmp r3, #0 800b5a0: d104 bne.n 800b5ac mem = 0; 800b5a2: 2300 movs r3, #0 800b5a4: 61bb str r3, [r7, #24] 800b5a6: e001 b.n 800b5ac } } } else { mem = 0; 800b5a8: 2300 movs r3, #0 800b5aa: 61bb str r3, [r7, #24] } if (mem == 1) { 800b5ac: 69bb ldr r3, [r7, #24] 800b5ae: 2b01 cmp r3, #1 800b5b0: d110 bne.n 800b5d4 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 800b5b2: 687b ldr r3, [r7, #4] 800b5b4: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 800b5b6: 687a ldr r2, [r7, #4] 800b5b8: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 800b5ba: 9202 str r2, [sp, #8] 800b5bc: 9301 str r3, [sp, #4] 800b5be: 69fb ldr r3, [r7, #28] 800b5c0: 9300 str r3, [sp, #0] 800b5c2: 68bb ldr r3, [r7, #8] 800b5c4: 6a3a ldr r2, [r7, #32] 800b5c6: 6a79 ldr r1, [r7, #36] @ 0x24 800b5c8: 68f8 ldr r0, [r7, #12] 800b5ca: f001 fb02 bl 800cbd2 800b5ce: 4603 mov r3, r0 800b5d0: 613b str r3, [r7, #16] 800b5d2: e013 b.n 800b5fc #endif } else { if (mem == 0) { 800b5d4: 69bb ldr r3, [r7, #24] 800b5d6: 2b00 cmp r3, #0 800b5d8: d110 bne.n 800b5fc #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 800b5da: 6a3b ldr r3, [r7, #32] 800b5dc: b29a uxth r2, r3 800b5de: f107 0310 add.w r3, r7, #16 800b5e2: 9301 str r3, [sp, #4] 800b5e4: 69fb ldr r3, [r7, #28] 800b5e6: 9300 str r3, [sp, #0] 800b5e8: 68bb ldr r3, [r7, #8] 800b5ea: 6a79 ldr r1, [r7, #36] @ 0x24 800b5ec: 68f8 ldr r0, [r7, #12] 800b5ee: f001 fb50 bl 800cc92 800b5f2: 4603 mov r3, r0 800b5f4: 2b01 cmp r3, #1 800b5f6: d001 beq.n 800b5fc hTask = NULL; 800b5f8: 2300 movs r3, #0 800b5fa: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 800b5fc: 693b ldr r3, [r7, #16] } 800b5fe: 4618 mov r0, r3 800b600: 3728 adds r7, #40 @ 0x28 800b602: 46bd mov sp, r7 800b604: bd80 pop {r7, pc} 0800b606 : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 800b606: b580 push {r7, lr} 800b608: b084 sub sp, #16 800b60a: af00 add r7, sp, #0 800b60c: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800b60e: f3ef 8305 mrs r3, IPSR 800b612: 60bb str r3, [r7, #8] return(result); 800b614: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 800b616: 2b00 cmp r3, #0 800b618: d003 beq.n 800b622 stat = osErrorISR; 800b61a: f06f 0305 mvn.w r3, #5 800b61e: 60fb str r3, [r7, #12] 800b620: e007 b.n 800b632 } else { stat = osOK; 800b622: 2300 movs r3, #0 800b624: 60fb str r3, [r7, #12] if (ticks != 0U) { 800b626: 687b ldr r3, [r7, #4] 800b628: 2b00 cmp r3, #0 800b62a: d002 beq.n 800b632 vTaskDelay(ticks); 800b62c: 6878 ldr r0, [r7, #4] 800b62e: f001 fc8d bl 800cf4c } } return (stat); 800b632: 68fb ldr r3, [r7, #12] } 800b634: 4618 mov r0, r3 800b636: 3710 adds r7, #16 800b638: 46bd mov sp, r7 800b63a: bd80 pop {r7, pc} 0800b63c : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 800b63c: b580 push {r7, lr} 800b63e: b088 sub sp, #32 800b640: af00 add r7, sp, #0 800b642: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 800b644: 2300 movs r3, #0 800b646: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800b648: f3ef 8305 mrs r3, IPSR 800b64c: 60bb str r3, [r7, #8] return(result); 800b64e: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 800b650: 2b00 cmp r3, #0 800b652: d174 bne.n 800b73e if (attr != NULL) { 800b654: 687b ldr r3, [r7, #4] 800b656: 2b00 cmp r3, #0 800b658: d003 beq.n 800b662 type = attr->attr_bits; 800b65a: 687b ldr r3, [r7, #4] 800b65c: 685b ldr r3, [r3, #4] 800b65e: 61bb str r3, [r7, #24] 800b660: e001 b.n 800b666 } else { type = 0U; 800b662: 2300 movs r3, #0 800b664: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 800b666: 69bb ldr r3, [r7, #24] 800b668: f003 0301 and.w r3, r3, #1 800b66c: 2b00 cmp r3, #0 800b66e: d002 beq.n 800b676 rmtx = 1U; 800b670: 2301 movs r3, #1 800b672: 617b str r3, [r7, #20] 800b674: e001 b.n 800b67a } else { rmtx = 0U; 800b676: 2300 movs r3, #0 800b678: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 800b67a: 69bb ldr r3, [r7, #24] 800b67c: f003 0308 and.w r3, r3, #8 800b680: 2b00 cmp r3, #0 800b682: d15c bne.n 800b73e mem = -1; 800b684: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800b688: 613b str r3, [r7, #16] if (attr != NULL) { 800b68a: 687b ldr r3, [r7, #4] 800b68c: 2b00 cmp r3, #0 800b68e: d015 beq.n 800b6bc if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 800b690: 687b ldr r3, [r7, #4] 800b692: 689b ldr r3, [r3, #8] 800b694: 2b00 cmp r3, #0 800b696: d006 beq.n 800b6a6 800b698: 687b ldr r3, [r7, #4] 800b69a: 68db ldr r3, [r3, #12] 800b69c: 2b4f cmp r3, #79 @ 0x4f 800b69e: d902 bls.n 800b6a6 mem = 1; 800b6a0: 2301 movs r3, #1 800b6a2: 613b str r3, [r7, #16] 800b6a4: e00c b.n 800b6c0 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 800b6a6: 687b ldr r3, [r7, #4] 800b6a8: 689b ldr r3, [r3, #8] 800b6aa: 2b00 cmp r3, #0 800b6ac: d108 bne.n 800b6c0 800b6ae: 687b ldr r3, [r7, #4] 800b6b0: 68db ldr r3, [r3, #12] 800b6b2: 2b00 cmp r3, #0 800b6b4: d104 bne.n 800b6c0 mem = 0; 800b6b6: 2300 movs r3, #0 800b6b8: 613b str r3, [r7, #16] 800b6ba: e001 b.n 800b6c0 } } } else { mem = 0; 800b6bc: 2300 movs r3, #0 800b6be: 613b str r3, [r7, #16] } if (mem == 1) { 800b6c0: 693b ldr r3, [r7, #16] 800b6c2: 2b01 cmp r3, #1 800b6c4: d112 bne.n 800b6ec #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 800b6c6: 697b ldr r3, [r7, #20] 800b6c8: 2b00 cmp r3, #0 800b6ca: d007 beq.n 800b6dc #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 800b6cc: 687b ldr r3, [r7, #4] 800b6ce: 689b ldr r3, [r3, #8] 800b6d0: 4619 mov r1, r3 800b6d2: 2004 movs r0, #4 800b6d4: f000 fb1f bl 800bd16 800b6d8: 61f8 str r0, [r7, #28] 800b6da: e016 b.n 800b70a #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 800b6dc: 687b ldr r3, [r7, #4] 800b6de: 689b ldr r3, [r3, #8] 800b6e0: 4619 mov r1, r3 800b6e2: 2001 movs r0, #1 800b6e4: f000 fb17 bl 800bd16 800b6e8: 61f8 str r0, [r7, #28] 800b6ea: e00e b.n 800b70a } #endif } else { if (mem == 0) { 800b6ec: 693b ldr r3, [r7, #16] 800b6ee: 2b00 cmp r3, #0 800b6f0: d10b bne.n 800b70a #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 800b6f2: 697b ldr r3, [r7, #20] 800b6f4: 2b00 cmp r3, #0 800b6f6: d004 beq.n 800b702 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 800b6f8: 2004 movs r0, #4 800b6fa: f000 faf4 bl 800bce6 800b6fe: 61f8 str r0, [r7, #28] 800b700: e003 b.n 800b70a #endif } else { hMutex = xSemaphoreCreateMutex (); 800b702: 2001 movs r0, #1 800b704: f000 faef bl 800bce6 800b708: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 800b70a: 69fb ldr r3, [r7, #28] 800b70c: 2b00 cmp r3, #0 800b70e: d00c beq.n 800b72a if (attr != NULL) { 800b710: 687b ldr r3, [r7, #4] 800b712: 2b00 cmp r3, #0 800b714: d003 beq.n 800b71e name = attr->name; 800b716: 687b ldr r3, [r7, #4] 800b718: 681b ldr r3, [r3, #0] 800b71a: 60fb str r3, [r7, #12] 800b71c: e001 b.n 800b722 } else { name = NULL; 800b71e: 2300 movs r3, #0 800b720: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 800b722: 68f9 ldr r1, [r7, #12] 800b724: 69f8 ldr r0, [r7, #28] 800b726: f001 f837 bl 800c798 } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 800b72a: 69fb ldr r3, [r7, #28] 800b72c: 2b00 cmp r3, #0 800b72e: d006 beq.n 800b73e 800b730: 697b ldr r3, [r7, #20] 800b732: 2b00 cmp r3, #0 800b734: d003 beq.n 800b73e hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 800b736: 69fb ldr r3, [r7, #28] 800b738: f043 0301 orr.w r3, r3, #1 800b73c: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 800b73e: 69fb ldr r3, [r7, #28] } 800b740: 4618 mov r0, r3 800b742: 3720 adds r7, #32 800b744: 46bd mov sp, r7 800b746: bd80 pop {r7, pc} 0800b748 : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 800b748: b580 push {r7, lr} 800b74a: b086 sub sp, #24 800b74c: af00 add r7, sp, #0 800b74e: 6078 str r0, [r7, #4] 800b750: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 800b752: 687b ldr r3, [r7, #4] 800b754: f023 0301 bic.w r3, r3, #1 800b758: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 800b75a: 687b ldr r3, [r7, #4] 800b75c: f003 0301 and.w r3, r3, #1 800b760: 60fb str r3, [r7, #12] stat = osOK; 800b762: 2300 movs r3, #0 800b764: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800b766: f3ef 8305 mrs r3, IPSR 800b76a: 60bb str r3, [r7, #8] return(result); 800b76c: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 800b76e: 2b00 cmp r3, #0 800b770: d003 beq.n 800b77a stat = osErrorISR; 800b772: f06f 0305 mvn.w r3, #5 800b776: 617b str r3, [r7, #20] 800b778: e02c b.n 800b7d4 } else if (hMutex == NULL) { 800b77a: 693b ldr r3, [r7, #16] 800b77c: 2b00 cmp r3, #0 800b77e: d103 bne.n 800b788 stat = osErrorParameter; 800b780: f06f 0303 mvn.w r3, #3 800b784: 617b str r3, [r7, #20] 800b786: e025 b.n 800b7d4 } else { if (rmtx != 0U) { 800b788: 68fb ldr r3, [r7, #12] 800b78a: 2b00 cmp r3, #0 800b78c: d011 beq.n 800b7b2 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 800b78e: 6839 ldr r1, [r7, #0] 800b790: 6938 ldr r0, [r7, #16] 800b792: f000 fb10 bl 800bdb6 800b796: 4603 mov r3, r0 800b798: 2b01 cmp r3, #1 800b79a: d01b beq.n 800b7d4 if (timeout != 0U) { 800b79c: 683b ldr r3, [r7, #0] 800b79e: 2b00 cmp r3, #0 800b7a0: d003 beq.n 800b7aa stat = osErrorTimeout; 800b7a2: f06f 0301 mvn.w r3, #1 800b7a6: 617b str r3, [r7, #20] 800b7a8: e014 b.n 800b7d4 } else { stat = osErrorResource; 800b7aa: f06f 0302 mvn.w r3, #2 800b7ae: 617b str r3, [r7, #20] 800b7b0: e010 b.n 800b7d4 } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 800b7b2: 6839 ldr r1, [r7, #0] 800b7b4: 6938 ldr r0, [r7, #16] 800b7b6: f000 fdb7 bl 800c328 800b7ba: 4603 mov r3, r0 800b7bc: 2b01 cmp r3, #1 800b7be: d009 beq.n 800b7d4 if (timeout != 0U) { 800b7c0: 683b ldr r3, [r7, #0] 800b7c2: 2b00 cmp r3, #0 800b7c4: d003 beq.n 800b7ce stat = osErrorTimeout; 800b7c6: f06f 0301 mvn.w r3, #1 800b7ca: 617b str r3, [r7, #20] 800b7cc: e002 b.n 800b7d4 } else { stat = osErrorResource; 800b7ce: f06f 0302 mvn.w r3, #2 800b7d2: 617b str r3, [r7, #20] } } } } return (stat); 800b7d4: 697b ldr r3, [r7, #20] } 800b7d6: 4618 mov r0, r3 800b7d8: 3718 adds r7, #24 800b7da: 46bd mov sp, r7 800b7dc: bd80 pop {r7, pc} 0800b7de : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 800b7de: b580 push {r7, lr} 800b7e0: b086 sub sp, #24 800b7e2: af00 add r7, sp, #0 800b7e4: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 800b7e6: 687b ldr r3, [r7, #4] 800b7e8: f023 0301 bic.w r3, r3, #1 800b7ec: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 800b7ee: 687b ldr r3, [r7, #4] 800b7f0: f003 0301 and.w r3, r3, #1 800b7f4: 60fb str r3, [r7, #12] stat = osOK; 800b7f6: 2300 movs r3, #0 800b7f8: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 800b7fa: f3ef 8305 mrs r3, IPSR 800b7fe: 60bb str r3, [r7, #8] return(result); 800b800: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 800b802: 2b00 cmp r3, #0 800b804: d003 beq.n 800b80e stat = osErrorISR; 800b806: f06f 0305 mvn.w r3, #5 800b80a: 617b str r3, [r7, #20] 800b80c: e01f b.n 800b84e } else if (hMutex == NULL) { 800b80e: 693b ldr r3, [r7, #16] 800b810: 2b00 cmp r3, #0 800b812: d103 bne.n 800b81c stat = osErrorParameter; 800b814: f06f 0303 mvn.w r3, #3 800b818: 617b str r3, [r7, #20] 800b81a: e018 b.n 800b84e } else { if (rmtx != 0U) { 800b81c: 68fb ldr r3, [r7, #12] 800b81e: 2b00 cmp r3, #0 800b820: d009 beq.n 800b836 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 800b822: 6938 ldr r0, [r7, #16] 800b824: f000 fa92 bl 800bd4c 800b828: 4603 mov r3, r0 800b82a: 2b01 cmp r3, #1 800b82c: d00f beq.n 800b84e stat = osErrorResource; 800b82e: f06f 0302 mvn.w r3, #2 800b832: 617b str r3, [r7, #20] 800b834: e00b b.n 800b84e } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 800b836: 2300 movs r3, #0 800b838: 2200 movs r2, #0 800b83a: 2100 movs r1, #0 800b83c: 6938 ldr r0, [r7, #16] 800b83e: f000 faf1 bl 800be24 800b842: 4603 mov r3, r0 800b844: 2b01 cmp r3, #1 800b846: d002 beq.n 800b84e stat = osErrorResource; 800b848: f06f 0302 mvn.w r3, #2 800b84c: 617b str r3, [r7, #20] } } } return (stat); 800b84e: 697b ldr r3, [r7, #20] } 800b850: 4618 mov r0, r3 800b852: 3718 adds r7, #24 800b854: 46bd mov sp, r7 800b856: bd80 pop {r7, pc} 0800b858 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 800b858: b480 push {r7} 800b85a: b085 sub sp, #20 800b85c: af00 add r7, sp, #0 800b85e: 60f8 str r0, [r7, #12] 800b860: 60b9 str r1, [r7, #8] 800b862: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 800b864: 68fb ldr r3, [r7, #12] 800b866: 4a07 ldr r2, [pc, #28] @ (800b884 ) 800b868: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 800b86a: 68bb ldr r3, [r7, #8] 800b86c: 4a06 ldr r2, [pc, #24] @ (800b888 ) 800b86e: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 800b870: 687b ldr r3, [r7, #4] 800b872: f44f 7200 mov.w r2, #512 @ 0x200 800b876: 601a str r2, [r3, #0] } 800b878: bf00 nop 800b87a: 3714 adds r7, #20 800b87c: 46bd mov sp, r7 800b87e: f85d 7b04 ldr.w r7, [sp], #4 800b882: 4770 bx lr 800b884: 24000798 .word 0x24000798 800b888: 24000840 .word 0x24000840 0800b88c : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 800b88c: b480 push {r7} 800b88e: b085 sub sp, #20 800b890: af00 add r7, sp, #0 800b892: 60f8 str r0, [r7, #12] 800b894: 60b9 str r1, [r7, #8] 800b896: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 800b898: 68fb ldr r3, [r7, #12] 800b89a: 4a07 ldr r2, [pc, #28] @ (800b8b8 ) 800b89c: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 800b89e: 68bb ldr r3, [r7, #8] 800b8a0: 4a06 ldr r2, [pc, #24] @ (800b8bc ) 800b8a2: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 800b8a4: 687b ldr r3, [r7, #4] 800b8a6: f44f 6280 mov.w r2, #1024 @ 0x400 800b8aa: 601a str r2, [r3, #0] } 800b8ac: bf00 nop 800b8ae: 3714 adds r7, #20 800b8b0: 46bd mov sp, r7 800b8b2: f85d 7b04 ldr.w r7, [sp], #4 800b8b6: 4770 bx lr 800b8b8: 24001040 .word 0x24001040 800b8bc: 240010e8 .word 0x240010e8 0800b8c0 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 800b8c0: b480 push {r7} 800b8c2: b083 sub sp, #12 800b8c4: af00 add r7, sp, #0 800b8c6: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 800b8c8: 687b ldr r3, [r7, #4] 800b8ca: f103 0208 add.w r2, r3, #8 800b8ce: 687b ldr r3, [r7, #4] 800b8d0: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 800b8d2: 687b ldr r3, [r7, #4] 800b8d4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800b8d8: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 800b8da: 687b ldr r3, [r7, #4] 800b8dc: f103 0208 add.w r2, r3, #8 800b8e0: 687b ldr r3, [r7, #4] 800b8e2: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 800b8e4: 687b ldr r3, [r7, #4] 800b8e6: f103 0208 add.w r2, r3, #8 800b8ea: 687b ldr r3, [r7, #4] 800b8ec: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 800b8ee: 687b ldr r3, [r7, #4] 800b8f0: 2200 movs r2, #0 800b8f2: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 800b8f4: bf00 nop 800b8f6: 370c adds r7, #12 800b8f8: 46bd mov sp, r7 800b8fa: f85d 7b04 ldr.w r7, [sp], #4 800b8fe: 4770 bx lr 0800b900 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 800b900: b480 push {r7} 800b902: b083 sub sp, #12 800b904: af00 add r7, sp, #0 800b906: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 800b908: 687b ldr r3, [r7, #4] 800b90a: 2200 movs r2, #0 800b90c: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 800b90e: bf00 nop 800b910: 370c adds r7, #12 800b912: 46bd mov sp, r7 800b914: f85d 7b04 ldr.w r7, [sp], #4 800b918: 4770 bx lr 0800b91a : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 800b91a: b480 push {r7} 800b91c: b085 sub sp, #20 800b91e: af00 add r7, sp, #0 800b920: 6078 str r0, [r7, #4] 800b922: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 800b924: 687b ldr r3, [r7, #4] 800b926: 685b ldr r3, [r3, #4] 800b928: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 800b92a: 683b ldr r3, [r7, #0] 800b92c: 68fa ldr r2, [r7, #12] 800b92e: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 800b930: 68fb ldr r3, [r7, #12] 800b932: 689a ldr r2, [r3, #8] 800b934: 683b ldr r3, [r7, #0] 800b936: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 800b938: 68fb ldr r3, [r7, #12] 800b93a: 689b ldr r3, [r3, #8] 800b93c: 683a ldr r2, [r7, #0] 800b93e: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 800b940: 68fb ldr r3, [r7, #12] 800b942: 683a ldr r2, [r7, #0] 800b944: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 800b946: 683b ldr r3, [r7, #0] 800b948: 687a ldr r2, [r7, #4] 800b94a: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 800b94c: 687b ldr r3, [r7, #4] 800b94e: 681b ldr r3, [r3, #0] 800b950: 1c5a adds r2, r3, #1 800b952: 687b ldr r3, [r7, #4] 800b954: 601a str r2, [r3, #0] } 800b956: bf00 nop 800b958: 3714 adds r7, #20 800b95a: 46bd mov sp, r7 800b95c: f85d 7b04 ldr.w r7, [sp], #4 800b960: 4770 bx lr 0800b962 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 800b962: b480 push {r7} 800b964: b085 sub sp, #20 800b966: af00 add r7, sp, #0 800b968: 6078 str r0, [r7, #4] 800b96a: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 800b96c: 683b ldr r3, [r7, #0] 800b96e: 681b ldr r3, [r3, #0] 800b970: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 800b972: 68bb ldr r3, [r7, #8] 800b974: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800b978: d103 bne.n 800b982 { pxIterator = pxList->xListEnd.pxPrevious; 800b97a: 687b ldr r3, [r7, #4] 800b97c: 691b ldr r3, [r3, #16] 800b97e: 60fb str r3, [r7, #12] 800b980: e00c b.n 800b99c 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 800b982: 687b ldr r3, [r7, #4] 800b984: 3308 adds r3, #8 800b986: 60fb str r3, [r7, #12] 800b988: e002 b.n 800b990 800b98a: 68fb ldr r3, [r7, #12] 800b98c: 685b ldr r3, [r3, #4] 800b98e: 60fb str r3, [r7, #12] 800b990: 68fb ldr r3, [r7, #12] 800b992: 685b ldr r3, [r3, #4] 800b994: 681b ldr r3, [r3, #0] 800b996: 68ba ldr r2, [r7, #8] 800b998: 429a cmp r2, r3 800b99a: d2f6 bcs.n 800b98a /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 800b99c: 68fb ldr r3, [r7, #12] 800b99e: 685a ldr r2, [r3, #4] 800b9a0: 683b ldr r3, [r7, #0] 800b9a2: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 800b9a4: 683b ldr r3, [r7, #0] 800b9a6: 685b ldr r3, [r3, #4] 800b9a8: 683a ldr r2, [r7, #0] 800b9aa: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 800b9ac: 683b ldr r3, [r7, #0] 800b9ae: 68fa ldr r2, [r7, #12] 800b9b0: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 800b9b2: 68fb ldr r3, [r7, #12] 800b9b4: 683a ldr r2, [r7, #0] 800b9b6: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 800b9b8: 683b ldr r3, [r7, #0] 800b9ba: 687a ldr r2, [r7, #4] 800b9bc: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 800b9be: 687b ldr r3, [r7, #4] 800b9c0: 681b ldr r3, [r3, #0] 800b9c2: 1c5a adds r2, r3, #1 800b9c4: 687b ldr r3, [r7, #4] 800b9c6: 601a str r2, [r3, #0] } 800b9c8: bf00 nop 800b9ca: 3714 adds r7, #20 800b9cc: 46bd mov sp, r7 800b9ce: f85d 7b04 ldr.w r7, [sp], #4 800b9d2: 4770 bx lr 0800b9d4 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 800b9d4: b480 push {r7} 800b9d6: b085 sub sp, #20 800b9d8: af00 add r7, sp, #0 800b9da: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 800b9dc: 687b ldr r3, [r7, #4] 800b9de: 691b ldr r3, [r3, #16] 800b9e0: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 800b9e2: 687b ldr r3, [r7, #4] 800b9e4: 685b ldr r3, [r3, #4] 800b9e6: 687a ldr r2, [r7, #4] 800b9e8: 6892 ldr r2, [r2, #8] 800b9ea: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 800b9ec: 687b ldr r3, [r7, #4] 800b9ee: 689b ldr r3, [r3, #8] 800b9f0: 687a ldr r2, [r7, #4] 800b9f2: 6852 ldr r2, [r2, #4] 800b9f4: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 800b9f6: 68fb ldr r3, [r7, #12] 800b9f8: 685b ldr r3, [r3, #4] 800b9fa: 687a ldr r2, [r7, #4] 800b9fc: 429a cmp r2, r3 800b9fe: d103 bne.n 800ba08 { pxList->pxIndex = pxItemToRemove->pxPrevious; 800ba00: 687b ldr r3, [r7, #4] 800ba02: 689a ldr r2, [r3, #8] 800ba04: 68fb ldr r3, [r7, #12] 800ba06: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 800ba08: 687b ldr r3, [r7, #4] 800ba0a: 2200 movs r2, #0 800ba0c: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 800ba0e: 68fb ldr r3, [r7, #12] 800ba10: 681b ldr r3, [r3, #0] 800ba12: 1e5a subs r2, r3, #1 800ba14: 68fb ldr r3, [r7, #12] 800ba16: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 800ba18: 68fb ldr r3, [r7, #12] 800ba1a: 681b ldr r3, [r3, #0] } 800ba1c: 4618 mov r0, r3 800ba1e: 3714 adds r7, #20 800ba20: 46bd mov sp, r7 800ba22: f85d 7b04 ldr.w r7, [sp], #4 800ba26: 4770 bx lr 0800ba28 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 800ba28: b580 push {r7, lr} 800ba2a: b084 sub sp, #16 800ba2c: af00 add r7, sp, #0 800ba2e: 6078 str r0, [r7, #4] 800ba30: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 800ba32: 687b ldr r3, [r7, #4] 800ba34: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 800ba36: 68fb ldr r3, [r7, #12] 800ba38: 2b00 cmp r3, #0 800ba3a: d10b bne.n 800ba54 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 800ba3c: f04f 0350 mov.w r3, #80 @ 0x50 800ba40: f383 8811 msr BASEPRI, r3 800ba44: f3bf 8f6f isb sy 800ba48: f3bf 8f4f dsb sy 800ba4c: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 800ba4e: bf00 nop 800ba50: bf00 nop 800ba52: e7fd b.n 800ba50 taskENTER_CRITICAL(); 800ba54: f002 fff8 bl 800ea48 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800ba58: 68fb ldr r3, [r7, #12] 800ba5a: 681a ldr r2, [r3, #0] 800ba5c: 68fb ldr r3, [r7, #12] 800ba5e: 6bdb ldr r3, [r3, #60] @ 0x3c 800ba60: 68f9 ldr r1, [r7, #12] 800ba62: 6c09 ldr r1, [r1, #64] @ 0x40 800ba64: fb01 f303 mul.w r3, r1, r3 800ba68: 441a add r2, r3 800ba6a: 68fb ldr r3, [r7, #12] 800ba6c: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 800ba6e: 68fb ldr r3, [r7, #12] 800ba70: 2200 movs r2, #0 800ba72: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 800ba74: 68fb ldr r3, [r7, #12] 800ba76: 681a ldr r2, [r3, #0] 800ba78: 68fb ldr r3, [r7, #12] 800ba7a: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800ba7c: 68fb ldr r3, [r7, #12] 800ba7e: 681a ldr r2, [r3, #0] 800ba80: 68fb ldr r3, [r7, #12] 800ba82: 6bdb ldr r3, [r3, #60] @ 0x3c 800ba84: 3b01 subs r3, #1 800ba86: 68f9 ldr r1, [r7, #12] 800ba88: 6c09 ldr r1, [r1, #64] @ 0x40 800ba8a: fb01 f303 mul.w r3, r1, r3 800ba8e: 441a add r2, r3 800ba90: 68fb ldr r3, [r7, #12] 800ba92: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 800ba94: 68fb ldr r3, [r7, #12] 800ba96: 22ff movs r2, #255 @ 0xff 800ba98: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 800ba9c: 68fb ldr r3, [r7, #12] 800ba9e: 22ff movs r2, #255 @ 0xff 800baa0: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 800baa4: 683b ldr r3, [r7, #0] 800baa6: 2b00 cmp r3, #0 800baa8: d114 bne.n 800bad4 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800baaa: 68fb ldr r3, [r7, #12] 800baac: 691b ldr r3, [r3, #16] 800baae: 2b00 cmp r3, #0 800bab0: d01a beq.n 800bae8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800bab2: 68fb ldr r3, [r7, #12] 800bab4: 3310 adds r3, #16 800bab6: 4618 mov r0, r3 800bab8: f001 fd2a bl 800d510 800babc: 4603 mov r3, r0 800babe: 2b00 cmp r3, #0 800bac0: d012 beq.n 800bae8 { queueYIELD_IF_USING_PREEMPTION(); 800bac2: 4b0d ldr r3, [pc, #52] @ (800baf8 ) 800bac4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800bac8: 601a str r2, [r3, #0] 800baca: f3bf 8f4f dsb sy 800bace: f3bf 8f6f isb sy 800bad2: e009 b.n 800bae8 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 800bad4: 68fb ldr r3, [r7, #12] 800bad6: 3310 adds r3, #16 800bad8: 4618 mov r0, r3 800bada: f7ff fef1 bl 800b8c0 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 800bade: 68fb ldr r3, [r7, #12] 800bae0: 3324 adds r3, #36 @ 0x24 800bae2: 4618 mov r0, r3 800bae4: f7ff feec bl 800b8c0 } } taskEXIT_CRITICAL(); 800bae8: f002 ffe0 bl 800eaac /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 800baec: 2301 movs r3, #1 } 800baee: 4618 mov r0, r3 800baf0: 3710 adds r7, #16 800baf2: 46bd mov sp, r7 800baf4: bd80 pop {r7, pc} 800baf6: bf00 nop 800baf8: e000ed04 .word 0xe000ed04 0800bafc : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 800bafc: b580 push {r7, lr} 800bafe: b08e sub sp, #56 @ 0x38 800bb00: af02 add r7, sp, #8 800bb02: 60f8 str r0, [r7, #12] 800bb04: 60b9 str r1, [r7, #8] 800bb06: 607a str r2, [r7, #4] 800bb08: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 800bb0a: 68fb ldr r3, [r7, #12] 800bb0c: 2b00 cmp r3, #0 800bb0e: d10b bne.n 800bb28 __asm volatile 800bb10: f04f 0350 mov.w r3, #80 @ 0x50 800bb14: f383 8811 msr BASEPRI, r3 800bb18: f3bf 8f6f isb sy 800bb1c: f3bf 8f4f dsb sy 800bb20: 62bb str r3, [r7, #40] @ 0x28 } 800bb22: bf00 nop 800bb24: bf00 nop 800bb26: e7fd b.n 800bb24 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 800bb28: 683b ldr r3, [r7, #0] 800bb2a: 2b00 cmp r3, #0 800bb2c: d10b bne.n 800bb46 __asm volatile 800bb2e: f04f 0350 mov.w r3, #80 @ 0x50 800bb32: f383 8811 msr BASEPRI, r3 800bb36: f3bf 8f6f isb sy 800bb3a: f3bf 8f4f dsb sy 800bb3e: 627b str r3, [r7, #36] @ 0x24 } 800bb40: bf00 nop 800bb42: bf00 nop 800bb44: e7fd b.n 800bb42 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 800bb46: 687b ldr r3, [r7, #4] 800bb48: 2b00 cmp r3, #0 800bb4a: d002 beq.n 800bb52 800bb4c: 68bb ldr r3, [r7, #8] 800bb4e: 2b00 cmp r3, #0 800bb50: d001 beq.n 800bb56 800bb52: 2301 movs r3, #1 800bb54: e000 b.n 800bb58 800bb56: 2300 movs r3, #0 800bb58: 2b00 cmp r3, #0 800bb5a: d10b bne.n 800bb74 __asm volatile 800bb5c: f04f 0350 mov.w r3, #80 @ 0x50 800bb60: f383 8811 msr BASEPRI, r3 800bb64: f3bf 8f6f isb sy 800bb68: f3bf 8f4f dsb sy 800bb6c: 623b str r3, [r7, #32] } 800bb6e: bf00 nop 800bb70: bf00 nop 800bb72: e7fd b.n 800bb70 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 800bb74: 687b ldr r3, [r7, #4] 800bb76: 2b00 cmp r3, #0 800bb78: d102 bne.n 800bb80 800bb7a: 68bb ldr r3, [r7, #8] 800bb7c: 2b00 cmp r3, #0 800bb7e: d101 bne.n 800bb84 800bb80: 2301 movs r3, #1 800bb82: e000 b.n 800bb86 800bb84: 2300 movs r3, #0 800bb86: 2b00 cmp r3, #0 800bb88: d10b bne.n 800bba2 __asm volatile 800bb8a: f04f 0350 mov.w r3, #80 @ 0x50 800bb8e: f383 8811 msr BASEPRI, r3 800bb92: f3bf 8f6f isb sy 800bb96: f3bf 8f4f dsb sy 800bb9a: 61fb str r3, [r7, #28] } 800bb9c: bf00 nop 800bb9e: bf00 nop 800bba0: e7fd b.n 800bb9e #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 800bba2: 2350 movs r3, #80 @ 0x50 800bba4: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 800bba6: 697b ldr r3, [r7, #20] 800bba8: 2b50 cmp r3, #80 @ 0x50 800bbaa: d00b beq.n 800bbc4 __asm volatile 800bbac: f04f 0350 mov.w r3, #80 @ 0x50 800bbb0: f383 8811 msr BASEPRI, r3 800bbb4: f3bf 8f6f isb sy 800bbb8: f3bf 8f4f dsb sy 800bbbc: 61bb str r3, [r7, #24] } 800bbbe: bf00 nop 800bbc0: bf00 nop 800bbc2: e7fd b.n 800bbc0 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 800bbc4: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 800bbc6: 683b ldr r3, [r7, #0] 800bbc8: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 800bbca: 6afb ldr r3, [r7, #44] @ 0x2c 800bbcc: 2b00 cmp r3, #0 800bbce: d00d beq.n 800bbec #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 800bbd0: 6afb ldr r3, [r7, #44] @ 0x2c 800bbd2: 2201 movs r2, #1 800bbd4: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 800bbd8: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 800bbdc: 6afb ldr r3, [r7, #44] @ 0x2c 800bbde: 9300 str r3, [sp, #0] 800bbe0: 4613 mov r3, r2 800bbe2: 687a ldr r2, [r7, #4] 800bbe4: 68b9 ldr r1, [r7, #8] 800bbe6: 68f8 ldr r0, [r7, #12] 800bbe8: f000 f840 bl 800bc6c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 800bbec: 6afb ldr r3, [r7, #44] @ 0x2c } 800bbee: 4618 mov r0, r3 800bbf0: 3730 adds r7, #48 @ 0x30 800bbf2: 46bd mov sp, r7 800bbf4: bd80 pop {r7, pc} 0800bbf6 : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 800bbf6: b580 push {r7, lr} 800bbf8: b08a sub sp, #40 @ 0x28 800bbfa: af02 add r7, sp, #8 800bbfc: 60f8 str r0, [r7, #12] 800bbfe: 60b9 str r1, [r7, #8] 800bc00: 4613 mov r3, r2 800bc02: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 800bc04: 68fb ldr r3, [r7, #12] 800bc06: 2b00 cmp r3, #0 800bc08: d10b bne.n 800bc22 __asm volatile 800bc0a: f04f 0350 mov.w r3, #80 @ 0x50 800bc0e: f383 8811 msr BASEPRI, r3 800bc12: f3bf 8f6f isb sy 800bc16: f3bf 8f4f dsb sy 800bc1a: 613b str r3, [r7, #16] } 800bc1c: bf00 nop 800bc1e: bf00 nop 800bc20: e7fd b.n 800bc1e /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800bc22: 68fb ldr r3, [r7, #12] 800bc24: 68ba ldr r2, [r7, #8] 800bc26: fb02 f303 mul.w r3, r2, r3 800bc2a: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 800bc2c: 69fb ldr r3, [r7, #28] 800bc2e: 3350 adds r3, #80 @ 0x50 800bc30: 4618 mov r0, r3 800bc32: f003 f82b bl 800ec8c 800bc36: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 800bc38: 69bb ldr r3, [r7, #24] 800bc3a: 2b00 cmp r3, #0 800bc3c: d011 beq.n 800bc62 { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 800bc3e: 69bb ldr r3, [r7, #24] 800bc40: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 800bc42: 697b ldr r3, [r7, #20] 800bc44: 3350 adds r3, #80 @ 0x50 800bc46: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 800bc48: 69bb ldr r3, [r7, #24] 800bc4a: 2200 movs r2, #0 800bc4c: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 800bc50: 79fa ldrb r2, [r7, #7] 800bc52: 69bb ldr r3, [r7, #24] 800bc54: 9300 str r3, [sp, #0] 800bc56: 4613 mov r3, r2 800bc58: 697a ldr r2, [r7, #20] 800bc5a: 68b9 ldr r1, [r7, #8] 800bc5c: 68f8 ldr r0, [r7, #12] 800bc5e: f000 f805 bl 800bc6c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 800bc62: 69bb ldr r3, [r7, #24] } 800bc64: 4618 mov r0, r3 800bc66: 3720 adds r7, #32 800bc68: 46bd mov sp, r7 800bc6a: bd80 pop {r7, pc} 0800bc6c : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 800bc6c: b580 push {r7, lr} 800bc6e: b084 sub sp, #16 800bc70: af00 add r7, sp, #0 800bc72: 60f8 str r0, [r7, #12] 800bc74: 60b9 str r1, [r7, #8] 800bc76: 607a str r2, [r7, #4] 800bc78: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 800bc7a: 68bb ldr r3, [r7, #8] 800bc7c: 2b00 cmp r3, #0 800bc7e: d103 bne.n 800bc88 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 800bc80: 69bb ldr r3, [r7, #24] 800bc82: 69ba ldr r2, [r7, #24] 800bc84: 601a str r2, [r3, #0] 800bc86: e002 b.n 800bc8e } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 800bc88: 69bb ldr r3, [r7, #24] 800bc8a: 687a ldr r2, [r7, #4] 800bc8c: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 800bc8e: 69bb ldr r3, [r7, #24] 800bc90: 68fa ldr r2, [r7, #12] 800bc92: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 800bc94: 69bb ldr r3, [r7, #24] 800bc96: 68ba ldr r2, [r7, #8] 800bc98: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 800bc9a: 2101 movs r1, #1 800bc9c: 69b8 ldr r0, [r7, #24] 800bc9e: f7ff fec3 bl 800ba28 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 800bca2: 69bb ldr r3, [r7, #24] 800bca4: 78fa ldrb r2, [r7, #3] 800bca6: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 800bcaa: bf00 nop 800bcac: 3710 adds r7, #16 800bcae: 46bd mov sp, r7 800bcb0: bd80 pop {r7, pc} 0800bcb2 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 800bcb2: b580 push {r7, lr} 800bcb4: b082 sub sp, #8 800bcb6: af00 add r7, sp, #0 800bcb8: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 800bcba: 687b ldr r3, [r7, #4] 800bcbc: 2b00 cmp r3, #0 800bcbe: d00e beq.n 800bcde { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 800bcc0: 687b ldr r3, [r7, #4] 800bcc2: 2200 movs r2, #0 800bcc4: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 800bcc6: 687b ldr r3, [r7, #4] 800bcc8: 2200 movs r2, #0 800bcca: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 800bccc: 687b ldr r3, [r7, #4] 800bcce: 2200 movs r2, #0 800bcd0: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 800bcd2: 2300 movs r3, #0 800bcd4: 2200 movs r2, #0 800bcd6: 2100 movs r1, #0 800bcd8: 6878 ldr r0, [r7, #4] 800bcda: f000 f8a3 bl 800be24 } else { traceCREATE_MUTEX_FAILED(); } } 800bcde: bf00 nop 800bce0: 3708 adds r7, #8 800bce2: 46bd mov sp, r7 800bce4: bd80 pop {r7, pc} 0800bce6 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 800bce6: b580 push {r7, lr} 800bce8: b086 sub sp, #24 800bcea: af00 add r7, sp, #0 800bcec: 4603 mov r3, r0 800bcee: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 800bcf0: 2301 movs r3, #1 800bcf2: 617b str r3, [r7, #20] 800bcf4: 2300 movs r3, #0 800bcf6: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 800bcf8: 79fb ldrb r3, [r7, #7] 800bcfa: 461a mov r2, r3 800bcfc: 6939 ldr r1, [r7, #16] 800bcfe: 6978 ldr r0, [r7, #20] 800bd00: f7ff ff79 bl 800bbf6 800bd04: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 800bd06: 68f8 ldr r0, [r7, #12] 800bd08: f7ff ffd3 bl 800bcb2 return xNewQueue; 800bd0c: 68fb ldr r3, [r7, #12] } 800bd0e: 4618 mov r0, r3 800bd10: 3718 adds r7, #24 800bd12: 46bd mov sp, r7 800bd14: bd80 pop {r7, pc} 0800bd16 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 800bd16: b580 push {r7, lr} 800bd18: b088 sub sp, #32 800bd1a: af02 add r7, sp, #8 800bd1c: 4603 mov r3, r0 800bd1e: 6039 str r1, [r7, #0] 800bd20: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 800bd22: 2301 movs r3, #1 800bd24: 617b str r3, [r7, #20] 800bd26: 2300 movs r3, #0 800bd28: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 800bd2a: 79fb ldrb r3, [r7, #7] 800bd2c: 9300 str r3, [sp, #0] 800bd2e: 683b ldr r3, [r7, #0] 800bd30: 2200 movs r2, #0 800bd32: 6939 ldr r1, [r7, #16] 800bd34: 6978 ldr r0, [r7, #20] 800bd36: f7ff fee1 bl 800bafc 800bd3a: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 800bd3c: 68f8 ldr r0, [r7, #12] 800bd3e: f7ff ffb8 bl 800bcb2 return xNewQueue; 800bd42: 68fb ldr r3, [r7, #12] } 800bd44: 4618 mov r0, r3 800bd46: 3718 adds r7, #24 800bd48: 46bd mov sp, r7 800bd4a: bd80 pop {r7, pc} 0800bd4c : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 800bd4c: b590 push {r4, r7, lr} 800bd4e: b087 sub sp, #28 800bd50: af00 add r7, sp, #0 800bd52: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 800bd54: 687b ldr r3, [r7, #4] 800bd56: 613b str r3, [r7, #16] configASSERT( pxMutex ); 800bd58: 693b ldr r3, [r7, #16] 800bd5a: 2b00 cmp r3, #0 800bd5c: d10b bne.n 800bd76 __asm volatile 800bd5e: f04f 0350 mov.w r3, #80 @ 0x50 800bd62: f383 8811 msr BASEPRI, r3 800bd66: f3bf 8f6f isb sy 800bd6a: f3bf 8f4f dsb sy 800bd6e: 60fb str r3, [r7, #12] } 800bd70: bf00 nop 800bd72: bf00 nop 800bd74: e7fd b.n 800bd72 change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 800bd76: 693b ldr r3, [r7, #16] 800bd78: 689c ldr r4, [r3, #8] 800bd7a: f001 fdb7 bl 800d8ec 800bd7e: 4603 mov r3, r0 800bd80: 429c cmp r4, r3 800bd82: d111 bne.n 800bda8 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 800bd84: 693b ldr r3, [r7, #16] 800bd86: 68db ldr r3, [r3, #12] 800bd88: 1e5a subs r2, r3, #1 800bd8a: 693b ldr r3, [r7, #16] 800bd8c: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 800bd8e: 693b ldr r3, [r7, #16] 800bd90: 68db ldr r3, [r3, #12] 800bd92: 2b00 cmp r3, #0 800bd94: d105 bne.n 800bda2 { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 800bd96: 2300 movs r3, #0 800bd98: 2200 movs r2, #0 800bd9a: 2100 movs r1, #0 800bd9c: 6938 ldr r0, [r7, #16] 800bd9e: f000 f841 bl 800be24 else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 800bda2: 2301 movs r3, #1 800bda4: 617b str r3, [r7, #20] 800bda6: e001 b.n 800bdac } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 800bda8: 2300 movs r3, #0 800bdaa: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 800bdac: 697b ldr r3, [r7, #20] } 800bdae: 4618 mov r0, r3 800bdb0: 371c adds r7, #28 800bdb2: 46bd mov sp, r7 800bdb4: bd90 pop {r4, r7, pc} 0800bdb6 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 800bdb6: b590 push {r4, r7, lr} 800bdb8: b087 sub sp, #28 800bdba: af00 add r7, sp, #0 800bdbc: 6078 str r0, [r7, #4] 800bdbe: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 800bdc0: 687b ldr r3, [r7, #4] 800bdc2: 613b str r3, [r7, #16] configASSERT( pxMutex ); 800bdc4: 693b ldr r3, [r7, #16] 800bdc6: 2b00 cmp r3, #0 800bdc8: d10b bne.n 800bde2 __asm volatile 800bdca: f04f 0350 mov.w r3, #80 @ 0x50 800bdce: f383 8811 msr BASEPRI, r3 800bdd2: f3bf 8f6f isb sy 800bdd6: f3bf 8f4f dsb sy 800bdda: 60fb str r3, [r7, #12] } 800bddc: bf00 nop 800bdde: bf00 nop 800bde0: e7fd b.n 800bdde /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 800bde2: 693b ldr r3, [r7, #16] 800bde4: 689c ldr r4, [r3, #8] 800bde6: f001 fd81 bl 800d8ec 800bdea: 4603 mov r3, r0 800bdec: 429c cmp r4, r3 800bdee: d107 bne.n 800be00 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 800bdf0: 693b ldr r3, [r7, #16] 800bdf2: 68db ldr r3, [r3, #12] 800bdf4: 1c5a adds r2, r3, #1 800bdf6: 693b ldr r3, [r7, #16] 800bdf8: 60da str r2, [r3, #12] xReturn = pdPASS; 800bdfa: 2301 movs r3, #1 800bdfc: 617b str r3, [r7, #20] 800bdfe: e00c b.n 800be1a } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 800be00: 6839 ldr r1, [r7, #0] 800be02: 6938 ldr r0, [r7, #16] 800be04: f000 fa90 bl 800c328 800be08: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 800be0a: 697b ldr r3, [r7, #20] 800be0c: 2b00 cmp r3, #0 800be0e: d004 beq.n 800be1a { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 800be10: 693b ldr r3, [r7, #16] 800be12: 68db ldr r3, [r3, #12] 800be14: 1c5a adds r2, r3, #1 800be16: 693b ldr r3, [r7, #16] 800be18: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 800be1a: 697b ldr r3, [r7, #20] } 800be1c: 4618 mov r0, r3 800be1e: 371c adds r7, #28 800be20: 46bd mov sp, r7 800be22: bd90 pop {r4, r7, pc} 0800be24 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 800be24: b580 push {r7, lr} 800be26: b08e sub sp, #56 @ 0x38 800be28: af00 add r7, sp, #0 800be2a: 60f8 str r0, [r7, #12] 800be2c: 60b9 str r1, [r7, #8] 800be2e: 607a str r2, [r7, #4] 800be30: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 800be32: 2300 movs r3, #0 800be34: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 800be36: 68fb ldr r3, [r7, #12] 800be38: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 800be3a: 6b3b ldr r3, [r7, #48] @ 0x30 800be3c: 2b00 cmp r3, #0 800be3e: d10b bne.n 800be58 __asm volatile 800be40: f04f 0350 mov.w r3, #80 @ 0x50 800be44: f383 8811 msr BASEPRI, r3 800be48: f3bf 8f6f isb sy 800be4c: f3bf 8f4f dsb sy 800be50: 62bb str r3, [r7, #40] @ 0x28 } 800be52: bf00 nop 800be54: bf00 nop 800be56: e7fd b.n 800be54 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800be58: 68bb ldr r3, [r7, #8] 800be5a: 2b00 cmp r3, #0 800be5c: d103 bne.n 800be66 800be5e: 6b3b ldr r3, [r7, #48] @ 0x30 800be60: 6c1b ldr r3, [r3, #64] @ 0x40 800be62: 2b00 cmp r3, #0 800be64: d101 bne.n 800be6a 800be66: 2301 movs r3, #1 800be68: e000 b.n 800be6c 800be6a: 2300 movs r3, #0 800be6c: 2b00 cmp r3, #0 800be6e: d10b bne.n 800be88 __asm volatile 800be70: f04f 0350 mov.w r3, #80 @ 0x50 800be74: f383 8811 msr BASEPRI, r3 800be78: f3bf 8f6f isb sy 800be7c: f3bf 8f4f dsb sy 800be80: 627b str r3, [r7, #36] @ 0x24 } 800be82: bf00 nop 800be84: bf00 nop 800be86: e7fd b.n 800be84 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 800be88: 683b ldr r3, [r7, #0] 800be8a: 2b02 cmp r3, #2 800be8c: d103 bne.n 800be96 800be8e: 6b3b ldr r3, [r7, #48] @ 0x30 800be90: 6bdb ldr r3, [r3, #60] @ 0x3c 800be92: 2b01 cmp r3, #1 800be94: d101 bne.n 800be9a 800be96: 2301 movs r3, #1 800be98: e000 b.n 800be9c 800be9a: 2300 movs r3, #0 800be9c: 2b00 cmp r3, #0 800be9e: d10b bne.n 800beb8 __asm volatile 800bea0: f04f 0350 mov.w r3, #80 @ 0x50 800bea4: f383 8811 msr BASEPRI, r3 800bea8: f3bf 8f6f isb sy 800beac: f3bf 8f4f dsb sy 800beb0: 623b str r3, [r7, #32] } 800beb2: bf00 nop 800beb4: bf00 nop 800beb6: e7fd b.n 800beb4 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800beb8: f001 fd28 bl 800d90c 800bebc: 4603 mov r3, r0 800bebe: 2b00 cmp r3, #0 800bec0: d102 bne.n 800bec8 800bec2: 687b ldr r3, [r7, #4] 800bec4: 2b00 cmp r3, #0 800bec6: d101 bne.n 800becc 800bec8: 2301 movs r3, #1 800beca: e000 b.n 800bece 800becc: 2300 movs r3, #0 800bece: 2b00 cmp r3, #0 800bed0: d10b bne.n 800beea __asm volatile 800bed2: f04f 0350 mov.w r3, #80 @ 0x50 800bed6: f383 8811 msr BASEPRI, r3 800beda: f3bf 8f6f isb sy 800bede: f3bf 8f4f dsb sy 800bee2: 61fb str r3, [r7, #28] } 800bee4: bf00 nop 800bee6: bf00 nop 800bee8: e7fd b.n 800bee6 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 800beea: f002 fdad bl 800ea48 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 800beee: 6b3b ldr r3, [r7, #48] @ 0x30 800bef0: 6b9a ldr r2, [r3, #56] @ 0x38 800bef2: 6b3b ldr r3, [r7, #48] @ 0x30 800bef4: 6bdb ldr r3, [r3, #60] @ 0x3c 800bef6: 429a cmp r2, r3 800bef8: d302 bcc.n 800bf00 800befa: 683b ldr r3, [r7, #0] 800befc: 2b02 cmp r3, #2 800befe: d129 bne.n 800bf54 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 800bf00: 683a ldr r2, [r7, #0] 800bf02: 68b9 ldr r1, [r7, #8] 800bf04: 6b38 ldr r0, [r7, #48] @ 0x30 800bf06: f000 fb37 bl 800c578 800bf0a: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800bf0c: 6b3b ldr r3, [r7, #48] @ 0x30 800bf0e: 6a5b ldr r3, [r3, #36] @ 0x24 800bf10: 2b00 cmp r3, #0 800bf12: d010 beq.n 800bf36 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800bf14: 6b3b ldr r3, [r7, #48] @ 0x30 800bf16: 3324 adds r3, #36 @ 0x24 800bf18: 4618 mov r0, r3 800bf1a: f001 faf9 bl 800d510 800bf1e: 4603 mov r3, r0 800bf20: 2b00 cmp r3, #0 800bf22: d013 beq.n 800bf4c { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 800bf24: 4b3f ldr r3, [pc, #252] @ (800c024 ) 800bf26: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800bf2a: 601a str r2, [r3, #0] 800bf2c: f3bf 8f4f dsb sy 800bf30: f3bf 8f6f isb sy 800bf34: e00a b.n 800bf4c else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 800bf36: 6afb ldr r3, [r7, #44] @ 0x2c 800bf38: 2b00 cmp r3, #0 800bf3a: d007 beq.n 800bf4c { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 800bf3c: 4b39 ldr r3, [pc, #228] @ (800c024 ) 800bf3e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800bf42: 601a str r2, [r3, #0] 800bf44: f3bf 8f4f dsb sy 800bf48: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 800bf4c: f002 fdae bl 800eaac return pdPASS; 800bf50: 2301 movs r3, #1 800bf52: e063 b.n 800c01c } else { if( xTicksToWait == ( TickType_t ) 0 ) 800bf54: 687b ldr r3, [r7, #4] 800bf56: 2b00 cmp r3, #0 800bf58: d103 bne.n 800bf62 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 800bf5a: f002 fda7 bl 800eaac /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 800bf5e: 2300 movs r3, #0 800bf60: e05c b.n 800c01c } else if( xEntryTimeSet == pdFALSE ) 800bf62: 6b7b ldr r3, [r7, #52] @ 0x34 800bf64: 2b00 cmp r3, #0 800bf66: d106 bne.n 800bf76 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 800bf68: f107 0314 add.w r3, r7, #20 800bf6c: 4618 mov r0, r3 800bf6e: f001 fb5b bl 800d628 xEntryTimeSet = pdTRUE; 800bf72: 2301 movs r3, #1 800bf74: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 800bf76: f002 fd99 bl 800eaac /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 800bf7a: f001 f88d bl 800d098 prvLockQueue( pxQueue ); 800bf7e: f002 fd63 bl 800ea48 800bf82: 6b3b ldr r3, [r7, #48] @ 0x30 800bf84: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800bf88: b25b sxtb r3, r3 800bf8a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800bf8e: d103 bne.n 800bf98 800bf90: 6b3b ldr r3, [r7, #48] @ 0x30 800bf92: 2200 movs r2, #0 800bf94: f883 2044 strb.w r2, [r3, #68] @ 0x44 800bf98: 6b3b ldr r3, [r7, #48] @ 0x30 800bf9a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800bf9e: b25b sxtb r3, r3 800bfa0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800bfa4: d103 bne.n 800bfae 800bfa6: 6b3b ldr r3, [r7, #48] @ 0x30 800bfa8: 2200 movs r2, #0 800bfaa: f883 2045 strb.w r2, [r3, #69] @ 0x45 800bfae: f002 fd7d bl 800eaac /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 800bfb2: 1d3a adds r2, r7, #4 800bfb4: f107 0314 add.w r3, r7, #20 800bfb8: 4611 mov r1, r2 800bfba: 4618 mov r0, r3 800bfbc: f001 fb4a bl 800d654 800bfc0: 4603 mov r3, r0 800bfc2: 2b00 cmp r3, #0 800bfc4: d124 bne.n 800c010 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 800bfc6: 6b38 ldr r0, [r7, #48] @ 0x30 800bfc8: f000 fbce bl 800c768 800bfcc: 4603 mov r3, r0 800bfce: 2b00 cmp r3, #0 800bfd0: d018 beq.n 800c004 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 800bfd2: 6b3b ldr r3, [r7, #48] @ 0x30 800bfd4: 3310 adds r3, #16 800bfd6: 687a ldr r2, [r7, #4] 800bfd8: 4611 mov r1, r2 800bfda: 4618 mov r0, r3 800bfdc: f001 fa46 bl 800d46c /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 800bfe0: 6b38 ldr r0, [r7, #48] @ 0x30 800bfe2: f000 fb59 bl 800c698 /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 800bfe6: f001 f865 bl 800d0b4 800bfea: 4603 mov r3, r0 800bfec: 2b00 cmp r3, #0 800bfee: f47f af7c bne.w 800beea { portYIELD_WITHIN_API(); 800bff2: 4b0c ldr r3, [pc, #48] @ (800c024 ) 800bff4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800bff8: 601a str r2, [r3, #0] 800bffa: f3bf 8f4f dsb sy 800bffe: f3bf 8f6f isb sy 800c002: e772 b.n 800beea } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 800c004: 6b38 ldr r0, [r7, #48] @ 0x30 800c006: f000 fb47 bl 800c698 ( void ) xTaskResumeAll(); 800c00a: f001 f853 bl 800d0b4 800c00e: e76c b.n 800beea } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 800c010: 6b38 ldr r0, [r7, #48] @ 0x30 800c012: f000 fb41 bl 800c698 ( void ) xTaskResumeAll(); 800c016: f001 f84d bl 800d0b4 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 800c01a: 2300 movs r3, #0 } } /*lint -restore */ } 800c01c: 4618 mov r0, r3 800c01e: 3738 adds r7, #56 @ 0x38 800c020: 46bd mov sp, r7 800c022: bd80 pop {r7, pc} 800c024: e000ed04 .word 0xe000ed04 0800c028 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 800c028: b580 push {r7, lr} 800c02a: b090 sub sp, #64 @ 0x40 800c02c: af00 add r7, sp, #0 800c02e: 60f8 str r0, [r7, #12] 800c030: 60b9 str r1, [r7, #8] 800c032: 607a str r2, [r7, #4] 800c034: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 800c036: 68fb ldr r3, [r7, #12] 800c038: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 800c03a: 6bbb ldr r3, [r7, #56] @ 0x38 800c03c: 2b00 cmp r3, #0 800c03e: d10b bne.n 800c058 __asm volatile 800c040: f04f 0350 mov.w r3, #80 @ 0x50 800c044: f383 8811 msr BASEPRI, r3 800c048: f3bf 8f6f isb sy 800c04c: f3bf 8f4f dsb sy 800c050: 62bb str r3, [r7, #40] @ 0x28 } 800c052: bf00 nop 800c054: bf00 nop 800c056: e7fd b.n 800c054 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800c058: 68bb ldr r3, [r7, #8] 800c05a: 2b00 cmp r3, #0 800c05c: d103 bne.n 800c066 800c05e: 6bbb ldr r3, [r7, #56] @ 0x38 800c060: 6c1b ldr r3, [r3, #64] @ 0x40 800c062: 2b00 cmp r3, #0 800c064: d101 bne.n 800c06a 800c066: 2301 movs r3, #1 800c068: e000 b.n 800c06c 800c06a: 2300 movs r3, #0 800c06c: 2b00 cmp r3, #0 800c06e: d10b bne.n 800c088 __asm volatile 800c070: f04f 0350 mov.w r3, #80 @ 0x50 800c074: f383 8811 msr BASEPRI, r3 800c078: f3bf 8f6f isb sy 800c07c: f3bf 8f4f dsb sy 800c080: 627b str r3, [r7, #36] @ 0x24 } 800c082: bf00 nop 800c084: bf00 nop 800c086: e7fd b.n 800c084 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 800c088: 683b ldr r3, [r7, #0] 800c08a: 2b02 cmp r3, #2 800c08c: d103 bne.n 800c096 800c08e: 6bbb ldr r3, [r7, #56] @ 0x38 800c090: 6bdb ldr r3, [r3, #60] @ 0x3c 800c092: 2b01 cmp r3, #1 800c094: d101 bne.n 800c09a 800c096: 2301 movs r3, #1 800c098: e000 b.n 800c09c 800c09a: 2300 movs r3, #0 800c09c: 2b00 cmp r3, #0 800c09e: d10b bne.n 800c0b8 __asm volatile 800c0a0: f04f 0350 mov.w r3, #80 @ 0x50 800c0a4: f383 8811 msr BASEPRI, r3 800c0a8: f3bf 8f6f isb sy 800c0ac: f3bf 8f4f dsb sy 800c0b0: 623b str r3, [r7, #32] } 800c0b2: bf00 nop 800c0b4: bf00 nop 800c0b6: e7fd b.n 800c0b4 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 800c0b8: f002 fda6 bl 800ec08 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 800c0bc: f3ef 8211 mrs r2, BASEPRI 800c0c0: f04f 0350 mov.w r3, #80 @ 0x50 800c0c4: f383 8811 msr BASEPRI, r3 800c0c8: f3bf 8f6f isb sy 800c0cc: f3bf 8f4f dsb sy 800c0d0: 61fa str r2, [r7, #28] 800c0d2: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 800c0d4: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 800c0d6: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 800c0d8: 6bbb ldr r3, [r7, #56] @ 0x38 800c0da: 6b9a ldr r2, [r3, #56] @ 0x38 800c0dc: 6bbb ldr r3, [r7, #56] @ 0x38 800c0de: 6bdb ldr r3, [r3, #60] @ 0x3c 800c0e0: 429a cmp r2, r3 800c0e2: d302 bcc.n 800c0ea 800c0e4: 683b ldr r3, [r7, #0] 800c0e6: 2b02 cmp r3, #2 800c0e8: d12f bne.n 800c14a { const int8_t cTxLock = pxQueue->cTxLock; 800c0ea: 6bbb ldr r3, [r7, #56] @ 0x38 800c0ec: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800c0f0: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 800c0f4: 6bbb ldr r3, [r7, #56] @ 0x38 800c0f6: 6b9b ldr r3, [r3, #56] @ 0x38 800c0f8: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 800c0fa: 683a ldr r2, [r7, #0] 800c0fc: 68b9 ldr r1, [r7, #8] 800c0fe: 6bb8 ldr r0, [r7, #56] @ 0x38 800c100: f000 fa3a bl 800c578 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 800c104: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 800c108: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800c10c: d112 bne.n 800c134 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c10e: 6bbb ldr r3, [r7, #56] @ 0x38 800c110: 6a5b ldr r3, [r3, #36] @ 0x24 800c112: 2b00 cmp r3, #0 800c114: d016 beq.n 800c144 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c116: 6bbb ldr r3, [r7, #56] @ 0x38 800c118: 3324 adds r3, #36 @ 0x24 800c11a: 4618 mov r0, r3 800c11c: f001 f9f8 bl 800d510 800c120: 4603 mov r3, r0 800c122: 2b00 cmp r3, #0 800c124: d00e beq.n 800c144 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 800c126: 687b ldr r3, [r7, #4] 800c128: 2b00 cmp r3, #0 800c12a: d00b beq.n 800c144 { *pxHigherPriorityTaskWoken = pdTRUE; 800c12c: 687b ldr r3, [r7, #4] 800c12e: 2201 movs r2, #1 800c130: 601a str r2, [r3, #0] 800c132: e007 b.n 800c144 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 800c134: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 800c138: 3301 adds r3, #1 800c13a: b2db uxtb r3, r3 800c13c: b25a sxtb r2, r3 800c13e: 6bbb ldr r3, [r7, #56] @ 0x38 800c140: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 800c144: 2301 movs r3, #1 800c146: 63fb str r3, [r7, #60] @ 0x3c { 800c148: e001 b.n 800c14e } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 800c14a: 2300 movs r3, #0 800c14c: 63fb str r3, [r7, #60] @ 0x3c 800c14e: 6b7b ldr r3, [r7, #52] @ 0x34 800c150: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 800c152: 697b ldr r3, [r7, #20] 800c154: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 800c158: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 800c15a: 6bfb ldr r3, [r7, #60] @ 0x3c } 800c15c: 4618 mov r0, r3 800c15e: 3740 adds r7, #64 @ 0x40 800c160: 46bd mov sp, r7 800c162: bd80 pop {r7, pc} 0800c164 : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 800c164: b580 push {r7, lr} 800c166: b08c sub sp, #48 @ 0x30 800c168: af00 add r7, sp, #0 800c16a: 60f8 str r0, [r7, #12] 800c16c: 60b9 str r1, [r7, #8] 800c16e: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 800c170: 2300 movs r3, #0 800c172: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 800c174: 68fb ldr r3, [r7, #12] 800c176: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 800c178: 6abb ldr r3, [r7, #40] @ 0x28 800c17a: 2b00 cmp r3, #0 800c17c: d10b bne.n 800c196 __asm volatile 800c17e: f04f 0350 mov.w r3, #80 @ 0x50 800c182: f383 8811 msr BASEPRI, r3 800c186: f3bf 8f6f isb sy 800c18a: f3bf 8f4f dsb sy 800c18e: 623b str r3, [r7, #32] } 800c190: bf00 nop 800c192: bf00 nop 800c194: e7fd b.n 800c192 /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 800c196: 68bb ldr r3, [r7, #8] 800c198: 2b00 cmp r3, #0 800c19a: d103 bne.n 800c1a4 800c19c: 6abb ldr r3, [r7, #40] @ 0x28 800c19e: 6c1b ldr r3, [r3, #64] @ 0x40 800c1a0: 2b00 cmp r3, #0 800c1a2: d101 bne.n 800c1a8 800c1a4: 2301 movs r3, #1 800c1a6: e000 b.n 800c1aa 800c1a8: 2300 movs r3, #0 800c1aa: 2b00 cmp r3, #0 800c1ac: d10b bne.n 800c1c6 __asm volatile 800c1ae: f04f 0350 mov.w r3, #80 @ 0x50 800c1b2: f383 8811 msr BASEPRI, r3 800c1b6: f3bf 8f6f isb sy 800c1ba: f3bf 8f4f dsb sy 800c1be: 61fb str r3, [r7, #28] } 800c1c0: bf00 nop 800c1c2: bf00 nop 800c1c4: e7fd b.n 800c1c2 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800c1c6: f001 fba1 bl 800d90c 800c1ca: 4603 mov r3, r0 800c1cc: 2b00 cmp r3, #0 800c1ce: d102 bne.n 800c1d6 800c1d0: 687b ldr r3, [r7, #4] 800c1d2: 2b00 cmp r3, #0 800c1d4: d101 bne.n 800c1da 800c1d6: 2301 movs r3, #1 800c1d8: e000 b.n 800c1dc 800c1da: 2300 movs r3, #0 800c1dc: 2b00 cmp r3, #0 800c1de: d10b bne.n 800c1f8 __asm volatile 800c1e0: f04f 0350 mov.w r3, #80 @ 0x50 800c1e4: f383 8811 msr BASEPRI, r3 800c1e8: f3bf 8f6f isb sy 800c1ec: f3bf 8f4f dsb sy 800c1f0: 61bb str r3, [r7, #24] } 800c1f2: bf00 nop 800c1f4: bf00 nop 800c1f6: e7fd b.n 800c1f4 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 800c1f8: f002 fc26 bl 800ea48 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 800c1fc: 6abb ldr r3, [r7, #40] @ 0x28 800c1fe: 6b9b ldr r3, [r3, #56] @ 0x38 800c200: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 800c202: 6a7b ldr r3, [r7, #36] @ 0x24 800c204: 2b00 cmp r3, #0 800c206: d01f beq.n 800c248 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 800c208: 68b9 ldr r1, [r7, #8] 800c20a: 6ab8 ldr r0, [r7, #40] @ 0x28 800c20c: f000 fa1e bl 800c64c traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 800c210: 6a7b ldr r3, [r7, #36] @ 0x24 800c212: 1e5a subs r2, r3, #1 800c214: 6abb ldr r3, [r7, #40] @ 0x28 800c216: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c218: 6abb ldr r3, [r7, #40] @ 0x28 800c21a: 691b ldr r3, [r3, #16] 800c21c: 2b00 cmp r3, #0 800c21e: d00f beq.n 800c240 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c220: 6abb ldr r3, [r7, #40] @ 0x28 800c222: 3310 adds r3, #16 800c224: 4618 mov r0, r3 800c226: f001 f973 bl 800d510 800c22a: 4603 mov r3, r0 800c22c: 2b00 cmp r3, #0 800c22e: d007 beq.n 800c240 { queueYIELD_IF_USING_PREEMPTION(); 800c230: 4b3c ldr r3, [pc, #240] @ (800c324 ) 800c232: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800c236: 601a str r2, [r3, #0] 800c238: f3bf 8f4f dsb sy 800c23c: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 800c240: f002 fc34 bl 800eaac return pdPASS; 800c244: 2301 movs r3, #1 800c246: e069 b.n 800c31c } else { if( xTicksToWait == ( TickType_t ) 0 ) 800c248: 687b ldr r3, [r7, #4] 800c24a: 2b00 cmp r3, #0 800c24c: d103 bne.n 800c256 { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 800c24e: f002 fc2d bl 800eaac traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 800c252: 2300 movs r3, #0 800c254: e062 b.n 800c31c } else if( xEntryTimeSet == pdFALSE ) 800c256: 6afb ldr r3, [r7, #44] @ 0x2c 800c258: 2b00 cmp r3, #0 800c25a: d106 bne.n 800c26a { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 800c25c: f107 0310 add.w r3, r7, #16 800c260: 4618 mov r0, r3 800c262: f001 f9e1 bl 800d628 xEntryTimeSet = pdTRUE; 800c266: 2301 movs r3, #1 800c268: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 800c26a: f002 fc1f bl 800eaac /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 800c26e: f000 ff13 bl 800d098 prvLockQueue( pxQueue ); 800c272: f002 fbe9 bl 800ea48 800c276: 6abb ldr r3, [r7, #40] @ 0x28 800c278: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800c27c: b25b sxtb r3, r3 800c27e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800c282: d103 bne.n 800c28c 800c284: 6abb ldr r3, [r7, #40] @ 0x28 800c286: 2200 movs r2, #0 800c288: f883 2044 strb.w r2, [r3, #68] @ 0x44 800c28c: 6abb ldr r3, [r7, #40] @ 0x28 800c28e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800c292: b25b sxtb r3, r3 800c294: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800c298: d103 bne.n 800c2a2 800c29a: 6abb ldr r3, [r7, #40] @ 0x28 800c29c: 2200 movs r2, #0 800c29e: f883 2045 strb.w r2, [r3, #69] @ 0x45 800c2a2: f002 fc03 bl 800eaac /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 800c2a6: 1d3a adds r2, r7, #4 800c2a8: f107 0310 add.w r3, r7, #16 800c2ac: 4611 mov r1, r2 800c2ae: 4618 mov r0, r3 800c2b0: f001 f9d0 bl 800d654 800c2b4: 4603 mov r3, r0 800c2b6: 2b00 cmp r3, #0 800c2b8: d123 bne.n 800c302 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 800c2ba: 6ab8 ldr r0, [r7, #40] @ 0x28 800c2bc: f000 fa3e bl 800c73c 800c2c0: 4603 mov r3, r0 800c2c2: 2b00 cmp r3, #0 800c2c4: d017 beq.n 800c2f6 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 800c2c6: 6abb ldr r3, [r7, #40] @ 0x28 800c2c8: 3324 adds r3, #36 @ 0x24 800c2ca: 687a ldr r2, [r7, #4] 800c2cc: 4611 mov r1, r2 800c2ce: 4618 mov r0, r3 800c2d0: f001 f8cc bl 800d46c prvUnlockQueue( pxQueue ); 800c2d4: 6ab8 ldr r0, [r7, #40] @ 0x28 800c2d6: f000 f9df bl 800c698 if( xTaskResumeAll() == pdFALSE ) 800c2da: f000 feeb bl 800d0b4 800c2de: 4603 mov r3, r0 800c2e0: 2b00 cmp r3, #0 800c2e2: d189 bne.n 800c1f8 { portYIELD_WITHIN_API(); 800c2e4: 4b0f ldr r3, [pc, #60] @ (800c324 ) 800c2e6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800c2ea: 601a str r2, [r3, #0] 800c2ec: f3bf 8f4f dsb sy 800c2f0: f3bf 8f6f isb sy 800c2f4: e780 b.n 800c1f8 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 800c2f6: 6ab8 ldr r0, [r7, #40] @ 0x28 800c2f8: f000 f9ce bl 800c698 ( void ) xTaskResumeAll(); 800c2fc: f000 feda bl 800d0b4 800c300: e77a b.n 800c1f8 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 800c302: 6ab8 ldr r0, [r7, #40] @ 0x28 800c304: f000 f9c8 bl 800c698 ( void ) xTaskResumeAll(); 800c308: f000 fed4 bl 800d0b4 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 800c30c: 6ab8 ldr r0, [r7, #40] @ 0x28 800c30e: f000 fa15 bl 800c73c 800c312: 4603 mov r3, r0 800c314: 2b00 cmp r3, #0 800c316: f43f af6f beq.w 800c1f8 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 800c31a: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 800c31c: 4618 mov r0, r3 800c31e: 3730 adds r7, #48 @ 0x30 800c320: 46bd mov sp, r7 800c322: bd80 pop {r7, pc} 800c324: e000ed04 .word 0xe000ed04 0800c328 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 800c328: b580 push {r7, lr} 800c32a: b08e sub sp, #56 @ 0x38 800c32c: af00 add r7, sp, #0 800c32e: 6078 str r0, [r7, #4] 800c330: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 800c332: 2300 movs r3, #0 800c334: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 800c336: 687b ldr r3, [r7, #4] 800c338: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 800c33a: 2300 movs r3, #0 800c33c: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 800c33e: 6afb ldr r3, [r7, #44] @ 0x2c 800c340: 2b00 cmp r3, #0 800c342: d10b bne.n 800c35c __asm volatile 800c344: f04f 0350 mov.w r3, #80 @ 0x50 800c348: f383 8811 msr BASEPRI, r3 800c34c: f3bf 8f6f isb sy 800c350: f3bf 8f4f dsb sy 800c354: 623b str r3, [r7, #32] } 800c356: bf00 nop 800c358: bf00 nop 800c35a: e7fd b.n 800c358 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 800c35c: 6afb ldr r3, [r7, #44] @ 0x2c 800c35e: 6c1b ldr r3, [r3, #64] @ 0x40 800c360: 2b00 cmp r3, #0 800c362: d00b beq.n 800c37c __asm volatile 800c364: f04f 0350 mov.w r3, #80 @ 0x50 800c368: f383 8811 msr BASEPRI, r3 800c36c: f3bf 8f6f isb sy 800c370: f3bf 8f4f dsb sy 800c374: 61fb str r3, [r7, #28] } 800c376: bf00 nop 800c378: bf00 nop 800c37a: e7fd b.n 800c378 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 800c37c: f001 fac6 bl 800d90c 800c380: 4603 mov r3, r0 800c382: 2b00 cmp r3, #0 800c384: d102 bne.n 800c38c 800c386: 683b ldr r3, [r7, #0] 800c388: 2b00 cmp r3, #0 800c38a: d101 bne.n 800c390 800c38c: 2301 movs r3, #1 800c38e: e000 b.n 800c392 800c390: 2300 movs r3, #0 800c392: 2b00 cmp r3, #0 800c394: d10b bne.n 800c3ae __asm volatile 800c396: f04f 0350 mov.w r3, #80 @ 0x50 800c39a: f383 8811 msr BASEPRI, r3 800c39e: f3bf 8f6f isb sy 800c3a2: f3bf 8f4f dsb sy 800c3a6: 61bb str r3, [r7, #24] } 800c3a8: bf00 nop 800c3aa: bf00 nop 800c3ac: e7fd b.n 800c3aa /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 800c3ae: f002 fb4b bl 800ea48 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 800c3b2: 6afb ldr r3, [r7, #44] @ 0x2c 800c3b4: 6b9b ldr r3, [r3, #56] @ 0x38 800c3b6: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 800c3b8: 6abb ldr r3, [r7, #40] @ 0x28 800c3ba: 2b00 cmp r3, #0 800c3bc: d024 beq.n 800c408 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 800c3be: 6abb ldr r3, [r7, #40] @ 0x28 800c3c0: 1e5a subs r2, r3, #1 800c3c2: 6afb ldr r3, [r7, #44] @ 0x2c 800c3c4: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 800c3c6: 6afb ldr r3, [r7, #44] @ 0x2c 800c3c8: 681b ldr r3, [r3, #0] 800c3ca: 2b00 cmp r3, #0 800c3cc: d104 bne.n 800c3d8 { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 800c3ce: f001 fc17 bl 800dc00 800c3d2: 4602 mov r2, r0 800c3d4: 6afb ldr r3, [r7, #44] @ 0x2c 800c3d6: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c3d8: 6afb ldr r3, [r7, #44] @ 0x2c 800c3da: 691b ldr r3, [r3, #16] 800c3dc: 2b00 cmp r3, #0 800c3de: d00f beq.n 800c400 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c3e0: 6afb ldr r3, [r7, #44] @ 0x2c 800c3e2: 3310 adds r3, #16 800c3e4: 4618 mov r0, r3 800c3e6: f001 f893 bl 800d510 800c3ea: 4603 mov r3, r0 800c3ec: 2b00 cmp r3, #0 800c3ee: d007 beq.n 800c400 { queueYIELD_IF_USING_PREEMPTION(); 800c3f0: 4b54 ldr r3, [pc, #336] @ (800c544 ) 800c3f2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800c3f6: 601a str r2, [r3, #0] 800c3f8: f3bf 8f4f dsb sy 800c3fc: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 800c400: f002 fb54 bl 800eaac return pdPASS; 800c404: 2301 movs r3, #1 800c406: e098 b.n 800c53a } else { if( xTicksToWait == ( TickType_t ) 0 ) 800c408: 683b ldr r3, [r7, #0] 800c40a: 2b00 cmp r3, #0 800c40c: d112 bne.n 800c434 /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 800c40e: 6b3b ldr r3, [r7, #48] @ 0x30 800c410: 2b00 cmp r3, #0 800c412: d00b beq.n 800c42c __asm volatile 800c414: f04f 0350 mov.w r3, #80 @ 0x50 800c418: f383 8811 msr BASEPRI, r3 800c41c: f3bf 8f6f isb sy 800c420: f3bf 8f4f dsb sy 800c424: 617b str r3, [r7, #20] } 800c426: bf00 nop 800c428: bf00 nop 800c42a: e7fd b.n 800c428 } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 800c42c: f002 fb3e bl 800eaac traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 800c430: 2300 movs r3, #0 800c432: e082 b.n 800c53a } else if( xEntryTimeSet == pdFALSE ) 800c434: 6b7b ldr r3, [r7, #52] @ 0x34 800c436: 2b00 cmp r3, #0 800c438: d106 bne.n 800c448 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 800c43a: f107 030c add.w r3, r7, #12 800c43e: 4618 mov r0, r3 800c440: f001 f8f2 bl 800d628 xEntryTimeSet = pdTRUE; 800c444: 2301 movs r3, #1 800c446: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 800c448: f002 fb30 bl 800eaac /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 800c44c: f000 fe24 bl 800d098 prvLockQueue( pxQueue ); 800c450: f002 fafa bl 800ea48 800c454: 6afb ldr r3, [r7, #44] @ 0x2c 800c456: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800c45a: b25b sxtb r3, r3 800c45c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800c460: d103 bne.n 800c46a 800c462: 6afb ldr r3, [r7, #44] @ 0x2c 800c464: 2200 movs r2, #0 800c466: f883 2044 strb.w r2, [r3, #68] @ 0x44 800c46a: 6afb ldr r3, [r7, #44] @ 0x2c 800c46c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800c470: b25b sxtb r3, r3 800c472: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800c476: d103 bne.n 800c480 800c478: 6afb ldr r3, [r7, #44] @ 0x2c 800c47a: 2200 movs r2, #0 800c47c: f883 2045 strb.w r2, [r3, #69] @ 0x45 800c480: f002 fb14 bl 800eaac /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 800c484: 463a mov r2, r7 800c486: f107 030c add.w r3, r7, #12 800c48a: 4611 mov r1, r2 800c48c: 4618 mov r0, r3 800c48e: f001 f8e1 bl 800d654 800c492: 4603 mov r3, r0 800c494: 2b00 cmp r3, #0 800c496: d132 bne.n 800c4fe { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 800c498: 6af8 ldr r0, [r7, #44] @ 0x2c 800c49a: f000 f94f bl 800c73c 800c49e: 4603 mov r3, r0 800c4a0: 2b00 cmp r3, #0 800c4a2: d026 beq.n 800c4f2 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 800c4a4: 6afb ldr r3, [r7, #44] @ 0x2c 800c4a6: 681b ldr r3, [r3, #0] 800c4a8: 2b00 cmp r3, #0 800c4aa: d109 bne.n 800c4c0 { taskENTER_CRITICAL(); 800c4ac: f002 facc bl 800ea48 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 800c4b0: 6afb ldr r3, [r7, #44] @ 0x2c 800c4b2: 689b ldr r3, [r3, #8] 800c4b4: 4618 mov r0, r3 800c4b6: f001 fa47 bl 800d948 800c4ba: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 800c4bc: f002 faf6 bl 800eaac mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 800c4c0: 6afb ldr r3, [r7, #44] @ 0x2c 800c4c2: 3324 adds r3, #36 @ 0x24 800c4c4: 683a ldr r2, [r7, #0] 800c4c6: 4611 mov r1, r2 800c4c8: 4618 mov r0, r3 800c4ca: f000 ffcf bl 800d46c prvUnlockQueue( pxQueue ); 800c4ce: 6af8 ldr r0, [r7, #44] @ 0x2c 800c4d0: f000 f8e2 bl 800c698 if( xTaskResumeAll() == pdFALSE ) 800c4d4: f000 fdee bl 800d0b4 800c4d8: 4603 mov r3, r0 800c4da: 2b00 cmp r3, #0 800c4dc: f47f af67 bne.w 800c3ae { portYIELD_WITHIN_API(); 800c4e0: 4b18 ldr r3, [pc, #96] @ (800c544 ) 800c4e2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800c4e6: 601a str r2, [r3, #0] 800c4e8: f3bf 8f4f dsb sy 800c4ec: f3bf 8f6f isb sy 800c4f0: e75d b.n 800c3ae } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 800c4f2: 6af8 ldr r0, [r7, #44] @ 0x2c 800c4f4: f000 f8d0 bl 800c698 ( void ) xTaskResumeAll(); 800c4f8: f000 fddc bl 800d0b4 800c4fc: e757 b.n 800c3ae } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 800c4fe: 6af8 ldr r0, [r7, #44] @ 0x2c 800c500: f000 f8ca bl 800c698 ( void ) xTaskResumeAll(); 800c504: f000 fdd6 bl 800d0b4 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 800c508: 6af8 ldr r0, [r7, #44] @ 0x2c 800c50a: f000 f917 bl 800c73c 800c50e: 4603 mov r3, r0 800c510: 2b00 cmp r3, #0 800c512: f43f af4c beq.w 800c3ae #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 800c516: 6b3b ldr r3, [r7, #48] @ 0x30 800c518: 2b00 cmp r3, #0 800c51a: d00d beq.n 800c538 { taskENTER_CRITICAL(); 800c51c: f002 fa94 bl 800ea48 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 800c520: 6af8 ldr r0, [r7, #44] @ 0x2c 800c522: f000 f811 bl 800c548 800c526: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 800c528: 6afb ldr r3, [r7, #44] @ 0x2c 800c52a: 689b ldr r3, [r3, #8] 800c52c: 6a79 ldr r1, [r7, #36] @ 0x24 800c52e: 4618 mov r0, r3 800c530: f001 fae2 bl 800daf8 } taskEXIT_CRITICAL(); 800c534: f002 faba bl 800eaac } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 800c538: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 800c53a: 4618 mov r0, r3 800c53c: 3738 adds r7, #56 @ 0x38 800c53e: 46bd mov sp, r7 800c540: bd80 pop {r7, pc} 800c542: bf00 nop 800c544: e000ed04 .word 0xe000ed04 0800c548 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 800c548: b480 push {r7} 800c54a: b085 sub sp, #20 800c54c: af00 add r7, sp, #0 800c54e: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 800c550: 687b ldr r3, [r7, #4] 800c552: 6a5b ldr r3, [r3, #36] @ 0x24 800c554: 2b00 cmp r3, #0 800c556: d006 beq.n 800c566 { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 800c558: 687b ldr r3, [r7, #4] 800c55a: 6b1b ldr r3, [r3, #48] @ 0x30 800c55c: 681b ldr r3, [r3, #0] 800c55e: f1c3 0338 rsb r3, r3, #56 @ 0x38 800c562: 60fb str r3, [r7, #12] 800c564: e001 b.n 800c56a } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 800c566: 2300 movs r3, #0 800c568: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 800c56a: 68fb ldr r3, [r7, #12] } 800c56c: 4618 mov r0, r3 800c56e: 3714 adds r7, #20 800c570: 46bd mov sp, r7 800c572: f85d 7b04 ldr.w r7, [sp], #4 800c576: 4770 bx lr 0800c578 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 800c578: b580 push {r7, lr} 800c57a: b086 sub sp, #24 800c57c: af00 add r7, sp, #0 800c57e: 60f8 str r0, [r7, #12] 800c580: 60b9 str r1, [r7, #8] 800c582: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 800c584: 2300 movs r3, #0 800c586: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 800c588: 68fb ldr r3, [r7, #12] 800c58a: 6b9b ldr r3, [r3, #56] @ 0x38 800c58c: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 800c58e: 68fb ldr r3, [r7, #12] 800c590: 6c1b ldr r3, [r3, #64] @ 0x40 800c592: 2b00 cmp r3, #0 800c594: d10d bne.n 800c5b2 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 800c596: 68fb ldr r3, [r7, #12] 800c598: 681b ldr r3, [r3, #0] 800c59a: 2b00 cmp r3, #0 800c59c: d14d bne.n 800c63a { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 800c59e: 68fb ldr r3, [r7, #12] 800c5a0: 689b ldr r3, [r3, #8] 800c5a2: 4618 mov r0, r3 800c5a4: f001 fa38 bl 800da18 800c5a8: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 800c5aa: 68fb ldr r3, [r7, #12] 800c5ac: 2200 movs r2, #0 800c5ae: 609a str r2, [r3, #8] 800c5b0: e043 b.n 800c63a mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 800c5b2: 687b ldr r3, [r7, #4] 800c5b4: 2b00 cmp r3, #0 800c5b6: d119 bne.n 800c5ec { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 800c5b8: 68fb ldr r3, [r7, #12] 800c5ba: 6858 ldr r0, [r3, #4] 800c5bc: 68fb ldr r3, [r7, #12] 800c5be: 6c1b ldr r3, [r3, #64] @ 0x40 800c5c0: 461a mov r2, r3 800c5c2: 68b9 ldr r1, [r7, #8] 800c5c4: f002 ff39 bl 800f43a pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800c5c8: 68fb ldr r3, [r7, #12] 800c5ca: 685a ldr r2, [r3, #4] 800c5cc: 68fb ldr r3, [r7, #12] 800c5ce: 6c1b ldr r3, [r3, #64] @ 0x40 800c5d0: 441a add r2, r3 800c5d2: 68fb ldr r3, [r7, #12] 800c5d4: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 800c5d6: 68fb ldr r3, [r7, #12] 800c5d8: 685a ldr r2, [r3, #4] 800c5da: 68fb ldr r3, [r7, #12] 800c5dc: 689b ldr r3, [r3, #8] 800c5de: 429a cmp r2, r3 800c5e0: d32b bcc.n 800c63a { pxQueue->pcWriteTo = pxQueue->pcHead; 800c5e2: 68fb ldr r3, [r7, #12] 800c5e4: 681a ldr r2, [r3, #0] 800c5e6: 68fb ldr r3, [r7, #12] 800c5e8: 605a str r2, [r3, #4] 800c5ea: e026 b.n 800c63a mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 800c5ec: 68fb ldr r3, [r7, #12] 800c5ee: 68d8 ldr r0, [r3, #12] 800c5f0: 68fb ldr r3, [r7, #12] 800c5f2: 6c1b ldr r3, [r3, #64] @ 0x40 800c5f4: 461a mov r2, r3 800c5f6: 68b9 ldr r1, [r7, #8] 800c5f8: f002 ff1f bl 800f43a pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 800c5fc: 68fb ldr r3, [r7, #12] 800c5fe: 68da ldr r2, [r3, #12] 800c600: 68fb ldr r3, [r7, #12] 800c602: 6c1b ldr r3, [r3, #64] @ 0x40 800c604: 425b negs r3, r3 800c606: 441a add r2, r3 800c608: 68fb ldr r3, [r7, #12] 800c60a: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 800c60c: 68fb ldr r3, [r7, #12] 800c60e: 68da ldr r2, [r3, #12] 800c610: 68fb ldr r3, [r7, #12] 800c612: 681b ldr r3, [r3, #0] 800c614: 429a cmp r2, r3 800c616: d207 bcs.n 800c628 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 800c618: 68fb ldr r3, [r7, #12] 800c61a: 689a ldr r2, [r3, #8] 800c61c: 68fb ldr r3, [r7, #12] 800c61e: 6c1b ldr r3, [r3, #64] @ 0x40 800c620: 425b negs r3, r3 800c622: 441a add r2, r3 800c624: 68fb ldr r3, [r7, #12] 800c626: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 800c628: 687b ldr r3, [r7, #4] 800c62a: 2b02 cmp r3, #2 800c62c: d105 bne.n 800c63a { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 800c62e: 693b ldr r3, [r7, #16] 800c630: 2b00 cmp r3, #0 800c632: d002 beq.n 800c63a { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 800c634: 693b ldr r3, [r7, #16] 800c636: 3b01 subs r3, #1 800c638: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 800c63a: 693b ldr r3, [r7, #16] 800c63c: 1c5a adds r2, r3, #1 800c63e: 68fb ldr r3, [r7, #12] 800c640: 639a str r2, [r3, #56] @ 0x38 return xReturn; 800c642: 697b ldr r3, [r7, #20] } 800c644: 4618 mov r0, r3 800c646: 3718 adds r7, #24 800c648: 46bd mov sp, r7 800c64a: bd80 pop {r7, pc} 0800c64c : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 800c64c: b580 push {r7, lr} 800c64e: b082 sub sp, #8 800c650: af00 add r7, sp, #0 800c652: 6078 str r0, [r7, #4] 800c654: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 800c656: 687b ldr r3, [r7, #4] 800c658: 6c1b ldr r3, [r3, #64] @ 0x40 800c65a: 2b00 cmp r3, #0 800c65c: d018 beq.n 800c690 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 800c65e: 687b ldr r3, [r7, #4] 800c660: 68da ldr r2, [r3, #12] 800c662: 687b ldr r3, [r7, #4] 800c664: 6c1b ldr r3, [r3, #64] @ 0x40 800c666: 441a add r2, r3 800c668: 687b ldr r3, [r7, #4] 800c66a: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 800c66c: 687b ldr r3, [r7, #4] 800c66e: 68da ldr r2, [r3, #12] 800c670: 687b ldr r3, [r7, #4] 800c672: 689b ldr r3, [r3, #8] 800c674: 429a cmp r2, r3 800c676: d303 bcc.n 800c680 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 800c678: 687b ldr r3, [r7, #4] 800c67a: 681a ldr r2, [r3, #0] 800c67c: 687b ldr r3, [r7, #4] 800c67e: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 800c680: 687b ldr r3, [r7, #4] 800c682: 68d9 ldr r1, [r3, #12] 800c684: 687b ldr r3, [r7, #4] 800c686: 6c1b ldr r3, [r3, #64] @ 0x40 800c688: 461a mov r2, r3 800c68a: 6838 ldr r0, [r7, #0] 800c68c: f002 fed5 bl 800f43a } } 800c690: bf00 nop 800c692: 3708 adds r7, #8 800c694: 46bd mov sp, r7 800c696: bd80 pop {r7, pc} 0800c698 : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 800c698: b580 push {r7, lr} 800c69a: b084 sub sp, #16 800c69c: af00 add r7, sp, #0 800c69e: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 800c6a0: f002 f9d2 bl 800ea48 { int8_t cTxLock = pxQueue->cTxLock; 800c6a4: 687b ldr r3, [r7, #4] 800c6a6: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800c6aa: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 800c6ac: e011 b.n 800c6d2 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800c6ae: 687b ldr r3, [r7, #4] 800c6b0: 6a5b ldr r3, [r3, #36] @ 0x24 800c6b2: 2b00 cmp r3, #0 800c6b4: d012 beq.n 800c6dc { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800c6b6: 687b ldr r3, [r7, #4] 800c6b8: 3324 adds r3, #36 @ 0x24 800c6ba: 4618 mov r0, r3 800c6bc: f000 ff28 bl 800d510 800c6c0: 4603 mov r3, r0 800c6c2: 2b00 cmp r3, #0 800c6c4: d001 beq.n 800c6ca { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 800c6c6: f001 f829 bl 800d71c break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 800c6ca: 7bfb ldrb r3, [r7, #15] 800c6cc: 3b01 subs r3, #1 800c6ce: b2db uxtb r3, r3 800c6d0: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 800c6d2: f997 300f ldrsb.w r3, [r7, #15] 800c6d6: 2b00 cmp r3, #0 800c6d8: dce9 bgt.n 800c6ae 800c6da: e000 b.n 800c6de break; 800c6dc: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 800c6de: 687b ldr r3, [r7, #4] 800c6e0: 22ff movs r2, #255 @ 0xff 800c6e2: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 800c6e6: f002 f9e1 bl 800eaac /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 800c6ea: f002 f9ad bl 800ea48 { int8_t cRxLock = pxQueue->cRxLock; 800c6ee: 687b ldr r3, [r7, #4] 800c6f0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800c6f4: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 800c6f6: e011 b.n 800c71c { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800c6f8: 687b ldr r3, [r7, #4] 800c6fa: 691b ldr r3, [r3, #16] 800c6fc: 2b00 cmp r3, #0 800c6fe: d012 beq.n 800c726 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 800c700: 687b ldr r3, [r7, #4] 800c702: 3310 adds r3, #16 800c704: 4618 mov r0, r3 800c706: f000 ff03 bl 800d510 800c70a: 4603 mov r3, r0 800c70c: 2b00 cmp r3, #0 800c70e: d001 beq.n 800c714 { vTaskMissedYield(); 800c710: f001 f804 bl 800d71c else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 800c714: 7bbb ldrb r3, [r7, #14] 800c716: 3b01 subs r3, #1 800c718: b2db uxtb r3, r3 800c71a: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 800c71c: f997 300e ldrsb.w r3, [r7, #14] 800c720: 2b00 cmp r3, #0 800c722: dce9 bgt.n 800c6f8 800c724: e000 b.n 800c728 } else { break; 800c726: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 800c728: 687b ldr r3, [r7, #4] 800c72a: 22ff movs r2, #255 @ 0xff 800c72c: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 800c730: f002 f9bc bl 800eaac } 800c734: bf00 nop 800c736: 3710 adds r7, #16 800c738: 46bd mov sp, r7 800c73a: bd80 pop {r7, pc} 0800c73c : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 800c73c: b580 push {r7, lr} 800c73e: b084 sub sp, #16 800c740: af00 add r7, sp, #0 800c742: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 800c744: f002 f980 bl 800ea48 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 800c748: 687b ldr r3, [r7, #4] 800c74a: 6b9b ldr r3, [r3, #56] @ 0x38 800c74c: 2b00 cmp r3, #0 800c74e: d102 bne.n 800c756 { xReturn = pdTRUE; 800c750: 2301 movs r3, #1 800c752: 60fb str r3, [r7, #12] 800c754: e001 b.n 800c75a } else { xReturn = pdFALSE; 800c756: 2300 movs r3, #0 800c758: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 800c75a: f002 f9a7 bl 800eaac return xReturn; 800c75e: 68fb ldr r3, [r7, #12] } 800c760: 4618 mov r0, r3 800c762: 3710 adds r7, #16 800c764: 46bd mov sp, r7 800c766: bd80 pop {r7, pc} 0800c768 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 800c768: b580 push {r7, lr} 800c76a: b084 sub sp, #16 800c76c: af00 add r7, sp, #0 800c76e: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 800c770: f002 f96a bl 800ea48 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 800c774: 687b ldr r3, [r7, #4] 800c776: 6b9a ldr r2, [r3, #56] @ 0x38 800c778: 687b ldr r3, [r7, #4] 800c77a: 6bdb ldr r3, [r3, #60] @ 0x3c 800c77c: 429a cmp r2, r3 800c77e: d102 bne.n 800c786 { xReturn = pdTRUE; 800c780: 2301 movs r3, #1 800c782: 60fb str r3, [r7, #12] 800c784: e001 b.n 800c78a } else { xReturn = pdFALSE; 800c786: 2300 movs r3, #0 800c788: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 800c78a: f002 f98f bl 800eaac return xReturn; 800c78e: 68fb ldr r3, [r7, #12] } 800c790: 4618 mov r0, r3 800c792: 3710 adds r7, #16 800c794: 46bd mov sp, r7 800c796: bd80 pop {r7, pc} 0800c798 : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 800c798: b480 push {r7} 800c79a: b085 sub sp, #20 800c79c: af00 add r7, sp, #0 800c79e: 6078 str r0, [r7, #4] 800c7a0: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 800c7a2: 2300 movs r3, #0 800c7a4: 60fb str r3, [r7, #12] 800c7a6: e014 b.n 800c7d2 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 800c7a8: 4a0f ldr r2, [pc, #60] @ (800c7e8 ) 800c7aa: 68fb ldr r3, [r7, #12] 800c7ac: f852 3033 ldr.w r3, [r2, r3, lsl #3] 800c7b0: 2b00 cmp r3, #0 800c7b2: d10b bne.n 800c7cc { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 800c7b4: 490c ldr r1, [pc, #48] @ (800c7e8 ) 800c7b6: 68fb ldr r3, [r7, #12] 800c7b8: 683a ldr r2, [r7, #0] 800c7ba: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 800c7be: 4a0a ldr r2, [pc, #40] @ (800c7e8 ) 800c7c0: 68fb ldr r3, [r7, #12] 800c7c2: 00db lsls r3, r3, #3 800c7c4: 4413 add r3, r2 800c7c6: 687a ldr r2, [r7, #4] 800c7c8: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 800c7ca: e006 b.n 800c7da for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 800c7cc: 68fb ldr r3, [r7, #12] 800c7ce: 3301 adds r3, #1 800c7d0: 60fb str r3, [r7, #12] 800c7d2: 68fb ldr r3, [r7, #12] 800c7d4: 2b07 cmp r3, #7 800c7d6: d9e7 bls.n 800c7a8 else { mtCOVERAGE_TEST_MARKER(); } } } 800c7d8: bf00 nop 800c7da: bf00 nop 800c7dc: 3714 adds r7, #20 800c7de: 46bd mov sp, r7 800c7e0: f85d 7b04 ldr.w r7, [sp], #4 800c7e4: 4770 bx lr 800c7e6: bf00 nop 800c7e8: 240020e8 .word 0x240020e8 0800c7ec : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 800c7ec: b580 push {r7, lr} 800c7ee: b086 sub sp, #24 800c7f0: af00 add r7, sp, #0 800c7f2: 60f8 str r0, [r7, #12] 800c7f4: 60b9 str r1, [r7, #8] 800c7f6: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 800c7f8: 68fb ldr r3, [r7, #12] 800c7fa: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 800c7fc: f002 f924 bl 800ea48 800c800: 697b ldr r3, [r7, #20] 800c802: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800c806: b25b sxtb r3, r3 800c808: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800c80c: d103 bne.n 800c816 800c80e: 697b ldr r3, [r7, #20] 800c810: 2200 movs r2, #0 800c812: f883 2044 strb.w r2, [r3, #68] @ 0x44 800c816: 697b ldr r3, [r7, #20] 800c818: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800c81c: b25b sxtb r3, r3 800c81e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800c822: d103 bne.n 800c82c 800c824: 697b ldr r3, [r7, #20] 800c826: 2200 movs r2, #0 800c828: f883 2045 strb.w r2, [r3, #69] @ 0x45 800c82c: f002 f93e bl 800eaac if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 800c830: 697b ldr r3, [r7, #20] 800c832: 6b9b ldr r3, [r3, #56] @ 0x38 800c834: 2b00 cmp r3, #0 800c836: d106 bne.n 800c846 { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 800c838: 697b ldr r3, [r7, #20] 800c83a: 3324 adds r3, #36 @ 0x24 800c83c: 687a ldr r2, [r7, #4] 800c83e: 68b9 ldr r1, [r7, #8] 800c840: 4618 mov r0, r3 800c842: f000 fe39 bl 800d4b8 } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 800c846: 6978 ldr r0, [r7, #20] 800c848: f7ff ff26 bl 800c698 } 800c84c: bf00 nop 800c84e: 3718 adds r7, #24 800c850: 46bd mov sp, r7 800c852: bd80 pop {r7, pc} 0800c854 : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 800c854: b480 push {r7} 800c856: b087 sub sp, #28 800c858: af00 add r7, sp, #0 800c85a: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 800c85c: 687b ldr r3, [r7, #4] 800c85e: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 800c860: 693b ldr r3, [r7, #16] 800c862: 2b00 cmp r3, #0 800c864: d10b bne.n 800c87e __asm volatile 800c866: f04f 0350 mov.w r3, #80 @ 0x50 800c86a: f383 8811 msr BASEPRI, r3 800c86e: f3bf 8f6f isb sy 800c872: f3bf 8f4f dsb sy 800c876: 60fb str r3, [r7, #12] } 800c878: bf00 nop 800c87a: bf00 nop 800c87c: e7fd b.n 800c87a xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 800c87e: 693b ldr r3, [r7, #16] 800c880: 689a ldr r2, [r3, #8] 800c882: 693b ldr r3, [r7, #16] 800c884: 681b ldr r3, [r3, #0] 800c886: 4413 add r3, r2 800c888: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 800c88a: 693b ldr r3, [r7, #16] 800c88c: 685b ldr r3, [r3, #4] 800c88e: 697a ldr r2, [r7, #20] 800c890: 1ad3 subs r3, r2, r3 800c892: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 800c894: 697b ldr r3, [r7, #20] 800c896: 3b01 subs r3, #1 800c898: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 800c89a: 693b ldr r3, [r7, #16] 800c89c: 689b ldr r3, [r3, #8] 800c89e: 697a ldr r2, [r7, #20] 800c8a0: 429a cmp r2, r3 800c8a2: d304 bcc.n 800c8ae { xSpace -= pxStreamBuffer->xLength; 800c8a4: 693b ldr r3, [r7, #16] 800c8a6: 689b ldr r3, [r3, #8] 800c8a8: 697a ldr r2, [r7, #20] 800c8aa: 1ad3 subs r3, r2, r3 800c8ac: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 800c8ae: 697b ldr r3, [r7, #20] } 800c8b0: 4618 mov r0, r3 800c8b2: 371c adds r7, #28 800c8b4: 46bd mov sp, r7 800c8b6: f85d 7b04 ldr.w r7, [sp], #4 800c8ba: 4770 bx lr 0800c8bc : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 800c8bc: b580 push {r7, lr} 800c8be: b090 sub sp, #64 @ 0x40 800c8c0: af02 add r7, sp, #8 800c8c2: 60f8 str r0, [r7, #12] 800c8c4: 60b9 str r1, [r7, #8] 800c8c6: 607a str r2, [r7, #4] 800c8c8: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 800c8ca: 68fb ldr r3, [r7, #12] 800c8cc: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 800c8ce: 2300 movs r3, #0 800c8d0: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 800c8d2: 687b ldr r3, [r7, #4] 800c8d4: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 800c8d6: 68bb ldr r3, [r7, #8] 800c8d8: 2b00 cmp r3, #0 800c8da: d10b bne.n 800c8f4 __asm volatile 800c8dc: f04f 0350 mov.w r3, #80 @ 0x50 800c8e0: f383 8811 msr BASEPRI, r3 800c8e4: f3bf 8f6f isb sy 800c8e8: f3bf 8f4f dsb sy 800c8ec: 627b str r3, [r7, #36] @ 0x24 } 800c8ee: bf00 nop 800c8f0: bf00 nop 800c8f2: e7fd b.n 800c8f0 configASSERT( pxStreamBuffer ); 800c8f4: 6afb ldr r3, [r7, #44] @ 0x2c 800c8f6: 2b00 cmp r3, #0 800c8f8: d10b bne.n 800c912 __asm volatile 800c8fa: f04f 0350 mov.w r3, #80 @ 0x50 800c8fe: f383 8811 msr BASEPRI, r3 800c902: f3bf 8f6f isb sy 800c906: f3bf 8f4f dsb sy 800c90a: 623b str r3, [r7, #32] } 800c90c: bf00 nop 800c90e: bf00 nop 800c910: e7fd b.n 800c90e /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 800c912: 6afb ldr r3, [r7, #44] @ 0x2c 800c914: 7f1b ldrb r3, [r3, #28] 800c916: f003 0301 and.w r3, r3, #1 800c91a: 2b00 cmp r3, #0 800c91c: d012 beq.n 800c944 { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 800c91e: 6b3b ldr r3, [r7, #48] @ 0x30 800c920: 3304 adds r3, #4 800c922: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 800c924: 6b3a ldr r2, [r7, #48] @ 0x30 800c926: 687b ldr r3, [r7, #4] 800c928: 429a cmp r2, r3 800c92a: d80b bhi.n 800c944 __asm volatile 800c92c: f04f 0350 mov.w r3, #80 @ 0x50 800c930: f383 8811 msr BASEPRI, r3 800c934: f3bf 8f6f isb sy 800c938: f3bf 8f4f dsb sy 800c93c: 61fb str r3, [r7, #28] } 800c93e: bf00 nop 800c940: bf00 nop 800c942: e7fd b.n 800c940 else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 800c944: 683b ldr r3, [r7, #0] 800c946: 2b00 cmp r3, #0 800c948: d03f beq.n 800c9ca { vTaskSetTimeOutState( &xTimeOut ); 800c94a: f107 0310 add.w r3, r7, #16 800c94e: 4618 mov r0, r3 800c950: f000 fe42 bl 800d5d8 do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 800c954: f002 f878 bl 800ea48 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 800c958: 6af8 ldr r0, [r7, #44] @ 0x2c 800c95a: f7ff ff7b bl 800c854 800c95e: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 800c960: 6b7a ldr r2, [r7, #52] @ 0x34 800c962: 6b3b ldr r3, [r7, #48] @ 0x30 800c964: 429a cmp r2, r3 800c966: d218 bcs.n 800c99a { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 800c968: 2000 movs r0, #0 800c96a: f001 fb65 bl 800e038 /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 800c96e: 6afb ldr r3, [r7, #44] @ 0x2c 800c970: 695b ldr r3, [r3, #20] 800c972: 2b00 cmp r3, #0 800c974: d00b beq.n 800c98e __asm volatile 800c976: f04f 0350 mov.w r3, #80 @ 0x50 800c97a: f383 8811 msr BASEPRI, r3 800c97e: f3bf 8f6f isb sy 800c982: f3bf 8f4f dsb sy 800c986: 61bb str r3, [r7, #24] } 800c988: bf00 nop 800c98a: bf00 nop 800c98c: e7fd b.n 800c98a pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 800c98e: f000 ffad bl 800d8ec 800c992: 4602 mov r2, r0 800c994: 6afb ldr r3, [r7, #44] @ 0x2c 800c996: 615a str r2, [r3, #20] 800c998: e002 b.n 800c9a0 } else { taskEXIT_CRITICAL(); 800c99a: f002 f887 bl 800eaac break; 800c99e: e014 b.n 800c9ca } } taskEXIT_CRITICAL(); 800c9a0: f002 f884 bl 800eaac traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 800c9a4: 683b ldr r3, [r7, #0] 800c9a6: 2200 movs r2, #0 800c9a8: 2100 movs r1, #0 800c9aa: 2000 movs r0, #0 800c9ac: f001 f93c bl 800dc28 pxStreamBuffer->xTaskWaitingToSend = NULL; 800c9b0: 6afb ldr r3, [r7, #44] @ 0x2c 800c9b2: 2200 movs r2, #0 800c9b4: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 800c9b6: 463a mov r2, r7 800c9b8: f107 0310 add.w r3, r7, #16 800c9bc: 4611 mov r1, r2 800c9be: 4618 mov r0, r3 800c9c0: f000 fe48 bl 800d654 800c9c4: 4603 mov r3, r0 800c9c6: 2b00 cmp r3, #0 800c9c8: d0c4 beq.n 800c954 else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 800c9ca: 6b7b ldr r3, [r7, #52] @ 0x34 800c9cc: 2b00 cmp r3, #0 800c9ce: d103 bne.n 800c9d8 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 800c9d0: 6af8 ldr r0, [r7, #44] @ 0x2c 800c9d2: f7ff ff3f bl 800c854 800c9d6: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 800c9d8: 6b3b ldr r3, [r7, #48] @ 0x30 800c9da: 9300 str r3, [sp, #0] 800c9dc: 6b7b ldr r3, [r7, #52] @ 0x34 800c9de: 687a ldr r2, [r7, #4] 800c9e0: 68b9 ldr r1, [r7, #8] 800c9e2: 6af8 ldr r0, [r7, #44] @ 0x2c 800c9e4: f000 f823 bl 800ca2e 800c9e8: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 800c9ea: 6abb ldr r3, [r7, #40] @ 0x28 800c9ec: 2b00 cmp r3, #0 800c9ee: d019 beq.n 800ca24 { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 800c9f0: 6af8 ldr r0, [r7, #44] @ 0x2c 800c9f2: f000 f8ce bl 800cb92 800c9f6: 4602 mov r2, r0 800c9f8: 6afb ldr r3, [r7, #44] @ 0x2c 800c9fa: 68db ldr r3, [r3, #12] 800c9fc: 429a cmp r2, r3 800c9fe: d311 bcc.n 800ca24 { sbSEND_COMPLETED( pxStreamBuffer ); 800ca00: f000 fb4a bl 800d098 800ca04: 6afb ldr r3, [r7, #44] @ 0x2c 800ca06: 691b ldr r3, [r3, #16] 800ca08: 2b00 cmp r3, #0 800ca0a: d009 beq.n 800ca20 800ca0c: 6afb ldr r3, [r7, #44] @ 0x2c 800ca0e: 6918 ldr r0, [r3, #16] 800ca10: 2300 movs r3, #0 800ca12: 2200 movs r2, #0 800ca14: 2100 movs r1, #0 800ca16: f001 f967 bl 800dce8 800ca1a: 6afb ldr r3, [r7, #44] @ 0x2c 800ca1c: 2200 movs r2, #0 800ca1e: 611a str r2, [r3, #16] 800ca20: f000 fb48 bl 800d0b4 { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 800ca24: 6abb ldr r3, [r7, #40] @ 0x28 } 800ca26: 4618 mov r0, r3 800ca28: 3738 adds r7, #56 @ 0x38 800ca2a: 46bd mov sp, r7 800ca2c: bd80 pop {r7, pc} 0800ca2e : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 800ca2e: b580 push {r7, lr} 800ca30: b086 sub sp, #24 800ca32: af00 add r7, sp, #0 800ca34: 60f8 str r0, [r7, #12] 800ca36: 60b9 str r1, [r7, #8] 800ca38: 607a str r2, [r7, #4] 800ca3a: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 800ca3c: 683b ldr r3, [r7, #0] 800ca3e: 2b00 cmp r3, #0 800ca40: d102 bne.n 800ca48 { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 800ca42: 2300 movs r3, #0 800ca44: 617b str r3, [r7, #20] 800ca46: e01d b.n 800ca84 } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 800ca48: 68fb ldr r3, [r7, #12] 800ca4a: 7f1b ldrb r3, [r3, #28] 800ca4c: f003 0301 and.w r3, r3, #1 800ca50: 2b00 cmp r3, #0 800ca52: d108 bne.n 800ca66 { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 800ca54: 2301 movs r3, #1 800ca56: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 800ca58: 687a ldr r2, [r7, #4] 800ca5a: 683b ldr r3, [r7, #0] 800ca5c: 4293 cmp r3, r2 800ca5e: bf28 it cs 800ca60: 4613 movcs r3, r2 800ca62: 607b str r3, [r7, #4] 800ca64: e00e b.n 800ca84 } else if( xSpace >= xRequiredSpace ) 800ca66: 683a ldr r2, [r7, #0] 800ca68: 6a3b ldr r3, [r7, #32] 800ca6a: 429a cmp r2, r3 800ca6c: d308 bcc.n 800ca80 { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 800ca6e: 2301 movs r3, #1 800ca70: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 800ca72: 1d3b adds r3, r7, #4 800ca74: 2204 movs r2, #4 800ca76: 4619 mov r1, r3 800ca78: 68f8 ldr r0, [r7, #12] 800ca7a: f000 f815 bl 800caa8 800ca7e: e001 b.n 800ca84 } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 800ca80: 2300 movs r3, #0 800ca82: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 800ca84: 697b ldr r3, [r7, #20] 800ca86: 2b00 cmp r3, #0 800ca88: d007 beq.n 800ca9a { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 800ca8a: 687b ldr r3, [r7, #4] 800ca8c: 461a mov r2, r3 800ca8e: 68b9 ldr r1, [r7, #8] 800ca90: 68f8 ldr r0, [r7, #12] 800ca92: f000 f809 bl 800caa8 800ca96: 6138 str r0, [r7, #16] 800ca98: e001 b.n 800ca9e } else { xReturn = 0; 800ca9a: 2300 movs r3, #0 800ca9c: 613b str r3, [r7, #16] } return xReturn; 800ca9e: 693b ldr r3, [r7, #16] } 800caa0: 4618 mov r0, r3 800caa2: 3718 adds r7, #24 800caa4: 46bd mov sp, r7 800caa6: bd80 pop {r7, pc} 0800caa8 : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 800caa8: b580 push {r7, lr} 800caaa: b08a sub sp, #40 @ 0x28 800caac: af00 add r7, sp, #0 800caae: 60f8 str r0, [r7, #12] 800cab0: 60b9 str r1, [r7, #8] 800cab2: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 800cab4: 687b ldr r3, [r7, #4] 800cab6: 2b00 cmp r3, #0 800cab8: d10b bne.n 800cad2 __asm volatile 800caba: f04f 0350 mov.w r3, #80 @ 0x50 800cabe: f383 8811 msr BASEPRI, r3 800cac2: f3bf 8f6f isb sy 800cac6: f3bf 8f4f dsb sy 800caca: 61fb str r3, [r7, #28] } 800cacc: bf00 nop 800cace: bf00 nop 800cad0: e7fd b.n 800cace xNextHead = pxStreamBuffer->xHead; 800cad2: 68fb ldr r3, [r7, #12] 800cad4: 685b ldr r3, [r3, #4] 800cad6: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 800cad8: 68fb ldr r3, [r7, #12] 800cada: 689a ldr r2, [r3, #8] 800cadc: 6a7b ldr r3, [r7, #36] @ 0x24 800cade: 1ad3 subs r3, r2, r3 800cae0: 687a ldr r2, [r7, #4] 800cae2: 4293 cmp r3, r2 800cae4: bf28 it cs 800cae6: 4613 movcs r3, r2 800cae8: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 800caea: 6a7a ldr r2, [r7, #36] @ 0x24 800caec: 6a3b ldr r3, [r7, #32] 800caee: 441a add r2, r3 800caf0: 68fb ldr r3, [r7, #12] 800caf2: 689b ldr r3, [r3, #8] 800caf4: 429a cmp r2, r3 800caf6: d90b bls.n 800cb10 __asm volatile 800caf8: f04f 0350 mov.w r3, #80 @ 0x50 800cafc: f383 8811 msr BASEPRI, r3 800cb00: f3bf 8f6f isb sy 800cb04: f3bf 8f4f dsb sy 800cb08: 61bb str r3, [r7, #24] } 800cb0a: bf00 nop 800cb0c: bf00 nop 800cb0e: e7fd b.n 800cb0c ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 800cb10: 68fb ldr r3, [r7, #12] 800cb12: 699a ldr r2, [r3, #24] 800cb14: 6a7b ldr r3, [r7, #36] @ 0x24 800cb16: 4413 add r3, r2 800cb18: 6a3a ldr r2, [r7, #32] 800cb1a: 68b9 ldr r1, [r7, #8] 800cb1c: 4618 mov r0, r3 800cb1e: f002 fc8c bl 800f43a /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 800cb22: 687a ldr r2, [r7, #4] 800cb24: 6a3b ldr r3, [r7, #32] 800cb26: 429a cmp r2, r3 800cb28: d91d bls.n 800cb66 { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 800cb2a: 687a ldr r2, [r7, #4] 800cb2c: 6a3b ldr r3, [r7, #32] 800cb2e: 1ad2 subs r2, r2, r3 800cb30: 68fb ldr r3, [r7, #12] 800cb32: 689b ldr r3, [r3, #8] 800cb34: 429a cmp r2, r3 800cb36: d90b bls.n 800cb50 __asm volatile 800cb38: f04f 0350 mov.w r3, #80 @ 0x50 800cb3c: f383 8811 msr BASEPRI, r3 800cb40: f3bf 8f6f isb sy 800cb44: f3bf 8f4f dsb sy 800cb48: 617b str r3, [r7, #20] } 800cb4a: bf00 nop 800cb4c: bf00 nop 800cb4e: e7fd b.n 800cb4c ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 800cb50: 68fb ldr r3, [r7, #12] 800cb52: 6998 ldr r0, [r3, #24] 800cb54: 68ba ldr r2, [r7, #8] 800cb56: 6a3b ldr r3, [r7, #32] 800cb58: 18d1 adds r1, r2, r3 800cb5a: 687a ldr r2, [r7, #4] 800cb5c: 6a3b ldr r3, [r7, #32] 800cb5e: 1ad3 subs r3, r2, r3 800cb60: 461a mov r2, r3 800cb62: f002 fc6a bl 800f43a else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 800cb66: 6a7a ldr r2, [r7, #36] @ 0x24 800cb68: 687b ldr r3, [r7, #4] 800cb6a: 4413 add r3, r2 800cb6c: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 800cb6e: 68fb ldr r3, [r7, #12] 800cb70: 689b ldr r3, [r3, #8] 800cb72: 6a7a ldr r2, [r7, #36] @ 0x24 800cb74: 429a cmp r2, r3 800cb76: d304 bcc.n 800cb82 { xNextHead -= pxStreamBuffer->xLength; 800cb78: 68fb ldr r3, [r7, #12] 800cb7a: 689b ldr r3, [r3, #8] 800cb7c: 6a7a ldr r2, [r7, #36] @ 0x24 800cb7e: 1ad3 subs r3, r2, r3 800cb80: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 800cb82: 68fb ldr r3, [r7, #12] 800cb84: 6a7a ldr r2, [r7, #36] @ 0x24 800cb86: 605a str r2, [r3, #4] return xCount; 800cb88: 687b ldr r3, [r7, #4] } 800cb8a: 4618 mov r0, r3 800cb8c: 3728 adds r7, #40 @ 0x28 800cb8e: 46bd mov sp, r7 800cb90: bd80 pop {r7, pc} 0800cb92 : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 800cb92: b480 push {r7} 800cb94: b085 sub sp, #20 800cb96: af00 add r7, sp, #0 800cb98: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 800cb9a: 687b ldr r3, [r7, #4] 800cb9c: 689a ldr r2, [r3, #8] 800cb9e: 687b ldr r3, [r7, #4] 800cba0: 685b ldr r3, [r3, #4] 800cba2: 4413 add r3, r2 800cba4: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 800cba6: 687b ldr r3, [r7, #4] 800cba8: 681b ldr r3, [r3, #0] 800cbaa: 68fa ldr r2, [r7, #12] 800cbac: 1ad3 subs r3, r2, r3 800cbae: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 800cbb0: 687b ldr r3, [r7, #4] 800cbb2: 689b ldr r3, [r3, #8] 800cbb4: 68fa ldr r2, [r7, #12] 800cbb6: 429a cmp r2, r3 800cbb8: d304 bcc.n 800cbc4 { xCount -= pxStreamBuffer->xLength; 800cbba: 687b ldr r3, [r7, #4] 800cbbc: 689b ldr r3, [r3, #8] 800cbbe: 68fa ldr r2, [r7, #12] 800cbc0: 1ad3 subs r3, r2, r3 800cbc2: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 800cbc4: 68fb ldr r3, [r7, #12] } 800cbc6: 4618 mov r0, r3 800cbc8: 3714 adds r7, #20 800cbca: 46bd mov sp, r7 800cbcc: f85d 7b04 ldr.w r7, [sp], #4 800cbd0: 4770 bx lr 0800cbd2 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 800cbd2: b580 push {r7, lr} 800cbd4: b08e sub sp, #56 @ 0x38 800cbd6: af04 add r7, sp, #16 800cbd8: 60f8 str r0, [r7, #12] 800cbda: 60b9 str r1, [r7, #8] 800cbdc: 607a str r2, [r7, #4] 800cbde: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 800cbe0: 6b7b ldr r3, [r7, #52] @ 0x34 800cbe2: 2b00 cmp r3, #0 800cbe4: d10b bne.n 800cbfe __asm volatile 800cbe6: f04f 0350 mov.w r3, #80 @ 0x50 800cbea: f383 8811 msr BASEPRI, r3 800cbee: f3bf 8f6f isb sy 800cbf2: f3bf 8f4f dsb sy 800cbf6: 623b str r3, [r7, #32] } 800cbf8: bf00 nop 800cbfa: bf00 nop 800cbfc: e7fd b.n 800cbfa configASSERT( pxTaskBuffer != NULL ); 800cbfe: 6bbb ldr r3, [r7, #56] @ 0x38 800cc00: 2b00 cmp r3, #0 800cc02: d10b bne.n 800cc1c __asm volatile 800cc04: f04f 0350 mov.w r3, #80 @ 0x50 800cc08: f383 8811 msr BASEPRI, r3 800cc0c: f3bf 8f6f isb sy 800cc10: f3bf 8f4f dsb sy 800cc14: 61fb str r3, [r7, #28] } 800cc16: bf00 nop 800cc18: bf00 nop 800cc1a: e7fd b.n 800cc18 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 800cc1c: 23a8 movs r3, #168 @ 0xa8 800cc1e: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 800cc20: 693b ldr r3, [r7, #16] 800cc22: 2ba8 cmp r3, #168 @ 0xa8 800cc24: d00b beq.n 800cc3e __asm volatile 800cc26: f04f 0350 mov.w r3, #80 @ 0x50 800cc2a: f383 8811 msr BASEPRI, r3 800cc2e: f3bf 8f6f isb sy 800cc32: f3bf 8f4f dsb sy 800cc36: 61bb str r3, [r7, #24] } 800cc38: bf00 nop 800cc3a: bf00 nop 800cc3c: e7fd b.n 800cc3a ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 800cc3e: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 800cc40: 6bbb ldr r3, [r7, #56] @ 0x38 800cc42: 2b00 cmp r3, #0 800cc44: d01e beq.n 800cc84 800cc46: 6b7b ldr r3, [r7, #52] @ 0x34 800cc48: 2b00 cmp r3, #0 800cc4a: d01b beq.n 800cc84 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 800cc4c: 6bbb ldr r3, [r7, #56] @ 0x38 800cc4e: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 800cc50: 6a7b ldr r3, [r7, #36] @ 0x24 800cc52: 6b7a ldr r2, [r7, #52] @ 0x34 800cc54: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 800cc56: 6a7b ldr r3, [r7, #36] @ 0x24 800cc58: 2202 movs r2, #2 800cc5a: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 800cc5e: 2300 movs r3, #0 800cc60: 9303 str r3, [sp, #12] 800cc62: 6a7b ldr r3, [r7, #36] @ 0x24 800cc64: 9302 str r3, [sp, #8] 800cc66: f107 0314 add.w r3, r7, #20 800cc6a: 9301 str r3, [sp, #4] 800cc6c: 6b3b ldr r3, [r7, #48] @ 0x30 800cc6e: 9300 str r3, [sp, #0] 800cc70: 683b ldr r3, [r7, #0] 800cc72: 687a ldr r2, [r7, #4] 800cc74: 68b9 ldr r1, [r7, #8] 800cc76: 68f8 ldr r0, [r7, #12] 800cc78: f000 f850 bl 800cd1c prvAddNewTaskToReadyList( pxNewTCB ); 800cc7c: 6a78 ldr r0, [r7, #36] @ 0x24 800cc7e: f000 f8f5 bl 800ce6c 800cc82: e001 b.n 800cc88 } else { xReturn = NULL; 800cc84: 2300 movs r3, #0 800cc86: 617b str r3, [r7, #20] } return xReturn; 800cc88: 697b ldr r3, [r7, #20] } 800cc8a: 4618 mov r0, r3 800cc8c: 3728 adds r7, #40 @ 0x28 800cc8e: 46bd mov sp, r7 800cc90: bd80 pop {r7, pc} 0800cc92 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 800cc92: b580 push {r7, lr} 800cc94: b08c sub sp, #48 @ 0x30 800cc96: af04 add r7, sp, #16 800cc98: 60f8 str r0, [r7, #12] 800cc9a: 60b9 str r1, [r7, #8] 800cc9c: 603b str r3, [r7, #0] 800cc9e: 4613 mov r3, r2 800cca0: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 800cca2: 88fb ldrh r3, [r7, #6] 800cca4: 009b lsls r3, r3, #2 800cca6: 4618 mov r0, r3 800cca8: f001 fff0 bl 800ec8c 800ccac: 6178 str r0, [r7, #20] if( pxStack != NULL ) 800ccae: 697b ldr r3, [r7, #20] 800ccb0: 2b00 cmp r3, #0 800ccb2: d00e beq.n 800ccd2 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 800ccb4: 20a8 movs r0, #168 @ 0xa8 800ccb6: f001 ffe9 bl 800ec8c 800ccba: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 800ccbc: 69fb ldr r3, [r7, #28] 800ccbe: 2b00 cmp r3, #0 800ccc0: d003 beq.n 800ccca { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 800ccc2: 69fb ldr r3, [r7, #28] 800ccc4: 697a ldr r2, [r7, #20] 800ccc6: 631a str r2, [r3, #48] @ 0x30 800ccc8: e005 b.n 800ccd6 } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 800ccca: 6978 ldr r0, [r7, #20] 800cccc: f002 f8ac bl 800ee28 800ccd0: e001 b.n 800ccd6 } } else { pxNewTCB = NULL; 800ccd2: 2300 movs r3, #0 800ccd4: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 800ccd6: 69fb ldr r3, [r7, #28] 800ccd8: 2b00 cmp r3, #0 800ccda: d017 beq.n 800cd0c { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 800ccdc: 69fb ldr r3, [r7, #28] 800ccde: 2200 movs r2, #0 800cce0: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 800cce4: 88fa ldrh r2, [r7, #6] 800cce6: 2300 movs r3, #0 800cce8: 9303 str r3, [sp, #12] 800ccea: 69fb ldr r3, [r7, #28] 800ccec: 9302 str r3, [sp, #8] 800ccee: 6afb ldr r3, [r7, #44] @ 0x2c 800ccf0: 9301 str r3, [sp, #4] 800ccf2: 6abb ldr r3, [r7, #40] @ 0x28 800ccf4: 9300 str r3, [sp, #0] 800ccf6: 683b ldr r3, [r7, #0] 800ccf8: 68b9 ldr r1, [r7, #8] 800ccfa: 68f8 ldr r0, [r7, #12] 800ccfc: f000 f80e bl 800cd1c prvAddNewTaskToReadyList( pxNewTCB ); 800cd00: 69f8 ldr r0, [r7, #28] 800cd02: f000 f8b3 bl 800ce6c xReturn = pdPASS; 800cd06: 2301 movs r3, #1 800cd08: 61bb str r3, [r7, #24] 800cd0a: e002 b.n 800cd12 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 800cd0c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800cd10: 61bb str r3, [r7, #24] } return xReturn; 800cd12: 69bb ldr r3, [r7, #24] } 800cd14: 4618 mov r0, r3 800cd16: 3720 adds r7, #32 800cd18: 46bd mov sp, r7 800cd1a: bd80 pop {r7, pc} 0800cd1c : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 800cd1c: b580 push {r7, lr} 800cd1e: b088 sub sp, #32 800cd20: af00 add r7, sp, #0 800cd22: 60f8 str r0, [r7, #12] 800cd24: 60b9 str r1, [r7, #8] 800cd26: 607a str r2, [r7, #4] 800cd28: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 800cd2a: 6b3b ldr r3, [r7, #48] @ 0x30 800cd2c: 6b18 ldr r0, [r3, #48] @ 0x30 800cd2e: 687b ldr r3, [r7, #4] 800cd30: 009b lsls r3, r3, #2 800cd32: 461a mov r2, r3 800cd34: 21a5 movs r1, #165 @ 0xa5 800cd36: f002 faae bl 800f296 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 800cd3a: 6b3b ldr r3, [r7, #48] @ 0x30 800cd3c: 6b1a ldr r2, [r3, #48] @ 0x30 800cd3e: 6879 ldr r1, [r7, #4] 800cd40: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 800cd44: 440b add r3, r1 800cd46: 009b lsls r3, r3, #2 800cd48: 4413 add r3, r2 800cd4a: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 800cd4c: 69bb ldr r3, [r7, #24] 800cd4e: f023 0307 bic.w r3, r3, #7 800cd52: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 800cd54: 69bb ldr r3, [r7, #24] 800cd56: f003 0307 and.w r3, r3, #7 800cd5a: 2b00 cmp r3, #0 800cd5c: d00b beq.n 800cd76 __asm volatile 800cd5e: f04f 0350 mov.w r3, #80 @ 0x50 800cd62: f383 8811 msr BASEPRI, r3 800cd66: f3bf 8f6f isb sy 800cd6a: f3bf 8f4f dsb sy 800cd6e: 617b str r3, [r7, #20] } 800cd70: bf00 nop 800cd72: bf00 nop 800cd74: e7fd b.n 800cd72 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 800cd76: 68bb ldr r3, [r7, #8] 800cd78: 2b00 cmp r3, #0 800cd7a: d01f beq.n 800cdbc { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 800cd7c: 2300 movs r3, #0 800cd7e: 61fb str r3, [r7, #28] 800cd80: e012 b.n 800cda8 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 800cd82: 68ba ldr r2, [r7, #8] 800cd84: 69fb ldr r3, [r7, #28] 800cd86: 4413 add r3, r2 800cd88: 7819 ldrb r1, [r3, #0] 800cd8a: 6b3a ldr r2, [r7, #48] @ 0x30 800cd8c: 69fb ldr r3, [r7, #28] 800cd8e: 4413 add r3, r2 800cd90: 3334 adds r3, #52 @ 0x34 800cd92: 460a mov r2, r1 800cd94: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 800cd96: 68ba ldr r2, [r7, #8] 800cd98: 69fb ldr r3, [r7, #28] 800cd9a: 4413 add r3, r2 800cd9c: 781b ldrb r3, [r3, #0] 800cd9e: 2b00 cmp r3, #0 800cda0: d006 beq.n 800cdb0 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 800cda2: 69fb ldr r3, [r7, #28] 800cda4: 3301 adds r3, #1 800cda6: 61fb str r3, [r7, #28] 800cda8: 69fb ldr r3, [r7, #28] 800cdaa: 2b0f cmp r3, #15 800cdac: d9e9 bls.n 800cd82 800cdae: e000 b.n 800cdb2 { break; 800cdb0: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 800cdb2: 6b3b ldr r3, [r7, #48] @ 0x30 800cdb4: 2200 movs r2, #0 800cdb6: f883 2043 strb.w r2, [r3, #67] @ 0x43 800cdba: e003 b.n 800cdc4 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 800cdbc: 6b3b ldr r3, [r7, #48] @ 0x30 800cdbe: 2200 movs r2, #0 800cdc0: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 800cdc4: 6abb ldr r3, [r7, #40] @ 0x28 800cdc6: 2b37 cmp r3, #55 @ 0x37 800cdc8: d901 bls.n 800cdce { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 800cdca: 2337 movs r3, #55 @ 0x37 800cdcc: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 800cdce: 6b3b ldr r3, [r7, #48] @ 0x30 800cdd0: 6aba ldr r2, [r7, #40] @ 0x28 800cdd2: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 800cdd4: 6b3b ldr r3, [r7, #48] @ 0x30 800cdd6: 6aba ldr r2, [r7, #40] @ 0x28 800cdd8: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 800cdda: 6b3b ldr r3, [r7, #48] @ 0x30 800cddc: 2200 movs r2, #0 800cdde: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 800cde0: 6b3b ldr r3, [r7, #48] @ 0x30 800cde2: 3304 adds r3, #4 800cde4: 4618 mov r0, r3 800cde6: f7fe fd8b bl 800b900 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 800cdea: 6b3b ldr r3, [r7, #48] @ 0x30 800cdec: 3318 adds r3, #24 800cdee: 4618 mov r0, r3 800cdf0: f7fe fd86 bl 800b900 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 800cdf4: 6b3b ldr r3, [r7, #48] @ 0x30 800cdf6: 6b3a ldr r2, [r7, #48] @ 0x30 800cdf8: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800cdfa: 6abb ldr r3, [r7, #40] @ 0x28 800cdfc: f1c3 0238 rsb r2, r3, #56 @ 0x38 800ce00: 6b3b ldr r3, [r7, #48] @ 0x30 800ce02: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 800ce04: 6b3b ldr r3, [r7, #48] @ 0x30 800ce06: 6b3a ldr r2, [r7, #48] @ 0x30 800ce08: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 800ce0a: 6b3b ldr r3, [r7, #48] @ 0x30 800ce0c: 2200 movs r2, #0 800ce0e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 800ce12: 6b3b ldr r3, [r7, #48] @ 0x30 800ce14: 2200 movs r2, #0 800ce16: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 800ce1a: 6b3b ldr r3, [r7, #48] @ 0x30 800ce1c: 3354 adds r3, #84 @ 0x54 800ce1e: 224c movs r2, #76 @ 0x4c 800ce20: 2100 movs r1, #0 800ce22: 4618 mov r0, r3 800ce24: f002 fa37 bl 800f296 800ce28: 6b3b ldr r3, [r7, #48] @ 0x30 800ce2a: 4a0d ldr r2, [pc, #52] @ (800ce60 ) 800ce2c: 659a str r2, [r3, #88] @ 0x58 800ce2e: 6b3b ldr r3, [r7, #48] @ 0x30 800ce30: 4a0c ldr r2, [pc, #48] @ (800ce64 ) 800ce32: 65da str r2, [r3, #92] @ 0x5c 800ce34: 6b3b ldr r3, [r7, #48] @ 0x30 800ce36: 4a0c ldr r2, [pc, #48] @ (800ce68 ) 800ce38: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 800ce3a: 683a ldr r2, [r7, #0] 800ce3c: 68f9 ldr r1, [r7, #12] 800ce3e: 69b8 ldr r0, [r7, #24] 800ce40: f001 fcce bl 800e7e0 800ce44: 4602 mov r2, r0 800ce46: 6b3b ldr r3, [r7, #48] @ 0x30 800ce48: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 800ce4a: 6afb ldr r3, [r7, #44] @ 0x2c 800ce4c: 2b00 cmp r3, #0 800ce4e: d002 beq.n 800ce56 { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 800ce50: 6afb ldr r3, [r7, #44] @ 0x2c 800ce52: 6b3a ldr r2, [r7, #48] @ 0x30 800ce54: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 800ce56: bf00 nop 800ce58: 3720 adds r7, #32 800ce5a: 46bd mov sp, r7 800ce5c: bd80 pop {r7, pc} 800ce5e: bf00 nop 800ce60: 2401277c .word 0x2401277c 800ce64: 240127e4 .word 0x240127e4 800ce68: 2401284c .word 0x2401284c 0800ce6c : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 800ce6c: b580 push {r7, lr} 800ce6e: b082 sub sp, #8 800ce70: af00 add r7, sp, #0 800ce72: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 800ce74: f001 fde8 bl 800ea48 { uxCurrentNumberOfTasks++; 800ce78: 4b2d ldr r3, [pc, #180] @ (800cf30 ) 800ce7a: 681b ldr r3, [r3, #0] 800ce7c: 3301 adds r3, #1 800ce7e: 4a2c ldr r2, [pc, #176] @ (800cf30 ) 800ce80: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 800ce82: 4b2c ldr r3, [pc, #176] @ (800cf34 ) 800ce84: 681b ldr r3, [r3, #0] 800ce86: 2b00 cmp r3, #0 800ce88: d109 bne.n 800ce9e { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 800ce8a: 4a2a ldr r2, [pc, #168] @ (800cf34 ) 800ce8c: 687b ldr r3, [r7, #4] 800ce8e: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 800ce90: 4b27 ldr r3, [pc, #156] @ (800cf30 ) 800ce92: 681b ldr r3, [r3, #0] 800ce94: 2b01 cmp r3, #1 800ce96: d110 bne.n 800ceba { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 800ce98: f000 fc64 bl 800d764 800ce9c: e00d b.n 800ceba else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 800ce9e: 4b26 ldr r3, [pc, #152] @ (800cf38 ) 800cea0: 681b ldr r3, [r3, #0] 800cea2: 2b00 cmp r3, #0 800cea4: d109 bne.n 800ceba { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 800cea6: 4b23 ldr r3, [pc, #140] @ (800cf34 ) 800cea8: 681b ldr r3, [r3, #0] 800ceaa: 6ada ldr r2, [r3, #44] @ 0x2c 800ceac: 687b ldr r3, [r7, #4] 800ceae: 6adb ldr r3, [r3, #44] @ 0x2c 800ceb0: 429a cmp r2, r3 800ceb2: d802 bhi.n 800ceba { pxCurrentTCB = pxNewTCB; 800ceb4: 4a1f ldr r2, [pc, #124] @ (800cf34 ) 800ceb6: 687b ldr r3, [r7, #4] 800ceb8: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 800ceba: 4b20 ldr r3, [pc, #128] @ (800cf3c ) 800cebc: 681b ldr r3, [r3, #0] 800cebe: 3301 adds r3, #1 800cec0: 4a1e ldr r2, [pc, #120] @ (800cf3c ) 800cec2: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 800cec4: 4b1d ldr r3, [pc, #116] @ (800cf3c ) 800cec6: 681a ldr r2, [r3, #0] 800cec8: 687b ldr r3, [r7, #4] 800ceca: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 800cecc: 687b ldr r3, [r7, #4] 800cece: 6ada ldr r2, [r3, #44] @ 0x2c 800ced0: 4b1b ldr r3, [pc, #108] @ (800cf40 ) 800ced2: 681b ldr r3, [r3, #0] 800ced4: 429a cmp r2, r3 800ced6: d903 bls.n 800cee0 800ced8: 687b ldr r3, [r7, #4] 800ceda: 6adb ldr r3, [r3, #44] @ 0x2c 800cedc: 4a18 ldr r2, [pc, #96] @ (800cf40 ) 800cede: 6013 str r3, [r2, #0] 800cee0: 687b ldr r3, [r7, #4] 800cee2: 6ada ldr r2, [r3, #44] @ 0x2c 800cee4: 4613 mov r3, r2 800cee6: 009b lsls r3, r3, #2 800cee8: 4413 add r3, r2 800ceea: 009b lsls r3, r3, #2 800ceec: 4a15 ldr r2, [pc, #84] @ (800cf44 ) 800ceee: 441a add r2, r3 800cef0: 687b ldr r3, [r7, #4] 800cef2: 3304 adds r3, #4 800cef4: 4619 mov r1, r3 800cef6: 4610 mov r0, r2 800cef8: f7fe fd0f bl 800b91a portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 800cefc: f001 fdd6 bl 800eaac if( xSchedulerRunning != pdFALSE ) 800cf00: 4b0d ldr r3, [pc, #52] @ (800cf38 ) 800cf02: 681b ldr r3, [r3, #0] 800cf04: 2b00 cmp r3, #0 800cf06: d00e beq.n 800cf26 { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 800cf08: 4b0a ldr r3, [pc, #40] @ (800cf34 ) 800cf0a: 681b ldr r3, [r3, #0] 800cf0c: 6ada ldr r2, [r3, #44] @ 0x2c 800cf0e: 687b ldr r3, [r7, #4] 800cf10: 6adb ldr r3, [r3, #44] @ 0x2c 800cf12: 429a cmp r2, r3 800cf14: d207 bcs.n 800cf26 { taskYIELD_IF_USING_PREEMPTION(); 800cf16: 4b0c ldr r3, [pc, #48] @ (800cf48 ) 800cf18: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800cf1c: 601a str r2, [r3, #0] 800cf1e: f3bf 8f4f dsb sy 800cf22: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 800cf26: bf00 nop 800cf28: 3708 adds r7, #8 800cf2a: 46bd mov sp, r7 800cf2c: bd80 pop {r7, pc} 800cf2e: bf00 nop 800cf30: 240025fc .word 0x240025fc 800cf34: 24002128 .word 0x24002128 800cf38: 24002608 .word 0x24002608 800cf3c: 24002618 .word 0x24002618 800cf40: 24002604 .word 0x24002604 800cf44: 2400212c .word 0x2400212c 800cf48: e000ed04 .word 0xe000ed04 0800cf4c : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 800cf4c: b580 push {r7, lr} 800cf4e: b084 sub sp, #16 800cf50: af00 add r7, sp, #0 800cf52: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 800cf54: 2300 movs r3, #0 800cf56: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 800cf58: 687b ldr r3, [r7, #4] 800cf5a: 2b00 cmp r3, #0 800cf5c: d018 beq.n 800cf90 { configASSERT( uxSchedulerSuspended == 0 ); 800cf5e: 4b14 ldr r3, [pc, #80] @ (800cfb0 ) 800cf60: 681b ldr r3, [r3, #0] 800cf62: 2b00 cmp r3, #0 800cf64: d00b beq.n 800cf7e __asm volatile 800cf66: f04f 0350 mov.w r3, #80 @ 0x50 800cf6a: f383 8811 msr BASEPRI, r3 800cf6e: f3bf 8f6f isb sy 800cf72: f3bf 8f4f dsb sy 800cf76: 60bb str r3, [r7, #8] } 800cf78: bf00 nop 800cf7a: bf00 nop 800cf7c: e7fd b.n 800cf7a vTaskSuspendAll(); 800cf7e: f000 f88b bl 800d098 list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 800cf82: 2100 movs r1, #0 800cf84: 6878 ldr r0, [r7, #4] 800cf86: f001 f87d bl 800e084 } xAlreadyYielded = xTaskResumeAll(); 800cf8a: f000 f893 bl 800d0b4 800cf8e: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 800cf90: 68fb ldr r3, [r7, #12] 800cf92: 2b00 cmp r3, #0 800cf94: d107 bne.n 800cfa6 { portYIELD_WITHIN_API(); 800cf96: 4b07 ldr r3, [pc, #28] @ (800cfb4 ) 800cf98: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800cf9c: 601a str r2, [r3, #0] 800cf9e: f3bf 8f4f dsb sy 800cfa2: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 800cfa6: bf00 nop 800cfa8: 3710 adds r7, #16 800cfaa: 46bd mov sp, r7 800cfac: bd80 pop {r7, pc} 800cfae: bf00 nop 800cfb0: 24002624 .word 0x24002624 800cfb4: e000ed04 .word 0xe000ed04 0800cfb8 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 800cfb8: b580 push {r7, lr} 800cfba: b08a sub sp, #40 @ 0x28 800cfbc: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 800cfbe: 2300 movs r3, #0 800cfc0: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 800cfc2: 2300 movs r3, #0 800cfc4: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 800cfc6: 463a mov r2, r7 800cfc8: 1d39 adds r1, r7, #4 800cfca: f107 0308 add.w r3, r7, #8 800cfce: 4618 mov r0, r3 800cfd0: f7fe fc42 bl 800b858 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 800cfd4: 6839 ldr r1, [r7, #0] 800cfd6: 687b ldr r3, [r7, #4] 800cfd8: 68ba ldr r2, [r7, #8] 800cfda: 9202 str r2, [sp, #8] 800cfdc: 9301 str r3, [sp, #4] 800cfde: 2300 movs r3, #0 800cfe0: 9300 str r3, [sp, #0] 800cfe2: 2300 movs r3, #0 800cfe4: 460a mov r2, r1 800cfe6: 4924 ldr r1, [pc, #144] @ (800d078 ) 800cfe8: 4824 ldr r0, [pc, #144] @ (800d07c ) 800cfea: f7ff fdf2 bl 800cbd2 800cfee: 4603 mov r3, r0 800cff0: 4a23 ldr r2, [pc, #140] @ (800d080 ) 800cff2: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 800cff4: 4b22 ldr r3, [pc, #136] @ (800d080 ) 800cff6: 681b ldr r3, [r3, #0] 800cff8: 2b00 cmp r3, #0 800cffa: d002 beq.n 800d002 { xReturn = pdPASS; 800cffc: 2301 movs r3, #1 800cffe: 617b str r3, [r7, #20] 800d000: e001 b.n 800d006 } else { xReturn = pdFAIL; 800d002: 2300 movs r3, #0 800d004: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 800d006: 697b ldr r3, [r7, #20] 800d008: 2b01 cmp r3, #1 800d00a: d102 bne.n 800d012 { xReturn = xTimerCreateTimerTask(); 800d00c: f001 f88e bl 800e12c 800d010: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 800d012: 697b ldr r3, [r7, #20] 800d014: 2b01 cmp r3, #1 800d016: d11b bne.n 800d050 __asm volatile 800d018: f04f 0350 mov.w r3, #80 @ 0x50 800d01c: f383 8811 msr BASEPRI, r3 800d020: f3bf 8f6f isb sy 800d024: f3bf 8f4f dsb sy 800d028: 613b str r3, [r7, #16] } 800d02a: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 800d02c: 4b15 ldr r3, [pc, #84] @ (800d084 ) 800d02e: 681b ldr r3, [r3, #0] 800d030: 3354 adds r3, #84 @ 0x54 800d032: 4a15 ldr r2, [pc, #84] @ (800d088 ) 800d034: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 800d036: 4b15 ldr r3, [pc, #84] @ (800d08c ) 800d038: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800d03c: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 800d03e: 4b14 ldr r3, [pc, #80] @ (800d090 ) 800d040: 2201 movs r2, #1 800d042: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 800d044: 4b13 ldr r3, [pc, #76] @ (800d094 ) 800d046: 2200 movs r2, #0 800d048: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 800d04a: f001 fc59 bl 800e900 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 800d04e: e00f b.n 800d070 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 800d050: 697b ldr r3, [r7, #20] 800d052: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d056: d10b bne.n 800d070 __asm volatile 800d058: f04f 0350 mov.w r3, #80 @ 0x50 800d05c: f383 8811 msr BASEPRI, r3 800d060: f3bf 8f6f isb sy 800d064: f3bf 8f4f dsb sy 800d068: 60fb str r3, [r7, #12] } 800d06a: bf00 nop 800d06c: bf00 nop 800d06e: e7fd b.n 800d06c } 800d070: bf00 nop 800d072: 3718 adds r7, #24 800d074: 46bd mov sp, r7 800d076: bd80 pop {r7, pc} 800d078: 08010074 .word 0x08010074 800d07c: 0800d735 .word 0x0800d735 800d080: 24002620 .word 0x24002620 800d084: 24002128 .word 0x24002128 800d088: 24000020 .word 0x24000020 800d08c: 2400261c .word 0x2400261c 800d090: 24002608 .word 0x24002608 800d094: 24002600 .word 0x24002600 0800d098 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 800d098: b480 push {r7} 800d09a: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 800d09c: 4b04 ldr r3, [pc, #16] @ (800d0b0 ) 800d09e: 681b ldr r3, [r3, #0] 800d0a0: 3301 adds r3, #1 800d0a2: 4a03 ldr r2, [pc, #12] @ (800d0b0 ) 800d0a4: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 800d0a6: bf00 nop 800d0a8: 46bd mov sp, r7 800d0aa: f85d 7b04 ldr.w r7, [sp], #4 800d0ae: 4770 bx lr 800d0b0: 24002624 .word 0x24002624 0800d0b4 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 800d0b4: b580 push {r7, lr} 800d0b6: b084 sub sp, #16 800d0b8: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 800d0ba: 2300 movs r3, #0 800d0bc: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 800d0be: 2300 movs r3, #0 800d0c0: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 800d0c2: 4b42 ldr r3, [pc, #264] @ (800d1cc ) 800d0c4: 681b ldr r3, [r3, #0] 800d0c6: 2b00 cmp r3, #0 800d0c8: d10b bne.n 800d0e2 __asm volatile 800d0ca: f04f 0350 mov.w r3, #80 @ 0x50 800d0ce: f383 8811 msr BASEPRI, r3 800d0d2: f3bf 8f6f isb sy 800d0d6: f3bf 8f4f dsb sy 800d0da: 603b str r3, [r7, #0] } 800d0dc: bf00 nop 800d0de: bf00 nop 800d0e0: e7fd b.n 800d0de /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 800d0e2: f001 fcb1 bl 800ea48 { --uxSchedulerSuspended; 800d0e6: 4b39 ldr r3, [pc, #228] @ (800d1cc ) 800d0e8: 681b ldr r3, [r3, #0] 800d0ea: 3b01 subs r3, #1 800d0ec: 4a37 ldr r2, [pc, #220] @ (800d1cc ) 800d0ee: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800d0f0: 4b36 ldr r3, [pc, #216] @ (800d1cc ) 800d0f2: 681b ldr r3, [r3, #0] 800d0f4: 2b00 cmp r3, #0 800d0f6: d162 bne.n 800d1be { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 800d0f8: 4b35 ldr r3, [pc, #212] @ (800d1d0 ) 800d0fa: 681b ldr r3, [r3, #0] 800d0fc: 2b00 cmp r3, #0 800d0fe: d05e beq.n 800d1be { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 800d100: e02f b.n 800d162 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d102: 4b34 ldr r3, [pc, #208] @ (800d1d4 ) 800d104: 68db ldr r3, [r3, #12] 800d106: 68db ldr r3, [r3, #12] 800d108: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 800d10a: 68fb ldr r3, [r7, #12] 800d10c: 3318 adds r3, #24 800d10e: 4618 mov r0, r3 800d110: f7fe fc60 bl 800b9d4 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d114: 68fb ldr r3, [r7, #12] 800d116: 3304 adds r3, #4 800d118: 4618 mov r0, r3 800d11a: f7fe fc5b bl 800b9d4 prvAddTaskToReadyList( pxTCB ); 800d11e: 68fb ldr r3, [r7, #12] 800d120: 6ada ldr r2, [r3, #44] @ 0x2c 800d122: 4b2d ldr r3, [pc, #180] @ (800d1d8 ) 800d124: 681b ldr r3, [r3, #0] 800d126: 429a cmp r2, r3 800d128: d903 bls.n 800d132 800d12a: 68fb ldr r3, [r7, #12] 800d12c: 6adb ldr r3, [r3, #44] @ 0x2c 800d12e: 4a2a ldr r2, [pc, #168] @ (800d1d8 ) 800d130: 6013 str r3, [r2, #0] 800d132: 68fb ldr r3, [r7, #12] 800d134: 6ada ldr r2, [r3, #44] @ 0x2c 800d136: 4613 mov r3, r2 800d138: 009b lsls r3, r3, #2 800d13a: 4413 add r3, r2 800d13c: 009b lsls r3, r3, #2 800d13e: 4a27 ldr r2, [pc, #156] @ (800d1dc ) 800d140: 441a add r2, r3 800d142: 68fb ldr r3, [r7, #12] 800d144: 3304 adds r3, #4 800d146: 4619 mov r1, r3 800d148: 4610 mov r0, r2 800d14a: f7fe fbe6 bl 800b91a /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 800d14e: 68fb ldr r3, [r7, #12] 800d150: 6ada ldr r2, [r3, #44] @ 0x2c 800d152: 4b23 ldr r3, [pc, #140] @ (800d1e0 ) 800d154: 681b ldr r3, [r3, #0] 800d156: 6adb ldr r3, [r3, #44] @ 0x2c 800d158: 429a cmp r2, r3 800d15a: d302 bcc.n 800d162 { xYieldPending = pdTRUE; 800d15c: 4b21 ldr r3, [pc, #132] @ (800d1e4 ) 800d15e: 2201 movs r2, #1 800d160: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 800d162: 4b1c ldr r3, [pc, #112] @ (800d1d4 ) 800d164: 681b ldr r3, [r3, #0] 800d166: 2b00 cmp r3, #0 800d168: d1cb bne.n 800d102 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 800d16a: 68fb ldr r3, [r7, #12] 800d16c: 2b00 cmp r3, #0 800d16e: d001 beq.n 800d174 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 800d170: f000 fb9c bl 800d8ac /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 800d174: 4b1c ldr r3, [pc, #112] @ (800d1e8 ) 800d176: 681b ldr r3, [r3, #0] 800d178: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 800d17a: 687b ldr r3, [r7, #4] 800d17c: 2b00 cmp r3, #0 800d17e: d010 beq.n 800d1a2 { do { if( xTaskIncrementTick() != pdFALSE ) 800d180: f000 f846 bl 800d210 800d184: 4603 mov r3, r0 800d186: 2b00 cmp r3, #0 800d188: d002 beq.n 800d190 { xYieldPending = pdTRUE; 800d18a: 4b16 ldr r3, [pc, #88] @ (800d1e4 ) 800d18c: 2201 movs r2, #1 800d18e: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 800d190: 687b ldr r3, [r7, #4] 800d192: 3b01 subs r3, #1 800d194: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 800d196: 687b ldr r3, [r7, #4] 800d198: 2b00 cmp r3, #0 800d19a: d1f1 bne.n 800d180 xPendedTicks = 0; 800d19c: 4b12 ldr r3, [pc, #72] @ (800d1e8 ) 800d19e: 2200 movs r2, #0 800d1a0: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 800d1a2: 4b10 ldr r3, [pc, #64] @ (800d1e4 ) 800d1a4: 681b ldr r3, [r3, #0] 800d1a6: 2b00 cmp r3, #0 800d1a8: d009 beq.n 800d1be { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 800d1aa: 2301 movs r3, #1 800d1ac: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 800d1ae: 4b0f ldr r3, [pc, #60] @ (800d1ec ) 800d1b0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800d1b4: 601a str r2, [r3, #0] 800d1b6: f3bf 8f4f dsb sy 800d1ba: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 800d1be: f001 fc75 bl 800eaac return xAlreadyYielded; 800d1c2: 68bb ldr r3, [r7, #8] } 800d1c4: 4618 mov r0, r3 800d1c6: 3710 adds r7, #16 800d1c8: 46bd mov sp, r7 800d1ca: bd80 pop {r7, pc} 800d1cc: 24002624 .word 0x24002624 800d1d0: 240025fc .word 0x240025fc 800d1d4: 240025bc .word 0x240025bc 800d1d8: 24002604 .word 0x24002604 800d1dc: 2400212c .word 0x2400212c 800d1e0: 24002128 .word 0x24002128 800d1e4: 24002610 .word 0x24002610 800d1e8: 2400260c .word 0x2400260c 800d1ec: e000ed04 .word 0xe000ed04 0800d1f0 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 800d1f0: b480 push {r7} 800d1f2: b083 sub sp, #12 800d1f4: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 800d1f6: 4b05 ldr r3, [pc, #20] @ (800d20c ) 800d1f8: 681b ldr r3, [r3, #0] 800d1fa: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 800d1fc: 687b ldr r3, [r7, #4] } 800d1fe: 4618 mov r0, r3 800d200: 370c adds r7, #12 800d202: 46bd mov sp, r7 800d204: f85d 7b04 ldr.w r7, [sp], #4 800d208: 4770 bx lr 800d20a: bf00 nop 800d20c: 24002600 .word 0x24002600 0800d210 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 800d210: b580 push {r7, lr} 800d212: b086 sub sp, #24 800d214: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 800d216: 2300 movs r3, #0 800d218: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800d21a: 4b4f ldr r3, [pc, #316] @ (800d358 ) 800d21c: 681b ldr r3, [r3, #0] 800d21e: 2b00 cmp r3, #0 800d220: f040 8090 bne.w 800d344 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 800d224: 4b4d ldr r3, [pc, #308] @ (800d35c ) 800d226: 681b ldr r3, [r3, #0] 800d228: 3301 adds r3, #1 800d22a: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 800d22c: 4a4b ldr r2, [pc, #300] @ (800d35c ) 800d22e: 693b ldr r3, [r7, #16] 800d230: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 800d232: 693b ldr r3, [r7, #16] 800d234: 2b00 cmp r3, #0 800d236: d121 bne.n 800d27c { taskSWITCH_DELAYED_LISTS(); 800d238: 4b49 ldr r3, [pc, #292] @ (800d360 ) 800d23a: 681b ldr r3, [r3, #0] 800d23c: 681b ldr r3, [r3, #0] 800d23e: 2b00 cmp r3, #0 800d240: d00b beq.n 800d25a __asm volatile 800d242: f04f 0350 mov.w r3, #80 @ 0x50 800d246: f383 8811 msr BASEPRI, r3 800d24a: f3bf 8f6f isb sy 800d24e: f3bf 8f4f dsb sy 800d252: 603b str r3, [r7, #0] } 800d254: bf00 nop 800d256: bf00 nop 800d258: e7fd b.n 800d256 800d25a: 4b41 ldr r3, [pc, #260] @ (800d360 ) 800d25c: 681b ldr r3, [r3, #0] 800d25e: 60fb str r3, [r7, #12] 800d260: 4b40 ldr r3, [pc, #256] @ (800d364 ) 800d262: 681b ldr r3, [r3, #0] 800d264: 4a3e ldr r2, [pc, #248] @ (800d360 ) 800d266: 6013 str r3, [r2, #0] 800d268: 4a3e ldr r2, [pc, #248] @ (800d364 ) 800d26a: 68fb ldr r3, [r7, #12] 800d26c: 6013 str r3, [r2, #0] 800d26e: 4b3e ldr r3, [pc, #248] @ (800d368 ) 800d270: 681b ldr r3, [r3, #0] 800d272: 3301 adds r3, #1 800d274: 4a3c ldr r2, [pc, #240] @ (800d368 ) 800d276: 6013 str r3, [r2, #0] 800d278: f000 fb18 bl 800d8ac /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 800d27c: 4b3b ldr r3, [pc, #236] @ (800d36c ) 800d27e: 681b ldr r3, [r3, #0] 800d280: 693a ldr r2, [r7, #16] 800d282: 429a cmp r2, r3 800d284: d349 bcc.n 800d31a { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d286: 4b36 ldr r3, [pc, #216] @ (800d360 ) 800d288: 681b ldr r3, [r3, #0] 800d28a: 681b ldr r3, [r3, #0] 800d28c: 2b00 cmp r3, #0 800d28e: d104 bne.n 800d29a /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800d290: 4b36 ldr r3, [pc, #216] @ (800d36c ) 800d292: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800d296: 601a str r2, [r3, #0] break; 800d298: e03f b.n 800d31a { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d29a: 4b31 ldr r3, [pc, #196] @ (800d360 ) 800d29c: 681b ldr r3, [r3, #0] 800d29e: 68db ldr r3, [r3, #12] 800d2a0: 68db ldr r3, [r3, #12] 800d2a2: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 800d2a4: 68bb ldr r3, [r7, #8] 800d2a6: 685b ldr r3, [r3, #4] 800d2a8: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 800d2aa: 693a ldr r2, [r7, #16] 800d2ac: 687b ldr r3, [r7, #4] 800d2ae: 429a cmp r2, r3 800d2b0: d203 bcs.n 800d2ba /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 800d2b2: 4a2e ldr r2, [pc, #184] @ (800d36c ) 800d2b4: 687b ldr r3, [r7, #4] 800d2b6: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 800d2b8: e02f b.n 800d31a { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d2ba: 68bb ldr r3, [r7, #8] 800d2bc: 3304 adds r3, #4 800d2be: 4618 mov r0, r3 800d2c0: f7fe fb88 bl 800b9d4 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 800d2c4: 68bb ldr r3, [r7, #8] 800d2c6: 6a9b ldr r3, [r3, #40] @ 0x28 800d2c8: 2b00 cmp r3, #0 800d2ca: d004 beq.n 800d2d6 { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 800d2cc: 68bb ldr r3, [r7, #8] 800d2ce: 3318 adds r3, #24 800d2d0: 4618 mov r0, r3 800d2d2: f7fe fb7f bl 800b9d4 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 800d2d6: 68bb ldr r3, [r7, #8] 800d2d8: 6ada ldr r2, [r3, #44] @ 0x2c 800d2da: 4b25 ldr r3, [pc, #148] @ (800d370 ) 800d2dc: 681b ldr r3, [r3, #0] 800d2de: 429a cmp r2, r3 800d2e0: d903 bls.n 800d2ea 800d2e2: 68bb ldr r3, [r7, #8] 800d2e4: 6adb ldr r3, [r3, #44] @ 0x2c 800d2e6: 4a22 ldr r2, [pc, #136] @ (800d370 ) 800d2e8: 6013 str r3, [r2, #0] 800d2ea: 68bb ldr r3, [r7, #8] 800d2ec: 6ada ldr r2, [r3, #44] @ 0x2c 800d2ee: 4613 mov r3, r2 800d2f0: 009b lsls r3, r3, #2 800d2f2: 4413 add r3, r2 800d2f4: 009b lsls r3, r3, #2 800d2f6: 4a1f ldr r2, [pc, #124] @ (800d374 ) 800d2f8: 441a add r2, r3 800d2fa: 68bb ldr r3, [r7, #8] 800d2fc: 3304 adds r3, #4 800d2fe: 4619 mov r1, r3 800d300: 4610 mov r0, r2 800d302: f7fe fb0a bl 800b91a { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 800d306: 68bb ldr r3, [r7, #8] 800d308: 6ada ldr r2, [r3, #44] @ 0x2c 800d30a: 4b1b ldr r3, [pc, #108] @ (800d378 ) 800d30c: 681b ldr r3, [r3, #0] 800d30e: 6adb ldr r3, [r3, #44] @ 0x2c 800d310: 429a cmp r2, r3 800d312: d3b8 bcc.n 800d286 { xSwitchRequired = pdTRUE; 800d314: 2301 movs r3, #1 800d316: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d318: e7b5 b.n 800d286 /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 800d31a: 4b17 ldr r3, [pc, #92] @ (800d378 ) 800d31c: 681b ldr r3, [r3, #0] 800d31e: 6ada ldr r2, [r3, #44] @ 0x2c 800d320: 4914 ldr r1, [pc, #80] @ (800d374 ) 800d322: 4613 mov r3, r2 800d324: 009b lsls r3, r3, #2 800d326: 4413 add r3, r2 800d328: 009b lsls r3, r3, #2 800d32a: 440b add r3, r1 800d32c: 681b ldr r3, [r3, #0] 800d32e: 2b01 cmp r3, #1 800d330: d901 bls.n 800d336 { xSwitchRequired = pdTRUE; 800d332: 2301 movs r3, #1 800d334: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 800d336: 4b11 ldr r3, [pc, #68] @ (800d37c ) 800d338: 681b ldr r3, [r3, #0] 800d33a: 2b00 cmp r3, #0 800d33c: d007 beq.n 800d34e { xSwitchRequired = pdTRUE; 800d33e: 2301 movs r3, #1 800d340: 617b str r3, [r7, #20] 800d342: e004 b.n 800d34e } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 800d344: 4b0e ldr r3, [pc, #56] @ (800d380 ) 800d346: 681b ldr r3, [r3, #0] 800d348: 3301 adds r3, #1 800d34a: 4a0d ldr r2, [pc, #52] @ (800d380 ) 800d34c: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 800d34e: 697b ldr r3, [r7, #20] } 800d350: 4618 mov r0, r3 800d352: 3718 adds r7, #24 800d354: 46bd mov sp, r7 800d356: bd80 pop {r7, pc} 800d358: 24002624 .word 0x24002624 800d35c: 24002600 .word 0x24002600 800d360: 240025b4 .word 0x240025b4 800d364: 240025b8 .word 0x240025b8 800d368: 24002614 .word 0x24002614 800d36c: 2400261c .word 0x2400261c 800d370: 24002604 .word 0x24002604 800d374: 2400212c .word 0x2400212c 800d378: 24002128 .word 0x24002128 800d37c: 24002610 .word 0x24002610 800d380: 2400260c .word 0x2400260c 0800d384 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 800d384: b580 push {r7, lr} 800d386: b084 sub sp, #16 800d388: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 800d38a: 4b32 ldr r3, [pc, #200] @ (800d454 ) 800d38c: 681b ldr r3, [r3, #0] 800d38e: 2b00 cmp r3, #0 800d390: d003 beq.n 800d39a { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 800d392: 4b31 ldr r3, [pc, #196] @ (800d458 ) 800d394: 2201 movs r2, #1 800d396: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 800d398: e058 b.n 800d44c xYieldPending = pdFALSE; 800d39a: 4b2f ldr r3, [pc, #188] @ (800d458 ) 800d39c: 2200 movs r2, #0 800d39e: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 800d3a0: 4b2e ldr r3, [pc, #184] @ (800d45c ) 800d3a2: 681b ldr r3, [r3, #0] 800d3a4: 681a ldr r2, [r3, #0] 800d3a6: 4b2d ldr r3, [pc, #180] @ (800d45c ) 800d3a8: 681b ldr r3, [r3, #0] 800d3aa: 6b1b ldr r3, [r3, #48] @ 0x30 800d3ac: 429a cmp r2, r3 800d3ae: d808 bhi.n 800d3c2 800d3b0: 4b2a ldr r3, [pc, #168] @ (800d45c ) 800d3b2: 681a ldr r2, [r3, #0] 800d3b4: 4b29 ldr r3, [pc, #164] @ (800d45c ) 800d3b6: 681b ldr r3, [r3, #0] 800d3b8: 3334 adds r3, #52 @ 0x34 800d3ba: 4619 mov r1, r3 800d3bc: 4610 mov r0, r2 800d3be: f7f3 f957 bl 8000670 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d3c2: 4b27 ldr r3, [pc, #156] @ (800d460 ) 800d3c4: 681b ldr r3, [r3, #0] 800d3c6: 60fb str r3, [r7, #12] 800d3c8: e011 b.n 800d3ee 800d3ca: 68fb ldr r3, [r7, #12] 800d3cc: 2b00 cmp r3, #0 800d3ce: d10b bne.n 800d3e8 __asm volatile 800d3d0: f04f 0350 mov.w r3, #80 @ 0x50 800d3d4: f383 8811 msr BASEPRI, r3 800d3d8: f3bf 8f6f isb sy 800d3dc: f3bf 8f4f dsb sy 800d3e0: 607b str r3, [r7, #4] } 800d3e2: bf00 nop 800d3e4: bf00 nop 800d3e6: e7fd b.n 800d3e4 800d3e8: 68fb ldr r3, [r7, #12] 800d3ea: 3b01 subs r3, #1 800d3ec: 60fb str r3, [r7, #12] 800d3ee: 491d ldr r1, [pc, #116] @ (800d464 ) 800d3f0: 68fa ldr r2, [r7, #12] 800d3f2: 4613 mov r3, r2 800d3f4: 009b lsls r3, r3, #2 800d3f6: 4413 add r3, r2 800d3f8: 009b lsls r3, r3, #2 800d3fa: 440b add r3, r1 800d3fc: 681b ldr r3, [r3, #0] 800d3fe: 2b00 cmp r3, #0 800d400: d0e3 beq.n 800d3ca 800d402: 68fa ldr r2, [r7, #12] 800d404: 4613 mov r3, r2 800d406: 009b lsls r3, r3, #2 800d408: 4413 add r3, r2 800d40a: 009b lsls r3, r3, #2 800d40c: 4a15 ldr r2, [pc, #84] @ (800d464 ) 800d40e: 4413 add r3, r2 800d410: 60bb str r3, [r7, #8] 800d412: 68bb ldr r3, [r7, #8] 800d414: 685b ldr r3, [r3, #4] 800d416: 685a ldr r2, [r3, #4] 800d418: 68bb ldr r3, [r7, #8] 800d41a: 605a str r2, [r3, #4] 800d41c: 68bb ldr r3, [r7, #8] 800d41e: 685a ldr r2, [r3, #4] 800d420: 68bb ldr r3, [r7, #8] 800d422: 3308 adds r3, #8 800d424: 429a cmp r2, r3 800d426: d104 bne.n 800d432 800d428: 68bb ldr r3, [r7, #8] 800d42a: 685b ldr r3, [r3, #4] 800d42c: 685a ldr r2, [r3, #4] 800d42e: 68bb ldr r3, [r7, #8] 800d430: 605a str r2, [r3, #4] 800d432: 68bb ldr r3, [r7, #8] 800d434: 685b ldr r3, [r3, #4] 800d436: 68db ldr r3, [r3, #12] 800d438: 4a08 ldr r2, [pc, #32] @ (800d45c ) 800d43a: 6013 str r3, [r2, #0] 800d43c: 4a08 ldr r2, [pc, #32] @ (800d460 ) 800d43e: 68fb ldr r3, [r7, #12] 800d440: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 800d442: 4b06 ldr r3, [pc, #24] @ (800d45c ) 800d444: 681b ldr r3, [r3, #0] 800d446: 3354 adds r3, #84 @ 0x54 800d448: 4a07 ldr r2, [pc, #28] @ (800d468 ) 800d44a: 6013 str r3, [r2, #0] } 800d44c: bf00 nop 800d44e: 3710 adds r7, #16 800d450: 46bd mov sp, r7 800d452: bd80 pop {r7, pc} 800d454: 24002624 .word 0x24002624 800d458: 24002610 .word 0x24002610 800d45c: 24002128 .word 0x24002128 800d460: 24002604 .word 0x24002604 800d464: 2400212c .word 0x2400212c 800d468: 24000020 .word 0x24000020 0800d46c : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 800d46c: b580 push {r7, lr} 800d46e: b084 sub sp, #16 800d470: af00 add r7, sp, #0 800d472: 6078 str r0, [r7, #4] 800d474: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 800d476: 687b ldr r3, [r7, #4] 800d478: 2b00 cmp r3, #0 800d47a: d10b bne.n 800d494 __asm volatile 800d47c: f04f 0350 mov.w r3, #80 @ 0x50 800d480: f383 8811 msr BASEPRI, r3 800d484: f3bf 8f6f isb sy 800d488: f3bf 8f4f dsb sy 800d48c: 60fb str r3, [r7, #12] } 800d48e: bf00 nop 800d490: bf00 nop 800d492: e7fd b.n 800d490 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 800d494: 4b07 ldr r3, [pc, #28] @ (800d4b4 ) 800d496: 681b ldr r3, [r3, #0] 800d498: 3318 adds r3, #24 800d49a: 4619 mov r1, r3 800d49c: 6878 ldr r0, [r7, #4] 800d49e: f7fe fa60 bl 800b962 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 800d4a2: 2101 movs r1, #1 800d4a4: 6838 ldr r0, [r7, #0] 800d4a6: f000 fded bl 800e084 } 800d4aa: bf00 nop 800d4ac: 3710 adds r7, #16 800d4ae: 46bd mov sp, r7 800d4b0: bd80 pop {r7, pc} 800d4b2: bf00 nop 800d4b4: 24002128 .word 0x24002128 0800d4b8 : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 800d4b8: b580 push {r7, lr} 800d4ba: b086 sub sp, #24 800d4bc: af00 add r7, sp, #0 800d4be: 60f8 str r0, [r7, #12] 800d4c0: 60b9 str r1, [r7, #8] 800d4c2: 607a str r2, [r7, #4] configASSERT( pxEventList ); 800d4c4: 68fb ldr r3, [r7, #12] 800d4c6: 2b00 cmp r3, #0 800d4c8: d10b bne.n 800d4e2 __asm volatile 800d4ca: f04f 0350 mov.w r3, #80 @ 0x50 800d4ce: f383 8811 msr BASEPRI, r3 800d4d2: f3bf 8f6f isb sy 800d4d6: f3bf 8f4f dsb sy 800d4da: 617b str r3, [r7, #20] } 800d4dc: bf00 nop 800d4de: bf00 nop 800d4e0: e7fd b.n 800d4de /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 800d4e2: 4b0a ldr r3, [pc, #40] @ (800d50c ) 800d4e4: 681b ldr r3, [r3, #0] 800d4e6: 3318 adds r3, #24 800d4e8: 4619 mov r1, r3 800d4ea: 68f8 ldr r0, [r7, #12] 800d4ec: f7fe fa15 bl 800b91a /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 800d4f0: 687b ldr r3, [r7, #4] 800d4f2: 2b00 cmp r3, #0 800d4f4: d002 beq.n 800d4fc { xTicksToWait = portMAX_DELAY; 800d4f6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800d4fa: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 800d4fc: 6879 ldr r1, [r7, #4] 800d4fe: 68b8 ldr r0, [r7, #8] 800d500: f000 fdc0 bl 800e084 } 800d504: bf00 nop 800d506: 3718 adds r7, #24 800d508: 46bd mov sp, r7 800d50a: bd80 pop {r7, pc} 800d50c: 24002128 .word 0x24002128 0800d510 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 800d510: b580 push {r7, lr} 800d512: b086 sub sp, #24 800d514: af00 add r7, sp, #0 800d516: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d518: 687b ldr r3, [r7, #4] 800d51a: 68db ldr r3, [r3, #12] 800d51c: 68db ldr r3, [r3, #12] 800d51e: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 800d520: 693b ldr r3, [r7, #16] 800d522: 2b00 cmp r3, #0 800d524: d10b bne.n 800d53e __asm volatile 800d526: f04f 0350 mov.w r3, #80 @ 0x50 800d52a: f383 8811 msr BASEPRI, r3 800d52e: f3bf 8f6f isb sy 800d532: f3bf 8f4f dsb sy 800d536: 60fb str r3, [r7, #12] } 800d538: bf00 nop 800d53a: bf00 nop 800d53c: e7fd b.n 800d53a ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 800d53e: 693b ldr r3, [r7, #16] 800d540: 3318 adds r3, #24 800d542: 4618 mov r0, r3 800d544: f7fe fa46 bl 800b9d4 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800d548: 4b1d ldr r3, [pc, #116] @ (800d5c0 ) 800d54a: 681b ldr r3, [r3, #0] 800d54c: 2b00 cmp r3, #0 800d54e: d11d bne.n 800d58c { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 800d550: 693b ldr r3, [r7, #16] 800d552: 3304 adds r3, #4 800d554: 4618 mov r0, r3 800d556: f7fe fa3d bl 800b9d4 prvAddTaskToReadyList( pxUnblockedTCB ); 800d55a: 693b ldr r3, [r7, #16] 800d55c: 6ada ldr r2, [r3, #44] @ 0x2c 800d55e: 4b19 ldr r3, [pc, #100] @ (800d5c4 ) 800d560: 681b ldr r3, [r3, #0] 800d562: 429a cmp r2, r3 800d564: d903 bls.n 800d56e 800d566: 693b ldr r3, [r7, #16] 800d568: 6adb ldr r3, [r3, #44] @ 0x2c 800d56a: 4a16 ldr r2, [pc, #88] @ (800d5c4 ) 800d56c: 6013 str r3, [r2, #0] 800d56e: 693b ldr r3, [r7, #16] 800d570: 6ada ldr r2, [r3, #44] @ 0x2c 800d572: 4613 mov r3, r2 800d574: 009b lsls r3, r3, #2 800d576: 4413 add r3, r2 800d578: 009b lsls r3, r3, #2 800d57a: 4a13 ldr r2, [pc, #76] @ (800d5c8 ) 800d57c: 441a add r2, r3 800d57e: 693b ldr r3, [r7, #16] 800d580: 3304 adds r3, #4 800d582: 4619 mov r1, r3 800d584: 4610 mov r0, r2 800d586: f7fe f9c8 bl 800b91a 800d58a: e005 b.n 800d598 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 800d58c: 693b ldr r3, [r7, #16] 800d58e: 3318 adds r3, #24 800d590: 4619 mov r1, r3 800d592: 480e ldr r0, [pc, #56] @ (800d5cc ) 800d594: f7fe f9c1 bl 800b91a } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 800d598: 693b ldr r3, [r7, #16] 800d59a: 6ada ldr r2, [r3, #44] @ 0x2c 800d59c: 4b0c ldr r3, [pc, #48] @ (800d5d0 ) 800d59e: 681b ldr r3, [r3, #0] 800d5a0: 6adb ldr r3, [r3, #44] @ 0x2c 800d5a2: 429a cmp r2, r3 800d5a4: d905 bls.n 800d5b2 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 800d5a6: 2301 movs r3, #1 800d5a8: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 800d5aa: 4b0a ldr r3, [pc, #40] @ (800d5d4 ) 800d5ac: 2201 movs r2, #1 800d5ae: 601a str r2, [r3, #0] 800d5b0: e001 b.n 800d5b6 } else { xReturn = pdFALSE; 800d5b2: 2300 movs r3, #0 800d5b4: 617b str r3, [r7, #20] } return xReturn; 800d5b6: 697b ldr r3, [r7, #20] } 800d5b8: 4618 mov r0, r3 800d5ba: 3718 adds r7, #24 800d5bc: 46bd mov sp, r7 800d5be: bd80 pop {r7, pc} 800d5c0: 24002624 .word 0x24002624 800d5c4: 24002604 .word 0x24002604 800d5c8: 2400212c .word 0x2400212c 800d5cc: 240025bc .word 0x240025bc 800d5d0: 24002128 .word 0x24002128 800d5d4: 24002610 .word 0x24002610 0800d5d8 : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 800d5d8: b580 push {r7, lr} 800d5da: b084 sub sp, #16 800d5dc: af00 add r7, sp, #0 800d5de: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 800d5e0: 687b ldr r3, [r7, #4] 800d5e2: 2b00 cmp r3, #0 800d5e4: d10b bne.n 800d5fe __asm volatile 800d5e6: f04f 0350 mov.w r3, #80 @ 0x50 800d5ea: f383 8811 msr BASEPRI, r3 800d5ee: f3bf 8f6f isb sy 800d5f2: f3bf 8f4f dsb sy 800d5f6: 60fb str r3, [r7, #12] } 800d5f8: bf00 nop 800d5fa: bf00 nop 800d5fc: e7fd b.n 800d5fa taskENTER_CRITICAL(); 800d5fe: f001 fa23 bl 800ea48 { pxTimeOut->xOverflowCount = xNumOfOverflows; 800d602: 4b07 ldr r3, [pc, #28] @ (800d620 ) 800d604: 681a ldr r2, [r3, #0] 800d606: 687b ldr r3, [r7, #4] 800d608: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 800d60a: 4b06 ldr r3, [pc, #24] @ (800d624 ) 800d60c: 681a ldr r2, [r3, #0] 800d60e: 687b ldr r3, [r7, #4] 800d610: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 800d612: f001 fa4b bl 800eaac } 800d616: bf00 nop 800d618: 3710 adds r7, #16 800d61a: 46bd mov sp, r7 800d61c: bd80 pop {r7, pc} 800d61e: bf00 nop 800d620: 24002614 .word 0x24002614 800d624: 24002600 .word 0x24002600 0800d628 : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 800d628: b480 push {r7} 800d62a: b083 sub sp, #12 800d62c: af00 add r7, sp, #0 800d62e: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 800d630: 4b06 ldr r3, [pc, #24] @ (800d64c ) 800d632: 681a ldr r2, [r3, #0] 800d634: 687b ldr r3, [r7, #4] 800d636: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 800d638: 4b05 ldr r3, [pc, #20] @ (800d650 ) 800d63a: 681a ldr r2, [r3, #0] 800d63c: 687b ldr r3, [r7, #4] 800d63e: 605a str r2, [r3, #4] } 800d640: bf00 nop 800d642: 370c adds r7, #12 800d644: 46bd mov sp, r7 800d646: f85d 7b04 ldr.w r7, [sp], #4 800d64a: 4770 bx lr 800d64c: 24002614 .word 0x24002614 800d650: 24002600 .word 0x24002600 0800d654 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 800d654: b580 push {r7, lr} 800d656: b088 sub sp, #32 800d658: af00 add r7, sp, #0 800d65a: 6078 str r0, [r7, #4] 800d65c: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 800d65e: 687b ldr r3, [r7, #4] 800d660: 2b00 cmp r3, #0 800d662: d10b bne.n 800d67c __asm volatile 800d664: f04f 0350 mov.w r3, #80 @ 0x50 800d668: f383 8811 msr BASEPRI, r3 800d66c: f3bf 8f6f isb sy 800d670: f3bf 8f4f dsb sy 800d674: 613b str r3, [r7, #16] } 800d676: bf00 nop 800d678: bf00 nop 800d67a: e7fd b.n 800d678 configASSERT( pxTicksToWait ); 800d67c: 683b ldr r3, [r7, #0] 800d67e: 2b00 cmp r3, #0 800d680: d10b bne.n 800d69a __asm volatile 800d682: f04f 0350 mov.w r3, #80 @ 0x50 800d686: f383 8811 msr BASEPRI, r3 800d68a: f3bf 8f6f isb sy 800d68e: f3bf 8f4f dsb sy 800d692: 60fb str r3, [r7, #12] } 800d694: bf00 nop 800d696: bf00 nop 800d698: e7fd b.n 800d696 taskENTER_CRITICAL(); 800d69a: f001 f9d5 bl 800ea48 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 800d69e: 4b1d ldr r3, [pc, #116] @ (800d714 ) 800d6a0: 681b ldr r3, [r3, #0] 800d6a2: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 800d6a4: 687b ldr r3, [r7, #4] 800d6a6: 685b ldr r3, [r3, #4] 800d6a8: 69ba ldr r2, [r7, #24] 800d6aa: 1ad3 subs r3, r2, r3 800d6ac: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 800d6ae: 683b ldr r3, [r7, #0] 800d6b0: 681b ldr r3, [r3, #0] 800d6b2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800d6b6: d102 bne.n 800d6be { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 800d6b8: 2300 movs r3, #0 800d6ba: 61fb str r3, [r7, #28] 800d6bc: e023 b.n 800d706 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 800d6be: 687b ldr r3, [r7, #4] 800d6c0: 681a ldr r2, [r3, #0] 800d6c2: 4b15 ldr r3, [pc, #84] @ (800d718 ) 800d6c4: 681b ldr r3, [r3, #0] 800d6c6: 429a cmp r2, r3 800d6c8: d007 beq.n 800d6da 800d6ca: 687b ldr r3, [r7, #4] 800d6cc: 685b ldr r3, [r3, #4] 800d6ce: 69ba ldr r2, [r7, #24] 800d6d0: 429a cmp r2, r3 800d6d2: d302 bcc.n 800d6da /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 800d6d4: 2301 movs r3, #1 800d6d6: 61fb str r3, [r7, #28] 800d6d8: e015 b.n 800d706 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 800d6da: 683b ldr r3, [r7, #0] 800d6dc: 681b ldr r3, [r3, #0] 800d6de: 697a ldr r2, [r7, #20] 800d6e0: 429a cmp r2, r3 800d6e2: d20b bcs.n 800d6fc { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 800d6e4: 683b ldr r3, [r7, #0] 800d6e6: 681a ldr r2, [r3, #0] 800d6e8: 697b ldr r3, [r7, #20] 800d6ea: 1ad2 subs r2, r2, r3 800d6ec: 683b ldr r3, [r7, #0] 800d6ee: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 800d6f0: 6878 ldr r0, [r7, #4] 800d6f2: f7ff ff99 bl 800d628 xReturn = pdFALSE; 800d6f6: 2300 movs r3, #0 800d6f8: 61fb str r3, [r7, #28] 800d6fa: e004 b.n 800d706 } else { *pxTicksToWait = 0; 800d6fc: 683b ldr r3, [r7, #0] 800d6fe: 2200 movs r2, #0 800d700: 601a str r2, [r3, #0] xReturn = pdTRUE; 800d702: 2301 movs r3, #1 800d704: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 800d706: f001 f9d1 bl 800eaac return xReturn; 800d70a: 69fb ldr r3, [r7, #28] } 800d70c: 4618 mov r0, r3 800d70e: 3720 adds r7, #32 800d710: 46bd mov sp, r7 800d712: bd80 pop {r7, pc} 800d714: 24002600 .word 0x24002600 800d718: 24002614 .word 0x24002614 0800d71c : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 800d71c: b480 push {r7} 800d71e: af00 add r7, sp, #0 xYieldPending = pdTRUE; 800d720: 4b03 ldr r3, [pc, #12] @ (800d730 ) 800d722: 2201 movs r2, #1 800d724: 601a str r2, [r3, #0] } 800d726: bf00 nop 800d728: 46bd mov sp, r7 800d72a: f85d 7b04 ldr.w r7, [sp], #4 800d72e: 4770 bx lr 800d730: 24002610 .word 0x24002610 0800d734 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 800d734: b580 push {r7, lr} 800d736: b082 sub sp, #8 800d738: af00 add r7, sp, #0 800d73a: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 800d73c: f000 f852 bl 800d7e4 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 800d740: 4b06 ldr r3, [pc, #24] @ (800d75c ) 800d742: 681b ldr r3, [r3, #0] 800d744: 2b01 cmp r3, #1 800d746: d9f9 bls.n 800d73c { taskYIELD(); 800d748: 4b05 ldr r3, [pc, #20] @ (800d760 ) 800d74a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800d74e: 601a str r2, [r3, #0] 800d750: f3bf 8f4f dsb sy 800d754: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 800d758: e7f0 b.n 800d73c 800d75a: bf00 nop 800d75c: 2400212c .word 0x2400212c 800d760: e000ed04 .word 0xe000ed04 0800d764 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 800d764: b580 push {r7, lr} 800d766: b082 sub sp, #8 800d768: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 800d76a: 2300 movs r3, #0 800d76c: 607b str r3, [r7, #4] 800d76e: e00c b.n 800d78a { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 800d770: 687a ldr r2, [r7, #4] 800d772: 4613 mov r3, r2 800d774: 009b lsls r3, r3, #2 800d776: 4413 add r3, r2 800d778: 009b lsls r3, r3, #2 800d77a: 4a12 ldr r2, [pc, #72] @ (800d7c4 ) 800d77c: 4413 add r3, r2 800d77e: 4618 mov r0, r3 800d780: f7fe f89e bl 800b8c0 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 800d784: 687b ldr r3, [r7, #4] 800d786: 3301 adds r3, #1 800d788: 607b str r3, [r7, #4] 800d78a: 687b ldr r3, [r7, #4] 800d78c: 2b37 cmp r3, #55 @ 0x37 800d78e: d9ef bls.n 800d770 } vListInitialise( &xDelayedTaskList1 ); 800d790: 480d ldr r0, [pc, #52] @ (800d7c8 ) 800d792: f7fe f895 bl 800b8c0 vListInitialise( &xDelayedTaskList2 ); 800d796: 480d ldr r0, [pc, #52] @ (800d7cc ) 800d798: f7fe f892 bl 800b8c0 vListInitialise( &xPendingReadyList ); 800d79c: 480c ldr r0, [pc, #48] @ (800d7d0 ) 800d79e: f7fe f88f bl 800b8c0 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 800d7a2: 480c ldr r0, [pc, #48] @ (800d7d4 ) 800d7a4: f7fe f88c bl 800b8c0 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 800d7a8: 480b ldr r0, [pc, #44] @ (800d7d8 ) 800d7aa: f7fe f889 bl 800b8c0 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 800d7ae: 4b0b ldr r3, [pc, #44] @ (800d7dc ) 800d7b0: 4a05 ldr r2, [pc, #20] @ (800d7c8 ) 800d7b2: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 800d7b4: 4b0a ldr r3, [pc, #40] @ (800d7e0 ) 800d7b6: 4a05 ldr r2, [pc, #20] @ (800d7cc ) 800d7b8: 601a str r2, [r3, #0] } 800d7ba: bf00 nop 800d7bc: 3708 adds r7, #8 800d7be: 46bd mov sp, r7 800d7c0: bd80 pop {r7, pc} 800d7c2: bf00 nop 800d7c4: 2400212c .word 0x2400212c 800d7c8: 2400258c .word 0x2400258c 800d7cc: 240025a0 .word 0x240025a0 800d7d0: 240025bc .word 0x240025bc 800d7d4: 240025d0 .word 0x240025d0 800d7d8: 240025e8 .word 0x240025e8 800d7dc: 240025b4 .word 0x240025b4 800d7e0: 240025b8 .word 0x240025b8 0800d7e4 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 800d7e4: b580 push {r7, lr} 800d7e6: b082 sub sp, #8 800d7e8: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 800d7ea: e019 b.n 800d820 { taskENTER_CRITICAL(); 800d7ec: f001 f92c bl 800ea48 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d7f0: 4b10 ldr r3, [pc, #64] @ (800d834 ) 800d7f2: 68db ldr r3, [r3, #12] 800d7f4: 68db ldr r3, [r3, #12] 800d7f6: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800d7f8: 687b ldr r3, [r7, #4] 800d7fa: 3304 adds r3, #4 800d7fc: 4618 mov r0, r3 800d7fe: f7fe f8e9 bl 800b9d4 --uxCurrentNumberOfTasks; 800d802: 4b0d ldr r3, [pc, #52] @ (800d838 ) 800d804: 681b ldr r3, [r3, #0] 800d806: 3b01 subs r3, #1 800d808: 4a0b ldr r2, [pc, #44] @ (800d838 ) 800d80a: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 800d80c: 4b0b ldr r3, [pc, #44] @ (800d83c ) 800d80e: 681b ldr r3, [r3, #0] 800d810: 3b01 subs r3, #1 800d812: 4a0a ldr r2, [pc, #40] @ (800d83c ) 800d814: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 800d816: f001 f949 bl 800eaac prvDeleteTCB( pxTCB ); 800d81a: 6878 ldr r0, [r7, #4] 800d81c: f000 f810 bl 800d840 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 800d820: 4b06 ldr r3, [pc, #24] @ (800d83c ) 800d822: 681b ldr r3, [r3, #0] 800d824: 2b00 cmp r3, #0 800d826: d1e1 bne.n 800d7ec } } #endif /* INCLUDE_vTaskDelete */ } 800d828: bf00 nop 800d82a: bf00 nop 800d82c: 3708 adds r7, #8 800d82e: 46bd mov sp, r7 800d830: bd80 pop {r7, pc} 800d832: bf00 nop 800d834: 240025d0 .word 0x240025d0 800d838: 240025fc .word 0x240025fc 800d83c: 240025e4 .word 0x240025e4 0800d840 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 800d840: b580 push {r7, lr} 800d842: b084 sub sp, #16 800d844: af00 add r7, sp, #0 800d846: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 800d848: 687b ldr r3, [r7, #4] 800d84a: 3354 adds r3, #84 @ 0x54 800d84c: 4618 mov r0, r3 800d84e: f001 fd3b bl 800f2c8 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 800d852: 687b ldr r3, [r7, #4] 800d854: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 800d858: 2b00 cmp r3, #0 800d85a: d108 bne.n 800d86e { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 800d85c: 687b ldr r3, [r7, #4] 800d85e: 6b1b ldr r3, [r3, #48] @ 0x30 800d860: 4618 mov r0, r3 800d862: f001 fae1 bl 800ee28 vPortFree( pxTCB ); 800d866: 6878 ldr r0, [r7, #4] 800d868: f001 fade bl 800ee28 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 800d86c: e019 b.n 800d8a2 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 800d86e: 687b ldr r3, [r7, #4] 800d870: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 800d874: 2b01 cmp r3, #1 800d876: d103 bne.n 800d880 vPortFree( pxTCB ); 800d878: 6878 ldr r0, [r7, #4] 800d87a: f001 fad5 bl 800ee28 } 800d87e: e010 b.n 800d8a2 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 800d880: 687b ldr r3, [r7, #4] 800d882: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 800d886: 2b02 cmp r3, #2 800d888: d00b beq.n 800d8a2 __asm volatile 800d88a: f04f 0350 mov.w r3, #80 @ 0x50 800d88e: f383 8811 msr BASEPRI, r3 800d892: f3bf 8f6f isb sy 800d896: f3bf 8f4f dsb sy 800d89a: 60fb str r3, [r7, #12] } 800d89c: bf00 nop 800d89e: bf00 nop 800d8a0: e7fd b.n 800d89e } 800d8a2: bf00 nop 800d8a4: 3710 adds r7, #16 800d8a6: 46bd mov sp, r7 800d8a8: bd80 pop {r7, pc} ... 0800d8ac : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 800d8ac: b480 push {r7} 800d8ae: b083 sub sp, #12 800d8b0: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800d8b2: 4b0c ldr r3, [pc, #48] @ (800d8e4 ) 800d8b4: 681b ldr r3, [r3, #0] 800d8b6: 681b ldr r3, [r3, #0] 800d8b8: 2b00 cmp r3, #0 800d8ba: d104 bne.n 800d8c6 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 800d8bc: 4b0a ldr r3, [pc, #40] @ (800d8e8 ) 800d8be: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800d8c2: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 800d8c4: e008 b.n 800d8d8 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800d8c6: 4b07 ldr r3, [pc, #28] @ (800d8e4 ) 800d8c8: 681b ldr r3, [r3, #0] 800d8ca: 68db ldr r3, [r3, #12] 800d8cc: 68db ldr r3, [r3, #12] 800d8ce: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 800d8d0: 687b ldr r3, [r7, #4] 800d8d2: 685b ldr r3, [r3, #4] 800d8d4: 4a04 ldr r2, [pc, #16] @ (800d8e8 ) 800d8d6: 6013 str r3, [r2, #0] } 800d8d8: bf00 nop 800d8da: 370c adds r7, #12 800d8dc: 46bd mov sp, r7 800d8de: f85d 7b04 ldr.w r7, [sp], #4 800d8e2: 4770 bx lr 800d8e4: 240025b4 .word 0x240025b4 800d8e8: 2400261c .word 0x2400261c 0800d8ec : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 800d8ec: b480 push {r7} 800d8ee: b083 sub sp, #12 800d8f0: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 800d8f2: 4b05 ldr r3, [pc, #20] @ (800d908 ) 800d8f4: 681b ldr r3, [r3, #0] 800d8f6: 607b str r3, [r7, #4] return xReturn; 800d8f8: 687b ldr r3, [r7, #4] } 800d8fa: 4618 mov r0, r3 800d8fc: 370c adds r7, #12 800d8fe: 46bd mov sp, r7 800d900: f85d 7b04 ldr.w r7, [sp], #4 800d904: 4770 bx lr 800d906: bf00 nop 800d908: 24002128 .word 0x24002128 0800d90c : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 800d90c: b480 push {r7} 800d90e: b083 sub sp, #12 800d910: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 800d912: 4b0b ldr r3, [pc, #44] @ (800d940 ) 800d914: 681b ldr r3, [r3, #0] 800d916: 2b00 cmp r3, #0 800d918: d102 bne.n 800d920 { xReturn = taskSCHEDULER_NOT_STARTED; 800d91a: 2301 movs r3, #1 800d91c: 607b str r3, [r7, #4] 800d91e: e008 b.n 800d932 } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800d920: 4b08 ldr r3, [pc, #32] @ (800d944 ) 800d922: 681b ldr r3, [r3, #0] 800d924: 2b00 cmp r3, #0 800d926: d102 bne.n 800d92e { xReturn = taskSCHEDULER_RUNNING; 800d928: 2302 movs r3, #2 800d92a: 607b str r3, [r7, #4] 800d92c: e001 b.n 800d932 } else { xReturn = taskSCHEDULER_SUSPENDED; 800d92e: 2300 movs r3, #0 800d930: 607b str r3, [r7, #4] } } return xReturn; 800d932: 687b ldr r3, [r7, #4] } 800d934: 4618 mov r0, r3 800d936: 370c adds r7, #12 800d938: 46bd mov sp, r7 800d93a: f85d 7b04 ldr.w r7, [sp], #4 800d93e: 4770 bx lr 800d940: 24002608 .word 0x24002608 800d944: 24002624 .word 0x24002624 0800d948 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 800d948: b580 push {r7, lr} 800d94a: b084 sub sp, #16 800d94c: af00 add r7, sp, #0 800d94e: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 800d950: 687b ldr r3, [r7, #4] 800d952: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 800d954: 2300 movs r3, #0 800d956: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 800d958: 687b ldr r3, [r7, #4] 800d95a: 2b00 cmp r3, #0 800d95c: d051 beq.n 800da02 { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 800d95e: 68bb ldr r3, [r7, #8] 800d960: 6ada ldr r2, [r3, #44] @ 0x2c 800d962: 4b2a ldr r3, [pc, #168] @ (800da0c ) 800d964: 681b ldr r3, [r3, #0] 800d966: 6adb ldr r3, [r3, #44] @ 0x2c 800d968: 429a cmp r2, r3 800d96a: d241 bcs.n 800d9f0 { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 800d96c: 68bb ldr r3, [r7, #8] 800d96e: 699b ldr r3, [r3, #24] 800d970: 2b00 cmp r3, #0 800d972: db06 blt.n 800d982 { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800d974: 4b25 ldr r3, [pc, #148] @ (800da0c ) 800d976: 681b ldr r3, [r3, #0] 800d978: 6adb ldr r3, [r3, #44] @ 0x2c 800d97a: f1c3 0238 rsb r2, r3, #56 @ 0x38 800d97e: 68bb ldr r3, [r7, #8] 800d980: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 800d982: 68bb ldr r3, [r7, #8] 800d984: 6959 ldr r1, [r3, #20] 800d986: 68bb ldr r3, [r7, #8] 800d988: 6ada ldr r2, [r3, #44] @ 0x2c 800d98a: 4613 mov r3, r2 800d98c: 009b lsls r3, r3, #2 800d98e: 4413 add r3, r2 800d990: 009b lsls r3, r3, #2 800d992: 4a1f ldr r2, [pc, #124] @ (800da10 ) 800d994: 4413 add r3, r2 800d996: 4299 cmp r1, r3 800d998: d122 bne.n 800d9e0 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800d99a: 68bb ldr r3, [r7, #8] 800d99c: 3304 adds r3, #4 800d99e: 4618 mov r0, r3 800d9a0: f7fe f818 bl 800b9d4 { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 800d9a4: 4b19 ldr r3, [pc, #100] @ (800da0c ) 800d9a6: 681b ldr r3, [r3, #0] 800d9a8: 6ada ldr r2, [r3, #44] @ 0x2c 800d9aa: 68bb ldr r3, [r7, #8] 800d9ac: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 800d9ae: 68bb ldr r3, [r7, #8] 800d9b0: 6ada ldr r2, [r3, #44] @ 0x2c 800d9b2: 4b18 ldr r3, [pc, #96] @ (800da14 ) 800d9b4: 681b ldr r3, [r3, #0] 800d9b6: 429a cmp r2, r3 800d9b8: d903 bls.n 800d9c2 800d9ba: 68bb ldr r3, [r7, #8] 800d9bc: 6adb ldr r3, [r3, #44] @ 0x2c 800d9be: 4a15 ldr r2, [pc, #84] @ (800da14 ) 800d9c0: 6013 str r3, [r2, #0] 800d9c2: 68bb ldr r3, [r7, #8] 800d9c4: 6ada ldr r2, [r3, #44] @ 0x2c 800d9c6: 4613 mov r3, r2 800d9c8: 009b lsls r3, r3, #2 800d9ca: 4413 add r3, r2 800d9cc: 009b lsls r3, r3, #2 800d9ce: 4a10 ldr r2, [pc, #64] @ (800da10 ) 800d9d0: 441a add r2, r3 800d9d2: 68bb ldr r3, [r7, #8] 800d9d4: 3304 adds r3, #4 800d9d6: 4619 mov r1, r3 800d9d8: 4610 mov r0, r2 800d9da: f7fd ff9e bl 800b91a 800d9de: e004 b.n 800d9ea } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 800d9e0: 4b0a ldr r3, [pc, #40] @ (800da0c ) 800d9e2: 681b ldr r3, [r3, #0] 800d9e4: 6ada ldr r2, [r3, #44] @ 0x2c 800d9e6: 68bb ldr r3, [r7, #8] 800d9e8: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 800d9ea: 2301 movs r3, #1 800d9ec: 60fb str r3, [r7, #12] 800d9ee: e008 b.n 800da02 } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 800d9f0: 68bb ldr r3, [r7, #8] 800d9f2: 6cda ldr r2, [r3, #76] @ 0x4c 800d9f4: 4b05 ldr r3, [pc, #20] @ (800da0c ) 800d9f6: 681b ldr r3, [r3, #0] 800d9f8: 6adb ldr r3, [r3, #44] @ 0x2c 800d9fa: 429a cmp r2, r3 800d9fc: d201 bcs.n 800da02 current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 800d9fe: 2301 movs r3, #1 800da00: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 800da02: 68fb ldr r3, [r7, #12] } 800da04: 4618 mov r0, r3 800da06: 3710 adds r7, #16 800da08: 46bd mov sp, r7 800da0a: bd80 pop {r7, pc} 800da0c: 24002128 .word 0x24002128 800da10: 2400212c .word 0x2400212c 800da14: 24002604 .word 0x24002604 0800da18 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 800da18: b580 push {r7, lr} 800da1a: b086 sub sp, #24 800da1c: af00 add r7, sp, #0 800da1e: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 800da20: 687b ldr r3, [r7, #4] 800da22: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 800da24: 2300 movs r3, #0 800da26: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 800da28: 687b ldr r3, [r7, #4] 800da2a: 2b00 cmp r3, #0 800da2c: d058 beq.n 800dae0 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 800da2e: 4b2f ldr r3, [pc, #188] @ (800daec ) 800da30: 681b ldr r3, [r3, #0] 800da32: 693a ldr r2, [r7, #16] 800da34: 429a cmp r2, r3 800da36: d00b beq.n 800da50 __asm volatile 800da38: f04f 0350 mov.w r3, #80 @ 0x50 800da3c: f383 8811 msr BASEPRI, r3 800da40: f3bf 8f6f isb sy 800da44: f3bf 8f4f dsb sy 800da48: 60fb str r3, [r7, #12] } 800da4a: bf00 nop 800da4c: bf00 nop 800da4e: e7fd b.n 800da4c configASSERT( pxTCB->uxMutexesHeld ); 800da50: 693b ldr r3, [r7, #16] 800da52: 6d1b ldr r3, [r3, #80] @ 0x50 800da54: 2b00 cmp r3, #0 800da56: d10b bne.n 800da70 __asm volatile 800da58: f04f 0350 mov.w r3, #80 @ 0x50 800da5c: f383 8811 msr BASEPRI, r3 800da60: f3bf 8f6f isb sy 800da64: f3bf 8f4f dsb sy 800da68: 60bb str r3, [r7, #8] } 800da6a: bf00 nop 800da6c: bf00 nop 800da6e: e7fd b.n 800da6c ( pxTCB->uxMutexesHeld )--; 800da70: 693b ldr r3, [r7, #16] 800da72: 6d1b ldr r3, [r3, #80] @ 0x50 800da74: 1e5a subs r2, r3, #1 800da76: 693b ldr r3, [r7, #16] 800da78: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 800da7a: 693b ldr r3, [r7, #16] 800da7c: 6ada ldr r2, [r3, #44] @ 0x2c 800da7e: 693b ldr r3, [r7, #16] 800da80: 6cdb ldr r3, [r3, #76] @ 0x4c 800da82: 429a cmp r2, r3 800da84: d02c beq.n 800dae0 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 800da86: 693b ldr r3, [r7, #16] 800da88: 6d1b ldr r3, [r3, #80] @ 0x50 800da8a: 2b00 cmp r3, #0 800da8c: d128 bne.n 800dae0 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800da8e: 693b ldr r3, [r7, #16] 800da90: 3304 adds r3, #4 800da92: 4618 mov r0, r3 800da94: f7fd ff9e bl 800b9d4 } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 800da98: 693b ldr r3, [r7, #16] 800da9a: 6cda ldr r2, [r3, #76] @ 0x4c 800da9c: 693b ldr r3, [r7, #16] 800da9e: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800daa0: 693b ldr r3, [r7, #16] 800daa2: 6adb ldr r3, [r3, #44] @ 0x2c 800daa4: f1c3 0238 rsb r2, r3, #56 @ 0x38 800daa8: 693b ldr r3, [r7, #16] 800daaa: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 800daac: 693b ldr r3, [r7, #16] 800daae: 6ada ldr r2, [r3, #44] @ 0x2c 800dab0: 4b0f ldr r3, [pc, #60] @ (800daf0 ) 800dab2: 681b ldr r3, [r3, #0] 800dab4: 429a cmp r2, r3 800dab6: d903 bls.n 800dac0 800dab8: 693b ldr r3, [r7, #16] 800daba: 6adb ldr r3, [r3, #44] @ 0x2c 800dabc: 4a0c ldr r2, [pc, #48] @ (800daf0 ) 800dabe: 6013 str r3, [r2, #0] 800dac0: 693b ldr r3, [r7, #16] 800dac2: 6ada ldr r2, [r3, #44] @ 0x2c 800dac4: 4613 mov r3, r2 800dac6: 009b lsls r3, r3, #2 800dac8: 4413 add r3, r2 800daca: 009b lsls r3, r3, #2 800dacc: 4a09 ldr r2, [pc, #36] @ (800daf4 ) 800dace: 441a add r2, r3 800dad0: 693b ldr r3, [r7, #16] 800dad2: 3304 adds r3, #4 800dad4: 4619 mov r1, r3 800dad6: 4610 mov r0, r2 800dad8: f7fd ff1f bl 800b91a in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 800dadc: 2301 movs r3, #1 800dade: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 800dae0: 697b ldr r3, [r7, #20] } 800dae2: 4618 mov r0, r3 800dae4: 3718 adds r7, #24 800dae6: 46bd mov sp, r7 800dae8: bd80 pop {r7, pc} 800daea: bf00 nop 800daec: 24002128 .word 0x24002128 800daf0: 24002604 .word 0x24002604 800daf4: 2400212c .word 0x2400212c 0800daf8 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 800daf8: b580 push {r7, lr} 800dafa: b088 sub sp, #32 800dafc: af00 add r7, sp, #0 800dafe: 6078 str r0, [r7, #4] 800db00: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 800db02: 687b ldr r3, [r7, #4] 800db04: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 800db06: 2301 movs r3, #1 800db08: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 800db0a: 687b ldr r3, [r7, #4] 800db0c: 2b00 cmp r3, #0 800db0e: d06c beq.n 800dbea { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 800db10: 69bb ldr r3, [r7, #24] 800db12: 6d1b ldr r3, [r3, #80] @ 0x50 800db14: 2b00 cmp r3, #0 800db16: d10b bne.n 800db30 __asm volatile 800db18: f04f 0350 mov.w r3, #80 @ 0x50 800db1c: f383 8811 msr BASEPRI, r3 800db20: f3bf 8f6f isb sy 800db24: f3bf 8f4f dsb sy 800db28: 60fb str r3, [r7, #12] } 800db2a: bf00 nop 800db2c: bf00 nop 800db2e: e7fd b.n 800db2c /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 800db30: 69bb ldr r3, [r7, #24] 800db32: 6cdb ldr r3, [r3, #76] @ 0x4c 800db34: 683a ldr r2, [r7, #0] 800db36: 429a cmp r2, r3 800db38: d902 bls.n 800db40 { uxPriorityToUse = uxHighestPriorityWaitingTask; 800db3a: 683b ldr r3, [r7, #0] 800db3c: 61fb str r3, [r7, #28] 800db3e: e002 b.n 800db46 } else { uxPriorityToUse = pxTCB->uxBasePriority; 800db40: 69bb ldr r3, [r7, #24] 800db42: 6cdb ldr r3, [r3, #76] @ 0x4c 800db44: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 800db46: 69bb ldr r3, [r7, #24] 800db48: 6adb ldr r3, [r3, #44] @ 0x2c 800db4a: 69fa ldr r2, [r7, #28] 800db4c: 429a cmp r2, r3 800db4e: d04c beq.n 800dbea { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 800db50: 69bb ldr r3, [r7, #24] 800db52: 6d1b ldr r3, [r3, #80] @ 0x50 800db54: 697a ldr r2, [r7, #20] 800db56: 429a cmp r2, r3 800db58: d147 bne.n 800dbea { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 800db5a: 4b26 ldr r3, [pc, #152] @ (800dbf4 ) 800db5c: 681b ldr r3, [r3, #0] 800db5e: 69ba ldr r2, [r7, #24] 800db60: 429a cmp r2, r3 800db62: d10b bne.n 800db7c __asm volatile 800db64: f04f 0350 mov.w r3, #80 @ 0x50 800db68: f383 8811 msr BASEPRI, r3 800db6c: f3bf 8f6f isb sy 800db70: f3bf 8f4f dsb sy 800db74: 60bb str r3, [r7, #8] } 800db76: bf00 nop 800db78: bf00 nop 800db7a: e7fd b.n 800db78 /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 800db7c: 69bb ldr r3, [r7, #24] 800db7e: 6adb ldr r3, [r3, #44] @ 0x2c 800db80: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 800db82: 69bb ldr r3, [r7, #24] 800db84: 69fa ldr r2, [r7, #28] 800db86: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 800db88: 69bb ldr r3, [r7, #24] 800db8a: 699b ldr r3, [r3, #24] 800db8c: 2b00 cmp r3, #0 800db8e: db04 blt.n 800db9a { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800db90: 69fb ldr r3, [r7, #28] 800db92: f1c3 0238 rsb r2, r3, #56 @ 0x38 800db96: 69bb ldr r3, [r7, #24] 800db98: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 800db9a: 69bb ldr r3, [r7, #24] 800db9c: 6959 ldr r1, [r3, #20] 800db9e: 693a ldr r2, [r7, #16] 800dba0: 4613 mov r3, r2 800dba2: 009b lsls r3, r3, #2 800dba4: 4413 add r3, r2 800dba6: 009b lsls r3, r3, #2 800dba8: 4a13 ldr r2, [pc, #76] @ (800dbf8 ) 800dbaa: 4413 add r3, r2 800dbac: 4299 cmp r1, r3 800dbae: d11c bne.n 800dbea { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800dbb0: 69bb ldr r3, [r7, #24] 800dbb2: 3304 adds r3, #4 800dbb4: 4618 mov r0, r3 800dbb6: f7fd ff0d bl 800b9d4 else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 800dbba: 69bb ldr r3, [r7, #24] 800dbbc: 6ada ldr r2, [r3, #44] @ 0x2c 800dbbe: 4b0f ldr r3, [pc, #60] @ (800dbfc ) 800dbc0: 681b ldr r3, [r3, #0] 800dbc2: 429a cmp r2, r3 800dbc4: d903 bls.n 800dbce 800dbc6: 69bb ldr r3, [r7, #24] 800dbc8: 6adb ldr r3, [r3, #44] @ 0x2c 800dbca: 4a0c ldr r2, [pc, #48] @ (800dbfc ) 800dbcc: 6013 str r3, [r2, #0] 800dbce: 69bb ldr r3, [r7, #24] 800dbd0: 6ada ldr r2, [r3, #44] @ 0x2c 800dbd2: 4613 mov r3, r2 800dbd4: 009b lsls r3, r3, #2 800dbd6: 4413 add r3, r2 800dbd8: 009b lsls r3, r3, #2 800dbda: 4a07 ldr r2, [pc, #28] @ (800dbf8 ) 800dbdc: 441a add r2, r3 800dbde: 69bb ldr r3, [r7, #24] 800dbe0: 3304 adds r3, #4 800dbe2: 4619 mov r1, r3 800dbe4: 4610 mov r0, r2 800dbe6: f7fd fe98 bl 800b91a } else { mtCOVERAGE_TEST_MARKER(); } } 800dbea: bf00 nop 800dbec: 3720 adds r7, #32 800dbee: 46bd mov sp, r7 800dbf0: bd80 pop {r7, pc} 800dbf2: bf00 nop 800dbf4: 24002128 .word 0x24002128 800dbf8: 2400212c .word 0x2400212c 800dbfc: 24002604 .word 0x24002604 0800dc00 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 800dc00: b480 push {r7} 800dc02: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 800dc04: 4b07 ldr r3, [pc, #28] @ (800dc24 ) 800dc06: 681b ldr r3, [r3, #0] 800dc08: 2b00 cmp r3, #0 800dc0a: d004 beq.n 800dc16 { ( pxCurrentTCB->uxMutexesHeld )++; 800dc0c: 4b05 ldr r3, [pc, #20] @ (800dc24 ) 800dc0e: 681b ldr r3, [r3, #0] 800dc10: 6d1a ldr r2, [r3, #80] @ 0x50 800dc12: 3201 adds r2, #1 800dc14: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 800dc16: 4b03 ldr r3, [pc, #12] @ (800dc24 ) 800dc18: 681b ldr r3, [r3, #0] } 800dc1a: 4618 mov r0, r3 800dc1c: 46bd mov sp, r7 800dc1e: f85d 7b04 ldr.w r7, [sp], #4 800dc22: 4770 bx lr 800dc24: 24002128 .word 0x24002128 0800dc28 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 800dc28: b580 push {r7, lr} 800dc2a: b086 sub sp, #24 800dc2c: af00 add r7, sp, #0 800dc2e: 60f8 str r0, [r7, #12] 800dc30: 60b9 str r1, [r7, #8] 800dc32: 607a str r2, [r7, #4] 800dc34: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 800dc36: f000 ff07 bl 800ea48 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 800dc3a: 4b29 ldr r3, [pc, #164] @ (800dce0 ) 800dc3c: 681b ldr r3, [r3, #0] 800dc3e: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 800dc42: b2db uxtb r3, r3 800dc44: 2b02 cmp r3, #2 800dc46: d01c beq.n 800dc82 { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 800dc48: 4b25 ldr r3, [pc, #148] @ (800dce0 ) 800dc4a: 681b ldr r3, [r3, #0] 800dc4c: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 800dc50: 68fa ldr r2, [r7, #12] 800dc52: 43d2 mvns r2, r2 800dc54: 400a ands r2, r1 800dc56: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 800dc5a: 4b21 ldr r3, [pc, #132] @ (800dce0 ) 800dc5c: 681b ldr r3, [r3, #0] 800dc5e: 2201 movs r2, #1 800dc60: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 800dc64: 683b ldr r3, [r7, #0] 800dc66: 2b00 cmp r3, #0 800dc68: d00b beq.n 800dc82 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 800dc6a: 2101 movs r1, #1 800dc6c: 6838 ldr r0, [r7, #0] 800dc6e: f000 fa09 bl 800e084 /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 800dc72: 4b1c ldr r3, [pc, #112] @ (800dce4 ) 800dc74: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800dc78: 601a str r2, [r3, #0] 800dc7a: f3bf 8f4f dsb sy 800dc7e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 800dc82: f000 ff13 bl 800eaac taskENTER_CRITICAL(); 800dc86: f000 fedf bl 800ea48 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 800dc8a: 687b ldr r3, [r7, #4] 800dc8c: 2b00 cmp r3, #0 800dc8e: d005 beq.n 800dc9c { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 800dc90: 4b13 ldr r3, [pc, #76] @ (800dce0 ) 800dc92: 681b ldr r3, [r3, #0] 800dc94: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 800dc98: 687b ldr r3, [r7, #4] 800dc9a: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 800dc9c: 4b10 ldr r3, [pc, #64] @ (800dce0 ) 800dc9e: 681b ldr r3, [r3, #0] 800dca0: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 800dca4: b2db uxtb r3, r3 800dca6: 2b02 cmp r3, #2 800dca8: d002 beq.n 800dcb0 { /* A notification was not received. */ xReturn = pdFALSE; 800dcaa: 2300 movs r3, #0 800dcac: 617b str r3, [r7, #20] 800dcae: e00a b.n 800dcc6 } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 800dcb0: 4b0b ldr r3, [pc, #44] @ (800dce0 ) 800dcb2: 681b ldr r3, [r3, #0] 800dcb4: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 800dcb8: 68ba ldr r2, [r7, #8] 800dcba: 43d2 mvns r2, r2 800dcbc: 400a ands r2, r1 800dcbe: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 800dcc2: 2301 movs r3, #1 800dcc4: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 800dcc6: 4b06 ldr r3, [pc, #24] @ (800dce0 ) 800dcc8: 681b ldr r3, [r3, #0] 800dcca: 2200 movs r2, #0 800dccc: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 800dcd0: f000 feec bl 800eaac return xReturn; 800dcd4: 697b ldr r3, [r7, #20] } 800dcd6: 4618 mov r0, r3 800dcd8: 3718 adds r7, #24 800dcda: 46bd mov sp, r7 800dcdc: bd80 pop {r7, pc} 800dcde: bf00 nop 800dce0: 24002128 .word 0x24002128 800dce4: e000ed04 .word 0xe000ed04 0800dce8 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 800dce8: b580 push {r7, lr} 800dcea: b08a sub sp, #40 @ 0x28 800dcec: af00 add r7, sp, #0 800dcee: 60f8 str r0, [r7, #12] 800dcf0: 60b9 str r1, [r7, #8] 800dcf2: 603b str r3, [r7, #0] 800dcf4: 4613 mov r3, r2 800dcf6: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 800dcf8: 2301 movs r3, #1 800dcfa: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 800dcfc: 68fb ldr r3, [r7, #12] 800dcfe: 2b00 cmp r3, #0 800dd00: d10b bne.n 800dd1a __asm volatile 800dd02: f04f 0350 mov.w r3, #80 @ 0x50 800dd06: f383 8811 msr BASEPRI, r3 800dd0a: f3bf 8f6f isb sy 800dd0e: f3bf 8f4f dsb sy 800dd12: 61bb str r3, [r7, #24] } 800dd14: bf00 nop 800dd16: bf00 nop 800dd18: e7fd b.n 800dd16 pxTCB = xTaskToNotify; 800dd1a: 68fb ldr r3, [r7, #12] 800dd1c: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 800dd1e: f000 fe93 bl 800ea48 { if( pulPreviousNotificationValue != NULL ) 800dd22: 683b ldr r3, [r7, #0] 800dd24: 2b00 cmp r3, #0 800dd26: d004 beq.n 800dd32 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 800dd28: 6a3b ldr r3, [r7, #32] 800dd2a: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 800dd2e: 683b ldr r3, [r7, #0] 800dd30: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 800dd32: 6a3b ldr r3, [r7, #32] 800dd34: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 800dd38: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 800dd3a: 6a3b ldr r3, [r7, #32] 800dd3c: 2202 movs r2, #2 800dd3e: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 800dd42: 79fb ldrb r3, [r7, #7] 800dd44: 2b04 cmp r3, #4 800dd46: d82e bhi.n 800dda6 800dd48: a201 add r2, pc, #4 @ (adr r2, 800dd50 ) 800dd4a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800dd4e: bf00 nop 800dd50: 0800ddcb .word 0x0800ddcb 800dd54: 0800dd65 .word 0x0800dd65 800dd58: 0800dd77 .word 0x0800dd77 800dd5c: 0800dd87 .word 0x0800dd87 800dd60: 0800dd91 .word 0x0800dd91 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 800dd64: 6a3b ldr r3, [r7, #32] 800dd66: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 800dd6a: 68bb ldr r3, [r7, #8] 800dd6c: 431a orrs r2, r3 800dd6e: 6a3b ldr r3, [r7, #32] 800dd70: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 800dd74: e02c b.n 800ddd0 case eIncrement : ( pxTCB->ulNotifiedValue )++; 800dd76: 6a3b ldr r3, [r7, #32] 800dd78: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800dd7c: 1c5a adds r2, r3, #1 800dd7e: 6a3b ldr r3, [r7, #32] 800dd80: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 800dd84: e024 b.n 800ddd0 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 800dd86: 6a3b ldr r3, [r7, #32] 800dd88: 68ba ldr r2, [r7, #8] 800dd8a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 800dd8e: e01f b.n 800ddd0 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 800dd90: 7ffb ldrb r3, [r7, #31] 800dd92: 2b02 cmp r3, #2 800dd94: d004 beq.n 800dda0 { pxTCB->ulNotifiedValue = ulValue; 800dd96: 6a3b ldr r3, [r7, #32] 800dd98: 68ba ldr r2, [r7, #8] 800dd9a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 800dd9e: e017 b.n 800ddd0 xReturn = pdFAIL; 800dda0: 2300 movs r3, #0 800dda2: 627b str r3, [r7, #36] @ 0x24 break; 800dda4: e014 b.n 800ddd0 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 800dda6: 6a3b ldr r3, [r7, #32] 800dda8: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800ddac: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800ddb0: d00d beq.n 800ddce __asm volatile 800ddb2: f04f 0350 mov.w r3, #80 @ 0x50 800ddb6: f383 8811 msr BASEPRI, r3 800ddba: f3bf 8f6f isb sy 800ddbe: f3bf 8f4f dsb sy 800ddc2: 617b str r3, [r7, #20] } 800ddc4: bf00 nop 800ddc6: bf00 nop 800ddc8: e7fd b.n 800ddc6 break; 800ddca: bf00 nop 800ddcc: e000 b.n 800ddd0 break; 800ddce: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 800ddd0: 7ffb ldrb r3, [r7, #31] 800ddd2: 2b01 cmp r3, #1 800ddd4: d13b bne.n 800de4e { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800ddd6: 6a3b ldr r3, [r7, #32] 800ddd8: 3304 adds r3, #4 800ddda: 4618 mov r0, r3 800dddc: f7fd fdfa bl 800b9d4 prvAddTaskToReadyList( pxTCB ); 800dde0: 6a3b ldr r3, [r7, #32] 800dde2: 6ada ldr r2, [r3, #44] @ 0x2c 800dde4: 4b1d ldr r3, [pc, #116] @ (800de5c ) 800dde6: 681b ldr r3, [r3, #0] 800dde8: 429a cmp r2, r3 800ddea: d903 bls.n 800ddf4 800ddec: 6a3b ldr r3, [r7, #32] 800ddee: 6adb ldr r3, [r3, #44] @ 0x2c 800ddf0: 4a1a ldr r2, [pc, #104] @ (800de5c ) 800ddf2: 6013 str r3, [r2, #0] 800ddf4: 6a3b ldr r3, [r7, #32] 800ddf6: 6ada ldr r2, [r3, #44] @ 0x2c 800ddf8: 4613 mov r3, r2 800ddfa: 009b lsls r3, r3, #2 800ddfc: 4413 add r3, r2 800ddfe: 009b lsls r3, r3, #2 800de00: 4a17 ldr r2, [pc, #92] @ (800de60 ) 800de02: 441a add r2, r3 800de04: 6a3b ldr r3, [r7, #32] 800de06: 3304 adds r3, #4 800de08: 4619 mov r1, r3 800de0a: 4610 mov r0, r2 800de0c: f7fd fd85 bl 800b91a /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 800de10: 6a3b ldr r3, [r7, #32] 800de12: 6a9b ldr r3, [r3, #40] @ 0x28 800de14: 2b00 cmp r3, #0 800de16: d00b beq.n 800de30 __asm volatile 800de18: f04f 0350 mov.w r3, #80 @ 0x50 800de1c: f383 8811 msr BASEPRI, r3 800de20: f3bf 8f6f isb sy 800de24: f3bf 8f4f dsb sy 800de28: 613b str r3, [r7, #16] } 800de2a: bf00 nop 800de2c: bf00 nop 800de2e: e7fd b.n 800de2c earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 800de30: 6a3b ldr r3, [r7, #32] 800de32: 6ada ldr r2, [r3, #44] @ 0x2c 800de34: 4b0b ldr r3, [pc, #44] @ (800de64 ) 800de36: 681b ldr r3, [r3, #0] 800de38: 6adb ldr r3, [r3, #44] @ 0x2c 800de3a: 429a cmp r2, r3 800de3c: d907 bls.n 800de4e { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 800de3e: 4b0a ldr r3, [pc, #40] @ (800de68 ) 800de40: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800de44: 601a str r2, [r3, #0] 800de46: f3bf 8f4f dsb sy 800de4a: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 800de4e: f000 fe2d bl 800eaac return xReturn; 800de52: 6a7b ldr r3, [r7, #36] @ 0x24 } 800de54: 4618 mov r0, r3 800de56: 3728 adds r7, #40 @ 0x28 800de58: 46bd mov sp, r7 800de5a: bd80 pop {r7, pc} 800de5c: 24002604 .word 0x24002604 800de60: 2400212c .word 0x2400212c 800de64: 24002128 .word 0x24002128 800de68: e000ed04 .word 0xe000ed04 0800de6c : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 800de6c: b580 push {r7, lr} 800de6e: b08e sub sp, #56 @ 0x38 800de70: af00 add r7, sp, #0 800de72: 60f8 str r0, [r7, #12] 800de74: 60b9 str r1, [r7, #8] 800de76: 603b str r3, [r7, #0] 800de78: 4613 mov r3, r2 800de7a: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 800de7c: 2301 movs r3, #1 800de7e: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 800de80: 68fb ldr r3, [r7, #12] 800de82: 2b00 cmp r3, #0 800de84: d10b bne.n 800de9e __asm volatile 800de86: f04f 0350 mov.w r3, #80 @ 0x50 800de8a: f383 8811 msr BASEPRI, r3 800de8e: f3bf 8f6f isb sy 800de92: f3bf 8f4f dsb sy 800de96: 627b str r3, [r7, #36] @ 0x24 } 800de98: bf00 nop 800de9a: bf00 nop 800de9c: e7fd b.n 800de9a below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 800de9e: f000 feb3 bl 800ec08 pxTCB = xTaskToNotify; 800dea2: 68fb ldr r3, [r7, #12] 800dea4: 633b str r3, [r7, #48] @ 0x30 __asm volatile 800dea6: f3ef 8211 mrs r2, BASEPRI 800deaa: f04f 0350 mov.w r3, #80 @ 0x50 800deae: f383 8811 msr BASEPRI, r3 800deb2: f3bf 8f6f isb sy 800deb6: f3bf 8f4f dsb sy 800deba: 623a str r2, [r7, #32] 800debc: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 800debe: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 800dec0: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 800dec2: 683b ldr r3, [r7, #0] 800dec4: 2b00 cmp r3, #0 800dec6: d004 beq.n 800ded2 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 800dec8: 6b3b ldr r3, [r7, #48] @ 0x30 800deca: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 800dece: 683b ldr r3, [r7, #0] 800ded0: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 800ded2: 6b3b ldr r3, [r7, #48] @ 0x30 800ded4: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 800ded8: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 800dedc: 6b3b ldr r3, [r7, #48] @ 0x30 800dede: 2202 movs r2, #2 800dee0: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 800dee4: 79fb ldrb r3, [r7, #7] 800dee6: 2b04 cmp r3, #4 800dee8: d82e bhi.n 800df48 800deea: a201 add r2, pc, #4 @ (adr r2, 800def0 ) 800deec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800def0: 0800df6d .word 0x0800df6d 800def4: 0800df05 .word 0x0800df05 800def8: 0800df17 .word 0x0800df17 800defc: 0800df27 .word 0x0800df27 800df00: 0800df31 .word 0x0800df31 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 800df04: 6b3b ldr r3, [r7, #48] @ 0x30 800df06: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 800df0a: 68bb ldr r3, [r7, #8] 800df0c: 431a orrs r2, r3 800df0e: 6b3b ldr r3, [r7, #48] @ 0x30 800df10: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 800df14: e02d b.n 800df72 case eIncrement : ( pxTCB->ulNotifiedValue )++; 800df16: 6b3b ldr r3, [r7, #48] @ 0x30 800df18: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800df1c: 1c5a adds r2, r3, #1 800df1e: 6b3b ldr r3, [r7, #48] @ 0x30 800df20: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 800df24: e025 b.n 800df72 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 800df26: 6b3b ldr r3, [r7, #48] @ 0x30 800df28: 68ba ldr r2, [r7, #8] 800df2a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 800df2e: e020 b.n 800df72 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 800df30: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 800df34: 2b02 cmp r3, #2 800df36: d004 beq.n 800df42 { pxTCB->ulNotifiedValue = ulValue; 800df38: 6b3b ldr r3, [r7, #48] @ 0x30 800df3a: 68ba ldr r2, [r7, #8] 800df3c: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 800df40: e017 b.n 800df72 xReturn = pdFAIL; 800df42: 2300 movs r3, #0 800df44: 637b str r3, [r7, #52] @ 0x34 break; 800df46: e014 b.n 800df72 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 800df48: 6b3b ldr r3, [r7, #48] @ 0x30 800df4a: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800df4e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800df52: d00d beq.n 800df70 __asm volatile 800df54: f04f 0350 mov.w r3, #80 @ 0x50 800df58: f383 8811 msr BASEPRI, r3 800df5c: f3bf 8f6f isb sy 800df60: f3bf 8f4f dsb sy 800df64: 61bb str r3, [r7, #24] } 800df66: bf00 nop 800df68: bf00 nop 800df6a: e7fd b.n 800df68 break; 800df6c: bf00 nop 800df6e: e000 b.n 800df72 break; 800df70: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 800df72: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 800df76: 2b01 cmp r3, #1 800df78: d147 bne.n 800e00a { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 800df7a: 6b3b ldr r3, [r7, #48] @ 0x30 800df7c: 6a9b ldr r3, [r3, #40] @ 0x28 800df7e: 2b00 cmp r3, #0 800df80: d00b beq.n 800df9a __asm volatile 800df82: f04f 0350 mov.w r3, #80 @ 0x50 800df86: f383 8811 msr BASEPRI, r3 800df8a: f3bf 8f6f isb sy 800df8e: f3bf 8f4f dsb sy 800df92: 617b str r3, [r7, #20] } 800df94: bf00 nop 800df96: bf00 nop 800df98: e7fd b.n 800df96 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800df9a: 4b21 ldr r3, [pc, #132] @ (800e020 ) 800df9c: 681b ldr r3, [r3, #0] 800df9e: 2b00 cmp r3, #0 800dfa0: d11d bne.n 800dfde { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800dfa2: 6b3b ldr r3, [r7, #48] @ 0x30 800dfa4: 3304 adds r3, #4 800dfa6: 4618 mov r0, r3 800dfa8: f7fd fd14 bl 800b9d4 prvAddTaskToReadyList( pxTCB ); 800dfac: 6b3b ldr r3, [r7, #48] @ 0x30 800dfae: 6ada ldr r2, [r3, #44] @ 0x2c 800dfb0: 4b1c ldr r3, [pc, #112] @ (800e024 ) 800dfb2: 681b ldr r3, [r3, #0] 800dfb4: 429a cmp r2, r3 800dfb6: d903 bls.n 800dfc0 800dfb8: 6b3b ldr r3, [r7, #48] @ 0x30 800dfba: 6adb ldr r3, [r3, #44] @ 0x2c 800dfbc: 4a19 ldr r2, [pc, #100] @ (800e024 ) 800dfbe: 6013 str r3, [r2, #0] 800dfc0: 6b3b ldr r3, [r7, #48] @ 0x30 800dfc2: 6ada ldr r2, [r3, #44] @ 0x2c 800dfc4: 4613 mov r3, r2 800dfc6: 009b lsls r3, r3, #2 800dfc8: 4413 add r3, r2 800dfca: 009b lsls r3, r3, #2 800dfcc: 4a16 ldr r2, [pc, #88] @ (800e028 ) 800dfce: 441a add r2, r3 800dfd0: 6b3b ldr r3, [r7, #48] @ 0x30 800dfd2: 3304 adds r3, #4 800dfd4: 4619 mov r1, r3 800dfd6: 4610 mov r0, r2 800dfd8: f7fd fc9f bl 800b91a 800dfdc: e005 b.n 800dfea } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 800dfde: 6b3b ldr r3, [r7, #48] @ 0x30 800dfe0: 3318 adds r3, #24 800dfe2: 4619 mov r1, r3 800dfe4: 4811 ldr r0, [pc, #68] @ (800e02c ) 800dfe6: f7fd fc98 bl 800b91a } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 800dfea: 6b3b ldr r3, [r7, #48] @ 0x30 800dfec: 6ada ldr r2, [r3, #44] @ 0x2c 800dfee: 4b10 ldr r3, [pc, #64] @ (800e030 ) 800dff0: 681b ldr r3, [r3, #0] 800dff2: 6adb ldr r3, [r3, #44] @ 0x2c 800dff4: 429a cmp r2, r3 800dff6: d908 bls.n 800e00a { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 800dff8: 6c3b ldr r3, [r7, #64] @ 0x40 800dffa: 2b00 cmp r3, #0 800dffc: d002 beq.n 800e004 { *pxHigherPriorityTaskWoken = pdTRUE; 800dffe: 6c3b ldr r3, [r7, #64] @ 0x40 800e000: 2201 movs r2, #1 800e002: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 800e004: 4b0b ldr r3, [pc, #44] @ (800e034 ) 800e006: 2201 movs r2, #1 800e008: 601a str r2, [r3, #0] 800e00a: 6afb ldr r3, [r7, #44] @ 0x2c 800e00c: 613b str r3, [r7, #16] __asm volatile 800e00e: 693b ldr r3, [r7, #16] 800e010: f383 8811 msr BASEPRI, r3 } 800e014: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 800e016: 6b7b ldr r3, [r7, #52] @ 0x34 } 800e018: 4618 mov r0, r3 800e01a: 3738 adds r7, #56 @ 0x38 800e01c: 46bd mov sp, r7 800e01e: bd80 pop {r7, pc} 800e020: 24002624 .word 0x24002624 800e024: 24002604 .word 0x24002604 800e028: 2400212c .word 0x2400212c 800e02c: 240025bc .word 0x240025bc 800e030: 24002128 .word 0x24002128 800e034: 24002610 .word 0x24002610 0800e038 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 800e038: b580 push {r7, lr} 800e03a: b084 sub sp, #16 800e03c: af00 add r7, sp, #0 800e03e: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 800e040: 687b ldr r3, [r7, #4] 800e042: 2b00 cmp r3, #0 800e044: d102 bne.n 800e04c 800e046: 4b0e ldr r3, [pc, #56] @ (800e080 ) 800e048: 681b ldr r3, [r3, #0] 800e04a: e000 b.n 800e04e 800e04c: 687b ldr r3, [r7, #4] 800e04e: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 800e050: f000 fcfa bl 800ea48 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 800e054: 68bb ldr r3, [r7, #8] 800e056: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 800e05a: b2db uxtb r3, r3 800e05c: 2b02 cmp r3, #2 800e05e: d106 bne.n 800e06e { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 800e060: 68bb ldr r3, [r7, #8] 800e062: 2200 movs r2, #0 800e064: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 800e068: 2301 movs r3, #1 800e06a: 60fb str r3, [r7, #12] 800e06c: e001 b.n 800e072 } else { xReturn = pdFAIL; 800e06e: 2300 movs r3, #0 800e070: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 800e072: f000 fd1b bl 800eaac return xReturn; 800e076: 68fb ldr r3, [r7, #12] } 800e078: 4618 mov r0, r3 800e07a: 3710 adds r7, #16 800e07c: 46bd mov sp, r7 800e07e: bd80 pop {r7, pc} 800e080: 24002128 .word 0x24002128 0800e084 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 800e084: b580 push {r7, lr} 800e086: b084 sub sp, #16 800e088: af00 add r7, sp, #0 800e08a: 6078 str r0, [r7, #4] 800e08c: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 800e08e: 4b21 ldr r3, [pc, #132] @ (800e114 ) 800e090: 681b ldr r3, [r3, #0] 800e092: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 800e094: 4b20 ldr r3, [pc, #128] @ (800e118 ) 800e096: 681b ldr r3, [r3, #0] 800e098: 3304 adds r3, #4 800e09a: 4618 mov r0, r3 800e09c: f7fd fc9a bl 800b9d4 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 800e0a0: 687b ldr r3, [r7, #4] 800e0a2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e0a6: d10a bne.n 800e0be 800e0a8: 683b ldr r3, [r7, #0] 800e0aa: 2b00 cmp r3, #0 800e0ac: d007 beq.n 800e0be { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800e0ae: 4b1a ldr r3, [pc, #104] @ (800e118 ) 800e0b0: 681b ldr r3, [r3, #0] 800e0b2: 3304 adds r3, #4 800e0b4: 4619 mov r1, r3 800e0b6: 4819 ldr r0, [pc, #100] @ (800e11c ) 800e0b8: f7fd fc2f bl 800b91a /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 800e0bc: e026 b.n 800e10c xTimeToWake = xConstTickCount + xTicksToWait; 800e0be: 68fa ldr r2, [r7, #12] 800e0c0: 687b ldr r3, [r7, #4] 800e0c2: 4413 add r3, r2 800e0c4: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 800e0c6: 4b14 ldr r3, [pc, #80] @ (800e118 ) 800e0c8: 681b ldr r3, [r3, #0] 800e0ca: 68ba ldr r2, [r7, #8] 800e0cc: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 800e0ce: 68ba ldr r2, [r7, #8] 800e0d0: 68fb ldr r3, [r7, #12] 800e0d2: 429a cmp r2, r3 800e0d4: d209 bcs.n 800e0ea vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800e0d6: 4b12 ldr r3, [pc, #72] @ (800e120 ) 800e0d8: 681a ldr r2, [r3, #0] 800e0da: 4b0f ldr r3, [pc, #60] @ (800e118 ) 800e0dc: 681b ldr r3, [r3, #0] 800e0de: 3304 adds r3, #4 800e0e0: 4619 mov r1, r3 800e0e2: 4610 mov r0, r2 800e0e4: f7fd fc3d bl 800b962 } 800e0e8: e010 b.n 800e10c vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 800e0ea: 4b0e ldr r3, [pc, #56] @ (800e124 ) 800e0ec: 681a ldr r2, [r3, #0] 800e0ee: 4b0a ldr r3, [pc, #40] @ (800e118 ) 800e0f0: 681b ldr r3, [r3, #0] 800e0f2: 3304 adds r3, #4 800e0f4: 4619 mov r1, r3 800e0f6: 4610 mov r0, r2 800e0f8: f7fd fc33 bl 800b962 if( xTimeToWake < xNextTaskUnblockTime ) 800e0fc: 4b0a ldr r3, [pc, #40] @ (800e128 ) 800e0fe: 681b ldr r3, [r3, #0] 800e100: 68ba ldr r2, [r7, #8] 800e102: 429a cmp r2, r3 800e104: d202 bcs.n 800e10c xNextTaskUnblockTime = xTimeToWake; 800e106: 4a08 ldr r2, [pc, #32] @ (800e128 ) 800e108: 68bb ldr r3, [r7, #8] 800e10a: 6013 str r3, [r2, #0] } 800e10c: bf00 nop 800e10e: 3710 adds r7, #16 800e110: 46bd mov sp, r7 800e112: bd80 pop {r7, pc} 800e114: 24002600 .word 0x24002600 800e118: 24002128 .word 0x24002128 800e11c: 240025e8 .word 0x240025e8 800e120: 240025b8 .word 0x240025b8 800e124: 240025b4 .word 0x240025b4 800e128: 2400261c .word 0x2400261c 0800e12c : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 800e12c: b580 push {r7, lr} 800e12e: b08a sub sp, #40 @ 0x28 800e130: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 800e132: 2300 movs r3, #0 800e134: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 800e136: f000 fb13 bl 800e760 if( xTimerQueue != NULL ) 800e13a: 4b1d ldr r3, [pc, #116] @ (800e1b0 ) 800e13c: 681b ldr r3, [r3, #0] 800e13e: 2b00 cmp r3, #0 800e140: d021 beq.n 800e186 { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 800e142: 2300 movs r3, #0 800e144: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 800e146: 2300 movs r3, #0 800e148: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 800e14a: 1d3a adds r2, r7, #4 800e14c: f107 0108 add.w r1, r7, #8 800e150: f107 030c add.w r3, r7, #12 800e154: 4618 mov r0, r3 800e156: f7fd fb99 bl 800b88c xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 800e15a: 6879 ldr r1, [r7, #4] 800e15c: 68bb ldr r3, [r7, #8] 800e15e: 68fa ldr r2, [r7, #12] 800e160: 9202 str r2, [sp, #8] 800e162: 9301 str r3, [sp, #4] 800e164: 2302 movs r3, #2 800e166: 9300 str r3, [sp, #0] 800e168: 2300 movs r3, #0 800e16a: 460a mov r2, r1 800e16c: 4911 ldr r1, [pc, #68] @ (800e1b4 ) 800e16e: 4812 ldr r0, [pc, #72] @ (800e1b8 ) 800e170: f7fe fd2f bl 800cbd2 800e174: 4603 mov r3, r0 800e176: 4a11 ldr r2, [pc, #68] @ (800e1bc ) 800e178: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 800e17a: 4b10 ldr r3, [pc, #64] @ (800e1bc ) 800e17c: 681b ldr r3, [r3, #0] 800e17e: 2b00 cmp r3, #0 800e180: d001 beq.n 800e186 { xReturn = pdPASS; 800e182: 2301 movs r3, #1 800e184: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 800e186: 697b ldr r3, [r7, #20] 800e188: 2b00 cmp r3, #0 800e18a: d10b bne.n 800e1a4 __asm volatile 800e18c: f04f 0350 mov.w r3, #80 @ 0x50 800e190: f383 8811 msr BASEPRI, r3 800e194: f3bf 8f6f isb sy 800e198: f3bf 8f4f dsb sy 800e19c: 613b str r3, [r7, #16] } 800e19e: bf00 nop 800e1a0: bf00 nop 800e1a2: e7fd b.n 800e1a0 return xReturn; 800e1a4: 697b ldr r3, [r7, #20] } 800e1a6: 4618 mov r0, r3 800e1a8: 3718 adds r7, #24 800e1aa: 46bd mov sp, r7 800e1ac: bd80 pop {r7, pc} 800e1ae: bf00 nop 800e1b0: 24002658 .word 0x24002658 800e1b4: 0801007c .word 0x0801007c 800e1b8: 0800e2f9 .word 0x0800e2f9 800e1bc: 2400265c .word 0x2400265c 0800e1c0 : } } /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 800e1c0: b580 push {r7, lr} 800e1c2: b08a sub sp, #40 @ 0x28 800e1c4: af00 add r7, sp, #0 800e1c6: 60f8 str r0, [r7, #12] 800e1c8: 60b9 str r1, [r7, #8] 800e1ca: 607a str r2, [r7, #4] 800e1cc: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 800e1ce: 2300 movs r3, #0 800e1d0: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 800e1d2: 68fb ldr r3, [r7, #12] 800e1d4: 2b00 cmp r3, #0 800e1d6: d10b bne.n 800e1f0 __asm volatile 800e1d8: f04f 0350 mov.w r3, #80 @ 0x50 800e1dc: f383 8811 msr BASEPRI, r3 800e1e0: f3bf 8f6f isb sy 800e1e4: f3bf 8f4f dsb sy 800e1e8: 623b str r3, [r7, #32] } 800e1ea: bf00 nop 800e1ec: bf00 nop 800e1ee: e7fd b.n 800e1ec /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 800e1f0: 4b19 ldr r3, [pc, #100] @ (800e258 ) 800e1f2: 681b ldr r3, [r3, #0] 800e1f4: 2b00 cmp r3, #0 800e1f6: d02a beq.n 800e24e { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 800e1f8: 68bb ldr r3, [r7, #8] 800e1fa: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 800e1fc: 687b ldr r3, [r7, #4] 800e1fe: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 800e200: 68fb ldr r3, [r7, #12] 800e202: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 800e204: 68bb ldr r3, [r7, #8] 800e206: 2b05 cmp r3, #5 800e208: dc18 bgt.n 800e23c { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 800e20a: f7ff fb7f bl 800d90c 800e20e: 4603 mov r3, r0 800e210: 2b02 cmp r3, #2 800e212: d109 bne.n 800e228 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 800e214: 4b10 ldr r3, [pc, #64] @ (800e258 ) 800e216: 6818 ldr r0, [r3, #0] 800e218: f107 0110 add.w r1, r7, #16 800e21c: 2300 movs r3, #0 800e21e: 6b3a ldr r2, [r7, #48] @ 0x30 800e220: f7fd fe00 bl 800be24 800e224: 6278 str r0, [r7, #36] @ 0x24 800e226: e012 b.n 800e24e } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 800e228: 4b0b ldr r3, [pc, #44] @ (800e258 ) 800e22a: 6818 ldr r0, [r3, #0] 800e22c: f107 0110 add.w r1, r7, #16 800e230: 2300 movs r3, #0 800e232: 2200 movs r2, #0 800e234: f7fd fdf6 bl 800be24 800e238: 6278 str r0, [r7, #36] @ 0x24 800e23a: e008 b.n 800e24e } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 800e23c: 4b06 ldr r3, [pc, #24] @ (800e258 ) 800e23e: 6818 ldr r0, [r3, #0] 800e240: f107 0110 add.w r1, r7, #16 800e244: 2300 movs r3, #0 800e246: 683a ldr r2, [r7, #0] 800e248: f7fd feee bl 800c028 800e24c: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 800e24e: 6a7b ldr r3, [r7, #36] @ 0x24 } 800e250: 4618 mov r0, r3 800e252: 3728 adds r7, #40 @ 0x28 800e254: 46bd mov sp, r7 800e256: bd80 pop {r7, pc} 800e258: 24002658 .word 0x24002658 0800e25c : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 800e25c: b580 push {r7, lr} 800e25e: b088 sub sp, #32 800e260: af02 add r7, sp, #8 800e262: 6078 str r0, [r7, #4] 800e264: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800e266: 4b23 ldr r3, [pc, #140] @ (800e2f4 ) 800e268: 681b ldr r3, [r3, #0] 800e26a: 68db ldr r3, [r3, #12] 800e26c: 68db ldr r3, [r3, #12] 800e26e: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 800e270: 697b ldr r3, [r7, #20] 800e272: 3304 adds r3, #4 800e274: 4618 mov r0, r3 800e276: f7fd fbad bl 800b9d4 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 800e27a: 697b ldr r3, [r7, #20] 800e27c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e280: f003 0304 and.w r3, r3, #4 800e284: 2b00 cmp r3, #0 800e286: d023 beq.n 800e2d0 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 800e288: 697b ldr r3, [r7, #20] 800e28a: 699a ldr r2, [r3, #24] 800e28c: 687b ldr r3, [r7, #4] 800e28e: 18d1 adds r1, r2, r3 800e290: 687b ldr r3, [r7, #4] 800e292: 683a ldr r2, [r7, #0] 800e294: 6978 ldr r0, [r7, #20] 800e296: f000 f8d5 bl 800e444 800e29a: 4603 mov r3, r0 800e29c: 2b00 cmp r3, #0 800e29e: d020 beq.n 800e2e2 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 800e2a0: 2300 movs r3, #0 800e2a2: 9300 str r3, [sp, #0] 800e2a4: 2300 movs r3, #0 800e2a6: 687a ldr r2, [r7, #4] 800e2a8: 2100 movs r1, #0 800e2aa: 6978 ldr r0, [r7, #20] 800e2ac: f7ff ff88 bl 800e1c0 800e2b0: 6138 str r0, [r7, #16] configASSERT( xResult ); 800e2b2: 693b ldr r3, [r7, #16] 800e2b4: 2b00 cmp r3, #0 800e2b6: d114 bne.n 800e2e2 __asm volatile 800e2b8: f04f 0350 mov.w r3, #80 @ 0x50 800e2bc: f383 8811 msr BASEPRI, r3 800e2c0: f3bf 8f6f isb sy 800e2c4: f3bf 8f4f dsb sy 800e2c8: 60fb str r3, [r7, #12] } 800e2ca: bf00 nop 800e2cc: bf00 nop 800e2ce: e7fd b.n 800e2cc mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 800e2d0: 697b ldr r3, [r7, #20] 800e2d2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e2d6: f023 0301 bic.w r3, r3, #1 800e2da: b2da uxtb r2, r3 800e2dc: 697b ldr r3, [r7, #20] 800e2de: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 800e2e2: 697b ldr r3, [r7, #20] 800e2e4: 6a1b ldr r3, [r3, #32] 800e2e6: 6978 ldr r0, [r7, #20] 800e2e8: 4798 blx r3 } 800e2ea: bf00 nop 800e2ec: 3718 adds r7, #24 800e2ee: 46bd mov sp, r7 800e2f0: bd80 pop {r7, pc} 800e2f2: bf00 nop 800e2f4: 24002650 .word 0x24002650 0800e2f8 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 800e2f8: b580 push {r7, lr} 800e2fa: b084 sub sp, #16 800e2fc: af00 add r7, sp, #0 800e2fe: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 800e300: f107 0308 add.w r3, r7, #8 800e304: 4618 mov r0, r3 800e306: f000 f859 bl 800e3bc 800e30a: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 800e30c: 68bb ldr r3, [r7, #8] 800e30e: 4619 mov r1, r3 800e310: 68f8 ldr r0, [r7, #12] 800e312: f000 f805 bl 800e320 /* Empty the command queue. */ prvProcessReceivedCommands(); 800e316: f000 f8d7 bl 800e4c8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 800e31a: bf00 nop 800e31c: e7f0 b.n 800e300 ... 0800e320 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 800e320: b580 push {r7, lr} 800e322: b084 sub sp, #16 800e324: af00 add r7, sp, #0 800e326: 6078 str r0, [r7, #4] 800e328: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 800e32a: f7fe feb5 bl 800d098 /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 800e32e: f107 0308 add.w r3, r7, #8 800e332: 4618 mov r0, r3 800e334: f000 f866 bl 800e404 800e338: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 800e33a: 68bb ldr r3, [r7, #8] 800e33c: 2b00 cmp r3, #0 800e33e: d130 bne.n 800e3a2 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 800e340: 683b ldr r3, [r7, #0] 800e342: 2b00 cmp r3, #0 800e344: d10a bne.n 800e35c 800e346: 687a ldr r2, [r7, #4] 800e348: 68fb ldr r3, [r7, #12] 800e34a: 429a cmp r2, r3 800e34c: d806 bhi.n 800e35c { ( void ) xTaskResumeAll(); 800e34e: f7fe feb1 bl 800d0b4 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 800e352: 68f9 ldr r1, [r7, #12] 800e354: 6878 ldr r0, [r7, #4] 800e356: f7ff ff81 bl 800e25c else { ( void ) xTaskResumeAll(); } } } 800e35a: e024 b.n 800e3a6 if( xListWasEmpty != pdFALSE ) 800e35c: 683b ldr r3, [r7, #0] 800e35e: 2b00 cmp r3, #0 800e360: d008 beq.n 800e374 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 800e362: 4b13 ldr r3, [pc, #76] @ (800e3b0 ) 800e364: 681b ldr r3, [r3, #0] 800e366: 681b ldr r3, [r3, #0] 800e368: 2b00 cmp r3, #0 800e36a: d101 bne.n 800e370 800e36c: 2301 movs r3, #1 800e36e: e000 b.n 800e372 800e370: 2300 movs r3, #0 800e372: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 800e374: 4b0f ldr r3, [pc, #60] @ (800e3b4 ) 800e376: 6818 ldr r0, [r3, #0] 800e378: 687a ldr r2, [r7, #4] 800e37a: 68fb ldr r3, [r7, #12] 800e37c: 1ad3 subs r3, r2, r3 800e37e: 683a ldr r2, [r7, #0] 800e380: 4619 mov r1, r3 800e382: f7fe fa33 bl 800c7ec if( xTaskResumeAll() == pdFALSE ) 800e386: f7fe fe95 bl 800d0b4 800e38a: 4603 mov r3, r0 800e38c: 2b00 cmp r3, #0 800e38e: d10a bne.n 800e3a6 portYIELD_WITHIN_API(); 800e390: 4b09 ldr r3, [pc, #36] @ (800e3b8 ) 800e392: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800e396: 601a str r2, [r3, #0] 800e398: f3bf 8f4f dsb sy 800e39c: f3bf 8f6f isb sy } 800e3a0: e001 b.n 800e3a6 ( void ) xTaskResumeAll(); 800e3a2: f7fe fe87 bl 800d0b4 } 800e3a6: bf00 nop 800e3a8: 3710 adds r7, #16 800e3aa: 46bd mov sp, r7 800e3ac: bd80 pop {r7, pc} 800e3ae: bf00 nop 800e3b0: 24002654 .word 0x24002654 800e3b4: 24002658 .word 0x24002658 800e3b8: e000ed04 .word 0xe000ed04 0800e3bc : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 800e3bc: b480 push {r7} 800e3be: b085 sub sp, #20 800e3c0: af00 add r7, sp, #0 800e3c2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 800e3c4: 4b0e ldr r3, [pc, #56] @ (800e400 ) 800e3c6: 681b ldr r3, [r3, #0] 800e3c8: 681b ldr r3, [r3, #0] 800e3ca: 2b00 cmp r3, #0 800e3cc: d101 bne.n 800e3d2 800e3ce: 2201 movs r2, #1 800e3d0: e000 b.n 800e3d4 800e3d2: 2200 movs r2, #0 800e3d4: 687b ldr r3, [r7, #4] 800e3d6: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 800e3d8: 687b ldr r3, [r7, #4] 800e3da: 681b ldr r3, [r3, #0] 800e3dc: 2b00 cmp r3, #0 800e3de: d105 bne.n 800e3ec { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 800e3e0: 4b07 ldr r3, [pc, #28] @ (800e400 ) 800e3e2: 681b ldr r3, [r3, #0] 800e3e4: 68db ldr r3, [r3, #12] 800e3e6: 681b ldr r3, [r3, #0] 800e3e8: 60fb str r3, [r7, #12] 800e3ea: e001 b.n 800e3f0 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 800e3ec: 2300 movs r3, #0 800e3ee: 60fb str r3, [r7, #12] } return xNextExpireTime; 800e3f0: 68fb ldr r3, [r7, #12] } 800e3f2: 4618 mov r0, r3 800e3f4: 3714 adds r7, #20 800e3f6: 46bd mov sp, r7 800e3f8: f85d 7b04 ldr.w r7, [sp], #4 800e3fc: 4770 bx lr 800e3fe: bf00 nop 800e400: 24002650 .word 0x24002650 0800e404 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 800e404: b580 push {r7, lr} 800e406: b084 sub sp, #16 800e408: af00 add r7, sp, #0 800e40a: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 800e40c: f7fe fef0 bl 800d1f0 800e410: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 800e412: 4b0b ldr r3, [pc, #44] @ (800e440 ) 800e414: 681b ldr r3, [r3, #0] 800e416: 68fa ldr r2, [r7, #12] 800e418: 429a cmp r2, r3 800e41a: d205 bcs.n 800e428 { prvSwitchTimerLists(); 800e41c: f000 f93a bl 800e694 *pxTimerListsWereSwitched = pdTRUE; 800e420: 687b ldr r3, [r7, #4] 800e422: 2201 movs r2, #1 800e424: 601a str r2, [r3, #0] 800e426: e002 b.n 800e42e } else { *pxTimerListsWereSwitched = pdFALSE; 800e428: 687b ldr r3, [r7, #4] 800e42a: 2200 movs r2, #0 800e42c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 800e42e: 4a04 ldr r2, [pc, #16] @ (800e440 ) 800e430: 68fb ldr r3, [r7, #12] 800e432: 6013 str r3, [r2, #0] return xTimeNow; 800e434: 68fb ldr r3, [r7, #12] } 800e436: 4618 mov r0, r3 800e438: 3710 adds r7, #16 800e43a: 46bd mov sp, r7 800e43c: bd80 pop {r7, pc} 800e43e: bf00 nop 800e440: 24002660 .word 0x24002660 0800e444 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 800e444: b580 push {r7, lr} 800e446: b086 sub sp, #24 800e448: af00 add r7, sp, #0 800e44a: 60f8 str r0, [r7, #12] 800e44c: 60b9 str r1, [r7, #8] 800e44e: 607a str r2, [r7, #4] 800e450: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 800e452: 2300 movs r3, #0 800e454: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 800e456: 68fb ldr r3, [r7, #12] 800e458: 68ba ldr r2, [r7, #8] 800e45a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 800e45c: 68fb ldr r3, [r7, #12] 800e45e: 68fa ldr r2, [r7, #12] 800e460: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 800e462: 68ba ldr r2, [r7, #8] 800e464: 687b ldr r3, [r7, #4] 800e466: 429a cmp r2, r3 800e468: d812 bhi.n 800e490 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 800e46a: 687a ldr r2, [r7, #4] 800e46c: 683b ldr r3, [r7, #0] 800e46e: 1ad2 subs r2, r2, r3 800e470: 68fb ldr r3, [r7, #12] 800e472: 699b ldr r3, [r3, #24] 800e474: 429a cmp r2, r3 800e476: d302 bcc.n 800e47e { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 800e478: 2301 movs r3, #1 800e47a: 617b str r3, [r7, #20] 800e47c: e01b b.n 800e4b6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 800e47e: 4b10 ldr r3, [pc, #64] @ (800e4c0 ) 800e480: 681a ldr r2, [r3, #0] 800e482: 68fb ldr r3, [r7, #12] 800e484: 3304 adds r3, #4 800e486: 4619 mov r1, r3 800e488: 4610 mov r0, r2 800e48a: f7fd fa6a bl 800b962 800e48e: e012 b.n 800e4b6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 800e490: 687a ldr r2, [r7, #4] 800e492: 683b ldr r3, [r7, #0] 800e494: 429a cmp r2, r3 800e496: d206 bcs.n 800e4a6 800e498: 68ba ldr r2, [r7, #8] 800e49a: 683b ldr r3, [r7, #0] 800e49c: 429a cmp r2, r3 800e49e: d302 bcc.n 800e4a6 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 800e4a0: 2301 movs r3, #1 800e4a2: 617b str r3, [r7, #20] 800e4a4: e007 b.n 800e4b6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 800e4a6: 4b07 ldr r3, [pc, #28] @ (800e4c4 ) 800e4a8: 681a ldr r2, [r3, #0] 800e4aa: 68fb ldr r3, [r7, #12] 800e4ac: 3304 adds r3, #4 800e4ae: 4619 mov r1, r3 800e4b0: 4610 mov r0, r2 800e4b2: f7fd fa56 bl 800b962 } } return xProcessTimerNow; 800e4b6: 697b ldr r3, [r7, #20] } 800e4b8: 4618 mov r0, r3 800e4ba: 3718 adds r7, #24 800e4bc: 46bd mov sp, r7 800e4be: bd80 pop {r7, pc} 800e4c0: 24002654 .word 0x24002654 800e4c4: 24002650 .word 0x24002650 0800e4c8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 800e4c8: b580 push {r7, lr} 800e4ca: b08e sub sp, #56 @ 0x38 800e4cc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 800e4ce: e0ce b.n 800e66e { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 800e4d0: 687b ldr r3, [r7, #4] 800e4d2: 2b00 cmp r3, #0 800e4d4: da19 bge.n 800e50a { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 800e4d6: 1d3b adds r3, r7, #4 800e4d8: 3304 adds r3, #4 800e4da: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 800e4dc: 6afb ldr r3, [r7, #44] @ 0x2c 800e4de: 2b00 cmp r3, #0 800e4e0: d10b bne.n 800e4fa __asm volatile 800e4e2: f04f 0350 mov.w r3, #80 @ 0x50 800e4e6: f383 8811 msr BASEPRI, r3 800e4ea: f3bf 8f6f isb sy 800e4ee: f3bf 8f4f dsb sy 800e4f2: 61fb str r3, [r7, #28] } 800e4f4: bf00 nop 800e4f6: bf00 nop 800e4f8: e7fd b.n 800e4f6 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 800e4fa: 6afb ldr r3, [r7, #44] @ 0x2c 800e4fc: 681b ldr r3, [r3, #0] 800e4fe: 6afa ldr r2, [r7, #44] @ 0x2c 800e500: 6850 ldr r0, [r2, #4] 800e502: 6afa ldr r2, [r7, #44] @ 0x2c 800e504: 6892 ldr r2, [r2, #8] 800e506: 4611 mov r1, r2 800e508: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 800e50a: 687b ldr r3, [r7, #4] 800e50c: 2b00 cmp r3, #0 800e50e: f2c0 80ae blt.w 800e66e { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 800e512: 68fb ldr r3, [r7, #12] 800e514: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 800e516: 6abb ldr r3, [r7, #40] @ 0x28 800e518: 695b ldr r3, [r3, #20] 800e51a: 2b00 cmp r3, #0 800e51c: d004 beq.n 800e528 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 800e51e: 6abb ldr r3, [r7, #40] @ 0x28 800e520: 3304 adds r3, #4 800e522: 4618 mov r0, r3 800e524: f7fd fa56 bl 800b9d4 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 800e528: 463b mov r3, r7 800e52a: 4618 mov r0, r3 800e52c: f7ff ff6a bl 800e404 800e530: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 800e532: 687b ldr r3, [r7, #4] 800e534: 2b09 cmp r3, #9 800e536: f200 8097 bhi.w 800e668 800e53a: a201 add r2, pc, #4 @ (adr r2, 800e540 ) 800e53c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800e540: 0800e569 .word 0x0800e569 800e544: 0800e569 .word 0x0800e569 800e548: 0800e569 .word 0x0800e569 800e54c: 0800e5df .word 0x0800e5df 800e550: 0800e5f3 .word 0x0800e5f3 800e554: 0800e63f .word 0x0800e63f 800e558: 0800e569 .word 0x0800e569 800e55c: 0800e569 .word 0x0800e569 800e560: 0800e5df .word 0x0800e5df 800e564: 0800e5f3 .word 0x0800e5f3 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 800e568: 6abb ldr r3, [r7, #40] @ 0x28 800e56a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e56e: f043 0301 orr.w r3, r3, #1 800e572: b2da uxtb r2, r3 800e574: 6abb ldr r3, [r7, #40] @ 0x28 800e576: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 800e57a: 68ba ldr r2, [r7, #8] 800e57c: 6abb ldr r3, [r7, #40] @ 0x28 800e57e: 699b ldr r3, [r3, #24] 800e580: 18d1 adds r1, r2, r3 800e582: 68bb ldr r3, [r7, #8] 800e584: 6a7a ldr r2, [r7, #36] @ 0x24 800e586: 6ab8 ldr r0, [r7, #40] @ 0x28 800e588: f7ff ff5c bl 800e444 800e58c: 4603 mov r3, r0 800e58e: 2b00 cmp r3, #0 800e590: d06c beq.n 800e66c { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 800e592: 6abb ldr r3, [r7, #40] @ 0x28 800e594: 6a1b ldr r3, [r3, #32] 800e596: 6ab8 ldr r0, [r7, #40] @ 0x28 800e598: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 800e59a: 6abb ldr r3, [r7, #40] @ 0x28 800e59c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e5a0: f003 0304 and.w r3, r3, #4 800e5a4: 2b00 cmp r3, #0 800e5a6: d061 beq.n 800e66c { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 800e5a8: 68ba ldr r2, [r7, #8] 800e5aa: 6abb ldr r3, [r7, #40] @ 0x28 800e5ac: 699b ldr r3, [r3, #24] 800e5ae: 441a add r2, r3 800e5b0: 2300 movs r3, #0 800e5b2: 9300 str r3, [sp, #0] 800e5b4: 2300 movs r3, #0 800e5b6: 2100 movs r1, #0 800e5b8: 6ab8 ldr r0, [r7, #40] @ 0x28 800e5ba: f7ff fe01 bl 800e1c0 800e5be: 6238 str r0, [r7, #32] configASSERT( xResult ); 800e5c0: 6a3b ldr r3, [r7, #32] 800e5c2: 2b00 cmp r3, #0 800e5c4: d152 bne.n 800e66c __asm volatile 800e5c6: f04f 0350 mov.w r3, #80 @ 0x50 800e5ca: f383 8811 msr BASEPRI, r3 800e5ce: f3bf 8f6f isb sy 800e5d2: f3bf 8f4f dsb sy 800e5d6: 61bb str r3, [r7, #24] } 800e5d8: bf00 nop 800e5da: bf00 nop 800e5dc: e7fd b.n 800e5da break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 800e5de: 6abb ldr r3, [r7, #40] @ 0x28 800e5e0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e5e4: f023 0301 bic.w r3, r3, #1 800e5e8: b2da uxtb r2, r3 800e5ea: 6abb ldr r3, [r7, #40] @ 0x28 800e5ec: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 800e5f0: e03d b.n 800e66e case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 800e5f2: 6abb ldr r3, [r7, #40] @ 0x28 800e5f4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e5f8: f043 0301 orr.w r3, r3, #1 800e5fc: b2da uxtb r2, r3 800e5fe: 6abb ldr r3, [r7, #40] @ 0x28 800e600: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 800e604: 68ba ldr r2, [r7, #8] 800e606: 6abb ldr r3, [r7, #40] @ 0x28 800e608: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 800e60a: 6abb ldr r3, [r7, #40] @ 0x28 800e60c: 699b ldr r3, [r3, #24] 800e60e: 2b00 cmp r3, #0 800e610: d10b bne.n 800e62a __asm volatile 800e612: f04f 0350 mov.w r3, #80 @ 0x50 800e616: f383 8811 msr BASEPRI, r3 800e61a: f3bf 8f6f isb sy 800e61e: f3bf 8f4f dsb sy 800e622: 617b str r3, [r7, #20] } 800e624: bf00 nop 800e626: bf00 nop 800e628: e7fd b.n 800e626 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 800e62a: 6abb ldr r3, [r7, #40] @ 0x28 800e62c: 699a ldr r2, [r3, #24] 800e62e: 6a7b ldr r3, [r7, #36] @ 0x24 800e630: 18d1 adds r1, r2, r3 800e632: 6a7b ldr r3, [r7, #36] @ 0x24 800e634: 6a7a ldr r2, [r7, #36] @ 0x24 800e636: 6ab8 ldr r0, [r7, #40] @ 0x28 800e638: f7ff ff04 bl 800e444 break; 800e63c: e017 b.n 800e66e #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 800e63e: 6abb ldr r3, [r7, #40] @ 0x28 800e640: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e644: f003 0302 and.w r3, r3, #2 800e648: 2b00 cmp r3, #0 800e64a: d103 bne.n 800e654 { vPortFree( pxTimer ); 800e64c: 6ab8 ldr r0, [r7, #40] @ 0x28 800e64e: f000 fbeb bl 800ee28 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 800e652: e00c b.n 800e66e pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 800e654: 6abb ldr r3, [r7, #40] @ 0x28 800e656: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e65a: f023 0301 bic.w r3, r3, #1 800e65e: b2da uxtb r2, r3 800e660: 6abb ldr r3, [r7, #40] @ 0x28 800e662: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 800e666: e002 b.n 800e66e default : /* Don't expect to get here. */ break; 800e668: bf00 nop 800e66a: e000 b.n 800e66e break; 800e66c: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 800e66e: 4b08 ldr r3, [pc, #32] @ (800e690 ) 800e670: 681b ldr r3, [r3, #0] 800e672: 1d39 adds r1, r7, #4 800e674: 2200 movs r2, #0 800e676: 4618 mov r0, r3 800e678: f7fd fd74 bl 800c164 800e67c: 4603 mov r3, r0 800e67e: 2b00 cmp r3, #0 800e680: f47f af26 bne.w 800e4d0 } } } } 800e684: bf00 nop 800e686: bf00 nop 800e688: 3730 adds r7, #48 @ 0x30 800e68a: 46bd mov sp, r7 800e68c: bd80 pop {r7, pc} 800e68e: bf00 nop 800e690: 24002658 .word 0x24002658 0800e694 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 800e694: b580 push {r7, lr} 800e696: b088 sub sp, #32 800e698: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 800e69a: e049 b.n 800e730 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 800e69c: 4b2e ldr r3, [pc, #184] @ (800e758 ) 800e69e: 681b ldr r3, [r3, #0] 800e6a0: 68db ldr r3, [r3, #12] 800e6a2: 681b ldr r3, [r3, #0] 800e6a4: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800e6a6: 4b2c ldr r3, [pc, #176] @ (800e758 ) 800e6a8: 681b ldr r3, [r3, #0] 800e6aa: 68db ldr r3, [r3, #12] 800e6ac: 68db ldr r3, [r3, #12] 800e6ae: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 800e6b0: 68fb ldr r3, [r7, #12] 800e6b2: 3304 adds r3, #4 800e6b4: 4618 mov r0, r3 800e6b6: f7fd f98d bl 800b9d4 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 800e6ba: 68fb ldr r3, [r7, #12] 800e6bc: 6a1b ldr r3, [r3, #32] 800e6be: 68f8 ldr r0, [r7, #12] 800e6c0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 800e6c2: 68fb ldr r3, [r7, #12] 800e6c4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 800e6c8: f003 0304 and.w r3, r3, #4 800e6cc: 2b00 cmp r3, #0 800e6ce: d02f beq.n 800e730 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 800e6d0: 68fb ldr r3, [r7, #12] 800e6d2: 699b ldr r3, [r3, #24] 800e6d4: 693a ldr r2, [r7, #16] 800e6d6: 4413 add r3, r2 800e6d8: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 800e6da: 68ba ldr r2, [r7, #8] 800e6dc: 693b ldr r3, [r7, #16] 800e6de: 429a cmp r2, r3 800e6e0: d90e bls.n 800e700 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 800e6e2: 68fb ldr r3, [r7, #12] 800e6e4: 68ba ldr r2, [r7, #8] 800e6e6: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 800e6e8: 68fb ldr r3, [r7, #12] 800e6ea: 68fa ldr r2, [r7, #12] 800e6ec: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 800e6ee: 4b1a ldr r3, [pc, #104] @ (800e758 ) 800e6f0: 681a ldr r2, [r3, #0] 800e6f2: 68fb ldr r3, [r7, #12] 800e6f4: 3304 adds r3, #4 800e6f6: 4619 mov r1, r3 800e6f8: 4610 mov r0, r2 800e6fa: f7fd f932 bl 800b962 800e6fe: e017 b.n 800e730 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 800e700: 2300 movs r3, #0 800e702: 9300 str r3, [sp, #0] 800e704: 2300 movs r3, #0 800e706: 693a ldr r2, [r7, #16] 800e708: 2100 movs r1, #0 800e70a: 68f8 ldr r0, [r7, #12] 800e70c: f7ff fd58 bl 800e1c0 800e710: 6078 str r0, [r7, #4] configASSERT( xResult ); 800e712: 687b ldr r3, [r7, #4] 800e714: 2b00 cmp r3, #0 800e716: d10b bne.n 800e730 __asm volatile 800e718: f04f 0350 mov.w r3, #80 @ 0x50 800e71c: f383 8811 msr BASEPRI, r3 800e720: f3bf 8f6f isb sy 800e724: f3bf 8f4f dsb sy 800e728: 603b str r3, [r7, #0] } 800e72a: bf00 nop 800e72c: bf00 nop 800e72e: e7fd b.n 800e72c while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 800e730: 4b09 ldr r3, [pc, #36] @ (800e758 ) 800e732: 681b ldr r3, [r3, #0] 800e734: 681b ldr r3, [r3, #0] 800e736: 2b00 cmp r3, #0 800e738: d1b0 bne.n 800e69c { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 800e73a: 4b07 ldr r3, [pc, #28] @ (800e758 ) 800e73c: 681b ldr r3, [r3, #0] 800e73e: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 800e740: 4b06 ldr r3, [pc, #24] @ (800e75c ) 800e742: 681b ldr r3, [r3, #0] 800e744: 4a04 ldr r2, [pc, #16] @ (800e758 ) 800e746: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 800e748: 4a04 ldr r2, [pc, #16] @ (800e75c ) 800e74a: 697b ldr r3, [r7, #20] 800e74c: 6013 str r3, [r2, #0] } 800e74e: bf00 nop 800e750: 3718 adds r7, #24 800e752: 46bd mov sp, r7 800e754: bd80 pop {r7, pc} 800e756: bf00 nop 800e758: 24002650 .word 0x24002650 800e75c: 24002654 .word 0x24002654 0800e760 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 800e760: b580 push {r7, lr} 800e762: b082 sub sp, #8 800e764: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 800e766: f000 f96f bl 800ea48 { if( xTimerQueue == NULL ) 800e76a: 4b15 ldr r3, [pc, #84] @ (800e7c0 ) 800e76c: 681b ldr r3, [r3, #0] 800e76e: 2b00 cmp r3, #0 800e770: d120 bne.n 800e7b4 { vListInitialise( &xActiveTimerList1 ); 800e772: 4814 ldr r0, [pc, #80] @ (800e7c4 ) 800e774: f7fd f8a4 bl 800b8c0 vListInitialise( &xActiveTimerList2 ); 800e778: 4813 ldr r0, [pc, #76] @ (800e7c8 ) 800e77a: f7fd f8a1 bl 800b8c0 pxCurrentTimerList = &xActiveTimerList1; 800e77e: 4b13 ldr r3, [pc, #76] @ (800e7cc ) 800e780: 4a10 ldr r2, [pc, #64] @ (800e7c4 ) 800e782: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 800e784: 4b12 ldr r3, [pc, #72] @ (800e7d0 ) 800e786: 4a10 ldr r2, [pc, #64] @ (800e7c8 ) 800e788: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 800e78a: 2300 movs r3, #0 800e78c: 9300 str r3, [sp, #0] 800e78e: 4b11 ldr r3, [pc, #68] @ (800e7d4 ) 800e790: 4a11 ldr r2, [pc, #68] @ (800e7d8 ) 800e792: 2110 movs r1, #16 800e794: 200a movs r0, #10 800e796: f7fd f9b1 bl 800bafc 800e79a: 4603 mov r3, r0 800e79c: 4a08 ldr r2, [pc, #32] @ (800e7c0 ) 800e79e: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 800e7a0: 4b07 ldr r3, [pc, #28] @ (800e7c0 ) 800e7a2: 681b ldr r3, [r3, #0] 800e7a4: 2b00 cmp r3, #0 800e7a6: d005 beq.n 800e7b4 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 800e7a8: 4b05 ldr r3, [pc, #20] @ (800e7c0 ) 800e7aa: 681b ldr r3, [r3, #0] 800e7ac: 490b ldr r1, [pc, #44] @ (800e7dc ) 800e7ae: 4618 mov r0, r3 800e7b0: f7fd fff2 bl 800c798 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 800e7b4: f000 f97a bl 800eaac } 800e7b8: bf00 nop 800e7ba: 46bd mov sp, r7 800e7bc: bd80 pop {r7, pc} 800e7be: bf00 nop 800e7c0: 24002658 .word 0x24002658 800e7c4: 24002628 .word 0x24002628 800e7c8: 2400263c .word 0x2400263c 800e7cc: 24002650 .word 0x24002650 800e7d0: 24002654 .word 0x24002654 800e7d4: 24002704 .word 0x24002704 800e7d8: 24002664 .word 0x24002664 800e7dc: 08010084 .word 0x08010084 0800e7e0 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 800e7e0: b480 push {r7} 800e7e2: b085 sub sp, #20 800e7e4: af00 add r7, sp, #0 800e7e6: 60f8 str r0, [r7, #12] 800e7e8: 60b9 str r1, [r7, #8] 800e7ea: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 800e7ec: 68fb ldr r3, [r7, #12] 800e7ee: 3b04 subs r3, #4 800e7f0: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 800e7f2: 68fb ldr r3, [r7, #12] 800e7f4: f04f 7280 mov.w r2, #16777216 @ 0x1000000 800e7f8: 601a str r2, [r3, #0] pxTopOfStack--; 800e7fa: 68fb ldr r3, [r7, #12] 800e7fc: 3b04 subs r3, #4 800e7fe: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 800e800: 68bb ldr r3, [r7, #8] 800e802: f023 0201 bic.w r2, r3, #1 800e806: 68fb ldr r3, [r7, #12] 800e808: 601a str r2, [r3, #0] pxTopOfStack--; 800e80a: 68fb ldr r3, [r7, #12] 800e80c: 3b04 subs r3, #4 800e80e: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 800e810: 4a0c ldr r2, [pc, #48] @ (800e844 ) 800e812: 68fb ldr r3, [r7, #12] 800e814: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 800e816: 68fb ldr r3, [r7, #12] 800e818: 3b14 subs r3, #20 800e81a: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 800e81c: 687a ldr r2, [r7, #4] 800e81e: 68fb ldr r3, [r7, #12] 800e820: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 800e822: 68fb ldr r3, [r7, #12] 800e824: 3b04 subs r3, #4 800e826: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 800e828: 68fb ldr r3, [r7, #12] 800e82a: f06f 0202 mvn.w r2, #2 800e82e: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 800e830: 68fb ldr r3, [r7, #12] 800e832: 3b20 subs r3, #32 800e834: 60fb str r3, [r7, #12] return pxTopOfStack; 800e836: 68fb ldr r3, [r7, #12] } 800e838: 4618 mov r0, r3 800e83a: 3714 adds r7, #20 800e83c: 46bd mov sp, r7 800e83e: f85d 7b04 ldr.w r7, [sp], #4 800e842: 4770 bx lr 800e844: 0800e849 .word 0x0800e849 0800e848 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 800e848: b480 push {r7} 800e84a: b085 sub sp, #20 800e84c: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 800e84e: 2300 movs r3, #0 800e850: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 800e852: 4b13 ldr r3, [pc, #76] @ (800e8a0 ) 800e854: 681b ldr r3, [r3, #0] 800e856: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800e85a: d00b beq.n 800e874 __asm volatile 800e85c: f04f 0350 mov.w r3, #80 @ 0x50 800e860: f383 8811 msr BASEPRI, r3 800e864: f3bf 8f6f isb sy 800e868: f3bf 8f4f dsb sy 800e86c: 60fb str r3, [r7, #12] } 800e86e: bf00 nop 800e870: bf00 nop 800e872: e7fd b.n 800e870 __asm volatile 800e874: f04f 0350 mov.w r3, #80 @ 0x50 800e878: f383 8811 msr BASEPRI, r3 800e87c: f3bf 8f6f isb sy 800e880: f3bf 8f4f dsb sy 800e884: 60bb str r3, [r7, #8] } 800e886: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 800e888: bf00 nop 800e88a: 687b ldr r3, [r7, #4] 800e88c: 2b00 cmp r3, #0 800e88e: d0fc beq.n 800e88a about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 800e890: bf00 nop 800e892: bf00 nop 800e894: 3714 adds r7, #20 800e896: 46bd mov sp, r7 800e898: f85d 7b04 ldr.w r7, [sp], #4 800e89c: 4770 bx lr 800e89e: bf00 nop 800e8a0: 24000010 .word 0x24000010 ... 0800e8b0 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 800e8b0: 4b07 ldr r3, [pc, #28] @ (800e8d0 ) 800e8b2: 6819 ldr r1, [r3, #0] 800e8b4: 6808 ldr r0, [r1, #0] 800e8b6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800e8ba: f380 8809 msr PSP, r0 800e8be: f3bf 8f6f isb sy 800e8c2: f04f 0000 mov.w r0, #0 800e8c6: f380 8811 msr BASEPRI, r0 800e8ca: 4770 bx lr 800e8cc: f3af 8000 nop.w 0800e8d0 : 800e8d0: 24002128 .word 0x24002128 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 800e8d4: bf00 nop 800e8d6: bf00 nop 0800e8d8 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 800e8d8: 4808 ldr r0, [pc, #32] @ (800e8fc ) 800e8da: 6800 ldr r0, [r0, #0] 800e8dc: 6800 ldr r0, [r0, #0] 800e8de: f380 8808 msr MSP, r0 800e8e2: f04f 0000 mov.w r0, #0 800e8e6: f380 8814 msr CONTROL, r0 800e8ea: b662 cpsie i 800e8ec: b661 cpsie f 800e8ee: f3bf 8f4f dsb sy 800e8f2: f3bf 8f6f isb sy 800e8f6: df00 svc 0 800e8f8: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 800e8fa: bf00 nop 800e8fc: e000ed08 .word 0xe000ed08 0800e900 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 800e900: b580 push {r7, lr} 800e902: b086 sub sp, #24 800e904: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 800e906: 4b47 ldr r3, [pc, #284] @ (800ea24 ) 800e908: 681b ldr r3, [r3, #0] 800e90a: 4a47 ldr r2, [pc, #284] @ (800ea28 ) 800e90c: 4293 cmp r3, r2 800e90e: d10b bne.n 800e928 __asm volatile 800e910: f04f 0350 mov.w r3, #80 @ 0x50 800e914: f383 8811 msr BASEPRI, r3 800e918: f3bf 8f6f isb sy 800e91c: f3bf 8f4f dsb sy 800e920: 613b str r3, [r7, #16] } 800e922: bf00 nop 800e924: bf00 nop 800e926: e7fd b.n 800e924 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 800e928: 4b3e ldr r3, [pc, #248] @ (800ea24 ) 800e92a: 681b ldr r3, [r3, #0] 800e92c: 4a3f ldr r2, [pc, #252] @ (800ea2c ) 800e92e: 4293 cmp r3, r2 800e930: d10b bne.n 800e94a __asm volatile 800e932: f04f 0350 mov.w r3, #80 @ 0x50 800e936: f383 8811 msr BASEPRI, r3 800e93a: f3bf 8f6f isb sy 800e93e: f3bf 8f4f dsb sy 800e942: 60fb str r3, [r7, #12] } 800e944: bf00 nop 800e946: bf00 nop 800e948: e7fd b.n 800e946 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 800e94a: 4b39 ldr r3, [pc, #228] @ (800ea30 ) 800e94c: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 800e94e: 697b ldr r3, [r7, #20] 800e950: 781b ldrb r3, [r3, #0] 800e952: b2db uxtb r3, r3 800e954: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 800e956: 697b ldr r3, [r7, #20] 800e958: 22ff movs r2, #255 @ 0xff 800e95a: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 800e95c: 697b ldr r3, [r7, #20] 800e95e: 781b ldrb r3, [r3, #0] 800e960: b2db uxtb r3, r3 800e962: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 800e964: 78fb ldrb r3, [r7, #3] 800e966: b2db uxtb r3, r3 800e968: f003 0350 and.w r3, r3, #80 @ 0x50 800e96c: b2da uxtb r2, r3 800e96e: 4b31 ldr r3, [pc, #196] @ (800ea34 ) 800e970: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 800e972: 4b31 ldr r3, [pc, #196] @ (800ea38 ) 800e974: 2207 movs r2, #7 800e976: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 800e978: e009 b.n 800e98e { ulMaxPRIGROUPValue--; 800e97a: 4b2f ldr r3, [pc, #188] @ (800ea38 ) 800e97c: 681b ldr r3, [r3, #0] 800e97e: 3b01 subs r3, #1 800e980: 4a2d ldr r2, [pc, #180] @ (800ea38 ) 800e982: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 800e984: 78fb ldrb r3, [r7, #3] 800e986: b2db uxtb r3, r3 800e988: 005b lsls r3, r3, #1 800e98a: b2db uxtb r3, r3 800e98c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 800e98e: 78fb ldrb r3, [r7, #3] 800e990: b2db uxtb r3, r3 800e992: f003 0380 and.w r3, r3, #128 @ 0x80 800e996: 2b80 cmp r3, #128 @ 0x80 800e998: d0ef beq.n 800e97a #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 800e99a: 4b27 ldr r3, [pc, #156] @ (800ea38 ) 800e99c: 681b ldr r3, [r3, #0] 800e99e: f1c3 0307 rsb r3, r3, #7 800e9a2: 2b04 cmp r3, #4 800e9a4: d00b beq.n 800e9be __asm volatile 800e9a6: f04f 0350 mov.w r3, #80 @ 0x50 800e9aa: f383 8811 msr BASEPRI, r3 800e9ae: f3bf 8f6f isb sy 800e9b2: f3bf 8f4f dsb sy 800e9b6: 60bb str r3, [r7, #8] } 800e9b8: bf00 nop 800e9ba: bf00 nop 800e9bc: e7fd b.n 800e9ba } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 800e9be: 4b1e ldr r3, [pc, #120] @ (800ea38 ) 800e9c0: 681b ldr r3, [r3, #0] 800e9c2: 021b lsls r3, r3, #8 800e9c4: 4a1c ldr r2, [pc, #112] @ (800ea38 ) 800e9c6: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 800e9c8: 4b1b ldr r3, [pc, #108] @ (800ea38 ) 800e9ca: 681b ldr r3, [r3, #0] 800e9cc: f403 63e0 and.w r3, r3, #1792 @ 0x700 800e9d0: 4a19 ldr r2, [pc, #100] @ (800ea38 ) 800e9d2: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 800e9d4: 687b ldr r3, [r7, #4] 800e9d6: b2da uxtb r2, r3 800e9d8: 697b ldr r3, [r7, #20] 800e9da: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 800e9dc: 4b17 ldr r3, [pc, #92] @ (800ea3c ) 800e9de: 681b ldr r3, [r3, #0] 800e9e0: 4a16 ldr r2, [pc, #88] @ (800ea3c ) 800e9e2: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800e9e6: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 800e9e8: 4b14 ldr r3, [pc, #80] @ (800ea3c ) 800e9ea: 681b ldr r3, [r3, #0] 800e9ec: 4a13 ldr r2, [pc, #76] @ (800ea3c ) 800e9ee: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 800e9f2: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 800e9f4: f000 f8da bl 800ebac /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 800e9f8: 4b11 ldr r3, [pc, #68] @ (800ea40 ) 800e9fa: 2200 movs r2, #0 800e9fc: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 800e9fe: f000 f8f9 bl 800ebf4 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 800ea02: 4b10 ldr r3, [pc, #64] @ (800ea44 ) 800ea04: 681b ldr r3, [r3, #0] 800ea06: 4a0f ldr r2, [pc, #60] @ (800ea44 ) 800ea08: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 800ea0c: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 800ea0e: f7ff ff63 bl 800e8d8 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 800ea12: f7fe fcb7 bl 800d384 prvTaskExitError(); 800ea16: f7ff ff17 bl 800e848 /* Should not get here! */ return 0; 800ea1a: 2300 movs r3, #0 } 800ea1c: 4618 mov r0, r3 800ea1e: 3718 adds r7, #24 800ea20: 46bd mov sp, r7 800ea22: bd80 pop {r7, pc} 800ea24: e000ed00 .word 0xe000ed00 800ea28: 410fc271 .word 0x410fc271 800ea2c: 410fc270 .word 0x410fc270 800ea30: e000e400 .word 0xe000e400 800ea34: 24002754 .word 0x24002754 800ea38: 24002758 .word 0x24002758 800ea3c: e000ed20 .word 0xe000ed20 800ea40: 24000010 .word 0x24000010 800ea44: e000ef34 .word 0xe000ef34 0800ea48 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 800ea48: b480 push {r7} 800ea4a: b083 sub sp, #12 800ea4c: af00 add r7, sp, #0 __asm volatile 800ea4e: f04f 0350 mov.w r3, #80 @ 0x50 800ea52: f383 8811 msr BASEPRI, r3 800ea56: f3bf 8f6f isb sy 800ea5a: f3bf 8f4f dsb sy 800ea5e: 607b str r3, [r7, #4] } 800ea60: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 800ea62: 4b10 ldr r3, [pc, #64] @ (800eaa4 ) 800ea64: 681b ldr r3, [r3, #0] 800ea66: 3301 adds r3, #1 800ea68: 4a0e ldr r2, [pc, #56] @ (800eaa4 ) 800ea6a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 800ea6c: 4b0d ldr r3, [pc, #52] @ (800eaa4 ) 800ea6e: 681b ldr r3, [r3, #0] 800ea70: 2b01 cmp r3, #1 800ea72: d110 bne.n 800ea96 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 800ea74: 4b0c ldr r3, [pc, #48] @ (800eaa8 ) 800ea76: 681b ldr r3, [r3, #0] 800ea78: b2db uxtb r3, r3 800ea7a: 2b00 cmp r3, #0 800ea7c: d00b beq.n 800ea96 __asm volatile 800ea7e: f04f 0350 mov.w r3, #80 @ 0x50 800ea82: f383 8811 msr BASEPRI, r3 800ea86: f3bf 8f6f isb sy 800ea8a: f3bf 8f4f dsb sy 800ea8e: 603b str r3, [r7, #0] } 800ea90: bf00 nop 800ea92: bf00 nop 800ea94: e7fd b.n 800ea92 } } 800ea96: bf00 nop 800ea98: 370c adds r7, #12 800ea9a: 46bd mov sp, r7 800ea9c: f85d 7b04 ldr.w r7, [sp], #4 800eaa0: 4770 bx lr 800eaa2: bf00 nop 800eaa4: 24000010 .word 0x24000010 800eaa8: e000ed04 .word 0xe000ed04 0800eaac : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 800eaac: b480 push {r7} 800eaae: b083 sub sp, #12 800eab0: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 800eab2: 4b12 ldr r3, [pc, #72] @ (800eafc ) 800eab4: 681b ldr r3, [r3, #0] 800eab6: 2b00 cmp r3, #0 800eab8: d10b bne.n 800ead2 __asm volatile 800eaba: f04f 0350 mov.w r3, #80 @ 0x50 800eabe: f383 8811 msr BASEPRI, r3 800eac2: f3bf 8f6f isb sy 800eac6: f3bf 8f4f dsb sy 800eaca: 607b str r3, [r7, #4] } 800eacc: bf00 nop 800eace: bf00 nop 800ead0: e7fd b.n 800eace uxCriticalNesting--; 800ead2: 4b0a ldr r3, [pc, #40] @ (800eafc ) 800ead4: 681b ldr r3, [r3, #0] 800ead6: 3b01 subs r3, #1 800ead8: 4a08 ldr r2, [pc, #32] @ (800eafc ) 800eada: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 800eadc: 4b07 ldr r3, [pc, #28] @ (800eafc ) 800eade: 681b ldr r3, [r3, #0] 800eae0: 2b00 cmp r3, #0 800eae2: d105 bne.n 800eaf0 800eae4: 2300 movs r3, #0 800eae6: 603b str r3, [r7, #0] __asm volatile 800eae8: 683b ldr r3, [r7, #0] 800eaea: f383 8811 msr BASEPRI, r3 } 800eaee: bf00 nop { portENABLE_INTERRUPTS(); } } 800eaf0: bf00 nop 800eaf2: 370c adds r7, #12 800eaf4: 46bd mov sp, r7 800eaf6: f85d 7b04 ldr.w r7, [sp], #4 800eafa: 4770 bx lr 800eafc: 24000010 .word 0x24000010 0800eb00 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 800eb00: f3ef 8009 mrs r0, PSP 800eb04: f3bf 8f6f isb sy 800eb08: 4b15 ldr r3, [pc, #84] @ (800eb60 ) 800eb0a: 681a ldr r2, [r3, #0] 800eb0c: f01e 0f10 tst.w lr, #16 800eb10: bf08 it eq 800eb12: ed20 8a10 vstmdbeq r0!, {s16-s31} 800eb16: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800eb1a: 6010 str r0, [r2, #0] 800eb1c: e92d 0009 stmdb sp!, {r0, r3} 800eb20: f04f 0050 mov.w r0, #80 @ 0x50 800eb24: f380 8811 msr BASEPRI, r0 800eb28: f3bf 8f4f dsb sy 800eb2c: f3bf 8f6f isb sy 800eb30: f7fe fc28 bl 800d384 800eb34: f04f 0000 mov.w r0, #0 800eb38: f380 8811 msr BASEPRI, r0 800eb3c: bc09 pop {r0, r3} 800eb3e: 6819 ldr r1, [r3, #0] 800eb40: 6808 ldr r0, [r1, #0] 800eb42: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800eb46: f01e 0f10 tst.w lr, #16 800eb4a: bf08 it eq 800eb4c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 800eb50: f380 8809 msr PSP, r0 800eb54: f3bf 8f6f isb sy 800eb58: 4770 bx lr 800eb5a: bf00 nop 800eb5c: f3af 8000 nop.w 0800eb60 : 800eb60: 24002128 .word 0x24002128 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 800eb64: bf00 nop 800eb66: bf00 nop 0800eb68 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 800eb68: b580 push {r7, lr} 800eb6a: b082 sub sp, #8 800eb6c: af00 add r7, sp, #0 __asm volatile 800eb6e: f04f 0350 mov.w r3, #80 @ 0x50 800eb72: f383 8811 msr BASEPRI, r3 800eb76: f3bf 8f6f isb sy 800eb7a: f3bf 8f4f dsb sy 800eb7e: 607b str r3, [r7, #4] } 800eb80: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 800eb82: f7fe fb45 bl 800d210 800eb86: 4603 mov r3, r0 800eb88: 2b00 cmp r3, #0 800eb8a: d003 beq.n 800eb94 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 800eb8c: 4b06 ldr r3, [pc, #24] @ (800eba8 ) 800eb8e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800eb92: 601a str r2, [r3, #0] 800eb94: 2300 movs r3, #0 800eb96: 603b str r3, [r7, #0] __asm volatile 800eb98: 683b ldr r3, [r7, #0] 800eb9a: f383 8811 msr BASEPRI, r3 } 800eb9e: bf00 nop } } portENABLE_INTERRUPTS(); } 800eba0: bf00 nop 800eba2: 3708 adds r7, #8 800eba4: 46bd mov sp, r7 800eba6: bd80 pop {r7, pc} 800eba8: e000ed04 .word 0xe000ed04 0800ebac : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 800ebac: b480 push {r7} 800ebae: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 800ebb0: 4b0b ldr r3, [pc, #44] @ (800ebe0 ) 800ebb2: 2200 movs r2, #0 800ebb4: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 800ebb6: 4b0b ldr r3, [pc, #44] @ (800ebe4 ) 800ebb8: 2200 movs r2, #0 800ebba: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 800ebbc: 4b0a ldr r3, [pc, #40] @ (800ebe8 ) 800ebbe: 681b ldr r3, [r3, #0] 800ebc0: 4a0a ldr r2, [pc, #40] @ (800ebec ) 800ebc2: fba2 2303 umull r2, r3, r2, r3 800ebc6: 099b lsrs r3, r3, #6 800ebc8: 4a09 ldr r2, [pc, #36] @ (800ebf0 ) 800ebca: 3b01 subs r3, #1 800ebcc: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 800ebce: 4b04 ldr r3, [pc, #16] @ (800ebe0 ) 800ebd0: 2207 movs r2, #7 800ebd2: 601a str r2, [r3, #0] } 800ebd4: bf00 nop 800ebd6: 46bd mov sp, r7 800ebd8: f85d 7b04 ldr.w r7, [sp], #4 800ebdc: 4770 bx lr 800ebde: bf00 nop 800ebe0: e000e010 .word 0xe000e010 800ebe4: e000e018 .word 0xe000e018 800ebe8: 24000000 .word 0x24000000 800ebec: 10624dd3 .word 0x10624dd3 800ebf0: e000e014 .word 0xe000e014 0800ebf4 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 800ebf4: f8df 000c ldr.w r0, [pc, #12] @ 800ec04 800ebf8: 6801 ldr r1, [r0, #0] 800ebfa: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 800ebfe: 6001 str r1, [r0, #0] 800ec00: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 800ec02: bf00 nop 800ec04: e000ed88 .word 0xe000ed88 0800ec08 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 800ec08: b480 push {r7} 800ec0a: b085 sub sp, #20 800ec0c: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 800ec0e: f3ef 8305 mrs r3, IPSR 800ec12: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 800ec14: 68fb ldr r3, [r7, #12] 800ec16: 2b0f cmp r3, #15 800ec18: d915 bls.n 800ec46 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 800ec1a: 4a18 ldr r2, [pc, #96] @ (800ec7c ) 800ec1c: 68fb ldr r3, [r7, #12] 800ec1e: 4413 add r3, r2 800ec20: 781b ldrb r3, [r3, #0] 800ec22: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 800ec24: 4b16 ldr r3, [pc, #88] @ (800ec80 ) 800ec26: 781b ldrb r3, [r3, #0] 800ec28: 7afa ldrb r2, [r7, #11] 800ec2a: 429a cmp r2, r3 800ec2c: d20b bcs.n 800ec46 __asm volatile 800ec2e: f04f 0350 mov.w r3, #80 @ 0x50 800ec32: f383 8811 msr BASEPRI, r3 800ec36: f3bf 8f6f isb sy 800ec3a: f3bf 8f4f dsb sy 800ec3e: 607b str r3, [r7, #4] } 800ec40: bf00 nop 800ec42: bf00 nop 800ec44: e7fd b.n 800ec42 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 800ec46: 4b0f ldr r3, [pc, #60] @ (800ec84 ) 800ec48: 681b ldr r3, [r3, #0] 800ec4a: f403 62e0 and.w r2, r3, #1792 @ 0x700 800ec4e: 4b0e ldr r3, [pc, #56] @ (800ec88 ) 800ec50: 681b ldr r3, [r3, #0] 800ec52: 429a cmp r2, r3 800ec54: d90b bls.n 800ec6e __asm volatile 800ec56: f04f 0350 mov.w r3, #80 @ 0x50 800ec5a: f383 8811 msr BASEPRI, r3 800ec5e: f3bf 8f6f isb sy 800ec62: f3bf 8f4f dsb sy 800ec66: 603b str r3, [r7, #0] } 800ec68: bf00 nop 800ec6a: bf00 nop 800ec6c: e7fd b.n 800ec6a } 800ec6e: bf00 nop 800ec70: 3714 adds r7, #20 800ec72: 46bd mov sp, r7 800ec74: f85d 7b04 ldr.w r7, [sp], #4 800ec78: 4770 bx lr 800ec7a: bf00 nop 800ec7c: e000e3f0 .word 0xe000e3f0 800ec80: 24002754 .word 0x24002754 800ec84: e000ed0c .word 0xe000ed0c 800ec88: 24002758 .word 0x24002758 0800ec8c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 800ec8c: b580 push {r7, lr} 800ec8e: b08a sub sp, #40 @ 0x28 800ec90: af00 add r7, sp, #0 800ec92: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 800ec94: 2300 movs r3, #0 800ec96: 61fb str r3, [r7, #28] vTaskSuspendAll(); 800ec98: f7fe f9fe bl 800d098 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 800ec9c: 4b5c ldr r3, [pc, #368] @ (800ee10 ) 800ec9e: 681b ldr r3, [r3, #0] 800eca0: 2b00 cmp r3, #0 800eca2: d101 bne.n 800eca8 { prvHeapInit(); 800eca4: f000 f924 bl 800eef0 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 800eca8: 4b5a ldr r3, [pc, #360] @ (800ee14 ) 800ecaa: 681a ldr r2, [r3, #0] 800ecac: 687b ldr r3, [r7, #4] 800ecae: 4013 ands r3, r2 800ecb0: 2b00 cmp r3, #0 800ecb2: f040 8095 bne.w 800ede0 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 800ecb6: 687b ldr r3, [r7, #4] 800ecb8: 2b00 cmp r3, #0 800ecba: d01e beq.n 800ecfa { xWantedSize += xHeapStructSize; 800ecbc: 2208 movs r2, #8 800ecbe: 687b ldr r3, [r7, #4] 800ecc0: 4413 add r3, r2 800ecc2: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 800ecc4: 687b ldr r3, [r7, #4] 800ecc6: f003 0307 and.w r3, r3, #7 800ecca: 2b00 cmp r3, #0 800eccc: d015 beq.n 800ecfa { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 800ecce: 687b ldr r3, [r7, #4] 800ecd0: f023 0307 bic.w r3, r3, #7 800ecd4: 3308 adds r3, #8 800ecd6: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 800ecd8: 687b ldr r3, [r7, #4] 800ecda: f003 0307 and.w r3, r3, #7 800ecde: 2b00 cmp r3, #0 800ece0: d00b beq.n 800ecfa __asm volatile 800ece2: f04f 0350 mov.w r3, #80 @ 0x50 800ece6: f383 8811 msr BASEPRI, r3 800ecea: f3bf 8f6f isb sy 800ecee: f3bf 8f4f dsb sy 800ecf2: 617b str r3, [r7, #20] } 800ecf4: bf00 nop 800ecf6: bf00 nop 800ecf8: e7fd b.n 800ecf6 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 800ecfa: 687b ldr r3, [r7, #4] 800ecfc: 2b00 cmp r3, #0 800ecfe: d06f beq.n 800ede0 800ed00: 4b45 ldr r3, [pc, #276] @ (800ee18 ) 800ed02: 681b ldr r3, [r3, #0] 800ed04: 687a ldr r2, [r7, #4] 800ed06: 429a cmp r2, r3 800ed08: d86a bhi.n 800ede0 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 800ed0a: 4b44 ldr r3, [pc, #272] @ (800ee1c ) 800ed0c: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 800ed0e: 4b43 ldr r3, [pc, #268] @ (800ee1c ) 800ed10: 681b ldr r3, [r3, #0] 800ed12: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 800ed14: e004 b.n 800ed20 { pxPreviousBlock = pxBlock; 800ed16: 6a7b ldr r3, [r7, #36] @ 0x24 800ed18: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 800ed1a: 6a7b ldr r3, [r7, #36] @ 0x24 800ed1c: 681b ldr r3, [r3, #0] 800ed1e: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 800ed20: 6a7b ldr r3, [r7, #36] @ 0x24 800ed22: 685b ldr r3, [r3, #4] 800ed24: 687a ldr r2, [r7, #4] 800ed26: 429a cmp r2, r3 800ed28: d903 bls.n 800ed32 800ed2a: 6a7b ldr r3, [r7, #36] @ 0x24 800ed2c: 681b ldr r3, [r3, #0] 800ed2e: 2b00 cmp r3, #0 800ed30: d1f1 bne.n 800ed16 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 800ed32: 4b37 ldr r3, [pc, #220] @ (800ee10 ) 800ed34: 681b ldr r3, [r3, #0] 800ed36: 6a7a ldr r2, [r7, #36] @ 0x24 800ed38: 429a cmp r2, r3 800ed3a: d051 beq.n 800ede0 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 800ed3c: 6a3b ldr r3, [r7, #32] 800ed3e: 681b ldr r3, [r3, #0] 800ed40: 2208 movs r2, #8 800ed42: 4413 add r3, r2 800ed44: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 800ed46: 6a7b ldr r3, [r7, #36] @ 0x24 800ed48: 681a ldr r2, [r3, #0] 800ed4a: 6a3b ldr r3, [r7, #32] 800ed4c: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 800ed4e: 6a7b ldr r3, [r7, #36] @ 0x24 800ed50: 685a ldr r2, [r3, #4] 800ed52: 687b ldr r3, [r7, #4] 800ed54: 1ad2 subs r2, r2, r3 800ed56: 2308 movs r3, #8 800ed58: 005b lsls r3, r3, #1 800ed5a: 429a cmp r2, r3 800ed5c: d920 bls.n 800eda0 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 800ed5e: 6a7a ldr r2, [r7, #36] @ 0x24 800ed60: 687b ldr r3, [r7, #4] 800ed62: 4413 add r3, r2 800ed64: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 800ed66: 69bb ldr r3, [r7, #24] 800ed68: f003 0307 and.w r3, r3, #7 800ed6c: 2b00 cmp r3, #0 800ed6e: d00b beq.n 800ed88 __asm volatile 800ed70: f04f 0350 mov.w r3, #80 @ 0x50 800ed74: f383 8811 msr BASEPRI, r3 800ed78: f3bf 8f6f isb sy 800ed7c: f3bf 8f4f dsb sy 800ed80: 613b str r3, [r7, #16] } 800ed82: bf00 nop 800ed84: bf00 nop 800ed86: e7fd b.n 800ed84 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 800ed88: 6a7b ldr r3, [r7, #36] @ 0x24 800ed8a: 685a ldr r2, [r3, #4] 800ed8c: 687b ldr r3, [r7, #4] 800ed8e: 1ad2 subs r2, r2, r3 800ed90: 69bb ldr r3, [r7, #24] 800ed92: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 800ed94: 6a7b ldr r3, [r7, #36] @ 0x24 800ed96: 687a ldr r2, [r7, #4] 800ed98: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 800ed9a: 69b8 ldr r0, [r7, #24] 800ed9c: f000 f90a bl 800efb4 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 800eda0: 4b1d ldr r3, [pc, #116] @ (800ee18 ) 800eda2: 681a ldr r2, [r3, #0] 800eda4: 6a7b ldr r3, [r7, #36] @ 0x24 800eda6: 685b ldr r3, [r3, #4] 800eda8: 1ad3 subs r3, r2, r3 800edaa: 4a1b ldr r2, [pc, #108] @ (800ee18 ) 800edac: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 800edae: 4b1a ldr r3, [pc, #104] @ (800ee18 ) 800edb0: 681a ldr r2, [r3, #0] 800edb2: 4b1b ldr r3, [pc, #108] @ (800ee20 ) 800edb4: 681b ldr r3, [r3, #0] 800edb6: 429a cmp r2, r3 800edb8: d203 bcs.n 800edc2 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 800edba: 4b17 ldr r3, [pc, #92] @ (800ee18 ) 800edbc: 681b ldr r3, [r3, #0] 800edbe: 4a18 ldr r2, [pc, #96] @ (800ee20 ) 800edc0: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 800edc2: 6a7b ldr r3, [r7, #36] @ 0x24 800edc4: 685a ldr r2, [r3, #4] 800edc6: 4b13 ldr r3, [pc, #76] @ (800ee14 ) 800edc8: 681b ldr r3, [r3, #0] 800edca: 431a orrs r2, r3 800edcc: 6a7b ldr r3, [r7, #36] @ 0x24 800edce: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 800edd0: 6a7b ldr r3, [r7, #36] @ 0x24 800edd2: 2200 movs r2, #0 800edd4: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 800edd6: 4b13 ldr r3, [pc, #76] @ (800ee24 ) 800edd8: 681b ldr r3, [r3, #0] 800edda: 3301 adds r3, #1 800eddc: 4a11 ldr r2, [pc, #68] @ (800ee24 ) 800edde: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 800ede0: f7fe f968 bl 800d0b4 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 800ede4: 69fb ldr r3, [r7, #28] 800ede6: f003 0307 and.w r3, r3, #7 800edea: 2b00 cmp r3, #0 800edec: d00b beq.n 800ee06 __asm volatile 800edee: f04f 0350 mov.w r3, #80 @ 0x50 800edf2: f383 8811 msr BASEPRI, r3 800edf6: f3bf 8f6f isb sy 800edfa: f3bf 8f4f dsb sy 800edfe: 60fb str r3, [r7, #12] } 800ee00: bf00 nop 800ee02: bf00 nop 800ee04: e7fd b.n 800ee02 return pvReturn; 800ee06: 69fb ldr r3, [r7, #28] } 800ee08: 4618 mov r0, r3 800ee0a: 3728 adds r7, #40 @ 0x28 800ee0c: 46bd mov sp, r7 800ee0e: bd80 pop {r7, pc} 800ee10: 24012764 .word 0x24012764 800ee14: 24012778 .word 0x24012778 800ee18: 24012768 .word 0x24012768 800ee1c: 2401275c .word 0x2401275c 800ee20: 2401276c .word 0x2401276c 800ee24: 24012770 .word 0x24012770 0800ee28 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 800ee28: b580 push {r7, lr} 800ee2a: b086 sub sp, #24 800ee2c: af00 add r7, sp, #0 800ee2e: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 800ee30: 687b ldr r3, [r7, #4] 800ee32: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 800ee34: 687b ldr r3, [r7, #4] 800ee36: 2b00 cmp r3, #0 800ee38: d04f beq.n 800eeda { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 800ee3a: 2308 movs r3, #8 800ee3c: 425b negs r3, r3 800ee3e: 697a ldr r2, [r7, #20] 800ee40: 4413 add r3, r2 800ee42: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 800ee44: 697b ldr r3, [r7, #20] 800ee46: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 800ee48: 693b ldr r3, [r7, #16] 800ee4a: 685a ldr r2, [r3, #4] 800ee4c: 4b25 ldr r3, [pc, #148] @ (800eee4 ) 800ee4e: 681b ldr r3, [r3, #0] 800ee50: 4013 ands r3, r2 800ee52: 2b00 cmp r3, #0 800ee54: d10b bne.n 800ee6e __asm volatile 800ee56: f04f 0350 mov.w r3, #80 @ 0x50 800ee5a: f383 8811 msr BASEPRI, r3 800ee5e: f3bf 8f6f isb sy 800ee62: f3bf 8f4f dsb sy 800ee66: 60fb str r3, [r7, #12] } 800ee68: bf00 nop 800ee6a: bf00 nop 800ee6c: e7fd b.n 800ee6a configASSERT( pxLink->pxNextFreeBlock == NULL ); 800ee6e: 693b ldr r3, [r7, #16] 800ee70: 681b ldr r3, [r3, #0] 800ee72: 2b00 cmp r3, #0 800ee74: d00b beq.n 800ee8e __asm volatile 800ee76: f04f 0350 mov.w r3, #80 @ 0x50 800ee7a: f383 8811 msr BASEPRI, r3 800ee7e: f3bf 8f6f isb sy 800ee82: f3bf 8f4f dsb sy 800ee86: 60bb str r3, [r7, #8] } 800ee88: bf00 nop 800ee8a: bf00 nop 800ee8c: e7fd b.n 800ee8a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 800ee8e: 693b ldr r3, [r7, #16] 800ee90: 685a ldr r2, [r3, #4] 800ee92: 4b14 ldr r3, [pc, #80] @ (800eee4 ) 800ee94: 681b ldr r3, [r3, #0] 800ee96: 4013 ands r3, r2 800ee98: 2b00 cmp r3, #0 800ee9a: d01e beq.n 800eeda { if( pxLink->pxNextFreeBlock == NULL ) 800ee9c: 693b ldr r3, [r7, #16] 800ee9e: 681b ldr r3, [r3, #0] 800eea0: 2b00 cmp r3, #0 800eea2: d11a bne.n 800eeda { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 800eea4: 693b ldr r3, [r7, #16] 800eea6: 685a ldr r2, [r3, #4] 800eea8: 4b0e ldr r3, [pc, #56] @ (800eee4 ) 800eeaa: 681b ldr r3, [r3, #0] 800eeac: 43db mvns r3, r3 800eeae: 401a ands r2, r3 800eeb0: 693b ldr r3, [r7, #16] 800eeb2: 605a str r2, [r3, #4] vTaskSuspendAll(); 800eeb4: f7fe f8f0 bl 800d098 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 800eeb8: 693b ldr r3, [r7, #16] 800eeba: 685a ldr r2, [r3, #4] 800eebc: 4b0a ldr r3, [pc, #40] @ (800eee8 ) 800eebe: 681b ldr r3, [r3, #0] 800eec0: 4413 add r3, r2 800eec2: 4a09 ldr r2, [pc, #36] @ (800eee8 ) 800eec4: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 800eec6: 6938 ldr r0, [r7, #16] 800eec8: f000 f874 bl 800efb4 xNumberOfSuccessfulFrees++; 800eecc: 4b07 ldr r3, [pc, #28] @ (800eeec ) 800eece: 681b ldr r3, [r3, #0] 800eed0: 3301 adds r3, #1 800eed2: 4a06 ldr r2, [pc, #24] @ (800eeec ) 800eed4: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 800eed6: f7fe f8ed bl 800d0b4 else { mtCOVERAGE_TEST_MARKER(); } } } 800eeda: bf00 nop 800eedc: 3718 adds r7, #24 800eede: 46bd mov sp, r7 800eee0: bd80 pop {r7, pc} 800eee2: bf00 nop 800eee4: 24012778 .word 0x24012778 800eee8: 24012768 .word 0x24012768 800eeec: 24012774 .word 0x24012774 0800eef0 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 800eef0: b480 push {r7} 800eef2: b085 sub sp, #20 800eef4: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 800eef6: f44f 3380 mov.w r3, #65536 @ 0x10000 800eefa: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 800eefc: 4b27 ldr r3, [pc, #156] @ (800ef9c ) 800eefe: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 800ef00: 68fb ldr r3, [r7, #12] 800ef02: f003 0307 and.w r3, r3, #7 800ef06: 2b00 cmp r3, #0 800ef08: d00c beq.n 800ef24 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 800ef0a: 68fb ldr r3, [r7, #12] 800ef0c: 3307 adds r3, #7 800ef0e: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 800ef10: 68fb ldr r3, [r7, #12] 800ef12: f023 0307 bic.w r3, r3, #7 800ef16: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 800ef18: 68ba ldr r2, [r7, #8] 800ef1a: 68fb ldr r3, [r7, #12] 800ef1c: 1ad3 subs r3, r2, r3 800ef1e: 4a1f ldr r2, [pc, #124] @ (800ef9c ) 800ef20: 4413 add r3, r2 800ef22: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 800ef24: 68fb ldr r3, [r7, #12] 800ef26: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 800ef28: 4a1d ldr r2, [pc, #116] @ (800efa0 ) 800ef2a: 687b ldr r3, [r7, #4] 800ef2c: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 800ef2e: 4b1c ldr r3, [pc, #112] @ (800efa0 ) 800ef30: 2200 movs r2, #0 800ef32: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 800ef34: 687b ldr r3, [r7, #4] 800ef36: 68ba ldr r2, [r7, #8] 800ef38: 4413 add r3, r2 800ef3a: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 800ef3c: 2208 movs r2, #8 800ef3e: 68fb ldr r3, [r7, #12] 800ef40: 1a9b subs r3, r3, r2 800ef42: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 800ef44: 68fb ldr r3, [r7, #12] 800ef46: f023 0307 bic.w r3, r3, #7 800ef4a: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 800ef4c: 68fb ldr r3, [r7, #12] 800ef4e: 4a15 ldr r2, [pc, #84] @ (800efa4 ) 800ef50: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 800ef52: 4b14 ldr r3, [pc, #80] @ (800efa4 ) 800ef54: 681b ldr r3, [r3, #0] 800ef56: 2200 movs r2, #0 800ef58: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 800ef5a: 4b12 ldr r3, [pc, #72] @ (800efa4 ) 800ef5c: 681b ldr r3, [r3, #0] 800ef5e: 2200 movs r2, #0 800ef60: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 800ef62: 687b ldr r3, [r7, #4] 800ef64: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 800ef66: 683b ldr r3, [r7, #0] 800ef68: 68fa ldr r2, [r7, #12] 800ef6a: 1ad2 subs r2, r2, r3 800ef6c: 683b ldr r3, [r7, #0] 800ef6e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 800ef70: 4b0c ldr r3, [pc, #48] @ (800efa4 ) 800ef72: 681a ldr r2, [r3, #0] 800ef74: 683b ldr r3, [r7, #0] 800ef76: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 800ef78: 683b ldr r3, [r7, #0] 800ef7a: 685b ldr r3, [r3, #4] 800ef7c: 4a0a ldr r2, [pc, #40] @ (800efa8 ) 800ef7e: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 800ef80: 683b ldr r3, [r7, #0] 800ef82: 685b ldr r3, [r3, #4] 800ef84: 4a09 ldr r2, [pc, #36] @ (800efac ) 800ef86: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 800ef88: 4b09 ldr r3, [pc, #36] @ (800efb0 ) 800ef8a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 800ef8e: 601a str r2, [r3, #0] } 800ef90: bf00 nop 800ef92: 3714 adds r7, #20 800ef94: 46bd mov sp, r7 800ef96: f85d 7b04 ldr.w r7, [sp], #4 800ef9a: 4770 bx lr 800ef9c: 2400275c .word 0x2400275c 800efa0: 2401275c .word 0x2401275c 800efa4: 24012764 .word 0x24012764 800efa8: 2401276c .word 0x2401276c 800efac: 24012768 .word 0x24012768 800efb0: 24012778 .word 0x24012778 0800efb4 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 800efb4: b480 push {r7} 800efb6: b085 sub sp, #20 800efb8: af00 add r7, sp, #0 800efba: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 800efbc: 4b28 ldr r3, [pc, #160] @ (800f060 ) 800efbe: 60fb str r3, [r7, #12] 800efc0: e002 b.n 800efc8 800efc2: 68fb ldr r3, [r7, #12] 800efc4: 681b ldr r3, [r3, #0] 800efc6: 60fb str r3, [r7, #12] 800efc8: 68fb ldr r3, [r7, #12] 800efca: 681b ldr r3, [r3, #0] 800efcc: 687a ldr r2, [r7, #4] 800efce: 429a cmp r2, r3 800efd0: d8f7 bhi.n 800efc2 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 800efd2: 68fb ldr r3, [r7, #12] 800efd4: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 800efd6: 68fb ldr r3, [r7, #12] 800efd8: 685b ldr r3, [r3, #4] 800efda: 68ba ldr r2, [r7, #8] 800efdc: 4413 add r3, r2 800efde: 687a ldr r2, [r7, #4] 800efe0: 429a cmp r2, r3 800efe2: d108 bne.n 800eff6 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 800efe4: 68fb ldr r3, [r7, #12] 800efe6: 685a ldr r2, [r3, #4] 800efe8: 687b ldr r3, [r7, #4] 800efea: 685b ldr r3, [r3, #4] 800efec: 441a add r2, r3 800efee: 68fb ldr r3, [r7, #12] 800eff0: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 800eff2: 68fb ldr r3, [r7, #12] 800eff4: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 800eff6: 687b ldr r3, [r7, #4] 800eff8: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 800effa: 687b ldr r3, [r7, #4] 800effc: 685b ldr r3, [r3, #4] 800effe: 68ba ldr r2, [r7, #8] 800f000: 441a add r2, r3 800f002: 68fb ldr r3, [r7, #12] 800f004: 681b ldr r3, [r3, #0] 800f006: 429a cmp r2, r3 800f008: d118 bne.n 800f03c { if( pxIterator->pxNextFreeBlock != pxEnd ) 800f00a: 68fb ldr r3, [r7, #12] 800f00c: 681a ldr r2, [r3, #0] 800f00e: 4b15 ldr r3, [pc, #84] @ (800f064 ) 800f010: 681b ldr r3, [r3, #0] 800f012: 429a cmp r2, r3 800f014: d00d beq.n 800f032 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 800f016: 687b ldr r3, [r7, #4] 800f018: 685a ldr r2, [r3, #4] 800f01a: 68fb ldr r3, [r7, #12] 800f01c: 681b ldr r3, [r3, #0] 800f01e: 685b ldr r3, [r3, #4] 800f020: 441a add r2, r3 800f022: 687b ldr r3, [r7, #4] 800f024: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 800f026: 68fb ldr r3, [r7, #12] 800f028: 681b ldr r3, [r3, #0] 800f02a: 681a ldr r2, [r3, #0] 800f02c: 687b ldr r3, [r7, #4] 800f02e: 601a str r2, [r3, #0] 800f030: e008 b.n 800f044 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 800f032: 4b0c ldr r3, [pc, #48] @ (800f064 ) 800f034: 681a ldr r2, [r3, #0] 800f036: 687b ldr r3, [r7, #4] 800f038: 601a str r2, [r3, #0] 800f03a: e003 b.n 800f044 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 800f03c: 68fb ldr r3, [r7, #12] 800f03e: 681a ldr r2, [r3, #0] 800f040: 687b ldr r3, [r7, #4] 800f042: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 800f044: 68fa ldr r2, [r7, #12] 800f046: 687b ldr r3, [r7, #4] 800f048: 429a cmp r2, r3 800f04a: d002 beq.n 800f052 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 800f04c: 68fb ldr r3, [r7, #12] 800f04e: 687a ldr r2, [r7, #4] 800f050: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 800f052: bf00 nop 800f054: 3714 adds r7, #20 800f056: 46bd mov sp, r7 800f058: f85d 7b04 ldr.w r7, [sp], #4 800f05c: 4770 bx lr 800f05e: bf00 nop 800f060: 2401275c .word 0x2401275c 800f064: 24012764 .word 0x24012764 0800f068 : 800f068: 2300 movs r3, #0 800f06a: b510 push {r4, lr} 800f06c: 4604 mov r4, r0 800f06e: e9c0 3300 strd r3, r3, [r0] 800f072: e9c0 3304 strd r3, r3, [r0, #16] 800f076: 6083 str r3, [r0, #8] 800f078: 8181 strh r1, [r0, #12] 800f07a: 6643 str r3, [r0, #100] @ 0x64 800f07c: 81c2 strh r2, [r0, #14] 800f07e: 6183 str r3, [r0, #24] 800f080: 4619 mov r1, r3 800f082: 2208 movs r2, #8 800f084: 305c adds r0, #92 @ 0x5c 800f086: f000 f906 bl 800f296 800f08a: 4b0d ldr r3, [pc, #52] @ (800f0c0 ) 800f08c: 6263 str r3, [r4, #36] @ 0x24 800f08e: 4b0d ldr r3, [pc, #52] @ (800f0c4 ) 800f090: 62a3 str r3, [r4, #40] @ 0x28 800f092: 4b0d ldr r3, [pc, #52] @ (800f0c8 ) 800f094: 62e3 str r3, [r4, #44] @ 0x2c 800f096: 4b0d ldr r3, [pc, #52] @ (800f0cc ) 800f098: 6323 str r3, [r4, #48] @ 0x30 800f09a: 4b0d ldr r3, [pc, #52] @ (800f0d0 ) 800f09c: 6224 str r4, [r4, #32] 800f09e: 429c cmp r4, r3 800f0a0: d006 beq.n 800f0b0 800f0a2: f103 0268 add.w r2, r3, #104 @ 0x68 800f0a6: 4294 cmp r4, r2 800f0a8: d002 beq.n 800f0b0 800f0aa: 33d0 adds r3, #208 @ 0xd0 800f0ac: 429c cmp r4, r3 800f0ae: d105 bne.n 800f0bc 800f0b0: f104 0058 add.w r0, r4, #88 @ 0x58 800f0b4: e8bd 4010 ldmia.w sp!, {r4, lr} 800f0b8: f000 b9bc b.w 800f434 <__retarget_lock_init_recursive> 800f0bc: bd10 pop {r4, pc} 800f0be: bf00 nop 800f0c0: 0800f211 .word 0x0800f211 800f0c4: 0800f233 .word 0x0800f233 800f0c8: 0800f26b .word 0x0800f26b 800f0cc: 0800f28f .word 0x0800f28f 800f0d0: 2401277c .word 0x2401277c 0800f0d4 : 800f0d4: 4a02 ldr r2, [pc, #8] @ (800f0e0 ) 800f0d6: 4903 ldr r1, [pc, #12] @ (800f0e4 ) 800f0d8: 4803 ldr r0, [pc, #12] @ (800f0e8 ) 800f0da: f000 b869 b.w 800f1b0 <_fwalk_sglue> 800f0de: bf00 nop 800f0e0: 24000014 .word 0x24000014 800f0e4: 0800fcf1 .word 0x0800fcf1 800f0e8: 24000024 .word 0x24000024 0800f0ec : 800f0ec: 6841 ldr r1, [r0, #4] 800f0ee: 4b0c ldr r3, [pc, #48] @ (800f120 ) 800f0f0: 4299 cmp r1, r3 800f0f2: b510 push {r4, lr} 800f0f4: 4604 mov r4, r0 800f0f6: d001 beq.n 800f0fc 800f0f8: f000 fdfa bl 800fcf0 <_fflush_r> 800f0fc: 68a1 ldr r1, [r4, #8] 800f0fe: 4b09 ldr r3, [pc, #36] @ (800f124 ) 800f100: 4299 cmp r1, r3 800f102: d002 beq.n 800f10a 800f104: 4620 mov r0, r4 800f106: f000 fdf3 bl 800fcf0 <_fflush_r> 800f10a: 68e1 ldr r1, [r4, #12] 800f10c: 4b06 ldr r3, [pc, #24] @ (800f128 ) 800f10e: 4299 cmp r1, r3 800f110: d004 beq.n 800f11c 800f112: 4620 mov r0, r4 800f114: e8bd 4010 ldmia.w sp!, {r4, lr} 800f118: f000 bdea b.w 800fcf0 <_fflush_r> 800f11c: bd10 pop {r4, pc} 800f11e: bf00 nop 800f120: 2401277c .word 0x2401277c 800f124: 240127e4 .word 0x240127e4 800f128: 2401284c .word 0x2401284c 0800f12c : 800f12c: b510 push {r4, lr} 800f12e: 4b0b ldr r3, [pc, #44] @ (800f15c ) 800f130: 4c0b ldr r4, [pc, #44] @ (800f160 ) 800f132: 4a0c ldr r2, [pc, #48] @ (800f164 ) 800f134: 601a str r2, [r3, #0] 800f136: 4620 mov r0, r4 800f138: 2200 movs r2, #0 800f13a: 2104 movs r1, #4 800f13c: f7ff ff94 bl 800f068 800f140: f104 0068 add.w r0, r4, #104 @ 0x68 800f144: 2201 movs r2, #1 800f146: 2109 movs r1, #9 800f148: f7ff ff8e bl 800f068 800f14c: f104 00d0 add.w r0, r4, #208 @ 0xd0 800f150: 2202 movs r2, #2 800f152: e8bd 4010 ldmia.w sp!, {r4, lr} 800f156: 2112 movs r1, #18 800f158: f7ff bf86 b.w 800f068 800f15c: 240128b4 .word 0x240128b4 800f160: 2401277c .word 0x2401277c 800f164: 0800f0d5 .word 0x0800f0d5 0800f168 <__sfp_lock_acquire>: 800f168: 4801 ldr r0, [pc, #4] @ (800f170 <__sfp_lock_acquire+0x8>) 800f16a: f000 b964 b.w 800f436 <__retarget_lock_acquire_recursive> 800f16e: bf00 nop 800f170: 240128bd .word 0x240128bd 0800f174 <__sfp_lock_release>: 800f174: 4801 ldr r0, [pc, #4] @ (800f17c <__sfp_lock_release+0x8>) 800f176: f000 b95f b.w 800f438 <__retarget_lock_release_recursive> 800f17a: bf00 nop 800f17c: 240128bd .word 0x240128bd 0800f180 <__sinit>: 800f180: b510 push {r4, lr} 800f182: 4604 mov r4, r0 800f184: f7ff fff0 bl 800f168 <__sfp_lock_acquire> 800f188: 6a23 ldr r3, [r4, #32] 800f18a: b11b cbz r3, 800f194 <__sinit+0x14> 800f18c: e8bd 4010 ldmia.w sp!, {r4, lr} 800f190: f7ff bff0 b.w 800f174 <__sfp_lock_release> 800f194: 4b04 ldr r3, [pc, #16] @ (800f1a8 <__sinit+0x28>) 800f196: 6223 str r3, [r4, #32] 800f198: 4b04 ldr r3, [pc, #16] @ (800f1ac <__sinit+0x2c>) 800f19a: 681b ldr r3, [r3, #0] 800f19c: 2b00 cmp r3, #0 800f19e: d1f5 bne.n 800f18c <__sinit+0xc> 800f1a0: f7ff ffc4 bl 800f12c 800f1a4: e7f2 b.n 800f18c <__sinit+0xc> 800f1a6: bf00 nop 800f1a8: 0800f0ed .word 0x0800f0ed 800f1ac: 240128b4 .word 0x240128b4 0800f1b0 <_fwalk_sglue>: 800f1b0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800f1b4: 4607 mov r7, r0 800f1b6: 4688 mov r8, r1 800f1b8: 4614 mov r4, r2 800f1ba: 2600 movs r6, #0 800f1bc: e9d4 9501 ldrd r9, r5, [r4, #4] 800f1c0: f1b9 0901 subs.w r9, r9, #1 800f1c4: d505 bpl.n 800f1d2 <_fwalk_sglue+0x22> 800f1c6: 6824 ldr r4, [r4, #0] 800f1c8: 2c00 cmp r4, #0 800f1ca: d1f7 bne.n 800f1bc <_fwalk_sglue+0xc> 800f1cc: 4630 mov r0, r6 800f1ce: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800f1d2: 89ab ldrh r3, [r5, #12] 800f1d4: 2b01 cmp r3, #1 800f1d6: d907 bls.n 800f1e8 <_fwalk_sglue+0x38> 800f1d8: f9b5 300e ldrsh.w r3, [r5, #14] 800f1dc: 3301 adds r3, #1 800f1de: d003 beq.n 800f1e8 <_fwalk_sglue+0x38> 800f1e0: 4629 mov r1, r5 800f1e2: 4638 mov r0, r7 800f1e4: 47c0 blx r8 800f1e6: 4306 orrs r6, r0 800f1e8: 3568 adds r5, #104 @ 0x68 800f1ea: e7e9 b.n 800f1c0 <_fwalk_sglue+0x10> 0800f1ec : 800f1ec: b40f push {r0, r1, r2, r3} 800f1ee: b507 push {r0, r1, r2, lr} 800f1f0: 4906 ldr r1, [pc, #24] @ (800f20c ) 800f1f2: ab04 add r3, sp, #16 800f1f4: 6808 ldr r0, [r1, #0] 800f1f6: f853 2b04 ldr.w r2, [r3], #4 800f1fa: 6881 ldr r1, [r0, #8] 800f1fc: 9301 str r3, [sp, #4] 800f1fe: f000 fa4d bl 800f69c <_vfiprintf_r> 800f202: b003 add sp, #12 800f204: f85d eb04 ldr.w lr, [sp], #4 800f208: b004 add sp, #16 800f20a: 4770 bx lr 800f20c: 24000020 .word 0x24000020 0800f210 <__sread>: 800f210: b510 push {r4, lr} 800f212: 460c mov r4, r1 800f214: f9b1 100e ldrsh.w r1, [r1, #14] 800f218: f000 f8be bl 800f398 <_read_r> 800f21c: 2800 cmp r0, #0 800f21e: bfab itete ge 800f220: 6d63 ldrge r3, [r4, #84] @ 0x54 800f222: 89a3 ldrhlt r3, [r4, #12] 800f224: 181b addge r3, r3, r0 800f226: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 800f22a: bfac ite ge 800f22c: 6563 strge r3, [r4, #84] @ 0x54 800f22e: 81a3 strhlt r3, [r4, #12] 800f230: bd10 pop {r4, pc} 0800f232 <__swrite>: 800f232: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800f236: 461f mov r7, r3 800f238: 898b ldrh r3, [r1, #12] 800f23a: 05db lsls r3, r3, #23 800f23c: 4605 mov r5, r0 800f23e: 460c mov r4, r1 800f240: 4616 mov r6, r2 800f242: d505 bpl.n 800f250 <__swrite+0x1e> 800f244: f9b1 100e ldrsh.w r1, [r1, #14] 800f248: 2302 movs r3, #2 800f24a: 2200 movs r2, #0 800f24c: f000 f892 bl 800f374 <_lseek_r> 800f250: 89a3 ldrh r3, [r4, #12] 800f252: f9b4 100e ldrsh.w r1, [r4, #14] 800f256: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800f25a: 81a3 strh r3, [r4, #12] 800f25c: 4632 mov r2, r6 800f25e: 463b mov r3, r7 800f260: 4628 mov r0, r5 800f262: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 800f266: f000 b8a9 b.w 800f3bc <_write_r> 0800f26a <__sseek>: 800f26a: b510 push {r4, lr} 800f26c: 460c mov r4, r1 800f26e: f9b1 100e ldrsh.w r1, [r1, #14] 800f272: f000 f87f bl 800f374 <_lseek_r> 800f276: 1c43 adds r3, r0, #1 800f278: 89a3 ldrh r3, [r4, #12] 800f27a: bf15 itete ne 800f27c: 6560 strne r0, [r4, #84] @ 0x54 800f27e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 800f282: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 800f286: 81a3 strheq r3, [r4, #12] 800f288: bf18 it ne 800f28a: 81a3 strhne r3, [r4, #12] 800f28c: bd10 pop {r4, pc} 0800f28e <__sclose>: 800f28e: f9b1 100e ldrsh.w r1, [r1, #14] 800f292: f000 b809 b.w 800f2a8 <_close_r> 0800f296 : 800f296: 4402 add r2, r0 800f298: 4603 mov r3, r0 800f29a: 4293 cmp r3, r2 800f29c: d100 bne.n 800f2a0 800f29e: 4770 bx lr 800f2a0: f803 1b01 strb.w r1, [r3], #1 800f2a4: e7f9 b.n 800f29a ... 0800f2a8 <_close_r>: 800f2a8: b538 push {r3, r4, r5, lr} 800f2aa: 4d06 ldr r5, [pc, #24] @ (800f2c4 <_close_r+0x1c>) 800f2ac: 2300 movs r3, #0 800f2ae: 4604 mov r4, r0 800f2b0: 4608 mov r0, r1 800f2b2: 602b str r3, [r5, #0] 800f2b4: f7f2 fb69 bl 800198a <_close> 800f2b8: 1c43 adds r3, r0, #1 800f2ba: d102 bne.n 800f2c2 <_close_r+0x1a> 800f2bc: 682b ldr r3, [r5, #0] 800f2be: b103 cbz r3, 800f2c2 <_close_r+0x1a> 800f2c0: 6023 str r3, [r4, #0] 800f2c2: bd38 pop {r3, r4, r5, pc} 800f2c4: 240128b8 .word 0x240128b8 0800f2c8 <_reclaim_reent>: 800f2c8: 4b29 ldr r3, [pc, #164] @ (800f370 <_reclaim_reent+0xa8>) 800f2ca: 681b ldr r3, [r3, #0] 800f2cc: 4283 cmp r3, r0 800f2ce: b570 push {r4, r5, r6, lr} 800f2d0: 4604 mov r4, r0 800f2d2: d04b beq.n 800f36c <_reclaim_reent+0xa4> 800f2d4: 69c3 ldr r3, [r0, #28] 800f2d6: b1ab cbz r3, 800f304 <_reclaim_reent+0x3c> 800f2d8: 68db ldr r3, [r3, #12] 800f2da: b16b cbz r3, 800f2f8 <_reclaim_reent+0x30> 800f2dc: 2500 movs r5, #0 800f2de: 69e3 ldr r3, [r4, #28] 800f2e0: 68db ldr r3, [r3, #12] 800f2e2: 5959 ldr r1, [r3, r5] 800f2e4: 2900 cmp r1, #0 800f2e6: d13b bne.n 800f360 <_reclaim_reent+0x98> 800f2e8: 3504 adds r5, #4 800f2ea: 2d80 cmp r5, #128 @ 0x80 800f2ec: d1f7 bne.n 800f2de <_reclaim_reent+0x16> 800f2ee: 69e3 ldr r3, [r4, #28] 800f2f0: 4620 mov r0, r4 800f2f2: 68d9 ldr r1, [r3, #12] 800f2f4: f000 f8b0 bl 800f458 <_free_r> 800f2f8: 69e3 ldr r3, [r4, #28] 800f2fa: 6819 ldr r1, [r3, #0] 800f2fc: b111 cbz r1, 800f304 <_reclaim_reent+0x3c> 800f2fe: 4620 mov r0, r4 800f300: f000 f8aa bl 800f458 <_free_r> 800f304: 6961 ldr r1, [r4, #20] 800f306: b111 cbz r1, 800f30e <_reclaim_reent+0x46> 800f308: 4620 mov r0, r4 800f30a: f000 f8a5 bl 800f458 <_free_r> 800f30e: 69e1 ldr r1, [r4, #28] 800f310: b111 cbz r1, 800f318 <_reclaim_reent+0x50> 800f312: 4620 mov r0, r4 800f314: f000 f8a0 bl 800f458 <_free_r> 800f318: 6b21 ldr r1, [r4, #48] @ 0x30 800f31a: b111 cbz r1, 800f322 <_reclaim_reent+0x5a> 800f31c: 4620 mov r0, r4 800f31e: f000 f89b bl 800f458 <_free_r> 800f322: 6b61 ldr r1, [r4, #52] @ 0x34 800f324: b111 cbz r1, 800f32c <_reclaim_reent+0x64> 800f326: 4620 mov r0, r4 800f328: f000 f896 bl 800f458 <_free_r> 800f32c: 6ba1 ldr r1, [r4, #56] @ 0x38 800f32e: b111 cbz r1, 800f336 <_reclaim_reent+0x6e> 800f330: 4620 mov r0, r4 800f332: f000 f891 bl 800f458 <_free_r> 800f336: 6ca1 ldr r1, [r4, #72] @ 0x48 800f338: b111 cbz r1, 800f340 <_reclaim_reent+0x78> 800f33a: 4620 mov r0, r4 800f33c: f000 f88c bl 800f458 <_free_r> 800f340: 6c61 ldr r1, [r4, #68] @ 0x44 800f342: b111 cbz r1, 800f34a <_reclaim_reent+0x82> 800f344: 4620 mov r0, r4 800f346: f000 f887 bl 800f458 <_free_r> 800f34a: 6ae1 ldr r1, [r4, #44] @ 0x2c 800f34c: b111 cbz r1, 800f354 <_reclaim_reent+0x8c> 800f34e: 4620 mov r0, r4 800f350: f000 f882 bl 800f458 <_free_r> 800f354: 6a23 ldr r3, [r4, #32] 800f356: b14b cbz r3, 800f36c <_reclaim_reent+0xa4> 800f358: 4620 mov r0, r4 800f35a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 800f35e: 4718 bx r3 800f360: 680e ldr r6, [r1, #0] 800f362: 4620 mov r0, r4 800f364: f000 f878 bl 800f458 <_free_r> 800f368: 4631 mov r1, r6 800f36a: e7bb b.n 800f2e4 <_reclaim_reent+0x1c> 800f36c: bd70 pop {r4, r5, r6, pc} 800f36e: bf00 nop 800f370: 24000020 .word 0x24000020 0800f374 <_lseek_r>: 800f374: b538 push {r3, r4, r5, lr} 800f376: 4d07 ldr r5, [pc, #28] @ (800f394 <_lseek_r+0x20>) 800f378: 4604 mov r4, r0 800f37a: 4608 mov r0, r1 800f37c: 4611 mov r1, r2 800f37e: 2200 movs r2, #0 800f380: 602a str r2, [r5, #0] 800f382: 461a mov r2, r3 800f384: f7f2 fb28 bl 80019d8 <_lseek> 800f388: 1c43 adds r3, r0, #1 800f38a: d102 bne.n 800f392 <_lseek_r+0x1e> 800f38c: 682b ldr r3, [r5, #0] 800f38e: b103 cbz r3, 800f392 <_lseek_r+0x1e> 800f390: 6023 str r3, [r4, #0] 800f392: bd38 pop {r3, r4, r5, pc} 800f394: 240128b8 .word 0x240128b8 0800f398 <_read_r>: 800f398: b538 push {r3, r4, r5, lr} 800f39a: 4d07 ldr r5, [pc, #28] @ (800f3b8 <_read_r+0x20>) 800f39c: 4604 mov r4, r0 800f39e: 4608 mov r0, r1 800f3a0: 4611 mov r1, r2 800f3a2: 2200 movs r2, #0 800f3a4: 602a str r2, [r5, #0] 800f3a6: 461a mov r2, r3 800f3a8: f7f2 fab6 bl 8001918 <_read> 800f3ac: 1c43 adds r3, r0, #1 800f3ae: d102 bne.n 800f3b6 <_read_r+0x1e> 800f3b0: 682b ldr r3, [r5, #0] 800f3b2: b103 cbz r3, 800f3b6 <_read_r+0x1e> 800f3b4: 6023 str r3, [r4, #0] 800f3b6: bd38 pop {r3, r4, r5, pc} 800f3b8: 240128b8 .word 0x240128b8 0800f3bc <_write_r>: 800f3bc: b538 push {r3, r4, r5, lr} 800f3be: 4d07 ldr r5, [pc, #28] @ (800f3dc <_write_r+0x20>) 800f3c0: 4604 mov r4, r0 800f3c2: 4608 mov r0, r1 800f3c4: 4611 mov r1, r2 800f3c6: 2200 movs r2, #0 800f3c8: 602a str r2, [r5, #0] 800f3ca: 461a mov r2, r3 800f3cc: f7f2 fac1 bl 8001952 <_write> 800f3d0: 1c43 adds r3, r0, #1 800f3d2: d102 bne.n 800f3da <_write_r+0x1e> 800f3d4: 682b ldr r3, [r5, #0] 800f3d6: b103 cbz r3, 800f3da <_write_r+0x1e> 800f3d8: 6023 str r3, [r4, #0] 800f3da: bd38 pop {r3, r4, r5, pc} 800f3dc: 240128b8 .word 0x240128b8 0800f3e0 <__errno>: 800f3e0: 4b01 ldr r3, [pc, #4] @ (800f3e8 <__errno+0x8>) 800f3e2: 6818 ldr r0, [r3, #0] 800f3e4: 4770 bx lr 800f3e6: bf00 nop 800f3e8: 24000020 .word 0x24000020 0800f3ec <__libc_init_array>: 800f3ec: b570 push {r4, r5, r6, lr} 800f3ee: 4d0d ldr r5, [pc, #52] @ (800f424 <__libc_init_array+0x38>) 800f3f0: 4c0d ldr r4, [pc, #52] @ (800f428 <__libc_init_array+0x3c>) 800f3f2: 1b64 subs r4, r4, r5 800f3f4: 10a4 asrs r4, r4, #2 800f3f6: 2600 movs r6, #0 800f3f8: 42a6 cmp r6, r4 800f3fa: d109 bne.n 800f410 <__libc_init_array+0x24> 800f3fc: 4d0b ldr r5, [pc, #44] @ (800f42c <__libc_init_array+0x40>) 800f3fe: 4c0c ldr r4, [pc, #48] @ (800f430 <__libc_init_array+0x44>) 800f400: f000 fdc6 bl 800ff90 <_init> 800f404: 1b64 subs r4, r4, r5 800f406: 10a4 asrs r4, r4, #2 800f408: 2600 movs r6, #0 800f40a: 42a6 cmp r6, r4 800f40c: d105 bne.n 800f41a <__libc_init_array+0x2e> 800f40e: bd70 pop {r4, r5, r6, pc} 800f410: f855 3b04 ldr.w r3, [r5], #4 800f414: 4798 blx r3 800f416: 3601 adds r6, #1 800f418: e7ee b.n 800f3f8 <__libc_init_array+0xc> 800f41a: f855 3b04 ldr.w r3, [r5], #4 800f41e: 4798 blx r3 800f420: 3601 adds r6, #1 800f422: e7f2 b.n 800f40a <__libc_init_array+0x1e> 800f424: 0801012c .word 0x0801012c 800f428: 0801012c .word 0x0801012c 800f42c: 0801012c .word 0x0801012c 800f430: 08010130 .word 0x08010130 0800f434 <__retarget_lock_init_recursive>: 800f434: 4770 bx lr 0800f436 <__retarget_lock_acquire_recursive>: 800f436: 4770 bx lr 0800f438 <__retarget_lock_release_recursive>: 800f438: 4770 bx lr 0800f43a : 800f43a: 440a add r2, r1 800f43c: 4291 cmp r1, r2 800f43e: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 800f442: d100 bne.n 800f446 800f444: 4770 bx lr 800f446: b510 push {r4, lr} 800f448: f811 4b01 ldrb.w r4, [r1], #1 800f44c: f803 4f01 strb.w r4, [r3, #1]! 800f450: 4291 cmp r1, r2 800f452: d1f9 bne.n 800f448 800f454: bd10 pop {r4, pc} ... 0800f458 <_free_r>: 800f458: b538 push {r3, r4, r5, lr} 800f45a: 4605 mov r5, r0 800f45c: 2900 cmp r1, #0 800f45e: d041 beq.n 800f4e4 <_free_r+0x8c> 800f460: f851 3c04 ldr.w r3, [r1, #-4] 800f464: 1f0c subs r4, r1, #4 800f466: 2b00 cmp r3, #0 800f468: bfb8 it lt 800f46a: 18e4 addlt r4, r4, r3 800f46c: f000 f8e0 bl 800f630 <__malloc_lock> 800f470: 4a1d ldr r2, [pc, #116] @ (800f4e8 <_free_r+0x90>) 800f472: 6813 ldr r3, [r2, #0] 800f474: b933 cbnz r3, 800f484 <_free_r+0x2c> 800f476: 6063 str r3, [r4, #4] 800f478: 6014 str r4, [r2, #0] 800f47a: 4628 mov r0, r5 800f47c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 800f480: f000 b8dc b.w 800f63c <__malloc_unlock> 800f484: 42a3 cmp r3, r4 800f486: d908 bls.n 800f49a <_free_r+0x42> 800f488: 6820 ldr r0, [r4, #0] 800f48a: 1821 adds r1, r4, r0 800f48c: 428b cmp r3, r1 800f48e: bf01 itttt eq 800f490: 6819 ldreq r1, [r3, #0] 800f492: 685b ldreq r3, [r3, #4] 800f494: 1809 addeq r1, r1, r0 800f496: 6021 streq r1, [r4, #0] 800f498: e7ed b.n 800f476 <_free_r+0x1e> 800f49a: 461a mov r2, r3 800f49c: 685b ldr r3, [r3, #4] 800f49e: b10b cbz r3, 800f4a4 <_free_r+0x4c> 800f4a0: 42a3 cmp r3, r4 800f4a2: d9fa bls.n 800f49a <_free_r+0x42> 800f4a4: 6811 ldr r1, [r2, #0] 800f4a6: 1850 adds r0, r2, r1 800f4a8: 42a0 cmp r0, r4 800f4aa: d10b bne.n 800f4c4 <_free_r+0x6c> 800f4ac: 6820 ldr r0, [r4, #0] 800f4ae: 4401 add r1, r0 800f4b0: 1850 adds r0, r2, r1 800f4b2: 4283 cmp r3, r0 800f4b4: 6011 str r1, [r2, #0] 800f4b6: d1e0 bne.n 800f47a <_free_r+0x22> 800f4b8: 6818 ldr r0, [r3, #0] 800f4ba: 685b ldr r3, [r3, #4] 800f4bc: 6053 str r3, [r2, #4] 800f4be: 4408 add r0, r1 800f4c0: 6010 str r0, [r2, #0] 800f4c2: e7da b.n 800f47a <_free_r+0x22> 800f4c4: d902 bls.n 800f4cc <_free_r+0x74> 800f4c6: 230c movs r3, #12 800f4c8: 602b str r3, [r5, #0] 800f4ca: e7d6 b.n 800f47a <_free_r+0x22> 800f4cc: 6820 ldr r0, [r4, #0] 800f4ce: 1821 adds r1, r4, r0 800f4d0: 428b cmp r3, r1 800f4d2: bf04 itt eq 800f4d4: 6819 ldreq r1, [r3, #0] 800f4d6: 685b ldreq r3, [r3, #4] 800f4d8: 6063 str r3, [r4, #4] 800f4da: bf04 itt eq 800f4dc: 1809 addeq r1, r1, r0 800f4de: 6021 streq r1, [r4, #0] 800f4e0: 6054 str r4, [r2, #4] 800f4e2: e7ca b.n 800f47a <_free_r+0x22> 800f4e4: bd38 pop {r3, r4, r5, pc} 800f4e6: bf00 nop 800f4e8: 240128c4 .word 0x240128c4 0800f4ec : 800f4ec: b570 push {r4, r5, r6, lr} 800f4ee: 4e0f ldr r6, [pc, #60] @ (800f52c ) 800f4f0: 460c mov r4, r1 800f4f2: 6831 ldr r1, [r6, #0] 800f4f4: 4605 mov r5, r0 800f4f6: b911 cbnz r1, 800f4fe 800f4f8: f000 fcb6 bl 800fe68 <_sbrk_r> 800f4fc: 6030 str r0, [r6, #0] 800f4fe: 4621 mov r1, r4 800f500: 4628 mov r0, r5 800f502: f000 fcb1 bl 800fe68 <_sbrk_r> 800f506: 1c43 adds r3, r0, #1 800f508: d103 bne.n 800f512 800f50a: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 800f50e: 4620 mov r0, r4 800f510: bd70 pop {r4, r5, r6, pc} 800f512: 1cc4 adds r4, r0, #3 800f514: f024 0403 bic.w r4, r4, #3 800f518: 42a0 cmp r0, r4 800f51a: d0f8 beq.n 800f50e 800f51c: 1a21 subs r1, r4, r0 800f51e: 4628 mov r0, r5 800f520: f000 fca2 bl 800fe68 <_sbrk_r> 800f524: 3001 adds r0, #1 800f526: d1f2 bne.n 800f50e 800f528: e7ef b.n 800f50a 800f52a: bf00 nop 800f52c: 240128c0 .word 0x240128c0 0800f530 <_malloc_r>: 800f530: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 800f534: 1ccd adds r5, r1, #3 800f536: f025 0503 bic.w r5, r5, #3 800f53a: 3508 adds r5, #8 800f53c: 2d0c cmp r5, #12 800f53e: bf38 it cc 800f540: 250c movcc r5, #12 800f542: 2d00 cmp r5, #0 800f544: 4606 mov r6, r0 800f546: db01 blt.n 800f54c <_malloc_r+0x1c> 800f548: 42a9 cmp r1, r5 800f54a: d904 bls.n 800f556 <_malloc_r+0x26> 800f54c: 230c movs r3, #12 800f54e: 6033 str r3, [r6, #0] 800f550: 2000 movs r0, #0 800f552: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 800f556: f8df 80d4 ldr.w r8, [pc, #212] @ 800f62c <_malloc_r+0xfc> 800f55a: f000 f869 bl 800f630 <__malloc_lock> 800f55e: f8d8 3000 ldr.w r3, [r8] 800f562: 461c mov r4, r3 800f564: bb44 cbnz r4, 800f5b8 <_malloc_r+0x88> 800f566: 4629 mov r1, r5 800f568: 4630 mov r0, r6 800f56a: f7ff ffbf bl 800f4ec 800f56e: 1c43 adds r3, r0, #1 800f570: 4604 mov r4, r0 800f572: d158 bne.n 800f626 <_malloc_r+0xf6> 800f574: f8d8 4000 ldr.w r4, [r8] 800f578: 4627 mov r7, r4 800f57a: 2f00 cmp r7, #0 800f57c: d143 bne.n 800f606 <_malloc_r+0xd6> 800f57e: 2c00 cmp r4, #0 800f580: d04b beq.n 800f61a <_malloc_r+0xea> 800f582: 6823 ldr r3, [r4, #0] 800f584: 4639 mov r1, r7 800f586: 4630 mov r0, r6 800f588: eb04 0903 add.w r9, r4, r3 800f58c: f000 fc6c bl 800fe68 <_sbrk_r> 800f590: 4581 cmp r9, r0 800f592: d142 bne.n 800f61a <_malloc_r+0xea> 800f594: 6821 ldr r1, [r4, #0] 800f596: 1a6d subs r5, r5, r1 800f598: 4629 mov r1, r5 800f59a: 4630 mov r0, r6 800f59c: f7ff ffa6 bl 800f4ec 800f5a0: 3001 adds r0, #1 800f5a2: d03a beq.n 800f61a <_malloc_r+0xea> 800f5a4: 6823 ldr r3, [r4, #0] 800f5a6: 442b add r3, r5 800f5a8: 6023 str r3, [r4, #0] 800f5aa: f8d8 3000 ldr.w r3, [r8] 800f5ae: 685a ldr r2, [r3, #4] 800f5b0: bb62 cbnz r2, 800f60c <_malloc_r+0xdc> 800f5b2: f8c8 7000 str.w r7, [r8] 800f5b6: e00f b.n 800f5d8 <_malloc_r+0xa8> 800f5b8: 6822 ldr r2, [r4, #0] 800f5ba: 1b52 subs r2, r2, r5 800f5bc: d420 bmi.n 800f600 <_malloc_r+0xd0> 800f5be: 2a0b cmp r2, #11 800f5c0: d917 bls.n 800f5f2 <_malloc_r+0xc2> 800f5c2: 1961 adds r1, r4, r5 800f5c4: 42a3 cmp r3, r4 800f5c6: 6025 str r5, [r4, #0] 800f5c8: bf18 it ne 800f5ca: 6059 strne r1, [r3, #4] 800f5cc: 6863 ldr r3, [r4, #4] 800f5ce: bf08 it eq 800f5d0: f8c8 1000 streq.w r1, [r8] 800f5d4: 5162 str r2, [r4, r5] 800f5d6: 604b str r3, [r1, #4] 800f5d8: 4630 mov r0, r6 800f5da: f000 f82f bl 800f63c <__malloc_unlock> 800f5de: f104 000b add.w r0, r4, #11 800f5e2: 1d23 adds r3, r4, #4 800f5e4: f020 0007 bic.w r0, r0, #7 800f5e8: 1ac2 subs r2, r0, r3 800f5ea: bf1c itt ne 800f5ec: 1a1b subne r3, r3, r0 800f5ee: 50a3 strne r3, [r4, r2] 800f5f0: e7af b.n 800f552 <_malloc_r+0x22> 800f5f2: 6862 ldr r2, [r4, #4] 800f5f4: 42a3 cmp r3, r4 800f5f6: bf0c ite eq 800f5f8: f8c8 2000 streq.w r2, [r8] 800f5fc: 605a strne r2, [r3, #4] 800f5fe: e7eb b.n 800f5d8 <_malloc_r+0xa8> 800f600: 4623 mov r3, r4 800f602: 6864 ldr r4, [r4, #4] 800f604: e7ae b.n 800f564 <_malloc_r+0x34> 800f606: 463c mov r4, r7 800f608: 687f ldr r7, [r7, #4] 800f60a: e7b6 b.n 800f57a <_malloc_r+0x4a> 800f60c: 461a mov r2, r3 800f60e: 685b ldr r3, [r3, #4] 800f610: 42a3 cmp r3, r4 800f612: d1fb bne.n 800f60c <_malloc_r+0xdc> 800f614: 2300 movs r3, #0 800f616: 6053 str r3, [r2, #4] 800f618: e7de b.n 800f5d8 <_malloc_r+0xa8> 800f61a: 230c movs r3, #12 800f61c: 6033 str r3, [r6, #0] 800f61e: 4630 mov r0, r6 800f620: f000 f80c bl 800f63c <__malloc_unlock> 800f624: e794 b.n 800f550 <_malloc_r+0x20> 800f626: 6005 str r5, [r0, #0] 800f628: e7d6 b.n 800f5d8 <_malloc_r+0xa8> 800f62a: bf00 nop 800f62c: 240128c4 .word 0x240128c4 0800f630 <__malloc_lock>: 800f630: 4801 ldr r0, [pc, #4] @ (800f638 <__malloc_lock+0x8>) 800f632: f7ff bf00 b.w 800f436 <__retarget_lock_acquire_recursive> 800f636: bf00 nop 800f638: 240128bc .word 0x240128bc 0800f63c <__malloc_unlock>: 800f63c: 4801 ldr r0, [pc, #4] @ (800f644 <__malloc_unlock+0x8>) 800f63e: f7ff befb b.w 800f438 <__retarget_lock_release_recursive> 800f642: bf00 nop 800f644: 240128bc .word 0x240128bc 0800f648 <__sfputc_r>: 800f648: 6893 ldr r3, [r2, #8] 800f64a: 3b01 subs r3, #1 800f64c: 2b00 cmp r3, #0 800f64e: b410 push {r4} 800f650: 6093 str r3, [r2, #8] 800f652: da08 bge.n 800f666 <__sfputc_r+0x1e> 800f654: 6994 ldr r4, [r2, #24] 800f656: 42a3 cmp r3, r4 800f658: db01 blt.n 800f65e <__sfputc_r+0x16> 800f65a: 290a cmp r1, #10 800f65c: d103 bne.n 800f666 <__sfputc_r+0x1e> 800f65e: f85d 4b04 ldr.w r4, [sp], #4 800f662: f000 bb6d b.w 800fd40 <__swbuf_r> 800f666: 6813 ldr r3, [r2, #0] 800f668: 1c58 adds r0, r3, #1 800f66a: 6010 str r0, [r2, #0] 800f66c: 7019 strb r1, [r3, #0] 800f66e: 4608 mov r0, r1 800f670: f85d 4b04 ldr.w r4, [sp], #4 800f674: 4770 bx lr 0800f676 <__sfputs_r>: 800f676: b5f8 push {r3, r4, r5, r6, r7, lr} 800f678: 4606 mov r6, r0 800f67a: 460f mov r7, r1 800f67c: 4614 mov r4, r2 800f67e: 18d5 adds r5, r2, r3 800f680: 42ac cmp r4, r5 800f682: d101 bne.n 800f688 <__sfputs_r+0x12> 800f684: 2000 movs r0, #0 800f686: e007 b.n 800f698 <__sfputs_r+0x22> 800f688: f814 1b01 ldrb.w r1, [r4], #1 800f68c: 463a mov r2, r7 800f68e: 4630 mov r0, r6 800f690: f7ff ffda bl 800f648 <__sfputc_r> 800f694: 1c43 adds r3, r0, #1 800f696: d1f3 bne.n 800f680 <__sfputs_r+0xa> 800f698: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 0800f69c <_vfiprintf_r>: 800f69c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800f6a0: 460d mov r5, r1 800f6a2: b09d sub sp, #116 @ 0x74 800f6a4: 4614 mov r4, r2 800f6a6: 4698 mov r8, r3 800f6a8: 4606 mov r6, r0 800f6aa: b118 cbz r0, 800f6b4 <_vfiprintf_r+0x18> 800f6ac: 6a03 ldr r3, [r0, #32] 800f6ae: b90b cbnz r3, 800f6b4 <_vfiprintf_r+0x18> 800f6b0: f7ff fd66 bl 800f180 <__sinit> 800f6b4: 6e6b ldr r3, [r5, #100] @ 0x64 800f6b6: 07d9 lsls r1, r3, #31 800f6b8: d405 bmi.n 800f6c6 <_vfiprintf_r+0x2a> 800f6ba: 89ab ldrh r3, [r5, #12] 800f6bc: 059a lsls r2, r3, #22 800f6be: d402 bmi.n 800f6c6 <_vfiprintf_r+0x2a> 800f6c0: 6da8 ldr r0, [r5, #88] @ 0x58 800f6c2: f7ff feb8 bl 800f436 <__retarget_lock_acquire_recursive> 800f6c6: 89ab ldrh r3, [r5, #12] 800f6c8: 071b lsls r3, r3, #28 800f6ca: d501 bpl.n 800f6d0 <_vfiprintf_r+0x34> 800f6cc: 692b ldr r3, [r5, #16] 800f6ce: b99b cbnz r3, 800f6f8 <_vfiprintf_r+0x5c> 800f6d0: 4629 mov r1, r5 800f6d2: 4630 mov r0, r6 800f6d4: f000 fb72 bl 800fdbc <__swsetup_r> 800f6d8: b170 cbz r0, 800f6f8 <_vfiprintf_r+0x5c> 800f6da: 6e6b ldr r3, [r5, #100] @ 0x64 800f6dc: 07dc lsls r4, r3, #31 800f6de: d504 bpl.n 800f6ea <_vfiprintf_r+0x4e> 800f6e0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800f6e4: b01d add sp, #116 @ 0x74 800f6e6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 800f6ea: 89ab ldrh r3, [r5, #12] 800f6ec: 0598 lsls r0, r3, #22 800f6ee: d4f7 bmi.n 800f6e0 <_vfiprintf_r+0x44> 800f6f0: 6da8 ldr r0, [r5, #88] @ 0x58 800f6f2: f7ff fea1 bl 800f438 <__retarget_lock_release_recursive> 800f6f6: e7f3 b.n 800f6e0 <_vfiprintf_r+0x44> 800f6f8: 2300 movs r3, #0 800f6fa: 9309 str r3, [sp, #36] @ 0x24 800f6fc: 2320 movs r3, #32 800f6fe: f88d 3029 strb.w r3, [sp, #41] @ 0x29 800f702: f8cd 800c str.w r8, [sp, #12] 800f706: 2330 movs r3, #48 @ 0x30 800f708: f8df 81ac ldr.w r8, [pc, #428] @ 800f8b8 <_vfiprintf_r+0x21c> 800f70c: f88d 302a strb.w r3, [sp, #42] @ 0x2a 800f710: f04f 0901 mov.w r9, #1 800f714: 4623 mov r3, r4 800f716: 469a mov sl, r3 800f718: f813 2b01 ldrb.w r2, [r3], #1 800f71c: b10a cbz r2, 800f722 <_vfiprintf_r+0x86> 800f71e: 2a25 cmp r2, #37 @ 0x25 800f720: d1f9 bne.n 800f716 <_vfiprintf_r+0x7a> 800f722: ebba 0b04 subs.w fp, sl, r4 800f726: d00b beq.n 800f740 <_vfiprintf_r+0xa4> 800f728: 465b mov r3, fp 800f72a: 4622 mov r2, r4 800f72c: 4629 mov r1, r5 800f72e: 4630 mov r0, r6 800f730: f7ff ffa1 bl 800f676 <__sfputs_r> 800f734: 3001 adds r0, #1 800f736: f000 80a7 beq.w 800f888 <_vfiprintf_r+0x1ec> 800f73a: 9a09 ldr r2, [sp, #36] @ 0x24 800f73c: 445a add r2, fp 800f73e: 9209 str r2, [sp, #36] @ 0x24 800f740: f89a 3000 ldrb.w r3, [sl] 800f744: 2b00 cmp r3, #0 800f746: f000 809f beq.w 800f888 <_vfiprintf_r+0x1ec> 800f74a: 2300 movs r3, #0 800f74c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800f750: e9cd 2305 strd r2, r3, [sp, #20] 800f754: f10a 0a01 add.w sl, sl, #1 800f758: 9304 str r3, [sp, #16] 800f75a: 9307 str r3, [sp, #28] 800f75c: f88d 3053 strb.w r3, [sp, #83] @ 0x53 800f760: 931a str r3, [sp, #104] @ 0x68 800f762: 4654 mov r4, sl 800f764: 2205 movs r2, #5 800f766: f814 1b01 ldrb.w r1, [r4], #1 800f76a: 4853 ldr r0, [pc, #332] @ (800f8b8 <_vfiprintf_r+0x21c>) 800f76c: f7f0 fdb8 bl 80002e0 800f770: 9a04 ldr r2, [sp, #16] 800f772: b9d8 cbnz r0, 800f7ac <_vfiprintf_r+0x110> 800f774: 06d1 lsls r1, r2, #27 800f776: bf44 itt mi 800f778: 2320 movmi r3, #32 800f77a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800f77e: 0713 lsls r3, r2, #28 800f780: bf44 itt mi 800f782: 232b movmi r3, #43 @ 0x2b 800f784: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 800f788: f89a 3000 ldrb.w r3, [sl] 800f78c: 2b2a cmp r3, #42 @ 0x2a 800f78e: d015 beq.n 800f7bc <_vfiprintf_r+0x120> 800f790: 9a07 ldr r2, [sp, #28] 800f792: 4654 mov r4, sl 800f794: 2000 movs r0, #0 800f796: f04f 0c0a mov.w ip, #10 800f79a: 4621 mov r1, r4 800f79c: f811 3b01 ldrb.w r3, [r1], #1 800f7a0: 3b30 subs r3, #48 @ 0x30 800f7a2: 2b09 cmp r3, #9 800f7a4: d94b bls.n 800f83e <_vfiprintf_r+0x1a2> 800f7a6: b1b0 cbz r0, 800f7d6 <_vfiprintf_r+0x13a> 800f7a8: 9207 str r2, [sp, #28] 800f7aa: e014 b.n 800f7d6 <_vfiprintf_r+0x13a> 800f7ac: eba0 0308 sub.w r3, r0, r8 800f7b0: fa09 f303 lsl.w r3, r9, r3 800f7b4: 4313 orrs r3, r2 800f7b6: 9304 str r3, [sp, #16] 800f7b8: 46a2 mov sl, r4 800f7ba: e7d2 b.n 800f762 <_vfiprintf_r+0xc6> 800f7bc: 9b03 ldr r3, [sp, #12] 800f7be: 1d19 adds r1, r3, #4 800f7c0: 681b ldr r3, [r3, #0] 800f7c2: 9103 str r1, [sp, #12] 800f7c4: 2b00 cmp r3, #0 800f7c6: bfbb ittet lt 800f7c8: 425b neglt r3, r3 800f7ca: f042 0202 orrlt.w r2, r2, #2 800f7ce: 9307 strge r3, [sp, #28] 800f7d0: 9307 strlt r3, [sp, #28] 800f7d2: bfb8 it lt 800f7d4: 9204 strlt r2, [sp, #16] 800f7d6: 7823 ldrb r3, [r4, #0] 800f7d8: 2b2e cmp r3, #46 @ 0x2e 800f7da: d10a bne.n 800f7f2 <_vfiprintf_r+0x156> 800f7dc: 7863 ldrb r3, [r4, #1] 800f7de: 2b2a cmp r3, #42 @ 0x2a 800f7e0: d132 bne.n 800f848 <_vfiprintf_r+0x1ac> 800f7e2: 9b03 ldr r3, [sp, #12] 800f7e4: 1d1a adds r2, r3, #4 800f7e6: 681b ldr r3, [r3, #0] 800f7e8: 9203 str r2, [sp, #12] 800f7ea: ea43 73e3 orr.w r3, r3, r3, asr #31 800f7ee: 3402 adds r4, #2 800f7f0: 9305 str r3, [sp, #20] 800f7f2: f8df a0d4 ldr.w sl, [pc, #212] @ 800f8c8 <_vfiprintf_r+0x22c> 800f7f6: 7821 ldrb r1, [r4, #0] 800f7f8: 2203 movs r2, #3 800f7fa: 4650 mov r0, sl 800f7fc: f7f0 fd70 bl 80002e0 800f800: b138 cbz r0, 800f812 <_vfiprintf_r+0x176> 800f802: 9b04 ldr r3, [sp, #16] 800f804: eba0 000a sub.w r0, r0, sl 800f808: 2240 movs r2, #64 @ 0x40 800f80a: 4082 lsls r2, r0 800f80c: 4313 orrs r3, r2 800f80e: 3401 adds r4, #1 800f810: 9304 str r3, [sp, #16] 800f812: f814 1b01 ldrb.w r1, [r4], #1 800f816: 4829 ldr r0, [pc, #164] @ (800f8bc <_vfiprintf_r+0x220>) 800f818: f88d 1028 strb.w r1, [sp, #40] @ 0x28 800f81c: 2206 movs r2, #6 800f81e: f7f0 fd5f bl 80002e0 800f822: 2800 cmp r0, #0 800f824: d03f beq.n 800f8a6 <_vfiprintf_r+0x20a> 800f826: 4b26 ldr r3, [pc, #152] @ (800f8c0 <_vfiprintf_r+0x224>) 800f828: bb1b cbnz r3, 800f872 <_vfiprintf_r+0x1d6> 800f82a: 9b03 ldr r3, [sp, #12] 800f82c: 3307 adds r3, #7 800f82e: f023 0307 bic.w r3, r3, #7 800f832: 3308 adds r3, #8 800f834: 9303 str r3, [sp, #12] 800f836: 9b09 ldr r3, [sp, #36] @ 0x24 800f838: 443b add r3, r7 800f83a: 9309 str r3, [sp, #36] @ 0x24 800f83c: e76a b.n 800f714 <_vfiprintf_r+0x78> 800f83e: fb0c 3202 mla r2, ip, r2, r3 800f842: 460c mov r4, r1 800f844: 2001 movs r0, #1 800f846: e7a8 b.n 800f79a <_vfiprintf_r+0xfe> 800f848: 2300 movs r3, #0 800f84a: 3401 adds r4, #1 800f84c: 9305 str r3, [sp, #20] 800f84e: 4619 mov r1, r3 800f850: f04f 0c0a mov.w ip, #10 800f854: 4620 mov r0, r4 800f856: f810 2b01 ldrb.w r2, [r0], #1 800f85a: 3a30 subs r2, #48 @ 0x30 800f85c: 2a09 cmp r2, #9 800f85e: d903 bls.n 800f868 <_vfiprintf_r+0x1cc> 800f860: 2b00 cmp r3, #0 800f862: d0c6 beq.n 800f7f2 <_vfiprintf_r+0x156> 800f864: 9105 str r1, [sp, #20] 800f866: e7c4 b.n 800f7f2 <_vfiprintf_r+0x156> 800f868: fb0c 2101 mla r1, ip, r1, r2 800f86c: 4604 mov r4, r0 800f86e: 2301 movs r3, #1 800f870: e7f0 b.n 800f854 <_vfiprintf_r+0x1b8> 800f872: ab03 add r3, sp, #12 800f874: 9300 str r3, [sp, #0] 800f876: 462a mov r2, r5 800f878: 4b12 ldr r3, [pc, #72] @ (800f8c4 <_vfiprintf_r+0x228>) 800f87a: a904 add r1, sp, #16 800f87c: 4630 mov r0, r6 800f87e: f3af 8000 nop.w 800f882: 4607 mov r7, r0 800f884: 1c78 adds r0, r7, #1 800f886: d1d6 bne.n 800f836 <_vfiprintf_r+0x19a> 800f888: 6e6b ldr r3, [r5, #100] @ 0x64 800f88a: 07d9 lsls r1, r3, #31 800f88c: d405 bmi.n 800f89a <_vfiprintf_r+0x1fe> 800f88e: 89ab ldrh r3, [r5, #12] 800f890: 059a lsls r2, r3, #22 800f892: d402 bmi.n 800f89a <_vfiprintf_r+0x1fe> 800f894: 6da8 ldr r0, [r5, #88] @ 0x58 800f896: f7ff fdcf bl 800f438 <__retarget_lock_release_recursive> 800f89a: 89ab ldrh r3, [r5, #12] 800f89c: 065b lsls r3, r3, #25 800f89e: f53f af1f bmi.w 800f6e0 <_vfiprintf_r+0x44> 800f8a2: 9809 ldr r0, [sp, #36] @ 0x24 800f8a4: e71e b.n 800f6e4 <_vfiprintf_r+0x48> 800f8a6: ab03 add r3, sp, #12 800f8a8: 9300 str r3, [sp, #0] 800f8aa: 462a mov r2, r5 800f8ac: 4b05 ldr r3, [pc, #20] @ (800f8c4 <_vfiprintf_r+0x228>) 800f8ae: a904 add r1, sp, #16 800f8b0: 4630 mov r0, r6 800f8b2: f000 f879 bl 800f9a8 <_printf_i> 800f8b6: e7e4 b.n 800f882 <_vfiprintf_r+0x1e6> 800f8b8: 080100f0 .word 0x080100f0 800f8bc: 080100fa .word 0x080100fa 800f8c0: 00000000 .word 0x00000000 800f8c4: 0800f677 .word 0x0800f677 800f8c8: 080100f6 .word 0x080100f6 0800f8cc <_printf_common>: 800f8cc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 800f8d0: 4616 mov r6, r2 800f8d2: 4698 mov r8, r3 800f8d4: 688a ldr r2, [r1, #8] 800f8d6: 690b ldr r3, [r1, #16] 800f8d8: f8dd 9020 ldr.w r9, [sp, #32] 800f8dc: 4293 cmp r3, r2 800f8de: bfb8 it lt 800f8e0: 4613 movlt r3, r2 800f8e2: 6033 str r3, [r6, #0] 800f8e4: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 800f8e8: 4607 mov r7, r0 800f8ea: 460c mov r4, r1 800f8ec: b10a cbz r2, 800f8f2 <_printf_common+0x26> 800f8ee: 3301 adds r3, #1 800f8f0: 6033 str r3, [r6, #0] 800f8f2: 6823 ldr r3, [r4, #0] 800f8f4: 0699 lsls r1, r3, #26 800f8f6: bf42 ittt mi 800f8f8: 6833 ldrmi r3, [r6, #0] 800f8fa: 3302 addmi r3, #2 800f8fc: 6033 strmi r3, [r6, #0] 800f8fe: 6825 ldr r5, [r4, #0] 800f900: f015 0506 ands.w r5, r5, #6 800f904: d106 bne.n 800f914 <_printf_common+0x48> 800f906: f104 0a19 add.w sl, r4, #25 800f90a: 68e3 ldr r3, [r4, #12] 800f90c: 6832 ldr r2, [r6, #0] 800f90e: 1a9b subs r3, r3, r2 800f910: 42ab cmp r3, r5 800f912: dc26 bgt.n 800f962 <_printf_common+0x96> 800f914: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 800f918: 6822 ldr r2, [r4, #0] 800f91a: 3b00 subs r3, #0 800f91c: bf18 it ne 800f91e: 2301 movne r3, #1 800f920: 0692 lsls r2, r2, #26 800f922: d42b bmi.n 800f97c <_printf_common+0xb0> 800f924: f104 0243 add.w r2, r4, #67 @ 0x43 800f928: 4641 mov r1, r8 800f92a: 4638 mov r0, r7 800f92c: 47c8 blx r9 800f92e: 3001 adds r0, #1 800f930: d01e beq.n 800f970 <_printf_common+0xa4> 800f932: 6823 ldr r3, [r4, #0] 800f934: 6922 ldr r2, [r4, #16] 800f936: f003 0306 and.w r3, r3, #6 800f93a: 2b04 cmp r3, #4 800f93c: bf02 ittt eq 800f93e: 68e5 ldreq r5, [r4, #12] 800f940: 6833 ldreq r3, [r6, #0] 800f942: 1aed subeq r5, r5, r3 800f944: 68a3 ldr r3, [r4, #8] 800f946: bf0c ite eq 800f948: ea25 75e5 biceq.w r5, r5, r5, asr #31 800f94c: 2500 movne r5, #0 800f94e: 4293 cmp r3, r2 800f950: bfc4 itt gt 800f952: 1a9b subgt r3, r3, r2 800f954: 18ed addgt r5, r5, r3 800f956: 2600 movs r6, #0 800f958: 341a adds r4, #26 800f95a: 42b5 cmp r5, r6 800f95c: d11a bne.n 800f994 <_printf_common+0xc8> 800f95e: 2000 movs r0, #0 800f960: e008 b.n 800f974 <_printf_common+0xa8> 800f962: 2301 movs r3, #1 800f964: 4652 mov r2, sl 800f966: 4641 mov r1, r8 800f968: 4638 mov r0, r7 800f96a: 47c8 blx r9 800f96c: 3001 adds r0, #1 800f96e: d103 bne.n 800f978 <_printf_common+0xac> 800f970: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800f974: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800f978: 3501 adds r5, #1 800f97a: e7c6 b.n 800f90a <_printf_common+0x3e> 800f97c: 18e1 adds r1, r4, r3 800f97e: 1c5a adds r2, r3, #1 800f980: 2030 movs r0, #48 @ 0x30 800f982: f881 0043 strb.w r0, [r1, #67] @ 0x43 800f986: 4422 add r2, r4 800f988: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 800f98c: f882 1043 strb.w r1, [r2, #67] @ 0x43 800f990: 3302 adds r3, #2 800f992: e7c7 b.n 800f924 <_printf_common+0x58> 800f994: 2301 movs r3, #1 800f996: 4622 mov r2, r4 800f998: 4641 mov r1, r8 800f99a: 4638 mov r0, r7 800f99c: 47c8 blx r9 800f99e: 3001 adds r0, #1 800f9a0: d0e6 beq.n 800f970 <_printf_common+0xa4> 800f9a2: 3601 adds r6, #1 800f9a4: e7d9 b.n 800f95a <_printf_common+0x8e> ... 0800f9a8 <_printf_i>: 800f9a8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 800f9ac: 7e0f ldrb r7, [r1, #24] 800f9ae: 9e0c ldr r6, [sp, #48] @ 0x30 800f9b0: 2f78 cmp r7, #120 @ 0x78 800f9b2: 4691 mov r9, r2 800f9b4: 4680 mov r8, r0 800f9b6: 460c mov r4, r1 800f9b8: 469a mov sl, r3 800f9ba: f101 0243 add.w r2, r1, #67 @ 0x43 800f9be: d807 bhi.n 800f9d0 <_printf_i+0x28> 800f9c0: 2f62 cmp r7, #98 @ 0x62 800f9c2: d80a bhi.n 800f9da <_printf_i+0x32> 800f9c4: 2f00 cmp r7, #0 800f9c6: f000 80d2 beq.w 800fb6e <_printf_i+0x1c6> 800f9ca: 2f58 cmp r7, #88 @ 0x58 800f9cc: f000 80b9 beq.w 800fb42 <_printf_i+0x19a> 800f9d0: f104 0642 add.w r6, r4, #66 @ 0x42 800f9d4: f884 7042 strb.w r7, [r4, #66] @ 0x42 800f9d8: e03a b.n 800fa50 <_printf_i+0xa8> 800f9da: f1a7 0363 sub.w r3, r7, #99 @ 0x63 800f9de: 2b15 cmp r3, #21 800f9e0: d8f6 bhi.n 800f9d0 <_printf_i+0x28> 800f9e2: a101 add r1, pc, #4 @ (adr r1, 800f9e8 <_printf_i+0x40>) 800f9e4: f851 f023 ldr.w pc, [r1, r3, lsl #2] 800f9e8: 0800fa41 .word 0x0800fa41 800f9ec: 0800fa55 .word 0x0800fa55 800f9f0: 0800f9d1 .word 0x0800f9d1 800f9f4: 0800f9d1 .word 0x0800f9d1 800f9f8: 0800f9d1 .word 0x0800f9d1 800f9fc: 0800f9d1 .word 0x0800f9d1 800fa00: 0800fa55 .word 0x0800fa55 800fa04: 0800f9d1 .word 0x0800f9d1 800fa08: 0800f9d1 .word 0x0800f9d1 800fa0c: 0800f9d1 .word 0x0800f9d1 800fa10: 0800f9d1 .word 0x0800f9d1 800fa14: 0800fb55 .word 0x0800fb55 800fa18: 0800fa7f .word 0x0800fa7f 800fa1c: 0800fb0f .word 0x0800fb0f 800fa20: 0800f9d1 .word 0x0800f9d1 800fa24: 0800f9d1 .word 0x0800f9d1 800fa28: 0800fb77 .word 0x0800fb77 800fa2c: 0800f9d1 .word 0x0800f9d1 800fa30: 0800fa7f .word 0x0800fa7f 800fa34: 0800f9d1 .word 0x0800f9d1 800fa38: 0800f9d1 .word 0x0800f9d1 800fa3c: 0800fb17 .word 0x0800fb17 800fa40: 6833 ldr r3, [r6, #0] 800fa42: 1d1a adds r2, r3, #4 800fa44: 681b ldr r3, [r3, #0] 800fa46: 6032 str r2, [r6, #0] 800fa48: f104 0642 add.w r6, r4, #66 @ 0x42 800fa4c: f884 3042 strb.w r3, [r4, #66] @ 0x42 800fa50: 2301 movs r3, #1 800fa52: e09d b.n 800fb90 <_printf_i+0x1e8> 800fa54: 6833 ldr r3, [r6, #0] 800fa56: 6820 ldr r0, [r4, #0] 800fa58: 1d19 adds r1, r3, #4 800fa5a: 6031 str r1, [r6, #0] 800fa5c: 0606 lsls r6, r0, #24 800fa5e: d501 bpl.n 800fa64 <_printf_i+0xbc> 800fa60: 681d ldr r5, [r3, #0] 800fa62: e003 b.n 800fa6c <_printf_i+0xc4> 800fa64: 0645 lsls r5, r0, #25 800fa66: d5fb bpl.n 800fa60 <_printf_i+0xb8> 800fa68: f9b3 5000 ldrsh.w r5, [r3] 800fa6c: 2d00 cmp r5, #0 800fa6e: da03 bge.n 800fa78 <_printf_i+0xd0> 800fa70: 232d movs r3, #45 @ 0x2d 800fa72: 426d negs r5, r5 800fa74: f884 3043 strb.w r3, [r4, #67] @ 0x43 800fa78: 4859 ldr r0, [pc, #356] @ (800fbe0 <_printf_i+0x238>) 800fa7a: 230a movs r3, #10 800fa7c: e011 b.n 800faa2 <_printf_i+0xfa> 800fa7e: 6821 ldr r1, [r4, #0] 800fa80: 6833 ldr r3, [r6, #0] 800fa82: 0608 lsls r0, r1, #24 800fa84: f853 5b04 ldr.w r5, [r3], #4 800fa88: d402 bmi.n 800fa90 <_printf_i+0xe8> 800fa8a: 0649 lsls r1, r1, #25 800fa8c: bf48 it mi 800fa8e: b2ad uxthmi r5, r5 800fa90: 2f6f cmp r7, #111 @ 0x6f 800fa92: 4853 ldr r0, [pc, #332] @ (800fbe0 <_printf_i+0x238>) 800fa94: 6033 str r3, [r6, #0] 800fa96: bf14 ite ne 800fa98: 230a movne r3, #10 800fa9a: 2308 moveq r3, #8 800fa9c: 2100 movs r1, #0 800fa9e: f884 1043 strb.w r1, [r4, #67] @ 0x43 800faa2: 6866 ldr r6, [r4, #4] 800faa4: 60a6 str r6, [r4, #8] 800faa6: 2e00 cmp r6, #0 800faa8: bfa2 ittt ge 800faaa: 6821 ldrge r1, [r4, #0] 800faac: f021 0104 bicge.w r1, r1, #4 800fab0: 6021 strge r1, [r4, #0] 800fab2: b90d cbnz r5, 800fab8 <_printf_i+0x110> 800fab4: 2e00 cmp r6, #0 800fab6: d04b beq.n 800fb50 <_printf_i+0x1a8> 800fab8: 4616 mov r6, r2 800faba: fbb5 f1f3 udiv r1, r5, r3 800fabe: fb03 5711 mls r7, r3, r1, r5 800fac2: 5dc7 ldrb r7, [r0, r7] 800fac4: f806 7d01 strb.w r7, [r6, #-1]! 800fac8: 462f mov r7, r5 800faca: 42bb cmp r3, r7 800facc: 460d mov r5, r1 800face: d9f4 bls.n 800faba <_printf_i+0x112> 800fad0: 2b08 cmp r3, #8 800fad2: d10b bne.n 800faec <_printf_i+0x144> 800fad4: 6823 ldr r3, [r4, #0] 800fad6: 07df lsls r7, r3, #31 800fad8: d508 bpl.n 800faec <_printf_i+0x144> 800fada: 6923 ldr r3, [r4, #16] 800fadc: 6861 ldr r1, [r4, #4] 800fade: 4299 cmp r1, r3 800fae0: bfde ittt le 800fae2: 2330 movle r3, #48 @ 0x30 800fae4: f806 3c01 strble.w r3, [r6, #-1] 800fae8: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 800faec: 1b92 subs r2, r2, r6 800faee: 6122 str r2, [r4, #16] 800faf0: f8cd a000 str.w sl, [sp] 800faf4: 464b mov r3, r9 800faf6: aa03 add r2, sp, #12 800faf8: 4621 mov r1, r4 800fafa: 4640 mov r0, r8 800fafc: f7ff fee6 bl 800f8cc <_printf_common> 800fb00: 3001 adds r0, #1 800fb02: d14a bne.n 800fb9a <_printf_i+0x1f2> 800fb04: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800fb08: b004 add sp, #16 800fb0a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800fb0e: 6823 ldr r3, [r4, #0] 800fb10: f043 0320 orr.w r3, r3, #32 800fb14: 6023 str r3, [r4, #0] 800fb16: 4833 ldr r0, [pc, #204] @ (800fbe4 <_printf_i+0x23c>) 800fb18: 2778 movs r7, #120 @ 0x78 800fb1a: f884 7045 strb.w r7, [r4, #69] @ 0x45 800fb1e: 6823 ldr r3, [r4, #0] 800fb20: 6831 ldr r1, [r6, #0] 800fb22: 061f lsls r7, r3, #24 800fb24: f851 5b04 ldr.w r5, [r1], #4 800fb28: d402 bmi.n 800fb30 <_printf_i+0x188> 800fb2a: 065f lsls r7, r3, #25 800fb2c: bf48 it mi 800fb2e: b2ad uxthmi r5, r5 800fb30: 6031 str r1, [r6, #0] 800fb32: 07d9 lsls r1, r3, #31 800fb34: bf44 itt mi 800fb36: f043 0320 orrmi.w r3, r3, #32 800fb3a: 6023 strmi r3, [r4, #0] 800fb3c: b11d cbz r5, 800fb46 <_printf_i+0x19e> 800fb3e: 2310 movs r3, #16 800fb40: e7ac b.n 800fa9c <_printf_i+0xf4> 800fb42: 4827 ldr r0, [pc, #156] @ (800fbe0 <_printf_i+0x238>) 800fb44: e7e9 b.n 800fb1a <_printf_i+0x172> 800fb46: 6823 ldr r3, [r4, #0] 800fb48: f023 0320 bic.w r3, r3, #32 800fb4c: 6023 str r3, [r4, #0] 800fb4e: e7f6 b.n 800fb3e <_printf_i+0x196> 800fb50: 4616 mov r6, r2 800fb52: e7bd b.n 800fad0 <_printf_i+0x128> 800fb54: 6833 ldr r3, [r6, #0] 800fb56: 6825 ldr r5, [r4, #0] 800fb58: 6961 ldr r1, [r4, #20] 800fb5a: 1d18 adds r0, r3, #4 800fb5c: 6030 str r0, [r6, #0] 800fb5e: 062e lsls r6, r5, #24 800fb60: 681b ldr r3, [r3, #0] 800fb62: d501 bpl.n 800fb68 <_printf_i+0x1c0> 800fb64: 6019 str r1, [r3, #0] 800fb66: e002 b.n 800fb6e <_printf_i+0x1c6> 800fb68: 0668 lsls r0, r5, #25 800fb6a: d5fb bpl.n 800fb64 <_printf_i+0x1bc> 800fb6c: 8019 strh r1, [r3, #0] 800fb6e: 2300 movs r3, #0 800fb70: 6123 str r3, [r4, #16] 800fb72: 4616 mov r6, r2 800fb74: e7bc b.n 800faf0 <_printf_i+0x148> 800fb76: 6833 ldr r3, [r6, #0] 800fb78: 1d1a adds r2, r3, #4 800fb7a: 6032 str r2, [r6, #0] 800fb7c: 681e ldr r6, [r3, #0] 800fb7e: 6862 ldr r2, [r4, #4] 800fb80: 2100 movs r1, #0 800fb82: 4630 mov r0, r6 800fb84: f7f0 fbac bl 80002e0 800fb88: b108 cbz r0, 800fb8e <_printf_i+0x1e6> 800fb8a: 1b80 subs r0, r0, r6 800fb8c: 6060 str r0, [r4, #4] 800fb8e: 6863 ldr r3, [r4, #4] 800fb90: 6123 str r3, [r4, #16] 800fb92: 2300 movs r3, #0 800fb94: f884 3043 strb.w r3, [r4, #67] @ 0x43 800fb98: e7aa b.n 800faf0 <_printf_i+0x148> 800fb9a: 6923 ldr r3, [r4, #16] 800fb9c: 4632 mov r2, r6 800fb9e: 4649 mov r1, r9 800fba0: 4640 mov r0, r8 800fba2: 47d0 blx sl 800fba4: 3001 adds r0, #1 800fba6: d0ad beq.n 800fb04 <_printf_i+0x15c> 800fba8: 6823 ldr r3, [r4, #0] 800fbaa: 079b lsls r3, r3, #30 800fbac: d413 bmi.n 800fbd6 <_printf_i+0x22e> 800fbae: 68e0 ldr r0, [r4, #12] 800fbb0: 9b03 ldr r3, [sp, #12] 800fbb2: 4298 cmp r0, r3 800fbb4: bfb8 it lt 800fbb6: 4618 movlt r0, r3 800fbb8: e7a6 b.n 800fb08 <_printf_i+0x160> 800fbba: 2301 movs r3, #1 800fbbc: 4632 mov r2, r6 800fbbe: 4649 mov r1, r9 800fbc0: 4640 mov r0, r8 800fbc2: 47d0 blx sl 800fbc4: 3001 adds r0, #1 800fbc6: d09d beq.n 800fb04 <_printf_i+0x15c> 800fbc8: 3501 adds r5, #1 800fbca: 68e3 ldr r3, [r4, #12] 800fbcc: 9903 ldr r1, [sp, #12] 800fbce: 1a5b subs r3, r3, r1 800fbd0: 42ab cmp r3, r5 800fbd2: dcf2 bgt.n 800fbba <_printf_i+0x212> 800fbd4: e7eb b.n 800fbae <_printf_i+0x206> 800fbd6: 2500 movs r5, #0 800fbd8: f104 0619 add.w r6, r4, #25 800fbdc: e7f5 b.n 800fbca <_printf_i+0x222> 800fbde: bf00 nop 800fbe0: 08010101 .word 0x08010101 800fbe4: 08010112 .word 0x08010112 0800fbe8 <__sflush_r>: 800fbe8: f9b1 200c ldrsh.w r2, [r1, #12] 800fbec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 800fbf0: 0716 lsls r6, r2, #28 800fbf2: 4605 mov r5, r0 800fbf4: 460c mov r4, r1 800fbf6: d454 bmi.n 800fca2 <__sflush_r+0xba> 800fbf8: 684b ldr r3, [r1, #4] 800fbfa: 2b00 cmp r3, #0 800fbfc: dc02 bgt.n 800fc04 <__sflush_r+0x1c> 800fbfe: 6c0b ldr r3, [r1, #64] @ 0x40 800fc00: 2b00 cmp r3, #0 800fc02: dd48 ble.n 800fc96 <__sflush_r+0xae> 800fc04: 6ae6 ldr r6, [r4, #44] @ 0x2c 800fc06: 2e00 cmp r6, #0 800fc08: d045 beq.n 800fc96 <__sflush_r+0xae> 800fc0a: 2300 movs r3, #0 800fc0c: f412 5280 ands.w r2, r2, #4096 @ 0x1000 800fc10: 682f ldr r7, [r5, #0] 800fc12: 6a21 ldr r1, [r4, #32] 800fc14: 602b str r3, [r5, #0] 800fc16: d030 beq.n 800fc7a <__sflush_r+0x92> 800fc18: 6d62 ldr r2, [r4, #84] @ 0x54 800fc1a: 89a3 ldrh r3, [r4, #12] 800fc1c: 0759 lsls r1, r3, #29 800fc1e: d505 bpl.n 800fc2c <__sflush_r+0x44> 800fc20: 6863 ldr r3, [r4, #4] 800fc22: 1ad2 subs r2, r2, r3 800fc24: 6b63 ldr r3, [r4, #52] @ 0x34 800fc26: b10b cbz r3, 800fc2c <__sflush_r+0x44> 800fc28: 6c23 ldr r3, [r4, #64] @ 0x40 800fc2a: 1ad2 subs r2, r2, r3 800fc2c: 2300 movs r3, #0 800fc2e: 6ae6 ldr r6, [r4, #44] @ 0x2c 800fc30: 6a21 ldr r1, [r4, #32] 800fc32: 4628 mov r0, r5 800fc34: 47b0 blx r6 800fc36: 1c43 adds r3, r0, #1 800fc38: 89a3 ldrh r3, [r4, #12] 800fc3a: d106 bne.n 800fc4a <__sflush_r+0x62> 800fc3c: 6829 ldr r1, [r5, #0] 800fc3e: 291d cmp r1, #29 800fc40: d82b bhi.n 800fc9a <__sflush_r+0xb2> 800fc42: 4a2a ldr r2, [pc, #168] @ (800fcec <__sflush_r+0x104>) 800fc44: 410a asrs r2, r1 800fc46: 07d6 lsls r6, r2, #31 800fc48: d427 bmi.n 800fc9a <__sflush_r+0xb2> 800fc4a: 2200 movs r2, #0 800fc4c: 6062 str r2, [r4, #4] 800fc4e: 04d9 lsls r1, r3, #19 800fc50: 6922 ldr r2, [r4, #16] 800fc52: 6022 str r2, [r4, #0] 800fc54: d504 bpl.n 800fc60 <__sflush_r+0x78> 800fc56: 1c42 adds r2, r0, #1 800fc58: d101 bne.n 800fc5e <__sflush_r+0x76> 800fc5a: 682b ldr r3, [r5, #0] 800fc5c: b903 cbnz r3, 800fc60 <__sflush_r+0x78> 800fc5e: 6560 str r0, [r4, #84] @ 0x54 800fc60: 6b61 ldr r1, [r4, #52] @ 0x34 800fc62: 602f str r7, [r5, #0] 800fc64: b1b9 cbz r1, 800fc96 <__sflush_r+0xae> 800fc66: f104 0344 add.w r3, r4, #68 @ 0x44 800fc6a: 4299 cmp r1, r3 800fc6c: d002 beq.n 800fc74 <__sflush_r+0x8c> 800fc6e: 4628 mov r0, r5 800fc70: f7ff fbf2 bl 800f458 <_free_r> 800fc74: 2300 movs r3, #0 800fc76: 6363 str r3, [r4, #52] @ 0x34 800fc78: e00d b.n 800fc96 <__sflush_r+0xae> 800fc7a: 2301 movs r3, #1 800fc7c: 4628 mov r0, r5 800fc7e: 47b0 blx r6 800fc80: 4602 mov r2, r0 800fc82: 1c50 adds r0, r2, #1 800fc84: d1c9 bne.n 800fc1a <__sflush_r+0x32> 800fc86: 682b ldr r3, [r5, #0] 800fc88: 2b00 cmp r3, #0 800fc8a: d0c6 beq.n 800fc1a <__sflush_r+0x32> 800fc8c: 2b1d cmp r3, #29 800fc8e: d001 beq.n 800fc94 <__sflush_r+0xac> 800fc90: 2b16 cmp r3, #22 800fc92: d11e bne.n 800fcd2 <__sflush_r+0xea> 800fc94: 602f str r7, [r5, #0] 800fc96: 2000 movs r0, #0 800fc98: e022 b.n 800fce0 <__sflush_r+0xf8> 800fc9a: f043 0340 orr.w r3, r3, #64 @ 0x40 800fc9e: b21b sxth r3, r3 800fca0: e01b b.n 800fcda <__sflush_r+0xf2> 800fca2: 690f ldr r7, [r1, #16] 800fca4: 2f00 cmp r7, #0 800fca6: d0f6 beq.n 800fc96 <__sflush_r+0xae> 800fca8: 0793 lsls r3, r2, #30 800fcaa: 680e ldr r6, [r1, #0] 800fcac: bf08 it eq 800fcae: 694b ldreq r3, [r1, #20] 800fcb0: 600f str r7, [r1, #0] 800fcb2: bf18 it ne 800fcb4: 2300 movne r3, #0 800fcb6: eba6 0807 sub.w r8, r6, r7 800fcba: 608b str r3, [r1, #8] 800fcbc: f1b8 0f00 cmp.w r8, #0 800fcc0: dde9 ble.n 800fc96 <__sflush_r+0xae> 800fcc2: 6a21 ldr r1, [r4, #32] 800fcc4: 6aa6 ldr r6, [r4, #40] @ 0x28 800fcc6: 4643 mov r3, r8 800fcc8: 463a mov r2, r7 800fcca: 4628 mov r0, r5 800fccc: 47b0 blx r6 800fcce: 2800 cmp r0, #0 800fcd0: dc08 bgt.n 800fce4 <__sflush_r+0xfc> 800fcd2: f9b4 300c ldrsh.w r3, [r4, #12] 800fcd6: f043 0340 orr.w r3, r3, #64 @ 0x40 800fcda: 81a3 strh r3, [r4, #12] 800fcdc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800fce0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 800fce4: 4407 add r7, r0 800fce6: eba8 0800 sub.w r8, r8, r0 800fcea: e7e7 b.n 800fcbc <__sflush_r+0xd4> 800fcec: dfbffffe .word 0xdfbffffe 0800fcf0 <_fflush_r>: 800fcf0: b538 push {r3, r4, r5, lr} 800fcf2: 690b ldr r3, [r1, #16] 800fcf4: 4605 mov r5, r0 800fcf6: 460c mov r4, r1 800fcf8: b913 cbnz r3, 800fd00 <_fflush_r+0x10> 800fcfa: 2500 movs r5, #0 800fcfc: 4628 mov r0, r5 800fcfe: bd38 pop {r3, r4, r5, pc} 800fd00: b118 cbz r0, 800fd0a <_fflush_r+0x1a> 800fd02: 6a03 ldr r3, [r0, #32] 800fd04: b90b cbnz r3, 800fd0a <_fflush_r+0x1a> 800fd06: f7ff fa3b bl 800f180 <__sinit> 800fd0a: f9b4 300c ldrsh.w r3, [r4, #12] 800fd0e: 2b00 cmp r3, #0 800fd10: d0f3 beq.n 800fcfa <_fflush_r+0xa> 800fd12: 6e62 ldr r2, [r4, #100] @ 0x64 800fd14: 07d0 lsls r0, r2, #31 800fd16: d404 bmi.n 800fd22 <_fflush_r+0x32> 800fd18: 0599 lsls r1, r3, #22 800fd1a: d402 bmi.n 800fd22 <_fflush_r+0x32> 800fd1c: 6da0 ldr r0, [r4, #88] @ 0x58 800fd1e: f7ff fb8a bl 800f436 <__retarget_lock_acquire_recursive> 800fd22: 4628 mov r0, r5 800fd24: 4621 mov r1, r4 800fd26: f7ff ff5f bl 800fbe8 <__sflush_r> 800fd2a: 6e63 ldr r3, [r4, #100] @ 0x64 800fd2c: 07da lsls r2, r3, #31 800fd2e: 4605 mov r5, r0 800fd30: d4e4 bmi.n 800fcfc <_fflush_r+0xc> 800fd32: 89a3 ldrh r3, [r4, #12] 800fd34: 059b lsls r3, r3, #22 800fd36: d4e1 bmi.n 800fcfc <_fflush_r+0xc> 800fd38: 6da0 ldr r0, [r4, #88] @ 0x58 800fd3a: f7ff fb7d bl 800f438 <__retarget_lock_release_recursive> 800fd3e: e7dd b.n 800fcfc <_fflush_r+0xc> 0800fd40 <__swbuf_r>: 800fd40: b5f8 push {r3, r4, r5, r6, r7, lr} 800fd42: 460e mov r6, r1 800fd44: 4614 mov r4, r2 800fd46: 4605 mov r5, r0 800fd48: b118 cbz r0, 800fd52 <__swbuf_r+0x12> 800fd4a: 6a03 ldr r3, [r0, #32] 800fd4c: b90b cbnz r3, 800fd52 <__swbuf_r+0x12> 800fd4e: f7ff fa17 bl 800f180 <__sinit> 800fd52: 69a3 ldr r3, [r4, #24] 800fd54: 60a3 str r3, [r4, #8] 800fd56: 89a3 ldrh r3, [r4, #12] 800fd58: 071a lsls r2, r3, #28 800fd5a: d501 bpl.n 800fd60 <__swbuf_r+0x20> 800fd5c: 6923 ldr r3, [r4, #16] 800fd5e: b943 cbnz r3, 800fd72 <__swbuf_r+0x32> 800fd60: 4621 mov r1, r4 800fd62: 4628 mov r0, r5 800fd64: f000 f82a bl 800fdbc <__swsetup_r> 800fd68: b118 cbz r0, 800fd72 <__swbuf_r+0x32> 800fd6a: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 800fd6e: 4638 mov r0, r7 800fd70: bdf8 pop {r3, r4, r5, r6, r7, pc} 800fd72: 6823 ldr r3, [r4, #0] 800fd74: 6922 ldr r2, [r4, #16] 800fd76: 1a98 subs r0, r3, r2 800fd78: 6963 ldr r3, [r4, #20] 800fd7a: b2f6 uxtb r6, r6 800fd7c: 4283 cmp r3, r0 800fd7e: 4637 mov r7, r6 800fd80: dc05 bgt.n 800fd8e <__swbuf_r+0x4e> 800fd82: 4621 mov r1, r4 800fd84: 4628 mov r0, r5 800fd86: f7ff ffb3 bl 800fcf0 <_fflush_r> 800fd8a: 2800 cmp r0, #0 800fd8c: d1ed bne.n 800fd6a <__swbuf_r+0x2a> 800fd8e: 68a3 ldr r3, [r4, #8] 800fd90: 3b01 subs r3, #1 800fd92: 60a3 str r3, [r4, #8] 800fd94: 6823 ldr r3, [r4, #0] 800fd96: 1c5a adds r2, r3, #1 800fd98: 6022 str r2, [r4, #0] 800fd9a: 701e strb r6, [r3, #0] 800fd9c: 6962 ldr r2, [r4, #20] 800fd9e: 1c43 adds r3, r0, #1 800fda0: 429a cmp r2, r3 800fda2: d004 beq.n 800fdae <__swbuf_r+0x6e> 800fda4: 89a3 ldrh r3, [r4, #12] 800fda6: 07db lsls r3, r3, #31 800fda8: d5e1 bpl.n 800fd6e <__swbuf_r+0x2e> 800fdaa: 2e0a cmp r6, #10 800fdac: d1df bne.n 800fd6e <__swbuf_r+0x2e> 800fdae: 4621 mov r1, r4 800fdb0: 4628 mov r0, r5 800fdb2: f7ff ff9d bl 800fcf0 <_fflush_r> 800fdb6: 2800 cmp r0, #0 800fdb8: d0d9 beq.n 800fd6e <__swbuf_r+0x2e> 800fdba: e7d6 b.n 800fd6a <__swbuf_r+0x2a> 0800fdbc <__swsetup_r>: 800fdbc: b538 push {r3, r4, r5, lr} 800fdbe: 4b29 ldr r3, [pc, #164] @ (800fe64 <__swsetup_r+0xa8>) 800fdc0: 4605 mov r5, r0 800fdc2: 6818 ldr r0, [r3, #0] 800fdc4: 460c mov r4, r1 800fdc6: b118 cbz r0, 800fdd0 <__swsetup_r+0x14> 800fdc8: 6a03 ldr r3, [r0, #32] 800fdca: b90b cbnz r3, 800fdd0 <__swsetup_r+0x14> 800fdcc: f7ff f9d8 bl 800f180 <__sinit> 800fdd0: f9b4 300c ldrsh.w r3, [r4, #12] 800fdd4: 0719 lsls r1, r3, #28 800fdd6: d422 bmi.n 800fe1e <__swsetup_r+0x62> 800fdd8: 06da lsls r2, r3, #27 800fdda: d407 bmi.n 800fdec <__swsetup_r+0x30> 800fddc: 2209 movs r2, #9 800fdde: 602a str r2, [r5, #0] 800fde0: f043 0340 orr.w r3, r3, #64 @ 0x40 800fde4: 81a3 strh r3, [r4, #12] 800fde6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 800fdea: e033 b.n 800fe54 <__swsetup_r+0x98> 800fdec: 0758 lsls r0, r3, #29 800fdee: d512 bpl.n 800fe16 <__swsetup_r+0x5a> 800fdf0: 6b61 ldr r1, [r4, #52] @ 0x34 800fdf2: b141 cbz r1, 800fe06 <__swsetup_r+0x4a> 800fdf4: f104 0344 add.w r3, r4, #68 @ 0x44 800fdf8: 4299 cmp r1, r3 800fdfa: d002 beq.n 800fe02 <__swsetup_r+0x46> 800fdfc: 4628 mov r0, r5 800fdfe: f7ff fb2b bl 800f458 <_free_r> 800fe02: 2300 movs r3, #0 800fe04: 6363 str r3, [r4, #52] @ 0x34 800fe06: 89a3 ldrh r3, [r4, #12] 800fe08: f023 0324 bic.w r3, r3, #36 @ 0x24 800fe0c: 81a3 strh r3, [r4, #12] 800fe0e: 2300 movs r3, #0 800fe10: 6063 str r3, [r4, #4] 800fe12: 6923 ldr r3, [r4, #16] 800fe14: 6023 str r3, [r4, #0] 800fe16: 89a3 ldrh r3, [r4, #12] 800fe18: f043 0308 orr.w r3, r3, #8 800fe1c: 81a3 strh r3, [r4, #12] 800fe1e: 6923 ldr r3, [r4, #16] 800fe20: b94b cbnz r3, 800fe36 <__swsetup_r+0x7a> 800fe22: 89a3 ldrh r3, [r4, #12] 800fe24: f403 7320 and.w r3, r3, #640 @ 0x280 800fe28: f5b3 7f00 cmp.w r3, #512 @ 0x200 800fe2c: d003 beq.n 800fe36 <__swsetup_r+0x7a> 800fe2e: 4621 mov r1, r4 800fe30: 4628 mov r0, r5 800fe32: f000 f84f bl 800fed4 <__smakebuf_r> 800fe36: f9b4 300c ldrsh.w r3, [r4, #12] 800fe3a: f013 0201 ands.w r2, r3, #1 800fe3e: d00a beq.n 800fe56 <__swsetup_r+0x9a> 800fe40: 2200 movs r2, #0 800fe42: 60a2 str r2, [r4, #8] 800fe44: 6962 ldr r2, [r4, #20] 800fe46: 4252 negs r2, r2 800fe48: 61a2 str r2, [r4, #24] 800fe4a: 6922 ldr r2, [r4, #16] 800fe4c: b942 cbnz r2, 800fe60 <__swsetup_r+0xa4> 800fe4e: f013 0080 ands.w r0, r3, #128 @ 0x80 800fe52: d1c5 bne.n 800fde0 <__swsetup_r+0x24> 800fe54: bd38 pop {r3, r4, r5, pc} 800fe56: 0799 lsls r1, r3, #30 800fe58: bf58 it pl 800fe5a: 6962 ldrpl r2, [r4, #20] 800fe5c: 60a2 str r2, [r4, #8] 800fe5e: e7f4 b.n 800fe4a <__swsetup_r+0x8e> 800fe60: 2000 movs r0, #0 800fe62: e7f7 b.n 800fe54 <__swsetup_r+0x98> 800fe64: 24000020 .word 0x24000020 0800fe68 <_sbrk_r>: 800fe68: b538 push {r3, r4, r5, lr} 800fe6a: 4d06 ldr r5, [pc, #24] @ (800fe84 <_sbrk_r+0x1c>) 800fe6c: 2300 movs r3, #0 800fe6e: 4604 mov r4, r0 800fe70: 4608 mov r0, r1 800fe72: 602b str r3, [r5, #0] 800fe74: f7f1 fdbe bl 80019f4 <_sbrk> 800fe78: 1c43 adds r3, r0, #1 800fe7a: d102 bne.n 800fe82 <_sbrk_r+0x1a> 800fe7c: 682b ldr r3, [r5, #0] 800fe7e: b103 cbz r3, 800fe82 <_sbrk_r+0x1a> 800fe80: 6023 str r3, [r4, #0] 800fe82: bd38 pop {r3, r4, r5, pc} 800fe84: 240128b8 .word 0x240128b8 0800fe88 <__swhatbuf_r>: 800fe88: b570 push {r4, r5, r6, lr} 800fe8a: 460c mov r4, r1 800fe8c: f9b1 100e ldrsh.w r1, [r1, #14] 800fe90: 2900 cmp r1, #0 800fe92: b096 sub sp, #88 @ 0x58 800fe94: 4615 mov r5, r2 800fe96: 461e mov r6, r3 800fe98: da0d bge.n 800feb6 <__swhatbuf_r+0x2e> 800fe9a: 89a3 ldrh r3, [r4, #12] 800fe9c: f013 0f80 tst.w r3, #128 @ 0x80 800fea0: f04f 0100 mov.w r1, #0 800fea4: bf14 ite ne 800fea6: 2340 movne r3, #64 @ 0x40 800fea8: f44f 6380 moveq.w r3, #1024 @ 0x400 800feac: 2000 movs r0, #0 800feae: 6031 str r1, [r6, #0] 800feb0: 602b str r3, [r5, #0] 800feb2: b016 add sp, #88 @ 0x58 800feb4: bd70 pop {r4, r5, r6, pc} 800feb6: 466a mov r2, sp 800feb8: f000 f848 bl 800ff4c <_fstat_r> 800febc: 2800 cmp r0, #0 800febe: dbec blt.n 800fe9a <__swhatbuf_r+0x12> 800fec0: 9901 ldr r1, [sp, #4] 800fec2: f401 4170 and.w r1, r1, #61440 @ 0xf000 800fec6: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 800feca: 4259 negs r1, r3 800fecc: 4159 adcs r1, r3 800fece: f44f 6380 mov.w r3, #1024 @ 0x400 800fed2: e7eb b.n 800feac <__swhatbuf_r+0x24> 0800fed4 <__smakebuf_r>: 800fed4: 898b ldrh r3, [r1, #12] 800fed6: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 800fed8: 079d lsls r5, r3, #30 800feda: 4606 mov r6, r0 800fedc: 460c mov r4, r1 800fede: d507 bpl.n 800fef0 <__smakebuf_r+0x1c> 800fee0: f104 0347 add.w r3, r4, #71 @ 0x47 800fee4: 6023 str r3, [r4, #0] 800fee6: 6123 str r3, [r4, #16] 800fee8: 2301 movs r3, #1 800feea: 6163 str r3, [r4, #20] 800feec: b003 add sp, #12 800feee: bdf0 pop {r4, r5, r6, r7, pc} 800fef0: ab01 add r3, sp, #4 800fef2: 466a mov r2, sp 800fef4: f7ff ffc8 bl 800fe88 <__swhatbuf_r> 800fef8: 9f00 ldr r7, [sp, #0] 800fefa: 4605 mov r5, r0 800fefc: 4639 mov r1, r7 800fefe: 4630 mov r0, r6 800ff00: f7ff fb16 bl 800f530 <_malloc_r> 800ff04: b948 cbnz r0, 800ff1a <__smakebuf_r+0x46> 800ff06: f9b4 300c ldrsh.w r3, [r4, #12] 800ff0a: 059a lsls r2, r3, #22 800ff0c: d4ee bmi.n 800feec <__smakebuf_r+0x18> 800ff0e: f023 0303 bic.w r3, r3, #3 800ff12: f043 0302 orr.w r3, r3, #2 800ff16: 81a3 strh r3, [r4, #12] 800ff18: e7e2 b.n 800fee0 <__smakebuf_r+0xc> 800ff1a: 89a3 ldrh r3, [r4, #12] 800ff1c: 6020 str r0, [r4, #0] 800ff1e: f043 0380 orr.w r3, r3, #128 @ 0x80 800ff22: 81a3 strh r3, [r4, #12] 800ff24: 9b01 ldr r3, [sp, #4] 800ff26: e9c4 0704 strd r0, r7, [r4, #16] 800ff2a: b15b cbz r3, 800ff44 <__smakebuf_r+0x70> 800ff2c: f9b4 100e ldrsh.w r1, [r4, #14] 800ff30: 4630 mov r0, r6 800ff32: f000 f81d bl 800ff70 <_isatty_r> 800ff36: b128 cbz r0, 800ff44 <__smakebuf_r+0x70> 800ff38: 89a3 ldrh r3, [r4, #12] 800ff3a: f023 0303 bic.w r3, r3, #3 800ff3e: f043 0301 orr.w r3, r3, #1 800ff42: 81a3 strh r3, [r4, #12] 800ff44: 89a3 ldrh r3, [r4, #12] 800ff46: 431d orrs r5, r3 800ff48: 81a5 strh r5, [r4, #12] 800ff4a: e7cf b.n 800feec <__smakebuf_r+0x18> 0800ff4c <_fstat_r>: 800ff4c: b538 push {r3, r4, r5, lr} 800ff4e: 4d07 ldr r5, [pc, #28] @ (800ff6c <_fstat_r+0x20>) 800ff50: 2300 movs r3, #0 800ff52: 4604 mov r4, r0 800ff54: 4608 mov r0, r1 800ff56: 4611 mov r1, r2 800ff58: 602b str r3, [r5, #0] 800ff5a: f7f1 fd22 bl 80019a2 <_fstat> 800ff5e: 1c43 adds r3, r0, #1 800ff60: d102 bne.n 800ff68 <_fstat_r+0x1c> 800ff62: 682b ldr r3, [r5, #0] 800ff64: b103 cbz r3, 800ff68 <_fstat_r+0x1c> 800ff66: 6023 str r3, [r4, #0] 800ff68: bd38 pop {r3, r4, r5, pc} 800ff6a: bf00 nop 800ff6c: 240128b8 .word 0x240128b8 0800ff70 <_isatty_r>: 800ff70: b538 push {r3, r4, r5, lr} 800ff72: 4d06 ldr r5, [pc, #24] @ (800ff8c <_isatty_r+0x1c>) 800ff74: 2300 movs r3, #0 800ff76: 4604 mov r4, r0 800ff78: 4608 mov r0, r1 800ff7a: 602b str r3, [r5, #0] 800ff7c: f7f1 fd21 bl 80019c2 <_isatty> 800ff80: 1c43 adds r3, r0, #1 800ff82: d102 bne.n 800ff8a <_isatty_r+0x1a> 800ff84: 682b ldr r3, [r5, #0] 800ff86: b103 cbz r3, 800ff8a <_isatty_r+0x1a> 800ff88: 6023 str r3, [r4, #0] 800ff8a: bd38 pop {r3, r4, r5, pc} 800ff8c: 240128b8 .word 0x240128b8 0800ff90 <_init>: 800ff90: b5f8 push {r3, r4, r5, r6, r7, lr} 800ff92: bf00 nop 800ff94: bcf8 pop {r3, r4, r5, r6, r7} 800ff96: bc08 pop {r3} 800ff98: 469e mov lr, r3 800ff9a: 4770 bx lr 0800ff9c <_fini>: 800ff9c: b5f8 push {r3, r4, r5, r6, r7, lr} 800ff9e: bf00 nop 800ffa0: bcf8 pop {r3, r4, r5, r6, r7} 800ffa2: bc08 pop {r3} 800ffa4: 469e mov lr, r3 800ffa6: 4770 bx lr