OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000185c8 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 000001d4 08018868 08018868 00019868 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 08018a3c 08018a3c 00019a3c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 08018a44 08018a44 00019a44 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 08018a48 08018a48 00019a48 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 000000a4 24000000 08018a4c 0001a000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 00012d20 240000c0 08018af0 0001a0c0 2**5 ALLOC 8 ._user_heap_stack 00000600 24012de0 08018af0 0001ade0 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 0001a0a4 2**0 CONTENTS, READONLY 10 .debug_info 00033c84 00000000 00000000 0001a0d2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 0000628c 00000000 00000000 0004dd56 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 000024d0 00000000 00000000 00053fe8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003f37d 00000000 00000000 000564b8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 00030703 00000000 00000000 00095835 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00187ded 00000000 00000000 000c5f38 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 0024dd25 2**0 CONTENTS, READONLY 17 .debug_rnglists 00001c5b 00000000 00000000 0024dd68 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 0000a2e4 00000000 00000000 0024f9c4 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 00259ca8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 240000c0 .word 0x240000c0 80002bc: 00000000 .word 0x00000000 80002c0: 08018850 .word 0x08018850 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 240000c4 .word 0x240000c4 80002dc: 08018850 .word 0x08018850 080002e0 : 80002e0: f001 01ff and.w r1, r1, #255 @ 0xff 80002e4: 2a10 cmp r2, #16 80002e6: db2b blt.n 8000340 80002e8: f010 0f07 tst.w r0, #7 80002ec: d008 beq.n 8000300 80002ee: f810 3b01 ldrb.w r3, [r0], #1 80002f2: 3a01 subs r2, #1 80002f4: 428b cmp r3, r1 80002f6: d02d beq.n 8000354 80002f8: f010 0f07 tst.w r0, #7 80002fc: b342 cbz r2, 8000350 80002fe: d1f6 bne.n 80002ee 8000300: b4f0 push {r4, r5, r6, r7} 8000302: ea41 2101 orr.w r1, r1, r1, lsl #8 8000306: ea41 4101 orr.w r1, r1, r1, lsl #16 800030a: f022 0407 bic.w r4, r2, #7 800030e: f07f 0700 mvns.w r7, #0 8000312: 2300 movs r3, #0 8000314: e8f0 5602 ldrd r5, r6, [r0], #8 8000318: 3c08 subs r4, #8 800031a: ea85 0501 eor.w r5, r5, r1 800031e: ea86 0601 eor.w r6, r6, r1 8000322: fa85 f547 uadd8 r5, r5, r7 8000326: faa3 f587 sel r5, r3, r7 800032a: fa86 f647 uadd8 r6, r6, r7 800032e: faa5 f687 sel r6, r5, r7 8000332: b98e cbnz r6, 8000358 8000334: d1ee bne.n 8000314 8000336: bcf0 pop {r4, r5, r6, r7} 8000338: f001 01ff and.w r1, r1, #255 @ 0xff 800033c: f002 0207 and.w r2, r2, #7 8000340: b132 cbz r2, 8000350 8000342: f810 3b01 ldrb.w r3, [r0], #1 8000346: 3a01 subs r2, #1 8000348: ea83 0301 eor.w r3, r3, r1 800034c: b113 cbz r3, 8000354 800034e: d1f8 bne.n 8000342 8000350: 2000 movs r0, #0 8000352: 4770 bx lr 8000354: 3801 subs r0, #1 8000356: 4770 bx lr 8000358: 2d00 cmp r5, #0 800035a: bf06 itte eq 800035c: 4635 moveq r5, r6 800035e: 3803 subeq r0, #3 8000360: 3807 subne r0, #7 8000362: f015 0f01 tst.w r5, #1 8000366: d107 bne.n 8000378 8000368: 3001 adds r0, #1 800036a: f415 7f80 tst.w r5, #256 @ 0x100 800036e: bf02 ittt eq 8000370: 3001 addeq r0, #1 8000372: f415 3fc0 tsteq.w r5, #98304 @ 0x18000 8000376: 3001 addeq r0, #1 8000378: bcf0 pop {r4, r5, r6, r7} 800037a: 3801 subs r0, #1 800037c: 4770 bx lr 800037e: bf00 nop 08000380 <__aeabi_uldivmod>: 8000380: b953 cbnz r3, 8000398 <__aeabi_uldivmod+0x18> 8000382: b94a cbnz r2, 8000398 <__aeabi_uldivmod+0x18> 8000384: 2900 cmp r1, #0 8000386: bf08 it eq 8000388: 2800 cmpeq r0, #0 800038a: bf1c itt ne 800038c: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000390: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000394: f000 b96a b.w 800066c <__aeabi_idiv0> 8000398: f1ad 0c08 sub.w ip, sp, #8 800039c: e96d ce04 strd ip, lr, [sp, #-16]! 80003a0: f000 f806 bl 80003b0 <__udivmoddi4> 80003a4: f8dd e004 ldr.w lr, [sp, #4] 80003a8: e9dd 2302 ldrd r2, r3, [sp, #8] 80003ac: b004 add sp, #16 80003ae: 4770 bx lr 080003b0 <__udivmoddi4>: 80003b0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 80003b4: 9d08 ldr r5, [sp, #32] 80003b6: 460c mov r4, r1 80003b8: 2b00 cmp r3, #0 80003ba: d14e bne.n 800045a <__udivmoddi4+0xaa> 80003bc: 4694 mov ip, r2 80003be: 458c cmp ip, r1 80003c0: 4686 mov lr, r0 80003c2: fab2 f282 clz r2, r2 80003c6: d962 bls.n 800048e <__udivmoddi4+0xde> 80003c8: b14a cbz r2, 80003de <__udivmoddi4+0x2e> 80003ca: f1c2 0320 rsb r3, r2, #32 80003ce: 4091 lsls r1, r2 80003d0: fa20 f303 lsr.w r3, r0, r3 80003d4: fa0c fc02 lsl.w ip, ip, r2 80003d8: 4319 orrs r1, r3 80003da: fa00 fe02 lsl.w lr, r0, r2 80003de: ea4f 471c mov.w r7, ip, lsr #16 80003e2: fa1f f68c uxth.w r6, ip 80003e6: fbb1 f4f7 udiv r4, r1, r7 80003ea: ea4f 431e mov.w r3, lr, lsr #16 80003ee: fb07 1114 mls r1, r7, r4, r1 80003f2: ea43 4301 orr.w r3, r3, r1, lsl #16 80003f6: fb04 f106 mul.w r1, r4, r6 80003fa: 4299 cmp r1, r3 80003fc: d90a bls.n 8000414 <__udivmoddi4+0x64> 80003fe: eb1c 0303 adds.w r3, ip, r3 8000402: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000406: f080 8112 bcs.w 800062e <__udivmoddi4+0x27e> 800040a: 4299 cmp r1, r3 800040c: f240 810f bls.w 800062e <__udivmoddi4+0x27e> 8000410: 3c02 subs r4, #2 8000412: 4463 add r3, ip 8000414: 1a59 subs r1, r3, r1 8000416: fa1f f38e uxth.w r3, lr 800041a: fbb1 f0f7 udiv r0, r1, r7 800041e: fb07 1110 mls r1, r7, r0, r1 8000422: ea43 4301 orr.w r3, r3, r1, lsl #16 8000426: fb00 f606 mul.w r6, r0, r6 800042a: 429e cmp r6, r3 800042c: d90a bls.n 8000444 <__udivmoddi4+0x94> 800042e: eb1c 0303 adds.w r3, ip, r3 8000432: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000436: f080 80fc bcs.w 8000632 <__udivmoddi4+0x282> 800043a: 429e cmp r6, r3 800043c: f240 80f9 bls.w 8000632 <__udivmoddi4+0x282> 8000440: 4463 add r3, ip 8000442: 3802 subs r0, #2 8000444: 1b9b subs r3, r3, r6 8000446: ea40 4004 orr.w r0, r0, r4, lsl #16 800044a: 2100 movs r1, #0 800044c: b11d cbz r5, 8000456 <__udivmoddi4+0xa6> 800044e: 40d3 lsrs r3, r2 8000450: 2200 movs r2, #0 8000452: e9c5 3200 strd r3, r2, [r5] 8000456: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800045a: 428b cmp r3, r1 800045c: d905 bls.n 800046a <__udivmoddi4+0xba> 800045e: b10d cbz r5, 8000464 <__udivmoddi4+0xb4> 8000460: e9c5 0100 strd r0, r1, [r5] 8000464: 2100 movs r1, #0 8000466: 4608 mov r0, r1 8000468: e7f5 b.n 8000456 <__udivmoddi4+0xa6> 800046a: fab3 f183 clz r1, r3 800046e: 2900 cmp r1, #0 8000470: d146 bne.n 8000500 <__udivmoddi4+0x150> 8000472: 42a3 cmp r3, r4 8000474: d302 bcc.n 800047c <__udivmoddi4+0xcc> 8000476: 4290 cmp r0, r2 8000478: f0c0 80f0 bcc.w 800065c <__udivmoddi4+0x2ac> 800047c: 1a86 subs r6, r0, r2 800047e: eb64 0303 sbc.w r3, r4, r3 8000482: 2001 movs r0, #1 8000484: 2d00 cmp r5, #0 8000486: d0e6 beq.n 8000456 <__udivmoddi4+0xa6> 8000488: e9c5 6300 strd r6, r3, [r5] 800048c: e7e3 b.n 8000456 <__udivmoddi4+0xa6> 800048e: 2a00 cmp r2, #0 8000490: f040 8090 bne.w 80005b4 <__udivmoddi4+0x204> 8000494: eba1 040c sub.w r4, r1, ip 8000498: ea4f 481c mov.w r8, ip, lsr #16 800049c: fa1f f78c uxth.w r7, ip 80004a0: 2101 movs r1, #1 80004a2: fbb4 f6f8 udiv r6, r4, r8 80004a6: ea4f 431e mov.w r3, lr, lsr #16 80004aa: fb08 4416 mls r4, r8, r6, r4 80004ae: ea43 4304 orr.w r3, r3, r4, lsl #16 80004b2: fb07 f006 mul.w r0, r7, r6 80004b6: 4298 cmp r0, r3 80004b8: d908 bls.n 80004cc <__udivmoddi4+0x11c> 80004ba: eb1c 0303 adds.w r3, ip, r3 80004be: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 80004c2: d202 bcs.n 80004ca <__udivmoddi4+0x11a> 80004c4: 4298 cmp r0, r3 80004c6: f200 80cd bhi.w 8000664 <__udivmoddi4+0x2b4> 80004ca: 4626 mov r6, r4 80004cc: 1a1c subs r4, r3, r0 80004ce: fa1f f38e uxth.w r3, lr 80004d2: fbb4 f0f8 udiv r0, r4, r8 80004d6: fb08 4410 mls r4, r8, r0, r4 80004da: ea43 4304 orr.w r3, r3, r4, lsl #16 80004de: fb00 f707 mul.w r7, r0, r7 80004e2: 429f cmp r7, r3 80004e4: d908 bls.n 80004f8 <__udivmoddi4+0x148> 80004e6: eb1c 0303 adds.w r3, ip, r3 80004ea: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 80004ee: d202 bcs.n 80004f6 <__udivmoddi4+0x146> 80004f0: 429f cmp r7, r3 80004f2: f200 80b0 bhi.w 8000656 <__udivmoddi4+0x2a6> 80004f6: 4620 mov r0, r4 80004f8: 1bdb subs r3, r3, r7 80004fa: ea40 4006 orr.w r0, r0, r6, lsl #16 80004fe: e7a5 b.n 800044c <__udivmoddi4+0x9c> 8000500: f1c1 0620 rsb r6, r1, #32 8000504: 408b lsls r3, r1 8000506: fa22 f706 lsr.w r7, r2, r6 800050a: 431f orrs r7, r3 800050c: fa20 fc06 lsr.w ip, r0, r6 8000510: fa04 f301 lsl.w r3, r4, r1 8000514: ea43 030c orr.w r3, r3, ip 8000518: 40f4 lsrs r4, r6 800051a: fa00 f801 lsl.w r8, r0, r1 800051e: 0c38 lsrs r0, r7, #16 8000520: ea4f 4913 mov.w r9, r3, lsr #16 8000524: fbb4 fef0 udiv lr, r4, r0 8000528: fa1f fc87 uxth.w ip, r7 800052c: fb00 441e mls r4, r0, lr, r4 8000530: ea49 4404 orr.w r4, r9, r4, lsl #16 8000534: fb0e f90c mul.w r9, lr, ip 8000538: 45a1 cmp r9, r4 800053a: fa02 f201 lsl.w r2, r2, r1 800053e: d90a bls.n 8000556 <__udivmoddi4+0x1a6> 8000540: 193c adds r4, r7, r4 8000542: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 8000546: f080 8084 bcs.w 8000652 <__udivmoddi4+0x2a2> 800054a: 45a1 cmp r9, r4 800054c: f240 8081 bls.w 8000652 <__udivmoddi4+0x2a2> 8000550: f1ae 0e02 sub.w lr, lr, #2 8000554: 443c add r4, r7 8000556: eba4 0409 sub.w r4, r4, r9 800055a: fa1f f983 uxth.w r9, r3 800055e: fbb4 f3f0 udiv r3, r4, r0 8000562: fb00 4413 mls r4, r0, r3, r4 8000566: ea49 4404 orr.w r4, r9, r4, lsl #16 800056a: fb03 fc0c mul.w ip, r3, ip 800056e: 45a4 cmp ip, r4 8000570: d907 bls.n 8000582 <__udivmoddi4+0x1d2> 8000572: 193c adds r4, r7, r4 8000574: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 8000578: d267 bcs.n 800064a <__udivmoddi4+0x29a> 800057a: 45a4 cmp ip, r4 800057c: d965 bls.n 800064a <__udivmoddi4+0x29a> 800057e: 3b02 subs r3, #2 8000580: 443c add r4, r7 8000582: ea43 400e orr.w r0, r3, lr, lsl #16 8000586: fba0 9302 umull r9, r3, r0, r2 800058a: eba4 040c sub.w r4, r4, ip 800058e: 429c cmp r4, r3 8000590: 46ce mov lr, r9 8000592: 469c mov ip, r3 8000594: d351 bcc.n 800063a <__udivmoddi4+0x28a> 8000596: d04e beq.n 8000636 <__udivmoddi4+0x286> 8000598: b155 cbz r5, 80005b0 <__udivmoddi4+0x200> 800059a: ebb8 030e subs.w r3, r8, lr 800059e: eb64 040c sbc.w r4, r4, ip 80005a2: fa04 f606 lsl.w r6, r4, r6 80005a6: 40cb lsrs r3, r1 80005a8: 431e orrs r6, r3 80005aa: 40cc lsrs r4, r1 80005ac: e9c5 6400 strd r6, r4, [r5] 80005b0: 2100 movs r1, #0 80005b2: e750 b.n 8000456 <__udivmoddi4+0xa6> 80005b4: f1c2 0320 rsb r3, r2, #32 80005b8: fa20 f103 lsr.w r1, r0, r3 80005bc: fa0c fc02 lsl.w ip, ip, r2 80005c0: fa24 f303 lsr.w r3, r4, r3 80005c4: 4094 lsls r4, r2 80005c6: 430c orrs r4, r1 80005c8: ea4f 481c mov.w r8, ip, lsr #16 80005cc: fa00 fe02 lsl.w lr, r0, r2 80005d0: fa1f f78c uxth.w r7, ip 80005d4: fbb3 f0f8 udiv r0, r3, r8 80005d8: fb08 3110 mls r1, r8, r0, r3 80005dc: 0c23 lsrs r3, r4, #16 80005de: ea43 4301 orr.w r3, r3, r1, lsl #16 80005e2: fb00 f107 mul.w r1, r0, r7 80005e6: 4299 cmp r1, r3 80005e8: d908 bls.n 80005fc <__udivmoddi4+0x24c> 80005ea: eb1c 0303 adds.w r3, ip, r3 80005ee: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 80005f2: d22c bcs.n 800064e <__udivmoddi4+0x29e> 80005f4: 4299 cmp r1, r3 80005f6: d92a bls.n 800064e <__udivmoddi4+0x29e> 80005f8: 3802 subs r0, #2 80005fa: 4463 add r3, ip 80005fc: 1a5b subs r3, r3, r1 80005fe: b2a4 uxth r4, r4 8000600: fbb3 f1f8 udiv r1, r3, r8 8000604: fb08 3311 mls r3, r8, r1, r3 8000608: ea44 4403 orr.w r4, r4, r3, lsl #16 800060c: fb01 f307 mul.w r3, r1, r7 8000610: 42a3 cmp r3, r4 8000612: d908 bls.n 8000626 <__udivmoddi4+0x276> 8000614: eb1c 0404 adds.w r4, ip, r4 8000618: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800061c: d213 bcs.n 8000646 <__udivmoddi4+0x296> 800061e: 42a3 cmp r3, r4 8000620: d911 bls.n 8000646 <__udivmoddi4+0x296> 8000622: 3902 subs r1, #2 8000624: 4464 add r4, ip 8000626: 1ae4 subs r4, r4, r3 8000628: ea41 4100 orr.w r1, r1, r0, lsl #16 800062c: e739 b.n 80004a2 <__udivmoddi4+0xf2> 800062e: 4604 mov r4, r0 8000630: e6f0 b.n 8000414 <__udivmoddi4+0x64> 8000632: 4608 mov r0, r1 8000634: e706 b.n 8000444 <__udivmoddi4+0x94> 8000636: 45c8 cmp r8, r9 8000638: d2ae bcs.n 8000598 <__udivmoddi4+0x1e8> 800063a: ebb9 0e02 subs.w lr, r9, r2 800063e: eb63 0c07 sbc.w ip, r3, r7 8000642: 3801 subs r0, #1 8000644: e7a8 b.n 8000598 <__udivmoddi4+0x1e8> 8000646: 4631 mov r1, r6 8000648: e7ed b.n 8000626 <__udivmoddi4+0x276> 800064a: 4603 mov r3, r0 800064c: e799 b.n 8000582 <__udivmoddi4+0x1d2> 800064e: 4630 mov r0, r6 8000650: e7d4 b.n 80005fc <__udivmoddi4+0x24c> 8000652: 46d6 mov lr, sl 8000654: e77f b.n 8000556 <__udivmoddi4+0x1a6> 8000656: 4463 add r3, ip 8000658: 3802 subs r0, #2 800065a: e74d b.n 80004f8 <__udivmoddi4+0x148> 800065c: 4606 mov r6, r0 800065e: 4623 mov r3, r4 8000660: 4608 mov r0, r1 8000662: e70f b.n 8000484 <__udivmoddi4+0xd4> 8000664: 3e02 subs r6, #2 8000666: 4463 add r3, ip 8000668: e730 b.n 80004cc <__udivmoddi4+0x11c> 800066a: bf00 nop 0800066c <__aeabi_idiv0>: 800066c: 4770 bx lr 800066e: bf00 nop 08000670 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 8000670: b480 push {r7} 8000672: b083 sub sp, #12 8000674: af00 add r7, sp, #0 8000676: 6078 str r0, [r7, #4] 8000678: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 800067a: bf00 nop 800067c: 370c adds r7, #12 800067e: 46bd mov sp, r7 8000680: f85d 7b04 ldr.w r7, [sp], #4 8000684: 4770 bx lr ... 08000688 <__io_putchar>: /* USER CODE END PFP */ /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ int __io_putchar(int ch) { 8000688: b580 push {r7, lr} 800068a: b082 sub sp, #8 800068c: af00 add r7, sp, #0 800068e: 6078 str r0, [r7, #4] #if UART_TASK_LOGS HAL_UART_Transmit(&huart8, (uint8_t *)&ch, 1, 0xFFFF); // Use UART8 as debug interface 8000690: 1d39 adds r1, r7, #4 8000692: f64f 73ff movw r3, #65535 @ 0xffff 8000696: 2201 movs r2, #1 8000698: 4803 ldr r0, [pc, #12] @ (80006a8 <__io_putchar+0x20>) 800069a: f010 f961 bl 8010960 // ITM_SendChar(ch); // Use SWV as debug interface #endif return ch; 800069e: 687b ldr r3, [r7, #4] } 80006a0: 4618 mov r0, r3 80006a2: 3708 adds r7, #8 80006a4: 46bd mov sp, r7 80006a6: bd80 pop {r7, pc} 80006a8: 2400057c .word 0x2400057c 080006ac : void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 80006ac: b580 push {r7, lr} 80006ae: b084 sub sp, #16 80006b0: af00 add r7, sp, #0 80006b2: 4603 mov r3, r0 80006b4: 80fb strh r3, [r7, #6] LimiterSwitchData limiterSwitchData = { 0 }; 80006b6: 2300 movs r3, #0 80006b8: 60fb str r3, [r7, #12] limiterSwitchData.gpioPin = GPIO_Pin; 80006ba: 88fb ldrh r3, [r7, #6] 80006bc: 81bb strh r3, [r7, #12] limiterSwitchData.pinState = HAL_GPIO_ReadPin(GPIOD, GPIO_Pin); 80006be: 88fb ldrh r3, [r7, #6] 80006c0: 4619 mov r1, r3 80006c2: 4808 ldr r0, [pc, #32] @ (80006e4 ) 80006c4: f00a fa12 bl 800aaec 80006c8: 4603 mov r3, r0 80006ca: 73bb strb r3, [r7, #14] osMessageQueuePut(limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 80006cc: 4b06 ldr r3, [pc, #24] @ (80006e8 ) 80006ce: 6818 ldr r0, [r3, #0] 80006d0: f107 010c add.w r1, r7, #12 80006d4: 2300 movs r3, #0 80006d6: 2200 movs r2, #0 80006d8: f013 faf8 bl 8013ccc } 80006dc: bf00 nop 80006de: 3710 adds r7, #16 80006e0: 46bd mov sp, r7 80006e2: bd80 pop {r7, pc} 80006e4: 58020c00 .word 0x58020c00 80006e8: 240007d4 .word 0x240007d4 080006ec
: /** * @brief The application entry point. * @retval int */ int main(void) { 80006ec: b580 push {r7, lr} 80006ee: b084 sub sp, #16 80006f0: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 80006f2: f001 fadd bl 8001cb0 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80006f6: 4b5e ldr r3, [pc, #376] @ (8000870 ) 80006f8: 695b ldr r3, [r3, #20] 80006fa: f403 3300 and.w r3, r3, #131072 @ 0x20000 80006fe: 2b00 cmp r3, #0 8000700: d11b bne.n 800073a \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 8000702: f3bf 8f4f dsb sy } 8000706: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000708: f3bf 8f6f isb sy } 800070c: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 800070e: 4b58 ldr r3, [pc, #352] @ (8000870 ) 8000710: 2200 movs r2, #0 8000712: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 8000716: f3bf 8f4f dsb sy } 800071a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800071c: f3bf 8f6f isb sy } 8000720: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 8000722: 4b53 ldr r3, [pc, #332] @ (8000870 ) 8000724: 695b ldr r3, [r3, #20] 8000726: 4a52 ldr r2, [pc, #328] @ (8000870 ) 8000728: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800072c: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 800072e: f3bf 8f4f dsb sy } 8000732: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000734: f3bf 8f6f isb sy } 8000738: e000 b.n 800073c if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 800073a: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 800073c: 4b4c ldr r3, [pc, #304] @ (8000870 ) 800073e: 695b ldr r3, [r3, #20] 8000740: f403 3380 and.w r3, r3, #65536 @ 0x10000 8000744: 2b00 cmp r3, #0 8000746: d138 bne.n 80007ba SCB->CSSELR = 0U; /* select Level 1 data cache */ 8000748: 4b49 ldr r3, [pc, #292] @ (8000870 ) 800074a: 2200 movs r2, #0 800074c: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 8000750: f3bf 8f4f dsb sy } 8000754: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 8000756: 4b46 ldr r3, [pc, #280] @ (8000870 ) 8000758: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800075c: 60fb str r3, [r7, #12] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 800075e: 68fb ldr r3, [r7, #12] 8000760: 0b5b lsrs r3, r3, #13 8000762: f3c3 030e ubfx r3, r3, #0, #15 8000766: 60bb str r3, [r7, #8] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 8000768: 68fb ldr r3, [r7, #12] 800076a: 08db lsrs r3, r3, #3 800076c: f3c3 0309 ubfx r3, r3, #0, #10 8000770: 607b str r3, [r7, #4] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000772: 68bb ldr r3, [r7, #8] 8000774: 015a lsls r2, r3, #5 8000776: f643 73e0 movw r3, #16352 @ 0x3fe0 800077a: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 800077c: 687a ldr r2, [r7, #4] 800077e: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 8000780: 493b ldr r1, [pc, #236] @ (8000870 ) 8000782: 4313 orrs r3, r2 8000784: f8c1 3260 str.w r3, [r1, #608] @ 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 8000788: 687b ldr r3, [r7, #4] 800078a: 1e5a subs r2, r3, #1 800078c: 607a str r2, [r7, #4] 800078e: 2b00 cmp r3, #0 8000790: d1ef bne.n 8000772 } while(sets-- != 0U); 8000792: 68bb ldr r3, [r7, #8] 8000794: 1e5a subs r2, r3, #1 8000796: 60ba str r2, [r7, #8] 8000798: 2b00 cmp r3, #0 800079a: d1e5 bne.n 8000768 __ASM volatile ("dsb 0xF":::"memory"); 800079c: f3bf 8f4f dsb sy } 80007a0: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 80007a2: 4b33 ldr r3, [pc, #204] @ (8000870 ) 80007a4: 695b ldr r3, [r3, #20] 80007a6: 4a32 ldr r2, [pc, #200] @ (8000870 ) 80007a8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80007ac: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 80007ae: f3bf 8f4f dsb sy } 80007b2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80007b4: f3bf 8f6f isb sy } 80007b8: e000 b.n 80007bc if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80007ba: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80007bc: f004 fdbe bl 800533c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80007c0: f000 f876 bl 80008b0 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 80007c4: f000 f8f0 bl 80009a8 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80007c8: f000 ff06 bl 80015d8 MX_DMA_Init(); 80007cc: f000 fed4 bl 8001578 MX_RNG_Init(); 80007d0: f000 fbdc bl 8000f8c MX_USART1_UART_Init(); 80007d4: f000 fe80 bl 80014d8 MX_ADC1_Init(); 80007d8: f000 f916 bl 8000a08 MX_UART8_Init(); 80007dc: f000 fe30 bl 8001440 MX_CRC_Init(); 80007e0: f000 fb6e bl 8000ec0 MX_ADC2_Init(); 80007e4: f000 f9fa bl 8000bdc MX_ADC3_Init(); 80007e8: f000 fa8c bl 8000d04 MX_TIM2_Init(); 80007ec: f000 fc80 bl 80010f0 MX_TIM1_Init(); 80007f0: f000 fbe2 bl 8000fb8 MX_TIM3_Init(); 80007f4: f000 fcfa bl 80011ec MX_DAC1_Init(); 80007f8: f000 fb8c bl 8000f14 MX_COMP1_Init(); 80007fc: f000 fb32 bl 8000e64 MX_TIM4_Init(); 8000800: f000 fda0 bl 8001344 /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 8000804: f012 fef2 bl 80135ec /* add semaphores, ... */ /* USER CODE END RTOS_SEMAPHORES */ /* Create the timer(s) */ /* creation of debugLedTimer */ debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 8000808: 4b1a ldr r3, [pc, #104] @ (8000874 ) 800080a: 2200 movs r2, #0 800080c: 2100 movs r1, #0 800080e: 481a ldr r0, [pc, #104] @ (8000878 ) 8000810: f012 fffa bl 8013808 8000814: 4603 mov r3, r0 8000816: 4a19 ldr r2, [pc, #100] @ (800087c ) 8000818: 6013 str r3, [r2, #0] /* creation of fanTimer */ fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 800081a: 4b19 ldr r3, [pc, #100] @ (8000880 ) 800081c: 2200 movs r2, #0 800081e: 2100 movs r1, #0 8000820: 4818 ldr r0, [pc, #96] @ (8000884 ) 8000822: f012 fff1 bl 8013808 8000826: 4603 mov r3, r0 8000828: 4a17 ldr r2, [pc, #92] @ (8000888 ) 800082a: 6013 str r3, [r2, #0] /* creation of motorXTimer */ motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 800082c: 4b17 ldr r3, [pc, #92] @ (800088c ) 800082e: 2200 movs r2, #0 8000830: 2101 movs r1, #1 8000832: 4817 ldr r0, [pc, #92] @ (8000890 ) 8000834: f012 ffe8 bl 8013808 8000838: 4603 mov r3, r0 800083a: 4a16 ldr r2, [pc, #88] @ (8000894 ) 800083c: 6013 str r3, [r2, #0] /* creation of motorYTimer */ motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 800083e: 4b16 ldr r3, [pc, #88] @ (8000898 ) 8000840: 2200 movs r2, #0 8000842: 2101 movs r1, #1 8000844: 4815 ldr r0, [pc, #84] @ (800089c ) 8000846: f012 ffdf bl 8013808 800084a: 4603 mov r3, r0 800084c: 4a14 ldr r2, [pc, #80] @ (80008a0 ) 800084e: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 8000850: 4a14 ldr r2, [pc, #80] @ (80008a4 ) 8000852: 2100 movs r1, #0 8000854: 4814 ldr r0, [pc, #80] @ (80008a8 ) 8000856: f012 ff13 bl 8013680 800085a: 4603 mov r3, r0 800085c: 4a13 ldr r2, [pc, #76] @ (80008ac ) 800085e: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ // Uart8TasksInit(); UartTasksInit(); 8000860: f003 fcc8 bl 80041f4 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); #else MeasTasksInit(); 8000864: f001 fada bl 8001e1c /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 8000868: f012 fee4 bl 8013634 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 800086c: bf00 nop 800086e: e7fd b.n 800086c 8000870: e000ed00 .word 0xe000ed00 8000874: 08018988 .word 0x08018988 8000878: 08001c05 .word 0x08001c05 800087c: 240006a8 .word 0x240006a8 8000880: 08018998 .word 0x08018998 8000884: 08001c1d .word 0x08001c1d 8000888: 240006d8 .word 0x240006d8 800088c: 080189a8 .word 0x080189a8 8000890: 08001c39 .word 0x08001c39 8000894: 24000708 .word 0x24000708 8000898: 080189b8 .word 0x080189b8 800089c: 08001c75 .word 0x08001c75 80008a0: 24000738 .word 0x24000738 80008a4: 08018964 .word 0x08018964 80008a8: 08001a75 .word 0x08001a75 80008ac: 240006a4 .word 0x240006a4 080008b0 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80008b0: b580 push {r7, lr} 80008b2: b09c sub sp, #112 @ 0x70 80008b4: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80008b6: f107 0324 add.w r3, r7, #36 @ 0x24 80008ba: 224c movs r2, #76 @ 0x4c 80008bc: 2100 movs r1, #0 80008be: 4618 mov r0, r3 80008c0: f017 f949 bl 8017b56 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80008c4: 1d3b adds r3, r7, #4 80008c6: 2220 movs r2, #32 80008c8: 2100 movs r1, #0 80008ca: 4618 mov r0, r3 80008cc: f017 f943 bl 8017b56 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 80008d0: 2002 movs r0, #2 80008d2: f00a f9fb bl 800accc /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 80008d6: 2300 movs r3, #0 80008d8: 603b str r3, [r7, #0] 80008da: 4b31 ldr r3, [pc, #196] @ (80009a0 ) 80008dc: 6adb ldr r3, [r3, #44] @ 0x2c 80008de: 4a30 ldr r2, [pc, #192] @ (80009a0 ) 80008e0: f023 0301 bic.w r3, r3, #1 80008e4: 62d3 str r3, [r2, #44] @ 0x2c 80008e6: 4b2e ldr r3, [pc, #184] @ (80009a0 ) 80008e8: 6adb ldr r3, [r3, #44] @ 0x2c 80008ea: f003 0301 and.w r3, r3, #1 80008ee: 603b str r3, [r7, #0] 80008f0: 4b2c ldr r3, [pc, #176] @ (80009a4 ) 80008f2: 699b ldr r3, [r3, #24] 80008f4: 4a2b ldr r2, [pc, #172] @ (80009a4 ) 80008f6: f443 4340 orr.w r3, r3, #49152 @ 0xc000 80008fa: 6193 str r3, [r2, #24] 80008fc: 4b29 ldr r3, [pc, #164] @ (80009a4 ) 80008fe: 699b ldr r3, [r3, #24] 8000900: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000904: 603b str r3, [r7, #0] 8000906: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 8000908: bf00 nop 800090a: 4b26 ldr r3, [pc, #152] @ (80009a4 ) 800090c: 699b ldr r3, [r3, #24] 800090e: f403 5300 and.w r3, r3, #8192 @ 0x2000 8000912: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8000916: d1f8 bne.n 800090a /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; 8000918: 2321 movs r3, #33 @ 0x21 800091a: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 800091c: f44f 3380 mov.w r3, #65536 @ 0x10000 8000920: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 8000922: 2301 movs r3, #1 8000924: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000926: 2302 movs r3, #2 8000928: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 800092a: 2302 movs r3, #2 800092c: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 800092e: 2305 movs r3, #5 8000930: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 8000932: 23a0 movs r3, #160 @ 0xa0 8000934: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 8000936: 2302 movs r3, #2 8000938: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 800093a: 2302 movs r3, #2 800093c: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 800093e: 2302 movs r3, #2 8000940: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 8000942: 2308 movs r3, #8 8000944: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 8000946: 2300 movs r3, #0 8000948: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 800094a: 2300 movs r3, #0 800094c: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 800094e: f107 0324 add.w r3, r7, #36 @ 0x24 8000952: 4618 mov r0, r3 8000954: f00a fa7a bl 800ae4c 8000958: 4603 mov r3, r0 800095a: 2b00 cmp r3, #0 800095c: d001 beq.n 8000962 { Error_Handler(); 800095e: f001 fa57 bl 8001e10 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000962: 233f movs r3, #63 @ 0x3f 8000964: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000966: 2303 movs r3, #3 8000968: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 800096a: 2300 movs r3, #0 800096c: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 800096e: 2308 movs r3, #8 8000970: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 8000972: 2340 movs r3, #64 @ 0x40 8000974: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 8000976: 2340 movs r3, #64 @ 0x40 8000978: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 800097a: f44f 6380 mov.w r3, #1024 @ 0x400 800097e: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000980: 2340 movs r3, #64 @ 0x40 8000982: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8000984: 1d3b adds r3, r7, #4 8000986: 2102 movs r1, #2 8000988: 4618 mov r0, r3 800098a: f00a feb9 bl 800b700 800098e: 4603 mov r3, r0 8000990: 2b00 cmp r3, #0 8000992: d001 beq.n 8000998 { Error_Handler(); 8000994: f001 fa3c bl 8001e10 } } 8000998: bf00 nop 800099a: 3770 adds r7, #112 @ 0x70 800099c: 46bd mov sp, r7 800099e: bd80 pop {r7, pc} 80009a0: 58000400 .word 0x58000400 80009a4: 58024800 .word 0x58024800 080009a8 : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 80009a8: b580 push {r7, lr} 80009aa: b0b0 sub sp, #192 @ 0xc0 80009ac: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80009ae: 463b mov r3, r7 80009b0: 22c0 movs r2, #192 @ 0xc0 80009b2: 2100 movs r1, #0 80009b4: 4618 mov r0, r3 80009b6: f017 f8ce bl 8017b56 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 80009ba: f44f 2200 mov.w r2, #524288 @ 0x80000 80009be: f04f 0300 mov.w r3, #0 80009c2: e9c7 2300 strd r2, r3, [r7] PeriphClkInitStruct.PLL2.PLL2M = 5; 80009c6: 2305 movs r3, #5 80009c8: 60bb str r3, [r7, #8] PeriphClkInitStruct.PLL2.PLL2N = 52; 80009ca: 2334 movs r3, #52 @ 0x34 80009cc: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLL2.PLL2P = 26; 80009ce: 231a movs r3, #26 80009d0: 613b str r3, [r7, #16] PeriphClkInitStruct.PLL2.PLL2Q = 2; 80009d2: 2302 movs r3, #2 80009d4: 617b str r3, [r7, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 80009d6: 2302 movs r3, #2 80009d8: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 80009da: 2380 movs r3, #128 @ 0x80 80009dc: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 80009de: 2300 movs r3, #0 80009e0: 623b str r3, [r7, #32] PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 80009e2: 2300 movs r3, #0 80009e4: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 80009e6: 2300 movs r3, #0 80009e8: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80009ec: 463b mov r3, r7 80009ee: 4618 mov r0, r3 80009f0: f00b fa54 bl 800be9c 80009f4: 4603 mov r3, r0 80009f6: 2b00 cmp r3, #0 80009f8: d001 beq.n 80009fe { Error_Handler(); 80009fa: f001 fa09 bl 8001e10 } } 80009fe: bf00 nop 8000a00: 37c0 adds r7, #192 @ 0xc0 8000a02: 46bd mov sp, r7 8000a04: bd80 pop {r7, pc} ... 08000a08 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000a08: b580 push {r7, lr} 8000a0a: b08a sub sp, #40 @ 0x28 8000a0c: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000a0e: f107 031c add.w r3, r7, #28 8000a12: 2200 movs r2, #0 8000a14: 601a str r2, [r3, #0] 8000a16: 605a str r2, [r3, #4] 8000a18: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 8000a1a: 463b mov r3, r7 8000a1c: 2200 movs r2, #0 8000a1e: 601a str r2, [r3, #0] 8000a20: 605a str r2, [r3, #4] 8000a22: 609a str r2, [r3, #8] 8000a24: 60da str r2, [r3, #12] 8000a26: 611a str r2, [r3, #16] 8000a28: 615a str r2, [r3, #20] 8000a2a: 619a str r2, [r3, #24] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 8000a2c: 4b62 ldr r3, [pc, #392] @ (8000bb8 ) 8000a2e: 4a63 ldr r2, [pc, #396] @ (8000bbc ) 8000a30: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000a32: 4b61 ldr r3, [pc, #388] @ (8000bb8 ) 8000a34: 2200 movs r2, #0 8000a36: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 8000a38: 4b5f ldr r3, [pc, #380] @ (8000bb8 ) 8000a3a: 2200 movs r2, #0 8000a3c: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000a3e: 4b5e ldr r3, [pc, #376] @ (8000bb8 ) 8000a40: 2201 movs r2, #1 8000a42: 60da str r2, [r3, #12] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000a44: 4b5c ldr r3, [pc, #368] @ (8000bb8 ) 8000a46: 2208 movs r2, #8 8000a48: 611a str r2, [r3, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 8000a4a: 4b5b ldr r3, [pc, #364] @ (8000bb8 ) 8000a4c: 2200 movs r2, #0 8000a4e: 751a strb r2, [r3, #20] hadc1.Init.ContinuousConvMode = ENABLE; 8000a50: 4b59 ldr r3, [pc, #356] @ (8000bb8 ) 8000a52: 2201 movs r2, #1 8000a54: 755a strb r2, [r3, #21] hadc1.Init.NbrOfConversion = 7; 8000a56: 4b58 ldr r3, [pc, #352] @ (8000bb8 ) 8000a58: 2207 movs r2, #7 8000a5a: 619a str r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 8000a5c: 4b56 ldr r3, [pc, #344] @ (8000bb8 ) 8000a5e: 2200 movs r2, #0 8000a60: 771a strb r2, [r3, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8000a62: 4b55 ldr r3, [pc, #340] @ (8000bb8 ) 8000a64: f44f 62ac mov.w r2, #1376 @ 0x560 8000a68: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000a6a: 4b53 ldr r3, [pc, #332] @ (8000bb8 ) 8000a6c: f44f 6280 mov.w r2, #1024 @ 0x400 8000a70: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000a72: 4b51 ldr r3, [pc, #324] @ (8000bb8 ) 8000a74: 2201 movs r2, #1 8000a76: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000a78: 4b4f ldr r3, [pc, #316] @ (8000bb8 ) 8000a7a: 2200 movs r2, #0 8000a7c: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000a7e: 4b4e ldr r3, [pc, #312] @ (8000bb8 ) 8000a80: 2200 movs r2, #0 8000a82: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 8000a84: 4b4c ldr r3, [pc, #304] @ (8000bb8 ) 8000a86: 2200 movs r2, #0 8000a88: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000a8c: 484a ldr r0, [pc, #296] @ (8000bb8 ) 8000a8e: f004 ff05 bl 800589c 8000a92: 4603 mov r3, r0 8000a94: 2b00 cmp r3, #0 8000a96: d001 beq.n 8000a9c { Error_Handler(); 8000a98: f001 f9ba bl 8001e10 } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8000a9c: 2300 movs r3, #0 8000a9e: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000aa0: f107 031c add.w r3, r7, #28 8000aa4: 4619 mov r1, r3 8000aa6: 4844 ldr r0, [pc, #272] @ (8000bb8 ) 8000aa8: f006 f816 bl 8006ad8 8000aac: 4603 mov r3, r0 8000aae: 2b00 cmp r3, #0 8000ab0: d001 beq.n 8000ab6 { Error_Handler(); 8000ab2: f001 f9ad bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000ab6: 4b42 ldr r3, [pc, #264] @ (8000bc0 ) 8000ab8: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000aba: 2306 movs r3, #6 8000abc: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000abe: 2306 movs r3, #6 8000ac0: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000ac2: f240 73ff movw r3, #2047 @ 0x7ff 8000ac6: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000ac8: 2304 movs r3, #4 8000aca: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000acc: 2300 movs r3, #0 8000ace: 617b str r3, [r7, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000ad0: 2300 movs r3, #0 8000ad2: 767b strb r3, [r7, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ad4: 463b mov r3, r7 8000ad6: 4619 mov r1, r3 8000ad8: 4837 ldr r0, [pc, #220] @ (8000bb8 ) 8000ada: f005 f959 bl 8005d90 8000ade: 4603 mov r3, r0 8000ae0: 2b00 cmp r3, #0 8000ae2: d001 beq.n 8000ae8 { Error_Handler(); 8000ae4: f001 f994 bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 8000ae8: 4b36 ldr r3, [pc, #216] @ (8000bc4 ) 8000aea: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 8000aec: 230c movs r3, #12 8000aee: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000af0: 463b mov r3, r7 8000af2: 4619 mov r1, r3 8000af4: 4830 ldr r0, [pc, #192] @ (8000bb8 ) 8000af6: f005 f94b bl 8005d90 8000afa: 4603 mov r3, r0 8000afc: 2b00 cmp r3, #0 8000afe: d001 beq.n 8000b04 { Error_Handler(); 8000b00: f001 f986 bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8000b04: 4b30 ldr r3, [pc, #192] @ (8000bc8 ) 8000b06: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8000b08: 2312 movs r3, #18 8000b0a: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b0c: 463b mov r3, r7 8000b0e: 4619 mov r1, r3 8000b10: 4829 ldr r0, [pc, #164] @ (8000bb8 ) 8000b12: f005 f93d bl 8005d90 8000b16: 4603 mov r3, r0 8000b18: 2b00 cmp r3, #0 8000b1a: d001 beq.n 8000b20 { Error_Handler(); 8000b1c: f001 f978 bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; 8000b20: 4b2a ldr r3, [pc, #168] @ (8000bcc ) 8000b22: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 8000b24: 2318 movs r3, #24 8000b26: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b28: 463b mov r3, r7 8000b2a: 4619 mov r1, r3 8000b2c: 4822 ldr r0, [pc, #136] @ (8000bb8 ) 8000b2e: f005 f92f bl 8005d90 8000b32: 4603 mov r3, r0 8000b34: 2b00 cmp r3, #0 8000b36: d001 beq.n 8000b3c { Error_Handler(); 8000b38: f001 f96a bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_17; 8000b3c: 4b24 ldr r3, [pc, #144] @ (8000bd0 ) 8000b3e: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 8000b40: f44f 7380 mov.w r3, #256 @ 0x100 8000b44: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b46: 463b mov r3, r7 8000b48: 4619 mov r1, r3 8000b4a: 481b ldr r0, [pc, #108] @ (8000bb8 ) 8000b4c: f005 f920 bl 8005d90 8000b50: 4603 mov r3, r0 8000b52: 2b00 cmp r3, #0 8000b54: d001 beq.n 8000b5a { Error_Handler(); 8000b56: f001 f95b bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; 8000b5a: 4b1e ldr r3, [pc, #120] @ (8000bd4 ) 8000b5c: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8000b5e: f44f 7383 mov.w r3, #262 @ 0x106 8000b62: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b64: 463b mov r3, r7 8000b66: 4619 mov r1, r3 8000b68: 4813 ldr r0, [pc, #76] @ (8000bb8 ) 8000b6a: f005 f911 bl 8005d90 8000b6e: 4603 mov r3, r0 8000b70: 2b00 cmp r3, #0 8000b72: d001 beq.n 8000b78 { Error_Handler(); 8000b74: f001 f94c bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000b78: 4b17 ldr r3, [pc, #92] @ (8000bd8 ) 8000b7a: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_7; 8000b7c: f44f 7386 mov.w r3, #268 @ 0x10c 8000b80: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b82: 463b mov r3, r7 8000b84: 4619 mov r1, r3 8000b86: 480c ldr r0, [pc, #48] @ (8000bb8 ) 8000b88: f005 f902 bl 8005d90 8000b8c: 4603 mov r3, r0 8000b8e: 2b00 cmp r3, #0 8000b90: d001 beq.n 8000b96 { Error_Handler(); 8000b92: f001 f93d bl 8001e10 } /* USER CODE BEGIN ADC1_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000b96: f240 72ff movw r2, #2047 @ 0x7ff 8000b9a: f04f 1101 mov.w r1, #65537 @ 0x10001 8000b9e: 4806 ldr r0, [pc, #24] @ (8000bb8 ) 8000ba0: f005 ff36 bl 8006a10 8000ba4: 4603 mov r3, r0 8000ba6: 2b00 cmp r3, #0 8000ba8: d001 beq.n 8000bae { Error_Handler(); 8000baa: f001 f931 bl 8001e10 } /* USER CODE END ADC1_Init 2 */ } 8000bae: bf00 nop 8000bb0: 3728 adds r7, #40 @ 0x28 8000bb2: 46bd mov sp, r7 8000bb4: bd80 pop {r7, pc} 8000bb6: bf00 nop 8000bb8: 24000140 .word 0x24000140 8000bbc: 40022000 .word 0x40022000 8000bc0: 21800100 .word 0x21800100 8000bc4: 1d500080 .word 0x1d500080 8000bc8: 25b00200 .word 0x25b00200 8000bcc: 43210000 .word 0x43210000 8000bd0: 47520000 .word 0x47520000 8000bd4: 3ac04000 .word 0x3ac04000 8000bd8: 3ef08000 .word 0x3ef08000 08000bdc : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8000bdc: b580 push {r7, lr} 8000bde: b088 sub sp, #32 8000be0: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000be2: 1d3b adds r3, r7, #4 8000be4: 2200 movs r2, #0 8000be6: 601a str r2, [r3, #0] 8000be8: 605a str r2, [r3, #4] 8000bea: 609a str r2, [r3, #8] 8000bec: 60da str r2, [r3, #12] 8000bee: 611a str r2, [r3, #16] 8000bf0: 615a str r2, [r3, #20] 8000bf2: 619a str r2, [r3, #24] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000bf4: 4b3e ldr r3, [pc, #248] @ (8000cf0 ) 8000bf6: 4a3f ldr r2, [pc, #252] @ (8000cf4 ) 8000bf8: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000bfa: 4b3d ldr r3, [pc, #244] @ (8000cf0 ) 8000bfc: 2200 movs r2, #0 8000bfe: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_16B; 8000c00: 4b3b ldr r3, [pc, #236] @ (8000cf0 ) 8000c02: 2200 movs r2, #0 8000c04: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000c06: 4b3a ldr r3, [pc, #232] @ (8000cf0 ) 8000c08: 2201 movs r2, #1 8000c0a: 60da str r2, [r3, #12] hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000c0c: 4b38 ldr r3, [pc, #224] @ (8000cf0 ) 8000c0e: 2208 movs r2, #8 8000c10: 611a str r2, [r3, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000c12: 4b37 ldr r3, [pc, #220] @ (8000cf0 ) 8000c14: 2200 movs r2, #0 8000c16: 751a strb r2, [r3, #20] hadc2.Init.ContinuousConvMode = ENABLE; 8000c18: 4b35 ldr r3, [pc, #212] @ (8000cf0 ) 8000c1a: 2201 movs r2, #1 8000c1c: 755a strb r2, [r3, #21] hadc2.Init.NbrOfConversion = 3; 8000c1e: 4b34 ldr r3, [pc, #208] @ (8000cf0 ) 8000c20: 2203 movs r2, #3 8000c22: 619a str r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000c24: 4b32 ldr r3, [pc, #200] @ (8000cf0 ) 8000c26: 2200 movs r2, #0 8000c28: 771a strb r2, [r3, #28] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8000c2a: 4b31 ldr r3, [pc, #196] @ (8000cf0 ) 8000c2c: f44f 62ac mov.w r2, #1376 @ 0x560 8000c30: 625a str r2, [r3, #36] @ 0x24 hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000c32: 4b2f ldr r3, [pc, #188] @ (8000cf0 ) 8000c34: f44f 6280 mov.w r2, #1024 @ 0x400 8000c38: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000c3a: 4b2d ldr r3, [pc, #180] @ (8000cf0 ) 8000c3c: 2201 movs r2, #1 8000c3e: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000c40: 4b2b ldr r3, [pc, #172] @ (8000cf0 ) 8000c42: 2200 movs r2, #0 8000c44: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000c46: 4b2a ldr r3, [pc, #168] @ (8000cf0 ) 8000c48: 2200 movs r2, #0 8000c4a: 635a str r2, [r3, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000c4c: 4b28 ldr r3, [pc, #160] @ (8000cf0 ) 8000c4e: 2200 movs r2, #0 8000c50: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000c54: 4826 ldr r0, [pc, #152] @ (8000cf0 ) 8000c56: f004 fe21 bl 800589c 8000c5a: 4603 mov r3, r0 8000c5c: 2b00 cmp r3, #0 8000c5e: d001 beq.n 8000c64 { Error_Handler(); 8000c60: f001 f8d6 bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000c64: 4b24 ldr r3, [pc, #144] @ (8000cf8 ) 8000c66: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000c68: 2306 movs r3, #6 8000c6a: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000c6c: 2306 movs r3, #6 8000c6e: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000c70: f240 73ff movw r3, #2047 @ 0x7ff 8000c74: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000c76: 2304 movs r3, #4 8000c78: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000c7a: 2300 movs r3, #0 8000c7c: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000c7e: 2300 movs r3, #0 8000c80: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c82: 1d3b adds r3, r7, #4 8000c84: 4619 mov r1, r3 8000c86: 481a ldr r0, [pc, #104] @ (8000cf0 ) 8000c88: f005 f882 bl 8005d90 8000c8c: 4603 mov r3, r0 8000c8e: 2b00 cmp r3, #0 8000c90: d001 beq.n 8000c96 { Error_Handler(); 8000c92: f001 f8bd bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000c96: 4b19 ldr r3, [pc, #100] @ (8000cfc ) 8000c98: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000c9a: 230c movs r3, #12 8000c9c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c9e: 1d3b adds r3, r7, #4 8000ca0: 4619 mov r1, r3 8000ca2: 4813 ldr r0, [pc, #76] @ (8000cf0 ) 8000ca4: f005 f874 bl 8005d90 8000ca8: 4603 mov r3, r0 8000caa: 2b00 cmp r3, #0 8000cac: d001 beq.n 8000cb2 { Error_Handler(); 8000cae: f001 f8af bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000cb2: 4b13 ldr r3, [pc, #76] @ (8000d00 ) 8000cb4: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000cb6: 2312 movs r3, #18 8000cb8: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000cba: 1d3b adds r3, r7, #4 8000cbc: 4619 mov r1, r3 8000cbe: 480c ldr r0, [pc, #48] @ (8000cf0 ) 8000cc0: f005 f866 bl 8005d90 8000cc4: 4603 mov r3, r0 8000cc6: 2b00 cmp r3, #0 8000cc8: d001 beq.n 8000cce { Error_Handler(); 8000cca: f001 f8a1 bl 8001e10 } /* USER CODE BEGIN ADC2_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000cce: f240 72ff movw r2, #2047 @ 0x7ff 8000cd2: f04f 1101 mov.w r1, #65537 @ 0x10001 8000cd6: 4806 ldr r0, [pc, #24] @ (8000cf0 ) 8000cd8: f005 fe9a bl 8006a10 8000cdc: 4603 mov r3, r0 8000cde: 2b00 cmp r3, #0 8000ce0: d001 beq.n 8000ce6 { Error_Handler(); 8000ce2: f001 f895 bl 8001e10 } /* USER CODE END ADC2_Init 2 */ } 8000ce6: bf00 nop 8000ce8: 3720 adds r7, #32 8000cea: 46bd mov sp, r7 8000cec: bd80 pop {r7, pc} 8000cee: bf00 nop 8000cf0: 240001a4 .word 0x240001a4 8000cf4: 40022100 .word 0x40022100 8000cf8: 0c900008 .word 0x0c900008 8000cfc: 10c00010 .word 0x10c00010 8000d00: 14f00020 .word 0x14f00020 08000d04 : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 8000d04: b580 push {r7, lr} 8000d06: b088 sub sp, #32 8000d08: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000d0a: 1d3b adds r3, r7, #4 8000d0c: 2200 movs r2, #0 8000d0e: 601a str r2, [r3, #0] 8000d10: 605a str r2, [r3, #4] 8000d12: 609a str r2, [r3, #8] 8000d14: 60da str r2, [r3, #12] 8000d16: 611a str r2, [r3, #16] 8000d18: 615a str r2, [r3, #20] 8000d1a: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 8000d1c: 4b4b ldr r3, [pc, #300] @ (8000e4c ) 8000d1e: 4a4c ldr r2, [pc, #304] @ (8000e50 ) 8000d20: 601a str r2, [r3, #0] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000d22: 4b4a ldr r3, [pc, #296] @ (8000e4c ) 8000d24: 2200 movs r2, #0 8000d26: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000d28: 4b48 ldr r3, [pc, #288] @ (8000e4c ) 8000d2a: 2201 movs r2, #1 8000d2c: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000d2e: 4b47 ldr r3, [pc, #284] @ (8000e4c ) 8000d30: 2208 movs r2, #8 8000d32: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000d34: 4b45 ldr r3, [pc, #276] @ (8000e4c ) 8000d36: 2200 movs r2, #0 8000d38: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = ENABLE; 8000d3a: 4b44 ldr r3, [pc, #272] @ (8000e4c ) 8000d3c: 2201 movs r2, #1 8000d3e: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 5; 8000d40: 4b42 ldr r3, [pc, #264] @ (8000e4c ) 8000d42: 2205 movs r2, #5 8000d44: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000d46: 4b41 ldr r3, [pc, #260] @ (8000e4c ) 8000d48: 2200 movs r2, #0 8000d4a: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T2_TRGO; 8000d4c: 4b3f ldr r3, [pc, #252] @ (8000e4c ) 8000d4e: f44f 62ac mov.w r2, #1376 @ 0x560 8000d52: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000d54: 4b3d ldr r3, [pc, #244] @ (8000e4c ) 8000d56: f44f 6280 mov.w r2, #1024 @ 0x400 8000d5a: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000d5c: 4b3b ldr r3, [pc, #236] @ (8000e4c ) 8000d5e: 2201 movs r2, #1 8000d60: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000d62: 4b3a ldr r3, [pc, #232] @ (8000e4c ) 8000d64: 2200 movs r2, #0 8000d66: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000d68: 4b38 ldr r3, [pc, #224] @ (8000e4c ) 8000d6a: 2200 movs r2, #0 8000d6c: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000d6e: 4b37 ldr r3, [pc, #220] @ (8000e4c ) 8000d70: 2200 movs r2, #0 8000d72: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000d76: 4835 ldr r0, [pc, #212] @ (8000e4c ) 8000d78: f004 fd90 bl 800589c 8000d7c: 4603 mov r3, r0 8000d7e: 2b00 cmp r3, #0 8000d80: d001 beq.n 8000d86 { Error_Handler(); 8000d82: f001 f845 bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8000d86: 2301 movs r3, #1 8000d88: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000d8a: 2306 movs r3, #6 8000d8c: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000d8e: 2306 movs r3, #6 8000d90: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000d92: f240 73ff movw r3, #2047 @ 0x7ff 8000d96: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000d98: 2304 movs r3, #4 8000d9a: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000d9c: 2300 movs r3, #0 8000d9e: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000da0: 2300 movs r3, #0 8000da2: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000da4: 1d3b adds r3, r7, #4 8000da6: 4619 mov r1, r3 8000da8: 4828 ldr r0, [pc, #160] @ (8000e4c ) 8000daa: f004 fff1 bl 8005d90 8000dae: 4603 mov r3, r0 8000db0: 2b00 cmp r3, #0 8000db2: d001 beq.n 8000db8 { Error_Handler(); 8000db4: f001 f82c bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000db8: 4b26 ldr r3, [pc, #152] @ (8000e54 ) 8000dba: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000dbc: 230c movs r3, #12 8000dbe: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000dc0: 1d3b adds r3, r7, #4 8000dc2: 4619 mov r1, r3 8000dc4: 4821 ldr r0, [pc, #132] @ (8000e4c ) 8000dc6: f004 ffe3 bl 8005d90 8000dca: 4603 mov r3, r0 8000dcc: 2b00 cmp r3, #0 8000dce: d001 beq.n 8000dd4 { Error_Handler(); 8000dd0: f001 f81e bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_10; 8000dd4: 4b20 ldr r3, [pc, #128] @ (8000e58 ) 8000dd6: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000dd8: 2312 movs r3, #18 8000dda: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000ddc: 1d3b adds r3, r7, #4 8000dde: 4619 mov r1, r3 8000de0: 481a ldr r0, [pc, #104] @ (8000e4c ) 8000de2: f004 ffd5 bl 8005d90 8000de6: 4603 mov r3, r0 8000de8: 2b00 cmp r3, #0 8000dea: d001 beq.n 8000df0 { Error_Handler(); 8000dec: f001 f810 bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; 8000df0: 4b1a ldr r3, [pc, #104] @ (8000e5c ) 8000df2: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8000df4: 2318 movs r3, #24 8000df6: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000df8: 1d3b adds r3, r7, #4 8000dfa: 4619 mov r1, r3 8000dfc: 4813 ldr r0, [pc, #76] @ (8000e4c ) 8000dfe: f004 ffc7 bl 8005d90 8000e02: 4603 mov r3, r0 8000e04: 2b00 cmp r3, #0 8000e06: d001 beq.n 8000e0c { Error_Handler(); 8000e08: f001 f802 bl 8001e10 } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000e0c: 4b14 ldr r3, [pc, #80] @ (8000e60 ) 8000e0e: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 8000e10: f44f 7380 mov.w r3, #256 @ 0x100 8000e14: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000e16: 1d3b adds r3, r7, #4 8000e18: 4619 mov r1, r3 8000e1a: 480c ldr r0, [pc, #48] @ (8000e4c ) 8000e1c: f004 ffb8 bl 8005d90 8000e20: 4603 mov r3, r0 8000e22: 2b00 cmp r3, #0 8000e24: d001 beq.n 8000e2a { Error_Handler(); 8000e26: f000 fff3 bl 8001e10 } /* USER CODE BEGIN ADC3_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000e2a: f240 72ff movw r2, #2047 @ 0x7ff 8000e2e: f04f 1101 mov.w r1, #65537 @ 0x10001 8000e32: 4806 ldr r0, [pc, #24] @ (8000e4c ) 8000e34: f005 fdec bl 8006a10 8000e38: 4603 mov r3, r0 8000e3a: 2b00 cmp r3, #0 8000e3c: d001 beq.n 8000e42 { Error_Handler(); 8000e3e: f000 ffe7 bl 8001e10 } /* USER CODE END ADC3_Init 2 */ } 8000e42: bf00 nop 8000e44: 3720 adds r7, #32 8000e46: 46bd mov sp, r7 8000e48: bd80 pop {r7, pc} 8000e4a: bf00 nop 8000e4c: 24000208 .word 0x24000208 8000e50: 58026000 .word 0x58026000 8000e54: 04300002 .word 0x04300002 8000e58: 2a000400 .word 0x2a000400 8000e5c: 2e300800 .word 0x2e300800 8000e60: cfb80000 .word 0xcfb80000 08000e64 : * @brief COMP1 Initialization Function * @param None * @retval None */ static void MX_COMP1_Init(void) { 8000e64: b580 push {r7, lr} 8000e66: af00 add r7, sp, #0 /* USER CODE END COMP1_Init 0 */ /* USER CODE BEGIN COMP1_Init 1 */ /* USER CODE END COMP1_Init 1 */ hcomp1.Instance = COMP1; 8000e68: 4b12 ldr r3, [pc, #72] @ (8000eb4 ) 8000e6a: 4a13 ldr r2, [pc, #76] @ (8000eb8 ) 8000e6c: 601a str r2, [r3, #0] hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT; 8000e6e: 4b11 ldr r3, [pc, #68] @ (8000eb4 ) 8000e70: 4a12 ldr r2, [pc, #72] @ (8000ebc ) 8000e72: 611a str r2, [r3, #16] hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 8000e74: 4b0f ldr r3, [pc, #60] @ (8000eb4 ) 8000e76: f44f 1280 mov.w r2, #1048576 @ 0x100000 8000e7a: 60da str r2, [r3, #12] hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 8000e7c: 4b0d ldr r3, [pc, #52] @ (8000eb4 ) 8000e7e: 2200 movs r2, #0 8000e80: 619a str r2, [r3, #24] hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE; 8000e82: 4b0c ldr r3, [pc, #48] @ (8000eb4 ) 8000e84: 2200 movs r2, #0 8000e86: 615a str r2, [r3, #20] hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 8000e88: 4b0a ldr r3, [pc, #40] @ (8000eb4 ) 8000e8a: 2200 movs r2, #0 8000e8c: 61da str r2, [r3, #28] hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED; 8000e8e: 4b09 ldr r3, [pc, #36] @ (8000eb4 ) 8000e90: 2200 movs r2, #0 8000e92: 609a str r2, [r3, #8] hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; 8000e94: 4b07 ldr r3, [pc, #28] @ (8000eb4 ) 8000e96: 2200 movs r2, #0 8000e98: 605a str r2, [r3, #4] hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 8000e9a: 4b06 ldr r3, [pc, #24] @ (8000eb4 ) 8000e9c: 2200 movs r2, #0 8000e9e: 621a str r2, [r3, #32] if (HAL_COMP_Init(&hcomp1) != HAL_OK) 8000ea0: 4804 ldr r0, [pc, #16] @ (8000eb4 ) 8000ea2: f005 fef7 bl 8006c94 8000ea6: 4603 mov r3, r0 8000ea8: 2b00 cmp r3, #0 8000eaa: d001 beq.n 8000eb0 { Error_Handler(); 8000eac: f000 ffb0 bl 8001e10 } /* USER CODE BEGIN COMP1_Init 2 */ /* USER CODE END COMP1_Init 2 */ } 8000eb0: bf00 nop 8000eb2: bd80 pop {r7, pc} 8000eb4: 240003d4 .word 0x240003d4 8000eb8: 5800380c .word 0x5800380c 8000ebc: 00020006 .word 0x00020006 08000ec0 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000ec0: b580 push {r7, lr} 8000ec2: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000ec4: 4b11 ldr r3, [pc, #68] @ (8000f0c ) 8000ec6: 4a12 ldr r2, [pc, #72] @ (8000f10 ) 8000ec8: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000eca: 4b10 ldr r3, [pc, #64] @ (8000f0c ) 8000ecc: 2201 movs r2, #1 8000ece: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 8000ed0: 4b0e ldr r3, [pc, #56] @ (8000f0c ) 8000ed2: 2200 movs r2, #0 8000ed4: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 8000ed6: 4b0d ldr r3, [pc, #52] @ (8000f0c ) 8000ed8: f241 0221 movw r2, #4129 @ 0x1021 8000edc: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000ede: 4b0b ldr r3, [pc, #44] @ (8000f0c ) 8000ee0: 2208 movs r2, #8 8000ee2: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000ee4: 4b09 ldr r3, [pc, #36] @ (8000f0c ) 8000ee6: 2200 movs r2, #0 8000ee8: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000eea: 4b08 ldr r3, [pc, #32] @ (8000f0c ) 8000eec: 2200 movs r2, #0 8000eee: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000ef0: 4b06 ldr r3, [pc, #24] @ (8000f0c ) 8000ef2: 2201 movs r2, #1 8000ef4: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000ef6: 4805 ldr r0, [pc, #20] @ (8000f0c ) 8000ef8: f006 f9b6 bl 8007268 8000efc: 4603 mov r3, r0 8000efe: 2b00 cmp r3, #0 8000f00: d001 beq.n 8000f06 { Error_Handler(); 8000f02: f000 ff85 bl 8001e10 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 8000f06: bf00 nop 8000f08: bd80 pop {r7, pc} 8000f0a: bf00 nop 8000f0c: 24000400 .word 0x24000400 8000f10: 58024c00 .word 0x58024c00 08000f14 : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8000f14: b580 push {r7, lr} 8000f16: b08a sub sp, #40 @ 0x28 8000f18: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000f1a: 1d3b adds r3, r7, #4 8000f1c: 2224 movs r2, #36 @ 0x24 8000f1e: 2100 movs r1, #0 8000f20: 4618 mov r0, r3 8000f22: f016 fe18 bl 8017b56 /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8000f26: 4b17 ldr r3, [pc, #92] @ (8000f84 ) 8000f28: 4a17 ldr r2, [pc, #92] @ (8000f88 ) 8000f2a: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8000f2c: 4815 ldr r0, [pc, #84] @ (8000f84 ) 8000f2e: f006 fba1 bl 8007674 8000f32: 4603 mov r3, r0 8000f34: 2b00 cmp r3, #0 8000f36: d001 beq.n 8000f3c { Error_Handler(); 8000f38: f000 ff6a bl 8001e10 } /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000f3c: 2300 movs r3, #0 8000f3e: 607b str r3, [r7, #4] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8000f40: 2300 movs r3, #0 8000f42: 60bb str r3, [r7, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8000f44: 2300 movs r3, #0 8000f46: 60fb str r3, [r7, #12] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8000f48: 2301 movs r3, #1 8000f4a: 613b str r3, [r7, #16] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 8000f4c: 2300 movs r3, #0 8000f4e: 617b str r3, [r7, #20] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000f50: 1d3b adds r3, r7, #4 8000f52: 2200 movs r2, #0 8000f54: 4619 mov r1, r3 8000f56: 480b ldr r0, [pc, #44] @ (8000f84 ) 8000f58: f006 fc90 bl 800787c 8000f5c: 4603 mov r3, r0 8000f5e: 2b00 cmp r3, #0 8000f60: d001 beq.n 8000f66 { Error_Handler(); 8000f62: f000 ff55 bl 8001e10 } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8000f66: 1d3b adds r3, r7, #4 8000f68: 2210 movs r2, #16 8000f6a: 4619 mov r1, r3 8000f6c: 4805 ldr r0, [pc, #20] @ (8000f84 ) 8000f6e: f006 fc85 bl 800787c 8000f72: 4603 mov r3, r0 8000f74: 2b00 cmp r3, #0 8000f76: d001 beq.n 8000f7c { Error_Handler(); 8000f78: f000 ff4a bl 8001e10 } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8000f7c: bf00 nop 8000f7e: 3728 adds r7, #40 @ 0x28 8000f80: 46bd mov sp, r7 8000f82: bd80 pop {r7, pc} 8000f84: 24000424 .word 0x24000424 8000f88: 40007400 .word 0x40007400 08000f8c : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 8000f8c: b580 push {r7, lr} 8000f8e: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8000f90: 4b07 ldr r3, [pc, #28] @ (8000fb0 ) 8000f92: 4a08 ldr r2, [pc, #32] @ (8000fb4 ) 8000f94: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 8000f96: 4b06 ldr r3, [pc, #24] @ (8000fb0 ) 8000f98: 2200 movs r2, #0 8000f9a: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000f9c: 4804 ldr r0, [pc, #16] @ (8000fb0 ) 8000f9e: f00d fc5f bl 800e860 8000fa2: 4603 mov r3, r0 8000fa4: 2b00 cmp r3, #0 8000fa6: d001 beq.n 8000fac { Error_Handler(); 8000fa8: f000 ff32 bl 8001e10 } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000fac: bf00 nop 8000fae: bd80 pop {r7, pc} 8000fb0: 24000438 .word 0x24000438 8000fb4: 48021800 .word 0x48021800 08000fb8 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000fb8: b5b0 push {r4, r5, r7, lr} 8000fba: b096 sub sp, #88 @ 0x58 8000fbc: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000fbe: f107 034c add.w r3, r7, #76 @ 0x4c 8000fc2: 2200 movs r2, #0 8000fc4: 601a str r2, [r3, #0] 8000fc6: 605a str r2, [r3, #4] 8000fc8: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8000fca: f107 0330 add.w r3, r7, #48 @ 0x30 8000fce: 2200 movs r2, #0 8000fd0: 601a str r2, [r3, #0] 8000fd2: 605a str r2, [r3, #4] 8000fd4: 609a str r2, [r3, #8] 8000fd6: 60da str r2, [r3, #12] 8000fd8: 611a str r2, [r3, #16] 8000fda: 615a str r2, [r3, #20] 8000fdc: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000fde: 1d3b adds r3, r7, #4 8000fe0: 222c movs r2, #44 @ 0x2c 8000fe2: 2100 movs r1, #0 8000fe4: 4618 mov r0, r3 8000fe6: f016 fdb6 bl 8017b56 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000fea: 4b3e ldr r3, [pc, #248] @ (80010e4 ) 8000fec: 4a3e ldr r2, [pc, #248] @ (80010e8 ) 8000fee: 601a str r2, [r3, #0] htim1.Init.Prescaler = 199; 8000ff0: 4b3c ldr r3, [pc, #240] @ (80010e4 ) 8000ff2: 22c7 movs r2, #199 @ 0xc7 8000ff4: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000ff6: 4b3b ldr r3, [pc, #236] @ (80010e4 ) 8000ff8: 2200 movs r2, #0 8000ffa: 609a str r2, [r3, #8] htim1.Init.Period = 999; 8000ffc: 4b39 ldr r3, [pc, #228] @ (80010e4 ) 8000ffe: f240 32e7 movw r2, #999 @ 0x3e7 8001002: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001004: 4b37 ldr r3, [pc, #220] @ (80010e4 ) 8001006: 2200 movs r2, #0 8001008: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 800100a: 4b36 ldr r3, [pc, #216] @ (80010e4 ) 800100c: 2200 movs r2, #0 800100e: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001010: 4b34 ldr r3, [pc, #208] @ (80010e4 ) 8001012: 2280 movs r2, #128 @ 0x80 8001014: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8001016: 4833 ldr r0, [pc, #204] @ (80010e4 ) 8001018: f00d fdc4 bl 800eba4 800101c: 4603 mov r3, r0 800101e: 2b00 cmp r3, #0 8001020: d001 beq.n 8001026 { Error_Handler(); 8001022: f000 fef5 bl 8001e10 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001026: 2300 movs r3, #0 8001028: 64fb str r3, [r7, #76] @ 0x4c sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 800102a: 2300 movs r3, #0 800102c: 653b str r3, [r7, #80] @ 0x50 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800102e: 2300 movs r3, #0 8001030: 657b str r3, [r7, #84] @ 0x54 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8001032: f107 034c add.w r3, r7, #76 @ 0x4c 8001036: 4619 mov r1, r3 8001038: 482a ldr r0, [pc, #168] @ (80010e4 ) 800103a: f00f fb17 bl 801066c 800103e: 4603 mov r3, r0 8001040: 2b00 cmp r3, #0 8001042: d001 beq.n 8001048 { Error_Handler(); 8001044: f000 fee4 bl 8001e10 } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001048: 2360 movs r3, #96 @ 0x60 800104a: 633b str r3, [r7, #48] @ 0x30 sConfigOC.Pulse = 99; 800104c: 2363 movs r3, #99 @ 0x63 800104e: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001050: 2300 movs r3, #0 8001052: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8001054: 2300 movs r3, #0 8001056: 63fb str r3, [r7, #60] @ 0x3c sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001058: 2300 movs r3, #0 800105a: 643b str r3, [r7, #64] @ 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 800105c: 2300 movs r3, #0 800105e: 647b str r3, [r7, #68] @ 0x44 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8001060: 2300 movs r3, #0 8001062: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001064: f107 0330 add.w r3, r7, #48 @ 0x30 8001068: 2204 movs r2, #4 800106a: 4619 mov r1, r3 800106c: 481d ldr r0, [pc, #116] @ (80010e4 ) 800106e: f00e faeb bl 800f648 8001072: 4603 mov r3, r0 8001074: 2b00 cmp r3, #0 8001076: d001 beq.n 800107c { Error_Handler(); 8001078: f000 feca bl 8001e10 } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 800107c: 2300 movs r3, #0 800107e: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8001080: 2300 movs r3, #0 8001082: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 8001084: 2300 movs r3, #0 8001086: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 8001088: 2300 movs r3, #0 800108a: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 800108c: 2300 movs r3, #0 800108e: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8001090: f44f 5300 mov.w r3, #8192 @ 0x2000 8001094: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.BreakFilter = 0; 8001096: 2300 movs r3, #0 8001098: 61fb str r3, [r7, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 800109a: 2300 movs r3, #0 800109c: 623b str r3, [r7, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800109e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 80010a2: 627b str r3, [r7, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 80010a4: 2300 movs r3, #0 80010a6: 62bb str r3, [r7, #40] @ 0x28 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 80010a8: 2300 movs r3, #0 80010aa: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 80010ac: 1d3b adds r3, r7, #4 80010ae: 4619 mov r1, r3 80010b0: 480c ldr r0, [pc, #48] @ (80010e4 ) 80010b2: f00f fb69 bl 8010788 80010b6: 4603 mov r3, r0 80010b8: 2b00 cmp r3, #0 80010ba: d001 beq.n 80010c0 { Error_Handler(); 80010bc: f000 fea8 bl 8001e10 } /* USER CODE BEGIN TIM1_Init 2 */ memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 80010c0: 4b0a ldr r3, [pc, #40] @ (80010ec ) 80010c2: 461d mov r5, r3 80010c4: f107 0430 add.w r4, r7, #48 @ 0x30 80010c8: cc0f ldmia r4!, {r0, r1, r2, r3} 80010ca: c50f stmia r5!, {r0, r1, r2, r3} 80010cc: e894 0007 ldmia.w r4, {r0, r1, r2} 80010d0: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 80010d4: 4803 ldr r0, [pc, #12] @ (80010e4 ) 80010d6: f002 fd29 bl 8003b2c } 80010da: bf00 nop 80010dc: 3758 adds r7, #88 @ 0x58 80010de: 46bd mov sp, r7 80010e0: bdb0 pop {r4, r5, r7, pc} 80010e2: bf00 nop 80010e4: 2400044c .word 0x2400044c 80010e8: 40010000 .word 0x40010000 80010ec: 24000768 .word 0x24000768 080010f0 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80010f0: b580 push {r7, lr} 80010f2: b08c sub sp, #48 @ 0x30 80010f4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80010f6: f107 0320 add.w r3, r7, #32 80010fa: 2200 movs r2, #0 80010fc: 601a str r2, [r3, #0] 80010fe: 605a str r2, [r3, #4] 8001100: 609a str r2, [r3, #8] 8001102: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001104: f107 0314 add.w r3, r7, #20 8001108: 2200 movs r2, #0 800110a: 601a str r2, [r3, #0] 800110c: 605a str r2, [r3, #4] 800110e: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 8001110: 1d3b adds r3, r7, #4 8001112: 2200 movs r2, #0 8001114: 601a str r2, [r3, #0] 8001116: 605a str r2, [r3, #4] 8001118: 609a str r2, [r3, #8] 800111a: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 800111c: 4b31 ldr r3, [pc, #196] @ (80011e4 ) 800111e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 8001122: 601a str r2, [r3, #0] htim2.Init.Prescaler = 0; 8001124: 4b2f ldr r3, [pc, #188] @ (80011e4 ) 8001126: 2200 movs r2, #0 8001128: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 800112a: 4b2e ldr r3, [pc, #184] @ (80011e4 ) 800112c: 2200 movs r2, #0 800112e: 609a str r2, [r3, #8] htim2.Init.Period = 9999999; 8001130: 4b2c ldr r3, [pc, #176] @ (80011e4 ) 8001132: 4a2d ldr r2, [pc, #180] @ (80011e8 ) 8001134: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 8001136: 4b2b ldr r3, [pc, #172] @ (80011e4 ) 8001138: f44f 7280 mov.w r2, #256 @ 0x100 800113c: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 800113e: 4b29 ldr r3, [pc, #164] @ (80011e4 ) 8001140: 2280 movs r2, #128 @ 0x80 8001142: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8001144: 4827 ldr r0, [pc, #156] @ (80011e4 ) 8001146: f00d fbed bl 800e924 800114a: 4603 mov r3, r0 800114c: 2b00 cmp r3, #0 800114e: d001 beq.n 8001154 { Error_Handler(); 8001150: f000 fe5e bl 8001e10 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001154: f44f 5380 mov.w r3, #4096 @ 0x1000 8001158: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 800115a: f107 0320 add.w r3, r7, #32 800115e: 4619 mov r1, r3 8001160: 4820 ldr r0, [pc, #128] @ (80011e4 ) 8001162: f00e fb85 bl 800f870 8001166: 4603 mov r3, r0 8001168: 2b00 cmp r3, #0 800116a: d001 beq.n 8001170 { Error_Handler(); 800116c: f000 fe50 bl 8001e10 } if (HAL_TIM_IC_Init(&htim2) != HAL_OK) 8001170: 481c ldr r0, [pc, #112] @ (80011e4 ) 8001172: f00d ff13 bl 800ef9c 8001176: 4603 mov r3, r0 8001178: 2b00 cmp r3, #0 800117a: d001 beq.n 8001180 { Error_Handler(); 800117c: f000 fe48 bl 8001e10 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001180: 2320 movs r3, #32 8001182: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001184: 2380 movs r3, #128 @ 0x80 8001186: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 8001188: f107 0314 add.w r3, r7, #20 800118c: 4619 mov r1, r3 800118e: 4815 ldr r0, [pc, #84] @ (80011e4 ) 8001190: f00f fa6c bl 801066c 8001194: 4603 mov r3, r0 8001196: 2b00 cmp r3, #0 8001198: d001 beq.n 800119e { Error_Handler(); 800119a: f000 fe39 bl 8001e10 } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 800119e: 2300 movs r3, #0 80011a0: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 80011a2: 2301 movs r3, #1 80011a4: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 80011a6: 2300 movs r3, #0 80011a8: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 80011aa: 2300 movs r3, #0 80011ac: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 80011ae: 1d3b adds r3, r7, #4 80011b0: 2208 movs r2, #8 80011b2: 4619 mov r1, r3 80011b4: 480b ldr r0, [pc, #44] @ (80011e4 ) 80011b6: f00e f9aa bl 800f50e 80011ba: 4603 mov r3, r0 80011bc: 2b00 cmp r3, #0 80011be: d001 beq.n 80011c4 { Error_Handler(); 80011c0: f000 fe26 bl 8001e10 } if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 80011c4: 1d3b adds r3, r7, #4 80011c6: 220c movs r2, #12 80011c8: 4619 mov r1, r3 80011ca: 4806 ldr r0, [pc, #24] @ (80011e4 ) 80011cc: f00e f99f bl 800f50e 80011d0: 4603 mov r3, r0 80011d2: 2b00 cmp r3, #0 80011d4: d001 beq.n 80011da { Error_Handler(); 80011d6: f000 fe1b bl 8001e10 } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 80011da: bf00 nop 80011dc: 3730 adds r7, #48 @ 0x30 80011de: 46bd mov sp, r7 80011e0: bd80 pop {r7, pc} 80011e2: bf00 nop 80011e4: 24000498 .word 0x24000498 80011e8: 0098967f .word 0x0098967f 080011ec : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 80011ec: b5b0 push {r4, r5, r7, lr} 80011ee: b08a sub sp, #40 @ 0x28 80011f0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011f2: f107 031c add.w r3, r7, #28 80011f6: 2200 movs r2, #0 80011f8: 601a str r2, [r3, #0] 80011fa: 605a str r2, [r3, #4] 80011fc: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 80011fe: 463b mov r3, r7 8001200: 2200 movs r2, #0 8001202: 601a str r2, [r3, #0] 8001204: 605a str r2, [r3, #4] 8001206: 609a str r2, [r3, #8] 8001208: 60da str r2, [r3, #12] 800120a: 611a str r2, [r3, #16] 800120c: 615a str r2, [r3, #20] 800120e: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 8001210: 4b48 ldr r3, [pc, #288] @ (8001334 ) 8001212: 4a49 ldr r2, [pc, #292] @ (8001338 ) 8001214: 601a str r2, [r3, #0] htim3.Init.Prescaler = 199; 8001216: 4b47 ldr r3, [pc, #284] @ (8001334 ) 8001218: 22c7 movs r2, #199 @ 0xc7 800121a: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 800121c: 4b45 ldr r3, [pc, #276] @ (8001334 ) 800121e: 2200 movs r2, #0 8001220: 609a str r2, [r3, #8] htim3.Init.Period = 999; 8001222: 4b44 ldr r3, [pc, #272] @ (8001334 ) 8001224: f240 32e7 movw r2, #999 @ 0x3e7 8001228: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800122a: 4b42 ldr r3, [pc, #264] @ (8001334 ) 800122c: 2200 movs r2, #0 800122e: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001230: 4b40 ldr r3, [pc, #256] @ (8001334 ) 8001232: 2280 movs r2, #128 @ 0x80 8001234: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 8001236: 483f ldr r0, [pc, #252] @ (8001334 ) 8001238: f00d fcb4 bl 800eba4 800123c: 4603 mov r3, r0 800123e: 2b00 cmp r3, #0 8001240: d001 beq.n 8001246 { Error_Handler(); 8001242: f000 fde5 bl 8001e10 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001246: 2300 movs r3, #0 8001248: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800124a: 2300 movs r3, #0 800124c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800124e: f107 031c add.w r3, r7, #28 8001252: 4619 mov r1, r3 8001254: 4837 ldr r0, [pc, #220] @ (8001334 ) 8001256: f00f fa09 bl 801066c 800125a: 4603 mov r3, r0 800125c: 2b00 cmp r3, #0 800125e: d001 beq.n 8001264 { Error_Handler(); 8001260: f000 fdd6 bl 8001e10 } sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 8001264: 4b35 ldr r3, [pc, #212] @ (800133c ) 8001266: 603b str r3, [r7, #0] sConfigOC.Pulse = 500; 8001268: f44f 73fa mov.w r3, #500 @ 0x1f4 800126c: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800126e: 2300 movs r3, #0 8001270: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001272: 2300 movs r3, #0 8001274: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001276: 463b mov r3, r7 8001278: 2200 movs r2, #0 800127a: 4619 mov r1, r3 800127c: 482d ldr r0, [pc, #180] @ (8001334 ) 800127e: f00e f9e3 bl 800f648 8001282: 4603 mov r3, r0 8001284: 2b00 cmp r3, #0 8001286: d001 beq.n 800128c { Error_Handler(); 8001288: f000 fdc2 bl 8001e10 } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 800128c: 4b29 ldr r3, [pc, #164] @ (8001334 ) 800128e: 681b ldr r3, [r3, #0] 8001290: 699a ldr r2, [r3, #24] 8001292: 4b28 ldr r3, [pc, #160] @ (8001334 ) 8001294: 681b ldr r3, [r3, #0] 8001296: f022 0208 bic.w r2, r2, #8 800129a: 619a str r2, [r3, #24] sConfigOC.OCMode = TIM_OCMODE_PWM1; 800129c: 2360 movs r3, #96 @ 0x60 800129e: 603b str r3, [r7, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 80012a0: 463b mov r3, r7 80012a2: 2204 movs r2, #4 80012a4: 4619 mov r1, r3 80012a6: 4823 ldr r0, [pc, #140] @ (8001334 ) 80012a8: f00e f9ce bl 800f648 80012ac: 4603 mov r3, r0 80012ae: 2b00 cmp r3, #0 80012b0: d001 beq.n 80012b6 { Error_Handler(); 80012b2: f000 fdad bl 8001e10 } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 80012b6: 4b1f ldr r3, [pc, #124] @ (8001334 ) 80012b8: 681b ldr r3, [r3, #0] 80012ba: 699a ldr r2, [r3, #24] 80012bc: 4b1d ldr r3, [pc, #116] @ (8001334 ) 80012be: 681b ldr r3, [r3, #0] 80012c0: f422 6200 bic.w r2, r2, #2048 @ 0x800 80012c4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 80012c6: 463b mov r3, r7 80012c8: 2208 movs r2, #8 80012ca: 4619 mov r1, r3 80012cc: 4819 ldr r0, [pc, #100] @ (8001334 ) 80012ce: f00e f9bb bl 800f648 80012d2: 4603 mov r3, r0 80012d4: 2b00 cmp r3, #0 80012d6: d001 beq.n 80012dc { Error_Handler(); 80012d8: f000 fd9a bl 8001e10 } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 80012dc: 4b15 ldr r3, [pc, #84] @ (8001334 ) 80012de: 681b ldr r3, [r3, #0] 80012e0: 69da ldr r2, [r3, #28] 80012e2: 4b14 ldr r3, [pc, #80] @ (8001334 ) 80012e4: 681b ldr r3, [r3, #0] 80012e6: f022 0208 bic.w r2, r2, #8 80012ea: 61da str r2, [r3, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 80012ec: 463b mov r3, r7 80012ee: 220c movs r2, #12 80012f0: 4619 mov r1, r3 80012f2: 4810 ldr r0, [pc, #64] @ (8001334 ) 80012f4: f00e f9a8 bl 800f648 80012f8: 4603 mov r3, r0 80012fa: 2b00 cmp r3, #0 80012fc: d001 beq.n 8001302 { Error_Handler(); 80012fe: f000 fd87 bl 8001e10 } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 8001302: 4b0c ldr r3, [pc, #48] @ (8001334 ) 8001304: 681b ldr r3, [r3, #0] 8001306: 69da ldr r2, [r3, #28] 8001308: 4b0a ldr r3, [pc, #40] @ (8001334 ) 800130a: 681b ldr r3, [r3, #0] 800130c: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001310: 61da str r2, [r3, #28] /* USER CODE BEGIN TIM3_Init 2 */ memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001312: 4b0b ldr r3, [pc, #44] @ (8001340 ) 8001314: 461d mov r5, r3 8001316: 463c mov r4, r7 8001318: cc0f ldmia r4!, {r0, r1, r2, r3} 800131a: c50f stmia r5!, {r0, r1, r2, r3} 800131c: e894 0007 ldmia.w r4, {r0, r1, r2} 8001320: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 8001324: 4803 ldr r0, [pc, #12] @ (8001334 ) 8001326: f002 fc01 bl 8003b2c } 800132a: bf00 nop 800132c: 3728 adds r7, #40 @ 0x28 800132e: 46bd mov sp, r7 8001330: bdb0 pop {r4, r5, r7, pc} 8001332: bf00 nop 8001334: 240004e4 .word 0x240004e4 8001338: 40000400 .word 0x40000400 800133c: 00010040 .word 0x00010040 8001340: 24000784 .word 0x24000784 08001344 : * @brief TIM4 Initialization Function * @param None * @retval None */ static void MX_TIM4_Init(void) { 8001344: b580 push {r7, lr} 8001346: b08c sub sp, #48 @ 0x30 8001348: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800134a: f107 0320 add.w r3, r7, #32 800134e: 2200 movs r2, #0 8001350: 601a str r2, [r3, #0] 8001352: 605a str r2, [r3, #4] 8001354: 609a str r2, [r3, #8] 8001356: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001358: f107 0314 add.w r3, r7, #20 800135c: 2200 movs r2, #0 800135e: 601a str r2, [r3, #0] 8001360: 605a str r2, [r3, #4] 8001362: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 8001364: 1d3b adds r3, r7, #4 8001366: 2200 movs r2, #0 8001368: 601a str r2, [r3, #0] 800136a: 605a str r2, [r3, #4] 800136c: 609a str r2, [r3, #8] 800136e: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 8001370: 4b31 ldr r3, [pc, #196] @ (8001438 ) 8001372: 4a32 ldr r2, [pc, #200] @ (800143c ) 8001374: 601a str r2, [r3, #0] htim4.Init.Prescaler = 19999; 8001376: 4b30 ldr r3, [pc, #192] @ (8001438 ) 8001378: f644 621f movw r2, #19999 @ 0x4e1f 800137c: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800137e: 4b2e ldr r3, [pc, #184] @ (8001438 ) 8001380: 2200 movs r2, #0 8001382: 609a str r2, [r3, #8] htim4.Init.Period = 9999; 8001384: 4b2c ldr r3, [pc, #176] @ (8001438 ) 8001386: f242 720f movw r2, #9999 @ 0x270f 800138a: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800138c: 4b2a ldr r3, [pc, #168] @ (8001438 ) 800138e: 2200 movs r2, #0 8001390: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001392: 4b29 ldr r3, [pc, #164] @ (8001438 ) 8001394: 2280 movs r2, #128 @ 0x80 8001396: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 8001398: 4827 ldr r0, [pc, #156] @ (8001438 ) 800139a: f00d fac3 bl 800e924 800139e: 4603 mov r3, r0 80013a0: 2b00 cmp r3, #0 80013a2: d001 beq.n 80013a8 { Error_Handler(); 80013a4: f000 fd34 bl 8001e10 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 80013a8: f44f 5380 mov.w r3, #4096 @ 0x1000 80013ac: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 80013ae: f107 0320 add.w r3, r7, #32 80013b2: 4619 mov r1, r3 80013b4: 4820 ldr r0, [pc, #128] @ (8001438 ) 80013b6: f00e fa5b bl 800f870 80013ba: 4603 mov r3, r0 80013bc: 2b00 cmp r3, #0 80013be: d001 beq.n 80013c4 { Error_Handler(); 80013c0: f000 fd26 bl 8001e10 } if (HAL_TIM_IC_Init(&htim4) != HAL_OK) 80013c4: 481c ldr r0, [pc, #112] @ (8001438 ) 80013c6: f00d fde9 bl 800ef9c 80013ca: 4603 mov r3, r0 80013cc: 2b00 cmp r3, #0 80013ce: d001 beq.n 80013d4 { Error_Handler(); 80013d0: f000 fd1e bl 8001e10 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80013d4: 2300 movs r3, #0 80013d6: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80013d8: 2300 movs r3, #0 80013da: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 80013dc: f107 0314 add.w r3, r7, #20 80013e0: 4619 mov r1, r3 80013e2: 4815 ldr r0, [pc, #84] @ (8001438 ) 80013e4: f00f f942 bl 801066c 80013e8: 4603 mov r3, r0 80013ea: 2b00 cmp r3, #0 80013ec: d001 beq.n 80013f2 { Error_Handler(); 80013ee: f000 fd0f bl 8001e10 } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 80013f2: 2300 movs r3, #0 80013f4: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 80013f6: 2301 movs r3, #1 80013f8: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 80013fa: 2300 movs r3, #0 80013fc: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 80013fe: 2300 movs r3, #0 8001400: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 8001402: 1d3b adds r3, r7, #4 8001404: 2208 movs r2, #8 8001406: 4619 mov r1, r3 8001408: 480b ldr r0, [pc, #44] @ (8001438 ) 800140a: f00e f880 bl 800f50e 800140e: 4603 mov r3, r0 8001410: 2b00 cmp r3, #0 8001412: d001 beq.n 8001418 { Error_Handler(); 8001414: f000 fcfc bl 8001e10 } if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 8001418: 1d3b adds r3, r7, #4 800141a: 220c movs r2, #12 800141c: 4619 mov r1, r3 800141e: 4806 ldr r0, [pc, #24] @ (8001438 ) 8001420: f00e f875 bl 800f50e 8001424: 4603 mov r3, r0 8001426: 2b00 cmp r3, #0 8001428: d001 beq.n 800142e { Error_Handler(); 800142a: f000 fcf1 bl 8001e10 } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ } 800142e: bf00 nop 8001430: 3730 adds r7, #48 @ 0x30 8001432: 46bd mov sp, r7 8001434: bd80 pop {r7, pc} 8001436: bf00 nop 8001438: 24000530 .word 0x24000530 800143c: 40000800 .word 0x40000800 08001440 : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 8001440: b580 push {r7, lr} 8001442: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 8001444: 4b22 ldr r3, [pc, #136] @ (80014d0 ) 8001446: 4a23 ldr r2, [pc, #140] @ (80014d4 ) 8001448: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 800144a: 4b21 ldr r3, [pc, #132] @ (80014d0 ) 800144c: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001450: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 8001452: 4b1f ldr r3, [pc, #124] @ (80014d0 ) 8001454: 2200 movs r2, #0 8001456: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 8001458: 4b1d ldr r3, [pc, #116] @ (80014d0 ) 800145a: 2200 movs r2, #0 800145c: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 800145e: 4b1c ldr r3, [pc, #112] @ (80014d0 ) 8001460: 2200 movs r2, #0 8001462: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 8001464: 4b1a ldr r3, [pc, #104] @ (80014d0 ) 8001466: 220c movs r2, #12 8001468: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800146a: 4b19 ldr r3, [pc, #100] @ (80014d0 ) 800146c: 2200 movs r2, #0 800146e: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 8001470: 4b17 ldr r3, [pc, #92] @ (80014d0 ) 8001472: 2200 movs r2, #0 8001474: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 8001476: 4b16 ldr r3, [pc, #88] @ (80014d0 ) 8001478: 2200 movs r2, #0 800147a: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 800147c: 4b14 ldr r3, [pc, #80] @ (80014d0 ) 800147e: 2200 movs r2, #0 8001480: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8001482: 4b13 ldr r3, [pc, #76] @ (80014d0 ) 8001484: 2200 movs r2, #0 8001486: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 8001488: 4811 ldr r0, [pc, #68] @ (80014d0 ) 800148a: f00f fa19 bl 80108c0 800148e: 4603 mov r3, r0 8001490: 2b00 cmp r3, #0 8001492: d001 beq.n 8001498 { Error_Handler(); 8001494: f000 fcbc bl 8001e10 } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001498: 2100 movs r1, #0 800149a: 480d ldr r0, [pc, #52] @ (80014d0 ) 800149c: f011 ff47 bl 801332e 80014a0: 4603 mov r3, r0 80014a2: 2b00 cmp r3, #0 80014a4: d001 beq.n 80014aa { Error_Handler(); 80014a6: f000 fcb3 bl 8001e10 } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80014aa: 2100 movs r1, #0 80014ac: 4808 ldr r0, [pc, #32] @ (80014d0 ) 80014ae: f011 ff7c bl 80133aa 80014b2: 4603 mov r3, r0 80014b4: 2b00 cmp r3, #0 80014b6: d001 beq.n 80014bc { Error_Handler(); 80014b8: f000 fcaa bl 8001e10 } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 80014bc: 4804 ldr r0, [pc, #16] @ (80014d0 ) 80014be: f011 fefd bl 80132bc 80014c2: 4603 mov r3, r0 80014c4: 2b00 cmp r3, #0 80014c6: d001 beq.n 80014cc { Error_Handler(); 80014c8: f000 fca2 bl 8001e10 } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 80014cc: bf00 nop 80014ce: bd80 pop {r7, pc} 80014d0: 2400057c .word 0x2400057c 80014d4: 40007c00 .word 0x40007c00 080014d8 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 80014d8: b580 push {r7, lr} 80014da: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80014dc: 4b24 ldr r3, [pc, #144] @ (8001570 ) 80014de: 4a25 ldr r2, [pc, #148] @ (8001574 ) 80014e0: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80014e2: 4b23 ldr r3, [pc, #140] @ (8001570 ) 80014e4: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80014e8: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80014ea: 4b21 ldr r3, [pc, #132] @ (8001570 ) 80014ec: 2200 movs r2, #0 80014ee: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80014f0: 4b1f ldr r3, [pc, #124] @ (8001570 ) 80014f2: 2200 movs r2, #0 80014f4: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80014f6: 4b1e ldr r3, [pc, #120] @ (8001570 ) 80014f8: 2200 movs r2, #0 80014fa: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80014fc: 4b1c ldr r3, [pc, #112] @ (8001570 ) 80014fe: 220c movs r2, #12 8001500: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8001502: 4b1b ldr r3, [pc, #108] @ (8001570 ) 8001504: 2200 movs r2, #0 8001506: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001508: 4b19 ldr r3, [pc, #100] @ (8001570 ) 800150a: 2200 movs r2, #0 800150c: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800150e: 4b18 ldr r3, [pc, #96] @ (8001570 ) 8001510: 2200 movs r2, #0 8001512: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001514: 4b16 ldr r3, [pc, #88] @ (8001570 ) 8001516: 2200 movs r2, #0 8001518: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT; 800151a: 4b15 ldr r3, [pc, #84] @ (8001570 ) 800151c: 2201 movs r2, #1 800151e: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 8001520: 4b13 ldr r3, [pc, #76] @ (8001570 ) 8001522: f44f 3200 mov.w r2, #131072 @ 0x20000 8001526: 62da str r2, [r3, #44] @ 0x2c if (HAL_UART_Init(&huart1) != HAL_OK) 8001528: 4811 ldr r0, [pc, #68] @ (8001570 ) 800152a: f00f f9c9 bl 80108c0 800152e: 4603 mov r3, r0 8001530: 2b00 cmp r3, #0 8001532: d001 beq.n 8001538 { Error_Handler(); 8001534: f000 fc6c bl 8001e10 } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001538: 2100 movs r1, #0 800153a: 480d ldr r0, [pc, #52] @ (8001570 ) 800153c: f011 fef7 bl 801332e 8001540: 4603 mov r3, r0 8001542: 2b00 cmp r3, #0 8001544: d001 beq.n 800154a { Error_Handler(); 8001546: f000 fc63 bl 8001e10 } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 800154a: 2100 movs r1, #0 800154c: 4808 ldr r0, [pc, #32] @ (8001570 ) 800154e: f011 ff2c bl 80133aa 8001552: 4603 mov r3, r0 8001554: 2b00 cmp r3, #0 8001556: d001 beq.n 800155c { Error_Handler(); 8001558: f000 fc5a bl 8001e10 } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 800155c: 4804 ldr r0, [pc, #16] @ (8001570 ) 800155e: f011 fead bl 80132bc 8001562: 4603 mov r3, r0 8001564: 2b00 cmp r3, #0 8001566: d001 beq.n 800156c { Error_Handler(); 8001568: f000 fc52 bl 8001e10 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 800156c: bf00 nop 800156e: bd80 pop {r7, pc} 8001570: 24000610 .word 0x24000610 8001574: 40011000 .word 0x40011000 08001578 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 8001578: b580 push {r7, lr} 800157a: b082 sub sp, #8 800157c: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 800157e: 4b15 ldr r3, [pc, #84] @ (80015d4 ) 8001580: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8001584: 4a13 ldr r2, [pc, #76] @ (80015d4 ) 8001586: f043 0301 orr.w r3, r3, #1 800158a: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 800158e: 4b11 ldr r3, [pc, #68] @ (80015d4 ) 8001590: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8001594: f003 0301 and.w r3, r3, #1 8001598: 607b str r3, [r7, #4] 800159a: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 800159c: 2200 movs r2, #0 800159e: 2105 movs r1, #5 80015a0: 200b movs r0, #11 80015a2: f005 fdc1 bl 8007128 HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 80015a6: 200b movs r0, #11 80015a8: f005 fdd8 bl 800715c /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 80015ac: 2200 movs r2, #0 80015ae: 2105 movs r1, #5 80015b0: 200c movs r0, #12 80015b2: f005 fdb9 bl 8007128 HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 80015b6: 200c movs r0, #12 80015b8: f005 fdd0 bl 800715c /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 80015bc: 2200 movs r2, #0 80015be: 2105 movs r1, #5 80015c0: 200d movs r0, #13 80015c2: f005 fdb1 bl 8007128 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 80015c6: 200d movs r0, #13 80015c8: f005 fdc8 bl 800715c } 80015cc: bf00 nop 80015ce: 3708 adds r7, #8 80015d0: 46bd mov sp, r7 80015d2: bd80 pop {r7, pc} 80015d4: 58024400 .word 0x58024400 080015d8 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80015d8: b580 push {r7, lr} 80015da: b08c sub sp, #48 @ 0x30 80015dc: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80015de: f107 031c add.w r3, r7, #28 80015e2: 2200 movs r2, #0 80015e4: 601a str r2, [r3, #0] 80015e6: 605a str r2, [r3, #4] 80015e8: 609a str r2, [r3, #8] 80015ea: 60da str r2, [r3, #12] 80015ec: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 80015ee: 4b58 ldr r3, [pc, #352] @ (8001750 ) 80015f0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80015f4: 4a56 ldr r2, [pc, #344] @ (8001750 ) 80015f6: f043 0380 orr.w r3, r3, #128 @ 0x80 80015fa: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80015fe: 4b54 ldr r3, [pc, #336] @ (8001750 ) 8001600: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001604: f003 0380 and.w r3, r3, #128 @ 0x80 8001608: 61bb str r3, [r7, #24] 800160a: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 800160c: 4b50 ldr r3, [pc, #320] @ (8001750 ) 800160e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001612: 4a4f ldr r2, [pc, #316] @ (8001750 ) 8001614: f043 0304 orr.w r3, r3, #4 8001618: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800161c: 4b4c ldr r3, [pc, #304] @ (8001750 ) 800161e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001622: f003 0304 and.w r3, r3, #4 8001626: 617b str r3, [r7, #20] 8001628: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 800162a: 4b49 ldr r3, [pc, #292] @ (8001750 ) 800162c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001630: 4a47 ldr r2, [pc, #284] @ (8001750 ) 8001632: f043 0301 orr.w r3, r3, #1 8001636: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800163a: 4b45 ldr r3, [pc, #276] @ (8001750 ) 800163c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001640: f003 0301 and.w r3, r3, #1 8001644: 613b str r3, [r7, #16] 8001646: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001648: 4b41 ldr r3, [pc, #260] @ (8001750 ) 800164a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800164e: 4a40 ldr r2, [pc, #256] @ (8001750 ) 8001650: f043 0302 orr.w r3, r3, #2 8001654: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001658: 4b3d ldr r3, [pc, #244] @ (8001750 ) 800165a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800165e: f003 0302 and.w r3, r3, #2 8001662: 60fb str r3, [r7, #12] 8001664: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8001666: 4b3a ldr r3, [pc, #232] @ (8001750 ) 8001668: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800166c: 4a38 ldr r2, [pc, #224] @ (8001750 ) 800166e: f043 0310 orr.w r3, r3, #16 8001672: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001676: 4b36 ldr r3, [pc, #216] @ (8001750 ) 8001678: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800167c: f003 0310 and.w r3, r3, #16 8001680: 60bb str r3, [r7, #8] 8001682: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001684: 4b32 ldr r3, [pc, #200] @ (8001750 ) 8001686: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800168a: 4a31 ldr r2, [pc, #196] @ (8001750 ) 800168c: f043 0308 orr.w r3, r3, #8 8001690: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001694: 4b2e ldr r3, [pc, #184] @ (8001750 ) 8001696: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800169a: f003 0308 and.w r3, r3, #8 800169e: 607b str r3, [r7, #4] 80016a0: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 80016a2: 2200 movs r2, #0 80016a4: f24e 7180 movw r1, #59264 @ 0xe780 80016a8: 482a ldr r0, [pc, #168] @ (8001754 ) 80016aa: f009 fa37 bl 800ab1c |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 80016ae: 2200 movs r2, #0 80016b0: 21f0 movs r1, #240 @ 0xf0 80016b2: 4829 ldr r0, [pc, #164] @ (8001758 ) 80016b4: f009 fa32 bl 800ab1c /*Configure GPIO pins : PE7 PE8 PE9 PE10 PE13 PE14 PE15 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 80016b8: f24e 7380 movw r3, #59264 @ 0xe780 80016bc: 61fb str r3, [r7, #28] |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80016be: 2301 movs r3, #1 80016c0: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016c2: 2300 movs r3, #0 80016c4: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80016c6: 2300 movs r3, #0 80016c8: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80016ca: f107 031c add.w r3, r7, #28 80016ce: 4619 mov r1, r3 80016d0: 4820 ldr r0, [pc, #128] @ (8001754 ) 80016d2: f009 f85b bl 800a78c /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12 PD13 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 80016d6: f44f 537c mov.w r3, #16128 @ 0x3f00 80016da: 61fb str r3, [r7, #28] |GPIO_PIN_12|GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 80016dc: f44f 1344 mov.w r3, #3211264 @ 0x310000 80016e0: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016e2: 2300 movs r3, #0 80016e4: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80016e6: f107 031c add.w r3, r7, #28 80016ea: 4619 mov r1, r3 80016ec: 481a ldr r0, [pc, #104] @ (8001758 ) 80016ee: f009 f84d bl 800a78c /*Configure GPIO pin : PD3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 80016f2: 2308 movs r3, #8 80016f4: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80016f6: 2300 movs r3, #0 80016f8: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80016fa: 2300 movs r3, #0 80016fc: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80016fe: f107 031c add.w r3, r7, #28 8001702: 4619 mov r1, r3 8001704: 4814 ldr r0, [pc, #80] @ (8001758 ) 8001706: f009 f841 bl 800a78c /*Configure GPIO pins : PD4 PD5 PD6 PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 800170a: 23f0 movs r3, #240 @ 0xf0 800170c: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800170e: 2301 movs r3, #1 8001710: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001712: 2300 movs r3, #0 8001714: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001716: 2300 movs r3, #0 8001718: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800171a: f107 031c add.w r3, r7, #28 800171e: 4619 mov r1, r3 8001720: 480d ldr r0, [pc, #52] @ (8001758 ) 8001722: f009 f833 bl 800a78c /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); 8001726: 2200 movs r2, #0 8001728: 2105 movs r1, #5 800172a: 2017 movs r0, #23 800172c: f005 fcfc bl 8007128 HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 8001730: 2017 movs r0, #23 8001732: f005 fd13 bl 800715c HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 8001736: 2200 movs r2, #0 8001738: 2105 movs r1, #5 800173a: 2028 movs r0, #40 @ 0x28 800173c: f005 fcf4 bl 8007128 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8001740: 2028 movs r0, #40 @ 0x28 8001742: f005 fd0b bl 800715c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8001746: bf00 nop 8001748: 3730 adds r7, #48 @ 0x30 800174a: 46bd mov sp, r7 800174c: bd80 pop {r7, pc} 800174e: bf00 nop 8001750: 58024400 .word 0x58024400 8001754: 58021000 .word 0x58021000 8001758: 58020c00 .word 0x58020c00 0800175c : /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 800175c: b580 push {r7, lr} 800175e: b08e sub sp, #56 @ 0x38 8001760: af00 add r7, sp, #0 8001762: 6078 str r0, [r7, #4] if(hadc->Instance == ADC1) 8001764: 687b ldr r3, [r7, #4] 8001766: 681b ldr r3, [r3, #0] 8001768: 4a67 ldr r2, [pc, #412] @ (8001908 ) 800176a: 4293 cmp r3, r2 800176c: d13f bne.n 80017ee { DbgLEDToggle(DBG_LED4); 800176e: 2080 movs r0, #128 @ 0x80 8001770: f001 fada bl 8002d28 SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 8001774: 4b65 ldr r3, [pc, #404] @ (800190c ) 8001776: f023 031f bic.w r3, r3, #31 800177a: 637b str r3, [r7, #52] @ 0x34 800177c: 2320 movs r3, #32 800177e: 633b str r3, [r7, #48] @ 0x30 \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { 8001780: 6b3b ldr r3, [r7, #48] @ 0x30 8001782: 2b00 cmp r3, #0 8001784: dd1d ble.n 80017c2 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 8001786: 6b7b ldr r3, [r7, #52] @ 0x34 8001788: f003 021f and.w r2, r3, #31 800178c: 6b3b ldr r3, [r7, #48] @ 0x30 800178e: 4413 add r3, r2 8001790: 62fb str r3, [r7, #44] @ 0x2c uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001792: 6b7b ldr r3, [r7, #52] @ 0x34 8001794: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("dsb 0xF":::"memory"); 8001796: f3bf 8f4f dsb sy } 800179a: bf00 nop __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 800179c: 4a5c ldr r2, [pc, #368] @ (8001910 ) 800179e: 6abb ldr r3, [r7, #40] @ 0x28 80017a0: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 80017a4: 6abb ldr r3, [r7, #40] @ 0x28 80017a6: 3320 adds r3, #32 80017a8: 62bb str r3, [r7, #40] @ 0x28 op_size -= __SCB_DCACHE_LINE_SIZE; 80017aa: 6afb ldr r3, [r7, #44] @ 0x2c 80017ac: 3b20 subs r3, #32 80017ae: 62fb str r3, [r7, #44] @ 0x2c } while ( op_size > 0 ); 80017b0: 6afb ldr r3, [r7, #44] @ 0x2c 80017b2: 2b00 cmp r3, #0 80017b4: dcf2 bgt.n 800179c __ASM volatile ("dsb 0xF":::"memory"); 80017b6: f3bf 8f4f dsb sy } 80017ba: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80017bc: f3bf 8f6f isb sy } 80017c0: bf00 nop __DSB(); __ISB(); } #endif } 80017c2: bf00 nop if(adc1MeasDataQueue != NULL) 80017c4: 4b53 ldr r3, [pc, #332] @ (8001914 ) 80017c6: 681b ldr r3, [r3, #0] 80017c8: 2b00 cmp r3, #0 80017ca: d006 beq.n 80017da { osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 80017cc: 4b51 ldr r3, [pc, #324] @ (8001914 ) 80017ce: 6818 ldr r0, [r3, #0] 80017d0: 2300 movs r3, #0 80017d2: 2200 movs r2, #0 80017d4: 494d ldr r1, [pc, #308] @ (800190c ) 80017d6: f012 fa79 bl 8013ccc } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 80017da: 2207 movs r2, #7 80017dc: 494b ldr r1, [pc, #300] @ (800190c ) 80017de: 484e ldr r0, [pc, #312] @ (8001918 ) 80017e0: f004 f9fe bl 8005be0 80017e4: 4603 mov r3, r0 80017e6: 2b00 cmp r3, #0 80017e8: d001 beq.n 80017ee { Error_Handler(); 80017ea: f000 fb11 bl 8001e10 } } if(hadc->Instance == ADC2) 80017ee: 687b ldr r3, [r7, #4] 80017f0: 681b ldr r3, [r3, #0] 80017f2: 4a4a ldr r2, [pc, #296] @ (800191c ) 80017f4: 4293 cmp r3, r2 80017f6: d13c bne.n 8001872 { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80017f8: 4b49 ldr r3, [pc, #292] @ (8001920 ) 80017fa: f023 031f bic.w r3, r3, #31 80017fe: 627b str r3, [r7, #36] @ 0x24 8001800: 2320 movs r3, #32 8001802: 623b str r3, [r7, #32] if ( dsize > 0 ) { 8001804: 6a3b ldr r3, [r7, #32] 8001806: 2b00 cmp r3, #0 8001808: dd1d ble.n 8001846 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 800180a: 6a7b ldr r3, [r7, #36] @ 0x24 800180c: f003 021f and.w r2, r3, #31 8001810: 6a3b ldr r3, [r7, #32] 8001812: 4413 add r3, r2 8001814: 61fb str r3, [r7, #28] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001816: 6a7b ldr r3, [r7, #36] @ 0x24 8001818: 61bb str r3, [r7, #24] __ASM volatile ("dsb 0xF":::"memory"); 800181a: f3bf 8f4f dsb sy } 800181e: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001820: 4a3b ldr r2, [pc, #236] @ (8001910 ) 8001822: 69bb ldr r3, [r7, #24] 8001824: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001828: 69bb ldr r3, [r7, #24] 800182a: 3320 adds r3, #32 800182c: 61bb str r3, [r7, #24] op_size -= __SCB_DCACHE_LINE_SIZE; 800182e: 69fb ldr r3, [r7, #28] 8001830: 3b20 subs r3, #32 8001832: 61fb str r3, [r7, #28] } while ( op_size > 0 ); 8001834: 69fb ldr r3, [r7, #28] 8001836: 2b00 cmp r3, #0 8001838: dcf2 bgt.n 8001820 __ASM volatile ("dsb 0xF":::"memory"); 800183a: f3bf 8f4f dsb sy } 800183e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001840: f3bf 8f6f isb sy } 8001844: bf00 nop } 8001846: bf00 nop if(adc2MeasDataQueue != NULL) 8001848: 4b36 ldr r3, [pc, #216] @ (8001924 ) 800184a: 681b ldr r3, [r3, #0] 800184c: 2b00 cmp r3, #0 800184e: d006 beq.n 800185e { osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0); 8001850: 4b34 ldr r3, [pc, #208] @ (8001924 ) 8001852: 6818 ldr r0, [r3, #0] 8001854: 2300 movs r3, #0 8001856: 2200 movs r2, #0 8001858: 4931 ldr r1, [pc, #196] @ (8001920 ) 800185a: f012 fa37 bl 8013ccc } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 800185e: 2203 movs r2, #3 8001860: 492f ldr r1, [pc, #188] @ (8001920 ) 8001862: 4831 ldr r0, [pc, #196] @ (8001928 ) 8001864: f004 f9bc bl 8005be0 8001868: 4603 mov r3, r0 800186a: 2b00 cmp r3, #0 800186c: d001 beq.n 8001872 { Error_Handler(); 800186e: f000 facf bl 8001e10 } } if(hadc->Instance == ADC3) 8001872: 687b ldr r3, [r7, #4] 8001874: 681b ldr r3, [r3, #0] 8001876: 4a2d ldr r2, [pc, #180] @ (800192c ) 8001878: 4293 cmp r3, r2 800187a: d13c bne.n 80018f6 { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 800187c: 4b2c ldr r3, [pc, #176] @ (8001930 ) 800187e: f023 031f bic.w r3, r3, #31 8001882: 617b str r3, [r7, #20] 8001884: 2320 movs r3, #32 8001886: 613b str r3, [r7, #16] if ( dsize > 0 ) { 8001888: 693b ldr r3, [r7, #16] 800188a: 2b00 cmp r3, #0 800188c: dd1d ble.n 80018ca int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 800188e: 697b ldr r3, [r7, #20] 8001890: f003 021f and.w r2, r3, #31 8001894: 693b ldr r3, [r7, #16] 8001896: 4413 add r3, r2 8001898: 60fb str r3, [r7, #12] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 800189a: 697b ldr r3, [r7, #20] 800189c: 60bb str r3, [r7, #8] __ASM volatile ("dsb 0xF":::"memory"); 800189e: f3bf 8f4f dsb sy } 80018a2: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 80018a4: 4a1a ldr r2, [pc, #104] @ (8001910 ) 80018a6: 68bb ldr r3, [r7, #8] 80018a8: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 80018ac: 68bb ldr r3, [r7, #8] 80018ae: 3320 adds r3, #32 80018b0: 60bb str r3, [r7, #8] op_size -= __SCB_DCACHE_LINE_SIZE; 80018b2: 68fb ldr r3, [r7, #12] 80018b4: 3b20 subs r3, #32 80018b6: 60fb str r3, [r7, #12] } while ( op_size > 0 ); 80018b8: 68fb ldr r3, [r7, #12] 80018ba: 2b00 cmp r3, #0 80018bc: dcf2 bgt.n 80018a4 __ASM volatile ("dsb 0xF":::"memory"); 80018be: f3bf 8f4f dsb sy } 80018c2: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80018c4: f3bf 8f6f isb sy } 80018c8: bf00 nop } 80018ca: bf00 nop if(adc3MeasDataQueue != NULL) 80018cc: 4b19 ldr r3, [pc, #100] @ (8001934 ) 80018ce: 681b ldr r3, [r3, #0] 80018d0: 2b00 cmp r3, #0 80018d2: d006 beq.n 80018e2 { osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 80018d4: 4b17 ldr r3, [pc, #92] @ (8001934 ) 80018d6: 6818 ldr r0, [r3, #0] 80018d8: 2300 movs r3, #0 80018da: 2200 movs r2, #0 80018dc: 4914 ldr r1, [pc, #80] @ (8001930 ) 80018de: f012 f9f5 bl 8013ccc } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 80018e2: 2205 movs r2, #5 80018e4: 4912 ldr r1, [pc, #72] @ (8001930 ) 80018e6: 4814 ldr r0, [pc, #80] @ (8001938 ) 80018e8: f004 f97a bl 8005be0 80018ec: 4603 mov r3, r0 80018ee: 2b00 cmp r3, #0 80018f0: d001 beq.n 80018f6 { Error_Handler(); 80018f2: f000 fa8d bl 8001e10 } }osTimerStop (debugLedTimerHandle); 80018f6: 4b11 ldr r3, [pc, #68] @ (800193c ) 80018f8: 681b ldr r3, [r3, #0] 80018fa: 4618 mov r0, r3 80018fc: f012 f82e bl 801395c } 8001900: bf00 nop 8001902: 3738 adds r7, #56 @ 0x38 8001904: 46bd mov sp, r7 8001906: bd80 pop {r7, pc} 8001908: 40022000 .word 0x40022000 800190c: 240000e0 .word 0x240000e0 8001910: e000ed00 .word 0xe000ed00 8001914: 240007c8 .word 0x240007c8 8001918: 24000140 .word 0x24000140 800191c: 40022100 .word 0x40022100 8001920: 24000100 .word 0x24000100 8001924: 240007cc .word 0x240007cc 8001928: 240001a4 .word 0x240001a4 800192c: 58026000 .word 0x58026000 8001930: 24000120 .word 0x24000120 8001934: 240007d0 .word 0x240007d0 8001938: 24000208 .word 0x24000208 800193c: 240006a8 .word 0x240006a8 08001940 : void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8001940: b580 push {r7, lr} 8001942: b084 sub sp, #16 8001944: af00 add r7, sp, #0 8001946: 6078 str r0, [r7, #4] if (htim->Instance == TIM4) 8001948: 687b ldr r3, [r7, #4] 800194a: 681b ldr r3, [r3, #0] 800194c: 4a42 ldr r2, [pc, #264] @ (8001a58 ) 800194e: 4293 cmp r3, r2 8001950: d13c bne.n 80019cc { if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 8001952: 687b ldr r3, [r7, #4] 8001954: 7f1b ldrb r3, [r3, #28] 8001956: 2b04 cmp r3, #4 8001958: d108 bne.n 800196c { encoderXChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 800195a: 2108 movs r1, #8 800195c: 6878 ldr r0, [r7, #4] 800195e: f00e f87f bl 800fa60 8001962: 4603 mov r3, r0 8001964: 461a mov r2, r3 8001966: 4b3d ldr r3, [pc, #244] @ (8001a5c ) 8001968: 601a str r2, [r3, #0] 800196a: e00b b.n 8001984 } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 800196c: 687b ldr r3, [r7, #4] 800196e: 7f1b ldrb r3, [r3, #28] 8001970: 2b08 cmp r3, #8 8001972: d107 bne.n 8001984 { encoderXChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001974: 210c movs r1, #12 8001976: 6878 ldr r0, [r7, #4] 8001978: f00e f872 bl 800fa60 800197c: 4603 mov r3, r0 800197e: 461a mov r2, r3 8001980: 4b37 ldr r3, [pc, #220] @ (8001a60 ) 8001982: 601a str r2, [r3, #0] } if((encoderXChannelA != 0) && (encoderXChannelB != 0)) 8001984: 4b35 ldr r3, [pc, #212] @ (8001a5c ) 8001986: 681b ldr r3, [r3, #0] 8001988: 2b00 cmp r3, #0 800198a: d060 beq.n 8001a4e 800198c: 4b34 ldr r3, [pc, #208] @ (8001a60 ) 800198e: 681b ldr r3, [r3, #0] 8001990: 2b00 cmp r3, #0 8001992: d05c beq.n 8001a4e { EncoderData encoderData = { 0 }; 8001994: 2300 movs r3, #0 8001996: 81bb strh r3, [r7, #12] encoderData.axe = encoderAxeX; 8001998: 2300 movs r3, #0 800199a: 733b strb r3, [r7, #12] encoderData.direction = encoderXChannelA - encoderXChannelB < 0 ? encoderCW : encoderCCW; 800199c: 4b2f ldr r3, [pc, #188] @ (8001a5c ) 800199e: 681a ldr r2, [r3, #0] 80019a0: 4b2f ldr r3, [pc, #188] @ (8001a60 ) 80019a2: 681b ldr r3, [r3, #0] 80019a4: 1ad3 subs r3, r2, r3 80019a6: 43db mvns r3, r3 80019a8: 0fdb lsrs r3, r3, #31 80019aa: b2db uxtb r3, r3 80019ac: 737b strb r3, [r7, #13] osMessageQueuePut(encoderXDataQueue, &encoderData, 0, 0); 80019ae: 4b2d ldr r3, [pc, #180] @ (8001a64 ) 80019b0: 6818 ldr r0, [r3, #0] 80019b2: f107 010c add.w r1, r7, #12 80019b6: 2300 movs r3, #0 80019b8: 2200 movs r2, #0 80019ba: f012 f987 bl 8013ccc encoderXChannelA = 0; 80019be: 4b27 ldr r3, [pc, #156] @ (8001a5c ) 80019c0: 2200 movs r2, #0 80019c2: 601a str r2, [r3, #0] encoderXChannelB = 0; 80019c4: 4b26 ldr r3, [pc, #152] @ (8001a60 ) 80019c6: 2200 movs r2, #0 80019c8: 601a str r2, [r3, #0] osMessageQueuePut(encoderYDataQueue, &encoderData, 0, 0); encoderYChannelA = 0; encoderYChannelB = 0; } } } 80019ca: e040 b.n 8001a4e } else if (htim->Instance == TIM2) 80019cc: 687b ldr r3, [r7, #4] 80019ce: 681b ldr r3, [r3, #0] 80019d0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80019d4: d13b bne.n 8001a4e if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 80019d6: 687b ldr r3, [r7, #4] 80019d8: 7f1b ldrb r3, [r3, #28] 80019da: 2b04 cmp r3, #4 80019dc: d108 bne.n 80019f0 encoderYChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 80019de: 2108 movs r1, #8 80019e0: 6878 ldr r0, [r7, #4] 80019e2: f00e f83d bl 800fa60 80019e6: 4603 mov r3, r0 80019e8: 461a mov r2, r3 80019ea: 4b1f ldr r3, [pc, #124] @ (8001a68 ) 80019ec: 601a str r2, [r3, #0] 80019ee: e00b b.n 8001a08 } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 80019f0: 687b ldr r3, [r7, #4] 80019f2: 7f1b ldrb r3, [r3, #28] 80019f4: 2b08 cmp r3, #8 80019f6: d107 bne.n 8001a08 encoderYChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 80019f8: 210c movs r1, #12 80019fa: 6878 ldr r0, [r7, #4] 80019fc: f00e f830 bl 800fa60 8001a00: 4603 mov r3, r0 8001a02: 461a mov r2, r3 8001a04: 4b19 ldr r3, [pc, #100] @ (8001a6c ) 8001a06: 601a str r2, [r3, #0] if((encoderYChannelA != 0) && (encoderYChannelB != 0)) 8001a08: 4b17 ldr r3, [pc, #92] @ (8001a68 ) 8001a0a: 681b ldr r3, [r3, #0] 8001a0c: 2b00 cmp r3, #0 8001a0e: d01e beq.n 8001a4e 8001a10: 4b16 ldr r3, [pc, #88] @ (8001a6c ) 8001a12: 681b ldr r3, [r3, #0] 8001a14: 2b00 cmp r3, #0 8001a16: d01a beq.n 8001a4e EncoderData encoderData = { 0 }; 8001a18: 2300 movs r3, #0 8001a1a: 813b strh r3, [r7, #8] encoderData.axe = encoderAxeY; 8001a1c: 2301 movs r3, #1 8001a1e: 723b strb r3, [r7, #8] encoderData.direction = encoderYChannelA - encoderYChannelB < 0 ? encoderCW : encoderCCW; 8001a20: 4b11 ldr r3, [pc, #68] @ (8001a68 ) 8001a22: 681a ldr r2, [r3, #0] 8001a24: 4b11 ldr r3, [pc, #68] @ (8001a6c ) 8001a26: 681b ldr r3, [r3, #0] 8001a28: 1ad3 subs r3, r2, r3 8001a2a: 43db mvns r3, r3 8001a2c: 0fdb lsrs r3, r3, #31 8001a2e: b2db uxtb r3, r3 8001a30: 727b strb r3, [r7, #9] osMessageQueuePut(encoderYDataQueue, &encoderData, 0, 0); 8001a32: 4b0f ldr r3, [pc, #60] @ (8001a70 ) 8001a34: 6818 ldr r0, [r3, #0] 8001a36: f107 0108 add.w r1, r7, #8 8001a3a: 2300 movs r3, #0 8001a3c: 2200 movs r2, #0 8001a3e: f012 f945 bl 8013ccc encoderYChannelA = 0; 8001a42: 4b09 ldr r3, [pc, #36] @ (8001a68 ) 8001a44: 2200 movs r2, #0 8001a46: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001a48: 4b08 ldr r3, [pc, #32] @ (8001a6c ) 8001a4a: 2200 movs r2, #0 8001a4c: 601a str r2, [r3, #0] } 8001a4e: bf00 nop 8001a50: 3710 adds r7, #16 8001a52: 46bd mov sp, r7 8001a54: bd80 pop {r7, pc} 8001a56: bf00 nop 8001a58: 40000800 .word 0x40000800 8001a5c: 240007a0 .word 0x240007a0 8001a60: 240007a4 .word 0x240007a4 8001a64: 240007d8 .word 0x240007d8 8001a68: 240007a8 .word 0x240007a8 8001a6c: 240007ac .word 0x240007ac 8001a70: 240007dc .word 0x240007dc 08001a74 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 8001a74: b580 push {r7, lr} 8001a76: b082 sub sp, #8 8001a78: af00 add r7, sp, #0 8001a7a: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ SelectCurrentSensorGain(CurrentSensorL1, csGain3); 8001a7c: 2102 movs r1, #2 8001a7e: 2000 movs r0, #0 8001a80: f001 f970 bl 8002d64 SelectCurrentSensorGain(CurrentSensorL2, csGain3); 8001a84: 2102 movs r1, #2 8001a86: 2001 movs r0, #1 8001a88: f001 f96c bl 8002d64 SelectCurrentSensorGain(CurrentSensorL3, csGain3); 8001a8c: 2102 movs r1, #2 8001a8e: 2002 movs r0, #2 8001a90: f001 f968 bl 8002d64 EnableCurrentSensors(); 8001a94: f001 f95a bl 8002d4c osDelay(pdMS_TO_TICKS(1000)); 8001a98: f44f 707a mov.w r0, #1000 @ 0x3e8 8001a9c: f011 fe83 bl 80137a6 if(HAL_TIM_Base_Start(&htim2) != HAL_OK) 8001aa0: 484c ldr r0, [pc, #304] @ (8001bd4 ) 8001aa2: f00c ff97 bl 800e9d4 8001aa6: 4603 mov r3, r0 8001aa8: 2b00 cmp r3, #0 8001aaa: d001 beq.n 8001ab0 { Error_Handler(); 8001aac: f000 f9b0 bl 8001e10 } if(HAL_TIM_Base_Start_IT(&htim4) != HAL_OK) 8001ab0: 4849 ldr r0, [pc, #292] @ (8001bd8 ) 8001ab2: f00c ffff bl 800eab4 8001ab6: 4603 mov r3, r0 8001ab8: 2b00 cmp r3, #0 8001aba: d001 beq.n 8001ac0 { Error_Handler(); 8001abc: f000 f9a8 bl 8001e10 } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_3) != HAL_OK) 8001ac0: 2108 movs r1, #8 8001ac2: 4845 ldr r0, [pc, #276] @ (8001bd8 ) 8001ac4: f00d facc bl 800f060 8001ac8: 4603 mov r3, r0 8001aca: 2b00 cmp r3, #0 8001acc: d001 beq.n 8001ad2 { Error_Handler(); 8001ace: f000 f99f bl 8001e10 } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_4) != HAL_OK) 8001ad2: 210c movs r1, #12 8001ad4: 4840 ldr r0, [pc, #256] @ (8001bd8 ) 8001ad6: f00d fac3 bl 800f060 8001ada: 4603 mov r3, r0 8001adc: 2b00 cmp r3, #0 8001ade: d001 beq.n 8001ae4 { Error_Handler(); 8001ae0: f000 f996 bl 8001e10 } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_3) != HAL_OK) 8001ae4: 2108 movs r1, #8 8001ae6: 483b ldr r0, [pc, #236] @ (8001bd4 ) 8001ae8: f00d faba bl 800f060 8001aec: 4603 mov r3, r0 8001aee: 2b00 cmp r3, #0 8001af0: d001 beq.n 8001af6 { Error_Handler(); 8001af2: f000 f98d bl 8001e10 } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_4) != HAL_OK) 8001af6: 210c movs r1, #12 8001af8: 4836 ldr r0, [pc, #216] @ (8001bd4 ) 8001afa: f00d fab1 bl 800f060 8001afe: 4603 mov r3, r0 8001b00: 2b00 cmp r3, #0 8001b02: d001 beq.n 8001b08 { Error_Handler(); 8001b04: f000 f984 bl 8001e10 } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001b08: 2207 movs r2, #7 8001b0a: 4934 ldr r1, [pc, #208] @ (8001bdc ) 8001b0c: 4834 ldr r0, [pc, #208] @ (8001be0 ) 8001b0e: f004 f867 bl 8005be0 8001b12: 4603 mov r3, r0 8001b14: 2b00 cmp r3, #0 8001b16: d001 beq.n 8001b1c { Error_Handler(); 8001b18: f000 f97a bl 8001e10 } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 8001b1c: 2203 movs r2, #3 8001b1e: 4931 ldr r1, [pc, #196] @ (8001be4 ) 8001b20: 4831 ldr r0, [pc, #196] @ (8001be8 ) 8001b22: f004 f85d bl 8005be0 8001b26: 4603 mov r3, r0 8001b28: 2b00 cmp r3, #0 8001b2a: d001 beq.n 8001b30 { Error_Handler(); 8001b2c: f000 f970 bl 8001e10 } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 8001b30: 2205 movs r2, #5 8001b32: 492e ldr r1, [pc, #184] @ (8001bec ) 8001b34: 482e ldr r0, [pc, #184] @ (8001bf0 ) 8001b36: f004 f853 bl 8005be0 8001b3a: 4603 mov r3, r0 8001b3c: 2b00 cmp r3, #0 8001b3e: d001 beq.n 8001b44 { Error_Handler(); 8001b40: f000 f966 bl 8001e10 } HAL_COMP_Start(&hcomp1); 8001b44: 482b ldr r0, [pc, #172] @ (8001bf4 ) 8001b46: f005 f9cf bl 8006ee8 /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(100)); 8001b4a: 2064 movs r0, #100 @ 0x64 8001b4c: f011 fe2b bl 80137a6 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001b50: 2100 movs r1, #0 8001b52: 4829 ldr r0, [pc, #164] @ (8001bf8 ) 8001b54: f00d ffe6 bl 800fb24 8001b58: 4603 mov r3, r0 8001b5a: 2b01 cmp r3, #1 8001b5c: d118 bne.n 8001b90 HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001b5e: 2104 movs r1, #4 8001b60: 4825 ldr r0, [pc, #148] @ (8001bf8 ) 8001b62: f00d ffdf bl 800fb24 8001b66: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001b68: 2b01 cmp r3, #1 8001b6a: d111 bne.n 8001b90 { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001b6c: 4b23 ldr r3, [pc, #140] @ (8001bfc ) 8001b6e: 681b ldr r3, [r3, #0] 8001b70: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001b74: 4618 mov r0, r3 8001b76: f011 ffae bl 8013ad6 8001b7a: 4603 mov r3, r0 8001b7c: 2b00 cmp r3, #0 8001b7e: d107 bne.n 8001b90 { sensorsInfo.motorXStatus = 0; 8001b80: 4b1f ldr r3, [pc, #124] @ (8001c00 ) 8001b82: 2200 movs r2, #0 8001b84: 751a strb r2, [r3, #20] osMutexRelease(sensorsInfoMutex); 8001b86: 4b1d ldr r3, [pc, #116] @ (8001bfc ) 8001b88: 681b ldr r3, [r3, #0] 8001b8a: 4618 mov r0, r3 8001b8c: f011 ffee bl 8013b6c } } if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001b90: 2108 movs r1, #8 8001b92: 4819 ldr r0, [pc, #100] @ (8001bf8 ) 8001b94: f00d ffc6 bl 800fb24 8001b98: 4603 mov r3, r0 8001b9a: 2b01 cmp r3, #1 8001b9c: d1d5 bne.n 8001b4a HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 8001b9e: 210c movs r1, #12 8001ba0: 4815 ldr r0, [pc, #84] @ (8001bf8 ) 8001ba2: f00d ffbf bl 800fb24 8001ba6: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001ba8: 2b01 cmp r3, #1 8001baa: d1ce bne.n 8001b4a { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001bac: 4b13 ldr r3, [pc, #76] @ (8001bfc ) 8001bae: 681b ldr r3, [r3, #0] 8001bb0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001bb4: 4618 mov r0, r3 8001bb6: f011 ff8e bl 8013ad6 8001bba: 4603 mov r3, r0 8001bbc: 2b00 cmp r3, #0 8001bbe: d1c4 bne.n 8001b4a { sensorsInfo.motorYStatus = 0; 8001bc0: 4b0f ldr r3, [pc, #60] @ (8001c00 ) 8001bc2: 2200 movs r2, #0 8001bc4: 755a strb r2, [r3, #21] osMutexRelease(sensorsInfoMutex); 8001bc6: 4b0d ldr r3, [pc, #52] @ (8001bfc ) 8001bc8: 681b ldr r3, [r3, #0] 8001bca: 4618 mov r0, r3 8001bcc: f011 ffce bl 8013b6c osDelay(pdMS_TO_TICKS(100)); 8001bd0: e7bb b.n 8001b4a 8001bd2: bf00 nop 8001bd4: 24000498 .word 0x24000498 8001bd8: 24000530 .word 0x24000530 8001bdc: 240000e0 .word 0x240000e0 8001be0: 24000140 .word 0x24000140 8001be4: 24000100 .word 0x24000100 8001be8: 240001a4 .word 0x240001a4 8001bec: 24000120 .word 0x24000120 8001bf0: 24000208 .word 0x24000208 8001bf4: 240003d4 .word 0x240003d4 8001bf8: 240004e4 .word 0x240004e4 8001bfc: 240007e8 .word 0x240007e8 8001c00: 2400082c .word 0x2400082c 08001c04 : /* USER CODE END 5 */ } /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { 8001c04: b580 push {r7, lr} 8001c06: b082 sub sp, #8 8001c08: af00 add r7, sp, #0 8001c0a: 6078 str r0, [r7, #4] /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 8001c0c: 2010 movs r0, #16 8001c0e: f001 f879 bl 8002d04 /* USER CODE END debugLedTimerCallback */ } 8001c12: bf00 nop 8001c14: 3708 adds r7, #8 8001c16: 46bd mov sp, r7 8001c18: bd80 pop {r7, pc} ... 08001c1c : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { 8001c1c: b580 push {r7, lr} 8001c1e: b082 sub sp, #8 8001c20: af00 add r7, sp, #0 8001c22: 6078 str r0, [r7, #4] /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 8001c24: 2104 movs r1, #4 8001c26: 4803 ldr r0, [pc, #12] @ (8001c34 ) 8001c28: f00d f922 bl 800ee70 /* USER CODE END fanTimerCallback */ } 8001c2c: bf00 nop 8001c2e: 3708 adds r7, #8 8001c30: 46bd mov sp, r7 8001c32: bd80 pop {r7, pc} 8001c34: 2400044c .word 0x2400044c 08001c38 : /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 8001c38: b580 push {r7, lr} 8001c3a: b084 sub sp, #16 8001c3c: af02 add r7, sp, #8 8001c3e: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorXTimerCallback */ motorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 8001c40: 2300 movs r3, #0 8001c42: 9301 str r3, [sp, #4] 8001c44: 2300 movs r3, #0 8001c46: 9300 str r3, [sp, #0] 8001c48: 2304 movs r3, #4 8001c4a: 2200 movs r2, #0 8001c4c: 4907 ldr r1, [pc, #28] @ (8001c6c ) 8001c4e: 4808 ldr r0, [pc, #32] @ (8001c70 ) 8001c50: f001 fa0d bl 800306e HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 8001c54: 2100 movs r1, #0 8001c56: 4806 ldr r0, [pc, #24] @ (8001c70 ) 8001c58: f00d f90a bl 800ee70 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 8001c5c: 2104 movs r1, #4 8001c5e: 4804 ldr r0, [pc, #16] @ (8001c70 ) 8001c60: f00d f906 bl 800ee70 /* USER CODE END motorXTimerCallback */ } 8001c64: bf00 nop 8001c66: 3708 adds r7, #8 8001c68: 46bd mov sp, r7 8001c6a: bd80 pop {r7, pc} 8001c6c: 24000784 .word 0x24000784 8001c70: 240004e4 .word 0x240004e4 08001c74 : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 8001c74: b580 push {r7, lr} 8001c76: b084 sub sp, #16 8001c78: af02 add r7, sp, #8 8001c7a: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorYTimerCallback */ motorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 8001c7c: 2300 movs r3, #0 8001c7e: 9301 str r3, [sp, #4] 8001c80: 2300 movs r3, #0 8001c82: 9300 str r3, [sp, #0] 8001c84: 230c movs r3, #12 8001c86: 2208 movs r2, #8 8001c88: 4907 ldr r1, [pc, #28] @ (8001ca8 ) 8001c8a: 4808 ldr r0, [pc, #32] @ (8001cac ) 8001c8c: f001 f9ef bl 800306e HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 8001c90: 2108 movs r1, #8 8001c92: 4806 ldr r0, [pc, #24] @ (8001cac ) 8001c94: f00d f8ec bl 800ee70 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 8001c98: 210c movs r1, #12 8001c9a: 4804 ldr r0, [pc, #16] @ (8001cac ) 8001c9c: f00d f8e8 bl 800ee70 /* USER CODE END motorYTimerCallback */ } 8001ca0: bf00 nop 8001ca2: 3708 adds r7, #8 8001ca4: 46bd mov sp, r7 8001ca6: bd80 pop {r7, pc} 8001ca8: 24000784 .word 0x24000784 8001cac: 240004e4 .word 0x240004e4 08001cb0 : /* MPU Configuration */ void MPU_Config(void) { 8001cb0: b580 push {r7, lr} 8001cb2: b084 sub sp, #16 8001cb4: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8001cb6: 463b mov r3, r7 8001cb8: 2200 movs r2, #0 8001cba: 601a str r2, [r3, #0] 8001cbc: 605a str r2, [r3, #4] 8001cbe: 609a str r2, [r3, #8] 8001cc0: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8001cc2: f005 fa59 bl 8007178 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8001cc6: 2301 movs r3, #1 8001cc8: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8001cca: 2300 movs r3, #0 8001ccc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001cce: 2300 movs r3, #0 8001cd0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8001cd2: 231f movs r3, #31 8001cd4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8001cd6: 2387 movs r3, #135 @ 0x87 8001cd8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001cda: 2300 movs r3, #0 8001cdc: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001cde: 2300 movs r3, #0 8001ce0: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8001ce2: 2301 movs r3, #1 8001ce4: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001ce6: 2301 movs r3, #1 8001ce8: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8001cea: 2300 movs r3, #0 8001cec: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001cee: 2300 movs r3, #0 8001cf0: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001cf2: 463b mov r3, r7 8001cf4: 4618 mov r0, r3 8001cf6: f005 fa77 bl 80071e8 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8001cfa: 2301 movs r3, #1 8001cfc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 8001cfe: 4b13 ldr r3, [pc, #76] @ (8001d4c ) 8001d00: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8001d02: 2310 movs r3, #16 8001d04: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 8001d06: 2300 movs r3, #0 8001d08: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8001d0a: 2301 movs r3, #1 8001d0c: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8001d0e: 2303 movs r3, #3 8001d10: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8001d12: 2300 movs r3, #0 8001d14: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001d16: 463b mov r3, r7 8001d18: 4618 mov r0, r3 8001d1a: f005 fa65 bl 80071e8 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8001d1e: 2302 movs r3, #2 8001d20: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 8001d22: 4b0b ldr r3, [pc, #44] @ (8001d50 ) 8001d24: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8001d26: 2308 movs r3, #8 8001d28: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001d2a: 2300 movs r3, #0 8001d2c: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001d2e: 2301 movs r3, #1 8001d30: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8001d32: 2301 movs r3, #1 8001d34: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001d36: 463b mov r3, r7 8001d38: 4618 mov r0, r3 8001d3a: f005 fa55 bl 80071e8 /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8001d3e: 2004 movs r0, #4 8001d40: f005 fa32 bl 80071a8 } 8001d44: bf00 nop 8001d46: 3710 adds r7, #16 8001d48: 46bd mov sp, r7 8001d4a: bd80 pop {r7, pc} 8001d4c: 24020000 .word 0x24020000 8001d50: 24040000 .word 0x24040000 08001d54 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001d54: b580 push {r7, lr} 8001d56: b082 sub sp, #8 8001d58: af00 add r7, sp, #0 8001d5a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8001d5c: 687b ldr r3, [r7, #4] 8001d5e: 681b ldr r3, [r3, #0] 8001d60: 4a25 ldr r2, [pc, #148] @ (8001df8 ) 8001d62: 4293 cmp r3, r2 8001d64: d102 bne.n 8001d6c HAL_IncTick(); 8001d66: f003 fb25 bl 80053b4 encoderYChannelA += htim->Instance->ARR; } } /* USER CODE END Callback 1 */ } 8001d6a: e040 b.n 8001dee else if (htim->Instance == TIM4) 8001d6c: 687b ldr r3, [r7, #4] 8001d6e: 681b ldr r3, [r3, #0] 8001d70: 4a22 ldr r2, [pc, #136] @ (8001dfc ) 8001d72: 4293 cmp r3, r2 8001d74: d11b bne.n 8001dae if(encoderXChannelA > 0) 8001d76: 4b22 ldr r3, [pc, #136] @ (8001e00 ) 8001d78: 681b ldr r3, [r3, #0] 8001d7a: 2b00 cmp r3, #0 8001d7c: dd09 ble.n 8001d92 encoderXChannelB += htim->Instance->ARR; 8001d7e: 687b ldr r3, [r7, #4] 8001d80: 681b ldr r3, [r3, #0] 8001d82: 6adb ldr r3, [r3, #44] @ 0x2c 8001d84: 4a1f ldr r2, [pc, #124] @ (8001e04 ) 8001d86: 6812 ldr r2, [r2, #0] 8001d88: 4413 add r3, r2 8001d8a: 461a mov r2, r3 8001d8c: 4b1d ldr r3, [pc, #116] @ (8001e04 ) 8001d8e: 601a str r2, [r3, #0] } 8001d90: e02d b.n 8001dee } else if(encoderXChannelB > 0) 8001d92: 4b1c ldr r3, [pc, #112] @ (8001e04 ) 8001d94: 681b ldr r3, [r3, #0] 8001d96: 2b00 cmp r3, #0 8001d98: dd29 ble.n 8001dee encoderXChannelA += htim->Instance->ARR; 8001d9a: 687b ldr r3, [r7, #4] 8001d9c: 681b ldr r3, [r3, #0] 8001d9e: 6adb ldr r3, [r3, #44] @ 0x2c 8001da0: 4a17 ldr r2, [pc, #92] @ (8001e00 ) 8001da2: 6812 ldr r2, [r2, #0] 8001da4: 4413 add r3, r2 8001da6: 461a mov r2, r3 8001da8: 4b15 ldr r3, [pc, #84] @ (8001e00 ) 8001daa: 601a str r2, [r3, #0] } 8001dac: e01f b.n 8001dee else if (htim->Instance == TIM2) 8001dae: 687b ldr r3, [r7, #4] 8001db0: 681b ldr r3, [r3, #0] 8001db2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001db6: d11a bne.n 8001dee if(encoderYChannelA > 0) 8001db8: 4b13 ldr r3, [pc, #76] @ (8001e08 ) 8001dba: 681b ldr r3, [r3, #0] 8001dbc: 2b00 cmp r3, #0 8001dbe: dd09 ble.n 8001dd4 encoderYChannelB += htim->Instance->ARR; 8001dc0: 687b ldr r3, [r7, #4] 8001dc2: 681b ldr r3, [r3, #0] 8001dc4: 6adb ldr r3, [r3, #44] @ 0x2c 8001dc6: 4a11 ldr r2, [pc, #68] @ (8001e0c ) 8001dc8: 6812 ldr r2, [r2, #0] 8001dca: 4413 add r3, r2 8001dcc: 461a mov r2, r3 8001dce: 4b0f ldr r3, [pc, #60] @ (8001e0c ) 8001dd0: 601a str r2, [r3, #0] } 8001dd2: e00c b.n 8001dee } else if(encoderYChannelB > 0) 8001dd4: 4b0d ldr r3, [pc, #52] @ (8001e0c ) 8001dd6: 681b ldr r3, [r3, #0] 8001dd8: 2b00 cmp r3, #0 8001dda: dd08 ble.n 8001dee encoderYChannelA += htim->Instance->ARR; 8001ddc: 687b ldr r3, [r7, #4] 8001dde: 681b ldr r3, [r3, #0] 8001de0: 6adb ldr r3, [r3, #44] @ 0x2c 8001de2: 4a09 ldr r2, [pc, #36] @ (8001e08 ) 8001de4: 6812 ldr r2, [r2, #0] 8001de6: 4413 add r3, r2 8001de8: 461a mov r2, r3 8001dea: 4b07 ldr r3, [pc, #28] @ (8001e08 ) 8001dec: 601a str r2, [r3, #0] } 8001dee: bf00 nop 8001df0: 3708 adds r7, #8 8001df2: 46bd mov sp, r7 8001df4: bd80 pop {r7, pc} 8001df6: bf00 nop 8001df8: 40001000 .word 0x40001000 8001dfc: 40000800 .word 0x40000800 8001e00: 240007a0 .word 0x240007a0 8001e04: 240007a4 .word 0x240007a4 8001e08: 240007a8 .word 0x240007a8 8001e0c: 240007ac .word 0x240007ac 08001e10 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001e10: b480 push {r7} 8001e12: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001e14: b672 cpsid i } 8001e16: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8001e18: bf00 nop 8001e1a: e7fd b.n 8001e18 08001e1c : extern TIM_OC_InitTypeDef motorXYTimerConfigOC; extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; void MeasTasksInit (void) { 8001e1c: b580 push {r7, lr} 8001e1e: b0b6 sub sp, #216 @ 0xd8 8001e20: af00 add r7, sp, #0 vRefmVMutex = osMutexNew (NULL); 8001e22: 2000 movs r0, #0 8001e24: f011 fdd1 bl 80139ca 8001e28: 4603 mov r3, r0 8001e2a: 4a69 ldr r2, [pc, #420] @ (8001fd0 ) 8001e2c: 6013 str r3, [r2, #0] resMeasurementsMutex = osMutexNew (NULL); 8001e2e: 2000 movs r0, #0 8001e30: f011 fdcb bl 80139ca 8001e34: 4603 mov r3, r0 8001e36: 4a67 ldr r2, [pc, #412] @ (8001fd4 ) 8001e38: 6013 str r3, [r2, #0] sensorsInfoMutex = osMutexNew (NULL); 8001e3a: 2000 movs r0, #0 8001e3c: f011 fdc5 bl 80139ca 8001e40: 4603 mov r3, r0 8001e42: 4a65 ldr r2, [pc, #404] @ (8001fd8 ) 8001e44: 6013 str r3, [r2, #0] ILxRefMutex = osMutexNew (NULL); 8001e46: 2000 movs r0, #0 8001e48: f011 fdbf bl 80139ca 8001e4c: 4603 mov r3, r0 8001e4e: 4a63 ldr r2, [pc, #396] @ (8001fdc ) 8001e50: 6013 str r3, [r2, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001e52: 2200 movs r2, #0 8001e54: 2120 movs r1, #32 8001e56: 2008 movs r0, #8 8001e58: f011 fec5 bl 8013be6 8001e5c: 4603 mov r3, r0 8001e5e: 4a60 ldr r2, [pc, #384] @ (8001fe0 ) 8001e60: 6013 str r3, [r2, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001e62: 2200 movs r2, #0 8001e64: 2120 movs r1, #32 8001e66: 2008 movs r0, #8 8001e68: f011 febd bl 8013be6 8001e6c: 4603 mov r3, r0 8001e6e: 4a5d ldr r2, [pc, #372] @ (8001fe4 ) 8001e70: 6013 str r3, [r2, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001e72: 2200 movs r2, #0 8001e74: 2120 movs r1, #32 8001e76: 2008 movs r0, #8 8001e78: f011 feb5 bl 8013be6 8001e7c: 4603 mov r3, r0 8001e7e: 4a5a ldr r2, [pc, #360] @ (8001fe8 ) 8001e80: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001e82: f107 03b4 add.w r3, r7, #180 @ 0xb4 8001e86: 2224 movs r2, #36 @ 0x24 8001e88: 2100 movs r1, #0 8001e8a: 4618 mov r0, r3 8001e8c: f015 fe63 bl 8017b56 osThreadAttr_t osThreadAttradc2MeasTask = { 0 }; 8001e90: f107 0390 add.w r3, r7, #144 @ 0x90 8001e94: 2224 movs r2, #36 @ 0x24 8001e96: 2100 movs r1, #0 8001e98: 4618 mov r0, r3 8001e9a: f015 fe5c bl 8017b56 osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001e9e: f107 036c add.w r3, r7, #108 @ 0x6c 8001ea2: 2224 movs r2, #36 @ 0x24 8001ea4: 2100 movs r1, #0 8001ea6: 4618 mov r0, r3 8001ea8: f015 fe55 bl 8017b56 osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001eac: f44f 6380 mov.w r3, #1024 @ 0x400 8001eb0: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001eb4: 2330 movs r3, #48 @ 0x30 8001eb6: f8c7 30cc str.w r3, [r7, #204] @ 0xcc osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001eba: f44f 6380 mov.w r3, #1024 @ 0x400 8001ebe: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 osThreadAttradc2MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001ec2: 2330 movs r3, #48 @ 0x30 8001ec4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001ec8: f44f 6380 mov.w r3, #1024 @ 0x400 8001ecc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001ed0: 2318 movs r3, #24 8001ed2: f8c7 3084 str.w r3, [r7, #132] @ 0x84 adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001ed6: f107 03b4 add.w r3, r7, #180 @ 0xb4 8001eda: 461a mov r2, r3 8001edc: 2100 movs r1, #0 8001ede: 4843 ldr r0, [pc, #268] @ (8001fec ) 8001ee0: f011 fbce bl 8013680 8001ee4: 4603 mov r3, r0 8001ee6: 4a42 ldr r2, [pc, #264] @ (8001ff0 ) 8001ee8: 6013 str r3, [r2, #0] adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask); 8001eea: f107 0390 add.w r3, r7, #144 @ 0x90 8001eee: 461a mov r2, r3 8001ef0: 2100 movs r1, #0 8001ef2: 4840 ldr r0, [pc, #256] @ (8001ff4 ) 8001ef4: f011 fbc4 bl 8013680 8001ef8: 4603 mov r3, r0 8001efa: 4a3f ldr r2, [pc, #252] @ (8001ff8 ) 8001efc: 6013 str r3, [r2, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001efe: f107 036c add.w r3, r7, #108 @ 0x6c 8001f02: 461a mov r2, r3 8001f04: 2100 movs r1, #0 8001f06: 483d ldr r0, [pc, #244] @ (8001ffc ) 8001f08: f011 fbba bl 8013680 8001f0c: 4603 mov r3, r0 8001f0e: 4a3c ldr r2, [pc, #240] @ (8002000 ) 8001f10: 6013 str r3, [r2, #0] limiterSwitchDataQueue = osMessageQueueNew (8, sizeof (LimiterSwitchData), NULL); 8001f12: 2200 movs r2, #0 8001f14: 2104 movs r1, #4 8001f16: 2008 movs r0, #8 8001f18: f011 fe65 bl 8013be6 8001f1c: 4603 mov r3, r0 8001f1e: 4a39 ldr r2, [pc, #228] @ (8002004 ) 8001f20: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001f22: f107 0348 add.w r3, r7, #72 @ 0x48 8001f26: 2224 movs r2, #36 @ 0x24 8001f28: 2100 movs r1, #0 8001f2a: 4618 mov r0, r3 8001f2c: f015 fe13 bl 8017b56 osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f30: f44f 6380 mov.w r3, #1024 @ 0x400 8001f34: 65fb str r3, [r7, #92] @ 0x5c osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001f36: 2318 movs r3, #24 8001f38: 663b str r3, [r7, #96] @ 0x60 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001f3a: f107 0348 add.w r3, r7, #72 @ 0x48 8001f3e: 461a mov r2, r3 8001f40: 2100 movs r1, #0 8001f42: 4831 ldr r0, [pc, #196] @ (8002008 ) 8001f44: f011 fb9c bl 8013680 8001f48: 4603 mov r3, r0 8001f4a: 4a30 ldr r2, [pc, #192] @ (800200c ) 8001f4c: 6013 str r3, [r2, #0] encoderXDataQueue = osMessageQueueNew (8, sizeof (EncoderData), NULL); 8001f4e: 2200 movs r2, #0 8001f50: 2102 movs r1, #2 8001f52: 2008 movs r0, #8 8001f54: f011 fe47 bl 8013be6 8001f58: 4603 mov r3, r0 8001f5a: 4a2d ldr r2, [pc, #180] @ (8002010 ) 8001f5c: 6013 str r3, [r2, #0] encoderYDataQueue = osMessageQueueNew (8, sizeof (EncoderData), NULL); 8001f5e: 2200 movs r2, #0 8001f60: 2102 movs r1, #2 8001f62: 2008 movs r0, #8 8001f64: f011 fe3f bl 8013be6 8001f68: 4603 mov r3, r0 8001f6a: 4a2a ldr r2, [pc, #168] @ (8002014 ) 8001f6c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrEncoderXTask = { 0 }; 8001f6e: f107 0324 add.w r3, r7, #36 @ 0x24 8001f72: 2224 movs r2, #36 @ 0x24 8001f74: 2100 movs r1, #0 8001f76: 4618 mov r0, r3 8001f78: f015 fded bl 8017b56 osThreadAttrEncoderXTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f7c: f44f 6380 mov.w r3, #1024 @ 0x400 8001f80: 63bb str r3, [r7, #56] @ 0x38 osThreadAttrEncoderXTask.priority = (osPriority_t)osPriorityNormal; 8001f82: 2318 movs r3, #24 8001f84: 63fb str r3, [r7, #60] @ 0x3c encoderXTaskHandle = osThreadNew (EncoderTask, encoderXDataQueue, &osThreadAttrEncoderXTask); 8001f86: 4b22 ldr r3, [pc, #136] @ (8002010 ) 8001f88: 681b ldr r3, [r3, #0] 8001f8a: f107 0224 add.w r2, r7, #36 @ 0x24 8001f8e: 4619 mov r1, r3 8001f90: 4821 ldr r0, [pc, #132] @ (8002018 ) 8001f92: f011 fb75 bl 8013680 8001f96: 4603 mov r3, r0 8001f98: 4a20 ldr r2, [pc, #128] @ (800201c ) 8001f9a: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrEncoderYTask = { 0 }; 8001f9c: 463b mov r3, r7 8001f9e: 2224 movs r2, #36 @ 0x24 8001fa0: 2100 movs r1, #0 8001fa2: 4618 mov r0, r3 8001fa4: f015 fdd7 bl 8017b56 osThreadAttrEncoderYTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001fa8: f44f 6380 mov.w r3, #1024 @ 0x400 8001fac: 617b str r3, [r7, #20] osThreadAttrEncoderYTask.priority = (osPriority_t)osPriorityNormal; 8001fae: 2318 movs r3, #24 8001fb0: 61bb str r3, [r7, #24] encoderYTaskHandle = osThreadNew (EncoderTask, encoderYDataQueue, &osThreadAttrEncoderYTask); 8001fb2: 4b18 ldr r3, [pc, #96] @ (8002014 ) 8001fb4: 681b ldr r3, [r3, #0] 8001fb6: 463a mov r2, r7 8001fb8: 4619 mov r1, r3 8001fba: 4817 ldr r0, [pc, #92] @ (8002018 ) 8001fbc: f011 fb60 bl 8013680 8001fc0: 4603 mov r3, r0 8001fc2: 4a17 ldr r2, [pc, #92] @ (8002020 ) 8001fc4: 6013 str r3, [r2, #0] } 8001fc6: bf00 nop 8001fc8: 37d8 adds r7, #216 @ 0xd8 8001fca: 46bd mov sp, r7 8001fcc: bd80 pop {r7, pc} 8001fce: bf00 nop 8001fd0: 240007e0 .word 0x240007e0 8001fd4: 240007e4 .word 0x240007e4 8001fd8: 240007e8 .word 0x240007e8 8001fdc: 240007ec .word 0x240007ec 8001fe0: 240007c8 .word 0x240007c8 8001fe4: 240007cc .word 0x240007cc 8001fe8: 240007d0 .word 0x240007d0 8001fec: 08002029 .word 0x08002029 8001ff0: 240007b0 .word 0x240007b0 8001ff4: 080023b1 .word 0x080023b1 8001ff8: 240007b4 .word 0x240007b4 8001ffc: 080026b9 .word 0x080026b9 8002000: 240007b8 .word 0x240007b8 8002004: 240007d4 .word 0x240007d4 8002008: 08002a35 .word 0x08002a35 800200c: 240007bc .word 0x240007bc 8002010: 240007d8 .word 0x240007d8 8002014: 240007dc .word 0x240007dc 8002018: 08002c25 .word 0x08002c25 800201c: 240007c0 .word 0x240007c0 8002020: 240007c4 .word 0x240007c4 8002024: 00000000 .word 0x00000000 08002028 : void ADC1MeasTask (void* arg) { 8002028: b580 push {r7, lr} 800202a: b09a sub sp, #104 @ 0x68 800202c: af00 add r7, sp, #0 800202e: 6078 str r0, [r7, #4] float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN] = { 0 }; 8002030: f107 032c add.w r3, r7, #44 @ 0x2c 8002034: 2228 movs r2, #40 @ 0x28 8002036: 2100 movs r1, #0 8002038: 4618 mov r0, r3 800203a: f015 fd8c bl 8017b56 float rms[VOLTAGES_COUNT] = { 0 }; 800203e: f04f 0300 mov.w r3, #0 8002042: 62bb str r3, [r7, #40] @ 0x28 ; ADC1_Data adcData = { 0 }; 8002044: f107 0308 add.w r3, r7, #8 8002048: 2220 movs r2, #32 800204a: 2100 movs r1, #0 800204c: 4618 mov r0, r3 800204e: f015 fd82 bl 8017b56 uint32_t circBuffPos = 0; 8002052: 2300 movs r3, #0 8002054: 667b str r3, [r7, #100] @ 0x64 float gainCorrection = 1.0; 8002056: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 800205a: 663b str r3, [r7, #96] @ 0x60 while (pdTRUE) { osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 800205c: 4bc8 ldr r3, [pc, #800] @ (8002380 ) 800205e: 6818 ldr r0, [r3, #0] 8002060: f107 0108 add.w r1, r7, #8 8002064: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002068: 2200 movs r2, #0 800206a: f011 fe8f bl 8013d8c #ifdef GAIN_AUTO_CORRECTION if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 800206e: 4bc5 ldr r3, [pc, #788] @ (8002384 ) 8002070: 681b ldr r3, [r3, #0] 8002072: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002076: 4618 mov r0, r3 8002078: f011 fd2d bl 8013ad6 800207c: 4603 mov r3, r0 800207e: 2b00 cmp r3, #0 8002080: d10c bne.n 800209c gainCorrection = (float)vRefmV; 8002082: 4bc1 ldr r3, [pc, #772] @ (8002388 ) 8002084: 681b ldr r3, [r3, #0] 8002086: ee07 3a90 vmov s15, r3 800208a: eef8 7a67 vcvt.f32.u32 s15, s15 800208e: edc7 7a18 vstr s15, [r7, #96] @ 0x60 osMutexRelease (vRefmVMutex); 8002092: 4bbc ldr r3, [pc, #752] @ (8002384 ) 8002094: 681b ldr r3, [r3, #0] 8002096: 4618 mov r0, r3 8002098: f011 fd68 bl 8013b6c } gainCorrection = gainCorrection / EXT_VREF_mV; 800209c: ed97 7a18 vldr s14, [r7, #96] @ 0x60 80020a0: eddf 6aba vldr s13, [pc, #744] @ 800238c 80020a4: eec7 7a26 vdiv.f32 s15, s14, s13 80020a8: edc7 7a18 vstr s15, [r7, #96] @ 0x60 #endif for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 80020ac: 2300 movs r3, #0 80020ae: f887 305f strb.w r3, [r7, #95] @ 0x5f 80020b2: e0e7 b.n 8002284 float val = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 80020b4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80020b8: 005b lsls r3, r3, #1 80020ba: 3368 adds r3, #104 @ 0x68 80020bc: 443b add r3, r7 80020be: f833 3c60 ldrh.w r3, [r3, #-96] 80020c2: ee07 3a90 vmov s15, r3 80020c6: eeb8 7be7 vcvt.f64.s32 d7, s15 80020ca: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80020ce: ee27 6b06 vmul.f64 d6, d7, d6 80020d2: ed9f 5ba5 vldr d5, [pc, #660] @ 8002368 80020d6: ee86 7b05 vdiv.f64 d7, d6, d5 80020da: ed9f 6ba5 vldr d6, [pc, #660] @ 8002370 80020de: ee27 6b06 vmul.f64 d6, d7, d6 80020e2: edd7 7a18 vldr s15, [r7, #96] @ 0x60 80020e6: eeb7 7ae7 vcvt.f64.f32 d7, s15 80020ea: ee26 6b07 vmul.f64 d6, d6, d7 80020ee: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80020f2: 4aa7 ldr r2, [pc, #668] @ (8002390 ) 80020f4: 00db lsls r3, r3, #3 80020f6: 4413 add r3, r2 80020f8: edd3 7a00 vldr s15, [r3] 80020fc: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002100: ee26 6b07 vmul.f64 d6, d6, d7 8002104: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002108: 4aa1 ldr r2, [pc, #644] @ (8002390 ) 800210a: 00db lsls r3, r3, #3 800210c: 4413 add r3, r2 800210e: 3304 adds r3, #4 8002110: edd3 7a00 vldr s15, [r3] 8002114: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002118: ee36 7b07 vadd.f64 d7, d6, d7 800211c: eef7 7bc7 vcvt.f32.f64 s15, d7 8002120: edc7 7a15 vstr s15, [r7, #84] @ 0x54 circBuffer[i][circBuffPos] = val; 8002124: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002128: 4613 mov r3, r2 800212a: 009b lsls r3, r3, #2 800212c: 4413 add r3, r2 800212e: 005b lsls r3, r3, #1 8002130: 6e7a ldr r2, [r7, #100] @ 0x64 8002132: 4413 add r3, r2 8002134: 009b lsls r3, r3, #2 8002136: 3368 adds r3, #104 @ 0x68 8002138: 443b add r3, r7 800213a: 3b3c subs r3, #60 @ 0x3c 800213c: 6d7a ldr r2, [r7, #84] @ 0x54 800213e: 601a str r2, [r3, #0] rms[i] = 0.0; 8002140: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002144: 009b lsls r3, r3, #2 8002146: 3368 adds r3, #104 @ 0x68 8002148: 443b add r3, r7 800214a: 3b40 subs r3, #64 @ 0x40 800214c: f04f 0200 mov.w r2, #0 8002150: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8002152: 2300 movs r3, #0 8002154: f887 305e strb.w r3, [r7, #94] @ 0x5e 8002158: e025 b.n 80021a6 rms[i] += circBuffer[i][c]; 800215a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800215e: 009b lsls r3, r3, #2 8002160: 3368 adds r3, #104 @ 0x68 8002162: 443b add r3, r7 8002164: 3b40 subs r3, #64 @ 0x40 8002166: ed93 7a00 vldr s14, [r3] 800216a: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 800216e: f897 105e ldrb.w r1, [r7, #94] @ 0x5e 8002172: 4613 mov r3, r2 8002174: 009b lsls r3, r3, #2 8002176: 4413 add r3, r2 8002178: 005b lsls r3, r3, #1 800217a: 440b add r3, r1 800217c: 009b lsls r3, r3, #2 800217e: 3368 adds r3, #104 @ 0x68 8002180: 443b add r3, r7 8002182: 3b3c subs r3, #60 @ 0x3c 8002184: edd3 7a00 vldr s15, [r3] 8002188: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800218c: ee77 7a27 vadd.f32 s15, s14, s15 8002190: 009b lsls r3, r3, #2 8002192: 3368 adds r3, #104 @ 0x68 8002194: 443b add r3, r7 8002196: 3b40 subs r3, #64 @ 0x40 8002198: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 800219c: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 80021a0: 3301 adds r3, #1 80021a2: f887 305e strb.w r3, [r7, #94] @ 0x5e 80021a6: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 80021aa: 2b09 cmp r3, #9 80021ac: d9d5 bls.n 800215a } rms[i] = rms[i] / CIRC_BUFF_LEN; 80021ae: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021b2: 009b lsls r3, r3, #2 80021b4: 3368 adds r3, #104 @ 0x68 80021b6: 443b add r3, r7 80021b8: 3b40 subs r3, #64 @ 0x40 80021ba: ed93 7a00 vldr s14, [r3] 80021be: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021c2: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80021c6: eec7 7a26 vdiv.f32 s15, s14, s13 80021ca: 009b lsls r3, r3, #2 80021cc: 3368 adds r3, #104 @ 0x68 80021ce: 443b add r3, r7 80021d0: 3b40 subs r3, #64 @ 0x40 80021d2: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80021d6: 4b6f ldr r3, [pc, #444] @ (8002394 ) 80021d8: 681b ldr r3, [r3, #0] 80021da: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80021de: 4618 mov r0, r3 80021e0: f011 fc79 bl 8013ad6 80021e4: 4603 mov r3, r0 80021e6: 2b00 cmp r3, #0 80021e8: d147 bne.n 800227a if (fabs (resMeasurements.voltagePeak[i]) < fabs (val)) { 80021ea: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021ee: 4a6a ldr r2, [pc, #424] @ (8002398 ) 80021f0: 3302 adds r3, #2 80021f2: 009b lsls r3, r3, #2 80021f4: 4413 add r3, r2 80021f6: 3304 adds r3, #4 80021f8: edd3 7a00 vldr s15, [r3] 80021fc: eeb0 7ae7 vabs.f32 s14, s15 8002200: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8002204: eef0 7ae7 vabs.f32 s15, s15 8002208: eeb4 7ae7 vcmpe.f32 s14, s15 800220c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002210: d508 bpl.n 8002224 resMeasurements.voltagePeak[i] = val; 8002212: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002216: 4a60 ldr r2, [pc, #384] @ (8002398 ) 8002218: 3302 adds r3, #2 800221a: 009b lsls r3, r3, #2 800221c: 4413 add r3, r2 800221e: 3304 adds r3, #4 8002220: 6d7a ldr r2, [r7, #84] @ 0x54 8002222: 601a str r2, [r3, #0] } resMeasurements.voltageRMS[i] = rms[i]; 8002224: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002228: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800222c: 0092 lsls r2, r2, #2 800222e: 3268 adds r2, #104 @ 0x68 8002230: 443a add r2, r7 8002232: 3a40 subs r2, #64 @ 0x40 8002234: 6812 ldr r2, [r2, #0] 8002236: 4958 ldr r1, [pc, #352] @ (8002398 ) 8002238: 009b lsls r3, r3, #2 800223a: 440b add r3, r1 800223c: 601a str r2, [r3, #0] resMeasurements.power[i] = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i]; 800223e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002242: 4a55 ldr r2, [pc, #340] @ (8002398 ) 8002244: 009b lsls r3, r3, #2 8002246: 4413 add r3, r2 8002248: ed93 7a00 vldr s14, [r3] 800224c: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002250: 4a51 ldr r2, [pc, #324] @ (8002398 ) 8002252: 3306 adds r3, #6 8002254: 009b lsls r3, r3, #2 8002256: 4413 add r3, r2 8002258: edd3 7a00 vldr s15, [r3] 800225c: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002260: ee67 7a27 vmul.f32 s15, s14, s15 8002264: 4a4c ldr r2, [pc, #304] @ (8002398 ) 8002266: 330c adds r3, #12 8002268: 009b lsls r3, r3, #2 800226a: 4413 add r3, r2 800226c: edc3 7a00 vstr s15, [r3] osMutexRelease (resMeasurementsMutex); 8002270: 4b48 ldr r3, [pc, #288] @ (8002394 ) 8002272: 681b ldr r3, [r3, #0] 8002274: 4618 mov r0, r3 8002276: f011 fc79 bl 8013b6c for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 800227a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800227e: 3301 adds r3, #1 8002280: f887 305f strb.w r3, [r7, #95] @ 0x5f 8002284: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002288: 2b00 cmp r3, #0 800228a: f43f af13 beq.w 80020b4 } } ++circBuffPos; 800228e: 6e7b ldr r3, [r7, #100] @ 0x64 8002290: 3301 adds r3, #1 8002292: 667b str r3, [r7, #100] @ 0x64 circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002294: 6e7a ldr r2, [r7, #100] @ 0x64 8002296: 4b41 ldr r3, [pc, #260] @ (800239c ) 8002298: fba3 1302 umull r1, r3, r3, r2 800229c: 08d9 lsrs r1, r3, #3 800229e: 460b mov r3, r1 80022a0: 009b lsls r3, r3, #2 80022a2: 440b add r3, r1 80022a4: 005b lsls r3, r3, #1 80022a6: 1ad3 subs r3, r2, r3 80022a8: 667b str r3, [r7, #100] @ 0x64 if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 80022aa: 4b3d ldr r3, [pc, #244] @ (80023a0 ) 80022ac: 681b ldr r3, [r3, #0] 80022ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80022b2: 4618 mov r0, r3 80022b4: f011 fc0f bl 8013ad6 80022b8: 4603 mov r3, r0 80022ba: 2b00 cmp r3, #0 80022bc: d124 bne.n 8002308 uint8_t refIdx = 0; 80022be: 2300 movs r3, #0 80022c0: f887 305d strb.w r3, [r7, #93] @ 0x5d for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 80022c4: 2303 movs r3, #3 80022c6: f887 305c strb.w r3, [r7, #92] @ 0x5c 80022ca: e014 b.n 80022f6 ILxRef[refIdx++] = adcData.adcDataBuffer[i]; 80022cc: f897 205c ldrb.w r2, [r7, #92] @ 0x5c 80022d0: f897 305d ldrb.w r3, [r7, #93] @ 0x5d 80022d4: 1c59 adds r1, r3, #1 80022d6: f887 105d strb.w r1, [r7, #93] @ 0x5d 80022da: 4619 mov r1, r3 80022dc: 0053 lsls r3, r2, #1 80022de: 3368 adds r3, #104 @ 0x68 80022e0: 443b add r3, r7 80022e2: f833 2c60 ldrh.w r2, [r3, #-96] 80022e6: 4b2f ldr r3, [pc, #188] @ (80023a4 ) 80022e8: f823 2011 strh.w r2, [r3, r1, lsl #1] for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 80022ec: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 80022f0: 3301 adds r3, #1 80022f2: f887 305c strb.w r3, [r7, #92] @ 0x5c 80022f6: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 80022fa: 2b05 cmp r3, #5 80022fc: d9e6 bls.n 80022cc } osMutexRelease (ILxRefMutex); 80022fe: 4b28 ldr r3, [pc, #160] @ (80023a0 ) 8002300: 681b ldr r3, [r3, #0] 8002302: 4618 mov r0, r3 8002304: f011 fc32 bl 8013b6c } float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8002308: 8abb ldrh r3, [r7, #20] 800230a: ee07 3a90 vmov s15, r3 800230e: eeb8 7be7 vcvt.f64.s32 d7, s15 8002312: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002316: ee27 6b06 vmul.f64 d6, d7, d6 800231a: ed9f 5b13 vldr d5, [pc, #76] @ 8002368 800231e: ee86 7b05 vdiv.f64 d7, d6, d5 8002322: ed9f 6b15 vldr d6, [pc, #84] @ 8002378 8002326: ee27 7b06 vmul.f64 d7, d7, d6 800232a: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 800232e: ee37 7b06 vadd.f64 d7, d7, d6 8002332: eef7 7bc7 vcvt.f32.f64 s15, d7 8002336: edc7 7a16 vstr s15, [r7, #88] @ 0x58 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800233a: 4b1b ldr r3, [pc, #108] @ (80023a8 ) 800233c: 681b ldr r3, [r3, #0] 800233e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002342: 4618 mov r0, r3 8002344: f011 fbc7 bl 8013ad6 8002348: 4603 mov r3, r0 800234a: 2b00 cmp r3, #0 800234c: f47f ae86 bne.w 800205c sensorsInfo.fanVoltage = fanFBVoltage; 8002350: 4a16 ldr r2, [pc, #88] @ (80023ac ) 8002352: 6dbb ldr r3, [r7, #88] @ 0x58 8002354: 6093 str r3, [r2, #8] osMutexRelease (sensorsInfoMutex); 8002356: 4b14 ldr r3, [pc, #80] @ (80023a8 ) 8002358: 681b ldr r3, [r3, #0] 800235a: 4618 mov r0, r3 800235c: f011 fc06 bl 8013b6c while (pdTRUE) { 8002360: e67c b.n 800205c 8002362: bf00 nop 8002364: f3af 8000 nop.w 8002368: 00000000 .word 0x00000000 800236c: 40efffe0 .word 0x40efffe0 8002370: f5c28f5c .word 0xf5c28f5c 8002374: 401e5c28 .word 0x401e5c28 8002378: 66666666 .word 0x66666666 800237c: c0116666 .word 0xc0116666 8002380: 240007c8 .word 0x240007c8 8002384: 240007e0 .word 0x240007e0 8002388: 24000030 .word 0x24000030 800238c: 453b8000 .word 0x453b8000 8002390: 24000000 .word 0x24000000 8002394: 240007e4 .word 0x240007e4 8002398: 240007f0 .word 0x240007f0 800239c: cccccccd .word 0xcccccccd 80023a0: 240007ec .word 0x240007ec 80023a4: 2400085c .word 0x2400085c 80023a8: 240007e8 .word 0x240007e8 80023ac: 2400082c .word 0x2400082c 080023b0 : } } } void ADC2MeasTask (void* arg) { 80023b0: b580 push {r7, lr} 80023b2: b09c sub sp, #112 @ 0x70 80023b4: af00 add r7, sp, #0 80023b6: 6078 str r0, [r7, #4] float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN] = { 0 }; 80023b8: f107 0334 add.w r3, r7, #52 @ 0x34 80023bc: 2228 movs r2, #40 @ 0x28 80023be: 2100 movs r1, #0 80023c0: 4618 mov r0, r3 80023c2: f015 fbc8 bl 8017b56 float rms[CURRENTS_COUNT] = { 0 }; 80023c6: f04f 0300 mov.w r3, #0 80023ca: 633b str r3, [r7, #48] @ 0x30 ADC2_Data adcData = { 0 }; 80023cc: f107 0310 add.w r3, r7, #16 80023d0: 2220 movs r2, #32 80023d2: 2100 movs r1, #0 80023d4: 4618 mov r0, r3 80023d6: f015 fbbe bl 8017b56 uint32_t circBuffPos = 0; 80023da: 2300 movs r3, #0 80023dc: 66fb str r3, [r7, #108] @ 0x6c float gainCorrection = 1.0; 80023de: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 80023e2: 66bb str r3, [r7, #104] @ 0x68 while (pdTRUE) { osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever); 80023e4: 4baa ldr r3, [pc, #680] @ (8002690 ) 80023e6: 6818 ldr r0, [r3, #0] 80023e8: f107 0110 add.w r1, r7, #16 80023ec: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80023f0: 2200 movs r2, #0 80023f2: f011 fccb bl 8013d8c if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80023f6: 4ba7 ldr r3, [pc, #668] @ (8002694 ) 80023f8: 681b ldr r3, [r3, #0] 80023fa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80023fe: 4618 mov r0, r3 8002400: f011 fb69 bl 8013ad6 8002404: 4603 mov r3, r0 8002406: 2b00 cmp r3, #0 8002408: d10c bne.n 8002424 gainCorrection = (float)vRefmV; 800240a: 4ba3 ldr r3, [pc, #652] @ (8002698 ) 800240c: 681b ldr r3, [r3, #0] 800240e: ee07 3a90 vmov s15, r3 8002412: eef8 7a67 vcvt.f32.u32 s15, s15 8002416: edc7 7a1a vstr s15, [r7, #104] @ 0x68 osMutexRelease (vRefmVMutex); 800241a: 4b9e ldr r3, [pc, #632] @ (8002694 ) 800241c: 681b ldr r3, [r3, #0] 800241e: 4618 mov r0, r3 8002420: f011 fba4 bl 8013b6c } gainCorrection = gainCorrection / EXT_VREF_mV; 8002424: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8002428: eddf 6a9c vldr s13, [pc, #624] @ 800269c 800242c: eec7 7a26 vdiv.f32 s15, s14, s13 8002430: edc7 7a1a vstr s15, [r7, #104] @ 0x68 float ref[CURRENTS_COUNT] = { 0 }; 8002434: f04f 0300 mov.w r3, #0 8002438: 60fb str r3, [r7, #12] if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 800243a: 4b99 ldr r3, [pc, #612] @ (80026a0 ) 800243c: 681b ldr r3, [r3, #0] 800243e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002442: 4618 mov r0, r3 8002444: f011 fb47 bl 8013ad6 8002448: 4603 mov r3, r0 800244a: 2b00 cmp r3, #0 800244c: d122 bne.n 8002494 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 800244e: 2300 movs r3, #0 8002450: f887 3067 strb.w r3, [r7, #103] @ 0x67 8002454: e015 b.n 8002482 ref[i] = (float)ILxRef[i]; 8002456: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 800245a: 4a92 ldr r2, [pc, #584] @ (80026a4 ) 800245c: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 8002460: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8002464: ee07 2a90 vmov s15, r2 8002468: eef8 7a67 vcvt.f32.u32 s15, s15 800246c: 009b lsls r3, r3, #2 800246e: 3370 adds r3, #112 @ 0x70 8002470: 443b add r3, r7 8002472: 3b64 subs r3, #100 @ 0x64 8002474: edc3 7a00 vstr s15, [r3] for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8002478: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 800247c: 3301 adds r3, #1 800247e: f887 3067 strb.w r3, [r7, #103] @ 0x67 8002482: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 8002486: 2b00 cmp r3, #0 8002488: d0e5 beq.n 8002456 } osMutexRelease (ILxRefMutex); 800248a: 4b85 ldr r3, [pc, #532] @ (80026a0 ) 800248c: 681b ldr r3, [r3, #0] 800248e: 4618 mov r0, r3 8002490: f011 fb6c bl 8013b6c } for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8002494: 2300 movs r3, #0 8002496: f887 3066 strb.w r3, [r7, #102] @ 0x66 800249a: e0db b.n 8002654 float adcVal = (float)adcData.adcDataBuffer[i]; 800249c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80024a0: 005b lsls r3, r3, #1 80024a2: 3370 adds r3, #112 @ 0x70 80024a4: 443b add r3, r7 80024a6: f833 3c60 ldrh.w r3, [r3, #-96] 80024aa: ee07 3a90 vmov s15, r3 80024ae: eef8 7a67 vcvt.f32.u32 s15, s15 80024b2: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float val = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 80024b6: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80024ba: 009b lsls r3, r3, #2 80024bc: 3370 adds r3, #112 @ 0x70 80024be: 443b add r3, r7 80024c0: 3b64 subs r3, #100 @ 0x64 80024c2: edd3 7a00 vldr s15, [r3] 80024c6: ed97 7a18 vldr s14, [r7, #96] @ 0x60 80024ca: ee77 7a67 vsub.f32 s15, s14, s15 80024ce: eeb7 7ae7 vcvt.f64.f32 d7, s15 80024d2: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80024d6: ee27 6b06 vmul.f64 d6, d7, d6 80024da: ed9f 5b69 vldr d5, [pc, #420] @ 8002680 80024de: ee86 7b05 vdiv.f64 d7, d6, d5 80024e2: ed9f 6b69 vldr d6, [pc, #420] @ 8002688 80024e6: ee27 6b06 vmul.f64 d6, d7, d6 80024ea: edd7 7a1a vldr s15, [r7, #104] @ 0x68 80024ee: eeb7 7ae7 vcvt.f64.f32 d7, s15 80024f2: ee26 6b07 vmul.f64 d6, d6, d7 80024f6: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80024fa: 4a6b ldr r2, [pc, #428] @ (80026a8 ) 80024fc: 00db lsls r3, r3, #3 80024fe: 4413 add r3, r2 8002500: edd3 7a00 vldr s15, [r3] 8002504: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002508: ee26 6b07 vmul.f64 d6, d6, d7 800250c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002510: 4a65 ldr r2, [pc, #404] @ (80026a8 ) 8002512: 00db lsls r3, r3, #3 8002514: 4413 add r3, r2 8002516: 3304 adds r3, #4 8002518: edd3 7a00 vldr s15, [r3] 800251c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002520: ee36 7b07 vadd.f64 d7, d6, d7 8002524: eef7 7bc7 vcvt.f32.f64 s15, d7 8002528: edc7 7a17 vstr s15, [r7, #92] @ 0x5c circBuffer[i][circBuffPos] = val; 800252c: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002530: 4613 mov r3, r2 8002532: 009b lsls r3, r3, #2 8002534: 4413 add r3, r2 8002536: 005b lsls r3, r3, #1 8002538: 6efa ldr r2, [r7, #108] @ 0x6c 800253a: 4413 add r3, r2 800253c: 009b lsls r3, r3, #2 800253e: 3370 adds r3, #112 @ 0x70 8002540: 443b add r3, r7 8002542: 3b3c subs r3, #60 @ 0x3c 8002544: 6dfa ldr r2, [r7, #92] @ 0x5c 8002546: 601a str r2, [r3, #0] rms[i] = 0.0; 8002548: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800254c: 009b lsls r3, r3, #2 800254e: 3370 adds r3, #112 @ 0x70 8002550: 443b add r3, r7 8002552: 3b40 subs r3, #64 @ 0x40 8002554: f04f 0200 mov.w r2, #0 8002558: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 800255a: 2300 movs r3, #0 800255c: f887 3065 strb.w r3, [r7, #101] @ 0x65 8002560: e025 b.n 80025ae rms[i] += circBuffer[i][c]; 8002562: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002566: 009b lsls r3, r3, #2 8002568: 3370 adds r3, #112 @ 0x70 800256a: 443b add r3, r7 800256c: 3b40 subs r3, #64 @ 0x40 800256e: ed93 7a00 vldr s14, [r3] 8002572: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002576: f897 1065 ldrb.w r1, [r7, #101] @ 0x65 800257a: 4613 mov r3, r2 800257c: 009b lsls r3, r3, #2 800257e: 4413 add r3, r2 8002580: 005b lsls r3, r3, #1 8002582: 440b add r3, r1 8002584: 009b lsls r3, r3, #2 8002586: 3370 adds r3, #112 @ 0x70 8002588: 443b add r3, r7 800258a: 3b3c subs r3, #60 @ 0x3c 800258c: edd3 7a00 vldr s15, [r3] 8002590: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002594: ee77 7a27 vadd.f32 s15, s14, s15 8002598: 009b lsls r3, r3, #2 800259a: 3370 adds r3, #112 @ 0x70 800259c: 443b add r3, r7 800259e: 3b40 subs r3, #64 @ 0x40 80025a0: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80025a4: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 80025a8: 3301 adds r3, #1 80025aa: f887 3065 strb.w r3, [r7, #101] @ 0x65 80025ae: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 80025b2: 2b09 cmp r3, #9 80025b4: d9d5 bls.n 8002562 } rms[i] = rms[i] / CIRC_BUFF_LEN; 80025b6: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025ba: 009b lsls r3, r3, #2 80025bc: 3370 adds r3, #112 @ 0x70 80025be: 443b add r3, r7 80025c0: 3b40 subs r3, #64 @ 0x40 80025c2: ed93 7a00 vldr s14, [r3] 80025c6: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025ca: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80025ce: eec7 7a26 vdiv.f32 s15, s14, s13 80025d2: 009b lsls r3, r3, #2 80025d4: 3370 adds r3, #112 @ 0x70 80025d6: 443b add r3, r7 80025d8: 3b40 subs r3, #64 @ 0x40 80025da: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80025de: 4b33 ldr r3, [pc, #204] @ (80026ac ) 80025e0: 681b ldr r3, [r3, #0] 80025e2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80025e6: 4618 mov r0, r3 80025e8: f011 fa75 bl 8013ad6 80025ec: 4603 mov r3, r0 80025ee: 2b00 cmp r3, #0 80025f0: d12b bne.n 800264a if (resMeasurements.currentPeak[i] < val) { 80025f2: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025f6: 4a2e ldr r2, [pc, #184] @ (80026b0 ) 80025f8: 3308 adds r3, #8 80025fa: 009b lsls r3, r3, #2 80025fc: 4413 add r3, r2 80025fe: 3304 adds r3, #4 8002600: edd3 7a00 vldr s15, [r3] 8002604: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8002608: eeb4 7ae7 vcmpe.f32 s14, s15 800260c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002610: dd08 ble.n 8002624 resMeasurements.currentPeak[i] = val; 8002612: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002616: 4a26 ldr r2, [pc, #152] @ (80026b0 ) 8002618: 3308 adds r3, #8 800261a: 009b lsls r3, r3, #2 800261c: 4413 add r3, r2 800261e: 3304 adds r3, #4 8002620: 6dfa ldr r2, [r7, #92] @ 0x5c 8002622: 601a str r2, [r3, #0] } resMeasurements.currentRMS[i] = rms[i]; 8002624: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002628: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800262c: 0092 lsls r2, r2, #2 800262e: 3270 adds r2, #112 @ 0x70 8002630: 443a add r2, r7 8002632: 3a40 subs r2, #64 @ 0x40 8002634: 6812 ldr r2, [r2, #0] 8002636: 491e ldr r1, [pc, #120] @ (80026b0 ) 8002638: 3306 adds r3, #6 800263a: 009b lsls r3, r3, #2 800263c: 440b add r3, r1 800263e: 601a str r2, [r3, #0] osMutexRelease (resMeasurementsMutex); 8002640: 4b1a ldr r3, [pc, #104] @ (80026ac ) 8002642: 681b ldr r3, [r3, #0] 8002644: 4618 mov r0, r3 8002646: f011 fa91 bl 8013b6c for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 800264a: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800264e: 3301 adds r3, #1 8002650: f887 3066 strb.w r3, [r7, #102] @ 0x66 8002654: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002658: 2b00 cmp r3, #0 800265a: f43f af1f beq.w 800249c } } ++circBuffPos; 800265e: 6efb ldr r3, [r7, #108] @ 0x6c 8002660: 3301 adds r3, #1 8002662: 66fb str r3, [r7, #108] @ 0x6c circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002664: 6efa ldr r2, [r7, #108] @ 0x6c 8002666: 4b13 ldr r3, [pc, #76] @ (80026b4 ) 8002668: fba3 1302 umull r1, r3, r3, r2 800266c: 08d9 lsrs r1, r3, #3 800266e: 460b mov r3, r1 8002670: 009b lsls r3, r3, #2 8002672: 440b add r3, r1 8002674: 005b lsls r3, r3, #1 8002676: 1ad3 subs r3, r2, r3 8002678: 66fb str r3, [r7, #108] @ 0x6c while (pdTRUE) { 800267a: e6b3 b.n 80023e4 800267c: f3af 8000 nop.w 8002680: 00000000 .word 0x00000000 8002684: 40efffe0 .word 0x40efffe0 8002688: 83e425af .word 0x83e425af 800268c: 401e4d9e .word 0x401e4d9e 8002690: 240007cc .word 0x240007cc 8002694: 240007e0 .word 0x240007e0 8002698: 24000030 .word 0x24000030 800269c: 453b8000 .word 0x453b8000 80026a0: 240007ec .word 0x240007ec 80026a4: 2400085c .word 0x2400085c 80026a8: 24000018 .word 0x24000018 80026ac: 240007e4 .word 0x240007e4 80026b0: 240007f0 .word 0x240007f0 80026b4: cccccccd .word 0xcccccccd 080026b8 : } } void ADC3MeasTask (void* arg) { 80026b8: b580 push {r7, lr} 80026ba: b0bc sub sp, #240 @ 0xf0 80026bc: af00 add r7, sp, #0 80026be: 6078 str r0, [r7, #4] float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 80026c0: f107 03a4 add.w r3, r7, #164 @ 0xa4 80026c4: 2228 movs r2, #40 @ 0x28 80026c6: 2100 movs r1, #0 80026c8: 4618 mov r0, r3 80026ca: f015 fa44 bl 8017b56 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 80026ce: f107 037c add.w r3, r7, #124 @ 0x7c 80026d2: 2228 movs r2, #40 @ 0x28 80026d4: 2100 movs r1, #0 80026d6: 4618 mov r0, r3 80026d8: f015 fa3d bl 8017b56 float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 80026dc: f107 0354 add.w r3, r7, #84 @ 0x54 80026e0: 2228 movs r2, #40 @ 0x28 80026e2: 2100 movs r1, #0 80026e4: 4618 mov r0, r3 80026e6: f015 fa36 bl 8017b56 float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 80026ea: f107 032c add.w r3, r7, #44 @ 0x2c 80026ee: 2228 movs r2, #40 @ 0x28 80026f0: 2100 movs r1, #0 80026f2: 4618 mov r0, r3 80026f4: f015 fa2f bl 8017b56 uint32_t circBuffPos = 0; 80026f8: 2300 movs r3, #0 80026fa: f8c7 30ec str.w r3, [r7, #236] @ 0xec ADC3_Data adcData = { 0 }; 80026fe: f107 030c add.w r3, r7, #12 8002702: 2220 movs r2, #32 8002704: 2100 movs r1, #0 8002706: 4618 mov r0, r3 8002708: f015 fa25 bl 8017b56 while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 800270c: 4bc2 ldr r3, [pc, #776] @ (8002a18 ) 800270e: 6818 ldr r0, [r3, #0] 8002710: f107 010c add.w r1, r7, #12 8002714: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002718: 2200 movs r2, #0 800271a: f011 fb37 bl 8013d8c uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 800271e: 4bbf ldr r3, [pc, #764] @ (8002a1c ) 8002720: 881b ldrh r3, [r3, #0] 8002722: 461a mov r2, r3 8002724: f640 43e4 movw r3, #3300 @ 0xce4 8002728: fb02 f303 mul.w r3, r2, r3 800272c: 8aba ldrh r2, [r7, #20] 800272e: fbb3 f3f2 udiv r3, r3, r2 8002732: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8002736: 4bba ldr r3, [pc, #744] @ (8002a20 ) 8002738: 681b ldr r3, [r3, #0] 800273a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800273e: 4618 mov r0, r3 8002740: f011 f9c9 bl 8013ad6 8002744: 4603 mov r3, r0 8002746: 2b00 cmp r3, #0 8002748: d108 bne.n 800275c vRefmV = vRef; 800274a: 4ab6 ldr r2, [pc, #728] @ (8002a24 ) 800274c: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8002750: 6013 str r3, [r2, #0] osMutexRelease (vRefmVMutex); 8002752: 4bb3 ldr r3, [pc, #716] @ (8002a20 ) 8002754: 681b ldr r3, [r3, #0] 8002756: 4618 mov r0, r3 8002758: f011 fa08 bl 8013b6c } float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 800275c: 8a3b ldrh r3, [r7, #16] 800275e: ee07 3a90 vmov s15, r3 8002762: eeb8 7be7 vcvt.f64.s32 d7, s15 8002766: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800276a: ee27 6b06 vmul.f64 d6, d7, d6 800276e: ed9f 5ba2 vldr d5, [pc, #648] @ 80029f8 8002772: ee86 7b05 vdiv.f64 d7, d6, d5 8002776: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 800277a: ee27 6b06 vmul.f64 d6, d7, d6 800277e: ed9f 5ba0 vldr d5, [pc, #640] @ 8002a00 8002782: ee86 7b05 vdiv.f64 d7, d6, d5 8002786: eef7 7bc7 vcvt.f32.f64 s15, d7 800278a: edc7 7a34 vstr s15, [r7, #208] @ 0xd0 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 800278e: 8a7b ldrh r3, [r7, #18] 8002790: ee07 3a90 vmov s15, r3 8002794: eeb8 7be7 vcvt.f64.s32 d7, s15 8002798: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800279c: ee27 6b06 vmul.f64 d6, d7, d6 80027a0: ed9f 5b95 vldr d5, [pc, #596] @ 80029f8 80027a4: ee86 7b05 vdiv.f64 d7, d6, d5 80027a8: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 80027ac: ee27 6b06 vmul.f64 d6, d7, d6 80027b0: ed9f 5b93 vldr d5, [pc, #588] @ 8002a00 80027b4: ee86 7b05 vdiv.f64 d7, d6, d5 80027b8: eef7 7bc7 vcvt.f32.f64 s15, d7 80027bc: edc7 7a33 vstr s15, [r7, #204] @ 0xcc motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 80027c0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80027c4: 009b lsls r3, r3, #2 80027c6: 33f0 adds r3, #240 @ 0xf0 80027c8: 443b add r3, r7 80027ca: 3b4c subs r3, #76 @ 0x4c 80027cc: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80027d0: 601a str r2, [r3, #0] motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 80027d2: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80027d6: 009b lsls r3, r3, #2 80027d8: 33f0 adds r3, #240 @ 0xf0 80027da: 443b add r3, r7 80027dc: 3b74 subs r3, #116 @ 0x74 80027de: f8d7 20cc ldr.w r2, [r7, #204] @ 0xcc 80027e2: 601a str r2, [r3, #0] pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 80027e4: 89bb ldrh r3, [r7, #12] 80027e6: ee07 3a90 vmov s15, r3 80027ea: eeb8 7be7 vcvt.f64.s32 d7, s15 80027ee: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80027f2: ee27 6b06 vmul.f64 d6, d7, d6 80027f6: ed9f 5b80 vldr d5, [pc, #512] @ 80029f8 80027fa: ee86 7b05 vdiv.f64 d7, d6, d5 80027fe: ed9f 6b82 vldr d6, [pc, #520] @ 8002a08 8002802: ee27 7b06 vmul.f64 d7, d7, d6 8002806: ed9f 6b82 vldr d6, [pc, #520] @ 8002a10 800280a: ee37 7b46 vsub.f64 d7, d7, d6 800280e: eef7 7bc7 vcvt.f32.f64 s15, d7 8002812: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002816: 009b lsls r3, r3, #2 8002818: 33f0 adds r3, #240 @ 0xf0 800281a: 443b add r3, r7 800281c: 3b9c subs r3, #156 @ 0x9c 800281e: edc3 7a00 vstr s15, [r3] pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 8002822: 89fb ldrh r3, [r7, #14] 8002824: ee07 3a90 vmov s15, r3 8002828: eeb8 7be7 vcvt.f64.s32 d7, s15 800282c: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002830: ee27 6b06 vmul.f64 d6, d7, d6 8002834: ed9f 5b70 vldr d5, [pc, #448] @ 80029f8 8002838: ee86 7b05 vdiv.f64 d7, d6, d5 800283c: ed9f 6b72 vldr d6, [pc, #456] @ 8002a08 8002840: ee27 7b06 vmul.f64 d7, d7, d6 8002844: ed9f 6b72 vldr d6, [pc, #456] @ 8002a10 8002848: ee37 7b46 vsub.f64 d7, d7, d6 800284c: eef7 7bc7 vcvt.f32.f64 s15, d7 8002850: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002854: 009b lsls r3, r3, #2 8002856: 33f0 adds r3, #240 @ 0xf0 8002858: 443b add r3, r7 800285a: 3bc4 subs r3, #196 @ 0xc4 800285c: edc3 7a00 vstr s15, [r3] float motorXAveCurrent = 0; 8002860: f04f 0300 mov.w r3, #0 8002864: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 float motorYAveCurrent = 0; 8002868: f04f 0300 mov.w r3, #0 800286c: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 float pvT1AveTemp = 0; 8002870: f04f 0300 mov.w r3, #0 8002874: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 float pvT2AveTemp = 0; 8002878: f04f 0300 mov.w r3, #0 800287c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002880: 2300 movs r3, #0 8002882: f887 30db strb.w r3, [r7, #219] @ 0xdb 8002886: e03c b.n 8002902 motorXAveCurrent += motorXSensCircBuffer[i]; 8002888: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800288c: 009b lsls r3, r3, #2 800288e: 33f0 adds r3, #240 @ 0xf0 8002890: 443b add r3, r7 8002892: 3b4c subs r3, #76 @ 0x4c 8002894: edd3 7a00 vldr s15, [r3] 8002898: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800289c: ee77 7a27 vadd.f32 s15, s14, s15 80028a0: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 80028a4: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80028a8: 009b lsls r3, r3, #2 80028aa: 33f0 adds r3, #240 @ 0xf0 80028ac: 443b add r3, r7 80028ae: 3b74 subs r3, #116 @ 0x74 80028b0: edd3 7a00 vldr s15, [r3] 80028b4: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 80028b8: ee77 7a27 vadd.f32 s15, s14, s15 80028bc: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 #ifdef PV_BOARD pvT1AveTemp += pvT1CircBuffer[i]; 80028c0: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80028c4: 009b lsls r3, r3, #2 80028c6: 33f0 adds r3, #240 @ 0xf0 80028c8: 443b add r3, r7 80028ca: 3b9c subs r3, #156 @ 0x9c 80028cc: edd3 7a00 vldr s15, [r3] 80028d0: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 80028d4: ee77 7a27 vadd.f32 s15, s14, s15 80028d8: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp += pvT2CircBuffer[i]; 80028dc: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80028e0: 009b lsls r3, r3, #2 80028e2: 33f0 adds r3, #240 @ 0xf0 80028e4: 443b add r3, r7 80028e6: 3bc4 subs r3, #196 @ 0xc4 80028e8: edd3 7a00 vldr s15, [r3] 80028ec: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 80028f0: ee77 7a27 vadd.f32 s15, s14, s15 80028f4: edc7 7a37 vstr s15, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 80028f8: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80028fc: 3301 adds r3, #1 80028fe: f887 30db strb.w r3, [r7, #219] @ 0xdb 8002902: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002906: 2b09 cmp r3, #9 8002908: d9be bls.n 8002888 #endif } motorXAveCurrent /= CIRC_BUFF_LEN; 800290a: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800290e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002912: eec7 7a26 vdiv.f32 s15, s14, s13 8002916: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent /= CIRC_BUFF_LEN; 800291a: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 800291e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002922: eec7 7a26 vdiv.f32 s15, s14, s13 8002926: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp /= CIRC_BUFF_LEN; 800292a: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 800292e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002932: eec7 7a26 vdiv.f32 s15, s14, s13 8002936: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp /= CIRC_BUFF_LEN; 800293a: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 800293e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002942: eec7 7a26 vdiv.f32 s15, s14, s13 8002946: edc7 7a37 vstr s15, [r7, #220] @ 0xdc if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800294a: 4b37 ldr r3, [pc, #220] @ (8002a28 ) 800294c: 681b ldr r3, [r3, #0] 800294e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002952: 4618 mov r0, r3 8002954: f011 f8bf bl 8013ad6 8002958: 4603 mov r3, r0 800295a: 2b00 cmp r3, #0 800295c: d138 bne.n 80029d0 if (sensorsInfo.motorXStatus == 1) { 800295e: 4b33 ldr r3, [pc, #204] @ (8002a2c ) 8002960: 7d1b ldrb r3, [r3, #20] 8002962: 2b01 cmp r3, #1 8002964: d111 bne.n 800298a sensorsInfo.motorXAveCurrent = motorXAveCurrent; 8002966: 4a31 ldr r2, [pc, #196] @ (8002a2c ) 8002968: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 800296c: 6193 str r3, [r2, #24] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 800296e: 4b2f ldr r3, [pc, #188] @ (8002a2c ) 8002970: edd3 7a08 vldr s15, [r3, #32] 8002974: ed97 7a34 vldr s14, [r7, #208] @ 0xd0 8002978: eeb4 7ae7 vcmpe.f32 s14, s15 800297c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002980: dd03 ble.n 800298a sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 8002982: 4a2a ldr r2, [pc, #168] @ (8002a2c ) 8002984: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 8002988: 6213 str r3, [r2, #32] } } if (sensorsInfo.motorYStatus == 1) { 800298a: 4b28 ldr r3, [pc, #160] @ (8002a2c ) 800298c: 7d5b ldrb r3, [r3, #21] 800298e: 2b01 cmp r3, #1 8002990: d111 bne.n 80029b6 sensorsInfo.motorYAveCurrent = motorYAveCurrent; 8002992: 4a26 ldr r2, [pc, #152] @ (8002a2c ) 8002994: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002998: 61d3 str r3, [r2, #28] if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 800299a: 4b24 ldr r3, [pc, #144] @ (8002a2c ) 800299c: edd3 7a09 vldr s15, [r3, #36] @ 0x24 80029a0: ed97 7a33 vldr s14, [r7, #204] @ 0xcc 80029a4: eeb4 7ae7 vcmpe.f32 s14, s15 80029a8: eef1 fa10 vmrs APSR_nzcv, fpscr 80029ac: dd03 ble.n 80029b6 sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 80029ae: 4a1f ldr r2, [pc, #124] @ (8002a2c ) 80029b0: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 80029b4: 6253 str r3, [r2, #36] @ 0x24 } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; 80029b6: 4a1d ldr r2, [pc, #116] @ (8002a2c ) 80029b8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80029bc: 6013 str r3, [r2, #0] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 80029be: 4a1b ldr r2, [pc, #108] @ (8002a2c ) 80029c0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80029c4: 6053 str r3, [r2, #4] osMutexRelease (sensorsInfoMutex); 80029c6: 4b18 ldr r3, [pc, #96] @ (8002a28 ) 80029c8: 681b ldr r3, [r3, #0] 80029ca: 4618 mov r0, r3 80029cc: f011 f8ce bl 8013b6c } ++circBuffPos; 80029d0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80029d4: 3301 adds r3, #1 80029d6: f8c7 30ec str.w r3, [r7, #236] @ 0xec circBuffPos = circBuffPos % CIRC_BUFF_LEN; 80029da: f8d7 20ec ldr.w r2, [r7, #236] @ 0xec 80029de: 4b14 ldr r3, [pc, #80] @ (8002a30 ) 80029e0: fba3 1302 umull r1, r3, r3, r2 80029e4: 08d9 lsrs r1, r3, #3 80029e6: 460b mov r3, r1 80029e8: 009b lsls r3, r3, #2 80029ea: 440b add r3, r1 80029ec: 005b lsls r3, r3, #1 80029ee: 1ad3 subs r3, r2, r3 80029f0: f8c7 30ec str.w r3, [r7, #236] @ 0xec while (pdTRUE) { 80029f4: e68a b.n 800270c 80029f6: bf00 nop 80029f8: 00000000 .word 0x00000000 80029fc: 40efffe0 .word 0x40efffe0 8002a00: 3ad18d26 .word 0x3ad18d26 8002a04: 4020aaaa .word 0x4020aaaa 8002a08: aaa38226 .word 0xaaa38226 8002a0c: 4046aaaa .word 0x4046aaaa 8002a10: 00000000 .word 0x00000000 8002a14: 404f8000 .word 0x404f8000 8002a18: 240007d0 .word 0x240007d0 8002a1c: 1ff1e860 .word 0x1ff1e860 8002a20: 240007e0 .word 0x240007e0 8002a24: 24000030 .word 0x24000030 8002a28: 240007e8 .word 0x240007e8 8002a2c: 2400082c .word 0x2400082c 8002a30: cccccccd .word 0xcccccccd 08002a34 : } } void LimiterSwitchTask (void* arg) { 8002a34: b580 push {r7, lr} 8002a36: b08a sub sp, #40 @ 0x28 8002a38: af06 add r7, sp, #24 8002a3a: 6078 str r0, [r7, #4] LimiterSwitchData limiterSwitchData = { 0 }; 8002a3c: 2300 movs r3, #0 8002a3e: 60bb str r3, [r7, #8] limiterSwitchData.gpioPin = GPIO_PIN_8; 8002a40: f44f 7380 mov.w r3, #256 @ 0x100 8002a44: 813b strh r3, [r7, #8] for (uint8_t i = 0; i < 6; i++) { 8002a46: 2300 movs r3, #0 8002a48: 73fb strb r3, [r7, #15] 8002a4a: e015 b.n 8002a78 limiterSwitchData.pinState = HAL_GPIO_ReadPin (GPIOD, limiterSwitchData.gpioPin); 8002a4c: 893b ldrh r3, [r7, #8] 8002a4e: 4619 mov r1, r3 8002a50: 486c ldr r0, [pc, #432] @ (8002c04 ) 8002a52: f008 f84b bl 800aaec 8002a56: 4603 mov r3, r0 8002a58: 72bb strb r3, [r7, #10] osMessageQueuePut (limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8002a5a: 4b6b ldr r3, [pc, #428] @ (8002c08 ) 8002a5c: 6818 ldr r0, [r3, #0] 8002a5e: f107 0108 add.w r1, r7, #8 8002a62: 2300 movs r3, #0 8002a64: 2200 movs r2, #0 8002a66: f011 f931 bl 8013ccc limiterSwitchData.gpioPin = limiterSwitchData.gpioPin << 1; 8002a6a: 893b ldrh r3, [r7, #8] 8002a6c: 005b lsls r3, r3, #1 8002a6e: b29b uxth r3, r3 8002a70: 813b strh r3, [r7, #8] for (uint8_t i = 0; i < 6; i++) { 8002a72: 7bfb ldrb r3, [r7, #15] 8002a74: 3301 adds r3, #1 8002a76: 73fb strb r3, [r7, #15] 8002a78: 7bfb ldrb r3, [r7, #15] 8002a7a: 2b05 cmp r3, #5 8002a7c: d9e6 bls.n 8002a4c } while (pdTRUE) { osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002a7e: 4b62 ldr r3, [pc, #392] @ (8002c08 ) 8002a80: 6818 ldr r0, [r3, #0] 8002a82: f107 0108 add.w r1, r7, #8 8002a86: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002a8a: 2200 movs r2, #0 8002a8c: f011 f97e bl 8013d8c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002a90: 4b5e ldr r3, [pc, #376] @ (8002c0c ) 8002a92: 681b ldr r3, [r3, #0] 8002a94: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002a98: 4618 mov r0, r3 8002a9a: f011 f81c bl 8013ad6 8002a9e: 4603 mov r3, r0 8002aa0: 2b00 cmp r3, #0 8002aa2: d1ec bne.n 8002a7e switch (limiterSwitchData.gpioPin) { 8002aa4: 893b ldrh r3, [r7, #8] 8002aa6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002aaa: d052 beq.n 8002b52 8002aac: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002ab0: dc5a bgt.n 8002b68 8002ab2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002ab6: d041 beq.n 8002b3c 8002ab8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002abc: dc54 bgt.n 8002b68 8002abe: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002ac2: d030 beq.n 8002b26 8002ac4: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002ac8: dc4e bgt.n 8002b68 8002aca: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002ace: d01f beq.n 8002b10 8002ad0: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002ad4: dc48 bgt.n 8002b68 8002ad6: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002ada: d003 beq.n 8002ae4 8002adc: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002ae0: d00b beq.n 8002afa case GPIO_PIN_9: sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; case GPIO_PIN_10: sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; case GPIO_PIN_11: sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; case GPIO_PIN_12: sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; case GPIO_PIN_13: sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; default: break; 8002ae2: e041 b.n 8002b68 case GPIO_PIN_8: sensorsInfo.limitYSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; 8002ae4: 7abb ldrb r3, [r7, #10] 8002ae6: 2b01 cmp r3, #1 8002ae8: bf14 ite ne 8002aea: 2301 movne r3, #1 8002aec: 2300 moveq r3, #0 8002aee: b2db uxtb r3, r3 8002af0: 461a mov r2, r3 8002af2: 4b47 ldr r3, [pc, #284] @ (8002c10 ) 8002af4: f883 202d strb.w r2, [r3, #45] @ 0x2d 8002af8: e037 b.n 8002b6a case GPIO_PIN_9: sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; 8002afa: 7abb ldrb r3, [r7, #10] 8002afc: 2b01 cmp r3, #1 8002afe: bf14 ite ne 8002b00: 2301 movne r3, #1 8002b02: 2300 moveq r3, #0 8002b04: b2db uxtb r3, r3 8002b06: 461a mov r2, r3 8002b08: 4b41 ldr r3, [pc, #260] @ (8002c10 ) 8002b0a: f883 202c strb.w r2, [r3, #44] @ 0x2c 8002b0e: e02c b.n 8002b6a case GPIO_PIN_10: sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; 8002b10: 7abb ldrb r3, [r7, #10] 8002b12: 2b01 cmp r3, #1 8002b14: bf14 ite ne 8002b16: 2301 movne r3, #1 8002b18: 2300 moveq r3, #0 8002b1a: b2db uxtb r3, r3 8002b1c: 461a mov r2, r3 8002b1e: 4b3c ldr r3, [pc, #240] @ (8002c10 ) 8002b20: f883 202a strb.w r2, [r3, #42] @ 0x2a 8002b24: e021 b.n 8002b6a case GPIO_PIN_11: sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; 8002b26: 7abb ldrb r3, [r7, #10] 8002b28: 2b01 cmp r3, #1 8002b2a: bf14 ite ne 8002b2c: 2301 movne r3, #1 8002b2e: 2300 moveq r3, #0 8002b30: b2db uxtb r3, r3 8002b32: 461a mov r2, r3 8002b34: 4b36 ldr r3, [pc, #216] @ (8002c10 ) 8002b36: f883 202b strb.w r2, [r3, #43] @ 0x2b 8002b3a: e016 b.n 8002b6a case GPIO_PIN_12: sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; 8002b3c: 7abb ldrb r3, [r7, #10] 8002b3e: 2b01 cmp r3, #1 8002b40: bf14 ite ne 8002b42: 2301 movne r3, #1 8002b44: 2300 moveq r3, #0 8002b46: b2db uxtb r3, r3 8002b48: 461a mov r2, r3 8002b4a: 4b31 ldr r3, [pc, #196] @ (8002c10 ) 8002b4c: f883 2028 strb.w r2, [r3, #40] @ 0x28 8002b50: e00b b.n 8002b6a case GPIO_PIN_13: sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 0 : 1; break; 8002b52: 7abb ldrb r3, [r7, #10] 8002b54: 2b01 cmp r3, #1 8002b56: bf14 ite ne 8002b58: 2301 movne r3, #1 8002b5a: 2300 moveq r3, #0 8002b5c: b2db uxtb r3, r3 8002b5e: 461a mov r2, r3 8002b60: 4b2b ldr r3, [pc, #172] @ (8002c10 ) 8002b62: f883 2029 strb.w r2, [r3, #41] @ 0x29 8002b66: e000 b.n 8002b6a default: break; 8002b68: bf00 nop } if ((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) { 8002b6a: 4b29 ldr r3, [pc, #164] @ (8002c10 ) 8002b6c: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002b70: 2b01 cmp r3, #1 8002b72: d004 beq.n 8002b7e 8002b74: 4b26 ldr r3, [pc, #152] @ (8002c10 ) 8002b76: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002b7a: 2b01 cmp r3, #1 8002b7c: d118 bne.n 8002bb0 sensorsInfo.motorXStatus = motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8002b7e: 4b25 ldr r3, [pc, #148] @ (8002c14 ) 8002b80: 681b ldr r3, [r3, #0] 8002b82: 4a23 ldr r2, [pc, #140] @ (8002c10 ) 8002b84: f892 2028 ldrb.w r2, [r2, #40] @ 0x28 8002b88: 4921 ldr r1, [pc, #132] @ (8002c10 ) 8002b8a: f891 1029 ldrb.w r1, [r1, #41] @ 0x29 8002b8e: 9104 str r1, [sp, #16] 8002b90: 9203 str r2, [sp, #12] 8002b92: 2200 movs r2, #0 8002b94: 9202 str r2, [sp, #8] 8002b96: 2200 movs r2, #0 8002b98: 9201 str r2, [sp, #4] 8002b9a: 9300 str r3, [sp, #0] 8002b9c: 2304 movs r3, #4 8002b9e: 2200 movs r2, #0 8002ba0: 491d ldr r1, [pc, #116] @ (8002c18 ) 8002ba2: 481e ldr r0, [pc, #120] @ (8002c1c ) 8002ba4: f000 f92a bl 8002dfc 8002ba8: 4603 mov r3, r0 8002baa: 461a mov r2, r3 8002bac: 4b18 ldr r3, [pc, #96] @ (8002c10 ) 8002bae: 751a strb r2, [r3, #20] } if ((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) { 8002bb0: 4b17 ldr r3, [pc, #92] @ (8002c10 ) 8002bb2: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002bb6: 2b01 cmp r3, #1 8002bb8: d004 beq.n 8002bc4 8002bba: 4b15 ldr r3, [pc, #84] @ (8002c10 ) 8002bbc: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002bc0: 2b01 cmp r3, #1 8002bc2: d118 bne.n 8002bf6 sensorsInfo.motorYStatus = motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8002bc4: 4b16 ldr r3, [pc, #88] @ (8002c20 ) 8002bc6: 681b ldr r3, [r3, #0] 8002bc8: 4a11 ldr r2, [pc, #68] @ (8002c10 ) 8002bca: f892 202b ldrb.w r2, [r2, #43] @ 0x2b 8002bce: 4910 ldr r1, [pc, #64] @ (8002c10 ) 8002bd0: f891 102c ldrb.w r1, [r1, #44] @ 0x2c 8002bd4: 9104 str r1, [sp, #16] 8002bd6: 9203 str r2, [sp, #12] 8002bd8: 2200 movs r2, #0 8002bda: 9202 str r2, [sp, #8] 8002bdc: 2200 movs r2, #0 8002bde: 9201 str r2, [sp, #4] 8002be0: 9300 str r3, [sp, #0] 8002be2: 230c movs r3, #12 8002be4: 2208 movs r2, #8 8002be6: 490c ldr r1, [pc, #48] @ (8002c18 ) 8002be8: 480c ldr r0, [pc, #48] @ (8002c1c ) 8002bea: f000 f907 bl 8002dfc 8002bee: 4603 mov r3, r0 8002bf0: 461a mov r2, r3 8002bf2: 4b07 ldr r3, [pc, #28] @ (8002c10 ) 8002bf4: 755a strb r2, [r3, #21] } osMutexRelease (sensorsInfoMutex); 8002bf6: 4b05 ldr r3, [pc, #20] @ (8002c0c ) 8002bf8: 681b ldr r3, [r3, #0] 8002bfa: 4618 mov r0, r3 8002bfc: f010 ffb6 bl 8013b6c osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002c00: e73d b.n 8002a7e 8002c02: bf00 nop 8002c04: 58020c00 .word 0x58020c00 8002c08: 240007d4 .word 0x240007d4 8002c0c: 240007e8 .word 0x240007e8 8002c10: 2400082c .word 0x2400082c 8002c14: 24000708 .word 0x24000708 8002c18: 24000784 .word 0x24000784 8002c1c: 240004e4 .word 0x240004e4 8002c20: 24000738 .word 0x24000738 08002c24 : } } } void EncoderTask (void* arg) { 8002c24: b580 push {r7, lr} 8002c26: b084 sub sp, #16 8002c28: af00 add r7, sp, #0 8002c2a: 6078 str r0, [r7, #4] EncoderData encoderData = { 0 }; 8002c2c: 2300 movs r3, #0 8002c2e: 813b strh r3, [r7, #8] osMessageQueueId_t encoderQueue = (osMessageQueueId_t)arg; 8002c30: 687b ldr r3, [r7, #4] 8002c32: 60fb str r3, [r7, #12] while (pdTRUE) { osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002c34: f107 0108 add.w r1, r7, #8 8002c38: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002c3c: 2200 movs r2, #0 8002c3e: 68f8 ldr r0, [r7, #12] 8002c40: f011 f8a4 bl 8013d8c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002c44: 4b24 ldr r3, [pc, #144] @ (8002cd8 ) 8002c46: 681b ldr r3, [r3, #0] 8002c48: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002c4c: 4618 mov r0, r3 8002c4e: f010 ff42 bl 8013ad6 8002c52: 4603 mov r3, r0 8002c54: 2b00 cmp r3, #0 8002c56: d1ed bne.n 8002c34 if (encoderData.axe == encoderAxeX) { 8002c58: 7a3b ldrb r3, [r7, #8] 8002c5a: 2b00 cmp r3, #0 8002c5c: d11b bne.n 8002c96 if (encoderData.direction == encoderCW) { 8002c5e: 7a7b ldrb r3, [r7, #9] 8002c60: 2b00 cmp r3, #0 8002c62: d10a bne.n 8002c7a sensorsInfo.pvEncoderX += 360.0 / ENCODER_X_IMP_PER_TURN; 8002c64: 4b1d ldr r3, [pc, #116] @ (8002cdc ) 8002c66: edd3 7a03 vldr s15, [r3, #12] 8002c6a: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002c6e: ee77 7a87 vadd.f32 s15, s15, s14 8002c72: 4b1a ldr r3, [pc, #104] @ (8002cdc ) 8002c74: edc3 7a03 vstr s15, [r3, #12] 8002c78: e009 b.n 8002c8e } else { sensorsInfo.pvEncoderX -= 360.0 / ENCODER_X_IMP_PER_TURN; 8002c7a: 4b18 ldr r3, [pc, #96] @ (8002cdc ) 8002c7c: edd3 7a03 vldr s15, [r3, #12] 8002c80: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002c84: ee77 7ac7 vsub.f32 s15, s15, s14 8002c88: 4b14 ldr r3, [pc, #80] @ (8002cdc ) 8002c8a: edc3 7a03 vstr s15, [r3, #12] } DbgLEDToggle(DBG_LED2); 8002c8e: 2020 movs r0, #32 8002c90: f000 f84a bl 8002d28 8002c94: e01a b.n 8002ccc } else { if (encoderData.direction == encoderCW) { 8002c96: 7a7b ldrb r3, [r7, #9] 8002c98: 2b00 cmp r3, #0 8002c9a: d10a bne.n 8002cb2 sensorsInfo.pvEncoderY += 360.0 / ENCODER_Y_IMP_PER_TURN; 8002c9c: 4b0f ldr r3, [pc, #60] @ (8002cdc ) 8002c9e: edd3 7a04 vldr s15, [r3, #16] 8002ca2: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002ca6: ee77 7a87 vadd.f32 s15, s15, s14 8002caa: 4b0c ldr r3, [pc, #48] @ (8002cdc ) 8002cac: edc3 7a04 vstr s15, [r3, #16] 8002cb0: e009 b.n 8002cc6 } else { sensorsInfo.pvEncoderY -= 360.0 / ENCODER_Y_IMP_PER_TURN; 8002cb2: 4b0a ldr r3, [pc, #40] @ (8002cdc ) 8002cb4: edd3 7a04 vldr s15, [r3, #16] 8002cb8: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002cbc: ee77 7ac7 vsub.f32 s15, s15, s14 8002cc0: 4b06 ldr r3, [pc, #24] @ (8002cdc ) 8002cc2: edc3 7a04 vstr s15, [r3, #16] } DbgLEDToggle(DBG_LED3); 8002cc6: 2040 movs r0, #64 @ 0x40 8002cc8: f000 f82e bl 8002d28 } osMutexRelease (sensorsInfoMutex); 8002ccc: 4b02 ldr r3, [pc, #8] @ (8002cd8 ) 8002cce: 681b ldr r3, [r3, #0] 8002cd0: 4618 mov r0, r3 8002cd2: f010 ff4b bl 8013b6c osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002cd6: e7ad b.n 8002c34 8002cd8: 240007e8 .word 0x240007e8 8002cdc: 2400082c .word 0x2400082c 08002ce0 : #include #include "peripherial.h" void DbgLEDOn (uint8_t ledNumber) { 8002ce0: b580 push {r7, lr} 8002ce2: b082 sub sp, #8 8002ce4: af00 add r7, sp, #0 8002ce6: 4603 mov r3, r0 8002ce8: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET); 8002cea: 79fb ldrb r3, [r7, #7] 8002cec: b29b uxth r3, r3 8002cee: 2201 movs r2, #1 8002cf0: 4619 mov r1, r3 8002cf2: 4803 ldr r0, [pc, #12] @ (8002d00 ) 8002cf4: f007 ff12 bl 800ab1c } 8002cf8: bf00 nop 8002cfa: 3708 adds r7, #8 8002cfc: 46bd mov sp, r7 8002cfe: bd80 pop {r7, pc} 8002d00: 58020c00 .word 0x58020c00 08002d04 : void DbgLEDOff (uint8_t ledNumber) { 8002d04: b580 push {r7, lr} 8002d06: b082 sub sp, #8 8002d08: af00 add r7, sp, #0 8002d0a: 4603 mov r3, r0 8002d0c: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET); 8002d0e: 79fb ldrb r3, [r7, #7] 8002d10: b29b uxth r3, r3 8002d12: 2200 movs r2, #0 8002d14: 4619 mov r1, r3 8002d16: 4803 ldr r0, [pc, #12] @ (8002d24 ) 8002d18: f007 ff00 bl 800ab1c } 8002d1c: bf00 nop 8002d1e: 3708 adds r7, #8 8002d20: 46bd mov sp, r7 8002d22: bd80 pop {r7, pc} 8002d24: 58020c00 .word 0x58020c00 08002d28 : void DbgLEDToggle (uint8_t ledNumber) { 8002d28: b580 push {r7, lr} 8002d2a: b082 sub sp, #8 8002d2c: af00 add r7, sp, #0 8002d2e: 4603 mov r3, r0 8002d30: 71fb strb r3, [r7, #7] HAL_GPIO_TogglePin (GPIOD, ledNumber); 8002d32: 79fb ldrb r3, [r7, #7] 8002d34: b29b uxth r3, r3 8002d36: 4619 mov r1, r3 8002d38: 4803 ldr r0, [pc, #12] @ (8002d48 ) 8002d3a: f007 ff08 bl 800ab4e } 8002d3e: bf00 nop 8002d40: 3708 adds r7, #8 8002d42: 46bd mov sp, r7 8002d44: bd80 pop {r7, pc} 8002d46: bf00 nop 8002d48: 58020c00 .word 0x58020c00 08002d4c : void EnableCurrentSensors (void) { 8002d4c: b580 push {r7, lr} 8002d4e: af00 add r7, sp, #0 HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 8002d50: 2201 movs r2, #1 8002d52: f44f 4100 mov.w r1, #32768 @ 0x8000 8002d56: 4802 ldr r0, [pc, #8] @ (8002d60 ) 8002d58: f007 fee0 bl 800ab1c } 8002d5c: bf00 nop 8002d5e: bd80 pop {r7, pc} 8002d60: 58021000 .word 0x58021000 08002d64 : void DisableCurrentSensors (void) { HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { 8002d64: b580 push {r7, lr} 8002d66: b084 sub sp, #16 8002d68: af00 add r7, sp, #0 8002d6a: 4603 mov r3, r0 8002d6c: 460a mov r2, r1 8002d6e: 71fb strb r3, [r7, #7] 8002d70: 4613 mov r3, r2 8002d72: 71bb strb r3, [r7, #6] uint8_t gpioOffset = 0; 8002d74: 2300 movs r3, #0 8002d76: 73fb strb r3, [r7, #15] switch (sensor) { 8002d78: 79fb ldrb r3, [r7, #7] 8002d7a: 2b02 cmp r3, #2 8002d7c: d00c beq.n 8002d98 8002d7e: 2b02 cmp r3, #2 8002d80: dc0d bgt.n 8002d9e 8002d82: 2b00 cmp r3, #0 8002d84: d002 beq.n 8002d8c 8002d86: 2b01 cmp r3, #1 8002d88: d003 beq.n 8002d92 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; 8002d8a: e008 b.n 8002d9e case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; 8002d8c: 2307 movs r3, #7 8002d8e: 73fb strb r3, [r7, #15] 8002d90: e006 b.n 8002da0 case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; 8002d92: 2309 movs r3, #9 8002d94: 73fb strb r3, [r7, #15] 8002d96: e003 b.n 8002da0 case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; 8002d98: 230d movs r3, #13 8002d9a: 73fb strb r3, [r7, #15] 8002d9c: e000 b.n 8002da0 default: break; 8002d9e: bf00 nop } if (gpioOffset > 0) { 8002da0: 7bfb ldrb r3, [r7, #15] 8002da2: 2b00 cmp r3, #0 8002da4: d023 beq.n 8002dee uint16_t gain0Gpio = 1 << gpioOffset; 8002da6: 7bfb ldrb r3, [r7, #15] 8002da8: 2201 movs r2, #1 8002daa: fa02 f303 lsl.w r3, r2, r3 8002dae: 81bb strh r3, [r7, #12] uint16_t gain1Gpio = 1 << (gpioOffset + 1); 8002db0: 7bfb ldrb r3, [r7, #15] 8002db2: 3301 adds r3, #1 8002db4: 2201 movs r2, #1 8002db6: fa02 f303 lsl.w r3, r2, r3 8002dba: 817b strh r3, [r7, #10] uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8002dbc: 79bb ldrb r3, [r7, #6] 8002dbe: b29b uxth r3, r3 8002dc0: f003 0301 and.w r3, r3, #1 8002dc4: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 8002dc6: 893b ldrh r3, [r7, #8] 8002dc8: b2da uxtb r2, r3 8002dca: 89bb ldrh r3, [r7, #12] 8002dcc: 4619 mov r1, r3 8002dce: 480a ldr r0, [pc, #40] @ (8002df8 ) 8002dd0: f007 fea4 bl 800ab1c gpioState = (((uint16_t)gain) >> 1) & 0x0001; 8002dd4: 79bb ldrb r3, [r7, #6] 8002dd6: 085b lsrs r3, r3, #1 8002dd8: b2db uxtb r3, r3 8002dda: f003 0301 and.w r3, r3, #1 8002dde: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 8002de0: 893b ldrh r3, [r7, #8] 8002de2: b2da uxtb r2, r3 8002de4: 897b ldrh r3, [r7, #10] 8002de6: 4619 mov r1, r3 8002de8: 4803 ldr r0, [pc, #12] @ (8002df8 ) 8002dea: f007 fe97 bl 800ab1c } } 8002dee: bf00 nop 8002df0: 3710 adds r7, #16 8002df2: 46bd mov sp, r7 8002df4: bd80 pop {r7, pc} 8002df6: bf00 nop 8002df8: 58021000 .word 0x58021000 08002dfc : uint8_t motorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8002dfc: b580 push {r7, lr} 8002dfe: b088 sub sp, #32 8002e00: af02 add r7, sp, #8 8002e02: 60f8 str r0, [r7, #12] 8002e04: 60b9 str r1, [r7, #8] 8002e06: 4611 mov r1, r2 8002e08: 461a mov r2, r3 8002e0a: 460b mov r3, r1 8002e0c: 71fb strb r3, [r7, #7] 8002e0e: 4613 mov r3, r2 8002e10: 71bb strb r3, [r7, #6] uint32_t motorStatus = 0; 8002e12: 2300 movs r3, #0 8002e14: 617b str r3, [r7, #20] MotorDriverState setMotorYState = HiZ; 8002e16: 2300 movs r3, #0 8002e18: 74fb strb r3, [r7, #19] HAL_TIM_PWM_Stop (htim, channel1); 8002e1a: 79fb ldrb r3, [r7, #7] 8002e1c: 4619 mov r1, r3 8002e1e: 68f8 ldr r0, [r7, #12] 8002e20: f00c f826 bl 800ee70 HAL_TIM_PWM_Stop (htim, channel2); 8002e24: 79bb ldrb r3, [r7, #6] 8002e26: 4619 mov r1, r3 8002e28: 68f8 ldr r0, [r7, #12] 8002e2a: f00c f821 bl 800ee70 if (motorTimerPeriod > 0) { 8002e2e: 6abb ldr r3, [r7, #40] @ 0x28 8002e30: 2b00 cmp r3, #0 8002e32: f340 808c ble.w 8002f4e if (motorPWMPulse > 0) { 8002e36: 6a7b ldr r3, [r7, #36] @ 0x24 8002e38: 2b00 cmp r3, #0 8002e3a: dd2c ble.n 8002e96 // Forward if (switchLimiterUpStat == 0) { 8002e3c: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8002e40: 2b00 cmp r3, #0 8002e42: d11d bne.n 8002e80 setMotorYState = Forward; 8002e44: 2301 movs r3, #1 8002e46: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8002e48: 79f9 ldrb r1, [r7, #7] 8002e4a: 79b8 ldrb r0, [r7, #6] 8002e4c: 6a7b ldr r3, [r7, #36] @ 0x24 8002e4e: ea83 72e3 eor.w r2, r3, r3, asr #31 8002e52: eba2 72e3 sub.w r2, r2, r3, asr #31 8002e56: 4613 mov r3, r2 8002e58: 009b lsls r3, r3, #2 8002e5a: 4413 add r3, r2 8002e5c: 005b lsls r3, r3, #1 8002e5e: 9301 str r3, [sp, #4] 8002e60: 7cfb ldrb r3, [r7, #19] 8002e62: 9300 str r3, [sp, #0] 8002e64: 4603 mov r3, r0 8002e66: 460a mov r2, r1 8002e68: 68b9 ldr r1, [r7, #8] 8002e6a: 68f8 ldr r0, [r7, #12] 8002e6c: f000 f8ff bl 800306e HAL_TIM_PWM_Start (htim, channel1); 8002e70: 79fb ldrb r3, [r7, #7] 8002e72: 4619 mov r1, r3 8002e74: 68f8 ldr r0, [r7, #12] 8002e76: f00b feed bl 800ec54 motorStatus = 1; 8002e7a: 2301 movs r3, #1 8002e7c: 617b str r3, [r7, #20] 8002e7e: e004 b.n 8002e8a } else { HAL_TIM_PWM_Stop (htim, channel1); 8002e80: 79fb ldrb r3, [r7, #7] 8002e82: 4619 mov r1, r3 8002e84: 68f8 ldr r0, [r7, #12] 8002e86: f00b fff3 bl 800ee70 } HAL_TIM_PWM_Stop (htim, channel2); 8002e8a: 79bb ldrb r3, [r7, #6] 8002e8c: 4619 mov r1, r3 8002e8e: 68f8 ldr r0, [r7, #12] 8002e90: f00b ffee bl 800ee70 8002e94: e051 b.n 8002f3a } else if (motorPWMPulse < 0) { 8002e96: 6a7b ldr r3, [r7, #36] @ 0x24 8002e98: 2b00 cmp r3, #0 8002e9a: da2c bge.n 8002ef6 // Reverse if (switchLimiterDownStat == 0) { 8002e9c: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8002ea0: 2b00 cmp r3, #0 8002ea2: d11d bne.n 8002ee0 setMotorYState = Reverse; 8002ea4: 2302 movs r3, #2 8002ea6: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8002ea8: 79f9 ldrb r1, [r7, #7] 8002eaa: 79b8 ldrb r0, [r7, #6] 8002eac: 6a7b ldr r3, [r7, #36] @ 0x24 8002eae: ea83 72e3 eor.w r2, r3, r3, asr #31 8002eb2: eba2 72e3 sub.w r2, r2, r3, asr #31 8002eb6: 4613 mov r3, r2 8002eb8: 009b lsls r3, r3, #2 8002eba: 4413 add r3, r2 8002ebc: 005b lsls r3, r3, #1 8002ebe: 9301 str r3, [sp, #4] 8002ec0: 7cfb ldrb r3, [r7, #19] 8002ec2: 9300 str r3, [sp, #0] 8002ec4: 4603 mov r3, r0 8002ec6: 460a mov r2, r1 8002ec8: 68b9 ldr r1, [r7, #8] 8002eca: 68f8 ldr r0, [r7, #12] 8002ecc: f000 f8cf bl 800306e HAL_TIM_PWM_Start (htim, channel2); 8002ed0: 79bb ldrb r3, [r7, #6] 8002ed2: 4619 mov r1, r3 8002ed4: 68f8 ldr r0, [r7, #12] 8002ed6: f00b febd bl 800ec54 motorStatus = 1; 8002eda: 2301 movs r3, #1 8002edc: 617b str r3, [r7, #20] 8002ede: e004 b.n 8002eea } else { HAL_TIM_PWM_Stop (htim, channel2); 8002ee0: 79bb ldrb r3, [r7, #6] 8002ee2: 4619 mov r1, r3 8002ee4: 68f8 ldr r0, [r7, #12] 8002ee6: f00b ffc3 bl 800ee70 } HAL_TIM_PWM_Stop (htim, channel1); 8002eea: 79fb ldrb r3, [r7, #7] 8002eec: 4619 mov r1, r3 8002eee: 68f8 ldr r0, [r7, #12] 8002ef0: f00b ffbe bl 800ee70 8002ef4: e021 b.n 8002f3a } else { // Brake setMotorYState = Brake; 8002ef6: 2303 movs r3, #3 8002ef8: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8002efa: 79f9 ldrb r1, [r7, #7] 8002efc: 79b8 ldrb r0, [r7, #6] 8002efe: 6a7b ldr r3, [r7, #36] @ 0x24 8002f00: ea83 72e3 eor.w r2, r3, r3, asr #31 8002f04: eba2 72e3 sub.w r2, r2, r3, asr #31 8002f08: 4613 mov r3, r2 8002f0a: 009b lsls r3, r3, #2 8002f0c: 4413 add r3, r2 8002f0e: 005b lsls r3, r3, #1 8002f10: 9301 str r3, [sp, #4] 8002f12: 7cfb ldrb r3, [r7, #19] 8002f14: 9300 str r3, [sp, #0] 8002f16: 4603 mov r3, r0 8002f18: 460a mov r2, r1 8002f1a: 68b9 ldr r1, [r7, #8] 8002f1c: 68f8 ldr r0, [r7, #12] 8002f1e: f000 f8a6 bl 800306e HAL_TIM_PWM_Start (htim, channel1); 8002f22: 79fb ldrb r3, [r7, #7] 8002f24: 4619 mov r1, r3 8002f26: 68f8 ldr r0, [r7, #12] 8002f28: f00b fe94 bl 800ec54 HAL_TIM_PWM_Start (htim, channel2); 8002f2c: 79bb ldrb r3, [r7, #6] 8002f2e: 4619 mov r1, r3 8002f30: 68f8 ldr r0, [r7, #12] 8002f32: f00b fe8f bl 800ec54 motorStatus = 0; 8002f36: 2300 movs r3, #0 8002f38: 617b str r3, [r7, #20] } osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 8002f3a: 6abb ldr r3, [r7, #40] @ 0x28 8002f3c: f44f 727a mov.w r2, #1000 @ 0x3e8 8002f40: fb02 f303 mul.w r3, r2, r3 8002f44: 4619 mov r1, r3 8002f46: 6a38 ldr r0, [r7, #32] 8002f48: f010 fcda bl 8013900 8002f4c: e089 b.n 8003062 } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 8002f4e: 6abb ldr r3, [r7, #40] @ 0x28 8002f50: 2b00 cmp r3, #0 8002f52: d126 bne.n 8002fa2 8002f54: 6a7b ldr r3, [r7, #36] @ 0x24 8002f56: 2b00 cmp r3, #0 8002f58: d123 bne.n 8002fa2 motorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10); 8002f5a: 79f9 ldrb r1, [r7, #7] 8002f5c: 79b8 ldrb r0, [r7, #6] 8002f5e: 6a7b ldr r3, [r7, #36] @ 0x24 8002f60: ea83 72e3 eor.w r2, r3, r3, asr #31 8002f64: eba2 72e3 sub.w r2, r2, r3, asr #31 8002f68: 4613 mov r3, r2 8002f6a: 009b lsls r3, r3, #2 8002f6c: 4413 add r3, r2 8002f6e: 005b lsls r3, r3, #1 8002f70: 9301 str r3, [sp, #4] 8002f72: 2300 movs r3, #0 8002f74: 9300 str r3, [sp, #0] 8002f76: 4603 mov r3, r0 8002f78: 460a mov r2, r1 8002f7a: 68b9 ldr r1, [r7, #8] 8002f7c: 68f8 ldr r0, [r7, #12] 8002f7e: f000 f876 bl 800306e HAL_TIM_PWM_Stop (htim, channel1); 8002f82: 79fb ldrb r3, [r7, #7] 8002f84: 4619 mov r1, r3 8002f86: 68f8 ldr r0, [r7, #12] 8002f88: f00b ff72 bl 800ee70 HAL_TIM_PWM_Stop (htim, channel2); 8002f8c: 79bb ldrb r3, [r7, #6] 8002f8e: 4619 mov r1, r3 8002f90: 68f8 ldr r0, [r7, #12] 8002f92: f00b ff6d bl 800ee70 osTimerStop (motorTimerHandle); 8002f96: 6a38 ldr r0, [r7, #32] 8002f98: f010 fce0 bl 801395c motorStatus = 0; 8002f9c: 2300 movs r3, #0 8002f9e: 617b str r3, [r7, #20] 8002fa0: e05f b.n 8003062 } else if (motorTimerPeriod == -1) { 8002fa2: 6abb ldr r3, [r7, #40] @ 0x28 8002fa4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8002fa8: d15b bne.n 8003062 if (motorPWMPulse > 0) { 8002faa: 6a7b ldr r3, [r7, #36] @ 0x24 8002fac: 2b00 cmp r3, #0 8002fae: dd2c ble.n 800300a // Forward if (switchLimiterUpStat == 0) { 8002fb0: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8002fb4: 2b00 cmp r3, #0 8002fb6: d11d bne.n 8002ff4 setMotorYState = Forward; 8002fb8: 2301 movs r3, #1 8002fba: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8002fbc: 79f9 ldrb r1, [r7, #7] 8002fbe: 79b8 ldrb r0, [r7, #6] 8002fc0: 6a7b ldr r3, [r7, #36] @ 0x24 8002fc2: ea83 72e3 eor.w r2, r3, r3, asr #31 8002fc6: eba2 72e3 sub.w r2, r2, r3, asr #31 8002fca: 4613 mov r3, r2 8002fcc: 009b lsls r3, r3, #2 8002fce: 4413 add r3, r2 8002fd0: 005b lsls r3, r3, #1 8002fd2: 9301 str r3, [sp, #4] 8002fd4: 7cfb ldrb r3, [r7, #19] 8002fd6: 9300 str r3, [sp, #0] 8002fd8: 4603 mov r3, r0 8002fda: 460a mov r2, r1 8002fdc: 68b9 ldr r1, [r7, #8] 8002fde: 68f8 ldr r0, [r7, #12] 8002fe0: f000 f845 bl 800306e HAL_TIM_PWM_Start (htim, channel1); 8002fe4: 79fb ldrb r3, [r7, #7] 8002fe6: 4619 mov r1, r3 8002fe8: 68f8 ldr r0, [r7, #12] 8002fea: f00b fe33 bl 800ec54 motorStatus = 1; 8002fee: 2301 movs r3, #1 8002ff0: 617b str r3, [r7, #20] 8002ff2: e004 b.n 8002ffe } else { HAL_TIM_PWM_Stop (htim, channel1); 8002ff4: 79fb ldrb r3, [r7, #7] 8002ff6: 4619 mov r1, r3 8002ff8: 68f8 ldr r0, [r7, #12] 8002ffa: f00b ff39 bl 800ee70 } HAL_TIM_PWM_Stop (htim, channel2); 8002ffe: 79bb ldrb r3, [r7, #6] 8003000: 4619 mov r1, r3 8003002: 68f8 ldr r0, [r7, #12] 8003004: f00b ff34 bl 800ee70 8003008: e02b b.n 8003062 } else { // Reverse if (switchLimiterDownStat == 0) { 800300a: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 800300e: 2b00 cmp r3, #0 8003010: d11d bne.n 800304e setMotorYState = Reverse; 8003012: 2302 movs r3, #2 8003014: 74fb strb r3, [r7, #19] motorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorYState, abs (motorPWMPulse) * 10); 8003016: 79f9 ldrb r1, [r7, #7] 8003018: 79b8 ldrb r0, [r7, #6] 800301a: 6a7b ldr r3, [r7, #36] @ 0x24 800301c: ea83 72e3 eor.w r2, r3, r3, asr #31 8003020: eba2 72e3 sub.w r2, r2, r3, asr #31 8003024: 4613 mov r3, r2 8003026: 009b lsls r3, r3, #2 8003028: 4413 add r3, r2 800302a: 005b lsls r3, r3, #1 800302c: 9301 str r3, [sp, #4] 800302e: 7cfb ldrb r3, [r7, #19] 8003030: 9300 str r3, [sp, #0] 8003032: 4603 mov r3, r0 8003034: 460a mov r2, r1 8003036: 68b9 ldr r1, [r7, #8] 8003038: 68f8 ldr r0, [r7, #12] 800303a: f000 f818 bl 800306e HAL_TIM_PWM_Start (htim, channel2); 800303e: 79bb ldrb r3, [r7, #6] 8003040: 4619 mov r1, r3 8003042: 68f8 ldr r0, [r7, #12] 8003044: f00b fe06 bl 800ec54 motorStatus = 1; 8003048: 2301 movs r3, #1 800304a: 617b str r3, [r7, #20] 800304c: e004 b.n 8003058 } else { HAL_TIM_PWM_Stop (htim, channel2); 800304e: 79bb ldrb r3, [r7, #6] 8003050: 4619 mov r1, r3 8003052: 68f8 ldr r0, [r7, #12] 8003054: f00b ff0c bl 800ee70 } HAL_TIM_PWM_Stop (htim, channel1); 8003058: 79fb ldrb r3, [r7, #7] 800305a: 4619 mov r1, r3 800305c: 68f8 ldr r0, [r7, #12] 800305e: f00b ff07 bl 800ee70 } } return motorStatus; 8003062: 697b ldr r3, [r7, #20] 8003064: b2db uxtb r3, r3 } 8003066: 4618 mov r0, r3 8003068: 3718 adds r7, #24 800306a: 46bd mov sp, r7 800306c: bd80 pop {r7, pc} 0800306e : void motorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 800306e: b580 push {r7, lr} 8003070: b084 sub sp, #16 8003072: af00 add r7, sp, #0 8003074: 60f8 str r0, [r7, #12] 8003076: 60b9 str r1, [r7, #8] 8003078: 607a str r2, [r7, #4] 800307a: 603b str r3, [r7, #0] timerConf->Pulse = pulse; 800307c: 68bb ldr r3, [r7, #8] 800307e: 69fa ldr r2, [r7, #28] 8003080: 605a str r2, [r3, #4] switch (setState) { 8003082: 7e3b ldrb r3, [r7, #24] 8003084: 2b02 cmp r3, #2 8003086: dc02 bgt.n 800308e 8003088: 2b00 cmp r3, #0 800308a: da03 bge.n 8003094 800308c: e038 b.n 8003100 800308e: 2b03 cmp r3, #3 8003090: d01b beq.n 80030ca 8003092: e035 b.n 8003100 case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003094: 68bb ldr r3, [r7, #8] 8003096: 2200 movs r2, #0 8003098: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800309a: 687a ldr r2, [r7, #4] 800309c: 68b9 ldr r1, [r7, #8] 800309e: 68f8 ldr r0, [r7, #12] 80030a0: f00c fad2 bl 800f648 80030a4: 4603 mov r3, r0 80030a6: 2b00 cmp r3, #0 80030a8: d001 beq.n 80030ae Error_Handler (); 80030aa: f7fe feb1 bl 8001e10 } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80030ae: 68bb ldr r3, [r7, #8] 80030b0: 2200 movs r2, #0 80030b2: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80030b4: 683a ldr r2, [r7, #0] 80030b6: 68b9 ldr r1, [r7, #8] 80030b8: 68f8 ldr r0, [r7, #12] 80030ba: f00c fac5 bl 800f648 80030be: 4603 mov r3, r0 80030c0: 2b00 cmp r3, #0 80030c2: d038 beq.n 8003136 Error_Handler (); 80030c4: f7fe fea4 bl 8001e10 } break; 80030c8: e035 b.n 8003136 case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80030ca: 68bb ldr r3, [r7, #8] 80030cc: 2202 movs r2, #2 80030ce: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80030d0: 687a ldr r2, [r7, #4] 80030d2: 68b9 ldr r1, [r7, #8] 80030d4: 68f8 ldr r0, [r7, #12] 80030d6: f00c fab7 bl 800f648 80030da: 4603 mov r3, r0 80030dc: 2b00 cmp r3, #0 80030de: d001 beq.n 80030e4 Error_Handler (); 80030e0: f7fe fe96 bl 8001e10 } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80030e4: 68bb ldr r3, [r7, #8] 80030e6: 2202 movs r2, #2 80030e8: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80030ea: 683a ldr r2, [r7, #0] 80030ec: 68b9 ldr r1, [r7, #8] 80030ee: 68f8 ldr r0, [r7, #12] 80030f0: f00c faaa bl 800f648 80030f4: 4603 mov r3, r0 80030f6: 2b00 cmp r3, #0 80030f8: d01f beq.n 800313a Error_Handler (); 80030fa: f7fe fe89 bl 8001e10 } break; 80030fe: e01c b.n 800313a default: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003100: 68bb ldr r3, [r7, #8] 8003102: 2200 movs r2, #0 8003104: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 8003106: 687a ldr r2, [r7, #4] 8003108: 68b9 ldr r1, [r7, #8] 800310a: 68f8 ldr r0, [r7, #12] 800310c: f00c fa9c bl 800f648 8003110: 4603 mov r3, r0 8003112: 2b00 cmp r3, #0 8003114: d001 beq.n 800311a Error_Handler (); 8003116: f7fe fe7b bl 8001e10 } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800311a: 68bb ldr r3, [r7, #8] 800311c: 2200 movs r2, #0 800311e: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8003120: 683a ldr r2, [r7, #0] 8003122: 68b9 ldr r1, [r7, #8] 8003124: 68f8 ldr r0, [r7, #12] 8003126: f00c fa8f bl 800f648 800312a: 4603 mov r3, r0 800312c: 2b00 cmp r3, #0 800312e: d006 beq.n 800313e Error_Handler (); 8003130: f7fe fe6e bl 8001e10 } break; 8003134: e003 b.n 800313e break; 8003136: bf00 nop 8003138: e002 b.n 8003140 break; 800313a: bf00 nop 800313c: e000 b.n 8003140 break; 800313e: bf00 nop } } 8003140: bf00 nop 8003142: 3710 adds r7, #16 8003144: 46bd mov sp, r7 8003146: bd80 pop {r7, pc} 08003148 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 8003148: b480 push {r7} 800314a: b089 sub sp, #36 @ 0x24 800314c: af00 add r7, sp, #0 800314e: 60f8 str r0, [r7, #12] 8003150: 60b9 str r1, [r7, #8] 8003152: 607a str r2, [r7, #4] 8003154: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 8003156: 687b ldr r3, [r7, #4] 8003158: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 800315a: 69bb ldr r3, [r7, #24] 800315c: 681b ldr r3, [r3, #0] 800315e: 617b str r3, [r7, #20] uint8_t i = 0; 8003160: 2300 movs r3, #0 8003162: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 8003164: 68bb ldr r3, [r7, #8] 8003166: 881b ldrh r3, [r3, #0] 8003168: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 800316a: 2300 movs r3, #0 800316c: 77fb strb r3, [r7, #31] 800316e: e00e b.n 800318e buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 8003170: 7ffb ldrb r3, [r7, #31] 8003172: 00db lsls r3, r3, #3 8003174: 697a ldr r2, [r7, #20] 8003176: 40da lsrs r2, r3 8003178: 7fbb ldrb r3, [r7, #30] 800317a: 1c59 adds r1, r3, #1 800317c: 77b9 strb r1, [r7, #30] 800317e: 4619 mov r1, r3 8003180: 68fb ldr r3, [r7, #12] 8003182: 440b add r3, r1 8003184: b2d2 uxtb r2, r2 8003186: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 8003188: 7ffb ldrb r3, [r7, #31] 800318a: 3301 adds r3, #1 800318c: 77fb strb r3, [r7, #31] 800318e: 7ffa ldrb r2, [r7, #31] 8003190: 78fb ldrb r3, [r7, #3] 8003192: 429a cmp r2, r3 8003194: d3ec bcc.n 8003170 } *buffPos = newBuffPos; 8003196: 7fbb ldrb r3, [r7, #30] 8003198: b29a uxth r2, r3 800319a: 68bb ldr r3, [r7, #8] 800319c: 801a strh r2, [r3, #0] } 800319e: bf00 nop 80031a0: 3724 adds r7, #36 @ 0x24 80031a2: 46bd mov sp, r7 80031a4: f85d 7b04 ldr.w r7, [sp], #4 80031a8: 4770 bx lr 080031aa : *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) { 80031aa: b480 push {r7} 80031ac: b085 sub sp, #20 80031ae: af00 add r7, sp, #0 80031b0: 60f8 str r0, [r7, #12] 80031b2: 60b9 str r1, [r7, #8] 80031b4: 607a str r2, [r7, #4] *data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 80031b6: 68bb ldr r3, [r7, #8] 80031b8: 881b ldrh r3, [r3, #0] 80031ba: 3303 adds r3, #3 80031bc: 68fa ldr r2, [r7, #12] 80031be: 4413 add r3, r2 80031c0: 781b ldrb r3, [r3, #0] 80031c2: 061a lsls r2, r3, #24 80031c4: 68bb ldr r3, [r7, #8] 80031c6: 881b ldrh r3, [r3, #0] 80031c8: 3302 adds r3, #2 80031ca: 68f9 ldr r1, [r7, #12] 80031cc: 440b add r3, r1 80031ce: 781b ldrb r3, [r3, #0] 80031d0: 041b lsls r3, r3, #16 80031d2: 431a orrs r2, r3 80031d4: 68bb ldr r3, [r7, #8] 80031d6: 881b ldrh r3, [r3, #0] 80031d8: 3301 adds r3, #1 80031da: 68f9 ldr r1, [r7, #12] 80031dc: 440b add r3, r1 80031de: 781b ldrb r3, [r3, #0] 80031e0: 021b lsls r3, r3, #8 80031e2: 4313 orrs r3, r2 80031e4: 68ba ldr r2, [r7, #8] 80031e6: 8812 ldrh r2, [r2, #0] 80031e8: 4611 mov r1, r2 80031ea: 68fa ldr r2, [r7, #12] 80031ec: 440a add r2, r1 80031ee: 7812 ldrb r2, [r2, #0] 80031f0: 4313 orrs r3, r2 80031f2: 461a mov r2, r3 80031f4: 687b ldr r3, [r7, #4] 80031f6: 601a str r2, [r3, #0] *buffPos += sizeof(uint32_t); 80031f8: 68bb ldr r3, [r7, #8] 80031fa: 881b ldrh r3, [r3, #0] 80031fc: 3304 adds r3, #4 80031fe: b29a uxth r2, r3 8003200: 68bb ldr r3, [r7, #8] 8003202: 801a strh r2, [r3, #0] } 8003204: bf00 nop 8003206: 3714 adds r7, #20 8003208: 46bd mov sp, r7 800320a: f85d 7b04 ldr.w r7, [sp], #4 800320e: 4770 bx lr 08003210 : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 8003210: b580 push {r7, lr} 8003212: b084 sub sp, #16 8003214: af00 add r7, sp, #0 8003216: 6078 str r0, [r7, #4] 8003218: 4608 mov r0, r1 800321a: 4611 mov r1, r2 800321c: 461a mov r2, r3 800321e: 4603 mov r3, r0 8003220: 807b strh r3, [r7, #2] 8003222: 460b mov r3, r1 8003224: 707b strb r3, [r7, #1] 8003226: 4613 mov r3, r2 8003228: 703b strb r3, [r7, #0] uint16_t crc = 0; 800322a: 2300 movs r3, #0 800322c: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 800322e: 2300 movs r3, #0 8003230: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 8003232: 787b ldrb r3, [r7, #1] 8003234: b21a sxth r2, r3 8003236: 4b43 ldr r3, [pc, #268] @ (8003344 ) 8003238: 4313 orrs r3, r2 800323a: b21b sxth r3, r3 800323c: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 800323e: 8bbb ldrh r3, [r7, #28] 8003240: 461a mov r2, r3 8003242: 2100 movs r1, #0 8003244: 6878 ldr r0, [r7, #4] 8003246: f014 fc86 bl 8017b56 txBuffer[txBufferPos++] = FRAME_INDICATOR; 800324a: 89fb ldrh r3, [r7, #14] 800324c: 1c5a adds r2, r3, #1 800324e: 81fa strh r2, [r7, #14] 8003250: 461a mov r2, r3 8003252: 687b ldr r3, [r7, #4] 8003254: 4413 add r3, r2 8003256: 22aa movs r2, #170 @ 0xaa 8003258: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 800325a: 89fb ldrh r3, [r7, #14] 800325c: 1c5a adds r2, r3, #1 800325e: 81fa strh r2, [r7, #14] 8003260: 461a mov r2, r3 8003262: 687b ldr r3, [r7, #4] 8003264: 4413 add r3, r2 8003266: 887a ldrh r2, [r7, #2] 8003268: b2d2 uxtb r2, r2 800326a: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 800326c: 887b ldrh r3, [r7, #2] 800326e: 0a1b lsrs r3, r3, #8 8003270: b29a uxth r2, r3 8003272: 89fb ldrh r3, [r7, #14] 8003274: 1c59 adds r1, r3, #1 8003276: 81f9 strh r1, [r7, #14] 8003278: 4619 mov r1, r3 800327a: 687b ldr r3, [r7, #4] 800327c: 440b add r3, r1 800327e: b2d2 uxtb r2, r2 8003280: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 8003282: 89fb ldrh r3, [r7, #14] 8003284: 1c5a adds r2, r3, #1 8003286: 81fa strh r2, [r7, #14] 8003288: 461a mov r2, r3 800328a: 687b ldr r3, [r7, #4] 800328c: 4413 add r3, r2 800328e: 897a ldrh r2, [r7, #10] 8003290: b2d2 uxtb r2, r2 8003292: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 8003294: 897b ldrh r3, [r7, #10] 8003296: 0a1b lsrs r3, r3, #8 8003298: b29a uxth r2, r3 800329a: 89fb ldrh r3, [r7, #14] 800329c: 1c59 adds r1, r3, #1 800329e: 81f9 strh r1, [r7, #14] 80032a0: 4619 mov r1, r3 80032a2: 687b ldr r3, [r7, #4] 80032a4: 440b add r3, r1 80032a6: b2d2 uxtb r2, r2 80032a8: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 80032aa: 89fb ldrh r3, [r7, #14] 80032ac: 1c5a adds r2, r3, #1 80032ae: 81fa strh r2, [r7, #14] 80032b0: 461a mov r2, r3 80032b2: 687b ldr r3, [r7, #4] 80032b4: 4413 add r3, r2 80032b6: 8bba ldrh r2, [r7, #28] 80032b8: b2d2 uxtb r2, r2 80032ba: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 80032bc: 8bbb ldrh r3, [r7, #28] 80032be: 0a1b lsrs r3, r3, #8 80032c0: b29a uxth r2, r3 80032c2: 89fb ldrh r3, [r7, #14] 80032c4: 1c59 adds r1, r3, #1 80032c6: 81f9 strh r1, [r7, #14] 80032c8: 4619 mov r1, r3 80032ca: 687b ldr r3, [r7, #4] 80032cc: 440b add r3, r1 80032ce: b2d2 uxtb r2, r2 80032d0: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 80032d2: 89fb ldrh r3, [r7, #14] 80032d4: 1c5a adds r2, r3, #1 80032d6: 81fa strh r2, [r7, #14] 80032d8: 461a mov r2, r3 80032da: 687b ldr r3, [r7, #4] 80032dc: 4413 add r3, r2 80032de: 783a ldrb r2, [r7, #0] 80032e0: 701a strb r2, [r3, #0] if (dataLength > 0) { 80032e2: 8bbb ldrh r3, [r7, #28] 80032e4: 2b00 cmp r3, #0 80032e6: d00b beq.n 8003300 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 80032e8: 89fb ldrh r3, [r7, #14] 80032ea: 687a ldr r2, [r7, #4] 80032ec: 4413 add r3, r2 80032ee: 8bba ldrh r2, [r7, #28] 80032f0: 69b9 ldr r1, [r7, #24] 80032f2: 4618 mov r0, r3 80032f4: f014 fd01 bl 8017cfa txBufferPos += dataLength; 80032f8: 89fa ldrh r2, [r7, #14] 80032fa: 8bbb ldrh r3, [r7, #28] 80032fc: 4413 add r3, r2 80032fe: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 8003300: 89fb ldrh r3, [r7, #14] 8003302: 461a mov r2, r3 8003304: 6879 ldr r1, [r7, #4] 8003306: 4810 ldr r0, [pc, #64] @ (8003348 ) 8003308: f004 f812 bl 8007330 800330c: 4603 mov r3, r0 800330e: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 8003310: 89fb ldrh r3, [r7, #14] 8003312: 1c5a adds r2, r3, #1 8003314: 81fa strh r2, [r7, #14] 8003316: 461a mov r2, r3 8003318: 687b ldr r3, [r7, #4] 800331a: 4413 add r3, r2 800331c: 89ba ldrh r2, [r7, #12] 800331e: b2d2 uxtb r2, r2 8003320: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 8003322: 89bb ldrh r3, [r7, #12] 8003324: 0a1b lsrs r3, r3, #8 8003326: b29a uxth r2, r3 8003328: 89fb ldrh r3, [r7, #14] 800332a: 1c59 adds r1, r3, #1 800332c: 81f9 strh r1, [r7, #14] 800332e: 4619 mov r1, r3 8003330: 687b ldr r3, [r7, #4] 8003332: 440b add r3, r1 8003334: b2d2 uxtb r2, r2 8003336: 701a strb r2, [r3, #0] return txBufferPos; 8003338: 89fb ldrh r3, [r7, #14] } 800333a: 4618 mov r0, r3 800333c: 3710 adds r7, #16 800333e: 46bd mov sp, r7 8003340: bd80 pop {r7, pc} 8003342: bf00 nop 8003344: ffff8000 .word 0xffff8000 8003348: 24000400 .word 0x24000400 0800334c : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 800334c: b580 push {r7, lr} 800334e: b086 sub sp, #24 8003350: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; 8003352: f107 0310 add.w r3, r7, #16 8003356: 2200 movs r2, #0 8003358: 601a str r2, [r3, #0] 800335a: 605a str r2, [r3, #4] PWR_PVDTypeDef sConfigPVD = {0}; 800335c: f107 0308 add.w r3, r7, #8 8003360: 2200 movs r2, #0 8003362: 601a str r2, [r3, #0] 8003364: 605a str r2, [r3, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 8003366: 4b26 ldr r3, [pc, #152] @ (8003400 ) 8003368: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800336c: 4a24 ldr r2, [pc, #144] @ (8003400 ) 800336e: f043 0302 orr.w r3, r3, #2 8003372: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003376: 4b22 ldr r3, [pc, #136] @ (8003400 ) 8003378: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800337c: f003 0302 and.w r3, r3, #2 8003380: 607b str r3, [r7, #4] 8003382: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8003384: 2200 movs r2, #0 8003386: 210f movs r1, #15 8003388: f06f 0001 mvn.w r0, #1 800338c: f003 fecc bl 8007128 /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8003390: 2200 movs r2, #0 8003392: 2105 movs r1, #5 8003394: 2005 movs r0, #5 8003396: f003 fec7 bl 8007128 HAL_NVIC_EnableIRQ(RCC_IRQn); 800339a: 2005 movs r0, #5 800339c: f003 fede bl 800715c /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 80033a0: f44f 23c0 mov.w r3, #393216 @ 0x60000 80033a4: 613b str r3, [r7, #16] sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; 80033a6: 2300 movs r3, #0 80033a8: 617b str r3, [r7, #20] HAL_PWREx_ConfigAVD(&sConfigAVD); 80033aa: f107 0310 add.w r3, r7, #16 80033ae: 4618 mov r0, r3 80033b0: f007 fcc6 bl 800ad40 /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 80033b4: f007 fd3a bl 800ae2c /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 80033b8: 23c0 movs r3, #192 @ 0xc0 80033ba: 60bb str r3, [r7, #8] sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; 80033bc: 2300 movs r3, #0 80033be: 60fb str r3, [r7, #12] HAL_PWR_ConfigPVD(&sConfigPVD); 80033c0: f107 0308 add.w r3, r7, #8 80033c4: 4618 mov r0, r3 80033c6: f007 fbf7 bl 800abb8 /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 80033ca: f007 fc6f bl 800acac /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 80033ce: 4b0c ldr r3, [pc, #48] @ (8003400 ) 80033d0: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80033d4: 4a0a ldr r2, [pc, #40] @ (8003400 ) 80033d6: f443 4300 orr.w r3, r3, #32768 @ 0x8000 80033da: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 80033de: 4b08 ldr r3, [pc, #32] @ (8003400 ) 80033e0: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80033e4: f403 4300 and.w r3, r3, #32768 @ 0x8000 80033e8: 603b str r3, [r7, #0] 80033ea: 683b ldr r3, [r7, #0] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 80033ec: f002 f822 bl 8005434 /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 80033f0: 2002 movs r0, #2 80033f2: f002 f80b bl 800540c /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 80033f6: bf00 nop 80033f8: 3718 adds r7, #24 80033fa: 46bd mov sp, r7 80033fc: bd80 pop {r7, pc} 80033fe: bf00 nop 8003400: 58024400 .word 0x58024400 08003404 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8003404: b580 push {r7, lr} 8003406: b092 sub sp, #72 @ 0x48 8003408: af00 add r7, sp, #0 800340a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800340c: f107 0334 add.w r3, r7, #52 @ 0x34 8003410: 2200 movs r2, #0 8003412: 601a str r2, [r3, #0] 8003414: 605a str r2, [r3, #4] 8003416: 609a str r2, [r3, #8] 8003418: 60da str r2, [r3, #12] 800341a: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 800341c: 687b ldr r3, [r7, #4] 800341e: 681b ldr r3, [r3, #0] 8003420: 4a9d ldr r2, [pc, #628] @ (8003698 ) 8003422: 4293 cmp r3, r2 8003424: f040 8099 bne.w 800355a { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8003428: 4b9c ldr r3, [pc, #624] @ (800369c ) 800342a: 681b ldr r3, [r3, #0] 800342c: 3301 adds r3, #1 800342e: 4a9b ldr r2, [pc, #620] @ (800369c ) 8003430: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003432: 4b9a ldr r3, [pc, #616] @ (800369c ) 8003434: 681b ldr r3, [r3, #0] 8003436: 2b01 cmp r3, #1 8003438: d10e bne.n 8003458 __HAL_RCC_ADC12_CLK_ENABLE(); 800343a: 4b99 ldr r3, [pc, #612] @ (80036a0 ) 800343c: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003440: 4a97 ldr r2, [pc, #604] @ (80036a0 ) 8003442: f043 0320 orr.w r3, r3, #32 8003446: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 800344a: 4b95 ldr r3, [pc, #596] @ (80036a0 ) 800344c: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003450: f003 0320 and.w r3, r3, #32 8003454: 633b str r3, [r7, #48] @ 0x30 8003456: 6b3b ldr r3, [r7, #48] @ 0x30 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8003458: 4b91 ldr r3, [pc, #580] @ (80036a0 ) 800345a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800345e: 4a90 ldr r2, [pc, #576] @ (80036a0 ) 8003460: f043 0301 orr.w r3, r3, #1 8003464: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003468: 4b8d ldr r3, [pc, #564] @ (80036a0 ) 800346a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800346e: f003 0301 and.w r3, r3, #1 8003472: 62fb str r3, [r7, #44] @ 0x2c 8003474: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 8003476: 4b8a ldr r3, [pc, #552] @ (80036a0 ) 8003478: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800347c: 4a88 ldr r2, [pc, #544] @ (80036a0 ) 800347e: f043 0304 orr.w r3, r3, #4 8003482: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003486: 4b86 ldr r3, [pc, #536] @ (80036a0 ) 8003488: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800348c: f003 0304 and.w r3, r3, #4 8003490: 62bb str r3, [r7, #40] @ 0x28 8003492: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOB_CLK_ENABLE(); 8003494: 4b82 ldr r3, [pc, #520] @ (80036a0 ) 8003496: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800349a: 4a81 ldr r2, [pc, #516] @ (80036a0 ) 800349c: f043 0302 orr.w r3, r3, #2 80034a0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80034a4: 4b7e ldr r3, [pc, #504] @ (80036a0 ) 80034a6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80034aa: f003 0302 and.w r3, r3, #2 80034ae: 627b str r3, [r7, #36] @ 0x24 80034b0: 6a7b ldr r3, [r7, #36] @ 0x24 PA3 ------> ADC1_INP15 PA7 ------> ADC1_INP7 PC5 ------> ADC1_INP8 PB0 ------> ADC1_INP9 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 80034b2: 238f movs r3, #143 @ 0x8f 80034b4: 637b str r3, [r7, #52] @ 0x34 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80034b6: 2303 movs r3, #3 80034b8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80034ba: 2300 movs r3, #0 80034bc: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80034be: f107 0334 add.w r3, r7, #52 @ 0x34 80034c2: 4619 mov r1, r3 80034c4: 4877 ldr r0, [pc, #476] @ (80036a4 ) 80034c6: f007 f961 bl 800a78c GPIO_InitStruct.Pin = GPIO_PIN_5; 80034ca: 2320 movs r3, #32 80034cc: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80034ce: 2303 movs r3, #3 80034d0: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80034d2: 2300 movs r3, #0 80034d4: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80034d6: f107 0334 add.w r3, r7, #52 @ 0x34 80034da: 4619 mov r1, r3 80034dc: 4872 ldr r0, [pc, #456] @ (80036a8 ) 80034de: f007 f955 bl 800a78c GPIO_InitStruct.Pin = GPIO_PIN_0; 80034e2: 2301 movs r3, #1 80034e4: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80034e6: 2303 movs r3, #3 80034e8: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80034ea: 2300 movs r3, #0 80034ec: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80034ee: f107 0334 add.w r3, r7, #52 @ 0x34 80034f2: 4619 mov r1, r3 80034f4: 486d ldr r0, [pc, #436] @ (80036ac ) 80034f6: f007 f949 bl 800a78c /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Stream0; 80034fa: 4b6d ldr r3, [pc, #436] @ (80036b0 ) 80034fc: 4a6d ldr r2, [pc, #436] @ (80036b4 ) 80034fe: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8003500: 4b6b ldr r3, [pc, #428] @ (80036b0 ) 8003502: 2209 movs r2, #9 8003504: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003506: 4b6a ldr r3, [pc, #424] @ (80036b0 ) 8003508: 2200 movs r2, #0 800350a: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 800350c: 4b68 ldr r3, [pc, #416] @ (80036b0 ) 800350e: 2200 movs r2, #0 8003510: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8003512: 4b67 ldr r3, [pc, #412] @ (80036b0 ) 8003514: f44f 6280 mov.w r2, #1024 @ 0x400 8003518: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800351a: 4b65 ldr r3, [pc, #404] @ (80036b0 ) 800351c: f44f 6200 mov.w r2, #2048 @ 0x800 8003520: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003522: 4b63 ldr r3, [pc, #396] @ (80036b0 ) 8003524: f44f 5200 mov.w r2, #8192 @ 0x2000 8003528: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 800352a: 4b61 ldr r3, [pc, #388] @ (80036b0 ) 800352c: 2200 movs r2, #0 800352e: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8003530: 4b5f ldr r3, [pc, #380] @ (80036b0 ) 8003532: 2200 movs r2, #0 8003534: 621a str r2, [r3, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003536: 4b5e ldr r3, [pc, #376] @ (80036b0 ) 8003538: 2200 movs r2, #0 800353a: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 800353c: 485c ldr r0, [pc, #368] @ (80036b0 ) 800353e: f004 fae9 bl 8007b14 8003542: 4603 mov r3, r0 8003544: 2b00 cmp r3, #0 8003546: d001 beq.n 800354c { Error_Handler(); 8003548: f7fe fc62 bl 8001e10 } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 800354c: 687b ldr r3, [r7, #4] 800354e: 4a58 ldr r2, [pc, #352] @ (80036b0 ) 8003550: 64da str r2, [r3, #76] @ 0x4c 8003552: 4a57 ldr r2, [pc, #348] @ (80036b0 ) 8003554: 687b ldr r3, [r7, #4] 8003556: 6393 str r3, [r2, #56] @ 0x38 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 8003558: e11e b.n 8003798 else if(hadc->Instance==ADC2) 800355a: 687b ldr r3, [r7, #4] 800355c: 681b ldr r3, [r3, #0] 800355e: 4a56 ldr r2, [pc, #344] @ (80036b8 ) 8003560: 4293 cmp r3, r2 8003562: f040 80af bne.w 80036c4 HAL_RCC_ADC12_CLK_ENABLED++; 8003566: 4b4d ldr r3, [pc, #308] @ (800369c ) 8003568: 681b ldr r3, [r3, #0] 800356a: 3301 adds r3, #1 800356c: 4a4b ldr r2, [pc, #300] @ (800369c ) 800356e: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003570: 4b4a ldr r3, [pc, #296] @ (800369c ) 8003572: 681b ldr r3, [r3, #0] 8003574: 2b01 cmp r3, #1 8003576: d10e bne.n 8003596 __HAL_RCC_ADC12_CLK_ENABLE(); 8003578: 4b49 ldr r3, [pc, #292] @ (80036a0 ) 800357a: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 800357e: 4a48 ldr r2, [pc, #288] @ (80036a0 ) 8003580: f043 0320 orr.w r3, r3, #32 8003584: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003588: 4b45 ldr r3, [pc, #276] @ (80036a0 ) 800358a: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 800358e: f003 0320 and.w r3, r3, #32 8003592: 623b str r3, [r7, #32] 8003594: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003596: 4b42 ldr r3, [pc, #264] @ (80036a0 ) 8003598: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800359c: 4a40 ldr r2, [pc, #256] @ (80036a0 ) 800359e: f043 0301 orr.w r3, r3, #1 80035a2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80035a6: 4b3e ldr r3, [pc, #248] @ (80036a0 ) 80035a8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80035ac: f003 0301 and.w r3, r3, #1 80035b0: 61fb str r3, [r7, #28] 80035b2: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 80035b4: 4b3a ldr r3, [pc, #232] @ (80036a0 ) 80035b6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80035ba: 4a39 ldr r2, [pc, #228] @ (80036a0 ) 80035bc: f043 0304 orr.w r3, r3, #4 80035c0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80035c4: 4b36 ldr r3, [pc, #216] @ (80036a0 ) 80035c6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80035ca: f003 0304 and.w r3, r3, #4 80035ce: 61bb str r3, [r7, #24] 80035d0: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 80035d2: 4b33 ldr r3, [pc, #204] @ (80036a0 ) 80035d4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80035d8: 4a31 ldr r2, [pc, #196] @ (80036a0 ) 80035da: f043 0302 orr.w r3, r3, #2 80035de: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80035e2: 4b2f ldr r3, [pc, #188] @ (80036a0 ) 80035e4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80035e8: f003 0302 and.w r3, r3, #2 80035ec: 617b str r3, [r7, #20] 80035ee: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_6; 80035f0: 2340 movs r3, #64 @ 0x40 80035f2: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80035f4: 2303 movs r3, #3 80035f6: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 80035f8: 2300 movs r3, #0 80035fa: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80035fc: f107 0334 add.w r3, r7, #52 @ 0x34 8003600: 4619 mov r1, r3 8003602: 4828 ldr r0, [pc, #160] @ (80036a4 ) 8003604: f007 f8c2 bl 800a78c GPIO_InitStruct.Pin = GPIO_PIN_4; 8003608: 2310 movs r3, #16 800360a: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800360c: 2303 movs r3, #3 800360e: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003610: 2300 movs r3, #0 8003612: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003614: f107 0334 add.w r3, r7, #52 @ 0x34 8003618: 4619 mov r1, r3 800361a: 4823 ldr r0, [pc, #140] @ (80036a8 ) 800361c: f007 f8b6 bl 800a78c GPIO_InitStruct.Pin = GPIO_PIN_1; 8003620: 2302 movs r3, #2 8003622: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003624: 2303 movs r3, #3 8003626: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003628: 2300 movs r3, #0 800362a: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800362c: f107 0334 add.w r3, r7, #52 @ 0x34 8003630: 4619 mov r1, r3 8003632: 481e ldr r0, [pc, #120] @ (80036ac ) 8003634: f007 f8aa bl 800a78c hdma_adc2.Instance = DMA1_Stream1; 8003638: 4b20 ldr r3, [pc, #128] @ (80036bc ) 800363a: 4a21 ldr r2, [pc, #132] @ (80036c0 ) 800363c: 601a str r2, [r3, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 800363e: 4b1f ldr r3, [pc, #124] @ (80036bc ) 8003640: 220a movs r2, #10 8003642: 605a str r2, [r3, #4] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003644: 4b1d ldr r3, [pc, #116] @ (80036bc ) 8003646: 2200 movs r2, #0 8003648: 609a str r2, [r3, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 800364a: 4b1c ldr r3, [pc, #112] @ (80036bc ) 800364c: 2200 movs r2, #0 800364e: 60da str r2, [r3, #12] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8003650: 4b1a ldr r3, [pc, #104] @ (80036bc ) 8003652: f44f 6280 mov.w r2, #1024 @ 0x400 8003656: 611a str r2, [r3, #16] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003658: 4b18 ldr r3, [pc, #96] @ (80036bc ) 800365a: f44f 6200 mov.w r2, #2048 @ 0x800 800365e: 615a str r2, [r3, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003660: 4b16 ldr r3, [pc, #88] @ (80036bc ) 8003662: f44f 5200 mov.w r2, #8192 @ 0x2000 8003666: 619a str r2, [r3, #24] hdma_adc2.Init.Mode = DMA_NORMAL; 8003668: 4b14 ldr r3, [pc, #80] @ (80036bc ) 800366a: 2200 movs r2, #0 800366c: 61da str r2, [r3, #28] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 800366e: 4b13 ldr r3, [pc, #76] @ (80036bc ) 8003670: 2200 movs r2, #0 8003672: 621a str r2, [r3, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003674: 4b11 ldr r3, [pc, #68] @ (80036bc ) 8003676: 2200 movs r2, #0 8003678: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 800367a: 4810 ldr r0, [pc, #64] @ (80036bc ) 800367c: f004 fa4a bl 8007b14 8003680: 4603 mov r3, r0 8003682: 2b00 cmp r3, #0 8003684: d001 beq.n 800368a Error_Handler(); 8003686: f7fe fbc3 bl 8001e10 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 800368a: 687b ldr r3, [r7, #4] 800368c: 4a0b ldr r2, [pc, #44] @ (80036bc ) 800368e: 64da str r2, [r3, #76] @ 0x4c 8003690: 4a0a ldr r2, [pc, #40] @ (80036bc ) 8003692: 687b ldr r3, [r7, #4] 8003694: 6393 str r3, [r2, #56] @ 0x38 } 8003696: e07f b.n 8003798 8003698: 40022000 .word 0x40022000 800369c: 24000860 .word 0x24000860 80036a0: 58024400 .word 0x58024400 80036a4: 58020000 .word 0x58020000 80036a8: 58020800 .word 0x58020800 80036ac: 58020400 .word 0x58020400 80036b0: 2400026c .word 0x2400026c 80036b4: 40020010 .word 0x40020010 80036b8: 40022100 .word 0x40022100 80036bc: 240002e4 .word 0x240002e4 80036c0: 40020028 .word 0x40020028 else if(hadc->Instance==ADC3) 80036c4: 687b ldr r3, [r7, #4] 80036c6: 681b ldr r3, [r3, #0] 80036c8: 4a35 ldr r2, [pc, #212] @ (80037a0 ) 80036ca: 4293 cmp r3, r2 80036cc: d164 bne.n 8003798 __HAL_RCC_ADC3_CLK_ENABLE(); 80036ce: 4b35 ldr r3, [pc, #212] @ (80037a4 ) 80036d0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80036d4: 4a33 ldr r2, [pc, #204] @ (80037a4 ) 80036d6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 80036da: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80036de: 4b31 ldr r3, [pc, #196] @ (80037a4 ) 80036e0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80036e4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80036e8: 613b str r3, [r7, #16] 80036ea: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 80036ec: 4b2d ldr r3, [pc, #180] @ (80037a4 ) 80036ee: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80036f2: 4a2c ldr r2, [pc, #176] @ (80037a4 ) 80036f4: f043 0304 orr.w r3, r3, #4 80036f8: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80036fc: 4b29 ldr r3, [pc, #164] @ (80037a4 ) 80036fe: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003702: f003 0304 and.w r3, r3, #4 8003706: 60fb str r3, [r7, #12] 8003708: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 800370a: 2303 movs r3, #3 800370c: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 800370e: 2303 movs r3, #3 8003710: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003712: 2300 movs r3, #0 8003714: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003716: f107 0334 add.w r3, r7, #52 @ 0x34 800371a: 4619 mov r1, r3 800371c: 4822 ldr r0, [pc, #136] @ (80037a8 ) 800371e: f007 f835 bl 800a78c HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 8003722: f04f 6180 mov.w r1, #67108864 @ 0x4000000 8003726: f04f 6080 mov.w r0, #67108864 @ 0x4000000 800372a: f001 fe93 bl 8005454 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 800372e: f04f 6100 mov.w r1, #134217728 @ 0x8000000 8003732: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8003736: f001 fe8d bl 8005454 hdma_adc3.Instance = DMA1_Stream2; 800373a: 4b1c ldr r3, [pc, #112] @ (80037ac ) 800373c: 4a1c ldr r2, [pc, #112] @ (80037b0 ) 800373e: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 8003740: 4b1a ldr r3, [pc, #104] @ (80037ac ) 8003742: 2273 movs r2, #115 @ 0x73 8003744: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003746: 4b19 ldr r3, [pc, #100] @ (80037ac ) 8003748: 2200 movs r2, #0 800374a: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 800374c: 4b17 ldr r3, [pc, #92] @ (80037ac ) 800374e: 2200 movs r2, #0 8003750: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 8003752: 4b16 ldr r3, [pc, #88] @ (80037ac ) 8003754: f44f 6280 mov.w r2, #1024 @ 0x400 8003758: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800375a: 4b14 ldr r3, [pc, #80] @ (80037ac ) 800375c: f44f 6200 mov.w r2, #2048 @ 0x800 8003760: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003762: 4b12 ldr r3, [pc, #72] @ (80037ac ) 8003764: f44f 5200 mov.w r2, #8192 @ 0x2000 8003768: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_NORMAL; 800376a: 4b10 ldr r3, [pc, #64] @ (80037ac ) 800376c: 2200 movs r2, #0 800376e: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 8003770: 4b0e ldr r3, [pc, #56] @ (80037ac ) 8003772: 2200 movs r2, #0 8003774: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003776: 4b0d ldr r3, [pc, #52] @ (80037ac ) 8003778: 2200 movs r2, #0 800377a: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 800377c: 480b ldr r0, [pc, #44] @ (80037ac ) 800377e: f004 f9c9 bl 8007b14 8003782: 4603 mov r3, r0 8003784: 2b00 cmp r3, #0 8003786: d001 beq.n 800378c Error_Handler(); 8003788: f7fe fb42 bl 8001e10 __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 800378c: 687b ldr r3, [r7, #4] 800378e: 4a07 ldr r2, [pc, #28] @ (80037ac ) 8003790: 64da str r2, [r3, #76] @ 0x4c 8003792: 4a06 ldr r2, [pc, #24] @ (80037ac ) 8003794: 687b ldr r3, [r7, #4] 8003796: 6393 str r3, [r2, #56] @ 0x38 } 8003798: bf00 nop 800379a: 3748 adds r7, #72 @ 0x48 800379c: 46bd mov sp, r7 800379e: bd80 pop {r7, pc} 80037a0: 58026000 .word 0x58026000 80037a4: 58024400 .word 0x58024400 80037a8: 58020800 .word 0x58020800 80037ac: 2400035c .word 0x2400035c 80037b0: 40020040 .word 0x40020040 080037b4 : * This function configures the hardware resources used in this example * @param hcomp: COMP handle pointer * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { 80037b4: b580 push {r7, lr} 80037b6: b08a sub sp, #40 @ 0x28 80037b8: af00 add r7, sp, #0 80037ba: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80037bc: f107 0314 add.w r3, r7, #20 80037c0: 2200 movs r2, #0 80037c2: 601a str r2, [r3, #0] 80037c4: 605a str r2, [r3, #4] 80037c6: 609a str r2, [r3, #8] 80037c8: 60da str r2, [r3, #12] 80037ca: 611a str r2, [r3, #16] if(hcomp->Instance==COMP1) 80037cc: 687b ldr r3, [r7, #4] 80037ce: 681b ldr r3, [r3, #0] 80037d0: 4a18 ldr r2, [pc, #96] @ (8003834 ) 80037d2: 4293 cmp r3, r2 80037d4: d129 bne.n 800382a { /* USER CODE BEGIN COMP1_MspInit 0 */ /* USER CODE END COMP1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_COMP12_CLK_ENABLE(); 80037d6: 4b18 ldr r3, [pc, #96] @ (8003838 ) 80037d8: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80037dc: 4a16 ldr r2, [pc, #88] @ (8003838 ) 80037de: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80037e2: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 80037e6: 4b14 ldr r3, [pc, #80] @ (8003838 ) 80037e8: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80037ec: f403 4380 and.w r3, r3, #16384 @ 0x4000 80037f0: 613b str r3, [r7, #16] 80037f2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80037f4: 4b10 ldr r3, [pc, #64] @ (8003838 ) 80037f6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80037fa: 4a0f ldr r2, [pc, #60] @ (8003838 ) 80037fc: f043 0302 orr.w r3, r3, #2 8003800: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003804: 4b0c ldr r3, [pc, #48] @ (8003838 ) 8003806: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800380a: f003 0302 and.w r3, r3, #2 800380e: 60fb str r3, [r7, #12] 8003810: 68fb ldr r3, [r7, #12] /**COMP1 GPIO Configuration PB2 ------> COMP1_INP */ GPIO_InitStruct.Pin = GPIO_PIN_2; 8003812: 2304 movs r3, #4 8003814: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003816: 2303 movs r3, #3 8003818: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800381a: 2300 movs r3, #0 800381c: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800381e: f107 0314 add.w r3, r7, #20 8003822: 4619 mov r1, r3 8003824: 4805 ldr r0, [pc, #20] @ (800383c ) 8003826: f006 ffb1 bl 800a78c /* USER CODE BEGIN COMP1_MspInit 1 */ /* USER CODE END COMP1_MspInit 1 */ } } 800382a: bf00 nop 800382c: 3728 adds r7, #40 @ 0x28 800382e: 46bd mov sp, r7 8003830: bd80 pop {r7, pc} 8003832: bf00 nop 8003834: 5800380c .word 0x5800380c 8003838: 58024400 .word 0x58024400 800383c: 58020400 .word 0x58020400 08003840 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 8003840: b480 push {r7} 8003842: b085 sub sp, #20 8003844: af00 add r7, sp, #0 8003846: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8003848: 687b ldr r3, [r7, #4] 800384a: 681b ldr r3, [r3, #0] 800384c: 4a0b ldr r2, [pc, #44] @ (800387c ) 800384e: 4293 cmp r3, r2 8003850: d10e bne.n 8003870 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8003852: 4b0b ldr r3, [pc, #44] @ (8003880 ) 8003854: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003858: 4a09 ldr r2, [pc, #36] @ (8003880 ) 800385a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800385e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003862: 4b07 ldr r3, [pc, #28] @ (8003880 ) 8003864: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003868: f403 2300 and.w r3, r3, #524288 @ 0x80000 800386c: 60fb str r3, [r7, #12] 800386e: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 8003870: bf00 nop 8003872: 3714 adds r7, #20 8003874: 46bd mov sp, r7 8003876: f85d 7b04 ldr.w r7, [sp], #4 800387a: 4770 bx lr 800387c: 58024c00 .word 0x58024c00 8003880: 58024400 .word 0x58024400 08003884 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 8003884: b580 push {r7, lr} 8003886: b08a sub sp, #40 @ 0x28 8003888: af00 add r7, sp, #0 800388a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800388c: f107 0314 add.w r3, r7, #20 8003890: 2200 movs r2, #0 8003892: 601a str r2, [r3, #0] 8003894: 605a str r2, [r3, #4] 8003896: 609a str r2, [r3, #8] 8003898: 60da str r2, [r3, #12] 800389a: 611a str r2, [r3, #16] if(hdac->Instance==DAC1) 800389c: 687b ldr r3, [r7, #4] 800389e: 681b ldr r3, [r3, #0] 80038a0: 4a1c ldr r2, [pc, #112] @ (8003914 ) 80038a2: 4293 cmp r3, r2 80038a4: d131 bne.n 800390a { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); 80038a6: 4b1c ldr r3, [pc, #112] @ (8003918 ) 80038a8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80038ac: 4a1a ldr r2, [pc, #104] @ (8003918 ) 80038ae: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 80038b2: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80038b6: 4b18 ldr r3, [pc, #96] @ (8003918 ) 80038b8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80038bc: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80038c0: 613b str r3, [r7, #16] 80038c2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80038c4: 4b14 ldr r3, [pc, #80] @ (8003918 ) 80038c6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80038ca: 4a13 ldr r2, [pc, #76] @ (8003918 ) 80038cc: f043 0301 orr.w r3, r3, #1 80038d0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80038d4: 4b10 ldr r3, [pc, #64] @ (8003918 ) 80038d6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80038da: f003 0301 and.w r3, r3, #1 80038de: 60fb str r3, [r7, #12] 80038e0: 68fb ldr r3, [r7, #12] /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80038e2: 2330 movs r3, #48 @ 0x30 80038e4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80038e6: 2303 movs r3, #3 80038e8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80038ea: 2300 movs r3, #0 80038ec: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80038ee: f107 0314 add.w r3, r7, #20 80038f2: 4619 mov r1, r3 80038f4: 4809 ldr r0, [pc, #36] @ (800391c ) 80038f6: f006 ff49 bl 800a78c /* DAC1 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 80038fa: 2200 movs r2, #0 80038fc: 2105 movs r1, #5 80038fe: 2036 movs r0, #54 @ 0x36 8003900: f003 fc12 bl 8007128 HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8003904: 2036 movs r0, #54 @ 0x36 8003906: f003 fc29 bl 800715c /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 800390a: bf00 nop 800390c: 3728 adds r7, #40 @ 0x28 800390e: 46bd mov sp, r7 8003910: bd80 pop {r7, pc} 8003912: bf00 nop 8003914: 40007400 .word 0x40007400 8003918: 58024400 .word 0x58024400 800391c: 58020000 .word 0x58020000 08003920 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 8003920: b580 push {r7, lr} 8003922: b0b4 sub sp, #208 @ 0xd0 8003924: af00 add r7, sp, #0 8003926: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8003928: f107 0310 add.w r3, r7, #16 800392c: 22c0 movs r2, #192 @ 0xc0 800392e: 2100 movs r1, #0 8003930: 4618 mov r0, r3 8003932: f014 f910 bl 8017b56 if(hrng->Instance==RNG) 8003936: 687b ldr r3, [r7, #4] 8003938: 681b ldr r3, [r3, #0] 800393a: 4a14 ldr r2, [pc, #80] @ (800398c ) 800393c: 4293 cmp r3, r2 800393e: d121 bne.n 8003984 /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 8003940: f44f 3200 mov.w r2, #131072 @ 0x20000 8003944: f04f 0300 mov.w r3, #0 8003948: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 800394c: 2300 movs r3, #0 800394e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8003952: f107 0310 add.w r3, r7, #16 8003956: 4618 mov r0, r3 8003958: f008 faa0 bl 800be9c 800395c: 4603 mov r3, r0 800395e: 2b00 cmp r3, #0 8003960: d001 beq.n 8003966 { Error_Handler(); 8003962: f7fe fa55 bl 8001e10 } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 8003966: 4b0a ldr r3, [pc, #40] @ (8003990 ) 8003968: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 800396c: 4a08 ldr r2, [pc, #32] @ (8003990 ) 800396e: f043 0340 orr.w r3, r3, #64 @ 0x40 8003972: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 8003976: 4b06 ldr r3, [pc, #24] @ (8003990 ) 8003978: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 800397c: f003 0340 and.w r3, r3, #64 @ 0x40 8003980: 60fb str r3, [r7, #12] 8003982: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 8003984: bf00 nop 8003986: 37d0 adds r7, #208 @ 0xd0 8003988: 46bd mov sp, r7 800398a: bd80 pop {r7, pc} 800398c: 48021800 .word 0x48021800 8003990: 58024400 .word 0x58024400 08003994 : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 8003994: b480 push {r7} 8003996: b085 sub sp, #20 8003998: af00 add r7, sp, #0 800399a: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 800399c: 687b ldr r3, [r7, #4] 800399e: 681b ldr r3, [r3, #0] 80039a0: 4a16 ldr r2, [pc, #88] @ (80039fc ) 80039a2: 4293 cmp r3, r2 80039a4: d10f bne.n 80039c6 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 80039a6: 4b16 ldr r3, [pc, #88] @ (8003a00 ) 80039a8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80039ac: 4a14 ldr r2, [pc, #80] @ (8003a00 ) 80039ae: f043 0301 orr.w r3, r3, #1 80039b2: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80039b6: 4b12 ldr r3, [pc, #72] @ (8003a00 ) 80039b8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80039bc: f003 0301 and.w r3, r3, #1 80039c0: 60fb str r3, [r7, #12] 80039c2: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 80039c4: e013 b.n 80039ee else if(htim_pwm->Instance==TIM3) 80039c6: 687b ldr r3, [r7, #4] 80039c8: 681b ldr r3, [r3, #0] 80039ca: 4a0e ldr r2, [pc, #56] @ (8003a04 ) 80039cc: 4293 cmp r3, r2 80039ce: d10e bne.n 80039ee __HAL_RCC_TIM3_CLK_ENABLE(); 80039d0: 4b0b ldr r3, [pc, #44] @ (8003a00 ) 80039d2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80039d6: 4a0a ldr r2, [pc, #40] @ (8003a00 ) 80039d8: f043 0302 orr.w r3, r3, #2 80039dc: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80039e0: 4b07 ldr r3, [pc, #28] @ (8003a00 ) 80039e2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80039e6: f003 0302 and.w r3, r3, #2 80039ea: 60bb str r3, [r7, #8] 80039ec: 68bb ldr r3, [r7, #8] } 80039ee: bf00 nop 80039f0: 3714 adds r7, #20 80039f2: 46bd mov sp, r7 80039f4: f85d 7b04 ldr.w r7, [sp], #4 80039f8: 4770 bx lr 80039fa: bf00 nop 80039fc: 40010000 .word 0x40010000 8003a00: 58024400 .word 0x58024400 8003a04: 40000400 .word 0x40000400 08003a08 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8003a08: b580 push {r7, lr} 8003a0a: b08c sub sp, #48 @ 0x30 8003a0c: af00 add r7, sp, #0 8003a0e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003a10: f107 031c add.w r3, r7, #28 8003a14: 2200 movs r2, #0 8003a16: 601a str r2, [r3, #0] 8003a18: 605a str r2, [r3, #4] 8003a1a: 609a str r2, [r3, #8] 8003a1c: 60da str r2, [r3, #12] 8003a1e: 611a str r2, [r3, #16] if(htim_base->Instance==TIM2) 8003a20: 687b ldr r3, [r7, #4] 8003a22: 681b ldr r3, [r3, #0] 8003a24: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8003a28: d137 bne.n 8003a9a { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 8003a2a: 4b3c ldr r3, [pc, #240] @ (8003b1c ) 8003a2c: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003a30: 4a3a ldr r2, [pc, #232] @ (8003b1c ) 8003a32: f043 0301 orr.w r3, r3, #1 8003a36: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003a3a: 4b38 ldr r3, [pc, #224] @ (8003b1c ) 8003a3c: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003a40: f003 0301 and.w r3, r3, #1 8003a44: 61bb str r3, [r7, #24] 8003a46: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003a48: 4b34 ldr r3, [pc, #208] @ (8003b1c ) 8003a4a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003a4e: 4a33 ldr r2, [pc, #204] @ (8003b1c ) 8003a50: f043 0302 orr.w r3, r3, #2 8003a54: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003a58: 4b30 ldr r3, [pc, #192] @ (8003b1c ) 8003a5a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003a5e: f003 0302 and.w r3, r3, #2 8003a62: 617b str r3, [r7, #20] 8003a64: 697b ldr r3, [r7, #20] /**TIM2 GPIO Configuration PB10 ------> TIM2_CH3 PB11 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 8003a66: f44f 6340 mov.w r3, #3072 @ 0xc00 8003a6a: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003a6c: 2302 movs r3, #2 8003a6e: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003a70: 2300 movs r3, #0 8003a72: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003a74: 2300 movs r3, #0 8003a76: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8003a78: 2301 movs r3, #1 8003a7a: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003a7c: f107 031c add.w r3, r7, #28 8003a80: 4619 mov r1, r3 8003a82: 4827 ldr r0, [pc, #156] @ (8003b20 ) 8003a84: f006 fe82 bl 800a78c /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0); 8003a88: 2200 movs r2, #0 8003a8a: 2105 movs r1, #5 8003a8c: 201c movs r0, #28 8003a8e: f003 fb4b bl 8007128 HAL_NVIC_EnableIRQ(TIM2_IRQn); 8003a92: 201c movs r0, #28 8003a94: f003 fb62 bl 800715c /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ } } 8003a98: e03b b.n 8003b12 else if(htim_base->Instance==TIM4) 8003a9a: 687b ldr r3, [r7, #4] 8003a9c: 681b ldr r3, [r3, #0] 8003a9e: 4a21 ldr r2, [pc, #132] @ (8003b24 ) 8003aa0: 4293 cmp r3, r2 8003aa2: d136 bne.n 8003b12 __HAL_RCC_TIM4_CLK_ENABLE(); 8003aa4: 4b1d ldr r3, [pc, #116] @ (8003b1c ) 8003aa6: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003aaa: 4a1c ldr r2, [pc, #112] @ (8003b1c ) 8003aac: f043 0304 orr.w r3, r3, #4 8003ab0: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003ab4: 4b19 ldr r3, [pc, #100] @ (8003b1c ) 8003ab6: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003aba: f003 0304 and.w r3, r3, #4 8003abe: 613b str r3, [r7, #16] 8003ac0: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 8003ac2: 4b16 ldr r3, [pc, #88] @ (8003b1c ) 8003ac4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ac8: 4a14 ldr r2, [pc, #80] @ (8003b1c ) 8003aca: f043 0308 orr.w r3, r3, #8 8003ace: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003ad2: 4b12 ldr r3, [pc, #72] @ (8003b1c ) 8003ad4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ad8: f003 0308 and.w r3, r3, #8 8003adc: 60fb str r3, [r7, #12] 8003ade: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8003ae0: f44f 4340 mov.w r3, #49152 @ 0xc000 8003ae4: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003ae6: 2302 movs r3, #2 8003ae8: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003aea: 2300 movs r3, #0 8003aec: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003aee: 2300 movs r3, #0 8003af0: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; 8003af2: 2302 movs r3, #2 8003af4: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8003af6: f107 031c add.w r3, r7, #28 8003afa: 4619 mov r1, r3 8003afc: 480a ldr r0, [pc, #40] @ (8003b28 ) 8003afe: f006 fe45 bl 800a78c HAL_NVIC_SetPriority(TIM4_IRQn, 5, 0); 8003b02: 2200 movs r2, #0 8003b04: 2105 movs r1, #5 8003b06: 201e movs r0, #30 8003b08: f003 fb0e bl 8007128 HAL_NVIC_EnableIRQ(TIM4_IRQn); 8003b0c: 201e movs r0, #30 8003b0e: f003 fb25 bl 800715c } 8003b12: bf00 nop 8003b14: 3730 adds r7, #48 @ 0x30 8003b16: 46bd mov sp, r7 8003b18: bd80 pop {r7, pc} 8003b1a: bf00 nop 8003b1c: 58024400 .word 0x58024400 8003b20: 58020400 .word 0x58020400 8003b24: 40000800 .word 0x40000800 8003b28: 58020c00 .word 0x58020c00 08003b2c : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8003b2c: b580 push {r7, lr} 8003b2e: b08a sub sp, #40 @ 0x28 8003b30: af00 add r7, sp, #0 8003b32: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003b34: f107 0314 add.w r3, r7, #20 8003b38: 2200 movs r2, #0 8003b3a: 601a str r2, [r3, #0] 8003b3c: 605a str r2, [r3, #4] 8003b3e: 609a str r2, [r3, #8] 8003b40: 60da str r2, [r3, #12] 8003b42: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 8003b44: 687b ldr r3, [r7, #4] 8003b46: 681b ldr r3, [r3, #0] 8003b48: 4a26 ldr r2, [pc, #152] @ (8003be4 ) 8003b4a: 4293 cmp r3, r2 8003b4c: d120 bne.n 8003b90 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8003b4e: 4b26 ldr r3, [pc, #152] @ (8003be8 ) 8003b50: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003b54: 4a24 ldr r2, [pc, #144] @ (8003be8 ) 8003b56: f043 0301 orr.w r3, r3, #1 8003b5a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003b5e: 4b22 ldr r3, [pc, #136] @ (8003be8 ) 8003b60: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003b64: f003 0301 and.w r3, r3, #1 8003b68: 613b str r3, [r7, #16] 8003b6a: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8003b6c: f44f 7300 mov.w r3, #512 @ 0x200 8003b70: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003b72: 2302 movs r3, #2 8003b74: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003b76: 2300 movs r3, #0 8003b78: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003b7a: 2300 movs r3, #0 8003b7c: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 8003b7e: 2301 movs r3, #1 8003b80: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003b82: f107 0314 add.w r3, r7, #20 8003b86: 4619 mov r1, r3 8003b88: 4818 ldr r0, [pc, #96] @ (8003bec ) 8003b8a: f006 fdff bl 800a78c /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 8003b8e: e024 b.n 8003bda else if(htim->Instance==TIM3) 8003b90: 687b ldr r3, [r7, #4] 8003b92: 681b ldr r3, [r3, #0] 8003b94: 4a16 ldr r2, [pc, #88] @ (8003bf0 ) 8003b96: 4293 cmp r3, r2 8003b98: d11f bne.n 8003bda __HAL_RCC_GPIOC_CLK_ENABLE(); 8003b9a: 4b13 ldr r3, [pc, #76] @ (8003be8 ) 8003b9c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ba0: 4a11 ldr r2, [pc, #68] @ (8003be8 ) 8003ba2: f043 0304 orr.w r3, r3, #4 8003ba6: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003baa: 4b0f ldr r3, [pc, #60] @ (8003be8 ) 8003bac: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003bb0: f003 0304 and.w r3, r3, #4 8003bb4: 60fb str r3, [r7, #12] 8003bb6: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 8003bb8: f44f 7370 mov.w r3, #960 @ 0x3c0 8003bbc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003bbe: 2302 movs r3, #2 8003bc0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003bc2: 2300 movs r3, #0 8003bc4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 8003bc6: 2301 movs r3, #1 8003bc8: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 8003bca: 2302 movs r3, #2 8003bcc: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003bce: f107 0314 add.w r3, r7, #20 8003bd2: 4619 mov r1, r3 8003bd4: 4807 ldr r0, [pc, #28] @ (8003bf4 ) 8003bd6: f006 fdd9 bl 800a78c } 8003bda: bf00 nop 8003bdc: 3728 adds r7, #40 @ 0x28 8003bde: 46bd mov sp, r7 8003be0: bd80 pop {r7, pc} 8003be2: bf00 nop 8003be4: 40010000 .word 0x40010000 8003be8: 58024400 .word 0x58024400 8003bec: 58020000 .word 0x58020000 8003bf0: 40000400 .word 0x40000400 8003bf4: 58020800 .word 0x58020800 08003bf8 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8003bf8: b580 push {r7, lr} 8003bfa: b0bc sub sp, #240 @ 0xf0 8003bfc: af00 add r7, sp, #0 8003bfe: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003c00: f107 03dc add.w r3, r7, #220 @ 0xdc 8003c04: 2200 movs r2, #0 8003c06: 601a str r2, [r3, #0] 8003c08: 605a str r2, [r3, #4] 8003c0a: 609a str r2, [r3, #8] 8003c0c: 60da str r2, [r3, #12] 8003c0e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8003c10: f107 0318 add.w r3, r7, #24 8003c14: 22c0 movs r2, #192 @ 0xc0 8003c16: 2100 movs r1, #0 8003c18: 4618 mov r0, r3 8003c1a: f013 ff9c bl 8017b56 if(huart->Instance==UART8) 8003c1e: 687b ldr r3, [r7, #4] 8003c20: 681b ldr r3, [r3, #0] 8003c22: 4a55 ldr r2, [pc, #340] @ (8003d78 ) 8003c24: 4293 cmp r3, r2 8003c26: d14e bne.n 8003cc6 /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8003c28: f04f 0202 mov.w r2, #2 8003c2c: f04f 0300 mov.w r3, #0 8003c30: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8003c34: 2300 movs r3, #0 8003c36: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8003c3a: f107 0318 add.w r3, r7, #24 8003c3e: 4618 mov r0, r3 8003c40: f008 f92c bl 800be9c 8003c44: 4603 mov r3, r0 8003c46: 2b00 cmp r3, #0 8003c48: d001 beq.n 8003c4e { Error_Handler(); 8003c4a: f7fe f8e1 bl 8001e10 } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 8003c4e: 4b4b ldr r3, [pc, #300] @ (8003d7c ) 8003c50: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003c54: 4a49 ldr r2, [pc, #292] @ (8003d7c ) 8003c56: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8003c5a: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003c5e: 4b47 ldr r3, [pc, #284] @ (8003d7c ) 8003c60: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003c64: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8003c68: 617b str r3, [r7, #20] 8003c6a: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 8003c6c: 4b43 ldr r3, [pc, #268] @ (8003d7c ) 8003c6e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c72: 4a42 ldr r2, [pc, #264] @ (8003d7c ) 8003c74: f043 0310 orr.w r3, r3, #16 8003c78: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003c7c: 4b3f ldr r3, [pc, #252] @ (8003d7c ) 8003c7e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003c82: f003 0310 and.w r3, r3, #16 8003c86: 613b str r3, [r7, #16] 8003c88: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8003c8a: 2303 movs r3, #3 8003c8c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003c90: 2302 movs r3, #2 8003c92: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003c96: 2300 movs r3, #0 8003c98: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003c9c: 2300 movs r3, #0 8003c9e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 8003ca2: 2308 movs r3, #8 8003ca4: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8003ca8: f107 03dc add.w r3, r7, #220 @ 0xdc 8003cac: 4619 mov r1, r3 8003cae: 4834 ldr r0, [pc, #208] @ (8003d80 ) 8003cb0: f006 fd6c bl 800a78c /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 8003cb4: 2200 movs r2, #0 8003cb6: 2105 movs r1, #5 8003cb8: 2053 movs r0, #83 @ 0x53 8003cba: f003 fa35 bl 8007128 HAL_NVIC_EnableIRQ(UART8_IRQn); 8003cbe: 2053 movs r0, #83 @ 0x53 8003cc0: f003 fa4c bl 800715c /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 8003cc4: e053 b.n 8003d6e else if(huart->Instance==USART1) 8003cc6: 687b ldr r3, [r7, #4] 8003cc8: 681b ldr r3, [r3, #0] 8003cca: 4a2e ldr r2, [pc, #184] @ (8003d84 ) 8003ccc: 4293 cmp r3, r2 8003cce: d14e bne.n 8003d6e PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8003cd0: f04f 0201 mov.w r2, #1 8003cd4: f04f 0300 mov.w r3, #0 8003cd8: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 8003cdc: 2300 movs r3, #0 8003cde: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8003ce2: f107 0318 add.w r3, r7, #24 8003ce6: 4618 mov r0, r3 8003ce8: f008 f8d8 bl 800be9c 8003cec: 4603 mov r3, r0 8003cee: 2b00 cmp r3, #0 8003cf0: d001 beq.n 8003cf6 Error_Handler(); 8003cf2: f7fe f88d bl 8001e10 __HAL_RCC_USART1_CLK_ENABLE(); 8003cf6: 4b21 ldr r3, [pc, #132] @ (8003d7c ) 8003cf8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8003cfc: 4a1f ldr r2, [pc, #124] @ (8003d7c ) 8003cfe: f043 0310 orr.w r3, r3, #16 8003d02: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 8003d06: 4b1d ldr r3, [pc, #116] @ (8003d7c ) 8003d08: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8003d0c: f003 0310 and.w r3, r3, #16 8003d10: 60fb str r3, [r7, #12] 8003d12: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003d14: 4b19 ldr r3, [pc, #100] @ (8003d7c ) 8003d16: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d1a: 4a18 ldr r2, [pc, #96] @ (8003d7c ) 8003d1c: f043 0302 orr.w r3, r3, #2 8003d20: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d24: 4b15 ldr r3, [pc, #84] @ (8003d7c ) 8003d26: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d2a: f003 0302 and.w r3, r3, #2 8003d2e: 60bb str r3, [r7, #8] 8003d30: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8003d32: f44f 4340 mov.w r3, #49152 @ 0xc000 8003d36: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003d3a: 2302 movs r3, #2 8003d3c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d40: 2300 movs r3, #0 8003d42: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003d46: 2300 movs r3, #0 8003d48: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 8003d4c: 2304 movs r3, #4 8003d4e: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003d52: f107 03dc add.w r3, r7, #220 @ 0xdc 8003d56: 4619 mov r1, r3 8003d58: 480b ldr r0, [pc, #44] @ (8003d88 ) 8003d5a: f006 fd17 bl 800a78c HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 8003d5e: 2200 movs r2, #0 8003d60: 2105 movs r1, #5 8003d62: 2025 movs r0, #37 @ 0x25 8003d64: f003 f9e0 bl 8007128 HAL_NVIC_EnableIRQ(USART1_IRQn); 8003d68: 2025 movs r0, #37 @ 0x25 8003d6a: f003 f9f7 bl 800715c } 8003d6e: bf00 nop 8003d70: 37f0 adds r7, #240 @ 0xf0 8003d72: 46bd mov sp, r7 8003d74: bd80 pop {r7, pc} 8003d76: bf00 nop 8003d78: 40007c00 .word 0x40007c00 8003d7c: 58024400 .word 0x58024400 8003d80: 58021000 .word 0x58021000 8003d84: 40011000 .word 0x40011000 8003d88: 58020400 .word 0x58020400 08003d8c : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8003d8c: b580 push {r7, lr} 8003d8e: b090 sub sp, #64 @ 0x40 8003d90: af00 add r7, sp, #0 8003d92: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8003d94: 687b ldr r3, [r7, #4] 8003d96: 2b0f cmp r3, #15 8003d98: d827 bhi.n 8003dea { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 8003d9a: 2200 movs r2, #0 8003d9c: 6879 ldr r1, [r7, #4] 8003d9e: 2036 movs r0, #54 @ 0x36 8003da0: f003 f9c2 bl 8007128 /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8003da4: 2036 movs r0, #54 @ 0x36 8003da6: f003 f9d9 bl 800715c uwTickPrio = TickPriority; 8003daa: 4a29 ldr r2, [pc, #164] @ (8003e50 ) 8003dac: 687b ldr r3, [r7, #4] 8003dae: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 8003db0: 4b28 ldr r3, [pc, #160] @ (8003e54 ) 8003db2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003db6: 4a27 ldr r2, [pc, #156] @ (8003e54 ) 8003db8: f043 0310 orr.w r3, r3, #16 8003dbc: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8003dc0: 4b24 ldr r3, [pc, #144] @ (8003e54 ) 8003dc2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8003dc6: f003 0310 and.w r3, r3, #16 8003dca: 60fb str r3, [r7, #12] 8003dcc: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8003dce: f107 0210 add.w r2, r7, #16 8003dd2: f107 0314 add.w r3, r7, #20 8003dd6: 4611 mov r1, r2 8003dd8: 4618 mov r0, r3 8003dda: f008 f81d bl 800be18 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 8003dde: 6abb ldr r3, [r7, #40] @ 0x28 8003de0: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 8003de2: 6bbb ldr r3, [r7, #56] @ 0x38 8003de4: 2b00 cmp r3, #0 8003de6: d106 bne.n 8003df6 8003de8: e001 b.n 8003dee return HAL_ERROR; 8003dea: 2301 movs r3, #1 8003dec: e02b b.n 8003e46 { uwTimclock = HAL_RCC_GetPCLK1Freq(); 8003dee: f007 ffe7 bl 800bdc0 8003df2: 63f8 str r0, [r7, #60] @ 0x3c 8003df4: e004 b.n 8003e00 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 8003df6: f007 ffe3 bl 800bdc0 8003dfa: 4603 mov r3, r0 8003dfc: 005b lsls r3, r3, #1 8003dfe: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 8003e00: 6bfb ldr r3, [r7, #60] @ 0x3c 8003e02: 4a15 ldr r2, [pc, #84] @ (8003e58 ) 8003e04: fba2 2303 umull r2, r3, r2, r3 8003e08: 0c9b lsrs r3, r3, #18 8003e0a: 3b01 subs r3, #1 8003e0c: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 8003e0e: 4b13 ldr r3, [pc, #76] @ (8003e5c ) 8003e10: 4a13 ldr r2, [pc, #76] @ (8003e60 ) 8003e12: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 8003e14: 4b11 ldr r3, [pc, #68] @ (8003e5c ) 8003e16: f240 32e7 movw r2, #999 @ 0x3e7 8003e1a: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8003e1c: 4a0f ldr r2, [pc, #60] @ (8003e5c ) 8003e1e: 6b7b ldr r3, [r7, #52] @ 0x34 8003e20: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 8003e22: 4b0e ldr r3, [pc, #56] @ (8003e5c ) 8003e24: 2200 movs r2, #0 8003e26: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8003e28: 4b0c ldr r3, [pc, #48] @ (8003e5c ) 8003e2a: 2200 movs r2, #0 8003e2c: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 8003e2e: 480b ldr r0, [pc, #44] @ (8003e5c ) 8003e30: f00a fd78 bl 800e924 8003e34: 4603 mov r3, r0 8003e36: 2b00 cmp r3, #0 8003e38: d104 bne.n 8003e44 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 8003e3a: 4808 ldr r0, [pc, #32] @ (8003e5c ) 8003e3c: f00a fe3a bl 800eab4 8003e40: 4603 mov r3, r0 8003e42: e000 b.n 8003e46 } /* Return function status */ return HAL_ERROR; 8003e44: 2301 movs r3, #1 } 8003e46: 4618 mov r0, r3 8003e48: 3740 adds r7, #64 @ 0x40 8003e4a: 46bd mov sp, r7 8003e4c: bd80 pop {r7, pc} 8003e4e: bf00 nop 8003e50: 2400003c .word 0x2400003c 8003e54: 58024400 .word 0x58024400 8003e58: 431bde83 .word 0x431bde83 8003e5c: 24000864 .word 0x24000864 8003e60: 40001000 .word 0x40001000 08003e64 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8003e64: b480 push {r7} 8003e66: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8003e68: bf00 nop 8003e6a: e7fd b.n 8003e68 08003e6c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8003e6c: b480 push {r7} 8003e6e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8003e70: bf00 nop 8003e72: e7fd b.n 8003e70 08003e74 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8003e74: b480 push {r7} 8003e76: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8003e78: bf00 nop 8003e7a: e7fd b.n 8003e78 08003e7c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8003e7c: b480 push {r7} 8003e7e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8003e80: bf00 nop 8003e82: e7fd b.n 8003e80 08003e84 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8003e84: b480 push {r7} 8003e86: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8003e88: bf00 nop 8003e8a: e7fd b.n 8003e88 08003e8c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8003e8c: b480 push {r7} 8003e8e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8003e90: bf00 nop 8003e92: 46bd mov sp, r7 8003e94: f85d 7b04 ldr.w r7, [sp], #4 8003e98: 4770 bx lr 08003e9a : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 8003e9a: b480 push {r7} 8003e9c: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 8003e9e: bf00 nop 8003ea0: 46bd mov sp, r7 8003ea2: f85d 7b04 ldr.w r7, [sp], #4 8003ea6: 4770 bx lr 08003ea8 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8003ea8: b580 push {r7, lr} 8003eaa: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 8003eac: 4802 ldr r0, [pc, #8] @ (8003eb8 ) 8003eae: f005 f95b bl 8009168 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 8003eb2: bf00 nop 8003eb4: bd80 pop {r7, pc} 8003eb6: bf00 nop 8003eb8: 2400026c .word 0x2400026c 08003ebc : /** * @brief This function handles DMA1 stream1 global interrupt. */ void DMA1_Stream1_IRQHandler(void) { 8003ebc: b580 push {r7, lr} 8003ebe: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 8003ec0: 4802 ldr r0, [pc, #8] @ (8003ecc ) 8003ec2: f005 f951 bl 8009168 /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ /* USER CODE END DMA1_Stream1_IRQn 1 */ } 8003ec6: bf00 nop 8003ec8: bd80 pop {r7, pc} 8003eca: bf00 nop 8003ecc: 240002e4 .word 0x240002e4 08003ed0 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 8003ed0: b580 push {r7, lr} 8003ed2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 8003ed4: 4802 ldr r0, [pc, #8] @ (8003ee0 ) 8003ed6: f005 f947 bl 8009168 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 8003eda: bf00 nop 8003edc: bd80 pop {r7, pc} 8003ede: bf00 nop 8003ee0: 2400035c .word 0x2400035c 08003ee4 : /** * @brief This function handles EXTI line[9:5] interrupts. */ void EXTI9_5_IRQHandler(void) { 8003ee4: b580 push {r7, lr} 8003ee6: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ /* USER CODE END EXTI9_5_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); 8003ee8: f44f 7080 mov.w r0, #256 @ 0x100 8003eec: f006 fe49 bl 800ab82 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); 8003ef0: f44f 7000 mov.w r0, #512 @ 0x200 8003ef4: f006 fe45 bl 800ab82 /* USER CODE BEGIN EXTI9_5_IRQn 1 */ /* USER CODE END EXTI9_5_IRQn 1 */ } 8003ef8: bf00 nop 8003efa: bd80 pop {r7, pc} 08003efc : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 8003efc: b580 push {r7, lr} 8003efe: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 8003f00: 4802 ldr r0, [pc, #8] @ (8003f0c ) 8003f02: f00b f9fd bl 800f300 /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 8003f06: bf00 nop 8003f08: bd80 pop {r7, pc} 8003f0a: bf00 nop 8003f0c: 24000498 .word 0x24000498 08003f10 : /** * @brief This function handles TIM4 global interrupt. */ void TIM4_IRQHandler(void) { 8003f10: b580 push {r7, lr} 8003f12: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_IRQn 0 */ /* USER CODE END TIM4_IRQn 0 */ HAL_TIM_IRQHandler(&htim4); 8003f14: 4802 ldr r0, [pc, #8] @ (8003f20 ) 8003f16: f00b f9f3 bl 800f300 /* USER CODE BEGIN TIM4_IRQn 1 */ /* USER CODE END TIM4_IRQn 1 */ } 8003f1a: bf00 nop 8003f1c: bd80 pop {r7, pc} 8003f1e: bf00 nop 8003f20: 24000530 .word 0x24000530 08003f24 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8003f24: b580 push {r7, lr} 8003f26: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8003f28: 4802 ldr r0, [pc, #8] @ (8003f34 ) 8003f2a: f00c fe3b bl 8010ba4 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8003f2e: bf00 nop 8003f30: bd80 pop {r7, pc} 8003f32: bf00 nop 8003f34: 24000610 .word 0x24000610 08003f38 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8003f38: b580 push {r7, lr} 8003f3a: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 8003f3c: f44f 6080 mov.w r0, #1024 @ 0x400 8003f40: f006 fe1f bl 800ab82 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 8003f44: f44f 6000 mov.w r0, #2048 @ 0x800 8003f48: f006 fe1b bl 800ab82 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); 8003f4c: f44f 5080 mov.w r0, #4096 @ 0x1000 8003f50: f006 fe17 bl 800ab82 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); 8003f54: f44f 5000 mov.w r0, #8192 @ 0x2000 8003f58: f006 fe13 bl 800ab82 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 8003f5c: bf00 nop 8003f5e: bd80 pop {r7, pc} 08003f60 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8003f60: b580 push {r7, lr} 8003f62: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 8003f64: 4b06 ldr r3, [pc, #24] @ (8003f80 ) 8003f66: 791b ldrb r3, [r3, #4] 8003f68: b2db uxtb r3, r3 8003f6a: 2b00 cmp r3, #0 8003f6c: d002 beq.n 8003f74 HAL_DAC_IRQHandler(&hdac1); 8003f6e: 4804 ldr r0, [pc, #16] @ (8003f80 ) 8003f70: f003 fbf9 bl 8007766 } HAL_TIM_IRQHandler(&htim6); 8003f74: 4803 ldr r0, [pc, #12] @ (8003f84 ) 8003f76: f00b f9c3 bl 800f300 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8003f7a: bf00 nop 8003f7c: bd80 pop {r7, pc} 8003f7e: bf00 nop 8003f80: 24000424 .word 0x24000424 8003f84: 24000864 .word 0x24000864 08003f88 : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 8003f88: b580 push {r7, lr} 8003f8a: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 8003f8c: 4802 ldr r0, [pc, #8] @ (8003f98 ) 8003f8e: f00c fe09 bl 8010ba4 /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 8003f92: bf00 nop 8003f94: bd80 pop {r7, pc} 8003f96: bf00 nop 8003f98: 2400057c .word 0x2400057c 08003f9c <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { 8003f9c: b580 push {r7, lr} 8003f9e: b086 sub sp, #24 8003fa0: af00 add r7, sp, #0 8003fa2: 60f8 str r0, [r7, #12] 8003fa4: 60b9 str r1, [r7, #8] 8003fa6: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8003fa8: 2300 movs r3, #0 8003faa: 617b str r3, [r7, #20] 8003fac: e00a b.n 8003fc4 <_read+0x28> { *ptr++ = __io_getchar(); 8003fae: f3af 8000 nop.w 8003fb2: 4601 mov r1, r0 8003fb4: 68bb ldr r3, [r7, #8] 8003fb6: 1c5a adds r2, r3, #1 8003fb8: 60ba str r2, [r7, #8] 8003fba: b2ca uxtb r2, r1 8003fbc: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) 8003fbe: 697b ldr r3, [r7, #20] 8003fc0: 3301 adds r3, #1 8003fc2: 617b str r3, [r7, #20] 8003fc4: 697a ldr r2, [r7, #20] 8003fc6: 687b ldr r3, [r7, #4] 8003fc8: 429a cmp r2, r3 8003fca: dbf0 blt.n 8003fae <_read+0x12> } return len; 8003fcc: 687b ldr r3, [r7, #4] } 8003fce: 4618 mov r0, r3 8003fd0: 3718 adds r7, #24 8003fd2: 46bd mov sp, r7 8003fd4: bd80 pop {r7, pc} 08003fd6 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { 8003fd6: b580 push {r7, lr} 8003fd8: b086 sub sp, #24 8003fda: af00 add r7, sp, #0 8003fdc: 60f8 str r0, [r7, #12] 8003fde: 60b9 str r1, [r7, #8] 8003fe0: 607a str r2, [r7, #4] (void)file; int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) 8003fe2: 2300 movs r3, #0 8003fe4: 617b str r3, [r7, #20] 8003fe6: e009 b.n 8003ffc <_write+0x26> { __io_putchar(*ptr++); 8003fe8: 68bb ldr r3, [r7, #8] 8003fea: 1c5a adds r2, r3, #1 8003fec: 60ba str r2, [r7, #8] 8003fee: 781b ldrb r3, [r3, #0] 8003ff0: 4618 mov r0, r3 8003ff2: f7fc fb49 bl 8000688 <__io_putchar> for (DataIdx = 0; DataIdx < len; DataIdx++) 8003ff6: 697b ldr r3, [r7, #20] 8003ff8: 3301 adds r3, #1 8003ffa: 617b str r3, [r7, #20] 8003ffc: 697a ldr r2, [r7, #20] 8003ffe: 687b ldr r3, [r7, #4] 8004000: 429a cmp r2, r3 8004002: dbf1 blt.n 8003fe8 <_write+0x12> } return len; 8004004: 687b ldr r3, [r7, #4] } 8004006: 4618 mov r0, r3 8004008: 3718 adds r7, #24 800400a: 46bd mov sp, r7 800400c: bd80 pop {r7, pc} 0800400e <_close>: int _close(int file) { 800400e: b480 push {r7} 8004010: b083 sub sp, #12 8004012: af00 add r7, sp, #0 8004014: 6078 str r0, [r7, #4] (void)file; return -1; 8004016: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff } 800401a: 4618 mov r0, r3 800401c: 370c adds r7, #12 800401e: 46bd mov sp, r7 8004020: f85d 7b04 ldr.w r7, [sp], #4 8004024: 4770 bx lr 08004026 <_fstat>: int _fstat(int file, struct stat *st) { 8004026: b480 push {r7} 8004028: b083 sub sp, #12 800402a: af00 add r7, sp, #0 800402c: 6078 str r0, [r7, #4] 800402e: 6039 str r1, [r7, #0] (void)file; st->st_mode = S_IFCHR; 8004030: 683b ldr r3, [r7, #0] 8004032: f44f 5200 mov.w r2, #8192 @ 0x2000 8004036: 605a str r2, [r3, #4] return 0; 8004038: 2300 movs r3, #0 } 800403a: 4618 mov r0, r3 800403c: 370c adds r7, #12 800403e: 46bd mov sp, r7 8004040: f85d 7b04 ldr.w r7, [sp], #4 8004044: 4770 bx lr 08004046 <_isatty>: int _isatty(int file) { 8004046: b480 push {r7} 8004048: b083 sub sp, #12 800404a: af00 add r7, sp, #0 800404c: 6078 str r0, [r7, #4] (void)file; return 1; 800404e: 2301 movs r3, #1 } 8004050: 4618 mov r0, r3 8004052: 370c adds r7, #12 8004054: 46bd mov sp, r7 8004056: f85d 7b04 ldr.w r7, [sp], #4 800405a: 4770 bx lr 0800405c <_lseek>: int _lseek(int file, int ptr, int dir) { 800405c: b480 push {r7} 800405e: b085 sub sp, #20 8004060: af00 add r7, sp, #0 8004062: 60f8 str r0, [r7, #12] 8004064: 60b9 str r1, [r7, #8] 8004066: 607a str r2, [r7, #4] (void)file; (void)ptr; (void)dir; return 0; 8004068: 2300 movs r3, #0 } 800406a: 4618 mov r0, r3 800406c: 3714 adds r7, #20 800406e: 46bd mov sp, r7 8004070: f85d 7b04 ldr.w r7, [sp], #4 8004074: 4770 bx lr ... 08004078 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { 8004078: b580 push {r7, lr} 800407a: b086 sub sp, #24 800407c: af00 add r7, sp, #0 800407e: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 8004080: 4a14 ldr r2, [pc, #80] @ (80040d4 <_sbrk+0x5c>) 8004082: 4b15 ldr r3, [pc, #84] @ (80040d8 <_sbrk+0x60>) 8004084: 1ad3 subs r3, r2, r3 8004086: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; 8004088: 697b ldr r3, [r7, #20] 800408a: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) 800408c: 4b13 ldr r3, [pc, #76] @ (80040dc <_sbrk+0x64>) 800408e: 681b ldr r3, [r3, #0] 8004090: 2b00 cmp r3, #0 8004092: d102 bne.n 800409a <_sbrk+0x22> { __sbrk_heap_end = &_end; 8004094: 4b11 ldr r3, [pc, #68] @ (80040dc <_sbrk+0x64>) 8004096: 4a12 ldr r2, [pc, #72] @ (80040e0 <_sbrk+0x68>) 8004098: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) 800409a: 4b10 ldr r3, [pc, #64] @ (80040dc <_sbrk+0x64>) 800409c: 681a ldr r2, [r3, #0] 800409e: 687b ldr r3, [r7, #4] 80040a0: 4413 add r3, r2 80040a2: 693a ldr r2, [r7, #16] 80040a4: 429a cmp r2, r3 80040a6: d207 bcs.n 80040b8 <_sbrk+0x40> { errno = ENOMEM; 80040a8: f013 fdfa bl 8017ca0 <__errno> 80040ac: 4603 mov r3, r0 80040ae: 220c movs r2, #12 80040b0: 601a str r2, [r3, #0] return (void *)-1; 80040b2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80040b6: e009 b.n 80040cc <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; 80040b8: 4b08 ldr r3, [pc, #32] @ (80040dc <_sbrk+0x64>) 80040ba: 681b ldr r3, [r3, #0] 80040bc: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; 80040be: 4b07 ldr r3, [pc, #28] @ (80040dc <_sbrk+0x64>) 80040c0: 681a ldr r2, [r3, #0] 80040c2: 687b ldr r3, [r7, #4] 80040c4: 4413 add r3, r2 80040c6: 4a05 ldr r2, [pc, #20] @ (80040dc <_sbrk+0x64>) 80040c8: 6013 str r3, [r2, #0] return (void *)prev_heap_end; 80040ca: 68fb ldr r3, [r7, #12] } 80040cc: 4618 mov r0, r3 80040ce: 3718 adds r7, #24 80040d0: 46bd mov sp, r7 80040d2: bd80 pop {r7, pc} 80040d4: 24060000 .word 0x24060000 80040d8: 00000400 .word 0x00000400 80040dc: 240008b0 .word 0x240008b0 80040e0: 24012de0 .word 0x24012de0 080040e4 : * configuration. * @param None * @retval None */ void SystemInit (void) { 80040e4: b480 push {r7} 80040e6: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 80040e8: 4b37 ldr r3, [pc, #220] @ (80041c8 ) 80040ea: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80040ee: 4a36 ldr r2, [pc, #216] @ (80041c8 ) 80040f0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80040f4: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80040f8: 4b34 ldr r3, [pc, #208] @ (80041cc ) 80040fa: 681b ldr r3, [r3, #0] 80040fc: f003 030f and.w r3, r3, #15 8004100: 2b06 cmp r3, #6 8004102: d807 bhi.n 8004114 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 8004104: 4b31 ldr r3, [pc, #196] @ (80041cc ) 8004106: 681b ldr r3, [r3, #0] 8004108: f023 030f bic.w r3, r3, #15 800410c: 4a2f ldr r2, [pc, #188] @ (80041cc ) 800410e: f043 0307 orr.w r3, r3, #7 8004112: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 8004114: 4b2e ldr r3, [pc, #184] @ (80041d0 ) 8004116: 681b ldr r3, [r3, #0] 8004118: 4a2d ldr r2, [pc, #180] @ (80041d0 ) 800411a: f043 0301 orr.w r3, r3, #1 800411e: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8004120: 4b2b ldr r3, [pc, #172] @ (80041d0 ) 8004122: 2200 movs r2, #0 8004124: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 8004126: 4b2a ldr r3, [pc, #168] @ (80041d0 ) 8004128: 681a ldr r2, [r3, #0] 800412a: 4929 ldr r1, [pc, #164] @ (80041d0 ) 800412c: 4b29 ldr r3, [pc, #164] @ (80041d4 ) 800412e: 4013 ands r3, r2 8004130: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 8004132: 4b26 ldr r3, [pc, #152] @ (80041cc ) 8004134: 681b ldr r3, [r3, #0] 8004136: f003 0308 and.w r3, r3, #8 800413a: 2b00 cmp r3, #0 800413c: d007 beq.n 800414e { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 800413e: 4b23 ldr r3, [pc, #140] @ (80041cc ) 8004140: 681b ldr r3, [r3, #0] 8004142: f023 030f bic.w r3, r3, #15 8004146: 4a21 ldr r2, [pc, #132] @ (80041cc ) 8004148: f043 0307 orr.w r3, r3, #7 800414c: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 800414e: 4b20 ldr r3, [pc, #128] @ (80041d0 ) 8004150: 2200 movs r2, #0 8004152: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 8004154: 4b1e ldr r3, [pc, #120] @ (80041d0 ) 8004156: 2200 movs r2, #0 8004158: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 800415a: 4b1d ldr r3, [pc, #116] @ (80041d0 ) 800415c: 2200 movs r2, #0 800415e: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8004160: 4b1b ldr r3, [pc, #108] @ (80041d0 ) 8004162: 4a1d ldr r2, [pc, #116] @ (80041d8 ) 8004164: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8004166: 4b1a ldr r3, [pc, #104] @ (80041d0 ) 8004168: 4a1c ldr r2, [pc, #112] @ (80041dc ) 800416a: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 800416c: 4b18 ldr r3, [pc, #96] @ (80041d0 ) 800416e: 4a1c ldr r2, [pc, #112] @ (80041e0 ) 8004170: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 8004172: 4b17 ldr r3, [pc, #92] @ (80041d0 ) 8004174: 2200 movs r2, #0 8004176: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8004178: 4b15 ldr r3, [pc, #84] @ (80041d0 ) 800417a: 4a19 ldr r2, [pc, #100] @ (80041e0 ) 800417c: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 800417e: 4b14 ldr r3, [pc, #80] @ (80041d0 ) 8004180: 2200 movs r2, #0 8004182: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 8004184: 4b12 ldr r3, [pc, #72] @ (80041d0 ) 8004186: 4a16 ldr r2, [pc, #88] @ (80041e0 ) 8004188: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 800418a: 4b11 ldr r3, [pc, #68] @ (80041d0 ) 800418c: 2200 movs r2, #0 800418e: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8004190: 4b0f ldr r3, [pc, #60] @ (80041d0 ) 8004192: 681b ldr r3, [r3, #0] 8004194: 4a0e ldr r2, [pc, #56] @ (80041d0 ) 8004196: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800419a: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 800419c: 4b0c ldr r3, [pc, #48] @ (80041d0 ) 800419e: 2200 movs r2, #0 80041a0: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 80041a2: 4b10 ldr r3, [pc, #64] @ (80041e4 ) 80041a4: 681a ldr r2, [r3, #0] 80041a6: 4b10 ldr r3, [pc, #64] @ (80041e8 ) 80041a8: 4013 ands r3, r2 80041aa: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80041ae: d202 bcs.n 80041b6 { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 80041b0: 4b0e ldr r3, [pc, #56] @ (80041ec ) 80041b2: 2201 movs r2, #1 80041b4: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 80041b6: 4b0e ldr r3, [pc, #56] @ (80041f0 ) 80041b8: f243 02d2 movw r2, #12498 @ 0x30d2 80041bc: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 80041be: bf00 nop 80041c0: 46bd mov sp, r7 80041c2: f85d 7b04 ldr.w r7, [sp], #4 80041c6: 4770 bx lr 80041c8: e000ed00 .word 0xe000ed00 80041cc: 52002000 .word 0x52002000 80041d0: 58024400 .word 0x58024400 80041d4: eaf6ed7f .word 0xeaf6ed7f 80041d8: 02020200 .word 0x02020200 80041dc: 01ff0000 .word 0x01ff0000 80041e0: 01010280 .word 0x01010280 80041e4: 5c001000 .word 0x5c001000 80041e8: ffff0000 .word 0xffff0000 80041ec: 51008108 .word 0x51008108 80041f0: 52004000 .word 0x52004000 080041f4 : uint32_t slaveLastSeen[SLAVES_COUNT] = { 0 }; extern RNG_HandleTypeDef hrng; void UartTasksInit (void) { 80041f4: b580 push {r7, lr} 80041f6: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 80041f8: 4b13 ldr r3, [pc, #76] @ (8004248 ) 80041fa: 4a14 ldr r2, [pc, #80] @ (800424c ) 80041fc: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 80041fe: 4b12 ldr r3, [pc, #72] @ (8004248 ) 8004200: f44f 7280 mov.w r2, #256 @ 0x100 8004204: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 8004206: 4b10 ldr r3, [pc, #64] @ (8004248 ) 8004208: 4a11 ldr r2, [pc, #68] @ (8004250 ) 800420a: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 800420c: 4b0e ldr r3, [pc, #56] @ (8004248 ) 800420e: f44f 7280 mov.w r2, #256 @ 0x100 8004212: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 8004214: 4b0c ldr r3, [pc, #48] @ (8004248 ) 8004216: 4a0f ldr r2, [pc, #60] @ (8004254 ) 8004218: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 800421a: 4b0b ldr r3, [pc, #44] @ (8004248 ) 800421c: f44f 7280 mov.w r2, #256 @ 0x100 8004220: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 8004222: 4b09 ldr r3, [pc, #36] @ (8004248 ) 8004224: 4a0c ldr r2, [pc, #48] @ (8004258 ) 8004226: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 8004228: 4b07 ldr r3, [pc, #28] @ (8004248 ) 800422a: 2201 movs r2, #1 800422c: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 8004230: 4b05 ldr r3, [pc, #20] @ (8004248 ) 8004232: 4a0a ldr r2, [pc, #40] @ (800425c ) 8004234: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 8004236: 4b04 ldr r3, [pc, #16] @ (8004248 ) 8004238: 2200 movs r2, #0 800423a: 625a str r2, [r3, #36] @ 0x24 UartTaskCreate (&uart1TaskData); 800423c: 4802 ldr r0, [pc, #8] @ (8004248 ) 800423e: f000 f80f bl 8004260 } 8004242: bf00 nop 8004244: bd80 pop {r7, pc} 8004246: bf00 nop 8004248: 24000bb4 .word 0x24000bb4 800424c: 240008b4 .word 0x240008b4 8004250: 240009b4 .word 0x240009b4 8004254: 24000ab4 .word 0x24000ab4 8004258: 24000610 .word 0x24000610 800425c: 08004965 .word 0x08004965 08004260 : void UartTaskCreate (UartTaskData* uartTaskData) { 8004260: b580 push {r7, lr} 8004262: b08c sub sp, #48 @ 0x30 8004264: af00 add r7, sp, #0 8004266: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8004268: f107 030c add.w r3, r7, #12 800426c: 2224 movs r2, #36 @ 0x24 800426e: 2100 movs r1, #0 8004270: 4618 mov r0, r3 8004272: f013 fc70 bl 8017b56 osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8004276: f44f 6380 mov.w r3, #1024 @ 0x400 800427a: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 800427c: 2328 movs r3, #40 @ 0x28 800427e: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8004280: f107 030c add.w r3, r7, #12 8004284: 461a mov r2, r3 8004286: 6879 ldr r1, [r7, #4] 8004288: 4804 ldr r0, [pc, #16] @ (800429c ) 800428a: f00f f9f9 bl 8013680 800428e: 4602 mov r2, r0 8004290: 687b ldr r3, [r7, #4] 8004292: 619a str r2, [r3, #24] } 8004294: bf00 nop 8004296: 3730 adds r7, #48 @ 0x30 8004298: 46bd mov sp, r7 800429a: bd80 pop {r7, pc} 800429c: 080043b5 .word 0x080043b5 080042a0 : uart8TaskData.huart = &huart8; uart8TaskData.uartNumber = 8; uart8TaskData.uartRecieveTaskHandle = osThreadNew (UartRxTask, &uart8TaskData, &osThreadAttrRxUart); } void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 80042a0: b480 push {r7} 80042a2: b083 sub sp, #12 80042a4: af00 add r7, sp, #0 80042a6: 6078 str r0, [r7, #4] } 80042a8: bf00 nop 80042aa: 370c adds r7, #12 80042ac: 46bd mov sp, r7 80042ae: f85d 7b04 ldr.w r7, [sp], #4 80042b2: 4770 bx lr 080042b4 : void HAL_UARTEx_RxEventCallback (UART_HandleTypeDef* huart, uint16_t Size) { 80042b4: b580 push {r7, lr} 80042b6: b082 sub sp, #8 80042b8: af00 add r7, sp, #0 80042ba: 6078 str r0, [r7, #4] 80042bc: 460b mov r3, r1 80042be: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 80042c0: 687b ldr r3, [r7, #4] 80042c2: 681b ldr r3, [r3, #0] 80042c4: 4a0c ldr r2, [pc, #48] @ (80042f8 ) 80042c6: 4293 cmp r3, r2 80042c8: d106 bne.n 80042d8 HandleUartRxCallback (&uart1TaskData, huart, Size); 80042ca: 887b ldrh r3, [r7, #2] 80042cc: 461a mov r2, r3 80042ce: 6879 ldr r1, [r7, #4] 80042d0: 480a ldr r0, [pc, #40] @ (80042fc ) 80042d2: f000 f823 bl 800431c } else if (huart->Instance == UART8) { HandleUartRxCallback (&uart8TaskData, huart, Size); } } 80042d6: e00a b.n 80042ee } else if (huart->Instance == UART8) { 80042d8: 687b ldr r3, [r7, #4] 80042da: 681b ldr r3, [r3, #0] 80042dc: 4a08 ldr r2, [pc, #32] @ (8004300 ) 80042de: 4293 cmp r3, r2 80042e0: d105 bne.n 80042ee HandleUartRxCallback (&uart8TaskData, huart, Size); 80042e2: 887b ldrh r3, [r7, #2] 80042e4: 461a mov r2, r3 80042e6: 6879 ldr r1, [r7, #4] 80042e8: 4806 ldr r0, [pc, #24] @ (8004304 ) 80042ea: f000 f817 bl 800431c } 80042ee: bf00 nop 80042f0: 3708 adds r7, #8 80042f2: 46bd mov sp, r7 80042f4: bd80 pop {r7, pc} 80042f6: bf00 nop 80042f8: 40011000 .word 0x40011000 80042fc: 24000bb4 .word 0x24000bb4 8004300: 40007c00 .word 0x40007c00 8004304: 24000bec .word 0x24000bec 08004308 : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 8004308: b480 push {r7} 800430a: b083 sub sp, #12 800430c: af00 add r7, sp, #0 800430e: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 8004310: bf00 nop 8004312: 370c adds r7, #12 8004314: 46bd mov sp, r7 8004316: f85d 7b04 ldr.w r7, [sp], #4 800431a: 4770 bx lr 0800431c : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 800431c: b580 push {r7, lr} 800431e: b088 sub sp, #32 8004320: af02 add r7, sp, #8 8004322: 60f8 str r0, [r7, #12] 8004324: 60b9 str r1, [r7, #8] 8004326: 4613 mov r3, r2 8004328: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 800432a: 2300 movs r3, #0 800432c: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 800432e: 68fb ldr r3, [r7, #12] 8004330: 6a1b ldr r3, [r3, #32] 8004332: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004336: 4618 mov r0, r3 8004338: f00f fbcd bl 8013ad6 memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 800433c: 68fb ldr r3, [r7, #12] 800433e: 691b ldr r3, [r3, #16] 8004340: 68fa ldr r2, [r7, #12] 8004342: 8ad2 ldrh r2, [r2, #22] 8004344: 1898 adds r0, r3, r2 8004346: 68fb ldr r3, [r7, #12] 8004348: 681b ldr r3, [r3, #0] 800434a: 88fa ldrh r2, [r7, #6] 800434c: 4619 mov r1, r3 800434e: f013 fcd4 bl 8017cfa uartTaskData->frameBytesCount += Size; 8004352: 68fb ldr r3, [r7, #12] 8004354: 8ada ldrh r2, [r3, #22] 8004356: 88fb ldrh r3, [r7, #6] 8004358: 4413 add r3, r2 800435a: b29a uxth r2, r3 800435c: 68fb ldr r3, [r7, #12] 800435e: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004360: 68fb ldr r3, [r7, #12] 8004362: 6a1b ldr r3, [r3, #32] 8004364: 4618 mov r0, r3 8004366: f00f fc01 bl 8013b6c xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 800436a: 68fb ldr r3, [r7, #12] 800436c: 6998 ldr r0, [r3, #24] 800436e: 88f9 ldrh r1, [r7, #6] 8004370: f107 0314 add.w r3, r7, #20 8004374: 9300 str r3, [sp, #0] 8004376: 2300 movs r3, #0 8004378: 2203 movs r2, #3 800437a: f012 f8f1 bl 8016560 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 800437e: 68fb ldr r3, [r7, #12] 8004380: 6b18 ldr r0, [r3, #48] @ 0x30 8004382: 68fb ldr r3, [r7, #12] 8004384: 6819 ldr r1, [r3, #0] 8004386: 68fb ldr r3, [r7, #12] 8004388: 889b ldrh r3, [r3, #4] 800438a: 461a mov r2, r3 800438c: f00f f84b bl 8013426 portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8004390: 697b ldr r3, [r7, #20] 8004392: 2b00 cmp r3, #0 8004394: d007 beq.n 80043a6 8004396: 4b06 ldr r3, [pc, #24] @ (80043b0 ) 8004398: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800439c: 601a str r2, [r3, #0] 800439e: f3bf 8f4f dsb sy 80043a2: f3bf 8f6f isb sy } 80043a6: bf00 nop 80043a8: 3718 adds r7, #24 80043aa: 46bd mov sp, r7 80043ac: bd80 pop {r7, pc} 80043ae: bf00 nop 80043b0: e000ed04 .word 0xe000ed04 080043b4 : void UartRxTask (void* argument) { 80043b4: b580 push {r7, lr} 80043b6: b0d2 sub sp, #328 @ 0x148 80043b8: af02 add r7, sp, #8 80043ba: f507 73a0 add.w r3, r7, #320 @ 0x140 80043be: f5a3 739e sub.w r3, r3, #316 @ 0x13c 80043c2: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 80043c4: f507 73a0 add.w r3, r7, #320 @ 0x140 80043c8: f5a3 739e sub.w r3, r3, #316 @ 0x13c 80043cc: 681b ldr r3, [r3, #0] 80043ce: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 80043d2: f507 73a0 add.w r3, r7, #320 @ 0x140 80043d6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80043da: 4618 mov r0, r3 80043dc: f44f 7386 mov.w r3, #268 @ 0x10c 80043e0: 461a mov r2, r3 80043e2: 2100 movs r1, #0 80043e4: f013 fbb7 bl 8017b56 uint32_t bytesRec = 0; 80043e8: f507 73a0 add.w r3, r7, #320 @ 0x140 80043ec: f5a3 739a sub.w r3, r3, #308 @ 0x134 80043f0: 2200 movs r2, #0 80043f2: 601a str r2, [r3, #0] uint32_t crc = 0; 80043f4: 2300 movs r3, #0 80043f6: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 80043fa: 2300 movs r3, #0 80043fc: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 8004400: 2300 movs r3, #0 8004402: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 8004406: 2300 movs r3, #0 8004408: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 800440c: 2300 movs r3, #0 800440e: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 8004412: 2300 movs r3, #0 8004414: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 8004418: 2300 movs r3, #0 800441a: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 800441e: 2300 movs r3, #0 8004420: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 8004424: 2300 movs r3, #0 8004426: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 800442a: 2300 movs r3, #0 800442c: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8004430: 2000 movs r0, #0 8004432: f00f faca bl 80139ca 8004436: 4602 mov r2, r0 8004438: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800443c: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 800443e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004442: 6b18 ldr r0, [r3, #48] @ 0x30 8004444: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004448: 6819 ldr r1, [r3, #0] 800444a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800444e: 889b ldrh r3, [r3, #4] 8004450: 461a mov r2, r3 8004452: f00e ffe8 bl 8013426 while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004456: f107 020c add.w r2, r7, #12 800445a: f44f 63fa mov.w r3, #2000 @ 0x7d0 800445e: 2100 movs r1, #0 8004460: 2000 movs r0, #0 8004462: f011 ff5b bl 801631c 8004466: 4603 mov r3, r0 8004468: 2b00 cmp r3, #0 800446a: bf0c ite eq 800446c: 2301 moveq r3, #1 800446e: 2300 movne r3, #0 8004470: b2db uxtb r3, r3 8004472: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004476: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800447a: 6a1b ldr r3, [r3, #32] 800447c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004480: 4618 mov r0, r3 8004482: f00f fb28 bl 8013ad6 frameBytesCount = uartTaskData->frameBytesCount; 8004486: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800448a: 8adb ldrh r3, [r3, #22] 800448c: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004490: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004494: 6a1b ldr r3, [r3, #32] 8004496: 4618 mov r0, r3 8004498: f00f fb68 bl 8013b6c if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 800449c: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 80044a0: 2b01 cmp r3, #1 80044a2: d10a bne.n 80044ba 80044a4: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 80044a8: 2b00 cmp r3, #0 80044aa: d006 beq.n 80044ba receverState = srFail; 80044ac: 2304 movs r3, #4 80044ae: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 80044b2: 2301 movs r3, #1 80044b4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 80044b8: e029 b.n 800450e } else { if (frameTimeout == pdFALSE) { 80044ba: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 80044be: 2b00 cmp r3, #0 80044c0: d111 bne.n 80044e6 proceed = pdTRUE; 80044c2: 2301 movs r3, #1 80044c4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); 80044c8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80044cc: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 80044d0: 4619 mov r1, r3 80044d2: f507 73a0 add.w r3, r7, #320 @ 0x140 80044d6: f5a3 739a sub.w r3, r3, #308 @ 0x134 80044da: 681b ldr r3, [r3, #0] 80044dc: 461a mov r2, r3 80044de: 48c1 ldr r0, [pc, #772] @ (80047e4 ) 80044e0: f013 fae4 bl 8017aac 80044e4: e22f b.n 8004946 } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 80044e6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80044ea: 6b1b ldr r3, [r3, #48] @ 0x30 80044ec: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80044f0: 2b20 cmp r3, #32 80044f2: f040 8228 bne.w 8004946 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 80044f6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80044fa: 6b18 ldr r0, [r3, #48] @ 0x30 80044fc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004500: 6819 ldr r1, [r3, #0] 8004502: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004506: 889b ldrh r3, [r3, #4] 8004508: 461a mov r2, r3 800450a: f00e ff8c bl 8013426 } } } while (proceed) { 800450e: e21a b.n 8004946 switch (receverState) { 8004510: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 8004514: 2b04 cmp r3, #4 8004516: f200 81f1 bhi.w 80048fc 800451a: a201 add r2, pc, #4 @ (adr r2, 8004520 ) 800451c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004520: 08004535 .word 0x08004535 8004524: 08004697 .word 0x08004697 8004528: 0800467b .word 0x0800467b 800452c: 08004737 .word 0x08004737 8004530: 080047f1 .word 0x080047f1 case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004534: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004538: 6a1b ldr r3, [r3, #32] 800453a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800453e: 4618 mov r0, r3 8004540: f00f fac9 bl 8013ad6 if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 8004544: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004548: 691b ldr r3, [r3, #16] 800454a: 781b ldrb r3, [r3, #0] 800454c: 2baa cmp r3, #170 @ 0xaa 800454e: f040 8082 bne.w 8004656 if (frameBytesCount > FRAME_ID_LENGTH) { 8004552: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004556: 2b02 cmp r3, #2 8004558: d914 bls.n 8004584 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 800455a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800455e: 691b ldr r3, [r3, #16] 8004560: 3302 adds r3, #2 8004562: 781b ldrb r3, [r3, #0] 8004564: 021b lsls r3, r3, #8 8004566: b21a sxth r2, r3 8004568: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800456c: 691b ldr r3, [r3, #16] 800456e: 3301 adds r3, #1 8004570: 781b ldrb r3, [r3, #0] 8004572: b21b sxth r3, r3 8004574: 4313 orrs r3, r2 8004576: b21b sxth r3, r3 8004578: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 800457a: f507 73a0 add.w r3, r7, #320 @ 0x140 800457e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004582: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8004584: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004588: 2b04 cmp r3, #4 800458a: d923 bls.n 80045d4 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 800458c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004590: 691b ldr r3, [r3, #16] 8004592: 3304 adds r3, #4 8004594: 781b ldrb r3, [r3, #0] 8004596: 021b lsls r3, r3, #8 8004598: b21a sxth r2, r3 800459a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800459e: 691b ldr r3, [r3, #16] 80045a0: 3303 adds r3, #3 80045a2: 781b ldrb r3, [r3, #0] 80045a4: b21b sxth r3, r3 80045a6: 4313 orrs r3, r2 80045a8: b21b sxth r3, r3 80045aa: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 80045ae: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 80045b2: b2da uxtb r2, r3 80045b4: f507 73a0 add.w r3, r7, #320 @ 0x140 80045b8: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80045bc: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 80045be: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 80045c2: 13db asrs r3, r3, #15 80045c4: b21b sxth r3, r3 80045c6: f003 0201 and.w r2, r3, #1 80045ca: f507 73a0 add.w r3, r7, #320 @ 0x140 80045ce: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80045d2: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 80045d4: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 80045d8: 2b05 cmp r3, #5 80045da: d913 bls.n 8004604 80045dc: f507 73a0 add.w r3, r7, #320 @ 0x140 80045e0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80045e4: 789b ldrb r3, [r3, #2] 80045e6: f403 4300 and.w r3, r3, #32768 @ 0x8000 80045ea: 2b00 cmp r3, #0 80045ec: d00a beq.n 8004604 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 80045ee: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80045f2: 691b ldr r3, [r3, #16] 80045f4: 3305 adds r3, #5 80045f6: 781b ldrb r3, [r3, #0] 80045f8: b25a sxtb r2, r3 80045fa: f507 73a0 add.w r3, r7, #320 @ 0x140 80045fe: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004602: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8004604: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004608: 2b07 cmp r3, #7 800460a: d920 bls.n 800464e spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 800460c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004610: 691b ldr r3, [r3, #16] 8004612: 3306 adds r3, #6 8004614: 781b ldrb r3, [r3, #0] 8004616: 021b lsls r3, r3, #8 8004618: b21a sxth r2, r3 800461a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800461e: 691b ldr r3, [r3, #16] 8004620: 3305 adds r3, #5 8004622: 781b ldrb r3, [r3, #0] 8004624: b21b sxth r3, r3 8004626: 4313 orrs r3, r2 8004628: b21b sxth r3, r3 800462a: b29a uxth r2, r3 800462c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004630: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004634: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8004636: f507 73a0 add.w r3, r7, #320 @ 0x140 800463a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800463e: 889b ldrh r3, [r3, #4] 8004640: 330a adds r3, #10 8004642: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 8004646: 2302 movs r3, #2 8004648: f887 3133 strb.w r3, [r7, #307] @ 0x133 800464c: e00e b.n 800466c } else { proceed = pdFALSE; 800464e: 2300 movs r3, #0 8004650: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004654: e00a b.n 800466c } } else { if (frameBytesCount > 0) { 8004656: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 800465a: 2b00 cmp r3, #0 800465c: d003 beq.n 8004666 receverState = srFail; 800465e: 2304 movs r3, #4 8004660: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004664: e002 b.n 800466c } else { proceed = pdFALSE; 8004666: 2300 movs r3, #0 8004668: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 800466c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004670: 6a1b ldr r3, [r3, #32] 8004672: 4618 mov r0, r3 8004674: f00f fa7a bl 8013b6c break; 8004678: e165 b.n 8004946 case srRecieveData: if (frameBytesCount >= frameTotalLength) { 800467a: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 800467e: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004682: 429a cmp r2, r3 8004684: d303 bcc.n 800468e receverState = srCheckCrc; 8004686: 2301 movs r3, #1 8004688: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 800468c: e15b b.n 8004946 proceed = pdFALSE; 800468e: 2300 movs r3, #0 8004690: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004694: e157 b.n 8004946 case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004696: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800469a: 6a1b ldr r3, [r3, #32] 800469c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80046a0: 4618 mov r0, r3 80046a2: f00f fa18 bl 8013ad6 frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 80046a6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80046aa: 691a ldr r2, [r3, #16] 80046ac: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 80046b0: 3b01 subs r3, #1 80046b2: 4413 add r3, r2 80046b4: 781b ldrb r3, [r3, #0] 80046b6: 021b lsls r3, r3, #8 80046b8: b21a sxth r2, r3 80046ba: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80046be: 6919 ldr r1, [r3, #16] 80046c0: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 80046c4: 3b02 subs r3, #2 80046c6: 440b add r3, r1 80046c8: 781b ldrb r3, [r3, #0] 80046ca: b21b sxth r3, r3 80046cc: 4313 orrs r3, r2 80046ce: b21b sxth r3, r3 80046d0: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 80046d4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80046d8: 6919 ldr r1, [r3, #16] 80046da: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 80046de: 3b02 subs r3, #2 80046e0: 461a mov r2, r3 80046e2: 4841 ldr r0, [pc, #260] @ (80047e8 ) 80046e4: f002 fe24 bl 8007330 80046e8: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 80046ec: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80046f0: 6a1b ldr r3, [r3, #32] 80046f2: 4618 mov r0, r3 80046f4: f00f fa3a bl 8013b6c crcPass = frameCrc == crc; 80046f8: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 80046fc: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 8004700: 429a cmp r2, r3 8004702: bf0c ite eq 8004704: 2301 moveq r3, #1 8004706: 2300 movne r3, #0 8004708: b2db uxtb r3, r3 800470a: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 800470e: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004712: 2b00 cmp r3, #0 8004714: d00b beq.n 800472e printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); 8004716: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800471a: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 800471e: 4619 mov r1, r3 8004720: 4832 ldr r0, [pc, #200] @ (80047ec ) 8004722: f013 f9c3 bl 8017aac receverState = srExecuteCmd; 8004726: 2303 movs r3, #3 8004728: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 800472c: e10b b.n 8004946 receverState = srFail; 800472e: 2304 movs r3, #4 8004730: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004734: e107 b.n 8004946 case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 8004736: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800473a: 6a9b ldr r3, [r3, #40] @ 0x28 800473c: 2b00 cmp r3, #0 800473e: d104 bne.n 800474a 8004740: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004744: 6a5b ldr r3, [r3, #36] @ 0x24 8004746: 2b00 cmp r3, #0 8004748: d01e beq.n 8004788 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 800474a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800474e: 6a1b ldr r3, [r3, #32] 8004750: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004754: 4618 mov r0, r3 8004756: f00f f9be bl 8013ad6 memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 800475a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800475e: 691b ldr r3, [r3, #16] 8004760: f103 0108 add.w r1, r3, #8 8004764: f507 73a0 add.w r3, r7, #320 @ 0x140 8004768: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800476c: 889b ldrh r3, [r3, #4] 800476e: 461a mov r2, r3 8004770: f107 0310 add.w r3, r7, #16 8004774: 330c adds r3, #12 8004776: 4618 mov r0, r3 8004778: f013 fabf bl 8017cfa osMutexRelease (uartTaskData->rxDataBufferMutex); 800477c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004780: 6a1b ldr r3, [r3, #32] 8004782: 4618 mov r0, r3 8004784: f00f f9f2 bl 8013b6c } if (uartTaskData->processRxDataMsgBuffer != NULL) { 8004788: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800478c: 6a5b ldr r3, [r3, #36] @ 0x24 800478e: 2b00 cmp r3, #0 8004790: d015 beq.n 80047be if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) { 8004792: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004796: 6a58 ldr r0, [r3, #36] @ 0x24 8004798: f507 73a0 add.w r3, r7, #320 @ 0x140 800479c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80047a0: 889b ldrh r3, [r3, #4] 80047a2: f103 020c add.w r2, r3, #12 80047a6: f107 0110 add.w r1, r7, #16 80047aa: 23c8 movs r3, #200 @ 0xc8 80047ac: f010 fc00 bl 8014fb0 80047b0: 4603 mov r3, r0 80047b2: 2b00 cmp r3, #0 80047b4: d103 bne.n 80047be receverState = srFail; 80047b6: 2304 movs r3, #4 80047b8: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 80047bc: e0c3 b.n 8004946 } } if (uartTaskData->processDataCb != NULL) { 80047be: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80047c2: 6a9b ldr r3, [r3, #40] @ 0x28 80047c4: 2b00 cmp r3, #0 80047c6: d008 beq.n 80047da uartTaskData->processDataCb (uartTaskData, &spFrameData); 80047c8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80047cc: 6a9b ldr r3, [r3, #40] @ 0x28 80047ce: f107 0210 add.w r2, r7, #16 80047d2: 4611 mov r1, r2 80047d4: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 80047d8: 4798 blx r3 } receverState = srFinish; 80047da: 2305 movs r3, #5 80047dc: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 80047e0: e0b1 b.n 8004946 80047e2: bf00 nop 80047e4: 080188bc .word 0x080188bc 80047e8: 24000400 .word 0x24000400 80047ec: 080188dc .word 0x080188dc case srFail: dataToSend = 0; 80047f0: 2300 movs r3, #0 80047f2: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 80047f6: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 80047fa: 2b01 cmp r3, #1 80047fc: d124 bne.n 8004848 80047fe: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004802: 2b02 cmp r3, #2 8004804: d920 bls.n 8004848 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8004806: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800480a: 6898 ldr r0, [r3, #8] 800480c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004810: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004814: 8819 ldrh r1, [r3, #0] 8004816: f507 73a0 add.w r3, r7, #320 @ 0x140 800481a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800481e: 789a ldrb r2, [r3, #2] 8004820: 2300 movs r3, #0 8004822: 9301 str r3, [sp, #4] 8004824: 2300 movs r3, #0 8004826: 9300 str r3, [sp, #0] 8004828: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800482c: f7fe fcf0 bl 8003210 8004830: 4603 mov r3, r0 8004832: f8a7 313c strh.w r3, [r7, #316] @ 0x13c printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); 8004836: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800483a: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 800483e: 4619 mov r1, r3 8004840: 4844 ldr r0, [pc, #272] @ (8004954 ) 8004842: f013 f933 bl 8017aac 8004846: e03c b.n 80048c2 } else if (!crcPass) { 8004848: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 800484c: 2b00 cmp r3, #0 800484e: d120 bne.n 8004892 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 8004850: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004854: 6898 ldr r0, [r3, #8] 8004856: f507 73a0 add.w r3, r7, #320 @ 0x140 800485a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800485e: 8819 ldrh r1, [r3, #0] 8004860: f507 73a0 add.w r3, r7, #320 @ 0x140 8004864: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004868: 789a ldrb r2, [r3, #2] 800486a: 2300 movs r3, #0 800486c: 9301 str r3, [sp, #4] 800486e: 2300 movs r3, #0 8004870: 9300 str r3, [sp, #0] 8004872: f06f 0301 mvn.w r3, #1 8004876: f7fe fccb bl 8003210 800487a: 4603 mov r3, r0 800487c: f8a7 313c strh.w r3, [r7, #316] @ 0x13c printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); 8004880: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004884: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8004888: 4619 mov r1, r3 800488a: 4833 ldr r0, [pc, #204] @ (8004958 ) 800488c: f013 f90e bl 8017aac 8004890: e017 b.n 80048c2 } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 8004892: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004896: 6898 ldr r0, [r3, #8] 8004898: f507 73a0 add.w r3, r7, #320 @ 0x140 800489c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80048a0: 8819 ldrh r1, [r3, #0] 80048a2: f507 73a0 add.w r3, r7, #320 @ 0x140 80048a6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80048aa: 789a ldrb r2, [r3, #2] 80048ac: 2300 movs r3, #0 80048ae: 9301 str r3, [sp, #4] 80048b0: 2300 movs r3, #0 80048b2: 9300 str r3, [sp, #0] 80048b4: f06f 0303 mvn.w r3, #3 80048b8: f7fe fcaa bl 8003210 80048bc: 4603 mov r3, r0 80048be: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 80048c2: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 80048c6: 2b00 cmp r3, #0 80048c8: d00a beq.n 80048e0 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 80048ca: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80048ce: 6b18 ldr r0, [r3, #48] @ 0x30 80048d0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80048d4: 689b ldr r3, [r3, #8] 80048d6: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 80048da: 4619 mov r1, r3 80048dc: f00c f8ce bl 8010a7c } printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); 80048e0: f8b7 113c ldrh.w r1, [r7, #316] @ 0x13c 80048e4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80048e8: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 80048ec: 461a mov r2, r3 80048ee: 481b ldr r0, [pc, #108] @ (800495c ) 80048f0: f013 f8dc bl 8017aac receverState = srFinish; 80048f4: 2305 movs r3, #5 80048f6: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 80048fa: e024 b.n 8004946 case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80048fc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004900: 6a1b ldr r3, [r3, #32] 8004902: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004906: 4618 mov r0, r3 8004908: f00f f8e5 bl 8013ad6 uartTaskData->frameBytesCount = 0; 800490c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004910: 2200 movs r2, #0 8004912: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004914: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004918: 6a1b ldr r3, [r3, #32] 800491a: 4618 mov r0, r3 800491c: f00f f926 bl 8013b6c spFrameData.frameHeader.frameCommand = spUnknown; 8004920: f507 73a0 add.w r3, r7, #320 @ 0x140 8004924: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004928: 220f movs r2, #15 800492a: 709a strb r2, [r3, #2] frameTotalLength = 0; 800492c: 2300 movs r3, #0 800492e: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 8004932: 4b0b ldr r3, [pc, #44] @ (8004960 ) 8004934: 2200 movs r2, #0 8004936: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 8004938: 2300 movs r3, #0 800493a: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 800493e: 2300 movs r3, #0 8004940: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004944: bf00 nop while (proceed) { 8004946: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 800494a: 2b00 cmp r3, #0 800494c: f47f ade0 bne.w 8004510 frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004950: e581 b.n 8004456 8004952: bf00 nop 8004954: 080188f4 .word 0x080188f4 8004958: 08018918 .word 0x08018918 800495c: 08018930 .word 0x08018930 8004960: 24000ca4 .word 0x24000ca4 08004964 : void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { Uart1ReceivedDataProcessCallback (arg, spFrameData); } void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8004964: b590 push {r4, r7, lr} 8004966: b0a3 sub sp, #140 @ 0x8c 8004968: af06 add r7, sp, #24 800496a: 6078 str r0, [r7, #4] 800496c: 6039 str r1, [r7, #0] UartTaskData* uartTaskData = (UartTaskData*)arg; 800496e: 687b ldr r3, [r7, #4] 8004970: 64fb str r3, [r7, #76] @ 0x4c uint16_t dataToSend = 0; 8004972: 2300 movs r3, #0 8004974: f8a7 304a strh.w r3, [r7, #74] @ 0x4a outputDataBufferPos = 0; 8004978: 4ba3 ldr r3, [pc, #652] @ (8004c08 ) 800497a: 2200 movs r2, #0 800497c: 801a strh r2, [r3, #0] uint16_t inputDataBufferPos = 0; 800497e: 2300 movs r3, #0 8004980: 86bb strh r3, [r7, #52] @ 0x34 SerialProtocolRespStatus respStatus = spUnknownCommand; 8004982: 23fd movs r3, #253 @ 0xfd 8004984: f887 306f strb.w r3, [r7, #111] @ 0x6f switch (spFrameData->frameHeader.frameCommand) { 8004988: 683b ldr r3, [r7, #0] 800498a: 789b ldrb r3, [r3, #2] 800498c: 2b0e cmp r3, #14 800498e: f200 8473 bhi.w 8005278 8004992: a201 add r2, pc, #4 @ (adr r2, 8004998 ) 8004994: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004998: 080049d5 .word 0x080049d5 800499c: 08004ac3 .word 0x08004ac3 80049a0: 08004c6d .word 0x08004c6d 80049a4: 08004d29 .word 0x08004d29 80049a8: 08004dcb .word 0x08004dcb 80049ac: 08004ee9 .word 0x08004ee9 80049b0: 08004f71 .word 0x08004f71 80049b4: 08004e6d .word 0x08004e6d 80049b8: 08004fc7 .word 0x08004fc7 80049bc: 08005039 .word 0x08005039 80049c0: 08005085 .word 0x08005085 80049c4: 080050d1 .word 0x080050d1 80049c8: 08005133 .word 0x08005133 80049cc: 08005197 .word 0x08005197 80049d0: 080051f9 .word 0x080051f9 case spGetElectricalMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80049d4: 4b8d ldr r3, [pc, #564] @ (8004c0c ) 80049d6: 681b ldr r3, [r3, #0] 80049d8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80049dc: 4618 mov r0, r3 80049de: f00f f87a bl 8013ad6 80049e2: 4603 mov r3, r0 80049e4: 2b00 cmp r3, #0 80049e6: d168 bne.n 8004aba for (int i = 0; i < 3; i++) { 80049e8: 2300 movs r3, #0 80049ea: 66bb str r3, [r7, #104] @ 0x68 80049ec: e00b b.n 8004a06 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 80049ee: 6ebb ldr r3, [r7, #104] @ 0x68 80049f0: 009b lsls r3, r3, #2 80049f2: 4a87 ldr r2, [pc, #540] @ (8004c10 ) 80049f4: 441a add r2, r3 80049f6: 2304 movs r3, #4 80049f8: 4983 ldr r1, [pc, #524] @ (8004c08 ) 80049fa: 4886 ldr r0, [pc, #536] @ (8004c14 ) 80049fc: f7fe fba4 bl 8003148 for (int i = 0; i < 3; i++) { 8004a00: 6ebb ldr r3, [r7, #104] @ 0x68 8004a02: 3301 adds r3, #1 8004a04: 66bb str r3, [r7, #104] @ 0x68 8004a06: 6ebb ldr r3, [r7, #104] @ 0x68 8004a08: 2b02 cmp r3, #2 8004a0a: ddf0 ble.n 80049ee } for (int i = 0; i < 3; i++) { 8004a0c: 2300 movs r3, #0 8004a0e: 667b str r3, [r7, #100] @ 0x64 8004a10: e00d b.n 8004a2e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 8004a12: 6e7b ldr r3, [r7, #100] @ 0x64 8004a14: 3302 adds r3, #2 8004a16: 009b lsls r3, r3, #2 8004a18: 4a7d ldr r2, [pc, #500] @ (8004c10 ) 8004a1a: 4413 add r3, r2 8004a1c: 1d1a adds r2, r3, #4 8004a1e: 2304 movs r3, #4 8004a20: 4979 ldr r1, [pc, #484] @ (8004c08 ) 8004a22: 487c ldr r0, [pc, #496] @ (8004c14 ) 8004a24: f7fe fb90 bl 8003148 for (int i = 0; i < 3; i++) { 8004a28: 6e7b ldr r3, [r7, #100] @ 0x64 8004a2a: 3301 adds r3, #1 8004a2c: 667b str r3, [r7, #100] @ 0x64 8004a2e: 6e7b ldr r3, [r7, #100] @ 0x64 8004a30: 2b02 cmp r3, #2 8004a32: ddee ble.n 8004a12 } for (int i = 0; i < 3; i++) { 8004a34: 2300 movs r3, #0 8004a36: 663b str r3, [r7, #96] @ 0x60 8004a38: e00c b.n 8004a54 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 8004a3a: 6e3b ldr r3, [r7, #96] @ 0x60 8004a3c: 3306 adds r3, #6 8004a3e: 009b lsls r3, r3, #2 8004a40: 4a73 ldr r2, [pc, #460] @ (8004c10 ) 8004a42: 441a add r2, r3 8004a44: 2304 movs r3, #4 8004a46: 4970 ldr r1, [pc, #448] @ (8004c08 ) 8004a48: 4872 ldr r0, [pc, #456] @ (8004c14 ) 8004a4a: f7fe fb7d bl 8003148 for (int i = 0; i < 3; i++) { 8004a4e: 6e3b ldr r3, [r7, #96] @ 0x60 8004a50: 3301 adds r3, #1 8004a52: 663b str r3, [r7, #96] @ 0x60 8004a54: 6e3b ldr r3, [r7, #96] @ 0x60 8004a56: 2b02 cmp r3, #2 8004a58: ddef ble.n 8004a3a } for (int i = 0; i < 3; i++) { 8004a5a: 2300 movs r3, #0 8004a5c: 65fb str r3, [r7, #92] @ 0x5c 8004a5e: e00d b.n 8004a7c WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 8004a60: 6dfb ldr r3, [r7, #92] @ 0x5c 8004a62: 3308 adds r3, #8 8004a64: 009b lsls r3, r3, #2 8004a66: 4a6a ldr r2, [pc, #424] @ (8004c10 ) 8004a68: 4413 add r3, r2 8004a6a: 1d1a adds r2, r3, #4 8004a6c: 2304 movs r3, #4 8004a6e: 4966 ldr r1, [pc, #408] @ (8004c08 ) 8004a70: 4868 ldr r0, [pc, #416] @ (8004c14 ) 8004a72: f7fe fb69 bl 8003148 for (int i = 0; i < 3; i++) { 8004a76: 6dfb ldr r3, [r7, #92] @ 0x5c 8004a78: 3301 adds r3, #1 8004a7a: 65fb str r3, [r7, #92] @ 0x5c 8004a7c: 6dfb ldr r3, [r7, #92] @ 0x5c 8004a7e: 2b02 cmp r3, #2 8004a80: ddee ble.n 8004a60 } for (int i = 0; i < 3; i++) { 8004a82: 2300 movs r3, #0 8004a84: 65bb str r3, [r7, #88] @ 0x58 8004a86: e00c b.n 8004aa2 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 8004a88: 6dbb ldr r3, [r7, #88] @ 0x58 8004a8a: 330c adds r3, #12 8004a8c: 009b lsls r3, r3, #2 8004a8e: 4a60 ldr r2, [pc, #384] @ (8004c10 ) 8004a90: 441a add r2, r3 8004a92: 2304 movs r3, #4 8004a94: 495c ldr r1, [pc, #368] @ (8004c08 ) 8004a96: 485f ldr r0, [pc, #380] @ (8004c14 ) 8004a98: f7fe fb56 bl 8003148 for (int i = 0; i < 3; i++) { 8004a9c: 6dbb ldr r3, [r7, #88] @ 0x58 8004a9e: 3301 adds r3, #1 8004aa0: 65bb str r3, [r7, #88] @ 0x58 8004aa2: 6dbb ldr r3, [r7, #88] @ 0x58 8004aa4: 2b02 cmp r3, #2 8004aa6: ddef ble.n 8004a88 } osMutexRelease (resMeasurementsMutex); 8004aa8: 4b58 ldr r3, [pc, #352] @ (8004c0c ) 8004aaa: 681b ldr r3, [r3, #0] 8004aac: 4618 mov r0, r3 8004aae: f00f f85d bl 8013b6c respStatus = spOK; 8004ab2: 2300 movs r3, #0 8004ab4: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 8004ab8: e3e2 b.n 8005280 respStatus = spInternalError; 8004aba: 23fc movs r3, #252 @ 0xfc 8004abc: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8004ac0: e3de b.n 8005280 case spGetSensorMeasurments: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8004ac2: 4b55 ldr r3, [pc, #340] @ (8004c18 ) 8004ac4: 681b ldr r3, [r3, #0] 8004ac6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004aca: 4618 mov r0, r3 8004acc: f00f f803 bl 8013ad6 8004ad0: 4603 mov r3, r0 8004ad2: 2b00 cmp r3, #0 8004ad4: f040 8094 bne.w 8004c00 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 8004ad8: 2304 movs r3, #4 8004ada: 4a50 ldr r2, [pc, #320] @ (8004c1c ) 8004adc: 494a ldr r1, [pc, #296] @ (8004c08 ) 8004ade: 484d ldr r0, [pc, #308] @ (8004c14 ) 8004ae0: f7fe fb32 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 8004ae4: 2304 movs r3, #4 8004ae6: 4a4e ldr r2, [pc, #312] @ (8004c20 ) 8004ae8: 4947 ldr r1, [pc, #284] @ (8004c08 ) 8004aea: 484a ldr r0, [pc, #296] @ (8004c14 ) 8004aec: f7fe fb2c bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 8004af0: 2304 movs r3, #4 8004af2: 4a4c ldr r2, [pc, #304] @ (8004c24 ) 8004af4: 4944 ldr r1, [pc, #272] @ (8004c08 ) 8004af6: 4847 ldr r0, [pc, #284] @ (8004c14 ) 8004af8: f7fe fb26 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float)); 8004afc: 2304 movs r3, #4 8004afe: 4a4a ldr r2, [pc, #296] @ (8004c28 ) 8004b00: 4941 ldr r1, [pc, #260] @ (8004c08 ) 8004b02: 4844 ldr r0, [pc, #272] @ (8004c14 ) 8004b04: f7fe fb20 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float)); 8004b08: 2304 movs r3, #4 8004b0a: 4a48 ldr r2, [pc, #288] @ (8004c2c ) 8004b0c: 493e ldr r1, [pc, #248] @ (8004c08 ) 8004b0e: 4841 ldr r0, [pc, #260] @ (8004c14 ) 8004b10: f7fe fb1a bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 8004b14: 2301 movs r3, #1 8004b16: 4a46 ldr r2, [pc, #280] @ (8004c30 ) 8004b18: 493b ldr r1, [pc, #236] @ (8004c08 ) 8004b1a: 483e ldr r0, [pc, #248] @ (8004c14 ) 8004b1c: f7fe fb14 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 8004b20: 2301 movs r3, #1 8004b22: 4a44 ldr r2, [pc, #272] @ (8004c34 ) 8004b24: 4938 ldr r1, [pc, #224] @ (8004c08 ) 8004b26: 483b ldr r0, [pc, #236] @ (8004c14 ) 8004b28: f7fe fb0e bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 8004b2c: 2304 movs r3, #4 8004b2e: 4a42 ldr r2, [pc, #264] @ (8004c38 ) 8004b30: 4935 ldr r1, [pc, #212] @ (8004c08 ) 8004b32: 4838 ldr r0, [pc, #224] @ (8004c14 ) 8004b34: f7fe fb08 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 8004b38: 2304 movs r3, #4 8004b3a: 4a40 ldr r2, [pc, #256] @ (8004c3c ) 8004b3c: 4932 ldr r1, [pc, #200] @ (8004c08 ) 8004b3e: 4835 ldr r0, [pc, #212] @ (8004c14 ) 8004b40: f7fe fb02 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 8004b44: 2304 movs r3, #4 8004b46: 4a3e ldr r2, [pc, #248] @ (8004c40 ) 8004b48: 492f ldr r1, [pc, #188] @ (8004c08 ) 8004b4a: 4832 ldr r0, [pc, #200] @ (8004c14 ) 8004b4c: f7fe fafc bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 8004b50: 2304 movs r3, #4 8004b52: 4a3c ldr r2, [pc, #240] @ (8004c44 ) 8004b54: 492c ldr r1, [pc, #176] @ (8004c08 ) 8004b56: 482f ldr r0, [pc, #188] @ (8004c14 ) 8004b58: f7fe faf6 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 8004b5c: 2301 movs r3, #1 8004b5e: 4a3a ldr r2, [pc, #232] @ (8004c48 ) 8004b60: 4929 ldr r1, [pc, #164] @ (8004c08 ) 8004b62: 482c ldr r0, [pc, #176] @ (8004c14 ) 8004b64: f7fe faf0 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 8004b68: 2301 movs r3, #1 8004b6a: 4a38 ldr r2, [pc, #224] @ (8004c4c ) 8004b6c: 4926 ldr r1, [pc, #152] @ (8004c08 ) 8004b6e: 4829 ldr r0, [pc, #164] @ (8004c14 ) 8004b70: f7fe faea bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 8004b74: 2301 movs r3, #1 8004b76: 4a36 ldr r2, [pc, #216] @ (8004c50 ) 8004b78: 4923 ldr r1, [pc, #140] @ (8004c08 ) 8004b7a: 4826 ldr r0, [pc, #152] @ (8004c14 ) 8004b7c: f7fe fae4 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 8004b80: 2301 movs r3, #1 8004b82: 4a34 ldr r2, [pc, #208] @ (8004c54 ) 8004b84: 4920 ldr r1, [pc, #128] @ (8004c08 ) 8004b86: 4823 ldr r0, [pc, #140] @ (8004c14 ) 8004b88: f7fe fade bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 8004b8c: 2301 movs r3, #1 8004b8e: 4a32 ldr r2, [pc, #200] @ (8004c58 ) 8004b90: 491d ldr r1, [pc, #116] @ (8004c08 ) 8004b92: 4820 ldr r0, [pc, #128] @ (8004c14 ) 8004b94: f7fe fad8 bl 8003148 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 8004b98: 2301 movs r3, #1 8004b9a: 4a30 ldr r2, [pc, #192] @ (8004c5c ) 8004b9c: 491a ldr r1, [pc, #104] @ (8004c08 ) 8004b9e: 481d ldr r0, [pc, #116] @ (8004c14 ) 8004ba0: f7fe fad2 bl 8003148 uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 8004ba4: 482e ldr r0, [pc, #184] @ (8004c60 ) 8004ba6: f002 f9e9 bl 8006f7c 8004baa: 4603 mov r3, r0 8004bac: 2b01 cmp r3, #1 8004bae: bf0c ite eq 8004bb0: 2301 moveq r3, #1 8004bb2: 2300 movne r3, #0 8004bb4: b2db uxtb r3, r3 8004bb6: f887 3037 strb.w r3, [r7, #55] @ 0x37 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 8004bba: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8004bbe: 005c lsls r4, r3, #1 8004bc0: 2108 movs r1, #8 8004bc2: 4828 ldr r0, [pc, #160] @ (8004c64 ) 8004bc4: f005 ff92 bl 800aaec 8004bc8: 4603 mov r3, r0 8004bca: 4323 orrs r3, r4 8004bcc: f003 0301 and.w r3, r3, #1 8004bd0: 2b00 cmp r3, #0 8004bd2: bf0c ite eq 8004bd4: 2301 moveq r3, #1 8004bd6: 2300 movne r3, #0 8004bd8: b2db uxtb r3, r3 8004bda: 461a mov r2, r3 8004bdc: 4b0f ldr r3, [pc, #60] @ (8004c1c ) 8004bde: f883 202e strb.w r2, [r3, #46] @ 0x2e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 8004be2: 2301 movs r3, #1 8004be4: 4a20 ldr r2, [pc, #128] @ (8004c68 ) 8004be6: 4908 ldr r1, [pc, #32] @ (8004c08 ) 8004be8: 480a ldr r0, [pc, #40] @ (8004c14 ) 8004bea: f7fe faad bl 8003148 osMutexRelease (sensorsInfoMutex); 8004bee: 4b0a ldr r3, [pc, #40] @ (8004c18 ) 8004bf0: 681b ldr r3, [r3, #0] 8004bf2: 4618 mov r0, r3 8004bf4: f00e ffba bl 8013b6c respStatus = spOK; 8004bf8: 2300 movs r3, #0 8004bfa: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 8004bfe: e33f b.n 8005280 respStatus = spInternalError; 8004c00: 23fc movs r3, #252 @ 0xfc 8004c02: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8004c06: e33b b.n 8005280 8004c08: 24000ca4 .word 0x24000ca4 8004c0c: 240007e4 .word 0x240007e4 8004c10: 240007f0 .word 0x240007f0 8004c14: 24000c24 .word 0x24000c24 8004c18: 240007e8 .word 0x240007e8 8004c1c: 2400082c .word 0x2400082c 8004c20: 24000830 .word 0x24000830 8004c24: 24000834 .word 0x24000834 8004c28: 24000838 .word 0x24000838 8004c2c: 2400083c .word 0x2400083c 8004c30: 24000840 .word 0x24000840 8004c34: 24000841 .word 0x24000841 8004c38: 24000844 .word 0x24000844 8004c3c: 24000848 .word 0x24000848 8004c40: 2400084c .word 0x2400084c 8004c44: 24000850 .word 0x24000850 8004c48: 24000854 .word 0x24000854 8004c4c: 24000855 .word 0x24000855 8004c50: 24000856 .word 0x24000856 8004c54: 24000857 .word 0x24000857 8004c58: 24000858 .word 0x24000858 8004c5c: 24000859 .word 0x24000859 8004c60: 240003d4 .word 0x240003d4 8004c64: 58020c00 .word 0x58020c00 8004c68: 2400085a .word 0x2400085a case spSetFanSpeed: osTimerStop (fanTimerHandle); 8004c6c: 4bb4 ldr r3, [pc, #720] @ (8004f40 ) 8004c6e: 681b ldr r3, [r3, #0] 8004c70: 4618 mov r0, r3 8004c72: f00e fe73 bl 801395c int32_t fanTimerPeriod = 0; 8004c76: 2300 movs r3, #0 8004c78: 633b str r3, [r7, #48] @ 0x30 uint32_t pulse = 0; 8004c7a: 2300 movs r3, #0 8004c7c: 62fb str r3, [r7, #44] @ 0x2c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 8004c7e: 683b ldr r3, [r7, #0] 8004c80: 330c adds r3, #12 8004c82: f107 022c add.w r2, r7, #44 @ 0x2c 8004c86: f107 0134 add.w r1, r7, #52 @ 0x34 8004c8a: 4618 mov r0, r3 8004c8c: f7fe fa8d bl 80031aa ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 8004c90: 683b ldr r3, [r7, #0] 8004c92: 330c adds r3, #12 8004c94: f107 0230 add.w r2, r7, #48 @ 0x30 8004c98: f107 0134 add.w r1, r7, #52 @ 0x34 8004c9c: 4618 mov r0, r3 8004c9e: f7fe fa84 bl 80031aa fanTimerConfigOC.Pulse = pulse * 10; 8004ca2: 6afa ldr r2, [r7, #44] @ 0x2c 8004ca4: 4613 mov r3, r2 8004ca6: 009b lsls r3, r3, #2 8004ca8: 4413 add r3, r2 8004caa: 005b lsls r3, r3, #1 8004cac: 461a mov r2, r3 8004cae: 4ba5 ldr r3, [pc, #660] @ (8004f44 ) 8004cb0: 605a str r2, [r3, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 8004cb2: 2204 movs r2, #4 8004cb4: 49a3 ldr r1, [pc, #652] @ (8004f44 ) 8004cb6: 48a4 ldr r0, [pc, #656] @ (8004f48 ) 8004cb8: f00a fcc6 bl 800f648 8004cbc: 4603 mov r3, r0 8004cbe: 2b00 cmp r3, #0 8004cc0: d001 beq.n 8004cc6 Error_Handler (); 8004cc2: f7fd f8a5 bl 8001e10 } if (fanTimerPeriod > 0) { 8004cc6: 6b3b ldr r3, [r7, #48] @ 0x30 8004cc8: 2b00 cmp r3, #0 8004cca: dd0f ble.n 8004cec osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 8004ccc: 4b9c ldr r3, [pc, #624] @ (8004f40 ) 8004cce: 681a ldr r2, [r3, #0] 8004cd0: 6b3b ldr r3, [r7, #48] @ 0x30 8004cd2: f44f 717a mov.w r1, #1000 @ 0x3e8 8004cd6: fb01 f303 mul.w r3, r1, r3 8004cda: 4619 mov r1, r3 8004cdc: 4610 mov r0, r2 8004cde: f00e fe0f bl 8013900 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 8004ce2: 2104 movs r1, #4 8004ce4: 4898 ldr r0, [pc, #608] @ (8004f48 ) 8004ce6: f009 ffb5 bl 800ec54 8004cea: e019 b.n 8004d20 } else if (fanTimerPeriod == 0) { 8004cec: 6b3b ldr r3, [r7, #48] @ 0x30 8004cee: 2b00 cmp r3, #0 8004cf0: d109 bne.n 8004d06 osTimerStop (fanTimerHandle); 8004cf2: 4b93 ldr r3, [pc, #588] @ (8004f40 ) 8004cf4: 681b ldr r3, [r3, #0] 8004cf6: 4618 mov r0, r3 8004cf8: f00e fe30 bl 801395c HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 8004cfc: 2104 movs r1, #4 8004cfe: 4892 ldr r0, [pc, #584] @ (8004f48 ) 8004d00: f00a f8b6 bl 800ee70 8004d04: e00c b.n 8004d20 } else if (fanTimerPeriod == -1) { 8004d06: 6b3b ldr r3, [r7, #48] @ 0x30 8004d08: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8004d0c: d108 bne.n 8004d20 osTimerStop (fanTimerHandle); 8004d0e: 4b8c ldr r3, [pc, #560] @ (8004f40 ) 8004d10: 681b ldr r3, [r3, #0] 8004d12: 4618 mov r0, r3 8004d14: f00e fe22 bl 801395c HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 8004d18: 2104 movs r1, #4 8004d1a: 488b ldr r0, [pc, #556] @ (8004f48 ) 8004d1c: f009 ff9a bl 800ec54 } respStatus = spOK; 8004d20: 2300 movs r3, #0 8004d22: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8004d26: e2ab b.n 8005280 case spSetMotorXOn: int32_t motorXPWMPulse = 0; 8004d28: 2300 movs r3, #0 8004d2a: 62bb str r3, [r7, #40] @ 0x28 int32_t motorXTimerPeriod = 0; 8004d2c: 2300 movs r3, #0 8004d2e: 627b str r3, [r7, #36] @ 0x24 uint32_t motorXStatus = 0; 8004d30: 2300 movs r3, #0 8004d32: 63bb str r3, [r7, #56] @ 0x38 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 8004d34: 683b ldr r3, [r7, #0] 8004d36: 330c adds r3, #12 8004d38: f107 0228 add.w r2, r7, #40 @ 0x28 8004d3c: f107 0134 add.w r1, r7, #52 @ 0x34 8004d40: 4618 mov r0, r3 8004d42: f7fe fa32 bl 80031aa ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 8004d46: 683b ldr r3, [r7, #0] 8004d48: 330c adds r3, #12 8004d4a: f107 0224 add.w r2, r7, #36 @ 0x24 8004d4e: f107 0134 add.w r1, r7, #52 @ 0x34 8004d52: 4618 mov r0, r3 8004d54: f7fe fa29 bl 80031aa if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8004d58: 4b7c ldr r3, [pc, #496] @ (8004f4c ) 8004d5a: 681b ldr r3, [r3, #0] 8004d5c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004d60: 4618 mov r0, r3 8004d62: f00e feb8 bl 8013ad6 8004d66: 4603 mov r3, r0 8004d68: 2b00 cmp r3, #0 8004d6a: d12a bne.n 8004dc2 motorXStatus = motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8004d6c: 4b78 ldr r3, [pc, #480] @ (8004f50 ) 8004d6e: 681b ldr r3, [r3, #0] 8004d70: 6aba ldr r2, [r7, #40] @ 0x28 8004d72: 6a79 ldr r1, [r7, #36] @ 0x24 8004d74: 4877 ldr r0, [pc, #476] @ (8004f54 ) 8004d76: f890 0028 ldrb.w r0, [r0, #40] @ 0x28 8004d7a: 4c76 ldr r4, [pc, #472] @ (8004f54 ) 8004d7c: f894 4029 ldrb.w r4, [r4, #41] @ 0x29 8004d80: 9404 str r4, [sp, #16] 8004d82: 9003 str r0, [sp, #12] 8004d84: 9102 str r1, [sp, #8] 8004d86: 9201 str r2, [sp, #4] 8004d88: 9300 str r3, [sp, #0] 8004d8a: 2304 movs r3, #4 8004d8c: 2200 movs r2, #0 8004d8e: 4972 ldr r1, [pc, #456] @ (8004f58 ) 8004d90: 4872 ldr r0, [pc, #456] @ (8004f5c ) 8004d92: f7fe f833 bl 8002dfc 8004d96: 4603 mov r3, r0 motorXStatus = 8004d98: 63bb str r3, [r7, #56] @ 0x38 sensorsInfo.motorXStatus = motorXStatus; 8004d9a: 6bbb ldr r3, [r7, #56] @ 0x38 8004d9c: b2da uxtb r2, r3 8004d9e: 4b6d ldr r3, [pc, #436] @ (8004f54 ) 8004da0: 751a strb r2, [r3, #20] if (motorXStatus == 1) { 8004da2: 6bbb ldr r3, [r7, #56] @ 0x38 8004da4: 2b01 cmp r3, #1 8004da6: d103 bne.n 8004db0 sensorsInfo.motorXPeakCurrent = 0.0; 8004da8: 4b6a ldr r3, [pc, #424] @ (8004f54 ) 8004daa: f04f 0200 mov.w r2, #0 8004dae: 621a str r2, [r3, #32] } osMutexRelease (sensorsInfoMutex); 8004db0: 4b66 ldr r3, [pc, #408] @ (8004f4c ) 8004db2: 681b ldr r3, [r3, #0] 8004db4: 4618 mov r0, r3 8004db6: f00e fed9 bl 8013b6c respStatus = spOK; 8004dba: 2300 movs r3, #0 8004dbc: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 8004dc0: e25e b.n 8005280 respStatus = spInternalError; 8004dc2: 23fc movs r3, #252 @ 0xfc 8004dc4: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8004dc8: e25a b.n 8005280 case spSetMotorYOn: int32_t motorYPWMPulse = 0; 8004dca: 2300 movs r3, #0 8004dcc: 623b str r3, [r7, #32] int32_t motorYTimerPeriod = 0; 8004dce: 2300 movs r3, #0 8004dd0: 61fb str r3, [r7, #28] uint32_t motorYStatus = 0; 8004dd2: 2300 movs r3, #0 8004dd4: 63fb str r3, [r7, #60] @ 0x3c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 8004dd6: 683b ldr r3, [r7, #0] 8004dd8: 330c adds r3, #12 8004dda: f107 0220 add.w r2, r7, #32 8004dde: f107 0134 add.w r1, r7, #52 @ 0x34 8004de2: 4618 mov r0, r3 8004de4: f7fe f9e1 bl 80031aa ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 8004de8: 683b ldr r3, [r7, #0] 8004dea: 330c adds r3, #12 8004dec: f107 021c add.w r2, r7, #28 8004df0: f107 0134 add.w r1, r7, #52 @ 0x34 8004df4: 4618 mov r0, r3 8004df6: f7fe f9d8 bl 80031aa if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8004dfa: 4b54 ldr r3, [pc, #336] @ (8004f4c ) 8004dfc: 681b ldr r3, [r3, #0] 8004dfe: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004e02: 4618 mov r0, r3 8004e04: f00e fe67 bl 8013ad6 8004e08: 4603 mov r3, r0 8004e0a: 2b00 cmp r3, #0 8004e0c: d12a bne.n 8004e64 motorYStatus = motorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8004e0e: 4b54 ldr r3, [pc, #336] @ (8004f60 ) 8004e10: 681b ldr r3, [r3, #0] 8004e12: 6a3a ldr r2, [r7, #32] 8004e14: 69f9 ldr r1, [r7, #28] 8004e16: 484f ldr r0, [pc, #316] @ (8004f54 ) 8004e18: f890 002b ldrb.w r0, [r0, #43] @ 0x2b 8004e1c: 4c4d ldr r4, [pc, #308] @ (8004f54 ) 8004e1e: f894 402c ldrb.w r4, [r4, #44] @ 0x2c 8004e22: 9404 str r4, [sp, #16] 8004e24: 9003 str r0, [sp, #12] 8004e26: 9102 str r1, [sp, #8] 8004e28: 9201 str r2, [sp, #4] 8004e2a: 9300 str r3, [sp, #0] 8004e2c: 230c movs r3, #12 8004e2e: 2208 movs r2, #8 8004e30: 4949 ldr r1, [pc, #292] @ (8004f58 ) 8004e32: 484a ldr r0, [pc, #296] @ (8004f5c ) 8004e34: f7fd ffe2 bl 8002dfc 8004e38: 4603 mov r3, r0 motorYStatus = 8004e3a: 63fb str r3, [r7, #60] @ 0x3c sensorsInfo.motorYStatus = motorYStatus; 8004e3c: 6bfb ldr r3, [r7, #60] @ 0x3c 8004e3e: b2da uxtb r2, r3 8004e40: 4b44 ldr r3, [pc, #272] @ (8004f54 ) 8004e42: 755a strb r2, [r3, #21] if (motorYStatus == 1) { 8004e44: 6bfb ldr r3, [r7, #60] @ 0x3c 8004e46: 2b01 cmp r3, #1 8004e48: d103 bne.n 8004e52 sensorsInfo.motorYPeakCurrent = 0.0; 8004e4a: 4b42 ldr r3, [pc, #264] @ (8004f54 ) 8004e4c: f04f 0200 mov.w r2, #0 8004e50: 625a str r2, [r3, #36] @ 0x24 } osMutexRelease (sensorsInfoMutex); 8004e52: 4b3e ldr r3, [pc, #248] @ (8004f4c ) 8004e54: 681b ldr r3, [r3, #0] 8004e56: 4618 mov r0, r3 8004e58: f00e fe88 bl 8013b6c respStatus = spOK; 8004e5c: 2300 movs r3, #0 8004e5e: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 8004e62: e20d b.n 8005280 respStatus = spInternalError; 8004e64: 23fc movs r3, #252 @ 0xfc 8004e66: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8004e6a: e209 b.n 8005280 case spSetDiodeOn: osTimerStop (debugLedTimerHandle); 8004e6c: 4b3d ldr r3, [pc, #244] @ (8004f64 ) 8004e6e: 681b ldr r3, [r3, #0] 8004e70: 4618 mov r0, r3 8004e72: f00e fd73 bl 801395c int32_t dbgLedTimerPeriod = 0; 8004e76: 2300 movs r3, #0 8004e78: 61bb str r3, [r7, #24] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 8004e7a: 683b ldr r3, [r7, #0] 8004e7c: 330c adds r3, #12 8004e7e: f107 0218 add.w r2, r7, #24 8004e82: f107 0134 add.w r1, r7, #52 @ 0x34 8004e86: 4618 mov r0, r3 8004e88: f7fe f98f bl 80031aa if (dbgLedTimerPeriod > 0) { 8004e8c: 69bb ldr r3, [r7, #24] 8004e8e: 2b00 cmp r3, #0 8004e90: dd0e ble.n 8004eb0 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 8004e92: 4b34 ldr r3, [pc, #208] @ (8004f64 ) 8004e94: 681a ldr r2, [r3, #0] 8004e96: 69bb ldr r3, [r7, #24] 8004e98: f44f 717a mov.w r1, #1000 @ 0x3e8 8004e9c: fb01 f303 mul.w r3, r1, r3 8004ea0: 4619 mov r1, r3 8004ea2: 4610 mov r0, r2 8004ea4: f00e fd2c bl 8013900 DbgLEDOn (DBG_LED1); 8004ea8: 2010 movs r0, #16 8004eaa: f7fd ff19 bl 8002ce0 8004eae: e017 b.n 8004ee0 } else if (dbgLedTimerPeriod == 0) { 8004eb0: 69bb ldr r3, [r7, #24] 8004eb2: 2b00 cmp r3, #0 8004eb4: d108 bne.n 8004ec8 osTimerStop (debugLedTimerHandle); 8004eb6: 4b2b ldr r3, [pc, #172] @ (8004f64 ) 8004eb8: 681b ldr r3, [r3, #0] 8004eba: 4618 mov r0, r3 8004ebc: f00e fd4e bl 801395c DbgLEDOff (DBG_LED1); 8004ec0: 2010 movs r0, #16 8004ec2: f7fd ff1f bl 8002d04 8004ec6: e00b b.n 8004ee0 } else if (dbgLedTimerPeriod == -1) { 8004ec8: 69bb ldr r3, [r7, #24] 8004eca: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8004ece: d107 bne.n 8004ee0 osTimerStop (debugLedTimerHandle); 8004ed0: 4b24 ldr r3, [pc, #144] @ (8004f64 ) 8004ed2: 681b ldr r3, [r3, #0] 8004ed4: 4618 mov r0, r3 8004ed6: f00e fd41 bl 801395c DbgLEDOn (DBG_LED1); 8004eda: 2010 movs r0, #16 8004edc: f7fd ff00 bl 8002ce0 } respStatus = spOK; 8004ee0: 2300 movs r3, #0 8004ee2: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8004ee6: e1cb b.n 8005280 case spSetmotorXMaxCurrent: float motorXMaxCurrent = 0; 8004ee8: f04f 0300 mov.w r3, #0 8004eec: 617b str r3, [r7, #20] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 8004eee: 683b ldr r3, [r7, #0] 8004ef0: 330c adds r3, #12 8004ef2: f107 0214 add.w r2, r7, #20 8004ef6: f107 0134 add.w r1, r7, #52 @ 0x34 8004efa: 4618 mov r0, r3 8004efc: f7fe f955 bl 80031aa uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 8004f00: edd7 7a05 vldr s15, [r7, #20] 8004f04: ed9f 7a19 vldr s14, [pc, #100] @ 8004f6c 8004f08: ee67 7a87 vmul.f32 s15, s15, s14 8004f0c: eeb7 6ae7 vcvt.f64.f32 d6, s15 8004f10: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 8004f14: ee86 7b05 vdiv.f64 d7, d6, d5 8004f18: eefc 7bc7 vcvt.u32.f64 s15, d7 8004f1c: ee17 3a90 vmov r3, s15 8004f20: 643b str r3, [r7, #64] @ 0x40 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 8004f22: 6c3b ldr r3, [r7, #64] @ 0x40 8004f24: 2200 movs r2, #0 8004f26: 2100 movs r1, #0 8004f28: 480f ldr r0, [pc, #60] @ (8004f68 ) 8004f2a: f002 fc72 bl 8007812 HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 8004f2e: 2100 movs r1, #0 8004f30: 480d ldr r0, [pc, #52] @ (8004f68 ) 8004f32: f002 fbc1 bl 80076b8 respStatus = spOK; 8004f36: 2300 movs r3, #0 8004f38: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8004f3c: e1a0 b.n 8005280 8004f3e: bf00 nop 8004f40: 240006d8 .word 0x240006d8 8004f44: 24000768 .word 0x24000768 8004f48: 2400044c .word 0x2400044c 8004f4c: 240007e8 .word 0x240007e8 8004f50: 24000708 .word 0x24000708 8004f54: 2400082c .word 0x2400082c 8004f58: 24000784 .word 0x24000784 8004f5c: 240004e4 .word 0x240004e4 8004f60: 24000738 .word 0x24000738 8004f64: 240006a8 .word 0x240006a8 8004f68: 24000424 .word 0x24000424 8004f6c: 457ff000 .word 0x457ff000 case spSetmotorYMaxCurrent: float motorYMaxCurrent = 0; 8004f70: f04f 0300 mov.w r3, #0 8004f74: 613b str r3, [r7, #16] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 8004f76: 683b ldr r3, [r7, #0] 8004f78: 330c adds r3, #12 8004f7a: f107 0210 add.w r2, r7, #16 8004f7e: f107 0134 add.w r1, r7, #52 @ 0x34 8004f82: 4618 mov r0, r3 8004f84: f7fe f911 bl 80031aa uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 8004f88: edd7 7a04 vldr s15, [r7, #16] 8004f8c: ed1f 7a09 vldr s14, [pc, #-36] @ 8004f6c 8004f90: ee67 7a87 vmul.f32 s15, s15, s14 8004f94: eeb7 6ae7 vcvt.f64.f32 d6, s15 8004f98: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 8004f9c: ee86 7b05 vdiv.f64 d7, d6, d5 8004fa0: eefc 7bc7 vcvt.u32.f64 s15, d7 8004fa4: ee17 3a90 vmov r3, s15 8004fa8: 647b str r3, [r7, #68] @ 0x44 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 8004faa: 6c7b ldr r3, [r7, #68] @ 0x44 8004fac: 2200 movs r2, #0 8004fae: 2110 movs r1, #16 8004fb0: 48aa ldr r0, [pc, #680] @ (800525c ) 8004fb2: f002 fc2e bl 8007812 HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 8004fb6: 2110 movs r1, #16 8004fb8: 48a8 ldr r0, [pc, #672] @ (800525c ) 8004fba: f002 fb7d bl 80076b8 respStatus = spOK; 8004fbe: 2300 movs r3, #0 8004fc0: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8004fc4: e15c b.n 8005280 case spClearPeakMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8004fc6: 4ba6 ldr r3, [pc, #664] @ (8005260 ) 8004fc8: 681b ldr r3, [r3, #0] 8004fca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004fce: 4618 mov r0, r3 8004fd0: f00e fd81 bl 8013ad6 8004fd4: 4603 mov r3, r0 8004fd6: 2b00 cmp r3, #0 8004fd8: d12a bne.n 8005030 for (int i = 0; i < 3; i++) { 8004fda: 2300 movs r3, #0 8004fdc: 657b str r3, [r7, #84] @ 0x54 8004fde: e01b b.n 8005018 resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 8004fe0: 4aa0 ldr r2, [pc, #640] @ (8005264 ) 8004fe2: 6d7b ldr r3, [r7, #84] @ 0x54 8004fe4: 009b lsls r3, r3, #2 8004fe6: 4413 add r3, r2 8004fe8: 681a ldr r2, [r3, #0] 8004fea: 499e ldr r1, [pc, #632] @ (8005264 ) 8004fec: 6d7b ldr r3, [r7, #84] @ 0x54 8004fee: 3302 adds r3, #2 8004ff0: 009b lsls r3, r3, #2 8004ff2: 440b add r3, r1 8004ff4: 3304 adds r3, #4 8004ff6: 601a str r2, [r3, #0] resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 8004ff8: 4a9a ldr r2, [pc, #616] @ (8005264 ) 8004ffa: 6d7b ldr r3, [r7, #84] @ 0x54 8004ffc: 3306 adds r3, #6 8004ffe: 009b lsls r3, r3, #2 8005000: 4413 add r3, r2 8005002: 681a ldr r2, [r3, #0] 8005004: 4997 ldr r1, [pc, #604] @ (8005264 ) 8005006: 6d7b ldr r3, [r7, #84] @ 0x54 8005008: 3308 adds r3, #8 800500a: 009b lsls r3, r3, #2 800500c: 440b add r3, r1 800500e: 3304 adds r3, #4 8005010: 601a str r2, [r3, #0] for (int i = 0; i < 3; i++) { 8005012: 6d7b ldr r3, [r7, #84] @ 0x54 8005014: 3301 adds r3, #1 8005016: 657b str r3, [r7, #84] @ 0x54 8005018: 6d7b ldr r3, [r7, #84] @ 0x54 800501a: 2b02 cmp r3, #2 800501c: dde0 ble.n 8004fe0 } osMutexRelease (resMeasurementsMutex); 800501e: 4b90 ldr r3, [pc, #576] @ (8005260 ) 8005020: 681b ldr r3, [r3, #0] 8005022: 4618 mov r0, r3 8005024: f00e fda2 bl 8013b6c respStatus = spOK; 8005028: 2300 movs r3, #0 800502a: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 800502e: e127 b.n 8005280 respStatus = spInternalError; 8005030: 23fc movs r3, #252 @ 0xfc 8005032: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8005036: e123 b.n 8005280 case spSetEncoderXValue: float enocoderXValue = 0; 8005038: f04f 0300 mov.w r3, #0 800503c: 60fb str r3, [r7, #12] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 800503e: 683b ldr r3, [r7, #0] 8005040: 330c adds r3, #12 8005042: f107 020c add.w r2, r7, #12 8005046: f107 0134 add.w r1, r7, #52 @ 0x34 800504a: 4618 mov r0, r3 800504c: f7fe f8ad bl 80031aa if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005050: 4b85 ldr r3, [pc, #532] @ (8005268 ) 8005052: 681b ldr r3, [r3, #0] 8005054: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005058: 4618 mov r0, r3 800505a: f00e fd3c bl 8013ad6 800505e: 4603 mov r3, r0 8005060: 2b00 cmp r3, #0 8005062: d10b bne.n 800507c sensorsInfo.pvEncoderX = enocoderXValue; 8005064: 68fb ldr r3, [r7, #12] 8005066: 4a81 ldr r2, [pc, #516] @ (800526c ) 8005068: 60d3 str r3, [r2, #12] osMutexRelease (sensorsInfoMutex); 800506a: 4b7f ldr r3, [pc, #508] @ (8005268 ) 800506c: 681b ldr r3, [r3, #0] 800506e: 4618 mov r0, r3 8005070: f00e fd7c bl 8013b6c respStatus = spOK; 8005074: 2300 movs r3, #0 8005076: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 800507a: e101 b.n 8005280 respStatus = spInternalError; 800507c: 23fc movs r3, #252 @ 0xfc 800507e: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8005082: e0fd b.n 8005280 case spSetEncoderYValue: float enocoderYValue = 0; 8005084: f04f 0300 mov.w r3, #0 8005088: 60bb str r3, [r7, #8] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 800508a: 683b ldr r3, [r7, #0] 800508c: 330c adds r3, #12 800508e: f107 0208 add.w r2, r7, #8 8005092: f107 0134 add.w r1, r7, #52 @ 0x34 8005096: 4618 mov r0, r3 8005098: f7fe f887 bl 80031aa if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800509c: 4b72 ldr r3, [pc, #456] @ (8005268 ) 800509e: 681b ldr r3, [r3, #0] 80050a0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80050a4: 4618 mov r0, r3 80050a6: f00e fd16 bl 8013ad6 80050aa: 4603 mov r3, r0 80050ac: 2b00 cmp r3, #0 80050ae: d10b bne.n 80050c8 sensorsInfo.pvEncoderY = enocoderYValue; 80050b0: 68bb ldr r3, [r7, #8] 80050b2: 4a6e ldr r2, [pc, #440] @ (800526c ) 80050b4: 6113 str r3, [r2, #16] osMutexRelease (sensorsInfoMutex); 80050b6: 4b6c ldr r3, [pc, #432] @ (8005268 ) 80050b8: 681b ldr r3, [r3, #0] 80050ba: 4618 mov r0, r3 80050bc: f00e fd56 bl 8013b6c respStatus = spOK; 80050c0: 2300 movs r3, #0 80050c2: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 80050c6: e0db b.n 8005280 respStatus = spInternalError; 80050c8: 23fc movs r3, #252 @ 0xfc 80050ca: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 80050ce: e0d7 b.n 8005280 case spSetVoltageMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80050d0: 4b63 ldr r3, [pc, #396] @ (8005260 ) 80050d2: 681b ldr r3, [r3, #0] 80050d4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80050d8: 4618 mov r0, r3 80050da: f00e fcfc bl 8013ad6 80050de: 4603 mov r3, r0 80050e0: 2b00 cmp r3, #0 80050e2: d122 bne.n 800512a for (uint8_t i = 0; i < 3; i++) { 80050e4: 2300 movs r3, #0 80050e6: f887 3053 strb.w r3, [r7, #83] @ 0x53 80050ea: e011 b.n 8005110 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain); 80050ec: 683b ldr r3, [r7, #0] 80050ee: f103 000c add.w r0, r3, #12 80050f2: f897 3053 ldrb.w r3, [r7, #83] @ 0x53 80050f6: 00db lsls r3, r3, #3 80050f8: 4a5d ldr r2, [pc, #372] @ (8005270 ) 80050fa: 441a add r2, r3 80050fc: f107 0334 add.w r3, r7, #52 @ 0x34 8005100: 4619 mov r1, r3 8005102: f7fe f852 bl 80031aa for (uint8_t i = 0; i < 3; i++) { 8005106: f897 3053 ldrb.w r3, [r7, #83] @ 0x53 800510a: 3301 adds r3, #1 800510c: f887 3053 strb.w r3, [r7, #83] @ 0x53 8005110: f897 3053 ldrb.w r3, [r7, #83] @ 0x53 8005114: 2b02 cmp r3, #2 8005116: d9e9 bls.n 80050ec } osMutexRelease (resMeasurementsMutex); 8005118: 4b51 ldr r3, [pc, #324] @ (8005260 ) 800511a: 681b ldr r3, [r3, #0] 800511c: 4618 mov r0, r3 800511e: f00e fd25 bl 8013b6c respStatus = spOK; 8005122: 2300 movs r3, #0 8005124: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 8005128: e0aa b.n 8005280 respStatus = spInternalError; 800512a: 23fc movs r3, #252 @ 0xfc 800512c: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8005130: e0a6 b.n 8005280 case spSetVoltageMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005132: 4b4b ldr r3, [pc, #300] @ (8005260 ) 8005134: 681b ldr r3, [r3, #0] 8005136: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800513a: 4618 mov r0, r3 800513c: f00e fccb bl 8013ad6 8005140: 4603 mov r3, r0 8005142: 2b00 cmp r3, #0 8005144: d123 bne.n 800518e for (uint8_t i = 0; i < 3; i++) { 8005146: 2300 movs r3, #0 8005148: f887 3052 strb.w r3, [r7, #82] @ 0x52 800514c: e012 b.n 8005174 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset); 800514e: 683b ldr r3, [r7, #0] 8005150: f103 000c add.w r0, r3, #12 8005154: f897 3052 ldrb.w r3, [r7, #82] @ 0x52 8005158: 00db lsls r3, r3, #3 800515a: 4a45 ldr r2, [pc, #276] @ (8005270 ) 800515c: 4413 add r3, r2 800515e: 1d1a adds r2, r3, #4 8005160: f107 0334 add.w r3, r7, #52 @ 0x34 8005164: 4619 mov r1, r3 8005166: f7fe f820 bl 80031aa for (uint8_t i = 0; i < 3; i++) { 800516a: f897 3052 ldrb.w r3, [r7, #82] @ 0x52 800516e: 3301 adds r3, #1 8005170: f887 3052 strb.w r3, [r7, #82] @ 0x52 8005174: f897 3052 ldrb.w r3, [r7, #82] @ 0x52 8005178: 2b02 cmp r3, #2 800517a: d9e8 bls.n 800514e } osMutexRelease (resMeasurementsMutex); 800517c: 4b38 ldr r3, [pc, #224] @ (8005260 ) 800517e: 681b ldr r3, [r3, #0] 8005180: 4618 mov r0, r3 8005182: f00e fcf3 bl 8013b6c respStatus = spOK; 8005186: 2300 movs r3, #0 8005188: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 800518c: e078 b.n 8005280 respStatus = spInternalError; 800518e: 23fc movs r3, #252 @ 0xfc 8005190: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 8005194: e074 b.n 8005280 case spSetCurrentMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005196: 4b32 ldr r3, [pc, #200] @ (8005260 ) 8005198: 681b ldr r3, [r3, #0] 800519a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800519e: 4618 mov r0, r3 80051a0: f00e fc99 bl 8013ad6 80051a4: 4603 mov r3, r0 80051a6: 2b00 cmp r3, #0 80051a8: d122 bne.n 80051f0 for (uint8_t i = 0; i < 3; i++) { 80051aa: 2300 movs r3, #0 80051ac: f887 3051 strb.w r3, [r7, #81] @ 0x51 80051b0: e011 b.n 80051d6 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain); 80051b2: 683b ldr r3, [r7, #0] 80051b4: f103 000c add.w r0, r3, #12 80051b8: f897 3051 ldrb.w r3, [r7, #81] @ 0x51 80051bc: 00db lsls r3, r3, #3 80051be: 4a2d ldr r2, [pc, #180] @ (8005274 ) 80051c0: 441a add r2, r3 80051c2: f107 0334 add.w r3, r7, #52 @ 0x34 80051c6: 4619 mov r1, r3 80051c8: f7fd ffef bl 80031aa for (uint8_t i = 0; i < 3; i++) { 80051cc: f897 3051 ldrb.w r3, [r7, #81] @ 0x51 80051d0: 3301 adds r3, #1 80051d2: f887 3051 strb.w r3, [r7, #81] @ 0x51 80051d6: f897 3051 ldrb.w r3, [r7, #81] @ 0x51 80051da: 2b02 cmp r3, #2 80051dc: d9e9 bls.n 80051b2 } osMutexRelease (resMeasurementsMutex); 80051de: 4b20 ldr r3, [pc, #128] @ (8005260 ) 80051e0: 681b ldr r3, [r3, #0] 80051e2: 4618 mov r0, r3 80051e4: f00e fcc2 bl 8013b6c respStatus = spOK; 80051e8: 2300 movs r3, #0 80051ea: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 80051ee: e047 b.n 8005280 respStatus = spInternalError; 80051f0: 23fc movs r3, #252 @ 0xfc 80051f2: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 80051f6: e043 b.n 8005280 case spSetCurrentMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80051f8: 4b19 ldr r3, [pc, #100] @ (8005260 ) 80051fa: 681b ldr r3, [r3, #0] 80051fc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005200: 4618 mov r0, r3 8005202: f00e fc68 bl 8013ad6 8005206: 4603 mov r3, r0 8005208: 2b00 cmp r3, #0 800520a: d123 bne.n 8005254 for (uint8_t i = 0; i < 3; i++) { 800520c: 2300 movs r3, #0 800520e: f887 3050 strb.w r3, [r7, #80] @ 0x50 8005212: e012 b.n 800523a ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 8005214: 683b ldr r3, [r7, #0] 8005216: f103 000c add.w r0, r3, #12 800521a: f897 3050 ldrb.w r3, [r7, #80] @ 0x50 800521e: 00db lsls r3, r3, #3 8005220: 4a14 ldr r2, [pc, #80] @ (8005274 ) 8005222: 4413 add r3, r2 8005224: 1d1a adds r2, r3, #4 8005226: f107 0334 add.w r3, r7, #52 @ 0x34 800522a: 4619 mov r1, r3 800522c: f7fd ffbd bl 80031aa for (uint8_t i = 0; i < 3; i++) { 8005230: f897 3050 ldrb.w r3, [r7, #80] @ 0x50 8005234: 3301 adds r3, #1 8005236: f887 3050 strb.w r3, [r7, #80] @ 0x50 800523a: f897 3050 ldrb.w r3, [r7, #80] @ 0x50 800523e: 2b02 cmp r3, #2 8005240: d9e8 bls.n 8005214 } osMutexRelease (resMeasurementsMutex); 8005242: 4b07 ldr r3, [pc, #28] @ (8005260 ) 8005244: 681b ldr r3, [r3, #0] 8005246: 4618 mov r0, r3 8005248: f00e fc90 bl 8013b6c respStatus = spOK; 800524c: 2300 movs r3, #0 800524e: f887 306f strb.w r3, [r7, #111] @ 0x6f } else { respStatus = spInternalError; } break; 8005252: e015 b.n 8005280 respStatus = spInternalError; 8005254: 23fc movs r3, #252 @ 0xfc 8005256: f887 306f strb.w r3, [r7, #111] @ 0x6f break; 800525a: e011 b.n 8005280 800525c: 24000424 .word 0x24000424 8005260: 240007e4 .word 0x240007e4 8005264: 240007f0 .word 0x240007f0 8005268: 240007e8 .word 0x240007e8 800526c: 2400082c .word 0x2400082c 8005270: 24000000 .word 0x24000000 8005274: 24000018 .word 0x24000018 default: respStatus = spUnknownCommand; break; 8005278: 23fd movs r3, #253 @ 0xfd 800527a: f887 306f strb.w r3, [r7, #111] @ 0x6f 800527e: bf00 nop } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8005280: 6cfb ldr r3, [r7, #76] @ 0x4c 8005282: 6898 ldr r0, [r3, #8] 8005284: 683b ldr r3, [r7, #0] 8005286: 8819 ldrh r1, [r3, #0] 8005288: 683b ldr r3, [r7, #0] 800528a: 789a ldrb r2, [r3, #2] 800528c: 4b13 ldr r3, [pc, #76] @ (80052dc ) 800528e: 881b ldrh r3, [r3, #0] 8005290: f997 406f ldrsb.w r4, [r7, #111] @ 0x6f 8005294: 9301 str r3, [sp, #4] 8005296: 4b12 ldr r3, [pc, #72] @ (80052e0 ) 8005298: 9300 str r3, [sp, #0] 800529a: 4623 mov r3, r4 800529c: f7fd ffb8 bl 8003210 80052a0: 4603 mov r3, r0 80052a2: f8a7 304a strh.w r3, [r7, #74] @ 0x4a if (dataToSend > 0) { 80052a6: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 80052aa: 2b00 cmp r3, #0 80052ac: d008 beq.n 80052c0 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 80052ae: 6cfb ldr r3, [r7, #76] @ 0x4c 80052b0: 6b18 ldr r0, [r3, #48] @ 0x30 80052b2: 6cfb ldr r3, [r7, #76] @ 0x4c 80052b4: 689b ldr r3, [r3, #8] 80052b6: f8b7 204a ldrh.w r2, [r7, #74] @ 0x4a 80052ba: 4619 mov r1, r3 80052bc: f00b fbde bl 8010a7c } printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); 80052c0: 6cfb ldr r3, [r7, #76] @ 0x4c 80052c2: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 80052c6: 4619 mov r1, r3 80052c8: f8b7 304a ldrh.w r3, [r7, #74] @ 0x4a 80052cc: 461a mov r2, r3 80052ce: 4805 ldr r0, [pc, #20] @ (80052e4 ) 80052d0: f012 fbec bl 8017aac } 80052d4: bf00 nop 80052d6: 3774 adds r7, #116 @ 0x74 80052d8: 46bd mov sp, r7 80052da: bd90 pop {r4, r7, pc} 80052dc: 24000ca4 .word 0x24000ca4 80052e0: 24000c24 .word 0x24000c24 80052e4: 08018930 .word 0x08018930 080052e8 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 80052e8: f8df d034 ldr.w sp, [pc, #52] @ 8005320 /* Call the clock system initialization function.*/ bl SystemInit 80052ec: f7fe fefa bl 80040e4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80052f0: 480c ldr r0, [pc, #48] @ (8005324 ) ldr r1, =_edata 80052f2: 490d ldr r1, [pc, #52] @ (8005328 ) ldr r2, =_sidata 80052f4: 4a0d ldr r2, [pc, #52] @ (800532c ) movs r3, #0 80052f6: 2300 movs r3, #0 b LoopCopyDataInit 80052f8: e002 b.n 8005300 080052fa : CopyDataInit: ldr r4, [r2, r3] 80052fa: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80052fc: 50c4 str r4, [r0, r3] adds r3, r3, #4 80052fe: 3304 adds r3, #4 08005300 : LoopCopyDataInit: adds r4, r0, r3 8005300: 18c4 adds r4, r0, r3 cmp r4, r1 8005302: 428c cmp r4, r1 bcc CopyDataInit 8005304: d3f9 bcc.n 80052fa /* Zero fill the bss segment. */ ldr r2, =_sbss 8005306: 4a0a ldr r2, [pc, #40] @ (8005330 ) ldr r4, =_ebss 8005308: 4c0a ldr r4, [pc, #40] @ (8005334 ) movs r3, #0 800530a: 2300 movs r3, #0 b LoopFillZerobss 800530c: e001 b.n 8005312 0800530e : FillZerobss: str r3, [r2] 800530e: 6013 str r3, [r2, #0] adds r2, r2, #4 8005310: 3204 adds r2, #4 08005312 : LoopFillZerobss: cmp r2, r4 8005312: 42a2 cmp r2, r4 bcc FillZerobss 8005314: d3fb bcc.n 800530e /* Call static constructors */ bl __libc_init_array 8005316: f012 fcc9 bl 8017cac <__libc_init_array> /* Call the application's entry point.*/ bl main 800531a: f7fb f9e7 bl 80006ec
bx lr 800531e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8005320: 24060000 .word 0x24060000 ldr r0, =_sdata 8005324: 24000000 .word 0x24000000 ldr r1, =_edata 8005328: 240000a4 .word 0x240000a4 ldr r2, =_sidata 800532c: 08018a4c .word 0x08018a4c ldr r2, =_sbss 8005330: 240000c0 .word 0x240000c0 ldr r4, =_ebss 8005334: 24012de0 .word 0x24012de0 08005338 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005338: e7fe b.n 8005338 ... 0800533c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 800533c: b580 push {r7, lr} 800533e: b082 sub sp, #8 8005340: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005342: 2003 movs r0, #3 8005344: f001 fee5 bl 8007112 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8005348: f006 fb90 bl 800ba6c 800534c: 4602 mov r2, r0 800534e: 4b15 ldr r3, [pc, #84] @ (80053a4 ) 8005350: 699b ldr r3, [r3, #24] 8005352: 0a1b lsrs r3, r3, #8 8005354: f003 030f and.w r3, r3, #15 8005358: 4913 ldr r1, [pc, #76] @ (80053a8 ) 800535a: 5ccb ldrb r3, [r1, r3] 800535c: f003 031f and.w r3, r3, #31 8005360: fa22 f303 lsr.w r3, r2, r3 8005364: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005366: 4b0f ldr r3, [pc, #60] @ (80053a4 ) 8005368: 699b ldr r3, [r3, #24] 800536a: f003 030f and.w r3, r3, #15 800536e: 4a0e ldr r2, [pc, #56] @ (80053a8 ) 8005370: 5cd3 ldrb r3, [r2, r3] 8005372: f003 031f and.w r3, r3, #31 8005376: 687a ldr r2, [r7, #4] 8005378: fa22 f303 lsr.w r3, r2, r3 800537c: 4a0b ldr r2, [pc, #44] @ (80053ac ) 800537e: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005380: 4a0b ldr r2, [pc, #44] @ (80053b0 ) 8005382: 687b ldr r3, [r7, #4] 8005384: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8005386: 2005 movs r0, #5 8005388: f7fe fd00 bl 8003d8c 800538c: 4603 mov r3, r0 800538e: 2b00 cmp r3, #0 8005390: d001 beq.n 8005396 { return HAL_ERROR; 8005392: 2301 movs r3, #1 8005394: e002 b.n 800539c } /* Init the low level hardware */ HAL_MspInit(); 8005396: f7fd ffd9 bl 800334c /* Return function status */ return HAL_OK; 800539a: 2300 movs r3, #0 } 800539c: 4618 mov r0, r3 800539e: 3708 adds r7, #8 80053a0: 46bd mov sp, r7 80053a2: bd80 pop {r7, pc} 80053a4: 58024400 .word 0x58024400 80053a8: 080189c8 .word 0x080189c8 80053ac: 24000038 .word 0x24000038 80053b0: 24000034 .word 0x24000034 080053b4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80053b4: b480 push {r7} 80053b6: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 80053b8: 4b06 ldr r3, [pc, #24] @ (80053d4 ) 80053ba: 781b ldrb r3, [r3, #0] 80053bc: 461a mov r2, r3 80053be: 4b06 ldr r3, [pc, #24] @ (80053d8 ) 80053c0: 681b ldr r3, [r3, #0] 80053c2: 4413 add r3, r2 80053c4: 4a04 ldr r2, [pc, #16] @ (80053d8 ) 80053c6: 6013 str r3, [r2, #0] } 80053c8: bf00 nop 80053ca: 46bd mov sp, r7 80053cc: f85d 7b04 ldr.w r7, [sp], #4 80053d0: 4770 bx lr 80053d2: bf00 nop 80053d4: 24000040 .word 0x24000040 80053d8: 24000ca8 .word 0x24000ca8 080053dc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80053dc: b480 push {r7} 80053de: af00 add r7, sp, #0 return uwTick; 80053e0: 4b03 ldr r3, [pc, #12] @ (80053f0 ) 80053e2: 681b ldr r3, [r3, #0] } 80053e4: 4618 mov r0, r3 80053e6: 46bd mov sp, r7 80053e8: f85d 7b04 ldr.w r7, [sp], #4 80053ec: 4770 bx lr 80053ee: bf00 nop 80053f0: 24000ca8 .word 0x24000ca8 080053f4 : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 80053f4: b480 push {r7} 80053f6: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 80053f8: 4b03 ldr r3, [pc, #12] @ (8005408 ) 80053fa: 681b ldr r3, [r3, #0] 80053fc: 0c1b lsrs r3, r3, #16 } 80053fe: 4618 mov r0, r3 8005400: 46bd mov sp, r7 8005402: f85d 7b04 ldr.w r7, [sp], #4 8005406: 4770 bx lr 8005408: 5c001000 .word 0x5c001000 0800540c : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 800540c: b480 push {r7} 800540e: b083 sub sp, #12 8005410: af00 add r7, sp, #0 8005412: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 8005414: 4b06 ldr r3, [pc, #24] @ (8005430 ) 8005416: 681b ldr r3, [r3, #0] 8005418: f023 0202 bic.w r2, r3, #2 800541c: 4904 ldr r1, [pc, #16] @ (8005430 ) 800541e: 687b ldr r3, [r7, #4] 8005420: 4313 orrs r3, r2 8005422: 600b str r3, [r1, #0] } 8005424: bf00 nop 8005426: 370c adds r7, #12 8005428: 46bd mov sp, r7 800542a: f85d 7b04 ldr.w r7, [sp], #4 800542e: 4770 bx lr 8005430: 58003c00 .word 0x58003c00 08005434 : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 8005434: b480 push {r7} 8005436: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 8005438: 4b05 ldr r3, [pc, #20] @ (8005450 ) 800543a: 681b ldr r3, [r3, #0] 800543c: 4a04 ldr r2, [pc, #16] @ (8005450 ) 800543e: f023 0301 bic.w r3, r3, #1 8005442: 6013 str r3, [r2, #0] } 8005444: bf00 nop 8005446: 46bd mov sp, r7 8005448: f85d 7b04 ldr.w r7, [sp], #4 800544c: 4770 bx lr 800544e: bf00 nop 8005450: 58003c00 .word 0x58003c00 08005454 : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8005454: b480 push {r7} 8005456: b083 sub sp, #12 8005458: af00 add r7, sp, #0 800545a: 6078 str r0, [r7, #4] 800545c: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 800545e: 4b07 ldr r3, [pc, #28] @ (800547c ) 8005460: 685a ldr r2, [r3, #4] 8005462: 687b ldr r3, [r7, #4] 8005464: 43db mvns r3, r3 8005466: 401a ands r2, r3 8005468: 4904 ldr r1, [pc, #16] @ (800547c ) 800546a: 683b ldr r3, [r7, #0] 800546c: 4313 orrs r3, r2 800546e: 604b str r3, [r1, #4] } 8005470: bf00 nop 8005472: 370c adds r7, #12 8005474: 46bd mov sp, r7 8005476: f85d 7b04 ldr.w r7, [sp], #4 800547a: 4770 bx lr 800547c: 58000400 .word 0x58000400 08005480 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8005480: b480 push {r7} 8005482: b083 sub sp, #12 8005484: af00 add r7, sp, #0 8005486: 6078 str r0, [r7, #4] 8005488: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 800548a: 687b ldr r3, [r7, #4] 800548c: 689b ldr r3, [r3, #8] 800548e: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8005492: 683b ldr r3, [r7, #0] 8005494: 431a orrs r2, r3 8005496: 687b ldr r3, [r7, #4] 8005498: 609a str r2, [r3, #8] } 800549a: bf00 nop 800549c: 370c adds r7, #12 800549e: 46bd mov sp, r7 80054a0: f85d 7b04 ldr.w r7, [sp], #4 80054a4: 4770 bx lr 080054a6 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 80054a6: b480 push {r7} 80054a8: b083 sub sp, #12 80054aa: af00 add r7, sp, #0 80054ac: 6078 str r0, [r7, #4] 80054ae: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 80054b0: 687b ldr r3, [r7, #4] 80054b2: 689b ldr r3, [r3, #8] 80054b4: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 80054b8: 683b ldr r3, [r7, #0] 80054ba: 431a orrs r2, r3 80054bc: 687b ldr r3, [r7, #4] 80054be: 609a str r2, [r3, #8] } 80054c0: bf00 nop 80054c2: 370c adds r7, #12 80054c4: 46bd mov sp, r7 80054c6: f85d 7b04 ldr.w r7, [sp], #4 80054ca: 4770 bx lr 080054cc : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { 80054cc: b480 push {r7} 80054ce: b083 sub sp, #12 80054d0: af00 add r7, sp, #0 80054d2: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 80054d4: 687b ldr r3, [r7, #4] 80054d6: 689b ldr r3, [r3, #8] 80054d8: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 80054dc: 4618 mov r0, r3 80054de: 370c adds r7, #12 80054e0: 46bd mov sp, r7 80054e2: f85d 7b04 ldr.w r7, [sp], #4 80054e6: 4770 bx lr 080054e8 : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 80054e8: b480 push {r7} 80054ea: b087 sub sp, #28 80054ec: af00 add r7, sp, #0 80054ee: 60f8 str r0, [r7, #12] 80054f0: 60b9 str r1, [r7, #8] 80054f2: 607a str r2, [r7, #4] 80054f4: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 80054f6: 68fb ldr r3, [r7, #12] 80054f8: 3360 adds r3, #96 @ 0x60 80054fa: 461a mov r2, r3 80054fc: 68bb ldr r3, [r7, #8] 80054fe: 009b lsls r3, r3, #2 8005500: 4413 add r3, r2 8005502: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 8005504: 697b ldr r3, [r7, #20] 8005506: 681b ldr r3, [r3, #0] 8005508: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 800550c: 687b ldr r3, [r7, #4] 800550e: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 8005512: 683b ldr r3, [r7, #0] 8005514: 430b orrs r3, r1 8005516: 431a orrs r2, r3 8005518: 697b ldr r3, [r7, #20] 800551a: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 800551c: bf00 nop 800551e: 371c adds r7, #28 8005520: 46bd mov sp, r7 8005522: f85d 7b04 ldr.w r7, [sp], #4 8005526: 4770 bx lr 08005528 : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 8005528: b480 push {r7} 800552a: b085 sub sp, #20 800552c: af00 add r7, sp, #0 800552e: 60f8 str r0, [r7, #12] 8005530: 60b9 str r1, [r7, #8] 8005532: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 8005534: 68fb ldr r3, [r7, #12] 8005536: 691b ldr r3, [r3, #16] 8005538: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 800553c: 68bb ldr r3, [r7, #8] 800553e: f003 031f and.w r3, r3, #31 8005542: 6879 ldr r1, [r7, #4] 8005544: fa01 f303 lsl.w r3, r1, r3 8005548: 431a orrs r2, r3 800554a: 68fb ldr r3, [r7, #12] 800554c: 611a str r2, [r3, #16] } 800554e: bf00 nop 8005550: 3714 adds r7, #20 8005552: 46bd mov sp, r7 8005554: f85d 7b04 ldr.w r7, [sp], #4 8005558: 4770 bx lr 0800555a : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 800555a: b480 push {r7} 800555c: b087 sub sp, #28 800555e: af00 add r7, sp, #0 8005560: 60f8 str r0, [r7, #12] 8005562: 60b9 str r1, [r7, #8] 8005564: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005566: 68fb ldr r3, [r7, #12] 8005568: 3360 adds r3, #96 @ 0x60 800556a: 461a mov r2, r3 800556c: 68bb ldr r3, [r7, #8] 800556e: 009b lsls r3, r3, #2 8005570: 4413 add r3, r2 8005572: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8005574: 697b ldr r3, [r7, #20] 8005576: 681b ldr r3, [r3, #0] 8005578: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 800557c: 687b ldr r3, [r7, #4] 800557e: 431a orrs r2, r3 8005580: 697b ldr r3, [r7, #20] 8005582: 601a str r2, [r3, #0] } } 8005584: bf00 nop 8005586: 371c adds r7, #28 8005588: 46bd mov sp, r7 800558a: f85d 7b04 ldr.w r7, [sp], #4 800558e: 4770 bx lr 08005590 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { 8005590: b480 push {r7} 8005592: b083 sub sp, #12 8005594: af00 add r7, sp, #0 8005596: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8005598: 687b ldr r3, [r7, #4] 800559a: 68db ldr r3, [r3, #12] 800559c: f403 6340 and.w r3, r3, #3072 @ 0xc00 80055a0: 2b00 cmp r3, #0 80055a2: d101 bne.n 80055a8 80055a4: 2301 movs r3, #1 80055a6: e000 b.n 80055aa 80055a8: 2300 movs r3, #0 } 80055aa: 4618 mov r0, r3 80055ac: 370c adds r7, #12 80055ae: 46bd mov sp, r7 80055b0: f85d 7b04 ldr.w r7, [sp], #4 80055b4: 4770 bx lr 080055b6 : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 80055b6: b480 push {r7} 80055b8: b087 sub sp, #28 80055ba: af00 add r7, sp, #0 80055bc: 60f8 str r0, [r7, #12] 80055be: 60b9 str r1, [r7, #8] 80055c0: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 80055c2: 68fb ldr r3, [r7, #12] 80055c4: 3330 adds r3, #48 @ 0x30 80055c6: 461a mov r2, r3 80055c8: 68bb ldr r3, [r7, #8] 80055ca: 0a1b lsrs r3, r3, #8 80055cc: 009b lsls r3, r3, #2 80055ce: f003 030c and.w r3, r3, #12 80055d2: 4413 add r3, r2 80055d4: 617b str r3, [r7, #20] MODIFY_REG(*preg, 80055d6: 697b ldr r3, [r7, #20] 80055d8: 681a ldr r2, [r3, #0] 80055da: 68bb ldr r3, [r7, #8] 80055dc: f003 031f and.w r3, r3, #31 80055e0: 211f movs r1, #31 80055e2: fa01 f303 lsl.w r3, r1, r3 80055e6: 43db mvns r3, r3 80055e8: 401a ands r2, r3 80055ea: 687b ldr r3, [r7, #4] 80055ec: 0e9b lsrs r3, r3, #26 80055ee: f003 011f and.w r1, r3, #31 80055f2: 68bb ldr r3, [r7, #8] 80055f4: f003 031f and.w r3, r3, #31 80055f8: fa01 f303 lsl.w r3, r1, r3 80055fc: 431a orrs r2, r3 80055fe: 697b ldr r3, [r7, #20] 8005600: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8005602: bf00 nop 8005604: 371c adds r7, #28 8005606: 46bd mov sp, r7 8005608: f85d 7b04 ldr.w r7, [sp], #4 800560c: 4770 bx lr 0800560e : * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) { 800560e: b480 push {r7} 8005610: b083 sub sp, #12 8005612: af00 add r7, sp, #0 8005614: 6078 str r0, [r7, #4] 8005616: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 8005618: 687b ldr r3, [r7, #4] 800561a: 68db ldr r3, [r3, #12] 800561c: f023 0203 bic.w r2, r3, #3 8005620: 683b ldr r3, [r7, #0] 8005622: 431a orrs r2, r3 8005624: 687b ldr r3, [r7, #4] 8005626: 60da str r2, [r3, #12] } 8005628: bf00 nop 800562a: 370c adds r7, #12 800562c: 46bd mov sp, r7 800562e: f85d 7b04 ldr.w r7, [sp], #4 8005632: 4770 bx lr 08005634 : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 8005634: b480 push {r7} 8005636: b087 sub sp, #28 8005638: af00 add r7, sp, #0 800563a: 60f8 str r0, [r7, #12] 800563c: 60b9 str r1, [r7, #8] 800563e: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8005640: 68fb ldr r3, [r7, #12] 8005642: 3314 adds r3, #20 8005644: 461a mov r2, r3 8005646: 68bb ldr r3, [r7, #8] 8005648: 0e5b lsrs r3, r3, #25 800564a: 009b lsls r3, r3, #2 800564c: f003 0304 and.w r3, r3, #4 8005650: 4413 add r3, r2 8005652: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8005654: 697b ldr r3, [r7, #20] 8005656: 681a ldr r2, [r3, #0] 8005658: 68bb ldr r3, [r7, #8] 800565a: 0d1b lsrs r3, r3, #20 800565c: f003 031f and.w r3, r3, #31 8005660: 2107 movs r1, #7 8005662: fa01 f303 lsl.w r3, r1, r3 8005666: 43db mvns r3, r3 8005668: 401a ands r2, r3 800566a: 68bb ldr r3, [r7, #8] 800566c: 0d1b lsrs r3, r3, #20 800566e: f003 031f and.w r3, r3, #31 8005672: 6879 ldr r1, [r7, #4] 8005674: fa01 f303 lsl.w r3, r1, r3 8005678: 431a orrs r2, r3 800567a: 697b ldr r3, [r7, #20] 800567c: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 800567e: bf00 nop 8005680: 371c adds r7, #28 8005682: 46bd mov sp, r7 8005684: f85d 7b04 ldr.w r7, [sp], #4 8005688: 4770 bx lr ... 0800568c : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 800568c: b480 push {r7} 800568e: b085 sub sp, #20 8005690: af00 add r7, sp, #0 8005692: 60f8 str r0, [r7, #12] 8005694: 60b9 str r1, [r7, #8] 8005696: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 8005698: 68fb ldr r3, [r7, #12] 800569a: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 800569e: 68bb ldr r3, [r7, #8] 80056a0: f3c3 0313 ubfx r3, r3, #0, #20 80056a4: 43db mvns r3, r3 80056a6: 401a ands r2, r3 80056a8: 687b ldr r3, [r7, #4] 80056aa: f003 0318 and.w r3, r3, #24 80056ae: 4908 ldr r1, [pc, #32] @ (80056d0 ) 80056b0: 40d9 lsrs r1, r3 80056b2: 68bb ldr r3, [r7, #8] 80056b4: 400b ands r3, r1 80056b6: f3c3 0313 ubfx r3, r3, #0, #20 80056ba: 431a orrs r2, r3 80056bc: 68fb ldr r3, [r7, #12] 80056be: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 80056c2: bf00 nop 80056c4: 3714 adds r7, #20 80056c6: 46bd mov sp, r7 80056c8: f85d 7b04 ldr.w r7, [sp], #4 80056cc: 4770 bx lr 80056ce: bf00 nop 80056d0: 000fffff .word 0x000fffff 080056d4 : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { 80056d4: b480 push {r7} 80056d6: b083 sub sp, #12 80056d8: af00 add r7, sp, #0 80056da: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 80056dc: 687b ldr r3, [r7, #4] 80056de: 689b ldr r3, [r3, #8] 80056e0: f003 031f and.w r3, r3, #31 } 80056e4: 4618 mov r0, r3 80056e6: 370c adds r7, #12 80056e8: 46bd mov sp, r7 80056ea: f85d 7b04 ldr.w r7, [sp], #4 80056ee: 4770 bx lr 080056f0 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 80056f0: b480 push {r7} 80056f2: b083 sub sp, #12 80056f4: af00 add r7, sp, #0 80056f6: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 80056f8: 687b ldr r3, [r7, #4] 80056fa: 689a ldr r2, [r3, #8] 80056fc: 4b04 ldr r3, [pc, #16] @ (8005710 ) 80056fe: 4013 ands r3, r2 8005700: 687a ldr r2, [r7, #4] 8005702: 6093 str r3, [r2, #8] } 8005704: bf00 nop 8005706: 370c adds r7, #12 8005708: 46bd mov sp, r7 800570a: f85d 7b04 ldr.w r7, [sp], #4 800570e: 4770 bx lr 8005710: 5fffffc0 .word 0x5fffffc0 08005714 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { 8005714: b480 push {r7} 8005716: b083 sub sp, #12 8005718: af00 add r7, sp, #0 800571a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 800571c: 687b ldr r3, [r7, #4] 800571e: 689b ldr r3, [r3, #8] 8005720: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8005724: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005728: d101 bne.n 800572e 800572a: 2301 movs r3, #1 800572c: e000 b.n 8005730 800572e: 2300 movs r3, #0 } 8005730: 4618 mov r0, r3 8005732: 370c adds r7, #12 8005734: 46bd mov sp, r7 8005736: f85d 7b04 ldr.w r7, [sp], #4 800573a: 4770 bx lr 0800573c : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 800573c: b480 push {r7} 800573e: b083 sub sp, #12 8005740: af00 add r7, sp, #0 8005742: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005744: 687b ldr r3, [r7, #4] 8005746: 689a ldr r2, [r3, #8] 8005748: 4b05 ldr r3, [pc, #20] @ (8005760 ) 800574a: 4013 ands r3, r2 800574c: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8005750: 687b ldr r3, [r7, #4] 8005752: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8005754: bf00 nop 8005756: 370c adds r7, #12 8005758: 46bd mov sp, r7 800575a: f85d 7b04 ldr.w r7, [sp], #4 800575e: 4770 bx lr 8005760: 6fffffc0 .word 0x6fffffc0 08005764 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { 8005764: b480 push {r7} 8005766: b083 sub sp, #12 8005768: af00 add r7, sp, #0 800576a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 800576c: 687b ldr r3, [r7, #4] 800576e: 689b ldr r3, [r3, #8] 8005770: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005774: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005778: d101 bne.n 800577e 800577a: 2301 movs r3, #1 800577c: e000 b.n 8005780 800577e: 2300 movs r3, #0 } 8005780: 4618 mov r0, r3 8005782: 370c adds r7, #12 8005784: 46bd mov sp, r7 8005786: f85d 7b04 ldr.w r7, [sp], #4 800578a: 4770 bx lr 0800578c : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 800578c: b480 push {r7} 800578e: b083 sub sp, #12 8005790: af00 add r7, sp, #0 8005792: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005794: 687b ldr r3, [r7, #4] 8005796: 689a ldr r2, [r3, #8] 8005798: 4b05 ldr r3, [pc, #20] @ (80057b0 ) 800579a: 4013 ands r3, r2 800579c: f043 0201 orr.w r2, r3, #1 80057a0: 687b ldr r3, [r7, #4] 80057a2: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 80057a4: bf00 nop 80057a6: 370c adds r7, #12 80057a8: 46bd mov sp, r7 80057aa: f85d 7b04 ldr.w r7, [sp], #4 80057ae: 4770 bx lr 80057b0: 7fffffc0 .word 0x7fffffc0 080057b4 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 80057b4: b480 push {r7} 80057b6: b083 sub sp, #12 80057b8: af00 add r7, sp, #0 80057ba: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80057bc: 687b ldr r3, [r7, #4] 80057be: 689a ldr r2, [r3, #8] 80057c0: 4b05 ldr r3, [pc, #20] @ (80057d8 ) 80057c2: 4013 ands r3, r2 80057c4: f043 0202 orr.w r2, r3, #2 80057c8: 687b ldr r3, [r7, #4] 80057ca: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 80057cc: bf00 nop 80057ce: 370c adds r7, #12 80057d0: 46bd mov sp, r7 80057d2: f85d 7b04 ldr.w r7, [sp], #4 80057d6: 4770 bx lr 80057d8: 7fffffc0 .word 0x7fffffc0 080057dc : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { 80057dc: b480 push {r7} 80057de: b083 sub sp, #12 80057e0: af00 add r7, sp, #0 80057e2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80057e4: 687b ldr r3, [r7, #4] 80057e6: 689b ldr r3, [r3, #8] 80057e8: f003 0301 and.w r3, r3, #1 80057ec: 2b01 cmp r3, #1 80057ee: d101 bne.n 80057f4 80057f0: 2301 movs r3, #1 80057f2: e000 b.n 80057f6 80057f4: 2300 movs r3, #0 } 80057f6: 4618 mov r0, r3 80057f8: 370c adds r7, #12 80057fa: 46bd mov sp, r7 80057fc: f85d 7b04 ldr.w r7, [sp], #4 8005800: 4770 bx lr 08005802 : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { 8005802: b480 push {r7} 8005804: b083 sub sp, #12 8005806: af00 add r7, sp, #0 8005808: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 800580a: 687b ldr r3, [r7, #4] 800580c: 689b ldr r3, [r3, #8] 800580e: f003 0302 and.w r3, r3, #2 8005812: 2b02 cmp r3, #2 8005814: d101 bne.n 800581a 8005816: 2301 movs r3, #1 8005818: e000 b.n 800581c 800581a: 2300 movs r3, #0 } 800581c: 4618 mov r0, r3 800581e: 370c adds r7, #12 8005820: 46bd mov sp, r7 8005822: f85d 7b04 ldr.w r7, [sp], #4 8005826: 4770 bx lr 08005828 : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8005828: b480 push {r7} 800582a: b083 sub sp, #12 800582c: af00 add r7, sp, #0 800582e: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8005830: 687b ldr r3, [r7, #4] 8005832: 689a ldr r2, [r3, #8] 8005834: 4b05 ldr r3, [pc, #20] @ (800584c ) 8005836: 4013 ands r3, r2 8005838: f043 0204 orr.w r2, r3, #4 800583c: 687b ldr r3, [r7, #4] 800583e: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8005840: bf00 nop 8005842: 370c adds r7, #12 8005844: 46bd mov sp, r7 8005846: f85d 7b04 ldr.w r7, [sp], #4 800584a: 4770 bx lr 800584c: 7fffffc0 .word 0x7fffffc0 08005850 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { 8005850: b480 push {r7} 8005852: b083 sub sp, #12 8005854: af00 add r7, sp, #0 8005856: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8005858: 687b ldr r3, [r7, #4] 800585a: 689b ldr r3, [r3, #8] 800585c: f003 0304 and.w r3, r3, #4 8005860: 2b04 cmp r3, #4 8005862: d101 bne.n 8005868 8005864: 2301 movs r3, #1 8005866: e000 b.n 800586a 8005868: 2300 movs r3, #0 } 800586a: 4618 mov r0, r3 800586c: 370c adds r7, #12 800586e: 46bd mov sp, r7 8005870: f85d 7b04 ldr.w r7, [sp], #4 8005874: 4770 bx lr 08005876 : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { 8005876: b480 push {r7} 8005878: b083 sub sp, #12 800587a: af00 add r7, sp, #0 800587c: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 800587e: 687b ldr r3, [r7, #4] 8005880: 689b ldr r3, [r3, #8] 8005882: f003 0308 and.w r3, r3, #8 8005886: 2b08 cmp r3, #8 8005888: d101 bne.n 800588e 800588a: 2301 movs r3, #1 800588c: e000 b.n 8005890 800588e: 2300 movs r3, #0 } 8005890: 4618 mov r0, r3 8005892: 370c adds r7, #12 8005894: 46bd mov sp, r7 8005896: f85d 7b04 ldr.w r7, [sp], #4 800589a: 4770 bx lr 0800589c : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 800589c: b590 push {r4, r7, lr} 800589e: b089 sub sp, #36 @ 0x24 80058a0: af00 add r7, sp, #0 80058a2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80058a4: 2300 movs r3, #0 80058a6: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 80058a8: 2300 movs r3, #0 80058aa: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 80058ac: 687b ldr r3, [r7, #4] 80058ae: 2b00 cmp r3, #0 80058b0: d101 bne.n 80058b6 { return HAL_ERROR; 80058b2: 2301 movs r3, #1 80058b4: e18f b.n 8005bd6 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 80058b6: 687b ldr r3, [r7, #4] 80058b8: 68db ldr r3, [r3, #12] 80058ba: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 80058bc: 687b ldr r3, [r7, #4] 80058be: 6d5b ldr r3, [r3, #84] @ 0x54 80058c0: 2b00 cmp r3, #0 80058c2: d109 bne.n 80058d8 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 80058c4: 6878 ldr r0, [r7, #4] 80058c6: f7fd fd9d bl 8003404 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 80058ca: 687b ldr r3, [r7, #4] 80058cc: 2200 movs r2, #0 80058ce: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 80058d0: 687b ldr r3, [r7, #4] 80058d2: 2200 movs r2, #0 80058d4: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 80058d8: 687b ldr r3, [r7, #4] 80058da: 681b ldr r3, [r3, #0] 80058dc: 4618 mov r0, r3 80058de: f7ff ff19 bl 8005714 80058e2: 4603 mov r3, r0 80058e4: 2b00 cmp r3, #0 80058e6: d004 beq.n 80058f2 { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 80058e8: 687b ldr r3, [r7, #4] 80058ea: 681b ldr r3, [r3, #0] 80058ec: 4618 mov r0, r3 80058ee: f7ff feff bl 80056f0 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 80058f2: 687b ldr r3, [r7, #4] 80058f4: 681b ldr r3, [r3, #0] 80058f6: 4618 mov r0, r3 80058f8: f7ff ff34 bl 8005764 80058fc: 4603 mov r3, r0 80058fe: 2b00 cmp r3, #0 8005900: d114 bne.n 800592c { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8005902: 687b ldr r3, [r7, #4] 8005904: 681b ldr r3, [r3, #0] 8005906: 4618 mov r0, r3 8005908: f7ff ff18 bl 800573c /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800590c: 4b87 ldr r3, [pc, #540] @ (8005b2c ) 800590e: 681b ldr r3, [r3, #0] 8005910: 099b lsrs r3, r3, #6 8005912: 4a87 ldr r2, [pc, #540] @ (8005b30 ) 8005914: fba2 2303 umull r2, r3, r2, r3 8005918: 099b lsrs r3, r3, #6 800591a: 3301 adds r3, #1 800591c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 800591e: e002 b.n 8005926 { wait_loop_index--; 8005920: 68bb ldr r3, [r7, #8] 8005922: 3b01 subs r3, #1 8005924: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8005926: 68bb ldr r3, [r7, #8] 8005928: 2b00 cmp r3, #0 800592a: d1f9 bne.n 8005920 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 800592c: 687b ldr r3, [r7, #4] 800592e: 681b ldr r3, [r3, #0] 8005930: 4618 mov r0, r3 8005932: f7ff ff17 bl 8005764 8005936: 4603 mov r3, r0 8005938: 2b00 cmp r3, #0 800593a: d10d bne.n 8005958 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800593c: 687b ldr r3, [r7, #4] 800593e: 6d5b ldr r3, [r3, #84] @ 0x54 8005940: f043 0210 orr.w r2, r3, #16 8005944: 687b ldr r3, [r7, #4] 8005946: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8005948: 687b ldr r3, [r7, #4] 800594a: 6d9b ldr r3, [r3, #88] @ 0x58 800594c: f043 0201 orr.w r2, r3, #1 8005950: 687b ldr r3, [r7, #4] 8005952: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 8005954: 2301 movs r3, #1 8005956: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8005958: 687b ldr r3, [r7, #4] 800595a: 681b ldr r3, [r3, #0] 800595c: 4618 mov r0, r3 800595e: f7ff ff77 bl 8005850 8005962: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 8005964: 687b ldr r3, [r7, #4] 8005966: 6d5b ldr r3, [r3, #84] @ 0x54 8005968: f003 0310 and.w r3, r3, #16 800596c: 2b00 cmp r3, #0 800596e: f040 8129 bne.w 8005bc4 && (tmp_adc_reg_is_conversion_on_going == 0UL) 8005972: 697b ldr r3, [r7, #20] 8005974: 2b00 cmp r3, #0 8005976: f040 8125 bne.w 8005bc4 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800597a: 687b ldr r3, [r7, #4] 800597c: 6d5b ldr r3, [r3, #84] @ 0x54 800597e: f423 7381 bic.w r3, r3, #258 @ 0x102 8005982: f043 0202 orr.w r2, r3, #2 8005986: 687b ldr r3, [r7, #4] 8005988: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 800598a: 687b ldr r3, [r7, #4] 800598c: 681b ldr r3, [r3, #0] 800598e: 4618 mov r0, r3 8005990: f7ff ff24 bl 80057dc 8005994: 4603 mov r3, r0 8005996: 2b00 cmp r3, #0 8005998: d136 bne.n 8005a08 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 800599a: 687b ldr r3, [r7, #4] 800599c: 681b ldr r3, [r3, #0] 800599e: 4a65 ldr r2, [pc, #404] @ (8005b34 ) 80059a0: 4293 cmp r3, r2 80059a2: d004 beq.n 80059ae 80059a4: 687b ldr r3, [r7, #4] 80059a6: 681b ldr r3, [r3, #0] 80059a8: 4a63 ldr r2, [pc, #396] @ (8005b38 ) 80059aa: 4293 cmp r3, r2 80059ac: d10e bne.n 80059cc 80059ae: 4861 ldr r0, [pc, #388] @ (8005b34 ) 80059b0: f7ff ff14 bl 80057dc 80059b4: 4604 mov r4, r0 80059b6: 4860 ldr r0, [pc, #384] @ (8005b38 ) 80059b8: f7ff ff10 bl 80057dc 80059bc: 4603 mov r3, r0 80059be: 4323 orrs r3, r4 80059c0: 2b00 cmp r3, #0 80059c2: bf0c ite eq 80059c4: 2301 moveq r3, #1 80059c6: 2300 movne r3, #0 80059c8: b2db uxtb r3, r3 80059ca: e008 b.n 80059de 80059cc: 485b ldr r0, [pc, #364] @ (8005b3c ) 80059ce: f7ff ff05 bl 80057dc 80059d2: 4603 mov r3, r0 80059d4: 2b00 cmp r3, #0 80059d6: bf0c ite eq 80059d8: 2301 moveq r3, #1 80059da: 2300 movne r3, #0 80059dc: b2db uxtb r3, r3 80059de: 2b00 cmp r3, #0 80059e0: d012 beq.n 8005a08 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 80059e2: 687b ldr r3, [r7, #4] 80059e4: 681b ldr r3, [r3, #0] 80059e6: 4a53 ldr r2, [pc, #332] @ (8005b34 ) 80059e8: 4293 cmp r3, r2 80059ea: d004 beq.n 80059f6 80059ec: 687b ldr r3, [r7, #4] 80059ee: 681b ldr r3, [r3, #0] 80059f0: 4a51 ldr r2, [pc, #324] @ (8005b38 ) 80059f2: 4293 cmp r3, r2 80059f4: d101 bne.n 80059fa 80059f6: 4a52 ldr r2, [pc, #328] @ (8005b40 ) 80059f8: e000 b.n 80059fc 80059fa: 4a52 ldr r2, [pc, #328] @ (8005b44 ) 80059fc: 687b ldr r3, [r7, #4] 80059fe: 685b ldr r3, [r3, #4] 8005a00: 4619 mov r1, r3 8005a02: 4610 mov r0, r2 8005a04: f7ff fd3c bl 8005480 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8005a08: f7ff fcf4 bl 80053f4 8005a0c: 4603 mov r3, r0 8005a0e: f241 0203 movw r2, #4099 @ 0x1003 8005a12: 4293 cmp r3, r2 8005a14: d914 bls.n 8005a40 8005a16: 687b ldr r3, [r7, #4] 8005a18: 689b ldr r3, [r3, #8] 8005a1a: 2b10 cmp r3, #16 8005a1c: d110 bne.n 8005a40 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005a1e: 687b ldr r3, [r7, #4] 8005a20: 7d5b ldrb r3, [r3, #21] 8005a22: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8005a24: 687b ldr r3, [r7, #4] 8005a26: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005a28: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8005a2a: 687b ldr r3, [r7, #4] 8005a2c: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8005a2e: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8005a30: 687b ldr r3, [r7, #4] 8005a32: 7f1b ldrb r3, [r3, #28] 8005a34: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8005a36: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005a38: f043 030c orr.w r3, r3, #12 8005a3c: 61bb str r3, [r7, #24] 8005a3e: e00d b.n 8005a5c } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005a40: 687b ldr r3, [r7, #4] 8005a42: 7d5b ldrb r3, [r3, #21] 8005a44: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8005a46: 687b ldr r3, [r7, #4] 8005a48: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005a4a: 431a orrs r2, r3 hadc->Init.Resolution | 8005a4c: 687b ldr r3, [r7, #4] 8005a4e: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8005a50: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8005a52: 687b ldr r3, [r7, #4] 8005a54: 7f1b ldrb r3, [r3, #28] 8005a56: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8005a58: 4313 orrs r3, r2 8005a5a: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 8005a5c: 687b ldr r3, [r7, #4] 8005a5e: 7f1b ldrb r3, [r3, #28] 8005a60: 2b01 cmp r3, #1 8005a62: d106 bne.n 8005a72 { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 8005a64: 687b ldr r3, [r7, #4] 8005a66: 6a1b ldr r3, [r3, #32] 8005a68: 3b01 subs r3, #1 8005a6a: 045b lsls r3, r3, #17 8005a6c: 69ba ldr r2, [r7, #24] 8005a6e: 4313 orrs r3, r2 8005a70: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 8005a72: 687b ldr r3, [r7, #4] 8005a74: 6a5b ldr r3, [r3, #36] @ 0x24 8005a76: 2b00 cmp r3, #0 8005a78: d009 beq.n 8005a8e { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8005a7a: 687b ldr r3, [r7, #4] 8005a7c: 6a5b ldr r3, [r3, #36] @ 0x24 8005a7e: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 8005a82: 687b ldr r3, [r7, #4] 8005a84: 6a9b ldr r3, [r3, #40] @ 0x28 8005a86: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 8005a88: 69ba ldr r2, [r7, #24] 8005a8a: 4313 orrs r3, r2 8005a8c: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 8005a8e: 687b ldr r3, [r7, #4] 8005a90: 681b ldr r3, [r3, #0] 8005a92: 68da ldr r2, [r3, #12] 8005a94: 4b2c ldr r3, [pc, #176] @ (8005b48 ) 8005a96: 4013 ands r3, r2 8005a98: 687a ldr r2, [r7, #4] 8005a9a: 6812 ldr r2, [r2, #0] 8005a9c: 69b9 ldr r1, [r7, #24] 8005a9e: 430b orrs r3, r1 8005aa0: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8005aa2: 687b ldr r3, [r7, #4] 8005aa4: 681b ldr r3, [r3, #0] 8005aa6: 4618 mov r0, r3 8005aa8: f7ff fed2 bl 8005850 8005aac: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8005aae: 687b ldr r3, [r7, #4] 8005ab0: 681b ldr r3, [r3, #0] 8005ab2: 4618 mov r0, r3 8005ab4: f7ff fedf bl 8005876 8005ab8: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8005aba: 693b ldr r3, [r7, #16] 8005abc: 2b00 cmp r3, #0 8005abe: d15f bne.n 8005b80 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8005ac0: 68fb ldr r3, [r7, #12] 8005ac2: 2b00 cmp r3, #0 8005ac4: d15c bne.n 8005b80 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8005ac6: 687b ldr r3, [r7, #4] 8005ac8: 7d1b ldrb r3, [r3, #20] 8005aca: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 8005acc: 687b ldr r3, [r7, #4] 8005ace: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 8005ad0: 4313 orrs r3, r2 8005ad2: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8005ad4: 687b ldr r3, [r7, #4] 8005ad6: 681b ldr r3, [r3, #0] 8005ad8: 68da ldr r2, [r3, #12] 8005ada: 4b1c ldr r3, [pc, #112] @ (8005b4c ) 8005adc: 4013 ands r3, r2 8005ade: 687a ldr r2, [r7, #4] 8005ae0: 6812 ldr r2, [r2, #0] 8005ae2: 69b9 ldr r1, [r7, #24] 8005ae4: 430b orrs r3, r1 8005ae6: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 8005ae8: 687b ldr r3, [r7, #4] 8005aea: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8005aee: 2b01 cmp r3, #1 8005af0: d130 bne.n 8005b54 #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 8005af2: 687b ldr r3, [r7, #4] 8005af4: 6a5b ldr r3, [r3, #36] @ 0x24 8005af6: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 8005af8: 687b ldr r3, [r7, #4] 8005afa: 681b ldr r3, [r3, #0] 8005afc: 691a ldr r2, [r3, #16] 8005afe: 4b14 ldr r3, [pc, #80] @ (8005b50 ) 8005b00: 4013 ands r3, r2 8005b02: 687a ldr r2, [r7, #4] 8005b04: 6bd2 ldr r2, [r2, #60] @ 0x3c 8005b06: 3a01 subs r2, #1 8005b08: 0411 lsls r1, r2, #16 8005b0a: 687a ldr r2, [r7, #4] 8005b0c: 6c12 ldr r2, [r2, #64] @ 0x40 8005b0e: 4311 orrs r1, r2 8005b10: 687a ldr r2, [r7, #4] 8005b12: 6c52 ldr r2, [r2, #68] @ 0x44 8005b14: 4311 orrs r1, r2 8005b16: 687a ldr r2, [r7, #4] 8005b18: 6c92 ldr r2, [r2, #72] @ 0x48 8005b1a: 430a orrs r2, r1 8005b1c: 431a orrs r2, r3 8005b1e: 687b ldr r3, [r7, #4] 8005b20: 681b ldr r3, [r3, #0] 8005b22: f042 0201 orr.w r2, r2, #1 8005b26: 611a str r2, [r3, #16] 8005b28: e01c b.n 8005b64 8005b2a: bf00 nop 8005b2c: 24000034 .word 0x24000034 8005b30: 053e2d63 .word 0x053e2d63 8005b34: 40022000 .word 0x40022000 8005b38: 40022100 .word 0x40022100 8005b3c: 58026000 .word 0x58026000 8005b40: 40022300 .word 0x40022300 8005b44: 58026300 .word 0x58026300 8005b48: fff0c003 .word 0xfff0c003 8005b4c: ffffbffc .word 0xffffbffc 8005b50: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8005b54: 687b ldr r3, [r7, #4] 8005b56: 681b ldr r3, [r3, #0] 8005b58: 691a ldr r2, [r3, #16] 8005b5a: 687b ldr r3, [r7, #4] 8005b5c: 681b ldr r3, [r3, #0] 8005b5e: f022 0201 bic.w r2, r2, #1 8005b62: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 8005b64: 687b ldr r3, [r7, #4] 8005b66: 681b ldr r3, [r3, #0] 8005b68: 691b ldr r3, [r3, #16] 8005b6a: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 8005b6e: 687b ldr r3, [r7, #4] 8005b70: 6b5a ldr r2, [r3, #52] @ 0x34 8005b72: 687b ldr r3, [r7, #4] 8005b74: 681b ldr r3, [r3, #0] 8005b76: 430a orrs r2, r1 8005b78: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 8005b7a: 6878 ldr r0, [r7, #4] 8005b7c: f000 fde2 bl 8006744 /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 8005b80: 687b ldr r3, [r7, #4] 8005b82: 68db ldr r3, [r3, #12] 8005b84: 2b01 cmp r3, #1 8005b86: d10c bne.n 8005ba2 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 8005b88: 687b ldr r3, [r7, #4] 8005b8a: 681b ldr r3, [r3, #0] 8005b8c: 6b1b ldr r3, [r3, #48] @ 0x30 8005b8e: f023 010f bic.w r1, r3, #15 8005b92: 687b ldr r3, [r7, #4] 8005b94: 699b ldr r3, [r3, #24] 8005b96: 1e5a subs r2, r3, #1 8005b98: 687b ldr r3, [r7, #4] 8005b9a: 681b ldr r3, [r3, #0] 8005b9c: 430a orrs r2, r1 8005b9e: 631a str r2, [r3, #48] @ 0x30 8005ba0: e007 b.n 8005bb2 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 8005ba2: 687b ldr r3, [r7, #4] 8005ba4: 681b ldr r3, [r3, #0] 8005ba6: 6b1a ldr r2, [r3, #48] @ 0x30 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 681b ldr r3, [r3, #0] 8005bac: f022 020f bic.w r2, r2, #15 8005bb0: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 8005bb2: 687b ldr r3, [r7, #4] 8005bb4: 6d5b ldr r3, [r3, #84] @ 0x54 8005bb6: f023 0303 bic.w r3, r3, #3 8005bba: f043 0201 orr.w r2, r3, #1 8005bbe: 687b ldr r3, [r7, #4] 8005bc0: 655a str r2, [r3, #84] @ 0x54 8005bc2: e007 b.n 8005bd4 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8005bc4: 687b ldr r3, [r7, #4] 8005bc6: 6d5b ldr r3, [r3, #84] @ 0x54 8005bc8: f043 0210 orr.w r2, r3, #16 8005bcc: 687b ldr r3, [r7, #4] 8005bce: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8005bd0: 2301 movs r3, #1 8005bd2: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 8005bd4: 7ffb ldrb r3, [r7, #31] } 8005bd6: 4618 mov r0, r3 8005bd8: 3724 adds r7, #36 @ 0x24 8005bda: 46bd mov sp, r7 8005bdc: bd90 pop {r4, r7, pc} 8005bde: bf00 nop 08005be0 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 8005be0: b580 push {r7, lr} 8005be2: b086 sub sp, #24 8005be4: af00 add r7, sp, #0 8005be6: 60f8 str r0, [r7, #12] 8005be8: 60b9 str r1, [r7, #8] 8005bea: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8005bec: 68fb ldr r3, [r7, #12] 8005bee: 681b ldr r3, [r3, #0] 8005bf0: 4a55 ldr r2, [pc, #340] @ (8005d48 ) 8005bf2: 4293 cmp r3, r2 8005bf4: d004 beq.n 8005c00 8005bf6: 68fb ldr r3, [r7, #12] 8005bf8: 681b ldr r3, [r3, #0] 8005bfa: 4a54 ldr r2, [pc, #336] @ (8005d4c ) 8005bfc: 4293 cmp r3, r2 8005bfe: d101 bne.n 8005c04 8005c00: 4b53 ldr r3, [pc, #332] @ (8005d50 ) 8005c02: e000 b.n 8005c06 8005c04: 4b53 ldr r3, [pc, #332] @ (8005d54 ) 8005c06: 4618 mov r0, r3 8005c08: f7ff fd64 bl 80056d4 8005c0c: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8005c0e: 68fb ldr r3, [r7, #12] 8005c10: 681b ldr r3, [r3, #0] 8005c12: 4618 mov r0, r3 8005c14: f7ff fe1c bl 8005850 8005c18: 4603 mov r3, r0 8005c1a: 2b00 cmp r3, #0 8005c1c: f040 808c bne.w 8005d38 { /* Process locked */ __HAL_LOCK(hadc); 8005c20: 68fb ldr r3, [r7, #12] 8005c22: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8005c26: 2b01 cmp r3, #1 8005c28: d101 bne.n 8005c2e 8005c2a: 2302 movs r3, #2 8005c2c: e087 b.n 8005d3e 8005c2e: 68fb ldr r3, [r7, #12] 8005c30: 2201 movs r2, #1 8005c32: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8005c36: 693b ldr r3, [r7, #16] 8005c38: 2b00 cmp r3, #0 8005c3a: d005 beq.n 8005c48 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 8005c3c: 693b ldr r3, [r7, #16] 8005c3e: 2b05 cmp r3, #5 8005c40: d002 beq.n 8005c48 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 8005c42: 693b ldr r3, [r7, #16] 8005c44: 2b09 cmp r3, #9 8005c46: d170 bne.n 8005d2a ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8005c48: 68f8 ldr r0, [r7, #12] 8005c4a: f000 fbfd bl 8006448 8005c4e: 4603 mov r3, r0 8005c50: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8005c52: 7dfb ldrb r3, [r7, #23] 8005c54: 2b00 cmp r3, #0 8005c56: d163 bne.n 8005d20 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8005c58: 68fb ldr r3, [r7, #12] 8005c5a: 6d5a ldr r2, [r3, #84] @ 0x54 8005c5c: 4b3e ldr r3, [pc, #248] @ (8005d58 ) 8005c5e: 4013 ands r3, r2 8005c60: f443 7280 orr.w r2, r3, #256 @ 0x100 8005c64: 68fb ldr r3, [r7, #12] 8005c66: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8005c68: 68fb ldr r3, [r7, #12] 8005c6a: 681b ldr r3, [r3, #0] 8005c6c: 4a37 ldr r2, [pc, #220] @ (8005d4c ) 8005c6e: 4293 cmp r3, r2 8005c70: d002 beq.n 8005c78 8005c72: 68fb ldr r3, [r7, #12] 8005c74: 681b ldr r3, [r3, #0] 8005c76: e000 b.n 8005c7a 8005c78: 4b33 ldr r3, [pc, #204] @ (8005d48 ) 8005c7a: 68fa ldr r2, [r7, #12] 8005c7c: 6812 ldr r2, [r2, #0] 8005c7e: 4293 cmp r3, r2 8005c80: d002 beq.n 8005c88 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8005c82: 693b ldr r3, [r7, #16] 8005c84: 2b00 cmp r3, #0 8005c86: d105 bne.n 8005c94 ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 8005c88: 68fb ldr r3, [r7, #12] 8005c8a: 6d5b ldr r3, [r3, #84] @ 0x54 8005c8c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8005c90: 68fb ldr r3, [r7, #12] 8005c92: 655a str r2, [r3, #84] @ 0x54 } /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 8005c94: 68fb ldr r3, [r7, #12] 8005c96: 6d5b ldr r3, [r3, #84] @ 0x54 8005c98: f403 5380 and.w r3, r3, #4096 @ 0x1000 8005c9c: 2b00 cmp r3, #0 8005c9e: d006 beq.n 8005cae { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 8005ca0: 68fb ldr r3, [r7, #12] 8005ca2: 6d9b ldr r3, [r3, #88] @ 0x58 8005ca4: f023 0206 bic.w r2, r3, #6 8005ca8: 68fb ldr r3, [r7, #12] 8005caa: 659a str r2, [r3, #88] @ 0x58 8005cac: e002 b.n 8005cb4 } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 8005cae: 68fb ldr r3, [r7, #12] 8005cb0: 2200 movs r2, #0 8005cb2: 659a str r2, [r3, #88] @ 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 8005cb4: 68fb ldr r3, [r7, #12] 8005cb6: 6cdb ldr r3, [r3, #76] @ 0x4c 8005cb8: 4a28 ldr r2, [pc, #160] @ (8005d5c ) 8005cba: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8005cbc: 68fb ldr r3, [r7, #12] 8005cbe: 6cdb ldr r3, [r3, #76] @ 0x4c 8005cc0: 4a27 ldr r2, [pc, #156] @ (8005d60 ) 8005cc2: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8005cc4: 68fb ldr r3, [r7, #12] 8005cc6: 6cdb ldr r3, [r3, #76] @ 0x4c 8005cc8: 4a26 ldr r2, [pc, #152] @ (8005d64 ) 8005cca: 64da str r2, [r3, #76] @ 0x4c /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8005ccc: 68fb ldr r3, [r7, #12] 8005cce: 681b ldr r3, [r3, #0] 8005cd0: 221c movs r2, #28 8005cd2: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8005cd4: 68fb ldr r3, [r7, #12] 8005cd6: 2200 movs r2, #0 8005cd8: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 8005cdc: 68fb ldr r3, [r7, #12] 8005cde: 681b ldr r3, [r3, #0] 8005ce0: 685a ldr r2, [r3, #4] 8005ce2: 68fb ldr r3, [r7, #12] 8005ce4: 681b ldr r3, [r3, #0] 8005ce6: f042 0210 orr.w r2, r2, #16 8005cea: 605a str r2, [r3, #4] { LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); 8005cec: 68fb ldr r3, [r7, #12] 8005cee: 681a ldr r2, [r3, #0] 8005cf0: 68fb ldr r3, [r7, #12] 8005cf2: 6adb ldr r3, [r3, #44] @ 0x2c 8005cf4: 4619 mov r1, r3 8005cf6: 4610 mov r0, r2 8005cf8: f7ff fc89 bl 800560e #endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8005cfc: 68fb ldr r3, [r7, #12] 8005cfe: 6cd8 ldr r0, [r3, #76] @ 0x4c 8005d00: 68fb ldr r3, [r7, #12] 8005d02: 681b ldr r3, [r3, #0] 8005d04: 3340 adds r3, #64 @ 0x40 8005d06: 4619 mov r1, r3 8005d08: 68ba ldr r2, [r7, #8] 8005d0a: 687b ldr r3, [r7, #4] 8005d0c: f002 fa5e bl 80081cc 8005d10: 4603 mov r3, r0 8005d12: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 8005d14: 68fb ldr r3, [r7, #12] 8005d16: 681b ldr r3, [r3, #0] 8005d18: 4618 mov r0, r3 8005d1a: f7ff fd85 bl 8005828 if (tmp_hal_status == HAL_OK) 8005d1e: e00d b.n 8005d3c } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8005d20: 68fb ldr r3, [r7, #12] 8005d22: 2200 movs r2, #0 8005d24: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (tmp_hal_status == HAL_OK) 8005d28: e008 b.n 8005d3c } } else { tmp_hal_status = HAL_ERROR; 8005d2a: 2301 movs r3, #1 8005d2c: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 8005d2e: 68fb ldr r3, [r7, #12] 8005d30: 2200 movs r2, #0 8005d32: f883 2050 strb.w r2, [r3, #80] @ 0x50 8005d36: e001 b.n 8005d3c } } else { tmp_hal_status = HAL_BUSY; 8005d38: 2302 movs r3, #2 8005d3a: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8005d3c: 7dfb ldrb r3, [r7, #23] } 8005d3e: 4618 mov r0, r3 8005d40: 3718 adds r7, #24 8005d42: 46bd mov sp, r7 8005d44: bd80 pop {r7, pc} 8005d46: bf00 nop 8005d48: 40022000 .word 0x40022000 8005d4c: 40022100 .word 0x40022100 8005d50: 40022300 .word 0x40022300 8005d54: 58026300 .word 0x58026300 8005d58: fffff0fe .word 0xfffff0fe 8005d5c: 0800661b .word 0x0800661b 8005d60: 080066f3 .word 0x080066f3 8005d64: 0800670f .word 0x0800670f 08005d68 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 8005d68: b480 push {r7} 8005d6a: b083 sub sp, #12 8005d6c: af00 add r7, sp, #0 8005d6e: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 8005d70: bf00 nop 8005d72: 370c adds r7, #12 8005d74: 46bd mov sp, r7 8005d76: f85d 7b04 ldr.w r7, [sp], #4 8005d7a: 4770 bx lr 08005d7c : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 8005d7c: b480 push {r7} 8005d7e: b083 sub sp, #12 8005d80: af00 add r7, sp, #0 8005d82: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 8005d84: bf00 nop 8005d86: 370c adds r7, #12 8005d88: 46bd mov sp, r7 8005d8a: f85d 7b04 ldr.w r7, [sp], #4 8005d8e: 4770 bx lr 08005d90 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 8005d90: b590 push {r4, r7, lr} 8005d92: b0a1 sub sp, #132 @ 0x84 8005d94: af00 add r7, sp, #0 8005d96: 6078 str r0, [r7, #4] 8005d98: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8005d9a: 2300 movs r3, #0 8005d9c: f887 307f strb.w r3, [r7, #127] @ 0x7f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 8005da0: 2300 movs r3, #0 8005da2: 60bb str r3, [r7, #8] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 8005da4: 683b ldr r3, [r7, #0] 8005da6: 68db ldr r3, [r3, #12] 8005da8: 4a65 ldr r2, [pc, #404] @ (8005f40 ) 8005daa: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 8005dac: 687b ldr r3, [r7, #4] 8005dae: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8005db2: 2b01 cmp r3, #1 8005db4: d101 bne.n 8005dba 8005db6: 2302 movs r3, #2 8005db8: e32e b.n 8006418 8005dba: 687b ldr r3, [r7, #4] 8005dbc: 2201 movs r2, #1 8005dbe: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8005dc2: 687b ldr r3, [r7, #4] 8005dc4: 681b ldr r3, [r3, #0] 8005dc6: 4618 mov r0, r3 8005dc8: f7ff fd42 bl 8005850 8005dcc: 4603 mov r3, r0 8005dce: 2b00 cmp r3, #0 8005dd0: f040 8313 bne.w 80063fa { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 8005dd4: 683b ldr r3, [r7, #0] 8005dd6: 681b ldr r3, [r3, #0] 8005dd8: 2b00 cmp r3, #0 8005dda: db2c blt.n 8005e36 /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 8005ddc: 683b ldr r3, [r7, #0] 8005dde: 681b ldr r3, [r3, #0] 8005de0: f3c3 0313 ubfx r3, r3, #0, #20 8005de4: 2b00 cmp r3, #0 8005de6: d108 bne.n 8005dfa 8005de8: 683b ldr r3, [r7, #0] 8005dea: 681b ldr r3, [r3, #0] 8005dec: 0e9b lsrs r3, r3, #26 8005dee: f003 031f and.w r3, r3, #31 8005df2: 2201 movs r2, #1 8005df4: fa02 f303 lsl.w r3, r2, r3 8005df8: e016 b.n 8005e28 8005dfa: 683b ldr r3, [r7, #0] 8005dfc: 681b ldr r3, [r3, #0] 8005dfe: 667b str r3, [r7, #100] @ 0x64 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8005e00: 6e7b ldr r3, [r7, #100] @ 0x64 8005e02: fa93 f3a3 rbit r3, r3 8005e06: 663b str r3, [r7, #96] @ 0x60 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8005e08: 6e3b ldr r3, [r7, #96] @ 0x60 8005e0a: 66bb str r3, [r7, #104] @ 0x68 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8005e0c: 6ebb ldr r3, [r7, #104] @ 0x68 8005e0e: 2b00 cmp r3, #0 8005e10: d101 bne.n 8005e16 { return 32U; 8005e12: 2320 movs r3, #32 8005e14: e003 b.n 8005e1e } return __builtin_clz(value); 8005e16: 6ebb ldr r3, [r7, #104] @ 0x68 8005e18: fab3 f383 clz r3, r3 8005e1c: b2db uxtb r3, r3 8005e1e: f003 031f and.w r3, r3, #31 8005e22: 2201 movs r2, #1 8005e24: fa02 f303 lsl.w r3, r2, r3 8005e28: 687a ldr r2, [r7, #4] 8005e2a: 6812 ldr r2, [r2, #0] 8005e2c: 69d1 ldr r1, [r2, #28] 8005e2e: 687a ldr r2, [r7, #4] 8005e30: 6812 ldr r2, [r2, #0] 8005e32: 430b orrs r3, r1 8005e34: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 8005e36: 687b ldr r3, [r7, #4] 8005e38: 6818 ldr r0, [r3, #0] 8005e3a: 683b ldr r3, [r7, #0] 8005e3c: 6859 ldr r1, [r3, #4] 8005e3e: 683b ldr r3, [r7, #0] 8005e40: 681b ldr r3, [r3, #0] 8005e42: 461a mov r2, r3 8005e44: f7ff fbb7 bl 80055b6 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8005e48: 687b ldr r3, [r7, #4] 8005e4a: 681b ldr r3, [r3, #0] 8005e4c: 4618 mov r0, r3 8005e4e: f7ff fcff bl 8005850 8005e52: 67b8 str r0, [r7, #120] @ 0x78 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8005e54: 687b ldr r3, [r7, #4] 8005e56: 681b ldr r3, [r3, #0] 8005e58: 4618 mov r0, r3 8005e5a: f7ff fd0c bl 8005876 8005e5e: 6778 str r0, [r7, #116] @ 0x74 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8005e60: 6fbb ldr r3, [r7, #120] @ 0x78 8005e62: 2b00 cmp r3, #0 8005e64: f040 80b8 bne.w 8005fd8 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8005e68: 6f7b ldr r3, [r7, #116] @ 0x74 8005e6a: 2b00 cmp r3, #0 8005e6c: f040 80b4 bne.w 8005fd8 ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 8005e70: 687b ldr r3, [r7, #4] 8005e72: 6818 ldr r0, [r3, #0] 8005e74: 683b ldr r3, [r7, #0] 8005e76: 6819 ldr r1, [r3, #0] 8005e78: 683b ldr r3, [r7, #0] 8005e7a: 689b ldr r3, [r3, #8] 8005e7c: 461a mov r2, r3 8005e7e: f7ff fbd9 bl 8005634 tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 8005e82: 4b30 ldr r3, [pc, #192] @ (8005f44 ) 8005e84: 681b ldr r3, [r3, #0] 8005e86: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 8005e8a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8005e8e: d10b bne.n 8005ea8 8005e90: 683b ldr r3, [r7, #0] 8005e92: 695a ldr r2, [r3, #20] 8005e94: 687b ldr r3, [r7, #4] 8005e96: 681b ldr r3, [r3, #0] 8005e98: 68db ldr r3, [r3, #12] 8005e9a: 089b lsrs r3, r3, #2 8005e9c: f003 0307 and.w r3, r3, #7 8005ea0: 005b lsls r3, r3, #1 8005ea2: fa02 f303 lsl.w r3, r2, r3 8005ea6: e01d b.n 8005ee4 8005ea8: 687b ldr r3, [r7, #4] 8005eaa: 681b ldr r3, [r3, #0] 8005eac: 68db ldr r3, [r3, #12] 8005eae: f003 0310 and.w r3, r3, #16 8005eb2: 2b00 cmp r3, #0 8005eb4: d10b bne.n 8005ece 8005eb6: 683b ldr r3, [r7, #0] 8005eb8: 695a ldr r2, [r3, #20] 8005eba: 687b ldr r3, [r7, #4] 8005ebc: 681b ldr r3, [r3, #0] 8005ebe: 68db ldr r3, [r3, #12] 8005ec0: 089b lsrs r3, r3, #2 8005ec2: f003 0307 and.w r3, r3, #7 8005ec6: 005b lsls r3, r3, #1 8005ec8: fa02 f303 lsl.w r3, r2, r3 8005ecc: e00a b.n 8005ee4 8005ece: 683b ldr r3, [r7, #0] 8005ed0: 695a ldr r2, [r3, #20] 8005ed2: 687b ldr r3, [r7, #4] 8005ed4: 681b ldr r3, [r3, #0] 8005ed6: 68db ldr r3, [r3, #12] 8005ed8: 089b lsrs r3, r3, #2 8005eda: f003 0304 and.w r3, r3, #4 8005ede: 005b lsls r3, r3, #1 8005ee0: fa02 f303 lsl.w r3, r2, r3 8005ee4: 673b str r3, [r7, #112] @ 0x70 } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 8005ee6: 683b ldr r3, [r7, #0] 8005ee8: 691b ldr r3, [r3, #16] 8005eea: 2b04 cmp r3, #4 8005eec: d02c beq.n 8005f48 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 8005eee: 687b ldr r3, [r7, #4] 8005ef0: 6818 ldr r0, [r3, #0] 8005ef2: 683b ldr r3, [r7, #0] 8005ef4: 6919 ldr r1, [r3, #16] 8005ef6: 683b ldr r3, [r7, #0] 8005ef8: 681a ldr r2, [r3, #0] 8005efa: 6f3b ldr r3, [r7, #112] @ 0x70 8005efc: f7ff faf4 bl 80054e8 else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 8005f00: 687b ldr r3, [r7, #4] 8005f02: 6818 ldr r0, [r3, #0] 8005f04: 683b ldr r3, [r7, #0] 8005f06: 6919 ldr r1, [r3, #16] 8005f08: 683b ldr r3, [r7, #0] 8005f0a: 7e5b ldrb r3, [r3, #25] 8005f0c: 2b01 cmp r3, #1 8005f0e: d102 bne.n 8005f16 8005f10: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8005f14: e000 b.n 8005f18 8005f16: 2300 movs r3, #0 8005f18: 461a mov r2, r3 8005f1a: f7ff fb1e bl 800555a assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 8005f1e: 687b ldr r3, [r7, #4] 8005f20: 6818 ldr r0, [r3, #0] 8005f22: 683b ldr r3, [r7, #0] 8005f24: 6919 ldr r1, [r3, #16] 8005f26: 683b ldr r3, [r7, #0] 8005f28: 7e1b ldrb r3, [r3, #24] 8005f2a: 2b01 cmp r3, #1 8005f2c: d102 bne.n 8005f34 8005f2e: f44f 6300 mov.w r3, #2048 @ 0x800 8005f32: e000 b.n 8005f36 8005f34: 2300 movs r3, #0 8005f36: 461a mov r2, r3 8005f38: f7ff faf6 bl 8005528 8005f3c: e04c b.n 8005fd8 8005f3e: bf00 nop 8005f40: 47ff0000 .word 0x47ff0000 8005f44: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8005f48: 687b ldr r3, [r7, #4] 8005f4a: 681b ldr r3, [r3, #0] 8005f4c: 6e1b ldr r3, [r3, #96] @ 0x60 8005f4e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8005f52: 683b ldr r3, [r7, #0] 8005f54: 681b ldr r3, [r3, #0] 8005f56: 069b lsls r3, r3, #26 8005f58: 429a cmp r2, r3 8005f5a: d107 bne.n 8005f6c { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 8005f5c: 687b ldr r3, [r7, #4] 8005f5e: 681b ldr r3, [r3, #0] 8005f60: 6e1a ldr r2, [r3, #96] @ 0x60 8005f62: 687b ldr r3, [r7, #4] 8005f64: 681b ldr r3, [r3, #0] 8005f66: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8005f6a: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8005f6c: 687b ldr r3, [r7, #4] 8005f6e: 681b ldr r3, [r3, #0] 8005f70: 6e5b ldr r3, [r3, #100] @ 0x64 8005f72: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8005f76: 683b ldr r3, [r7, #0] 8005f78: 681b ldr r3, [r3, #0] 8005f7a: 069b lsls r3, r3, #26 8005f7c: 429a cmp r2, r3 8005f7e: d107 bne.n 8005f90 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 8005f80: 687b ldr r3, [r7, #4] 8005f82: 681b ldr r3, [r3, #0] 8005f84: 6e5a ldr r2, [r3, #100] @ 0x64 8005f86: 687b ldr r3, [r7, #4] 8005f88: 681b ldr r3, [r3, #0] 8005f8a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8005f8e: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8005f90: 687b ldr r3, [r7, #4] 8005f92: 681b ldr r3, [r3, #0] 8005f94: 6e9b ldr r3, [r3, #104] @ 0x68 8005f96: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8005f9a: 683b ldr r3, [r7, #0] 8005f9c: 681b ldr r3, [r3, #0] 8005f9e: 069b lsls r3, r3, #26 8005fa0: 429a cmp r2, r3 8005fa2: d107 bne.n 8005fb4 { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 8005fa4: 687b ldr r3, [r7, #4] 8005fa6: 681b ldr r3, [r3, #0] 8005fa8: 6e9a ldr r2, [r3, #104] @ 0x68 8005faa: 687b ldr r3, [r7, #4] 8005fac: 681b ldr r3, [r3, #0] 8005fae: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8005fb2: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8005fb4: 687b ldr r3, [r7, #4] 8005fb6: 681b ldr r3, [r3, #0] 8005fb8: 6edb ldr r3, [r3, #108] @ 0x6c 8005fba: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8005fbe: 683b ldr r3, [r7, #0] 8005fc0: 681b ldr r3, [r3, #0] 8005fc2: 069b lsls r3, r3, #26 8005fc4: 429a cmp r2, r3 8005fc6: d107 bne.n 8005fd8 { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8005fc8: 687b ldr r3, [r7, #4] 8005fca: 681b ldr r3, [r3, #0] 8005fcc: 6eda ldr r2, [r3, #108] @ 0x6c 8005fce: 687b ldr r3, [r7, #4] 8005fd0: 681b ldr r3, [r3, #0] 8005fd2: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8005fd6: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8005fd8: 687b ldr r3, [r7, #4] 8005fda: 681b ldr r3, [r3, #0] 8005fdc: 4618 mov r0, r3 8005fde: f7ff fbfd bl 80057dc 8005fe2: 4603 mov r3, r0 8005fe4: 2b00 cmp r3, #0 8005fe6: f040 8211 bne.w 800640c { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 8005fea: 687b ldr r3, [r7, #4] 8005fec: 6818 ldr r0, [r3, #0] 8005fee: 683b ldr r3, [r7, #0] 8005ff0: 6819 ldr r1, [r3, #0] 8005ff2: 683b ldr r3, [r7, #0] 8005ff4: 68db ldr r3, [r3, #12] 8005ff6: 461a mov r2, r3 8005ff8: f7ff fb48 bl 800568c /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 8005ffc: 683b ldr r3, [r7, #0] 8005ffe: 68db ldr r3, [r3, #12] 8006000: 4aa1 ldr r2, [pc, #644] @ (8006288 ) 8006002: 4293 cmp r3, r2 8006004: f040 812e bne.w 8006264 { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006008: 687b ldr r3, [r7, #4] 800600a: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 800600c: 683b ldr r3, [r7, #0] 800600e: 681b ldr r3, [r3, #0] 8006010: f3c3 0313 ubfx r3, r3, #0, #20 8006014: 2b00 cmp r3, #0 8006016: d10b bne.n 8006030 8006018: 683b ldr r3, [r7, #0] 800601a: 681b ldr r3, [r3, #0] 800601c: 0e9b lsrs r3, r3, #26 800601e: 3301 adds r3, #1 8006020: f003 031f and.w r3, r3, #31 8006024: 2b09 cmp r3, #9 8006026: bf94 ite ls 8006028: 2301 movls r3, #1 800602a: 2300 movhi r3, #0 800602c: b2db uxtb r3, r3 800602e: e019 b.n 8006064 8006030: 683b ldr r3, [r7, #0] 8006032: 681b ldr r3, [r3, #0] 8006034: 65bb str r3, [r7, #88] @ 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006036: 6dbb ldr r3, [r7, #88] @ 0x58 8006038: fa93 f3a3 rbit r3, r3 800603c: 657b str r3, [r7, #84] @ 0x54 return result; 800603e: 6d7b ldr r3, [r7, #84] @ 0x54 8006040: 65fb str r3, [r7, #92] @ 0x5c if (value == 0U) 8006042: 6dfb ldr r3, [r7, #92] @ 0x5c 8006044: 2b00 cmp r3, #0 8006046: d101 bne.n 800604c return 32U; 8006048: 2320 movs r3, #32 800604a: e003 b.n 8006054 return __builtin_clz(value); 800604c: 6dfb ldr r3, [r7, #92] @ 0x5c 800604e: fab3 f383 clz r3, r3 8006052: b2db uxtb r3, r3 8006054: 3301 adds r3, #1 8006056: f003 031f and.w r3, r3, #31 800605a: 2b09 cmp r3, #9 800605c: bf94 ite ls 800605e: 2301 movls r3, #1 8006060: 2300 movhi r3, #0 8006062: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006064: 2b00 cmp r3, #0 8006066: d079 beq.n 800615c (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006068: 683b ldr r3, [r7, #0] 800606a: 681b ldr r3, [r3, #0] 800606c: f3c3 0313 ubfx r3, r3, #0, #20 8006070: 2b00 cmp r3, #0 8006072: d107 bne.n 8006084 8006074: 683b ldr r3, [r7, #0] 8006076: 681b ldr r3, [r3, #0] 8006078: 0e9b lsrs r3, r3, #26 800607a: 3301 adds r3, #1 800607c: 069b lsls r3, r3, #26 800607e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006082: e015 b.n 80060b0 8006084: 683b ldr r3, [r7, #0] 8006086: 681b ldr r3, [r3, #0] 8006088: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800608a: 6cfb ldr r3, [r7, #76] @ 0x4c 800608c: fa93 f3a3 rbit r3, r3 8006090: 64bb str r3, [r7, #72] @ 0x48 return result; 8006092: 6cbb ldr r3, [r7, #72] @ 0x48 8006094: 653b str r3, [r7, #80] @ 0x50 if (value == 0U) 8006096: 6d3b ldr r3, [r7, #80] @ 0x50 8006098: 2b00 cmp r3, #0 800609a: d101 bne.n 80060a0 return 32U; 800609c: 2320 movs r3, #32 800609e: e003 b.n 80060a8 return __builtin_clz(value); 80060a0: 6d3b ldr r3, [r7, #80] @ 0x50 80060a2: fab3 f383 clz r3, r3 80060a6: b2db uxtb r3, r3 80060a8: 3301 adds r3, #1 80060aa: 069b lsls r3, r3, #26 80060ac: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80060b0: 683b ldr r3, [r7, #0] 80060b2: 681b ldr r3, [r3, #0] 80060b4: f3c3 0313 ubfx r3, r3, #0, #20 80060b8: 2b00 cmp r3, #0 80060ba: d109 bne.n 80060d0 80060bc: 683b ldr r3, [r7, #0] 80060be: 681b ldr r3, [r3, #0] 80060c0: 0e9b lsrs r3, r3, #26 80060c2: 3301 adds r3, #1 80060c4: f003 031f and.w r3, r3, #31 80060c8: 2101 movs r1, #1 80060ca: fa01 f303 lsl.w r3, r1, r3 80060ce: e017 b.n 8006100 80060d0: 683b ldr r3, [r7, #0] 80060d2: 681b ldr r3, [r3, #0] 80060d4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80060d6: 6c3b ldr r3, [r7, #64] @ 0x40 80060d8: fa93 f3a3 rbit r3, r3 80060dc: 63fb str r3, [r7, #60] @ 0x3c return result; 80060de: 6bfb ldr r3, [r7, #60] @ 0x3c 80060e0: 647b str r3, [r7, #68] @ 0x44 if (value == 0U) 80060e2: 6c7b ldr r3, [r7, #68] @ 0x44 80060e4: 2b00 cmp r3, #0 80060e6: d101 bne.n 80060ec return 32U; 80060e8: 2320 movs r3, #32 80060ea: e003 b.n 80060f4 return __builtin_clz(value); 80060ec: 6c7b ldr r3, [r7, #68] @ 0x44 80060ee: fab3 f383 clz r3, r3 80060f2: b2db uxtb r3, r3 80060f4: 3301 adds r3, #1 80060f6: f003 031f and.w r3, r3, #31 80060fa: 2101 movs r1, #1 80060fc: fa01 f303 lsl.w r3, r1, r3 8006100: ea42 0103 orr.w r1, r2, r3 8006104: 683b ldr r3, [r7, #0] 8006106: 681b ldr r3, [r3, #0] 8006108: f3c3 0313 ubfx r3, r3, #0, #20 800610c: 2b00 cmp r3, #0 800610e: d10a bne.n 8006126 8006110: 683b ldr r3, [r7, #0] 8006112: 681b ldr r3, [r3, #0] 8006114: 0e9b lsrs r3, r3, #26 8006116: 3301 adds r3, #1 8006118: f003 021f and.w r2, r3, #31 800611c: 4613 mov r3, r2 800611e: 005b lsls r3, r3, #1 8006120: 4413 add r3, r2 8006122: 051b lsls r3, r3, #20 8006124: e018 b.n 8006158 8006126: 683b ldr r3, [r7, #0] 8006128: 681b ldr r3, [r3, #0] 800612a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800612c: 6b7b ldr r3, [r7, #52] @ 0x34 800612e: fa93 f3a3 rbit r3, r3 8006132: 633b str r3, [r7, #48] @ 0x30 return result; 8006134: 6b3b ldr r3, [r7, #48] @ 0x30 8006136: 63bb str r3, [r7, #56] @ 0x38 if (value == 0U) 8006138: 6bbb ldr r3, [r7, #56] @ 0x38 800613a: 2b00 cmp r3, #0 800613c: d101 bne.n 8006142 return 32U; 800613e: 2320 movs r3, #32 8006140: e003 b.n 800614a return __builtin_clz(value); 8006142: 6bbb ldr r3, [r7, #56] @ 0x38 8006144: fab3 f383 clz r3, r3 8006148: b2db uxtb r3, r3 800614a: 3301 adds r3, #1 800614c: f003 021f and.w r2, r3, #31 8006150: 4613 mov r3, r2 8006152: 005b lsls r3, r3, #1 8006154: 4413 add r3, r2 8006156: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006158: 430b orrs r3, r1 800615a: e07e b.n 800625a (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 800615c: 683b ldr r3, [r7, #0] 800615e: 681b ldr r3, [r3, #0] 8006160: f3c3 0313 ubfx r3, r3, #0, #20 8006164: 2b00 cmp r3, #0 8006166: d107 bne.n 8006178 8006168: 683b ldr r3, [r7, #0] 800616a: 681b ldr r3, [r3, #0] 800616c: 0e9b lsrs r3, r3, #26 800616e: 3301 adds r3, #1 8006170: 069b lsls r3, r3, #26 8006172: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006176: e015 b.n 80061a4 8006178: 683b ldr r3, [r7, #0] 800617a: 681b ldr r3, [r3, #0] 800617c: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800617e: 6abb ldr r3, [r7, #40] @ 0x28 8006180: fa93 f3a3 rbit r3, r3 8006184: 627b str r3, [r7, #36] @ 0x24 return result; 8006186: 6a7b ldr r3, [r7, #36] @ 0x24 8006188: 62fb str r3, [r7, #44] @ 0x2c if (value == 0U) 800618a: 6afb ldr r3, [r7, #44] @ 0x2c 800618c: 2b00 cmp r3, #0 800618e: d101 bne.n 8006194 return 32U; 8006190: 2320 movs r3, #32 8006192: e003 b.n 800619c return __builtin_clz(value); 8006194: 6afb ldr r3, [r7, #44] @ 0x2c 8006196: fab3 f383 clz r3, r3 800619a: b2db uxtb r3, r3 800619c: 3301 adds r3, #1 800619e: 069b lsls r3, r3, #26 80061a0: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80061a4: 683b ldr r3, [r7, #0] 80061a6: 681b ldr r3, [r3, #0] 80061a8: f3c3 0313 ubfx r3, r3, #0, #20 80061ac: 2b00 cmp r3, #0 80061ae: d109 bne.n 80061c4 80061b0: 683b ldr r3, [r7, #0] 80061b2: 681b ldr r3, [r3, #0] 80061b4: 0e9b lsrs r3, r3, #26 80061b6: 3301 adds r3, #1 80061b8: f003 031f and.w r3, r3, #31 80061bc: 2101 movs r1, #1 80061be: fa01 f303 lsl.w r3, r1, r3 80061c2: e017 b.n 80061f4 80061c4: 683b ldr r3, [r7, #0] 80061c6: 681b ldr r3, [r3, #0] 80061c8: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80061ca: 69fb ldr r3, [r7, #28] 80061cc: fa93 f3a3 rbit r3, r3 80061d0: 61bb str r3, [r7, #24] return result; 80061d2: 69bb ldr r3, [r7, #24] 80061d4: 623b str r3, [r7, #32] if (value == 0U) 80061d6: 6a3b ldr r3, [r7, #32] 80061d8: 2b00 cmp r3, #0 80061da: d101 bne.n 80061e0 return 32U; 80061dc: 2320 movs r3, #32 80061de: e003 b.n 80061e8 return __builtin_clz(value); 80061e0: 6a3b ldr r3, [r7, #32] 80061e2: fab3 f383 clz r3, r3 80061e6: b2db uxtb r3, r3 80061e8: 3301 adds r3, #1 80061ea: f003 031f and.w r3, r3, #31 80061ee: 2101 movs r1, #1 80061f0: fa01 f303 lsl.w r3, r1, r3 80061f4: ea42 0103 orr.w r1, r2, r3 80061f8: 683b ldr r3, [r7, #0] 80061fa: 681b ldr r3, [r3, #0] 80061fc: f3c3 0313 ubfx r3, r3, #0, #20 8006200: 2b00 cmp r3, #0 8006202: d10d bne.n 8006220 8006204: 683b ldr r3, [r7, #0] 8006206: 681b ldr r3, [r3, #0] 8006208: 0e9b lsrs r3, r3, #26 800620a: 3301 adds r3, #1 800620c: f003 021f and.w r2, r3, #31 8006210: 4613 mov r3, r2 8006212: 005b lsls r3, r3, #1 8006214: 4413 add r3, r2 8006216: 3b1e subs r3, #30 8006218: 051b lsls r3, r3, #20 800621a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 800621e: e01b b.n 8006258 8006220: 683b ldr r3, [r7, #0] 8006222: 681b ldr r3, [r3, #0] 8006224: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006226: 693b ldr r3, [r7, #16] 8006228: fa93 f3a3 rbit r3, r3 800622c: 60fb str r3, [r7, #12] return result; 800622e: 68fb ldr r3, [r7, #12] 8006230: 617b str r3, [r7, #20] if (value == 0U) 8006232: 697b ldr r3, [r7, #20] 8006234: 2b00 cmp r3, #0 8006236: d101 bne.n 800623c return 32U; 8006238: 2320 movs r3, #32 800623a: e003 b.n 8006244 return __builtin_clz(value); 800623c: 697b ldr r3, [r7, #20] 800623e: fab3 f383 clz r3, r3 8006242: b2db uxtb r3, r3 8006244: 3301 adds r3, #1 8006246: f003 021f and.w r2, r3, #31 800624a: 4613 mov r3, r2 800624c: 005b lsls r3, r3, #1 800624e: 4413 add r3, r2 8006250: 3b1e subs r3, #30 8006252: 051b lsls r3, r3, #20 8006254: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006258: 430b orrs r3, r1 800625a: 683a ldr r2, [r7, #0] 800625c: 6892 ldr r2, [r2, #8] 800625e: 4619 mov r1, r3 8006260: f7ff f9e8 bl 8005634 /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8006264: 683b ldr r3, [r7, #0] 8006266: 681b ldr r3, [r3, #0] 8006268: 2b00 cmp r3, #0 800626a: f280 80cf bge.w 800640c { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800626e: 687b ldr r3, [r7, #4] 8006270: 681b ldr r3, [r3, #0] 8006272: 4a06 ldr r2, [pc, #24] @ (800628c ) 8006274: 4293 cmp r3, r2 8006276: d004 beq.n 8006282 8006278: 687b ldr r3, [r7, #4] 800627a: 681b ldr r3, [r3, #0] 800627c: 4a04 ldr r2, [pc, #16] @ (8006290 ) 800627e: 4293 cmp r3, r2 8006280: d10a bne.n 8006298 8006282: 4b04 ldr r3, [pc, #16] @ (8006294 ) 8006284: e009 b.n 800629a 8006286: bf00 nop 8006288: 47ff0000 .word 0x47ff0000 800628c: 40022000 .word 0x40022000 8006290: 40022100 .word 0x40022100 8006294: 40022300 .word 0x40022300 8006298: 4b61 ldr r3, [pc, #388] @ (8006420 ) 800629a: 4618 mov r0, r3 800629c: f7ff f916 bl 80054cc 80062a0: 66f8 str r0, [r7, #108] @ 0x6c /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80062a2: 687b ldr r3, [r7, #4] 80062a4: 681b ldr r3, [r3, #0] 80062a6: 4a5f ldr r2, [pc, #380] @ (8006424 ) 80062a8: 4293 cmp r3, r2 80062aa: d004 beq.n 80062b6 80062ac: 687b ldr r3, [r7, #4] 80062ae: 681b ldr r3, [r3, #0] 80062b0: 4a5d ldr r2, [pc, #372] @ (8006428 ) 80062b2: 4293 cmp r3, r2 80062b4: d10e bne.n 80062d4 80062b6: 485b ldr r0, [pc, #364] @ (8006424 ) 80062b8: f7ff fa90 bl 80057dc 80062bc: 4604 mov r4, r0 80062be: 485a ldr r0, [pc, #360] @ (8006428 ) 80062c0: f7ff fa8c bl 80057dc 80062c4: 4603 mov r3, r0 80062c6: 4323 orrs r3, r4 80062c8: 2b00 cmp r3, #0 80062ca: bf0c ite eq 80062cc: 2301 moveq r3, #1 80062ce: 2300 movne r3, #0 80062d0: b2db uxtb r3, r3 80062d2: e008 b.n 80062e6 80062d4: 4855 ldr r0, [pc, #340] @ (800642c ) 80062d6: f7ff fa81 bl 80057dc 80062da: 4603 mov r3, r0 80062dc: 2b00 cmp r3, #0 80062de: bf0c ite eq 80062e0: 2301 moveq r3, #1 80062e2: 2300 movne r3, #0 80062e4: b2db uxtb r3, r3 80062e6: 2b00 cmp r3, #0 80062e8: d07d beq.n 80063e6 { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 80062ea: 683b ldr r3, [r7, #0] 80062ec: 681b ldr r3, [r3, #0] 80062ee: 4a50 ldr r2, [pc, #320] @ (8006430 ) 80062f0: 4293 cmp r3, r2 80062f2: d130 bne.n 8006356 80062f4: 6efb ldr r3, [r7, #108] @ 0x6c 80062f6: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80062fa: 2b00 cmp r3, #0 80062fc: d12b bne.n 8006356 { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 80062fe: 687b ldr r3, [r7, #4] 8006300: 681b ldr r3, [r3, #0] 8006302: 4a4a ldr r2, [pc, #296] @ (800642c ) 8006304: 4293 cmp r3, r2 8006306: f040 8081 bne.w 800640c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 800630a: 687b ldr r3, [r7, #4] 800630c: 681b ldr r3, [r3, #0] 800630e: 4a45 ldr r2, [pc, #276] @ (8006424 ) 8006310: 4293 cmp r3, r2 8006312: d004 beq.n 800631e 8006314: 687b ldr r3, [r7, #4] 8006316: 681b ldr r3, [r3, #0] 8006318: 4a43 ldr r2, [pc, #268] @ (8006428 ) 800631a: 4293 cmp r3, r2 800631c: d101 bne.n 8006322 800631e: 4a45 ldr r2, [pc, #276] @ (8006434 ) 8006320: e000 b.n 8006324 8006322: 4a3f ldr r2, [pc, #252] @ (8006420 ) 8006324: 6efb ldr r3, [r7, #108] @ 0x6c 8006326: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800632a: 4619 mov r1, r3 800632c: 4610 mov r0, r2 800632e: f7ff f8ba bl 80054a6 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006332: 4b41 ldr r3, [pc, #260] @ (8006438 ) 8006334: 681b ldr r3, [r3, #0] 8006336: 099b lsrs r3, r3, #6 8006338: 4a40 ldr r2, [pc, #256] @ (800643c ) 800633a: fba2 2303 umull r2, r3, r2, r3 800633e: 099b lsrs r3, r3, #6 8006340: 3301 adds r3, #1 8006342: 005b lsls r3, r3, #1 8006344: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006346: e002 b.n 800634e { wait_loop_index--; 8006348: 68bb ldr r3, [r7, #8] 800634a: 3b01 subs r3, #1 800634c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 800634e: 68bb ldr r3, [r7, #8] 8006350: 2b00 cmp r3, #0 8006352: d1f9 bne.n 8006348 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006354: e05a b.n 800640c } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8006356: 683b ldr r3, [r7, #0] 8006358: 681b ldr r3, [r3, #0] 800635a: 4a39 ldr r2, [pc, #228] @ (8006440 ) 800635c: 4293 cmp r3, r2 800635e: d11e bne.n 800639e 8006360: 6efb ldr r3, [r7, #108] @ 0x6c 8006362: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8006366: 2b00 cmp r3, #0 8006368: d119 bne.n 800639e { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800636a: 687b ldr r3, [r7, #4] 800636c: 681b ldr r3, [r3, #0] 800636e: 4a2f ldr r2, [pc, #188] @ (800642c ) 8006370: 4293 cmp r3, r2 8006372: d14b bne.n 800640c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8006374: 687b ldr r3, [r7, #4] 8006376: 681b ldr r3, [r3, #0] 8006378: 4a2a ldr r2, [pc, #168] @ (8006424 ) 800637a: 4293 cmp r3, r2 800637c: d004 beq.n 8006388 800637e: 687b ldr r3, [r7, #4] 8006380: 681b ldr r3, [r3, #0] 8006382: 4a29 ldr r2, [pc, #164] @ (8006428 ) 8006384: 4293 cmp r3, r2 8006386: d101 bne.n 800638c 8006388: 4a2a ldr r2, [pc, #168] @ (8006434 ) 800638a: e000 b.n 800638e 800638c: 4a24 ldr r2, [pc, #144] @ (8006420 ) 800638e: 6efb ldr r3, [r7, #108] @ 0x6c 8006390: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8006394: 4619 mov r1, r3 8006396: 4610 mov r0, r2 8006398: f7ff f885 bl 80054a6 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 800639c: e036 b.n 800640c } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 800639e: 683b ldr r3, [r7, #0] 80063a0: 681b ldr r3, [r3, #0] 80063a2: 4a28 ldr r2, [pc, #160] @ (8006444 ) 80063a4: 4293 cmp r3, r2 80063a6: d131 bne.n 800640c 80063a8: 6efb ldr r3, [r7, #108] @ 0x6c 80063aa: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80063ae: 2b00 cmp r3, #0 80063b0: d12c bne.n 800640c { if (ADC_VREFINT_INSTANCE(hadc)) 80063b2: 687b ldr r3, [r7, #4] 80063b4: 681b ldr r3, [r3, #0] 80063b6: 4a1d ldr r2, [pc, #116] @ (800642c ) 80063b8: 4293 cmp r3, r2 80063ba: d127 bne.n 800640c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 80063bc: 687b ldr r3, [r7, #4] 80063be: 681b ldr r3, [r3, #0] 80063c0: 4a18 ldr r2, [pc, #96] @ (8006424 ) 80063c2: 4293 cmp r3, r2 80063c4: d004 beq.n 80063d0 80063c6: 687b ldr r3, [r7, #4] 80063c8: 681b ldr r3, [r3, #0] 80063ca: 4a17 ldr r2, [pc, #92] @ (8006428 ) 80063cc: 4293 cmp r3, r2 80063ce: d101 bne.n 80063d4 80063d0: 4a18 ldr r2, [pc, #96] @ (8006434 ) 80063d2: e000 b.n 80063d6 80063d4: 4a12 ldr r2, [pc, #72] @ (8006420 ) 80063d6: 6efb ldr r3, [r7, #108] @ 0x6c 80063d8: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 80063dc: 4619 mov r1, r3 80063de: 4610 mov r0, r2 80063e0: f7ff f861 bl 80054a6 80063e4: e012 b.n 800640c /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80063e6: 687b ldr r3, [r7, #4] 80063e8: 6d5b ldr r3, [r3, #84] @ 0x54 80063ea: f043 0220 orr.w r2, r3, #32 80063ee: 687b ldr r3, [r7, #4] 80063f0: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80063f2: 2301 movs r3, #1 80063f4: f887 307f strb.w r3, [r7, #127] @ 0x7f 80063f8: e008 b.n 800640c /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 80063fa: 687b ldr r3, [r7, #4] 80063fc: 6d5b ldr r3, [r3, #84] @ 0x54 80063fe: f043 0220 orr.w r2, r3, #32 8006402: 687b ldr r3, [r7, #4] 8006404: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006406: 2301 movs r3, #1 8006408: f887 307f strb.w r3, [r7, #127] @ 0x7f } /* Process unlocked */ __HAL_UNLOCK(hadc); 800640c: 687b ldr r3, [r7, #4] 800640e: 2200 movs r2, #0 8006410: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006414: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8006418: 4618 mov r0, r3 800641a: 3784 adds r7, #132 @ 0x84 800641c: 46bd mov sp, r7 800641e: bd90 pop {r4, r7, pc} 8006420: 58026300 .word 0x58026300 8006424: 40022000 .word 0x40022000 8006428: 40022100 .word 0x40022100 800642c: 58026000 .word 0x58026000 8006430: cb840000 .word 0xcb840000 8006434: 40022300 .word 0x40022300 8006438: 24000034 .word 0x24000034 800643c: 053e2d63 .word 0x053e2d63 8006440: c7520000 .word 0xc7520000 8006444: cfb80000 .word 0xcfb80000 08006448 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8006448: b580 push {r7, lr} 800644a: b084 sub sp, #16 800644c: af00 add r7, sp, #0 800644e: 6078 str r0, [r7, #4] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006450: 687b ldr r3, [r7, #4] 8006452: 681b ldr r3, [r3, #0] 8006454: 4618 mov r0, r3 8006456: f7ff f9c1 bl 80057dc 800645a: 4603 mov r3, r0 800645c: 2b00 cmp r3, #0 800645e: d16e bne.n 800653e { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8006460: 687b ldr r3, [r7, #4] 8006462: 681b ldr r3, [r3, #0] 8006464: 689a ldr r2, [r3, #8] 8006466: 4b38 ldr r3, [pc, #224] @ (8006548 ) 8006468: 4013 ands r3, r2 800646a: 2b00 cmp r3, #0 800646c: d00d beq.n 800648a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800646e: 687b ldr r3, [r7, #4] 8006470: 6d5b ldr r3, [r3, #84] @ 0x54 8006472: f043 0210 orr.w r2, r3, #16 8006476: 687b ldr r3, [r7, #4] 8006478: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800647a: 687b ldr r3, [r7, #4] 800647c: 6d9b ldr r3, [r3, #88] @ 0x58 800647e: f043 0201 orr.w r2, r3, #1 8006482: 687b ldr r3, [r7, #4] 8006484: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006486: 2301 movs r3, #1 8006488: e05a b.n 8006540 } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 800648a: 687b ldr r3, [r7, #4] 800648c: 681b ldr r3, [r3, #0] 800648e: 4618 mov r0, r3 8006490: f7ff f97c bl 800578c /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 8006494: f7fe ffa2 bl 80053dc 8006498: 60f8 str r0, [r7, #12] /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800649a: 687b ldr r3, [r7, #4] 800649c: 681b ldr r3, [r3, #0] 800649e: 4a2b ldr r2, [pc, #172] @ (800654c ) 80064a0: 4293 cmp r3, r2 80064a2: d004 beq.n 80064ae 80064a4: 687b ldr r3, [r7, #4] 80064a6: 681b ldr r3, [r3, #0] 80064a8: 4a29 ldr r2, [pc, #164] @ (8006550 ) 80064aa: 4293 cmp r3, r2 80064ac: d101 bne.n 80064b2 80064ae: 4b29 ldr r3, [pc, #164] @ (8006554 ) 80064b0: e000 b.n 80064b4 80064b2: 4b29 ldr r3, [pc, #164] @ (8006558 ) 80064b4: 4618 mov r0, r3 80064b6: f7ff f90d bl 80056d4 80064ba: 60b8 str r0, [r7, #8] if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 80064bc: 687b ldr r3, [r7, #4] 80064be: 681b ldr r3, [r3, #0] 80064c0: 4a23 ldr r2, [pc, #140] @ (8006550 ) 80064c2: 4293 cmp r3, r2 80064c4: d002 beq.n 80064cc 80064c6: 687b ldr r3, [r7, #4] 80064c8: 681b ldr r3, [r3, #0] 80064ca: e000 b.n 80064ce 80064cc: 4b1f ldr r3, [pc, #124] @ (800654c ) 80064ce: 687a ldr r2, [r7, #4] 80064d0: 6812 ldr r2, [r2, #0] 80064d2: 4293 cmp r3, r2 80064d4: d02c beq.n 8006530 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80064d6: 68bb ldr r3, [r7, #8] 80064d8: 2b00 cmp r3, #0 80064da: d130 bne.n 800653e ) { while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 80064dc: e028 b.n 8006530 The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80064de: 687b ldr r3, [r7, #4] 80064e0: 681b ldr r3, [r3, #0] 80064e2: 4618 mov r0, r3 80064e4: f7ff f97a bl 80057dc 80064e8: 4603 mov r3, r0 80064ea: 2b00 cmp r3, #0 80064ec: d104 bne.n 80064f8 { LL_ADC_Enable(hadc->Instance); 80064ee: 687b ldr r3, [r7, #4] 80064f0: 681b ldr r3, [r3, #0] 80064f2: 4618 mov r0, r3 80064f4: f7ff f94a bl 800578c } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 80064f8: f7fe ff70 bl 80053dc 80064fc: 4602 mov r2, r0 80064fe: 68fb ldr r3, [r7, #12] 8006500: 1ad3 subs r3, r2, r3 8006502: 2b02 cmp r3, #2 8006504: d914 bls.n 8006530 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006506: 687b ldr r3, [r7, #4] 8006508: 681b ldr r3, [r3, #0] 800650a: 681b ldr r3, [r3, #0] 800650c: f003 0301 and.w r3, r3, #1 8006510: 2b01 cmp r3, #1 8006512: d00d beq.n 8006530 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006514: 687b ldr r3, [r7, #4] 8006516: 6d5b ldr r3, [r3, #84] @ 0x54 8006518: f043 0210 orr.w r2, r3, #16 800651c: 687b ldr r3, [r7, #4] 800651e: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006520: 687b ldr r3, [r7, #4] 8006522: 6d9b ldr r3, [r3, #88] @ 0x58 8006524: f043 0201 orr.w r2, r3, #1 8006528: 687b ldr r3, [r7, #4] 800652a: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 800652c: 2301 movs r3, #1 800652e: e007 b.n 8006540 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006530: 687b ldr r3, [r7, #4] 8006532: 681b ldr r3, [r3, #0] 8006534: 681b ldr r3, [r3, #0] 8006536: f003 0301 and.w r3, r3, #1 800653a: 2b01 cmp r3, #1 800653c: d1cf bne.n 80064de } } } /* Return HAL status */ return HAL_OK; 800653e: 2300 movs r3, #0 } 8006540: 4618 mov r0, r3 8006542: 3710 adds r7, #16 8006544: 46bd mov sp, r7 8006546: bd80 pop {r7, pc} 8006548: 8000003f .word 0x8000003f 800654c: 40022000 .word 0x40022000 8006550: 40022100 .word 0x40022100 8006554: 40022300 .word 0x40022300 8006558: 58026300 .word 0x58026300 0800655c : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 800655c: b580 push {r7, lr} 800655e: b084 sub sp, #16 8006560: af00 add r7, sp, #0 8006562: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8006564: 687b ldr r3, [r7, #4] 8006566: 681b ldr r3, [r3, #0] 8006568: 4618 mov r0, r3 800656a: f7ff f94a bl 8005802 800656e: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8006570: 687b ldr r3, [r7, #4] 8006572: 681b ldr r3, [r3, #0] 8006574: 4618 mov r0, r3 8006576: f7ff f931 bl 80057dc 800657a: 4603 mov r3, r0 800657c: 2b00 cmp r3, #0 800657e: d047 beq.n 8006610 && (tmp_adc_is_disable_on_going == 0UL) 8006580: 68fb ldr r3, [r7, #12] 8006582: 2b00 cmp r3, #0 8006584: d144 bne.n 8006610 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8006586: 687b ldr r3, [r7, #4] 8006588: 681b ldr r3, [r3, #0] 800658a: 689b ldr r3, [r3, #8] 800658c: f003 030d and.w r3, r3, #13 8006590: 2b01 cmp r3, #1 8006592: d10c bne.n 80065ae { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8006594: 687b ldr r3, [r7, #4] 8006596: 681b ldr r3, [r3, #0] 8006598: 4618 mov r0, r3 800659a: f7ff f90b bl 80057b4 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 800659e: 687b ldr r3, [r7, #4] 80065a0: 681b ldr r3, [r3, #0] 80065a2: 2203 movs r2, #3 80065a4: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 80065a6: f7fe ff19 bl 80053dc 80065aa: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80065ac: e029 b.n 8006602 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80065ae: 687b ldr r3, [r7, #4] 80065b0: 6d5b ldr r3, [r3, #84] @ 0x54 80065b2: f043 0210 orr.w r2, r3, #16 80065b6: 687b ldr r3, [r7, #4] 80065b8: 655a str r2, [r3, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80065ba: 687b ldr r3, [r7, #4] 80065bc: 6d9b ldr r3, [r3, #88] @ 0x58 80065be: f043 0201 orr.w r2, r3, #1 80065c2: 687b ldr r3, [r7, #4] 80065c4: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 80065c6: 2301 movs r3, #1 80065c8: e023 b.n 8006612 { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 80065ca: f7fe ff07 bl 80053dc 80065ce: 4602 mov r2, r0 80065d0: 68bb ldr r3, [r7, #8] 80065d2: 1ad3 subs r3, r2, r3 80065d4: 2b02 cmp r3, #2 80065d6: d914 bls.n 8006602 { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 80065d8: 687b ldr r3, [r7, #4] 80065da: 681b ldr r3, [r3, #0] 80065dc: 689b ldr r3, [r3, #8] 80065de: f003 0301 and.w r3, r3, #1 80065e2: 2b00 cmp r3, #0 80065e4: d00d beq.n 8006602 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80065e6: 687b ldr r3, [r7, #4] 80065e8: 6d5b ldr r3, [r3, #84] @ 0x54 80065ea: f043 0210 orr.w r2, r3, #16 80065ee: 687b ldr r3, [r7, #4] 80065f0: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 80065f2: 687b ldr r3, [r7, #4] 80065f4: 6d9b ldr r3, [r3, #88] @ 0x58 80065f6: f043 0201 orr.w r2, r3, #1 80065fa: 687b ldr r3, [r7, #4] 80065fc: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 80065fe: 2301 movs r3, #1 8006600: e007 b.n 8006612 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006602: 687b ldr r3, [r7, #4] 8006604: 681b ldr r3, [r3, #0] 8006606: 689b ldr r3, [r3, #8] 8006608: f003 0301 and.w r3, r3, #1 800660c: 2b00 cmp r3, #0 800660e: d1dc bne.n 80065ca } } } /* Return HAL status */ return HAL_OK; 8006610: 2300 movs r3, #0 } 8006612: 4618 mov r0, r3 8006614: 3710 adds r7, #16 8006616: 46bd mov sp, r7 8006618: bd80 pop {r7, pc} 0800661a : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800661a: b580 push {r7, lr} 800661c: b084 sub sp, #16 800661e: af00 add r7, sp, #0 8006620: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006622: 687b ldr r3, [r7, #4] 8006624: 6b9b ldr r3, [r3, #56] @ 0x38 8006626: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8006628: 68fb ldr r3, [r7, #12] 800662a: 6d5b ldr r3, [r3, #84] @ 0x54 800662c: f003 0350 and.w r3, r3, #80 @ 0x50 8006630: 2b00 cmp r3, #0 8006632: d14b bne.n 80066cc { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8006634: 68fb ldr r3, [r7, #12] 8006636: 6d5b ldr r3, [r3, #84] @ 0x54 8006638: f443 7200 orr.w r2, r3, #512 @ 0x200 800663c: 68fb ldr r3, [r7, #12] 800663e: 655a str r2, [r3, #84] @ 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8006640: 68fb ldr r3, [r7, #12] 8006642: 681b ldr r3, [r3, #0] 8006644: 681b ldr r3, [r3, #0] 8006646: f003 0308 and.w r3, r3, #8 800664a: 2b00 cmp r3, #0 800664c: d021 beq.n 8006692 { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 800664e: 68fb ldr r3, [r7, #12] 8006650: 681b ldr r3, [r3, #0] 8006652: 4618 mov r0, r3 8006654: f7fe ff9c bl 8005590 8006658: 4603 mov r3, r0 800665a: 2b00 cmp r3, #0 800665c: d032 beq.n 80066c4 { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 800665e: 68fb ldr r3, [r7, #12] 8006660: 681b ldr r3, [r3, #0] 8006662: 68db ldr r3, [r3, #12] 8006664: f403 5300 and.w r3, r3, #8192 @ 0x2000 8006668: 2b00 cmp r3, #0 800666a: d12b bne.n 80066c4 { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 800666c: 68fb ldr r3, [r7, #12] 800666e: 6d5b ldr r3, [r3, #84] @ 0x54 8006670: f423 7280 bic.w r2, r3, #256 @ 0x100 8006674: 68fb ldr r3, [r7, #12] 8006676: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 8006678: 68fb ldr r3, [r7, #12] 800667a: 6d5b ldr r3, [r3, #84] @ 0x54 800667c: f403 5380 and.w r3, r3, #4096 @ 0x1000 8006680: 2b00 cmp r3, #0 8006682: d11f bne.n 80066c4 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8006684: 68fb ldr r3, [r7, #12] 8006686: 6d5b ldr r3, [r3, #84] @ 0x54 8006688: f043 0201 orr.w r2, r3, #1 800668c: 68fb ldr r3, [r7, #12] 800668e: 655a str r2, [r3, #84] @ 0x54 8006690: e018 b.n 80066c4 } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 8006692: 68fb ldr r3, [r7, #12] 8006694: 681b ldr r3, [r3, #0] 8006696: 68db ldr r3, [r3, #12] 8006698: f003 0303 and.w r3, r3, #3 800669c: 2b00 cmp r3, #0 800669e: d111 bne.n 80066c4 { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80066a0: 68fb ldr r3, [r7, #12] 80066a2: 6d5b ldr r3, [r3, #84] @ 0x54 80066a4: f423 7280 bic.w r2, r3, #256 @ 0x100 80066a8: 68fb ldr r3, [r7, #12] 80066aa: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 80066ac: 68fb ldr r3, [r7, #12] 80066ae: 6d5b ldr r3, [r3, #84] @ 0x54 80066b0: f403 5380 and.w r3, r3, #4096 @ 0x1000 80066b4: 2b00 cmp r3, #0 80066b6: d105 bne.n 80066c4 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80066b8: 68fb ldr r3, [r7, #12] 80066ba: 6d5b ldr r3, [r3, #84] @ 0x54 80066bc: f043 0201 orr.w r2, r3, #1 80066c0: 68fb ldr r3, [r7, #12] 80066c2: 655a str r2, [r3, #84] @ 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 80066c4: 68f8 ldr r0, [r7, #12] 80066c6: f7fb f849 bl 800175c { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 80066ca: e00e b.n 80066ea if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 80066cc: 68fb ldr r3, [r7, #12] 80066ce: 6d5b ldr r3, [r3, #84] @ 0x54 80066d0: f003 0310 and.w r3, r3, #16 80066d4: 2b00 cmp r3, #0 80066d6: d003 beq.n 80066e0 HAL_ADC_ErrorCallback(hadc); 80066d8: 68f8 ldr r0, [r7, #12] 80066da: f7ff fb4f bl 8005d7c } 80066de: e004 b.n 80066ea hadc->DMA_Handle->XferErrorCallback(hdma); 80066e0: 68fb ldr r3, [r7, #12] 80066e2: 6cdb ldr r3, [r3, #76] @ 0x4c 80066e4: 6cdb ldr r3, [r3, #76] @ 0x4c 80066e6: 6878 ldr r0, [r7, #4] 80066e8: 4798 blx r3 } 80066ea: bf00 nop 80066ec: 3710 adds r7, #16 80066ee: 46bd mov sp, r7 80066f0: bd80 pop {r7, pc} 080066f2 : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 80066f2: b580 push {r7, lr} 80066f4: b084 sub sp, #16 80066f6: af00 add r7, sp, #0 80066f8: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 80066fa: 687b ldr r3, [r7, #4] 80066fc: 6b9b ldr r3, [r3, #56] @ 0x38 80066fe: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8006700: 68f8 ldr r0, [r7, #12] 8006702: f7ff fb31 bl 8005d68 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8006706: bf00 nop 8006708: 3710 adds r7, #16 800670a: 46bd mov sp, r7 800670c: bd80 pop {r7, pc} 0800670e : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800670e: b580 push {r7, lr} 8006710: b084 sub sp, #16 8006712: af00 add r7, sp, #0 8006714: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8006716: 687b ldr r3, [r7, #4] 8006718: 6b9b ldr r3, [r3, #56] @ 0x38 800671a: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800671c: 68fb ldr r3, [r7, #12] 800671e: 6d5b ldr r3, [r3, #84] @ 0x54 8006720: f043 0240 orr.w r2, r3, #64 @ 0x40 8006724: 68fb ldr r3, [r7, #12] 8006726: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8006728: 68fb ldr r3, [r7, #12] 800672a: 6d9b ldr r3, [r3, #88] @ 0x58 800672c: f043 0204 orr.w r2, r3, #4 8006730: 68fb ldr r3, [r7, #12] 8006732: 659a str r2, [r3, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8006734: 68f8 ldr r0, [r7, #12] 8006736: f7ff fb21 bl 8005d7c #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800673a: bf00 nop 800673c: 3710 adds r7, #16 800673e: 46bd mov sp, r7 8006740: bd80 pop {r7, pc} ... 08006744 : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 8006744: b580 push {r7, lr} 8006746: b084 sub sp, #16 8006748: af00 add r7, sp, #0 800674a: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 800674c: 687b ldr r3, [r7, #4] 800674e: 681b ldr r3, [r3, #0] 8006750: 4a7a ldr r2, [pc, #488] @ (800693c ) 8006752: 4293 cmp r3, r2 8006754: d004 beq.n 8006760 8006756: 687b ldr r3, [r7, #4] 8006758: 681b ldr r3, [r3, #0] 800675a: 4a79 ldr r2, [pc, #484] @ (8006940 ) 800675c: 4293 cmp r3, r2 800675e: d109 bne.n 8006774 8006760: 4b78 ldr r3, [pc, #480] @ (8006944 ) 8006762: 689b ldr r3, [r3, #8] 8006764: f403 3340 and.w r3, r3, #196608 @ 0x30000 8006768: 2b00 cmp r3, #0 800676a: bf14 ite ne 800676c: 2301 movne r3, #1 800676e: 2300 moveq r3, #0 8006770: b2db uxtb r3, r3 8006772: e008 b.n 8006786 8006774: 4b74 ldr r3, [pc, #464] @ (8006948 ) 8006776: 689b ldr r3, [r3, #8] 8006778: f403 3340 and.w r3, r3, #196608 @ 0x30000 800677c: 2b00 cmp r3, #0 800677e: bf14 ite ne 8006780: 2301 movne r3, #1 8006782: 2300 moveq r3, #0 8006784: b2db uxtb r3, r3 8006786: 2b00 cmp r3, #0 8006788: d01c beq.n 80067c4 { freq = HAL_RCC_GetHCLKFreq(); 800678a: f005 fae9 bl 800bd60 800678e: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8006790: 687b ldr r3, [r7, #4] 8006792: 685b ldr r3, [r3, #4] 8006794: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 8006798: d010 beq.n 80067bc 800679a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800679e: d873 bhi.n 8006888 80067a0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80067a4: d002 beq.n 80067ac 80067a6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80067aa: d16d bne.n 8006888 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 80067ac: 687b ldr r3, [r7, #4] 80067ae: 685b ldr r3, [r3, #4] 80067b0: 0c1b lsrs r3, r3, #16 80067b2: 68fa ldr r2, [r7, #12] 80067b4: fbb2 f3f3 udiv r3, r2, r3 80067b8: 60fb str r3, [r7, #12] break; 80067ba: e068 b.n 800688e case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 80067bc: 68fb ldr r3, [r7, #12] 80067be: 089b lsrs r3, r3, #2 80067c0: 60fb str r3, [r7, #12] break; 80067c2: e064 b.n 800688e break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 80067c4: f44f 2000 mov.w r0, #524288 @ 0x80000 80067c8: f04f 0100 mov.w r1, #0 80067cc: f006 fd54 bl 800d278 80067d0: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 80067d2: 687b ldr r3, [r7, #4] 80067d4: 685b ldr r3, [r3, #4] 80067d6: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 80067da: d051 beq.n 8006880 80067dc: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 80067e0: d854 bhi.n 800688c 80067e2: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 80067e6: d047 beq.n 8006878 80067e8: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 80067ec: d84e bhi.n 800688c 80067ee: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 80067f2: d03d beq.n 8006870 80067f4: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 80067f8: d848 bhi.n 800688c 80067fa: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80067fe: d033 beq.n 8006868 8006800: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8006804: d842 bhi.n 800688c 8006806: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 800680a: d029 beq.n 8006860 800680c: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8006810: d83c bhi.n 800688c 8006812: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8006816: d01a beq.n 800684e 8006818: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 800681c: d836 bhi.n 800688c 800681e: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8006822: d014 beq.n 800684e 8006824: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8006828: d830 bhi.n 800688c 800682a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800682e: d00e beq.n 800684e 8006830: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8006834: d82a bhi.n 800688c 8006836: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 800683a: d008 beq.n 800684e 800683c: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8006840: d824 bhi.n 800688c 8006842: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8006846: d002 beq.n 800684e 8006848: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 800684c: d11e bne.n 800688c case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 800684e: 687b ldr r3, [r7, #4] 8006850: 685b ldr r3, [r3, #4] 8006852: 0c9b lsrs r3, r3, #18 8006854: 005b lsls r3, r3, #1 8006856: 68fa ldr r2, [r7, #12] 8006858: fbb2 f3f3 udiv r3, r2, r3 800685c: 60fb str r3, [r7, #12] break; 800685e: e016 b.n 800688e case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 8006860: 68fb ldr r3, [r7, #12] 8006862: 091b lsrs r3, r3, #4 8006864: 60fb str r3, [r7, #12] break; 8006866: e012 b.n 800688e case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 8006868: 68fb ldr r3, [r7, #12] 800686a: 095b lsrs r3, r3, #5 800686c: 60fb str r3, [r7, #12] break; 800686e: e00e b.n 800688e case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 8006870: 68fb ldr r3, [r7, #12] 8006872: 099b lsrs r3, r3, #6 8006874: 60fb str r3, [r7, #12] break; 8006876: e00a b.n 800688e case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 8006878: 68fb ldr r3, [r7, #12] 800687a: 09db lsrs r3, r3, #7 800687c: 60fb str r3, [r7, #12] break; 800687e: e006 b.n 800688e case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 8006880: 68fb ldr r3, [r7, #12] 8006882: 0a1b lsrs r3, r3, #8 8006884: 60fb str r3, [r7, #12] break; 8006886: e002 b.n 800688e break; 8006888: bf00 nop 800688a: e000 b.n 800688e default: break; 800688c: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 800688e: f7fe fdb1 bl 80053f4 8006892: 4603 mov r3, r0 8006894: f241 0203 movw r2, #4099 @ 0x1003 8006898: 4293 cmp r3, r2 800689a: d815 bhi.n 80068c8 { if (freq > 20000000UL) 800689c: 68fb ldr r3, [r7, #12] 800689e: 4a2b ldr r2, [pc, #172] @ (800694c ) 80068a0: 4293 cmp r3, r2 80068a2: d908 bls.n 80068b6 { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80068a4: 687b ldr r3, [r7, #4] 80068a6: 681b ldr r3, [r3, #0] 80068a8: 689a ldr r2, [r3, #8] 80068aa: 687b ldr r3, [r7, #4] 80068ac: 681b ldr r3, [r3, #0] 80068ae: f442 7280 orr.w r2, r2, #256 @ 0x100 80068b2: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 80068b4: e03e b.n 8006934 CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80068b6: 687b ldr r3, [r7, #4] 80068b8: 681b ldr r3, [r3, #0] 80068ba: 689a ldr r2, [r3, #8] 80068bc: 687b ldr r3, [r7, #4] 80068be: 681b ldr r3, [r3, #0] 80068c0: f422 7280 bic.w r2, r2, #256 @ 0x100 80068c4: 609a str r2, [r3, #8] } 80068c6: e035 b.n 8006934 freq /= 2U; /* divider by 2 for Rev.V */ 80068c8: 68fb ldr r3, [r7, #12] 80068ca: 085b lsrs r3, r3, #1 80068cc: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 80068ce: 68fb ldr r3, [r7, #12] 80068d0: 4a1f ldr r2, [pc, #124] @ (8006950 ) 80068d2: 4293 cmp r3, r2 80068d4: d808 bhi.n 80068e8 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 80068d6: 687b ldr r3, [r7, #4] 80068d8: 681b ldr r3, [r3, #0] 80068da: 689a ldr r2, [r3, #8] 80068dc: 687b ldr r3, [r7, #4] 80068de: 681b ldr r3, [r3, #0] 80068e0: f422 7240 bic.w r2, r2, #768 @ 0x300 80068e4: 609a str r2, [r3, #8] } 80068e6: e025 b.n 8006934 else if (freq <= 12500000UL) 80068e8: 68fb ldr r3, [r7, #12] 80068ea: 4a1a ldr r2, [pc, #104] @ (8006954 ) 80068ec: 4293 cmp r3, r2 80068ee: d80a bhi.n 8006906 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 80068f0: 687b ldr r3, [r7, #4] 80068f2: 681b ldr r3, [r3, #0] 80068f4: 689b ldr r3, [r3, #8] 80068f6: f423 7240 bic.w r2, r3, #768 @ 0x300 80068fa: 687b ldr r3, [r7, #4] 80068fc: 681b ldr r3, [r3, #0] 80068fe: f442 7280 orr.w r2, r2, #256 @ 0x100 8006902: 609a str r2, [r3, #8] } 8006904: e016 b.n 8006934 else if (freq <= 25000000UL) 8006906: 68fb ldr r3, [r7, #12] 8006908: 4a13 ldr r2, [pc, #76] @ (8006958 ) 800690a: 4293 cmp r3, r2 800690c: d80a bhi.n 8006924 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 800690e: 687b ldr r3, [r7, #4] 8006910: 681b ldr r3, [r3, #0] 8006912: 689b ldr r3, [r3, #8] 8006914: f423 7240 bic.w r2, r3, #768 @ 0x300 8006918: 687b ldr r3, [r7, #4] 800691a: 681b ldr r3, [r3, #0] 800691c: f442 7200 orr.w r2, r2, #512 @ 0x200 8006920: 609a str r2, [r3, #8] } 8006922: e007 b.n 8006934 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 8006924: 687b ldr r3, [r7, #4] 8006926: 681b ldr r3, [r3, #0] 8006928: 689a ldr r2, [r3, #8] 800692a: 687b ldr r3, [r7, #4] 800692c: 681b ldr r3, [r3, #0] 800692e: f442 7240 orr.w r2, r2, #768 @ 0x300 8006932: 609a str r2, [r3, #8] } 8006934: bf00 nop 8006936: 3710 adds r7, #16 8006938: 46bd mov sp, r7 800693a: bd80 pop {r7, pc} 800693c: 40022000 .word 0x40022000 8006940: 40022100 .word 0x40022100 8006944: 40022300 .word 0x40022300 8006948: 58026300 .word 0x58026300 800694c: 01312d00 .word 0x01312d00 8006950: 005f5e10 .word 0x005f5e10 8006954: 00bebc20 .word 0x00bebc20 8006958: 017d7840 .word 0x017d7840 0800695c : { 800695c: b480 push {r7} 800695e: b083 sub sp, #12 8006960: af00 add r7, sp, #0 8006962: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8006964: 687b ldr r3, [r7, #4] 8006966: 689b ldr r3, [r3, #8] 8006968: f003 0301 and.w r3, r3, #1 800696c: 2b01 cmp r3, #1 800696e: d101 bne.n 8006974 8006970: 2301 movs r3, #1 8006972: e000 b.n 8006976 8006974: 2300 movs r3, #0 } 8006976: 4618 mov r0, r3 8006978: 370c adds r7, #12 800697a: 46bd mov sp, r7 800697c: f85d 7b04 ldr.w r7, [sp], #4 8006980: 4770 bx lr ... 08006984 : { 8006984: b480 push {r7} 8006986: b085 sub sp, #20 8006988: af00 add r7, sp, #0 800698a: 60f8 str r0, [r7, #12] 800698c: 60b9 str r1, [r7, #8] 800698e: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CR, 8006990: 68fb ldr r3, [r7, #12] 8006992: 689a ldr r2, [r3, #8] 8006994: 4b09 ldr r3, [pc, #36] @ (80069bc ) 8006996: 4013 ands r3, r2 8006998: 68ba ldr r2, [r7, #8] 800699a: f402 3180 and.w r1, r2, #65536 @ 0x10000 800699e: 687a ldr r2, [r7, #4] 80069a0: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80069a4: 430a orrs r2, r1 80069a6: 4313 orrs r3, r2 80069a8: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 80069ac: 68fb ldr r3, [r7, #12] 80069ae: 609a str r2, [r3, #8] } 80069b0: bf00 nop 80069b2: 3714 adds r7, #20 80069b4: 46bd mov sp, r7 80069b6: f85d 7b04 ldr.w r7, [sp], #4 80069ba: 4770 bx lr 80069bc: 3ffeffc0 .word 0x3ffeffc0 080069c0 : { 80069c0: b480 push {r7} 80069c2: b083 sub sp, #12 80069c4: af00 add r7, sp, #0 80069c6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 80069c8: 687b ldr r3, [r7, #4] 80069ca: 689b ldr r3, [r3, #8] 80069cc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80069d0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80069d4: d101 bne.n 80069da 80069d6: 2301 movs r3, #1 80069d8: e000 b.n 80069dc 80069da: 2300 movs r3, #0 } 80069dc: 4618 mov r0, r3 80069de: 370c adds r7, #12 80069e0: 46bd mov sp, r7 80069e2: f85d 7b04 ldr.w r7, [sp], #4 80069e6: 4770 bx lr 080069e8 : { 80069e8: b480 push {r7} 80069ea: b083 sub sp, #12 80069ec: af00 add r7, sp, #0 80069ee: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80069f0: 687b ldr r3, [r7, #4] 80069f2: 689b ldr r3, [r3, #8] 80069f4: f003 0304 and.w r3, r3, #4 80069f8: 2b04 cmp r3, #4 80069fa: d101 bne.n 8006a00 80069fc: 2301 movs r3, #1 80069fe: e000 b.n 8006a02 8006a00: 2300 movs r3, #0 } 8006a02: 4618 mov r0, r3 8006a04: 370c adds r7, #12 8006a06: 46bd mov sp, r7 8006a08: f85d 7b04 ldr.w r7, [sp], #4 8006a0c: 4770 bx lr ... 08006a10 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 8006a10: b580 push {r7, lr} 8006a12: b086 sub sp, #24 8006a14: af00 add r7, sp, #0 8006a16: 60f8 str r0, [r7, #12] 8006a18: 60b9 str r1, [r7, #8] 8006a1a: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 8006a1c: 2300 movs r3, #0 8006a1e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 8006a20: 68fb ldr r3, [r7, #12] 8006a22: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006a26: 2b01 cmp r3, #1 8006a28: d101 bne.n 8006a2e 8006a2a: 2302 movs r3, #2 8006a2c: e04c b.n 8006ac8 8006a2e: 68fb ldr r3, [r7, #12] 8006a30: 2201 movs r2, #1 8006a32: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8006a36: 68f8 ldr r0, [r7, #12] 8006a38: f7ff fd90 bl 800655c 8006a3c: 4603 mov r3, r0 8006a3e: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8006a40: 7dfb ldrb r3, [r7, #23] 8006a42: 2b00 cmp r3, #0 8006a44: d135 bne.n 8006ab2 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8006a46: 68fb ldr r3, [r7, #12] 8006a48: 6d5a ldr r2, [r3, #84] @ 0x54 8006a4a: 4b21 ldr r3, [pc, #132] @ (8006ad0 ) 8006a4c: 4013 ands r3, r2 8006a4e: f043 0202 orr.w r2, r3, #2 8006a52: 68fb ldr r3, [r7, #12] 8006a54: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 8006a56: 68fb ldr r3, [r7, #12] 8006a58: 681b ldr r3, [r3, #0] 8006a5a: 687a ldr r2, [r7, #4] 8006a5c: 68b9 ldr r1, [r7, #8] 8006a5e: 4618 mov r0, r3 8006a60: f7ff ff90 bl 8006984 /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8006a64: e014 b.n 8006a90 { wait_loop_index++; 8006a66: 693b ldr r3, [r7, #16] 8006a68: 3301 adds r3, #1 8006a6a: 613b str r3, [r7, #16] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 8006a6c: 693b ldr r3, [r7, #16] 8006a6e: 4a19 ldr r2, [pc, #100] @ (8006ad4 ) 8006a70: 4293 cmp r3, r2 8006a72: d30d bcc.n 8006a90 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 8006a74: 68fb ldr r3, [r7, #12] 8006a76: 6d5b ldr r3, [r3, #84] @ 0x54 8006a78: f023 0312 bic.w r3, r3, #18 8006a7c: f043 0210 orr.w r2, r3, #16 8006a80: 68fb ldr r3, [r7, #12] 8006a82: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 8006a84: 68fb ldr r3, [r7, #12] 8006a86: 2200 movs r2, #0 8006a88: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8006a8c: 2301 movs r3, #1 8006a8e: e01b b.n 8006ac8 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 8006a90: 68fb ldr r3, [r7, #12] 8006a92: 681b ldr r3, [r3, #0] 8006a94: 4618 mov r0, r3 8006a96: f7ff ff93 bl 80069c0 8006a9a: 4603 mov r3, r0 8006a9c: 2b00 cmp r3, #0 8006a9e: d1e2 bne.n 8006a66 } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8006aa0: 68fb ldr r3, [r7, #12] 8006aa2: 6d5b ldr r3, [r3, #84] @ 0x54 8006aa4: f023 0303 bic.w r3, r3, #3 8006aa8: f043 0201 orr.w r2, r3, #1 8006aac: 68fb ldr r3, [r7, #12] 8006aae: 655a str r2, [r3, #84] @ 0x54 8006ab0: e005 b.n 8006abe HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006ab2: 68fb ldr r3, [r7, #12] 8006ab4: 6d5b ldr r3, [r3, #84] @ 0x54 8006ab6: f043 0210 orr.w r2, r3, #16 8006aba: 68fb ldr r3, [r7, #12] 8006abc: 655a str r2, [r3, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006abe: 68fb ldr r3, [r7, #12] 8006ac0: 2200 movs r2, #0 8006ac2: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006ac6: 7dfb ldrb r3, [r7, #23] } 8006ac8: 4618 mov r0, r3 8006aca: 3718 adds r7, #24 8006acc: 46bd mov sp, r7 8006ace: bd80 pop {r7, pc} 8006ad0: ffffeefd .word 0xffffeefd 8006ad4: 25c3f800 .word 0x25c3f800 08006ad8 : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 8006ad8: b590 push {r4, r7, lr} 8006ada: b09f sub sp, #124 @ 0x7c 8006adc: af00 add r7, sp, #0 8006ade: 6078 str r0, [r7, #4] 8006ae0: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8006ae2: 2300 movs r3, #0 8006ae4: f887 3077 strb.w r3, [r7, #119] @ 0x77 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8006ae8: 687b ldr r3, [r7, #4] 8006aea: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006aee: 2b01 cmp r3, #1 8006af0: d101 bne.n 8006af6 8006af2: 2302 movs r3, #2 8006af4: e0be b.n 8006c74 8006af6: 687b ldr r3, [r7, #4] 8006af8: 2201 movs r2, #1 8006afa: f883 2050 strb.w r2, [r3, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 8006afe: 2300 movs r3, #0 8006b00: 65fb str r3, [r7, #92] @ 0x5c tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 8006b02: 2300 movs r3, #0 8006b04: 663b str r3, [r7, #96] @ 0x60 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8006b06: 687b ldr r3, [r7, #4] 8006b08: 681b ldr r3, [r3, #0] 8006b0a: 4a5c ldr r2, [pc, #368] @ (8006c7c ) 8006b0c: 4293 cmp r3, r2 8006b0e: d102 bne.n 8006b16 8006b10: 4b5b ldr r3, [pc, #364] @ (8006c80 ) 8006b12: 60bb str r3, [r7, #8] 8006b14: e001 b.n 8006b1a 8006b16: 2300 movs r3, #0 8006b18: 60bb str r3, [r7, #8] if (tmphadcSlave.Instance == NULL) 8006b1a: 68bb ldr r3, [r7, #8] 8006b1c: 2b00 cmp r3, #0 8006b1e: d10b bne.n 8006b38 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006b20: 687b ldr r3, [r7, #4] 8006b22: 6d5b ldr r3, [r3, #84] @ 0x54 8006b24: f043 0220 orr.w r2, r3, #32 8006b28: 687b ldr r3, [r7, #4] 8006b2a: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 8006b2c: 687b ldr r3, [r7, #4] 8006b2e: 2200 movs r2, #0 8006b30: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8006b34: 2301 movs r3, #1 8006b36: e09d b.n 8006c74 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); 8006b38: 68bb ldr r3, [r7, #8] 8006b3a: 4618 mov r0, r3 8006b3c: f7ff ff54 bl 80069e8 8006b40: 6738 str r0, [r7, #112] @ 0x70 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8006b42: 687b ldr r3, [r7, #4] 8006b44: 681b ldr r3, [r3, #0] 8006b46: 4618 mov r0, r3 8006b48: f7ff ff4e bl 80069e8 8006b4c: 4603 mov r3, r0 8006b4e: 2b00 cmp r3, #0 8006b50: d17f bne.n 8006c52 && (tmphadcSlave_conversion_on_going == 0UL)) 8006b52: 6f3b ldr r3, [r7, #112] @ 0x70 8006b54: 2b00 cmp r3, #0 8006b56: d17c bne.n 8006c52 { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 8006b58: 687b ldr r3, [r7, #4] 8006b5a: 681b ldr r3, [r3, #0] 8006b5c: 4a47 ldr r2, [pc, #284] @ (8006c7c ) 8006b5e: 4293 cmp r3, r2 8006b60: d004 beq.n 8006b6c 8006b62: 687b ldr r3, [r7, #4] 8006b64: 681b ldr r3, [r3, #0] 8006b66: 4a46 ldr r2, [pc, #280] @ (8006c80 ) 8006b68: 4293 cmp r3, r2 8006b6a: d101 bne.n 8006b70 8006b6c: 4b45 ldr r3, [pc, #276] @ (8006c84 ) 8006b6e: e000 b.n 8006b72 8006b70: 4b45 ldr r3, [pc, #276] @ (8006c88 ) 8006b72: 66fb str r3, [r7, #108] @ 0x6c /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 8006b74: 683b ldr r3, [r7, #0] 8006b76: 681b ldr r3, [r3, #0] 8006b78: 2b00 cmp r3, #0 8006b7a: d039 beq.n 8006bf0 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 8006b7c: 6efb ldr r3, [r7, #108] @ 0x6c 8006b7e: 689b ldr r3, [r3, #8] 8006b80: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8006b84: 683b ldr r3, [r7, #0] 8006b86: 685b ldr r3, [r3, #4] 8006b88: 431a orrs r2, r3 8006b8a: 6efb ldr r3, [r7, #108] @ 0x6c 8006b8c: 609a str r2, [r3, #8] /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006b8e: 687b ldr r3, [r7, #4] 8006b90: 681b ldr r3, [r3, #0] 8006b92: 4a3a ldr r2, [pc, #232] @ (8006c7c ) 8006b94: 4293 cmp r3, r2 8006b96: d004 beq.n 8006ba2 8006b98: 687b ldr r3, [r7, #4] 8006b9a: 681b ldr r3, [r3, #0] 8006b9c: 4a38 ldr r2, [pc, #224] @ (8006c80 ) 8006b9e: 4293 cmp r3, r2 8006ba0: d10e bne.n 8006bc0 8006ba2: 4836 ldr r0, [pc, #216] @ (8006c7c ) 8006ba4: f7ff feda bl 800695c 8006ba8: 4604 mov r4, r0 8006baa: 4835 ldr r0, [pc, #212] @ (8006c80 ) 8006bac: f7ff fed6 bl 800695c 8006bb0: 4603 mov r3, r0 8006bb2: 4323 orrs r3, r4 8006bb4: 2b00 cmp r3, #0 8006bb6: bf0c ite eq 8006bb8: 2301 moveq r3, #1 8006bba: 2300 movne r3, #0 8006bbc: b2db uxtb r3, r3 8006bbe: e008 b.n 8006bd2 8006bc0: 4832 ldr r0, [pc, #200] @ (8006c8c ) 8006bc2: f7ff fecb bl 800695c 8006bc6: 4603 mov r3, r0 8006bc8: 2b00 cmp r3, #0 8006bca: bf0c ite eq 8006bcc: 2301 moveq r3, #1 8006bce: 2300 movne r3, #0 8006bd0: b2db uxtb r3, r3 8006bd2: 2b00 cmp r3, #0 8006bd4: d047 beq.n 8006c66 { MODIFY_REG(tmpADC_Common->CCR, 8006bd6: 6efb ldr r3, [r7, #108] @ 0x6c 8006bd8: 689a ldr r2, [r3, #8] 8006bda: 4b2d ldr r3, [pc, #180] @ (8006c90 ) 8006bdc: 4013 ands r3, r2 8006bde: 683a ldr r2, [r7, #0] 8006be0: 6811 ldr r1, [r2, #0] 8006be2: 683a ldr r2, [r7, #0] 8006be4: 6892 ldr r2, [r2, #8] 8006be6: 430a orrs r2, r1 8006be8: 431a orrs r2, r3 8006bea: 6efb ldr r3, [r7, #108] @ 0x6c 8006bec: 609a str r2, [r3, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8006bee: e03a b.n 8006c66 ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 8006bf0: 6efb ldr r3, [r7, #108] @ 0x6c 8006bf2: 689b ldr r3, [r3, #8] 8006bf4: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8006bf8: 6efb ldr r3, [r7, #108] @ 0x6c 8006bfa: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006bfc: 687b ldr r3, [r7, #4] 8006bfe: 681b ldr r3, [r3, #0] 8006c00: 4a1e ldr r2, [pc, #120] @ (8006c7c ) 8006c02: 4293 cmp r3, r2 8006c04: d004 beq.n 8006c10 8006c06: 687b ldr r3, [r7, #4] 8006c08: 681b ldr r3, [r3, #0] 8006c0a: 4a1d ldr r2, [pc, #116] @ (8006c80 ) 8006c0c: 4293 cmp r3, r2 8006c0e: d10e bne.n 8006c2e 8006c10: 481a ldr r0, [pc, #104] @ (8006c7c ) 8006c12: f7ff fea3 bl 800695c 8006c16: 4604 mov r4, r0 8006c18: 4819 ldr r0, [pc, #100] @ (8006c80 ) 8006c1a: f7ff fe9f bl 800695c 8006c1e: 4603 mov r3, r0 8006c20: 4323 orrs r3, r4 8006c22: 2b00 cmp r3, #0 8006c24: bf0c ite eq 8006c26: 2301 moveq r3, #1 8006c28: 2300 movne r3, #0 8006c2a: b2db uxtb r3, r3 8006c2c: e008 b.n 8006c40 8006c2e: 4817 ldr r0, [pc, #92] @ (8006c8c ) 8006c30: f7ff fe94 bl 800695c 8006c34: 4603 mov r3, r0 8006c36: 2b00 cmp r3, #0 8006c38: bf0c ite eq 8006c3a: 2301 moveq r3, #1 8006c3c: 2300 movne r3, #0 8006c3e: b2db uxtb r3, r3 8006c40: 2b00 cmp r3, #0 8006c42: d010 beq.n 8006c66 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 8006c44: 6efb ldr r3, [r7, #108] @ 0x6c 8006c46: 689a ldr r2, [r3, #8] 8006c48: 4b11 ldr r3, [pc, #68] @ (8006c90 ) 8006c4a: 4013 ands r3, r2 8006c4c: 6efa ldr r2, [r7, #108] @ 0x6c 8006c4e: 6093 str r3, [r2, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8006c50: e009 b.n 8006c66 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006c52: 687b ldr r3, [r7, #4] 8006c54: 6d5b ldr r3, [r3, #84] @ 0x54 8006c56: f043 0220 orr.w r2, r3, #32 8006c5a: 687b ldr r3, [r7, #4] 8006c5c: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006c5e: 2301 movs r3, #1 8006c60: f887 3077 strb.w r3, [r7, #119] @ 0x77 8006c64: e000 b.n 8006c68 if (multimode->Mode != ADC_MODE_INDEPENDENT) 8006c66: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006c68: 687b ldr r3, [r7, #4] 8006c6a: 2200 movs r2, #0 8006c6c: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006c70: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 8006c74: 4618 mov r0, r3 8006c76: 377c adds r7, #124 @ 0x7c 8006c78: 46bd mov sp, r7 8006c7a: bd90 pop {r4, r7, pc} 8006c7c: 40022000 .word 0x40022000 8006c80: 40022100 .word 0x40022100 8006c84: 40022300 .word 0x40022300 8006c88: 58026300 .word 0x58026300 8006c8c: 58026000 .word 0x58026000 8006c90: fffff0e0 .word 0xfffff0e0 08006c94 : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 8006c94: b580 push {r7, lr} 8006c96: b088 sub sp, #32 8006c98: af00 add r7, sp, #0 8006c9a: 6078 str r0, [r7, #4] uint32_t tmp_csr ; uint32_t exti_line ; uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 8006c9c: 2300 movs r3, #0 8006c9e: 60fb str r3, [r7, #12] HAL_StatusTypeDef status = HAL_OK; 8006ca0: 2300 movs r3, #0 8006ca2: 77fb strb r3, [r7, #31] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8006ca4: 687b ldr r3, [r7, #4] 8006ca6: 2b00 cmp r3, #0 8006ca8: d102 bne.n 8006cb0 { status = HAL_ERROR; 8006caa: 2301 movs r3, #1 8006cac: 77fb strb r3, [r7, #31] 8006cae: e10e b.n 8006ece } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8006cb0: 687b ldr r3, [r7, #4] 8006cb2: 681b ldr r3, [r3, #0] 8006cb4: 681b ldr r3, [r3, #0] 8006cb6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8006cba: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8006cbe: d102 bne.n 8006cc6 { status = HAL_ERROR; 8006cc0: 2301 movs r3, #1 8006cc2: 77fb strb r3, [r7, #31] 8006cc4: e103 b.n 8006ece assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) 8006cc6: 687b ldr r3, [r7, #4] 8006cc8: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8006ccc: b2db uxtb r3, r3 8006cce: 2b00 cmp r3, #0 8006cd0: d109 bne.n 8006ce6 { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; 8006cd2: 687b ldr r3, [r7, #4] 8006cd4: 2200 movs r2, #0 8006cd6: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); 8006cda: 687b ldr r3, [r7, #4] 8006cdc: 2200 movs r2, #0 8006cde: 629a str r2, [r3, #40] @ 0x28 /* Init the low level hardware */ hcomp->MspInitCallback(hcomp); #else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); 8006ce0: 6878 ldr r0, [r7, #4] 8006ce2: f7fc fd67 bl 80037b4 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 8006ce6: 687b ldr r3, [r7, #4] 8006ce8: 681b ldr r3, [r3, #0] 8006cea: 681b ldr r3, [r3, #0] 8006cec: f003 0304 and.w r3, r3, #4 8006cf0: 61bb str r3, [r7, #24] /* Set BLANKING bits according to hcomp->Init.BlankingSrce value */ /* Set HYST bits according to hcomp->Init.Hysteresis value */ /* Set POLARITY bit according to hcomp->Init.OutputPol value */ /* Set POWERMODE bits according to hcomp->Init.Mode value */ tmp_csr = (hcomp->Init.InvertingInput | \ 8006cf2: 687b ldr r3, [r7, #4] 8006cf4: 691a ldr r2, [r3, #16] hcomp->Init.NonInvertingInput | \ 8006cf6: 687b ldr r3, [r7, #4] 8006cf8: 68db ldr r3, [r3, #12] tmp_csr = (hcomp->Init.InvertingInput | \ 8006cfa: 431a orrs r2, r3 hcomp->Init.BlankingSrce | \ 8006cfc: 687b ldr r3, [r7, #4] 8006cfe: 69db ldr r3, [r3, #28] hcomp->Init.NonInvertingInput | \ 8006d00: 431a orrs r2, r3 hcomp->Init.Hysteresis | \ 8006d02: 687b ldr r3, [r7, #4] 8006d04: 695b ldr r3, [r3, #20] hcomp->Init.BlankingSrce | \ 8006d06: 431a orrs r2, r3 hcomp->Init.OutputPol | \ 8006d08: 687b ldr r3, [r7, #4] 8006d0a: 699b ldr r3, [r3, #24] hcomp->Init.Hysteresis | \ 8006d0c: 431a orrs r2, r3 hcomp->Init.Mode ); 8006d0e: 687b ldr r3, [r7, #4] 8006d10: 689b ldr r3, [r3, #8] tmp_csr = (hcomp->Init.InvertingInput | \ 8006d12: 4313 orrs r3, r2 8006d14: 617b str r3, [r7, #20] COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST | COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN, tmp_csr ); #else MODIFY_REG(hcomp->Instance->CFGR, 8006d16: 687b ldr r3, [r7, #4] 8006d18: 681b ldr r3, [r3, #0] 8006d1a: 681a ldr r2, [r3, #0] 8006d1c: 4b6e ldr r3, [pc, #440] @ (8006ed8 ) 8006d1e: 4013 ands r3, r2 8006d20: 687a ldr r2, [r7, #4] 8006d22: 6812 ldr r2, [r2, #0] 8006d24: 6979 ldr r1, [r7, #20] 8006d26: 430b orrs r3, r1 8006d28: 6013 str r3, [r2, #0] #endif /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 8006d2a: 687b ldr r3, [r7, #4] 8006d2c: 685b ldr r3, [r3, #4] 8006d2e: 2b10 cmp r3, #16 8006d30: d108 bne.n 8006d44 { SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8006d32: 687b ldr r3, [r7, #4] 8006d34: 681b ldr r3, [r3, #0] 8006d36: 681a ldr r2, [r3, #0] 8006d38: 687b ldr r3, [r7, #4] 8006d3a: 681b ldr r3, [r3, #0] 8006d3c: f042 0210 orr.w r2, r2, #16 8006d40: 601a str r2, [r3, #0] 8006d42: e007 b.n 8006d54 } else { CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8006d44: 687b ldr r3, [r7, #4] 8006d46: 681b ldr r3, [r3, #0] 8006d48: 681a ldr r2, [r3, #0] 8006d4a: 687b ldr r3, [r7, #4] 8006d4c: 681b ldr r3, [r3, #0] 8006d4e: f022 0210 bic.w r2, r2, #16 8006d52: 601a str r2, [r3, #0] } /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) && 8006d54: 687b ldr r3, [r7, #4] 8006d56: 681b ldr r3, [r3, #0] 8006d58: 681b ldr r3, [r3, #0] 8006d5a: f003 0304 and.w r3, r3, #4 8006d5e: 2b00 cmp r3, #0 8006d60: d016 beq.n 8006d90 8006d62: 69bb ldr r3, [r7, #24] 8006d64: 2b00 cmp r3, #0 8006d66: d013 beq.n 8006d90 { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles.*/ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006d68: 4b5c ldr r3, [pc, #368] @ (8006edc ) 8006d6a: 681b ldr r3, [r3, #0] 8006d6c: 099b lsrs r3, r3, #6 8006d6e: 4a5c ldr r2, [pc, #368] @ (8006ee0 ) 8006d70: fba2 2303 umull r2, r3, r2, r3 8006d74: 099b lsrs r3, r3, #6 8006d76: 1c5a adds r2, r3, #1 8006d78: 4613 mov r3, r2 8006d7a: 009b lsls r3, r3, #2 8006d7c: 4413 add r3, r2 8006d7e: 009b lsls r3, r3, #2 8006d80: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 8006d82: e002 b.n 8006d8a { wait_loop_index --; 8006d84: 68fb ldr r3, [r7, #12] 8006d86: 3b01 subs r3, #1 8006d88: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 8006d8a: 68fb ldr r3, [r7, #12] 8006d8c: 2b00 cmp r3, #0 8006d8e: d1f9 bne.n 8006d84 } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 8006d90: 687b ldr r3, [r7, #4] 8006d92: 681b ldr r3, [r3, #0] 8006d94: 4a53 ldr r2, [pc, #332] @ (8006ee4 ) 8006d96: 4293 cmp r3, r2 8006d98: d102 bne.n 8006da0 8006d9a: f44f 1380 mov.w r3, #1048576 @ 0x100000 8006d9e: e001 b.n 8006da4 8006da0: f44f 1300 mov.w r3, #2097152 @ 0x200000 8006da4: 613b str r3, [r7, #16] /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 8006da6: 687b ldr r3, [r7, #4] 8006da8: 6a1b ldr r3, [r3, #32] 8006daa: f003 0303 and.w r3, r3, #3 8006dae: 2b00 cmp r3, #0 8006db0: d06d beq.n 8006e8e { /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 8006db2: 687b ldr r3, [r7, #4] 8006db4: 6a1b ldr r3, [r3, #32] 8006db6: f003 0310 and.w r3, r3, #16 8006dba: 2b00 cmp r3, #0 8006dbc: d008 beq.n 8006dd0 { SET_BIT(EXTI->RTSR1, exti_line); 8006dbe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006dc2: 681a ldr r2, [r3, #0] 8006dc4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006dc8: 693b ldr r3, [r7, #16] 8006dca: 4313 orrs r3, r2 8006dcc: 600b str r3, [r1, #0] 8006dce: e008 b.n 8006de2 } else { CLEAR_BIT(EXTI->RTSR1, exti_line); 8006dd0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006dd4: 681a ldr r2, [r3, #0] 8006dd6: 693b ldr r3, [r7, #16] 8006dd8: 43db mvns r3, r3 8006dda: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006dde: 4013 ands r3, r2 8006de0: 600b str r3, [r1, #0] } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 8006de2: 687b ldr r3, [r7, #4] 8006de4: 6a1b ldr r3, [r3, #32] 8006de6: f003 0320 and.w r3, r3, #32 8006dea: 2b00 cmp r3, #0 8006dec: d008 beq.n 8006e00 { SET_BIT(EXTI->FTSR1, exti_line); 8006dee: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006df2: 685a ldr r2, [r3, #4] 8006df4: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006df8: 693b ldr r3, [r7, #16] 8006dfa: 4313 orrs r3, r2 8006dfc: 604b str r3, [r1, #4] 8006dfe: e008 b.n 8006e12 } else { CLEAR_BIT(EXTI->FTSR1, exti_line); 8006e00: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006e04: 685a ldr r2, [r3, #4] 8006e06: 693b ldr r3, [r7, #16] 8006e08: 43db mvns r3, r3 8006e0a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006e0e: 4013 ands r3, r2 8006e10: 604b str r3, [r1, #4] } #if !defined (CORE_CM4) /* Clear COMP EXTI pending bit (if any) */ WRITE_REG(EXTI->PR1, exti_line); 8006e12: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8006e16: 693b ldr r3, [r7, #16] 8006e18: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 8006e1c: 687b ldr r3, [r7, #4] 8006e1e: 6a1b ldr r3, [r3, #32] 8006e20: f003 0302 and.w r3, r3, #2 8006e24: 2b00 cmp r3, #0 8006e26: d00a beq.n 8006e3e { SET_BIT(EXTI->EMR1, exti_line); 8006e28: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006e2c: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8006e30: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006e34: 693b ldr r3, [r7, #16] 8006e36: 4313 orrs r3, r2 8006e38: f8c1 3084 str.w r3, [r1, #132] @ 0x84 8006e3c: e00a b.n 8006e54 } else { CLEAR_BIT(EXTI->EMR1, exti_line); 8006e3e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006e42: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8006e46: 693b ldr r3, [r7, #16] 8006e48: 43db mvns r3, r3 8006e4a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006e4e: 4013 ands r3, r2 8006e50: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 8006e54: 687b ldr r3, [r7, #4] 8006e56: 6a1b ldr r3, [r3, #32] 8006e58: f003 0301 and.w r3, r3, #1 8006e5c: 2b00 cmp r3, #0 8006e5e: d00a beq.n 8006e76 { SET_BIT(EXTI->IMR1, exti_line); 8006e60: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006e64: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8006e68: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006e6c: 693b ldr r3, [r7, #16] 8006e6e: 4313 orrs r3, r2 8006e70: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8006e74: e021 b.n 8006eba } else { CLEAR_BIT(EXTI->IMR1, exti_line); 8006e76: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006e7a: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8006e7e: 693b ldr r3, [r7, #16] 8006e80: 43db mvns r3, r3 8006e82: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006e86: 4013 ands r3, r2 8006e88: f8c1 3080 str.w r3, [r1, #128] @ 0x80 8006e8c: e015 b.n 8006eba } } else { /* Disable EXTI event mode */ CLEAR_BIT(EXTI->EMR1, exti_line); 8006e8e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006e92: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8006e96: 693b ldr r3, [r7, #16] 8006e98: 43db mvns r3, r3 8006e9a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006e9e: 4013 ands r3, r2 8006ea0: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* Disable EXTI interrupt mode */ CLEAR_BIT(EXTI->IMR1, exti_line); 8006ea4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8006ea8: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 8006eac: 693b ldr r3, [r7, #16] 8006eae: 43db mvns r3, r3 8006eb0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8006eb4: 4013 ands r3, r2 8006eb6: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } #endif /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ if (hcomp->State == HAL_COMP_STATE_RESET) 8006eba: 687b ldr r3, [r7, #4] 8006ebc: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8006ec0: b2db uxtb r3, r3 8006ec2: 2b00 cmp r3, #0 8006ec4: d103 bne.n 8006ece { hcomp->State = HAL_COMP_STATE_READY; 8006ec6: 687b ldr r3, [r7, #4] 8006ec8: 2201 movs r2, #1 8006eca: f883 2025 strb.w r2, [r3, #37] @ 0x25 } } return status; 8006ece: 7ffb ldrb r3, [r7, #31] } 8006ed0: 4618 mov r0, r3 8006ed2: 3720 adds r7, #32 8006ed4: 46bd mov sp, r7 8006ed6: bd80 pop {r7, pc} 8006ed8: f0e8cce1 .word 0xf0e8cce1 8006edc: 24000034 .word 0x24000034 8006ee0: 053e2d63 .word 0x053e2d63 8006ee4: 5800380c .word 0x5800380c 08006ee8 : * @brief Start the comparator. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { 8006ee8: b480 push {r7} 8006eea: b085 sub sp, #20 8006eec: af00 add r7, sp, #0 8006eee: 6078 str r0, [r7, #4] __IO uint32_t wait_loop_index = 0UL; 8006ef0: 2300 movs r3, #0 8006ef2: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 8006ef4: 2300 movs r3, #0 8006ef6: 73fb strb r3, [r7, #15] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8006ef8: 687b ldr r3, [r7, #4] 8006efa: 2b00 cmp r3, #0 8006efc: d102 bne.n 8006f04 { status = HAL_ERROR; 8006efe: 2301 movs r3, #1 8006f00: 73fb strb r3, [r7, #15] 8006f02: e030 b.n 8006f66 } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8006f04: 687b ldr r3, [r7, #4] 8006f06: 681b ldr r3, [r3, #0] 8006f08: 681b ldr r3, [r3, #0] 8006f0a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8006f0e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8006f12: d102 bne.n 8006f1a { status = HAL_ERROR; 8006f14: 2301 movs r3, #1 8006f16: 73fb strb r3, [r7, #15] 8006f18: e025 b.n 8006f66 else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if(hcomp->State == HAL_COMP_STATE_READY) 8006f1a: 687b ldr r3, [r7, #4] 8006f1c: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8006f20: b2db uxtb r3, r3 8006f22: 2b01 cmp r3, #1 8006f24: d11d bne.n 8006f62 { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 8006f26: 687b ldr r3, [r7, #4] 8006f28: 681b ldr r3, [r3, #0] 8006f2a: 681a ldr r2, [r3, #0] 8006f2c: 687b ldr r3, [r7, #4] 8006f2e: 681b ldr r3, [r3, #0] 8006f30: f042 0201 orr.w r2, r2, #1 8006f34: 601a str r2, [r3, #0] /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; 8006f36: 687b ldr r3, [r7, #4] 8006f38: 2202 movs r2, #2 8006f3a: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Delay for COMP startup time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006f3e: 4b0d ldr r3, [pc, #52] @ (8006f74 ) 8006f40: 681b ldr r3, [r3, #0] 8006f42: 099b lsrs r3, r3, #6 8006f44: 4a0c ldr r2, [pc, #48] @ (8006f78 ) 8006f46: fba2 2303 umull r2, r3, r2, r3 8006f4a: 099b lsrs r3, r3, #6 8006f4c: 3301 adds r3, #1 8006f4e: 00db lsls r3, r3, #3 8006f50: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 8006f52: e002 b.n 8006f5a { wait_loop_index--; 8006f54: 68bb ldr r3, [r7, #8] 8006f56: 3b01 subs r3, #1 8006f58: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 8006f5a: 68bb ldr r3, [r7, #8] 8006f5c: 2b00 cmp r3, #0 8006f5e: d1f9 bne.n 8006f54 8006f60: e001 b.n 8006f66 } } else { status = HAL_ERROR; 8006f62: 2301 movs r3, #1 8006f64: 73fb strb r3, [r7, #15] } } return status; 8006f66: 7bfb ldrb r3, [r7, #15] } 8006f68: 4618 mov r0, r3 8006f6a: 3714 adds r7, #20 8006f6c: 46bd mov sp, r7 8006f6e: f85d 7b04 ldr.w r7, [sp], #4 8006f72: 4770 bx lr 8006f74: 24000034 .word 0x24000034 8006f78: 053e2d63 .word 0x053e2d63 08006f7c : * @arg @ref COMP_OUTPUT_LEVEL_LOW * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { 8006f7c: b480 push {r7} 8006f7e: b083 sub sp, #12 8006f80: af00 add r7, sp, #0 8006f82: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if (hcomp->Instance == COMP1) 8006f84: 687b ldr r3, [r7, #4] 8006f86: 681b ldr r3, [r3, #0] 8006f88: 4a09 ldr r2, [pc, #36] @ (8006fb0 ) 8006f8a: 4293 cmp r3, r2 8006f8c: d104 bne.n 8006f98 { return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); 8006f8e: 4b09 ldr r3, [pc, #36] @ (8006fb4 ) 8006f90: 681b ldr r3, [r3, #0] 8006f92: f003 0301 and.w r3, r3, #1 8006f96: e004 b.n 8006fa2 } else { return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL); 8006f98: 4b06 ldr r3, [pc, #24] @ (8006fb4 ) 8006f9a: 681b ldr r3, [r3, #0] 8006f9c: 085b lsrs r3, r3, #1 8006f9e: f003 0301 and.w r3, r3, #1 } } 8006fa2: 4618 mov r0, r3 8006fa4: 370c adds r7, #12 8006fa6: 46bd mov sp, r7 8006fa8: f85d 7b04 ldr.w r7, [sp], #4 8006fac: 4770 bx lr 8006fae: bf00 nop 8006fb0: 5800380c .word 0x5800380c 8006fb4: 58003800 .word 0x58003800 08006fb8 <__NVIC_SetPriorityGrouping>: { 8006fb8: b480 push {r7} 8006fba: b085 sub sp, #20 8006fbc: af00 add r7, sp, #0 8006fbe: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8006fc0: 687b ldr r3, [r7, #4] 8006fc2: f003 0307 and.w r3, r3, #7 8006fc6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8006fc8: 4b0b ldr r3, [pc, #44] @ (8006ff8 <__NVIC_SetPriorityGrouping+0x40>) 8006fca: 68db ldr r3, [r3, #12] 8006fcc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8006fce: 68ba ldr r2, [r7, #8] 8006fd0: f64f 03ff movw r3, #63743 @ 0xf8ff 8006fd4: 4013 ands r3, r2 8006fd6: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8006fd8: 68fb ldr r3, [r7, #12] 8006fda: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8006fdc: 68bb ldr r3, [r7, #8] 8006fde: 431a orrs r2, r3 reg_value = (reg_value | 8006fe0: 4b06 ldr r3, [pc, #24] @ (8006ffc <__NVIC_SetPriorityGrouping+0x44>) 8006fe2: 4313 orrs r3, r2 8006fe4: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8006fe6: 4a04 ldr r2, [pc, #16] @ (8006ff8 <__NVIC_SetPriorityGrouping+0x40>) 8006fe8: 68bb ldr r3, [r7, #8] 8006fea: 60d3 str r3, [r2, #12] } 8006fec: bf00 nop 8006fee: 3714 adds r7, #20 8006ff0: 46bd mov sp, r7 8006ff2: f85d 7b04 ldr.w r7, [sp], #4 8006ff6: 4770 bx lr 8006ff8: e000ed00 .word 0xe000ed00 8006ffc: 05fa0000 .word 0x05fa0000 08007000 <__NVIC_GetPriorityGrouping>: { 8007000: b480 push {r7} 8007002: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8007004: 4b04 ldr r3, [pc, #16] @ (8007018 <__NVIC_GetPriorityGrouping+0x18>) 8007006: 68db ldr r3, [r3, #12] 8007008: 0a1b lsrs r3, r3, #8 800700a: f003 0307 and.w r3, r3, #7 } 800700e: 4618 mov r0, r3 8007010: 46bd mov sp, r7 8007012: f85d 7b04 ldr.w r7, [sp], #4 8007016: 4770 bx lr 8007018: e000ed00 .word 0xe000ed00 0800701c <__NVIC_EnableIRQ>: { 800701c: b480 push {r7} 800701e: b083 sub sp, #12 8007020: af00 add r7, sp, #0 8007022: 4603 mov r3, r0 8007024: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007026: f9b7 3006 ldrsh.w r3, [r7, #6] 800702a: 2b00 cmp r3, #0 800702c: db0b blt.n 8007046 <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800702e: 88fb ldrh r3, [r7, #6] 8007030: f003 021f and.w r2, r3, #31 8007034: 4907 ldr r1, [pc, #28] @ (8007054 <__NVIC_EnableIRQ+0x38>) 8007036: f9b7 3006 ldrsh.w r3, [r7, #6] 800703a: 095b lsrs r3, r3, #5 800703c: 2001 movs r0, #1 800703e: fa00 f202 lsl.w r2, r0, r2 8007042: f841 2023 str.w r2, [r1, r3, lsl #2] } 8007046: bf00 nop 8007048: 370c adds r7, #12 800704a: 46bd mov sp, r7 800704c: f85d 7b04 ldr.w r7, [sp], #4 8007050: 4770 bx lr 8007052: bf00 nop 8007054: e000e100 .word 0xe000e100 08007058 <__NVIC_SetPriority>: { 8007058: b480 push {r7} 800705a: b083 sub sp, #12 800705c: af00 add r7, sp, #0 800705e: 4603 mov r3, r0 8007060: 6039 str r1, [r7, #0] 8007062: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007064: f9b7 3006 ldrsh.w r3, [r7, #6] 8007068: 2b00 cmp r3, #0 800706a: db0a blt.n 8007082 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800706c: 683b ldr r3, [r7, #0] 800706e: b2da uxtb r2, r3 8007070: 490c ldr r1, [pc, #48] @ (80070a4 <__NVIC_SetPriority+0x4c>) 8007072: f9b7 3006 ldrsh.w r3, [r7, #6] 8007076: 0112 lsls r2, r2, #4 8007078: b2d2 uxtb r2, r2 800707a: 440b add r3, r1 800707c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8007080: e00a b.n 8007098 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007082: 683b ldr r3, [r7, #0] 8007084: b2da uxtb r2, r3 8007086: 4908 ldr r1, [pc, #32] @ (80070a8 <__NVIC_SetPriority+0x50>) 8007088: 88fb ldrh r3, [r7, #6] 800708a: f003 030f and.w r3, r3, #15 800708e: 3b04 subs r3, #4 8007090: 0112 lsls r2, r2, #4 8007092: b2d2 uxtb r2, r2 8007094: 440b add r3, r1 8007096: 761a strb r2, [r3, #24] } 8007098: bf00 nop 800709a: 370c adds r7, #12 800709c: 46bd mov sp, r7 800709e: f85d 7b04 ldr.w r7, [sp], #4 80070a2: 4770 bx lr 80070a4: e000e100 .word 0xe000e100 80070a8: e000ed00 .word 0xe000ed00 080070ac : { 80070ac: b480 push {r7} 80070ae: b089 sub sp, #36 @ 0x24 80070b0: af00 add r7, sp, #0 80070b2: 60f8 str r0, [r7, #12] 80070b4: 60b9 str r1, [r7, #8] 80070b6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80070b8: 68fb ldr r3, [r7, #12] 80070ba: f003 0307 and.w r3, r3, #7 80070be: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80070c0: 69fb ldr r3, [r7, #28] 80070c2: f1c3 0307 rsb r3, r3, #7 80070c6: 2b04 cmp r3, #4 80070c8: bf28 it cs 80070ca: 2304 movcs r3, #4 80070cc: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80070ce: 69fb ldr r3, [r7, #28] 80070d0: 3304 adds r3, #4 80070d2: 2b06 cmp r3, #6 80070d4: d902 bls.n 80070dc 80070d6: 69fb ldr r3, [r7, #28] 80070d8: 3b03 subs r3, #3 80070da: e000 b.n 80070de 80070dc: 2300 movs r3, #0 80070de: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80070e0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80070e4: 69bb ldr r3, [r7, #24] 80070e6: fa02 f303 lsl.w r3, r2, r3 80070ea: 43da mvns r2, r3 80070ec: 68bb ldr r3, [r7, #8] 80070ee: 401a ands r2, r3 80070f0: 697b ldr r3, [r7, #20] 80070f2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80070f4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80070f8: 697b ldr r3, [r7, #20] 80070fa: fa01 f303 lsl.w r3, r1, r3 80070fe: 43d9 mvns r1, r3 8007100: 687b ldr r3, [r7, #4] 8007102: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007104: 4313 orrs r3, r2 } 8007106: 4618 mov r0, r3 8007108: 3724 adds r7, #36 @ 0x24 800710a: 46bd mov sp, r7 800710c: f85d 7b04 ldr.w r7, [sp], #4 8007110: 4770 bx lr 08007112 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8007112: b580 push {r7, lr} 8007114: b082 sub sp, #8 8007116: af00 add r7, sp, #0 8007118: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800711a: 6878 ldr r0, [r7, #4] 800711c: f7ff ff4c bl 8006fb8 <__NVIC_SetPriorityGrouping> } 8007120: bf00 nop 8007122: 3708 adds r7, #8 8007124: 46bd mov sp, r7 8007126: bd80 pop {r7, pc} 08007128 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8007128: b580 push {r7, lr} 800712a: b086 sub sp, #24 800712c: af00 add r7, sp, #0 800712e: 4603 mov r3, r0 8007130: 60b9 str r1, [r7, #8] 8007132: 607a str r2, [r7, #4] 8007134: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8007136: f7ff ff63 bl 8007000 <__NVIC_GetPriorityGrouping> 800713a: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800713c: 687a ldr r2, [r7, #4] 800713e: 68b9 ldr r1, [r7, #8] 8007140: 6978 ldr r0, [r7, #20] 8007142: f7ff ffb3 bl 80070ac 8007146: 4602 mov r2, r0 8007148: f9b7 300e ldrsh.w r3, [r7, #14] 800714c: 4611 mov r1, r2 800714e: 4618 mov r0, r3 8007150: f7ff ff82 bl 8007058 <__NVIC_SetPriority> } 8007154: bf00 nop 8007156: 3718 adds r7, #24 8007158: 46bd mov sp, r7 800715a: bd80 pop {r7, pc} 0800715c : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 800715c: b580 push {r7, lr} 800715e: b082 sub sp, #8 8007160: af00 add r7, sp, #0 8007162: 4603 mov r3, r0 8007164: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8007166: f9b7 3006 ldrsh.w r3, [r7, #6] 800716a: 4618 mov r0, r3 800716c: f7ff ff56 bl 800701c <__NVIC_EnableIRQ> } 8007170: bf00 nop 8007172: 3708 adds r7, #8 8007174: 46bd mov sp, r7 8007176: bd80 pop {r7, pc} 08007178 : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 8007178: b480 push {r7} 800717a: af00 add r7, sp, #0 __ASM volatile ("dmb 0xF":::"memory"); 800717c: f3bf 8f5f dmb sy } 8007180: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8007182: 4b07 ldr r3, [pc, #28] @ (80071a0 ) 8007184: 6a5b ldr r3, [r3, #36] @ 0x24 8007186: 4a06 ldr r2, [pc, #24] @ (80071a0 ) 8007188: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800718c: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 800718e: 4b05 ldr r3, [pc, #20] @ (80071a4 ) 8007190: 2200 movs r2, #0 8007192: 605a str r2, [r3, #4] } 8007194: bf00 nop 8007196: 46bd mov sp, r7 8007198: f85d 7b04 ldr.w r7, [sp], #4 800719c: 4770 bx lr 800719e: bf00 nop 80071a0: e000ed00 .word 0xe000ed00 80071a4: e000ed90 .word 0xe000ed90 080071a8 : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 80071a8: b480 push {r7} 80071aa: b083 sub sp, #12 80071ac: af00 add r7, sp, #0 80071ae: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 80071b0: 4a0b ldr r2, [pc, #44] @ (80071e0 ) 80071b2: 687b ldr r3, [r7, #4] 80071b4: f043 0301 orr.w r3, r3, #1 80071b8: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 80071ba: 4b0a ldr r3, [pc, #40] @ (80071e4 ) 80071bc: 6a5b ldr r3, [r3, #36] @ 0x24 80071be: 4a09 ldr r2, [pc, #36] @ (80071e4 ) 80071c0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80071c4: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 80071c6: f3bf 8f4f dsb sy } 80071ca: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80071cc: f3bf 8f6f isb sy } 80071d0: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 80071d2: bf00 nop 80071d4: 370c adds r7, #12 80071d6: 46bd mov sp, r7 80071d8: f85d 7b04 ldr.w r7, [sp], #4 80071dc: 4770 bx lr 80071de: bf00 nop 80071e0: e000ed90 .word 0xe000ed90 80071e4: e000ed00 .word 0xe000ed00 080071e8 : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 80071e8: b480 push {r7} 80071ea: b083 sub sp, #12 80071ec: af00 add r7, sp, #0 80071ee: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 80071f0: 687b ldr r3, [r7, #4] 80071f2: 785a ldrb r2, [r3, #1] 80071f4: 4b1b ldr r3, [pc, #108] @ (8007264 ) 80071f6: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 80071f8: 4b1a ldr r3, [pc, #104] @ (8007264 ) 80071fa: 691b ldr r3, [r3, #16] 80071fc: 4a19 ldr r2, [pc, #100] @ (8007264 ) 80071fe: f023 0301 bic.w r3, r3, #1 8007202: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 8007204: 4a17 ldr r2, [pc, #92] @ (8007264 ) 8007206: 687b ldr r3, [r7, #4] 8007208: 685b ldr r3, [r3, #4] 800720a: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 800720c: 687b ldr r3, [r7, #4] 800720e: 7b1b ldrb r3, [r3, #12] 8007210: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007212: 687b ldr r3, [r7, #4] 8007214: 7adb ldrb r3, [r3, #11] 8007216: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007218: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 800721a: 687b ldr r3, [r7, #4] 800721c: 7a9b ldrb r3, [r3, #10] 800721e: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007220: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007222: 687b ldr r3, [r7, #4] 8007224: 7b5b ldrb r3, [r3, #13] 8007226: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007228: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 800722a: 687b ldr r3, [r7, #4] 800722c: 7b9b ldrb r3, [r3, #14] 800722e: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007230: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007232: 687b ldr r3, [r7, #4] 8007234: 7bdb ldrb r3, [r3, #15] 8007236: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007238: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 800723a: 687b ldr r3, [r7, #4] 800723c: 7a5b ldrb r3, [r3, #9] 800723e: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007240: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007242: 687b ldr r3, [r7, #4] 8007244: 7a1b ldrb r3, [r3, #8] 8007246: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007248: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 800724a: 687a ldr r2, [r7, #4] 800724c: 7812 ldrb r2, [r2, #0] 800724e: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007250: 4a04 ldr r2, [pc, #16] @ (8007264 ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007252: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007254: 6113 str r3, [r2, #16] } 8007256: bf00 nop 8007258: 370c adds r7, #12 800725a: 46bd mov sp, r7 800725c: f85d 7b04 ldr.w r7, [sp], #4 8007260: 4770 bx lr 8007262: bf00 nop 8007264: e000ed90 .word 0xe000ed90 08007268 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 8007268: b580 push {r7, lr} 800726a: b082 sub sp, #8 800726c: af00 add r7, sp, #0 800726e: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8007270: 687b ldr r3, [r7, #4] 8007272: 2b00 cmp r3, #0 8007274: d101 bne.n 800727a { return HAL_ERROR; 8007276: 2301 movs r3, #1 8007278: e054 b.n 8007324 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800727a: 687b ldr r3, [r7, #4] 800727c: 7f5b ldrb r3, [r3, #29] 800727e: b2db uxtb r3, r3 8007280: 2b00 cmp r3, #0 8007282: d105 bne.n 8007290 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8007284: 687b ldr r3, [r7, #4] 8007286: 2200 movs r2, #0 8007288: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800728a: 6878 ldr r0, [r7, #4] 800728c: f7fc fad8 bl 8003840 } hcrc->State = HAL_CRC_STATE_BUSY; 8007290: 687b ldr r3, [r7, #4] 8007292: 2202 movs r2, #2 8007294: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 8007296: 687b ldr r3, [r7, #4] 8007298: 791b ldrb r3, [r3, #4] 800729a: 2b00 cmp r3, #0 800729c: d10c bne.n 80072b8 { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 800729e: 687b ldr r3, [r7, #4] 80072a0: 681b ldr r3, [r3, #0] 80072a2: 4a22 ldr r2, [pc, #136] @ (800732c ) 80072a4: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 80072a6: 687b ldr r3, [r7, #4] 80072a8: 681b ldr r3, [r3, #0] 80072aa: 689a ldr r2, [r3, #8] 80072ac: 687b ldr r3, [r7, #4] 80072ae: 681b ldr r3, [r3, #0] 80072b0: f022 0218 bic.w r2, r2, #24 80072b4: 609a str r2, [r3, #8] 80072b6: e00c b.n 80072d2 } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 80072b8: 687b ldr r3, [r7, #4] 80072ba: 6899 ldr r1, [r3, #8] 80072bc: 687b ldr r3, [r7, #4] 80072be: 68db ldr r3, [r3, #12] 80072c0: 461a mov r2, r3 80072c2: 6878 ldr r0, [r7, #4] 80072c4: f000 f948 bl 8007558 80072c8: 4603 mov r3, r0 80072ca: 2b00 cmp r3, #0 80072cc: d001 beq.n 80072d2 { return HAL_ERROR; 80072ce: 2301 movs r3, #1 80072d0: e028 b.n 8007324 } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 80072d2: 687b ldr r3, [r7, #4] 80072d4: 795b ldrb r3, [r3, #5] 80072d6: 2b00 cmp r3, #0 80072d8: d105 bne.n 80072e6 { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 80072da: 687b ldr r3, [r7, #4] 80072dc: 681b ldr r3, [r3, #0] 80072de: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80072e2: 611a str r2, [r3, #16] 80072e4: e004 b.n 80072f0 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 80072e6: 687b ldr r3, [r7, #4] 80072e8: 681b ldr r3, [r3, #0] 80072ea: 687a ldr r2, [r7, #4] 80072ec: 6912 ldr r2, [r2, #16] 80072ee: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 80072f0: 687b ldr r3, [r7, #4] 80072f2: 681b ldr r3, [r3, #0] 80072f4: 689b ldr r3, [r3, #8] 80072f6: f023 0160 bic.w r1, r3, #96 @ 0x60 80072fa: 687b ldr r3, [r7, #4] 80072fc: 695a ldr r2, [r3, #20] 80072fe: 687b ldr r3, [r7, #4] 8007300: 681b ldr r3, [r3, #0] 8007302: 430a orrs r2, r1 8007304: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 8007306: 687b ldr r3, [r7, #4] 8007308: 681b ldr r3, [r3, #0] 800730a: 689b ldr r3, [r3, #8] 800730c: f023 0180 bic.w r1, r3, #128 @ 0x80 8007310: 687b ldr r3, [r7, #4] 8007312: 699a ldr r2, [r3, #24] 8007314: 687b ldr r3, [r7, #4] 8007316: 681b ldr r3, [r3, #0] 8007318: 430a orrs r2, r1 800731a: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 800731c: 687b ldr r3, [r7, #4] 800731e: 2201 movs r2, #1 8007320: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 8007322: 2300 movs r3, #0 } 8007324: 4618 mov r0, r3 8007326: 3708 adds r7, #8 8007328: 46bd mov sp, r7 800732a: bd80 pop {r7, pc} 800732c: 04c11db7 .word 0x04c11db7 08007330 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 8007330: b580 push {r7, lr} 8007332: b086 sub sp, #24 8007334: af00 add r7, sp, #0 8007336: 60f8 str r0, [r7, #12] 8007338: 60b9 str r1, [r7, #8] 800733a: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 800733c: 2300 movs r3, #0 800733e: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 8007340: 68fb ldr r3, [r7, #12] 8007342: 2202 movs r2, #2 8007344: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 8007346: 68fb ldr r3, [r7, #12] 8007348: 681b ldr r3, [r3, #0] 800734a: 689a ldr r2, [r3, #8] 800734c: 68fb ldr r3, [r7, #12] 800734e: 681b ldr r3, [r3, #0] 8007350: f042 0201 orr.w r2, r2, #1 8007354: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 8007356: 68fb ldr r3, [r7, #12] 8007358: 6a1b ldr r3, [r3, #32] 800735a: 2b03 cmp r3, #3 800735c: d006 beq.n 800736c 800735e: 2b03 cmp r3, #3 8007360: d829 bhi.n 80073b6 8007362: 2b01 cmp r3, #1 8007364: d019 beq.n 800739a 8007366: 2b02 cmp r3, #2 8007368: d01e beq.n 80073a8 /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 800736a: e024 b.n 80073b6 for (index = 0U; index < BufferLength; index++) 800736c: 2300 movs r3, #0 800736e: 617b str r3, [r7, #20] 8007370: e00a b.n 8007388 hcrc->Instance->DR = pBuffer[index]; 8007372: 697b ldr r3, [r7, #20] 8007374: 009b lsls r3, r3, #2 8007376: 68ba ldr r2, [r7, #8] 8007378: 441a add r2, r3 800737a: 68fb ldr r3, [r7, #12] 800737c: 681b ldr r3, [r3, #0] 800737e: 6812 ldr r2, [r2, #0] 8007380: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 8007382: 697b ldr r3, [r7, #20] 8007384: 3301 adds r3, #1 8007386: 617b str r3, [r7, #20] 8007388: 697a ldr r2, [r7, #20] 800738a: 687b ldr r3, [r7, #4] 800738c: 429a cmp r2, r3 800738e: d3f0 bcc.n 8007372 temp = hcrc->Instance->DR; 8007390: 68fb ldr r3, [r7, #12] 8007392: 681b ldr r3, [r3, #0] 8007394: 681b ldr r3, [r3, #0] 8007396: 613b str r3, [r7, #16] break; 8007398: e00e b.n 80073b8 temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 800739a: 687a ldr r2, [r7, #4] 800739c: 68b9 ldr r1, [r7, #8] 800739e: 68f8 ldr r0, [r7, #12] 80073a0: f000 f812 bl 80073c8 80073a4: 6138 str r0, [r7, #16] break; 80073a6: e007 b.n 80073b8 temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 80073a8: 687a ldr r2, [r7, #4] 80073aa: 68b9 ldr r1, [r7, #8] 80073ac: 68f8 ldr r0, [r7, #12] 80073ae: f000 f899 bl 80074e4 80073b2: 6138 str r0, [r7, #16] break; 80073b4: e000 b.n 80073b8 break; 80073b6: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 80073b8: 68fb ldr r3, [r7, #12] 80073ba: 2201 movs r2, #1 80073bc: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 80073be: 693b ldr r3, [r7, #16] } 80073c0: 4618 mov r0, r3 80073c2: 3718 adds r7, #24 80073c4: 46bd mov sp, r7 80073c6: bd80 pop {r7, pc} 080073c8 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 80073c8: b480 push {r7} 80073ca: b089 sub sp, #36 @ 0x24 80073cc: af00 add r7, sp, #0 80073ce: 60f8 str r0, [r7, #12] 80073d0: 60b9 str r1, [r7, #8] 80073d2: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 80073d4: 2300 movs r3, #0 80073d6: 61fb str r3, [r7, #28] 80073d8: e023 b.n 8007422 { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 80073da: 69fb ldr r3, [r7, #28] 80073dc: 009b lsls r3, r3, #2 80073de: 68ba ldr r2, [r7, #8] 80073e0: 4413 add r3, r2 80073e2: 781b ldrb r3, [r3, #0] 80073e4: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 80073e6: 69fb ldr r3, [r7, #28] 80073e8: 009b lsls r3, r3, #2 80073ea: 3301 adds r3, #1 80073ec: 68b9 ldr r1, [r7, #8] 80073ee: 440b add r3, r1 80073f0: 781b ldrb r3, [r3, #0] 80073f2: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 80073f4: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 80073f6: 69fb ldr r3, [r7, #28] 80073f8: 009b lsls r3, r3, #2 80073fa: 3302 adds r3, #2 80073fc: 68b9 ldr r1, [r7, #8] 80073fe: 440b add r3, r1 8007400: 781b ldrb r3, [r3, #0] 8007402: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007404: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 8007406: 69fb ldr r3, [r7, #28] 8007408: 009b lsls r3, r3, #2 800740a: 3303 adds r3, #3 800740c: 68b9 ldr r1, [r7, #8] 800740e: 440b add r3, r1 8007410: 781b ldrb r3, [r3, #0] 8007412: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007414: 68fb ldr r3, [r7, #12] 8007416: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007418: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 800741a: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 800741c: 69fb ldr r3, [r7, #28] 800741e: 3301 adds r3, #1 8007420: 61fb str r3, [r7, #28] 8007422: 687b ldr r3, [r7, #4] 8007424: 089b lsrs r3, r3, #2 8007426: 69fa ldr r2, [r7, #28] 8007428: 429a cmp r2, r3 800742a: d3d6 bcc.n 80073da } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 800742c: 687b ldr r3, [r7, #4] 800742e: f003 0303 and.w r3, r3, #3 8007432: 2b00 cmp r3, #0 8007434: d04d beq.n 80074d2 { if ((BufferLength % 4U) == 1U) 8007436: 687b ldr r3, [r7, #4] 8007438: f003 0303 and.w r3, r3, #3 800743c: 2b01 cmp r3, #1 800743e: d107 bne.n 8007450 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 8007440: 69fb ldr r3, [r7, #28] 8007442: 009b lsls r3, r3, #2 8007444: 68ba ldr r2, [r7, #8] 8007446: 4413 add r3, r2 8007448: 68fa ldr r2, [r7, #12] 800744a: 6812 ldr r2, [r2, #0] 800744c: 781b ldrb r3, [r3, #0] 800744e: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 8007450: 687b ldr r3, [r7, #4] 8007452: f003 0303 and.w r3, r3, #3 8007456: 2b02 cmp r3, #2 8007458: d116 bne.n 8007488 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 800745a: 69fb ldr r3, [r7, #28] 800745c: 009b lsls r3, r3, #2 800745e: 68ba ldr r2, [r7, #8] 8007460: 4413 add r3, r2 8007462: 781b ldrb r3, [r3, #0] 8007464: 021b lsls r3, r3, #8 8007466: b21a sxth r2, r3 8007468: 69fb ldr r3, [r7, #28] 800746a: 009b lsls r3, r3, #2 800746c: 3301 adds r3, #1 800746e: 68b9 ldr r1, [r7, #8] 8007470: 440b add r3, r1 8007472: 781b ldrb r3, [r3, #0] 8007474: b21b sxth r3, r3 8007476: 4313 orrs r3, r2 8007478: b21b sxth r3, r3 800747a: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 800747c: 68fb ldr r3, [r7, #12] 800747e: 681b ldr r3, [r3, #0] 8007480: 617b str r3, [r7, #20] *pReg = data; 8007482: 697b ldr r3, [r7, #20] 8007484: 8b7a ldrh r2, [r7, #26] 8007486: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 8007488: 687b ldr r3, [r7, #4] 800748a: f003 0303 and.w r3, r3, #3 800748e: 2b03 cmp r3, #3 8007490: d11f bne.n 80074d2 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007492: 69fb ldr r3, [r7, #28] 8007494: 009b lsls r3, r3, #2 8007496: 68ba ldr r2, [r7, #8] 8007498: 4413 add r3, r2 800749a: 781b ldrb r3, [r3, #0] 800749c: 021b lsls r3, r3, #8 800749e: b21a sxth r2, r3 80074a0: 69fb ldr r3, [r7, #28] 80074a2: 009b lsls r3, r3, #2 80074a4: 3301 adds r3, #1 80074a6: 68b9 ldr r1, [r7, #8] 80074a8: 440b add r3, r1 80074aa: 781b ldrb r3, [r3, #0] 80074ac: b21b sxth r3, r3 80074ae: 4313 orrs r3, r2 80074b0: b21b sxth r3, r3 80074b2: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 80074b4: 68fb ldr r3, [r7, #12] 80074b6: 681b ldr r3, [r3, #0] 80074b8: 617b str r3, [r7, #20] *pReg = data; 80074ba: 697b ldr r3, [r7, #20] 80074bc: 8b7a ldrh r2, [r7, #26] 80074be: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 80074c0: 69fb ldr r3, [r7, #28] 80074c2: 009b lsls r3, r3, #2 80074c4: 3302 adds r3, #2 80074c6: 68ba ldr r2, [r7, #8] 80074c8: 4413 add r3, r2 80074ca: 68fa ldr r2, [r7, #12] 80074cc: 6812 ldr r2, [r2, #0] 80074ce: 781b ldrb r3, [r3, #0] 80074d0: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 80074d2: 68fb ldr r3, [r7, #12] 80074d4: 681b ldr r3, [r3, #0] 80074d6: 681b ldr r3, [r3, #0] } 80074d8: 4618 mov r0, r3 80074da: 3724 adds r7, #36 @ 0x24 80074dc: 46bd mov sp, r7 80074de: f85d 7b04 ldr.w r7, [sp], #4 80074e2: 4770 bx lr 080074e4 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 80074e4: b480 push {r7} 80074e6: b087 sub sp, #28 80074e8: af00 add r7, sp, #0 80074ea: 60f8 str r0, [r7, #12] 80074ec: 60b9 str r1, [r7, #8] 80074ee: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 80074f0: 2300 movs r3, #0 80074f2: 617b str r3, [r7, #20] 80074f4: e013 b.n 800751e { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 80074f6: 697b ldr r3, [r7, #20] 80074f8: 009b lsls r3, r3, #2 80074fa: 68ba ldr r2, [r7, #8] 80074fc: 4413 add r3, r2 80074fe: 881b ldrh r3, [r3, #0] 8007500: 041a lsls r2, r3, #16 8007502: 697b ldr r3, [r7, #20] 8007504: 009b lsls r3, r3, #2 8007506: 3302 adds r3, #2 8007508: 68b9 ldr r1, [r7, #8] 800750a: 440b add r3, r1 800750c: 881b ldrh r3, [r3, #0] 800750e: 4619 mov r1, r3 8007510: 68fb ldr r3, [r7, #12] 8007512: 681b ldr r3, [r3, #0] 8007514: 430a orrs r2, r1 8007516: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 8007518: 697b ldr r3, [r7, #20] 800751a: 3301 adds r3, #1 800751c: 617b str r3, [r7, #20] 800751e: 687b ldr r3, [r7, #4] 8007520: 085b lsrs r3, r3, #1 8007522: 697a ldr r2, [r7, #20] 8007524: 429a cmp r2, r3 8007526: d3e6 bcc.n 80074f6 } if ((BufferLength % 2U) != 0U) 8007528: 687b ldr r3, [r7, #4] 800752a: f003 0301 and.w r3, r3, #1 800752e: 2b00 cmp r3, #0 8007530: d009 beq.n 8007546 { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007532: 68fb ldr r3, [r7, #12] 8007534: 681b ldr r3, [r3, #0] 8007536: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 8007538: 697b ldr r3, [r7, #20] 800753a: 009b lsls r3, r3, #2 800753c: 68ba ldr r2, [r7, #8] 800753e: 4413 add r3, r2 8007540: 881a ldrh r2, [r3, #0] 8007542: 693b ldr r3, [r7, #16] 8007544: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007546: 68fb ldr r3, [r7, #12] 8007548: 681b ldr r3, [r3, #0] 800754a: 681b ldr r3, [r3, #0] } 800754c: 4618 mov r0, r3 800754e: 371c adds r7, #28 8007550: 46bd mov sp, r7 8007552: f85d 7b04 ldr.w r7, [sp], #4 8007556: 4770 bx lr 08007558 : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 8007558: b480 push {r7} 800755a: b087 sub sp, #28 800755c: af00 add r7, sp, #0 800755e: 60f8 str r0, [r7, #12] 8007560: 60b9 str r1, [r7, #8] 8007562: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8007564: 2300 movs r3, #0 8007566: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 8007568: 231f movs r3, #31 800756a: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 800756c: 68bb ldr r3, [r7, #8] 800756e: f003 0301 and.w r3, r3, #1 8007572: 2b00 cmp r3, #0 8007574: d102 bne.n 800757c { status = HAL_ERROR; 8007576: 2301 movs r3, #1 8007578: 75fb strb r3, [r7, #23] 800757a: e063 b.n 8007644 * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 800757c: bf00 nop 800757e: 693b ldr r3, [r7, #16] 8007580: 1e5a subs r2, r3, #1 8007582: 613a str r2, [r7, #16] 8007584: 2b00 cmp r3, #0 8007586: d009 beq.n 800759c 8007588: 693b ldr r3, [r7, #16] 800758a: f003 031f and.w r3, r3, #31 800758e: 68ba ldr r2, [r7, #8] 8007590: fa22 f303 lsr.w r3, r2, r3 8007594: f003 0301 and.w r3, r3, #1 8007598: 2b00 cmp r3, #0 800759a: d0f0 beq.n 800757e { } switch (PolyLength) 800759c: 687b ldr r3, [r7, #4] 800759e: 2b18 cmp r3, #24 80075a0: d846 bhi.n 8007630 80075a2: a201 add r2, pc, #4 @ (adr r2, 80075a8 ) 80075a4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80075a8: 08007637 .word 0x08007637 80075ac: 08007631 .word 0x08007631 80075b0: 08007631 .word 0x08007631 80075b4: 08007631 .word 0x08007631 80075b8: 08007631 .word 0x08007631 80075bc: 08007631 .word 0x08007631 80075c0: 08007631 .word 0x08007631 80075c4: 08007631 .word 0x08007631 80075c8: 08007625 .word 0x08007625 80075cc: 08007631 .word 0x08007631 80075d0: 08007631 .word 0x08007631 80075d4: 08007631 .word 0x08007631 80075d8: 08007631 .word 0x08007631 80075dc: 08007631 .word 0x08007631 80075e0: 08007631 .word 0x08007631 80075e4: 08007631 .word 0x08007631 80075e8: 08007619 .word 0x08007619 80075ec: 08007631 .word 0x08007631 80075f0: 08007631 .word 0x08007631 80075f4: 08007631 .word 0x08007631 80075f8: 08007631 .word 0x08007631 80075fc: 08007631 .word 0x08007631 8007600: 08007631 .word 0x08007631 8007604: 08007631 .word 0x08007631 8007608: 0800760d .word 0x0800760d { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 800760c: 693b ldr r3, [r7, #16] 800760e: 2b06 cmp r3, #6 8007610: d913 bls.n 800763a { status = HAL_ERROR; 8007612: 2301 movs r3, #1 8007614: 75fb strb r3, [r7, #23] } break; 8007616: e010 b.n 800763a case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 8007618: 693b ldr r3, [r7, #16] 800761a: 2b07 cmp r3, #7 800761c: d90f bls.n 800763e { status = HAL_ERROR; 800761e: 2301 movs r3, #1 8007620: 75fb strb r3, [r7, #23] } break; 8007622: e00c b.n 800763e case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 8007624: 693b ldr r3, [r7, #16] 8007626: 2b0f cmp r3, #15 8007628: d90b bls.n 8007642 { status = HAL_ERROR; 800762a: 2301 movs r3, #1 800762c: 75fb strb r3, [r7, #23] } break; 800762e: e008 b.n 8007642 case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 8007630: 2301 movs r3, #1 8007632: 75fb strb r3, [r7, #23] break; 8007634: e006 b.n 8007644 break; 8007636: bf00 nop 8007638: e004 b.n 8007644 break; 800763a: bf00 nop 800763c: e002 b.n 8007644 break; 800763e: bf00 nop 8007640: e000 b.n 8007644 break; 8007642: bf00 nop } } if (status == HAL_OK) 8007644: 7dfb ldrb r3, [r7, #23] 8007646: 2b00 cmp r3, #0 8007648: d10d bne.n 8007666 { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 800764a: 68fb ldr r3, [r7, #12] 800764c: 681b ldr r3, [r3, #0] 800764e: 68ba ldr r2, [r7, #8] 8007650: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 8007652: 68fb ldr r3, [r7, #12] 8007654: 681b ldr r3, [r3, #0] 8007656: 689b ldr r3, [r3, #8] 8007658: f023 0118 bic.w r1, r3, #24 800765c: 68fb ldr r3, [r7, #12] 800765e: 681b ldr r3, [r3, #0] 8007660: 687a ldr r2, [r7, #4] 8007662: 430a orrs r2, r1 8007664: 609a str r2, [r3, #8] } /* Return function status */ return status; 8007666: 7dfb ldrb r3, [r7, #23] } 8007668: 4618 mov r0, r3 800766a: 371c adds r7, #28 800766c: 46bd mov sp, r7 800766e: f85d 7b04 ldr.w r7, [sp], #4 8007672: 4770 bx lr 08007674 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 8007674: b580 push {r7, lr} 8007676: b082 sub sp, #8 8007678: af00 add r7, sp, #0 800767a: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 800767c: 687b ldr r3, [r7, #4] 800767e: 2b00 cmp r3, #0 8007680: d101 bne.n 8007686 { return HAL_ERROR; 8007682: 2301 movs r3, #1 8007684: e014 b.n 80076b0 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 8007686: 687b ldr r3, [r7, #4] 8007688: 791b ldrb r3, [r3, #4] 800768a: b2db uxtb r3, r3 800768c: 2b00 cmp r3, #0 800768e: d105 bne.n 800769c hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 8007690: 687b ldr r3, [r7, #4] 8007692: 2200 movs r2, #0 8007694: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 8007696: 6878 ldr r0, [r7, #4] 8007698: f7fc f8f4 bl 8003884 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 800769c: 687b ldr r3, [r7, #4] 800769e: 2202 movs r2, #2 80076a0: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 80076a2: 687b ldr r3, [r7, #4] 80076a4: 2200 movs r2, #0 80076a6: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 80076a8: 687b ldr r3, [r7, #4] 80076aa: 2201 movs r2, #1 80076ac: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 80076ae: 2300 movs r3, #0 } 80076b0: 4618 mov r0, r3 80076b2: 3708 adds r7, #8 80076b4: 46bd mov sp, r7 80076b6: bd80 pop {r7, pc} 080076b8 : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 80076b8: b480 push {r7} 80076ba: b083 sub sp, #12 80076bc: af00 add r7, sp, #0 80076be: 6078 str r0, [r7, #4] 80076c0: 6039 str r1, [r7, #0] /* Check the DAC peripheral handle */ if (hdac == NULL) 80076c2: 687b ldr r3, [r7, #4] 80076c4: 2b00 cmp r3, #0 80076c6: d101 bne.n 80076cc { return HAL_ERROR; 80076c8: 2301 movs r3, #1 80076ca: e046 b.n 800775a /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 80076cc: 687b ldr r3, [r7, #4] 80076ce: 795b ldrb r3, [r3, #5] 80076d0: 2b01 cmp r3, #1 80076d2: d101 bne.n 80076d8 80076d4: 2302 movs r3, #2 80076d6: e040 b.n 800775a 80076d8: 687b ldr r3, [r7, #4] 80076da: 2201 movs r2, #1 80076dc: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 80076de: 687b ldr r3, [r7, #4] 80076e0: 2202 movs r2, #2 80076e2: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 80076e4: 687b ldr r3, [r7, #4] 80076e6: 681b ldr r3, [r3, #0] 80076e8: 6819 ldr r1, [r3, #0] 80076ea: 683b ldr r3, [r7, #0] 80076ec: f003 0310 and.w r3, r3, #16 80076f0: 2201 movs r2, #1 80076f2: 409a lsls r2, r3 80076f4: 687b ldr r3, [r7, #4] 80076f6: 681b ldr r3, [r3, #0] 80076f8: 430a orrs r2, r1 80076fa: 601a str r2, [r3, #0] if (Channel == DAC_CHANNEL_1) 80076fc: 683b ldr r3, [r7, #0] 80076fe: 2b00 cmp r3, #0 8007700: d10f bne.n 8007722 { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 8007702: 687b ldr r3, [r7, #4] 8007704: 681b ldr r3, [r3, #0] 8007706: 681b ldr r3, [r3, #0] 8007708: f003 033e and.w r3, r3, #62 @ 0x3e 800770c: 2b02 cmp r3, #2 800770e: d11d bne.n 800774c { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 8007710: 687b ldr r3, [r7, #4] 8007712: 681b ldr r3, [r3, #0] 8007714: 685a ldr r2, [r3, #4] 8007716: 687b ldr r3, [r7, #4] 8007718: 681b ldr r3, [r3, #0] 800771a: f042 0201 orr.w r2, r2, #1 800771e: 605a str r2, [r3, #4] 8007720: e014 b.n 800774c } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 8007722: 687b ldr r3, [r7, #4] 8007724: 681b ldr r3, [r3, #0] 8007726: 681b ldr r3, [r3, #0] 8007728: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 800772c: 683b ldr r3, [r7, #0] 800772e: f003 0310 and.w r3, r3, #16 8007732: 2102 movs r1, #2 8007734: fa01 f303 lsl.w r3, r1, r3 8007738: 429a cmp r2, r3 800773a: d107 bne.n 800774c { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 800773c: 687b ldr r3, [r7, #4] 800773e: 681b ldr r3, [r3, #0] 8007740: 685a ldr r2, [r3, #4] 8007742: 687b ldr r3, [r7, #4] 8007744: 681b ldr r3, [r3, #0] 8007746: f042 0202 orr.w r2, r2, #2 800774a: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 800774c: 687b ldr r3, [r7, #4] 800774e: 2201 movs r2, #1 8007750: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8007752: 687b ldr r3, [r7, #4] 8007754: 2200 movs r2, #0 8007756: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8007758: 2300 movs r3, #0 } 800775a: 4618 mov r0, r3 800775c: 370c adds r7, #12 800775e: 46bd mov sp, r7 8007760: f85d 7b04 ldr.w r7, [sp], #4 8007764: 4770 bx lr 08007766 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { 8007766: b580 push {r7, lr} 8007768: b084 sub sp, #16 800776a: af00 add r7, sp, #0 800776c: 6078 str r0, [r7, #4] uint32_t itsource = hdac->Instance->CR; 800776e: 687b ldr r3, [r7, #4] 8007770: 681b ldr r3, [r3, #0] 8007772: 681b ldr r3, [r3, #0] 8007774: 60fb str r3, [r7, #12] uint32_t itflag = hdac->Instance->SR; 8007776: 687b ldr r3, [r7, #4] 8007778: 681b ldr r3, [r3, #0] 800777a: 6b5b ldr r3, [r3, #52] @ 0x34 800777c: 60bb str r3, [r7, #8] if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 800777e: 68fb ldr r3, [r7, #12] 8007780: f403 5300 and.w r3, r3, #8192 @ 0x2000 8007784: 2b00 cmp r3, #0 8007786: d01d beq.n 80077c4 { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 8007788: 68bb ldr r3, [r7, #8] 800778a: f403 5300 and.w r3, r3, #8192 @ 0x2000 800778e: 2b00 cmp r3, #0 8007790: d018 beq.n 80077c4 { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8007792: 687b ldr r3, [r7, #4] 8007794: 2204 movs r2, #4 8007796: 711a strb r2, [r3, #4] /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 8007798: 687b ldr r3, [r7, #4] 800779a: 691b ldr r3, [r3, #16] 800779c: f043 0201 orr.w r2, r3, #1 80077a0: 687b ldr r3, [r7, #4] 80077a2: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 80077a4: 687b ldr r3, [r7, #4] 80077a6: 681b ldr r3, [r3, #0] 80077a8: f44f 5200 mov.w r2, #8192 @ 0x2000 80077ac: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 80077ae: 687b ldr r3, [r7, #4] 80077b0: 681b ldr r3, [r3, #0] 80077b2: 681a ldr r2, [r3, #0] 80077b4: 687b ldr r3, [r7, #4] 80077b6: 681b ldr r3, [r3, #0] 80077b8: f422 5280 bic.w r2, r2, #4096 @ 0x1000 80077bc: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); 80077be: 6878 ldr r0, [r7, #4] 80077c0: f000 f851 bl 8007866 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 80077c4: 68fb ldr r3, [r7, #12] 80077c6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80077ca: 2b00 cmp r3, #0 80077cc: d01d beq.n 800780a { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 80077ce: 68bb ldr r3, [r7, #8] 80077d0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80077d4: 2b00 cmp r3, #0 80077d6: d018 beq.n 800780a { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 80077d8: 687b ldr r3, [r7, #4] 80077da: 2204 movs r2, #4 80077dc: 711a strb r2, [r3, #4] /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 80077de: 687b ldr r3, [r7, #4] 80077e0: 691b ldr r3, [r3, #16] 80077e2: f043 0202 orr.w r2, r3, #2 80077e6: 687b ldr r3, [r7, #4] 80077e8: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 80077ea: 687b ldr r3, [r7, #4] 80077ec: 681b ldr r3, [r3, #0] 80077ee: f04f 5200 mov.w r2, #536870912 @ 0x20000000 80077f2: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 80077f4: 687b ldr r3, [r7, #4] 80077f6: 681b ldr r3, [r3, #0] 80077f8: 681a ldr r2, [r3, #0] 80077fa: 687b ldr r3, [r7, #4] 80077fc: 681b ldr r3, [r3, #0] 80077fe: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 8007802: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 8007804: 6878 ldr r0, [r7, #4] 8007806: f000 f97b bl 8007b00 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } 800780a: bf00 nop 800780c: 3710 adds r7, #16 800780e: 46bd mov sp, r7 8007810: bd80 pop {r7, pc} 08007812 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 8007812: b480 push {r7} 8007814: b087 sub sp, #28 8007816: af00 add r7, sp, #0 8007818: 60f8 str r0, [r7, #12] 800781a: 60b9 str r1, [r7, #8] 800781c: 607a str r2, [r7, #4] 800781e: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 8007820: 2300 movs r3, #0 8007822: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 8007824: 68fb ldr r3, [r7, #12] 8007826: 2b00 cmp r3, #0 8007828: d101 bne.n 800782e { return HAL_ERROR; 800782a: 2301 movs r3, #1 800782c: e015 b.n 800785a /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 800782e: 68fb ldr r3, [r7, #12] 8007830: 681b ldr r3, [r3, #0] 8007832: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 8007834: 68bb ldr r3, [r7, #8] 8007836: 2b00 cmp r3, #0 8007838: d105 bne.n 8007846 { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 800783a: 697a ldr r2, [r7, #20] 800783c: 687b ldr r3, [r7, #4] 800783e: 4413 add r3, r2 8007840: 3308 adds r3, #8 8007842: 617b str r3, [r7, #20] 8007844: e004 b.n 8007850 } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 8007846: 697a ldr r2, [r7, #20] 8007848: 687b ldr r3, [r7, #4] 800784a: 4413 add r3, r2 800784c: 3314 adds r3, #20 800784e: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8007850: 697b ldr r3, [r7, #20] 8007852: 461a mov r2, r3 8007854: 683b ldr r3, [r7, #0] 8007856: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 8007858: 2300 movs r3, #0 } 800785a: 4618 mov r0, r3 800785c: 371c adds r7, #28 800785e: 46bd mov sp, r7 8007860: f85d 7b04 ldr.w r7, [sp], #4 8007864: 4770 bx lr 08007866 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { 8007866: b480 push {r7} 8007868: b083 sub sp, #12 800786a: af00 add r7, sp, #0 800786c: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } 800786e: bf00 nop 8007870: 370c adds r7, #12 8007872: 46bd mov sp, r7 8007874: f85d 7b04 ldr.w r7, [sp], #4 8007878: 4770 bx lr ... 0800787c : * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 800787c: b580 push {r7, lr} 800787e: b08a sub sp, #40 @ 0x28 8007880: af00 add r7, sp, #0 8007882: 60f8 str r0, [r7, #12] 8007884: 60b9 str r1, [r7, #8] 8007886: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8007888: 2300 movs r3, #0 800788a: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 800788e: 68fb ldr r3, [r7, #12] 8007890: 2b00 cmp r3, #0 8007892: d002 beq.n 800789a 8007894: 68bb ldr r3, [r7, #8] 8007896: 2b00 cmp r3, #0 8007898: d101 bne.n 800789e { return HAL_ERROR; 800789a: 2301 movs r3, #1 800789c: e12a b.n 8007af4 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 800789e: 68fb ldr r3, [r7, #12] 80078a0: 795b ldrb r3, [r3, #5] 80078a2: 2b01 cmp r3, #1 80078a4: d101 bne.n 80078aa 80078a6: 2302 movs r3, #2 80078a8: e124 b.n 8007af4 80078aa: 68fb ldr r3, [r7, #12] 80078ac: 2201 movs r2, #1 80078ae: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 80078b0: 68fb ldr r3, [r7, #12] 80078b2: 2202 movs r2, #2 80078b4: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 80078b6: 68bb ldr r3, [r7, #8] 80078b8: 681b ldr r3, [r3, #0] 80078ba: 2b04 cmp r3, #4 80078bc: d17a bne.n 80079b4 { /* Get timeout */ tickstart = HAL_GetTick(); 80078be: f7fd fd8d bl 80053dc 80078c2: 61f8 str r0, [r7, #28] if (Channel == DAC_CHANNEL_1) 80078c4: 687b ldr r3, [r7, #4] 80078c6: 2b00 cmp r3, #0 80078c8: d13d bne.n 8007946 { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80078ca: e018 b.n 80078fe { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 80078cc: f7fd fd86 bl 80053dc 80078d0: 4602 mov r2, r0 80078d2: 69fb ldr r3, [r7, #28] 80078d4: 1ad3 subs r3, r2, r3 80078d6: 2b01 cmp r3, #1 80078d8: d911 bls.n 80078fe { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80078da: 68fb ldr r3, [r7, #12] 80078dc: 681b ldr r3, [r3, #0] 80078de: 6b5a ldr r2, [r3, #52] @ 0x34 80078e0: 4b86 ldr r3, [pc, #536] @ (8007afc ) 80078e2: 4013 ands r3, r2 80078e4: 2b00 cmp r3, #0 80078e6: d00a beq.n 80078fe { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 80078e8: 68fb ldr r3, [r7, #12] 80078ea: 691b ldr r3, [r3, #16] 80078ec: f043 0208 orr.w r2, r3, #8 80078f0: 68fb ldr r3, [r7, #12] 80078f2: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 80078f4: 68fb ldr r3, [r7, #12] 80078f6: 2203 movs r2, #3 80078f8: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 80078fa: 2303 movs r3, #3 80078fc: e0fa b.n 8007af4 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 80078fe: 68fb ldr r3, [r7, #12] 8007900: 681b ldr r3, [r3, #0] 8007902: 6b5a ldr r2, [r3, #52] @ 0x34 8007904: 4b7d ldr r3, [pc, #500] @ (8007afc ) 8007906: 4013 ands r3, r2 8007908: 2b00 cmp r3, #0 800790a: d1df bne.n 80078cc } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 800790c: 68fb ldr r3, [r7, #12] 800790e: 681b ldr r3, [r3, #0] 8007910: 68ba ldr r2, [r7, #8] 8007912: 6992 ldr r2, [r2, #24] 8007914: 641a str r2, [r3, #64] @ 0x40 8007916: e020 b.n 800795a { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8007918: f7fd fd60 bl 80053dc 800791c: 4602 mov r2, r0 800791e: 69fb ldr r3, [r7, #28] 8007920: 1ad3 subs r3, r2, r3 8007922: 2b01 cmp r3, #1 8007924: d90f bls.n 8007946 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8007926: 68fb ldr r3, [r7, #12] 8007928: 681b ldr r3, [r3, #0] 800792a: 6b5b ldr r3, [r3, #52] @ 0x34 800792c: 2b00 cmp r3, #0 800792e: da0a bge.n 8007946 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8007930: 68fb ldr r3, [r7, #12] 8007932: 691b ldr r3, [r3, #16] 8007934: f043 0208 orr.w r2, r3, #8 8007938: 68fb ldr r3, [r7, #12] 800793a: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 800793c: 68fb ldr r3, [r7, #12] 800793e: 2203 movs r2, #3 8007940: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8007942: 2303 movs r3, #3 8007944: e0d6 b.n 8007af4 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8007946: 68fb ldr r3, [r7, #12] 8007948: 681b ldr r3, [r3, #0] 800794a: 6b5b ldr r3, [r3, #52] @ 0x34 800794c: 2b00 cmp r3, #0 800794e: dbe3 blt.n 8007918 } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8007950: 68fb ldr r3, [r7, #12] 8007952: 681b ldr r3, [r3, #0] 8007954: 68ba ldr r2, [r7, #8] 8007956: 6992 ldr r2, [r2, #24] 8007958: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 800795a: 68fb ldr r3, [r7, #12] 800795c: 681b ldr r3, [r3, #0] 800795e: 6c9a ldr r2, [r3, #72] @ 0x48 8007960: 687b ldr r3, [r7, #4] 8007962: f003 0310 and.w r3, r3, #16 8007966: f240 31ff movw r1, #1023 @ 0x3ff 800796a: fa01 f303 lsl.w r3, r1, r3 800796e: 43db mvns r3, r3 8007970: ea02 0103 and.w r1, r2, r3 8007974: 68bb ldr r3, [r7, #8] 8007976: 69da ldr r2, [r3, #28] 8007978: 687b ldr r3, [r7, #4] 800797a: f003 0310 and.w r3, r3, #16 800797e: 409a lsls r2, r3 8007980: 68fb ldr r3, [r7, #12] 8007982: 681b ldr r3, [r3, #0] 8007984: 430a orrs r2, r1 8007986: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 8007988: 68fb ldr r3, [r7, #12] 800798a: 681b ldr r3, [r3, #0] 800798c: 6cda ldr r2, [r3, #76] @ 0x4c 800798e: 687b ldr r3, [r7, #4] 8007990: f003 0310 and.w r3, r3, #16 8007994: 21ff movs r1, #255 @ 0xff 8007996: fa01 f303 lsl.w r3, r1, r3 800799a: 43db mvns r3, r3 800799c: ea02 0103 and.w r1, r2, r3 80079a0: 68bb ldr r3, [r7, #8] 80079a2: 6a1a ldr r2, [r3, #32] 80079a4: 687b ldr r3, [r7, #4] 80079a6: f003 0310 and.w r3, r3, #16 80079aa: 409a lsls r2, r3 80079ac: 68fb ldr r3, [r7, #12] 80079ae: 681b ldr r3, [r3, #0] 80079b0: 430a orrs r2, r1 80079b2: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 80079b4: 68bb ldr r3, [r7, #8] 80079b6: 691b ldr r3, [r3, #16] 80079b8: 2b01 cmp r3, #1 80079ba: d11d bne.n 80079f8 /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 80079bc: 68fb ldr r3, [r7, #12] 80079be: 681b ldr r3, [r3, #0] 80079c0: 6b9b ldr r3, [r3, #56] @ 0x38 80079c2: 61bb str r3, [r7, #24] /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 80079c4: 687b ldr r3, [r7, #4] 80079c6: f003 0310 and.w r3, r3, #16 80079ca: 221f movs r2, #31 80079cc: fa02 f303 lsl.w r3, r2, r3 80079d0: 43db mvns r3, r3 80079d2: 69ba ldr r2, [r7, #24] 80079d4: 4013 ands r3, r2 80079d6: 61bb str r3, [r7, #24] /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 80079d8: 68bb ldr r3, [r7, #8] 80079da: 695b ldr r3, [r3, #20] 80079dc: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80079de: 687b ldr r3, [r7, #4] 80079e0: f003 0310 and.w r3, r3, #16 80079e4: 697a ldr r2, [r7, #20] 80079e6: fa02 f303 lsl.w r3, r2, r3 80079ea: 69ba ldr r2, [r7, #24] 80079ec: 4313 orrs r3, r2 80079ee: 61bb str r3, [r7, #24] /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 80079f0: 68fb ldr r3, [r7, #12] 80079f2: 681b ldr r3, [r3, #0] 80079f4: 69ba ldr r2, [r7, #24] 80079f6: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 80079f8: 68fb ldr r3, [r7, #12] 80079fa: 681b ldr r3, [r3, #0] 80079fc: 6bdb ldr r3, [r3, #60] @ 0x3c 80079fe: 61bb str r3, [r7, #24] /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 8007a00: 687b ldr r3, [r7, #4] 8007a02: f003 0310 and.w r3, r3, #16 8007a06: 2207 movs r2, #7 8007a08: fa02 f303 lsl.w r3, r2, r3 8007a0c: 43db mvns r3, r3 8007a0e: 69ba ldr r2, [r7, #24] 8007a10: 4013 ands r3, r2 8007a12: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 8007a14: 68bb ldr r3, [r7, #8] 8007a16: 68db ldr r3, [r3, #12] 8007a18: 2b01 cmp r3, #1 8007a1a: d102 bne.n 8007a22 { connectOnChip = 0x00000000UL; 8007a1c: 2300 movs r3, #0 8007a1e: 627b str r3, [r7, #36] @ 0x24 8007a20: e00f b.n 8007a42 } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 8007a22: 68bb ldr r3, [r7, #8] 8007a24: 68db ldr r3, [r3, #12] 8007a26: 2b02 cmp r3, #2 8007a28: d102 bne.n 8007a30 { connectOnChip = DAC_MCR_MODE1_0; 8007a2a: 2301 movs r3, #1 8007a2c: 627b str r3, [r7, #36] @ 0x24 8007a2e: e008 b.n 8007a42 } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 8007a30: 68bb ldr r3, [r7, #8] 8007a32: 689b ldr r3, [r3, #8] 8007a34: 2b00 cmp r3, #0 8007a36: d102 bne.n 8007a3e { connectOnChip = DAC_MCR_MODE1_0; 8007a38: 2301 movs r3, #1 8007a3a: 627b str r3, [r7, #36] @ 0x24 8007a3c: e001 b.n 8007a42 } else { connectOnChip = 0x00000000UL; 8007a3e: 2300 movs r3, #0 8007a40: 627b str r3, [r7, #36] @ 0x24 } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 8007a42: 68bb ldr r3, [r7, #8] 8007a44: 681a ldr r2, [r3, #0] 8007a46: 68bb ldr r3, [r7, #8] 8007a48: 689b ldr r3, [r3, #8] 8007a4a: 4313 orrs r3, r2 8007a4c: 6a7a ldr r2, [r7, #36] @ 0x24 8007a4e: 4313 orrs r3, r2 8007a50: 617b str r3, [r7, #20] /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8007a52: 687b ldr r3, [r7, #4] 8007a54: f003 0310 and.w r3, r3, #16 8007a58: 697a ldr r2, [r7, #20] 8007a5a: fa02 f303 lsl.w r3, r2, r3 8007a5e: 69ba ldr r2, [r7, #24] 8007a60: 4313 orrs r3, r2 8007a62: 61bb str r3, [r7, #24] /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 8007a64: 68fb ldr r3, [r7, #12] 8007a66: 681b ldr r3, [r3, #0] 8007a68: 69ba ldr r2, [r7, #24] 8007a6a: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 8007a6c: 68fb ldr r3, [r7, #12] 8007a6e: 681b ldr r3, [r3, #0] 8007a70: 6819 ldr r1, [r3, #0] 8007a72: 687b ldr r3, [r7, #4] 8007a74: f003 0310 and.w r3, r3, #16 8007a78: f44f 4280 mov.w r2, #16384 @ 0x4000 8007a7c: fa02 f303 lsl.w r3, r2, r3 8007a80: 43da mvns r2, r3 8007a82: 68fb ldr r3, [r7, #12] 8007a84: 681b ldr r3, [r3, #0] 8007a86: 400a ands r2, r1 8007a88: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 8007a8a: 68fb ldr r3, [r7, #12] 8007a8c: 681b ldr r3, [r3, #0] 8007a8e: 681b ldr r3, [r3, #0] 8007a90: 61bb str r3, [r7, #24] /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 8007a92: 687b ldr r3, [r7, #4] 8007a94: f003 0310 and.w r3, r3, #16 8007a98: f640 72fe movw r2, #4094 @ 0xffe 8007a9c: fa02 f303 lsl.w r3, r2, r3 8007aa0: 43db mvns r3, r3 8007aa2: 69ba ldr r2, [r7, #24] 8007aa4: 4013 ands r3, r2 8007aa6: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 8007aa8: 68bb ldr r3, [r7, #8] 8007aaa: 685b ldr r3, [r3, #4] 8007aac: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8007aae: 687b ldr r3, [r7, #4] 8007ab0: f003 0310 and.w r3, r3, #16 8007ab4: 697a ldr r2, [r7, #20] 8007ab6: fa02 f303 lsl.w r3, r2, r3 8007aba: 69ba ldr r2, [r7, #24] 8007abc: 4313 orrs r3, r2 8007abe: 61bb str r3, [r7, #24] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 8007ac0: 68fb ldr r3, [r7, #12] 8007ac2: 681b ldr r3, [r3, #0] 8007ac4: 69ba ldr r2, [r7, #24] 8007ac6: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 8007ac8: 68fb ldr r3, [r7, #12] 8007aca: 681b ldr r3, [r3, #0] 8007acc: 6819 ldr r1, [r3, #0] 8007ace: 687b ldr r3, [r7, #4] 8007ad0: f003 0310 and.w r3, r3, #16 8007ad4: 22c0 movs r2, #192 @ 0xc0 8007ad6: fa02 f303 lsl.w r3, r2, r3 8007ada: 43da mvns r2, r3 8007adc: 68fb ldr r3, [r7, #12] 8007ade: 681b ldr r3, [r3, #0] 8007ae0: 400a ands r2, r1 8007ae2: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8007ae4: 68fb ldr r3, [r7, #12] 8007ae6: 2201 movs r2, #1 8007ae8: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8007aea: 68fb ldr r3, [r7, #12] 8007aec: 2200 movs r2, #0 8007aee: 715a strb r2, [r3, #5] /* Return function status */ return status; 8007af0: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 8007af4: 4618 mov r0, r3 8007af6: 3728 adds r7, #40 @ 0x28 8007af8: 46bd mov sp, r7 8007afa: bd80 pop {r7, pc} 8007afc: 20008000 .word 0x20008000 08007b00 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { 8007b00: b480 push {r7} 8007b02: b083 sub sp, #12 8007b04: af00 add r7, sp, #0 8007b06: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } 8007b08: bf00 nop 8007b0a: 370c adds r7, #12 8007b0c: 46bd mov sp, r7 8007b0e: f85d 7b04 ldr.w r7, [sp], #4 8007b12: 4770 bx lr 08007b14 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8007b14: b580 push {r7, lr} 8007b16: b086 sub sp, #24 8007b18: af00 add r7, sp, #0 8007b1a: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 8007b1c: f7fd fc5e bl 80053dc 8007b20: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8007b22: 687b ldr r3, [r7, #4] 8007b24: 2b00 cmp r3, #0 8007b26: d101 bne.n 8007b2c { return HAL_ERROR; 8007b28: 2301 movs r3, #1 8007b2a: e316 b.n 800815a assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8007b2c: 687b ldr r3, [r7, #4] 8007b2e: 681b ldr r3, [r3, #0] 8007b30: 4a66 ldr r2, [pc, #408] @ (8007ccc ) 8007b32: 4293 cmp r3, r2 8007b34: d04a beq.n 8007bcc 8007b36: 687b ldr r3, [r7, #4] 8007b38: 681b ldr r3, [r3, #0] 8007b3a: 4a65 ldr r2, [pc, #404] @ (8007cd0 ) 8007b3c: 4293 cmp r3, r2 8007b3e: d045 beq.n 8007bcc 8007b40: 687b ldr r3, [r7, #4] 8007b42: 681b ldr r3, [r3, #0] 8007b44: 4a63 ldr r2, [pc, #396] @ (8007cd4 ) 8007b46: 4293 cmp r3, r2 8007b48: d040 beq.n 8007bcc 8007b4a: 687b ldr r3, [r7, #4] 8007b4c: 681b ldr r3, [r3, #0] 8007b4e: 4a62 ldr r2, [pc, #392] @ (8007cd8 ) 8007b50: 4293 cmp r3, r2 8007b52: d03b beq.n 8007bcc 8007b54: 687b ldr r3, [r7, #4] 8007b56: 681b ldr r3, [r3, #0] 8007b58: 4a60 ldr r2, [pc, #384] @ (8007cdc ) 8007b5a: 4293 cmp r3, r2 8007b5c: d036 beq.n 8007bcc 8007b5e: 687b ldr r3, [r7, #4] 8007b60: 681b ldr r3, [r3, #0] 8007b62: 4a5f ldr r2, [pc, #380] @ (8007ce0 ) 8007b64: 4293 cmp r3, r2 8007b66: d031 beq.n 8007bcc 8007b68: 687b ldr r3, [r7, #4] 8007b6a: 681b ldr r3, [r3, #0] 8007b6c: 4a5d ldr r2, [pc, #372] @ (8007ce4 ) 8007b6e: 4293 cmp r3, r2 8007b70: d02c beq.n 8007bcc 8007b72: 687b ldr r3, [r7, #4] 8007b74: 681b ldr r3, [r3, #0] 8007b76: 4a5c ldr r2, [pc, #368] @ (8007ce8 ) 8007b78: 4293 cmp r3, r2 8007b7a: d027 beq.n 8007bcc 8007b7c: 687b ldr r3, [r7, #4] 8007b7e: 681b ldr r3, [r3, #0] 8007b80: 4a5a ldr r2, [pc, #360] @ (8007cec ) 8007b82: 4293 cmp r3, r2 8007b84: d022 beq.n 8007bcc 8007b86: 687b ldr r3, [r7, #4] 8007b88: 681b ldr r3, [r3, #0] 8007b8a: 4a59 ldr r2, [pc, #356] @ (8007cf0 ) 8007b8c: 4293 cmp r3, r2 8007b8e: d01d beq.n 8007bcc 8007b90: 687b ldr r3, [r7, #4] 8007b92: 681b ldr r3, [r3, #0] 8007b94: 4a57 ldr r2, [pc, #348] @ (8007cf4 ) 8007b96: 4293 cmp r3, r2 8007b98: d018 beq.n 8007bcc 8007b9a: 687b ldr r3, [r7, #4] 8007b9c: 681b ldr r3, [r3, #0] 8007b9e: 4a56 ldr r2, [pc, #344] @ (8007cf8 ) 8007ba0: 4293 cmp r3, r2 8007ba2: d013 beq.n 8007bcc 8007ba4: 687b ldr r3, [r7, #4] 8007ba6: 681b ldr r3, [r3, #0] 8007ba8: 4a54 ldr r2, [pc, #336] @ (8007cfc ) 8007baa: 4293 cmp r3, r2 8007bac: d00e beq.n 8007bcc 8007bae: 687b ldr r3, [r7, #4] 8007bb0: 681b ldr r3, [r3, #0] 8007bb2: 4a53 ldr r2, [pc, #332] @ (8007d00 ) 8007bb4: 4293 cmp r3, r2 8007bb6: d009 beq.n 8007bcc 8007bb8: 687b ldr r3, [r7, #4] 8007bba: 681b ldr r3, [r3, #0] 8007bbc: 4a51 ldr r2, [pc, #324] @ (8007d04 ) 8007bbe: 4293 cmp r3, r2 8007bc0: d004 beq.n 8007bcc 8007bc2: 687b ldr r3, [r7, #4] 8007bc4: 681b ldr r3, [r3, #0] 8007bc6: 4a50 ldr r2, [pc, #320] @ (8007d08 ) 8007bc8: 4293 cmp r3, r2 8007bca: d101 bne.n 8007bd0 8007bcc: 2301 movs r3, #1 8007bce: e000 b.n 8007bd2 8007bd0: 2300 movs r3, #0 8007bd2: 2b00 cmp r3, #0 8007bd4: f000 813b beq.w 8007e4e assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8007bd8: 687b ldr r3, [r7, #4] 8007bda: 2202 movs r2, #2 8007bdc: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8007be0: 687b ldr r3, [r7, #4] 8007be2: 2200 movs r2, #0 8007be4: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8007be8: 687b ldr r3, [r7, #4] 8007bea: 681b ldr r3, [r3, #0] 8007bec: 4a37 ldr r2, [pc, #220] @ (8007ccc ) 8007bee: 4293 cmp r3, r2 8007bf0: d04a beq.n 8007c88 8007bf2: 687b ldr r3, [r7, #4] 8007bf4: 681b ldr r3, [r3, #0] 8007bf6: 4a36 ldr r2, [pc, #216] @ (8007cd0 ) 8007bf8: 4293 cmp r3, r2 8007bfa: d045 beq.n 8007c88 8007bfc: 687b ldr r3, [r7, #4] 8007bfe: 681b ldr r3, [r3, #0] 8007c00: 4a34 ldr r2, [pc, #208] @ (8007cd4 ) 8007c02: 4293 cmp r3, r2 8007c04: d040 beq.n 8007c88 8007c06: 687b ldr r3, [r7, #4] 8007c08: 681b ldr r3, [r3, #0] 8007c0a: 4a33 ldr r2, [pc, #204] @ (8007cd8 ) 8007c0c: 4293 cmp r3, r2 8007c0e: d03b beq.n 8007c88 8007c10: 687b ldr r3, [r7, #4] 8007c12: 681b ldr r3, [r3, #0] 8007c14: 4a31 ldr r2, [pc, #196] @ (8007cdc ) 8007c16: 4293 cmp r3, r2 8007c18: d036 beq.n 8007c88 8007c1a: 687b ldr r3, [r7, #4] 8007c1c: 681b ldr r3, [r3, #0] 8007c1e: 4a30 ldr r2, [pc, #192] @ (8007ce0 ) 8007c20: 4293 cmp r3, r2 8007c22: d031 beq.n 8007c88 8007c24: 687b ldr r3, [r7, #4] 8007c26: 681b ldr r3, [r3, #0] 8007c28: 4a2e ldr r2, [pc, #184] @ (8007ce4 ) 8007c2a: 4293 cmp r3, r2 8007c2c: d02c beq.n 8007c88 8007c2e: 687b ldr r3, [r7, #4] 8007c30: 681b ldr r3, [r3, #0] 8007c32: 4a2d ldr r2, [pc, #180] @ (8007ce8 ) 8007c34: 4293 cmp r3, r2 8007c36: d027 beq.n 8007c88 8007c38: 687b ldr r3, [r7, #4] 8007c3a: 681b ldr r3, [r3, #0] 8007c3c: 4a2b ldr r2, [pc, #172] @ (8007cec ) 8007c3e: 4293 cmp r3, r2 8007c40: d022 beq.n 8007c88 8007c42: 687b ldr r3, [r7, #4] 8007c44: 681b ldr r3, [r3, #0] 8007c46: 4a2a ldr r2, [pc, #168] @ (8007cf0 ) 8007c48: 4293 cmp r3, r2 8007c4a: d01d beq.n 8007c88 8007c4c: 687b ldr r3, [r7, #4] 8007c4e: 681b ldr r3, [r3, #0] 8007c50: 4a28 ldr r2, [pc, #160] @ (8007cf4 ) 8007c52: 4293 cmp r3, r2 8007c54: d018 beq.n 8007c88 8007c56: 687b ldr r3, [r7, #4] 8007c58: 681b ldr r3, [r3, #0] 8007c5a: 4a27 ldr r2, [pc, #156] @ (8007cf8 ) 8007c5c: 4293 cmp r3, r2 8007c5e: d013 beq.n 8007c88 8007c60: 687b ldr r3, [r7, #4] 8007c62: 681b ldr r3, [r3, #0] 8007c64: 4a25 ldr r2, [pc, #148] @ (8007cfc ) 8007c66: 4293 cmp r3, r2 8007c68: d00e beq.n 8007c88 8007c6a: 687b ldr r3, [r7, #4] 8007c6c: 681b ldr r3, [r3, #0] 8007c6e: 4a24 ldr r2, [pc, #144] @ (8007d00 ) 8007c70: 4293 cmp r3, r2 8007c72: d009 beq.n 8007c88 8007c74: 687b ldr r3, [r7, #4] 8007c76: 681b ldr r3, [r3, #0] 8007c78: 4a22 ldr r2, [pc, #136] @ (8007d04 ) 8007c7a: 4293 cmp r3, r2 8007c7c: d004 beq.n 8007c88 8007c7e: 687b ldr r3, [r7, #4] 8007c80: 681b ldr r3, [r3, #0] 8007c82: 4a21 ldr r2, [pc, #132] @ (8007d08 ) 8007c84: 4293 cmp r3, r2 8007c86: d108 bne.n 8007c9a 8007c88: 687b ldr r3, [r7, #4] 8007c8a: 681b ldr r3, [r3, #0] 8007c8c: 681a ldr r2, [r3, #0] 8007c8e: 687b ldr r3, [r7, #4] 8007c90: 681b ldr r3, [r3, #0] 8007c92: f022 0201 bic.w r2, r2, #1 8007c96: 601a str r2, [r3, #0] 8007c98: e007 b.n 8007caa 8007c9a: 687b ldr r3, [r7, #4] 8007c9c: 681b ldr r3, [r3, #0] 8007c9e: 681a ldr r2, [r3, #0] 8007ca0: 687b ldr r3, [r7, #4] 8007ca2: 681b ldr r3, [r3, #0] 8007ca4: f022 0201 bic.w r2, r2, #1 8007ca8: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8007caa: e02f b.n 8007d0c { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8007cac: f7fd fb96 bl 80053dc 8007cb0: 4602 mov r2, r0 8007cb2: 693b ldr r3, [r7, #16] 8007cb4: 1ad3 subs r3, r2, r3 8007cb6: 2b05 cmp r3, #5 8007cb8: d928 bls.n 8007d0c { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8007cba: 687b ldr r3, [r7, #4] 8007cbc: 2220 movs r2, #32 8007cbe: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8007cc0: 687b ldr r3, [r7, #4] 8007cc2: 2203 movs r2, #3 8007cc4: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8007cc8: 2301 movs r3, #1 8007cca: e246 b.n 800815a 8007ccc: 40020010 .word 0x40020010 8007cd0: 40020028 .word 0x40020028 8007cd4: 40020040 .word 0x40020040 8007cd8: 40020058 .word 0x40020058 8007cdc: 40020070 .word 0x40020070 8007ce0: 40020088 .word 0x40020088 8007ce4: 400200a0 .word 0x400200a0 8007ce8: 400200b8 .word 0x400200b8 8007cec: 40020410 .word 0x40020410 8007cf0: 40020428 .word 0x40020428 8007cf4: 40020440 .word 0x40020440 8007cf8: 40020458 .word 0x40020458 8007cfc: 40020470 .word 0x40020470 8007d00: 40020488 .word 0x40020488 8007d04: 400204a0 .word 0x400204a0 8007d08: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8007d0c: 687b ldr r3, [r7, #4] 8007d0e: 681b ldr r3, [r3, #0] 8007d10: 681b ldr r3, [r3, #0] 8007d12: f003 0301 and.w r3, r3, #1 8007d16: 2b00 cmp r3, #0 8007d18: d1c8 bne.n 8007cac } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 8007d1a: 687b ldr r3, [r7, #4] 8007d1c: 681b ldr r3, [r3, #0] 8007d1e: 681b ldr r3, [r3, #0] 8007d20: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8007d22: 697a ldr r2, [r7, #20] 8007d24: 4b83 ldr r3, [pc, #524] @ (8007f34 ) 8007d26: 4013 ands r3, r2 8007d28: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 8007d2a: 687b ldr r3, [r7, #4] 8007d2c: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8007d2e: 687b ldr r3, [r7, #4] 8007d30: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 8007d32: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8007d34: 687b ldr r3, [r7, #4] 8007d36: 691b ldr r3, [r3, #16] 8007d38: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8007d3a: 687b ldr r3, [r7, #4] 8007d3c: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8007d3e: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8007d40: 687b ldr r3, [r7, #4] 8007d42: 699b ldr r3, [r3, #24] 8007d44: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8007d46: 687b ldr r3, [r7, #4] 8007d48: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8007d4a: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8007d4c: 687b ldr r3, [r7, #4] 8007d4e: 6a1b ldr r3, [r3, #32] 8007d50: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 8007d52: 697a ldr r2, [r7, #20] 8007d54: 4313 orrs r3, r2 8007d56: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8007d58: 687b ldr r3, [r7, #4] 8007d5a: 6a5b ldr r3, [r3, #36] @ 0x24 8007d5c: 2b04 cmp r3, #4 8007d5e: d107 bne.n 8007d70 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 8007d60: 687b ldr r3, [r7, #4] 8007d62: 6ada ldr r2, [r3, #44] @ 0x2c 8007d64: 687b ldr r3, [r7, #4] 8007d66: 6b1b ldr r3, [r3, #48] @ 0x30 8007d68: 4313 orrs r3, r2 8007d6a: 697a ldr r2, [r7, #20] 8007d6c: 4313 orrs r3, r2 8007d6e: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 8007d70: 4b71 ldr r3, [pc, #452] @ (8007f38 ) 8007d72: 681a ldr r2, [r3, #0] 8007d74: 4b71 ldr r3, [pc, #452] @ (8007f3c ) 8007d76: 4013 ands r3, r2 8007d78: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8007d7c: d328 bcc.n 8007dd0 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 8007d7e: 687b ldr r3, [r7, #4] 8007d80: 685b ldr r3, [r3, #4] 8007d82: 2b28 cmp r3, #40 @ 0x28 8007d84: d903 bls.n 8007d8e 8007d86: 687b ldr r3, [r7, #4] 8007d88: 685b ldr r3, [r3, #4] 8007d8a: 2b2e cmp r3, #46 @ 0x2e 8007d8c: d917 bls.n 8007dbe 8007d8e: 687b ldr r3, [r7, #4] 8007d90: 685b ldr r3, [r3, #4] 8007d92: 2b3e cmp r3, #62 @ 0x3e 8007d94: d903 bls.n 8007d9e 8007d96: 687b ldr r3, [r7, #4] 8007d98: 685b ldr r3, [r3, #4] 8007d9a: 2b42 cmp r3, #66 @ 0x42 8007d9c: d90f bls.n 8007dbe 8007d9e: 687b ldr r3, [r7, #4] 8007da0: 685b ldr r3, [r3, #4] 8007da2: 2b46 cmp r3, #70 @ 0x46 8007da4: d903 bls.n 8007dae 8007da6: 687b ldr r3, [r7, #4] 8007da8: 685b ldr r3, [r3, #4] 8007daa: 2b48 cmp r3, #72 @ 0x48 8007dac: d907 bls.n 8007dbe 8007dae: 687b ldr r3, [r7, #4] 8007db0: 685b ldr r3, [r3, #4] 8007db2: 2b4e cmp r3, #78 @ 0x4e 8007db4: d905 bls.n 8007dc2 8007db6: 687b ldr r3, [r7, #4] 8007db8: 685b ldr r3, [r3, #4] 8007dba: 2b52 cmp r3, #82 @ 0x52 8007dbc: d801 bhi.n 8007dc2 8007dbe: 2301 movs r3, #1 8007dc0: e000 b.n 8007dc4 8007dc2: 2300 movs r3, #0 8007dc4: 2b00 cmp r3, #0 8007dc6: d003 beq.n 8007dd0 { registerValue |= DMA_SxCR_TRBUFF; 8007dc8: 697b ldr r3, [r7, #20] 8007dca: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8007dce: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8007dd0: 687b ldr r3, [r7, #4] 8007dd2: 681b ldr r3, [r3, #0] 8007dd4: 697a ldr r2, [r7, #20] 8007dd6: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 8007dd8: 687b ldr r3, [r7, #4] 8007dda: 681b ldr r3, [r3, #0] 8007ddc: 695b ldr r3, [r3, #20] 8007dde: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8007de0: 697b ldr r3, [r7, #20] 8007de2: f023 0307 bic.w r3, r3, #7 8007de6: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 8007de8: 687b ldr r3, [r7, #4] 8007dea: 6a5b ldr r3, [r3, #36] @ 0x24 8007dec: 697a ldr r2, [r7, #20] 8007dee: 4313 orrs r3, r2 8007df0: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8007df2: 687b ldr r3, [r7, #4] 8007df4: 6a5b ldr r3, [r3, #36] @ 0x24 8007df6: 2b04 cmp r3, #4 8007df8: d117 bne.n 8007e2a { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 8007dfa: 687b ldr r3, [r7, #4] 8007dfc: 6a9b ldr r3, [r3, #40] @ 0x28 8007dfe: 697a ldr r2, [r7, #20] 8007e00: 4313 orrs r3, r2 8007e02: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8007e04: 687b ldr r3, [r7, #4] 8007e06: 6adb ldr r3, [r3, #44] @ 0x2c 8007e08: 2b00 cmp r3, #0 8007e0a: d00e beq.n 8007e2a { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8007e0c: 6878 ldr r0, [r7, #4] 8007e0e: f002 fb33 bl 800a478 8007e12: 4603 mov r3, r0 8007e14: 2b00 cmp r3, #0 8007e16: d008 beq.n 8007e2a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8007e18: 687b ldr r3, [r7, #4] 8007e1a: 2240 movs r2, #64 @ 0x40 8007e1c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8007e1e: 687b ldr r3, [r7, #4] 8007e20: 2201 movs r2, #1 8007e22: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8007e26: 2301 movs r3, #1 8007e28: e197 b.n 800815a } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 8007e2a: 687b ldr r3, [r7, #4] 8007e2c: 681b ldr r3, [r3, #0] 8007e2e: 697a ldr r2, [r7, #20] 8007e30: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8007e32: 6878 ldr r0, [r7, #4] 8007e34: f002 fa6e bl 800a314 8007e38: 4603 mov r3, r0 8007e3a: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8007e3c: 687b ldr r3, [r7, #4] 8007e3e: 6ddb ldr r3, [r3, #92] @ 0x5c 8007e40: f003 031f and.w r3, r3, #31 8007e44: 223f movs r2, #63 @ 0x3f 8007e46: 409a lsls r2, r3 8007e48: 68bb ldr r3, [r7, #8] 8007e4a: 609a str r2, [r3, #8] 8007e4c: e0cd b.n 8007fea } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8007e4e: 687b ldr r3, [r7, #4] 8007e50: 681b ldr r3, [r3, #0] 8007e52: 4a3b ldr r2, [pc, #236] @ (8007f40 ) 8007e54: 4293 cmp r3, r2 8007e56: d022 beq.n 8007e9e 8007e58: 687b ldr r3, [r7, #4] 8007e5a: 681b ldr r3, [r3, #0] 8007e5c: 4a39 ldr r2, [pc, #228] @ (8007f44 ) 8007e5e: 4293 cmp r3, r2 8007e60: d01d beq.n 8007e9e 8007e62: 687b ldr r3, [r7, #4] 8007e64: 681b ldr r3, [r3, #0] 8007e66: 4a38 ldr r2, [pc, #224] @ (8007f48 ) 8007e68: 4293 cmp r3, r2 8007e6a: d018 beq.n 8007e9e 8007e6c: 687b ldr r3, [r7, #4] 8007e6e: 681b ldr r3, [r3, #0] 8007e70: 4a36 ldr r2, [pc, #216] @ (8007f4c ) 8007e72: 4293 cmp r3, r2 8007e74: d013 beq.n 8007e9e 8007e76: 687b ldr r3, [r7, #4] 8007e78: 681b ldr r3, [r3, #0] 8007e7a: 4a35 ldr r2, [pc, #212] @ (8007f50 ) 8007e7c: 4293 cmp r3, r2 8007e7e: d00e beq.n 8007e9e 8007e80: 687b ldr r3, [r7, #4] 8007e82: 681b ldr r3, [r3, #0] 8007e84: 4a33 ldr r2, [pc, #204] @ (8007f54 ) 8007e86: 4293 cmp r3, r2 8007e88: d009 beq.n 8007e9e 8007e8a: 687b ldr r3, [r7, #4] 8007e8c: 681b ldr r3, [r3, #0] 8007e8e: 4a32 ldr r2, [pc, #200] @ (8007f58 ) 8007e90: 4293 cmp r3, r2 8007e92: d004 beq.n 8007e9e 8007e94: 687b ldr r3, [r7, #4] 8007e96: 681b ldr r3, [r3, #0] 8007e98: 4a30 ldr r2, [pc, #192] @ (8007f5c ) 8007e9a: 4293 cmp r3, r2 8007e9c: d101 bne.n 8007ea2 8007e9e: 2301 movs r3, #1 8007ea0: e000 b.n 8007ea4 8007ea2: 2300 movs r3, #0 8007ea4: 2b00 cmp r3, #0 8007ea6: f000 8097 beq.w 8007fd8 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 8007eaa: 687b ldr r3, [r7, #4] 8007eac: 681b ldr r3, [r3, #0] 8007eae: 4a24 ldr r2, [pc, #144] @ (8007f40 ) 8007eb0: 4293 cmp r3, r2 8007eb2: d021 beq.n 8007ef8 8007eb4: 687b ldr r3, [r7, #4] 8007eb6: 681b ldr r3, [r3, #0] 8007eb8: 4a22 ldr r2, [pc, #136] @ (8007f44 ) 8007eba: 4293 cmp r3, r2 8007ebc: d01c beq.n 8007ef8 8007ebe: 687b ldr r3, [r7, #4] 8007ec0: 681b ldr r3, [r3, #0] 8007ec2: 4a21 ldr r2, [pc, #132] @ (8007f48 ) 8007ec4: 4293 cmp r3, r2 8007ec6: d017 beq.n 8007ef8 8007ec8: 687b ldr r3, [r7, #4] 8007eca: 681b ldr r3, [r3, #0] 8007ecc: 4a1f ldr r2, [pc, #124] @ (8007f4c ) 8007ece: 4293 cmp r3, r2 8007ed0: d012 beq.n 8007ef8 8007ed2: 687b ldr r3, [r7, #4] 8007ed4: 681b ldr r3, [r3, #0] 8007ed6: 4a1e ldr r2, [pc, #120] @ (8007f50 ) 8007ed8: 4293 cmp r3, r2 8007eda: d00d beq.n 8007ef8 8007edc: 687b ldr r3, [r7, #4] 8007ede: 681b ldr r3, [r3, #0] 8007ee0: 4a1c ldr r2, [pc, #112] @ (8007f54 ) 8007ee2: 4293 cmp r3, r2 8007ee4: d008 beq.n 8007ef8 8007ee6: 687b ldr r3, [r7, #4] 8007ee8: 681b ldr r3, [r3, #0] 8007eea: 4a1b ldr r2, [pc, #108] @ (8007f58 ) 8007eec: 4293 cmp r3, r2 8007eee: d003 beq.n 8007ef8 8007ef0: 687b ldr r3, [r7, #4] 8007ef2: 681b ldr r3, [r3, #0] 8007ef4: 4a19 ldr r2, [pc, #100] @ (8007f5c ) 8007ef6: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8007ef8: 687b ldr r3, [r7, #4] 8007efa: 2202 movs r2, #2 8007efc: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8007f00: 687b ldr r3, [r7, #4] 8007f02: 2200 movs r2, #0 8007f04: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 8007f08: 687b ldr r3, [r7, #4] 8007f0a: 681b ldr r3, [r3, #0] 8007f0c: 681b ldr r3, [r3, #0] 8007f0e: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8007f10: 697a ldr r2, [r7, #20] 8007f12: 4b13 ldr r3, [pc, #76] @ (8007f60 ) 8007f14: 4013 ands r3, r2 8007f16: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8007f18: 687b ldr r3, [r7, #4] 8007f1a: 689b ldr r3, [r3, #8] 8007f1c: 2b40 cmp r3, #64 @ 0x40 8007f1e: d021 beq.n 8007f64 8007f20: 687b ldr r3, [r7, #4] 8007f22: 689b ldr r3, [r3, #8] 8007f24: 2b80 cmp r3, #128 @ 0x80 8007f26: d102 bne.n 8007f2e 8007f28: f44f 4380 mov.w r3, #16384 @ 0x4000 8007f2c: e01b b.n 8007f66 8007f2e: 2300 movs r3, #0 8007f30: e019 b.n 8007f66 8007f32: bf00 nop 8007f34: fe10803f .word 0xfe10803f 8007f38: 5c001000 .word 0x5c001000 8007f3c: ffff0000 .word 0xffff0000 8007f40: 58025408 .word 0x58025408 8007f44: 5802541c .word 0x5802541c 8007f48: 58025430 .word 0x58025430 8007f4c: 58025444 .word 0x58025444 8007f50: 58025458 .word 0x58025458 8007f54: 5802546c .word 0x5802546c 8007f58: 58025480 .word 0x58025480 8007f5c: 58025494 .word 0x58025494 8007f60: fffe000f .word 0xfffe000f 8007f64: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8007f66: 687a ldr r2, [r7, #4] 8007f68: 68d2 ldr r2, [r2, #12] 8007f6a: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8007f6c: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8007f6e: 687b ldr r3, [r7, #4] 8007f70: 691b ldr r3, [r3, #16] 8007f72: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 8007f74: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8007f76: 687b ldr r3, [r7, #4] 8007f78: 695b ldr r3, [r3, #20] 8007f7a: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 8007f7c: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8007f7e: 687b ldr r3, [r7, #4] 8007f80: 699b ldr r3, [r3, #24] 8007f82: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 8007f84: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8007f86: 687b ldr r3, [r7, #4] 8007f88: 69db ldr r3, [r3, #28] 8007f8a: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 8007f8c: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 8007f8e: 687b ldr r3, [r7, #4] 8007f90: 6a1b ldr r3, [r3, #32] 8007f92: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 8007f94: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8007f96: 697a ldr r2, [r7, #20] 8007f98: 4313 orrs r3, r2 8007f9a: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 8007f9c: 687b ldr r3, [r7, #4] 8007f9e: 681b ldr r3, [r3, #0] 8007fa0: 697a ldr r2, [r7, #20] 8007fa2: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 8007fa4: 687b ldr r3, [r7, #4] 8007fa6: 681b ldr r3, [r3, #0] 8007fa8: 461a mov r2, r3 8007faa: 4b6e ldr r3, [pc, #440] @ (8008164 ) 8007fac: 4413 add r3, r2 8007fae: 4a6e ldr r2, [pc, #440] @ (8008168 ) 8007fb0: fba2 2303 umull r2, r3, r2, r3 8007fb4: 091b lsrs r3, r3, #4 8007fb6: 009a lsls r2, r3, #2 8007fb8: 687b ldr r3, [r7, #4] 8007fba: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8007fbc: 6878 ldr r0, [r7, #4] 8007fbe: f002 f9a9 bl 800a314 8007fc2: 4603 mov r3, r0 8007fc4: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8007fc6: 687b ldr r3, [r7, #4] 8007fc8: 6ddb ldr r3, [r3, #92] @ 0x5c 8007fca: f003 031f and.w r3, r3, #31 8007fce: 2201 movs r2, #1 8007fd0: 409a lsls r2, r3 8007fd2: 68fb ldr r3, [r7, #12] 8007fd4: 605a str r2, [r3, #4] 8007fd6: e008 b.n 8007fea } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8007fd8: 687b ldr r3, [r7, #4] 8007fda: 2240 movs r2, #64 @ 0x40 8007fdc: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8007fde: 687b ldr r3, [r7, #4] 8007fe0: 2203 movs r2, #3 8007fe2: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8007fe6: 2301 movs r3, #1 8007fe8: e0b7 b.n 800815a } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8007fea: 687b ldr r3, [r7, #4] 8007fec: 681b ldr r3, [r3, #0] 8007fee: 4a5f ldr r2, [pc, #380] @ (800816c ) 8007ff0: 4293 cmp r3, r2 8007ff2: d072 beq.n 80080da 8007ff4: 687b ldr r3, [r7, #4] 8007ff6: 681b ldr r3, [r3, #0] 8007ff8: 4a5d ldr r2, [pc, #372] @ (8008170 ) 8007ffa: 4293 cmp r3, r2 8007ffc: d06d beq.n 80080da 8007ffe: 687b ldr r3, [r7, #4] 8008000: 681b ldr r3, [r3, #0] 8008002: 4a5c ldr r2, [pc, #368] @ (8008174 ) 8008004: 4293 cmp r3, r2 8008006: d068 beq.n 80080da 8008008: 687b ldr r3, [r7, #4] 800800a: 681b ldr r3, [r3, #0] 800800c: 4a5a ldr r2, [pc, #360] @ (8008178 ) 800800e: 4293 cmp r3, r2 8008010: d063 beq.n 80080da 8008012: 687b ldr r3, [r7, #4] 8008014: 681b ldr r3, [r3, #0] 8008016: 4a59 ldr r2, [pc, #356] @ (800817c ) 8008018: 4293 cmp r3, r2 800801a: d05e beq.n 80080da 800801c: 687b ldr r3, [r7, #4] 800801e: 681b ldr r3, [r3, #0] 8008020: 4a57 ldr r2, [pc, #348] @ (8008180 ) 8008022: 4293 cmp r3, r2 8008024: d059 beq.n 80080da 8008026: 687b ldr r3, [r7, #4] 8008028: 681b ldr r3, [r3, #0] 800802a: 4a56 ldr r2, [pc, #344] @ (8008184 ) 800802c: 4293 cmp r3, r2 800802e: d054 beq.n 80080da 8008030: 687b ldr r3, [r7, #4] 8008032: 681b ldr r3, [r3, #0] 8008034: 4a54 ldr r2, [pc, #336] @ (8008188 ) 8008036: 4293 cmp r3, r2 8008038: d04f beq.n 80080da 800803a: 687b ldr r3, [r7, #4] 800803c: 681b ldr r3, [r3, #0] 800803e: 4a53 ldr r2, [pc, #332] @ (800818c ) 8008040: 4293 cmp r3, r2 8008042: d04a beq.n 80080da 8008044: 687b ldr r3, [r7, #4] 8008046: 681b ldr r3, [r3, #0] 8008048: 4a51 ldr r2, [pc, #324] @ (8008190 ) 800804a: 4293 cmp r3, r2 800804c: d045 beq.n 80080da 800804e: 687b ldr r3, [r7, #4] 8008050: 681b ldr r3, [r3, #0] 8008052: 4a50 ldr r2, [pc, #320] @ (8008194 ) 8008054: 4293 cmp r3, r2 8008056: d040 beq.n 80080da 8008058: 687b ldr r3, [r7, #4] 800805a: 681b ldr r3, [r3, #0] 800805c: 4a4e ldr r2, [pc, #312] @ (8008198 ) 800805e: 4293 cmp r3, r2 8008060: d03b beq.n 80080da 8008062: 687b ldr r3, [r7, #4] 8008064: 681b ldr r3, [r3, #0] 8008066: 4a4d ldr r2, [pc, #308] @ (800819c ) 8008068: 4293 cmp r3, r2 800806a: d036 beq.n 80080da 800806c: 687b ldr r3, [r7, #4] 800806e: 681b ldr r3, [r3, #0] 8008070: 4a4b ldr r2, [pc, #300] @ (80081a0 ) 8008072: 4293 cmp r3, r2 8008074: d031 beq.n 80080da 8008076: 687b ldr r3, [r7, #4] 8008078: 681b ldr r3, [r3, #0] 800807a: 4a4a ldr r2, [pc, #296] @ (80081a4 ) 800807c: 4293 cmp r3, r2 800807e: d02c beq.n 80080da 8008080: 687b ldr r3, [r7, #4] 8008082: 681b ldr r3, [r3, #0] 8008084: 4a48 ldr r2, [pc, #288] @ (80081a8 ) 8008086: 4293 cmp r3, r2 8008088: d027 beq.n 80080da 800808a: 687b ldr r3, [r7, #4] 800808c: 681b ldr r3, [r3, #0] 800808e: 4a47 ldr r2, [pc, #284] @ (80081ac ) 8008090: 4293 cmp r3, r2 8008092: d022 beq.n 80080da 8008094: 687b ldr r3, [r7, #4] 8008096: 681b ldr r3, [r3, #0] 8008098: 4a45 ldr r2, [pc, #276] @ (80081b0 ) 800809a: 4293 cmp r3, r2 800809c: d01d beq.n 80080da 800809e: 687b ldr r3, [r7, #4] 80080a0: 681b ldr r3, [r3, #0] 80080a2: 4a44 ldr r2, [pc, #272] @ (80081b4 ) 80080a4: 4293 cmp r3, r2 80080a6: d018 beq.n 80080da 80080a8: 687b ldr r3, [r7, #4] 80080aa: 681b ldr r3, [r3, #0] 80080ac: 4a42 ldr r2, [pc, #264] @ (80081b8 ) 80080ae: 4293 cmp r3, r2 80080b0: d013 beq.n 80080da 80080b2: 687b ldr r3, [r7, #4] 80080b4: 681b ldr r3, [r3, #0] 80080b6: 4a41 ldr r2, [pc, #260] @ (80081bc ) 80080b8: 4293 cmp r3, r2 80080ba: d00e beq.n 80080da 80080bc: 687b ldr r3, [r7, #4] 80080be: 681b ldr r3, [r3, #0] 80080c0: 4a3f ldr r2, [pc, #252] @ (80081c0 ) 80080c2: 4293 cmp r3, r2 80080c4: d009 beq.n 80080da 80080c6: 687b ldr r3, [r7, #4] 80080c8: 681b ldr r3, [r3, #0] 80080ca: 4a3e ldr r2, [pc, #248] @ (80081c4 ) 80080cc: 4293 cmp r3, r2 80080ce: d004 beq.n 80080da 80080d0: 687b ldr r3, [r7, #4] 80080d2: 681b ldr r3, [r3, #0] 80080d4: 4a3c ldr r2, [pc, #240] @ (80081c8 ) 80080d6: 4293 cmp r3, r2 80080d8: d101 bne.n 80080de 80080da: 2301 movs r3, #1 80080dc: e000 b.n 80080e0 80080de: 2300 movs r3, #0 80080e0: 2b00 cmp r3, #0 80080e2: d032 beq.n 800814a { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 80080e4: 6878 ldr r0, [r7, #4] 80080e6: f002 fa43 bl 800a570 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 80080ea: 687b ldr r3, [r7, #4] 80080ec: 689b ldr r3, [r3, #8] 80080ee: 2b80 cmp r3, #128 @ 0x80 80080f0: d102 bne.n 80080f8 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 80080f2: 687b ldr r3, [r7, #4] 80080f4: 2200 movs r2, #0 80080f6: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 80080f8: 687b ldr r3, [r7, #4] 80080fa: 685a ldr r2, [r3, #4] 80080fc: 687b ldr r3, [r7, #4] 80080fe: 6e1b ldr r3, [r3, #96] @ 0x60 8008100: b2d2 uxtb r2, r2 8008102: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8008104: 687b ldr r3, [r7, #4] 8008106: 6e5b ldr r3, [r3, #100] @ 0x64 8008108: 687a ldr r2, [r7, #4] 800810a: 6e92 ldr r2, [r2, #104] @ 0x68 800810c: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 800810e: 687b ldr r3, [r7, #4] 8008110: 685b ldr r3, [r3, #4] 8008112: 2b00 cmp r3, #0 8008114: d010 beq.n 8008138 8008116: 687b ldr r3, [r7, #4] 8008118: 685b ldr r3, [r3, #4] 800811a: 2b08 cmp r3, #8 800811c: d80c bhi.n 8008138 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 800811e: 6878 ldr r0, [r7, #4] 8008120: f002 fac0 bl 800a6a4 /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8008124: 687b ldr r3, [r7, #4] 8008126: 6edb ldr r3, [r3, #108] @ 0x6c 8008128: 2200 movs r2, #0 800812a: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800812c: 687b ldr r3, [r7, #4] 800812e: 6f1b ldr r3, [r3, #112] @ 0x70 8008130: 687a ldr r2, [r7, #4] 8008132: 6f52 ldr r2, [r2, #116] @ 0x74 8008134: 605a str r2, [r3, #4] 8008136: e008 b.n 800814a } else { hdma->DMAmuxRequestGen = 0U; 8008138: 687b ldr r3, [r7, #4] 800813a: 2200 movs r2, #0 800813c: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 800813e: 687b ldr r3, [r7, #4] 8008140: 2200 movs r2, #0 8008142: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8008144: 687b ldr r3, [r7, #4] 8008146: 2200 movs r2, #0 8008148: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 800814a: 687b ldr r3, [r7, #4] 800814c: 2200 movs r2, #0 800814e: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008150: 687b ldr r3, [r7, #4] 8008152: 2201 movs r2, #1 8008154: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8008158: 2300 movs r3, #0 } 800815a: 4618 mov r0, r3 800815c: 3718 adds r7, #24 800815e: 46bd mov sp, r7 8008160: bd80 pop {r7, pc} 8008162: bf00 nop 8008164: a7fdabf8 .word 0xa7fdabf8 8008168: cccccccd .word 0xcccccccd 800816c: 40020010 .word 0x40020010 8008170: 40020028 .word 0x40020028 8008174: 40020040 .word 0x40020040 8008178: 40020058 .word 0x40020058 800817c: 40020070 .word 0x40020070 8008180: 40020088 .word 0x40020088 8008184: 400200a0 .word 0x400200a0 8008188: 400200b8 .word 0x400200b8 800818c: 40020410 .word 0x40020410 8008190: 40020428 .word 0x40020428 8008194: 40020440 .word 0x40020440 8008198: 40020458 .word 0x40020458 800819c: 40020470 .word 0x40020470 80081a0: 40020488 .word 0x40020488 80081a4: 400204a0 .word 0x400204a0 80081a8: 400204b8 .word 0x400204b8 80081ac: 58025408 .word 0x58025408 80081b0: 5802541c .word 0x5802541c 80081b4: 58025430 .word 0x58025430 80081b8: 58025444 .word 0x58025444 80081bc: 58025458 .word 0x58025458 80081c0: 5802546c .word 0x5802546c 80081c4: 58025480 .word 0x58025480 80081c8: 58025494 .word 0x58025494 080081cc : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80081cc: b580 push {r7, lr} 80081ce: b086 sub sp, #24 80081d0: af00 add r7, sp, #0 80081d2: 60f8 str r0, [r7, #12] 80081d4: 60b9 str r1, [r7, #8] 80081d6: 607a str r2, [r7, #4] 80081d8: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 80081da: 2300 movs r3, #0 80081dc: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Check the DMA peripheral handle */ if(hdma == NULL) 80081de: 68fb ldr r3, [r7, #12] 80081e0: 2b00 cmp r3, #0 80081e2: d101 bne.n 80081e8 { return HAL_ERROR; 80081e4: 2301 movs r3, #1 80081e6: e226 b.n 8008636 } /* Process locked */ __HAL_LOCK(hdma); 80081e8: 68fb ldr r3, [r7, #12] 80081ea: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 80081ee: 2b01 cmp r3, #1 80081f0: d101 bne.n 80081f6 80081f2: 2302 movs r3, #2 80081f4: e21f b.n 8008636 80081f6: 68fb ldr r3, [r7, #12] 80081f8: 2201 movs r2, #1 80081fa: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 80081fe: 68fb ldr r3, [r7, #12] 8008200: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008204: b2db uxtb r3, r3 8008206: 2b01 cmp r3, #1 8008208: f040 820a bne.w 8008620 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 800820c: 68fb ldr r3, [r7, #12] 800820e: 2202 movs r2, #2 8008210: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008214: 68fb ldr r3, [r7, #12] 8008216: 2200 movs r2, #0 8008218: 655a str r2, [r3, #84] @ 0x54 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 800821a: 68fb ldr r3, [r7, #12] 800821c: 681b ldr r3, [r3, #0] 800821e: 4a68 ldr r2, [pc, #416] @ (80083c0 ) 8008220: 4293 cmp r3, r2 8008222: d04a beq.n 80082ba 8008224: 68fb ldr r3, [r7, #12] 8008226: 681b ldr r3, [r3, #0] 8008228: 4a66 ldr r2, [pc, #408] @ (80083c4 ) 800822a: 4293 cmp r3, r2 800822c: d045 beq.n 80082ba 800822e: 68fb ldr r3, [r7, #12] 8008230: 681b ldr r3, [r3, #0] 8008232: 4a65 ldr r2, [pc, #404] @ (80083c8 ) 8008234: 4293 cmp r3, r2 8008236: d040 beq.n 80082ba 8008238: 68fb ldr r3, [r7, #12] 800823a: 681b ldr r3, [r3, #0] 800823c: 4a63 ldr r2, [pc, #396] @ (80083cc ) 800823e: 4293 cmp r3, r2 8008240: d03b beq.n 80082ba 8008242: 68fb ldr r3, [r7, #12] 8008244: 681b ldr r3, [r3, #0] 8008246: 4a62 ldr r2, [pc, #392] @ (80083d0 ) 8008248: 4293 cmp r3, r2 800824a: d036 beq.n 80082ba 800824c: 68fb ldr r3, [r7, #12] 800824e: 681b ldr r3, [r3, #0] 8008250: 4a60 ldr r2, [pc, #384] @ (80083d4 ) 8008252: 4293 cmp r3, r2 8008254: d031 beq.n 80082ba 8008256: 68fb ldr r3, [r7, #12] 8008258: 681b ldr r3, [r3, #0] 800825a: 4a5f ldr r2, [pc, #380] @ (80083d8 ) 800825c: 4293 cmp r3, r2 800825e: d02c beq.n 80082ba 8008260: 68fb ldr r3, [r7, #12] 8008262: 681b ldr r3, [r3, #0] 8008264: 4a5d ldr r2, [pc, #372] @ (80083dc ) 8008266: 4293 cmp r3, r2 8008268: d027 beq.n 80082ba 800826a: 68fb ldr r3, [r7, #12] 800826c: 681b ldr r3, [r3, #0] 800826e: 4a5c ldr r2, [pc, #368] @ (80083e0 ) 8008270: 4293 cmp r3, r2 8008272: d022 beq.n 80082ba 8008274: 68fb ldr r3, [r7, #12] 8008276: 681b ldr r3, [r3, #0] 8008278: 4a5a ldr r2, [pc, #360] @ (80083e4 ) 800827a: 4293 cmp r3, r2 800827c: d01d beq.n 80082ba 800827e: 68fb ldr r3, [r7, #12] 8008280: 681b ldr r3, [r3, #0] 8008282: 4a59 ldr r2, [pc, #356] @ (80083e8 ) 8008284: 4293 cmp r3, r2 8008286: d018 beq.n 80082ba 8008288: 68fb ldr r3, [r7, #12] 800828a: 681b ldr r3, [r3, #0] 800828c: 4a57 ldr r2, [pc, #348] @ (80083ec ) 800828e: 4293 cmp r3, r2 8008290: d013 beq.n 80082ba 8008292: 68fb ldr r3, [r7, #12] 8008294: 681b ldr r3, [r3, #0] 8008296: 4a56 ldr r2, [pc, #344] @ (80083f0 ) 8008298: 4293 cmp r3, r2 800829a: d00e beq.n 80082ba 800829c: 68fb ldr r3, [r7, #12] 800829e: 681b ldr r3, [r3, #0] 80082a0: 4a54 ldr r2, [pc, #336] @ (80083f4 ) 80082a2: 4293 cmp r3, r2 80082a4: d009 beq.n 80082ba 80082a6: 68fb ldr r3, [r7, #12] 80082a8: 681b ldr r3, [r3, #0] 80082aa: 4a53 ldr r2, [pc, #332] @ (80083f8 ) 80082ac: 4293 cmp r3, r2 80082ae: d004 beq.n 80082ba 80082b0: 68fb ldr r3, [r7, #12] 80082b2: 681b ldr r3, [r3, #0] 80082b4: 4a51 ldr r2, [pc, #324] @ (80083fc ) 80082b6: 4293 cmp r3, r2 80082b8: d108 bne.n 80082cc 80082ba: 68fb ldr r3, [r7, #12] 80082bc: 681b ldr r3, [r3, #0] 80082be: 681a ldr r2, [r3, #0] 80082c0: 68fb ldr r3, [r7, #12] 80082c2: 681b ldr r3, [r3, #0] 80082c4: f022 0201 bic.w r2, r2, #1 80082c8: 601a str r2, [r3, #0] 80082ca: e007 b.n 80082dc 80082cc: 68fb ldr r3, [r7, #12] 80082ce: 681b ldr r3, [r3, #0] 80082d0: 681a ldr r2, [r3, #0] 80082d2: 68fb ldr r3, [r7, #12] 80082d4: 681b ldr r3, [r3, #0] 80082d6: f022 0201 bic.w r2, r2, #1 80082da: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 80082dc: 683b ldr r3, [r7, #0] 80082de: 687a ldr r2, [r7, #4] 80082e0: 68b9 ldr r1, [r7, #8] 80082e2: 68f8 ldr r0, [r7, #12] 80082e4: f001 fe6a bl 8009fbc if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80082e8: 68fb ldr r3, [r7, #12] 80082ea: 681b ldr r3, [r3, #0] 80082ec: 4a34 ldr r2, [pc, #208] @ (80083c0 ) 80082ee: 4293 cmp r3, r2 80082f0: d04a beq.n 8008388 80082f2: 68fb ldr r3, [r7, #12] 80082f4: 681b ldr r3, [r3, #0] 80082f6: 4a33 ldr r2, [pc, #204] @ (80083c4 ) 80082f8: 4293 cmp r3, r2 80082fa: d045 beq.n 8008388 80082fc: 68fb ldr r3, [r7, #12] 80082fe: 681b ldr r3, [r3, #0] 8008300: 4a31 ldr r2, [pc, #196] @ (80083c8 ) 8008302: 4293 cmp r3, r2 8008304: d040 beq.n 8008388 8008306: 68fb ldr r3, [r7, #12] 8008308: 681b ldr r3, [r3, #0] 800830a: 4a30 ldr r2, [pc, #192] @ (80083cc ) 800830c: 4293 cmp r3, r2 800830e: d03b beq.n 8008388 8008310: 68fb ldr r3, [r7, #12] 8008312: 681b ldr r3, [r3, #0] 8008314: 4a2e ldr r2, [pc, #184] @ (80083d0 ) 8008316: 4293 cmp r3, r2 8008318: d036 beq.n 8008388 800831a: 68fb ldr r3, [r7, #12] 800831c: 681b ldr r3, [r3, #0] 800831e: 4a2d ldr r2, [pc, #180] @ (80083d4 ) 8008320: 4293 cmp r3, r2 8008322: d031 beq.n 8008388 8008324: 68fb ldr r3, [r7, #12] 8008326: 681b ldr r3, [r3, #0] 8008328: 4a2b ldr r2, [pc, #172] @ (80083d8 ) 800832a: 4293 cmp r3, r2 800832c: d02c beq.n 8008388 800832e: 68fb ldr r3, [r7, #12] 8008330: 681b ldr r3, [r3, #0] 8008332: 4a2a ldr r2, [pc, #168] @ (80083dc ) 8008334: 4293 cmp r3, r2 8008336: d027 beq.n 8008388 8008338: 68fb ldr r3, [r7, #12] 800833a: 681b ldr r3, [r3, #0] 800833c: 4a28 ldr r2, [pc, #160] @ (80083e0 ) 800833e: 4293 cmp r3, r2 8008340: d022 beq.n 8008388 8008342: 68fb ldr r3, [r7, #12] 8008344: 681b ldr r3, [r3, #0] 8008346: 4a27 ldr r2, [pc, #156] @ (80083e4 ) 8008348: 4293 cmp r3, r2 800834a: d01d beq.n 8008388 800834c: 68fb ldr r3, [r7, #12] 800834e: 681b ldr r3, [r3, #0] 8008350: 4a25 ldr r2, [pc, #148] @ (80083e8 ) 8008352: 4293 cmp r3, r2 8008354: d018 beq.n 8008388 8008356: 68fb ldr r3, [r7, #12] 8008358: 681b ldr r3, [r3, #0] 800835a: 4a24 ldr r2, [pc, #144] @ (80083ec ) 800835c: 4293 cmp r3, r2 800835e: d013 beq.n 8008388 8008360: 68fb ldr r3, [r7, #12] 8008362: 681b ldr r3, [r3, #0] 8008364: 4a22 ldr r2, [pc, #136] @ (80083f0 ) 8008366: 4293 cmp r3, r2 8008368: d00e beq.n 8008388 800836a: 68fb ldr r3, [r7, #12] 800836c: 681b ldr r3, [r3, #0] 800836e: 4a21 ldr r2, [pc, #132] @ (80083f4 ) 8008370: 4293 cmp r3, r2 8008372: d009 beq.n 8008388 8008374: 68fb ldr r3, [r7, #12] 8008376: 681b ldr r3, [r3, #0] 8008378: 4a1f ldr r2, [pc, #124] @ (80083f8 ) 800837a: 4293 cmp r3, r2 800837c: d004 beq.n 8008388 800837e: 68fb ldr r3, [r7, #12] 8008380: 681b ldr r3, [r3, #0] 8008382: 4a1e ldr r2, [pc, #120] @ (80083fc ) 8008384: 4293 cmp r3, r2 8008386: d101 bne.n 800838c 8008388: 2301 movs r3, #1 800838a: e000 b.n 800838e 800838c: 2300 movs r3, #0 800838e: 2b00 cmp r3, #0 8008390: d036 beq.n 8008400 { /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8008392: 68fb ldr r3, [r7, #12] 8008394: 681b ldr r3, [r3, #0] 8008396: 681b ldr r3, [r3, #0] 8008398: f023 021e bic.w r2, r3, #30 800839c: 68fb ldr r3, [r7, #12] 800839e: 681b ldr r3, [r3, #0] 80083a0: f042 0216 orr.w r2, r2, #22 80083a4: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 80083a6: 68fb ldr r3, [r7, #12] 80083a8: 6c1b ldr r3, [r3, #64] @ 0x40 80083aa: 2b00 cmp r3, #0 80083ac: d03e beq.n 800842c { /* Enable Half Transfer IT if corresponding Callback is set */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 80083ae: 68fb ldr r3, [r7, #12] 80083b0: 681b ldr r3, [r3, #0] 80083b2: 681a ldr r2, [r3, #0] 80083b4: 68fb ldr r3, [r7, #12] 80083b6: 681b ldr r3, [r3, #0] 80083b8: f042 0208 orr.w r2, r2, #8 80083bc: 601a str r2, [r3, #0] 80083be: e035 b.n 800842c 80083c0: 40020010 .word 0x40020010 80083c4: 40020028 .word 0x40020028 80083c8: 40020040 .word 0x40020040 80083cc: 40020058 .word 0x40020058 80083d0: 40020070 .word 0x40020070 80083d4: 40020088 .word 0x40020088 80083d8: 400200a0 .word 0x400200a0 80083dc: 400200b8 .word 0x400200b8 80083e0: 40020410 .word 0x40020410 80083e4: 40020428 .word 0x40020428 80083e8: 40020440 .word 0x40020440 80083ec: 40020458 .word 0x40020458 80083f0: 40020470 .word 0x40020470 80083f4: 40020488 .word 0x40020488 80083f8: 400204a0 .word 0x400204a0 80083fc: 400204b8 .word 0x400204b8 } } else /* BDMA channel */ { /* Enable Common interrupts */ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8008400: 68fb ldr r3, [r7, #12] 8008402: 681b ldr r3, [r3, #0] 8008404: 681b ldr r3, [r3, #0] 8008406: f023 020e bic.w r2, r3, #14 800840a: 68fb ldr r3, [r7, #12] 800840c: 681b ldr r3, [r3, #0] 800840e: f042 020a orr.w r2, r2, #10 8008412: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008414: 68fb ldr r3, [r7, #12] 8008416: 6c1b ldr r3, [r3, #64] @ 0x40 8008418: 2b00 cmp r3, #0 800841a: d007 beq.n 800842c { /*Enable Half Transfer IT if corresponding Callback is set */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 800841c: 68fb ldr r3, [r7, #12] 800841e: 681b ldr r3, [r3, #0] 8008420: 681a ldr r2, [r3, #0] 8008422: 68fb ldr r3, [r7, #12] 8008424: 681b ldr r3, [r3, #0] 8008426: f042 0204 orr.w r2, r2, #4 800842a: 601a str r2, [r3, #0] } } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800842c: 68fb ldr r3, [r7, #12] 800842e: 681b ldr r3, [r3, #0] 8008430: 4a83 ldr r2, [pc, #524] @ (8008640 ) 8008432: 4293 cmp r3, r2 8008434: d072 beq.n 800851c 8008436: 68fb ldr r3, [r7, #12] 8008438: 681b ldr r3, [r3, #0] 800843a: 4a82 ldr r2, [pc, #520] @ (8008644 ) 800843c: 4293 cmp r3, r2 800843e: d06d beq.n 800851c 8008440: 68fb ldr r3, [r7, #12] 8008442: 681b ldr r3, [r3, #0] 8008444: 4a80 ldr r2, [pc, #512] @ (8008648 ) 8008446: 4293 cmp r3, r2 8008448: d068 beq.n 800851c 800844a: 68fb ldr r3, [r7, #12] 800844c: 681b ldr r3, [r3, #0] 800844e: 4a7f ldr r2, [pc, #508] @ (800864c ) 8008450: 4293 cmp r3, r2 8008452: d063 beq.n 800851c 8008454: 68fb ldr r3, [r7, #12] 8008456: 681b ldr r3, [r3, #0] 8008458: 4a7d ldr r2, [pc, #500] @ (8008650 ) 800845a: 4293 cmp r3, r2 800845c: d05e beq.n 800851c 800845e: 68fb ldr r3, [r7, #12] 8008460: 681b ldr r3, [r3, #0] 8008462: 4a7c ldr r2, [pc, #496] @ (8008654 ) 8008464: 4293 cmp r3, r2 8008466: d059 beq.n 800851c 8008468: 68fb ldr r3, [r7, #12] 800846a: 681b ldr r3, [r3, #0] 800846c: 4a7a ldr r2, [pc, #488] @ (8008658 ) 800846e: 4293 cmp r3, r2 8008470: d054 beq.n 800851c 8008472: 68fb ldr r3, [r7, #12] 8008474: 681b ldr r3, [r3, #0] 8008476: 4a79 ldr r2, [pc, #484] @ (800865c ) 8008478: 4293 cmp r3, r2 800847a: d04f beq.n 800851c 800847c: 68fb ldr r3, [r7, #12] 800847e: 681b ldr r3, [r3, #0] 8008480: 4a77 ldr r2, [pc, #476] @ (8008660 ) 8008482: 4293 cmp r3, r2 8008484: d04a beq.n 800851c 8008486: 68fb ldr r3, [r7, #12] 8008488: 681b ldr r3, [r3, #0] 800848a: 4a76 ldr r2, [pc, #472] @ (8008664 ) 800848c: 4293 cmp r3, r2 800848e: d045 beq.n 800851c 8008490: 68fb ldr r3, [r7, #12] 8008492: 681b ldr r3, [r3, #0] 8008494: 4a74 ldr r2, [pc, #464] @ (8008668 ) 8008496: 4293 cmp r3, r2 8008498: d040 beq.n 800851c 800849a: 68fb ldr r3, [r7, #12] 800849c: 681b ldr r3, [r3, #0] 800849e: 4a73 ldr r2, [pc, #460] @ (800866c ) 80084a0: 4293 cmp r3, r2 80084a2: d03b beq.n 800851c 80084a4: 68fb ldr r3, [r7, #12] 80084a6: 681b ldr r3, [r3, #0] 80084a8: 4a71 ldr r2, [pc, #452] @ (8008670 ) 80084aa: 4293 cmp r3, r2 80084ac: d036 beq.n 800851c 80084ae: 68fb ldr r3, [r7, #12] 80084b0: 681b ldr r3, [r3, #0] 80084b2: 4a70 ldr r2, [pc, #448] @ (8008674 ) 80084b4: 4293 cmp r3, r2 80084b6: d031 beq.n 800851c 80084b8: 68fb ldr r3, [r7, #12] 80084ba: 681b ldr r3, [r3, #0] 80084bc: 4a6e ldr r2, [pc, #440] @ (8008678 ) 80084be: 4293 cmp r3, r2 80084c0: d02c beq.n 800851c 80084c2: 68fb ldr r3, [r7, #12] 80084c4: 681b ldr r3, [r3, #0] 80084c6: 4a6d ldr r2, [pc, #436] @ (800867c ) 80084c8: 4293 cmp r3, r2 80084ca: d027 beq.n 800851c 80084cc: 68fb ldr r3, [r7, #12] 80084ce: 681b ldr r3, [r3, #0] 80084d0: 4a6b ldr r2, [pc, #428] @ (8008680 ) 80084d2: 4293 cmp r3, r2 80084d4: d022 beq.n 800851c 80084d6: 68fb ldr r3, [r7, #12] 80084d8: 681b ldr r3, [r3, #0] 80084da: 4a6a ldr r2, [pc, #424] @ (8008684 ) 80084dc: 4293 cmp r3, r2 80084de: d01d beq.n 800851c 80084e0: 68fb ldr r3, [r7, #12] 80084e2: 681b ldr r3, [r3, #0] 80084e4: 4a68 ldr r2, [pc, #416] @ (8008688 ) 80084e6: 4293 cmp r3, r2 80084e8: d018 beq.n 800851c 80084ea: 68fb ldr r3, [r7, #12] 80084ec: 681b ldr r3, [r3, #0] 80084ee: 4a67 ldr r2, [pc, #412] @ (800868c ) 80084f0: 4293 cmp r3, r2 80084f2: d013 beq.n 800851c 80084f4: 68fb ldr r3, [r7, #12] 80084f6: 681b ldr r3, [r3, #0] 80084f8: 4a65 ldr r2, [pc, #404] @ (8008690 ) 80084fa: 4293 cmp r3, r2 80084fc: d00e beq.n 800851c 80084fe: 68fb ldr r3, [r7, #12] 8008500: 681b ldr r3, [r3, #0] 8008502: 4a64 ldr r2, [pc, #400] @ (8008694 ) 8008504: 4293 cmp r3, r2 8008506: d009 beq.n 800851c 8008508: 68fb ldr r3, [r7, #12] 800850a: 681b ldr r3, [r3, #0] 800850c: 4a62 ldr r2, [pc, #392] @ (8008698 ) 800850e: 4293 cmp r3, r2 8008510: d004 beq.n 800851c 8008512: 68fb ldr r3, [r7, #12] 8008514: 681b ldr r3, [r3, #0] 8008516: 4a61 ldr r2, [pc, #388] @ (800869c ) 8008518: 4293 cmp r3, r2 800851a: d101 bne.n 8008520 800851c: 2301 movs r3, #1 800851e: e000 b.n 8008522 8008520: 2300 movs r3, #0 8008522: 2b00 cmp r3, #0 8008524: d01a beq.n 800855c { /* Check if DMAMUX Synchronization is enabled */ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8008526: 68fb ldr r3, [r7, #12] 8008528: 6e1b ldr r3, [r3, #96] @ 0x60 800852a: 681b ldr r3, [r3, #0] 800852c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008530: 2b00 cmp r3, #0 8008532: d007 beq.n 8008544 { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8008534: 68fb ldr r3, [r7, #12] 8008536: 6e1b ldr r3, [r3, #96] @ 0x60 8008538: 681a ldr r2, [r3, #0] 800853a: 68fb ldr r3, [r7, #12] 800853c: 6e1b ldr r3, [r3, #96] @ 0x60 800853e: f442 7280 orr.w r2, r2, #256 @ 0x100 8008542: 601a str r2, [r3, #0] } if(hdma->DMAmuxRequestGen != 0U) 8008544: 68fb ldr r3, [r7, #12] 8008546: 6edb ldr r3, [r3, #108] @ 0x6c 8008548: 2b00 cmp r3, #0 800854a: d007 beq.n 800855c { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 800854c: 68fb ldr r3, [r7, #12] 800854e: 6edb ldr r3, [r3, #108] @ 0x6c 8008550: 681a ldr r2, [r3, #0] 8008552: 68fb ldr r3, [r7, #12] 8008554: 6edb ldr r3, [r3, #108] @ 0x6c 8008556: f442 7280 orr.w r2, r2, #256 @ 0x100 800855a: 601a str r2, [r3, #0] } } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 800855c: 68fb ldr r3, [r7, #12] 800855e: 681b ldr r3, [r3, #0] 8008560: 4a37 ldr r2, [pc, #220] @ (8008640 ) 8008562: 4293 cmp r3, r2 8008564: d04a beq.n 80085fc 8008566: 68fb ldr r3, [r7, #12] 8008568: 681b ldr r3, [r3, #0] 800856a: 4a36 ldr r2, [pc, #216] @ (8008644 ) 800856c: 4293 cmp r3, r2 800856e: d045 beq.n 80085fc 8008570: 68fb ldr r3, [r7, #12] 8008572: 681b ldr r3, [r3, #0] 8008574: 4a34 ldr r2, [pc, #208] @ (8008648 ) 8008576: 4293 cmp r3, r2 8008578: d040 beq.n 80085fc 800857a: 68fb ldr r3, [r7, #12] 800857c: 681b ldr r3, [r3, #0] 800857e: 4a33 ldr r2, [pc, #204] @ (800864c ) 8008580: 4293 cmp r3, r2 8008582: d03b beq.n 80085fc 8008584: 68fb ldr r3, [r7, #12] 8008586: 681b ldr r3, [r3, #0] 8008588: 4a31 ldr r2, [pc, #196] @ (8008650 ) 800858a: 4293 cmp r3, r2 800858c: d036 beq.n 80085fc 800858e: 68fb ldr r3, [r7, #12] 8008590: 681b ldr r3, [r3, #0] 8008592: 4a30 ldr r2, [pc, #192] @ (8008654 ) 8008594: 4293 cmp r3, r2 8008596: d031 beq.n 80085fc 8008598: 68fb ldr r3, [r7, #12] 800859a: 681b ldr r3, [r3, #0] 800859c: 4a2e ldr r2, [pc, #184] @ (8008658 ) 800859e: 4293 cmp r3, r2 80085a0: d02c beq.n 80085fc 80085a2: 68fb ldr r3, [r7, #12] 80085a4: 681b ldr r3, [r3, #0] 80085a6: 4a2d ldr r2, [pc, #180] @ (800865c ) 80085a8: 4293 cmp r3, r2 80085aa: d027 beq.n 80085fc 80085ac: 68fb ldr r3, [r7, #12] 80085ae: 681b ldr r3, [r3, #0] 80085b0: 4a2b ldr r2, [pc, #172] @ (8008660 ) 80085b2: 4293 cmp r3, r2 80085b4: d022 beq.n 80085fc 80085b6: 68fb ldr r3, [r7, #12] 80085b8: 681b ldr r3, [r3, #0] 80085ba: 4a2a ldr r2, [pc, #168] @ (8008664 ) 80085bc: 4293 cmp r3, r2 80085be: d01d beq.n 80085fc 80085c0: 68fb ldr r3, [r7, #12] 80085c2: 681b ldr r3, [r3, #0] 80085c4: 4a28 ldr r2, [pc, #160] @ (8008668 ) 80085c6: 4293 cmp r3, r2 80085c8: d018 beq.n 80085fc 80085ca: 68fb ldr r3, [r7, #12] 80085cc: 681b ldr r3, [r3, #0] 80085ce: 4a27 ldr r2, [pc, #156] @ (800866c ) 80085d0: 4293 cmp r3, r2 80085d2: d013 beq.n 80085fc 80085d4: 68fb ldr r3, [r7, #12] 80085d6: 681b ldr r3, [r3, #0] 80085d8: 4a25 ldr r2, [pc, #148] @ (8008670 ) 80085da: 4293 cmp r3, r2 80085dc: d00e beq.n 80085fc 80085de: 68fb ldr r3, [r7, #12] 80085e0: 681b ldr r3, [r3, #0] 80085e2: 4a24 ldr r2, [pc, #144] @ (8008674 ) 80085e4: 4293 cmp r3, r2 80085e6: d009 beq.n 80085fc 80085e8: 68fb ldr r3, [r7, #12] 80085ea: 681b ldr r3, [r3, #0] 80085ec: 4a22 ldr r2, [pc, #136] @ (8008678 ) 80085ee: 4293 cmp r3, r2 80085f0: d004 beq.n 80085fc 80085f2: 68fb ldr r3, [r7, #12] 80085f4: 681b ldr r3, [r3, #0] 80085f6: 4a21 ldr r2, [pc, #132] @ (800867c ) 80085f8: 4293 cmp r3, r2 80085fa: d108 bne.n 800860e 80085fc: 68fb ldr r3, [r7, #12] 80085fe: 681b ldr r3, [r3, #0] 8008600: 681a ldr r2, [r3, #0] 8008602: 68fb ldr r3, [r7, #12] 8008604: 681b ldr r3, [r3, #0] 8008606: f042 0201 orr.w r2, r2, #1 800860a: 601a str r2, [r3, #0] 800860c: e012 b.n 8008634 800860e: 68fb ldr r3, [r7, #12] 8008610: 681b ldr r3, [r3, #0] 8008612: 681a ldr r2, [r3, #0] 8008614: 68fb ldr r3, [r7, #12] 8008616: 681b ldr r3, [r3, #0] 8008618: f042 0201 orr.w r2, r2, #1 800861c: 601a str r2, [r3, #0] 800861e: e009 b.n 8008634 } else { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8008620: 68fb ldr r3, [r7, #12] 8008622: f44f 6200 mov.w r2, #2048 @ 0x800 8008626: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hdma); 8008628: 68fb ldr r3, [r7, #12] 800862a: 2200 movs r2, #0 800862c: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_ERROR; 8008630: 2301 movs r3, #1 8008632: 75fb strb r3, [r7, #23] } return status; 8008634: 7dfb ldrb r3, [r7, #23] } 8008636: 4618 mov r0, r3 8008638: 3718 adds r7, #24 800863a: 46bd mov sp, r7 800863c: bd80 pop {r7, pc} 800863e: bf00 nop 8008640: 40020010 .word 0x40020010 8008644: 40020028 .word 0x40020028 8008648: 40020040 .word 0x40020040 800864c: 40020058 .word 0x40020058 8008650: 40020070 .word 0x40020070 8008654: 40020088 .word 0x40020088 8008658: 400200a0 .word 0x400200a0 800865c: 400200b8 .word 0x400200b8 8008660: 40020410 .word 0x40020410 8008664: 40020428 .word 0x40020428 8008668: 40020440 .word 0x40020440 800866c: 40020458 .word 0x40020458 8008670: 40020470 .word 0x40020470 8008674: 40020488 .word 0x40020488 8008678: 400204a0 .word 0x400204a0 800867c: 400204b8 .word 0x400204b8 8008680: 58025408 .word 0x58025408 8008684: 5802541c .word 0x5802541c 8008688: 58025430 .word 0x58025430 800868c: 58025444 .word 0x58025444 8008690: 58025458 .word 0x58025458 8008694: 5802546c .word 0x5802546c 8008698: 58025480 .word 0x58025480 800869c: 58025494 .word 0x58025494 080086a0 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80086a0: b580 push {r7, lr} 80086a2: b086 sub sp, #24 80086a4: af00 add r7, sp, #0 80086a6: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 80086a8: f7fc fe98 bl 80053dc 80086ac: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 80086ae: 687b ldr r3, [r7, #4] 80086b0: 2b00 cmp r3, #0 80086b2: d101 bne.n 80086b8 { return HAL_ERROR; 80086b4: 2301 movs r3, #1 80086b6: e2dc b.n 8008c72 } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 80086b8: 687b ldr r3, [r7, #4] 80086ba: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80086be: b2db uxtb r3, r3 80086c0: 2b02 cmp r3, #2 80086c2: d008 beq.n 80086d6 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 80086c4: 687b ldr r3, [r7, #4] 80086c6: 2280 movs r2, #128 @ 0x80 80086c8: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80086ca: 687b ldr r3, [r7, #4] 80086cc: 2200 movs r2, #0 80086ce: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 80086d2: 2301 movs r3, #1 80086d4: e2cd b.n 8008c72 } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 80086d6: 687b ldr r3, [r7, #4] 80086d8: 681b ldr r3, [r3, #0] 80086da: 4a76 ldr r2, [pc, #472] @ (80088b4 ) 80086dc: 4293 cmp r3, r2 80086de: d04a beq.n 8008776 80086e0: 687b ldr r3, [r7, #4] 80086e2: 681b ldr r3, [r3, #0] 80086e4: 4a74 ldr r2, [pc, #464] @ (80088b8 ) 80086e6: 4293 cmp r3, r2 80086e8: d045 beq.n 8008776 80086ea: 687b ldr r3, [r7, #4] 80086ec: 681b ldr r3, [r3, #0] 80086ee: 4a73 ldr r2, [pc, #460] @ (80088bc ) 80086f0: 4293 cmp r3, r2 80086f2: d040 beq.n 8008776 80086f4: 687b ldr r3, [r7, #4] 80086f6: 681b ldr r3, [r3, #0] 80086f8: 4a71 ldr r2, [pc, #452] @ (80088c0 ) 80086fa: 4293 cmp r3, r2 80086fc: d03b beq.n 8008776 80086fe: 687b ldr r3, [r7, #4] 8008700: 681b ldr r3, [r3, #0] 8008702: 4a70 ldr r2, [pc, #448] @ (80088c4 ) 8008704: 4293 cmp r3, r2 8008706: d036 beq.n 8008776 8008708: 687b ldr r3, [r7, #4] 800870a: 681b ldr r3, [r3, #0] 800870c: 4a6e ldr r2, [pc, #440] @ (80088c8 ) 800870e: 4293 cmp r3, r2 8008710: d031 beq.n 8008776 8008712: 687b ldr r3, [r7, #4] 8008714: 681b ldr r3, [r3, #0] 8008716: 4a6d ldr r2, [pc, #436] @ (80088cc ) 8008718: 4293 cmp r3, r2 800871a: d02c beq.n 8008776 800871c: 687b ldr r3, [r7, #4] 800871e: 681b ldr r3, [r3, #0] 8008720: 4a6b ldr r2, [pc, #428] @ (80088d0 ) 8008722: 4293 cmp r3, r2 8008724: d027 beq.n 8008776 8008726: 687b ldr r3, [r7, #4] 8008728: 681b ldr r3, [r3, #0] 800872a: 4a6a ldr r2, [pc, #424] @ (80088d4 ) 800872c: 4293 cmp r3, r2 800872e: d022 beq.n 8008776 8008730: 687b ldr r3, [r7, #4] 8008732: 681b ldr r3, [r3, #0] 8008734: 4a68 ldr r2, [pc, #416] @ (80088d8 ) 8008736: 4293 cmp r3, r2 8008738: d01d beq.n 8008776 800873a: 687b ldr r3, [r7, #4] 800873c: 681b ldr r3, [r3, #0] 800873e: 4a67 ldr r2, [pc, #412] @ (80088dc ) 8008740: 4293 cmp r3, r2 8008742: d018 beq.n 8008776 8008744: 687b ldr r3, [r7, #4] 8008746: 681b ldr r3, [r3, #0] 8008748: 4a65 ldr r2, [pc, #404] @ (80088e0 ) 800874a: 4293 cmp r3, r2 800874c: d013 beq.n 8008776 800874e: 687b ldr r3, [r7, #4] 8008750: 681b ldr r3, [r3, #0] 8008752: 4a64 ldr r2, [pc, #400] @ (80088e4 ) 8008754: 4293 cmp r3, r2 8008756: d00e beq.n 8008776 8008758: 687b ldr r3, [r7, #4] 800875a: 681b ldr r3, [r3, #0] 800875c: 4a62 ldr r2, [pc, #392] @ (80088e8 ) 800875e: 4293 cmp r3, r2 8008760: d009 beq.n 8008776 8008762: 687b ldr r3, [r7, #4] 8008764: 681b ldr r3, [r3, #0] 8008766: 4a61 ldr r2, [pc, #388] @ (80088ec ) 8008768: 4293 cmp r3, r2 800876a: d004 beq.n 8008776 800876c: 687b ldr r3, [r7, #4] 800876e: 681b ldr r3, [r3, #0] 8008770: 4a5f ldr r2, [pc, #380] @ (80088f0 ) 8008772: 4293 cmp r3, r2 8008774: d101 bne.n 800877a 8008776: 2301 movs r3, #1 8008778: e000 b.n 800877c 800877a: 2300 movs r3, #0 800877c: 2b00 cmp r3, #0 800877e: d013 beq.n 80087a8 { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 8008780: 687b ldr r3, [r7, #4] 8008782: 681b ldr r3, [r3, #0] 8008784: 681a ldr r2, [r3, #0] 8008786: 687b ldr r3, [r7, #4] 8008788: 681b ldr r3, [r3, #0] 800878a: f022 021e bic.w r2, r2, #30 800878e: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 8008790: 687b ldr r3, [r7, #4] 8008792: 681b ldr r3, [r3, #0] 8008794: 695a ldr r2, [r3, #20] 8008796: 687b ldr r3, [r7, #4] 8008798: 681b ldr r3, [r3, #0] 800879a: f022 0280 bic.w r2, r2, #128 @ 0x80 800879e: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 80087a0: 687b ldr r3, [r7, #4] 80087a2: 681b ldr r3, [r3, #0] 80087a4: 617b str r3, [r7, #20] 80087a6: e00a b.n 80087be } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80087a8: 687b ldr r3, [r7, #4] 80087aa: 681b ldr r3, [r3, #0] 80087ac: 681a ldr r2, [r3, #0] 80087ae: 687b ldr r3, [r7, #4] 80087b0: 681b ldr r3, [r3, #0] 80087b2: f022 020e bic.w r2, r2, #14 80087b6: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 80087b8: 687b ldr r3, [r7, #4] 80087ba: 681b ldr r3, [r3, #0] 80087bc: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80087be: 687b ldr r3, [r7, #4] 80087c0: 681b ldr r3, [r3, #0] 80087c2: 4a3c ldr r2, [pc, #240] @ (80088b4 ) 80087c4: 4293 cmp r3, r2 80087c6: d072 beq.n 80088ae 80087c8: 687b ldr r3, [r7, #4] 80087ca: 681b ldr r3, [r3, #0] 80087cc: 4a3a ldr r2, [pc, #232] @ (80088b8 ) 80087ce: 4293 cmp r3, r2 80087d0: d06d beq.n 80088ae 80087d2: 687b ldr r3, [r7, #4] 80087d4: 681b ldr r3, [r3, #0] 80087d6: 4a39 ldr r2, [pc, #228] @ (80088bc ) 80087d8: 4293 cmp r3, r2 80087da: d068 beq.n 80088ae 80087dc: 687b ldr r3, [r7, #4] 80087de: 681b ldr r3, [r3, #0] 80087e0: 4a37 ldr r2, [pc, #220] @ (80088c0 ) 80087e2: 4293 cmp r3, r2 80087e4: d063 beq.n 80088ae 80087e6: 687b ldr r3, [r7, #4] 80087e8: 681b ldr r3, [r3, #0] 80087ea: 4a36 ldr r2, [pc, #216] @ (80088c4 ) 80087ec: 4293 cmp r3, r2 80087ee: d05e beq.n 80088ae 80087f0: 687b ldr r3, [r7, #4] 80087f2: 681b ldr r3, [r3, #0] 80087f4: 4a34 ldr r2, [pc, #208] @ (80088c8 ) 80087f6: 4293 cmp r3, r2 80087f8: d059 beq.n 80088ae 80087fa: 687b ldr r3, [r7, #4] 80087fc: 681b ldr r3, [r3, #0] 80087fe: 4a33 ldr r2, [pc, #204] @ (80088cc ) 8008800: 4293 cmp r3, r2 8008802: d054 beq.n 80088ae 8008804: 687b ldr r3, [r7, #4] 8008806: 681b ldr r3, [r3, #0] 8008808: 4a31 ldr r2, [pc, #196] @ (80088d0 ) 800880a: 4293 cmp r3, r2 800880c: d04f beq.n 80088ae 800880e: 687b ldr r3, [r7, #4] 8008810: 681b ldr r3, [r3, #0] 8008812: 4a30 ldr r2, [pc, #192] @ (80088d4 ) 8008814: 4293 cmp r3, r2 8008816: d04a beq.n 80088ae 8008818: 687b ldr r3, [r7, #4] 800881a: 681b ldr r3, [r3, #0] 800881c: 4a2e ldr r2, [pc, #184] @ (80088d8 ) 800881e: 4293 cmp r3, r2 8008820: d045 beq.n 80088ae 8008822: 687b ldr r3, [r7, #4] 8008824: 681b ldr r3, [r3, #0] 8008826: 4a2d ldr r2, [pc, #180] @ (80088dc ) 8008828: 4293 cmp r3, r2 800882a: d040 beq.n 80088ae 800882c: 687b ldr r3, [r7, #4] 800882e: 681b ldr r3, [r3, #0] 8008830: 4a2b ldr r2, [pc, #172] @ (80088e0 ) 8008832: 4293 cmp r3, r2 8008834: d03b beq.n 80088ae 8008836: 687b ldr r3, [r7, #4] 8008838: 681b ldr r3, [r3, #0] 800883a: 4a2a ldr r2, [pc, #168] @ (80088e4 ) 800883c: 4293 cmp r3, r2 800883e: d036 beq.n 80088ae 8008840: 687b ldr r3, [r7, #4] 8008842: 681b ldr r3, [r3, #0] 8008844: 4a28 ldr r2, [pc, #160] @ (80088e8 ) 8008846: 4293 cmp r3, r2 8008848: d031 beq.n 80088ae 800884a: 687b ldr r3, [r7, #4] 800884c: 681b ldr r3, [r3, #0] 800884e: 4a27 ldr r2, [pc, #156] @ (80088ec ) 8008850: 4293 cmp r3, r2 8008852: d02c beq.n 80088ae 8008854: 687b ldr r3, [r7, #4] 8008856: 681b ldr r3, [r3, #0] 8008858: 4a25 ldr r2, [pc, #148] @ (80088f0 ) 800885a: 4293 cmp r3, r2 800885c: d027 beq.n 80088ae 800885e: 687b ldr r3, [r7, #4] 8008860: 681b ldr r3, [r3, #0] 8008862: 4a24 ldr r2, [pc, #144] @ (80088f4 ) 8008864: 4293 cmp r3, r2 8008866: d022 beq.n 80088ae 8008868: 687b ldr r3, [r7, #4] 800886a: 681b ldr r3, [r3, #0] 800886c: 4a22 ldr r2, [pc, #136] @ (80088f8 ) 800886e: 4293 cmp r3, r2 8008870: d01d beq.n 80088ae 8008872: 687b ldr r3, [r7, #4] 8008874: 681b ldr r3, [r3, #0] 8008876: 4a21 ldr r2, [pc, #132] @ (80088fc ) 8008878: 4293 cmp r3, r2 800887a: d018 beq.n 80088ae 800887c: 687b ldr r3, [r7, #4] 800887e: 681b ldr r3, [r3, #0] 8008880: 4a1f ldr r2, [pc, #124] @ (8008900 ) 8008882: 4293 cmp r3, r2 8008884: d013 beq.n 80088ae 8008886: 687b ldr r3, [r7, #4] 8008888: 681b ldr r3, [r3, #0] 800888a: 4a1e ldr r2, [pc, #120] @ (8008904 ) 800888c: 4293 cmp r3, r2 800888e: d00e beq.n 80088ae 8008890: 687b ldr r3, [r7, #4] 8008892: 681b ldr r3, [r3, #0] 8008894: 4a1c ldr r2, [pc, #112] @ (8008908 ) 8008896: 4293 cmp r3, r2 8008898: d009 beq.n 80088ae 800889a: 687b ldr r3, [r7, #4] 800889c: 681b ldr r3, [r3, #0] 800889e: 4a1b ldr r2, [pc, #108] @ (800890c ) 80088a0: 4293 cmp r3, r2 80088a2: d004 beq.n 80088ae 80088a4: 687b ldr r3, [r7, #4] 80088a6: 681b ldr r3, [r3, #0] 80088a8: 4a19 ldr r2, [pc, #100] @ (8008910 ) 80088aa: 4293 cmp r3, r2 80088ac: d132 bne.n 8008914 80088ae: 2301 movs r3, #1 80088b0: e031 b.n 8008916 80088b2: bf00 nop 80088b4: 40020010 .word 0x40020010 80088b8: 40020028 .word 0x40020028 80088bc: 40020040 .word 0x40020040 80088c0: 40020058 .word 0x40020058 80088c4: 40020070 .word 0x40020070 80088c8: 40020088 .word 0x40020088 80088cc: 400200a0 .word 0x400200a0 80088d0: 400200b8 .word 0x400200b8 80088d4: 40020410 .word 0x40020410 80088d8: 40020428 .word 0x40020428 80088dc: 40020440 .word 0x40020440 80088e0: 40020458 .word 0x40020458 80088e4: 40020470 .word 0x40020470 80088e8: 40020488 .word 0x40020488 80088ec: 400204a0 .word 0x400204a0 80088f0: 400204b8 .word 0x400204b8 80088f4: 58025408 .word 0x58025408 80088f8: 5802541c .word 0x5802541c 80088fc: 58025430 .word 0x58025430 8008900: 58025444 .word 0x58025444 8008904: 58025458 .word 0x58025458 8008908: 5802546c .word 0x5802546c 800890c: 58025480 .word 0x58025480 8008910: 58025494 .word 0x58025494 8008914: 2300 movs r3, #0 8008916: 2b00 cmp r3, #0 8008918: d007 beq.n 800892a { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800891a: 687b ldr r3, [r7, #4] 800891c: 6e1b ldr r3, [r3, #96] @ 0x60 800891e: 681a ldr r2, [r3, #0] 8008920: 687b ldr r3, [r7, #4] 8008922: 6e1b ldr r3, [r3, #96] @ 0x60 8008924: f422 7280 bic.w r2, r2, #256 @ 0x100 8008928: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800892a: 687b ldr r3, [r7, #4] 800892c: 681b ldr r3, [r3, #0] 800892e: 4a6d ldr r2, [pc, #436] @ (8008ae4 ) 8008930: 4293 cmp r3, r2 8008932: d04a beq.n 80089ca 8008934: 687b ldr r3, [r7, #4] 8008936: 681b ldr r3, [r3, #0] 8008938: 4a6b ldr r2, [pc, #428] @ (8008ae8 ) 800893a: 4293 cmp r3, r2 800893c: d045 beq.n 80089ca 800893e: 687b ldr r3, [r7, #4] 8008940: 681b ldr r3, [r3, #0] 8008942: 4a6a ldr r2, [pc, #424] @ (8008aec ) 8008944: 4293 cmp r3, r2 8008946: d040 beq.n 80089ca 8008948: 687b ldr r3, [r7, #4] 800894a: 681b ldr r3, [r3, #0] 800894c: 4a68 ldr r2, [pc, #416] @ (8008af0 ) 800894e: 4293 cmp r3, r2 8008950: d03b beq.n 80089ca 8008952: 687b ldr r3, [r7, #4] 8008954: 681b ldr r3, [r3, #0] 8008956: 4a67 ldr r2, [pc, #412] @ (8008af4 ) 8008958: 4293 cmp r3, r2 800895a: d036 beq.n 80089ca 800895c: 687b ldr r3, [r7, #4] 800895e: 681b ldr r3, [r3, #0] 8008960: 4a65 ldr r2, [pc, #404] @ (8008af8 ) 8008962: 4293 cmp r3, r2 8008964: d031 beq.n 80089ca 8008966: 687b ldr r3, [r7, #4] 8008968: 681b ldr r3, [r3, #0] 800896a: 4a64 ldr r2, [pc, #400] @ (8008afc ) 800896c: 4293 cmp r3, r2 800896e: d02c beq.n 80089ca 8008970: 687b ldr r3, [r7, #4] 8008972: 681b ldr r3, [r3, #0] 8008974: 4a62 ldr r2, [pc, #392] @ (8008b00 ) 8008976: 4293 cmp r3, r2 8008978: d027 beq.n 80089ca 800897a: 687b ldr r3, [r7, #4] 800897c: 681b ldr r3, [r3, #0] 800897e: 4a61 ldr r2, [pc, #388] @ (8008b04 ) 8008980: 4293 cmp r3, r2 8008982: d022 beq.n 80089ca 8008984: 687b ldr r3, [r7, #4] 8008986: 681b ldr r3, [r3, #0] 8008988: 4a5f ldr r2, [pc, #380] @ (8008b08 ) 800898a: 4293 cmp r3, r2 800898c: d01d beq.n 80089ca 800898e: 687b ldr r3, [r7, #4] 8008990: 681b ldr r3, [r3, #0] 8008992: 4a5e ldr r2, [pc, #376] @ (8008b0c ) 8008994: 4293 cmp r3, r2 8008996: d018 beq.n 80089ca 8008998: 687b ldr r3, [r7, #4] 800899a: 681b ldr r3, [r3, #0] 800899c: 4a5c ldr r2, [pc, #368] @ (8008b10 ) 800899e: 4293 cmp r3, r2 80089a0: d013 beq.n 80089ca 80089a2: 687b ldr r3, [r7, #4] 80089a4: 681b ldr r3, [r3, #0] 80089a6: 4a5b ldr r2, [pc, #364] @ (8008b14 ) 80089a8: 4293 cmp r3, r2 80089aa: d00e beq.n 80089ca 80089ac: 687b ldr r3, [r7, #4] 80089ae: 681b ldr r3, [r3, #0] 80089b0: 4a59 ldr r2, [pc, #356] @ (8008b18 ) 80089b2: 4293 cmp r3, r2 80089b4: d009 beq.n 80089ca 80089b6: 687b ldr r3, [r7, #4] 80089b8: 681b ldr r3, [r3, #0] 80089ba: 4a58 ldr r2, [pc, #352] @ (8008b1c ) 80089bc: 4293 cmp r3, r2 80089be: d004 beq.n 80089ca 80089c0: 687b ldr r3, [r7, #4] 80089c2: 681b ldr r3, [r3, #0] 80089c4: 4a56 ldr r2, [pc, #344] @ (8008b20 ) 80089c6: 4293 cmp r3, r2 80089c8: d108 bne.n 80089dc 80089ca: 687b ldr r3, [r7, #4] 80089cc: 681b ldr r3, [r3, #0] 80089ce: 681a ldr r2, [r3, #0] 80089d0: 687b ldr r3, [r7, #4] 80089d2: 681b ldr r3, [r3, #0] 80089d4: f022 0201 bic.w r2, r2, #1 80089d8: 601a str r2, [r3, #0] 80089da: e007 b.n 80089ec 80089dc: 687b ldr r3, [r7, #4] 80089de: 681b ldr r3, [r3, #0] 80089e0: 681a ldr r2, [r3, #0] 80089e2: 687b ldr r3, [r7, #4] 80089e4: 681b ldr r3, [r3, #0] 80089e6: f022 0201 bic.w r2, r2, #1 80089ea: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 80089ec: e013 b.n 8008a16 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80089ee: f7fc fcf5 bl 80053dc 80089f2: 4602 mov r2, r0 80089f4: 693b ldr r3, [r7, #16] 80089f6: 1ad3 subs r3, r2, r3 80089f8: 2b05 cmp r3, #5 80089fa: d90c bls.n 8008a16 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80089fc: 687b ldr r3, [r7, #4] 80089fe: 2220 movs r2, #32 8008a00: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8008a02: 687b ldr r3, [r7, #4] 8008a04: 2203 movs r2, #3 8008a06: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8008a0a: 687b ldr r3, [r7, #4] 8008a0c: 2200 movs r2, #0 8008a0e: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8008a12: 2301 movs r3, #1 8008a14: e12d b.n 8008c72 while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8008a16: 697b ldr r3, [r7, #20] 8008a18: 681b ldr r3, [r3, #0] 8008a1a: f003 0301 and.w r3, r3, #1 8008a1e: 2b00 cmp r3, #0 8008a20: d1e5 bne.n 80089ee } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008a22: 687b ldr r3, [r7, #4] 8008a24: 681b ldr r3, [r3, #0] 8008a26: 4a2f ldr r2, [pc, #188] @ (8008ae4 ) 8008a28: 4293 cmp r3, r2 8008a2a: d04a beq.n 8008ac2 8008a2c: 687b ldr r3, [r7, #4] 8008a2e: 681b ldr r3, [r3, #0] 8008a30: 4a2d ldr r2, [pc, #180] @ (8008ae8 ) 8008a32: 4293 cmp r3, r2 8008a34: d045 beq.n 8008ac2 8008a36: 687b ldr r3, [r7, #4] 8008a38: 681b ldr r3, [r3, #0] 8008a3a: 4a2c ldr r2, [pc, #176] @ (8008aec ) 8008a3c: 4293 cmp r3, r2 8008a3e: d040 beq.n 8008ac2 8008a40: 687b ldr r3, [r7, #4] 8008a42: 681b ldr r3, [r3, #0] 8008a44: 4a2a ldr r2, [pc, #168] @ (8008af0 ) 8008a46: 4293 cmp r3, r2 8008a48: d03b beq.n 8008ac2 8008a4a: 687b ldr r3, [r7, #4] 8008a4c: 681b ldr r3, [r3, #0] 8008a4e: 4a29 ldr r2, [pc, #164] @ (8008af4 ) 8008a50: 4293 cmp r3, r2 8008a52: d036 beq.n 8008ac2 8008a54: 687b ldr r3, [r7, #4] 8008a56: 681b ldr r3, [r3, #0] 8008a58: 4a27 ldr r2, [pc, #156] @ (8008af8 ) 8008a5a: 4293 cmp r3, r2 8008a5c: d031 beq.n 8008ac2 8008a5e: 687b ldr r3, [r7, #4] 8008a60: 681b ldr r3, [r3, #0] 8008a62: 4a26 ldr r2, [pc, #152] @ (8008afc ) 8008a64: 4293 cmp r3, r2 8008a66: d02c beq.n 8008ac2 8008a68: 687b ldr r3, [r7, #4] 8008a6a: 681b ldr r3, [r3, #0] 8008a6c: 4a24 ldr r2, [pc, #144] @ (8008b00 ) 8008a6e: 4293 cmp r3, r2 8008a70: d027 beq.n 8008ac2 8008a72: 687b ldr r3, [r7, #4] 8008a74: 681b ldr r3, [r3, #0] 8008a76: 4a23 ldr r2, [pc, #140] @ (8008b04 ) 8008a78: 4293 cmp r3, r2 8008a7a: d022 beq.n 8008ac2 8008a7c: 687b ldr r3, [r7, #4] 8008a7e: 681b ldr r3, [r3, #0] 8008a80: 4a21 ldr r2, [pc, #132] @ (8008b08 ) 8008a82: 4293 cmp r3, r2 8008a84: d01d beq.n 8008ac2 8008a86: 687b ldr r3, [r7, #4] 8008a88: 681b ldr r3, [r3, #0] 8008a8a: 4a20 ldr r2, [pc, #128] @ (8008b0c ) 8008a8c: 4293 cmp r3, r2 8008a8e: d018 beq.n 8008ac2 8008a90: 687b ldr r3, [r7, #4] 8008a92: 681b ldr r3, [r3, #0] 8008a94: 4a1e ldr r2, [pc, #120] @ (8008b10 ) 8008a96: 4293 cmp r3, r2 8008a98: d013 beq.n 8008ac2 8008a9a: 687b ldr r3, [r7, #4] 8008a9c: 681b ldr r3, [r3, #0] 8008a9e: 4a1d ldr r2, [pc, #116] @ (8008b14 ) 8008aa0: 4293 cmp r3, r2 8008aa2: d00e beq.n 8008ac2 8008aa4: 687b ldr r3, [r7, #4] 8008aa6: 681b ldr r3, [r3, #0] 8008aa8: 4a1b ldr r2, [pc, #108] @ (8008b18 ) 8008aaa: 4293 cmp r3, r2 8008aac: d009 beq.n 8008ac2 8008aae: 687b ldr r3, [r7, #4] 8008ab0: 681b ldr r3, [r3, #0] 8008ab2: 4a1a ldr r2, [pc, #104] @ (8008b1c ) 8008ab4: 4293 cmp r3, r2 8008ab6: d004 beq.n 8008ac2 8008ab8: 687b ldr r3, [r7, #4] 8008aba: 681b ldr r3, [r3, #0] 8008abc: 4a18 ldr r2, [pc, #96] @ (8008b20 ) 8008abe: 4293 cmp r3, r2 8008ac0: d101 bne.n 8008ac6 8008ac2: 2301 movs r3, #1 8008ac4: e000 b.n 8008ac8 8008ac6: 2300 movs r3, #0 8008ac8: 2b00 cmp r3, #0 8008aca: d02b beq.n 8008b24 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8008acc: 687b ldr r3, [r7, #4] 8008ace: 6d9b ldr r3, [r3, #88] @ 0x58 8008ad0: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8008ad2: 687b ldr r3, [r7, #4] 8008ad4: 6ddb ldr r3, [r3, #92] @ 0x5c 8008ad6: f003 031f and.w r3, r3, #31 8008ada: 223f movs r2, #63 @ 0x3f 8008adc: 409a lsls r2, r3 8008ade: 68bb ldr r3, [r7, #8] 8008ae0: 609a str r2, [r3, #8] 8008ae2: e02a b.n 8008b3a 8008ae4: 40020010 .word 0x40020010 8008ae8: 40020028 .word 0x40020028 8008aec: 40020040 .word 0x40020040 8008af0: 40020058 .word 0x40020058 8008af4: 40020070 .word 0x40020070 8008af8: 40020088 .word 0x40020088 8008afc: 400200a0 .word 0x400200a0 8008b00: 400200b8 .word 0x400200b8 8008b04: 40020410 .word 0x40020410 8008b08: 40020428 .word 0x40020428 8008b0c: 40020440 .word 0x40020440 8008b10: 40020458 .word 0x40020458 8008b14: 40020470 .word 0x40020470 8008b18: 40020488 .word 0x40020488 8008b1c: 400204a0 .word 0x400204a0 8008b20: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8008b24: 687b ldr r3, [r7, #4] 8008b26: 6d9b ldr r3, [r3, #88] @ 0x58 8008b28: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8008b2a: 687b ldr r3, [r7, #4] 8008b2c: 6ddb ldr r3, [r3, #92] @ 0x5c 8008b2e: f003 031f and.w r3, r3, #31 8008b32: 2201 movs r2, #1 8008b34: 409a lsls r2, r3 8008b36: 68fb ldr r3, [r7, #12] 8008b38: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008b3a: 687b ldr r3, [r7, #4] 8008b3c: 681b ldr r3, [r3, #0] 8008b3e: 4a4f ldr r2, [pc, #316] @ (8008c7c ) 8008b40: 4293 cmp r3, r2 8008b42: d072 beq.n 8008c2a 8008b44: 687b ldr r3, [r7, #4] 8008b46: 681b ldr r3, [r3, #0] 8008b48: 4a4d ldr r2, [pc, #308] @ (8008c80 ) 8008b4a: 4293 cmp r3, r2 8008b4c: d06d beq.n 8008c2a 8008b4e: 687b ldr r3, [r7, #4] 8008b50: 681b ldr r3, [r3, #0] 8008b52: 4a4c ldr r2, [pc, #304] @ (8008c84 ) 8008b54: 4293 cmp r3, r2 8008b56: d068 beq.n 8008c2a 8008b58: 687b ldr r3, [r7, #4] 8008b5a: 681b ldr r3, [r3, #0] 8008b5c: 4a4a ldr r2, [pc, #296] @ (8008c88 ) 8008b5e: 4293 cmp r3, r2 8008b60: d063 beq.n 8008c2a 8008b62: 687b ldr r3, [r7, #4] 8008b64: 681b ldr r3, [r3, #0] 8008b66: 4a49 ldr r2, [pc, #292] @ (8008c8c ) 8008b68: 4293 cmp r3, r2 8008b6a: d05e beq.n 8008c2a 8008b6c: 687b ldr r3, [r7, #4] 8008b6e: 681b ldr r3, [r3, #0] 8008b70: 4a47 ldr r2, [pc, #284] @ (8008c90 ) 8008b72: 4293 cmp r3, r2 8008b74: d059 beq.n 8008c2a 8008b76: 687b ldr r3, [r7, #4] 8008b78: 681b ldr r3, [r3, #0] 8008b7a: 4a46 ldr r2, [pc, #280] @ (8008c94 ) 8008b7c: 4293 cmp r3, r2 8008b7e: d054 beq.n 8008c2a 8008b80: 687b ldr r3, [r7, #4] 8008b82: 681b ldr r3, [r3, #0] 8008b84: 4a44 ldr r2, [pc, #272] @ (8008c98 ) 8008b86: 4293 cmp r3, r2 8008b88: d04f beq.n 8008c2a 8008b8a: 687b ldr r3, [r7, #4] 8008b8c: 681b ldr r3, [r3, #0] 8008b8e: 4a43 ldr r2, [pc, #268] @ (8008c9c ) 8008b90: 4293 cmp r3, r2 8008b92: d04a beq.n 8008c2a 8008b94: 687b ldr r3, [r7, #4] 8008b96: 681b ldr r3, [r3, #0] 8008b98: 4a41 ldr r2, [pc, #260] @ (8008ca0 ) 8008b9a: 4293 cmp r3, r2 8008b9c: d045 beq.n 8008c2a 8008b9e: 687b ldr r3, [r7, #4] 8008ba0: 681b ldr r3, [r3, #0] 8008ba2: 4a40 ldr r2, [pc, #256] @ (8008ca4 ) 8008ba4: 4293 cmp r3, r2 8008ba6: d040 beq.n 8008c2a 8008ba8: 687b ldr r3, [r7, #4] 8008baa: 681b ldr r3, [r3, #0] 8008bac: 4a3e ldr r2, [pc, #248] @ (8008ca8 ) 8008bae: 4293 cmp r3, r2 8008bb0: d03b beq.n 8008c2a 8008bb2: 687b ldr r3, [r7, #4] 8008bb4: 681b ldr r3, [r3, #0] 8008bb6: 4a3d ldr r2, [pc, #244] @ (8008cac ) 8008bb8: 4293 cmp r3, r2 8008bba: d036 beq.n 8008c2a 8008bbc: 687b ldr r3, [r7, #4] 8008bbe: 681b ldr r3, [r3, #0] 8008bc0: 4a3b ldr r2, [pc, #236] @ (8008cb0 ) 8008bc2: 4293 cmp r3, r2 8008bc4: d031 beq.n 8008c2a 8008bc6: 687b ldr r3, [r7, #4] 8008bc8: 681b ldr r3, [r3, #0] 8008bca: 4a3a ldr r2, [pc, #232] @ (8008cb4 ) 8008bcc: 4293 cmp r3, r2 8008bce: d02c beq.n 8008c2a 8008bd0: 687b ldr r3, [r7, #4] 8008bd2: 681b ldr r3, [r3, #0] 8008bd4: 4a38 ldr r2, [pc, #224] @ (8008cb8 ) 8008bd6: 4293 cmp r3, r2 8008bd8: d027 beq.n 8008c2a 8008bda: 687b ldr r3, [r7, #4] 8008bdc: 681b ldr r3, [r3, #0] 8008bde: 4a37 ldr r2, [pc, #220] @ (8008cbc ) 8008be0: 4293 cmp r3, r2 8008be2: d022 beq.n 8008c2a 8008be4: 687b ldr r3, [r7, #4] 8008be6: 681b ldr r3, [r3, #0] 8008be8: 4a35 ldr r2, [pc, #212] @ (8008cc0 ) 8008bea: 4293 cmp r3, r2 8008bec: d01d beq.n 8008c2a 8008bee: 687b ldr r3, [r7, #4] 8008bf0: 681b ldr r3, [r3, #0] 8008bf2: 4a34 ldr r2, [pc, #208] @ (8008cc4 ) 8008bf4: 4293 cmp r3, r2 8008bf6: d018 beq.n 8008c2a 8008bf8: 687b ldr r3, [r7, #4] 8008bfa: 681b ldr r3, [r3, #0] 8008bfc: 4a32 ldr r2, [pc, #200] @ (8008cc8 ) 8008bfe: 4293 cmp r3, r2 8008c00: d013 beq.n 8008c2a 8008c02: 687b ldr r3, [r7, #4] 8008c04: 681b ldr r3, [r3, #0] 8008c06: 4a31 ldr r2, [pc, #196] @ (8008ccc ) 8008c08: 4293 cmp r3, r2 8008c0a: d00e beq.n 8008c2a 8008c0c: 687b ldr r3, [r7, #4] 8008c0e: 681b ldr r3, [r3, #0] 8008c10: 4a2f ldr r2, [pc, #188] @ (8008cd0 ) 8008c12: 4293 cmp r3, r2 8008c14: d009 beq.n 8008c2a 8008c16: 687b ldr r3, [r7, #4] 8008c18: 681b ldr r3, [r3, #0] 8008c1a: 4a2e ldr r2, [pc, #184] @ (8008cd4 ) 8008c1c: 4293 cmp r3, r2 8008c1e: d004 beq.n 8008c2a 8008c20: 687b ldr r3, [r7, #4] 8008c22: 681b ldr r3, [r3, #0] 8008c24: 4a2c ldr r2, [pc, #176] @ (8008cd8 ) 8008c26: 4293 cmp r3, r2 8008c28: d101 bne.n 8008c2e 8008c2a: 2301 movs r3, #1 8008c2c: e000 b.n 8008c30 8008c2e: 2300 movs r3, #0 8008c30: 2b00 cmp r3, #0 8008c32: d015 beq.n 8008c60 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8008c34: 687b ldr r3, [r7, #4] 8008c36: 6e5b ldr r3, [r3, #100] @ 0x64 8008c38: 687a ldr r2, [r7, #4] 8008c3a: 6e92 ldr r2, [r2, #104] @ 0x68 8008c3c: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8008c3e: 687b ldr r3, [r7, #4] 8008c40: 6edb ldr r3, [r3, #108] @ 0x6c 8008c42: 2b00 cmp r3, #0 8008c44: d00c beq.n 8008c60 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8008c46: 687b ldr r3, [r7, #4] 8008c48: 6edb ldr r3, [r3, #108] @ 0x6c 8008c4a: 681a ldr r2, [r3, #0] 8008c4c: 687b ldr r3, [r7, #4] 8008c4e: 6edb ldr r3, [r3, #108] @ 0x6c 8008c50: f422 7280 bic.w r2, r2, #256 @ 0x100 8008c54: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8008c56: 687b ldr r3, [r7, #4] 8008c58: 6f1b ldr r3, [r3, #112] @ 0x70 8008c5a: 687a ldr r2, [r7, #4] 8008c5c: 6f52 ldr r2, [r2, #116] @ 0x74 8008c5e: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008c60: 687b ldr r3, [r7, #4] 8008c62: 2201 movs r2, #1 8008c64: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8008c68: 687b ldr r3, [r7, #4] 8008c6a: 2200 movs r2, #0 8008c6c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 8008c70: 2300 movs r3, #0 } 8008c72: 4618 mov r0, r3 8008c74: 3718 adds r7, #24 8008c76: 46bd mov sp, r7 8008c78: bd80 pop {r7, pc} 8008c7a: bf00 nop 8008c7c: 40020010 .word 0x40020010 8008c80: 40020028 .word 0x40020028 8008c84: 40020040 .word 0x40020040 8008c88: 40020058 .word 0x40020058 8008c8c: 40020070 .word 0x40020070 8008c90: 40020088 .word 0x40020088 8008c94: 400200a0 .word 0x400200a0 8008c98: 400200b8 .word 0x400200b8 8008c9c: 40020410 .word 0x40020410 8008ca0: 40020428 .word 0x40020428 8008ca4: 40020440 .word 0x40020440 8008ca8: 40020458 .word 0x40020458 8008cac: 40020470 .word 0x40020470 8008cb0: 40020488 .word 0x40020488 8008cb4: 400204a0 .word 0x400204a0 8008cb8: 400204b8 .word 0x400204b8 8008cbc: 58025408 .word 0x58025408 8008cc0: 5802541c .word 0x5802541c 8008cc4: 58025430 .word 0x58025430 8008cc8: 58025444 .word 0x58025444 8008ccc: 58025458 .word 0x58025458 8008cd0: 5802546c .word 0x5802546c 8008cd4: 58025480 .word 0x58025480 8008cd8: 58025494 .word 0x58025494 08008cdc : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8008cdc: b580 push {r7, lr} 8008cde: b084 sub sp, #16 8008ce0: af00 add r7, sp, #0 8008ce2: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8008ce4: 687b ldr r3, [r7, #4] 8008ce6: 2b00 cmp r3, #0 8008ce8: d101 bne.n 8008cee { return HAL_ERROR; 8008cea: 2301 movs r3, #1 8008cec: e237 b.n 800915e } if(hdma->State != HAL_DMA_STATE_BUSY) 8008cee: 687b ldr r3, [r7, #4] 8008cf0: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008cf4: b2db uxtb r3, r3 8008cf6: 2b02 cmp r3, #2 8008cf8: d004 beq.n 8008d04 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8008cfa: 687b ldr r3, [r7, #4] 8008cfc: 2280 movs r2, #128 @ 0x80 8008cfe: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8008d00: 2301 movs r3, #1 8008d02: e22c b.n 800915e } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008d04: 687b ldr r3, [r7, #4] 8008d06: 681b ldr r3, [r3, #0] 8008d08: 4a5c ldr r2, [pc, #368] @ (8008e7c ) 8008d0a: 4293 cmp r3, r2 8008d0c: d04a beq.n 8008da4 8008d0e: 687b ldr r3, [r7, #4] 8008d10: 681b ldr r3, [r3, #0] 8008d12: 4a5b ldr r2, [pc, #364] @ (8008e80 ) 8008d14: 4293 cmp r3, r2 8008d16: d045 beq.n 8008da4 8008d18: 687b ldr r3, [r7, #4] 8008d1a: 681b ldr r3, [r3, #0] 8008d1c: 4a59 ldr r2, [pc, #356] @ (8008e84 ) 8008d1e: 4293 cmp r3, r2 8008d20: d040 beq.n 8008da4 8008d22: 687b ldr r3, [r7, #4] 8008d24: 681b ldr r3, [r3, #0] 8008d26: 4a58 ldr r2, [pc, #352] @ (8008e88 ) 8008d28: 4293 cmp r3, r2 8008d2a: d03b beq.n 8008da4 8008d2c: 687b ldr r3, [r7, #4] 8008d2e: 681b ldr r3, [r3, #0] 8008d30: 4a56 ldr r2, [pc, #344] @ (8008e8c ) 8008d32: 4293 cmp r3, r2 8008d34: d036 beq.n 8008da4 8008d36: 687b ldr r3, [r7, #4] 8008d38: 681b ldr r3, [r3, #0] 8008d3a: 4a55 ldr r2, [pc, #340] @ (8008e90 ) 8008d3c: 4293 cmp r3, r2 8008d3e: d031 beq.n 8008da4 8008d40: 687b ldr r3, [r7, #4] 8008d42: 681b ldr r3, [r3, #0] 8008d44: 4a53 ldr r2, [pc, #332] @ (8008e94 ) 8008d46: 4293 cmp r3, r2 8008d48: d02c beq.n 8008da4 8008d4a: 687b ldr r3, [r7, #4] 8008d4c: 681b ldr r3, [r3, #0] 8008d4e: 4a52 ldr r2, [pc, #328] @ (8008e98 ) 8008d50: 4293 cmp r3, r2 8008d52: d027 beq.n 8008da4 8008d54: 687b ldr r3, [r7, #4] 8008d56: 681b ldr r3, [r3, #0] 8008d58: 4a50 ldr r2, [pc, #320] @ (8008e9c ) 8008d5a: 4293 cmp r3, r2 8008d5c: d022 beq.n 8008da4 8008d5e: 687b ldr r3, [r7, #4] 8008d60: 681b ldr r3, [r3, #0] 8008d62: 4a4f ldr r2, [pc, #316] @ (8008ea0 ) 8008d64: 4293 cmp r3, r2 8008d66: d01d beq.n 8008da4 8008d68: 687b ldr r3, [r7, #4] 8008d6a: 681b ldr r3, [r3, #0] 8008d6c: 4a4d ldr r2, [pc, #308] @ (8008ea4 ) 8008d6e: 4293 cmp r3, r2 8008d70: d018 beq.n 8008da4 8008d72: 687b ldr r3, [r7, #4] 8008d74: 681b ldr r3, [r3, #0] 8008d76: 4a4c ldr r2, [pc, #304] @ (8008ea8 ) 8008d78: 4293 cmp r3, r2 8008d7a: d013 beq.n 8008da4 8008d7c: 687b ldr r3, [r7, #4] 8008d7e: 681b ldr r3, [r3, #0] 8008d80: 4a4a ldr r2, [pc, #296] @ (8008eac ) 8008d82: 4293 cmp r3, r2 8008d84: d00e beq.n 8008da4 8008d86: 687b ldr r3, [r7, #4] 8008d88: 681b ldr r3, [r3, #0] 8008d8a: 4a49 ldr r2, [pc, #292] @ (8008eb0 ) 8008d8c: 4293 cmp r3, r2 8008d8e: d009 beq.n 8008da4 8008d90: 687b ldr r3, [r7, #4] 8008d92: 681b ldr r3, [r3, #0] 8008d94: 4a47 ldr r2, [pc, #284] @ (8008eb4 ) 8008d96: 4293 cmp r3, r2 8008d98: d004 beq.n 8008da4 8008d9a: 687b ldr r3, [r7, #4] 8008d9c: 681b ldr r3, [r3, #0] 8008d9e: 4a46 ldr r2, [pc, #280] @ (8008eb8 ) 8008da0: 4293 cmp r3, r2 8008da2: d101 bne.n 8008da8 8008da4: 2301 movs r3, #1 8008da6: e000 b.n 8008daa 8008da8: 2300 movs r3, #0 8008daa: 2b00 cmp r3, #0 8008dac: f000 8086 beq.w 8008ebc { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 8008db0: 687b ldr r3, [r7, #4] 8008db2: 2204 movs r2, #4 8008db4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8008db8: 687b ldr r3, [r7, #4] 8008dba: 681b ldr r3, [r3, #0] 8008dbc: 4a2f ldr r2, [pc, #188] @ (8008e7c ) 8008dbe: 4293 cmp r3, r2 8008dc0: d04a beq.n 8008e58 8008dc2: 687b ldr r3, [r7, #4] 8008dc4: 681b ldr r3, [r3, #0] 8008dc6: 4a2e ldr r2, [pc, #184] @ (8008e80 ) 8008dc8: 4293 cmp r3, r2 8008dca: d045 beq.n 8008e58 8008dcc: 687b ldr r3, [r7, #4] 8008dce: 681b ldr r3, [r3, #0] 8008dd0: 4a2c ldr r2, [pc, #176] @ (8008e84 ) 8008dd2: 4293 cmp r3, r2 8008dd4: d040 beq.n 8008e58 8008dd6: 687b ldr r3, [r7, #4] 8008dd8: 681b ldr r3, [r3, #0] 8008dda: 4a2b ldr r2, [pc, #172] @ (8008e88 ) 8008ddc: 4293 cmp r3, r2 8008dde: d03b beq.n 8008e58 8008de0: 687b ldr r3, [r7, #4] 8008de2: 681b ldr r3, [r3, #0] 8008de4: 4a29 ldr r2, [pc, #164] @ (8008e8c ) 8008de6: 4293 cmp r3, r2 8008de8: d036 beq.n 8008e58 8008dea: 687b ldr r3, [r7, #4] 8008dec: 681b ldr r3, [r3, #0] 8008dee: 4a28 ldr r2, [pc, #160] @ (8008e90 ) 8008df0: 4293 cmp r3, r2 8008df2: d031 beq.n 8008e58 8008df4: 687b ldr r3, [r7, #4] 8008df6: 681b ldr r3, [r3, #0] 8008df8: 4a26 ldr r2, [pc, #152] @ (8008e94 ) 8008dfa: 4293 cmp r3, r2 8008dfc: d02c beq.n 8008e58 8008dfe: 687b ldr r3, [r7, #4] 8008e00: 681b ldr r3, [r3, #0] 8008e02: 4a25 ldr r2, [pc, #148] @ (8008e98 ) 8008e04: 4293 cmp r3, r2 8008e06: d027 beq.n 8008e58 8008e08: 687b ldr r3, [r7, #4] 8008e0a: 681b ldr r3, [r3, #0] 8008e0c: 4a23 ldr r2, [pc, #140] @ (8008e9c ) 8008e0e: 4293 cmp r3, r2 8008e10: d022 beq.n 8008e58 8008e12: 687b ldr r3, [r7, #4] 8008e14: 681b ldr r3, [r3, #0] 8008e16: 4a22 ldr r2, [pc, #136] @ (8008ea0 ) 8008e18: 4293 cmp r3, r2 8008e1a: d01d beq.n 8008e58 8008e1c: 687b ldr r3, [r7, #4] 8008e1e: 681b ldr r3, [r3, #0] 8008e20: 4a20 ldr r2, [pc, #128] @ (8008ea4 ) 8008e22: 4293 cmp r3, r2 8008e24: d018 beq.n 8008e58 8008e26: 687b ldr r3, [r7, #4] 8008e28: 681b ldr r3, [r3, #0] 8008e2a: 4a1f ldr r2, [pc, #124] @ (8008ea8 ) 8008e2c: 4293 cmp r3, r2 8008e2e: d013 beq.n 8008e58 8008e30: 687b ldr r3, [r7, #4] 8008e32: 681b ldr r3, [r3, #0] 8008e34: 4a1d ldr r2, [pc, #116] @ (8008eac ) 8008e36: 4293 cmp r3, r2 8008e38: d00e beq.n 8008e58 8008e3a: 687b ldr r3, [r7, #4] 8008e3c: 681b ldr r3, [r3, #0] 8008e3e: 4a1c ldr r2, [pc, #112] @ (8008eb0 ) 8008e40: 4293 cmp r3, r2 8008e42: d009 beq.n 8008e58 8008e44: 687b ldr r3, [r7, #4] 8008e46: 681b ldr r3, [r3, #0] 8008e48: 4a1a ldr r2, [pc, #104] @ (8008eb4 ) 8008e4a: 4293 cmp r3, r2 8008e4c: d004 beq.n 8008e58 8008e4e: 687b ldr r3, [r7, #4] 8008e50: 681b ldr r3, [r3, #0] 8008e52: 4a19 ldr r2, [pc, #100] @ (8008eb8 ) 8008e54: 4293 cmp r3, r2 8008e56: d108 bne.n 8008e6a 8008e58: 687b ldr r3, [r7, #4] 8008e5a: 681b ldr r3, [r3, #0] 8008e5c: 681a ldr r2, [r3, #0] 8008e5e: 687b ldr r3, [r7, #4] 8008e60: 681b ldr r3, [r3, #0] 8008e62: f022 0201 bic.w r2, r2, #1 8008e66: 601a str r2, [r3, #0] 8008e68: e178 b.n 800915c 8008e6a: 687b ldr r3, [r7, #4] 8008e6c: 681b ldr r3, [r3, #0] 8008e6e: 681a ldr r2, [r3, #0] 8008e70: 687b ldr r3, [r7, #4] 8008e72: 681b ldr r3, [r3, #0] 8008e74: f022 0201 bic.w r2, r2, #1 8008e78: 601a str r2, [r3, #0] 8008e7a: e16f b.n 800915c 8008e7c: 40020010 .word 0x40020010 8008e80: 40020028 .word 0x40020028 8008e84: 40020040 .word 0x40020040 8008e88: 40020058 .word 0x40020058 8008e8c: 40020070 .word 0x40020070 8008e90: 40020088 .word 0x40020088 8008e94: 400200a0 .word 0x400200a0 8008e98: 400200b8 .word 0x400200b8 8008e9c: 40020410 .word 0x40020410 8008ea0: 40020428 .word 0x40020428 8008ea4: 40020440 .word 0x40020440 8008ea8: 40020458 .word 0x40020458 8008eac: 40020470 .word 0x40020470 8008eb0: 40020488 .word 0x40020488 8008eb4: 400204a0 .word 0x400204a0 8008eb8: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8008ebc: 687b ldr r3, [r7, #4] 8008ebe: 681b ldr r3, [r3, #0] 8008ec0: 681a ldr r2, [r3, #0] 8008ec2: 687b ldr r3, [r7, #4] 8008ec4: 681b ldr r3, [r3, #0] 8008ec6: f022 020e bic.w r2, r2, #14 8008eca: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8008ecc: 687b ldr r3, [r7, #4] 8008ece: 681b ldr r3, [r3, #0] 8008ed0: 4a6c ldr r2, [pc, #432] @ (8009084 ) 8008ed2: 4293 cmp r3, r2 8008ed4: d04a beq.n 8008f6c 8008ed6: 687b ldr r3, [r7, #4] 8008ed8: 681b ldr r3, [r3, #0] 8008eda: 4a6b ldr r2, [pc, #428] @ (8009088 ) 8008edc: 4293 cmp r3, r2 8008ede: d045 beq.n 8008f6c 8008ee0: 687b ldr r3, [r7, #4] 8008ee2: 681b ldr r3, [r3, #0] 8008ee4: 4a69 ldr r2, [pc, #420] @ (800908c ) 8008ee6: 4293 cmp r3, r2 8008ee8: d040 beq.n 8008f6c 8008eea: 687b ldr r3, [r7, #4] 8008eec: 681b ldr r3, [r3, #0] 8008eee: 4a68 ldr r2, [pc, #416] @ (8009090 ) 8008ef0: 4293 cmp r3, r2 8008ef2: d03b beq.n 8008f6c 8008ef4: 687b ldr r3, [r7, #4] 8008ef6: 681b ldr r3, [r3, #0] 8008ef8: 4a66 ldr r2, [pc, #408] @ (8009094 ) 8008efa: 4293 cmp r3, r2 8008efc: d036 beq.n 8008f6c 8008efe: 687b ldr r3, [r7, #4] 8008f00: 681b ldr r3, [r3, #0] 8008f02: 4a65 ldr r2, [pc, #404] @ (8009098 ) 8008f04: 4293 cmp r3, r2 8008f06: d031 beq.n 8008f6c 8008f08: 687b ldr r3, [r7, #4] 8008f0a: 681b ldr r3, [r3, #0] 8008f0c: 4a63 ldr r2, [pc, #396] @ (800909c ) 8008f0e: 4293 cmp r3, r2 8008f10: d02c beq.n 8008f6c 8008f12: 687b ldr r3, [r7, #4] 8008f14: 681b ldr r3, [r3, #0] 8008f16: 4a62 ldr r2, [pc, #392] @ (80090a0 ) 8008f18: 4293 cmp r3, r2 8008f1a: d027 beq.n 8008f6c 8008f1c: 687b ldr r3, [r7, #4] 8008f1e: 681b ldr r3, [r3, #0] 8008f20: 4a60 ldr r2, [pc, #384] @ (80090a4 ) 8008f22: 4293 cmp r3, r2 8008f24: d022 beq.n 8008f6c 8008f26: 687b ldr r3, [r7, #4] 8008f28: 681b ldr r3, [r3, #0] 8008f2a: 4a5f ldr r2, [pc, #380] @ (80090a8 ) 8008f2c: 4293 cmp r3, r2 8008f2e: d01d beq.n 8008f6c 8008f30: 687b ldr r3, [r7, #4] 8008f32: 681b ldr r3, [r3, #0] 8008f34: 4a5d ldr r2, [pc, #372] @ (80090ac ) 8008f36: 4293 cmp r3, r2 8008f38: d018 beq.n 8008f6c 8008f3a: 687b ldr r3, [r7, #4] 8008f3c: 681b ldr r3, [r3, #0] 8008f3e: 4a5c ldr r2, [pc, #368] @ (80090b0 ) 8008f40: 4293 cmp r3, r2 8008f42: d013 beq.n 8008f6c 8008f44: 687b ldr r3, [r7, #4] 8008f46: 681b ldr r3, [r3, #0] 8008f48: 4a5a ldr r2, [pc, #360] @ (80090b4 ) 8008f4a: 4293 cmp r3, r2 8008f4c: d00e beq.n 8008f6c 8008f4e: 687b ldr r3, [r7, #4] 8008f50: 681b ldr r3, [r3, #0] 8008f52: 4a59 ldr r2, [pc, #356] @ (80090b8 ) 8008f54: 4293 cmp r3, r2 8008f56: d009 beq.n 8008f6c 8008f58: 687b ldr r3, [r7, #4] 8008f5a: 681b ldr r3, [r3, #0] 8008f5c: 4a57 ldr r2, [pc, #348] @ (80090bc ) 8008f5e: 4293 cmp r3, r2 8008f60: d004 beq.n 8008f6c 8008f62: 687b ldr r3, [r7, #4] 8008f64: 681b ldr r3, [r3, #0] 8008f66: 4a56 ldr r2, [pc, #344] @ (80090c0 ) 8008f68: 4293 cmp r3, r2 8008f6a: d108 bne.n 8008f7e 8008f6c: 687b ldr r3, [r7, #4] 8008f6e: 681b ldr r3, [r3, #0] 8008f70: 681a ldr r2, [r3, #0] 8008f72: 687b ldr r3, [r7, #4] 8008f74: 681b ldr r3, [r3, #0] 8008f76: f022 0201 bic.w r2, r2, #1 8008f7a: 601a str r2, [r3, #0] 8008f7c: e007 b.n 8008f8e 8008f7e: 687b ldr r3, [r7, #4] 8008f80: 681b ldr r3, [r3, #0] 8008f82: 681a ldr r2, [r3, #0] 8008f84: 687b ldr r3, [r7, #4] 8008f86: 681b ldr r3, [r3, #0] 8008f88: f022 0201 bic.w r2, r2, #1 8008f8c: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008f8e: 687b ldr r3, [r7, #4] 8008f90: 681b ldr r3, [r3, #0] 8008f92: 4a3c ldr r2, [pc, #240] @ (8009084 ) 8008f94: 4293 cmp r3, r2 8008f96: d072 beq.n 800907e 8008f98: 687b ldr r3, [r7, #4] 8008f9a: 681b ldr r3, [r3, #0] 8008f9c: 4a3a ldr r2, [pc, #232] @ (8009088 ) 8008f9e: 4293 cmp r3, r2 8008fa0: d06d beq.n 800907e 8008fa2: 687b ldr r3, [r7, #4] 8008fa4: 681b ldr r3, [r3, #0] 8008fa6: 4a39 ldr r2, [pc, #228] @ (800908c ) 8008fa8: 4293 cmp r3, r2 8008faa: d068 beq.n 800907e 8008fac: 687b ldr r3, [r7, #4] 8008fae: 681b ldr r3, [r3, #0] 8008fb0: 4a37 ldr r2, [pc, #220] @ (8009090 ) 8008fb2: 4293 cmp r3, r2 8008fb4: d063 beq.n 800907e 8008fb6: 687b ldr r3, [r7, #4] 8008fb8: 681b ldr r3, [r3, #0] 8008fba: 4a36 ldr r2, [pc, #216] @ (8009094 ) 8008fbc: 4293 cmp r3, r2 8008fbe: d05e beq.n 800907e 8008fc0: 687b ldr r3, [r7, #4] 8008fc2: 681b ldr r3, [r3, #0] 8008fc4: 4a34 ldr r2, [pc, #208] @ (8009098 ) 8008fc6: 4293 cmp r3, r2 8008fc8: d059 beq.n 800907e 8008fca: 687b ldr r3, [r7, #4] 8008fcc: 681b ldr r3, [r3, #0] 8008fce: 4a33 ldr r2, [pc, #204] @ (800909c ) 8008fd0: 4293 cmp r3, r2 8008fd2: d054 beq.n 800907e 8008fd4: 687b ldr r3, [r7, #4] 8008fd6: 681b ldr r3, [r3, #0] 8008fd8: 4a31 ldr r2, [pc, #196] @ (80090a0 ) 8008fda: 4293 cmp r3, r2 8008fdc: d04f beq.n 800907e 8008fde: 687b ldr r3, [r7, #4] 8008fe0: 681b ldr r3, [r3, #0] 8008fe2: 4a30 ldr r2, [pc, #192] @ (80090a4 ) 8008fe4: 4293 cmp r3, r2 8008fe6: d04a beq.n 800907e 8008fe8: 687b ldr r3, [r7, #4] 8008fea: 681b ldr r3, [r3, #0] 8008fec: 4a2e ldr r2, [pc, #184] @ (80090a8 ) 8008fee: 4293 cmp r3, r2 8008ff0: d045 beq.n 800907e 8008ff2: 687b ldr r3, [r7, #4] 8008ff4: 681b ldr r3, [r3, #0] 8008ff6: 4a2d ldr r2, [pc, #180] @ (80090ac ) 8008ff8: 4293 cmp r3, r2 8008ffa: d040 beq.n 800907e 8008ffc: 687b ldr r3, [r7, #4] 8008ffe: 681b ldr r3, [r3, #0] 8009000: 4a2b ldr r2, [pc, #172] @ (80090b0 ) 8009002: 4293 cmp r3, r2 8009004: d03b beq.n 800907e 8009006: 687b ldr r3, [r7, #4] 8009008: 681b ldr r3, [r3, #0] 800900a: 4a2a ldr r2, [pc, #168] @ (80090b4 ) 800900c: 4293 cmp r3, r2 800900e: d036 beq.n 800907e 8009010: 687b ldr r3, [r7, #4] 8009012: 681b ldr r3, [r3, #0] 8009014: 4a28 ldr r2, [pc, #160] @ (80090b8 ) 8009016: 4293 cmp r3, r2 8009018: d031 beq.n 800907e 800901a: 687b ldr r3, [r7, #4] 800901c: 681b ldr r3, [r3, #0] 800901e: 4a27 ldr r2, [pc, #156] @ (80090bc ) 8009020: 4293 cmp r3, r2 8009022: d02c beq.n 800907e 8009024: 687b ldr r3, [r7, #4] 8009026: 681b ldr r3, [r3, #0] 8009028: 4a25 ldr r2, [pc, #148] @ (80090c0 ) 800902a: 4293 cmp r3, r2 800902c: d027 beq.n 800907e 800902e: 687b ldr r3, [r7, #4] 8009030: 681b ldr r3, [r3, #0] 8009032: 4a24 ldr r2, [pc, #144] @ (80090c4 ) 8009034: 4293 cmp r3, r2 8009036: d022 beq.n 800907e 8009038: 687b ldr r3, [r7, #4] 800903a: 681b ldr r3, [r3, #0] 800903c: 4a22 ldr r2, [pc, #136] @ (80090c8 ) 800903e: 4293 cmp r3, r2 8009040: d01d beq.n 800907e 8009042: 687b ldr r3, [r7, #4] 8009044: 681b ldr r3, [r3, #0] 8009046: 4a21 ldr r2, [pc, #132] @ (80090cc ) 8009048: 4293 cmp r3, r2 800904a: d018 beq.n 800907e 800904c: 687b ldr r3, [r7, #4] 800904e: 681b ldr r3, [r3, #0] 8009050: 4a1f ldr r2, [pc, #124] @ (80090d0 ) 8009052: 4293 cmp r3, r2 8009054: d013 beq.n 800907e 8009056: 687b ldr r3, [r7, #4] 8009058: 681b ldr r3, [r3, #0] 800905a: 4a1e ldr r2, [pc, #120] @ (80090d4 ) 800905c: 4293 cmp r3, r2 800905e: d00e beq.n 800907e 8009060: 687b ldr r3, [r7, #4] 8009062: 681b ldr r3, [r3, #0] 8009064: 4a1c ldr r2, [pc, #112] @ (80090d8 ) 8009066: 4293 cmp r3, r2 8009068: d009 beq.n 800907e 800906a: 687b ldr r3, [r7, #4] 800906c: 681b ldr r3, [r3, #0] 800906e: 4a1b ldr r2, [pc, #108] @ (80090dc ) 8009070: 4293 cmp r3, r2 8009072: d004 beq.n 800907e 8009074: 687b ldr r3, [r7, #4] 8009076: 681b ldr r3, [r3, #0] 8009078: 4a19 ldr r2, [pc, #100] @ (80090e0 ) 800907a: 4293 cmp r3, r2 800907c: d132 bne.n 80090e4 800907e: 2301 movs r3, #1 8009080: e031 b.n 80090e6 8009082: bf00 nop 8009084: 40020010 .word 0x40020010 8009088: 40020028 .word 0x40020028 800908c: 40020040 .word 0x40020040 8009090: 40020058 .word 0x40020058 8009094: 40020070 .word 0x40020070 8009098: 40020088 .word 0x40020088 800909c: 400200a0 .word 0x400200a0 80090a0: 400200b8 .word 0x400200b8 80090a4: 40020410 .word 0x40020410 80090a8: 40020428 .word 0x40020428 80090ac: 40020440 .word 0x40020440 80090b0: 40020458 .word 0x40020458 80090b4: 40020470 .word 0x40020470 80090b8: 40020488 .word 0x40020488 80090bc: 400204a0 .word 0x400204a0 80090c0: 400204b8 .word 0x400204b8 80090c4: 58025408 .word 0x58025408 80090c8: 5802541c .word 0x5802541c 80090cc: 58025430 .word 0x58025430 80090d0: 58025444 .word 0x58025444 80090d4: 58025458 .word 0x58025458 80090d8: 5802546c .word 0x5802546c 80090dc: 58025480 .word 0x58025480 80090e0: 58025494 .word 0x58025494 80090e4: 2300 movs r3, #0 80090e6: 2b00 cmp r3, #0 80090e8: d028 beq.n 800913c { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 80090ea: 687b ldr r3, [r7, #4] 80090ec: 6e1b ldr r3, [r3, #96] @ 0x60 80090ee: 681a ldr r2, [r3, #0] 80090f0: 687b ldr r3, [r7, #4] 80090f2: 6e1b ldr r3, [r3, #96] @ 0x60 80090f4: f422 7280 bic.w r2, r2, #256 @ 0x100 80090f8: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 80090fa: 687b ldr r3, [r7, #4] 80090fc: 6d9b ldr r3, [r3, #88] @ 0x58 80090fe: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8009100: 687b ldr r3, [r7, #4] 8009102: 6ddb ldr r3, [r3, #92] @ 0x5c 8009104: f003 031f and.w r3, r3, #31 8009108: 2201 movs r2, #1 800910a: 409a lsls r2, r3 800910c: 68fb ldr r3, [r7, #12] 800910e: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009110: 687b ldr r3, [r7, #4] 8009112: 6e5b ldr r3, [r3, #100] @ 0x64 8009114: 687a ldr r2, [r7, #4] 8009116: 6e92 ldr r2, [r2, #104] @ 0x68 8009118: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800911a: 687b ldr r3, [r7, #4] 800911c: 6edb ldr r3, [r3, #108] @ 0x6c 800911e: 2b00 cmp r3, #0 8009120: d00c beq.n 800913c { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8009122: 687b ldr r3, [r7, #4] 8009124: 6edb ldr r3, [r3, #108] @ 0x6c 8009126: 681a ldr r2, [r3, #0] 8009128: 687b ldr r3, [r7, #4] 800912a: 6edb ldr r3, [r3, #108] @ 0x6c 800912c: f422 7280 bic.w r2, r2, #256 @ 0x100 8009130: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009132: 687b ldr r3, [r7, #4] 8009134: 6f1b ldr r3, [r3, #112] @ 0x70 8009136: 687a ldr r2, [r7, #4] 8009138: 6f52 ldr r2, [r2, #116] @ 0x74 800913a: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800913c: 687b ldr r3, [r7, #4] 800913e: 2201 movs r2, #1 8009140: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009144: 687b ldr r3, [r7, #4] 8009146: 2200 movs r2, #0 8009148: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 800914c: 687b ldr r3, [r7, #4] 800914e: 6d1b ldr r3, [r3, #80] @ 0x50 8009150: 2b00 cmp r3, #0 8009152: d003 beq.n 800915c { hdma->XferAbortCallback(hdma); 8009154: 687b ldr r3, [r7, #4] 8009156: 6d1b ldr r3, [r3, #80] @ 0x50 8009158: 6878 ldr r0, [r7, #4] 800915a: 4798 blx r3 } } } return HAL_OK; 800915c: 2300 movs r3, #0 } 800915e: 4618 mov r0, r3 8009160: 3710 adds r7, #16 8009162: 46bd mov sp, r7 8009164: bd80 pop {r7, pc} 8009166: bf00 nop 08009168 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8009168: b580 push {r7, lr} 800916a: b08a sub sp, #40 @ 0x28 800916c: af00 add r7, sp, #0 800916e: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8009170: 2300 movs r3, #0 8009172: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8009174: 4b67 ldr r3, [pc, #412] @ (8009314 ) 8009176: 681b ldr r3, [r3, #0] 8009178: 4a67 ldr r2, [pc, #412] @ (8009318 ) 800917a: fba2 2303 umull r2, r3, r2, r3 800917e: 0a9b lsrs r3, r3, #10 8009180: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009182: 687b ldr r3, [r7, #4] 8009184: 6d9b ldr r3, [r3, #88] @ 0x58 8009186: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009188: 687b ldr r3, [r7, #4] 800918a: 6d9b ldr r3, [r3, #88] @ 0x58 800918c: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 800918e: 6a3b ldr r3, [r7, #32] 8009190: 681b ldr r3, [r3, #0] 8009192: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8009194: 69fb ldr r3, [r7, #28] 8009196: 681b ldr r3, [r3, #0] 8009198: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800919a: 687b ldr r3, [r7, #4] 800919c: 681b ldr r3, [r3, #0] 800919e: 4a5f ldr r2, [pc, #380] @ (800931c ) 80091a0: 4293 cmp r3, r2 80091a2: d04a beq.n 800923a 80091a4: 687b ldr r3, [r7, #4] 80091a6: 681b ldr r3, [r3, #0] 80091a8: 4a5d ldr r2, [pc, #372] @ (8009320 ) 80091aa: 4293 cmp r3, r2 80091ac: d045 beq.n 800923a 80091ae: 687b ldr r3, [r7, #4] 80091b0: 681b ldr r3, [r3, #0] 80091b2: 4a5c ldr r2, [pc, #368] @ (8009324 ) 80091b4: 4293 cmp r3, r2 80091b6: d040 beq.n 800923a 80091b8: 687b ldr r3, [r7, #4] 80091ba: 681b ldr r3, [r3, #0] 80091bc: 4a5a ldr r2, [pc, #360] @ (8009328 ) 80091be: 4293 cmp r3, r2 80091c0: d03b beq.n 800923a 80091c2: 687b ldr r3, [r7, #4] 80091c4: 681b ldr r3, [r3, #0] 80091c6: 4a59 ldr r2, [pc, #356] @ (800932c ) 80091c8: 4293 cmp r3, r2 80091ca: d036 beq.n 800923a 80091cc: 687b ldr r3, [r7, #4] 80091ce: 681b ldr r3, [r3, #0] 80091d0: 4a57 ldr r2, [pc, #348] @ (8009330 ) 80091d2: 4293 cmp r3, r2 80091d4: d031 beq.n 800923a 80091d6: 687b ldr r3, [r7, #4] 80091d8: 681b ldr r3, [r3, #0] 80091da: 4a56 ldr r2, [pc, #344] @ (8009334 ) 80091dc: 4293 cmp r3, r2 80091de: d02c beq.n 800923a 80091e0: 687b ldr r3, [r7, #4] 80091e2: 681b ldr r3, [r3, #0] 80091e4: 4a54 ldr r2, [pc, #336] @ (8009338 ) 80091e6: 4293 cmp r3, r2 80091e8: d027 beq.n 800923a 80091ea: 687b ldr r3, [r7, #4] 80091ec: 681b ldr r3, [r3, #0] 80091ee: 4a53 ldr r2, [pc, #332] @ (800933c ) 80091f0: 4293 cmp r3, r2 80091f2: d022 beq.n 800923a 80091f4: 687b ldr r3, [r7, #4] 80091f6: 681b ldr r3, [r3, #0] 80091f8: 4a51 ldr r2, [pc, #324] @ (8009340 ) 80091fa: 4293 cmp r3, r2 80091fc: d01d beq.n 800923a 80091fe: 687b ldr r3, [r7, #4] 8009200: 681b ldr r3, [r3, #0] 8009202: 4a50 ldr r2, [pc, #320] @ (8009344 ) 8009204: 4293 cmp r3, r2 8009206: d018 beq.n 800923a 8009208: 687b ldr r3, [r7, #4] 800920a: 681b ldr r3, [r3, #0] 800920c: 4a4e ldr r2, [pc, #312] @ (8009348 ) 800920e: 4293 cmp r3, r2 8009210: d013 beq.n 800923a 8009212: 687b ldr r3, [r7, #4] 8009214: 681b ldr r3, [r3, #0] 8009216: 4a4d ldr r2, [pc, #308] @ (800934c ) 8009218: 4293 cmp r3, r2 800921a: d00e beq.n 800923a 800921c: 687b ldr r3, [r7, #4] 800921e: 681b ldr r3, [r3, #0] 8009220: 4a4b ldr r2, [pc, #300] @ (8009350 ) 8009222: 4293 cmp r3, r2 8009224: d009 beq.n 800923a 8009226: 687b ldr r3, [r7, #4] 8009228: 681b ldr r3, [r3, #0] 800922a: 4a4a ldr r2, [pc, #296] @ (8009354 ) 800922c: 4293 cmp r3, r2 800922e: d004 beq.n 800923a 8009230: 687b ldr r3, [r7, #4] 8009232: 681b ldr r3, [r3, #0] 8009234: 4a48 ldr r2, [pc, #288] @ (8009358 ) 8009236: 4293 cmp r3, r2 8009238: d101 bne.n 800923e 800923a: 2301 movs r3, #1 800923c: e000 b.n 8009240 800923e: 2300 movs r3, #0 8009240: 2b00 cmp r3, #0 8009242: f000 842b beq.w 8009a9c { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009246: 687b ldr r3, [r7, #4] 8009248: 6ddb ldr r3, [r3, #92] @ 0x5c 800924a: f003 031f and.w r3, r3, #31 800924e: 2208 movs r2, #8 8009250: 409a lsls r2, r3 8009252: 69bb ldr r3, [r7, #24] 8009254: 4013 ands r3, r2 8009256: 2b00 cmp r3, #0 8009258: f000 80a2 beq.w 80093a0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 800925c: 687b ldr r3, [r7, #4] 800925e: 681b ldr r3, [r3, #0] 8009260: 4a2e ldr r2, [pc, #184] @ (800931c ) 8009262: 4293 cmp r3, r2 8009264: d04a beq.n 80092fc 8009266: 687b ldr r3, [r7, #4] 8009268: 681b ldr r3, [r3, #0] 800926a: 4a2d ldr r2, [pc, #180] @ (8009320 ) 800926c: 4293 cmp r3, r2 800926e: d045 beq.n 80092fc 8009270: 687b ldr r3, [r7, #4] 8009272: 681b ldr r3, [r3, #0] 8009274: 4a2b ldr r2, [pc, #172] @ (8009324 ) 8009276: 4293 cmp r3, r2 8009278: d040 beq.n 80092fc 800927a: 687b ldr r3, [r7, #4] 800927c: 681b ldr r3, [r3, #0] 800927e: 4a2a ldr r2, [pc, #168] @ (8009328 ) 8009280: 4293 cmp r3, r2 8009282: d03b beq.n 80092fc 8009284: 687b ldr r3, [r7, #4] 8009286: 681b ldr r3, [r3, #0] 8009288: 4a28 ldr r2, [pc, #160] @ (800932c ) 800928a: 4293 cmp r3, r2 800928c: d036 beq.n 80092fc 800928e: 687b ldr r3, [r7, #4] 8009290: 681b ldr r3, [r3, #0] 8009292: 4a27 ldr r2, [pc, #156] @ (8009330 ) 8009294: 4293 cmp r3, r2 8009296: d031 beq.n 80092fc 8009298: 687b ldr r3, [r7, #4] 800929a: 681b ldr r3, [r3, #0] 800929c: 4a25 ldr r2, [pc, #148] @ (8009334 ) 800929e: 4293 cmp r3, r2 80092a0: d02c beq.n 80092fc 80092a2: 687b ldr r3, [r7, #4] 80092a4: 681b ldr r3, [r3, #0] 80092a6: 4a24 ldr r2, [pc, #144] @ (8009338 ) 80092a8: 4293 cmp r3, r2 80092aa: d027 beq.n 80092fc 80092ac: 687b ldr r3, [r7, #4] 80092ae: 681b ldr r3, [r3, #0] 80092b0: 4a22 ldr r2, [pc, #136] @ (800933c ) 80092b2: 4293 cmp r3, r2 80092b4: d022 beq.n 80092fc 80092b6: 687b ldr r3, [r7, #4] 80092b8: 681b ldr r3, [r3, #0] 80092ba: 4a21 ldr r2, [pc, #132] @ (8009340 ) 80092bc: 4293 cmp r3, r2 80092be: d01d beq.n 80092fc 80092c0: 687b ldr r3, [r7, #4] 80092c2: 681b ldr r3, [r3, #0] 80092c4: 4a1f ldr r2, [pc, #124] @ (8009344 ) 80092c6: 4293 cmp r3, r2 80092c8: d018 beq.n 80092fc 80092ca: 687b ldr r3, [r7, #4] 80092cc: 681b ldr r3, [r3, #0] 80092ce: 4a1e ldr r2, [pc, #120] @ (8009348 ) 80092d0: 4293 cmp r3, r2 80092d2: d013 beq.n 80092fc 80092d4: 687b ldr r3, [r7, #4] 80092d6: 681b ldr r3, [r3, #0] 80092d8: 4a1c ldr r2, [pc, #112] @ (800934c ) 80092da: 4293 cmp r3, r2 80092dc: d00e beq.n 80092fc 80092de: 687b ldr r3, [r7, #4] 80092e0: 681b ldr r3, [r3, #0] 80092e2: 4a1b ldr r2, [pc, #108] @ (8009350 ) 80092e4: 4293 cmp r3, r2 80092e6: d009 beq.n 80092fc 80092e8: 687b ldr r3, [r7, #4] 80092ea: 681b ldr r3, [r3, #0] 80092ec: 4a19 ldr r2, [pc, #100] @ (8009354 ) 80092ee: 4293 cmp r3, r2 80092f0: d004 beq.n 80092fc 80092f2: 687b ldr r3, [r7, #4] 80092f4: 681b ldr r3, [r3, #0] 80092f6: 4a18 ldr r2, [pc, #96] @ (8009358 ) 80092f8: 4293 cmp r3, r2 80092fa: d12f bne.n 800935c 80092fc: 687b ldr r3, [r7, #4] 80092fe: 681b ldr r3, [r3, #0] 8009300: 681b ldr r3, [r3, #0] 8009302: f003 0304 and.w r3, r3, #4 8009306: 2b00 cmp r3, #0 8009308: bf14 ite ne 800930a: 2301 movne r3, #1 800930c: 2300 moveq r3, #0 800930e: b2db uxtb r3, r3 8009310: e02e b.n 8009370 8009312: bf00 nop 8009314: 24000034 .word 0x24000034 8009318: 1b4e81b5 .word 0x1b4e81b5 800931c: 40020010 .word 0x40020010 8009320: 40020028 .word 0x40020028 8009324: 40020040 .word 0x40020040 8009328: 40020058 .word 0x40020058 800932c: 40020070 .word 0x40020070 8009330: 40020088 .word 0x40020088 8009334: 400200a0 .word 0x400200a0 8009338: 400200b8 .word 0x400200b8 800933c: 40020410 .word 0x40020410 8009340: 40020428 .word 0x40020428 8009344: 40020440 .word 0x40020440 8009348: 40020458 .word 0x40020458 800934c: 40020470 .word 0x40020470 8009350: 40020488 .word 0x40020488 8009354: 400204a0 .word 0x400204a0 8009358: 400204b8 .word 0x400204b8 800935c: 687b ldr r3, [r7, #4] 800935e: 681b ldr r3, [r3, #0] 8009360: 681b ldr r3, [r3, #0] 8009362: f003 0308 and.w r3, r3, #8 8009366: 2b00 cmp r3, #0 8009368: bf14 ite ne 800936a: 2301 movne r3, #1 800936c: 2300 moveq r3, #0 800936e: b2db uxtb r3, r3 8009370: 2b00 cmp r3, #0 8009372: d015 beq.n 80093a0 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8009374: 687b ldr r3, [r7, #4] 8009376: 681b ldr r3, [r3, #0] 8009378: 681a ldr r2, [r3, #0] 800937a: 687b ldr r3, [r7, #4] 800937c: 681b ldr r3, [r3, #0] 800937e: f022 0204 bic.w r2, r2, #4 8009382: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009384: 687b ldr r3, [r7, #4] 8009386: 6ddb ldr r3, [r3, #92] @ 0x5c 8009388: f003 031f and.w r3, r3, #31 800938c: 2208 movs r2, #8 800938e: 409a lsls r2, r3 8009390: 6a3b ldr r3, [r7, #32] 8009392: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8009394: 687b ldr r3, [r7, #4] 8009396: 6d5b ldr r3, [r3, #84] @ 0x54 8009398: f043 0201 orr.w r2, r3, #1 800939c: 687b ldr r3, [r7, #4] 800939e: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80093a0: 687b ldr r3, [r7, #4] 80093a2: 6ddb ldr r3, [r3, #92] @ 0x5c 80093a4: f003 031f and.w r3, r3, #31 80093a8: 69ba ldr r2, [r7, #24] 80093aa: fa22 f303 lsr.w r3, r2, r3 80093ae: f003 0301 and.w r3, r3, #1 80093b2: 2b00 cmp r3, #0 80093b4: d06e beq.n 8009494 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 80093b6: 687b ldr r3, [r7, #4] 80093b8: 681b ldr r3, [r3, #0] 80093ba: 4a69 ldr r2, [pc, #420] @ (8009560 ) 80093bc: 4293 cmp r3, r2 80093be: d04a beq.n 8009456 80093c0: 687b ldr r3, [r7, #4] 80093c2: 681b ldr r3, [r3, #0] 80093c4: 4a67 ldr r2, [pc, #412] @ (8009564 ) 80093c6: 4293 cmp r3, r2 80093c8: d045 beq.n 8009456 80093ca: 687b ldr r3, [r7, #4] 80093cc: 681b ldr r3, [r3, #0] 80093ce: 4a66 ldr r2, [pc, #408] @ (8009568 ) 80093d0: 4293 cmp r3, r2 80093d2: d040 beq.n 8009456 80093d4: 687b ldr r3, [r7, #4] 80093d6: 681b ldr r3, [r3, #0] 80093d8: 4a64 ldr r2, [pc, #400] @ (800956c ) 80093da: 4293 cmp r3, r2 80093dc: d03b beq.n 8009456 80093de: 687b ldr r3, [r7, #4] 80093e0: 681b ldr r3, [r3, #0] 80093e2: 4a63 ldr r2, [pc, #396] @ (8009570 ) 80093e4: 4293 cmp r3, r2 80093e6: d036 beq.n 8009456 80093e8: 687b ldr r3, [r7, #4] 80093ea: 681b ldr r3, [r3, #0] 80093ec: 4a61 ldr r2, [pc, #388] @ (8009574 ) 80093ee: 4293 cmp r3, r2 80093f0: d031 beq.n 8009456 80093f2: 687b ldr r3, [r7, #4] 80093f4: 681b ldr r3, [r3, #0] 80093f6: 4a60 ldr r2, [pc, #384] @ (8009578 ) 80093f8: 4293 cmp r3, r2 80093fa: d02c beq.n 8009456 80093fc: 687b ldr r3, [r7, #4] 80093fe: 681b ldr r3, [r3, #0] 8009400: 4a5e ldr r2, [pc, #376] @ (800957c ) 8009402: 4293 cmp r3, r2 8009404: d027 beq.n 8009456 8009406: 687b ldr r3, [r7, #4] 8009408: 681b ldr r3, [r3, #0] 800940a: 4a5d ldr r2, [pc, #372] @ (8009580 ) 800940c: 4293 cmp r3, r2 800940e: d022 beq.n 8009456 8009410: 687b ldr r3, [r7, #4] 8009412: 681b ldr r3, [r3, #0] 8009414: 4a5b ldr r2, [pc, #364] @ (8009584 ) 8009416: 4293 cmp r3, r2 8009418: d01d beq.n 8009456 800941a: 687b ldr r3, [r7, #4] 800941c: 681b ldr r3, [r3, #0] 800941e: 4a5a ldr r2, [pc, #360] @ (8009588 ) 8009420: 4293 cmp r3, r2 8009422: d018 beq.n 8009456 8009424: 687b ldr r3, [r7, #4] 8009426: 681b ldr r3, [r3, #0] 8009428: 4a58 ldr r2, [pc, #352] @ (800958c ) 800942a: 4293 cmp r3, r2 800942c: d013 beq.n 8009456 800942e: 687b ldr r3, [r7, #4] 8009430: 681b ldr r3, [r3, #0] 8009432: 4a57 ldr r2, [pc, #348] @ (8009590 ) 8009434: 4293 cmp r3, r2 8009436: d00e beq.n 8009456 8009438: 687b ldr r3, [r7, #4] 800943a: 681b ldr r3, [r3, #0] 800943c: 4a55 ldr r2, [pc, #340] @ (8009594 ) 800943e: 4293 cmp r3, r2 8009440: d009 beq.n 8009456 8009442: 687b ldr r3, [r7, #4] 8009444: 681b ldr r3, [r3, #0] 8009446: 4a54 ldr r2, [pc, #336] @ (8009598 ) 8009448: 4293 cmp r3, r2 800944a: d004 beq.n 8009456 800944c: 687b ldr r3, [r7, #4] 800944e: 681b ldr r3, [r3, #0] 8009450: 4a52 ldr r2, [pc, #328] @ (800959c ) 8009452: 4293 cmp r3, r2 8009454: d10a bne.n 800946c 8009456: 687b ldr r3, [r7, #4] 8009458: 681b ldr r3, [r3, #0] 800945a: 695b ldr r3, [r3, #20] 800945c: f003 0380 and.w r3, r3, #128 @ 0x80 8009460: 2b00 cmp r3, #0 8009462: bf14 ite ne 8009464: 2301 movne r3, #1 8009466: 2300 moveq r3, #0 8009468: b2db uxtb r3, r3 800946a: e003 b.n 8009474 800946c: 687b ldr r3, [r7, #4] 800946e: 681b ldr r3, [r3, #0] 8009470: 681b ldr r3, [r3, #0] 8009472: 2300 movs r3, #0 8009474: 2b00 cmp r3, #0 8009476: d00d beq.n 8009494 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009478: 687b ldr r3, [r7, #4] 800947a: 6ddb ldr r3, [r3, #92] @ 0x5c 800947c: f003 031f and.w r3, r3, #31 8009480: 2201 movs r2, #1 8009482: 409a lsls r2, r3 8009484: 6a3b ldr r3, [r7, #32] 8009486: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8009488: 687b ldr r3, [r7, #4] 800948a: 6d5b ldr r3, [r3, #84] @ 0x54 800948c: f043 0202 orr.w r2, r3, #2 8009490: 687b ldr r3, [r7, #4] 8009492: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009494: 687b ldr r3, [r7, #4] 8009496: 6ddb ldr r3, [r3, #92] @ 0x5c 8009498: f003 031f and.w r3, r3, #31 800949c: 2204 movs r2, #4 800949e: 409a lsls r2, r3 80094a0: 69bb ldr r3, [r7, #24] 80094a2: 4013 ands r3, r2 80094a4: 2b00 cmp r3, #0 80094a6: f000 808f beq.w 80095c8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 80094aa: 687b ldr r3, [r7, #4] 80094ac: 681b ldr r3, [r3, #0] 80094ae: 4a2c ldr r2, [pc, #176] @ (8009560 ) 80094b0: 4293 cmp r3, r2 80094b2: d04a beq.n 800954a 80094b4: 687b ldr r3, [r7, #4] 80094b6: 681b ldr r3, [r3, #0] 80094b8: 4a2a ldr r2, [pc, #168] @ (8009564 ) 80094ba: 4293 cmp r3, r2 80094bc: d045 beq.n 800954a 80094be: 687b ldr r3, [r7, #4] 80094c0: 681b ldr r3, [r3, #0] 80094c2: 4a29 ldr r2, [pc, #164] @ (8009568 ) 80094c4: 4293 cmp r3, r2 80094c6: d040 beq.n 800954a 80094c8: 687b ldr r3, [r7, #4] 80094ca: 681b ldr r3, [r3, #0] 80094cc: 4a27 ldr r2, [pc, #156] @ (800956c ) 80094ce: 4293 cmp r3, r2 80094d0: d03b beq.n 800954a 80094d2: 687b ldr r3, [r7, #4] 80094d4: 681b ldr r3, [r3, #0] 80094d6: 4a26 ldr r2, [pc, #152] @ (8009570 ) 80094d8: 4293 cmp r3, r2 80094da: d036 beq.n 800954a 80094dc: 687b ldr r3, [r7, #4] 80094de: 681b ldr r3, [r3, #0] 80094e0: 4a24 ldr r2, [pc, #144] @ (8009574 ) 80094e2: 4293 cmp r3, r2 80094e4: d031 beq.n 800954a 80094e6: 687b ldr r3, [r7, #4] 80094e8: 681b ldr r3, [r3, #0] 80094ea: 4a23 ldr r2, [pc, #140] @ (8009578 ) 80094ec: 4293 cmp r3, r2 80094ee: d02c beq.n 800954a 80094f0: 687b ldr r3, [r7, #4] 80094f2: 681b ldr r3, [r3, #0] 80094f4: 4a21 ldr r2, [pc, #132] @ (800957c ) 80094f6: 4293 cmp r3, r2 80094f8: d027 beq.n 800954a 80094fa: 687b ldr r3, [r7, #4] 80094fc: 681b ldr r3, [r3, #0] 80094fe: 4a20 ldr r2, [pc, #128] @ (8009580 ) 8009500: 4293 cmp r3, r2 8009502: d022 beq.n 800954a 8009504: 687b ldr r3, [r7, #4] 8009506: 681b ldr r3, [r3, #0] 8009508: 4a1e ldr r2, [pc, #120] @ (8009584 ) 800950a: 4293 cmp r3, r2 800950c: d01d beq.n 800954a 800950e: 687b ldr r3, [r7, #4] 8009510: 681b ldr r3, [r3, #0] 8009512: 4a1d ldr r2, [pc, #116] @ (8009588 ) 8009514: 4293 cmp r3, r2 8009516: d018 beq.n 800954a 8009518: 687b ldr r3, [r7, #4] 800951a: 681b ldr r3, [r3, #0] 800951c: 4a1b ldr r2, [pc, #108] @ (800958c ) 800951e: 4293 cmp r3, r2 8009520: d013 beq.n 800954a 8009522: 687b ldr r3, [r7, #4] 8009524: 681b ldr r3, [r3, #0] 8009526: 4a1a ldr r2, [pc, #104] @ (8009590 ) 8009528: 4293 cmp r3, r2 800952a: d00e beq.n 800954a 800952c: 687b ldr r3, [r7, #4] 800952e: 681b ldr r3, [r3, #0] 8009530: 4a18 ldr r2, [pc, #96] @ (8009594 ) 8009532: 4293 cmp r3, r2 8009534: d009 beq.n 800954a 8009536: 687b ldr r3, [r7, #4] 8009538: 681b ldr r3, [r3, #0] 800953a: 4a17 ldr r2, [pc, #92] @ (8009598 ) 800953c: 4293 cmp r3, r2 800953e: d004 beq.n 800954a 8009540: 687b ldr r3, [r7, #4] 8009542: 681b ldr r3, [r3, #0] 8009544: 4a15 ldr r2, [pc, #84] @ (800959c ) 8009546: 4293 cmp r3, r2 8009548: d12a bne.n 80095a0 800954a: 687b ldr r3, [r7, #4] 800954c: 681b ldr r3, [r3, #0] 800954e: 681b ldr r3, [r3, #0] 8009550: f003 0302 and.w r3, r3, #2 8009554: 2b00 cmp r3, #0 8009556: bf14 ite ne 8009558: 2301 movne r3, #1 800955a: 2300 moveq r3, #0 800955c: b2db uxtb r3, r3 800955e: e023 b.n 80095a8 8009560: 40020010 .word 0x40020010 8009564: 40020028 .word 0x40020028 8009568: 40020040 .word 0x40020040 800956c: 40020058 .word 0x40020058 8009570: 40020070 .word 0x40020070 8009574: 40020088 .word 0x40020088 8009578: 400200a0 .word 0x400200a0 800957c: 400200b8 .word 0x400200b8 8009580: 40020410 .word 0x40020410 8009584: 40020428 .word 0x40020428 8009588: 40020440 .word 0x40020440 800958c: 40020458 .word 0x40020458 8009590: 40020470 .word 0x40020470 8009594: 40020488 .word 0x40020488 8009598: 400204a0 .word 0x400204a0 800959c: 400204b8 .word 0x400204b8 80095a0: 687b ldr r3, [r7, #4] 80095a2: 681b ldr r3, [r3, #0] 80095a4: 681b ldr r3, [r3, #0] 80095a6: 2300 movs r3, #0 80095a8: 2b00 cmp r3, #0 80095aa: d00d beq.n 80095c8 { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 80095ac: 687b ldr r3, [r7, #4] 80095ae: 6ddb ldr r3, [r3, #92] @ 0x5c 80095b0: f003 031f and.w r3, r3, #31 80095b4: 2204 movs r2, #4 80095b6: 409a lsls r2, r3 80095b8: 6a3b ldr r3, [r7, #32] 80095ba: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 80095bc: 687b ldr r3, [r7, #4] 80095be: 6d5b ldr r3, [r3, #84] @ 0x54 80095c0: f043 0204 orr.w r2, r3, #4 80095c4: 687b ldr r3, [r7, #4] 80095c6: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 80095c8: 687b ldr r3, [r7, #4] 80095ca: 6ddb ldr r3, [r3, #92] @ 0x5c 80095cc: f003 031f and.w r3, r3, #31 80095d0: 2210 movs r2, #16 80095d2: 409a lsls r2, r3 80095d4: 69bb ldr r3, [r7, #24] 80095d6: 4013 ands r3, r2 80095d8: 2b00 cmp r3, #0 80095da: f000 80a6 beq.w 800972a { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 80095de: 687b ldr r3, [r7, #4] 80095e0: 681b ldr r3, [r3, #0] 80095e2: 4a85 ldr r2, [pc, #532] @ (80097f8 ) 80095e4: 4293 cmp r3, r2 80095e6: d04a beq.n 800967e 80095e8: 687b ldr r3, [r7, #4] 80095ea: 681b ldr r3, [r3, #0] 80095ec: 4a83 ldr r2, [pc, #524] @ (80097fc ) 80095ee: 4293 cmp r3, r2 80095f0: d045 beq.n 800967e 80095f2: 687b ldr r3, [r7, #4] 80095f4: 681b ldr r3, [r3, #0] 80095f6: 4a82 ldr r2, [pc, #520] @ (8009800 ) 80095f8: 4293 cmp r3, r2 80095fa: d040 beq.n 800967e 80095fc: 687b ldr r3, [r7, #4] 80095fe: 681b ldr r3, [r3, #0] 8009600: 4a80 ldr r2, [pc, #512] @ (8009804 ) 8009602: 4293 cmp r3, r2 8009604: d03b beq.n 800967e 8009606: 687b ldr r3, [r7, #4] 8009608: 681b ldr r3, [r3, #0] 800960a: 4a7f ldr r2, [pc, #508] @ (8009808 ) 800960c: 4293 cmp r3, r2 800960e: d036 beq.n 800967e 8009610: 687b ldr r3, [r7, #4] 8009612: 681b ldr r3, [r3, #0] 8009614: 4a7d ldr r2, [pc, #500] @ (800980c ) 8009616: 4293 cmp r3, r2 8009618: d031 beq.n 800967e 800961a: 687b ldr r3, [r7, #4] 800961c: 681b ldr r3, [r3, #0] 800961e: 4a7c ldr r2, [pc, #496] @ (8009810 ) 8009620: 4293 cmp r3, r2 8009622: d02c beq.n 800967e 8009624: 687b ldr r3, [r7, #4] 8009626: 681b ldr r3, [r3, #0] 8009628: 4a7a ldr r2, [pc, #488] @ (8009814 ) 800962a: 4293 cmp r3, r2 800962c: d027 beq.n 800967e 800962e: 687b ldr r3, [r7, #4] 8009630: 681b ldr r3, [r3, #0] 8009632: 4a79 ldr r2, [pc, #484] @ (8009818 ) 8009634: 4293 cmp r3, r2 8009636: d022 beq.n 800967e 8009638: 687b ldr r3, [r7, #4] 800963a: 681b ldr r3, [r3, #0] 800963c: 4a77 ldr r2, [pc, #476] @ (800981c ) 800963e: 4293 cmp r3, r2 8009640: d01d beq.n 800967e 8009642: 687b ldr r3, [r7, #4] 8009644: 681b ldr r3, [r3, #0] 8009646: 4a76 ldr r2, [pc, #472] @ (8009820 ) 8009648: 4293 cmp r3, r2 800964a: d018 beq.n 800967e 800964c: 687b ldr r3, [r7, #4] 800964e: 681b ldr r3, [r3, #0] 8009650: 4a74 ldr r2, [pc, #464] @ (8009824 ) 8009652: 4293 cmp r3, r2 8009654: d013 beq.n 800967e 8009656: 687b ldr r3, [r7, #4] 8009658: 681b ldr r3, [r3, #0] 800965a: 4a73 ldr r2, [pc, #460] @ (8009828 ) 800965c: 4293 cmp r3, r2 800965e: d00e beq.n 800967e 8009660: 687b ldr r3, [r7, #4] 8009662: 681b ldr r3, [r3, #0] 8009664: 4a71 ldr r2, [pc, #452] @ (800982c ) 8009666: 4293 cmp r3, r2 8009668: d009 beq.n 800967e 800966a: 687b ldr r3, [r7, #4] 800966c: 681b ldr r3, [r3, #0] 800966e: 4a70 ldr r2, [pc, #448] @ (8009830 ) 8009670: 4293 cmp r3, r2 8009672: d004 beq.n 800967e 8009674: 687b ldr r3, [r7, #4] 8009676: 681b ldr r3, [r3, #0] 8009678: 4a6e ldr r2, [pc, #440] @ (8009834 ) 800967a: 4293 cmp r3, r2 800967c: d10a bne.n 8009694 800967e: 687b ldr r3, [r7, #4] 8009680: 681b ldr r3, [r3, #0] 8009682: 681b ldr r3, [r3, #0] 8009684: f003 0308 and.w r3, r3, #8 8009688: 2b00 cmp r3, #0 800968a: bf14 ite ne 800968c: 2301 movne r3, #1 800968e: 2300 moveq r3, #0 8009690: b2db uxtb r3, r3 8009692: e009 b.n 80096a8 8009694: 687b ldr r3, [r7, #4] 8009696: 681b ldr r3, [r3, #0] 8009698: 681b ldr r3, [r3, #0] 800969a: f003 0304 and.w r3, r3, #4 800969e: 2b00 cmp r3, #0 80096a0: bf14 ite ne 80096a2: 2301 movne r3, #1 80096a4: 2300 moveq r3, #0 80096a6: b2db uxtb r3, r3 80096a8: 2b00 cmp r3, #0 80096aa: d03e beq.n 800972a { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 80096ac: 687b ldr r3, [r7, #4] 80096ae: 6ddb ldr r3, [r3, #92] @ 0x5c 80096b0: f003 031f and.w r3, r3, #31 80096b4: 2210 movs r2, #16 80096b6: 409a lsls r2, r3 80096b8: 6a3b ldr r3, [r7, #32] 80096ba: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 80096bc: 687b ldr r3, [r7, #4] 80096be: 681b ldr r3, [r3, #0] 80096c0: 681b ldr r3, [r3, #0] 80096c2: f403 2380 and.w r3, r3, #262144 @ 0x40000 80096c6: 2b00 cmp r3, #0 80096c8: d018 beq.n 80096fc { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 80096ca: 687b ldr r3, [r7, #4] 80096cc: 681b ldr r3, [r3, #0] 80096ce: 681b ldr r3, [r3, #0] 80096d0: f403 2300 and.w r3, r3, #524288 @ 0x80000 80096d4: 2b00 cmp r3, #0 80096d6: d108 bne.n 80096ea { if(hdma->XferHalfCpltCallback != NULL) 80096d8: 687b ldr r3, [r7, #4] 80096da: 6c1b ldr r3, [r3, #64] @ 0x40 80096dc: 2b00 cmp r3, #0 80096de: d024 beq.n 800972a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80096e0: 687b ldr r3, [r7, #4] 80096e2: 6c1b ldr r3, [r3, #64] @ 0x40 80096e4: 6878 ldr r0, [r7, #4] 80096e6: 4798 blx r3 80096e8: e01f b.n 800972a } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 80096ea: 687b ldr r3, [r7, #4] 80096ec: 6c9b ldr r3, [r3, #72] @ 0x48 80096ee: 2b00 cmp r3, #0 80096f0: d01b beq.n 800972a { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 80096f2: 687b ldr r3, [r7, #4] 80096f4: 6c9b ldr r3, [r3, #72] @ 0x48 80096f6: 6878 ldr r0, [r7, #4] 80096f8: 4798 blx r3 80096fa: e016 b.n 800972a } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 80096fc: 687b ldr r3, [r7, #4] 80096fe: 681b ldr r3, [r3, #0] 8009700: 681b ldr r3, [r3, #0] 8009702: f403 7380 and.w r3, r3, #256 @ 0x100 8009706: 2b00 cmp r3, #0 8009708: d107 bne.n 800971a { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800970a: 687b ldr r3, [r7, #4] 800970c: 681b ldr r3, [r3, #0] 800970e: 681a ldr r2, [r3, #0] 8009710: 687b ldr r3, [r7, #4] 8009712: 681b ldr r3, [r3, #0] 8009714: f022 0208 bic.w r2, r2, #8 8009718: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800971a: 687b ldr r3, [r7, #4] 800971c: 6c1b ldr r3, [r3, #64] @ 0x40 800971e: 2b00 cmp r3, #0 8009720: d003 beq.n 800972a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8009722: 687b ldr r3, [r7, #4] 8009724: 6c1b ldr r3, [r3, #64] @ 0x40 8009726: 6878 ldr r0, [r7, #4] 8009728: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800972a: 687b ldr r3, [r7, #4] 800972c: 6ddb ldr r3, [r3, #92] @ 0x5c 800972e: f003 031f and.w r3, r3, #31 8009732: 2220 movs r2, #32 8009734: 409a lsls r2, r3 8009736: 69bb ldr r3, [r7, #24] 8009738: 4013 ands r3, r2 800973a: 2b00 cmp r3, #0 800973c: f000 8110 beq.w 8009960 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 8009740: 687b ldr r3, [r7, #4] 8009742: 681b ldr r3, [r3, #0] 8009744: 4a2c ldr r2, [pc, #176] @ (80097f8 ) 8009746: 4293 cmp r3, r2 8009748: d04a beq.n 80097e0 800974a: 687b ldr r3, [r7, #4] 800974c: 681b ldr r3, [r3, #0] 800974e: 4a2b ldr r2, [pc, #172] @ (80097fc ) 8009750: 4293 cmp r3, r2 8009752: d045 beq.n 80097e0 8009754: 687b ldr r3, [r7, #4] 8009756: 681b ldr r3, [r3, #0] 8009758: 4a29 ldr r2, [pc, #164] @ (8009800 ) 800975a: 4293 cmp r3, r2 800975c: d040 beq.n 80097e0 800975e: 687b ldr r3, [r7, #4] 8009760: 681b ldr r3, [r3, #0] 8009762: 4a28 ldr r2, [pc, #160] @ (8009804 ) 8009764: 4293 cmp r3, r2 8009766: d03b beq.n 80097e0 8009768: 687b ldr r3, [r7, #4] 800976a: 681b ldr r3, [r3, #0] 800976c: 4a26 ldr r2, [pc, #152] @ (8009808 ) 800976e: 4293 cmp r3, r2 8009770: d036 beq.n 80097e0 8009772: 687b ldr r3, [r7, #4] 8009774: 681b ldr r3, [r3, #0] 8009776: 4a25 ldr r2, [pc, #148] @ (800980c ) 8009778: 4293 cmp r3, r2 800977a: d031 beq.n 80097e0 800977c: 687b ldr r3, [r7, #4] 800977e: 681b ldr r3, [r3, #0] 8009780: 4a23 ldr r2, [pc, #140] @ (8009810 ) 8009782: 4293 cmp r3, r2 8009784: d02c beq.n 80097e0 8009786: 687b ldr r3, [r7, #4] 8009788: 681b ldr r3, [r3, #0] 800978a: 4a22 ldr r2, [pc, #136] @ (8009814 ) 800978c: 4293 cmp r3, r2 800978e: d027 beq.n 80097e0 8009790: 687b ldr r3, [r7, #4] 8009792: 681b ldr r3, [r3, #0] 8009794: 4a20 ldr r2, [pc, #128] @ (8009818 ) 8009796: 4293 cmp r3, r2 8009798: d022 beq.n 80097e0 800979a: 687b ldr r3, [r7, #4] 800979c: 681b ldr r3, [r3, #0] 800979e: 4a1f ldr r2, [pc, #124] @ (800981c ) 80097a0: 4293 cmp r3, r2 80097a2: d01d beq.n 80097e0 80097a4: 687b ldr r3, [r7, #4] 80097a6: 681b ldr r3, [r3, #0] 80097a8: 4a1d ldr r2, [pc, #116] @ (8009820 ) 80097aa: 4293 cmp r3, r2 80097ac: d018 beq.n 80097e0 80097ae: 687b ldr r3, [r7, #4] 80097b0: 681b ldr r3, [r3, #0] 80097b2: 4a1c ldr r2, [pc, #112] @ (8009824 ) 80097b4: 4293 cmp r3, r2 80097b6: d013 beq.n 80097e0 80097b8: 687b ldr r3, [r7, #4] 80097ba: 681b ldr r3, [r3, #0] 80097bc: 4a1a ldr r2, [pc, #104] @ (8009828 ) 80097be: 4293 cmp r3, r2 80097c0: d00e beq.n 80097e0 80097c2: 687b ldr r3, [r7, #4] 80097c4: 681b ldr r3, [r3, #0] 80097c6: 4a19 ldr r2, [pc, #100] @ (800982c ) 80097c8: 4293 cmp r3, r2 80097ca: d009 beq.n 80097e0 80097cc: 687b ldr r3, [r7, #4] 80097ce: 681b ldr r3, [r3, #0] 80097d0: 4a17 ldr r2, [pc, #92] @ (8009830 ) 80097d2: 4293 cmp r3, r2 80097d4: d004 beq.n 80097e0 80097d6: 687b ldr r3, [r7, #4] 80097d8: 681b ldr r3, [r3, #0] 80097da: 4a16 ldr r2, [pc, #88] @ (8009834 ) 80097dc: 4293 cmp r3, r2 80097de: d12b bne.n 8009838 80097e0: 687b ldr r3, [r7, #4] 80097e2: 681b ldr r3, [r3, #0] 80097e4: 681b ldr r3, [r3, #0] 80097e6: f003 0310 and.w r3, r3, #16 80097ea: 2b00 cmp r3, #0 80097ec: bf14 ite ne 80097ee: 2301 movne r3, #1 80097f0: 2300 moveq r3, #0 80097f2: b2db uxtb r3, r3 80097f4: e02a b.n 800984c 80097f6: bf00 nop 80097f8: 40020010 .word 0x40020010 80097fc: 40020028 .word 0x40020028 8009800: 40020040 .word 0x40020040 8009804: 40020058 .word 0x40020058 8009808: 40020070 .word 0x40020070 800980c: 40020088 .word 0x40020088 8009810: 400200a0 .word 0x400200a0 8009814: 400200b8 .word 0x400200b8 8009818: 40020410 .word 0x40020410 800981c: 40020428 .word 0x40020428 8009820: 40020440 .word 0x40020440 8009824: 40020458 .word 0x40020458 8009828: 40020470 .word 0x40020470 800982c: 40020488 .word 0x40020488 8009830: 400204a0 .word 0x400204a0 8009834: 400204b8 .word 0x400204b8 8009838: 687b ldr r3, [r7, #4] 800983a: 681b ldr r3, [r3, #0] 800983c: 681b ldr r3, [r3, #0] 800983e: f003 0302 and.w r3, r3, #2 8009842: 2b00 cmp r3, #0 8009844: bf14 ite ne 8009846: 2301 movne r3, #1 8009848: 2300 moveq r3, #0 800984a: b2db uxtb r3, r3 800984c: 2b00 cmp r3, #0 800984e: f000 8087 beq.w 8009960 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 8009852: 687b ldr r3, [r7, #4] 8009854: 6ddb ldr r3, [r3, #92] @ 0x5c 8009856: f003 031f and.w r3, r3, #31 800985a: 2220 movs r2, #32 800985c: 409a lsls r2, r3 800985e: 6a3b ldr r3, [r7, #32] 8009860: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 8009862: 687b ldr r3, [r7, #4] 8009864: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8009868: b2db uxtb r3, r3 800986a: 2b04 cmp r3, #4 800986c: d139 bne.n 80098e2 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800986e: 687b ldr r3, [r7, #4] 8009870: 681b ldr r3, [r3, #0] 8009872: 681a ldr r2, [r3, #0] 8009874: 687b ldr r3, [r7, #4] 8009876: 681b ldr r3, [r3, #0] 8009878: f022 0216 bic.w r2, r2, #22 800987c: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800987e: 687b ldr r3, [r7, #4] 8009880: 681b ldr r3, [r3, #0] 8009882: 695a ldr r2, [r3, #20] 8009884: 687b ldr r3, [r7, #4] 8009886: 681b ldr r3, [r3, #0] 8009888: f022 0280 bic.w r2, r2, #128 @ 0x80 800988c: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800988e: 687b ldr r3, [r7, #4] 8009890: 6c1b ldr r3, [r3, #64] @ 0x40 8009892: 2b00 cmp r3, #0 8009894: d103 bne.n 800989e 8009896: 687b ldr r3, [r7, #4] 8009898: 6c9b ldr r3, [r3, #72] @ 0x48 800989a: 2b00 cmp r3, #0 800989c: d007 beq.n 80098ae { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800989e: 687b ldr r3, [r7, #4] 80098a0: 681b ldr r3, [r3, #0] 80098a2: 681a ldr r2, [r3, #0] 80098a4: 687b ldr r3, [r7, #4] 80098a6: 681b ldr r3, [r3, #0] 80098a8: f022 0208 bic.w r2, r2, #8 80098ac: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 80098ae: 687b ldr r3, [r7, #4] 80098b0: 6ddb ldr r3, [r3, #92] @ 0x5c 80098b2: f003 031f and.w r3, r3, #31 80098b6: 223f movs r2, #63 @ 0x3f 80098b8: 409a lsls r2, r3 80098ba: 6a3b ldr r3, [r7, #32] 80098bc: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80098be: 687b ldr r3, [r7, #4] 80098c0: 2201 movs r2, #1 80098c2: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80098c6: 687b ldr r3, [r7, #4] 80098c8: 2200 movs r2, #0 80098ca: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 80098ce: 687b ldr r3, [r7, #4] 80098d0: 6d1b ldr r3, [r3, #80] @ 0x50 80098d2: 2b00 cmp r3, #0 80098d4: f000 834a beq.w 8009f6c { hdma->XferAbortCallback(hdma); 80098d8: 687b ldr r3, [r7, #4] 80098da: 6d1b ldr r3, [r3, #80] @ 0x50 80098dc: 6878 ldr r0, [r7, #4] 80098de: 4798 blx r3 } return; 80098e0: e344 b.n 8009f6c } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 80098e2: 687b ldr r3, [r7, #4] 80098e4: 681b ldr r3, [r3, #0] 80098e6: 681b ldr r3, [r3, #0] 80098e8: f403 2380 and.w r3, r3, #262144 @ 0x40000 80098ec: 2b00 cmp r3, #0 80098ee: d018 beq.n 8009922 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 80098f0: 687b ldr r3, [r7, #4] 80098f2: 681b ldr r3, [r3, #0] 80098f4: 681b ldr r3, [r3, #0] 80098f6: f403 2300 and.w r3, r3, #524288 @ 0x80000 80098fa: 2b00 cmp r3, #0 80098fc: d108 bne.n 8009910 { if(hdma->XferM1CpltCallback != NULL) 80098fe: 687b ldr r3, [r7, #4] 8009900: 6c5b ldr r3, [r3, #68] @ 0x44 8009902: 2b00 cmp r3, #0 8009904: d02c beq.n 8009960 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 8009906: 687b ldr r3, [r7, #4] 8009908: 6c5b ldr r3, [r3, #68] @ 0x44 800990a: 6878 ldr r0, [r7, #4] 800990c: 4798 blx r3 800990e: e027 b.n 8009960 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8009910: 687b ldr r3, [r7, #4] 8009912: 6bdb ldr r3, [r3, #60] @ 0x3c 8009914: 2b00 cmp r3, #0 8009916: d023 beq.n 8009960 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 8009918: 687b ldr r3, [r7, #4] 800991a: 6bdb ldr r3, [r3, #60] @ 0x3c 800991c: 6878 ldr r0, [r7, #4] 800991e: 4798 blx r3 8009920: e01e b.n 8009960 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 8009922: 687b ldr r3, [r7, #4] 8009924: 681b ldr r3, [r3, #0] 8009926: 681b ldr r3, [r3, #0] 8009928: f403 7380 and.w r3, r3, #256 @ 0x100 800992c: 2b00 cmp r3, #0 800992e: d10f bne.n 8009950 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 8009930: 687b ldr r3, [r7, #4] 8009932: 681b ldr r3, [r3, #0] 8009934: 681a ldr r2, [r3, #0] 8009936: 687b ldr r3, [r7, #4] 8009938: 681b ldr r3, [r3, #0] 800993a: f022 0210 bic.w r2, r2, #16 800993e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009940: 687b ldr r3, [r7, #4] 8009942: 2201 movs r2, #1 8009944: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009948: 687b ldr r3, [r7, #4] 800994a: 2200 movs r2, #0 800994c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 8009950: 687b ldr r3, [r7, #4] 8009952: 6bdb ldr r3, [r3, #60] @ 0x3c 8009954: 2b00 cmp r3, #0 8009956: d003 beq.n 8009960 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8009958: 687b ldr r3, [r7, #4] 800995a: 6bdb ldr r3, [r3, #60] @ 0x3c 800995c: 6878 ldr r0, [r7, #4] 800995e: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 8009960: 687b ldr r3, [r7, #4] 8009962: 6d5b ldr r3, [r3, #84] @ 0x54 8009964: 2b00 cmp r3, #0 8009966: f000 8306 beq.w 8009f76 { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800996a: 687b ldr r3, [r7, #4] 800996c: 6d5b ldr r3, [r3, #84] @ 0x54 800996e: f003 0301 and.w r3, r3, #1 8009972: 2b00 cmp r3, #0 8009974: f000 8088 beq.w 8009a88 { hdma->State = HAL_DMA_STATE_ABORT; 8009978: 687b ldr r3, [r7, #4] 800997a: 2204 movs r2, #4 800997c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8009980: 687b ldr r3, [r7, #4] 8009982: 681b ldr r3, [r3, #0] 8009984: 4a7a ldr r2, [pc, #488] @ (8009b70 ) 8009986: 4293 cmp r3, r2 8009988: d04a beq.n 8009a20 800998a: 687b ldr r3, [r7, #4] 800998c: 681b ldr r3, [r3, #0] 800998e: 4a79 ldr r2, [pc, #484] @ (8009b74 ) 8009990: 4293 cmp r3, r2 8009992: d045 beq.n 8009a20 8009994: 687b ldr r3, [r7, #4] 8009996: 681b ldr r3, [r3, #0] 8009998: 4a77 ldr r2, [pc, #476] @ (8009b78 ) 800999a: 4293 cmp r3, r2 800999c: d040 beq.n 8009a20 800999e: 687b ldr r3, [r7, #4] 80099a0: 681b ldr r3, [r3, #0] 80099a2: 4a76 ldr r2, [pc, #472] @ (8009b7c ) 80099a4: 4293 cmp r3, r2 80099a6: d03b beq.n 8009a20 80099a8: 687b ldr r3, [r7, #4] 80099aa: 681b ldr r3, [r3, #0] 80099ac: 4a74 ldr r2, [pc, #464] @ (8009b80 ) 80099ae: 4293 cmp r3, r2 80099b0: d036 beq.n 8009a20 80099b2: 687b ldr r3, [r7, #4] 80099b4: 681b ldr r3, [r3, #0] 80099b6: 4a73 ldr r2, [pc, #460] @ (8009b84 ) 80099b8: 4293 cmp r3, r2 80099ba: d031 beq.n 8009a20 80099bc: 687b ldr r3, [r7, #4] 80099be: 681b ldr r3, [r3, #0] 80099c0: 4a71 ldr r2, [pc, #452] @ (8009b88 ) 80099c2: 4293 cmp r3, r2 80099c4: d02c beq.n 8009a20 80099c6: 687b ldr r3, [r7, #4] 80099c8: 681b ldr r3, [r3, #0] 80099ca: 4a70 ldr r2, [pc, #448] @ (8009b8c ) 80099cc: 4293 cmp r3, r2 80099ce: d027 beq.n 8009a20 80099d0: 687b ldr r3, [r7, #4] 80099d2: 681b ldr r3, [r3, #0] 80099d4: 4a6e ldr r2, [pc, #440] @ (8009b90 ) 80099d6: 4293 cmp r3, r2 80099d8: d022 beq.n 8009a20 80099da: 687b ldr r3, [r7, #4] 80099dc: 681b ldr r3, [r3, #0] 80099de: 4a6d ldr r2, [pc, #436] @ (8009b94 ) 80099e0: 4293 cmp r3, r2 80099e2: d01d beq.n 8009a20 80099e4: 687b ldr r3, [r7, #4] 80099e6: 681b ldr r3, [r3, #0] 80099e8: 4a6b ldr r2, [pc, #428] @ (8009b98 ) 80099ea: 4293 cmp r3, r2 80099ec: d018 beq.n 8009a20 80099ee: 687b ldr r3, [r7, #4] 80099f0: 681b ldr r3, [r3, #0] 80099f2: 4a6a ldr r2, [pc, #424] @ (8009b9c ) 80099f4: 4293 cmp r3, r2 80099f6: d013 beq.n 8009a20 80099f8: 687b ldr r3, [r7, #4] 80099fa: 681b ldr r3, [r3, #0] 80099fc: 4a68 ldr r2, [pc, #416] @ (8009ba0 ) 80099fe: 4293 cmp r3, r2 8009a00: d00e beq.n 8009a20 8009a02: 687b ldr r3, [r7, #4] 8009a04: 681b ldr r3, [r3, #0] 8009a06: 4a67 ldr r2, [pc, #412] @ (8009ba4 ) 8009a08: 4293 cmp r3, r2 8009a0a: d009 beq.n 8009a20 8009a0c: 687b ldr r3, [r7, #4] 8009a0e: 681b ldr r3, [r3, #0] 8009a10: 4a65 ldr r2, [pc, #404] @ (8009ba8 ) 8009a12: 4293 cmp r3, r2 8009a14: d004 beq.n 8009a20 8009a16: 687b ldr r3, [r7, #4] 8009a18: 681b ldr r3, [r3, #0] 8009a1a: 4a64 ldr r2, [pc, #400] @ (8009bac ) 8009a1c: 4293 cmp r3, r2 8009a1e: d108 bne.n 8009a32 8009a20: 687b ldr r3, [r7, #4] 8009a22: 681b ldr r3, [r3, #0] 8009a24: 681a ldr r2, [r3, #0] 8009a26: 687b ldr r3, [r7, #4] 8009a28: 681b ldr r3, [r3, #0] 8009a2a: f022 0201 bic.w r2, r2, #1 8009a2e: 601a str r2, [r3, #0] 8009a30: e007 b.n 8009a42 8009a32: 687b ldr r3, [r7, #4] 8009a34: 681b ldr r3, [r3, #0] 8009a36: 681a ldr r2, [r3, #0] 8009a38: 687b ldr r3, [r7, #4] 8009a3a: 681b ldr r3, [r3, #0] 8009a3c: f022 0201 bic.w r2, r2, #1 8009a40: 601a str r2, [r3, #0] do { if (++count > timeout) 8009a42: 68fb ldr r3, [r7, #12] 8009a44: 3301 adds r3, #1 8009a46: 60fb str r3, [r7, #12] 8009a48: 6a7a ldr r2, [r7, #36] @ 0x24 8009a4a: 429a cmp r2, r3 8009a4c: d307 bcc.n 8009a5e { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 8009a4e: 687b ldr r3, [r7, #4] 8009a50: 681b ldr r3, [r3, #0] 8009a52: 681b ldr r3, [r3, #0] 8009a54: f003 0301 and.w r3, r3, #1 8009a58: 2b00 cmp r3, #0 8009a5a: d1f2 bne.n 8009a42 8009a5c: e000 b.n 8009a60 break; 8009a5e: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8009a60: 687b ldr r3, [r7, #4] 8009a62: 681b ldr r3, [r3, #0] 8009a64: 681b ldr r3, [r3, #0] 8009a66: f003 0301 and.w r3, r3, #1 8009a6a: 2b00 cmp r3, #0 8009a6c: d004 beq.n 8009a78 { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 8009a6e: 687b ldr r3, [r7, #4] 8009a70: 2203 movs r2, #3 8009a72: f883 2035 strb.w r2, [r3, #53] @ 0x35 8009a76: e003 b.n 8009a80 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 8009a78: 687b ldr r3, [r7, #4] 8009a7a: 2201 movs r2, #1 8009a7c: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009a80: 687b ldr r3, [r7, #4] 8009a82: 2200 movs r2, #0 8009a84: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 8009a88: 687b ldr r3, [r7, #4] 8009a8a: 6cdb ldr r3, [r3, #76] @ 0x4c 8009a8c: 2b00 cmp r3, #0 8009a8e: f000 8272 beq.w 8009f76 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8009a92: 687b ldr r3, [r7, #4] 8009a94: 6cdb ldr r3, [r3, #76] @ 0x4c 8009a96: 6878 ldr r0, [r7, #4] 8009a98: 4798 blx r3 8009a9a: e26c b.n 8009f76 } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8009a9c: 687b ldr r3, [r7, #4] 8009a9e: 681b ldr r3, [r3, #0] 8009aa0: 4a43 ldr r2, [pc, #268] @ (8009bb0 ) 8009aa2: 4293 cmp r3, r2 8009aa4: d022 beq.n 8009aec 8009aa6: 687b ldr r3, [r7, #4] 8009aa8: 681b ldr r3, [r3, #0] 8009aaa: 4a42 ldr r2, [pc, #264] @ (8009bb4 ) 8009aac: 4293 cmp r3, r2 8009aae: d01d beq.n 8009aec 8009ab0: 687b ldr r3, [r7, #4] 8009ab2: 681b ldr r3, [r3, #0] 8009ab4: 4a40 ldr r2, [pc, #256] @ (8009bb8 ) 8009ab6: 4293 cmp r3, r2 8009ab8: d018 beq.n 8009aec 8009aba: 687b ldr r3, [r7, #4] 8009abc: 681b ldr r3, [r3, #0] 8009abe: 4a3f ldr r2, [pc, #252] @ (8009bbc ) 8009ac0: 4293 cmp r3, r2 8009ac2: d013 beq.n 8009aec 8009ac4: 687b ldr r3, [r7, #4] 8009ac6: 681b ldr r3, [r3, #0] 8009ac8: 4a3d ldr r2, [pc, #244] @ (8009bc0 ) 8009aca: 4293 cmp r3, r2 8009acc: d00e beq.n 8009aec 8009ace: 687b ldr r3, [r7, #4] 8009ad0: 681b ldr r3, [r3, #0] 8009ad2: 4a3c ldr r2, [pc, #240] @ (8009bc4 ) 8009ad4: 4293 cmp r3, r2 8009ad6: d009 beq.n 8009aec 8009ad8: 687b ldr r3, [r7, #4] 8009ada: 681b ldr r3, [r3, #0] 8009adc: 4a3a ldr r2, [pc, #232] @ (8009bc8 ) 8009ade: 4293 cmp r3, r2 8009ae0: d004 beq.n 8009aec 8009ae2: 687b ldr r3, [r7, #4] 8009ae4: 681b ldr r3, [r3, #0] 8009ae6: 4a39 ldr r2, [pc, #228] @ (8009bcc ) 8009ae8: 4293 cmp r3, r2 8009aea: d101 bne.n 8009af0 8009aec: 2301 movs r3, #1 8009aee: e000 b.n 8009af2 8009af0: 2300 movs r3, #0 8009af2: 2b00 cmp r3, #0 8009af4: f000 823f beq.w 8009f76 { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 8009af8: 687b ldr r3, [r7, #4] 8009afa: 681b ldr r3, [r3, #0] 8009afc: 681b ldr r3, [r3, #0] 8009afe: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 8009b00: 687b ldr r3, [r7, #4] 8009b02: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b04: f003 031f and.w r3, r3, #31 8009b08: 2204 movs r2, #4 8009b0a: 409a lsls r2, r3 8009b0c: 697b ldr r3, [r7, #20] 8009b0e: 4013 ands r3, r2 8009b10: 2b00 cmp r3, #0 8009b12: f000 80cd beq.w 8009cb0 8009b16: 693b ldr r3, [r7, #16] 8009b18: f003 0304 and.w r3, r3, #4 8009b1c: 2b00 cmp r3, #0 8009b1e: f000 80c7 beq.w 8009cb0 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 8009b22: 687b ldr r3, [r7, #4] 8009b24: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b26: f003 031f and.w r3, r3, #31 8009b2a: 2204 movs r2, #4 8009b2c: 409a lsls r2, r3 8009b2e: 69fb ldr r3, [r7, #28] 8009b30: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009b32: 693b ldr r3, [r7, #16] 8009b34: f403 4300 and.w r3, r3, #32768 @ 0x8000 8009b38: 2b00 cmp r3, #0 8009b3a: d049 beq.n 8009bd0 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 8009b3c: 693b ldr r3, [r7, #16] 8009b3e: f403 3380 and.w r3, r3, #65536 @ 0x10000 8009b42: 2b00 cmp r3, #0 8009b44: d109 bne.n 8009b5a { if(hdma->XferM1HalfCpltCallback != NULL) 8009b46: 687b ldr r3, [r7, #4] 8009b48: 6c9b ldr r3, [r3, #72] @ 0x48 8009b4a: 2b00 cmp r3, #0 8009b4c: f000 8210 beq.w 8009f70 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 8009b50: 687b ldr r3, [r7, #4] 8009b52: 6c9b ldr r3, [r3, #72] @ 0x48 8009b54: 6878 ldr r0, [r7, #4] 8009b56: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009b58: e20a b.n 8009f70 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 8009b5a: 687b ldr r3, [r7, #4] 8009b5c: 6c1b ldr r3, [r3, #64] @ 0x40 8009b5e: 2b00 cmp r3, #0 8009b60: f000 8206 beq.w 8009f70 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 8009b64: 687b ldr r3, [r7, #4] 8009b66: 6c1b ldr r3, [r3, #64] @ 0x40 8009b68: 6878 ldr r0, [r7, #4] 8009b6a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009b6c: e200 b.n 8009f70 8009b6e: bf00 nop 8009b70: 40020010 .word 0x40020010 8009b74: 40020028 .word 0x40020028 8009b78: 40020040 .word 0x40020040 8009b7c: 40020058 .word 0x40020058 8009b80: 40020070 .word 0x40020070 8009b84: 40020088 .word 0x40020088 8009b88: 400200a0 .word 0x400200a0 8009b8c: 400200b8 .word 0x400200b8 8009b90: 40020410 .word 0x40020410 8009b94: 40020428 .word 0x40020428 8009b98: 40020440 .word 0x40020440 8009b9c: 40020458 .word 0x40020458 8009ba0: 40020470 .word 0x40020470 8009ba4: 40020488 .word 0x40020488 8009ba8: 400204a0 .word 0x400204a0 8009bac: 400204b8 .word 0x400204b8 8009bb0: 58025408 .word 0x58025408 8009bb4: 5802541c .word 0x5802541c 8009bb8: 58025430 .word 0x58025430 8009bbc: 58025444 .word 0x58025444 8009bc0: 58025458 .word 0x58025458 8009bc4: 5802546c .word 0x5802546c 8009bc8: 58025480 .word 0x58025480 8009bcc: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8009bd0: 693b ldr r3, [r7, #16] 8009bd2: f003 0320 and.w r3, r3, #32 8009bd6: 2b00 cmp r3, #0 8009bd8: d160 bne.n 8009c9c { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 8009bda: 687b ldr r3, [r7, #4] 8009bdc: 681b ldr r3, [r3, #0] 8009bde: 4a7f ldr r2, [pc, #508] @ (8009ddc ) 8009be0: 4293 cmp r3, r2 8009be2: d04a beq.n 8009c7a 8009be4: 687b ldr r3, [r7, #4] 8009be6: 681b ldr r3, [r3, #0] 8009be8: 4a7d ldr r2, [pc, #500] @ (8009de0 ) 8009bea: 4293 cmp r3, r2 8009bec: d045 beq.n 8009c7a 8009bee: 687b ldr r3, [r7, #4] 8009bf0: 681b ldr r3, [r3, #0] 8009bf2: 4a7c ldr r2, [pc, #496] @ (8009de4 ) 8009bf4: 4293 cmp r3, r2 8009bf6: d040 beq.n 8009c7a 8009bf8: 687b ldr r3, [r7, #4] 8009bfa: 681b ldr r3, [r3, #0] 8009bfc: 4a7a ldr r2, [pc, #488] @ (8009de8 ) 8009bfe: 4293 cmp r3, r2 8009c00: d03b beq.n 8009c7a 8009c02: 687b ldr r3, [r7, #4] 8009c04: 681b ldr r3, [r3, #0] 8009c06: 4a79 ldr r2, [pc, #484] @ (8009dec ) 8009c08: 4293 cmp r3, r2 8009c0a: d036 beq.n 8009c7a 8009c0c: 687b ldr r3, [r7, #4] 8009c0e: 681b ldr r3, [r3, #0] 8009c10: 4a77 ldr r2, [pc, #476] @ (8009df0 ) 8009c12: 4293 cmp r3, r2 8009c14: d031 beq.n 8009c7a 8009c16: 687b ldr r3, [r7, #4] 8009c18: 681b ldr r3, [r3, #0] 8009c1a: 4a76 ldr r2, [pc, #472] @ (8009df4 ) 8009c1c: 4293 cmp r3, r2 8009c1e: d02c beq.n 8009c7a 8009c20: 687b ldr r3, [r7, #4] 8009c22: 681b ldr r3, [r3, #0] 8009c24: 4a74 ldr r2, [pc, #464] @ (8009df8 ) 8009c26: 4293 cmp r3, r2 8009c28: d027 beq.n 8009c7a 8009c2a: 687b ldr r3, [r7, #4] 8009c2c: 681b ldr r3, [r3, #0] 8009c2e: 4a73 ldr r2, [pc, #460] @ (8009dfc ) 8009c30: 4293 cmp r3, r2 8009c32: d022 beq.n 8009c7a 8009c34: 687b ldr r3, [r7, #4] 8009c36: 681b ldr r3, [r3, #0] 8009c38: 4a71 ldr r2, [pc, #452] @ (8009e00 ) 8009c3a: 4293 cmp r3, r2 8009c3c: d01d beq.n 8009c7a 8009c3e: 687b ldr r3, [r7, #4] 8009c40: 681b ldr r3, [r3, #0] 8009c42: 4a70 ldr r2, [pc, #448] @ (8009e04 ) 8009c44: 4293 cmp r3, r2 8009c46: d018 beq.n 8009c7a 8009c48: 687b ldr r3, [r7, #4] 8009c4a: 681b ldr r3, [r3, #0] 8009c4c: 4a6e ldr r2, [pc, #440] @ (8009e08 ) 8009c4e: 4293 cmp r3, r2 8009c50: d013 beq.n 8009c7a 8009c52: 687b ldr r3, [r7, #4] 8009c54: 681b ldr r3, [r3, #0] 8009c56: 4a6d ldr r2, [pc, #436] @ (8009e0c ) 8009c58: 4293 cmp r3, r2 8009c5a: d00e beq.n 8009c7a 8009c5c: 687b ldr r3, [r7, #4] 8009c5e: 681b ldr r3, [r3, #0] 8009c60: 4a6b ldr r2, [pc, #428] @ (8009e10 ) 8009c62: 4293 cmp r3, r2 8009c64: d009 beq.n 8009c7a 8009c66: 687b ldr r3, [r7, #4] 8009c68: 681b ldr r3, [r3, #0] 8009c6a: 4a6a ldr r2, [pc, #424] @ (8009e14 ) 8009c6c: 4293 cmp r3, r2 8009c6e: d004 beq.n 8009c7a 8009c70: 687b ldr r3, [r7, #4] 8009c72: 681b ldr r3, [r3, #0] 8009c74: 4a68 ldr r2, [pc, #416] @ (8009e18 ) 8009c76: 4293 cmp r3, r2 8009c78: d108 bne.n 8009c8c 8009c7a: 687b ldr r3, [r7, #4] 8009c7c: 681b ldr r3, [r3, #0] 8009c7e: 681a ldr r2, [r3, #0] 8009c80: 687b ldr r3, [r7, #4] 8009c82: 681b ldr r3, [r3, #0] 8009c84: f022 0208 bic.w r2, r2, #8 8009c88: 601a str r2, [r3, #0] 8009c8a: e007 b.n 8009c9c 8009c8c: 687b ldr r3, [r7, #4] 8009c8e: 681b ldr r3, [r3, #0] 8009c90: 681a ldr r2, [r3, #0] 8009c92: 687b ldr r3, [r7, #4] 8009c94: 681b ldr r3, [r3, #0] 8009c96: f022 0204 bic.w r2, r2, #4 8009c9a: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 8009c9c: 687b ldr r3, [r7, #4] 8009c9e: 6c1b ldr r3, [r3, #64] @ 0x40 8009ca0: 2b00 cmp r3, #0 8009ca2: f000 8165 beq.w 8009f70 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 8009ca6: 687b ldr r3, [r7, #4] 8009ca8: 6c1b ldr r3, [r3, #64] @ 0x40 8009caa: 6878 ldr r0, [r7, #4] 8009cac: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009cae: e15f b.n 8009f70 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 8009cb0: 687b ldr r3, [r7, #4] 8009cb2: 6ddb ldr r3, [r3, #92] @ 0x5c 8009cb4: f003 031f and.w r3, r3, #31 8009cb8: 2202 movs r2, #2 8009cba: 409a lsls r2, r3 8009cbc: 697b ldr r3, [r7, #20] 8009cbe: 4013 ands r3, r2 8009cc0: 2b00 cmp r3, #0 8009cc2: f000 80c5 beq.w 8009e50 8009cc6: 693b ldr r3, [r7, #16] 8009cc8: f003 0302 and.w r3, r3, #2 8009ccc: 2b00 cmp r3, #0 8009cce: f000 80bf beq.w 8009e50 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 8009cd2: 687b ldr r3, [r7, #4] 8009cd4: 6ddb ldr r3, [r3, #92] @ 0x5c 8009cd6: f003 031f and.w r3, r3, #31 8009cda: 2202 movs r2, #2 8009cdc: 409a lsls r2, r3 8009cde: 69fb ldr r3, [r7, #28] 8009ce0: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009ce2: 693b ldr r3, [r7, #16] 8009ce4: f403 4300 and.w r3, r3, #32768 @ 0x8000 8009ce8: 2b00 cmp r3, #0 8009cea: d018 beq.n 8009d1e { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 8009cec: 693b ldr r3, [r7, #16] 8009cee: f403 3380 and.w r3, r3, #65536 @ 0x10000 8009cf2: 2b00 cmp r3, #0 8009cf4: d109 bne.n 8009d0a { if(hdma->XferM1CpltCallback != NULL) 8009cf6: 687b ldr r3, [r7, #4] 8009cf8: 6c5b ldr r3, [r3, #68] @ 0x44 8009cfa: 2b00 cmp r3, #0 8009cfc: f000 813a beq.w 8009f74 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 8009d00: 687b ldr r3, [r7, #4] 8009d02: 6c5b ldr r3, [r3, #68] @ 0x44 8009d04: 6878 ldr r0, [r7, #4] 8009d06: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009d08: e134 b.n 8009f74 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 8009d0a: 687b ldr r3, [r7, #4] 8009d0c: 6bdb ldr r3, [r3, #60] @ 0x3c 8009d0e: 2b00 cmp r3, #0 8009d10: f000 8130 beq.w 8009f74 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 8009d14: 687b ldr r3, [r7, #4] 8009d16: 6bdb ldr r3, [r3, #60] @ 0x3c 8009d18: 6878 ldr r0, [r7, #4] 8009d1a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009d1c: e12a b.n 8009f74 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 8009d1e: 693b ldr r3, [r7, #16] 8009d20: f003 0320 and.w r3, r3, #32 8009d24: 2b00 cmp r3, #0 8009d26: f040 8089 bne.w 8009e3c { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 8009d2a: 687b ldr r3, [r7, #4] 8009d2c: 681b ldr r3, [r3, #0] 8009d2e: 4a2b ldr r2, [pc, #172] @ (8009ddc ) 8009d30: 4293 cmp r3, r2 8009d32: d04a beq.n 8009dca 8009d34: 687b ldr r3, [r7, #4] 8009d36: 681b ldr r3, [r3, #0] 8009d38: 4a29 ldr r2, [pc, #164] @ (8009de0 ) 8009d3a: 4293 cmp r3, r2 8009d3c: d045 beq.n 8009dca 8009d3e: 687b ldr r3, [r7, #4] 8009d40: 681b ldr r3, [r3, #0] 8009d42: 4a28 ldr r2, [pc, #160] @ (8009de4 ) 8009d44: 4293 cmp r3, r2 8009d46: d040 beq.n 8009dca 8009d48: 687b ldr r3, [r7, #4] 8009d4a: 681b ldr r3, [r3, #0] 8009d4c: 4a26 ldr r2, [pc, #152] @ (8009de8 ) 8009d4e: 4293 cmp r3, r2 8009d50: d03b beq.n 8009dca 8009d52: 687b ldr r3, [r7, #4] 8009d54: 681b ldr r3, [r3, #0] 8009d56: 4a25 ldr r2, [pc, #148] @ (8009dec ) 8009d58: 4293 cmp r3, r2 8009d5a: d036 beq.n 8009dca 8009d5c: 687b ldr r3, [r7, #4] 8009d5e: 681b ldr r3, [r3, #0] 8009d60: 4a23 ldr r2, [pc, #140] @ (8009df0 ) 8009d62: 4293 cmp r3, r2 8009d64: d031 beq.n 8009dca 8009d66: 687b ldr r3, [r7, #4] 8009d68: 681b ldr r3, [r3, #0] 8009d6a: 4a22 ldr r2, [pc, #136] @ (8009df4 ) 8009d6c: 4293 cmp r3, r2 8009d6e: d02c beq.n 8009dca 8009d70: 687b ldr r3, [r7, #4] 8009d72: 681b ldr r3, [r3, #0] 8009d74: 4a20 ldr r2, [pc, #128] @ (8009df8 ) 8009d76: 4293 cmp r3, r2 8009d78: d027 beq.n 8009dca 8009d7a: 687b ldr r3, [r7, #4] 8009d7c: 681b ldr r3, [r3, #0] 8009d7e: 4a1f ldr r2, [pc, #124] @ (8009dfc ) 8009d80: 4293 cmp r3, r2 8009d82: d022 beq.n 8009dca 8009d84: 687b ldr r3, [r7, #4] 8009d86: 681b ldr r3, [r3, #0] 8009d88: 4a1d ldr r2, [pc, #116] @ (8009e00 ) 8009d8a: 4293 cmp r3, r2 8009d8c: d01d beq.n 8009dca 8009d8e: 687b ldr r3, [r7, #4] 8009d90: 681b ldr r3, [r3, #0] 8009d92: 4a1c ldr r2, [pc, #112] @ (8009e04 ) 8009d94: 4293 cmp r3, r2 8009d96: d018 beq.n 8009dca 8009d98: 687b ldr r3, [r7, #4] 8009d9a: 681b ldr r3, [r3, #0] 8009d9c: 4a1a ldr r2, [pc, #104] @ (8009e08 ) 8009d9e: 4293 cmp r3, r2 8009da0: d013 beq.n 8009dca 8009da2: 687b ldr r3, [r7, #4] 8009da4: 681b ldr r3, [r3, #0] 8009da6: 4a19 ldr r2, [pc, #100] @ (8009e0c ) 8009da8: 4293 cmp r3, r2 8009daa: d00e beq.n 8009dca 8009dac: 687b ldr r3, [r7, #4] 8009dae: 681b ldr r3, [r3, #0] 8009db0: 4a17 ldr r2, [pc, #92] @ (8009e10 ) 8009db2: 4293 cmp r3, r2 8009db4: d009 beq.n 8009dca 8009db6: 687b ldr r3, [r7, #4] 8009db8: 681b ldr r3, [r3, #0] 8009dba: 4a16 ldr r2, [pc, #88] @ (8009e14 ) 8009dbc: 4293 cmp r3, r2 8009dbe: d004 beq.n 8009dca 8009dc0: 687b ldr r3, [r7, #4] 8009dc2: 681b ldr r3, [r3, #0] 8009dc4: 4a14 ldr r2, [pc, #80] @ (8009e18 ) 8009dc6: 4293 cmp r3, r2 8009dc8: d128 bne.n 8009e1c 8009dca: 687b ldr r3, [r7, #4] 8009dcc: 681b ldr r3, [r3, #0] 8009dce: 681a ldr r2, [r3, #0] 8009dd0: 687b ldr r3, [r7, #4] 8009dd2: 681b ldr r3, [r3, #0] 8009dd4: f022 0214 bic.w r2, r2, #20 8009dd8: 601a str r2, [r3, #0] 8009dda: e027 b.n 8009e2c 8009ddc: 40020010 .word 0x40020010 8009de0: 40020028 .word 0x40020028 8009de4: 40020040 .word 0x40020040 8009de8: 40020058 .word 0x40020058 8009dec: 40020070 .word 0x40020070 8009df0: 40020088 .word 0x40020088 8009df4: 400200a0 .word 0x400200a0 8009df8: 400200b8 .word 0x400200b8 8009dfc: 40020410 .word 0x40020410 8009e00: 40020428 .word 0x40020428 8009e04: 40020440 .word 0x40020440 8009e08: 40020458 .word 0x40020458 8009e0c: 40020470 .word 0x40020470 8009e10: 40020488 .word 0x40020488 8009e14: 400204a0 .word 0x400204a0 8009e18: 400204b8 .word 0x400204b8 8009e1c: 687b ldr r3, [r7, #4] 8009e1e: 681b ldr r3, [r3, #0] 8009e20: 681a ldr r2, [r3, #0] 8009e22: 687b ldr r3, [r7, #4] 8009e24: 681b ldr r3, [r3, #0] 8009e26: f022 020a bic.w r2, r2, #10 8009e2a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009e2c: 687b ldr r3, [r7, #4] 8009e2e: 2201 movs r2, #1 8009e30: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009e34: 687b ldr r3, [r7, #4] 8009e36: 2200 movs r2, #0 8009e38: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 8009e3c: 687b ldr r3, [r7, #4] 8009e3e: 6bdb ldr r3, [r3, #60] @ 0x3c 8009e40: 2b00 cmp r3, #0 8009e42: f000 8097 beq.w 8009f74 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8009e46: 687b ldr r3, [r7, #4] 8009e48: 6bdb ldr r3, [r3, #60] @ 0x3c 8009e4a: 6878 ldr r0, [r7, #4] 8009e4c: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009e4e: e091 b.n 8009f74 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 8009e50: 687b ldr r3, [r7, #4] 8009e52: 6ddb ldr r3, [r3, #92] @ 0x5c 8009e54: f003 031f and.w r3, r3, #31 8009e58: 2208 movs r2, #8 8009e5a: 409a lsls r2, r3 8009e5c: 697b ldr r3, [r7, #20] 8009e5e: 4013 ands r3, r2 8009e60: 2b00 cmp r3, #0 8009e62: f000 8088 beq.w 8009f76 8009e66: 693b ldr r3, [r7, #16] 8009e68: f003 0308 and.w r3, r3, #8 8009e6c: 2b00 cmp r3, #0 8009e6e: f000 8082 beq.w 8009f76 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8009e72: 687b ldr r3, [r7, #4] 8009e74: 681b ldr r3, [r3, #0] 8009e76: 4a41 ldr r2, [pc, #260] @ (8009f7c ) 8009e78: 4293 cmp r3, r2 8009e7a: d04a beq.n 8009f12 8009e7c: 687b ldr r3, [r7, #4] 8009e7e: 681b ldr r3, [r3, #0] 8009e80: 4a3f ldr r2, [pc, #252] @ (8009f80 ) 8009e82: 4293 cmp r3, r2 8009e84: d045 beq.n 8009f12 8009e86: 687b ldr r3, [r7, #4] 8009e88: 681b ldr r3, [r3, #0] 8009e8a: 4a3e ldr r2, [pc, #248] @ (8009f84 ) 8009e8c: 4293 cmp r3, r2 8009e8e: d040 beq.n 8009f12 8009e90: 687b ldr r3, [r7, #4] 8009e92: 681b ldr r3, [r3, #0] 8009e94: 4a3c ldr r2, [pc, #240] @ (8009f88 ) 8009e96: 4293 cmp r3, r2 8009e98: d03b beq.n 8009f12 8009e9a: 687b ldr r3, [r7, #4] 8009e9c: 681b ldr r3, [r3, #0] 8009e9e: 4a3b ldr r2, [pc, #236] @ (8009f8c ) 8009ea0: 4293 cmp r3, r2 8009ea2: d036 beq.n 8009f12 8009ea4: 687b ldr r3, [r7, #4] 8009ea6: 681b ldr r3, [r3, #0] 8009ea8: 4a39 ldr r2, [pc, #228] @ (8009f90 ) 8009eaa: 4293 cmp r3, r2 8009eac: d031 beq.n 8009f12 8009eae: 687b ldr r3, [r7, #4] 8009eb0: 681b ldr r3, [r3, #0] 8009eb2: 4a38 ldr r2, [pc, #224] @ (8009f94 ) 8009eb4: 4293 cmp r3, r2 8009eb6: d02c beq.n 8009f12 8009eb8: 687b ldr r3, [r7, #4] 8009eba: 681b ldr r3, [r3, #0] 8009ebc: 4a36 ldr r2, [pc, #216] @ (8009f98 ) 8009ebe: 4293 cmp r3, r2 8009ec0: d027 beq.n 8009f12 8009ec2: 687b ldr r3, [r7, #4] 8009ec4: 681b ldr r3, [r3, #0] 8009ec6: 4a35 ldr r2, [pc, #212] @ (8009f9c ) 8009ec8: 4293 cmp r3, r2 8009eca: d022 beq.n 8009f12 8009ecc: 687b ldr r3, [r7, #4] 8009ece: 681b ldr r3, [r3, #0] 8009ed0: 4a33 ldr r2, [pc, #204] @ (8009fa0 ) 8009ed2: 4293 cmp r3, r2 8009ed4: d01d beq.n 8009f12 8009ed6: 687b ldr r3, [r7, #4] 8009ed8: 681b ldr r3, [r3, #0] 8009eda: 4a32 ldr r2, [pc, #200] @ (8009fa4 ) 8009edc: 4293 cmp r3, r2 8009ede: d018 beq.n 8009f12 8009ee0: 687b ldr r3, [r7, #4] 8009ee2: 681b ldr r3, [r3, #0] 8009ee4: 4a30 ldr r2, [pc, #192] @ (8009fa8 ) 8009ee6: 4293 cmp r3, r2 8009ee8: d013 beq.n 8009f12 8009eea: 687b ldr r3, [r7, #4] 8009eec: 681b ldr r3, [r3, #0] 8009eee: 4a2f ldr r2, [pc, #188] @ (8009fac ) 8009ef0: 4293 cmp r3, r2 8009ef2: d00e beq.n 8009f12 8009ef4: 687b ldr r3, [r7, #4] 8009ef6: 681b ldr r3, [r3, #0] 8009ef8: 4a2d ldr r2, [pc, #180] @ (8009fb0 ) 8009efa: 4293 cmp r3, r2 8009efc: d009 beq.n 8009f12 8009efe: 687b ldr r3, [r7, #4] 8009f00: 681b ldr r3, [r3, #0] 8009f02: 4a2c ldr r2, [pc, #176] @ (8009fb4 ) 8009f04: 4293 cmp r3, r2 8009f06: d004 beq.n 8009f12 8009f08: 687b ldr r3, [r7, #4] 8009f0a: 681b ldr r3, [r3, #0] 8009f0c: 4a2a ldr r2, [pc, #168] @ (8009fb8 ) 8009f0e: 4293 cmp r3, r2 8009f10: d108 bne.n 8009f24 8009f12: 687b ldr r3, [r7, #4] 8009f14: 681b ldr r3, [r3, #0] 8009f16: 681a ldr r2, [r3, #0] 8009f18: 687b ldr r3, [r7, #4] 8009f1a: 681b ldr r3, [r3, #0] 8009f1c: f022 021c bic.w r2, r2, #28 8009f20: 601a str r2, [r3, #0] 8009f22: e007 b.n 8009f34 8009f24: 687b ldr r3, [r7, #4] 8009f26: 681b ldr r3, [r3, #0] 8009f28: 681a ldr r2, [r3, #0] 8009f2a: 687b ldr r3, [r7, #4] 8009f2c: 681b ldr r3, [r3, #0] 8009f2e: f022 020e bic.w r2, r2, #14 8009f32: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 8009f34: 687b ldr r3, [r7, #4] 8009f36: 6ddb ldr r3, [r3, #92] @ 0x5c 8009f38: f003 031f and.w r3, r3, #31 8009f3c: 2201 movs r2, #1 8009f3e: 409a lsls r2, r3 8009f40: 69fb ldr r3, [r7, #28] 8009f42: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 8009f44: 687b ldr r3, [r7, #4] 8009f46: 2201 movs r2, #1 8009f48: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009f4a: 687b ldr r3, [r7, #4] 8009f4c: 2201 movs r2, #1 8009f4e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009f52: 687b ldr r3, [r7, #4] 8009f54: 2200 movs r2, #0 8009f56: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 8009f5a: 687b ldr r3, [r7, #4] 8009f5c: 6cdb ldr r3, [r3, #76] @ 0x4c 8009f5e: 2b00 cmp r3, #0 8009f60: d009 beq.n 8009f76 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 8009f62: 687b ldr r3, [r7, #4] 8009f64: 6cdb ldr r3, [r3, #76] @ 0x4c 8009f66: 6878 ldr r0, [r7, #4] 8009f68: 4798 blx r3 8009f6a: e004 b.n 8009f76 return; 8009f6c: bf00 nop 8009f6e: e002 b.n 8009f76 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009f70: bf00 nop 8009f72: e000 b.n 8009f76 if((ccr_reg & BDMA_CCR_DBM) != 0U) 8009f74: bf00 nop } else { /* Nothing To Do */ } } 8009f76: 3728 adds r7, #40 @ 0x28 8009f78: 46bd mov sp, r7 8009f7a: bd80 pop {r7, pc} 8009f7c: 40020010 .word 0x40020010 8009f80: 40020028 .word 0x40020028 8009f84: 40020040 .word 0x40020040 8009f88: 40020058 .word 0x40020058 8009f8c: 40020070 .word 0x40020070 8009f90: 40020088 .word 0x40020088 8009f94: 400200a0 .word 0x400200a0 8009f98: 400200b8 .word 0x400200b8 8009f9c: 40020410 .word 0x40020410 8009fa0: 40020428 .word 0x40020428 8009fa4: 40020440 .word 0x40020440 8009fa8: 40020458 .word 0x40020458 8009fac: 40020470 .word 0x40020470 8009fb0: 40020488 .word 0x40020488 8009fb4: 400204a0 .word 0x400204a0 8009fb8: 400204b8 .word 0x400204b8 08009fbc : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8009fbc: b480 push {r7} 8009fbe: b087 sub sp, #28 8009fc0: af00 add r7, sp, #0 8009fc2: 60f8 str r0, [r7, #12] 8009fc4: 60b9 str r1, [r7, #8] 8009fc6: 607a str r2, [r7, #4] 8009fc8: 603b str r3, [r7, #0] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009fca: 68fb ldr r3, [r7, #12] 8009fcc: 6d9b ldr r3, [r3, #88] @ 0x58 8009fce: 617b str r3, [r7, #20] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009fd0: 68fb ldr r3, [r7, #12] 8009fd2: 6d9b ldr r3, [r3, #88] @ 0x58 8009fd4: 613b str r3, [r7, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8009fd6: 68fb ldr r3, [r7, #12] 8009fd8: 681b ldr r3, [r3, #0] 8009fda: 4a7f ldr r2, [pc, #508] @ (800a1d8 ) 8009fdc: 4293 cmp r3, r2 8009fde: d072 beq.n 800a0c6 8009fe0: 68fb ldr r3, [r7, #12] 8009fe2: 681b ldr r3, [r3, #0] 8009fe4: 4a7d ldr r2, [pc, #500] @ (800a1dc ) 8009fe6: 4293 cmp r3, r2 8009fe8: d06d beq.n 800a0c6 8009fea: 68fb ldr r3, [r7, #12] 8009fec: 681b ldr r3, [r3, #0] 8009fee: 4a7c ldr r2, [pc, #496] @ (800a1e0 ) 8009ff0: 4293 cmp r3, r2 8009ff2: d068 beq.n 800a0c6 8009ff4: 68fb ldr r3, [r7, #12] 8009ff6: 681b ldr r3, [r3, #0] 8009ff8: 4a7a ldr r2, [pc, #488] @ (800a1e4 ) 8009ffa: 4293 cmp r3, r2 8009ffc: d063 beq.n 800a0c6 8009ffe: 68fb ldr r3, [r7, #12] 800a000: 681b ldr r3, [r3, #0] 800a002: 4a79 ldr r2, [pc, #484] @ (800a1e8 ) 800a004: 4293 cmp r3, r2 800a006: d05e beq.n 800a0c6 800a008: 68fb ldr r3, [r7, #12] 800a00a: 681b ldr r3, [r3, #0] 800a00c: 4a77 ldr r2, [pc, #476] @ (800a1ec ) 800a00e: 4293 cmp r3, r2 800a010: d059 beq.n 800a0c6 800a012: 68fb ldr r3, [r7, #12] 800a014: 681b ldr r3, [r3, #0] 800a016: 4a76 ldr r2, [pc, #472] @ (800a1f0 ) 800a018: 4293 cmp r3, r2 800a01a: d054 beq.n 800a0c6 800a01c: 68fb ldr r3, [r7, #12] 800a01e: 681b ldr r3, [r3, #0] 800a020: 4a74 ldr r2, [pc, #464] @ (800a1f4 ) 800a022: 4293 cmp r3, r2 800a024: d04f beq.n 800a0c6 800a026: 68fb ldr r3, [r7, #12] 800a028: 681b ldr r3, [r3, #0] 800a02a: 4a73 ldr r2, [pc, #460] @ (800a1f8 ) 800a02c: 4293 cmp r3, r2 800a02e: d04a beq.n 800a0c6 800a030: 68fb ldr r3, [r7, #12] 800a032: 681b ldr r3, [r3, #0] 800a034: 4a71 ldr r2, [pc, #452] @ (800a1fc ) 800a036: 4293 cmp r3, r2 800a038: d045 beq.n 800a0c6 800a03a: 68fb ldr r3, [r7, #12] 800a03c: 681b ldr r3, [r3, #0] 800a03e: 4a70 ldr r2, [pc, #448] @ (800a200 ) 800a040: 4293 cmp r3, r2 800a042: d040 beq.n 800a0c6 800a044: 68fb ldr r3, [r7, #12] 800a046: 681b ldr r3, [r3, #0] 800a048: 4a6e ldr r2, [pc, #440] @ (800a204 ) 800a04a: 4293 cmp r3, r2 800a04c: d03b beq.n 800a0c6 800a04e: 68fb ldr r3, [r7, #12] 800a050: 681b ldr r3, [r3, #0] 800a052: 4a6d ldr r2, [pc, #436] @ (800a208 ) 800a054: 4293 cmp r3, r2 800a056: d036 beq.n 800a0c6 800a058: 68fb ldr r3, [r7, #12] 800a05a: 681b ldr r3, [r3, #0] 800a05c: 4a6b ldr r2, [pc, #428] @ (800a20c ) 800a05e: 4293 cmp r3, r2 800a060: d031 beq.n 800a0c6 800a062: 68fb ldr r3, [r7, #12] 800a064: 681b ldr r3, [r3, #0] 800a066: 4a6a ldr r2, [pc, #424] @ (800a210 ) 800a068: 4293 cmp r3, r2 800a06a: d02c beq.n 800a0c6 800a06c: 68fb ldr r3, [r7, #12] 800a06e: 681b ldr r3, [r3, #0] 800a070: 4a68 ldr r2, [pc, #416] @ (800a214 ) 800a072: 4293 cmp r3, r2 800a074: d027 beq.n 800a0c6 800a076: 68fb ldr r3, [r7, #12] 800a078: 681b ldr r3, [r3, #0] 800a07a: 4a67 ldr r2, [pc, #412] @ (800a218 ) 800a07c: 4293 cmp r3, r2 800a07e: d022 beq.n 800a0c6 800a080: 68fb ldr r3, [r7, #12] 800a082: 681b ldr r3, [r3, #0] 800a084: 4a65 ldr r2, [pc, #404] @ (800a21c ) 800a086: 4293 cmp r3, r2 800a088: d01d beq.n 800a0c6 800a08a: 68fb ldr r3, [r7, #12] 800a08c: 681b ldr r3, [r3, #0] 800a08e: 4a64 ldr r2, [pc, #400] @ (800a220 ) 800a090: 4293 cmp r3, r2 800a092: d018 beq.n 800a0c6 800a094: 68fb ldr r3, [r7, #12] 800a096: 681b ldr r3, [r3, #0] 800a098: 4a62 ldr r2, [pc, #392] @ (800a224 ) 800a09a: 4293 cmp r3, r2 800a09c: d013 beq.n 800a0c6 800a09e: 68fb ldr r3, [r7, #12] 800a0a0: 681b ldr r3, [r3, #0] 800a0a2: 4a61 ldr r2, [pc, #388] @ (800a228 ) 800a0a4: 4293 cmp r3, r2 800a0a6: d00e beq.n 800a0c6 800a0a8: 68fb ldr r3, [r7, #12] 800a0aa: 681b ldr r3, [r3, #0] 800a0ac: 4a5f ldr r2, [pc, #380] @ (800a22c ) 800a0ae: 4293 cmp r3, r2 800a0b0: d009 beq.n 800a0c6 800a0b2: 68fb ldr r3, [r7, #12] 800a0b4: 681b ldr r3, [r3, #0] 800a0b6: 4a5e ldr r2, [pc, #376] @ (800a230 ) 800a0b8: 4293 cmp r3, r2 800a0ba: d004 beq.n 800a0c6 800a0bc: 68fb ldr r3, [r7, #12] 800a0be: 681b ldr r3, [r3, #0] 800a0c0: 4a5c ldr r2, [pc, #368] @ (800a234 ) 800a0c2: 4293 cmp r3, r2 800a0c4: d101 bne.n 800a0ca 800a0c6: 2301 movs r3, #1 800a0c8: e000 b.n 800a0cc 800a0ca: 2300 movs r3, #0 800a0cc: 2b00 cmp r3, #0 800a0ce: d00d beq.n 800a0ec { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800a0d0: 68fb ldr r3, [r7, #12] 800a0d2: 6e5b ldr r3, [r3, #100] @ 0x64 800a0d4: 68fa ldr r2, [r7, #12] 800a0d6: 6e92 ldr r2, [r2, #104] @ 0x68 800a0d8: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800a0da: 68fb ldr r3, [r7, #12] 800a0dc: 6edb ldr r3, [r3, #108] @ 0x6c 800a0de: 2b00 cmp r3, #0 800a0e0: d004 beq.n 800a0ec { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800a0e2: 68fb ldr r3, [r7, #12] 800a0e4: 6f1b ldr r3, [r3, #112] @ 0x70 800a0e6: 68fa ldr r2, [r7, #12] 800a0e8: 6f52 ldr r2, [r2, #116] @ 0x74 800a0ea: 605a str r2, [r3, #4] } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800a0ec: 68fb ldr r3, [r7, #12] 800a0ee: 681b ldr r3, [r3, #0] 800a0f0: 4a39 ldr r2, [pc, #228] @ (800a1d8 ) 800a0f2: 4293 cmp r3, r2 800a0f4: d04a beq.n 800a18c 800a0f6: 68fb ldr r3, [r7, #12] 800a0f8: 681b ldr r3, [r3, #0] 800a0fa: 4a38 ldr r2, [pc, #224] @ (800a1dc ) 800a0fc: 4293 cmp r3, r2 800a0fe: d045 beq.n 800a18c 800a100: 68fb ldr r3, [r7, #12] 800a102: 681b ldr r3, [r3, #0] 800a104: 4a36 ldr r2, [pc, #216] @ (800a1e0 ) 800a106: 4293 cmp r3, r2 800a108: d040 beq.n 800a18c 800a10a: 68fb ldr r3, [r7, #12] 800a10c: 681b ldr r3, [r3, #0] 800a10e: 4a35 ldr r2, [pc, #212] @ (800a1e4 ) 800a110: 4293 cmp r3, r2 800a112: d03b beq.n 800a18c 800a114: 68fb ldr r3, [r7, #12] 800a116: 681b ldr r3, [r3, #0] 800a118: 4a33 ldr r2, [pc, #204] @ (800a1e8 ) 800a11a: 4293 cmp r3, r2 800a11c: d036 beq.n 800a18c 800a11e: 68fb ldr r3, [r7, #12] 800a120: 681b ldr r3, [r3, #0] 800a122: 4a32 ldr r2, [pc, #200] @ (800a1ec ) 800a124: 4293 cmp r3, r2 800a126: d031 beq.n 800a18c 800a128: 68fb ldr r3, [r7, #12] 800a12a: 681b ldr r3, [r3, #0] 800a12c: 4a30 ldr r2, [pc, #192] @ (800a1f0 ) 800a12e: 4293 cmp r3, r2 800a130: d02c beq.n 800a18c 800a132: 68fb ldr r3, [r7, #12] 800a134: 681b ldr r3, [r3, #0] 800a136: 4a2f ldr r2, [pc, #188] @ (800a1f4 ) 800a138: 4293 cmp r3, r2 800a13a: d027 beq.n 800a18c 800a13c: 68fb ldr r3, [r7, #12] 800a13e: 681b ldr r3, [r3, #0] 800a140: 4a2d ldr r2, [pc, #180] @ (800a1f8 ) 800a142: 4293 cmp r3, r2 800a144: d022 beq.n 800a18c 800a146: 68fb ldr r3, [r7, #12] 800a148: 681b ldr r3, [r3, #0] 800a14a: 4a2c ldr r2, [pc, #176] @ (800a1fc ) 800a14c: 4293 cmp r3, r2 800a14e: d01d beq.n 800a18c 800a150: 68fb ldr r3, [r7, #12] 800a152: 681b ldr r3, [r3, #0] 800a154: 4a2a ldr r2, [pc, #168] @ (800a200 ) 800a156: 4293 cmp r3, r2 800a158: d018 beq.n 800a18c 800a15a: 68fb ldr r3, [r7, #12] 800a15c: 681b ldr r3, [r3, #0] 800a15e: 4a29 ldr r2, [pc, #164] @ (800a204 ) 800a160: 4293 cmp r3, r2 800a162: d013 beq.n 800a18c 800a164: 68fb ldr r3, [r7, #12] 800a166: 681b ldr r3, [r3, #0] 800a168: 4a27 ldr r2, [pc, #156] @ (800a208 ) 800a16a: 4293 cmp r3, r2 800a16c: d00e beq.n 800a18c 800a16e: 68fb ldr r3, [r7, #12] 800a170: 681b ldr r3, [r3, #0] 800a172: 4a26 ldr r2, [pc, #152] @ (800a20c ) 800a174: 4293 cmp r3, r2 800a176: d009 beq.n 800a18c 800a178: 68fb ldr r3, [r7, #12] 800a17a: 681b ldr r3, [r3, #0] 800a17c: 4a24 ldr r2, [pc, #144] @ (800a210 ) 800a17e: 4293 cmp r3, r2 800a180: d004 beq.n 800a18c 800a182: 68fb ldr r3, [r7, #12] 800a184: 681b ldr r3, [r3, #0] 800a186: 4a23 ldr r2, [pc, #140] @ (800a214 ) 800a188: 4293 cmp r3, r2 800a18a: d101 bne.n 800a190 800a18c: 2301 movs r3, #1 800a18e: e000 b.n 800a192 800a190: 2300 movs r3, #0 800a192: 2b00 cmp r3, #0 800a194: d059 beq.n 800a24a { /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800a196: 68fb ldr r3, [r7, #12] 800a198: 6ddb ldr r3, [r3, #92] @ 0x5c 800a19a: f003 031f and.w r3, r3, #31 800a19e: 223f movs r2, #63 @ 0x3f 800a1a0: 409a lsls r2, r3 800a1a2: 697b ldr r3, [r7, #20] 800a1a4: 609a str r2, [r3, #8] /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 800a1a6: 68fb ldr r3, [r7, #12] 800a1a8: 681b ldr r3, [r3, #0] 800a1aa: 681a ldr r2, [r3, #0] 800a1ac: 68fb ldr r3, [r7, #12] 800a1ae: 681b ldr r3, [r3, #0] 800a1b0: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800a1b4: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 800a1b6: 68fb ldr r3, [r7, #12] 800a1b8: 681b ldr r3, [r3, #0] 800a1ba: 683a ldr r2, [r7, #0] 800a1bc: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800a1be: 68fb ldr r3, [r7, #12] 800a1c0: 689b ldr r3, [r3, #8] 800a1c2: 2b40 cmp r3, #64 @ 0x40 800a1c4: d138 bne.n 800a238 { /* Configure DMA Stream destination address */ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800a1c6: 68fb ldr r3, [r7, #12] 800a1c8: 681b ldr r3, [r3, #0] 800a1ca: 687a ldr r2, [r7, #4] 800a1cc: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 800a1ce: 68fb ldr r3, [r7, #12] 800a1d0: 681b ldr r3, [r3, #0] 800a1d2: 68ba ldr r2, [r7, #8] 800a1d4: 60da str r2, [r3, #12] } else { /* Nothing To Do */ } } 800a1d6: e086 b.n 800a2e6 800a1d8: 40020010 .word 0x40020010 800a1dc: 40020028 .word 0x40020028 800a1e0: 40020040 .word 0x40020040 800a1e4: 40020058 .word 0x40020058 800a1e8: 40020070 .word 0x40020070 800a1ec: 40020088 .word 0x40020088 800a1f0: 400200a0 .word 0x400200a0 800a1f4: 400200b8 .word 0x400200b8 800a1f8: 40020410 .word 0x40020410 800a1fc: 40020428 .word 0x40020428 800a200: 40020440 .word 0x40020440 800a204: 40020458 .word 0x40020458 800a208: 40020470 .word 0x40020470 800a20c: 40020488 .word 0x40020488 800a210: 400204a0 .word 0x400204a0 800a214: 400204b8 .word 0x400204b8 800a218: 58025408 .word 0x58025408 800a21c: 5802541c .word 0x5802541c 800a220: 58025430 .word 0x58025430 800a224: 58025444 .word 0x58025444 800a228: 58025458 .word 0x58025458 800a22c: 5802546c .word 0x5802546c 800a230: 58025480 .word 0x58025480 800a234: 58025494 .word 0x58025494 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 800a238: 68fb ldr r3, [r7, #12] 800a23a: 681b ldr r3, [r3, #0] 800a23c: 68ba ldr r2, [r7, #8] 800a23e: 609a str r2, [r3, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 800a240: 68fb ldr r3, [r7, #12] 800a242: 681b ldr r3, [r3, #0] 800a244: 687a ldr r2, [r7, #4] 800a246: 60da str r2, [r3, #12] } 800a248: e04d b.n 800a2e6 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800a24a: 68fb ldr r3, [r7, #12] 800a24c: 681b ldr r3, [r3, #0] 800a24e: 4a29 ldr r2, [pc, #164] @ (800a2f4 ) 800a250: 4293 cmp r3, r2 800a252: d022 beq.n 800a29a 800a254: 68fb ldr r3, [r7, #12] 800a256: 681b ldr r3, [r3, #0] 800a258: 4a27 ldr r2, [pc, #156] @ (800a2f8 ) 800a25a: 4293 cmp r3, r2 800a25c: d01d beq.n 800a29a 800a25e: 68fb ldr r3, [r7, #12] 800a260: 681b ldr r3, [r3, #0] 800a262: 4a26 ldr r2, [pc, #152] @ (800a2fc ) 800a264: 4293 cmp r3, r2 800a266: d018 beq.n 800a29a 800a268: 68fb ldr r3, [r7, #12] 800a26a: 681b ldr r3, [r3, #0] 800a26c: 4a24 ldr r2, [pc, #144] @ (800a300 ) 800a26e: 4293 cmp r3, r2 800a270: d013 beq.n 800a29a 800a272: 68fb ldr r3, [r7, #12] 800a274: 681b ldr r3, [r3, #0] 800a276: 4a23 ldr r2, [pc, #140] @ (800a304 ) 800a278: 4293 cmp r3, r2 800a27a: d00e beq.n 800a29a 800a27c: 68fb ldr r3, [r7, #12] 800a27e: 681b ldr r3, [r3, #0] 800a280: 4a21 ldr r2, [pc, #132] @ (800a308 ) 800a282: 4293 cmp r3, r2 800a284: d009 beq.n 800a29a 800a286: 68fb ldr r3, [r7, #12] 800a288: 681b ldr r3, [r3, #0] 800a28a: 4a20 ldr r2, [pc, #128] @ (800a30c ) 800a28c: 4293 cmp r3, r2 800a28e: d004 beq.n 800a29a 800a290: 68fb ldr r3, [r7, #12] 800a292: 681b ldr r3, [r3, #0] 800a294: 4a1e ldr r2, [pc, #120] @ (800a310 ) 800a296: 4293 cmp r3, r2 800a298: d101 bne.n 800a29e 800a29a: 2301 movs r3, #1 800a29c: e000 b.n 800a2a0 800a29e: 2300 movs r3, #0 800a2a0: 2b00 cmp r3, #0 800a2a2: d020 beq.n 800a2e6 regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800a2a4: 68fb ldr r3, [r7, #12] 800a2a6: 6ddb ldr r3, [r3, #92] @ 0x5c 800a2a8: f003 031f and.w r3, r3, #31 800a2ac: 2201 movs r2, #1 800a2ae: 409a lsls r2, r3 800a2b0: 693b ldr r3, [r7, #16] 800a2b2: 605a str r2, [r3, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 800a2b4: 68fb ldr r3, [r7, #12] 800a2b6: 681b ldr r3, [r3, #0] 800a2b8: 683a ldr r2, [r7, #0] 800a2ba: 605a str r2, [r3, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800a2bc: 68fb ldr r3, [r7, #12] 800a2be: 689b ldr r3, [r3, #8] 800a2c0: 2b40 cmp r3, #64 @ 0x40 800a2c2: d108 bne.n 800a2d6 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 800a2c4: 68fb ldr r3, [r7, #12] 800a2c6: 681b ldr r3, [r3, #0] 800a2c8: 687a ldr r2, [r7, #4] 800a2ca: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 800a2cc: 68fb ldr r3, [r7, #12] 800a2ce: 681b ldr r3, [r3, #0] 800a2d0: 68ba ldr r2, [r7, #8] 800a2d2: 60da str r2, [r3, #12] } 800a2d4: e007 b.n 800a2e6 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 800a2d6: 68fb ldr r3, [r7, #12] 800a2d8: 681b ldr r3, [r3, #0] 800a2da: 68ba ldr r2, [r7, #8] 800a2dc: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 800a2de: 68fb ldr r3, [r7, #12] 800a2e0: 681b ldr r3, [r3, #0] 800a2e2: 687a ldr r2, [r7, #4] 800a2e4: 60da str r2, [r3, #12] } 800a2e6: bf00 nop 800a2e8: 371c adds r7, #28 800a2ea: 46bd mov sp, r7 800a2ec: f85d 7b04 ldr.w r7, [sp], #4 800a2f0: 4770 bx lr 800a2f2: bf00 nop 800a2f4: 58025408 .word 0x58025408 800a2f8: 5802541c .word 0x5802541c 800a2fc: 58025430 .word 0x58025430 800a300: 58025444 .word 0x58025444 800a304: 58025458 .word 0x58025458 800a308: 5802546c .word 0x5802546c 800a30c: 58025480 .word 0x58025480 800a310: 58025494 .word 0x58025494 0800a314 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800a314: b480 push {r7} 800a316: b085 sub sp, #20 800a318: af00 add r7, sp, #0 800a31a: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800a31c: 687b ldr r3, [r7, #4] 800a31e: 681b ldr r3, [r3, #0] 800a320: 4a42 ldr r2, [pc, #264] @ (800a42c ) 800a322: 4293 cmp r3, r2 800a324: d04a beq.n 800a3bc 800a326: 687b ldr r3, [r7, #4] 800a328: 681b ldr r3, [r3, #0] 800a32a: 4a41 ldr r2, [pc, #260] @ (800a430 ) 800a32c: 4293 cmp r3, r2 800a32e: d045 beq.n 800a3bc 800a330: 687b ldr r3, [r7, #4] 800a332: 681b ldr r3, [r3, #0] 800a334: 4a3f ldr r2, [pc, #252] @ (800a434 ) 800a336: 4293 cmp r3, r2 800a338: d040 beq.n 800a3bc 800a33a: 687b ldr r3, [r7, #4] 800a33c: 681b ldr r3, [r3, #0] 800a33e: 4a3e ldr r2, [pc, #248] @ (800a438 ) 800a340: 4293 cmp r3, r2 800a342: d03b beq.n 800a3bc 800a344: 687b ldr r3, [r7, #4] 800a346: 681b ldr r3, [r3, #0] 800a348: 4a3c ldr r2, [pc, #240] @ (800a43c ) 800a34a: 4293 cmp r3, r2 800a34c: d036 beq.n 800a3bc 800a34e: 687b ldr r3, [r7, #4] 800a350: 681b ldr r3, [r3, #0] 800a352: 4a3b ldr r2, [pc, #236] @ (800a440 ) 800a354: 4293 cmp r3, r2 800a356: d031 beq.n 800a3bc 800a358: 687b ldr r3, [r7, #4] 800a35a: 681b ldr r3, [r3, #0] 800a35c: 4a39 ldr r2, [pc, #228] @ (800a444 ) 800a35e: 4293 cmp r3, r2 800a360: d02c beq.n 800a3bc 800a362: 687b ldr r3, [r7, #4] 800a364: 681b ldr r3, [r3, #0] 800a366: 4a38 ldr r2, [pc, #224] @ (800a448 ) 800a368: 4293 cmp r3, r2 800a36a: d027 beq.n 800a3bc 800a36c: 687b ldr r3, [r7, #4] 800a36e: 681b ldr r3, [r3, #0] 800a370: 4a36 ldr r2, [pc, #216] @ (800a44c ) 800a372: 4293 cmp r3, r2 800a374: d022 beq.n 800a3bc 800a376: 687b ldr r3, [r7, #4] 800a378: 681b ldr r3, [r3, #0] 800a37a: 4a35 ldr r2, [pc, #212] @ (800a450 ) 800a37c: 4293 cmp r3, r2 800a37e: d01d beq.n 800a3bc 800a380: 687b ldr r3, [r7, #4] 800a382: 681b ldr r3, [r3, #0] 800a384: 4a33 ldr r2, [pc, #204] @ (800a454 ) 800a386: 4293 cmp r3, r2 800a388: d018 beq.n 800a3bc 800a38a: 687b ldr r3, [r7, #4] 800a38c: 681b ldr r3, [r3, #0] 800a38e: 4a32 ldr r2, [pc, #200] @ (800a458 ) 800a390: 4293 cmp r3, r2 800a392: d013 beq.n 800a3bc 800a394: 687b ldr r3, [r7, #4] 800a396: 681b ldr r3, [r3, #0] 800a398: 4a30 ldr r2, [pc, #192] @ (800a45c ) 800a39a: 4293 cmp r3, r2 800a39c: d00e beq.n 800a3bc 800a39e: 687b ldr r3, [r7, #4] 800a3a0: 681b ldr r3, [r3, #0] 800a3a2: 4a2f ldr r2, [pc, #188] @ (800a460 ) 800a3a4: 4293 cmp r3, r2 800a3a6: d009 beq.n 800a3bc 800a3a8: 687b ldr r3, [r7, #4] 800a3aa: 681b ldr r3, [r3, #0] 800a3ac: 4a2d ldr r2, [pc, #180] @ (800a464 ) 800a3ae: 4293 cmp r3, r2 800a3b0: d004 beq.n 800a3bc 800a3b2: 687b ldr r3, [r7, #4] 800a3b4: 681b ldr r3, [r3, #0] 800a3b6: 4a2c ldr r2, [pc, #176] @ (800a468 ) 800a3b8: 4293 cmp r3, r2 800a3ba: d101 bne.n 800a3c0 800a3bc: 2301 movs r3, #1 800a3be: e000 b.n 800a3c2 800a3c0: 2300 movs r3, #0 800a3c2: 2b00 cmp r3, #0 800a3c4: d024 beq.n 800a410 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800a3c6: 687b ldr r3, [r7, #4] 800a3c8: 681b ldr r3, [r3, #0] 800a3ca: b2db uxtb r3, r3 800a3cc: 3b10 subs r3, #16 800a3ce: 4a27 ldr r2, [pc, #156] @ (800a46c ) 800a3d0: fba2 2303 umull r2, r3, r2, r3 800a3d4: 091b lsrs r3, r3, #4 800a3d6: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 800a3d8: 68fb ldr r3, [r7, #12] 800a3da: f003 0307 and.w r3, r3, #7 800a3de: 4a24 ldr r2, [pc, #144] @ (800a470 ) 800a3e0: 5cd3 ldrb r3, [r2, r3] 800a3e2: 461a mov r2, r3 800a3e4: 687b ldr r3, [r7, #4] 800a3e6: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 800a3e8: 68fb ldr r3, [r7, #12] 800a3ea: 2b03 cmp r3, #3 800a3ec: d908 bls.n 800a400 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 800a3ee: 687b ldr r3, [r7, #4] 800a3f0: 681b ldr r3, [r3, #0] 800a3f2: 461a mov r2, r3 800a3f4: 4b1f ldr r3, [pc, #124] @ (800a474 ) 800a3f6: 4013 ands r3, r2 800a3f8: 1d1a adds r2, r3, #4 800a3fa: 687b ldr r3, [r7, #4] 800a3fc: 659a str r2, [r3, #88] @ 0x58 800a3fe: e00d b.n 800a41c } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 800a400: 687b ldr r3, [r7, #4] 800a402: 681b ldr r3, [r3, #0] 800a404: 461a mov r2, r3 800a406: 4b1b ldr r3, [pc, #108] @ (800a474 ) 800a408: 4013 ands r3, r2 800a40a: 687a ldr r2, [r7, #4] 800a40c: 6593 str r3, [r2, #88] @ 0x58 800a40e: e005 b.n 800a41c } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 800a410: 687b ldr r3, [r7, #4] 800a412: 681b ldr r3, [r3, #0] 800a414: f023 02ff bic.w r2, r3, #255 @ 0xff 800a418: 687b ldr r3, [r7, #4] 800a41a: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 800a41c: 687b ldr r3, [r7, #4] 800a41e: 6d9b ldr r3, [r3, #88] @ 0x58 } 800a420: 4618 mov r0, r3 800a422: 3714 adds r7, #20 800a424: 46bd mov sp, r7 800a426: f85d 7b04 ldr.w r7, [sp], #4 800a42a: 4770 bx lr 800a42c: 40020010 .word 0x40020010 800a430: 40020028 .word 0x40020028 800a434: 40020040 .word 0x40020040 800a438: 40020058 .word 0x40020058 800a43c: 40020070 .word 0x40020070 800a440: 40020088 .word 0x40020088 800a444: 400200a0 .word 0x400200a0 800a448: 400200b8 .word 0x400200b8 800a44c: 40020410 .word 0x40020410 800a450: 40020428 .word 0x40020428 800a454: 40020440 .word 0x40020440 800a458: 40020458 .word 0x40020458 800a45c: 40020470 .word 0x40020470 800a460: 40020488 .word 0x40020488 800a464: 400204a0 .word 0x400204a0 800a468: 400204b8 .word 0x400204b8 800a46c: aaaaaaab .word 0xaaaaaaab 800a470: 080189d8 .word 0x080189d8 800a474: fffffc00 .word 0xfffffc00 0800a478 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 800a478: b480 push {r7} 800a47a: b085 sub sp, #20 800a47c: af00 add r7, sp, #0 800a47e: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800a480: 2300 movs r3, #0 800a482: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800a484: 687b ldr r3, [r7, #4] 800a486: 699b ldr r3, [r3, #24] 800a488: 2b00 cmp r3, #0 800a48a: d120 bne.n 800a4ce { switch (hdma->Init.FIFOThreshold) 800a48c: 687b ldr r3, [r7, #4] 800a48e: 6a9b ldr r3, [r3, #40] @ 0x28 800a490: 2b03 cmp r3, #3 800a492: d858 bhi.n 800a546 800a494: a201 add r2, pc, #4 @ (adr r2, 800a49c ) 800a496: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a49a: bf00 nop 800a49c: 0800a4ad .word 0x0800a4ad 800a4a0: 0800a4bf .word 0x0800a4bf 800a4a4: 0800a4ad .word 0x0800a4ad 800a4a8: 0800a547 .word 0x0800a547 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800a4ac: 687b ldr r3, [r7, #4] 800a4ae: 6adb ldr r3, [r3, #44] @ 0x2c 800a4b0: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800a4b4: 2b00 cmp r3, #0 800a4b6: d048 beq.n 800a54a { status = HAL_ERROR; 800a4b8: 2301 movs r3, #1 800a4ba: 73fb strb r3, [r7, #15] } break; 800a4bc: e045 b.n 800a54a case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800a4be: 687b ldr r3, [r7, #4] 800a4c0: 6adb ldr r3, [r3, #44] @ 0x2c 800a4c2: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800a4c6: d142 bne.n 800a54e { status = HAL_ERROR; 800a4c8: 2301 movs r3, #1 800a4ca: 73fb strb r3, [r7, #15] } break; 800a4cc: e03f b.n 800a54e break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800a4ce: 687b ldr r3, [r7, #4] 800a4d0: 699b ldr r3, [r3, #24] 800a4d2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800a4d6: d123 bne.n 800a520 { switch (hdma->Init.FIFOThreshold) 800a4d8: 687b ldr r3, [r7, #4] 800a4da: 6a9b ldr r3, [r3, #40] @ 0x28 800a4dc: 2b03 cmp r3, #3 800a4de: d838 bhi.n 800a552 800a4e0: a201 add r2, pc, #4 @ (adr r2, 800a4e8 ) 800a4e2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800a4e6: bf00 nop 800a4e8: 0800a4f9 .word 0x0800a4f9 800a4ec: 0800a4ff .word 0x0800a4ff 800a4f0: 0800a4f9 .word 0x0800a4f9 800a4f4: 0800a511 .word 0x0800a511 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800a4f8: 2301 movs r3, #1 800a4fa: 73fb strb r3, [r7, #15] break; 800a4fc: e030 b.n 800a560 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800a4fe: 687b ldr r3, [r7, #4] 800a500: 6adb ldr r3, [r3, #44] @ 0x2c 800a502: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800a506: 2b00 cmp r3, #0 800a508: d025 beq.n 800a556 { status = HAL_ERROR; 800a50a: 2301 movs r3, #1 800a50c: 73fb strb r3, [r7, #15] } break; 800a50e: e022 b.n 800a556 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800a510: 687b ldr r3, [r7, #4] 800a512: 6adb ldr r3, [r3, #44] @ 0x2c 800a514: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800a518: d11f bne.n 800a55a { status = HAL_ERROR; 800a51a: 2301 movs r3, #1 800a51c: 73fb strb r3, [r7, #15] } break; 800a51e: e01c b.n 800a55a } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 800a520: 687b ldr r3, [r7, #4] 800a522: 6a9b ldr r3, [r3, #40] @ 0x28 800a524: 2b02 cmp r3, #2 800a526: d902 bls.n 800a52e 800a528: 2b03 cmp r3, #3 800a52a: d003 beq.n 800a534 status = HAL_ERROR; } break; default: break; 800a52c: e018 b.n 800a560 status = HAL_ERROR; 800a52e: 2301 movs r3, #1 800a530: 73fb strb r3, [r7, #15] break; 800a532: e015 b.n 800a560 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800a534: 687b ldr r3, [r7, #4] 800a536: 6adb ldr r3, [r3, #44] @ 0x2c 800a538: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800a53c: 2b00 cmp r3, #0 800a53e: d00e beq.n 800a55e status = HAL_ERROR; 800a540: 2301 movs r3, #1 800a542: 73fb strb r3, [r7, #15] break; 800a544: e00b b.n 800a55e break; 800a546: bf00 nop 800a548: e00a b.n 800a560 break; 800a54a: bf00 nop 800a54c: e008 b.n 800a560 break; 800a54e: bf00 nop 800a550: e006 b.n 800a560 break; 800a552: bf00 nop 800a554: e004 b.n 800a560 break; 800a556: bf00 nop 800a558: e002 b.n 800a560 break; 800a55a: bf00 nop 800a55c: e000 b.n 800a560 break; 800a55e: bf00 nop } } return status; 800a560: 7bfb ldrb r3, [r7, #15] } 800a562: 4618 mov r0, r3 800a564: 3714 adds r7, #20 800a566: 46bd mov sp, r7 800a568: f85d 7b04 ldr.w r7, [sp], #4 800a56c: 4770 bx lr 800a56e: bf00 nop 0800a570 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800a570: b480 push {r7} 800a572: b085 sub sp, #20 800a574: af00 add r7, sp, #0 800a576: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 800a578: 687b ldr r3, [r7, #4] 800a57a: 681b ldr r3, [r3, #0] 800a57c: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800a57e: 687b ldr r3, [r7, #4] 800a580: 681b ldr r3, [r3, #0] 800a582: 4a38 ldr r2, [pc, #224] @ (800a664 ) 800a584: 4293 cmp r3, r2 800a586: d022 beq.n 800a5ce 800a588: 687b ldr r3, [r7, #4] 800a58a: 681b ldr r3, [r3, #0] 800a58c: 4a36 ldr r2, [pc, #216] @ (800a668 ) 800a58e: 4293 cmp r3, r2 800a590: d01d beq.n 800a5ce 800a592: 687b ldr r3, [r7, #4] 800a594: 681b ldr r3, [r3, #0] 800a596: 4a35 ldr r2, [pc, #212] @ (800a66c ) 800a598: 4293 cmp r3, r2 800a59a: d018 beq.n 800a5ce 800a59c: 687b ldr r3, [r7, #4] 800a59e: 681b ldr r3, [r3, #0] 800a5a0: 4a33 ldr r2, [pc, #204] @ (800a670 ) 800a5a2: 4293 cmp r3, r2 800a5a4: d013 beq.n 800a5ce 800a5a6: 687b ldr r3, [r7, #4] 800a5a8: 681b ldr r3, [r3, #0] 800a5aa: 4a32 ldr r2, [pc, #200] @ (800a674 ) 800a5ac: 4293 cmp r3, r2 800a5ae: d00e beq.n 800a5ce 800a5b0: 687b ldr r3, [r7, #4] 800a5b2: 681b ldr r3, [r3, #0] 800a5b4: 4a30 ldr r2, [pc, #192] @ (800a678 ) 800a5b6: 4293 cmp r3, r2 800a5b8: d009 beq.n 800a5ce 800a5ba: 687b ldr r3, [r7, #4] 800a5bc: 681b ldr r3, [r3, #0] 800a5be: 4a2f ldr r2, [pc, #188] @ (800a67c ) 800a5c0: 4293 cmp r3, r2 800a5c2: d004 beq.n 800a5ce 800a5c4: 687b ldr r3, [r7, #4] 800a5c6: 681b ldr r3, [r3, #0] 800a5c8: 4a2d ldr r2, [pc, #180] @ (800a680 ) 800a5ca: 4293 cmp r3, r2 800a5cc: d101 bne.n 800a5d2 800a5ce: 2301 movs r3, #1 800a5d0: e000 b.n 800a5d4 800a5d2: 2300 movs r3, #0 800a5d4: 2b00 cmp r3, #0 800a5d6: d01a beq.n 800a60e { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 800a5d8: 687b ldr r3, [r7, #4] 800a5da: 681b ldr r3, [r3, #0] 800a5dc: b2db uxtb r3, r3 800a5de: 3b08 subs r3, #8 800a5e0: 4a28 ldr r2, [pc, #160] @ (800a684 ) 800a5e2: fba2 2303 umull r2, r3, r2, r3 800a5e6: 091b lsrs r3, r3, #4 800a5e8: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 800a5ea: 68fa ldr r2, [r7, #12] 800a5ec: 4b26 ldr r3, [pc, #152] @ (800a688 ) 800a5ee: 4413 add r3, r2 800a5f0: 009b lsls r3, r3, #2 800a5f2: 461a mov r2, r3 800a5f4: 687b ldr r3, [r7, #4] 800a5f6: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800a5f8: 687b ldr r3, [r7, #4] 800a5fa: 4a24 ldr r2, [pc, #144] @ (800a68c ) 800a5fc: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800a5fe: 68fb ldr r3, [r7, #12] 800a600: f003 031f and.w r3, r3, #31 800a604: 2201 movs r2, #1 800a606: 409a lsls r2, r3 800a608: 687b ldr r3, [r7, #4] 800a60a: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 800a60c: e024 b.n 800a658 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800a60e: 687b ldr r3, [r7, #4] 800a610: 681b ldr r3, [r3, #0] 800a612: b2db uxtb r3, r3 800a614: 3b10 subs r3, #16 800a616: 4a1e ldr r2, [pc, #120] @ (800a690 ) 800a618: fba2 2303 umull r2, r3, r2, r3 800a61c: 091b lsrs r3, r3, #4 800a61e: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800a620: 68bb ldr r3, [r7, #8] 800a622: 4a1c ldr r2, [pc, #112] @ (800a694 ) 800a624: 4293 cmp r3, r2 800a626: d806 bhi.n 800a636 800a628: 68bb ldr r3, [r7, #8] 800a62a: 4a1b ldr r2, [pc, #108] @ (800a698 ) 800a62c: 4293 cmp r3, r2 800a62e: d902 bls.n 800a636 stream_number += 8U; 800a630: 68fb ldr r3, [r7, #12] 800a632: 3308 adds r3, #8 800a634: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800a636: 68fa ldr r2, [r7, #12] 800a638: 4b18 ldr r3, [pc, #96] @ (800a69c ) 800a63a: 4413 add r3, r2 800a63c: 009b lsls r3, r3, #2 800a63e: 461a mov r2, r3 800a640: 687b ldr r3, [r7, #4] 800a642: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800a644: 687b ldr r3, [r7, #4] 800a646: 4a16 ldr r2, [pc, #88] @ (800a6a0 ) 800a648: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800a64a: 68fb ldr r3, [r7, #12] 800a64c: f003 031f and.w r3, r3, #31 800a650: 2201 movs r2, #1 800a652: 409a lsls r2, r3 800a654: 687b ldr r3, [r7, #4] 800a656: 669a str r2, [r3, #104] @ 0x68 } 800a658: bf00 nop 800a65a: 3714 adds r7, #20 800a65c: 46bd mov sp, r7 800a65e: f85d 7b04 ldr.w r7, [sp], #4 800a662: 4770 bx lr 800a664: 58025408 .word 0x58025408 800a668: 5802541c .word 0x5802541c 800a66c: 58025430 .word 0x58025430 800a670: 58025444 .word 0x58025444 800a674: 58025458 .word 0x58025458 800a678: 5802546c .word 0x5802546c 800a67c: 58025480 .word 0x58025480 800a680: 58025494 .word 0x58025494 800a684: cccccccd .word 0xcccccccd 800a688: 16009600 .word 0x16009600 800a68c: 58025880 .word 0x58025880 800a690: aaaaaaab .word 0xaaaaaaab 800a694: 400204b8 .word 0x400204b8 800a698: 4002040f .word 0x4002040f 800a69c: 10008200 .word 0x10008200 800a6a0: 40020880 .word 0x40020880 0800a6a4 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 800a6a4: b480 push {r7} 800a6a6: b085 sub sp, #20 800a6a8: af00 add r7, sp, #0 800a6aa: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 800a6ac: 687b ldr r3, [r7, #4] 800a6ae: 685b ldr r3, [r3, #4] 800a6b0: b2db uxtb r3, r3 800a6b2: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 800a6b4: 68fb ldr r3, [r7, #12] 800a6b6: 2b00 cmp r3, #0 800a6b8: d04a beq.n 800a750 800a6ba: 68fb ldr r3, [r7, #12] 800a6bc: 2b08 cmp r3, #8 800a6be: d847 bhi.n 800a750 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800a6c0: 687b ldr r3, [r7, #4] 800a6c2: 681b ldr r3, [r3, #0] 800a6c4: 4a25 ldr r2, [pc, #148] @ (800a75c ) 800a6c6: 4293 cmp r3, r2 800a6c8: d022 beq.n 800a710 800a6ca: 687b ldr r3, [r7, #4] 800a6cc: 681b ldr r3, [r3, #0] 800a6ce: 4a24 ldr r2, [pc, #144] @ (800a760 ) 800a6d0: 4293 cmp r3, r2 800a6d2: d01d beq.n 800a710 800a6d4: 687b ldr r3, [r7, #4] 800a6d6: 681b ldr r3, [r3, #0] 800a6d8: 4a22 ldr r2, [pc, #136] @ (800a764 ) 800a6da: 4293 cmp r3, r2 800a6dc: d018 beq.n 800a710 800a6de: 687b ldr r3, [r7, #4] 800a6e0: 681b ldr r3, [r3, #0] 800a6e2: 4a21 ldr r2, [pc, #132] @ (800a768 ) 800a6e4: 4293 cmp r3, r2 800a6e6: d013 beq.n 800a710 800a6e8: 687b ldr r3, [r7, #4] 800a6ea: 681b ldr r3, [r3, #0] 800a6ec: 4a1f ldr r2, [pc, #124] @ (800a76c ) 800a6ee: 4293 cmp r3, r2 800a6f0: d00e beq.n 800a710 800a6f2: 687b ldr r3, [r7, #4] 800a6f4: 681b ldr r3, [r3, #0] 800a6f6: 4a1e ldr r2, [pc, #120] @ (800a770 ) 800a6f8: 4293 cmp r3, r2 800a6fa: d009 beq.n 800a710 800a6fc: 687b ldr r3, [r7, #4] 800a6fe: 681b ldr r3, [r3, #0] 800a700: 4a1c ldr r2, [pc, #112] @ (800a774 ) 800a702: 4293 cmp r3, r2 800a704: d004 beq.n 800a710 800a706: 687b ldr r3, [r7, #4] 800a708: 681b ldr r3, [r3, #0] 800a70a: 4a1b ldr r2, [pc, #108] @ (800a778 ) 800a70c: 4293 cmp r3, r2 800a70e: d101 bne.n 800a714 800a710: 2301 movs r3, #1 800a712: e000 b.n 800a716 800a714: 2300 movs r3, #0 800a716: 2b00 cmp r3, #0 800a718: d00a beq.n 800a730 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 800a71a: 68fa ldr r2, [r7, #12] 800a71c: 4b17 ldr r3, [pc, #92] @ (800a77c ) 800a71e: 4413 add r3, r2 800a720: 009b lsls r3, r3, #2 800a722: 461a mov r2, r3 800a724: 687b ldr r3, [r7, #4] 800a726: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 800a728: 687b ldr r3, [r7, #4] 800a72a: 4a15 ldr r2, [pc, #84] @ (800a780 ) 800a72c: 671a str r2, [r3, #112] @ 0x70 800a72e: e009 b.n 800a744 } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800a730: 68fa ldr r2, [r7, #12] 800a732: 4b14 ldr r3, [pc, #80] @ (800a784 ) 800a734: 4413 add r3, r2 800a736: 009b lsls r3, r3, #2 800a738: 461a mov r2, r3 800a73a: 687b ldr r3, [r7, #4] 800a73c: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800a73e: 687b ldr r3, [r7, #4] 800a740: 4a11 ldr r2, [pc, #68] @ (800a788 ) 800a742: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 800a744: 68fb ldr r3, [r7, #12] 800a746: 3b01 subs r3, #1 800a748: 2201 movs r2, #1 800a74a: 409a lsls r2, r3 800a74c: 687b ldr r3, [r7, #4] 800a74e: 675a str r2, [r3, #116] @ 0x74 } } 800a750: bf00 nop 800a752: 3714 adds r7, #20 800a754: 46bd mov sp, r7 800a756: f85d 7b04 ldr.w r7, [sp], #4 800a75a: 4770 bx lr 800a75c: 58025408 .word 0x58025408 800a760: 5802541c .word 0x5802541c 800a764: 58025430 .word 0x58025430 800a768: 58025444 .word 0x58025444 800a76c: 58025458 .word 0x58025458 800a770: 5802546c .word 0x5802546c 800a774: 58025480 .word 0x58025480 800a778: 58025494 .word 0x58025494 800a77c: 1600963f .word 0x1600963f 800a780: 58025940 .word 0x58025940 800a784: 1000823f .word 0x1000823f 800a788: 40020940 .word 0x40020940 0800a78c : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800a78c: b480 push {r7} 800a78e: b089 sub sp, #36 @ 0x24 800a790: af00 add r7, sp, #0 800a792: 6078 str r0, [r7, #4] 800a794: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 800a796: 2300 movs r3, #0 800a798: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 800a79a: 4b89 ldr r3, [pc, #548] @ (800a9c0 ) 800a79c: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 800a79e: e194 b.n 800aaca { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 800a7a0: 683b ldr r3, [r7, #0] 800a7a2: 681a ldr r2, [r3, #0] 800a7a4: 2101 movs r1, #1 800a7a6: 69fb ldr r3, [r7, #28] 800a7a8: fa01 f303 lsl.w r3, r1, r3 800a7ac: 4013 ands r3, r2 800a7ae: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 800a7b0: 693b ldr r3, [r7, #16] 800a7b2: 2b00 cmp r3, #0 800a7b4: f000 8186 beq.w 800aac4 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800a7b8: 683b ldr r3, [r7, #0] 800a7ba: 685b ldr r3, [r3, #4] 800a7bc: f003 0303 and.w r3, r3, #3 800a7c0: 2b01 cmp r3, #1 800a7c2: d005 beq.n 800a7d0 800a7c4: 683b ldr r3, [r7, #0] 800a7c6: 685b ldr r3, [r3, #4] 800a7c8: f003 0303 and.w r3, r3, #3 800a7cc: 2b02 cmp r3, #2 800a7ce: d130 bne.n 800a832 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800a7d0: 687b ldr r3, [r7, #4] 800a7d2: 689b ldr r3, [r3, #8] 800a7d4: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800a7d6: 69fb ldr r3, [r7, #28] 800a7d8: 005b lsls r3, r3, #1 800a7da: 2203 movs r2, #3 800a7dc: fa02 f303 lsl.w r3, r2, r3 800a7e0: 43db mvns r3, r3 800a7e2: 69ba ldr r2, [r7, #24] 800a7e4: 4013 ands r3, r2 800a7e6: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800a7e8: 683b ldr r3, [r7, #0] 800a7ea: 68da ldr r2, [r3, #12] 800a7ec: 69fb ldr r3, [r7, #28] 800a7ee: 005b lsls r3, r3, #1 800a7f0: fa02 f303 lsl.w r3, r2, r3 800a7f4: 69ba ldr r2, [r7, #24] 800a7f6: 4313 orrs r3, r2 800a7f8: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800a7fa: 687b ldr r3, [r7, #4] 800a7fc: 69ba ldr r2, [r7, #24] 800a7fe: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800a800: 687b ldr r3, [r7, #4] 800a802: 685b ldr r3, [r3, #4] 800a804: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800a806: 2201 movs r2, #1 800a808: 69fb ldr r3, [r7, #28] 800a80a: fa02 f303 lsl.w r3, r2, r3 800a80e: 43db mvns r3, r3 800a810: 69ba ldr r2, [r7, #24] 800a812: 4013 ands r3, r2 800a814: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800a816: 683b ldr r3, [r7, #0] 800a818: 685b ldr r3, [r3, #4] 800a81a: 091b lsrs r3, r3, #4 800a81c: f003 0201 and.w r2, r3, #1 800a820: 69fb ldr r3, [r7, #28] 800a822: fa02 f303 lsl.w r3, r2, r3 800a826: 69ba ldr r2, [r7, #24] 800a828: 4313 orrs r3, r2 800a82a: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800a82c: 687b ldr r3, [r7, #4] 800a82e: 69ba ldr r2, [r7, #24] 800a830: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800a832: 683b ldr r3, [r7, #0] 800a834: 685b ldr r3, [r3, #4] 800a836: f003 0303 and.w r3, r3, #3 800a83a: 2b03 cmp r3, #3 800a83c: d017 beq.n 800a86e { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800a83e: 687b ldr r3, [r7, #4] 800a840: 68db ldr r3, [r3, #12] 800a842: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 800a844: 69fb ldr r3, [r7, #28] 800a846: 005b lsls r3, r3, #1 800a848: 2203 movs r2, #3 800a84a: fa02 f303 lsl.w r3, r2, r3 800a84e: 43db mvns r3, r3 800a850: 69ba ldr r2, [r7, #24] 800a852: 4013 ands r3, r2 800a854: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800a856: 683b ldr r3, [r7, #0] 800a858: 689a ldr r2, [r3, #8] 800a85a: 69fb ldr r3, [r7, #28] 800a85c: 005b lsls r3, r3, #1 800a85e: fa02 f303 lsl.w r3, r2, r3 800a862: 69ba ldr r2, [r7, #24] 800a864: 4313 orrs r3, r2 800a866: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800a868: 687b ldr r3, [r7, #4] 800a86a: 69ba ldr r2, [r7, #24] 800a86c: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800a86e: 683b ldr r3, [r7, #0] 800a870: 685b ldr r3, [r3, #4] 800a872: f003 0303 and.w r3, r3, #3 800a876: 2b02 cmp r3, #2 800a878: d123 bne.n 800a8c2 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800a87a: 69fb ldr r3, [r7, #28] 800a87c: 08da lsrs r2, r3, #3 800a87e: 687b ldr r3, [r7, #4] 800a880: 3208 adds r2, #8 800a882: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800a886: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800a888: 69fb ldr r3, [r7, #28] 800a88a: f003 0307 and.w r3, r3, #7 800a88e: 009b lsls r3, r3, #2 800a890: 220f movs r2, #15 800a892: fa02 f303 lsl.w r3, r2, r3 800a896: 43db mvns r3, r3 800a898: 69ba ldr r2, [r7, #24] 800a89a: 4013 ands r3, r2 800a89c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 800a89e: 683b ldr r3, [r7, #0] 800a8a0: 691a ldr r2, [r3, #16] 800a8a2: 69fb ldr r3, [r7, #28] 800a8a4: f003 0307 and.w r3, r3, #7 800a8a8: 009b lsls r3, r3, #2 800a8aa: fa02 f303 lsl.w r3, r2, r3 800a8ae: 69ba ldr r2, [r7, #24] 800a8b0: 4313 orrs r3, r2 800a8b2: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 800a8b4: 69fb ldr r3, [r7, #28] 800a8b6: 08da lsrs r2, r3, #3 800a8b8: 687b ldr r3, [r7, #4] 800a8ba: 3208 adds r2, #8 800a8bc: 69b9 ldr r1, [r7, #24] 800a8be: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800a8c2: 687b ldr r3, [r7, #4] 800a8c4: 681b ldr r3, [r3, #0] 800a8c6: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800a8c8: 69fb ldr r3, [r7, #28] 800a8ca: 005b lsls r3, r3, #1 800a8cc: 2203 movs r2, #3 800a8ce: fa02 f303 lsl.w r3, r2, r3 800a8d2: 43db mvns r3, r3 800a8d4: 69ba ldr r2, [r7, #24] 800a8d6: 4013 ands r3, r2 800a8d8: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800a8da: 683b ldr r3, [r7, #0] 800a8dc: 685b ldr r3, [r3, #4] 800a8de: f003 0203 and.w r2, r3, #3 800a8e2: 69fb ldr r3, [r7, #28] 800a8e4: 005b lsls r3, r3, #1 800a8e6: fa02 f303 lsl.w r3, r2, r3 800a8ea: 69ba ldr r2, [r7, #24] 800a8ec: 4313 orrs r3, r2 800a8ee: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 800a8f0: 687b ldr r3, [r7, #4] 800a8f2: 69ba ldr r2, [r7, #24] 800a8f4: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800a8f6: 683b ldr r3, [r7, #0] 800a8f8: 685b ldr r3, [r3, #4] 800a8fa: f403 3340 and.w r3, r3, #196608 @ 0x30000 800a8fe: 2b00 cmp r3, #0 800a900: f000 80e0 beq.w 800aac4 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800a904: 4b2f ldr r3, [pc, #188] @ (800a9c4 ) 800a906: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800a90a: 4a2e ldr r2, [pc, #184] @ (800a9c4 ) 800a90c: f043 0302 orr.w r3, r3, #2 800a910: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800a914: 4b2b ldr r3, [pc, #172] @ (800a9c4 ) 800a916: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800a91a: f003 0302 and.w r3, r3, #2 800a91e: 60fb str r3, [r7, #12] 800a920: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800a922: 4a29 ldr r2, [pc, #164] @ (800a9c8 ) 800a924: 69fb ldr r3, [r7, #28] 800a926: 089b lsrs r3, r3, #2 800a928: 3302 adds r3, #2 800a92a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800a92e: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800a930: 69fb ldr r3, [r7, #28] 800a932: f003 0303 and.w r3, r3, #3 800a936: 009b lsls r3, r3, #2 800a938: 220f movs r2, #15 800a93a: fa02 f303 lsl.w r3, r2, r3 800a93e: 43db mvns r3, r3 800a940: 69ba ldr r2, [r7, #24] 800a942: 4013 ands r3, r2 800a944: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800a946: 687b ldr r3, [r7, #4] 800a948: 4a20 ldr r2, [pc, #128] @ (800a9cc ) 800a94a: 4293 cmp r3, r2 800a94c: d052 beq.n 800a9f4 800a94e: 687b ldr r3, [r7, #4] 800a950: 4a1f ldr r2, [pc, #124] @ (800a9d0 ) 800a952: 4293 cmp r3, r2 800a954: d031 beq.n 800a9ba 800a956: 687b ldr r3, [r7, #4] 800a958: 4a1e ldr r2, [pc, #120] @ (800a9d4 ) 800a95a: 4293 cmp r3, r2 800a95c: d02b beq.n 800a9b6 800a95e: 687b ldr r3, [r7, #4] 800a960: 4a1d ldr r2, [pc, #116] @ (800a9d8 ) 800a962: 4293 cmp r3, r2 800a964: d025 beq.n 800a9b2 800a966: 687b ldr r3, [r7, #4] 800a968: 4a1c ldr r2, [pc, #112] @ (800a9dc ) 800a96a: 4293 cmp r3, r2 800a96c: d01f beq.n 800a9ae 800a96e: 687b ldr r3, [r7, #4] 800a970: 4a1b ldr r2, [pc, #108] @ (800a9e0 ) 800a972: 4293 cmp r3, r2 800a974: d019 beq.n 800a9aa 800a976: 687b ldr r3, [r7, #4] 800a978: 4a1a ldr r2, [pc, #104] @ (800a9e4 ) 800a97a: 4293 cmp r3, r2 800a97c: d013 beq.n 800a9a6 800a97e: 687b ldr r3, [r7, #4] 800a980: 4a19 ldr r2, [pc, #100] @ (800a9e8 ) 800a982: 4293 cmp r3, r2 800a984: d00d beq.n 800a9a2 800a986: 687b ldr r3, [r7, #4] 800a988: 4a18 ldr r2, [pc, #96] @ (800a9ec ) 800a98a: 4293 cmp r3, r2 800a98c: d007 beq.n 800a99e 800a98e: 687b ldr r3, [r7, #4] 800a990: 4a17 ldr r2, [pc, #92] @ (800a9f0 ) 800a992: 4293 cmp r3, r2 800a994: d101 bne.n 800a99a 800a996: 2309 movs r3, #9 800a998: e02d b.n 800a9f6 800a99a: 230a movs r3, #10 800a99c: e02b b.n 800a9f6 800a99e: 2308 movs r3, #8 800a9a0: e029 b.n 800a9f6 800a9a2: 2307 movs r3, #7 800a9a4: e027 b.n 800a9f6 800a9a6: 2306 movs r3, #6 800a9a8: e025 b.n 800a9f6 800a9aa: 2305 movs r3, #5 800a9ac: e023 b.n 800a9f6 800a9ae: 2304 movs r3, #4 800a9b0: e021 b.n 800a9f6 800a9b2: 2303 movs r3, #3 800a9b4: e01f b.n 800a9f6 800a9b6: 2302 movs r3, #2 800a9b8: e01d b.n 800a9f6 800a9ba: 2301 movs r3, #1 800a9bc: e01b b.n 800a9f6 800a9be: bf00 nop 800a9c0: 58000080 .word 0x58000080 800a9c4: 58024400 .word 0x58024400 800a9c8: 58000400 .word 0x58000400 800a9cc: 58020000 .word 0x58020000 800a9d0: 58020400 .word 0x58020400 800a9d4: 58020800 .word 0x58020800 800a9d8: 58020c00 .word 0x58020c00 800a9dc: 58021000 .word 0x58021000 800a9e0: 58021400 .word 0x58021400 800a9e4: 58021800 .word 0x58021800 800a9e8: 58021c00 .word 0x58021c00 800a9ec: 58022000 .word 0x58022000 800a9f0: 58022400 .word 0x58022400 800a9f4: 2300 movs r3, #0 800a9f6: 69fa ldr r2, [r7, #28] 800a9f8: f002 0203 and.w r2, r2, #3 800a9fc: 0092 lsls r2, r2, #2 800a9fe: 4093 lsls r3, r2 800aa00: 69ba ldr r2, [r7, #24] 800aa02: 4313 orrs r3, r2 800aa04: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800aa06: 4938 ldr r1, [pc, #224] @ (800aae8 ) 800aa08: 69fb ldr r3, [r7, #28] 800aa0a: 089b lsrs r3, r3, #2 800aa0c: 3302 adds r3, #2 800aa0e: 69ba ldr r2, [r7, #24] 800aa10: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800aa14: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aa18: 681b ldr r3, [r3, #0] 800aa1a: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800aa1c: 693b ldr r3, [r7, #16] 800aa1e: 43db mvns r3, r3 800aa20: 69ba ldr r2, [r7, #24] 800aa22: 4013 ands r3, r2 800aa24: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800aa26: 683b ldr r3, [r7, #0] 800aa28: 685b ldr r3, [r3, #4] 800aa2a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800aa2e: 2b00 cmp r3, #0 800aa30: d003 beq.n 800aa3a { temp |= iocurrent; 800aa32: 69ba ldr r2, [r7, #24] 800aa34: 693b ldr r3, [r7, #16] 800aa36: 4313 orrs r3, r2 800aa38: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 800aa3a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800aa3e: 69bb ldr r3, [r7, #24] 800aa40: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800aa42: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800aa46: 685b ldr r3, [r3, #4] 800aa48: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800aa4a: 693b ldr r3, [r7, #16] 800aa4c: 43db mvns r3, r3 800aa4e: 69ba ldr r2, [r7, #24] 800aa50: 4013 ands r3, r2 800aa52: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800aa54: 683b ldr r3, [r7, #0] 800aa56: 685b ldr r3, [r3, #4] 800aa58: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800aa5c: 2b00 cmp r3, #0 800aa5e: d003 beq.n 800aa68 { temp |= iocurrent; 800aa60: 69ba ldr r2, [r7, #24] 800aa62: 693b ldr r3, [r7, #16] 800aa64: 4313 orrs r3, r2 800aa66: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 800aa68: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800aa6c: 69bb ldr r3, [r7, #24] 800aa6e: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800aa70: 697b ldr r3, [r7, #20] 800aa72: 685b ldr r3, [r3, #4] 800aa74: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800aa76: 693b ldr r3, [r7, #16] 800aa78: 43db mvns r3, r3 800aa7a: 69ba ldr r2, [r7, #24] 800aa7c: 4013 ands r3, r2 800aa7e: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800aa80: 683b ldr r3, [r7, #0] 800aa82: 685b ldr r3, [r3, #4] 800aa84: f403 3300 and.w r3, r3, #131072 @ 0x20000 800aa88: 2b00 cmp r3, #0 800aa8a: d003 beq.n 800aa94 { temp |= iocurrent; 800aa8c: 69ba ldr r2, [r7, #24] 800aa8e: 693b ldr r3, [r7, #16] 800aa90: 4313 orrs r3, r2 800aa92: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 800aa94: 697b ldr r3, [r7, #20] 800aa96: 69ba ldr r2, [r7, #24] 800aa98: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 800aa9a: 697b ldr r3, [r7, #20] 800aa9c: 681b ldr r3, [r3, #0] 800aa9e: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800aaa0: 693b ldr r3, [r7, #16] 800aaa2: 43db mvns r3, r3 800aaa4: 69ba ldr r2, [r7, #24] 800aaa6: 4013 ands r3, r2 800aaa8: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 800aaaa: 683b ldr r3, [r7, #0] 800aaac: 685b ldr r3, [r3, #4] 800aaae: f403 3380 and.w r3, r3, #65536 @ 0x10000 800aab2: 2b00 cmp r3, #0 800aab4: d003 beq.n 800aabe { temp |= iocurrent; 800aab6: 69ba ldr r2, [r7, #24] 800aab8: 693b ldr r3, [r7, #16] 800aaba: 4313 orrs r3, r2 800aabc: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 800aabe: 697b ldr r3, [r7, #20] 800aac0: 69ba ldr r2, [r7, #24] 800aac2: 601a str r2, [r3, #0] } } position++; 800aac4: 69fb ldr r3, [r7, #28] 800aac6: 3301 adds r3, #1 800aac8: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 800aaca: 683b ldr r3, [r7, #0] 800aacc: 681a ldr r2, [r3, #0] 800aace: 69fb ldr r3, [r7, #28] 800aad0: fa22 f303 lsr.w r3, r2, r3 800aad4: 2b00 cmp r3, #0 800aad6: f47f ae63 bne.w 800a7a0 } } 800aada: bf00 nop 800aadc: bf00 nop 800aade: 3724 adds r7, #36 @ 0x24 800aae0: 46bd mov sp, r7 800aae2: f85d 7b04 ldr.w r7, [sp], #4 800aae6: 4770 bx lr 800aae8: 58000400 .word 0x58000400 0800aaec : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800aaec: b480 push {r7} 800aaee: b085 sub sp, #20 800aaf0: af00 add r7, sp, #0 800aaf2: 6078 str r0, [r7, #4] 800aaf4: 460b mov r3, r1 800aaf6: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 800aaf8: 687b ldr r3, [r7, #4] 800aafa: 691a ldr r2, [r3, #16] 800aafc: 887b ldrh r3, [r7, #2] 800aafe: 4013 ands r3, r2 800ab00: 2b00 cmp r3, #0 800ab02: d002 beq.n 800ab0a { bitstatus = GPIO_PIN_SET; 800ab04: 2301 movs r3, #1 800ab06: 73fb strb r3, [r7, #15] 800ab08: e001 b.n 800ab0e } else { bitstatus = GPIO_PIN_RESET; 800ab0a: 2300 movs r3, #0 800ab0c: 73fb strb r3, [r7, #15] } return bitstatus; 800ab0e: 7bfb ldrb r3, [r7, #15] } 800ab10: 4618 mov r0, r3 800ab12: 3714 adds r7, #20 800ab14: 46bd mov sp, r7 800ab16: f85d 7b04 ldr.w r7, [sp], #4 800ab1a: 4770 bx lr 0800ab1c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800ab1c: b480 push {r7} 800ab1e: b083 sub sp, #12 800ab20: af00 add r7, sp, #0 800ab22: 6078 str r0, [r7, #4] 800ab24: 460b mov r3, r1 800ab26: 807b strh r3, [r7, #2] 800ab28: 4613 mov r3, r2 800ab2a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800ab2c: 787b ldrb r3, [r7, #1] 800ab2e: 2b00 cmp r3, #0 800ab30: d003 beq.n 800ab3a { GPIOx->BSRR = GPIO_Pin; 800ab32: 887a ldrh r2, [r7, #2] 800ab34: 687b ldr r3, [r7, #4] 800ab36: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 800ab38: e003 b.n 800ab42 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 800ab3a: 887b ldrh r3, [r7, #2] 800ab3c: 041a lsls r2, r3, #16 800ab3e: 687b ldr r3, [r7, #4] 800ab40: 619a str r2, [r3, #24] } 800ab42: bf00 nop 800ab44: 370c adds r7, #12 800ab46: 46bd mov sp, r7 800ab48: f85d 7b04 ldr.w r7, [sp], #4 800ab4c: 4770 bx lr 0800ab4e : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800ab4e: b480 push {r7} 800ab50: b085 sub sp, #20 800ab52: af00 add r7, sp, #0 800ab54: 6078 str r0, [r7, #4] 800ab56: 460b mov r3, r1 800ab58: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 800ab5a: 687b ldr r3, [r7, #4] 800ab5c: 695b ldr r3, [r3, #20] 800ab5e: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800ab60: 887a ldrh r2, [r7, #2] 800ab62: 68fb ldr r3, [r7, #12] 800ab64: 4013 ands r3, r2 800ab66: 041a lsls r2, r3, #16 800ab68: 68fb ldr r3, [r7, #12] 800ab6a: 43d9 mvns r1, r3 800ab6c: 887b ldrh r3, [r7, #2] 800ab6e: 400b ands r3, r1 800ab70: 431a orrs r2, r3 800ab72: 687b ldr r3, [r7, #4] 800ab74: 619a str r2, [r3, #24] } 800ab76: bf00 nop 800ab78: 3714 adds r7, #20 800ab7a: 46bd mov sp, r7 800ab7c: f85d 7b04 ldr.w r7, [sp], #4 800ab80: 4770 bx lr 0800ab82 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 800ab82: b580 push {r7, lr} 800ab84: b082 sub sp, #8 800ab86: af00 add r7, sp, #0 800ab88: 4603 mov r3, r0 800ab8a: 80fb strh r3, [r7, #6] __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 800ab8c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ab90: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800ab94: 88fb ldrh r3, [r7, #6] 800ab96: 4013 ands r3, r2 800ab98: 2b00 cmp r3, #0 800ab9a: d008 beq.n 800abae { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800ab9c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800aba0: 88fb ldrh r3, [r7, #6] 800aba2: f8c2 3088 str.w r3, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 800aba6: 88fb ldrh r3, [r7, #6] 800aba8: 4618 mov r0, r3 800abaa: f7f5 fd7f bl 80006ac } #endif } 800abae: bf00 nop 800abb0: 3708 adds r7, #8 800abb2: 46bd mov sp, r7 800abb4: bd80 pop {r7, pc} ... 0800abb8 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { 800abb8: b480 push {r7} 800abba: b083 sub sp, #12 800abbc: af00 add r7, sp, #0 800abbe: 6078 str r0, [r7, #4] /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 800abc0: 687b ldr r3, [r7, #4] 800abc2: 2b00 cmp r3, #0 800abc4: d069 beq.n 800ac9a /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800abc6: 4b38 ldr r3, [pc, #224] @ (800aca8 ) 800abc8: 681b ldr r3, [r3, #0] 800abca: f023 02e0 bic.w r2, r3, #224 @ 0xe0 800abce: 687b ldr r3, [r7, #4] 800abd0: 681b ldr r3, [r3, #0] 800abd2: 4935 ldr r1, [pc, #212] @ (800aca8 ) 800abd4: 4313 orrs r3, r2 800abd6: 600b str r3, [r1, #0] /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 800abd8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800abdc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800abe0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800abe4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800abe8: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 800abec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800abf0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800abf4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800abf8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800abfc: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 800ac00: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac04: 681b ldr r3, [r3, #0] 800ac06: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac0a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ac0e: 6013 str r3, [r2, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 800ac10: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac14: 685b ldr r3, [r3, #4] 800ac16: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac1a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ac1e: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 800ac20: 687b ldr r3, [r7, #4] 800ac22: 685b ldr r3, [r3, #4] 800ac24: f403 3380 and.w r3, r3, #65536 @ 0x10000 800ac28: 2b00 cmp r3, #0 800ac2a: d009 beq.n 800ac40 { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 800ac2c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac30: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800ac34: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac38: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ac3c: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 800ac40: 687b ldr r3, [r7, #4] 800ac42: 685b ldr r3, [r3, #4] 800ac44: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ac48: 2b00 cmp r3, #0 800ac4a: d009 beq.n 800ac60 { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 800ac4c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac50: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800ac54: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac58: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ac5c: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 800ac60: 687b ldr r3, [r7, #4] 800ac62: 685b ldr r3, [r3, #4] 800ac64: f003 0301 and.w r3, r3, #1 800ac68: 2b00 cmp r3, #0 800ac6a: d007 beq.n 800ac7c { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 800ac6c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac70: 681b ldr r3, [r3, #0] 800ac72: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac76: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ac7a: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 800ac7c: 687b ldr r3, [r7, #4] 800ac7e: 685b ldr r3, [r3, #4] 800ac80: f003 0302 and.w r3, r3, #2 800ac84: 2b00 cmp r3, #0 800ac86: d009 beq.n 800ac9c { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 800ac88: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ac8c: 685b ldr r3, [r3, #4] 800ac8e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ac92: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ac96: 6053 str r3, [r2, #4] 800ac98: e000 b.n 800ac9c return; 800ac9a: bf00 nop } } 800ac9c: 370c adds r7, #12 800ac9e: 46bd mov sp, r7 800aca0: f85d 7b04 ldr.w r7, [sp], #4 800aca4: 4770 bx lr 800aca6: bf00 nop 800aca8: 58024800 .word 0x58024800 0800acac : /** * @brief Enable the Programmable Voltage Detector (PVD). * @retval None. */ void HAL_PWR_EnablePVD (void) { 800acac: b480 push {r7} 800acae: af00 add r7, sp, #0 /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 800acb0: 4b05 ldr r3, [pc, #20] @ (800acc8 ) 800acb2: 681b ldr r3, [r3, #0] 800acb4: 4a04 ldr r2, [pc, #16] @ (800acc8 ) 800acb6: f043 0310 orr.w r3, r3, #16 800acba: 6013 str r3, [r2, #0] } 800acbc: bf00 nop 800acbe: 46bd mov sp, r7 800acc0: f85d 7b04 ldr.w r7, [sp], #4 800acc4: 4770 bx lr 800acc6: bf00 nop 800acc8: 58024800 .word 0x58024800 0800accc : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800accc: b580 push {r7, lr} 800acce: b084 sub sp, #16 800acd0: af00 add r7, sp, #0 800acd2: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800acd4: 4b19 ldr r3, [pc, #100] @ (800ad3c ) 800acd6: 68db ldr r3, [r3, #12] 800acd8: f003 0304 and.w r3, r3, #4 800acdc: 2b04 cmp r3, #4 800acde: d00a beq.n 800acf6 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800ace0: 4b16 ldr r3, [pc, #88] @ (800ad3c ) 800ace2: 68db ldr r3, [r3, #12] 800ace4: f003 0307 and.w r3, r3, #7 800ace8: 687a ldr r2, [r7, #4] 800acea: 429a cmp r2, r3 800acec: d001 beq.n 800acf2 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800acee: 2301 movs r3, #1 800acf0: e01f b.n 800ad32 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800acf2: 2300 movs r3, #0 800acf4: e01d b.n 800ad32 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800acf6: 4b11 ldr r3, [pc, #68] @ (800ad3c ) 800acf8: 68db ldr r3, [r3, #12] 800acfa: f023 0207 bic.w r2, r3, #7 800acfe: 490f ldr r1, [pc, #60] @ (800ad3c ) 800ad00: 687b ldr r3, [r7, #4] 800ad02: 4313 orrs r3, r2 800ad04: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 800ad06: f7fa fb69 bl 80053dc 800ad0a: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800ad0c: e009 b.n 800ad22 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800ad0e: f7fa fb65 bl 80053dc 800ad12: 4602 mov r2, r0 800ad14: 68fb ldr r3, [r7, #12] 800ad16: 1ad3 subs r3, r2, r3 800ad18: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800ad1c: d901 bls.n 800ad22 { return HAL_ERROR; 800ad1e: 2301 movs r3, #1 800ad20: e007 b.n 800ad32 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800ad22: 4b06 ldr r3, [pc, #24] @ (800ad3c ) 800ad24: 685b ldr r3, [r3, #4] 800ad26: f403 5300 and.w r3, r3, #8192 @ 0x2000 800ad2a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ad2e: d1ee bne.n 800ad0e } } } #endif /* defined (SMPS) */ return HAL_OK; 800ad30: 2300 movs r3, #0 } 800ad32: 4618 mov r0, r3 800ad34: 3710 adds r7, #16 800ad36: 46bd mov sp, r7 800ad38: bd80 pop {r7, pc} 800ad3a: bf00 nop 800ad3c: 58024800 .word 0x58024800 0800ad40 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { 800ad40: b480 push {r7} 800ad42: b083 sub sp, #12 800ad44: af00 add r7, sp, #0 800ad46: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800ad48: 4b37 ldr r3, [pc, #220] @ (800ae28 ) 800ad4a: 681b ldr r3, [r3, #0] 800ad4c: f423 22c0 bic.w r2, r3, #393216 @ 0x60000 800ad50: 687b ldr r3, [r7, #4] 800ad52: 681b ldr r3, [r3, #0] 800ad54: 4934 ldr r1, [pc, #208] @ (800ae28 ) 800ad56: 4313 orrs r3, r2 800ad58: 600b str r3, [r1, #0] /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800ad5a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad5e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800ad62: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ad66: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ad6a: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800ad6e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad72: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800ad76: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ad7a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ad7e: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 800ad82: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad86: 681b ldr r3, [r3, #0] 800ad88: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ad8c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ad90: 6013 str r3, [r2, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 800ad92: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ad96: 685b ldr r3, [r3, #4] 800ad98: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ad9c: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ada0: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 800ada2: 687b ldr r3, [r7, #4] 800ada4: 685b ldr r3, [r3, #4] 800ada6: f403 3380 and.w r3, r3, #65536 @ 0x10000 800adaa: 2b00 cmp r3, #0 800adac: d009 beq.n 800adc2 { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800adae: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800adb2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800adb6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800adba: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800adbe: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800adc2: 687b ldr r3, [r7, #4] 800adc4: 685b ldr r3, [r3, #4] 800adc6: f403 3300 and.w r3, r3, #131072 @ 0x20000 800adca: 2b00 cmp r3, #0 800adcc: d009 beq.n 800ade2 { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800adce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800add2: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800add6: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800adda: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800adde: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 800ade2: 687b ldr r3, [r7, #4] 800ade4: 685b ldr r3, [r3, #4] 800ade6: f003 0301 and.w r3, r3, #1 800adea: 2b00 cmp r3, #0 800adec: d007 beq.n 800adfe { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 800adee: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800adf2: 681b ldr r3, [r3, #0] 800adf4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800adf8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800adfc: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 800adfe: 687b ldr r3, [r7, #4] 800ae00: 685b ldr r3, [r3, #4] 800ae02: f003 0302 and.w r3, r3, #2 800ae06: 2b00 cmp r3, #0 800ae08: d007 beq.n 800ae1a { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 800ae0a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800ae0e: 685b ldr r3, [r3, #4] 800ae10: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800ae14: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ae18: 6053 str r3, [r2, #4] } } 800ae1a: bf00 nop 800ae1c: 370c adds r7, #12 800ae1e: 46bd mov sp, r7 800ae20: f85d 7b04 ldr.w r7, [sp], #4 800ae24: 4770 bx lr 800ae26: bf00 nop 800ae28: 58024800 .word 0x58024800 0800ae2c : /** * @brief Enable the Analog Voltage Detector (AVD). * @retval None. */ void HAL_PWREx_EnableAVD (void) { 800ae2c: b480 push {r7} 800ae2e: af00 add r7, sp, #0 /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 800ae30: 4b05 ldr r3, [pc, #20] @ (800ae48 ) 800ae32: 681b ldr r3, [r3, #0] 800ae34: 4a04 ldr r2, [pc, #16] @ (800ae48 ) 800ae36: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ae3a: 6013 str r3, [r2, #0] } 800ae3c: bf00 nop 800ae3e: 46bd mov sp, r7 800ae40: f85d 7b04 ldr.w r7, [sp], #4 800ae44: 4770 bx lr 800ae46: bf00 nop 800ae48: 58024800 .word 0x58024800 0800ae4c : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800ae4c: b580 push {r7, lr} 800ae4e: b08c sub sp, #48 @ 0x30 800ae50: af00 add r7, sp, #0 800ae52: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800ae54: 687b ldr r3, [r7, #4] 800ae56: 2b00 cmp r3, #0 800ae58: d102 bne.n 800ae60 { return HAL_ERROR; 800ae5a: 2301 movs r3, #1 800ae5c: f000 bc48 b.w 800b6f0 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800ae60: 687b ldr r3, [r7, #4] 800ae62: 681b ldr r3, [r3, #0] 800ae64: f003 0301 and.w r3, r3, #1 800ae68: 2b00 cmp r3, #0 800ae6a: f000 8088 beq.w 800af7e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800ae6e: 4b99 ldr r3, [pc, #612] @ (800b0d4 ) 800ae70: 691b ldr r3, [r3, #16] 800ae72: f003 0338 and.w r3, r3, #56 @ 0x38 800ae76: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800ae78: 4b96 ldr r3, [pc, #600] @ (800b0d4 ) 800ae7a: 6a9b ldr r3, [r3, #40] @ 0x28 800ae7c: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800ae7e: 6afb ldr r3, [r7, #44] @ 0x2c 800ae80: 2b10 cmp r3, #16 800ae82: d007 beq.n 800ae94 800ae84: 6afb ldr r3, [r7, #44] @ 0x2c 800ae86: 2b18 cmp r3, #24 800ae88: d111 bne.n 800aeae 800ae8a: 6abb ldr r3, [r7, #40] @ 0x28 800ae8c: f003 0303 and.w r3, r3, #3 800ae90: 2b02 cmp r3, #2 800ae92: d10c bne.n 800aeae { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800ae94: 4b8f ldr r3, [pc, #572] @ (800b0d4 ) 800ae96: 681b ldr r3, [r3, #0] 800ae98: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ae9c: 2b00 cmp r3, #0 800ae9e: d06d beq.n 800af7c 800aea0: 687b ldr r3, [r7, #4] 800aea2: 685b ldr r3, [r3, #4] 800aea4: 2b00 cmp r3, #0 800aea6: d169 bne.n 800af7c { return HAL_ERROR; 800aea8: 2301 movs r3, #1 800aeaa: f000 bc21 b.w 800b6f0 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800aeae: 687b ldr r3, [r7, #4] 800aeb0: 685b ldr r3, [r3, #4] 800aeb2: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800aeb6: d106 bne.n 800aec6 800aeb8: 4b86 ldr r3, [pc, #536] @ (800b0d4 ) 800aeba: 681b ldr r3, [r3, #0] 800aebc: 4a85 ldr r2, [pc, #532] @ (800b0d4 ) 800aebe: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800aec2: 6013 str r3, [r2, #0] 800aec4: e02e b.n 800af24 800aec6: 687b ldr r3, [r7, #4] 800aec8: 685b ldr r3, [r3, #4] 800aeca: 2b00 cmp r3, #0 800aecc: d10c bne.n 800aee8 800aece: 4b81 ldr r3, [pc, #516] @ (800b0d4 ) 800aed0: 681b ldr r3, [r3, #0] 800aed2: 4a80 ldr r2, [pc, #512] @ (800b0d4 ) 800aed4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800aed8: 6013 str r3, [r2, #0] 800aeda: 4b7e ldr r3, [pc, #504] @ (800b0d4 ) 800aedc: 681b ldr r3, [r3, #0] 800aede: 4a7d ldr r2, [pc, #500] @ (800b0d4 ) 800aee0: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800aee4: 6013 str r3, [r2, #0] 800aee6: e01d b.n 800af24 800aee8: 687b ldr r3, [r7, #4] 800aeea: 685b ldr r3, [r3, #4] 800aeec: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800aef0: d10c bne.n 800af0c 800aef2: 4b78 ldr r3, [pc, #480] @ (800b0d4 ) 800aef4: 681b ldr r3, [r3, #0] 800aef6: 4a77 ldr r2, [pc, #476] @ (800b0d4 ) 800aef8: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800aefc: 6013 str r3, [r2, #0] 800aefe: 4b75 ldr r3, [pc, #468] @ (800b0d4 ) 800af00: 681b ldr r3, [r3, #0] 800af02: 4a74 ldr r2, [pc, #464] @ (800b0d4 ) 800af04: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800af08: 6013 str r3, [r2, #0] 800af0a: e00b b.n 800af24 800af0c: 4b71 ldr r3, [pc, #452] @ (800b0d4 ) 800af0e: 681b ldr r3, [r3, #0] 800af10: 4a70 ldr r2, [pc, #448] @ (800b0d4 ) 800af12: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800af16: 6013 str r3, [r2, #0] 800af18: 4b6e ldr r3, [pc, #440] @ (800b0d4 ) 800af1a: 681b ldr r3, [r3, #0] 800af1c: 4a6d ldr r2, [pc, #436] @ (800b0d4 ) 800af1e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800af22: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800af24: 687b ldr r3, [r7, #4] 800af26: 685b ldr r3, [r3, #4] 800af28: 2b00 cmp r3, #0 800af2a: d013 beq.n 800af54 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800af2c: f7fa fa56 bl 80053dc 800af30: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800af32: e008 b.n 800af46 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800af34: f7fa fa52 bl 80053dc 800af38: 4602 mov r2, r0 800af3a: 6a7b ldr r3, [r7, #36] @ 0x24 800af3c: 1ad3 subs r3, r2, r3 800af3e: 2b64 cmp r3, #100 @ 0x64 800af40: d901 bls.n 800af46 { return HAL_TIMEOUT; 800af42: 2303 movs r3, #3 800af44: e3d4 b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800af46: 4b63 ldr r3, [pc, #396] @ (800b0d4 ) 800af48: 681b ldr r3, [r3, #0] 800af4a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800af4e: 2b00 cmp r3, #0 800af50: d0f0 beq.n 800af34 800af52: e014 b.n 800af7e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800af54: f7fa fa42 bl 80053dc 800af58: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800af5a: e008 b.n 800af6e { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800af5c: f7fa fa3e bl 80053dc 800af60: 4602 mov r2, r0 800af62: 6a7b ldr r3, [r7, #36] @ 0x24 800af64: 1ad3 subs r3, r2, r3 800af66: 2b64 cmp r3, #100 @ 0x64 800af68: d901 bls.n 800af6e { return HAL_TIMEOUT; 800af6a: 2303 movs r3, #3 800af6c: e3c0 b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800af6e: 4b59 ldr r3, [pc, #356] @ (800b0d4 ) 800af70: 681b ldr r3, [r3, #0] 800af72: f403 3300 and.w r3, r3, #131072 @ 0x20000 800af76: 2b00 cmp r3, #0 800af78: d1f0 bne.n 800af5c 800af7a: e000 b.n 800af7e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800af7c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800af7e: 687b ldr r3, [r7, #4] 800af80: 681b ldr r3, [r3, #0] 800af82: f003 0302 and.w r3, r3, #2 800af86: 2b00 cmp r3, #0 800af88: f000 80ca beq.w 800b120 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800af8c: 4b51 ldr r3, [pc, #324] @ (800b0d4 ) 800af8e: 691b ldr r3, [r3, #16] 800af90: f003 0338 and.w r3, r3, #56 @ 0x38 800af94: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800af96: 4b4f ldr r3, [pc, #316] @ (800b0d4 ) 800af98: 6a9b ldr r3, [r3, #40] @ 0x28 800af9a: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800af9c: 6a3b ldr r3, [r7, #32] 800af9e: 2b00 cmp r3, #0 800afa0: d007 beq.n 800afb2 800afa2: 6a3b ldr r3, [r7, #32] 800afa4: 2b18 cmp r3, #24 800afa6: d156 bne.n 800b056 800afa8: 69fb ldr r3, [r7, #28] 800afaa: f003 0303 and.w r3, r3, #3 800afae: 2b00 cmp r3, #0 800afb0: d151 bne.n 800b056 { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800afb2: 4b48 ldr r3, [pc, #288] @ (800b0d4 ) 800afb4: 681b ldr r3, [r3, #0] 800afb6: f003 0304 and.w r3, r3, #4 800afba: 2b00 cmp r3, #0 800afbc: d005 beq.n 800afca 800afbe: 687b ldr r3, [r7, #4] 800afc0: 68db ldr r3, [r3, #12] 800afc2: 2b00 cmp r3, #0 800afc4: d101 bne.n 800afca { return HAL_ERROR; 800afc6: 2301 movs r3, #1 800afc8: e392 b.n 800b6f0 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800afca: 4b42 ldr r3, [pc, #264] @ (800b0d4 ) 800afcc: 681b ldr r3, [r3, #0] 800afce: f023 0219 bic.w r2, r3, #25 800afd2: 687b ldr r3, [r7, #4] 800afd4: 68db ldr r3, [r3, #12] 800afd6: 493f ldr r1, [pc, #252] @ (800b0d4 ) 800afd8: 4313 orrs r3, r2 800afda: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800afdc: f7fa f9fe bl 80053dc 800afe0: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800afe2: e008 b.n 800aff6 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800afe4: f7fa f9fa bl 80053dc 800afe8: 4602 mov r2, r0 800afea: 6a7b ldr r3, [r7, #36] @ 0x24 800afec: 1ad3 subs r3, r2, r3 800afee: 2b02 cmp r3, #2 800aff0: d901 bls.n 800aff6 { return HAL_TIMEOUT; 800aff2: 2303 movs r3, #3 800aff4: e37c b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800aff6: 4b37 ldr r3, [pc, #220] @ (800b0d4 ) 800aff8: 681b ldr r3, [r3, #0] 800affa: f003 0304 and.w r3, r3, #4 800affe: 2b00 cmp r3, #0 800b000: d0f0 beq.n 800afe4 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b002: f7fa f9f7 bl 80053f4 800b006: 4603 mov r3, r0 800b008: f241 0203 movw r2, #4099 @ 0x1003 800b00c: 4293 cmp r3, r2 800b00e: d817 bhi.n 800b040 800b010: 687b ldr r3, [r7, #4] 800b012: 691b ldr r3, [r3, #16] 800b014: 2b40 cmp r3, #64 @ 0x40 800b016: d108 bne.n 800b02a 800b018: 4b2e ldr r3, [pc, #184] @ (800b0d4 ) 800b01a: 685b ldr r3, [r3, #4] 800b01c: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800b020: 4a2c ldr r2, [pc, #176] @ (800b0d4 ) 800b022: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b026: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b028: e07a b.n 800b120 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b02a: 4b2a ldr r3, [pc, #168] @ (800b0d4 ) 800b02c: 685b ldr r3, [r3, #4] 800b02e: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800b032: 687b ldr r3, [r7, #4] 800b034: 691b ldr r3, [r3, #16] 800b036: 031b lsls r3, r3, #12 800b038: 4926 ldr r1, [pc, #152] @ (800b0d4 ) 800b03a: 4313 orrs r3, r2 800b03c: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b03e: e06f b.n 800b120 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b040: 4b24 ldr r3, [pc, #144] @ (800b0d4 ) 800b042: 685b ldr r3, [r3, #4] 800b044: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800b048: 687b ldr r3, [r7, #4] 800b04a: 691b ldr r3, [r3, #16] 800b04c: 061b lsls r3, r3, #24 800b04e: 4921 ldr r1, [pc, #132] @ (800b0d4 ) 800b050: 4313 orrs r3, r2 800b052: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800b054: e064 b.n 800b120 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800b056: 687b ldr r3, [r7, #4] 800b058: 68db ldr r3, [r3, #12] 800b05a: 2b00 cmp r3, #0 800b05c: d047 beq.n 800b0ee { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800b05e: 4b1d ldr r3, [pc, #116] @ (800b0d4 ) 800b060: 681b ldr r3, [r3, #0] 800b062: f023 0219 bic.w r2, r3, #25 800b066: 687b ldr r3, [r7, #4] 800b068: 68db ldr r3, [r3, #12] 800b06a: 491a ldr r1, [pc, #104] @ (800b0d4 ) 800b06c: 4313 orrs r3, r2 800b06e: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b070: f7fa f9b4 bl 80053dc 800b074: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b076: e008 b.n 800b08a { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b078: f7fa f9b0 bl 80053dc 800b07c: 4602 mov r2, r0 800b07e: 6a7b ldr r3, [r7, #36] @ 0x24 800b080: 1ad3 subs r3, r2, r3 800b082: 2b02 cmp r3, #2 800b084: d901 bls.n 800b08a { return HAL_TIMEOUT; 800b086: 2303 movs r3, #3 800b088: e332 b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b08a: 4b12 ldr r3, [pc, #72] @ (800b0d4 ) 800b08c: 681b ldr r3, [r3, #0] 800b08e: f003 0304 and.w r3, r3, #4 800b092: 2b00 cmp r3, #0 800b094: d0f0 beq.n 800b078 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800b096: f7fa f9ad bl 80053f4 800b09a: 4603 mov r3, r0 800b09c: f241 0203 movw r2, #4099 @ 0x1003 800b0a0: 4293 cmp r3, r2 800b0a2: d819 bhi.n 800b0d8 800b0a4: 687b ldr r3, [r7, #4] 800b0a6: 691b ldr r3, [r3, #16] 800b0a8: 2b40 cmp r3, #64 @ 0x40 800b0aa: d108 bne.n 800b0be 800b0ac: 4b09 ldr r3, [pc, #36] @ (800b0d4 ) 800b0ae: 685b ldr r3, [r3, #4] 800b0b0: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800b0b4: 4a07 ldr r2, [pc, #28] @ (800b0d4 ) 800b0b6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b0ba: 6053 str r3, [r2, #4] 800b0bc: e030 b.n 800b120 800b0be: 4b05 ldr r3, [pc, #20] @ (800b0d4 ) 800b0c0: 685b ldr r3, [r3, #4] 800b0c2: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800b0c6: 687b ldr r3, [r7, #4] 800b0c8: 691b ldr r3, [r3, #16] 800b0ca: 031b lsls r3, r3, #12 800b0cc: 4901 ldr r1, [pc, #4] @ (800b0d4 ) 800b0ce: 4313 orrs r3, r2 800b0d0: 604b str r3, [r1, #4] 800b0d2: e025 b.n 800b120 800b0d4: 58024400 .word 0x58024400 800b0d8: 4b9a ldr r3, [pc, #616] @ (800b344 ) 800b0da: 685b ldr r3, [r3, #4] 800b0dc: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800b0e0: 687b ldr r3, [r7, #4] 800b0e2: 691b ldr r3, [r3, #16] 800b0e4: 061b lsls r3, r3, #24 800b0e6: 4997 ldr r1, [pc, #604] @ (800b344 ) 800b0e8: 4313 orrs r3, r2 800b0ea: 604b str r3, [r1, #4] 800b0ec: e018 b.n 800b120 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800b0ee: 4b95 ldr r3, [pc, #596] @ (800b344 ) 800b0f0: 681b ldr r3, [r3, #0] 800b0f2: 4a94 ldr r2, [pc, #592] @ (800b344 ) 800b0f4: f023 0301 bic.w r3, r3, #1 800b0f8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b0fa: f7fa f96f bl 80053dc 800b0fe: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800b100: e008 b.n 800b114 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800b102: f7fa f96b bl 80053dc 800b106: 4602 mov r2, r0 800b108: 6a7b ldr r3, [r7, #36] @ 0x24 800b10a: 1ad3 subs r3, r2, r3 800b10c: 2b02 cmp r3, #2 800b10e: d901 bls.n 800b114 { return HAL_TIMEOUT; 800b110: 2303 movs r3, #3 800b112: e2ed b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800b114: 4b8b ldr r3, [pc, #556] @ (800b344 ) 800b116: 681b ldr r3, [r3, #0] 800b118: f003 0304 and.w r3, r3, #4 800b11c: 2b00 cmp r3, #0 800b11e: d1f0 bne.n 800b102 } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800b120: 687b ldr r3, [r7, #4] 800b122: 681b ldr r3, [r3, #0] 800b124: f003 0310 and.w r3, r3, #16 800b128: 2b00 cmp r3, #0 800b12a: f000 80a9 beq.w 800b280 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b12e: 4b85 ldr r3, [pc, #532] @ (800b344 ) 800b130: 691b ldr r3, [r3, #16] 800b132: f003 0338 and.w r3, r3, #56 @ 0x38 800b136: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b138: 4b82 ldr r3, [pc, #520] @ (800b344 ) 800b13a: 6a9b ldr r3, [r3, #40] @ 0x28 800b13c: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800b13e: 69bb ldr r3, [r7, #24] 800b140: 2b08 cmp r3, #8 800b142: d007 beq.n 800b154 800b144: 69bb ldr r3, [r7, #24] 800b146: 2b18 cmp r3, #24 800b148: d13a bne.n 800b1c0 800b14a: 697b ldr r3, [r7, #20] 800b14c: f003 0303 and.w r3, r3, #3 800b150: 2b01 cmp r3, #1 800b152: d135 bne.n 800b1c0 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b154: 4b7b ldr r3, [pc, #492] @ (800b344 ) 800b156: 681b ldr r3, [r3, #0] 800b158: f403 7380 and.w r3, r3, #256 @ 0x100 800b15c: 2b00 cmp r3, #0 800b15e: d005 beq.n 800b16c 800b160: 687b ldr r3, [r7, #4] 800b162: 69db ldr r3, [r3, #28] 800b164: 2b80 cmp r3, #128 @ 0x80 800b166: d001 beq.n 800b16c { return HAL_ERROR; 800b168: 2301 movs r3, #1 800b16a: e2c1 b.n 800b6f0 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b16c: f7fa f942 bl 80053f4 800b170: 4603 mov r3, r0 800b172: f241 0203 movw r2, #4099 @ 0x1003 800b176: 4293 cmp r3, r2 800b178: d817 bhi.n 800b1aa 800b17a: 687b ldr r3, [r7, #4] 800b17c: 6a1b ldr r3, [r3, #32] 800b17e: 2b20 cmp r3, #32 800b180: d108 bne.n 800b194 800b182: 4b70 ldr r3, [pc, #448] @ (800b344 ) 800b184: 685b ldr r3, [r3, #4] 800b186: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800b18a: 4a6e ldr r2, [pc, #440] @ (800b344 ) 800b18c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800b190: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b192: e075 b.n 800b280 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b194: 4b6b ldr r3, [pc, #428] @ (800b344 ) 800b196: 685b ldr r3, [r3, #4] 800b198: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800b19c: 687b ldr r3, [r7, #4] 800b19e: 6a1b ldr r3, [r3, #32] 800b1a0: 069b lsls r3, r3, #26 800b1a2: 4968 ldr r1, [pc, #416] @ (800b344 ) 800b1a4: 4313 orrs r3, r2 800b1a6: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b1a8: e06a b.n 800b280 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b1aa: 4b66 ldr r3, [pc, #408] @ (800b344 ) 800b1ac: 68db ldr r3, [r3, #12] 800b1ae: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800b1b2: 687b ldr r3, [r7, #4] 800b1b4: 6a1b ldr r3, [r3, #32] 800b1b6: 061b lsls r3, r3, #24 800b1b8: 4962 ldr r1, [pc, #392] @ (800b344 ) 800b1ba: 4313 orrs r3, r2 800b1bc: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800b1be: e05f b.n 800b280 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800b1c0: 687b ldr r3, [r7, #4] 800b1c2: 69db ldr r3, [r3, #28] 800b1c4: 2b00 cmp r3, #0 800b1c6: d042 beq.n 800b24e { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800b1c8: 4b5e ldr r3, [pc, #376] @ (800b344 ) 800b1ca: 681b ldr r3, [r3, #0] 800b1cc: 4a5d ldr r2, [pc, #372] @ (800b344 ) 800b1ce: f043 0380 orr.w r3, r3, #128 @ 0x80 800b1d2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b1d4: f7fa f902 bl 80053dc 800b1d8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800b1da: e008 b.n 800b1ee { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800b1dc: f7fa f8fe bl 80053dc 800b1e0: 4602 mov r2, r0 800b1e2: 6a7b ldr r3, [r7, #36] @ 0x24 800b1e4: 1ad3 subs r3, r2, r3 800b1e6: 2b02 cmp r3, #2 800b1e8: d901 bls.n 800b1ee { return HAL_TIMEOUT; 800b1ea: 2303 movs r3, #3 800b1ec: e280 b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800b1ee: 4b55 ldr r3, [pc, #340] @ (800b344 ) 800b1f0: 681b ldr r3, [r3, #0] 800b1f2: f403 7380 and.w r3, r3, #256 @ 0x100 800b1f6: 2b00 cmp r3, #0 800b1f8: d0f0 beq.n 800b1dc } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800b1fa: f7fa f8fb bl 80053f4 800b1fe: 4603 mov r3, r0 800b200: f241 0203 movw r2, #4099 @ 0x1003 800b204: 4293 cmp r3, r2 800b206: d817 bhi.n 800b238 800b208: 687b ldr r3, [r7, #4] 800b20a: 6a1b ldr r3, [r3, #32] 800b20c: 2b20 cmp r3, #32 800b20e: d108 bne.n 800b222 800b210: 4b4c ldr r3, [pc, #304] @ (800b344 ) 800b212: 685b ldr r3, [r3, #4] 800b214: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800b218: 4a4a ldr r2, [pc, #296] @ (800b344 ) 800b21a: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800b21e: 6053 str r3, [r2, #4] 800b220: e02e b.n 800b280 800b222: 4b48 ldr r3, [pc, #288] @ (800b344 ) 800b224: 685b ldr r3, [r3, #4] 800b226: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800b22a: 687b ldr r3, [r7, #4] 800b22c: 6a1b ldr r3, [r3, #32] 800b22e: 069b lsls r3, r3, #26 800b230: 4944 ldr r1, [pc, #272] @ (800b344 ) 800b232: 4313 orrs r3, r2 800b234: 604b str r3, [r1, #4] 800b236: e023 b.n 800b280 800b238: 4b42 ldr r3, [pc, #264] @ (800b344 ) 800b23a: 68db ldr r3, [r3, #12] 800b23c: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800b240: 687b ldr r3, [r7, #4] 800b242: 6a1b ldr r3, [r3, #32] 800b244: 061b lsls r3, r3, #24 800b246: 493f ldr r1, [pc, #252] @ (800b344 ) 800b248: 4313 orrs r3, r2 800b24a: 60cb str r3, [r1, #12] 800b24c: e018 b.n 800b280 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800b24e: 4b3d ldr r3, [pc, #244] @ (800b344 ) 800b250: 681b ldr r3, [r3, #0] 800b252: 4a3c ldr r2, [pc, #240] @ (800b344 ) 800b254: f023 0380 bic.w r3, r3, #128 @ 0x80 800b258: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b25a: f7fa f8bf bl 80053dc 800b25e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800b260: e008 b.n 800b274 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800b262: f7fa f8bb bl 80053dc 800b266: 4602 mov r2, r0 800b268: 6a7b ldr r3, [r7, #36] @ 0x24 800b26a: 1ad3 subs r3, r2, r3 800b26c: 2b02 cmp r3, #2 800b26e: d901 bls.n 800b274 { return HAL_TIMEOUT; 800b270: 2303 movs r3, #3 800b272: e23d b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800b274: 4b33 ldr r3, [pc, #204] @ (800b344 ) 800b276: 681b ldr r3, [r3, #0] 800b278: f403 7380 and.w r3, r3, #256 @ 0x100 800b27c: 2b00 cmp r3, #0 800b27e: d1f0 bne.n 800b262 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800b280: 687b ldr r3, [r7, #4] 800b282: 681b ldr r3, [r3, #0] 800b284: f003 0308 and.w r3, r3, #8 800b288: 2b00 cmp r3, #0 800b28a: d036 beq.n 800b2fa { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800b28c: 687b ldr r3, [r7, #4] 800b28e: 695b ldr r3, [r3, #20] 800b290: 2b00 cmp r3, #0 800b292: d019 beq.n 800b2c8 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800b294: 4b2b ldr r3, [pc, #172] @ (800b344 ) 800b296: 6f5b ldr r3, [r3, #116] @ 0x74 800b298: 4a2a ldr r2, [pc, #168] @ (800b344 ) 800b29a: f043 0301 orr.w r3, r3, #1 800b29e: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b2a0: f7fa f89c bl 80053dc 800b2a4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800b2a6: e008 b.n 800b2ba { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800b2a8: f7fa f898 bl 80053dc 800b2ac: 4602 mov r2, r0 800b2ae: 6a7b ldr r3, [r7, #36] @ 0x24 800b2b0: 1ad3 subs r3, r2, r3 800b2b2: 2b02 cmp r3, #2 800b2b4: d901 bls.n 800b2ba { return HAL_TIMEOUT; 800b2b6: 2303 movs r3, #3 800b2b8: e21a b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800b2ba: 4b22 ldr r3, [pc, #136] @ (800b344 ) 800b2bc: 6f5b ldr r3, [r3, #116] @ 0x74 800b2be: f003 0302 and.w r3, r3, #2 800b2c2: 2b00 cmp r3, #0 800b2c4: d0f0 beq.n 800b2a8 800b2c6: e018 b.n 800b2fa } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800b2c8: 4b1e ldr r3, [pc, #120] @ (800b344 ) 800b2ca: 6f5b ldr r3, [r3, #116] @ 0x74 800b2cc: 4a1d ldr r2, [pc, #116] @ (800b344 ) 800b2ce: f023 0301 bic.w r3, r3, #1 800b2d2: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b2d4: f7fa f882 bl 80053dc 800b2d8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800b2da: e008 b.n 800b2ee { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800b2dc: f7fa f87e bl 80053dc 800b2e0: 4602 mov r2, r0 800b2e2: 6a7b ldr r3, [r7, #36] @ 0x24 800b2e4: 1ad3 subs r3, r2, r3 800b2e6: 2b02 cmp r3, #2 800b2e8: d901 bls.n 800b2ee { return HAL_TIMEOUT; 800b2ea: 2303 movs r3, #3 800b2ec: e200 b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800b2ee: 4b15 ldr r3, [pc, #84] @ (800b344 ) 800b2f0: 6f5b ldr r3, [r3, #116] @ 0x74 800b2f2: f003 0302 and.w r3, r3, #2 800b2f6: 2b00 cmp r3, #0 800b2f8: d1f0 bne.n 800b2dc } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800b2fa: 687b ldr r3, [r7, #4] 800b2fc: 681b ldr r3, [r3, #0] 800b2fe: f003 0320 and.w r3, r3, #32 800b302: 2b00 cmp r3, #0 800b304: d039 beq.n 800b37a { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 800b306: 687b ldr r3, [r7, #4] 800b308: 699b ldr r3, [r3, #24] 800b30a: 2b00 cmp r3, #0 800b30c: d01c beq.n 800b348 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800b30e: 4b0d ldr r3, [pc, #52] @ (800b344 ) 800b310: 681b ldr r3, [r3, #0] 800b312: 4a0c ldr r2, [pc, #48] @ (800b344 ) 800b314: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800b318: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800b31a: f7fa f85f bl 80053dc 800b31e: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800b320: e008 b.n 800b334 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800b322: f7fa f85b bl 80053dc 800b326: 4602 mov r2, r0 800b328: 6a7b ldr r3, [r7, #36] @ 0x24 800b32a: 1ad3 subs r3, r2, r3 800b32c: 2b02 cmp r3, #2 800b32e: d901 bls.n 800b334 { return HAL_TIMEOUT; 800b330: 2303 movs r3, #3 800b332: e1dd b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800b334: 4b03 ldr r3, [pc, #12] @ (800b344 ) 800b336: 681b ldr r3, [r3, #0] 800b338: f403 5300 and.w r3, r3, #8192 @ 0x2000 800b33c: 2b00 cmp r3, #0 800b33e: d0f0 beq.n 800b322 800b340: e01b b.n 800b37a 800b342: bf00 nop 800b344: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800b348: 4b9b ldr r3, [pc, #620] @ (800b5b8 ) 800b34a: 681b ldr r3, [r3, #0] 800b34c: 4a9a ldr r2, [pc, #616] @ (800b5b8 ) 800b34e: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800b352: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800b354: f7fa f842 bl 80053dc 800b358: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800b35a: e008 b.n 800b36e { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800b35c: f7fa f83e bl 80053dc 800b360: 4602 mov r2, r0 800b362: 6a7b ldr r3, [r7, #36] @ 0x24 800b364: 1ad3 subs r3, r2, r3 800b366: 2b02 cmp r3, #2 800b368: d901 bls.n 800b36e { return HAL_TIMEOUT; 800b36a: 2303 movs r3, #3 800b36c: e1c0 b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800b36e: 4b92 ldr r3, [pc, #584] @ (800b5b8 ) 800b370: 681b ldr r3, [r3, #0] 800b372: f403 5300 and.w r3, r3, #8192 @ 0x2000 800b376: 2b00 cmp r3, #0 800b378: d1f0 bne.n 800b35c } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800b37a: 687b ldr r3, [r7, #4] 800b37c: 681b ldr r3, [r3, #0] 800b37e: f003 0304 and.w r3, r3, #4 800b382: 2b00 cmp r3, #0 800b384: f000 8081 beq.w 800b48a { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 800b388: 4b8c ldr r3, [pc, #560] @ (800b5bc ) 800b38a: 681b ldr r3, [r3, #0] 800b38c: 4a8b ldr r2, [pc, #556] @ (800b5bc ) 800b38e: f443 7380 orr.w r3, r3, #256 @ 0x100 800b392: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800b394: f7fa f822 bl 80053dc 800b398: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800b39a: e008 b.n 800b3ae { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800b39c: f7fa f81e bl 80053dc 800b3a0: 4602 mov r2, r0 800b3a2: 6a7b ldr r3, [r7, #36] @ 0x24 800b3a4: 1ad3 subs r3, r2, r3 800b3a6: 2b64 cmp r3, #100 @ 0x64 800b3a8: d901 bls.n 800b3ae { return HAL_TIMEOUT; 800b3aa: 2303 movs r3, #3 800b3ac: e1a0 b.n 800b6f0 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800b3ae: 4b83 ldr r3, [pc, #524] @ (800b5bc ) 800b3b0: 681b ldr r3, [r3, #0] 800b3b2: f403 7380 and.w r3, r3, #256 @ 0x100 800b3b6: 2b00 cmp r3, #0 800b3b8: d0f0 beq.n 800b39c } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800b3ba: 687b ldr r3, [r7, #4] 800b3bc: 689b ldr r3, [r3, #8] 800b3be: 2b01 cmp r3, #1 800b3c0: d106 bne.n 800b3d0 800b3c2: 4b7d ldr r3, [pc, #500] @ (800b5b8 ) 800b3c4: 6f1b ldr r3, [r3, #112] @ 0x70 800b3c6: 4a7c ldr r2, [pc, #496] @ (800b5b8 ) 800b3c8: f043 0301 orr.w r3, r3, #1 800b3cc: 6713 str r3, [r2, #112] @ 0x70 800b3ce: e02d b.n 800b42c 800b3d0: 687b ldr r3, [r7, #4] 800b3d2: 689b ldr r3, [r3, #8] 800b3d4: 2b00 cmp r3, #0 800b3d6: d10c bne.n 800b3f2 800b3d8: 4b77 ldr r3, [pc, #476] @ (800b5b8 ) 800b3da: 6f1b ldr r3, [r3, #112] @ 0x70 800b3dc: 4a76 ldr r2, [pc, #472] @ (800b5b8 ) 800b3de: f023 0301 bic.w r3, r3, #1 800b3e2: 6713 str r3, [r2, #112] @ 0x70 800b3e4: 4b74 ldr r3, [pc, #464] @ (800b5b8 ) 800b3e6: 6f1b ldr r3, [r3, #112] @ 0x70 800b3e8: 4a73 ldr r2, [pc, #460] @ (800b5b8 ) 800b3ea: f023 0304 bic.w r3, r3, #4 800b3ee: 6713 str r3, [r2, #112] @ 0x70 800b3f0: e01c b.n 800b42c 800b3f2: 687b ldr r3, [r7, #4] 800b3f4: 689b ldr r3, [r3, #8] 800b3f6: 2b05 cmp r3, #5 800b3f8: d10c bne.n 800b414 800b3fa: 4b6f ldr r3, [pc, #444] @ (800b5b8 ) 800b3fc: 6f1b ldr r3, [r3, #112] @ 0x70 800b3fe: 4a6e ldr r2, [pc, #440] @ (800b5b8 ) 800b400: f043 0304 orr.w r3, r3, #4 800b404: 6713 str r3, [r2, #112] @ 0x70 800b406: 4b6c ldr r3, [pc, #432] @ (800b5b8 ) 800b408: 6f1b ldr r3, [r3, #112] @ 0x70 800b40a: 4a6b ldr r2, [pc, #428] @ (800b5b8 ) 800b40c: f043 0301 orr.w r3, r3, #1 800b410: 6713 str r3, [r2, #112] @ 0x70 800b412: e00b b.n 800b42c 800b414: 4b68 ldr r3, [pc, #416] @ (800b5b8 ) 800b416: 6f1b ldr r3, [r3, #112] @ 0x70 800b418: 4a67 ldr r2, [pc, #412] @ (800b5b8 ) 800b41a: f023 0301 bic.w r3, r3, #1 800b41e: 6713 str r3, [r2, #112] @ 0x70 800b420: 4b65 ldr r3, [pc, #404] @ (800b5b8 ) 800b422: 6f1b ldr r3, [r3, #112] @ 0x70 800b424: 4a64 ldr r2, [pc, #400] @ (800b5b8 ) 800b426: f023 0304 bic.w r3, r3, #4 800b42a: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800b42c: 687b ldr r3, [r7, #4] 800b42e: 689b ldr r3, [r3, #8] 800b430: 2b00 cmp r3, #0 800b432: d015 beq.n 800b460 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b434: f7f9 ffd2 bl 80053dc 800b438: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800b43a: e00a b.n 800b452 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800b43c: f7f9 ffce bl 80053dc 800b440: 4602 mov r2, r0 800b442: 6a7b ldr r3, [r7, #36] @ 0x24 800b444: 1ad3 subs r3, r2, r3 800b446: f241 3288 movw r2, #5000 @ 0x1388 800b44a: 4293 cmp r3, r2 800b44c: d901 bls.n 800b452 { return HAL_TIMEOUT; 800b44e: 2303 movs r3, #3 800b450: e14e b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800b452: 4b59 ldr r3, [pc, #356] @ (800b5b8 ) 800b454: 6f1b ldr r3, [r3, #112] @ 0x70 800b456: f003 0302 and.w r3, r3, #2 800b45a: 2b00 cmp r3, #0 800b45c: d0ee beq.n 800b43c 800b45e: e014 b.n 800b48a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b460: f7f9 ffbc bl 80053dc 800b464: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800b466: e00a b.n 800b47e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800b468: f7f9 ffb8 bl 80053dc 800b46c: 4602 mov r2, r0 800b46e: 6a7b ldr r3, [r7, #36] @ 0x24 800b470: 1ad3 subs r3, r2, r3 800b472: f241 3288 movw r2, #5000 @ 0x1388 800b476: 4293 cmp r3, r2 800b478: d901 bls.n 800b47e { return HAL_TIMEOUT; 800b47a: 2303 movs r3, #3 800b47c: e138 b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800b47e: 4b4e ldr r3, [pc, #312] @ (800b5b8 ) 800b480: 6f1b ldr r3, [r3, #112] @ 0x70 800b482: f003 0302 and.w r3, r3, #2 800b486: 2b00 cmp r3, #0 800b488: d1ee bne.n 800b468 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800b48a: 687b ldr r3, [r7, #4] 800b48c: 6a5b ldr r3, [r3, #36] @ 0x24 800b48e: 2b00 cmp r3, #0 800b490: f000 812d beq.w 800b6ee { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800b494: 4b48 ldr r3, [pc, #288] @ (800b5b8 ) 800b496: 691b ldr r3, [r3, #16] 800b498: f003 0338 and.w r3, r3, #56 @ 0x38 800b49c: 2b18 cmp r3, #24 800b49e: f000 80bd beq.w 800b61c { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800b4a2: 687b ldr r3, [r7, #4] 800b4a4: 6a5b ldr r3, [r3, #36] @ 0x24 800b4a6: 2b02 cmp r3, #2 800b4a8: f040 809e bne.w 800b5e8 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800b4ac: 4b42 ldr r3, [pc, #264] @ (800b5b8 ) 800b4ae: 681b ldr r3, [r3, #0] 800b4b0: 4a41 ldr r2, [pc, #260] @ (800b5b8 ) 800b4b2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800b4b6: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b4b8: f7f9 ff90 bl 80053dc 800b4bc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800b4be: e008 b.n 800b4d2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800b4c0: f7f9 ff8c bl 80053dc 800b4c4: 4602 mov r2, r0 800b4c6: 6a7b ldr r3, [r7, #36] @ 0x24 800b4c8: 1ad3 subs r3, r2, r3 800b4ca: 2b02 cmp r3, #2 800b4cc: d901 bls.n 800b4d2 { return HAL_TIMEOUT; 800b4ce: 2303 movs r3, #3 800b4d0: e10e b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800b4d2: 4b39 ldr r3, [pc, #228] @ (800b5b8 ) 800b4d4: 681b ldr r3, [r3, #0] 800b4d6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b4da: 2b00 cmp r3, #0 800b4dc: d1f0 bne.n 800b4c0 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800b4de: 4b36 ldr r3, [pc, #216] @ (800b5b8 ) 800b4e0: 6a9a ldr r2, [r3, #40] @ 0x28 800b4e2: 4b37 ldr r3, [pc, #220] @ (800b5c0 ) 800b4e4: 4013 ands r3, r2 800b4e6: 687a ldr r2, [r7, #4] 800b4e8: 6a91 ldr r1, [r2, #40] @ 0x28 800b4ea: 687a ldr r2, [r7, #4] 800b4ec: 6ad2 ldr r2, [r2, #44] @ 0x2c 800b4ee: 0112 lsls r2, r2, #4 800b4f0: 430a orrs r2, r1 800b4f2: 4931 ldr r1, [pc, #196] @ (800b5b8 ) 800b4f4: 4313 orrs r3, r2 800b4f6: 628b str r3, [r1, #40] @ 0x28 800b4f8: 687b ldr r3, [r7, #4] 800b4fa: 6b1b ldr r3, [r3, #48] @ 0x30 800b4fc: 3b01 subs r3, #1 800b4fe: f3c3 0208 ubfx r2, r3, #0, #9 800b502: 687b ldr r3, [r7, #4] 800b504: 6b5b ldr r3, [r3, #52] @ 0x34 800b506: 3b01 subs r3, #1 800b508: 025b lsls r3, r3, #9 800b50a: b29b uxth r3, r3 800b50c: 431a orrs r2, r3 800b50e: 687b ldr r3, [r7, #4] 800b510: 6b9b ldr r3, [r3, #56] @ 0x38 800b512: 3b01 subs r3, #1 800b514: 041b lsls r3, r3, #16 800b516: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800b51a: 431a orrs r2, r3 800b51c: 687b ldr r3, [r7, #4] 800b51e: 6bdb ldr r3, [r3, #60] @ 0x3c 800b520: 3b01 subs r3, #1 800b522: 061b lsls r3, r3, #24 800b524: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800b528: 4923 ldr r1, [pc, #140] @ (800b5b8 ) 800b52a: 4313 orrs r3, r2 800b52c: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800b52e: 4b22 ldr r3, [pc, #136] @ (800b5b8 ) 800b530: 6adb ldr r3, [r3, #44] @ 0x2c 800b532: 4a21 ldr r2, [pc, #132] @ (800b5b8 ) 800b534: f023 0301 bic.w r3, r3, #1 800b538: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800b53a: 4b1f ldr r3, [pc, #124] @ (800b5b8 ) 800b53c: 6b5a ldr r2, [r3, #52] @ 0x34 800b53e: 4b21 ldr r3, [pc, #132] @ (800b5c4 ) 800b540: 4013 ands r3, r2 800b542: 687a ldr r2, [r7, #4] 800b544: 6c92 ldr r2, [r2, #72] @ 0x48 800b546: 00d2 lsls r2, r2, #3 800b548: 491b ldr r1, [pc, #108] @ (800b5b8 ) 800b54a: 4313 orrs r3, r2 800b54c: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800b54e: 4b1a ldr r3, [pc, #104] @ (800b5b8 ) 800b550: 6adb ldr r3, [r3, #44] @ 0x2c 800b552: f023 020c bic.w r2, r3, #12 800b556: 687b ldr r3, [r7, #4] 800b558: 6c1b ldr r3, [r3, #64] @ 0x40 800b55a: 4917 ldr r1, [pc, #92] @ (800b5b8 ) 800b55c: 4313 orrs r3, r2 800b55e: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800b560: 4b15 ldr r3, [pc, #84] @ (800b5b8 ) 800b562: 6adb ldr r3, [r3, #44] @ 0x2c 800b564: f023 0202 bic.w r2, r3, #2 800b568: 687b ldr r3, [r7, #4] 800b56a: 6c5b ldr r3, [r3, #68] @ 0x44 800b56c: 4912 ldr r1, [pc, #72] @ (800b5b8 ) 800b56e: 4313 orrs r3, r2 800b570: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800b572: 4b11 ldr r3, [pc, #68] @ (800b5b8 ) 800b574: 6adb ldr r3, [r3, #44] @ 0x2c 800b576: 4a10 ldr r2, [pc, #64] @ (800b5b8 ) 800b578: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b57c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800b57e: 4b0e ldr r3, [pc, #56] @ (800b5b8 ) 800b580: 6adb ldr r3, [r3, #44] @ 0x2c 800b582: 4a0d ldr r2, [pc, #52] @ (800b5b8 ) 800b584: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800b588: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800b58a: 4b0b ldr r3, [pc, #44] @ (800b5b8 ) 800b58c: 6adb ldr r3, [r3, #44] @ 0x2c 800b58e: 4a0a ldr r2, [pc, #40] @ (800b5b8 ) 800b590: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800b594: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800b596: 4b08 ldr r3, [pc, #32] @ (800b5b8 ) 800b598: 6adb ldr r3, [r3, #44] @ 0x2c 800b59a: 4a07 ldr r2, [pc, #28] @ (800b5b8 ) 800b59c: f043 0301 orr.w r3, r3, #1 800b5a0: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800b5a2: 4b05 ldr r3, [pc, #20] @ (800b5b8 ) 800b5a4: 681b ldr r3, [r3, #0] 800b5a6: 4a04 ldr r2, [pc, #16] @ (800b5b8 ) 800b5a8: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800b5ac: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b5ae: f7f9 ff15 bl 80053dc 800b5b2: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800b5b4: e011 b.n 800b5da 800b5b6: bf00 nop 800b5b8: 58024400 .word 0x58024400 800b5bc: 58024800 .word 0x58024800 800b5c0: fffffc0c .word 0xfffffc0c 800b5c4: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800b5c8: f7f9 ff08 bl 80053dc 800b5cc: 4602 mov r2, r0 800b5ce: 6a7b ldr r3, [r7, #36] @ 0x24 800b5d0: 1ad3 subs r3, r2, r3 800b5d2: 2b02 cmp r3, #2 800b5d4: d901 bls.n 800b5da { return HAL_TIMEOUT; 800b5d6: 2303 movs r3, #3 800b5d8: e08a b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800b5da: 4b47 ldr r3, [pc, #284] @ (800b6f8 ) 800b5dc: 681b ldr r3, [r3, #0] 800b5de: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b5e2: 2b00 cmp r3, #0 800b5e4: d0f0 beq.n 800b5c8 800b5e6: e082 b.n 800b6ee } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800b5e8: 4b43 ldr r3, [pc, #268] @ (800b6f8 ) 800b5ea: 681b ldr r3, [r3, #0] 800b5ec: 4a42 ldr r2, [pc, #264] @ (800b6f8 ) 800b5ee: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800b5f2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b5f4: f7f9 fef2 bl 80053dc 800b5f8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800b5fa: e008 b.n 800b60e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800b5fc: f7f9 feee bl 80053dc 800b600: 4602 mov r2, r0 800b602: 6a7b ldr r3, [r7, #36] @ 0x24 800b604: 1ad3 subs r3, r2, r3 800b606: 2b02 cmp r3, #2 800b608: d901 bls.n 800b60e { return HAL_TIMEOUT; 800b60a: 2303 movs r3, #3 800b60c: e070 b.n 800b6f0 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800b60e: 4b3a ldr r3, [pc, #232] @ (800b6f8 ) 800b610: 681b ldr r3, [r3, #0] 800b612: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b616: 2b00 cmp r3, #0 800b618: d1f0 bne.n 800b5fc 800b61a: e068 b.n 800b6ee } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800b61c: 4b36 ldr r3, [pc, #216] @ (800b6f8 ) 800b61e: 6a9b ldr r3, [r3, #40] @ 0x28 800b620: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800b622: 4b35 ldr r3, [pc, #212] @ (800b6f8 ) 800b624: 6b1b ldr r3, [r3, #48] @ 0x30 800b626: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800b628: 687b ldr r3, [r7, #4] 800b62a: 6a5b ldr r3, [r3, #36] @ 0x24 800b62c: 2b01 cmp r3, #1 800b62e: d031 beq.n 800b694 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800b630: 693b ldr r3, [r7, #16] 800b632: f003 0203 and.w r2, r3, #3 800b636: 687b ldr r3, [r7, #4] 800b638: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800b63a: 429a cmp r2, r3 800b63c: d12a bne.n 800b694 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800b63e: 693b ldr r3, [r7, #16] 800b640: 091b lsrs r3, r3, #4 800b642: f003 023f and.w r2, r3, #63 @ 0x3f 800b646: 687b ldr r3, [r7, #4] 800b648: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800b64a: 429a cmp r2, r3 800b64c: d122 bne.n 800b694 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800b64e: 68fb ldr r3, [r7, #12] 800b650: f3c3 0208 ubfx r2, r3, #0, #9 800b654: 687b ldr r3, [r7, #4] 800b656: 6b1b ldr r3, [r3, #48] @ 0x30 800b658: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800b65a: 429a cmp r2, r3 800b65c: d11a bne.n 800b694 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800b65e: 68fb ldr r3, [r7, #12] 800b660: 0a5b lsrs r3, r3, #9 800b662: f003 027f and.w r2, r3, #127 @ 0x7f 800b666: 687b ldr r3, [r7, #4] 800b668: 6b5b ldr r3, [r3, #52] @ 0x34 800b66a: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800b66c: 429a cmp r2, r3 800b66e: d111 bne.n 800b694 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800b670: 68fb ldr r3, [r7, #12] 800b672: 0c1b lsrs r3, r3, #16 800b674: f003 027f and.w r2, r3, #127 @ 0x7f 800b678: 687b ldr r3, [r7, #4] 800b67a: 6b9b ldr r3, [r3, #56] @ 0x38 800b67c: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800b67e: 429a cmp r2, r3 800b680: d108 bne.n 800b694 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800b682: 68fb ldr r3, [r7, #12] 800b684: 0e1b lsrs r3, r3, #24 800b686: f003 027f and.w r2, r3, #127 @ 0x7f 800b68a: 687b ldr r3, [r7, #4] 800b68c: 6bdb ldr r3, [r3, #60] @ 0x3c 800b68e: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800b690: 429a cmp r2, r3 800b692: d001 beq.n 800b698 { return HAL_ERROR; 800b694: 2301 movs r3, #1 800b696: e02b b.n 800b6f0 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 800b698: 4b17 ldr r3, [pc, #92] @ (800b6f8 ) 800b69a: 6b5b ldr r3, [r3, #52] @ 0x34 800b69c: 08db lsrs r3, r3, #3 800b69e: f3c3 030c ubfx r3, r3, #0, #13 800b6a2: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 800b6a4: 687b ldr r3, [r7, #4] 800b6a6: 6c9b ldr r3, [r3, #72] @ 0x48 800b6a8: 693a ldr r2, [r7, #16] 800b6aa: 429a cmp r2, r3 800b6ac: d01f beq.n 800b6ee { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800b6ae: 4b12 ldr r3, [pc, #72] @ (800b6f8 ) 800b6b0: 6adb ldr r3, [r3, #44] @ 0x2c 800b6b2: 4a11 ldr r2, [pc, #68] @ (800b6f8 ) 800b6b4: f023 0301 bic.w r3, r3, #1 800b6b8: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b6ba: f7f9 fe8f bl 80053dc 800b6be: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 800b6c0: bf00 nop 800b6c2: f7f9 fe8b bl 80053dc 800b6c6: 4602 mov r2, r0 800b6c8: 6a7b ldr r3, [r7, #36] @ 0x24 800b6ca: 4293 cmp r3, r2 800b6cc: d0f9 beq.n 800b6c2 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800b6ce: 4b0a ldr r3, [pc, #40] @ (800b6f8 ) 800b6d0: 6b5a ldr r2, [r3, #52] @ 0x34 800b6d2: 4b0a ldr r3, [pc, #40] @ (800b6fc ) 800b6d4: 4013 ands r3, r2 800b6d6: 687a ldr r2, [r7, #4] 800b6d8: 6c92 ldr r2, [r2, #72] @ 0x48 800b6da: 00d2 lsls r2, r2, #3 800b6dc: 4906 ldr r1, [pc, #24] @ (800b6f8 ) 800b6de: 4313 orrs r3, r2 800b6e0: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 800b6e2: 4b05 ldr r3, [pc, #20] @ (800b6f8 ) 800b6e4: 6adb ldr r3, [r3, #44] @ 0x2c 800b6e6: 4a04 ldr r2, [pc, #16] @ (800b6f8 ) 800b6e8: f043 0301 orr.w r3, r3, #1 800b6ec: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800b6ee: 2300 movs r3, #0 } 800b6f0: 4618 mov r0, r3 800b6f2: 3730 adds r7, #48 @ 0x30 800b6f4: 46bd mov sp, r7 800b6f6: bd80 pop {r7, pc} 800b6f8: 58024400 .word 0x58024400 800b6fc: ffff0007 .word 0xffff0007 0800b700 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800b700: b580 push {r7, lr} 800b702: b086 sub sp, #24 800b704: af00 add r7, sp, #0 800b706: 6078 str r0, [r7, #4] 800b708: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800b70a: 687b ldr r3, [r7, #4] 800b70c: 2b00 cmp r3, #0 800b70e: d101 bne.n 800b714 { return HAL_ERROR; 800b710: 2301 movs r3, #1 800b712: e19c b.n 800ba4e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800b714: 4b8a ldr r3, [pc, #552] @ (800b940 ) 800b716: 681b ldr r3, [r3, #0] 800b718: f003 030f and.w r3, r3, #15 800b71c: 683a ldr r2, [r7, #0] 800b71e: 429a cmp r2, r3 800b720: d910 bls.n 800b744 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800b722: 4b87 ldr r3, [pc, #540] @ (800b940 ) 800b724: 681b ldr r3, [r3, #0] 800b726: f023 020f bic.w r2, r3, #15 800b72a: 4985 ldr r1, [pc, #532] @ (800b940 ) 800b72c: 683b ldr r3, [r7, #0] 800b72e: 4313 orrs r3, r2 800b730: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800b732: 4b83 ldr r3, [pc, #524] @ (800b940 ) 800b734: 681b ldr r3, [r3, #0] 800b736: f003 030f and.w r3, r3, #15 800b73a: 683a ldr r2, [r7, #0] 800b73c: 429a cmp r2, r3 800b73e: d001 beq.n 800b744 { return HAL_ERROR; 800b740: 2301 movs r3, #1 800b742: e184 b.n 800ba4e } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800b744: 687b ldr r3, [r7, #4] 800b746: 681b ldr r3, [r3, #0] 800b748: f003 0304 and.w r3, r3, #4 800b74c: 2b00 cmp r3, #0 800b74e: d010 beq.n 800b772 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800b750: 687b ldr r3, [r7, #4] 800b752: 691a ldr r2, [r3, #16] 800b754: 4b7b ldr r3, [pc, #492] @ (800b944 ) 800b756: 699b ldr r3, [r3, #24] 800b758: f003 0370 and.w r3, r3, #112 @ 0x70 800b75c: 429a cmp r2, r3 800b75e: d908 bls.n 800b772 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800b760: 4b78 ldr r3, [pc, #480] @ (800b944 ) 800b762: 699b ldr r3, [r3, #24] 800b764: f023 0270 bic.w r2, r3, #112 @ 0x70 800b768: 687b ldr r3, [r7, #4] 800b76a: 691b ldr r3, [r3, #16] 800b76c: 4975 ldr r1, [pc, #468] @ (800b944 ) 800b76e: 4313 orrs r3, r2 800b770: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800b772: 687b ldr r3, [r7, #4] 800b774: 681b ldr r3, [r3, #0] 800b776: f003 0308 and.w r3, r3, #8 800b77a: 2b00 cmp r3, #0 800b77c: d010 beq.n 800b7a0 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800b77e: 687b ldr r3, [r7, #4] 800b780: 695a ldr r2, [r3, #20] 800b782: 4b70 ldr r3, [pc, #448] @ (800b944 ) 800b784: 69db ldr r3, [r3, #28] 800b786: f003 0370 and.w r3, r3, #112 @ 0x70 800b78a: 429a cmp r2, r3 800b78c: d908 bls.n 800b7a0 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800b78e: 4b6d ldr r3, [pc, #436] @ (800b944 ) 800b790: 69db ldr r3, [r3, #28] 800b792: f023 0270 bic.w r2, r3, #112 @ 0x70 800b796: 687b ldr r3, [r7, #4] 800b798: 695b ldr r3, [r3, #20] 800b79a: 496a ldr r1, [pc, #424] @ (800b944 ) 800b79c: 4313 orrs r3, r2 800b79e: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800b7a0: 687b ldr r3, [r7, #4] 800b7a2: 681b ldr r3, [r3, #0] 800b7a4: f003 0310 and.w r3, r3, #16 800b7a8: 2b00 cmp r3, #0 800b7aa: d010 beq.n 800b7ce { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800b7ac: 687b ldr r3, [r7, #4] 800b7ae: 699a ldr r2, [r3, #24] 800b7b0: 4b64 ldr r3, [pc, #400] @ (800b944 ) 800b7b2: 69db ldr r3, [r3, #28] 800b7b4: f403 63e0 and.w r3, r3, #1792 @ 0x700 800b7b8: 429a cmp r2, r3 800b7ba: d908 bls.n 800b7ce { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800b7bc: 4b61 ldr r3, [pc, #388] @ (800b944 ) 800b7be: 69db ldr r3, [r3, #28] 800b7c0: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800b7c4: 687b ldr r3, [r7, #4] 800b7c6: 699b ldr r3, [r3, #24] 800b7c8: 495e ldr r1, [pc, #376] @ (800b944 ) 800b7ca: 4313 orrs r3, r2 800b7cc: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800b7ce: 687b ldr r3, [r7, #4] 800b7d0: 681b ldr r3, [r3, #0] 800b7d2: f003 0320 and.w r3, r3, #32 800b7d6: 2b00 cmp r3, #0 800b7d8: d010 beq.n 800b7fc { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800b7da: 687b ldr r3, [r7, #4] 800b7dc: 69da ldr r2, [r3, #28] 800b7de: 4b59 ldr r3, [pc, #356] @ (800b944 ) 800b7e0: 6a1b ldr r3, [r3, #32] 800b7e2: f003 0370 and.w r3, r3, #112 @ 0x70 800b7e6: 429a cmp r2, r3 800b7e8: d908 bls.n 800b7fc { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800b7ea: 4b56 ldr r3, [pc, #344] @ (800b944 ) 800b7ec: 6a1b ldr r3, [r3, #32] 800b7ee: f023 0270 bic.w r2, r3, #112 @ 0x70 800b7f2: 687b ldr r3, [r7, #4] 800b7f4: 69db ldr r3, [r3, #28] 800b7f6: 4953 ldr r1, [pc, #332] @ (800b944 ) 800b7f8: 4313 orrs r3, r2 800b7fa: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800b7fc: 687b ldr r3, [r7, #4] 800b7fe: 681b ldr r3, [r3, #0] 800b800: f003 0302 and.w r3, r3, #2 800b804: 2b00 cmp r3, #0 800b806: d010 beq.n 800b82a { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800b808: 687b ldr r3, [r7, #4] 800b80a: 68da ldr r2, [r3, #12] 800b80c: 4b4d ldr r3, [pc, #308] @ (800b944 ) 800b80e: 699b ldr r3, [r3, #24] 800b810: f003 030f and.w r3, r3, #15 800b814: 429a cmp r2, r3 800b816: d908 bls.n 800b82a { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800b818: 4b4a ldr r3, [pc, #296] @ (800b944 ) 800b81a: 699b ldr r3, [r3, #24] 800b81c: f023 020f bic.w r2, r3, #15 800b820: 687b ldr r3, [r7, #4] 800b822: 68db ldr r3, [r3, #12] 800b824: 4947 ldr r1, [pc, #284] @ (800b944 ) 800b826: 4313 orrs r3, r2 800b828: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800b82a: 687b ldr r3, [r7, #4] 800b82c: 681b ldr r3, [r3, #0] 800b82e: f003 0301 and.w r3, r3, #1 800b832: 2b00 cmp r3, #0 800b834: d055 beq.n 800b8e2 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800b836: 4b43 ldr r3, [pc, #268] @ (800b944 ) 800b838: 699b ldr r3, [r3, #24] 800b83a: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800b83e: 687b ldr r3, [r7, #4] 800b840: 689b ldr r3, [r3, #8] 800b842: 4940 ldr r1, [pc, #256] @ (800b944 ) 800b844: 4313 orrs r3, r2 800b846: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800b848: 687b ldr r3, [r7, #4] 800b84a: 685b ldr r3, [r3, #4] 800b84c: 2b02 cmp r3, #2 800b84e: d107 bne.n 800b860 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800b850: 4b3c ldr r3, [pc, #240] @ (800b944 ) 800b852: 681b ldr r3, [r3, #0] 800b854: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b858: 2b00 cmp r3, #0 800b85a: d121 bne.n 800b8a0 { return HAL_ERROR; 800b85c: 2301 movs r3, #1 800b85e: e0f6 b.n 800ba4e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800b860: 687b ldr r3, [r7, #4] 800b862: 685b ldr r3, [r3, #4] 800b864: 2b03 cmp r3, #3 800b866: d107 bne.n 800b878 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800b868: 4b36 ldr r3, [pc, #216] @ (800b944 ) 800b86a: 681b ldr r3, [r3, #0] 800b86c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800b870: 2b00 cmp r3, #0 800b872: d115 bne.n 800b8a0 { return HAL_ERROR; 800b874: 2301 movs r3, #1 800b876: e0ea b.n 800ba4e } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 800b878: 687b ldr r3, [r7, #4] 800b87a: 685b ldr r3, [r3, #4] 800b87c: 2b01 cmp r3, #1 800b87e: d107 bne.n 800b890 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800b880: 4b30 ldr r3, [pc, #192] @ (800b944 ) 800b882: 681b ldr r3, [r3, #0] 800b884: f403 7380 and.w r3, r3, #256 @ 0x100 800b888: 2b00 cmp r3, #0 800b88a: d109 bne.n 800b8a0 { return HAL_ERROR; 800b88c: 2301 movs r3, #1 800b88e: e0de b.n 800ba4e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800b890: 4b2c ldr r3, [pc, #176] @ (800b944 ) 800b892: 681b ldr r3, [r3, #0] 800b894: f003 0304 and.w r3, r3, #4 800b898: 2b00 cmp r3, #0 800b89a: d101 bne.n 800b8a0 { return HAL_ERROR; 800b89c: 2301 movs r3, #1 800b89e: e0d6 b.n 800ba4e } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800b8a0: 4b28 ldr r3, [pc, #160] @ (800b944 ) 800b8a2: 691b ldr r3, [r3, #16] 800b8a4: f023 0207 bic.w r2, r3, #7 800b8a8: 687b ldr r3, [r7, #4] 800b8aa: 685b ldr r3, [r3, #4] 800b8ac: 4925 ldr r1, [pc, #148] @ (800b944 ) 800b8ae: 4313 orrs r3, r2 800b8b0: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800b8b2: f7f9 fd93 bl 80053dc 800b8b6: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800b8b8: e00a b.n 800b8d0 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800b8ba: f7f9 fd8f bl 80053dc 800b8be: 4602 mov r2, r0 800b8c0: 697b ldr r3, [r7, #20] 800b8c2: 1ad3 subs r3, r2, r3 800b8c4: f241 3288 movw r2, #5000 @ 0x1388 800b8c8: 4293 cmp r3, r2 800b8ca: d901 bls.n 800b8d0 { return HAL_TIMEOUT; 800b8cc: 2303 movs r3, #3 800b8ce: e0be b.n 800ba4e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800b8d0: 4b1c ldr r3, [pc, #112] @ (800b944 ) 800b8d2: 691b ldr r3, [r3, #16] 800b8d4: f003 0238 and.w r2, r3, #56 @ 0x38 800b8d8: 687b ldr r3, [r7, #4] 800b8da: 685b ldr r3, [r3, #4] 800b8dc: 00db lsls r3, r3, #3 800b8de: 429a cmp r2, r3 800b8e0: d1eb bne.n 800b8ba } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800b8e2: 687b ldr r3, [r7, #4] 800b8e4: 681b ldr r3, [r3, #0] 800b8e6: f003 0302 and.w r3, r3, #2 800b8ea: 2b00 cmp r3, #0 800b8ec: d010 beq.n 800b910 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800b8ee: 687b ldr r3, [r7, #4] 800b8f0: 68da ldr r2, [r3, #12] 800b8f2: 4b14 ldr r3, [pc, #80] @ (800b944 ) 800b8f4: 699b ldr r3, [r3, #24] 800b8f6: f003 030f and.w r3, r3, #15 800b8fa: 429a cmp r2, r3 800b8fc: d208 bcs.n 800b910 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800b8fe: 4b11 ldr r3, [pc, #68] @ (800b944 ) 800b900: 699b ldr r3, [r3, #24] 800b902: f023 020f bic.w r2, r3, #15 800b906: 687b ldr r3, [r7, #4] 800b908: 68db ldr r3, [r3, #12] 800b90a: 490e ldr r1, [pc, #56] @ (800b944 ) 800b90c: 4313 orrs r3, r2 800b90e: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800b910: 4b0b ldr r3, [pc, #44] @ (800b940 ) 800b912: 681b ldr r3, [r3, #0] 800b914: f003 030f and.w r3, r3, #15 800b918: 683a ldr r2, [r7, #0] 800b91a: 429a cmp r2, r3 800b91c: d214 bcs.n 800b948 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800b91e: 4b08 ldr r3, [pc, #32] @ (800b940 ) 800b920: 681b ldr r3, [r3, #0] 800b922: f023 020f bic.w r2, r3, #15 800b926: 4906 ldr r1, [pc, #24] @ (800b940 ) 800b928: 683b ldr r3, [r7, #0] 800b92a: 4313 orrs r3, r2 800b92c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800b92e: 4b04 ldr r3, [pc, #16] @ (800b940 ) 800b930: 681b ldr r3, [r3, #0] 800b932: f003 030f and.w r3, r3, #15 800b936: 683a ldr r2, [r7, #0] 800b938: 429a cmp r2, r3 800b93a: d005 beq.n 800b948 { return HAL_ERROR; 800b93c: 2301 movs r3, #1 800b93e: e086 b.n 800ba4e 800b940: 52002000 .word 0x52002000 800b944: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800b948: 687b ldr r3, [r7, #4] 800b94a: 681b ldr r3, [r3, #0] 800b94c: f003 0304 and.w r3, r3, #4 800b950: 2b00 cmp r3, #0 800b952: d010 beq.n 800b976 { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800b954: 687b ldr r3, [r7, #4] 800b956: 691a ldr r2, [r3, #16] 800b958: 4b3f ldr r3, [pc, #252] @ (800ba58 ) 800b95a: 699b ldr r3, [r3, #24] 800b95c: f003 0370 and.w r3, r3, #112 @ 0x70 800b960: 429a cmp r2, r3 800b962: d208 bcs.n 800b976 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800b964: 4b3c ldr r3, [pc, #240] @ (800ba58 ) 800b966: 699b ldr r3, [r3, #24] 800b968: f023 0270 bic.w r2, r3, #112 @ 0x70 800b96c: 687b ldr r3, [r7, #4] 800b96e: 691b ldr r3, [r3, #16] 800b970: 4939 ldr r1, [pc, #228] @ (800ba58 ) 800b972: 4313 orrs r3, r2 800b974: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800b976: 687b ldr r3, [r7, #4] 800b978: 681b ldr r3, [r3, #0] 800b97a: f003 0308 and.w r3, r3, #8 800b97e: 2b00 cmp r3, #0 800b980: d010 beq.n 800b9a4 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800b982: 687b ldr r3, [r7, #4] 800b984: 695a ldr r2, [r3, #20] 800b986: 4b34 ldr r3, [pc, #208] @ (800ba58 ) 800b988: 69db ldr r3, [r3, #28] 800b98a: f003 0370 and.w r3, r3, #112 @ 0x70 800b98e: 429a cmp r2, r3 800b990: d208 bcs.n 800b9a4 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800b992: 4b31 ldr r3, [pc, #196] @ (800ba58 ) 800b994: 69db ldr r3, [r3, #28] 800b996: f023 0270 bic.w r2, r3, #112 @ 0x70 800b99a: 687b ldr r3, [r7, #4] 800b99c: 695b ldr r3, [r3, #20] 800b99e: 492e ldr r1, [pc, #184] @ (800ba58 ) 800b9a0: 4313 orrs r3, r2 800b9a2: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800b9a4: 687b ldr r3, [r7, #4] 800b9a6: 681b ldr r3, [r3, #0] 800b9a8: f003 0310 and.w r3, r3, #16 800b9ac: 2b00 cmp r3, #0 800b9ae: d010 beq.n 800b9d2 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800b9b0: 687b ldr r3, [r7, #4] 800b9b2: 699a ldr r2, [r3, #24] 800b9b4: 4b28 ldr r3, [pc, #160] @ (800ba58 ) 800b9b6: 69db ldr r3, [r3, #28] 800b9b8: f403 63e0 and.w r3, r3, #1792 @ 0x700 800b9bc: 429a cmp r2, r3 800b9be: d208 bcs.n 800b9d2 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800b9c0: 4b25 ldr r3, [pc, #148] @ (800ba58 ) 800b9c2: 69db ldr r3, [r3, #28] 800b9c4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800b9c8: 687b ldr r3, [r7, #4] 800b9ca: 699b ldr r3, [r3, #24] 800b9cc: 4922 ldr r1, [pc, #136] @ (800ba58 ) 800b9ce: 4313 orrs r3, r2 800b9d0: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800b9d2: 687b ldr r3, [r7, #4] 800b9d4: 681b ldr r3, [r3, #0] 800b9d6: f003 0320 and.w r3, r3, #32 800b9da: 2b00 cmp r3, #0 800b9dc: d010 beq.n 800ba00 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800b9de: 687b ldr r3, [r7, #4] 800b9e0: 69da ldr r2, [r3, #28] 800b9e2: 4b1d ldr r3, [pc, #116] @ (800ba58 ) 800b9e4: 6a1b ldr r3, [r3, #32] 800b9e6: f003 0370 and.w r3, r3, #112 @ 0x70 800b9ea: 429a cmp r2, r3 800b9ec: d208 bcs.n 800ba00 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800b9ee: 4b1a ldr r3, [pc, #104] @ (800ba58 ) 800b9f0: 6a1b ldr r3, [r3, #32] 800b9f2: f023 0270 bic.w r2, r3, #112 @ 0x70 800b9f6: 687b ldr r3, [r7, #4] 800b9f8: 69db ldr r3, [r3, #28] 800b9fa: 4917 ldr r1, [pc, #92] @ (800ba58 ) 800b9fc: 4313 orrs r3, r2 800b9fe: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 800ba00: f000 f834 bl 800ba6c 800ba04: 4602 mov r2, r0 800ba06: 4b14 ldr r3, [pc, #80] @ (800ba58 ) 800ba08: 699b ldr r3, [r3, #24] 800ba0a: 0a1b lsrs r3, r3, #8 800ba0c: f003 030f and.w r3, r3, #15 800ba10: 4912 ldr r1, [pc, #72] @ (800ba5c ) 800ba12: 5ccb ldrb r3, [r1, r3] 800ba14: f003 031f and.w r3, r3, #31 800ba18: fa22 f303 lsr.w r3, r2, r3 800ba1c: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800ba1e: 4b0e ldr r3, [pc, #56] @ (800ba58 ) 800ba20: 699b ldr r3, [r3, #24] 800ba22: f003 030f and.w r3, r3, #15 800ba26: 4a0d ldr r2, [pc, #52] @ (800ba5c ) 800ba28: 5cd3 ldrb r3, [r2, r3] 800ba2a: f003 031f and.w r3, r3, #31 800ba2e: 693a ldr r2, [r7, #16] 800ba30: fa22 f303 lsr.w r3, r2, r3 800ba34: 4a0a ldr r2, [pc, #40] @ (800ba60 ) 800ba36: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800ba38: 4a0a ldr r2, [pc, #40] @ (800ba64 ) 800ba3a: 693b ldr r3, [r7, #16] 800ba3c: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800ba3e: 4b0a ldr r3, [pc, #40] @ (800ba68 ) 800ba40: 681b ldr r3, [r3, #0] 800ba42: 4618 mov r0, r3 800ba44: f7f8 f9a2 bl 8003d8c 800ba48: 4603 mov r3, r0 800ba4a: 73fb strb r3, [r7, #15] return halstatus; 800ba4c: 7bfb ldrb r3, [r7, #15] } 800ba4e: 4618 mov r0, r3 800ba50: 3718 adds r7, #24 800ba52: 46bd mov sp, r7 800ba54: bd80 pop {r7, pc} 800ba56: bf00 nop 800ba58: 58024400 .word 0x58024400 800ba5c: 080189c8 .word 0x080189c8 800ba60: 24000038 .word 0x24000038 800ba64: 24000034 .word 0x24000034 800ba68: 2400003c .word 0x2400003c 0800ba6c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800ba6c: b480 push {r7} 800ba6e: b089 sub sp, #36 @ 0x24 800ba70: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800ba72: 4bb3 ldr r3, [pc, #716] @ (800bd40 ) 800ba74: 691b ldr r3, [r3, #16] 800ba76: f003 0338 and.w r3, r3, #56 @ 0x38 800ba7a: 2b18 cmp r3, #24 800ba7c: f200 8155 bhi.w 800bd2a 800ba80: a201 add r2, pc, #4 @ (adr r2, 800ba88 ) 800ba82: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ba86: bf00 nop 800ba88: 0800baed .word 0x0800baed 800ba8c: 0800bd2b .word 0x0800bd2b 800ba90: 0800bd2b .word 0x0800bd2b 800ba94: 0800bd2b .word 0x0800bd2b 800ba98: 0800bd2b .word 0x0800bd2b 800ba9c: 0800bd2b .word 0x0800bd2b 800baa0: 0800bd2b .word 0x0800bd2b 800baa4: 0800bd2b .word 0x0800bd2b 800baa8: 0800bb13 .word 0x0800bb13 800baac: 0800bd2b .word 0x0800bd2b 800bab0: 0800bd2b .word 0x0800bd2b 800bab4: 0800bd2b .word 0x0800bd2b 800bab8: 0800bd2b .word 0x0800bd2b 800babc: 0800bd2b .word 0x0800bd2b 800bac0: 0800bd2b .word 0x0800bd2b 800bac4: 0800bd2b .word 0x0800bd2b 800bac8: 0800bb19 .word 0x0800bb19 800bacc: 0800bd2b .word 0x0800bd2b 800bad0: 0800bd2b .word 0x0800bd2b 800bad4: 0800bd2b .word 0x0800bd2b 800bad8: 0800bd2b .word 0x0800bd2b 800badc: 0800bd2b .word 0x0800bd2b 800bae0: 0800bd2b .word 0x0800bd2b 800bae4: 0800bd2b .word 0x0800bd2b 800bae8: 0800bb1f .word 0x0800bb1f { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800baec: 4b94 ldr r3, [pc, #592] @ (800bd40 ) 800baee: 681b ldr r3, [r3, #0] 800baf0: f003 0320 and.w r3, r3, #32 800baf4: 2b00 cmp r3, #0 800baf6: d009 beq.n 800bb0c { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800baf8: 4b91 ldr r3, [pc, #580] @ (800bd40 ) 800bafa: 681b ldr r3, [r3, #0] 800bafc: 08db lsrs r3, r3, #3 800bafe: f003 0303 and.w r3, r3, #3 800bb02: 4a90 ldr r2, [pc, #576] @ (800bd44 ) 800bb04: fa22 f303 lsr.w r3, r2, r3 800bb08: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800bb0a: e111 b.n 800bd30 sysclockfreq = (uint32_t) HSI_VALUE; 800bb0c: 4b8d ldr r3, [pc, #564] @ (800bd44 ) 800bb0e: 61bb str r3, [r7, #24] break; 800bb10: e10e b.n 800bd30 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 800bb12: 4b8d ldr r3, [pc, #564] @ (800bd48 ) 800bb14: 61bb str r3, [r7, #24] break; 800bb16: e10b b.n 800bd30 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 800bb18: 4b8c ldr r3, [pc, #560] @ (800bd4c ) 800bb1a: 61bb str r3, [r7, #24] break; 800bb1c: e108 b.n 800bd30 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800bb1e: 4b88 ldr r3, [pc, #544] @ (800bd40 ) 800bb20: 6a9b ldr r3, [r3, #40] @ 0x28 800bb22: f003 0303 and.w r3, r3, #3 800bb26: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800bb28: 4b85 ldr r3, [pc, #532] @ (800bd40 ) 800bb2a: 6a9b ldr r3, [r3, #40] @ 0x28 800bb2c: 091b lsrs r3, r3, #4 800bb2e: f003 033f and.w r3, r3, #63 @ 0x3f 800bb32: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 800bb34: 4b82 ldr r3, [pc, #520] @ (800bd40 ) 800bb36: 6adb ldr r3, [r3, #44] @ 0x2c 800bb38: f003 0301 and.w r3, r3, #1 800bb3c: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800bb3e: 4b80 ldr r3, [pc, #512] @ (800bd40 ) 800bb40: 6b5b ldr r3, [r3, #52] @ 0x34 800bb42: 08db lsrs r3, r3, #3 800bb44: f3c3 030c ubfx r3, r3, #0, #13 800bb48: 68fa ldr r2, [r7, #12] 800bb4a: fb02 f303 mul.w r3, r2, r3 800bb4e: ee07 3a90 vmov s15, r3 800bb52: eef8 7a67 vcvt.f32.u32 s15, s15 800bb56: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800bb5a: 693b ldr r3, [r7, #16] 800bb5c: 2b00 cmp r3, #0 800bb5e: f000 80e1 beq.w 800bd24 800bb62: 697b ldr r3, [r7, #20] 800bb64: 2b02 cmp r3, #2 800bb66: f000 8083 beq.w 800bc70 800bb6a: 697b ldr r3, [r7, #20] 800bb6c: 2b02 cmp r3, #2 800bb6e: f200 80a1 bhi.w 800bcb4 800bb72: 697b ldr r3, [r7, #20] 800bb74: 2b00 cmp r3, #0 800bb76: d003 beq.n 800bb80 800bb78: 697b ldr r3, [r7, #20] 800bb7a: 2b01 cmp r3, #1 800bb7c: d056 beq.n 800bc2c 800bb7e: e099 b.n 800bcb4 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800bb80: 4b6f ldr r3, [pc, #444] @ (800bd40 ) 800bb82: 681b ldr r3, [r3, #0] 800bb84: f003 0320 and.w r3, r3, #32 800bb88: 2b00 cmp r3, #0 800bb8a: d02d beq.n 800bbe8 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800bb8c: 4b6c ldr r3, [pc, #432] @ (800bd40 ) 800bb8e: 681b ldr r3, [r3, #0] 800bb90: 08db lsrs r3, r3, #3 800bb92: f003 0303 and.w r3, r3, #3 800bb96: 4a6b ldr r2, [pc, #428] @ (800bd44 ) 800bb98: fa22 f303 lsr.w r3, r2, r3 800bb9c: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800bb9e: 687b ldr r3, [r7, #4] 800bba0: ee07 3a90 vmov s15, r3 800bba4: eef8 6a67 vcvt.f32.u32 s13, s15 800bba8: 693b ldr r3, [r7, #16] 800bbaa: ee07 3a90 vmov s15, r3 800bbae: eef8 7a67 vcvt.f32.u32 s15, s15 800bbb2: ee86 7aa7 vdiv.f32 s14, s13, s15 800bbb6: 4b62 ldr r3, [pc, #392] @ (800bd40 ) 800bbb8: 6b1b ldr r3, [r3, #48] @ 0x30 800bbba: f3c3 0308 ubfx r3, r3, #0, #9 800bbbe: ee07 3a90 vmov s15, r3 800bbc2: eef8 6a67 vcvt.f32.u32 s13, s15 800bbc6: ed97 6a02 vldr s12, [r7, #8] 800bbca: eddf 5a61 vldr s11, [pc, #388] @ 800bd50 800bbce: eec6 7a25 vdiv.f32 s15, s12, s11 800bbd2: ee76 7aa7 vadd.f32 s15, s13, s15 800bbd6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800bbda: ee77 7aa6 vadd.f32 s15, s15, s13 800bbde: ee67 7a27 vmul.f32 s15, s14, s15 800bbe2: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800bbe6: e087 b.n 800bcf8 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800bbe8: 693b ldr r3, [r7, #16] 800bbea: ee07 3a90 vmov s15, r3 800bbee: eef8 7a67 vcvt.f32.u32 s15, s15 800bbf2: eddf 6a58 vldr s13, [pc, #352] @ 800bd54 800bbf6: ee86 7aa7 vdiv.f32 s14, s13, s15 800bbfa: 4b51 ldr r3, [pc, #324] @ (800bd40 ) 800bbfc: 6b1b ldr r3, [r3, #48] @ 0x30 800bbfe: f3c3 0308 ubfx r3, r3, #0, #9 800bc02: ee07 3a90 vmov s15, r3 800bc06: eef8 6a67 vcvt.f32.u32 s13, s15 800bc0a: ed97 6a02 vldr s12, [r7, #8] 800bc0e: eddf 5a50 vldr s11, [pc, #320] @ 800bd50 800bc12: eec6 7a25 vdiv.f32 s15, s12, s11 800bc16: ee76 7aa7 vadd.f32 s15, s13, s15 800bc1a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800bc1e: ee77 7aa6 vadd.f32 s15, s15, s13 800bc22: ee67 7a27 vmul.f32 s15, s14, s15 800bc26: edc7 7a07 vstr s15, [r7, #28] break; 800bc2a: e065 b.n 800bcf8 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800bc2c: 693b ldr r3, [r7, #16] 800bc2e: ee07 3a90 vmov s15, r3 800bc32: eef8 7a67 vcvt.f32.u32 s15, s15 800bc36: eddf 6a48 vldr s13, [pc, #288] @ 800bd58 800bc3a: ee86 7aa7 vdiv.f32 s14, s13, s15 800bc3e: 4b40 ldr r3, [pc, #256] @ (800bd40 ) 800bc40: 6b1b ldr r3, [r3, #48] @ 0x30 800bc42: f3c3 0308 ubfx r3, r3, #0, #9 800bc46: ee07 3a90 vmov s15, r3 800bc4a: eef8 6a67 vcvt.f32.u32 s13, s15 800bc4e: ed97 6a02 vldr s12, [r7, #8] 800bc52: eddf 5a3f vldr s11, [pc, #252] @ 800bd50 800bc56: eec6 7a25 vdiv.f32 s15, s12, s11 800bc5a: ee76 7aa7 vadd.f32 s15, s13, s15 800bc5e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800bc62: ee77 7aa6 vadd.f32 s15, s15, s13 800bc66: ee67 7a27 vmul.f32 s15, s14, s15 800bc6a: edc7 7a07 vstr s15, [r7, #28] break; 800bc6e: e043 b.n 800bcf8 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800bc70: 693b ldr r3, [r7, #16] 800bc72: ee07 3a90 vmov s15, r3 800bc76: eef8 7a67 vcvt.f32.u32 s15, s15 800bc7a: eddf 6a38 vldr s13, [pc, #224] @ 800bd5c 800bc7e: ee86 7aa7 vdiv.f32 s14, s13, s15 800bc82: 4b2f ldr r3, [pc, #188] @ (800bd40 ) 800bc84: 6b1b ldr r3, [r3, #48] @ 0x30 800bc86: f3c3 0308 ubfx r3, r3, #0, #9 800bc8a: ee07 3a90 vmov s15, r3 800bc8e: eef8 6a67 vcvt.f32.u32 s13, s15 800bc92: ed97 6a02 vldr s12, [r7, #8] 800bc96: eddf 5a2e vldr s11, [pc, #184] @ 800bd50 800bc9a: eec6 7a25 vdiv.f32 s15, s12, s11 800bc9e: ee76 7aa7 vadd.f32 s15, s13, s15 800bca2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800bca6: ee77 7aa6 vadd.f32 s15, s15, s13 800bcaa: ee67 7a27 vmul.f32 s15, s14, s15 800bcae: edc7 7a07 vstr s15, [r7, #28] break; 800bcb2: e021 b.n 800bcf8 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800bcb4: 693b ldr r3, [r7, #16] 800bcb6: ee07 3a90 vmov s15, r3 800bcba: eef8 7a67 vcvt.f32.u32 s15, s15 800bcbe: eddf 6a26 vldr s13, [pc, #152] @ 800bd58 800bcc2: ee86 7aa7 vdiv.f32 s14, s13, s15 800bcc6: 4b1e ldr r3, [pc, #120] @ (800bd40 ) 800bcc8: 6b1b ldr r3, [r3, #48] @ 0x30 800bcca: f3c3 0308 ubfx r3, r3, #0, #9 800bcce: ee07 3a90 vmov s15, r3 800bcd2: eef8 6a67 vcvt.f32.u32 s13, s15 800bcd6: ed97 6a02 vldr s12, [r7, #8] 800bcda: eddf 5a1d vldr s11, [pc, #116] @ 800bd50 800bcde: eec6 7a25 vdiv.f32 s15, s12, s11 800bce2: ee76 7aa7 vadd.f32 s15, s13, s15 800bce6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800bcea: ee77 7aa6 vadd.f32 s15, s15, s13 800bcee: ee67 7a27 vmul.f32 s15, s14, s15 800bcf2: edc7 7a07 vstr s15, [r7, #28] break; 800bcf6: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800bcf8: 4b11 ldr r3, [pc, #68] @ (800bd40 ) 800bcfa: 6b1b ldr r3, [r3, #48] @ 0x30 800bcfc: 0a5b lsrs r3, r3, #9 800bcfe: f003 037f and.w r3, r3, #127 @ 0x7f 800bd02: 3301 adds r3, #1 800bd04: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800bd06: 683b ldr r3, [r7, #0] 800bd08: ee07 3a90 vmov s15, r3 800bd0c: eeb8 7a67 vcvt.f32.u32 s14, s15 800bd10: edd7 6a07 vldr s13, [r7, #28] 800bd14: eec6 7a87 vdiv.f32 s15, s13, s14 800bd18: eefc 7ae7 vcvt.u32.f32 s15, s15 800bd1c: ee17 3a90 vmov r3, s15 800bd20: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 800bd22: e005 b.n 800bd30 sysclockfreq = 0U; 800bd24: 2300 movs r3, #0 800bd26: 61bb str r3, [r7, #24] break; 800bd28: e002 b.n 800bd30 default: sysclockfreq = CSI_VALUE; 800bd2a: 4b07 ldr r3, [pc, #28] @ (800bd48 ) 800bd2c: 61bb str r3, [r7, #24] break; 800bd2e: bf00 nop } return sysclockfreq; 800bd30: 69bb ldr r3, [r7, #24] } 800bd32: 4618 mov r0, r3 800bd34: 3724 adds r7, #36 @ 0x24 800bd36: 46bd mov sp, r7 800bd38: f85d 7b04 ldr.w r7, [sp], #4 800bd3c: 4770 bx lr 800bd3e: bf00 nop 800bd40: 58024400 .word 0x58024400 800bd44: 03d09000 .word 0x03d09000 800bd48: 003d0900 .word 0x003d0900 800bd4c: 017d7840 .word 0x017d7840 800bd50: 46000000 .word 0x46000000 800bd54: 4c742400 .word 0x4c742400 800bd58: 4a742400 .word 0x4a742400 800bd5c: 4bbebc20 .word 0x4bbebc20 0800bd60 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800bd60: b580 push {r7, lr} 800bd62: b082 sub sp, #8 800bd64: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 800bd66: f7ff fe81 bl 800ba6c 800bd6a: 4602 mov r2, r0 800bd6c: 4b10 ldr r3, [pc, #64] @ (800bdb0 ) 800bd6e: 699b ldr r3, [r3, #24] 800bd70: 0a1b lsrs r3, r3, #8 800bd72: f003 030f and.w r3, r3, #15 800bd76: 490f ldr r1, [pc, #60] @ (800bdb4 ) 800bd78: 5ccb ldrb r3, [r1, r3] 800bd7a: f003 031f and.w r3, r3, #31 800bd7e: fa22 f303 lsr.w r3, r2, r3 800bd82: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800bd84: 4b0a ldr r3, [pc, #40] @ (800bdb0 ) 800bd86: 699b ldr r3, [r3, #24] 800bd88: f003 030f and.w r3, r3, #15 800bd8c: 4a09 ldr r2, [pc, #36] @ (800bdb4 ) 800bd8e: 5cd3 ldrb r3, [r2, r3] 800bd90: f003 031f and.w r3, r3, #31 800bd94: 687a ldr r2, [r7, #4] 800bd96: fa22 f303 lsr.w r3, r2, r3 800bd9a: 4a07 ldr r2, [pc, #28] @ (800bdb8 ) 800bd9c: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800bd9e: 4a07 ldr r2, [pc, #28] @ (800bdbc ) 800bda0: 687b ldr r3, [r7, #4] 800bda2: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800bda4: 4b04 ldr r3, [pc, #16] @ (800bdb8 ) 800bda6: 681b ldr r3, [r3, #0] } 800bda8: 4618 mov r0, r3 800bdaa: 3708 adds r7, #8 800bdac: 46bd mov sp, r7 800bdae: bd80 pop {r7, pc} 800bdb0: 58024400 .word 0x58024400 800bdb4: 080189c8 .word 0x080189c8 800bdb8: 24000038 .word 0x24000038 800bdbc: 24000034 .word 0x24000034 0800bdc0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800bdc0: b580 push {r7, lr} 800bdc2: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 800bdc4: f7ff ffcc bl 800bd60 800bdc8: 4602 mov r2, r0 800bdca: 4b06 ldr r3, [pc, #24] @ (800bde4 ) 800bdcc: 69db ldr r3, [r3, #28] 800bdce: 091b lsrs r3, r3, #4 800bdd0: f003 0307 and.w r3, r3, #7 800bdd4: 4904 ldr r1, [pc, #16] @ (800bde8 ) 800bdd6: 5ccb ldrb r3, [r1, r3] 800bdd8: f003 031f and.w r3, r3, #31 800bddc: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 800bde0: 4618 mov r0, r3 800bde2: bd80 pop {r7, pc} 800bde4: 58024400 .word 0x58024400 800bde8: 080189c8 .word 0x080189c8 0800bdec : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800bdec: b580 push {r7, lr} 800bdee: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 800bdf0: f7ff ffb6 bl 800bd60 800bdf4: 4602 mov r2, r0 800bdf6: 4b06 ldr r3, [pc, #24] @ (800be10 ) 800bdf8: 69db ldr r3, [r3, #28] 800bdfa: 0a1b lsrs r3, r3, #8 800bdfc: f003 0307 and.w r3, r3, #7 800be00: 4904 ldr r1, [pc, #16] @ (800be14 ) 800be02: 5ccb ldrb r3, [r1, r3] 800be04: f003 031f and.w r3, r3, #31 800be08: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800be0c: 4618 mov r0, r3 800be0e: bd80 pop {r7, pc} 800be10: 58024400 .word 0x58024400 800be14: 080189c8 .word 0x080189c8 0800be18 : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800be18: b480 push {r7} 800be1a: b083 sub sp, #12 800be1c: af00 add r7, sp, #0 800be1e: 6078 str r0, [r7, #4] 800be20: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 800be22: 687b ldr r3, [r7, #4] 800be24: 223f movs r2, #63 @ 0x3f 800be26: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 800be28: 4b1a ldr r3, [pc, #104] @ (800be94 ) 800be2a: 691b ldr r3, [r3, #16] 800be2c: f003 0207 and.w r2, r3, #7 800be30: 687b ldr r3, [r7, #4] 800be32: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 800be34: 4b17 ldr r3, [pc, #92] @ (800be94 ) 800be36: 699b ldr r3, [r3, #24] 800be38: f403 6270 and.w r2, r3, #3840 @ 0xf00 800be3c: 687b ldr r3, [r7, #4] 800be3e: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 800be40: 4b14 ldr r3, [pc, #80] @ (800be94 ) 800be42: 699b ldr r3, [r3, #24] 800be44: f003 020f and.w r2, r3, #15 800be48: 687b ldr r3, [r7, #4] 800be4a: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800be4c: 4b11 ldr r3, [pc, #68] @ (800be94 ) 800be4e: 699b ldr r3, [r3, #24] 800be50: f003 0270 and.w r2, r3, #112 @ 0x70 800be54: 687b ldr r3, [r7, #4] 800be56: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 800be58: 4b0e ldr r3, [pc, #56] @ (800be94 ) 800be5a: 69db ldr r3, [r3, #28] 800be5c: f003 0270 and.w r2, r3, #112 @ 0x70 800be60: 687b ldr r3, [r7, #4] 800be62: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 800be64: 4b0b ldr r3, [pc, #44] @ (800be94 ) 800be66: 69db ldr r3, [r3, #28] 800be68: f403 62e0 and.w r2, r3, #1792 @ 0x700 800be6c: 687b ldr r3, [r7, #4] 800be6e: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 800be70: 4b08 ldr r3, [pc, #32] @ (800be94 ) 800be72: 6a1b ldr r3, [r3, #32] 800be74: f003 0270 and.w r2, r3, #112 @ 0x70 800be78: 687b ldr r3, [r7, #4] 800be7a: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800be7c: 4b06 ldr r3, [pc, #24] @ (800be98 ) 800be7e: 681b ldr r3, [r3, #0] 800be80: f003 020f and.w r2, r3, #15 800be84: 683b ldr r3, [r7, #0] 800be86: 601a str r2, [r3, #0] } 800be88: bf00 nop 800be8a: 370c adds r7, #12 800be8c: 46bd mov sp, r7 800be8e: f85d 7b04 ldr.w r7, [sp], #4 800be92: 4770 bx lr 800be94: 58024400 .word 0x58024400 800be98: 52002000 .word 0x52002000 0800be9c : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800be9c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800bea0: b0c8 sub sp, #288 @ 0x120 800bea2: af00 add r7, sp, #0 800bea4: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800bea8: 2300 movs r3, #0 800beaa: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800beae: 2300 movs r3, #0 800beb0: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800beb4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800beb8: e9d3 2300 ldrd r2, r3, [r3] 800bebc: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800bec0: 2500 movs r5, #0 800bec2: ea54 0305 orrs.w r3, r4, r5 800bec6: d049 beq.n 800bf5c { switch (PeriphClkInit->SpdifrxClockSelection) 800bec8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800becc: 6e9b ldr r3, [r3, #104] @ 0x68 800bece: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800bed2: d02f beq.n 800bf34 800bed4: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800bed8: d828 bhi.n 800bf2c 800beda: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800bede: d01a beq.n 800bf16 800bee0: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800bee4: d822 bhi.n 800bf2c 800bee6: 2b00 cmp r3, #0 800bee8: d003 beq.n 800bef2 800beea: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800beee: d007 beq.n 800bf00 800bef0: e01c b.n 800bf2c { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800bef2: 4bb8 ldr r3, [pc, #736] @ (800c1d4 ) 800bef4: 6adb ldr r3, [r3, #44] @ 0x2c 800bef6: 4ab7 ldr r2, [pc, #732] @ (800c1d4 ) 800bef8: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800befc: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800befe: e01a b.n 800bf36 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800bf00: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bf04: 3308 adds r3, #8 800bf06: 2102 movs r1, #2 800bf08: 4618 mov r0, r3 800bf0a: f002 fb45 bl 800e598 800bf0e: 4603 mov r3, r0 800bf10: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800bf14: e00f b.n 800bf36 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800bf16: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bf1a: 3328 adds r3, #40 @ 0x28 800bf1c: 2102 movs r1, #2 800bf1e: 4618 mov r0, r3 800bf20: f002 fbec bl 800e6fc 800bf24: 4603 mov r3, r0 800bf26: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800bf2a: e004 b.n 800bf36 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800bf2c: 2301 movs r3, #1 800bf2e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800bf32: e000 b.n 800bf36 break; 800bf34: bf00 nop } if (ret == HAL_OK) 800bf36: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bf3a: 2b00 cmp r3, #0 800bf3c: d10a bne.n 800bf54 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800bf3e: 4ba5 ldr r3, [pc, #660] @ (800c1d4 ) 800bf40: 6d1b ldr r3, [r3, #80] @ 0x50 800bf42: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800bf46: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bf4a: 6e9b ldr r3, [r3, #104] @ 0x68 800bf4c: 4aa1 ldr r2, [pc, #644] @ (800c1d4 ) 800bf4e: 430b orrs r3, r1 800bf50: 6513 str r3, [r2, #80] @ 0x50 800bf52: e003 b.n 800bf5c } else { /* set overall return value */ status = ret; 800bf54: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bf58: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800bf5c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bf60: e9d3 2300 ldrd r2, r3, [r3] 800bf64: f402 7880 and.w r8, r2, #256 @ 0x100 800bf68: f04f 0900 mov.w r9, #0 800bf6c: ea58 0309 orrs.w r3, r8, r9 800bf70: d047 beq.n 800c002 { switch (PeriphClkInit->Sai1ClockSelection) 800bf72: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bf76: 6d9b ldr r3, [r3, #88] @ 0x58 800bf78: 2b04 cmp r3, #4 800bf7a: d82a bhi.n 800bfd2 800bf7c: a201 add r2, pc, #4 @ (adr r2, 800bf84 ) 800bf7e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800bf82: bf00 nop 800bf84: 0800bf99 .word 0x0800bf99 800bf88: 0800bfa7 .word 0x0800bfa7 800bf8c: 0800bfbd .word 0x0800bfbd 800bf90: 0800bfdb .word 0x0800bfdb 800bf94: 0800bfdb .word 0x0800bfdb { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800bf98: 4b8e ldr r3, [pc, #568] @ (800c1d4 ) 800bf9a: 6adb ldr r3, [r3, #44] @ 0x2c 800bf9c: 4a8d ldr r2, [pc, #564] @ (800c1d4 ) 800bf9e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bfa2: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800bfa4: e01a b.n 800bfdc case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800bfa6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bfaa: 3308 adds r3, #8 800bfac: 2100 movs r1, #0 800bfae: 4618 mov r0, r3 800bfb0: f002 faf2 bl 800e598 800bfb4: 4603 mov r3, r0 800bfb6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800bfba: e00f b.n 800bfdc case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800bfbc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bfc0: 3328 adds r3, #40 @ 0x28 800bfc2: 2100 movs r1, #0 800bfc4: 4618 mov r0, r3 800bfc6: f002 fb99 bl 800e6fc 800bfca: 4603 mov r3, r0 800bfcc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800bfd0: e004 b.n 800bfdc /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800bfd2: 2301 movs r3, #1 800bfd4: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800bfd8: e000 b.n 800bfdc break; 800bfda: bf00 nop } if (ret == HAL_OK) 800bfdc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bfe0: 2b00 cmp r3, #0 800bfe2: d10a bne.n 800bffa { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800bfe4: 4b7b ldr r3, [pc, #492] @ (800c1d4 ) 800bfe6: 6d1b ldr r3, [r3, #80] @ 0x50 800bfe8: f023 0107 bic.w r1, r3, #7 800bfec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800bff0: 6d9b ldr r3, [r3, #88] @ 0x58 800bff2: 4a78 ldr r2, [pc, #480] @ (800c1d4 ) 800bff4: 430b orrs r3, r1 800bff6: 6513 str r3, [r2, #80] @ 0x50 800bff8: e003 b.n 800c002 } else { /* set overall return value */ status = ret; 800bffa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800bffe: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800c002: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c006: e9d3 2300 ldrd r2, r3, [r3] 800c00a: f402 7a00 and.w sl, r2, #512 @ 0x200 800c00e: f04f 0b00 mov.w fp, #0 800c012: ea5a 030b orrs.w r3, sl, fp 800c016: d04c beq.n 800c0b2 { switch (PeriphClkInit->Sai23ClockSelection) 800c018: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c01c: 6ddb ldr r3, [r3, #92] @ 0x5c 800c01e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c022: d030 beq.n 800c086 800c024: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c028: d829 bhi.n 800c07e 800c02a: 2bc0 cmp r3, #192 @ 0xc0 800c02c: d02d beq.n 800c08a 800c02e: 2bc0 cmp r3, #192 @ 0xc0 800c030: d825 bhi.n 800c07e 800c032: 2b80 cmp r3, #128 @ 0x80 800c034: d018 beq.n 800c068 800c036: 2b80 cmp r3, #128 @ 0x80 800c038: d821 bhi.n 800c07e 800c03a: 2b00 cmp r3, #0 800c03c: d002 beq.n 800c044 800c03e: 2b40 cmp r3, #64 @ 0x40 800c040: d007 beq.n 800c052 800c042: e01c b.n 800c07e { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c044: 4b63 ldr r3, [pc, #396] @ (800c1d4 ) 800c046: 6adb ldr r3, [r3, #44] @ 0x2c 800c048: 4a62 ldr r2, [pc, #392] @ (800c1d4 ) 800c04a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c04e: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c050: e01c b.n 800c08c case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c052: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c056: 3308 adds r3, #8 800c058: 2100 movs r1, #0 800c05a: 4618 mov r0, r3 800c05c: f002 fa9c bl 800e598 800c060: 4603 mov r3, r0 800c062: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c066: e011 b.n 800c08c case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c068: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c06c: 3328 adds r3, #40 @ 0x28 800c06e: 2100 movs r1, #0 800c070: 4618 mov r0, r3 800c072: f002 fb43 bl 800e6fc 800c076: 4603 mov r3, r0 800c078: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800c07c: e006 b.n 800c08c /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c07e: 2301 movs r3, #1 800c080: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c084: e002 b.n 800c08c break; 800c086: bf00 nop 800c088: e000 b.n 800c08c break; 800c08a: bf00 nop } if (ret == HAL_OK) 800c08c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c090: 2b00 cmp r3, #0 800c092: d10a bne.n 800c0aa { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800c094: 4b4f ldr r3, [pc, #316] @ (800c1d4 ) 800c096: 6d1b ldr r3, [r3, #80] @ 0x50 800c098: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 800c09c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c0a0: 6ddb ldr r3, [r3, #92] @ 0x5c 800c0a2: 4a4c ldr r2, [pc, #304] @ (800c1d4 ) 800c0a4: 430b orrs r3, r1 800c0a6: 6513 str r3, [r2, #80] @ 0x50 800c0a8: e003 b.n 800c0b2 } else { /* set overall return value */ status = ret; 800c0aa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c0ae: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800c0b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c0b6: e9d3 2300 ldrd r2, r3, [r3] 800c0ba: f402 6380 and.w r3, r2, #1024 @ 0x400 800c0be: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800c0c2: 2300 movs r3, #0 800c0c4: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800c0c8: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 800c0cc: 460b mov r3, r1 800c0ce: 4313 orrs r3, r2 800c0d0: d053 beq.n 800c17a { switch (PeriphClkInit->Sai4AClockSelection) 800c0d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c0d6: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800c0da: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c0de: d035 beq.n 800c14c 800c0e0: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800c0e4: d82e bhi.n 800c144 800c0e6: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800c0ea: d031 beq.n 800c150 800c0ec: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800c0f0: d828 bhi.n 800c144 800c0f2: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c0f6: d01a beq.n 800c12e 800c0f8: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800c0fc: d822 bhi.n 800c144 800c0fe: 2b00 cmp r3, #0 800c100: d003 beq.n 800c10a 800c102: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c106: d007 beq.n 800c118 800c108: e01c b.n 800c144 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c10a: 4b32 ldr r3, [pc, #200] @ (800c1d4 ) 800c10c: 6adb ldr r3, [r3, #44] @ 0x2c 800c10e: 4a31 ldr r2, [pc, #196] @ (800c1d4 ) 800c110: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c114: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800c116: e01c b.n 800c152 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c118: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c11c: 3308 adds r3, #8 800c11e: 2100 movs r1, #0 800c120: 4618 mov r0, r3 800c122: f002 fa39 bl 800e598 800c126: 4603 mov r3, r0 800c128: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800c12c: e011 b.n 800c152 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c12e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c132: 3328 adds r3, #40 @ 0x28 800c134: 2100 movs r1, #0 800c136: 4618 mov r0, r3 800c138: f002 fae0 bl 800e6fc 800c13c: 4603 mov r3, r0 800c13e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c142: e006 b.n 800c152 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800c144: 2301 movs r3, #1 800c146: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c14a: e002 b.n 800c152 break; 800c14c: bf00 nop 800c14e: e000 b.n 800c152 break; 800c150: bf00 nop } if (ret == HAL_OK) 800c152: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c156: 2b00 cmp r3, #0 800c158: d10b bne.n 800c172 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800c15a: 4b1e ldr r3, [pc, #120] @ (800c1d4 ) 800c15c: 6d9b ldr r3, [r3, #88] @ 0x58 800c15e: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 800c162: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c166: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800c16a: 4a1a ldr r2, [pc, #104] @ (800c1d4 ) 800c16c: 430b orrs r3, r1 800c16e: 6593 str r3, [r2, #88] @ 0x58 800c170: e003 b.n 800c17a } else { /* set overall return value */ status = ret; 800c172: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c176: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800c17a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c17e: e9d3 2300 ldrd r2, r3, [r3] 800c182: f402 6300 and.w r3, r2, #2048 @ 0x800 800c186: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800c18a: 2300 movs r3, #0 800c18c: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800c190: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 800c194: 460b mov r3, r1 800c196: 4313 orrs r3, r2 800c198: d056 beq.n 800c248 { switch (PeriphClkInit->Sai4BClockSelection) 800c19a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c19e: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800c1a2: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c1a6: d038 beq.n 800c21a 800c1a8: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800c1ac: d831 bhi.n 800c212 800c1ae: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800c1b2: d034 beq.n 800c21e 800c1b4: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800c1b8: d82b bhi.n 800c212 800c1ba: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c1be: d01d beq.n 800c1fc 800c1c0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800c1c4: d825 bhi.n 800c212 800c1c6: 2b00 cmp r3, #0 800c1c8: d006 beq.n 800c1d8 800c1ca: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800c1ce: d00a beq.n 800c1e6 800c1d0: e01f b.n 800c212 800c1d2: bf00 nop 800c1d4: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c1d8: 4ba2 ldr r3, [pc, #648] @ (800c464 ) 800c1da: 6adb ldr r3, [r3, #44] @ 0x2c 800c1dc: 4aa1 ldr r2, [pc, #644] @ (800c464 ) 800c1de: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c1e2: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800c1e4: e01c b.n 800c220 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c1e6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c1ea: 3308 adds r3, #8 800c1ec: 2100 movs r1, #0 800c1ee: 4618 mov r0, r3 800c1f0: f002 f9d2 bl 800e598 800c1f4: 4603 mov r3, r0 800c1f6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800c1fa: e011 b.n 800c220 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c1fc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c200: 3328 adds r3, #40 @ 0x28 800c202: 2100 movs r1, #0 800c204: 4618 mov r0, r3 800c206: f002 fa79 bl 800e6fc 800c20a: 4603 mov r3, r0 800c20c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800c210: e006 b.n 800c220 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800c212: 2301 movs r3, #1 800c214: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c218: e002 b.n 800c220 break; 800c21a: bf00 nop 800c21c: e000 b.n 800c220 break; 800c21e: bf00 nop } if (ret == HAL_OK) 800c220: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c224: 2b00 cmp r3, #0 800c226: d10b bne.n 800c240 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800c228: 4b8e ldr r3, [pc, #568] @ (800c464 ) 800c22a: 6d9b ldr r3, [r3, #88] @ 0x58 800c22c: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 800c230: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c234: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800c238: 4a8a ldr r2, [pc, #552] @ (800c464 ) 800c23a: 430b orrs r3, r1 800c23c: 6593 str r3, [r2, #88] @ 0x58 800c23e: e003 b.n 800c248 } else { /* set overall return value */ status = ret; 800c240: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c244: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800c248: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c24c: e9d3 2300 ldrd r2, r3, [r3] 800c250: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 800c254: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800c258: 2300 movs r3, #0 800c25a: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800c25e: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 800c262: 460b mov r3, r1 800c264: 4313 orrs r3, r2 800c266: d03a beq.n 800c2de { switch (PeriphClkInit->QspiClockSelection) 800c268: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c26c: 6cdb ldr r3, [r3, #76] @ 0x4c 800c26e: 2b30 cmp r3, #48 @ 0x30 800c270: d01f beq.n 800c2b2 800c272: 2b30 cmp r3, #48 @ 0x30 800c274: d819 bhi.n 800c2aa 800c276: 2b20 cmp r3, #32 800c278: d00c beq.n 800c294 800c27a: 2b20 cmp r3, #32 800c27c: d815 bhi.n 800c2aa 800c27e: 2b00 cmp r3, #0 800c280: d019 beq.n 800c2b6 800c282: 2b10 cmp r3, #16 800c284: d111 bne.n 800c2aa { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c286: 4b77 ldr r3, [pc, #476] @ (800c464 ) 800c288: 6adb ldr r3, [r3, #44] @ 0x2c 800c28a: 4a76 ldr r2, [pc, #472] @ (800c464 ) 800c28c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c290: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800c292: e011 b.n 800c2b8 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c294: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c298: 3308 adds r3, #8 800c29a: 2102 movs r1, #2 800c29c: 4618 mov r0, r3 800c29e: f002 f97b bl 800e598 800c2a2: 4603 mov r3, r0 800c2a4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 800c2a8: e006 b.n 800c2b8 case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800c2aa: 2301 movs r3, #1 800c2ac: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c2b0: e002 b.n 800c2b8 break; 800c2b2: bf00 nop 800c2b4: e000 b.n 800c2b8 break; 800c2b6: bf00 nop } if (ret == HAL_OK) 800c2b8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c2bc: 2b00 cmp r3, #0 800c2be: d10a bne.n 800c2d6 { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800c2c0: 4b68 ldr r3, [pc, #416] @ (800c464 ) 800c2c2: 6cdb ldr r3, [r3, #76] @ 0x4c 800c2c4: f023 0130 bic.w r1, r3, #48 @ 0x30 800c2c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c2cc: 6cdb ldr r3, [r3, #76] @ 0x4c 800c2ce: 4a65 ldr r2, [pc, #404] @ (800c464 ) 800c2d0: 430b orrs r3, r1 800c2d2: 64d3 str r3, [r2, #76] @ 0x4c 800c2d4: e003 b.n 800c2de } else { /* set overall return value */ status = ret; 800c2d6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c2da: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800c2de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c2e2: e9d3 2300 ldrd r2, r3, [r3] 800c2e6: f402 5380 and.w r3, r2, #4096 @ 0x1000 800c2ea: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800c2ee: 2300 movs r3, #0 800c2f0: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800c2f4: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 800c2f8: 460b mov r3, r1 800c2fa: 4313 orrs r3, r2 800c2fc: d051 beq.n 800c3a2 { switch (PeriphClkInit->Spi123ClockSelection) 800c2fe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c302: 6e1b ldr r3, [r3, #96] @ 0x60 800c304: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800c308: d035 beq.n 800c376 800c30a: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800c30e: d82e bhi.n 800c36e 800c310: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800c314: d031 beq.n 800c37a 800c316: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800c31a: d828 bhi.n 800c36e 800c31c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800c320: d01a beq.n 800c358 800c322: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800c326: d822 bhi.n 800c36e 800c328: 2b00 cmp r3, #0 800c32a: d003 beq.n 800c334 800c32c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800c330: d007 beq.n 800c342 800c332: e01c b.n 800c36e { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c334: 4b4b ldr r3, [pc, #300] @ (800c464 ) 800c336: 6adb ldr r3, [r3, #44] @ 0x2c 800c338: 4a4a ldr r2, [pc, #296] @ (800c464 ) 800c33a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c33e: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800c340: e01c b.n 800c37c case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800c342: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c346: 3308 adds r3, #8 800c348: 2100 movs r1, #0 800c34a: 4618 mov r0, r3 800c34c: f002 f924 bl 800e598 800c350: 4603 mov r3, r0 800c352: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800c356: e011 b.n 800c37c case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800c358: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c35c: 3328 adds r3, #40 @ 0x28 800c35e: 2100 movs r1, #0 800c360: 4618 mov r0, r3 800c362: f002 f9cb bl 800e6fc 800c366: 4603 mov r3, r0 800c368: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800c36c: e006 b.n 800c37c /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c36e: 2301 movs r3, #1 800c370: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c374: e002 b.n 800c37c break; 800c376: bf00 nop 800c378: e000 b.n 800c37c break; 800c37a: bf00 nop } if (ret == HAL_OK) 800c37c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c380: 2b00 cmp r3, #0 800c382: d10a bne.n 800c39a { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800c384: 4b37 ldr r3, [pc, #220] @ (800c464 ) 800c386: 6d1b ldr r3, [r3, #80] @ 0x50 800c388: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 800c38c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c390: 6e1b ldr r3, [r3, #96] @ 0x60 800c392: 4a34 ldr r2, [pc, #208] @ (800c464 ) 800c394: 430b orrs r3, r1 800c396: 6513 str r3, [r2, #80] @ 0x50 800c398: e003 b.n 800c3a2 } else { /* set overall return value */ status = ret; 800c39a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c39e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800c3a2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c3a6: e9d3 2300 ldrd r2, r3, [r3] 800c3aa: f402 5300 and.w r3, r2, #8192 @ 0x2000 800c3ae: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800c3b2: 2300 movs r3, #0 800c3b4: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800c3b8: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 800c3bc: 460b mov r3, r1 800c3be: 4313 orrs r3, r2 800c3c0: d056 beq.n 800c470 { switch (PeriphClkInit->Spi45ClockSelection) 800c3c2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c3c6: 6e5b ldr r3, [r3, #100] @ 0x64 800c3c8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800c3cc: d033 beq.n 800c436 800c3ce: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800c3d2: d82c bhi.n 800c42e 800c3d4: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800c3d8: d02f beq.n 800c43a 800c3da: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800c3de: d826 bhi.n 800c42e 800c3e0: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800c3e4: d02b beq.n 800c43e 800c3e6: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800c3ea: d820 bhi.n 800c42e 800c3ec: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800c3f0: d012 beq.n 800c418 800c3f2: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800c3f6: d81a bhi.n 800c42e 800c3f8: 2b00 cmp r3, #0 800c3fa: d022 beq.n 800c442 800c3fc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800c400: d115 bne.n 800c42e /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800c402: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c406: 3308 adds r3, #8 800c408: 2101 movs r1, #1 800c40a: 4618 mov r0, r3 800c40c: f002 f8c4 bl 800e598 800c410: 4603 mov r3, r0 800c412: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800c416: e015 b.n 800c444 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800c418: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c41c: 3328 adds r3, #40 @ 0x28 800c41e: 2101 movs r1, #1 800c420: 4618 mov r0, r3 800c422: f002 f96b bl 800e6fc 800c426: 4603 mov r3, r0 800c428: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800c42c: e00a b.n 800c444 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c42e: 2301 movs r3, #1 800c430: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c434: e006 b.n 800c444 break; 800c436: bf00 nop 800c438: e004 b.n 800c444 break; 800c43a: bf00 nop 800c43c: e002 b.n 800c444 break; 800c43e: bf00 nop 800c440: e000 b.n 800c444 break; 800c442: bf00 nop } if (ret == HAL_OK) 800c444: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c448: 2b00 cmp r3, #0 800c44a: d10d bne.n 800c468 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800c44c: 4b05 ldr r3, [pc, #20] @ (800c464 ) 800c44e: 6d1b ldr r3, [r3, #80] @ 0x50 800c450: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 800c454: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c458: 6e5b ldr r3, [r3, #100] @ 0x64 800c45a: 4a02 ldr r2, [pc, #8] @ (800c464 ) 800c45c: 430b orrs r3, r1 800c45e: 6513 str r3, [r2, #80] @ 0x50 800c460: e006 b.n 800c470 800c462: bf00 nop 800c464: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800c468: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c46c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800c470: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c474: e9d3 2300 ldrd r2, r3, [r3] 800c478: f402 4380 and.w r3, r2, #16384 @ 0x4000 800c47c: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800c480: 2300 movs r3, #0 800c482: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800c486: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800c48a: 460b mov r3, r1 800c48c: 4313 orrs r3, r2 800c48e: d055 beq.n 800c53c { switch (PeriphClkInit->Spi6ClockSelection) 800c490: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c494: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800c498: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800c49c: d033 beq.n 800c506 800c49e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800c4a2: d82c bhi.n 800c4fe 800c4a4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800c4a8: d02f beq.n 800c50a 800c4aa: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800c4ae: d826 bhi.n 800c4fe 800c4b0: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800c4b4: d02b beq.n 800c50e 800c4b6: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800c4ba: d820 bhi.n 800c4fe 800c4bc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c4c0: d012 beq.n 800c4e8 800c4c2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c4c6: d81a bhi.n 800c4fe 800c4c8: 2b00 cmp r3, #0 800c4ca: d022 beq.n 800c512 800c4cc: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800c4d0: d115 bne.n 800c4fe /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800c4d2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c4d6: 3308 adds r3, #8 800c4d8: 2101 movs r1, #1 800c4da: 4618 mov r0, r3 800c4dc: f002 f85c bl 800e598 800c4e0: 4603 mov r3, r0 800c4e2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800c4e6: e015 b.n 800c514 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800c4e8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c4ec: 3328 adds r3, #40 @ 0x28 800c4ee: 2101 movs r1, #1 800c4f0: 4618 mov r0, r3 800c4f2: f002 f903 bl 800e6fc 800c4f6: 4603 mov r3, r0 800c4f8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800c4fc: e00a b.n 800c514 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800c4fe: 2301 movs r3, #1 800c500: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c504: e006 b.n 800c514 break; 800c506: bf00 nop 800c508: e004 b.n 800c514 break; 800c50a: bf00 nop 800c50c: e002 b.n 800c514 break; 800c50e: bf00 nop 800c510: e000 b.n 800c514 break; 800c512: bf00 nop } if (ret == HAL_OK) 800c514: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c518: 2b00 cmp r3, #0 800c51a: d10b bne.n 800c534 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800c51c: 4ba3 ldr r3, [pc, #652] @ (800c7ac ) 800c51e: 6d9b ldr r3, [r3, #88] @ 0x58 800c520: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800c524: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c528: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800c52c: 4a9f ldr r2, [pc, #636] @ (800c7ac ) 800c52e: 430b orrs r3, r1 800c530: 6593 str r3, [r2, #88] @ 0x58 800c532: e003 b.n 800c53c } else { /* set overall return value */ status = ret; 800c534: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c538: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800c53c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c540: e9d3 2300 ldrd r2, r3, [r3] 800c544: f402 4300 and.w r3, r2, #32768 @ 0x8000 800c548: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800c54c: 2300 movs r3, #0 800c54e: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800c552: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 800c556: 460b mov r3, r1 800c558: 4313 orrs r3, r2 800c55a: d037 beq.n 800c5cc { switch (PeriphClkInit->FdcanClockSelection) 800c55c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c560: 6f1b ldr r3, [r3, #112] @ 0x70 800c562: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c566: d00e beq.n 800c586 800c568: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800c56c: d816 bhi.n 800c59c 800c56e: 2b00 cmp r3, #0 800c570: d018 beq.n 800c5a4 800c572: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800c576: d111 bne.n 800c59c { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c578: 4b8c ldr r3, [pc, #560] @ (800c7ac ) 800c57a: 6adb ldr r3, [r3, #44] @ 0x2c 800c57c: 4a8b ldr r2, [pc, #556] @ (800c7ac ) 800c57e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c582: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800c584: e00f b.n 800c5a6 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800c586: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c58a: 3308 adds r3, #8 800c58c: 2101 movs r1, #1 800c58e: 4618 mov r0, r3 800c590: f002 f802 bl 800e598 800c594: 4603 mov r3, r0 800c596: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 800c59a: e004 b.n 800c5a6 /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c59c: 2301 movs r3, #1 800c59e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c5a2: e000 b.n 800c5a6 break; 800c5a4: bf00 nop } if (ret == HAL_OK) 800c5a6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c5aa: 2b00 cmp r3, #0 800c5ac: d10a bne.n 800c5c4 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800c5ae: 4b7f ldr r3, [pc, #508] @ (800c7ac ) 800c5b0: 6d1b ldr r3, [r3, #80] @ 0x50 800c5b2: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800c5b6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c5ba: 6f1b ldr r3, [r3, #112] @ 0x70 800c5bc: 4a7b ldr r2, [pc, #492] @ (800c7ac ) 800c5be: 430b orrs r3, r1 800c5c0: 6513 str r3, [r2, #80] @ 0x50 800c5c2: e003 b.n 800c5cc } else { /* set overall return value */ status = ret; 800c5c4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c5c8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 800c5cc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c5d0: e9d3 2300 ldrd r2, r3, [r3] 800c5d4: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 800c5d8: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800c5dc: 2300 movs r3, #0 800c5de: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800c5e2: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 800c5e6: 460b mov r3, r1 800c5e8: 4313 orrs r3, r2 800c5ea: d039 beq.n 800c660 { switch (PeriphClkInit->FmcClockSelection) 800c5ec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c5f0: 6c9b ldr r3, [r3, #72] @ 0x48 800c5f2: 2b03 cmp r3, #3 800c5f4: d81c bhi.n 800c630 800c5f6: a201 add r2, pc, #4 @ (adr r2, 800c5fc ) 800c5f8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c5fc: 0800c639 .word 0x0800c639 800c600: 0800c60d .word 0x0800c60d 800c604: 0800c61b .word 0x0800c61b 800c608: 0800c639 .word 0x0800c639 { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c60c: 4b67 ldr r3, [pc, #412] @ (800c7ac ) 800c60e: 6adb ldr r3, [r3, #44] @ 0x2c 800c610: 4a66 ldr r2, [pc, #408] @ (800c7ac ) 800c612: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c616: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800c618: e00f b.n 800c63a case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c61a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c61e: 3308 adds r3, #8 800c620: 2102 movs r1, #2 800c622: 4618 mov r0, r3 800c624: f001 ffb8 bl 800e598 800c628: 4603 mov r3, r0 800c62a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 800c62e: e004 b.n 800c63a case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800c630: 2301 movs r3, #1 800c632: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c636: e000 b.n 800c63a break; 800c638: bf00 nop } if (ret == HAL_OK) 800c63a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c63e: 2b00 cmp r3, #0 800c640: d10a bne.n 800c658 { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800c642: 4b5a ldr r3, [pc, #360] @ (800c7ac ) 800c644: 6cdb ldr r3, [r3, #76] @ 0x4c 800c646: f023 0103 bic.w r1, r3, #3 800c64a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c64e: 6c9b ldr r3, [r3, #72] @ 0x48 800c650: 4a56 ldr r2, [pc, #344] @ (800c7ac ) 800c652: 430b orrs r3, r1 800c654: 64d3 str r3, [r2, #76] @ 0x4c 800c656: e003 b.n 800c660 } else { /* set overall return value */ status = ret; 800c658: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c65c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800c660: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c664: e9d3 2300 ldrd r2, r3, [r3] 800c668: f402 0380 and.w r3, r2, #4194304 @ 0x400000 800c66c: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800c670: 2300 movs r3, #0 800c672: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800c676: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800c67a: 460b mov r3, r1 800c67c: 4313 orrs r3, r2 800c67e: f000 809f beq.w 800c7c0 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800c682: 4b4b ldr r3, [pc, #300] @ (800c7b0 ) 800c684: 681b ldr r3, [r3, #0] 800c686: 4a4a ldr r2, [pc, #296] @ (800c7b0 ) 800c688: f443 7380 orr.w r3, r3, #256 @ 0x100 800c68c: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800c68e: f7f8 fea5 bl 80053dc 800c692: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800c696: e00b b.n 800c6b0 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800c698: f7f8 fea0 bl 80053dc 800c69c: 4602 mov r2, r0 800c69e: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800c6a2: 1ad3 subs r3, r2, r3 800c6a4: 2b64 cmp r3, #100 @ 0x64 800c6a6: d903 bls.n 800c6b0 { ret = HAL_TIMEOUT; 800c6a8: 2303 movs r3, #3 800c6aa: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c6ae: e005 b.n 800c6bc while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800c6b0: 4b3f ldr r3, [pc, #252] @ (800c7b0 ) 800c6b2: 681b ldr r3, [r3, #0] 800c6b4: f403 7380 and.w r3, r3, #256 @ 0x100 800c6b8: 2b00 cmp r3, #0 800c6ba: d0ed beq.n 800c698 } } if (ret == HAL_OK) 800c6bc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c6c0: 2b00 cmp r3, #0 800c6c2: d179 bne.n 800c7b8 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800c6c4: 4b39 ldr r3, [pc, #228] @ (800c7ac ) 800c6c6: 6f1a ldr r2, [r3, #112] @ 0x70 800c6c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c6cc: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800c6d0: 4053 eors r3, r2 800c6d2: f403 7340 and.w r3, r3, #768 @ 0x300 800c6d6: 2b00 cmp r3, #0 800c6d8: d015 beq.n 800c706 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800c6da: 4b34 ldr r3, [pc, #208] @ (800c7ac ) 800c6dc: 6f1b ldr r3, [r3, #112] @ 0x70 800c6de: f423 7340 bic.w r3, r3, #768 @ 0x300 800c6e2: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800c6e6: 4b31 ldr r3, [pc, #196] @ (800c7ac ) 800c6e8: 6f1b ldr r3, [r3, #112] @ 0x70 800c6ea: 4a30 ldr r2, [pc, #192] @ (800c7ac ) 800c6ec: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c6f0: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800c6f2: 4b2e ldr r3, [pc, #184] @ (800c7ac ) 800c6f4: 6f1b ldr r3, [r3, #112] @ 0x70 800c6f6: 4a2d ldr r2, [pc, #180] @ (800c7ac ) 800c6f8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800c6fc: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800c6fe: 4a2b ldr r2, [pc, #172] @ (800c7ac ) 800c700: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800c704: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800c706: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c70a: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800c70e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800c712: d118 bne.n 800c746 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c714: f7f8 fe62 bl 80053dc 800c718: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800c71c: e00d b.n 800c73a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800c71e: f7f8 fe5d bl 80053dc 800c722: 4602 mov r2, r0 800c724: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800c728: 1ad2 subs r2, r2, r3 800c72a: f241 3388 movw r3, #5000 @ 0x1388 800c72e: 429a cmp r2, r3 800c730: d903 bls.n 800c73a { ret = HAL_TIMEOUT; 800c732: 2303 movs r3, #3 800c734: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c738: e005 b.n 800c746 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800c73a: 4b1c ldr r3, [pc, #112] @ (800c7ac ) 800c73c: 6f1b ldr r3, [r3, #112] @ 0x70 800c73e: f003 0302 and.w r3, r3, #2 800c742: 2b00 cmp r3, #0 800c744: d0eb beq.n 800c71e } } } if (ret == HAL_OK) 800c746: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c74a: 2b00 cmp r3, #0 800c74c: d129 bne.n 800c7a2 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800c74e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c752: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800c756: f403 7340 and.w r3, r3, #768 @ 0x300 800c75a: f5b3 7f40 cmp.w r3, #768 @ 0x300 800c75e: d10e bne.n 800c77e 800c760: 4b12 ldr r3, [pc, #72] @ (800c7ac ) 800c762: 691b ldr r3, [r3, #16] 800c764: f423 517c bic.w r1, r3, #16128 @ 0x3f00 800c768: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c76c: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800c770: 091a lsrs r2, r3, #4 800c772: 4b10 ldr r3, [pc, #64] @ (800c7b4 ) 800c774: 4013 ands r3, r2 800c776: 4a0d ldr r2, [pc, #52] @ (800c7ac ) 800c778: 430b orrs r3, r1 800c77a: 6113 str r3, [r2, #16] 800c77c: e005 b.n 800c78a 800c77e: 4b0b ldr r3, [pc, #44] @ (800c7ac ) 800c780: 691b ldr r3, [r3, #16] 800c782: 4a0a ldr r2, [pc, #40] @ (800c7ac ) 800c784: f423 537c bic.w r3, r3, #16128 @ 0x3f00 800c788: 6113 str r3, [r2, #16] 800c78a: 4b08 ldr r3, [pc, #32] @ (800c7ac ) 800c78c: 6f19 ldr r1, [r3, #112] @ 0x70 800c78e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c792: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800c796: f3c3 030b ubfx r3, r3, #0, #12 800c79a: 4a04 ldr r2, [pc, #16] @ (800c7ac ) 800c79c: 430b orrs r3, r1 800c79e: 6713 str r3, [r2, #112] @ 0x70 800c7a0: e00e b.n 800c7c0 } else { /* set overall return value */ status = ret; 800c7a2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c7a6: f887 311e strb.w r3, [r7, #286] @ 0x11e 800c7aa: e009 b.n 800c7c0 800c7ac: 58024400 .word 0x58024400 800c7b0: 58024800 .word 0x58024800 800c7b4: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 800c7b8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c7bc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800c7c0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c7c4: e9d3 2300 ldrd r2, r3, [r3] 800c7c8: f002 0301 and.w r3, r2, #1 800c7cc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800c7d0: 2300 movs r3, #0 800c7d2: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800c7d6: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 800c7da: 460b mov r3, r1 800c7dc: 4313 orrs r3, r2 800c7de: f000 8089 beq.w 800c8f4 { switch (PeriphClkInit->Usart16ClockSelection) 800c7e2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c7e6: 6fdb ldr r3, [r3, #124] @ 0x7c 800c7e8: 2b28 cmp r3, #40 @ 0x28 800c7ea: d86b bhi.n 800c8c4 800c7ec: a201 add r2, pc, #4 @ (adr r2, 800c7f4 ) 800c7ee: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c7f2: bf00 nop 800c7f4: 0800c8cd .word 0x0800c8cd 800c7f8: 0800c8c5 .word 0x0800c8c5 800c7fc: 0800c8c5 .word 0x0800c8c5 800c800: 0800c8c5 .word 0x0800c8c5 800c804: 0800c8c5 .word 0x0800c8c5 800c808: 0800c8c5 .word 0x0800c8c5 800c80c: 0800c8c5 .word 0x0800c8c5 800c810: 0800c8c5 .word 0x0800c8c5 800c814: 0800c899 .word 0x0800c899 800c818: 0800c8c5 .word 0x0800c8c5 800c81c: 0800c8c5 .word 0x0800c8c5 800c820: 0800c8c5 .word 0x0800c8c5 800c824: 0800c8c5 .word 0x0800c8c5 800c828: 0800c8c5 .word 0x0800c8c5 800c82c: 0800c8c5 .word 0x0800c8c5 800c830: 0800c8c5 .word 0x0800c8c5 800c834: 0800c8af .word 0x0800c8af 800c838: 0800c8c5 .word 0x0800c8c5 800c83c: 0800c8c5 .word 0x0800c8c5 800c840: 0800c8c5 .word 0x0800c8c5 800c844: 0800c8c5 .word 0x0800c8c5 800c848: 0800c8c5 .word 0x0800c8c5 800c84c: 0800c8c5 .word 0x0800c8c5 800c850: 0800c8c5 .word 0x0800c8c5 800c854: 0800c8cd .word 0x0800c8cd 800c858: 0800c8c5 .word 0x0800c8c5 800c85c: 0800c8c5 .word 0x0800c8c5 800c860: 0800c8c5 .word 0x0800c8c5 800c864: 0800c8c5 .word 0x0800c8c5 800c868: 0800c8c5 .word 0x0800c8c5 800c86c: 0800c8c5 .word 0x0800c8c5 800c870: 0800c8c5 .word 0x0800c8c5 800c874: 0800c8cd .word 0x0800c8cd 800c878: 0800c8c5 .word 0x0800c8c5 800c87c: 0800c8c5 .word 0x0800c8c5 800c880: 0800c8c5 .word 0x0800c8c5 800c884: 0800c8c5 .word 0x0800c8c5 800c888: 0800c8c5 .word 0x0800c8c5 800c88c: 0800c8c5 .word 0x0800c8c5 800c890: 0800c8c5 .word 0x0800c8c5 800c894: 0800c8cd .word 0x0800c8cd case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800c898: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c89c: 3308 adds r3, #8 800c89e: 2101 movs r1, #1 800c8a0: 4618 mov r0, r3 800c8a2: f001 fe79 bl 800e598 800c8a6: 4603 mov r3, r0 800c8a8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800c8ac: e00f b.n 800c8ce case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800c8ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c8b2: 3328 adds r3, #40 @ 0x28 800c8b4: 2101 movs r1, #1 800c8b6: 4618 mov r0, r3 800c8b8: f001 ff20 bl 800e6fc 800c8bc: 4603 mov r3, r0 800c8be: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800c8c2: e004 b.n 800c8ce /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c8c4: 2301 movs r3, #1 800c8c6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c8ca: e000 b.n 800c8ce break; 800c8cc: bf00 nop } if (ret == HAL_OK) 800c8ce: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c8d2: 2b00 cmp r3, #0 800c8d4: d10a bne.n 800c8ec { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800c8d6: 4bbf ldr r3, [pc, #764] @ (800cbd4 ) 800c8d8: 6d5b ldr r3, [r3, #84] @ 0x54 800c8da: f023 0138 bic.w r1, r3, #56 @ 0x38 800c8de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c8e2: 6fdb ldr r3, [r3, #124] @ 0x7c 800c8e4: 4abb ldr r2, [pc, #748] @ (800cbd4 ) 800c8e6: 430b orrs r3, r1 800c8e8: 6553 str r3, [r2, #84] @ 0x54 800c8ea: e003 b.n 800c8f4 } else { /* set overall return value */ status = ret; 800c8ec: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c8f0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800c8f4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c8f8: e9d3 2300 ldrd r2, r3, [r3] 800c8fc: f002 0302 and.w r3, r2, #2 800c900: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800c904: 2300 movs r3, #0 800c906: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800c90a: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800c90e: 460b mov r3, r1 800c910: 4313 orrs r3, r2 800c912: d041 beq.n 800c998 { switch (PeriphClkInit->Usart234578ClockSelection) 800c914: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c918: 6f9b ldr r3, [r3, #120] @ 0x78 800c91a: 2b05 cmp r3, #5 800c91c: d824 bhi.n 800c968 800c91e: a201 add r2, pc, #4 @ (adr r2, 800c924 ) 800c920: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c924: 0800c971 .word 0x0800c971 800c928: 0800c93d .word 0x0800c93d 800c92c: 0800c953 .word 0x0800c953 800c930: 0800c971 .word 0x0800c971 800c934: 0800c971 .word 0x0800c971 800c938: 0800c971 .word 0x0800c971 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800c93c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c940: 3308 adds r3, #8 800c942: 2101 movs r1, #1 800c944: 4618 mov r0, r3 800c946: f001 fe27 bl 800e598 800c94a: 4603 mov r3, r0 800c94c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800c950: e00f b.n 800c972 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800c952: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c956: 3328 adds r3, #40 @ 0x28 800c958: 2101 movs r1, #1 800c95a: 4618 mov r0, r3 800c95c: f001 fece bl 800e6fc 800c960: 4603 mov r3, r0 800c962: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800c966: e004 b.n 800c972 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800c968: 2301 movs r3, #1 800c96a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800c96e: e000 b.n 800c972 break; 800c970: bf00 nop } if (ret == HAL_OK) 800c972: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c976: 2b00 cmp r3, #0 800c978: d10a bne.n 800c990 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800c97a: 4b96 ldr r3, [pc, #600] @ (800cbd4 ) 800c97c: 6d5b ldr r3, [r3, #84] @ 0x54 800c97e: f023 0107 bic.w r1, r3, #7 800c982: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c986: 6f9b ldr r3, [r3, #120] @ 0x78 800c988: 4a92 ldr r2, [pc, #584] @ (800cbd4 ) 800c98a: 430b orrs r3, r1 800c98c: 6553 str r3, [r2, #84] @ 0x54 800c98e: e003 b.n 800c998 } else { /* set overall return value */ status = ret; 800c990: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800c994: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800c998: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c99c: e9d3 2300 ldrd r2, r3, [r3] 800c9a0: f002 0304 and.w r3, r2, #4 800c9a4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800c9a8: 2300 movs r3, #0 800c9aa: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800c9ae: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 800c9b2: 460b mov r3, r1 800c9b4: 4313 orrs r3, r2 800c9b6: d044 beq.n 800ca42 { switch (PeriphClkInit->Lpuart1ClockSelection) 800c9b8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9bc: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800c9c0: 2b05 cmp r3, #5 800c9c2: d825 bhi.n 800ca10 800c9c4: a201 add r2, pc, #4 @ (adr r2, 800c9cc ) 800c9c6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c9ca: bf00 nop 800c9cc: 0800ca19 .word 0x0800ca19 800c9d0: 0800c9e5 .word 0x0800c9e5 800c9d4: 0800c9fb .word 0x0800c9fb 800c9d8: 0800ca19 .word 0x0800ca19 800c9dc: 0800ca19 .word 0x0800ca19 800c9e0: 0800ca19 .word 0x0800ca19 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800c9e4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9e8: 3308 adds r3, #8 800c9ea: 2101 movs r1, #1 800c9ec: 4618 mov r0, r3 800c9ee: f001 fdd3 bl 800e598 800c9f2: 4603 mov r3, r0 800c9f4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800c9f8: e00f b.n 800ca1a case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800c9fa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9fe: 3328 adds r3, #40 @ 0x28 800ca00: 2101 movs r1, #1 800ca02: 4618 mov r0, r3 800ca04: f001 fe7a bl 800e6fc 800ca08: 4603 mov r3, r0 800ca0a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800ca0e: e004 b.n 800ca1a /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ca10: 2301 movs r3, #1 800ca12: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ca16: e000 b.n 800ca1a break; 800ca18: bf00 nop } if (ret == HAL_OK) 800ca1a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca1e: 2b00 cmp r3, #0 800ca20: d10b bne.n 800ca3a { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800ca22: 4b6c ldr r3, [pc, #432] @ (800cbd4 ) 800ca24: 6d9b ldr r3, [r3, #88] @ 0x58 800ca26: f023 0107 bic.w r1, r3, #7 800ca2a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca2e: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800ca32: 4a68 ldr r2, [pc, #416] @ (800cbd4 ) 800ca34: 430b orrs r3, r1 800ca36: 6593 str r3, [r2, #88] @ 0x58 800ca38: e003 b.n 800ca42 } else { /* set overall return value */ status = ret; 800ca3a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca3e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800ca42: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca46: e9d3 2300 ldrd r2, r3, [r3] 800ca4a: f002 0320 and.w r3, r2, #32 800ca4e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800ca52: 2300 movs r3, #0 800ca54: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800ca58: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800ca5c: 460b mov r3, r1 800ca5e: 4313 orrs r3, r2 800ca60: d055 beq.n 800cb0e { switch (PeriphClkInit->Lptim1ClockSelection) 800ca62: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca66: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800ca6a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800ca6e: d033 beq.n 800cad8 800ca70: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800ca74: d82c bhi.n 800cad0 800ca76: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800ca7a: d02f beq.n 800cadc 800ca7c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800ca80: d826 bhi.n 800cad0 800ca82: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800ca86: d02b beq.n 800cae0 800ca88: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800ca8c: d820 bhi.n 800cad0 800ca8e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800ca92: d012 beq.n 800caba 800ca94: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800ca98: d81a bhi.n 800cad0 800ca9a: 2b00 cmp r3, #0 800ca9c: d022 beq.n 800cae4 800ca9e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800caa2: d115 bne.n 800cad0 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800caa4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caa8: 3308 adds r3, #8 800caaa: 2100 movs r1, #0 800caac: 4618 mov r0, r3 800caae: f001 fd73 bl 800e598 800cab2: 4603 mov r3, r0 800cab4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800cab8: e015 b.n 800cae6 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800caba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cabe: 3328 adds r3, #40 @ 0x28 800cac0: 2102 movs r1, #2 800cac2: 4618 mov r0, r3 800cac4: f001 fe1a bl 800e6fc 800cac8: 4603 mov r3, r0 800caca: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800cace: e00a b.n 800cae6 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cad0: 2301 movs r3, #1 800cad2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cad6: e006 b.n 800cae6 break; 800cad8: bf00 nop 800cada: e004 b.n 800cae6 break; 800cadc: bf00 nop 800cade: e002 b.n 800cae6 break; 800cae0: bf00 nop 800cae2: e000 b.n 800cae6 break; 800cae4: bf00 nop } if (ret == HAL_OK) 800cae6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800caea: 2b00 cmp r3, #0 800caec: d10b bne.n 800cb06 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800caee: 4b39 ldr r3, [pc, #228] @ (800cbd4 ) 800caf0: 6d5b ldr r3, [r3, #84] @ 0x54 800caf2: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800caf6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cafa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800cafe: 4a35 ldr r2, [pc, #212] @ (800cbd4 ) 800cb00: 430b orrs r3, r1 800cb02: 6553 str r3, [r2, #84] @ 0x54 800cb04: e003 b.n 800cb0e } else { /* set overall return value */ status = ret; 800cb06: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb0a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800cb0e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb12: e9d3 2300 ldrd r2, r3, [r3] 800cb16: f002 0340 and.w r3, r2, #64 @ 0x40 800cb1a: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800cb1e: 2300 movs r3, #0 800cb20: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800cb24: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 800cb28: 460b mov r3, r1 800cb2a: 4313 orrs r3, r2 800cb2c: d058 beq.n 800cbe0 { switch (PeriphClkInit->Lptim2ClockSelection) 800cb2e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb32: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800cb36: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800cb3a: d033 beq.n 800cba4 800cb3c: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800cb40: d82c bhi.n 800cb9c 800cb42: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800cb46: d02f beq.n 800cba8 800cb48: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800cb4c: d826 bhi.n 800cb9c 800cb4e: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800cb52: d02b beq.n 800cbac 800cb54: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800cb58: d820 bhi.n 800cb9c 800cb5a: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800cb5e: d012 beq.n 800cb86 800cb60: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800cb64: d81a bhi.n 800cb9c 800cb66: 2b00 cmp r3, #0 800cb68: d022 beq.n 800cbb0 800cb6a: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800cb6e: d115 bne.n 800cb9c /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cb70: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb74: 3308 adds r3, #8 800cb76: 2100 movs r1, #0 800cb78: 4618 mov r0, r3 800cb7a: f001 fd0d bl 800e598 800cb7e: 4603 mov r3, r0 800cb80: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800cb84: e015 b.n 800cbb2 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800cb86: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb8a: 3328 adds r3, #40 @ 0x28 800cb8c: 2102 movs r1, #2 800cb8e: 4618 mov r0, r3 800cb90: f001 fdb4 bl 800e6fc 800cb94: 4603 mov r3, r0 800cb96: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800cb9a: e00a b.n 800cbb2 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cb9c: 2301 movs r3, #1 800cb9e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cba2: e006 b.n 800cbb2 break; 800cba4: bf00 nop 800cba6: e004 b.n 800cbb2 break; 800cba8: bf00 nop 800cbaa: e002 b.n 800cbb2 break; 800cbac: bf00 nop 800cbae: e000 b.n 800cbb2 break; 800cbb0: bf00 nop } if (ret == HAL_OK) 800cbb2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cbb6: 2b00 cmp r3, #0 800cbb8: d10e bne.n 800cbd8 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800cbba: 4b06 ldr r3, [pc, #24] @ (800cbd4 ) 800cbbc: 6d9b ldr r3, [r3, #88] @ 0x58 800cbbe: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 800cbc2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbc6: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800cbca: 4a02 ldr r2, [pc, #8] @ (800cbd4 ) 800cbcc: 430b orrs r3, r1 800cbce: 6593 str r3, [r2, #88] @ 0x58 800cbd0: e006 b.n 800cbe0 800cbd2: bf00 nop 800cbd4: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800cbd8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cbdc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800cbe0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbe4: e9d3 2300 ldrd r2, r3, [r3] 800cbe8: f002 0380 and.w r3, r2, #128 @ 0x80 800cbec: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800cbf0: 2300 movs r3, #0 800cbf2: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800cbf6: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800cbfa: 460b mov r3, r1 800cbfc: 4313 orrs r3, r2 800cbfe: d055 beq.n 800ccac { switch (PeriphClkInit->Lptim345ClockSelection) 800cc00: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc04: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800cc08: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800cc0c: d033 beq.n 800cc76 800cc0e: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800cc12: d82c bhi.n 800cc6e 800cc14: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800cc18: d02f beq.n 800cc7a 800cc1a: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800cc1e: d826 bhi.n 800cc6e 800cc20: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800cc24: d02b beq.n 800cc7e 800cc26: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800cc2a: d820 bhi.n 800cc6e 800cc2c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800cc30: d012 beq.n 800cc58 800cc32: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800cc36: d81a bhi.n 800cc6e 800cc38: 2b00 cmp r3, #0 800cc3a: d022 beq.n 800cc82 800cc3c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800cc40: d115 bne.n 800cc6e case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cc42: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc46: 3308 adds r3, #8 800cc48: 2100 movs r1, #0 800cc4a: 4618 mov r0, r3 800cc4c: f001 fca4 bl 800e598 800cc50: 4603 mov r3, r0 800cc52: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800cc56: e015 b.n 800cc84 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800cc58: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc5c: 3328 adds r3, #40 @ 0x28 800cc5e: 2102 movs r1, #2 800cc60: 4618 mov r0, r3 800cc62: f001 fd4b bl 800e6fc 800cc66: 4603 mov r3, r0 800cc68: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800cc6c: e00a b.n 800cc84 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cc6e: 2301 movs r3, #1 800cc70: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cc74: e006 b.n 800cc84 break; 800cc76: bf00 nop 800cc78: e004 b.n 800cc84 break; 800cc7a: bf00 nop 800cc7c: e002 b.n 800cc84 break; 800cc7e: bf00 nop 800cc80: e000 b.n 800cc84 break; 800cc82: bf00 nop } if (ret == HAL_OK) 800cc84: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc88: 2b00 cmp r3, #0 800cc8a: d10b bne.n 800cca4 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800cc8c: 4bbb ldr r3, [pc, #748] @ (800cf7c ) 800cc8e: 6d9b ldr r3, [r3, #88] @ 0x58 800cc90: f423 4160 bic.w r1, r3, #57344 @ 0xe000 800cc94: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc98: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800cc9c: 4ab7 ldr r2, [pc, #732] @ (800cf7c ) 800cc9e: 430b orrs r3, r1 800cca0: 6593 str r3, [r2, #88] @ 0x58 800cca2: e003 b.n 800ccac } else { /* set overall return value */ status = ret; 800cca4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cca8: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800ccac: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccb0: e9d3 2300 ldrd r2, r3, [r3] 800ccb4: f002 0308 and.w r3, r2, #8 800ccb8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800ccbc: 2300 movs r3, #0 800ccbe: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800ccc2: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 800ccc6: 460b mov r3, r1 800ccc8: 4313 orrs r3, r2 800ccca: d01e beq.n 800cd0a { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 800cccc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccd0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800ccd4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800ccd8: d10c bne.n 800ccf4 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800ccda: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccde: 3328 adds r3, #40 @ 0x28 800cce0: 2102 movs r1, #2 800cce2: 4618 mov r0, r3 800cce4: f001 fd0a bl 800e6fc 800cce8: 4603 mov r3, r0 800ccea: 2b00 cmp r3, #0 800ccec: d002 beq.n 800ccf4 { status = HAL_ERROR; 800ccee: 2301 movs r3, #1 800ccf0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800ccf4: 4ba1 ldr r3, [pc, #644] @ (800cf7c ) 800ccf6: 6d5b ldr r3, [r3, #84] @ 0x54 800ccf8: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800ccfc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd00: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800cd04: 4a9d ldr r2, [pc, #628] @ (800cf7c ) 800cd06: 430b orrs r3, r1 800cd08: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800cd0a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd0e: e9d3 2300 ldrd r2, r3, [r3] 800cd12: f002 0310 and.w r3, r2, #16 800cd16: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800cd1a: 2300 movs r3, #0 800cd1c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800cd20: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 800cd24: 460b mov r3, r1 800cd26: 4313 orrs r3, r2 800cd28: d01e beq.n 800cd68 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800cd2a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd2e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800cd32: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cd36: d10c bne.n 800cd52 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800cd38: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd3c: 3328 adds r3, #40 @ 0x28 800cd3e: 2102 movs r1, #2 800cd40: 4618 mov r0, r3 800cd42: f001 fcdb bl 800e6fc 800cd46: 4603 mov r3, r0 800cd48: 2b00 cmp r3, #0 800cd4a: d002 beq.n 800cd52 { status = HAL_ERROR; 800cd4c: 2301 movs r3, #1 800cd4e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800cd52: 4b8a ldr r3, [pc, #552] @ (800cf7c ) 800cd54: 6d9b ldr r3, [r3, #88] @ 0x58 800cd56: f423 7140 bic.w r1, r3, #768 @ 0x300 800cd5a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd5e: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800cd62: 4a86 ldr r2, [pc, #536] @ (800cf7c ) 800cd64: 430b orrs r3, r1 800cd66: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800cd68: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd6c: e9d3 2300 ldrd r2, r3, [r3] 800cd70: f402 2300 and.w r3, r2, #524288 @ 0x80000 800cd74: 67bb str r3, [r7, #120] @ 0x78 800cd76: 2300 movs r3, #0 800cd78: 67fb str r3, [r7, #124] @ 0x7c 800cd7a: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800cd7e: 460b mov r3, r1 800cd80: 4313 orrs r3, r2 800cd82: d03e beq.n 800ce02 { switch (PeriphClkInit->AdcClockSelection) 800cd84: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd88: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800cd8c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cd90: d022 beq.n 800cdd8 800cd92: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cd96: d81b bhi.n 800cdd0 800cd98: 2b00 cmp r3, #0 800cd9a: d003 beq.n 800cda4 800cd9c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cda0: d00b beq.n 800cdba 800cda2: e015 b.n 800cdd0 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cda4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cda8: 3308 adds r3, #8 800cdaa: 2100 movs r1, #0 800cdac: 4618 mov r0, r3 800cdae: f001 fbf3 bl 800e598 800cdb2: 4603 mov r3, r0 800cdb4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800cdb8: e00f b.n 800cdda case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800cdba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdbe: 3328 adds r3, #40 @ 0x28 800cdc0: 2102 movs r1, #2 800cdc2: 4618 mov r0, r3 800cdc4: f001 fc9a bl 800e6fc 800cdc8: 4603 mov r3, r0 800cdca: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800cdce: e004 b.n 800cdda /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cdd0: 2301 movs r3, #1 800cdd2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cdd6: e000 b.n 800cdda break; 800cdd8: bf00 nop } if (ret == HAL_OK) 800cdda: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdde: 2b00 cmp r3, #0 800cde0: d10b bne.n 800cdfa { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800cde2: 4b66 ldr r3, [pc, #408] @ (800cf7c ) 800cde4: 6d9b ldr r3, [r3, #88] @ 0x58 800cde6: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800cdea: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdee: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800cdf2: 4a62 ldr r2, [pc, #392] @ (800cf7c ) 800cdf4: 430b orrs r3, r1 800cdf6: 6593 str r3, [r2, #88] @ 0x58 800cdf8: e003 b.n 800ce02 } else { /* set overall return value */ status = ret; 800cdfa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdfe: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800ce02: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce06: e9d3 2300 ldrd r2, r3, [r3] 800ce0a: f402 2380 and.w r3, r2, #262144 @ 0x40000 800ce0e: 673b str r3, [r7, #112] @ 0x70 800ce10: 2300 movs r3, #0 800ce12: 677b str r3, [r7, #116] @ 0x74 800ce14: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800ce18: 460b mov r3, r1 800ce1a: 4313 orrs r3, r2 800ce1c: d03b beq.n 800ce96 { switch (PeriphClkInit->UsbClockSelection) 800ce1e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce22: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800ce26: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800ce2a: d01f beq.n 800ce6c 800ce2c: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800ce30: d818 bhi.n 800ce64 800ce32: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800ce36: d003 beq.n 800ce40 800ce38: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800ce3c: d007 beq.n 800ce4e 800ce3e: e011 b.n 800ce64 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ce40: 4b4e ldr r3, [pc, #312] @ (800cf7c ) 800ce42: 6adb ldr r3, [r3, #44] @ 0x2c 800ce44: 4a4d ldr r2, [pc, #308] @ (800cf7c ) 800ce46: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ce4a: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800ce4c: e00f b.n 800ce6e case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800ce4e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce52: 3328 adds r3, #40 @ 0x28 800ce54: 2101 movs r1, #1 800ce56: 4618 mov r0, r3 800ce58: f001 fc50 bl 800e6fc 800ce5c: 4603 mov r3, r0 800ce5e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 800ce62: e004 b.n 800ce6e /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ce64: 2301 movs r3, #1 800ce66: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce6a: e000 b.n 800ce6e break; 800ce6c: bf00 nop } if (ret == HAL_OK) 800ce6e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce72: 2b00 cmp r3, #0 800ce74: d10b bne.n 800ce8e { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800ce76: 4b41 ldr r3, [pc, #260] @ (800cf7c ) 800ce78: 6d5b ldr r3, [r3, #84] @ 0x54 800ce7a: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800ce7e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce82: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800ce86: 4a3d ldr r2, [pc, #244] @ (800cf7c ) 800ce88: 430b orrs r3, r1 800ce8a: 6553 str r3, [r2, #84] @ 0x54 800ce8c: e003 b.n 800ce96 } else { /* set overall return value */ status = ret; 800ce8e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce92: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 800ce96: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce9a: e9d3 2300 ldrd r2, r3, [r3] 800ce9e: f402 3380 and.w r3, r2, #65536 @ 0x10000 800cea2: 66bb str r3, [r7, #104] @ 0x68 800cea4: 2300 movs r3, #0 800cea6: 66fb str r3, [r7, #108] @ 0x6c 800cea8: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 800ceac: 460b mov r3, r1 800ceae: 4313 orrs r3, r2 800ceb0: d031 beq.n 800cf16 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 800ceb2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ceb6: 6d1b ldr r3, [r3, #80] @ 0x50 800ceb8: 2b00 cmp r3, #0 800ceba: d003 beq.n 800cec4 800cebc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cec0: d007 beq.n 800ced2 800cec2: e011 b.n 800cee8 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cec4: 4b2d ldr r3, [pc, #180] @ (800cf7c ) 800cec6: 6adb ldr r3, [r3, #44] @ 0x2c 800cec8: 4a2c ldr r2, [pc, #176] @ (800cf7c ) 800ceca: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cece: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 800ced0: e00e b.n 800cef0 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800ced2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ced6: 3308 adds r3, #8 800ced8: 2102 movs r1, #2 800ceda: 4618 mov r0, r3 800cedc: f001 fb5c bl 800e598 800cee0: 4603 mov r3, r0 800cee2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 800cee6: e003 b.n 800cef0 default: ret = HAL_ERROR; 800cee8: 2301 movs r3, #1 800ceea: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ceee: bf00 nop } if (ret == HAL_OK) 800cef0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cef4: 2b00 cmp r3, #0 800cef6: d10a bne.n 800cf0e { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 800cef8: 4b20 ldr r3, [pc, #128] @ (800cf7c ) 800cefa: 6cdb ldr r3, [r3, #76] @ 0x4c 800cefc: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800cf00: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf04: 6d1b ldr r3, [r3, #80] @ 0x50 800cf06: 4a1d ldr r2, [pc, #116] @ (800cf7c ) 800cf08: 430b orrs r3, r1 800cf0a: 64d3 str r3, [r2, #76] @ 0x4c 800cf0c: e003 b.n 800cf16 } else { /* set overall return value */ status = ret; 800cf0e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf12: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 800cf16: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf1a: e9d3 2300 ldrd r2, r3, [r3] 800cf1e: f402 3300 and.w r3, r2, #131072 @ 0x20000 800cf22: 663b str r3, [r7, #96] @ 0x60 800cf24: 2300 movs r3, #0 800cf26: 667b str r3, [r7, #100] @ 0x64 800cf28: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800cf2c: 460b mov r3, r1 800cf2e: 4313 orrs r3, r2 800cf30: d03b beq.n 800cfaa { switch (PeriphClkInit->RngClockSelection) 800cf32: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf36: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800cf3a: f5b3 7f40 cmp.w r3, #768 @ 0x300 800cf3e: d018 beq.n 800cf72 800cf40: f5b3 7f40 cmp.w r3, #768 @ 0x300 800cf44: d811 bhi.n 800cf6a 800cf46: f5b3 7f00 cmp.w r3, #512 @ 0x200 800cf4a: d014 beq.n 800cf76 800cf4c: f5b3 7f00 cmp.w r3, #512 @ 0x200 800cf50: d80b bhi.n 800cf6a 800cf52: 2b00 cmp r3, #0 800cf54: d014 beq.n 800cf80 800cf56: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cf5a: d106 bne.n 800cf6a { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cf5c: 4b07 ldr r3, [pc, #28] @ (800cf7c ) 800cf5e: 6adb ldr r3, [r3, #44] @ 0x2c 800cf60: 4a06 ldr r2, [pc, #24] @ (800cf7c ) 800cf62: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cf66: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800cf68: e00b b.n 800cf82 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cf6a: 2301 movs r3, #1 800cf6c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cf70: e007 b.n 800cf82 break; 800cf72: bf00 nop 800cf74: e005 b.n 800cf82 break; 800cf76: bf00 nop 800cf78: e003 b.n 800cf82 800cf7a: bf00 nop 800cf7c: 58024400 .word 0x58024400 break; 800cf80: bf00 nop } if (ret == HAL_OK) 800cf82: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf86: 2b00 cmp r3, #0 800cf88: d10b bne.n 800cfa2 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800cf8a: 4bba ldr r3, [pc, #744] @ (800d274 ) 800cf8c: 6d5b ldr r3, [r3, #84] @ 0x54 800cf8e: f423 7140 bic.w r1, r3, #768 @ 0x300 800cf92: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf96: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800cf9a: 4ab6 ldr r2, [pc, #728] @ (800d274 ) 800cf9c: 430b orrs r3, r1 800cf9e: 6553 str r3, [r2, #84] @ 0x54 800cfa0: e003 b.n 800cfaa } else { /* set overall return value */ status = ret; 800cfa2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cfa6: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800cfaa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfae: e9d3 2300 ldrd r2, r3, [r3] 800cfb2: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800cfb6: 65bb str r3, [r7, #88] @ 0x58 800cfb8: 2300 movs r3, #0 800cfba: 65fb str r3, [r7, #92] @ 0x5c 800cfbc: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 800cfc0: 460b mov r3, r1 800cfc2: 4313 orrs r3, r2 800cfc4: d009 beq.n 800cfda { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800cfc6: 4bab ldr r3, [pc, #684] @ (800d274 ) 800cfc8: 6d1b ldr r3, [r3, #80] @ 0x50 800cfca: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 800cfce: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfd2: 6f5b ldr r3, [r3, #116] @ 0x74 800cfd4: 4aa7 ldr r2, [pc, #668] @ (800d274 ) 800cfd6: 430b orrs r3, r1 800cfd8: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800cfda: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfde: e9d3 2300 ldrd r2, r3, [r3] 800cfe2: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 800cfe6: 653b str r3, [r7, #80] @ 0x50 800cfe8: 2300 movs r3, #0 800cfea: 657b str r3, [r7, #84] @ 0x54 800cfec: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 800cff0: 460b mov r3, r1 800cff2: 4313 orrs r3, r2 800cff4: d00a beq.n 800d00c { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 800cff6: 4b9f ldr r3, [pc, #636] @ (800d274 ) 800cff8: 691b ldr r3, [r3, #16] 800cffa: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800cffe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d002: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 800d006: 4a9b ldr r2, [pc, #620] @ (800d274 ) 800d008: 430b orrs r3, r1 800d00a: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800d00c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d010: e9d3 2300 ldrd r2, r3, [r3] 800d014: f402 1300 and.w r3, r2, #2097152 @ 0x200000 800d018: 64bb str r3, [r7, #72] @ 0x48 800d01a: 2300 movs r3, #0 800d01c: 64fb str r3, [r7, #76] @ 0x4c 800d01e: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 800d022: 460b mov r3, r1 800d024: 4313 orrs r3, r2 800d026: d009 beq.n 800d03c { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800d028: 4b92 ldr r3, [pc, #584] @ (800d274 ) 800d02a: 6d1b ldr r3, [r3, #80] @ 0x50 800d02c: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 800d030: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d034: 6edb ldr r3, [r3, #108] @ 0x6c 800d036: 4a8f ldr r2, [pc, #572] @ (800d274 ) 800d038: 430b orrs r3, r1 800d03a: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800d03c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d040: e9d3 2300 ldrd r2, r3, [r3] 800d044: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800d048: 643b str r3, [r7, #64] @ 0x40 800d04a: 2300 movs r3, #0 800d04c: 647b str r3, [r7, #68] @ 0x44 800d04e: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 800d052: 460b mov r3, r1 800d054: 4313 orrs r3, r2 800d056: d00e beq.n 800d076 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800d058: 4b86 ldr r3, [pc, #536] @ (800d274 ) 800d05a: 691b ldr r3, [r3, #16] 800d05c: 4a85 ldr r2, [pc, #532] @ (800d274 ) 800d05e: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800d062: 6113 str r3, [r2, #16] 800d064: 4b83 ldr r3, [pc, #524] @ (800d274 ) 800d066: 6919 ldr r1, [r3, #16] 800d068: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d06c: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 800d070: 4a80 ldr r2, [pc, #512] @ (800d274 ) 800d072: 430b orrs r3, r1 800d074: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800d076: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d07a: e9d3 2300 ldrd r2, r3, [r3] 800d07e: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 800d082: 63bb str r3, [r7, #56] @ 0x38 800d084: 2300 movs r3, #0 800d086: 63fb str r3, [r7, #60] @ 0x3c 800d088: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 800d08c: 460b mov r3, r1 800d08e: 4313 orrs r3, r2 800d090: d009 beq.n 800d0a6 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800d092: 4b78 ldr r3, [pc, #480] @ (800d274 ) 800d094: 6cdb ldr r3, [r3, #76] @ 0x4c 800d096: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800d09a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d09e: 6d5b ldr r3, [r3, #84] @ 0x54 800d0a0: 4a74 ldr r2, [pc, #464] @ (800d274 ) 800d0a2: 430b orrs r3, r1 800d0a4: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800d0a6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0aa: e9d3 2300 ldrd r2, r3, [r3] 800d0ae: f402 0300 and.w r3, r2, #8388608 @ 0x800000 800d0b2: 633b str r3, [r7, #48] @ 0x30 800d0b4: 2300 movs r3, #0 800d0b6: 637b str r3, [r7, #52] @ 0x34 800d0b8: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 800d0bc: 460b mov r3, r1 800d0be: 4313 orrs r3, r2 800d0c0: d00a beq.n 800d0d8 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800d0c2: 4b6c ldr r3, [pc, #432] @ (800d274 ) 800d0c4: 6d5b ldr r3, [r3, #84] @ 0x54 800d0c6: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 800d0ca: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0ce: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800d0d2: 4a68 ldr r2, [pc, #416] @ (800d274 ) 800d0d4: 430b orrs r3, r1 800d0d6: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 800d0d8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0dc: e9d3 2300 ldrd r2, r3, [r3] 800d0e0: 2100 movs r1, #0 800d0e2: 62b9 str r1, [r7, #40] @ 0x28 800d0e4: f003 0301 and.w r3, r3, #1 800d0e8: 62fb str r3, [r7, #44] @ 0x2c 800d0ea: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800d0ee: 460b mov r3, r1 800d0f0: 4313 orrs r3, r2 800d0f2: d011 beq.n 800d118 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d0f4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0f8: 3308 adds r3, #8 800d0fa: 2100 movs r1, #0 800d0fc: 4618 mov r0, r3 800d0fe: f001 fa4b bl 800e598 800d102: 4603 mov r3, r0 800d104: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d108: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d10c: 2b00 cmp r3, #0 800d10e: d003 beq.n 800d118 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d110: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d114: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800d118: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d11c: e9d3 2300 ldrd r2, r3, [r3] 800d120: 2100 movs r1, #0 800d122: 6239 str r1, [r7, #32] 800d124: f003 0302 and.w r3, r3, #2 800d128: 627b str r3, [r7, #36] @ 0x24 800d12a: e9d7 1208 ldrd r1, r2, [r7, #32] 800d12e: 460b mov r3, r1 800d130: 4313 orrs r3, r2 800d132: d011 beq.n 800d158 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d134: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d138: 3308 adds r3, #8 800d13a: 2101 movs r1, #1 800d13c: 4618 mov r0, r3 800d13e: f001 fa2b bl 800e598 800d142: 4603 mov r3, r0 800d144: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d148: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d14c: 2b00 cmp r3, #0 800d14e: d003 beq.n 800d158 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d150: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d154: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800d158: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d15c: e9d3 2300 ldrd r2, r3, [r3] 800d160: 2100 movs r1, #0 800d162: 61b9 str r1, [r7, #24] 800d164: f003 0304 and.w r3, r3, #4 800d168: 61fb str r3, [r7, #28] 800d16a: e9d7 1206 ldrd r1, r2, [r7, #24] 800d16e: 460b mov r3, r1 800d170: 4313 orrs r3, r2 800d172: d011 beq.n 800d198 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d174: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d178: 3308 adds r3, #8 800d17a: 2102 movs r1, #2 800d17c: 4618 mov r0, r3 800d17e: f001 fa0b bl 800e598 800d182: 4603 mov r3, r0 800d184: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d188: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d18c: 2b00 cmp r3, #0 800d18e: d003 beq.n 800d198 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d190: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d194: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800d198: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d19c: e9d3 2300 ldrd r2, r3, [r3] 800d1a0: 2100 movs r1, #0 800d1a2: 6139 str r1, [r7, #16] 800d1a4: f003 0308 and.w r3, r3, #8 800d1a8: 617b str r3, [r7, #20] 800d1aa: e9d7 1204 ldrd r1, r2, [r7, #16] 800d1ae: 460b mov r3, r1 800d1b0: 4313 orrs r3, r2 800d1b2: d011 beq.n 800d1d8 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800d1b4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1b8: 3328 adds r3, #40 @ 0x28 800d1ba: 2100 movs r1, #0 800d1bc: 4618 mov r0, r3 800d1be: f001 fa9d bl 800e6fc 800d1c2: 4603 mov r3, r0 800d1c4: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d1c8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d1cc: 2b00 cmp r3, #0 800d1ce: d003 beq.n 800d1d8 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d1d0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d1d4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800d1d8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1dc: e9d3 2300 ldrd r2, r3, [r3] 800d1e0: 2100 movs r1, #0 800d1e2: 60b9 str r1, [r7, #8] 800d1e4: f003 0310 and.w r3, r3, #16 800d1e8: 60fb str r3, [r7, #12] 800d1ea: e9d7 1202 ldrd r1, r2, [r7, #8] 800d1ee: 460b mov r3, r1 800d1f0: 4313 orrs r3, r2 800d1f2: d011 beq.n 800d218 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d1f4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1f8: 3328 adds r3, #40 @ 0x28 800d1fa: 2101 movs r1, #1 800d1fc: 4618 mov r0, r3 800d1fe: f001 fa7d bl 800e6fc 800d202: 4603 mov r3, r0 800d204: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d208: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d20c: 2b00 cmp r3, #0 800d20e: d003 beq.n 800d218 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d210: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d214: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800d218: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d21c: e9d3 2300 ldrd r2, r3, [r3] 800d220: 2100 movs r1, #0 800d222: 6039 str r1, [r7, #0] 800d224: f003 0320 and.w r3, r3, #32 800d228: 607b str r3, [r7, #4] 800d22a: e9d7 1200 ldrd r1, r2, [r7] 800d22e: 460b mov r3, r1 800d230: 4313 orrs r3, r2 800d232: d011 beq.n 800d258 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d234: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d238: 3328 adds r3, #40 @ 0x28 800d23a: 2102 movs r1, #2 800d23c: 4618 mov r0, r3 800d23e: f001 fa5d bl 800e6fc 800d242: 4603 mov r3, r0 800d244: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800d248: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d24c: 2b00 cmp r3, #0 800d24e: d003 beq.n 800d258 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800d250: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d254: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 800d258: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800d25c: 2b00 cmp r3, #0 800d25e: d101 bne.n 800d264 { return HAL_OK; 800d260: 2300 movs r3, #0 800d262: e000 b.n 800d266 } return HAL_ERROR; 800d264: 2301 movs r3, #1 } 800d266: 4618 mov r0, r3 800d268: f507 7790 add.w r7, r7, #288 @ 0x120 800d26c: 46bd mov sp, r7 800d26e: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800d272: bf00 nop 800d274: 58024400 .word 0x58024400 0800d278 : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800d278: b580 push {r7, lr} 800d27a: b090 sub sp, #64 @ 0x40 800d27c: af00 add r7, sp, #0 800d27e: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 800d282: e9d7 2300 ldrd r2, r3, [r7] 800d286: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800d28a: 430b orrs r3, r1 800d28c: f040 8094 bne.w 800d3b8 { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800d290: 4b9e ldr r3, [pc, #632] @ (800d50c ) 800d292: 6d1b ldr r3, [r3, #80] @ 0x50 800d294: f003 0307 and.w r3, r3, #7 800d298: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800d29a: 6b3b ldr r3, [r7, #48] @ 0x30 800d29c: 2b04 cmp r3, #4 800d29e: f200 8087 bhi.w 800d3b0 800d2a2: a201 add r2, pc, #4 @ (adr r2, 800d2a8 ) 800d2a4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d2a8: 0800d2bd .word 0x0800d2bd 800d2ac: 0800d2e5 .word 0x0800d2e5 800d2b0: 0800d30d .word 0x0800d30d 800d2b4: 0800d3a9 .word 0x0800d3a9 800d2b8: 0800d335 .word 0x0800d335 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800d2bc: 4b93 ldr r3, [pc, #588] @ (800d50c ) 800d2be: 681b ldr r3, [r3, #0] 800d2c0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800d2c4: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800d2c8: d108 bne.n 800d2dc { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800d2ca: f107 0324 add.w r3, r7, #36 @ 0x24 800d2ce: 4618 mov r0, r3 800d2d0: f001 f810 bl 800e2f4 frequency = pll1_clocks.PLL1_Q_Frequency; 800d2d4: 6abb ldr r3, [r7, #40] @ 0x28 800d2d6: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d2d8: f000 bd45 b.w 800dd66 frequency = 0; 800d2dc: 2300 movs r3, #0 800d2de: 63fb str r3, [r7, #60] @ 0x3c break; 800d2e0: f000 bd41 b.w 800dd66 } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800d2e4: 4b89 ldr r3, [pc, #548] @ (800d50c ) 800d2e6: 681b ldr r3, [r3, #0] 800d2e8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800d2ec: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800d2f0: d108 bne.n 800d304 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d2f2: f107 0318 add.w r3, r7, #24 800d2f6: 4618 mov r0, r3 800d2f8: f000 fd54 bl 800dda4 frequency = pll2_clocks.PLL2_P_Frequency; 800d2fc: 69bb ldr r3, [r7, #24] 800d2fe: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d300: f000 bd31 b.w 800dd66 frequency = 0; 800d304: 2300 movs r3, #0 800d306: 63fb str r3, [r7, #60] @ 0x3c break; 800d308: f000 bd2d b.w 800dd66 } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800d30c: 4b7f ldr r3, [pc, #508] @ (800d50c ) 800d30e: 681b ldr r3, [r3, #0] 800d310: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800d314: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d318: d108 bne.n 800d32c { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d31a: f107 030c add.w r3, r7, #12 800d31e: 4618 mov r0, r3 800d320: f000 fe94 bl 800e04c frequency = pll3_clocks.PLL3_P_Frequency; 800d324: 68fb ldr r3, [r7, #12] 800d326: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d328: f000 bd1d b.w 800dd66 frequency = 0; 800d32c: 2300 movs r3, #0 800d32e: 63fb str r3, [r7, #60] @ 0x3c break; 800d330: f000 bd19 b.w 800dd66 } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800d334: 4b75 ldr r3, [pc, #468] @ (800d50c ) 800d336: 6cdb ldr r3, [r3, #76] @ 0x4c 800d338: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800d33c: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800d33e: 4b73 ldr r3, [pc, #460] @ (800d50c ) 800d340: 681b ldr r3, [r3, #0] 800d342: f003 0304 and.w r3, r3, #4 800d346: 2b04 cmp r3, #4 800d348: d10c bne.n 800d364 800d34a: 6b7b ldr r3, [r7, #52] @ 0x34 800d34c: 2b00 cmp r3, #0 800d34e: d109 bne.n 800d364 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d350: 4b6e ldr r3, [pc, #440] @ (800d50c ) 800d352: 681b ldr r3, [r3, #0] 800d354: 08db lsrs r3, r3, #3 800d356: f003 0303 and.w r3, r3, #3 800d35a: 4a6d ldr r2, [pc, #436] @ (800d510 ) 800d35c: fa22 f303 lsr.w r3, r2, r3 800d360: 63fb str r3, [r7, #60] @ 0x3c 800d362: e01f b.n 800d3a4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800d364: 4b69 ldr r3, [pc, #420] @ (800d50c ) 800d366: 681b ldr r3, [r3, #0] 800d368: f403 7380 and.w r3, r3, #256 @ 0x100 800d36c: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d370: d106 bne.n 800d380 800d372: 6b7b ldr r3, [r7, #52] @ 0x34 800d374: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d378: d102 bne.n 800d380 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800d37a: 4b66 ldr r3, [pc, #408] @ (800d514 ) 800d37c: 63fb str r3, [r7, #60] @ 0x3c 800d37e: e011 b.n 800d3a4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800d380: 4b62 ldr r3, [pc, #392] @ (800d50c ) 800d382: 681b ldr r3, [r3, #0] 800d384: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d388: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d38c: d106 bne.n 800d39c 800d38e: 6b7b ldr r3, [r7, #52] @ 0x34 800d390: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d394: d102 bne.n 800d39c { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800d396: 4b60 ldr r3, [pc, #384] @ (800d518 ) 800d398: 63fb str r3, [r7, #60] @ 0x3c 800d39a: e003 b.n 800d3a4 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800d39c: 2300 movs r3, #0 800d39e: 63fb str r3, [r7, #60] @ 0x3c } break; 800d3a0: f000 bce1 b.w 800dd66 800d3a4: f000 bcdf b.w 800dd66 } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800d3a8: 4b5c ldr r3, [pc, #368] @ (800d51c ) 800d3aa: 63fb str r3, [r7, #60] @ 0x3c break; 800d3ac: f000 bcdb b.w 800dd66 } default : { frequency = 0; 800d3b0: 2300 movs r3, #0 800d3b2: 63fb str r3, [r7, #60] @ 0x3c break; 800d3b4: f000 bcd7 b.w 800dd66 } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800d3b8: e9d7 2300 ldrd r2, r3, [r7] 800d3bc: f5a2 7100 sub.w r1, r2, #512 @ 0x200 800d3c0: 430b orrs r3, r1 800d3c2: f040 80ad bne.w 800d520 { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800d3c6: 4b51 ldr r3, [pc, #324] @ (800d50c ) 800d3c8: 6d1b ldr r3, [r3, #80] @ 0x50 800d3ca: f403 73e0 and.w r3, r3, #448 @ 0x1c0 800d3ce: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800d3d0: 6b3b ldr r3, [r7, #48] @ 0x30 800d3d2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d3d6: d056 beq.n 800d486 800d3d8: 6b3b ldr r3, [r7, #48] @ 0x30 800d3da: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d3de: f200 8090 bhi.w 800d502 800d3e2: 6b3b ldr r3, [r7, #48] @ 0x30 800d3e4: 2bc0 cmp r3, #192 @ 0xc0 800d3e6: f000 8088 beq.w 800d4fa 800d3ea: 6b3b ldr r3, [r7, #48] @ 0x30 800d3ec: 2bc0 cmp r3, #192 @ 0xc0 800d3ee: f200 8088 bhi.w 800d502 800d3f2: 6b3b ldr r3, [r7, #48] @ 0x30 800d3f4: 2b80 cmp r3, #128 @ 0x80 800d3f6: d032 beq.n 800d45e 800d3f8: 6b3b ldr r3, [r7, #48] @ 0x30 800d3fa: 2b80 cmp r3, #128 @ 0x80 800d3fc: f200 8081 bhi.w 800d502 800d400: 6b3b ldr r3, [r7, #48] @ 0x30 800d402: 2b00 cmp r3, #0 800d404: d003 beq.n 800d40e 800d406: 6b3b ldr r3, [r7, #48] @ 0x30 800d408: 2b40 cmp r3, #64 @ 0x40 800d40a: d014 beq.n 800d436 800d40c: e079 b.n 800d502 { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800d40e: 4b3f ldr r3, [pc, #252] @ (800d50c ) 800d410: 681b ldr r3, [r3, #0] 800d412: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800d416: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800d41a: d108 bne.n 800d42e { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800d41c: f107 0324 add.w r3, r7, #36 @ 0x24 800d420: 4618 mov r0, r3 800d422: f000 ff67 bl 800e2f4 frequency = pll1_clocks.PLL1_Q_Frequency; 800d426: 6abb ldr r3, [r7, #40] @ 0x28 800d428: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d42a: f000 bc9c b.w 800dd66 frequency = 0; 800d42e: 2300 movs r3, #0 800d430: 63fb str r3, [r7, #60] @ 0x3c break; 800d432: f000 bc98 b.w 800dd66 } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800d436: 4b35 ldr r3, [pc, #212] @ (800d50c ) 800d438: 681b ldr r3, [r3, #0] 800d43a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800d43e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800d442: d108 bne.n 800d456 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d444: f107 0318 add.w r3, r7, #24 800d448: 4618 mov r0, r3 800d44a: f000 fcab bl 800dda4 frequency = pll2_clocks.PLL2_P_Frequency; 800d44e: 69bb ldr r3, [r7, #24] 800d450: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d452: f000 bc88 b.w 800dd66 frequency = 0; 800d456: 2300 movs r3, #0 800d458: 63fb str r3, [r7, #60] @ 0x3c break; 800d45a: f000 bc84 b.w 800dd66 } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800d45e: 4b2b ldr r3, [pc, #172] @ (800d50c ) 800d460: 681b ldr r3, [r3, #0] 800d462: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800d466: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d46a: d108 bne.n 800d47e { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d46c: f107 030c add.w r3, r7, #12 800d470: 4618 mov r0, r3 800d472: f000 fdeb bl 800e04c frequency = pll3_clocks.PLL3_P_Frequency; 800d476: 68fb ldr r3, [r7, #12] 800d478: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d47a: f000 bc74 b.w 800dd66 frequency = 0; 800d47e: 2300 movs r3, #0 800d480: 63fb str r3, [r7, #60] @ 0x3c break; 800d482: f000 bc70 b.w 800dd66 } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800d486: 4b21 ldr r3, [pc, #132] @ (800d50c ) 800d488: 6cdb ldr r3, [r3, #76] @ 0x4c 800d48a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800d48e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800d490: 4b1e ldr r3, [pc, #120] @ (800d50c ) 800d492: 681b ldr r3, [r3, #0] 800d494: f003 0304 and.w r3, r3, #4 800d498: 2b04 cmp r3, #4 800d49a: d10c bne.n 800d4b6 800d49c: 6b7b ldr r3, [r7, #52] @ 0x34 800d49e: 2b00 cmp r3, #0 800d4a0: d109 bne.n 800d4b6 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d4a2: 4b1a ldr r3, [pc, #104] @ (800d50c ) 800d4a4: 681b ldr r3, [r3, #0] 800d4a6: 08db lsrs r3, r3, #3 800d4a8: f003 0303 and.w r3, r3, #3 800d4ac: 4a18 ldr r2, [pc, #96] @ (800d510 ) 800d4ae: fa22 f303 lsr.w r3, r2, r3 800d4b2: 63fb str r3, [r7, #60] @ 0x3c 800d4b4: e01f b.n 800d4f6 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800d4b6: 4b15 ldr r3, [pc, #84] @ (800d50c ) 800d4b8: 681b ldr r3, [r3, #0] 800d4ba: f403 7380 and.w r3, r3, #256 @ 0x100 800d4be: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d4c2: d106 bne.n 800d4d2 800d4c4: 6b7b ldr r3, [r7, #52] @ 0x34 800d4c6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d4ca: d102 bne.n 800d4d2 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800d4cc: 4b11 ldr r3, [pc, #68] @ (800d514 ) 800d4ce: 63fb str r3, [r7, #60] @ 0x3c 800d4d0: e011 b.n 800d4f6 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800d4d2: 4b0e ldr r3, [pc, #56] @ (800d50c ) 800d4d4: 681b ldr r3, [r3, #0] 800d4d6: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d4da: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d4de: d106 bne.n 800d4ee 800d4e0: 6b7b ldr r3, [r7, #52] @ 0x34 800d4e2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d4e6: d102 bne.n 800d4ee { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800d4e8: 4b0b ldr r3, [pc, #44] @ (800d518 ) 800d4ea: 63fb str r3, [r7, #60] @ 0x3c 800d4ec: e003 b.n 800d4f6 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800d4ee: 2300 movs r3, #0 800d4f0: 63fb str r3, [r7, #60] @ 0x3c } break; 800d4f2: f000 bc38 b.w 800dd66 800d4f6: f000 bc36 b.w 800dd66 } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 800d4fa: 4b08 ldr r3, [pc, #32] @ (800d51c ) 800d4fc: 63fb str r3, [r7, #60] @ 0x3c break; 800d4fe: f000 bc32 b.w 800dd66 } default : { frequency = 0; 800d502: 2300 movs r3, #0 800d504: 63fb str r3, [r7, #60] @ 0x3c break; 800d506: f000 bc2e b.w 800dd66 800d50a: bf00 nop 800d50c: 58024400 .word 0x58024400 800d510: 03d09000 .word 0x03d09000 800d514: 003d0900 .word 0x003d0900 800d518: 017d7840 .word 0x017d7840 800d51c: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 800d520: e9d7 2300 ldrd r2, r3, [r7] 800d524: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 800d528: 430b orrs r3, r1 800d52a: f040 809c bne.w 800d666 { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 800d52e: 4b9e ldr r3, [pc, #632] @ (800d7a8 ) 800d530: 6d9b ldr r3, [r3, #88] @ 0x58 800d532: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800d536: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800d538: 6b3b ldr r3, [r7, #48] @ 0x30 800d53a: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800d53e: d054 beq.n 800d5ea 800d540: 6b3b ldr r3, [r7, #48] @ 0x30 800d542: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800d546: f200 808b bhi.w 800d660 800d54a: 6b3b ldr r3, [r7, #48] @ 0x30 800d54c: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800d550: f000 8083 beq.w 800d65a 800d554: 6b3b ldr r3, [r7, #48] @ 0x30 800d556: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800d55a: f200 8081 bhi.w 800d660 800d55e: 6b3b ldr r3, [r7, #48] @ 0x30 800d560: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800d564: d02f beq.n 800d5c6 800d566: 6b3b ldr r3, [r7, #48] @ 0x30 800d568: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800d56c: d878 bhi.n 800d660 800d56e: 6b3b ldr r3, [r7, #48] @ 0x30 800d570: 2b00 cmp r3, #0 800d572: d004 beq.n 800d57e 800d574: 6b3b ldr r3, [r7, #48] @ 0x30 800d576: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800d57a: d012 beq.n 800d5a2 800d57c: e070 b.n 800d660 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800d57e: 4b8a ldr r3, [pc, #552] @ (800d7a8 ) 800d580: 681b ldr r3, [r3, #0] 800d582: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800d586: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800d58a: d107 bne.n 800d59c { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800d58c: f107 0324 add.w r3, r7, #36 @ 0x24 800d590: 4618 mov r0, r3 800d592: f000 feaf bl 800e2f4 frequency = pll1_clocks.PLL1_Q_Frequency; 800d596: 6abb ldr r3, [r7, #40] @ 0x28 800d598: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d59a: e3e4 b.n 800dd66 frequency = 0; 800d59c: 2300 movs r3, #0 800d59e: 63fb str r3, [r7, #60] @ 0x3c break; 800d5a0: e3e1 b.n 800dd66 } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800d5a2: 4b81 ldr r3, [pc, #516] @ (800d7a8 ) 800d5a4: 681b ldr r3, [r3, #0] 800d5a6: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800d5aa: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800d5ae: d107 bne.n 800d5c0 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d5b0: f107 0318 add.w r3, r7, #24 800d5b4: 4618 mov r0, r3 800d5b6: f000 fbf5 bl 800dda4 frequency = pll2_clocks.PLL2_P_Frequency; 800d5ba: 69bb ldr r3, [r7, #24] 800d5bc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d5be: e3d2 b.n 800dd66 frequency = 0; 800d5c0: 2300 movs r3, #0 800d5c2: 63fb str r3, [r7, #60] @ 0x3c break; 800d5c4: e3cf b.n 800dd66 } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800d5c6: 4b78 ldr r3, [pc, #480] @ (800d7a8 ) 800d5c8: 681b ldr r3, [r3, #0] 800d5ca: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800d5ce: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d5d2: d107 bne.n 800d5e4 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d5d4: f107 030c add.w r3, r7, #12 800d5d8: 4618 mov r0, r3 800d5da: f000 fd37 bl 800e04c frequency = pll3_clocks.PLL3_P_Frequency; 800d5de: 68fb ldr r3, [r7, #12] 800d5e0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d5e2: e3c0 b.n 800dd66 frequency = 0; 800d5e4: 2300 movs r3, #0 800d5e6: 63fb str r3, [r7, #60] @ 0x3c break; 800d5e8: e3bd b.n 800dd66 } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800d5ea: 4b6f ldr r3, [pc, #444] @ (800d7a8 ) 800d5ec: 6cdb ldr r3, [r3, #76] @ 0x4c 800d5ee: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800d5f2: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800d5f4: 4b6c ldr r3, [pc, #432] @ (800d7a8 ) 800d5f6: 681b ldr r3, [r3, #0] 800d5f8: f003 0304 and.w r3, r3, #4 800d5fc: 2b04 cmp r3, #4 800d5fe: d10c bne.n 800d61a 800d600: 6b7b ldr r3, [r7, #52] @ 0x34 800d602: 2b00 cmp r3, #0 800d604: d109 bne.n 800d61a { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d606: 4b68 ldr r3, [pc, #416] @ (800d7a8 ) 800d608: 681b ldr r3, [r3, #0] 800d60a: 08db lsrs r3, r3, #3 800d60c: f003 0303 and.w r3, r3, #3 800d610: 4a66 ldr r2, [pc, #408] @ (800d7ac ) 800d612: fa22 f303 lsr.w r3, r2, r3 800d616: 63fb str r3, [r7, #60] @ 0x3c 800d618: e01e b.n 800d658 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800d61a: 4b63 ldr r3, [pc, #396] @ (800d7a8 ) 800d61c: 681b ldr r3, [r3, #0] 800d61e: f403 7380 and.w r3, r3, #256 @ 0x100 800d622: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d626: d106 bne.n 800d636 800d628: 6b7b ldr r3, [r7, #52] @ 0x34 800d62a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d62e: d102 bne.n 800d636 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800d630: 4b5f ldr r3, [pc, #380] @ (800d7b0 ) 800d632: 63fb str r3, [r7, #60] @ 0x3c 800d634: e010 b.n 800d658 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800d636: 4b5c ldr r3, [pc, #368] @ (800d7a8 ) 800d638: 681b ldr r3, [r3, #0] 800d63a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d63e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d642: d106 bne.n 800d652 800d644: 6b7b ldr r3, [r7, #52] @ 0x34 800d646: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d64a: d102 bne.n 800d652 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800d64c: 4b59 ldr r3, [pc, #356] @ (800d7b4 ) 800d64e: 63fb str r3, [r7, #60] @ 0x3c 800d650: e002 b.n 800d658 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800d652: 2300 movs r3, #0 800d654: 63fb str r3, [r7, #60] @ 0x3c } break; 800d656: e386 b.n 800dd66 800d658: e385 b.n 800dd66 } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800d65a: 4b57 ldr r3, [pc, #348] @ (800d7b8 ) 800d65c: 63fb str r3, [r7, #60] @ 0x3c break; 800d65e: e382 b.n 800dd66 } default : { frequency = 0; 800d660: 2300 movs r3, #0 800d662: 63fb str r3, [r7, #60] @ 0x3c break; 800d664: e37f b.n 800dd66 } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800d666: e9d7 2300 ldrd r2, r3, [r7] 800d66a: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 800d66e: 430b orrs r3, r1 800d670: f040 80a7 bne.w 800d7c2 { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 800d674: 4b4c ldr r3, [pc, #304] @ (800d7a8 ) 800d676: 6d9b ldr r3, [r3, #88] @ 0x58 800d678: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 800d67c: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800d67e: 6b3b ldr r3, [r7, #48] @ 0x30 800d680: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800d684: d055 beq.n 800d732 800d686: 6b3b ldr r3, [r7, #48] @ 0x30 800d688: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800d68c: f200 8096 bhi.w 800d7bc 800d690: 6b3b ldr r3, [r7, #48] @ 0x30 800d692: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800d696: f000 8084 beq.w 800d7a2 800d69a: 6b3b ldr r3, [r7, #48] @ 0x30 800d69c: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800d6a0: f200 808c bhi.w 800d7bc 800d6a4: 6b3b ldr r3, [r7, #48] @ 0x30 800d6a6: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800d6aa: d030 beq.n 800d70e 800d6ac: 6b3b ldr r3, [r7, #48] @ 0x30 800d6ae: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800d6b2: f200 8083 bhi.w 800d7bc 800d6b6: 6b3b ldr r3, [r7, #48] @ 0x30 800d6b8: 2b00 cmp r3, #0 800d6ba: d004 beq.n 800d6c6 800d6bc: 6b3b ldr r3, [r7, #48] @ 0x30 800d6be: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800d6c2: d012 beq.n 800d6ea 800d6c4: e07a b.n 800d7bc { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800d6c6: 4b38 ldr r3, [pc, #224] @ (800d7a8 ) 800d6c8: 681b ldr r3, [r3, #0] 800d6ca: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800d6ce: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800d6d2: d107 bne.n 800d6e4 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800d6d4: f107 0324 add.w r3, r7, #36 @ 0x24 800d6d8: 4618 mov r0, r3 800d6da: f000 fe0b bl 800e2f4 frequency = pll1_clocks.PLL1_Q_Frequency; 800d6de: 6abb ldr r3, [r7, #40] @ 0x28 800d6e0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d6e2: e340 b.n 800dd66 frequency = 0; 800d6e4: 2300 movs r3, #0 800d6e6: 63fb str r3, [r7, #60] @ 0x3c break; 800d6e8: e33d b.n 800dd66 } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800d6ea: 4b2f ldr r3, [pc, #188] @ (800d7a8 ) 800d6ec: 681b ldr r3, [r3, #0] 800d6ee: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800d6f2: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800d6f6: d107 bne.n 800d708 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d6f8: f107 0318 add.w r3, r7, #24 800d6fc: 4618 mov r0, r3 800d6fe: f000 fb51 bl 800dda4 frequency = pll2_clocks.PLL2_P_Frequency; 800d702: 69bb ldr r3, [r7, #24] 800d704: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d706: e32e b.n 800dd66 frequency = 0; 800d708: 2300 movs r3, #0 800d70a: 63fb str r3, [r7, #60] @ 0x3c break; 800d70c: e32b b.n 800dd66 } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800d70e: 4b26 ldr r3, [pc, #152] @ (800d7a8 ) 800d710: 681b ldr r3, [r3, #0] 800d712: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800d716: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d71a: d107 bne.n 800d72c { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d71c: f107 030c add.w r3, r7, #12 800d720: 4618 mov r0, r3 800d722: f000 fc93 bl 800e04c frequency = pll3_clocks.PLL3_P_Frequency; 800d726: 68fb ldr r3, [r7, #12] 800d728: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d72a: e31c b.n 800dd66 frequency = 0; 800d72c: 2300 movs r3, #0 800d72e: 63fb str r3, [r7, #60] @ 0x3c break; 800d730: e319 b.n 800dd66 } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800d732: 4b1d ldr r3, [pc, #116] @ (800d7a8 ) 800d734: 6cdb ldr r3, [r3, #76] @ 0x4c 800d736: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800d73a: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800d73c: 4b1a ldr r3, [pc, #104] @ (800d7a8 ) 800d73e: 681b ldr r3, [r3, #0] 800d740: f003 0304 and.w r3, r3, #4 800d744: 2b04 cmp r3, #4 800d746: d10c bne.n 800d762 800d748: 6b7b ldr r3, [r7, #52] @ 0x34 800d74a: 2b00 cmp r3, #0 800d74c: d109 bne.n 800d762 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d74e: 4b16 ldr r3, [pc, #88] @ (800d7a8 ) 800d750: 681b ldr r3, [r3, #0] 800d752: 08db lsrs r3, r3, #3 800d754: f003 0303 and.w r3, r3, #3 800d758: 4a14 ldr r2, [pc, #80] @ (800d7ac ) 800d75a: fa22 f303 lsr.w r3, r2, r3 800d75e: 63fb str r3, [r7, #60] @ 0x3c 800d760: e01e b.n 800d7a0 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800d762: 4b11 ldr r3, [pc, #68] @ (800d7a8 ) 800d764: 681b ldr r3, [r3, #0] 800d766: f403 7380 and.w r3, r3, #256 @ 0x100 800d76a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d76e: d106 bne.n 800d77e 800d770: 6b7b ldr r3, [r7, #52] @ 0x34 800d772: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d776: d102 bne.n 800d77e { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800d778: 4b0d ldr r3, [pc, #52] @ (800d7b0 ) 800d77a: 63fb str r3, [r7, #60] @ 0x3c 800d77c: e010 b.n 800d7a0 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800d77e: 4b0a ldr r3, [pc, #40] @ (800d7a8 ) 800d780: 681b ldr r3, [r3, #0] 800d782: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d786: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d78a: d106 bne.n 800d79a 800d78c: 6b7b ldr r3, [r7, #52] @ 0x34 800d78e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d792: d102 bne.n 800d79a { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800d794: 4b07 ldr r3, [pc, #28] @ (800d7b4 ) 800d796: 63fb str r3, [r7, #60] @ 0x3c 800d798: e002 b.n 800d7a0 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800d79a: 2300 movs r3, #0 800d79c: 63fb str r3, [r7, #60] @ 0x3c } break; 800d79e: e2e2 b.n 800dd66 800d7a0: e2e1 b.n 800dd66 } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 800d7a2: 4b05 ldr r3, [pc, #20] @ (800d7b8 ) 800d7a4: 63fb str r3, [r7, #60] @ 0x3c break; 800d7a6: e2de b.n 800dd66 800d7a8: 58024400 .word 0x58024400 800d7ac: 03d09000 .word 0x03d09000 800d7b0: 003d0900 .word 0x003d0900 800d7b4: 017d7840 .word 0x017d7840 800d7b8: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 800d7bc: 2300 movs r3, #0 800d7be: 63fb str r3, [r7, #60] @ 0x3c break; 800d7c0: e2d1 b.n 800dd66 } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800d7c2: e9d7 2300 ldrd r2, r3, [r7] 800d7c6: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800d7ca: 430b orrs r3, r1 800d7cc: f040 809c bne.w 800d908 { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800d7d0: 4b93 ldr r3, [pc, #588] @ (800da20 ) 800d7d2: 6d1b ldr r3, [r3, #80] @ 0x50 800d7d4: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800d7d8: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800d7da: 6bbb ldr r3, [r7, #56] @ 0x38 800d7dc: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d7e0: d054 beq.n 800d88c 800d7e2: 6bbb ldr r3, [r7, #56] @ 0x38 800d7e4: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d7e8: f200 808b bhi.w 800d902 800d7ec: 6bbb ldr r3, [r7, #56] @ 0x38 800d7ee: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800d7f2: f000 8083 beq.w 800d8fc 800d7f6: 6bbb ldr r3, [r7, #56] @ 0x38 800d7f8: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800d7fc: f200 8081 bhi.w 800d902 800d800: 6bbb ldr r3, [r7, #56] @ 0x38 800d802: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d806: d02f beq.n 800d868 800d808: 6bbb ldr r3, [r7, #56] @ 0x38 800d80a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d80e: d878 bhi.n 800d902 800d810: 6bbb ldr r3, [r7, #56] @ 0x38 800d812: 2b00 cmp r3, #0 800d814: d004 beq.n 800d820 800d816: 6bbb ldr r3, [r7, #56] @ 0x38 800d818: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d81c: d012 beq.n 800d844 800d81e: e070 b.n 800d902 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800d820: 4b7f ldr r3, [pc, #508] @ (800da20 ) 800d822: 681b ldr r3, [r3, #0] 800d824: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800d828: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800d82c: d107 bne.n 800d83e { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800d82e: f107 0324 add.w r3, r7, #36 @ 0x24 800d832: 4618 mov r0, r3 800d834: f000 fd5e bl 800e2f4 frequency = pll1_clocks.PLL1_Q_Frequency; 800d838: 6abb ldr r3, [r7, #40] @ 0x28 800d83a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d83c: e293 b.n 800dd66 frequency = 0; 800d83e: 2300 movs r3, #0 800d840: 63fb str r3, [r7, #60] @ 0x3c break; 800d842: e290 b.n 800dd66 } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800d844: 4b76 ldr r3, [pc, #472] @ (800da20 ) 800d846: 681b ldr r3, [r3, #0] 800d848: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800d84c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800d850: d107 bne.n 800d862 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d852: f107 0318 add.w r3, r7, #24 800d856: 4618 mov r0, r3 800d858: f000 faa4 bl 800dda4 frequency = pll2_clocks.PLL2_P_Frequency; 800d85c: 69bb ldr r3, [r7, #24] 800d85e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d860: e281 b.n 800dd66 frequency = 0; 800d862: 2300 movs r3, #0 800d864: 63fb str r3, [r7, #60] @ 0x3c break; 800d866: e27e b.n 800dd66 } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800d868: 4b6d ldr r3, [pc, #436] @ (800da20 ) 800d86a: 681b ldr r3, [r3, #0] 800d86c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800d870: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d874: d107 bne.n 800d886 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d876: f107 030c add.w r3, r7, #12 800d87a: 4618 mov r0, r3 800d87c: f000 fbe6 bl 800e04c frequency = pll3_clocks.PLL3_P_Frequency; 800d880: 68fb ldr r3, [r7, #12] 800d882: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d884: e26f b.n 800dd66 frequency = 0; 800d886: 2300 movs r3, #0 800d888: 63fb str r3, [r7, #60] @ 0x3c break; 800d88a: e26c b.n 800dd66 } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800d88c: 4b64 ldr r3, [pc, #400] @ (800da20 ) 800d88e: 6cdb ldr r3, [r3, #76] @ 0x4c 800d890: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800d894: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800d896: 4b62 ldr r3, [pc, #392] @ (800da20 ) 800d898: 681b ldr r3, [r3, #0] 800d89a: f003 0304 and.w r3, r3, #4 800d89e: 2b04 cmp r3, #4 800d8a0: d10c bne.n 800d8bc 800d8a2: 6b7b ldr r3, [r7, #52] @ 0x34 800d8a4: 2b00 cmp r3, #0 800d8a6: d109 bne.n 800d8bc { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d8a8: 4b5d ldr r3, [pc, #372] @ (800da20 ) 800d8aa: 681b ldr r3, [r3, #0] 800d8ac: 08db lsrs r3, r3, #3 800d8ae: f003 0303 and.w r3, r3, #3 800d8b2: 4a5c ldr r2, [pc, #368] @ (800da24 ) 800d8b4: fa22 f303 lsr.w r3, r2, r3 800d8b8: 63fb str r3, [r7, #60] @ 0x3c 800d8ba: e01e b.n 800d8fa } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800d8bc: 4b58 ldr r3, [pc, #352] @ (800da20 ) 800d8be: 681b ldr r3, [r3, #0] 800d8c0: f403 7380 and.w r3, r3, #256 @ 0x100 800d8c4: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d8c8: d106 bne.n 800d8d8 800d8ca: 6b7b ldr r3, [r7, #52] @ 0x34 800d8cc: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d8d0: d102 bne.n 800d8d8 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800d8d2: 4b55 ldr r3, [pc, #340] @ (800da28 ) 800d8d4: 63fb str r3, [r7, #60] @ 0x3c 800d8d6: e010 b.n 800d8fa } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800d8d8: 4b51 ldr r3, [pc, #324] @ (800da20 ) 800d8da: 681b ldr r3, [r3, #0] 800d8dc: f403 3300 and.w r3, r3, #131072 @ 0x20000 800d8e0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d8e4: d106 bne.n 800d8f4 800d8e6: 6b7b ldr r3, [r7, #52] @ 0x34 800d8e8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d8ec: d102 bne.n 800d8f4 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800d8ee: 4b4f ldr r3, [pc, #316] @ (800da2c ) 800d8f0: 63fb str r3, [r7, #60] @ 0x3c 800d8f2: e002 b.n 800d8fa } else { /* In Case the CKPER is disabled*/ frequency = 0; 800d8f4: 2300 movs r3, #0 800d8f6: 63fb str r3, [r7, #60] @ 0x3c } break; 800d8f8: e235 b.n 800dd66 800d8fa: e234 b.n 800dd66 } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800d8fc: 4b4c ldr r3, [pc, #304] @ (800da30 ) 800d8fe: 63fb str r3, [r7, #60] @ 0x3c break; 800d900: e231 b.n 800dd66 } default : { frequency = 0; 800d902: 2300 movs r3, #0 800d904: 63fb str r3, [r7, #60] @ 0x3c break; 800d906: e22e b.n 800dd66 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800d908: e9d7 2300 ldrd r2, r3, [r7] 800d90c: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 800d910: 430b orrs r3, r1 800d912: f040 808f bne.w 800da34 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800d916: 4b42 ldr r3, [pc, #264] @ (800da20 ) 800d918: 6d1b ldr r3, [r3, #80] @ 0x50 800d91a: f403 23e0 and.w r3, r3, #458752 @ 0x70000 800d91e: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800d920: 6bbb ldr r3, [r7, #56] @ 0x38 800d922: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800d926: d06b beq.n 800da00 800d928: 6bbb ldr r3, [r7, #56] @ 0x38 800d92a: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800d92e: d874 bhi.n 800da1a 800d930: 6bbb ldr r3, [r7, #56] @ 0x38 800d932: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800d936: d056 beq.n 800d9e6 800d938: 6bbb ldr r3, [r7, #56] @ 0x38 800d93a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800d93e: d86c bhi.n 800da1a 800d940: 6bbb ldr r3, [r7, #56] @ 0x38 800d942: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800d946: d03b beq.n 800d9c0 800d948: 6bbb ldr r3, [r7, #56] @ 0x38 800d94a: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800d94e: d864 bhi.n 800da1a 800d950: 6bbb ldr r3, [r7, #56] @ 0x38 800d952: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d956: d021 beq.n 800d99c 800d958: 6bbb ldr r3, [r7, #56] @ 0x38 800d95a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d95e: d85c bhi.n 800da1a 800d960: 6bbb ldr r3, [r7, #56] @ 0x38 800d962: 2b00 cmp r3, #0 800d964: d004 beq.n 800d970 800d966: 6bbb ldr r3, [r7, #56] @ 0x38 800d968: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d96c: d004 beq.n 800d978 800d96e: e054 b.n 800da1a { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 800d970: f7fe fa26 bl 800bdc0 800d974: 63f8 str r0, [r7, #60] @ 0x3c break; 800d976: e1f6 b.n 800dd66 } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800d978: 4b29 ldr r3, [pc, #164] @ (800da20 ) 800d97a: 681b ldr r3, [r3, #0] 800d97c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800d980: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800d984: d107 bne.n 800d996 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800d986: f107 0318 add.w r3, r7, #24 800d98a: 4618 mov r0, r3 800d98c: f000 fa0a bl 800dda4 frequency = pll2_clocks.PLL2_Q_Frequency; 800d990: 69fb ldr r3, [r7, #28] 800d992: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d994: e1e7 b.n 800dd66 frequency = 0; 800d996: 2300 movs r3, #0 800d998: 63fb str r3, [r7, #60] @ 0x3c break; 800d99a: e1e4 b.n 800dd66 } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800d99c: 4b20 ldr r3, [pc, #128] @ (800da20 ) 800d99e: 681b ldr r3, [r3, #0] 800d9a0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800d9a4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d9a8: d107 bne.n 800d9ba { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800d9aa: f107 030c add.w r3, r7, #12 800d9ae: 4618 mov r0, r3 800d9b0: f000 fb4c bl 800e04c frequency = pll3_clocks.PLL3_Q_Frequency; 800d9b4: 693b ldr r3, [r7, #16] 800d9b6: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d9b8: e1d5 b.n 800dd66 frequency = 0; 800d9ba: 2300 movs r3, #0 800d9bc: 63fb str r3, [r7, #60] @ 0x3c break; 800d9be: e1d2 b.n 800dd66 } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800d9c0: 4b17 ldr r3, [pc, #92] @ (800da20 ) 800d9c2: 681b ldr r3, [r3, #0] 800d9c4: f003 0304 and.w r3, r3, #4 800d9c8: 2b04 cmp r3, #4 800d9ca: d109 bne.n 800d9e0 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800d9cc: 4b14 ldr r3, [pc, #80] @ (800da20 ) 800d9ce: 681b ldr r3, [r3, #0] 800d9d0: 08db lsrs r3, r3, #3 800d9d2: f003 0303 and.w r3, r3, #3 800d9d6: 4a13 ldr r2, [pc, #76] @ (800da24 ) 800d9d8: fa22 f303 lsr.w r3, r2, r3 800d9dc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d9de: e1c2 b.n 800dd66 frequency = 0; 800d9e0: 2300 movs r3, #0 800d9e2: 63fb str r3, [r7, #60] @ 0x3c break; 800d9e4: e1bf b.n 800dd66 } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800d9e6: 4b0e ldr r3, [pc, #56] @ (800da20 ) 800d9e8: 681b ldr r3, [r3, #0] 800d9ea: f403 7380 and.w r3, r3, #256 @ 0x100 800d9ee: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d9f2: d102 bne.n 800d9fa { frequency = CSI_VALUE; 800d9f4: 4b0c ldr r3, [pc, #48] @ (800da28 ) 800d9f6: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800d9f8: e1b5 b.n 800dd66 frequency = 0; 800d9fa: 2300 movs r3, #0 800d9fc: 63fb str r3, [r7, #60] @ 0x3c break; 800d9fe: e1b2 b.n 800dd66 } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800da00: 4b07 ldr r3, [pc, #28] @ (800da20 ) 800da02: 681b ldr r3, [r3, #0] 800da04: f403 3300 and.w r3, r3, #131072 @ 0x20000 800da08: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800da0c: d102 bne.n 800da14 { frequency = HSE_VALUE; 800da0e: 4b07 ldr r3, [pc, #28] @ (800da2c ) 800da10: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800da12: e1a8 b.n 800dd66 frequency = 0; 800da14: 2300 movs r3, #0 800da16: 63fb str r3, [r7, #60] @ 0x3c break; 800da18: e1a5 b.n 800dd66 } default : { frequency = 0; 800da1a: 2300 movs r3, #0 800da1c: 63fb str r3, [r7, #60] @ 0x3c break; 800da1e: e1a2 b.n 800dd66 800da20: 58024400 .word 0x58024400 800da24: 03d09000 .word 0x03d09000 800da28: 003d0900 .word 0x003d0900 800da2c: 017d7840 .word 0x017d7840 800da30: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 800da34: e9d7 2300 ldrd r2, r3, [r7] 800da38: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 800da3c: 430b orrs r3, r1 800da3e: d173 bne.n 800db28 { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 800da40: 4b9c ldr r3, [pc, #624] @ (800dcb4 ) 800da42: 6d9b ldr r3, [r3, #88] @ 0x58 800da44: f403 3340 and.w r3, r3, #196608 @ 0x30000 800da48: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800da4a: 6bbb ldr r3, [r7, #56] @ 0x38 800da4c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800da50: d02f beq.n 800dab2 800da52: 6bbb ldr r3, [r7, #56] @ 0x38 800da54: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800da58: d863 bhi.n 800db22 800da5a: 6bbb ldr r3, [r7, #56] @ 0x38 800da5c: 2b00 cmp r3, #0 800da5e: d004 beq.n 800da6a 800da60: 6bbb ldr r3, [r7, #56] @ 0x38 800da62: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800da66: d012 beq.n 800da8e 800da68: e05b b.n 800db22 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800da6a: 4b92 ldr r3, [pc, #584] @ (800dcb4 ) 800da6c: 681b ldr r3, [r3, #0] 800da6e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800da72: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800da76: d107 bne.n 800da88 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800da78: f107 0318 add.w r3, r7, #24 800da7c: 4618 mov r0, r3 800da7e: f000 f991 bl 800dda4 frequency = pll2_clocks.PLL2_P_Frequency; 800da82: 69bb ldr r3, [r7, #24] 800da84: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800da86: e16e b.n 800dd66 frequency = 0; 800da88: 2300 movs r3, #0 800da8a: 63fb str r3, [r7, #60] @ 0x3c break; 800da8c: e16b b.n 800dd66 } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800da8e: 4b89 ldr r3, [pc, #548] @ (800dcb4 ) 800da90: 681b ldr r3, [r3, #0] 800da92: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800da96: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800da9a: d107 bne.n 800daac { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800da9c: f107 030c add.w r3, r7, #12 800daa0: 4618 mov r0, r3 800daa2: f000 fad3 bl 800e04c frequency = pll3_clocks.PLL3_R_Frequency; 800daa6: 697b ldr r3, [r7, #20] 800daa8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800daaa: e15c b.n 800dd66 frequency = 0; 800daac: 2300 movs r3, #0 800daae: 63fb str r3, [r7, #60] @ 0x3c break; 800dab0: e159 b.n 800dd66 } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800dab2: 4b80 ldr r3, [pc, #512] @ (800dcb4 ) 800dab4: 6cdb ldr r3, [r3, #76] @ 0x4c 800dab6: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800daba: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800dabc: 4b7d ldr r3, [pc, #500] @ (800dcb4 ) 800dabe: 681b ldr r3, [r3, #0] 800dac0: f003 0304 and.w r3, r3, #4 800dac4: 2b04 cmp r3, #4 800dac6: d10c bne.n 800dae2 800dac8: 6b7b ldr r3, [r7, #52] @ 0x34 800daca: 2b00 cmp r3, #0 800dacc: d109 bne.n 800dae2 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800dace: 4b79 ldr r3, [pc, #484] @ (800dcb4 ) 800dad0: 681b ldr r3, [r3, #0] 800dad2: 08db lsrs r3, r3, #3 800dad4: f003 0303 and.w r3, r3, #3 800dad8: 4a77 ldr r2, [pc, #476] @ (800dcb8 ) 800dada: fa22 f303 lsr.w r3, r2, r3 800dade: 63fb str r3, [r7, #60] @ 0x3c 800dae0: e01e b.n 800db20 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dae2: 4b74 ldr r3, [pc, #464] @ (800dcb4 ) 800dae4: 681b ldr r3, [r3, #0] 800dae6: f403 7380 and.w r3, r3, #256 @ 0x100 800daea: f5b3 7f80 cmp.w r3, #256 @ 0x100 800daee: d106 bne.n 800dafe 800daf0: 6b7b ldr r3, [r7, #52] @ 0x34 800daf2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800daf6: d102 bne.n 800dafe { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800daf8: 4b70 ldr r3, [pc, #448] @ (800dcbc ) 800dafa: 63fb str r3, [r7, #60] @ 0x3c 800dafc: e010 b.n 800db20 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dafe: 4b6d ldr r3, [pc, #436] @ (800dcb4 ) 800db00: 681b ldr r3, [r3, #0] 800db02: f403 3300 and.w r3, r3, #131072 @ 0x20000 800db06: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800db0a: d106 bne.n 800db1a 800db0c: 6b7b ldr r3, [r7, #52] @ 0x34 800db0e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800db12: d102 bne.n 800db1a { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800db14: 4b6a ldr r3, [pc, #424] @ (800dcc0 ) 800db16: 63fb str r3, [r7, #60] @ 0x3c 800db18: e002 b.n 800db20 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800db1a: 2300 movs r3, #0 800db1c: 63fb str r3, [r7, #60] @ 0x3c } break; 800db1e: e122 b.n 800dd66 800db20: e121 b.n 800dd66 } default : { frequency = 0; 800db22: 2300 movs r3, #0 800db24: 63fb str r3, [r7, #60] @ 0x3c break; 800db26: e11e b.n 800dd66 } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 800db28: e9d7 2300 ldrd r2, r3, [r7] 800db2c: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 800db30: 430b orrs r3, r1 800db32: d133 bne.n 800db9c { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 800db34: 4b5f ldr r3, [pc, #380] @ (800dcb4 ) 800db36: 6cdb ldr r3, [r3, #76] @ 0x4c 800db38: f403 3380 and.w r3, r3, #65536 @ 0x10000 800db3c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800db3e: 6bbb ldr r3, [r7, #56] @ 0x38 800db40: 2b00 cmp r3, #0 800db42: d004 beq.n 800db4e 800db44: 6bbb ldr r3, [r7, #56] @ 0x38 800db46: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800db4a: d012 beq.n 800db72 800db4c: e023 b.n 800db96 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800db4e: 4b59 ldr r3, [pc, #356] @ (800dcb4 ) 800db50: 681b ldr r3, [r3, #0] 800db52: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800db56: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800db5a: d107 bne.n 800db6c { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800db5c: f107 0324 add.w r3, r7, #36 @ 0x24 800db60: 4618 mov r0, r3 800db62: f000 fbc7 bl 800e2f4 frequency = pll1_clocks.PLL1_Q_Frequency; 800db66: 6abb ldr r3, [r7, #40] @ 0x28 800db68: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800db6a: e0fc b.n 800dd66 frequency = 0; 800db6c: 2300 movs r3, #0 800db6e: 63fb str r3, [r7, #60] @ 0x3c break; 800db70: e0f9 b.n 800dd66 } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800db72: 4b50 ldr r3, [pc, #320] @ (800dcb4 ) 800db74: 681b ldr r3, [r3, #0] 800db76: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800db7a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800db7e: d107 bne.n 800db90 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800db80: f107 0318 add.w r3, r7, #24 800db84: 4618 mov r0, r3 800db86: f000 f90d bl 800dda4 frequency = pll2_clocks.PLL2_R_Frequency; 800db8a: 6a3b ldr r3, [r7, #32] 800db8c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800db8e: e0ea b.n 800dd66 frequency = 0; 800db90: 2300 movs r3, #0 800db92: 63fb str r3, [r7, #60] @ 0x3c break; 800db94: e0e7 b.n 800dd66 } default : { frequency = 0; 800db96: 2300 movs r3, #0 800db98: 63fb str r3, [r7, #60] @ 0x3c break; 800db9a: e0e4 b.n 800dd66 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800db9c: e9d7 2300 ldrd r2, r3, [r7] 800dba0: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 800dba4: 430b orrs r3, r1 800dba6: f040 808d bne.w 800dcc4 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800dbaa: 4b42 ldr r3, [pc, #264] @ (800dcb4 ) 800dbac: 6d9b ldr r3, [r3, #88] @ 0x58 800dbae: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 800dbb2: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800dbb4: 6bbb ldr r3, [r7, #56] @ 0x38 800dbb6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800dbba: d06b beq.n 800dc94 800dbbc: 6bbb ldr r3, [r7, #56] @ 0x38 800dbbe: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800dbc2: d874 bhi.n 800dcae 800dbc4: 6bbb ldr r3, [r7, #56] @ 0x38 800dbc6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800dbca: d056 beq.n 800dc7a 800dbcc: 6bbb ldr r3, [r7, #56] @ 0x38 800dbce: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800dbd2: d86c bhi.n 800dcae 800dbd4: 6bbb ldr r3, [r7, #56] @ 0x38 800dbd6: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800dbda: d03b beq.n 800dc54 800dbdc: 6bbb ldr r3, [r7, #56] @ 0x38 800dbde: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800dbe2: d864 bhi.n 800dcae 800dbe4: 6bbb ldr r3, [r7, #56] @ 0x38 800dbe6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dbea: d021 beq.n 800dc30 800dbec: 6bbb ldr r3, [r7, #56] @ 0x38 800dbee: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dbf2: d85c bhi.n 800dcae 800dbf4: 6bbb ldr r3, [r7, #56] @ 0x38 800dbf6: 2b00 cmp r3, #0 800dbf8: d004 beq.n 800dc04 800dbfa: 6bbb ldr r3, [r7, #56] @ 0x38 800dbfc: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dc00: d004 beq.n 800dc0c 800dc02: e054 b.n 800dcae { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800dc04: f000 f8b8 bl 800dd78 800dc08: 63f8 str r0, [r7, #60] @ 0x3c break; 800dc0a: e0ac b.n 800dd66 } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dc0c: 4b29 ldr r3, [pc, #164] @ (800dcb4 ) 800dc0e: 681b ldr r3, [r3, #0] 800dc10: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dc14: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dc18: d107 bne.n 800dc2a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dc1a: f107 0318 add.w r3, r7, #24 800dc1e: 4618 mov r0, r3 800dc20: f000 f8c0 bl 800dda4 frequency = pll2_clocks.PLL2_Q_Frequency; 800dc24: 69fb ldr r3, [r7, #28] 800dc26: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dc28: e09d b.n 800dd66 frequency = 0; 800dc2a: 2300 movs r3, #0 800dc2c: 63fb str r3, [r7, #60] @ 0x3c break; 800dc2e: e09a b.n 800dd66 } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800dc30: 4b20 ldr r3, [pc, #128] @ (800dcb4 ) 800dc32: 681b ldr r3, [r3, #0] 800dc34: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800dc38: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dc3c: d107 bne.n 800dc4e { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800dc3e: f107 030c add.w r3, r7, #12 800dc42: 4618 mov r0, r3 800dc44: f000 fa02 bl 800e04c frequency = pll3_clocks.PLL3_Q_Frequency; 800dc48: 693b ldr r3, [r7, #16] 800dc4a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dc4c: e08b b.n 800dd66 frequency = 0; 800dc4e: 2300 movs r3, #0 800dc50: 63fb str r3, [r7, #60] @ 0x3c break; 800dc52: e088 b.n 800dd66 } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800dc54: 4b17 ldr r3, [pc, #92] @ (800dcb4 ) 800dc56: 681b ldr r3, [r3, #0] 800dc58: f003 0304 and.w r3, r3, #4 800dc5c: 2b04 cmp r3, #4 800dc5e: d109 bne.n 800dc74 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800dc60: 4b14 ldr r3, [pc, #80] @ (800dcb4 ) 800dc62: 681b ldr r3, [r3, #0] 800dc64: 08db lsrs r3, r3, #3 800dc66: f003 0303 and.w r3, r3, #3 800dc6a: 4a13 ldr r2, [pc, #76] @ (800dcb8 ) 800dc6c: fa22 f303 lsr.w r3, r2, r3 800dc70: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dc72: e078 b.n 800dd66 frequency = 0; 800dc74: 2300 movs r3, #0 800dc76: 63fb str r3, [r7, #60] @ 0x3c break; 800dc78: e075 b.n 800dd66 } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800dc7a: 4b0e ldr r3, [pc, #56] @ (800dcb4 ) 800dc7c: 681b ldr r3, [r3, #0] 800dc7e: f403 7380 and.w r3, r3, #256 @ 0x100 800dc82: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dc86: d102 bne.n 800dc8e { frequency = CSI_VALUE; 800dc88: 4b0c ldr r3, [pc, #48] @ (800dcbc ) 800dc8a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dc8c: e06b b.n 800dd66 frequency = 0; 800dc8e: 2300 movs r3, #0 800dc90: 63fb str r3, [r7, #60] @ 0x3c break; 800dc92: e068 b.n 800dd66 } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800dc94: 4b07 ldr r3, [pc, #28] @ (800dcb4 ) 800dc96: 681b ldr r3, [r3, #0] 800dc98: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dc9c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800dca0: d102 bne.n 800dca8 { frequency = HSE_VALUE; 800dca2: 4b07 ldr r3, [pc, #28] @ (800dcc0 ) 800dca4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dca6: e05e b.n 800dd66 frequency = 0; 800dca8: 2300 movs r3, #0 800dcaa: 63fb str r3, [r7, #60] @ 0x3c break; 800dcac: e05b b.n 800dd66 break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 800dcae: 2300 movs r3, #0 800dcb0: 63fb str r3, [r7, #60] @ 0x3c break; 800dcb2: e058 b.n 800dd66 800dcb4: 58024400 .word 0x58024400 800dcb8: 03d09000 .word 0x03d09000 800dcbc: 003d0900 .word 0x003d0900 800dcc0: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800dcc4: e9d7 2300 ldrd r2, r3, [r7] 800dcc8: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 800dccc: 430b orrs r3, r1 800dcce: d148 bne.n 800dd62 { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800dcd0: 4b27 ldr r3, [pc, #156] @ (800dd70 ) 800dcd2: 6d1b ldr r3, [r3, #80] @ 0x50 800dcd4: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800dcd8: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800dcda: 6bbb ldr r3, [r7, #56] @ 0x38 800dcdc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dce0: d02a beq.n 800dd38 800dce2: 6bbb ldr r3, [r7, #56] @ 0x38 800dce4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dce8: d838 bhi.n 800dd5c 800dcea: 6bbb ldr r3, [r7, #56] @ 0x38 800dcec: 2b00 cmp r3, #0 800dcee: d004 beq.n 800dcfa 800dcf0: 6bbb ldr r3, [r7, #56] @ 0x38 800dcf2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dcf6: d00d beq.n 800dd14 800dcf8: e030 b.n 800dd5c { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800dcfa: 4b1d ldr r3, [pc, #116] @ (800dd70 ) 800dcfc: 681b ldr r3, [r3, #0] 800dcfe: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dd02: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800dd06: d102 bne.n 800dd0e { frequency = HSE_VALUE; 800dd08: 4b1a ldr r3, [pc, #104] @ (800dd74 ) 800dd0a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dd0c: e02b b.n 800dd66 frequency = 0; 800dd0e: 2300 movs r3, #0 800dd10: 63fb str r3, [r7, #60] @ 0x3c break; 800dd12: e028 b.n 800dd66 } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800dd14: 4b16 ldr r3, [pc, #88] @ (800dd70 ) 800dd16: 681b ldr r3, [r3, #0] 800dd18: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800dd1c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800dd20: d107 bne.n 800dd32 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800dd22: f107 0324 add.w r3, r7, #36 @ 0x24 800dd26: 4618 mov r0, r3 800dd28: f000 fae4 bl 800e2f4 frequency = pll1_clocks.PLL1_Q_Frequency; 800dd2c: 6abb ldr r3, [r7, #40] @ 0x28 800dd2e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dd30: e019 b.n 800dd66 frequency = 0; 800dd32: 2300 movs r3, #0 800dd34: 63fb str r3, [r7, #60] @ 0x3c break; 800dd36: e016 b.n 800dd66 } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dd38: 4b0d ldr r3, [pc, #52] @ (800dd70 ) 800dd3a: 681b ldr r3, [r3, #0] 800dd3c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dd40: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800dd44: d107 bne.n 800dd56 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800dd46: f107 0318 add.w r3, r7, #24 800dd4a: 4618 mov r0, r3 800dd4c: f000 f82a bl 800dda4 frequency = pll2_clocks.PLL2_Q_Frequency; 800dd50: 69fb ldr r3, [r7, #28] 800dd52: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dd54: e007 b.n 800dd66 frequency = 0; 800dd56: 2300 movs r3, #0 800dd58: 63fb str r3, [r7, #60] @ 0x3c break; 800dd5a: e004 b.n 800dd66 } default : { frequency = 0; 800dd5c: 2300 movs r3, #0 800dd5e: 63fb str r3, [r7, #60] @ 0x3c break; 800dd60: e001 b.n 800dd66 } } } else { frequency = 0; 800dd62: 2300 movs r3, #0 800dd64: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 800dd66: 6bfb ldr r3, [r7, #60] @ 0x3c } 800dd68: 4618 mov r0, r3 800dd6a: 3740 adds r7, #64 @ 0x40 800dd6c: 46bd mov sp, r7 800dd6e: bd80 pop {r7, pc} 800dd70: 58024400 .word 0x58024400 800dd74: 017d7840 .word 0x017d7840 0800dd78 : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 800dd78: b580 push {r7, lr} 800dd7a: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800dd7c: f7fd fff0 bl 800bd60 800dd80: 4602 mov r2, r0 800dd82: 4b06 ldr r3, [pc, #24] @ (800dd9c ) 800dd84: 6a1b ldr r3, [r3, #32] 800dd86: 091b lsrs r3, r3, #4 800dd88: f003 0307 and.w r3, r3, #7 800dd8c: 4904 ldr r1, [pc, #16] @ (800dda0 ) 800dd8e: 5ccb ldrb r3, [r1, r3] 800dd90: f003 031f and.w r3, r3, #31 800dd94: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 800dd98: 4618 mov r0, r3 800dd9a: bd80 pop {r7, pc} 800dd9c: 58024400 .word 0x58024400 800dda0: 080189c8 .word 0x080189c8 0800dda4 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 800dda4: b480 push {r7} 800dda6: b089 sub sp, #36 @ 0x24 800dda8: af00 add r7, sp, #0 800ddaa: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800ddac: 4ba1 ldr r3, [pc, #644] @ (800e034 ) 800ddae: 6a9b ldr r3, [r3, #40] @ 0x28 800ddb0: f003 0303 and.w r3, r3, #3 800ddb4: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 800ddb6: 4b9f ldr r3, [pc, #636] @ (800e034 ) 800ddb8: 6a9b ldr r3, [r3, #40] @ 0x28 800ddba: 0b1b lsrs r3, r3, #12 800ddbc: f003 033f and.w r3, r3, #63 @ 0x3f 800ddc0: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 800ddc2: 4b9c ldr r3, [pc, #624] @ (800e034 ) 800ddc4: 6adb ldr r3, [r3, #44] @ 0x2c 800ddc6: 091b lsrs r3, r3, #4 800ddc8: f003 0301 and.w r3, r3, #1 800ddcc: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 800ddce: 4b99 ldr r3, [pc, #612] @ (800e034 ) 800ddd0: 6bdb ldr r3, [r3, #60] @ 0x3c 800ddd2: 08db lsrs r3, r3, #3 800ddd4: f3c3 030c ubfx r3, r3, #0, #13 800ddd8: 693a ldr r2, [r7, #16] 800ddda: fb02 f303 mul.w r3, r2, r3 800ddde: ee07 3a90 vmov s15, r3 800dde2: eef8 7a67 vcvt.f32.u32 s15, s15 800dde6: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 800ddea: 697b ldr r3, [r7, #20] 800ddec: 2b00 cmp r3, #0 800ddee: f000 8111 beq.w 800e014 { switch (pllsource) 800ddf2: 69bb ldr r3, [r7, #24] 800ddf4: 2b02 cmp r3, #2 800ddf6: f000 8083 beq.w 800df00 800ddfa: 69bb ldr r3, [r7, #24] 800ddfc: 2b02 cmp r3, #2 800ddfe: f200 80a1 bhi.w 800df44 800de02: 69bb ldr r3, [r7, #24] 800de04: 2b00 cmp r3, #0 800de06: d003 beq.n 800de10 800de08: 69bb ldr r3, [r7, #24] 800de0a: 2b01 cmp r3, #1 800de0c: d056 beq.n 800debc 800de0e: e099 b.n 800df44 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800de10: 4b88 ldr r3, [pc, #544] @ (800e034 ) 800de12: 681b ldr r3, [r3, #0] 800de14: f003 0320 and.w r3, r3, #32 800de18: 2b00 cmp r3, #0 800de1a: d02d beq.n 800de78 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800de1c: 4b85 ldr r3, [pc, #532] @ (800e034 ) 800de1e: 681b ldr r3, [r3, #0] 800de20: 08db lsrs r3, r3, #3 800de22: f003 0303 and.w r3, r3, #3 800de26: 4a84 ldr r2, [pc, #528] @ (800e038 ) 800de28: fa22 f303 lsr.w r3, r2, r3 800de2c: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800de2e: 68bb ldr r3, [r7, #8] 800de30: ee07 3a90 vmov s15, r3 800de34: eef8 6a67 vcvt.f32.u32 s13, s15 800de38: 697b ldr r3, [r7, #20] 800de3a: ee07 3a90 vmov s15, r3 800de3e: eef8 7a67 vcvt.f32.u32 s15, s15 800de42: ee86 7aa7 vdiv.f32 s14, s13, s15 800de46: 4b7b ldr r3, [pc, #492] @ (800e034 ) 800de48: 6b9b ldr r3, [r3, #56] @ 0x38 800de4a: f3c3 0308 ubfx r3, r3, #0, #9 800de4e: ee07 3a90 vmov s15, r3 800de52: eef8 6a67 vcvt.f32.u32 s13, s15 800de56: ed97 6a03 vldr s12, [r7, #12] 800de5a: eddf 5a78 vldr s11, [pc, #480] @ 800e03c 800de5e: eec6 7a25 vdiv.f32 s15, s12, s11 800de62: ee76 7aa7 vadd.f32 s15, s13, s15 800de66: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800de6a: ee77 7aa6 vadd.f32 s15, s15, s13 800de6e: ee67 7a27 vmul.f32 s15, s14, s15 800de72: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800de76: e087 b.n 800df88 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800de78: 697b ldr r3, [r7, #20] 800de7a: ee07 3a90 vmov s15, r3 800de7e: eef8 7a67 vcvt.f32.u32 s15, s15 800de82: eddf 6a6f vldr s13, [pc, #444] @ 800e040 800de86: ee86 7aa7 vdiv.f32 s14, s13, s15 800de8a: 4b6a ldr r3, [pc, #424] @ (800e034 ) 800de8c: 6b9b ldr r3, [r3, #56] @ 0x38 800de8e: f3c3 0308 ubfx r3, r3, #0, #9 800de92: ee07 3a90 vmov s15, r3 800de96: eef8 6a67 vcvt.f32.u32 s13, s15 800de9a: ed97 6a03 vldr s12, [r7, #12] 800de9e: eddf 5a67 vldr s11, [pc, #412] @ 800e03c 800dea2: eec6 7a25 vdiv.f32 s15, s12, s11 800dea6: ee76 7aa7 vadd.f32 s15, s13, s15 800deaa: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800deae: ee77 7aa6 vadd.f32 s15, s15, s13 800deb2: ee67 7a27 vmul.f32 s15, s14, s15 800deb6: edc7 7a07 vstr s15, [r7, #28] break; 800deba: e065 b.n 800df88 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800debc: 697b ldr r3, [r7, #20] 800debe: ee07 3a90 vmov s15, r3 800dec2: eef8 7a67 vcvt.f32.u32 s15, s15 800dec6: eddf 6a5f vldr s13, [pc, #380] @ 800e044 800deca: ee86 7aa7 vdiv.f32 s14, s13, s15 800dece: 4b59 ldr r3, [pc, #356] @ (800e034 ) 800ded0: 6b9b ldr r3, [r3, #56] @ 0x38 800ded2: f3c3 0308 ubfx r3, r3, #0, #9 800ded6: ee07 3a90 vmov s15, r3 800deda: eef8 6a67 vcvt.f32.u32 s13, s15 800dede: ed97 6a03 vldr s12, [r7, #12] 800dee2: eddf 5a56 vldr s11, [pc, #344] @ 800e03c 800dee6: eec6 7a25 vdiv.f32 s15, s12, s11 800deea: ee76 7aa7 vadd.f32 s15, s13, s15 800deee: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800def2: ee77 7aa6 vadd.f32 s15, s15, s13 800def6: ee67 7a27 vmul.f32 s15, s14, s15 800defa: edc7 7a07 vstr s15, [r7, #28] break; 800defe: e043 b.n 800df88 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800df00: 697b ldr r3, [r7, #20] 800df02: ee07 3a90 vmov s15, r3 800df06: eef8 7a67 vcvt.f32.u32 s15, s15 800df0a: eddf 6a4f vldr s13, [pc, #316] @ 800e048 800df0e: ee86 7aa7 vdiv.f32 s14, s13, s15 800df12: 4b48 ldr r3, [pc, #288] @ (800e034 ) 800df14: 6b9b ldr r3, [r3, #56] @ 0x38 800df16: f3c3 0308 ubfx r3, r3, #0, #9 800df1a: ee07 3a90 vmov s15, r3 800df1e: eef8 6a67 vcvt.f32.u32 s13, s15 800df22: ed97 6a03 vldr s12, [r7, #12] 800df26: eddf 5a45 vldr s11, [pc, #276] @ 800e03c 800df2a: eec6 7a25 vdiv.f32 s15, s12, s11 800df2e: ee76 7aa7 vadd.f32 s15, s13, s15 800df32: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800df36: ee77 7aa6 vadd.f32 s15, s15, s13 800df3a: ee67 7a27 vmul.f32 s15, s14, s15 800df3e: edc7 7a07 vstr s15, [r7, #28] break; 800df42: e021 b.n 800df88 default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800df44: 697b ldr r3, [r7, #20] 800df46: ee07 3a90 vmov s15, r3 800df4a: eef8 7a67 vcvt.f32.u32 s15, s15 800df4e: eddf 6a3d vldr s13, [pc, #244] @ 800e044 800df52: ee86 7aa7 vdiv.f32 s14, s13, s15 800df56: 4b37 ldr r3, [pc, #220] @ (800e034 ) 800df58: 6b9b ldr r3, [r3, #56] @ 0x38 800df5a: f3c3 0308 ubfx r3, r3, #0, #9 800df5e: ee07 3a90 vmov s15, r3 800df62: eef8 6a67 vcvt.f32.u32 s13, s15 800df66: ed97 6a03 vldr s12, [r7, #12] 800df6a: eddf 5a34 vldr s11, [pc, #208] @ 800e03c 800df6e: eec6 7a25 vdiv.f32 s15, s12, s11 800df72: ee76 7aa7 vadd.f32 s15, s13, s15 800df76: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800df7a: ee77 7aa6 vadd.f32 s15, s15, s13 800df7e: ee67 7a27 vmul.f32 s15, s14, s15 800df82: edc7 7a07 vstr s15, [r7, #28] break; 800df86: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800df88: 4b2a ldr r3, [pc, #168] @ (800e034 ) 800df8a: 6b9b ldr r3, [r3, #56] @ 0x38 800df8c: 0a5b lsrs r3, r3, #9 800df8e: f003 037f and.w r3, r3, #127 @ 0x7f 800df92: ee07 3a90 vmov s15, r3 800df96: eef8 7a67 vcvt.f32.u32 s15, s15 800df9a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800df9e: ee37 7a87 vadd.f32 s14, s15, s14 800dfa2: edd7 6a07 vldr s13, [r7, #28] 800dfa6: eec6 7a87 vdiv.f32 s15, s13, s14 800dfaa: eefc 7ae7 vcvt.u32.f32 s15, s15 800dfae: ee17 2a90 vmov r2, s15 800dfb2: 687b ldr r3, [r7, #4] 800dfb4: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800dfb6: 4b1f ldr r3, [pc, #124] @ (800e034 ) 800dfb8: 6b9b ldr r3, [r3, #56] @ 0x38 800dfba: 0c1b lsrs r3, r3, #16 800dfbc: f003 037f and.w r3, r3, #127 @ 0x7f 800dfc0: ee07 3a90 vmov s15, r3 800dfc4: eef8 7a67 vcvt.f32.u32 s15, s15 800dfc8: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800dfcc: ee37 7a87 vadd.f32 s14, s15, s14 800dfd0: edd7 6a07 vldr s13, [r7, #28] 800dfd4: eec6 7a87 vdiv.f32 s15, s13, s14 800dfd8: eefc 7ae7 vcvt.u32.f32 s15, s15 800dfdc: ee17 2a90 vmov r2, s15 800dfe0: 687b ldr r3, [r7, #4] 800dfe2: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800dfe4: 4b13 ldr r3, [pc, #76] @ (800e034 ) 800dfe6: 6b9b ldr r3, [r3, #56] @ 0x38 800dfe8: 0e1b lsrs r3, r3, #24 800dfea: f003 037f and.w r3, r3, #127 @ 0x7f 800dfee: ee07 3a90 vmov s15, r3 800dff2: eef8 7a67 vcvt.f32.u32 s15, s15 800dff6: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800dffa: ee37 7a87 vadd.f32 s14, s15, s14 800dffe: edd7 6a07 vldr s13, [r7, #28] 800e002: eec6 7a87 vdiv.f32 s15, s13, s14 800e006: eefc 7ae7 vcvt.u32.f32 s15, s15 800e00a: ee17 2a90 vmov r2, s15 800e00e: 687b ldr r3, [r7, #4] 800e010: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800e012: e008 b.n 800e026 PLL2_Clocks->PLL2_P_Frequency = 0U; 800e014: 687b ldr r3, [r7, #4] 800e016: 2200 movs r2, #0 800e018: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 800e01a: 687b ldr r3, [r7, #4] 800e01c: 2200 movs r2, #0 800e01e: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 800e020: 687b ldr r3, [r7, #4] 800e022: 2200 movs r2, #0 800e024: 609a str r2, [r3, #8] } 800e026: bf00 nop 800e028: 3724 adds r7, #36 @ 0x24 800e02a: 46bd mov sp, r7 800e02c: f85d 7b04 ldr.w r7, [sp], #4 800e030: 4770 bx lr 800e032: bf00 nop 800e034: 58024400 .word 0x58024400 800e038: 03d09000 .word 0x03d09000 800e03c: 46000000 .word 0x46000000 800e040: 4c742400 .word 0x4c742400 800e044: 4a742400 .word 0x4a742400 800e048: 4bbebc20 .word 0x4bbebc20 0800e04c : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 800e04c: b480 push {r7} 800e04e: b089 sub sp, #36 @ 0x24 800e050: af00 add r7, sp, #0 800e052: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e054: 4ba1 ldr r3, [pc, #644] @ (800e2dc ) 800e056: 6a9b ldr r3, [r3, #40] @ 0x28 800e058: f003 0303 and.w r3, r3, #3 800e05c: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800e05e: 4b9f ldr r3, [pc, #636] @ (800e2dc ) 800e060: 6a9b ldr r3, [r3, #40] @ 0x28 800e062: 0d1b lsrs r3, r3, #20 800e064: f003 033f and.w r3, r3, #63 @ 0x3f 800e068: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800e06a: 4b9c ldr r3, [pc, #624] @ (800e2dc ) 800e06c: 6adb ldr r3, [r3, #44] @ 0x2c 800e06e: 0a1b lsrs r3, r3, #8 800e070: f003 0301 and.w r3, r3, #1 800e074: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800e076: 4b99 ldr r3, [pc, #612] @ (800e2dc ) 800e078: 6c5b ldr r3, [r3, #68] @ 0x44 800e07a: 08db lsrs r3, r3, #3 800e07c: f3c3 030c ubfx r3, r3, #0, #13 800e080: 693a ldr r2, [r7, #16] 800e082: fb02 f303 mul.w r3, r2, r3 800e086: ee07 3a90 vmov s15, r3 800e08a: eef8 7a67 vcvt.f32.u32 s15, s15 800e08e: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800e092: 697b ldr r3, [r7, #20] 800e094: 2b00 cmp r3, #0 800e096: f000 8111 beq.w 800e2bc { switch (pllsource) 800e09a: 69bb ldr r3, [r7, #24] 800e09c: 2b02 cmp r3, #2 800e09e: f000 8083 beq.w 800e1a8 800e0a2: 69bb ldr r3, [r7, #24] 800e0a4: 2b02 cmp r3, #2 800e0a6: f200 80a1 bhi.w 800e1ec 800e0aa: 69bb ldr r3, [r7, #24] 800e0ac: 2b00 cmp r3, #0 800e0ae: d003 beq.n 800e0b8 800e0b0: 69bb ldr r3, [r7, #24] 800e0b2: 2b01 cmp r3, #1 800e0b4: d056 beq.n 800e164 800e0b6: e099 b.n 800e1ec { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e0b8: 4b88 ldr r3, [pc, #544] @ (800e2dc ) 800e0ba: 681b ldr r3, [r3, #0] 800e0bc: f003 0320 and.w r3, r3, #32 800e0c0: 2b00 cmp r3, #0 800e0c2: d02d beq.n 800e120 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e0c4: 4b85 ldr r3, [pc, #532] @ (800e2dc ) 800e0c6: 681b ldr r3, [r3, #0] 800e0c8: 08db lsrs r3, r3, #3 800e0ca: f003 0303 and.w r3, r3, #3 800e0ce: 4a84 ldr r2, [pc, #528] @ (800e2e0 ) 800e0d0: fa22 f303 lsr.w r3, r2, r3 800e0d4: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e0d6: 68bb ldr r3, [r7, #8] 800e0d8: ee07 3a90 vmov s15, r3 800e0dc: eef8 6a67 vcvt.f32.u32 s13, s15 800e0e0: 697b ldr r3, [r7, #20] 800e0e2: ee07 3a90 vmov s15, r3 800e0e6: eef8 7a67 vcvt.f32.u32 s15, s15 800e0ea: ee86 7aa7 vdiv.f32 s14, s13, s15 800e0ee: 4b7b ldr r3, [pc, #492] @ (800e2dc ) 800e0f0: 6c1b ldr r3, [r3, #64] @ 0x40 800e0f2: f3c3 0308 ubfx r3, r3, #0, #9 800e0f6: ee07 3a90 vmov s15, r3 800e0fa: eef8 6a67 vcvt.f32.u32 s13, s15 800e0fe: ed97 6a03 vldr s12, [r7, #12] 800e102: eddf 5a78 vldr s11, [pc, #480] @ 800e2e4 800e106: eec6 7a25 vdiv.f32 s15, s12, s11 800e10a: ee76 7aa7 vadd.f32 s15, s13, s15 800e10e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e112: ee77 7aa6 vadd.f32 s15, s15, s13 800e116: ee67 7a27 vmul.f32 s15, s14, s15 800e11a: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800e11e: e087 b.n 800e230 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e120: 697b ldr r3, [r7, #20] 800e122: ee07 3a90 vmov s15, r3 800e126: eef8 7a67 vcvt.f32.u32 s15, s15 800e12a: eddf 6a6f vldr s13, [pc, #444] @ 800e2e8 800e12e: ee86 7aa7 vdiv.f32 s14, s13, s15 800e132: 4b6a ldr r3, [pc, #424] @ (800e2dc ) 800e134: 6c1b ldr r3, [r3, #64] @ 0x40 800e136: f3c3 0308 ubfx r3, r3, #0, #9 800e13a: ee07 3a90 vmov s15, r3 800e13e: eef8 6a67 vcvt.f32.u32 s13, s15 800e142: ed97 6a03 vldr s12, [r7, #12] 800e146: eddf 5a67 vldr s11, [pc, #412] @ 800e2e4 800e14a: eec6 7a25 vdiv.f32 s15, s12, s11 800e14e: ee76 7aa7 vadd.f32 s15, s13, s15 800e152: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e156: ee77 7aa6 vadd.f32 s15, s15, s13 800e15a: ee67 7a27 vmul.f32 s15, s14, s15 800e15e: edc7 7a07 vstr s15, [r7, #28] break; 800e162: e065 b.n 800e230 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e164: 697b ldr r3, [r7, #20] 800e166: ee07 3a90 vmov s15, r3 800e16a: eef8 7a67 vcvt.f32.u32 s15, s15 800e16e: eddf 6a5f vldr s13, [pc, #380] @ 800e2ec 800e172: ee86 7aa7 vdiv.f32 s14, s13, s15 800e176: 4b59 ldr r3, [pc, #356] @ (800e2dc ) 800e178: 6c1b ldr r3, [r3, #64] @ 0x40 800e17a: f3c3 0308 ubfx r3, r3, #0, #9 800e17e: ee07 3a90 vmov s15, r3 800e182: eef8 6a67 vcvt.f32.u32 s13, s15 800e186: ed97 6a03 vldr s12, [r7, #12] 800e18a: eddf 5a56 vldr s11, [pc, #344] @ 800e2e4 800e18e: eec6 7a25 vdiv.f32 s15, s12, s11 800e192: ee76 7aa7 vadd.f32 s15, s13, s15 800e196: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e19a: ee77 7aa6 vadd.f32 s15, s15, s13 800e19e: ee67 7a27 vmul.f32 s15, s14, s15 800e1a2: edc7 7a07 vstr s15, [r7, #28] break; 800e1a6: e043 b.n 800e230 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e1a8: 697b ldr r3, [r7, #20] 800e1aa: ee07 3a90 vmov s15, r3 800e1ae: eef8 7a67 vcvt.f32.u32 s15, s15 800e1b2: eddf 6a4f vldr s13, [pc, #316] @ 800e2f0 800e1b6: ee86 7aa7 vdiv.f32 s14, s13, s15 800e1ba: 4b48 ldr r3, [pc, #288] @ (800e2dc ) 800e1bc: 6c1b ldr r3, [r3, #64] @ 0x40 800e1be: f3c3 0308 ubfx r3, r3, #0, #9 800e1c2: ee07 3a90 vmov s15, r3 800e1c6: eef8 6a67 vcvt.f32.u32 s13, s15 800e1ca: ed97 6a03 vldr s12, [r7, #12] 800e1ce: eddf 5a45 vldr s11, [pc, #276] @ 800e2e4 800e1d2: eec6 7a25 vdiv.f32 s15, s12, s11 800e1d6: ee76 7aa7 vadd.f32 s15, s13, s15 800e1da: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e1de: ee77 7aa6 vadd.f32 s15, s15, s13 800e1e2: ee67 7a27 vmul.f32 s15, s14, s15 800e1e6: edc7 7a07 vstr s15, [r7, #28] break; 800e1ea: e021 b.n 800e230 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800e1ec: 697b ldr r3, [r7, #20] 800e1ee: ee07 3a90 vmov s15, r3 800e1f2: eef8 7a67 vcvt.f32.u32 s15, s15 800e1f6: eddf 6a3d vldr s13, [pc, #244] @ 800e2ec 800e1fa: ee86 7aa7 vdiv.f32 s14, s13, s15 800e1fe: 4b37 ldr r3, [pc, #220] @ (800e2dc ) 800e200: 6c1b ldr r3, [r3, #64] @ 0x40 800e202: f3c3 0308 ubfx r3, r3, #0, #9 800e206: ee07 3a90 vmov s15, r3 800e20a: eef8 6a67 vcvt.f32.u32 s13, s15 800e20e: ed97 6a03 vldr s12, [r7, #12] 800e212: eddf 5a34 vldr s11, [pc, #208] @ 800e2e4 800e216: eec6 7a25 vdiv.f32 s15, s12, s11 800e21a: ee76 7aa7 vadd.f32 s15, s13, s15 800e21e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e222: ee77 7aa6 vadd.f32 s15, s15, s13 800e226: ee67 7a27 vmul.f32 s15, s14, s15 800e22a: edc7 7a07 vstr s15, [r7, #28] break; 800e22e: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800e230: 4b2a ldr r3, [pc, #168] @ (800e2dc ) 800e232: 6c1b ldr r3, [r3, #64] @ 0x40 800e234: 0a5b lsrs r3, r3, #9 800e236: f003 037f and.w r3, r3, #127 @ 0x7f 800e23a: ee07 3a90 vmov s15, r3 800e23e: eef8 7a67 vcvt.f32.u32 s15, s15 800e242: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e246: ee37 7a87 vadd.f32 s14, s15, s14 800e24a: edd7 6a07 vldr s13, [r7, #28] 800e24e: eec6 7a87 vdiv.f32 s15, s13, s14 800e252: eefc 7ae7 vcvt.u32.f32 s15, s15 800e256: ee17 2a90 vmov r2, s15 800e25a: 687b ldr r3, [r7, #4] 800e25c: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800e25e: 4b1f ldr r3, [pc, #124] @ (800e2dc ) 800e260: 6c1b ldr r3, [r3, #64] @ 0x40 800e262: 0c1b lsrs r3, r3, #16 800e264: f003 037f and.w r3, r3, #127 @ 0x7f 800e268: ee07 3a90 vmov s15, r3 800e26c: eef8 7a67 vcvt.f32.u32 s15, s15 800e270: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e274: ee37 7a87 vadd.f32 s14, s15, s14 800e278: edd7 6a07 vldr s13, [r7, #28] 800e27c: eec6 7a87 vdiv.f32 s15, s13, s14 800e280: eefc 7ae7 vcvt.u32.f32 s15, s15 800e284: ee17 2a90 vmov r2, s15 800e288: 687b ldr r3, [r7, #4] 800e28a: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800e28c: 4b13 ldr r3, [pc, #76] @ (800e2dc ) 800e28e: 6c1b ldr r3, [r3, #64] @ 0x40 800e290: 0e1b lsrs r3, r3, #24 800e292: f003 037f and.w r3, r3, #127 @ 0x7f 800e296: ee07 3a90 vmov s15, r3 800e29a: eef8 7a67 vcvt.f32.u32 s15, s15 800e29e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e2a2: ee37 7a87 vadd.f32 s14, s15, s14 800e2a6: edd7 6a07 vldr s13, [r7, #28] 800e2aa: eec6 7a87 vdiv.f32 s15, s13, s14 800e2ae: eefc 7ae7 vcvt.u32.f32 s15, s15 800e2b2: ee17 2a90 vmov r2, s15 800e2b6: 687b ldr r3, [r7, #4] 800e2b8: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800e2ba: e008 b.n 800e2ce PLL3_Clocks->PLL3_P_Frequency = 0U; 800e2bc: 687b ldr r3, [r7, #4] 800e2be: 2200 movs r2, #0 800e2c0: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800e2c2: 687b ldr r3, [r7, #4] 800e2c4: 2200 movs r2, #0 800e2c6: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800e2c8: 687b ldr r3, [r7, #4] 800e2ca: 2200 movs r2, #0 800e2cc: 609a str r2, [r3, #8] } 800e2ce: bf00 nop 800e2d0: 3724 adds r7, #36 @ 0x24 800e2d2: 46bd mov sp, r7 800e2d4: f85d 7b04 ldr.w r7, [sp], #4 800e2d8: 4770 bx lr 800e2da: bf00 nop 800e2dc: 58024400 .word 0x58024400 800e2e0: 03d09000 .word 0x03d09000 800e2e4: 46000000 .word 0x46000000 800e2e8: 4c742400 .word 0x4c742400 800e2ec: 4a742400 .word 0x4a742400 800e2f0: 4bbebc20 .word 0x4bbebc20 0800e2f4 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800e2f4: b480 push {r7} 800e2f6: b089 sub sp, #36 @ 0x24 800e2f8: af00 add r7, sp, #0 800e2fa: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e2fc: 4ba0 ldr r3, [pc, #640] @ (800e580 ) 800e2fe: 6a9b ldr r3, [r3, #40] @ 0x28 800e300: f003 0303 and.w r3, r3, #3 800e304: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800e306: 4b9e ldr r3, [pc, #632] @ (800e580 ) 800e308: 6a9b ldr r3, [r3, #40] @ 0x28 800e30a: 091b lsrs r3, r3, #4 800e30c: f003 033f and.w r3, r3, #63 @ 0x3f 800e310: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800e312: 4b9b ldr r3, [pc, #620] @ (800e580 ) 800e314: 6adb ldr r3, [r3, #44] @ 0x2c 800e316: f003 0301 and.w r3, r3, #1 800e31a: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800e31c: 4b98 ldr r3, [pc, #608] @ (800e580 ) 800e31e: 6b5b ldr r3, [r3, #52] @ 0x34 800e320: 08db lsrs r3, r3, #3 800e322: f3c3 030c ubfx r3, r3, #0, #13 800e326: 693a ldr r2, [r7, #16] 800e328: fb02 f303 mul.w r3, r2, r3 800e32c: ee07 3a90 vmov s15, r3 800e330: eef8 7a67 vcvt.f32.u32 s15, s15 800e334: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800e338: 697b ldr r3, [r7, #20] 800e33a: 2b00 cmp r3, #0 800e33c: f000 8111 beq.w 800e562 { switch (pllsource) 800e340: 69bb ldr r3, [r7, #24] 800e342: 2b02 cmp r3, #2 800e344: f000 8083 beq.w 800e44e 800e348: 69bb ldr r3, [r7, #24] 800e34a: 2b02 cmp r3, #2 800e34c: f200 80a1 bhi.w 800e492 800e350: 69bb ldr r3, [r7, #24] 800e352: 2b00 cmp r3, #0 800e354: d003 beq.n 800e35e 800e356: 69bb ldr r3, [r7, #24] 800e358: 2b01 cmp r3, #1 800e35a: d056 beq.n 800e40a 800e35c: e099 b.n 800e492 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e35e: 4b88 ldr r3, [pc, #544] @ (800e580 ) 800e360: 681b ldr r3, [r3, #0] 800e362: f003 0320 and.w r3, r3, #32 800e366: 2b00 cmp r3, #0 800e368: d02d beq.n 800e3c6 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e36a: 4b85 ldr r3, [pc, #532] @ (800e580 ) 800e36c: 681b ldr r3, [r3, #0] 800e36e: 08db lsrs r3, r3, #3 800e370: f003 0303 and.w r3, r3, #3 800e374: 4a83 ldr r2, [pc, #524] @ (800e584 ) 800e376: fa22 f303 lsr.w r3, r2, r3 800e37a: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800e37c: 68bb ldr r3, [r7, #8] 800e37e: ee07 3a90 vmov s15, r3 800e382: eef8 6a67 vcvt.f32.u32 s13, s15 800e386: 697b ldr r3, [r7, #20] 800e388: ee07 3a90 vmov s15, r3 800e38c: eef8 7a67 vcvt.f32.u32 s15, s15 800e390: ee86 7aa7 vdiv.f32 s14, s13, s15 800e394: 4b7a ldr r3, [pc, #488] @ (800e580 ) 800e396: 6b1b ldr r3, [r3, #48] @ 0x30 800e398: f3c3 0308 ubfx r3, r3, #0, #9 800e39c: ee07 3a90 vmov s15, r3 800e3a0: eef8 6a67 vcvt.f32.u32 s13, s15 800e3a4: ed97 6a03 vldr s12, [r7, #12] 800e3a8: eddf 5a77 vldr s11, [pc, #476] @ 800e588 800e3ac: eec6 7a25 vdiv.f32 s15, s12, s11 800e3b0: ee76 7aa7 vadd.f32 s15, s13, s15 800e3b4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e3b8: ee77 7aa6 vadd.f32 s15, s15, s13 800e3bc: ee67 7a27 vmul.f32 s15, s14, s15 800e3c0: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800e3c4: e087 b.n 800e4d6 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800e3c6: 697b ldr r3, [r7, #20] 800e3c8: ee07 3a90 vmov s15, r3 800e3cc: eef8 7a67 vcvt.f32.u32 s15, s15 800e3d0: eddf 6a6e vldr s13, [pc, #440] @ 800e58c 800e3d4: ee86 7aa7 vdiv.f32 s14, s13, s15 800e3d8: 4b69 ldr r3, [pc, #420] @ (800e580 ) 800e3da: 6b1b ldr r3, [r3, #48] @ 0x30 800e3dc: f3c3 0308 ubfx r3, r3, #0, #9 800e3e0: ee07 3a90 vmov s15, r3 800e3e4: eef8 6a67 vcvt.f32.u32 s13, s15 800e3e8: ed97 6a03 vldr s12, [r7, #12] 800e3ec: eddf 5a66 vldr s11, [pc, #408] @ 800e588 800e3f0: eec6 7a25 vdiv.f32 s15, s12, s11 800e3f4: ee76 7aa7 vadd.f32 s15, s13, s15 800e3f8: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e3fc: ee77 7aa6 vadd.f32 s15, s15, s13 800e400: ee67 7a27 vmul.f32 s15, s14, s15 800e404: edc7 7a07 vstr s15, [r7, #28] break; 800e408: e065 b.n 800e4d6 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800e40a: 697b ldr r3, [r7, #20] 800e40c: ee07 3a90 vmov s15, r3 800e410: eef8 7a67 vcvt.f32.u32 s15, s15 800e414: eddf 6a5e vldr s13, [pc, #376] @ 800e590 800e418: ee86 7aa7 vdiv.f32 s14, s13, s15 800e41c: 4b58 ldr r3, [pc, #352] @ (800e580 ) 800e41e: 6b1b ldr r3, [r3, #48] @ 0x30 800e420: f3c3 0308 ubfx r3, r3, #0, #9 800e424: ee07 3a90 vmov s15, r3 800e428: eef8 6a67 vcvt.f32.u32 s13, s15 800e42c: ed97 6a03 vldr s12, [r7, #12] 800e430: eddf 5a55 vldr s11, [pc, #340] @ 800e588 800e434: eec6 7a25 vdiv.f32 s15, s12, s11 800e438: ee76 7aa7 vadd.f32 s15, s13, s15 800e43c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e440: ee77 7aa6 vadd.f32 s15, s15, s13 800e444: ee67 7a27 vmul.f32 s15, s14, s15 800e448: edc7 7a07 vstr s15, [r7, #28] break; 800e44c: e043 b.n 800e4d6 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800e44e: 697b ldr r3, [r7, #20] 800e450: ee07 3a90 vmov s15, r3 800e454: eef8 7a67 vcvt.f32.u32 s15, s15 800e458: eddf 6a4e vldr s13, [pc, #312] @ 800e594 800e45c: ee86 7aa7 vdiv.f32 s14, s13, s15 800e460: 4b47 ldr r3, [pc, #284] @ (800e580 ) 800e462: 6b1b ldr r3, [r3, #48] @ 0x30 800e464: f3c3 0308 ubfx r3, r3, #0, #9 800e468: ee07 3a90 vmov s15, r3 800e46c: eef8 6a67 vcvt.f32.u32 s13, s15 800e470: ed97 6a03 vldr s12, [r7, #12] 800e474: eddf 5a44 vldr s11, [pc, #272] @ 800e588 800e478: eec6 7a25 vdiv.f32 s15, s12, s11 800e47c: ee76 7aa7 vadd.f32 s15, s13, s15 800e480: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e484: ee77 7aa6 vadd.f32 s15, s15, s13 800e488: ee67 7a27 vmul.f32 s15, s14, s15 800e48c: edc7 7a07 vstr s15, [r7, #28] break; 800e490: e021 b.n 800e4d6 default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800e492: 697b ldr r3, [r7, #20] 800e494: ee07 3a90 vmov s15, r3 800e498: eef8 7a67 vcvt.f32.u32 s15, s15 800e49c: eddf 6a3b vldr s13, [pc, #236] @ 800e58c 800e4a0: ee86 7aa7 vdiv.f32 s14, s13, s15 800e4a4: 4b36 ldr r3, [pc, #216] @ (800e580 ) 800e4a6: 6b1b ldr r3, [r3, #48] @ 0x30 800e4a8: f3c3 0308 ubfx r3, r3, #0, #9 800e4ac: ee07 3a90 vmov s15, r3 800e4b0: eef8 6a67 vcvt.f32.u32 s13, s15 800e4b4: ed97 6a03 vldr s12, [r7, #12] 800e4b8: eddf 5a33 vldr s11, [pc, #204] @ 800e588 800e4bc: eec6 7a25 vdiv.f32 s15, s12, s11 800e4c0: ee76 7aa7 vadd.f32 s15, s13, s15 800e4c4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e4c8: ee77 7aa6 vadd.f32 s15, s15, s13 800e4cc: ee67 7a27 vmul.f32 s15, s14, s15 800e4d0: edc7 7a07 vstr s15, [r7, #28] break; 800e4d4: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800e4d6: 4b2a ldr r3, [pc, #168] @ (800e580 ) 800e4d8: 6b1b ldr r3, [r3, #48] @ 0x30 800e4da: 0a5b lsrs r3, r3, #9 800e4dc: f003 037f and.w r3, r3, #127 @ 0x7f 800e4e0: ee07 3a90 vmov s15, r3 800e4e4: eef8 7a67 vcvt.f32.u32 s15, s15 800e4e8: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e4ec: ee37 7a87 vadd.f32 s14, s15, s14 800e4f0: edd7 6a07 vldr s13, [r7, #28] 800e4f4: eec6 7a87 vdiv.f32 s15, s13, s14 800e4f8: eefc 7ae7 vcvt.u32.f32 s15, s15 800e4fc: ee17 2a90 vmov r2, s15 800e500: 687b ldr r3, [r7, #4] 800e502: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800e504: 4b1e ldr r3, [pc, #120] @ (800e580 ) 800e506: 6b1b ldr r3, [r3, #48] @ 0x30 800e508: 0c1b lsrs r3, r3, #16 800e50a: f003 037f and.w r3, r3, #127 @ 0x7f 800e50e: ee07 3a90 vmov s15, r3 800e512: eef8 7a67 vcvt.f32.u32 s15, s15 800e516: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e51a: ee37 7a87 vadd.f32 s14, s15, s14 800e51e: edd7 6a07 vldr s13, [r7, #28] 800e522: eec6 7a87 vdiv.f32 s15, s13, s14 800e526: eefc 7ae7 vcvt.u32.f32 s15, s15 800e52a: ee17 2a90 vmov r2, s15 800e52e: 687b ldr r3, [r7, #4] 800e530: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800e532: 4b13 ldr r3, [pc, #76] @ (800e580 ) 800e534: 6b1b ldr r3, [r3, #48] @ 0x30 800e536: 0e1b lsrs r3, r3, #24 800e538: f003 037f and.w r3, r3, #127 @ 0x7f 800e53c: ee07 3a90 vmov s15, r3 800e540: eef8 7a67 vcvt.f32.u32 s15, s15 800e544: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800e548: ee37 7a87 vadd.f32 s14, s15, s14 800e54c: edd7 6a07 vldr s13, [r7, #28] 800e550: eec6 7a87 vdiv.f32 s15, s13, s14 800e554: eefc 7ae7 vcvt.u32.f32 s15, s15 800e558: ee17 2a90 vmov r2, s15 800e55c: 687b ldr r3, [r7, #4] 800e55e: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800e560: e008 b.n 800e574 PLL1_Clocks->PLL1_P_Frequency = 0U; 800e562: 687b ldr r3, [r7, #4] 800e564: 2200 movs r2, #0 800e566: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800e568: 687b ldr r3, [r7, #4] 800e56a: 2200 movs r2, #0 800e56c: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800e56e: 687b ldr r3, [r7, #4] 800e570: 2200 movs r2, #0 800e572: 609a str r2, [r3, #8] } 800e574: bf00 nop 800e576: 3724 adds r7, #36 @ 0x24 800e578: 46bd mov sp, r7 800e57a: f85d 7b04 ldr.w r7, [sp], #4 800e57e: 4770 bx lr 800e580: 58024400 .word 0x58024400 800e584: 03d09000 .word 0x03d09000 800e588: 46000000 .word 0x46000000 800e58c: 4c742400 .word 0x4c742400 800e590: 4a742400 .word 0x4a742400 800e594: 4bbebc20 .word 0x4bbebc20 0800e598 : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800e598: b580 push {r7, lr} 800e59a: b084 sub sp, #16 800e59c: af00 add r7, sp, #0 800e59e: 6078 str r0, [r7, #4] 800e5a0: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800e5a2: 2300 movs r3, #0 800e5a4: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800e5a6: 4b53 ldr r3, [pc, #332] @ (800e6f4 ) 800e5a8: 6a9b ldr r3, [r3, #40] @ 0x28 800e5aa: f003 0303 and.w r3, r3, #3 800e5ae: 2b03 cmp r3, #3 800e5b0: d101 bne.n 800e5b6 { return HAL_ERROR; 800e5b2: 2301 movs r3, #1 800e5b4: e099 b.n 800e6ea else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800e5b6: 4b4f ldr r3, [pc, #316] @ (800e6f4 ) 800e5b8: 681b ldr r3, [r3, #0] 800e5ba: 4a4e ldr r2, [pc, #312] @ (800e6f4 ) 800e5bc: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800e5c0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800e5c2: f7f6 ff0b bl 80053dc 800e5c6: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800e5c8: e008 b.n 800e5dc { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800e5ca: f7f6 ff07 bl 80053dc 800e5ce: 4602 mov r2, r0 800e5d0: 68bb ldr r3, [r7, #8] 800e5d2: 1ad3 subs r3, r2, r3 800e5d4: 2b02 cmp r3, #2 800e5d6: d901 bls.n 800e5dc { return HAL_TIMEOUT; 800e5d8: 2303 movs r3, #3 800e5da: e086 b.n 800e6ea while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800e5dc: 4b45 ldr r3, [pc, #276] @ (800e6f4 ) 800e5de: 681b ldr r3, [r3, #0] 800e5e0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e5e4: 2b00 cmp r3, #0 800e5e6: d1f0 bne.n 800e5ca } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800e5e8: 4b42 ldr r3, [pc, #264] @ (800e6f4 ) 800e5ea: 6a9b ldr r3, [r3, #40] @ 0x28 800e5ec: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800e5f0: 687b ldr r3, [r7, #4] 800e5f2: 681b ldr r3, [r3, #0] 800e5f4: 031b lsls r3, r3, #12 800e5f6: 493f ldr r1, [pc, #252] @ (800e6f4 ) 800e5f8: 4313 orrs r3, r2 800e5fa: 628b str r3, [r1, #40] @ 0x28 800e5fc: 687b ldr r3, [r7, #4] 800e5fe: 685b ldr r3, [r3, #4] 800e600: 3b01 subs r3, #1 800e602: f3c3 0208 ubfx r2, r3, #0, #9 800e606: 687b ldr r3, [r7, #4] 800e608: 689b ldr r3, [r3, #8] 800e60a: 3b01 subs r3, #1 800e60c: 025b lsls r3, r3, #9 800e60e: b29b uxth r3, r3 800e610: 431a orrs r2, r3 800e612: 687b ldr r3, [r7, #4] 800e614: 68db ldr r3, [r3, #12] 800e616: 3b01 subs r3, #1 800e618: 041b lsls r3, r3, #16 800e61a: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800e61e: 431a orrs r2, r3 800e620: 687b ldr r3, [r7, #4] 800e622: 691b ldr r3, [r3, #16] 800e624: 3b01 subs r3, #1 800e626: 061b lsls r3, r3, #24 800e628: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800e62c: 4931 ldr r1, [pc, #196] @ (800e6f4 ) 800e62e: 4313 orrs r3, r2 800e630: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800e632: 4b30 ldr r3, [pc, #192] @ (800e6f4 ) 800e634: 6adb ldr r3, [r3, #44] @ 0x2c 800e636: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800e63a: 687b ldr r3, [r7, #4] 800e63c: 695b ldr r3, [r3, #20] 800e63e: 492d ldr r1, [pc, #180] @ (800e6f4 ) 800e640: 4313 orrs r3, r2 800e642: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800e644: 4b2b ldr r3, [pc, #172] @ (800e6f4 ) 800e646: 6adb ldr r3, [r3, #44] @ 0x2c 800e648: f023 0220 bic.w r2, r3, #32 800e64c: 687b ldr r3, [r7, #4] 800e64e: 699b ldr r3, [r3, #24] 800e650: 4928 ldr r1, [pc, #160] @ (800e6f4 ) 800e652: 4313 orrs r3, r2 800e654: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800e656: 4b27 ldr r3, [pc, #156] @ (800e6f4 ) 800e658: 6adb ldr r3, [r3, #44] @ 0x2c 800e65a: 4a26 ldr r2, [pc, #152] @ (800e6f4 ) 800e65c: f023 0310 bic.w r3, r3, #16 800e660: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800e662: 4b24 ldr r3, [pc, #144] @ (800e6f4 ) 800e664: 6bda ldr r2, [r3, #60] @ 0x3c 800e666: 4b24 ldr r3, [pc, #144] @ (800e6f8 ) 800e668: 4013 ands r3, r2 800e66a: 687a ldr r2, [r7, #4] 800e66c: 69d2 ldr r2, [r2, #28] 800e66e: 00d2 lsls r2, r2, #3 800e670: 4920 ldr r1, [pc, #128] @ (800e6f4 ) 800e672: 4313 orrs r3, r2 800e674: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800e676: 4b1f ldr r3, [pc, #124] @ (800e6f4 ) 800e678: 6adb ldr r3, [r3, #44] @ 0x2c 800e67a: 4a1e ldr r2, [pc, #120] @ (800e6f4 ) 800e67c: f043 0310 orr.w r3, r3, #16 800e680: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800e682: 683b ldr r3, [r7, #0] 800e684: 2b00 cmp r3, #0 800e686: d106 bne.n 800e696 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800e688: 4b1a ldr r3, [pc, #104] @ (800e6f4 ) 800e68a: 6adb ldr r3, [r3, #44] @ 0x2c 800e68c: 4a19 ldr r2, [pc, #100] @ (800e6f4 ) 800e68e: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800e692: 62d3 str r3, [r2, #44] @ 0x2c 800e694: e00f b.n 800e6b6 } else if (Divider == DIVIDER_Q_UPDATE) 800e696: 683b ldr r3, [r7, #0] 800e698: 2b01 cmp r3, #1 800e69a: d106 bne.n 800e6aa { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800e69c: 4b15 ldr r3, [pc, #84] @ (800e6f4 ) 800e69e: 6adb ldr r3, [r3, #44] @ 0x2c 800e6a0: 4a14 ldr r2, [pc, #80] @ (800e6f4 ) 800e6a2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800e6a6: 62d3 str r3, [r2, #44] @ 0x2c 800e6a8: e005 b.n 800e6b6 } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800e6aa: 4b12 ldr r3, [pc, #72] @ (800e6f4 ) 800e6ac: 6adb ldr r3, [r3, #44] @ 0x2c 800e6ae: 4a11 ldr r2, [pc, #68] @ (800e6f4 ) 800e6b0: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800e6b4: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800e6b6: 4b0f ldr r3, [pc, #60] @ (800e6f4 ) 800e6b8: 681b ldr r3, [r3, #0] 800e6ba: 4a0e ldr r2, [pc, #56] @ (800e6f4 ) 800e6bc: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800e6c0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800e6c2: f7f6 fe8b bl 80053dc 800e6c6: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800e6c8: e008 b.n 800e6dc { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800e6ca: f7f6 fe87 bl 80053dc 800e6ce: 4602 mov r2, r0 800e6d0: 68bb ldr r3, [r7, #8] 800e6d2: 1ad3 subs r3, r2, r3 800e6d4: 2b02 cmp r3, #2 800e6d6: d901 bls.n 800e6dc { return HAL_TIMEOUT; 800e6d8: 2303 movs r3, #3 800e6da: e006 b.n 800e6ea while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800e6dc: 4b05 ldr r3, [pc, #20] @ (800e6f4 ) 800e6de: 681b ldr r3, [r3, #0] 800e6e0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e6e4: 2b00 cmp r3, #0 800e6e6: d0f0 beq.n 800e6ca } } return status; 800e6e8: 7bfb ldrb r3, [r7, #15] } 800e6ea: 4618 mov r0, r3 800e6ec: 3710 adds r7, #16 800e6ee: 46bd mov sp, r7 800e6f0: bd80 pop {r7, pc} 800e6f2: bf00 nop 800e6f4: 58024400 .word 0x58024400 800e6f8: ffff0007 .word 0xffff0007 0800e6fc : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800e6fc: b580 push {r7, lr} 800e6fe: b084 sub sp, #16 800e700: af00 add r7, sp, #0 800e702: 6078 str r0, [r7, #4] 800e704: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800e706: 2300 movs r3, #0 800e708: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800e70a: 4b53 ldr r3, [pc, #332] @ (800e858 ) 800e70c: 6a9b ldr r3, [r3, #40] @ 0x28 800e70e: f003 0303 and.w r3, r3, #3 800e712: 2b03 cmp r3, #3 800e714: d101 bne.n 800e71a { return HAL_ERROR; 800e716: 2301 movs r3, #1 800e718: e099 b.n 800e84e else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800e71a: 4b4f ldr r3, [pc, #316] @ (800e858 ) 800e71c: 681b ldr r3, [r3, #0] 800e71e: 4a4e ldr r2, [pc, #312] @ (800e858 ) 800e720: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800e724: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800e726: f7f6 fe59 bl 80053dc 800e72a: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800e72c: e008 b.n 800e740 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800e72e: f7f6 fe55 bl 80053dc 800e732: 4602 mov r2, r0 800e734: 68bb ldr r3, [r7, #8] 800e736: 1ad3 subs r3, r2, r3 800e738: 2b02 cmp r3, #2 800e73a: d901 bls.n 800e740 { return HAL_TIMEOUT; 800e73c: 2303 movs r3, #3 800e73e: e086 b.n 800e84e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800e740: 4b45 ldr r3, [pc, #276] @ (800e858 ) 800e742: 681b ldr r3, [r3, #0] 800e744: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e748: 2b00 cmp r3, #0 800e74a: d1f0 bne.n 800e72e } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800e74c: 4b42 ldr r3, [pc, #264] @ (800e858 ) 800e74e: 6a9b ldr r3, [r3, #40] @ 0x28 800e750: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 800e754: 687b ldr r3, [r7, #4] 800e756: 681b ldr r3, [r3, #0] 800e758: 051b lsls r3, r3, #20 800e75a: 493f ldr r1, [pc, #252] @ (800e858 ) 800e75c: 4313 orrs r3, r2 800e75e: 628b str r3, [r1, #40] @ 0x28 800e760: 687b ldr r3, [r7, #4] 800e762: 685b ldr r3, [r3, #4] 800e764: 3b01 subs r3, #1 800e766: f3c3 0208 ubfx r2, r3, #0, #9 800e76a: 687b ldr r3, [r7, #4] 800e76c: 689b ldr r3, [r3, #8] 800e76e: 3b01 subs r3, #1 800e770: 025b lsls r3, r3, #9 800e772: b29b uxth r3, r3 800e774: 431a orrs r2, r3 800e776: 687b ldr r3, [r7, #4] 800e778: 68db ldr r3, [r3, #12] 800e77a: 3b01 subs r3, #1 800e77c: 041b lsls r3, r3, #16 800e77e: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800e782: 431a orrs r2, r3 800e784: 687b ldr r3, [r7, #4] 800e786: 691b ldr r3, [r3, #16] 800e788: 3b01 subs r3, #1 800e78a: 061b lsls r3, r3, #24 800e78c: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800e790: 4931 ldr r1, [pc, #196] @ (800e858 ) 800e792: 4313 orrs r3, r2 800e794: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800e796: 4b30 ldr r3, [pc, #192] @ (800e858 ) 800e798: 6adb ldr r3, [r3, #44] @ 0x2c 800e79a: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800e79e: 687b ldr r3, [r7, #4] 800e7a0: 695b ldr r3, [r3, #20] 800e7a2: 492d ldr r1, [pc, #180] @ (800e858 ) 800e7a4: 4313 orrs r3, r2 800e7a6: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800e7a8: 4b2b ldr r3, [pc, #172] @ (800e858 ) 800e7aa: 6adb ldr r3, [r3, #44] @ 0x2c 800e7ac: f423 7200 bic.w r2, r3, #512 @ 0x200 800e7b0: 687b ldr r3, [r7, #4] 800e7b2: 699b ldr r3, [r3, #24] 800e7b4: 4928 ldr r1, [pc, #160] @ (800e858 ) 800e7b6: 4313 orrs r3, r2 800e7b8: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800e7ba: 4b27 ldr r3, [pc, #156] @ (800e858 ) 800e7bc: 6adb ldr r3, [r3, #44] @ 0x2c 800e7be: 4a26 ldr r2, [pc, #152] @ (800e858 ) 800e7c0: f423 7380 bic.w r3, r3, #256 @ 0x100 800e7c4: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800e7c6: 4b24 ldr r3, [pc, #144] @ (800e858 ) 800e7c8: 6c5a ldr r2, [r3, #68] @ 0x44 800e7ca: 4b24 ldr r3, [pc, #144] @ (800e85c ) 800e7cc: 4013 ands r3, r2 800e7ce: 687a ldr r2, [r7, #4] 800e7d0: 69d2 ldr r2, [r2, #28] 800e7d2: 00d2 lsls r2, r2, #3 800e7d4: 4920 ldr r1, [pc, #128] @ (800e858 ) 800e7d6: 4313 orrs r3, r2 800e7d8: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800e7da: 4b1f ldr r3, [pc, #124] @ (800e858 ) 800e7dc: 6adb ldr r3, [r3, #44] @ 0x2c 800e7de: 4a1e ldr r2, [pc, #120] @ (800e858 ) 800e7e0: f443 7380 orr.w r3, r3, #256 @ 0x100 800e7e4: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800e7e6: 683b ldr r3, [r7, #0] 800e7e8: 2b00 cmp r3, #0 800e7ea: d106 bne.n 800e7fa { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800e7ec: 4b1a ldr r3, [pc, #104] @ (800e858 ) 800e7ee: 6adb ldr r3, [r3, #44] @ 0x2c 800e7f0: 4a19 ldr r2, [pc, #100] @ (800e858 ) 800e7f2: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800e7f6: 62d3 str r3, [r2, #44] @ 0x2c 800e7f8: e00f b.n 800e81a } else if (Divider == DIVIDER_Q_UPDATE) 800e7fa: 683b ldr r3, [r7, #0] 800e7fc: 2b01 cmp r3, #1 800e7fe: d106 bne.n 800e80e { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800e800: 4b15 ldr r3, [pc, #84] @ (800e858 ) 800e802: 6adb ldr r3, [r3, #44] @ 0x2c 800e804: 4a14 ldr r2, [pc, #80] @ (800e858 ) 800e806: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800e80a: 62d3 str r3, [r2, #44] @ 0x2c 800e80c: e005 b.n 800e81a } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800e80e: 4b12 ldr r3, [pc, #72] @ (800e858 ) 800e810: 6adb ldr r3, [r3, #44] @ 0x2c 800e812: 4a11 ldr r2, [pc, #68] @ (800e858 ) 800e814: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800e818: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800e81a: 4b0f ldr r3, [pc, #60] @ (800e858 ) 800e81c: 681b ldr r3, [r3, #0] 800e81e: 4a0e ldr r2, [pc, #56] @ (800e858 ) 800e820: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800e824: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800e826: f7f6 fdd9 bl 80053dc 800e82a: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800e82c: e008 b.n 800e840 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800e82e: f7f6 fdd5 bl 80053dc 800e832: 4602 mov r2, r0 800e834: 68bb ldr r3, [r7, #8] 800e836: 1ad3 subs r3, r2, r3 800e838: 2b02 cmp r3, #2 800e83a: d901 bls.n 800e840 { return HAL_TIMEOUT; 800e83c: 2303 movs r3, #3 800e83e: e006 b.n 800e84e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800e840: 4b05 ldr r3, [pc, #20] @ (800e858 ) 800e842: 681b ldr r3, [r3, #0] 800e844: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e848: 2b00 cmp r3, #0 800e84a: d0f0 beq.n 800e82e } } return status; 800e84c: 7bfb ldrb r3, [r7, #15] } 800e84e: 4618 mov r0, r3 800e850: 3710 adds r7, #16 800e852: 46bd mov sp, r7 800e854: bd80 pop {r7, pc} 800e856: bf00 nop 800e858: 58024400 .word 0x58024400 800e85c: ffff0007 .word 0xffff0007 0800e860 : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 800e860: b580 push {r7, lr} 800e862: b084 sub sp, #16 800e864: af00 add r7, sp, #0 800e866: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 800e868: 687b ldr r3, [r7, #4] 800e86a: 2b00 cmp r3, #0 800e86c: d101 bne.n 800e872 { return HAL_ERROR; 800e86e: 2301 movs r3, #1 800e870: e054 b.n 800e91c /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 800e872: 687b ldr r3, [r7, #4] 800e874: 7a5b ldrb r3, [r3, #9] 800e876: b2db uxtb r3, r3 800e878: 2b00 cmp r3, #0 800e87a: d105 bne.n 800e888 { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 800e87c: 687b ldr r3, [r7, #4] 800e87e: 2200 movs r2, #0 800e880: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 800e882: 6878 ldr r0, [r7, #4] 800e884: f7f5 f84c bl 8003920 } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 800e888: 687b ldr r3, [r7, #4] 800e88a: 2202 movs r2, #2 800e88c: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800e88e: 687b ldr r3, [r7, #4] 800e890: 681b ldr r3, [r3, #0] 800e892: 681b ldr r3, [r3, #0] 800e894: f023 0120 bic.w r1, r3, #32 800e898: 687b ldr r3, [r7, #4] 800e89a: 685a ldr r2, [r3, #4] 800e89c: 687b ldr r3, [r7, #4] 800e89e: 681b ldr r3, [r3, #0] 800e8a0: 430a orrs r2, r1 800e8a2: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 800e8a4: 687b ldr r3, [r7, #4] 800e8a6: 681b ldr r3, [r3, #0] 800e8a8: 681a ldr r2, [r3, #0] 800e8aa: 687b ldr r3, [r7, #4] 800e8ac: 681b ldr r3, [r3, #0] 800e8ae: f042 0204 orr.w r2, r2, #4 800e8b2: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 800e8b4: 687b ldr r3, [r7, #4] 800e8b6: 681b ldr r3, [r3, #0] 800e8b8: 685b ldr r3, [r3, #4] 800e8ba: f003 0340 and.w r3, r3, #64 @ 0x40 800e8be: 2b40 cmp r3, #64 @ 0x40 800e8c0: d104 bne.n 800e8cc { hrng->State = HAL_RNG_STATE_ERROR; 800e8c2: 687b ldr r3, [r7, #4] 800e8c4: 2204 movs r2, #4 800e8c6: 725a strb r2, [r3, #9] return HAL_ERROR; 800e8c8: 2301 movs r3, #1 800e8ca: e027 b.n 800e91c } /* Get tick */ tickstart = HAL_GetTick(); 800e8cc: f7f6 fd86 bl 80053dc 800e8d0: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800e8d2: e015 b.n 800e900 { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800e8d4: f7f6 fd82 bl 80053dc 800e8d8: 4602 mov r2, r0 800e8da: 68fb ldr r3, [r7, #12] 800e8dc: 1ad3 subs r3, r2, r3 800e8de: 2b02 cmp r3, #2 800e8e0: d90e bls.n 800e900 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800e8e2: 687b ldr r3, [r7, #4] 800e8e4: 681b ldr r3, [r3, #0] 800e8e6: 685b ldr r3, [r3, #4] 800e8e8: f003 0304 and.w r3, r3, #4 800e8ec: 2b04 cmp r3, #4 800e8ee: d107 bne.n 800e900 { hrng->State = HAL_RNG_STATE_ERROR; 800e8f0: 687b ldr r3, [r7, #4] 800e8f2: 2204 movs r2, #4 800e8f4: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800e8f6: 687b ldr r3, [r7, #4] 800e8f8: 2202 movs r2, #2 800e8fa: 60da str r2, [r3, #12] return HAL_ERROR; 800e8fc: 2301 movs r3, #1 800e8fe: e00d b.n 800e91c while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800e900: 687b ldr r3, [r7, #4] 800e902: 681b ldr r3, [r3, #0] 800e904: 685b ldr r3, [r3, #4] 800e906: f003 0304 and.w r3, r3, #4 800e90a: 2b04 cmp r3, #4 800e90c: d0e2 beq.n 800e8d4 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800e90e: 687b ldr r3, [r7, #4] 800e910: 2201 movs r2, #1 800e912: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800e914: 687b ldr r3, [r7, #4] 800e916: 2200 movs r2, #0 800e918: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 800e91a: 2300 movs r3, #0 } 800e91c: 4618 mov r0, r3 800e91e: 3710 adds r7, #16 800e920: 46bd mov sp, r7 800e922: bd80 pop {r7, pc} 0800e924 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800e924: b580 push {r7, lr} 800e926: b082 sub sp, #8 800e928: af00 add r7, sp, #0 800e92a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800e92c: 687b ldr r3, [r7, #4] 800e92e: 2b00 cmp r3, #0 800e930: d101 bne.n 800e936 { return HAL_ERROR; 800e932: 2301 movs r3, #1 800e934: e049 b.n 800e9ca assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800e936: 687b ldr r3, [r7, #4] 800e938: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800e93c: b2db uxtb r3, r3 800e93e: 2b00 cmp r3, #0 800e940: d106 bne.n 800e950 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800e942: 687b ldr r3, [r7, #4] 800e944: 2200 movs r2, #0 800e946: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800e94a: 6878 ldr r0, [r7, #4] 800e94c: f7f5 f85c bl 8003a08 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800e950: 687b ldr r3, [r7, #4] 800e952: 2202 movs r2, #2 800e954: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800e958: 687b ldr r3, [r7, #4] 800e95a: 681a ldr r2, [r3, #0] 800e95c: 687b ldr r3, [r7, #4] 800e95e: 3304 adds r3, #4 800e960: 4619 mov r1, r3 800e962: 4610 mov r0, r2 800e964: f001 f918 bl 800fb98 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800e968: 687b ldr r3, [r7, #4] 800e96a: 2201 movs r2, #1 800e96c: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800e970: 687b ldr r3, [r7, #4] 800e972: 2201 movs r2, #1 800e974: f883 203e strb.w r2, [r3, #62] @ 0x3e 800e978: 687b ldr r3, [r7, #4] 800e97a: 2201 movs r2, #1 800e97c: f883 203f strb.w r2, [r3, #63] @ 0x3f 800e980: 687b ldr r3, [r7, #4] 800e982: 2201 movs r2, #1 800e984: f883 2040 strb.w r2, [r3, #64] @ 0x40 800e988: 687b ldr r3, [r7, #4] 800e98a: 2201 movs r2, #1 800e98c: f883 2041 strb.w r2, [r3, #65] @ 0x41 800e990: 687b ldr r3, [r7, #4] 800e992: 2201 movs r2, #1 800e994: f883 2042 strb.w r2, [r3, #66] @ 0x42 800e998: 687b ldr r3, [r7, #4] 800e99a: 2201 movs r2, #1 800e99c: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800e9a0: 687b ldr r3, [r7, #4] 800e9a2: 2201 movs r2, #1 800e9a4: f883 2044 strb.w r2, [r3, #68] @ 0x44 800e9a8: 687b ldr r3, [r7, #4] 800e9aa: 2201 movs r2, #1 800e9ac: f883 2045 strb.w r2, [r3, #69] @ 0x45 800e9b0: 687b ldr r3, [r7, #4] 800e9b2: 2201 movs r2, #1 800e9b4: f883 2046 strb.w r2, [r3, #70] @ 0x46 800e9b8: 687b ldr r3, [r7, #4] 800e9ba: 2201 movs r2, #1 800e9bc: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800e9c0: 687b ldr r3, [r7, #4] 800e9c2: 2201 movs r2, #1 800e9c4: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800e9c8: 2300 movs r3, #0 } 800e9ca: 4618 mov r0, r3 800e9cc: 3708 adds r7, #8 800e9ce: 46bd mov sp, r7 800e9d0: bd80 pop {r7, pc} ... 0800e9d4 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 800e9d4: b480 push {r7} 800e9d6: b085 sub sp, #20 800e9d8: af00 add r7, sp, #0 800e9da: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800e9dc: 687b ldr r3, [r7, #4] 800e9de: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800e9e2: b2db uxtb r3, r3 800e9e4: 2b01 cmp r3, #1 800e9e6: d001 beq.n 800e9ec { return HAL_ERROR; 800e9e8: 2301 movs r3, #1 800e9ea: e04c b.n 800ea86 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800e9ec: 687b ldr r3, [r7, #4] 800e9ee: 2202 movs r2, #2 800e9f0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800e9f4: 687b ldr r3, [r7, #4] 800e9f6: 681b ldr r3, [r3, #0] 800e9f8: 4a26 ldr r2, [pc, #152] @ (800ea94 ) 800e9fa: 4293 cmp r3, r2 800e9fc: d022 beq.n 800ea44 800e9fe: 687b ldr r3, [r7, #4] 800ea00: 681b ldr r3, [r3, #0] 800ea02: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800ea06: d01d beq.n 800ea44 800ea08: 687b ldr r3, [r7, #4] 800ea0a: 681b ldr r3, [r3, #0] 800ea0c: 4a22 ldr r2, [pc, #136] @ (800ea98 ) 800ea0e: 4293 cmp r3, r2 800ea10: d018 beq.n 800ea44 800ea12: 687b ldr r3, [r7, #4] 800ea14: 681b ldr r3, [r3, #0] 800ea16: 4a21 ldr r2, [pc, #132] @ (800ea9c ) 800ea18: 4293 cmp r3, r2 800ea1a: d013 beq.n 800ea44 800ea1c: 687b ldr r3, [r7, #4] 800ea1e: 681b ldr r3, [r3, #0] 800ea20: 4a1f ldr r2, [pc, #124] @ (800eaa0 ) 800ea22: 4293 cmp r3, r2 800ea24: d00e beq.n 800ea44 800ea26: 687b ldr r3, [r7, #4] 800ea28: 681b ldr r3, [r3, #0] 800ea2a: 4a1e ldr r2, [pc, #120] @ (800eaa4 ) 800ea2c: 4293 cmp r3, r2 800ea2e: d009 beq.n 800ea44 800ea30: 687b ldr r3, [r7, #4] 800ea32: 681b ldr r3, [r3, #0] 800ea34: 4a1c ldr r2, [pc, #112] @ (800eaa8 ) 800ea36: 4293 cmp r3, r2 800ea38: d004 beq.n 800ea44 800ea3a: 687b ldr r3, [r7, #4] 800ea3c: 681b ldr r3, [r3, #0] 800ea3e: 4a1b ldr r2, [pc, #108] @ (800eaac ) 800ea40: 4293 cmp r3, r2 800ea42: d115 bne.n 800ea70 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800ea44: 687b ldr r3, [r7, #4] 800ea46: 681b ldr r3, [r3, #0] 800ea48: 689a ldr r2, [r3, #8] 800ea4a: 4b19 ldr r3, [pc, #100] @ (800eab0 ) 800ea4c: 4013 ands r3, r2 800ea4e: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ea50: 68fb ldr r3, [r7, #12] 800ea52: 2b06 cmp r3, #6 800ea54: d015 beq.n 800ea82 800ea56: 68fb ldr r3, [r7, #12] 800ea58: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800ea5c: d011 beq.n 800ea82 { __HAL_TIM_ENABLE(htim); 800ea5e: 687b ldr r3, [r7, #4] 800ea60: 681b ldr r3, [r3, #0] 800ea62: 681a ldr r2, [r3, #0] 800ea64: 687b ldr r3, [r7, #4] 800ea66: 681b ldr r3, [r3, #0] 800ea68: f042 0201 orr.w r2, r2, #1 800ea6c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ea6e: e008 b.n 800ea82 } } else { __HAL_TIM_ENABLE(htim); 800ea70: 687b ldr r3, [r7, #4] 800ea72: 681b ldr r3, [r3, #0] 800ea74: 681a ldr r2, [r3, #0] 800ea76: 687b ldr r3, [r7, #4] 800ea78: 681b ldr r3, [r3, #0] 800ea7a: f042 0201 orr.w r2, r2, #1 800ea7e: 601a str r2, [r3, #0] 800ea80: e000 b.n 800ea84 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ea82: bf00 nop } /* Return function status */ return HAL_OK; 800ea84: 2300 movs r3, #0 } 800ea86: 4618 mov r0, r3 800ea88: 3714 adds r7, #20 800ea8a: 46bd mov sp, r7 800ea8c: f85d 7b04 ldr.w r7, [sp], #4 800ea90: 4770 bx lr 800ea92: bf00 nop 800ea94: 40010000 .word 0x40010000 800ea98: 40000400 .word 0x40000400 800ea9c: 40000800 .word 0x40000800 800eaa0: 40000c00 .word 0x40000c00 800eaa4: 40010400 .word 0x40010400 800eaa8: 40001800 .word 0x40001800 800eaac: 40014000 .word 0x40014000 800eab0: 00010007 .word 0x00010007 0800eab4 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800eab4: b480 push {r7} 800eab6: b085 sub sp, #20 800eab8: af00 add r7, sp, #0 800eaba: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800eabc: 687b ldr r3, [r7, #4] 800eabe: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800eac2: b2db uxtb r3, r3 800eac4: 2b01 cmp r3, #1 800eac6: d001 beq.n 800eacc { return HAL_ERROR; 800eac8: 2301 movs r3, #1 800eaca: e054 b.n 800eb76 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800eacc: 687b ldr r3, [r7, #4] 800eace: 2202 movs r2, #2 800ead0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800ead4: 687b ldr r3, [r7, #4] 800ead6: 681b ldr r3, [r3, #0] 800ead8: 68da ldr r2, [r3, #12] 800eada: 687b ldr r3, [r7, #4] 800eadc: 681b ldr r3, [r3, #0] 800eade: f042 0201 orr.w r2, r2, #1 800eae2: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800eae4: 687b ldr r3, [r7, #4] 800eae6: 681b ldr r3, [r3, #0] 800eae8: 4a26 ldr r2, [pc, #152] @ (800eb84 ) 800eaea: 4293 cmp r3, r2 800eaec: d022 beq.n 800eb34 800eaee: 687b ldr r3, [r7, #4] 800eaf0: 681b ldr r3, [r3, #0] 800eaf2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800eaf6: d01d beq.n 800eb34 800eaf8: 687b ldr r3, [r7, #4] 800eafa: 681b ldr r3, [r3, #0] 800eafc: 4a22 ldr r2, [pc, #136] @ (800eb88 ) 800eafe: 4293 cmp r3, r2 800eb00: d018 beq.n 800eb34 800eb02: 687b ldr r3, [r7, #4] 800eb04: 681b ldr r3, [r3, #0] 800eb06: 4a21 ldr r2, [pc, #132] @ (800eb8c ) 800eb08: 4293 cmp r3, r2 800eb0a: d013 beq.n 800eb34 800eb0c: 687b ldr r3, [r7, #4] 800eb0e: 681b ldr r3, [r3, #0] 800eb10: 4a1f ldr r2, [pc, #124] @ (800eb90 ) 800eb12: 4293 cmp r3, r2 800eb14: d00e beq.n 800eb34 800eb16: 687b ldr r3, [r7, #4] 800eb18: 681b ldr r3, [r3, #0] 800eb1a: 4a1e ldr r2, [pc, #120] @ (800eb94 ) 800eb1c: 4293 cmp r3, r2 800eb1e: d009 beq.n 800eb34 800eb20: 687b ldr r3, [r7, #4] 800eb22: 681b ldr r3, [r3, #0] 800eb24: 4a1c ldr r2, [pc, #112] @ (800eb98 ) 800eb26: 4293 cmp r3, r2 800eb28: d004 beq.n 800eb34 800eb2a: 687b ldr r3, [r7, #4] 800eb2c: 681b ldr r3, [r3, #0] 800eb2e: 4a1b ldr r2, [pc, #108] @ (800eb9c ) 800eb30: 4293 cmp r3, r2 800eb32: d115 bne.n 800eb60 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800eb34: 687b ldr r3, [r7, #4] 800eb36: 681b ldr r3, [r3, #0] 800eb38: 689a ldr r2, [r3, #8] 800eb3a: 4b19 ldr r3, [pc, #100] @ (800eba0 ) 800eb3c: 4013 ands r3, r2 800eb3e: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800eb40: 68fb ldr r3, [r7, #12] 800eb42: 2b06 cmp r3, #6 800eb44: d015 beq.n 800eb72 800eb46: 68fb ldr r3, [r7, #12] 800eb48: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800eb4c: d011 beq.n 800eb72 { __HAL_TIM_ENABLE(htim); 800eb4e: 687b ldr r3, [r7, #4] 800eb50: 681b ldr r3, [r3, #0] 800eb52: 681a ldr r2, [r3, #0] 800eb54: 687b ldr r3, [r7, #4] 800eb56: 681b ldr r3, [r3, #0] 800eb58: f042 0201 orr.w r2, r2, #1 800eb5c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800eb5e: e008 b.n 800eb72 } } else { __HAL_TIM_ENABLE(htim); 800eb60: 687b ldr r3, [r7, #4] 800eb62: 681b ldr r3, [r3, #0] 800eb64: 681a ldr r2, [r3, #0] 800eb66: 687b ldr r3, [r7, #4] 800eb68: 681b ldr r3, [r3, #0] 800eb6a: f042 0201 orr.w r2, r2, #1 800eb6e: 601a str r2, [r3, #0] 800eb70: e000 b.n 800eb74 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800eb72: bf00 nop } /* Return function status */ return HAL_OK; 800eb74: 2300 movs r3, #0 } 800eb76: 4618 mov r0, r3 800eb78: 3714 adds r7, #20 800eb7a: 46bd mov sp, r7 800eb7c: f85d 7b04 ldr.w r7, [sp], #4 800eb80: 4770 bx lr 800eb82: bf00 nop 800eb84: 40010000 .word 0x40010000 800eb88: 40000400 .word 0x40000400 800eb8c: 40000800 .word 0x40000800 800eb90: 40000c00 .word 0x40000c00 800eb94: 40010400 .word 0x40010400 800eb98: 40001800 .word 0x40001800 800eb9c: 40014000 .word 0x40014000 800eba0: 00010007 .word 0x00010007 0800eba4 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800eba4: b580 push {r7, lr} 800eba6: b082 sub sp, #8 800eba8: af00 add r7, sp, #0 800ebaa: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800ebac: 687b ldr r3, [r7, #4] 800ebae: 2b00 cmp r3, #0 800ebb0: d101 bne.n 800ebb6 { return HAL_ERROR; 800ebb2: 2301 movs r3, #1 800ebb4: e049 b.n 800ec4a assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800ebb6: 687b ldr r3, [r7, #4] 800ebb8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800ebbc: b2db uxtb r3, r3 800ebbe: 2b00 cmp r3, #0 800ebc0: d106 bne.n 800ebd0 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800ebc2: 687b ldr r3, [r7, #4] 800ebc4: 2200 movs r2, #0 800ebc6: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800ebca: 6878 ldr r0, [r7, #4] 800ebcc: f7f4 fee2 bl 8003994 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800ebd0: 687b ldr r3, [r7, #4] 800ebd2: 2202 movs r2, #2 800ebd4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800ebd8: 687b ldr r3, [r7, #4] 800ebda: 681a ldr r2, [r3, #0] 800ebdc: 687b ldr r3, [r7, #4] 800ebde: 3304 adds r3, #4 800ebe0: 4619 mov r1, r3 800ebe2: 4610 mov r0, r2 800ebe4: f000 ffd8 bl 800fb98 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800ebe8: 687b ldr r3, [r7, #4] 800ebea: 2201 movs r2, #1 800ebec: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800ebf0: 687b ldr r3, [r7, #4] 800ebf2: 2201 movs r2, #1 800ebf4: f883 203e strb.w r2, [r3, #62] @ 0x3e 800ebf8: 687b ldr r3, [r7, #4] 800ebfa: 2201 movs r2, #1 800ebfc: f883 203f strb.w r2, [r3, #63] @ 0x3f 800ec00: 687b ldr r3, [r7, #4] 800ec02: 2201 movs r2, #1 800ec04: f883 2040 strb.w r2, [r3, #64] @ 0x40 800ec08: 687b ldr r3, [r7, #4] 800ec0a: 2201 movs r2, #1 800ec0c: f883 2041 strb.w r2, [r3, #65] @ 0x41 800ec10: 687b ldr r3, [r7, #4] 800ec12: 2201 movs r2, #1 800ec14: f883 2042 strb.w r2, [r3, #66] @ 0x42 800ec18: 687b ldr r3, [r7, #4] 800ec1a: 2201 movs r2, #1 800ec1c: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800ec20: 687b ldr r3, [r7, #4] 800ec22: 2201 movs r2, #1 800ec24: f883 2044 strb.w r2, [r3, #68] @ 0x44 800ec28: 687b ldr r3, [r7, #4] 800ec2a: 2201 movs r2, #1 800ec2c: f883 2045 strb.w r2, [r3, #69] @ 0x45 800ec30: 687b ldr r3, [r7, #4] 800ec32: 2201 movs r2, #1 800ec34: f883 2046 strb.w r2, [r3, #70] @ 0x46 800ec38: 687b ldr r3, [r7, #4] 800ec3a: 2201 movs r2, #1 800ec3c: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800ec40: 687b ldr r3, [r7, #4] 800ec42: 2201 movs r2, #1 800ec44: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800ec48: 2300 movs r3, #0 } 800ec4a: 4618 mov r0, r3 800ec4c: 3708 adds r7, #8 800ec4e: 46bd mov sp, r7 800ec50: bd80 pop {r7, pc} ... 0800ec54 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 800ec54: b580 push {r7, lr} 800ec56: b084 sub sp, #16 800ec58: af00 add r7, sp, #0 800ec5a: 6078 str r0, [r7, #4] 800ec5c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800ec5e: 683b ldr r3, [r7, #0] 800ec60: 2b00 cmp r3, #0 800ec62: d109 bne.n 800ec78 800ec64: 687b ldr r3, [r7, #4] 800ec66: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800ec6a: b2db uxtb r3, r3 800ec6c: 2b01 cmp r3, #1 800ec6e: bf14 ite ne 800ec70: 2301 movne r3, #1 800ec72: 2300 moveq r3, #0 800ec74: b2db uxtb r3, r3 800ec76: e03c b.n 800ecf2 800ec78: 683b ldr r3, [r7, #0] 800ec7a: 2b04 cmp r3, #4 800ec7c: d109 bne.n 800ec92 800ec7e: 687b ldr r3, [r7, #4] 800ec80: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800ec84: b2db uxtb r3, r3 800ec86: 2b01 cmp r3, #1 800ec88: bf14 ite ne 800ec8a: 2301 movne r3, #1 800ec8c: 2300 moveq r3, #0 800ec8e: b2db uxtb r3, r3 800ec90: e02f b.n 800ecf2 800ec92: 683b ldr r3, [r7, #0] 800ec94: 2b08 cmp r3, #8 800ec96: d109 bne.n 800ecac 800ec98: 687b ldr r3, [r7, #4] 800ec9a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800ec9e: b2db uxtb r3, r3 800eca0: 2b01 cmp r3, #1 800eca2: bf14 ite ne 800eca4: 2301 movne r3, #1 800eca6: 2300 moveq r3, #0 800eca8: b2db uxtb r3, r3 800ecaa: e022 b.n 800ecf2 800ecac: 683b ldr r3, [r7, #0] 800ecae: 2b0c cmp r3, #12 800ecb0: d109 bne.n 800ecc6 800ecb2: 687b ldr r3, [r7, #4] 800ecb4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800ecb8: b2db uxtb r3, r3 800ecba: 2b01 cmp r3, #1 800ecbc: bf14 ite ne 800ecbe: 2301 movne r3, #1 800ecc0: 2300 moveq r3, #0 800ecc2: b2db uxtb r3, r3 800ecc4: e015 b.n 800ecf2 800ecc6: 683b ldr r3, [r7, #0] 800ecc8: 2b10 cmp r3, #16 800ecca: d109 bne.n 800ece0 800eccc: 687b ldr r3, [r7, #4] 800ecce: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800ecd2: b2db uxtb r3, r3 800ecd4: 2b01 cmp r3, #1 800ecd6: bf14 ite ne 800ecd8: 2301 movne r3, #1 800ecda: 2300 moveq r3, #0 800ecdc: b2db uxtb r3, r3 800ecde: e008 b.n 800ecf2 800ece0: 687b ldr r3, [r7, #4] 800ece2: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800ece6: b2db uxtb r3, r3 800ece8: 2b01 cmp r3, #1 800ecea: bf14 ite ne 800ecec: 2301 movne r3, #1 800ecee: 2300 moveq r3, #0 800ecf0: b2db uxtb r3, r3 800ecf2: 2b00 cmp r3, #0 800ecf4: d001 beq.n 800ecfa { return HAL_ERROR; 800ecf6: 2301 movs r3, #1 800ecf8: e0a1 b.n 800ee3e } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800ecfa: 683b ldr r3, [r7, #0] 800ecfc: 2b00 cmp r3, #0 800ecfe: d104 bne.n 800ed0a 800ed00: 687b ldr r3, [r7, #4] 800ed02: 2202 movs r2, #2 800ed04: f883 203e strb.w r2, [r3, #62] @ 0x3e 800ed08: e023 b.n 800ed52 800ed0a: 683b ldr r3, [r7, #0] 800ed0c: 2b04 cmp r3, #4 800ed0e: d104 bne.n 800ed1a 800ed10: 687b ldr r3, [r7, #4] 800ed12: 2202 movs r2, #2 800ed14: f883 203f strb.w r2, [r3, #63] @ 0x3f 800ed18: e01b b.n 800ed52 800ed1a: 683b ldr r3, [r7, #0] 800ed1c: 2b08 cmp r3, #8 800ed1e: d104 bne.n 800ed2a 800ed20: 687b ldr r3, [r7, #4] 800ed22: 2202 movs r2, #2 800ed24: f883 2040 strb.w r2, [r3, #64] @ 0x40 800ed28: e013 b.n 800ed52 800ed2a: 683b ldr r3, [r7, #0] 800ed2c: 2b0c cmp r3, #12 800ed2e: d104 bne.n 800ed3a 800ed30: 687b ldr r3, [r7, #4] 800ed32: 2202 movs r2, #2 800ed34: f883 2041 strb.w r2, [r3, #65] @ 0x41 800ed38: e00b b.n 800ed52 800ed3a: 683b ldr r3, [r7, #0] 800ed3c: 2b10 cmp r3, #16 800ed3e: d104 bne.n 800ed4a 800ed40: 687b ldr r3, [r7, #4] 800ed42: 2202 movs r2, #2 800ed44: f883 2042 strb.w r2, [r3, #66] @ 0x42 800ed48: e003 b.n 800ed52 800ed4a: 687b ldr r3, [r7, #4] 800ed4c: 2202 movs r2, #2 800ed4e: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800ed52: 687b ldr r3, [r7, #4] 800ed54: 681b ldr r3, [r3, #0] 800ed56: 2201 movs r2, #1 800ed58: 6839 ldr r1, [r7, #0] 800ed5a: 4618 mov r0, r3 800ed5c: f001 fc60 bl 8010620 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800ed60: 687b ldr r3, [r7, #4] 800ed62: 681b ldr r3, [r3, #0] 800ed64: 4a38 ldr r2, [pc, #224] @ (800ee48 ) 800ed66: 4293 cmp r3, r2 800ed68: d013 beq.n 800ed92 800ed6a: 687b ldr r3, [r7, #4] 800ed6c: 681b ldr r3, [r3, #0] 800ed6e: 4a37 ldr r2, [pc, #220] @ (800ee4c ) 800ed70: 4293 cmp r3, r2 800ed72: d00e beq.n 800ed92 800ed74: 687b ldr r3, [r7, #4] 800ed76: 681b ldr r3, [r3, #0] 800ed78: 4a35 ldr r2, [pc, #212] @ (800ee50 ) 800ed7a: 4293 cmp r3, r2 800ed7c: d009 beq.n 800ed92 800ed7e: 687b ldr r3, [r7, #4] 800ed80: 681b ldr r3, [r3, #0] 800ed82: 4a34 ldr r2, [pc, #208] @ (800ee54 ) 800ed84: 4293 cmp r3, r2 800ed86: d004 beq.n 800ed92 800ed88: 687b ldr r3, [r7, #4] 800ed8a: 681b ldr r3, [r3, #0] 800ed8c: 4a32 ldr r2, [pc, #200] @ (800ee58 ) 800ed8e: 4293 cmp r3, r2 800ed90: d101 bne.n 800ed96 800ed92: 2301 movs r3, #1 800ed94: e000 b.n 800ed98 800ed96: 2300 movs r3, #0 800ed98: 2b00 cmp r3, #0 800ed9a: d007 beq.n 800edac { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800ed9c: 687b ldr r3, [r7, #4] 800ed9e: 681b ldr r3, [r3, #0] 800eda0: 6c5a ldr r2, [r3, #68] @ 0x44 800eda2: 687b ldr r3, [r7, #4] 800eda4: 681b ldr r3, [r3, #0] 800eda6: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800edaa: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800edac: 687b ldr r3, [r7, #4] 800edae: 681b ldr r3, [r3, #0] 800edb0: 4a25 ldr r2, [pc, #148] @ (800ee48 ) 800edb2: 4293 cmp r3, r2 800edb4: d022 beq.n 800edfc 800edb6: 687b ldr r3, [r7, #4] 800edb8: 681b ldr r3, [r3, #0] 800edba: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800edbe: d01d beq.n 800edfc 800edc0: 687b ldr r3, [r7, #4] 800edc2: 681b ldr r3, [r3, #0] 800edc4: 4a25 ldr r2, [pc, #148] @ (800ee5c ) 800edc6: 4293 cmp r3, r2 800edc8: d018 beq.n 800edfc 800edca: 687b ldr r3, [r7, #4] 800edcc: 681b ldr r3, [r3, #0] 800edce: 4a24 ldr r2, [pc, #144] @ (800ee60 ) 800edd0: 4293 cmp r3, r2 800edd2: d013 beq.n 800edfc 800edd4: 687b ldr r3, [r7, #4] 800edd6: 681b ldr r3, [r3, #0] 800edd8: 4a22 ldr r2, [pc, #136] @ (800ee64 ) 800edda: 4293 cmp r3, r2 800eddc: d00e beq.n 800edfc 800edde: 687b ldr r3, [r7, #4] 800ede0: 681b ldr r3, [r3, #0] 800ede2: 4a1a ldr r2, [pc, #104] @ (800ee4c ) 800ede4: 4293 cmp r3, r2 800ede6: d009 beq.n 800edfc 800ede8: 687b ldr r3, [r7, #4] 800edea: 681b ldr r3, [r3, #0] 800edec: 4a1e ldr r2, [pc, #120] @ (800ee68 ) 800edee: 4293 cmp r3, r2 800edf0: d004 beq.n 800edfc 800edf2: 687b ldr r3, [r7, #4] 800edf4: 681b ldr r3, [r3, #0] 800edf6: 4a16 ldr r2, [pc, #88] @ (800ee50 ) 800edf8: 4293 cmp r3, r2 800edfa: d115 bne.n 800ee28 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800edfc: 687b ldr r3, [r7, #4] 800edfe: 681b ldr r3, [r3, #0] 800ee00: 689a ldr r2, [r3, #8] 800ee02: 4b1a ldr r3, [pc, #104] @ (800ee6c ) 800ee04: 4013 ands r3, r2 800ee06: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ee08: 68fb ldr r3, [r7, #12] 800ee0a: 2b06 cmp r3, #6 800ee0c: d015 beq.n 800ee3a 800ee0e: 68fb ldr r3, [r7, #12] 800ee10: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800ee14: d011 beq.n 800ee3a { __HAL_TIM_ENABLE(htim); 800ee16: 687b ldr r3, [r7, #4] 800ee18: 681b ldr r3, [r3, #0] 800ee1a: 681a ldr r2, [r3, #0] 800ee1c: 687b ldr r3, [r7, #4] 800ee1e: 681b ldr r3, [r3, #0] 800ee20: f042 0201 orr.w r2, r2, #1 800ee24: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ee26: e008 b.n 800ee3a } } else { __HAL_TIM_ENABLE(htim); 800ee28: 687b ldr r3, [r7, #4] 800ee2a: 681b ldr r3, [r3, #0] 800ee2c: 681a ldr r2, [r3, #0] 800ee2e: 687b ldr r3, [r7, #4] 800ee30: 681b ldr r3, [r3, #0] 800ee32: f042 0201 orr.w r2, r2, #1 800ee36: 601a str r2, [r3, #0] 800ee38: e000 b.n 800ee3c if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800ee3a: bf00 nop } /* Return function status */ return HAL_OK; 800ee3c: 2300 movs r3, #0 } 800ee3e: 4618 mov r0, r3 800ee40: 3710 adds r7, #16 800ee42: 46bd mov sp, r7 800ee44: bd80 pop {r7, pc} 800ee46: bf00 nop 800ee48: 40010000 .word 0x40010000 800ee4c: 40010400 .word 0x40010400 800ee50: 40014000 .word 0x40014000 800ee54: 40014400 .word 0x40014400 800ee58: 40014800 .word 0x40014800 800ee5c: 40000400 .word 0x40000400 800ee60: 40000800 .word 0x40000800 800ee64: 40000c00 .word 0x40000c00 800ee68: 40001800 .word 0x40001800 800ee6c: 00010007 .word 0x00010007 0800ee70 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800ee70: b580 push {r7, lr} 800ee72: b082 sub sp, #8 800ee74: af00 add r7, sp, #0 800ee76: 6078 str r0, [r7, #4] 800ee78: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 800ee7a: 687b ldr r3, [r7, #4] 800ee7c: 681b ldr r3, [r3, #0] 800ee7e: 2200 movs r2, #0 800ee80: 6839 ldr r1, [r7, #0] 800ee82: 4618 mov r0, r3 800ee84: f001 fbcc bl 8010620 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800ee88: 687b ldr r3, [r7, #4] 800ee8a: 681b ldr r3, [r3, #0] 800ee8c: 4a3e ldr r2, [pc, #248] @ (800ef88 ) 800ee8e: 4293 cmp r3, r2 800ee90: d013 beq.n 800eeba 800ee92: 687b ldr r3, [r7, #4] 800ee94: 681b ldr r3, [r3, #0] 800ee96: 4a3d ldr r2, [pc, #244] @ (800ef8c ) 800ee98: 4293 cmp r3, r2 800ee9a: d00e beq.n 800eeba 800ee9c: 687b ldr r3, [r7, #4] 800ee9e: 681b ldr r3, [r3, #0] 800eea0: 4a3b ldr r2, [pc, #236] @ (800ef90 ) 800eea2: 4293 cmp r3, r2 800eea4: d009 beq.n 800eeba 800eea6: 687b ldr r3, [r7, #4] 800eea8: 681b ldr r3, [r3, #0] 800eeaa: 4a3a ldr r2, [pc, #232] @ (800ef94 ) 800eeac: 4293 cmp r3, r2 800eeae: d004 beq.n 800eeba 800eeb0: 687b ldr r3, [r7, #4] 800eeb2: 681b ldr r3, [r3, #0] 800eeb4: 4a38 ldr r2, [pc, #224] @ (800ef98 ) 800eeb6: 4293 cmp r3, r2 800eeb8: d101 bne.n 800eebe 800eeba: 2301 movs r3, #1 800eebc: e000 b.n 800eec0 800eebe: 2300 movs r3, #0 800eec0: 2b00 cmp r3, #0 800eec2: d017 beq.n 800eef4 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 800eec4: 687b ldr r3, [r7, #4] 800eec6: 681b ldr r3, [r3, #0] 800eec8: 6a1a ldr r2, [r3, #32] 800eeca: f241 1311 movw r3, #4369 @ 0x1111 800eece: 4013 ands r3, r2 800eed0: 2b00 cmp r3, #0 800eed2: d10f bne.n 800eef4 800eed4: 687b ldr r3, [r7, #4] 800eed6: 681b ldr r3, [r3, #0] 800eed8: 6a1a ldr r2, [r3, #32] 800eeda: f240 4344 movw r3, #1092 @ 0x444 800eede: 4013 ands r3, r2 800eee0: 2b00 cmp r3, #0 800eee2: d107 bne.n 800eef4 800eee4: 687b ldr r3, [r7, #4] 800eee6: 681b ldr r3, [r3, #0] 800eee8: 6c5a ldr r2, [r3, #68] @ 0x44 800eeea: 687b ldr r3, [r7, #4] 800eeec: 681b ldr r3, [r3, #0] 800eeee: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800eef2: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800eef4: 687b ldr r3, [r7, #4] 800eef6: 681b ldr r3, [r3, #0] 800eef8: 6a1a ldr r2, [r3, #32] 800eefa: f241 1311 movw r3, #4369 @ 0x1111 800eefe: 4013 ands r3, r2 800ef00: 2b00 cmp r3, #0 800ef02: d10f bne.n 800ef24 800ef04: 687b ldr r3, [r7, #4] 800ef06: 681b ldr r3, [r3, #0] 800ef08: 6a1a ldr r2, [r3, #32] 800ef0a: f240 4344 movw r3, #1092 @ 0x444 800ef0e: 4013 ands r3, r2 800ef10: 2b00 cmp r3, #0 800ef12: d107 bne.n 800ef24 800ef14: 687b ldr r3, [r7, #4] 800ef16: 681b ldr r3, [r3, #0] 800ef18: 681a ldr r2, [r3, #0] 800ef1a: 687b ldr r3, [r7, #4] 800ef1c: 681b ldr r3, [r3, #0] 800ef1e: f022 0201 bic.w r2, r2, #1 800ef22: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 800ef24: 683b ldr r3, [r7, #0] 800ef26: 2b00 cmp r3, #0 800ef28: d104 bne.n 800ef34 800ef2a: 687b ldr r3, [r7, #4] 800ef2c: 2201 movs r2, #1 800ef2e: f883 203e strb.w r2, [r3, #62] @ 0x3e 800ef32: e023 b.n 800ef7c 800ef34: 683b ldr r3, [r7, #0] 800ef36: 2b04 cmp r3, #4 800ef38: d104 bne.n 800ef44 800ef3a: 687b ldr r3, [r7, #4] 800ef3c: 2201 movs r2, #1 800ef3e: f883 203f strb.w r2, [r3, #63] @ 0x3f 800ef42: e01b b.n 800ef7c 800ef44: 683b ldr r3, [r7, #0] 800ef46: 2b08 cmp r3, #8 800ef48: d104 bne.n 800ef54 800ef4a: 687b ldr r3, [r7, #4] 800ef4c: 2201 movs r2, #1 800ef4e: f883 2040 strb.w r2, [r3, #64] @ 0x40 800ef52: e013 b.n 800ef7c 800ef54: 683b ldr r3, [r7, #0] 800ef56: 2b0c cmp r3, #12 800ef58: d104 bne.n 800ef64 800ef5a: 687b ldr r3, [r7, #4] 800ef5c: 2201 movs r2, #1 800ef5e: f883 2041 strb.w r2, [r3, #65] @ 0x41 800ef62: e00b b.n 800ef7c 800ef64: 683b ldr r3, [r7, #0] 800ef66: 2b10 cmp r3, #16 800ef68: d104 bne.n 800ef74 800ef6a: 687b ldr r3, [r7, #4] 800ef6c: 2201 movs r2, #1 800ef6e: f883 2042 strb.w r2, [r3, #66] @ 0x42 800ef72: e003 b.n 800ef7c 800ef74: 687b ldr r3, [r7, #4] 800ef76: 2201 movs r2, #1 800ef78: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Return function status */ return HAL_OK; 800ef7c: 2300 movs r3, #0 } 800ef7e: 4618 mov r0, r3 800ef80: 3708 adds r7, #8 800ef82: 46bd mov sp, r7 800ef84: bd80 pop {r7, pc} 800ef86: bf00 nop 800ef88: 40010000 .word 0x40010000 800ef8c: 40010400 .word 0x40010400 800ef90: 40014000 .word 0x40014000 800ef94: 40014400 .word 0x40014400 800ef98: 40014800 .word 0x40014800 0800ef9c : * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { 800ef9c: b580 push {r7, lr} 800ef9e: b082 sub sp, #8 800efa0: af00 add r7, sp, #0 800efa2: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800efa4: 687b ldr r3, [r7, #4] 800efa6: 2b00 cmp r3, #0 800efa8: d101 bne.n 800efae { return HAL_ERROR; 800efaa: 2301 movs r3, #1 800efac: e049 b.n 800f042 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800efae: 687b ldr r3, [r7, #4] 800efb0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800efb4: b2db uxtb r3, r3 800efb6: 2b00 cmp r3, #0 800efb8: d106 bne.n 800efc8 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800efba: 687b ldr r3, [r7, #4] 800efbc: 2200 movs r2, #0 800efbe: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); 800efc2: 6878 ldr r0, [r7, #4] 800efc4: f000 f841 bl 800f04a #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800efc8: 687b ldr r3, [r7, #4] 800efca: 2202 movs r2, #2 800efcc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800efd0: 687b ldr r3, [r7, #4] 800efd2: 681a ldr r2, [r3, #0] 800efd4: 687b ldr r3, [r7, #4] 800efd6: 3304 adds r3, #4 800efd8: 4619 mov r1, r3 800efda: 4610 mov r0, r2 800efdc: f000 fddc bl 800fb98 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800efe0: 687b ldr r3, [r7, #4] 800efe2: 2201 movs r2, #1 800efe4: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800efe8: 687b ldr r3, [r7, #4] 800efea: 2201 movs r2, #1 800efec: f883 203e strb.w r2, [r3, #62] @ 0x3e 800eff0: 687b ldr r3, [r7, #4] 800eff2: 2201 movs r2, #1 800eff4: f883 203f strb.w r2, [r3, #63] @ 0x3f 800eff8: 687b ldr r3, [r7, #4] 800effa: 2201 movs r2, #1 800effc: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f000: 687b ldr r3, [r7, #4] 800f002: 2201 movs r2, #1 800f004: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f008: 687b ldr r3, [r7, #4] 800f00a: 2201 movs r2, #1 800f00c: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f010: 687b ldr r3, [r7, #4] 800f012: 2201 movs r2, #1 800f014: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f018: 687b ldr r3, [r7, #4] 800f01a: 2201 movs r2, #1 800f01c: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f020: 687b ldr r3, [r7, #4] 800f022: 2201 movs r2, #1 800f024: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f028: 687b ldr r3, [r7, #4] 800f02a: 2201 movs r2, #1 800f02c: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f030: 687b ldr r3, [r7, #4] 800f032: 2201 movs r2, #1 800f034: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f038: 687b ldr r3, [r7, #4] 800f03a: 2201 movs r2, #1 800f03c: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f040: 2300 movs r3, #0 } 800f042: 4618 mov r0, r3 800f044: 3708 adds r7, #8 800f046: 46bd mov sp, r7 800f048: bd80 pop {r7, pc} 0800f04a : * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { 800f04a: b480 push {r7} 800f04c: b083 sub sp, #12 800f04e: af00 add r7, sp, #0 800f050: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } 800f052: bf00 nop 800f054: 370c adds r7, #12 800f056: 46bd mov sp, r7 800f058: f85d 7b04 ldr.w r7, [sp], #4 800f05c: 4770 bx lr ... 0800f060 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f060: b580 push {r7, lr} 800f062: b084 sub sp, #16 800f064: af00 add r7, sp, #0 800f066: 6078 str r0, [r7, #4] 800f068: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800f06a: 2300 movs r3, #0 800f06c: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800f06e: 683b ldr r3, [r7, #0] 800f070: 2b00 cmp r3, #0 800f072: d104 bne.n 800f07e 800f074: 687b ldr r3, [r7, #4] 800f076: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800f07a: b2db uxtb r3, r3 800f07c: e023 b.n 800f0c6 800f07e: 683b ldr r3, [r7, #0] 800f080: 2b04 cmp r3, #4 800f082: d104 bne.n 800f08e 800f084: 687b ldr r3, [r7, #4] 800f086: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800f08a: b2db uxtb r3, r3 800f08c: e01b b.n 800f0c6 800f08e: 683b ldr r3, [r7, #0] 800f090: 2b08 cmp r3, #8 800f092: d104 bne.n 800f09e 800f094: 687b ldr r3, [r7, #4] 800f096: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800f09a: b2db uxtb r3, r3 800f09c: e013 b.n 800f0c6 800f09e: 683b ldr r3, [r7, #0] 800f0a0: 2b0c cmp r3, #12 800f0a2: d104 bne.n 800f0ae 800f0a4: 687b ldr r3, [r7, #4] 800f0a6: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800f0aa: b2db uxtb r3, r3 800f0ac: e00b b.n 800f0c6 800f0ae: 683b ldr r3, [r7, #0] 800f0b0: 2b10 cmp r3, #16 800f0b2: d104 bne.n 800f0be 800f0b4: 687b ldr r3, [r7, #4] 800f0b6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800f0ba: b2db uxtb r3, r3 800f0bc: e003 b.n 800f0c6 800f0be: 687b ldr r3, [r7, #4] 800f0c0: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800f0c4: b2db uxtb r3, r3 800f0c6: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); 800f0c8: 683b ldr r3, [r7, #0] 800f0ca: 2b00 cmp r3, #0 800f0cc: d104 bne.n 800f0d8 800f0ce: 687b ldr r3, [r7, #4] 800f0d0: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800f0d4: b2db uxtb r3, r3 800f0d6: e013 b.n 800f100 800f0d8: 683b ldr r3, [r7, #0] 800f0da: 2b04 cmp r3, #4 800f0dc: d104 bne.n 800f0e8 800f0de: 687b ldr r3, [r7, #4] 800f0e0: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800f0e4: b2db uxtb r3, r3 800f0e6: e00b b.n 800f100 800f0e8: 683b ldr r3, [r7, #0] 800f0ea: 2b08 cmp r3, #8 800f0ec: d104 bne.n 800f0f8 800f0ee: 687b ldr r3, [r7, #4] 800f0f0: f893 3046 ldrb.w r3, [r3, #70] @ 0x46 800f0f4: b2db uxtb r3, r3 800f0f6: e003 b.n 800f100 800f0f8: 687b ldr r3, [r7, #4] 800f0fa: f893 3047 ldrb.w r3, [r3, #71] @ 0x47 800f0fe: b2db uxtb r3, r3 800f100: 737b strb r3, [r7, #13] /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) 800f102: 7bbb ldrb r3, [r7, #14] 800f104: 2b01 cmp r3, #1 800f106: d102 bne.n 800f10e || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) 800f108: 7b7b ldrb r3, [r7, #13] 800f10a: 2b01 cmp r3, #1 800f10c: d001 beq.n 800f112 { return HAL_ERROR; 800f10e: 2301 movs r3, #1 800f110: e0e2 b.n 800f2d8 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800f112: 683b ldr r3, [r7, #0] 800f114: 2b00 cmp r3, #0 800f116: d104 bne.n 800f122 800f118: 687b ldr r3, [r7, #4] 800f11a: 2202 movs r2, #2 800f11c: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f120: e023 b.n 800f16a 800f122: 683b ldr r3, [r7, #0] 800f124: 2b04 cmp r3, #4 800f126: d104 bne.n 800f132 800f128: 687b ldr r3, [r7, #4] 800f12a: 2202 movs r2, #2 800f12c: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f130: e01b b.n 800f16a 800f132: 683b ldr r3, [r7, #0] 800f134: 2b08 cmp r3, #8 800f136: d104 bne.n 800f142 800f138: 687b ldr r3, [r7, #4] 800f13a: 2202 movs r2, #2 800f13c: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f140: e013 b.n 800f16a 800f142: 683b ldr r3, [r7, #0] 800f144: 2b0c cmp r3, #12 800f146: d104 bne.n 800f152 800f148: 687b ldr r3, [r7, #4] 800f14a: 2202 movs r2, #2 800f14c: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f150: e00b b.n 800f16a 800f152: 683b ldr r3, [r7, #0] 800f154: 2b10 cmp r3, #16 800f156: d104 bne.n 800f162 800f158: 687b ldr r3, [r7, #4] 800f15a: 2202 movs r2, #2 800f15c: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f160: e003 b.n 800f16a 800f162: 687b ldr r3, [r7, #4] 800f164: 2202 movs r2, #2 800f166: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800f16a: 683b ldr r3, [r7, #0] 800f16c: 2b00 cmp r3, #0 800f16e: d104 bne.n 800f17a 800f170: 687b ldr r3, [r7, #4] 800f172: 2202 movs r2, #2 800f174: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f178: e013 b.n 800f1a2 800f17a: 683b ldr r3, [r7, #0] 800f17c: 2b04 cmp r3, #4 800f17e: d104 bne.n 800f18a 800f180: 687b ldr r3, [r7, #4] 800f182: 2202 movs r2, #2 800f184: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f188: e00b b.n 800f1a2 800f18a: 683b ldr r3, [r7, #0] 800f18c: 2b08 cmp r3, #8 800f18e: d104 bne.n 800f19a 800f190: 687b ldr r3, [r7, #4] 800f192: 2202 movs r2, #2 800f194: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f198: e003 b.n 800f1a2 800f19a: 687b ldr r3, [r7, #4] 800f19c: 2202 movs r2, #2 800f19e: f883 2047 strb.w r2, [r3, #71] @ 0x47 switch (Channel) 800f1a2: 683b ldr r3, [r7, #0] 800f1a4: 2b0c cmp r3, #12 800f1a6: d841 bhi.n 800f22c 800f1a8: a201 add r2, pc, #4 @ (adr r2, 800f1b0 ) 800f1aa: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f1ae: bf00 nop 800f1b0: 0800f1e5 .word 0x0800f1e5 800f1b4: 0800f22d .word 0x0800f22d 800f1b8: 0800f22d .word 0x0800f22d 800f1bc: 0800f22d .word 0x0800f22d 800f1c0: 0800f1f7 .word 0x0800f1f7 800f1c4: 0800f22d .word 0x0800f22d 800f1c8: 0800f22d .word 0x0800f22d 800f1cc: 0800f22d .word 0x0800f22d 800f1d0: 0800f209 .word 0x0800f209 800f1d4: 0800f22d .word 0x0800f22d 800f1d8: 0800f22d .word 0x0800f22d 800f1dc: 0800f22d .word 0x0800f22d 800f1e0: 0800f21b .word 0x0800f21b { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 800f1e4: 687b ldr r3, [r7, #4] 800f1e6: 681b ldr r3, [r3, #0] 800f1e8: 68da ldr r2, [r3, #12] 800f1ea: 687b ldr r3, [r7, #4] 800f1ec: 681b ldr r3, [r3, #0] 800f1ee: f042 0202 orr.w r2, r2, #2 800f1f2: 60da str r2, [r3, #12] break; 800f1f4: e01d b.n 800f232 } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 800f1f6: 687b ldr r3, [r7, #4] 800f1f8: 681b ldr r3, [r3, #0] 800f1fa: 68da ldr r2, [r3, #12] 800f1fc: 687b ldr r3, [r7, #4] 800f1fe: 681b ldr r3, [r3, #0] 800f200: f042 0204 orr.w r2, r2, #4 800f204: 60da str r2, [r3, #12] break; 800f206: e014 b.n 800f232 } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 800f208: 687b ldr r3, [r7, #4] 800f20a: 681b ldr r3, [r3, #0] 800f20c: 68da ldr r2, [r3, #12] 800f20e: 687b ldr r3, [r7, #4] 800f210: 681b ldr r3, [r3, #0] 800f212: f042 0208 orr.w r2, r2, #8 800f216: 60da str r2, [r3, #12] break; 800f218: e00b b.n 800f232 } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 800f21a: 687b ldr r3, [r7, #4] 800f21c: 681b ldr r3, [r3, #0] 800f21e: 68da ldr r2, [r3, #12] 800f220: 687b ldr r3, [r7, #4] 800f222: 681b ldr r3, [r3, #0] 800f224: f042 0210 orr.w r2, r2, #16 800f228: 60da str r2, [r3, #12] break; 800f22a: e002 b.n 800f232 } default: status = HAL_ERROR; 800f22c: 2301 movs r3, #1 800f22e: 73fb strb r3, [r7, #15] break; 800f230: bf00 nop } if (status == HAL_OK) 800f232: 7bfb ldrb r3, [r7, #15] 800f234: 2b00 cmp r3, #0 800f236: d14e bne.n 800f2d6 { /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800f238: 687b ldr r3, [r7, #4] 800f23a: 681b ldr r3, [r3, #0] 800f23c: 2201 movs r2, #1 800f23e: 6839 ldr r1, [r7, #0] 800f240: 4618 mov r0, r3 800f242: f001 f9ed bl 8010620 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f246: 687b ldr r3, [r7, #4] 800f248: 681b ldr r3, [r3, #0] 800f24a: 4a25 ldr r2, [pc, #148] @ (800f2e0 ) 800f24c: 4293 cmp r3, r2 800f24e: d022 beq.n 800f296 800f250: 687b ldr r3, [r7, #4] 800f252: 681b ldr r3, [r3, #0] 800f254: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f258: d01d beq.n 800f296 800f25a: 687b ldr r3, [r7, #4] 800f25c: 681b ldr r3, [r3, #0] 800f25e: 4a21 ldr r2, [pc, #132] @ (800f2e4 ) 800f260: 4293 cmp r3, r2 800f262: d018 beq.n 800f296 800f264: 687b ldr r3, [r7, #4] 800f266: 681b ldr r3, [r3, #0] 800f268: 4a1f ldr r2, [pc, #124] @ (800f2e8 ) 800f26a: 4293 cmp r3, r2 800f26c: d013 beq.n 800f296 800f26e: 687b ldr r3, [r7, #4] 800f270: 681b ldr r3, [r3, #0] 800f272: 4a1e ldr r2, [pc, #120] @ (800f2ec ) 800f274: 4293 cmp r3, r2 800f276: d00e beq.n 800f296 800f278: 687b ldr r3, [r7, #4] 800f27a: 681b ldr r3, [r3, #0] 800f27c: 4a1c ldr r2, [pc, #112] @ (800f2f0 ) 800f27e: 4293 cmp r3, r2 800f280: d009 beq.n 800f296 800f282: 687b ldr r3, [r7, #4] 800f284: 681b ldr r3, [r3, #0] 800f286: 4a1b ldr r2, [pc, #108] @ (800f2f4 ) 800f288: 4293 cmp r3, r2 800f28a: d004 beq.n 800f296 800f28c: 687b ldr r3, [r7, #4] 800f28e: 681b ldr r3, [r3, #0] 800f290: 4a19 ldr r2, [pc, #100] @ (800f2f8 ) 800f292: 4293 cmp r3, r2 800f294: d115 bne.n 800f2c2 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f296: 687b ldr r3, [r7, #4] 800f298: 681b ldr r3, [r3, #0] 800f29a: 689a ldr r2, [r3, #8] 800f29c: 4b17 ldr r3, [pc, #92] @ (800f2fc ) 800f29e: 4013 ands r3, r2 800f2a0: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f2a2: 68bb ldr r3, [r7, #8] 800f2a4: 2b06 cmp r3, #6 800f2a6: d015 beq.n 800f2d4 800f2a8: 68bb ldr r3, [r7, #8] 800f2aa: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f2ae: d011 beq.n 800f2d4 { __HAL_TIM_ENABLE(htim); 800f2b0: 687b ldr r3, [r7, #4] 800f2b2: 681b ldr r3, [r3, #0] 800f2b4: 681a ldr r2, [r3, #0] 800f2b6: 687b ldr r3, [r7, #4] 800f2b8: 681b ldr r3, [r3, #0] 800f2ba: f042 0201 orr.w r2, r2, #1 800f2be: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f2c0: e008 b.n 800f2d4 } } else { __HAL_TIM_ENABLE(htim); 800f2c2: 687b ldr r3, [r7, #4] 800f2c4: 681b ldr r3, [r3, #0] 800f2c6: 681a ldr r2, [r3, #0] 800f2c8: 687b ldr r3, [r7, #4] 800f2ca: 681b ldr r3, [r3, #0] 800f2cc: f042 0201 orr.w r2, r2, #1 800f2d0: 601a str r2, [r3, #0] 800f2d2: e000 b.n 800f2d6 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f2d4: bf00 nop } } /* Return function status */ return status; 800f2d6: 7bfb ldrb r3, [r7, #15] } 800f2d8: 4618 mov r0, r3 800f2da: 3710 adds r7, #16 800f2dc: 46bd mov sp, r7 800f2de: bd80 pop {r7, pc} 800f2e0: 40010000 .word 0x40010000 800f2e4: 40000400 .word 0x40000400 800f2e8: 40000800 .word 0x40000800 800f2ec: 40000c00 .word 0x40000c00 800f2f0: 40010400 .word 0x40010400 800f2f4: 40001800 .word 0x40001800 800f2f8: 40014000 .word 0x40014000 800f2fc: 00010007 .word 0x00010007 0800f300 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800f300: b580 push {r7, lr} 800f302: b084 sub sp, #16 800f304: af00 add r7, sp, #0 800f306: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800f308: 687b ldr r3, [r7, #4] 800f30a: 681b ldr r3, [r3, #0] 800f30c: 68db ldr r3, [r3, #12] 800f30e: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800f310: 687b ldr r3, [r7, #4] 800f312: 681b ldr r3, [r3, #0] 800f314: 691b ldr r3, [r3, #16] 800f316: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800f318: 68bb ldr r3, [r7, #8] 800f31a: f003 0302 and.w r3, r3, #2 800f31e: 2b00 cmp r3, #0 800f320: d020 beq.n 800f364 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800f322: 68fb ldr r3, [r7, #12] 800f324: f003 0302 and.w r3, r3, #2 800f328: 2b00 cmp r3, #0 800f32a: d01b beq.n 800f364 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800f32c: 687b ldr r3, [r7, #4] 800f32e: 681b ldr r3, [r3, #0] 800f330: f06f 0202 mvn.w r2, #2 800f334: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800f336: 687b ldr r3, [r7, #4] 800f338: 2201 movs r2, #1 800f33a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800f33c: 687b ldr r3, [r7, #4] 800f33e: 681b ldr r3, [r3, #0] 800f340: 699b ldr r3, [r3, #24] 800f342: f003 0303 and.w r3, r3, #3 800f346: 2b00 cmp r3, #0 800f348: d003 beq.n 800f352 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f34a: 6878 ldr r0, [r7, #4] 800f34c: f7f2 faf8 bl 8001940 800f350: e005 b.n 800f35e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f352: 6878 ldr r0, [r7, #4] 800f354: f000 fbc8 bl 800fae8 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f358: 6878 ldr r0, [r7, #4] 800f35a: f000 fbcf bl 800fafc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f35e: 687b ldr r3, [r7, #4] 800f360: 2200 movs r2, #0 800f362: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800f364: 68bb ldr r3, [r7, #8] 800f366: f003 0304 and.w r3, r3, #4 800f36a: 2b00 cmp r3, #0 800f36c: d020 beq.n 800f3b0 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800f36e: 68fb ldr r3, [r7, #12] 800f370: f003 0304 and.w r3, r3, #4 800f374: 2b00 cmp r3, #0 800f376: d01b beq.n 800f3b0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800f378: 687b ldr r3, [r7, #4] 800f37a: 681b ldr r3, [r3, #0] 800f37c: f06f 0204 mvn.w r2, #4 800f380: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800f382: 687b ldr r3, [r7, #4] 800f384: 2202 movs r2, #2 800f386: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800f388: 687b ldr r3, [r7, #4] 800f38a: 681b ldr r3, [r3, #0] 800f38c: 699b ldr r3, [r3, #24] 800f38e: f403 7340 and.w r3, r3, #768 @ 0x300 800f392: 2b00 cmp r3, #0 800f394: d003 beq.n 800f39e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f396: 6878 ldr r0, [r7, #4] 800f398: f7f2 fad2 bl 8001940 800f39c: e005 b.n 800f3aa { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f39e: 6878 ldr r0, [r7, #4] 800f3a0: f000 fba2 bl 800fae8 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f3a4: 6878 ldr r0, [r7, #4] 800f3a6: f000 fba9 bl 800fafc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f3aa: 687b ldr r3, [r7, #4] 800f3ac: 2200 movs r2, #0 800f3ae: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800f3b0: 68bb ldr r3, [r7, #8] 800f3b2: f003 0308 and.w r3, r3, #8 800f3b6: 2b00 cmp r3, #0 800f3b8: d020 beq.n 800f3fc { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800f3ba: 68fb ldr r3, [r7, #12] 800f3bc: f003 0308 and.w r3, r3, #8 800f3c0: 2b00 cmp r3, #0 800f3c2: d01b beq.n 800f3fc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800f3c4: 687b ldr r3, [r7, #4] 800f3c6: 681b ldr r3, [r3, #0] 800f3c8: f06f 0208 mvn.w r2, #8 800f3cc: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800f3ce: 687b ldr r3, [r7, #4] 800f3d0: 2204 movs r2, #4 800f3d2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800f3d4: 687b ldr r3, [r7, #4] 800f3d6: 681b ldr r3, [r3, #0] 800f3d8: 69db ldr r3, [r3, #28] 800f3da: f003 0303 and.w r3, r3, #3 800f3de: 2b00 cmp r3, #0 800f3e0: d003 beq.n 800f3ea { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f3e2: 6878 ldr r0, [r7, #4] 800f3e4: f7f2 faac bl 8001940 800f3e8: e005 b.n 800f3f6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f3ea: 6878 ldr r0, [r7, #4] 800f3ec: f000 fb7c bl 800fae8 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f3f0: 6878 ldr r0, [r7, #4] 800f3f2: f000 fb83 bl 800fafc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f3f6: 687b ldr r3, [r7, #4] 800f3f8: 2200 movs r2, #0 800f3fa: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800f3fc: 68bb ldr r3, [r7, #8] 800f3fe: f003 0310 and.w r3, r3, #16 800f402: 2b00 cmp r3, #0 800f404: d020 beq.n 800f448 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800f406: 68fb ldr r3, [r7, #12] 800f408: f003 0310 and.w r3, r3, #16 800f40c: 2b00 cmp r3, #0 800f40e: d01b beq.n 800f448 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800f410: 687b ldr r3, [r7, #4] 800f412: 681b ldr r3, [r3, #0] 800f414: f06f 0210 mvn.w r2, #16 800f418: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800f41a: 687b ldr r3, [r7, #4] 800f41c: 2208 movs r2, #8 800f41e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800f420: 687b ldr r3, [r7, #4] 800f422: 681b ldr r3, [r3, #0] 800f424: 69db ldr r3, [r3, #28] 800f426: f403 7340 and.w r3, r3, #768 @ 0x300 800f42a: 2b00 cmp r3, #0 800f42c: d003 beq.n 800f436 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800f42e: 6878 ldr r0, [r7, #4] 800f430: f7f2 fa86 bl 8001940 800f434: e005 b.n 800f442 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800f436: 6878 ldr r0, [r7, #4] 800f438: f000 fb56 bl 800fae8 HAL_TIM_PWM_PulseFinishedCallback(htim); 800f43c: 6878 ldr r0, [r7, #4] 800f43e: f000 fb5d bl 800fafc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800f442: 687b ldr r3, [r7, #4] 800f444: 2200 movs r2, #0 800f446: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800f448: 68bb ldr r3, [r7, #8] 800f44a: f003 0301 and.w r3, r3, #1 800f44e: 2b00 cmp r3, #0 800f450: d00c beq.n 800f46c { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800f452: 68fb ldr r3, [r7, #12] 800f454: f003 0301 and.w r3, r3, #1 800f458: 2b00 cmp r3, #0 800f45a: d007 beq.n 800f46c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800f45c: 687b ldr r3, [r7, #4] 800f45e: 681b ldr r3, [r3, #0] 800f460: f06f 0201 mvn.w r2, #1 800f464: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800f466: 6878 ldr r0, [r7, #4] 800f468: f7f2 fc74 bl 8001d54 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800f46c: 68bb ldr r3, [r7, #8] 800f46e: f003 0380 and.w r3, r3, #128 @ 0x80 800f472: 2b00 cmp r3, #0 800f474: d104 bne.n 800f480 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800f476: 68bb ldr r3, [r7, #8] 800f478: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800f47c: 2b00 cmp r3, #0 800f47e: d00c beq.n 800f49a { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800f480: 68fb ldr r3, [r7, #12] 800f482: f003 0380 and.w r3, r3, #128 @ 0x80 800f486: 2b00 cmp r3, #0 800f488: d007 beq.n 800f49a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800f48a: 687b ldr r3, [r7, #4] 800f48c: 681b ldr r3, [r3, #0] 800f48e: f46f 5202 mvn.w r2, #8320 @ 0x2080 800f492: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800f494: 6878 ldr r0, [r7, #4] 800f496: f001 f9ff bl 8010898 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800f49a: 68bb ldr r3, [r7, #8] 800f49c: f403 7380 and.w r3, r3, #256 @ 0x100 800f4a0: 2b00 cmp r3, #0 800f4a2: d00c beq.n 800f4be { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800f4a4: 68fb ldr r3, [r7, #12] 800f4a6: f003 0380 and.w r3, r3, #128 @ 0x80 800f4aa: 2b00 cmp r3, #0 800f4ac: d007 beq.n 800f4be { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800f4ae: 687b ldr r3, [r7, #4] 800f4b0: 681b ldr r3, [r3, #0] 800f4b2: f46f 7280 mvn.w r2, #256 @ 0x100 800f4b6: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800f4b8: 6878 ldr r0, [r7, #4] 800f4ba: f001 f9f7 bl 80108ac #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800f4be: 68bb ldr r3, [r7, #8] 800f4c0: f003 0340 and.w r3, r3, #64 @ 0x40 800f4c4: 2b00 cmp r3, #0 800f4c6: d00c beq.n 800f4e2 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800f4c8: 68fb ldr r3, [r7, #12] 800f4ca: f003 0340 and.w r3, r3, #64 @ 0x40 800f4ce: 2b00 cmp r3, #0 800f4d0: d007 beq.n 800f4e2 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800f4d2: 687b ldr r3, [r7, #4] 800f4d4: 681b ldr r3, [r3, #0] 800f4d6: f06f 0240 mvn.w r2, #64 @ 0x40 800f4da: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800f4dc: 6878 ldr r0, [r7, #4] 800f4de: f000 fb17 bl 800fb10 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800f4e2: 68bb ldr r3, [r7, #8] 800f4e4: f003 0320 and.w r3, r3, #32 800f4e8: 2b00 cmp r3, #0 800f4ea: d00c beq.n 800f506 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800f4ec: 68fb ldr r3, [r7, #12] 800f4ee: f003 0320 and.w r3, r3, #32 800f4f2: 2b00 cmp r3, #0 800f4f4: d007 beq.n 800f506 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800f4f6: 687b ldr r3, [r7, #4] 800f4f8: 681b ldr r3, [r3, #0] 800f4fa: f06f 0220 mvn.w r2, #32 800f4fe: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800f500: 6878 ldr r0, [r7, #4] 800f502: f001 f9bf bl 8010884 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 800f506: bf00 nop 800f508: 3710 adds r7, #16 800f50a: 46bd mov sp, r7 800f50c: bd80 pop {r7, pc} 0800f50e : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { 800f50e: b580 push {r7, lr} 800f510: b086 sub sp, #24 800f512: af00 add r7, sp, #0 800f514: 60f8 str r0, [r7, #12] 800f516: 60b9 str r1, [r7, #8] 800f518: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f51a: 2300 movs r3, #0 800f51c: 75fb strb r3, [r7, #23] assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); 800f51e: 68fb ldr r3, [r7, #12] 800f520: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800f524: 2b01 cmp r3, #1 800f526: d101 bne.n 800f52c 800f528: 2302 movs r3, #2 800f52a: e088 b.n 800f63e 800f52c: 68fb ldr r3, [r7, #12] 800f52e: 2201 movs r2, #1 800f530: f883 203c strb.w r2, [r3, #60] @ 0x3c if (Channel == TIM_CHANNEL_1) 800f534: 687b ldr r3, [r7, #4] 800f536: 2b00 cmp r3, #0 800f538: d11b bne.n 800f572 { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, 800f53a: 68fb ldr r3, [r7, #12] 800f53c: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 800f53e: 68bb ldr r3, [r7, #8] 800f540: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 800f542: 68bb ldr r3, [r7, #8] 800f544: 685a ldr r2, [r3, #4] sConfig->ICFilter); 800f546: 68bb ldr r3, [r7, #8] 800f548: 68db ldr r3, [r3, #12] TIM_TI1_SetConfig(htim->Instance, 800f54a: f000 fea1 bl 8010290 /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 800f54e: 68fb ldr r3, [r7, #12] 800f550: 681b ldr r3, [r3, #0] 800f552: 699a ldr r2, [r3, #24] 800f554: 68fb ldr r3, [r7, #12] 800f556: 681b ldr r3, [r3, #0] 800f558: f022 020c bic.w r2, r2, #12 800f55c: 619a str r2, [r3, #24] /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; 800f55e: 68fb ldr r3, [r7, #12] 800f560: 681b ldr r3, [r3, #0] 800f562: 6999 ldr r1, [r3, #24] 800f564: 68bb ldr r3, [r7, #8] 800f566: 689a ldr r2, [r3, #8] 800f568: 68fb ldr r3, [r7, #12] 800f56a: 681b ldr r3, [r3, #0] 800f56c: 430a orrs r2, r1 800f56e: 619a str r2, [r3, #24] 800f570: e060 b.n 800f634 } else if (Channel == TIM_CHANNEL_2) 800f572: 687b ldr r3, [r7, #4] 800f574: 2b04 cmp r3, #4 800f576: d11c bne.n 800f5b2 { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, 800f578: 68fb ldr r3, [r7, #12] 800f57a: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 800f57c: 68bb ldr r3, [r7, #8] 800f57e: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 800f580: 68bb ldr r3, [r7, #8] 800f582: 685a ldr r2, [r3, #4] sConfig->ICFilter); 800f584: 68bb ldr r3, [r7, #8] 800f586: 68db ldr r3, [r3, #12] TIM_TI2_SetConfig(htim->Instance, 800f588: f000 ff25 bl 80103d6 /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 800f58c: 68fb ldr r3, [r7, #12] 800f58e: 681b ldr r3, [r3, #0] 800f590: 699a ldr r2, [r3, #24] 800f592: 68fb ldr r3, [r7, #12] 800f594: 681b ldr r3, [r3, #0] 800f596: f422 6240 bic.w r2, r2, #3072 @ 0xc00 800f59a: 619a str r2, [r3, #24] /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); 800f59c: 68fb ldr r3, [r7, #12] 800f59e: 681b ldr r3, [r3, #0] 800f5a0: 6999 ldr r1, [r3, #24] 800f5a2: 68bb ldr r3, [r7, #8] 800f5a4: 689b ldr r3, [r3, #8] 800f5a6: 021a lsls r2, r3, #8 800f5a8: 68fb ldr r3, [r7, #12] 800f5aa: 681b ldr r3, [r3, #0] 800f5ac: 430a orrs r2, r1 800f5ae: 619a str r2, [r3, #24] 800f5b0: e040 b.n 800f634 } else if (Channel == TIM_CHANNEL_3) 800f5b2: 687b ldr r3, [r7, #4] 800f5b4: 2b08 cmp r3, #8 800f5b6: d11b bne.n 800f5f0 { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, 800f5b8: 68fb ldr r3, [r7, #12] 800f5ba: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 800f5bc: 68bb ldr r3, [r7, #8] 800f5be: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 800f5c0: 68bb ldr r3, [r7, #8] 800f5c2: 685a ldr r2, [r3, #4] sConfig->ICFilter); 800f5c4: 68bb ldr r3, [r7, #8] 800f5c6: 68db ldr r3, [r3, #12] TIM_TI3_SetConfig(htim->Instance, 800f5c8: f000 ff72 bl 80104b0 /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 800f5cc: 68fb ldr r3, [r7, #12] 800f5ce: 681b ldr r3, [r3, #0] 800f5d0: 69da ldr r2, [r3, #28] 800f5d2: 68fb ldr r3, [r7, #12] 800f5d4: 681b ldr r3, [r3, #0] 800f5d6: f022 020c bic.w r2, r2, #12 800f5da: 61da str r2, [r3, #28] /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; 800f5dc: 68fb ldr r3, [r7, #12] 800f5de: 681b ldr r3, [r3, #0] 800f5e0: 69d9 ldr r1, [r3, #28] 800f5e2: 68bb ldr r3, [r7, #8] 800f5e4: 689a ldr r2, [r3, #8] 800f5e6: 68fb ldr r3, [r7, #12] 800f5e8: 681b ldr r3, [r3, #0] 800f5ea: 430a orrs r2, r1 800f5ec: 61da str r2, [r3, #28] 800f5ee: e021 b.n 800f634 } else if (Channel == TIM_CHANNEL_4) 800f5f0: 687b ldr r3, [r7, #4] 800f5f2: 2b0c cmp r3, #12 800f5f4: d11c bne.n 800f630 { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, 800f5f6: 68fb ldr r3, [r7, #12] 800f5f8: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 800f5fa: 68bb ldr r3, [r7, #8] 800f5fc: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 800f5fe: 68bb ldr r3, [r7, #8] 800f600: 685a ldr r2, [r3, #4] sConfig->ICFilter); 800f602: 68bb ldr r3, [r7, #8] 800f604: 68db ldr r3, [r3, #12] TIM_TI4_SetConfig(htim->Instance, 800f606: f000 ff8f bl 8010528 /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 800f60a: 68fb ldr r3, [r7, #12] 800f60c: 681b ldr r3, [r3, #0] 800f60e: 69da ldr r2, [r3, #28] 800f610: 68fb ldr r3, [r7, #12] 800f612: 681b ldr r3, [r3, #0] 800f614: f422 6240 bic.w r2, r2, #3072 @ 0xc00 800f618: 61da str r2, [r3, #28] /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); 800f61a: 68fb ldr r3, [r7, #12] 800f61c: 681b ldr r3, [r3, #0] 800f61e: 69d9 ldr r1, [r3, #28] 800f620: 68bb ldr r3, [r7, #8] 800f622: 689b ldr r3, [r3, #8] 800f624: 021a lsls r2, r3, #8 800f626: 68fb ldr r3, [r7, #12] 800f628: 681b ldr r3, [r3, #0] 800f62a: 430a orrs r2, r1 800f62c: 61da str r2, [r3, #28] 800f62e: e001 b.n 800f634 } else { status = HAL_ERROR; 800f630: 2301 movs r3, #1 800f632: 75fb strb r3, [r7, #23] } __HAL_UNLOCK(htim); 800f634: 68fb ldr r3, [r7, #12] 800f636: 2200 movs r2, #0 800f638: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800f63c: 7dfb ldrb r3, [r7, #23] } 800f63e: 4618 mov r0, r3 800f640: 3718 adds r7, #24 800f642: 46bd mov sp, r7 800f644: bd80 pop {r7, pc} ... 0800f648 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 800f648: b580 push {r7, lr} 800f64a: b086 sub sp, #24 800f64c: af00 add r7, sp, #0 800f64e: 60f8 str r0, [r7, #12] 800f650: 60b9 str r1, [r7, #8] 800f652: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800f654: 2300 movs r3, #0 800f656: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 800f658: 68fb ldr r3, [r7, #12] 800f65a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800f65e: 2b01 cmp r3, #1 800f660: d101 bne.n 800f666 800f662: 2302 movs r3, #2 800f664: e0ff b.n 800f866 800f666: 68fb ldr r3, [r7, #12] 800f668: 2201 movs r2, #1 800f66a: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 800f66e: 687b ldr r3, [r7, #4] 800f670: 2b14 cmp r3, #20 800f672: f200 80f0 bhi.w 800f856 800f676: a201 add r2, pc, #4 @ (adr r2, 800f67c ) 800f678: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800f67c: 0800f6d1 .word 0x0800f6d1 800f680: 0800f857 .word 0x0800f857 800f684: 0800f857 .word 0x0800f857 800f688: 0800f857 .word 0x0800f857 800f68c: 0800f711 .word 0x0800f711 800f690: 0800f857 .word 0x0800f857 800f694: 0800f857 .word 0x0800f857 800f698: 0800f857 .word 0x0800f857 800f69c: 0800f753 .word 0x0800f753 800f6a0: 0800f857 .word 0x0800f857 800f6a4: 0800f857 .word 0x0800f857 800f6a8: 0800f857 .word 0x0800f857 800f6ac: 0800f793 .word 0x0800f793 800f6b0: 0800f857 .word 0x0800f857 800f6b4: 0800f857 .word 0x0800f857 800f6b8: 0800f857 .word 0x0800f857 800f6bc: 0800f7d5 .word 0x0800f7d5 800f6c0: 0800f857 .word 0x0800f857 800f6c4: 0800f857 .word 0x0800f857 800f6c8: 0800f857 .word 0x0800f857 800f6cc: 0800f815 .word 0x0800f815 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 800f6d0: 68fb ldr r3, [r7, #12] 800f6d2: 681b ldr r3, [r3, #0] 800f6d4: 68b9 ldr r1, [r7, #8] 800f6d6: 4618 mov r0, r3 800f6d8: f000 fb04 bl 800fce4 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 800f6dc: 68fb ldr r3, [r7, #12] 800f6de: 681b ldr r3, [r3, #0] 800f6e0: 699a ldr r2, [r3, #24] 800f6e2: 68fb ldr r3, [r7, #12] 800f6e4: 681b ldr r3, [r3, #0] 800f6e6: f042 0208 orr.w r2, r2, #8 800f6ea: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 800f6ec: 68fb ldr r3, [r7, #12] 800f6ee: 681b ldr r3, [r3, #0] 800f6f0: 699a ldr r2, [r3, #24] 800f6f2: 68fb ldr r3, [r7, #12] 800f6f4: 681b ldr r3, [r3, #0] 800f6f6: f022 0204 bic.w r2, r2, #4 800f6fa: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 800f6fc: 68fb ldr r3, [r7, #12] 800f6fe: 681b ldr r3, [r3, #0] 800f700: 6999 ldr r1, [r3, #24] 800f702: 68bb ldr r3, [r7, #8] 800f704: 691a ldr r2, [r3, #16] 800f706: 68fb ldr r3, [r7, #12] 800f708: 681b ldr r3, [r3, #0] 800f70a: 430a orrs r2, r1 800f70c: 619a str r2, [r3, #24] break; 800f70e: e0a5 b.n 800f85c { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 800f710: 68fb ldr r3, [r7, #12] 800f712: 681b ldr r3, [r3, #0] 800f714: 68b9 ldr r1, [r7, #8] 800f716: 4618 mov r0, r3 800f718: f000 fb74 bl 800fe04 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 800f71c: 68fb ldr r3, [r7, #12] 800f71e: 681b ldr r3, [r3, #0] 800f720: 699a ldr r2, [r3, #24] 800f722: 68fb ldr r3, [r7, #12] 800f724: 681b ldr r3, [r3, #0] 800f726: f442 6200 orr.w r2, r2, #2048 @ 0x800 800f72a: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 800f72c: 68fb ldr r3, [r7, #12] 800f72e: 681b ldr r3, [r3, #0] 800f730: 699a ldr r2, [r3, #24] 800f732: 68fb ldr r3, [r7, #12] 800f734: 681b ldr r3, [r3, #0] 800f736: f422 6280 bic.w r2, r2, #1024 @ 0x400 800f73a: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 800f73c: 68fb ldr r3, [r7, #12] 800f73e: 681b ldr r3, [r3, #0] 800f740: 6999 ldr r1, [r3, #24] 800f742: 68bb ldr r3, [r7, #8] 800f744: 691b ldr r3, [r3, #16] 800f746: 021a lsls r2, r3, #8 800f748: 68fb ldr r3, [r7, #12] 800f74a: 681b ldr r3, [r3, #0] 800f74c: 430a orrs r2, r1 800f74e: 619a str r2, [r3, #24] break; 800f750: e084 b.n 800f85c { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 800f752: 68fb ldr r3, [r7, #12] 800f754: 681b ldr r3, [r3, #0] 800f756: 68b9 ldr r1, [r7, #8] 800f758: 4618 mov r0, r3 800f75a: f000 fbdd bl 800ff18 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 800f75e: 68fb ldr r3, [r7, #12] 800f760: 681b ldr r3, [r3, #0] 800f762: 69da ldr r2, [r3, #28] 800f764: 68fb ldr r3, [r7, #12] 800f766: 681b ldr r3, [r3, #0] 800f768: f042 0208 orr.w r2, r2, #8 800f76c: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 800f76e: 68fb ldr r3, [r7, #12] 800f770: 681b ldr r3, [r3, #0] 800f772: 69da ldr r2, [r3, #28] 800f774: 68fb ldr r3, [r7, #12] 800f776: 681b ldr r3, [r3, #0] 800f778: f022 0204 bic.w r2, r2, #4 800f77c: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 800f77e: 68fb ldr r3, [r7, #12] 800f780: 681b ldr r3, [r3, #0] 800f782: 69d9 ldr r1, [r3, #28] 800f784: 68bb ldr r3, [r7, #8] 800f786: 691a ldr r2, [r3, #16] 800f788: 68fb ldr r3, [r7, #12] 800f78a: 681b ldr r3, [r3, #0] 800f78c: 430a orrs r2, r1 800f78e: 61da str r2, [r3, #28] break; 800f790: e064 b.n 800f85c { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 800f792: 68fb ldr r3, [r7, #12] 800f794: 681b ldr r3, [r3, #0] 800f796: 68b9 ldr r1, [r7, #8] 800f798: 4618 mov r0, r3 800f79a: f000 fc45 bl 8010028 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 800f79e: 68fb ldr r3, [r7, #12] 800f7a0: 681b ldr r3, [r3, #0] 800f7a2: 69da ldr r2, [r3, #28] 800f7a4: 68fb ldr r3, [r7, #12] 800f7a6: 681b ldr r3, [r3, #0] 800f7a8: f442 6200 orr.w r2, r2, #2048 @ 0x800 800f7ac: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 800f7ae: 68fb ldr r3, [r7, #12] 800f7b0: 681b ldr r3, [r3, #0] 800f7b2: 69da ldr r2, [r3, #28] 800f7b4: 68fb ldr r3, [r7, #12] 800f7b6: 681b ldr r3, [r3, #0] 800f7b8: f422 6280 bic.w r2, r2, #1024 @ 0x400 800f7bc: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 800f7be: 68fb ldr r3, [r7, #12] 800f7c0: 681b ldr r3, [r3, #0] 800f7c2: 69d9 ldr r1, [r3, #28] 800f7c4: 68bb ldr r3, [r7, #8] 800f7c6: 691b ldr r3, [r3, #16] 800f7c8: 021a lsls r2, r3, #8 800f7ca: 68fb ldr r3, [r7, #12] 800f7cc: 681b ldr r3, [r3, #0] 800f7ce: 430a orrs r2, r1 800f7d0: 61da str r2, [r3, #28] break; 800f7d2: e043 b.n 800f85c { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 800f7d4: 68fb ldr r3, [r7, #12] 800f7d6: 681b ldr r3, [r3, #0] 800f7d8: 68b9 ldr r1, [r7, #8] 800f7da: 4618 mov r0, r3 800f7dc: f000 fc8e bl 80100fc /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 800f7e0: 68fb ldr r3, [r7, #12] 800f7e2: 681b ldr r3, [r3, #0] 800f7e4: 6d5a ldr r2, [r3, #84] @ 0x54 800f7e6: 68fb ldr r3, [r7, #12] 800f7e8: 681b ldr r3, [r3, #0] 800f7ea: f042 0208 orr.w r2, r2, #8 800f7ee: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 800f7f0: 68fb ldr r3, [r7, #12] 800f7f2: 681b ldr r3, [r3, #0] 800f7f4: 6d5a ldr r2, [r3, #84] @ 0x54 800f7f6: 68fb ldr r3, [r7, #12] 800f7f8: 681b ldr r3, [r3, #0] 800f7fa: f022 0204 bic.w r2, r2, #4 800f7fe: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 800f800: 68fb ldr r3, [r7, #12] 800f802: 681b ldr r3, [r3, #0] 800f804: 6d59 ldr r1, [r3, #84] @ 0x54 800f806: 68bb ldr r3, [r7, #8] 800f808: 691a ldr r2, [r3, #16] 800f80a: 68fb ldr r3, [r7, #12] 800f80c: 681b ldr r3, [r3, #0] 800f80e: 430a orrs r2, r1 800f810: 655a str r2, [r3, #84] @ 0x54 break; 800f812: e023 b.n 800f85c { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 800f814: 68fb ldr r3, [r7, #12] 800f816: 681b ldr r3, [r3, #0] 800f818: 68b9 ldr r1, [r7, #8] 800f81a: 4618 mov r0, r3 800f81c: f000 fcd2 bl 80101c4 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 800f820: 68fb ldr r3, [r7, #12] 800f822: 681b ldr r3, [r3, #0] 800f824: 6d5a ldr r2, [r3, #84] @ 0x54 800f826: 68fb ldr r3, [r7, #12] 800f828: 681b ldr r3, [r3, #0] 800f82a: f442 6200 orr.w r2, r2, #2048 @ 0x800 800f82e: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 800f830: 68fb ldr r3, [r7, #12] 800f832: 681b ldr r3, [r3, #0] 800f834: 6d5a ldr r2, [r3, #84] @ 0x54 800f836: 68fb ldr r3, [r7, #12] 800f838: 681b ldr r3, [r3, #0] 800f83a: f422 6280 bic.w r2, r2, #1024 @ 0x400 800f83e: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 800f840: 68fb ldr r3, [r7, #12] 800f842: 681b ldr r3, [r3, #0] 800f844: 6d59 ldr r1, [r3, #84] @ 0x54 800f846: 68bb ldr r3, [r7, #8] 800f848: 691b ldr r3, [r3, #16] 800f84a: 021a lsls r2, r3, #8 800f84c: 68fb ldr r3, [r7, #12] 800f84e: 681b ldr r3, [r3, #0] 800f850: 430a orrs r2, r1 800f852: 655a str r2, [r3, #84] @ 0x54 break; 800f854: e002 b.n 800f85c } default: status = HAL_ERROR; 800f856: 2301 movs r3, #1 800f858: 75fb strb r3, [r7, #23] break; 800f85a: bf00 nop } __HAL_UNLOCK(htim); 800f85c: 68fb ldr r3, [r7, #12] 800f85e: 2200 movs r2, #0 800f860: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800f864: 7dfb ldrb r3, [r7, #23] } 800f866: 4618 mov r0, r3 800f868: 3718 adds r7, #24 800f86a: 46bd mov sp, r7 800f86c: bd80 pop {r7, pc} 800f86e: bf00 nop 0800f870 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 800f870: b580 push {r7, lr} 800f872: b084 sub sp, #16 800f874: af00 add r7, sp, #0 800f876: 6078 str r0, [r7, #4] 800f878: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800f87a: 2300 movs r3, #0 800f87c: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800f87e: 687b ldr r3, [r7, #4] 800f880: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800f884: 2b01 cmp r3, #1 800f886: d101 bne.n 800f88c 800f888: 2302 movs r3, #2 800f88a: e0dc b.n 800fa46 800f88c: 687b ldr r3, [r7, #4] 800f88e: 2201 movs r2, #1 800f890: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 800f894: 687b ldr r3, [r7, #4] 800f896: 2202 movs r2, #2 800f898: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 800f89c: 687b ldr r3, [r7, #4] 800f89e: 681b ldr r3, [r3, #0] 800f8a0: 689b ldr r3, [r3, #8] 800f8a2: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800f8a4: 68ba ldr r2, [r7, #8] 800f8a6: 4b6a ldr r3, [pc, #424] @ (800fa50 ) 800f8a8: 4013 ands r3, r2 800f8aa: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800f8ac: 68bb ldr r3, [r7, #8] 800f8ae: f423 437f bic.w r3, r3, #65280 @ 0xff00 800f8b2: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 800f8b4: 687b ldr r3, [r7, #4] 800f8b6: 681b ldr r3, [r3, #0] 800f8b8: 68ba ldr r2, [r7, #8] 800f8ba: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800f8bc: 683b ldr r3, [r7, #0] 800f8be: 681b ldr r3, [r3, #0] 800f8c0: 4a64 ldr r2, [pc, #400] @ (800fa54 ) 800f8c2: 4293 cmp r3, r2 800f8c4: f000 80a9 beq.w 800fa1a 800f8c8: 4a62 ldr r2, [pc, #392] @ (800fa54 ) 800f8ca: 4293 cmp r3, r2 800f8cc: f200 80ae bhi.w 800fa2c 800f8d0: 4a61 ldr r2, [pc, #388] @ (800fa58 ) 800f8d2: 4293 cmp r3, r2 800f8d4: f000 80a1 beq.w 800fa1a 800f8d8: 4a5f ldr r2, [pc, #380] @ (800fa58 ) 800f8da: 4293 cmp r3, r2 800f8dc: f200 80a6 bhi.w 800fa2c 800f8e0: 4a5e ldr r2, [pc, #376] @ (800fa5c ) 800f8e2: 4293 cmp r3, r2 800f8e4: f000 8099 beq.w 800fa1a 800f8e8: 4a5c ldr r2, [pc, #368] @ (800fa5c ) 800f8ea: 4293 cmp r3, r2 800f8ec: f200 809e bhi.w 800fa2c 800f8f0: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 800f8f4: f000 8091 beq.w 800fa1a 800f8f8: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 800f8fc: f200 8096 bhi.w 800fa2c 800f900: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800f904: f000 8089 beq.w 800fa1a 800f908: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800f90c: f200 808e bhi.w 800fa2c 800f910: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800f914: d03e beq.n 800f994 800f916: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800f91a: f200 8087 bhi.w 800fa2c 800f91e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800f922: f000 8086 beq.w 800fa32 800f926: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800f92a: d87f bhi.n 800fa2c 800f92c: 2b70 cmp r3, #112 @ 0x70 800f92e: d01a beq.n 800f966 800f930: 2b70 cmp r3, #112 @ 0x70 800f932: d87b bhi.n 800fa2c 800f934: 2b60 cmp r3, #96 @ 0x60 800f936: d050 beq.n 800f9da 800f938: 2b60 cmp r3, #96 @ 0x60 800f93a: d877 bhi.n 800fa2c 800f93c: 2b50 cmp r3, #80 @ 0x50 800f93e: d03c beq.n 800f9ba 800f940: 2b50 cmp r3, #80 @ 0x50 800f942: d873 bhi.n 800fa2c 800f944: 2b40 cmp r3, #64 @ 0x40 800f946: d058 beq.n 800f9fa 800f948: 2b40 cmp r3, #64 @ 0x40 800f94a: d86f bhi.n 800fa2c 800f94c: 2b30 cmp r3, #48 @ 0x30 800f94e: d064 beq.n 800fa1a 800f950: 2b30 cmp r3, #48 @ 0x30 800f952: d86b bhi.n 800fa2c 800f954: 2b20 cmp r3, #32 800f956: d060 beq.n 800fa1a 800f958: 2b20 cmp r3, #32 800f95a: d867 bhi.n 800fa2c 800f95c: 2b00 cmp r3, #0 800f95e: d05c beq.n 800fa1a 800f960: 2b10 cmp r3, #16 800f962: d05a beq.n 800fa1a 800f964: e062 b.n 800fa2c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800f966: 687b ldr r3, [r7, #4] 800f968: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800f96a: 683b ldr r3, [r7, #0] 800f96c: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800f96e: 683b ldr r3, [r7, #0] 800f970: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800f972: 683b ldr r3, [r7, #0] 800f974: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800f976: f000 fe33 bl 80105e0 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 800f97a: 687b ldr r3, [r7, #4] 800f97c: 681b ldr r3, [r3, #0] 800f97e: 689b ldr r3, [r3, #8] 800f980: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 800f982: 68bb ldr r3, [r7, #8] 800f984: f043 0377 orr.w r3, r3, #119 @ 0x77 800f988: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 800f98a: 687b ldr r3, [r7, #4] 800f98c: 681b ldr r3, [r3, #0] 800f98e: 68ba ldr r2, [r7, #8] 800f990: 609a str r2, [r3, #8] break; 800f992: e04f b.n 800fa34 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800f994: 687b ldr r3, [r7, #4] 800f996: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 800f998: 683b ldr r3, [r7, #0] 800f99a: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 800f99c: 683b ldr r3, [r7, #0] 800f99e: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800f9a0: 683b ldr r3, [r7, #0] 800f9a2: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800f9a4: f000 fe1c bl 80105e0 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 800f9a8: 687b ldr r3, [r7, #4] 800f9aa: 681b ldr r3, [r3, #0] 800f9ac: 689a ldr r2, [r3, #8] 800f9ae: 687b ldr r3, [r7, #4] 800f9b0: 681b ldr r3, [r3, #0] 800f9b2: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800f9b6: 609a str r2, [r3, #8] break; 800f9b8: e03c b.n 800fa34 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800f9ba: 687b ldr r3, [r7, #4] 800f9bc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800f9be: 683b ldr r3, [r7, #0] 800f9c0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800f9c2: 683b ldr r3, [r7, #0] 800f9c4: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800f9c6: 461a mov r2, r3 800f9c8: f000 fcd6 bl 8010378 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 800f9cc: 687b ldr r3, [r7, #4] 800f9ce: 681b ldr r3, [r3, #0] 800f9d0: 2150 movs r1, #80 @ 0x50 800f9d2: 4618 mov r0, r3 800f9d4: f000 fde6 bl 80105a4 break; 800f9d8: e02c b.n 800fa34 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 800f9da: 687b ldr r3, [r7, #4] 800f9dc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800f9de: 683b ldr r3, [r7, #0] 800f9e0: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800f9e2: 683b ldr r3, [r7, #0] 800f9e4: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 800f9e6: 461a mov r2, r3 800f9e8: f000 fd32 bl 8010450 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800f9ec: 687b ldr r3, [r7, #4] 800f9ee: 681b ldr r3, [r3, #0] 800f9f0: 2160 movs r1, #96 @ 0x60 800f9f2: 4618 mov r0, r3 800f9f4: f000 fdd6 bl 80105a4 break; 800f9f8: e01c b.n 800fa34 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800f9fa: 687b ldr r3, [r7, #4] 800f9fc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800f9fe: 683b ldr r3, [r7, #0] 800fa00: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800fa02: 683b ldr r3, [r7, #0] 800fa04: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800fa06: 461a mov r2, r3 800fa08: f000 fcb6 bl 8010378 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800fa0c: 687b ldr r3, [r7, #4] 800fa0e: 681b ldr r3, [r3, #0] 800fa10: 2140 movs r1, #64 @ 0x40 800fa12: 4618 mov r0, r3 800fa14: f000 fdc6 bl 80105a4 break; 800fa18: e00c b.n 800fa34 case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800fa1a: 687b ldr r3, [r7, #4] 800fa1c: 681a ldr r2, [r3, #0] 800fa1e: 683b ldr r3, [r7, #0] 800fa20: 681b ldr r3, [r3, #0] 800fa22: 4619 mov r1, r3 800fa24: 4610 mov r0, r2 800fa26: f000 fdbd bl 80105a4 break; 800fa2a: e003 b.n 800fa34 } default: status = HAL_ERROR; 800fa2c: 2301 movs r3, #1 800fa2e: 73fb strb r3, [r7, #15] break; 800fa30: e000 b.n 800fa34 break; 800fa32: bf00 nop } htim->State = HAL_TIM_STATE_READY; 800fa34: 687b ldr r3, [r7, #4] 800fa36: 2201 movs r2, #1 800fa38: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800fa3c: 687b ldr r3, [r7, #4] 800fa3e: 2200 movs r2, #0 800fa40: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 800fa44: 7bfb ldrb r3, [r7, #15] } 800fa46: 4618 mov r0, r3 800fa48: 3710 adds r7, #16 800fa4a: 46bd mov sp, r7 800fa4c: bd80 pop {r7, pc} 800fa4e: bf00 nop 800fa50: ffceff88 .word 0xffceff88 800fa54: 00100040 .word 0x00100040 800fa58: 00100030 .word 0x00100030 800fa5c: 00100020 .word 0x00100020 0800fa60 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { 800fa60: b480 push {r7} 800fa62: b085 sub sp, #20 800fa64: af00 add r7, sp, #0 800fa66: 6078 str r0, [r7, #4] 800fa68: 6039 str r1, [r7, #0] uint32_t tmpreg = 0U; 800fa6a: 2300 movs r3, #0 800fa6c: 60fb str r3, [r7, #12] switch (Channel) 800fa6e: 683b ldr r3, [r7, #0] 800fa70: 2b0c cmp r3, #12 800fa72: d831 bhi.n 800fad8 800fa74: a201 add r2, pc, #4 @ (adr r2, 800fa7c ) 800fa76: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800fa7a: bf00 nop 800fa7c: 0800fab1 .word 0x0800fab1 800fa80: 0800fad9 .word 0x0800fad9 800fa84: 0800fad9 .word 0x0800fad9 800fa88: 0800fad9 .word 0x0800fad9 800fa8c: 0800fabb .word 0x0800fabb 800fa90: 0800fad9 .word 0x0800fad9 800fa94: 0800fad9 .word 0x0800fad9 800fa98: 0800fad9 .word 0x0800fad9 800fa9c: 0800fac5 .word 0x0800fac5 800faa0: 0800fad9 .word 0x0800fad9 800faa4: 0800fad9 .word 0x0800fad9 800faa8: 0800fad9 .word 0x0800fad9 800faac: 0800facf .word 0x0800facf { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; 800fab0: 687b ldr r3, [r7, #4] 800fab2: 681b ldr r3, [r3, #0] 800fab4: 6b5b ldr r3, [r3, #52] @ 0x34 800fab6: 60fb str r3, [r7, #12] break; 800fab8: e00f b.n 800fada { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; 800faba: 687b ldr r3, [r7, #4] 800fabc: 681b ldr r3, [r3, #0] 800fabe: 6b9b ldr r3, [r3, #56] @ 0x38 800fac0: 60fb str r3, [r7, #12] break; 800fac2: e00a b.n 800fada { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; 800fac4: 687b ldr r3, [r7, #4] 800fac6: 681b ldr r3, [r3, #0] 800fac8: 6bdb ldr r3, [r3, #60] @ 0x3c 800faca: 60fb str r3, [r7, #12] break; 800facc: e005 b.n 800fada { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; 800face: 687b ldr r3, [r7, #4] 800fad0: 681b ldr r3, [r3, #0] 800fad2: 6c1b ldr r3, [r3, #64] @ 0x40 800fad4: 60fb str r3, [r7, #12] break; 800fad6: e000 b.n 800fada } default: break; 800fad8: bf00 nop } return tmpreg; 800fada: 68fb ldr r3, [r7, #12] } 800fadc: 4618 mov r0, r3 800fade: 3714 adds r7, #20 800fae0: 46bd mov sp, r7 800fae2: f85d 7b04 ldr.w r7, [sp], #4 800fae6: 4770 bx lr 0800fae8 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 800fae8: b480 push {r7} 800faea: b083 sub sp, #12 800faec: af00 add r7, sp, #0 800faee: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 800faf0: bf00 nop 800faf2: 370c adds r7, #12 800faf4: 46bd mov sp, r7 800faf6: f85d 7b04 ldr.w r7, [sp], #4 800fafa: 4770 bx lr 0800fafc : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800fafc: b480 push {r7} 800fafe: b083 sub sp, #12 800fb00: af00 add r7, sp, #0 800fb02: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 800fb04: bf00 nop 800fb06: 370c adds r7, #12 800fb08: 46bd mov sp, r7 800fb0a: f85d 7b04 ldr.w r7, [sp], #4 800fb0e: 4770 bx lr 0800fb10 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 800fb10: b480 push {r7} 800fb12: b083 sub sp, #12 800fb14: af00 add r7, sp, #0 800fb16: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800fb18: bf00 nop 800fb1a: 370c adds r7, #12 800fb1c: 46bd mov sp, r7 800fb1e: f85d 7b04 ldr.w r7, [sp], #4 800fb22: 4770 bx lr 0800fb24 : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 800fb24: b480 push {r7} 800fb26: b085 sub sp, #20 800fb28: af00 add r7, sp, #0 800fb2a: 6078 str r0, [r7, #4] 800fb2c: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800fb2e: 683b ldr r3, [r7, #0] 800fb30: 2b00 cmp r3, #0 800fb32: d104 bne.n 800fb3e 800fb34: 687b ldr r3, [r7, #4] 800fb36: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800fb3a: b2db uxtb r3, r3 800fb3c: e023 b.n 800fb86 800fb3e: 683b ldr r3, [r7, #0] 800fb40: 2b04 cmp r3, #4 800fb42: d104 bne.n 800fb4e 800fb44: 687b ldr r3, [r7, #4] 800fb46: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800fb4a: b2db uxtb r3, r3 800fb4c: e01b b.n 800fb86 800fb4e: 683b ldr r3, [r7, #0] 800fb50: 2b08 cmp r3, #8 800fb52: d104 bne.n 800fb5e 800fb54: 687b ldr r3, [r7, #4] 800fb56: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800fb5a: b2db uxtb r3, r3 800fb5c: e013 b.n 800fb86 800fb5e: 683b ldr r3, [r7, #0] 800fb60: 2b0c cmp r3, #12 800fb62: d104 bne.n 800fb6e 800fb64: 687b ldr r3, [r7, #4] 800fb66: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800fb6a: b2db uxtb r3, r3 800fb6c: e00b b.n 800fb86 800fb6e: 683b ldr r3, [r7, #0] 800fb70: 2b10 cmp r3, #16 800fb72: d104 bne.n 800fb7e 800fb74: 687b ldr r3, [r7, #4] 800fb76: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800fb7a: b2db uxtb r3, r3 800fb7c: e003 b.n 800fb86 800fb7e: 687b ldr r3, [r7, #4] 800fb80: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800fb84: b2db uxtb r3, r3 800fb86: 73fb strb r3, [r7, #15] return channel_state; 800fb88: 7bfb ldrb r3, [r7, #15] } 800fb8a: 4618 mov r0, r3 800fb8c: 3714 adds r7, #20 800fb8e: 46bd mov sp, r7 800fb90: f85d 7b04 ldr.w r7, [sp], #4 800fb94: 4770 bx lr ... 0800fb98 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 800fb98: b480 push {r7} 800fb9a: b085 sub sp, #20 800fb9c: af00 add r7, sp, #0 800fb9e: 6078 str r0, [r7, #4] 800fba0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800fba2: 687b ldr r3, [r7, #4] 800fba4: 681b ldr r3, [r3, #0] 800fba6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 800fba8: 687b ldr r3, [r7, #4] 800fbaa: 4a46 ldr r2, [pc, #280] @ (800fcc4 ) 800fbac: 4293 cmp r3, r2 800fbae: d013 beq.n 800fbd8 800fbb0: 687b ldr r3, [r7, #4] 800fbb2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fbb6: d00f beq.n 800fbd8 800fbb8: 687b ldr r3, [r7, #4] 800fbba: 4a43 ldr r2, [pc, #268] @ (800fcc8 ) 800fbbc: 4293 cmp r3, r2 800fbbe: d00b beq.n 800fbd8 800fbc0: 687b ldr r3, [r7, #4] 800fbc2: 4a42 ldr r2, [pc, #264] @ (800fccc ) 800fbc4: 4293 cmp r3, r2 800fbc6: d007 beq.n 800fbd8 800fbc8: 687b ldr r3, [r7, #4] 800fbca: 4a41 ldr r2, [pc, #260] @ (800fcd0 ) 800fbcc: 4293 cmp r3, r2 800fbce: d003 beq.n 800fbd8 800fbd0: 687b ldr r3, [r7, #4] 800fbd2: 4a40 ldr r2, [pc, #256] @ (800fcd4 ) 800fbd4: 4293 cmp r3, r2 800fbd6: d108 bne.n 800fbea { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 800fbd8: 68fb ldr r3, [r7, #12] 800fbda: f023 0370 bic.w r3, r3, #112 @ 0x70 800fbde: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 800fbe0: 683b ldr r3, [r7, #0] 800fbe2: 685b ldr r3, [r3, #4] 800fbe4: 68fa ldr r2, [r7, #12] 800fbe6: 4313 orrs r3, r2 800fbe8: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800fbea: 687b ldr r3, [r7, #4] 800fbec: 4a35 ldr r2, [pc, #212] @ (800fcc4 ) 800fbee: 4293 cmp r3, r2 800fbf0: d01f beq.n 800fc32 800fbf2: 687b ldr r3, [r7, #4] 800fbf4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fbf8: d01b beq.n 800fc32 800fbfa: 687b ldr r3, [r7, #4] 800fbfc: 4a32 ldr r2, [pc, #200] @ (800fcc8 ) 800fbfe: 4293 cmp r3, r2 800fc00: d017 beq.n 800fc32 800fc02: 687b ldr r3, [r7, #4] 800fc04: 4a31 ldr r2, [pc, #196] @ (800fccc ) 800fc06: 4293 cmp r3, r2 800fc08: d013 beq.n 800fc32 800fc0a: 687b ldr r3, [r7, #4] 800fc0c: 4a30 ldr r2, [pc, #192] @ (800fcd0 ) 800fc0e: 4293 cmp r3, r2 800fc10: d00f beq.n 800fc32 800fc12: 687b ldr r3, [r7, #4] 800fc14: 4a2f ldr r2, [pc, #188] @ (800fcd4 ) 800fc16: 4293 cmp r3, r2 800fc18: d00b beq.n 800fc32 800fc1a: 687b ldr r3, [r7, #4] 800fc1c: 4a2e ldr r2, [pc, #184] @ (800fcd8 ) 800fc1e: 4293 cmp r3, r2 800fc20: d007 beq.n 800fc32 800fc22: 687b ldr r3, [r7, #4] 800fc24: 4a2d ldr r2, [pc, #180] @ (800fcdc ) 800fc26: 4293 cmp r3, r2 800fc28: d003 beq.n 800fc32 800fc2a: 687b ldr r3, [r7, #4] 800fc2c: 4a2c ldr r2, [pc, #176] @ (800fce0 ) 800fc2e: 4293 cmp r3, r2 800fc30: d108 bne.n 800fc44 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 800fc32: 68fb ldr r3, [r7, #12] 800fc34: f423 7340 bic.w r3, r3, #768 @ 0x300 800fc38: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800fc3a: 683b ldr r3, [r7, #0] 800fc3c: 68db ldr r3, [r3, #12] 800fc3e: 68fa ldr r2, [r7, #12] 800fc40: 4313 orrs r3, r2 800fc42: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 800fc44: 68fb ldr r3, [r7, #12] 800fc46: f023 0280 bic.w r2, r3, #128 @ 0x80 800fc4a: 683b ldr r3, [r7, #0] 800fc4c: 695b ldr r3, [r3, #20] 800fc4e: 4313 orrs r3, r2 800fc50: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 800fc52: 687b ldr r3, [r7, #4] 800fc54: 68fa ldr r2, [r7, #12] 800fc56: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 800fc58: 683b ldr r3, [r7, #0] 800fc5a: 689a ldr r2, [r3, #8] 800fc5c: 687b ldr r3, [r7, #4] 800fc5e: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 800fc60: 683b ldr r3, [r7, #0] 800fc62: 681a ldr r2, [r3, #0] 800fc64: 687b ldr r3, [r7, #4] 800fc66: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 800fc68: 687b ldr r3, [r7, #4] 800fc6a: 4a16 ldr r2, [pc, #88] @ (800fcc4 ) 800fc6c: 4293 cmp r3, r2 800fc6e: d00f beq.n 800fc90 800fc70: 687b ldr r3, [r7, #4] 800fc72: 4a18 ldr r2, [pc, #96] @ (800fcd4 ) 800fc74: 4293 cmp r3, r2 800fc76: d00b beq.n 800fc90 800fc78: 687b ldr r3, [r7, #4] 800fc7a: 4a17 ldr r2, [pc, #92] @ (800fcd8 ) 800fc7c: 4293 cmp r3, r2 800fc7e: d007 beq.n 800fc90 800fc80: 687b ldr r3, [r7, #4] 800fc82: 4a16 ldr r2, [pc, #88] @ (800fcdc ) 800fc84: 4293 cmp r3, r2 800fc86: d003 beq.n 800fc90 800fc88: 687b ldr r3, [r7, #4] 800fc8a: 4a15 ldr r2, [pc, #84] @ (800fce0 ) 800fc8c: 4293 cmp r3, r2 800fc8e: d103 bne.n 800fc98 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 800fc90: 683b ldr r3, [r7, #0] 800fc92: 691a ldr r2, [r3, #16] 800fc94: 687b ldr r3, [r7, #4] 800fc96: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 800fc98: 687b ldr r3, [r7, #4] 800fc9a: 2201 movs r2, #1 800fc9c: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 800fc9e: 687b ldr r3, [r7, #4] 800fca0: 691b ldr r3, [r3, #16] 800fca2: f003 0301 and.w r3, r3, #1 800fca6: 2b01 cmp r3, #1 800fca8: d105 bne.n 800fcb6 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 800fcaa: 687b ldr r3, [r7, #4] 800fcac: 691b ldr r3, [r3, #16] 800fcae: f023 0201 bic.w r2, r3, #1 800fcb2: 687b ldr r3, [r7, #4] 800fcb4: 611a str r2, [r3, #16] } } 800fcb6: bf00 nop 800fcb8: 3714 adds r7, #20 800fcba: 46bd mov sp, r7 800fcbc: f85d 7b04 ldr.w r7, [sp], #4 800fcc0: 4770 bx lr 800fcc2: bf00 nop 800fcc4: 40010000 .word 0x40010000 800fcc8: 40000400 .word 0x40000400 800fccc: 40000800 .word 0x40000800 800fcd0: 40000c00 .word 0x40000c00 800fcd4: 40010400 .word 0x40010400 800fcd8: 40014000 .word 0x40014000 800fcdc: 40014400 .word 0x40014400 800fce0: 40014800 .word 0x40014800 0800fce4 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800fce4: b480 push {r7} 800fce6: b087 sub sp, #28 800fce8: af00 add r7, sp, #0 800fcea: 6078 str r0, [r7, #4] 800fcec: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800fcee: 687b ldr r3, [r7, #4] 800fcf0: 6a1b ldr r3, [r3, #32] 800fcf2: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 800fcf4: 687b ldr r3, [r7, #4] 800fcf6: 6a1b ldr r3, [r3, #32] 800fcf8: f023 0201 bic.w r2, r3, #1 800fcfc: 687b ldr r3, [r7, #4] 800fcfe: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800fd00: 687b ldr r3, [r7, #4] 800fd02: 685b ldr r3, [r3, #4] 800fd04: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800fd06: 687b ldr r3, [r7, #4] 800fd08: 699b ldr r3, [r3, #24] 800fd0a: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800fd0c: 68fa ldr r2, [r7, #12] 800fd0e: 4b37 ldr r3, [pc, #220] @ (800fdec ) 800fd10: 4013 ands r3, r2 800fd12: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 800fd14: 68fb ldr r3, [r7, #12] 800fd16: f023 0303 bic.w r3, r3, #3 800fd1a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800fd1c: 683b ldr r3, [r7, #0] 800fd1e: 681b ldr r3, [r3, #0] 800fd20: 68fa ldr r2, [r7, #12] 800fd22: 4313 orrs r3, r2 800fd24: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 800fd26: 697b ldr r3, [r7, #20] 800fd28: f023 0302 bic.w r3, r3, #2 800fd2c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800fd2e: 683b ldr r3, [r7, #0] 800fd30: 689b ldr r3, [r3, #8] 800fd32: 697a ldr r2, [r7, #20] 800fd34: 4313 orrs r3, r2 800fd36: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 800fd38: 687b ldr r3, [r7, #4] 800fd3a: 4a2d ldr r2, [pc, #180] @ (800fdf0 ) 800fd3c: 4293 cmp r3, r2 800fd3e: d00f beq.n 800fd60 800fd40: 687b ldr r3, [r7, #4] 800fd42: 4a2c ldr r2, [pc, #176] @ (800fdf4 ) 800fd44: 4293 cmp r3, r2 800fd46: d00b beq.n 800fd60 800fd48: 687b ldr r3, [r7, #4] 800fd4a: 4a2b ldr r2, [pc, #172] @ (800fdf8 ) 800fd4c: 4293 cmp r3, r2 800fd4e: d007 beq.n 800fd60 800fd50: 687b ldr r3, [r7, #4] 800fd52: 4a2a ldr r2, [pc, #168] @ (800fdfc ) 800fd54: 4293 cmp r3, r2 800fd56: d003 beq.n 800fd60 800fd58: 687b ldr r3, [r7, #4] 800fd5a: 4a29 ldr r2, [pc, #164] @ (800fe00 ) 800fd5c: 4293 cmp r3, r2 800fd5e: d10c bne.n 800fd7a { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 800fd60: 697b ldr r3, [r7, #20] 800fd62: f023 0308 bic.w r3, r3, #8 800fd66: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 800fd68: 683b ldr r3, [r7, #0] 800fd6a: 68db ldr r3, [r3, #12] 800fd6c: 697a ldr r2, [r7, #20] 800fd6e: 4313 orrs r3, r2 800fd70: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 800fd72: 697b ldr r3, [r7, #20] 800fd74: f023 0304 bic.w r3, r3, #4 800fd78: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800fd7a: 687b ldr r3, [r7, #4] 800fd7c: 4a1c ldr r2, [pc, #112] @ (800fdf0 ) 800fd7e: 4293 cmp r3, r2 800fd80: d00f beq.n 800fda2 800fd82: 687b ldr r3, [r7, #4] 800fd84: 4a1b ldr r2, [pc, #108] @ (800fdf4 ) 800fd86: 4293 cmp r3, r2 800fd88: d00b beq.n 800fda2 800fd8a: 687b ldr r3, [r7, #4] 800fd8c: 4a1a ldr r2, [pc, #104] @ (800fdf8 ) 800fd8e: 4293 cmp r3, r2 800fd90: d007 beq.n 800fda2 800fd92: 687b ldr r3, [r7, #4] 800fd94: 4a19 ldr r2, [pc, #100] @ (800fdfc ) 800fd96: 4293 cmp r3, r2 800fd98: d003 beq.n 800fda2 800fd9a: 687b ldr r3, [r7, #4] 800fd9c: 4a18 ldr r2, [pc, #96] @ (800fe00 ) 800fd9e: 4293 cmp r3, r2 800fda0: d111 bne.n 800fdc6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 800fda2: 693b ldr r3, [r7, #16] 800fda4: f423 7380 bic.w r3, r3, #256 @ 0x100 800fda8: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 800fdaa: 693b ldr r3, [r7, #16] 800fdac: f423 7300 bic.w r3, r3, #512 @ 0x200 800fdb0: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 800fdb2: 683b ldr r3, [r7, #0] 800fdb4: 695b ldr r3, [r3, #20] 800fdb6: 693a ldr r2, [r7, #16] 800fdb8: 4313 orrs r3, r2 800fdba: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 800fdbc: 683b ldr r3, [r7, #0] 800fdbe: 699b ldr r3, [r3, #24] 800fdc0: 693a ldr r2, [r7, #16] 800fdc2: 4313 orrs r3, r2 800fdc4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800fdc6: 687b ldr r3, [r7, #4] 800fdc8: 693a ldr r2, [r7, #16] 800fdca: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800fdcc: 687b ldr r3, [r7, #4] 800fdce: 68fa ldr r2, [r7, #12] 800fdd0: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 800fdd2: 683b ldr r3, [r7, #0] 800fdd4: 685a ldr r2, [r3, #4] 800fdd6: 687b ldr r3, [r7, #4] 800fdd8: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800fdda: 687b ldr r3, [r7, #4] 800fddc: 697a ldr r2, [r7, #20] 800fdde: 621a str r2, [r3, #32] } 800fde0: bf00 nop 800fde2: 371c adds r7, #28 800fde4: 46bd mov sp, r7 800fde6: f85d 7b04 ldr.w r7, [sp], #4 800fdea: 4770 bx lr 800fdec: fffeff8f .word 0xfffeff8f 800fdf0: 40010000 .word 0x40010000 800fdf4: 40010400 .word 0x40010400 800fdf8: 40014000 .word 0x40014000 800fdfc: 40014400 .word 0x40014400 800fe00: 40014800 .word 0x40014800 0800fe04 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800fe04: b480 push {r7} 800fe06: b087 sub sp, #28 800fe08: af00 add r7, sp, #0 800fe0a: 6078 str r0, [r7, #4] 800fe0c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800fe0e: 687b ldr r3, [r7, #4] 800fe10: 6a1b ldr r3, [r3, #32] 800fe12: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 800fe14: 687b ldr r3, [r7, #4] 800fe16: 6a1b ldr r3, [r3, #32] 800fe18: f023 0210 bic.w r2, r3, #16 800fe1c: 687b ldr r3, [r7, #4] 800fe1e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800fe20: 687b ldr r3, [r7, #4] 800fe22: 685b ldr r3, [r3, #4] 800fe24: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 800fe26: 687b ldr r3, [r7, #4] 800fe28: 699b ldr r3, [r3, #24] 800fe2a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 800fe2c: 68fa ldr r2, [r7, #12] 800fe2e: 4b34 ldr r3, [pc, #208] @ (800ff00 ) 800fe30: 4013 ands r3, r2 800fe32: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 800fe34: 68fb ldr r3, [r7, #12] 800fe36: f423 7340 bic.w r3, r3, #768 @ 0x300 800fe3a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800fe3c: 683b ldr r3, [r7, #0] 800fe3e: 681b ldr r3, [r3, #0] 800fe40: 021b lsls r3, r3, #8 800fe42: 68fa ldr r2, [r7, #12] 800fe44: 4313 orrs r3, r2 800fe46: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 800fe48: 697b ldr r3, [r7, #20] 800fe4a: f023 0320 bic.w r3, r3, #32 800fe4e: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 800fe50: 683b ldr r3, [r7, #0] 800fe52: 689b ldr r3, [r3, #8] 800fe54: 011b lsls r3, r3, #4 800fe56: 697a ldr r2, [r7, #20] 800fe58: 4313 orrs r3, r2 800fe5a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800fe5c: 687b ldr r3, [r7, #4] 800fe5e: 4a29 ldr r2, [pc, #164] @ (800ff04 ) 800fe60: 4293 cmp r3, r2 800fe62: d003 beq.n 800fe6c 800fe64: 687b ldr r3, [r7, #4] 800fe66: 4a28 ldr r2, [pc, #160] @ (800ff08 ) 800fe68: 4293 cmp r3, r2 800fe6a: d10d bne.n 800fe88 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 800fe6c: 697b ldr r3, [r7, #20] 800fe6e: f023 0380 bic.w r3, r3, #128 @ 0x80 800fe72: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 800fe74: 683b ldr r3, [r7, #0] 800fe76: 68db ldr r3, [r3, #12] 800fe78: 011b lsls r3, r3, #4 800fe7a: 697a ldr r2, [r7, #20] 800fe7c: 4313 orrs r3, r2 800fe7e: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 800fe80: 697b ldr r3, [r7, #20] 800fe82: f023 0340 bic.w r3, r3, #64 @ 0x40 800fe86: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800fe88: 687b ldr r3, [r7, #4] 800fe8a: 4a1e ldr r2, [pc, #120] @ (800ff04 ) 800fe8c: 4293 cmp r3, r2 800fe8e: d00f beq.n 800feb0 800fe90: 687b ldr r3, [r7, #4] 800fe92: 4a1d ldr r2, [pc, #116] @ (800ff08 ) 800fe94: 4293 cmp r3, r2 800fe96: d00b beq.n 800feb0 800fe98: 687b ldr r3, [r7, #4] 800fe9a: 4a1c ldr r2, [pc, #112] @ (800ff0c ) 800fe9c: 4293 cmp r3, r2 800fe9e: d007 beq.n 800feb0 800fea0: 687b ldr r3, [r7, #4] 800fea2: 4a1b ldr r2, [pc, #108] @ (800ff10 ) 800fea4: 4293 cmp r3, r2 800fea6: d003 beq.n 800feb0 800fea8: 687b ldr r3, [r7, #4] 800feaa: 4a1a ldr r2, [pc, #104] @ (800ff14 ) 800feac: 4293 cmp r3, r2 800feae: d113 bne.n 800fed8 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 800feb0: 693b ldr r3, [r7, #16] 800feb2: f423 6380 bic.w r3, r3, #1024 @ 0x400 800feb6: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 800feb8: 693b ldr r3, [r7, #16] 800feba: f423 6300 bic.w r3, r3, #2048 @ 0x800 800febe: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 800fec0: 683b ldr r3, [r7, #0] 800fec2: 695b ldr r3, [r3, #20] 800fec4: 009b lsls r3, r3, #2 800fec6: 693a ldr r2, [r7, #16] 800fec8: 4313 orrs r3, r2 800feca: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 800fecc: 683b ldr r3, [r7, #0] 800fece: 699b ldr r3, [r3, #24] 800fed0: 009b lsls r3, r3, #2 800fed2: 693a ldr r2, [r7, #16] 800fed4: 4313 orrs r3, r2 800fed6: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800fed8: 687b ldr r3, [r7, #4] 800feda: 693a ldr r2, [r7, #16] 800fedc: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 800fede: 687b ldr r3, [r7, #4] 800fee0: 68fa ldr r2, [r7, #12] 800fee2: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 800fee4: 683b ldr r3, [r7, #0] 800fee6: 685a ldr r2, [r3, #4] 800fee8: 687b ldr r3, [r7, #4] 800feea: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800feec: 687b ldr r3, [r7, #4] 800feee: 697a ldr r2, [r7, #20] 800fef0: 621a str r2, [r3, #32] } 800fef2: bf00 nop 800fef4: 371c adds r7, #28 800fef6: 46bd mov sp, r7 800fef8: f85d 7b04 ldr.w r7, [sp], #4 800fefc: 4770 bx lr 800fefe: bf00 nop 800ff00: feff8fff .word 0xfeff8fff 800ff04: 40010000 .word 0x40010000 800ff08: 40010400 .word 0x40010400 800ff0c: 40014000 .word 0x40014000 800ff10: 40014400 .word 0x40014400 800ff14: 40014800 .word 0x40014800 0800ff18 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800ff18: b480 push {r7} 800ff1a: b087 sub sp, #28 800ff1c: af00 add r7, sp, #0 800ff1e: 6078 str r0, [r7, #4] 800ff20: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800ff22: 687b ldr r3, [r7, #4] 800ff24: 6a1b ldr r3, [r3, #32] 800ff26: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 800ff28: 687b ldr r3, [r7, #4] 800ff2a: 6a1b ldr r3, [r3, #32] 800ff2c: f423 7280 bic.w r2, r3, #256 @ 0x100 800ff30: 687b ldr r3, [r7, #4] 800ff32: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800ff34: 687b ldr r3, [r7, #4] 800ff36: 685b ldr r3, [r3, #4] 800ff38: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800ff3a: 687b ldr r3, [r7, #4] 800ff3c: 69db ldr r3, [r3, #28] 800ff3e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 800ff40: 68fa ldr r2, [r7, #12] 800ff42: 4b33 ldr r3, [pc, #204] @ (8010010 ) 800ff44: 4013 ands r3, r2 800ff46: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 800ff48: 68fb ldr r3, [r7, #12] 800ff4a: f023 0303 bic.w r3, r3, #3 800ff4e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800ff50: 683b ldr r3, [r7, #0] 800ff52: 681b ldr r3, [r3, #0] 800ff54: 68fa ldr r2, [r7, #12] 800ff56: 4313 orrs r3, r2 800ff58: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 800ff5a: 697b ldr r3, [r7, #20] 800ff5c: f423 7300 bic.w r3, r3, #512 @ 0x200 800ff60: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 800ff62: 683b ldr r3, [r7, #0] 800ff64: 689b ldr r3, [r3, #8] 800ff66: 021b lsls r3, r3, #8 800ff68: 697a ldr r2, [r7, #20] 800ff6a: 4313 orrs r3, r2 800ff6c: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 800ff6e: 687b ldr r3, [r7, #4] 800ff70: 4a28 ldr r2, [pc, #160] @ (8010014 ) 800ff72: 4293 cmp r3, r2 800ff74: d003 beq.n 800ff7e 800ff76: 687b ldr r3, [r7, #4] 800ff78: 4a27 ldr r2, [pc, #156] @ (8010018 ) 800ff7a: 4293 cmp r3, r2 800ff7c: d10d bne.n 800ff9a { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 800ff7e: 697b ldr r3, [r7, #20] 800ff80: f423 6300 bic.w r3, r3, #2048 @ 0x800 800ff84: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 800ff86: 683b ldr r3, [r7, #0] 800ff88: 68db ldr r3, [r3, #12] 800ff8a: 021b lsls r3, r3, #8 800ff8c: 697a ldr r2, [r7, #20] 800ff8e: 4313 orrs r3, r2 800ff90: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 800ff92: 697b ldr r3, [r7, #20] 800ff94: f423 6380 bic.w r3, r3, #1024 @ 0x400 800ff98: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800ff9a: 687b ldr r3, [r7, #4] 800ff9c: 4a1d ldr r2, [pc, #116] @ (8010014 ) 800ff9e: 4293 cmp r3, r2 800ffa0: d00f beq.n 800ffc2 800ffa2: 687b ldr r3, [r7, #4] 800ffa4: 4a1c ldr r2, [pc, #112] @ (8010018 ) 800ffa6: 4293 cmp r3, r2 800ffa8: d00b beq.n 800ffc2 800ffaa: 687b ldr r3, [r7, #4] 800ffac: 4a1b ldr r2, [pc, #108] @ (801001c ) 800ffae: 4293 cmp r3, r2 800ffb0: d007 beq.n 800ffc2 800ffb2: 687b ldr r3, [r7, #4] 800ffb4: 4a1a ldr r2, [pc, #104] @ (8010020 ) 800ffb6: 4293 cmp r3, r2 800ffb8: d003 beq.n 800ffc2 800ffba: 687b ldr r3, [r7, #4] 800ffbc: 4a19 ldr r2, [pc, #100] @ (8010024 ) 800ffbe: 4293 cmp r3, r2 800ffc0: d113 bne.n 800ffea /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 800ffc2: 693b ldr r3, [r7, #16] 800ffc4: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800ffc8: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 800ffca: 693b ldr r3, [r7, #16] 800ffcc: f423 5300 bic.w r3, r3, #8192 @ 0x2000 800ffd0: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 800ffd2: 683b ldr r3, [r7, #0] 800ffd4: 695b ldr r3, [r3, #20] 800ffd6: 011b lsls r3, r3, #4 800ffd8: 693a ldr r2, [r7, #16] 800ffda: 4313 orrs r3, r2 800ffdc: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 800ffde: 683b ldr r3, [r7, #0] 800ffe0: 699b ldr r3, [r3, #24] 800ffe2: 011b lsls r3, r3, #4 800ffe4: 693a ldr r2, [r7, #16] 800ffe6: 4313 orrs r3, r2 800ffe8: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 800ffea: 687b ldr r3, [r7, #4] 800ffec: 693a ldr r2, [r7, #16] 800ffee: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800fff0: 687b ldr r3, [r7, #4] 800fff2: 68fa ldr r2, [r7, #12] 800fff4: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 800fff6: 683b ldr r3, [r7, #0] 800fff8: 685a ldr r2, [r3, #4] 800fffa: 687b ldr r3, [r7, #4] 800fffc: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800fffe: 687b ldr r3, [r7, #4] 8010000: 697a ldr r2, [r7, #20] 8010002: 621a str r2, [r3, #32] } 8010004: bf00 nop 8010006: 371c adds r7, #28 8010008: 46bd mov sp, r7 801000a: f85d 7b04 ldr.w r7, [sp], #4 801000e: 4770 bx lr 8010010: fffeff8f .word 0xfffeff8f 8010014: 40010000 .word 0x40010000 8010018: 40010400 .word 0x40010400 801001c: 40014000 .word 0x40014000 8010020: 40014400 .word 0x40014400 8010024: 40014800 .word 0x40014800 08010028 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010028: b480 push {r7} 801002a: b087 sub sp, #28 801002c: af00 add r7, sp, #0 801002e: 6078 str r0, [r7, #4] 8010030: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010032: 687b ldr r3, [r7, #4] 8010034: 6a1b ldr r3, [r3, #32] 8010036: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8010038: 687b ldr r3, [r7, #4] 801003a: 6a1b ldr r3, [r3, #32] 801003c: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8010040: 687b ldr r3, [r7, #4] 8010042: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010044: 687b ldr r3, [r7, #4] 8010046: 685b ldr r3, [r3, #4] 8010048: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 801004a: 687b ldr r3, [r7, #4] 801004c: 69db ldr r3, [r3, #28] 801004e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8010050: 68fa ldr r2, [r7, #12] 8010052: 4b24 ldr r3, [pc, #144] @ (80100e4 ) 8010054: 4013 ands r3, r2 8010056: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8010058: 68fb ldr r3, [r7, #12] 801005a: f423 7340 bic.w r3, r3, #768 @ 0x300 801005e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010060: 683b ldr r3, [r7, #0] 8010062: 681b ldr r3, [r3, #0] 8010064: 021b lsls r3, r3, #8 8010066: 68fa ldr r2, [r7, #12] 8010068: 4313 orrs r3, r2 801006a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 801006c: 693b ldr r3, [r7, #16] 801006e: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010072: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8010074: 683b ldr r3, [r7, #0] 8010076: 689b ldr r3, [r3, #8] 8010078: 031b lsls r3, r3, #12 801007a: 693a ldr r2, [r7, #16] 801007c: 4313 orrs r3, r2 801007e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010080: 687b ldr r3, [r7, #4] 8010082: 4a19 ldr r2, [pc, #100] @ (80100e8 ) 8010084: 4293 cmp r3, r2 8010086: d00f beq.n 80100a8 8010088: 687b ldr r3, [r7, #4] 801008a: 4a18 ldr r2, [pc, #96] @ (80100ec ) 801008c: 4293 cmp r3, r2 801008e: d00b beq.n 80100a8 8010090: 687b ldr r3, [r7, #4] 8010092: 4a17 ldr r2, [pc, #92] @ (80100f0 ) 8010094: 4293 cmp r3, r2 8010096: d007 beq.n 80100a8 8010098: 687b ldr r3, [r7, #4] 801009a: 4a16 ldr r2, [pc, #88] @ (80100f4 ) 801009c: 4293 cmp r3, r2 801009e: d003 beq.n 80100a8 80100a0: 687b ldr r3, [r7, #4] 80100a2: 4a15 ldr r2, [pc, #84] @ (80100f8 ) 80100a4: 4293 cmp r3, r2 80100a6: d109 bne.n 80100bc { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 80100a8: 697b ldr r3, [r7, #20] 80100aa: f423 4380 bic.w r3, r3, #16384 @ 0x4000 80100ae: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 80100b0: 683b ldr r3, [r7, #0] 80100b2: 695b ldr r3, [r3, #20] 80100b4: 019b lsls r3, r3, #6 80100b6: 697a ldr r2, [r7, #20] 80100b8: 4313 orrs r3, r2 80100ba: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80100bc: 687b ldr r3, [r7, #4] 80100be: 697a ldr r2, [r7, #20] 80100c0: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80100c2: 687b ldr r3, [r7, #4] 80100c4: 68fa ldr r2, [r7, #12] 80100c6: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 80100c8: 683b ldr r3, [r7, #0] 80100ca: 685a ldr r2, [r3, #4] 80100cc: 687b ldr r3, [r7, #4] 80100ce: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80100d0: 687b ldr r3, [r7, #4] 80100d2: 693a ldr r2, [r7, #16] 80100d4: 621a str r2, [r3, #32] } 80100d6: bf00 nop 80100d8: 371c adds r7, #28 80100da: 46bd mov sp, r7 80100dc: f85d 7b04 ldr.w r7, [sp], #4 80100e0: 4770 bx lr 80100e2: bf00 nop 80100e4: feff8fff .word 0xfeff8fff 80100e8: 40010000 .word 0x40010000 80100ec: 40010400 .word 0x40010400 80100f0: 40014000 .word 0x40014000 80100f4: 40014400 .word 0x40014400 80100f8: 40014800 .word 0x40014800 080100fc : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80100fc: b480 push {r7} 80100fe: b087 sub sp, #28 8010100: af00 add r7, sp, #0 8010102: 6078 str r0, [r7, #4] 8010104: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010106: 687b ldr r3, [r7, #4] 8010108: 6a1b ldr r3, [r3, #32] 801010a: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 801010c: 687b ldr r3, [r7, #4] 801010e: 6a1b ldr r3, [r3, #32] 8010110: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8010114: 687b ldr r3, [r7, #4] 8010116: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010118: 687b ldr r3, [r7, #4] 801011a: 685b ldr r3, [r3, #4] 801011c: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 801011e: 687b ldr r3, [r7, #4] 8010120: 6d5b ldr r3, [r3, #84] @ 0x54 8010122: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8010124: 68fa ldr r2, [r7, #12] 8010126: 4b21 ldr r3, [pc, #132] @ (80101ac ) 8010128: 4013 ands r3, r2 801012a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 801012c: 683b ldr r3, [r7, #0] 801012e: 681b ldr r3, [r3, #0] 8010130: 68fa ldr r2, [r7, #12] 8010132: 4313 orrs r3, r2 8010134: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 8010136: 693b ldr r3, [r7, #16] 8010138: f423 3300 bic.w r3, r3, #131072 @ 0x20000 801013c: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 801013e: 683b ldr r3, [r7, #0] 8010140: 689b ldr r3, [r3, #8] 8010142: 041b lsls r3, r3, #16 8010144: 693a ldr r2, [r7, #16] 8010146: 4313 orrs r3, r2 8010148: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 801014a: 687b ldr r3, [r7, #4] 801014c: 4a18 ldr r2, [pc, #96] @ (80101b0 ) 801014e: 4293 cmp r3, r2 8010150: d00f beq.n 8010172 8010152: 687b ldr r3, [r7, #4] 8010154: 4a17 ldr r2, [pc, #92] @ (80101b4 ) 8010156: 4293 cmp r3, r2 8010158: d00b beq.n 8010172 801015a: 687b ldr r3, [r7, #4] 801015c: 4a16 ldr r2, [pc, #88] @ (80101b8 ) 801015e: 4293 cmp r3, r2 8010160: d007 beq.n 8010172 8010162: 687b ldr r3, [r7, #4] 8010164: 4a15 ldr r2, [pc, #84] @ (80101bc ) 8010166: 4293 cmp r3, r2 8010168: d003 beq.n 8010172 801016a: 687b ldr r3, [r7, #4] 801016c: 4a14 ldr r2, [pc, #80] @ (80101c0 ) 801016e: 4293 cmp r3, r2 8010170: d109 bne.n 8010186 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 8010172: 697b ldr r3, [r7, #20] 8010174: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010178: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 801017a: 683b ldr r3, [r7, #0] 801017c: 695b ldr r3, [r3, #20] 801017e: 021b lsls r3, r3, #8 8010180: 697a ldr r2, [r7, #20] 8010182: 4313 orrs r3, r2 8010184: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010186: 687b ldr r3, [r7, #4] 8010188: 697a ldr r2, [r7, #20] 801018a: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 801018c: 687b ldr r3, [r7, #4] 801018e: 68fa ldr r2, [r7, #12] 8010190: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 8010192: 683b ldr r3, [r7, #0] 8010194: 685a ldr r2, [r3, #4] 8010196: 687b ldr r3, [r7, #4] 8010198: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 801019a: 687b ldr r3, [r7, #4] 801019c: 693a ldr r2, [r7, #16] 801019e: 621a str r2, [r3, #32] } 80101a0: bf00 nop 80101a2: 371c adds r7, #28 80101a4: 46bd mov sp, r7 80101a6: f85d 7b04 ldr.w r7, [sp], #4 80101aa: 4770 bx lr 80101ac: fffeff8f .word 0xfffeff8f 80101b0: 40010000 .word 0x40010000 80101b4: 40010400 .word 0x40010400 80101b8: 40014000 .word 0x40014000 80101bc: 40014400 .word 0x40014400 80101c0: 40014800 .word 0x40014800 080101c4 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80101c4: b480 push {r7} 80101c6: b087 sub sp, #28 80101c8: af00 add r7, sp, #0 80101ca: 6078 str r0, [r7, #4] 80101cc: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80101ce: 687b ldr r3, [r7, #4] 80101d0: 6a1b ldr r3, [r3, #32] 80101d2: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 80101d4: 687b ldr r3, [r7, #4] 80101d6: 6a1b ldr r3, [r3, #32] 80101d8: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 80101dc: 687b ldr r3, [r7, #4] 80101de: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80101e0: 687b ldr r3, [r7, #4] 80101e2: 685b ldr r3, [r3, #4] 80101e4: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 80101e6: 687b ldr r3, [r7, #4] 80101e8: 6d5b ldr r3, [r3, #84] @ 0x54 80101ea: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 80101ec: 68fa ldr r2, [r7, #12] 80101ee: 4b22 ldr r3, [pc, #136] @ (8010278 ) 80101f0: 4013 ands r3, r2 80101f2: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80101f4: 683b ldr r3, [r7, #0] 80101f6: 681b ldr r3, [r3, #0] 80101f8: 021b lsls r3, r3, #8 80101fa: 68fa ldr r2, [r7, #12] 80101fc: 4313 orrs r3, r2 80101fe: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8010200: 693b ldr r3, [r7, #16] 8010202: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8010206: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 8010208: 683b ldr r3, [r7, #0] 801020a: 689b ldr r3, [r3, #8] 801020c: 051b lsls r3, r3, #20 801020e: 693a ldr r2, [r7, #16] 8010210: 4313 orrs r3, r2 8010212: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010214: 687b ldr r3, [r7, #4] 8010216: 4a19 ldr r2, [pc, #100] @ (801027c ) 8010218: 4293 cmp r3, r2 801021a: d00f beq.n 801023c 801021c: 687b ldr r3, [r7, #4] 801021e: 4a18 ldr r2, [pc, #96] @ (8010280 ) 8010220: 4293 cmp r3, r2 8010222: d00b beq.n 801023c 8010224: 687b ldr r3, [r7, #4] 8010226: 4a17 ldr r2, [pc, #92] @ (8010284 ) 8010228: 4293 cmp r3, r2 801022a: d007 beq.n 801023c 801022c: 687b ldr r3, [r7, #4] 801022e: 4a16 ldr r2, [pc, #88] @ (8010288 ) 8010230: 4293 cmp r3, r2 8010232: d003 beq.n 801023c 8010234: 687b ldr r3, [r7, #4] 8010236: 4a15 ldr r2, [pc, #84] @ (801028c ) 8010238: 4293 cmp r3, r2 801023a: d109 bne.n 8010250 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 801023c: 697b ldr r3, [r7, #20] 801023e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010242: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8010244: 683b ldr r3, [r7, #0] 8010246: 695b ldr r3, [r3, #20] 8010248: 029b lsls r3, r3, #10 801024a: 697a ldr r2, [r7, #20] 801024c: 4313 orrs r3, r2 801024e: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010250: 687b ldr r3, [r7, #4] 8010252: 697a ldr r2, [r7, #20] 8010254: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010256: 687b ldr r3, [r7, #4] 8010258: 68fa ldr r2, [r7, #12] 801025a: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 801025c: 683b ldr r3, [r7, #0] 801025e: 685a ldr r2, [r3, #4] 8010260: 687b ldr r3, [r7, #4] 8010262: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010264: 687b ldr r3, [r7, #4] 8010266: 693a ldr r2, [r7, #16] 8010268: 621a str r2, [r3, #32] } 801026a: bf00 nop 801026c: 371c adds r7, #28 801026e: 46bd mov sp, r7 8010270: f85d 7b04 ldr.w r7, [sp], #4 8010274: 4770 bx lr 8010276: bf00 nop 8010278: feff8fff .word 0xfeff8fff 801027c: 40010000 .word 0x40010000 8010280: 40010400 .word 0x40010400 8010284: 40014000 .word 0x40014000 8010288: 40014400 .word 0x40014400 801028c: 40014800 .word 0x40014800 08010290 : * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010290: b480 push {r7} 8010292: b087 sub sp, #28 8010294: af00 add r7, sp, #0 8010296: 60f8 str r0, [r7, #12] 8010298: 60b9 str r1, [r7, #8] 801029a: 607a str r2, [r7, #4] 801029c: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 801029e: 68fb ldr r3, [r7, #12] 80102a0: 6a1b ldr r3, [r3, #32] 80102a2: 613b str r3, [r7, #16] TIMx->CCER &= ~TIM_CCER_CC1E; 80102a4: 68fb ldr r3, [r7, #12] 80102a6: 6a1b ldr r3, [r3, #32] 80102a8: f023 0201 bic.w r2, r3, #1 80102ac: 68fb ldr r3, [r7, #12] 80102ae: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80102b0: 68fb ldr r3, [r7, #12] 80102b2: 699b ldr r3, [r3, #24] 80102b4: 617b str r3, [r7, #20] /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) 80102b6: 68fb ldr r3, [r7, #12] 80102b8: 4a28 ldr r2, [pc, #160] @ (801035c ) 80102ba: 4293 cmp r3, r2 80102bc: d01b beq.n 80102f6 80102be: 68fb ldr r3, [r7, #12] 80102c0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80102c4: d017 beq.n 80102f6 80102c6: 68fb ldr r3, [r7, #12] 80102c8: 4a25 ldr r2, [pc, #148] @ (8010360 ) 80102ca: 4293 cmp r3, r2 80102cc: d013 beq.n 80102f6 80102ce: 68fb ldr r3, [r7, #12] 80102d0: 4a24 ldr r2, [pc, #144] @ (8010364 ) 80102d2: 4293 cmp r3, r2 80102d4: d00f beq.n 80102f6 80102d6: 68fb ldr r3, [r7, #12] 80102d8: 4a23 ldr r2, [pc, #140] @ (8010368 ) 80102da: 4293 cmp r3, r2 80102dc: d00b beq.n 80102f6 80102de: 68fb ldr r3, [r7, #12] 80102e0: 4a22 ldr r2, [pc, #136] @ (801036c ) 80102e2: 4293 cmp r3, r2 80102e4: d007 beq.n 80102f6 80102e6: 68fb ldr r3, [r7, #12] 80102e8: 4a21 ldr r2, [pc, #132] @ (8010370 ) 80102ea: 4293 cmp r3, r2 80102ec: d003 beq.n 80102f6 80102ee: 68fb ldr r3, [r7, #12] 80102f0: 4a20 ldr r2, [pc, #128] @ (8010374 ) 80102f2: 4293 cmp r3, r2 80102f4: d101 bne.n 80102fa 80102f6: 2301 movs r3, #1 80102f8: e000 b.n 80102fc 80102fa: 2300 movs r3, #0 80102fc: 2b00 cmp r3, #0 80102fe: d008 beq.n 8010312 { tmpccmr1 &= ~TIM_CCMR1_CC1S; 8010300: 697b ldr r3, [r7, #20] 8010302: f023 0303 bic.w r3, r3, #3 8010306: 617b str r3, [r7, #20] tmpccmr1 |= TIM_ICSelection; 8010308: 697a ldr r2, [r7, #20] 801030a: 687b ldr r3, [r7, #4] 801030c: 4313 orrs r3, r2 801030e: 617b str r3, [r7, #20] 8010310: e003 b.n 801031a } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; 8010312: 697b ldr r3, [r7, #20] 8010314: f043 0301 orr.w r3, r3, #1 8010318: 617b str r3, [r7, #20] } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 801031a: 697b ldr r3, [r7, #20] 801031c: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010320: 617b str r3, [r7, #20] tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); 8010322: 683b ldr r3, [r7, #0] 8010324: 011b lsls r3, r3, #4 8010326: b2db uxtb r3, r3 8010328: 697a ldr r2, [r7, #20] 801032a: 4313 orrs r3, r2 801032c: 617b str r3, [r7, #20] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 801032e: 693b ldr r3, [r7, #16] 8010330: f023 030a bic.w r3, r3, #10 8010334: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 8010336: 68bb ldr r3, [r7, #8] 8010338: f003 030a and.w r3, r3, #10 801033c: 693a ldr r2, [r7, #16] 801033e: 4313 orrs r3, r2 8010340: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010342: 68fb ldr r3, [r7, #12] 8010344: 697a ldr r2, [r7, #20] 8010346: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010348: 68fb ldr r3, [r7, #12] 801034a: 693a ldr r2, [r7, #16] 801034c: 621a str r2, [r3, #32] } 801034e: bf00 nop 8010350: 371c adds r7, #28 8010352: 46bd mov sp, r7 8010354: f85d 7b04 ldr.w r7, [sp], #4 8010358: 4770 bx lr 801035a: bf00 nop 801035c: 40010000 .word 0x40010000 8010360: 40000400 .word 0x40000400 8010364: 40000800 .word 0x40000800 8010368: 40000c00 .word 0x40000c00 801036c: 40010400 .word 0x40010400 8010370: 40001800 .word 0x40001800 8010374: 40014000 .word 0x40014000 08010378 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010378: b480 push {r7} 801037a: b087 sub sp, #28 801037c: af00 add r7, sp, #0 801037e: 60f8 str r0, [r7, #12] 8010380: 60b9 str r1, [r7, #8] 8010382: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010384: 68fb ldr r3, [r7, #12] 8010386: 6a1b ldr r3, [r3, #32] 8010388: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 801038a: 68fb ldr r3, [r7, #12] 801038c: 6a1b ldr r3, [r3, #32] 801038e: f023 0201 bic.w r2, r3, #1 8010392: 68fb ldr r3, [r7, #12] 8010394: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010396: 68fb ldr r3, [r7, #12] 8010398: 699b ldr r3, [r3, #24] 801039a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 801039c: 693b ldr r3, [r7, #16] 801039e: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80103a2: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 80103a4: 687b ldr r3, [r7, #4] 80103a6: 011b lsls r3, r3, #4 80103a8: 693a ldr r2, [r7, #16] 80103aa: 4313 orrs r3, r2 80103ac: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 80103ae: 697b ldr r3, [r7, #20] 80103b0: f023 030a bic.w r3, r3, #10 80103b4: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 80103b6: 697a ldr r2, [r7, #20] 80103b8: 68bb ldr r3, [r7, #8] 80103ba: 4313 orrs r3, r2 80103bc: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 80103be: 68fb ldr r3, [r7, #12] 80103c0: 693a ldr r2, [r7, #16] 80103c2: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80103c4: 68fb ldr r3, [r7, #12] 80103c6: 697a ldr r2, [r7, #20] 80103c8: 621a str r2, [r3, #32] } 80103ca: bf00 nop 80103cc: 371c adds r7, #28 80103ce: 46bd mov sp, r7 80103d0: f85d 7b04 ldr.w r7, [sp], #4 80103d4: 4770 bx lr 080103d6 : * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 80103d6: b480 push {r7} 80103d8: b087 sub sp, #28 80103da: af00 add r7, sp, #0 80103dc: 60f8 str r0, [r7, #12] 80103de: 60b9 str r1, [r7, #8] 80103e0: 607a str r2, [r7, #4] 80103e2: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 80103e4: 68fb ldr r3, [r7, #12] 80103e6: 6a1b ldr r3, [r3, #32] 80103e8: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 80103ea: 68fb ldr r3, [r7, #12] 80103ec: 6a1b ldr r3, [r3, #32] 80103ee: f023 0210 bic.w r2, r3, #16 80103f2: 68fb ldr r3, [r7, #12] 80103f4: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80103f6: 68fb ldr r3, [r7, #12] 80103f8: 699b ldr r3, [r3, #24] 80103fa: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; 80103fc: 693b ldr r3, [r7, #16] 80103fe: f423 7340 bic.w r3, r3, #768 @ 0x300 8010402: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICSelection << 8U); 8010404: 687b ldr r3, [r7, #4] 8010406: 021b lsls r3, r3, #8 8010408: 693a ldr r2, [r7, #16] 801040a: 4313 orrs r3, r2 801040c: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 801040e: 693b ldr r3, [r7, #16] 8010410: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010414: 613b str r3, [r7, #16] tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); 8010416: 683b ldr r3, [r7, #0] 8010418: 031b lsls r3, r3, #12 801041a: b29b uxth r3, r3 801041c: 693a ldr r2, [r7, #16] 801041e: 4313 orrs r3, r2 8010420: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010422: 697b ldr r3, [r7, #20] 8010424: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8010428: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 801042a: 68bb ldr r3, [r7, #8] 801042c: 011b lsls r3, r3, #4 801042e: f003 03a0 and.w r3, r3, #160 @ 0xa0 8010432: 697a ldr r2, [r7, #20] 8010434: 4313 orrs r3, r2 8010436: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010438: 68fb ldr r3, [r7, #12] 801043a: 693a ldr r2, [r7, #16] 801043c: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 801043e: 68fb ldr r3, [r7, #12] 8010440: 697a ldr r2, [r7, #20] 8010442: 621a str r2, [r3, #32] } 8010444: bf00 nop 8010446: 371c adds r7, #28 8010448: 46bd mov sp, r7 801044a: f85d 7b04 ldr.w r7, [sp], #4 801044e: 4770 bx lr 08010450 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010450: b480 push {r7} 8010452: b087 sub sp, #28 8010454: af00 add r7, sp, #0 8010456: 60f8 str r0, [r7, #12] 8010458: 60b9 str r1, [r7, #8] 801045a: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 801045c: 68fb ldr r3, [r7, #12] 801045e: 6a1b ldr r3, [r3, #32] 8010460: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010462: 68fb ldr r3, [r7, #12] 8010464: 6a1b ldr r3, [r3, #32] 8010466: f023 0210 bic.w r2, r3, #16 801046a: 68fb ldr r3, [r7, #12] 801046c: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 801046e: 68fb ldr r3, [r7, #12] 8010470: 699b ldr r3, [r3, #24] 8010472: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010474: 693b ldr r3, [r7, #16] 8010476: f423 4370 bic.w r3, r3, #61440 @ 0xf000 801047a: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 801047c: 687b ldr r3, [r7, #4] 801047e: 031b lsls r3, r3, #12 8010480: 693a ldr r2, [r7, #16] 8010482: 4313 orrs r3, r2 8010484: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010486: 697b ldr r3, [r7, #20] 8010488: f023 03a0 bic.w r3, r3, #160 @ 0xa0 801048c: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 801048e: 68bb ldr r3, [r7, #8] 8010490: 011b lsls r3, r3, #4 8010492: 697a ldr r2, [r7, #20] 8010494: 4313 orrs r3, r2 8010496: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010498: 68fb ldr r3, [r7, #12] 801049a: 693a ldr r2, [r7, #16] 801049c: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 801049e: 68fb ldr r3, [r7, #12] 80104a0: 697a ldr r2, [r7, #20] 80104a2: 621a str r2, [r3, #32] } 80104a4: bf00 nop 80104a6: 371c adds r7, #28 80104a8: 46bd mov sp, r7 80104aa: f85d 7b04 ldr.w r7, [sp], #4 80104ae: 4770 bx lr 080104b0 : * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 80104b0: b480 push {r7} 80104b2: b087 sub sp, #28 80104b4: af00 add r7, sp, #0 80104b6: 60f8 str r0, [r7, #12] 80104b8: 60b9 str r1, [r7, #8] 80104ba: 607a str r2, [r7, #4] 80104bc: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ tmpccer = TIMx->CCER; 80104be: 68fb ldr r3, [r7, #12] 80104c0: 6a1b ldr r3, [r3, #32] 80104c2: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC3E; 80104c4: 68fb ldr r3, [r7, #12] 80104c6: 6a1b ldr r3, [r3, #32] 80104c8: f423 7280 bic.w r2, r3, #256 @ 0x100 80104cc: 68fb ldr r3, [r7, #12] 80104ce: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 80104d0: 68fb ldr r3, [r7, #12] 80104d2: 69db ldr r3, [r3, #28] 80104d4: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; 80104d6: 693b ldr r3, [r7, #16] 80104d8: f023 0303 bic.w r3, r3, #3 80104dc: 613b str r3, [r7, #16] tmpccmr2 |= TIM_ICSelection; 80104de: 693a ldr r2, [r7, #16] 80104e0: 687b ldr r3, [r7, #4] 80104e2: 4313 orrs r3, r2 80104e4: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; 80104e6: 693b ldr r3, [r7, #16] 80104e8: f023 03f0 bic.w r3, r3, #240 @ 0xf0 80104ec: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); 80104ee: 683b ldr r3, [r7, #0] 80104f0: 011b lsls r3, r3, #4 80104f2: b2db uxtb r3, r3 80104f4: 693a ldr r2, [r7, #16] 80104f6: 4313 orrs r3, r2 80104f8: 613b str r3, [r7, #16] /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 80104fa: 697b ldr r3, [r7, #20] 80104fc: f423 6320 bic.w r3, r3, #2560 @ 0xa00 8010500: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 8010502: 68bb ldr r3, [r7, #8] 8010504: 021b lsls r3, r3, #8 8010506: f403 6320 and.w r3, r3, #2560 @ 0xa00 801050a: 697a ldr r2, [r7, #20] 801050c: 4313 orrs r3, r2 801050e: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 8010510: 68fb ldr r3, [r7, #12] 8010512: 693a ldr r2, [r7, #16] 8010514: 61da str r2, [r3, #28] TIMx->CCER = tmpccer; 8010516: 68fb ldr r3, [r7, #12] 8010518: 697a ldr r2, [r7, #20] 801051a: 621a str r2, [r3, #32] } 801051c: bf00 nop 801051e: 371c adds r7, #28 8010520: 46bd mov sp, r7 8010522: f85d 7b04 ldr.w r7, [sp], #4 8010526: 4770 bx lr 08010528 : * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010528: b480 push {r7} 801052a: b087 sub sp, #28 801052c: af00 add r7, sp, #0 801052e: 60f8 str r0, [r7, #12] 8010530: 60b9 str r1, [r7, #8] 8010532: 607a str r2, [r7, #4] 8010534: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ tmpccer = TIMx->CCER; 8010536: 68fb ldr r3, [r7, #12] 8010538: 6a1b ldr r3, [r3, #32] 801053a: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC4E; 801053c: 68fb ldr r3, [r7, #12] 801053e: 6a1b ldr r3, [r3, #32] 8010540: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8010544: 68fb ldr r3, [r7, #12] 8010546: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 8010548: 68fb ldr r3, [r7, #12] 801054a: 69db ldr r3, [r3, #28] 801054c: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; 801054e: 693b ldr r3, [r7, #16] 8010550: f423 7340 bic.w r3, r3, #768 @ 0x300 8010554: 613b str r3, [r7, #16] tmpccmr2 |= (TIM_ICSelection << 8U); 8010556: 687b ldr r3, [r7, #4] 8010558: 021b lsls r3, r3, #8 801055a: 693a ldr r2, [r7, #16] 801055c: 4313 orrs r3, r2 801055e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; 8010560: 693b ldr r3, [r7, #16] 8010562: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010566: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); 8010568: 683b ldr r3, [r7, #0] 801056a: 031b lsls r3, r3, #12 801056c: b29b uxth r3, r3 801056e: 693a ldr r2, [r7, #16] 8010570: 4313 orrs r3, r2 8010572: 613b str r3, [r7, #16] /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 8010574: 697b ldr r3, [r7, #20] 8010576: f423 4320 bic.w r3, r3, #40960 @ 0xa000 801057a: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 801057c: 68bb ldr r3, [r7, #8] 801057e: 031b lsls r3, r3, #12 8010580: f403 4320 and.w r3, r3, #40960 @ 0xa000 8010584: 697a ldr r2, [r7, #20] 8010586: 4313 orrs r3, r2 8010588: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 801058a: 68fb ldr r3, [r7, #12] 801058c: 693a ldr r2, [r7, #16] 801058e: 61da str r2, [r3, #28] TIMx->CCER = tmpccer ; 8010590: 68fb ldr r3, [r7, #12] 8010592: 697a ldr r2, [r7, #20] 8010594: 621a str r2, [r3, #32] } 8010596: bf00 nop 8010598: 371c adds r7, #28 801059a: 46bd mov sp, r7 801059c: f85d 7b04 ldr.w r7, [sp], #4 80105a0: 4770 bx lr ... 080105a4 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 80105a4: b480 push {r7} 80105a6: b085 sub sp, #20 80105a8: af00 add r7, sp, #0 80105aa: 6078 str r0, [r7, #4] 80105ac: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80105ae: 687b ldr r3, [r7, #4] 80105b0: 689b ldr r3, [r3, #8] 80105b2: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80105b4: 68fa ldr r2, [r7, #12] 80105b6: 4b09 ldr r3, [pc, #36] @ (80105dc ) 80105b8: 4013 ands r3, r2 80105ba: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80105bc: 683a ldr r2, [r7, #0] 80105be: 68fb ldr r3, [r7, #12] 80105c0: 4313 orrs r3, r2 80105c2: f043 0307 orr.w r3, r3, #7 80105c6: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80105c8: 687b ldr r3, [r7, #4] 80105ca: 68fa ldr r2, [r7, #12] 80105cc: 609a str r2, [r3, #8] } 80105ce: bf00 nop 80105d0: 3714 adds r7, #20 80105d2: 46bd mov sp, r7 80105d4: f85d 7b04 ldr.w r7, [sp], #4 80105d8: 4770 bx lr 80105da: bf00 nop 80105dc: ffcfff8f .word 0xffcfff8f 080105e0 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 80105e0: b480 push {r7} 80105e2: b087 sub sp, #28 80105e4: af00 add r7, sp, #0 80105e6: 60f8 str r0, [r7, #12] 80105e8: 60b9 str r1, [r7, #8] 80105ea: 607a str r2, [r7, #4] 80105ec: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 80105ee: 68fb ldr r3, [r7, #12] 80105f0: 689b ldr r3, [r3, #8] 80105f2: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80105f4: 697b ldr r3, [r7, #20] 80105f6: f423 437f bic.w r3, r3, #65280 @ 0xff00 80105fa: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80105fc: 683b ldr r3, [r7, #0] 80105fe: 021a lsls r2, r3, #8 8010600: 687b ldr r3, [r7, #4] 8010602: 431a orrs r2, r3 8010604: 68bb ldr r3, [r7, #8] 8010606: 4313 orrs r3, r2 8010608: 697a ldr r2, [r7, #20] 801060a: 4313 orrs r3, r2 801060c: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 801060e: 68fb ldr r3, [r7, #12] 8010610: 697a ldr r2, [r7, #20] 8010612: 609a str r2, [r3, #8] } 8010614: bf00 nop 8010616: 371c adds r7, #28 8010618: 46bd mov sp, r7 801061a: f85d 7b04 ldr.w r7, [sp], #4 801061e: 4770 bx lr 08010620 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8010620: b480 push {r7} 8010622: b087 sub sp, #28 8010624: af00 add r7, sp, #0 8010626: 60f8 str r0, [r7, #12] 8010628: 60b9 str r1, [r7, #8] 801062a: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 801062c: 68bb ldr r3, [r7, #8] 801062e: f003 031f and.w r3, r3, #31 8010632: 2201 movs r2, #1 8010634: fa02 f303 lsl.w r3, r2, r3 8010638: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 801063a: 68fb ldr r3, [r7, #12] 801063c: 6a1a ldr r2, [r3, #32] 801063e: 697b ldr r3, [r7, #20] 8010640: 43db mvns r3, r3 8010642: 401a ands r2, r3 8010644: 68fb ldr r3, [r7, #12] 8010646: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8010648: 68fb ldr r3, [r7, #12] 801064a: 6a1a ldr r2, [r3, #32] 801064c: 68bb ldr r3, [r7, #8] 801064e: f003 031f and.w r3, r3, #31 8010652: 6879 ldr r1, [r7, #4] 8010654: fa01 f303 lsl.w r3, r1, r3 8010658: 431a orrs r2, r3 801065a: 68fb ldr r3, [r7, #12] 801065c: 621a str r2, [r3, #32] } 801065e: bf00 nop 8010660: 371c adds r7, #28 8010662: 46bd mov sp, r7 8010664: f85d 7b04 ldr.w r7, [sp], #4 8010668: 4770 bx lr ... 0801066c : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 801066c: b480 push {r7} 801066e: b085 sub sp, #20 8010670: af00 add r7, sp, #0 8010672: 6078 str r0, [r7, #4] 8010674: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8010676: 687b ldr r3, [r7, #4] 8010678: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801067c: 2b01 cmp r3, #1 801067e: d101 bne.n 8010684 8010680: 2302 movs r3, #2 8010682: e06d b.n 8010760 8010684: 687b ldr r3, [r7, #4] 8010686: 2201 movs r2, #1 8010688: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 801068c: 687b ldr r3, [r7, #4] 801068e: 2202 movs r2, #2 8010690: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8010694: 687b ldr r3, [r7, #4] 8010696: 681b ldr r3, [r3, #0] 8010698: 685b ldr r3, [r3, #4] 801069a: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 801069c: 687b ldr r3, [r7, #4] 801069e: 681b ldr r3, [r3, #0] 80106a0: 689b ldr r3, [r3, #8] 80106a2: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80106a4: 687b ldr r3, [r7, #4] 80106a6: 681b ldr r3, [r3, #0] 80106a8: 4a30 ldr r2, [pc, #192] @ (801076c ) 80106aa: 4293 cmp r3, r2 80106ac: d004 beq.n 80106b8 80106ae: 687b ldr r3, [r7, #4] 80106b0: 681b ldr r3, [r3, #0] 80106b2: 4a2f ldr r2, [pc, #188] @ (8010770 ) 80106b4: 4293 cmp r3, r2 80106b6: d108 bne.n 80106ca { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 80106b8: 68fb ldr r3, [r7, #12] 80106ba: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 80106be: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 80106c0: 683b ldr r3, [r7, #0] 80106c2: 685b ldr r3, [r3, #4] 80106c4: 68fa ldr r2, [r7, #12] 80106c6: 4313 orrs r3, r2 80106c8: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80106ca: 68fb ldr r3, [r7, #12] 80106cc: f023 0370 bic.w r3, r3, #112 @ 0x70 80106d0: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80106d2: 683b ldr r3, [r7, #0] 80106d4: 681b ldr r3, [r3, #0] 80106d6: 68fa ldr r2, [r7, #12] 80106d8: 4313 orrs r3, r2 80106da: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80106dc: 687b ldr r3, [r7, #4] 80106de: 681b ldr r3, [r3, #0] 80106e0: 68fa ldr r2, [r7, #12] 80106e2: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80106e4: 687b ldr r3, [r7, #4] 80106e6: 681b ldr r3, [r3, #0] 80106e8: 4a20 ldr r2, [pc, #128] @ (801076c ) 80106ea: 4293 cmp r3, r2 80106ec: d022 beq.n 8010734 80106ee: 687b ldr r3, [r7, #4] 80106f0: 681b ldr r3, [r3, #0] 80106f2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80106f6: d01d beq.n 8010734 80106f8: 687b ldr r3, [r7, #4] 80106fa: 681b ldr r3, [r3, #0] 80106fc: 4a1d ldr r2, [pc, #116] @ (8010774 ) 80106fe: 4293 cmp r3, r2 8010700: d018 beq.n 8010734 8010702: 687b ldr r3, [r7, #4] 8010704: 681b ldr r3, [r3, #0] 8010706: 4a1c ldr r2, [pc, #112] @ (8010778 ) 8010708: 4293 cmp r3, r2 801070a: d013 beq.n 8010734 801070c: 687b ldr r3, [r7, #4] 801070e: 681b ldr r3, [r3, #0] 8010710: 4a1a ldr r2, [pc, #104] @ (801077c ) 8010712: 4293 cmp r3, r2 8010714: d00e beq.n 8010734 8010716: 687b ldr r3, [r7, #4] 8010718: 681b ldr r3, [r3, #0] 801071a: 4a15 ldr r2, [pc, #84] @ (8010770 ) 801071c: 4293 cmp r3, r2 801071e: d009 beq.n 8010734 8010720: 687b ldr r3, [r7, #4] 8010722: 681b ldr r3, [r3, #0] 8010724: 4a16 ldr r2, [pc, #88] @ (8010780 ) 8010726: 4293 cmp r3, r2 8010728: d004 beq.n 8010734 801072a: 687b ldr r3, [r7, #4] 801072c: 681b ldr r3, [r3, #0] 801072e: 4a15 ldr r2, [pc, #84] @ (8010784 ) 8010730: 4293 cmp r3, r2 8010732: d10c bne.n 801074e { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8010734: 68bb ldr r3, [r7, #8] 8010736: f023 0380 bic.w r3, r3, #128 @ 0x80 801073a: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 801073c: 683b ldr r3, [r7, #0] 801073e: 689b ldr r3, [r3, #8] 8010740: 68ba ldr r2, [r7, #8] 8010742: 4313 orrs r3, r2 8010744: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8010746: 687b ldr r3, [r7, #4] 8010748: 681b ldr r3, [r3, #0] 801074a: 68ba ldr r2, [r7, #8] 801074c: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 801074e: 687b ldr r3, [r7, #4] 8010750: 2201 movs r2, #1 8010752: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8010756: 687b ldr r3, [r7, #4] 8010758: 2200 movs r2, #0 801075a: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801075e: 2300 movs r3, #0 } 8010760: 4618 mov r0, r3 8010762: 3714 adds r7, #20 8010764: 46bd mov sp, r7 8010766: f85d 7b04 ldr.w r7, [sp], #4 801076a: 4770 bx lr 801076c: 40010000 .word 0x40010000 8010770: 40010400 .word 0x40010400 8010774: 40000400 .word 0x40000400 8010778: 40000800 .word 0x40000800 801077c: 40000c00 .word 0x40000c00 8010780: 40001800 .word 0x40001800 8010784: 40014000 .word 0x40014000 08010788 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 8010788: b480 push {r7} 801078a: b085 sub sp, #20 801078c: af00 add r7, sp, #0 801078e: 6078 str r0, [r7, #4] 8010790: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 8010792: 2300 movs r3, #0 8010794: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 8010796: 687b ldr r3, [r7, #4] 8010798: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801079c: 2b01 cmp r3, #1 801079e: d101 bne.n 80107a4 80107a0: 2302 movs r3, #2 80107a2: e065 b.n 8010870 80107a4: 687b ldr r3, [r7, #4] 80107a6: 2201 movs r2, #1 80107a8: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 80107ac: 68fb ldr r3, [r7, #12] 80107ae: f023 02ff bic.w r2, r3, #255 @ 0xff 80107b2: 683b ldr r3, [r7, #0] 80107b4: 68db ldr r3, [r3, #12] 80107b6: 4313 orrs r3, r2 80107b8: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 80107ba: 68fb ldr r3, [r7, #12] 80107bc: f423 7240 bic.w r2, r3, #768 @ 0x300 80107c0: 683b ldr r3, [r7, #0] 80107c2: 689b ldr r3, [r3, #8] 80107c4: 4313 orrs r3, r2 80107c6: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 80107c8: 68fb ldr r3, [r7, #12] 80107ca: f423 6280 bic.w r2, r3, #1024 @ 0x400 80107ce: 683b ldr r3, [r7, #0] 80107d0: 685b ldr r3, [r3, #4] 80107d2: 4313 orrs r3, r2 80107d4: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 80107d6: 68fb ldr r3, [r7, #12] 80107d8: f423 6200 bic.w r2, r3, #2048 @ 0x800 80107dc: 683b ldr r3, [r7, #0] 80107de: 681b ldr r3, [r3, #0] 80107e0: 4313 orrs r3, r2 80107e2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 80107e4: 68fb ldr r3, [r7, #12] 80107e6: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80107ea: 683b ldr r3, [r7, #0] 80107ec: 691b ldr r3, [r3, #16] 80107ee: 4313 orrs r3, r2 80107f0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 80107f2: 68fb ldr r3, [r7, #12] 80107f4: f423 5200 bic.w r2, r3, #8192 @ 0x2000 80107f8: 683b ldr r3, [r7, #0] 80107fa: 695b ldr r3, [r3, #20] 80107fc: 4313 orrs r3, r2 80107fe: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8010800: 68fb ldr r3, [r7, #12] 8010802: f423 4280 bic.w r2, r3, #16384 @ 0x4000 8010806: 683b ldr r3, [r7, #0] 8010808: 6a9b ldr r3, [r3, #40] @ 0x28 801080a: 4313 orrs r3, r2 801080c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 801080e: 68fb ldr r3, [r7, #12] 8010810: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8010814: 683b ldr r3, [r7, #0] 8010816: 699b ldr r3, [r3, #24] 8010818: 041b lsls r3, r3, #16 801081a: 4313 orrs r3, r2 801081c: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 801081e: 687b ldr r3, [r7, #4] 8010820: 681b ldr r3, [r3, #0] 8010822: 4a16 ldr r2, [pc, #88] @ (801087c ) 8010824: 4293 cmp r3, r2 8010826: d004 beq.n 8010832 8010828: 687b ldr r3, [r7, #4] 801082a: 681b ldr r3, [r3, #0] 801082c: 4a14 ldr r2, [pc, #80] @ (8010880 ) 801082e: 4293 cmp r3, r2 8010830: d115 bne.n 801085e #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 8010832: 68fb ldr r3, [r7, #12] 8010834: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000 8010838: 683b ldr r3, [r7, #0] 801083a: 6a5b ldr r3, [r3, #36] @ 0x24 801083c: 051b lsls r3, r3, #20 801083e: 4313 orrs r3, r2 8010840: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 8010842: 68fb ldr r3, [r7, #12] 8010844: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 8010848: 683b ldr r3, [r7, #0] 801084a: 69db ldr r3, [r3, #28] 801084c: 4313 orrs r3, r2 801084e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 8010850: 68fb ldr r3, [r7, #12] 8010852: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 8010856: 683b ldr r3, [r7, #0] 8010858: 6a1b ldr r3, [r3, #32] 801085a: 4313 orrs r3, r2 801085c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 801085e: 687b ldr r3, [r7, #4] 8010860: 681b ldr r3, [r3, #0] 8010862: 68fa ldr r2, [r7, #12] 8010864: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 8010866: 687b ldr r3, [r7, #4] 8010868: 2200 movs r2, #0 801086a: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801086e: 2300 movs r3, #0 } 8010870: 4618 mov r0, r3 8010872: 3714 adds r7, #20 8010874: 46bd mov sp, r7 8010876: f85d 7b04 ldr.w r7, [sp], #4 801087a: 4770 bx lr 801087c: 40010000 .word 0x40010000 8010880: 40010400 .word 0x40010400 08010884 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8010884: b480 push {r7} 8010886: b083 sub sp, #12 8010888: af00 add r7, sp, #0 801088a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 801088c: bf00 nop 801088e: 370c adds r7, #12 8010890: 46bd mov sp, r7 8010892: f85d 7b04 ldr.w r7, [sp], #4 8010896: 4770 bx lr 08010898 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8010898: b480 push {r7} 801089a: b083 sub sp, #12 801089c: af00 add r7, sp, #0 801089e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 80108a0: bf00 nop 80108a2: 370c adds r7, #12 80108a4: 46bd mov sp, r7 80108a6: f85d 7b04 ldr.w r7, [sp], #4 80108aa: 4770 bx lr 080108ac : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 80108ac: b480 push {r7} 80108ae: b083 sub sp, #12 80108b0: af00 add r7, sp, #0 80108b2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 80108b4: bf00 nop 80108b6: 370c adds r7, #12 80108b8: 46bd mov sp, r7 80108ba: f85d 7b04 ldr.w r7, [sp], #4 80108be: 4770 bx lr 080108c0 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80108c0: b580 push {r7, lr} 80108c2: b082 sub sp, #8 80108c4: af00 add r7, sp, #0 80108c6: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80108c8: 687b ldr r3, [r7, #4] 80108ca: 2b00 cmp r3, #0 80108cc: d101 bne.n 80108d2 { return HAL_ERROR; 80108ce: 2301 movs r3, #1 80108d0: e042 b.n 8010958 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 80108d2: 687b ldr r3, [r7, #4] 80108d4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80108d8: 2b00 cmp r3, #0 80108da: d106 bne.n 80108ea { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80108dc: 687b ldr r3, [r7, #4] 80108de: 2200 movs r2, #0 80108e0: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80108e4: 6878 ldr r0, [r7, #4] 80108e6: f7f3 f987 bl 8003bf8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80108ea: 687b ldr r3, [r7, #4] 80108ec: 2224 movs r2, #36 @ 0x24 80108ee: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 80108f2: 687b ldr r3, [r7, #4] 80108f4: 681b ldr r3, [r3, #0] 80108f6: 681a ldr r2, [r3, #0] 80108f8: 687b ldr r3, [r7, #4] 80108fa: 681b ldr r3, [r3, #0] 80108fc: f022 0201 bic.w r2, r2, #1 8010900: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8010902: 687b ldr r3, [r7, #4] 8010904: 6a9b ldr r3, [r3, #40] @ 0x28 8010906: 2b00 cmp r3, #0 8010908: d002 beq.n 8010910 { UART_AdvFeatureConfig(huart); 801090a: 6878 ldr r0, [r7, #4] 801090c: f001 fa76 bl 8011dfc } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 8010910: 6878 ldr r0, [r7, #4] 8010912: f000 fd0b bl 801132c 8010916: 4603 mov r3, r0 8010918: 2b01 cmp r3, #1 801091a: d101 bne.n 8010920 { return HAL_ERROR; 801091c: 2301 movs r3, #1 801091e: e01b b.n 8010958 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8010920: 687b ldr r3, [r7, #4] 8010922: 681b ldr r3, [r3, #0] 8010924: 685a ldr r2, [r3, #4] 8010926: 687b ldr r3, [r7, #4] 8010928: 681b ldr r3, [r3, #0] 801092a: f422 4290 bic.w r2, r2, #18432 @ 0x4800 801092e: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8010930: 687b ldr r3, [r7, #4] 8010932: 681b ldr r3, [r3, #0] 8010934: 689a ldr r2, [r3, #8] 8010936: 687b ldr r3, [r7, #4] 8010938: 681b ldr r3, [r3, #0] 801093a: f022 022a bic.w r2, r2, #42 @ 0x2a 801093e: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 8010940: 687b ldr r3, [r7, #4] 8010942: 681b ldr r3, [r3, #0] 8010944: 681a ldr r2, [r3, #0] 8010946: 687b ldr r3, [r7, #4] 8010948: 681b ldr r3, [r3, #0] 801094a: f042 0201 orr.w r2, r2, #1 801094e: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 8010950: 6878 ldr r0, [r7, #4] 8010952: f001 faf5 bl 8011f40 8010956: 4603 mov r3, r0 } 8010958: 4618 mov r0, r3 801095a: 3708 adds r7, #8 801095c: 46bd mov sp, r7 801095e: bd80 pop {r7, pc} 08010960 : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8010960: b580 push {r7, lr} 8010962: b08a sub sp, #40 @ 0x28 8010964: af02 add r7, sp, #8 8010966: 60f8 str r0, [r7, #12] 8010968: 60b9 str r1, [r7, #8] 801096a: 603b str r3, [r7, #0] 801096c: 4613 mov r3, r2 801096e: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8010970: 68fb ldr r3, [r7, #12] 8010972: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8010976: 2b20 cmp r3, #32 8010978: d17b bne.n 8010a72 { if ((pData == NULL) || (Size == 0U)) 801097a: 68bb ldr r3, [r7, #8] 801097c: 2b00 cmp r3, #0 801097e: d002 beq.n 8010986 8010980: 88fb ldrh r3, [r7, #6] 8010982: 2b00 cmp r3, #0 8010984: d101 bne.n 801098a { return HAL_ERROR; 8010986: 2301 movs r3, #1 8010988: e074 b.n 8010a74 } huart->ErrorCode = HAL_UART_ERROR_NONE; 801098a: 68fb ldr r3, [r7, #12] 801098c: 2200 movs r2, #0 801098e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 8010992: 68fb ldr r3, [r7, #12] 8010994: 2221 movs r2, #33 @ 0x21 8010996: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 801099a: f7f4 fd1f bl 80053dc 801099e: 6178 str r0, [r7, #20] huart->TxXferSize = Size; 80109a0: 68fb ldr r3, [r7, #12] 80109a2: 88fa ldrh r2, [r7, #6] 80109a4: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 80109a8: 68fb ldr r3, [r7, #12] 80109aa: 88fa ldrh r2, [r7, #6] 80109ac: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80109b0: 68fb ldr r3, [r7, #12] 80109b2: 689b ldr r3, [r3, #8] 80109b4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80109b8: d108 bne.n 80109cc 80109ba: 68fb ldr r3, [r7, #12] 80109bc: 691b ldr r3, [r3, #16] 80109be: 2b00 cmp r3, #0 80109c0: d104 bne.n 80109cc { pdata8bits = NULL; 80109c2: 2300 movs r3, #0 80109c4: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 80109c6: 68bb ldr r3, [r7, #8] 80109c8: 61bb str r3, [r7, #24] 80109ca: e003 b.n 80109d4 } else { pdata8bits = pData; 80109cc: 68bb ldr r3, [r7, #8] 80109ce: 61fb str r3, [r7, #28] pdata16bits = NULL; 80109d0: 2300 movs r3, #0 80109d2: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 80109d4: e030 b.n 8010a38 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 80109d6: 683b ldr r3, [r7, #0] 80109d8: 9300 str r3, [sp, #0] 80109da: 697b ldr r3, [r7, #20] 80109dc: 2200 movs r2, #0 80109de: 2180 movs r1, #128 @ 0x80 80109e0: 68f8 ldr r0, [r7, #12] 80109e2: f001 fb57 bl 8012094 80109e6: 4603 mov r3, r0 80109e8: 2b00 cmp r3, #0 80109ea: d005 beq.n 80109f8 { huart->gState = HAL_UART_STATE_READY; 80109ec: 68fb ldr r3, [r7, #12] 80109ee: 2220 movs r2, #32 80109f0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 80109f4: 2303 movs r3, #3 80109f6: e03d b.n 8010a74 } if (pdata8bits == NULL) 80109f8: 69fb ldr r3, [r7, #28] 80109fa: 2b00 cmp r3, #0 80109fc: d10b bne.n 8010a16 { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); 80109fe: 69bb ldr r3, [r7, #24] 8010a00: 881b ldrh r3, [r3, #0] 8010a02: 461a mov r2, r3 8010a04: 68fb ldr r3, [r7, #12] 8010a06: 681b ldr r3, [r3, #0] 8010a08: f3c2 0208 ubfx r2, r2, #0, #9 8010a0c: 629a str r2, [r3, #40] @ 0x28 pdata16bits++; 8010a0e: 69bb ldr r3, [r7, #24] 8010a10: 3302 adds r3, #2 8010a12: 61bb str r3, [r7, #24] 8010a14: e007 b.n 8010a26 } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); 8010a16: 69fb ldr r3, [r7, #28] 8010a18: 781a ldrb r2, [r3, #0] 8010a1a: 68fb ldr r3, [r7, #12] 8010a1c: 681b ldr r3, [r3, #0] 8010a1e: 629a str r2, [r3, #40] @ 0x28 pdata8bits++; 8010a20: 69fb ldr r3, [r7, #28] 8010a22: 3301 adds r3, #1 8010a24: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8010a26: 68fb ldr r3, [r7, #12] 8010a28: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8010a2c: b29b uxth r3, r3 8010a2e: 3b01 subs r3, #1 8010a30: b29a uxth r2, r3 8010a32: 68fb ldr r3, [r7, #12] 8010a34: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 while (huart->TxXferCount > 0U) 8010a38: 68fb ldr r3, [r7, #12] 8010a3a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8010a3e: b29b uxth r3, r3 8010a40: 2b00 cmp r3, #0 8010a42: d1c8 bne.n 80109d6 } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8010a44: 683b ldr r3, [r7, #0] 8010a46: 9300 str r3, [sp, #0] 8010a48: 697b ldr r3, [r7, #20] 8010a4a: 2200 movs r2, #0 8010a4c: 2140 movs r1, #64 @ 0x40 8010a4e: 68f8 ldr r0, [r7, #12] 8010a50: f001 fb20 bl 8012094 8010a54: 4603 mov r3, r0 8010a56: 2b00 cmp r3, #0 8010a58: d005 beq.n 8010a66 { huart->gState = HAL_UART_STATE_READY; 8010a5a: 68fb ldr r3, [r7, #12] 8010a5c: 2220 movs r2, #32 8010a5e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_TIMEOUT; 8010a62: 2303 movs r3, #3 8010a64: e006 b.n 8010a74 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8010a66: 68fb ldr r3, [r7, #12] 8010a68: 2220 movs r2, #32 8010a6a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 return HAL_OK; 8010a6e: 2300 movs r3, #0 8010a70: e000 b.n 8010a74 } else { return HAL_BUSY; 8010a72: 2302 movs r3, #2 } } 8010a74: 4618 mov r0, r3 8010a76: 3720 adds r7, #32 8010a78: 46bd mov sp, r7 8010a7a: bd80 pop {r7, pc} 08010a7c : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8010a7c: b480 push {r7} 8010a7e: b091 sub sp, #68 @ 0x44 8010a80: af00 add r7, sp, #0 8010a82: 60f8 str r0, [r7, #12] 8010a84: 60b9 str r1, [r7, #8] 8010a86: 4613 mov r3, r2 8010a88: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8010a8a: 68fb ldr r3, [r7, #12] 8010a8c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8010a90: 2b20 cmp r3, #32 8010a92: d178 bne.n 8010b86 { if ((pData == NULL) || (Size == 0U)) 8010a94: 68bb ldr r3, [r7, #8] 8010a96: 2b00 cmp r3, #0 8010a98: d002 beq.n 8010aa0 8010a9a: 88fb ldrh r3, [r7, #6] 8010a9c: 2b00 cmp r3, #0 8010a9e: d101 bne.n 8010aa4 { return HAL_ERROR; 8010aa0: 2301 movs r3, #1 8010aa2: e071 b.n 8010b88 } huart->pTxBuffPtr = pData; 8010aa4: 68fb ldr r3, [r7, #12] 8010aa6: 68ba ldr r2, [r7, #8] 8010aa8: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 8010aaa: 68fb ldr r3, [r7, #12] 8010aac: 88fa ldrh r2, [r7, #6] 8010aae: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8010ab2: 68fb ldr r3, [r7, #12] 8010ab4: 88fa ldrh r2, [r7, #6] 8010ab6: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 8010aba: 68fb ldr r3, [r7, #12] 8010abc: 2200 movs r2, #0 8010abe: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 8010ac0: 68fb ldr r3, [r7, #12] 8010ac2: 2200 movs r2, #0 8010ac4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 8010ac8: 68fb ldr r3, [r7, #12] 8010aca: 2221 movs r2, #33 @ 0x21 8010acc: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 8010ad0: 68fb ldr r3, [r7, #12] 8010ad2: 6e5b ldr r3, [r3, #100] @ 0x64 8010ad4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8010ad8: d12a bne.n 8010b30 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8010ada: 68fb ldr r3, [r7, #12] 8010adc: 689b ldr r3, [r3, #8] 8010ade: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010ae2: d107 bne.n 8010af4 8010ae4: 68fb ldr r3, [r7, #12] 8010ae6: 691b ldr r3, [r3, #16] 8010ae8: 2b00 cmp r3, #0 8010aea: d103 bne.n 8010af4 { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 8010aec: 68fb ldr r3, [r7, #12] 8010aee: 4a29 ldr r2, [pc, #164] @ (8010b94 ) 8010af0: 679a str r2, [r3, #120] @ 0x78 8010af2: e002 b.n 8010afa } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 8010af4: 68fb ldr r3, [r7, #12] 8010af6: 4a28 ldr r2, [pc, #160] @ (8010b98 ) 8010af8: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 8010afa: 68fb ldr r3, [r7, #12] 8010afc: 681b ldr r3, [r3, #0] 8010afe: 3308 adds r3, #8 8010b00: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010b02: 6abb ldr r3, [r7, #40] @ 0x28 8010b04: e853 3f00 ldrex r3, [r3] 8010b08: 627b str r3, [r7, #36] @ 0x24 return(result); 8010b0a: 6a7b ldr r3, [r7, #36] @ 0x24 8010b0c: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8010b10: 63bb str r3, [r7, #56] @ 0x38 8010b12: 68fb ldr r3, [r7, #12] 8010b14: 681b ldr r3, [r3, #0] 8010b16: 3308 adds r3, #8 8010b18: 6bba ldr r2, [r7, #56] @ 0x38 8010b1a: 637a str r2, [r7, #52] @ 0x34 8010b1c: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010b1e: 6b39 ldr r1, [r7, #48] @ 0x30 8010b20: 6b7a ldr r2, [r7, #52] @ 0x34 8010b22: e841 2300 strex r3, r2, [r1] 8010b26: 62fb str r3, [r7, #44] @ 0x2c return(result); 8010b28: 6afb ldr r3, [r7, #44] @ 0x2c 8010b2a: 2b00 cmp r3, #0 8010b2c: d1e5 bne.n 8010afa 8010b2e: e028 b.n 8010b82 } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8010b30: 68fb ldr r3, [r7, #12] 8010b32: 689b ldr r3, [r3, #8] 8010b34: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010b38: d107 bne.n 8010b4a 8010b3a: 68fb ldr r3, [r7, #12] 8010b3c: 691b ldr r3, [r3, #16] 8010b3e: 2b00 cmp r3, #0 8010b40: d103 bne.n 8010b4a { huart->TxISR = UART_TxISR_16BIT; 8010b42: 68fb ldr r3, [r7, #12] 8010b44: 4a15 ldr r2, [pc, #84] @ (8010b9c ) 8010b46: 679a str r2, [r3, #120] @ 0x78 8010b48: e002 b.n 8010b50 } else { huart->TxISR = UART_TxISR_8BIT; 8010b4a: 68fb ldr r3, [r7, #12] 8010b4c: 4a14 ldr r2, [pc, #80] @ (8010ba0 ) 8010b4e: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8010b50: 68fb ldr r3, [r7, #12] 8010b52: 681b ldr r3, [r3, #0] 8010b54: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010b56: 697b ldr r3, [r7, #20] 8010b58: e853 3f00 ldrex r3, [r3] 8010b5c: 613b str r3, [r7, #16] return(result); 8010b5e: 693b ldr r3, [r7, #16] 8010b60: f043 0380 orr.w r3, r3, #128 @ 0x80 8010b64: 63fb str r3, [r7, #60] @ 0x3c 8010b66: 68fb ldr r3, [r7, #12] 8010b68: 681b ldr r3, [r3, #0] 8010b6a: 461a mov r2, r3 8010b6c: 6bfb ldr r3, [r7, #60] @ 0x3c 8010b6e: 623b str r3, [r7, #32] 8010b70: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010b72: 69f9 ldr r1, [r7, #28] 8010b74: 6a3a ldr r2, [r7, #32] 8010b76: e841 2300 strex r3, r2, [r1] 8010b7a: 61bb str r3, [r7, #24] return(result); 8010b7c: 69bb ldr r3, [r7, #24] 8010b7e: 2b00 cmp r3, #0 8010b80: d1e6 bne.n 8010b50 } return HAL_OK; 8010b82: 2300 movs r3, #0 8010b84: e000 b.n 8010b88 } else { return HAL_BUSY; 8010b86: 2302 movs r3, #2 } } 8010b88: 4618 mov r0, r3 8010b8a: 3744 adds r7, #68 @ 0x44 8010b8c: 46bd mov sp, r7 8010b8e: f85d 7b04 ldr.w r7, [sp], #4 8010b92: 4770 bx lr 8010b94: 08012707 .word 0x08012707 8010b98: 08012627 .word 0x08012627 8010b9c: 08012565 .word 0x08012565 8010ba0: 080124ad .word 0x080124ad 08010ba4 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8010ba4: b580 push {r7, lr} 8010ba6: b0ba sub sp, #232 @ 0xe8 8010ba8: af00 add r7, sp, #0 8010baa: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8010bac: 687b ldr r3, [r7, #4] 8010bae: 681b ldr r3, [r3, #0] 8010bb0: 69db ldr r3, [r3, #28] 8010bb2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8010bb6: 687b ldr r3, [r7, #4] 8010bb8: 681b ldr r3, [r3, #0] 8010bba: 681b ldr r3, [r3, #0] 8010bbc: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8010bc0: 687b ldr r3, [r7, #4] 8010bc2: 681b ldr r3, [r3, #0] 8010bc4: 689b ldr r3, [r3, #8] 8010bc6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 8010bca: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 8010bce: f640 030f movw r3, #2063 @ 0x80f 8010bd2: 4013 ands r3, r2 8010bd4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 8010bd8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8010bdc: 2b00 cmp r3, #0 8010bde: d11b bne.n 8010c18 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8010be0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010be4: f003 0320 and.w r3, r3, #32 8010be8: 2b00 cmp r3, #0 8010bea: d015 beq.n 8010c18 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8010bec: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010bf0: f003 0320 and.w r3, r3, #32 8010bf4: 2b00 cmp r3, #0 8010bf6: d105 bne.n 8010c04 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8010bf8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010bfc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010c00: 2b00 cmp r3, #0 8010c02: d009 beq.n 8010c18 { if (huart->RxISR != NULL) 8010c04: 687b ldr r3, [r7, #4] 8010c06: 6f5b ldr r3, [r3, #116] @ 0x74 8010c08: 2b00 cmp r3, #0 8010c0a: f000 8377 beq.w 80112fc { huart->RxISR(huart); 8010c0e: 687b ldr r3, [r7, #4] 8010c10: 6f5b ldr r3, [r3, #116] @ 0x74 8010c12: 6878 ldr r0, [r7, #4] 8010c14: 4798 blx r3 } return; 8010c16: e371 b.n 80112fc } } /* If some errors occur */ if ((errorflags != 0U) 8010c18: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8010c1c: 2b00 cmp r3, #0 8010c1e: f000 8123 beq.w 8010e68 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 8010c22: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8010c26: 4b8d ldr r3, [pc, #564] @ (8010e5c ) 8010c28: 4013 ands r3, r2 8010c2a: 2b00 cmp r3, #0 8010c2c: d106 bne.n 8010c3c || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8010c2e: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 8010c32: 4b8b ldr r3, [pc, #556] @ (8010e60 ) 8010c34: 4013 ands r3, r2 8010c36: 2b00 cmp r3, #0 8010c38: f000 8116 beq.w 8010e68 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8010c3c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010c40: f003 0301 and.w r3, r3, #1 8010c44: 2b00 cmp r3, #0 8010c46: d011 beq.n 8010c6c 8010c48: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010c4c: f403 7380 and.w r3, r3, #256 @ 0x100 8010c50: 2b00 cmp r3, #0 8010c52: d00b beq.n 8010c6c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8010c54: 687b ldr r3, [r7, #4] 8010c56: 681b ldr r3, [r3, #0] 8010c58: 2201 movs r2, #1 8010c5a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8010c5c: 687b ldr r3, [r7, #4] 8010c5e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c62: f043 0201 orr.w r2, r3, #1 8010c66: 687b ldr r3, [r7, #4] 8010c68: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8010c6c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010c70: f003 0302 and.w r3, r3, #2 8010c74: 2b00 cmp r3, #0 8010c76: d011 beq.n 8010c9c 8010c78: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010c7c: f003 0301 and.w r3, r3, #1 8010c80: 2b00 cmp r3, #0 8010c82: d00b beq.n 8010c9c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8010c84: 687b ldr r3, [r7, #4] 8010c86: 681b ldr r3, [r3, #0] 8010c88: 2202 movs r2, #2 8010c8a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8010c8c: 687b ldr r3, [r7, #4] 8010c8e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010c92: f043 0204 orr.w r2, r3, #4 8010c96: 687b ldr r3, [r7, #4] 8010c98: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8010c9c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010ca0: f003 0304 and.w r3, r3, #4 8010ca4: 2b00 cmp r3, #0 8010ca6: d011 beq.n 8010ccc 8010ca8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010cac: f003 0301 and.w r3, r3, #1 8010cb0: 2b00 cmp r3, #0 8010cb2: d00b beq.n 8010ccc { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8010cb4: 687b ldr r3, [r7, #4] 8010cb6: 681b ldr r3, [r3, #0] 8010cb8: 2204 movs r2, #4 8010cba: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8010cbc: 687b ldr r3, [r7, #4] 8010cbe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010cc2: f043 0202 orr.w r2, r3, #2 8010cc6: 687b ldr r3, [r7, #4] 8010cc8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 8010ccc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010cd0: f003 0308 and.w r3, r3, #8 8010cd4: 2b00 cmp r3, #0 8010cd6: d017 beq.n 8010d08 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8010cd8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010cdc: f003 0320 and.w r3, r3, #32 8010ce0: 2b00 cmp r3, #0 8010ce2: d105 bne.n 8010cf0 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 8010ce4: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8010ce8: 4b5c ldr r3, [pc, #368] @ (8010e5c ) 8010cea: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 8010cec: 2b00 cmp r3, #0 8010cee: d00b beq.n 8010d08 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8010cf0: 687b ldr r3, [r7, #4] 8010cf2: 681b ldr r3, [r3, #0] 8010cf4: 2208 movs r2, #8 8010cf6: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 8010cf8: 687b ldr r3, [r7, #4] 8010cfa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010cfe: f043 0208 orr.w r2, r3, #8 8010d02: 687b ldr r3, [r7, #4] 8010d04: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 8010d08: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010d0c: f403 6300 and.w r3, r3, #2048 @ 0x800 8010d10: 2b00 cmp r3, #0 8010d12: d012 beq.n 8010d3a 8010d14: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010d18: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8010d1c: 2b00 cmp r3, #0 8010d1e: d00c beq.n 8010d3a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8010d20: 687b ldr r3, [r7, #4] 8010d22: 681b ldr r3, [r3, #0] 8010d24: f44f 6200 mov.w r2, #2048 @ 0x800 8010d28: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8010d2a: 687b ldr r3, [r7, #4] 8010d2c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010d30: f043 0220 orr.w r2, r3, #32 8010d34: 687b ldr r3, [r7, #4] 8010d36: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8010d3a: 687b ldr r3, [r7, #4] 8010d3c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010d40: 2b00 cmp r3, #0 8010d42: f000 82dd beq.w 8011300 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8010d46: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010d4a: f003 0320 and.w r3, r3, #32 8010d4e: 2b00 cmp r3, #0 8010d50: d013 beq.n 8010d7a && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8010d52: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010d56: f003 0320 and.w r3, r3, #32 8010d5a: 2b00 cmp r3, #0 8010d5c: d105 bne.n 8010d6a || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8010d5e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8010d62: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8010d66: 2b00 cmp r3, #0 8010d68: d007 beq.n 8010d7a { if (huart->RxISR != NULL) 8010d6a: 687b ldr r3, [r7, #4] 8010d6c: 6f5b ldr r3, [r3, #116] @ 0x74 8010d6e: 2b00 cmp r3, #0 8010d70: d003 beq.n 8010d7a { huart->RxISR(huart); 8010d72: 687b ldr r3, [r7, #4] 8010d74: 6f5b ldr r3, [r3, #116] @ 0x74 8010d76: 6878 ldr r0, [r7, #4] 8010d78: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 8010d7a: 687b ldr r3, [r7, #4] 8010d7c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8010d80: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8010d84: 687b ldr r3, [r7, #4] 8010d86: 681b ldr r3, [r3, #0] 8010d88: 689b ldr r3, [r3, #8] 8010d8a: f003 0340 and.w r3, r3, #64 @ 0x40 8010d8e: 2b40 cmp r3, #64 @ 0x40 8010d90: d005 beq.n 8010d9e ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8010d92: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8010d96: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8010d9a: 2b00 cmp r3, #0 8010d9c: d054 beq.n 8010e48 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8010d9e: 6878 ldr r0, [r7, #4] 8010da0: f001 fb08 bl 80123b4 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010da4: 687b ldr r3, [r7, #4] 8010da6: 681b ldr r3, [r3, #0] 8010da8: 689b ldr r3, [r3, #8] 8010daa: f003 0340 and.w r3, r3, #64 @ 0x40 8010dae: 2b40 cmp r3, #64 @ 0x40 8010db0: d146 bne.n 8010e40 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8010db2: 687b ldr r3, [r7, #4] 8010db4: 681b ldr r3, [r3, #0] 8010db6: 3308 adds r3, #8 8010db8: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010dbc: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8010dc0: e853 3f00 ldrex r3, [r3] 8010dc4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 8010dc8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8010dcc: f023 0340 bic.w r3, r3, #64 @ 0x40 8010dd0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8010dd4: 687b ldr r3, [r7, #4] 8010dd6: 681b ldr r3, [r3, #0] 8010dd8: 3308 adds r3, #8 8010dda: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8010dde: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 8010de2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8010de6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 8010dea: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 8010dee: e841 2300 strex r3, r2, [r1] 8010df2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 8010df6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8010dfa: 2b00 cmp r3, #0 8010dfc: d1d9 bne.n 8010db2 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 8010dfe: 687b ldr r3, [r7, #4] 8010e00: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e04: 2b00 cmp r3, #0 8010e06: d017 beq.n 8010e38 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 8010e08: 687b ldr r3, [r7, #4] 8010e0a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e0e: 4a15 ldr r2, [pc, #84] @ (8010e64 ) 8010e10: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 8010e12: 687b ldr r3, [r7, #4] 8010e14: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e18: 4618 mov r0, r3 8010e1a: f7f7 ff5f bl 8008cdc 8010e1e: 4603 mov r3, r0 8010e20: 2b00 cmp r3, #0 8010e22: d019 beq.n 8010e58 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8010e24: 687b ldr r3, [r7, #4] 8010e26: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010e2a: 6d1b ldr r3, [r3, #80] @ 0x50 8010e2c: 687a ldr r2, [r7, #4] 8010e2e: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 8010e32: 4610 mov r0, r2 8010e34: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010e36: e00f b.n 8010e58 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010e38: 6878 ldr r0, [r7, #4] 8010e3a: f000 fa6d bl 8011318 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010e3e: e00b b.n 8010e58 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010e40: 6878 ldr r0, [r7, #4] 8010e42: f000 fa69 bl 8011318 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010e46: e007 b.n 8010e58 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8010e48: 6878 ldr r0, [r7, #4] 8010e4a: f000 fa65 bl 8011318 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8010e4e: 687b ldr r3, [r7, #4] 8010e50: 2200 movs r2, #0 8010e52: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 8010e56: e253 b.n 8011300 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010e58: bf00 nop return; 8010e5a: e251 b.n 8011300 8010e5c: 10000001 .word 0x10000001 8010e60: 04000120 .word 0x04000120 8010e64: 08012481 .word 0x08012481 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8010e68: 687b ldr r3, [r7, #4] 8010e6a: 6edb ldr r3, [r3, #108] @ 0x6c 8010e6c: 2b01 cmp r3, #1 8010e6e: f040 81e7 bne.w 8011240 && ((isrflags & USART_ISR_IDLE) != 0U) 8010e72: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8010e76: f003 0310 and.w r3, r3, #16 8010e7a: 2b00 cmp r3, #0 8010e7c: f000 81e0 beq.w 8011240 && ((cr1its & USART_ISR_IDLE) != 0U)) 8010e80: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8010e84: f003 0310 and.w r3, r3, #16 8010e88: 2b00 cmp r3, #0 8010e8a: f000 81d9 beq.w 8011240 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8010e8e: 687b ldr r3, [r7, #4] 8010e90: 681b ldr r3, [r3, #0] 8010e92: 2210 movs r2, #16 8010e94: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8010e96: 687b ldr r3, [r7, #4] 8010e98: 681b ldr r3, [r3, #0] 8010e9a: 689b ldr r3, [r3, #8] 8010e9c: f003 0340 and.w r3, r3, #64 @ 0x40 8010ea0: 2b40 cmp r3, #64 @ 0x40 8010ea2: f040 8151 bne.w 8011148 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8010ea6: 687b ldr r3, [r7, #4] 8010ea8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010eac: 681b ldr r3, [r3, #0] 8010eae: 4a96 ldr r2, [pc, #600] @ (8011108 ) 8010eb0: 4293 cmp r3, r2 8010eb2: d068 beq.n 8010f86 8010eb4: 687b ldr r3, [r7, #4] 8010eb6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010eba: 681b ldr r3, [r3, #0] 8010ebc: 4a93 ldr r2, [pc, #588] @ (801110c ) 8010ebe: 4293 cmp r3, r2 8010ec0: d061 beq.n 8010f86 8010ec2: 687b ldr r3, [r7, #4] 8010ec4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ec8: 681b ldr r3, [r3, #0] 8010eca: 4a91 ldr r2, [pc, #580] @ (8011110 ) 8010ecc: 4293 cmp r3, r2 8010ece: d05a beq.n 8010f86 8010ed0: 687b ldr r3, [r7, #4] 8010ed2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ed6: 681b ldr r3, [r3, #0] 8010ed8: 4a8e ldr r2, [pc, #568] @ (8011114 ) 8010eda: 4293 cmp r3, r2 8010edc: d053 beq.n 8010f86 8010ede: 687b ldr r3, [r7, #4] 8010ee0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ee4: 681b ldr r3, [r3, #0] 8010ee6: 4a8c ldr r2, [pc, #560] @ (8011118 ) 8010ee8: 4293 cmp r3, r2 8010eea: d04c beq.n 8010f86 8010eec: 687b ldr r3, [r7, #4] 8010eee: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010ef2: 681b ldr r3, [r3, #0] 8010ef4: 4a89 ldr r2, [pc, #548] @ (801111c ) 8010ef6: 4293 cmp r3, r2 8010ef8: d045 beq.n 8010f86 8010efa: 687b ldr r3, [r7, #4] 8010efc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f00: 681b ldr r3, [r3, #0] 8010f02: 4a87 ldr r2, [pc, #540] @ (8011120 ) 8010f04: 4293 cmp r3, r2 8010f06: d03e beq.n 8010f86 8010f08: 687b ldr r3, [r7, #4] 8010f0a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f0e: 681b ldr r3, [r3, #0] 8010f10: 4a84 ldr r2, [pc, #528] @ (8011124 ) 8010f12: 4293 cmp r3, r2 8010f14: d037 beq.n 8010f86 8010f16: 687b ldr r3, [r7, #4] 8010f18: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f1c: 681b ldr r3, [r3, #0] 8010f1e: 4a82 ldr r2, [pc, #520] @ (8011128 ) 8010f20: 4293 cmp r3, r2 8010f22: d030 beq.n 8010f86 8010f24: 687b ldr r3, [r7, #4] 8010f26: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f2a: 681b ldr r3, [r3, #0] 8010f2c: 4a7f ldr r2, [pc, #508] @ (801112c ) 8010f2e: 4293 cmp r3, r2 8010f30: d029 beq.n 8010f86 8010f32: 687b ldr r3, [r7, #4] 8010f34: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f38: 681b ldr r3, [r3, #0] 8010f3a: 4a7d ldr r2, [pc, #500] @ (8011130 ) 8010f3c: 4293 cmp r3, r2 8010f3e: d022 beq.n 8010f86 8010f40: 687b ldr r3, [r7, #4] 8010f42: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f46: 681b ldr r3, [r3, #0] 8010f48: 4a7a ldr r2, [pc, #488] @ (8011134 ) 8010f4a: 4293 cmp r3, r2 8010f4c: d01b beq.n 8010f86 8010f4e: 687b ldr r3, [r7, #4] 8010f50: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f54: 681b ldr r3, [r3, #0] 8010f56: 4a78 ldr r2, [pc, #480] @ (8011138 ) 8010f58: 4293 cmp r3, r2 8010f5a: d014 beq.n 8010f86 8010f5c: 687b ldr r3, [r7, #4] 8010f5e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f62: 681b ldr r3, [r3, #0] 8010f64: 4a75 ldr r2, [pc, #468] @ (801113c ) 8010f66: 4293 cmp r3, r2 8010f68: d00d beq.n 8010f86 8010f6a: 687b ldr r3, [r7, #4] 8010f6c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f70: 681b ldr r3, [r3, #0] 8010f72: 4a73 ldr r2, [pc, #460] @ (8011140 ) 8010f74: 4293 cmp r3, r2 8010f76: d006 beq.n 8010f86 8010f78: 687b ldr r3, [r7, #4] 8010f7a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f7e: 681b ldr r3, [r3, #0] 8010f80: 4a70 ldr r2, [pc, #448] @ (8011144 ) 8010f82: 4293 cmp r3, r2 8010f84: d106 bne.n 8010f94 8010f86: 687b ldr r3, [r7, #4] 8010f88: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f8c: 681b ldr r3, [r3, #0] 8010f8e: 685b ldr r3, [r3, #4] 8010f90: b29b uxth r3, r3 8010f92: e005 b.n 8010fa0 8010f94: 687b ldr r3, [r7, #4] 8010f96: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010f9a: 681b ldr r3, [r3, #0] 8010f9c: 685b ldr r3, [r3, #4] 8010f9e: b29b uxth r3, r3 8010fa0: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8010fa4: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8010fa8: 2b00 cmp r3, #0 8010faa: f000 81ab beq.w 8011304 && (nb_remaining_rx_data < huart->RxXferSize)) 8010fae: 687b ldr r3, [r7, #4] 8010fb0: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8010fb4: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8010fb8: 429a cmp r2, r3 8010fba: f080 81a3 bcs.w 8011304 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 8010fbe: 687b ldr r3, [r7, #4] 8010fc0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8010fc4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 8010fc8: 687b ldr r3, [r7, #4] 8010fca: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8010fce: 69db ldr r3, [r3, #28] 8010fd0: f5b3 7f80 cmp.w r3, #256 @ 0x100 8010fd4: f000 8087 beq.w 80110e6 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8010fd8: 687b ldr r3, [r7, #4] 8010fda: 681b ldr r3, [r3, #0] 8010fdc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8010fe0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8010fe4: e853 3f00 ldrex r3, [r3] 8010fe8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 8010fec: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8010ff0: f423 7380 bic.w r3, r3, #256 @ 0x100 8010ff4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8010ff8: 687b ldr r3, [r7, #4] 8010ffa: 681b ldr r3, [r3, #0] 8010ffc: 461a mov r2, r3 8010ffe: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 8011002: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8011006: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801100a: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 801100e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8011012: e841 2300 strex r3, r2, [r1] 8011016: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 801101a: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 801101e: 2b00 cmp r3, #0 8011020: d1da bne.n 8010fd8 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8011022: 687b ldr r3, [r7, #4] 8011024: 681b ldr r3, [r3, #0] 8011026: 3308 adds r3, #8 8011028: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801102a: 6f7b ldr r3, [r7, #116] @ 0x74 801102c: e853 3f00 ldrex r3, [r3] 8011030: 673b str r3, [r7, #112] @ 0x70 return(result); 8011032: 6f3b ldr r3, [r7, #112] @ 0x70 8011034: f023 0301 bic.w r3, r3, #1 8011038: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 801103c: 687b ldr r3, [r7, #4] 801103e: 681b ldr r3, [r3, #0] 8011040: 3308 adds r3, #8 8011042: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8011046: f8c7 2080 str.w r2, [r7, #128] @ 0x80 801104a: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801104c: 6ff9 ldr r1, [r7, #124] @ 0x7c 801104e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8011052: e841 2300 strex r3, r2, [r1] 8011056: 67bb str r3, [r7, #120] @ 0x78 return(result); 8011058: 6fbb ldr r3, [r7, #120] @ 0x78 801105a: 2b00 cmp r3, #0 801105c: d1e1 bne.n 8011022 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801105e: 687b ldr r3, [r7, #4] 8011060: 681b ldr r3, [r3, #0] 8011062: 3308 adds r3, #8 8011064: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011066: 6e3b ldr r3, [r7, #96] @ 0x60 8011068: e853 3f00 ldrex r3, [r3] 801106c: 65fb str r3, [r7, #92] @ 0x5c return(result); 801106e: 6dfb ldr r3, [r7, #92] @ 0x5c 8011070: f023 0340 bic.w r3, r3, #64 @ 0x40 8011074: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8011078: 687b ldr r3, [r7, #4] 801107a: 681b ldr r3, [r3, #0] 801107c: 3308 adds r3, #8 801107e: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8011082: 66fa str r2, [r7, #108] @ 0x6c 8011084: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011086: 6eb9 ldr r1, [r7, #104] @ 0x68 8011088: 6efa ldr r2, [r7, #108] @ 0x6c 801108a: e841 2300 strex r3, r2, [r1] 801108e: 667b str r3, [r7, #100] @ 0x64 return(result); 8011090: 6e7b ldr r3, [r7, #100] @ 0x64 8011092: 2b00 cmp r3, #0 8011094: d1e3 bne.n 801105e /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011096: 687b ldr r3, [r7, #4] 8011098: 2220 movs r2, #32 801109a: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801109e: 687b ldr r3, [r7, #4] 80110a0: 2200 movs r2, #0 80110a2: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80110a4: 687b ldr r3, [r7, #4] 80110a6: 681b ldr r3, [r3, #0] 80110a8: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80110aa: 6cfb ldr r3, [r7, #76] @ 0x4c 80110ac: e853 3f00 ldrex r3, [r3] 80110b0: 64bb str r3, [r7, #72] @ 0x48 return(result); 80110b2: 6cbb ldr r3, [r7, #72] @ 0x48 80110b4: f023 0310 bic.w r3, r3, #16 80110b8: f8c7 30ac str.w r3, [r7, #172] @ 0xac 80110bc: 687b ldr r3, [r7, #4] 80110be: 681b ldr r3, [r3, #0] 80110c0: 461a mov r2, r3 80110c2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80110c6: 65bb str r3, [r7, #88] @ 0x58 80110c8: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80110ca: 6d79 ldr r1, [r7, #84] @ 0x54 80110cc: 6dba ldr r2, [r7, #88] @ 0x58 80110ce: e841 2300 strex r3, r2, [r1] 80110d2: 653b str r3, [r7, #80] @ 0x50 return(result); 80110d4: 6d3b ldr r3, [r7, #80] @ 0x50 80110d6: 2b00 cmp r3, #0 80110d8: d1e4 bne.n 80110a4 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 80110da: 687b ldr r3, [r7, #4] 80110dc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80110e0: 4618 mov r0, r3 80110e2: f7f7 fadd bl 80086a0 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 80110e6: 687b ldr r3, [r7, #4] 80110e8: 2202 movs r2, #2 80110ea: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80110ec: 687b ldr r3, [r7, #4] 80110ee: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 80110f2: 687b ldr r3, [r7, #4] 80110f4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80110f8: b29b uxth r3, r3 80110fa: 1ad3 subs r3, r2, r3 80110fc: b29b uxth r3, r3 80110fe: 4619 mov r1, r3 8011100: 6878 ldr r0, [r7, #4] 8011102: f7f3 f8d7 bl 80042b4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011106: e0fd b.n 8011304 8011108: 40020010 .word 0x40020010 801110c: 40020028 .word 0x40020028 8011110: 40020040 .word 0x40020040 8011114: 40020058 .word 0x40020058 8011118: 40020070 .word 0x40020070 801111c: 40020088 .word 0x40020088 8011120: 400200a0 .word 0x400200a0 8011124: 400200b8 .word 0x400200b8 8011128: 40020410 .word 0x40020410 801112c: 40020428 .word 0x40020428 8011130: 40020440 .word 0x40020440 8011134: 40020458 .word 0x40020458 8011138: 40020470 .word 0x40020470 801113c: 40020488 .word 0x40020488 8011140: 400204a0 .word 0x400204a0 8011144: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8011148: 687b ldr r3, [r7, #4] 801114a: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 801114e: 687b ldr r3, [r7, #4] 8011150: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011154: b29b uxth r3, r3 8011156: 1ad3 subs r3, r2, r3 8011158: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 801115c: 687b ldr r3, [r7, #4] 801115e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011162: b29b uxth r3, r3 8011164: 2b00 cmp r3, #0 8011166: f000 80cf beq.w 8011308 && (nb_rx_data > 0U)) 801116a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 801116e: 2b00 cmp r3, #0 8011170: f000 80ca beq.w 8011308 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011174: 687b ldr r3, [r7, #4] 8011176: 681b ldr r3, [r3, #0] 8011178: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801117a: 6bbb ldr r3, [r7, #56] @ 0x38 801117c: e853 3f00 ldrex r3, [r3] 8011180: 637b str r3, [r7, #52] @ 0x34 return(result); 8011182: 6b7b ldr r3, [r7, #52] @ 0x34 8011184: f423 7390 bic.w r3, r3, #288 @ 0x120 8011188: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 801118c: 687b ldr r3, [r7, #4] 801118e: 681b ldr r3, [r3, #0] 8011190: 461a mov r2, r3 8011192: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8011196: 647b str r3, [r7, #68] @ 0x44 8011198: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801119a: 6c39 ldr r1, [r7, #64] @ 0x40 801119c: 6c7a ldr r2, [r7, #68] @ 0x44 801119e: e841 2300 strex r3, r2, [r1] 80111a2: 63fb str r3, [r7, #60] @ 0x3c return(result); 80111a4: 6bfb ldr r3, [r7, #60] @ 0x3c 80111a6: 2b00 cmp r3, #0 80111a8: d1e4 bne.n 8011174 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80111aa: 687b ldr r3, [r7, #4] 80111ac: 681b ldr r3, [r3, #0] 80111ae: 3308 adds r3, #8 80111b0: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80111b2: 6a7b ldr r3, [r7, #36] @ 0x24 80111b4: e853 3f00 ldrex r3, [r3] 80111b8: 623b str r3, [r7, #32] return(result); 80111ba: 6a3a ldr r2, [r7, #32] 80111bc: 4b55 ldr r3, [pc, #340] @ (8011314 ) 80111be: 4013 ands r3, r2 80111c0: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 80111c4: 687b ldr r3, [r7, #4] 80111c6: 681b ldr r3, [r3, #0] 80111c8: 3308 adds r3, #8 80111ca: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 80111ce: 633a str r2, [r7, #48] @ 0x30 80111d0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80111d2: 6af9 ldr r1, [r7, #44] @ 0x2c 80111d4: 6b3a ldr r2, [r7, #48] @ 0x30 80111d6: e841 2300 strex r3, r2, [r1] 80111da: 62bb str r3, [r7, #40] @ 0x28 return(result); 80111dc: 6abb ldr r3, [r7, #40] @ 0x28 80111de: 2b00 cmp r3, #0 80111e0: d1e3 bne.n 80111aa /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80111e2: 687b ldr r3, [r7, #4] 80111e4: 2220 movs r2, #32 80111e6: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80111ea: 687b ldr r3, [r7, #4] 80111ec: 2200 movs r2, #0 80111ee: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80111f0: 687b ldr r3, [r7, #4] 80111f2: 2200 movs r2, #0 80111f4: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80111f6: 687b ldr r3, [r7, #4] 80111f8: 681b ldr r3, [r3, #0] 80111fa: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80111fc: 693b ldr r3, [r7, #16] 80111fe: e853 3f00 ldrex r3, [r3] 8011202: 60fb str r3, [r7, #12] return(result); 8011204: 68fb ldr r3, [r7, #12] 8011206: f023 0310 bic.w r3, r3, #16 801120a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 801120e: 687b ldr r3, [r7, #4] 8011210: 681b ldr r3, [r3, #0] 8011212: 461a mov r2, r3 8011214: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8011218: 61fb str r3, [r7, #28] 801121a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801121c: 69b9 ldr r1, [r7, #24] 801121e: 69fa ldr r2, [r7, #28] 8011220: e841 2300 strex r3, r2, [r1] 8011224: 617b str r3, [r7, #20] return(result); 8011226: 697b ldr r3, [r7, #20] 8011228: 2b00 cmp r3, #0 801122a: d1e4 bne.n 80111f6 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 801122c: 687b ldr r3, [r7, #4] 801122e: 2202 movs r2, #2 8011230: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8011232: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011236: 4619 mov r1, r3 8011238: 6878 ldr r0, [r7, #4] 801123a: f7f3 f83b bl 80042b4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 801123e: e063 b.n 8011308 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8011240: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011244: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8011248: 2b00 cmp r3, #0 801124a: d00e beq.n 801126a 801124c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011250: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011254: 2b00 cmp r3, #0 8011256: d008 beq.n 801126a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8011258: 687b ldr r3, [r7, #4] 801125a: 681b ldr r3, [r3, #0] 801125c: f44f 1280 mov.w r2, #1048576 @ 0x100000 8011260: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8011262: 6878 ldr r0, [r7, #4] 8011264: f002 f80c bl 8013280 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011268: e051 b.n 801130e } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 801126a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801126e: f003 0380 and.w r3, r3, #128 @ 0x80 8011272: 2b00 cmp r3, #0 8011274: d014 beq.n 80112a0 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8011276: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801127a: f003 0380 and.w r3, r3, #128 @ 0x80 801127e: 2b00 cmp r3, #0 8011280: d105 bne.n 801128e || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8011282: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011286: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801128a: 2b00 cmp r3, #0 801128c: d008 beq.n 80112a0 { if (huart->TxISR != NULL) 801128e: 687b ldr r3, [r7, #4] 8011290: 6f9b ldr r3, [r3, #120] @ 0x78 8011292: 2b00 cmp r3, #0 8011294: d03a beq.n 801130c { huart->TxISR(huart); 8011296: 687b ldr r3, [r7, #4] 8011298: 6f9b ldr r3, [r3, #120] @ 0x78 801129a: 6878 ldr r0, [r7, #4] 801129c: 4798 blx r3 } return; 801129e: e035 b.n 801130c } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 80112a0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80112a4: f003 0340 and.w r3, r3, #64 @ 0x40 80112a8: 2b00 cmp r3, #0 80112aa: d009 beq.n 80112c0 80112ac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80112b0: f003 0340 and.w r3, r3, #64 @ 0x40 80112b4: 2b00 cmp r3, #0 80112b6: d003 beq.n 80112c0 { UART_EndTransmit_IT(huart); 80112b8: 6878 ldr r0, [r7, #4] 80112ba: f001 fa99 bl 80127f0 return; 80112be: e026 b.n 801130e } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 80112c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80112c4: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80112c8: 2b00 cmp r3, #0 80112ca: d009 beq.n 80112e0 80112cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80112d0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 80112d4: 2b00 cmp r3, #0 80112d6: d003 beq.n 80112e0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 80112d8: 6878 ldr r0, [r7, #4] 80112da: f001 ffe5 bl 80132a8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 80112de: e016 b.n 801130e } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 80112e0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80112e4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80112e8: 2b00 cmp r3, #0 80112ea: d010 beq.n 801130e 80112ec: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80112f0: 2b00 cmp r3, #0 80112f2: da0c bge.n 801130e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 80112f4: 6878 ldr r0, [r7, #4] 80112f6: f001 ffcd bl 8013294 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 80112fa: e008 b.n 801130e return; 80112fc: bf00 nop 80112fe: e006 b.n 801130e return; 8011300: bf00 nop 8011302: e004 b.n 801130e return; 8011304: bf00 nop 8011306: e002 b.n 801130e return; 8011308: bf00 nop 801130a: e000 b.n 801130e return; 801130c: bf00 nop } } 801130e: 37e8 adds r7, #232 @ 0xe8 8011310: 46bd mov sp, r7 8011312: bd80 pop {r7, pc} 8011314: effffffe .word 0xeffffffe 08011318 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8011318: b480 push {r7} 801131a: b083 sub sp, #12 801131c: af00 add r7, sp, #0 801131e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8011320: bf00 nop 8011322: 370c adds r7, #12 8011324: 46bd mov sp, r7 8011326: f85d 7b04 ldr.w r7, [sp], #4 801132a: 4770 bx lr 0801132c : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 801132c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8011330: b092 sub sp, #72 @ 0x48 8011332: af00 add r7, sp, #0 8011334: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8011336: 2300 movs r3, #0 8011338: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 801133c: 697b ldr r3, [r7, #20] 801133e: 689a ldr r2, [r3, #8] 8011340: 697b ldr r3, [r7, #20] 8011342: 691b ldr r3, [r3, #16] 8011344: 431a orrs r2, r3 8011346: 697b ldr r3, [r7, #20] 8011348: 695b ldr r3, [r3, #20] 801134a: 431a orrs r2, r3 801134c: 697b ldr r3, [r7, #20] 801134e: 69db ldr r3, [r3, #28] 8011350: 4313 orrs r3, r2 8011352: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8011354: 697b ldr r3, [r7, #20] 8011356: 681b ldr r3, [r3, #0] 8011358: 681a ldr r2, [r3, #0] 801135a: 4bbe ldr r3, [pc, #760] @ (8011654 ) 801135c: 4013 ands r3, r2 801135e: 697a ldr r2, [r7, #20] 8011360: 6812 ldr r2, [r2, #0] 8011362: 6c79 ldr r1, [r7, #68] @ 0x44 8011364: 430b orrs r3, r1 8011366: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8011368: 697b ldr r3, [r7, #20] 801136a: 681b ldr r3, [r3, #0] 801136c: 685b ldr r3, [r3, #4] 801136e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8011372: 697b ldr r3, [r7, #20] 8011374: 68da ldr r2, [r3, #12] 8011376: 697b ldr r3, [r7, #20] 8011378: 681b ldr r3, [r3, #0] 801137a: 430a orrs r2, r1 801137c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 801137e: 697b ldr r3, [r7, #20] 8011380: 699b ldr r3, [r3, #24] 8011382: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 8011384: 697b ldr r3, [r7, #20] 8011386: 681b ldr r3, [r3, #0] 8011388: 4ab3 ldr r2, [pc, #716] @ (8011658 ) 801138a: 4293 cmp r3, r2 801138c: d004 beq.n 8011398 { tmpreg |= huart->Init.OneBitSampling; 801138e: 697b ldr r3, [r7, #20] 8011390: 6a1b ldr r3, [r3, #32] 8011392: 6c7a ldr r2, [r7, #68] @ 0x44 8011394: 4313 orrs r3, r2 8011396: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8011398: 697b ldr r3, [r7, #20] 801139a: 681b ldr r3, [r3, #0] 801139c: 689a ldr r2, [r3, #8] 801139e: 4baf ldr r3, [pc, #700] @ (801165c ) 80113a0: 4013 ands r3, r2 80113a2: 697a ldr r2, [r7, #20] 80113a4: 6812 ldr r2, [r2, #0] 80113a6: 6c79 ldr r1, [r7, #68] @ 0x44 80113a8: 430b orrs r3, r1 80113aa: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 80113ac: 697b ldr r3, [r7, #20] 80113ae: 681b ldr r3, [r3, #0] 80113b0: 6adb ldr r3, [r3, #44] @ 0x2c 80113b2: f023 010f bic.w r1, r3, #15 80113b6: 697b ldr r3, [r7, #20] 80113b8: 6a5a ldr r2, [r3, #36] @ 0x24 80113ba: 697b ldr r3, [r7, #20] 80113bc: 681b ldr r3, [r3, #0] 80113be: 430a orrs r2, r1 80113c0: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 80113c2: 697b ldr r3, [r7, #20] 80113c4: 681b ldr r3, [r3, #0] 80113c6: 4aa6 ldr r2, [pc, #664] @ (8011660 ) 80113c8: 4293 cmp r3, r2 80113ca: d177 bne.n 80114bc 80113cc: 4ba5 ldr r3, [pc, #660] @ (8011664 ) 80113ce: 6d5b ldr r3, [r3, #84] @ 0x54 80113d0: f003 0338 and.w r3, r3, #56 @ 0x38 80113d4: 2b28 cmp r3, #40 @ 0x28 80113d6: d86d bhi.n 80114b4 80113d8: a201 add r2, pc, #4 @ (adr r2, 80113e0 ) 80113da: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80113de: bf00 nop 80113e0: 08011485 .word 0x08011485 80113e4: 080114b5 .word 0x080114b5 80113e8: 080114b5 .word 0x080114b5 80113ec: 080114b5 .word 0x080114b5 80113f0: 080114b5 .word 0x080114b5 80113f4: 080114b5 .word 0x080114b5 80113f8: 080114b5 .word 0x080114b5 80113fc: 080114b5 .word 0x080114b5 8011400: 0801148d .word 0x0801148d 8011404: 080114b5 .word 0x080114b5 8011408: 080114b5 .word 0x080114b5 801140c: 080114b5 .word 0x080114b5 8011410: 080114b5 .word 0x080114b5 8011414: 080114b5 .word 0x080114b5 8011418: 080114b5 .word 0x080114b5 801141c: 080114b5 .word 0x080114b5 8011420: 08011495 .word 0x08011495 8011424: 080114b5 .word 0x080114b5 8011428: 080114b5 .word 0x080114b5 801142c: 080114b5 .word 0x080114b5 8011430: 080114b5 .word 0x080114b5 8011434: 080114b5 .word 0x080114b5 8011438: 080114b5 .word 0x080114b5 801143c: 080114b5 .word 0x080114b5 8011440: 0801149d .word 0x0801149d 8011444: 080114b5 .word 0x080114b5 8011448: 080114b5 .word 0x080114b5 801144c: 080114b5 .word 0x080114b5 8011450: 080114b5 .word 0x080114b5 8011454: 080114b5 .word 0x080114b5 8011458: 080114b5 .word 0x080114b5 801145c: 080114b5 .word 0x080114b5 8011460: 080114a5 .word 0x080114a5 8011464: 080114b5 .word 0x080114b5 8011468: 080114b5 .word 0x080114b5 801146c: 080114b5 .word 0x080114b5 8011470: 080114b5 .word 0x080114b5 8011474: 080114b5 .word 0x080114b5 8011478: 080114b5 .word 0x080114b5 801147c: 080114b5 .word 0x080114b5 8011480: 080114ad .word 0x080114ad 8011484: 2301 movs r3, #1 8011486: f887 3043 strb.w r3, [r7, #67] @ 0x43 801148a: e222 b.n 80118d2 801148c: 2304 movs r3, #4 801148e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011492: e21e b.n 80118d2 8011494: 2308 movs r3, #8 8011496: f887 3043 strb.w r3, [r7, #67] @ 0x43 801149a: e21a b.n 80118d2 801149c: 2310 movs r3, #16 801149e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114a2: e216 b.n 80118d2 80114a4: 2320 movs r3, #32 80114a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114aa: e212 b.n 80118d2 80114ac: 2340 movs r3, #64 @ 0x40 80114ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114b2: e20e b.n 80118d2 80114b4: 2380 movs r3, #128 @ 0x80 80114b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114ba: e20a b.n 80118d2 80114bc: 697b ldr r3, [r7, #20] 80114be: 681b ldr r3, [r3, #0] 80114c0: 4a69 ldr r2, [pc, #420] @ (8011668 ) 80114c2: 4293 cmp r3, r2 80114c4: d130 bne.n 8011528 80114c6: 4b67 ldr r3, [pc, #412] @ (8011664 ) 80114c8: 6d5b ldr r3, [r3, #84] @ 0x54 80114ca: f003 0307 and.w r3, r3, #7 80114ce: 2b05 cmp r3, #5 80114d0: d826 bhi.n 8011520 80114d2: a201 add r2, pc, #4 @ (adr r2, 80114d8 ) 80114d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80114d8: 080114f1 .word 0x080114f1 80114dc: 080114f9 .word 0x080114f9 80114e0: 08011501 .word 0x08011501 80114e4: 08011509 .word 0x08011509 80114e8: 08011511 .word 0x08011511 80114ec: 08011519 .word 0x08011519 80114f0: 2300 movs r3, #0 80114f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114f6: e1ec b.n 80118d2 80114f8: 2304 movs r3, #4 80114fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80114fe: e1e8 b.n 80118d2 8011500: 2308 movs r3, #8 8011502: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011506: e1e4 b.n 80118d2 8011508: 2310 movs r3, #16 801150a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801150e: e1e0 b.n 80118d2 8011510: 2320 movs r3, #32 8011512: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011516: e1dc b.n 80118d2 8011518: 2340 movs r3, #64 @ 0x40 801151a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801151e: e1d8 b.n 80118d2 8011520: 2380 movs r3, #128 @ 0x80 8011522: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011526: e1d4 b.n 80118d2 8011528: 697b ldr r3, [r7, #20] 801152a: 681b ldr r3, [r3, #0] 801152c: 4a4f ldr r2, [pc, #316] @ (801166c ) 801152e: 4293 cmp r3, r2 8011530: d130 bne.n 8011594 8011532: 4b4c ldr r3, [pc, #304] @ (8011664 ) 8011534: 6d5b ldr r3, [r3, #84] @ 0x54 8011536: f003 0307 and.w r3, r3, #7 801153a: 2b05 cmp r3, #5 801153c: d826 bhi.n 801158c 801153e: a201 add r2, pc, #4 @ (adr r2, 8011544 ) 8011540: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011544: 0801155d .word 0x0801155d 8011548: 08011565 .word 0x08011565 801154c: 0801156d .word 0x0801156d 8011550: 08011575 .word 0x08011575 8011554: 0801157d .word 0x0801157d 8011558: 08011585 .word 0x08011585 801155c: 2300 movs r3, #0 801155e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011562: e1b6 b.n 80118d2 8011564: 2304 movs r3, #4 8011566: f887 3043 strb.w r3, [r7, #67] @ 0x43 801156a: e1b2 b.n 80118d2 801156c: 2308 movs r3, #8 801156e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011572: e1ae b.n 80118d2 8011574: 2310 movs r3, #16 8011576: f887 3043 strb.w r3, [r7, #67] @ 0x43 801157a: e1aa b.n 80118d2 801157c: 2320 movs r3, #32 801157e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011582: e1a6 b.n 80118d2 8011584: 2340 movs r3, #64 @ 0x40 8011586: f887 3043 strb.w r3, [r7, #67] @ 0x43 801158a: e1a2 b.n 80118d2 801158c: 2380 movs r3, #128 @ 0x80 801158e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011592: e19e b.n 80118d2 8011594: 697b ldr r3, [r7, #20] 8011596: 681b ldr r3, [r3, #0] 8011598: 4a35 ldr r2, [pc, #212] @ (8011670 ) 801159a: 4293 cmp r3, r2 801159c: d130 bne.n 8011600 801159e: 4b31 ldr r3, [pc, #196] @ (8011664 ) 80115a0: 6d5b ldr r3, [r3, #84] @ 0x54 80115a2: f003 0307 and.w r3, r3, #7 80115a6: 2b05 cmp r3, #5 80115a8: d826 bhi.n 80115f8 80115aa: a201 add r2, pc, #4 @ (adr r2, 80115b0 ) 80115ac: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80115b0: 080115c9 .word 0x080115c9 80115b4: 080115d1 .word 0x080115d1 80115b8: 080115d9 .word 0x080115d9 80115bc: 080115e1 .word 0x080115e1 80115c0: 080115e9 .word 0x080115e9 80115c4: 080115f1 .word 0x080115f1 80115c8: 2300 movs r3, #0 80115ca: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115ce: e180 b.n 80118d2 80115d0: 2304 movs r3, #4 80115d2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115d6: e17c b.n 80118d2 80115d8: 2308 movs r3, #8 80115da: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115de: e178 b.n 80118d2 80115e0: 2310 movs r3, #16 80115e2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115e6: e174 b.n 80118d2 80115e8: 2320 movs r3, #32 80115ea: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115ee: e170 b.n 80118d2 80115f0: 2340 movs r3, #64 @ 0x40 80115f2: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115f6: e16c b.n 80118d2 80115f8: 2380 movs r3, #128 @ 0x80 80115fa: f887 3043 strb.w r3, [r7, #67] @ 0x43 80115fe: e168 b.n 80118d2 8011600: 697b ldr r3, [r7, #20] 8011602: 681b ldr r3, [r3, #0] 8011604: 4a1b ldr r2, [pc, #108] @ (8011674 ) 8011606: 4293 cmp r3, r2 8011608: d142 bne.n 8011690 801160a: 4b16 ldr r3, [pc, #88] @ (8011664 ) 801160c: 6d5b ldr r3, [r3, #84] @ 0x54 801160e: f003 0307 and.w r3, r3, #7 8011612: 2b05 cmp r3, #5 8011614: d838 bhi.n 8011688 8011616: a201 add r2, pc, #4 @ (adr r2, 801161c ) 8011618: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801161c: 08011635 .word 0x08011635 8011620: 0801163d .word 0x0801163d 8011624: 08011645 .word 0x08011645 8011628: 0801164d .word 0x0801164d 801162c: 08011679 .word 0x08011679 8011630: 08011681 .word 0x08011681 8011634: 2300 movs r3, #0 8011636: f887 3043 strb.w r3, [r7, #67] @ 0x43 801163a: e14a b.n 80118d2 801163c: 2304 movs r3, #4 801163e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011642: e146 b.n 80118d2 8011644: 2308 movs r3, #8 8011646: f887 3043 strb.w r3, [r7, #67] @ 0x43 801164a: e142 b.n 80118d2 801164c: 2310 movs r3, #16 801164e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011652: e13e b.n 80118d2 8011654: cfff69f3 .word 0xcfff69f3 8011658: 58000c00 .word 0x58000c00 801165c: 11fff4ff .word 0x11fff4ff 8011660: 40011000 .word 0x40011000 8011664: 58024400 .word 0x58024400 8011668: 40004400 .word 0x40004400 801166c: 40004800 .word 0x40004800 8011670: 40004c00 .word 0x40004c00 8011674: 40005000 .word 0x40005000 8011678: 2320 movs r3, #32 801167a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801167e: e128 b.n 80118d2 8011680: 2340 movs r3, #64 @ 0x40 8011682: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011686: e124 b.n 80118d2 8011688: 2380 movs r3, #128 @ 0x80 801168a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801168e: e120 b.n 80118d2 8011690: 697b ldr r3, [r7, #20] 8011692: 681b ldr r3, [r3, #0] 8011694: 4acb ldr r2, [pc, #812] @ (80119c4 ) 8011696: 4293 cmp r3, r2 8011698: d176 bne.n 8011788 801169a: 4bcb ldr r3, [pc, #812] @ (80119c8 ) 801169c: 6d5b ldr r3, [r3, #84] @ 0x54 801169e: f003 0338 and.w r3, r3, #56 @ 0x38 80116a2: 2b28 cmp r3, #40 @ 0x28 80116a4: d86c bhi.n 8011780 80116a6: a201 add r2, pc, #4 @ (adr r2, 80116ac ) 80116a8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80116ac: 08011751 .word 0x08011751 80116b0: 08011781 .word 0x08011781 80116b4: 08011781 .word 0x08011781 80116b8: 08011781 .word 0x08011781 80116bc: 08011781 .word 0x08011781 80116c0: 08011781 .word 0x08011781 80116c4: 08011781 .word 0x08011781 80116c8: 08011781 .word 0x08011781 80116cc: 08011759 .word 0x08011759 80116d0: 08011781 .word 0x08011781 80116d4: 08011781 .word 0x08011781 80116d8: 08011781 .word 0x08011781 80116dc: 08011781 .word 0x08011781 80116e0: 08011781 .word 0x08011781 80116e4: 08011781 .word 0x08011781 80116e8: 08011781 .word 0x08011781 80116ec: 08011761 .word 0x08011761 80116f0: 08011781 .word 0x08011781 80116f4: 08011781 .word 0x08011781 80116f8: 08011781 .word 0x08011781 80116fc: 08011781 .word 0x08011781 8011700: 08011781 .word 0x08011781 8011704: 08011781 .word 0x08011781 8011708: 08011781 .word 0x08011781 801170c: 08011769 .word 0x08011769 8011710: 08011781 .word 0x08011781 8011714: 08011781 .word 0x08011781 8011718: 08011781 .word 0x08011781 801171c: 08011781 .word 0x08011781 8011720: 08011781 .word 0x08011781 8011724: 08011781 .word 0x08011781 8011728: 08011781 .word 0x08011781 801172c: 08011771 .word 0x08011771 8011730: 08011781 .word 0x08011781 8011734: 08011781 .word 0x08011781 8011738: 08011781 .word 0x08011781 801173c: 08011781 .word 0x08011781 8011740: 08011781 .word 0x08011781 8011744: 08011781 .word 0x08011781 8011748: 08011781 .word 0x08011781 801174c: 08011779 .word 0x08011779 8011750: 2301 movs r3, #1 8011752: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011756: e0bc b.n 80118d2 8011758: 2304 movs r3, #4 801175a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801175e: e0b8 b.n 80118d2 8011760: 2308 movs r3, #8 8011762: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011766: e0b4 b.n 80118d2 8011768: 2310 movs r3, #16 801176a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801176e: e0b0 b.n 80118d2 8011770: 2320 movs r3, #32 8011772: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011776: e0ac b.n 80118d2 8011778: 2340 movs r3, #64 @ 0x40 801177a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801177e: e0a8 b.n 80118d2 8011780: 2380 movs r3, #128 @ 0x80 8011782: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011786: e0a4 b.n 80118d2 8011788: 697b ldr r3, [r7, #20] 801178a: 681b ldr r3, [r3, #0] 801178c: 4a8f ldr r2, [pc, #572] @ (80119cc ) 801178e: 4293 cmp r3, r2 8011790: d130 bne.n 80117f4 8011792: 4b8d ldr r3, [pc, #564] @ (80119c8 ) 8011794: 6d5b ldr r3, [r3, #84] @ 0x54 8011796: f003 0307 and.w r3, r3, #7 801179a: 2b05 cmp r3, #5 801179c: d826 bhi.n 80117ec 801179e: a201 add r2, pc, #4 @ (adr r2, 80117a4 ) 80117a0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80117a4: 080117bd .word 0x080117bd 80117a8: 080117c5 .word 0x080117c5 80117ac: 080117cd .word 0x080117cd 80117b0: 080117d5 .word 0x080117d5 80117b4: 080117dd .word 0x080117dd 80117b8: 080117e5 .word 0x080117e5 80117bc: 2300 movs r3, #0 80117be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117c2: e086 b.n 80118d2 80117c4: 2304 movs r3, #4 80117c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117ca: e082 b.n 80118d2 80117cc: 2308 movs r3, #8 80117ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117d2: e07e b.n 80118d2 80117d4: 2310 movs r3, #16 80117d6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117da: e07a b.n 80118d2 80117dc: 2320 movs r3, #32 80117de: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117e2: e076 b.n 80118d2 80117e4: 2340 movs r3, #64 @ 0x40 80117e6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117ea: e072 b.n 80118d2 80117ec: 2380 movs r3, #128 @ 0x80 80117ee: f887 3043 strb.w r3, [r7, #67] @ 0x43 80117f2: e06e b.n 80118d2 80117f4: 697b ldr r3, [r7, #20] 80117f6: 681b ldr r3, [r3, #0] 80117f8: 4a75 ldr r2, [pc, #468] @ (80119d0 ) 80117fa: 4293 cmp r3, r2 80117fc: d130 bne.n 8011860 80117fe: 4b72 ldr r3, [pc, #456] @ (80119c8 ) 8011800: 6d5b ldr r3, [r3, #84] @ 0x54 8011802: f003 0307 and.w r3, r3, #7 8011806: 2b05 cmp r3, #5 8011808: d826 bhi.n 8011858 801180a: a201 add r2, pc, #4 @ (adr r2, 8011810 ) 801180c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011810: 08011829 .word 0x08011829 8011814: 08011831 .word 0x08011831 8011818: 08011839 .word 0x08011839 801181c: 08011841 .word 0x08011841 8011820: 08011849 .word 0x08011849 8011824: 08011851 .word 0x08011851 8011828: 2300 movs r3, #0 801182a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801182e: e050 b.n 80118d2 8011830: 2304 movs r3, #4 8011832: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011836: e04c b.n 80118d2 8011838: 2308 movs r3, #8 801183a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801183e: e048 b.n 80118d2 8011840: 2310 movs r3, #16 8011842: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011846: e044 b.n 80118d2 8011848: 2320 movs r3, #32 801184a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801184e: e040 b.n 80118d2 8011850: 2340 movs r3, #64 @ 0x40 8011852: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011856: e03c b.n 80118d2 8011858: 2380 movs r3, #128 @ 0x80 801185a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801185e: e038 b.n 80118d2 8011860: 697b ldr r3, [r7, #20] 8011862: 681b ldr r3, [r3, #0] 8011864: 4a5b ldr r2, [pc, #364] @ (80119d4 ) 8011866: 4293 cmp r3, r2 8011868: d130 bne.n 80118cc 801186a: 4b57 ldr r3, [pc, #348] @ (80119c8 ) 801186c: 6d9b ldr r3, [r3, #88] @ 0x58 801186e: f003 0307 and.w r3, r3, #7 8011872: 2b05 cmp r3, #5 8011874: d826 bhi.n 80118c4 8011876: a201 add r2, pc, #4 @ (adr r2, 801187c ) 8011878: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801187c: 08011895 .word 0x08011895 8011880: 0801189d .word 0x0801189d 8011884: 080118a5 .word 0x080118a5 8011888: 080118ad .word 0x080118ad 801188c: 080118b5 .word 0x080118b5 8011890: 080118bd .word 0x080118bd 8011894: 2302 movs r3, #2 8011896: f887 3043 strb.w r3, [r7, #67] @ 0x43 801189a: e01a b.n 80118d2 801189c: 2304 movs r3, #4 801189e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80118a2: e016 b.n 80118d2 80118a4: 2308 movs r3, #8 80118a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80118aa: e012 b.n 80118d2 80118ac: 2310 movs r3, #16 80118ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80118b2: e00e b.n 80118d2 80118b4: 2320 movs r3, #32 80118b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80118ba: e00a b.n 80118d2 80118bc: 2340 movs r3, #64 @ 0x40 80118be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80118c2: e006 b.n 80118d2 80118c4: 2380 movs r3, #128 @ 0x80 80118c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80118ca: e002 b.n 80118d2 80118cc: 2380 movs r3, #128 @ 0x80 80118ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 80118d2: 697b ldr r3, [r7, #20] 80118d4: 681b ldr r3, [r3, #0] 80118d6: 4a3f ldr r2, [pc, #252] @ (80119d4 ) 80118d8: 4293 cmp r3, r2 80118da: f040 80f8 bne.w 8011ace { /* Retrieve frequency clock */ switch (clocksource) 80118de: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80118e2: 2b20 cmp r3, #32 80118e4: dc46 bgt.n 8011974 80118e6: 2b02 cmp r3, #2 80118e8: f2c0 8082 blt.w 80119f0 80118ec: 3b02 subs r3, #2 80118ee: 2b1e cmp r3, #30 80118f0: d87e bhi.n 80119f0 80118f2: a201 add r2, pc, #4 @ (adr r2, 80118f8 ) 80118f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80118f8: 0801197b .word 0x0801197b 80118fc: 080119f1 .word 0x080119f1 8011900: 08011983 .word 0x08011983 8011904: 080119f1 .word 0x080119f1 8011908: 080119f1 .word 0x080119f1 801190c: 080119f1 .word 0x080119f1 8011910: 08011993 .word 0x08011993 8011914: 080119f1 .word 0x080119f1 8011918: 080119f1 .word 0x080119f1 801191c: 080119f1 .word 0x080119f1 8011920: 080119f1 .word 0x080119f1 8011924: 080119f1 .word 0x080119f1 8011928: 080119f1 .word 0x080119f1 801192c: 080119f1 .word 0x080119f1 8011930: 080119a3 .word 0x080119a3 8011934: 080119f1 .word 0x080119f1 8011938: 080119f1 .word 0x080119f1 801193c: 080119f1 .word 0x080119f1 8011940: 080119f1 .word 0x080119f1 8011944: 080119f1 .word 0x080119f1 8011948: 080119f1 .word 0x080119f1 801194c: 080119f1 .word 0x080119f1 8011950: 080119f1 .word 0x080119f1 8011954: 080119f1 .word 0x080119f1 8011958: 080119f1 .word 0x080119f1 801195c: 080119f1 .word 0x080119f1 8011960: 080119f1 .word 0x080119f1 8011964: 080119f1 .word 0x080119f1 8011968: 080119f1 .word 0x080119f1 801196c: 080119f1 .word 0x080119f1 8011970: 080119e3 .word 0x080119e3 8011974: 2b40 cmp r3, #64 @ 0x40 8011976: d037 beq.n 80119e8 8011978: e03a b.n 80119f0 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 801197a: f7fc f9fd bl 800dd78 801197e: 63f8 str r0, [r7, #60] @ 0x3c break; 8011980: e03c b.n 80119fc case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8011982: f107 0324 add.w r3, r7, #36 @ 0x24 8011986: 4618 mov r0, r3 8011988: f7fc fa0c bl 800dda4 pclk = pll2_clocks.PLL2_Q_Frequency; 801198c: 6abb ldr r3, [r7, #40] @ 0x28 801198e: 63fb str r3, [r7, #60] @ 0x3c break; 8011990: e034 b.n 80119fc case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8011992: f107 0318 add.w r3, r7, #24 8011996: 4618 mov r0, r3 8011998: f7fc fb58 bl 800e04c pclk = pll3_clocks.PLL3_Q_Frequency; 801199c: 69fb ldr r3, [r7, #28] 801199e: 63fb str r3, [r7, #60] @ 0x3c break; 80119a0: e02c b.n 80119fc case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 80119a2: 4b09 ldr r3, [pc, #36] @ (80119c8 ) 80119a4: 681b ldr r3, [r3, #0] 80119a6: f003 0320 and.w r3, r3, #32 80119aa: 2b00 cmp r3, #0 80119ac: d016 beq.n 80119dc { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 80119ae: 4b06 ldr r3, [pc, #24] @ (80119c8 ) 80119b0: 681b ldr r3, [r3, #0] 80119b2: 08db lsrs r3, r3, #3 80119b4: f003 0303 and.w r3, r3, #3 80119b8: 4a07 ldr r2, [pc, #28] @ (80119d8 ) 80119ba: fa22 f303 lsr.w r3, r2, r3 80119be: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80119c0: e01c b.n 80119fc 80119c2: bf00 nop 80119c4: 40011400 .word 0x40011400 80119c8: 58024400 .word 0x58024400 80119cc: 40007800 .word 0x40007800 80119d0: 40007c00 .word 0x40007c00 80119d4: 58000c00 .word 0x58000c00 80119d8: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 80119dc: 4b9d ldr r3, [pc, #628] @ (8011c54 ) 80119de: 63fb str r3, [r7, #60] @ 0x3c break; 80119e0: e00c b.n 80119fc case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80119e2: 4b9d ldr r3, [pc, #628] @ (8011c58 ) 80119e4: 63fb str r3, [r7, #60] @ 0x3c break; 80119e6: e009 b.n 80119fc case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80119e8: f44f 4300 mov.w r3, #32768 @ 0x8000 80119ec: 63fb str r3, [r7, #60] @ 0x3c break; 80119ee: e005 b.n 80119fc default: pclk = 0U; 80119f0: 2300 movs r3, #0 80119f2: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80119f4: 2301 movs r3, #1 80119f6: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80119fa: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 80119fc: 6bfb ldr r3, [r7, #60] @ 0x3c 80119fe: 2b00 cmp r3, #0 8011a00: f000 81de beq.w 8011dc0 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 8011a04: 697b ldr r3, [r7, #20] 8011a06: 6a5b ldr r3, [r3, #36] @ 0x24 8011a08: 4a94 ldr r2, [pc, #592] @ (8011c5c ) 8011a0a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011a0e: 461a mov r2, r3 8011a10: 6bfb ldr r3, [r7, #60] @ 0x3c 8011a12: fbb3 f3f2 udiv r3, r3, r2 8011a16: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8011a18: 697b ldr r3, [r7, #20] 8011a1a: 685a ldr r2, [r3, #4] 8011a1c: 4613 mov r3, r2 8011a1e: 005b lsls r3, r3, #1 8011a20: 4413 add r3, r2 8011a22: 6b3a ldr r2, [r7, #48] @ 0x30 8011a24: 429a cmp r2, r3 8011a26: d305 bcc.n 8011a34 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8011a28: 697b ldr r3, [r7, #20] 8011a2a: 685b ldr r3, [r3, #4] 8011a2c: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8011a2e: 6b3a ldr r2, [r7, #48] @ 0x30 8011a30: 429a cmp r2, r3 8011a32: d903 bls.n 8011a3c { ret = HAL_ERROR; 8011a34: 2301 movs r3, #1 8011a36: f887 3042 strb.w r3, [r7, #66] @ 0x42 8011a3a: e1c1 b.n 8011dc0 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8011a3c: 6bfb ldr r3, [r7, #60] @ 0x3c 8011a3e: 2200 movs r2, #0 8011a40: 60bb str r3, [r7, #8] 8011a42: 60fa str r2, [r7, #12] 8011a44: 697b ldr r3, [r7, #20] 8011a46: 6a5b ldr r3, [r3, #36] @ 0x24 8011a48: 4a84 ldr r2, [pc, #528] @ (8011c5c ) 8011a4a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011a4e: b29b uxth r3, r3 8011a50: 2200 movs r2, #0 8011a52: 603b str r3, [r7, #0] 8011a54: 607a str r2, [r7, #4] 8011a56: e9d7 2300 ldrd r2, r3, [r7] 8011a5a: e9d7 0102 ldrd r0, r1, [r7, #8] 8011a5e: f7ee fc8f bl 8000380 <__aeabi_uldivmod> 8011a62: 4602 mov r2, r0 8011a64: 460b mov r3, r1 8011a66: 4610 mov r0, r2 8011a68: 4619 mov r1, r3 8011a6a: f04f 0200 mov.w r2, #0 8011a6e: f04f 0300 mov.w r3, #0 8011a72: 020b lsls r3, r1, #8 8011a74: ea43 6310 orr.w r3, r3, r0, lsr #24 8011a78: 0202 lsls r2, r0, #8 8011a7a: 6979 ldr r1, [r7, #20] 8011a7c: 6849 ldr r1, [r1, #4] 8011a7e: 0849 lsrs r1, r1, #1 8011a80: 2000 movs r0, #0 8011a82: 460c mov r4, r1 8011a84: 4605 mov r5, r0 8011a86: eb12 0804 adds.w r8, r2, r4 8011a8a: eb43 0905 adc.w r9, r3, r5 8011a8e: 697b ldr r3, [r7, #20] 8011a90: 685b ldr r3, [r3, #4] 8011a92: 2200 movs r2, #0 8011a94: 469a mov sl, r3 8011a96: 4693 mov fp, r2 8011a98: 4652 mov r2, sl 8011a9a: 465b mov r3, fp 8011a9c: 4640 mov r0, r8 8011a9e: 4649 mov r1, r9 8011aa0: f7ee fc6e bl 8000380 <__aeabi_uldivmod> 8011aa4: 4602 mov r2, r0 8011aa6: 460b mov r3, r1 8011aa8: 4613 mov r3, r2 8011aaa: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8011aac: 6bbb ldr r3, [r7, #56] @ 0x38 8011aae: f5b3 7f40 cmp.w r3, #768 @ 0x300 8011ab2: d308 bcc.n 8011ac6 8011ab4: 6bbb ldr r3, [r7, #56] @ 0x38 8011ab6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8011aba: d204 bcs.n 8011ac6 { huart->Instance->BRR = usartdiv; 8011abc: 697b ldr r3, [r7, #20] 8011abe: 681b ldr r3, [r3, #0] 8011ac0: 6bba ldr r2, [r7, #56] @ 0x38 8011ac2: 60da str r2, [r3, #12] 8011ac4: e17c b.n 8011dc0 } else { ret = HAL_ERROR; 8011ac6: 2301 movs r3, #1 8011ac8: f887 3042 strb.w r3, [r7, #66] @ 0x42 8011acc: e178 b.n 8011dc0 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8011ace: 697b ldr r3, [r7, #20] 8011ad0: 69db ldr r3, [r3, #28] 8011ad2: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8011ad6: f040 80c5 bne.w 8011c64 { switch (clocksource) 8011ada: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8011ade: 2b20 cmp r3, #32 8011ae0: dc48 bgt.n 8011b74 8011ae2: 2b00 cmp r3, #0 8011ae4: db7b blt.n 8011bde 8011ae6: 2b20 cmp r3, #32 8011ae8: d879 bhi.n 8011bde 8011aea: a201 add r2, pc, #4 @ (adr r2, 8011af0 ) 8011aec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011af0: 08011b7b .word 0x08011b7b 8011af4: 08011b83 .word 0x08011b83 8011af8: 08011bdf .word 0x08011bdf 8011afc: 08011bdf .word 0x08011bdf 8011b00: 08011b8b .word 0x08011b8b 8011b04: 08011bdf .word 0x08011bdf 8011b08: 08011bdf .word 0x08011bdf 8011b0c: 08011bdf .word 0x08011bdf 8011b10: 08011b9b .word 0x08011b9b 8011b14: 08011bdf .word 0x08011bdf 8011b18: 08011bdf .word 0x08011bdf 8011b1c: 08011bdf .word 0x08011bdf 8011b20: 08011bdf .word 0x08011bdf 8011b24: 08011bdf .word 0x08011bdf 8011b28: 08011bdf .word 0x08011bdf 8011b2c: 08011bdf .word 0x08011bdf 8011b30: 08011bab .word 0x08011bab 8011b34: 08011bdf .word 0x08011bdf 8011b38: 08011bdf .word 0x08011bdf 8011b3c: 08011bdf .word 0x08011bdf 8011b40: 08011bdf .word 0x08011bdf 8011b44: 08011bdf .word 0x08011bdf 8011b48: 08011bdf .word 0x08011bdf 8011b4c: 08011bdf .word 0x08011bdf 8011b50: 08011bdf .word 0x08011bdf 8011b54: 08011bdf .word 0x08011bdf 8011b58: 08011bdf .word 0x08011bdf 8011b5c: 08011bdf .word 0x08011bdf 8011b60: 08011bdf .word 0x08011bdf 8011b64: 08011bdf .word 0x08011bdf 8011b68: 08011bdf .word 0x08011bdf 8011b6c: 08011bdf .word 0x08011bdf 8011b70: 08011bd1 .word 0x08011bd1 8011b74: 2b40 cmp r3, #64 @ 0x40 8011b76: d02e beq.n 8011bd6 8011b78: e031 b.n 8011bde { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8011b7a: f7fa f921 bl 800bdc0 8011b7e: 63f8 str r0, [r7, #60] @ 0x3c break; 8011b80: e033 b.n 8011bea case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8011b82: f7fa f933 bl 800bdec 8011b86: 63f8 str r0, [r7, #60] @ 0x3c break; 8011b88: e02f b.n 8011bea case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8011b8a: f107 0324 add.w r3, r7, #36 @ 0x24 8011b8e: 4618 mov r0, r3 8011b90: f7fc f908 bl 800dda4 pclk = pll2_clocks.PLL2_Q_Frequency; 8011b94: 6abb ldr r3, [r7, #40] @ 0x28 8011b96: 63fb str r3, [r7, #60] @ 0x3c break; 8011b98: e027 b.n 8011bea case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8011b9a: f107 0318 add.w r3, r7, #24 8011b9e: 4618 mov r0, r3 8011ba0: f7fc fa54 bl 800e04c pclk = pll3_clocks.PLL3_Q_Frequency; 8011ba4: 69fb ldr r3, [r7, #28] 8011ba6: 63fb str r3, [r7, #60] @ 0x3c break; 8011ba8: e01f b.n 8011bea case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8011baa: 4b2d ldr r3, [pc, #180] @ (8011c60 ) 8011bac: 681b ldr r3, [r3, #0] 8011bae: f003 0320 and.w r3, r3, #32 8011bb2: 2b00 cmp r3, #0 8011bb4: d009 beq.n 8011bca { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8011bb6: 4b2a ldr r3, [pc, #168] @ (8011c60 ) 8011bb8: 681b ldr r3, [r3, #0] 8011bba: 08db lsrs r3, r3, #3 8011bbc: f003 0303 and.w r3, r3, #3 8011bc0: 4a24 ldr r2, [pc, #144] @ (8011c54 ) 8011bc2: fa22 f303 lsr.w r3, r2, r3 8011bc6: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8011bc8: e00f b.n 8011bea pclk = (uint32_t) HSI_VALUE; 8011bca: 4b22 ldr r3, [pc, #136] @ (8011c54 ) 8011bcc: 63fb str r3, [r7, #60] @ 0x3c break; 8011bce: e00c b.n 8011bea case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8011bd0: 4b21 ldr r3, [pc, #132] @ (8011c58 ) 8011bd2: 63fb str r3, [r7, #60] @ 0x3c break; 8011bd4: e009 b.n 8011bea case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8011bd6: f44f 4300 mov.w r3, #32768 @ 0x8000 8011bda: 63fb str r3, [r7, #60] @ 0x3c break; 8011bdc: e005 b.n 8011bea default: pclk = 0U; 8011bde: 2300 movs r3, #0 8011be0: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8011be2: 2301 movs r3, #1 8011be4: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8011be8: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8011bea: 6bfb ldr r3, [r7, #60] @ 0x3c 8011bec: 2b00 cmp r3, #0 8011bee: f000 80e7 beq.w 8011dc0 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8011bf2: 697b ldr r3, [r7, #20] 8011bf4: 6a5b ldr r3, [r3, #36] @ 0x24 8011bf6: 4a19 ldr r2, [pc, #100] @ (8011c5c ) 8011bf8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011bfc: 461a mov r2, r3 8011bfe: 6bfb ldr r3, [r7, #60] @ 0x3c 8011c00: fbb3 f3f2 udiv r3, r3, r2 8011c04: 005a lsls r2, r3, #1 8011c06: 697b ldr r3, [r7, #20] 8011c08: 685b ldr r3, [r3, #4] 8011c0a: 085b lsrs r3, r3, #1 8011c0c: 441a add r2, r3 8011c0e: 697b ldr r3, [r7, #20] 8011c10: 685b ldr r3, [r3, #4] 8011c12: fbb2 f3f3 udiv r3, r2, r3 8011c16: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8011c18: 6bbb ldr r3, [r7, #56] @ 0x38 8011c1a: 2b0f cmp r3, #15 8011c1c: d916 bls.n 8011c4c 8011c1e: 6bbb ldr r3, [r7, #56] @ 0x38 8011c20: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011c24: d212 bcs.n 8011c4c { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8011c26: 6bbb ldr r3, [r7, #56] @ 0x38 8011c28: b29b uxth r3, r3 8011c2a: f023 030f bic.w r3, r3, #15 8011c2e: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8011c30: 6bbb ldr r3, [r7, #56] @ 0x38 8011c32: 085b lsrs r3, r3, #1 8011c34: b29b uxth r3, r3 8011c36: f003 0307 and.w r3, r3, #7 8011c3a: b29a uxth r2, r3 8011c3c: 8efb ldrh r3, [r7, #54] @ 0x36 8011c3e: 4313 orrs r3, r2 8011c40: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 8011c42: 697b ldr r3, [r7, #20] 8011c44: 681b ldr r3, [r3, #0] 8011c46: 8efa ldrh r2, [r7, #54] @ 0x36 8011c48: 60da str r2, [r3, #12] 8011c4a: e0b9 b.n 8011dc0 } else { ret = HAL_ERROR; 8011c4c: 2301 movs r3, #1 8011c4e: f887 3042 strb.w r3, [r7, #66] @ 0x42 8011c52: e0b5 b.n 8011dc0 8011c54: 03d09000 .word 0x03d09000 8011c58: 003d0900 .word 0x003d0900 8011c5c: 080189e0 .word 0x080189e0 8011c60: 58024400 .word 0x58024400 } } } else { switch (clocksource) 8011c64: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8011c68: 2b20 cmp r3, #32 8011c6a: dc49 bgt.n 8011d00 8011c6c: 2b00 cmp r3, #0 8011c6e: db7c blt.n 8011d6a 8011c70: 2b20 cmp r3, #32 8011c72: d87a bhi.n 8011d6a 8011c74: a201 add r2, pc, #4 @ (adr r2, 8011c7c ) 8011c76: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011c7a: bf00 nop 8011c7c: 08011d07 .word 0x08011d07 8011c80: 08011d0f .word 0x08011d0f 8011c84: 08011d6b .word 0x08011d6b 8011c88: 08011d6b .word 0x08011d6b 8011c8c: 08011d17 .word 0x08011d17 8011c90: 08011d6b .word 0x08011d6b 8011c94: 08011d6b .word 0x08011d6b 8011c98: 08011d6b .word 0x08011d6b 8011c9c: 08011d27 .word 0x08011d27 8011ca0: 08011d6b .word 0x08011d6b 8011ca4: 08011d6b .word 0x08011d6b 8011ca8: 08011d6b .word 0x08011d6b 8011cac: 08011d6b .word 0x08011d6b 8011cb0: 08011d6b .word 0x08011d6b 8011cb4: 08011d6b .word 0x08011d6b 8011cb8: 08011d6b .word 0x08011d6b 8011cbc: 08011d37 .word 0x08011d37 8011cc0: 08011d6b .word 0x08011d6b 8011cc4: 08011d6b .word 0x08011d6b 8011cc8: 08011d6b .word 0x08011d6b 8011ccc: 08011d6b .word 0x08011d6b 8011cd0: 08011d6b .word 0x08011d6b 8011cd4: 08011d6b .word 0x08011d6b 8011cd8: 08011d6b .word 0x08011d6b 8011cdc: 08011d6b .word 0x08011d6b 8011ce0: 08011d6b .word 0x08011d6b 8011ce4: 08011d6b .word 0x08011d6b 8011ce8: 08011d6b .word 0x08011d6b 8011cec: 08011d6b .word 0x08011d6b 8011cf0: 08011d6b .word 0x08011d6b 8011cf4: 08011d6b .word 0x08011d6b 8011cf8: 08011d6b .word 0x08011d6b 8011cfc: 08011d5d .word 0x08011d5d 8011d00: 2b40 cmp r3, #64 @ 0x40 8011d02: d02e beq.n 8011d62 8011d04: e031 b.n 8011d6a { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8011d06: f7fa f85b bl 800bdc0 8011d0a: 63f8 str r0, [r7, #60] @ 0x3c break; 8011d0c: e033 b.n 8011d76 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8011d0e: f7fa f86d bl 800bdec 8011d12: 63f8 str r0, [r7, #60] @ 0x3c break; 8011d14: e02f b.n 8011d76 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8011d16: f107 0324 add.w r3, r7, #36 @ 0x24 8011d1a: 4618 mov r0, r3 8011d1c: f7fc f842 bl 800dda4 pclk = pll2_clocks.PLL2_Q_Frequency; 8011d20: 6abb ldr r3, [r7, #40] @ 0x28 8011d22: 63fb str r3, [r7, #60] @ 0x3c break; 8011d24: e027 b.n 8011d76 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8011d26: f107 0318 add.w r3, r7, #24 8011d2a: 4618 mov r0, r3 8011d2c: f7fc f98e bl 800e04c pclk = pll3_clocks.PLL3_Q_Frequency; 8011d30: 69fb ldr r3, [r7, #28] 8011d32: 63fb str r3, [r7, #60] @ 0x3c break; 8011d34: e01f b.n 8011d76 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8011d36: 4b2d ldr r3, [pc, #180] @ (8011dec ) 8011d38: 681b ldr r3, [r3, #0] 8011d3a: f003 0320 and.w r3, r3, #32 8011d3e: 2b00 cmp r3, #0 8011d40: d009 beq.n 8011d56 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8011d42: 4b2a ldr r3, [pc, #168] @ (8011dec ) 8011d44: 681b ldr r3, [r3, #0] 8011d46: 08db lsrs r3, r3, #3 8011d48: f003 0303 and.w r3, r3, #3 8011d4c: 4a28 ldr r2, [pc, #160] @ (8011df0 ) 8011d4e: fa22 f303 lsr.w r3, r2, r3 8011d52: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8011d54: e00f b.n 8011d76 pclk = (uint32_t) HSI_VALUE; 8011d56: 4b26 ldr r3, [pc, #152] @ (8011df0 ) 8011d58: 63fb str r3, [r7, #60] @ 0x3c break; 8011d5a: e00c b.n 8011d76 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8011d5c: 4b25 ldr r3, [pc, #148] @ (8011df4 ) 8011d5e: 63fb str r3, [r7, #60] @ 0x3c break; 8011d60: e009 b.n 8011d76 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8011d62: f44f 4300 mov.w r3, #32768 @ 0x8000 8011d66: 63fb str r3, [r7, #60] @ 0x3c break; 8011d68: e005 b.n 8011d76 default: pclk = 0U; 8011d6a: 2300 movs r3, #0 8011d6c: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8011d6e: 2301 movs r3, #1 8011d70: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8011d74: bf00 nop } if (pclk != 0U) 8011d76: 6bfb ldr r3, [r7, #60] @ 0x3c 8011d78: 2b00 cmp r3, #0 8011d7a: d021 beq.n 8011dc0 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8011d7c: 697b ldr r3, [r7, #20] 8011d7e: 6a5b ldr r3, [r3, #36] @ 0x24 8011d80: 4a1d ldr r2, [pc, #116] @ (8011df8 ) 8011d82: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8011d86: 461a mov r2, r3 8011d88: 6bfb ldr r3, [r7, #60] @ 0x3c 8011d8a: fbb3 f2f2 udiv r2, r3, r2 8011d8e: 697b ldr r3, [r7, #20] 8011d90: 685b ldr r3, [r3, #4] 8011d92: 085b lsrs r3, r3, #1 8011d94: 441a add r2, r3 8011d96: 697b ldr r3, [r7, #20] 8011d98: 685b ldr r3, [r3, #4] 8011d9a: fbb2 f3f3 udiv r3, r2, r3 8011d9e: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8011da0: 6bbb ldr r3, [r7, #56] @ 0x38 8011da2: 2b0f cmp r3, #15 8011da4: d909 bls.n 8011dba 8011da6: 6bbb ldr r3, [r7, #56] @ 0x38 8011da8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8011dac: d205 bcs.n 8011dba { huart->Instance->BRR = (uint16_t)usartdiv; 8011dae: 6bbb ldr r3, [r7, #56] @ 0x38 8011db0: b29a uxth r2, r3 8011db2: 697b ldr r3, [r7, #20] 8011db4: 681b ldr r3, [r3, #0] 8011db6: 60da str r2, [r3, #12] 8011db8: e002 b.n 8011dc0 } else { ret = HAL_ERROR; 8011dba: 2301 movs r3, #1 8011dbc: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8011dc0: 697b ldr r3, [r7, #20] 8011dc2: 2201 movs r2, #1 8011dc4: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 8011dc8: 697b ldr r3, [r7, #20] 8011dca: 2201 movs r2, #1 8011dcc: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 8011dd0: 697b ldr r3, [r7, #20] 8011dd2: 2200 movs r2, #0 8011dd4: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8011dd6: 697b ldr r3, [r7, #20] 8011dd8: 2200 movs r2, #0 8011dda: 679a str r2, [r3, #120] @ 0x78 return ret; 8011ddc: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 8011de0: 4618 mov r0, r3 8011de2: 3748 adds r7, #72 @ 0x48 8011de4: 46bd mov sp, r7 8011de6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8011dea: bf00 nop 8011dec: 58024400 .word 0x58024400 8011df0: 03d09000 .word 0x03d09000 8011df4: 003d0900 .word 0x003d0900 8011df8: 080189e0 .word 0x080189e0 08011dfc : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8011dfc: b480 push {r7} 8011dfe: b083 sub sp, #12 8011e00: af00 add r7, sp, #0 8011e02: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8011e04: 687b ldr r3, [r7, #4] 8011e06: 6a9b ldr r3, [r3, #40] @ 0x28 8011e08: f003 0308 and.w r3, r3, #8 8011e0c: 2b00 cmp r3, #0 8011e0e: d00a beq.n 8011e26 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8011e10: 687b ldr r3, [r7, #4] 8011e12: 681b ldr r3, [r3, #0] 8011e14: 685b ldr r3, [r3, #4] 8011e16: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8011e1a: 687b ldr r3, [r7, #4] 8011e1c: 6b9a ldr r2, [r3, #56] @ 0x38 8011e1e: 687b ldr r3, [r7, #4] 8011e20: 681b ldr r3, [r3, #0] 8011e22: 430a orrs r2, r1 8011e24: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8011e26: 687b ldr r3, [r7, #4] 8011e28: 6a9b ldr r3, [r3, #40] @ 0x28 8011e2a: f003 0301 and.w r3, r3, #1 8011e2e: 2b00 cmp r3, #0 8011e30: d00a beq.n 8011e48 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8011e32: 687b ldr r3, [r7, #4] 8011e34: 681b ldr r3, [r3, #0] 8011e36: 685b ldr r3, [r3, #4] 8011e38: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8011e3c: 687b ldr r3, [r7, #4] 8011e3e: 6ada ldr r2, [r3, #44] @ 0x2c 8011e40: 687b ldr r3, [r7, #4] 8011e42: 681b ldr r3, [r3, #0] 8011e44: 430a orrs r2, r1 8011e46: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8011e48: 687b ldr r3, [r7, #4] 8011e4a: 6a9b ldr r3, [r3, #40] @ 0x28 8011e4c: f003 0302 and.w r3, r3, #2 8011e50: 2b00 cmp r3, #0 8011e52: d00a beq.n 8011e6a { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8011e54: 687b ldr r3, [r7, #4] 8011e56: 681b ldr r3, [r3, #0] 8011e58: 685b ldr r3, [r3, #4] 8011e5a: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8011e5e: 687b ldr r3, [r7, #4] 8011e60: 6b1a ldr r2, [r3, #48] @ 0x30 8011e62: 687b ldr r3, [r7, #4] 8011e64: 681b ldr r3, [r3, #0] 8011e66: 430a orrs r2, r1 8011e68: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8011e6a: 687b ldr r3, [r7, #4] 8011e6c: 6a9b ldr r3, [r3, #40] @ 0x28 8011e6e: f003 0304 and.w r3, r3, #4 8011e72: 2b00 cmp r3, #0 8011e74: d00a beq.n 8011e8c { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8011e76: 687b ldr r3, [r7, #4] 8011e78: 681b ldr r3, [r3, #0] 8011e7a: 685b ldr r3, [r3, #4] 8011e7c: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8011e80: 687b ldr r3, [r7, #4] 8011e82: 6b5a ldr r2, [r3, #52] @ 0x34 8011e84: 687b ldr r3, [r7, #4] 8011e86: 681b ldr r3, [r3, #0] 8011e88: 430a orrs r2, r1 8011e8a: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8011e8c: 687b ldr r3, [r7, #4] 8011e8e: 6a9b ldr r3, [r3, #40] @ 0x28 8011e90: f003 0310 and.w r3, r3, #16 8011e94: 2b00 cmp r3, #0 8011e96: d00a beq.n 8011eae { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8011e98: 687b ldr r3, [r7, #4] 8011e9a: 681b ldr r3, [r3, #0] 8011e9c: 689b ldr r3, [r3, #8] 8011e9e: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8011ea2: 687b ldr r3, [r7, #4] 8011ea4: 6bda ldr r2, [r3, #60] @ 0x3c 8011ea6: 687b ldr r3, [r7, #4] 8011ea8: 681b ldr r3, [r3, #0] 8011eaa: 430a orrs r2, r1 8011eac: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8011eae: 687b ldr r3, [r7, #4] 8011eb0: 6a9b ldr r3, [r3, #40] @ 0x28 8011eb2: f003 0320 and.w r3, r3, #32 8011eb6: 2b00 cmp r3, #0 8011eb8: d00a beq.n 8011ed0 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 8011eba: 687b ldr r3, [r7, #4] 8011ebc: 681b ldr r3, [r3, #0] 8011ebe: 689b ldr r3, [r3, #8] 8011ec0: f423 5100 bic.w r1, r3, #8192 @ 0x2000 8011ec4: 687b ldr r3, [r7, #4] 8011ec6: 6c1a ldr r2, [r3, #64] @ 0x40 8011ec8: 687b ldr r3, [r7, #4] 8011eca: 681b ldr r3, [r3, #0] 8011ecc: 430a orrs r2, r1 8011ece: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 8011ed0: 687b ldr r3, [r7, #4] 8011ed2: 6a9b ldr r3, [r3, #40] @ 0x28 8011ed4: f003 0340 and.w r3, r3, #64 @ 0x40 8011ed8: 2b00 cmp r3, #0 8011eda: d01a beq.n 8011f12 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 8011edc: 687b ldr r3, [r7, #4] 8011ede: 681b ldr r3, [r3, #0] 8011ee0: 685b ldr r3, [r3, #4] 8011ee2: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 8011ee6: 687b ldr r3, [r7, #4] 8011ee8: 6c5a ldr r2, [r3, #68] @ 0x44 8011eea: 687b ldr r3, [r7, #4] 8011eec: 681b ldr r3, [r3, #0] 8011eee: 430a orrs r2, r1 8011ef0: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8011ef2: 687b ldr r3, [r7, #4] 8011ef4: 6c5b ldr r3, [r3, #68] @ 0x44 8011ef6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8011efa: d10a bne.n 8011f12 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8011efc: 687b ldr r3, [r7, #4] 8011efe: 681b ldr r3, [r3, #0] 8011f00: 685b ldr r3, [r3, #4] 8011f02: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 8011f06: 687b ldr r3, [r7, #4] 8011f08: 6c9a ldr r2, [r3, #72] @ 0x48 8011f0a: 687b ldr r3, [r7, #4] 8011f0c: 681b ldr r3, [r3, #0] 8011f0e: 430a orrs r2, r1 8011f10: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 8011f12: 687b ldr r3, [r7, #4] 8011f14: 6a9b ldr r3, [r3, #40] @ 0x28 8011f16: f003 0380 and.w r3, r3, #128 @ 0x80 8011f1a: 2b00 cmp r3, #0 8011f1c: d00a beq.n 8011f34 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8011f1e: 687b ldr r3, [r7, #4] 8011f20: 681b ldr r3, [r3, #0] 8011f22: 685b ldr r3, [r3, #4] 8011f24: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8011f28: 687b ldr r3, [r7, #4] 8011f2a: 6cda ldr r2, [r3, #76] @ 0x4c 8011f2c: 687b ldr r3, [r7, #4] 8011f2e: 681b ldr r3, [r3, #0] 8011f30: 430a orrs r2, r1 8011f32: 605a str r2, [r3, #4] } } 8011f34: bf00 nop 8011f36: 370c adds r7, #12 8011f38: 46bd mov sp, r7 8011f3a: f85d 7b04 ldr.w r7, [sp], #4 8011f3e: 4770 bx lr 08011f40 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8011f40: b580 push {r7, lr} 8011f42: b098 sub sp, #96 @ 0x60 8011f44: af02 add r7, sp, #8 8011f46: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8011f48: 687b ldr r3, [r7, #4] 8011f4a: 2200 movs r2, #0 8011f4c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8011f50: f7f3 fa44 bl 80053dc 8011f54: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8011f56: 687b ldr r3, [r7, #4] 8011f58: 681b ldr r3, [r3, #0] 8011f5a: 681b ldr r3, [r3, #0] 8011f5c: f003 0308 and.w r3, r3, #8 8011f60: 2b08 cmp r3, #8 8011f62: d12f bne.n 8011fc4 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8011f64: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8011f68: 9300 str r3, [sp, #0] 8011f6a: 6d7b ldr r3, [r7, #84] @ 0x54 8011f6c: 2200 movs r2, #0 8011f6e: f44f 1100 mov.w r1, #2097152 @ 0x200000 8011f72: 6878 ldr r0, [r7, #4] 8011f74: f000 f88e bl 8012094 8011f78: 4603 mov r3, r0 8011f7a: 2b00 cmp r3, #0 8011f7c: d022 beq.n 8011fc4 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8011f7e: 687b ldr r3, [r7, #4] 8011f80: 681b ldr r3, [r3, #0] 8011f82: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011f84: 6bbb ldr r3, [r7, #56] @ 0x38 8011f86: e853 3f00 ldrex r3, [r3] 8011f8a: 637b str r3, [r7, #52] @ 0x34 return(result); 8011f8c: 6b7b ldr r3, [r7, #52] @ 0x34 8011f8e: f023 0380 bic.w r3, r3, #128 @ 0x80 8011f92: 653b str r3, [r7, #80] @ 0x50 8011f94: 687b ldr r3, [r7, #4] 8011f96: 681b ldr r3, [r3, #0] 8011f98: 461a mov r2, r3 8011f9a: 6d3b ldr r3, [r7, #80] @ 0x50 8011f9c: 647b str r3, [r7, #68] @ 0x44 8011f9e: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011fa0: 6c39 ldr r1, [r7, #64] @ 0x40 8011fa2: 6c7a ldr r2, [r7, #68] @ 0x44 8011fa4: e841 2300 strex r3, r2, [r1] 8011fa8: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011faa: 6bfb ldr r3, [r7, #60] @ 0x3c 8011fac: 2b00 cmp r3, #0 8011fae: d1e6 bne.n 8011f7e huart->gState = HAL_UART_STATE_READY; 8011fb0: 687b ldr r3, [r7, #4] 8011fb2: 2220 movs r2, #32 8011fb4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8011fb8: 687b ldr r3, [r7, #4] 8011fba: 2200 movs r2, #0 8011fbc: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8011fc0: 2303 movs r3, #3 8011fc2: e063 b.n 801208c } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 8011fc4: 687b ldr r3, [r7, #4] 8011fc6: 681b ldr r3, [r3, #0] 8011fc8: 681b ldr r3, [r3, #0] 8011fca: f003 0304 and.w r3, r3, #4 8011fce: 2b04 cmp r3, #4 8011fd0: d149 bne.n 8012066 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8011fd2: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8011fd6: 9300 str r3, [sp, #0] 8011fd8: 6d7b ldr r3, [r7, #84] @ 0x54 8011fda: 2200 movs r2, #0 8011fdc: f44f 0180 mov.w r1, #4194304 @ 0x400000 8011fe0: 6878 ldr r0, [r7, #4] 8011fe2: f000 f857 bl 8012094 8011fe6: 4603 mov r3, r0 8011fe8: 2b00 cmp r3, #0 8011fea: d03c beq.n 8012066 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011fec: 687b ldr r3, [r7, #4] 8011fee: 681b ldr r3, [r3, #0] 8011ff0: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011ff2: 6a7b ldr r3, [r7, #36] @ 0x24 8011ff4: e853 3f00 ldrex r3, [r3] 8011ff8: 623b str r3, [r7, #32] return(result); 8011ffa: 6a3b ldr r3, [r7, #32] 8011ffc: f423 7390 bic.w r3, r3, #288 @ 0x120 8012000: 64fb str r3, [r7, #76] @ 0x4c 8012002: 687b ldr r3, [r7, #4] 8012004: 681b ldr r3, [r3, #0] 8012006: 461a mov r2, r3 8012008: 6cfb ldr r3, [r7, #76] @ 0x4c 801200a: 633b str r3, [r7, #48] @ 0x30 801200c: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801200e: 6af9 ldr r1, [r7, #44] @ 0x2c 8012010: 6b3a ldr r2, [r7, #48] @ 0x30 8012012: e841 2300 strex r3, r2, [r1] 8012016: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012018: 6abb ldr r3, [r7, #40] @ 0x28 801201a: 2b00 cmp r3, #0 801201c: d1e6 bne.n 8011fec ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801201e: 687b ldr r3, [r7, #4] 8012020: 681b ldr r3, [r3, #0] 8012022: 3308 adds r3, #8 8012024: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012026: 693b ldr r3, [r7, #16] 8012028: e853 3f00 ldrex r3, [r3] 801202c: 60fb str r3, [r7, #12] return(result); 801202e: 68fb ldr r3, [r7, #12] 8012030: f023 0301 bic.w r3, r3, #1 8012034: 64bb str r3, [r7, #72] @ 0x48 8012036: 687b ldr r3, [r7, #4] 8012038: 681b ldr r3, [r3, #0] 801203a: 3308 adds r3, #8 801203c: 6cba ldr r2, [r7, #72] @ 0x48 801203e: 61fa str r2, [r7, #28] 8012040: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012042: 69b9 ldr r1, [r7, #24] 8012044: 69fa ldr r2, [r7, #28] 8012046: e841 2300 strex r3, r2, [r1] 801204a: 617b str r3, [r7, #20] return(result); 801204c: 697b ldr r3, [r7, #20] 801204e: 2b00 cmp r3, #0 8012050: d1e5 bne.n 801201e huart->RxState = HAL_UART_STATE_READY; 8012052: 687b ldr r3, [r7, #4] 8012054: 2220 movs r2, #32 8012056: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 801205a: 687b ldr r3, [r7, #4] 801205c: 2200 movs r2, #0 801205e: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8012062: 2303 movs r3, #3 8012064: e012 b.n 801208c } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8012066: 687b ldr r3, [r7, #4] 8012068: 2220 movs r2, #32 801206a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 801206e: 687b ldr r3, [r7, #4] 8012070: 2220 movs r2, #32 8012072: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012076: 687b ldr r3, [r7, #4] 8012078: 2200 movs r2, #0 801207a: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 801207c: 687b ldr r3, [r7, #4] 801207e: 2200 movs r2, #0 8012080: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8012082: 687b ldr r3, [r7, #4] 8012084: 2200 movs r2, #0 8012086: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 801208a: 2300 movs r3, #0 } 801208c: 4618 mov r0, r3 801208e: 3758 adds r7, #88 @ 0x58 8012090: 46bd mov sp, r7 8012092: bd80 pop {r7, pc} 08012094 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8012094: b580 push {r7, lr} 8012096: b084 sub sp, #16 8012098: af00 add r7, sp, #0 801209a: 60f8 str r0, [r7, #12] 801209c: 60b9 str r1, [r7, #8] 801209e: 603b str r3, [r7, #0] 80120a0: 4613 mov r3, r2 80120a2: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80120a4: e04f b.n 8012146 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80120a6: 69bb ldr r3, [r7, #24] 80120a8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80120ac: d04b beq.n 8012146 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80120ae: f7f3 f995 bl 80053dc 80120b2: 4602 mov r2, r0 80120b4: 683b ldr r3, [r7, #0] 80120b6: 1ad3 subs r3, r2, r3 80120b8: 69ba ldr r2, [r7, #24] 80120ba: 429a cmp r2, r3 80120bc: d302 bcc.n 80120c4 80120be: 69bb ldr r3, [r7, #24] 80120c0: 2b00 cmp r3, #0 80120c2: d101 bne.n 80120c8 { return HAL_TIMEOUT; 80120c4: 2303 movs r3, #3 80120c6: e04e b.n 8012166 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 80120c8: 68fb ldr r3, [r7, #12] 80120ca: 681b ldr r3, [r3, #0] 80120cc: 681b ldr r3, [r3, #0] 80120ce: f003 0304 and.w r3, r3, #4 80120d2: 2b00 cmp r3, #0 80120d4: d037 beq.n 8012146 80120d6: 68bb ldr r3, [r7, #8] 80120d8: 2b80 cmp r3, #128 @ 0x80 80120da: d034 beq.n 8012146 80120dc: 68bb ldr r3, [r7, #8] 80120de: 2b40 cmp r3, #64 @ 0x40 80120e0: d031 beq.n 8012146 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 80120e2: 68fb ldr r3, [r7, #12] 80120e4: 681b ldr r3, [r3, #0] 80120e6: 69db ldr r3, [r3, #28] 80120e8: f003 0308 and.w r3, r3, #8 80120ec: 2b08 cmp r3, #8 80120ee: d110 bne.n 8012112 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80120f0: 68fb ldr r3, [r7, #12] 80120f2: 681b ldr r3, [r3, #0] 80120f4: 2208 movs r2, #8 80120f6: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 80120f8: 68f8 ldr r0, [r7, #12] 80120fa: f000 f95b bl 80123b4 huart->ErrorCode = HAL_UART_ERROR_ORE; 80120fe: 68fb ldr r3, [r7, #12] 8012100: 2208 movs r2, #8 8012102: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012106: 68fb ldr r3, [r7, #12] 8012108: 2200 movs r2, #0 801210a: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 801210e: 2301 movs r3, #1 8012110: e029 b.n 8012166 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8012112: 68fb ldr r3, [r7, #12] 8012114: 681b ldr r3, [r3, #0] 8012116: 69db ldr r3, [r3, #28] 8012118: f403 6300 and.w r3, r3, #2048 @ 0x800 801211c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8012120: d111 bne.n 8012146 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8012122: 68fb ldr r3, [r7, #12] 8012124: 681b ldr r3, [r3, #0] 8012126: f44f 6200 mov.w r2, #2048 @ 0x800 801212a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 801212c: 68f8 ldr r0, [r7, #12] 801212e: f000 f941 bl 80123b4 huart->ErrorCode = HAL_UART_ERROR_RTO; 8012132: 68fb ldr r3, [r7, #12] 8012134: 2220 movs r2, #32 8012136: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 801213a: 68fb ldr r3, [r7, #12] 801213c: 2200 movs r2, #0 801213e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8012142: 2303 movs r3, #3 8012144: e00f b.n 8012166 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012146: 68fb ldr r3, [r7, #12] 8012148: 681b ldr r3, [r3, #0] 801214a: 69da ldr r2, [r3, #28] 801214c: 68bb ldr r3, [r7, #8] 801214e: 4013 ands r3, r2 8012150: 68ba ldr r2, [r7, #8] 8012152: 429a cmp r2, r3 8012154: bf0c ite eq 8012156: 2301 moveq r3, #1 8012158: 2300 movne r3, #0 801215a: b2db uxtb r3, r3 801215c: 461a mov r2, r3 801215e: 79fb ldrb r3, [r7, #7] 8012160: 429a cmp r2, r3 8012162: d0a0 beq.n 80120a6 } } } } return HAL_OK; 8012164: 2300 movs r3, #0 } 8012166: 4618 mov r0, r3 8012168: 3710 adds r7, #16 801216a: 46bd mov sp, r7 801216c: bd80 pop {r7, pc} ... 08012170 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012170: b480 push {r7} 8012172: b0a3 sub sp, #140 @ 0x8c 8012174: af00 add r7, sp, #0 8012176: 60f8 str r0, [r7, #12] 8012178: 60b9 str r1, [r7, #8] 801217a: 4613 mov r3, r2 801217c: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 801217e: 68fb ldr r3, [r7, #12] 8012180: 68ba ldr r2, [r7, #8] 8012182: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8012184: 68fb ldr r3, [r7, #12] 8012186: 88fa ldrh r2, [r7, #6] 8012188: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 801218c: 68fb ldr r3, [r7, #12] 801218e: 88fa ldrh r2, [r7, #6] 8012190: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8012194: 68fb ldr r3, [r7, #12] 8012196: 2200 movs r2, #0 8012198: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 801219a: 68fb ldr r3, [r7, #12] 801219c: 689b ldr r3, [r3, #8] 801219e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80121a2: d10e bne.n 80121c2 80121a4: 68fb ldr r3, [r7, #12] 80121a6: 691b ldr r3, [r3, #16] 80121a8: 2b00 cmp r3, #0 80121aa: d105 bne.n 80121b8 80121ac: 68fb ldr r3, [r7, #12] 80121ae: f240 12ff movw r2, #511 @ 0x1ff 80121b2: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80121b6: e02d b.n 8012214 80121b8: 68fb ldr r3, [r7, #12] 80121ba: 22ff movs r2, #255 @ 0xff 80121bc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80121c0: e028 b.n 8012214 80121c2: 68fb ldr r3, [r7, #12] 80121c4: 689b ldr r3, [r3, #8] 80121c6: 2b00 cmp r3, #0 80121c8: d10d bne.n 80121e6 80121ca: 68fb ldr r3, [r7, #12] 80121cc: 691b ldr r3, [r3, #16] 80121ce: 2b00 cmp r3, #0 80121d0: d104 bne.n 80121dc 80121d2: 68fb ldr r3, [r7, #12] 80121d4: 22ff movs r2, #255 @ 0xff 80121d6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80121da: e01b b.n 8012214 80121dc: 68fb ldr r3, [r7, #12] 80121de: 227f movs r2, #127 @ 0x7f 80121e0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 80121e4: e016 b.n 8012214 80121e6: 68fb ldr r3, [r7, #12] 80121e8: 689b ldr r3, [r3, #8] 80121ea: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80121ee: d10d bne.n 801220c 80121f0: 68fb ldr r3, [r7, #12] 80121f2: 691b ldr r3, [r3, #16] 80121f4: 2b00 cmp r3, #0 80121f6: d104 bne.n 8012202 80121f8: 68fb ldr r3, [r7, #12] 80121fa: 227f movs r2, #127 @ 0x7f 80121fc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012200: e008 b.n 8012214 8012202: 68fb ldr r3, [r7, #12] 8012204: 223f movs r2, #63 @ 0x3f 8012206: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 801220a: e003 b.n 8012214 801220c: 68fb ldr r3, [r7, #12] 801220e: 2200 movs r2, #0 8012210: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012214: 68fb ldr r3, [r7, #12] 8012216: 2200 movs r2, #0 8012218: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 801221c: 68fb ldr r3, [r7, #12] 801221e: 2222 movs r2, #34 @ 0x22 8012220: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012224: 68fb ldr r3, [r7, #12] 8012226: 681b ldr r3, [r3, #0] 8012228: 3308 adds r3, #8 801222a: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801222c: 6e7b ldr r3, [r7, #100] @ 0x64 801222e: e853 3f00 ldrex r3, [r3] 8012232: 663b str r3, [r7, #96] @ 0x60 return(result); 8012234: 6e3b ldr r3, [r7, #96] @ 0x60 8012236: f043 0301 orr.w r3, r3, #1 801223a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 801223e: 68fb ldr r3, [r7, #12] 8012240: 681b ldr r3, [r3, #0] 8012242: 3308 adds r3, #8 8012244: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012248: 673a str r2, [r7, #112] @ 0x70 801224a: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801224c: 6ef9 ldr r1, [r7, #108] @ 0x6c 801224e: 6f3a ldr r2, [r7, #112] @ 0x70 8012250: e841 2300 strex r3, r2, [r1] 8012254: 66bb str r3, [r7, #104] @ 0x68 return(result); 8012256: 6ebb ldr r3, [r7, #104] @ 0x68 8012258: 2b00 cmp r3, #0 801225a: d1e3 bne.n 8012224 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 801225c: 68fb ldr r3, [r7, #12] 801225e: 6e5b ldr r3, [r3, #100] @ 0x64 8012260: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8012264: d14f bne.n 8012306 8012266: 68fb ldr r3, [r7, #12] 8012268: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 801226c: 88fa ldrh r2, [r7, #6] 801226e: 429a cmp r2, r3 8012270: d349 bcc.n 8012306 { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012272: 68fb ldr r3, [r7, #12] 8012274: 689b ldr r3, [r3, #8] 8012276: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801227a: d107 bne.n 801228c 801227c: 68fb ldr r3, [r7, #12] 801227e: 691b ldr r3, [r3, #16] 8012280: 2b00 cmp r3, #0 8012282: d103 bne.n 801228c { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8012284: 68fb ldr r3, [r7, #12] 8012286: 4a47 ldr r2, [pc, #284] @ (80123a4 ) 8012288: 675a str r2, [r3, #116] @ 0x74 801228a: e002 b.n 8012292 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 801228c: 68fb ldr r3, [r7, #12] 801228e: 4a46 ldr r2, [pc, #280] @ (80123a8 ) 8012290: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012292: 68fb ldr r3, [r7, #12] 8012294: 691b ldr r3, [r3, #16] 8012296: 2b00 cmp r3, #0 8012298: d01a beq.n 80122d0 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 801229a: 68fb ldr r3, [r7, #12] 801229c: 681b ldr r3, [r3, #0] 801229e: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80122a0: 6d3b ldr r3, [r7, #80] @ 0x50 80122a2: e853 3f00 ldrex r3, [r3] 80122a6: 64fb str r3, [r7, #76] @ 0x4c return(result); 80122a8: 6cfb ldr r3, [r7, #76] @ 0x4c 80122aa: f443 7380 orr.w r3, r3, #256 @ 0x100 80122ae: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80122b2: 68fb ldr r3, [r7, #12] 80122b4: 681b ldr r3, [r3, #0] 80122b6: 461a mov r2, r3 80122b8: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80122bc: 65fb str r3, [r7, #92] @ 0x5c 80122be: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80122c0: 6db9 ldr r1, [r7, #88] @ 0x58 80122c2: 6dfa ldr r2, [r7, #92] @ 0x5c 80122c4: e841 2300 strex r3, r2, [r1] 80122c8: 657b str r3, [r7, #84] @ 0x54 return(result); 80122ca: 6d7b ldr r3, [r7, #84] @ 0x54 80122cc: 2b00 cmp r3, #0 80122ce: d1e4 bne.n 801229a } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80122d0: 68fb ldr r3, [r7, #12] 80122d2: 681b ldr r3, [r3, #0] 80122d4: 3308 adds r3, #8 80122d6: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80122d8: 6bfb ldr r3, [r7, #60] @ 0x3c 80122da: e853 3f00 ldrex r3, [r3] 80122de: 63bb str r3, [r7, #56] @ 0x38 return(result); 80122e0: 6bbb ldr r3, [r7, #56] @ 0x38 80122e2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80122e6: 67fb str r3, [r7, #124] @ 0x7c 80122e8: 68fb ldr r3, [r7, #12] 80122ea: 681b ldr r3, [r3, #0] 80122ec: 3308 adds r3, #8 80122ee: 6ffa ldr r2, [r7, #124] @ 0x7c 80122f0: 64ba str r2, [r7, #72] @ 0x48 80122f2: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80122f4: 6c79 ldr r1, [r7, #68] @ 0x44 80122f6: 6cba ldr r2, [r7, #72] @ 0x48 80122f8: e841 2300 strex r3, r2, [r1] 80122fc: 643b str r3, [r7, #64] @ 0x40 return(result); 80122fe: 6c3b ldr r3, [r7, #64] @ 0x40 8012300: 2b00 cmp r3, #0 8012302: d1e5 bne.n 80122d0 8012304: e046 b.n 8012394 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012306: 68fb ldr r3, [r7, #12] 8012308: 689b ldr r3, [r3, #8] 801230a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801230e: d107 bne.n 8012320 8012310: 68fb ldr r3, [r7, #12] 8012312: 691b ldr r3, [r3, #16] 8012314: 2b00 cmp r3, #0 8012316: d103 bne.n 8012320 { huart->RxISR = UART_RxISR_16BIT; 8012318: 68fb ldr r3, [r7, #12] 801231a: 4a24 ldr r2, [pc, #144] @ (80123ac ) 801231c: 675a str r2, [r3, #116] @ 0x74 801231e: e002 b.n 8012326 } else { huart->RxISR = UART_RxISR_8BIT; 8012320: 68fb ldr r3, [r7, #12] 8012322: 4a23 ldr r2, [pc, #140] @ (80123b0 ) 8012324: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012326: 68fb ldr r3, [r7, #12] 8012328: 691b ldr r3, [r3, #16] 801232a: 2b00 cmp r3, #0 801232c: d019 beq.n 8012362 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 801232e: 68fb ldr r3, [r7, #12] 8012330: 681b ldr r3, [r3, #0] 8012332: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012334: 6abb ldr r3, [r7, #40] @ 0x28 8012336: e853 3f00 ldrex r3, [r3] 801233a: 627b str r3, [r7, #36] @ 0x24 return(result); 801233c: 6a7b ldr r3, [r7, #36] @ 0x24 801233e: f443 7390 orr.w r3, r3, #288 @ 0x120 8012342: 677b str r3, [r7, #116] @ 0x74 8012344: 68fb ldr r3, [r7, #12] 8012346: 681b ldr r3, [r3, #0] 8012348: 461a mov r2, r3 801234a: 6f7b ldr r3, [r7, #116] @ 0x74 801234c: 637b str r3, [r7, #52] @ 0x34 801234e: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012350: 6b39 ldr r1, [r7, #48] @ 0x30 8012352: 6b7a ldr r2, [r7, #52] @ 0x34 8012354: e841 2300 strex r3, r2, [r1] 8012358: 62fb str r3, [r7, #44] @ 0x2c return(result); 801235a: 6afb ldr r3, [r7, #44] @ 0x2c 801235c: 2b00 cmp r3, #0 801235e: d1e6 bne.n 801232e 8012360: e018 b.n 8012394 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012362: 68fb ldr r3, [r7, #12] 8012364: 681b ldr r3, [r3, #0] 8012366: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012368: 697b ldr r3, [r7, #20] 801236a: e853 3f00 ldrex r3, [r3] 801236e: 613b str r3, [r7, #16] return(result); 8012370: 693b ldr r3, [r7, #16] 8012372: f043 0320 orr.w r3, r3, #32 8012376: 67bb str r3, [r7, #120] @ 0x78 8012378: 68fb ldr r3, [r7, #12] 801237a: 681b ldr r3, [r3, #0] 801237c: 461a mov r2, r3 801237e: 6fbb ldr r3, [r7, #120] @ 0x78 8012380: 623b str r3, [r7, #32] 8012382: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012384: 69f9 ldr r1, [r7, #28] 8012386: 6a3a ldr r2, [r7, #32] 8012388: e841 2300 strex r3, r2, [r1] 801238c: 61bb str r3, [r7, #24] return(result); 801238e: 69bb ldr r3, [r7, #24] 8012390: 2b00 cmp r3, #0 8012392: d1e6 bne.n 8012362 } } return HAL_OK; 8012394: 2300 movs r3, #0 } 8012396: 4618 mov r0, r3 8012398: 378c adds r7, #140 @ 0x8c 801239a: 46bd mov sp, r7 801239c: f85d 7b04 ldr.w r7, [sp], #4 80123a0: 4770 bx lr 80123a2: bf00 nop 80123a4: 08012f19 .word 0x08012f19 80123a8: 08012bb9 .word 0x08012bb9 80123ac: 08012a01 .word 0x08012a01 80123b0: 08012849 .word 0x08012849 080123b4 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 80123b4: b480 push {r7} 80123b6: b095 sub sp, #84 @ 0x54 80123b8: af00 add r7, sp, #0 80123ba: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80123bc: 687b ldr r3, [r7, #4] 80123be: 681b ldr r3, [r3, #0] 80123c0: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80123c2: 6b7b ldr r3, [r7, #52] @ 0x34 80123c4: e853 3f00 ldrex r3, [r3] 80123c8: 633b str r3, [r7, #48] @ 0x30 return(result); 80123ca: 6b3b ldr r3, [r7, #48] @ 0x30 80123cc: f423 7390 bic.w r3, r3, #288 @ 0x120 80123d0: 64fb str r3, [r7, #76] @ 0x4c 80123d2: 687b ldr r3, [r7, #4] 80123d4: 681b ldr r3, [r3, #0] 80123d6: 461a mov r2, r3 80123d8: 6cfb ldr r3, [r7, #76] @ 0x4c 80123da: 643b str r3, [r7, #64] @ 0x40 80123dc: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80123de: 6bf9 ldr r1, [r7, #60] @ 0x3c 80123e0: 6c3a ldr r2, [r7, #64] @ 0x40 80123e2: e841 2300 strex r3, r2, [r1] 80123e6: 63bb str r3, [r7, #56] @ 0x38 return(result); 80123e8: 6bbb ldr r3, [r7, #56] @ 0x38 80123ea: 2b00 cmp r3, #0 80123ec: d1e6 bne.n 80123bc ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80123ee: 687b ldr r3, [r7, #4] 80123f0: 681b ldr r3, [r3, #0] 80123f2: 3308 adds r3, #8 80123f4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80123f6: 6a3b ldr r3, [r7, #32] 80123f8: e853 3f00 ldrex r3, [r3] 80123fc: 61fb str r3, [r7, #28] return(result); 80123fe: 69fa ldr r2, [r7, #28] 8012400: 4b1e ldr r3, [pc, #120] @ (801247c ) 8012402: 4013 ands r3, r2 8012404: 64bb str r3, [r7, #72] @ 0x48 8012406: 687b ldr r3, [r7, #4] 8012408: 681b ldr r3, [r3, #0] 801240a: 3308 adds r3, #8 801240c: 6cba ldr r2, [r7, #72] @ 0x48 801240e: 62fa str r2, [r7, #44] @ 0x2c 8012410: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012412: 6ab9 ldr r1, [r7, #40] @ 0x28 8012414: 6afa ldr r2, [r7, #44] @ 0x2c 8012416: e841 2300 strex r3, r2, [r1] 801241a: 627b str r3, [r7, #36] @ 0x24 return(result); 801241c: 6a7b ldr r3, [r7, #36] @ 0x24 801241e: 2b00 cmp r3, #0 8012420: d1e5 bne.n 80123ee /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012422: 687b ldr r3, [r7, #4] 8012424: 6edb ldr r3, [r3, #108] @ 0x6c 8012426: 2b01 cmp r3, #1 8012428: d118 bne.n 801245c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801242a: 687b ldr r3, [r7, #4] 801242c: 681b ldr r3, [r3, #0] 801242e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012430: 68fb ldr r3, [r7, #12] 8012432: e853 3f00 ldrex r3, [r3] 8012436: 60bb str r3, [r7, #8] return(result); 8012438: 68bb ldr r3, [r7, #8] 801243a: f023 0310 bic.w r3, r3, #16 801243e: 647b str r3, [r7, #68] @ 0x44 8012440: 687b ldr r3, [r7, #4] 8012442: 681b ldr r3, [r3, #0] 8012444: 461a mov r2, r3 8012446: 6c7b ldr r3, [r7, #68] @ 0x44 8012448: 61bb str r3, [r7, #24] 801244a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801244c: 6979 ldr r1, [r7, #20] 801244e: 69ba ldr r2, [r7, #24] 8012450: e841 2300 strex r3, r2, [r1] 8012454: 613b str r3, [r7, #16] return(result); 8012456: 693b ldr r3, [r7, #16] 8012458: 2b00 cmp r3, #0 801245a: d1e6 bne.n 801242a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801245c: 687b ldr r3, [r7, #4] 801245e: 2220 movs r2, #32 8012460: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012464: 687b ldr r3, [r7, #4] 8012466: 2200 movs r2, #0 8012468: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 801246a: 687b ldr r3, [r7, #4] 801246c: 2200 movs r2, #0 801246e: 675a str r2, [r3, #116] @ 0x74 } 8012470: bf00 nop 8012472: 3754 adds r7, #84 @ 0x54 8012474: 46bd mov sp, r7 8012476: f85d 7b04 ldr.w r7, [sp], #4 801247a: 4770 bx lr 801247c: effffffe .word 0xeffffffe 08012480 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012480: b580 push {r7, lr} 8012482: b084 sub sp, #16 8012484: af00 add r7, sp, #0 8012486: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8012488: 687b ldr r3, [r7, #4] 801248a: 6b9b ldr r3, [r3, #56] @ 0x38 801248c: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 801248e: 68fb ldr r3, [r7, #12] 8012490: 2200 movs r2, #0 8012492: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 8012496: 68fb ldr r3, [r7, #12] 8012498: 2200 movs r2, #0 801249a: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 801249e: 68f8 ldr r0, [r7, #12] 80124a0: f7fe ff3a bl 8011318 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80124a4: bf00 nop 80124a6: 3710 adds r7, #16 80124a8: 46bd mov sp, r7 80124aa: bd80 pop {r7, pc} 080124ac : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 80124ac: b480 push {r7} 80124ae: b08f sub sp, #60 @ 0x3c 80124b0: af00 add r7, sp, #0 80124b2: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80124b4: 687b ldr r3, [r7, #4] 80124b6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80124ba: 2b21 cmp r3, #33 @ 0x21 80124bc: d14c bne.n 8012558 { if (huart->TxXferCount == 0U) 80124be: 687b ldr r3, [r7, #4] 80124c0: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80124c4: b29b uxth r3, r3 80124c6: 2b00 cmp r3, #0 80124c8: d132 bne.n 8012530 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 80124ca: 687b ldr r3, [r7, #4] 80124cc: 681b ldr r3, [r3, #0] 80124ce: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80124d0: 6a3b ldr r3, [r7, #32] 80124d2: e853 3f00 ldrex r3, [r3] 80124d6: 61fb str r3, [r7, #28] return(result); 80124d8: 69fb ldr r3, [r7, #28] 80124da: f023 0380 bic.w r3, r3, #128 @ 0x80 80124de: 637b str r3, [r7, #52] @ 0x34 80124e0: 687b ldr r3, [r7, #4] 80124e2: 681b ldr r3, [r3, #0] 80124e4: 461a mov r2, r3 80124e6: 6b7b ldr r3, [r7, #52] @ 0x34 80124e8: 62fb str r3, [r7, #44] @ 0x2c 80124ea: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80124ec: 6ab9 ldr r1, [r7, #40] @ 0x28 80124ee: 6afa ldr r2, [r7, #44] @ 0x2c 80124f0: e841 2300 strex r3, r2, [r1] 80124f4: 627b str r3, [r7, #36] @ 0x24 return(result); 80124f6: 6a7b ldr r3, [r7, #36] @ 0x24 80124f8: 2b00 cmp r3, #0 80124fa: d1e6 bne.n 80124ca /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80124fc: 687b ldr r3, [r7, #4] 80124fe: 681b ldr r3, [r3, #0] 8012500: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012502: 68fb ldr r3, [r7, #12] 8012504: e853 3f00 ldrex r3, [r3] 8012508: 60bb str r3, [r7, #8] return(result); 801250a: 68bb ldr r3, [r7, #8] 801250c: f043 0340 orr.w r3, r3, #64 @ 0x40 8012510: 633b str r3, [r7, #48] @ 0x30 8012512: 687b ldr r3, [r7, #4] 8012514: 681b ldr r3, [r3, #0] 8012516: 461a mov r2, r3 8012518: 6b3b ldr r3, [r7, #48] @ 0x30 801251a: 61bb str r3, [r7, #24] 801251c: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801251e: 6979 ldr r1, [r7, #20] 8012520: 69ba ldr r2, [r7, #24] 8012522: e841 2300 strex r3, r2, [r1] 8012526: 613b str r3, [r7, #16] return(result); 8012528: 693b ldr r3, [r7, #16] 801252a: 2b00 cmp r3, #0 801252c: d1e6 bne.n 80124fc huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 801252e: e013 b.n 8012558 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8012530: 687b ldr r3, [r7, #4] 8012532: 6d1b ldr r3, [r3, #80] @ 0x50 8012534: 781a ldrb r2, [r3, #0] 8012536: 687b ldr r3, [r7, #4] 8012538: 681b ldr r3, [r3, #0] 801253a: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 801253c: 687b ldr r3, [r7, #4] 801253e: 6d1b ldr r3, [r3, #80] @ 0x50 8012540: 1c5a adds r2, r3, #1 8012542: 687b ldr r3, [r7, #4] 8012544: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012546: 687b ldr r3, [r7, #4] 8012548: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801254c: b29b uxth r3, r3 801254e: 3b01 subs r3, #1 8012550: b29a uxth r2, r3 8012552: 687b ldr r3, [r7, #4] 8012554: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8012558: bf00 nop 801255a: 373c adds r7, #60 @ 0x3c 801255c: 46bd mov sp, r7 801255e: f85d 7b04 ldr.w r7, [sp], #4 8012562: 4770 bx lr 08012564 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 8012564: b480 push {r7} 8012566: b091 sub sp, #68 @ 0x44 8012568: af00 add r7, sp, #0 801256a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801256c: 687b ldr r3, [r7, #4] 801256e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012572: 2b21 cmp r3, #33 @ 0x21 8012574: d151 bne.n 801261a { if (huart->TxXferCount == 0U) 8012576: 687b ldr r3, [r7, #4] 8012578: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801257c: b29b uxth r3, r3 801257e: 2b00 cmp r3, #0 8012580: d132 bne.n 80125e8 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012582: 687b ldr r3, [r7, #4] 8012584: 681b ldr r3, [r3, #0] 8012586: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012588: 6a7b ldr r3, [r7, #36] @ 0x24 801258a: e853 3f00 ldrex r3, [r3] 801258e: 623b str r3, [r7, #32] return(result); 8012590: 6a3b ldr r3, [r7, #32] 8012592: f023 0380 bic.w r3, r3, #128 @ 0x80 8012596: 63bb str r3, [r7, #56] @ 0x38 8012598: 687b ldr r3, [r7, #4] 801259a: 681b ldr r3, [r3, #0] 801259c: 461a mov r2, r3 801259e: 6bbb ldr r3, [r7, #56] @ 0x38 80125a0: 633b str r3, [r7, #48] @ 0x30 80125a2: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125a4: 6af9 ldr r1, [r7, #44] @ 0x2c 80125a6: 6b3a ldr r2, [r7, #48] @ 0x30 80125a8: e841 2300 strex r3, r2, [r1] 80125ac: 62bb str r3, [r7, #40] @ 0x28 return(result); 80125ae: 6abb ldr r3, [r7, #40] @ 0x28 80125b0: 2b00 cmp r3, #0 80125b2: d1e6 bne.n 8012582 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80125b4: 687b ldr r3, [r7, #4] 80125b6: 681b ldr r3, [r3, #0] 80125b8: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80125ba: 693b ldr r3, [r7, #16] 80125bc: e853 3f00 ldrex r3, [r3] 80125c0: 60fb str r3, [r7, #12] return(result); 80125c2: 68fb ldr r3, [r7, #12] 80125c4: f043 0340 orr.w r3, r3, #64 @ 0x40 80125c8: 637b str r3, [r7, #52] @ 0x34 80125ca: 687b ldr r3, [r7, #4] 80125cc: 681b ldr r3, [r3, #0] 80125ce: 461a mov r2, r3 80125d0: 6b7b ldr r3, [r7, #52] @ 0x34 80125d2: 61fb str r3, [r7, #28] 80125d4: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80125d6: 69b9 ldr r1, [r7, #24] 80125d8: 69fa ldr r2, [r7, #28] 80125da: e841 2300 strex r3, r2, [r1] 80125de: 617b str r3, [r7, #20] return(result); 80125e0: 697b ldr r3, [r7, #20] 80125e2: 2b00 cmp r3, #0 80125e4: d1e6 bne.n 80125b4 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 80125e6: e018 b.n 801261a tmp = (const uint16_t *) huart->pTxBuffPtr; 80125e8: 687b ldr r3, [r7, #4] 80125ea: 6d1b ldr r3, [r3, #80] @ 0x50 80125ec: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 80125ee: 6bfb ldr r3, [r7, #60] @ 0x3c 80125f0: 881b ldrh r3, [r3, #0] 80125f2: 461a mov r2, r3 80125f4: 687b ldr r3, [r7, #4] 80125f6: 681b ldr r3, [r3, #0] 80125f8: f3c2 0208 ubfx r2, r2, #0, #9 80125fc: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 80125fe: 687b ldr r3, [r7, #4] 8012600: 6d1b ldr r3, [r3, #80] @ 0x50 8012602: 1c9a adds r2, r3, #2 8012604: 687b ldr r3, [r7, #4] 8012606: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012608: 687b ldr r3, [r7, #4] 801260a: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 801260e: b29b uxth r3, r3 8012610: 3b01 subs r3, #1 8012612: b29a uxth r2, r3 8012614: 687b ldr r3, [r7, #4] 8012616: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 801261a: bf00 nop 801261c: 3744 adds r7, #68 @ 0x44 801261e: 46bd mov sp, r7 8012620: f85d 7b04 ldr.w r7, [sp], #4 8012624: 4770 bx lr 08012626 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012626: b480 push {r7} 8012628: b091 sub sp, #68 @ 0x44 801262a: af00 add r7, sp, #0 801262c: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801262e: 687b ldr r3, [r7, #4] 8012630: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012634: 2b21 cmp r3, #33 @ 0x21 8012636: d160 bne.n 80126fa { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8012638: 687b ldr r3, [r7, #4] 801263a: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 801263e: 87fb strh r3, [r7, #62] @ 0x3e 8012640: e057 b.n 80126f2 { if (huart->TxXferCount == 0U) 8012642: 687b ldr r3, [r7, #4] 8012644: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012648: b29b uxth r3, r3 801264a: 2b00 cmp r3, #0 801264c: d133 bne.n 80126b6 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801264e: 687b ldr r3, [r7, #4] 8012650: 681b ldr r3, [r3, #0] 8012652: 3308 adds r3, #8 8012654: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012656: 6a7b ldr r3, [r7, #36] @ 0x24 8012658: e853 3f00 ldrex r3, [r3] 801265c: 623b str r3, [r7, #32] return(result); 801265e: 6a3b ldr r3, [r7, #32] 8012660: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8012664: 63bb str r3, [r7, #56] @ 0x38 8012666: 687b ldr r3, [r7, #4] 8012668: 681b ldr r3, [r3, #0] 801266a: 3308 adds r3, #8 801266c: 6bba ldr r2, [r7, #56] @ 0x38 801266e: 633a str r2, [r7, #48] @ 0x30 8012670: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012672: 6af9 ldr r1, [r7, #44] @ 0x2c 8012674: 6b3a ldr r2, [r7, #48] @ 0x30 8012676: e841 2300 strex r3, r2, [r1] 801267a: 62bb str r3, [r7, #40] @ 0x28 return(result); 801267c: 6abb ldr r3, [r7, #40] @ 0x28 801267e: 2b00 cmp r3, #0 8012680: d1e5 bne.n 801264e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012682: 687b ldr r3, [r7, #4] 8012684: 681b ldr r3, [r3, #0] 8012686: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012688: 693b ldr r3, [r7, #16] 801268a: e853 3f00 ldrex r3, [r3] 801268e: 60fb str r3, [r7, #12] return(result); 8012690: 68fb ldr r3, [r7, #12] 8012692: f043 0340 orr.w r3, r3, #64 @ 0x40 8012696: 637b str r3, [r7, #52] @ 0x34 8012698: 687b ldr r3, [r7, #4] 801269a: 681b ldr r3, [r3, #0] 801269c: 461a mov r2, r3 801269e: 6b7b ldr r3, [r7, #52] @ 0x34 80126a0: 61fb str r3, [r7, #28] 80126a2: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80126a4: 69b9 ldr r1, [r7, #24] 80126a6: 69fa ldr r2, [r7, #28] 80126a8: e841 2300 strex r3, r2, [r1] 80126ac: 617b str r3, [r7, #20] return(result); 80126ae: 697b ldr r3, [r7, #20] 80126b0: 2b00 cmp r3, #0 80126b2: d1e6 bne.n 8012682 break; /* force exit loop */ 80126b4: e021 b.n 80126fa } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 80126b6: 687b ldr r3, [r7, #4] 80126b8: 681b ldr r3, [r3, #0] 80126ba: 69db ldr r3, [r3, #28] 80126bc: f003 0380 and.w r3, r3, #128 @ 0x80 80126c0: 2b00 cmp r3, #0 80126c2: d013 beq.n 80126ec { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 80126c4: 687b ldr r3, [r7, #4] 80126c6: 6d1b ldr r3, [r3, #80] @ 0x50 80126c8: 781a ldrb r2, [r3, #0] 80126ca: 687b ldr r3, [r7, #4] 80126cc: 681b ldr r3, [r3, #0] 80126ce: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 80126d0: 687b ldr r3, [r7, #4] 80126d2: 6d1b ldr r3, [r3, #80] @ 0x50 80126d4: 1c5a adds r2, r3, #1 80126d6: 687b ldr r3, [r7, #4] 80126d8: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80126da: 687b ldr r3, [r7, #4] 80126dc: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80126e0: b29b uxth r3, r3 80126e2: 3b01 subs r3, #1 80126e4: b29a uxth r2, r3 80126e6: 687b ldr r3, [r7, #4] 80126e8: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80126ec: 8ffb ldrh r3, [r7, #62] @ 0x3e 80126ee: 3b01 subs r3, #1 80126f0: 87fb strh r3, [r7, #62] @ 0x3e 80126f2: 8ffb ldrh r3, [r7, #62] @ 0x3e 80126f4: 2b00 cmp r3, #0 80126f6: d1a4 bne.n 8012642 { /* Nothing to do */ } } } } 80126f8: e7ff b.n 80126fa 80126fa: bf00 nop 80126fc: 3744 adds r7, #68 @ 0x44 80126fe: 46bd mov sp, r7 8012700: f85d 7b04 ldr.w r7, [sp], #4 8012704: 4770 bx lr 08012706 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012706: b480 push {r7} 8012708: b091 sub sp, #68 @ 0x44 801270a: af00 add r7, sp, #0 801270c: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801270e: 687b ldr r3, [r7, #4] 8012710: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012714: 2b21 cmp r3, #33 @ 0x21 8012716: d165 bne.n 80127e4 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8012718: 687b ldr r3, [r7, #4] 801271a: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 801271e: 87fb strh r3, [r7, #62] @ 0x3e 8012720: e05c b.n 80127dc { if (huart->TxXferCount == 0U) 8012722: 687b ldr r3, [r7, #4] 8012724: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012728: b29b uxth r3, r3 801272a: 2b00 cmp r3, #0 801272c: d133 bne.n 8012796 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801272e: 687b ldr r3, [r7, #4] 8012730: 681b ldr r3, [r3, #0] 8012732: 3308 adds r3, #8 8012734: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012736: 6a3b ldr r3, [r7, #32] 8012738: e853 3f00 ldrex r3, [r3] 801273c: 61fb str r3, [r7, #28] return(result); 801273e: 69fb ldr r3, [r7, #28] 8012740: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8012744: 637b str r3, [r7, #52] @ 0x34 8012746: 687b ldr r3, [r7, #4] 8012748: 681b ldr r3, [r3, #0] 801274a: 3308 adds r3, #8 801274c: 6b7a ldr r2, [r7, #52] @ 0x34 801274e: 62fa str r2, [r7, #44] @ 0x2c 8012750: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012752: 6ab9 ldr r1, [r7, #40] @ 0x28 8012754: 6afa ldr r2, [r7, #44] @ 0x2c 8012756: e841 2300 strex r3, r2, [r1] 801275a: 627b str r3, [r7, #36] @ 0x24 return(result); 801275c: 6a7b ldr r3, [r7, #36] @ 0x24 801275e: 2b00 cmp r3, #0 8012760: d1e5 bne.n 801272e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012762: 687b ldr r3, [r7, #4] 8012764: 681b ldr r3, [r3, #0] 8012766: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012768: 68fb ldr r3, [r7, #12] 801276a: e853 3f00 ldrex r3, [r3] 801276e: 60bb str r3, [r7, #8] return(result); 8012770: 68bb ldr r3, [r7, #8] 8012772: f043 0340 orr.w r3, r3, #64 @ 0x40 8012776: 633b str r3, [r7, #48] @ 0x30 8012778: 687b ldr r3, [r7, #4] 801277a: 681b ldr r3, [r3, #0] 801277c: 461a mov r2, r3 801277e: 6b3b ldr r3, [r7, #48] @ 0x30 8012780: 61bb str r3, [r7, #24] 8012782: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012784: 6979 ldr r1, [r7, #20] 8012786: 69ba ldr r2, [r7, #24] 8012788: e841 2300 strex r3, r2, [r1] 801278c: 613b str r3, [r7, #16] return(result); 801278e: 693b ldr r3, [r7, #16] 8012790: 2b00 cmp r3, #0 8012792: d1e6 bne.n 8012762 break; /* force exit loop */ 8012794: e026 b.n 80127e4 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8012796: 687b ldr r3, [r7, #4] 8012798: 681b ldr r3, [r3, #0] 801279a: 69db ldr r3, [r3, #28] 801279c: f003 0380 and.w r3, r3, #128 @ 0x80 80127a0: 2b00 cmp r3, #0 80127a2: d018 beq.n 80127d6 { tmp = (const uint16_t *) huart->pTxBuffPtr; 80127a4: 687b ldr r3, [r7, #4] 80127a6: 6d1b ldr r3, [r3, #80] @ 0x50 80127a8: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 80127aa: 6bbb ldr r3, [r7, #56] @ 0x38 80127ac: 881b ldrh r3, [r3, #0] 80127ae: 461a mov r2, r3 80127b0: 687b ldr r3, [r7, #4] 80127b2: 681b ldr r3, [r3, #0] 80127b4: f3c2 0208 ubfx r2, r2, #0, #9 80127b8: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 80127ba: 687b ldr r3, [r7, #4] 80127bc: 6d1b ldr r3, [r3, #80] @ 0x50 80127be: 1c9a adds r2, r3, #2 80127c0: 687b ldr r3, [r7, #4] 80127c2: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80127c4: 687b ldr r3, [r7, #4] 80127c6: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80127ca: b29b uxth r3, r3 80127cc: 3b01 subs r3, #1 80127ce: b29a uxth r2, r3 80127d0: 687b ldr r3, [r7, #4] 80127d2: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80127d6: 8ffb ldrh r3, [r7, #62] @ 0x3e 80127d8: 3b01 subs r3, #1 80127da: 87fb strh r3, [r7, #62] @ 0x3e 80127dc: 8ffb ldrh r3, [r7, #62] @ 0x3e 80127de: 2b00 cmp r3, #0 80127e0: d19f bne.n 8012722 { /* Nothing to do */ } } } } 80127e2: e7ff b.n 80127e4 80127e4: bf00 nop 80127e6: 3744 adds r7, #68 @ 0x44 80127e8: 46bd mov sp, r7 80127ea: f85d 7b04 ldr.w r7, [sp], #4 80127ee: 4770 bx lr 080127f0 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80127f0: b580 push {r7, lr} 80127f2: b088 sub sp, #32 80127f4: af00 add r7, sp, #0 80127f6: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80127f8: 687b ldr r3, [r7, #4] 80127fa: 681b ldr r3, [r3, #0] 80127fc: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80127fe: 68fb ldr r3, [r7, #12] 8012800: e853 3f00 ldrex r3, [r3] 8012804: 60bb str r3, [r7, #8] return(result); 8012806: 68bb ldr r3, [r7, #8] 8012808: f023 0340 bic.w r3, r3, #64 @ 0x40 801280c: 61fb str r3, [r7, #28] 801280e: 687b ldr r3, [r7, #4] 8012810: 681b ldr r3, [r3, #0] 8012812: 461a mov r2, r3 8012814: 69fb ldr r3, [r7, #28] 8012816: 61bb str r3, [r7, #24] 8012818: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801281a: 6979 ldr r1, [r7, #20] 801281c: 69ba ldr r2, [r7, #24] 801281e: e841 2300 strex r3, r2, [r1] 8012822: 613b str r3, [r7, #16] return(result); 8012824: 693b ldr r3, [r7, #16] 8012826: 2b00 cmp r3, #0 8012828: d1e6 bne.n 80127f8 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801282a: 687b ldr r3, [r7, #4] 801282c: 2220 movs r2, #32 801282e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 8012832: 687b ldr r3, [r7, #4] 8012834: 2200 movs r2, #0 8012836: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8012838: 6878 ldr r0, [r7, #4] 801283a: f7f1 fd65 bl 8004308 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 801283e: bf00 nop 8012840: 3720 adds r7, #32 8012842: 46bd mov sp, r7 8012844: bd80 pop {r7, pc} ... 08012848 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8012848: b580 push {r7, lr} 801284a: b09c sub sp, #112 @ 0x70 801284c: af00 add r7, sp, #0 801284e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8012850: 687b ldr r3, [r7, #4] 8012852: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012856: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 801285a: 687b ldr r3, [r7, #4] 801285c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012860: 2b22 cmp r3, #34 @ 0x22 8012862: f040 80be bne.w 80129e2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012866: 687b ldr r3, [r7, #4] 8012868: 681b ldr r3, [r3, #0] 801286a: 6a5b ldr r3, [r3, #36] @ 0x24 801286c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8012870: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8012874: b2d9 uxtb r1, r3 8012876: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 801287a: b2da uxtb r2, r3 801287c: 687b ldr r3, [r7, #4] 801287e: 6d9b ldr r3, [r3, #88] @ 0x58 8012880: 400a ands r2, r1 8012882: b2d2 uxtb r2, r2 8012884: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8012886: 687b ldr r3, [r7, #4] 8012888: 6d9b ldr r3, [r3, #88] @ 0x58 801288a: 1c5a adds r2, r3, #1 801288c: 687b ldr r3, [r7, #4] 801288e: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012890: 687b ldr r3, [r7, #4] 8012892: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012896: b29b uxth r3, r3 8012898: 3b01 subs r3, #1 801289a: b29a uxth r2, r3 801289c: 687b ldr r3, [r7, #4] 801289e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 80128a2: 687b ldr r3, [r7, #4] 80128a4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80128a8: b29b uxth r3, r3 80128aa: 2b00 cmp r3, #0 80128ac: f040 80a1 bne.w 80129f2 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80128b0: 687b ldr r3, [r7, #4] 80128b2: 681b ldr r3, [r3, #0] 80128b4: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80128b6: 6cfb ldr r3, [r7, #76] @ 0x4c 80128b8: e853 3f00 ldrex r3, [r3] 80128bc: 64bb str r3, [r7, #72] @ 0x48 return(result); 80128be: 6cbb ldr r3, [r7, #72] @ 0x48 80128c0: f423 7390 bic.w r3, r3, #288 @ 0x120 80128c4: 66bb str r3, [r7, #104] @ 0x68 80128c6: 687b ldr r3, [r7, #4] 80128c8: 681b ldr r3, [r3, #0] 80128ca: 461a mov r2, r3 80128cc: 6ebb ldr r3, [r7, #104] @ 0x68 80128ce: 65bb str r3, [r7, #88] @ 0x58 80128d0: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80128d2: 6d79 ldr r1, [r7, #84] @ 0x54 80128d4: 6dba ldr r2, [r7, #88] @ 0x58 80128d6: e841 2300 strex r3, r2, [r1] 80128da: 653b str r3, [r7, #80] @ 0x50 return(result); 80128dc: 6d3b ldr r3, [r7, #80] @ 0x50 80128de: 2b00 cmp r3, #0 80128e0: d1e6 bne.n 80128b0 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80128e2: 687b ldr r3, [r7, #4] 80128e4: 681b ldr r3, [r3, #0] 80128e6: 3308 adds r3, #8 80128e8: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80128ea: 6bbb ldr r3, [r7, #56] @ 0x38 80128ec: e853 3f00 ldrex r3, [r3] 80128f0: 637b str r3, [r7, #52] @ 0x34 return(result); 80128f2: 6b7b ldr r3, [r7, #52] @ 0x34 80128f4: f023 0301 bic.w r3, r3, #1 80128f8: 667b str r3, [r7, #100] @ 0x64 80128fa: 687b ldr r3, [r7, #4] 80128fc: 681b ldr r3, [r3, #0] 80128fe: 3308 adds r3, #8 8012900: 6e7a ldr r2, [r7, #100] @ 0x64 8012902: 647a str r2, [r7, #68] @ 0x44 8012904: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012906: 6c39 ldr r1, [r7, #64] @ 0x40 8012908: 6c7a ldr r2, [r7, #68] @ 0x44 801290a: e841 2300 strex r3, r2, [r1] 801290e: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012910: 6bfb ldr r3, [r7, #60] @ 0x3c 8012912: 2b00 cmp r3, #0 8012914: d1e5 bne.n 80128e2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012916: 687b ldr r3, [r7, #4] 8012918: 2220 movs r2, #32 801291a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 801291e: 687b ldr r3, [r7, #4] 8012920: 2200 movs r2, #0 8012922: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012924: 687b ldr r3, [r7, #4] 8012926: 2200 movs r2, #0 8012928: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801292a: 687b ldr r3, [r7, #4] 801292c: 681b ldr r3, [r3, #0] 801292e: 4a33 ldr r2, [pc, #204] @ (80129fc ) 8012930: 4293 cmp r3, r2 8012932: d01f beq.n 8012974 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012934: 687b ldr r3, [r7, #4] 8012936: 681b ldr r3, [r3, #0] 8012938: 685b ldr r3, [r3, #4] 801293a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801293e: 2b00 cmp r3, #0 8012940: d018 beq.n 8012974 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012942: 687b ldr r3, [r7, #4] 8012944: 681b ldr r3, [r3, #0] 8012946: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012948: 6a7b ldr r3, [r7, #36] @ 0x24 801294a: e853 3f00 ldrex r3, [r3] 801294e: 623b str r3, [r7, #32] return(result); 8012950: 6a3b ldr r3, [r7, #32] 8012952: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8012956: 663b str r3, [r7, #96] @ 0x60 8012958: 687b ldr r3, [r7, #4] 801295a: 681b ldr r3, [r3, #0] 801295c: 461a mov r2, r3 801295e: 6e3b ldr r3, [r7, #96] @ 0x60 8012960: 633b str r3, [r7, #48] @ 0x30 8012962: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012964: 6af9 ldr r1, [r7, #44] @ 0x2c 8012966: 6b3a ldr r2, [r7, #48] @ 0x30 8012968: e841 2300 strex r3, r2, [r1] 801296c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801296e: 6abb ldr r3, [r7, #40] @ 0x28 8012970: 2b00 cmp r3, #0 8012972: d1e6 bne.n 8012942 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012974: 687b ldr r3, [r7, #4] 8012976: 6edb ldr r3, [r3, #108] @ 0x6c 8012978: 2b01 cmp r3, #1 801297a: d12e bne.n 80129da { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801297c: 687b ldr r3, [r7, #4] 801297e: 2200 movs r2, #0 8012980: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012982: 687b ldr r3, [r7, #4] 8012984: 681b ldr r3, [r3, #0] 8012986: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012988: 693b ldr r3, [r7, #16] 801298a: e853 3f00 ldrex r3, [r3] 801298e: 60fb str r3, [r7, #12] return(result); 8012990: 68fb ldr r3, [r7, #12] 8012992: f023 0310 bic.w r3, r3, #16 8012996: 65fb str r3, [r7, #92] @ 0x5c 8012998: 687b ldr r3, [r7, #4] 801299a: 681b ldr r3, [r3, #0] 801299c: 461a mov r2, r3 801299e: 6dfb ldr r3, [r7, #92] @ 0x5c 80129a0: 61fb str r3, [r7, #28] 80129a2: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80129a4: 69b9 ldr r1, [r7, #24] 80129a6: 69fa ldr r2, [r7, #28] 80129a8: e841 2300 strex r3, r2, [r1] 80129ac: 617b str r3, [r7, #20] return(result); 80129ae: 697b ldr r3, [r7, #20] 80129b0: 2b00 cmp r3, #0 80129b2: d1e6 bne.n 8012982 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 80129b4: 687b ldr r3, [r7, #4] 80129b6: 681b ldr r3, [r3, #0] 80129b8: 69db ldr r3, [r3, #28] 80129ba: f003 0310 and.w r3, r3, #16 80129be: 2b10 cmp r3, #16 80129c0: d103 bne.n 80129ca { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80129c2: 687b ldr r3, [r7, #4] 80129c4: 681b ldr r3, [r3, #0] 80129c6: 2210 movs r2, #16 80129c8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80129ca: 687b ldr r3, [r7, #4] 80129cc: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80129d0: 4619 mov r1, r3 80129d2: 6878 ldr r0, [r7, #4] 80129d4: f7f1 fc6e bl 80042b4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80129d8: e00b b.n 80129f2 HAL_UART_RxCpltCallback(huart); 80129da: 6878 ldr r0, [r7, #4] 80129dc: f7f1 fc60 bl 80042a0 } 80129e0: e007 b.n 80129f2 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80129e2: 687b ldr r3, [r7, #4] 80129e4: 681b ldr r3, [r3, #0] 80129e6: 699a ldr r2, [r3, #24] 80129e8: 687b ldr r3, [r7, #4] 80129ea: 681b ldr r3, [r3, #0] 80129ec: f042 0208 orr.w r2, r2, #8 80129f0: 619a str r2, [r3, #24] } 80129f2: bf00 nop 80129f4: 3770 adds r7, #112 @ 0x70 80129f6: 46bd mov sp, r7 80129f8: bd80 pop {r7, pc} 80129fa: bf00 nop 80129fc: 58000c00 .word 0x58000c00 08012a00 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 8012a00: b580 push {r7, lr} 8012a02: b09c sub sp, #112 @ 0x70 8012a04: af00 add r7, sp, #0 8012a06: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8012a08: 687b ldr r3, [r7, #4] 8012a0a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012a0e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012a12: 687b ldr r3, [r7, #4] 8012a14: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012a18: 2b22 cmp r3, #34 @ 0x22 8012a1a: f040 80be bne.w 8012b9a { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012a1e: 687b ldr r3, [r7, #4] 8012a20: 681b ldr r3, [r3, #0] 8012a22: 6a5b ldr r3, [r3, #36] @ 0x24 8012a24: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 8012a28: 687b ldr r3, [r7, #4] 8012a2a: 6d9b ldr r3, [r3, #88] @ 0x58 8012a2c: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 8012a2e: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 8012a32: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 8012a36: 4013 ands r3, r2 8012a38: b29a uxth r2, r3 8012a3a: 6ebb ldr r3, [r7, #104] @ 0x68 8012a3c: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012a3e: 687b ldr r3, [r7, #4] 8012a40: 6d9b ldr r3, [r3, #88] @ 0x58 8012a42: 1c9a adds r2, r3, #2 8012a44: 687b ldr r3, [r7, #4] 8012a46: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012a48: 687b ldr r3, [r7, #4] 8012a4a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012a4e: b29b uxth r3, r3 8012a50: 3b01 subs r3, #1 8012a52: b29a uxth r2, r3 8012a54: 687b ldr r3, [r7, #4] 8012a56: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8012a5a: 687b ldr r3, [r7, #4] 8012a5c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012a60: b29b uxth r3, r3 8012a62: 2b00 cmp r3, #0 8012a64: f040 80a1 bne.w 8012baa { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012a68: 687b ldr r3, [r7, #4] 8012a6a: 681b ldr r3, [r3, #0] 8012a6c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a6e: 6cbb ldr r3, [r7, #72] @ 0x48 8012a70: e853 3f00 ldrex r3, [r3] 8012a74: 647b str r3, [r7, #68] @ 0x44 return(result); 8012a76: 6c7b ldr r3, [r7, #68] @ 0x44 8012a78: f423 7390 bic.w r3, r3, #288 @ 0x120 8012a7c: 667b str r3, [r7, #100] @ 0x64 8012a7e: 687b ldr r3, [r7, #4] 8012a80: 681b ldr r3, [r3, #0] 8012a82: 461a mov r2, r3 8012a84: 6e7b ldr r3, [r7, #100] @ 0x64 8012a86: 657b str r3, [r7, #84] @ 0x54 8012a88: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a8a: 6d39 ldr r1, [r7, #80] @ 0x50 8012a8c: 6d7a ldr r2, [r7, #84] @ 0x54 8012a8e: e841 2300 strex r3, r2, [r1] 8012a92: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012a94: 6cfb ldr r3, [r7, #76] @ 0x4c 8012a96: 2b00 cmp r3, #0 8012a98: d1e6 bne.n 8012a68 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012a9a: 687b ldr r3, [r7, #4] 8012a9c: 681b ldr r3, [r3, #0] 8012a9e: 3308 adds r3, #8 8012aa0: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012aa2: 6b7b ldr r3, [r7, #52] @ 0x34 8012aa4: e853 3f00 ldrex r3, [r3] 8012aa8: 633b str r3, [r7, #48] @ 0x30 return(result); 8012aaa: 6b3b ldr r3, [r7, #48] @ 0x30 8012aac: f023 0301 bic.w r3, r3, #1 8012ab0: 663b str r3, [r7, #96] @ 0x60 8012ab2: 687b ldr r3, [r7, #4] 8012ab4: 681b ldr r3, [r3, #0] 8012ab6: 3308 adds r3, #8 8012ab8: 6e3a ldr r2, [r7, #96] @ 0x60 8012aba: 643a str r2, [r7, #64] @ 0x40 8012abc: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012abe: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012ac0: 6c3a ldr r2, [r7, #64] @ 0x40 8012ac2: e841 2300 strex r3, r2, [r1] 8012ac6: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012ac8: 6bbb ldr r3, [r7, #56] @ 0x38 8012aca: 2b00 cmp r3, #0 8012acc: d1e5 bne.n 8012a9a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012ace: 687b ldr r3, [r7, #4] 8012ad0: 2220 movs r2, #32 8012ad2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8012ad6: 687b ldr r3, [r7, #4] 8012ad8: 2200 movs r2, #0 8012ada: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012adc: 687b ldr r3, [r7, #4] 8012ade: 2200 movs r2, #0 8012ae0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8012ae2: 687b ldr r3, [r7, #4] 8012ae4: 681b ldr r3, [r3, #0] 8012ae6: 4a33 ldr r2, [pc, #204] @ (8012bb4 ) 8012ae8: 4293 cmp r3, r2 8012aea: d01f beq.n 8012b2c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012aec: 687b ldr r3, [r7, #4] 8012aee: 681b ldr r3, [r3, #0] 8012af0: 685b ldr r3, [r3, #4] 8012af2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8012af6: 2b00 cmp r3, #0 8012af8: d018 beq.n 8012b2c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012afa: 687b ldr r3, [r7, #4] 8012afc: 681b ldr r3, [r3, #0] 8012afe: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012b00: 6a3b ldr r3, [r7, #32] 8012b02: e853 3f00 ldrex r3, [r3] 8012b06: 61fb str r3, [r7, #28] return(result); 8012b08: 69fb ldr r3, [r7, #28] 8012b0a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8012b0e: 65fb str r3, [r7, #92] @ 0x5c 8012b10: 687b ldr r3, [r7, #4] 8012b12: 681b ldr r3, [r3, #0] 8012b14: 461a mov r2, r3 8012b16: 6dfb ldr r3, [r7, #92] @ 0x5c 8012b18: 62fb str r3, [r7, #44] @ 0x2c 8012b1a: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012b1c: 6ab9 ldr r1, [r7, #40] @ 0x28 8012b1e: 6afa ldr r2, [r7, #44] @ 0x2c 8012b20: e841 2300 strex r3, r2, [r1] 8012b24: 627b str r3, [r7, #36] @ 0x24 return(result); 8012b26: 6a7b ldr r3, [r7, #36] @ 0x24 8012b28: 2b00 cmp r3, #0 8012b2a: d1e6 bne.n 8012afa } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012b2c: 687b ldr r3, [r7, #4] 8012b2e: 6edb ldr r3, [r3, #108] @ 0x6c 8012b30: 2b01 cmp r3, #1 8012b32: d12e bne.n 8012b92 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012b34: 687b ldr r3, [r7, #4] 8012b36: 2200 movs r2, #0 8012b38: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012b3a: 687b ldr r3, [r7, #4] 8012b3c: 681b ldr r3, [r3, #0] 8012b3e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012b40: 68fb ldr r3, [r7, #12] 8012b42: e853 3f00 ldrex r3, [r3] 8012b46: 60bb str r3, [r7, #8] return(result); 8012b48: 68bb ldr r3, [r7, #8] 8012b4a: f023 0310 bic.w r3, r3, #16 8012b4e: 65bb str r3, [r7, #88] @ 0x58 8012b50: 687b ldr r3, [r7, #4] 8012b52: 681b ldr r3, [r3, #0] 8012b54: 461a mov r2, r3 8012b56: 6dbb ldr r3, [r7, #88] @ 0x58 8012b58: 61bb str r3, [r7, #24] 8012b5a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012b5c: 6979 ldr r1, [r7, #20] 8012b5e: 69ba ldr r2, [r7, #24] 8012b60: e841 2300 strex r3, r2, [r1] 8012b64: 613b str r3, [r7, #16] return(result); 8012b66: 693b ldr r3, [r7, #16] 8012b68: 2b00 cmp r3, #0 8012b6a: d1e6 bne.n 8012b3a if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8012b6c: 687b ldr r3, [r7, #4] 8012b6e: 681b ldr r3, [r3, #0] 8012b70: 69db ldr r3, [r3, #28] 8012b72: f003 0310 and.w r3, r3, #16 8012b76: 2b10 cmp r3, #16 8012b78: d103 bne.n 8012b82 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8012b7a: 687b ldr r3, [r7, #4] 8012b7c: 681b ldr r3, [r3, #0] 8012b7e: 2210 movs r2, #16 8012b80: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012b82: 687b ldr r3, [r7, #4] 8012b84: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8012b88: 4619 mov r1, r3 8012b8a: 6878 ldr r0, [r7, #4] 8012b8c: f7f1 fb92 bl 80042b4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8012b90: e00b b.n 8012baa HAL_UART_RxCpltCallback(huart); 8012b92: 6878 ldr r0, [r7, #4] 8012b94: f7f1 fb84 bl 80042a0 } 8012b98: e007 b.n 8012baa __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8012b9a: 687b ldr r3, [r7, #4] 8012b9c: 681b ldr r3, [r3, #0] 8012b9e: 699a ldr r2, [r3, #24] 8012ba0: 687b ldr r3, [r7, #4] 8012ba2: 681b ldr r3, [r3, #0] 8012ba4: f042 0208 orr.w r2, r2, #8 8012ba8: 619a str r2, [r3, #24] } 8012baa: bf00 nop 8012bac: 3770 adds r7, #112 @ 0x70 8012bae: 46bd mov sp, r7 8012bb0: bd80 pop {r7, pc} 8012bb2: bf00 nop 8012bb4: 58000c00 .word 0x58000c00 08012bb8 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012bb8: b580 push {r7, lr} 8012bba: b0ac sub sp, #176 @ 0xb0 8012bbc: af00 add r7, sp, #0 8012bbe: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8012bc0: 687b ldr r3, [r7, #4] 8012bc2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012bc6: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8012bca: 687b ldr r3, [r7, #4] 8012bcc: 681b ldr r3, [r3, #0] 8012bce: 69db ldr r3, [r3, #28] 8012bd0: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012bd4: 687b ldr r3, [r7, #4] 8012bd6: 681b ldr r3, [r3, #0] 8012bd8: 681b ldr r3, [r3, #0] 8012bda: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012bde: 687b ldr r3, [r7, #4] 8012be0: 681b ldr r3, [r3, #0] 8012be2: 689b ldr r3, [r3, #8] 8012be4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012be8: 687b ldr r3, [r7, #4] 8012bea: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012bee: 2b22 cmp r3, #34 @ 0x22 8012bf0: f040 8180 bne.w 8012ef4 { nb_rx_data = huart->NbRxDataToProcess; 8012bf4: 687b ldr r3, [r7, #4] 8012bf6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012bfa: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012bfe: e123 b.n 8012e48 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012c00: 687b ldr r3, [r7, #4] 8012c02: 681b ldr r3, [r3, #0] 8012c04: 6a5b ldr r3, [r3, #36] @ 0x24 8012c06: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8012c0a: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 8012c0e: b2d9 uxtb r1, r3 8012c10: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 8012c14: b2da uxtb r2, r3 8012c16: 687b ldr r3, [r7, #4] 8012c18: 6d9b ldr r3, [r3, #88] @ 0x58 8012c1a: 400a ands r2, r1 8012c1c: b2d2 uxtb r2, r2 8012c1e: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8012c20: 687b ldr r3, [r7, #4] 8012c22: 6d9b ldr r3, [r3, #88] @ 0x58 8012c24: 1c5a adds r2, r3, #1 8012c26: 687b ldr r3, [r7, #4] 8012c28: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012c2a: 687b ldr r3, [r7, #4] 8012c2c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012c30: b29b uxth r3, r3 8012c32: 3b01 subs r3, #1 8012c34: b29a uxth r2, r3 8012c36: 687b ldr r3, [r7, #4] 8012c38: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8012c3c: 687b ldr r3, [r7, #4] 8012c3e: 681b ldr r3, [r3, #0] 8012c40: 69db ldr r3, [r3, #28] 8012c42: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8012c46: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012c4a: f003 0307 and.w r3, r3, #7 8012c4e: 2b00 cmp r3, #0 8012c50: d053 beq.n 8012cfa { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8012c52: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012c56: f003 0301 and.w r3, r3, #1 8012c5a: 2b00 cmp r3, #0 8012c5c: d011 beq.n 8012c82 8012c5e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8012c62: f403 7380 and.w r3, r3, #256 @ 0x100 8012c66: 2b00 cmp r3, #0 8012c68: d00b beq.n 8012c82 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8012c6a: 687b ldr r3, [r7, #4] 8012c6c: 681b ldr r3, [r3, #0] 8012c6e: 2201 movs r2, #1 8012c70: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8012c72: 687b ldr r3, [r7, #4] 8012c74: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012c78: f043 0201 orr.w r2, r3, #1 8012c7c: 687b ldr r3, [r7, #4] 8012c7e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012c82: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012c86: f003 0302 and.w r3, r3, #2 8012c8a: 2b00 cmp r3, #0 8012c8c: d011 beq.n 8012cb2 8012c8e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012c92: f003 0301 and.w r3, r3, #1 8012c96: 2b00 cmp r3, #0 8012c98: d00b beq.n 8012cb2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8012c9a: 687b ldr r3, [r7, #4] 8012c9c: 681b ldr r3, [r3, #0] 8012c9e: 2202 movs r2, #2 8012ca0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8012ca2: 687b ldr r3, [r7, #4] 8012ca4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012ca8: f043 0204 orr.w r2, r3, #4 8012cac: 687b ldr r3, [r7, #4] 8012cae: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012cb2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012cb6: f003 0304 and.w r3, r3, #4 8012cba: 2b00 cmp r3, #0 8012cbc: d011 beq.n 8012ce2 8012cbe: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012cc2: f003 0301 and.w r3, r3, #1 8012cc6: 2b00 cmp r3, #0 8012cc8: d00b beq.n 8012ce2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8012cca: 687b ldr r3, [r7, #4] 8012ccc: 681b ldr r3, [r3, #0] 8012cce: 2204 movs r2, #4 8012cd0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8012cd2: 687b ldr r3, [r7, #4] 8012cd4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012cd8: f043 0202 orr.w r2, r3, #2 8012cdc: 687b ldr r3, [r7, #4] 8012cde: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8012ce2: 687b ldr r3, [r7, #4] 8012ce4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012ce8: 2b00 cmp r3, #0 8012cea: d006 beq.n 8012cfa #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012cec: 6878 ldr r0, [r7, #4] 8012cee: f7fe fb13 bl 8011318 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012cf2: 687b ldr r3, [r7, #4] 8012cf4: 2200 movs r2, #0 8012cf6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8012cfa: 687b ldr r3, [r7, #4] 8012cfc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012d00: b29b uxth r3, r3 8012d02: 2b00 cmp r3, #0 8012d04: f040 80a0 bne.w 8012e48 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012d08: 687b ldr r3, [r7, #4] 8012d0a: 681b ldr r3, [r3, #0] 8012d0c: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d0e: 6f3b ldr r3, [r7, #112] @ 0x70 8012d10: e853 3f00 ldrex r3, [r3] 8012d14: 66fb str r3, [r7, #108] @ 0x6c return(result); 8012d16: 6efb ldr r3, [r7, #108] @ 0x6c 8012d18: f423 7380 bic.w r3, r3, #256 @ 0x100 8012d1c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8012d20: 687b ldr r3, [r7, #4] 8012d22: 681b ldr r3, [r3, #0] 8012d24: 461a mov r2, r3 8012d26: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8012d2a: 67fb str r3, [r7, #124] @ 0x7c 8012d2c: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d2e: 6fb9 ldr r1, [r7, #120] @ 0x78 8012d30: 6ffa ldr r2, [r7, #124] @ 0x7c 8012d32: e841 2300 strex r3, r2, [r1] 8012d36: 677b str r3, [r7, #116] @ 0x74 return(result); 8012d38: 6f7b ldr r3, [r7, #116] @ 0x74 8012d3a: 2b00 cmp r3, #0 8012d3c: d1e4 bne.n 8012d08 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012d3e: 687b ldr r3, [r7, #4] 8012d40: 681b ldr r3, [r3, #0] 8012d42: 3308 adds r3, #8 8012d44: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d46: 6dfb ldr r3, [r7, #92] @ 0x5c 8012d48: e853 3f00 ldrex r3, [r3] 8012d4c: 65bb str r3, [r7, #88] @ 0x58 return(result); 8012d4e: 6dba ldr r2, [r7, #88] @ 0x58 8012d50: 4b6e ldr r3, [pc, #440] @ (8012f0c ) 8012d52: 4013 ands r3, r2 8012d54: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8012d58: 687b ldr r3, [r7, #4] 8012d5a: 681b ldr r3, [r3, #0] 8012d5c: 3308 adds r3, #8 8012d5e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8012d62: 66ba str r2, [r7, #104] @ 0x68 8012d64: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d66: 6e79 ldr r1, [r7, #100] @ 0x64 8012d68: 6eba ldr r2, [r7, #104] @ 0x68 8012d6a: e841 2300 strex r3, r2, [r1] 8012d6e: 663b str r3, [r7, #96] @ 0x60 return(result); 8012d70: 6e3b ldr r3, [r7, #96] @ 0x60 8012d72: 2b00 cmp r3, #0 8012d74: d1e3 bne.n 8012d3e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012d76: 687b ldr r3, [r7, #4] 8012d78: 2220 movs r2, #32 8012d7a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8012d7e: 687b ldr r3, [r7, #4] 8012d80: 2200 movs r2, #0 8012d82: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8012d84: 687b ldr r3, [r7, #4] 8012d86: 2200 movs r2, #0 8012d88: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8012d8a: 687b ldr r3, [r7, #4] 8012d8c: 681b ldr r3, [r3, #0] 8012d8e: 4a60 ldr r2, [pc, #384] @ (8012f10 ) 8012d90: 4293 cmp r3, r2 8012d92: d021 beq.n 8012dd8 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8012d94: 687b ldr r3, [r7, #4] 8012d96: 681b ldr r3, [r3, #0] 8012d98: 685b ldr r3, [r3, #4] 8012d9a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8012d9e: 2b00 cmp r3, #0 8012da0: d01a beq.n 8012dd8 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8012da2: 687b ldr r3, [r7, #4] 8012da4: 681b ldr r3, [r3, #0] 8012da6: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012da8: 6cbb ldr r3, [r7, #72] @ 0x48 8012daa: e853 3f00 ldrex r3, [r3] 8012dae: 647b str r3, [r7, #68] @ 0x44 return(result); 8012db0: 6c7b ldr r3, [r7, #68] @ 0x44 8012db2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8012db6: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8012dba: 687b ldr r3, [r7, #4] 8012dbc: 681b ldr r3, [r3, #0] 8012dbe: 461a mov r2, r3 8012dc0: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8012dc4: 657b str r3, [r7, #84] @ 0x54 8012dc6: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dc8: 6d39 ldr r1, [r7, #80] @ 0x50 8012dca: 6d7a ldr r2, [r7, #84] @ 0x54 8012dcc: e841 2300 strex r3, r2, [r1] 8012dd0: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012dd2: 6cfb ldr r3, [r7, #76] @ 0x4c 8012dd4: 2b00 cmp r3, #0 8012dd6: d1e4 bne.n 8012da2 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012dd8: 687b ldr r3, [r7, #4] 8012dda: 6edb ldr r3, [r3, #108] @ 0x6c 8012ddc: 2b01 cmp r3, #1 8012dde: d130 bne.n 8012e42 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012de0: 687b ldr r3, [r7, #4] 8012de2: 2200 movs r2, #0 8012de4: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012de6: 687b ldr r3, [r7, #4] 8012de8: 681b ldr r3, [r3, #0] 8012dea: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012dec: 6b7b ldr r3, [r7, #52] @ 0x34 8012dee: e853 3f00 ldrex r3, [r3] 8012df2: 633b str r3, [r7, #48] @ 0x30 return(result); 8012df4: 6b3b ldr r3, [r7, #48] @ 0x30 8012df6: f023 0310 bic.w r3, r3, #16 8012dfa: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8012dfe: 687b ldr r3, [r7, #4] 8012e00: 681b ldr r3, [r3, #0] 8012e02: 461a mov r2, r3 8012e04: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8012e08: 643b str r3, [r7, #64] @ 0x40 8012e0a: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012e0c: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012e0e: 6c3a ldr r2, [r7, #64] @ 0x40 8012e10: e841 2300 strex r3, r2, [r1] 8012e14: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012e16: 6bbb ldr r3, [r7, #56] @ 0x38 8012e18: 2b00 cmp r3, #0 8012e1a: d1e4 bne.n 8012de6 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8012e1c: 687b ldr r3, [r7, #4] 8012e1e: 681b ldr r3, [r3, #0] 8012e20: 69db ldr r3, [r3, #28] 8012e22: f003 0310 and.w r3, r3, #16 8012e26: 2b10 cmp r3, #16 8012e28: d103 bne.n 8012e32 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8012e2a: 687b ldr r3, [r7, #4] 8012e2c: 681b ldr r3, [r3, #0] 8012e2e: 2210 movs r2, #16 8012e30: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8012e32: 687b ldr r3, [r7, #4] 8012e34: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8012e38: 4619 mov r1, r3 8012e3a: 6878 ldr r0, [r7, #4] 8012e3c: f7f1 fa3a bl 80042b4 8012e40: e002 b.n 8012e48 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8012e42: 6878 ldr r0, [r7, #4] 8012e44: f7f1 fa2c bl 80042a0 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012e48: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 8012e4c: 2b00 cmp r3, #0 8012e4e: d006 beq.n 8012e5e 8012e50: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012e54: f003 0320 and.w r3, r3, #32 8012e58: 2b00 cmp r3, #0 8012e5a: f47f aed1 bne.w 8012c00 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8012e5e: 687b ldr r3, [r7, #4] 8012e60: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012e64: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8012e68: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8012e6c: 2b00 cmp r3, #0 8012e6e: d049 beq.n 8012f04 8012e70: 687b ldr r3, [r7, #4] 8012e72: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012e76: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 8012e7a: 429a cmp r2, r3 8012e7c: d242 bcs.n 8012f04 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8012e7e: 687b ldr r3, [r7, #4] 8012e80: 681b ldr r3, [r3, #0] 8012e82: 3308 adds r3, #8 8012e84: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e86: 6a3b ldr r3, [r7, #32] 8012e88: e853 3f00 ldrex r3, [r3] 8012e8c: 61fb str r3, [r7, #28] return(result); 8012e8e: 69fb ldr r3, [r7, #28] 8012e90: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8012e94: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012e98: 687b ldr r3, [r7, #4] 8012e9a: 681b ldr r3, [r3, #0] 8012e9c: 3308 adds r3, #8 8012e9e: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012ea2: 62fa str r2, [r7, #44] @ 0x2c 8012ea4: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ea6: 6ab9 ldr r1, [r7, #40] @ 0x28 8012ea8: 6afa ldr r2, [r7, #44] @ 0x2c 8012eaa: e841 2300 strex r3, r2, [r1] 8012eae: 627b str r3, [r7, #36] @ 0x24 return(result); 8012eb0: 6a7b ldr r3, [r7, #36] @ 0x24 8012eb2: 2b00 cmp r3, #0 8012eb4: d1e3 bne.n 8012e7e /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8012eb6: 687b ldr r3, [r7, #4] 8012eb8: 4a16 ldr r2, [pc, #88] @ (8012f14 ) 8012eba: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012ebc: 687b ldr r3, [r7, #4] 8012ebe: 681b ldr r3, [r3, #0] 8012ec0: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012ec2: 68fb ldr r3, [r7, #12] 8012ec4: e853 3f00 ldrex r3, [r3] 8012ec8: 60bb str r3, [r7, #8] return(result); 8012eca: 68bb ldr r3, [r7, #8] 8012ecc: f043 0320 orr.w r3, r3, #32 8012ed0: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012ed4: 687b ldr r3, [r7, #4] 8012ed6: 681b ldr r3, [r3, #0] 8012ed8: 461a mov r2, r3 8012eda: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8012ede: 61bb str r3, [r7, #24] 8012ee0: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ee2: 6979 ldr r1, [r7, #20] 8012ee4: 69ba ldr r2, [r7, #24] 8012ee6: e841 2300 strex r3, r2, [r1] 8012eea: 613b str r3, [r7, #16] return(result); 8012eec: 693b ldr r3, [r7, #16] 8012eee: 2b00 cmp r3, #0 8012ef0: d1e4 bne.n 8012ebc else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8012ef2: e007 b.n 8012f04 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8012ef4: 687b ldr r3, [r7, #4] 8012ef6: 681b ldr r3, [r3, #0] 8012ef8: 699a ldr r2, [r3, #24] 8012efa: 687b ldr r3, [r7, #4] 8012efc: 681b ldr r3, [r3, #0] 8012efe: f042 0208 orr.w r2, r2, #8 8012f02: 619a str r2, [r3, #24] } 8012f04: bf00 nop 8012f06: 37b0 adds r7, #176 @ 0xb0 8012f08: 46bd mov sp, r7 8012f0a: bd80 pop {r7, pc} 8012f0c: effffffe .word 0xeffffffe 8012f10: 58000c00 .word 0x58000c00 8012f14: 08012849 .word 0x08012849 08012f18 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8012f18: b580 push {r7, lr} 8012f1a: b0ae sub sp, #184 @ 0xb8 8012f1c: af00 add r7, sp, #0 8012f1e: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8012f20: 687b ldr r3, [r7, #4] 8012f22: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8012f26: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8012f2a: 687b ldr r3, [r7, #4] 8012f2c: 681b ldr r3, [r3, #0] 8012f2e: 69db ldr r3, [r3, #28] 8012f30: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8012f34: 687b ldr r3, [r7, #4] 8012f36: 681b ldr r3, [r3, #0] 8012f38: 681b ldr r3, [r3, #0] 8012f3a: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 8012f3e: 687b ldr r3, [r7, #4] 8012f40: 681b ldr r3, [r3, #0] 8012f42: 689b ldr r3, [r3, #8] 8012f44: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8012f48: 687b ldr r3, [r7, #4] 8012f4a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8012f4e: 2b22 cmp r3, #34 @ 0x22 8012f50: f040 8184 bne.w 801325c { nb_rx_data = huart->NbRxDataToProcess; 8012f54: 687b ldr r3, [r7, #4] 8012f56: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012f5a: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8012f5e: e127 b.n 80131b0 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8012f60: 687b ldr r3, [r7, #4] 8012f62: 681b ldr r3, [r3, #0] 8012f64: 6a5b ldr r3, [r3, #36] @ 0x24 8012f66: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 8012f6a: 687b ldr r3, [r7, #4] 8012f6c: 6d9b ldr r3, [r3, #88] @ 0x58 8012f6e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 8012f72: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 8012f76: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 8012f7a: 4013 ands r3, r2 8012f7c: b29a uxth r2, r3 8012f7e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8012f82: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8012f84: 687b ldr r3, [r7, #4] 8012f86: 6d9b ldr r3, [r3, #88] @ 0x58 8012f88: 1c9a adds r2, r3, #2 8012f8a: 687b ldr r3, [r7, #4] 8012f8c: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8012f8e: 687b ldr r3, [r7, #4] 8012f90: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8012f94: b29b uxth r3, r3 8012f96: 3b01 subs r3, #1 8012f98: b29a uxth r2, r3 8012f9a: 687b ldr r3, [r7, #4] 8012f9c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8012fa0: 687b ldr r3, [r7, #4] 8012fa2: 681b ldr r3, [r3, #0] 8012fa4: 69db ldr r3, [r3, #28] 8012fa6: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8012faa: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012fae: f003 0307 and.w r3, r3, #7 8012fb2: 2b00 cmp r3, #0 8012fb4: d053 beq.n 801305e { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8012fb6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012fba: f003 0301 and.w r3, r3, #1 8012fbe: 2b00 cmp r3, #0 8012fc0: d011 beq.n 8012fe6 8012fc2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8012fc6: f403 7380 and.w r3, r3, #256 @ 0x100 8012fca: 2b00 cmp r3, #0 8012fcc: d00b beq.n 8012fe6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8012fce: 687b ldr r3, [r7, #4] 8012fd0: 681b ldr r3, [r3, #0] 8012fd2: 2201 movs r2, #1 8012fd4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8012fd6: 687b ldr r3, [r7, #4] 8012fd8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8012fdc: f043 0201 orr.w r2, r3, #1 8012fe0: 687b ldr r3, [r7, #4] 8012fe2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8012fe6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8012fea: f003 0302 and.w r3, r3, #2 8012fee: 2b00 cmp r3, #0 8012ff0: d011 beq.n 8013016 8012ff2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8012ff6: f003 0301 and.w r3, r3, #1 8012ffa: 2b00 cmp r3, #0 8012ffc: d00b beq.n 8013016 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8012ffe: 687b ldr r3, [r7, #4] 8013000: 681b ldr r3, [r3, #0] 8013002: 2202 movs r2, #2 8013004: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8013006: 687b ldr r3, [r7, #4] 8013008: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 801300c: f043 0204 orr.w r2, r3, #4 8013010: 687b ldr r3, [r7, #4] 8013012: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8013016: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 801301a: f003 0304 and.w r3, r3, #4 801301e: 2b00 cmp r3, #0 8013020: d011 beq.n 8013046 8013022: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8013026: f003 0301 and.w r3, r3, #1 801302a: 2b00 cmp r3, #0 801302c: d00b beq.n 8013046 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 801302e: 687b ldr r3, [r7, #4] 8013030: 681b ldr r3, [r3, #0] 8013032: 2204 movs r2, #4 8013034: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8013036: 687b ldr r3, [r7, #4] 8013038: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 801303c: f043 0202 orr.w r2, r3, #2 8013040: 687b ldr r3, [r7, #4] 8013042: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8013046: 687b ldr r3, [r7, #4] 8013048: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 801304c: 2b00 cmp r3, #0 801304e: d006 beq.n 801305e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013050: 6878 ldr r0, [r7, #4] 8013052: f7fe f961 bl 8011318 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013056: 687b ldr r3, [r7, #4] 8013058: 2200 movs r2, #0 801305a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 801305e: 687b ldr r3, [r7, #4] 8013060: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013064: b29b uxth r3, r3 8013066: 2b00 cmp r3, #0 8013068: f040 80a2 bne.w 80131b0 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 801306c: 687b ldr r3, [r7, #4] 801306e: 681b ldr r3, [r3, #0] 8013070: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013072: 6f7b ldr r3, [r7, #116] @ 0x74 8013074: e853 3f00 ldrex r3, [r3] 8013078: 673b str r3, [r7, #112] @ 0x70 return(result); 801307a: 6f3b ldr r3, [r7, #112] @ 0x70 801307c: f423 7380 bic.w r3, r3, #256 @ 0x100 8013080: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8013084: 687b ldr r3, [r7, #4] 8013086: 681b ldr r3, [r3, #0] 8013088: 461a mov r2, r3 801308a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 801308e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8013092: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013094: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013096: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 801309a: e841 2300 strex r3, r2, [r1] 801309e: 67bb str r3, [r7, #120] @ 0x78 return(result); 80130a0: 6fbb ldr r3, [r7, #120] @ 0x78 80130a2: 2b00 cmp r3, #0 80130a4: d1e2 bne.n 801306c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80130a6: 687b ldr r3, [r7, #4] 80130a8: 681b ldr r3, [r3, #0] 80130aa: 3308 adds r3, #8 80130ac: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80130ae: 6e3b ldr r3, [r7, #96] @ 0x60 80130b0: e853 3f00 ldrex r3, [r3] 80130b4: 65fb str r3, [r7, #92] @ 0x5c return(result); 80130b6: 6dfa ldr r2, [r7, #92] @ 0x5c 80130b8: 4b6e ldr r3, [pc, #440] @ (8013274 ) 80130ba: 4013 ands r3, r2 80130bc: f8c7 3098 str.w r3, [r7, #152] @ 0x98 80130c0: 687b ldr r3, [r7, #4] 80130c2: 681b ldr r3, [r3, #0] 80130c4: 3308 adds r3, #8 80130c6: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 80130ca: 66fa str r2, [r7, #108] @ 0x6c 80130cc: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80130ce: 6eb9 ldr r1, [r7, #104] @ 0x68 80130d0: 6efa ldr r2, [r7, #108] @ 0x6c 80130d2: e841 2300 strex r3, r2, [r1] 80130d6: 667b str r3, [r7, #100] @ 0x64 return(result); 80130d8: 6e7b ldr r3, [r7, #100] @ 0x64 80130da: 2b00 cmp r3, #0 80130dc: d1e3 bne.n 80130a6 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80130de: 687b ldr r3, [r7, #4] 80130e0: 2220 movs r2, #32 80130e2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80130e6: 687b ldr r3, [r7, #4] 80130e8: 2200 movs r2, #0 80130ea: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80130ec: 687b ldr r3, [r7, #4] 80130ee: 2200 movs r2, #0 80130f0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80130f2: 687b ldr r3, [r7, #4] 80130f4: 681b ldr r3, [r3, #0] 80130f6: 4a60 ldr r2, [pc, #384] @ (8013278 ) 80130f8: 4293 cmp r3, r2 80130fa: d021 beq.n 8013140 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80130fc: 687b ldr r3, [r7, #4] 80130fe: 681b ldr r3, [r3, #0] 8013100: 685b ldr r3, [r3, #4] 8013102: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8013106: 2b00 cmp r3, #0 8013108: d01a beq.n 8013140 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 801310a: 687b ldr r3, [r7, #4] 801310c: 681b ldr r3, [r3, #0] 801310e: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013110: 6cfb ldr r3, [r7, #76] @ 0x4c 8013112: e853 3f00 ldrex r3, [r3] 8013116: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013118: 6cbb ldr r3, [r7, #72] @ 0x48 801311a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 801311e: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013122: 687b ldr r3, [r7, #4] 8013124: 681b ldr r3, [r3, #0] 8013126: 461a mov r2, r3 8013128: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 801312c: 65bb str r3, [r7, #88] @ 0x58 801312e: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013130: 6d79 ldr r1, [r7, #84] @ 0x54 8013132: 6dba ldr r2, [r7, #88] @ 0x58 8013134: e841 2300 strex r3, r2, [r1] 8013138: 653b str r3, [r7, #80] @ 0x50 return(result); 801313a: 6d3b ldr r3, [r7, #80] @ 0x50 801313c: 2b00 cmp r3, #0 801313e: d1e4 bne.n 801310a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013140: 687b ldr r3, [r7, #4] 8013142: 6edb ldr r3, [r3, #108] @ 0x6c 8013144: 2b01 cmp r3, #1 8013146: d130 bne.n 80131aa { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013148: 687b ldr r3, [r7, #4] 801314a: 2200 movs r2, #0 801314c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801314e: 687b ldr r3, [r7, #4] 8013150: 681b ldr r3, [r3, #0] 8013152: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013154: 6bbb ldr r3, [r7, #56] @ 0x38 8013156: e853 3f00 ldrex r3, [r3] 801315a: 637b str r3, [r7, #52] @ 0x34 return(result); 801315c: 6b7b ldr r3, [r7, #52] @ 0x34 801315e: f023 0310 bic.w r3, r3, #16 8013162: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8013166: 687b ldr r3, [r7, #4] 8013168: 681b ldr r3, [r3, #0] 801316a: 461a mov r2, r3 801316c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8013170: 647b str r3, [r7, #68] @ 0x44 8013172: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013174: 6c39 ldr r1, [r7, #64] @ 0x40 8013176: 6c7a ldr r2, [r7, #68] @ 0x44 8013178: e841 2300 strex r3, r2, [r1] 801317c: 63fb str r3, [r7, #60] @ 0x3c return(result); 801317e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013180: 2b00 cmp r3, #0 8013182: d1e4 bne.n 801314e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013184: 687b ldr r3, [r7, #4] 8013186: 681b ldr r3, [r3, #0] 8013188: 69db ldr r3, [r3, #28] 801318a: f003 0310 and.w r3, r3, #16 801318e: 2b10 cmp r3, #16 8013190: d103 bne.n 801319a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013192: 687b ldr r3, [r7, #4] 8013194: 681b ldr r3, [r3, #0] 8013196: 2210 movs r2, #16 8013198: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 801319a: 687b ldr r3, [r7, #4] 801319c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80131a0: 4619 mov r1, r3 80131a2: 6878 ldr r0, [r7, #4] 80131a4: f7f1 f886 bl 80042b4 80131a8: e002 b.n 80131b0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 80131aa: 6878 ldr r0, [r7, #4] 80131ac: f7f1 f878 bl 80042a0 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80131b0: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 80131b4: 2b00 cmp r3, #0 80131b6: d006 beq.n 80131c6 80131b8: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80131bc: f003 0320 and.w r3, r3, #32 80131c0: 2b00 cmp r3, #0 80131c2: f47f aecd bne.w 8012f60 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 80131c6: 687b ldr r3, [r7, #4] 80131c8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80131cc: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 80131d0: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 80131d4: 2b00 cmp r3, #0 80131d6: d049 beq.n 801326c 80131d8: 687b ldr r3, [r7, #4] 80131da: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80131de: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 80131e2: 429a cmp r2, r3 80131e4: d242 bcs.n 801326c { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 80131e6: 687b ldr r3, [r7, #4] 80131e8: 681b ldr r3, [r3, #0] 80131ea: 3308 adds r3, #8 80131ec: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131ee: 6a7b ldr r3, [r7, #36] @ 0x24 80131f0: e853 3f00 ldrex r3, [r3] 80131f4: 623b str r3, [r7, #32] return(result); 80131f6: 6a3b ldr r3, [r7, #32] 80131f8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80131fc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8013200: 687b ldr r3, [r7, #4] 8013202: 681b ldr r3, [r3, #0] 8013204: 3308 adds r3, #8 8013206: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 801320a: 633a str r2, [r7, #48] @ 0x30 801320c: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801320e: 6af9 ldr r1, [r7, #44] @ 0x2c 8013210: 6b3a ldr r2, [r7, #48] @ 0x30 8013212: e841 2300 strex r3, r2, [r1] 8013216: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013218: 6abb ldr r3, [r7, #40] @ 0x28 801321a: 2b00 cmp r3, #0 801321c: d1e3 bne.n 80131e6 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 801321e: 687b ldr r3, [r7, #4] 8013220: 4a16 ldr r2, [pc, #88] @ (801327c ) 8013222: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8013224: 687b ldr r3, [r7, #4] 8013226: 681b ldr r3, [r3, #0] 8013228: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801322a: 693b ldr r3, [r7, #16] 801322c: e853 3f00 ldrex r3, [r3] 8013230: 60fb str r3, [r7, #12] return(result); 8013232: 68fb ldr r3, [r7, #12] 8013234: f043 0320 orr.w r3, r3, #32 8013238: f8c7 3084 str.w r3, [r7, #132] @ 0x84 801323c: 687b ldr r3, [r7, #4] 801323e: 681b ldr r3, [r3, #0] 8013240: 461a mov r2, r3 8013242: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013246: 61fb str r3, [r7, #28] 8013248: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801324a: 69b9 ldr r1, [r7, #24] 801324c: 69fa ldr r2, [r7, #28] 801324e: e841 2300 strex r3, r2, [r1] 8013252: 617b str r3, [r7, #20] return(result); 8013254: 697b ldr r3, [r7, #20] 8013256: 2b00 cmp r3, #0 8013258: d1e4 bne.n 8013224 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 801325a: e007 b.n 801326c __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 801325c: 687b ldr r3, [r7, #4] 801325e: 681b ldr r3, [r3, #0] 8013260: 699a ldr r2, [r3, #24] 8013262: 687b ldr r3, [r7, #4] 8013264: 681b ldr r3, [r3, #0] 8013266: f042 0208 orr.w r2, r2, #8 801326a: 619a str r2, [r3, #24] } 801326c: bf00 nop 801326e: 37b8 adds r7, #184 @ 0xb8 8013270: 46bd mov sp, r7 8013272: bd80 pop {r7, pc} 8013274: effffffe .word 0xeffffffe 8013278: 58000c00 .word 0x58000c00 801327c: 08012a01 .word 0x08012a01 08013280 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8013280: b480 push {r7} 8013282: b083 sub sp, #12 8013284: af00 add r7, sp, #0 8013286: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8013288: bf00 nop 801328a: 370c adds r7, #12 801328c: 46bd mov sp, r7 801328e: f85d 7b04 ldr.w r7, [sp], #4 8013292: 4770 bx lr 08013294 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8013294: b480 push {r7} 8013296: b083 sub sp, #12 8013298: af00 add r7, sp, #0 801329a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 801329c: bf00 nop 801329e: 370c adds r7, #12 80132a0: 46bd mov sp, r7 80132a2: f85d 7b04 ldr.w r7, [sp], #4 80132a6: 4770 bx lr 080132a8 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 80132a8: b480 push {r7} 80132aa: b083 sub sp, #12 80132ac: af00 add r7, sp, #0 80132ae: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 80132b0: bf00 nop 80132b2: 370c adds r7, #12 80132b4: 46bd mov sp, r7 80132b6: f85d 7b04 ldr.w r7, [sp], #4 80132ba: 4770 bx lr 080132bc : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 80132bc: b480 push {r7} 80132be: b085 sub sp, #20 80132c0: af00 add r7, sp, #0 80132c2: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 80132c4: 687b ldr r3, [r7, #4] 80132c6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 80132ca: 2b01 cmp r3, #1 80132cc: d101 bne.n 80132d2 80132ce: 2302 movs r3, #2 80132d0: e027 b.n 8013322 80132d2: 687b ldr r3, [r7, #4] 80132d4: 2201 movs r2, #1 80132d6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 80132da: 687b ldr r3, [r7, #4] 80132dc: 2224 movs r2, #36 @ 0x24 80132de: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80132e2: 687b ldr r3, [r7, #4] 80132e4: 681b ldr r3, [r3, #0] 80132e6: 681b ldr r3, [r3, #0] 80132e8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80132ea: 687b ldr r3, [r7, #4] 80132ec: 681b ldr r3, [r3, #0] 80132ee: 681a ldr r2, [r3, #0] 80132f0: 687b ldr r3, [r7, #4] 80132f2: 681b ldr r3, [r3, #0] 80132f4: f022 0201 bic.w r2, r2, #1 80132f8: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 80132fa: 68fb ldr r3, [r7, #12] 80132fc: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8013300: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8013302: 687b ldr r3, [r7, #4] 8013304: 2200 movs r2, #0 8013306: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013308: 687b ldr r3, [r7, #4] 801330a: 681b ldr r3, [r3, #0] 801330c: 68fa ldr r2, [r7, #12] 801330e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013310: 687b ldr r3, [r7, #4] 8013312: 2220 movs r2, #32 8013314: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013318: 687b ldr r3, [r7, #4] 801331a: 2200 movs r2, #0 801331c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013320: 2300 movs r3, #0 } 8013322: 4618 mov r0, r3 8013324: 3714 adds r7, #20 8013326: 46bd mov sp, r7 8013328: f85d 7b04 ldr.w r7, [sp], #4 801332c: 4770 bx lr 0801332e : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 801332e: b580 push {r7, lr} 8013330: b084 sub sp, #16 8013332: af00 add r7, sp, #0 8013334: 6078 str r0, [r7, #4] 8013336: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013338: 687b ldr r3, [r7, #4] 801333a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 801333e: 2b01 cmp r3, #1 8013340: d101 bne.n 8013346 8013342: 2302 movs r3, #2 8013344: e02d b.n 80133a2 8013346: 687b ldr r3, [r7, #4] 8013348: 2201 movs r2, #1 801334a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 801334e: 687b ldr r3, [r7, #4] 8013350: 2224 movs r2, #36 @ 0x24 8013352: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013356: 687b ldr r3, [r7, #4] 8013358: 681b ldr r3, [r3, #0] 801335a: 681b ldr r3, [r3, #0] 801335c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 801335e: 687b ldr r3, [r7, #4] 8013360: 681b ldr r3, [r3, #0] 8013362: 681a ldr r2, [r3, #0] 8013364: 687b ldr r3, [r7, #4] 8013366: 681b ldr r3, [r3, #0] 8013368: f022 0201 bic.w r2, r2, #1 801336c: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 801336e: 687b ldr r3, [r7, #4] 8013370: 681b ldr r3, [r3, #0] 8013372: 689b ldr r3, [r3, #8] 8013374: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8013378: 687b ldr r3, [r7, #4] 801337a: 681b ldr r3, [r3, #0] 801337c: 683a ldr r2, [r7, #0] 801337e: 430a orrs r2, r1 8013380: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013382: 6878 ldr r0, [r7, #4] 8013384: f000 f8a0 bl 80134c8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013388: 687b ldr r3, [r7, #4] 801338a: 681b ldr r3, [r3, #0] 801338c: 68fa ldr r2, [r7, #12] 801338e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013390: 687b ldr r3, [r7, #4] 8013392: 2220 movs r2, #32 8013394: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013398: 687b ldr r3, [r7, #4] 801339a: 2200 movs r2, #0 801339c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 80133a0: 2300 movs r3, #0 } 80133a2: 4618 mov r0, r3 80133a4: 3710 adds r7, #16 80133a6: 46bd mov sp, r7 80133a8: bd80 pop {r7, pc} 080133aa : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 80133aa: b580 push {r7, lr} 80133ac: b084 sub sp, #16 80133ae: af00 add r7, sp, #0 80133b0: 6078 str r0, [r7, #4] 80133b2: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 80133b4: 687b ldr r3, [r7, #4] 80133b6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 80133ba: 2b01 cmp r3, #1 80133bc: d101 bne.n 80133c2 80133be: 2302 movs r3, #2 80133c0: e02d b.n 801341e 80133c2: 687b ldr r3, [r7, #4] 80133c4: 2201 movs r2, #1 80133c6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 80133ca: 687b ldr r3, [r7, #4] 80133cc: 2224 movs r2, #36 @ 0x24 80133ce: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80133d2: 687b ldr r3, [r7, #4] 80133d4: 681b ldr r3, [r3, #0] 80133d6: 681b ldr r3, [r3, #0] 80133d8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80133da: 687b ldr r3, [r7, #4] 80133dc: 681b ldr r3, [r3, #0] 80133de: 681a ldr r2, [r3, #0] 80133e0: 687b ldr r3, [r7, #4] 80133e2: 681b ldr r3, [r3, #0] 80133e4: f022 0201 bic.w r2, r2, #1 80133e8: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 80133ea: 687b ldr r3, [r7, #4] 80133ec: 681b ldr r3, [r3, #0] 80133ee: 689b ldr r3, [r3, #8] 80133f0: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 80133f4: 687b ldr r3, [r7, #4] 80133f6: 681b ldr r3, [r3, #0] 80133f8: 683a ldr r2, [r7, #0] 80133fa: 430a orrs r2, r1 80133fc: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 80133fe: 6878 ldr r0, [r7, #4] 8013400: f000 f862 bl 80134c8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013404: 687b ldr r3, [r7, #4] 8013406: 681b ldr r3, [r3, #0] 8013408: 68fa ldr r2, [r7, #12] 801340a: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 801340c: 687b ldr r3, [r7, #4] 801340e: 2220 movs r2, #32 8013410: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013414: 687b ldr r3, [r7, #4] 8013416: 2200 movs r2, #0 8013418: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 801341c: 2300 movs r3, #0 } 801341e: 4618 mov r0, r3 8013420: 3710 adds r7, #16 8013422: 46bd mov sp, r7 8013424: bd80 pop {r7, pc} 08013426 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013426: b580 push {r7, lr} 8013428: b08c sub sp, #48 @ 0x30 801342a: af00 add r7, sp, #0 801342c: 60f8 str r0, [r7, #12] 801342e: 60b9 str r1, [r7, #8] 8013430: 4613 mov r3, r2 8013432: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 8013434: 2300 movs r3, #0 8013436: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 801343a: 68fb ldr r3, [r7, #12] 801343c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013440: 2b20 cmp r3, #32 8013442: d13b bne.n 80134bc { if ((pData == NULL) || (Size == 0U)) 8013444: 68bb ldr r3, [r7, #8] 8013446: 2b00 cmp r3, #0 8013448: d002 beq.n 8013450 801344a: 88fb ldrh r3, [r7, #6] 801344c: 2b00 cmp r3, #0 801344e: d101 bne.n 8013454 { return HAL_ERROR; 8013450: 2301 movs r3, #1 8013452: e034 b.n 80134be } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013454: 68fb ldr r3, [r7, #12] 8013456: 2201 movs r2, #1 8013458: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 801345a: 68fb ldr r3, [r7, #12] 801345c: 2200 movs r2, #0 801345e: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 8013460: 88fb ldrh r3, [r7, #6] 8013462: 461a mov r2, r3 8013464: 68b9 ldr r1, [r7, #8] 8013466: 68f8 ldr r0, [r7, #12] 8013468: f7fe fe82 bl 8012170 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801346c: 68fb ldr r3, [r7, #12] 801346e: 6edb ldr r3, [r3, #108] @ 0x6c 8013470: 2b01 cmp r3, #1 8013472: d11d bne.n 80134b0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013474: 68fb ldr r3, [r7, #12] 8013476: 681b ldr r3, [r3, #0] 8013478: 2210 movs r2, #16 801347a: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801347c: 68fb ldr r3, [r7, #12] 801347e: 681b ldr r3, [r3, #0] 8013480: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013482: 69bb ldr r3, [r7, #24] 8013484: e853 3f00 ldrex r3, [r3] 8013488: 617b str r3, [r7, #20] return(result); 801348a: 697b ldr r3, [r7, #20] 801348c: f043 0310 orr.w r3, r3, #16 8013490: 62bb str r3, [r7, #40] @ 0x28 8013492: 68fb ldr r3, [r7, #12] 8013494: 681b ldr r3, [r3, #0] 8013496: 461a mov r2, r3 8013498: 6abb ldr r3, [r7, #40] @ 0x28 801349a: 627b str r3, [r7, #36] @ 0x24 801349c: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801349e: 6a39 ldr r1, [r7, #32] 80134a0: 6a7a ldr r2, [r7, #36] @ 0x24 80134a2: e841 2300 strex r3, r2, [r1] 80134a6: 61fb str r3, [r7, #28] return(result); 80134a8: 69fb ldr r3, [r7, #28] 80134aa: 2b00 cmp r3, #0 80134ac: d1e6 bne.n 801347c 80134ae: e002 b.n 80134b6 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 80134b0: 2301 movs r3, #1 80134b2: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 80134b6: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 80134ba: e000 b.n 80134be } else { return HAL_BUSY; 80134bc: 2302 movs r3, #2 } } 80134be: 4618 mov r0, r3 80134c0: 3730 adds r7, #48 @ 0x30 80134c2: 46bd mov sp, r7 80134c4: bd80 pop {r7, pc} ... 080134c8 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 80134c8: b480 push {r7} 80134ca: b085 sub sp, #20 80134cc: af00 add r7, sp, #0 80134ce: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 80134d0: 687b ldr r3, [r7, #4] 80134d2: 6e5b ldr r3, [r3, #100] @ 0x64 80134d4: 2b00 cmp r3, #0 80134d6: d108 bne.n 80134ea { huart->NbTxDataToProcess = 1U; 80134d8: 687b ldr r3, [r7, #4] 80134da: 2201 movs r2, #1 80134dc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 80134e0: 687b ldr r3, [r7, #4] 80134e2: 2201 movs r2, #1 80134e4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 80134e8: e031 b.n 801354e rx_fifo_depth = RX_FIFO_DEPTH; 80134ea: 2310 movs r3, #16 80134ec: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 80134ee: 2310 movs r3, #16 80134f0: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 80134f2: 687b ldr r3, [r7, #4] 80134f4: 681b ldr r3, [r3, #0] 80134f6: 689b ldr r3, [r3, #8] 80134f8: 0e5b lsrs r3, r3, #25 80134fa: b2db uxtb r3, r3 80134fc: f003 0307 and.w r3, r3, #7 8013500: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8013502: 687b ldr r3, [r7, #4] 8013504: 681b ldr r3, [r3, #0] 8013506: 689b ldr r3, [r3, #8] 8013508: 0f5b lsrs r3, r3, #29 801350a: b2db uxtb r3, r3 801350c: f003 0307 and.w r3, r3, #7 8013510: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013512: 7bbb ldrb r3, [r7, #14] 8013514: 7b3a ldrb r2, [r7, #12] 8013516: 4911 ldr r1, [pc, #68] @ (801355c ) 8013518: 5c8a ldrb r2, [r1, r2] 801351a: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 801351e: 7b3a ldrb r2, [r7, #12] 8013520: 490f ldr r1, [pc, #60] @ (8013560 ) 8013522: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013524: fb93 f3f2 sdiv r3, r3, r2 8013528: b29a uxth r2, r3 801352a: 687b ldr r3, [r7, #4] 801352c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013530: 7bfb ldrb r3, [r7, #15] 8013532: 7b7a ldrb r2, [r7, #13] 8013534: 4909 ldr r1, [pc, #36] @ (801355c ) 8013536: 5c8a ldrb r2, [r1, r2] 8013538: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 801353c: 7b7a ldrb r2, [r7, #13] 801353e: 4908 ldr r1, [pc, #32] @ (8013560 ) 8013540: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013542: fb93 f3f2 sdiv r3, r3, r2 8013546: b29a uxth r2, r3 8013548: 687b ldr r3, [r7, #4] 801354a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 801354e: bf00 nop 8013550: 3714 adds r7, #20 8013552: 46bd mov sp, r7 8013554: f85d 7b04 ldr.w r7, [sp], #4 8013558: 4770 bx lr 801355a: bf00 nop 801355c: 080189f8 .word 0x080189f8 8013560: 08018a00 .word 0x08018a00 08013564 <__NVIC_SetPriority>: { 8013564: b480 push {r7} 8013566: b083 sub sp, #12 8013568: af00 add r7, sp, #0 801356a: 4603 mov r3, r0 801356c: 6039 str r1, [r7, #0] 801356e: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8013570: f9b7 3006 ldrsh.w r3, [r7, #6] 8013574: 2b00 cmp r3, #0 8013576: db0a blt.n 801358e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013578: 683b ldr r3, [r7, #0] 801357a: b2da uxtb r2, r3 801357c: 490c ldr r1, [pc, #48] @ (80135b0 <__NVIC_SetPriority+0x4c>) 801357e: f9b7 3006 ldrsh.w r3, [r7, #6] 8013582: 0112 lsls r2, r2, #4 8013584: b2d2 uxtb r2, r2 8013586: 440b add r3, r1 8013588: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 801358c: e00a b.n 80135a4 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 801358e: 683b ldr r3, [r7, #0] 8013590: b2da uxtb r2, r3 8013592: 4908 ldr r1, [pc, #32] @ (80135b4 <__NVIC_SetPriority+0x50>) 8013594: 88fb ldrh r3, [r7, #6] 8013596: f003 030f and.w r3, r3, #15 801359a: 3b04 subs r3, #4 801359c: 0112 lsls r2, r2, #4 801359e: b2d2 uxtb r2, r2 80135a0: 440b add r3, r1 80135a2: 761a strb r2, [r3, #24] } 80135a4: bf00 nop 80135a6: 370c adds r7, #12 80135a8: 46bd mov sp, r7 80135aa: f85d 7b04 ldr.w r7, [sp], #4 80135ae: 4770 bx lr 80135b0: e000e100 .word 0xe000e100 80135b4: e000ed00 .word 0xe000ed00 080135b8 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 80135b8: b580 push {r7, lr} 80135ba: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 80135bc: 4b05 ldr r3, [pc, #20] @ (80135d4 ) 80135be: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 80135c0: f002 fd1e bl 8016000 80135c4: 4603 mov r3, r0 80135c6: 2b01 cmp r3, #1 80135c8: d001 beq.n 80135ce /* Call tick handler */ xPortSysTickHandler(); 80135ca: f003 ff2d bl 8017428 } } 80135ce: bf00 nop 80135d0: bd80 pop {r7, pc} 80135d2: bf00 nop 80135d4: e000e010 .word 0xe000e010 080135d8 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 80135d8: b580 push {r7, lr} 80135da: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 80135dc: 2100 movs r1, #0 80135de: f06f 0004 mvn.w r0, #4 80135e2: f7ff ffbf bl 8013564 <__NVIC_SetPriority> #endif } 80135e6: bf00 nop 80135e8: bd80 pop {r7, pc} ... 080135ec : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 80135ec: b480 push {r7} 80135ee: b083 sub sp, #12 80135f0: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80135f2: f3ef 8305 mrs r3, IPSR 80135f6: 603b str r3, [r7, #0] return(result); 80135f8: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 80135fa: 2b00 cmp r3, #0 80135fc: d003 beq.n 8013606 stat = osErrorISR; 80135fe: f06f 0305 mvn.w r3, #5 8013602: 607b str r3, [r7, #4] 8013604: e00c b.n 8013620 } else { if (KernelState == osKernelInactive) { 8013606: 4b0a ldr r3, [pc, #40] @ (8013630 ) 8013608: 681b ldr r3, [r3, #0] 801360a: 2b00 cmp r3, #0 801360c: d105 bne.n 801361a EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 801360e: 4b08 ldr r3, [pc, #32] @ (8013630 ) 8013610: 2201 movs r2, #1 8013612: 601a str r2, [r3, #0] stat = osOK; 8013614: 2300 movs r3, #0 8013616: 607b str r3, [r7, #4] 8013618: e002 b.n 8013620 } else { stat = osError; 801361a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801361e: 607b str r3, [r7, #4] } } return (stat); 8013620: 687b ldr r3, [r7, #4] } 8013622: 4618 mov r0, r3 8013624: 370c adds r7, #12 8013626: 46bd mov sp, r7 8013628: f85d 7b04 ldr.w r7, [sp], #4 801362c: 4770 bx lr 801362e: bf00 nop 8013630: 24000cac .word 0x24000cac 08013634 : } return (state); } osStatus_t osKernelStart (void) { 8013634: b580 push {r7, lr} 8013636: b082 sub sp, #8 8013638: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801363a: f3ef 8305 mrs r3, IPSR 801363e: 603b str r3, [r7, #0] return(result); 8013640: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8013642: 2b00 cmp r3, #0 8013644: d003 beq.n 801364e stat = osErrorISR; 8013646: f06f 0305 mvn.w r3, #5 801364a: 607b str r3, [r7, #4] 801364c: e010 b.n 8013670 } else { if (KernelState == osKernelReady) { 801364e: 4b0b ldr r3, [pc, #44] @ (801367c ) 8013650: 681b ldr r3, [r3, #0] 8013652: 2b01 cmp r3, #1 8013654: d109 bne.n 801366a /* Ensure SVC priority is at the reset value */ SVC_Setup(); 8013656: f7ff ffbf bl 80135d8 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 801365a: 4b08 ldr r3, [pc, #32] @ (801367c ) 801365c: 2202 movs r2, #2 801365e: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 8013660: f002 f824 bl 80156ac stat = osOK; 8013664: 2300 movs r3, #0 8013666: 607b str r3, [r7, #4] 8013668: e002 b.n 8013670 } else { stat = osError; 801366a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801366e: 607b str r3, [r7, #4] } } return (stat); 8013670: 687b ldr r3, [r7, #4] } 8013672: 4618 mov r0, r3 8013674: 3708 adds r7, #8 8013676: 46bd mov sp, r7 8013678: bd80 pop {r7, pc} 801367a: bf00 nop 801367c: 24000cac .word 0x24000cac 08013680 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 8013680: b580 push {r7, lr} 8013682: b08e sub sp, #56 @ 0x38 8013684: af04 add r7, sp, #16 8013686: 60f8 str r0, [r7, #12] 8013688: 60b9 str r1, [r7, #8] 801368a: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 801368c: 2300 movs r3, #0 801368e: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013690: f3ef 8305 mrs r3, IPSR 8013694: 617b str r3, [r7, #20] return(result); 8013696: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 8013698: 2b00 cmp r3, #0 801369a: d17f bne.n 801379c 801369c: 68fb ldr r3, [r7, #12] 801369e: 2b00 cmp r3, #0 80136a0: d07c beq.n 801379c stack = configMINIMAL_STACK_SIZE; 80136a2: f44f 7300 mov.w r3, #512 @ 0x200 80136a6: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 80136a8: 2318 movs r3, #24 80136aa: 61fb str r3, [r7, #28] name = NULL; 80136ac: 2300 movs r3, #0 80136ae: 627b str r3, [r7, #36] @ 0x24 mem = -1; 80136b0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80136b4: 61bb str r3, [r7, #24] if (attr != NULL) { 80136b6: 687b ldr r3, [r7, #4] 80136b8: 2b00 cmp r3, #0 80136ba: d045 beq.n 8013748 if (attr->name != NULL) { 80136bc: 687b ldr r3, [r7, #4] 80136be: 681b ldr r3, [r3, #0] 80136c0: 2b00 cmp r3, #0 80136c2: d002 beq.n 80136ca name = attr->name; 80136c4: 687b ldr r3, [r7, #4] 80136c6: 681b ldr r3, [r3, #0] 80136c8: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 80136ca: 687b ldr r3, [r7, #4] 80136cc: 699b ldr r3, [r3, #24] 80136ce: 2b00 cmp r3, #0 80136d0: d002 beq.n 80136d8 prio = (UBaseType_t)attr->priority; 80136d2: 687b ldr r3, [r7, #4] 80136d4: 699b ldr r3, [r3, #24] 80136d6: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 80136d8: 69fb ldr r3, [r7, #28] 80136da: 2b00 cmp r3, #0 80136dc: d008 beq.n 80136f0 80136de: 69fb ldr r3, [r7, #28] 80136e0: 2b38 cmp r3, #56 @ 0x38 80136e2: d805 bhi.n 80136f0 80136e4: 687b ldr r3, [r7, #4] 80136e6: 685b ldr r3, [r3, #4] 80136e8: f003 0301 and.w r3, r3, #1 80136ec: 2b00 cmp r3, #0 80136ee: d001 beq.n 80136f4 return (NULL); 80136f0: 2300 movs r3, #0 80136f2: e054 b.n 801379e } if (attr->stack_size > 0U) { 80136f4: 687b ldr r3, [r7, #4] 80136f6: 695b ldr r3, [r3, #20] 80136f8: 2b00 cmp r3, #0 80136fa: d003 beq.n 8013704 /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 80136fc: 687b ldr r3, [r7, #4] 80136fe: 695b ldr r3, [r3, #20] 8013700: 089b lsrs r3, r3, #2 8013702: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 8013704: 687b ldr r3, [r7, #4] 8013706: 689b ldr r3, [r3, #8] 8013708: 2b00 cmp r3, #0 801370a: d00e beq.n 801372a 801370c: 687b ldr r3, [r7, #4] 801370e: 68db ldr r3, [r3, #12] 8013710: 2ba7 cmp r3, #167 @ 0xa7 8013712: d90a bls.n 801372a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 8013714: 687b ldr r3, [r7, #4] 8013716: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 8013718: 2b00 cmp r3, #0 801371a: d006 beq.n 801372a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 801371c: 687b ldr r3, [r7, #4] 801371e: 695b ldr r3, [r3, #20] 8013720: 2b00 cmp r3, #0 8013722: d002 beq.n 801372a mem = 1; 8013724: 2301 movs r3, #1 8013726: 61bb str r3, [r7, #24] 8013728: e010 b.n 801374c } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 801372a: 687b ldr r3, [r7, #4] 801372c: 689b ldr r3, [r3, #8] 801372e: 2b00 cmp r3, #0 8013730: d10c bne.n 801374c 8013732: 687b ldr r3, [r7, #4] 8013734: 68db ldr r3, [r3, #12] 8013736: 2b00 cmp r3, #0 8013738: d108 bne.n 801374c 801373a: 687b ldr r3, [r7, #4] 801373c: 691b ldr r3, [r3, #16] 801373e: 2b00 cmp r3, #0 8013740: d104 bne.n 801374c mem = 0; 8013742: 2300 movs r3, #0 8013744: 61bb str r3, [r7, #24] 8013746: e001 b.n 801374c } } } else { mem = 0; 8013748: 2300 movs r3, #0 801374a: 61bb str r3, [r7, #24] } if (mem == 1) { 801374c: 69bb ldr r3, [r7, #24] 801374e: 2b01 cmp r3, #1 8013750: d110 bne.n 8013774 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8013752: 687b ldr r3, [r7, #4] 8013754: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 8013756: 687a ldr r2, [r7, #4] 8013758: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 801375a: 9202 str r2, [sp, #8] 801375c: 9301 str r3, [sp, #4] 801375e: 69fb ldr r3, [r7, #28] 8013760: 9300 str r3, [sp, #0] 8013762: 68bb ldr r3, [r7, #8] 8013764: 6a3a ldr r2, [r7, #32] 8013766: 6a79 ldr r1, [r7, #36] @ 0x24 8013768: 68f8 ldr r0, [r7, #12] 801376a: f001 fdac bl 80152c6 801376e: 4603 mov r3, r0 8013770: 613b str r3, [r7, #16] 8013772: e013 b.n 801379c #endif } else { if (mem == 0) { 8013774: 69bb ldr r3, [r7, #24] 8013776: 2b00 cmp r3, #0 8013778: d110 bne.n 801379c #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 801377a: 6a3b ldr r3, [r7, #32] 801377c: b29a uxth r2, r3 801377e: f107 0310 add.w r3, r7, #16 8013782: 9301 str r3, [sp, #4] 8013784: 69fb ldr r3, [r7, #28] 8013786: 9300 str r3, [sp, #0] 8013788: 68bb ldr r3, [r7, #8] 801378a: 6a79 ldr r1, [r7, #36] @ 0x24 801378c: 68f8 ldr r0, [r7, #12] 801378e: f001 fdfa bl 8015386 8013792: 4603 mov r3, r0 8013794: 2b01 cmp r3, #1 8013796: d001 beq.n 801379c hTask = NULL; 8013798: 2300 movs r3, #0 801379a: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 801379c: 693b ldr r3, [r7, #16] } 801379e: 4618 mov r0, r3 80137a0: 3728 adds r7, #40 @ 0x28 80137a2: 46bd mov sp, r7 80137a4: bd80 pop {r7, pc} 080137a6 : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 80137a6: b580 push {r7, lr} 80137a8: b084 sub sp, #16 80137aa: af00 add r7, sp, #0 80137ac: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80137ae: f3ef 8305 mrs r3, IPSR 80137b2: 60bb str r3, [r7, #8] return(result); 80137b4: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 80137b6: 2b00 cmp r3, #0 80137b8: d003 beq.n 80137c2 stat = osErrorISR; 80137ba: f06f 0305 mvn.w r3, #5 80137be: 60fb str r3, [r7, #12] 80137c0: e007 b.n 80137d2 } else { stat = osOK; 80137c2: 2300 movs r3, #0 80137c4: 60fb str r3, [r7, #12] if (ticks != 0U) { 80137c6: 687b ldr r3, [r7, #4] 80137c8: 2b00 cmp r3, #0 80137ca: d002 beq.n 80137d2 vTaskDelay(ticks); 80137cc: 6878 ldr r0, [r7, #4] 80137ce: f001 ff37 bl 8015640 } } return (stat); 80137d2: 68fb ldr r3, [r7, #12] } 80137d4: 4618 mov r0, r3 80137d6: 3710 adds r7, #16 80137d8: 46bd mov sp, r7 80137da: bd80 pop {r7, pc} 080137dc : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 80137dc: b580 push {r7, lr} 80137de: b084 sub sp, #16 80137e0: af00 add r7, sp, #0 80137e2: 6078 str r0, [r7, #4] TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 80137e4: 6878 ldr r0, [r7, #4] 80137e6: f003 fc3d bl 8017064 80137ea: 60f8 str r0, [r7, #12] if (callb != NULL) { 80137ec: 68fb ldr r3, [r7, #12] 80137ee: 2b00 cmp r3, #0 80137f0: d005 beq.n 80137fe callb->func (callb->arg); 80137f2: 68fb ldr r3, [r7, #12] 80137f4: 681b ldr r3, [r3, #0] 80137f6: 68fa ldr r2, [r7, #12] 80137f8: 6852 ldr r2, [r2, #4] 80137fa: 4610 mov r0, r2 80137fc: 4798 blx r3 } } 80137fe: bf00 nop 8013800: 3710 adds r7, #16 8013802: 46bd mov sp, r7 8013804: bd80 pop {r7, pc} ... 08013808 : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 8013808: b580 push {r7, lr} 801380a: b08c sub sp, #48 @ 0x30 801380c: af02 add r7, sp, #8 801380e: 60f8 str r0, [r7, #12] 8013810: 607a str r2, [r7, #4] 8013812: 603b str r3, [r7, #0] 8013814: 460b mov r3, r1 8013816: 72fb strb r3, [r7, #11] TimerHandle_t hTimer; TimerCallback_t *callb; UBaseType_t reload; int32_t mem; hTimer = NULL; 8013818: 2300 movs r3, #0 801381a: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801381c: f3ef 8305 mrs r3, IPSR 8013820: 613b str r3, [r7, #16] return(result); 8013822: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (func != NULL)) { 8013824: 2b00 cmp r3, #0 8013826: d163 bne.n 80138f0 8013828: 68fb ldr r3, [r7, #12] 801382a: 2b00 cmp r3, #0 801382c: d060 beq.n 80138f0 /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 801382e: 2008 movs r0, #8 8013830: f003 fe8c bl 801754c 8013834: 6178 str r0, [r7, #20] if (callb != NULL) { 8013836: 697b ldr r3, [r7, #20] 8013838: 2b00 cmp r3, #0 801383a: d059 beq.n 80138f0 callb->func = func; 801383c: 697b ldr r3, [r7, #20] 801383e: 68fa ldr r2, [r7, #12] 8013840: 601a str r2, [r3, #0] callb->arg = argument; 8013842: 697b ldr r3, [r7, #20] 8013844: 687a ldr r2, [r7, #4] 8013846: 605a str r2, [r3, #4] if (type == osTimerOnce) { 8013848: 7afb ldrb r3, [r7, #11] 801384a: 2b00 cmp r3, #0 801384c: d102 bne.n 8013854 reload = pdFALSE; 801384e: 2300 movs r3, #0 8013850: 61fb str r3, [r7, #28] 8013852: e001 b.n 8013858 } else { reload = pdTRUE; 8013854: 2301 movs r3, #1 8013856: 61fb str r3, [r7, #28] } mem = -1; 8013858: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801385c: 61bb str r3, [r7, #24] name = NULL; 801385e: 2300 movs r3, #0 8013860: 627b str r3, [r7, #36] @ 0x24 if (attr != NULL) { 8013862: 683b ldr r3, [r7, #0] 8013864: 2b00 cmp r3, #0 8013866: d01c beq.n 80138a2 if (attr->name != NULL) { 8013868: 683b ldr r3, [r7, #0] 801386a: 681b ldr r3, [r3, #0] 801386c: 2b00 cmp r3, #0 801386e: d002 beq.n 8013876 name = attr->name; 8013870: 683b ldr r3, [r7, #0] 8013872: 681b ldr r3, [r3, #0] 8013874: 627b str r3, [r7, #36] @ 0x24 } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 8013876: 683b ldr r3, [r7, #0] 8013878: 689b ldr r3, [r3, #8] 801387a: 2b00 cmp r3, #0 801387c: d006 beq.n 801388c 801387e: 683b ldr r3, [r7, #0] 8013880: 68db ldr r3, [r3, #12] 8013882: 2b2b cmp r3, #43 @ 0x2b 8013884: d902 bls.n 801388c mem = 1; 8013886: 2301 movs r3, #1 8013888: 61bb str r3, [r7, #24] 801388a: e00c b.n 80138a6 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 801388c: 683b ldr r3, [r7, #0] 801388e: 689b ldr r3, [r3, #8] 8013890: 2b00 cmp r3, #0 8013892: d108 bne.n 80138a6 8013894: 683b ldr r3, [r7, #0] 8013896: 68db ldr r3, [r3, #12] 8013898: 2b00 cmp r3, #0 801389a: d104 bne.n 80138a6 mem = 0; 801389c: 2300 movs r3, #0 801389e: 61bb str r3, [r7, #24] 80138a0: e001 b.n 80138a6 } } } else { mem = 0; 80138a2: 2300 movs r3, #0 80138a4: 61bb str r3, [r7, #24] } if (mem == 1) { 80138a6: 69bb ldr r3, [r7, #24] 80138a8: 2b01 cmp r3, #1 80138aa: d10c bne.n 80138c6 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 80138ac: 683b ldr r3, [r7, #0] 80138ae: 689b ldr r3, [r3, #8] 80138b0: 9301 str r3, [sp, #4] 80138b2: 4b12 ldr r3, [pc, #72] @ (80138fc ) 80138b4: 9300 str r3, [sp, #0] 80138b6: 697b ldr r3, [r7, #20] 80138b8: 69fa ldr r2, [r7, #28] 80138ba: 2101 movs r1, #1 80138bc: 6a78 ldr r0, [r7, #36] @ 0x24 80138be: f003 f81a bl 80168f6 80138c2: 6238 str r0, [r7, #32] 80138c4: e00b b.n 80138de #endif } else { if (mem == 0) { 80138c6: 69bb ldr r3, [r7, #24] 80138c8: 2b00 cmp r3, #0 80138ca: d108 bne.n 80138de #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 80138cc: 4b0b ldr r3, [pc, #44] @ (80138fc ) 80138ce: 9300 str r3, [sp, #0] 80138d0: 697b ldr r3, [r7, #20] 80138d2: 69fa ldr r2, [r7, #28] 80138d4: 2101 movs r1, #1 80138d6: 6a78 ldr r0, [r7, #36] @ 0x24 80138d8: f002 ffec bl 80168b4 80138dc: 6238 str r0, [r7, #32] #endif } } if ((hTimer == NULL) && (callb != NULL)) { 80138de: 6a3b ldr r3, [r7, #32] 80138e0: 2b00 cmp r3, #0 80138e2: d105 bne.n 80138f0 80138e4: 697b ldr r3, [r7, #20] 80138e6: 2b00 cmp r3, #0 80138e8: d002 beq.n 80138f0 vPortFree (callb); 80138ea: 6978 ldr r0, [r7, #20] 80138ec: f003 fefc bl 80176e8 } } } return ((osTimerId_t)hTimer); 80138f0: 6a3b ldr r3, [r7, #32] } 80138f2: 4618 mov r0, r3 80138f4: 3728 adds r7, #40 @ 0x28 80138f6: 46bd mov sp, r7 80138f8: bd80 pop {r7, pc} 80138fa: bf00 nop 80138fc: 080137dd .word 0x080137dd 08013900 : } return (p); } osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 8013900: b580 push {r7, lr} 8013902: b088 sub sp, #32 8013904: af02 add r7, sp, #8 8013906: 6078 str r0, [r7, #4] 8013908: 6039 str r1, [r7, #0] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 801390a: 687b ldr r3, [r7, #4] 801390c: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801390e: f3ef 8305 mrs r3, IPSR 8013912: 60fb str r3, [r7, #12] return(result); 8013914: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 8013916: 2b00 cmp r3, #0 8013918: d003 beq.n 8013922 stat = osErrorISR; 801391a: f06f 0305 mvn.w r3, #5 801391e: 617b str r3, [r7, #20] 8013920: e017 b.n 8013952 } else if (hTimer == NULL) { 8013922: 693b ldr r3, [r7, #16] 8013924: 2b00 cmp r3, #0 8013926: d103 bne.n 8013930 stat = osErrorParameter; 8013928: f06f 0303 mvn.w r3, #3 801392c: 617b str r3, [r7, #20] 801392e: e010 b.n 8013952 } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 8013930: 2300 movs r3, #0 8013932: 9300 str r3, [sp, #0] 8013934: 2300 movs r3, #0 8013936: 683a ldr r2, [r7, #0] 8013938: 2104 movs r1, #4 801393a: 6938 ldr r0, [r7, #16] 801393c: f003 f858 bl 80169f0 8013940: 4603 mov r3, r0 8013942: 2b01 cmp r3, #1 8013944: d102 bne.n 801394c stat = osOK; 8013946: 2300 movs r3, #0 8013948: 617b str r3, [r7, #20] 801394a: e002 b.n 8013952 } else { stat = osErrorResource; 801394c: f06f 0302 mvn.w r3, #2 8013950: 617b str r3, [r7, #20] } } return (stat); 8013952: 697b ldr r3, [r7, #20] } 8013954: 4618 mov r0, r3 8013956: 3718 adds r7, #24 8013958: 46bd mov sp, r7 801395a: bd80 pop {r7, pc} 0801395c : osStatus_t osTimerStop (osTimerId_t timer_id) { 801395c: b580 push {r7, lr} 801395e: b088 sub sp, #32 8013960: af02 add r7, sp, #8 8013962: 6078 str r0, [r7, #4] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 8013964: 687b ldr r3, [r7, #4] 8013966: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013968: f3ef 8305 mrs r3, IPSR 801396c: 60fb str r3, [r7, #12] return(result); 801396e: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 8013970: 2b00 cmp r3, #0 8013972: d003 beq.n 801397c stat = osErrorISR; 8013974: f06f 0305 mvn.w r3, #5 8013978: 617b str r3, [r7, #20] 801397a: e021 b.n 80139c0 } else if (hTimer == NULL) { 801397c: 693b ldr r3, [r7, #16] 801397e: 2b00 cmp r3, #0 8013980: d103 bne.n 801398a stat = osErrorParameter; 8013982: f06f 0303 mvn.w r3, #3 8013986: 617b str r3, [r7, #20] 8013988: e01a b.n 80139c0 } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 801398a: 6938 ldr r0, [r7, #16] 801398c: f003 fb40 bl 8017010 8013990: 4603 mov r3, r0 8013992: 2b00 cmp r3, #0 8013994: d103 bne.n 801399e stat = osErrorResource; 8013996: f06f 0302 mvn.w r3, #2 801399a: 617b str r3, [r7, #20] 801399c: e010 b.n 80139c0 } else { if (xTimerStop (hTimer, 0) == pdPASS) { 801399e: 2300 movs r3, #0 80139a0: 9300 str r3, [sp, #0] 80139a2: 2300 movs r3, #0 80139a4: 2200 movs r2, #0 80139a6: 2103 movs r1, #3 80139a8: 6938 ldr r0, [r7, #16] 80139aa: f003 f821 bl 80169f0 80139ae: 4603 mov r3, r0 80139b0: 2b01 cmp r3, #1 80139b2: d102 bne.n 80139ba stat = osOK; 80139b4: 2300 movs r3, #0 80139b6: 617b str r3, [r7, #20] 80139b8: e002 b.n 80139c0 } else { stat = osError; 80139ba: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80139be: 617b str r3, [r7, #20] } } } return (stat); 80139c0: 697b ldr r3, [r7, #20] } 80139c2: 4618 mov r0, r3 80139c4: 3718 adds r7, #24 80139c6: 46bd mov sp, r7 80139c8: bd80 pop {r7, pc} 080139ca : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 80139ca: b580 push {r7, lr} 80139cc: b088 sub sp, #32 80139ce: af00 add r7, sp, #0 80139d0: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 80139d2: 2300 movs r3, #0 80139d4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80139d6: f3ef 8305 mrs r3, IPSR 80139da: 60bb str r3, [r7, #8] return(result); 80139dc: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 80139de: 2b00 cmp r3, #0 80139e0: d174 bne.n 8013acc if (attr != NULL) { 80139e2: 687b ldr r3, [r7, #4] 80139e4: 2b00 cmp r3, #0 80139e6: d003 beq.n 80139f0 type = attr->attr_bits; 80139e8: 687b ldr r3, [r7, #4] 80139ea: 685b ldr r3, [r3, #4] 80139ec: 61bb str r3, [r7, #24] 80139ee: e001 b.n 80139f4 } else { type = 0U; 80139f0: 2300 movs r3, #0 80139f2: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 80139f4: 69bb ldr r3, [r7, #24] 80139f6: f003 0301 and.w r3, r3, #1 80139fa: 2b00 cmp r3, #0 80139fc: d002 beq.n 8013a04 rmtx = 1U; 80139fe: 2301 movs r3, #1 8013a00: 617b str r3, [r7, #20] 8013a02: e001 b.n 8013a08 } else { rmtx = 0U; 8013a04: 2300 movs r3, #0 8013a06: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 8013a08: 69bb ldr r3, [r7, #24] 8013a0a: f003 0308 and.w r3, r3, #8 8013a0e: 2b00 cmp r3, #0 8013a10: d15c bne.n 8013acc mem = -1; 8013a12: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013a16: 613b str r3, [r7, #16] if (attr != NULL) { 8013a18: 687b ldr r3, [r7, #4] 8013a1a: 2b00 cmp r3, #0 8013a1c: d015 beq.n 8013a4a if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 8013a1e: 687b ldr r3, [r7, #4] 8013a20: 689b ldr r3, [r3, #8] 8013a22: 2b00 cmp r3, #0 8013a24: d006 beq.n 8013a34 8013a26: 687b ldr r3, [r7, #4] 8013a28: 68db ldr r3, [r3, #12] 8013a2a: 2b4f cmp r3, #79 @ 0x4f 8013a2c: d902 bls.n 8013a34 mem = 1; 8013a2e: 2301 movs r3, #1 8013a30: 613b str r3, [r7, #16] 8013a32: e00c b.n 8013a4e } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8013a34: 687b ldr r3, [r7, #4] 8013a36: 689b ldr r3, [r3, #8] 8013a38: 2b00 cmp r3, #0 8013a3a: d108 bne.n 8013a4e 8013a3c: 687b ldr r3, [r7, #4] 8013a3e: 68db ldr r3, [r3, #12] 8013a40: 2b00 cmp r3, #0 8013a42: d104 bne.n 8013a4e mem = 0; 8013a44: 2300 movs r3, #0 8013a46: 613b str r3, [r7, #16] 8013a48: e001 b.n 8013a4e } } } else { mem = 0; 8013a4a: 2300 movs r3, #0 8013a4c: 613b str r3, [r7, #16] } if (mem == 1) { 8013a4e: 693b ldr r3, [r7, #16] 8013a50: 2b01 cmp r3, #1 8013a52: d112 bne.n 8013a7a #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 8013a54: 697b ldr r3, [r7, #20] 8013a56: 2b00 cmp r3, #0 8013a58: d007 beq.n 8013a6a #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 8013a5a: 687b ldr r3, [r7, #4] 8013a5c: 689b ldr r3, [r3, #8] 8013a5e: 4619 mov r1, r3 8013a60: 2004 movs r0, #4 8013a62: f000 fc50 bl 8014306 8013a66: 61f8 str r0, [r7, #28] 8013a68: e016 b.n 8013a98 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 8013a6a: 687b ldr r3, [r7, #4] 8013a6c: 689b ldr r3, [r3, #8] 8013a6e: 4619 mov r1, r3 8013a70: 2001 movs r0, #1 8013a72: f000 fc48 bl 8014306 8013a76: 61f8 str r0, [r7, #28] 8013a78: e00e b.n 8013a98 } #endif } else { if (mem == 0) { 8013a7a: 693b ldr r3, [r7, #16] 8013a7c: 2b00 cmp r3, #0 8013a7e: d10b bne.n 8013a98 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 8013a80: 697b ldr r3, [r7, #20] 8013a82: 2b00 cmp r3, #0 8013a84: d004 beq.n 8013a90 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 8013a86: 2004 movs r0, #4 8013a88: f000 fc25 bl 80142d6 8013a8c: 61f8 str r0, [r7, #28] 8013a8e: e003 b.n 8013a98 #endif } else { hMutex = xSemaphoreCreateMutex (); 8013a90: 2001 movs r0, #1 8013a92: f000 fc20 bl 80142d6 8013a96: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8013a98: 69fb ldr r3, [r7, #28] 8013a9a: 2b00 cmp r3, #0 8013a9c: d00c beq.n 8013ab8 if (attr != NULL) { 8013a9e: 687b ldr r3, [r7, #4] 8013aa0: 2b00 cmp r3, #0 8013aa2: d003 beq.n 8013aac name = attr->name; 8013aa4: 687b ldr r3, [r7, #4] 8013aa6: 681b ldr r3, [r3, #0] 8013aa8: 60fb str r3, [r7, #12] 8013aaa: e001 b.n 8013ab0 } else { name = NULL; 8013aac: 2300 movs r3, #0 8013aae: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 8013ab0: 68f9 ldr r1, [r7, #12] 8013ab2: 69f8 ldr r0, [r7, #28] 8013ab4: f001 f9ea bl 8014e8c } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 8013ab8: 69fb ldr r3, [r7, #28] 8013aba: 2b00 cmp r3, #0 8013abc: d006 beq.n 8013acc 8013abe: 697b ldr r3, [r7, #20] 8013ac0: 2b00 cmp r3, #0 8013ac2: d003 beq.n 8013acc hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 8013ac4: 69fb ldr r3, [r7, #28] 8013ac6: f043 0301 orr.w r3, r3, #1 8013aca: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 8013acc: 69fb ldr r3, [r7, #28] } 8013ace: 4618 mov r0, r3 8013ad0: 3720 adds r7, #32 8013ad2: 46bd mov sp, r7 8013ad4: bd80 pop {r7, pc} 08013ad6 : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 8013ad6: b580 push {r7, lr} 8013ad8: b086 sub sp, #24 8013ada: af00 add r7, sp, #0 8013adc: 6078 str r0, [r7, #4] 8013ade: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8013ae0: 687b ldr r3, [r7, #4] 8013ae2: f023 0301 bic.w r3, r3, #1 8013ae6: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 8013ae8: 687b ldr r3, [r7, #4] 8013aea: f003 0301 and.w r3, r3, #1 8013aee: 60fb str r3, [r7, #12] stat = osOK; 8013af0: 2300 movs r3, #0 8013af2: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013af4: f3ef 8305 mrs r3, IPSR 8013af8: 60bb str r3, [r7, #8] return(result); 8013afa: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8013afc: 2b00 cmp r3, #0 8013afe: d003 beq.n 8013b08 stat = osErrorISR; 8013b00: f06f 0305 mvn.w r3, #5 8013b04: 617b str r3, [r7, #20] 8013b06: e02c b.n 8013b62 } else if (hMutex == NULL) { 8013b08: 693b ldr r3, [r7, #16] 8013b0a: 2b00 cmp r3, #0 8013b0c: d103 bne.n 8013b16 stat = osErrorParameter; 8013b0e: f06f 0303 mvn.w r3, #3 8013b12: 617b str r3, [r7, #20] 8013b14: e025 b.n 8013b62 } else { if (rmtx != 0U) { 8013b16: 68fb ldr r3, [r7, #12] 8013b18: 2b00 cmp r3, #0 8013b1a: d011 beq.n 8013b40 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 8013b1c: 6839 ldr r1, [r7, #0] 8013b1e: 6938 ldr r0, [r7, #16] 8013b20: f000 fc41 bl 80143a6 8013b24: 4603 mov r3, r0 8013b26: 2b01 cmp r3, #1 8013b28: d01b beq.n 8013b62 if (timeout != 0U) { 8013b2a: 683b ldr r3, [r7, #0] 8013b2c: 2b00 cmp r3, #0 8013b2e: d003 beq.n 8013b38 stat = osErrorTimeout; 8013b30: f06f 0301 mvn.w r3, #1 8013b34: 617b str r3, [r7, #20] 8013b36: e014 b.n 8013b62 } else { stat = osErrorResource; 8013b38: f06f 0302 mvn.w r3, #2 8013b3c: 617b str r3, [r7, #20] 8013b3e: e010 b.n 8013b62 } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 8013b40: 6839 ldr r1, [r7, #0] 8013b42: 6938 ldr r0, [r7, #16] 8013b44: f000 fee8 bl 8014918 8013b48: 4603 mov r3, r0 8013b4a: 2b01 cmp r3, #1 8013b4c: d009 beq.n 8013b62 if (timeout != 0U) { 8013b4e: 683b ldr r3, [r7, #0] 8013b50: 2b00 cmp r3, #0 8013b52: d003 beq.n 8013b5c stat = osErrorTimeout; 8013b54: f06f 0301 mvn.w r3, #1 8013b58: 617b str r3, [r7, #20] 8013b5a: e002 b.n 8013b62 } else { stat = osErrorResource; 8013b5c: f06f 0302 mvn.w r3, #2 8013b60: 617b str r3, [r7, #20] } } } } return (stat); 8013b62: 697b ldr r3, [r7, #20] } 8013b64: 4618 mov r0, r3 8013b66: 3718 adds r7, #24 8013b68: 46bd mov sp, r7 8013b6a: bd80 pop {r7, pc} 08013b6c : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 8013b6c: b580 push {r7, lr} 8013b6e: b086 sub sp, #24 8013b70: af00 add r7, sp, #0 8013b72: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8013b74: 687b ldr r3, [r7, #4] 8013b76: f023 0301 bic.w r3, r3, #1 8013b7a: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 8013b7c: 687b ldr r3, [r7, #4] 8013b7e: f003 0301 and.w r3, r3, #1 8013b82: 60fb str r3, [r7, #12] stat = osOK; 8013b84: 2300 movs r3, #0 8013b86: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013b88: f3ef 8305 mrs r3, IPSR 8013b8c: 60bb str r3, [r7, #8] return(result); 8013b8e: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8013b90: 2b00 cmp r3, #0 8013b92: d003 beq.n 8013b9c stat = osErrorISR; 8013b94: f06f 0305 mvn.w r3, #5 8013b98: 617b str r3, [r7, #20] 8013b9a: e01f b.n 8013bdc } else if (hMutex == NULL) { 8013b9c: 693b ldr r3, [r7, #16] 8013b9e: 2b00 cmp r3, #0 8013ba0: d103 bne.n 8013baa stat = osErrorParameter; 8013ba2: f06f 0303 mvn.w r3, #3 8013ba6: 617b str r3, [r7, #20] 8013ba8: e018 b.n 8013bdc } else { if (rmtx != 0U) { 8013baa: 68fb ldr r3, [r7, #12] 8013bac: 2b00 cmp r3, #0 8013bae: d009 beq.n 8013bc4 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 8013bb0: 6938 ldr r0, [r7, #16] 8013bb2: f000 fbc3 bl 801433c 8013bb6: 4603 mov r3, r0 8013bb8: 2b01 cmp r3, #1 8013bba: d00f beq.n 8013bdc stat = osErrorResource; 8013bbc: f06f 0302 mvn.w r3, #2 8013bc0: 617b str r3, [r7, #20] 8013bc2: e00b b.n 8013bdc } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 8013bc4: 2300 movs r3, #0 8013bc6: 2200 movs r2, #0 8013bc8: 2100 movs r1, #0 8013bca: 6938 ldr r0, [r7, #16] 8013bcc: f000 fc22 bl 8014414 8013bd0: 4603 mov r3, r0 8013bd2: 2b01 cmp r3, #1 8013bd4: d002 beq.n 8013bdc stat = osErrorResource; 8013bd6: f06f 0302 mvn.w r3, #2 8013bda: 617b str r3, [r7, #20] } } } return (stat); 8013bdc: 697b ldr r3, [r7, #20] } 8013bde: 4618 mov r0, r3 8013be0: 3718 adds r7, #24 8013be2: 46bd mov sp, r7 8013be4: bd80 pop {r7, pc} 08013be6 : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 8013be6: b580 push {r7, lr} 8013be8: b08a sub sp, #40 @ 0x28 8013bea: af02 add r7, sp, #8 8013bec: 60f8 str r0, [r7, #12] 8013bee: 60b9 str r1, [r7, #8] 8013bf0: 607a str r2, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hQueue = NULL; 8013bf2: 2300 movs r3, #0 8013bf4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013bf6: f3ef 8305 mrs r3, IPSR 8013bfa: 613b str r3, [r7, #16] return(result); 8013bfc: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 8013bfe: 2b00 cmp r3, #0 8013c00: d15f bne.n 8013cc2 8013c02: 68fb ldr r3, [r7, #12] 8013c04: 2b00 cmp r3, #0 8013c06: d05c beq.n 8013cc2 8013c08: 68bb ldr r3, [r7, #8] 8013c0a: 2b00 cmp r3, #0 8013c0c: d059 beq.n 8013cc2 mem = -1; 8013c0e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013c12: 61bb str r3, [r7, #24] if (attr != NULL) { 8013c14: 687b ldr r3, [r7, #4] 8013c16: 2b00 cmp r3, #0 8013c18: d029 beq.n 8013c6e if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8013c1a: 687b ldr r3, [r7, #4] 8013c1c: 689b ldr r3, [r3, #8] 8013c1e: 2b00 cmp r3, #0 8013c20: d012 beq.n 8013c48 8013c22: 687b ldr r3, [r7, #4] 8013c24: 68db ldr r3, [r3, #12] 8013c26: 2b4f cmp r3, #79 @ 0x4f 8013c28: d90e bls.n 8013c48 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8013c2a: 687b ldr r3, [r7, #4] 8013c2c: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8013c2e: 2b00 cmp r3, #0 8013c30: d00a beq.n 8013c48 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8013c32: 687b ldr r3, [r7, #4] 8013c34: 695a ldr r2, [r3, #20] 8013c36: 68fb ldr r3, [r7, #12] 8013c38: 68b9 ldr r1, [r7, #8] 8013c3a: fb01 f303 mul.w r3, r1, r3 8013c3e: 429a cmp r2, r3 8013c40: d302 bcc.n 8013c48 mem = 1; 8013c42: 2301 movs r3, #1 8013c44: 61bb str r3, [r7, #24] 8013c46: e014 b.n 8013c72 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8013c48: 687b ldr r3, [r7, #4] 8013c4a: 689b ldr r3, [r3, #8] 8013c4c: 2b00 cmp r3, #0 8013c4e: d110 bne.n 8013c72 8013c50: 687b ldr r3, [r7, #4] 8013c52: 68db ldr r3, [r3, #12] 8013c54: 2b00 cmp r3, #0 8013c56: d10c bne.n 8013c72 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8013c58: 687b ldr r3, [r7, #4] 8013c5a: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8013c5c: 2b00 cmp r3, #0 8013c5e: d108 bne.n 8013c72 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8013c60: 687b ldr r3, [r7, #4] 8013c62: 695b ldr r3, [r3, #20] 8013c64: 2b00 cmp r3, #0 8013c66: d104 bne.n 8013c72 mem = 0; 8013c68: 2300 movs r3, #0 8013c6a: 61bb str r3, [r7, #24] 8013c6c: e001 b.n 8013c72 } } } else { mem = 0; 8013c6e: 2300 movs r3, #0 8013c70: 61bb str r3, [r7, #24] } if (mem == 1) { 8013c72: 69bb ldr r3, [r7, #24] 8013c74: 2b01 cmp r3, #1 8013c76: d10b bne.n 8013c90 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8013c78: 687b ldr r3, [r7, #4] 8013c7a: 691a ldr r2, [r3, #16] 8013c7c: 687b ldr r3, [r7, #4] 8013c7e: 689b ldr r3, [r3, #8] 8013c80: 2100 movs r1, #0 8013c82: 9100 str r1, [sp, #0] 8013c84: 68b9 ldr r1, [r7, #8] 8013c86: 68f8 ldr r0, [r7, #12] 8013c88: f000 fa30 bl 80140ec 8013c8c: 61f8 str r0, [r7, #28] 8013c8e: e008 b.n 8013ca2 #endif } else { if (mem == 0) { 8013c90: 69bb ldr r3, [r7, #24] 8013c92: 2b00 cmp r3, #0 8013c94: d105 bne.n 8013ca2 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 8013c96: 2200 movs r2, #0 8013c98: 68b9 ldr r1, [r7, #8] 8013c9a: 68f8 ldr r0, [r7, #12] 8013c9c: f000 faa3 bl 80141e6 8013ca0: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 8013ca2: 69fb ldr r3, [r7, #28] 8013ca4: 2b00 cmp r3, #0 8013ca6: d00c beq.n 8013cc2 if (attr != NULL) { 8013ca8: 687b ldr r3, [r7, #4] 8013caa: 2b00 cmp r3, #0 8013cac: d003 beq.n 8013cb6 name = attr->name; 8013cae: 687b ldr r3, [r7, #4] 8013cb0: 681b ldr r3, [r3, #0] 8013cb2: 617b str r3, [r7, #20] 8013cb4: e001 b.n 8013cba } else { name = NULL; 8013cb6: 2300 movs r3, #0 8013cb8: 617b str r3, [r7, #20] } vQueueAddToRegistry (hQueue, name); 8013cba: 6979 ldr r1, [r7, #20] 8013cbc: 69f8 ldr r0, [r7, #28] 8013cbe: f001 f8e5 bl 8014e8c } #endif } return ((osMessageQueueId_t)hQueue); 8013cc2: 69fb ldr r3, [r7, #28] } 8013cc4: 4618 mov r0, r3 8013cc6: 3720 adds r7, #32 8013cc8: 46bd mov sp, r7 8013cca: bd80 pop {r7, pc} 08013ccc : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 8013ccc: b580 push {r7, lr} 8013cce: b088 sub sp, #32 8013cd0: af00 add r7, sp, #0 8013cd2: 60f8 str r0, [r7, #12] 8013cd4: 60b9 str r1, [r7, #8] 8013cd6: 603b str r3, [r7, #0] 8013cd8: 4613 mov r3, r2 8013cda: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8013cdc: 68fb ldr r3, [r7, #12] 8013cde: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8013ce0: 2300 movs r3, #0 8013ce2: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013ce4: f3ef 8305 mrs r3, IPSR 8013ce8: 617b str r3, [r7, #20] return(result); 8013cea: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8013cec: 2b00 cmp r3, #0 8013cee: d028 beq.n 8013d42 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8013cf0: 69bb ldr r3, [r7, #24] 8013cf2: 2b00 cmp r3, #0 8013cf4: d005 beq.n 8013d02 8013cf6: 68bb ldr r3, [r7, #8] 8013cf8: 2b00 cmp r3, #0 8013cfa: d002 beq.n 8013d02 8013cfc: 683b ldr r3, [r7, #0] 8013cfe: 2b00 cmp r3, #0 8013d00: d003 beq.n 8013d0a stat = osErrorParameter; 8013d02: f06f 0303 mvn.w r3, #3 8013d06: 61fb str r3, [r7, #28] 8013d08: e038 b.n 8013d7c } else { yield = pdFALSE; 8013d0a: 2300 movs r3, #0 8013d0c: 613b str r3, [r7, #16] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 8013d0e: f107 0210 add.w r2, r7, #16 8013d12: 2300 movs r3, #0 8013d14: 68b9 ldr r1, [r7, #8] 8013d16: 69b8 ldr r0, [r7, #24] 8013d18: f000 fc7e bl 8014618 8013d1c: 4603 mov r3, r0 8013d1e: 2b01 cmp r3, #1 8013d20: d003 beq.n 8013d2a stat = osErrorResource; 8013d22: f06f 0302 mvn.w r3, #2 8013d26: 61fb str r3, [r7, #28] 8013d28: e028 b.n 8013d7c } else { portYIELD_FROM_ISR (yield); 8013d2a: 693b ldr r3, [r7, #16] 8013d2c: 2b00 cmp r3, #0 8013d2e: d025 beq.n 8013d7c 8013d30: 4b15 ldr r3, [pc, #84] @ (8013d88 ) 8013d32: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013d36: 601a str r2, [r3, #0] 8013d38: f3bf 8f4f dsb sy 8013d3c: f3bf 8f6f isb sy 8013d40: e01c b.n 8013d7c } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8013d42: 69bb ldr r3, [r7, #24] 8013d44: 2b00 cmp r3, #0 8013d46: d002 beq.n 8013d4e 8013d48: 68bb ldr r3, [r7, #8] 8013d4a: 2b00 cmp r3, #0 8013d4c: d103 bne.n 8013d56 stat = osErrorParameter; 8013d4e: f06f 0303 mvn.w r3, #3 8013d52: 61fb str r3, [r7, #28] 8013d54: e012 b.n 8013d7c } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8013d56: 2300 movs r3, #0 8013d58: 683a ldr r2, [r7, #0] 8013d5a: 68b9 ldr r1, [r7, #8] 8013d5c: 69b8 ldr r0, [r7, #24] 8013d5e: f000 fb59 bl 8014414 8013d62: 4603 mov r3, r0 8013d64: 2b01 cmp r3, #1 8013d66: d009 beq.n 8013d7c if (timeout != 0U) { 8013d68: 683b ldr r3, [r7, #0] 8013d6a: 2b00 cmp r3, #0 8013d6c: d003 beq.n 8013d76 stat = osErrorTimeout; 8013d6e: f06f 0301 mvn.w r3, #1 8013d72: 61fb str r3, [r7, #28] 8013d74: e002 b.n 8013d7c } else { stat = osErrorResource; 8013d76: f06f 0302 mvn.w r3, #2 8013d7a: 61fb str r3, [r7, #28] } } } } return (stat); 8013d7c: 69fb ldr r3, [r7, #28] } 8013d7e: 4618 mov r0, r3 8013d80: 3720 adds r7, #32 8013d82: 46bd mov sp, r7 8013d84: bd80 pop {r7, pc} 8013d86: bf00 nop 8013d88: e000ed04 .word 0xe000ed04 08013d8c : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 8013d8c: b580 push {r7, lr} 8013d8e: b088 sub sp, #32 8013d90: af00 add r7, sp, #0 8013d92: 60f8 str r0, [r7, #12] 8013d94: 60b9 str r1, [r7, #8] 8013d96: 607a str r2, [r7, #4] 8013d98: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8013d9a: 68fb ldr r3, [r7, #12] 8013d9c: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8013d9e: 2300 movs r3, #0 8013da0: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013da2: f3ef 8305 mrs r3, IPSR 8013da6: 617b str r3, [r7, #20] return(result); 8013da8: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8013daa: 2b00 cmp r3, #0 8013dac: d028 beq.n 8013e00 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8013dae: 69bb ldr r3, [r7, #24] 8013db0: 2b00 cmp r3, #0 8013db2: d005 beq.n 8013dc0 8013db4: 68bb ldr r3, [r7, #8] 8013db6: 2b00 cmp r3, #0 8013db8: d002 beq.n 8013dc0 8013dba: 683b ldr r3, [r7, #0] 8013dbc: 2b00 cmp r3, #0 8013dbe: d003 beq.n 8013dc8 stat = osErrorParameter; 8013dc0: f06f 0303 mvn.w r3, #3 8013dc4: 61fb str r3, [r7, #28] 8013dc6: e037 b.n 8013e38 } else { yield = pdFALSE; 8013dc8: 2300 movs r3, #0 8013dca: 613b str r3, [r7, #16] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 8013dcc: f107 0310 add.w r3, r7, #16 8013dd0: 461a mov r2, r3 8013dd2: 68b9 ldr r1, [r7, #8] 8013dd4: 69b8 ldr r0, [r7, #24] 8013dd6: f000 feaf bl 8014b38 8013dda: 4603 mov r3, r0 8013ddc: 2b01 cmp r3, #1 8013dde: d003 beq.n 8013de8 stat = osErrorResource; 8013de0: f06f 0302 mvn.w r3, #2 8013de4: 61fb str r3, [r7, #28] 8013de6: e027 b.n 8013e38 } else { portYIELD_FROM_ISR (yield); 8013de8: 693b ldr r3, [r7, #16] 8013dea: 2b00 cmp r3, #0 8013dec: d024 beq.n 8013e38 8013dee: 4b15 ldr r3, [pc, #84] @ (8013e44 ) 8013df0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8013df4: 601a str r2, [r3, #0] 8013df6: f3bf 8f4f dsb sy 8013dfa: f3bf 8f6f isb sy 8013dfe: e01b b.n 8013e38 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8013e00: 69bb ldr r3, [r7, #24] 8013e02: 2b00 cmp r3, #0 8013e04: d002 beq.n 8013e0c 8013e06: 68bb ldr r3, [r7, #8] 8013e08: 2b00 cmp r3, #0 8013e0a: d103 bne.n 8013e14 stat = osErrorParameter; 8013e0c: f06f 0303 mvn.w r3, #3 8013e10: 61fb str r3, [r7, #28] 8013e12: e011 b.n 8013e38 } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8013e14: 683a ldr r2, [r7, #0] 8013e16: 68b9 ldr r1, [r7, #8] 8013e18: 69b8 ldr r0, [r7, #24] 8013e1a: f000 fc9b bl 8014754 8013e1e: 4603 mov r3, r0 8013e20: 2b01 cmp r3, #1 8013e22: d009 beq.n 8013e38 if (timeout != 0U) { 8013e24: 683b ldr r3, [r7, #0] 8013e26: 2b00 cmp r3, #0 8013e28: d003 beq.n 8013e32 stat = osErrorTimeout; 8013e2a: f06f 0301 mvn.w r3, #1 8013e2e: 61fb str r3, [r7, #28] 8013e30: e002 b.n 8013e38 } else { stat = osErrorResource; 8013e32: f06f 0302 mvn.w r3, #2 8013e36: 61fb str r3, [r7, #28] } } } } return (stat); 8013e38: 69fb ldr r3, [r7, #28] } 8013e3a: 4618 mov r0, r3 8013e3c: 3720 adds r7, #32 8013e3e: 46bd mov sp, r7 8013e40: bd80 pop {r7, pc} 8013e42: bf00 nop 8013e44: e000ed04 .word 0xe000ed04 08013e48 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 8013e48: b480 push {r7} 8013e4a: b085 sub sp, #20 8013e4c: af00 add r7, sp, #0 8013e4e: 60f8 str r0, [r7, #12] 8013e50: 60b9 str r1, [r7, #8] 8013e52: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 8013e54: 68fb ldr r3, [r7, #12] 8013e56: 4a07 ldr r2, [pc, #28] @ (8013e74 ) 8013e58: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 8013e5a: 68bb ldr r3, [r7, #8] 8013e5c: 4a06 ldr r2, [pc, #24] @ (8013e78 ) 8013e5e: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8013e60: 687b ldr r3, [r7, #4] 8013e62: f44f 7200 mov.w r2, #512 @ 0x200 8013e66: 601a str r2, [r3, #0] } 8013e68: bf00 nop 8013e6a: 3714 adds r7, #20 8013e6c: 46bd mov sp, r7 8013e6e: f85d 7b04 ldr.w r7, [sp], #4 8013e72: 4770 bx lr 8013e74: 24000cb0 .word 0x24000cb0 8013e78: 24000d58 .word 0x24000d58 08013e7c : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 8013e7c: b480 push {r7} 8013e7e: b085 sub sp, #20 8013e80: af00 add r7, sp, #0 8013e82: 60f8 str r0, [r7, #12] 8013e84: 60b9 str r1, [r7, #8] 8013e86: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 8013e88: 68fb ldr r3, [r7, #12] 8013e8a: 4a07 ldr r2, [pc, #28] @ (8013ea8 ) 8013e8c: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 8013e8e: 68bb ldr r3, [r7, #8] 8013e90: 4a06 ldr r2, [pc, #24] @ (8013eac ) 8013e92: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8013e94: 687b ldr r3, [r7, #4] 8013e96: f44f 6280 mov.w r2, #1024 @ 0x400 8013e9a: 601a str r2, [r3, #0] } 8013e9c: bf00 nop 8013e9e: 3714 adds r7, #20 8013ea0: 46bd mov sp, r7 8013ea2: f85d 7b04 ldr.w r7, [sp], #4 8013ea6: 4770 bx lr 8013ea8: 24001558 .word 0x24001558 8013eac: 24001600 .word 0x24001600 08013eb0 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8013eb0: b480 push {r7} 8013eb2: b083 sub sp, #12 8013eb4: af00 add r7, sp, #0 8013eb6: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013eb8: 687b ldr r3, [r7, #4] 8013eba: f103 0208 add.w r2, r3, #8 8013ebe: 687b ldr r3, [r7, #4] 8013ec0: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 8013ec2: 687b ldr r3, [r7, #4] 8013ec4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8013ec8: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013eca: 687b ldr r3, [r7, #4] 8013ecc: f103 0208 add.w r2, r3, #8 8013ed0: 687b ldr r3, [r7, #4] 8013ed2: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8013ed4: 687b ldr r3, [r7, #4] 8013ed6: f103 0208 add.w r2, r3, #8 8013eda: 687b ldr r3, [r7, #4] 8013edc: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 8013ede: 687b ldr r3, [r7, #4] 8013ee0: 2200 movs r2, #0 8013ee2: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 8013ee4: bf00 nop 8013ee6: 370c adds r7, #12 8013ee8: 46bd mov sp, r7 8013eea: f85d 7b04 ldr.w r7, [sp], #4 8013eee: 4770 bx lr 08013ef0 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 8013ef0: b480 push {r7} 8013ef2: b083 sub sp, #12 8013ef4: af00 add r7, sp, #0 8013ef6: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 8013ef8: 687b ldr r3, [r7, #4] 8013efa: 2200 movs r2, #0 8013efc: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 8013efe: bf00 nop 8013f00: 370c adds r7, #12 8013f02: 46bd mov sp, r7 8013f04: f85d 7b04 ldr.w r7, [sp], #4 8013f08: 4770 bx lr 08013f0a : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8013f0a: b480 push {r7} 8013f0c: b085 sub sp, #20 8013f0e: af00 add r7, sp, #0 8013f10: 6078 str r0, [r7, #4] 8013f12: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 8013f14: 687b ldr r3, [r7, #4] 8013f16: 685b ldr r3, [r3, #4] 8013f18: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8013f1a: 683b ldr r3, [r7, #0] 8013f1c: 68fa ldr r2, [r7, #12] 8013f1e: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8013f20: 68fb ldr r3, [r7, #12] 8013f22: 689a ldr r2, [r3, #8] 8013f24: 683b ldr r3, [r7, #0] 8013f26: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8013f28: 68fb ldr r3, [r7, #12] 8013f2a: 689b ldr r3, [r3, #8] 8013f2c: 683a ldr r2, [r7, #0] 8013f2e: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8013f30: 68fb ldr r3, [r7, #12] 8013f32: 683a ldr r2, [r7, #0] 8013f34: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8013f36: 683b ldr r3, [r7, #0] 8013f38: 687a ldr r2, [r7, #4] 8013f3a: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8013f3c: 687b ldr r3, [r7, #4] 8013f3e: 681b ldr r3, [r3, #0] 8013f40: 1c5a adds r2, r3, #1 8013f42: 687b ldr r3, [r7, #4] 8013f44: 601a str r2, [r3, #0] } 8013f46: bf00 nop 8013f48: 3714 adds r7, #20 8013f4a: 46bd mov sp, r7 8013f4c: f85d 7b04 ldr.w r7, [sp], #4 8013f50: 4770 bx lr 08013f52 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8013f52: b480 push {r7} 8013f54: b085 sub sp, #20 8013f56: af00 add r7, sp, #0 8013f58: 6078 str r0, [r7, #4] 8013f5a: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8013f5c: 683b ldr r3, [r7, #0] 8013f5e: 681b ldr r3, [r3, #0] 8013f60: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8013f62: 68bb ldr r3, [r7, #8] 8013f64: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8013f68: d103 bne.n 8013f72 { pxIterator = pxList->xListEnd.pxPrevious; 8013f6a: 687b ldr r3, [r7, #4] 8013f6c: 691b ldr r3, [r3, #16] 8013f6e: 60fb str r3, [r7, #12] 8013f70: e00c b.n 8013f8c 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8013f72: 687b ldr r3, [r7, #4] 8013f74: 3308 adds r3, #8 8013f76: 60fb str r3, [r7, #12] 8013f78: e002 b.n 8013f80 8013f7a: 68fb ldr r3, [r7, #12] 8013f7c: 685b ldr r3, [r3, #4] 8013f7e: 60fb str r3, [r7, #12] 8013f80: 68fb ldr r3, [r7, #12] 8013f82: 685b ldr r3, [r3, #4] 8013f84: 681b ldr r3, [r3, #0] 8013f86: 68ba ldr r2, [r7, #8] 8013f88: 429a cmp r2, r3 8013f8a: d2f6 bcs.n 8013f7a /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8013f8c: 68fb ldr r3, [r7, #12] 8013f8e: 685a ldr r2, [r3, #4] 8013f90: 683b ldr r3, [r7, #0] 8013f92: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8013f94: 683b ldr r3, [r7, #0] 8013f96: 685b ldr r3, [r3, #4] 8013f98: 683a ldr r2, [r7, #0] 8013f9a: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8013f9c: 683b ldr r3, [r7, #0] 8013f9e: 68fa ldr r2, [r7, #12] 8013fa0: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8013fa2: 68fb ldr r3, [r7, #12] 8013fa4: 683a ldr r2, [r7, #0] 8013fa6: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8013fa8: 683b ldr r3, [r7, #0] 8013faa: 687a ldr r2, [r7, #4] 8013fac: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8013fae: 687b ldr r3, [r7, #4] 8013fb0: 681b ldr r3, [r3, #0] 8013fb2: 1c5a adds r2, r3, #1 8013fb4: 687b ldr r3, [r7, #4] 8013fb6: 601a str r2, [r3, #0] } 8013fb8: bf00 nop 8013fba: 3714 adds r7, #20 8013fbc: 46bd mov sp, r7 8013fbe: f85d 7b04 ldr.w r7, [sp], #4 8013fc2: 4770 bx lr 08013fc4 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8013fc4: b480 push {r7} 8013fc6: b085 sub sp, #20 8013fc8: af00 add r7, sp, #0 8013fca: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8013fcc: 687b ldr r3, [r7, #4] 8013fce: 691b ldr r3, [r3, #16] 8013fd0: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8013fd2: 687b ldr r3, [r7, #4] 8013fd4: 685b ldr r3, [r3, #4] 8013fd6: 687a ldr r2, [r7, #4] 8013fd8: 6892 ldr r2, [r2, #8] 8013fda: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8013fdc: 687b ldr r3, [r7, #4] 8013fde: 689b ldr r3, [r3, #8] 8013fe0: 687a ldr r2, [r7, #4] 8013fe2: 6852 ldr r2, [r2, #4] 8013fe4: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 8013fe6: 68fb ldr r3, [r7, #12] 8013fe8: 685b ldr r3, [r3, #4] 8013fea: 687a ldr r2, [r7, #4] 8013fec: 429a cmp r2, r3 8013fee: d103 bne.n 8013ff8 { pxList->pxIndex = pxItemToRemove->pxPrevious; 8013ff0: 687b ldr r3, [r7, #4] 8013ff2: 689a ldr r2, [r3, #8] 8013ff4: 68fb ldr r3, [r7, #12] 8013ff6: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8013ff8: 687b ldr r3, [r7, #4] 8013ffa: 2200 movs r2, #0 8013ffc: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8013ffe: 68fb ldr r3, [r7, #12] 8014000: 681b ldr r3, [r3, #0] 8014002: 1e5a subs r2, r3, #1 8014004: 68fb ldr r3, [r7, #12] 8014006: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8014008: 68fb ldr r3, [r7, #12] 801400a: 681b ldr r3, [r3, #0] } 801400c: 4618 mov r0, r3 801400e: 3714 adds r7, #20 8014010: 46bd mov sp, r7 8014012: f85d 7b04 ldr.w r7, [sp], #4 8014016: 4770 bx lr 08014018 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 8014018: b580 push {r7, lr} 801401a: b084 sub sp, #16 801401c: af00 add r7, sp, #0 801401e: 6078 str r0, [r7, #4] 8014020: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 8014022: 687b ldr r3, [r7, #4] 8014024: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 8014026: 68fb ldr r3, [r7, #12] 8014028: 2b00 cmp r3, #0 801402a: d10b bne.n 8014044 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 801402c: f04f 0350 mov.w r3, #80 @ 0x50 8014030: f383 8811 msr BASEPRI, r3 8014034: f3bf 8f6f isb sy 8014038: f3bf 8f4f dsb sy 801403c: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 801403e: bf00 nop 8014040: bf00 nop 8014042: e7fd b.n 8014040 taskENTER_CRITICAL(); 8014044: f003 f960 bl 8017308 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014048: 68fb ldr r3, [r7, #12] 801404a: 681a ldr r2, [r3, #0] 801404c: 68fb ldr r3, [r7, #12] 801404e: 6bdb ldr r3, [r3, #60] @ 0x3c 8014050: 68f9 ldr r1, [r7, #12] 8014052: 6c09 ldr r1, [r1, #64] @ 0x40 8014054: fb01 f303 mul.w r3, r1, r3 8014058: 441a add r2, r3 801405a: 68fb ldr r3, [r7, #12] 801405c: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 801405e: 68fb ldr r3, [r7, #12] 8014060: 2200 movs r2, #0 8014062: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8014064: 68fb ldr r3, [r7, #12] 8014066: 681a ldr r2, [r3, #0] 8014068: 68fb ldr r3, [r7, #12] 801406a: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 801406c: 68fb ldr r3, [r7, #12] 801406e: 681a ldr r2, [r3, #0] 8014070: 68fb ldr r3, [r7, #12] 8014072: 6bdb ldr r3, [r3, #60] @ 0x3c 8014074: 3b01 subs r3, #1 8014076: 68f9 ldr r1, [r7, #12] 8014078: 6c09 ldr r1, [r1, #64] @ 0x40 801407a: fb01 f303 mul.w r3, r1, r3 801407e: 441a add r2, r3 8014080: 68fb ldr r3, [r7, #12] 8014082: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8014084: 68fb ldr r3, [r7, #12] 8014086: 22ff movs r2, #255 @ 0xff 8014088: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 801408c: 68fb ldr r3, [r7, #12] 801408e: 22ff movs r2, #255 @ 0xff 8014090: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8014094: 683b ldr r3, [r7, #0] 8014096: 2b00 cmp r3, #0 8014098: d114 bne.n 80140c4 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 801409a: 68fb ldr r3, [r7, #12] 801409c: 691b ldr r3, [r3, #16] 801409e: 2b00 cmp r3, #0 80140a0: d01a beq.n 80140d8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80140a2: 68fb ldr r3, [r7, #12] 80140a4: 3310 adds r3, #16 80140a6: 4618 mov r0, r3 80140a8: f001 fdac bl 8015c04 80140ac: 4603 mov r3, r0 80140ae: 2b00 cmp r3, #0 80140b0: d012 beq.n 80140d8 { queueYIELD_IF_USING_PREEMPTION(); 80140b2: 4b0d ldr r3, [pc, #52] @ (80140e8 ) 80140b4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80140b8: 601a str r2, [r3, #0] 80140ba: f3bf 8f4f dsb sy 80140be: f3bf 8f6f isb sy 80140c2: e009 b.n 80140d8 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 80140c4: 68fb ldr r3, [r7, #12] 80140c6: 3310 adds r3, #16 80140c8: 4618 mov r0, r3 80140ca: f7ff fef1 bl 8013eb0 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 80140ce: 68fb ldr r3, [r7, #12] 80140d0: 3324 adds r3, #36 @ 0x24 80140d2: 4618 mov r0, r3 80140d4: f7ff feec bl 8013eb0 } } taskEXIT_CRITICAL(); 80140d8: f003 f948 bl 801736c /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 80140dc: 2301 movs r3, #1 } 80140de: 4618 mov r0, r3 80140e0: 3710 adds r7, #16 80140e2: 46bd mov sp, r7 80140e4: bd80 pop {r7, pc} 80140e6: bf00 nop 80140e8: e000ed04 .word 0xe000ed04 080140ec : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 80140ec: b580 push {r7, lr} 80140ee: b08e sub sp, #56 @ 0x38 80140f0: af02 add r7, sp, #8 80140f2: 60f8 str r0, [r7, #12] 80140f4: 60b9 str r1, [r7, #8] 80140f6: 607a str r2, [r7, #4] 80140f8: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 80140fa: 68fb ldr r3, [r7, #12] 80140fc: 2b00 cmp r3, #0 80140fe: d10b bne.n 8014118 __asm volatile 8014100: f04f 0350 mov.w r3, #80 @ 0x50 8014104: f383 8811 msr BASEPRI, r3 8014108: f3bf 8f6f isb sy 801410c: f3bf 8f4f dsb sy 8014110: 62bb str r3, [r7, #40] @ 0x28 } 8014112: bf00 nop 8014114: bf00 nop 8014116: e7fd b.n 8014114 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 8014118: 683b ldr r3, [r7, #0] 801411a: 2b00 cmp r3, #0 801411c: d10b bne.n 8014136 __asm volatile 801411e: f04f 0350 mov.w r3, #80 @ 0x50 8014122: f383 8811 msr BASEPRI, r3 8014126: f3bf 8f6f isb sy 801412a: f3bf 8f4f dsb sy 801412e: 627b str r3, [r7, #36] @ 0x24 } 8014130: bf00 nop 8014132: bf00 nop 8014134: e7fd b.n 8014132 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 8014136: 687b ldr r3, [r7, #4] 8014138: 2b00 cmp r3, #0 801413a: d002 beq.n 8014142 801413c: 68bb ldr r3, [r7, #8] 801413e: 2b00 cmp r3, #0 8014140: d001 beq.n 8014146 8014142: 2301 movs r3, #1 8014144: e000 b.n 8014148 8014146: 2300 movs r3, #0 8014148: 2b00 cmp r3, #0 801414a: d10b bne.n 8014164 __asm volatile 801414c: f04f 0350 mov.w r3, #80 @ 0x50 8014150: f383 8811 msr BASEPRI, r3 8014154: f3bf 8f6f isb sy 8014158: f3bf 8f4f dsb sy 801415c: 623b str r3, [r7, #32] } 801415e: bf00 nop 8014160: bf00 nop 8014162: e7fd b.n 8014160 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8014164: 687b ldr r3, [r7, #4] 8014166: 2b00 cmp r3, #0 8014168: d102 bne.n 8014170 801416a: 68bb ldr r3, [r7, #8] 801416c: 2b00 cmp r3, #0 801416e: d101 bne.n 8014174 8014170: 2301 movs r3, #1 8014172: e000 b.n 8014176 8014174: 2300 movs r3, #0 8014176: 2b00 cmp r3, #0 8014178: d10b bne.n 8014192 __asm volatile 801417a: f04f 0350 mov.w r3, #80 @ 0x50 801417e: f383 8811 msr BASEPRI, r3 8014182: f3bf 8f6f isb sy 8014186: f3bf 8f4f dsb sy 801418a: 61fb str r3, [r7, #28] } 801418c: bf00 nop 801418e: bf00 nop 8014190: e7fd b.n 801418e #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8014192: 2350 movs r3, #80 @ 0x50 8014194: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 8014196: 697b ldr r3, [r7, #20] 8014198: 2b50 cmp r3, #80 @ 0x50 801419a: d00b beq.n 80141b4 __asm volatile 801419c: f04f 0350 mov.w r3, #80 @ 0x50 80141a0: f383 8811 msr BASEPRI, r3 80141a4: f3bf 8f6f isb sy 80141a8: f3bf 8f4f dsb sy 80141ac: 61bb str r3, [r7, #24] } 80141ae: bf00 nop 80141b0: bf00 nop 80141b2: e7fd b.n 80141b0 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 80141b4: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 80141b6: 683b ldr r3, [r7, #0] 80141b8: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 80141ba: 6afb ldr r3, [r7, #44] @ 0x2c 80141bc: 2b00 cmp r3, #0 80141be: d00d beq.n 80141dc #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 80141c0: 6afb ldr r3, [r7, #44] @ 0x2c 80141c2: 2201 movs r2, #1 80141c4: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 80141c8: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 80141cc: 6afb ldr r3, [r7, #44] @ 0x2c 80141ce: 9300 str r3, [sp, #0] 80141d0: 4613 mov r3, r2 80141d2: 687a ldr r2, [r7, #4] 80141d4: 68b9 ldr r1, [r7, #8] 80141d6: 68f8 ldr r0, [r7, #12] 80141d8: f000 f840 bl 801425c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 80141dc: 6afb ldr r3, [r7, #44] @ 0x2c } 80141de: 4618 mov r0, r3 80141e0: 3730 adds r7, #48 @ 0x30 80141e2: 46bd mov sp, r7 80141e4: bd80 pop {r7, pc} 080141e6 : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 80141e6: b580 push {r7, lr} 80141e8: b08a sub sp, #40 @ 0x28 80141ea: af02 add r7, sp, #8 80141ec: 60f8 str r0, [r7, #12] 80141ee: 60b9 str r1, [r7, #8] 80141f0: 4613 mov r3, r2 80141f2: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 80141f4: 68fb ldr r3, [r7, #12] 80141f6: 2b00 cmp r3, #0 80141f8: d10b bne.n 8014212 __asm volatile 80141fa: f04f 0350 mov.w r3, #80 @ 0x50 80141fe: f383 8811 msr BASEPRI, r3 8014202: f3bf 8f6f isb sy 8014206: f3bf 8f4f dsb sy 801420a: 613b str r3, [r7, #16] } 801420c: bf00 nop 801420e: bf00 nop 8014210: e7fd b.n 801420e /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014212: 68fb ldr r3, [r7, #12] 8014214: 68ba ldr r2, [r7, #8] 8014216: fb02 f303 mul.w r3, r2, r3 801421a: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 801421c: 69fb ldr r3, [r7, #28] 801421e: 3350 adds r3, #80 @ 0x50 8014220: 4618 mov r0, r3 8014222: f003 f993 bl 801754c 8014226: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 8014228: 69bb ldr r3, [r7, #24] 801422a: 2b00 cmp r3, #0 801422c: d011 beq.n 8014252 { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 801422e: 69bb ldr r3, [r7, #24] 8014230: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014232: 697b ldr r3, [r7, #20] 8014234: 3350 adds r3, #80 @ 0x50 8014236: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8014238: 69bb ldr r3, [r7, #24] 801423a: 2200 movs r2, #0 801423c: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014240: 79fa ldrb r2, [r7, #7] 8014242: 69bb ldr r3, [r7, #24] 8014244: 9300 str r3, [sp, #0] 8014246: 4613 mov r3, r2 8014248: 697a ldr r2, [r7, #20] 801424a: 68b9 ldr r1, [r7, #8] 801424c: 68f8 ldr r0, [r7, #12] 801424e: f000 f805 bl 801425c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014252: 69bb ldr r3, [r7, #24] } 8014254: 4618 mov r0, r3 8014256: 3720 adds r7, #32 8014258: 46bd mov sp, r7 801425a: bd80 pop {r7, pc} 0801425c : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 801425c: b580 push {r7, lr} 801425e: b084 sub sp, #16 8014260: af00 add r7, sp, #0 8014262: 60f8 str r0, [r7, #12] 8014264: 60b9 str r1, [r7, #8] 8014266: 607a str r2, [r7, #4] 8014268: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 801426a: 68bb ldr r3, [r7, #8] 801426c: 2b00 cmp r3, #0 801426e: d103 bne.n 8014278 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8014270: 69bb ldr r3, [r7, #24] 8014272: 69ba ldr r2, [r7, #24] 8014274: 601a str r2, [r3, #0] 8014276: e002 b.n 801427e } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8014278: 69bb ldr r3, [r7, #24] 801427a: 687a ldr r2, [r7, #4] 801427c: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 801427e: 69bb ldr r3, [r7, #24] 8014280: 68fa ldr r2, [r7, #12] 8014282: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8014284: 69bb ldr r3, [r7, #24] 8014286: 68ba ldr r2, [r7, #8] 8014288: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 801428a: 2101 movs r1, #1 801428c: 69b8 ldr r0, [r7, #24] 801428e: f7ff fec3 bl 8014018 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8014292: 69bb ldr r3, [r7, #24] 8014294: 78fa ldrb r2, [r7, #3] 8014296: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 801429a: bf00 nop 801429c: 3710 adds r7, #16 801429e: 46bd mov sp, r7 80142a0: bd80 pop {r7, pc} 080142a2 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 80142a2: b580 push {r7, lr} 80142a4: b082 sub sp, #8 80142a6: af00 add r7, sp, #0 80142a8: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 80142aa: 687b ldr r3, [r7, #4] 80142ac: 2b00 cmp r3, #0 80142ae: d00e beq.n 80142ce { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 80142b0: 687b ldr r3, [r7, #4] 80142b2: 2200 movs r2, #0 80142b4: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 80142b6: 687b ldr r3, [r7, #4] 80142b8: 2200 movs r2, #0 80142ba: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 80142bc: 687b ldr r3, [r7, #4] 80142be: 2200 movs r2, #0 80142c0: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 80142c2: 2300 movs r3, #0 80142c4: 2200 movs r2, #0 80142c6: 2100 movs r1, #0 80142c8: 6878 ldr r0, [r7, #4] 80142ca: f000 f8a3 bl 8014414 } else { traceCREATE_MUTEX_FAILED(); } } 80142ce: bf00 nop 80142d0: 3708 adds r7, #8 80142d2: 46bd mov sp, r7 80142d4: bd80 pop {r7, pc} 080142d6 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 80142d6: b580 push {r7, lr} 80142d8: b086 sub sp, #24 80142da: af00 add r7, sp, #0 80142dc: 4603 mov r3, r0 80142de: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 80142e0: 2301 movs r3, #1 80142e2: 617b str r3, [r7, #20] 80142e4: 2300 movs r3, #0 80142e6: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 80142e8: 79fb ldrb r3, [r7, #7] 80142ea: 461a mov r2, r3 80142ec: 6939 ldr r1, [r7, #16] 80142ee: 6978 ldr r0, [r7, #20] 80142f0: f7ff ff79 bl 80141e6 80142f4: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 80142f6: 68f8 ldr r0, [r7, #12] 80142f8: f7ff ffd3 bl 80142a2 return xNewQueue; 80142fc: 68fb ldr r3, [r7, #12] } 80142fe: 4618 mov r0, r3 8014300: 3718 adds r7, #24 8014302: 46bd mov sp, r7 8014304: bd80 pop {r7, pc} 08014306 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 8014306: b580 push {r7, lr} 8014308: b088 sub sp, #32 801430a: af02 add r7, sp, #8 801430c: 4603 mov r3, r0 801430e: 6039 str r1, [r7, #0] 8014310: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014312: 2301 movs r3, #1 8014314: 617b str r3, [r7, #20] 8014316: 2300 movs r3, #0 8014318: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 801431a: 79fb ldrb r3, [r7, #7] 801431c: 9300 str r3, [sp, #0] 801431e: 683b ldr r3, [r7, #0] 8014320: 2200 movs r2, #0 8014322: 6939 ldr r1, [r7, #16] 8014324: 6978 ldr r0, [r7, #20] 8014326: f7ff fee1 bl 80140ec 801432a: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 801432c: 68f8 ldr r0, [r7, #12] 801432e: f7ff ffb8 bl 80142a2 return xNewQueue; 8014332: 68fb ldr r3, [r7, #12] } 8014334: 4618 mov r0, r3 8014336: 3718 adds r7, #24 8014338: 46bd mov sp, r7 801433a: bd80 pop {r7, pc} 0801433c : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 801433c: b590 push {r4, r7, lr} 801433e: b087 sub sp, #28 8014340: af00 add r7, sp, #0 8014342: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014344: 687b ldr r3, [r7, #4] 8014346: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014348: 693b ldr r3, [r7, #16] 801434a: 2b00 cmp r3, #0 801434c: d10b bne.n 8014366 __asm volatile 801434e: f04f 0350 mov.w r3, #80 @ 0x50 8014352: f383 8811 msr BASEPRI, r3 8014356: f3bf 8f6f isb sy 801435a: f3bf 8f4f dsb sy 801435e: 60fb str r3, [r7, #12] } 8014360: bf00 nop 8014362: bf00 nop 8014364: e7fd b.n 8014362 change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014366: 693b ldr r3, [r7, #16] 8014368: 689c ldr r4, [r3, #8] 801436a: f001 fe39 bl 8015fe0 801436e: 4603 mov r3, r0 8014370: 429c cmp r4, r3 8014372: d111 bne.n 8014398 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8014374: 693b ldr r3, [r7, #16] 8014376: 68db ldr r3, [r3, #12] 8014378: 1e5a subs r2, r3, #1 801437a: 693b ldr r3, [r7, #16] 801437c: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 801437e: 693b ldr r3, [r7, #16] 8014380: 68db ldr r3, [r3, #12] 8014382: 2b00 cmp r3, #0 8014384: d105 bne.n 8014392 { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8014386: 2300 movs r3, #0 8014388: 2200 movs r2, #0 801438a: 2100 movs r1, #0 801438c: 6938 ldr r0, [r7, #16] 801438e: f000 f841 bl 8014414 else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8014392: 2301 movs r3, #1 8014394: 617b str r3, [r7, #20] 8014396: e001 b.n 801439c } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 8014398: 2300 movs r3, #0 801439a: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 801439c: 697b ldr r3, [r7, #20] } 801439e: 4618 mov r0, r3 80143a0: 371c adds r7, #28 80143a2: 46bd mov sp, r7 80143a4: bd90 pop {r4, r7, pc} 080143a6 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 80143a6: b590 push {r4, r7, lr} 80143a8: b087 sub sp, #28 80143aa: af00 add r7, sp, #0 80143ac: 6078 str r0, [r7, #4] 80143ae: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 80143b0: 687b ldr r3, [r7, #4] 80143b2: 613b str r3, [r7, #16] configASSERT( pxMutex ); 80143b4: 693b ldr r3, [r7, #16] 80143b6: 2b00 cmp r3, #0 80143b8: d10b bne.n 80143d2 __asm volatile 80143ba: f04f 0350 mov.w r3, #80 @ 0x50 80143be: f383 8811 msr BASEPRI, r3 80143c2: f3bf 8f6f isb sy 80143c6: f3bf 8f4f dsb sy 80143ca: 60fb str r3, [r7, #12] } 80143cc: bf00 nop 80143ce: bf00 nop 80143d0: e7fd b.n 80143ce /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 80143d2: 693b ldr r3, [r7, #16] 80143d4: 689c ldr r4, [r3, #8] 80143d6: f001 fe03 bl 8015fe0 80143da: 4603 mov r3, r0 80143dc: 429c cmp r4, r3 80143de: d107 bne.n 80143f0 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 80143e0: 693b ldr r3, [r7, #16] 80143e2: 68db ldr r3, [r3, #12] 80143e4: 1c5a adds r2, r3, #1 80143e6: 693b ldr r3, [r7, #16] 80143e8: 60da str r2, [r3, #12] xReturn = pdPASS; 80143ea: 2301 movs r3, #1 80143ec: 617b str r3, [r7, #20] 80143ee: e00c b.n 801440a } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 80143f0: 6839 ldr r1, [r7, #0] 80143f2: 6938 ldr r0, [r7, #16] 80143f4: f000 fa90 bl 8014918 80143f8: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 80143fa: 697b ldr r3, [r7, #20] 80143fc: 2b00 cmp r3, #0 80143fe: d004 beq.n 801440a { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014400: 693b ldr r3, [r7, #16] 8014402: 68db ldr r3, [r3, #12] 8014404: 1c5a adds r2, r3, #1 8014406: 693b ldr r3, [r7, #16] 8014408: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 801440a: 697b ldr r3, [r7, #20] } 801440c: 4618 mov r0, r3 801440e: 371c adds r7, #28 8014410: 46bd mov sp, r7 8014412: bd90 pop {r4, r7, pc} 08014414 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8014414: b580 push {r7, lr} 8014416: b08e sub sp, #56 @ 0x38 8014418: af00 add r7, sp, #0 801441a: 60f8 str r0, [r7, #12] 801441c: 60b9 str r1, [r7, #8] 801441e: 607a str r2, [r7, #4] 8014420: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8014422: 2300 movs r3, #0 8014424: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014426: 68fb ldr r3, [r7, #12] 8014428: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 801442a: 6b3b ldr r3, [r7, #48] @ 0x30 801442c: 2b00 cmp r3, #0 801442e: d10b bne.n 8014448 __asm volatile 8014430: f04f 0350 mov.w r3, #80 @ 0x50 8014434: f383 8811 msr BASEPRI, r3 8014438: f3bf 8f6f isb sy 801443c: f3bf 8f4f dsb sy 8014440: 62bb str r3, [r7, #40] @ 0x28 } 8014442: bf00 nop 8014444: bf00 nop 8014446: e7fd b.n 8014444 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014448: 68bb ldr r3, [r7, #8] 801444a: 2b00 cmp r3, #0 801444c: d103 bne.n 8014456 801444e: 6b3b ldr r3, [r7, #48] @ 0x30 8014450: 6c1b ldr r3, [r3, #64] @ 0x40 8014452: 2b00 cmp r3, #0 8014454: d101 bne.n 801445a 8014456: 2301 movs r3, #1 8014458: e000 b.n 801445c 801445a: 2300 movs r3, #0 801445c: 2b00 cmp r3, #0 801445e: d10b bne.n 8014478 __asm volatile 8014460: f04f 0350 mov.w r3, #80 @ 0x50 8014464: f383 8811 msr BASEPRI, r3 8014468: f3bf 8f6f isb sy 801446c: f3bf 8f4f dsb sy 8014470: 627b str r3, [r7, #36] @ 0x24 } 8014472: bf00 nop 8014474: bf00 nop 8014476: e7fd b.n 8014474 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014478: 683b ldr r3, [r7, #0] 801447a: 2b02 cmp r3, #2 801447c: d103 bne.n 8014486 801447e: 6b3b ldr r3, [r7, #48] @ 0x30 8014480: 6bdb ldr r3, [r3, #60] @ 0x3c 8014482: 2b01 cmp r3, #1 8014484: d101 bne.n 801448a 8014486: 2301 movs r3, #1 8014488: e000 b.n 801448c 801448a: 2300 movs r3, #0 801448c: 2b00 cmp r3, #0 801448e: d10b bne.n 80144a8 __asm volatile 8014490: f04f 0350 mov.w r3, #80 @ 0x50 8014494: f383 8811 msr BASEPRI, r3 8014498: f3bf 8f6f isb sy 801449c: f3bf 8f4f dsb sy 80144a0: 623b str r3, [r7, #32] } 80144a2: bf00 nop 80144a4: bf00 nop 80144a6: e7fd b.n 80144a4 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80144a8: f001 fdaa bl 8016000 80144ac: 4603 mov r3, r0 80144ae: 2b00 cmp r3, #0 80144b0: d102 bne.n 80144b8 80144b2: 687b ldr r3, [r7, #4] 80144b4: 2b00 cmp r3, #0 80144b6: d101 bne.n 80144bc 80144b8: 2301 movs r3, #1 80144ba: e000 b.n 80144be 80144bc: 2300 movs r3, #0 80144be: 2b00 cmp r3, #0 80144c0: d10b bne.n 80144da __asm volatile 80144c2: f04f 0350 mov.w r3, #80 @ 0x50 80144c6: f383 8811 msr BASEPRI, r3 80144ca: f3bf 8f6f isb sy 80144ce: f3bf 8f4f dsb sy 80144d2: 61fb str r3, [r7, #28] } 80144d4: bf00 nop 80144d6: bf00 nop 80144d8: e7fd b.n 80144d6 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80144da: f002 ff15 bl 8017308 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80144de: 6b3b ldr r3, [r7, #48] @ 0x30 80144e0: 6b9a ldr r2, [r3, #56] @ 0x38 80144e2: 6b3b ldr r3, [r7, #48] @ 0x30 80144e4: 6bdb ldr r3, [r3, #60] @ 0x3c 80144e6: 429a cmp r2, r3 80144e8: d302 bcc.n 80144f0 80144ea: 683b ldr r3, [r7, #0] 80144ec: 2b02 cmp r3, #2 80144ee: d129 bne.n 8014544 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80144f0: 683a ldr r2, [r7, #0] 80144f2: 68b9 ldr r1, [r7, #8] 80144f4: 6b38 ldr r0, [r7, #48] @ 0x30 80144f6: f000 fbb9 bl 8014c6c 80144fa: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80144fc: 6b3b ldr r3, [r7, #48] @ 0x30 80144fe: 6a5b ldr r3, [r3, #36] @ 0x24 8014500: 2b00 cmp r3, #0 8014502: d010 beq.n 8014526 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014504: 6b3b ldr r3, [r7, #48] @ 0x30 8014506: 3324 adds r3, #36 @ 0x24 8014508: 4618 mov r0, r3 801450a: f001 fb7b bl 8015c04 801450e: 4603 mov r3, r0 8014510: 2b00 cmp r3, #0 8014512: d013 beq.n 801453c { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8014514: 4b3f ldr r3, [pc, #252] @ (8014614 ) 8014516: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801451a: 601a str r2, [r3, #0] 801451c: f3bf 8f4f dsb sy 8014520: f3bf 8f6f isb sy 8014524: e00a b.n 801453c else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8014526: 6afb ldr r3, [r7, #44] @ 0x2c 8014528: 2b00 cmp r3, #0 801452a: d007 beq.n 801453c { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 801452c: 4b39 ldr r3, [pc, #228] @ (8014614 ) 801452e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014532: 601a str r2, [r3, #0] 8014534: f3bf 8f4f dsb sy 8014538: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 801453c: f002 ff16 bl 801736c return pdPASS; 8014540: 2301 movs r3, #1 8014542: e063 b.n 801460c } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014544: 687b ldr r3, [r7, #4] 8014546: 2b00 cmp r3, #0 8014548: d103 bne.n 8014552 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 801454a: f002 ff0f bl 801736c /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 801454e: 2300 movs r3, #0 8014550: e05c b.n 801460c } else if( xEntryTimeSet == pdFALSE ) 8014552: 6b7b ldr r3, [r7, #52] @ 0x34 8014554: 2b00 cmp r3, #0 8014556: d106 bne.n 8014566 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014558: f107 0314 add.w r3, r7, #20 801455c: 4618 mov r0, r3 801455e: f001 fbdd bl 8015d1c xEntryTimeSet = pdTRUE; 8014562: 2301 movs r3, #1 8014564: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014566: f002 ff01 bl 801736c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 801456a: f001 f90f bl 801578c prvLockQueue( pxQueue ); 801456e: f002 fecb bl 8017308 8014572: 6b3b ldr r3, [r7, #48] @ 0x30 8014574: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014578: b25b sxtb r3, r3 801457a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801457e: d103 bne.n 8014588 8014580: 6b3b ldr r3, [r7, #48] @ 0x30 8014582: 2200 movs r2, #0 8014584: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014588: 6b3b ldr r3, [r7, #48] @ 0x30 801458a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801458e: b25b sxtb r3, r3 8014590: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014594: d103 bne.n 801459e 8014596: 6b3b ldr r3, [r7, #48] @ 0x30 8014598: 2200 movs r2, #0 801459a: f883 2045 strb.w r2, [r3, #69] @ 0x45 801459e: f002 fee5 bl 801736c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 80145a2: 1d3a adds r2, r7, #4 80145a4: f107 0314 add.w r3, r7, #20 80145a8: 4611 mov r1, r2 80145aa: 4618 mov r0, r3 80145ac: f001 fbcc bl 8015d48 80145b0: 4603 mov r3, r0 80145b2: 2b00 cmp r3, #0 80145b4: d124 bne.n 8014600 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 80145b6: 6b38 ldr r0, [r7, #48] @ 0x30 80145b8: f000 fc50 bl 8014e5c 80145bc: 4603 mov r3, r0 80145be: 2b00 cmp r3, #0 80145c0: d018 beq.n 80145f4 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 80145c2: 6b3b ldr r3, [r7, #48] @ 0x30 80145c4: 3310 adds r3, #16 80145c6: 687a ldr r2, [r7, #4] 80145c8: 4611 mov r1, r2 80145ca: 4618 mov r0, r3 80145cc: f001 fac8 bl 8015b60 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 80145d0: 6b38 ldr r0, [r7, #48] @ 0x30 80145d2: f000 fbdb bl 8014d8c /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 80145d6: f001 f8e7 bl 80157a8 80145da: 4603 mov r3, r0 80145dc: 2b00 cmp r3, #0 80145de: f47f af7c bne.w 80144da { portYIELD_WITHIN_API(); 80145e2: 4b0c ldr r3, [pc, #48] @ (8014614 ) 80145e4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80145e8: 601a str r2, [r3, #0] 80145ea: f3bf 8f4f dsb sy 80145ee: f3bf 8f6f isb sy 80145f2: e772 b.n 80144da } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 80145f4: 6b38 ldr r0, [r7, #48] @ 0x30 80145f6: f000 fbc9 bl 8014d8c ( void ) xTaskResumeAll(); 80145fa: f001 f8d5 bl 80157a8 80145fe: e76c b.n 80144da } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8014600: 6b38 ldr r0, [r7, #48] @ 0x30 8014602: f000 fbc3 bl 8014d8c ( void ) xTaskResumeAll(); 8014606: f001 f8cf bl 80157a8 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 801460a: 2300 movs r3, #0 } } /*lint -restore */ } 801460c: 4618 mov r0, r3 801460e: 3738 adds r7, #56 @ 0x38 8014610: 46bd mov sp, r7 8014612: bd80 pop {r7, pc} 8014614: e000ed04 .word 0xe000ed04 08014618 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8014618: b580 push {r7, lr} 801461a: b090 sub sp, #64 @ 0x40 801461c: af00 add r7, sp, #0 801461e: 60f8 str r0, [r7, #12] 8014620: 60b9 str r1, [r7, #8] 8014622: 607a str r2, [r7, #4] 8014624: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014626: 68fb ldr r3, [r7, #12] 8014628: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 801462a: 6bbb ldr r3, [r7, #56] @ 0x38 801462c: 2b00 cmp r3, #0 801462e: d10b bne.n 8014648 __asm volatile 8014630: f04f 0350 mov.w r3, #80 @ 0x50 8014634: f383 8811 msr BASEPRI, r3 8014638: f3bf 8f6f isb sy 801463c: f3bf 8f4f dsb sy 8014640: 62bb str r3, [r7, #40] @ 0x28 } 8014642: bf00 nop 8014644: bf00 nop 8014646: e7fd b.n 8014644 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014648: 68bb ldr r3, [r7, #8] 801464a: 2b00 cmp r3, #0 801464c: d103 bne.n 8014656 801464e: 6bbb ldr r3, [r7, #56] @ 0x38 8014650: 6c1b ldr r3, [r3, #64] @ 0x40 8014652: 2b00 cmp r3, #0 8014654: d101 bne.n 801465a 8014656: 2301 movs r3, #1 8014658: e000 b.n 801465c 801465a: 2300 movs r3, #0 801465c: 2b00 cmp r3, #0 801465e: d10b bne.n 8014678 __asm volatile 8014660: f04f 0350 mov.w r3, #80 @ 0x50 8014664: f383 8811 msr BASEPRI, r3 8014668: f3bf 8f6f isb sy 801466c: f3bf 8f4f dsb sy 8014670: 627b str r3, [r7, #36] @ 0x24 } 8014672: bf00 nop 8014674: bf00 nop 8014676: e7fd b.n 8014674 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014678: 683b ldr r3, [r7, #0] 801467a: 2b02 cmp r3, #2 801467c: d103 bne.n 8014686 801467e: 6bbb ldr r3, [r7, #56] @ 0x38 8014680: 6bdb ldr r3, [r3, #60] @ 0x3c 8014682: 2b01 cmp r3, #1 8014684: d101 bne.n 801468a 8014686: 2301 movs r3, #1 8014688: e000 b.n 801468c 801468a: 2300 movs r3, #0 801468c: 2b00 cmp r3, #0 801468e: d10b bne.n 80146a8 __asm volatile 8014690: f04f 0350 mov.w r3, #80 @ 0x50 8014694: f383 8811 msr BASEPRI, r3 8014698: f3bf 8f6f isb sy 801469c: f3bf 8f4f dsb sy 80146a0: 623b str r3, [r7, #32] } 80146a2: bf00 nop 80146a4: bf00 nop 80146a6: e7fd b.n 80146a4 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 80146a8: f002 ff0e bl 80174c8 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 80146ac: f3ef 8211 mrs r2, BASEPRI 80146b0: f04f 0350 mov.w r3, #80 @ 0x50 80146b4: f383 8811 msr BASEPRI, r3 80146b8: f3bf 8f6f isb sy 80146bc: f3bf 8f4f dsb sy 80146c0: 61fa str r2, [r7, #28] 80146c2: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 80146c4: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80146c6: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80146c8: 6bbb ldr r3, [r7, #56] @ 0x38 80146ca: 6b9a ldr r2, [r3, #56] @ 0x38 80146cc: 6bbb ldr r3, [r7, #56] @ 0x38 80146ce: 6bdb ldr r3, [r3, #60] @ 0x3c 80146d0: 429a cmp r2, r3 80146d2: d302 bcc.n 80146da 80146d4: 683b ldr r3, [r7, #0] 80146d6: 2b02 cmp r3, #2 80146d8: d12f bne.n 801473a { const int8_t cTxLock = pxQueue->cTxLock; 80146da: 6bbb ldr r3, [r7, #56] @ 0x38 80146dc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80146e0: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 80146e4: 6bbb ldr r3, [r7, #56] @ 0x38 80146e6: 6b9b ldr r3, [r3, #56] @ 0x38 80146e8: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80146ea: 683a ldr r2, [r7, #0] 80146ec: 68b9 ldr r1, [r7, #8] 80146ee: 6bb8 ldr r0, [r7, #56] @ 0x38 80146f0: f000 fabc bl 8014c6c /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80146f4: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 80146f8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80146fc: d112 bne.n 8014724 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80146fe: 6bbb ldr r3, [r7, #56] @ 0x38 8014700: 6a5b ldr r3, [r3, #36] @ 0x24 8014702: 2b00 cmp r3, #0 8014704: d016 beq.n 8014734 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014706: 6bbb ldr r3, [r7, #56] @ 0x38 8014708: 3324 adds r3, #36 @ 0x24 801470a: 4618 mov r0, r3 801470c: f001 fa7a bl 8015c04 8014710: 4603 mov r3, r0 8014712: 2b00 cmp r3, #0 8014714: d00e beq.n 8014734 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 8014716: 687b ldr r3, [r7, #4] 8014718: 2b00 cmp r3, #0 801471a: d00b beq.n 8014734 { *pxHigherPriorityTaskWoken = pdTRUE; 801471c: 687b ldr r3, [r7, #4] 801471e: 2201 movs r2, #1 8014720: 601a str r2, [r3, #0] 8014722: e007 b.n 8014734 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 8014724: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8014728: 3301 adds r3, #1 801472a: b2db uxtb r3, r3 801472c: b25a sxtb r2, r3 801472e: 6bbb ldr r3, [r7, #56] @ 0x38 8014730: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8014734: 2301 movs r3, #1 8014736: 63fb str r3, [r7, #60] @ 0x3c { 8014738: e001 b.n 801473e } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 801473a: 2300 movs r3, #0 801473c: 63fb str r3, [r7, #60] @ 0x3c 801473e: 6b7b ldr r3, [r7, #52] @ 0x34 8014740: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8014742: 697b ldr r3, [r7, #20] 8014744: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 8014748: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801474a: 6bfb ldr r3, [r7, #60] @ 0x3c } 801474c: 4618 mov r0, r3 801474e: 3740 adds r7, #64 @ 0x40 8014750: 46bd mov sp, r7 8014752: bd80 pop {r7, pc} 08014754 : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 8014754: b580 push {r7, lr} 8014756: b08c sub sp, #48 @ 0x30 8014758: af00 add r7, sp, #0 801475a: 60f8 str r0, [r7, #12] 801475c: 60b9 str r1, [r7, #8] 801475e: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 8014760: 2300 movs r3, #0 8014762: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014764: 68fb ldr r3, [r7, #12] 8014766: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8014768: 6abb ldr r3, [r7, #40] @ 0x28 801476a: 2b00 cmp r3, #0 801476c: d10b bne.n 8014786 __asm volatile 801476e: f04f 0350 mov.w r3, #80 @ 0x50 8014772: f383 8811 msr BASEPRI, r3 8014776: f3bf 8f6f isb sy 801477a: f3bf 8f4f dsb sy 801477e: 623b str r3, [r7, #32] } 8014780: bf00 nop 8014782: bf00 nop 8014784: e7fd b.n 8014782 /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014786: 68bb ldr r3, [r7, #8] 8014788: 2b00 cmp r3, #0 801478a: d103 bne.n 8014794 801478c: 6abb ldr r3, [r7, #40] @ 0x28 801478e: 6c1b ldr r3, [r3, #64] @ 0x40 8014790: 2b00 cmp r3, #0 8014792: d101 bne.n 8014798 8014794: 2301 movs r3, #1 8014796: e000 b.n 801479a 8014798: 2300 movs r3, #0 801479a: 2b00 cmp r3, #0 801479c: d10b bne.n 80147b6 __asm volatile 801479e: f04f 0350 mov.w r3, #80 @ 0x50 80147a2: f383 8811 msr BASEPRI, r3 80147a6: f3bf 8f6f isb sy 80147aa: f3bf 8f4f dsb sy 80147ae: 61fb str r3, [r7, #28] } 80147b0: bf00 nop 80147b2: bf00 nop 80147b4: e7fd b.n 80147b2 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 80147b6: f001 fc23 bl 8016000 80147ba: 4603 mov r3, r0 80147bc: 2b00 cmp r3, #0 80147be: d102 bne.n 80147c6 80147c0: 687b ldr r3, [r7, #4] 80147c2: 2b00 cmp r3, #0 80147c4: d101 bne.n 80147ca 80147c6: 2301 movs r3, #1 80147c8: e000 b.n 80147cc 80147ca: 2300 movs r3, #0 80147cc: 2b00 cmp r3, #0 80147ce: d10b bne.n 80147e8 __asm volatile 80147d0: f04f 0350 mov.w r3, #80 @ 0x50 80147d4: f383 8811 msr BASEPRI, r3 80147d8: f3bf 8f6f isb sy 80147dc: f3bf 8f4f dsb sy 80147e0: 61bb str r3, [r7, #24] } 80147e2: bf00 nop 80147e4: bf00 nop 80147e6: e7fd b.n 80147e4 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80147e8: f002 fd8e bl 8017308 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80147ec: 6abb ldr r3, [r7, #40] @ 0x28 80147ee: 6b9b ldr r3, [r3, #56] @ 0x38 80147f0: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80147f2: 6a7b ldr r3, [r7, #36] @ 0x24 80147f4: 2b00 cmp r3, #0 80147f6: d01f beq.n 8014838 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 80147f8: 68b9 ldr r1, [r7, #8] 80147fa: 6ab8 ldr r0, [r7, #40] @ 0x28 80147fc: f000 faa0 bl 8014d40 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8014800: 6a7b ldr r3, [r7, #36] @ 0x24 8014802: 1e5a subs r2, r3, #1 8014804: 6abb ldr r3, [r7, #40] @ 0x28 8014806: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014808: 6abb ldr r3, [r7, #40] @ 0x28 801480a: 691b ldr r3, [r3, #16] 801480c: 2b00 cmp r3, #0 801480e: d00f beq.n 8014830 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014810: 6abb ldr r3, [r7, #40] @ 0x28 8014812: 3310 adds r3, #16 8014814: 4618 mov r0, r3 8014816: f001 f9f5 bl 8015c04 801481a: 4603 mov r3, r0 801481c: 2b00 cmp r3, #0 801481e: d007 beq.n 8014830 { queueYIELD_IF_USING_PREEMPTION(); 8014820: 4b3c ldr r3, [pc, #240] @ (8014914 ) 8014822: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014826: 601a str r2, [r3, #0] 8014828: f3bf 8f4f dsb sy 801482c: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8014830: f002 fd9c bl 801736c return pdPASS; 8014834: 2301 movs r3, #1 8014836: e069 b.n 801490c } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014838: 687b ldr r3, [r7, #4] 801483a: 2b00 cmp r3, #0 801483c: d103 bne.n 8014846 { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 801483e: f002 fd95 bl 801736c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014842: 2300 movs r3, #0 8014844: e062 b.n 801490c } else if( xEntryTimeSet == pdFALSE ) 8014846: 6afb ldr r3, [r7, #44] @ 0x2c 8014848: 2b00 cmp r3, #0 801484a: d106 bne.n 801485a { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801484c: f107 0310 add.w r3, r7, #16 8014850: 4618 mov r0, r3 8014852: f001 fa63 bl 8015d1c xEntryTimeSet = pdTRUE; 8014856: 2301 movs r3, #1 8014858: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 801485a: f002 fd87 bl 801736c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 801485e: f000 ff95 bl 801578c prvLockQueue( pxQueue ); 8014862: f002 fd51 bl 8017308 8014866: 6abb ldr r3, [r7, #40] @ 0x28 8014868: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801486c: b25b sxtb r3, r3 801486e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014872: d103 bne.n 801487c 8014874: 6abb ldr r3, [r7, #40] @ 0x28 8014876: 2200 movs r2, #0 8014878: f883 2044 strb.w r2, [r3, #68] @ 0x44 801487c: 6abb ldr r3, [r7, #40] @ 0x28 801487e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014882: b25b sxtb r3, r3 8014884: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014888: d103 bne.n 8014892 801488a: 6abb ldr r3, [r7, #40] @ 0x28 801488c: 2200 movs r2, #0 801488e: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014892: f002 fd6b bl 801736c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014896: 1d3a adds r2, r7, #4 8014898: f107 0310 add.w r3, r7, #16 801489c: 4611 mov r1, r2 801489e: 4618 mov r0, r3 80148a0: f001 fa52 bl 8015d48 80148a4: 4603 mov r3, r0 80148a6: 2b00 cmp r3, #0 80148a8: d123 bne.n 80148f2 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80148aa: 6ab8 ldr r0, [r7, #40] @ 0x28 80148ac: f000 fac0 bl 8014e30 80148b0: 4603 mov r3, r0 80148b2: 2b00 cmp r3, #0 80148b4: d017 beq.n 80148e6 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 80148b6: 6abb ldr r3, [r7, #40] @ 0x28 80148b8: 3324 adds r3, #36 @ 0x24 80148ba: 687a ldr r2, [r7, #4] 80148bc: 4611 mov r1, r2 80148be: 4618 mov r0, r3 80148c0: f001 f94e bl 8015b60 prvUnlockQueue( pxQueue ); 80148c4: 6ab8 ldr r0, [r7, #40] @ 0x28 80148c6: f000 fa61 bl 8014d8c if( xTaskResumeAll() == pdFALSE ) 80148ca: f000 ff6d bl 80157a8 80148ce: 4603 mov r3, r0 80148d0: 2b00 cmp r3, #0 80148d2: d189 bne.n 80147e8 { portYIELD_WITHIN_API(); 80148d4: 4b0f ldr r3, [pc, #60] @ (8014914 ) 80148d6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80148da: 601a str r2, [r3, #0] 80148dc: f3bf 8f4f dsb sy 80148e0: f3bf 8f6f isb sy 80148e4: e780 b.n 80147e8 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 80148e6: 6ab8 ldr r0, [r7, #40] @ 0x28 80148e8: f000 fa50 bl 8014d8c ( void ) xTaskResumeAll(); 80148ec: f000 ff5c bl 80157a8 80148f0: e77a b.n 80147e8 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 80148f2: 6ab8 ldr r0, [r7, #40] @ 0x28 80148f4: f000 fa4a bl 8014d8c ( void ) xTaskResumeAll(); 80148f8: f000 ff56 bl 80157a8 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80148fc: 6ab8 ldr r0, [r7, #40] @ 0x28 80148fe: f000 fa97 bl 8014e30 8014902: 4603 mov r3, r0 8014904: 2b00 cmp r3, #0 8014906: f43f af6f beq.w 80147e8 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 801490a: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 801490c: 4618 mov r0, r3 801490e: 3730 adds r7, #48 @ 0x30 8014910: 46bd mov sp, r7 8014912: bd80 pop {r7, pc} 8014914: e000ed04 .word 0xe000ed04 08014918 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 8014918: b580 push {r7, lr} 801491a: b08e sub sp, #56 @ 0x38 801491c: af00 add r7, sp, #0 801491e: 6078 str r0, [r7, #4] 8014920: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 8014922: 2300 movs r3, #0 8014924: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014926: 687b ldr r3, [r7, #4] 8014928: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 801492a: 2300 movs r3, #0 801492c: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 801492e: 6afb ldr r3, [r7, #44] @ 0x2c 8014930: 2b00 cmp r3, #0 8014932: d10b bne.n 801494c __asm volatile 8014934: f04f 0350 mov.w r3, #80 @ 0x50 8014938: f383 8811 msr BASEPRI, r3 801493c: f3bf 8f6f isb sy 8014940: f3bf 8f4f dsb sy 8014944: 623b str r3, [r7, #32] } 8014946: bf00 nop 8014948: bf00 nop 801494a: e7fd b.n 8014948 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 801494c: 6afb ldr r3, [r7, #44] @ 0x2c 801494e: 6c1b ldr r3, [r3, #64] @ 0x40 8014950: 2b00 cmp r3, #0 8014952: d00b beq.n 801496c __asm volatile 8014954: f04f 0350 mov.w r3, #80 @ 0x50 8014958: f383 8811 msr BASEPRI, r3 801495c: f3bf 8f6f isb sy 8014960: f3bf 8f4f dsb sy 8014964: 61fb str r3, [r7, #28] } 8014966: bf00 nop 8014968: bf00 nop 801496a: e7fd b.n 8014968 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801496c: f001 fb48 bl 8016000 8014970: 4603 mov r3, r0 8014972: 2b00 cmp r3, #0 8014974: d102 bne.n 801497c 8014976: 683b ldr r3, [r7, #0] 8014978: 2b00 cmp r3, #0 801497a: d101 bne.n 8014980 801497c: 2301 movs r3, #1 801497e: e000 b.n 8014982 8014980: 2300 movs r3, #0 8014982: 2b00 cmp r3, #0 8014984: d10b bne.n 801499e __asm volatile 8014986: f04f 0350 mov.w r3, #80 @ 0x50 801498a: f383 8811 msr BASEPRI, r3 801498e: f3bf 8f6f isb sy 8014992: f3bf 8f4f dsb sy 8014996: 61bb str r3, [r7, #24] } 8014998: bf00 nop 801499a: bf00 nop 801499c: e7fd b.n 801499a /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 801499e: f002 fcb3 bl 8017308 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 80149a2: 6afb ldr r3, [r7, #44] @ 0x2c 80149a4: 6b9b ldr r3, [r3, #56] @ 0x38 80149a6: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 80149a8: 6abb ldr r3, [r7, #40] @ 0x28 80149aa: 2b00 cmp r3, #0 80149ac: d024 beq.n 80149f8 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 80149ae: 6abb ldr r3, [r7, #40] @ 0x28 80149b0: 1e5a subs r2, r3, #1 80149b2: 6afb ldr r3, [r7, #44] @ 0x2c 80149b4: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80149b6: 6afb ldr r3, [r7, #44] @ 0x2c 80149b8: 681b ldr r3, [r3, #0] 80149ba: 2b00 cmp r3, #0 80149bc: d104 bne.n 80149c8 { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 80149be: f001 fc99 bl 80162f4 80149c2: 4602 mov r2, r0 80149c4: 6afb ldr r3, [r7, #44] @ 0x2c 80149c6: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80149c8: 6afb ldr r3, [r7, #44] @ 0x2c 80149ca: 691b ldr r3, [r3, #16] 80149cc: 2b00 cmp r3, #0 80149ce: d00f beq.n 80149f0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80149d0: 6afb ldr r3, [r7, #44] @ 0x2c 80149d2: 3310 adds r3, #16 80149d4: 4618 mov r0, r3 80149d6: f001 f915 bl 8015c04 80149da: 4603 mov r3, r0 80149dc: 2b00 cmp r3, #0 80149de: d007 beq.n 80149f0 { queueYIELD_IF_USING_PREEMPTION(); 80149e0: 4b54 ldr r3, [pc, #336] @ (8014b34 ) 80149e2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80149e6: 601a str r2, [r3, #0] 80149e8: f3bf 8f4f dsb sy 80149ec: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80149f0: f002 fcbc bl 801736c return pdPASS; 80149f4: 2301 movs r3, #1 80149f6: e098 b.n 8014b2a } else { if( xTicksToWait == ( TickType_t ) 0 ) 80149f8: 683b ldr r3, [r7, #0] 80149fa: 2b00 cmp r3, #0 80149fc: d112 bne.n 8014a24 /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 80149fe: 6b3b ldr r3, [r7, #48] @ 0x30 8014a00: 2b00 cmp r3, #0 8014a02: d00b beq.n 8014a1c __asm volatile 8014a04: f04f 0350 mov.w r3, #80 @ 0x50 8014a08: f383 8811 msr BASEPRI, r3 8014a0c: f3bf 8f6f isb sy 8014a10: f3bf 8f4f dsb sy 8014a14: 617b str r3, [r7, #20] } 8014a16: bf00 nop 8014a18: bf00 nop 8014a1a: e7fd b.n 8014a18 } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 8014a1c: f002 fca6 bl 801736c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014a20: 2300 movs r3, #0 8014a22: e082 b.n 8014b2a } else if( xEntryTimeSet == pdFALSE ) 8014a24: 6b7b ldr r3, [r7, #52] @ 0x34 8014a26: 2b00 cmp r3, #0 8014a28: d106 bne.n 8014a38 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014a2a: f107 030c add.w r3, r7, #12 8014a2e: 4618 mov r0, r3 8014a30: f001 f974 bl 8015d1c xEntryTimeSet = pdTRUE; 8014a34: 2301 movs r3, #1 8014a36: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014a38: f002 fc98 bl 801736c /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 8014a3c: f000 fea6 bl 801578c prvLockQueue( pxQueue ); 8014a40: f002 fc62 bl 8017308 8014a44: 6afb ldr r3, [r7, #44] @ 0x2c 8014a46: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014a4a: b25b sxtb r3, r3 8014a4c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014a50: d103 bne.n 8014a5a 8014a52: 6afb ldr r3, [r7, #44] @ 0x2c 8014a54: 2200 movs r2, #0 8014a56: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014a5a: 6afb ldr r3, [r7, #44] @ 0x2c 8014a5c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014a60: b25b sxtb r3, r3 8014a62: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014a66: d103 bne.n 8014a70 8014a68: 6afb ldr r3, [r7, #44] @ 0x2c 8014a6a: 2200 movs r2, #0 8014a6c: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014a70: f002 fc7c bl 801736c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014a74: 463a mov r2, r7 8014a76: f107 030c add.w r3, r7, #12 8014a7a: 4611 mov r1, r2 8014a7c: 4618 mov r0, r3 8014a7e: f001 f963 bl 8015d48 8014a82: 4603 mov r3, r0 8014a84: 2b00 cmp r3, #0 8014a86: d132 bne.n 8014aee { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014a88: 6af8 ldr r0, [r7, #44] @ 0x2c 8014a8a: f000 f9d1 bl 8014e30 8014a8e: 4603 mov r3, r0 8014a90: 2b00 cmp r3, #0 8014a92: d026 beq.n 8014ae2 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8014a94: 6afb ldr r3, [r7, #44] @ 0x2c 8014a96: 681b ldr r3, [r3, #0] 8014a98: 2b00 cmp r3, #0 8014a9a: d109 bne.n 8014ab0 { taskENTER_CRITICAL(); 8014a9c: f002 fc34 bl 8017308 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 8014aa0: 6afb ldr r3, [r7, #44] @ 0x2c 8014aa2: 689b ldr r3, [r3, #8] 8014aa4: 4618 mov r0, r3 8014aa6: f001 fac9 bl 801603c 8014aaa: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 8014aac: f002 fc5e bl 801736c mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8014ab0: 6afb ldr r3, [r7, #44] @ 0x2c 8014ab2: 3324 adds r3, #36 @ 0x24 8014ab4: 683a ldr r2, [r7, #0] 8014ab6: 4611 mov r1, r2 8014ab8: 4618 mov r0, r3 8014aba: f001 f851 bl 8015b60 prvUnlockQueue( pxQueue ); 8014abe: 6af8 ldr r0, [r7, #44] @ 0x2c 8014ac0: f000 f964 bl 8014d8c if( xTaskResumeAll() == pdFALSE ) 8014ac4: f000 fe70 bl 80157a8 8014ac8: 4603 mov r3, r0 8014aca: 2b00 cmp r3, #0 8014acc: f47f af67 bne.w 801499e { portYIELD_WITHIN_API(); 8014ad0: 4b18 ldr r3, [pc, #96] @ (8014b34 ) 8014ad2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014ad6: 601a str r2, [r3, #0] 8014ad8: f3bf 8f4f dsb sy 8014adc: f3bf 8f6f isb sy 8014ae0: e75d b.n 801499e } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 8014ae2: 6af8 ldr r0, [r7, #44] @ 0x2c 8014ae4: f000 f952 bl 8014d8c ( void ) xTaskResumeAll(); 8014ae8: f000 fe5e bl 80157a8 8014aec: e757 b.n 801499e } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 8014aee: 6af8 ldr r0, [r7, #44] @ 0x2c 8014af0: f000 f94c bl 8014d8c ( void ) xTaskResumeAll(); 8014af4: f000 fe58 bl 80157a8 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8014af8: 6af8 ldr r0, [r7, #44] @ 0x2c 8014afa: f000 f999 bl 8014e30 8014afe: 4603 mov r3, r0 8014b00: 2b00 cmp r3, #0 8014b02: f43f af4c beq.w 801499e #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 8014b06: 6b3b ldr r3, [r7, #48] @ 0x30 8014b08: 2b00 cmp r3, #0 8014b0a: d00d beq.n 8014b28 { taskENTER_CRITICAL(); 8014b0c: f002 fbfc bl 8017308 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 8014b10: 6af8 ldr r0, [r7, #44] @ 0x2c 8014b12: f000 f893 bl 8014c3c 8014b16: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 8014b18: 6afb ldr r3, [r7, #44] @ 0x2c 8014b1a: 689b ldr r3, [r3, #8] 8014b1c: 6a79 ldr r1, [r7, #36] @ 0x24 8014b1e: 4618 mov r0, r3 8014b20: f001 fb64 bl 80161ec } taskEXIT_CRITICAL(); 8014b24: f002 fc22 bl 801736c } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8014b28: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8014b2a: 4618 mov r0, r3 8014b2c: 3738 adds r7, #56 @ 0x38 8014b2e: 46bd mov sp, r7 8014b30: bd80 pop {r7, pc} 8014b32: bf00 nop 8014b34: e000ed04 .word 0xe000ed04 08014b38 : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 8014b38: b580 push {r7, lr} 8014b3a: b08e sub sp, #56 @ 0x38 8014b3c: af00 add r7, sp, #0 8014b3e: 60f8 str r0, [r7, #12] 8014b40: 60b9 str r1, [r7, #8] 8014b42: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8014b44: 68fb ldr r3, [r7, #12] 8014b46: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8014b48: 6b3b ldr r3, [r7, #48] @ 0x30 8014b4a: 2b00 cmp r3, #0 8014b4c: d10b bne.n 8014b66 __asm volatile 8014b4e: f04f 0350 mov.w r3, #80 @ 0x50 8014b52: f383 8811 msr BASEPRI, r3 8014b56: f3bf 8f6f isb sy 8014b5a: f3bf 8f4f dsb sy 8014b5e: 623b str r3, [r7, #32] } 8014b60: bf00 nop 8014b62: bf00 nop 8014b64: e7fd b.n 8014b62 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014b66: 68bb ldr r3, [r7, #8] 8014b68: 2b00 cmp r3, #0 8014b6a: d103 bne.n 8014b74 8014b6c: 6b3b ldr r3, [r7, #48] @ 0x30 8014b6e: 6c1b ldr r3, [r3, #64] @ 0x40 8014b70: 2b00 cmp r3, #0 8014b72: d101 bne.n 8014b78 8014b74: 2301 movs r3, #1 8014b76: e000 b.n 8014b7a 8014b78: 2300 movs r3, #0 8014b7a: 2b00 cmp r3, #0 8014b7c: d10b bne.n 8014b96 __asm volatile 8014b7e: f04f 0350 mov.w r3, #80 @ 0x50 8014b82: f383 8811 msr BASEPRI, r3 8014b86: f3bf 8f6f isb sy 8014b8a: f3bf 8f4f dsb sy 8014b8e: 61fb str r3, [r7, #28] } 8014b90: bf00 nop 8014b92: bf00 nop 8014b94: e7fd b.n 8014b92 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8014b96: f002 fc97 bl 80174c8 __asm volatile 8014b9a: f3ef 8211 mrs r2, BASEPRI 8014b9e: f04f 0350 mov.w r3, #80 @ 0x50 8014ba2: f383 8811 msr BASEPRI, r3 8014ba6: f3bf 8f6f isb sy 8014baa: f3bf 8f4f dsb sy 8014bae: 61ba str r2, [r7, #24] 8014bb0: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 8014bb2: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8014bb4: 62fb str r3, [r7, #44] @ 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014bb6: 6b3b ldr r3, [r7, #48] @ 0x30 8014bb8: 6b9b ldr r3, [r3, #56] @ 0x38 8014bba: 62bb str r3, [r7, #40] @ 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014bbc: 6abb ldr r3, [r7, #40] @ 0x28 8014bbe: 2b00 cmp r3, #0 8014bc0: d02f beq.n 8014c22 { const int8_t cRxLock = pxQueue->cRxLock; 8014bc2: 6b3b ldr r3, [r7, #48] @ 0x30 8014bc4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014bc8: f887 3027 strb.w r3, [r7, #39] @ 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 8014bcc: 68b9 ldr r1, [r7, #8] 8014bce: 6b38 ldr r0, [r7, #48] @ 0x30 8014bd0: f000 f8b6 bl 8014d40 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 8014bd4: 6abb ldr r3, [r7, #40] @ 0x28 8014bd6: 1e5a subs r2, r3, #1 8014bd8: 6b3b ldr r3, [r7, #48] @ 0x30 8014bda: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 8014bdc: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 8014be0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014be4: d112 bne.n 8014c0c { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014be6: 6b3b ldr r3, [r7, #48] @ 0x30 8014be8: 691b ldr r3, [r3, #16] 8014bea: 2b00 cmp r3, #0 8014bec: d016 beq.n 8014c1c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014bee: 6b3b ldr r3, [r7, #48] @ 0x30 8014bf0: 3310 adds r3, #16 8014bf2: 4618 mov r0, r3 8014bf4: f001 f806 bl 8015c04 8014bf8: 4603 mov r3, r0 8014bfa: 2b00 cmp r3, #0 8014bfc: d00e beq.n 8014c1c { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 8014bfe: 687b ldr r3, [r7, #4] 8014c00: 2b00 cmp r3, #0 8014c02: d00b beq.n 8014c1c { *pxHigherPriorityTaskWoken = pdTRUE; 8014c04: 687b ldr r3, [r7, #4] 8014c06: 2201 movs r2, #1 8014c08: 601a str r2, [r3, #0] 8014c0a: e007 b.n 8014c1c } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 8014c0c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 8014c10: 3301 adds r3, #1 8014c12: b2db uxtb r3, r3 8014c14: b25a sxtb r2, r3 8014c16: 6b3b ldr r3, [r7, #48] @ 0x30 8014c18: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 8014c1c: 2301 movs r3, #1 8014c1e: 637b str r3, [r7, #52] @ 0x34 8014c20: e001 b.n 8014c26 } else { xReturn = pdFAIL; 8014c22: 2300 movs r3, #0 8014c24: 637b str r3, [r7, #52] @ 0x34 8014c26: 6afb ldr r3, [r7, #44] @ 0x2c 8014c28: 613b str r3, [r7, #16] __asm volatile 8014c2a: 693b ldr r3, [r7, #16] 8014c2c: f383 8811 msr BASEPRI, r3 } 8014c30: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8014c32: 6b7b ldr r3, [r7, #52] @ 0x34 } 8014c34: 4618 mov r0, r3 8014c36: 3738 adds r7, #56 @ 0x38 8014c38: 46bd mov sp, r7 8014c3a: bd80 pop {r7, pc} 08014c3c : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 8014c3c: b480 push {r7} 8014c3e: b085 sub sp, #20 8014c40: af00 add r7, sp, #0 8014c42: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 8014c44: 687b ldr r3, [r7, #4] 8014c46: 6a5b ldr r3, [r3, #36] @ 0x24 8014c48: 2b00 cmp r3, #0 8014c4a: d006 beq.n 8014c5a { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 8014c4c: 687b ldr r3, [r7, #4] 8014c4e: 6b1b ldr r3, [r3, #48] @ 0x30 8014c50: 681b ldr r3, [r3, #0] 8014c52: f1c3 0338 rsb r3, r3, #56 @ 0x38 8014c56: 60fb str r3, [r7, #12] 8014c58: e001 b.n 8014c5e } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 8014c5a: 2300 movs r3, #0 8014c5c: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 8014c5e: 68fb ldr r3, [r7, #12] } 8014c60: 4618 mov r0, r3 8014c62: 3714 adds r7, #20 8014c64: 46bd mov sp, r7 8014c66: f85d 7b04 ldr.w r7, [sp], #4 8014c6a: 4770 bx lr 08014c6c : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 8014c6c: b580 push {r7, lr} 8014c6e: b086 sub sp, #24 8014c70: af00 add r7, sp, #0 8014c72: 60f8 str r0, [r7, #12] 8014c74: 60b9 str r1, [r7, #8] 8014c76: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8014c78: 2300 movs r3, #0 8014c7a: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8014c7c: 68fb ldr r3, [r7, #12] 8014c7e: 6b9b ldr r3, [r3, #56] @ 0x38 8014c80: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 8014c82: 68fb ldr r3, [r7, #12] 8014c84: 6c1b ldr r3, [r3, #64] @ 0x40 8014c86: 2b00 cmp r3, #0 8014c88: d10d bne.n 8014ca6 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8014c8a: 68fb ldr r3, [r7, #12] 8014c8c: 681b ldr r3, [r3, #0] 8014c8e: 2b00 cmp r3, #0 8014c90: d14d bne.n 8014d2e { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 8014c92: 68fb ldr r3, [r7, #12] 8014c94: 689b ldr r3, [r3, #8] 8014c96: 4618 mov r0, r3 8014c98: f001 fa38 bl 801610c 8014c9c: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 8014c9e: 68fb ldr r3, [r7, #12] 8014ca0: 2200 movs r2, #0 8014ca2: 609a str r2, [r3, #8] 8014ca4: e043 b.n 8014d2e mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8014ca6: 687b ldr r3, [r7, #4] 8014ca8: 2b00 cmp r3, #0 8014caa: d119 bne.n 8014ce0 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8014cac: 68fb ldr r3, [r7, #12] 8014cae: 6858 ldr r0, [r3, #4] 8014cb0: 68fb ldr r3, [r7, #12] 8014cb2: 6c1b ldr r3, [r3, #64] @ 0x40 8014cb4: 461a mov r2, r3 8014cb6: 68b9 ldr r1, [r7, #8] 8014cb8: f003 f81f bl 8017cfa pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8014cbc: 68fb ldr r3, [r7, #12] 8014cbe: 685a ldr r2, [r3, #4] 8014cc0: 68fb ldr r3, [r7, #12] 8014cc2: 6c1b ldr r3, [r3, #64] @ 0x40 8014cc4: 441a add r2, r3 8014cc6: 68fb ldr r3, [r7, #12] 8014cc8: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8014cca: 68fb ldr r3, [r7, #12] 8014ccc: 685a ldr r2, [r3, #4] 8014cce: 68fb ldr r3, [r7, #12] 8014cd0: 689b ldr r3, [r3, #8] 8014cd2: 429a cmp r2, r3 8014cd4: d32b bcc.n 8014d2e { pxQueue->pcWriteTo = pxQueue->pcHead; 8014cd6: 68fb ldr r3, [r7, #12] 8014cd8: 681a ldr r2, [r3, #0] 8014cda: 68fb ldr r3, [r7, #12] 8014cdc: 605a str r2, [r3, #4] 8014cde: e026 b.n 8014d2e mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 8014ce0: 68fb ldr r3, [r7, #12] 8014ce2: 68d8 ldr r0, [r3, #12] 8014ce4: 68fb ldr r3, [r7, #12] 8014ce6: 6c1b ldr r3, [r3, #64] @ 0x40 8014ce8: 461a mov r2, r3 8014cea: 68b9 ldr r1, [r7, #8] 8014cec: f003 f805 bl 8017cfa pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 8014cf0: 68fb ldr r3, [r7, #12] 8014cf2: 68da ldr r2, [r3, #12] 8014cf4: 68fb ldr r3, [r7, #12] 8014cf6: 6c1b ldr r3, [r3, #64] @ 0x40 8014cf8: 425b negs r3, r3 8014cfa: 441a add r2, r3 8014cfc: 68fb ldr r3, [r7, #12] 8014cfe: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8014d00: 68fb ldr r3, [r7, #12] 8014d02: 68da ldr r2, [r3, #12] 8014d04: 68fb ldr r3, [r7, #12] 8014d06: 681b ldr r3, [r3, #0] 8014d08: 429a cmp r2, r3 8014d0a: d207 bcs.n 8014d1c { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 8014d0c: 68fb ldr r3, [r7, #12] 8014d0e: 689a ldr r2, [r3, #8] 8014d10: 68fb ldr r3, [r7, #12] 8014d12: 6c1b ldr r3, [r3, #64] @ 0x40 8014d14: 425b negs r3, r3 8014d16: 441a add r2, r3 8014d18: 68fb ldr r3, [r7, #12] 8014d1a: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8014d1c: 687b ldr r3, [r7, #4] 8014d1e: 2b02 cmp r3, #2 8014d20: d105 bne.n 8014d2e { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8014d22: 693b ldr r3, [r7, #16] 8014d24: 2b00 cmp r3, #0 8014d26: d002 beq.n 8014d2e { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8014d28: 693b ldr r3, [r7, #16] 8014d2a: 3b01 subs r3, #1 8014d2c: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8014d2e: 693b ldr r3, [r7, #16] 8014d30: 1c5a adds r2, r3, #1 8014d32: 68fb ldr r3, [r7, #12] 8014d34: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8014d36: 697b ldr r3, [r7, #20] } 8014d38: 4618 mov r0, r3 8014d3a: 3718 adds r7, #24 8014d3c: 46bd mov sp, r7 8014d3e: bd80 pop {r7, pc} 08014d40 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8014d40: b580 push {r7, lr} 8014d42: b082 sub sp, #8 8014d44: af00 add r7, sp, #0 8014d46: 6078 str r0, [r7, #4] 8014d48: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 8014d4a: 687b ldr r3, [r7, #4] 8014d4c: 6c1b ldr r3, [r3, #64] @ 0x40 8014d4e: 2b00 cmp r3, #0 8014d50: d018 beq.n 8014d84 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8014d52: 687b ldr r3, [r7, #4] 8014d54: 68da ldr r2, [r3, #12] 8014d56: 687b ldr r3, [r7, #4] 8014d58: 6c1b ldr r3, [r3, #64] @ 0x40 8014d5a: 441a add r2, r3 8014d5c: 687b ldr r3, [r7, #4] 8014d5e: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8014d60: 687b ldr r3, [r7, #4] 8014d62: 68da ldr r2, [r3, #12] 8014d64: 687b ldr r3, [r7, #4] 8014d66: 689b ldr r3, [r3, #8] 8014d68: 429a cmp r2, r3 8014d6a: d303 bcc.n 8014d74 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 8014d6c: 687b ldr r3, [r7, #4] 8014d6e: 681a ldr r2, [r3, #0] 8014d70: 687b ldr r3, [r7, #4] 8014d72: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8014d74: 687b ldr r3, [r7, #4] 8014d76: 68d9 ldr r1, [r3, #12] 8014d78: 687b ldr r3, [r7, #4] 8014d7a: 6c1b ldr r3, [r3, #64] @ 0x40 8014d7c: 461a mov r2, r3 8014d7e: 6838 ldr r0, [r7, #0] 8014d80: f002 ffbb bl 8017cfa } } 8014d84: bf00 nop 8014d86: 3708 adds r7, #8 8014d88: 46bd mov sp, r7 8014d8a: bd80 pop {r7, pc} 08014d8c : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 8014d8c: b580 push {r7, lr} 8014d8e: b084 sub sp, #16 8014d90: af00 add r7, sp, #0 8014d92: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 8014d94: f002 fab8 bl 8017308 { int8_t cTxLock = pxQueue->cTxLock; 8014d98: 687b ldr r3, [r7, #4] 8014d9a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014d9e: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8014da0: e011 b.n 8014dc6 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014da2: 687b ldr r3, [r7, #4] 8014da4: 6a5b ldr r3, [r3, #36] @ 0x24 8014da6: 2b00 cmp r3, #0 8014da8: d012 beq.n 8014dd0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014daa: 687b ldr r3, [r7, #4] 8014dac: 3324 adds r3, #36 @ 0x24 8014dae: 4618 mov r0, r3 8014db0: f000 ff28 bl 8015c04 8014db4: 4603 mov r3, r0 8014db6: 2b00 cmp r3, #0 8014db8: d001 beq.n 8014dbe { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 8014dba: f001 f829 bl 8015e10 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 8014dbe: 7bfb ldrb r3, [r7, #15] 8014dc0: 3b01 subs r3, #1 8014dc2: b2db uxtb r3, r3 8014dc4: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8014dc6: f997 300f ldrsb.w r3, [r7, #15] 8014dca: 2b00 cmp r3, #0 8014dcc: dce9 bgt.n 8014da2 8014dce: e000 b.n 8014dd2 break; 8014dd0: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 8014dd2: 687b ldr r3, [r7, #4] 8014dd4: 22ff movs r2, #255 @ 0xff 8014dd6: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 8014dda: f002 fac7 bl 801736c /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 8014dde: f002 fa93 bl 8017308 { int8_t cRxLock = pxQueue->cRxLock; 8014de2: 687b ldr r3, [r7, #4] 8014de4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014de8: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8014dea: e011 b.n 8014e10 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014dec: 687b ldr r3, [r7, #4] 8014dee: 691b ldr r3, [r3, #16] 8014df0: 2b00 cmp r3, #0 8014df2: d012 beq.n 8014e1a { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014df4: 687b ldr r3, [r7, #4] 8014df6: 3310 adds r3, #16 8014df8: 4618 mov r0, r3 8014dfa: f000 ff03 bl 8015c04 8014dfe: 4603 mov r3, r0 8014e00: 2b00 cmp r3, #0 8014e02: d001 beq.n 8014e08 { vTaskMissedYield(); 8014e04: f001 f804 bl 8015e10 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 8014e08: 7bbb ldrb r3, [r7, #14] 8014e0a: 3b01 subs r3, #1 8014e0c: b2db uxtb r3, r3 8014e0e: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 8014e10: f997 300e ldrsb.w r3, [r7, #14] 8014e14: 2b00 cmp r3, #0 8014e16: dce9 bgt.n 8014dec 8014e18: e000 b.n 8014e1c } else { break; 8014e1a: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8014e1c: 687b ldr r3, [r7, #4] 8014e1e: 22ff movs r2, #255 @ 0xff 8014e20: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 8014e24: f002 faa2 bl 801736c } 8014e28: bf00 nop 8014e2a: 3710 adds r7, #16 8014e2c: 46bd mov sp, r7 8014e2e: bd80 pop {r7, pc} 08014e30 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 8014e30: b580 push {r7, lr} 8014e32: b084 sub sp, #16 8014e34: af00 add r7, sp, #0 8014e36: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8014e38: f002 fa66 bl 8017308 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 8014e3c: 687b ldr r3, [r7, #4] 8014e3e: 6b9b ldr r3, [r3, #56] @ 0x38 8014e40: 2b00 cmp r3, #0 8014e42: d102 bne.n 8014e4a { xReturn = pdTRUE; 8014e44: 2301 movs r3, #1 8014e46: 60fb str r3, [r7, #12] 8014e48: e001 b.n 8014e4e } else { xReturn = pdFALSE; 8014e4a: 2300 movs r3, #0 8014e4c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8014e4e: f002 fa8d bl 801736c return xReturn; 8014e52: 68fb ldr r3, [r7, #12] } 8014e54: 4618 mov r0, r3 8014e56: 3710 adds r7, #16 8014e58: 46bd mov sp, r7 8014e5a: bd80 pop {r7, pc} 08014e5c : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 8014e5c: b580 push {r7, lr} 8014e5e: b084 sub sp, #16 8014e60: af00 add r7, sp, #0 8014e62: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8014e64: f002 fa50 bl 8017308 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8014e68: 687b ldr r3, [r7, #4] 8014e6a: 6b9a ldr r2, [r3, #56] @ 0x38 8014e6c: 687b ldr r3, [r7, #4] 8014e6e: 6bdb ldr r3, [r3, #60] @ 0x3c 8014e70: 429a cmp r2, r3 8014e72: d102 bne.n 8014e7a { xReturn = pdTRUE; 8014e74: 2301 movs r3, #1 8014e76: 60fb str r3, [r7, #12] 8014e78: e001 b.n 8014e7e } else { xReturn = pdFALSE; 8014e7a: 2300 movs r3, #0 8014e7c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8014e7e: f002 fa75 bl 801736c return xReturn; 8014e82: 68fb ldr r3, [r7, #12] } 8014e84: 4618 mov r0, r3 8014e86: 3710 adds r7, #16 8014e88: 46bd mov sp, r7 8014e8a: bd80 pop {r7, pc} 08014e8c : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 8014e8c: b480 push {r7} 8014e8e: b085 sub sp, #20 8014e90: af00 add r7, sp, #0 8014e92: 6078 str r0, [r7, #4] 8014e94: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014e96: 2300 movs r3, #0 8014e98: 60fb str r3, [r7, #12] 8014e9a: e014 b.n 8014ec6 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 8014e9c: 4a0f ldr r2, [pc, #60] @ (8014edc ) 8014e9e: 68fb ldr r3, [r7, #12] 8014ea0: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8014ea4: 2b00 cmp r3, #0 8014ea6: d10b bne.n 8014ec0 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8014ea8: 490c ldr r1, [pc, #48] @ (8014edc ) 8014eaa: 68fb ldr r3, [r7, #12] 8014eac: 683a ldr r2, [r7, #0] 8014eae: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 8014eb2: 4a0a ldr r2, [pc, #40] @ (8014edc ) 8014eb4: 68fb ldr r3, [r7, #12] 8014eb6: 00db lsls r3, r3, #3 8014eb8: 4413 add r3, r2 8014eba: 687a ldr r2, [r7, #4] 8014ebc: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 8014ebe: e006 b.n 8014ece for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8014ec0: 68fb ldr r3, [r7, #12] 8014ec2: 3301 adds r3, #1 8014ec4: 60fb str r3, [r7, #12] 8014ec6: 68fb ldr r3, [r7, #12] 8014ec8: 2b07 cmp r3, #7 8014eca: d9e7 bls.n 8014e9c else { mtCOVERAGE_TEST_MARKER(); } } } 8014ecc: bf00 nop 8014ece: bf00 nop 8014ed0: 3714 adds r7, #20 8014ed2: 46bd mov sp, r7 8014ed4: f85d 7b04 ldr.w r7, [sp], #4 8014ed8: 4770 bx lr 8014eda: bf00 nop 8014edc: 24002600 .word 0x24002600 08014ee0 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8014ee0: b580 push {r7, lr} 8014ee2: b086 sub sp, #24 8014ee4: af00 add r7, sp, #0 8014ee6: 60f8 str r0, [r7, #12] 8014ee8: 60b9 str r1, [r7, #8] 8014eea: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 8014eec: 68fb ldr r3, [r7, #12] 8014eee: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 8014ef0: f002 fa0a bl 8017308 8014ef4: 697b ldr r3, [r7, #20] 8014ef6: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014efa: b25b sxtb r3, r3 8014efc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f00: d103 bne.n 8014f0a 8014f02: 697b ldr r3, [r7, #20] 8014f04: 2200 movs r2, #0 8014f06: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014f0a: 697b ldr r3, [r7, #20] 8014f0c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014f10: b25b sxtb r3, r3 8014f12: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f16: d103 bne.n 8014f20 8014f18: 697b ldr r3, [r7, #20] 8014f1a: 2200 movs r2, #0 8014f1c: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014f20: f002 fa24 bl 801736c if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8014f24: 697b ldr r3, [r7, #20] 8014f26: 6b9b ldr r3, [r3, #56] @ 0x38 8014f28: 2b00 cmp r3, #0 8014f2a: d106 bne.n 8014f3a { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8014f2c: 697b ldr r3, [r7, #20] 8014f2e: 3324 adds r3, #36 @ 0x24 8014f30: 687a ldr r2, [r7, #4] 8014f32: 68b9 ldr r1, [r7, #8] 8014f34: 4618 mov r0, r3 8014f36: f000 fe39 bl 8015bac } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8014f3a: 6978 ldr r0, [r7, #20] 8014f3c: f7ff ff26 bl 8014d8c } 8014f40: bf00 nop 8014f42: 3718 adds r7, #24 8014f44: 46bd mov sp, r7 8014f46: bd80 pop {r7, pc} 08014f48 : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 8014f48: b480 push {r7} 8014f4a: b087 sub sp, #28 8014f4c: af00 add r7, sp, #0 8014f4e: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8014f50: 687b ldr r3, [r7, #4] 8014f52: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 8014f54: 693b ldr r3, [r7, #16] 8014f56: 2b00 cmp r3, #0 8014f58: d10b bne.n 8014f72 __asm volatile 8014f5a: f04f 0350 mov.w r3, #80 @ 0x50 8014f5e: f383 8811 msr BASEPRI, r3 8014f62: f3bf 8f6f isb sy 8014f66: f3bf 8f4f dsb sy 8014f6a: 60fb str r3, [r7, #12] } 8014f6c: bf00 nop 8014f6e: bf00 nop 8014f70: e7fd b.n 8014f6e xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 8014f72: 693b ldr r3, [r7, #16] 8014f74: 689a ldr r2, [r3, #8] 8014f76: 693b ldr r3, [r7, #16] 8014f78: 681b ldr r3, [r3, #0] 8014f7a: 4413 add r3, r2 8014f7c: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 8014f7e: 693b ldr r3, [r7, #16] 8014f80: 685b ldr r3, [r3, #4] 8014f82: 697a ldr r2, [r7, #20] 8014f84: 1ad3 subs r3, r2, r3 8014f86: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 8014f88: 697b ldr r3, [r7, #20] 8014f8a: 3b01 subs r3, #1 8014f8c: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 8014f8e: 693b ldr r3, [r7, #16] 8014f90: 689b ldr r3, [r3, #8] 8014f92: 697a ldr r2, [r7, #20] 8014f94: 429a cmp r2, r3 8014f96: d304 bcc.n 8014fa2 { xSpace -= pxStreamBuffer->xLength; 8014f98: 693b ldr r3, [r7, #16] 8014f9a: 689b ldr r3, [r3, #8] 8014f9c: 697a ldr r2, [r7, #20] 8014f9e: 1ad3 subs r3, r2, r3 8014fa0: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 8014fa2: 697b ldr r3, [r7, #20] } 8014fa4: 4618 mov r0, r3 8014fa6: 371c adds r7, #28 8014fa8: 46bd mov sp, r7 8014faa: f85d 7b04 ldr.w r7, [sp], #4 8014fae: 4770 bx lr 08014fb0 : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 8014fb0: b580 push {r7, lr} 8014fb2: b090 sub sp, #64 @ 0x40 8014fb4: af02 add r7, sp, #8 8014fb6: 60f8 str r0, [r7, #12] 8014fb8: 60b9 str r1, [r7, #8] 8014fba: 607a str r2, [r7, #4] 8014fbc: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8014fbe: 68fb ldr r3, [r7, #12] 8014fc0: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 8014fc2: 2300 movs r3, #0 8014fc4: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 8014fc6: 687b ldr r3, [r7, #4] 8014fc8: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 8014fca: 68bb ldr r3, [r7, #8] 8014fcc: 2b00 cmp r3, #0 8014fce: d10b bne.n 8014fe8 __asm volatile 8014fd0: f04f 0350 mov.w r3, #80 @ 0x50 8014fd4: f383 8811 msr BASEPRI, r3 8014fd8: f3bf 8f6f isb sy 8014fdc: f3bf 8f4f dsb sy 8014fe0: 627b str r3, [r7, #36] @ 0x24 } 8014fe2: bf00 nop 8014fe4: bf00 nop 8014fe6: e7fd b.n 8014fe4 configASSERT( pxStreamBuffer ); 8014fe8: 6afb ldr r3, [r7, #44] @ 0x2c 8014fea: 2b00 cmp r3, #0 8014fec: d10b bne.n 8015006 __asm volatile 8014fee: f04f 0350 mov.w r3, #80 @ 0x50 8014ff2: f383 8811 msr BASEPRI, r3 8014ff6: f3bf 8f6f isb sy 8014ffa: f3bf 8f4f dsb sy 8014ffe: 623b str r3, [r7, #32] } 8015000: bf00 nop 8015002: bf00 nop 8015004: e7fd b.n 8015002 /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 8015006: 6afb ldr r3, [r7, #44] @ 0x2c 8015008: 7f1b ldrb r3, [r3, #28] 801500a: f003 0301 and.w r3, r3, #1 801500e: 2b00 cmp r3, #0 8015010: d012 beq.n 8015038 { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 8015012: 6b3b ldr r3, [r7, #48] @ 0x30 8015014: 3304 adds r3, #4 8015016: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 8015018: 6b3a ldr r2, [r7, #48] @ 0x30 801501a: 687b ldr r3, [r7, #4] 801501c: 429a cmp r2, r3 801501e: d80b bhi.n 8015038 __asm volatile 8015020: f04f 0350 mov.w r3, #80 @ 0x50 8015024: f383 8811 msr BASEPRI, r3 8015028: f3bf 8f6f isb sy 801502c: f3bf 8f4f dsb sy 8015030: 61fb str r3, [r7, #28] } 8015032: bf00 nop 8015034: bf00 nop 8015036: e7fd b.n 8015034 else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 8015038: 683b ldr r3, [r7, #0] 801503a: 2b00 cmp r3, #0 801503c: d03f beq.n 80150be { vTaskSetTimeOutState( &xTimeOut ); 801503e: f107 0310 add.w r3, r7, #16 8015042: 4618 mov r0, r3 8015044: f000 fe42 bl 8015ccc do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 8015048: f002 f95e bl 8017308 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 801504c: 6af8 ldr r0, [r7, #44] @ 0x2c 801504e: f7ff ff7b bl 8014f48 8015052: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 8015054: 6b7a ldr r2, [r7, #52] @ 0x34 8015056: 6b3b ldr r3, [r7, #48] @ 0x30 8015058: 429a cmp r2, r3 801505a: d218 bcs.n 801508e { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 801505c: 2000 movs r0, #0 801505e: f001 fb65 bl 801672c /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 8015062: 6afb ldr r3, [r7, #44] @ 0x2c 8015064: 695b ldr r3, [r3, #20] 8015066: 2b00 cmp r3, #0 8015068: d00b beq.n 8015082 __asm volatile 801506a: f04f 0350 mov.w r3, #80 @ 0x50 801506e: f383 8811 msr BASEPRI, r3 8015072: f3bf 8f6f isb sy 8015076: f3bf 8f4f dsb sy 801507a: 61bb str r3, [r7, #24] } 801507c: bf00 nop 801507e: bf00 nop 8015080: e7fd b.n 801507e pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 8015082: f000 ffad bl 8015fe0 8015086: 4602 mov r2, r0 8015088: 6afb ldr r3, [r7, #44] @ 0x2c 801508a: 615a str r2, [r3, #20] 801508c: e002 b.n 8015094 } else { taskEXIT_CRITICAL(); 801508e: f002 f96d bl 801736c break; 8015092: e014 b.n 80150be } } taskEXIT_CRITICAL(); 8015094: f002 f96a bl 801736c traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 8015098: 683b ldr r3, [r7, #0] 801509a: 2200 movs r2, #0 801509c: 2100 movs r1, #0 801509e: 2000 movs r0, #0 80150a0: f001 f93c bl 801631c pxStreamBuffer->xTaskWaitingToSend = NULL; 80150a4: 6afb ldr r3, [r7, #44] @ 0x2c 80150a6: 2200 movs r2, #0 80150a8: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 80150aa: 463a mov r2, r7 80150ac: f107 0310 add.w r3, r7, #16 80150b0: 4611 mov r1, r2 80150b2: 4618 mov r0, r3 80150b4: f000 fe48 bl 8015d48 80150b8: 4603 mov r3, r0 80150ba: 2b00 cmp r3, #0 80150bc: d0c4 beq.n 8015048 else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 80150be: 6b7b ldr r3, [r7, #52] @ 0x34 80150c0: 2b00 cmp r3, #0 80150c2: d103 bne.n 80150cc { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 80150c4: 6af8 ldr r0, [r7, #44] @ 0x2c 80150c6: f7ff ff3f bl 8014f48 80150ca: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 80150cc: 6b3b ldr r3, [r7, #48] @ 0x30 80150ce: 9300 str r3, [sp, #0] 80150d0: 6b7b ldr r3, [r7, #52] @ 0x34 80150d2: 687a ldr r2, [r7, #4] 80150d4: 68b9 ldr r1, [r7, #8] 80150d6: 6af8 ldr r0, [r7, #44] @ 0x2c 80150d8: f000 f823 bl 8015122 80150dc: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 80150de: 6abb ldr r3, [r7, #40] @ 0x28 80150e0: 2b00 cmp r3, #0 80150e2: d019 beq.n 8015118 { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 80150e4: 6af8 ldr r0, [r7, #44] @ 0x2c 80150e6: f000 f8ce bl 8015286 80150ea: 4602 mov r2, r0 80150ec: 6afb ldr r3, [r7, #44] @ 0x2c 80150ee: 68db ldr r3, [r3, #12] 80150f0: 429a cmp r2, r3 80150f2: d311 bcc.n 8015118 { sbSEND_COMPLETED( pxStreamBuffer ); 80150f4: f000 fb4a bl 801578c 80150f8: 6afb ldr r3, [r7, #44] @ 0x2c 80150fa: 691b ldr r3, [r3, #16] 80150fc: 2b00 cmp r3, #0 80150fe: d009 beq.n 8015114 8015100: 6afb ldr r3, [r7, #44] @ 0x2c 8015102: 6918 ldr r0, [r3, #16] 8015104: 2300 movs r3, #0 8015106: 2200 movs r2, #0 8015108: 2100 movs r1, #0 801510a: f001 f967 bl 80163dc 801510e: 6afb ldr r3, [r7, #44] @ 0x2c 8015110: 2200 movs r2, #0 8015112: 611a str r2, [r3, #16] 8015114: f000 fb48 bl 80157a8 { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 8015118: 6abb ldr r3, [r7, #40] @ 0x28 } 801511a: 4618 mov r0, r3 801511c: 3738 adds r7, #56 @ 0x38 801511e: 46bd mov sp, r7 8015120: bd80 pop {r7, pc} 08015122 : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 8015122: b580 push {r7, lr} 8015124: b086 sub sp, #24 8015126: af00 add r7, sp, #0 8015128: 60f8 str r0, [r7, #12] 801512a: 60b9 str r1, [r7, #8] 801512c: 607a str r2, [r7, #4] 801512e: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 8015130: 683b ldr r3, [r7, #0] 8015132: 2b00 cmp r3, #0 8015134: d102 bne.n 801513c { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 8015136: 2300 movs r3, #0 8015138: 617b str r3, [r7, #20] 801513a: e01d b.n 8015178 } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 801513c: 68fb ldr r3, [r7, #12] 801513e: 7f1b ldrb r3, [r3, #28] 8015140: f003 0301 and.w r3, r3, #1 8015144: 2b00 cmp r3, #0 8015146: d108 bne.n 801515a { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 8015148: 2301 movs r3, #1 801514a: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 801514c: 687a ldr r2, [r7, #4] 801514e: 683b ldr r3, [r7, #0] 8015150: 4293 cmp r3, r2 8015152: bf28 it cs 8015154: 4613 movcs r3, r2 8015156: 607b str r3, [r7, #4] 8015158: e00e b.n 8015178 } else if( xSpace >= xRequiredSpace ) 801515a: 683a ldr r2, [r7, #0] 801515c: 6a3b ldr r3, [r7, #32] 801515e: 429a cmp r2, r3 8015160: d308 bcc.n 8015174 { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 8015162: 2301 movs r3, #1 8015164: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 8015166: 1d3b adds r3, r7, #4 8015168: 2204 movs r2, #4 801516a: 4619 mov r1, r3 801516c: 68f8 ldr r0, [r7, #12] 801516e: f000 f815 bl 801519c 8015172: e001 b.n 8015178 } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 8015174: 2300 movs r3, #0 8015176: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 8015178: 697b ldr r3, [r7, #20] 801517a: 2b00 cmp r3, #0 801517c: d007 beq.n 801518e { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 801517e: 687b ldr r3, [r7, #4] 8015180: 461a mov r2, r3 8015182: 68b9 ldr r1, [r7, #8] 8015184: 68f8 ldr r0, [r7, #12] 8015186: f000 f809 bl 801519c 801518a: 6138 str r0, [r7, #16] 801518c: e001 b.n 8015192 } else { xReturn = 0; 801518e: 2300 movs r3, #0 8015190: 613b str r3, [r7, #16] } return xReturn; 8015192: 693b ldr r3, [r7, #16] } 8015194: 4618 mov r0, r3 8015196: 3718 adds r7, #24 8015198: 46bd mov sp, r7 801519a: bd80 pop {r7, pc} 0801519c : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 801519c: b580 push {r7, lr} 801519e: b08a sub sp, #40 @ 0x28 80151a0: af00 add r7, sp, #0 80151a2: 60f8 str r0, [r7, #12] 80151a4: 60b9 str r1, [r7, #8] 80151a6: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 80151a8: 687b ldr r3, [r7, #4] 80151aa: 2b00 cmp r3, #0 80151ac: d10b bne.n 80151c6 __asm volatile 80151ae: f04f 0350 mov.w r3, #80 @ 0x50 80151b2: f383 8811 msr BASEPRI, r3 80151b6: f3bf 8f6f isb sy 80151ba: f3bf 8f4f dsb sy 80151be: 61fb str r3, [r7, #28] } 80151c0: bf00 nop 80151c2: bf00 nop 80151c4: e7fd b.n 80151c2 xNextHead = pxStreamBuffer->xHead; 80151c6: 68fb ldr r3, [r7, #12] 80151c8: 685b ldr r3, [r3, #4] 80151ca: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 80151cc: 68fb ldr r3, [r7, #12] 80151ce: 689a ldr r2, [r3, #8] 80151d0: 6a7b ldr r3, [r7, #36] @ 0x24 80151d2: 1ad3 subs r3, r2, r3 80151d4: 687a ldr r2, [r7, #4] 80151d6: 4293 cmp r3, r2 80151d8: bf28 it cs 80151da: 4613 movcs r3, r2 80151dc: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 80151de: 6a7a ldr r2, [r7, #36] @ 0x24 80151e0: 6a3b ldr r3, [r7, #32] 80151e2: 441a add r2, r3 80151e4: 68fb ldr r3, [r7, #12] 80151e6: 689b ldr r3, [r3, #8] 80151e8: 429a cmp r2, r3 80151ea: d90b bls.n 8015204 __asm volatile 80151ec: f04f 0350 mov.w r3, #80 @ 0x50 80151f0: f383 8811 msr BASEPRI, r3 80151f4: f3bf 8f6f isb sy 80151f8: f3bf 8f4f dsb sy 80151fc: 61bb str r3, [r7, #24] } 80151fe: bf00 nop 8015200: bf00 nop 8015202: e7fd b.n 8015200 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015204: 68fb ldr r3, [r7, #12] 8015206: 699a ldr r2, [r3, #24] 8015208: 6a7b ldr r3, [r7, #36] @ 0x24 801520a: 4413 add r3, r2 801520c: 6a3a ldr r2, [r7, #32] 801520e: 68b9 ldr r1, [r7, #8] 8015210: 4618 mov r0, r3 8015212: f002 fd72 bl 8017cfa /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 8015216: 687a ldr r2, [r7, #4] 8015218: 6a3b ldr r3, [r7, #32] 801521a: 429a cmp r2, r3 801521c: d91d bls.n 801525a { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 801521e: 687a ldr r2, [r7, #4] 8015220: 6a3b ldr r3, [r7, #32] 8015222: 1ad2 subs r2, r2, r3 8015224: 68fb ldr r3, [r7, #12] 8015226: 689b ldr r3, [r3, #8] 8015228: 429a cmp r2, r3 801522a: d90b bls.n 8015244 __asm volatile 801522c: f04f 0350 mov.w r3, #80 @ 0x50 8015230: f383 8811 msr BASEPRI, r3 8015234: f3bf 8f6f isb sy 8015238: f3bf 8f4f dsb sy 801523c: 617b str r3, [r7, #20] } 801523e: bf00 nop 8015240: bf00 nop 8015242: e7fd b.n 8015240 ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015244: 68fb ldr r3, [r7, #12] 8015246: 6998 ldr r0, [r3, #24] 8015248: 68ba ldr r2, [r7, #8] 801524a: 6a3b ldr r3, [r7, #32] 801524c: 18d1 adds r1, r2, r3 801524e: 687a ldr r2, [r7, #4] 8015250: 6a3b ldr r3, [r7, #32] 8015252: 1ad3 subs r3, r2, r3 8015254: 461a mov r2, r3 8015256: f002 fd50 bl 8017cfa else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 801525a: 6a7a ldr r2, [r7, #36] @ 0x24 801525c: 687b ldr r3, [r7, #4] 801525e: 4413 add r3, r2 8015260: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 8015262: 68fb ldr r3, [r7, #12] 8015264: 689b ldr r3, [r3, #8] 8015266: 6a7a ldr r2, [r7, #36] @ 0x24 8015268: 429a cmp r2, r3 801526a: d304 bcc.n 8015276 { xNextHead -= pxStreamBuffer->xLength; 801526c: 68fb ldr r3, [r7, #12] 801526e: 689b ldr r3, [r3, #8] 8015270: 6a7a ldr r2, [r7, #36] @ 0x24 8015272: 1ad3 subs r3, r2, r3 8015274: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 8015276: 68fb ldr r3, [r7, #12] 8015278: 6a7a ldr r2, [r7, #36] @ 0x24 801527a: 605a str r2, [r3, #4] return xCount; 801527c: 687b ldr r3, [r7, #4] } 801527e: 4618 mov r0, r3 8015280: 3728 adds r7, #40 @ 0x28 8015282: 46bd mov sp, r7 8015284: bd80 pop {r7, pc} 08015286 : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 8015286: b480 push {r7} 8015288: b085 sub sp, #20 801528a: af00 add r7, sp, #0 801528c: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 801528e: 687b ldr r3, [r7, #4] 8015290: 689a ldr r2, [r3, #8] 8015292: 687b ldr r3, [r7, #4] 8015294: 685b ldr r3, [r3, #4] 8015296: 4413 add r3, r2 8015298: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 801529a: 687b ldr r3, [r7, #4] 801529c: 681b ldr r3, [r3, #0] 801529e: 68fa ldr r2, [r7, #12] 80152a0: 1ad3 subs r3, r2, r3 80152a2: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 80152a4: 687b ldr r3, [r7, #4] 80152a6: 689b ldr r3, [r3, #8] 80152a8: 68fa ldr r2, [r7, #12] 80152aa: 429a cmp r2, r3 80152ac: d304 bcc.n 80152b8 { xCount -= pxStreamBuffer->xLength; 80152ae: 687b ldr r3, [r7, #4] 80152b0: 689b ldr r3, [r3, #8] 80152b2: 68fa ldr r2, [r7, #12] 80152b4: 1ad3 subs r3, r2, r3 80152b6: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 80152b8: 68fb ldr r3, [r7, #12] } 80152ba: 4618 mov r0, r3 80152bc: 3714 adds r7, #20 80152be: 46bd mov sp, r7 80152c0: f85d 7b04 ldr.w r7, [sp], #4 80152c4: 4770 bx lr 080152c6 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 80152c6: b580 push {r7, lr} 80152c8: b08e sub sp, #56 @ 0x38 80152ca: af04 add r7, sp, #16 80152cc: 60f8 str r0, [r7, #12] 80152ce: 60b9 str r1, [r7, #8] 80152d0: 607a str r2, [r7, #4] 80152d2: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 80152d4: 6b7b ldr r3, [r7, #52] @ 0x34 80152d6: 2b00 cmp r3, #0 80152d8: d10b bne.n 80152f2 __asm volatile 80152da: f04f 0350 mov.w r3, #80 @ 0x50 80152de: f383 8811 msr BASEPRI, r3 80152e2: f3bf 8f6f isb sy 80152e6: f3bf 8f4f dsb sy 80152ea: 623b str r3, [r7, #32] } 80152ec: bf00 nop 80152ee: bf00 nop 80152f0: e7fd b.n 80152ee configASSERT( pxTaskBuffer != NULL ); 80152f2: 6bbb ldr r3, [r7, #56] @ 0x38 80152f4: 2b00 cmp r3, #0 80152f6: d10b bne.n 8015310 __asm volatile 80152f8: f04f 0350 mov.w r3, #80 @ 0x50 80152fc: f383 8811 msr BASEPRI, r3 8015300: f3bf 8f6f isb sy 8015304: f3bf 8f4f dsb sy 8015308: 61fb str r3, [r7, #28] } 801530a: bf00 nop 801530c: bf00 nop 801530e: e7fd b.n 801530c #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8015310: 23a8 movs r3, #168 @ 0xa8 8015312: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8015314: 693b ldr r3, [r7, #16] 8015316: 2ba8 cmp r3, #168 @ 0xa8 8015318: d00b beq.n 8015332 __asm volatile 801531a: f04f 0350 mov.w r3, #80 @ 0x50 801531e: f383 8811 msr BASEPRI, r3 8015322: f3bf 8f6f isb sy 8015326: f3bf 8f4f dsb sy 801532a: 61bb str r3, [r7, #24] } 801532c: bf00 nop 801532e: bf00 nop 8015330: e7fd b.n 801532e ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8015332: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8015334: 6bbb ldr r3, [r7, #56] @ 0x38 8015336: 2b00 cmp r3, #0 8015338: d01e beq.n 8015378 801533a: 6b7b ldr r3, [r7, #52] @ 0x34 801533c: 2b00 cmp r3, #0 801533e: d01b beq.n 8015378 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8015340: 6bbb ldr r3, [r7, #56] @ 0x38 8015342: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8015344: 6a7b ldr r3, [r7, #36] @ 0x24 8015346: 6b7a ldr r2, [r7, #52] @ 0x34 8015348: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 801534a: 6a7b ldr r3, [r7, #36] @ 0x24 801534c: 2202 movs r2, #2 801534e: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8015352: 2300 movs r3, #0 8015354: 9303 str r3, [sp, #12] 8015356: 6a7b ldr r3, [r7, #36] @ 0x24 8015358: 9302 str r3, [sp, #8] 801535a: f107 0314 add.w r3, r7, #20 801535e: 9301 str r3, [sp, #4] 8015360: 6b3b ldr r3, [r7, #48] @ 0x30 8015362: 9300 str r3, [sp, #0] 8015364: 683b ldr r3, [r7, #0] 8015366: 687a ldr r2, [r7, #4] 8015368: 68b9 ldr r1, [r7, #8] 801536a: 68f8 ldr r0, [r7, #12] 801536c: f000 f850 bl 8015410 prvAddNewTaskToReadyList( pxNewTCB ); 8015370: 6a78 ldr r0, [r7, #36] @ 0x24 8015372: f000 f8f5 bl 8015560 8015376: e001 b.n 801537c } else { xReturn = NULL; 8015378: 2300 movs r3, #0 801537a: 617b str r3, [r7, #20] } return xReturn; 801537c: 697b ldr r3, [r7, #20] } 801537e: 4618 mov r0, r3 8015380: 3728 adds r7, #40 @ 0x28 8015382: 46bd mov sp, r7 8015384: bd80 pop {r7, pc} 08015386 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8015386: b580 push {r7, lr} 8015388: b08c sub sp, #48 @ 0x30 801538a: af04 add r7, sp, #16 801538c: 60f8 str r0, [r7, #12] 801538e: 60b9 str r1, [r7, #8] 8015390: 603b str r3, [r7, #0] 8015392: 4613 mov r3, r2 8015394: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8015396: 88fb ldrh r3, [r7, #6] 8015398: 009b lsls r3, r3, #2 801539a: 4618 mov r0, r3 801539c: f002 f8d6 bl 801754c 80153a0: 6178 str r0, [r7, #20] if( pxStack != NULL ) 80153a2: 697b ldr r3, [r7, #20] 80153a4: 2b00 cmp r3, #0 80153a6: d00e beq.n 80153c6 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 80153a8: 20a8 movs r0, #168 @ 0xa8 80153aa: f002 f8cf bl 801754c 80153ae: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 80153b0: 69fb ldr r3, [r7, #28] 80153b2: 2b00 cmp r3, #0 80153b4: d003 beq.n 80153be { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 80153b6: 69fb ldr r3, [r7, #28] 80153b8: 697a ldr r2, [r7, #20] 80153ba: 631a str r2, [r3, #48] @ 0x30 80153bc: e005 b.n 80153ca } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 80153be: 6978 ldr r0, [r7, #20] 80153c0: f002 f992 bl 80176e8 80153c4: e001 b.n 80153ca } } else { pxNewTCB = NULL; 80153c6: 2300 movs r3, #0 80153c8: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 80153ca: 69fb ldr r3, [r7, #28] 80153cc: 2b00 cmp r3, #0 80153ce: d017 beq.n 8015400 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 80153d0: 69fb ldr r3, [r7, #28] 80153d2: 2200 movs r2, #0 80153d4: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 80153d8: 88fa ldrh r2, [r7, #6] 80153da: 2300 movs r3, #0 80153dc: 9303 str r3, [sp, #12] 80153de: 69fb ldr r3, [r7, #28] 80153e0: 9302 str r3, [sp, #8] 80153e2: 6afb ldr r3, [r7, #44] @ 0x2c 80153e4: 9301 str r3, [sp, #4] 80153e6: 6abb ldr r3, [r7, #40] @ 0x28 80153e8: 9300 str r3, [sp, #0] 80153ea: 683b ldr r3, [r7, #0] 80153ec: 68b9 ldr r1, [r7, #8] 80153ee: 68f8 ldr r0, [r7, #12] 80153f0: f000 f80e bl 8015410 prvAddNewTaskToReadyList( pxNewTCB ); 80153f4: 69f8 ldr r0, [r7, #28] 80153f6: f000 f8b3 bl 8015560 xReturn = pdPASS; 80153fa: 2301 movs r3, #1 80153fc: 61bb str r3, [r7, #24] 80153fe: e002 b.n 8015406 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8015400: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015404: 61bb str r3, [r7, #24] } return xReturn; 8015406: 69bb ldr r3, [r7, #24] } 8015408: 4618 mov r0, r3 801540a: 3720 adds r7, #32 801540c: 46bd mov sp, r7 801540e: bd80 pop {r7, pc} 08015410 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8015410: b580 push {r7, lr} 8015412: b088 sub sp, #32 8015414: af00 add r7, sp, #0 8015416: 60f8 str r0, [r7, #12] 8015418: 60b9 str r1, [r7, #8] 801541a: 607a str r2, [r7, #4] 801541c: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 801541e: 6b3b ldr r3, [r7, #48] @ 0x30 8015420: 6b18 ldr r0, [r3, #48] @ 0x30 8015422: 687b ldr r3, [r7, #4] 8015424: 009b lsls r3, r3, #2 8015426: 461a mov r2, r3 8015428: 21a5 movs r1, #165 @ 0xa5 801542a: f002 fb94 bl 8017b56 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 801542e: 6b3b ldr r3, [r7, #48] @ 0x30 8015430: 6b1a ldr r2, [r3, #48] @ 0x30 8015432: 6879 ldr r1, [r7, #4] 8015434: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 8015438: 440b add r3, r1 801543a: 009b lsls r3, r3, #2 801543c: 4413 add r3, r2 801543e: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8015440: 69bb ldr r3, [r7, #24] 8015442: f023 0307 bic.w r3, r3, #7 8015446: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8015448: 69bb ldr r3, [r7, #24] 801544a: f003 0307 and.w r3, r3, #7 801544e: 2b00 cmp r3, #0 8015450: d00b beq.n 801546a __asm volatile 8015452: f04f 0350 mov.w r3, #80 @ 0x50 8015456: f383 8811 msr BASEPRI, r3 801545a: f3bf 8f6f isb sy 801545e: f3bf 8f4f dsb sy 8015462: 617b str r3, [r7, #20] } 8015464: bf00 nop 8015466: bf00 nop 8015468: e7fd b.n 8015466 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 801546a: 68bb ldr r3, [r7, #8] 801546c: 2b00 cmp r3, #0 801546e: d01f beq.n 80154b0 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015470: 2300 movs r3, #0 8015472: 61fb str r3, [r7, #28] 8015474: e012 b.n 801549c { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8015476: 68ba ldr r2, [r7, #8] 8015478: 69fb ldr r3, [r7, #28] 801547a: 4413 add r3, r2 801547c: 7819 ldrb r1, [r3, #0] 801547e: 6b3a ldr r2, [r7, #48] @ 0x30 8015480: 69fb ldr r3, [r7, #28] 8015482: 4413 add r3, r2 8015484: 3334 adds r3, #52 @ 0x34 8015486: 460a mov r2, r1 8015488: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 801548a: 68ba ldr r2, [r7, #8] 801548c: 69fb ldr r3, [r7, #28] 801548e: 4413 add r3, r2 8015490: 781b ldrb r3, [r3, #0] 8015492: 2b00 cmp r3, #0 8015494: d006 beq.n 80154a4 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015496: 69fb ldr r3, [r7, #28] 8015498: 3301 adds r3, #1 801549a: 61fb str r3, [r7, #28] 801549c: 69fb ldr r3, [r7, #28] 801549e: 2b0f cmp r3, #15 80154a0: d9e9 bls.n 8015476 80154a2: e000 b.n 80154a6 { break; 80154a4: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 80154a6: 6b3b ldr r3, [r7, #48] @ 0x30 80154a8: 2200 movs r2, #0 80154aa: f883 2043 strb.w r2, [r3, #67] @ 0x43 80154ae: e003 b.n 80154b8 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 80154b0: 6b3b ldr r3, [r7, #48] @ 0x30 80154b2: 2200 movs r2, #0 80154b4: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 80154b8: 6abb ldr r3, [r7, #40] @ 0x28 80154ba: 2b37 cmp r3, #55 @ 0x37 80154bc: d901 bls.n 80154c2 { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 80154be: 2337 movs r3, #55 @ 0x37 80154c0: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 80154c2: 6b3b ldr r3, [r7, #48] @ 0x30 80154c4: 6aba ldr r2, [r7, #40] @ 0x28 80154c6: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 80154c8: 6b3b ldr r3, [r7, #48] @ 0x30 80154ca: 6aba ldr r2, [r7, #40] @ 0x28 80154cc: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 80154ce: 6b3b ldr r3, [r7, #48] @ 0x30 80154d0: 2200 movs r2, #0 80154d2: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 80154d4: 6b3b ldr r3, [r7, #48] @ 0x30 80154d6: 3304 adds r3, #4 80154d8: 4618 mov r0, r3 80154da: f7fe fd09 bl 8013ef0 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 80154de: 6b3b ldr r3, [r7, #48] @ 0x30 80154e0: 3318 adds r3, #24 80154e2: 4618 mov r0, r3 80154e4: f7fe fd04 bl 8013ef0 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 80154e8: 6b3b ldr r3, [r7, #48] @ 0x30 80154ea: 6b3a ldr r2, [r7, #48] @ 0x30 80154ec: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80154ee: 6abb ldr r3, [r7, #40] @ 0x28 80154f0: f1c3 0238 rsb r2, r3, #56 @ 0x38 80154f4: 6b3b ldr r3, [r7, #48] @ 0x30 80154f6: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 80154f8: 6b3b ldr r3, [r7, #48] @ 0x30 80154fa: 6b3a ldr r2, [r7, #48] @ 0x30 80154fc: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 80154fe: 6b3b ldr r3, [r7, #48] @ 0x30 8015500: 2200 movs r2, #0 8015502: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8015506: 6b3b ldr r3, [r7, #48] @ 0x30 8015508: 2200 movs r2, #0 801550a: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 801550e: 6b3b ldr r3, [r7, #48] @ 0x30 8015510: 3354 adds r3, #84 @ 0x54 8015512: 224c movs r2, #76 @ 0x4c 8015514: 2100 movs r1, #0 8015516: 4618 mov r0, r3 8015518: f002 fb1d bl 8017b56 801551c: 6b3b ldr r3, [r7, #48] @ 0x30 801551e: 4a0d ldr r2, [pc, #52] @ (8015554 ) 8015520: 659a str r2, [r3, #88] @ 0x58 8015522: 6b3b ldr r3, [r7, #48] @ 0x30 8015524: 4a0c ldr r2, [pc, #48] @ (8015558 ) 8015526: 65da str r2, [r3, #92] @ 0x5c 8015528: 6b3b ldr r3, [r7, #48] @ 0x30 801552a: 4a0c ldr r2, [pc, #48] @ (801555c ) 801552c: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 801552e: 683a ldr r2, [r7, #0] 8015530: 68f9 ldr r1, [r7, #12] 8015532: 69b8 ldr r0, [r7, #24] 8015534: f001 fdb8 bl 80170a8 8015538: 4602 mov r2, r0 801553a: 6b3b ldr r3, [r7, #48] @ 0x30 801553c: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 801553e: 6afb ldr r3, [r7, #44] @ 0x2c 8015540: 2b00 cmp r3, #0 8015542: d002 beq.n 801554a { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8015544: 6afb ldr r3, [r7, #44] @ 0x2c 8015546: 6b3a ldr r2, [r7, #48] @ 0x30 8015548: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 801554a: bf00 nop 801554c: 3720 adds r7, #32 801554e: 46bd mov sp, r7 8015550: bd80 pop {r7, pc} 8015552: bf00 nop 8015554: 24012c94 .word 0x24012c94 8015558: 24012cfc .word 0x24012cfc 801555c: 24012d64 .word 0x24012d64 08015560 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 8015560: b580 push {r7, lr} 8015562: b082 sub sp, #8 8015564: af00 add r7, sp, #0 8015566: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8015568: f001 fece bl 8017308 { uxCurrentNumberOfTasks++; 801556c: 4b2d ldr r3, [pc, #180] @ (8015624 ) 801556e: 681b ldr r3, [r3, #0] 8015570: 3301 adds r3, #1 8015572: 4a2c ldr r2, [pc, #176] @ (8015624 ) 8015574: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8015576: 4b2c ldr r3, [pc, #176] @ (8015628 ) 8015578: 681b ldr r3, [r3, #0] 801557a: 2b00 cmp r3, #0 801557c: d109 bne.n 8015592 { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 801557e: 4a2a ldr r2, [pc, #168] @ (8015628 ) 8015580: 687b ldr r3, [r7, #4] 8015582: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8015584: 4b27 ldr r3, [pc, #156] @ (8015624 ) 8015586: 681b ldr r3, [r3, #0] 8015588: 2b01 cmp r3, #1 801558a: d110 bne.n 80155ae { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 801558c: f000 fc64 bl 8015e58 8015590: e00d b.n 80155ae else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 8015592: 4b26 ldr r3, [pc, #152] @ (801562c ) 8015594: 681b ldr r3, [r3, #0] 8015596: 2b00 cmp r3, #0 8015598: d109 bne.n 80155ae { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 801559a: 4b23 ldr r3, [pc, #140] @ (8015628 ) 801559c: 681b ldr r3, [r3, #0] 801559e: 6ada ldr r2, [r3, #44] @ 0x2c 80155a0: 687b ldr r3, [r7, #4] 80155a2: 6adb ldr r3, [r3, #44] @ 0x2c 80155a4: 429a cmp r2, r3 80155a6: d802 bhi.n 80155ae { pxCurrentTCB = pxNewTCB; 80155a8: 4a1f ldr r2, [pc, #124] @ (8015628 ) 80155aa: 687b ldr r3, [r7, #4] 80155ac: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 80155ae: 4b20 ldr r3, [pc, #128] @ (8015630 ) 80155b0: 681b ldr r3, [r3, #0] 80155b2: 3301 adds r3, #1 80155b4: 4a1e ldr r2, [pc, #120] @ (8015630 ) 80155b6: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 80155b8: 4b1d ldr r3, [pc, #116] @ (8015630 ) 80155ba: 681a ldr r2, [r3, #0] 80155bc: 687b ldr r3, [r7, #4] 80155be: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 80155c0: 687b ldr r3, [r7, #4] 80155c2: 6ada ldr r2, [r3, #44] @ 0x2c 80155c4: 4b1b ldr r3, [pc, #108] @ (8015634 ) 80155c6: 681b ldr r3, [r3, #0] 80155c8: 429a cmp r2, r3 80155ca: d903 bls.n 80155d4 80155cc: 687b ldr r3, [r7, #4] 80155ce: 6adb ldr r3, [r3, #44] @ 0x2c 80155d0: 4a18 ldr r2, [pc, #96] @ (8015634 ) 80155d2: 6013 str r3, [r2, #0] 80155d4: 687b ldr r3, [r7, #4] 80155d6: 6ada ldr r2, [r3, #44] @ 0x2c 80155d8: 4613 mov r3, r2 80155da: 009b lsls r3, r3, #2 80155dc: 4413 add r3, r2 80155de: 009b lsls r3, r3, #2 80155e0: 4a15 ldr r2, [pc, #84] @ (8015638 ) 80155e2: 441a add r2, r3 80155e4: 687b ldr r3, [r7, #4] 80155e6: 3304 adds r3, #4 80155e8: 4619 mov r1, r3 80155ea: 4610 mov r0, r2 80155ec: f7fe fc8d bl 8013f0a portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 80155f0: f001 febc bl 801736c if( xSchedulerRunning != pdFALSE ) 80155f4: 4b0d ldr r3, [pc, #52] @ (801562c ) 80155f6: 681b ldr r3, [r3, #0] 80155f8: 2b00 cmp r3, #0 80155fa: d00e beq.n 801561a { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 80155fc: 4b0a ldr r3, [pc, #40] @ (8015628 ) 80155fe: 681b ldr r3, [r3, #0] 8015600: 6ada ldr r2, [r3, #44] @ 0x2c 8015602: 687b ldr r3, [r7, #4] 8015604: 6adb ldr r3, [r3, #44] @ 0x2c 8015606: 429a cmp r2, r3 8015608: d207 bcs.n 801561a { taskYIELD_IF_USING_PREEMPTION(); 801560a: 4b0c ldr r3, [pc, #48] @ (801563c ) 801560c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015610: 601a str r2, [r3, #0] 8015612: f3bf 8f4f dsb sy 8015616: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 801561a: bf00 nop 801561c: 3708 adds r7, #8 801561e: 46bd mov sp, r7 8015620: bd80 pop {r7, pc} 8015622: bf00 nop 8015624: 24002b14 .word 0x24002b14 8015628: 24002640 .word 0x24002640 801562c: 24002b20 .word 0x24002b20 8015630: 24002b30 .word 0x24002b30 8015634: 24002b1c .word 0x24002b1c 8015638: 24002644 .word 0x24002644 801563c: e000ed04 .word 0xe000ed04 08015640 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8015640: b580 push {r7, lr} 8015642: b084 sub sp, #16 8015644: af00 add r7, sp, #0 8015646: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 8015648: 2300 movs r3, #0 801564a: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 801564c: 687b ldr r3, [r7, #4] 801564e: 2b00 cmp r3, #0 8015650: d018 beq.n 8015684 { configASSERT( uxSchedulerSuspended == 0 ); 8015652: 4b14 ldr r3, [pc, #80] @ (80156a4 ) 8015654: 681b ldr r3, [r3, #0] 8015656: 2b00 cmp r3, #0 8015658: d00b beq.n 8015672 __asm volatile 801565a: f04f 0350 mov.w r3, #80 @ 0x50 801565e: f383 8811 msr BASEPRI, r3 8015662: f3bf 8f6f isb sy 8015666: f3bf 8f4f dsb sy 801566a: 60bb str r3, [r7, #8] } 801566c: bf00 nop 801566e: bf00 nop 8015670: e7fd b.n 801566e vTaskSuspendAll(); 8015672: f000 f88b bl 801578c list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 8015676: 2100 movs r1, #0 8015678: 6878 ldr r0, [r7, #4] 801567a: f001 f87d bl 8016778 } xAlreadyYielded = xTaskResumeAll(); 801567e: f000 f893 bl 80157a8 8015682: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 8015684: 68fb ldr r3, [r7, #12] 8015686: 2b00 cmp r3, #0 8015688: d107 bne.n 801569a { portYIELD_WITHIN_API(); 801568a: 4b07 ldr r3, [pc, #28] @ (80156a8 ) 801568c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015690: 601a str r2, [r3, #0] 8015692: f3bf 8f4f dsb sy 8015696: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 801569a: bf00 nop 801569c: 3710 adds r7, #16 801569e: 46bd mov sp, r7 80156a0: bd80 pop {r7, pc} 80156a2: bf00 nop 80156a4: 24002b3c .word 0x24002b3c 80156a8: e000ed04 .word 0xe000ed04 080156ac : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 80156ac: b580 push {r7, lr} 80156ae: b08a sub sp, #40 @ 0x28 80156b0: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 80156b2: 2300 movs r3, #0 80156b4: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 80156b6: 2300 movs r3, #0 80156b8: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 80156ba: 463a mov r2, r7 80156bc: 1d39 adds r1, r7, #4 80156be: f107 0308 add.w r3, r7, #8 80156c2: 4618 mov r0, r3 80156c4: f7fe fbc0 bl 8013e48 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 80156c8: 6839 ldr r1, [r7, #0] 80156ca: 687b ldr r3, [r7, #4] 80156cc: 68ba ldr r2, [r7, #8] 80156ce: 9202 str r2, [sp, #8] 80156d0: 9301 str r3, [sp, #4] 80156d2: 2300 movs r3, #0 80156d4: 9300 str r3, [sp, #0] 80156d6: 2300 movs r3, #0 80156d8: 460a mov r2, r1 80156da: 4924 ldr r1, [pc, #144] @ (801576c ) 80156dc: 4824 ldr r0, [pc, #144] @ (8015770 ) 80156de: f7ff fdf2 bl 80152c6 80156e2: 4603 mov r3, r0 80156e4: 4a23 ldr r2, [pc, #140] @ (8015774 ) 80156e6: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 80156e8: 4b22 ldr r3, [pc, #136] @ (8015774 ) 80156ea: 681b ldr r3, [r3, #0] 80156ec: 2b00 cmp r3, #0 80156ee: d002 beq.n 80156f6 { xReturn = pdPASS; 80156f0: 2301 movs r3, #1 80156f2: 617b str r3, [r7, #20] 80156f4: e001 b.n 80156fa } else { xReturn = pdFAIL; 80156f6: 2300 movs r3, #0 80156f8: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 80156fa: 697b ldr r3, [r7, #20] 80156fc: 2b01 cmp r3, #1 80156fe: d102 bne.n 8015706 { xReturn = xTimerCreateTimerTask(); 8015700: f001 f88e bl 8016820 8015704: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 8015706: 697b ldr r3, [r7, #20] 8015708: 2b01 cmp r3, #1 801570a: d11b bne.n 8015744 __asm volatile 801570c: f04f 0350 mov.w r3, #80 @ 0x50 8015710: f383 8811 msr BASEPRI, r3 8015714: f3bf 8f6f isb sy 8015718: f3bf 8f4f dsb sy 801571c: 613b str r3, [r7, #16] } 801571e: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8015720: 4b15 ldr r3, [pc, #84] @ (8015778 ) 8015722: 681b ldr r3, [r3, #0] 8015724: 3354 adds r3, #84 @ 0x54 8015726: 4a15 ldr r2, [pc, #84] @ (801577c ) 8015728: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 801572a: 4b15 ldr r3, [pc, #84] @ (8015780 ) 801572c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015730: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8015732: 4b14 ldr r3, [pc, #80] @ (8015784 ) 8015734: 2201 movs r2, #1 8015736: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 8015738: 4b13 ldr r3, [pc, #76] @ (8015788 ) 801573a: 2200 movs r2, #0 801573c: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 801573e: f001 fd3f bl 80171c0 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 8015742: e00f b.n 8015764 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8015744: 697b ldr r3, [r7, #20] 8015746: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801574a: d10b bne.n 8015764 __asm volatile 801574c: f04f 0350 mov.w r3, #80 @ 0x50 8015750: f383 8811 msr BASEPRI, r3 8015754: f3bf 8f6f isb sy 8015758: f3bf 8f4f dsb sy 801575c: 60fb str r3, [r7, #12] } 801575e: bf00 nop 8015760: bf00 nop 8015762: e7fd b.n 8015760 } 8015764: bf00 nop 8015766: 3718 adds r7, #24 8015768: 46bd mov sp, r7 801576a: bd80 pop {r7, pc} 801576c: 0801894c .word 0x0801894c 8015770: 08015e29 .word 0x08015e29 8015774: 24002b38 .word 0x24002b38 8015778: 24002640 .word 0x24002640 801577c: 24000054 .word 0x24000054 8015780: 24002b34 .word 0x24002b34 8015784: 24002b20 .word 0x24002b20 8015788: 24002b18 .word 0x24002b18 0801578c : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 801578c: b480 push {r7} 801578e: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8015790: 4b04 ldr r3, [pc, #16] @ (80157a4 ) 8015792: 681b ldr r3, [r3, #0] 8015794: 3301 adds r3, #1 8015796: 4a03 ldr r2, [pc, #12] @ (80157a4 ) 8015798: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 801579a: bf00 nop 801579c: 46bd mov sp, r7 801579e: f85d 7b04 ldr.w r7, [sp], #4 80157a2: 4770 bx lr 80157a4: 24002b3c .word 0x24002b3c 080157a8 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 80157a8: b580 push {r7, lr} 80157aa: b084 sub sp, #16 80157ac: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 80157ae: 2300 movs r3, #0 80157b0: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 80157b2: 2300 movs r3, #0 80157b4: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 80157b6: 4b42 ldr r3, [pc, #264] @ (80158c0 ) 80157b8: 681b ldr r3, [r3, #0] 80157ba: 2b00 cmp r3, #0 80157bc: d10b bne.n 80157d6 __asm volatile 80157be: f04f 0350 mov.w r3, #80 @ 0x50 80157c2: f383 8811 msr BASEPRI, r3 80157c6: f3bf 8f6f isb sy 80157ca: f3bf 8f4f dsb sy 80157ce: 603b str r3, [r7, #0] } 80157d0: bf00 nop 80157d2: bf00 nop 80157d4: e7fd b.n 80157d2 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 80157d6: f001 fd97 bl 8017308 { --uxSchedulerSuspended; 80157da: 4b39 ldr r3, [pc, #228] @ (80158c0 ) 80157dc: 681b ldr r3, [r3, #0] 80157de: 3b01 subs r3, #1 80157e0: 4a37 ldr r2, [pc, #220] @ (80158c0 ) 80157e2: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80157e4: 4b36 ldr r3, [pc, #216] @ (80158c0 ) 80157e6: 681b ldr r3, [r3, #0] 80157e8: 2b00 cmp r3, #0 80157ea: d162 bne.n 80158b2 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80157ec: 4b35 ldr r3, [pc, #212] @ (80158c4 ) 80157ee: 681b ldr r3, [r3, #0] 80157f0: 2b00 cmp r3, #0 80157f2: d05e beq.n 80158b2 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80157f4: e02f b.n 8015856 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80157f6: 4b34 ldr r3, [pc, #208] @ (80158c8 ) 80157f8: 68db ldr r3, [r3, #12] 80157fa: 68db ldr r3, [r3, #12] 80157fc: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80157fe: 68fb ldr r3, [r7, #12] 8015800: 3318 adds r3, #24 8015802: 4618 mov r0, r3 8015804: f7fe fbde bl 8013fc4 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8015808: 68fb ldr r3, [r7, #12] 801580a: 3304 adds r3, #4 801580c: 4618 mov r0, r3 801580e: f7fe fbd9 bl 8013fc4 prvAddTaskToReadyList( pxTCB ); 8015812: 68fb ldr r3, [r7, #12] 8015814: 6ada ldr r2, [r3, #44] @ 0x2c 8015816: 4b2d ldr r3, [pc, #180] @ (80158cc ) 8015818: 681b ldr r3, [r3, #0] 801581a: 429a cmp r2, r3 801581c: d903 bls.n 8015826 801581e: 68fb ldr r3, [r7, #12] 8015820: 6adb ldr r3, [r3, #44] @ 0x2c 8015822: 4a2a ldr r2, [pc, #168] @ (80158cc ) 8015824: 6013 str r3, [r2, #0] 8015826: 68fb ldr r3, [r7, #12] 8015828: 6ada ldr r2, [r3, #44] @ 0x2c 801582a: 4613 mov r3, r2 801582c: 009b lsls r3, r3, #2 801582e: 4413 add r3, r2 8015830: 009b lsls r3, r3, #2 8015832: 4a27 ldr r2, [pc, #156] @ (80158d0 ) 8015834: 441a add r2, r3 8015836: 68fb ldr r3, [r7, #12] 8015838: 3304 adds r3, #4 801583a: 4619 mov r1, r3 801583c: 4610 mov r0, r2 801583e: f7fe fb64 bl 8013f0a /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8015842: 68fb ldr r3, [r7, #12] 8015844: 6ada ldr r2, [r3, #44] @ 0x2c 8015846: 4b23 ldr r3, [pc, #140] @ (80158d4 ) 8015848: 681b ldr r3, [r3, #0] 801584a: 6adb ldr r3, [r3, #44] @ 0x2c 801584c: 429a cmp r2, r3 801584e: d302 bcc.n 8015856 { xYieldPending = pdTRUE; 8015850: 4b21 ldr r3, [pc, #132] @ (80158d8 ) 8015852: 2201 movs r2, #1 8015854: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8015856: 4b1c ldr r3, [pc, #112] @ (80158c8 ) 8015858: 681b ldr r3, [r3, #0] 801585a: 2b00 cmp r3, #0 801585c: d1cb bne.n 80157f6 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 801585e: 68fb ldr r3, [r7, #12] 8015860: 2b00 cmp r3, #0 8015862: d001 beq.n 8015868 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 8015864: f000 fb9c bl 8015fa0 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8015868: 4b1c ldr r3, [pc, #112] @ (80158dc ) 801586a: 681b ldr r3, [r3, #0] 801586c: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 801586e: 687b ldr r3, [r7, #4] 8015870: 2b00 cmp r3, #0 8015872: d010 beq.n 8015896 { do { if( xTaskIncrementTick() != pdFALSE ) 8015874: f000 f846 bl 8015904 8015878: 4603 mov r3, r0 801587a: 2b00 cmp r3, #0 801587c: d002 beq.n 8015884 { xYieldPending = pdTRUE; 801587e: 4b16 ldr r3, [pc, #88] @ (80158d8 ) 8015880: 2201 movs r2, #1 8015882: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8015884: 687b ldr r3, [r7, #4] 8015886: 3b01 subs r3, #1 8015888: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 801588a: 687b ldr r3, [r7, #4] 801588c: 2b00 cmp r3, #0 801588e: d1f1 bne.n 8015874 xPendedTicks = 0; 8015890: 4b12 ldr r3, [pc, #72] @ (80158dc ) 8015892: 2200 movs r2, #0 8015894: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8015896: 4b10 ldr r3, [pc, #64] @ (80158d8 ) 8015898: 681b ldr r3, [r3, #0] 801589a: 2b00 cmp r3, #0 801589c: d009 beq.n 80158b2 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 801589e: 2301 movs r3, #1 80158a0: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 80158a2: 4b0f ldr r3, [pc, #60] @ (80158e0 ) 80158a4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80158a8: 601a str r2, [r3, #0] 80158aa: f3bf 8f4f dsb sy 80158ae: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80158b2: f001 fd5b bl 801736c return xAlreadyYielded; 80158b6: 68bb ldr r3, [r7, #8] } 80158b8: 4618 mov r0, r3 80158ba: 3710 adds r7, #16 80158bc: 46bd mov sp, r7 80158be: bd80 pop {r7, pc} 80158c0: 24002b3c .word 0x24002b3c 80158c4: 24002b14 .word 0x24002b14 80158c8: 24002ad4 .word 0x24002ad4 80158cc: 24002b1c .word 0x24002b1c 80158d0: 24002644 .word 0x24002644 80158d4: 24002640 .word 0x24002640 80158d8: 24002b28 .word 0x24002b28 80158dc: 24002b24 .word 0x24002b24 80158e0: e000ed04 .word 0xe000ed04 080158e4 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 80158e4: b480 push {r7} 80158e6: b083 sub sp, #12 80158e8: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 80158ea: 4b05 ldr r3, [pc, #20] @ (8015900 ) 80158ec: 681b ldr r3, [r3, #0] 80158ee: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 80158f0: 687b ldr r3, [r7, #4] } 80158f2: 4618 mov r0, r3 80158f4: 370c adds r7, #12 80158f6: 46bd mov sp, r7 80158f8: f85d 7b04 ldr.w r7, [sp], #4 80158fc: 4770 bx lr 80158fe: bf00 nop 8015900: 24002b18 .word 0x24002b18 08015904 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 8015904: b580 push {r7, lr} 8015906: b086 sub sp, #24 8015908: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 801590a: 2300 movs r3, #0 801590c: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801590e: 4b4f ldr r3, [pc, #316] @ (8015a4c ) 8015910: 681b ldr r3, [r3, #0] 8015912: 2b00 cmp r3, #0 8015914: f040 8090 bne.w 8015a38 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 8015918: 4b4d ldr r3, [pc, #308] @ (8015a50 ) 801591a: 681b ldr r3, [r3, #0] 801591c: 3301 adds r3, #1 801591e: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8015920: 4a4b ldr r2, [pc, #300] @ (8015a50 ) 8015922: 693b ldr r3, [r7, #16] 8015924: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 8015926: 693b ldr r3, [r7, #16] 8015928: 2b00 cmp r3, #0 801592a: d121 bne.n 8015970 { taskSWITCH_DELAYED_LISTS(); 801592c: 4b49 ldr r3, [pc, #292] @ (8015a54 ) 801592e: 681b ldr r3, [r3, #0] 8015930: 681b ldr r3, [r3, #0] 8015932: 2b00 cmp r3, #0 8015934: d00b beq.n 801594e __asm volatile 8015936: f04f 0350 mov.w r3, #80 @ 0x50 801593a: f383 8811 msr BASEPRI, r3 801593e: f3bf 8f6f isb sy 8015942: f3bf 8f4f dsb sy 8015946: 603b str r3, [r7, #0] } 8015948: bf00 nop 801594a: bf00 nop 801594c: e7fd b.n 801594a 801594e: 4b41 ldr r3, [pc, #260] @ (8015a54 ) 8015950: 681b ldr r3, [r3, #0] 8015952: 60fb str r3, [r7, #12] 8015954: 4b40 ldr r3, [pc, #256] @ (8015a58 ) 8015956: 681b ldr r3, [r3, #0] 8015958: 4a3e ldr r2, [pc, #248] @ (8015a54 ) 801595a: 6013 str r3, [r2, #0] 801595c: 4a3e ldr r2, [pc, #248] @ (8015a58 ) 801595e: 68fb ldr r3, [r7, #12] 8015960: 6013 str r3, [r2, #0] 8015962: 4b3e ldr r3, [pc, #248] @ (8015a5c ) 8015964: 681b ldr r3, [r3, #0] 8015966: 3301 adds r3, #1 8015968: 4a3c ldr r2, [pc, #240] @ (8015a5c ) 801596a: 6013 str r3, [r2, #0] 801596c: f000 fb18 bl 8015fa0 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8015970: 4b3b ldr r3, [pc, #236] @ (8015a60 ) 8015972: 681b ldr r3, [r3, #0] 8015974: 693a ldr r2, [r7, #16] 8015976: 429a cmp r2, r3 8015978: d349 bcc.n 8015a0e { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 801597a: 4b36 ldr r3, [pc, #216] @ (8015a54 ) 801597c: 681b ldr r3, [r3, #0] 801597e: 681b ldr r3, [r3, #0] 8015980: 2b00 cmp r3, #0 8015982: d104 bne.n 801598e /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015984: 4b36 ldr r3, [pc, #216] @ (8015a60 ) 8015986: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801598a: 601a str r2, [r3, #0] break; 801598c: e03f b.n 8015a0e { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801598e: 4b31 ldr r3, [pc, #196] @ (8015a54 ) 8015990: 681b ldr r3, [r3, #0] 8015992: 68db ldr r3, [r3, #12] 8015994: 68db ldr r3, [r3, #12] 8015996: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8015998: 68bb ldr r3, [r7, #8] 801599a: 685b ldr r3, [r3, #4] 801599c: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 801599e: 693a ldr r2, [r7, #16] 80159a0: 687b ldr r3, [r7, #4] 80159a2: 429a cmp r2, r3 80159a4: d203 bcs.n 80159ae /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 80159a6: 4a2e ldr r2, [pc, #184] @ (8015a60 ) 80159a8: 687b ldr r3, [r7, #4] 80159aa: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 80159ac: e02f b.n 8015a0e { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80159ae: 68bb ldr r3, [r7, #8] 80159b0: 3304 adds r3, #4 80159b2: 4618 mov r0, r3 80159b4: f7fe fb06 bl 8013fc4 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 80159b8: 68bb ldr r3, [r7, #8] 80159ba: 6a9b ldr r3, [r3, #40] @ 0x28 80159bc: 2b00 cmp r3, #0 80159be: d004 beq.n 80159ca { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80159c0: 68bb ldr r3, [r7, #8] 80159c2: 3318 adds r3, #24 80159c4: 4618 mov r0, r3 80159c6: f7fe fafd bl 8013fc4 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 80159ca: 68bb ldr r3, [r7, #8] 80159cc: 6ada ldr r2, [r3, #44] @ 0x2c 80159ce: 4b25 ldr r3, [pc, #148] @ (8015a64 ) 80159d0: 681b ldr r3, [r3, #0] 80159d2: 429a cmp r2, r3 80159d4: d903 bls.n 80159de 80159d6: 68bb ldr r3, [r7, #8] 80159d8: 6adb ldr r3, [r3, #44] @ 0x2c 80159da: 4a22 ldr r2, [pc, #136] @ (8015a64 ) 80159dc: 6013 str r3, [r2, #0] 80159de: 68bb ldr r3, [r7, #8] 80159e0: 6ada ldr r2, [r3, #44] @ 0x2c 80159e2: 4613 mov r3, r2 80159e4: 009b lsls r3, r3, #2 80159e6: 4413 add r3, r2 80159e8: 009b lsls r3, r3, #2 80159ea: 4a1f ldr r2, [pc, #124] @ (8015a68 ) 80159ec: 441a add r2, r3 80159ee: 68bb ldr r3, [r7, #8] 80159f0: 3304 adds r3, #4 80159f2: 4619 mov r1, r3 80159f4: 4610 mov r0, r2 80159f6: f7fe fa88 bl 8013f0a { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80159fa: 68bb ldr r3, [r7, #8] 80159fc: 6ada ldr r2, [r3, #44] @ 0x2c 80159fe: 4b1b ldr r3, [pc, #108] @ (8015a6c ) 8015a00: 681b ldr r3, [r3, #0] 8015a02: 6adb ldr r3, [r3, #44] @ 0x2c 8015a04: 429a cmp r2, r3 8015a06: d3b8 bcc.n 801597a { xSwitchRequired = pdTRUE; 8015a08: 2301 movs r3, #1 8015a0a: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8015a0c: e7b5 b.n 801597a /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 8015a0e: 4b17 ldr r3, [pc, #92] @ (8015a6c ) 8015a10: 681b ldr r3, [r3, #0] 8015a12: 6ada ldr r2, [r3, #44] @ 0x2c 8015a14: 4914 ldr r1, [pc, #80] @ (8015a68 ) 8015a16: 4613 mov r3, r2 8015a18: 009b lsls r3, r3, #2 8015a1a: 4413 add r3, r2 8015a1c: 009b lsls r3, r3, #2 8015a1e: 440b add r3, r1 8015a20: 681b ldr r3, [r3, #0] 8015a22: 2b01 cmp r3, #1 8015a24: d901 bls.n 8015a2a { xSwitchRequired = pdTRUE; 8015a26: 2301 movs r3, #1 8015a28: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 8015a2a: 4b11 ldr r3, [pc, #68] @ (8015a70 ) 8015a2c: 681b ldr r3, [r3, #0] 8015a2e: 2b00 cmp r3, #0 8015a30: d007 beq.n 8015a42 { xSwitchRequired = pdTRUE; 8015a32: 2301 movs r3, #1 8015a34: 617b str r3, [r7, #20] 8015a36: e004 b.n 8015a42 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 8015a38: 4b0e ldr r3, [pc, #56] @ (8015a74 ) 8015a3a: 681b ldr r3, [r3, #0] 8015a3c: 3301 adds r3, #1 8015a3e: 4a0d ldr r2, [pc, #52] @ (8015a74 ) 8015a40: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8015a42: 697b ldr r3, [r7, #20] } 8015a44: 4618 mov r0, r3 8015a46: 3718 adds r7, #24 8015a48: 46bd mov sp, r7 8015a4a: bd80 pop {r7, pc} 8015a4c: 24002b3c .word 0x24002b3c 8015a50: 24002b18 .word 0x24002b18 8015a54: 24002acc .word 0x24002acc 8015a58: 24002ad0 .word 0x24002ad0 8015a5c: 24002b2c .word 0x24002b2c 8015a60: 24002b34 .word 0x24002b34 8015a64: 24002b1c .word 0x24002b1c 8015a68: 24002644 .word 0x24002644 8015a6c: 24002640 .word 0x24002640 8015a70: 24002b28 .word 0x24002b28 8015a74: 24002b24 .word 0x24002b24 08015a78 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 8015a78: b580 push {r7, lr} 8015a7a: b084 sub sp, #16 8015a7c: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 8015a7e: 4b32 ldr r3, [pc, #200] @ (8015b48 ) 8015a80: 681b ldr r3, [r3, #0] 8015a82: 2b00 cmp r3, #0 8015a84: d003 beq.n 8015a8e { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 8015a86: 4b31 ldr r3, [pc, #196] @ (8015b4c ) 8015a88: 2201 movs r2, #1 8015a8a: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 8015a8c: e058 b.n 8015b40 xYieldPending = pdFALSE; 8015a8e: 4b2f ldr r3, [pc, #188] @ (8015b4c ) 8015a90: 2200 movs r2, #0 8015a92: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 8015a94: 4b2e ldr r3, [pc, #184] @ (8015b50 ) 8015a96: 681b ldr r3, [r3, #0] 8015a98: 681a ldr r2, [r3, #0] 8015a9a: 4b2d ldr r3, [pc, #180] @ (8015b50 ) 8015a9c: 681b ldr r3, [r3, #0] 8015a9e: 6b1b ldr r3, [r3, #48] @ 0x30 8015aa0: 429a cmp r2, r3 8015aa2: d808 bhi.n 8015ab6 8015aa4: 4b2a ldr r3, [pc, #168] @ (8015b50 ) 8015aa6: 681a ldr r2, [r3, #0] 8015aa8: 4b29 ldr r3, [pc, #164] @ (8015b50 ) 8015aaa: 681b ldr r3, [r3, #0] 8015aac: 3334 adds r3, #52 @ 0x34 8015aae: 4619 mov r1, r3 8015ab0: 4610 mov r0, r2 8015ab2: f7ea fddd bl 8000670 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015ab6: 4b27 ldr r3, [pc, #156] @ (8015b54 ) 8015ab8: 681b ldr r3, [r3, #0] 8015aba: 60fb str r3, [r7, #12] 8015abc: e011 b.n 8015ae2 8015abe: 68fb ldr r3, [r7, #12] 8015ac0: 2b00 cmp r3, #0 8015ac2: d10b bne.n 8015adc __asm volatile 8015ac4: f04f 0350 mov.w r3, #80 @ 0x50 8015ac8: f383 8811 msr BASEPRI, r3 8015acc: f3bf 8f6f isb sy 8015ad0: f3bf 8f4f dsb sy 8015ad4: 607b str r3, [r7, #4] } 8015ad6: bf00 nop 8015ad8: bf00 nop 8015ada: e7fd b.n 8015ad8 8015adc: 68fb ldr r3, [r7, #12] 8015ade: 3b01 subs r3, #1 8015ae0: 60fb str r3, [r7, #12] 8015ae2: 491d ldr r1, [pc, #116] @ (8015b58 ) 8015ae4: 68fa ldr r2, [r7, #12] 8015ae6: 4613 mov r3, r2 8015ae8: 009b lsls r3, r3, #2 8015aea: 4413 add r3, r2 8015aec: 009b lsls r3, r3, #2 8015aee: 440b add r3, r1 8015af0: 681b ldr r3, [r3, #0] 8015af2: 2b00 cmp r3, #0 8015af4: d0e3 beq.n 8015abe 8015af6: 68fa ldr r2, [r7, #12] 8015af8: 4613 mov r3, r2 8015afa: 009b lsls r3, r3, #2 8015afc: 4413 add r3, r2 8015afe: 009b lsls r3, r3, #2 8015b00: 4a15 ldr r2, [pc, #84] @ (8015b58 ) 8015b02: 4413 add r3, r2 8015b04: 60bb str r3, [r7, #8] 8015b06: 68bb ldr r3, [r7, #8] 8015b08: 685b ldr r3, [r3, #4] 8015b0a: 685a ldr r2, [r3, #4] 8015b0c: 68bb ldr r3, [r7, #8] 8015b0e: 605a str r2, [r3, #4] 8015b10: 68bb ldr r3, [r7, #8] 8015b12: 685a ldr r2, [r3, #4] 8015b14: 68bb ldr r3, [r7, #8] 8015b16: 3308 adds r3, #8 8015b18: 429a cmp r2, r3 8015b1a: d104 bne.n 8015b26 8015b1c: 68bb ldr r3, [r7, #8] 8015b1e: 685b ldr r3, [r3, #4] 8015b20: 685a ldr r2, [r3, #4] 8015b22: 68bb ldr r3, [r7, #8] 8015b24: 605a str r2, [r3, #4] 8015b26: 68bb ldr r3, [r7, #8] 8015b28: 685b ldr r3, [r3, #4] 8015b2a: 68db ldr r3, [r3, #12] 8015b2c: 4a08 ldr r2, [pc, #32] @ (8015b50 ) 8015b2e: 6013 str r3, [r2, #0] 8015b30: 4a08 ldr r2, [pc, #32] @ (8015b54 ) 8015b32: 68fb ldr r3, [r7, #12] 8015b34: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8015b36: 4b06 ldr r3, [pc, #24] @ (8015b50 ) 8015b38: 681b ldr r3, [r3, #0] 8015b3a: 3354 adds r3, #84 @ 0x54 8015b3c: 4a07 ldr r2, [pc, #28] @ (8015b5c ) 8015b3e: 6013 str r3, [r2, #0] } 8015b40: bf00 nop 8015b42: 3710 adds r7, #16 8015b44: 46bd mov sp, r7 8015b46: bd80 pop {r7, pc} 8015b48: 24002b3c .word 0x24002b3c 8015b4c: 24002b28 .word 0x24002b28 8015b50: 24002640 .word 0x24002640 8015b54: 24002b1c .word 0x24002b1c 8015b58: 24002644 .word 0x24002644 8015b5c: 24000054 .word 0x24000054 08015b60 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8015b60: b580 push {r7, lr} 8015b62: b084 sub sp, #16 8015b64: af00 add r7, sp, #0 8015b66: 6078 str r0, [r7, #4] 8015b68: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 8015b6a: 687b ldr r3, [r7, #4] 8015b6c: 2b00 cmp r3, #0 8015b6e: d10b bne.n 8015b88 __asm volatile 8015b70: f04f 0350 mov.w r3, #80 @ 0x50 8015b74: f383 8811 msr BASEPRI, r3 8015b78: f3bf 8f6f isb sy 8015b7c: f3bf 8f4f dsb sy 8015b80: 60fb str r3, [r7, #12] } 8015b82: bf00 nop 8015b84: bf00 nop 8015b86: e7fd b.n 8015b84 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8015b88: 4b07 ldr r3, [pc, #28] @ (8015ba8 ) 8015b8a: 681b ldr r3, [r3, #0] 8015b8c: 3318 adds r3, #24 8015b8e: 4619 mov r1, r3 8015b90: 6878 ldr r0, [r7, #4] 8015b92: f7fe f9de bl 8013f52 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8015b96: 2101 movs r1, #1 8015b98: 6838 ldr r0, [r7, #0] 8015b9a: f000 fded bl 8016778 } 8015b9e: bf00 nop 8015ba0: 3710 adds r7, #16 8015ba2: 46bd mov sp, r7 8015ba4: bd80 pop {r7, pc} 8015ba6: bf00 nop 8015ba8: 24002640 .word 0x24002640 08015bac : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8015bac: b580 push {r7, lr} 8015bae: b086 sub sp, #24 8015bb0: af00 add r7, sp, #0 8015bb2: 60f8 str r0, [r7, #12] 8015bb4: 60b9 str r1, [r7, #8] 8015bb6: 607a str r2, [r7, #4] configASSERT( pxEventList ); 8015bb8: 68fb ldr r3, [r7, #12] 8015bba: 2b00 cmp r3, #0 8015bbc: d10b bne.n 8015bd6 __asm volatile 8015bbe: f04f 0350 mov.w r3, #80 @ 0x50 8015bc2: f383 8811 msr BASEPRI, r3 8015bc6: f3bf 8f6f isb sy 8015bca: f3bf 8f4f dsb sy 8015bce: 617b str r3, [r7, #20] } 8015bd0: bf00 nop 8015bd2: bf00 nop 8015bd4: e7fd b.n 8015bd2 /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8015bd6: 4b0a ldr r3, [pc, #40] @ (8015c00 ) 8015bd8: 681b ldr r3, [r3, #0] 8015bda: 3318 adds r3, #24 8015bdc: 4619 mov r1, r3 8015bde: 68f8 ldr r0, [r7, #12] 8015be0: f7fe f993 bl 8013f0a /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 8015be4: 687b ldr r3, [r7, #4] 8015be6: 2b00 cmp r3, #0 8015be8: d002 beq.n 8015bf0 { xTicksToWait = portMAX_DELAY; 8015bea: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015bee: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 8015bf0: 6879 ldr r1, [r7, #4] 8015bf2: 68b8 ldr r0, [r7, #8] 8015bf4: f000 fdc0 bl 8016778 } 8015bf8: bf00 nop 8015bfa: 3718 adds r7, #24 8015bfc: 46bd mov sp, r7 8015bfe: bd80 pop {r7, pc} 8015c00: 24002640 .word 0x24002640 08015c04 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 8015c04: b580 push {r7, lr} 8015c06: b086 sub sp, #24 8015c08: af00 add r7, sp, #0 8015c0a: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015c0c: 687b ldr r3, [r7, #4] 8015c0e: 68db ldr r3, [r3, #12] 8015c10: 68db ldr r3, [r3, #12] 8015c12: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 8015c14: 693b ldr r3, [r7, #16] 8015c16: 2b00 cmp r3, #0 8015c18: d10b bne.n 8015c32 __asm volatile 8015c1a: f04f 0350 mov.w r3, #80 @ 0x50 8015c1e: f383 8811 msr BASEPRI, r3 8015c22: f3bf 8f6f isb sy 8015c26: f3bf 8f4f dsb sy 8015c2a: 60fb str r3, [r7, #12] } 8015c2c: bf00 nop 8015c2e: bf00 nop 8015c30: e7fd b.n 8015c2e ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 8015c32: 693b ldr r3, [r7, #16] 8015c34: 3318 adds r3, #24 8015c36: 4618 mov r0, r3 8015c38: f7fe f9c4 bl 8013fc4 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8015c3c: 4b1d ldr r3, [pc, #116] @ (8015cb4 ) 8015c3e: 681b ldr r3, [r3, #0] 8015c40: 2b00 cmp r3, #0 8015c42: d11d bne.n 8015c80 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 8015c44: 693b ldr r3, [r7, #16] 8015c46: 3304 adds r3, #4 8015c48: 4618 mov r0, r3 8015c4a: f7fe f9bb bl 8013fc4 prvAddTaskToReadyList( pxUnblockedTCB ); 8015c4e: 693b ldr r3, [r7, #16] 8015c50: 6ada ldr r2, [r3, #44] @ 0x2c 8015c52: 4b19 ldr r3, [pc, #100] @ (8015cb8 ) 8015c54: 681b ldr r3, [r3, #0] 8015c56: 429a cmp r2, r3 8015c58: d903 bls.n 8015c62 8015c5a: 693b ldr r3, [r7, #16] 8015c5c: 6adb ldr r3, [r3, #44] @ 0x2c 8015c5e: 4a16 ldr r2, [pc, #88] @ (8015cb8 ) 8015c60: 6013 str r3, [r2, #0] 8015c62: 693b ldr r3, [r7, #16] 8015c64: 6ada ldr r2, [r3, #44] @ 0x2c 8015c66: 4613 mov r3, r2 8015c68: 009b lsls r3, r3, #2 8015c6a: 4413 add r3, r2 8015c6c: 009b lsls r3, r3, #2 8015c6e: 4a13 ldr r2, [pc, #76] @ (8015cbc ) 8015c70: 441a add r2, r3 8015c72: 693b ldr r3, [r7, #16] 8015c74: 3304 adds r3, #4 8015c76: 4619 mov r1, r3 8015c78: 4610 mov r0, r2 8015c7a: f7fe f946 bl 8013f0a 8015c7e: e005 b.n 8015c8c } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8015c80: 693b ldr r3, [r7, #16] 8015c82: 3318 adds r3, #24 8015c84: 4619 mov r1, r3 8015c86: 480e ldr r0, [pc, #56] @ (8015cc0 ) 8015c88: f7fe f93f bl 8013f0a } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 8015c8c: 693b ldr r3, [r7, #16] 8015c8e: 6ada ldr r2, [r3, #44] @ 0x2c 8015c90: 4b0c ldr r3, [pc, #48] @ (8015cc4 ) 8015c92: 681b ldr r3, [r3, #0] 8015c94: 6adb ldr r3, [r3, #44] @ 0x2c 8015c96: 429a cmp r2, r3 8015c98: d905 bls.n 8015ca6 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 8015c9a: 2301 movs r3, #1 8015c9c: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 8015c9e: 4b0a ldr r3, [pc, #40] @ (8015cc8 ) 8015ca0: 2201 movs r2, #1 8015ca2: 601a str r2, [r3, #0] 8015ca4: e001 b.n 8015caa } else { xReturn = pdFALSE; 8015ca6: 2300 movs r3, #0 8015ca8: 617b str r3, [r7, #20] } return xReturn; 8015caa: 697b ldr r3, [r7, #20] } 8015cac: 4618 mov r0, r3 8015cae: 3718 adds r7, #24 8015cb0: 46bd mov sp, r7 8015cb2: bd80 pop {r7, pc} 8015cb4: 24002b3c .word 0x24002b3c 8015cb8: 24002b1c .word 0x24002b1c 8015cbc: 24002644 .word 0x24002644 8015cc0: 24002ad4 .word 0x24002ad4 8015cc4: 24002640 .word 0x24002640 8015cc8: 24002b28 .word 0x24002b28 08015ccc : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8015ccc: b580 push {r7, lr} 8015cce: b084 sub sp, #16 8015cd0: af00 add r7, sp, #0 8015cd2: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 8015cd4: 687b ldr r3, [r7, #4] 8015cd6: 2b00 cmp r3, #0 8015cd8: d10b bne.n 8015cf2 __asm volatile 8015cda: f04f 0350 mov.w r3, #80 @ 0x50 8015cde: f383 8811 msr BASEPRI, r3 8015ce2: f3bf 8f6f isb sy 8015ce6: f3bf 8f4f dsb sy 8015cea: 60fb str r3, [r7, #12] } 8015cec: bf00 nop 8015cee: bf00 nop 8015cf0: e7fd b.n 8015cee taskENTER_CRITICAL(); 8015cf2: f001 fb09 bl 8017308 { pxTimeOut->xOverflowCount = xNumOfOverflows; 8015cf6: 4b07 ldr r3, [pc, #28] @ (8015d14 ) 8015cf8: 681a ldr r2, [r3, #0] 8015cfa: 687b ldr r3, [r7, #4] 8015cfc: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8015cfe: 4b06 ldr r3, [pc, #24] @ (8015d18 ) 8015d00: 681a ldr r2, [r3, #0] 8015d02: 687b ldr r3, [r7, #4] 8015d04: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 8015d06: f001 fb31 bl 801736c } 8015d0a: bf00 nop 8015d0c: 3710 adds r7, #16 8015d0e: 46bd mov sp, r7 8015d10: bd80 pop {r7, pc} 8015d12: bf00 nop 8015d14: 24002b2c .word 0x24002b2c 8015d18: 24002b18 .word 0x24002b18 08015d1c : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8015d1c: b480 push {r7} 8015d1e: b083 sub sp, #12 8015d20: af00 add r7, sp, #0 8015d22: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 8015d24: 4b06 ldr r3, [pc, #24] @ (8015d40 ) 8015d26: 681a ldr r2, [r3, #0] 8015d28: 687b ldr r3, [r7, #4] 8015d2a: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8015d2c: 4b05 ldr r3, [pc, #20] @ (8015d44 ) 8015d2e: 681a ldr r2, [r3, #0] 8015d30: 687b ldr r3, [r7, #4] 8015d32: 605a str r2, [r3, #4] } 8015d34: bf00 nop 8015d36: 370c adds r7, #12 8015d38: 46bd mov sp, r7 8015d3a: f85d 7b04 ldr.w r7, [sp], #4 8015d3e: 4770 bx lr 8015d40: 24002b2c .word 0x24002b2c 8015d44: 24002b18 .word 0x24002b18 08015d48 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8015d48: b580 push {r7, lr} 8015d4a: b088 sub sp, #32 8015d4c: af00 add r7, sp, #0 8015d4e: 6078 str r0, [r7, #4] 8015d50: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 8015d52: 687b ldr r3, [r7, #4] 8015d54: 2b00 cmp r3, #0 8015d56: d10b bne.n 8015d70 __asm volatile 8015d58: f04f 0350 mov.w r3, #80 @ 0x50 8015d5c: f383 8811 msr BASEPRI, r3 8015d60: f3bf 8f6f isb sy 8015d64: f3bf 8f4f dsb sy 8015d68: 613b str r3, [r7, #16] } 8015d6a: bf00 nop 8015d6c: bf00 nop 8015d6e: e7fd b.n 8015d6c configASSERT( pxTicksToWait ); 8015d70: 683b ldr r3, [r7, #0] 8015d72: 2b00 cmp r3, #0 8015d74: d10b bne.n 8015d8e __asm volatile 8015d76: f04f 0350 mov.w r3, #80 @ 0x50 8015d7a: f383 8811 msr BASEPRI, r3 8015d7e: f3bf 8f6f isb sy 8015d82: f3bf 8f4f dsb sy 8015d86: 60fb str r3, [r7, #12] } 8015d88: bf00 nop 8015d8a: bf00 nop 8015d8c: e7fd b.n 8015d8a taskENTER_CRITICAL(); 8015d8e: f001 fabb bl 8017308 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 8015d92: 4b1d ldr r3, [pc, #116] @ (8015e08 ) 8015d94: 681b ldr r3, [r3, #0] 8015d96: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8015d98: 687b ldr r3, [r7, #4] 8015d9a: 685b ldr r3, [r3, #4] 8015d9c: 69ba ldr r2, [r7, #24] 8015d9e: 1ad3 subs r3, r2, r3 8015da0: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 8015da2: 683b ldr r3, [r7, #0] 8015da4: 681b ldr r3, [r3, #0] 8015da6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015daa: d102 bne.n 8015db2 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8015dac: 2300 movs r3, #0 8015dae: 61fb str r3, [r7, #28] 8015db0: e023 b.n 8015dfa } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 8015db2: 687b ldr r3, [r7, #4] 8015db4: 681a ldr r2, [r3, #0] 8015db6: 4b15 ldr r3, [pc, #84] @ (8015e0c ) 8015db8: 681b ldr r3, [r3, #0] 8015dba: 429a cmp r2, r3 8015dbc: d007 beq.n 8015dce 8015dbe: 687b ldr r3, [r7, #4] 8015dc0: 685b ldr r3, [r3, #4] 8015dc2: 69ba ldr r2, [r7, #24] 8015dc4: 429a cmp r2, r3 8015dc6: d302 bcc.n 8015dce /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 8015dc8: 2301 movs r3, #1 8015dca: 61fb str r3, [r7, #28] 8015dcc: e015 b.n 8015dfa } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 8015dce: 683b ldr r3, [r7, #0] 8015dd0: 681b ldr r3, [r3, #0] 8015dd2: 697a ldr r2, [r7, #20] 8015dd4: 429a cmp r2, r3 8015dd6: d20b bcs.n 8015df0 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 8015dd8: 683b ldr r3, [r7, #0] 8015dda: 681a ldr r2, [r3, #0] 8015ddc: 697b ldr r3, [r7, #20] 8015dde: 1ad2 subs r2, r2, r3 8015de0: 683b ldr r3, [r7, #0] 8015de2: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 8015de4: 6878 ldr r0, [r7, #4] 8015de6: f7ff ff99 bl 8015d1c xReturn = pdFALSE; 8015dea: 2300 movs r3, #0 8015dec: 61fb str r3, [r7, #28] 8015dee: e004 b.n 8015dfa } else { *pxTicksToWait = 0; 8015df0: 683b ldr r3, [r7, #0] 8015df2: 2200 movs r2, #0 8015df4: 601a str r2, [r3, #0] xReturn = pdTRUE; 8015df6: 2301 movs r3, #1 8015df8: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 8015dfa: f001 fab7 bl 801736c return xReturn; 8015dfe: 69fb ldr r3, [r7, #28] } 8015e00: 4618 mov r0, r3 8015e02: 3720 adds r7, #32 8015e04: 46bd mov sp, r7 8015e06: bd80 pop {r7, pc} 8015e08: 24002b18 .word 0x24002b18 8015e0c: 24002b2c .word 0x24002b2c 08015e10 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 8015e10: b480 push {r7} 8015e12: af00 add r7, sp, #0 xYieldPending = pdTRUE; 8015e14: 4b03 ldr r3, [pc, #12] @ (8015e24 ) 8015e16: 2201 movs r2, #1 8015e18: 601a str r2, [r3, #0] } 8015e1a: bf00 nop 8015e1c: 46bd mov sp, r7 8015e1e: f85d 7b04 ldr.w r7, [sp], #4 8015e22: 4770 bx lr 8015e24: 24002b28 .word 0x24002b28 08015e28 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8015e28: b580 push {r7, lr} 8015e2a: b082 sub sp, #8 8015e2c: af00 add r7, sp, #0 8015e2e: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8015e30: f000 f852 bl 8015ed8 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 8015e34: 4b06 ldr r3, [pc, #24] @ (8015e50 ) 8015e36: 681b ldr r3, [r3, #0] 8015e38: 2b01 cmp r3, #1 8015e3a: d9f9 bls.n 8015e30 { taskYIELD(); 8015e3c: 4b05 ldr r3, [pc, #20] @ (8015e54 ) 8015e3e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015e42: 601a str r2, [r3, #0] 8015e44: f3bf 8f4f dsb sy 8015e48: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 8015e4c: e7f0 b.n 8015e30 8015e4e: bf00 nop 8015e50: 24002644 .word 0x24002644 8015e54: e000ed04 .word 0xe000ed04 08015e58 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8015e58: b580 push {r7, lr} 8015e5a: b082 sub sp, #8 8015e5c: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8015e5e: 2300 movs r3, #0 8015e60: 607b str r3, [r7, #4] 8015e62: e00c b.n 8015e7e { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8015e64: 687a ldr r2, [r7, #4] 8015e66: 4613 mov r3, r2 8015e68: 009b lsls r3, r3, #2 8015e6a: 4413 add r3, r2 8015e6c: 009b lsls r3, r3, #2 8015e6e: 4a12 ldr r2, [pc, #72] @ (8015eb8 ) 8015e70: 4413 add r3, r2 8015e72: 4618 mov r0, r3 8015e74: f7fe f81c bl 8013eb0 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8015e78: 687b ldr r3, [r7, #4] 8015e7a: 3301 adds r3, #1 8015e7c: 607b str r3, [r7, #4] 8015e7e: 687b ldr r3, [r7, #4] 8015e80: 2b37 cmp r3, #55 @ 0x37 8015e82: d9ef bls.n 8015e64 } vListInitialise( &xDelayedTaskList1 ); 8015e84: 480d ldr r0, [pc, #52] @ (8015ebc ) 8015e86: f7fe f813 bl 8013eb0 vListInitialise( &xDelayedTaskList2 ); 8015e8a: 480d ldr r0, [pc, #52] @ (8015ec0 ) 8015e8c: f7fe f810 bl 8013eb0 vListInitialise( &xPendingReadyList ); 8015e90: 480c ldr r0, [pc, #48] @ (8015ec4 ) 8015e92: f7fe f80d bl 8013eb0 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 8015e96: 480c ldr r0, [pc, #48] @ (8015ec8 ) 8015e98: f7fe f80a bl 8013eb0 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8015e9c: 480b ldr r0, [pc, #44] @ (8015ecc ) 8015e9e: f7fe f807 bl 8013eb0 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8015ea2: 4b0b ldr r3, [pc, #44] @ (8015ed0 ) 8015ea4: 4a05 ldr r2, [pc, #20] @ (8015ebc ) 8015ea6: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8015ea8: 4b0a ldr r3, [pc, #40] @ (8015ed4 ) 8015eaa: 4a05 ldr r2, [pc, #20] @ (8015ec0 ) 8015eac: 601a str r2, [r3, #0] } 8015eae: bf00 nop 8015eb0: 3708 adds r7, #8 8015eb2: 46bd mov sp, r7 8015eb4: bd80 pop {r7, pc} 8015eb6: bf00 nop 8015eb8: 24002644 .word 0x24002644 8015ebc: 24002aa4 .word 0x24002aa4 8015ec0: 24002ab8 .word 0x24002ab8 8015ec4: 24002ad4 .word 0x24002ad4 8015ec8: 24002ae8 .word 0x24002ae8 8015ecc: 24002b00 .word 0x24002b00 8015ed0: 24002acc .word 0x24002acc 8015ed4: 24002ad0 .word 0x24002ad0 08015ed8 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 8015ed8: b580 push {r7, lr} 8015eda: b082 sub sp, #8 8015edc: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8015ede: e019 b.n 8015f14 { taskENTER_CRITICAL(); 8015ee0: f001 fa12 bl 8017308 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015ee4: 4b10 ldr r3, [pc, #64] @ (8015f28 ) 8015ee6: 68db ldr r3, [r3, #12] 8015ee8: 68db ldr r3, [r3, #12] 8015eea: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8015eec: 687b ldr r3, [r7, #4] 8015eee: 3304 adds r3, #4 8015ef0: 4618 mov r0, r3 8015ef2: f7fe f867 bl 8013fc4 --uxCurrentNumberOfTasks; 8015ef6: 4b0d ldr r3, [pc, #52] @ (8015f2c ) 8015ef8: 681b ldr r3, [r3, #0] 8015efa: 3b01 subs r3, #1 8015efc: 4a0b ldr r2, [pc, #44] @ (8015f2c ) 8015efe: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 8015f00: 4b0b ldr r3, [pc, #44] @ (8015f30 ) 8015f02: 681b ldr r3, [r3, #0] 8015f04: 3b01 subs r3, #1 8015f06: 4a0a ldr r2, [pc, #40] @ (8015f30 ) 8015f08: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 8015f0a: f001 fa2f bl 801736c prvDeleteTCB( pxTCB ); 8015f0e: 6878 ldr r0, [r7, #4] 8015f10: f000 f810 bl 8015f34 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 8015f14: 4b06 ldr r3, [pc, #24] @ (8015f30 ) 8015f16: 681b ldr r3, [r3, #0] 8015f18: 2b00 cmp r3, #0 8015f1a: d1e1 bne.n 8015ee0 } } #endif /* INCLUDE_vTaskDelete */ } 8015f1c: bf00 nop 8015f1e: bf00 nop 8015f20: 3708 adds r7, #8 8015f22: 46bd mov sp, r7 8015f24: bd80 pop {r7, pc} 8015f26: bf00 nop 8015f28: 24002ae8 .word 0x24002ae8 8015f2c: 24002b14 .word 0x24002b14 8015f30: 24002afc .word 0x24002afc 08015f34 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 8015f34: b580 push {r7, lr} 8015f36: b084 sub sp, #16 8015f38: af00 add r7, sp, #0 8015f3a: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 8015f3c: 687b ldr r3, [r7, #4] 8015f3e: 3354 adds r3, #84 @ 0x54 8015f40: 4618 mov r0, r3 8015f42: f001 fe21 bl 8017b88 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8015f46: 687b ldr r3, [r7, #4] 8015f48: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015f4c: 2b00 cmp r3, #0 8015f4e: d108 bne.n 8015f62 { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 8015f50: 687b ldr r3, [r7, #4] 8015f52: 6b1b ldr r3, [r3, #48] @ 0x30 8015f54: 4618 mov r0, r3 8015f56: f001 fbc7 bl 80176e8 vPortFree( pxTCB ); 8015f5a: 6878 ldr r0, [r7, #4] 8015f5c: f001 fbc4 bl 80176e8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8015f60: e019 b.n 8015f96 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8015f62: 687b ldr r3, [r7, #4] 8015f64: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015f68: 2b01 cmp r3, #1 8015f6a: d103 bne.n 8015f74 vPortFree( pxTCB ); 8015f6c: 6878 ldr r0, [r7, #4] 8015f6e: f001 fbbb bl 80176e8 } 8015f72: e010 b.n 8015f96 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8015f74: 687b ldr r3, [r7, #4] 8015f76: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8015f7a: 2b02 cmp r3, #2 8015f7c: d00b beq.n 8015f96 __asm volatile 8015f7e: f04f 0350 mov.w r3, #80 @ 0x50 8015f82: f383 8811 msr BASEPRI, r3 8015f86: f3bf 8f6f isb sy 8015f8a: f3bf 8f4f dsb sy 8015f8e: 60fb str r3, [r7, #12] } 8015f90: bf00 nop 8015f92: bf00 nop 8015f94: e7fd b.n 8015f92 } 8015f96: bf00 nop 8015f98: 3710 adds r7, #16 8015f9a: 46bd mov sp, r7 8015f9c: bd80 pop {r7, pc} ... 08015fa0 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8015fa0: b480 push {r7} 8015fa2: b083 sub sp, #12 8015fa4: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8015fa6: 4b0c ldr r3, [pc, #48] @ (8015fd8 ) 8015fa8: 681b ldr r3, [r3, #0] 8015faa: 681b ldr r3, [r3, #0] 8015fac: 2b00 cmp r3, #0 8015fae: d104 bne.n 8015fba { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8015fb0: 4b0a ldr r3, [pc, #40] @ (8015fdc ) 8015fb2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8015fb6: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8015fb8: e008 b.n 8015fcc ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8015fba: 4b07 ldr r3, [pc, #28] @ (8015fd8 ) 8015fbc: 681b ldr r3, [r3, #0] 8015fbe: 68db ldr r3, [r3, #12] 8015fc0: 68db ldr r3, [r3, #12] 8015fc2: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 8015fc4: 687b ldr r3, [r7, #4] 8015fc6: 685b ldr r3, [r3, #4] 8015fc8: 4a04 ldr r2, [pc, #16] @ (8015fdc ) 8015fca: 6013 str r3, [r2, #0] } 8015fcc: bf00 nop 8015fce: 370c adds r7, #12 8015fd0: 46bd mov sp, r7 8015fd2: f85d 7b04 ldr.w r7, [sp], #4 8015fd6: 4770 bx lr 8015fd8: 24002acc .word 0x24002acc 8015fdc: 24002b34 .word 0x24002b34 08015fe0 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 8015fe0: b480 push {r7} 8015fe2: b083 sub sp, #12 8015fe4: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 8015fe6: 4b05 ldr r3, [pc, #20] @ (8015ffc ) 8015fe8: 681b ldr r3, [r3, #0] 8015fea: 607b str r3, [r7, #4] return xReturn; 8015fec: 687b ldr r3, [r7, #4] } 8015fee: 4618 mov r0, r3 8015ff0: 370c adds r7, #12 8015ff2: 46bd mov sp, r7 8015ff4: f85d 7b04 ldr.w r7, [sp], #4 8015ff8: 4770 bx lr 8015ffa: bf00 nop 8015ffc: 24002640 .word 0x24002640 08016000 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8016000: b480 push {r7} 8016002: b083 sub sp, #12 8016004: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8016006: 4b0b ldr r3, [pc, #44] @ (8016034 ) 8016008: 681b ldr r3, [r3, #0] 801600a: 2b00 cmp r3, #0 801600c: d102 bne.n 8016014 { xReturn = taskSCHEDULER_NOT_STARTED; 801600e: 2301 movs r3, #1 8016010: 607b str r3, [r7, #4] 8016012: e008 b.n 8016026 } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8016014: 4b08 ldr r3, [pc, #32] @ (8016038 ) 8016016: 681b ldr r3, [r3, #0] 8016018: 2b00 cmp r3, #0 801601a: d102 bne.n 8016022 { xReturn = taskSCHEDULER_RUNNING; 801601c: 2302 movs r3, #2 801601e: 607b str r3, [r7, #4] 8016020: e001 b.n 8016026 } else { xReturn = taskSCHEDULER_SUSPENDED; 8016022: 2300 movs r3, #0 8016024: 607b str r3, [r7, #4] } } return xReturn; 8016026: 687b ldr r3, [r7, #4] } 8016028: 4618 mov r0, r3 801602a: 370c adds r7, #12 801602c: 46bd mov sp, r7 801602e: f85d 7b04 ldr.w r7, [sp], #4 8016032: 4770 bx lr 8016034: 24002b20 .word 0x24002b20 8016038: 24002b3c .word 0x24002b3c 0801603c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 801603c: b580 push {r7, lr} 801603e: b084 sub sp, #16 8016040: af00 add r7, sp, #0 8016042: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8016044: 687b ldr r3, [r7, #4] 8016046: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8016048: 2300 movs r3, #0 801604a: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 801604c: 687b ldr r3, [r7, #4] 801604e: 2b00 cmp r3, #0 8016050: d051 beq.n 80160f6 { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8016052: 68bb ldr r3, [r7, #8] 8016054: 6ada ldr r2, [r3, #44] @ 0x2c 8016056: 4b2a ldr r3, [pc, #168] @ (8016100 ) 8016058: 681b ldr r3, [r3, #0] 801605a: 6adb ldr r3, [r3, #44] @ 0x2c 801605c: 429a cmp r2, r3 801605e: d241 bcs.n 80160e4 { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016060: 68bb ldr r3, [r7, #8] 8016062: 699b ldr r3, [r3, #24] 8016064: 2b00 cmp r3, #0 8016066: db06 blt.n 8016076 { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016068: 4b25 ldr r3, [pc, #148] @ (8016100 ) 801606a: 681b ldr r3, [r3, #0] 801606c: 6adb ldr r3, [r3, #44] @ 0x2c 801606e: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016072: 68bb ldr r3, [r7, #8] 8016074: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8016076: 68bb ldr r3, [r7, #8] 8016078: 6959 ldr r1, [r3, #20] 801607a: 68bb ldr r3, [r7, #8] 801607c: 6ada ldr r2, [r3, #44] @ 0x2c 801607e: 4613 mov r3, r2 8016080: 009b lsls r3, r3, #2 8016082: 4413 add r3, r2 8016084: 009b lsls r3, r3, #2 8016086: 4a1f ldr r2, [pc, #124] @ (8016104 ) 8016088: 4413 add r3, r2 801608a: 4299 cmp r1, r3 801608c: d122 bne.n 80160d4 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 801608e: 68bb ldr r3, [r7, #8] 8016090: 3304 adds r3, #4 8016092: 4618 mov r0, r3 8016094: f7fd ff96 bl 8013fc4 { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016098: 4b19 ldr r3, [pc, #100] @ (8016100 ) 801609a: 681b ldr r3, [r3, #0] 801609c: 6ada ldr r2, [r3, #44] @ 0x2c 801609e: 68bb ldr r3, [r7, #8] 80160a0: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 80160a2: 68bb ldr r3, [r7, #8] 80160a4: 6ada ldr r2, [r3, #44] @ 0x2c 80160a6: 4b18 ldr r3, [pc, #96] @ (8016108 ) 80160a8: 681b ldr r3, [r3, #0] 80160aa: 429a cmp r2, r3 80160ac: d903 bls.n 80160b6 80160ae: 68bb ldr r3, [r7, #8] 80160b0: 6adb ldr r3, [r3, #44] @ 0x2c 80160b2: 4a15 ldr r2, [pc, #84] @ (8016108 ) 80160b4: 6013 str r3, [r2, #0] 80160b6: 68bb ldr r3, [r7, #8] 80160b8: 6ada ldr r2, [r3, #44] @ 0x2c 80160ba: 4613 mov r3, r2 80160bc: 009b lsls r3, r3, #2 80160be: 4413 add r3, r2 80160c0: 009b lsls r3, r3, #2 80160c2: 4a10 ldr r2, [pc, #64] @ (8016104 ) 80160c4: 441a add r2, r3 80160c6: 68bb ldr r3, [r7, #8] 80160c8: 3304 adds r3, #4 80160ca: 4619 mov r1, r3 80160cc: 4610 mov r0, r2 80160ce: f7fd ff1c bl 8013f0a 80160d2: e004 b.n 80160de } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 80160d4: 4b0a ldr r3, [pc, #40] @ (8016100 ) 80160d6: 681b ldr r3, [r3, #0] 80160d8: 6ada ldr r2, [r3, #44] @ 0x2c 80160da: 68bb ldr r3, [r7, #8] 80160dc: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 80160de: 2301 movs r3, #1 80160e0: 60fb str r3, [r7, #12] 80160e2: e008 b.n 80160f6 } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 80160e4: 68bb ldr r3, [r7, #8] 80160e6: 6cda ldr r2, [r3, #76] @ 0x4c 80160e8: 4b05 ldr r3, [pc, #20] @ (8016100 ) 80160ea: 681b ldr r3, [r3, #0] 80160ec: 6adb ldr r3, [r3, #44] @ 0x2c 80160ee: 429a cmp r2, r3 80160f0: d201 bcs.n 80160f6 current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 80160f2: 2301 movs r3, #1 80160f4: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 80160f6: 68fb ldr r3, [r7, #12] } 80160f8: 4618 mov r0, r3 80160fa: 3710 adds r7, #16 80160fc: 46bd mov sp, r7 80160fe: bd80 pop {r7, pc} 8016100: 24002640 .word 0x24002640 8016104: 24002644 .word 0x24002644 8016108: 24002b1c .word 0x24002b1c 0801610c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 801610c: b580 push {r7, lr} 801610e: b086 sub sp, #24 8016110: af00 add r7, sp, #0 8016112: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8016114: 687b ldr r3, [r7, #4] 8016116: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8016118: 2300 movs r3, #0 801611a: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 801611c: 687b ldr r3, [r7, #4] 801611e: 2b00 cmp r3, #0 8016120: d058 beq.n 80161d4 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8016122: 4b2f ldr r3, [pc, #188] @ (80161e0 ) 8016124: 681b ldr r3, [r3, #0] 8016126: 693a ldr r2, [r7, #16] 8016128: 429a cmp r2, r3 801612a: d00b beq.n 8016144 __asm volatile 801612c: f04f 0350 mov.w r3, #80 @ 0x50 8016130: f383 8811 msr BASEPRI, r3 8016134: f3bf 8f6f isb sy 8016138: f3bf 8f4f dsb sy 801613c: 60fb str r3, [r7, #12] } 801613e: bf00 nop 8016140: bf00 nop 8016142: e7fd b.n 8016140 configASSERT( pxTCB->uxMutexesHeld ); 8016144: 693b ldr r3, [r7, #16] 8016146: 6d1b ldr r3, [r3, #80] @ 0x50 8016148: 2b00 cmp r3, #0 801614a: d10b bne.n 8016164 __asm volatile 801614c: f04f 0350 mov.w r3, #80 @ 0x50 8016150: f383 8811 msr BASEPRI, r3 8016154: f3bf 8f6f isb sy 8016158: f3bf 8f4f dsb sy 801615c: 60bb str r3, [r7, #8] } 801615e: bf00 nop 8016160: bf00 nop 8016162: e7fd b.n 8016160 ( pxTCB->uxMutexesHeld )--; 8016164: 693b ldr r3, [r7, #16] 8016166: 6d1b ldr r3, [r3, #80] @ 0x50 8016168: 1e5a subs r2, r3, #1 801616a: 693b ldr r3, [r7, #16] 801616c: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 801616e: 693b ldr r3, [r7, #16] 8016170: 6ada ldr r2, [r3, #44] @ 0x2c 8016172: 693b ldr r3, [r7, #16] 8016174: 6cdb ldr r3, [r3, #76] @ 0x4c 8016176: 429a cmp r2, r3 8016178: d02c beq.n 80161d4 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 801617a: 693b ldr r3, [r7, #16] 801617c: 6d1b ldr r3, [r3, #80] @ 0x50 801617e: 2b00 cmp r3, #0 8016180: d128 bne.n 80161d4 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016182: 693b ldr r3, [r7, #16] 8016184: 3304 adds r3, #4 8016186: 4618 mov r0, r3 8016188: f7fd ff1c bl 8013fc4 } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 801618c: 693b ldr r3, [r7, #16] 801618e: 6cda ldr r2, [r3, #76] @ 0x4c 8016190: 693b ldr r3, [r7, #16] 8016192: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016194: 693b ldr r3, [r7, #16] 8016196: 6adb ldr r3, [r3, #44] @ 0x2c 8016198: f1c3 0238 rsb r2, r3, #56 @ 0x38 801619c: 693b ldr r3, [r7, #16] 801619e: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 80161a0: 693b ldr r3, [r7, #16] 80161a2: 6ada ldr r2, [r3, #44] @ 0x2c 80161a4: 4b0f ldr r3, [pc, #60] @ (80161e4 ) 80161a6: 681b ldr r3, [r3, #0] 80161a8: 429a cmp r2, r3 80161aa: d903 bls.n 80161b4 80161ac: 693b ldr r3, [r7, #16] 80161ae: 6adb ldr r3, [r3, #44] @ 0x2c 80161b0: 4a0c ldr r2, [pc, #48] @ (80161e4 ) 80161b2: 6013 str r3, [r2, #0] 80161b4: 693b ldr r3, [r7, #16] 80161b6: 6ada ldr r2, [r3, #44] @ 0x2c 80161b8: 4613 mov r3, r2 80161ba: 009b lsls r3, r3, #2 80161bc: 4413 add r3, r2 80161be: 009b lsls r3, r3, #2 80161c0: 4a09 ldr r2, [pc, #36] @ (80161e8 ) 80161c2: 441a add r2, r3 80161c4: 693b ldr r3, [r7, #16] 80161c6: 3304 adds r3, #4 80161c8: 4619 mov r1, r3 80161ca: 4610 mov r0, r2 80161cc: f7fd fe9d bl 8013f0a in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 80161d0: 2301 movs r3, #1 80161d2: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 80161d4: 697b ldr r3, [r7, #20] } 80161d6: 4618 mov r0, r3 80161d8: 3718 adds r7, #24 80161da: 46bd mov sp, r7 80161dc: bd80 pop {r7, pc} 80161de: bf00 nop 80161e0: 24002640 .word 0x24002640 80161e4: 24002b1c .word 0x24002b1c 80161e8: 24002644 .word 0x24002644 080161ec : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 80161ec: b580 push {r7, lr} 80161ee: b088 sub sp, #32 80161f0: af00 add r7, sp, #0 80161f2: 6078 str r0, [r7, #4] 80161f4: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 80161f6: 687b ldr r3, [r7, #4] 80161f8: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 80161fa: 2301 movs r3, #1 80161fc: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 80161fe: 687b ldr r3, [r7, #4] 8016200: 2b00 cmp r3, #0 8016202: d06c beq.n 80162de { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8016204: 69bb ldr r3, [r7, #24] 8016206: 6d1b ldr r3, [r3, #80] @ 0x50 8016208: 2b00 cmp r3, #0 801620a: d10b bne.n 8016224 __asm volatile 801620c: f04f 0350 mov.w r3, #80 @ 0x50 8016210: f383 8811 msr BASEPRI, r3 8016214: f3bf 8f6f isb sy 8016218: f3bf 8f4f dsb sy 801621c: 60fb str r3, [r7, #12] } 801621e: bf00 nop 8016220: bf00 nop 8016222: e7fd b.n 8016220 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8016224: 69bb ldr r3, [r7, #24] 8016226: 6cdb ldr r3, [r3, #76] @ 0x4c 8016228: 683a ldr r2, [r7, #0] 801622a: 429a cmp r2, r3 801622c: d902 bls.n 8016234 { uxPriorityToUse = uxHighestPriorityWaitingTask; 801622e: 683b ldr r3, [r7, #0] 8016230: 61fb str r3, [r7, #28] 8016232: e002 b.n 801623a } else { uxPriorityToUse = pxTCB->uxBasePriority; 8016234: 69bb ldr r3, [r7, #24] 8016236: 6cdb ldr r3, [r3, #76] @ 0x4c 8016238: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 801623a: 69bb ldr r3, [r7, #24] 801623c: 6adb ldr r3, [r3, #44] @ 0x2c 801623e: 69fa ldr r2, [r7, #28] 8016240: 429a cmp r2, r3 8016242: d04c beq.n 80162de { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8016244: 69bb ldr r3, [r7, #24] 8016246: 6d1b ldr r3, [r3, #80] @ 0x50 8016248: 697a ldr r2, [r7, #20] 801624a: 429a cmp r2, r3 801624c: d147 bne.n 80162de { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 801624e: 4b26 ldr r3, [pc, #152] @ (80162e8 ) 8016250: 681b ldr r3, [r3, #0] 8016252: 69ba ldr r2, [r7, #24] 8016254: 429a cmp r2, r3 8016256: d10b bne.n 8016270 __asm volatile 8016258: f04f 0350 mov.w r3, #80 @ 0x50 801625c: f383 8811 msr BASEPRI, r3 8016260: f3bf 8f6f isb sy 8016264: f3bf 8f4f dsb sy 8016268: 60bb str r3, [r7, #8] } 801626a: bf00 nop 801626c: bf00 nop 801626e: e7fd b.n 801626c /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 8016270: 69bb ldr r3, [r7, #24] 8016272: 6adb ldr r3, [r3, #44] @ 0x2c 8016274: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 8016276: 69bb ldr r3, [r7, #24] 8016278: 69fa ldr r2, [r7, #28] 801627a: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 801627c: 69bb ldr r3, [r7, #24] 801627e: 699b ldr r3, [r3, #24] 8016280: 2b00 cmp r3, #0 8016282: db04 blt.n 801628e { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016284: 69fb ldr r3, [r7, #28] 8016286: f1c3 0238 rsb r2, r3, #56 @ 0x38 801628a: 69bb ldr r3, [r7, #24] 801628c: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 801628e: 69bb ldr r3, [r7, #24] 8016290: 6959 ldr r1, [r3, #20] 8016292: 693a ldr r2, [r7, #16] 8016294: 4613 mov r3, r2 8016296: 009b lsls r3, r3, #2 8016298: 4413 add r3, r2 801629a: 009b lsls r3, r3, #2 801629c: 4a13 ldr r2, [pc, #76] @ (80162ec ) 801629e: 4413 add r3, r2 80162a0: 4299 cmp r1, r3 80162a2: d11c bne.n 80162de { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80162a4: 69bb ldr r3, [r7, #24] 80162a6: 3304 adds r3, #4 80162a8: 4618 mov r0, r3 80162aa: f7fd fe8b bl 8013fc4 else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 80162ae: 69bb ldr r3, [r7, #24] 80162b0: 6ada ldr r2, [r3, #44] @ 0x2c 80162b2: 4b0f ldr r3, [pc, #60] @ (80162f0 ) 80162b4: 681b ldr r3, [r3, #0] 80162b6: 429a cmp r2, r3 80162b8: d903 bls.n 80162c2 80162ba: 69bb ldr r3, [r7, #24] 80162bc: 6adb ldr r3, [r3, #44] @ 0x2c 80162be: 4a0c ldr r2, [pc, #48] @ (80162f0 ) 80162c0: 6013 str r3, [r2, #0] 80162c2: 69bb ldr r3, [r7, #24] 80162c4: 6ada ldr r2, [r3, #44] @ 0x2c 80162c6: 4613 mov r3, r2 80162c8: 009b lsls r3, r3, #2 80162ca: 4413 add r3, r2 80162cc: 009b lsls r3, r3, #2 80162ce: 4a07 ldr r2, [pc, #28] @ (80162ec ) 80162d0: 441a add r2, r3 80162d2: 69bb ldr r3, [r7, #24] 80162d4: 3304 adds r3, #4 80162d6: 4619 mov r1, r3 80162d8: 4610 mov r0, r2 80162da: f7fd fe16 bl 8013f0a } else { mtCOVERAGE_TEST_MARKER(); } } 80162de: bf00 nop 80162e0: 3720 adds r7, #32 80162e2: 46bd mov sp, r7 80162e4: bd80 pop {r7, pc} 80162e6: bf00 nop 80162e8: 24002640 .word 0x24002640 80162ec: 24002644 .word 0x24002644 80162f0: 24002b1c .word 0x24002b1c 080162f4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 80162f4: b480 push {r7} 80162f6: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 80162f8: 4b07 ldr r3, [pc, #28] @ (8016318 ) 80162fa: 681b ldr r3, [r3, #0] 80162fc: 2b00 cmp r3, #0 80162fe: d004 beq.n 801630a { ( pxCurrentTCB->uxMutexesHeld )++; 8016300: 4b05 ldr r3, [pc, #20] @ (8016318 ) 8016302: 681b ldr r3, [r3, #0] 8016304: 6d1a ldr r2, [r3, #80] @ 0x50 8016306: 3201 adds r2, #1 8016308: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 801630a: 4b03 ldr r3, [pc, #12] @ (8016318 ) 801630c: 681b ldr r3, [r3, #0] } 801630e: 4618 mov r0, r3 8016310: 46bd mov sp, r7 8016312: f85d 7b04 ldr.w r7, [sp], #4 8016316: 4770 bx lr 8016318: 24002640 .word 0x24002640 0801631c : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 801631c: b580 push {r7, lr} 801631e: b086 sub sp, #24 8016320: af00 add r7, sp, #0 8016322: 60f8 str r0, [r7, #12] 8016324: 60b9 str r1, [r7, #8] 8016326: 607a str r2, [r7, #4] 8016328: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 801632a: f000 ffed bl 8017308 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 801632e: 4b29 ldr r3, [pc, #164] @ (80163d4 ) 8016330: 681b ldr r3, [r3, #0] 8016332: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016336: b2db uxtb r3, r3 8016338: 2b02 cmp r3, #2 801633a: d01c beq.n 8016376 { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 801633c: 4b25 ldr r3, [pc, #148] @ (80163d4 ) 801633e: 681b ldr r3, [r3, #0] 8016340: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016344: 68fa ldr r2, [r7, #12] 8016346: 43d2 mvns r2, r2 8016348: 400a ands r2, r1 801634a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 801634e: 4b21 ldr r3, [pc, #132] @ (80163d4 ) 8016350: 681b ldr r3, [r3, #0] 8016352: 2201 movs r2, #1 8016354: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 8016358: 683b ldr r3, [r7, #0] 801635a: 2b00 cmp r3, #0 801635c: d00b beq.n 8016376 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 801635e: 2101 movs r1, #1 8016360: 6838 ldr r0, [r7, #0] 8016362: f000 fa09 bl 8016778 /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 8016366: 4b1c ldr r3, [pc, #112] @ (80163d8 ) 8016368: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801636c: 601a str r2, [r3, #0] 801636e: f3bf 8f4f dsb sy 8016372: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016376: f000 fff9 bl 801736c taskENTER_CRITICAL(); 801637a: f000 ffc5 bl 8017308 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 801637e: 687b ldr r3, [r7, #4] 8016380: 2b00 cmp r3, #0 8016382: d005 beq.n 8016390 { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 8016384: 4b13 ldr r3, [pc, #76] @ (80163d4 ) 8016386: 681b ldr r3, [r3, #0] 8016388: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 801638c: 687b ldr r3, [r7, #4] 801638e: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016390: 4b10 ldr r3, [pc, #64] @ (80163d4 ) 8016392: 681b ldr r3, [r3, #0] 8016394: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016398: b2db uxtb r3, r3 801639a: 2b02 cmp r3, #2 801639c: d002 beq.n 80163a4 { /* A notification was not received. */ xReturn = pdFALSE; 801639e: 2300 movs r3, #0 80163a0: 617b str r3, [r7, #20] 80163a2: e00a b.n 80163ba } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 80163a4: 4b0b ldr r3, [pc, #44] @ (80163d4 ) 80163a6: 681b ldr r3, [r3, #0] 80163a8: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 80163ac: 68ba ldr r2, [r7, #8] 80163ae: 43d2 mvns r2, r2 80163b0: 400a ands r2, r1 80163b2: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 80163b6: 2301 movs r3, #1 80163b8: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 80163ba: 4b06 ldr r3, [pc, #24] @ (80163d4 ) 80163bc: 681b ldr r3, [r3, #0] 80163be: 2200 movs r2, #0 80163c0: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 80163c4: f000 ffd2 bl 801736c return xReturn; 80163c8: 697b ldr r3, [r7, #20] } 80163ca: 4618 mov r0, r3 80163cc: 3718 adds r7, #24 80163ce: 46bd mov sp, r7 80163d0: bd80 pop {r7, pc} 80163d2: bf00 nop 80163d4: 24002640 .word 0x24002640 80163d8: e000ed04 .word 0xe000ed04 080163dc : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 80163dc: b580 push {r7, lr} 80163de: b08a sub sp, #40 @ 0x28 80163e0: af00 add r7, sp, #0 80163e2: 60f8 str r0, [r7, #12] 80163e4: 60b9 str r1, [r7, #8] 80163e6: 603b str r3, [r7, #0] 80163e8: 4613 mov r3, r2 80163ea: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 80163ec: 2301 movs r3, #1 80163ee: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 80163f0: 68fb ldr r3, [r7, #12] 80163f2: 2b00 cmp r3, #0 80163f4: d10b bne.n 801640e __asm volatile 80163f6: f04f 0350 mov.w r3, #80 @ 0x50 80163fa: f383 8811 msr BASEPRI, r3 80163fe: f3bf 8f6f isb sy 8016402: f3bf 8f4f dsb sy 8016406: 61bb str r3, [r7, #24] } 8016408: bf00 nop 801640a: bf00 nop 801640c: e7fd b.n 801640a pxTCB = xTaskToNotify; 801640e: 68fb ldr r3, [r7, #12] 8016410: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 8016412: f000 ff79 bl 8017308 { if( pulPreviousNotificationValue != NULL ) 8016416: 683b ldr r3, [r7, #0] 8016418: 2b00 cmp r3, #0 801641a: d004 beq.n 8016426 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 801641c: 6a3b ldr r3, [r7, #32] 801641e: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016422: 683b ldr r3, [r7, #0] 8016424: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016426: 6a3b ldr r3, [r7, #32] 8016428: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801642c: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 801642e: 6a3b ldr r3, [r7, #32] 8016430: 2202 movs r2, #2 8016432: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016436: 79fb ldrb r3, [r7, #7] 8016438: 2b04 cmp r3, #4 801643a: d82e bhi.n 801649a 801643c: a201 add r2, pc, #4 @ (adr r2, 8016444 ) 801643e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016442: bf00 nop 8016444: 080164bf .word 0x080164bf 8016448: 08016459 .word 0x08016459 801644c: 0801646b .word 0x0801646b 8016450: 0801647b .word 0x0801647b 8016454: 08016485 .word 0x08016485 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016458: 6a3b ldr r3, [r7, #32] 801645a: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 801645e: 68bb ldr r3, [r7, #8] 8016460: 431a orrs r2, r3 8016462: 6a3b ldr r3, [r7, #32] 8016464: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016468: e02c b.n 80164c4 case eIncrement : ( pxTCB->ulNotifiedValue )++; 801646a: 6a3b ldr r3, [r7, #32] 801646c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016470: 1c5a adds r2, r3, #1 8016472: 6a3b ldr r3, [r7, #32] 8016474: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016478: e024 b.n 80164c4 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 801647a: 6a3b ldr r3, [r7, #32] 801647c: 68ba ldr r2, [r7, #8] 801647e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016482: e01f b.n 80164c4 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016484: 7ffb ldrb r3, [r7, #31] 8016486: 2b02 cmp r3, #2 8016488: d004 beq.n 8016494 { pxTCB->ulNotifiedValue = ulValue; 801648a: 6a3b ldr r3, [r7, #32] 801648c: 68ba ldr r2, [r7, #8] 801648e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016492: e017 b.n 80164c4 xReturn = pdFAIL; 8016494: 2300 movs r3, #0 8016496: 627b str r3, [r7, #36] @ 0x24 break; 8016498: e014 b.n 80164c4 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 801649a: 6a3b ldr r3, [r7, #32] 801649c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 80164a0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80164a4: d00d beq.n 80164c2 __asm volatile 80164a6: f04f 0350 mov.w r3, #80 @ 0x50 80164aa: f383 8811 msr BASEPRI, r3 80164ae: f3bf 8f6f isb sy 80164b2: f3bf 8f4f dsb sy 80164b6: 617b str r3, [r7, #20] } 80164b8: bf00 nop 80164ba: bf00 nop 80164bc: e7fd b.n 80164ba break; 80164be: bf00 nop 80164c0: e000 b.n 80164c4 break; 80164c2: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 80164c4: 7ffb ldrb r3, [r7, #31] 80164c6: 2b01 cmp r3, #1 80164c8: d13b bne.n 8016542 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80164ca: 6a3b ldr r3, [r7, #32] 80164cc: 3304 adds r3, #4 80164ce: 4618 mov r0, r3 80164d0: f7fd fd78 bl 8013fc4 prvAddTaskToReadyList( pxTCB ); 80164d4: 6a3b ldr r3, [r7, #32] 80164d6: 6ada ldr r2, [r3, #44] @ 0x2c 80164d8: 4b1d ldr r3, [pc, #116] @ (8016550 ) 80164da: 681b ldr r3, [r3, #0] 80164dc: 429a cmp r2, r3 80164de: d903 bls.n 80164e8 80164e0: 6a3b ldr r3, [r7, #32] 80164e2: 6adb ldr r3, [r3, #44] @ 0x2c 80164e4: 4a1a ldr r2, [pc, #104] @ (8016550 ) 80164e6: 6013 str r3, [r2, #0] 80164e8: 6a3b ldr r3, [r7, #32] 80164ea: 6ada ldr r2, [r3, #44] @ 0x2c 80164ec: 4613 mov r3, r2 80164ee: 009b lsls r3, r3, #2 80164f0: 4413 add r3, r2 80164f2: 009b lsls r3, r3, #2 80164f4: 4a17 ldr r2, [pc, #92] @ (8016554 ) 80164f6: 441a add r2, r3 80164f8: 6a3b ldr r3, [r7, #32] 80164fa: 3304 adds r3, #4 80164fc: 4619 mov r1, r3 80164fe: 4610 mov r0, r2 8016500: f7fd fd03 bl 8013f0a /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8016504: 6a3b ldr r3, [r7, #32] 8016506: 6a9b ldr r3, [r3, #40] @ 0x28 8016508: 2b00 cmp r3, #0 801650a: d00b beq.n 8016524 __asm volatile 801650c: f04f 0350 mov.w r3, #80 @ 0x50 8016510: f383 8811 msr BASEPRI, r3 8016514: f3bf 8f6f isb sy 8016518: f3bf 8f4f dsb sy 801651c: 613b str r3, [r7, #16] } 801651e: bf00 nop 8016520: bf00 nop 8016522: e7fd b.n 8016520 earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016524: 6a3b ldr r3, [r7, #32] 8016526: 6ada ldr r2, [r3, #44] @ 0x2c 8016528: 4b0b ldr r3, [pc, #44] @ (8016558 ) 801652a: 681b ldr r3, [r3, #0] 801652c: 6adb ldr r3, [r3, #44] @ 0x2c 801652e: 429a cmp r2, r3 8016530: d907 bls.n 8016542 { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016532: 4b0a ldr r3, [pc, #40] @ (801655c ) 8016534: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016538: 601a str r2, [r3, #0] 801653a: f3bf 8f4f dsb sy 801653e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016542: f000 ff13 bl 801736c return xReturn; 8016546: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016548: 4618 mov r0, r3 801654a: 3728 adds r7, #40 @ 0x28 801654c: 46bd mov sp, r7 801654e: bd80 pop {r7, pc} 8016550: 24002b1c .word 0x24002b1c 8016554: 24002644 .word 0x24002644 8016558: 24002640 .word 0x24002640 801655c: e000ed04 .word 0xe000ed04 08016560 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 8016560: b580 push {r7, lr} 8016562: b08e sub sp, #56 @ 0x38 8016564: af00 add r7, sp, #0 8016566: 60f8 str r0, [r7, #12] 8016568: 60b9 str r1, [r7, #8] 801656a: 603b str r3, [r7, #0] 801656c: 4613 mov r3, r2 801656e: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8016570: 2301 movs r3, #1 8016572: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016574: 68fb ldr r3, [r7, #12] 8016576: 2b00 cmp r3, #0 8016578: d10b bne.n 8016592 __asm volatile 801657a: f04f 0350 mov.w r3, #80 @ 0x50 801657e: f383 8811 msr BASEPRI, r3 8016582: f3bf 8f6f isb sy 8016586: f3bf 8f4f dsb sy 801658a: 627b str r3, [r7, #36] @ 0x24 } 801658c: bf00 nop 801658e: bf00 nop 8016590: e7fd b.n 801658e below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8016592: f000 ff99 bl 80174c8 pxTCB = xTaskToNotify; 8016596: 68fb ldr r3, [r7, #12] 8016598: 633b str r3, [r7, #48] @ 0x30 __asm volatile 801659a: f3ef 8211 mrs r2, BASEPRI 801659e: f04f 0350 mov.w r3, #80 @ 0x50 80165a2: f383 8811 msr BASEPRI, r3 80165a6: f3bf 8f6f isb sy 80165aa: f3bf 8f4f dsb sy 80165ae: 623a str r2, [r7, #32] 80165b0: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 80165b2: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80165b4: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 80165b6: 683b ldr r3, [r7, #0] 80165b8: 2b00 cmp r3, #0 80165ba: d004 beq.n 80165c6 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 80165bc: 6b3b ldr r3, [r7, #48] @ 0x30 80165be: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 80165c2: 683b ldr r3, [r7, #0] 80165c4: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 80165c6: 6b3b ldr r3, [r7, #48] @ 0x30 80165c8: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 80165cc: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 80165d0: 6b3b ldr r3, [r7, #48] @ 0x30 80165d2: 2202 movs r2, #2 80165d4: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 80165d8: 79fb ldrb r3, [r7, #7] 80165da: 2b04 cmp r3, #4 80165dc: d82e bhi.n 801663c 80165de: a201 add r2, pc, #4 @ (adr r2, 80165e4 ) 80165e0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80165e4: 08016661 .word 0x08016661 80165e8: 080165f9 .word 0x080165f9 80165ec: 0801660b .word 0x0801660b 80165f0: 0801661b .word 0x0801661b 80165f4: 08016625 .word 0x08016625 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 80165f8: 6b3b ldr r3, [r7, #48] @ 0x30 80165fa: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 80165fe: 68bb ldr r3, [r7, #8] 8016600: 431a orrs r2, r3 8016602: 6b3b ldr r3, [r7, #48] @ 0x30 8016604: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016608: e02d b.n 8016666 case eIncrement : ( pxTCB->ulNotifiedValue )++; 801660a: 6b3b ldr r3, [r7, #48] @ 0x30 801660c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016610: 1c5a adds r2, r3, #1 8016612: 6b3b ldr r3, [r7, #48] @ 0x30 8016614: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016618: e025 b.n 8016666 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 801661a: 6b3b ldr r3, [r7, #48] @ 0x30 801661c: 68ba ldr r2, [r7, #8] 801661e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016622: e020 b.n 8016666 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016624: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8016628: 2b02 cmp r3, #2 801662a: d004 beq.n 8016636 { pxTCB->ulNotifiedValue = ulValue; 801662c: 6b3b ldr r3, [r7, #48] @ 0x30 801662e: 68ba ldr r2, [r7, #8] 8016630: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016634: e017 b.n 8016666 xReturn = pdFAIL; 8016636: 2300 movs r3, #0 8016638: 637b str r3, [r7, #52] @ 0x34 break; 801663a: e014 b.n 8016666 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 801663c: 6b3b ldr r3, [r7, #48] @ 0x30 801663e: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016642: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016646: d00d beq.n 8016664 __asm volatile 8016648: f04f 0350 mov.w r3, #80 @ 0x50 801664c: f383 8811 msr BASEPRI, r3 8016650: f3bf 8f6f isb sy 8016654: f3bf 8f4f dsb sy 8016658: 61bb str r3, [r7, #24] } 801665a: bf00 nop 801665c: bf00 nop 801665e: e7fd b.n 801665c break; 8016660: bf00 nop 8016662: e000 b.n 8016666 break; 8016664: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8016666: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 801666a: 2b01 cmp r3, #1 801666c: d147 bne.n 80166fe { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 801666e: 6b3b ldr r3, [r7, #48] @ 0x30 8016670: 6a9b ldr r3, [r3, #40] @ 0x28 8016672: 2b00 cmp r3, #0 8016674: d00b beq.n 801668e __asm volatile 8016676: f04f 0350 mov.w r3, #80 @ 0x50 801667a: f383 8811 msr BASEPRI, r3 801667e: f3bf 8f6f isb sy 8016682: f3bf 8f4f dsb sy 8016686: 617b str r3, [r7, #20] } 8016688: bf00 nop 801668a: bf00 nop 801668c: e7fd b.n 801668a if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801668e: 4b21 ldr r3, [pc, #132] @ (8016714 ) 8016690: 681b ldr r3, [r3, #0] 8016692: 2b00 cmp r3, #0 8016694: d11d bne.n 80166d2 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016696: 6b3b ldr r3, [r7, #48] @ 0x30 8016698: 3304 adds r3, #4 801669a: 4618 mov r0, r3 801669c: f7fd fc92 bl 8013fc4 prvAddTaskToReadyList( pxTCB ); 80166a0: 6b3b ldr r3, [r7, #48] @ 0x30 80166a2: 6ada ldr r2, [r3, #44] @ 0x2c 80166a4: 4b1c ldr r3, [pc, #112] @ (8016718 ) 80166a6: 681b ldr r3, [r3, #0] 80166a8: 429a cmp r2, r3 80166aa: d903 bls.n 80166b4 80166ac: 6b3b ldr r3, [r7, #48] @ 0x30 80166ae: 6adb ldr r3, [r3, #44] @ 0x2c 80166b0: 4a19 ldr r2, [pc, #100] @ (8016718 ) 80166b2: 6013 str r3, [r2, #0] 80166b4: 6b3b ldr r3, [r7, #48] @ 0x30 80166b6: 6ada ldr r2, [r3, #44] @ 0x2c 80166b8: 4613 mov r3, r2 80166ba: 009b lsls r3, r3, #2 80166bc: 4413 add r3, r2 80166be: 009b lsls r3, r3, #2 80166c0: 4a16 ldr r2, [pc, #88] @ (801671c ) 80166c2: 441a add r2, r3 80166c4: 6b3b ldr r3, [r7, #48] @ 0x30 80166c6: 3304 adds r3, #4 80166c8: 4619 mov r1, r3 80166ca: 4610 mov r0, r2 80166cc: f7fd fc1d bl 8013f0a 80166d0: e005 b.n 80166de } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 80166d2: 6b3b ldr r3, [r7, #48] @ 0x30 80166d4: 3318 adds r3, #24 80166d6: 4619 mov r1, r3 80166d8: 4811 ldr r0, [pc, #68] @ (8016720 ) 80166da: f7fd fc16 bl 8013f0a } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80166de: 6b3b ldr r3, [r7, #48] @ 0x30 80166e0: 6ada ldr r2, [r3, #44] @ 0x2c 80166e2: 4b10 ldr r3, [pc, #64] @ (8016724 ) 80166e4: 681b ldr r3, [r3, #0] 80166e6: 6adb ldr r3, [r3, #44] @ 0x2c 80166e8: 429a cmp r2, r3 80166ea: d908 bls.n 80166fe { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80166ec: 6c3b ldr r3, [r7, #64] @ 0x40 80166ee: 2b00 cmp r3, #0 80166f0: d002 beq.n 80166f8 { *pxHigherPriorityTaskWoken = pdTRUE; 80166f2: 6c3b ldr r3, [r7, #64] @ 0x40 80166f4: 2201 movs r2, #1 80166f6: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80166f8: 4b0b ldr r3, [pc, #44] @ (8016728 ) 80166fa: 2201 movs r2, #1 80166fc: 601a str r2, [r3, #0] 80166fe: 6afb ldr r3, [r7, #44] @ 0x2c 8016700: 613b str r3, [r7, #16] __asm volatile 8016702: 693b ldr r3, [r7, #16] 8016704: f383 8811 msr BASEPRI, r3 } 8016708: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801670a: 6b7b ldr r3, [r7, #52] @ 0x34 } 801670c: 4618 mov r0, r3 801670e: 3738 adds r7, #56 @ 0x38 8016710: 46bd mov sp, r7 8016712: bd80 pop {r7, pc} 8016714: 24002b3c .word 0x24002b3c 8016718: 24002b1c .word 0x24002b1c 801671c: 24002644 .word 0x24002644 8016720: 24002ad4 .word 0x24002ad4 8016724: 24002640 .word 0x24002640 8016728: 24002b28 .word 0x24002b28 0801672c : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 801672c: b580 push {r7, lr} 801672e: b084 sub sp, #16 8016730: af00 add r7, sp, #0 8016732: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 8016734: 687b ldr r3, [r7, #4] 8016736: 2b00 cmp r3, #0 8016738: d102 bne.n 8016740 801673a: 4b0e ldr r3, [pc, #56] @ (8016774 ) 801673c: 681b ldr r3, [r3, #0] 801673e: e000 b.n 8016742 8016740: 687b ldr r3, [r7, #4] 8016742: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 8016744: f000 fde0 bl 8017308 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 8016748: 68bb ldr r3, [r7, #8] 801674a: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801674e: b2db uxtb r3, r3 8016750: 2b02 cmp r3, #2 8016752: d106 bne.n 8016762 { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8016754: 68bb ldr r3, [r7, #8] 8016756: 2200 movs r2, #0 8016758: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 801675c: 2301 movs r3, #1 801675e: 60fb str r3, [r7, #12] 8016760: e001 b.n 8016766 } else { xReturn = pdFAIL; 8016762: 2300 movs r3, #0 8016764: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8016766: f000 fe01 bl 801736c return xReturn; 801676a: 68fb ldr r3, [r7, #12] } 801676c: 4618 mov r0, r3 801676e: 3710 adds r7, #16 8016770: 46bd mov sp, r7 8016772: bd80 pop {r7, pc} 8016774: 24002640 .word 0x24002640 08016778 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8016778: b580 push {r7, lr} 801677a: b084 sub sp, #16 801677c: af00 add r7, sp, #0 801677e: 6078 str r0, [r7, #4] 8016780: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8016782: 4b21 ldr r3, [pc, #132] @ (8016808 ) 8016784: 681b ldr r3, [r3, #0] 8016786: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016788: 4b20 ldr r3, [pc, #128] @ (801680c ) 801678a: 681b ldr r3, [r3, #0] 801678c: 3304 adds r3, #4 801678e: 4618 mov r0, r3 8016790: f7fd fc18 bl 8013fc4 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8016794: 687b ldr r3, [r7, #4] 8016796: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801679a: d10a bne.n 80167b2 801679c: 683b ldr r3, [r7, #0] 801679e: 2b00 cmp r3, #0 80167a0: d007 beq.n 80167b2 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80167a2: 4b1a ldr r3, [pc, #104] @ (801680c ) 80167a4: 681b ldr r3, [r3, #0] 80167a6: 3304 adds r3, #4 80167a8: 4619 mov r1, r3 80167aa: 4819 ldr r0, [pc, #100] @ (8016810 ) 80167ac: f7fd fbad bl 8013f0a /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 80167b0: e026 b.n 8016800 xTimeToWake = xConstTickCount + xTicksToWait; 80167b2: 68fa ldr r2, [r7, #12] 80167b4: 687b ldr r3, [r7, #4] 80167b6: 4413 add r3, r2 80167b8: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 80167ba: 4b14 ldr r3, [pc, #80] @ (801680c ) 80167bc: 681b ldr r3, [r3, #0] 80167be: 68ba ldr r2, [r7, #8] 80167c0: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 80167c2: 68ba ldr r2, [r7, #8] 80167c4: 68fb ldr r3, [r7, #12] 80167c6: 429a cmp r2, r3 80167c8: d209 bcs.n 80167de vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80167ca: 4b12 ldr r3, [pc, #72] @ (8016814 ) 80167cc: 681a ldr r2, [r3, #0] 80167ce: 4b0f ldr r3, [pc, #60] @ (801680c ) 80167d0: 681b ldr r3, [r3, #0] 80167d2: 3304 adds r3, #4 80167d4: 4619 mov r1, r3 80167d6: 4610 mov r0, r2 80167d8: f7fd fbbb bl 8013f52 } 80167dc: e010 b.n 8016800 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80167de: 4b0e ldr r3, [pc, #56] @ (8016818 ) 80167e0: 681a ldr r2, [r3, #0] 80167e2: 4b0a ldr r3, [pc, #40] @ (801680c ) 80167e4: 681b ldr r3, [r3, #0] 80167e6: 3304 adds r3, #4 80167e8: 4619 mov r1, r3 80167ea: 4610 mov r0, r2 80167ec: f7fd fbb1 bl 8013f52 if( xTimeToWake < xNextTaskUnblockTime ) 80167f0: 4b0a ldr r3, [pc, #40] @ (801681c ) 80167f2: 681b ldr r3, [r3, #0] 80167f4: 68ba ldr r2, [r7, #8] 80167f6: 429a cmp r2, r3 80167f8: d202 bcs.n 8016800 xNextTaskUnblockTime = xTimeToWake; 80167fa: 4a08 ldr r2, [pc, #32] @ (801681c ) 80167fc: 68bb ldr r3, [r7, #8] 80167fe: 6013 str r3, [r2, #0] } 8016800: bf00 nop 8016802: 3710 adds r7, #16 8016804: 46bd mov sp, r7 8016806: bd80 pop {r7, pc} 8016808: 24002b18 .word 0x24002b18 801680c: 24002640 .word 0x24002640 8016810: 24002b00 .word 0x24002b00 8016814: 24002ad0 .word 0x24002ad0 8016818: 24002acc .word 0x24002acc 801681c: 24002b34 .word 0x24002b34 08016820 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8016820: b580 push {r7, lr} 8016822: b08a sub sp, #40 @ 0x28 8016824: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 8016826: 2300 movs r3, #0 8016828: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 801682a: f000 fbb1 bl 8016f90 if( xTimerQueue != NULL ) 801682e: 4b1d ldr r3, [pc, #116] @ (80168a4 ) 8016830: 681b ldr r3, [r3, #0] 8016832: 2b00 cmp r3, #0 8016834: d021 beq.n 801687a { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 8016836: 2300 movs r3, #0 8016838: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 801683a: 2300 movs r3, #0 801683c: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 801683e: 1d3a adds r2, r7, #4 8016840: f107 0108 add.w r1, r7, #8 8016844: f107 030c add.w r3, r7, #12 8016848: 4618 mov r0, r3 801684a: f7fd fb17 bl 8013e7c xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 801684e: 6879 ldr r1, [r7, #4] 8016850: 68bb ldr r3, [r7, #8] 8016852: 68fa ldr r2, [r7, #12] 8016854: 9202 str r2, [sp, #8] 8016856: 9301 str r3, [sp, #4] 8016858: 2302 movs r3, #2 801685a: 9300 str r3, [sp, #0] 801685c: 2300 movs r3, #0 801685e: 460a mov r2, r1 8016860: 4911 ldr r1, [pc, #68] @ (80168a8 ) 8016862: 4812 ldr r0, [pc, #72] @ (80168ac ) 8016864: f7fe fd2f bl 80152c6 8016868: 4603 mov r3, r0 801686a: 4a11 ldr r2, [pc, #68] @ (80168b0 ) 801686c: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 801686e: 4b10 ldr r3, [pc, #64] @ (80168b0 ) 8016870: 681b ldr r3, [r3, #0] 8016872: 2b00 cmp r3, #0 8016874: d001 beq.n 801687a { xReturn = pdPASS; 8016876: 2301 movs r3, #1 8016878: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 801687a: 697b ldr r3, [r7, #20] 801687c: 2b00 cmp r3, #0 801687e: d10b bne.n 8016898 __asm volatile 8016880: f04f 0350 mov.w r3, #80 @ 0x50 8016884: f383 8811 msr BASEPRI, r3 8016888: f3bf 8f6f isb sy 801688c: f3bf 8f4f dsb sy 8016890: 613b str r3, [r7, #16] } 8016892: bf00 nop 8016894: bf00 nop 8016896: e7fd b.n 8016894 return xReturn; 8016898: 697b ldr r3, [r7, #20] } 801689a: 4618 mov r0, r3 801689c: 3718 adds r7, #24 801689e: 46bd mov sp, r7 80168a0: bd80 pop {r7, pc} 80168a2: bf00 nop 80168a4: 24002b70 .word 0x24002b70 80168a8: 08018954 .word 0x08018954 80168ac: 08016b29 .word 0x08016b29 80168b0: 24002b74 .word 0x24002b74 080168b4 : TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) { 80168b4: b580 push {r7, lr} 80168b6: b088 sub sp, #32 80168b8: af02 add r7, sp, #8 80168ba: 60f8 str r0, [r7, #12] 80168bc: 60b9 str r1, [r7, #8] 80168be: 607a str r2, [r7, #4] 80168c0: 603b str r3, [r7, #0] Timer_t *pxNewTimer; pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 80168c2: 202c movs r0, #44 @ 0x2c 80168c4: f000 fe42 bl 801754c 80168c8: 6178 str r0, [r7, #20] if( pxNewTimer != NULL ) 80168ca: 697b ldr r3, [r7, #20] 80168cc: 2b00 cmp r3, #0 80168ce: d00d beq.n 80168ec { /* Status is thus far zero as the timer is not created statically and has not been started. The auto-reload bit may get set in prvInitialiseNewTimer. */ pxNewTimer->ucStatus = 0x00; 80168d0: 697b ldr r3, [r7, #20] 80168d2: 2200 movs r2, #0 80168d4: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 80168d8: 697b ldr r3, [r7, #20] 80168da: 9301 str r3, [sp, #4] 80168dc: 6a3b ldr r3, [r7, #32] 80168de: 9300 str r3, [sp, #0] 80168e0: 683b ldr r3, [r7, #0] 80168e2: 687a ldr r2, [r7, #4] 80168e4: 68b9 ldr r1, [r7, #8] 80168e6: 68f8 ldr r0, [r7, #12] 80168e8: f000 f845 bl 8016976 } return pxNewTimer; 80168ec: 697b ldr r3, [r7, #20] } 80168ee: 4618 mov r0, r3 80168f0: 3718 adds r7, #24 80168f2: 46bd mov sp, r7 80168f4: bd80 pop {r7, pc} 080168f6 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) { 80168f6: b580 push {r7, lr} 80168f8: b08a sub sp, #40 @ 0x28 80168fa: af02 add r7, sp, #8 80168fc: 60f8 str r0, [r7, #12] 80168fe: 60b9 str r1, [r7, #8] 8016900: 607a str r2, [r7, #4] 8016902: 603b str r3, [r7, #0] #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTimer_t equals the size of the real timer structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); 8016904: 232c movs r3, #44 @ 0x2c 8016906: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( Timer_t ) ); 8016908: 693b ldr r3, [r7, #16] 801690a: 2b2c cmp r3, #44 @ 0x2c 801690c: d00b beq.n 8016926 __asm volatile 801690e: f04f 0350 mov.w r3, #80 @ 0x50 8016912: f383 8811 msr BASEPRI, r3 8016916: f3bf 8f6f isb sy 801691a: f3bf 8f4f dsb sy 801691e: 61bb str r3, [r7, #24] } 8016920: bf00 nop 8016922: bf00 nop 8016924: e7fd b.n 8016922 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8016926: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); 8016928: 6afb ldr r3, [r7, #44] @ 0x2c 801692a: 2b00 cmp r3, #0 801692c: d10b bne.n 8016946 __asm volatile 801692e: f04f 0350 mov.w r3, #80 @ 0x50 8016932: f383 8811 msr BASEPRI, r3 8016936: f3bf 8f6f isb sy 801693a: f3bf 8f4f dsb sy 801693e: 617b str r3, [r7, #20] } 8016940: bf00 nop 8016942: bf00 nop 8016944: e7fd b.n 8016942 pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ 8016946: 6afb ldr r3, [r7, #44] @ 0x2c 8016948: 61fb str r3, [r7, #28] if( pxNewTimer != NULL ) 801694a: 69fb ldr r3, [r7, #28] 801694c: 2b00 cmp r3, #0 801694e: d00d beq.n 801696c { /* Timers can be created statically or dynamically so note this timer was created statically in case it is later deleted. The auto-reload bit may get set in prvInitialiseNewTimer(). */ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 8016950: 69fb ldr r3, [r7, #28] 8016952: 2202 movs r2, #2 8016954: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 8016958: 69fb ldr r3, [r7, #28] 801695a: 9301 str r3, [sp, #4] 801695c: 6abb ldr r3, [r7, #40] @ 0x28 801695e: 9300 str r3, [sp, #0] 8016960: 683b ldr r3, [r7, #0] 8016962: 687a ldr r2, [r7, #4] 8016964: 68b9 ldr r1, [r7, #8] 8016966: 68f8 ldr r0, [r7, #12] 8016968: f000 f805 bl 8016976 } return pxNewTimer; 801696c: 69fb ldr r3, [r7, #28] } 801696e: 4618 mov r0, r3 8016970: 3720 adds r7, #32 8016972: 46bd mov sp, r7 8016974: bd80 pop {r7, pc} 08016976 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) { 8016976: b580 push {r7, lr} 8016978: b086 sub sp, #24 801697a: af00 add r7, sp, #0 801697c: 60f8 str r0, [r7, #12] 801697e: 60b9 str r1, [r7, #8] 8016980: 607a str r2, [r7, #4] 8016982: 603b str r3, [r7, #0] /* 0 is not a valid value for xTimerPeriodInTicks. */ configASSERT( ( xTimerPeriodInTicks > 0 ) ); 8016984: 68bb ldr r3, [r7, #8] 8016986: 2b00 cmp r3, #0 8016988: d10b bne.n 80169a2 __asm volatile 801698a: f04f 0350 mov.w r3, #80 @ 0x50 801698e: f383 8811 msr BASEPRI, r3 8016992: f3bf 8f6f isb sy 8016996: f3bf 8f4f dsb sy 801699a: 617b str r3, [r7, #20] } 801699c: bf00 nop 801699e: bf00 nop 80169a0: e7fd b.n 801699e if( pxNewTimer != NULL ) 80169a2: 6a7b ldr r3, [r7, #36] @ 0x24 80169a4: 2b00 cmp r3, #0 80169a6: d01e beq.n 80169e6 { /* Ensure the infrastructure used by the timer service task has been created/initialised. */ prvCheckForValidListAndQueue(); 80169a8: f000 faf2 bl 8016f90 /* Initialise the timer structure members using the function parameters. */ pxNewTimer->pcTimerName = pcTimerName; 80169ac: 6a7b ldr r3, [r7, #36] @ 0x24 80169ae: 68fa ldr r2, [r7, #12] 80169b0: 601a str r2, [r3, #0] pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; 80169b2: 6a7b ldr r3, [r7, #36] @ 0x24 80169b4: 68ba ldr r2, [r7, #8] 80169b6: 619a str r2, [r3, #24] pxNewTimer->pvTimerID = pvTimerID; 80169b8: 6a7b ldr r3, [r7, #36] @ 0x24 80169ba: 683a ldr r2, [r7, #0] 80169bc: 61da str r2, [r3, #28] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 80169be: 6a7b ldr r3, [r7, #36] @ 0x24 80169c0: 6a3a ldr r2, [r7, #32] 80169c2: 621a str r2, [r3, #32] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 80169c4: 6a7b ldr r3, [r7, #36] @ 0x24 80169c6: 3304 adds r3, #4 80169c8: 4618 mov r0, r3 80169ca: f7fd fa91 bl 8013ef0 if( uxAutoReload != pdFALSE ) 80169ce: 687b ldr r3, [r7, #4] 80169d0: 2b00 cmp r3, #0 80169d2: d008 beq.n 80169e6 { pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 80169d4: 6a7b ldr r3, [r7, #36] @ 0x24 80169d6: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80169da: f043 0304 orr.w r3, r3, #4 80169de: b2da uxtb r2, r3 80169e0: 6a7b ldr r3, [r7, #36] @ 0x24 80169e2: f883 2028 strb.w r2, [r3, #40] @ 0x28 } traceTIMER_CREATE( pxNewTimer ); } } 80169e6: bf00 nop 80169e8: 3718 adds r7, #24 80169ea: 46bd mov sp, r7 80169ec: bd80 pop {r7, pc} ... 080169f0 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 80169f0: b580 push {r7, lr} 80169f2: b08a sub sp, #40 @ 0x28 80169f4: af00 add r7, sp, #0 80169f6: 60f8 str r0, [r7, #12] 80169f8: 60b9 str r1, [r7, #8] 80169fa: 607a str r2, [r7, #4] 80169fc: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 80169fe: 2300 movs r3, #0 8016a00: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 8016a02: 68fb ldr r3, [r7, #12] 8016a04: 2b00 cmp r3, #0 8016a06: d10b bne.n 8016a20 __asm volatile 8016a08: f04f 0350 mov.w r3, #80 @ 0x50 8016a0c: f383 8811 msr BASEPRI, r3 8016a10: f3bf 8f6f isb sy 8016a14: f3bf 8f4f dsb sy 8016a18: 623b str r3, [r7, #32] } 8016a1a: bf00 nop 8016a1c: bf00 nop 8016a1e: e7fd b.n 8016a1c /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8016a20: 4b19 ldr r3, [pc, #100] @ (8016a88 ) 8016a22: 681b ldr r3, [r3, #0] 8016a24: 2b00 cmp r3, #0 8016a26: d02a beq.n 8016a7e { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 8016a28: 68bb ldr r3, [r7, #8] 8016a2a: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 8016a2c: 687b ldr r3, [r7, #4] 8016a2e: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 8016a30: 68fb ldr r3, [r7, #12] 8016a32: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 8016a34: 68bb ldr r3, [r7, #8] 8016a36: 2b05 cmp r3, #5 8016a38: dc18 bgt.n 8016a6c { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 8016a3a: f7ff fae1 bl 8016000 8016a3e: 4603 mov r3, r0 8016a40: 2b02 cmp r3, #2 8016a42: d109 bne.n 8016a58 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 8016a44: 4b10 ldr r3, [pc, #64] @ (8016a88 ) 8016a46: 6818 ldr r0, [r3, #0] 8016a48: f107 0110 add.w r1, r7, #16 8016a4c: 2300 movs r3, #0 8016a4e: 6b3a ldr r2, [r7, #48] @ 0x30 8016a50: f7fd fce0 bl 8014414 8016a54: 6278 str r0, [r7, #36] @ 0x24 8016a56: e012 b.n 8016a7e } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 8016a58: 4b0b ldr r3, [pc, #44] @ (8016a88 ) 8016a5a: 6818 ldr r0, [r3, #0] 8016a5c: f107 0110 add.w r1, r7, #16 8016a60: 2300 movs r3, #0 8016a62: 2200 movs r2, #0 8016a64: f7fd fcd6 bl 8014414 8016a68: 6278 str r0, [r7, #36] @ 0x24 8016a6a: e008 b.n 8016a7e } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 8016a6c: 4b06 ldr r3, [pc, #24] @ (8016a88 ) 8016a6e: 6818 ldr r0, [r3, #0] 8016a70: f107 0110 add.w r1, r7, #16 8016a74: 2300 movs r3, #0 8016a76: 683a ldr r2, [r7, #0] 8016a78: f7fd fdce bl 8014618 8016a7c: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016a7e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016a80: 4618 mov r0, r3 8016a82: 3728 adds r7, #40 @ 0x28 8016a84: 46bd mov sp, r7 8016a86: bd80 pop {r7, pc} 8016a88: 24002b70 .word 0x24002b70 08016a8c : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 8016a8c: b580 push {r7, lr} 8016a8e: b088 sub sp, #32 8016a90: af02 add r7, sp, #8 8016a92: 6078 str r0, [r7, #4] 8016a94: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016a96: 4b23 ldr r3, [pc, #140] @ (8016b24 ) 8016a98: 681b ldr r3, [r3, #0] 8016a9a: 68db ldr r3, [r3, #12] 8016a9c: 68db ldr r3, [r3, #12] 8016a9e: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016aa0: 697b ldr r3, [r7, #20] 8016aa2: 3304 adds r3, #4 8016aa4: 4618 mov r0, r3 8016aa6: f7fd fa8d bl 8013fc4 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016aaa: 697b ldr r3, [r7, #20] 8016aac: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016ab0: f003 0304 and.w r3, r3, #4 8016ab4: 2b00 cmp r3, #0 8016ab6: d023 beq.n 8016b00 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 8016ab8: 697b ldr r3, [r7, #20] 8016aba: 699a ldr r2, [r3, #24] 8016abc: 687b ldr r3, [r7, #4] 8016abe: 18d1 adds r1, r2, r3 8016ac0: 687b ldr r3, [r7, #4] 8016ac2: 683a ldr r2, [r7, #0] 8016ac4: 6978 ldr r0, [r7, #20] 8016ac6: f000 f8d5 bl 8016c74 8016aca: 4603 mov r3, r0 8016acc: 2b00 cmp r3, #0 8016ace: d020 beq.n 8016b12 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8016ad0: 2300 movs r3, #0 8016ad2: 9300 str r3, [sp, #0] 8016ad4: 2300 movs r3, #0 8016ad6: 687a ldr r2, [r7, #4] 8016ad8: 2100 movs r1, #0 8016ada: 6978 ldr r0, [r7, #20] 8016adc: f7ff ff88 bl 80169f0 8016ae0: 6138 str r0, [r7, #16] configASSERT( xResult ); 8016ae2: 693b ldr r3, [r7, #16] 8016ae4: 2b00 cmp r3, #0 8016ae6: d114 bne.n 8016b12 __asm volatile 8016ae8: f04f 0350 mov.w r3, #80 @ 0x50 8016aec: f383 8811 msr BASEPRI, r3 8016af0: f3bf 8f6f isb sy 8016af4: f3bf 8f4f dsb sy 8016af8: 60fb str r3, [r7, #12] } 8016afa: bf00 nop 8016afc: bf00 nop 8016afe: e7fd b.n 8016afc mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8016b00: 697b ldr r3, [r7, #20] 8016b02: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016b06: f023 0301 bic.w r3, r3, #1 8016b0a: b2da uxtb r2, r3 8016b0c: 697b ldr r3, [r7, #20] 8016b0e: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016b12: 697b ldr r3, [r7, #20] 8016b14: 6a1b ldr r3, [r3, #32] 8016b16: 6978 ldr r0, [r7, #20] 8016b18: 4798 blx r3 } 8016b1a: bf00 nop 8016b1c: 3718 adds r7, #24 8016b1e: 46bd mov sp, r7 8016b20: bd80 pop {r7, pc} 8016b22: bf00 nop 8016b24: 24002b68 .word 0x24002b68 08016b28 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8016b28: b580 push {r7, lr} 8016b2a: b084 sub sp, #16 8016b2c: af00 add r7, sp, #0 8016b2e: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8016b30: f107 0308 add.w r3, r7, #8 8016b34: 4618 mov r0, r3 8016b36: f000 f859 bl 8016bec 8016b3a: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 8016b3c: 68bb ldr r3, [r7, #8] 8016b3e: 4619 mov r1, r3 8016b40: 68f8 ldr r0, [r7, #12] 8016b42: f000 f805 bl 8016b50 /* Empty the command queue. */ prvProcessReceivedCommands(); 8016b46: f000 f8d7 bl 8016cf8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8016b4a: bf00 nop 8016b4c: e7f0 b.n 8016b30 ... 08016b50 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8016b50: b580 push {r7, lr} 8016b52: b084 sub sp, #16 8016b54: af00 add r7, sp, #0 8016b56: 6078 str r0, [r7, #4] 8016b58: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 8016b5a: f7fe fe17 bl 801578c /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8016b5e: f107 0308 add.w r3, r7, #8 8016b62: 4618 mov r0, r3 8016b64: f000 f866 bl 8016c34 8016b68: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 8016b6a: 68bb ldr r3, [r7, #8] 8016b6c: 2b00 cmp r3, #0 8016b6e: d130 bne.n 8016bd2 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8016b70: 683b ldr r3, [r7, #0] 8016b72: 2b00 cmp r3, #0 8016b74: d10a bne.n 8016b8c 8016b76: 687a ldr r2, [r7, #4] 8016b78: 68fb ldr r3, [r7, #12] 8016b7a: 429a cmp r2, r3 8016b7c: d806 bhi.n 8016b8c { ( void ) xTaskResumeAll(); 8016b7e: f7fe fe13 bl 80157a8 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8016b82: 68f9 ldr r1, [r7, #12] 8016b84: 6878 ldr r0, [r7, #4] 8016b86: f7ff ff81 bl 8016a8c else { ( void ) xTaskResumeAll(); } } } 8016b8a: e024 b.n 8016bd6 if( xListWasEmpty != pdFALSE ) 8016b8c: 683b ldr r3, [r7, #0] 8016b8e: 2b00 cmp r3, #0 8016b90: d008 beq.n 8016ba4 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8016b92: 4b13 ldr r3, [pc, #76] @ (8016be0 ) 8016b94: 681b ldr r3, [r3, #0] 8016b96: 681b ldr r3, [r3, #0] 8016b98: 2b00 cmp r3, #0 8016b9a: d101 bne.n 8016ba0 8016b9c: 2301 movs r3, #1 8016b9e: e000 b.n 8016ba2 8016ba0: 2300 movs r3, #0 8016ba2: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 8016ba4: 4b0f ldr r3, [pc, #60] @ (8016be4 ) 8016ba6: 6818 ldr r0, [r3, #0] 8016ba8: 687a ldr r2, [r7, #4] 8016baa: 68fb ldr r3, [r7, #12] 8016bac: 1ad3 subs r3, r2, r3 8016bae: 683a ldr r2, [r7, #0] 8016bb0: 4619 mov r1, r3 8016bb2: f7fe f995 bl 8014ee0 if( xTaskResumeAll() == pdFALSE ) 8016bb6: f7fe fdf7 bl 80157a8 8016bba: 4603 mov r3, r0 8016bbc: 2b00 cmp r3, #0 8016bbe: d10a bne.n 8016bd6 portYIELD_WITHIN_API(); 8016bc0: 4b09 ldr r3, [pc, #36] @ (8016be8 ) 8016bc2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016bc6: 601a str r2, [r3, #0] 8016bc8: f3bf 8f4f dsb sy 8016bcc: f3bf 8f6f isb sy } 8016bd0: e001 b.n 8016bd6 ( void ) xTaskResumeAll(); 8016bd2: f7fe fde9 bl 80157a8 } 8016bd6: bf00 nop 8016bd8: 3710 adds r7, #16 8016bda: 46bd mov sp, r7 8016bdc: bd80 pop {r7, pc} 8016bde: bf00 nop 8016be0: 24002b6c .word 0x24002b6c 8016be4: 24002b70 .word 0x24002b70 8016be8: e000ed04 .word 0xe000ed04 08016bec : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 8016bec: b480 push {r7} 8016bee: b085 sub sp, #20 8016bf0: af00 add r7, sp, #0 8016bf2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 8016bf4: 4b0e ldr r3, [pc, #56] @ (8016c30 ) 8016bf6: 681b ldr r3, [r3, #0] 8016bf8: 681b ldr r3, [r3, #0] 8016bfa: 2b00 cmp r3, #0 8016bfc: d101 bne.n 8016c02 8016bfe: 2201 movs r2, #1 8016c00: e000 b.n 8016c04 8016c02: 2200 movs r2, #0 8016c04: 687b ldr r3, [r7, #4] 8016c06: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 8016c08: 687b ldr r3, [r7, #4] 8016c0a: 681b ldr r3, [r3, #0] 8016c0c: 2b00 cmp r3, #0 8016c0e: d105 bne.n 8016c1c { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8016c10: 4b07 ldr r3, [pc, #28] @ (8016c30 ) 8016c12: 681b ldr r3, [r3, #0] 8016c14: 68db ldr r3, [r3, #12] 8016c16: 681b ldr r3, [r3, #0] 8016c18: 60fb str r3, [r7, #12] 8016c1a: e001 b.n 8016c20 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8016c1c: 2300 movs r3, #0 8016c1e: 60fb str r3, [r7, #12] } return xNextExpireTime; 8016c20: 68fb ldr r3, [r7, #12] } 8016c22: 4618 mov r0, r3 8016c24: 3714 adds r7, #20 8016c26: 46bd mov sp, r7 8016c28: f85d 7b04 ldr.w r7, [sp], #4 8016c2c: 4770 bx lr 8016c2e: bf00 nop 8016c30: 24002b68 .word 0x24002b68 08016c34 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 8016c34: b580 push {r7, lr} 8016c36: b084 sub sp, #16 8016c38: af00 add r7, sp, #0 8016c3a: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 8016c3c: f7fe fe52 bl 80158e4 8016c40: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8016c42: 4b0b ldr r3, [pc, #44] @ (8016c70 ) 8016c44: 681b ldr r3, [r3, #0] 8016c46: 68fa ldr r2, [r7, #12] 8016c48: 429a cmp r2, r3 8016c4a: d205 bcs.n 8016c58 { prvSwitchTimerLists(); 8016c4c: f000 f93a bl 8016ec4 *pxTimerListsWereSwitched = pdTRUE; 8016c50: 687b ldr r3, [r7, #4] 8016c52: 2201 movs r2, #1 8016c54: 601a str r2, [r3, #0] 8016c56: e002 b.n 8016c5e } else { *pxTimerListsWereSwitched = pdFALSE; 8016c58: 687b ldr r3, [r7, #4] 8016c5a: 2200 movs r2, #0 8016c5c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 8016c5e: 4a04 ldr r2, [pc, #16] @ (8016c70 ) 8016c60: 68fb ldr r3, [r7, #12] 8016c62: 6013 str r3, [r2, #0] return xTimeNow; 8016c64: 68fb ldr r3, [r7, #12] } 8016c66: 4618 mov r0, r3 8016c68: 3710 adds r7, #16 8016c6a: 46bd mov sp, r7 8016c6c: bd80 pop {r7, pc} 8016c6e: bf00 nop 8016c70: 24002b78 .word 0x24002b78 08016c74 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8016c74: b580 push {r7, lr} 8016c76: b086 sub sp, #24 8016c78: af00 add r7, sp, #0 8016c7a: 60f8 str r0, [r7, #12] 8016c7c: 60b9 str r1, [r7, #8] 8016c7e: 607a str r2, [r7, #4] 8016c80: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8016c82: 2300 movs r3, #0 8016c84: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8016c86: 68fb ldr r3, [r7, #12] 8016c88: 68ba ldr r2, [r7, #8] 8016c8a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8016c8c: 68fb ldr r3, [r7, #12] 8016c8e: 68fa ldr r2, [r7, #12] 8016c90: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8016c92: 68ba ldr r2, [r7, #8] 8016c94: 687b ldr r3, [r7, #4] 8016c96: 429a cmp r2, r3 8016c98: d812 bhi.n 8016cc0 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016c9a: 687a ldr r2, [r7, #4] 8016c9c: 683b ldr r3, [r7, #0] 8016c9e: 1ad2 subs r2, r2, r3 8016ca0: 68fb ldr r3, [r7, #12] 8016ca2: 699b ldr r3, [r3, #24] 8016ca4: 429a cmp r2, r3 8016ca6: d302 bcc.n 8016cae { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8016ca8: 2301 movs r3, #1 8016caa: 617b str r3, [r7, #20] 8016cac: e01b b.n 8016ce6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 8016cae: 4b10 ldr r3, [pc, #64] @ (8016cf0 ) 8016cb0: 681a ldr r2, [r3, #0] 8016cb2: 68fb ldr r3, [r7, #12] 8016cb4: 3304 adds r3, #4 8016cb6: 4619 mov r1, r3 8016cb8: 4610 mov r0, r2 8016cba: f7fd f94a bl 8013f52 8016cbe: e012 b.n 8016ce6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 8016cc0: 687a ldr r2, [r7, #4] 8016cc2: 683b ldr r3, [r7, #0] 8016cc4: 429a cmp r2, r3 8016cc6: d206 bcs.n 8016cd6 8016cc8: 68ba ldr r2, [r7, #8] 8016cca: 683b ldr r3, [r7, #0] 8016ccc: 429a cmp r2, r3 8016cce: d302 bcc.n 8016cd6 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 8016cd0: 2301 movs r3, #1 8016cd2: 617b str r3, [r7, #20] 8016cd4: e007 b.n 8016ce6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8016cd6: 4b07 ldr r3, [pc, #28] @ (8016cf4 ) 8016cd8: 681a ldr r2, [r3, #0] 8016cda: 68fb ldr r3, [r7, #12] 8016cdc: 3304 adds r3, #4 8016cde: 4619 mov r1, r3 8016ce0: 4610 mov r0, r2 8016ce2: f7fd f936 bl 8013f52 } } return xProcessTimerNow; 8016ce6: 697b ldr r3, [r7, #20] } 8016ce8: 4618 mov r0, r3 8016cea: 3718 adds r7, #24 8016cec: 46bd mov sp, r7 8016cee: bd80 pop {r7, pc} 8016cf0: 24002b6c .word 0x24002b6c 8016cf4: 24002b68 .word 0x24002b68 08016cf8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 8016cf8: b580 push {r7, lr} 8016cfa: b08e sub sp, #56 @ 0x38 8016cfc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8016cfe: e0ce b.n 8016e9e { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 8016d00: 687b ldr r3, [r7, #4] 8016d02: 2b00 cmp r3, #0 8016d04: da19 bge.n 8016d3a { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 8016d06: 1d3b adds r3, r7, #4 8016d08: 3304 adds r3, #4 8016d0a: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 8016d0c: 6afb ldr r3, [r7, #44] @ 0x2c 8016d0e: 2b00 cmp r3, #0 8016d10: d10b bne.n 8016d2a __asm volatile 8016d12: f04f 0350 mov.w r3, #80 @ 0x50 8016d16: f383 8811 msr BASEPRI, r3 8016d1a: f3bf 8f6f isb sy 8016d1e: f3bf 8f4f dsb sy 8016d22: 61fb str r3, [r7, #28] } 8016d24: bf00 nop 8016d26: bf00 nop 8016d28: e7fd b.n 8016d26 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 8016d2a: 6afb ldr r3, [r7, #44] @ 0x2c 8016d2c: 681b ldr r3, [r3, #0] 8016d2e: 6afa ldr r2, [r7, #44] @ 0x2c 8016d30: 6850 ldr r0, [r2, #4] 8016d32: 6afa ldr r2, [r7, #44] @ 0x2c 8016d34: 6892 ldr r2, [r2, #8] 8016d36: 4611 mov r1, r2 8016d38: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 8016d3a: 687b ldr r3, [r7, #4] 8016d3c: 2b00 cmp r3, #0 8016d3e: f2c0 80ae blt.w 8016e9e { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8016d42: 68fb ldr r3, [r7, #12] 8016d44: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8016d46: 6abb ldr r3, [r7, #40] @ 0x28 8016d48: 695b ldr r3, [r3, #20] 8016d4a: 2b00 cmp r3, #0 8016d4c: d004 beq.n 8016d58 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016d4e: 6abb ldr r3, [r7, #40] @ 0x28 8016d50: 3304 adds r3, #4 8016d52: 4618 mov r0, r3 8016d54: f7fd f936 bl 8013fc4 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8016d58: 463b mov r3, r7 8016d5a: 4618 mov r0, r3 8016d5c: f7ff ff6a bl 8016c34 8016d60: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 8016d62: 687b ldr r3, [r7, #4] 8016d64: 2b09 cmp r3, #9 8016d66: f200 8097 bhi.w 8016e98 8016d6a: a201 add r2, pc, #4 @ (adr r2, 8016d70 ) 8016d6c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016d70: 08016d99 .word 0x08016d99 8016d74: 08016d99 .word 0x08016d99 8016d78: 08016d99 .word 0x08016d99 8016d7c: 08016e0f .word 0x08016e0f 8016d80: 08016e23 .word 0x08016e23 8016d84: 08016e6f .word 0x08016e6f 8016d88: 08016d99 .word 0x08016d99 8016d8c: 08016d99 .word 0x08016d99 8016d90: 08016e0f .word 0x08016e0f 8016d94: 08016e23 .word 0x08016e23 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8016d98: 6abb ldr r3, [r7, #40] @ 0x28 8016d9a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016d9e: f043 0301 orr.w r3, r3, #1 8016da2: b2da uxtb r2, r3 8016da4: 6abb ldr r3, [r7, #40] @ 0x28 8016da6: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 8016daa: 68ba ldr r2, [r7, #8] 8016dac: 6abb ldr r3, [r7, #40] @ 0x28 8016dae: 699b ldr r3, [r3, #24] 8016db0: 18d1 adds r1, r2, r3 8016db2: 68bb ldr r3, [r7, #8] 8016db4: 6a7a ldr r2, [r7, #36] @ 0x24 8016db6: 6ab8 ldr r0, [r7, #40] @ 0x28 8016db8: f7ff ff5c bl 8016c74 8016dbc: 4603 mov r3, r0 8016dbe: 2b00 cmp r3, #0 8016dc0: d06c beq.n 8016e9c { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016dc2: 6abb ldr r3, [r7, #40] @ 0x28 8016dc4: 6a1b ldr r3, [r3, #32] 8016dc6: 6ab8 ldr r0, [r7, #40] @ 0x28 8016dc8: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016dca: 6abb ldr r3, [r7, #40] @ 0x28 8016dcc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016dd0: f003 0304 and.w r3, r3, #4 8016dd4: 2b00 cmp r3, #0 8016dd6: d061 beq.n 8016e9c { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 8016dd8: 68ba ldr r2, [r7, #8] 8016dda: 6abb ldr r3, [r7, #40] @ 0x28 8016ddc: 699b ldr r3, [r3, #24] 8016dde: 441a add r2, r3 8016de0: 2300 movs r3, #0 8016de2: 9300 str r3, [sp, #0] 8016de4: 2300 movs r3, #0 8016de6: 2100 movs r1, #0 8016de8: 6ab8 ldr r0, [r7, #40] @ 0x28 8016dea: f7ff fe01 bl 80169f0 8016dee: 6238 str r0, [r7, #32] configASSERT( xResult ); 8016df0: 6a3b ldr r3, [r7, #32] 8016df2: 2b00 cmp r3, #0 8016df4: d152 bne.n 8016e9c __asm volatile 8016df6: f04f 0350 mov.w r3, #80 @ 0x50 8016dfa: f383 8811 msr BASEPRI, r3 8016dfe: f3bf 8f6f isb sy 8016e02: f3bf 8f4f dsb sy 8016e06: 61bb str r3, [r7, #24] } 8016e08: bf00 nop 8016e0a: bf00 nop 8016e0c: e7fd b.n 8016e0a break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8016e0e: 6abb ldr r3, [r7, #40] @ 0x28 8016e10: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016e14: f023 0301 bic.w r3, r3, #1 8016e18: b2da uxtb r2, r3 8016e1a: 6abb ldr r3, [r7, #40] @ 0x28 8016e1c: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8016e20: e03d b.n 8016e9e case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8016e22: 6abb ldr r3, [r7, #40] @ 0x28 8016e24: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016e28: f043 0301 orr.w r3, r3, #1 8016e2c: b2da uxtb r2, r3 8016e2e: 6abb ldr r3, [r7, #40] @ 0x28 8016e30: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 8016e34: 68ba ldr r2, [r7, #8] 8016e36: 6abb ldr r3, [r7, #40] @ 0x28 8016e38: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 8016e3a: 6abb ldr r3, [r7, #40] @ 0x28 8016e3c: 699b ldr r3, [r3, #24] 8016e3e: 2b00 cmp r3, #0 8016e40: d10b bne.n 8016e5a __asm volatile 8016e42: f04f 0350 mov.w r3, #80 @ 0x50 8016e46: f383 8811 msr BASEPRI, r3 8016e4a: f3bf 8f6f isb sy 8016e4e: f3bf 8f4f dsb sy 8016e52: 617b str r3, [r7, #20] } 8016e54: bf00 nop 8016e56: bf00 nop 8016e58: e7fd b.n 8016e56 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 8016e5a: 6abb ldr r3, [r7, #40] @ 0x28 8016e5c: 699a ldr r2, [r3, #24] 8016e5e: 6a7b ldr r3, [r7, #36] @ 0x24 8016e60: 18d1 adds r1, r2, r3 8016e62: 6a7b ldr r3, [r7, #36] @ 0x24 8016e64: 6a7a ldr r2, [r7, #36] @ 0x24 8016e66: 6ab8 ldr r0, [r7, #40] @ 0x28 8016e68: f7ff ff04 bl 8016c74 break; 8016e6c: e017 b.n 8016e9e #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 8016e6e: 6abb ldr r3, [r7, #40] @ 0x28 8016e70: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016e74: f003 0302 and.w r3, r3, #2 8016e78: 2b00 cmp r3, #0 8016e7a: d103 bne.n 8016e84 { vPortFree( pxTimer ); 8016e7c: 6ab8 ldr r0, [r7, #40] @ 0x28 8016e7e: f000 fc33 bl 80176e8 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 8016e82: e00c b.n 8016e9e pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8016e84: 6abb ldr r3, [r7, #40] @ 0x28 8016e86: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016e8a: f023 0301 bic.w r3, r3, #1 8016e8e: b2da uxtb r2, r3 8016e90: 6abb ldr r3, [r7, #40] @ 0x28 8016e92: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8016e96: e002 b.n 8016e9e default : /* Don't expect to get here. */ break; 8016e98: bf00 nop 8016e9a: e000 b.n 8016e9e break; 8016e9c: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8016e9e: 4b08 ldr r3, [pc, #32] @ (8016ec0 ) 8016ea0: 681b ldr r3, [r3, #0] 8016ea2: 1d39 adds r1, r7, #4 8016ea4: 2200 movs r2, #0 8016ea6: 4618 mov r0, r3 8016ea8: f7fd fc54 bl 8014754 8016eac: 4603 mov r3, r0 8016eae: 2b00 cmp r3, #0 8016eb0: f47f af26 bne.w 8016d00 } } } } 8016eb4: bf00 nop 8016eb6: bf00 nop 8016eb8: 3730 adds r7, #48 @ 0x30 8016eba: 46bd mov sp, r7 8016ebc: bd80 pop {r7, pc} 8016ebe: bf00 nop 8016ec0: 24002b70 .word 0x24002b70 08016ec4 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 8016ec4: b580 push {r7, lr} 8016ec6: b088 sub sp, #32 8016ec8: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8016eca: e049 b.n 8016f60 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 8016ecc: 4b2e ldr r3, [pc, #184] @ (8016f88 ) 8016ece: 681b ldr r3, [r3, #0] 8016ed0: 68db ldr r3, [r3, #12] 8016ed2: 681b ldr r3, [r3, #0] 8016ed4: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016ed6: 4b2c ldr r3, [pc, #176] @ (8016f88 ) 8016ed8: 681b ldr r3, [r3, #0] 8016eda: 68db ldr r3, [r3, #12] 8016edc: 68db ldr r3, [r3, #12] 8016ede: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8016ee0: 68fb ldr r3, [r7, #12] 8016ee2: 3304 adds r3, #4 8016ee4: 4618 mov r0, r3 8016ee6: f7fd f86d bl 8013fc4 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 8016eea: 68fb ldr r3, [r7, #12] 8016eec: 6a1b ldr r3, [r3, #32] 8016eee: 68f8 ldr r0, [r7, #12] 8016ef0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8016ef2: 68fb ldr r3, [r7, #12] 8016ef4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8016ef8: f003 0304 and.w r3, r3, #4 8016efc: 2b00 cmp r3, #0 8016efe: d02f beq.n 8016f60 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 8016f00: 68fb ldr r3, [r7, #12] 8016f02: 699b ldr r3, [r3, #24] 8016f04: 693a ldr r2, [r7, #16] 8016f06: 4413 add r3, r2 8016f08: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 8016f0a: 68ba ldr r2, [r7, #8] 8016f0c: 693b ldr r3, [r7, #16] 8016f0e: 429a cmp r2, r3 8016f10: d90e bls.n 8016f30 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 8016f12: 68fb ldr r3, [r7, #12] 8016f14: 68ba ldr r2, [r7, #8] 8016f16: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8016f18: 68fb ldr r3, [r7, #12] 8016f1a: 68fa ldr r2, [r7, #12] 8016f1c: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8016f1e: 4b1a ldr r3, [pc, #104] @ (8016f88 ) 8016f20: 681a ldr r2, [r3, #0] 8016f22: 68fb ldr r3, [r7, #12] 8016f24: 3304 adds r3, #4 8016f26: 4619 mov r1, r3 8016f28: 4610 mov r0, r2 8016f2a: f7fd f812 bl 8013f52 8016f2e: e017 b.n 8016f60 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8016f30: 2300 movs r3, #0 8016f32: 9300 str r3, [sp, #0] 8016f34: 2300 movs r3, #0 8016f36: 693a ldr r2, [r7, #16] 8016f38: 2100 movs r1, #0 8016f3a: 68f8 ldr r0, [r7, #12] 8016f3c: f7ff fd58 bl 80169f0 8016f40: 6078 str r0, [r7, #4] configASSERT( xResult ); 8016f42: 687b ldr r3, [r7, #4] 8016f44: 2b00 cmp r3, #0 8016f46: d10b bne.n 8016f60 __asm volatile 8016f48: f04f 0350 mov.w r3, #80 @ 0x50 8016f4c: f383 8811 msr BASEPRI, r3 8016f50: f3bf 8f6f isb sy 8016f54: f3bf 8f4f dsb sy 8016f58: 603b str r3, [r7, #0] } 8016f5a: bf00 nop 8016f5c: bf00 nop 8016f5e: e7fd b.n 8016f5c while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8016f60: 4b09 ldr r3, [pc, #36] @ (8016f88 ) 8016f62: 681b ldr r3, [r3, #0] 8016f64: 681b ldr r3, [r3, #0] 8016f66: 2b00 cmp r3, #0 8016f68: d1b0 bne.n 8016ecc { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 8016f6a: 4b07 ldr r3, [pc, #28] @ (8016f88 ) 8016f6c: 681b ldr r3, [r3, #0] 8016f6e: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8016f70: 4b06 ldr r3, [pc, #24] @ (8016f8c ) 8016f72: 681b ldr r3, [r3, #0] 8016f74: 4a04 ldr r2, [pc, #16] @ (8016f88 ) 8016f76: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8016f78: 4a04 ldr r2, [pc, #16] @ (8016f8c ) 8016f7a: 697b ldr r3, [r7, #20] 8016f7c: 6013 str r3, [r2, #0] } 8016f7e: bf00 nop 8016f80: 3718 adds r7, #24 8016f82: 46bd mov sp, r7 8016f84: bd80 pop {r7, pc} 8016f86: bf00 nop 8016f88: 24002b68 .word 0x24002b68 8016f8c: 24002b6c .word 0x24002b6c 08016f90 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8016f90: b580 push {r7, lr} 8016f92: b082 sub sp, #8 8016f94: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 8016f96: f000 f9b7 bl 8017308 { if( xTimerQueue == NULL ) 8016f9a: 4b15 ldr r3, [pc, #84] @ (8016ff0 ) 8016f9c: 681b ldr r3, [r3, #0] 8016f9e: 2b00 cmp r3, #0 8016fa0: d120 bne.n 8016fe4 { vListInitialise( &xActiveTimerList1 ); 8016fa2: 4814 ldr r0, [pc, #80] @ (8016ff4 ) 8016fa4: f7fc ff84 bl 8013eb0 vListInitialise( &xActiveTimerList2 ); 8016fa8: 4813 ldr r0, [pc, #76] @ (8016ff8 ) 8016faa: f7fc ff81 bl 8013eb0 pxCurrentTimerList = &xActiveTimerList1; 8016fae: 4b13 ldr r3, [pc, #76] @ (8016ffc ) 8016fb0: 4a10 ldr r2, [pc, #64] @ (8016ff4 ) 8016fb2: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8016fb4: 4b12 ldr r3, [pc, #72] @ (8017000 ) 8016fb6: 4a10 ldr r2, [pc, #64] @ (8016ff8 ) 8016fb8: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 8016fba: 2300 movs r3, #0 8016fbc: 9300 str r3, [sp, #0] 8016fbe: 4b11 ldr r3, [pc, #68] @ (8017004 ) 8016fc0: 4a11 ldr r2, [pc, #68] @ (8017008 ) 8016fc2: 2110 movs r1, #16 8016fc4: 200a movs r0, #10 8016fc6: f7fd f891 bl 80140ec 8016fca: 4603 mov r3, r0 8016fcc: 4a08 ldr r2, [pc, #32] @ (8016ff0 ) 8016fce: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 8016fd0: 4b07 ldr r3, [pc, #28] @ (8016ff0 ) 8016fd2: 681b ldr r3, [r3, #0] 8016fd4: 2b00 cmp r3, #0 8016fd6: d005 beq.n 8016fe4 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 8016fd8: 4b05 ldr r3, [pc, #20] @ (8016ff0 ) 8016fda: 681b ldr r3, [r3, #0] 8016fdc: 490b ldr r1, [pc, #44] @ (801700c ) 8016fde: 4618 mov r0, r3 8016fe0: f7fd ff54 bl 8014e8c else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016fe4: f000 f9c2 bl 801736c } 8016fe8: bf00 nop 8016fea: 46bd mov sp, r7 8016fec: bd80 pop {r7, pc} 8016fee: bf00 nop 8016ff0: 24002b70 .word 0x24002b70 8016ff4: 24002b40 .word 0x24002b40 8016ff8: 24002b54 .word 0x24002b54 8016ffc: 24002b68 .word 0x24002b68 8017000: 24002b6c .word 0x24002b6c 8017004: 24002c1c .word 0x24002c1c 8017008: 24002b7c .word 0x24002b7c 801700c: 0801895c .word 0x0801895c 08017010 : /*-----------------------------------------------------------*/ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { 8017010: b580 push {r7, lr} 8017012: b086 sub sp, #24 8017014: af00 add r7, sp, #0 8017016: 6078 str r0, [r7, #4] BaseType_t xReturn; Timer_t *pxTimer = xTimer; 8017018: 687b ldr r3, [r7, #4] 801701a: 613b str r3, [r7, #16] configASSERT( xTimer ); 801701c: 687b ldr r3, [r7, #4] 801701e: 2b00 cmp r3, #0 8017020: d10b bne.n 801703a __asm volatile 8017022: f04f 0350 mov.w r3, #80 @ 0x50 8017026: f383 8811 msr BASEPRI, r3 801702a: f3bf 8f6f isb sy 801702e: f3bf 8f4f dsb sy 8017032: 60fb str r3, [r7, #12] } 8017034: bf00 nop 8017036: bf00 nop 8017038: e7fd b.n 8017036 /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 801703a: f000 f965 bl 8017308 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 801703e: 693b ldr r3, [r7, #16] 8017040: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017044: f003 0301 and.w r3, r3, #1 8017048: 2b00 cmp r3, #0 801704a: d102 bne.n 8017052 { xReturn = pdFALSE; 801704c: 2300 movs r3, #0 801704e: 617b str r3, [r7, #20] 8017050: e001 b.n 8017056 } else { xReturn = pdTRUE; 8017052: 2301 movs r3, #1 8017054: 617b str r3, [r7, #20] } } taskEXIT_CRITICAL(); 8017056: f000 f989 bl 801736c return xReturn; 801705a: 697b ldr r3, [r7, #20] } /*lint !e818 Can't be pointer to const due to the typedef. */ 801705c: 4618 mov r0, r3 801705e: 3718 adds r7, #24 8017060: 46bd mov sp, r7 8017062: bd80 pop {r7, pc} 08017064 : /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { 8017064: b580 push {r7, lr} 8017066: b086 sub sp, #24 8017068: af00 add r7, sp, #0 801706a: 6078 str r0, [r7, #4] Timer_t * const pxTimer = xTimer; 801706c: 687b ldr r3, [r7, #4] 801706e: 617b str r3, [r7, #20] void *pvReturn; configASSERT( xTimer ); 8017070: 687b ldr r3, [r7, #4] 8017072: 2b00 cmp r3, #0 8017074: d10b bne.n 801708e __asm volatile 8017076: f04f 0350 mov.w r3, #80 @ 0x50 801707a: f383 8811 msr BASEPRI, r3 801707e: f3bf 8f6f isb sy 8017082: f3bf 8f4f dsb sy 8017086: 60fb str r3, [r7, #12] } 8017088: bf00 nop 801708a: bf00 nop 801708c: e7fd b.n 801708a taskENTER_CRITICAL(); 801708e: f000 f93b bl 8017308 { pvReturn = pxTimer->pvTimerID; 8017092: 697b ldr r3, [r7, #20] 8017094: 69db ldr r3, [r3, #28] 8017096: 613b str r3, [r7, #16] } taskEXIT_CRITICAL(); 8017098: f000 f968 bl 801736c return pvReturn; 801709c: 693b ldr r3, [r7, #16] } 801709e: 4618 mov r0, r3 80170a0: 3718 adds r7, #24 80170a2: 46bd mov sp, r7 80170a4: bd80 pop {r7, pc} ... 080170a8 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 80170a8: b480 push {r7} 80170aa: b085 sub sp, #20 80170ac: af00 add r7, sp, #0 80170ae: 60f8 str r0, [r7, #12] 80170b0: 60b9 str r1, [r7, #8] 80170b2: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 80170b4: 68fb ldr r3, [r7, #12] 80170b6: 3b04 subs r3, #4 80170b8: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 80170ba: 68fb ldr r3, [r7, #12] 80170bc: f04f 7280 mov.w r2, #16777216 @ 0x1000000 80170c0: 601a str r2, [r3, #0] pxTopOfStack--; 80170c2: 68fb ldr r3, [r7, #12] 80170c4: 3b04 subs r3, #4 80170c6: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 80170c8: 68bb ldr r3, [r7, #8] 80170ca: f023 0201 bic.w r2, r3, #1 80170ce: 68fb ldr r3, [r7, #12] 80170d0: 601a str r2, [r3, #0] pxTopOfStack--; 80170d2: 68fb ldr r3, [r7, #12] 80170d4: 3b04 subs r3, #4 80170d6: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 80170d8: 4a0c ldr r2, [pc, #48] @ (801710c ) 80170da: 68fb ldr r3, [r7, #12] 80170dc: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 80170de: 68fb ldr r3, [r7, #12] 80170e0: 3b14 subs r3, #20 80170e2: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 80170e4: 687a ldr r2, [r7, #4] 80170e6: 68fb ldr r3, [r7, #12] 80170e8: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 80170ea: 68fb ldr r3, [r7, #12] 80170ec: 3b04 subs r3, #4 80170ee: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 80170f0: 68fb ldr r3, [r7, #12] 80170f2: f06f 0202 mvn.w r2, #2 80170f6: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 80170f8: 68fb ldr r3, [r7, #12] 80170fa: 3b20 subs r3, #32 80170fc: 60fb str r3, [r7, #12] return pxTopOfStack; 80170fe: 68fb ldr r3, [r7, #12] } 8017100: 4618 mov r0, r3 8017102: 3714 adds r7, #20 8017104: 46bd mov sp, r7 8017106: f85d 7b04 ldr.w r7, [sp], #4 801710a: 4770 bx lr 801710c: 08017111 .word 0x08017111 08017110 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8017110: b480 push {r7} 8017112: b085 sub sp, #20 8017114: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8017116: 2300 movs r3, #0 8017118: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 801711a: 4b13 ldr r3, [pc, #76] @ (8017168 ) 801711c: 681b ldr r3, [r3, #0] 801711e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017122: d00b beq.n 801713c __asm volatile 8017124: f04f 0350 mov.w r3, #80 @ 0x50 8017128: f383 8811 msr BASEPRI, r3 801712c: f3bf 8f6f isb sy 8017130: f3bf 8f4f dsb sy 8017134: 60fb str r3, [r7, #12] } 8017136: bf00 nop 8017138: bf00 nop 801713a: e7fd b.n 8017138 __asm volatile 801713c: f04f 0350 mov.w r3, #80 @ 0x50 8017140: f383 8811 msr BASEPRI, r3 8017144: f3bf 8f6f isb sy 8017148: f3bf 8f4f dsb sy 801714c: 60bb str r3, [r7, #8] } 801714e: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8017150: bf00 nop 8017152: 687b ldr r3, [r7, #4] 8017154: 2b00 cmp r3, #0 8017156: d0fc beq.n 8017152 about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 8017158: bf00 nop 801715a: bf00 nop 801715c: 3714 adds r7, #20 801715e: 46bd mov sp, r7 8017160: f85d 7b04 ldr.w r7, [sp], #4 8017164: 4770 bx lr 8017166: bf00 nop 8017168: 24000044 .word 0x24000044 801716c: 00000000 .word 0x00000000 08017170 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8017170: 4b07 ldr r3, [pc, #28] @ (8017190 ) 8017172: 6819 ldr r1, [r3, #0] 8017174: 6808 ldr r0, [r1, #0] 8017176: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 801717a: f380 8809 msr PSP, r0 801717e: f3bf 8f6f isb sy 8017182: f04f 0000 mov.w r0, #0 8017186: f380 8811 msr BASEPRI, r0 801718a: 4770 bx lr 801718c: f3af 8000 nop.w 08017190 : 8017190: 24002640 .word 0x24002640 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8017194: bf00 nop 8017196: bf00 nop 08017198 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 8017198: 4808 ldr r0, [pc, #32] @ (80171bc ) 801719a: 6800 ldr r0, [r0, #0] 801719c: 6800 ldr r0, [r0, #0] 801719e: f380 8808 msr MSP, r0 80171a2: f04f 0000 mov.w r0, #0 80171a6: f380 8814 msr CONTROL, r0 80171aa: b662 cpsie i 80171ac: b661 cpsie f 80171ae: f3bf 8f4f dsb sy 80171b2: f3bf 8f6f isb sy 80171b6: df00 svc 0 80171b8: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 80171ba: bf00 nop 80171bc: e000ed08 .word 0xe000ed08 080171c0 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 80171c0: b580 push {r7, lr} 80171c2: b086 sub sp, #24 80171c4: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 80171c6: 4b47 ldr r3, [pc, #284] @ (80172e4 ) 80171c8: 681b ldr r3, [r3, #0] 80171ca: 4a47 ldr r2, [pc, #284] @ (80172e8 ) 80171cc: 4293 cmp r3, r2 80171ce: d10b bne.n 80171e8 __asm volatile 80171d0: f04f 0350 mov.w r3, #80 @ 0x50 80171d4: f383 8811 msr BASEPRI, r3 80171d8: f3bf 8f6f isb sy 80171dc: f3bf 8f4f dsb sy 80171e0: 613b str r3, [r7, #16] } 80171e2: bf00 nop 80171e4: bf00 nop 80171e6: e7fd b.n 80171e4 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 80171e8: 4b3e ldr r3, [pc, #248] @ (80172e4 ) 80171ea: 681b ldr r3, [r3, #0] 80171ec: 4a3f ldr r2, [pc, #252] @ (80172ec ) 80171ee: 4293 cmp r3, r2 80171f0: d10b bne.n 801720a __asm volatile 80171f2: f04f 0350 mov.w r3, #80 @ 0x50 80171f6: f383 8811 msr BASEPRI, r3 80171fa: f3bf 8f6f isb sy 80171fe: f3bf 8f4f dsb sy 8017202: 60fb str r3, [r7, #12] } 8017204: bf00 nop 8017206: bf00 nop 8017208: e7fd b.n 8017206 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 801720a: 4b39 ldr r3, [pc, #228] @ (80172f0 ) 801720c: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 801720e: 697b ldr r3, [r7, #20] 8017210: 781b ldrb r3, [r3, #0] 8017212: b2db uxtb r3, r3 8017214: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8017216: 697b ldr r3, [r7, #20] 8017218: 22ff movs r2, #255 @ 0xff 801721a: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 801721c: 697b ldr r3, [r7, #20] 801721e: 781b ldrb r3, [r3, #0] 8017220: b2db uxtb r3, r3 8017222: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8017224: 78fb ldrb r3, [r7, #3] 8017226: b2db uxtb r3, r3 8017228: f003 0350 and.w r3, r3, #80 @ 0x50 801722c: b2da uxtb r2, r3 801722e: 4b31 ldr r3, [pc, #196] @ (80172f4 ) 8017230: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8017232: 4b31 ldr r3, [pc, #196] @ (80172f8 ) 8017234: 2207 movs r2, #7 8017236: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017238: e009 b.n 801724e { ulMaxPRIGROUPValue--; 801723a: 4b2f ldr r3, [pc, #188] @ (80172f8 ) 801723c: 681b ldr r3, [r3, #0] 801723e: 3b01 subs r3, #1 8017240: 4a2d ldr r2, [pc, #180] @ (80172f8 ) 8017242: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8017244: 78fb ldrb r3, [r7, #3] 8017246: b2db uxtb r3, r3 8017248: 005b lsls r3, r3, #1 801724a: b2db uxtb r3, r3 801724c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 801724e: 78fb ldrb r3, [r7, #3] 8017250: b2db uxtb r3, r3 8017252: f003 0380 and.w r3, r3, #128 @ 0x80 8017256: 2b80 cmp r3, #128 @ 0x80 8017258: d0ef beq.n 801723a #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 801725a: 4b27 ldr r3, [pc, #156] @ (80172f8 ) 801725c: 681b ldr r3, [r3, #0] 801725e: f1c3 0307 rsb r3, r3, #7 8017262: 2b04 cmp r3, #4 8017264: d00b beq.n 801727e __asm volatile 8017266: f04f 0350 mov.w r3, #80 @ 0x50 801726a: f383 8811 msr BASEPRI, r3 801726e: f3bf 8f6f isb sy 8017272: f3bf 8f4f dsb sy 8017276: 60bb str r3, [r7, #8] } 8017278: bf00 nop 801727a: bf00 nop 801727c: e7fd b.n 801727a } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 801727e: 4b1e ldr r3, [pc, #120] @ (80172f8 ) 8017280: 681b ldr r3, [r3, #0] 8017282: 021b lsls r3, r3, #8 8017284: 4a1c ldr r2, [pc, #112] @ (80172f8 ) 8017286: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8017288: 4b1b ldr r3, [pc, #108] @ (80172f8 ) 801728a: 681b ldr r3, [r3, #0] 801728c: f403 63e0 and.w r3, r3, #1792 @ 0x700 8017290: 4a19 ldr r2, [pc, #100] @ (80172f8 ) 8017292: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 8017294: 687b ldr r3, [r7, #4] 8017296: b2da uxtb r2, r3 8017298: 697b ldr r3, [r7, #20] 801729a: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 801729c: 4b17 ldr r3, [pc, #92] @ (80172fc ) 801729e: 681b ldr r3, [r3, #0] 80172a0: 4a16 ldr r2, [pc, #88] @ (80172fc ) 80172a2: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80172a6: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 80172a8: 4b14 ldr r3, [pc, #80] @ (80172fc ) 80172aa: 681b ldr r3, [r3, #0] 80172ac: 4a13 ldr r2, [pc, #76] @ (80172fc ) 80172ae: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 80172b2: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 80172b4: f000 f8da bl 801746c /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 80172b8: 4b11 ldr r3, [pc, #68] @ (8017300 ) 80172ba: 2200 movs r2, #0 80172bc: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 80172be: f000 f8f9 bl 80174b4 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 80172c2: 4b10 ldr r3, [pc, #64] @ (8017304 ) 80172c4: 681b ldr r3, [r3, #0] 80172c6: 4a0f ldr r2, [pc, #60] @ (8017304 ) 80172c8: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 80172cc: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 80172ce: f7ff ff63 bl 8017198 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 80172d2: f7fe fbd1 bl 8015a78 prvTaskExitError(); 80172d6: f7ff ff1b bl 8017110 /* Should not get here! */ return 0; 80172da: 2300 movs r3, #0 } 80172dc: 4618 mov r0, r3 80172de: 3718 adds r7, #24 80172e0: 46bd mov sp, r7 80172e2: bd80 pop {r7, pc} 80172e4: e000ed00 .word 0xe000ed00 80172e8: 410fc271 .word 0x410fc271 80172ec: 410fc270 .word 0x410fc270 80172f0: e000e400 .word 0xe000e400 80172f4: 24002c6c .word 0x24002c6c 80172f8: 24002c70 .word 0x24002c70 80172fc: e000ed20 .word 0xe000ed20 8017300: 24000044 .word 0x24000044 8017304: e000ef34 .word 0xe000ef34 08017308 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8017308: b480 push {r7} 801730a: b083 sub sp, #12 801730c: af00 add r7, sp, #0 __asm volatile 801730e: f04f 0350 mov.w r3, #80 @ 0x50 8017312: f383 8811 msr BASEPRI, r3 8017316: f3bf 8f6f isb sy 801731a: f3bf 8f4f dsb sy 801731e: 607b str r3, [r7, #4] } 8017320: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8017322: 4b10 ldr r3, [pc, #64] @ (8017364 ) 8017324: 681b ldr r3, [r3, #0] 8017326: 3301 adds r3, #1 8017328: 4a0e ldr r2, [pc, #56] @ (8017364 ) 801732a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 801732c: 4b0d ldr r3, [pc, #52] @ (8017364 ) 801732e: 681b ldr r3, [r3, #0] 8017330: 2b01 cmp r3, #1 8017332: d110 bne.n 8017356 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8017334: 4b0c ldr r3, [pc, #48] @ (8017368 ) 8017336: 681b ldr r3, [r3, #0] 8017338: b2db uxtb r3, r3 801733a: 2b00 cmp r3, #0 801733c: d00b beq.n 8017356 __asm volatile 801733e: f04f 0350 mov.w r3, #80 @ 0x50 8017342: f383 8811 msr BASEPRI, r3 8017346: f3bf 8f6f isb sy 801734a: f3bf 8f4f dsb sy 801734e: 603b str r3, [r7, #0] } 8017350: bf00 nop 8017352: bf00 nop 8017354: e7fd b.n 8017352 } } 8017356: bf00 nop 8017358: 370c adds r7, #12 801735a: 46bd mov sp, r7 801735c: f85d 7b04 ldr.w r7, [sp], #4 8017360: 4770 bx lr 8017362: bf00 nop 8017364: 24000044 .word 0x24000044 8017368: e000ed04 .word 0xe000ed04 0801736c : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 801736c: b480 push {r7} 801736e: b083 sub sp, #12 8017370: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8017372: 4b12 ldr r3, [pc, #72] @ (80173bc ) 8017374: 681b ldr r3, [r3, #0] 8017376: 2b00 cmp r3, #0 8017378: d10b bne.n 8017392 __asm volatile 801737a: f04f 0350 mov.w r3, #80 @ 0x50 801737e: f383 8811 msr BASEPRI, r3 8017382: f3bf 8f6f isb sy 8017386: f3bf 8f4f dsb sy 801738a: 607b str r3, [r7, #4] } 801738c: bf00 nop 801738e: bf00 nop 8017390: e7fd b.n 801738e uxCriticalNesting--; 8017392: 4b0a ldr r3, [pc, #40] @ (80173bc ) 8017394: 681b ldr r3, [r3, #0] 8017396: 3b01 subs r3, #1 8017398: 4a08 ldr r2, [pc, #32] @ (80173bc ) 801739a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 801739c: 4b07 ldr r3, [pc, #28] @ (80173bc ) 801739e: 681b ldr r3, [r3, #0] 80173a0: 2b00 cmp r3, #0 80173a2: d105 bne.n 80173b0 80173a4: 2300 movs r3, #0 80173a6: 603b str r3, [r7, #0] __asm volatile 80173a8: 683b ldr r3, [r7, #0] 80173aa: f383 8811 msr BASEPRI, r3 } 80173ae: bf00 nop { portENABLE_INTERRUPTS(); } } 80173b0: bf00 nop 80173b2: 370c adds r7, #12 80173b4: 46bd mov sp, r7 80173b6: f85d 7b04 ldr.w r7, [sp], #4 80173ba: 4770 bx lr 80173bc: 24000044 .word 0x24000044 080173c0 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 80173c0: f3ef 8009 mrs r0, PSP 80173c4: f3bf 8f6f isb sy 80173c8: 4b15 ldr r3, [pc, #84] @ (8017420 ) 80173ca: 681a ldr r2, [r3, #0] 80173cc: f01e 0f10 tst.w lr, #16 80173d0: bf08 it eq 80173d2: ed20 8a10 vstmdbeq r0!, {s16-s31} 80173d6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80173da: 6010 str r0, [r2, #0] 80173dc: e92d 0009 stmdb sp!, {r0, r3} 80173e0: f04f 0050 mov.w r0, #80 @ 0x50 80173e4: f380 8811 msr BASEPRI, r0 80173e8: f3bf 8f4f dsb sy 80173ec: f3bf 8f6f isb sy 80173f0: f7fe fb42 bl 8015a78 80173f4: f04f 0000 mov.w r0, #0 80173f8: f380 8811 msr BASEPRI, r0 80173fc: bc09 pop {r0, r3} 80173fe: 6819 ldr r1, [r3, #0] 8017400: 6808 ldr r0, [r1, #0] 8017402: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017406: f01e 0f10 tst.w lr, #16 801740a: bf08 it eq 801740c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8017410: f380 8809 msr PSP, r0 8017414: f3bf 8f6f isb sy 8017418: 4770 bx lr 801741a: bf00 nop 801741c: f3af 8000 nop.w 08017420 : 8017420: 24002640 .word 0x24002640 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8017424: bf00 nop 8017426: bf00 nop 08017428 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017428: b580 push {r7, lr} 801742a: b082 sub sp, #8 801742c: af00 add r7, sp, #0 __asm volatile 801742e: f04f 0350 mov.w r3, #80 @ 0x50 8017432: f383 8811 msr BASEPRI, r3 8017436: f3bf 8f6f isb sy 801743a: f3bf 8f4f dsb sy 801743e: 607b str r3, [r7, #4] } 8017440: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8017442: f7fe fa5f bl 8015904 8017446: 4603 mov r3, r0 8017448: 2b00 cmp r3, #0 801744a: d003 beq.n 8017454 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 801744c: 4b06 ldr r3, [pc, #24] @ (8017468 ) 801744e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8017452: 601a str r2, [r3, #0] 8017454: 2300 movs r3, #0 8017456: 603b str r3, [r7, #0] __asm volatile 8017458: 683b ldr r3, [r7, #0] 801745a: f383 8811 msr BASEPRI, r3 } 801745e: bf00 nop } } portENABLE_INTERRUPTS(); } 8017460: bf00 nop 8017462: 3708 adds r7, #8 8017464: 46bd mov sp, r7 8017466: bd80 pop {r7, pc} 8017468: e000ed04 .word 0xe000ed04 0801746c : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 801746c: b480 push {r7} 801746e: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8017470: 4b0b ldr r3, [pc, #44] @ (80174a0 ) 8017472: 2200 movs r2, #0 8017474: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8017476: 4b0b ldr r3, [pc, #44] @ (80174a4 ) 8017478: 2200 movs r2, #0 801747a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 801747c: 4b0a ldr r3, [pc, #40] @ (80174a8 ) 801747e: 681b ldr r3, [r3, #0] 8017480: 4a0a ldr r2, [pc, #40] @ (80174ac ) 8017482: fba2 2303 umull r2, r3, r2, r3 8017486: 099b lsrs r3, r3, #6 8017488: 4a09 ldr r2, [pc, #36] @ (80174b0 ) 801748a: 3b01 subs r3, #1 801748c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 801748e: 4b04 ldr r3, [pc, #16] @ (80174a0 ) 8017490: 2207 movs r2, #7 8017492: 601a str r2, [r3, #0] } 8017494: bf00 nop 8017496: 46bd mov sp, r7 8017498: f85d 7b04 ldr.w r7, [sp], #4 801749c: 4770 bx lr 801749e: bf00 nop 80174a0: e000e010 .word 0xe000e010 80174a4: e000e018 .word 0xe000e018 80174a8: 24000034 .word 0x24000034 80174ac: 10624dd3 .word 0x10624dd3 80174b0: e000e014 .word 0xe000e014 080174b4 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 80174b4: f8df 000c ldr.w r0, [pc, #12] @ 80174c4 80174b8: 6801 ldr r1, [r0, #0] 80174ba: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 80174be: 6001 str r1, [r0, #0] 80174c0: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 80174c2: bf00 nop 80174c4: e000ed88 .word 0xe000ed88 080174c8 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 80174c8: b480 push {r7} 80174ca: b085 sub sp, #20 80174cc: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 80174ce: f3ef 8305 mrs r3, IPSR 80174d2: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 80174d4: 68fb ldr r3, [r7, #12] 80174d6: 2b0f cmp r3, #15 80174d8: d915 bls.n 8017506 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 80174da: 4a18 ldr r2, [pc, #96] @ (801753c ) 80174dc: 68fb ldr r3, [r7, #12] 80174de: 4413 add r3, r2 80174e0: 781b ldrb r3, [r3, #0] 80174e2: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 80174e4: 4b16 ldr r3, [pc, #88] @ (8017540 ) 80174e6: 781b ldrb r3, [r3, #0] 80174e8: 7afa ldrb r2, [r7, #11] 80174ea: 429a cmp r2, r3 80174ec: d20b bcs.n 8017506 __asm volatile 80174ee: f04f 0350 mov.w r3, #80 @ 0x50 80174f2: f383 8811 msr BASEPRI, r3 80174f6: f3bf 8f6f isb sy 80174fa: f3bf 8f4f dsb sy 80174fe: 607b str r3, [r7, #4] } 8017500: bf00 nop 8017502: bf00 nop 8017504: e7fd b.n 8017502 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8017506: 4b0f ldr r3, [pc, #60] @ (8017544 ) 8017508: 681b ldr r3, [r3, #0] 801750a: f403 62e0 and.w r2, r3, #1792 @ 0x700 801750e: 4b0e ldr r3, [pc, #56] @ (8017548 ) 8017510: 681b ldr r3, [r3, #0] 8017512: 429a cmp r2, r3 8017514: d90b bls.n 801752e __asm volatile 8017516: f04f 0350 mov.w r3, #80 @ 0x50 801751a: f383 8811 msr BASEPRI, r3 801751e: f3bf 8f6f isb sy 8017522: f3bf 8f4f dsb sy 8017526: 603b str r3, [r7, #0] } 8017528: bf00 nop 801752a: bf00 nop 801752c: e7fd b.n 801752a } 801752e: bf00 nop 8017530: 3714 adds r7, #20 8017532: 46bd mov sp, r7 8017534: f85d 7b04 ldr.w r7, [sp], #4 8017538: 4770 bx lr 801753a: bf00 nop 801753c: e000e3f0 .word 0xe000e3f0 8017540: 24002c6c .word 0x24002c6c 8017544: e000ed0c .word 0xe000ed0c 8017548: 24002c70 .word 0x24002c70 0801754c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 801754c: b580 push {r7, lr} 801754e: b08a sub sp, #40 @ 0x28 8017550: af00 add r7, sp, #0 8017552: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 8017554: 2300 movs r3, #0 8017556: 61fb str r3, [r7, #28] vTaskSuspendAll(); 8017558: f7fe f918 bl 801578c { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 801755c: 4b5c ldr r3, [pc, #368] @ (80176d0 ) 801755e: 681b ldr r3, [r3, #0] 8017560: 2b00 cmp r3, #0 8017562: d101 bne.n 8017568 { prvHeapInit(); 8017564: f000 f924 bl 80177b0 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 8017568: 4b5a ldr r3, [pc, #360] @ (80176d4 ) 801756a: 681a ldr r2, [r3, #0] 801756c: 687b ldr r3, [r7, #4] 801756e: 4013 ands r3, r2 8017570: 2b00 cmp r3, #0 8017572: f040 8095 bne.w 80176a0 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 8017576: 687b ldr r3, [r7, #4] 8017578: 2b00 cmp r3, #0 801757a: d01e beq.n 80175ba { xWantedSize += xHeapStructSize; 801757c: 2208 movs r2, #8 801757e: 687b ldr r3, [r7, #4] 8017580: 4413 add r3, r2 8017582: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8017584: 687b ldr r3, [r7, #4] 8017586: f003 0307 and.w r3, r3, #7 801758a: 2b00 cmp r3, #0 801758c: d015 beq.n 80175ba { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 801758e: 687b ldr r3, [r7, #4] 8017590: f023 0307 bic.w r3, r3, #7 8017594: 3308 adds r3, #8 8017596: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017598: 687b ldr r3, [r7, #4] 801759a: f003 0307 and.w r3, r3, #7 801759e: 2b00 cmp r3, #0 80175a0: d00b beq.n 80175ba __asm volatile 80175a2: f04f 0350 mov.w r3, #80 @ 0x50 80175a6: f383 8811 msr BASEPRI, r3 80175aa: f3bf 8f6f isb sy 80175ae: f3bf 8f4f dsb sy 80175b2: 617b str r3, [r7, #20] } 80175b4: bf00 nop 80175b6: bf00 nop 80175b8: e7fd b.n 80175b6 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 80175ba: 687b ldr r3, [r7, #4] 80175bc: 2b00 cmp r3, #0 80175be: d06f beq.n 80176a0 80175c0: 4b45 ldr r3, [pc, #276] @ (80176d8 ) 80175c2: 681b ldr r3, [r3, #0] 80175c4: 687a ldr r2, [r7, #4] 80175c6: 429a cmp r2, r3 80175c8: d86a bhi.n 80176a0 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 80175ca: 4b44 ldr r3, [pc, #272] @ (80176dc ) 80175cc: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 80175ce: 4b43 ldr r3, [pc, #268] @ (80176dc ) 80175d0: 681b ldr r3, [r3, #0] 80175d2: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 80175d4: e004 b.n 80175e0 { pxPreviousBlock = pxBlock; 80175d6: 6a7b ldr r3, [r7, #36] @ 0x24 80175d8: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 80175da: 6a7b ldr r3, [r7, #36] @ 0x24 80175dc: 681b ldr r3, [r3, #0] 80175de: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 80175e0: 6a7b ldr r3, [r7, #36] @ 0x24 80175e2: 685b ldr r3, [r3, #4] 80175e4: 687a ldr r2, [r7, #4] 80175e6: 429a cmp r2, r3 80175e8: d903 bls.n 80175f2 80175ea: 6a7b ldr r3, [r7, #36] @ 0x24 80175ec: 681b ldr r3, [r3, #0] 80175ee: 2b00 cmp r3, #0 80175f0: d1f1 bne.n 80175d6 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 80175f2: 4b37 ldr r3, [pc, #220] @ (80176d0 ) 80175f4: 681b ldr r3, [r3, #0] 80175f6: 6a7a ldr r2, [r7, #36] @ 0x24 80175f8: 429a cmp r2, r3 80175fa: d051 beq.n 80176a0 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 80175fc: 6a3b ldr r3, [r7, #32] 80175fe: 681b ldr r3, [r3, #0] 8017600: 2208 movs r2, #8 8017602: 4413 add r3, r2 8017604: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8017606: 6a7b ldr r3, [r7, #36] @ 0x24 8017608: 681a ldr r2, [r3, #0] 801760a: 6a3b ldr r3, [r7, #32] 801760c: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 801760e: 6a7b ldr r3, [r7, #36] @ 0x24 8017610: 685a ldr r2, [r3, #4] 8017612: 687b ldr r3, [r7, #4] 8017614: 1ad2 subs r2, r2, r3 8017616: 2308 movs r3, #8 8017618: 005b lsls r3, r3, #1 801761a: 429a cmp r2, r3 801761c: d920 bls.n 8017660 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 801761e: 6a7a ldr r2, [r7, #36] @ 0x24 8017620: 687b ldr r3, [r7, #4] 8017622: 4413 add r3, r2 8017624: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017626: 69bb ldr r3, [r7, #24] 8017628: f003 0307 and.w r3, r3, #7 801762c: 2b00 cmp r3, #0 801762e: d00b beq.n 8017648 __asm volatile 8017630: f04f 0350 mov.w r3, #80 @ 0x50 8017634: f383 8811 msr BASEPRI, r3 8017638: f3bf 8f6f isb sy 801763c: f3bf 8f4f dsb sy 8017640: 613b str r3, [r7, #16] } 8017642: bf00 nop 8017644: bf00 nop 8017646: e7fd b.n 8017644 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8017648: 6a7b ldr r3, [r7, #36] @ 0x24 801764a: 685a ldr r2, [r3, #4] 801764c: 687b ldr r3, [r7, #4] 801764e: 1ad2 subs r2, r2, r3 8017650: 69bb ldr r3, [r7, #24] 8017652: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 8017654: 6a7b ldr r3, [r7, #36] @ 0x24 8017656: 687a ldr r2, [r7, #4] 8017658: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 801765a: 69b8 ldr r0, [r7, #24] 801765c: f000 f90a bl 8017874 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 8017660: 4b1d ldr r3, [pc, #116] @ (80176d8 ) 8017662: 681a ldr r2, [r3, #0] 8017664: 6a7b ldr r3, [r7, #36] @ 0x24 8017666: 685b ldr r3, [r3, #4] 8017668: 1ad3 subs r3, r2, r3 801766a: 4a1b ldr r2, [pc, #108] @ (80176d8 ) 801766c: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 801766e: 4b1a ldr r3, [pc, #104] @ (80176d8 ) 8017670: 681a ldr r2, [r3, #0] 8017672: 4b1b ldr r3, [pc, #108] @ (80176e0 ) 8017674: 681b ldr r3, [r3, #0] 8017676: 429a cmp r2, r3 8017678: d203 bcs.n 8017682 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 801767a: 4b17 ldr r3, [pc, #92] @ (80176d8 ) 801767c: 681b ldr r3, [r3, #0] 801767e: 4a18 ldr r2, [pc, #96] @ (80176e0 ) 8017680: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 8017682: 6a7b ldr r3, [r7, #36] @ 0x24 8017684: 685a ldr r2, [r3, #4] 8017686: 4b13 ldr r3, [pc, #76] @ (80176d4 ) 8017688: 681b ldr r3, [r3, #0] 801768a: 431a orrs r2, r3 801768c: 6a7b ldr r3, [r7, #36] @ 0x24 801768e: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 8017690: 6a7b ldr r3, [r7, #36] @ 0x24 8017692: 2200 movs r2, #0 8017694: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 8017696: 4b13 ldr r3, [pc, #76] @ (80176e4 ) 8017698: 681b ldr r3, [r3, #0] 801769a: 3301 adds r3, #1 801769c: 4a11 ldr r2, [pc, #68] @ (80176e4 ) 801769e: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 80176a0: f7fe f882 bl 80157a8 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 80176a4: 69fb ldr r3, [r7, #28] 80176a6: f003 0307 and.w r3, r3, #7 80176aa: 2b00 cmp r3, #0 80176ac: d00b beq.n 80176c6 __asm volatile 80176ae: f04f 0350 mov.w r3, #80 @ 0x50 80176b2: f383 8811 msr BASEPRI, r3 80176b6: f3bf 8f6f isb sy 80176ba: f3bf 8f4f dsb sy 80176be: 60fb str r3, [r7, #12] } 80176c0: bf00 nop 80176c2: bf00 nop 80176c4: e7fd b.n 80176c2 return pvReturn; 80176c6: 69fb ldr r3, [r7, #28] } 80176c8: 4618 mov r0, r3 80176ca: 3728 adds r7, #40 @ 0x28 80176cc: 46bd mov sp, r7 80176ce: bd80 pop {r7, pc} 80176d0: 24012c7c .word 0x24012c7c 80176d4: 24012c90 .word 0x24012c90 80176d8: 24012c80 .word 0x24012c80 80176dc: 24012c74 .word 0x24012c74 80176e0: 24012c84 .word 0x24012c84 80176e4: 24012c88 .word 0x24012c88 080176e8 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 80176e8: b580 push {r7, lr} 80176ea: b086 sub sp, #24 80176ec: af00 add r7, sp, #0 80176ee: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 80176f0: 687b ldr r3, [r7, #4] 80176f2: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 80176f4: 687b ldr r3, [r7, #4] 80176f6: 2b00 cmp r3, #0 80176f8: d04f beq.n 801779a { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 80176fa: 2308 movs r3, #8 80176fc: 425b negs r3, r3 80176fe: 697a ldr r2, [r7, #20] 8017700: 4413 add r3, r2 8017702: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 8017704: 697b ldr r3, [r7, #20] 8017706: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 8017708: 693b ldr r3, [r7, #16] 801770a: 685a ldr r2, [r3, #4] 801770c: 4b25 ldr r3, [pc, #148] @ (80177a4 ) 801770e: 681b ldr r3, [r3, #0] 8017710: 4013 ands r3, r2 8017712: 2b00 cmp r3, #0 8017714: d10b bne.n 801772e __asm volatile 8017716: f04f 0350 mov.w r3, #80 @ 0x50 801771a: f383 8811 msr BASEPRI, r3 801771e: f3bf 8f6f isb sy 8017722: f3bf 8f4f dsb sy 8017726: 60fb str r3, [r7, #12] } 8017728: bf00 nop 801772a: bf00 nop 801772c: e7fd b.n 801772a configASSERT( pxLink->pxNextFreeBlock == NULL ); 801772e: 693b ldr r3, [r7, #16] 8017730: 681b ldr r3, [r3, #0] 8017732: 2b00 cmp r3, #0 8017734: d00b beq.n 801774e __asm volatile 8017736: f04f 0350 mov.w r3, #80 @ 0x50 801773a: f383 8811 msr BASEPRI, r3 801773e: f3bf 8f6f isb sy 8017742: f3bf 8f4f dsb sy 8017746: 60bb str r3, [r7, #8] } 8017748: bf00 nop 801774a: bf00 nop 801774c: e7fd b.n 801774a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 801774e: 693b ldr r3, [r7, #16] 8017750: 685a ldr r2, [r3, #4] 8017752: 4b14 ldr r3, [pc, #80] @ (80177a4 ) 8017754: 681b ldr r3, [r3, #0] 8017756: 4013 ands r3, r2 8017758: 2b00 cmp r3, #0 801775a: d01e beq.n 801779a { if( pxLink->pxNextFreeBlock == NULL ) 801775c: 693b ldr r3, [r7, #16] 801775e: 681b ldr r3, [r3, #0] 8017760: 2b00 cmp r3, #0 8017762: d11a bne.n 801779a { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 8017764: 693b ldr r3, [r7, #16] 8017766: 685a ldr r2, [r3, #4] 8017768: 4b0e ldr r3, [pc, #56] @ (80177a4 ) 801776a: 681b ldr r3, [r3, #0] 801776c: 43db mvns r3, r3 801776e: 401a ands r2, r3 8017770: 693b ldr r3, [r7, #16] 8017772: 605a str r2, [r3, #4] vTaskSuspendAll(); 8017774: f7fe f80a bl 801578c { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 8017778: 693b ldr r3, [r7, #16] 801777a: 685a ldr r2, [r3, #4] 801777c: 4b0a ldr r3, [pc, #40] @ (80177a8 ) 801777e: 681b ldr r3, [r3, #0] 8017780: 4413 add r3, r2 8017782: 4a09 ldr r2, [pc, #36] @ (80177a8 ) 8017784: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 8017786: 6938 ldr r0, [r7, #16] 8017788: f000 f874 bl 8017874 xNumberOfSuccessfulFrees++; 801778c: 4b07 ldr r3, [pc, #28] @ (80177ac ) 801778e: 681b ldr r3, [r3, #0] 8017790: 3301 adds r3, #1 8017792: 4a06 ldr r2, [pc, #24] @ (80177ac ) 8017794: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8017796: f7fe f807 bl 80157a8 else { mtCOVERAGE_TEST_MARKER(); } } } 801779a: bf00 nop 801779c: 3718 adds r7, #24 801779e: 46bd mov sp, r7 80177a0: bd80 pop {r7, pc} 80177a2: bf00 nop 80177a4: 24012c90 .word 0x24012c90 80177a8: 24012c80 .word 0x24012c80 80177ac: 24012c8c .word 0x24012c8c 080177b0 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 80177b0: b480 push {r7} 80177b2: b085 sub sp, #20 80177b4: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 80177b6: f44f 3380 mov.w r3, #65536 @ 0x10000 80177ba: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 80177bc: 4b27 ldr r3, [pc, #156] @ (801785c ) 80177be: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 80177c0: 68fb ldr r3, [r7, #12] 80177c2: f003 0307 and.w r3, r3, #7 80177c6: 2b00 cmp r3, #0 80177c8: d00c beq.n 80177e4 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 80177ca: 68fb ldr r3, [r7, #12] 80177cc: 3307 adds r3, #7 80177ce: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80177d0: 68fb ldr r3, [r7, #12] 80177d2: f023 0307 bic.w r3, r3, #7 80177d6: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 80177d8: 68ba ldr r2, [r7, #8] 80177da: 68fb ldr r3, [r7, #12] 80177dc: 1ad3 subs r3, r2, r3 80177de: 4a1f ldr r2, [pc, #124] @ (801785c ) 80177e0: 4413 add r3, r2 80177e2: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 80177e4: 68fb ldr r3, [r7, #12] 80177e6: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 80177e8: 4a1d ldr r2, [pc, #116] @ (8017860 ) 80177ea: 687b ldr r3, [r7, #4] 80177ec: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 80177ee: 4b1c ldr r3, [pc, #112] @ (8017860 ) 80177f0: 2200 movs r2, #0 80177f2: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 80177f4: 687b ldr r3, [r7, #4] 80177f6: 68ba ldr r2, [r7, #8] 80177f8: 4413 add r3, r2 80177fa: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 80177fc: 2208 movs r2, #8 80177fe: 68fb ldr r3, [r7, #12] 8017800: 1a9b subs r3, r3, r2 8017802: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 8017804: 68fb ldr r3, [r7, #12] 8017806: f023 0307 bic.w r3, r3, #7 801780a: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 801780c: 68fb ldr r3, [r7, #12] 801780e: 4a15 ldr r2, [pc, #84] @ (8017864 ) 8017810: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 8017812: 4b14 ldr r3, [pc, #80] @ (8017864 ) 8017814: 681b ldr r3, [r3, #0] 8017816: 2200 movs r2, #0 8017818: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 801781a: 4b12 ldr r3, [pc, #72] @ (8017864 ) 801781c: 681b ldr r3, [r3, #0] 801781e: 2200 movs r2, #0 8017820: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8017822: 687b ldr r3, [r7, #4] 8017824: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 8017826: 683b ldr r3, [r7, #0] 8017828: 68fa ldr r2, [r7, #12] 801782a: 1ad2 subs r2, r2, r3 801782c: 683b ldr r3, [r7, #0] 801782e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 8017830: 4b0c ldr r3, [pc, #48] @ (8017864 ) 8017832: 681a ldr r2, [r3, #0] 8017834: 683b ldr r3, [r7, #0] 8017836: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8017838: 683b ldr r3, [r7, #0] 801783a: 685b ldr r3, [r3, #4] 801783c: 4a0a ldr r2, [pc, #40] @ (8017868 ) 801783e: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8017840: 683b ldr r3, [r7, #0] 8017842: 685b ldr r3, [r3, #4] 8017844: 4a09 ldr r2, [pc, #36] @ (801786c ) 8017846: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 8017848: 4b09 ldr r3, [pc, #36] @ (8017870 ) 801784a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 801784e: 601a str r2, [r3, #0] } 8017850: bf00 nop 8017852: 3714 adds r7, #20 8017854: 46bd mov sp, r7 8017856: f85d 7b04 ldr.w r7, [sp], #4 801785a: 4770 bx lr 801785c: 24002c74 .word 0x24002c74 8017860: 24012c74 .word 0x24012c74 8017864: 24012c7c .word 0x24012c7c 8017868: 24012c84 .word 0x24012c84 801786c: 24012c80 .word 0x24012c80 8017870: 24012c90 .word 0x24012c90 08017874 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 8017874: b480 push {r7} 8017876: b085 sub sp, #20 8017878: af00 add r7, sp, #0 801787a: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 801787c: 4b28 ldr r3, [pc, #160] @ (8017920 ) 801787e: 60fb str r3, [r7, #12] 8017880: e002 b.n 8017888 8017882: 68fb ldr r3, [r7, #12] 8017884: 681b ldr r3, [r3, #0] 8017886: 60fb str r3, [r7, #12] 8017888: 68fb ldr r3, [r7, #12] 801788a: 681b ldr r3, [r3, #0] 801788c: 687a ldr r2, [r7, #4] 801788e: 429a cmp r2, r3 8017890: d8f7 bhi.n 8017882 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8017892: 68fb ldr r3, [r7, #12] 8017894: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8017896: 68fb ldr r3, [r7, #12] 8017898: 685b ldr r3, [r3, #4] 801789a: 68ba ldr r2, [r7, #8] 801789c: 4413 add r3, r2 801789e: 687a ldr r2, [r7, #4] 80178a0: 429a cmp r2, r3 80178a2: d108 bne.n 80178b6 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 80178a4: 68fb ldr r3, [r7, #12] 80178a6: 685a ldr r2, [r3, #4] 80178a8: 687b ldr r3, [r7, #4] 80178aa: 685b ldr r3, [r3, #4] 80178ac: 441a add r2, r3 80178ae: 68fb ldr r3, [r7, #12] 80178b0: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 80178b2: 68fb ldr r3, [r7, #12] 80178b4: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 80178b6: 687b ldr r3, [r7, #4] 80178b8: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 80178ba: 687b ldr r3, [r7, #4] 80178bc: 685b ldr r3, [r3, #4] 80178be: 68ba ldr r2, [r7, #8] 80178c0: 441a add r2, r3 80178c2: 68fb ldr r3, [r7, #12] 80178c4: 681b ldr r3, [r3, #0] 80178c6: 429a cmp r2, r3 80178c8: d118 bne.n 80178fc { if( pxIterator->pxNextFreeBlock != pxEnd ) 80178ca: 68fb ldr r3, [r7, #12] 80178cc: 681a ldr r2, [r3, #0] 80178ce: 4b15 ldr r3, [pc, #84] @ (8017924 ) 80178d0: 681b ldr r3, [r3, #0] 80178d2: 429a cmp r2, r3 80178d4: d00d beq.n 80178f2 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 80178d6: 687b ldr r3, [r7, #4] 80178d8: 685a ldr r2, [r3, #4] 80178da: 68fb ldr r3, [r7, #12] 80178dc: 681b ldr r3, [r3, #0] 80178de: 685b ldr r3, [r3, #4] 80178e0: 441a add r2, r3 80178e2: 687b ldr r3, [r7, #4] 80178e4: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 80178e6: 68fb ldr r3, [r7, #12] 80178e8: 681b ldr r3, [r3, #0] 80178ea: 681a ldr r2, [r3, #0] 80178ec: 687b ldr r3, [r7, #4] 80178ee: 601a str r2, [r3, #0] 80178f0: e008 b.n 8017904 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 80178f2: 4b0c ldr r3, [pc, #48] @ (8017924 ) 80178f4: 681a ldr r2, [r3, #0] 80178f6: 687b ldr r3, [r7, #4] 80178f8: 601a str r2, [r3, #0] 80178fa: e003 b.n 8017904 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 80178fc: 68fb ldr r3, [r7, #12] 80178fe: 681a ldr r2, [r3, #0] 8017900: 687b ldr r3, [r7, #4] 8017902: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 8017904: 68fa ldr r2, [r7, #12] 8017906: 687b ldr r3, [r7, #4] 8017908: 429a cmp r2, r3 801790a: d002 beq.n 8017912 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 801790c: 68fb ldr r3, [r7, #12] 801790e: 687a ldr r2, [r7, #4] 8017910: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8017912: bf00 nop 8017914: 3714 adds r7, #20 8017916: 46bd mov sp, r7 8017918: f85d 7b04 ldr.w r7, [sp], #4 801791c: 4770 bx lr 801791e: bf00 nop 8017920: 24012c74 .word 0x24012c74 8017924: 24012c7c .word 0x24012c7c 08017928 : 8017928: 2300 movs r3, #0 801792a: b510 push {r4, lr} 801792c: 4604 mov r4, r0 801792e: e9c0 3300 strd r3, r3, [r0] 8017932: e9c0 3304 strd r3, r3, [r0, #16] 8017936: 6083 str r3, [r0, #8] 8017938: 8181 strh r1, [r0, #12] 801793a: 6643 str r3, [r0, #100] @ 0x64 801793c: 81c2 strh r2, [r0, #14] 801793e: 6183 str r3, [r0, #24] 8017940: 4619 mov r1, r3 8017942: 2208 movs r2, #8 8017944: 305c adds r0, #92 @ 0x5c 8017946: f000 f906 bl 8017b56 801794a: 4b0d ldr r3, [pc, #52] @ (8017980 ) 801794c: 6263 str r3, [r4, #36] @ 0x24 801794e: 4b0d ldr r3, [pc, #52] @ (8017984 ) 8017950: 62a3 str r3, [r4, #40] @ 0x28 8017952: 4b0d ldr r3, [pc, #52] @ (8017988 ) 8017954: 62e3 str r3, [r4, #44] @ 0x2c 8017956: 4b0d ldr r3, [pc, #52] @ (801798c ) 8017958: 6323 str r3, [r4, #48] @ 0x30 801795a: 4b0d ldr r3, [pc, #52] @ (8017990 ) 801795c: 6224 str r4, [r4, #32] 801795e: 429c cmp r4, r3 8017960: d006 beq.n 8017970 8017962: f103 0268 add.w r2, r3, #104 @ 0x68 8017966: 4294 cmp r4, r2 8017968: d002 beq.n 8017970 801796a: 33d0 adds r3, #208 @ 0xd0 801796c: 429c cmp r4, r3 801796e: d105 bne.n 801797c 8017970: f104 0058 add.w r0, r4, #88 @ 0x58 8017974: e8bd 4010 ldmia.w sp!, {r4, lr} 8017978: f000 b9bc b.w 8017cf4 <__retarget_lock_init_recursive> 801797c: bd10 pop {r4, pc} 801797e: bf00 nop 8017980: 08017ad1 .word 0x08017ad1 8017984: 08017af3 .word 0x08017af3 8017988: 08017b2b .word 0x08017b2b 801798c: 08017b4f .word 0x08017b4f 8017990: 24012c94 .word 0x24012c94 08017994 : 8017994: 4a02 ldr r2, [pc, #8] @ (80179a0 ) 8017996: 4903 ldr r1, [pc, #12] @ (80179a4 ) 8017998: 4803 ldr r0, [pc, #12] @ (80179a8 ) 801799a: f000 b869 b.w 8017a70 <_fwalk_sglue> 801799e: bf00 nop 80179a0: 24000048 .word 0x24000048 80179a4: 080185b1 .word 0x080185b1 80179a8: 24000058 .word 0x24000058 080179ac : 80179ac: 6841 ldr r1, [r0, #4] 80179ae: 4b0c ldr r3, [pc, #48] @ (80179e0 ) 80179b0: 4299 cmp r1, r3 80179b2: b510 push {r4, lr} 80179b4: 4604 mov r4, r0 80179b6: d001 beq.n 80179bc 80179b8: f000 fdfa bl 80185b0 <_fflush_r> 80179bc: 68a1 ldr r1, [r4, #8] 80179be: 4b09 ldr r3, [pc, #36] @ (80179e4 ) 80179c0: 4299 cmp r1, r3 80179c2: d002 beq.n 80179ca 80179c4: 4620 mov r0, r4 80179c6: f000 fdf3 bl 80185b0 <_fflush_r> 80179ca: 68e1 ldr r1, [r4, #12] 80179cc: 4b06 ldr r3, [pc, #24] @ (80179e8 ) 80179ce: 4299 cmp r1, r3 80179d0: d004 beq.n 80179dc 80179d2: 4620 mov r0, r4 80179d4: e8bd 4010 ldmia.w sp!, {r4, lr} 80179d8: f000 bdea b.w 80185b0 <_fflush_r> 80179dc: bd10 pop {r4, pc} 80179de: bf00 nop 80179e0: 24012c94 .word 0x24012c94 80179e4: 24012cfc .word 0x24012cfc 80179e8: 24012d64 .word 0x24012d64 080179ec : 80179ec: b510 push {r4, lr} 80179ee: 4b0b ldr r3, [pc, #44] @ (8017a1c ) 80179f0: 4c0b ldr r4, [pc, #44] @ (8017a20 ) 80179f2: 4a0c ldr r2, [pc, #48] @ (8017a24 ) 80179f4: 601a str r2, [r3, #0] 80179f6: 4620 mov r0, r4 80179f8: 2200 movs r2, #0 80179fa: 2104 movs r1, #4 80179fc: f7ff ff94 bl 8017928 8017a00: f104 0068 add.w r0, r4, #104 @ 0x68 8017a04: 2201 movs r2, #1 8017a06: 2109 movs r1, #9 8017a08: f7ff ff8e bl 8017928 8017a0c: f104 00d0 add.w r0, r4, #208 @ 0xd0 8017a10: 2202 movs r2, #2 8017a12: e8bd 4010 ldmia.w sp!, {r4, lr} 8017a16: 2112 movs r1, #18 8017a18: f7ff bf86 b.w 8017928 8017a1c: 24012dcc .word 0x24012dcc 8017a20: 24012c94 .word 0x24012c94 8017a24: 08017995 .word 0x08017995 08017a28 <__sfp_lock_acquire>: 8017a28: 4801 ldr r0, [pc, #4] @ (8017a30 <__sfp_lock_acquire+0x8>) 8017a2a: f000 b964 b.w 8017cf6 <__retarget_lock_acquire_recursive> 8017a2e: bf00 nop 8017a30: 24012dd5 .word 0x24012dd5 08017a34 <__sfp_lock_release>: 8017a34: 4801 ldr r0, [pc, #4] @ (8017a3c <__sfp_lock_release+0x8>) 8017a36: f000 b95f b.w 8017cf8 <__retarget_lock_release_recursive> 8017a3a: bf00 nop 8017a3c: 24012dd5 .word 0x24012dd5 08017a40 <__sinit>: 8017a40: b510 push {r4, lr} 8017a42: 4604 mov r4, r0 8017a44: f7ff fff0 bl 8017a28 <__sfp_lock_acquire> 8017a48: 6a23 ldr r3, [r4, #32] 8017a4a: b11b cbz r3, 8017a54 <__sinit+0x14> 8017a4c: e8bd 4010 ldmia.w sp!, {r4, lr} 8017a50: f7ff bff0 b.w 8017a34 <__sfp_lock_release> 8017a54: 4b04 ldr r3, [pc, #16] @ (8017a68 <__sinit+0x28>) 8017a56: 6223 str r3, [r4, #32] 8017a58: 4b04 ldr r3, [pc, #16] @ (8017a6c <__sinit+0x2c>) 8017a5a: 681b ldr r3, [r3, #0] 8017a5c: 2b00 cmp r3, #0 8017a5e: d1f5 bne.n 8017a4c <__sinit+0xc> 8017a60: f7ff ffc4 bl 80179ec 8017a64: e7f2 b.n 8017a4c <__sinit+0xc> 8017a66: bf00 nop 8017a68: 080179ad .word 0x080179ad 8017a6c: 24012dcc .word 0x24012dcc 08017a70 <_fwalk_sglue>: 8017a70: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8017a74: 4607 mov r7, r0 8017a76: 4688 mov r8, r1 8017a78: 4614 mov r4, r2 8017a7a: 2600 movs r6, #0 8017a7c: e9d4 9501 ldrd r9, r5, [r4, #4] 8017a80: f1b9 0901 subs.w r9, r9, #1 8017a84: d505 bpl.n 8017a92 <_fwalk_sglue+0x22> 8017a86: 6824 ldr r4, [r4, #0] 8017a88: 2c00 cmp r4, #0 8017a8a: d1f7 bne.n 8017a7c <_fwalk_sglue+0xc> 8017a8c: 4630 mov r0, r6 8017a8e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8017a92: 89ab ldrh r3, [r5, #12] 8017a94: 2b01 cmp r3, #1 8017a96: d907 bls.n 8017aa8 <_fwalk_sglue+0x38> 8017a98: f9b5 300e ldrsh.w r3, [r5, #14] 8017a9c: 3301 adds r3, #1 8017a9e: d003 beq.n 8017aa8 <_fwalk_sglue+0x38> 8017aa0: 4629 mov r1, r5 8017aa2: 4638 mov r0, r7 8017aa4: 47c0 blx r8 8017aa6: 4306 orrs r6, r0 8017aa8: 3568 adds r5, #104 @ 0x68 8017aaa: e7e9 b.n 8017a80 <_fwalk_sglue+0x10> 08017aac : 8017aac: b40f push {r0, r1, r2, r3} 8017aae: b507 push {r0, r1, r2, lr} 8017ab0: 4906 ldr r1, [pc, #24] @ (8017acc ) 8017ab2: ab04 add r3, sp, #16 8017ab4: 6808 ldr r0, [r1, #0] 8017ab6: f853 2b04 ldr.w r2, [r3], #4 8017aba: 6881 ldr r1, [r0, #8] 8017abc: 9301 str r3, [sp, #4] 8017abe: f000 fa4d bl 8017f5c <_vfiprintf_r> 8017ac2: b003 add sp, #12 8017ac4: f85d eb04 ldr.w lr, [sp], #4 8017ac8: b004 add sp, #16 8017aca: 4770 bx lr 8017acc: 24000054 .word 0x24000054 08017ad0 <__sread>: 8017ad0: b510 push {r4, lr} 8017ad2: 460c mov r4, r1 8017ad4: f9b1 100e ldrsh.w r1, [r1, #14] 8017ad8: f000 f8be bl 8017c58 <_read_r> 8017adc: 2800 cmp r0, #0 8017ade: bfab itete ge 8017ae0: 6d63 ldrge r3, [r4, #84] @ 0x54 8017ae2: 89a3 ldrhlt r3, [r4, #12] 8017ae4: 181b addge r3, r3, r0 8017ae6: f423 5380 biclt.w r3, r3, #4096 @ 0x1000 8017aea: bfac ite ge 8017aec: 6563 strge r3, [r4, #84] @ 0x54 8017aee: 81a3 strhlt r3, [r4, #12] 8017af0: bd10 pop {r4, pc} 08017af2 <__swrite>: 8017af2: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 8017af6: 461f mov r7, r3 8017af8: 898b ldrh r3, [r1, #12] 8017afa: 05db lsls r3, r3, #23 8017afc: 4605 mov r5, r0 8017afe: 460c mov r4, r1 8017b00: 4616 mov r6, r2 8017b02: d505 bpl.n 8017b10 <__swrite+0x1e> 8017b04: f9b1 100e ldrsh.w r1, [r1, #14] 8017b08: 2302 movs r3, #2 8017b0a: 2200 movs r2, #0 8017b0c: f000 f892 bl 8017c34 <_lseek_r> 8017b10: 89a3 ldrh r3, [r4, #12] 8017b12: f9b4 100e ldrsh.w r1, [r4, #14] 8017b16: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8017b1a: 81a3 strh r3, [r4, #12] 8017b1c: 4632 mov r2, r6 8017b1e: 463b mov r3, r7 8017b20: 4628 mov r0, r5 8017b22: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} 8017b26: f000 b8a9 b.w 8017c7c <_write_r> 08017b2a <__sseek>: 8017b2a: b510 push {r4, lr} 8017b2c: 460c mov r4, r1 8017b2e: f9b1 100e ldrsh.w r1, [r1, #14] 8017b32: f000 f87f bl 8017c34 <_lseek_r> 8017b36: 1c43 adds r3, r0, #1 8017b38: 89a3 ldrh r3, [r4, #12] 8017b3a: bf15 itete ne 8017b3c: 6560 strne r0, [r4, #84] @ 0x54 8017b3e: f423 5380 biceq.w r3, r3, #4096 @ 0x1000 8017b42: f443 5380 orrne.w r3, r3, #4096 @ 0x1000 8017b46: 81a3 strheq r3, [r4, #12] 8017b48: bf18 it ne 8017b4a: 81a3 strhne r3, [r4, #12] 8017b4c: bd10 pop {r4, pc} 08017b4e <__sclose>: 8017b4e: f9b1 100e ldrsh.w r1, [r1, #14] 8017b52: f000 b809 b.w 8017b68 <_close_r> 08017b56 : 8017b56: 4402 add r2, r0 8017b58: 4603 mov r3, r0 8017b5a: 4293 cmp r3, r2 8017b5c: d100 bne.n 8017b60 8017b5e: 4770 bx lr 8017b60: f803 1b01 strb.w r1, [r3], #1 8017b64: e7f9 b.n 8017b5a ... 08017b68 <_close_r>: 8017b68: b538 push {r3, r4, r5, lr} 8017b6a: 4d06 ldr r5, [pc, #24] @ (8017b84 <_close_r+0x1c>) 8017b6c: 2300 movs r3, #0 8017b6e: 4604 mov r4, r0 8017b70: 4608 mov r0, r1 8017b72: 602b str r3, [r5, #0] 8017b74: f7ec fa4b bl 800400e <_close> 8017b78: 1c43 adds r3, r0, #1 8017b7a: d102 bne.n 8017b82 <_close_r+0x1a> 8017b7c: 682b ldr r3, [r5, #0] 8017b7e: b103 cbz r3, 8017b82 <_close_r+0x1a> 8017b80: 6023 str r3, [r4, #0] 8017b82: bd38 pop {r3, r4, r5, pc} 8017b84: 24012dd0 .word 0x24012dd0 08017b88 <_reclaim_reent>: 8017b88: 4b29 ldr r3, [pc, #164] @ (8017c30 <_reclaim_reent+0xa8>) 8017b8a: 681b ldr r3, [r3, #0] 8017b8c: 4283 cmp r3, r0 8017b8e: b570 push {r4, r5, r6, lr} 8017b90: 4604 mov r4, r0 8017b92: d04b beq.n 8017c2c <_reclaim_reent+0xa4> 8017b94: 69c3 ldr r3, [r0, #28] 8017b96: b1ab cbz r3, 8017bc4 <_reclaim_reent+0x3c> 8017b98: 68db ldr r3, [r3, #12] 8017b9a: b16b cbz r3, 8017bb8 <_reclaim_reent+0x30> 8017b9c: 2500 movs r5, #0 8017b9e: 69e3 ldr r3, [r4, #28] 8017ba0: 68db ldr r3, [r3, #12] 8017ba2: 5959 ldr r1, [r3, r5] 8017ba4: 2900 cmp r1, #0 8017ba6: d13b bne.n 8017c20 <_reclaim_reent+0x98> 8017ba8: 3504 adds r5, #4 8017baa: 2d80 cmp r5, #128 @ 0x80 8017bac: d1f7 bne.n 8017b9e <_reclaim_reent+0x16> 8017bae: 69e3 ldr r3, [r4, #28] 8017bb0: 4620 mov r0, r4 8017bb2: 68d9 ldr r1, [r3, #12] 8017bb4: f000 f8b0 bl 8017d18 <_free_r> 8017bb8: 69e3 ldr r3, [r4, #28] 8017bba: 6819 ldr r1, [r3, #0] 8017bbc: b111 cbz r1, 8017bc4 <_reclaim_reent+0x3c> 8017bbe: 4620 mov r0, r4 8017bc0: f000 f8aa bl 8017d18 <_free_r> 8017bc4: 6961 ldr r1, [r4, #20] 8017bc6: b111 cbz r1, 8017bce <_reclaim_reent+0x46> 8017bc8: 4620 mov r0, r4 8017bca: f000 f8a5 bl 8017d18 <_free_r> 8017bce: 69e1 ldr r1, [r4, #28] 8017bd0: b111 cbz r1, 8017bd8 <_reclaim_reent+0x50> 8017bd2: 4620 mov r0, r4 8017bd4: f000 f8a0 bl 8017d18 <_free_r> 8017bd8: 6b21 ldr r1, [r4, #48] @ 0x30 8017bda: b111 cbz r1, 8017be2 <_reclaim_reent+0x5a> 8017bdc: 4620 mov r0, r4 8017bde: f000 f89b bl 8017d18 <_free_r> 8017be2: 6b61 ldr r1, [r4, #52] @ 0x34 8017be4: b111 cbz r1, 8017bec <_reclaim_reent+0x64> 8017be6: 4620 mov r0, r4 8017be8: f000 f896 bl 8017d18 <_free_r> 8017bec: 6ba1 ldr r1, [r4, #56] @ 0x38 8017bee: b111 cbz r1, 8017bf6 <_reclaim_reent+0x6e> 8017bf0: 4620 mov r0, r4 8017bf2: f000 f891 bl 8017d18 <_free_r> 8017bf6: 6ca1 ldr r1, [r4, #72] @ 0x48 8017bf8: b111 cbz r1, 8017c00 <_reclaim_reent+0x78> 8017bfa: 4620 mov r0, r4 8017bfc: f000 f88c bl 8017d18 <_free_r> 8017c00: 6c61 ldr r1, [r4, #68] @ 0x44 8017c02: b111 cbz r1, 8017c0a <_reclaim_reent+0x82> 8017c04: 4620 mov r0, r4 8017c06: f000 f887 bl 8017d18 <_free_r> 8017c0a: 6ae1 ldr r1, [r4, #44] @ 0x2c 8017c0c: b111 cbz r1, 8017c14 <_reclaim_reent+0x8c> 8017c0e: 4620 mov r0, r4 8017c10: f000 f882 bl 8017d18 <_free_r> 8017c14: 6a23 ldr r3, [r4, #32] 8017c16: b14b cbz r3, 8017c2c <_reclaim_reent+0xa4> 8017c18: 4620 mov r0, r4 8017c1a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 8017c1e: 4718 bx r3 8017c20: 680e ldr r6, [r1, #0] 8017c22: 4620 mov r0, r4 8017c24: f000 f878 bl 8017d18 <_free_r> 8017c28: 4631 mov r1, r6 8017c2a: e7bb b.n 8017ba4 <_reclaim_reent+0x1c> 8017c2c: bd70 pop {r4, r5, r6, pc} 8017c2e: bf00 nop 8017c30: 24000054 .word 0x24000054 08017c34 <_lseek_r>: 8017c34: b538 push {r3, r4, r5, lr} 8017c36: 4d07 ldr r5, [pc, #28] @ (8017c54 <_lseek_r+0x20>) 8017c38: 4604 mov r4, r0 8017c3a: 4608 mov r0, r1 8017c3c: 4611 mov r1, r2 8017c3e: 2200 movs r2, #0 8017c40: 602a str r2, [r5, #0] 8017c42: 461a mov r2, r3 8017c44: f7ec fa0a bl 800405c <_lseek> 8017c48: 1c43 adds r3, r0, #1 8017c4a: d102 bne.n 8017c52 <_lseek_r+0x1e> 8017c4c: 682b ldr r3, [r5, #0] 8017c4e: b103 cbz r3, 8017c52 <_lseek_r+0x1e> 8017c50: 6023 str r3, [r4, #0] 8017c52: bd38 pop {r3, r4, r5, pc} 8017c54: 24012dd0 .word 0x24012dd0 08017c58 <_read_r>: 8017c58: b538 push {r3, r4, r5, lr} 8017c5a: 4d07 ldr r5, [pc, #28] @ (8017c78 <_read_r+0x20>) 8017c5c: 4604 mov r4, r0 8017c5e: 4608 mov r0, r1 8017c60: 4611 mov r1, r2 8017c62: 2200 movs r2, #0 8017c64: 602a str r2, [r5, #0] 8017c66: 461a mov r2, r3 8017c68: f7ec f998 bl 8003f9c <_read> 8017c6c: 1c43 adds r3, r0, #1 8017c6e: d102 bne.n 8017c76 <_read_r+0x1e> 8017c70: 682b ldr r3, [r5, #0] 8017c72: b103 cbz r3, 8017c76 <_read_r+0x1e> 8017c74: 6023 str r3, [r4, #0] 8017c76: bd38 pop {r3, r4, r5, pc} 8017c78: 24012dd0 .word 0x24012dd0 08017c7c <_write_r>: 8017c7c: b538 push {r3, r4, r5, lr} 8017c7e: 4d07 ldr r5, [pc, #28] @ (8017c9c <_write_r+0x20>) 8017c80: 4604 mov r4, r0 8017c82: 4608 mov r0, r1 8017c84: 4611 mov r1, r2 8017c86: 2200 movs r2, #0 8017c88: 602a str r2, [r5, #0] 8017c8a: 461a mov r2, r3 8017c8c: f7ec f9a3 bl 8003fd6 <_write> 8017c90: 1c43 adds r3, r0, #1 8017c92: d102 bne.n 8017c9a <_write_r+0x1e> 8017c94: 682b ldr r3, [r5, #0] 8017c96: b103 cbz r3, 8017c9a <_write_r+0x1e> 8017c98: 6023 str r3, [r4, #0] 8017c9a: bd38 pop {r3, r4, r5, pc} 8017c9c: 24012dd0 .word 0x24012dd0 08017ca0 <__errno>: 8017ca0: 4b01 ldr r3, [pc, #4] @ (8017ca8 <__errno+0x8>) 8017ca2: 6818 ldr r0, [r3, #0] 8017ca4: 4770 bx lr 8017ca6: bf00 nop 8017ca8: 24000054 .word 0x24000054 08017cac <__libc_init_array>: 8017cac: b570 push {r4, r5, r6, lr} 8017cae: 4d0d ldr r5, [pc, #52] @ (8017ce4 <__libc_init_array+0x38>) 8017cb0: 4c0d ldr r4, [pc, #52] @ (8017ce8 <__libc_init_array+0x3c>) 8017cb2: 1b64 subs r4, r4, r5 8017cb4: 10a4 asrs r4, r4, #2 8017cb6: 2600 movs r6, #0 8017cb8: 42a6 cmp r6, r4 8017cba: d109 bne.n 8017cd0 <__libc_init_array+0x24> 8017cbc: 4d0b ldr r5, [pc, #44] @ (8017cec <__libc_init_array+0x40>) 8017cbe: 4c0c ldr r4, [pc, #48] @ (8017cf0 <__libc_init_array+0x44>) 8017cc0: f000 fdc6 bl 8018850 <_init> 8017cc4: 1b64 subs r4, r4, r5 8017cc6: 10a4 asrs r4, r4, #2 8017cc8: 2600 movs r6, #0 8017cca: 42a6 cmp r6, r4 8017ccc: d105 bne.n 8017cda <__libc_init_array+0x2e> 8017cce: bd70 pop {r4, r5, r6, pc} 8017cd0: f855 3b04 ldr.w r3, [r5], #4 8017cd4: 4798 blx r3 8017cd6: 3601 adds r6, #1 8017cd8: e7ee b.n 8017cb8 <__libc_init_array+0xc> 8017cda: f855 3b04 ldr.w r3, [r5], #4 8017cde: 4798 blx r3 8017ce0: 3601 adds r6, #1 8017ce2: e7f2 b.n 8017cca <__libc_init_array+0x1e> 8017ce4: 08018a44 .word 0x08018a44 8017ce8: 08018a44 .word 0x08018a44 8017cec: 08018a44 .word 0x08018a44 8017cf0: 08018a48 .word 0x08018a48 08017cf4 <__retarget_lock_init_recursive>: 8017cf4: 4770 bx lr 08017cf6 <__retarget_lock_acquire_recursive>: 8017cf6: 4770 bx lr 08017cf8 <__retarget_lock_release_recursive>: 8017cf8: 4770 bx lr 08017cfa : 8017cfa: 440a add r2, r1 8017cfc: 4291 cmp r1, r2 8017cfe: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8017d02: d100 bne.n 8017d06 8017d04: 4770 bx lr 8017d06: b510 push {r4, lr} 8017d08: f811 4b01 ldrb.w r4, [r1], #1 8017d0c: f803 4f01 strb.w r4, [r3, #1]! 8017d10: 4291 cmp r1, r2 8017d12: d1f9 bne.n 8017d08 8017d14: bd10 pop {r4, pc} ... 08017d18 <_free_r>: 8017d18: b538 push {r3, r4, r5, lr} 8017d1a: 4605 mov r5, r0 8017d1c: 2900 cmp r1, #0 8017d1e: d041 beq.n 8017da4 <_free_r+0x8c> 8017d20: f851 3c04 ldr.w r3, [r1, #-4] 8017d24: 1f0c subs r4, r1, #4 8017d26: 2b00 cmp r3, #0 8017d28: bfb8 it lt 8017d2a: 18e4 addlt r4, r4, r3 8017d2c: f000 f8e0 bl 8017ef0 <__malloc_lock> 8017d30: 4a1d ldr r2, [pc, #116] @ (8017da8 <_free_r+0x90>) 8017d32: 6813 ldr r3, [r2, #0] 8017d34: b933 cbnz r3, 8017d44 <_free_r+0x2c> 8017d36: 6063 str r3, [r4, #4] 8017d38: 6014 str r4, [r2, #0] 8017d3a: 4628 mov r0, r5 8017d3c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8017d40: f000 b8dc b.w 8017efc <__malloc_unlock> 8017d44: 42a3 cmp r3, r4 8017d46: d908 bls.n 8017d5a <_free_r+0x42> 8017d48: 6820 ldr r0, [r4, #0] 8017d4a: 1821 adds r1, r4, r0 8017d4c: 428b cmp r3, r1 8017d4e: bf01 itttt eq 8017d50: 6819 ldreq r1, [r3, #0] 8017d52: 685b ldreq r3, [r3, #4] 8017d54: 1809 addeq r1, r1, r0 8017d56: 6021 streq r1, [r4, #0] 8017d58: e7ed b.n 8017d36 <_free_r+0x1e> 8017d5a: 461a mov r2, r3 8017d5c: 685b ldr r3, [r3, #4] 8017d5e: b10b cbz r3, 8017d64 <_free_r+0x4c> 8017d60: 42a3 cmp r3, r4 8017d62: d9fa bls.n 8017d5a <_free_r+0x42> 8017d64: 6811 ldr r1, [r2, #0] 8017d66: 1850 adds r0, r2, r1 8017d68: 42a0 cmp r0, r4 8017d6a: d10b bne.n 8017d84 <_free_r+0x6c> 8017d6c: 6820 ldr r0, [r4, #0] 8017d6e: 4401 add r1, r0 8017d70: 1850 adds r0, r2, r1 8017d72: 4283 cmp r3, r0 8017d74: 6011 str r1, [r2, #0] 8017d76: d1e0 bne.n 8017d3a <_free_r+0x22> 8017d78: 6818 ldr r0, [r3, #0] 8017d7a: 685b ldr r3, [r3, #4] 8017d7c: 6053 str r3, [r2, #4] 8017d7e: 4408 add r0, r1 8017d80: 6010 str r0, [r2, #0] 8017d82: e7da b.n 8017d3a <_free_r+0x22> 8017d84: d902 bls.n 8017d8c <_free_r+0x74> 8017d86: 230c movs r3, #12 8017d88: 602b str r3, [r5, #0] 8017d8a: e7d6 b.n 8017d3a <_free_r+0x22> 8017d8c: 6820 ldr r0, [r4, #0] 8017d8e: 1821 adds r1, r4, r0 8017d90: 428b cmp r3, r1 8017d92: bf04 itt eq 8017d94: 6819 ldreq r1, [r3, #0] 8017d96: 685b ldreq r3, [r3, #4] 8017d98: 6063 str r3, [r4, #4] 8017d9a: bf04 itt eq 8017d9c: 1809 addeq r1, r1, r0 8017d9e: 6021 streq r1, [r4, #0] 8017da0: 6054 str r4, [r2, #4] 8017da2: e7ca b.n 8017d3a <_free_r+0x22> 8017da4: bd38 pop {r3, r4, r5, pc} 8017da6: bf00 nop 8017da8: 24012ddc .word 0x24012ddc 08017dac : 8017dac: b570 push {r4, r5, r6, lr} 8017dae: 4e0f ldr r6, [pc, #60] @ (8017dec ) 8017db0: 460c mov r4, r1 8017db2: 6831 ldr r1, [r6, #0] 8017db4: 4605 mov r5, r0 8017db6: b911 cbnz r1, 8017dbe 8017db8: f000 fcb6 bl 8018728 <_sbrk_r> 8017dbc: 6030 str r0, [r6, #0] 8017dbe: 4621 mov r1, r4 8017dc0: 4628 mov r0, r5 8017dc2: f000 fcb1 bl 8018728 <_sbrk_r> 8017dc6: 1c43 adds r3, r0, #1 8017dc8: d103 bne.n 8017dd2 8017dca: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff 8017dce: 4620 mov r0, r4 8017dd0: bd70 pop {r4, r5, r6, pc} 8017dd2: 1cc4 adds r4, r0, #3 8017dd4: f024 0403 bic.w r4, r4, #3 8017dd8: 42a0 cmp r0, r4 8017dda: d0f8 beq.n 8017dce 8017ddc: 1a21 subs r1, r4, r0 8017dde: 4628 mov r0, r5 8017de0: f000 fca2 bl 8018728 <_sbrk_r> 8017de4: 3001 adds r0, #1 8017de6: d1f2 bne.n 8017dce 8017de8: e7ef b.n 8017dca 8017dea: bf00 nop 8017dec: 24012dd8 .word 0x24012dd8 08017df0 <_malloc_r>: 8017df0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} 8017df4: 1ccd adds r5, r1, #3 8017df6: f025 0503 bic.w r5, r5, #3 8017dfa: 3508 adds r5, #8 8017dfc: 2d0c cmp r5, #12 8017dfe: bf38 it cc 8017e00: 250c movcc r5, #12 8017e02: 2d00 cmp r5, #0 8017e04: 4606 mov r6, r0 8017e06: db01 blt.n 8017e0c <_malloc_r+0x1c> 8017e08: 42a9 cmp r1, r5 8017e0a: d904 bls.n 8017e16 <_malloc_r+0x26> 8017e0c: 230c movs r3, #12 8017e0e: 6033 str r3, [r6, #0] 8017e10: 2000 movs r0, #0 8017e12: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} 8017e16: f8df 80d4 ldr.w r8, [pc, #212] @ 8017eec <_malloc_r+0xfc> 8017e1a: f000 f869 bl 8017ef0 <__malloc_lock> 8017e1e: f8d8 3000 ldr.w r3, [r8] 8017e22: 461c mov r4, r3 8017e24: bb44 cbnz r4, 8017e78 <_malloc_r+0x88> 8017e26: 4629 mov r1, r5 8017e28: 4630 mov r0, r6 8017e2a: f7ff ffbf bl 8017dac 8017e2e: 1c43 adds r3, r0, #1 8017e30: 4604 mov r4, r0 8017e32: d158 bne.n 8017ee6 <_malloc_r+0xf6> 8017e34: f8d8 4000 ldr.w r4, [r8] 8017e38: 4627 mov r7, r4 8017e3a: 2f00 cmp r7, #0 8017e3c: d143 bne.n 8017ec6 <_malloc_r+0xd6> 8017e3e: 2c00 cmp r4, #0 8017e40: d04b beq.n 8017eda <_malloc_r+0xea> 8017e42: 6823 ldr r3, [r4, #0] 8017e44: 4639 mov r1, r7 8017e46: 4630 mov r0, r6 8017e48: eb04 0903 add.w r9, r4, r3 8017e4c: f000 fc6c bl 8018728 <_sbrk_r> 8017e50: 4581 cmp r9, r0 8017e52: d142 bne.n 8017eda <_malloc_r+0xea> 8017e54: 6821 ldr r1, [r4, #0] 8017e56: 1a6d subs r5, r5, r1 8017e58: 4629 mov r1, r5 8017e5a: 4630 mov r0, r6 8017e5c: f7ff ffa6 bl 8017dac 8017e60: 3001 adds r0, #1 8017e62: d03a beq.n 8017eda <_malloc_r+0xea> 8017e64: 6823 ldr r3, [r4, #0] 8017e66: 442b add r3, r5 8017e68: 6023 str r3, [r4, #0] 8017e6a: f8d8 3000 ldr.w r3, [r8] 8017e6e: 685a ldr r2, [r3, #4] 8017e70: bb62 cbnz r2, 8017ecc <_malloc_r+0xdc> 8017e72: f8c8 7000 str.w r7, [r8] 8017e76: e00f b.n 8017e98 <_malloc_r+0xa8> 8017e78: 6822 ldr r2, [r4, #0] 8017e7a: 1b52 subs r2, r2, r5 8017e7c: d420 bmi.n 8017ec0 <_malloc_r+0xd0> 8017e7e: 2a0b cmp r2, #11 8017e80: d917 bls.n 8017eb2 <_malloc_r+0xc2> 8017e82: 1961 adds r1, r4, r5 8017e84: 42a3 cmp r3, r4 8017e86: 6025 str r5, [r4, #0] 8017e88: bf18 it ne 8017e8a: 6059 strne r1, [r3, #4] 8017e8c: 6863 ldr r3, [r4, #4] 8017e8e: bf08 it eq 8017e90: f8c8 1000 streq.w r1, [r8] 8017e94: 5162 str r2, [r4, r5] 8017e96: 604b str r3, [r1, #4] 8017e98: 4630 mov r0, r6 8017e9a: f000 f82f bl 8017efc <__malloc_unlock> 8017e9e: f104 000b add.w r0, r4, #11 8017ea2: 1d23 adds r3, r4, #4 8017ea4: f020 0007 bic.w r0, r0, #7 8017ea8: 1ac2 subs r2, r0, r3 8017eaa: bf1c itt ne 8017eac: 1a1b subne r3, r3, r0 8017eae: 50a3 strne r3, [r4, r2] 8017eb0: e7af b.n 8017e12 <_malloc_r+0x22> 8017eb2: 6862 ldr r2, [r4, #4] 8017eb4: 42a3 cmp r3, r4 8017eb6: bf0c ite eq 8017eb8: f8c8 2000 streq.w r2, [r8] 8017ebc: 605a strne r2, [r3, #4] 8017ebe: e7eb b.n 8017e98 <_malloc_r+0xa8> 8017ec0: 4623 mov r3, r4 8017ec2: 6864 ldr r4, [r4, #4] 8017ec4: e7ae b.n 8017e24 <_malloc_r+0x34> 8017ec6: 463c mov r4, r7 8017ec8: 687f ldr r7, [r7, #4] 8017eca: e7b6 b.n 8017e3a <_malloc_r+0x4a> 8017ecc: 461a mov r2, r3 8017ece: 685b ldr r3, [r3, #4] 8017ed0: 42a3 cmp r3, r4 8017ed2: d1fb bne.n 8017ecc <_malloc_r+0xdc> 8017ed4: 2300 movs r3, #0 8017ed6: 6053 str r3, [r2, #4] 8017ed8: e7de b.n 8017e98 <_malloc_r+0xa8> 8017eda: 230c movs r3, #12 8017edc: 6033 str r3, [r6, #0] 8017ede: 4630 mov r0, r6 8017ee0: f000 f80c bl 8017efc <__malloc_unlock> 8017ee4: e794 b.n 8017e10 <_malloc_r+0x20> 8017ee6: 6005 str r5, [r0, #0] 8017ee8: e7d6 b.n 8017e98 <_malloc_r+0xa8> 8017eea: bf00 nop 8017eec: 24012ddc .word 0x24012ddc 08017ef0 <__malloc_lock>: 8017ef0: 4801 ldr r0, [pc, #4] @ (8017ef8 <__malloc_lock+0x8>) 8017ef2: f7ff bf00 b.w 8017cf6 <__retarget_lock_acquire_recursive> 8017ef6: bf00 nop 8017ef8: 24012dd4 .word 0x24012dd4 08017efc <__malloc_unlock>: 8017efc: 4801 ldr r0, [pc, #4] @ (8017f04 <__malloc_unlock+0x8>) 8017efe: f7ff befb b.w 8017cf8 <__retarget_lock_release_recursive> 8017f02: bf00 nop 8017f04: 24012dd4 .word 0x24012dd4 08017f08 <__sfputc_r>: 8017f08: 6893 ldr r3, [r2, #8] 8017f0a: 3b01 subs r3, #1 8017f0c: 2b00 cmp r3, #0 8017f0e: b410 push {r4} 8017f10: 6093 str r3, [r2, #8] 8017f12: da08 bge.n 8017f26 <__sfputc_r+0x1e> 8017f14: 6994 ldr r4, [r2, #24] 8017f16: 42a3 cmp r3, r4 8017f18: db01 blt.n 8017f1e <__sfputc_r+0x16> 8017f1a: 290a cmp r1, #10 8017f1c: d103 bne.n 8017f26 <__sfputc_r+0x1e> 8017f1e: f85d 4b04 ldr.w r4, [sp], #4 8017f22: f000 bb6d b.w 8018600 <__swbuf_r> 8017f26: 6813 ldr r3, [r2, #0] 8017f28: 1c58 adds r0, r3, #1 8017f2a: 6010 str r0, [r2, #0] 8017f2c: 7019 strb r1, [r3, #0] 8017f2e: 4608 mov r0, r1 8017f30: f85d 4b04 ldr.w r4, [sp], #4 8017f34: 4770 bx lr 08017f36 <__sfputs_r>: 8017f36: b5f8 push {r3, r4, r5, r6, r7, lr} 8017f38: 4606 mov r6, r0 8017f3a: 460f mov r7, r1 8017f3c: 4614 mov r4, r2 8017f3e: 18d5 adds r5, r2, r3 8017f40: 42ac cmp r4, r5 8017f42: d101 bne.n 8017f48 <__sfputs_r+0x12> 8017f44: 2000 movs r0, #0 8017f46: e007 b.n 8017f58 <__sfputs_r+0x22> 8017f48: f814 1b01 ldrb.w r1, [r4], #1 8017f4c: 463a mov r2, r7 8017f4e: 4630 mov r0, r6 8017f50: f7ff ffda bl 8017f08 <__sfputc_r> 8017f54: 1c43 adds r3, r0, #1 8017f56: d1f3 bne.n 8017f40 <__sfputs_r+0xa> 8017f58: bdf8 pop {r3, r4, r5, r6, r7, pc} ... 08017f5c <_vfiprintf_r>: 8017f5c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017f60: 460d mov r5, r1 8017f62: b09d sub sp, #116 @ 0x74 8017f64: 4614 mov r4, r2 8017f66: 4698 mov r8, r3 8017f68: 4606 mov r6, r0 8017f6a: b118 cbz r0, 8017f74 <_vfiprintf_r+0x18> 8017f6c: 6a03 ldr r3, [r0, #32] 8017f6e: b90b cbnz r3, 8017f74 <_vfiprintf_r+0x18> 8017f70: f7ff fd66 bl 8017a40 <__sinit> 8017f74: 6e6b ldr r3, [r5, #100] @ 0x64 8017f76: 07d9 lsls r1, r3, #31 8017f78: d405 bmi.n 8017f86 <_vfiprintf_r+0x2a> 8017f7a: 89ab ldrh r3, [r5, #12] 8017f7c: 059a lsls r2, r3, #22 8017f7e: d402 bmi.n 8017f86 <_vfiprintf_r+0x2a> 8017f80: 6da8 ldr r0, [r5, #88] @ 0x58 8017f82: f7ff feb8 bl 8017cf6 <__retarget_lock_acquire_recursive> 8017f86: 89ab ldrh r3, [r5, #12] 8017f88: 071b lsls r3, r3, #28 8017f8a: d501 bpl.n 8017f90 <_vfiprintf_r+0x34> 8017f8c: 692b ldr r3, [r5, #16] 8017f8e: b99b cbnz r3, 8017fb8 <_vfiprintf_r+0x5c> 8017f90: 4629 mov r1, r5 8017f92: 4630 mov r0, r6 8017f94: f000 fb72 bl 801867c <__swsetup_r> 8017f98: b170 cbz r0, 8017fb8 <_vfiprintf_r+0x5c> 8017f9a: 6e6b ldr r3, [r5, #100] @ 0x64 8017f9c: 07dc lsls r4, r3, #31 8017f9e: d504 bpl.n 8017faa <_vfiprintf_r+0x4e> 8017fa0: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8017fa4: b01d add sp, #116 @ 0x74 8017fa6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8017faa: 89ab ldrh r3, [r5, #12] 8017fac: 0598 lsls r0, r3, #22 8017fae: d4f7 bmi.n 8017fa0 <_vfiprintf_r+0x44> 8017fb0: 6da8 ldr r0, [r5, #88] @ 0x58 8017fb2: f7ff fea1 bl 8017cf8 <__retarget_lock_release_recursive> 8017fb6: e7f3 b.n 8017fa0 <_vfiprintf_r+0x44> 8017fb8: 2300 movs r3, #0 8017fba: 9309 str r3, [sp, #36] @ 0x24 8017fbc: 2320 movs r3, #32 8017fbe: f88d 3029 strb.w r3, [sp, #41] @ 0x29 8017fc2: f8cd 800c str.w r8, [sp, #12] 8017fc6: 2330 movs r3, #48 @ 0x30 8017fc8: f8df 81ac ldr.w r8, [pc, #428] @ 8018178 <_vfiprintf_r+0x21c> 8017fcc: f88d 302a strb.w r3, [sp, #42] @ 0x2a 8017fd0: f04f 0901 mov.w r9, #1 8017fd4: 4623 mov r3, r4 8017fd6: 469a mov sl, r3 8017fd8: f813 2b01 ldrb.w r2, [r3], #1 8017fdc: b10a cbz r2, 8017fe2 <_vfiprintf_r+0x86> 8017fde: 2a25 cmp r2, #37 @ 0x25 8017fe0: d1f9 bne.n 8017fd6 <_vfiprintf_r+0x7a> 8017fe2: ebba 0b04 subs.w fp, sl, r4 8017fe6: d00b beq.n 8018000 <_vfiprintf_r+0xa4> 8017fe8: 465b mov r3, fp 8017fea: 4622 mov r2, r4 8017fec: 4629 mov r1, r5 8017fee: 4630 mov r0, r6 8017ff0: f7ff ffa1 bl 8017f36 <__sfputs_r> 8017ff4: 3001 adds r0, #1 8017ff6: f000 80a7 beq.w 8018148 <_vfiprintf_r+0x1ec> 8017ffa: 9a09 ldr r2, [sp, #36] @ 0x24 8017ffc: 445a add r2, fp 8017ffe: 9209 str r2, [sp, #36] @ 0x24 8018000: f89a 3000 ldrb.w r3, [sl] 8018004: 2b00 cmp r3, #0 8018006: f000 809f beq.w 8018148 <_vfiprintf_r+0x1ec> 801800a: 2300 movs r3, #0 801800c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8018010: e9cd 2305 strd r2, r3, [sp, #20] 8018014: f10a 0a01 add.w sl, sl, #1 8018018: 9304 str r3, [sp, #16] 801801a: 9307 str r3, [sp, #28] 801801c: f88d 3053 strb.w r3, [sp, #83] @ 0x53 8018020: 931a str r3, [sp, #104] @ 0x68 8018022: 4654 mov r4, sl 8018024: 2205 movs r2, #5 8018026: f814 1b01 ldrb.w r1, [r4], #1 801802a: 4853 ldr r0, [pc, #332] @ (8018178 <_vfiprintf_r+0x21c>) 801802c: f7e8 f958 bl 80002e0 8018030: 9a04 ldr r2, [sp, #16] 8018032: b9d8 cbnz r0, 801806c <_vfiprintf_r+0x110> 8018034: 06d1 lsls r1, r2, #27 8018036: bf44 itt mi 8018038: 2320 movmi r3, #32 801803a: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 801803e: 0713 lsls r3, r2, #28 8018040: bf44 itt mi 8018042: 232b movmi r3, #43 @ 0x2b 8018044: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53 8018048: f89a 3000 ldrb.w r3, [sl] 801804c: 2b2a cmp r3, #42 @ 0x2a 801804e: d015 beq.n 801807c <_vfiprintf_r+0x120> 8018050: 9a07 ldr r2, [sp, #28] 8018052: 4654 mov r4, sl 8018054: 2000 movs r0, #0 8018056: f04f 0c0a mov.w ip, #10 801805a: 4621 mov r1, r4 801805c: f811 3b01 ldrb.w r3, [r1], #1 8018060: 3b30 subs r3, #48 @ 0x30 8018062: 2b09 cmp r3, #9 8018064: d94b bls.n 80180fe <_vfiprintf_r+0x1a2> 8018066: b1b0 cbz r0, 8018096 <_vfiprintf_r+0x13a> 8018068: 9207 str r2, [sp, #28] 801806a: e014 b.n 8018096 <_vfiprintf_r+0x13a> 801806c: eba0 0308 sub.w r3, r0, r8 8018070: fa09 f303 lsl.w r3, r9, r3 8018074: 4313 orrs r3, r2 8018076: 9304 str r3, [sp, #16] 8018078: 46a2 mov sl, r4 801807a: e7d2 b.n 8018022 <_vfiprintf_r+0xc6> 801807c: 9b03 ldr r3, [sp, #12] 801807e: 1d19 adds r1, r3, #4 8018080: 681b ldr r3, [r3, #0] 8018082: 9103 str r1, [sp, #12] 8018084: 2b00 cmp r3, #0 8018086: bfbb ittet lt 8018088: 425b neglt r3, r3 801808a: f042 0202 orrlt.w r2, r2, #2 801808e: 9307 strge r3, [sp, #28] 8018090: 9307 strlt r3, [sp, #28] 8018092: bfb8 it lt 8018094: 9204 strlt r2, [sp, #16] 8018096: 7823 ldrb r3, [r4, #0] 8018098: 2b2e cmp r3, #46 @ 0x2e 801809a: d10a bne.n 80180b2 <_vfiprintf_r+0x156> 801809c: 7863 ldrb r3, [r4, #1] 801809e: 2b2a cmp r3, #42 @ 0x2a 80180a0: d132 bne.n 8018108 <_vfiprintf_r+0x1ac> 80180a2: 9b03 ldr r3, [sp, #12] 80180a4: 1d1a adds r2, r3, #4 80180a6: 681b ldr r3, [r3, #0] 80180a8: 9203 str r2, [sp, #12] 80180aa: ea43 73e3 orr.w r3, r3, r3, asr #31 80180ae: 3402 adds r4, #2 80180b0: 9305 str r3, [sp, #20] 80180b2: f8df a0d4 ldr.w sl, [pc, #212] @ 8018188 <_vfiprintf_r+0x22c> 80180b6: 7821 ldrb r1, [r4, #0] 80180b8: 2203 movs r2, #3 80180ba: 4650 mov r0, sl 80180bc: f7e8 f910 bl 80002e0 80180c0: b138 cbz r0, 80180d2 <_vfiprintf_r+0x176> 80180c2: 9b04 ldr r3, [sp, #16] 80180c4: eba0 000a sub.w r0, r0, sl 80180c8: 2240 movs r2, #64 @ 0x40 80180ca: 4082 lsls r2, r0 80180cc: 4313 orrs r3, r2 80180ce: 3401 adds r4, #1 80180d0: 9304 str r3, [sp, #16] 80180d2: f814 1b01 ldrb.w r1, [r4], #1 80180d6: 4829 ldr r0, [pc, #164] @ (801817c <_vfiprintf_r+0x220>) 80180d8: f88d 1028 strb.w r1, [sp, #40] @ 0x28 80180dc: 2206 movs r2, #6 80180de: f7e8 f8ff bl 80002e0 80180e2: 2800 cmp r0, #0 80180e4: d03f beq.n 8018166 <_vfiprintf_r+0x20a> 80180e6: 4b26 ldr r3, [pc, #152] @ (8018180 <_vfiprintf_r+0x224>) 80180e8: bb1b cbnz r3, 8018132 <_vfiprintf_r+0x1d6> 80180ea: 9b03 ldr r3, [sp, #12] 80180ec: 3307 adds r3, #7 80180ee: f023 0307 bic.w r3, r3, #7 80180f2: 3308 adds r3, #8 80180f4: 9303 str r3, [sp, #12] 80180f6: 9b09 ldr r3, [sp, #36] @ 0x24 80180f8: 443b add r3, r7 80180fa: 9309 str r3, [sp, #36] @ 0x24 80180fc: e76a b.n 8017fd4 <_vfiprintf_r+0x78> 80180fe: fb0c 3202 mla r2, ip, r2, r3 8018102: 460c mov r4, r1 8018104: 2001 movs r0, #1 8018106: e7a8 b.n 801805a <_vfiprintf_r+0xfe> 8018108: 2300 movs r3, #0 801810a: 3401 adds r4, #1 801810c: 9305 str r3, [sp, #20] 801810e: 4619 mov r1, r3 8018110: f04f 0c0a mov.w ip, #10 8018114: 4620 mov r0, r4 8018116: f810 2b01 ldrb.w r2, [r0], #1 801811a: 3a30 subs r2, #48 @ 0x30 801811c: 2a09 cmp r2, #9 801811e: d903 bls.n 8018128 <_vfiprintf_r+0x1cc> 8018120: 2b00 cmp r3, #0 8018122: d0c6 beq.n 80180b2 <_vfiprintf_r+0x156> 8018124: 9105 str r1, [sp, #20] 8018126: e7c4 b.n 80180b2 <_vfiprintf_r+0x156> 8018128: fb0c 2101 mla r1, ip, r1, r2 801812c: 4604 mov r4, r0 801812e: 2301 movs r3, #1 8018130: e7f0 b.n 8018114 <_vfiprintf_r+0x1b8> 8018132: ab03 add r3, sp, #12 8018134: 9300 str r3, [sp, #0] 8018136: 462a mov r2, r5 8018138: 4b12 ldr r3, [pc, #72] @ (8018184 <_vfiprintf_r+0x228>) 801813a: a904 add r1, sp, #16 801813c: 4630 mov r0, r6 801813e: f3af 8000 nop.w 8018142: 4607 mov r7, r0 8018144: 1c78 adds r0, r7, #1 8018146: d1d6 bne.n 80180f6 <_vfiprintf_r+0x19a> 8018148: 6e6b ldr r3, [r5, #100] @ 0x64 801814a: 07d9 lsls r1, r3, #31 801814c: d405 bmi.n 801815a <_vfiprintf_r+0x1fe> 801814e: 89ab ldrh r3, [r5, #12] 8018150: 059a lsls r2, r3, #22 8018152: d402 bmi.n 801815a <_vfiprintf_r+0x1fe> 8018154: 6da8 ldr r0, [r5, #88] @ 0x58 8018156: f7ff fdcf bl 8017cf8 <__retarget_lock_release_recursive> 801815a: 89ab ldrh r3, [r5, #12] 801815c: 065b lsls r3, r3, #25 801815e: f53f af1f bmi.w 8017fa0 <_vfiprintf_r+0x44> 8018162: 9809 ldr r0, [sp, #36] @ 0x24 8018164: e71e b.n 8017fa4 <_vfiprintf_r+0x48> 8018166: ab03 add r3, sp, #12 8018168: 9300 str r3, [sp, #0] 801816a: 462a mov r2, r5 801816c: 4b05 ldr r3, [pc, #20] @ (8018184 <_vfiprintf_r+0x228>) 801816e: a904 add r1, sp, #16 8018170: 4630 mov r0, r6 8018172: f000 f879 bl 8018268 <_printf_i> 8018176: e7e4 b.n 8018142 <_vfiprintf_r+0x1e6> 8018178: 08018a08 .word 0x08018a08 801817c: 08018a12 .word 0x08018a12 8018180: 00000000 .word 0x00000000 8018184: 08017f37 .word 0x08017f37 8018188: 08018a0e .word 0x08018a0e 0801818c <_printf_common>: 801818c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8018190: 4616 mov r6, r2 8018192: 4698 mov r8, r3 8018194: 688a ldr r2, [r1, #8] 8018196: 690b ldr r3, [r1, #16] 8018198: f8dd 9020 ldr.w r9, [sp, #32] 801819c: 4293 cmp r3, r2 801819e: bfb8 it lt 80181a0: 4613 movlt r3, r2 80181a2: 6033 str r3, [r6, #0] 80181a4: f891 2043 ldrb.w r2, [r1, #67] @ 0x43 80181a8: 4607 mov r7, r0 80181aa: 460c mov r4, r1 80181ac: b10a cbz r2, 80181b2 <_printf_common+0x26> 80181ae: 3301 adds r3, #1 80181b0: 6033 str r3, [r6, #0] 80181b2: 6823 ldr r3, [r4, #0] 80181b4: 0699 lsls r1, r3, #26 80181b6: bf42 ittt mi 80181b8: 6833 ldrmi r3, [r6, #0] 80181ba: 3302 addmi r3, #2 80181bc: 6033 strmi r3, [r6, #0] 80181be: 6825 ldr r5, [r4, #0] 80181c0: f015 0506 ands.w r5, r5, #6 80181c4: d106 bne.n 80181d4 <_printf_common+0x48> 80181c6: f104 0a19 add.w sl, r4, #25 80181ca: 68e3 ldr r3, [r4, #12] 80181cc: 6832 ldr r2, [r6, #0] 80181ce: 1a9b subs r3, r3, r2 80181d0: 42ab cmp r3, r5 80181d2: dc26 bgt.n 8018222 <_printf_common+0x96> 80181d4: f894 3043 ldrb.w r3, [r4, #67] @ 0x43 80181d8: 6822 ldr r2, [r4, #0] 80181da: 3b00 subs r3, #0 80181dc: bf18 it ne 80181de: 2301 movne r3, #1 80181e0: 0692 lsls r2, r2, #26 80181e2: d42b bmi.n 801823c <_printf_common+0xb0> 80181e4: f104 0243 add.w r2, r4, #67 @ 0x43 80181e8: 4641 mov r1, r8 80181ea: 4638 mov r0, r7 80181ec: 47c8 blx r9 80181ee: 3001 adds r0, #1 80181f0: d01e beq.n 8018230 <_printf_common+0xa4> 80181f2: 6823 ldr r3, [r4, #0] 80181f4: 6922 ldr r2, [r4, #16] 80181f6: f003 0306 and.w r3, r3, #6 80181fa: 2b04 cmp r3, #4 80181fc: bf02 ittt eq 80181fe: 68e5 ldreq r5, [r4, #12] 8018200: 6833 ldreq r3, [r6, #0] 8018202: 1aed subeq r5, r5, r3 8018204: 68a3 ldr r3, [r4, #8] 8018206: bf0c ite eq 8018208: ea25 75e5 biceq.w r5, r5, r5, asr #31 801820c: 2500 movne r5, #0 801820e: 4293 cmp r3, r2 8018210: bfc4 itt gt 8018212: 1a9b subgt r3, r3, r2 8018214: 18ed addgt r5, r5, r3 8018216: 2600 movs r6, #0 8018218: 341a adds r4, #26 801821a: 42b5 cmp r5, r6 801821c: d11a bne.n 8018254 <_printf_common+0xc8> 801821e: 2000 movs r0, #0 8018220: e008 b.n 8018234 <_printf_common+0xa8> 8018222: 2301 movs r3, #1 8018224: 4652 mov r2, sl 8018226: 4641 mov r1, r8 8018228: 4638 mov r0, r7 801822a: 47c8 blx r9 801822c: 3001 adds r0, #1 801822e: d103 bne.n 8018238 <_printf_common+0xac> 8018230: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 8018234: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8018238: 3501 adds r5, #1 801823a: e7c6 b.n 80181ca <_printf_common+0x3e> 801823c: 18e1 adds r1, r4, r3 801823e: 1c5a adds r2, r3, #1 8018240: 2030 movs r0, #48 @ 0x30 8018242: f881 0043 strb.w r0, [r1, #67] @ 0x43 8018246: 4422 add r2, r4 8018248: f894 1045 ldrb.w r1, [r4, #69] @ 0x45 801824c: f882 1043 strb.w r1, [r2, #67] @ 0x43 8018250: 3302 adds r3, #2 8018252: e7c7 b.n 80181e4 <_printf_common+0x58> 8018254: 2301 movs r3, #1 8018256: 4622 mov r2, r4 8018258: 4641 mov r1, r8 801825a: 4638 mov r0, r7 801825c: 47c8 blx r9 801825e: 3001 adds r0, #1 8018260: d0e6 beq.n 8018230 <_printf_common+0xa4> 8018262: 3601 adds r6, #1 8018264: e7d9 b.n 801821a <_printf_common+0x8e> ... 08018268 <_printf_i>: 8018268: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} 801826c: 7e0f ldrb r7, [r1, #24] 801826e: 9e0c ldr r6, [sp, #48] @ 0x30 8018270: 2f78 cmp r7, #120 @ 0x78 8018272: 4691 mov r9, r2 8018274: 4680 mov r8, r0 8018276: 460c mov r4, r1 8018278: 469a mov sl, r3 801827a: f101 0243 add.w r2, r1, #67 @ 0x43 801827e: d807 bhi.n 8018290 <_printf_i+0x28> 8018280: 2f62 cmp r7, #98 @ 0x62 8018282: d80a bhi.n 801829a <_printf_i+0x32> 8018284: 2f00 cmp r7, #0 8018286: f000 80d2 beq.w 801842e <_printf_i+0x1c6> 801828a: 2f58 cmp r7, #88 @ 0x58 801828c: f000 80b9 beq.w 8018402 <_printf_i+0x19a> 8018290: f104 0642 add.w r6, r4, #66 @ 0x42 8018294: f884 7042 strb.w r7, [r4, #66] @ 0x42 8018298: e03a b.n 8018310 <_printf_i+0xa8> 801829a: f1a7 0363 sub.w r3, r7, #99 @ 0x63 801829e: 2b15 cmp r3, #21 80182a0: d8f6 bhi.n 8018290 <_printf_i+0x28> 80182a2: a101 add r1, pc, #4 @ (adr r1, 80182a8 <_printf_i+0x40>) 80182a4: f851 f023 ldr.w pc, [r1, r3, lsl #2] 80182a8: 08018301 .word 0x08018301 80182ac: 08018315 .word 0x08018315 80182b0: 08018291 .word 0x08018291 80182b4: 08018291 .word 0x08018291 80182b8: 08018291 .word 0x08018291 80182bc: 08018291 .word 0x08018291 80182c0: 08018315 .word 0x08018315 80182c4: 08018291 .word 0x08018291 80182c8: 08018291 .word 0x08018291 80182cc: 08018291 .word 0x08018291 80182d0: 08018291 .word 0x08018291 80182d4: 08018415 .word 0x08018415 80182d8: 0801833f .word 0x0801833f 80182dc: 080183cf .word 0x080183cf 80182e0: 08018291 .word 0x08018291 80182e4: 08018291 .word 0x08018291 80182e8: 08018437 .word 0x08018437 80182ec: 08018291 .word 0x08018291 80182f0: 0801833f .word 0x0801833f 80182f4: 08018291 .word 0x08018291 80182f8: 08018291 .word 0x08018291 80182fc: 080183d7 .word 0x080183d7 8018300: 6833 ldr r3, [r6, #0] 8018302: 1d1a adds r2, r3, #4 8018304: 681b ldr r3, [r3, #0] 8018306: 6032 str r2, [r6, #0] 8018308: f104 0642 add.w r6, r4, #66 @ 0x42 801830c: f884 3042 strb.w r3, [r4, #66] @ 0x42 8018310: 2301 movs r3, #1 8018312: e09d b.n 8018450 <_printf_i+0x1e8> 8018314: 6833 ldr r3, [r6, #0] 8018316: 6820 ldr r0, [r4, #0] 8018318: 1d19 adds r1, r3, #4 801831a: 6031 str r1, [r6, #0] 801831c: 0606 lsls r6, r0, #24 801831e: d501 bpl.n 8018324 <_printf_i+0xbc> 8018320: 681d ldr r5, [r3, #0] 8018322: e003 b.n 801832c <_printf_i+0xc4> 8018324: 0645 lsls r5, r0, #25 8018326: d5fb bpl.n 8018320 <_printf_i+0xb8> 8018328: f9b3 5000 ldrsh.w r5, [r3] 801832c: 2d00 cmp r5, #0 801832e: da03 bge.n 8018338 <_printf_i+0xd0> 8018330: 232d movs r3, #45 @ 0x2d 8018332: 426d negs r5, r5 8018334: f884 3043 strb.w r3, [r4, #67] @ 0x43 8018338: 4859 ldr r0, [pc, #356] @ (80184a0 <_printf_i+0x238>) 801833a: 230a movs r3, #10 801833c: e011 b.n 8018362 <_printf_i+0xfa> 801833e: 6821 ldr r1, [r4, #0] 8018340: 6833 ldr r3, [r6, #0] 8018342: 0608 lsls r0, r1, #24 8018344: f853 5b04 ldr.w r5, [r3], #4 8018348: d402 bmi.n 8018350 <_printf_i+0xe8> 801834a: 0649 lsls r1, r1, #25 801834c: bf48 it mi 801834e: b2ad uxthmi r5, r5 8018350: 2f6f cmp r7, #111 @ 0x6f 8018352: 4853 ldr r0, [pc, #332] @ (80184a0 <_printf_i+0x238>) 8018354: 6033 str r3, [r6, #0] 8018356: bf14 ite ne 8018358: 230a movne r3, #10 801835a: 2308 moveq r3, #8 801835c: 2100 movs r1, #0 801835e: f884 1043 strb.w r1, [r4, #67] @ 0x43 8018362: 6866 ldr r6, [r4, #4] 8018364: 60a6 str r6, [r4, #8] 8018366: 2e00 cmp r6, #0 8018368: bfa2 ittt ge 801836a: 6821 ldrge r1, [r4, #0] 801836c: f021 0104 bicge.w r1, r1, #4 8018370: 6021 strge r1, [r4, #0] 8018372: b90d cbnz r5, 8018378 <_printf_i+0x110> 8018374: 2e00 cmp r6, #0 8018376: d04b beq.n 8018410 <_printf_i+0x1a8> 8018378: 4616 mov r6, r2 801837a: fbb5 f1f3 udiv r1, r5, r3 801837e: fb03 5711 mls r7, r3, r1, r5 8018382: 5dc7 ldrb r7, [r0, r7] 8018384: f806 7d01 strb.w r7, [r6, #-1]! 8018388: 462f mov r7, r5 801838a: 42bb cmp r3, r7 801838c: 460d mov r5, r1 801838e: d9f4 bls.n 801837a <_printf_i+0x112> 8018390: 2b08 cmp r3, #8 8018392: d10b bne.n 80183ac <_printf_i+0x144> 8018394: 6823 ldr r3, [r4, #0] 8018396: 07df lsls r7, r3, #31 8018398: d508 bpl.n 80183ac <_printf_i+0x144> 801839a: 6923 ldr r3, [r4, #16] 801839c: 6861 ldr r1, [r4, #4] 801839e: 4299 cmp r1, r3 80183a0: bfde ittt le 80183a2: 2330 movle r3, #48 @ 0x30 80183a4: f806 3c01 strble.w r3, [r6, #-1] 80183a8: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff 80183ac: 1b92 subs r2, r2, r6 80183ae: 6122 str r2, [r4, #16] 80183b0: f8cd a000 str.w sl, [sp] 80183b4: 464b mov r3, r9 80183b6: aa03 add r2, sp, #12 80183b8: 4621 mov r1, r4 80183ba: 4640 mov r0, r8 80183bc: f7ff fee6 bl 801818c <_printf_common> 80183c0: 3001 adds r0, #1 80183c2: d14a bne.n 801845a <_printf_i+0x1f2> 80183c4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80183c8: b004 add sp, #16 80183ca: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80183ce: 6823 ldr r3, [r4, #0] 80183d0: f043 0320 orr.w r3, r3, #32 80183d4: 6023 str r3, [r4, #0] 80183d6: 4833 ldr r0, [pc, #204] @ (80184a4 <_printf_i+0x23c>) 80183d8: 2778 movs r7, #120 @ 0x78 80183da: f884 7045 strb.w r7, [r4, #69] @ 0x45 80183de: 6823 ldr r3, [r4, #0] 80183e0: 6831 ldr r1, [r6, #0] 80183e2: 061f lsls r7, r3, #24 80183e4: f851 5b04 ldr.w r5, [r1], #4 80183e8: d402 bmi.n 80183f0 <_printf_i+0x188> 80183ea: 065f lsls r7, r3, #25 80183ec: bf48 it mi 80183ee: b2ad uxthmi r5, r5 80183f0: 6031 str r1, [r6, #0] 80183f2: 07d9 lsls r1, r3, #31 80183f4: bf44 itt mi 80183f6: f043 0320 orrmi.w r3, r3, #32 80183fa: 6023 strmi r3, [r4, #0] 80183fc: b11d cbz r5, 8018406 <_printf_i+0x19e> 80183fe: 2310 movs r3, #16 8018400: e7ac b.n 801835c <_printf_i+0xf4> 8018402: 4827 ldr r0, [pc, #156] @ (80184a0 <_printf_i+0x238>) 8018404: e7e9 b.n 80183da <_printf_i+0x172> 8018406: 6823 ldr r3, [r4, #0] 8018408: f023 0320 bic.w r3, r3, #32 801840c: 6023 str r3, [r4, #0] 801840e: e7f6 b.n 80183fe <_printf_i+0x196> 8018410: 4616 mov r6, r2 8018412: e7bd b.n 8018390 <_printf_i+0x128> 8018414: 6833 ldr r3, [r6, #0] 8018416: 6825 ldr r5, [r4, #0] 8018418: 6961 ldr r1, [r4, #20] 801841a: 1d18 adds r0, r3, #4 801841c: 6030 str r0, [r6, #0] 801841e: 062e lsls r6, r5, #24 8018420: 681b ldr r3, [r3, #0] 8018422: d501 bpl.n 8018428 <_printf_i+0x1c0> 8018424: 6019 str r1, [r3, #0] 8018426: e002 b.n 801842e <_printf_i+0x1c6> 8018428: 0668 lsls r0, r5, #25 801842a: d5fb bpl.n 8018424 <_printf_i+0x1bc> 801842c: 8019 strh r1, [r3, #0] 801842e: 2300 movs r3, #0 8018430: 6123 str r3, [r4, #16] 8018432: 4616 mov r6, r2 8018434: e7bc b.n 80183b0 <_printf_i+0x148> 8018436: 6833 ldr r3, [r6, #0] 8018438: 1d1a adds r2, r3, #4 801843a: 6032 str r2, [r6, #0] 801843c: 681e ldr r6, [r3, #0] 801843e: 6862 ldr r2, [r4, #4] 8018440: 2100 movs r1, #0 8018442: 4630 mov r0, r6 8018444: f7e7 ff4c bl 80002e0 8018448: b108 cbz r0, 801844e <_printf_i+0x1e6> 801844a: 1b80 subs r0, r0, r6 801844c: 6060 str r0, [r4, #4] 801844e: 6863 ldr r3, [r4, #4] 8018450: 6123 str r3, [r4, #16] 8018452: 2300 movs r3, #0 8018454: f884 3043 strb.w r3, [r4, #67] @ 0x43 8018458: e7aa b.n 80183b0 <_printf_i+0x148> 801845a: 6923 ldr r3, [r4, #16] 801845c: 4632 mov r2, r6 801845e: 4649 mov r1, r9 8018460: 4640 mov r0, r8 8018462: 47d0 blx sl 8018464: 3001 adds r0, #1 8018466: d0ad beq.n 80183c4 <_printf_i+0x15c> 8018468: 6823 ldr r3, [r4, #0] 801846a: 079b lsls r3, r3, #30 801846c: d413 bmi.n 8018496 <_printf_i+0x22e> 801846e: 68e0 ldr r0, [r4, #12] 8018470: 9b03 ldr r3, [sp, #12] 8018472: 4298 cmp r0, r3 8018474: bfb8 it lt 8018476: 4618 movlt r0, r3 8018478: e7a6 b.n 80183c8 <_printf_i+0x160> 801847a: 2301 movs r3, #1 801847c: 4632 mov r2, r6 801847e: 4649 mov r1, r9 8018480: 4640 mov r0, r8 8018482: 47d0 blx sl 8018484: 3001 adds r0, #1 8018486: d09d beq.n 80183c4 <_printf_i+0x15c> 8018488: 3501 adds r5, #1 801848a: 68e3 ldr r3, [r4, #12] 801848c: 9903 ldr r1, [sp, #12] 801848e: 1a5b subs r3, r3, r1 8018490: 42ab cmp r3, r5 8018492: dcf2 bgt.n 801847a <_printf_i+0x212> 8018494: e7eb b.n 801846e <_printf_i+0x206> 8018496: 2500 movs r5, #0 8018498: f104 0619 add.w r6, r4, #25 801849c: e7f5 b.n 801848a <_printf_i+0x222> 801849e: bf00 nop 80184a0: 08018a19 .word 0x08018a19 80184a4: 08018a2a .word 0x08018a2a 080184a8 <__sflush_r>: 80184a8: f9b1 200c ldrsh.w r2, [r1, #12] 80184ac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} 80184b0: 0716 lsls r6, r2, #28 80184b2: 4605 mov r5, r0 80184b4: 460c mov r4, r1 80184b6: d454 bmi.n 8018562 <__sflush_r+0xba> 80184b8: 684b ldr r3, [r1, #4] 80184ba: 2b00 cmp r3, #0 80184bc: dc02 bgt.n 80184c4 <__sflush_r+0x1c> 80184be: 6c0b ldr r3, [r1, #64] @ 0x40 80184c0: 2b00 cmp r3, #0 80184c2: dd48 ble.n 8018556 <__sflush_r+0xae> 80184c4: 6ae6 ldr r6, [r4, #44] @ 0x2c 80184c6: 2e00 cmp r6, #0 80184c8: d045 beq.n 8018556 <__sflush_r+0xae> 80184ca: 2300 movs r3, #0 80184cc: f412 5280 ands.w r2, r2, #4096 @ 0x1000 80184d0: 682f ldr r7, [r5, #0] 80184d2: 6a21 ldr r1, [r4, #32] 80184d4: 602b str r3, [r5, #0] 80184d6: d030 beq.n 801853a <__sflush_r+0x92> 80184d8: 6d62 ldr r2, [r4, #84] @ 0x54 80184da: 89a3 ldrh r3, [r4, #12] 80184dc: 0759 lsls r1, r3, #29 80184de: d505 bpl.n 80184ec <__sflush_r+0x44> 80184e0: 6863 ldr r3, [r4, #4] 80184e2: 1ad2 subs r2, r2, r3 80184e4: 6b63 ldr r3, [r4, #52] @ 0x34 80184e6: b10b cbz r3, 80184ec <__sflush_r+0x44> 80184e8: 6c23 ldr r3, [r4, #64] @ 0x40 80184ea: 1ad2 subs r2, r2, r3 80184ec: 2300 movs r3, #0 80184ee: 6ae6 ldr r6, [r4, #44] @ 0x2c 80184f0: 6a21 ldr r1, [r4, #32] 80184f2: 4628 mov r0, r5 80184f4: 47b0 blx r6 80184f6: 1c43 adds r3, r0, #1 80184f8: 89a3 ldrh r3, [r4, #12] 80184fa: d106 bne.n 801850a <__sflush_r+0x62> 80184fc: 6829 ldr r1, [r5, #0] 80184fe: 291d cmp r1, #29 8018500: d82b bhi.n 801855a <__sflush_r+0xb2> 8018502: 4a2a ldr r2, [pc, #168] @ (80185ac <__sflush_r+0x104>) 8018504: 410a asrs r2, r1 8018506: 07d6 lsls r6, r2, #31 8018508: d427 bmi.n 801855a <__sflush_r+0xb2> 801850a: 2200 movs r2, #0 801850c: 6062 str r2, [r4, #4] 801850e: 04d9 lsls r1, r3, #19 8018510: 6922 ldr r2, [r4, #16] 8018512: 6022 str r2, [r4, #0] 8018514: d504 bpl.n 8018520 <__sflush_r+0x78> 8018516: 1c42 adds r2, r0, #1 8018518: d101 bne.n 801851e <__sflush_r+0x76> 801851a: 682b ldr r3, [r5, #0] 801851c: b903 cbnz r3, 8018520 <__sflush_r+0x78> 801851e: 6560 str r0, [r4, #84] @ 0x54 8018520: 6b61 ldr r1, [r4, #52] @ 0x34 8018522: 602f str r7, [r5, #0] 8018524: b1b9 cbz r1, 8018556 <__sflush_r+0xae> 8018526: f104 0344 add.w r3, r4, #68 @ 0x44 801852a: 4299 cmp r1, r3 801852c: d002 beq.n 8018534 <__sflush_r+0x8c> 801852e: 4628 mov r0, r5 8018530: f7ff fbf2 bl 8017d18 <_free_r> 8018534: 2300 movs r3, #0 8018536: 6363 str r3, [r4, #52] @ 0x34 8018538: e00d b.n 8018556 <__sflush_r+0xae> 801853a: 2301 movs r3, #1 801853c: 4628 mov r0, r5 801853e: 47b0 blx r6 8018540: 4602 mov r2, r0 8018542: 1c50 adds r0, r2, #1 8018544: d1c9 bne.n 80184da <__sflush_r+0x32> 8018546: 682b ldr r3, [r5, #0] 8018548: 2b00 cmp r3, #0 801854a: d0c6 beq.n 80184da <__sflush_r+0x32> 801854c: 2b1d cmp r3, #29 801854e: d001 beq.n 8018554 <__sflush_r+0xac> 8018550: 2b16 cmp r3, #22 8018552: d11e bne.n 8018592 <__sflush_r+0xea> 8018554: 602f str r7, [r5, #0] 8018556: 2000 movs r0, #0 8018558: e022 b.n 80185a0 <__sflush_r+0xf8> 801855a: f043 0340 orr.w r3, r3, #64 @ 0x40 801855e: b21b sxth r3, r3 8018560: e01b b.n 801859a <__sflush_r+0xf2> 8018562: 690f ldr r7, [r1, #16] 8018564: 2f00 cmp r7, #0 8018566: d0f6 beq.n 8018556 <__sflush_r+0xae> 8018568: 0793 lsls r3, r2, #30 801856a: 680e ldr r6, [r1, #0] 801856c: bf08 it eq 801856e: 694b ldreq r3, [r1, #20] 8018570: 600f str r7, [r1, #0] 8018572: bf18 it ne 8018574: 2300 movne r3, #0 8018576: eba6 0807 sub.w r8, r6, r7 801857a: 608b str r3, [r1, #8] 801857c: f1b8 0f00 cmp.w r8, #0 8018580: dde9 ble.n 8018556 <__sflush_r+0xae> 8018582: 6a21 ldr r1, [r4, #32] 8018584: 6aa6 ldr r6, [r4, #40] @ 0x28 8018586: 4643 mov r3, r8 8018588: 463a mov r2, r7 801858a: 4628 mov r0, r5 801858c: 47b0 blx r6 801858e: 2800 cmp r0, #0 8018590: dc08 bgt.n 80185a4 <__sflush_r+0xfc> 8018592: f9b4 300c ldrsh.w r3, [r4, #12] 8018596: f043 0340 orr.w r3, r3, #64 @ 0x40 801859a: 81a3 strh r3, [r4, #12] 801859c: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80185a0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 80185a4: 4407 add r7, r0 80185a6: eba8 0800 sub.w r8, r8, r0 80185aa: e7e7 b.n 801857c <__sflush_r+0xd4> 80185ac: dfbffffe .word 0xdfbffffe 080185b0 <_fflush_r>: 80185b0: b538 push {r3, r4, r5, lr} 80185b2: 690b ldr r3, [r1, #16] 80185b4: 4605 mov r5, r0 80185b6: 460c mov r4, r1 80185b8: b913 cbnz r3, 80185c0 <_fflush_r+0x10> 80185ba: 2500 movs r5, #0 80185bc: 4628 mov r0, r5 80185be: bd38 pop {r3, r4, r5, pc} 80185c0: b118 cbz r0, 80185ca <_fflush_r+0x1a> 80185c2: 6a03 ldr r3, [r0, #32] 80185c4: b90b cbnz r3, 80185ca <_fflush_r+0x1a> 80185c6: f7ff fa3b bl 8017a40 <__sinit> 80185ca: f9b4 300c ldrsh.w r3, [r4, #12] 80185ce: 2b00 cmp r3, #0 80185d0: d0f3 beq.n 80185ba <_fflush_r+0xa> 80185d2: 6e62 ldr r2, [r4, #100] @ 0x64 80185d4: 07d0 lsls r0, r2, #31 80185d6: d404 bmi.n 80185e2 <_fflush_r+0x32> 80185d8: 0599 lsls r1, r3, #22 80185da: d402 bmi.n 80185e2 <_fflush_r+0x32> 80185dc: 6da0 ldr r0, [r4, #88] @ 0x58 80185de: f7ff fb8a bl 8017cf6 <__retarget_lock_acquire_recursive> 80185e2: 4628 mov r0, r5 80185e4: 4621 mov r1, r4 80185e6: f7ff ff5f bl 80184a8 <__sflush_r> 80185ea: 6e63 ldr r3, [r4, #100] @ 0x64 80185ec: 07da lsls r2, r3, #31 80185ee: 4605 mov r5, r0 80185f0: d4e4 bmi.n 80185bc <_fflush_r+0xc> 80185f2: 89a3 ldrh r3, [r4, #12] 80185f4: 059b lsls r3, r3, #22 80185f6: d4e1 bmi.n 80185bc <_fflush_r+0xc> 80185f8: 6da0 ldr r0, [r4, #88] @ 0x58 80185fa: f7ff fb7d bl 8017cf8 <__retarget_lock_release_recursive> 80185fe: e7dd b.n 80185bc <_fflush_r+0xc> 08018600 <__swbuf_r>: 8018600: b5f8 push {r3, r4, r5, r6, r7, lr} 8018602: 460e mov r6, r1 8018604: 4614 mov r4, r2 8018606: 4605 mov r5, r0 8018608: b118 cbz r0, 8018612 <__swbuf_r+0x12> 801860a: 6a03 ldr r3, [r0, #32] 801860c: b90b cbnz r3, 8018612 <__swbuf_r+0x12> 801860e: f7ff fa17 bl 8017a40 <__sinit> 8018612: 69a3 ldr r3, [r4, #24] 8018614: 60a3 str r3, [r4, #8] 8018616: 89a3 ldrh r3, [r4, #12] 8018618: 071a lsls r2, r3, #28 801861a: d501 bpl.n 8018620 <__swbuf_r+0x20> 801861c: 6923 ldr r3, [r4, #16] 801861e: b943 cbnz r3, 8018632 <__swbuf_r+0x32> 8018620: 4621 mov r1, r4 8018622: 4628 mov r0, r5 8018624: f000 f82a bl 801867c <__swsetup_r> 8018628: b118 cbz r0, 8018632 <__swbuf_r+0x32> 801862a: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff 801862e: 4638 mov r0, r7 8018630: bdf8 pop {r3, r4, r5, r6, r7, pc} 8018632: 6823 ldr r3, [r4, #0] 8018634: 6922 ldr r2, [r4, #16] 8018636: 1a98 subs r0, r3, r2 8018638: 6963 ldr r3, [r4, #20] 801863a: b2f6 uxtb r6, r6 801863c: 4283 cmp r3, r0 801863e: 4637 mov r7, r6 8018640: dc05 bgt.n 801864e <__swbuf_r+0x4e> 8018642: 4621 mov r1, r4 8018644: 4628 mov r0, r5 8018646: f7ff ffb3 bl 80185b0 <_fflush_r> 801864a: 2800 cmp r0, #0 801864c: d1ed bne.n 801862a <__swbuf_r+0x2a> 801864e: 68a3 ldr r3, [r4, #8] 8018650: 3b01 subs r3, #1 8018652: 60a3 str r3, [r4, #8] 8018654: 6823 ldr r3, [r4, #0] 8018656: 1c5a adds r2, r3, #1 8018658: 6022 str r2, [r4, #0] 801865a: 701e strb r6, [r3, #0] 801865c: 6962 ldr r2, [r4, #20] 801865e: 1c43 adds r3, r0, #1 8018660: 429a cmp r2, r3 8018662: d004 beq.n 801866e <__swbuf_r+0x6e> 8018664: 89a3 ldrh r3, [r4, #12] 8018666: 07db lsls r3, r3, #31 8018668: d5e1 bpl.n 801862e <__swbuf_r+0x2e> 801866a: 2e0a cmp r6, #10 801866c: d1df bne.n 801862e <__swbuf_r+0x2e> 801866e: 4621 mov r1, r4 8018670: 4628 mov r0, r5 8018672: f7ff ff9d bl 80185b0 <_fflush_r> 8018676: 2800 cmp r0, #0 8018678: d0d9 beq.n 801862e <__swbuf_r+0x2e> 801867a: e7d6 b.n 801862a <__swbuf_r+0x2a> 0801867c <__swsetup_r>: 801867c: b538 push {r3, r4, r5, lr} 801867e: 4b29 ldr r3, [pc, #164] @ (8018724 <__swsetup_r+0xa8>) 8018680: 4605 mov r5, r0 8018682: 6818 ldr r0, [r3, #0] 8018684: 460c mov r4, r1 8018686: b118 cbz r0, 8018690 <__swsetup_r+0x14> 8018688: 6a03 ldr r3, [r0, #32] 801868a: b90b cbnz r3, 8018690 <__swsetup_r+0x14> 801868c: f7ff f9d8 bl 8017a40 <__sinit> 8018690: f9b4 300c ldrsh.w r3, [r4, #12] 8018694: 0719 lsls r1, r3, #28 8018696: d422 bmi.n 80186de <__swsetup_r+0x62> 8018698: 06da lsls r2, r3, #27 801869a: d407 bmi.n 80186ac <__swsetup_r+0x30> 801869c: 2209 movs r2, #9 801869e: 602a str r2, [r5, #0] 80186a0: f043 0340 orr.w r3, r3, #64 @ 0x40 80186a4: 81a3 strh r3, [r4, #12] 80186a6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff 80186aa: e033 b.n 8018714 <__swsetup_r+0x98> 80186ac: 0758 lsls r0, r3, #29 80186ae: d512 bpl.n 80186d6 <__swsetup_r+0x5a> 80186b0: 6b61 ldr r1, [r4, #52] @ 0x34 80186b2: b141 cbz r1, 80186c6 <__swsetup_r+0x4a> 80186b4: f104 0344 add.w r3, r4, #68 @ 0x44 80186b8: 4299 cmp r1, r3 80186ba: d002 beq.n 80186c2 <__swsetup_r+0x46> 80186bc: 4628 mov r0, r5 80186be: f7ff fb2b bl 8017d18 <_free_r> 80186c2: 2300 movs r3, #0 80186c4: 6363 str r3, [r4, #52] @ 0x34 80186c6: 89a3 ldrh r3, [r4, #12] 80186c8: f023 0324 bic.w r3, r3, #36 @ 0x24 80186cc: 81a3 strh r3, [r4, #12] 80186ce: 2300 movs r3, #0 80186d0: 6063 str r3, [r4, #4] 80186d2: 6923 ldr r3, [r4, #16] 80186d4: 6023 str r3, [r4, #0] 80186d6: 89a3 ldrh r3, [r4, #12] 80186d8: f043 0308 orr.w r3, r3, #8 80186dc: 81a3 strh r3, [r4, #12] 80186de: 6923 ldr r3, [r4, #16] 80186e0: b94b cbnz r3, 80186f6 <__swsetup_r+0x7a> 80186e2: 89a3 ldrh r3, [r4, #12] 80186e4: f403 7320 and.w r3, r3, #640 @ 0x280 80186e8: f5b3 7f00 cmp.w r3, #512 @ 0x200 80186ec: d003 beq.n 80186f6 <__swsetup_r+0x7a> 80186ee: 4621 mov r1, r4 80186f0: 4628 mov r0, r5 80186f2: f000 f84f bl 8018794 <__smakebuf_r> 80186f6: f9b4 300c ldrsh.w r3, [r4, #12] 80186fa: f013 0201 ands.w r2, r3, #1 80186fe: d00a beq.n 8018716 <__swsetup_r+0x9a> 8018700: 2200 movs r2, #0 8018702: 60a2 str r2, [r4, #8] 8018704: 6962 ldr r2, [r4, #20] 8018706: 4252 negs r2, r2 8018708: 61a2 str r2, [r4, #24] 801870a: 6922 ldr r2, [r4, #16] 801870c: b942 cbnz r2, 8018720 <__swsetup_r+0xa4> 801870e: f013 0080 ands.w r0, r3, #128 @ 0x80 8018712: d1c5 bne.n 80186a0 <__swsetup_r+0x24> 8018714: bd38 pop {r3, r4, r5, pc} 8018716: 0799 lsls r1, r3, #30 8018718: bf58 it pl 801871a: 6962 ldrpl r2, [r4, #20] 801871c: 60a2 str r2, [r4, #8] 801871e: e7f4 b.n 801870a <__swsetup_r+0x8e> 8018720: 2000 movs r0, #0 8018722: e7f7 b.n 8018714 <__swsetup_r+0x98> 8018724: 24000054 .word 0x24000054 08018728 <_sbrk_r>: 8018728: b538 push {r3, r4, r5, lr} 801872a: 4d06 ldr r5, [pc, #24] @ (8018744 <_sbrk_r+0x1c>) 801872c: 2300 movs r3, #0 801872e: 4604 mov r4, r0 8018730: 4608 mov r0, r1 8018732: 602b str r3, [r5, #0] 8018734: f7eb fca0 bl 8004078 <_sbrk> 8018738: 1c43 adds r3, r0, #1 801873a: d102 bne.n 8018742 <_sbrk_r+0x1a> 801873c: 682b ldr r3, [r5, #0] 801873e: b103 cbz r3, 8018742 <_sbrk_r+0x1a> 8018740: 6023 str r3, [r4, #0] 8018742: bd38 pop {r3, r4, r5, pc} 8018744: 24012dd0 .word 0x24012dd0 08018748 <__swhatbuf_r>: 8018748: b570 push {r4, r5, r6, lr} 801874a: 460c mov r4, r1 801874c: f9b1 100e ldrsh.w r1, [r1, #14] 8018750: 2900 cmp r1, #0 8018752: b096 sub sp, #88 @ 0x58 8018754: 4615 mov r5, r2 8018756: 461e mov r6, r3 8018758: da0d bge.n 8018776 <__swhatbuf_r+0x2e> 801875a: 89a3 ldrh r3, [r4, #12] 801875c: f013 0f80 tst.w r3, #128 @ 0x80 8018760: f04f 0100 mov.w r1, #0 8018764: bf14 ite ne 8018766: 2340 movne r3, #64 @ 0x40 8018768: f44f 6380 moveq.w r3, #1024 @ 0x400 801876c: 2000 movs r0, #0 801876e: 6031 str r1, [r6, #0] 8018770: 602b str r3, [r5, #0] 8018772: b016 add sp, #88 @ 0x58 8018774: bd70 pop {r4, r5, r6, pc} 8018776: 466a mov r2, sp 8018778: f000 f848 bl 801880c <_fstat_r> 801877c: 2800 cmp r0, #0 801877e: dbec blt.n 801875a <__swhatbuf_r+0x12> 8018780: 9901 ldr r1, [sp, #4] 8018782: f401 4170 and.w r1, r1, #61440 @ 0xf000 8018786: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000 801878a: 4259 negs r1, r3 801878c: 4159 adcs r1, r3 801878e: f44f 6380 mov.w r3, #1024 @ 0x400 8018792: e7eb b.n 801876c <__swhatbuf_r+0x24> 08018794 <__smakebuf_r>: 8018794: 898b ldrh r3, [r1, #12] 8018796: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} 8018798: 079d lsls r5, r3, #30 801879a: 4606 mov r6, r0 801879c: 460c mov r4, r1 801879e: d507 bpl.n 80187b0 <__smakebuf_r+0x1c> 80187a0: f104 0347 add.w r3, r4, #71 @ 0x47 80187a4: 6023 str r3, [r4, #0] 80187a6: 6123 str r3, [r4, #16] 80187a8: 2301 movs r3, #1 80187aa: 6163 str r3, [r4, #20] 80187ac: b003 add sp, #12 80187ae: bdf0 pop {r4, r5, r6, r7, pc} 80187b0: ab01 add r3, sp, #4 80187b2: 466a mov r2, sp 80187b4: f7ff ffc8 bl 8018748 <__swhatbuf_r> 80187b8: 9f00 ldr r7, [sp, #0] 80187ba: 4605 mov r5, r0 80187bc: 4639 mov r1, r7 80187be: 4630 mov r0, r6 80187c0: f7ff fb16 bl 8017df0 <_malloc_r> 80187c4: b948 cbnz r0, 80187da <__smakebuf_r+0x46> 80187c6: f9b4 300c ldrsh.w r3, [r4, #12] 80187ca: 059a lsls r2, r3, #22 80187cc: d4ee bmi.n 80187ac <__smakebuf_r+0x18> 80187ce: f023 0303 bic.w r3, r3, #3 80187d2: f043 0302 orr.w r3, r3, #2 80187d6: 81a3 strh r3, [r4, #12] 80187d8: e7e2 b.n 80187a0 <__smakebuf_r+0xc> 80187da: 89a3 ldrh r3, [r4, #12] 80187dc: 6020 str r0, [r4, #0] 80187de: f043 0380 orr.w r3, r3, #128 @ 0x80 80187e2: 81a3 strh r3, [r4, #12] 80187e4: 9b01 ldr r3, [sp, #4] 80187e6: e9c4 0704 strd r0, r7, [r4, #16] 80187ea: b15b cbz r3, 8018804 <__smakebuf_r+0x70> 80187ec: f9b4 100e ldrsh.w r1, [r4, #14] 80187f0: 4630 mov r0, r6 80187f2: f000 f81d bl 8018830 <_isatty_r> 80187f6: b128 cbz r0, 8018804 <__smakebuf_r+0x70> 80187f8: 89a3 ldrh r3, [r4, #12] 80187fa: f023 0303 bic.w r3, r3, #3 80187fe: f043 0301 orr.w r3, r3, #1 8018802: 81a3 strh r3, [r4, #12] 8018804: 89a3 ldrh r3, [r4, #12] 8018806: 431d orrs r5, r3 8018808: 81a5 strh r5, [r4, #12] 801880a: e7cf b.n 80187ac <__smakebuf_r+0x18> 0801880c <_fstat_r>: 801880c: b538 push {r3, r4, r5, lr} 801880e: 4d07 ldr r5, [pc, #28] @ (801882c <_fstat_r+0x20>) 8018810: 2300 movs r3, #0 8018812: 4604 mov r4, r0 8018814: 4608 mov r0, r1 8018816: 4611 mov r1, r2 8018818: 602b str r3, [r5, #0] 801881a: f7eb fc04 bl 8004026 <_fstat> 801881e: 1c43 adds r3, r0, #1 8018820: d102 bne.n 8018828 <_fstat_r+0x1c> 8018822: 682b ldr r3, [r5, #0] 8018824: b103 cbz r3, 8018828 <_fstat_r+0x1c> 8018826: 6023 str r3, [r4, #0] 8018828: bd38 pop {r3, r4, r5, pc} 801882a: bf00 nop 801882c: 24012dd0 .word 0x24012dd0 08018830 <_isatty_r>: 8018830: b538 push {r3, r4, r5, lr} 8018832: 4d06 ldr r5, [pc, #24] @ (801884c <_isatty_r+0x1c>) 8018834: 2300 movs r3, #0 8018836: 4604 mov r4, r0 8018838: 4608 mov r0, r1 801883a: 602b str r3, [r5, #0] 801883c: f7eb fc03 bl 8004046 <_isatty> 8018840: 1c43 adds r3, r0, #1 8018842: d102 bne.n 801884a <_isatty_r+0x1a> 8018844: 682b ldr r3, [r5, #0] 8018846: b103 cbz r3, 801884a <_isatty_r+0x1a> 8018848: 6023 str r3, [r4, #0] 801884a: bd38 pop {r3, r4, r5, pc} 801884c: 24012dd0 .word 0x24012dd0 08018850 <_init>: 8018850: b5f8 push {r3, r4, r5, r6, r7, lr} 8018852: bf00 nop 8018854: bcf8 pop {r3, r4, r5, r6, r7} 8018856: bc08 pop {r3} 8018858: 469e mov lr, r3 801885a: 4770 bx lr 0801885c <_fini>: 801885c: b5f8 push {r3, r4, r5, r6, r7, lr} 801885e: bf00 nop 8018860: bcf8 pop {r3, r4, r5, r6, r7} 8018862: bc08 pop {r3} 8018864: 469e mov lr, r3 8018866: 4770 bx lr