OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000183a0 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000104 08018640 08018640 00019640 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 08018744 08018744 00019744 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0801874c 0801874c 0001974c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 08018750 08018750 00019750 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 00000098 24000000 08018754 0001a000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 000130ec 240000a0 080187ec 0001a0a0 2**5 ALLOC 8 ._user_heap_stack 00000604 2401318c 080187ec 0001a18c 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 0001a098 2**0 CONTENTS, READONLY 10 .debug_info 0003514c 00000000 00000000 0001a0c6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 00006452 00000000 00000000 0004f212 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00002478 00000000 00000000 00055668 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003ef10 00000000 00000000 00057ae0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 000317e2 00000000 00000000 000969f0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00186a2c 00000000 00000000 000c81d2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 0024ebfe 2**0 CONTENTS, READONLY 17 .debug_rnglists 00001c1d 00000000 00000000 0024ec41 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 00009d14 00000000 00000000 00250860 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 0025a574 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 240000a0 .word 0x240000a0 80002bc: 00000000 .word 0x00000000 80002c0: 08018628 .word 0x08018628 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 240000a4 .word 0x240000a4 80002dc: 08018628 .word 0x08018628 080002e0 <__aeabi_uldivmod>: 80002e0: b953 cbnz r3, 80002f8 <__aeabi_uldivmod+0x18> 80002e2: b94a cbnz r2, 80002f8 <__aeabi_uldivmod+0x18> 80002e4: 2900 cmp r1, #0 80002e6: bf08 it eq 80002e8: 2800 cmpeq r0, #0 80002ea: bf1c itt ne 80002ec: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80002f0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80002f4: f000 b96a b.w 80005cc <__aeabi_idiv0> 80002f8: f1ad 0c08 sub.w ip, sp, #8 80002fc: e96d ce04 strd ip, lr, [sp, #-16]! 8000300: f000 f806 bl 8000310 <__udivmoddi4> 8000304: f8dd e004 ldr.w lr, [sp, #4] 8000308: e9dd 2302 ldrd r2, r3, [sp, #8] 800030c: b004 add sp, #16 800030e: 4770 bx lr 08000310 <__udivmoddi4>: 8000310: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000314: 9d08 ldr r5, [sp, #32] 8000316: 460c mov r4, r1 8000318: 2b00 cmp r3, #0 800031a: d14e bne.n 80003ba <__udivmoddi4+0xaa> 800031c: 4694 mov ip, r2 800031e: 458c cmp ip, r1 8000320: 4686 mov lr, r0 8000322: fab2 f282 clz r2, r2 8000326: d962 bls.n 80003ee <__udivmoddi4+0xde> 8000328: b14a cbz r2, 800033e <__udivmoddi4+0x2e> 800032a: f1c2 0320 rsb r3, r2, #32 800032e: 4091 lsls r1, r2 8000330: fa20 f303 lsr.w r3, r0, r3 8000334: fa0c fc02 lsl.w ip, ip, r2 8000338: 4319 orrs r1, r3 800033a: fa00 fe02 lsl.w lr, r0, r2 800033e: ea4f 471c mov.w r7, ip, lsr #16 8000342: fa1f f68c uxth.w r6, ip 8000346: fbb1 f4f7 udiv r4, r1, r7 800034a: ea4f 431e mov.w r3, lr, lsr #16 800034e: fb07 1114 mls r1, r7, r4, r1 8000352: ea43 4301 orr.w r3, r3, r1, lsl #16 8000356: fb04 f106 mul.w r1, r4, r6 800035a: 4299 cmp r1, r3 800035c: d90a bls.n 8000374 <__udivmoddi4+0x64> 800035e: eb1c 0303 adds.w r3, ip, r3 8000362: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000366: f080 8112 bcs.w 800058e <__udivmoddi4+0x27e> 800036a: 4299 cmp r1, r3 800036c: f240 810f bls.w 800058e <__udivmoddi4+0x27e> 8000370: 3c02 subs r4, #2 8000372: 4463 add r3, ip 8000374: 1a59 subs r1, r3, r1 8000376: fa1f f38e uxth.w r3, lr 800037a: fbb1 f0f7 udiv r0, r1, r7 800037e: fb07 1110 mls r1, r7, r0, r1 8000382: ea43 4301 orr.w r3, r3, r1, lsl #16 8000386: fb00 f606 mul.w r6, r0, r6 800038a: 429e cmp r6, r3 800038c: d90a bls.n 80003a4 <__udivmoddi4+0x94> 800038e: eb1c 0303 adds.w r3, ip, r3 8000392: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000396: f080 80fc bcs.w 8000592 <__udivmoddi4+0x282> 800039a: 429e cmp r6, r3 800039c: f240 80f9 bls.w 8000592 <__udivmoddi4+0x282> 80003a0: 4463 add r3, ip 80003a2: 3802 subs r0, #2 80003a4: 1b9b subs r3, r3, r6 80003a6: ea40 4004 orr.w r0, r0, r4, lsl #16 80003aa: 2100 movs r1, #0 80003ac: b11d cbz r5, 80003b6 <__udivmoddi4+0xa6> 80003ae: 40d3 lsrs r3, r2 80003b0: 2200 movs r2, #0 80003b2: e9c5 3200 strd r3, r2, [r5] 80003b6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80003ba: 428b cmp r3, r1 80003bc: d905 bls.n 80003ca <__udivmoddi4+0xba> 80003be: b10d cbz r5, 80003c4 <__udivmoddi4+0xb4> 80003c0: e9c5 0100 strd r0, r1, [r5] 80003c4: 2100 movs r1, #0 80003c6: 4608 mov r0, r1 80003c8: e7f5 b.n 80003b6 <__udivmoddi4+0xa6> 80003ca: fab3 f183 clz r1, r3 80003ce: 2900 cmp r1, #0 80003d0: d146 bne.n 8000460 <__udivmoddi4+0x150> 80003d2: 42a3 cmp r3, r4 80003d4: d302 bcc.n 80003dc <__udivmoddi4+0xcc> 80003d6: 4290 cmp r0, r2 80003d8: f0c0 80f0 bcc.w 80005bc <__udivmoddi4+0x2ac> 80003dc: 1a86 subs r6, r0, r2 80003de: eb64 0303 sbc.w r3, r4, r3 80003e2: 2001 movs r0, #1 80003e4: 2d00 cmp r5, #0 80003e6: d0e6 beq.n 80003b6 <__udivmoddi4+0xa6> 80003e8: e9c5 6300 strd r6, r3, [r5] 80003ec: e7e3 b.n 80003b6 <__udivmoddi4+0xa6> 80003ee: 2a00 cmp r2, #0 80003f0: f040 8090 bne.w 8000514 <__udivmoddi4+0x204> 80003f4: eba1 040c sub.w r4, r1, ip 80003f8: ea4f 481c mov.w r8, ip, lsr #16 80003fc: fa1f f78c uxth.w r7, ip 8000400: 2101 movs r1, #1 8000402: fbb4 f6f8 udiv r6, r4, r8 8000406: ea4f 431e mov.w r3, lr, lsr #16 800040a: fb08 4416 mls r4, r8, r6, r4 800040e: ea43 4304 orr.w r3, r3, r4, lsl #16 8000412: fb07 f006 mul.w r0, r7, r6 8000416: 4298 cmp r0, r3 8000418: d908 bls.n 800042c <__udivmoddi4+0x11c> 800041a: eb1c 0303 adds.w r3, ip, r3 800041e: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 8000422: d202 bcs.n 800042a <__udivmoddi4+0x11a> 8000424: 4298 cmp r0, r3 8000426: f200 80cd bhi.w 80005c4 <__udivmoddi4+0x2b4> 800042a: 4626 mov r6, r4 800042c: 1a1c subs r4, r3, r0 800042e: fa1f f38e uxth.w r3, lr 8000432: fbb4 f0f8 udiv r0, r4, r8 8000436: fb08 4410 mls r4, r8, r0, r4 800043a: ea43 4304 orr.w r3, r3, r4, lsl #16 800043e: fb00 f707 mul.w r7, r0, r7 8000442: 429f cmp r7, r3 8000444: d908 bls.n 8000458 <__udivmoddi4+0x148> 8000446: eb1c 0303 adds.w r3, ip, r3 800044a: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 800044e: d202 bcs.n 8000456 <__udivmoddi4+0x146> 8000450: 429f cmp r7, r3 8000452: f200 80b0 bhi.w 80005b6 <__udivmoddi4+0x2a6> 8000456: 4620 mov r0, r4 8000458: 1bdb subs r3, r3, r7 800045a: ea40 4006 orr.w r0, r0, r6, lsl #16 800045e: e7a5 b.n 80003ac <__udivmoddi4+0x9c> 8000460: f1c1 0620 rsb r6, r1, #32 8000464: 408b lsls r3, r1 8000466: fa22 f706 lsr.w r7, r2, r6 800046a: 431f orrs r7, r3 800046c: fa20 fc06 lsr.w ip, r0, r6 8000470: fa04 f301 lsl.w r3, r4, r1 8000474: ea43 030c orr.w r3, r3, ip 8000478: 40f4 lsrs r4, r6 800047a: fa00 f801 lsl.w r8, r0, r1 800047e: 0c38 lsrs r0, r7, #16 8000480: ea4f 4913 mov.w r9, r3, lsr #16 8000484: fbb4 fef0 udiv lr, r4, r0 8000488: fa1f fc87 uxth.w ip, r7 800048c: fb00 441e mls r4, r0, lr, r4 8000490: ea49 4404 orr.w r4, r9, r4, lsl #16 8000494: fb0e f90c mul.w r9, lr, ip 8000498: 45a1 cmp r9, r4 800049a: fa02 f201 lsl.w r2, r2, r1 800049e: d90a bls.n 80004b6 <__udivmoddi4+0x1a6> 80004a0: 193c adds r4, r7, r4 80004a2: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 80004a6: f080 8084 bcs.w 80005b2 <__udivmoddi4+0x2a2> 80004aa: 45a1 cmp r9, r4 80004ac: f240 8081 bls.w 80005b2 <__udivmoddi4+0x2a2> 80004b0: f1ae 0e02 sub.w lr, lr, #2 80004b4: 443c add r4, r7 80004b6: eba4 0409 sub.w r4, r4, r9 80004ba: fa1f f983 uxth.w r9, r3 80004be: fbb4 f3f0 udiv r3, r4, r0 80004c2: fb00 4413 mls r4, r0, r3, r4 80004c6: ea49 4404 orr.w r4, r9, r4, lsl #16 80004ca: fb03 fc0c mul.w ip, r3, ip 80004ce: 45a4 cmp ip, r4 80004d0: d907 bls.n 80004e2 <__udivmoddi4+0x1d2> 80004d2: 193c adds r4, r7, r4 80004d4: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80004d8: d267 bcs.n 80005aa <__udivmoddi4+0x29a> 80004da: 45a4 cmp ip, r4 80004dc: d965 bls.n 80005aa <__udivmoddi4+0x29a> 80004de: 3b02 subs r3, #2 80004e0: 443c add r4, r7 80004e2: ea43 400e orr.w r0, r3, lr, lsl #16 80004e6: fba0 9302 umull r9, r3, r0, r2 80004ea: eba4 040c sub.w r4, r4, ip 80004ee: 429c cmp r4, r3 80004f0: 46ce mov lr, r9 80004f2: 469c mov ip, r3 80004f4: d351 bcc.n 800059a <__udivmoddi4+0x28a> 80004f6: d04e beq.n 8000596 <__udivmoddi4+0x286> 80004f8: b155 cbz r5, 8000510 <__udivmoddi4+0x200> 80004fa: ebb8 030e subs.w r3, r8, lr 80004fe: eb64 040c sbc.w r4, r4, ip 8000502: fa04 f606 lsl.w r6, r4, r6 8000506: 40cb lsrs r3, r1 8000508: 431e orrs r6, r3 800050a: 40cc lsrs r4, r1 800050c: e9c5 6400 strd r6, r4, [r5] 8000510: 2100 movs r1, #0 8000512: e750 b.n 80003b6 <__udivmoddi4+0xa6> 8000514: f1c2 0320 rsb r3, r2, #32 8000518: fa20 f103 lsr.w r1, r0, r3 800051c: fa0c fc02 lsl.w ip, ip, r2 8000520: fa24 f303 lsr.w r3, r4, r3 8000524: 4094 lsls r4, r2 8000526: 430c orrs r4, r1 8000528: ea4f 481c mov.w r8, ip, lsr #16 800052c: fa00 fe02 lsl.w lr, r0, r2 8000530: fa1f f78c uxth.w r7, ip 8000534: fbb3 f0f8 udiv r0, r3, r8 8000538: fb08 3110 mls r1, r8, r0, r3 800053c: 0c23 lsrs r3, r4, #16 800053e: ea43 4301 orr.w r3, r3, r1, lsl #16 8000542: fb00 f107 mul.w r1, r0, r7 8000546: 4299 cmp r1, r3 8000548: d908 bls.n 800055c <__udivmoddi4+0x24c> 800054a: eb1c 0303 adds.w r3, ip, r3 800054e: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 8000552: d22c bcs.n 80005ae <__udivmoddi4+0x29e> 8000554: 4299 cmp r1, r3 8000556: d92a bls.n 80005ae <__udivmoddi4+0x29e> 8000558: 3802 subs r0, #2 800055a: 4463 add r3, ip 800055c: 1a5b subs r3, r3, r1 800055e: b2a4 uxth r4, r4 8000560: fbb3 f1f8 udiv r1, r3, r8 8000564: fb08 3311 mls r3, r8, r1, r3 8000568: ea44 4403 orr.w r4, r4, r3, lsl #16 800056c: fb01 f307 mul.w r3, r1, r7 8000570: 42a3 cmp r3, r4 8000572: d908 bls.n 8000586 <__udivmoddi4+0x276> 8000574: eb1c 0404 adds.w r4, ip, r4 8000578: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800057c: d213 bcs.n 80005a6 <__udivmoddi4+0x296> 800057e: 42a3 cmp r3, r4 8000580: d911 bls.n 80005a6 <__udivmoddi4+0x296> 8000582: 3902 subs r1, #2 8000584: 4464 add r4, ip 8000586: 1ae4 subs r4, r4, r3 8000588: ea41 4100 orr.w r1, r1, r0, lsl #16 800058c: e739 b.n 8000402 <__udivmoddi4+0xf2> 800058e: 4604 mov r4, r0 8000590: e6f0 b.n 8000374 <__udivmoddi4+0x64> 8000592: 4608 mov r0, r1 8000594: e706 b.n 80003a4 <__udivmoddi4+0x94> 8000596: 45c8 cmp r8, r9 8000598: d2ae bcs.n 80004f8 <__udivmoddi4+0x1e8> 800059a: ebb9 0e02 subs.w lr, r9, r2 800059e: eb63 0c07 sbc.w ip, r3, r7 80005a2: 3801 subs r0, #1 80005a4: e7a8 b.n 80004f8 <__udivmoddi4+0x1e8> 80005a6: 4631 mov r1, r6 80005a8: e7ed b.n 8000586 <__udivmoddi4+0x276> 80005aa: 4603 mov r3, r0 80005ac: e799 b.n 80004e2 <__udivmoddi4+0x1d2> 80005ae: 4630 mov r0, r6 80005b0: e7d4 b.n 800055c <__udivmoddi4+0x24c> 80005b2: 46d6 mov lr, sl 80005b4: e77f b.n 80004b6 <__udivmoddi4+0x1a6> 80005b6: 4463 add r3, ip 80005b8: 3802 subs r0, #2 80005ba: e74d b.n 8000458 <__udivmoddi4+0x148> 80005bc: 4606 mov r6, r0 80005be: 4623 mov r3, r4 80005c0: 4608 mov r0, r1 80005c2: e70f b.n 80003e4 <__udivmoddi4+0xd4> 80005c4: 3e02 subs r6, #2 80005c6: 4463 add r3, ip 80005c8: e730 b.n 800042c <__udivmoddi4+0x11c> 80005ca: bf00 nop 080005cc <__aeabi_idiv0>: 80005cc: 4770 bx lr 80005ce: bf00 nop 080005d0 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 80005d0: b480 push {r7} 80005d2: b083 sub sp, #12 80005d4: af00 add r7, sp, #0 80005d6: 6078 str r0, [r7, #4] 80005d8: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 80005da: bf00 nop 80005dc: 370c adds r7, #12 80005de: 46bd mov sp, r7 80005e0: f85d 7b04 ldr.w r7, [sp], #4 80005e4: 4770 bx lr ... 080005e8 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 80005e8: b480 push {r7} 80005ea: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 80005ec: f3bf 8f4f dsb sy } 80005f0: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 80005f2: 4b06 ldr r3, [pc, #24] @ (800060c <__NVIC_SystemReset+0x24>) 80005f4: 68db ldr r3, [r3, #12] 80005f6: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80005fa: 4904 ldr r1, [pc, #16] @ (800060c <__NVIC_SystemReset+0x24>) 80005fc: 4b04 ldr r3, [pc, #16] @ (8000610 <__NVIC_SystemReset+0x28>) 80005fe: 4313 orrs r3, r2 8000600: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8000602: f3bf 8f4f dsb sy } 8000606: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 8000608: bf00 nop 800060a: e7fd b.n 8000608 <__NVIC_SystemReset+0x20> 800060c: e000ed00 .word 0xe000ed00 8000610: 05fa0004 .word 0x05fa0004 08000614 : #endif return ch; } void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8000614: b580 push {r7, lr} 8000616: b084 sub sp, #16 8000618: af00 add r7, sp, #0 800061a: 4603 mov r3, r0 800061c: 80fb strh r3, [r7, #6] LimiterSwitchData limiterSwitchData = { 0 }; 800061e: 2300 movs r3, #0 8000620: 60fb str r3, [r7, #12] limiterSwitchData.gpioPin = GPIO_Pin; 8000622: 88fb ldrh r3, [r7, #6] 8000624: 81bb strh r3, [r7, #12] limiterSwitchData.pinState = HAL_GPIO_ReadPin(GPIOD, GPIO_Pin); 8000626: 88fb ldrh r3, [r7, #6] 8000628: 4619 mov r1, r3 800062a: 4808 ldr r0, [pc, #32] @ (800064c ) 800062c: f00a ff7e bl 800b52c 8000630: 4603 mov r3, r0 8000632: 73bb strb r3, [r7, #14] osMessageQueuePut(limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8000634: 4b06 ldr r3, [pc, #24] @ (8000650 ) 8000636: 6818 ldr r0, [r3, #0] 8000638: f107 010c add.w r1, r7, #12 800063c: 2300 movs r3, #0 800063e: 2200 movs r2, #0 8000640: f014 f834 bl 80146ac } 8000644: bf00 nop 8000646: 3710 adds r7, #16 8000648: 46bd mov sp, r7 800064a: bd80 pop {r7, pc} 800064c: 58020c00 .word 0x58020c00 8000650: 2400080c .word 0x2400080c 08000654
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000654: b580 push {r7, lr} 8000656: b084 sub sp, #16 8000658: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 800065a: f001 fbb1 bl 8001dc0 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 800065e: 4b64 ldr r3, [pc, #400] @ (80007f0 ) 8000660: 695b ldr r3, [r3, #20] 8000662: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000666: 2b00 cmp r3, #0 8000668: d11b bne.n 80006a2 __ASM volatile ("dsb 0xF":::"memory"); 800066a: f3bf 8f4f dsb sy } 800066e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000670: f3bf 8f6f isb sy } 8000674: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8000676: 4b5e ldr r3, [pc, #376] @ (80007f0 ) 8000678: 2200 movs r2, #0 800067a: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 800067e: f3bf 8f4f dsb sy } 8000682: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000684: f3bf 8f6f isb sy } 8000688: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 800068a: 4b59 ldr r3, [pc, #356] @ (80007f0 ) 800068c: 695b ldr r3, [r3, #20] 800068e: 4a58 ldr r2, [pc, #352] @ (80007f0 ) 8000690: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000694: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000696: f3bf 8f4f dsb sy } 800069a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800069c: f3bf 8f6f isb sy } 80006a0: e000 b.n 80006a4 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80006a2: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80006a4: 4b52 ldr r3, [pc, #328] @ (80007f0 ) 80006a6: 695b ldr r3, [r3, #20] 80006a8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80006ac: 2b00 cmp r3, #0 80006ae: d138 bne.n 8000722 SCB->CSSELR = 0U; /* select Level 1 data cache */ 80006b0: 4b4f ldr r3, [pc, #316] @ (80007f0 ) 80006b2: 2200 movs r2, #0 80006b4: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 80006b8: f3bf 8f4f dsb sy } 80006bc: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 80006be: 4b4c ldr r3, [pc, #304] @ (80007f0 ) 80006c0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80006c4: 60fb str r3, [r7, #12] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 80006c6: 68fb ldr r3, [r7, #12] 80006c8: 0b5b lsrs r3, r3, #13 80006ca: f3c3 030e ubfx r3, r3, #0, #15 80006ce: 60bb str r3, [r7, #8] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 80006d0: 68fb ldr r3, [r7, #12] 80006d2: 08db lsrs r3, r3, #3 80006d4: f3c3 0309 ubfx r3, r3, #0, #10 80006d8: 607b str r3, [r7, #4] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80006da: 68bb ldr r3, [r7, #8] 80006dc: 015a lsls r2, r3, #5 80006de: f643 73e0 movw r3, #16352 @ 0x3fe0 80006e2: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 80006e4: 687a ldr r2, [r7, #4] 80006e6: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80006e8: 4941 ldr r1, [pc, #260] @ (80007f0 ) 80006ea: 4313 orrs r3, r2 80006ec: f8c1 3260 str.w r3, [r1, #608] @ 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 80006f0: 687b ldr r3, [r7, #4] 80006f2: 1e5a subs r2, r3, #1 80006f4: 607a str r2, [r7, #4] 80006f6: 2b00 cmp r3, #0 80006f8: d1ef bne.n 80006da } while(sets-- != 0U); 80006fa: 68bb ldr r3, [r7, #8] 80006fc: 1e5a subs r2, r3, #1 80006fe: 60ba str r2, [r7, #8] 8000700: 2b00 cmp r3, #0 8000702: d1e5 bne.n 80006d0 __ASM volatile ("dsb 0xF":::"memory"); 8000704: f3bf 8f4f dsb sy } 8000708: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800070a: 4b39 ldr r3, [pc, #228] @ (80007f0 ) 800070c: 695b ldr r3, [r3, #20] 800070e: 4a38 ldr r2, [pc, #224] @ (80007f0 ) 8000710: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000714: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000716: f3bf 8f4f dsb sy } 800071a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800071c: f3bf 8f6f isb sy } 8000720: e000 b.n 8000724 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000722: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000724: f005 fb2a bl 8005d7c /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000728: f000 f884 bl 8000834 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 800072c: f000 f900 bl 8000930 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000730: f000 ff88 bl 8001644 MX_DMA_Init(); 8000734: f000 ff56 bl 80015e4 MX_RNG_Init(); 8000738: f000 fc08 bl 8000f4c MX_USART1_UART_Init(); 800073c: f000 ff02 bl 8001544 MX_ADC1_Init(); 8000740: f000 f926 bl 8000990 MX_UART8_Init(); 8000744: f000 feb2 bl 80014ac MX_CRC_Init(); 8000748: f000 fb7e bl 8000e48 MX_ADC2_Init(); 800074c: f000 fa0a bl 8000b64 MX_ADC3_Init(); 8000750: f000 fa9c bl 8000c8c MX_TIM2_Init(); 8000754: f000 fcac bl 80010b0 MX_TIM1_Init(); 8000758: f000 fc0e bl 8000f78 MX_TIM3_Init(); 800075c: f000 fd26 bl 80011ac MX_DAC1_Init(); 8000760: f000 fb9c bl 8000e9c MX_COMP1_Init(); 8000764: f000 fb42 bl 8000dec MX_TIM4_Init(); 8000768: f000 fdcc bl 8001304 MX_TIM8_Init(); 800076c: f000 fe48 bl 8001400 #ifdef WATCHDOG_ENABLED MX_IWDG1_Init(); 8000770: f000 fbd0 bl 8000f14 #endif /* USER CODE BEGIN 2 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8000774: 481f ldr r0, [pc, #124] @ (80007f4 ) 8000776: f00a ff8d bl 800b694 #endif /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 800077a: f013 fc27 bl 8013fcc /* add semaphores, ... */ /* USER CODE END RTOS_SEMAPHORES */ /* Create the timer(s) */ /* creation of debugLedTimer */ debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 800077e: 4b1e ldr r3, [pc, #120] @ (80007f8 ) 8000780: 2200 movs r2, #0 8000782: 2100 movs r1, #0 8000784: 481d ldr r0, [pc, #116] @ (80007fc ) 8000786: f013 fd2f bl 80141e8 800078a: 4603 mov r3, r0 800078c: 4a1c ldr r2, [pc, #112] @ (8000800 ) 800078e: 6013 str r3, [r2, #0] /* creation of fanTimer */ fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 8000790: 4b1c ldr r3, [pc, #112] @ (8000804 ) 8000792: 2200 movs r2, #0 8000794: 2100 movs r1, #0 8000796: 481c ldr r0, [pc, #112] @ (8000808 ) 8000798: f013 fd26 bl 80141e8 800079c: 4603 mov r3, r0 800079e: 4a1b ldr r2, [pc, #108] @ (800080c ) 80007a0: 6013 str r3, [r2, #0] /* creation of motorXTimer */ motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 80007a2: 4b1b ldr r3, [pc, #108] @ (8000810 ) 80007a4: 2200 movs r2, #0 80007a6: 2101 movs r1, #1 80007a8: 481a ldr r0, [pc, #104] @ (8000814 ) 80007aa: f013 fd1d bl 80141e8 80007ae: 4603 mov r3, r0 80007b0: 4a19 ldr r2, [pc, #100] @ (8000818 ) 80007b2: 6013 str r3, [r2, #0] /* creation of motorYTimer */ motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 80007b4: 4b19 ldr r3, [pc, #100] @ (800081c ) 80007b6: 2200 movs r2, #0 80007b8: 2101 movs r1, #1 80007ba: 4819 ldr r0, [pc, #100] @ (8000820 ) 80007bc: f013 fd14 bl 80141e8 80007c0: 4603 mov r3, r0 80007c2: 4a18 ldr r2, [pc, #96] @ (8000824 ) 80007c4: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 80007c6: 4a18 ldr r2, [pc, #96] @ (8000828 ) 80007c8: 2100 movs r1, #0 80007ca: 4818 ldr r0, [pc, #96] @ (800082c ) 80007cc: f013 fc48 bl 8014060 80007d0: 4603 mov r3, r0 80007d2: 4a17 ldr r2, [pc, #92] @ (8000830 ) 80007d4: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 80007d6: 4807 ldr r0, [pc, #28] @ (80007f4 ) 80007d8: f00a ff5c bl 800b694 #endif UartTasksInit(); 80007dc: f004 f8f4 bl 80049c8 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); #else MeasTasksInit(); 80007e0: f001 fb7a bl 8001ed8 #endif PositionControlTaskInit(); 80007e4: f002 fdb2 bl 800334c /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 80007e8: f013 fc14 bl 8014014 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 80007ec: bf00 nop 80007ee: e7fd b.n 80007ec 80007f0: e000ed00 .word 0xe000ed00 80007f4: 24000418 .word 0x24000418 80007f8: 080186bc .word 0x080186bc 80007fc: 08001d15 .word 0x08001d15 8000800: 240006e4 .word 0x240006e4 8000804: 080186cc .word 0x080186cc 8000808: 08001d2d .word 0x08001d2d 800080c: 24000714 .word 0x24000714 8000810: 080186dc .word 0x080186dc 8000814: 08001d49 .word 0x08001d49 8000818: 24000744 .word 0x24000744 800081c: 080186ec .word 0x080186ec 8000820: 08001d85 .word 0x08001d85 8000824: 24000774 .word 0x24000774 8000828: 08018698 .word 0x08018698 800082c: 08001b59 .word 0x08001b59 8000830: 240006e0 .word 0x240006e0 08000834 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000834: b580 push {r7, lr} 8000836: b09c sub sp, #112 @ 0x70 8000838: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800083a: f107 0324 add.w r3, r7, #36 @ 0x24 800083e: 224c movs r2, #76 @ 0x4c 8000840: 2100 movs r1, #0 8000842: 4618 mov r0, r3 8000844: f017 fd60 bl 8018308 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000848: 1d3b adds r3, r7, #4 800084a: 2220 movs r2, #32 800084c: 2100 movs r1, #0 800084e: 4618 mov r0, r3 8000850: f017 fd5a bl 8018308 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000854: 2002 movs r0, #2 8000856: f00a ffb7 bl 800b7c8 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 800085a: 2300 movs r3, #0 800085c: 603b str r3, [r7, #0] 800085e: 4b32 ldr r3, [pc, #200] @ (8000928 ) 8000860: 6adb ldr r3, [r3, #44] @ 0x2c 8000862: 4a31 ldr r2, [pc, #196] @ (8000928 ) 8000864: f023 0301 bic.w r3, r3, #1 8000868: 62d3 str r3, [r2, #44] @ 0x2c 800086a: 4b2f ldr r3, [pc, #188] @ (8000928 ) 800086c: 6adb ldr r3, [r3, #44] @ 0x2c 800086e: f003 0301 and.w r3, r3, #1 8000872: 603b str r3, [r7, #0] 8000874: 4b2d ldr r3, [pc, #180] @ (800092c ) 8000876: 699b ldr r3, [r3, #24] 8000878: 4a2c ldr r2, [pc, #176] @ (800092c ) 800087a: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800087e: 6193 str r3, [r2, #24] 8000880: 4b2a ldr r3, [pc, #168] @ (800092c ) 8000882: 699b ldr r3, [r3, #24] 8000884: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000888: 603b str r3, [r7, #0] 800088a: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 800088c: bf00 nop 800088e: 4b27 ldr r3, [pc, #156] @ (800092c ) 8000890: 699b ldr r3, [r3, #24] 8000892: f403 5300 and.w r3, r3, #8192 @ 0x2000 8000896: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800089a: d1f8 bne.n 800088e /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI 800089c: 2329 movs r3, #41 @ 0x29 800089e: 627b str r3, [r7, #36] @ 0x24 |RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80008a0: f44f 3380 mov.w r3, #65536 @ 0x10000 80008a4: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 80008a6: 2301 movs r3, #1 80008a8: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 80008aa: 2301 movs r3, #1 80008ac: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80008ae: 2302 movs r3, #2 80008b0: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80008b2: 2302 movs r3, #2 80008b4: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 80008b6: 2305 movs r3, #5 80008b8: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 80008ba: 23a0 movs r3, #160 @ 0xa0 80008bc: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 80008be: 2302 movs r3, #2 80008c0: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 80008c2: 2302 movs r3, #2 80008c4: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 80008c6: 2302 movs r3, #2 80008c8: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 80008ca: 2308 movs r3, #8 80008cc: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 80008ce: 2300 movs r3, #0 80008d0: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 80008d2: 2300 movs r3, #0 80008d4: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80008d6: f107 0324 add.w r3, r7, #36 @ 0x24 80008da: 4618 mov r0, r3 80008dc: f00b f834 bl 800b948 80008e0: 4603 mov r3, r0 80008e2: 2b00 cmp r3, #0 80008e4: d001 beq.n 80008ea { Error_Handler(); 80008e6: f001 faf1 bl 8001ecc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80008ea: 233f movs r3, #63 @ 0x3f 80008ec: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80008ee: 2303 movs r3, #3 80008f0: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80008f2: 2300 movs r3, #0 80008f4: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 80008f6: 2308 movs r3, #8 80008f8: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 80008fa: 2340 movs r3, #64 @ 0x40 80008fc: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 80008fe: 2340 movs r3, #64 @ 0x40 8000900: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000902: f44f 6380 mov.w r3, #1024 @ 0x400 8000906: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000908: 2340 movs r3, #64 @ 0x40 800090a: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800090c: 1d3b adds r3, r7, #4 800090e: 2102 movs r1, #2 8000910: 4618 mov r0, r3 8000912: f00b fc73 bl 800c1fc 8000916: 4603 mov r3, r0 8000918: 2b00 cmp r3, #0 800091a: d001 beq.n 8000920 { Error_Handler(); 800091c: f001 fad6 bl 8001ecc } } 8000920: bf00 nop 8000922: 3770 adds r7, #112 @ 0x70 8000924: 46bd mov sp, r7 8000926: bd80 pop {r7, pc} 8000928: 58000400 .word 0x58000400 800092c: 58024800 .word 0x58024800 08000930 : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 8000930: b580 push {r7, lr} 8000932: b0b0 sub sp, #192 @ 0xc0 8000934: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000936: 463b mov r3, r7 8000938: 22c0 movs r2, #192 @ 0xc0 800093a: 2100 movs r1, #0 800093c: 4618 mov r0, r3 800093e: f017 fce3 bl 8018308 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8000942: f44f 2200 mov.w r2, #524288 @ 0x80000 8000946: f04f 0300 mov.w r3, #0 800094a: e9c7 2300 strd r2, r3, [r7] PeriphClkInitStruct.PLL2.PLL2M = 5; 800094e: 2305 movs r3, #5 8000950: 60bb str r3, [r7, #8] PeriphClkInitStruct.PLL2.PLL2N = 52; 8000952: 2334 movs r3, #52 @ 0x34 8000954: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLL2.PLL2P = 26; 8000956: 231a movs r3, #26 8000958: 613b str r3, [r7, #16] PeriphClkInitStruct.PLL2.PLL2Q = 2; 800095a: 2302 movs r3, #2 800095c: 617b str r3, [r7, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 800095e: 2302 movs r3, #2 8000960: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 8000962: 2380 movs r3, #128 @ 0x80 8000964: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 8000966: 2300 movs r3, #0 8000968: 623b str r3, [r7, #32] PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 800096a: 2300 movs r3, #0 800096c: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 800096e: 2300 movs r3, #0 8000970: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000974: 463b mov r3, r7 8000976: 4618 mov r0, r3 8000978: f00c f80e bl 800c998 800097c: 4603 mov r3, r0 800097e: 2b00 cmp r3, #0 8000980: d001 beq.n 8000986 { Error_Handler(); 8000982: f001 faa3 bl 8001ecc } } 8000986: bf00 nop 8000988: 37c0 adds r7, #192 @ 0xc0 800098a: 46bd mov sp, r7 800098c: bd80 pop {r7, pc} ... 08000990 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000990: b580 push {r7, lr} 8000992: b08a sub sp, #40 @ 0x28 8000994: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000996: f107 031c add.w r3, r7, #28 800099a: 2200 movs r2, #0 800099c: 601a str r2, [r3, #0] 800099e: 605a str r2, [r3, #4] 80009a0: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 80009a2: 463b mov r3, r7 80009a4: 2200 movs r2, #0 80009a6: 601a str r2, [r3, #0] 80009a8: 605a str r2, [r3, #4] 80009aa: 609a str r2, [r3, #8] 80009ac: 60da str r2, [r3, #12] 80009ae: 611a str r2, [r3, #16] 80009b0: 615a str r2, [r3, #20] 80009b2: 619a str r2, [r3, #24] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80009b4: 4b62 ldr r3, [pc, #392] @ (8000b40 ) 80009b6: 4a63 ldr r2, [pc, #396] @ (8000b44 ) 80009b8: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80009ba: 4b61 ldr r3, [pc, #388] @ (8000b40 ) 80009bc: 2200 movs r2, #0 80009be: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 80009c0: 4b5f ldr r3, [pc, #380] @ (8000b40 ) 80009c2: 2200 movs r2, #0 80009c4: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80009c6: 4b5e ldr r3, [pc, #376] @ (8000b40 ) 80009c8: 2201 movs r2, #1 80009ca: 60da str r2, [r3, #12] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 80009cc: 4b5c ldr r3, [pc, #368] @ (8000b40 ) 80009ce: 2208 movs r2, #8 80009d0: 611a str r2, [r3, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 80009d2: 4b5b ldr r3, [pc, #364] @ (8000b40 ) 80009d4: 2200 movs r2, #0 80009d6: 751a strb r2, [r3, #20] hadc1.Init.ContinuousConvMode = ENABLE; 80009d8: 4b59 ldr r3, [pc, #356] @ (8000b40 ) 80009da: 2201 movs r2, #1 80009dc: 755a strb r2, [r3, #21] hadc1.Init.NbrOfConversion = 7; 80009de: 4b58 ldr r3, [pc, #352] @ (8000b40 ) 80009e0: 2207 movs r2, #7 80009e2: 619a str r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 80009e4: 4b56 ldr r3, [pc, #344] @ (8000b40 ) 80009e6: 2200 movs r2, #0 80009e8: 771a strb r2, [r3, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 80009ea: 4b55 ldr r3, [pc, #340] @ (8000b40 ) 80009ec: f44f 629c mov.w r2, #1248 @ 0x4e0 80009f0: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 80009f2: 4b53 ldr r3, [pc, #332] @ (8000b40 ) 80009f4: f44f 6280 mov.w r2, #1024 @ 0x400 80009f8: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 80009fa: 4b51 ldr r3, [pc, #324] @ (8000b40 ) 80009fc: 2201 movs r2, #1 80009fe: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000a00: 4b4f ldr r3, [pc, #316] @ (8000b40 ) 8000a02: 2200 movs r2, #0 8000a04: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000a06: 4b4e ldr r3, [pc, #312] @ (8000b40 ) 8000a08: 2200 movs r2, #0 8000a0a: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 8000a0c: 4b4c ldr r3, [pc, #304] @ (8000b40 ) 8000a0e: 2200 movs r2, #0 8000a10: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000a14: 484a ldr r0, [pc, #296] @ (8000b40 ) 8000a16: f005 fc61 bl 80062dc 8000a1a: 4603 mov r3, r0 8000a1c: 2b00 cmp r3, #0 8000a1e: d001 beq.n 8000a24 { Error_Handler(); 8000a20: f001 fa54 bl 8001ecc } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8000a24: 2300 movs r3, #0 8000a26: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000a28: f107 031c add.w r3, r7, #28 8000a2c: 4619 mov r1, r3 8000a2e: 4844 ldr r0, [pc, #272] @ (8000b40 ) 8000a30: f006 fd72 bl 8007518 8000a34: 4603 mov r3, r0 8000a36: 2b00 cmp r3, #0 8000a38: d001 beq.n 8000a3e { Error_Handler(); 8000a3a: f001 fa47 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000a3e: 4b42 ldr r3, [pc, #264] @ (8000b48 ) 8000a40: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000a42: 2306 movs r3, #6 8000a44: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000a46: 2306 movs r3, #6 8000a48: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000a4a: f240 73ff movw r3, #2047 @ 0x7ff 8000a4e: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000a50: 2304 movs r3, #4 8000a52: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000a54: 2300 movs r3, #0 8000a56: 617b str r3, [r7, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000a58: 2300 movs r3, #0 8000a5a: 767b strb r3, [r7, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a5c: 463b mov r3, r7 8000a5e: 4619 mov r1, r3 8000a60: 4837 ldr r0, [pc, #220] @ (8000b40 ) 8000a62: f005 feb5 bl 80067d0 8000a66: 4603 mov r3, r0 8000a68: 2b00 cmp r3, #0 8000a6a: d001 beq.n 8000a70 { Error_Handler(); 8000a6c: f001 fa2e bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 8000a70: 4b36 ldr r3, [pc, #216] @ (8000b4c ) 8000a72: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 8000a74: 230c movs r3, #12 8000a76: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a78: 463b mov r3, r7 8000a7a: 4619 mov r1, r3 8000a7c: 4830 ldr r0, [pc, #192] @ (8000b40 ) 8000a7e: f005 fea7 bl 80067d0 8000a82: 4603 mov r3, r0 8000a84: 2b00 cmp r3, #0 8000a86: d001 beq.n 8000a8c { Error_Handler(); 8000a88: f001 fa20 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8000a8c: 4b30 ldr r3, [pc, #192] @ (8000b50 ) 8000a8e: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8000a90: 2312 movs r3, #18 8000a92: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a94: 463b mov r3, r7 8000a96: 4619 mov r1, r3 8000a98: 4829 ldr r0, [pc, #164] @ (8000b40 ) 8000a9a: f005 fe99 bl 80067d0 8000a9e: 4603 mov r3, r0 8000aa0: 2b00 cmp r3, #0 8000aa2: d001 beq.n 8000aa8 { Error_Handler(); 8000aa4: f001 fa12 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; 8000aa8: 4b2a ldr r3, [pc, #168] @ (8000b54 ) 8000aaa: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 8000aac: 2318 movs r3, #24 8000aae: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ab0: 463b mov r3, r7 8000ab2: 4619 mov r1, r3 8000ab4: 4822 ldr r0, [pc, #136] @ (8000b40 ) 8000ab6: f005 fe8b bl 80067d0 8000aba: 4603 mov r3, r0 8000abc: 2b00 cmp r3, #0 8000abe: d001 beq.n 8000ac4 { Error_Handler(); 8000ac0: f001 fa04 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_17; 8000ac4: 4b24 ldr r3, [pc, #144] @ (8000b58 ) 8000ac6: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 8000ac8: f44f 7380 mov.w r3, #256 @ 0x100 8000acc: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ace: 463b mov r3, r7 8000ad0: 4619 mov r1, r3 8000ad2: 481b ldr r0, [pc, #108] @ (8000b40 ) 8000ad4: f005 fe7c bl 80067d0 8000ad8: 4603 mov r3, r0 8000ada: 2b00 cmp r3, #0 8000adc: d001 beq.n 8000ae2 { Error_Handler(); 8000ade: f001 f9f5 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; 8000ae2: 4b1e ldr r3, [pc, #120] @ (8000b5c ) 8000ae4: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8000ae6: f44f 7383 mov.w r3, #262 @ 0x106 8000aea: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000aec: 463b mov r3, r7 8000aee: 4619 mov r1, r3 8000af0: 4813 ldr r0, [pc, #76] @ (8000b40 ) 8000af2: f005 fe6d bl 80067d0 8000af6: 4603 mov r3, r0 8000af8: 2b00 cmp r3, #0 8000afa: d001 beq.n 8000b00 { Error_Handler(); 8000afc: f001 f9e6 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000b00: 4b17 ldr r3, [pc, #92] @ (8000b60 ) 8000b02: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_7; 8000b04: f44f 7386 mov.w r3, #268 @ 0x10c 8000b08: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b0a: 463b mov r3, r7 8000b0c: 4619 mov r1, r3 8000b0e: 480c ldr r0, [pc, #48] @ (8000b40 ) 8000b10: f005 fe5e bl 80067d0 8000b14: 4603 mov r3, r0 8000b16: 2b00 cmp r3, #0 8000b18: d001 beq.n 8000b1e { Error_Handler(); 8000b1a: f001 f9d7 bl 8001ecc } /* USER CODE BEGIN ADC1_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000b1e: f240 72ff movw r2, #2047 @ 0x7ff 8000b22: f04f 1101 mov.w r1, #65537 @ 0x10001 8000b26: 4806 ldr r0, [pc, #24] @ (8000b40 ) 8000b28: f006 fc92 bl 8007450 8000b2c: 4603 mov r3, r0 8000b2e: 2b00 cmp r3, #0 8000b30: d001 beq.n 8000b36 { Error_Handler(); 8000b32: f001 f9cb bl 8001ecc } /* USER CODE END ADC1_Init 2 */ } 8000b36: bf00 nop 8000b38: 3728 adds r7, #40 @ 0x28 8000b3a: 46bd mov sp, r7 8000b3c: bd80 pop {r7, pc} 8000b3e: bf00 nop 8000b40: 24000120 .word 0x24000120 8000b44: 40022000 .word 0x40022000 8000b48: 21800100 .word 0x21800100 8000b4c: 1d500080 .word 0x1d500080 8000b50: 25b00200 .word 0x25b00200 8000b54: 43210000 .word 0x43210000 8000b58: 47520000 .word 0x47520000 8000b5c: 3ac04000 .word 0x3ac04000 8000b60: 3ef08000 .word 0x3ef08000 08000b64 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8000b64: b580 push {r7, lr} 8000b66: b088 sub sp, #32 8000b68: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000b6a: 1d3b adds r3, r7, #4 8000b6c: 2200 movs r2, #0 8000b6e: 601a str r2, [r3, #0] 8000b70: 605a str r2, [r3, #4] 8000b72: 609a str r2, [r3, #8] 8000b74: 60da str r2, [r3, #12] 8000b76: 611a str r2, [r3, #16] 8000b78: 615a str r2, [r3, #20] 8000b7a: 619a str r2, [r3, #24] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000b7c: 4b3e ldr r3, [pc, #248] @ (8000c78 ) 8000b7e: 4a3f ldr r2, [pc, #252] @ (8000c7c ) 8000b80: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000b82: 4b3d ldr r3, [pc, #244] @ (8000c78 ) 8000b84: 2200 movs r2, #0 8000b86: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_16B; 8000b88: 4b3b ldr r3, [pc, #236] @ (8000c78 ) 8000b8a: 2200 movs r2, #0 8000b8c: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000b8e: 4b3a ldr r3, [pc, #232] @ (8000c78 ) 8000b90: 2201 movs r2, #1 8000b92: 60da str r2, [r3, #12] hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000b94: 4b38 ldr r3, [pc, #224] @ (8000c78 ) 8000b96: 2208 movs r2, #8 8000b98: 611a str r2, [r3, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000b9a: 4b37 ldr r3, [pc, #220] @ (8000c78 ) 8000b9c: 2200 movs r2, #0 8000b9e: 751a strb r2, [r3, #20] hadc2.Init.ContinuousConvMode = ENABLE; 8000ba0: 4b35 ldr r3, [pc, #212] @ (8000c78 ) 8000ba2: 2201 movs r2, #1 8000ba4: 755a strb r2, [r3, #21] hadc2.Init.NbrOfConversion = 3; 8000ba6: 4b34 ldr r3, [pc, #208] @ (8000c78 ) 8000ba8: 2203 movs r2, #3 8000baa: 619a str r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000bac: 4b32 ldr r3, [pc, #200] @ (8000c78 ) 8000bae: 2200 movs r2, #0 8000bb0: 771a strb r2, [r3, #28] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000bb2: 4b31 ldr r3, [pc, #196] @ (8000c78 ) 8000bb4: f44f 629c mov.w r2, #1248 @ 0x4e0 8000bb8: 625a str r2, [r3, #36] @ 0x24 hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000bba: 4b2f ldr r3, [pc, #188] @ (8000c78 ) 8000bbc: f44f 6280 mov.w r2, #1024 @ 0x400 8000bc0: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000bc2: 4b2d ldr r3, [pc, #180] @ (8000c78 ) 8000bc4: 2201 movs r2, #1 8000bc6: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000bc8: 4b2b ldr r3, [pc, #172] @ (8000c78 ) 8000bca: 2200 movs r2, #0 8000bcc: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000bce: 4b2a ldr r3, [pc, #168] @ (8000c78 ) 8000bd0: 2200 movs r2, #0 8000bd2: 635a str r2, [r3, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000bd4: 4b28 ldr r3, [pc, #160] @ (8000c78 ) 8000bd6: 2200 movs r2, #0 8000bd8: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000bdc: 4826 ldr r0, [pc, #152] @ (8000c78 ) 8000bde: f005 fb7d bl 80062dc 8000be2: 4603 mov r3, r0 8000be4: 2b00 cmp r3, #0 8000be6: d001 beq.n 8000bec { Error_Handler(); 8000be8: f001 f970 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000bec: 4b24 ldr r3, [pc, #144] @ (8000c80 ) 8000bee: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000bf0: 2306 movs r3, #6 8000bf2: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000bf4: 2306 movs r3, #6 8000bf6: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000bf8: f240 73ff movw r3, #2047 @ 0x7ff 8000bfc: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000bfe: 2304 movs r3, #4 8000c00: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000c02: 2300 movs r3, #0 8000c04: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000c06: 2300 movs r3, #0 8000c08: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c0a: 1d3b adds r3, r7, #4 8000c0c: 4619 mov r1, r3 8000c0e: 481a ldr r0, [pc, #104] @ (8000c78 ) 8000c10: f005 fdde bl 80067d0 8000c14: 4603 mov r3, r0 8000c16: 2b00 cmp r3, #0 8000c18: d001 beq.n 8000c1e { Error_Handler(); 8000c1a: f001 f957 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000c1e: 4b19 ldr r3, [pc, #100] @ (8000c84 ) 8000c20: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000c22: 230c movs r3, #12 8000c24: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c26: 1d3b adds r3, r7, #4 8000c28: 4619 mov r1, r3 8000c2a: 4813 ldr r0, [pc, #76] @ (8000c78 ) 8000c2c: f005 fdd0 bl 80067d0 8000c30: 4603 mov r3, r0 8000c32: 2b00 cmp r3, #0 8000c34: d001 beq.n 8000c3a { Error_Handler(); 8000c36: f001 f949 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000c3a: 4b13 ldr r3, [pc, #76] @ (8000c88 ) 8000c3c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000c3e: 2312 movs r3, #18 8000c40: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c42: 1d3b adds r3, r7, #4 8000c44: 4619 mov r1, r3 8000c46: 480c ldr r0, [pc, #48] @ (8000c78 ) 8000c48: f005 fdc2 bl 80067d0 8000c4c: 4603 mov r3, r0 8000c4e: 2b00 cmp r3, #0 8000c50: d001 beq.n 8000c56 { Error_Handler(); 8000c52: f001 f93b bl 8001ecc } /* USER CODE BEGIN ADC2_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000c56: f240 72ff movw r2, #2047 @ 0x7ff 8000c5a: f04f 1101 mov.w r1, #65537 @ 0x10001 8000c5e: 4806 ldr r0, [pc, #24] @ (8000c78 ) 8000c60: f006 fbf6 bl 8007450 8000c64: 4603 mov r3, r0 8000c66: 2b00 cmp r3, #0 8000c68: d001 beq.n 8000c6e { Error_Handler(); 8000c6a: f001 f92f bl 8001ecc } /* USER CODE END ADC2_Init 2 */ } 8000c6e: bf00 nop 8000c70: 3720 adds r7, #32 8000c72: 46bd mov sp, r7 8000c74: bd80 pop {r7, pc} 8000c76: bf00 nop 8000c78: 24000184 .word 0x24000184 8000c7c: 40022100 .word 0x40022100 8000c80: 0c900008 .word 0x0c900008 8000c84: 10c00010 .word 0x10c00010 8000c88: 14f00020 .word 0x14f00020 08000c8c : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 8000c8c: b580 push {r7, lr} 8000c8e: b088 sub sp, #32 8000c90: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000c92: 1d3b adds r3, r7, #4 8000c94: 2200 movs r2, #0 8000c96: 601a str r2, [r3, #0] 8000c98: 605a str r2, [r3, #4] 8000c9a: 609a str r2, [r3, #8] 8000c9c: 60da str r2, [r3, #12] 8000c9e: 611a str r2, [r3, #16] 8000ca0: 615a str r2, [r3, #20] 8000ca2: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 8000ca4: 4b4b ldr r3, [pc, #300] @ (8000dd4 ) 8000ca6: 4a4c ldr r2, [pc, #304] @ (8000dd8 ) 8000ca8: 601a str r2, [r3, #0] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000caa: 4b4a ldr r3, [pc, #296] @ (8000dd4 ) 8000cac: 2200 movs r2, #0 8000cae: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000cb0: 4b48 ldr r3, [pc, #288] @ (8000dd4 ) 8000cb2: 2201 movs r2, #1 8000cb4: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000cb6: 4b47 ldr r3, [pc, #284] @ (8000dd4 ) 8000cb8: 2208 movs r2, #8 8000cba: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000cbc: 4b45 ldr r3, [pc, #276] @ (8000dd4 ) 8000cbe: 2200 movs r2, #0 8000cc0: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = ENABLE; 8000cc2: 4b44 ldr r3, [pc, #272] @ (8000dd4 ) 8000cc4: 2201 movs r2, #1 8000cc6: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 5; 8000cc8: 4b42 ldr r3, [pc, #264] @ (8000dd4 ) 8000cca: 2205 movs r2, #5 8000ccc: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000cce: 4b41 ldr r3, [pc, #260] @ (8000dd4 ) 8000cd0: 2200 movs r2, #0 8000cd2: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000cd4: 4b3f ldr r3, [pc, #252] @ (8000dd4 ) 8000cd6: f44f 629c mov.w r2, #1248 @ 0x4e0 8000cda: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000cdc: 4b3d ldr r3, [pc, #244] @ (8000dd4 ) 8000cde: f44f 6280 mov.w r2, #1024 @ 0x400 8000ce2: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000ce4: 4b3b ldr r3, [pc, #236] @ (8000dd4 ) 8000ce6: 2201 movs r2, #1 8000ce8: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000cea: 4b3a ldr r3, [pc, #232] @ (8000dd4 ) 8000cec: 2200 movs r2, #0 8000cee: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000cf0: 4b38 ldr r3, [pc, #224] @ (8000dd4 ) 8000cf2: 2200 movs r2, #0 8000cf4: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000cf6: 4b37 ldr r3, [pc, #220] @ (8000dd4 ) 8000cf8: 2200 movs r2, #0 8000cfa: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000cfe: 4835 ldr r0, [pc, #212] @ (8000dd4 ) 8000d00: f005 faec bl 80062dc 8000d04: 4603 mov r3, r0 8000d06: 2b00 cmp r3, #0 8000d08: d001 beq.n 8000d0e { Error_Handler(); 8000d0a: f001 f8df bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8000d0e: 2301 movs r3, #1 8000d10: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000d12: 2306 movs r3, #6 8000d14: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000d16: 2306 movs r3, #6 8000d18: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000d1a: f240 73ff movw r3, #2047 @ 0x7ff 8000d1e: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000d20: 2304 movs r3, #4 8000d22: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000d24: 2300 movs r3, #0 8000d26: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000d28: 2300 movs r3, #0 8000d2a: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d2c: 1d3b adds r3, r7, #4 8000d2e: 4619 mov r1, r3 8000d30: 4828 ldr r0, [pc, #160] @ (8000dd4 ) 8000d32: f005 fd4d bl 80067d0 8000d36: 4603 mov r3, r0 8000d38: 2b00 cmp r3, #0 8000d3a: d001 beq.n 8000d40 { Error_Handler(); 8000d3c: f001 f8c6 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000d40: 4b26 ldr r3, [pc, #152] @ (8000ddc ) 8000d42: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000d44: 230c movs r3, #12 8000d46: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d48: 1d3b adds r3, r7, #4 8000d4a: 4619 mov r1, r3 8000d4c: 4821 ldr r0, [pc, #132] @ (8000dd4 ) 8000d4e: f005 fd3f bl 80067d0 8000d52: 4603 mov r3, r0 8000d54: 2b00 cmp r3, #0 8000d56: d001 beq.n 8000d5c { Error_Handler(); 8000d58: f001 f8b8 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_10; 8000d5c: 4b20 ldr r3, [pc, #128] @ (8000de0 ) 8000d5e: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000d60: 2312 movs r3, #18 8000d62: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d64: 1d3b adds r3, r7, #4 8000d66: 4619 mov r1, r3 8000d68: 481a ldr r0, [pc, #104] @ (8000dd4 ) 8000d6a: f005 fd31 bl 80067d0 8000d6e: 4603 mov r3, r0 8000d70: 2b00 cmp r3, #0 8000d72: d001 beq.n 8000d78 { Error_Handler(); 8000d74: f001 f8aa bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; 8000d78: 4b1a ldr r3, [pc, #104] @ (8000de4 ) 8000d7a: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8000d7c: 2318 movs r3, #24 8000d7e: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d80: 1d3b adds r3, r7, #4 8000d82: 4619 mov r1, r3 8000d84: 4813 ldr r0, [pc, #76] @ (8000dd4 ) 8000d86: f005 fd23 bl 80067d0 8000d8a: 4603 mov r3, r0 8000d8c: 2b00 cmp r3, #0 8000d8e: d001 beq.n 8000d94 { Error_Handler(); 8000d90: f001 f89c bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000d94: 4b14 ldr r3, [pc, #80] @ (8000de8 ) 8000d96: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 8000d98: f44f 7380 mov.w r3, #256 @ 0x100 8000d9c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d9e: 1d3b adds r3, r7, #4 8000da0: 4619 mov r1, r3 8000da2: 480c ldr r0, [pc, #48] @ (8000dd4 ) 8000da4: f005 fd14 bl 80067d0 8000da8: 4603 mov r3, r0 8000daa: 2b00 cmp r3, #0 8000dac: d001 beq.n 8000db2 { Error_Handler(); 8000dae: f001 f88d bl 8001ecc } /* USER CODE BEGIN ADC3_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000db2: f240 72ff movw r2, #2047 @ 0x7ff 8000db6: f04f 1101 mov.w r1, #65537 @ 0x10001 8000dba: 4806 ldr r0, [pc, #24] @ (8000dd4 ) 8000dbc: f006 fb48 bl 8007450 8000dc0: 4603 mov r3, r0 8000dc2: 2b00 cmp r3, #0 8000dc4: d001 beq.n 8000dca { Error_Handler(); 8000dc6: f001 f881 bl 8001ecc } /* USER CODE END ADC3_Init 2 */ } 8000dca: bf00 nop 8000dcc: 3720 adds r7, #32 8000dce: 46bd mov sp, r7 8000dd0: bd80 pop {r7, pc} 8000dd2: bf00 nop 8000dd4: 240001e8 .word 0x240001e8 8000dd8: 58026000 .word 0x58026000 8000ddc: 04300002 .word 0x04300002 8000de0: 2a000400 .word 0x2a000400 8000de4: 2e300800 .word 0x2e300800 8000de8: cfb80000 .word 0xcfb80000 08000dec : * @brief COMP1 Initialization Function * @param None * @retval None */ static void MX_COMP1_Init(void) { 8000dec: b580 push {r7, lr} 8000dee: af00 add r7, sp, #0 /* USER CODE END COMP1_Init 0 */ /* USER CODE BEGIN COMP1_Init 1 */ /* USER CODE END COMP1_Init 1 */ hcomp1.Instance = COMP1; 8000df0: 4b12 ldr r3, [pc, #72] @ (8000e3c ) 8000df2: 4a13 ldr r2, [pc, #76] @ (8000e40 ) 8000df4: 601a str r2, [r3, #0] hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT; 8000df6: 4b11 ldr r3, [pc, #68] @ (8000e3c ) 8000df8: 4a12 ldr r2, [pc, #72] @ (8000e44 ) 8000dfa: 611a str r2, [r3, #16] hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 8000dfc: 4b0f ldr r3, [pc, #60] @ (8000e3c ) 8000dfe: f44f 1280 mov.w r2, #1048576 @ 0x100000 8000e02: 60da str r2, [r3, #12] hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 8000e04: 4b0d ldr r3, [pc, #52] @ (8000e3c ) 8000e06: 2200 movs r2, #0 8000e08: 619a str r2, [r3, #24] hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE; 8000e0a: 4b0c ldr r3, [pc, #48] @ (8000e3c ) 8000e0c: 2200 movs r2, #0 8000e0e: 615a str r2, [r3, #20] hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 8000e10: 4b0a ldr r3, [pc, #40] @ (8000e3c ) 8000e12: 2200 movs r2, #0 8000e14: 61da str r2, [r3, #28] hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED; 8000e16: 4b09 ldr r3, [pc, #36] @ (8000e3c ) 8000e18: 2200 movs r2, #0 8000e1a: 609a str r2, [r3, #8] hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; 8000e1c: 4b07 ldr r3, [pc, #28] @ (8000e3c ) 8000e1e: 2200 movs r2, #0 8000e20: 605a str r2, [r3, #4] hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 8000e22: 4b06 ldr r3, [pc, #24] @ (8000e3c ) 8000e24: 2200 movs r2, #0 8000e26: 621a str r2, [r3, #32] if (HAL_COMP_Init(&hcomp1) != HAL_OK) 8000e28: 4804 ldr r0, [pc, #16] @ (8000e3c ) 8000e2a: f006 fc53 bl 80076d4 8000e2e: 4603 mov r3, r0 8000e30: 2b00 cmp r3, #0 8000e32: d001 beq.n 8000e38 { Error_Handler(); 8000e34: f001 f84a bl 8001ecc } /* USER CODE BEGIN COMP1_Init 2 */ /* USER CODE END COMP1_Init 2 */ } 8000e38: bf00 nop 8000e3a: bd80 pop {r7, pc} 8000e3c: 240003b4 .word 0x240003b4 8000e40: 5800380c .word 0x5800380c 8000e44: 00020006 .word 0x00020006 08000e48 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000e48: b580 push {r7, lr} 8000e4a: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000e4c: 4b11 ldr r3, [pc, #68] @ (8000e94 ) 8000e4e: 4a12 ldr r2, [pc, #72] @ (8000e98 ) 8000e50: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000e52: 4b10 ldr r3, [pc, #64] @ (8000e94 ) 8000e54: 2201 movs r2, #1 8000e56: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 8000e58: 4b0e ldr r3, [pc, #56] @ (8000e94 ) 8000e5a: 2200 movs r2, #0 8000e5c: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 8000e5e: 4b0d ldr r3, [pc, #52] @ (8000e94 ) 8000e60: f241 0221 movw r2, #4129 @ 0x1021 8000e64: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000e66: 4b0b ldr r3, [pc, #44] @ (8000e94 ) 8000e68: 2208 movs r2, #8 8000e6a: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000e6c: 4b09 ldr r3, [pc, #36] @ (8000e94 ) 8000e6e: 2200 movs r2, #0 8000e70: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000e72: 4b08 ldr r3, [pc, #32] @ (8000e94 ) 8000e74: 2200 movs r2, #0 8000e76: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000e78: 4b06 ldr r3, [pc, #24] @ (8000e94 ) 8000e7a: 2201 movs r2, #1 8000e7c: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000e7e: 4805 ldr r0, [pc, #20] @ (8000e94 ) 8000e80: f006 ff12 bl 8007ca8 8000e84: 4603 mov r3, r0 8000e86: 2b00 cmp r3, #0 8000e88: d001 beq.n 8000e8e { Error_Handler(); 8000e8a: f001 f81f bl 8001ecc } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 8000e8e: bf00 nop 8000e90: bd80 pop {r7, pc} 8000e92: bf00 nop 8000e94: 240003e0 .word 0x240003e0 8000e98: 58024c00 .word 0x58024c00 08000e9c : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8000e9c: b580 push {r7, lr} 8000e9e: b08a sub sp, #40 @ 0x28 8000ea0: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000ea2: 1d3b adds r3, r7, #4 8000ea4: 2224 movs r2, #36 @ 0x24 8000ea6: 2100 movs r1, #0 8000ea8: 4618 mov r0, r3 8000eaa: f017 fa2d bl 8018308 /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8000eae: 4b17 ldr r3, [pc, #92] @ (8000f0c ) 8000eb0: 4a17 ldr r2, [pc, #92] @ (8000f10 ) 8000eb2: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8000eb4: 4815 ldr r0, [pc, #84] @ (8000f0c ) 8000eb6: f007 f8fd bl 80080b4 8000eba: 4603 mov r3, r0 8000ebc: 2b00 cmp r3, #0 8000ebe: d001 beq.n 8000ec4 { Error_Handler(); 8000ec0: f001 f804 bl 8001ecc } /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000ec4: 2300 movs r3, #0 8000ec6: 607b str r3, [r7, #4] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8000ec8: 2300 movs r3, #0 8000eca: 60bb str r3, [r7, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8000ecc: 2300 movs r3, #0 8000ece: 60fb str r3, [r7, #12] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8000ed0: 2301 movs r3, #1 8000ed2: 613b str r3, [r7, #16] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 8000ed4: 2300 movs r3, #0 8000ed6: 617b str r3, [r7, #20] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000ed8: 1d3b adds r3, r7, #4 8000eda: 2200 movs r2, #0 8000edc: 4619 mov r1, r3 8000ede: 480b ldr r0, [pc, #44] @ (8000f0c ) 8000ee0: f007 f9ec bl 80082bc 8000ee4: 4603 mov r3, r0 8000ee6: 2b00 cmp r3, #0 8000ee8: d001 beq.n 8000eee { Error_Handler(); 8000eea: f000 ffef bl 8001ecc } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8000eee: 1d3b adds r3, r7, #4 8000ef0: 2210 movs r2, #16 8000ef2: 4619 mov r1, r3 8000ef4: 4805 ldr r0, [pc, #20] @ (8000f0c ) 8000ef6: f007 f9e1 bl 80082bc 8000efa: 4603 mov r3, r0 8000efc: 2b00 cmp r3, #0 8000efe: d001 beq.n 8000f04 { Error_Handler(); 8000f00: f000 ffe4 bl 8001ecc } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8000f04: bf00 nop 8000f06: 3728 adds r7, #40 @ 0x28 8000f08: 46bd mov sp, r7 8000f0a: bd80 pop {r7, pc} 8000f0c: 24000404 .word 0x24000404 8000f10: 40007400 .word 0x40007400 08000f14 : * @brief IWDG1 Initialization Function * @param None * @retval None */ static void MX_IWDG1_Init(void) { 8000f14: b580 push {r7, lr} 8000f16: af00 add r7, sp, #0 /* USER CODE END IWDG1_Init 0 */ /* USER CODE BEGIN IWDG1_Init 1 */ /* USER CODE END IWDG1_Init 1 */ hiwdg1.Instance = IWDG1; 8000f18: 4b0a ldr r3, [pc, #40] @ (8000f44 ) 8000f1a: 4a0b ldr r2, [pc, #44] @ (8000f48 ) 8000f1c: 601a str r2, [r3, #0] hiwdg1.Init.Prescaler = IWDG_PRESCALER_64; 8000f1e: 4b09 ldr r3, [pc, #36] @ (8000f44 ) 8000f20: 2204 movs r2, #4 8000f22: 605a str r2, [r3, #4] hiwdg1.Init.Window = 249; 8000f24: 4b07 ldr r3, [pc, #28] @ (8000f44 ) 8000f26: 22f9 movs r2, #249 @ 0xf9 8000f28: 60da str r2, [r3, #12] hiwdg1.Init.Reload = 249; 8000f2a: 4b06 ldr r3, [pc, #24] @ (8000f44 ) 8000f2c: 22f9 movs r2, #249 @ 0xf9 8000f2e: 609a str r2, [r3, #8] if (HAL_IWDG_Init(&hiwdg1) != HAL_OK) 8000f30: 4804 ldr r0, [pc, #16] @ (8000f44 ) 8000f32: f00a fb60 bl 800b5f6 8000f36: 4603 mov r3, r0 8000f38: 2b00 cmp r3, #0 8000f3a: d001 beq.n 8000f40 { Error_Handler(); 8000f3c: f000 ffc6 bl 8001ecc } /* USER CODE BEGIN IWDG1_Init 2 */ /* USER CODE END IWDG1_Init 2 */ } 8000f40: bf00 nop 8000f42: bd80 pop {r7, pc} 8000f44: 24000418 .word 0x24000418 8000f48: 58004800 .word 0x58004800 08000f4c : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 8000f4c: b580 push {r7, lr} 8000f4e: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8000f50: 4b07 ldr r3, [pc, #28] @ (8000f70 ) 8000f52: 4a08 ldr r2, [pc, #32] @ (8000f74 ) 8000f54: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 8000f56: 4b06 ldr r3, [pc, #24] @ (8000f70 ) 8000f58: 2200 movs r2, #0 8000f5a: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000f5c: 4804 ldr r0, [pc, #16] @ (8000f70 ) 8000f5e: f00e f9fd bl 800f35c 8000f62: 4603 mov r3, r0 8000f64: 2b00 cmp r3, #0 8000f66: d001 beq.n 8000f6c { Error_Handler(); 8000f68: f000 ffb0 bl 8001ecc } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000f6c: bf00 nop 8000f6e: bd80 pop {r7, pc} 8000f70: 24000428 .word 0x24000428 8000f74: 48021800 .word 0x48021800 08000f78 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000f78: b5b0 push {r4, r5, r7, lr} 8000f7a: b096 sub sp, #88 @ 0x58 8000f7c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000f7e: f107 034c add.w r3, r7, #76 @ 0x4c 8000f82: 2200 movs r2, #0 8000f84: 601a str r2, [r3, #0] 8000f86: 605a str r2, [r3, #4] 8000f88: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8000f8a: f107 0330 add.w r3, r7, #48 @ 0x30 8000f8e: 2200 movs r2, #0 8000f90: 601a str r2, [r3, #0] 8000f92: 605a str r2, [r3, #4] 8000f94: 609a str r2, [r3, #8] 8000f96: 60da str r2, [r3, #12] 8000f98: 611a str r2, [r3, #16] 8000f9a: 615a str r2, [r3, #20] 8000f9c: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000f9e: 1d3b adds r3, r7, #4 8000fa0: 222c movs r2, #44 @ 0x2c 8000fa2: 2100 movs r1, #0 8000fa4: 4618 mov r0, r3 8000fa6: f017 f9af bl 8018308 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000faa: 4b3e ldr r3, [pc, #248] @ (80010a4 ) 8000fac: 4a3e ldr r2, [pc, #248] @ (80010a8 ) 8000fae: 601a str r2, [r3, #0] htim1.Init.Prescaler = 199; 8000fb0: 4b3c ldr r3, [pc, #240] @ (80010a4 ) 8000fb2: 22c7 movs r2, #199 @ 0xc7 8000fb4: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000fb6: 4b3b ldr r3, [pc, #236] @ (80010a4 ) 8000fb8: 2200 movs r2, #0 8000fba: 609a str r2, [r3, #8] htim1.Init.Period = 999; 8000fbc: 4b39 ldr r3, [pc, #228] @ (80010a4 ) 8000fbe: f240 32e7 movw r2, #999 @ 0x3e7 8000fc2: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000fc4: 4b37 ldr r3, [pc, #220] @ (80010a4 ) 8000fc6: 2200 movs r2, #0 8000fc8: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8000fca: 4b36 ldr r3, [pc, #216] @ (80010a4 ) 8000fcc: 2200 movs r2, #0 8000fce: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000fd0: 4b34 ldr r3, [pc, #208] @ (80010a4 ) 8000fd2: 2280 movs r2, #128 @ 0x80 8000fd4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8000fd6: 4833 ldr r0, [pc, #204] @ (80010a4 ) 8000fd8: f00e fb62 bl 800f6a0 8000fdc: 4603 mov r3, r0 8000fde: 2b00 cmp r3, #0 8000fe0: d001 beq.n 8000fe6 { Error_Handler(); 8000fe2: f000 ff73 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000fe6: 2300 movs r3, #0 8000fe8: 64fb str r3, [r7, #76] @ 0x4c sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000fea: 2300 movs r3, #0 8000fec: 653b str r3, [r7, #80] @ 0x50 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000fee: 2300 movs r3, #0 8000ff0: 657b str r3, [r7, #84] @ 0x54 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000ff2: f107 034c add.w r3, r7, #76 @ 0x4c 8000ff6: 4619 mov r1, r3 8000ff8: 482a ldr r0, [pc, #168] @ (80010a4 ) 8000ffa: f010 f8b5 bl 8011168 8000ffe: 4603 mov r3, r0 8001000: 2b00 cmp r3, #0 8001002: d001 beq.n 8001008 { Error_Handler(); 8001004: f000 ff62 bl 8001ecc } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001008: 2360 movs r3, #96 @ 0x60 800100a: 633b str r3, [r7, #48] @ 0x30 sConfigOC.Pulse = 99; 800100c: 2363 movs r3, #99 @ 0x63 800100e: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001010: 2300 movs r3, #0 8001012: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8001014: 2300 movs r3, #0 8001016: 63fb str r3, [r7, #60] @ 0x3c sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001018: 2300 movs r3, #0 800101a: 643b str r3, [r7, #64] @ 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 800101c: 2300 movs r3, #0 800101e: 647b str r3, [r7, #68] @ 0x44 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8001020: 2300 movs r3, #0 8001022: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001024: f107 0330 add.w r3, r7, #48 @ 0x30 8001028: 2204 movs r2, #4 800102a: 4619 mov r1, r3 800102c: 481d ldr r0, [pc, #116] @ (80010a4 ) 800102e: f00f f889 bl 8010144 8001032: 4603 mov r3, r0 8001034: 2b00 cmp r3, #0 8001036: d001 beq.n 800103c { Error_Handler(); 8001038: f000 ff48 bl 8001ecc } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 800103c: 2300 movs r3, #0 800103e: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8001040: 2300 movs r3, #0 8001042: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 8001044: 2300 movs r3, #0 8001046: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 8001048: 2300 movs r3, #0 800104a: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 800104c: 2300 movs r3, #0 800104e: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8001050: f44f 5300 mov.w r3, #8192 @ 0x2000 8001054: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.BreakFilter = 0; 8001056: 2300 movs r3, #0 8001058: 61fb str r3, [r7, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 800105a: 2300 movs r3, #0 800105c: 623b str r3, [r7, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800105e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8001062: 627b str r3, [r7, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 8001064: 2300 movs r3, #0 8001066: 62bb str r3, [r7, #40] @ 0x28 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 8001068: 2300 movs r3, #0 800106a: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 800106c: 1d3b adds r3, r7, #4 800106e: 4619 mov r1, r3 8001070: 480c ldr r0, [pc, #48] @ (80010a4 ) 8001072: f010 f907 bl 8011284 8001076: 4603 mov r3, r0 8001078: 2b00 cmp r3, #0 800107a: d001 beq.n 8001080 { Error_Handler(); 800107c: f000 ff26 bl 8001ecc } /* USER CODE BEGIN TIM1_Init 2 */ memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001080: 4b0a ldr r3, [pc, #40] @ (80010ac ) 8001082: 461d mov r5, r3 8001084: f107 0430 add.w r4, r7, #48 @ 0x30 8001088: cc0f ldmia r4!, {r0, r1, r2, r3} 800108a: c50f stmia r5!, {r0, r1, r2, r3} 800108c: e894 0007 ldmia.w r4, {r0, r1, r2} 8001090: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 8001094: 4803 ldr r0, [pc, #12] @ (80010a4 ) 8001096: f003 f9c1 bl 800441c } 800109a: bf00 nop 800109c: 3758 adds r7, #88 @ 0x58 800109e: 46bd mov sp, r7 80010a0: bdb0 pop {r4, r5, r7, pc} 80010a2: bf00 nop 80010a4: 2400043c .word 0x2400043c 80010a8: 40010000 .word 0x40010000 80010ac: 240007a4 .word 0x240007a4 080010b0 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80010b0: b580 push {r7, lr} 80010b2: b08c sub sp, #48 @ 0x30 80010b4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80010b6: f107 0320 add.w r3, r7, #32 80010ba: 2200 movs r2, #0 80010bc: 601a str r2, [r3, #0] 80010be: 605a str r2, [r3, #4] 80010c0: 609a str r2, [r3, #8] 80010c2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010c4: f107 0314 add.w r3, r7, #20 80010c8: 2200 movs r2, #0 80010ca: 601a str r2, [r3, #0] 80010cc: 605a str r2, [r3, #4] 80010ce: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 80010d0: 1d3b adds r3, r7, #4 80010d2: 2200 movs r2, #0 80010d4: 601a str r2, [r3, #0] 80010d6: 605a str r2, [r3, #4] 80010d8: 609a str r2, [r3, #8] 80010da: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80010dc: 4b32 ldr r3, [pc, #200] @ (80011a8 ) 80010de: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80010e2: 601a str r2, [r3, #0] htim2.Init.Prescaler = 9999; 80010e4: 4b30 ldr r3, [pc, #192] @ (80011a8 ) 80010e6: f242 720f movw r2, #9999 @ 0x270f 80010ea: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80010ec: 4b2e ldr r3, [pc, #184] @ (80011a8 ) 80010ee: 2200 movs r2, #0 80010f0: 609a str r2, [r3, #8] htim2.Init.Period = 2999; 80010f2: 4b2d ldr r3, [pc, #180] @ (80011a8 ) 80010f4: f640 32b7 movw r2, #2999 @ 0xbb7 80010f8: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 80010fa: 4b2b ldr r3, [pc, #172] @ (80011a8 ) 80010fc: f44f 7280 mov.w r2, #256 @ 0x100 8001100: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001102: 4b29 ldr r3, [pc, #164] @ (80011a8 ) 8001104: 2280 movs r2, #128 @ 0x80 8001106: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8001108: 4827 ldr r0, [pc, #156] @ (80011a8 ) 800110a: f00e f989 bl 800f420 800110e: 4603 mov r3, r0 8001110: 2b00 cmp r3, #0 8001112: d001 beq.n 8001118 { Error_Handler(); 8001114: f000 feda bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001118: f44f 5380 mov.w r3, #4096 @ 0x1000 800111c: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 800111e: f107 0320 add.w r3, r7, #32 8001122: 4619 mov r1, r3 8001124: 4820 ldr r0, [pc, #128] @ (80011a8 ) 8001126: f00f f921 bl 801036c 800112a: 4603 mov r3, r0 800112c: 2b00 cmp r3, #0 800112e: d001 beq.n 8001134 { Error_Handler(); 8001130: f000 fecc bl 8001ecc } if (HAL_TIM_IC_Init(&htim2) != HAL_OK) 8001134: 481c ldr r0, [pc, #112] @ (80011a8 ) 8001136: f00e fcaf bl 800fa98 800113a: 4603 mov r3, r0 800113c: 2b00 cmp r3, #0 800113e: d001 beq.n 8001144 { Error_Handler(); 8001140: f000 fec4 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001144: 2320 movs r3, #32 8001146: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001148: 2380 movs r3, #128 @ 0x80 800114a: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800114c: f107 0314 add.w r3, r7, #20 8001150: 4619 mov r1, r3 8001152: 4815 ldr r0, [pc, #84] @ (80011a8 ) 8001154: f010 f808 bl 8011168 8001158: 4603 mov r3, r0 800115a: 2b00 cmp r3, #0 800115c: d001 beq.n 8001162 { Error_Handler(); 800115e: f000 feb5 bl 8001ecc } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 8001162: 2300 movs r3, #0 8001164: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 8001166: 2301 movs r3, #1 8001168: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 800116a: 2300 movs r3, #0 800116c: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 800116e: 2300 movs r3, #0 8001170: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 8001172: 1d3b adds r3, r7, #4 8001174: 2208 movs r2, #8 8001176: 4619 mov r1, r3 8001178: 480b ldr r0, [pc, #44] @ (80011a8 ) 800117a: f00e ff46 bl 801000a 800117e: 4603 mov r3, r0 8001180: 2b00 cmp r3, #0 8001182: d001 beq.n 8001188 { Error_Handler(); 8001184: f000 fea2 bl 8001ecc } if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 8001188: 1d3b adds r3, r7, #4 800118a: 220c movs r2, #12 800118c: 4619 mov r1, r3 800118e: 4806 ldr r0, [pc, #24] @ (80011a8 ) 8001190: f00e ff3b bl 801000a 8001194: 4603 mov r3, r0 8001196: 2b00 cmp r3, #0 8001198: d001 beq.n 800119e { Error_Handler(); 800119a: f000 fe97 bl 8001ecc } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 800119e: bf00 nop 80011a0: 3730 adds r7, #48 @ 0x30 80011a2: 46bd mov sp, r7 80011a4: bd80 pop {r7, pc} 80011a6: bf00 nop 80011a8: 24000488 .word 0x24000488 080011ac : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 80011ac: b5b0 push {r4, r5, r7, lr} 80011ae: b08a sub sp, #40 @ 0x28 80011b0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011b2: f107 031c add.w r3, r7, #28 80011b6: 2200 movs r2, #0 80011b8: 601a str r2, [r3, #0] 80011ba: 605a str r2, [r3, #4] 80011bc: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 80011be: 463b mov r3, r7 80011c0: 2200 movs r2, #0 80011c2: 601a str r2, [r3, #0] 80011c4: 605a str r2, [r3, #4] 80011c6: 609a str r2, [r3, #8] 80011c8: 60da str r2, [r3, #12] 80011ca: 611a str r2, [r3, #16] 80011cc: 615a str r2, [r3, #20] 80011ce: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80011d0: 4b48 ldr r3, [pc, #288] @ (80012f4 ) 80011d2: 4a49 ldr r2, [pc, #292] @ (80012f8 ) 80011d4: 601a str r2, [r3, #0] htim3.Init.Prescaler = 199; 80011d6: 4b47 ldr r3, [pc, #284] @ (80012f4 ) 80011d8: 22c7 movs r2, #199 @ 0xc7 80011da: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80011dc: 4b45 ldr r3, [pc, #276] @ (80012f4 ) 80011de: 2200 movs r2, #0 80011e0: 609a str r2, [r3, #8] htim3.Init.Period = 999; 80011e2: 4b44 ldr r3, [pc, #272] @ (80012f4 ) 80011e4: f240 32e7 movw r2, #999 @ 0x3e7 80011e8: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80011ea: 4b42 ldr r3, [pc, #264] @ (80012f4 ) 80011ec: 2200 movs r2, #0 80011ee: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80011f0: 4b40 ldr r3, [pc, #256] @ (80012f4 ) 80011f2: 2280 movs r2, #128 @ 0x80 80011f4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 80011f6: 483f ldr r0, [pc, #252] @ (80012f4 ) 80011f8: f00e fa52 bl 800f6a0 80011fc: 4603 mov r3, r0 80011fe: 2b00 cmp r3, #0 8001200: d001 beq.n 8001206 { Error_Handler(); 8001202: f000 fe63 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001206: 2300 movs r3, #0 8001208: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800120a: 2300 movs r3, #0 800120c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800120e: f107 031c add.w r3, r7, #28 8001212: 4619 mov r1, r3 8001214: 4837 ldr r0, [pc, #220] @ (80012f4 ) 8001216: f00f ffa7 bl 8011168 800121a: 4603 mov r3, r0 800121c: 2b00 cmp r3, #0 800121e: d001 beq.n 8001224 { Error_Handler(); 8001220: f000 fe54 bl 8001ecc } sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 8001224: 4b35 ldr r3, [pc, #212] @ (80012fc ) 8001226: 603b str r3, [r7, #0] sConfigOC.Pulse = 500; 8001228: f44f 73fa mov.w r3, #500 @ 0x1f4 800122c: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800122e: 2300 movs r3, #0 8001230: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001232: 2300 movs r3, #0 8001234: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001236: 463b mov r3, r7 8001238: 2200 movs r2, #0 800123a: 4619 mov r1, r3 800123c: 482d ldr r0, [pc, #180] @ (80012f4 ) 800123e: f00e ff81 bl 8010144 8001242: 4603 mov r3, r0 8001244: 2b00 cmp r3, #0 8001246: d001 beq.n 800124c { Error_Handler(); 8001248: f000 fe40 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 800124c: 4b29 ldr r3, [pc, #164] @ (80012f4 ) 800124e: 681b ldr r3, [r3, #0] 8001250: 699a ldr r2, [r3, #24] 8001252: 4b28 ldr r3, [pc, #160] @ (80012f4 ) 8001254: 681b ldr r3, [r3, #0] 8001256: f022 0208 bic.w r2, r2, #8 800125a: 619a str r2, [r3, #24] sConfigOC.OCMode = TIM_OCMODE_PWM1; 800125c: 2360 movs r3, #96 @ 0x60 800125e: 603b str r3, [r7, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001260: 463b mov r3, r7 8001262: 2204 movs r2, #4 8001264: 4619 mov r1, r3 8001266: 4823 ldr r0, [pc, #140] @ (80012f4 ) 8001268: f00e ff6c bl 8010144 800126c: 4603 mov r3, r0 800126e: 2b00 cmp r3, #0 8001270: d001 beq.n 8001276 { Error_Handler(); 8001272: f000 fe2b bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 8001276: 4b1f ldr r3, [pc, #124] @ (80012f4 ) 8001278: 681b ldr r3, [r3, #0] 800127a: 699a ldr r2, [r3, #24] 800127c: 4b1d ldr r3, [pc, #116] @ (80012f4 ) 800127e: 681b ldr r3, [r3, #0] 8001280: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001284: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8001286: 463b mov r3, r7 8001288: 2208 movs r2, #8 800128a: 4619 mov r1, r3 800128c: 4819 ldr r0, [pc, #100] @ (80012f4 ) 800128e: f00e ff59 bl 8010144 8001292: 4603 mov r3, r0 8001294: 2b00 cmp r3, #0 8001296: d001 beq.n 800129c { Error_Handler(); 8001298: f000 fe18 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 800129c: 4b15 ldr r3, [pc, #84] @ (80012f4 ) 800129e: 681b ldr r3, [r3, #0] 80012a0: 69da ldr r2, [r3, #28] 80012a2: 4b14 ldr r3, [pc, #80] @ (80012f4 ) 80012a4: 681b ldr r3, [r3, #0] 80012a6: f022 0208 bic.w r2, r2, #8 80012aa: 61da str r2, [r3, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 80012ac: 463b mov r3, r7 80012ae: 220c movs r2, #12 80012b0: 4619 mov r1, r3 80012b2: 4810 ldr r0, [pc, #64] @ (80012f4 ) 80012b4: f00e ff46 bl 8010144 80012b8: 4603 mov r3, r0 80012ba: 2b00 cmp r3, #0 80012bc: d001 beq.n 80012c2 { Error_Handler(); 80012be: f000 fe05 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 80012c2: 4b0c ldr r3, [pc, #48] @ (80012f4 ) 80012c4: 681b ldr r3, [r3, #0] 80012c6: 69da ldr r2, [r3, #28] 80012c8: 4b0a ldr r3, [pc, #40] @ (80012f4 ) 80012ca: 681b ldr r3, [r3, #0] 80012cc: f422 6200 bic.w r2, r2, #2048 @ 0x800 80012d0: 61da str r2, [r3, #28] /* USER CODE BEGIN TIM3_Init 2 */ memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 80012d2: 4b0b ldr r3, [pc, #44] @ (8001300 ) 80012d4: 461d mov r5, r3 80012d6: 463c mov r4, r7 80012d8: cc0f ldmia r4!, {r0, r1, r2, r3} 80012da: c50f stmia r5!, {r0, r1, r2, r3} 80012dc: e894 0007 ldmia.w r4, {r0, r1, r2} 80012e0: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 80012e4: 4803 ldr r0, [pc, #12] @ (80012f4 ) 80012e6: f003 f899 bl 800441c } 80012ea: bf00 nop 80012ec: 3728 adds r7, #40 @ 0x28 80012ee: 46bd mov sp, r7 80012f0: bdb0 pop {r4, r5, r7, pc} 80012f2: bf00 nop 80012f4: 240004d4 .word 0x240004d4 80012f8: 40000400 .word 0x40000400 80012fc: 00010040 .word 0x00010040 8001300: 240007c0 .word 0x240007c0 08001304 : * @brief TIM4 Initialization Function * @param None * @retval None */ static void MX_TIM4_Init(void) { 8001304: b580 push {r7, lr} 8001306: b08c sub sp, #48 @ 0x30 8001308: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800130a: f107 0320 add.w r3, r7, #32 800130e: 2200 movs r2, #0 8001310: 601a str r2, [r3, #0] 8001312: 605a str r2, [r3, #4] 8001314: 609a str r2, [r3, #8] 8001316: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001318: f107 0314 add.w r3, r7, #20 800131c: 2200 movs r2, #0 800131e: 601a str r2, [r3, #0] 8001320: 605a str r2, [r3, #4] 8001322: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 8001324: 1d3b adds r3, r7, #4 8001326: 2200 movs r2, #0 8001328: 601a str r2, [r3, #0] 800132a: 605a str r2, [r3, #4] 800132c: 609a str r2, [r3, #8] 800132e: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 8001330: 4b31 ldr r3, [pc, #196] @ (80013f8 ) 8001332: 4a32 ldr r2, [pc, #200] @ (80013fc ) 8001334: 601a str r2, [r3, #0] htim4.Init.Prescaler = 9999; 8001336: 4b30 ldr r3, [pc, #192] @ (80013f8 ) 8001338: f242 720f movw r2, #9999 @ 0x270f 800133c: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800133e: 4b2e ldr r3, [pc, #184] @ (80013f8 ) 8001340: 2200 movs r2, #0 8001342: 609a str r2, [r3, #8] htim4.Init.Period = 2999; 8001344: 4b2c ldr r3, [pc, #176] @ (80013f8 ) 8001346: f640 32b7 movw r2, #2999 @ 0xbb7 800134a: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 800134c: 4b2a ldr r3, [pc, #168] @ (80013f8 ) 800134e: f44f 7280 mov.w r2, #256 @ 0x100 8001352: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001354: 4b28 ldr r3, [pc, #160] @ (80013f8 ) 8001356: 2280 movs r2, #128 @ 0x80 8001358: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800135a: 4827 ldr r0, [pc, #156] @ (80013f8 ) 800135c: f00e f860 bl 800f420 8001360: 4603 mov r3, r0 8001362: 2b00 cmp r3, #0 8001364: d001 beq.n 800136a { Error_Handler(); 8001366: f000 fdb1 bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800136a: f44f 5380 mov.w r3, #4096 @ 0x1000 800136e: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 8001370: f107 0320 add.w r3, r7, #32 8001374: 4619 mov r1, r3 8001376: 4820 ldr r0, [pc, #128] @ (80013f8 ) 8001378: f00e fff8 bl 801036c 800137c: 4603 mov r3, r0 800137e: 2b00 cmp r3, #0 8001380: d001 beq.n 8001386 { Error_Handler(); 8001382: f000 fda3 bl 8001ecc } if (HAL_TIM_IC_Init(&htim4) != HAL_OK) 8001386: 481c ldr r0, [pc, #112] @ (80013f8 ) 8001388: f00e fb86 bl 800fa98 800138c: 4603 mov r3, r0 800138e: 2b00 cmp r3, #0 8001390: d001 beq.n 8001396 { Error_Handler(); 8001392: f000 fd9b bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001396: 2300 movs r3, #0 8001398: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800139a: 2300 movs r3, #0 800139c: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800139e: f107 0314 add.w r3, r7, #20 80013a2: 4619 mov r1, r3 80013a4: 4814 ldr r0, [pc, #80] @ (80013f8 ) 80013a6: f00f fedf bl 8011168 80013aa: 4603 mov r3, r0 80013ac: 2b00 cmp r3, #0 80013ae: d001 beq.n 80013b4 { Error_Handler(); 80013b0: f000 fd8c bl 8001ecc } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 80013b4: 2300 movs r3, #0 80013b6: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 80013b8: 2301 movs r3, #1 80013ba: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 80013bc: 2300 movs r3, #0 80013be: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 80013c0: 2300 movs r3, #0 80013c2: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 80013c4: 1d3b adds r3, r7, #4 80013c6: 2208 movs r2, #8 80013c8: 4619 mov r1, r3 80013ca: 480b ldr r0, [pc, #44] @ (80013f8 ) 80013cc: f00e fe1d bl 801000a 80013d0: 4603 mov r3, r0 80013d2: 2b00 cmp r3, #0 80013d4: d001 beq.n 80013da { Error_Handler(); 80013d6: f000 fd79 bl 8001ecc } if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 80013da: 1d3b adds r3, r7, #4 80013dc: 220c movs r2, #12 80013de: 4619 mov r1, r3 80013e0: 4805 ldr r0, [pc, #20] @ (80013f8 ) 80013e2: f00e fe12 bl 801000a 80013e6: 4603 mov r3, r0 80013e8: 2b00 cmp r3, #0 80013ea: d001 beq.n 80013f0 { Error_Handler(); 80013ec: f000 fd6e bl 8001ecc } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ } 80013f0: bf00 nop 80013f2: 3730 adds r7, #48 @ 0x30 80013f4: 46bd mov sp, r7 80013f6: bd80 pop {r7, pc} 80013f8: 24000520 .word 0x24000520 80013fc: 40000800 .word 0x40000800 08001400 : * @brief TIM8 Initialization Function * @param None * @retval None */ static void MX_TIM8_Init(void) { 8001400: b580 push {r7, lr} 8001402: b088 sub sp, #32 8001404: af00 add r7, sp, #0 /* USER CODE BEGIN TIM8_Init 0 */ /* USER CODE END TIM8_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001406: f107 0310 add.w r3, r7, #16 800140a: 2200 movs r2, #0 800140c: 601a str r2, [r3, #0] 800140e: 605a str r2, [r3, #4] 8001410: 609a str r2, [r3, #8] 8001412: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001414: 1d3b adds r3, r7, #4 8001416: 2200 movs r2, #0 8001418: 601a str r2, [r3, #0] 800141a: 605a str r2, [r3, #4] 800141c: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM8_Init 1 */ /* USER CODE END TIM8_Init 1 */ htim8.Instance = TIM8; 800141e: 4b21 ldr r3, [pc, #132] @ (80014a4 ) 8001420: 4a21 ldr r2, [pc, #132] @ (80014a8 ) 8001422: 601a str r2, [r3, #0] htim8.Init.Prescaler = 9999; 8001424: 4b1f ldr r3, [pc, #124] @ (80014a4 ) 8001426: f242 720f movw r2, #9999 @ 0x270f 800142a: 605a str r2, [r3, #4] htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 800142c: 4b1d ldr r3, [pc, #116] @ (80014a4 ) 800142e: 2200 movs r2, #0 8001430: 609a str r2, [r3, #8] htim8.Init.Period = 999; 8001432: 4b1c ldr r3, [pc, #112] @ (80014a4 ) 8001434: f240 32e7 movw r2, #999 @ 0x3e7 8001438: 60da str r2, [r3, #12] htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 800143a: 4b1a ldr r3, [pc, #104] @ (80014a4 ) 800143c: f44f 7280 mov.w r2, #256 @ 0x100 8001440: 611a str r2, [r3, #16] htim8.Init.RepetitionCounter = 0; 8001442: 4b18 ldr r3, [pc, #96] @ (80014a4 ) 8001444: 2200 movs r2, #0 8001446: 615a str r2, [r3, #20] htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001448: 4b16 ldr r3, [pc, #88] @ (80014a4 ) 800144a: 2280 movs r2, #128 @ 0x80 800144c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 800144e: 4815 ldr r0, [pc, #84] @ (80014a4 ) 8001450: f00d ffe6 bl 800f420 8001454: 4603 mov r3, r0 8001456: 2b00 cmp r3, #0 8001458: d001 beq.n 800145e { Error_Handler(); 800145a: f000 fd37 bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800145e: f44f 5380 mov.w r3, #4096 @ 0x1000 8001462: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 8001464: f107 0310 add.w r3, r7, #16 8001468: 4619 mov r1, r3 800146a: 480e ldr r0, [pc, #56] @ (80014a4 ) 800146c: f00e ff7e bl 801036c 8001470: 4603 mov r3, r0 8001472: 2b00 cmp r3, #0 8001474: d001 beq.n 800147a { Error_Handler(); 8001476: f000 fd29 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 800147a: 2320 movs r3, #32 800147c: 607b str r3, [r7, #4] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 800147e: 2300 movs r3, #0 8001480: 60bb str r3, [r7, #8] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001482: 2380 movs r3, #128 @ 0x80 8001484: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 8001486: 1d3b adds r3, r7, #4 8001488: 4619 mov r1, r3 800148a: 4806 ldr r0, [pc, #24] @ (80014a4 ) 800148c: f00f fe6c bl 8011168 8001490: 4603 mov r3, r0 8001492: 2b00 cmp r3, #0 8001494: d001 beq.n 800149a { Error_Handler(); 8001496: f000 fd19 bl 8001ecc } /* USER CODE BEGIN TIM8_Init 2 */ /* USER CODE END TIM8_Init 2 */ } 800149a: bf00 nop 800149c: 3720 adds r7, #32 800149e: 46bd mov sp, r7 80014a0: bd80 pop {r7, pc} 80014a2: bf00 nop 80014a4: 2400056c .word 0x2400056c 80014a8: 40010400 .word 0x40010400 080014ac : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 80014ac: b580 push {r7, lr} 80014ae: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 80014b0: 4b22 ldr r3, [pc, #136] @ (800153c ) 80014b2: 4a23 ldr r2, [pc, #140] @ (8001540 ) 80014b4: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 80014b6: 4b21 ldr r3, [pc, #132] @ (800153c ) 80014b8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80014bc: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 80014be: 4b1f ldr r3, [pc, #124] @ (800153c ) 80014c0: 2200 movs r2, #0 80014c2: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 80014c4: 4b1d ldr r3, [pc, #116] @ (800153c ) 80014c6: 2200 movs r2, #0 80014c8: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 80014ca: 4b1c ldr r3, [pc, #112] @ (800153c ) 80014cc: 2200 movs r2, #0 80014ce: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 80014d0: 4b1a ldr r3, [pc, #104] @ (800153c ) 80014d2: 220c movs r2, #12 80014d4: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80014d6: 4b19 ldr r3, [pc, #100] @ (800153c ) 80014d8: 2200 movs r2, #0 80014da: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 80014dc: 4b17 ldr r3, [pc, #92] @ (800153c ) 80014de: 2200 movs r2, #0 80014e0: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80014e2: 4b16 ldr r3, [pc, #88] @ (800153c ) 80014e4: 2200 movs r2, #0 80014e6: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80014e8: 4b14 ldr r3, [pc, #80] @ (800153c ) 80014ea: 2200 movs r2, #0 80014ec: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80014ee: 4b13 ldr r3, [pc, #76] @ (800153c ) 80014f0: 2200 movs r2, #0 80014f2: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 80014f4: 4811 ldr r0, [pc, #68] @ (800153c ) 80014f6: f00f ff61 bl 80113bc 80014fa: 4603 mov r3, r0 80014fc: 2b00 cmp r3, #0 80014fe: d001 beq.n 8001504 { Error_Handler(); 8001500: f000 fce4 bl 8001ecc } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001504: 2100 movs r1, #0 8001506: 480d ldr r0, [pc, #52] @ (800153c ) 8001508: f012 fc01 bl 8013d0e 800150c: 4603 mov r3, r0 800150e: 2b00 cmp r3, #0 8001510: d001 beq.n 8001516 { Error_Handler(); 8001512: f000 fcdb bl 8001ecc } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8001516: 2100 movs r1, #0 8001518: 4808 ldr r0, [pc, #32] @ (800153c ) 800151a: f012 fc36 bl 8013d8a 800151e: 4603 mov r3, r0 8001520: 2b00 cmp r3, #0 8001522: d001 beq.n 8001528 { Error_Handler(); 8001524: f000 fcd2 bl 8001ecc } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8001528: 4804 ldr r0, [pc, #16] @ (800153c ) 800152a: f012 fbb7 bl 8013c9c 800152e: 4603 mov r3, r0 8001530: 2b00 cmp r3, #0 8001532: d001 beq.n 8001538 { Error_Handler(); 8001534: f000 fcca bl 8001ecc } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 8001538: bf00 nop 800153a: bd80 pop {r7, pc} 800153c: 240005b8 .word 0x240005b8 8001540: 40007c00 .word 0x40007c00 08001544 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8001544: b580 push {r7, lr} 8001546: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001548: 4b24 ldr r3, [pc, #144] @ (80015dc ) 800154a: 4a25 ldr r2, [pc, #148] @ (80015e0 ) 800154c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800154e: 4b23 ldr r3, [pc, #140] @ (80015dc ) 8001550: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001554: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8001556: 4b21 ldr r3, [pc, #132] @ (80015dc ) 8001558: 2200 movs r2, #0 800155a: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800155c: 4b1f ldr r3, [pc, #124] @ (80015dc ) 800155e: 2200 movs r2, #0 8001560: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8001562: 4b1e ldr r3, [pc, #120] @ (80015dc ) 8001564: 2200 movs r2, #0 8001566: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001568: 4b1c ldr r3, [pc, #112] @ (80015dc ) 800156a: 220c movs r2, #12 800156c: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800156e: 4b1b ldr r3, [pc, #108] @ (80015dc ) 8001570: 2200 movs r2, #0 8001572: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001574: 4b19 ldr r3, [pc, #100] @ (80015dc ) 8001576: 2200 movs r2, #0 8001578: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800157a: 4b18 ldr r3, [pc, #96] @ (80015dc ) 800157c: 2200 movs r2, #0 800157e: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001580: 4b16 ldr r3, [pc, #88] @ (80015dc ) 8001582: 2200 movs r2, #0 8001584: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT; 8001586: 4b15 ldr r3, [pc, #84] @ (80015dc ) 8001588: 2201 movs r2, #1 800158a: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 800158c: 4b13 ldr r3, [pc, #76] @ (80015dc ) 800158e: f44f 3200 mov.w r2, #131072 @ 0x20000 8001592: 62da str r2, [r3, #44] @ 0x2c if (HAL_UART_Init(&huart1) != HAL_OK) 8001594: 4811 ldr r0, [pc, #68] @ (80015dc ) 8001596: f00f ff11 bl 80113bc 800159a: 4603 mov r3, r0 800159c: 2b00 cmp r3, #0 800159e: d001 beq.n 80015a4 { Error_Handler(); 80015a0: f000 fc94 bl 8001ecc } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 80015a4: 2100 movs r1, #0 80015a6: 480d ldr r0, [pc, #52] @ (80015dc ) 80015a8: f012 fbb1 bl 8013d0e 80015ac: 4603 mov r3, r0 80015ae: 2b00 cmp r3, #0 80015b0: d001 beq.n 80015b6 { Error_Handler(); 80015b2: f000 fc8b bl 8001ecc } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80015b6: 2100 movs r1, #0 80015b8: 4808 ldr r0, [pc, #32] @ (80015dc ) 80015ba: f012 fbe6 bl 8013d8a 80015be: 4603 mov r3, r0 80015c0: 2b00 cmp r3, #0 80015c2: d001 beq.n 80015c8 { Error_Handler(); 80015c4: f000 fc82 bl 8001ecc } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 80015c8: 4804 ldr r0, [pc, #16] @ (80015dc ) 80015ca: f012 fb67 bl 8013c9c 80015ce: 4603 mov r3, r0 80015d0: 2b00 cmp r3, #0 80015d2: d001 beq.n 80015d8 { Error_Handler(); 80015d4: f000 fc7a bl 8001ecc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80015d8: bf00 nop 80015da: bd80 pop {r7, pc} 80015dc: 2400064c .word 0x2400064c 80015e0: 40011000 .word 0x40011000 080015e4 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80015e4: b580 push {r7, lr} 80015e6: b082 sub sp, #8 80015e8: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 80015ea: 4b15 ldr r3, [pc, #84] @ (8001640 ) 80015ec: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 80015f0: 4a13 ldr r2, [pc, #76] @ (8001640 ) 80015f2: f043 0301 orr.w r3, r3, #1 80015f6: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 80015fa: 4b11 ldr r3, [pc, #68] @ (8001640 ) 80015fc: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8001600: f003 0301 and.w r3, r3, #1 8001604: 607b str r3, [r7, #4] 8001606: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8001608: 2200 movs r2, #0 800160a: 2105 movs r1, #5 800160c: 200b movs r0, #11 800160e: f006 faab bl 8007b68 HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8001612: 200b movs r0, #11 8001614: f006 fac2 bl 8007b9c /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 8001618: 2200 movs r2, #0 800161a: 2105 movs r1, #5 800161c: 200c movs r0, #12 800161e: f006 faa3 bl 8007b68 HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 8001622: 200c movs r0, #12 8001624: f006 faba bl 8007b9c /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 8001628: 2200 movs r2, #0 800162a: 2105 movs r1, #5 800162c: 200d movs r0, #13 800162e: f006 fa9b bl 8007b68 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8001632: 200d movs r0, #13 8001634: f006 fab2 bl 8007b9c } 8001638: bf00 nop 800163a: 3708 adds r7, #8 800163c: 46bd mov sp, r7 800163e: bd80 pop {r7, pc} 8001640: 58024400 .word 0x58024400 08001644 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001644: b580 push {r7, lr} 8001646: b08c sub sp, #48 @ 0x30 8001648: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800164a: f107 031c add.w r3, r7, #28 800164e: 2200 movs r2, #0 8001650: 601a str r2, [r3, #0] 8001652: 605a str r2, [r3, #4] 8001654: 609a str r2, [r3, #8] 8001656: 60da str r2, [r3, #12] 8001658: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 800165a: 4b58 ldr r3, [pc, #352] @ (80017bc ) 800165c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001660: 4a56 ldr r2, [pc, #344] @ (80017bc ) 8001662: f043 0380 orr.w r3, r3, #128 @ 0x80 8001666: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800166a: 4b54 ldr r3, [pc, #336] @ (80017bc ) 800166c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001670: f003 0380 and.w r3, r3, #128 @ 0x80 8001674: 61bb str r3, [r7, #24] 8001676: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001678: 4b50 ldr r3, [pc, #320] @ (80017bc ) 800167a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800167e: 4a4f ldr r2, [pc, #316] @ (80017bc ) 8001680: f043 0304 orr.w r3, r3, #4 8001684: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001688: 4b4c ldr r3, [pc, #304] @ (80017bc ) 800168a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800168e: f003 0304 and.w r3, r3, #4 8001692: 617b str r3, [r7, #20] 8001694: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001696: 4b49 ldr r3, [pc, #292] @ (80017bc ) 8001698: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800169c: 4a47 ldr r2, [pc, #284] @ (80017bc ) 800169e: f043 0301 orr.w r3, r3, #1 80016a2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016a6: 4b45 ldr r3, [pc, #276] @ (80017bc ) 80016a8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ac: f003 0301 and.w r3, r3, #1 80016b0: 613b str r3, [r7, #16] 80016b2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80016b4: 4b41 ldr r3, [pc, #260] @ (80017bc ) 80016b6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ba: 4a40 ldr r2, [pc, #256] @ (80017bc ) 80016bc: f043 0302 orr.w r3, r3, #2 80016c0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016c4: 4b3d ldr r3, [pc, #244] @ (80017bc ) 80016c6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ca: f003 0302 and.w r3, r3, #2 80016ce: 60fb str r3, [r7, #12] 80016d0: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 80016d2: 4b3a ldr r3, [pc, #232] @ (80017bc ) 80016d4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016d8: 4a38 ldr r2, [pc, #224] @ (80017bc ) 80016da: f043 0310 orr.w r3, r3, #16 80016de: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016e2: 4b36 ldr r3, [pc, #216] @ (80017bc ) 80016e4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016e8: f003 0310 and.w r3, r3, #16 80016ec: 60bb str r3, [r7, #8] 80016ee: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 80016f0: 4b32 ldr r3, [pc, #200] @ (80017bc ) 80016f2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016f6: 4a31 ldr r2, [pc, #196] @ (80017bc ) 80016f8: f043 0308 orr.w r3, r3, #8 80016fc: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001700: 4b2e ldr r3, [pc, #184] @ (80017bc ) 8001702: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001706: f003 0308 and.w r3, r3, #8 800170a: 607b str r3, [r7, #4] 800170c: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 800170e: 2200 movs r2, #0 8001710: f24e 7180 movw r1, #59264 @ 0xe780 8001714: 482a ldr r0, [pc, #168] @ (80017c0 ) 8001716: f009 ff21 bl 800b55c |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 800171a: 2200 movs r2, #0 800171c: 21f0 movs r1, #240 @ 0xf0 800171e: 4829 ldr r0, [pc, #164] @ (80017c4 ) 8001720: f009 ff1c bl 800b55c /*Configure GPIO pins : PE7 PE8 PE9 PE10 PE13 PE14 PE15 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8001724: f24e 7380 movw r3, #59264 @ 0xe780 8001728: 61fb str r3, [r7, #28] |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800172a: 2301 movs r3, #1 800172c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800172e: 2300 movs r3, #0 8001730: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001732: 2300 movs r3, #0 8001734: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001736: f107 031c add.w r3, r7, #28 800173a: 4619 mov r1, r3 800173c: 4820 ldr r0, [pc, #128] @ (80017c0 ) 800173e: f009 fd45 bl 800b1cc /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12 PD13 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 8001742: f44f 537c mov.w r3, #16128 @ 0x3f00 8001746: 61fb str r3, [r7, #28] |GPIO_PIN_12|GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8001748: f44f 1344 mov.w r3, #3211264 @ 0x310000 800174c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800174e: 2300 movs r3, #0 8001750: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001752: f107 031c add.w r3, r7, #28 8001756: 4619 mov r1, r3 8001758: 481a ldr r0, [pc, #104] @ (80017c4 ) 800175a: f009 fd37 bl 800b1cc /*Configure GPIO pin : PD3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 800175e: 2308 movs r3, #8 8001760: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001762: 2300 movs r3, #0 8001764: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001766: 2300 movs r3, #0 8001768: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800176a: f107 031c add.w r3, r7, #28 800176e: 4619 mov r1, r3 8001770: 4814 ldr r0, [pc, #80] @ (80017c4 ) 8001772: f009 fd2b bl 800b1cc /*Configure GPIO pins : PD4 PD5 PD6 PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 8001776: 23f0 movs r3, #240 @ 0xf0 8001778: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800177a: 2301 movs r3, #1 800177c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800177e: 2300 movs r3, #0 8001780: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001782: 2300 movs r3, #0 8001784: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001786: f107 031c add.w r3, r7, #28 800178a: 4619 mov r1, r3 800178c: 480d ldr r0, [pc, #52] @ (80017c4 ) 800178e: f009 fd1d bl 800b1cc /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); 8001792: 2200 movs r2, #0 8001794: 2105 movs r1, #5 8001796: 2017 movs r0, #23 8001798: f006 f9e6 bl 8007b68 HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 800179c: 2017 movs r0, #23 800179e: f006 f9fd bl 8007b9c HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 80017a2: 2200 movs r2, #0 80017a4: 2105 movs r1, #5 80017a6: 2028 movs r0, #40 @ 0x28 80017a8: f006 f9de bl 8007b68 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 80017ac: 2028 movs r0, #40 @ 0x28 80017ae: f006 f9f5 bl 8007b9c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 80017b2: bf00 nop 80017b4: 3730 adds r7, #48 @ 0x30 80017b6: 46bd mov sp, r7 80017b8: bd80 pop {r7, pc} 80017ba: bf00 nop 80017bc: 58024400 .word 0x58024400 80017c0: 58021000 .word 0x58021000 80017c4: 58020c00 .word 0x58020c00 080017c8 : /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 80017c8: b580 push {r7, lr} 80017ca: b08e sub sp, #56 @ 0x38 80017cc: af00 add r7, sp, #0 80017ce: 6078 str r0, [r7, #4] if(hadc->Instance == ADC1) 80017d0: 687b ldr r3, [r7, #4] 80017d2: 681b ldr r3, [r3, #0] 80017d4: 4a67 ldr r2, [pc, #412] @ (8001974 ) 80017d6: 4293 cmp r3, r2 80017d8: d13f bne.n 800185a { DbgLEDToggle(DBG_LED4); 80017da: 2080 movs r0, #128 @ 0x80 80017dc: f001 fba6 bl 8002f2c SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80017e0: 4b65 ldr r3, [pc, #404] @ (8001978 ) 80017e2: f023 031f bic.w r3, r3, #31 80017e6: 637b str r3, [r7, #52] @ 0x34 80017e8: 2320 movs r3, #32 80017ea: 633b str r3, [r7, #48] @ 0x30 \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { 80017ec: 6b3b ldr r3, [r7, #48] @ 0x30 80017ee: 2b00 cmp r3, #0 80017f0: dd1d ble.n 800182e int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80017f2: 6b7b ldr r3, [r7, #52] @ 0x34 80017f4: f003 021f and.w r2, r3, #31 80017f8: 6b3b ldr r3, [r7, #48] @ 0x30 80017fa: 4413 add r3, r2 80017fc: 62fb str r3, [r7, #44] @ 0x2c uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 80017fe: 6b7b ldr r3, [r7, #52] @ 0x34 8001800: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("dsb 0xF":::"memory"); 8001802: f3bf 8f4f dsb sy } 8001806: bf00 nop __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001808: 4a5c ldr r2, [pc, #368] @ (800197c ) 800180a: 6abb ldr r3, [r7, #40] @ 0x28 800180c: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001810: 6abb ldr r3, [r7, #40] @ 0x28 8001812: 3320 adds r3, #32 8001814: 62bb str r3, [r7, #40] @ 0x28 op_size -= __SCB_DCACHE_LINE_SIZE; 8001816: 6afb ldr r3, [r7, #44] @ 0x2c 8001818: 3b20 subs r3, #32 800181a: 62fb str r3, [r7, #44] @ 0x2c } while ( op_size > 0 ); 800181c: 6afb ldr r3, [r7, #44] @ 0x2c 800181e: 2b00 cmp r3, #0 8001820: dcf2 bgt.n 8001808 __ASM volatile ("dsb 0xF":::"memory"); 8001822: f3bf 8f4f dsb sy } 8001826: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001828: f3bf 8f6f isb sy } 800182c: bf00 nop __DSB(); __ISB(); } #endif } 800182e: bf00 nop if(adc1MeasDataQueue != NULL) 8001830: 4b53 ldr r3, [pc, #332] @ (8001980 ) 8001832: 681b ldr r3, [r3, #0] 8001834: 2b00 cmp r3, #0 8001836: d006 beq.n 8001846 { osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 8001838: 4b51 ldr r3, [pc, #324] @ (8001980 ) 800183a: 6818 ldr r0, [r3, #0] 800183c: 2300 movs r3, #0 800183e: 2200 movs r2, #0 8001840: 494d ldr r1, [pc, #308] @ (8001978 ) 8001842: f012 ff33 bl 80146ac } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001846: 2207 movs r2, #7 8001848: 494b ldr r1, [pc, #300] @ (8001978 ) 800184a: 484e ldr r0, [pc, #312] @ (8001984 ) 800184c: f004 fee8 bl 8006620 8001850: 4603 mov r3, r0 8001852: 2b00 cmp r3, #0 8001854: d001 beq.n 800185a { Error_Handler(); 8001856: f000 fb39 bl 8001ecc } } if(hadc->Instance == ADC2) 800185a: 687b ldr r3, [r7, #4] 800185c: 681b ldr r3, [r3, #0] 800185e: 4a4a ldr r2, [pc, #296] @ (8001988 ) 8001860: 4293 cmp r3, r2 8001862: d13c bne.n 80018de { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 8001864: 4b49 ldr r3, [pc, #292] @ (800198c ) 8001866: f023 031f bic.w r3, r3, #31 800186a: 627b str r3, [r7, #36] @ 0x24 800186c: 2320 movs r3, #32 800186e: 623b str r3, [r7, #32] if ( dsize > 0 ) { 8001870: 6a3b ldr r3, [r7, #32] 8001872: 2b00 cmp r3, #0 8001874: dd1d ble.n 80018b2 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 8001876: 6a7b ldr r3, [r7, #36] @ 0x24 8001878: f003 021f and.w r2, r3, #31 800187c: 6a3b ldr r3, [r7, #32] 800187e: 4413 add r3, r2 8001880: 61fb str r3, [r7, #28] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001882: 6a7b ldr r3, [r7, #36] @ 0x24 8001884: 61bb str r3, [r7, #24] __ASM volatile ("dsb 0xF":::"memory"); 8001886: f3bf 8f4f dsb sy } 800188a: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 800188c: 4a3b ldr r2, [pc, #236] @ (800197c ) 800188e: 69bb ldr r3, [r7, #24] 8001890: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001894: 69bb ldr r3, [r7, #24] 8001896: 3320 adds r3, #32 8001898: 61bb str r3, [r7, #24] op_size -= __SCB_DCACHE_LINE_SIZE; 800189a: 69fb ldr r3, [r7, #28] 800189c: 3b20 subs r3, #32 800189e: 61fb str r3, [r7, #28] } while ( op_size > 0 ); 80018a0: 69fb ldr r3, [r7, #28] 80018a2: 2b00 cmp r3, #0 80018a4: dcf2 bgt.n 800188c __ASM volatile ("dsb 0xF":::"memory"); 80018a6: f3bf 8f4f dsb sy } 80018aa: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80018ac: f3bf 8f6f isb sy } 80018b0: bf00 nop } 80018b2: bf00 nop if(adc2MeasDataQueue != NULL) 80018b4: 4b36 ldr r3, [pc, #216] @ (8001990 ) 80018b6: 681b ldr r3, [r3, #0] 80018b8: 2b00 cmp r3, #0 80018ba: d006 beq.n 80018ca { osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0); 80018bc: 4b34 ldr r3, [pc, #208] @ (8001990 ) 80018be: 6818 ldr r0, [r3, #0] 80018c0: 2300 movs r3, #0 80018c2: 2200 movs r2, #0 80018c4: 4931 ldr r1, [pc, #196] @ (800198c ) 80018c6: f012 fef1 bl 80146ac } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 80018ca: 2203 movs r2, #3 80018cc: 492f ldr r1, [pc, #188] @ (800198c ) 80018ce: 4831 ldr r0, [pc, #196] @ (8001994 ) 80018d0: f004 fea6 bl 8006620 80018d4: 4603 mov r3, r0 80018d6: 2b00 cmp r3, #0 80018d8: d001 beq.n 80018de { Error_Handler(); 80018da: f000 faf7 bl 8001ecc } } if(hadc->Instance == ADC3) 80018de: 687b ldr r3, [r7, #4] 80018e0: 681b ldr r3, [r3, #0] 80018e2: 4a2d ldr r2, [pc, #180] @ (8001998 ) 80018e4: 4293 cmp r3, r2 80018e6: d13c bne.n 8001962 { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80018e8: 4b2c ldr r3, [pc, #176] @ (800199c ) 80018ea: f023 031f bic.w r3, r3, #31 80018ee: 617b str r3, [r7, #20] 80018f0: 2320 movs r3, #32 80018f2: 613b str r3, [r7, #16] if ( dsize > 0 ) { 80018f4: 693b ldr r3, [r7, #16] 80018f6: 2b00 cmp r3, #0 80018f8: dd1d ble.n 8001936 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80018fa: 697b ldr r3, [r7, #20] 80018fc: f003 021f and.w r2, r3, #31 8001900: 693b ldr r3, [r7, #16] 8001902: 4413 add r3, r2 8001904: 60fb str r3, [r7, #12] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001906: 697b ldr r3, [r7, #20] 8001908: 60bb str r3, [r7, #8] __ASM volatile ("dsb 0xF":::"memory"); 800190a: f3bf 8f4f dsb sy } 800190e: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001910: 4a1a ldr r2, [pc, #104] @ (800197c ) 8001912: 68bb ldr r3, [r7, #8] 8001914: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001918: 68bb ldr r3, [r7, #8] 800191a: 3320 adds r3, #32 800191c: 60bb str r3, [r7, #8] op_size -= __SCB_DCACHE_LINE_SIZE; 800191e: 68fb ldr r3, [r7, #12] 8001920: 3b20 subs r3, #32 8001922: 60fb str r3, [r7, #12] } while ( op_size > 0 ); 8001924: 68fb ldr r3, [r7, #12] 8001926: 2b00 cmp r3, #0 8001928: dcf2 bgt.n 8001910 __ASM volatile ("dsb 0xF":::"memory"); 800192a: f3bf 8f4f dsb sy } 800192e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001930: f3bf 8f6f isb sy } 8001934: bf00 nop } 8001936: bf00 nop if(adc3MeasDataQueue != NULL) 8001938: 4b19 ldr r3, [pc, #100] @ (80019a0 ) 800193a: 681b ldr r3, [r3, #0] 800193c: 2b00 cmp r3, #0 800193e: d006 beq.n 800194e { osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 8001940: 4b17 ldr r3, [pc, #92] @ (80019a0 ) 8001942: 6818 ldr r0, [r3, #0] 8001944: 2300 movs r3, #0 8001946: 2200 movs r2, #0 8001948: 4914 ldr r1, [pc, #80] @ (800199c ) 800194a: f012 feaf bl 80146ac } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 800194e: 2205 movs r2, #5 8001950: 4912 ldr r1, [pc, #72] @ (800199c ) 8001952: 4814 ldr r0, [pc, #80] @ (80019a4 ) 8001954: f004 fe64 bl 8006620 8001958: 4603 mov r3, r0 800195a: 2b00 cmp r3, #0 800195c: d001 beq.n 8001962 { Error_Handler(); 800195e: f000 fab5 bl 8001ecc } }osTimerStop (debugLedTimerHandle); 8001962: 4b11 ldr r3, [pc, #68] @ (80019a8 ) 8001964: 681b ldr r3, [r3, #0] 8001966: 4618 mov r0, r3 8001968: f012 fce8 bl 801433c } 800196c: bf00 nop 800196e: 3738 adds r7, #56 @ 0x38 8001970: 46bd mov sp, r7 8001972: bd80 pop {r7, pc} 8001974: 40022000 .word 0x40022000 8001978: 240000c0 .word 0x240000c0 800197c: e000ed00 .word 0xe000ed00 8001980: 24000800 .word 0x24000800 8001984: 24000120 .word 0x24000120 8001988: 40022100 .word 0x40022100 800198c: 240000e0 .word 0x240000e0 8001990: 24000804 .word 0x24000804 8001994: 24000184 .word 0x24000184 8001998: 58026000 .word 0x58026000 800199c: 24000100 .word 0x24000100 80019a0: 24000808 .word 0x24000808 80019a4: 240001e8 .word 0x240001e8 80019a8: 240006e4 .word 0x240006e4 080019ac : void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80019ac: b580 push {r7, lr} 80019ae: b084 sub sp, #16 80019b0: af00 add r7, sp, #0 80019b2: 6078 str r0, [r7, #4] if (htim->Instance == TIM4) 80019b4: 687b ldr r3, [r7, #4] 80019b6: 681b ldr r3, [r3, #0] 80019b8: 4a61 ldr r2, [pc, #388] @ (8001b40 ) 80019ba: 4293 cmp r3, r2 80019bc: d15a bne.n 8001a74 { if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 80019be: 687b ldr r3, [r7, #4] 80019c0: 7f1b ldrb r3, [r3, #28] 80019c2: 2b04 cmp r3, #4 80019c4: d114 bne.n 80019f0 { if(encoderXChannelB > 0) 80019c6: 4b5f ldr r3, [pc, #380] @ (8001b44 ) 80019c8: 681b ldr r3, [r3, #0] 80019ca: 2b00 cmp r3, #0 80019cc: dd08 ble.n 80019e0 { encoderXChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 80019ce: 2108 movs r1, #8 80019d0: 6878 ldr r0, [r7, #4] 80019d2: f00e fdc3 bl 801055c 80019d6: 4603 mov r3, r0 80019d8: 461a mov r2, r3 80019da: 4b5b ldr r3, [pc, #364] @ (8001b48 ) 80019dc: 601a str r2, [r3, #0] 80019de: e01f b.n 8001a20 } else { encoderXChannelA = 1; 80019e0: 4b59 ldr r3, [pc, #356] @ (8001b48 ) 80019e2: 2201 movs r2, #1 80019e4: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 80019e6: 687b ldr r3, [r7, #4] 80019e8: 681b ldr r3, [r3, #0] 80019ea: 2200 movs r2, #0 80019ec: 625a str r2, [r3, #36] @ 0x24 80019ee: e017 b.n 8001a20 } } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 80019f0: 687b ldr r3, [r7, #4] 80019f2: 7f1b ldrb r3, [r3, #28] 80019f4: 2b08 cmp r3, #8 80019f6: d113 bne.n 8001a20 { if(encoderXChannelA > 0) 80019f8: 4b53 ldr r3, [pc, #332] @ (8001b48 ) 80019fa: 681b ldr r3, [r3, #0] 80019fc: 2b00 cmp r3, #0 80019fe: dd08 ble.n 8001a12 { encoderXChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001a00: 210c movs r1, #12 8001a02: 6878 ldr r0, [r7, #4] 8001a04: f00e fdaa bl 801055c 8001a08: 4603 mov r3, r0 8001a0a: 461a mov r2, r3 8001a0c: 4b4d ldr r3, [pc, #308] @ (8001b44 ) 8001a0e: 601a str r2, [r3, #0] 8001a10: e006 b.n 8001a20 } else { encoderXChannelB = 1; 8001a12: 4b4c ldr r3, [pc, #304] @ (8001b44 ) 8001a14: 2201 movs r2, #1 8001a16: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001a18: 687b ldr r3, [r7, #4] 8001a1a: 681b ldr r3, [r3, #0] 8001a1c: 2200 movs r2, #0 8001a1e: 625a str r2, [r3, #36] @ 0x24 } } if((encoderXChannelA != 0) && (encoderXChannelB != 0)) 8001a20: 4b49 ldr r3, [pc, #292] @ (8001b48 ) 8001a22: 681b ldr r3, [r3, #0] 8001a24: 2b00 cmp r3, #0 8001a26: f000 8086 beq.w 8001b36 8001a2a: 4b46 ldr r3, [pc, #280] @ (8001b44 ) 8001a2c: 681b ldr r3, [r3, #0] 8001a2e: 2b00 cmp r3, #0 8001a30: f000 8081 beq.w 8001b36 { EncoderData encoderData = { 0 }; 8001a34: 2300 movs r3, #0 8001a36: 81bb strh r3, [r7, #12] encoderData.axe = encoderAxeX; 8001a38: 2300 movs r3, #0 8001a3a: 733b strb r3, [r7, #12] encoderData.direction = encoderXChannelA - encoderXChannelB < 0 ? encoderCW : encoderCCW; 8001a3c: 4b42 ldr r3, [pc, #264] @ (8001b48 ) 8001a3e: 681a ldr r2, [r3, #0] 8001a40: 4b40 ldr r3, [pc, #256] @ (8001b44 ) 8001a42: 681b ldr r3, [r3, #0] 8001a44: 1ad3 subs r3, r2, r3 8001a46: 43db mvns r3, r3 8001a48: 0fdb lsrs r3, r3, #31 8001a4a: b2db uxtb r3, r3 8001a4c: 737b strb r3, [r7, #13] if (encoderData.direction == encoderCCW) 8001a4e: 7b7b ldrb r3, [r7, #13] 8001a50: 2b01 cmp r3, #1 8001a52: d100 bne.n 8001a56 { asm("nop;"); 8001a54: bf00 nop } osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); 8001a56: 4b3d ldr r3, [pc, #244] @ (8001b4c ) 8001a58: 6818 ldr r0, [r3, #0] 8001a5a: f107 010c add.w r1, r7, #12 8001a5e: 2300 movs r3, #0 8001a60: 2200 movs r2, #0 8001a62: f012 fe23 bl 80146ac encoderXChannelA = 0; 8001a66: 4b38 ldr r3, [pc, #224] @ (8001b48 ) 8001a68: 2200 movs r2, #0 8001a6a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001a6c: 4b35 ldr r3, [pc, #212] @ (8001b44 ) 8001a6e: 2200 movs r2, #0 8001a70: 601a str r2, [r3, #0] osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); encoderYChannelA = 0; encoderYChannelB = 0; } } } 8001a72: e060 b.n 8001b36 } else if (htim->Instance == TIM2) 8001a74: 687b ldr r3, [r7, #4] 8001a76: 681b ldr r3, [r3, #0] 8001a78: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001a7c: d15b bne.n 8001b36 if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 7f1b ldrb r3, [r3, #28] 8001a82: 2b04 cmp r3, #4 8001a84: d114 bne.n 8001ab0 if(encoderYChannelB > 0) 8001a86: 4b32 ldr r3, [pc, #200] @ (8001b50 ) 8001a88: 681b ldr r3, [r3, #0] 8001a8a: 2b00 cmp r3, #0 8001a8c: dd08 ble.n 8001aa0 encoderYChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 8001a8e: 2108 movs r1, #8 8001a90: 6878 ldr r0, [r7, #4] 8001a92: f00e fd63 bl 801055c 8001a96: 4603 mov r3, r0 8001a98: 461a mov r2, r3 8001a9a: 4b2e ldr r3, [pc, #184] @ (8001b54 ) 8001a9c: 601a str r2, [r3, #0] 8001a9e: e01f b.n 8001ae0 encoderYChannelA = 1; 8001aa0: 4b2c ldr r3, [pc, #176] @ (8001b54 ) 8001aa2: 2201 movs r2, #1 8001aa4: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001aa6: 687b ldr r3, [r7, #4] 8001aa8: 681b ldr r3, [r3, #0] 8001aaa: 2200 movs r2, #0 8001aac: 625a str r2, [r3, #36] @ 0x24 8001aae: e017 b.n 8001ae0 } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 8001ab0: 687b ldr r3, [r7, #4] 8001ab2: 7f1b ldrb r3, [r3, #28] 8001ab4: 2b08 cmp r3, #8 8001ab6: d113 bne.n 8001ae0 if(encoderYChannelA > 0) 8001ab8: 4b26 ldr r3, [pc, #152] @ (8001b54 ) 8001aba: 681b ldr r3, [r3, #0] 8001abc: 2b00 cmp r3, #0 8001abe: dd08 ble.n 8001ad2 encoderYChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001ac0: 210c movs r1, #12 8001ac2: 6878 ldr r0, [r7, #4] 8001ac4: f00e fd4a bl 801055c 8001ac8: 4603 mov r3, r0 8001aca: 461a mov r2, r3 8001acc: 4b20 ldr r3, [pc, #128] @ (8001b50 ) 8001ace: 601a str r2, [r3, #0] 8001ad0: e006 b.n 8001ae0 encoderYChannelB = 1; 8001ad2: 4b1f ldr r3, [pc, #124] @ (8001b50 ) 8001ad4: 2201 movs r2, #1 8001ad6: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001ad8: 687b ldr r3, [r7, #4] 8001ada: 681b ldr r3, [r3, #0] 8001adc: 2200 movs r2, #0 8001ade: 625a str r2, [r3, #36] @ 0x24 if((encoderYChannelA != 0) && (encoderYChannelB != 0)) 8001ae0: 4b1c ldr r3, [pc, #112] @ (8001b54 ) 8001ae2: 681b ldr r3, [r3, #0] 8001ae4: 2b00 cmp r3, #0 8001ae6: d026 beq.n 8001b36 8001ae8: 4b19 ldr r3, [pc, #100] @ (8001b50 ) 8001aea: 681b ldr r3, [r3, #0] 8001aec: 2b00 cmp r3, #0 8001aee: d022 beq.n 8001b36 EncoderData encoderData = { 0 }; 8001af0: 2300 movs r3, #0 8001af2: 813b strh r3, [r7, #8] encoderData.axe = encoderAxeY; 8001af4: 2301 movs r3, #1 8001af6: 723b strb r3, [r7, #8] encoderData.direction = encoderYChannelA - encoderYChannelB < 0 ? encoderCW : encoderCCW; 8001af8: 4b16 ldr r3, [pc, #88] @ (8001b54 ) 8001afa: 681a ldr r2, [r3, #0] 8001afc: 4b14 ldr r3, [pc, #80] @ (8001b50 ) 8001afe: 681b ldr r3, [r3, #0] 8001b00: 1ad3 subs r3, r2, r3 8001b02: 43db mvns r3, r3 8001b04: 0fdb lsrs r3, r3, #31 8001b06: b2db uxtb r3, r3 8001b08: 727b strb r3, [r7, #9] if (encoderData.direction == encoderCCW) 8001b0a: 7a7b ldrb r3, [r7, #9] 8001b0c: 2b01 cmp r3, #1 8001b0e: d100 bne.n 8001b12 asm("nop;"); 8001b10: bf00 nop if (encoderData.direction == encoderCW) 8001b12: 7a7b ldrb r3, [r7, #9] 8001b14: 2b00 cmp r3, #0 8001b16: d100 bne.n 8001b1a asm("nop;"); 8001b18: bf00 nop osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); 8001b1a: 4b0c ldr r3, [pc, #48] @ (8001b4c ) 8001b1c: 6818 ldr r0, [r3, #0] 8001b1e: f107 0108 add.w r1, r7, #8 8001b22: 2300 movs r3, #0 8001b24: 2200 movs r2, #0 8001b26: f012 fdc1 bl 80146ac encoderYChannelA = 0; 8001b2a: 4b0a ldr r3, [pc, #40] @ (8001b54 ) 8001b2c: 2200 movs r2, #0 8001b2e: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001b30: 4b07 ldr r3, [pc, #28] @ (8001b50 ) 8001b32: 2200 movs r2, #0 8001b34: 601a str r2, [r3, #0] } 8001b36: bf00 nop 8001b38: 3710 adds r7, #16 8001b3a: 46bd mov sp, r7 8001b3c: bd80 pop {r7, pc} 8001b3e: bf00 nop 8001b40: 40000800 .word 0x40000800 8001b44: 240007e0 .word 0x240007e0 8001b48: 240007dc .word 0x240007dc 8001b4c: 24000810 .word 0x24000810 8001b50: 240007e8 .word 0x240007e8 8001b54: 240007e4 .word 0x240007e4 08001b58 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 8001b58: b580 push {r7, lr} 8001b5a: b082 sub sp, #8 8001b5c: af00 add r7, sp, #0 8001b5e: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001b60: 485e ldr r0, [pc, #376] @ (8001cdc ) 8001b62: f009 fd97 bl 800b694 #endif SelectCurrentSensorGain(CurrentSensorL1, csGain3); 8001b66: 2102 movs r1, #2 8001b68: 2000 movs r0, #0 8001b6a: f001 f9fd bl 8002f68 SelectCurrentSensorGain(CurrentSensorL2, csGain3); 8001b6e: 2102 movs r1, #2 8001b70: 2001 movs r0, #1 8001b72: f001 f9f9 bl 8002f68 SelectCurrentSensorGain(CurrentSensorL3, csGain3); 8001b76: 2102 movs r1, #2 8001b78: 2002 movs r0, #2 8001b7a: f001 f9f5 bl 8002f68 EnableCurrentSensors(); 8001b7e: f001 f9e7 bl 8002f50 osDelay(pdMS_TO_TICKS(100)); 8001b82: 2064 movs r0, #100 @ 0x64 8001b84: f012 faff bl 8014186 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001b88: 4854 ldr r0, [pc, #336] @ (8001cdc ) 8001b8a: f009 fd83 bl 800b694 #endif if(HAL_TIM_Base_Start(&htim8) != HAL_OK) 8001b8e: 4854 ldr r0, [pc, #336] @ (8001ce0 ) 8001b90: f00d fc9e bl 800f4d0 8001b94: 4603 mov r3, r0 8001b96: 2b00 cmp r3, #0 8001b98: d001 beq.n 8001b9e { Error_Handler(); 8001b9a: f000 f997 bl 8001ecc } if(HAL_TIM_Base_Start_IT(&htim2) != HAL_OK) 8001b9e: 4851 ldr r0, [pc, #324] @ (8001ce4 ) 8001ba0: f00d fd06 bl 800f5b0 8001ba4: 4603 mov r3, r0 8001ba6: 2b00 cmp r3, #0 8001ba8: d001 beq.n 8001bae { Error_Handler(); 8001baa: f000 f98f bl 8001ecc } if(HAL_TIM_Base_Start_IT(&htim4) != HAL_OK) 8001bae: 484e ldr r0, [pc, #312] @ (8001ce8 ) 8001bb0: f00d fcfe bl 800f5b0 8001bb4: 4603 mov r3, r0 8001bb6: 2b00 cmp r3, #0 8001bb8: d001 beq.n 8001bbe { Error_Handler(); 8001bba: f000 f987 bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_3) != HAL_OK) 8001bbe: 2108 movs r1, #8 8001bc0: 4849 ldr r0, [pc, #292] @ (8001ce8 ) 8001bc2: f00d ffcb bl 800fb5c 8001bc6: 4603 mov r3, r0 8001bc8: 2b00 cmp r3, #0 8001bca: d001 beq.n 8001bd0 { Error_Handler(); 8001bcc: f000 f97e bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_4) != HAL_OK) 8001bd0: 210c movs r1, #12 8001bd2: 4845 ldr r0, [pc, #276] @ (8001ce8 ) 8001bd4: f00d ffc2 bl 800fb5c 8001bd8: 4603 mov r3, r0 8001bda: 2b00 cmp r3, #0 8001bdc: d001 beq.n 8001be2 { Error_Handler(); 8001bde: f000 f975 bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_3) != HAL_OK) 8001be2: 2108 movs r1, #8 8001be4: 483f ldr r0, [pc, #252] @ (8001ce4 ) 8001be6: f00d ffb9 bl 800fb5c 8001bea: 4603 mov r3, r0 8001bec: 2b00 cmp r3, #0 8001bee: d001 beq.n 8001bf4 { Error_Handler(); 8001bf0: f000 f96c bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_4) != HAL_OK) 8001bf4: 210c movs r1, #12 8001bf6: 483b ldr r0, [pc, #236] @ (8001ce4 ) 8001bf8: f00d ffb0 bl 800fb5c 8001bfc: 4603 mov r3, r0 8001bfe: 2b00 cmp r3, #0 8001c00: d001 beq.n 8001c06 { Error_Handler(); 8001c02: f000 f963 bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001c06: 2207 movs r2, #7 8001c08: 4938 ldr r1, [pc, #224] @ (8001cec ) 8001c0a: 4839 ldr r0, [pc, #228] @ (8001cf0 ) 8001c0c: f004 fd08 bl 8006620 8001c10: 4603 mov r3, r0 8001c12: 2b00 cmp r3, #0 8001c14: d001 beq.n 8001c1a { Error_Handler(); 8001c16: f000 f959 bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 8001c1a: 2203 movs r2, #3 8001c1c: 4935 ldr r1, [pc, #212] @ (8001cf4 ) 8001c1e: 4836 ldr r0, [pc, #216] @ (8001cf8 ) 8001c20: f004 fcfe bl 8006620 8001c24: 4603 mov r3, r0 8001c26: 2b00 cmp r3, #0 8001c28: d001 beq.n 8001c2e { Error_Handler(); 8001c2a: f000 f94f bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 8001c2e: 2205 movs r2, #5 8001c30: 4932 ldr r1, [pc, #200] @ (8001cfc ) 8001c32: 4833 ldr r0, [pc, #204] @ (8001d00 ) 8001c34: f004 fcf4 bl 8006620 8001c38: 4603 mov r3, r0 8001c3a: 2b00 cmp r3, #0 8001c3c: d001 beq.n 8001c42 { Error_Handler(); 8001c3e: f000 f945 bl 8001ecc } HAL_COMP_Start(&hcomp1); 8001c42: 4830 ldr r0, [pc, #192] @ (8001d04 ) 8001c44: f005 fe70 bl 8007928 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001c48: 4824 ldr r0, [pc, #144] @ (8001cdc ) 8001c4a: f009 fd23 bl 800b694 #endif /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(100)); 8001c4e: 2064 movs r0, #100 @ 0x64 8001c50: f012 fa99 bl 8014186 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001c54: 4821 ldr r0, [pc, #132] @ (8001cdc ) 8001c56: f009 fd1d bl 800b694 #endif if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001c5a: 2100 movs r1, #0 8001c5c: 482a ldr r0, [pc, #168] @ (8001d08 ) 8001c5e: f00e fcdf bl 8010620 8001c62: 4603 mov r3, r0 8001c64: 2b01 cmp r3, #1 8001c66: d118 bne.n 8001c9a HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001c68: 2104 movs r1, #4 8001c6a: 4827 ldr r0, [pc, #156] @ (8001d08 ) 8001c6c: f00e fcd8 bl 8010620 8001c70: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001c72: 2b01 cmp r3, #1 8001c74: d111 bne.n 8001c9a { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001c76: 4b25 ldr r3, [pc, #148] @ (8001d0c ) 8001c78: 681b ldr r3, [r3, #0] 8001c7a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001c7e: 4618 mov r0, r3 8001c80: f012 fc19 bl 80144b6 8001c84: 4603 mov r3, r0 8001c86: 2b00 cmp r3, #0 8001c88: d107 bne.n 8001c9a { sensorsInfo.motorXStatus = 0; 8001c8a: 4b21 ldr r3, [pc, #132] @ (8001d10 ) 8001c8c: 2200 movs r2, #0 8001c8e: 751a strb r2, [r3, #20] osMutexRelease(sensorsInfoMutex); 8001c90: 4b1e ldr r3, [pc, #120] @ (8001d0c ) 8001c92: 681b ldr r3, [r3, #0] 8001c94: 4618 mov r0, r3 8001c96: f012 fc59 bl 801454c } } if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001c9a: 2108 movs r1, #8 8001c9c: 481a ldr r0, [pc, #104] @ (8001d08 ) 8001c9e: f00e fcbf bl 8010620 8001ca2: 4603 mov r3, r0 8001ca4: 2b01 cmp r3, #1 8001ca6: d1d2 bne.n 8001c4e HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 8001ca8: 210c movs r1, #12 8001caa: 4817 ldr r0, [pc, #92] @ (8001d08 ) 8001cac: f00e fcb8 bl 8010620 8001cb0: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001cb2: 2b01 cmp r3, #1 8001cb4: d1cb bne.n 8001c4e { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001cb6: 4b15 ldr r3, [pc, #84] @ (8001d0c ) 8001cb8: 681b ldr r3, [r3, #0] 8001cba: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001cbe: 4618 mov r0, r3 8001cc0: f012 fbf9 bl 80144b6 8001cc4: 4603 mov r3, r0 8001cc6: 2b00 cmp r3, #0 8001cc8: d1c1 bne.n 8001c4e { sensorsInfo.motorYStatus = 0; 8001cca: 4b11 ldr r3, [pc, #68] @ (8001d10 ) 8001ccc: 2200 movs r2, #0 8001cce: 755a strb r2, [r3, #21] osMutexRelease(sensorsInfoMutex); 8001cd0: 4b0e ldr r3, [pc, #56] @ (8001d0c ) 8001cd2: 681b ldr r3, [r3, #0] 8001cd4: 4618 mov r0, r3 8001cd6: f012 fc39 bl 801454c osDelay(pdMS_TO_TICKS(100)); 8001cda: e7b8 b.n 8001c4e 8001cdc: 24000418 .word 0x24000418 8001ce0: 2400056c .word 0x2400056c 8001ce4: 24000488 .word 0x24000488 8001ce8: 24000520 .word 0x24000520 8001cec: 240000c0 .word 0x240000c0 8001cf0: 24000120 .word 0x24000120 8001cf4: 240000e0 .word 0x240000e0 8001cf8: 24000184 .word 0x24000184 8001cfc: 24000100 .word 0x24000100 8001d00: 240001e8 .word 0x240001e8 8001d04: 240003b4 .word 0x240003b4 8001d08: 240004d4 .word 0x240004d4 8001d0c: 2400081c .word 0x2400081c 8001d10: 24000860 .word 0x24000860 08001d14 : /* USER CODE END 5 */ } /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { 8001d14: b580 push {r7, lr} 8001d16: b082 sub sp, #8 8001d18: af00 add r7, sp, #0 8001d1a: 6078 str r0, [r7, #4] /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 8001d1c: 2010 movs r0, #16 8001d1e: f001 f8f3 bl 8002f08 /* USER CODE END debugLedTimerCallback */ } 8001d22: bf00 nop 8001d24: 3708 adds r7, #8 8001d26: 46bd mov sp, r7 8001d28: bd80 pop {r7, pc} ... 08001d2c : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { 8001d2c: b580 push {r7, lr} 8001d2e: b082 sub sp, #8 8001d30: af00 add r7, sp, #0 8001d32: 6078 str r0, [r7, #4] /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 8001d34: 2104 movs r1, #4 8001d36: 4803 ldr r0, [pc, #12] @ (8001d44 ) 8001d38: f00d fe18 bl 800f96c /* USER CODE END fanTimerCallback */ } 8001d3c: bf00 nop 8001d3e: 3708 adds r7, #8 8001d40: 46bd mov sp, r7 8001d42: bd80 pop {r7, pc} 8001d44: 2400043c .word 0x2400043c 08001d48 : /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 8001d48: b580 push {r7, lr} 8001d4a: b084 sub sp, #16 8001d4c: af02 add r7, sp, #8 8001d4e: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorXTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 8001d50: 2300 movs r3, #0 8001d52: 9301 str r3, [sp, #4] 8001d54: 2300 movs r3, #0 8001d56: 9300 str r3, [sp, #0] 8001d58: 2304 movs r3, #4 8001d5a: 2200 movs r2, #0 8001d5c: 4907 ldr r1, [pc, #28] @ (8001d7c ) 8001d5e: 4808 ldr r0, [pc, #32] @ (8001d80 ) 8001d60: f001 fa87 bl 8003272 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 8001d64: 2100 movs r1, #0 8001d66: 4806 ldr r0, [pc, #24] @ (8001d80 ) 8001d68: f00d fe00 bl 800f96c HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 8001d6c: 2104 movs r1, #4 8001d6e: 4804 ldr r0, [pc, #16] @ (8001d80 ) 8001d70: f00d fdfc bl 800f96c /* USER CODE END motorXTimerCallback */ } 8001d74: bf00 nop 8001d76: 3708 adds r7, #8 8001d78: 46bd mov sp, r7 8001d7a: bd80 pop {r7, pc} 8001d7c: 240007c0 .word 0x240007c0 8001d80: 240004d4 .word 0x240004d4 08001d84 : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 8001d84: b580 push {r7, lr} 8001d86: b084 sub sp, #16 8001d88: af02 add r7, sp, #8 8001d8a: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorYTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 8001d8c: 2300 movs r3, #0 8001d8e: 9301 str r3, [sp, #4] 8001d90: 2300 movs r3, #0 8001d92: 9300 str r3, [sp, #0] 8001d94: 230c movs r3, #12 8001d96: 2208 movs r2, #8 8001d98: 4907 ldr r1, [pc, #28] @ (8001db8 ) 8001d9a: 4808 ldr r0, [pc, #32] @ (8001dbc ) 8001d9c: f001 fa69 bl 8003272 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 8001da0: 2108 movs r1, #8 8001da2: 4806 ldr r0, [pc, #24] @ (8001dbc ) 8001da4: f00d fde2 bl 800f96c HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 8001da8: 210c movs r1, #12 8001daa: 4804 ldr r0, [pc, #16] @ (8001dbc ) 8001dac: f00d fdde bl 800f96c /* USER CODE END motorYTimerCallback */ } 8001db0: bf00 nop 8001db2: 3708 adds r7, #8 8001db4: 46bd mov sp, r7 8001db6: bd80 pop {r7, pc} 8001db8: 240007c0 .word 0x240007c0 8001dbc: 240004d4 .word 0x240004d4 08001dc0 : /* MPU Configuration */ void MPU_Config(void) { 8001dc0: b580 push {r7, lr} 8001dc2: b084 sub sp, #16 8001dc4: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8001dc6: 463b mov r3, r7 8001dc8: 2200 movs r2, #0 8001dca: 601a str r2, [r3, #0] 8001dcc: 605a str r2, [r3, #4] 8001dce: 609a str r2, [r3, #8] 8001dd0: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8001dd2: f005 fef1 bl 8007bb8 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8001dd6: 2301 movs r3, #1 8001dd8: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8001dda: 2300 movs r3, #0 8001ddc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001dde: 2300 movs r3, #0 8001de0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8001de2: 231f movs r3, #31 8001de4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8001de6: 2387 movs r3, #135 @ 0x87 8001de8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001dea: 2300 movs r3, #0 8001dec: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001dee: 2300 movs r3, #0 8001df0: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8001df2: 2301 movs r3, #1 8001df4: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001df6: 2301 movs r3, #1 8001df8: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8001dfa: 2300 movs r3, #0 8001dfc: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001dfe: 2300 movs r3, #0 8001e00: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e02: 463b mov r3, r7 8001e04: 4618 mov r0, r3 8001e06: f005 ff0f bl 8007c28 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8001e0a: 2301 movs r3, #1 8001e0c: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 8001e0e: 4b13 ldr r3, [pc, #76] @ (8001e5c ) 8001e10: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8001e12: 2310 movs r3, #16 8001e14: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 8001e16: 2300 movs r3, #0 8001e18: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8001e1a: 2301 movs r3, #1 8001e1c: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8001e1e: 2303 movs r3, #3 8001e20: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8001e22: 2300 movs r3, #0 8001e24: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e26: 463b mov r3, r7 8001e28: 4618 mov r0, r3 8001e2a: f005 fefd bl 8007c28 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8001e2e: 2302 movs r3, #2 8001e30: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 8001e32: 4b0b ldr r3, [pc, #44] @ (8001e60 ) 8001e34: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8001e36: 2308 movs r3, #8 8001e38: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001e3a: 2300 movs r3, #0 8001e3c: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001e3e: 2301 movs r3, #1 8001e40: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8001e42: 2301 movs r3, #1 8001e44: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e46: 463b mov r3, r7 8001e48: 4618 mov r0, r3 8001e4a: f005 feed bl 8007c28 /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8001e4e: 2004 movs r0, #4 8001e50: f005 feca bl 8007be8 } 8001e54: bf00 nop 8001e56: 3710 adds r7, #16 8001e58: 46bd mov sp, r7 8001e5a: bd80 pop {r7, pc} 8001e5c: 24020000 .word 0x24020000 8001e60: 24040000 .word 0x24040000 08001e64 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001e64: b580 push {r7, lr} 8001e66: b082 sub sp, #8 8001e68: af00 add r7, sp, #0 8001e6a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: 681b ldr r3, [r3, #0] 8001e70: 4a10 ldr r2, [pc, #64] @ (8001eb4 ) 8001e72: 4293 cmp r3, r2 8001e74: d102 bne.n 8001e7c HAL_IncTick(); 8001e76: f003 ffbd bl 8005df4 { encoderYChannelA = 0; encoderYChannelB = 0; } /* USER CODE END Callback 1 */ } 8001e7a: e016 b.n 8001eaa else if (htim->Instance == TIM4) 8001e7c: 687b ldr r3, [r7, #4] 8001e7e: 681b ldr r3, [r3, #0] 8001e80: 4a0d ldr r2, [pc, #52] @ (8001eb8 ) 8001e82: 4293 cmp r3, r2 8001e84: d106 bne.n 8001e94 encoderXChannelA = 0; 8001e86: 4b0d ldr r3, [pc, #52] @ (8001ebc ) 8001e88: 2200 movs r2, #0 8001e8a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001e8c: 4b0c ldr r3, [pc, #48] @ (8001ec0 ) 8001e8e: 2200 movs r2, #0 8001e90: 601a str r2, [r3, #0] } 8001e92: e00a b.n 8001eaa else if (htim->Instance == TIM2) 8001e94: 687b ldr r3, [r7, #4] 8001e96: 681b ldr r3, [r3, #0] 8001e98: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001e9c: d105 bne.n 8001eaa encoderYChannelA = 0; 8001e9e: 4b09 ldr r3, [pc, #36] @ (8001ec4 ) 8001ea0: 2200 movs r2, #0 8001ea2: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001ea4: 4b08 ldr r3, [pc, #32] @ (8001ec8 ) 8001ea6: 2200 movs r2, #0 8001ea8: 601a str r2, [r3, #0] } 8001eaa: bf00 nop 8001eac: 3708 adds r7, #8 8001eae: 46bd mov sp, r7 8001eb0: bd80 pop {r7, pc} 8001eb2: bf00 nop 8001eb4: 40001000 .word 0x40001000 8001eb8: 40000800 .word 0x40000800 8001ebc: 240007dc .word 0x240007dc 8001ec0: 240007e0 .word 0x240007e0 8001ec4: 240007e4 .word 0x240007e4 8001ec8: 240007e8 .word 0x240007e8 08001ecc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001ecc: b580 push {r7, lr} 8001ece: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001ed0: b672 cpsid i } 8001ed2: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); NVIC_SystemReset(); 8001ed4: f7fe fb88 bl 80005e8 <__NVIC_SystemReset> 08001ed8 : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; //extern osMutexId_t positionSettingMutex; void MeasTasksInit (void) { 8001ed8: b580 push {r7, lr} 8001eda: b0ae sub sp, #184 @ 0xb8 8001edc: af00 add r7, sp, #0 vRefmVMutex = osMutexNew (NULL); 8001ede: 2000 movs r0, #0 8001ee0: f012 fa63 bl 80143aa 8001ee4: 4603 mov r3, r0 8001ee6: 4a58 ldr r2, [pc, #352] @ (8002048 ) 8001ee8: 6013 str r3, [r2, #0] resMeasurementsMutex = osMutexNew (NULL); 8001eea: 2000 movs r0, #0 8001eec: f012 fa5d bl 80143aa 8001ef0: 4603 mov r3, r0 8001ef2: 4a56 ldr r2, [pc, #344] @ (800204c ) 8001ef4: 6013 str r3, [r2, #0] sensorsInfoMutex = osMutexNew (NULL); 8001ef6: 2000 movs r0, #0 8001ef8: f012 fa57 bl 80143aa 8001efc: 4603 mov r3, r0 8001efe: 4a54 ldr r2, [pc, #336] @ (8002050 ) 8001f00: 6013 str r3, [r2, #0] ILxRefMutex = osMutexNew (NULL); 8001f02: 2000 movs r0, #0 8001f04: f012 fa51 bl 80143aa 8001f08: 4603 mov r3, r0 8001f0a: 4a52 ldr r2, [pc, #328] @ (8002054 ) 8001f0c: 6013 str r3, [r2, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001f0e: 2200 movs r2, #0 8001f10: 2120 movs r1, #32 8001f12: 2008 movs r0, #8 8001f14: f012 fb57 bl 80145c6 8001f18: 4603 mov r3, r0 8001f1a: 4a4f ldr r2, [pc, #316] @ (8002058 ) 8001f1c: 6013 str r3, [r2, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001f1e: 2200 movs r2, #0 8001f20: 2120 movs r1, #32 8001f22: 2008 movs r0, #8 8001f24: f012 fb4f bl 80145c6 8001f28: 4603 mov r3, r0 8001f2a: 4a4c ldr r2, [pc, #304] @ (800205c ) 8001f2c: 6013 str r3, [r2, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001f2e: 2200 movs r2, #0 8001f30: 2120 movs r1, #32 8001f32: 2008 movs r0, #8 8001f34: f012 fb47 bl 80145c6 8001f38: 4603 mov r3, r0 8001f3a: 4a49 ldr r2, [pc, #292] @ (8002060 ) 8001f3c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001f3e: f107 0394 add.w r3, r7, #148 @ 0x94 8001f42: 2224 movs r2, #36 @ 0x24 8001f44: 2100 movs r1, #0 8001f46: 4618 mov r0, r3 8001f48: f016 f9de bl 8018308 osThreadAttr_t osThreadAttradc2MeasTask = { 0 }; 8001f4c: f107 0370 add.w r3, r7, #112 @ 0x70 8001f50: 2224 movs r2, #36 @ 0x24 8001f52: 2100 movs r1, #0 8001f54: 4618 mov r0, r3 8001f56: f016 f9d7 bl 8018308 osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001f5a: f107 034c add.w r3, r7, #76 @ 0x4c 8001f5e: 2224 movs r2, #36 @ 0x24 8001f60: 2100 movs r1, #0 8001f62: 4618 mov r0, r3 8001f64: f016 f9d0 bl 8018308 osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f68: f44f 6380 mov.w r3, #1024 @ 0x400 8001f6c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001f70: 2330 movs r3, #48 @ 0x30 8001f72: f8c7 30ac str.w r3, [r7, #172] @ 0xac osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f76: f44f 6380 mov.w r3, #1024 @ 0x400 8001f7a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 osThreadAttradc2MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001f7e: 2330 movs r3, #48 @ 0x30 8001f80: f8c7 3088 str.w r3, [r7, #136] @ 0x88 osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f84: f44f 6380 mov.w r3, #1024 @ 0x400 8001f88: 663b str r3, [r7, #96] @ 0x60 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001f8a: 2318 movs r3, #24 8001f8c: 667b str r3, [r7, #100] @ 0x64 adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001f8e: f107 0394 add.w r3, r7, #148 @ 0x94 8001f92: 461a mov r2, r3 8001f94: 2100 movs r1, #0 8001f96: 4833 ldr r0, [pc, #204] @ (8002064 ) 8001f98: f012 f862 bl 8014060 8001f9c: 4603 mov r3, r0 8001f9e: 4a32 ldr r2, [pc, #200] @ (8002068 ) 8001fa0: 6013 str r3, [r2, #0] adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask); 8001fa2: f107 0370 add.w r3, r7, #112 @ 0x70 8001fa6: 461a mov r2, r3 8001fa8: 2100 movs r1, #0 8001faa: 4830 ldr r0, [pc, #192] @ (800206c ) 8001fac: f012 f858 bl 8014060 8001fb0: 4603 mov r3, r0 8001fb2: 4a2f ldr r2, [pc, #188] @ (8002070 ) 8001fb4: 6013 str r3, [r2, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001fb6: f107 034c add.w r3, r7, #76 @ 0x4c 8001fba: 461a mov r2, r3 8001fbc: 2100 movs r1, #0 8001fbe: 482d ldr r0, [pc, #180] @ (8002074 ) 8001fc0: f012 f84e bl 8014060 8001fc4: 4603 mov r3, r0 8001fc6: 4a2c ldr r2, [pc, #176] @ (8002078 ) 8001fc8: 6013 str r3, [r2, #0] limiterSwitchDataQueue = osMessageQueueNew (8, sizeof (LimiterSwitchData), NULL); 8001fca: 2200 movs r2, #0 8001fcc: 2104 movs r1, #4 8001fce: 2008 movs r0, #8 8001fd0: f012 faf9 bl 80145c6 8001fd4: 4603 mov r3, r0 8001fd6: 4a29 ldr r2, [pc, #164] @ (800207c ) 8001fd8: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001fda: f107 0328 add.w r3, r7, #40 @ 0x28 8001fde: 2224 movs r2, #36 @ 0x24 8001fe0: 2100 movs r1, #0 8001fe2: 4618 mov r0, r3 8001fe4: f016 f990 bl 8018308 osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001fe8: f44f 6380 mov.w r3, #1024 @ 0x400 8001fec: 63fb str r3, [r7, #60] @ 0x3c osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001fee: 2318 movs r3, #24 8001ff0: 643b str r3, [r7, #64] @ 0x40 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001ff2: f107 0328 add.w r3, r7, #40 @ 0x28 8001ff6: 461a mov r2, r3 8001ff8: 2100 movs r1, #0 8001ffa: 4821 ldr r0, [pc, #132] @ (8002080 ) 8001ffc: f012 f830 bl 8014060 8002000: 4603 mov r3, r0 8002002: 4a20 ldr r2, [pc, #128] @ (8002084 ) 8002004: 6013 str r3, [r2, #0] encoderDataQueue = osMessageQueueNew (16, sizeof (EncoderData), NULL); 8002006: 2200 movs r2, #0 8002008: 2102 movs r1, #2 800200a: 2010 movs r0, #16 800200c: f012 fadb bl 80145c6 8002010: 4603 mov r3, r0 8002012: 4a1d ldr r2, [pc, #116] @ (8002088 ) 8002014: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8002016: 1d3b adds r3, r7, #4 8002018: 2224 movs r2, #36 @ 0x24 800201a: 2100 movs r1, #0 800201c: 4618 mov r0, r3 800201e: f016 f973 bl 8018308 osThreadAttrEncoderTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8002022: f44f 6380 mov.w r3, #1024 @ 0x400 8002026: 61bb str r3, [r7, #24] osThreadAttrEncoderTask.priority = (osPriority_t)osPriorityNormal; 8002028: 2318 movs r3, #24 800202a: 61fb str r3, [r7, #28] encoderTaskHandle = osThreadNew (EncoderTask, encoderDataQueue, &osThreadAttrEncoderTask); 800202c: 4b16 ldr r3, [pc, #88] @ (8002088 ) 800202e: 681b ldr r3, [r3, #0] 8002030: 1d3a adds r2, r7, #4 8002032: 4619 mov r1, r3 8002034: 4815 ldr r0, [pc, #84] @ (800208c ) 8002036: f012 f813 bl 8014060 800203a: 4603 mov r3, r0 800203c: 4a14 ldr r2, [pc, #80] @ (8002090 ) 800203e: 6013 str r3, [r2, #0] } 8002040: bf00 nop 8002042: 37b8 adds r7, #184 @ 0xb8 8002044: 46bd mov sp, r7 8002046: bd80 pop {r7, pc} 8002048: 24000814 .word 0x24000814 800204c: 24000818 .word 0x24000818 8002050: 2400081c .word 0x2400081c 8002054: 24000820 .word 0x24000820 8002058: 24000800 .word 0x24000800 800205c: 24000804 .word 0x24000804 8002060: 24000808 .word 0x24000808 8002064: 08002099 .word 0x08002099 8002068: 240007ec .word 0x240007ec 800206c: 08002421 .word 0x08002421 8002070: 240007f0 .word 0x240007f0 8002074: 08002729 .word 0x08002729 8002078: 240007f4 .word 0x240007f4 800207c: 2400080c .word 0x2400080c 8002080: 08002aa5 .word 0x08002aa5 8002084: 240007f8 .word 0x240007f8 8002088: 24000810 .word 0x24000810 800208c: 08002d81 .word 0x08002d81 8002090: 240007fc .word 0x240007fc 8002094: 00000000 .word 0x00000000 08002098 : void ADC1MeasTask (void* arg) { 8002098: b580 push {r7, lr} 800209a: b09a sub sp, #104 @ 0x68 800209c: af00 add r7, sp, #0 800209e: 6078 str r0, [r7, #4] float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN] = { 0 }; 80020a0: f107 032c add.w r3, r7, #44 @ 0x2c 80020a4: 2228 movs r2, #40 @ 0x28 80020a6: 2100 movs r1, #0 80020a8: 4618 mov r0, r3 80020aa: f016 f92d bl 8018308 float rms[VOLTAGES_COUNT] = { 0 }; 80020ae: f04f 0300 mov.w r3, #0 80020b2: 62bb str r3, [r7, #40] @ 0x28 ; ADC1_Data adcData = { 0 }; 80020b4: f107 0308 add.w r3, r7, #8 80020b8: 2220 movs r2, #32 80020ba: 2100 movs r1, #0 80020bc: 4618 mov r0, r3 80020be: f016 f923 bl 8018308 uint32_t circBuffPos = 0; 80020c2: 2300 movs r3, #0 80020c4: 667b str r3, [r7, #100] @ 0x64 float gainCorrection = 1.0; 80020c6: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 80020ca: 663b str r3, [r7, #96] @ 0x60 while (pdTRUE) { osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 80020cc: 4bc8 ldr r3, [pc, #800] @ (80023f0 ) 80020ce: 6818 ldr r0, [r3, #0] 80020d0: f107 0108 add.w r1, r7, #8 80020d4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80020d8: 2200 movs r2, #0 80020da: f012 fb47 bl 801476c #ifdef GAIN_AUTO_CORRECTION if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80020de: 4bc5 ldr r3, [pc, #788] @ (80023f4 ) 80020e0: 681b ldr r3, [r3, #0] 80020e2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80020e6: 4618 mov r0, r3 80020e8: f012 f9e5 bl 80144b6 80020ec: 4603 mov r3, r0 80020ee: 2b00 cmp r3, #0 80020f0: d10c bne.n 800210c gainCorrection = (float)vRefmV; 80020f2: 4bc1 ldr r3, [pc, #772] @ (80023f8 ) 80020f4: 681b ldr r3, [r3, #0] 80020f6: ee07 3a90 vmov s15, r3 80020fa: eef8 7a67 vcvt.f32.u32 s15, s15 80020fe: edc7 7a18 vstr s15, [r7, #96] @ 0x60 osMutexRelease (vRefmVMutex); 8002102: 4bbc ldr r3, [pc, #752] @ (80023f4 ) 8002104: 681b ldr r3, [r3, #0] 8002106: 4618 mov r0, r3 8002108: f012 fa20 bl 801454c } gainCorrection = gainCorrection / EXT_VREF_mV; 800210c: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8002110: eddf 6aba vldr s13, [pc, #744] @ 80023fc 8002114: eec7 7a26 vdiv.f32 s15, s14, s13 8002118: edc7 7a18 vstr s15, [r7, #96] @ 0x60 #endif for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 800211c: 2300 movs r3, #0 800211e: f887 305f strb.w r3, [r7, #95] @ 0x5f 8002122: e0e7 b.n 80022f4 float val = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8002124: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002128: 005b lsls r3, r3, #1 800212a: 3368 adds r3, #104 @ 0x68 800212c: 443b add r3, r7 800212e: f833 3c60 ldrh.w r3, [r3, #-96] 8002132: ee07 3a90 vmov s15, r3 8002136: eeb8 7be7 vcvt.f64.s32 d7, s15 800213a: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800213e: ee27 6b06 vmul.f64 d6, d7, d6 8002142: ed9f 5ba5 vldr d5, [pc, #660] @ 80023d8 8002146: ee86 7b05 vdiv.f64 d7, d6, d5 800214a: ed9f 6ba5 vldr d6, [pc, #660] @ 80023e0 800214e: ee27 6b06 vmul.f64 d6, d7, d6 8002152: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8002156: eeb7 7ae7 vcvt.f64.f32 d7, s15 800215a: ee26 6b07 vmul.f64 d6, d6, d7 800215e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002162: 4aa7 ldr r2, [pc, #668] @ (8002400 ) 8002164: 00db lsls r3, r3, #3 8002166: 4413 add r3, r2 8002168: edd3 7a00 vldr s15, [r3] 800216c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002170: ee26 6b07 vmul.f64 d6, d6, d7 8002174: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002178: 4aa1 ldr r2, [pc, #644] @ (8002400 ) 800217a: 00db lsls r3, r3, #3 800217c: 4413 add r3, r2 800217e: 3304 adds r3, #4 8002180: edd3 7a00 vldr s15, [r3] 8002184: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002188: ee36 7b07 vadd.f64 d7, d6, d7 800218c: eef7 7bc7 vcvt.f32.f64 s15, d7 8002190: edc7 7a15 vstr s15, [r7, #84] @ 0x54 circBuffer[i][circBuffPos] = val; 8002194: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002198: 4613 mov r3, r2 800219a: 009b lsls r3, r3, #2 800219c: 4413 add r3, r2 800219e: 005b lsls r3, r3, #1 80021a0: 6e7a ldr r2, [r7, #100] @ 0x64 80021a2: 4413 add r3, r2 80021a4: 009b lsls r3, r3, #2 80021a6: 3368 adds r3, #104 @ 0x68 80021a8: 443b add r3, r7 80021aa: 3b3c subs r3, #60 @ 0x3c 80021ac: 6d7a ldr r2, [r7, #84] @ 0x54 80021ae: 601a str r2, [r3, #0] rms[i] = 0.0; 80021b0: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021b4: 009b lsls r3, r3, #2 80021b6: 3368 adds r3, #104 @ 0x68 80021b8: 443b add r3, r7 80021ba: 3b40 subs r3, #64 @ 0x40 80021bc: f04f 0200 mov.w r2, #0 80021c0: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80021c2: 2300 movs r3, #0 80021c4: f887 305e strb.w r3, [r7, #94] @ 0x5e 80021c8: e025 b.n 8002216 rms[i] += circBuffer[i][c]; 80021ca: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021ce: 009b lsls r3, r3, #2 80021d0: 3368 adds r3, #104 @ 0x68 80021d2: 443b add r3, r7 80021d4: 3b40 subs r3, #64 @ 0x40 80021d6: ed93 7a00 vldr s14, [r3] 80021da: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 80021de: f897 105e ldrb.w r1, [r7, #94] @ 0x5e 80021e2: 4613 mov r3, r2 80021e4: 009b lsls r3, r3, #2 80021e6: 4413 add r3, r2 80021e8: 005b lsls r3, r3, #1 80021ea: 440b add r3, r1 80021ec: 009b lsls r3, r3, #2 80021ee: 3368 adds r3, #104 @ 0x68 80021f0: 443b add r3, r7 80021f2: 3b3c subs r3, #60 @ 0x3c 80021f4: edd3 7a00 vldr s15, [r3] 80021f8: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021fc: ee77 7a27 vadd.f32 s15, s14, s15 8002200: 009b lsls r3, r3, #2 8002202: 3368 adds r3, #104 @ 0x68 8002204: 443b add r3, r7 8002206: 3b40 subs r3, #64 @ 0x40 8002208: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 800220c: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8002210: 3301 adds r3, #1 8002212: f887 305e strb.w r3, [r7, #94] @ 0x5e 8002216: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 800221a: 2b09 cmp r3, #9 800221c: d9d5 bls.n 80021ca } rms[i] = rms[i] / CIRC_BUFF_LEN; 800221e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002222: 009b lsls r3, r3, #2 8002224: 3368 adds r3, #104 @ 0x68 8002226: 443b add r3, r7 8002228: 3b40 subs r3, #64 @ 0x40 800222a: ed93 7a00 vldr s14, [r3] 800222e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002232: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002236: eec7 7a26 vdiv.f32 s15, s14, s13 800223a: 009b lsls r3, r3, #2 800223c: 3368 adds r3, #104 @ 0x68 800223e: 443b add r3, r7 8002240: 3b40 subs r3, #64 @ 0x40 8002242: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8002246: 4b6f ldr r3, [pc, #444] @ (8002404 ) 8002248: 681b ldr r3, [r3, #0] 800224a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800224e: 4618 mov r0, r3 8002250: f012 f931 bl 80144b6 8002254: 4603 mov r3, r0 8002256: 2b00 cmp r3, #0 8002258: d147 bne.n 80022ea if (fabs (resMeasurements.voltagePeak[i]) < fabs (val)) { 800225a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800225e: 4a6a ldr r2, [pc, #424] @ (8002408 ) 8002260: 3302 adds r3, #2 8002262: 009b lsls r3, r3, #2 8002264: 4413 add r3, r2 8002266: 3304 adds r3, #4 8002268: edd3 7a00 vldr s15, [r3] 800226c: eeb0 7ae7 vabs.f32 s14, s15 8002270: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8002274: eef0 7ae7 vabs.f32 s15, s15 8002278: eeb4 7ae7 vcmpe.f32 s14, s15 800227c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002280: d508 bpl.n 8002294 resMeasurements.voltagePeak[i] = val; 8002282: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002286: 4a60 ldr r2, [pc, #384] @ (8002408 ) 8002288: 3302 adds r3, #2 800228a: 009b lsls r3, r3, #2 800228c: 4413 add r3, r2 800228e: 3304 adds r3, #4 8002290: 6d7a ldr r2, [r7, #84] @ 0x54 8002292: 601a str r2, [r3, #0] } resMeasurements.voltageRMS[i] = rms[i]; 8002294: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002298: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800229c: 0092 lsls r2, r2, #2 800229e: 3268 adds r2, #104 @ 0x68 80022a0: 443a add r2, r7 80022a2: 3a40 subs r2, #64 @ 0x40 80022a4: 6812 ldr r2, [r2, #0] 80022a6: 4958 ldr r1, [pc, #352] @ (8002408 ) 80022a8: 009b lsls r3, r3, #2 80022aa: 440b add r3, r1 80022ac: 601a str r2, [r3, #0] resMeasurements.power[i] = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i]; 80022ae: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022b2: 4a55 ldr r2, [pc, #340] @ (8002408 ) 80022b4: 009b lsls r3, r3, #2 80022b6: 4413 add r3, r2 80022b8: ed93 7a00 vldr s14, [r3] 80022bc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022c0: 4a51 ldr r2, [pc, #324] @ (8002408 ) 80022c2: 3306 adds r3, #6 80022c4: 009b lsls r3, r3, #2 80022c6: 4413 add r3, r2 80022c8: edd3 7a00 vldr s15, [r3] 80022cc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022d0: ee67 7a27 vmul.f32 s15, s14, s15 80022d4: 4a4c ldr r2, [pc, #304] @ (8002408 ) 80022d6: 330c adds r3, #12 80022d8: 009b lsls r3, r3, #2 80022da: 4413 add r3, r2 80022dc: edc3 7a00 vstr s15, [r3] osMutexRelease (resMeasurementsMutex); 80022e0: 4b48 ldr r3, [pc, #288] @ (8002404 ) 80022e2: 681b ldr r3, [r3, #0] 80022e4: 4618 mov r0, r3 80022e6: f012 f931 bl 801454c for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 80022ea: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022ee: 3301 adds r3, #1 80022f0: f887 305f strb.w r3, [r7, #95] @ 0x5f 80022f4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022f8: 2b00 cmp r3, #0 80022fa: f43f af13 beq.w 8002124 } } ++circBuffPos; 80022fe: 6e7b ldr r3, [r7, #100] @ 0x64 8002300: 3301 adds r3, #1 8002302: 667b str r3, [r7, #100] @ 0x64 circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002304: 6e7a ldr r2, [r7, #100] @ 0x64 8002306: 4b41 ldr r3, [pc, #260] @ (800240c ) 8002308: fba3 1302 umull r1, r3, r3, r2 800230c: 08d9 lsrs r1, r3, #3 800230e: 460b mov r3, r1 8002310: 009b lsls r3, r3, #2 8002312: 440b add r3, r1 8002314: 005b lsls r3, r3, #1 8002316: 1ad3 subs r3, r2, r3 8002318: 667b str r3, [r7, #100] @ 0x64 if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 800231a: 4b3d ldr r3, [pc, #244] @ (8002410 ) 800231c: 681b ldr r3, [r3, #0] 800231e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002322: 4618 mov r0, r3 8002324: f012 f8c7 bl 80144b6 8002328: 4603 mov r3, r0 800232a: 2b00 cmp r3, #0 800232c: d124 bne.n 8002378 uint8_t refIdx = 0; 800232e: 2300 movs r3, #0 8002330: f887 305d strb.w r3, [r7, #93] @ 0x5d for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 8002334: 2303 movs r3, #3 8002336: f887 305c strb.w r3, [r7, #92] @ 0x5c 800233a: e014 b.n 8002366 ILxRef[refIdx++] = adcData.adcDataBuffer[i]; 800233c: f897 205c ldrb.w r2, [r7, #92] @ 0x5c 8002340: f897 305d ldrb.w r3, [r7, #93] @ 0x5d 8002344: 1c59 adds r1, r3, #1 8002346: f887 105d strb.w r1, [r7, #93] @ 0x5d 800234a: 4619 mov r1, r3 800234c: 0053 lsls r3, r2, #1 800234e: 3368 adds r3, #104 @ 0x68 8002350: 443b add r3, r7 8002352: f833 2c60 ldrh.w r2, [r3, #-96] 8002356: 4b2f ldr r3, [pc, #188] @ (8002414 ) 8002358: f823 2011 strh.w r2, [r3, r1, lsl #1] for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 800235c: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 8002360: 3301 adds r3, #1 8002362: f887 305c strb.w r3, [r7, #92] @ 0x5c 8002366: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 800236a: 2b05 cmp r3, #5 800236c: d9e6 bls.n 800233c } osMutexRelease (ILxRefMutex); 800236e: 4b28 ldr r3, [pc, #160] @ (8002410 ) 8002370: 681b ldr r3, [r3, #0] 8002372: 4618 mov r0, r3 8002374: f012 f8ea bl 801454c } float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8002378: 8abb ldrh r3, [r7, #20] 800237a: ee07 3a90 vmov s15, r3 800237e: eeb8 7be7 vcvt.f64.s32 d7, s15 8002382: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002386: ee27 6b06 vmul.f64 d6, d7, d6 800238a: ed9f 5b13 vldr d5, [pc, #76] @ 80023d8 800238e: ee86 7b05 vdiv.f64 d7, d6, d5 8002392: ed9f 6b15 vldr d6, [pc, #84] @ 80023e8 8002396: ee27 7b06 vmul.f64 d7, d7, d6 800239a: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 800239e: ee37 7b06 vadd.f64 d7, d7, d6 80023a2: eef7 7bc7 vcvt.f32.f64 s15, d7 80023a6: edc7 7a16 vstr s15, [r7, #88] @ 0x58 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80023aa: 4b1b ldr r3, [pc, #108] @ (8002418 ) 80023ac: 681b ldr r3, [r3, #0] 80023ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80023b2: 4618 mov r0, r3 80023b4: f012 f87f bl 80144b6 80023b8: 4603 mov r3, r0 80023ba: 2b00 cmp r3, #0 80023bc: f47f ae86 bne.w 80020cc sensorsInfo.fanVoltage = fanFBVoltage; 80023c0: 4a16 ldr r2, [pc, #88] @ (800241c ) 80023c2: 6dbb ldr r3, [r7, #88] @ 0x58 80023c4: 6093 str r3, [r2, #8] osMutexRelease (sensorsInfoMutex); 80023c6: 4b14 ldr r3, [pc, #80] @ (8002418 ) 80023c8: 681b ldr r3, [r3, #0] 80023ca: 4618 mov r0, r3 80023cc: f012 f8be bl 801454c while (pdTRUE) { 80023d0: e67c b.n 80020cc 80023d2: bf00 nop 80023d4: f3af 8000 nop.w 80023d8: 00000000 .word 0x00000000 80023dc: 40efffe0 .word 0x40efffe0 80023e0: f5c28f5c .word 0xf5c28f5c 80023e4: 401e5c28 .word 0x401e5c28 80023e8: 66666666 .word 0x66666666 80023ec: c0116666 .word 0xc0116666 80023f0: 24000800 .word 0x24000800 80023f4: 24000814 .word 0x24000814 80023f8: 24000030 .word 0x24000030 80023fc: 453b8000 .word 0x453b8000 8002400: 24000000 .word 0x24000000 8002404: 24000818 .word 0x24000818 8002408: 24000824 .word 0x24000824 800240c: cccccccd .word 0xcccccccd 8002410: 24000820 .word 0x24000820 8002414: 2400089c .word 0x2400089c 8002418: 2400081c .word 0x2400081c 800241c: 24000860 .word 0x24000860 08002420 : } } } void ADC2MeasTask (void* arg) { 8002420: b580 push {r7, lr} 8002422: b09c sub sp, #112 @ 0x70 8002424: af00 add r7, sp, #0 8002426: 6078 str r0, [r7, #4] float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN] = { 0 }; 8002428: f107 0334 add.w r3, r7, #52 @ 0x34 800242c: 2228 movs r2, #40 @ 0x28 800242e: 2100 movs r1, #0 8002430: 4618 mov r0, r3 8002432: f015 ff69 bl 8018308 float rms[CURRENTS_COUNT] = { 0 }; 8002436: f04f 0300 mov.w r3, #0 800243a: 633b str r3, [r7, #48] @ 0x30 ADC2_Data adcData = { 0 }; 800243c: f107 0310 add.w r3, r7, #16 8002440: 2220 movs r2, #32 8002442: 2100 movs r1, #0 8002444: 4618 mov r0, r3 8002446: f015 ff5f bl 8018308 uint32_t circBuffPos = 0; 800244a: 2300 movs r3, #0 800244c: 66fb str r3, [r7, #108] @ 0x6c float gainCorrection = 1.0; 800244e: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8002452: 66bb str r3, [r7, #104] @ 0x68 while (pdTRUE) { osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever); 8002454: 4baa ldr r3, [pc, #680] @ (8002700 ) 8002456: 6818 ldr r0, [r3, #0] 8002458: f107 0110 add.w r1, r7, #16 800245c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002460: 2200 movs r2, #0 8002462: f012 f983 bl 801476c if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8002466: 4ba7 ldr r3, [pc, #668] @ (8002704 ) 8002468: 681b ldr r3, [r3, #0] 800246a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800246e: 4618 mov r0, r3 8002470: f012 f821 bl 80144b6 8002474: 4603 mov r3, r0 8002476: 2b00 cmp r3, #0 8002478: d10c bne.n 8002494 gainCorrection = (float)vRefmV; 800247a: 4ba3 ldr r3, [pc, #652] @ (8002708 ) 800247c: 681b ldr r3, [r3, #0] 800247e: ee07 3a90 vmov s15, r3 8002482: eef8 7a67 vcvt.f32.u32 s15, s15 8002486: edc7 7a1a vstr s15, [r7, #104] @ 0x68 osMutexRelease (vRefmVMutex); 800248a: 4b9e ldr r3, [pc, #632] @ (8002704 ) 800248c: 681b ldr r3, [r3, #0] 800248e: 4618 mov r0, r3 8002490: f012 f85c bl 801454c } gainCorrection = gainCorrection / EXT_VREF_mV; 8002494: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8002498: eddf 6a9c vldr s13, [pc, #624] @ 800270c 800249c: eec7 7a26 vdiv.f32 s15, s14, s13 80024a0: edc7 7a1a vstr s15, [r7, #104] @ 0x68 float ref[CURRENTS_COUNT] = { 0 }; 80024a4: f04f 0300 mov.w r3, #0 80024a8: 60fb str r3, [r7, #12] if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 80024aa: 4b99 ldr r3, [pc, #612] @ (8002710 ) 80024ac: 681b ldr r3, [r3, #0] 80024ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80024b2: 4618 mov r0, r3 80024b4: f011 ffff bl 80144b6 80024b8: 4603 mov r3, r0 80024ba: 2b00 cmp r3, #0 80024bc: d122 bne.n 8002504 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80024be: 2300 movs r3, #0 80024c0: f887 3067 strb.w r3, [r7, #103] @ 0x67 80024c4: e015 b.n 80024f2 ref[i] = (float)ILxRef[i]; 80024c6: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024ca: 4a92 ldr r2, [pc, #584] @ (8002714 ) 80024cc: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 80024d0: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024d4: ee07 2a90 vmov s15, r2 80024d8: eef8 7a67 vcvt.f32.u32 s15, s15 80024dc: 009b lsls r3, r3, #2 80024de: 3370 adds r3, #112 @ 0x70 80024e0: 443b add r3, r7 80024e2: 3b64 subs r3, #100 @ 0x64 80024e4: edc3 7a00 vstr s15, [r3] for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80024e8: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024ec: 3301 adds r3, #1 80024ee: f887 3067 strb.w r3, [r7, #103] @ 0x67 80024f2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024f6: 2b00 cmp r3, #0 80024f8: d0e5 beq.n 80024c6 } osMutexRelease (ILxRefMutex); 80024fa: 4b85 ldr r3, [pc, #532] @ (8002710 ) 80024fc: 681b ldr r3, [r3, #0] 80024fe: 4618 mov r0, r3 8002500: f012 f824 bl 801454c } for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8002504: 2300 movs r3, #0 8002506: f887 3066 strb.w r3, [r7, #102] @ 0x66 800250a: e0db b.n 80026c4 float adcVal = (float)adcData.adcDataBuffer[i]; 800250c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002510: 005b lsls r3, r3, #1 8002512: 3370 adds r3, #112 @ 0x70 8002514: 443b add r3, r7 8002516: f833 3c60 ldrh.w r3, [r3, #-96] 800251a: ee07 3a90 vmov s15, r3 800251e: eef8 7a67 vcvt.f32.u32 s15, s15 8002522: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float val = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8002526: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800252a: 009b lsls r3, r3, #2 800252c: 3370 adds r3, #112 @ 0x70 800252e: 443b add r3, r7 8002530: 3b64 subs r3, #100 @ 0x64 8002532: edd3 7a00 vldr s15, [r3] 8002536: ed97 7a18 vldr s14, [r7, #96] @ 0x60 800253a: ee77 7a67 vsub.f32 s15, s14, s15 800253e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002542: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002546: ee27 6b06 vmul.f64 d6, d7, d6 800254a: ed9f 5b69 vldr d5, [pc, #420] @ 80026f0 800254e: ee86 7b05 vdiv.f64 d7, d6, d5 8002552: ed9f 6b69 vldr d6, [pc, #420] @ 80026f8 8002556: ee27 6b06 vmul.f64 d6, d7, d6 800255a: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800255e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002562: ee26 6b07 vmul.f64 d6, d6, d7 8002566: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800256a: 4a6b ldr r2, [pc, #428] @ (8002718 ) 800256c: 00db lsls r3, r3, #3 800256e: 4413 add r3, r2 8002570: edd3 7a00 vldr s15, [r3] 8002574: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002578: ee26 6b07 vmul.f64 d6, d6, d7 800257c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002580: 4a65 ldr r2, [pc, #404] @ (8002718 ) 8002582: 00db lsls r3, r3, #3 8002584: 4413 add r3, r2 8002586: 3304 adds r3, #4 8002588: edd3 7a00 vldr s15, [r3] 800258c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002590: ee36 7b07 vadd.f64 d7, d6, d7 8002594: eef7 7bc7 vcvt.f32.f64 s15, d7 8002598: edc7 7a17 vstr s15, [r7, #92] @ 0x5c circBuffer[i][circBuffPos] = val; 800259c: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80025a0: 4613 mov r3, r2 80025a2: 009b lsls r3, r3, #2 80025a4: 4413 add r3, r2 80025a6: 005b lsls r3, r3, #1 80025a8: 6efa ldr r2, [r7, #108] @ 0x6c 80025aa: 4413 add r3, r2 80025ac: 009b lsls r3, r3, #2 80025ae: 3370 adds r3, #112 @ 0x70 80025b0: 443b add r3, r7 80025b2: 3b3c subs r3, #60 @ 0x3c 80025b4: 6dfa ldr r2, [r7, #92] @ 0x5c 80025b6: 601a str r2, [r3, #0] rms[i] = 0.0; 80025b8: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025bc: 009b lsls r3, r3, #2 80025be: 3370 adds r3, #112 @ 0x70 80025c0: 443b add r3, r7 80025c2: 3b40 subs r3, #64 @ 0x40 80025c4: f04f 0200 mov.w r2, #0 80025c8: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80025ca: 2300 movs r3, #0 80025cc: f887 3065 strb.w r3, [r7, #101] @ 0x65 80025d0: e025 b.n 800261e rms[i] += circBuffer[i][c]; 80025d2: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025d6: 009b lsls r3, r3, #2 80025d8: 3370 adds r3, #112 @ 0x70 80025da: 443b add r3, r7 80025dc: 3b40 subs r3, #64 @ 0x40 80025de: ed93 7a00 vldr s14, [r3] 80025e2: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80025e6: f897 1065 ldrb.w r1, [r7, #101] @ 0x65 80025ea: 4613 mov r3, r2 80025ec: 009b lsls r3, r3, #2 80025ee: 4413 add r3, r2 80025f0: 005b lsls r3, r3, #1 80025f2: 440b add r3, r1 80025f4: 009b lsls r3, r3, #2 80025f6: 3370 adds r3, #112 @ 0x70 80025f8: 443b add r3, r7 80025fa: 3b3c subs r3, #60 @ 0x3c 80025fc: edd3 7a00 vldr s15, [r3] 8002600: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002604: ee77 7a27 vadd.f32 s15, s14, s15 8002608: 009b lsls r3, r3, #2 800260a: 3370 adds r3, #112 @ 0x70 800260c: 443b add r3, r7 800260e: 3b40 subs r3, #64 @ 0x40 8002610: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8002614: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002618: 3301 adds r3, #1 800261a: f887 3065 strb.w r3, [r7, #101] @ 0x65 800261e: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002622: 2b09 cmp r3, #9 8002624: d9d5 bls.n 80025d2 } rms[i] = rms[i] / CIRC_BUFF_LEN; 8002626: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800262a: 009b lsls r3, r3, #2 800262c: 3370 adds r3, #112 @ 0x70 800262e: 443b add r3, r7 8002630: 3b40 subs r3, #64 @ 0x40 8002632: ed93 7a00 vldr s14, [r3] 8002636: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800263a: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 800263e: eec7 7a26 vdiv.f32 s15, s14, s13 8002642: 009b lsls r3, r3, #2 8002644: 3370 adds r3, #112 @ 0x70 8002646: 443b add r3, r7 8002648: 3b40 subs r3, #64 @ 0x40 800264a: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800264e: 4b33 ldr r3, [pc, #204] @ (800271c ) 8002650: 681b ldr r3, [r3, #0] 8002652: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002656: 4618 mov r0, r3 8002658: f011 ff2d bl 80144b6 800265c: 4603 mov r3, r0 800265e: 2b00 cmp r3, #0 8002660: d12b bne.n 80026ba if (resMeasurements.currentPeak[i] < val) { 8002662: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002666: 4a2e ldr r2, [pc, #184] @ (8002720 ) 8002668: 3308 adds r3, #8 800266a: 009b lsls r3, r3, #2 800266c: 4413 add r3, r2 800266e: 3304 adds r3, #4 8002670: edd3 7a00 vldr s15, [r3] 8002674: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8002678: eeb4 7ae7 vcmpe.f32 s14, s15 800267c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002680: dd08 ble.n 8002694 resMeasurements.currentPeak[i] = val; 8002682: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002686: 4a26 ldr r2, [pc, #152] @ (8002720 ) 8002688: 3308 adds r3, #8 800268a: 009b lsls r3, r3, #2 800268c: 4413 add r3, r2 800268e: 3304 adds r3, #4 8002690: 6dfa ldr r2, [r7, #92] @ 0x5c 8002692: 601a str r2, [r3, #0] } resMeasurements.currentRMS[i] = rms[i]; 8002694: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002698: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800269c: 0092 lsls r2, r2, #2 800269e: 3270 adds r2, #112 @ 0x70 80026a0: 443a add r2, r7 80026a2: 3a40 subs r2, #64 @ 0x40 80026a4: 6812 ldr r2, [r2, #0] 80026a6: 491e ldr r1, [pc, #120] @ (8002720 ) 80026a8: 3306 adds r3, #6 80026aa: 009b lsls r3, r3, #2 80026ac: 440b add r3, r1 80026ae: 601a str r2, [r3, #0] osMutexRelease (resMeasurementsMutex); 80026b0: 4b1a ldr r3, [pc, #104] @ (800271c ) 80026b2: 681b ldr r3, [r3, #0] 80026b4: 4618 mov r0, r3 80026b6: f011 ff49 bl 801454c for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80026ba: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80026be: 3301 adds r3, #1 80026c0: f887 3066 strb.w r3, [r7, #102] @ 0x66 80026c4: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80026c8: 2b00 cmp r3, #0 80026ca: f43f af1f beq.w 800250c } } ++circBuffPos; 80026ce: 6efb ldr r3, [r7, #108] @ 0x6c 80026d0: 3301 adds r3, #1 80026d2: 66fb str r3, [r7, #108] @ 0x6c circBuffPos = circBuffPos % CIRC_BUFF_LEN; 80026d4: 6efa ldr r2, [r7, #108] @ 0x6c 80026d6: 4b13 ldr r3, [pc, #76] @ (8002724 ) 80026d8: fba3 1302 umull r1, r3, r3, r2 80026dc: 08d9 lsrs r1, r3, #3 80026de: 460b mov r3, r1 80026e0: 009b lsls r3, r3, #2 80026e2: 440b add r3, r1 80026e4: 005b lsls r3, r3, #1 80026e6: 1ad3 subs r3, r2, r3 80026e8: 66fb str r3, [r7, #108] @ 0x6c while (pdTRUE) { 80026ea: e6b3 b.n 8002454 80026ec: f3af 8000 nop.w 80026f0: 00000000 .word 0x00000000 80026f4: 40efffe0 .word 0x40efffe0 80026f8: 83e425af .word 0x83e425af 80026fc: 401e4d9e .word 0x401e4d9e 8002700: 24000804 .word 0x24000804 8002704: 24000814 .word 0x24000814 8002708: 24000030 .word 0x24000030 800270c: 453b8000 .word 0x453b8000 8002710: 24000820 .word 0x24000820 8002714: 2400089c .word 0x2400089c 8002718: 24000018 .word 0x24000018 800271c: 24000818 .word 0x24000818 8002720: 24000824 .word 0x24000824 8002724: cccccccd .word 0xcccccccd 08002728 : } } void ADC3MeasTask (void* arg) { 8002728: b580 push {r7, lr} 800272a: b0bc sub sp, #240 @ 0xf0 800272c: af00 add r7, sp, #0 800272e: 6078 str r0, [r7, #4] float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002730: f107 03a4 add.w r3, r7, #164 @ 0xa4 8002734: 2228 movs r2, #40 @ 0x28 8002736: 2100 movs r1, #0 8002738: 4618 mov r0, r3 800273a: f015 fde5 bl 8018308 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 800273e: f107 037c add.w r3, r7, #124 @ 0x7c 8002742: 2228 movs r2, #40 @ 0x28 8002744: 2100 movs r1, #0 8002746: 4618 mov r0, r3 8002748: f015 fdde bl 8018308 float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800274c: f107 0354 add.w r3, r7, #84 @ 0x54 8002750: 2228 movs r2, #40 @ 0x28 8002752: 2100 movs r1, #0 8002754: 4618 mov r0, r3 8002756: f015 fdd7 bl 8018308 float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800275a: f107 032c add.w r3, r7, #44 @ 0x2c 800275e: 2228 movs r2, #40 @ 0x28 8002760: 2100 movs r1, #0 8002762: 4618 mov r0, r3 8002764: f015 fdd0 bl 8018308 uint32_t circBuffPos = 0; 8002768: 2300 movs r3, #0 800276a: f8c7 30ec str.w r3, [r7, #236] @ 0xec ADC3_Data adcData = { 0 }; 800276e: f107 030c add.w r3, r7, #12 8002772: 2220 movs r2, #32 8002774: 2100 movs r1, #0 8002776: 4618 mov r0, r3 8002778: f015 fdc6 bl 8018308 while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 800277c: 4bc2 ldr r3, [pc, #776] @ (8002a88 ) 800277e: 6818 ldr r0, [r3, #0] 8002780: f107 010c add.w r1, r7, #12 8002784: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002788: 2200 movs r2, #0 800278a: f011 ffef bl 801476c uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 800278e: 4bbf ldr r3, [pc, #764] @ (8002a8c ) 8002790: 881b ldrh r3, [r3, #0] 8002792: 461a mov r2, r3 8002794: f640 43e4 movw r3, #3300 @ 0xce4 8002798: fb02 f303 mul.w r3, r2, r3 800279c: 8aba ldrh r2, [r7, #20] 800279e: fbb3 f3f2 udiv r3, r3, r2 80027a2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80027a6: 4bba ldr r3, [pc, #744] @ (8002a90 ) 80027a8: 681b ldr r3, [r3, #0] 80027aa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80027ae: 4618 mov r0, r3 80027b0: f011 fe81 bl 80144b6 80027b4: 4603 mov r3, r0 80027b6: 2b00 cmp r3, #0 80027b8: d108 bne.n 80027cc vRefmV = vRef; 80027ba: 4ab6 ldr r2, [pc, #728] @ (8002a94 ) 80027bc: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80027c0: 6013 str r3, [r2, #0] osMutexRelease (vRefmVMutex); 80027c2: 4bb3 ldr r3, [pc, #716] @ (8002a90 ) 80027c4: 681b ldr r3, [r3, #0] 80027c6: 4618 mov r0, r3 80027c8: f011 fec0 bl 801454c } float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80027cc: 8a3b ldrh r3, [r7, #16] 80027ce: ee07 3a90 vmov s15, r3 80027d2: eeb8 7be7 vcvt.f64.s32 d7, s15 80027d6: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80027da: ee27 6b06 vmul.f64 d6, d7, d6 80027de: ed9f 5ba2 vldr d5, [pc, #648] @ 8002a68 80027e2: ee86 7b05 vdiv.f64 d7, d6, d5 80027e6: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 80027ea: ee27 6b06 vmul.f64 d6, d7, d6 80027ee: ed9f 5ba0 vldr d5, [pc, #640] @ 8002a70 80027f2: ee86 7b05 vdiv.f64 d7, d6, d5 80027f6: eef7 7bc7 vcvt.f32.f64 s15, d7 80027fa: edc7 7a34 vstr s15, [r7, #208] @ 0xd0 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 80027fe: 8a7b ldrh r3, [r7, #18] 8002800: ee07 3a90 vmov s15, r3 8002804: eeb8 7be7 vcvt.f64.s32 d7, s15 8002808: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800280c: ee27 6b06 vmul.f64 d6, d7, d6 8002810: ed9f 5b95 vldr d5, [pc, #596] @ 8002a68 8002814: ee86 7b05 vdiv.f64 d7, d6, d5 8002818: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 800281c: ee27 6b06 vmul.f64 d6, d7, d6 8002820: ed9f 5b93 vldr d5, [pc, #588] @ 8002a70 8002824: ee86 7b05 vdiv.f64 d7, d6, d5 8002828: eef7 7bc7 vcvt.f32.f64 s15, d7 800282c: edc7 7a33 vstr s15, [r7, #204] @ 0xcc motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 8002830: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002834: 009b lsls r3, r3, #2 8002836: 33f0 adds r3, #240 @ 0xf0 8002838: 443b add r3, r7 800283a: 3b4c subs r3, #76 @ 0x4c 800283c: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8002840: 601a str r2, [r3, #0] motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 8002842: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002846: 009b lsls r3, r3, #2 8002848: 33f0 adds r3, #240 @ 0xf0 800284a: 443b add r3, r7 800284c: 3b74 subs r3, #116 @ 0x74 800284e: f8d7 20cc ldr.w r2, [r7, #204] @ 0xcc 8002852: 601a str r2, [r3, #0] pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8002854: 89bb ldrh r3, [r7, #12] 8002856: ee07 3a90 vmov s15, r3 800285a: eeb8 7be7 vcvt.f64.s32 d7, s15 800285e: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002862: ee27 6b06 vmul.f64 d6, d7, d6 8002866: ed9f 5b80 vldr d5, [pc, #512] @ 8002a68 800286a: ee86 7b05 vdiv.f64 d7, d6, d5 800286e: ed9f 6b82 vldr d6, [pc, #520] @ 8002a78 8002872: ee27 7b06 vmul.f64 d7, d7, d6 8002876: ed9f 6b82 vldr d6, [pc, #520] @ 8002a80 800287a: ee37 7b46 vsub.f64 d7, d7, d6 800287e: eef7 7bc7 vcvt.f32.f64 s15, d7 8002882: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002886: 009b lsls r3, r3, #2 8002888: 33f0 adds r3, #240 @ 0xf0 800288a: 443b add r3, r7 800288c: 3b9c subs r3, #156 @ 0x9c 800288e: edc3 7a00 vstr s15, [r3] pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 8002892: 89fb ldrh r3, [r7, #14] 8002894: ee07 3a90 vmov s15, r3 8002898: eeb8 7be7 vcvt.f64.s32 d7, s15 800289c: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80028a0: ee27 6b06 vmul.f64 d6, d7, d6 80028a4: ed9f 5b70 vldr d5, [pc, #448] @ 8002a68 80028a8: ee86 7b05 vdiv.f64 d7, d6, d5 80028ac: ed9f 6b72 vldr d6, [pc, #456] @ 8002a78 80028b0: ee27 7b06 vmul.f64 d7, d7, d6 80028b4: ed9f 6b72 vldr d6, [pc, #456] @ 8002a80 80028b8: ee37 7b46 vsub.f64 d7, d7, d6 80028bc: eef7 7bc7 vcvt.f32.f64 s15, d7 80028c0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80028c4: 009b lsls r3, r3, #2 80028c6: 33f0 adds r3, #240 @ 0xf0 80028c8: 443b add r3, r7 80028ca: 3bc4 subs r3, #196 @ 0xc4 80028cc: edc3 7a00 vstr s15, [r3] float motorXAveCurrent = 0; 80028d0: f04f 0300 mov.w r3, #0 80028d4: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 float motorYAveCurrent = 0; 80028d8: f04f 0300 mov.w r3, #0 80028dc: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 float pvT1AveTemp = 0; 80028e0: f04f 0300 mov.w r3, #0 80028e4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 float pvT2AveTemp = 0; 80028e8: f04f 0300 mov.w r3, #0 80028ec: f8c7 30dc str.w r3, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 80028f0: 2300 movs r3, #0 80028f2: f887 30db strb.w r3, [r7, #219] @ 0xdb 80028f6: e03c b.n 8002972 motorXAveCurrent += motorXSensCircBuffer[i]; 80028f8: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80028fc: 009b lsls r3, r3, #2 80028fe: 33f0 adds r3, #240 @ 0xf0 8002900: 443b add r3, r7 8002902: 3b4c subs r3, #76 @ 0x4c 8002904: edd3 7a00 vldr s15, [r3] 8002908: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800290c: ee77 7a27 vadd.f32 s15, s14, s15 8002910: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 8002914: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002918: 009b lsls r3, r3, #2 800291a: 33f0 adds r3, #240 @ 0xf0 800291c: 443b add r3, r7 800291e: 3b74 subs r3, #116 @ 0x74 8002920: edd3 7a00 vldr s15, [r3] 8002924: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 8002928: ee77 7a27 vadd.f32 s15, s14, s15 800292c: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 #ifdef PV_BOARD pvT1AveTemp += pvT1CircBuffer[i]; 8002930: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002934: 009b lsls r3, r3, #2 8002936: 33f0 adds r3, #240 @ 0xf0 8002938: 443b add r3, r7 800293a: 3b9c subs r3, #156 @ 0x9c 800293c: edd3 7a00 vldr s15, [r3] 8002940: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 8002944: ee77 7a27 vadd.f32 s15, s14, s15 8002948: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp += pvT2CircBuffer[i]; 800294c: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002950: 009b lsls r3, r3, #2 8002952: 33f0 adds r3, #240 @ 0xf0 8002954: 443b add r3, r7 8002956: 3bc4 subs r3, #196 @ 0xc4 8002958: edd3 7a00 vldr s15, [r3] 800295c: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 8002960: ee77 7a27 vadd.f32 s15, s14, s15 8002964: edc7 7a37 vstr s15, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002968: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800296c: 3301 adds r3, #1 800296e: f887 30db strb.w r3, [r7, #219] @ 0xdb 8002972: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002976: 2b09 cmp r3, #9 8002978: d9be bls.n 80028f8 #endif } motorXAveCurrent /= CIRC_BUFF_LEN; 800297a: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800297e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002982: eec7 7a26 vdiv.f32 s15, s14, s13 8002986: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent /= CIRC_BUFF_LEN; 800298a: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 800298e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002992: eec7 7a26 vdiv.f32 s15, s14, s13 8002996: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp /= CIRC_BUFF_LEN; 800299a: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 800299e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80029a2: eec7 7a26 vdiv.f32 s15, s14, s13 80029a6: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp /= CIRC_BUFF_LEN; 80029aa: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 80029ae: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80029b2: eec7 7a26 vdiv.f32 s15, s14, s13 80029b6: edc7 7a37 vstr s15, [r7, #220] @ 0xdc if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80029ba: 4b37 ldr r3, [pc, #220] @ (8002a98 ) 80029bc: 681b ldr r3, [r3, #0] 80029be: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80029c2: 4618 mov r0, r3 80029c4: f011 fd77 bl 80144b6 80029c8: 4603 mov r3, r0 80029ca: 2b00 cmp r3, #0 80029cc: d138 bne.n 8002a40 if (sensorsInfo.motorXStatus == 1) { 80029ce: 4b33 ldr r3, [pc, #204] @ (8002a9c ) 80029d0: 7d1b ldrb r3, [r3, #20] 80029d2: 2b01 cmp r3, #1 80029d4: d111 bne.n 80029fa sensorsInfo.motorXAveCurrent = motorXAveCurrent; 80029d6: 4a31 ldr r2, [pc, #196] @ (8002a9c ) 80029d8: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 80029dc: 6193 str r3, [r2, #24] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 80029de: 4b2f ldr r3, [pc, #188] @ (8002a9c ) 80029e0: edd3 7a08 vldr s15, [r3, #32] 80029e4: ed97 7a34 vldr s14, [r7, #208] @ 0xd0 80029e8: eeb4 7ae7 vcmpe.f32 s14, s15 80029ec: eef1 fa10 vmrs APSR_nzcv, fpscr 80029f0: dd03 ble.n 80029fa sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 80029f2: 4a2a ldr r2, [pc, #168] @ (8002a9c ) 80029f4: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 80029f8: 6213 str r3, [r2, #32] } } if (sensorsInfo.motorYStatus == 1) { 80029fa: 4b28 ldr r3, [pc, #160] @ (8002a9c ) 80029fc: 7d5b ldrb r3, [r3, #21] 80029fe: 2b01 cmp r3, #1 8002a00: d111 bne.n 8002a26 sensorsInfo.motorYAveCurrent = motorYAveCurrent; 8002a02: 4a26 ldr r2, [pc, #152] @ (8002a9c ) 8002a04: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002a08: 61d3 str r3, [r2, #28] if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 8002a0a: 4b24 ldr r3, [pc, #144] @ (8002a9c ) 8002a0c: edd3 7a09 vldr s15, [r3, #36] @ 0x24 8002a10: ed97 7a33 vldr s14, [r7, #204] @ 0xcc 8002a14: eeb4 7ae7 vcmpe.f32 s14, s15 8002a18: eef1 fa10 vmrs APSR_nzcv, fpscr 8002a1c: dd03 ble.n 8002a26 sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 8002a1e: 4a1f ldr r2, [pc, #124] @ (8002a9c ) 8002a20: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 8002a24: 6253 str r3, [r2, #36] @ 0x24 } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; 8002a26: 4a1d ldr r2, [pc, #116] @ (8002a9c ) 8002a28: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002a2c: 6013 str r3, [r2, #0] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 8002a2e: 4a1b ldr r2, [pc, #108] @ (8002a9c ) 8002a30: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8002a34: 6053 str r3, [r2, #4] osMutexRelease (sensorsInfoMutex); 8002a36: 4b18 ldr r3, [pc, #96] @ (8002a98 ) 8002a38: 681b ldr r3, [r3, #0] 8002a3a: 4618 mov r0, r3 8002a3c: f011 fd86 bl 801454c } ++circBuffPos; 8002a40: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002a44: 3301 adds r3, #1 8002a46: f8c7 30ec str.w r3, [r7, #236] @ 0xec circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002a4a: f8d7 20ec ldr.w r2, [r7, #236] @ 0xec 8002a4e: 4b14 ldr r3, [pc, #80] @ (8002aa0 ) 8002a50: fba3 1302 umull r1, r3, r3, r2 8002a54: 08d9 lsrs r1, r3, #3 8002a56: 460b mov r3, r1 8002a58: 009b lsls r3, r3, #2 8002a5a: 440b add r3, r1 8002a5c: 005b lsls r3, r3, #1 8002a5e: 1ad3 subs r3, r2, r3 8002a60: f8c7 30ec str.w r3, [r7, #236] @ 0xec while (pdTRUE) { 8002a64: e68a b.n 800277c 8002a66: bf00 nop 8002a68: 00000000 .word 0x00000000 8002a6c: 40efffe0 .word 0x40efffe0 8002a70: 3ad18d26 .word 0x3ad18d26 8002a74: 4020aaaa .word 0x4020aaaa 8002a78: aaa38226 .word 0xaaa38226 8002a7c: 4046aaaa .word 0x4046aaaa 8002a80: 00000000 .word 0x00000000 8002a84: 404f8000 .word 0x404f8000 8002a88: 24000808 .word 0x24000808 8002a8c: 1ff1e860 .word 0x1ff1e860 8002a90: 24000814 .word 0x24000814 8002a94: 24000030 .word 0x24000030 8002a98: 2400081c .word 0x2400081c 8002a9c: 24000860 .word 0x24000860 8002aa0: cccccccd .word 0xcccccccd 08002aa4 : } } void LimiterSwitchTask (void* arg) { 8002aa4: b580 push {r7, lr} 8002aa6: b08a sub sp, #40 @ 0x28 8002aa8: af06 add r7, sp, #24 8002aaa: 6078 str r0, [r7, #4] LimiterSwitchData limiterSwitchData = { 0 }; 8002aac: 2300 movs r3, #0 8002aae: 60bb str r3, [r7, #8] limiterSwitchData.gpioPin = GPIO_PIN_8; 8002ab0: f44f 7380 mov.w r3, #256 @ 0x100 8002ab4: 813b strh r3, [r7, #8] for (uint8_t i = 0; i < 6; i++) { 8002ab6: 2300 movs r3, #0 8002ab8: 73fb strb r3, [r7, #15] 8002aba: e02c b.n 8002b16 limiterSwitchData.pinState = HAL_GPIO_ReadPin (GPIOD, limiterSwitchData.gpioPin); 8002abc: 893b ldrh r3, [r7, #8] 8002abe: 4619 mov r1, r3 8002ac0: 48a5 ldr r0, [pc, #660] @ (8002d58 ) 8002ac2: f008 fd33 bl 800b52c 8002ac6: 4603 mov r3, r0 8002ac8: 72bb strb r3, [r7, #10] osMessageQueuePut (limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8002aca: 4ba4 ldr r3, [pc, #656] @ (8002d5c ) 8002acc: 6818 ldr r0, [r3, #0] 8002ace: f107 0108 add.w r1, r7, #8 8002ad2: 2300 movs r3, #0 8002ad4: 2200 movs r2, #0 8002ad6: f011 fde9 bl 80146ac limiterSwitchData.gpioPin = limiterSwitchData.gpioPin << 1; 8002ada: 893b ldrh r3, [r7, #8] 8002adc: 005b lsls r3, r3, #1 8002ade: b29b uxth r3, r3 8002ae0: 813b strh r3, [r7, #8] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002ae2: 4b9f ldr r3, [pc, #636] @ (8002d60 ) 8002ae4: 681b ldr r3, [r3, #0] 8002ae6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002aea: 4618 mov r0, r3 8002aec: f011 fce3 bl 80144b6 8002af0: 4603 mov r3, r0 8002af2: 2b00 cmp r3, #0 8002af4: d10c bne.n 8002b10 sensorsInfo.positionXWeak = 1; 8002af6: 4b9b ldr r3, [pc, #620] @ (8002d64 ) 8002af8: 2201 movs r2, #1 8002afa: f883 2038 strb.w r2, [r3, #56] @ 0x38 sensorsInfo.positionYWeak = 1; 8002afe: 4b99 ldr r3, [pc, #612] @ (8002d64 ) 8002b00: 2201 movs r2, #1 8002b02: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 8002b06: 4b96 ldr r3, [pc, #600] @ (8002d60 ) 8002b08: 681b ldr r3, [r3, #0] 8002b0a: 4618 mov r0, r3 8002b0c: f011 fd1e bl 801454c for (uint8_t i = 0; i < 6; i++) { 8002b10: 7bfb ldrb r3, [r7, #15] 8002b12: 3301 adds r3, #1 8002b14: 73fb strb r3, [r7, #15] 8002b16: 7bfb ldrb r3, [r7, #15] 8002b18: 2b05 cmp r3, #5 8002b1a: d9cf bls.n 8002abc } } while (pdTRUE) { osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002b1c: 4b8f ldr r3, [pc, #572] @ (8002d5c ) 8002b1e: 6818 ldr r0, [r3, #0] 8002b20: f107 0108 add.w r1, r7, #8 8002b24: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002b28: 2200 movs r2, #0 8002b2a: f011 fe1f bl 801476c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002b2e: 4b8c ldr r3, [pc, #560] @ (8002d60 ) 8002b30: 681b ldr r3, [r3, #0] 8002b32: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002b36: 4618 mov r0, r3 8002b38: f011 fcbd bl 80144b6 8002b3c: 4603 mov r3, r0 8002b3e: 2b00 cmp r3, #0 8002b40: d1ec bne.n 8002b1c switch (limiterSwitchData.gpioPin) { 8002b42: 893b ldrh r3, [r7, #8] 8002b44: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002b48: f000 8094 beq.w 8002c74 8002b4c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002b50: f300 80a8 bgt.w 8002ca4 8002b54: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002b58: d075 beq.n 8002c46 8002b5a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002b5e: f300 80a1 bgt.w 8002ca4 8002b62: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002b66: d057 beq.n 8002c18 8002b68: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002b6c: f300 809a bgt.w 8002ca4 8002b70: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b74: d039 beq.n 8002bea 8002b76: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b7a: f300 8093 bgt.w 8002ca4 8002b7e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002b82: d003 beq.n 8002b8c 8002b84: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002b88: d017 beq.n 8002bba { sensorsInfo.currentXPosition = 0; sensorsInfo.positionXWeak = 0; } break; default: break; 8002b8a: e08b b.n 8002ca4 sensorsInfo.limitYSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002b8c: 7abb ldrb r3, [r7, #10] 8002b8e: 2b01 cmp r3, #1 8002b90: bf0c ite eq 8002b92: 2301 moveq r3, #1 8002b94: 2300 movne r3, #0 8002b96: b2db uxtb r3, r3 8002b98: 461a mov r2, r3 8002b9a: 4b72 ldr r3, [pc, #456] @ (8002d64 ) 8002b9c: f883 202d strb.w r2, [r3, #45] @ 0x2d if (sensorsInfo.limitYSwitchCenter == 1) 8002ba0: 4b70 ldr r3, [pc, #448] @ (8002d64 ) 8002ba2: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 8002ba6: 2b01 cmp r3, #1 8002ba8: d17e bne.n 8002ca8 sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE; 8002baa: 4b6e ldr r3, [pc, #440] @ (8002d64 ) 8002bac: 4a6e ldr r2, [pc, #440] @ (8002d68 ) 8002bae: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002bb0: 4b6c ldr r3, [pc, #432] @ (8002d64 ) 8002bb2: 2200 movs r2, #0 8002bb4: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002bb8: e076 b.n 8002ca8 sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002bba: 7abb ldrb r3, [r7, #10] 8002bbc: 2b01 cmp r3, #1 8002bbe: bf0c ite eq 8002bc0: 2301 moveq r3, #1 8002bc2: 2300 movne r3, #0 8002bc4: b2db uxtb r3, r3 8002bc6: 461a mov r2, r3 8002bc8: 4b66 ldr r3, [pc, #408] @ (8002d64 ) 8002bca: f883 202c strb.w r2, [r3, #44] @ 0x2c if (sensorsInfo.limitYSwitchDown == 1) 8002bce: 4b65 ldr r3, [pc, #404] @ (8002d64 ) 8002bd0: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002bd4: 2b01 cmp r3, #1 8002bd6: d169 bne.n 8002cac sensorsInfo.currentYPosition = 0; 8002bd8: 4b62 ldr r3, [pc, #392] @ (8002d64 ) 8002bda: f04f 0200 mov.w r2, #0 8002bde: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002be0: 4b60 ldr r3, [pc, #384] @ (8002d64 ) 8002be2: 2200 movs r2, #0 8002be4: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002be8: e060 b.n 8002cac sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002bea: 7abb ldrb r3, [r7, #10] 8002bec: 2b01 cmp r3, #1 8002bee: bf0c ite eq 8002bf0: 2301 moveq r3, #1 8002bf2: 2300 movne r3, #0 8002bf4: b2db uxtb r3, r3 8002bf6: 461a mov r2, r3 8002bf8: 4b5a ldr r3, [pc, #360] @ (8002d64 ) 8002bfa: f883 202a strb.w r2, [r3, #42] @ 0x2a if (sensorsInfo.limitXSwitchCenter == 1) 8002bfe: 4b59 ldr r3, [pc, #356] @ (8002d64 ) 8002c00: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 8002c04: 2b01 cmp r3, #1 8002c06: d153 bne.n 8002cb0 sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE; 8002c08: 4b56 ldr r3, [pc, #344] @ (8002d64 ) 8002c0a: 4a57 ldr r2, [pc, #348] @ (8002d68 ) 8002c0c: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c0e: 4b55 ldr r3, [pc, #340] @ (8002d64 ) 8002c10: 2200 movs r2, #0 8002c12: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002c16: e04b b.n 8002cb0 sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c18: 7abb ldrb r3, [r7, #10] 8002c1a: 2b01 cmp r3, #1 8002c1c: bf0c ite eq 8002c1e: 2301 moveq r3, #1 8002c20: 2300 movne r3, #0 8002c22: b2db uxtb r3, r3 8002c24: 461a mov r2, r3 8002c26: 4b4f ldr r3, [pc, #316] @ (8002d64 ) 8002c28: f883 202b strb.w r2, [r3, #43] @ 0x2b if (sensorsInfo.limitYSwitchUp == 1) 8002c2c: 4b4d ldr r3, [pc, #308] @ (8002d64 ) 8002c2e: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002c32: 2b01 cmp r3, #1 8002c34: d13e bne.n 8002cb4 sensorsInfo.currentYPosition = 100; 8002c36: 4b4b ldr r3, [pc, #300] @ (8002d64 ) 8002c38: 4a4c ldr r2, [pc, #304] @ (8002d6c ) 8002c3a: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002c3c: 4b49 ldr r3, [pc, #292] @ (8002d64 ) 8002c3e: 2200 movs r2, #0 8002c40: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002c44: e036 b.n 8002cb4 sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c46: 7abb ldrb r3, [r7, #10] 8002c48: 2b01 cmp r3, #1 8002c4a: bf0c ite eq 8002c4c: 2301 moveq r3, #1 8002c4e: 2300 movne r3, #0 8002c50: b2db uxtb r3, r3 8002c52: 461a mov r2, r3 8002c54: 4b43 ldr r3, [pc, #268] @ (8002d64 ) 8002c56: f883 2028 strb.w r2, [r3, #40] @ 0x28 if (sensorsInfo.limitXSwitchUp == 1) 8002c5a: 4b42 ldr r3, [pc, #264] @ (8002d64 ) 8002c5c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002c60: 2b01 cmp r3, #1 8002c62: d129 bne.n 8002cb8 sensorsInfo.currentXPosition = 100; 8002c64: 4b3f ldr r3, [pc, #252] @ (8002d64 ) 8002c66: 4a41 ldr r2, [pc, #260] @ (8002d6c ) 8002c68: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c6a: 4b3e ldr r3, [pc, #248] @ (8002d64 ) 8002c6c: 2200 movs r2, #0 8002c6e: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002c72: e021 b.n 8002cb8 sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c74: 7abb ldrb r3, [r7, #10] 8002c76: 2b01 cmp r3, #1 8002c78: bf0c ite eq 8002c7a: 2301 moveq r3, #1 8002c7c: 2300 movne r3, #0 8002c7e: b2db uxtb r3, r3 8002c80: 461a mov r2, r3 8002c82: 4b38 ldr r3, [pc, #224] @ (8002d64 ) 8002c84: f883 2029 strb.w r2, [r3, #41] @ 0x29 if (sensorsInfo.limitXSwitchDown == 1) 8002c88: 4b36 ldr r3, [pc, #216] @ (8002d64 ) 8002c8a: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002c8e: 2b01 cmp r3, #1 8002c90: d114 bne.n 8002cbc sensorsInfo.currentXPosition = 0; 8002c92: 4b34 ldr r3, [pc, #208] @ (8002d64 ) 8002c94: f04f 0200 mov.w r2, #0 8002c98: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c9a: 4b32 ldr r3, [pc, #200] @ (8002d64 ) 8002c9c: 2200 movs r2, #0 8002c9e: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002ca2: e00b b.n 8002cbc default: break; 8002ca4: bf00 nop 8002ca6: e00a b.n 8002cbe break; 8002ca8: bf00 nop 8002caa: e008 b.n 8002cbe break; 8002cac: bf00 nop 8002cae: e006 b.n 8002cbe break; 8002cb0: bf00 nop 8002cb2: e004 b.n 8002cbe break; 8002cb4: bf00 nop 8002cb6: e002 b.n 8002cbe break; 8002cb8: bf00 nop 8002cba: e000 b.n 8002cbe break; 8002cbc: bf00 nop } if ((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) { 8002cbe: 4b29 ldr r3, [pc, #164] @ (8002d64 ) 8002cc0: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002cc4: 2b01 cmp r3, #1 8002cc6: d004 beq.n 8002cd2 8002cc8: 4b26 ldr r3, [pc, #152] @ (8002d64 ) 8002cca: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002cce: 2b01 cmp r3, #1 8002cd0: d118 bne.n 8002d04 sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8002cd2: 4b27 ldr r3, [pc, #156] @ (8002d70 ) 8002cd4: 681b ldr r3, [r3, #0] 8002cd6: 4a23 ldr r2, [pc, #140] @ (8002d64 ) 8002cd8: f892 2028 ldrb.w r2, [r2, #40] @ 0x28 8002cdc: 4921 ldr r1, [pc, #132] @ (8002d64 ) 8002cde: f891 1029 ldrb.w r1, [r1, #41] @ 0x29 8002ce2: 9104 str r1, [sp, #16] 8002ce4: 9203 str r2, [sp, #12] 8002ce6: 2200 movs r2, #0 8002ce8: 9202 str r2, [sp, #8] 8002cea: 2200 movs r2, #0 8002cec: 9201 str r2, [sp, #4] 8002cee: 9300 str r3, [sp, #0] 8002cf0: 2304 movs r3, #4 8002cf2: 2200 movs r2, #0 8002cf4: 491f ldr r1, [pc, #124] @ (8002d74 ) 8002cf6: 4820 ldr r0, [pc, #128] @ (8002d78 ) 8002cf8: f000 f982 bl 8003000 8002cfc: 4603 mov r3, r0 8002cfe: 461a mov r2, r3 8002d00: 4b18 ldr r3, [pc, #96] @ (8002d64 ) 8002d02: 751a strb r2, [r3, #20] } if ((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) { 8002d04: 4b17 ldr r3, [pc, #92] @ (8002d64 ) 8002d06: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002d0a: 2b01 cmp r3, #1 8002d0c: d004 beq.n 8002d18 8002d0e: 4b15 ldr r3, [pc, #84] @ (8002d64 ) 8002d10: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002d14: 2b01 cmp r3, #1 8002d16: d118 bne.n 8002d4a sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8002d18: 4b18 ldr r3, [pc, #96] @ (8002d7c ) 8002d1a: 681b ldr r3, [r3, #0] 8002d1c: 4a11 ldr r2, [pc, #68] @ (8002d64 ) 8002d1e: f892 202b ldrb.w r2, [r2, #43] @ 0x2b 8002d22: 4910 ldr r1, [pc, #64] @ (8002d64 ) 8002d24: f891 102c ldrb.w r1, [r1, #44] @ 0x2c 8002d28: 9104 str r1, [sp, #16] 8002d2a: 9203 str r2, [sp, #12] 8002d2c: 2200 movs r2, #0 8002d2e: 9202 str r2, [sp, #8] 8002d30: 2200 movs r2, #0 8002d32: 9201 str r2, [sp, #4] 8002d34: 9300 str r3, [sp, #0] 8002d36: 230c movs r3, #12 8002d38: 2208 movs r2, #8 8002d3a: 490e ldr r1, [pc, #56] @ (8002d74 ) 8002d3c: 480e ldr r0, [pc, #56] @ (8002d78 ) 8002d3e: f000 f95f bl 8003000 8002d42: 4603 mov r3, r0 8002d44: 461a mov r2, r3 8002d46: 4b07 ldr r3, [pc, #28] @ (8002d64 ) 8002d48: 755a strb r2, [r3, #21] } osMutexRelease (sensorsInfoMutex); 8002d4a: 4b05 ldr r3, [pc, #20] @ (8002d60 ) 8002d4c: 681b ldr r3, [r3, #0] 8002d4e: 4618 mov r0, r3 8002d50: f011 fbfc bl 801454c osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002d54: e6e2 b.n 8002b1c 8002d56: bf00 nop 8002d58: 58020c00 .word 0x58020c00 8002d5c: 2400080c .word 0x2400080c 8002d60: 2400081c .word 0x2400081c 8002d64: 24000860 .word 0x24000860 8002d68: 42480000 .word 0x42480000 8002d6c: 42c80000 .word 0x42c80000 8002d70: 24000744 .word 0x24000744 8002d74: 240007c0 .word 0x240007c0 8002d78: 240004d4 .word 0x240004d4 8002d7c: 24000774 .word 0x24000774 08002d80 : } } } void EncoderTask (void* arg) { 8002d80: b580 push {r7, lr} 8002d82: b086 sub sp, #24 8002d84: af00 add r7, sp, #0 8002d86: 6078 str r0, [r7, #4] EncoderData encoderData = { 0 }; 8002d88: 2300 movs r3, #0 8002d8a: 813b strh r3, [r7, #8] osMessageQueueId_t encoderQueue = (osMessageQueueId_t)arg; 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 617b str r3, [r7, #20] while (pdTRUE) { osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002d90: f107 0108 add.w r1, r7, #8 8002d94: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002d98: 2200 movs r2, #0 8002d9a: 6978 ldr r0, [r7, #20] 8002d9c: f011 fce6 bl 801476c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002da0: 4b4b ldr r3, [pc, #300] @ (8002ed0 ) 8002da2: 681b ldr r3, [r3, #0] 8002da4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002da8: 4618 mov r0, r3 8002daa: f011 fb84 bl 80144b6 8002dae: 4603 mov r3, r0 8002db0: 2b00 cmp r3, #0 8002db2: d1ed bne.n 8002d90 if (encoderData.axe == encoderAxeX) { 8002db4: 7a3b ldrb r3, [r7, #8] 8002db6: 2b00 cmp r3, #0 8002db8: d142 bne.n 8002e40 if (encoderData.direction == encoderCW) { 8002dba: 7a7b ldrb r3, [r7, #9] 8002dbc: 2b00 cmp r3, #0 8002dbe: d10a bne.n 8002dd6 sensorsInfo.pvEncoderX += 360.0 / ENCODER_X_IMP_PER_TURN; 8002dc0: 4b44 ldr r3, [pc, #272] @ (8002ed4 ) 8002dc2: edd3 7a03 vldr s15, [r3, #12] 8002dc6: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002dca: ee77 7a87 vadd.f32 s15, s15, s14 8002dce: 4b41 ldr r3, [pc, #260] @ (8002ed4 ) 8002dd0: edc3 7a03 vstr s15, [r3, #12] 8002dd4: e009 b.n 8002dea } else { sensorsInfo.pvEncoderX -= 360.0 / ENCODER_X_IMP_PER_TURN; 8002dd6: 4b3f ldr r3, [pc, #252] @ (8002ed4 ) 8002dd8: edd3 7a03 vldr s15, [r3, #12] 8002ddc: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002de0: ee77 7ac7 vsub.f32 s15, s15, s14 8002de4: 4b3b ldr r3, [pc, #236] @ (8002ed4 ) 8002de6: edc3 7a03 vstr s15, [r3, #12] } float currentPercentPos = 100 * sensorsInfo.pvEncoderX / MAX_X_AXE_ANGLE; 8002dea: 4b3a ldr r3, [pc, #232] @ (8002ed4 ) 8002dec: edd3 7a03 vldr s15, [r3, #12] 8002df0: ed9f 7a39 vldr s14, [pc, #228] @ 8002ed8 8002df4: ee27 7a87 vmul.f32 s14, s15, s14 8002df8: eddf 6a38 vldr s13, [pc, #224] @ 8002edc 8002dfc: eec7 7a26 vdiv.f32 s15, s14, s13 8002e00: edc7 7a03 vstr s15, [r7, #12] currentPercentPos = currentPercentPos < 0 ? 0 : currentPercentPos; 8002e04: edd7 7a03 vldr s15, [r7, #12] 8002e08: eef5 7ac0 vcmpe.f32 s15, #0.0 8002e0c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e10: d502 bpl.n 8002e18 8002e12: f04f 0300 mov.w r3, #0 8002e16: e000 b.n 8002e1a 8002e18: 68fb ldr r3, [r7, #12] 8002e1a: 60fb str r3, [r7, #12] sensorsInfo.currentXPosition = currentPercentPos > 100 ? 100 : currentPercentPos; 8002e1c: edd7 7a03 vldr s15, [r7, #12] 8002e20: ed9f 7a2d vldr s14, [pc, #180] @ 8002ed8 8002e24: eef4 7ac7 vcmpe.f32 s15, s14 8002e28: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e2c: dd01 ble.n 8002e32 8002e2e: 4b2c ldr r3, [pc, #176] @ (8002ee0 ) 8002e30: e000 b.n 8002e34 8002e32: 68fb ldr r3, [r7, #12] 8002e34: 4a27 ldr r2, [pc, #156] @ (8002ed4 ) 8002e36: 6313 str r3, [r2, #48] @ 0x30 DbgLEDToggle(DBG_LED2); 8002e38: 2020 movs r0, #32 8002e3a: f000 f877 bl 8002f2c 8002e3e: e041 b.n 8002ec4 } else { if (encoderData.direction == encoderCW) { 8002e40: 7a7b ldrb r3, [r7, #9] 8002e42: 2b00 cmp r3, #0 8002e44: d10a bne.n 8002e5c sensorsInfo.pvEncoderY += 360.0 / ENCODER_Y_IMP_PER_TURN; 8002e46: 4b23 ldr r3, [pc, #140] @ (8002ed4 ) 8002e48: edd3 7a04 vldr s15, [r3, #16] 8002e4c: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002e50: ee77 7a87 vadd.f32 s15, s15, s14 8002e54: 4b1f ldr r3, [pc, #124] @ (8002ed4 ) 8002e56: edc3 7a04 vstr s15, [r3, #16] 8002e5a: e009 b.n 8002e70 } else { sensorsInfo.pvEncoderY -= 360.0 / ENCODER_Y_IMP_PER_TURN; 8002e5c: 4b1d ldr r3, [pc, #116] @ (8002ed4 ) 8002e5e: edd3 7a04 vldr s15, [r3, #16] 8002e62: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002e66: ee77 7ac7 vsub.f32 s15, s15, s14 8002e6a: 4b1a ldr r3, [pc, #104] @ (8002ed4 ) 8002e6c: edc3 7a04 vstr s15, [r3, #16] } float currentPercentPos = 100 * sensorsInfo.pvEncoderY / MAX_X_AXE_ANGLE; 8002e70: 4b18 ldr r3, [pc, #96] @ (8002ed4 ) 8002e72: edd3 7a04 vldr s15, [r3, #16] 8002e76: ed9f 7a18 vldr s14, [pc, #96] @ 8002ed8 8002e7a: ee27 7a87 vmul.f32 s14, s15, s14 8002e7e: eddf 6a17 vldr s13, [pc, #92] @ 8002edc 8002e82: eec7 7a26 vdiv.f32 s15, s14, s13 8002e86: edc7 7a04 vstr s15, [r7, #16] currentPercentPos = currentPercentPos < 0 ? 0 : currentPercentPos; 8002e8a: edd7 7a04 vldr s15, [r7, #16] 8002e8e: eef5 7ac0 vcmpe.f32 s15, #0.0 8002e92: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e96: d502 bpl.n 8002e9e 8002e98: f04f 0300 mov.w r3, #0 8002e9c: e000 b.n 8002ea0 8002e9e: 693b ldr r3, [r7, #16] 8002ea0: 613b str r3, [r7, #16] sensorsInfo.currentXPosition = currentPercentPos > 100 ? 100 : currentPercentPos; 8002ea2: edd7 7a04 vldr s15, [r7, #16] 8002ea6: ed9f 7a0c vldr s14, [pc, #48] @ 8002ed8 8002eaa: eef4 7ac7 vcmpe.f32 s15, s14 8002eae: eef1 fa10 vmrs APSR_nzcv, fpscr 8002eb2: dd01 ble.n 8002eb8 8002eb4: 4b0a ldr r3, [pc, #40] @ (8002ee0 ) 8002eb6: e000 b.n 8002eba 8002eb8: 693b ldr r3, [r7, #16] 8002eba: 4a06 ldr r2, [pc, #24] @ (8002ed4 ) 8002ebc: 6313 str r3, [r2, #48] @ 0x30 DbgLEDToggle(DBG_LED3); 8002ebe: 2040 movs r0, #64 @ 0x40 8002ec0: f000 f834 bl 8002f2c } osMutexRelease (sensorsInfoMutex); 8002ec4: 4b02 ldr r3, [pc, #8] @ (8002ed0 ) 8002ec6: 681b ldr r3, [r3, #0] 8002ec8: 4618 mov r0, r3 8002eca: f011 fb3f bl 801454c osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002ece: e75f b.n 8002d90 8002ed0: 2400081c .word 0x2400081c 8002ed4: 24000860 .word 0x24000860 8002ed8: 42c80000 .word 0x42c80000 8002edc: 43b40000 .word 0x43b40000 8002ee0: 42c80000 .word 0x42c80000 08002ee4 : #include #include "peripherial.h" void DbgLEDOn (uint8_t ledNumber) { 8002ee4: b580 push {r7, lr} 8002ee6: b082 sub sp, #8 8002ee8: af00 add r7, sp, #0 8002eea: 4603 mov r3, r0 8002eec: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET); 8002eee: 79fb ldrb r3, [r7, #7] 8002ef0: b29b uxth r3, r3 8002ef2: 2201 movs r2, #1 8002ef4: 4619 mov r1, r3 8002ef6: 4803 ldr r0, [pc, #12] @ (8002f04 ) 8002ef8: f008 fb30 bl 800b55c } 8002efc: bf00 nop 8002efe: 3708 adds r7, #8 8002f00: 46bd mov sp, r7 8002f02: bd80 pop {r7, pc} 8002f04: 58020c00 .word 0x58020c00 08002f08 : void DbgLEDOff (uint8_t ledNumber) { 8002f08: b580 push {r7, lr} 8002f0a: b082 sub sp, #8 8002f0c: af00 add r7, sp, #0 8002f0e: 4603 mov r3, r0 8002f10: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET); 8002f12: 79fb ldrb r3, [r7, #7] 8002f14: b29b uxth r3, r3 8002f16: 2200 movs r2, #0 8002f18: 4619 mov r1, r3 8002f1a: 4803 ldr r0, [pc, #12] @ (8002f28 ) 8002f1c: f008 fb1e bl 800b55c } 8002f20: bf00 nop 8002f22: 3708 adds r7, #8 8002f24: 46bd mov sp, r7 8002f26: bd80 pop {r7, pc} 8002f28: 58020c00 .word 0x58020c00 08002f2c : void DbgLEDToggle (uint8_t ledNumber) { 8002f2c: b580 push {r7, lr} 8002f2e: b082 sub sp, #8 8002f30: af00 add r7, sp, #0 8002f32: 4603 mov r3, r0 8002f34: 71fb strb r3, [r7, #7] HAL_GPIO_TogglePin (GPIOD, ledNumber); 8002f36: 79fb ldrb r3, [r7, #7] 8002f38: b29b uxth r3, r3 8002f3a: 4619 mov r1, r3 8002f3c: 4803 ldr r0, [pc, #12] @ (8002f4c ) 8002f3e: f008 fb26 bl 800b58e } 8002f42: bf00 nop 8002f44: 3708 adds r7, #8 8002f46: 46bd mov sp, r7 8002f48: bd80 pop {r7, pc} 8002f4a: bf00 nop 8002f4c: 58020c00 .word 0x58020c00 08002f50 : void EnableCurrentSensors (void) { 8002f50: b580 push {r7, lr} 8002f52: af00 add r7, sp, #0 HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 8002f54: 2201 movs r2, #1 8002f56: f44f 4100 mov.w r1, #32768 @ 0x8000 8002f5a: 4802 ldr r0, [pc, #8] @ (8002f64 ) 8002f5c: f008 fafe bl 800b55c } 8002f60: bf00 nop 8002f62: bd80 pop {r7, pc} 8002f64: 58021000 .word 0x58021000 08002f68 : void DisableCurrentSensors (void) { HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { 8002f68: b580 push {r7, lr} 8002f6a: b084 sub sp, #16 8002f6c: af00 add r7, sp, #0 8002f6e: 4603 mov r3, r0 8002f70: 460a mov r2, r1 8002f72: 71fb strb r3, [r7, #7] 8002f74: 4613 mov r3, r2 8002f76: 71bb strb r3, [r7, #6] uint8_t gpioOffset = 0; 8002f78: 2300 movs r3, #0 8002f7a: 73fb strb r3, [r7, #15] switch (sensor) { 8002f7c: 79fb ldrb r3, [r7, #7] 8002f7e: 2b02 cmp r3, #2 8002f80: d00c beq.n 8002f9c 8002f82: 2b02 cmp r3, #2 8002f84: dc0d bgt.n 8002fa2 8002f86: 2b00 cmp r3, #0 8002f88: d002 beq.n 8002f90 8002f8a: 2b01 cmp r3, #1 8002f8c: d003 beq.n 8002f96 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; 8002f8e: e008 b.n 8002fa2 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; 8002f90: 2307 movs r3, #7 8002f92: 73fb strb r3, [r7, #15] 8002f94: e006 b.n 8002fa4 case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; 8002f96: 2309 movs r3, #9 8002f98: 73fb strb r3, [r7, #15] 8002f9a: e003 b.n 8002fa4 case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; 8002f9c: 230d movs r3, #13 8002f9e: 73fb strb r3, [r7, #15] 8002fa0: e000 b.n 8002fa4 default: break; 8002fa2: bf00 nop } if (gpioOffset > 0) { 8002fa4: 7bfb ldrb r3, [r7, #15] 8002fa6: 2b00 cmp r3, #0 8002fa8: d023 beq.n 8002ff2 uint16_t gain0Gpio = 1 << gpioOffset; 8002faa: 7bfb ldrb r3, [r7, #15] 8002fac: 2201 movs r2, #1 8002fae: fa02 f303 lsl.w r3, r2, r3 8002fb2: 81bb strh r3, [r7, #12] uint16_t gain1Gpio = 1 << (gpioOffset + 1); 8002fb4: 7bfb ldrb r3, [r7, #15] 8002fb6: 3301 adds r3, #1 8002fb8: 2201 movs r2, #1 8002fba: fa02 f303 lsl.w r3, r2, r3 8002fbe: 817b strh r3, [r7, #10] uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8002fc0: 79bb ldrb r3, [r7, #6] 8002fc2: b29b uxth r3, r3 8002fc4: f003 0301 and.w r3, r3, #1 8002fc8: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 8002fca: 893b ldrh r3, [r7, #8] 8002fcc: b2da uxtb r2, r3 8002fce: 89bb ldrh r3, [r7, #12] 8002fd0: 4619 mov r1, r3 8002fd2: 480a ldr r0, [pc, #40] @ (8002ffc ) 8002fd4: f008 fac2 bl 800b55c gpioState = (((uint16_t)gain) >> 1) & 0x0001; 8002fd8: 79bb ldrb r3, [r7, #6] 8002fda: 085b lsrs r3, r3, #1 8002fdc: b2db uxtb r3, r3 8002fde: f003 0301 and.w r3, r3, #1 8002fe2: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 8002fe4: 893b ldrh r3, [r7, #8] 8002fe6: b2da uxtb r2, r3 8002fe8: 897b ldrh r3, [r7, #10] 8002fea: 4619 mov r1, r3 8002fec: 4803 ldr r0, [pc, #12] @ (8002ffc ) 8002fee: f008 fab5 bl 800b55c } } 8002ff2: bf00 nop 8002ff4: 3710 adds r7, #16 8002ff6: 46bd mov sp, r7 8002ff8: bd80 pop {r7, pc} 8002ffa: bf00 nop 8002ffc: 58021000 .word 0x58021000 08003000 : uint8_t MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8003000: b580 push {r7, lr} 8003002: b088 sub sp, #32 8003004: af02 add r7, sp, #8 8003006: 60f8 str r0, [r7, #12] 8003008: 60b9 str r1, [r7, #8] 800300a: 4611 mov r1, r2 800300c: 461a mov r2, r3 800300e: 460b mov r3, r1 8003010: 71fb strb r3, [r7, #7] 8003012: 4613 mov r3, r2 8003014: 71bb strb r3, [r7, #6] uint32_t motorStatus = 0; 8003016: 2300 movs r3, #0 8003018: 617b str r3, [r7, #20] MotorDriverState setMotorState = HiZ; 800301a: 2300 movs r3, #0 800301c: 74fb strb r3, [r7, #19] HAL_TIM_PWM_Stop (htim, channel1); 800301e: 79fb ldrb r3, [r7, #7] 8003020: 4619 mov r1, r3 8003022: 68f8 ldr r0, [r7, #12] 8003024: f00c fca2 bl 800f96c HAL_TIM_PWM_Stop (htim, channel2); 8003028: 79bb ldrb r3, [r7, #6] 800302a: 4619 mov r1, r3 800302c: 68f8 ldr r0, [r7, #12] 800302e: f00c fc9d bl 800f96c if (motorTimerPeriod > 0) { 8003032: 6abb ldr r3, [r7, #40] @ 0x28 8003034: 2b00 cmp r3, #0 8003036: f340 808c ble.w 8003152 if (motorPWMPulse > 0) { 800303a: 6a7b ldr r3, [r7, #36] @ 0x24 800303c: 2b00 cmp r3, #0 800303e: dd2c ble.n 800309a // Forward if (switchLimiterUpStat == 0) { 8003040: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8003044: 2b00 cmp r3, #0 8003046: d11d bne.n 8003084 setMotorState = Forward; 8003048: 2301 movs r3, #1 800304a: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800304c: 79f9 ldrb r1, [r7, #7] 800304e: 79b8 ldrb r0, [r7, #6] 8003050: 6a7b ldr r3, [r7, #36] @ 0x24 8003052: ea83 72e3 eor.w r2, r3, r3, asr #31 8003056: eba2 72e3 sub.w r2, r2, r3, asr #31 800305a: 4613 mov r3, r2 800305c: 009b lsls r3, r3, #2 800305e: 4413 add r3, r2 8003060: 005b lsls r3, r3, #1 8003062: 9301 str r3, [sp, #4] 8003064: 7cfb ldrb r3, [r7, #19] 8003066: 9300 str r3, [sp, #0] 8003068: 4603 mov r3, r0 800306a: 460a mov r2, r1 800306c: 68b9 ldr r1, [r7, #8] 800306e: 68f8 ldr r0, [r7, #12] 8003070: f000 f8ff bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 8003074: 79fb ldrb r3, [r7, #7] 8003076: 4619 mov r1, r3 8003078: 68f8 ldr r0, [r7, #12] 800307a: f00c fb69 bl 800f750 motorStatus = 1; 800307e: 2301 movs r3, #1 8003080: 617b str r3, [r7, #20] 8003082: e004 b.n 800308e } else { HAL_TIM_PWM_Stop (htim, channel1); 8003084: 79fb ldrb r3, [r7, #7] 8003086: 4619 mov r1, r3 8003088: 68f8 ldr r0, [r7, #12] 800308a: f00c fc6f bl 800f96c } HAL_TIM_PWM_Stop (htim, channel2); 800308e: 79bb ldrb r3, [r7, #6] 8003090: 4619 mov r1, r3 8003092: 68f8 ldr r0, [r7, #12] 8003094: f00c fc6a bl 800f96c 8003098: e051 b.n 800313e } else if (motorPWMPulse < 0) { 800309a: 6a7b ldr r3, [r7, #36] @ 0x24 800309c: 2b00 cmp r3, #0 800309e: da2c bge.n 80030fa // Reverse if (switchLimiterDownStat == 0) { 80030a0: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 80030a4: 2b00 cmp r3, #0 80030a6: d11d bne.n 80030e4 setMotorState = Reverse; 80030a8: 2302 movs r3, #2 80030aa: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80030ac: 79f9 ldrb r1, [r7, #7] 80030ae: 79b8 ldrb r0, [r7, #6] 80030b0: 6a7b ldr r3, [r7, #36] @ 0x24 80030b2: ea83 72e3 eor.w r2, r3, r3, asr #31 80030b6: eba2 72e3 sub.w r2, r2, r3, asr #31 80030ba: 4613 mov r3, r2 80030bc: 009b lsls r3, r3, #2 80030be: 4413 add r3, r2 80030c0: 005b lsls r3, r3, #1 80030c2: 9301 str r3, [sp, #4] 80030c4: 7cfb ldrb r3, [r7, #19] 80030c6: 9300 str r3, [sp, #0] 80030c8: 4603 mov r3, r0 80030ca: 460a mov r2, r1 80030cc: 68b9 ldr r1, [r7, #8] 80030ce: 68f8 ldr r0, [r7, #12] 80030d0: f000 f8cf bl 8003272 HAL_TIM_PWM_Start (htim, channel2); 80030d4: 79bb ldrb r3, [r7, #6] 80030d6: 4619 mov r1, r3 80030d8: 68f8 ldr r0, [r7, #12] 80030da: f00c fb39 bl 800f750 motorStatus = 1; 80030de: 2301 movs r3, #1 80030e0: 617b str r3, [r7, #20] 80030e2: e004 b.n 80030ee } else { HAL_TIM_PWM_Stop (htim, channel2); 80030e4: 79bb ldrb r3, [r7, #6] 80030e6: 4619 mov r1, r3 80030e8: 68f8 ldr r0, [r7, #12] 80030ea: f00c fc3f bl 800f96c } HAL_TIM_PWM_Stop (htim, channel1); 80030ee: 79fb ldrb r3, [r7, #7] 80030f0: 4619 mov r1, r3 80030f2: 68f8 ldr r0, [r7, #12] 80030f4: f00c fc3a bl 800f96c 80030f8: e021 b.n 800313e } else { // Brake setMotorState = Brake; 80030fa: 2303 movs r3, #3 80030fc: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80030fe: 79f9 ldrb r1, [r7, #7] 8003100: 79b8 ldrb r0, [r7, #6] 8003102: 6a7b ldr r3, [r7, #36] @ 0x24 8003104: ea83 72e3 eor.w r2, r3, r3, asr #31 8003108: eba2 72e3 sub.w r2, r2, r3, asr #31 800310c: 4613 mov r3, r2 800310e: 009b lsls r3, r3, #2 8003110: 4413 add r3, r2 8003112: 005b lsls r3, r3, #1 8003114: 9301 str r3, [sp, #4] 8003116: 7cfb ldrb r3, [r7, #19] 8003118: 9300 str r3, [sp, #0] 800311a: 4603 mov r3, r0 800311c: 460a mov r2, r1 800311e: 68b9 ldr r1, [r7, #8] 8003120: 68f8 ldr r0, [r7, #12] 8003122: f000 f8a6 bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 8003126: 79fb ldrb r3, [r7, #7] 8003128: 4619 mov r1, r3 800312a: 68f8 ldr r0, [r7, #12] 800312c: f00c fb10 bl 800f750 HAL_TIM_PWM_Start (htim, channel2); 8003130: 79bb ldrb r3, [r7, #6] 8003132: 4619 mov r1, r3 8003134: 68f8 ldr r0, [r7, #12] 8003136: f00c fb0b bl 800f750 motorStatus = 0; 800313a: 2300 movs r3, #0 800313c: 617b str r3, [r7, #20] } osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 800313e: 6abb ldr r3, [r7, #40] @ 0x28 8003140: f44f 727a mov.w r2, #1000 @ 0x3e8 8003144: fb02 f303 mul.w r3, r2, r3 8003148: 4619 mov r1, r3 800314a: 6a38 ldr r0, [r7, #32] 800314c: f011 f8c8 bl 80142e0 8003150: e089 b.n 8003266 } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 8003152: 6abb ldr r3, [r7, #40] @ 0x28 8003154: 2b00 cmp r3, #0 8003156: d126 bne.n 80031a6 8003158: 6a7b ldr r3, [r7, #36] @ 0x24 800315a: 2b00 cmp r3, #0 800315c: d123 bne.n 80031a6 MotorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10); 800315e: 79f9 ldrb r1, [r7, #7] 8003160: 79b8 ldrb r0, [r7, #6] 8003162: 6a7b ldr r3, [r7, #36] @ 0x24 8003164: ea83 72e3 eor.w r2, r3, r3, asr #31 8003168: eba2 72e3 sub.w r2, r2, r3, asr #31 800316c: 4613 mov r3, r2 800316e: 009b lsls r3, r3, #2 8003170: 4413 add r3, r2 8003172: 005b lsls r3, r3, #1 8003174: 9301 str r3, [sp, #4] 8003176: 2300 movs r3, #0 8003178: 9300 str r3, [sp, #0] 800317a: 4603 mov r3, r0 800317c: 460a mov r2, r1 800317e: 68b9 ldr r1, [r7, #8] 8003180: 68f8 ldr r0, [r7, #12] 8003182: f000 f876 bl 8003272 HAL_TIM_PWM_Stop (htim, channel1); 8003186: 79fb ldrb r3, [r7, #7] 8003188: 4619 mov r1, r3 800318a: 68f8 ldr r0, [r7, #12] 800318c: f00c fbee bl 800f96c HAL_TIM_PWM_Stop (htim, channel2); 8003190: 79bb ldrb r3, [r7, #6] 8003192: 4619 mov r1, r3 8003194: 68f8 ldr r0, [r7, #12] 8003196: f00c fbe9 bl 800f96c osTimerStop (motorTimerHandle); 800319a: 6a38 ldr r0, [r7, #32] 800319c: f011 f8ce bl 801433c motorStatus = 0; 80031a0: 2300 movs r3, #0 80031a2: 617b str r3, [r7, #20] 80031a4: e05f b.n 8003266 } else if (motorTimerPeriod == -1) { 80031a6: 6abb ldr r3, [r7, #40] @ 0x28 80031a8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80031ac: d15b bne.n 8003266 if (motorPWMPulse > 0) { 80031ae: 6a7b ldr r3, [r7, #36] @ 0x24 80031b0: 2b00 cmp r3, #0 80031b2: dd2c ble.n 800320e // Forward if (switchLimiterUpStat == 0) { 80031b4: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 80031b8: 2b00 cmp r3, #0 80031ba: d11d bne.n 80031f8 setMotorState = Forward; 80031bc: 2301 movs r3, #1 80031be: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80031c0: 79f9 ldrb r1, [r7, #7] 80031c2: 79b8 ldrb r0, [r7, #6] 80031c4: 6a7b ldr r3, [r7, #36] @ 0x24 80031c6: ea83 72e3 eor.w r2, r3, r3, asr #31 80031ca: eba2 72e3 sub.w r2, r2, r3, asr #31 80031ce: 4613 mov r3, r2 80031d0: 009b lsls r3, r3, #2 80031d2: 4413 add r3, r2 80031d4: 005b lsls r3, r3, #1 80031d6: 9301 str r3, [sp, #4] 80031d8: 7cfb ldrb r3, [r7, #19] 80031da: 9300 str r3, [sp, #0] 80031dc: 4603 mov r3, r0 80031de: 460a mov r2, r1 80031e0: 68b9 ldr r1, [r7, #8] 80031e2: 68f8 ldr r0, [r7, #12] 80031e4: f000 f845 bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 80031e8: 79fb ldrb r3, [r7, #7] 80031ea: 4619 mov r1, r3 80031ec: 68f8 ldr r0, [r7, #12] 80031ee: f00c faaf bl 800f750 motorStatus = 1; 80031f2: 2301 movs r3, #1 80031f4: 617b str r3, [r7, #20] 80031f6: e004 b.n 8003202 } else { HAL_TIM_PWM_Stop (htim, channel1); 80031f8: 79fb ldrb r3, [r7, #7] 80031fa: 4619 mov r1, r3 80031fc: 68f8 ldr r0, [r7, #12] 80031fe: f00c fbb5 bl 800f96c } HAL_TIM_PWM_Stop (htim, channel2); 8003202: 79bb ldrb r3, [r7, #6] 8003204: 4619 mov r1, r3 8003206: 68f8 ldr r0, [r7, #12] 8003208: f00c fbb0 bl 800f96c 800320c: e02b b.n 8003266 } else { // Reverse if (switchLimiterDownStat == 0) { 800320e: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8003212: 2b00 cmp r3, #0 8003214: d11d bne.n 8003252 setMotorState = Reverse; 8003216: 2302 movs r3, #2 8003218: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800321a: 79f9 ldrb r1, [r7, #7] 800321c: 79b8 ldrb r0, [r7, #6] 800321e: 6a7b ldr r3, [r7, #36] @ 0x24 8003220: ea83 72e3 eor.w r2, r3, r3, asr #31 8003224: eba2 72e3 sub.w r2, r2, r3, asr #31 8003228: 4613 mov r3, r2 800322a: 009b lsls r3, r3, #2 800322c: 4413 add r3, r2 800322e: 005b lsls r3, r3, #1 8003230: 9301 str r3, [sp, #4] 8003232: 7cfb ldrb r3, [r7, #19] 8003234: 9300 str r3, [sp, #0] 8003236: 4603 mov r3, r0 8003238: 460a mov r2, r1 800323a: 68b9 ldr r1, [r7, #8] 800323c: 68f8 ldr r0, [r7, #12] 800323e: f000 f818 bl 8003272 HAL_TIM_PWM_Start (htim, channel2); 8003242: 79bb ldrb r3, [r7, #6] 8003244: 4619 mov r1, r3 8003246: 68f8 ldr r0, [r7, #12] 8003248: f00c fa82 bl 800f750 motorStatus = 1; 800324c: 2301 movs r3, #1 800324e: 617b str r3, [r7, #20] 8003250: e004 b.n 800325c } else { HAL_TIM_PWM_Stop (htim, channel2); 8003252: 79bb ldrb r3, [r7, #6] 8003254: 4619 mov r1, r3 8003256: 68f8 ldr r0, [r7, #12] 8003258: f00c fb88 bl 800f96c } HAL_TIM_PWM_Stop (htim, channel1); 800325c: 79fb ldrb r3, [r7, #7] 800325e: 4619 mov r1, r3 8003260: 68f8 ldr r0, [r7, #12] 8003262: f00c fb83 bl 800f96c } } return motorStatus; 8003266: 697b ldr r3, [r7, #20] 8003268: b2db uxtb r3, r3 } 800326a: 4618 mov r0, r3 800326c: 3718 adds r7, #24 800326e: 46bd mov sp, r7 8003270: bd80 pop {r7, pc} 08003272 : void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 8003272: b580 push {r7, lr} 8003274: b084 sub sp, #16 8003276: af00 add r7, sp, #0 8003278: 60f8 str r0, [r7, #12] 800327a: 60b9 str r1, [r7, #8] 800327c: 607a str r2, [r7, #4] 800327e: 603b str r3, [r7, #0] timerConf->Pulse = pulse; 8003280: 68bb ldr r3, [r7, #8] 8003282: 69fa ldr r2, [r7, #28] 8003284: 605a str r2, [r3, #4] switch (setState) { 8003286: 7e3b ldrb r3, [r7, #24] 8003288: 2b02 cmp r3, #2 800328a: dc02 bgt.n 8003292 800328c: 2b00 cmp r3, #0 800328e: da03 bge.n 8003298 8003290: e038 b.n 8003304 8003292: 2b03 cmp r3, #3 8003294: d01b beq.n 80032ce 8003296: e035 b.n 8003304 case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003298: 68bb ldr r3, [r7, #8] 800329a: 2200 movs r2, #0 800329c: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800329e: 687a ldr r2, [r7, #4] 80032a0: 68b9 ldr r1, [r7, #8] 80032a2: 68f8 ldr r0, [r7, #12] 80032a4: f00c ff4e bl 8010144 80032a8: 4603 mov r3, r0 80032aa: 2b00 cmp r3, #0 80032ac: d001 beq.n 80032b2 Error_Handler (); 80032ae: f7fe fe0d bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80032b2: 68bb ldr r3, [r7, #8] 80032b4: 2200 movs r2, #0 80032b6: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80032b8: 683a ldr r2, [r7, #0] 80032ba: 68b9 ldr r1, [r7, #8] 80032bc: 68f8 ldr r0, [r7, #12] 80032be: f00c ff41 bl 8010144 80032c2: 4603 mov r3, r0 80032c4: 2b00 cmp r3, #0 80032c6: d038 beq.n 800333a Error_Handler (); 80032c8: f7fe fe00 bl 8001ecc } break; 80032cc: e035 b.n 800333a case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80032ce: 68bb ldr r3, [r7, #8] 80032d0: 2202 movs r2, #2 80032d2: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80032d4: 687a ldr r2, [r7, #4] 80032d6: 68b9 ldr r1, [r7, #8] 80032d8: 68f8 ldr r0, [r7, #12] 80032da: f00c ff33 bl 8010144 80032de: 4603 mov r3, r0 80032e0: 2b00 cmp r3, #0 80032e2: d001 beq.n 80032e8 Error_Handler (); 80032e4: f7fe fdf2 bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80032e8: 68bb ldr r3, [r7, #8] 80032ea: 2202 movs r2, #2 80032ec: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80032ee: 683a ldr r2, [r7, #0] 80032f0: 68b9 ldr r1, [r7, #8] 80032f2: 68f8 ldr r0, [r7, #12] 80032f4: f00c ff26 bl 8010144 80032f8: 4603 mov r3, r0 80032fa: 2b00 cmp r3, #0 80032fc: d01f beq.n 800333e Error_Handler (); 80032fe: f7fe fde5 bl 8001ecc } break; 8003302: e01c b.n 800333e default: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003304: 68bb ldr r3, [r7, #8] 8003306: 2200 movs r2, #0 8003308: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800330a: 687a ldr r2, [r7, #4] 800330c: 68b9 ldr r1, [r7, #8] 800330e: 68f8 ldr r0, [r7, #12] 8003310: f00c ff18 bl 8010144 8003314: 4603 mov r3, r0 8003316: 2b00 cmp r3, #0 8003318: d001 beq.n 800331e Error_Handler (); 800331a: f7fe fdd7 bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800331e: 68bb ldr r3, [r7, #8] 8003320: 2200 movs r2, #0 8003322: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8003324: 683a ldr r2, [r7, #0] 8003326: 68b9 ldr r1, [r7, #8] 8003328: 68f8 ldr r0, [r7, #12] 800332a: f00c ff0b bl 8010144 800332e: 4603 mov r3, r0 8003330: 2b00 cmp r3, #0 8003332: d006 beq.n 8003342 Error_Handler (); 8003334: f7fe fdca bl 8001ecc } break; 8003338: e003 b.n 8003342 break; 800333a: bf00 nop 800333c: e002 b.n 8003344 break; 800333e: bf00 nop 8003340: e000 b.n 8003344 break; 8003342: bf00 nop } } 8003344: bf00 nop 8003346: 3710 adds r7, #16 8003348: 46bd mov sp, r7 800334a: bd80 pop {r7, pc} 0800334c : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; extern TIM_HandleTypeDef htim3; extern TIM_OC_InitTypeDef motorXYTimerConfigOC; void PositionControlTaskInit (void) { 800334c: b580 push {r7, lr} 800334e: b08a sub sp, #40 @ 0x28 8003350: af00 add r7, sp, #0 positionSettingMutex = osMutexNew (NULL); 8003352: 2000 movs r0, #0 8003354: f011 f829 bl 80143aa 8003358: 4603 mov r3, r0 800335a: 4a42 ldr r2, [pc, #264] @ (8003464 ) 800335c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 800335e: 1d3b adds r3, r7, #4 8003360: 2224 movs r2, #36 @ 0x24 8003362: 2100 movs r1, #0 8003364: 4618 mov r0, r3 8003366: f014 ffcf bl 8018308 osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2; 800336a: f44f 6380 mov.w r3, #1024 @ 0x400 800336e: 61bb str r3, [r7, #24] osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal; 8003370: 2318 movs r3, #24 8003372: 61fb str r3, [r7, #28] positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1; 8003374: 4b3c ldr r3, [pc, #240] @ (8003468 ) 8003376: 2200 movs r2, #0 8003378: 721a strb r2, [r3, #8] positionXControlTaskInitArg.channel2 = TIM_CHANNEL_2; 800337a: 4b3b ldr r3, [pc, #236] @ (8003468 ) 800337c: 2204 movs r2, #4 800337e: 725a strb r2, [r3, #9] positionXControlTaskInitArg.htim = &htim3; 8003380: 4b39 ldr r3, [pc, #228] @ (8003468 ) 8003382: 4a3a ldr r2, [pc, #232] @ (800346c ) 8003384: 601a str r2, [r3, #0] positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8003386: 4b38 ldr r3, [pc, #224] @ (8003468 ) 8003388: 4a39 ldr r2, [pc, #228] @ (8003470 ) 800338a: 605a str r2, [r3, #4] positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 800338c: 4b39 ldr r3, [pc, #228] @ (8003474 ) 800338e: 681b ldr r3, [r3, #0] 8003390: 4a35 ldr r2, [pc, #212] @ (8003468 ) 8003392: 60d3 str r3, [r2, #12] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8003394: 2200 movs r2, #0 8003396: 2104 movs r1, #4 8003398: 2010 movs r0, #16 800339a: f011 f914 bl 80145c6 800339e: 4603 mov r3, r0 80033a0: 4a31 ldr r2, [pc, #196] @ (8003468 ) 80033a2: 6113 str r3, [r2, #16] positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter); 80033a4: 4b30 ldr r3, [pc, #192] @ (8003468 ) 80033a6: 4a34 ldr r2, [pc, #208] @ (8003478 ) 80033a8: 61da str r2, [r3, #28] positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp); 80033aa: 4b2f ldr r3, [pc, #188] @ (8003468 ) 80033ac: 4a33 ldr r2, [pc, #204] @ (800347c ) 80033ae: 615a str r2, [r3, #20] positionXControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitXSwitchDown); 80033b0: 4b2d ldr r3, [pc, #180] @ (8003468 ) 80033b2: 4a33 ldr r2, [pc, #204] @ (8003480 ) 80033b4: 619a str r2, [r3, #24] positionXControlTaskInitArg.currentPosition = &(sensorsInfo.currentXPosition); 80033b6: 4b2c ldr r3, [pc, #176] @ (8003468 ) 80033b8: 4a32 ldr r2, [pc, #200] @ (8003484 ) 80033ba: 621a str r2, [r3, #32] positionXControlTaskInitArg.motorStatus = &(sensorsInfo.motorXStatus); 80033bc: 4b2a ldr r3, [pc, #168] @ (8003468 ) 80033be: 4a32 ldr r2, [pc, #200] @ (8003488 ) 80033c0: 629a str r2, [r3, #40] @ 0x28 positionXControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorXPeakCurrent); 80033c2: 4b29 ldr r3, [pc, #164] @ (8003468 ) 80033c4: 4a31 ldr r2, [pc, #196] @ (800348c ) 80033c6: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionXSetting; 80033c8: 4b27 ldr r3, [pc, #156] @ (8003468 ) 80033ca: 4a31 ldr r2, [pc, #196] @ (8003490 ) 80033cc: 625a str r2, [r3, #36] @ 0x24 positionXControlTaskInitArg.axe = 'X'; 80033ce: 4b26 ldr r3, [pc, #152] @ (8003468 ) 80033d0: 2258 movs r2, #88 @ 0x58 80033d2: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 80033d6: 4b2f ldr r3, [pc, #188] @ (8003494 ) 80033d8: 2208 movs r2, #8 80033da: 721a strb r2, [r3, #8] positionYControlTaskInitArg.channel2 = TIM_CHANNEL_4; 80033dc: 4b2d ldr r3, [pc, #180] @ (8003494 ) 80033de: 220c movs r2, #12 80033e0: 725a strb r2, [r3, #9] positionYControlTaskInitArg.htim = &htim3; 80033e2: 4b2c ldr r3, [pc, #176] @ (8003494 ) 80033e4: 4a21 ldr r2, [pc, #132] @ (800346c ) 80033e6: 601a str r2, [r3, #0] positionYControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 80033e8: 4b2a ldr r3, [pc, #168] @ (8003494 ) 80033ea: 4a21 ldr r2, [pc, #132] @ (8003470 ) 80033ec: 605a str r2, [r3, #4] positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 80033ee: 4b2a ldr r3, [pc, #168] @ (8003498 ) 80033f0: 681b ldr r3, [r3, #0] 80033f2: 4a28 ldr r2, [pc, #160] @ (8003494 ) 80033f4: 60d3 str r3, [r2, #12] positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 80033f6: 2200 movs r2, #0 80033f8: 2104 movs r1, #4 80033fa: 2010 movs r0, #16 80033fc: f011 f8e3 bl 80145c6 8003400: 4603 mov r3, r0 8003402: 4a24 ldr r2, [pc, #144] @ (8003494 ) 8003404: 6113 str r3, [r2, #16] positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter); 8003406: 4b23 ldr r3, [pc, #140] @ (8003494 ) 8003408: 4a24 ldr r2, [pc, #144] @ (800349c ) 800340a: 61da str r2, [r3, #28] positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp); 800340c: 4b21 ldr r3, [pc, #132] @ (8003494 ) 800340e: 4a24 ldr r2, [pc, #144] @ (80034a0 ) 8003410: 615a str r2, [r3, #20] positionYControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitYSwitchDown); 8003412: 4b20 ldr r3, [pc, #128] @ (8003494 ) 8003414: 4a23 ldr r2, [pc, #140] @ (80034a4 ) 8003416: 619a str r2, [r3, #24] positionYControlTaskInitArg.currentPosition = &(sensorsInfo.currentYPosition); 8003418: 4b1e ldr r3, [pc, #120] @ (8003494 ) 800341a: 4a23 ldr r2, [pc, #140] @ (80034a8 ) 800341c: 621a str r2, [r3, #32] positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus); 800341e: 4b1d ldr r3, [pc, #116] @ (8003494 ) 8003420: 4a22 ldr r2, [pc, #136] @ (80034ac ) 8003422: 629a str r2, [r3, #40] @ 0x28 positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent); 8003424: 4b1b ldr r3, [pc, #108] @ (8003494 ) 8003426: 4a22 ldr r2, [pc, #136] @ (80034b0 ) 8003428: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionYSetting; 800342a: 4b0f ldr r3, [pc, #60] @ (8003468 ) 800342c: 4a21 ldr r2, [pc, #132] @ (80034b4 ) 800342e: 625a str r2, [r3, #36] @ 0x24 positionYControlTaskInitArg.axe = 'Y'; 8003430: 4b18 ldr r3, [pc, #96] @ (8003494 ) 8003432: 2259 movs r2, #89 @ 0x59 8003434: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 8003438: 1d3b adds r3, r7, #4 800343a: 461a mov r2, r3 800343c: 490a ldr r1, [pc, #40] @ (8003468 ) 800343e: 481e ldr r0, [pc, #120] @ (80034b8 ) 8003440: f010 fe0e bl 8014060 8003444: 4603 mov r3, r0 8003446: 4a1d ldr r2, [pc, #116] @ (80034bc ) 8003448: 6013 str r3, [r2, #0] positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); 800344a: 1d3b adds r3, r7, #4 800344c: 461a mov r2, r3 800344e: 4911 ldr r1, [pc, #68] @ (8003494 ) 8003450: 4819 ldr r0, [pc, #100] @ (80034b8 ) 8003452: f010 fe05 bl 8014060 8003456: 4603 mov r3, r0 8003458: 4a19 ldr r2, [pc, #100] @ (80034c0 ) 800345a: 6013 str r3, [r2, #0] } 800345c: bf00 nop 800345e: 3728 adds r7, #40 @ 0x28 8003460: 46bd mov sp, r7 8003462: bd80 pop {r7, pc} 8003464: 240008a8 .word 0x240008a8 8003468: 240008b4 .word 0x240008b4 800346c: 240004d4 .word 0x240004d4 8003470: 240007c0 .word 0x240007c0 8003474: 24000744 .word 0x24000744 8003478: 2400088a .word 0x2400088a 800347c: 24000888 .word 0x24000888 8003480: 24000889 .word 0x24000889 8003484: 24000890 .word 0x24000890 8003488: 24000874 .word 0x24000874 800348c: 24000880 .word 0x24000880 8003490: 240008a0 .word 0x240008a0 8003494: 240008e8 .word 0x240008e8 8003498: 24000774 .word 0x24000774 800349c: 2400088d .word 0x2400088d 80034a0: 2400088b .word 0x2400088b 80034a4: 2400088c .word 0x2400088c 80034a8: 24000894 .word 0x24000894 80034ac: 24000875 .word 0x24000875 80034b0: 24000884 .word 0x24000884 80034b4: 240008a4 .word 0x240008a4 80034b8: 080034c5 .word 0x080034c5 80034bc: 240008ac .word 0x240008ac 80034c0: 240008b0 .word 0x240008b0 080034c4 : void PositionControlTask (void* argument) { 80034c4: b5f0 push {r4, r5, r6, r7, lr} 80034c6: b097 sub sp, #92 @ 0x5c 80034c8: af06 add r7, sp, #24 80034ca: 6078 str r0, [r7, #4] const int32_t PositionControlTaskTimeOut = 100; 80034cc: 2364 movs r3, #100 @ 0x64 80034ce: 623b str r3, [r7, #32] PositionControlTaskInitArg* posCtrlTaskArg = (PositionControlTaskInitArg*)argument; 80034d0: 687b ldr r3, [r7, #4] 80034d2: 61fb str r3, [r7, #28] PositionControlTaskData posCtrlData = { 0 }; 80034d4: f04f 0300 mov.w r3, #0 80034d8: 60bb str r3, [r7, #8] uint32_t motorStatus = 0; 80034da: 2300 movs r3, #0 80034dc: 61bb str r3, [r7, #24] osStatus_t queueSatus; int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE; 80034de: 233c movs r3, #60 @ 0x3c 80034e0: 63fb str r3, [r7, #60] @ 0x3c int32_t sign = 0; 80034e2: 2300 movs r3, #0 80034e4: 63bb str r3, [r7, #56] @ 0x38 MovementPhases movementPhase = idlePhase; 80034e6: 2300 movs r3, #0 80034e8: f887 3037 strb.w r3, [r7, #55] @ 0x37 float startPosition = 0; 80034ec: f04f 0300 mov.w r3, #0 80034f0: 633b str r3, [r7, #48] @ 0x30 float prevPosition = 0; 80034f2: f04f 0300 mov.w r3, #0 80034f6: 62fb str r3, [r7, #44] @ 0x2c int32_t timeLeftMS = 0; 80034f8: 2300 movs r3, #0 80034fa: 62bb str r3, [r7, #40] @ 0x28 int32_t moveCmdTimeoutCounter = 0; 80034fc: 2300 movs r3, #0 80034fe: 627b str r3, [r7, #36] @ 0x24 while (pdTRUE) { queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003500: 69fb ldr r3, [r7, #28] 8003502: 6918 ldr r0, [r3, #16] 8003504: 6a3b ldr r3, [r7, #32] 8003506: f44f 727a mov.w r2, #1000 @ 0x3e8 800350a: fb02 f303 mul.w r3, r2, r3 800350e: 4a9f ldr r2, [pc, #636] @ (800378c ) 8003510: fba2 2303 umull r2, r3, r2, r3 8003514: 099b lsrs r3, r3, #6 8003516: f107 0108 add.w r1, r7, #8 800351a: 2200 movs r2, #0 800351c: f011 f926 bl 801476c 8003520: 6178 str r0, [r7, #20] if (queueSatus == osOK) { 8003522: 697b ldr r3, [r7, #20] 8003524: 2b00 cmp r3, #0 8003526: d14a bne.n 80035be if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003528: 4b99 ldr r3, [pc, #612] @ (8003790 ) 800352a: 681b ldr r3, [r3, #0] 800352c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003530: 4618 mov r0, r3 8003532: f010 ffc0 bl 80144b6 8003536: 4603 mov r3, r0 8003538: 2b00 cmp r3, #0 800353a: d1e1 bne.n 8003500 float posDiff = posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition; 800353c: ed97 7a02 vldr s14, [r7, #8] 8003540: 69fb ldr r3, [r7, #28] 8003542: 6a1b ldr r3, [r3, #32] 8003544: edd3 7a00 vldr s15, [r3] 8003548: ee77 7a67 vsub.f32 s15, s14, s15 800354c: edc7 7a03 vstr s15, [r7, #12] if (posDiff != 0) { 8003550: edd7 7a03 vldr s15, [r7, #12] 8003554: eef5 7a40 vcmp.f32 s15, #0.0 8003558: eef1 fa10 vmrs APSR_nzcv, fpscr 800355c: d016 beq.n 800358c sign = posDiff > 0 ? 1 : -1; 800355e: edd7 7a03 vldr s15, [r7, #12] 8003562: eef5 7ac0 vcmpe.f32 s15, #0.0 8003566: eef1 fa10 vmrs APSR_nzcv, fpscr 800356a: dd01 ble.n 8003570 800356c: 2301 movs r3, #1 800356e: e001 b.n 8003574 8003570: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8003574: 63bb str r3, [r7, #56] @ 0x38 startPosition = *posCtrlTaskArg->currentPosition; 8003576: 69fb ldr r3, [r7, #28] 8003578: 6a1b ldr r3, [r3, #32] 800357a: 681b ldr r3, [r3, #0] 800357c: 633b str r3, [r7, #48] @ 0x30 movementPhase = startPhase; 800357e: 2301 movs r3, #1 8003580: f887 3037 strb.w r3, [r7, #55] @ 0x37 moveCmdTimeoutCounter = 0; 8003584: 2300 movs r3, #0 8003586: 627b str r3, [r7, #36] @ 0x24 timeLeftMS = 0; 8003588: 2300 movs r3, #0 800358a: 62bb str r3, [r7, #40] @ 0x28 #ifdef DBG_POSITION printf ("Axe %c start phase\n", posCtrlTaskArg->axe); #endif } osMutexRelease (sensorsInfoMutex); 800358c: 4b80 ldr r3, [pc, #512] @ (8003790 ) 800358e: 681b ldr r3, [r3, #0] 8003590: 4618 mov r0, r3 8003592: f010 ffdb bl 801454c if (osMutexAcquire (positionSettingMutex, osWaitForever) == osOK) { 8003596: 4b7f ldr r3, [pc, #508] @ (8003794 ) 8003598: 681b ldr r3, [r3, #0] 800359a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800359e: 4618 mov r0, r3 80035a0: f010 ff89 bl 80144b6 80035a4: 4603 mov r3, r0 80035a6: 2b00 cmp r3, #0 80035a8: d1aa bne.n 8003500 *positionXControlTaskInitArg.positionSetting = posCtrlData.positionSettingValue; 80035aa: 4b7b ldr r3, [pc, #492] @ (8003798 ) 80035ac: 6a5b ldr r3, [r3, #36] @ 0x24 80035ae: 68ba ldr r2, [r7, #8] 80035b0: 601a str r2, [r3, #0] osMutexRelease (positionSettingMutex); 80035b2: 4b78 ldr r3, [pc, #480] @ (8003794 ) 80035b4: 681b ldr r3, [r3, #0] 80035b6: 4618 mov r0, r3 80035b8: f010 ffc8 bl 801454c 80035bc: e7a0 b.n 8003500 } } } else if (queueSatus == osErrorTimeout) { 80035be: 697b ldr r3, [r7, #20] 80035c0: f113 0f02 cmn.w r3, #2 80035c4: d19c bne.n 8003500 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80035c6: 4b72 ldr r3, [pc, #456] @ (8003790 ) 80035c8: 681b ldr r3, [r3, #0] 80035ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80035ce: 4618 mov r0, r3 80035d0: f010 ff71 bl 80144b6 80035d4: 4603 mov r3, r0 80035d6: 2b00 cmp r3, #0 80035d8: d192 bne.n 8003500 if ((*posCtrlTaskArg->motorStatus != 0) || (movementPhase == startPhase)) { 80035da: 69fb ldr r3, [r7, #28] 80035dc: 6a9b ldr r3, [r3, #40] @ 0x28 80035de: 781b ldrb r3, [r3, #0] 80035e0: 2b00 cmp r3, #0 80035e2: d104 bne.n 80035ee 80035e4: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80035e8: 2b01 cmp r3, #1 80035ea: f040 81c4 bne.w 8003976 if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 80035ee: 69fb ldr r3, [r7, #28] 80035f0: 699b ldr r3, [r3, #24] 80035f2: 781b ldrb r3, [r3, #0] 80035f4: 2b01 cmp r3, #1 80035f6: d104 bne.n 8003602 80035f8: 69fb ldr r3, [r7, #28] 80035fa: 695b ldr r3, [r3, #20] 80035fc: 781b ldrb r3, [r3, #0] 80035fe: 2b01 cmp r3, #1 8003600: d009 beq.n 8003616 ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 8003602: 69fb ldr r3, [r7, #28] 8003604: 695b ldr r3, [r3, #20] 8003606: 781b ldrb r3, [r3, #0] if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003608: 2b01 cmp r3, #1 800360a: d12a bne.n 8003662 ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 800360c: 69fb ldr r3, [r7, #28] 800360e: 69db ldr r3, [r3, #28] 8003610: 781b ldrb r3, [r3, #0] 8003612: 2b01 cmp r3, #1 8003614: d125 bne.n 8003662 movementPhase = idlePhase; 8003616: 2300 movs r3, #0 8003618: f887 3037 strb.w r3, [r7, #55] @ 0x37 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 800361c: 69fb ldr r3, [r7, #28] 800361e: 6818 ldr r0, [r3, #0] 8003620: 69fb ldr r3, [r7, #28] 8003622: 685c ldr r4, [r3, #4] 8003624: 69fb ldr r3, [r7, #28] 8003626: 7a1d ldrb r5, [r3, #8] 8003628: 69fb ldr r3, [r7, #28] 800362a: 7a5e ldrb r6, [r3, #9] 800362c: 69fb ldr r3, [r7, #28] 800362e: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003630: 69fa ldr r2, [r7, #28] 8003632: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003634: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003636: 69f9 ldr r1, [r7, #28] 8003638: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 800363a: 7809 ldrb r1, [r1, #0] 800363c: 9104 str r1, [sp, #16] 800363e: 9203 str r2, [sp, #12] 8003640: 2200 movs r2, #0 8003642: 9202 str r2, [sp, #8] 8003644: 2200 movs r2, #0 8003646: 9201 str r2, [sp, #4] 8003648: 9300 str r3, [sp, #0] 800364a: 4633 mov r3, r6 800364c: 462a mov r2, r5 800364e: 4621 mov r1, r4 8003650: f7ff fcd6 bl 8003000 8003654: 4603 mov r3, r0 8003656: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003658: 69fb ldr r3, [r7, #28] 800365a: 6a9b ldr r3, [r3, #40] @ 0x28 800365c: 69ba ldr r2, [r7, #24] 800365e: b2d2 uxtb r2, r2 8003660: 701a strb r2, [r3, #0] printf ("Axe %c limiters wrong state - idle phase\n", posCtrlTaskArg->axe); #endif } timeLeftMS += PositionControlTaskTimeOut; 8003662: 6aba ldr r2, [r7, #40] @ 0x28 8003664: 6a3b ldr r3, [r7, #32] 8003666: 4413 add r3, r2 8003668: 62bb str r3, [r7, #40] @ 0x28 if (prevPosition == *posCtrlTaskArg->currentPosition) { 800366a: 69fb ldr r3, [r7, #28] 800366c: 6a1b ldr r3, [r3, #32] 800366e: edd3 7a00 vldr s15, [r3] 8003672: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 8003676: eeb4 7a67 vcmp.f32 s14, s15 800367a: eef1 fa10 vmrs APSR_nzcv, fpscr 800367e: d104 bne.n 800368a moveCmdTimeoutCounter += PositionControlTaskTimeOut; 8003680: 6a7a ldr r2, [r7, #36] @ 0x24 8003682: 6a3b ldr r3, [r7, #32] 8003684: 4413 add r3, r2 8003686: 627b str r3, [r7, #36] @ 0x24 8003688: e001 b.n 800368e } else { moveCmdTimeoutCounter = 0; 800368a: 2300 movs r3, #0 800368c: 627b str r3, [r7, #36] @ 0x24 } prevPosition = *posCtrlTaskArg->currentPosition; 800368e: 69fb ldr r3, [r7, #28] 8003690: 6a1b ldr r3, [r3, #32] 8003692: 681b ldr r3, [r3, #0] 8003694: 62fb str r3, [r7, #44] @ 0x2c if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 8003696: 6a7b ldr r3, [r7, #36] @ 0x24 8003698: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800369c: dd25 ble.n 80036ea movementPhase = idlePhase; 800369e: 2300 movs r3, #0 80036a0: f887 3037 strb.w r3, [r7, #55] @ 0x37 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036a4: 69fb ldr r3, [r7, #28] 80036a6: 6818 ldr r0, [r3, #0] 80036a8: 69fb ldr r3, [r7, #28] 80036aa: 685c ldr r4, [r3, #4] 80036ac: 69fb ldr r3, [r7, #28] 80036ae: 7a1d ldrb r5, [r3, #8] 80036b0: 69fb ldr r3, [r7, #28] 80036b2: 7a5e ldrb r6, [r3, #9] 80036b4: 69fb ldr r3, [r7, #28] 80036b6: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80036b8: 69fa ldr r2, [r7, #28] 80036ba: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036bc: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80036be: 69f9 ldr r1, [r7, #28] 80036c0: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036c2: 7809 ldrb r1, [r1, #0] 80036c4: 9104 str r1, [sp, #16] 80036c6: 9203 str r2, [sp, #12] 80036c8: 2200 movs r2, #0 80036ca: 9202 str r2, [sp, #8] 80036cc: 2200 movs r2, #0 80036ce: 9201 str r2, [sp, #4] 80036d0: 9300 str r3, [sp, #0] 80036d2: 4633 mov r3, r6 80036d4: 462a mov r2, r5 80036d6: 4621 mov r1, r4 80036d8: f7ff fc92 bl 8003000 80036dc: 4603 mov r3, r0 80036de: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80036e0: 69fb ldr r3, [r7, #28] 80036e2: 6a9b ldr r3, [r3, #40] @ 0x28 80036e4: 69ba ldr r2, [r7, #24] 80036e6: b2d2 uxtb r2, r2 80036e8: 701a strb r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c no movement idle phase\n", posCtrlTaskArg->axe); #endif } switch (movementPhase) { 80036ea: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80036ee: 3b01 subs r3, #1 80036f0: 2b04 cmp r3, #4 80036f2: f200 8138 bhi.w 8003966 80036f6: a201 add r2, pc, #4 @ (adr r2, 80036fc ) 80036f8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80036fc: 08003711 .word 0x08003711 8003700: 0800379d .word 0x0800379d 8003704: 08003827 .word 0x08003827 8003708: 08003875 .word 0x08003875 800370c: 080038d7 .word 0x080038d7 case startPhase: motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003710: 69fb ldr r3, [r7, #28] 8003712: 681c ldr r4, [r3, #0] 8003714: 69fb ldr r3, [r7, #28] 8003716: 685d ldr r5, [r3, #4] 8003718: 69fb ldr r3, [r7, #28] 800371a: 7a1e ldrb r6, [r3, #8] 800371c: 69fb ldr r3, [r7, #28] 800371e: f893 c009 ldrb.w ip, [r3, #9] 8003722: 69fb ldr r3, [r7, #28] 8003724: 68db ldr r3, [r3, #12] 8003726: 6bba ldr r2, [r7, #56] @ 0x38 8003728: 6bf9 ldr r1, [r7, #60] @ 0x3c 800372a: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800372e: 69f9 ldr r1, [r7, #28] 8003730: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003732: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003734: 69f8 ldr r0, [r7, #28] 8003736: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003738: 7800 ldrb r0, [r0, #0] 800373a: 9004 str r0, [sp, #16] 800373c: 9103 str r1, [sp, #12] 800373e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003742: 9102 str r1, [sp, #8] 8003744: 9201 str r2, [sp, #4] 8003746: 9300 str r3, [sp, #0] 8003748: 4663 mov r3, ip 800374a: 4632 mov r2, r6 800374c: 4629 mov r1, r5 800374e: 4620 mov r0, r4 8003750: f7ff fc56 bl 8003000 8003754: 4603 mov r3, r0 8003756: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003758: 69fb ldr r3, [r7, #28] 800375a: 6a9b ldr r3, [r3, #40] @ 0x28 800375c: 69ba ldr r2, [r7, #24] 800375e: b2d2 uxtb r2, r2 8003760: 701a strb r2, [r3, #0] if (motorStatus == 1) { 8003762: 69bb ldr r3, [r7, #24] 8003764: 2b01 cmp r3, #1 8003766: d10c bne.n 8003782 *posCtrlTaskArg->motorPeakCurrent = 0.0; 8003768: 69fb ldr r3, [r7, #28] 800376a: 6adb ldr r3, [r3, #44] @ 0x2c 800376c: f04f 0200 mov.w r2, #0 8003770: 601a str r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c speed up phase\n", posCtrlTaskArg->axe); #endif movementPhase = speedUpPhase; 8003772: 2302 movs r3, #2 8003774: f887 3037 strb.w r3, [r7, #55] @ 0x37 timeLeftMS = 0; 8003778: 2300 movs r3, #0 800377a: 62bb str r3, [r7, #40] @ 0x28 moveCmdTimeoutCounter = 0; 800377c: 2300 movs r3, #0 800377e: 627b str r3, [r7, #36] @ 0x24 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 8003780: e0f8 b.n 8003974 movementPhase = idlePhase; 8003782: 2300 movs r3, #0 8003784: f887 3037 strb.w r3, [r7, #55] @ 0x37 break; 8003788: e0f4 b.n 8003974 800378a: bf00 nop 800378c: 10624dd3 .word 0x10624dd3 8003790: 2400081c .word 0x2400081c 8003794: 240008a8 .word 0x240008a8 8003798: 240008b4 .word 0x240008b4 case speedUpPhase: if ((abs (*posCtrlTaskArg->currentPosition - startPosition) >= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 800379c: 69fb ldr r3, [r7, #28] 800379e: 6a1b ldr r3, [r3, #32] 80037a0: ed93 7a00 vldr s14, [r3] 80037a4: edd7 7a0c vldr s15, [r7, #48] @ 0x30 80037a8: ee77 7a67 vsub.f32 s15, s14, s15 80037ac: eefd 7ae7 vcvt.s32.f32 s15, s15 80037b0: ee17 3a90 vmov r3, s15 80037b4: 2b00 cmp r3, #0 80037b6: bfb8 it lt 80037b8: 425b neglt r3, r3 80037ba: 2b04 cmp r3, #4 80037bc: dc04 bgt.n 80037c8 80037be: 6abb ldr r3, [r7, #40] @ 0x28 80037c0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80037c4: f2c0 80d1 blt.w 800396a pwmValue = MOTOR_HIGH_SPEED_PWM_VALUE; 80037c8: 2364 movs r3, #100 @ 0x64 80037ca: 63fb str r3, [r7, #60] @ 0x3c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037cc: 69fb ldr r3, [r7, #28] 80037ce: 681c ldr r4, [r3, #0] 80037d0: 69fb ldr r3, [r7, #28] 80037d2: 685d ldr r5, [r3, #4] 80037d4: 69fb ldr r3, [r7, #28] 80037d6: 7a1e ldrb r6, [r3, #8] 80037d8: 69fb ldr r3, [r7, #28] 80037da: f893 c009 ldrb.w ip, [r3, #9] 80037de: 69fb ldr r3, [r7, #28] 80037e0: 68db ldr r3, [r3, #12] 80037e2: 6bba ldr r2, [r7, #56] @ 0x38 80037e4: 6bf9 ldr r1, [r7, #60] @ 0x3c 80037e6: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037ea: 69f9 ldr r1, [r7, #28] 80037ec: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037ee: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037f0: 69f8 ldr r0, [r7, #28] 80037f2: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037f4: 7800 ldrb r0, [r0, #0] 80037f6: 9004 str r0, [sp, #16] 80037f8: 9103 str r1, [sp, #12] 80037fa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80037fe: 9102 str r1, [sp, #8] 8003800: 9201 str r2, [sp, #4] 8003802: 9300 str r3, [sp, #0] 8003804: 4663 mov r3, ip 8003806: 4632 mov r2, r6 8003808: 4629 mov r1, r5 800380a: 4620 mov r0, r4 800380c: f7ff fbf8 bl 8003000 8003810: 4603 mov r3, r0 8003812: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003814: 69fb ldr r3, [r7, #28] 8003816: 6a9b ldr r3, [r3, #40] @ 0x28 8003818: 69ba ldr r2, [r7, #24] 800381a: b2d2 uxtb r2, r2 800381c: 701a strb r2, [r3, #0] movementPhase = movePhase; 800381e: 2303 movs r3, #3 8003820: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c move phase\n", posCtrlTaskArg->axe); #endif } break; 8003824: e0a1 b.n 800396a case movePhase: if (abs (*posCtrlTaskArg->currentPosition - *posCtrlTaskArg->positionSetting) <= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) { 8003826: 69fb ldr r3, [r7, #28] 8003828: 6a1b ldr r3, [r3, #32] 800382a: ed93 7a00 vldr s14, [r3] 800382e: 69fb ldr r3, [r7, #28] 8003830: 6a5b ldr r3, [r3, #36] @ 0x24 8003832: edd3 7a00 vldr s15, [r3] 8003836: ee77 7a67 vsub.f32 s15, s14, s15 800383a: eefd 7ae7 vcvt.s32.f32 s15, s15 800383e: ee17 3a90 vmov r3, s15 8003842: f113 0f05 cmn.w r3, #5 8003846: f2c0 8092 blt.w 800396e 800384a: 69fb ldr r3, [r7, #28] 800384c: 6a1b ldr r3, [r3, #32] 800384e: ed93 7a00 vldr s14, [r3] 8003852: 69fb ldr r3, [r7, #28] 8003854: 6a5b ldr r3, [r3, #36] @ 0x24 8003856: edd3 7a00 vldr s15, [r3] 800385a: ee77 7a67 vsub.f32 s15, s14, s15 800385e: eefd 7ae7 vcvt.s32.f32 s15, s15 8003862: ee17 3a90 vmov r3, s15 8003866: 2b05 cmp r3, #5 8003868: f300 8081 bgt.w 800396e movementPhase = slowDownPhase; 800386c: 2304 movs r3, #4 800386e: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c slow down phase\n", posCtrlTaskArg->axe); #endif } break; 8003872: e07c b.n 800396e case slowDownPhase: pwmValue = MOTOR_START_STOP_PWM_VALUE; 8003874: 233c movs r3, #60 @ 0x3c 8003876: 63fb str r3, [r7, #60] @ 0x3c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003878: 69fb ldr r3, [r7, #28] 800387a: 681c ldr r4, [r3, #0] 800387c: 69fb ldr r3, [r7, #28] 800387e: 685d ldr r5, [r3, #4] 8003880: 69fb ldr r3, [r7, #28] 8003882: 7a1e ldrb r6, [r3, #8] 8003884: 69fb ldr r3, [r7, #28] 8003886: f893 c009 ldrb.w ip, [r3, #9] 800388a: 69fb ldr r3, [r7, #28] 800388c: 68db ldr r3, [r3, #12] 800388e: 6bba ldr r2, [r7, #56] @ 0x38 8003890: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003892: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003896: 69f9 ldr r1, [r7, #28] 8003898: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800389a: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800389c: 69f8 ldr r0, [r7, #28] 800389e: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80038a0: 7800 ldrb r0, [r0, #0] 80038a2: 9004 str r0, [sp, #16] 80038a4: 9103 str r1, [sp, #12] 80038a6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80038aa: 9102 str r1, [sp, #8] 80038ac: 9201 str r2, [sp, #4] 80038ae: 9300 str r3, [sp, #0] 80038b0: 4663 mov r3, ip 80038b2: 4632 mov r2, r6 80038b4: 4629 mov r1, r5 80038b6: 4620 mov r0, r4 80038b8: f7ff fba2 bl 8003000 80038bc: 4603 mov r3, r0 80038be: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80038c0: 69fb ldr r3, [r7, #28] 80038c2: 6a9b ldr r3, [r3, #40] @ 0x28 80038c4: 69ba ldr r2, [r7, #24] 80038c6: b2d2 uxtb r2, r2 80038c8: 701a strb r2, [r3, #0] movementPhase = stopPhase; 80038ca: 2305 movs r3, #5 80038cc: f887 3037 strb.w r3, [r7, #55] @ 0x37 timeLeftMS = 0; 80038d0: 2300 movs r3, #0 80038d2: 62bb str r3, [r7, #40] @ 0x28 #ifdef DBG_POSITION printf ("Axe %c stop phase\n", posCtrlTaskArg->axe); #endif break; 80038d4: e04e b.n 8003974 case stopPhase: float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue; 80038d6: 6bbb ldr r3, [r7, #56] @ 0x38 80038d8: 2b00 cmp r3, #0 80038da: dd08 ble.n 80038ee 80038dc: ed97 7a02 vldr s14, [r7, #8] 80038e0: 69fb ldr r3, [r7, #28] 80038e2: 6a1b ldr r3, [r3, #32] 80038e4: edd3 7a00 vldr s15, [r3] 80038e8: ee77 7a67 vsub.f32 s15, s14, s15 80038ec: e007 b.n 80038fe 80038ee: 69fb ldr r3, [r7, #28] 80038f0: 6a1b ldr r3, [r3, #32] 80038f2: ed93 7a00 vldr s14, [r3] 80038f6: edd7 7a02 vldr s15, [r7, #8] 80038fa: ee77 7a67 vsub.f32 s15, s14, s15 80038fe: edc7 7a04 vstr s15, [r7, #16] if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 8003902: edd7 7a04 vldr s15, [r7, #16] 8003906: eef5 7ac0 vcmpe.f32 s15, #0.0 800390a: eef1 fa10 vmrs APSR_nzcv, fpscr 800390e: d903 bls.n 8003918 8003910: 6abb ldr r3, [r7, #40] @ 0x28 8003912: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 8003916: db2c blt.n 8003972 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003918: 69fb ldr r3, [r7, #28] 800391a: 6818 ldr r0, [r3, #0] 800391c: 69fb ldr r3, [r7, #28] 800391e: 685c ldr r4, [r3, #4] 8003920: 69fb ldr r3, [r7, #28] 8003922: 7a1d ldrb r5, [r3, #8] 8003924: 69fb ldr r3, [r7, #28] 8003926: 7a5e ldrb r6, [r3, #9] 8003928: 69fb ldr r3, [r7, #28] 800392a: 68db ldr r3, [r3, #12] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800392c: 69fa ldr r2, [r7, #28] 800392e: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003930: 7812 ldrb r2, [r2, #0] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003932: 69f9 ldr r1, [r7, #28] 8003934: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003936: 7809 ldrb r1, [r1, #0] 8003938: 9104 str r1, [sp, #16] 800393a: 9203 str r2, [sp, #12] 800393c: 2200 movs r2, #0 800393e: 9202 str r2, [sp, #8] 8003940: 2200 movs r2, #0 8003942: 9201 str r2, [sp, #4] 8003944: 9300 str r3, [sp, #0] 8003946: 4633 mov r3, r6 8003948: 462a mov r2, r5 800394a: 4621 mov r1, r4 800394c: f7ff fb58 bl 8003000 8003950: 4603 mov r3, r0 8003952: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003954: 69fb ldr r3, [r7, #28] 8003956: 6a9b ldr r3, [r3, #40] @ 0x28 8003958: 69ba ldr r2, [r7, #24] 800395a: b2d2 uxtb r2, r2 800395c: 701a strb r2, [r3, #0] movementPhase = idlePhase; 800395e: 2300 movs r3, #0 8003960: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 8003964: e005 b.n 8003972 default: break; 8003966: bf00 nop 8003968: e011 b.n 800398e break; 800396a: bf00 nop 800396c: e00f b.n 800398e break; 800396e: bf00 nop 8003970: e00d b.n 800398e break; 8003972: bf00 nop switch (movementPhase) { 8003974: e00b b.n 800398e } } else { if ((*posCtrlTaskArg->motorStatus == 0) && (movementPhase != idlePhase)) { 8003976: 69fb ldr r3, [r7, #28] 8003978: 6a9b ldr r3, [r3, #40] @ 0x28 800397a: 781b ldrb r3, [r3, #0] 800397c: 2b00 cmp r3, #0 800397e: d106 bne.n 800398e 8003980: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 8003984: 2b00 cmp r3, #0 8003986: d002 beq.n 800398e movementPhase = idlePhase; 8003988: 2300 movs r3, #0 800398a: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } } osMutexRelease (sensorsInfoMutex); 800398e: 4b03 ldr r3, [pc, #12] @ (800399c ) 8003990: 681b ldr r3, [r3, #0] 8003992: 4618 mov r0, r3 8003994: f010 fdda bl 801454c queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003998: e5b2 b.n 8003500 800399a: bf00 nop 800399c: 2400081c .word 0x2400081c 080039a0 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 80039a0: b480 push {r7} 80039a2: b089 sub sp, #36 @ 0x24 80039a4: af00 add r7, sp, #0 80039a6: 60f8 str r0, [r7, #12] 80039a8: 60b9 str r1, [r7, #8] 80039aa: 607a str r2, [r7, #4] 80039ac: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 80039ae: 687b ldr r3, [r7, #4] 80039b0: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 80039b2: 69bb ldr r3, [r7, #24] 80039b4: 681b ldr r3, [r3, #0] 80039b6: 617b str r3, [r7, #20] uint8_t i = 0; 80039b8: 2300 movs r3, #0 80039ba: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 80039bc: 68bb ldr r3, [r7, #8] 80039be: 881b ldrh r3, [r3, #0] 80039c0: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 80039c2: 2300 movs r3, #0 80039c4: 77fb strb r3, [r7, #31] 80039c6: e00e b.n 80039e6 buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 80039c8: 7ffb ldrb r3, [r7, #31] 80039ca: 00db lsls r3, r3, #3 80039cc: 697a ldr r2, [r7, #20] 80039ce: 40da lsrs r2, r3 80039d0: 7fbb ldrb r3, [r7, #30] 80039d2: 1c59 adds r1, r3, #1 80039d4: 77b9 strb r1, [r7, #30] 80039d6: 4619 mov r1, r3 80039d8: 68fb ldr r3, [r7, #12] 80039da: 440b add r3, r1 80039dc: b2d2 uxtb r2, r2 80039de: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 80039e0: 7ffb ldrb r3, [r7, #31] 80039e2: 3301 adds r3, #1 80039e4: 77fb strb r3, [r7, #31] 80039e6: 7ffa ldrb r2, [r7, #31] 80039e8: 78fb ldrb r3, [r7, #3] 80039ea: 429a cmp r2, r3 80039ec: d3ec bcc.n 80039c8 } *buffPos = newBuffPos; 80039ee: 7fbb ldrb r3, [r7, #30] 80039f0: b29a uxth r2, r3 80039f2: 68bb ldr r3, [r7, #8] 80039f4: 801a strh r2, [r3, #0] } 80039f6: bf00 nop 80039f8: 3724 adds r7, #36 @ 0x24 80039fa: 46bd mov sp, r7 80039fc: f85d 7b04 ldr.w r7, [sp], #4 8003a00: 4770 bx lr 08003a02 : void ReadFloatFromBuffer(uint8_t* buff, uint16_t* buffPos, float* data) { 8003a02: b480 push {r7} 8003a04: b087 sub sp, #28 8003a06: af00 add r7, sp, #0 8003a08: 60f8 str r0, [r7, #12] 8003a0a: 60b9 str r1, [r7, #8] 8003a0c: 607a str r2, [r7, #4] uint32_t* word = (uint32_t *)data; 8003a0e: 687b ldr r3, [r7, #4] 8003a10: 617b str r3, [r7, #20] *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8003a12: 68bb ldr r3, [r7, #8] 8003a14: 881b ldrh r3, [r3, #0] 8003a16: 3303 adds r3, #3 8003a18: 68fa ldr r2, [r7, #12] 8003a1a: 4413 add r3, r2 8003a1c: 781b ldrb r3, [r3, #0] 8003a1e: 061a lsls r2, r3, #24 8003a20: 68bb ldr r3, [r7, #8] 8003a22: 881b ldrh r3, [r3, #0] 8003a24: 3302 adds r3, #2 8003a26: 68f9 ldr r1, [r7, #12] 8003a28: 440b add r3, r1 8003a2a: 781b ldrb r3, [r3, #0] 8003a2c: 041b lsls r3, r3, #16 8003a2e: 431a orrs r2, r3 8003a30: 68bb ldr r3, [r7, #8] 8003a32: 881b ldrh r3, [r3, #0] 8003a34: 3301 adds r3, #1 8003a36: 68f9 ldr r1, [r7, #12] 8003a38: 440b add r3, r1 8003a3a: 781b ldrb r3, [r3, #0] 8003a3c: 021b lsls r3, r3, #8 8003a3e: 4313 orrs r3, r2 8003a40: 68ba ldr r2, [r7, #8] 8003a42: 8812 ldrh r2, [r2, #0] 8003a44: 4611 mov r1, r2 8003a46: 68fa ldr r2, [r7, #12] 8003a48: 440a add r2, r1 8003a4a: 7812 ldrb r2, [r2, #0] 8003a4c: 4313 orrs r3, r2 8003a4e: 461a mov r2, r3 8003a50: 697b ldr r3, [r7, #20] 8003a52: 601a str r2, [r3, #0] *buffPos += sizeof(float); 8003a54: 68bb ldr r3, [r7, #8] 8003a56: 881b ldrh r3, [r3, #0] 8003a58: 3304 adds r3, #4 8003a5a: b29a uxth r2, r3 8003a5c: 68bb ldr r3, [r7, #8] 8003a5e: 801a strh r2, [r3, #0] } 8003a60: bf00 nop 8003a62: 371c adds r7, #28 8003a64: 46bd mov sp, r7 8003a66: f85d 7b04 ldr.w r7, [sp], #4 8003a6a: 4770 bx lr 08003a6c : *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) { 8003a6c: b480 push {r7} 8003a6e: b085 sub sp, #20 8003a70: af00 add r7, sp, #0 8003a72: 60f8 str r0, [r7, #12] 8003a74: 60b9 str r1, [r7, #8] 8003a76: 607a str r2, [r7, #4] *data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8003a78: 68bb ldr r3, [r7, #8] 8003a7a: 881b ldrh r3, [r3, #0] 8003a7c: 3303 adds r3, #3 8003a7e: 68fa ldr r2, [r7, #12] 8003a80: 4413 add r3, r2 8003a82: 781b ldrb r3, [r3, #0] 8003a84: 061a lsls r2, r3, #24 8003a86: 68bb ldr r3, [r7, #8] 8003a88: 881b ldrh r3, [r3, #0] 8003a8a: 3302 adds r3, #2 8003a8c: 68f9 ldr r1, [r7, #12] 8003a8e: 440b add r3, r1 8003a90: 781b ldrb r3, [r3, #0] 8003a92: 041b lsls r3, r3, #16 8003a94: 431a orrs r2, r3 8003a96: 68bb ldr r3, [r7, #8] 8003a98: 881b ldrh r3, [r3, #0] 8003a9a: 3301 adds r3, #1 8003a9c: 68f9 ldr r1, [r7, #12] 8003a9e: 440b add r3, r1 8003aa0: 781b ldrb r3, [r3, #0] 8003aa2: 021b lsls r3, r3, #8 8003aa4: 4313 orrs r3, r2 8003aa6: 68ba ldr r2, [r7, #8] 8003aa8: 8812 ldrh r2, [r2, #0] 8003aaa: 4611 mov r1, r2 8003aac: 68fa ldr r2, [r7, #12] 8003aae: 440a add r2, r1 8003ab0: 7812 ldrb r2, [r2, #0] 8003ab2: 4313 orrs r3, r2 8003ab4: 461a mov r2, r3 8003ab6: 687b ldr r3, [r7, #4] 8003ab8: 601a str r2, [r3, #0] *buffPos += sizeof(uint32_t); 8003aba: 68bb ldr r3, [r7, #8] 8003abc: 881b ldrh r3, [r3, #0] 8003abe: 3304 adds r3, #4 8003ac0: b29a uxth r2, r3 8003ac2: 68bb ldr r3, [r7, #8] 8003ac4: 801a strh r2, [r3, #0] } 8003ac6: bf00 nop 8003ac8: 3714 adds r7, #20 8003aca: 46bd mov sp, r7 8003acc: f85d 7b04 ldr.w r7, [sp], #4 8003ad0: 4770 bx lr ... 08003ad4 : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 8003ad4: b580 push {r7, lr} 8003ad6: b084 sub sp, #16 8003ad8: af00 add r7, sp, #0 8003ada: 6078 str r0, [r7, #4] 8003adc: 4608 mov r0, r1 8003ade: 4611 mov r1, r2 8003ae0: 461a mov r2, r3 8003ae2: 4603 mov r3, r0 8003ae4: 807b strh r3, [r7, #2] 8003ae6: 460b mov r3, r1 8003ae8: 707b strb r3, [r7, #1] 8003aea: 4613 mov r3, r2 8003aec: 703b strb r3, [r7, #0] uint16_t crc = 0; 8003aee: 2300 movs r3, #0 8003af0: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 8003af2: 2300 movs r3, #0 8003af4: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 8003af6: 787b ldrb r3, [r7, #1] 8003af8: b21a sxth r2, r3 8003afa: 4b43 ldr r3, [pc, #268] @ (8003c08 ) 8003afc: 4313 orrs r3, r2 8003afe: b21b sxth r3, r3 8003b00: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 8003b02: 8bbb ldrh r3, [r7, #28] 8003b04: 461a mov r2, r3 8003b06: 2100 movs r1, #0 8003b08: 6878 ldr r0, [r7, #4] 8003b0a: f014 fbfd bl 8018308 txBuffer[txBufferPos++] = FRAME_INDICATOR; 8003b0e: 89fb ldrh r3, [r7, #14] 8003b10: 1c5a adds r2, r3, #1 8003b12: 81fa strh r2, [r7, #14] 8003b14: 461a mov r2, r3 8003b16: 687b ldr r3, [r7, #4] 8003b18: 4413 add r3, r2 8003b1a: 22aa movs r2, #170 @ 0xaa 8003b1c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 8003b1e: 89fb ldrh r3, [r7, #14] 8003b20: 1c5a adds r2, r3, #1 8003b22: 81fa strh r2, [r7, #14] 8003b24: 461a mov r2, r3 8003b26: 687b ldr r3, [r7, #4] 8003b28: 4413 add r3, r2 8003b2a: 887a ldrh r2, [r7, #2] 8003b2c: b2d2 uxtb r2, r2 8003b2e: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 8003b30: 887b ldrh r3, [r7, #2] 8003b32: 0a1b lsrs r3, r3, #8 8003b34: b29a uxth r2, r3 8003b36: 89fb ldrh r3, [r7, #14] 8003b38: 1c59 adds r1, r3, #1 8003b3a: 81f9 strh r1, [r7, #14] 8003b3c: 4619 mov r1, r3 8003b3e: 687b ldr r3, [r7, #4] 8003b40: 440b add r3, r1 8003b42: b2d2 uxtb r2, r2 8003b44: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 8003b46: 89fb ldrh r3, [r7, #14] 8003b48: 1c5a adds r2, r3, #1 8003b4a: 81fa strh r2, [r7, #14] 8003b4c: 461a mov r2, r3 8003b4e: 687b ldr r3, [r7, #4] 8003b50: 4413 add r3, r2 8003b52: 897a ldrh r2, [r7, #10] 8003b54: b2d2 uxtb r2, r2 8003b56: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 8003b58: 897b ldrh r3, [r7, #10] 8003b5a: 0a1b lsrs r3, r3, #8 8003b5c: b29a uxth r2, r3 8003b5e: 89fb ldrh r3, [r7, #14] 8003b60: 1c59 adds r1, r3, #1 8003b62: 81f9 strh r1, [r7, #14] 8003b64: 4619 mov r1, r3 8003b66: 687b ldr r3, [r7, #4] 8003b68: 440b add r3, r1 8003b6a: b2d2 uxtb r2, r2 8003b6c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 8003b6e: 89fb ldrh r3, [r7, #14] 8003b70: 1c5a adds r2, r3, #1 8003b72: 81fa strh r2, [r7, #14] 8003b74: 461a mov r2, r3 8003b76: 687b ldr r3, [r7, #4] 8003b78: 4413 add r3, r2 8003b7a: 8bba ldrh r2, [r7, #28] 8003b7c: b2d2 uxtb r2, r2 8003b7e: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 8003b80: 8bbb ldrh r3, [r7, #28] 8003b82: 0a1b lsrs r3, r3, #8 8003b84: b29a uxth r2, r3 8003b86: 89fb ldrh r3, [r7, #14] 8003b88: 1c59 adds r1, r3, #1 8003b8a: 81f9 strh r1, [r7, #14] 8003b8c: 4619 mov r1, r3 8003b8e: 687b ldr r3, [r7, #4] 8003b90: 440b add r3, r1 8003b92: b2d2 uxtb r2, r2 8003b94: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 8003b96: 89fb ldrh r3, [r7, #14] 8003b98: 1c5a adds r2, r3, #1 8003b9a: 81fa strh r2, [r7, #14] 8003b9c: 461a mov r2, r3 8003b9e: 687b ldr r3, [r7, #4] 8003ba0: 4413 add r3, r2 8003ba2: 783a ldrb r2, [r7, #0] 8003ba4: 701a strb r2, [r3, #0] if (dataLength > 0) { 8003ba6: 8bbb ldrh r3, [r7, #28] 8003ba8: 2b00 cmp r3, #0 8003baa: d00b beq.n 8003bc4 memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 8003bac: 89fb ldrh r3, [r7, #14] 8003bae: 687a ldr r2, [r7, #4] 8003bb0: 4413 add r3, r2 8003bb2: 8bba ldrh r2, [r7, #28] 8003bb4: 69b9 ldr r1, [r7, #24] 8003bb6: 4618 mov r0, r3 8003bb8: f014 fc30 bl 801841c txBufferPos += dataLength; 8003bbc: 89fa ldrh r2, [r7, #14] 8003bbe: 8bbb ldrh r3, [r7, #28] 8003bc0: 4413 add r3, r2 8003bc2: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 8003bc4: 89fb ldrh r3, [r7, #14] 8003bc6: 461a mov r2, r3 8003bc8: 6879 ldr r1, [r7, #4] 8003bca: 4810 ldr r0, [pc, #64] @ (8003c0c ) 8003bcc: f004 f8d0 bl 8007d70 8003bd0: 4603 mov r3, r0 8003bd2: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 8003bd4: 89fb ldrh r3, [r7, #14] 8003bd6: 1c5a adds r2, r3, #1 8003bd8: 81fa strh r2, [r7, #14] 8003bda: 461a mov r2, r3 8003bdc: 687b ldr r3, [r7, #4] 8003bde: 4413 add r3, r2 8003be0: 89ba ldrh r2, [r7, #12] 8003be2: b2d2 uxtb r2, r2 8003be4: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 8003be6: 89bb ldrh r3, [r7, #12] 8003be8: 0a1b lsrs r3, r3, #8 8003bea: b29a uxth r2, r3 8003bec: 89fb ldrh r3, [r7, #14] 8003bee: 1c59 adds r1, r3, #1 8003bf0: 81f9 strh r1, [r7, #14] 8003bf2: 4619 mov r1, r3 8003bf4: 687b ldr r3, [r7, #4] 8003bf6: 440b add r3, r1 8003bf8: b2d2 uxtb r2, r2 8003bfa: 701a strb r2, [r3, #0] return txBufferPos; 8003bfc: 89fb ldrh r3, [r7, #14] } 8003bfe: 4618 mov r0, r3 8003c00: 3710 adds r7, #16 8003c02: 46bd mov sp, r7 8003c04: bd80 pop {r7, pc} 8003c06: bf00 nop 8003c08: ffff8000 .word 0xffff8000 8003c0c: 240003e0 .word 0x240003e0 08003c10 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8003c10: b580 push {r7, lr} 8003c12: b086 sub sp, #24 8003c14: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; 8003c16: f107 0310 add.w r3, r7, #16 8003c1a: 2200 movs r2, #0 8003c1c: 601a str r2, [r3, #0] 8003c1e: 605a str r2, [r3, #4] PWR_PVDTypeDef sConfigPVD = {0}; 8003c20: f107 0308 add.w r3, r7, #8 8003c24: 2200 movs r2, #0 8003c26: 601a str r2, [r3, #0] 8003c28: 605a str r2, [r3, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 8003c2a: 4b26 ldr r3, [pc, #152] @ (8003cc4 ) 8003c2c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c30: 4a24 ldr r2, [pc, #144] @ (8003cc4 ) 8003c32: f043 0302 orr.w r3, r3, #2 8003c36: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003c3a: 4b22 ldr r3, [pc, #136] @ (8003cc4 ) 8003c3c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c40: f003 0302 and.w r3, r3, #2 8003c44: 607b str r3, [r7, #4] 8003c46: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8003c48: 2200 movs r2, #0 8003c4a: 210f movs r1, #15 8003c4c: f06f 0001 mvn.w r0, #1 8003c50: f003 ff8a bl 8007b68 /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8003c54: 2200 movs r2, #0 8003c56: 2105 movs r1, #5 8003c58: 2005 movs r0, #5 8003c5a: f003 ff85 bl 8007b68 HAL_NVIC_EnableIRQ(RCC_IRQn); 8003c5e: 2005 movs r0, #5 8003c60: f003 ff9c bl 8007b9c /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 8003c64: f44f 23c0 mov.w r3, #393216 @ 0x60000 8003c68: 613b str r3, [r7, #16] sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; 8003c6a: 2300 movs r3, #0 8003c6c: 617b str r3, [r7, #20] HAL_PWREx_ConfigAVD(&sConfigAVD); 8003c6e: f107 0310 add.w r3, r7, #16 8003c72: 4618 mov r0, r3 8003c74: f007 fde2 bl 800b83c /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 8003c78: f007 fe56 bl 800b928 /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 8003c7c: 23c0 movs r3, #192 @ 0xc0 8003c7e: 60bb str r3, [r7, #8] sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; 8003c80: 2300 movs r3, #0 8003c82: 60fb str r3, [r7, #12] HAL_PWR_ConfigPVD(&sConfigPVD); 8003c84: f107 0308 add.w r3, r7, #8 8003c88: 4618 mov r0, r3 8003c8a: f007 fd13 bl 800b6b4 /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 8003c8e: f007 fd8b bl 800b7a8 /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 8003c92: 4b0c ldr r3, [pc, #48] @ (8003cc4 ) 8003c94: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c98: 4a0a ldr r2, [pc, #40] @ (8003cc4 ) 8003c9a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8003c9e: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003ca2: 4b08 ldr r3, [pc, #32] @ (8003cc4 ) 8003ca4: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003ca8: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003cac: 603b str r3, [r7, #0] 8003cae: 683b ldr r3, [r7, #0] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 8003cb0: f002 f8e0 bl 8005e74 /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 8003cb4: 2002 movs r0, #2 8003cb6: f002 f8c9 bl 8005e4c /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8003cba: bf00 nop 8003cbc: 3718 adds r7, #24 8003cbe: 46bd mov sp, r7 8003cc0: bd80 pop {r7, pc} 8003cc2: bf00 nop 8003cc4: 58024400 .word 0x58024400 08003cc8 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8003cc8: b580 push {r7, lr} 8003cca: b092 sub sp, #72 @ 0x48 8003ccc: af00 add r7, sp, #0 8003cce: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003cd0: f107 0334 add.w r3, r7, #52 @ 0x34 8003cd4: 2200 movs r2, #0 8003cd6: 601a str r2, [r3, #0] 8003cd8: 605a str r2, [r3, #4] 8003cda: 609a str r2, [r3, #8] 8003cdc: 60da str r2, [r3, #12] 8003cde: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8003ce0: 687b ldr r3, [r7, #4] 8003ce2: 681b ldr r3, [r3, #0] 8003ce4: 4a9d ldr r2, [pc, #628] @ (8003f5c ) 8003ce6: 4293 cmp r3, r2 8003ce8: f040 8099 bne.w 8003e1e { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8003cec: 4b9c ldr r3, [pc, #624] @ (8003f60 ) 8003cee: 681b ldr r3, [r3, #0] 8003cf0: 3301 adds r3, #1 8003cf2: 4a9b ldr r2, [pc, #620] @ (8003f60 ) 8003cf4: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003cf6: 4b9a ldr r3, [pc, #616] @ (8003f60 ) 8003cf8: 681b ldr r3, [r3, #0] 8003cfa: 2b01 cmp r3, #1 8003cfc: d10e bne.n 8003d1c __HAL_RCC_ADC12_CLK_ENABLE(); 8003cfe: 4b99 ldr r3, [pc, #612] @ (8003f64 ) 8003d00: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003d04: 4a97 ldr r2, [pc, #604] @ (8003f64 ) 8003d06: f043 0320 orr.w r3, r3, #32 8003d0a: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003d0e: 4b95 ldr r3, [pc, #596] @ (8003f64 ) 8003d10: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003d14: f003 0320 and.w r3, r3, #32 8003d18: 633b str r3, [r7, #48] @ 0x30 8003d1a: 6b3b ldr r3, [r7, #48] @ 0x30 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8003d1c: 4b91 ldr r3, [pc, #580] @ (8003f64 ) 8003d1e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d22: 4a90 ldr r2, [pc, #576] @ (8003f64 ) 8003d24: f043 0301 orr.w r3, r3, #1 8003d28: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d2c: 4b8d ldr r3, [pc, #564] @ (8003f64 ) 8003d2e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d32: f003 0301 and.w r3, r3, #1 8003d36: 62fb str r3, [r7, #44] @ 0x2c 8003d38: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 8003d3a: 4b8a ldr r3, [pc, #552] @ (8003f64 ) 8003d3c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d40: 4a88 ldr r2, [pc, #544] @ (8003f64 ) 8003d42: f043 0304 orr.w r3, r3, #4 8003d46: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d4a: 4b86 ldr r3, [pc, #536] @ (8003f64 ) 8003d4c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d50: f003 0304 and.w r3, r3, #4 8003d54: 62bb str r3, [r7, #40] @ 0x28 8003d56: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOB_CLK_ENABLE(); 8003d58: 4b82 ldr r3, [pc, #520] @ (8003f64 ) 8003d5a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d5e: 4a81 ldr r2, [pc, #516] @ (8003f64 ) 8003d60: f043 0302 orr.w r3, r3, #2 8003d64: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d68: 4b7e ldr r3, [pc, #504] @ (8003f64 ) 8003d6a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d6e: f003 0302 and.w r3, r3, #2 8003d72: 627b str r3, [r7, #36] @ 0x24 8003d74: 6a7b ldr r3, [r7, #36] @ 0x24 PA3 ------> ADC1_INP15 PA7 ------> ADC1_INP7 PC5 ------> ADC1_INP8 PB0 ------> ADC1_INP9 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 8003d76: 238f movs r3, #143 @ 0x8f 8003d78: 637b str r3, [r7, #52] @ 0x34 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003d7a: 2303 movs r3, #3 8003d7c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d7e: 2300 movs r3, #0 8003d80: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003d82: f107 0334 add.w r3, r7, #52 @ 0x34 8003d86: 4619 mov r1, r3 8003d88: 4877 ldr r0, [pc, #476] @ (8003f68 ) 8003d8a: f007 fa1f bl 800b1cc GPIO_InitStruct.Pin = GPIO_PIN_5; 8003d8e: 2320 movs r3, #32 8003d90: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003d92: 2303 movs r3, #3 8003d94: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d96: 2300 movs r3, #0 8003d98: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003d9a: f107 0334 add.w r3, r7, #52 @ 0x34 8003d9e: 4619 mov r1, r3 8003da0: 4872 ldr r0, [pc, #456] @ (8003f6c ) 8003da2: f007 fa13 bl 800b1cc GPIO_InitStruct.Pin = GPIO_PIN_0; 8003da6: 2301 movs r3, #1 8003da8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003daa: 2303 movs r3, #3 8003dac: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003dae: 2300 movs r3, #0 8003db0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003db2: f107 0334 add.w r3, r7, #52 @ 0x34 8003db6: 4619 mov r1, r3 8003db8: 486d ldr r0, [pc, #436] @ (8003f70 ) 8003dba: f007 fa07 bl 800b1cc /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Stream0; 8003dbe: 4b6d ldr r3, [pc, #436] @ (8003f74 ) 8003dc0: 4a6d ldr r2, [pc, #436] @ (8003f78 ) 8003dc2: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8003dc4: 4b6b ldr r3, [pc, #428] @ (8003f74 ) 8003dc6: 2209 movs r2, #9 8003dc8: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003dca: 4b6a ldr r3, [pc, #424] @ (8003f74 ) 8003dcc: 2200 movs r2, #0 8003dce: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8003dd0: 4b68 ldr r3, [pc, #416] @ (8003f74 ) 8003dd2: 2200 movs r2, #0 8003dd4: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8003dd6: 4b67 ldr r3, [pc, #412] @ (8003f74 ) 8003dd8: f44f 6280 mov.w r2, #1024 @ 0x400 8003ddc: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003dde: 4b65 ldr r3, [pc, #404] @ (8003f74 ) 8003de0: f44f 6200 mov.w r2, #2048 @ 0x800 8003de4: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003de6: 4b63 ldr r3, [pc, #396] @ (8003f74 ) 8003de8: f44f 5200 mov.w r2, #8192 @ 0x2000 8003dec: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 8003dee: 4b61 ldr r3, [pc, #388] @ (8003f74 ) 8003df0: 2200 movs r2, #0 8003df2: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8003df4: 4b5f ldr r3, [pc, #380] @ (8003f74 ) 8003df6: 2200 movs r2, #0 8003df8: 621a str r2, [r3, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003dfa: 4b5e ldr r3, [pc, #376] @ (8003f74 ) 8003dfc: 2200 movs r2, #0 8003dfe: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8003e00: 485c ldr r0, [pc, #368] @ (8003f74 ) 8003e02: f004 fba7 bl 8008554 8003e06: 4603 mov r3, r0 8003e08: 2b00 cmp r3, #0 8003e0a: d001 beq.n 8003e10 { Error_Handler(); 8003e0c: f7fe f85e bl 8001ecc } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8003e10: 687b ldr r3, [r7, #4] 8003e12: 4a58 ldr r2, [pc, #352] @ (8003f74 ) 8003e14: 64da str r2, [r3, #76] @ 0x4c 8003e16: 4a57 ldr r2, [pc, #348] @ (8003f74 ) 8003e18: 687b ldr r3, [r7, #4] 8003e1a: 6393 str r3, [r2, #56] @ 0x38 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 8003e1c: e11e b.n 800405c else if(hadc->Instance==ADC2) 8003e1e: 687b ldr r3, [r7, #4] 8003e20: 681b ldr r3, [r3, #0] 8003e22: 4a56 ldr r2, [pc, #344] @ (8003f7c ) 8003e24: 4293 cmp r3, r2 8003e26: f040 80af bne.w 8003f88 HAL_RCC_ADC12_CLK_ENABLED++; 8003e2a: 4b4d ldr r3, [pc, #308] @ (8003f60 ) 8003e2c: 681b ldr r3, [r3, #0] 8003e2e: 3301 adds r3, #1 8003e30: 4a4b ldr r2, [pc, #300] @ (8003f60 ) 8003e32: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003e34: 4b4a ldr r3, [pc, #296] @ (8003f60 ) 8003e36: 681b ldr r3, [r3, #0] 8003e38: 2b01 cmp r3, #1 8003e3a: d10e bne.n 8003e5a __HAL_RCC_ADC12_CLK_ENABLE(); 8003e3c: 4b49 ldr r3, [pc, #292] @ (8003f64 ) 8003e3e: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003e42: 4a48 ldr r2, [pc, #288] @ (8003f64 ) 8003e44: f043 0320 orr.w r3, r3, #32 8003e48: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003e4c: 4b45 ldr r3, [pc, #276] @ (8003f64 ) 8003e4e: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003e52: f003 0320 and.w r3, r3, #32 8003e56: 623b str r3, [r7, #32] 8003e58: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003e5a: 4b42 ldr r3, [pc, #264] @ (8003f64 ) 8003e5c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e60: 4a40 ldr r2, [pc, #256] @ (8003f64 ) 8003e62: f043 0301 orr.w r3, r3, #1 8003e66: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e6a: 4b3e ldr r3, [pc, #248] @ (8003f64 ) 8003e6c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e70: f003 0301 and.w r3, r3, #1 8003e74: 61fb str r3, [r7, #28] 8003e76: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003e78: 4b3a ldr r3, [pc, #232] @ (8003f64 ) 8003e7a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e7e: 4a39 ldr r2, [pc, #228] @ (8003f64 ) 8003e80: f043 0304 orr.w r3, r3, #4 8003e84: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e88: 4b36 ldr r3, [pc, #216] @ (8003f64 ) 8003e8a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e8e: f003 0304 and.w r3, r3, #4 8003e92: 61bb str r3, [r7, #24] 8003e94: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003e96: 4b33 ldr r3, [pc, #204] @ (8003f64 ) 8003e98: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e9c: 4a31 ldr r2, [pc, #196] @ (8003f64 ) 8003e9e: f043 0302 orr.w r3, r3, #2 8003ea2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003ea6: 4b2f ldr r3, [pc, #188] @ (8003f64 ) 8003ea8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003eac: f003 0302 and.w r3, r3, #2 8003eb0: 617b str r3, [r7, #20] 8003eb2: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_6; 8003eb4: 2340 movs r3, #64 @ 0x40 8003eb6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003eb8: 2303 movs r3, #3 8003eba: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003ebc: 2300 movs r3, #0 8003ebe: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003ec0: f107 0334 add.w r3, r7, #52 @ 0x34 8003ec4: 4619 mov r1, r3 8003ec6: 4828 ldr r0, [pc, #160] @ (8003f68 ) 8003ec8: f007 f980 bl 800b1cc GPIO_InitStruct.Pin = GPIO_PIN_4; 8003ecc: 2310 movs r3, #16 8003ece: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003ed0: 2303 movs r3, #3 8003ed2: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003ed4: 2300 movs r3, #0 8003ed6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003ed8: f107 0334 add.w r3, r7, #52 @ 0x34 8003edc: 4619 mov r1, r3 8003ede: 4823 ldr r0, [pc, #140] @ (8003f6c ) 8003ee0: f007 f974 bl 800b1cc GPIO_InitStruct.Pin = GPIO_PIN_1; 8003ee4: 2302 movs r3, #2 8003ee6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003ee8: 2303 movs r3, #3 8003eea: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003eec: 2300 movs r3, #0 8003eee: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003ef0: f107 0334 add.w r3, r7, #52 @ 0x34 8003ef4: 4619 mov r1, r3 8003ef6: 481e ldr r0, [pc, #120] @ (8003f70 ) 8003ef8: f007 f968 bl 800b1cc hdma_adc2.Instance = DMA1_Stream1; 8003efc: 4b20 ldr r3, [pc, #128] @ (8003f80 ) 8003efe: 4a21 ldr r2, [pc, #132] @ (8003f84 ) 8003f00: 601a str r2, [r3, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8003f02: 4b1f ldr r3, [pc, #124] @ (8003f80 ) 8003f04: 220a movs r2, #10 8003f06: 605a str r2, [r3, #4] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003f08: 4b1d ldr r3, [pc, #116] @ (8003f80 ) 8003f0a: 2200 movs r2, #0 8003f0c: 609a str r2, [r3, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8003f0e: 4b1c ldr r3, [pc, #112] @ (8003f80 ) 8003f10: 2200 movs r2, #0 8003f12: 60da str r2, [r3, #12] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8003f14: 4b1a ldr r3, [pc, #104] @ (8003f80 ) 8003f16: f44f 6280 mov.w r2, #1024 @ 0x400 8003f1a: 611a str r2, [r3, #16] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003f1c: 4b18 ldr r3, [pc, #96] @ (8003f80 ) 8003f1e: f44f 6200 mov.w r2, #2048 @ 0x800 8003f22: 615a str r2, [r3, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003f24: 4b16 ldr r3, [pc, #88] @ (8003f80 ) 8003f26: f44f 5200 mov.w r2, #8192 @ 0x2000 8003f2a: 619a str r2, [r3, #24] hdma_adc2.Init.Mode = DMA_NORMAL; 8003f2c: 4b14 ldr r3, [pc, #80] @ (8003f80 ) 8003f2e: 2200 movs r2, #0 8003f30: 61da str r2, [r3, #28] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8003f32: 4b13 ldr r3, [pc, #76] @ (8003f80 ) 8003f34: 2200 movs r2, #0 8003f36: 621a str r2, [r3, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003f38: 4b11 ldr r3, [pc, #68] @ (8003f80 ) 8003f3a: 2200 movs r2, #0 8003f3c: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8003f3e: 4810 ldr r0, [pc, #64] @ (8003f80 ) 8003f40: f004 fb08 bl 8008554 8003f44: 4603 mov r3, r0 8003f46: 2b00 cmp r3, #0 8003f48: d001 beq.n 8003f4e Error_Handler(); 8003f4a: f7fd ffbf bl 8001ecc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8003f4e: 687b ldr r3, [r7, #4] 8003f50: 4a0b ldr r2, [pc, #44] @ (8003f80 ) 8003f52: 64da str r2, [r3, #76] @ 0x4c 8003f54: 4a0a ldr r2, [pc, #40] @ (8003f80 ) 8003f56: 687b ldr r3, [r7, #4] 8003f58: 6393 str r3, [r2, #56] @ 0x38 } 8003f5a: e07f b.n 800405c 8003f5c: 40022000 .word 0x40022000 8003f60: 2400091c .word 0x2400091c 8003f64: 58024400 .word 0x58024400 8003f68: 58020000 .word 0x58020000 8003f6c: 58020800 .word 0x58020800 8003f70: 58020400 .word 0x58020400 8003f74: 2400024c .word 0x2400024c 8003f78: 40020010 .word 0x40020010 8003f7c: 40022100 .word 0x40022100 8003f80: 240002c4 .word 0x240002c4 8003f84: 40020028 .word 0x40020028 else if(hadc->Instance==ADC3) 8003f88: 687b ldr r3, [r7, #4] 8003f8a: 681b ldr r3, [r3, #0] 8003f8c: 4a35 ldr r2, [pc, #212] @ (8004064 ) 8003f8e: 4293 cmp r3, r2 8003f90: d164 bne.n 800405c __HAL_RCC_ADC3_CLK_ENABLE(); 8003f92: 4b35 ldr r3, [pc, #212] @ (8004068 ) 8003f94: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003f98: 4a33 ldr r2, [pc, #204] @ (8004068 ) 8003f9a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8003f9e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003fa2: 4b31 ldr r3, [pc, #196] @ (8004068 ) 8003fa4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fa8: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8003fac: 613b str r3, [r7, #16] 8003fae: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003fb0: 4b2d ldr r3, [pc, #180] @ (8004068 ) 8003fb2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fb6: 4a2c ldr r2, [pc, #176] @ (8004068 ) 8003fb8: f043 0304 orr.w r3, r3, #4 8003fbc: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003fc0: 4b29 ldr r3, [pc, #164] @ (8004068 ) 8003fc2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fc6: f003 0304 and.w r3, r3, #4 8003fca: 60fb str r3, [r7, #12] 8003fcc: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8003fce: 2303 movs r3, #3 8003fd0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003fd2: 2303 movs r3, #3 8003fd4: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003fd6: 2300 movs r3, #0 8003fd8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003fda: f107 0334 add.w r3, r7, #52 @ 0x34 8003fde: 4619 mov r1, r3 8003fe0: 4822 ldr r0, [pc, #136] @ (800406c ) 8003fe2: f007 f8f3 bl 800b1cc HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 8003fe6: f04f 6180 mov.w r1, #67108864 @ 0x4000000 8003fea: f04f 6080 mov.w r0, #67108864 @ 0x4000000 8003fee: f001 ff51 bl 8005e94 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 8003ff2: f04f 6100 mov.w r1, #134217728 @ 0x8000000 8003ff6: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8003ffa: f001 ff4b bl 8005e94 hdma_adc3.Instance = DMA1_Stream2; 8003ffe: 4b1c ldr r3, [pc, #112] @ (8004070 ) 8004000: 4a1c ldr r2, [pc, #112] @ (8004074 ) 8004002: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 8004004: 4b1a ldr r3, [pc, #104] @ (8004070 ) 8004006: 2273 movs r2, #115 @ 0x73 8004008: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 800400a: 4b19 ldr r3, [pc, #100] @ (8004070 ) 800400c: 2200 movs r2, #0 800400e: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8004010: 4b17 ldr r3, [pc, #92] @ (8004070 ) 8004012: 2200 movs r2, #0 8004014: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 8004016: 4b16 ldr r3, [pc, #88] @ (8004070 ) 8004018: f44f 6280 mov.w r2, #1024 @ 0x400 800401c: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 800401e: 4b14 ldr r3, [pc, #80] @ (8004070 ) 8004020: f44f 6200 mov.w r2, #2048 @ 0x800 8004024: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8004026: 4b12 ldr r3, [pc, #72] @ (8004070 ) 8004028: f44f 5200 mov.w r2, #8192 @ 0x2000 800402c: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_NORMAL; 800402e: 4b10 ldr r3, [pc, #64] @ (8004070 ) 8004030: 2200 movs r2, #0 8004032: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 8004034: 4b0e ldr r3, [pc, #56] @ (8004070 ) 8004036: 2200 movs r2, #0 8004038: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 800403a: 4b0d ldr r3, [pc, #52] @ (8004070 ) 800403c: 2200 movs r2, #0 800403e: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8004040: 480b ldr r0, [pc, #44] @ (8004070 ) 8004042: f004 fa87 bl 8008554 8004046: 4603 mov r3, r0 8004048: 2b00 cmp r3, #0 800404a: d001 beq.n 8004050 Error_Handler(); 800404c: f7fd ff3e bl 8001ecc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 8004050: 687b ldr r3, [r7, #4] 8004052: 4a07 ldr r2, [pc, #28] @ (8004070 ) 8004054: 64da str r2, [r3, #76] @ 0x4c 8004056: 4a06 ldr r2, [pc, #24] @ (8004070 ) 8004058: 687b ldr r3, [r7, #4] 800405a: 6393 str r3, [r2, #56] @ 0x38 } 800405c: bf00 nop 800405e: 3748 adds r7, #72 @ 0x48 8004060: 46bd mov sp, r7 8004062: bd80 pop {r7, pc} 8004064: 58026000 .word 0x58026000 8004068: 58024400 .word 0x58024400 800406c: 58020800 .word 0x58020800 8004070: 2400033c .word 0x2400033c 8004074: 40020040 .word 0x40020040 08004078 : * This function configures the hardware resources used in this example * @param hcomp: COMP handle pointer * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { 8004078: b580 push {r7, lr} 800407a: b08a sub sp, #40 @ 0x28 800407c: af00 add r7, sp, #0 800407e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004080: f107 0314 add.w r3, r7, #20 8004084: 2200 movs r2, #0 8004086: 601a str r2, [r3, #0] 8004088: 605a str r2, [r3, #4] 800408a: 609a str r2, [r3, #8] 800408c: 60da str r2, [r3, #12] 800408e: 611a str r2, [r3, #16] if(hcomp->Instance==COMP1) 8004090: 687b ldr r3, [r7, #4] 8004092: 681b ldr r3, [r3, #0] 8004094: 4a18 ldr r2, [pc, #96] @ (80040f8 ) 8004096: 4293 cmp r3, r2 8004098: d129 bne.n 80040ee { /* USER CODE BEGIN COMP1_MspInit 0 */ /* USER CODE END COMP1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_COMP12_CLK_ENABLE(); 800409a: 4b18 ldr r3, [pc, #96] @ (80040fc ) 800409c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80040a0: 4a16 ldr r2, [pc, #88] @ (80040fc ) 80040a2: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80040a6: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 80040aa: 4b14 ldr r3, [pc, #80] @ (80040fc ) 80040ac: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80040b0: f403 4380 and.w r3, r3, #16384 @ 0x4000 80040b4: 613b str r3, [r7, #16] 80040b6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80040b8: 4b10 ldr r3, [pc, #64] @ (80040fc ) 80040ba: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80040be: 4a0f ldr r2, [pc, #60] @ (80040fc ) 80040c0: f043 0302 orr.w r3, r3, #2 80040c4: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80040c8: 4b0c ldr r3, [pc, #48] @ (80040fc ) 80040ca: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80040ce: f003 0302 and.w r3, r3, #2 80040d2: 60fb str r3, [r7, #12] 80040d4: 68fb ldr r3, [r7, #12] /**COMP1 GPIO Configuration PB2 ------> COMP1_INP */ GPIO_InitStruct.Pin = GPIO_PIN_2; 80040d6: 2304 movs r3, #4 80040d8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80040da: 2303 movs r3, #3 80040dc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80040de: 2300 movs r3, #0 80040e0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80040e2: f107 0314 add.w r3, r7, #20 80040e6: 4619 mov r1, r3 80040e8: 4805 ldr r0, [pc, #20] @ (8004100 ) 80040ea: f007 f86f bl 800b1cc /* USER CODE BEGIN COMP1_MspInit 1 */ /* USER CODE END COMP1_MspInit 1 */ } } 80040ee: bf00 nop 80040f0: 3728 adds r7, #40 @ 0x28 80040f2: 46bd mov sp, r7 80040f4: bd80 pop {r7, pc} 80040f6: bf00 nop 80040f8: 5800380c .word 0x5800380c 80040fc: 58024400 .word 0x58024400 8004100: 58020400 .word 0x58020400 08004104 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 8004104: b480 push {r7} 8004106: b085 sub sp, #20 8004108: af00 add r7, sp, #0 800410a: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 800410c: 687b ldr r3, [r7, #4] 800410e: 681b ldr r3, [r3, #0] 8004110: 4a0b ldr r2, [pc, #44] @ (8004140 ) 8004112: 4293 cmp r3, r2 8004114: d10e bne.n 8004134 { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8004116: 4b0b ldr r3, [pc, #44] @ (8004144 ) 8004118: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800411c: 4a09 ldr r2, [pc, #36] @ (8004144 ) 800411e: f443 2300 orr.w r3, r3, #524288 @ 0x80000 8004122: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004126: 4b07 ldr r3, [pc, #28] @ (8004144 ) 8004128: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800412c: f403 2300 and.w r3, r3, #524288 @ 0x80000 8004130: 60fb str r3, [r7, #12] 8004132: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 8004134: bf00 nop 8004136: 3714 adds r7, #20 8004138: 46bd mov sp, r7 800413a: f85d 7b04 ldr.w r7, [sp], #4 800413e: 4770 bx lr 8004140: 58024c00 .word 0x58024c00 8004144: 58024400 .word 0x58024400 08004148 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 8004148: b580 push {r7, lr} 800414a: b08a sub sp, #40 @ 0x28 800414c: af00 add r7, sp, #0 800414e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004150: f107 0314 add.w r3, r7, #20 8004154: 2200 movs r2, #0 8004156: 601a str r2, [r3, #0] 8004158: 605a str r2, [r3, #4] 800415a: 609a str r2, [r3, #8] 800415c: 60da str r2, [r3, #12] 800415e: 611a str r2, [r3, #16] if(hdac->Instance==DAC1) 8004160: 687b ldr r3, [r7, #4] 8004162: 681b ldr r3, [r3, #0] 8004164: 4a1c ldr r2, [pc, #112] @ (80041d8 ) 8004166: 4293 cmp r3, r2 8004168: d131 bne.n 80041ce { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); 800416a: 4b1c ldr r3, [pc, #112] @ (80041dc ) 800416c: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004170: 4a1a ldr r2, [pc, #104] @ (80041dc ) 8004172: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8004176: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 800417a: 4b18 ldr r3, [pc, #96] @ (80041dc ) 800417c: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004180: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8004184: 613b str r3, [r7, #16] 8004186: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8004188: 4b14 ldr r3, [pc, #80] @ (80041dc ) 800418a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800418e: 4a13 ldr r2, [pc, #76] @ (80041dc ) 8004190: f043 0301 orr.w r3, r3, #1 8004194: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004198: 4b10 ldr r3, [pc, #64] @ (80041dc ) 800419a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800419e: f003 0301 and.w r3, r3, #1 80041a2: 60fb str r3, [r7, #12] 80041a4: 68fb ldr r3, [r7, #12] /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80041a6: 2330 movs r3, #48 @ 0x30 80041a8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80041aa: 2303 movs r3, #3 80041ac: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80041ae: 2300 movs r3, #0 80041b0: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80041b2: f107 0314 add.w r3, r7, #20 80041b6: 4619 mov r1, r3 80041b8: 4809 ldr r0, [pc, #36] @ (80041e0 ) 80041ba: f007 f807 bl 800b1cc /* DAC1 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 80041be: 2200 movs r2, #0 80041c0: 2105 movs r1, #5 80041c2: 2036 movs r0, #54 @ 0x36 80041c4: f003 fcd0 bl 8007b68 HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 80041c8: 2036 movs r0, #54 @ 0x36 80041ca: f003 fce7 bl 8007b9c /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 80041ce: bf00 nop 80041d0: 3728 adds r7, #40 @ 0x28 80041d2: 46bd mov sp, r7 80041d4: bd80 pop {r7, pc} 80041d6: bf00 nop 80041d8: 40007400 .word 0x40007400 80041dc: 58024400 .word 0x58024400 80041e0: 58020000 .word 0x58020000 080041e4 : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 80041e4: b580 push {r7, lr} 80041e6: b0b4 sub sp, #208 @ 0xd0 80041e8: af00 add r7, sp, #0 80041ea: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80041ec: f107 0310 add.w r3, r7, #16 80041f0: 22c0 movs r2, #192 @ 0xc0 80041f2: 2100 movs r1, #0 80041f4: 4618 mov r0, r3 80041f6: f014 f887 bl 8018308 if(hrng->Instance==RNG) 80041fa: 687b ldr r3, [r7, #4] 80041fc: 681b ldr r3, [r3, #0] 80041fe: 4a14 ldr r2, [pc, #80] @ (8004250 ) 8004200: 4293 cmp r3, r2 8004202: d121 bne.n 8004248 /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 8004204: f44f 3200 mov.w r2, #131072 @ 0x20000 8004208: f04f 0300 mov.w r3, #0 800420c: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 8004210: 2300 movs r3, #0 8004212: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8004216: f107 0310 add.w r3, r7, #16 800421a: 4618 mov r0, r3 800421c: f008 fbbc bl 800c998 8004220: 4603 mov r3, r0 8004222: 2b00 cmp r3, #0 8004224: d001 beq.n 800422a { Error_Handler(); 8004226: f7fd fe51 bl 8001ecc } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 800422a: 4b0a ldr r3, [pc, #40] @ (8004254 ) 800422c: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8004230: 4a08 ldr r2, [pc, #32] @ (8004254 ) 8004232: f043 0340 orr.w r3, r3, #64 @ 0x40 8004236: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 800423a: 4b06 ldr r3, [pc, #24] @ (8004254 ) 800423c: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8004240: f003 0340 and.w r3, r3, #64 @ 0x40 8004244: 60fb str r3, [r7, #12] 8004246: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 8004248: bf00 nop 800424a: 37d0 adds r7, #208 @ 0xd0 800424c: 46bd mov sp, r7 800424e: bd80 pop {r7, pc} 8004250: 48021800 .word 0x48021800 8004254: 58024400 .word 0x58024400 08004258 : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 8004258: b480 push {r7} 800425a: b085 sub sp, #20 800425c: af00 add r7, sp, #0 800425e: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 8004260: 687b ldr r3, [r7, #4] 8004262: 681b ldr r3, [r3, #0] 8004264: 4a16 ldr r2, [pc, #88] @ (80042c0 ) 8004266: 4293 cmp r3, r2 8004268: d10f bne.n 800428a { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 800426a: 4b16 ldr r3, [pc, #88] @ (80042c4 ) 800426c: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004270: 4a14 ldr r2, [pc, #80] @ (80042c4 ) 8004272: f043 0301 orr.w r3, r3, #1 8004276: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 800427a: 4b12 ldr r3, [pc, #72] @ (80042c4 ) 800427c: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004280: f003 0301 and.w r3, r3, #1 8004284: 60fb str r3, [r7, #12] 8004286: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8004288: e013 b.n 80042b2 else if(htim_pwm->Instance==TIM3) 800428a: 687b ldr r3, [r7, #4] 800428c: 681b ldr r3, [r3, #0] 800428e: 4a0e ldr r2, [pc, #56] @ (80042c8 ) 8004290: 4293 cmp r3, r2 8004292: d10e bne.n 80042b2 __HAL_RCC_TIM3_CLK_ENABLE(); 8004294: 4b0b ldr r3, [pc, #44] @ (80042c4 ) 8004296: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800429a: 4a0a ldr r2, [pc, #40] @ (80042c4 ) 800429c: f043 0302 orr.w r3, r3, #2 80042a0: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80042a4: 4b07 ldr r3, [pc, #28] @ (80042c4 ) 80042a6: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80042aa: f003 0302 and.w r3, r3, #2 80042ae: 60bb str r3, [r7, #8] 80042b0: 68bb ldr r3, [r7, #8] } 80042b2: bf00 nop 80042b4: 3714 adds r7, #20 80042b6: 46bd mov sp, r7 80042b8: f85d 7b04 ldr.w r7, [sp], #4 80042bc: 4770 bx lr 80042be: bf00 nop 80042c0: 40010000 .word 0x40010000 80042c4: 58024400 .word 0x58024400 80042c8: 40000400 .word 0x40000400 080042cc : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80042cc: b580 push {r7, lr} 80042ce: b08c sub sp, #48 @ 0x30 80042d0: af00 add r7, sp, #0 80042d2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80042d4: f107 031c add.w r3, r7, #28 80042d8: 2200 movs r2, #0 80042da: 601a str r2, [r3, #0] 80042dc: 605a str r2, [r3, #4] 80042de: 609a str r2, [r3, #8] 80042e0: 60da str r2, [r3, #12] 80042e2: 611a str r2, [r3, #16] if(htim_base->Instance==TIM2) 80042e4: 687b ldr r3, [r7, #4] 80042e6: 681b ldr r3, [r3, #0] 80042e8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80042ec: d137 bne.n 800435e { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 80042ee: 4b46 ldr r3, [pc, #280] @ (8004408 ) 80042f0: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80042f4: 4a44 ldr r2, [pc, #272] @ (8004408 ) 80042f6: f043 0301 orr.w r3, r3, #1 80042fa: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80042fe: 4b42 ldr r3, [pc, #264] @ (8004408 ) 8004300: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004304: f003 0301 and.w r3, r3, #1 8004308: 61bb str r3, [r7, #24] 800430a: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 800430c: 4b3e ldr r3, [pc, #248] @ (8004408 ) 800430e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004312: 4a3d ldr r2, [pc, #244] @ (8004408 ) 8004314: f043 0302 orr.w r3, r3, #2 8004318: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800431c: 4b3a ldr r3, [pc, #232] @ (8004408 ) 800431e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004322: f003 0302 and.w r3, r3, #2 8004326: 617b str r3, [r7, #20] 8004328: 697b ldr r3, [r7, #20] /**TIM2 GPIO Configuration PB10 ------> TIM2_CH3 PB11 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 800432a: f44f 6340 mov.w r3, #3072 @ 0xc00 800432e: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004330: 2302 movs r3, #2 8004332: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004334: 2300 movs r3, #0 8004336: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004338: 2300 movs r3, #0 800433a: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 800433c: 2301 movs r3, #1 800433e: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004340: f107 031c add.w r3, r7, #28 8004344: 4619 mov r1, r3 8004346: 4831 ldr r0, [pc, #196] @ (800440c ) 8004348: f006 ff40 bl 800b1cc /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0); 800434c: 2200 movs r2, #0 800434e: 2105 movs r1, #5 8004350: 201c movs r0, #28 8004352: f003 fc09 bl 8007b68 HAL_NVIC_EnableIRQ(TIM2_IRQn); 8004356: 201c movs r0, #28 8004358: f003 fc20 bl 8007b9c /* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE END TIM8_MspInit 1 */ } } 800435c: e050 b.n 8004400 else if(htim_base->Instance==TIM4) 800435e: 687b ldr r3, [r7, #4] 8004360: 681b ldr r3, [r3, #0] 8004362: 4a2b ldr r2, [pc, #172] @ (8004410 ) 8004364: 4293 cmp r3, r2 8004366: d137 bne.n 80043d8 __HAL_RCC_TIM4_CLK_ENABLE(); 8004368: 4b27 ldr r3, [pc, #156] @ (8004408 ) 800436a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800436e: 4a26 ldr r2, [pc, #152] @ (8004408 ) 8004370: f043 0304 orr.w r3, r3, #4 8004374: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004378: 4b23 ldr r3, [pc, #140] @ (8004408 ) 800437a: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800437e: f003 0304 and.w r3, r3, #4 8004382: 613b str r3, [r7, #16] 8004384: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 8004386: 4b20 ldr r3, [pc, #128] @ (8004408 ) 8004388: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800438c: 4a1e ldr r2, [pc, #120] @ (8004408 ) 800438e: f043 0308 orr.w r3, r3, #8 8004392: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004396: 4b1c ldr r3, [pc, #112] @ (8004408 ) 8004398: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800439c: f003 0308 and.w r3, r3, #8 80043a0: 60fb str r3, [r7, #12] 80043a2: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 80043a4: f44f 4340 mov.w r3, #49152 @ 0xc000 80043a8: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80043aa: 2302 movs r3, #2 80043ac: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80043ae: 2300 movs r3, #0 80043b0: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80043b2: 2300 movs r3, #0 80043b4: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; 80043b6: 2302 movs r3, #2 80043b8: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80043ba: f107 031c add.w r3, r7, #28 80043be: 4619 mov r1, r3 80043c0: 4814 ldr r0, [pc, #80] @ (8004414 ) 80043c2: f006 ff03 bl 800b1cc HAL_NVIC_SetPriority(TIM4_IRQn, 5, 0); 80043c6: 2200 movs r2, #0 80043c8: 2105 movs r1, #5 80043ca: 201e movs r0, #30 80043cc: f003 fbcc bl 8007b68 HAL_NVIC_EnableIRQ(TIM4_IRQn); 80043d0: 201e movs r0, #30 80043d2: f003 fbe3 bl 8007b9c } 80043d6: e013 b.n 8004400 else if(htim_base->Instance==TIM8) 80043d8: 687b ldr r3, [r7, #4] 80043da: 681b ldr r3, [r3, #0] 80043dc: 4a0e ldr r2, [pc, #56] @ (8004418 ) 80043de: 4293 cmp r3, r2 80043e0: d10e bne.n 8004400 __HAL_RCC_TIM8_CLK_ENABLE(); 80043e2: 4b09 ldr r3, [pc, #36] @ (8004408 ) 80043e4: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80043e8: 4a07 ldr r2, [pc, #28] @ (8004408 ) 80043ea: f043 0302 orr.w r3, r3, #2 80043ee: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80043f2: 4b05 ldr r3, [pc, #20] @ (8004408 ) 80043f4: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80043f8: f003 0302 and.w r3, r3, #2 80043fc: 60bb str r3, [r7, #8] 80043fe: 68bb ldr r3, [r7, #8] } 8004400: bf00 nop 8004402: 3730 adds r7, #48 @ 0x30 8004404: 46bd mov sp, r7 8004406: bd80 pop {r7, pc} 8004408: 58024400 .word 0x58024400 800440c: 58020400 .word 0x58020400 8004410: 40000800 .word 0x40000800 8004414: 58020c00 .word 0x58020c00 8004418: 40010400 .word 0x40010400 0800441c : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 800441c: b580 push {r7, lr} 800441e: b08a sub sp, #40 @ 0x28 8004420: af00 add r7, sp, #0 8004422: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004424: f107 0314 add.w r3, r7, #20 8004428: 2200 movs r2, #0 800442a: 601a str r2, [r3, #0] 800442c: 605a str r2, [r3, #4] 800442e: 609a str r2, [r3, #8] 8004430: 60da str r2, [r3, #12] 8004432: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 8004434: 687b ldr r3, [r7, #4] 8004436: 681b ldr r3, [r3, #0] 8004438: 4a26 ldr r2, [pc, #152] @ (80044d4 ) 800443a: 4293 cmp r3, r2 800443c: d120 bne.n 8004480 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800443e: 4b26 ldr r3, [pc, #152] @ (80044d8 ) 8004440: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004444: 4a24 ldr r2, [pc, #144] @ (80044d8 ) 8004446: f043 0301 orr.w r3, r3, #1 800444a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800444e: 4b22 ldr r3, [pc, #136] @ (80044d8 ) 8004450: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004454: f003 0301 and.w r3, r3, #1 8004458: 613b str r3, [r7, #16] 800445a: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 800445c: f44f 7300 mov.w r3, #512 @ 0x200 8004460: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004462: 2302 movs r3, #2 8004464: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8004466: 2300 movs r3, #0 8004468: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800446a: 2300 movs r3, #0 800446c: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 800446e: 2301 movs r3, #1 8004470: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8004472: f107 0314 add.w r3, r7, #20 8004476: 4619 mov r1, r3 8004478: 4818 ldr r0, [pc, #96] @ (80044dc ) 800447a: f006 fea7 bl 800b1cc /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 800447e: e024 b.n 80044ca else if(htim->Instance==TIM3) 8004480: 687b ldr r3, [r7, #4] 8004482: 681b ldr r3, [r3, #0] 8004484: 4a16 ldr r2, [pc, #88] @ (80044e0 ) 8004486: 4293 cmp r3, r2 8004488: d11f bne.n 80044ca __HAL_RCC_GPIOC_CLK_ENABLE(); 800448a: 4b13 ldr r3, [pc, #76] @ (80044d8 ) 800448c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004490: 4a11 ldr r2, [pc, #68] @ (80044d8 ) 8004492: f043 0304 orr.w r3, r3, #4 8004496: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800449a: 4b0f ldr r3, [pc, #60] @ (80044d8 ) 800449c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80044a0: f003 0304 and.w r3, r3, #4 80044a4: 60fb str r3, [r7, #12] 80044a6: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80044a8: f44f 7370 mov.w r3, #960 @ 0x3c0 80044ac: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80044ae: 2302 movs r3, #2 80044b0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80044b2: 2300 movs r3, #0 80044b4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 80044b6: 2301 movs r3, #1 80044b8: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 80044ba: 2302 movs r3, #2 80044bc: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80044be: f107 0314 add.w r3, r7, #20 80044c2: 4619 mov r1, r3 80044c4: 4807 ldr r0, [pc, #28] @ (80044e4 ) 80044c6: f006 fe81 bl 800b1cc } 80044ca: bf00 nop 80044cc: 3728 adds r7, #40 @ 0x28 80044ce: 46bd mov sp, r7 80044d0: bd80 pop {r7, pc} 80044d2: bf00 nop 80044d4: 40010000 .word 0x40010000 80044d8: 58024400 .word 0x58024400 80044dc: 58020000 .word 0x58020000 80044e0: 40000400 .word 0x40000400 80044e4: 58020800 .word 0x58020800 080044e8 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 80044e8: b580 push {r7, lr} 80044ea: b0bc sub sp, #240 @ 0xf0 80044ec: af00 add r7, sp, #0 80044ee: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80044f0: f107 03dc add.w r3, r7, #220 @ 0xdc 80044f4: 2200 movs r2, #0 80044f6: 601a str r2, [r3, #0] 80044f8: 605a str r2, [r3, #4] 80044fa: 609a str r2, [r3, #8] 80044fc: 60da str r2, [r3, #12] 80044fe: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8004500: f107 0318 add.w r3, r7, #24 8004504: 22c0 movs r2, #192 @ 0xc0 8004506: 2100 movs r1, #0 8004508: 4618 mov r0, r3 800450a: f013 fefd bl 8018308 if(huart->Instance==UART8) 800450e: 687b ldr r3, [r7, #4] 8004510: 681b ldr r3, [r3, #0] 8004512: 4a55 ldr r2, [pc, #340] @ (8004668 ) 8004514: 4293 cmp r3, r2 8004516: d14e bne.n 80045b6 /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8004518: f04f 0202 mov.w r2, #2 800451c: f04f 0300 mov.w r3, #0 8004520: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 8004524: 2300 movs r3, #0 8004526: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800452a: f107 0318 add.w r3, r7, #24 800452e: 4618 mov r0, r3 8004530: f008 fa32 bl 800c998 8004534: 4603 mov r3, r0 8004536: 2b00 cmp r3, #0 8004538: d001 beq.n 800453e { Error_Handler(); 800453a: f7fd fcc7 bl 8001ecc } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 800453e: 4b4b ldr r3, [pc, #300] @ (800466c ) 8004540: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004544: 4a49 ldr r2, [pc, #292] @ (800466c ) 8004546: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800454a: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 800454e: 4b47 ldr r3, [pc, #284] @ (800466c ) 8004550: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004554: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8004558: 617b str r3, [r7, #20] 800455a: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 800455c: 4b43 ldr r3, [pc, #268] @ (800466c ) 800455e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004562: 4a42 ldr r2, [pc, #264] @ (800466c ) 8004564: f043 0310 orr.w r3, r3, #16 8004568: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800456c: 4b3f ldr r3, [pc, #252] @ (800466c ) 800456e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004572: f003 0310 and.w r3, r3, #16 8004576: 613b str r3, [r7, #16] 8004578: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 800457a: 2303 movs r3, #3 800457c: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004580: 2302 movs r3, #2 8004582: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8004586: 2300 movs r3, #0 8004588: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800458c: 2300 movs r3, #0 800458e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 8004592: 2308 movs r3, #8 8004594: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8004598: f107 03dc add.w r3, r7, #220 @ 0xdc 800459c: 4619 mov r1, r3 800459e: 4834 ldr r0, [pc, #208] @ (8004670 ) 80045a0: f006 fe14 bl 800b1cc /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 80045a4: 2200 movs r2, #0 80045a6: 2105 movs r1, #5 80045a8: 2053 movs r0, #83 @ 0x53 80045aa: f003 fadd bl 8007b68 HAL_NVIC_EnableIRQ(UART8_IRQn); 80045ae: 2053 movs r0, #83 @ 0x53 80045b0: f003 faf4 bl 8007b9c /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 80045b4: e053 b.n 800465e else if(huart->Instance==USART1) 80045b6: 687b ldr r3, [r7, #4] 80045b8: 681b ldr r3, [r3, #0] 80045ba: 4a2e ldr r2, [pc, #184] @ (8004674 ) 80045bc: 4293 cmp r3, r2 80045be: d14e bne.n 800465e PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 80045c0: f04f 0201 mov.w r2, #1 80045c4: f04f 0300 mov.w r3, #0 80045c8: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 80045cc: 2300 movs r3, #0 80045ce: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80045d2: f107 0318 add.w r3, r7, #24 80045d6: 4618 mov r0, r3 80045d8: f008 f9de bl 800c998 80045dc: 4603 mov r3, r0 80045de: 2b00 cmp r3, #0 80045e0: d001 beq.n 80045e6 Error_Handler(); 80045e2: f7fd fc73 bl 8001ecc __HAL_RCC_USART1_CLK_ENABLE(); 80045e6: 4b21 ldr r3, [pc, #132] @ (800466c ) 80045e8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80045ec: 4a1f ldr r2, [pc, #124] @ (800466c ) 80045ee: f043 0310 orr.w r3, r3, #16 80045f2: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80045f6: 4b1d ldr r3, [pc, #116] @ (800466c ) 80045f8: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80045fc: f003 0310 and.w r3, r3, #16 8004600: 60fb str r3, [r7, #12] 8004602: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 8004604: 4b19 ldr r3, [pc, #100] @ (800466c ) 8004606: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800460a: 4a18 ldr r2, [pc, #96] @ (800466c ) 800460c: f043 0302 orr.w r3, r3, #2 8004610: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004614: 4b15 ldr r3, [pc, #84] @ (800466c ) 8004616: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800461a: f003 0302 and.w r3, r3, #2 800461e: 60bb str r3, [r7, #8] 8004620: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 8004622: f44f 4340 mov.w r3, #49152 @ 0xc000 8004626: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800462a: 2302 movs r3, #2 800462c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8004630: 2300 movs r3, #0 8004632: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004636: 2300 movs r3, #0 8004638: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 800463c: 2304 movs r3, #4 800463e: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004642: f107 03dc add.w r3, r7, #220 @ 0xdc 8004646: 4619 mov r1, r3 8004648: 480b ldr r0, [pc, #44] @ (8004678 ) 800464a: f006 fdbf bl 800b1cc HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 800464e: 2200 movs r2, #0 8004650: 2105 movs r1, #5 8004652: 2025 movs r0, #37 @ 0x25 8004654: f003 fa88 bl 8007b68 HAL_NVIC_EnableIRQ(USART1_IRQn); 8004658: 2025 movs r0, #37 @ 0x25 800465a: f003 fa9f bl 8007b9c } 800465e: bf00 nop 8004660: 37f0 adds r7, #240 @ 0xf0 8004662: 46bd mov sp, r7 8004664: bd80 pop {r7, pc} 8004666: bf00 nop 8004668: 40007c00 .word 0x40007c00 800466c: 58024400 .word 0x58024400 8004670: 58021000 .word 0x58021000 8004674: 40011000 .word 0x40011000 8004678: 58020400 .word 0x58020400 0800467c : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 800467c: b580 push {r7, lr} 800467e: b090 sub sp, #64 @ 0x40 8004680: af00 add r7, sp, #0 8004682: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8004684: 687b ldr r3, [r7, #4] 8004686: 2b0f cmp r3, #15 8004688: d827 bhi.n 80046da { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 800468a: 2200 movs r2, #0 800468c: 6879 ldr r1, [r7, #4] 800468e: 2036 movs r0, #54 @ 0x36 8004690: f003 fa6a bl 8007b68 /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8004694: 2036 movs r0, #54 @ 0x36 8004696: f003 fa81 bl 8007b9c uwTickPrio = TickPriority; 800469a: 4a29 ldr r2, [pc, #164] @ (8004740 ) 800469c: 687b ldr r3, [r7, #4] 800469e: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 80046a0: 4b28 ldr r3, [pc, #160] @ (8004744 ) 80046a2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80046a6: 4a27 ldr r2, [pc, #156] @ (8004744 ) 80046a8: f043 0310 orr.w r3, r3, #16 80046ac: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80046b0: 4b24 ldr r3, [pc, #144] @ (8004744 ) 80046b2: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80046b6: f003 0310 and.w r3, r3, #16 80046ba: 60fb str r3, [r7, #12] 80046bc: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 80046be: f107 0210 add.w r2, r7, #16 80046c2: f107 0314 add.w r3, r7, #20 80046c6: 4611 mov r1, r2 80046c8: 4618 mov r0, r3 80046ca: f008 f923 bl 800c914 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 80046ce: 6abb ldr r3, [r7, #40] @ 0x28 80046d0: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 80046d2: 6bbb ldr r3, [r7, #56] @ 0x38 80046d4: 2b00 cmp r3, #0 80046d6: d106 bne.n 80046e6 80046d8: e001 b.n 80046de return HAL_ERROR; 80046da: 2301 movs r3, #1 80046dc: e02b b.n 8004736 { uwTimclock = HAL_RCC_GetPCLK1Freq(); 80046de: f008 f8ed bl 800c8bc 80046e2: 63f8 str r0, [r7, #60] @ 0x3c 80046e4: e004 b.n 80046f0 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 80046e6: f008 f8e9 bl 800c8bc 80046ea: 4603 mov r3, r0 80046ec: 005b lsls r3, r3, #1 80046ee: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 80046f0: 6bfb ldr r3, [r7, #60] @ 0x3c 80046f2: 4a15 ldr r2, [pc, #84] @ (8004748 ) 80046f4: fba2 2303 umull r2, r3, r2, r3 80046f8: 0c9b lsrs r3, r3, #18 80046fa: 3b01 subs r3, #1 80046fc: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 80046fe: 4b13 ldr r3, [pc, #76] @ (800474c ) 8004700: 4a13 ldr r2, [pc, #76] @ (8004750 ) 8004702: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 8004704: 4b11 ldr r3, [pc, #68] @ (800474c ) 8004706: f240 32e7 movw r2, #999 @ 0x3e7 800470a: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 800470c: 4a0f ldr r2, [pc, #60] @ (800474c ) 800470e: 6b7b ldr r3, [r7, #52] @ 0x34 8004710: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 8004712: 4b0e ldr r3, [pc, #56] @ (800474c ) 8004714: 2200 movs r2, #0 8004716: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8004718: 4b0c ldr r3, [pc, #48] @ (800474c ) 800471a: 2200 movs r2, #0 800471c: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 800471e: 480b ldr r0, [pc, #44] @ (800474c ) 8004720: f00a fe7e bl 800f420 8004724: 4603 mov r3, r0 8004726: 2b00 cmp r3, #0 8004728: d104 bne.n 8004734 { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 800472a: 4808 ldr r0, [pc, #32] @ (800474c ) 800472c: f00a ff40 bl 800f5b0 8004730: 4603 mov r3, r0 8004732: e000 b.n 8004736 } /* Return function status */ return HAL_ERROR; 8004734: 2301 movs r3, #1 } 8004736: 4618 mov r0, r3 8004738: 3740 adds r7, #64 @ 0x40 800473a: 46bd mov sp, r7 800473c: bd80 pop {r7, pc} 800473e: bf00 nop 8004740: 2400003c .word 0x2400003c 8004744: 58024400 .word 0x58024400 8004748: 431bde83 .word 0x431bde83 800474c: 24000920 .word 0x24000920 8004750: 40001000 .word 0x40001000 08004754 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8004754: b480 push {r7} 8004756: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8004758: bf00 nop 800475a: e7fd b.n 8004758 0800475c : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 800475c: b480 push {r7} 800475e: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8004760: bf00 nop 8004762: e7fd b.n 8004760 08004764 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8004764: b480 push {r7} 8004766: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8004768: bf00 nop 800476a: e7fd b.n 8004768 0800476c : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 800476c: b480 push {r7} 800476e: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8004770: bf00 nop 8004772: e7fd b.n 8004770 08004774 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8004774: b480 push {r7} 8004776: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8004778: bf00 nop 800477a: e7fd b.n 8004778 0800477c : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 800477c: b480 push {r7} 800477e: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8004780: bf00 nop 8004782: 46bd mov sp, r7 8004784: f85d 7b04 ldr.w r7, [sp], #4 8004788: 4770 bx lr 0800478a : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 800478a: b480 push {r7} 800478c: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 800478e: bf00 nop 8004790: 46bd mov sp, r7 8004792: f85d 7b04 ldr.w r7, [sp], #4 8004796: 4770 bx lr 08004798 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 8004798: b580 push {r7, lr} 800479a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 800479c: 4802 ldr r0, [pc, #8] @ (80047a8 ) 800479e: f005 fa03 bl 8009ba8 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 80047a2: bf00 nop 80047a4: bd80 pop {r7, pc} 80047a6: bf00 nop 80047a8: 2400024c .word 0x2400024c 080047ac : /** * @brief This function handles DMA1 stream1 global interrupt. */ void DMA1_Stream1_IRQHandler(void) { 80047ac: b580 push {r7, lr} 80047ae: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 80047b0: 4802 ldr r0, [pc, #8] @ (80047bc ) 80047b2: f005 f9f9 bl 8009ba8 /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ /* USER CODE END DMA1_Stream1_IRQn 1 */ } 80047b6: bf00 nop 80047b8: bd80 pop {r7, pc} 80047ba: bf00 nop 80047bc: 240002c4 .word 0x240002c4 080047c0 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 80047c0: b580 push {r7, lr} 80047c2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 80047c4: 4802 ldr r0, [pc, #8] @ (80047d0 ) 80047c6: f005 f9ef bl 8009ba8 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 80047ca: bf00 nop 80047cc: bd80 pop {r7, pc} 80047ce: bf00 nop 80047d0: 2400033c .word 0x2400033c 080047d4 : /** * @brief This function handles EXTI line[9:5] interrupts. */ void EXTI9_5_IRQHandler(void) { 80047d4: b580 push {r7, lr} 80047d6: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ /* USER CODE END EXTI9_5_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); 80047d8: f44f 7080 mov.w r0, #256 @ 0x100 80047dc: f006 fef1 bl 800b5c2 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); 80047e0: f44f 7000 mov.w r0, #512 @ 0x200 80047e4: f006 feed bl 800b5c2 /* USER CODE BEGIN EXTI9_5_IRQn 1 */ /* USER CODE END EXTI9_5_IRQn 1 */ } 80047e8: bf00 nop 80047ea: bd80 pop {r7, pc} 080047ec : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 80047ec: b580 push {r7, lr} 80047ee: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 80047f0: 4802 ldr r0, [pc, #8] @ (80047fc ) 80047f2: f00b fb03 bl 800fdfc /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 80047f6: bf00 nop 80047f8: bd80 pop {r7, pc} 80047fa: bf00 nop 80047fc: 24000488 .word 0x24000488 08004800 : /** * @brief This function handles TIM4 global interrupt. */ void TIM4_IRQHandler(void) { 8004800: b580 push {r7, lr} 8004802: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_IRQn 0 */ /* USER CODE END TIM4_IRQn 0 */ HAL_TIM_IRQHandler(&htim4); 8004804: 4802 ldr r0, [pc, #8] @ (8004810 ) 8004806: f00b faf9 bl 800fdfc /* USER CODE BEGIN TIM4_IRQn 1 */ /* USER CODE END TIM4_IRQn 1 */ } 800480a: bf00 nop 800480c: bd80 pop {r7, pc} 800480e: bf00 nop 8004810: 24000520 .word 0x24000520 08004814 : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 8004814: b580 push {r7, lr} 8004816: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8004818: 4802 ldr r0, [pc, #8] @ (8004824 ) 800481a: f00c feb3 bl 8011584 /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 800481e: bf00 nop 8004820: bd80 pop {r7, pc} 8004822: bf00 nop 8004824: 2400064c .word 0x2400064c 08004828 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8004828: b580 push {r7, lr} 800482a: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 800482c: f44f 6080 mov.w r0, #1024 @ 0x400 8004830: f006 fec7 bl 800b5c2 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 8004834: f44f 6000 mov.w r0, #2048 @ 0x800 8004838: f006 fec3 bl 800b5c2 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); 800483c: f44f 5080 mov.w r0, #4096 @ 0x1000 8004840: f006 febf bl 800b5c2 HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); 8004844: f44f 5000 mov.w r0, #8192 @ 0x2000 8004848: f006 febb bl 800b5c2 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 800484c: bf00 nop 800484e: bd80 pop {r7, pc} 08004850 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8004850: b580 push {r7, lr} 8004852: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 8004854: 4b06 ldr r3, [pc, #24] @ (8004870 ) 8004856: 791b ldrb r3, [r3, #4] 8004858: b2db uxtb r3, r3 800485a: 2b00 cmp r3, #0 800485c: d002 beq.n 8004864 HAL_DAC_IRQHandler(&hdac1); 800485e: 4804 ldr r0, [pc, #16] @ (8004870 ) 8004860: f003 fca1 bl 80081a6 } HAL_TIM_IRQHandler(&htim6); 8004864: 4803 ldr r0, [pc, #12] @ (8004874 ) 8004866: f00b fac9 bl 800fdfc /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 800486a: bf00 nop 800486c: bd80 pop {r7, pc} 800486e: bf00 nop 8004870: 24000404 .word 0x24000404 8004874: 24000920 .word 0x24000920 08004878 : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 8004878: b580 push {r7, lr} 800487a: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 800487c: 4802 ldr r0, [pc, #8] @ (8004888 ) 800487e: f00c fe81 bl 8011584 /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 8004882: bf00 nop 8004884: bd80 pop {r7, pc} 8004886: bf00 nop 8004888: 240005b8 .word 0x240005b8 0800488c : * configuration. * @param None * @retval None */ void SystemInit (void) { 800488c: b480 push {r7} 800488e: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8004890: 4b37 ldr r3, [pc, #220] @ (8004970 ) 8004892: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8004896: 4a36 ldr r2, [pc, #216] @ (8004970 ) 8004898: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 800489c: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80048a0: 4b34 ldr r3, [pc, #208] @ (8004974 ) 80048a2: 681b ldr r3, [r3, #0] 80048a4: f003 030f and.w r3, r3, #15 80048a8: 2b06 cmp r3, #6 80048aa: d807 bhi.n 80048bc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80048ac: 4b31 ldr r3, [pc, #196] @ (8004974 ) 80048ae: 681b ldr r3, [r3, #0] 80048b0: f023 030f bic.w r3, r3, #15 80048b4: 4a2f ldr r2, [pc, #188] @ (8004974 ) 80048b6: f043 0307 orr.w r3, r3, #7 80048ba: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 80048bc: 4b2e ldr r3, [pc, #184] @ (8004978 ) 80048be: 681b ldr r3, [r3, #0] 80048c0: 4a2d ldr r2, [pc, #180] @ (8004978 ) 80048c2: f043 0301 orr.w r3, r3, #1 80048c6: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 80048c8: 4b2b ldr r3, [pc, #172] @ (8004978 ) 80048ca: 2200 movs r2, #0 80048cc: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 80048ce: 4b2a ldr r3, [pc, #168] @ (8004978 ) 80048d0: 681a ldr r2, [r3, #0] 80048d2: 4929 ldr r1, [pc, #164] @ (8004978 ) 80048d4: 4b29 ldr r3, [pc, #164] @ (800497c ) 80048d6: 4013 ands r3, r2 80048d8: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80048da: 4b26 ldr r3, [pc, #152] @ (8004974 ) 80048dc: 681b ldr r3, [r3, #0] 80048de: f003 0308 and.w r3, r3, #8 80048e2: 2b00 cmp r3, #0 80048e4: d007 beq.n 80048f6 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80048e6: 4b23 ldr r3, [pc, #140] @ (8004974 ) 80048e8: 681b ldr r3, [r3, #0] 80048ea: f023 030f bic.w r3, r3, #15 80048ee: 4a21 ldr r2, [pc, #132] @ (8004974 ) 80048f0: f043 0307 orr.w r3, r3, #7 80048f4: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 80048f6: 4b20 ldr r3, [pc, #128] @ (8004978 ) 80048f8: 2200 movs r2, #0 80048fa: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 80048fc: 4b1e ldr r3, [pc, #120] @ (8004978 ) 80048fe: 2200 movs r2, #0 8004900: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 8004902: 4b1d ldr r3, [pc, #116] @ (8004978 ) 8004904: 2200 movs r2, #0 8004906: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8004908: 4b1b ldr r3, [pc, #108] @ (8004978 ) 800490a: 4a1d ldr r2, [pc, #116] @ (8004980 ) 800490c: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 800490e: 4b1a ldr r3, [pc, #104] @ (8004978 ) 8004910: 4a1c ldr r2, [pc, #112] @ (8004984 ) 8004912: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 8004914: 4b18 ldr r3, [pc, #96] @ (8004978 ) 8004916: 4a1c ldr r2, [pc, #112] @ (8004988 ) 8004918: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 800491a: 4b17 ldr r3, [pc, #92] @ (8004978 ) 800491c: 2200 movs r2, #0 800491e: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8004920: 4b15 ldr r3, [pc, #84] @ (8004978 ) 8004922: 4a19 ldr r2, [pc, #100] @ (8004988 ) 8004924: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 8004926: 4b14 ldr r3, [pc, #80] @ (8004978 ) 8004928: 2200 movs r2, #0 800492a: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 800492c: 4b12 ldr r3, [pc, #72] @ (8004978 ) 800492e: 4a16 ldr r2, [pc, #88] @ (8004988 ) 8004930: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 8004932: 4b11 ldr r3, [pc, #68] @ (8004978 ) 8004934: 2200 movs r2, #0 8004936: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8004938: 4b0f ldr r3, [pc, #60] @ (8004978 ) 800493a: 681b ldr r3, [r3, #0] 800493c: 4a0e ldr r2, [pc, #56] @ (8004978 ) 800493e: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8004942: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8004944: 4b0c ldr r3, [pc, #48] @ (8004978 ) 8004946: 2200 movs r2, #0 8004948: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 800494a: 4b10 ldr r3, [pc, #64] @ (800498c ) 800494c: 681a ldr r2, [r3, #0] 800494e: 4b10 ldr r3, [pc, #64] @ (8004990 ) 8004950: 4013 ands r3, r2 8004952: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8004956: d202 bcs.n 800495e { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 8004958: 4b0e ldr r3, [pc, #56] @ (8004994 ) 800495a: 2201 movs r2, #1 800495c: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 800495e: 4b0e ldr r3, [pc, #56] @ (8004998 ) 8004960: f243 02d2 movw r2, #12498 @ 0x30d2 8004964: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 8004966: bf00 nop 8004968: 46bd mov sp, r7 800496a: f85d 7b04 ldr.w r7, [sp], #4 800496e: 4770 bx lr 8004970: e000ed00 .word 0xe000ed00 8004974: 52002000 .word 0x52002000 8004978: 58024400 .word 0x58024400 800497c: eaf6ed7f .word 0xeaf6ed7f 8004980: 02020200 .word 0x02020200 8004984: 01ff0000 .word 0x01ff0000 8004988: 01010280 .word 0x01010280 800498c: 5c001000 .word 0x5c001000 8004990: ffff0000 .word 0xffff0000 8004994: 51008108 .word 0x51008108 8004998: 52004000 .word 0x52004000 0800499c <__NVIC_SystemReset>: { 800499c: b480 push {r7} 800499e: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 80049a0: f3bf 8f4f dsb sy } 80049a4: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 80049a6: 4b06 ldr r3, [pc, #24] @ (80049c0 <__NVIC_SystemReset+0x24>) 80049a8: 68db ldr r3, [r3, #12] 80049aa: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80049ae: 4904 ldr r1, [pc, #16] @ (80049c0 <__NVIC_SystemReset+0x24>) 80049b0: 4b04 ldr r3, [pc, #16] @ (80049c4 <__NVIC_SystemReset+0x28>) 80049b2: 4313 orrs r3, r2 80049b4: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 80049b6: f3bf 8f4f dsb sy } 80049ba: bf00 nop __NOP(); 80049bc: bf00 nop 80049be: e7fd b.n 80049bc <__NVIC_SystemReset+0x20> 80049c0: e000ed00 .word 0xe000ed00 80049c4: 05fa0004 .word 0x05fa0004 080049c8 : uint8_t outputDataBuffer[OUTPUT_DATA_BUFF_SIZE]; uint16_t outputDataBufferPos = 0; extern RNG_HandleTypeDef hrng; void UartTasksInit (void) { 80049c8: b580 push {r7, lr} 80049ca: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 80049cc: 4b24 ldr r3, [pc, #144] @ (8004a60 ) 80049ce: 4a25 ldr r2, [pc, #148] @ (8004a64 ) 80049d0: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 80049d2: 4b23 ldr r3, [pc, #140] @ (8004a60 ) 80049d4: f44f 7280 mov.w r2, #256 @ 0x100 80049d8: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 80049da: 4b21 ldr r3, [pc, #132] @ (8004a60 ) 80049dc: 4a22 ldr r2, [pc, #136] @ (8004a68 ) 80049de: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 80049e0: 4b1f ldr r3, [pc, #124] @ (8004a60 ) 80049e2: f44f 7280 mov.w r2, #256 @ 0x100 80049e6: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 80049e8: 4b1d ldr r3, [pc, #116] @ (8004a60 ) 80049ea: 4a20 ldr r2, [pc, #128] @ (8004a6c ) 80049ec: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 80049ee: 4b1c ldr r3, [pc, #112] @ (8004a60 ) 80049f0: f44f 7280 mov.w r2, #256 @ 0x100 80049f4: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 80049f6: 4b1a ldr r3, [pc, #104] @ (8004a60 ) 80049f8: 4a1d ldr r2, [pc, #116] @ (8004a70 ) 80049fa: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 80049fc: 4b18 ldr r3, [pc, #96] @ (8004a60 ) 80049fe: 2201 movs r2, #1 8004a00: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 8004a04: 4b16 ldr r3, [pc, #88] @ (8004a60 ) 8004a06: 4a1b ldr r2, [pc, #108] @ (8004a74 ) 8004a08: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 8004a0a: 4b15 ldr r3, [pc, #84] @ (8004a60 ) 8004a0c: 2200 movs r2, #0 8004a0e: 625a str r2, [r3, #36] @ 0x24 uart8TaskData.uartRxBuffer = uart8RxBuffer; 8004a10: 4b19 ldr r3, [pc, #100] @ (8004a78 ) 8004a12: 4a1a ldr r2, [pc, #104] @ (8004a7c ) 8004a14: 601a str r2, [r3, #0] uart8TaskData.uartRxBufferLen = UART8_RX_BUFF_SIZE; 8004a16: 4b18 ldr r3, [pc, #96] @ (8004a78 ) 8004a18: f44f 7280 mov.w r2, #256 @ 0x100 8004a1c: 809a strh r2, [r3, #4] uart8TaskData.uartTxBuffer = uart8TxBuffer; 8004a1e: 4b16 ldr r3, [pc, #88] @ (8004a78 ) 8004a20: 4a17 ldr r2, [pc, #92] @ (8004a80 ) 8004a22: 609a str r2, [r3, #8] uart8TaskData.uartRxBufferLen = UART8_TX_BUFF_SIZE; 8004a24: 4b14 ldr r3, [pc, #80] @ (8004a78 ) 8004a26: f44f 7280 mov.w r2, #256 @ 0x100 8004a2a: 809a strh r2, [r3, #4] uart8TaskData.frameData = uart8TaskFrameData; 8004a2c: 4b12 ldr r3, [pc, #72] @ (8004a78 ) 8004a2e: 4a15 ldr r2, [pc, #84] @ (8004a84 ) 8004a30: 611a str r2, [r3, #16] uart8TaskData.frameDataLen = UART8_RX_BUFF_SIZE; 8004a32: 4b11 ldr r3, [pc, #68] @ (8004a78 ) 8004a34: f44f 7280 mov.w r2, #256 @ 0x100 8004a38: 829a strh r2, [r3, #20] uart8TaskData.huart = &huart8; 8004a3a: 4b0f ldr r3, [pc, #60] @ (8004a78 ) 8004a3c: 4a12 ldr r2, [pc, #72] @ (8004a88 ) 8004a3e: 631a str r2, [r3, #48] @ 0x30 uart8TaskData.uartNumber = 8; 8004a40: 4b0d ldr r3, [pc, #52] @ (8004a78 ) 8004a42: 2208 movs r2, #8 8004a44: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; 8004a48: 4b0b ldr r3, [pc, #44] @ (8004a78 ) 8004a4a: 4a10 ldr r2, [pc, #64] @ (8004a8c ) 8004a4c: 629a str r2, [r3, #40] @ 0x28 uart8TaskData.processRxDataMsgBuffer = NULL; 8004a4e: 4b0a ldr r3, [pc, #40] @ (8004a78 ) 8004a50: 2200 movs r2, #0 8004a52: 625a str r2, [r3, #36] @ 0x24 #ifdef USE_UART8_INSTEAD_UART1 UartTaskCreate (&uart8TaskData); #else UartTaskCreate (&uart1TaskData); 8004a54: 4802 ldr r0, [pc, #8] @ (8004a60 ) 8004a56: f000 f81b bl 8004a90 #endif } 8004a5a: bf00 nop 8004a5c: bd80 pop {r7, pc} 8004a5e: bf00 nop 8004a60: 24000f6c .word 0x24000f6c 8004a64: 2400096c .word 0x2400096c 8004a68: 24000a6c .word 0x24000a6c 8004a6c: 24000b6c .word 0x24000b6c 8004a70: 2400064c .word 0x2400064c 8004a74: 08005139 .word 0x08005139 8004a78: 24000fa4 .word 0x24000fa4 8004a7c: 24000c6c .word 0x24000c6c 8004a80: 24000d6c .word 0x24000d6c 8004a84: 24000e6c .word 0x24000e6c 8004a88: 240005b8 .word 0x240005b8 8004a8c: 0800511d .word 0x0800511d 08004a90 : void UartTaskCreate (UartTaskData* uartTaskData) { 8004a90: b580 push {r7, lr} 8004a92: b08c sub sp, #48 @ 0x30 8004a94: af00 add r7, sp, #0 8004a96: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8004a98: f107 030c add.w r3, r7, #12 8004a9c: 2224 movs r2, #36 @ 0x24 8004a9e: 2100 movs r1, #0 8004aa0: 4618 mov r0, r3 8004aa2: f013 fc31 bl 8018308 osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8004aa6: f44f 6380 mov.w r3, #1024 @ 0x400 8004aaa: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 8004aac: 2328 movs r3, #40 @ 0x28 8004aae: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8004ab0: f107 030c add.w r3, r7, #12 8004ab4: 461a mov r2, r3 8004ab6: 6879 ldr r1, [r7, #4] 8004ab8: 4804 ldr r0, [pc, #16] @ (8004acc ) 8004aba: f00f fad1 bl 8014060 8004abe: 4602 mov r2, r0 8004ac0: 687b ldr r3, [r7, #4] 8004ac2: 619a str r2, [r3, #24] } 8004ac4: bf00 nop 8004ac6: 3730 adds r7, #48 @ 0x30 8004ac8: 46bd mov sp, r7 8004aca: bd80 pop {r7, pc} 8004acc: 08004be5 .word 0x08004be5 08004ad0 : void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 8004ad0: b480 push {r7} 8004ad2: b083 sub sp, #12 8004ad4: af00 add r7, sp, #0 8004ad6: 6078 str r0, [r7, #4] } 8004ad8: bf00 nop 8004ada: 370c adds r7, #12 8004adc: 46bd mov sp, r7 8004ade: f85d 7b04 ldr.w r7, [sp], #4 8004ae2: 4770 bx lr 08004ae4 : void HAL_UARTEx_RxEventCallback (UART_HandleTypeDef* huart, uint16_t Size) { 8004ae4: b580 push {r7, lr} 8004ae6: b082 sub sp, #8 8004ae8: af00 add r7, sp, #0 8004aea: 6078 str r0, [r7, #4] 8004aec: 460b mov r3, r1 8004aee: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 8004af0: 687b ldr r3, [r7, #4] 8004af2: 681b ldr r3, [r3, #0] 8004af4: 4a0c ldr r2, [pc, #48] @ (8004b28 ) 8004af6: 4293 cmp r3, r2 8004af8: d106 bne.n 8004b08 HandleUartRxCallback (&uart1TaskData, huart, Size); 8004afa: 887b ldrh r3, [r7, #2] 8004afc: 461a mov r2, r3 8004afe: 6879 ldr r1, [r7, #4] 8004b00: 480a ldr r0, [pc, #40] @ (8004b2c ) 8004b02: f000 f823 bl 8004b4c } else if (huart->Instance == UART8) { HandleUartRxCallback (&uart8TaskData, huart, Size); } } 8004b06: e00a b.n 8004b1e } else if (huart->Instance == UART8) { 8004b08: 687b ldr r3, [r7, #4] 8004b0a: 681b ldr r3, [r3, #0] 8004b0c: 4a08 ldr r2, [pc, #32] @ (8004b30 ) 8004b0e: 4293 cmp r3, r2 8004b10: d105 bne.n 8004b1e HandleUartRxCallback (&uart8TaskData, huart, Size); 8004b12: 887b ldrh r3, [r7, #2] 8004b14: 461a mov r2, r3 8004b16: 6879 ldr r1, [r7, #4] 8004b18: 4806 ldr r0, [pc, #24] @ (8004b34 ) 8004b1a: f000 f817 bl 8004b4c } 8004b1e: bf00 nop 8004b20: 3708 adds r7, #8 8004b22: 46bd mov sp, r7 8004b24: bd80 pop {r7, pc} 8004b26: bf00 nop 8004b28: 40011000 .word 0x40011000 8004b2c: 24000f6c .word 0x24000f6c 8004b30: 40007c00 .word 0x40007c00 8004b34: 24000fa4 .word 0x24000fa4 08004b38 : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 8004b38: b480 push {r7} 8004b3a: b083 sub sp, #12 8004b3c: af00 add r7, sp, #0 8004b3e: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 8004b40: bf00 nop 8004b42: 370c adds r7, #12 8004b44: 46bd mov sp, r7 8004b46: f85d 7b04 ldr.w r7, [sp], #4 8004b4a: 4770 bx lr 08004b4c : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8004b4c: b580 push {r7, lr} 8004b4e: b088 sub sp, #32 8004b50: af02 add r7, sp, #8 8004b52: 60f8 str r0, [r7, #12] 8004b54: 60b9 str r1, [r7, #8] 8004b56: 4613 mov r3, r2 8004b58: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8004b5a: 2300 movs r3, #0 8004b5c: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004b5e: 68fb ldr r3, [r7, #12] 8004b60: 6a1b ldr r3, [r3, #32] 8004b62: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004b66: 4618 mov r0, r3 8004b68: f00f fca5 bl 80144b6 memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 8004b6c: 68fb ldr r3, [r7, #12] 8004b6e: 691b ldr r3, [r3, #16] 8004b70: 68fa ldr r2, [r7, #12] 8004b72: 8ad2 ldrh r2, [r2, #22] 8004b74: 1898 adds r0, r3, r2 8004b76: 68fb ldr r3, [r7, #12] 8004b78: 681b ldr r3, [r3, #0] 8004b7a: 88fa ldrh r2, [r7, #6] 8004b7c: 4619 mov r1, r3 8004b7e: f013 fc4d bl 801841c uartTaskData->frameBytesCount += Size; 8004b82: 68fb ldr r3, [r7, #12] 8004b84: 8ada ldrh r2, [r3, #22] 8004b86: 88fb ldrh r3, [r7, #6] 8004b88: 4413 add r3, r2 8004b8a: b29a uxth r2, r3 8004b8c: 68fb ldr r3, [r7, #12] 8004b8e: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004b90: 68fb ldr r3, [r7, #12] 8004b92: 6a1b ldr r3, [r3, #32] 8004b94: 4618 mov r0, r3 8004b96: f00f fcd9 bl 801454c xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 8004b9a: 68fb ldr r3, [r7, #12] 8004b9c: 6998 ldr r0, [r3, #24] 8004b9e: 88f9 ldrh r1, [r7, #6] 8004ba0: f107 0314 add.w r3, r7, #20 8004ba4: 9300 str r3, [sp, #0] 8004ba6: 2300 movs r3, #0 8004ba8: 2203 movs r2, #3 8004baa: f012 f9c9 bl 8016f40 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004bae: 68fb ldr r3, [r7, #12] 8004bb0: 6b18 ldr r0, [r3, #48] @ 0x30 8004bb2: 68fb ldr r3, [r7, #12] 8004bb4: 6819 ldr r1, [r3, #0] 8004bb6: 68fb ldr r3, [r7, #12] 8004bb8: 889b ldrh r3, [r3, #4] 8004bba: 461a mov r2, r3 8004bbc: f00f f923 bl 8013e06 portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8004bc0: 697b ldr r3, [r7, #20] 8004bc2: 2b00 cmp r3, #0 8004bc4: d007 beq.n 8004bd6 8004bc6: 4b06 ldr r3, [pc, #24] @ (8004be0 ) 8004bc8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8004bcc: 601a str r2, [r3, #0] 8004bce: f3bf 8f4f dsb sy 8004bd2: f3bf 8f6f isb sy } 8004bd6: bf00 nop 8004bd8: 3718 adds r7, #24 8004bda: 46bd mov sp, r7 8004bdc: bd80 pop {r7, pc} 8004bde: bf00 nop 8004be0: e000ed04 .word 0xe000ed04 08004be4 : void UartRxTask (void* argument) { 8004be4: b580 push {r7, lr} 8004be6: b0d2 sub sp, #328 @ 0x148 8004be8: af02 add r7, sp, #8 8004bea: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bee: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004bf2: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 8004bf4: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bf8: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004bfc: 681b ldr r3, [r3, #0] 8004bfe: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 8004c02: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c06: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004c0a: 4618 mov r0, r3 8004c0c: f44f 7386 mov.w r3, #268 @ 0x10c 8004c10: 461a mov r2, r3 8004c12: 2100 movs r1, #0 8004c14: f013 fb78 bl 8018308 uint32_t bytesRec = 0; 8004c18: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c1c: f5a3 739a sub.w r3, r3, #308 @ 0x134 8004c20: 2200 movs r2, #0 8004c22: 601a str r2, [r3, #0] uint32_t crc = 0; 8004c24: 2300 movs r3, #0 8004c26: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 8004c2a: 2300 movs r3, #0 8004c2c: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 8004c30: 2300 movs r3, #0 8004c32: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 8004c36: 2300 movs r3, #0 8004c38: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 8004c3c: 2300 movs r3, #0 8004c3e: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 8004c42: 2300 movs r3, #0 8004c44: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 8004c48: 2300 movs r3, #0 8004c4a: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 8004c4e: 2300 movs r3, #0 8004c50: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 8004c54: 2300 movs r3, #0 8004c56: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 8004c5a: 2300 movs r3, #0 8004c5c: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8004c60: 2000 movs r0, #0 8004c62: f00f fba2 bl 80143aa 8004c66: 4602 mov r2, r0 8004c68: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c6c: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004c6e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c72: 6b18 ldr r0, [r3, #48] @ 0x30 8004c74: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c78: 6819 ldr r1, [r3, #0] 8004c7a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c7e: 889b ldrh r3, [r3, #4] 8004c80: 461a mov r2, r3 8004c82: f00f f8c0 bl 8013e06 while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004c86: f107 020c add.w r2, r7, #12 8004c8a: f44f 63fa mov.w r3, #2000 @ 0x7d0 8004c8e: 2100 movs r1, #0 8004c90: 2000 movs r0, #0 8004c92: f012 f833 bl 8016cfc 8004c96: 4603 mov r3, r0 8004c98: 2b00 cmp r3, #0 8004c9a: bf0c ite eq 8004c9c: 2301 moveq r3, #1 8004c9e: 2300 movne r3, #0 8004ca0: b2db uxtb r3, r3 8004ca2: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004ca6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004caa: 6a1b ldr r3, [r3, #32] 8004cac: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004cb0: 4618 mov r0, r3 8004cb2: f00f fc00 bl 80144b6 frameBytesCount = uartTaskData->frameBytesCount; 8004cb6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cba: 8adb ldrh r3, [r3, #22] 8004cbc: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004cc0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cc4: 6a1b ldr r3, [r3, #32] 8004cc6: 4618 mov r0, r3 8004cc8: f00f fc40 bl 801454c if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8004ccc: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004cd0: 2b01 cmp r3, #1 8004cd2: d10a bne.n 8004cea 8004cd4: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004cd8: 2b00 cmp r3, #0 8004cda: d006 beq.n 8004cea receverState = srFail; 8004cdc: 2304 movs r3, #4 8004cde: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 8004ce2: 2301 movs r3, #1 8004ce4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004ce8: e01b b.n 8004d22 } else { if (frameTimeout == pdFALSE) { 8004cea: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004cee: 2b00 cmp r3, #0 8004cf0: d103 bne.n 8004cfa proceed = pdTRUE; 8004cf2: 2301 movs r3, #1 8004cf4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004cf8: e206 b.n 8005108 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); #endif } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 8004cfa: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cfe: 6b1b ldr r3, [r3, #48] @ 0x30 8004d00: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004d04: 2b20 cmp r3, #32 8004d06: f040 81ff bne.w 8005108 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004d0a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d0e: 6b18 ldr r0, [r3, #48] @ 0x30 8004d10: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d14: 6819 ldr r1, [r3, #0] 8004d16: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d1a: 889b ldrh r3, [r3, #4] 8004d1c: 461a mov r2, r3 8004d1e: f00f f872 bl 8013e06 } } } while (proceed) { 8004d22: e1f1 b.n 8005108 switch (receverState) { 8004d24: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 8004d28: 2b04 cmp r3, #4 8004d2a: f200 81c8 bhi.w 80050be 8004d2e: a201 add r2, pc, #4 @ (adr r2, 8004d34 ) 8004d30: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004d34: 08004d49 .word 0x08004d49 8004d38: 08004eab .word 0x08004eab 8004d3c: 08004e8f .word 0x08004e8f 8004d40: 08004f3b .word 0x08004f3b 8004d44: 08004fe7 .word 0x08004fe7 case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004d48: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d4c: 6a1b ldr r3, [r3, #32] 8004d4e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004d52: 4618 mov r0, r3 8004d54: f00f fbaf bl 80144b6 if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 8004d58: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d5c: 691b ldr r3, [r3, #16] 8004d5e: 781b ldrb r3, [r3, #0] 8004d60: 2baa cmp r3, #170 @ 0xaa 8004d62: f040 8082 bne.w 8004e6a if (frameBytesCount > FRAME_ID_LENGTH) { 8004d66: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004d6a: 2b02 cmp r3, #2 8004d6c: d914 bls.n 8004d98 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 8004d6e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d72: 691b ldr r3, [r3, #16] 8004d74: 3302 adds r3, #2 8004d76: 781b ldrb r3, [r3, #0] 8004d78: 021b lsls r3, r3, #8 8004d7a: b21a sxth r2, r3 8004d7c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d80: 691b ldr r3, [r3, #16] 8004d82: 3301 adds r3, #1 8004d84: 781b ldrb r3, [r3, #0] 8004d86: b21b sxth r3, r3 8004d88: 4313 orrs r3, r2 8004d8a: b21b sxth r3, r3 8004d8c: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 8004d8e: f507 73a0 add.w r3, r7, #320 @ 0x140 8004d92: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004d96: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8004d98: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004d9c: 2b04 cmp r3, #4 8004d9e: d923 bls.n 8004de8 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 8004da0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004da4: 691b ldr r3, [r3, #16] 8004da6: 3304 adds r3, #4 8004da8: 781b ldrb r3, [r3, #0] 8004daa: 021b lsls r3, r3, #8 8004dac: b21a sxth r2, r3 8004dae: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004db2: 691b ldr r3, [r3, #16] 8004db4: 3303 adds r3, #3 8004db6: 781b ldrb r3, [r3, #0] 8004db8: b21b sxth r3, r3 8004dba: 4313 orrs r3, r2 8004dbc: b21b sxth r3, r3 8004dbe: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 8004dc2: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 8004dc6: b2da uxtb r2, r3 8004dc8: f507 73a0 add.w r3, r7, #320 @ 0x140 8004dcc: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004dd0: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 8004dd2: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 8004dd6: 13db asrs r3, r3, #15 8004dd8: b21b sxth r3, r3 8004dda: f003 0201 and.w r2, r3, #1 8004dde: f507 73a0 add.w r3, r7, #320 @ 0x140 8004de2: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004de6: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 8004de8: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004dec: 2b05 cmp r3, #5 8004dee: d913 bls.n 8004e18 8004df0: f507 73a0 add.w r3, r7, #320 @ 0x140 8004df4: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004df8: 789b ldrb r3, [r3, #2] 8004dfa: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004dfe: 2b00 cmp r3, #0 8004e00: d00a beq.n 8004e18 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 8004e02: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e06: 691b ldr r3, [r3, #16] 8004e08: 3305 adds r3, #5 8004e0a: 781b ldrb r3, [r3, #0] 8004e0c: b25a sxtb r2, r3 8004e0e: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e12: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e16: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8004e18: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004e1c: 2b07 cmp r3, #7 8004e1e: d920 bls.n 8004e62 spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 8004e20: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e24: 691b ldr r3, [r3, #16] 8004e26: 3306 adds r3, #6 8004e28: 781b ldrb r3, [r3, #0] 8004e2a: 021b lsls r3, r3, #8 8004e2c: b21a sxth r2, r3 8004e2e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e32: 691b ldr r3, [r3, #16] 8004e34: 3305 adds r3, #5 8004e36: 781b ldrb r3, [r3, #0] 8004e38: b21b sxth r3, r3 8004e3a: 4313 orrs r3, r2 8004e3c: b21b sxth r3, r3 8004e3e: b29a uxth r2, r3 8004e40: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e44: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e48: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8004e4a: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e4e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e52: 889b ldrh r3, [r3, #4] 8004e54: 330a adds r3, #10 8004e56: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 8004e5a: 2302 movs r3, #2 8004e5c: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004e60: e00e b.n 8004e80 } else { proceed = pdFALSE; 8004e62: 2300 movs r3, #0 8004e64: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004e68: e00a b.n 8004e80 } } else { if (frameBytesCount > 0) { 8004e6a: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004e6e: 2b00 cmp r3, #0 8004e70: d003 beq.n 8004e7a receverState = srFail; 8004e72: 2304 movs r3, #4 8004e74: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004e78: e002 b.n 8004e80 } else { proceed = pdFALSE; 8004e7a: 2300 movs r3, #0 8004e7c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 8004e80: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e84: 6a1b ldr r3, [r3, #32] 8004e86: 4618 mov r0, r3 8004e88: f00f fb60 bl 801454c break; 8004e8c: e13c b.n 8005108 case srRecieveData: if (frameBytesCount >= frameTotalLength) { 8004e8e: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 8004e92: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004e96: 429a cmp r2, r3 8004e98: d303 bcc.n 8004ea2 receverState = srCheckCrc; 8004e9a: 2301 movs r3, #1 8004e9c: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 8004ea0: e132 b.n 8005108 proceed = pdFALSE; 8004ea2: 2300 movs r3, #0 8004ea4: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004ea8: e12e b.n 8005108 case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004eaa: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004eae: 6a1b ldr r3, [r3, #32] 8004eb0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004eb4: 4618 mov r0, r3 8004eb6: f00f fafe bl 80144b6 frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8004eba: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ebe: 691a ldr r2, [r3, #16] 8004ec0: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004ec4: 3b01 subs r3, #1 8004ec6: 4413 add r3, r2 8004ec8: 781b ldrb r3, [r3, #0] 8004eca: 021b lsls r3, r3, #8 8004ecc: b21a sxth r2, r3 8004ece: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ed2: 6919 ldr r1, [r3, #16] 8004ed4: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004ed8: 3b02 subs r3, #2 8004eda: 440b add r3, r1 8004edc: 781b ldrb r3, [r3, #0] 8004ede: b21b sxth r3, r3 8004ee0: 4313 orrs r3, r2 8004ee2: b21b sxth r3, r3 8004ee4: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8004ee8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004eec: 6919 ldr r1, [r3, #16] 8004eee: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004ef2: 3b02 subs r3, #2 8004ef4: 461a mov r2, r3 8004ef6: 4887 ldr r0, [pc, #540] @ (8005114 ) 8004ef8: f002 ff3a bl 8007d70 8004efc: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004f00: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f04: 6a1b ldr r3, [r3, #32] 8004f06: 4618 mov r0, r3 8004f08: f00f fb20 bl 801454c crcPass = frameCrc == crc; 8004f0c: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 8004f10: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 8004f14: 429a cmp r2, r3 8004f16: bf0c ite eq 8004f18: 2301 moveq r3, #1 8004f1a: 2300 movne r3, #0 8004f1c: b2db uxtb r3, r3 8004f1e: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 8004f22: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004f26: 2b00 cmp r3, #0 8004f28: d003 beq.n 8004f32 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); #endif receverState = srExecuteCmd; 8004f2a: 2303 movs r3, #3 8004f2c: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 8004f30: e0ea b.n 8005108 receverState = srFail; 8004f32: 2304 movs r3, #4 8004f34: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004f38: e0e6 b.n 8005108 case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 8004f3a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f3e: 6a9b ldr r3, [r3, #40] @ 0x28 8004f40: 2b00 cmp r3, #0 8004f42: d104 bne.n 8004f4e 8004f44: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f48: 6a5b ldr r3, [r3, #36] @ 0x24 8004f4a: 2b00 cmp r3, #0 8004f4c: d01e beq.n 8004f8c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004f4e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f52: 6a1b ldr r3, [r3, #32] 8004f54: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004f58: 4618 mov r0, r3 8004f5a: f00f faac bl 80144b6 memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 8004f5e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f62: 691b ldr r3, [r3, #16] 8004f64: f103 0108 add.w r1, r3, #8 8004f68: f507 73a0 add.w r3, r7, #320 @ 0x140 8004f6c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004f70: 889b ldrh r3, [r3, #4] 8004f72: 461a mov r2, r3 8004f74: f107 0310 add.w r3, r7, #16 8004f78: 330c adds r3, #12 8004f7a: 4618 mov r0, r3 8004f7c: f013 fa4e bl 801841c osMutexRelease (uartTaskData->rxDataBufferMutex); 8004f80: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f84: 6a1b ldr r3, [r3, #32] 8004f86: 4618 mov r0, r3 8004f88: f00f fae0 bl 801454c } if (uartTaskData->processRxDataMsgBuffer != NULL) { 8004f8c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f90: 6a5b ldr r3, [r3, #36] @ 0x24 8004f92: 2b00 cmp r3, #0 8004f94: d015 beq.n 8004fc2 if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) { 8004f96: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f9a: 6a58 ldr r0, [r3, #36] @ 0x24 8004f9c: f507 73a0 add.w r3, r7, #320 @ 0x140 8004fa0: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004fa4: 889b ldrh r3, [r3, #4] 8004fa6: f103 020c add.w r2, r3, #12 8004faa: f107 0110 add.w r1, r7, #16 8004fae: 23c8 movs r3, #200 @ 0xc8 8004fb0: f010 fcee bl 8015990 8004fb4: 4603 mov r3, r0 8004fb6: 2b00 cmp r3, #0 8004fb8: d103 bne.n 8004fc2 receverState = srFail; 8004fba: 2304 movs r3, #4 8004fbc: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004fc0: e0a2 b.n 8005108 } } if (uartTaskData->processDataCb != NULL) { 8004fc2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fc6: 6a9b ldr r3, [r3, #40] @ 0x28 8004fc8: 2b00 cmp r3, #0 8004fca: d008 beq.n 8004fde uartTaskData->processDataCb (uartTaskData, &spFrameData); 8004fcc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fd0: 6a9b ldr r3, [r3, #40] @ 0x28 8004fd2: f107 0210 add.w r2, r7, #16 8004fd6: 4611 mov r1, r2 8004fd8: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 8004fdc: 4798 blx r3 } receverState = srFinish; 8004fde: 2305 movs r3, #5 8004fe0: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004fe4: e090 b.n 8005108 case srFail: dataToSend = 0; 8004fe6: 2300 movs r3, #0 8004fe8: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8004fec: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004ff0: 2b01 cmp r3, #1 8004ff2: d11c bne.n 800502e 8004ff4: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004ff8: 2b02 cmp r3, #2 8004ffa: d918 bls.n 800502e dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8004ffc: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005000: 6898 ldr r0, [r3, #8] 8005002: f507 73a0 add.w r3, r7, #320 @ 0x140 8005006: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800500a: 8819 ldrh r1, [r3, #0] 800500c: f507 73a0 add.w r3, r7, #320 @ 0x140 8005010: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005014: 789a ldrb r2, [r3, #2] 8005016: 2300 movs r3, #0 8005018: 9301 str r3, [sp, #4] 800501a: 2300 movs r3, #0 800501c: 9300 str r3, [sp, #0] 800501e: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8005022: f7fe fd57 bl 8003ad4 8005026: 4603 mov r3, r0 8005028: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 800502c: e034 b.n 8005098 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); #endif } else if (!crcPass) { 800502e: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8005032: 2b00 cmp r3, #0 8005034: d118 bne.n 8005068 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 8005036: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800503a: 6898 ldr r0, [r3, #8] 800503c: f507 73a0 add.w r3, r7, #320 @ 0x140 8005040: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005044: 8819 ldrh r1, [r3, #0] 8005046: f507 73a0 add.w r3, r7, #320 @ 0x140 800504a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800504e: 789a ldrb r2, [r3, #2] 8005050: 2300 movs r3, #0 8005052: 9301 str r3, [sp, #4] 8005054: 2300 movs r3, #0 8005056: 9300 str r3, [sp, #0] 8005058: f06f 0301 mvn.w r3, #1 800505c: f7fe fd3a bl 8003ad4 8005060: 4603 mov r3, r0 8005062: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 8005066: e017 b.n 8005098 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 8005068: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 800506c: 6898 ldr r0, [r3, #8] 800506e: f507 73a0 add.w r3, r7, #320 @ 0x140 8005072: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005076: 8819 ldrh r1, [r3, #0] 8005078: f507 73a0 add.w r3, r7, #320 @ 0x140 800507c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005080: 789a ldrb r2, [r3, #2] 8005082: 2300 movs r3, #0 8005084: 9301 str r3, [sp, #4] 8005086: 2300 movs r3, #0 8005088: 9300 str r3, [sp, #0] 800508a: f06f 0303 mvn.w r3, #3 800508e: f7fe fd21 bl 8003ad4 8005092: 4603 mov r3, r0 8005094: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 8005098: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 800509c: 2b00 cmp r3, #0 800509e: d00a beq.n 80050b6 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 80050a0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050a4: 6b18 ldr r0, [r3, #48] @ 0x30 80050a6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050aa: 689b ldr r3, [r3, #8] 80050ac: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 80050b0: 4619 mov r1, r3 80050b2: f00c f9d3 bl 801145c } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); #endif receverState = srFinish; 80050b6: 2305 movs r3, #5 80050b8: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 80050bc: e024 b.n 8005108 case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80050be: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050c2: 6a1b ldr r3, [r3, #32] 80050c4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80050c8: 4618 mov r0, r3 80050ca: f00f f9f4 bl 80144b6 uartTaskData->frameBytesCount = 0; 80050ce: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050d2: 2200 movs r2, #0 80050d4: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 80050d6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050da: 6a1b ldr r3, [r3, #32] 80050dc: 4618 mov r0, r3 80050de: f00f fa35 bl 801454c spFrameData.frameHeader.frameCommand = spUnknown; 80050e2: f507 73a0 add.w r3, r7, #320 @ 0x140 80050e6: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80050ea: 2212 movs r2, #18 80050ec: 709a strb r2, [r3, #2] frameTotalLength = 0; 80050ee: 2300 movs r3, #0 80050f0: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 80050f4: 4b08 ldr r3, [pc, #32] @ (8005118 ) 80050f6: 2200 movs r2, #0 80050f8: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 80050fa: 2300 movs r3, #0 80050fc: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 8005100: 2300 movs r3, #0 8005102: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8005106: bf00 nop while (proceed) { 8005108: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 800510c: 2b00 cmp r3, #0 800510e: f47f ae09 bne.w 8004d24 frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8005112: e5b8 b.n 8004c86 8005114: 240003e0 .word 0x240003e0 8005118: 2400105c .word 0x2400105c 0800511c : } } } } void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 800511c: b580 push {r7, lr} 800511e: b082 sub sp, #8 8005120: af00 add r7, sp, #0 8005122: 6078 str r0, [r7, #4] 8005124: 6039 str r1, [r7, #0] Uart1ReceivedDataProcessCallback (arg, spFrameData); 8005126: 6839 ldr r1, [r7, #0] 8005128: 6878 ldr r0, [r7, #4] 800512a: f000 f805 bl 8005138 } 800512e: bf00 nop 8005130: 3708 adds r7, #8 8005132: 46bd mov sp, r7 8005134: bd80 pop {r7, pc} ... 08005138 : void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8005138: b590 push {r4, r7, lr} 800513a: b0ad sub sp, #180 @ 0xb4 800513c: af06 add r7, sp, #24 800513e: 6078 str r0, [r7, #4] 8005140: 6039 str r1, [r7, #0] UartTaskData* uartTaskData = (UartTaskData*)arg; 8005142: 687b ldr r3, [r7, #4] 8005144: 677b str r3, [r7, #116] @ 0x74 uint16_t dataToSend = 0; 8005146: 2300 movs r3, #0 8005148: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 outputDataBufferPos = 0; 800514c: 4b64 ldr r3, [pc, #400] @ (80052e0 ) 800514e: 2200 movs r2, #0 8005150: 801a strh r2, [r3, #0] uint16_t inputDataBufferPos = 0; 8005152: 2300 movs r3, #0 8005154: f8a7 3044 strh.w r3, [r7, #68] @ 0x44 SerialProtocolRespStatus respStatus = spUnknownCommand; 8005158: 23fd movs r3, #253 @ 0xfd 800515a: f887 3097 strb.w r3, [r7, #151] @ 0x97 switch (spFrameData->frameHeader.frameCommand) { 800515e: 683b ldr r3, [r7, #0] 8005160: 789b ldrb r3, [r3, #2] 8005162: 2b11 cmp r3, #17 8005164: f200 85a2 bhi.w 8005cac 8005168: a201 add r2, pc, #4 @ (adr r2, 8005170 ) 800516a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800516e: bf00 nop 8005170: 080051b9 .word 0x080051b9 8005174: 080052f1 .word 0x080052f1 8005178: 0800546b .word 0x0800546b 800517c: 080055a1 .word 0x080055a1 8005180: 08005643 .word 0x08005643 8005184: 08005761 .word 0x08005761 8005188: 080057b7 .word 0x080057b7 800518c: 080056e5 .word 0x080056e5 8005190: 0800580d .word 0x0800580d 8005194: 080058ad .word 0x080058ad 8005198: 080058f9 .word 0x080058f9 800519c: 08005945 .word 0x08005945 80051a0: 080059a7 .word 0x080059a7 80051a4: 08005a0b .word 0x08005a0b 80051a8: 08005a6d .word 0x08005a6d 80051ac: 08005ad1 .word 0x08005ad1 80051b0: 08005ad9 .word 0x08005ad9 80051b4: 08005bdd .word 0x08005bdd case spGetElectricalMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80051b8: 4b4a ldr r3, [pc, #296] @ (80052e4 ) 80051ba: 681b ldr r3, [r3, #0] 80051bc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80051c0: 4618 mov r0, r3 80051c2: f00f f978 bl 80144b6 80051c6: 4603 mov r3, r0 80051c8: 2b00 cmp r3, #0 80051ca: f040 8083 bne.w 80052d4 for (int i = 0; i < 3; i++) { 80051ce: 2300 movs r3, #0 80051d0: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80051d4: e00e b.n 80051f4 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 80051d6: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80051da: 009b lsls r3, r3, #2 80051dc: 4a42 ldr r2, [pc, #264] @ (80052e8 ) 80051de: 441a add r2, r3 80051e0: 2304 movs r3, #4 80051e2: 493f ldr r1, [pc, #252] @ (80052e0 ) 80051e4: 4841 ldr r0, [pc, #260] @ (80052ec ) 80051e6: f7fe fbdb bl 80039a0 for (int i = 0; i < 3; i++) { 80051ea: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80051ee: 3301 adds r3, #1 80051f0: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80051f4: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80051f8: 2b02 cmp r3, #2 80051fa: ddec ble.n 80051d6 } for (int i = 0; i < 3; i++) { 80051fc: 2300 movs r3, #0 80051fe: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8005202: e010 b.n 8005226 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 8005204: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005208: 3302 adds r3, #2 800520a: 009b lsls r3, r3, #2 800520c: 4a36 ldr r2, [pc, #216] @ (80052e8 ) 800520e: 4413 add r3, r2 8005210: 1d1a adds r2, r3, #4 8005212: 2304 movs r3, #4 8005214: 4932 ldr r1, [pc, #200] @ (80052e0 ) 8005216: 4835 ldr r0, [pc, #212] @ (80052ec ) 8005218: f7fe fbc2 bl 80039a0 for (int i = 0; i < 3; i++) { 800521c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005220: 3301 adds r3, #1 8005222: f8c7 308c str.w r3, [r7, #140] @ 0x8c 8005226: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 800522a: 2b02 cmp r3, #2 800522c: ddea ble.n 8005204 } for (int i = 0; i < 3; i++) { 800522e: 2300 movs r3, #0 8005230: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8005234: e00f b.n 8005256 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 8005236: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800523a: 3306 adds r3, #6 800523c: 009b lsls r3, r3, #2 800523e: 4a2a ldr r2, [pc, #168] @ (80052e8 ) 8005240: 441a add r2, r3 8005242: 2304 movs r3, #4 8005244: 4926 ldr r1, [pc, #152] @ (80052e0 ) 8005246: 4829 ldr r0, [pc, #164] @ (80052ec ) 8005248: f7fe fbaa bl 80039a0 for (int i = 0; i < 3; i++) { 800524c: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005250: 3301 adds r3, #1 8005252: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8005256: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 800525a: 2b02 cmp r3, #2 800525c: ddeb ble.n 8005236 } for (int i = 0; i < 3; i++) { 800525e: 2300 movs r3, #0 8005260: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8005264: e010 b.n 8005288 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 8005266: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800526a: 3308 adds r3, #8 800526c: 009b lsls r3, r3, #2 800526e: 4a1e ldr r2, [pc, #120] @ (80052e8 ) 8005270: 4413 add r3, r2 8005272: 1d1a adds r2, r3, #4 8005274: 2304 movs r3, #4 8005276: 491a ldr r1, [pc, #104] @ (80052e0 ) 8005278: 481c ldr r0, [pc, #112] @ (80052ec ) 800527a: f7fe fb91 bl 80039a0 for (int i = 0; i < 3; i++) { 800527e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005282: 3301 adds r3, #1 8005284: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8005288: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800528c: 2b02 cmp r3, #2 800528e: ddea ble.n 8005266 } for (int i = 0; i < 3; i++) { 8005290: 2300 movs r3, #0 8005292: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8005296: e00f b.n 80052b8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 8005298: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 800529c: 330c adds r3, #12 800529e: 009b lsls r3, r3, #2 80052a0: 4a11 ldr r2, [pc, #68] @ (80052e8 ) 80052a2: 441a add r2, r3 80052a4: 2304 movs r3, #4 80052a6: 490e ldr r1, [pc, #56] @ (80052e0 ) 80052a8: 4810 ldr r0, [pc, #64] @ (80052ec ) 80052aa: f7fe fb79 bl 80039a0 for (int i = 0; i < 3; i++) { 80052ae: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80052b2: 3301 adds r3, #1 80052b4: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80052b8: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80052bc: 2b02 cmp r3, #2 80052be: ddeb ble.n 8005298 } osMutexRelease (resMeasurementsMutex); 80052c0: 4b08 ldr r3, [pc, #32] @ (80052e4 ) 80052c2: 681b ldr r3, [r3, #0] 80052c4: 4618 mov r0, r3 80052c6: f00f f941 bl 801454c respStatus = spOK; 80052ca: 2300 movs r3, #0 80052cc: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80052d0: f000 bcf3 b.w 8005cba respStatus = spInternalError; 80052d4: 23fc movs r3, #252 @ 0xfc 80052d6: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80052da: f000 bcee b.w 8005cba 80052de: bf00 nop 80052e0: 2400105c .word 0x2400105c 80052e4: 24000818 .word 0x24000818 80052e8: 24000824 .word 0x24000824 80052ec: 24000fdc .word 0x24000fdc case spGetSensorMeasurments: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80052f0: 4b8d ldr r3, [pc, #564] @ (8005528 ) 80052f2: 681b ldr r3, [r3, #0] 80052f4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80052f8: 4618 mov r0, r3 80052fa: f00f f8dc bl 80144b6 80052fe: 4603 mov r3, r0 8005300: 2b00 cmp r3, #0 8005302: f040 80ad bne.w 8005460 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 8005306: 2304 movs r3, #4 8005308: 4a88 ldr r2, [pc, #544] @ (800552c ) 800530a: 4989 ldr r1, [pc, #548] @ (8005530 ) 800530c: 4889 ldr r0, [pc, #548] @ (8005534 ) 800530e: f7fe fb47 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 8005312: 2304 movs r3, #4 8005314: 4a88 ldr r2, [pc, #544] @ (8005538 ) 8005316: 4986 ldr r1, [pc, #536] @ (8005530 ) 8005318: 4886 ldr r0, [pc, #536] @ (8005534 ) 800531a: f7fe fb41 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 800531e: 2304 movs r3, #4 8005320: 4a86 ldr r2, [pc, #536] @ (800553c ) 8005322: 4983 ldr r1, [pc, #524] @ (8005530 ) 8005324: 4883 ldr r0, [pc, #524] @ (8005534 ) 8005326: f7fe fb3b bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float)); 800532a: 2304 movs r3, #4 800532c: 4a84 ldr r2, [pc, #528] @ (8005540 ) 800532e: 4980 ldr r1, [pc, #512] @ (8005530 ) 8005330: 4880 ldr r0, [pc, #512] @ (8005534 ) 8005332: f7fe fb35 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float)); 8005336: 2304 movs r3, #4 8005338: 4a82 ldr r2, [pc, #520] @ (8005544 ) 800533a: 497d ldr r1, [pc, #500] @ (8005530 ) 800533c: 487d ldr r0, [pc, #500] @ (8005534 ) 800533e: f7fe fb2f bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 8005342: 2301 movs r3, #1 8005344: 4a80 ldr r2, [pc, #512] @ (8005548 ) 8005346: 497a ldr r1, [pc, #488] @ (8005530 ) 8005348: 487a ldr r0, [pc, #488] @ (8005534 ) 800534a: f7fe fb29 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 800534e: 2301 movs r3, #1 8005350: 4a7e ldr r2, [pc, #504] @ (800554c ) 8005352: 4977 ldr r1, [pc, #476] @ (8005530 ) 8005354: 4877 ldr r0, [pc, #476] @ (8005534 ) 8005356: f7fe fb23 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 800535a: 2304 movs r3, #4 800535c: 4a7c ldr r2, [pc, #496] @ (8005550 ) 800535e: 4974 ldr r1, [pc, #464] @ (8005530 ) 8005360: 4874 ldr r0, [pc, #464] @ (8005534 ) 8005362: f7fe fb1d bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 8005366: 2304 movs r3, #4 8005368: 4a7a ldr r2, [pc, #488] @ (8005554 ) 800536a: 4971 ldr r1, [pc, #452] @ (8005530 ) 800536c: 4871 ldr r0, [pc, #452] @ (8005534 ) 800536e: f7fe fb17 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 8005372: 2304 movs r3, #4 8005374: 4a78 ldr r2, [pc, #480] @ (8005558 ) 8005376: 496e ldr r1, [pc, #440] @ (8005530 ) 8005378: 486e ldr r0, [pc, #440] @ (8005534 ) 800537a: f7fe fb11 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 800537e: 2304 movs r3, #4 8005380: 4a76 ldr r2, [pc, #472] @ (800555c ) 8005382: 496b ldr r1, [pc, #428] @ (8005530 ) 8005384: 486b ldr r0, [pc, #428] @ (8005534 ) 8005386: f7fe fb0b bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 800538a: 2301 movs r3, #1 800538c: 4a74 ldr r2, [pc, #464] @ (8005560 ) 800538e: 4968 ldr r1, [pc, #416] @ (8005530 ) 8005390: 4868 ldr r0, [pc, #416] @ (8005534 ) 8005392: f7fe fb05 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 8005396: 2301 movs r3, #1 8005398: 4a72 ldr r2, [pc, #456] @ (8005564 ) 800539a: 4965 ldr r1, [pc, #404] @ (8005530 ) 800539c: 4865 ldr r0, [pc, #404] @ (8005534 ) 800539e: f7fe faff bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 80053a2: 2301 movs r3, #1 80053a4: 4a70 ldr r2, [pc, #448] @ (8005568 ) 80053a6: 4962 ldr r1, [pc, #392] @ (8005530 ) 80053a8: 4862 ldr r0, [pc, #392] @ (8005534 ) 80053aa: f7fe faf9 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 80053ae: 2301 movs r3, #1 80053b0: 4a6e ldr r2, [pc, #440] @ (800556c ) 80053b2: 495f ldr r1, [pc, #380] @ (8005530 ) 80053b4: 485f ldr r0, [pc, #380] @ (8005534 ) 80053b6: f7fe faf3 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 80053ba: 2301 movs r3, #1 80053bc: 4a6c ldr r2, [pc, #432] @ (8005570 ) 80053be: 495c ldr r1, [pc, #368] @ (8005530 ) 80053c0: 485c ldr r0, [pc, #368] @ (8005534 ) 80053c2: f7fe faed bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 80053c6: 2301 movs r3, #1 80053c8: 4a6a ldr r2, [pc, #424] @ (8005574 ) 80053ca: 4959 ldr r1, [pc, #356] @ (8005530 ) 80053cc: 4859 ldr r0, [pc, #356] @ (8005534 ) 80053ce: f7fe fae7 bl 80039a0 uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 80053d2: 4869 ldr r0, [pc, #420] @ (8005578 ) 80053d4: f002 faf2 bl 80079bc 80053d8: 4603 mov r3, r0 80053da: 2b01 cmp r3, #1 80053dc: bf0c ite eq 80053de: 2301 moveq r3, #1 80053e0: 2300 movne r3, #0 80053e2: b2db uxtb r3, r3 80053e4: f887 3047 strb.w r3, [r7, #71] @ 0x47 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 80053e8: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80053ec: 005c lsls r4, r3, #1 80053ee: 2108 movs r1, #8 80053f0: 4862 ldr r0, [pc, #392] @ (800557c ) 80053f2: f006 f89b bl 800b52c 80053f6: 4603 mov r3, r0 80053f8: 4323 orrs r3, r4 80053fa: f003 0301 and.w r3, r3, #1 80053fe: 2b00 cmp r3, #0 8005400: bf0c ite eq 8005402: 2301 moveq r3, #1 8005404: 2300 movne r3, #0 8005406: b2db uxtb r3, r3 8005408: 461a mov r2, r3 800540a: 4b48 ldr r3, [pc, #288] @ (800552c ) 800540c: f883 202e strb.w r2, [r3, #46] @ 0x2e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 8005410: 2301 movs r3, #1 8005412: 4a5b ldr r2, [pc, #364] @ (8005580 ) 8005414: 4946 ldr r1, [pc, #280] @ (8005530 ) 8005416: 4847 ldr r0, [pc, #284] @ (8005534 ) 8005418: f7fe fac2 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentXPosition, sizeof (float)); 800541c: 2304 movs r3, #4 800541e: 4a59 ldr r2, [pc, #356] @ (8005584 ) 8005420: 4943 ldr r1, [pc, #268] @ (8005530 ) 8005422: 4844 ldr r0, [pc, #272] @ (8005534 ) 8005424: f7fe fabc bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentYPosition, sizeof (float)); 8005428: 2304 movs r3, #4 800542a: 4a57 ldr r2, [pc, #348] @ (8005588 ) 800542c: 4940 ldr r1, [pc, #256] @ (8005530 ) 800542e: 4841 ldr r0, [pc, #260] @ (8005534 ) 8005430: f7fe fab6 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionXWeak, sizeof (uint8_t)); 8005434: 2301 movs r3, #1 8005436: 4a55 ldr r2, [pc, #340] @ (800558c ) 8005438: 493d ldr r1, [pc, #244] @ (8005530 ) 800543a: 483e ldr r0, [pc, #248] @ (8005534 ) 800543c: f7fe fab0 bl 80039a0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionYWeak, sizeof (uint8_t)); 8005440: 2301 movs r3, #1 8005442: 4a53 ldr r2, [pc, #332] @ (8005590 ) 8005444: 493a ldr r1, [pc, #232] @ (8005530 ) 8005446: 483b ldr r0, [pc, #236] @ (8005534 ) 8005448: f7fe faaa bl 80039a0 osMutexRelease (sensorsInfoMutex); 800544c: 4b36 ldr r3, [pc, #216] @ (8005528 ) 800544e: 681b ldr r3, [r3, #0] 8005450: 4618 mov r0, r3 8005452: f00f f87b bl 801454c respStatus = spOK; 8005456: 2300 movs r3, #0 8005458: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 800545c: f000 bc2d b.w 8005cba respStatus = spInternalError; 8005460: 23fc movs r3, #252 @ 0xfc 8005462: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005466: f000 bc28 b.w 8005cba case spSetFanSpeed: osTimerStop (fanTimerHandle); 800546a: 4b4a ldr r3, [pc, #296] @ (8005594 ) 800546c: 681b ldr r3, [r3, #0] 800546e: 4618 mov r0, r3 8005470: f00e ff64 bl 801433c int32_t fanTimerPeriod = 0; 8005474: 2300 movs r3, #0 8005476: 643b str r3, [r7, #64] @ 0x40 uint32_t pulse = 0; 8005478: 2300 movs r3, #0 800547a: 63fb str r3, [r7, #60] @ 0x3c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 800547c: 683b ldr r3, [r7, #0] 800547e: 330c adds r3, #12 8005480: f107 023c add.w r2, r7, #60 @ 0x3c 8005484: f107 0144 add.w r1, r7, #68 @ 0x44 8005488: 4618 mov r0, r3 800548a: f7fe faef bl 8003a6c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 800548e: 683b ldr r3, [r7, #0] 8005490: 330c adds r3, #12 8005492: f107 0240 add.w r2, r7, #64 @ 0x40 8005496: f107 0144 add.w r1, r7, #68 @ 0x44 800549a: 4618 mov r0, r3 800549c: f7fe fae6 bl 8003a6c fanTimerConfigOC.Pulse = pulse * 10; 80054a0: 6bfa ldr r2, [r7, #60] @ 0x3c 80054a2: 4613 mov r3, r2 80054a4: 009b lsls r3, r3, #2 80054a6: 4413 add r3, r2 80054a8: 005b lsls r3, r3, #1 80054aa: 461a mov r2, r3 80054ac: 4b3a ldr r3, [pc, #232] @ (8005598 ) 80054ae: 605a str r2, [r3, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 80054b0: 2204 movs r2, #4 80054b2: 4939 ldr r1, [pc, #228] @ (8005598 ) 80054b4: 4839 ldr r0, [pc, #228] @ (800559c ) 80054b6: f00a fe45 bl 8010144 80054ba: 4603 mov r3, r0 80054bc: 2b00 cmp r3, #0 80054be: d001 beq.n 80054c4 Error_Handler (); 80054c0: f7fc fd04 bl 8001ecc } if (fanTimerPeriod > 0) { 80054c4: 6c3b ldr r3, [r7, #64] @ 0x40 80054c6: 2b00 cmp r3, #0 80054c8: dd0f ble.n 80054ea osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 80054ca: 4b32 ldr r3, [pc, #200] @ (8005594 ) 80054cc: 681a ldr r2, [r3, #0] 80054ce: 6c3b ldr r3, [r7, #64] @ 0x40 80054d0: f44f 717a mov.w r1, #1000 @ 0x3e8 80054d4: fb01 f303 mul.w r3, r1, r3 80054d8: 4619 mov r1, r3 80054da: 4610 mov r0, r2 80054dc: f00e ff00 bl 80142e0 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 80054e0: 2104 movs r1, #4 80054e2: 482e ldr r0, [pc, #184] @ (800559c ) 80054e4: f00a f934 bl 800f750 80054e8: e019 b.n 800551e } else if (fanTimerPeriod == 0) { 80054ea: 6c3b ldr r3, [r7, #64] @ 0x40 80054ec: 2b00 cmp r3, #0 80054ee: d109 bne.n 8005504 osTimerStop (fanTimerHandle); 80054f0: 4b28 ldr r3, [pc, #160] @ (8005594 ) 80054f2: 681b ldr r3, [r3, #0] 80054f4: 4618 mov r0, r3 80054f6: f00e ff21 bl 801433c HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 80054fa: 2104 movs r1, #4 80054fc: 4827 ldr r0, [pc, #156] @ (800559c ) 80054fe: f00a fa35 bl 800f96c 8005502: e00c b.n 800551e } else if (fanTimerPeriod == -1) { 8005504: 6c3b ldr r3, [r7, #64] @ 0x40 8005506: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800550a: d108 bne.n 800551e osTimerStop (fanTimerHandle); 800550c: 4b21 ldr r3, [pc, #132] @ (8005594 ) 800550e: 681b ldr r3, [r3, #0] 8005510: 4618 mov r0, r3 8005512: f00e ff13 bl 801433c HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 8005516: 2104 movs r1, #4 8005518: 4820 ldr r0, [pc, #128] @ (800559c ) 800551a: f00a f919 bl 800f750 } respStatus = spOK; 800551e: 2300 movs r3, #0 8005520: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005524: e3c9 b.n 8005cba 8005526: bf00 nop 8005528: 2400081c .word 0x2400081c 800552c: 24000860 .word 0x24000860 8005530: 2400105c .word 0x2400105c 8005534: 24000fdc .word 0x24000fdc 8005538: 24000864 .word 0x24000864 800553c: 24000868 .word 0x24000868 8005540: 2400086c .word 0x2400086c 8005544: 24000870 .word 0x24000870 8005548: 24000874 .word 0x24000874 800554c: 24000875 .word 0x24000875 8005550: 24000878 .word 0x24000878 8005554: 2400087c .word 0x2400087c 8005558: 24000880 .word 0x24000880 800555c: 24000884 .word 0x24000884 8005560: 24000888 .word 0x24000888 8005564: 24000889 .word 0x24000889 8005568: 2400088a .word 0x2400088a 800556c: 2400088b .word 0x2400088b 8005570: 2400088c .word 0x2400088c 8005574: 2400088d .word 0x2400088d 8005578: 240003b4 .word 0x240003b4 800557c: 58020c00 .word 0x58020c00 8005580: 2400088e .word 0x2400088e 8005584: 24000890 .word 0x24000890 8005588: 24000894 .word 0x24000894 800558c: 24000898 .word 0x24000898 8005590: 24000899 .word 0x24000899 8005594: 24000714 .word 0x24000714 8005598: 240007a4 .word 0x240007a4 800559c: 2400043c .word 0x2400043c case spSetMotorXOn: int32_t motorXPWMPulse = 0; 80055a0: 2300 movs r3, #0 80055a2: 63bb str r3, [r7, #56] @ 0x38 int32_t motorXTimerPeriod = 0; 80055a4: 2300 movs r3, #0 80055a6: 637b str r3, [r7, #52] @ 0x34 uint32_t motorXStatus = 0; 80055a8: 2300 movs r3, #0 80055aa: 64bb str r3, [r7, #72] @ 0x48 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 80055ac: 683b ldr r3, [r7, #0] 80055ae: 330c adds r3, #12 80055b0: f107 0238 add.w r2, r7, #56 @ 0x38 80055b4: f107 0144 add.w r1, r7, #68 @ 0x44 80055b8: 4618 mov r0, r3 80055ba: f7fe fa57 bl 8003a6c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 80055be: 683b ldr r3, [r7, #0] 80055c0: 330c adds r3, #12 80055c2: f107 0234 add.w r2, r7, #52 @ 0x34 80055c6: f107 0144 add.w r1, r7, #68 @ 0x44 80055ca: 4618 mov r0, r3 80055cc: f7fe fa4e bl 8003a6c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80055d0: 4bab ldr r3, [pc, #684] @ (8005880 ) 80055d2: 681b ldr r3, [r3, #0] 80055d4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80055d8: 4618 mov r0, r3 80055da: f00e ff6c bl 80144b6 80055de: 4603 mov r3, r0 80055e0: 2b00 cmp r3, #0 80055e2: d12a bne.n 800563a motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 80055e4: 4ba7 ldr r3, [pc, #668] @ (8005884 ) 80055e6: 681b ldr r3, [r3, #0] 80055e8: 6bba ldr r2, [r7, #56] @ 0x38 80055ea: 6b79 ldr r1, [r7, #52] @ 0x34 80055ec: 48a6 ldr r0, [pc, #664] @ (8005888 ) 80055ee: f890 0028 ldrb.w r0, [r0, #40] @ 0x28 80055f2: 4ca5 ldr r4, [pc, #660] @ (8005888 ) 80055f4: f894 4029 ldrb.w r4, [r4, #41] @ 0x29 80055f8: 9404 str r4, [sp, #16] 80055fa: 9003 str r0, [sp, #12] 80055fc: 9102 str r1, [sp, #8] 80055fe: 9201 str r2, [sp, #4] 8005600: 9300 str r3, [sp, #0] 8005602: 2304 movs r3, #4 8005604: 2200 movs r2, #0 8005606: 49a1 ldr r1, [pc, #644] @ (800588c ) 8005608: 48a1 ldr r0, [pc, #644] @ (8005890 ) 800560a: f7fd fcf9 bl 8003000 800560e: 4603 mov r3, r0 motorXStatus = 8005610: 64bb str r3, [r7, #72] @ 0x48 sensorsInfo.motorXStatus = motorXStatus; 8005612: 6cbb ldr r3, [r7, #72] @ 0x48 8005614: b2da uxtb r2, r3 8005616: 4b9c ldr r3, [pc, #624] @ (8005888 ) 8005618: 751a strb r2, [r3, #20] if (motorXStatus == 1) { 800561a: 6cbb ldr r3, [r7, #72] @ 0x48 800561c: 2b01 cmp r3, #1 800561e: d103 bne.n 8005628 sensorsInfo.motorXPeakCurrent = 0.0; 8005620: 4b99 ldr r3, [pc, #612] @ (8005888 ) 8005622: f04f 0200 mov.w r2, #0 8005626: 621a str r2, [r3, #32] } osMutexRelease (sensorsInfoMutex); 8005628: 4b95 ldr r3, [pc, #596] @ (8005880 ) 800562a: 681b ldr r3, [r3, #0] 800562c: 4618 mov r0, r3 800562e: f00e ff8d bl 801454c respStatus = spOK; 8005632: 2300 movs r3, #0 8005634: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005638: e33f b.n 8005cba respStatus = spInternalError; 800563a: 23fc movs r3, #252 @ 0xfc 800563c: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005640: e33b b.n 8005cba case spSetMotorYOn: int32_t motorYPWMPulse = 0; 8005642: 2300 movs r3, #0 8005644: 633b str r3, [r7, #48] @ 0x30 int32_t motorYTimerPeriod = 0; 8005646: 2300 movs r3, #0 8005648: 62fb str r3, [r7, #44] @ 0x2c uint32_t motorYStatus = 0; 800564a: 2300 movs r3, #0 800564c: 64fb str r3, [r7, #76] @ 0x4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 800564e: 683b ldr r3, [r7, #0] 8005650: 330c adds r3, #12 8005652: f107 0230 add.w r2, r7, #48 @ 0x30 8005656: f107 0144 add.w r1, r7, #68 @ 0x44 800565a: 4618 mov r0, r3 800565c: f7fe fa06 bl 8003a6c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 8005660: 683b ldr r3, [r7, #0] 8005662: 330c adds r3, #12 8005664: f107 022c add.w r2, r7, #44 @ 0x2c 8005668: f107 0144 add.w r1, r7, #68 @ 0x44 800566c: 4618 mov r0, r3 800566e: f7fe f9fd bl 8003a6c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005672: 4b83 ldr r3, [pc, #524] @ (8005880 ) 8005674: 681b ldr r3, [r3, #0] 8005676: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800567a: 4618 mov r0, r3 800567c: f00e ff1b bl 80144b6 8005680: 4603 mov r3, r0 8005682: 2b00 cmp r3, #0 8005684: d12a bne.n 80056dc motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8005686: 4b83 ldr r3, [pc, #524] @ (8005894 ) 8005688: 681b ldr r3, [r3, #0] 800568a: 6b3a ldr r2, [r7, #48] @ 0x30 800568c: 6af9 ldr r1, [r7, #44] @ 0x2c 800568e: 487e ldr r0, [pc, #504] @ (8005888 ) 8005690: f890 002b ldrb.w r0, [r0, #43] @ 0x2b 8005694: 4c7c ldr r4, [pc, #496] @ (8005888 ) 8005696: f894 402c ldrb.w r4, [r4, #44] @ 0x2c 800569a: 9404 str r4, [sp, #16] 800569c: 9003 str r0, [sp, #12] 800569e: 9102 str r1, [sp, #8] 80056a0: 9201 str r2, [sp, #4] 80056a2: 9300 str r3, [sp, #0] 80056a4: 230c movs r3, #12 80056a6: 2208 movs r2, #8 80056a8: 4978 ldr r1, [pc, #480] @ (800588c ) 80056aa: 4879 ldr r0, [pc, #484] @ (8005890 ) 80056ac: f7fd fca8 bl 8003000 80056b0: 4603 mov r3, r0 motorYStatus = 80056b2: 64fb str r3, [r7, #76] @ 0x4c sensorsInfo.motorYStatus = motorYStatus; 80056b4: 6cfb ldr r3, [r7, #76] @ 0x4c 80056b6: b2da uxtb r2, r3 80056b8: 4b73 ldr r3, [pc, #460] @ (8005888 ) 80056ba: 755a strb r2, [r3, #21] if (motorYStatus == 1) { 80056bc: 6cfb ldr r3, [r7, #76] @ 0x4c 80056be: 2b01 cmp r3, #1 80056c0: d103 bne.n 80056ca sensorsInfo.motorYPeakCurrent = 0.0; 80056c2: 4b71 ldr r3, [pc, #452] @ (8005888 ) 80056c4: f04f 0200 mov.w r2, #0 80056c8: 625a str r2, [r3, #36] @ 0x24 } osMutexRelease (sensorsInfoMutex); 80056ca: 4b6d ldr r3, [pc, #436] @ (8005880 ) 80056cc: 681b ldr r3, [r3, #0] 80056ce: 4618 mov r0, r3 80056d0: f00e ff3c bl 801454c respStatus = spOK; 80056d4: 2300 movs r3, #0 80056d6: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80056da: e2ee b.n 8005cba respStatus = spInternalError; 80056dc: 23fc movs r3, #252 @ 0xfc 80056de: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80056e2: e2ea b.n 8005cba case spSetDiodeOn: osTimerStop (debugLedTimerHandle); 80056e4: 4b6c ldr r3, [pc, #432] @ (8005898 ) 80056e6: 681b ldr r3, [r3, #0] 80056e8: 4618 mov r0, r3 80056ea: f00e fe27 bl 801433c int32_t dbgLedTimerPeriod = 0; 80056ee: 2300 movs r3, #0 80056f0: 62bb str r3, [r7, #40] @ 0x28 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 80056f2: 683b ldr r3, [r7, #0] 80056f4: 330c adds r3, #12 80056f6: f107 0228 add.w r2, r7, #40 @ 0x28 80056fa: f107 0144 add.w r1, r7, #68 @ 0x44 80056fe: 4618 mov r0, r3 8005700: f7fe f9b4 bl 8003a6c if (dbgLedTimerPeriod > 0) { 8005704: 6abb ldr r3, [r7, #40] @ 0x28 8005706: 2b00 cmp r3, #0 8005708: dd0e ble.n 8005728 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 800570a: 4b63 ldr r3, [pc, #396] @ (8005898 ) 800570c: 681a ldr r2, [r3, #0] 800570e: 6abb ldr r3, [r7, #40] @ 0x28 8005710: f44f 717a mov.w r1, #1000 @ 0x3e8 8005714: fb01 f303 mul.w r3, r1, r3 8005718: 4619 mov r1, r3 800571a: 4610 mov r0, r2 800571c: f00e fde0 bl 80142e0 DbgLEDOn (DBG_LED1); 8005720: 2010 movs r0, #16 8005722: f7fd fbdf bl 8002ee4 8005726: e017 b.n 8005758 } else if (dbgLedTimerPeriod == 0) { 8005728: 6abb ldr r3, [r7, #40] @ 0x28 800572a: 2b00 cmp r3, #0 800572c: d108 bne.n 8005740 osTimerStop (debugLedTimerHandle); 800572e: 4b5a ldr r3, [pc, #360] @ (8005898 ) 8005730: 681b ldr r3, [r3, #0] 8005732: 4618 mov r0, r3 8005734: f00e fe02 bl 801433c DbgLEDOff (DBG_LED1); 8005738: 2010 movs r0, #16 800573a: f7fd fbe5 bl 8002f08 800573e: e00b b.n 8005758 } else if (dbgLedTimerPeriod == -1) { 8005740: 6abb ldr r3, [r7, #40] @ 0x28 8005742: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005746: d107 bne.n 8005758 osTimerStop (debugLedTimerHandle); 8005748: 4b53 ldr r3, [pc, #332] @ (8005898 ) 800574a: 681b ldr r3, [r3, #0] 800574c: 4618 mov r0, r3 800574e: f00e fdf5 bl 801433c DbgLEDOn (DBG_LED1); 8005752: 2010 movs r0, #16 8005754: f7fd fbc6 bl 8002ee4 } respStatus = spOK; 8005758: 2300 movs r3, #0 800575a: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800575e: e2ac b.n 8005cba case spSetmotorXMaxCurrent: float motorXMaxCurrent = 0; 8005760: f04f 0300 mov.w r3, #0 8005764: 627b str r3, [r7, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 8005766: 683b ldr r3, [r7, #0] 8005768: 330c adds r3, #12 800576a: f107 0224 add.w r2, r7, #36 @ 0x24 800576e: f107 0144 add.w r1, r7, #68 @ 0x44 8005772: 4618 mov r0, r3 8005774: f7fe f97a bl 8003a6c uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 8005778: edd7 7a09 vldr s15, [r7, #36] @ 0x24 800577c: ed9f 7a47 vldr s14, [pc, #284] @ 800589c 8005780: ee67 7a87 vmul.f32 s15, s15, s14 8005784: eeb7 6ae7 vcvt.f64.f32 d6, s15 8005788: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 800578c: ee86 7b05 vdiv.f64 d7, d6, d5 8005790: eefc 7bc7 vcvt.u32.f64 s15, d7 8005794: ee17 3a90 vmov r3, s15 8005798: 653b str r3, [r7, #80] @ 0x50 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 800579a: 6d3b ldr r3, [r7, #80] @ 0x50 800579c: 2200 movs r2, #0 800579e: 2100 movs r1, #0 80057a0: 483f ldr r0, [pc, #252] @ (80058a0 ) 80057a2: f002 fd56 bl 8008252 HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 80057a6: 2100 movs r1, #0 80057a8: 483d ldr r0, [pc, #244] @ (80058a0 ) 80057aa: f002 fca5 bl 80080f8 respStatus = spOK; 80057ae: 2300 movs r3, #0 80057b0: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80057b4: e281 b.n 8005cba case spSetmotorYMaxCurrent: float motorYMaxCurrent = 0; 80057b6: f04f 0300 mov.w r3, #0 80057ba: 623b str r3, [r7, #32] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 80057bc: 683b ldr r3, [r7, #0] 80057be: 330c adds r3, #12 80057c0: f107 0220 add.w r2, r7, #32 80057c4: f107 0144 add.w r1, r7, #68 @ 0x44 80057c8: 4618 mov r0, r3 80057ca: f7fe f94f bl 8003a6c uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 80057ce: edd7 7a08 vldr s15, [r7, #32] 80057d2: ed9f 7a32 vldr s14, [pc, #200] @ 800589c 80057d6: ee67 7a87 vmul.f32 s15, s15, s14 80057da: eeb7 6ae7 vcvt.f64.f32 d6, s15 80057de: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 80057e2: ee86 7b05 vdiv.f64 d7, d6, d5 80057e6: eefc 7bc7 vcvt.u32.f64 s15, d7 80057ea: ee17 3a90 vmov r3, s15 80057ee: 657b str r3, [r7, #84] @ 0x54 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 80057f0: 6d7b ldr r3, [r7, #84] @ 0x54 80057f2: 2200 movs r2, #0 80057f4: 2110 movs r1, #16 80057f6: 482a ldr r0, [pc, #168] @ (80058a0 ) 80057f8: f002 fd2b bl 8008252 HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 80057fc: 2110 movs r1, #16 80057fe: 4828 ldr r0, [pc, #160] @ (80058a0 ) 8005800: f002 fc7a bl 80080f8 respStatus = spOK; 8005804: 2300 movs r3, #0 8005806: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800580a: e256 b.n 8005cba case spClearPeakMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800580c: 4b25 ldr r3, [pc, #148] @ (80058a4 ) 800580e: 681b ldr r3, [r3, #0] 8005810: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005814: 4618 mov r0, r3 8005816: f00e fe4e bl 80144b6 800581a: 4603 mov r3, r0 800581c: 2b00 cmp r3, #0 800581e: d12a bne.n 8005876 for (int i = 0; i < 3; i++) { 8005820: 2300 movs r3, #0 8005822: 67fb str r3, [r7, #124] @ 0x7c 8005824: e01b b.n 800585e resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 8005826: 4a20 ldr r2, [pc, #128] @ (80058a8 ) 8005828: 6ffb ldr r3, [r7, #124] @ 0x7c 800582a: 009b lsls r3, r3, #2 800582c: 4413 add r3, r2 800582e: 681a ldr r2, [r3, #0] 8005830: 491d ldr r1, [pc, #116] @ (80058a8 ) 8005832: 6ffb ldr r3, [r7, #124] @ 0x7c 8005834: 3302 adds r3, #2 8005836: 009b lsls r3, r3, #2 8005838: 440b add r3, r1 800583a: 3304 adds r3, #4 800583c: 601a str r2, [r3, #0] resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 800583e: 4a1a ldr r2, [pc, #104] @ (80058a8 ) 8005840: 6ffb ldr r3, [r7, #124] @ 0x7c 8005842: 3306 adds r3, #6 8005844: 009b lsls r3, r3, #2 8005846: 4413 add r3, r2 8005848: 681a ldr r2, [r3, #0] 800584a: 4917 ldr r1, [pc, #92] @ (80058a8 ) 800584c: 6ffb ldr r3, [r7, #124] @ 0x7c 800584e: 3308 adds r3, #8 8005850: 009b lsls r3, r3, #2 8005852: 440b add r3, r1 8005854: 3304 adds r3, #4 8005856: 601a str r2, [r3, #0] for (int i = 0; i < 3; i++) { 8005858: 6ffb ldr r3, [r7, #124] @ 0x7c 800585a: 3301 adds r3, #1 800585c: 67fb str r3, [r7, #124] @ 0x7c 800585e: 6ffb ldr r3, [r7, #124] @ 0x7c 8005860: 2b02 cmp r3, #2 8005862: dde0 ble.n 8005826 } osMutexRelease (resMeasurementsMutex); 8005864: 4b0f ldr r3, [pc, #60] @ (80058a4 ) 8005866: 681b ldr r3, [r3, #0] 8005868: 4618 mov r0, r3 800586a: f00e fe6f bl 801454c respStatus = spOK; 800586e: 2300 movs r3, #0 8005870: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005874: e221 b.n 8005cba respStatus = spInternalError; 8005876: 23fc movs r3, #252 @ 0xfc 8005878: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800587c: e21d b.n 8005cba 800587e: bf00 nop 8005880: 2400081c .word 0x2400081c 8005884: 24000744 .word 0x24000744 8005888: 24000860 .word 0x24000860 800588c: 240007c0 .word 0x240007c0 8005890: 240004d4 .word 0x240004d4 8005894: 24000774 .word 0x24000774 8005898: 240006e4 .word 0x240006e4 800589c: 457ff000 .word 0x457ff000 80058a0: 24000404 .word 0x24000404 80058a4: 24000818 .word 0x24000818 80058a8: 24000824 .word 0x24000824 case spSetEncoderXValue: float enocoderXValue = 0; 80058ac: f04f 0300 mov.w r3, #0 80058b0: 61fb str r3, [r7, #28] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 80058b2: 683b ldr r3, [r7, #0] 80058b4: 330c adds r3, #12 80058b6: f107 021c add.w r2, r7, #28 80058ba: f107 0144 add.w r1, r7, #68 @ 0x44 80058be: 4618 mov r0, r3 80058c0: f7fe f8d4 bl 8003a6c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80058c4: 4bbc ldr r3, [pc, #752] @ (8005bb8 ) 80058c6: 681b ldr r3, [r3, #0] 80058c8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80058cc: 4618 mov r0, r3 80058ce: f00e fdf2 bl 80144b6 80058d2: 4603 mov r3, r0 80058d4: 2b00 cmp r3, #0 80058d6: d10b bne.n 80058f0 sensorsInfo.pvEncoderX = enocoderXValue; 80058d8: 69fb ldr r3, [r7, #28] 80058da: 4ab8 ldr r2, [pc, #736] @ (8005bbc ) 80058dc: 60d3 str r3, [r2, #12] osMutexRelease (sensorsInfoMutex); 80058de: 4bb6 ldr r3, [pc, #728] @ (8005bb8 ) 80058e0: 681b ldr r3, [r3, #0] 80058e2: 4618 mov r0, r3 80058e4: f00e fe32 bl 801454c respStatus = spOK; 80058e8: 2300 movs r3, #0 80058ea: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80058ee: e1e4 b.n 8005cba respStatus = spInternalError; 80058f0: 23fc movs r3, #252 @ 0xfc 80058f2: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80058f6: e1e0 b.n 8005cba case spSetEncoderYValue: float enocoderYValue = 0; 80058f8: f04f 0300 mov.w r3, #0 80058fc: 61bb str r3, [r7, #24] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 80058fe: 683b ldr r3, [r7, #0] 8005900: 330c adds r3, #12 8005902: f107 0218 add.w r2, r7, #24 8005906: f107 0144 add.w r1, r7, #68 @ 0x44 800590a: 4618 mov r0, r3 800590c: f7fe f8ae bl 8003a6c if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005910: 4ba9 ldr r3, [pc, #676] @ (8005bb8 ) 8005912: 681b ldr r3, [r3, #0] 8005914: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005918: 4618 mov r0, r3 800591a: f00e fdcc bl 80144b6 800591e: 4603 mov r3, r0 8005920: 2b00 cmp r3, #0 8005922: d10b bne.n 800593c sensorsInfo.pvEncoderY = enocoderYValue; 8005924: 69bb ldr r3, [r7, #24] 8005926: 4aa5 ldr r2, [pc, #660] @ (8005bbc ) 8005928: 6113 str r3, [r2, #16] osMutexRelease (sensorsInfoMutex); 800592a: 4ba3 ldr r3, [pc, #652] @ (8005bb8 ) 800592c: 681b ldr r3, [r3, #0] 800592e: 4618 mov r0, r3 8005930: f00e fe0c bl 801454c respStatus = spOK; 8005934: 2300 movs r3, #0 8005936: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 800593a: e1be b.n 8005cba respStatus = spInternalError; 800593c: 23fc movs r3, #252 @ 0xfc 800593e: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005942: e1ba b.n 8005cba case spSetVoltageMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005944: 4b9e ldr r3, [pc, #632] @ (8005bc0 ) 8005946: 681b ldr r3, [r3, #0] 8005948: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800594c: 4618 mov r0, r3 800594e: f00e fdb2 bl 80144b6 8005952: 4603 mov r3, r0 8005954: 2b00 cmp r3, #0 8005956: d122 bne.n 800599e for (uint8_t i = 0; i < 3; i++) { 8005958: 2300 movs r3, #0 800595a: f887 307b strb.w r3, [r7, #123] @ 0x7b 800595e: e011 b.n 8005984 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain); 8005960: 683b ldr r3, [r7, #0] 8005962: f103 000c add.w r0, r3, #12 8005966: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 800596a: 00db lsls r3, r3, #3 800596c: 4a95 ldr r2, [pc, #596] @ (8005bc4 ) 800596e: 441a add r2, r3 8005970: f107 0344 add.w r3, r7, #68 @ 0x44 8005974: 4619 mov r1, r3 8005976: f7fe f879 bl 8003a6c for (uint8_t i = 0; i < 3; i++) { 800597a: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 800597e: 3301 adds r3, #1 8005980: f887 307b strb.w r3, [r7, #123] @ 0x7b 8005984: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 8005988: 2b02 cmp r3, #2 800598a: d9e9 bls.n 8005960 } osMutexRelease (resMeasurementsMutex); 800598c: 4b8c ldr r3, [pc, #560] @ (8005bc0 ) 800598e: 681b ldr r3, [r3, #0] 8005990: 4618 mov r0, r3 8005992: f00e fddb bl 801454c respStatus = spOK; 8005996: 2300 movs r3, #0 8005998: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 800599c: e18d b.n 8005cba respStatus = spInternalError; 800599e: 23fc movs r3, #252 @ 0xfc 80059a0: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80059a4: e189 b.n 8005cba case spSetVoltageMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80059a6: 4b86 ldr r3, [pc, #536] @ (8005bc0 ) 80059a8: 681b ldr r3, [r3, #0] 80059aa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80059ae: 4618 mov r0, r3 80059b0: f00e fd81 bl 80144b6 80059b4: 4603 mov r3, r0 80059b6: 2b00 cmp r3, #0 80059b8: d123 bne.n 8005a02 for (uint8_t i = 0; i < 3; i++) { 80059ba: 2300 movs r3, #0 80059bc: f887 307a strb.w r3, [r7, #122] @ 0x7a 80059c0: e012 b.n 80059e8 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset); 80059c2: 683b ldr r3, [r7, #0] 80059c4: f103 000c add.w r0, r3, #12 80059c8: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059cc: 00db lsls r3, r3, #3 80059ce: 4a7d ldr r2, [pc, #500] @ (8005bc4 ) 80059d0: 4413 add r3, r2 80059d2: 1d1a adds r2, r3, #4 80059d4: f107 0344 add.w r3, r7, #68 @ 0x44 80059d8: 4619 mov r1, r3 80059da: f7fe f847 bl 8003a6c for (uint8_t i = 0; i < 3; i++) { 80059de: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059e2: 3301 adds r3, #1 80059e4: f887 307a strb.w r3, [r7, #122] @ 0x7a 80059e8: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059ec: 2b02 cmp r3, #2 80059ee: d9e8 bls.n 80059c2 } osMutexRelease (resMeasurementsMutex); 80059f0: 4b73 ldr r3, [pc, #460] @ (8005bc0 ) 80059f2: 681b ldr r3, [r3, #0] 80059f4: 4618 mov r0, r3 80059f6: f00e fda9 bl 801454c respStatus = spOK; 80059fa: 2300 movs r3, #0 80059fc: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005a00: e15b b.n 8005cba respStatus = spInternalError; 8005a02: 23fc movs r3, #252 @ 0xfc 8005a04: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005a08: e157 b.n 8005cba case spSetCurrentMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005a0a: 4b6d ldr r3, [pc, #436] @ (8005bc0 ) 8005a0c: 681b ldr r3, [r3, #0] 8005a0e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005a12: 4618 mov r0, r3 8005a14: f00e fd4f bl 80144b6 8005a18: 4603 mov r3, r0 8005a1a: 2b00 cmp r3, #0 8005a1c: d122 bne.n 8005a64 for (uint8_t i = 0; i < 3; i++) { 8005a1e: 2300 movs r3, #0 8005a20: f887 3079 strb.w r3, [r7, #121] @ 0x79 8005a24: e011 b.n 8005a4a ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain); 8005a26: 683b ldr r3, [r7, #0] 8005a28: f103 000c add.w r0, r3, #12 8005a2c: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a30: 00db lsls r3, r3, #3 8005a32: 4a65 ldr r2, [pc, #404] @ (8005bc8 ) 8005a34: 441a add r2, r3 8005a36: f107 0344 add.w r3, r7, #68 @ 0x44 8005a3a: 4619 mov r1, r3 8005a3c: f7fe f816 bl 8003a6c for (uint8_t i = 0; i < 3; i++) { 8005a40: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a44: 3301 adds r3, #1 8005a46: f887 3079 strb.w r3, [r7, #121] @ 0x79 8005a4a: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a4e: 2b02 cmp r3, #2 8005a50: d9e9 bls.n 8005a26 } osMutexRelease (resMeasurementsMutex); 8005a52: 4b5b ldr r3, [pc, #364] @ (8005bc0 ) 8005a54: 681b ldr r3, [r3, #0] 8005a56: 4618 mov r0, r3 8005a58: f00e fd78 bl 801454c respStatus = spOK; 8005a5c: 2300 movs r3, #0 8005a5e: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005a62: e12a b.n 8005cba respStatus = spInternalError; 8005a64: 23fc movs r3, #252 @ 0xfc 8005a66: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005a6a: e126 b.n 8005cba case spSetCurrentMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005a6c: 4b54 ldr r3, [pc, #336] @ (8005bc0 ) 8005a6e: 681b ldr r3, [r3, #0] 8005a70: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005a74: 4618 mov r0, r3 8005a76: f00e fd1e bl 80144b6 8005a7a: 4603 mov r3, r0 8005a7c: 2b00 cmp r3, #0 8005a7e: d123 bne.n 8005ac8 for (uint8_t i = 0; i < 3; i++) { 8005a80: 2300 movs r3, #0 8005a82: f887 3078 strb.w r3, [r7, #120] @ 0x78 8005a86: e012 b.n 8005aae ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 8005a88: 683b ldr r3, [r7, #0] 8005a8a: f103 000c add.w r0, r3, #12 8005a8e: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005a92: 00db lsls r3, r3, #3 8005a94: 4a4c ldr r2, [pc, #304] @ (8005bc8 ) 8005a96: 4413 add r3, r2 8005a98: 1d1a adds r2, r3, #4 8005a9a: f107 0344 add.w r3, r7, #68 @ 0x44 8005a9e: 4619 mov r1, r3 8005aa0: f7fd ffe4 bl 8003a6c for (uint8_t i = 0; i < 3; i++) { 8005aa4: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005aa8: 3301 adds r3, #1 8005aaa: f887 3078 strb.w r3, [r7, #120] @ 0x78 8005aae: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005ab2: 2b02 cmp r3, #2 8005ab4: d9e8 bls.n 8005a88 } osMutexRelease (resMeasurementsMutex); 8005ab6: 4b42 ldr r3, [pc, #264] @ (8005bc0 ) 8005ab8: 681b ldr r3, [r3, #0] 8005aba: 4618 mov r0, r3 8005abc: f00e fd46 bl 801454c respStatus = spOK; 8005ac0: 2300 movs r3, #0 8005ac2: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005ac6: e0f8 b.n 8005cba respStatus = spInternalError; 8005ac8: 23fc movs r3, #252 @ 0xfc 8005aca: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005ace: e0f4 b.n 8005cba __ASM volatile ("cpsid i" : : : "memory"); 8005ad0: b672 cpsid i } 8005ad2: bf00 nop case spResetSystem: __disable_irq(); NVIC_SystemReset(); 8005ad4: f7fe ff62 bl 800499c <__NVIC_SystemReset> break; case spSetPositonX: PositionControlTaskData posXData = { 0 }; 8005ad8: f04f 0300 mov.w r3, #0 8005adc: 617b str r3, [r7, #20] if (positionXControlTaskInitArg.positionSettingQueue != NULL) 8005ade: 4b3b ldr r3, [pc, #236] @ (8005bcc ) 8005ae0: 691b ldr r3, [r3, #16] 8005ae2: 2b00 cmp r3, #0 8005ae4: f000 80e6 beq.w 8005cb4 { float posXPercent = 0; 8005ae8: f04f 0300 mov.w r3, #0 8005aec: 60fb str r3, [r7, #12] ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posXPercent); 8005aee: 683b ldr r3, [r7, #0] 8005af0: 330c adds r3, #12 8005af2: f107 020c add.w r2, r7, #12 8005af6: f107 0144 add.w r1, r7, #68 @ 0x44 8005afa: 4618 mov r0, r3 8005afc: f7fd ff81 bl 8003a02 float posXDegress = MAX_X_AXE_ANGLE * posXPercent * 0.01; 8005b00: edd7 7a03 vldr s15, [r7, #12] 8005b04: ed9f 7a32 vldr s14, [pc, #200] @ 8005bd0 8005b08: ee67 7a87 vmul.f32 s15, s15, s14 8005b0c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8005b10: ed9f 6b27 vldr d6, [pc, #156] @ 8005bb0 8005b14: ee27 7b06 vmul.f64 d7, d7, d6 8005b18: eef7 7bc7 vcvt.f32.f64 s15, d7 8005b1c: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float angleDelta = 360 / ENCODER_X_IMP_PER_TURN; 8005b20: 4b2c ldr r3, [pc, #176] @ (8005bd4 ) 8005b22: 65fb str r3, [r7, #92] @ 0x5c float rest = fmodf(posXDegress, angleDelta); 8005b24: edd7 0a17 vldr s1, [r7, #92] @ 0x5c 8005b28: ed97 0a18 vldr s0, [r7, #96] @ 0x60 8005b2c: f012 fcda bl 80184e4 8005b30: ed87 0a16 vstr s0, [r7, #88] @ 0x58 if ( rest > (angleDelta/2)) 8005b34: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8005b38: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0 8005b3c: eec7 7a26 vdiv.f32 s15, s14, s13 8005b40: ed97 7a16 vldr s14, [r7, #88] @ 0x58 8005b44: eeb4 7ae7 vcmpe.f32 s14, s15 8005b48: eef1 fa10 vmrs APSR_nzcv, fpscr 8005b4c: dd14 ble.n 8005b78 { posXData.positionSettingValue = 100 * (posXDegress - rest + angleDelta) / MAX_X_AXE_ANGLE; 8005b4e: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005b52: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8005b56: ee37 7a67 vsub.f32 s14, s14, s15 8005b5a: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8005b5e: ee77 7a27 vadd.f32 s15, s14, s15 8005b62: ed9f 7a1d vldr s14, [pc, #116] @ 8005bd8 8005b66: ee27 7a87 vmul.f32 s14, s15, s14 8005b6a: eddf 6a19 vldr s13, [pc, #100] @ 8005bd0 8005b6e: eec7 7a26 vdiv.f32 s15, s14, s13 8005b72: edc7 7a05 vstr s15, [r7, #20] 8005b76: e00f b.n 8005b98 } else { posXData.positionSettingValue = 100 * (posXDegress - rest) / MAX_X_AXE_ANGLE; 8005b78: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005b7c: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8005b80: ee77 7a67 vsub.f32 s15, s14, s15 8005b84: ed9f 7a14 vldr s14, [pc, #80] @ 8005bd8 8005b88: ee27 7a87 vmul.f32 s14, s15, s14 8005b8c: eddf 6a10 vldr s13, [pc, #64] @ 8005bd0 8005b90: eec7 7a26 vdiv.f32 s15, s14, s13 8005b94: edc7 7a05 vstr s15, [r7, #20] } osMessageQueuePut(positionXControlTaskInitArg.positionSettingQueue, &posXData, 0, 0); 8005b98: 4b0c ldr r3, [pc, #48] @ (8005bcc ) 8005b9a: 6918 ldr r0, [r3, #16] 8005b9c: f107 0114 add.w r1, r7, #20 8005ba0: 2300 movs r3, #0 8005ba2: 2200 movs r2, #0 8005ba4: f00e fd82 bl 80146ac } break; 8005ba8: e084 b.n 8005cb4 8005baa: bf00 nop 8005bac: f3af 8000 nop.w 8005bb0: 47ae147b .word 0x47ae147b 8005bb4: 3f847ae1 .word 0x3f847ae1 8005bb8: 2400081c .word 0x2400081c 8005bbc: 24000860 .word 0x24000860 8005bc0: 24000818 .word 0x24000818 8005bc4: 24000000 .word 0x24000000 8005bc8: 24000018 .word 0x24000018 8005bcc: 240008b4 .word 0x240008b4 8005bd0: 43b40000 .word 0x43b40000 8005bd4: 41900000 .word 0x41900000 8005bd8: 42c80000 .word 0x42c80000 case spSetPositonY: PositionControlTaskData posYData = { 0 }; 8005bdc: f04f 0300 mov.w r3, #0 8005be0: 613b str r3, [r7, #16] if (positionYControlTaskInitArg.positionSettingQueue != NULL) 8005be2: 4b4b ldr r3, [pc, #300] @ (8005d10 ) 8005be4: 691b ldr r3, [r3, #16] 8005be6: 2b00 cmp r3, #0 8005be8: d066 beq.n 8005cb8 { float posYPercent = 0; 8005bea: f04f 0300 mov.w r3, #0 8005bee: 60bb str r3, [r7, #8] ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posYPercent); 8005bf0: 683b ldr r3, [r7, #0] 8005bf2: 330c adds r3, #12 8005bf4: f107 0208 add.w r2, r7, #8 8005bf8: f107 0144 add.w r1, r7, #68 @ 0x44 8005bfc: 4618 mov r0, r3 8005bfe: f7fd ff00 bl 8003a02 float posYDegress = MAX_Y_AXE_ANGLE * posYPercent * 0.01; 8005c02: edd7 7a02 vldr s15, [r7, #8] 8005c06: ed9f 7a43 vldr s14, [pc, #268] @ 8005d14 8005c0a: ee67 7a87 vmul.f32 s15, s15, s14 8005c0e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8005c12: ed9f 6b3d vldr d6, [pc, #244] @ 8005d08 8005c16: ee27 7b06 vmul.f64 d7, d7, d6 8005c1a: eef7 7bc7 vcvt.f32.f64 s15, d7 8005c1e: edc7 7a1b vstr s15, [r7, #108] @ 0x6c float angleDelta = 360 / ENCODER_Y_IMP_PER_TURN; 8005c22: 4b3d ldr r3, [pc, #244] @ (8005d18 ) 8005c24: 66bb str r3, [r7, #104] @ 0x68 float rest = fmodf(posYDegress, angleDelta); 8005c26: edd7 0a1a vldr s1, [r7, #104] @ 0x68 8005c2a: ed97 0a1b vldr s0, [r7, #108] @ 0x6c 8005c2e: f012 fc59 bl 80184e4 8005c32: ed87 0a19 vstr s0, [r7, #100] @ 0x64 if ( rest > (angleDelta/2)) 8005c36: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8005c3a: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0 8005c3e: eec7 7a26 vdiv.f32 s15, s14, s13 8005c42: ed97 7a19 vldr s14, [r7, #100] @ 0x64 8005c46: eeb4 7ae7 vcmpe.f32 s14, s15 8005c4a: eef1 fa10 vmrs APSR_nzcv, fpscr 8005c4e: dd14 ble.n 8005c7a { posYData.positionSettingValue = 100 * (posYDegress - rest + angleDelta) / MAX_Y_AXE_ANGLE; 8005c50: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8005c54: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8005c58: ee37 7a67 vsub.f32 s14, s14, s15 8005c5c: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8005c60: ee77 7a27 vadd.f32 s15, s14, s15 8005c64: ed9f 7a2d vldr s14, [pc, #180] @ 8005d1c 8005c68: ee27 7a87 vmul.f32 s14, s15, s14 8005c6c: eddf 6a29 vldr s13, [pc, #164] @ 8005d14 8005c70: eec7 7a26 vdiv.f32 s15, s14, s13 8005c74: edc7 7a04 vstr s15, [r7, #16] 8005c78: e00f b.n 8005c9a } else { posYData.positionSettingValue = 100 * (posYDegress - rest) / MAX_Y_AXE_ANGLE; 8005c7a: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8005c7e: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8005c82: ee77 7a67 vsub.f32 s15, s14, s15 8005c86: ed9f 7a25 vldr s14, [pc, #148] @ 8005d1c 8005c8a: ee27 7a87 vmul.f32 s14, s15, s14 8005c8e: eddf 6a21 vldr s13, [pc, #132] @ 8005d14 8005c92: eec7 7a26 vdiv.f32 s15, s14, s13 8005c96: edc7 7a04 vstr s15, [r7, #16] } osMessageQueuePut(positionYControlTaskInitArg.positionSettingQueue, &posYData, 0, 0); 8005c9a: 4b1d ldr r3, [pc, #116] @ (8005d10 ) 8005c9c: 6918 ldr r0, [r3, #16] 8005c9e: f107 0110 add.w r1, r7, #16 8005ca2: 2300 movs r3, #0 8005ca4: 2200 movs r2, #0 8005ca6: f00e fd01 bl 80146ac } break; 8005caa: e005 b.n 8005cb8 default: respStatus = spUnknownCommand; break; 8005cac: 23fd movs r3, #253 @ 0xfd 8005cae: f887 3097 strb.w r3, [r7, #151] @ 0x97 8005cb2: e002 b.n 8005cba break; 8005cb4: bf00 nop 8005cb6: e000 b.n 8005cba break; 8005cb8: bf00 nop } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8005cba: 6f7b ldr r3, [r7, #116] @ 0x74 8005cbc: 6898 ldr r0, [r3, #8] 8005cbe: 683b ldr r3, [r7, #0] 8005cc0: 8819 ldrh r1, [r3, #0] 8005cc2: 683b ldr r3, [r7, #0] 8005cc4: 789a ldrb r2, [r3, #2] 8005cc6: 4b16 ldr r3, [pc, #88] @ (8005d20 ) 8005cc8: 881b ldrh r3, [r3, #0] 8005cca: f997 4097 ldrsb.w r4, [r7, #151] @ 0x97 8005cce: 9301 str r3, [sp, #4] 8005cd0: 4b14 ldr r3, [pc, #80] @ (8005d24 ) 8005cd2: 9300 str r3, [sp, #0] 8005cd4: 4623 mov r3, r4 8005cd6: f7fd fefd bl 8003ad4 8005cda: 4603 mov r3, r0 8005cdc: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 if (dataToSend > 0) { 8005ce0: f8b7 3072 ldrh.w r3, [r7, #114] @ 0x72 8005ce4: 2b00 cmp r3, #0 8005ce6: d008 beq.n 8005cfa HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8005ce8: 6f7b ldr r3, [r7, #116] @ 0x74 8005cea: 6b18 ldr r0, [r3, #48] @ 0x30 8005cec: 6f7b ldr r3, [r7, #116] @ 0x74 8005cee: 689b ldr r3, [r3, #8] 8005cf0: f8b7 2072 ldrh.w r2, [r7, #114] @ 0x72 8005cf4: 4619 mov r1, r3 8005cf6: f00b fbb1 bl 801145c } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); #endif } 8005cfa: bf00 nop 8005cfc: 379c adds r7, #156 @ 0x9c 8005cfe: 46bd mov sp, r7 8005d00: bd90 pop {r4, r7, pc} 8005d02: bf00 nop 8005d04: f3af 8000 nop.w 8005d08: 47ae147b .word 0x47ae147b 8005d0c: 3f847ae1 .word 0x3f847ae1 8005d10: 240008e8 .word 0x240008e8 8005d14: 43b40000 .word 0x43b40000 8005d18: 41900000 .word 0x41900000 8005d1c: 42c80000 .word 0x42c80000 8005d20: 2400105c .word 0x2400105c 8005d24: 24000fdc .word 0x24000fdc 08005d28 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8005d28: f8df d034 ldr.w sp, [pc, #52] @ 8005d60 /* Call the clock system initialization function.*/ bl SystemInit 8005d2c: f7fe fdae bl 800488c /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8005d30: 480c ldr r0, [pc, #48] @ (8005d64 ) ldr r1, =_edata 8005d32: 490d ldr r1, [pc, #52] @ (8005d68 ) ldr r2, =_sidata 8005d34: 4a0d ldr r2, [pc, #52] @ (8005d6c ) movs r3, #0 8005d36: 2300 movs r3, #0 b LoopCopyDataInit 8005d38: e002 b.n 8005d40 08005d3a : CopyDataInit: ldr r4, [r2, r3] 8005d3a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8005d3c: 50c4 str r4, [r0, r3] adds r3, r3, #4 8005d3e: 3304 adds r3, #4 08005d40 : LoopCopyDataInit: adds r4, r0, r3 8005d40: 18c4 adds r4, r0, r3 cmp r4, r1 8005d42: 428c cmp r4, r1 bcc CopyDataInit 8005d44: d3f9 bcc.n 8005d3a /* Zero fill the bss segment. */ ldr r2, =_sbss 8005d46: 4a0a ldr r2, [pc, #40] @ (8005d70 ) ldr r4, =_ebss 8005d48: 4c0a ldr r4, [pc, #40] @ (8005d74 ) movs r3, #0 8005d4a: 2300 movs r3, #0 b LoopFillZerobss 8005d4c: e001 b.n 8005d52 08005d4e : FillZerobss: str r3, [r2] 8005d4e: 6013 str r3, [r2, #0] adds r2, r2, #4 8005d50: 3204 adds r2, #4 08005d52 : LoopFillZerobss: cmp r2, r4 8005d52: 42a2 cmp r2, r4 bcc FillZerobss 8005d54: d3fb bcc.n 8005d4e /* Call static constructors */ bl __libc_init_array 8005d56: f012 fb3b bl 80183d0 <__libc_init_array> /* Call the application's entry point.*/ bl main 8005d5a: f7fa fc7b bl 8000654
bx lr 8005d5e: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8005d60: 24060000 .word 0x24060000 ldr r0, =_sdata 8005d64: 24000000 .word 0x24000000 ldr r1, =_edata 8005d68: 24000098 .word 0x24000098 ldr r2, =_sidata 8005d6c: 08018754 .word 0x08018754 ldr r2, =_sbss 8005d70: 240000a0 .word 0x240000a0 ldr r4, =_ebss 8005d74: 2401318c .word 0x2401318c 08005d78 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005d78: e7fe b.n 8005d78 ... 08005d7c : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8005d7c: b580 push {r7, lr} 8005d7e: b082 sub sp, #8 8005d80: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005d82: 2003 movs r0, #3 8005d84: f001 fee5 bl 8007b52 /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8005d88: f006 fbee bl 800c568 8005d8c: 4602 mov r2, r0 8005d8e: 4b15 ldr r3, [pc, #84] @ (8005de4 ) 8005d90: 699b ldr r3, [r3, #24] 8005d92: 0a1b lsrs r3, r3, #8 8005d94: f003 030f and.w r3, r3, #15 8005d98: 4913 ldr r1, [pc, #76] @ (8005de8 ) 8005d9a: 5ccb ldrb r3, [r1, r3] 8005d9c: f003 031f and.w r3, r3, #31 8005da0: fa22 f303 lsr.w r3, r2, r3 8005da4: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005da6: 4b0f ldr r3, [pc, #60] @ (8005de4 ) 8005da8: 699b ldr r3, [r3, #24] 8005daa: f003 030f and.w r3, r3, #15 8005dae: 4a0e ldr r2, [pc, #56] @ (8005de8 ) 8005db0: 5cd3 ldrb r3, [r2, r3] 8005db2: f003 031f and.w r3, r3, #31 8005db6: 687a ldr r2, [r7, #4] 8005db8: fa22 f303 lsr.w r3, r2, r3 8005dbc: 4a0b ldr r2, [pc, #44] @ (8005dec ) 8005dbe: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005dc0: 4a0b ldr r2, [pc, #44] @ (8005df0 ) 8005dc2: 687b ldr r3, [r7, #4] 8005dc4: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8005dc6: 2005 movs r0, #5 8005dc8: f7fe fc58 bl 800467c 8005dcc: 4603 mov r3, r0 8005dce: 2b00 cmp r3, #0 8005dd0: d001 beq.n 8005dd6 { return HAL_ERROR; 8005dd2: 2301 movs r3, #1 8005dd4: e002 b.n 8005ddc } /* Init the low level hardware */ HAL_MspInit(); 8005dd6: f7fd ff1b bl 8003c10 /* Return function status */ return HAL_OK; 8005dda: 2300 movs r3, #0 } 8005ddc: 4618 mov r0, r3 8005dde: 3708 adds r7, #8 8005de0: 46bd mov sp, r7 8005de2: bd80 pop {r7, pc} 8005de4: 58024400 .word 0x58024400 8005de8: 080186fc .word 0x080186fc 8005dec: 24000038 .word 0x24000038 8005df0: 24000034 .word 0x24000034 08005df4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8005df4: b480 push {r7} 8005df6: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8005df8: 4b06 ldr r3, [pc, #24] @ (8005e14 ) 8005dfa: 781b ldrb r3, [r3, #0] 8005dfc: 461a mov r2, r3 8005dfe: 4b06 ldr r3, [pc, #24] @ (8005e18 ) 8005e00: 681b ldr r3, [r3, #0] 8005e02: 4413 add r3, r2 8005e04: 4a04 ldr r2, [pc, #16] @ (8005e18 ) 8005e06: 6013 str r3, [r2, #0] } 8005e08: bf00 nop 8005e0a: 46bd mov sp, r7 8005e0c: f85d 7b04 ldr.w r7, [sp], #4 8005e10: 4770 bx lr 8005e12: bf00 nop 8005e14: 24000040 .word 0x24000040 8005e18: 24001060 .word 0x24001060 08005e1c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8005e1c: b480 push {r7} 8005e1e: af00 add r7, sp, #0 return uwTick; 8005e20: 4b03 ldr r3, [pc, #12] @ (8005e30 ) 8005e22: 681b ldr r3, [r3, #0] } 8005e24: 4618 mov r0, r3 8005e26: 46bd mov sp, r7 8005e28: f85d 7b04 ldr.w r7, [sp], #4 8005e2c: 4770 bx lr 8005e2e: bf00 nop 8005e30: 24001060 .word 0x24001060 08005e34 : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 8005e34: b480 push {r7} 8005e36: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 8005e38: 4b03 ldr r3, [pc, #12] @ (8005e48 ) 8005e3a: 681b ldr r3, [r3, #0] 8005e3c: 0c1b lsrs r3, r3, #16 } 8005e3e: 4618 mov r0, r3 8005e40: 46bd mov sp, r7 8005e42: f85d 7b04 ldr.w r7, [sp], #4 8005e46: 4770 bx lr 8005e48: 5c001000 .word 0x5c001000 08005e4c : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 8005e4c: b480 push {r7} 8005e4e: b083 sub sp, #12 8005e50: af00 add r7, sp, #0 8005e52: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 8005e54: 4b06 ldr r3, [pc, #24] @ (8005e70 ) 8005e56: 681b ldr r3, [r3, #0] 8005e58: f023 0202 bic.w r2, r3, #2 8005e5c: 4904 ldr r1, [pc, #16] @ (8005e70 ) 8005e5e: 687b ldr r3, [r7, #4] 8005e60: 4313 orrs r3, r2 8005e62: 600b str r3, [r1, #0] } 8005e64: bf00 nop 8005e66: 370c adds r7, #12 8005e68: 46bd mov sp, r7 8005e6a: f85d 7b04 ldr.w r7, [sp], #4 8005e6e: 4770 bx lr 8005e70: 58003c00 .word 0x58003c00 08005e74 : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 8005e74: b480 push {r7} 8005e76: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 8005e78: 4b05 ldr r3, [pc, #20] @ (8005e90 ) 8005e7a: 681b ldr r3, [r3, #0] 8005e7c: 4a04 ldr r2, [pc, #16] @ (8005e90 ) 8005e7e: f023 0301 bic.w r3, r3, #1 8005e82: 6013 str r3, [r2, #0] } 8005e84: bf00 nop 8005e86: 46bd mov sp, r7 8005e88: f85d 7b04 ldr.w r7, [sp], #4 8005e8c: 4770 bx lr 8005e8e: bf00 nop 8005e90: 58003c00 .word 0x58003c00 08005e94 : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8005e94: b480 push {r7} 8005e96: b083 sub sp, #12 8005e98: af00 add r7, sp, #0 8005e9a: 6078 str r0, [r7, #4] 8005e9c: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 8005e9e: 4b07 ldr r3, [pc, #28] @ (8005ebc ) 8005ea0: 685a ldr r2, [r3, #4] 8005ea2: 687b ldr r3, [r7, #4] 8005ea4: 43db mvns r3, r3 8005ea6: 401a ands r2, r3 8005ea8: 4904 ldr r1, [pc, #16] @ (8005ebc ) 8005eaa: 683b ldr r3, [r7, #0] 8005eac: 4313 orrs r3, r2 8005eae: 604b str r3, [r1, #4] } 8005eb0: bf00 nop 8005eb2: 370c adds r7, #12 8005eb4: 46bd mov sp, r7 8005eb6: f85d 7b04 ldr.w r7, [sp], #4 8005eba: 4770 bx lr 8005ebc: 58000400 .word 0x58000400 08005ec0 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8005ec0: b480 push {r7} 8005ec2: b083 sub sp, #12 8005ec4: af00 add r7, sp, #0 8005ec6: 6078 str r0, [r7, #4] 8005ec8: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8005eca: 687b ldr r3, [r7, #4] 8005ecc: 689b ldr r3, [r3, #8] 8005ece: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8005ed2: 683b ldr r3, [r7, #0] 8005ed4: 431a orrs r2, r3 8005ed6: 687b ldr r3, [r7, #4] 8005ed8: 609a str r2, [r3, #8] } 8005eda: bf00 nop 8005edc: 370c adds r7, #12 8005ede: 46bd mov sp, r7 8005ee0: f85d 7b04 ldr.w r7, [sp], #4 8005ee4: 4770 bx lr 08005ee6 : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8005ee6: b480 push {r7} 8005ee8: b083 sub sp, #12 8005eea: af00 add r7, sp, #0 8005eec: 6078 str r0, [r7, #4] 8005eee: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8005ef0: 687b ldr r3, [r7, #4] 8005ef2: 689b ldr r3, [r3, #8] 8005ef4: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8005ef8: 683b ldr r3, [r7, #0] 8005efa: 431a orrs r2, r3 8005efc: 687b ldr r3, [r7, #4] 8005efe: 609a str r2, [r3, #8] } 8005f00: bf00 nop 8005f02: 370c adds r7, #12 8005f04: 46bd mov sp, r7 8005f06: f85d 7b04 ldr.w r7, [sp], #4 8005f0a: 4770 bx lr 08005f0c : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { 8005f0c: b480 push {r7} 8005f0e: b083 sub sp, #12 8005f10: af00 add r7, sp, #0 8005f12: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8005f14: 687b ldr r3, [r7, #4] 8005f16: 689b ldr r3, [r3, #8] 8005f18: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 8005f1c: 4618 mov r0, r3 8005f1e: 370c adds r7, #12 8005f20: 46bd mov sp, r7 8005f22: f85d 7b04 ldr.w r7, [sp], #4 8005f26: 4770 bx lr 08005f28 : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 8005f28: b480 push {r7} 8005f2a: b087 sub sp, #28 8005f2c: af00 add r7, sp, #0 8005f2e: 60f8 str r0, [r7, #12] 8005f30: 60b9 str r1, [r7, #8] 8005f32: 607a str r2, [r7, #4] 8005f34: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005f36: 68fb ldr r3, [r7, #12] 8005f38: 3360 adds r3, #96 @ 0x60 8005f3a: 461a mov r2, r3 8005f3c: 68bb ldr r3, [r7, #8] 8005f3e: 009b lsls r3, r3, #2 8005f40: 4413 add r3, r2 8005f42: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 8005f44: 697b ldr r3, [r7, #20] 8005f46: 681b ldr r3, [r3, #0] 8005f48: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 8005f4c: 687b ldr r3, [r7, #4] 8005f4e: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 8005f52: 683b ldr r3, [r7, #0] 8005f54: 430b orrs r3, r1 8005f56: 431a orrs r2, r3 8005f58: 697b ldr r3, [r7, #20] 8005f5a: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 8005f5c: bf00 nop 8005f5e: 371c adds r7, #28 8005f60: 46bd mov sp, r7 8005f62: f85d 7b04 ldr.w r7, [sp], #4 8005f66: 4770 bx lr 08005f68 : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 8005f68: b480 push {r7} 8005f6a: b085 sub sp, #20 8005f6c: af00 add r7, sp, #0 8005f6e: 60f8 str r0, [r7, #12] 8005f70: 60b9 str r1, [r7, #8] 8005f72: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 8005f74: 68fb ldr r3, [r7, #12] 8005f76: 691b ldr r3, [r3, #16] 8005f78: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 8005f7c: 68bb ldr r3, [r7, #8] 8005f7e: f003 031f and.w r3, r3, #31 8005f82: 6879 ldr r1, [r7, #4] 8005f84: fa01 f303 lsl.w r3, r1, r3 8005f88: 431a orrs r2, r3 8005f8a: 68fb ldr r3, [r7, #12] 8005f8c: 611a str r2, [r3, #16] } 8005f8e: bf00 nop 8005f90: 3714 adds r7, #20 8005f92: 46bd mov sp, r7 8005f94: f85d 7b04 ldr.w r7, [sp], #4 8005f98: 4770 bx lr 08005f9a : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 8005f9a: b480 push {r7} 8005f9c: b087 sub sp, #28 8005f9e: af00 add r7, sp, #0 8005fa0: 60f8 str r0, [r7, #12] 8005fa2: 60b9 str r1, [r7, #8] 8005fa4: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005fa6: 68fb ldr r3, [r7, #12] 8005fa8: 3360 adds r3, #96 @ 0x60 8005faa: 461a mov r2, r3 8005fac: 68bb ldr r3, [r7, #8] 8005fae: 009b lsls r3, r3, #2 8005fb0: 4413 add r3, r2 8005fb2: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8005fb4: 697b ldr r3, [r7, #20] 8005fb6: 681b ldr r3, [r3, #0] 8005fb8: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8005fbc: 687b ldr r3, [r7, #4] 8005fbe: 431a orrs r2, r3 8005fc0: 697b ldr r3, [r7, #20] 8005fc2: 601a str r2, [r3, #0] } } 8005fc4: bf00 nop 8005fc6: 371c adds r7, #28 8005fc8: 46bd mov sp, r7 8005fca: f85d 7b04 ldr.w r7, [sp], #4 8005fce: 4770 bx lr 08005fd0 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { 8005fd0: b480 push {r7} 8005fd2: b083 sub sp, #12 8005fd4: af00 add r7, sp, #0 8005fd6: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8005fd8: 687b ldr r3, [r7, #4] 8005fda: 68db ldr r3, [r3, #12] 8005fdc: f403 6340 and.w r3, r3, #3072 @ 0xc00 8005fe0: 2b00 cmp r3, #0 8005fe2: d101 bne.n 8005fe8 8005fe4: 2301 movs r3, #1 8005fe6: e000 b.n 8005fea 8005fe8: 2300 movs r3, #0 } 8005fea: 4618 mov r0, r3 8005fec: 370c adds r7, #12 8005fee: 46bd mov sp, r7 8005ff0: f85d 7b04 ldr.w r7, [sp], #4 8005ff4: 4770 bx lr 08005ff6 : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8005ff6: b480 push {r7} 8005ff8: b087 sub sp, #28 8005ffa: af00 add r7, sp, #0 8005ffc: 60f8 str r0, [r7, #12] 8005ffe: 60b9 str r1, [r7, #8] 8006000: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 8006002: 68fb ldr r3, [r7, #12] 8006004: 3330 adds r3, #48 @ 0x30 8006006: 461a mov r2, r3 8006008: 68bb ldr r3, [r7, #8] 800600a: 0a1b lsrs r3, r3, #8 800600c: 009b lsls r3, r3, #2 800600e: f003 030c and.w r3, r3, #12 8006012: 4413 add r3, r2 8006014: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8006016: 697b ldr r3, [r7, #20] 8006018: 681a ldr r2, [r3, #0] 800601a: 68bb ldr r3, [r7, #8] 800601c: f003 031f and.w r3, r3, #31 8006020: 211f movs r1, #31 8006022: fa01 f303 lsl.w r3, r1, r3 8006026: 43db mvns r3, r3 8006028: 401a ands r2, r3 800602a: 687b ldr r3, [r7, #4] 800602c: 0e9b lsrs r3, r3, #26 800602e: f003 011f and.w r1, r3, #31 8006032: 68bb ldr r3, [r7, #8] 8006034: f003 031f and.w r3, r3, #31 8006038: fa01 f303 lsl.w r3, r1, r3 800603c: 431a orrs r2, r3 800603e: 697b ldr r3, [r7, #20] 8006040: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 8006042: bf00 nop 8006044: 371c adds r7, #28 8006046: 46bd mov sp, r7 8006048: f85d 7b04 ldr.w r7, [sp], #4 800604c: 4770 bx lr 0800604e : * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) { 800604e: b480 push {r7} 8006050: b083 sub sp, #12 8006052: af00 add r7, sp, #0 8006054: 6078 str r0, [r7, #4] 8006056: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 8006058: 687b ldr r3, [r7, #4] 800605a: 68db ldr r3, [r3, #12] 800605c: f023 0203 bic.w r2, r3, #3 8006060: 683b ldr r3, [r7, #0] 8006062: 431a orrs r2, r3 8006064: 687b ldr r3, [r7, #4] 8006066: 60da str r2, [r3, #12] } 8006068: bf00 nop 800606a: 370c adds r7, #12 800606c: 46bd mov sp, r7 800606e: f85d 7b04 ldr.w r7, [sp], #4 8006072: 4770 bx lr 08006074 : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 8006074: b480 push {r7} 8006076: b087 sub sp, #28 8006078: af00 add r7, sp, #0 800607a: 60f8 str r0, [r7, #12] 800607c: 60b9 str r1, [r7, #8] 800607e: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8006080: 68fb ldr r3, [r7, #12] 8006082: 3314 adds r3, #20 8006084: 461a mov r2, r3 8006086: 68bb ldr r3, [r7, #8] 8006088: 0e5b lsrs r3, r3, #25 800608a: 009b lsls r3, r3, #2 800608c: f003 0304 and.w r3, r3, #4 8006090: 4413 add r3, r2 8006092: 617b str r3, [r7, #20] MODIFY_REG(*preg, 8006094: 697b ldr r3, [r7, #20] 8006096: 681a ldr r2, [r3, #0] 8006098: 68bb ldr r3, [r7, #8] 800609a: 0d1b lsrs r3, r3, #20 800609c: f003 031f and.w r3, r3, #31 80060a0: 2107 movs r1, #7 80060a2: fa01 f303 lsl.w r3, r1, r3 80060a6: 43db mvns r3, r3 80060a8: 401a ands r2, r3 80060aa: 68bb ldr r3, [r7, #8] 80060ac: 0d1b lsrs r3, r3, #20 80060ae: f003 031f and.w r3, r3, #31 80060b2: 6879 ldr r1, [r7, #4] 80060b4: fa01 f303 lsl.w r3, r1, r3 80060b8: 431a orrs r2, r3 80060ba: 697b ldr r3, [r7, #20] 80060bc: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 80060be: bf00 nop 80060c0: 371c adds r7, #28 80060c2: 46bd mov sp, r7 80060c4: f85d 7b04 ldr.w r7, [sp], #4 80060c8: 4770 bx lr ... 080060cc : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 80060cc: b480 push {r7} 80060ce: b085 sub sp, #20 80060d0: af00 add r7, sp, #0 80060d2: 60f8 str r0, [r7, #12] 80060d4: 60b9 str r1, [r7, #8] 80060d6: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 80060d8: 68fb ldr r3, [r7, #12] 80060da: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 80060de: 68bb ldr r3, [r7, #8] 80060e0: f3c3 0313 ubfx r3, r3, #0, #20 80060e4: 43db mvns r3, r3 80060e6: 401a ands r2, r3 80060e8: 687b ldr r3, [r7, #4] 80060ea: f003 0318 and.w r3, r3, #24 80060ee: 4908 ldr r1, [pc, #32] @ (8006110 ) 80060f0: 40d9 lsrs r1, r3 80060f2: 68bb ldr r3, [r7, #8] 80060f4: 400b ands r3, r1 80060f6: f3c3 0313 ubfx r3, r3, #0, #20 80060fa: 431a orrs r2, r3 80060fc: 68fb ldr r3, [r7, #12] 80060fe: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 8006102: bf00 nop 8006104: 3714 adds r7, #20 8006106: 46bd mov sp, r7 8006108: f85d 7b04 ldr.w r7, [sp], #4 800610c: 4770 bx lr 800610e: bf00 nop 8006110: 000fffff .word 0x000fffff 08006114 : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { 8006114: b480 push {r7} 8006116: b083 sub sp, #12 8006118: af00 add r7, sp, #0 800611a: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 800611c: 687b ldr r3, [r7, #4] 800611e: 689b ldr r3, [r3, #8] 8006120: f003 031f and.w r3, r3, #31 } 8006124: 4618 mov r0, r3 8006126: 370c adds r7, #12 8006128: 46bd mov sp, r7 800612a: f85d 7b04 ldr.w r7, [sp], #4 800612e: 4770 bx lr 08006130 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 8006130: b480 push {r7} 8006132: b083 sub sp, #12 8006134: af00 add r7, sp, #0 8006136: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8006138: 687b ldr r3, [r7, #4] 800613a: 689a ldr r2, [r3, #8] 800613c: 4b04 ldr r3, [pc, #16] @ (8006150 ) 800613e: 4013 ands r3, r2 8006140: 687a ldr r2, [r7, #4] 8006142: 6093 str r3, [r2, #8] } 8006144: bf00 nop 8006146: 370c adds r7, #12 8006148: 46bd mov sp, r7 800614a: f85d 7b04 ldr.w r7, [sp], #4 800614e: 4770 bx lr 8006150: 5fffffc0 .word 0x5fffffc0 08006154 : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { 8006154: b480 push {r7} 8006156: b083 sub sp, #12 8006158: af00 add r7, sp, #0 800615a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 800615c: 687b ldr r3, [r7, #4] 800615e: 689b ldr r3, [r3, #8] 8006160: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8006164: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006168: d101 bne.n 800616e 800616a: 2301 movs r3, #1 800616c: e000 b.n 8006170 800616e: 2300 movs r3, #0 } 8006170: 4618 mov r0, r3 8006172: 370c adds r7, #12 8006174: 46bd mov sp, r7 8006176: f85d 7b04 ldr.w r7, [sp], #4 800617a: 4770 bx lr 0800617c : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 800617c: b480 push {r7} 800617e: b083 sub sp, #12 8006180: af00 add r7, sp, #0 8006182: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8006184: 687b ldr r3, [r7, #4] 8006186: 689a ldr r2, [r3, #8] 8006188: 4b05 ldr r3, [pc, #20] @ (80061a0 ) 800618a: 4013 ands r3, r2 800618c: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8006190: 687b ldr r3, [r7, #4] 8006192: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 8006194: bf00 nop 8006196: 370c adds r7, #12 8006198: 46bd mov sp, r7 800619a: f85d 7b04 ldr.w r7, [sp], #4 800619e: 4770 bx lr 80061a0: 6fffffc0 .word 0x6fffffc0 080061a4 : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { 80061a4: b480 push {r7} 80061a6: b083 sub sp, #12 80061a8: af00 add r7, sp, #0 80061aa: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 80061ac: 687b ldr r3, [r7, #4] 80061ae: 689b ldr r3, [r3, #8] 80061b0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80061b4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80061b8: d101 bne.n 80061be 80061ba: 2301 movs r3, #1 80061bc: e000 b.n 80061c0 80061be: 2300 movs r3, #0 } 80061c0: 4618 mov r0, r3 80061c2: 370c adds r7, #12 80061c4: 46bd mov sp, r7 80061c6: f85d 7b04 ldr.w r7, [sp], #4 80061ca: 4770 bx lr 080061cc : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 80061cc: b480 push {r7} 80061ce: b083 sub sp, #12 80061d0: af00 add r7, sp, #0 80061d2: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80061d4: 687b ldr r3, [r7, #4] 80061d6: 689a ldr r2, [r3, #8] 80061d8: 4b05 ldr r3, [pc, #20] @ (80061f0 ) 80061da: 4013 ands r3, r2 80061dc: f043 0201 orr.w r2, r3, #1 80061e0: 687b ldr r3, [r7, #4] 80061e2: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 80061e4: bf00 nop 80061e6: 370c adds r7, #12 80061e8: 46bd mov sp, r7 80061ea: f85d 7b04 ldr.w r7, [sp], #4 80061ee: 4770 bx lr 80061f0: 7fffffc0 .word 0x7fffffc0 080061f4 : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 80061f4: b480 push {r7} 80061f6: b083 sub sp, #12 80061f8: af00 add r7, sp, #0 80061fa: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80061fc: 687b ldr r3, [r7, #4] 80061fe: 689a ldr r2, [r3, #8] 8006200: 4b05 ldr r3, [pc, #20] @ (8006218 ) 8006202: 4013 ands r3, r2 8006204: f043 0202 orr.w r2, r3, #2 8006208: 687b ldr r3, [r7, #4] 800620a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 800620c: bf00 nop 800620e: 370c adds r7, #12 8006210: 46bd mov sp, r7 8006212: f85d 7b04 ldr.w r7, [sp], #4 8006216: 4770 bx lr 8006218: 7fffffc0 .word 0x7fffffc0 0800621c : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { 800621c: b480 push {r7} 800621e: b083 sub sp, #12 8006220: af00 add r7, sp, #0 8006222: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 8006224: 687b ldr r3, [r7, #4] 8006226: 689b ldr r3, [r3, #8] 8006228: f003 0301 and.w r3, r3, #1 800622c: 2b01 cmp r3, #1 800622e: d101 bne.n 8006234 8006230: 2301 movs r3, #1 8006232: e000 b.n 8006236 8006234: 2300 movs r3, #0 } 8006236: 4618 mov r0, r3 8006238: 370c adds r7, #12 800623a: 46bd mov sp, r7 800623c: f85d 7b04 ldr.w r7, [sp], #4 8006240: 4770 bx lr 08006242 : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { 8006242: b480 push {r7} 8006244: b083 sub sp, #12 8006246: af00 add r7, sp, #0 8006248: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 800624a: 687b ldr r3, [r7, #4] 800624c: 689b ldr r3, [r3, #8] 800624e: f003 0302 and.w r3, r3, #2 8006252: 2b02 cmp r3, #2 8006254: d101 bne.n 800625a 8006256: 2301 movs r3, #1 8006258: e000 b.n 800625c 800625a: 2300 movs r3, #0 } 800625c: 4618 mov r0, r3 800625e: 370c adds r7, #12 8006260: 46bd mov sp, r7 8006262: f85d 7b04 ldr.w r7, [sp], #4 8006266: 4770 bx lr 08006268 : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8006268: b480 push {r7} 800626a: b083 sub sp, #12 800626c: af00 add r7, sp, #0 800626e: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8006270: 687b ldr r3, [r7, #4] 8006272: 689a ldr r2, [r3, #8] 8006274: 4b05 ldr r3, [pc, #20] @ (800628c ) 8006276: 4013 ands r3, r2 8006278: f043 0204 orr.w r2, r3, #4 800627c: 687b ldr r3, [r7, #4] 800627e: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8006280: bf00 nop 8006282: 370c adds r7, #12 8006284: 46bd mov sp, r7 8006286: f85d 7b04 ldr.w r7, [sp], #4 800628a: 4770 bx lr 800628c: 7fffffc0 .word 0x7fffffc0 08006290 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { 8006290: b480 push {r7} 8006292: b083 sub sp, #12 8006294: af00 add r7, sp, #0 8006296: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8006298: 687b ldr r3, [r7, #4] 800629a: 689b ldr r3, [r3, #8] 800629c: f003 0304 and.w r3, r3, #4 80062a0: 2b04 cmp r3, #4 80062a2: d101 bne.n 80062a8 80062a4: 2301 movs r3, #1 80062a6: e000 b.n 80062aa 80062a8: 2300 movs r3, #0 } 80062aa: 4618 mov r0, r3 80062ac: 370c adds r7, #12 80062ae: 46bd mov sp, r7 80062b0: f85d 7b04 ldr.w r7, [sp], #4 80062b4: 4770 bx lr 080062b6 : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { 80062b6: b480 push {r7} 80062b8: b083 sub sp, #12 80062ba: af00 add r7, sp, #0 80062bc: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 80062be: 687b ldr r3, [r7, #4] 80062c0: 689b ldr r3, [r3, #8] 80062c2: f003 0308 and.w r3, r3, #8 80062c6: 2b08 cmp r3, #8 80062c8: d101 bne.n 80062ce 80062ca: 2301 movs r3, #1 80062cc: e000 b.n 80062d0 80062ce: 2300 movs r3, #0 } 80062d0: 4618 mov r0, r3 80062d2: 370c adds r7, #12 80062d4: 46bd mov sp, r7 80062d6: f85d 7b04 ldr.w r7, [sp], #4 80062da: 4770 bx lr 080062dc : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 80062dc: b590 push {r4, r7, lr} 80062de: b089 sub sp, #36 @ 0x24 80062e0: af00 add r7, sp, #0 80062e2: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80062e4: 2300 movs r3, #0 80062e6: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 80062e8: 2300 movs r3, #0 80062ea: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 80062ec: 687b ldr r3, [r7, #4] 80062ee: 2b00 cmp r3, #0 80062f0: d101 bne.n 80062f6 { return HAL_ERROR; 80062f2: 2301 movs r3, #1 80062f4: e18f b.n 8006616 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 80062f6: 687b ldr r3, [r7, #4] 80062f8: 68db ldr r3, [r3, #12] 80062fa: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 80062fc: 687b ldr r3, [r7, #4] 80062fe: 6d5b ldr r3, [r3, #84] @ 0x54 8006300: 2b00 cmp r3, #0 8006302: d109 bne.n 8006318 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 8006304: 6878 ldr r0, [r7, #4] 8006306: f7fd fcdf bl 8003cc8 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 800630a: 687b ldr r3, [r7, #4] 800630c: 2200 movs r2, #0 800630e: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8006310: 687b ldr r3, [r7, #4] 8006312: 2200 movs r2, #0 8006314: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8006318: 687b ldr r3, [r7, #4] 800631a: 681b ldr r3, [r3, #0] 800631c: 4618 mov r0, r3 800631e: f7ff ff19 bl 8006154 8006322: 4603 mov r3, r0 8006324: 2b00 cmp r3, #0 8006326: d004 beq.n 8006332 { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 8006328: 687b ldr r3, [r7, #4] 800632a: 681b ldr r3, [r3, #0] 800632c: 4618 mov r0, r3 800632e: f7ff feff bl 8006130 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8006332: 687b ldr r3, [r7, #4] 8006334: 681b ldr r3, [r3, #0] 8006336: 4618 mov r0, r3 8006338: f7ff ff34 bl 80061a4 800633c: 4603 mov r3, r0 800633e: 2b00 cmp r3, #0 8006340: d114 bne.n 800636c { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 8006342: 687b ldr r3, [r7, #4] 8006344: 681b ldr r3, [r3, #0] 8006346: 4618 mov r0, r3 8006348: f7ff ff18 bl 800617c /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800634c: 4b87 ldr r3, [pc, #540] @ (800656c ) 800634e: 681b ldr r3, [r3, #0] 8006350: 099b lsrs r3, r3, #6 8006352: 4a87 ldr r2, [pc, #540] @ (8006570 ) 8006354: fba2 2303 umull r2, r3, r2, r3 8006358: 099b lsrs r3, r3, #6 800635a: 3301 adds r3, #1 800635c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 800635e: e002 b.n 8006366 { wait_loop_index--; 8006360: 68bb ldr r3, [r7, #8] 8006362: 3b01 subs r3, #1 8006364: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006366: 68bb ldr r3, [r7, #8] 8006368: 2b00 cmp r3, #0 800636a: d1f9 bne.n 8006360 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 800636c: 687b ldr r3, [r7, #4] 800636e: 681b ldr r3, [r3, #0] 8006370: 4618 mov r0, r3 8006372: f7ff ff17 bl 80061a4 8006376: 4603 mov r3, r0 8006378: 2b00 cmp r3, #0 800637a: d10d bne.n 8006398 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800637c: 687b ldr r3, [r7, #4] 800637e: 6d5b ldr r3, [r3, #84] @ 0x54 8006380: f043 0210 orr.w r2, r3, #16 8006384: 687b ldr r3, [r7, #4] 8006386: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006388: 687b ldr r3, [r7, #4] 800638a: 6d9b ldr r3, [r3, #88] @ 0x58 800638c: f043 0201 orr.w r2, r3, #1 8006390: 687b ldr r3, [r7, #4] 8006392: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 8006394: 2301 movs r3, #1 8006396: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006398: 687b ldr r3, [r7, #4] 800639a: 681b ldr r3, [r3, #0] 800639c: 4618 mov r0, r3 800639e: f7ff ff77 bl 8006290 80063a2: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 80063a4: 687b ldr r3, [r7, #4] 80063a6: 6d5b ldr r3, [r3, #84] @ 0x54 80063a8: f003 0310 and.w r3, r3, #16 80063ac: 2b00 cmp r3, #0 80063ae: f040 8129 bne.w 8006604 && (tmp_adc_reg_is_conversion_on_going == 0UL) 80063b2: 697b ldr r3, [r7, #20] 80063b4: 2b00 cmp r3, #0 80063b6: f040 8125 bne.w 8006604 ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80063ba: 687b ldr r3, [r7, #4] 80063bc: 6d5b ldr r3, [r3, #84] @ 0x54 80063be: f423 7381 bic.w r3, r3, #258 @ 0x102 80063c2: f043 0202 orr.w r2, r3, #2 80063c6: 687b ldr r3, [r7, #4] 80063c8: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80063ca: 687b ldr r3, [r7, #4] 80063cc: 681b ldr r3, [r3, #0] 80063ce: 4618 mov r0, r3 80063d0: f7ff ff24 bl 800621c 80063d4: 4603 mov r3, r0 80063d6: 2b00 cmp r3, #0 80063d8: d136 bne.n 8006448 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80063da: 687b ldr r3, [r7, #4] 80063dc: 681b ldr r3, [r3, #0] 80063de: 4a65 ldr r2, [pc, #404] @ (8006574 ) 80063e0: 4293 cmp r3, r2 80063e2: d004 beq.n 80063ee 80063e4: 687b ldr r3, [r7, #4] 80063e6: 681b ldr r3, [r3, #0] 80063e8: 4a63 ldr r2, [pc, #396] @ (8006578 ) 80063ea: 4293 cmp r3, r2 80063ec: d10e bne.n 800640c 80063ee: 4861 ldr r0, [pc, #388] @ (8006574 ) 80063f0: f7ff ff14 bl 800621c 80063f4: 4604 mov r4, r0 80063f6: 4860 ldr r0, [pc, #384] @ (8006578 ) 80063f8: f7ff ff10 bl 800621c 80063fc: 4603 mov r3, r0 80063fe: 4323 orrs r3, r4 8006400: 2b00 cmp r3, #0 8006402: bf0c ite eq 8006404: 2301 moveq r3, #1 8006406: 2300 movne r3, #0 8006408: b2db uxtb r3, r3 800640a: e008 b.n 800641e 800640c: 485b ldr r0, [pc, #364] @ (800657c ) 800640e: f7ff ff05 bl 800621c 8006412: 4603 mov r3, r0 8006414: 2b00 cmp r3, #0 8006416: bf0c ite eq 8006418: 2301 moveq r3, #1 800641a: 2300 movne r3, #0 800641c: b2db uxtb r3, r3 800641e: 2b00 cmp r3, #0 8006420: d012 beq.n 8006448 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 8006422: 687b ldr r3, [r7, #4] 8006424: 681b ldr r3, [r3, #0] 8006426: 4a53 ldr r2, [pc, #332] @ (8006574 ) 8006428: 4293 cmp r3, r2 800642a: d004 beq.n 8006436 800642c: 687b ldr r3, [r7, #4] 800642e: 681b ldr r3, [r3, #0] 8006430: 4a51 ldr r2, [pc, #324] @ (8006578 ) 8006432: 4293 cmp r3, r2 8006434: d101 bne.n 800643a 8006436: 4a52 ldr r2, [pc, #328] @ (8006580 ) 8006438: e000 b.n 800643c 800643a: 4a52 ldr r2, [pc, #328] @ (8006584 ) 800643c: 687b ldr r3, [r7, #4] 800643e: 685b ldr r3, [r3, #4] 8006440: 4619 mov r1, r3 8006442: 4610 mov r0, r2 8006444: f7ff fd3c bl 8005ec0 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8006448: f7ff fcf4 bl 8005e34 800644c: 4603 mov r3, r0 800644e: f241 0203 movw r2, #4099 @ 0x1003 8006452: 4293 cmp r3, r2 8006454: d914 bls.n 8006480 8006456: 687b ldr r3, [r7, #4] 8006458: 689b ldr r3, [r3, #8] 800645a: 2b10 cmp r3, #16 800645c: d110 bne.n 8006480 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800645e: 687b ldr r3, [r7, #4] 8006460: 7d5b ldrb r3, [r3, #21] 8006462: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8006464: 687b ldr r3, [r7, #4] 8006466: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006468: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 800646a: 687b ldr r3, [r7, #4] 800646c: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 800646e: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8006470: 687b ldr r3, [r7, #4] 8006472: 7f1b ldrb r3, [r3, #28] 8006474: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8006476: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006478: f043 030c orr.w r3, r3, #12 800647c: 61bb str r3, [r7, #24] 800647e: e00d b.n 800649c } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006480: 687b ldr r3, [r7, #4] 8006482: 7d5b ldrb r3, [r3, #21] 8006484: 035a lsls r2, r3, #13 hadc->Init.Overrun | 8006486: 687b ldr r3, [r7, #4] 8006488: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 800648a: 431a orrs r2, r3 hadc->Init.Resolution | 800648c: 687b ldr r3, [r7, #4] 800648e: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8006490: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8006492: 687b ldr r3, [r7, #4] 8006494: 7f1b ldrb r3, [r3, #28] 8006496: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006498: 4313 orrs r3, r2 800649a: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 800649c: 687b ldr r3, [r7, #4] 800649e: 7f1b ldrb r3, [r3, #28] 80064a0: 2b01 cmp r3, #1 80064a2: d106 bne.n 80064b2 { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 80064a4: 687b ldr r3, [r7, #4] 80064a6: 6a1b ldr r3, [r3, #32] 80064a8: 3b01 subs r3, #1 80064aa: 045b lsls r3, r3, #17 80064ac: 69ba ldr r2, [r7, #24] 80064ae: 4313 orrs r3, r2 80064b0: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 80064b2: 687b ldr r3, [r7, #4] 80064b4: 6a5b ldr r3, [r3, #36] @ 0x24 80064b6: 2b00 cmp r3, #0 80064b8: d009 beq.n 80064ce { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 80064ba: 687b ldr r3, [r7, #4] 80064bc: 6a5b ldr r3, [r3, #36] @ 0x24 80064be: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 80064c2: 687b ldr r3, [r7, #4] 80064c4: 6a9b ldr r3, [r3, #40] @ 0x28 80064c6: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 80064c8: 69ba ldr r2, [r7, #24] 80064ca: 4313 orrs r3, r2 80064cc: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 80064ce: 687b ldr r3, [r7, #4] 80064d0: 681b ldr r3, [r3, #0] 80064d2: 68da ldr r2, [r3, #12] 80064d4: 4b2c ldr r3, [pc, #176] @ (8006588 ) 80064d6: 4013 ands r3, r2 80064d8: 687a ldr r2, [r7, #4] 80064da: 6812 ldr r2, [r2, #0] 80064dc: 69b9 ldr r1, [r7, #24] 80064de: 430b orrs r3, r1 80064e0: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80064e2: 687b ldr r3, [r7, #4] 80064e4: 681b ldr r3, [r3, #0] 80064e6: 4618 mov r0, r3 80064e8: f7ff fed2 bl 8006290 80064ec: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 80064ee: 687b ldr r3, [r7, #4] 80064f0: 681b ldr r3, [r3, #0] 80064f2: 4618 mov r0, r3 80064f4: f7ff fedf bl 80062b6 80064f8: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 80064fa: 693b ldr r3, [r7, #16] 80064fc: 2b00 cmp r3, #0 80064fe: d15f bne.n 80065c0 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8006500: 68fb ldr r3, [r7, #12] 8006502: 2b00 cmp r3, #0 8006504: d15c bne.n 80065c0 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 8006506: 687b ldr r3, [r7, #4] 8006508: 7d1b ldrb r3, [r3, #20] 800650a: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 800650c: 687b ldr r3, [r7, #4] 800650e: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 8006510: 4313 orrs r3, r2 8006512: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 8006514: 687b ldr r3, [r7, #4] 8006516: 681b ldr r3, [r3, #0] 8006518: 68da ldr r2, [r3, #12] 800651a: 4b1c ldr r3, [pc, #112] @ (800658c ) 800651c: 4013 ands r3, r2 800651e: 687a ldr r2, [r7, #4] 8006520: 6812 ldr r2, [r2, #0] 8006522: 69b9 ldr r1, [r7, #24] 8006524: 430b orrs r3, r1 8006526: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 8006528: 687b ldr r3, [r7, #4] 800652a: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 800652e: 2b01 cmp r3, #1 8006530: d130 bne.n 8006594 #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 8006532: 687b ldr r3, [r7, #4] 8006534: 6a5b ldr r3, [r3, #36] @ 0x24 8006536: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 8006538: 687b ldr r3, [r7, #4] 800653a: 681b ldr r3, [r3, #0] 800653c: 691a ldr r2, [r3, #16] 800653e: 4b14 ldr r3, [pc, #80] @ (8006590 ) 8006540: 4013 ands r3, r2 8006542: 687a ldr r2, [r7, #4] 8006544: 6bd2 ldr r2, [r2, #60] @ 0x3c 8006546: 3a01 subs r2, #1 8006548: 0411 lsls r1, r2, #16 800654a: 687a ldr r2, [r7, #4] 800654c: 6c12 ldr r2, [r2, #64] @ 0x40 800654e: 4311 orrs r1, r2 8006550: 687a ldr r2, [r7, #4] 8006552: 6c52 ldr r2, [r2, #68] @ 0x44 8006554: 4311 orrs r1, r2 8006556: 687a ldr r2, [r7, #4] 8006558: 6c92 ldr r2, [r2, #72] @ 0x48 800655a: 430a orrs r2, r1 800655c: 431a orrs r2, r3 800655e: 687b ldr r3, [r7, #4] 8006560: 681b ldr r3, [r3, #0] 8006562: f042 0201 orr.w r2, r2, #1 8006566: 611a str r2, [r3, #16] 8006568: e01c b.n 80065a4 800656a: bf00 nop 800656c: 24000034 .word 0x24000034 8006570: 053e2d63 .word 0x053e2d63 8006574: 40022000 .word 0x40022000 8006578: 40022100 .word 0x40022100 800657c: 58026000 .word 0x58026000 8006580: 40022300 .word 0x40022300 8006584: 58026300 .word 0x58026300 8006588: fff0c003 .word 0xfff0c003 800658c: ffffbffc .word 0xffffbffc 8006590: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 8006594: 687b ldr r3, [r7, #4] 8006596: 681b ldr r3, [r3, #0] 8006598: 691a ldr r2, [r3, #16] 800659a: 687b ldr r3, [r7, #4] 800659c: 681b ldr r3, [r3, #0] 800659e: f022 0201 bic.w r2, r2, #1 80065a2: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 80065a4: 687b ldr r3, [r7, #4] 80065a6: 681b ldr r3, [r3, #0] 80065a8: 691b ldr r3, [r3, #16] 80065aa: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 80065ae: 687b ldr r3, [r7, #4] 80065b0: 6b5a ldr r2, [r3, #52] @ 0x34 80065b2: 687b ldr r3, [r7, #4] 80065b4: 681b ldr r3, [r3, #0] 80065b6: 430a orrs r2, r1 80065b8: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 80065ba: 6878 ldr r0, [r7, #4] 80065bc: f000 fde2 bl 8007184 /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 80065c0: 687b ldr r3, [r7, #4] 80065c2: 68db ldr r3, [r3, #12] 80065c4: 2b01 cmp r3, #1 80065c6: d10c bne.n 80065e2 { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 80065c8: 687b ldr r3, [r7, #4] 80065ca: 681b ldr r3, [r3, #0] 80065cc: 6b1b ldr r3, [r3, #48] @ 0x30 80065ce: f023 010f bic.w r1, r3, #15 80065d2: 687b ldr r3, [r7, #4] 80065d4: 699b ldr r3, [r3, #24] 80065d6: 1e5a subs r2, r3, #1 80065d8: 687b ldr r3, [r7, #4] 80065da: 681b ldr r3, [r3, #0] 80065dc: 430a orrs r2, r1 80065de: 631a str r2, [r3, #48] @ 0x30 80065e0: e007 b.n 80065f2 } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 80065e2: 687b ldr r3, [r7, #4] 80065e4: 681b ldr r3, [r3, #0] 80065e6: 6b1a ldr r2, [r3, #48] @ 0x30 80065e8: 687b ldr r3, [r7, #4] 80065ea: 681b ldr r3, [r3, #0] 80065ec: f022 020f bic.w r2, r2, #15 80065f0: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 80065f2: 687b ldr r3, [r7, #4] 80065f4: 6d5b ldr r3, [r3, #84] @ 0x54 80065f6: f023 0303 bic.w r3, r3, #3 80065fa: f043 0201 orr.w r2, r3, #1 80065fe: 687b ldr r3, [r7, #4] 8006600: 655a str r2, [r3, #84] @ 0x54 8006602: e007 b.n 8006614 } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006604: 687b ldr r3, [r7, #4] 8006606: 6d5b ldr r3, [r3, #84] @ 0x54 8006608: f043 0210 orr.w r2, r3, #16 800660c: 687b ldr r3, [r7, #4] 800660e: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006610: 2301 movs r3, #1 8006612: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 8006614: 7ffb ldrb r3, [r7, #31] } 8006616: 4618 mov r0, r3 8006618: 3724 adds r7, #36 @ 0x24 800661a: 46bd mov sp, r7 800661c: bd90 pop {r4, r7, pc} 800661e: bf00 nop 08006620 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 8006620: b580 push {r7, lr} 8006622: b086 sub sp, #24 8006624: af00 add r7, sp, #0 8006626: 60f8 str r0, [r7, #12] 8006628: 60b9 str r1, [r7, #8] 800662a: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 800662c: 68fb ldr r3, [r7, #12] 800662e: 681b ldr r3, [r3, #0] 8006630: 4a55 ldr r2, [pc, #340] @ (8006788 ) 8006632: 4293 cmp r3, r2 8006634: d004 beq.n 8006640 8006636: 68fb ldr r3, [r7, #12] 8006638: 681b ldr r3, [r3, #0] 800663a: 4a54 ldr r2, [pc, #336] @ (800678c ) 800663c: 4293 cmp r3, r2 800663e: d101 bne.n 8006644 8006640: 4b53 ldr r3, [pc, #332] @ (8006790 ) 8006642: e000 b.n 8006646 8006644: 4b53 ldr r3, [pc, #332] @ (8006794 ) 8006646: 4618 mov r0, r3 8006648: f7ff fd64 bl 8006114 800664c: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800664e: 68fb ldr r3, [r7, #12] 8006650: 681b ldr r3, [r3, #0] 8006652: 4618 mov r0, r3 8006654: f7ff fe1c bl 8006290 8006658: 4603 mov r3, r0 800665a: 2b00 cmp r3, #0 800665c: f040 808c bne.w 8006778 { /* Process locked */ __HAL_LOCK(hadc); 8006660: 68fb ldr r3, [r7, #12] 8006662: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8006666: 2b01 cmp r3, #1 8006668: d101 bne.n 800666e 800666a: 2302 movs r3, #2 800666c: e087 b.n 800677e 800666e: 68fb ldr r3, [r7, #12] 8006670: 2201 movs r2, #1 8006672: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006676: 693b ldr r3, [r7, #16] 8006678: 2b00 cmp r3, #0 800667a: d005 beq.n 8006688 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 800667c: 693b ldr r3, [r7, #16] 800667e: 2b05 cmp r3, #5 8006680: d002 beq.n 8006688 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 8006682: 693b ldr r3, [r7, #16] 8006684: 2b09 cmp r3, #9 8006686: d170 bne.n 800676a ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8006688: 68f8 ldr r0, [r7, #12] 800668a: f000 fbfd bl 8006e88 800668e: 4603 mov r3, r0 8006690: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 8006692: 7dfb ldrb r3, [r7, #23] 8006694: 2b00 cmp r3, #0 8006696: d163 bne.n 8006760 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 8006698: 68fb ldr r3, [r7, #12] 800669a: 6d5a ldr r2, [r3, #84] @ 0x54 800669c: 4b3e ldr r3, [pc, #248] @ (8006798 ) 800669e: 4013 ands r3, r2 80066a0: f443 7280 orr.w r2, r3, #256 @ 0x100 80066a4: 68fb ldr r3, [r7, #12] 80066a6: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 80066a8: 68fb ldr r3, [r7, #12] 80066aa: 681b ldr r3, [r3, #0] 80066ac: 4a37 ldr r2, [pc, #220] @ (800678c ) 80066ae: 4293 cmp r3, r2 80066b0: d002 beq.n 80066b8 80066b2: 68fb ldr r3, [r7, #12] 80066b4: 681b ldr r3, [r3, #0] 80066b6: e000 b.n 80066ba 80066b8: 4b33 ldr r3, [pc, #204] @ (8006788 ) 80066ba: 68fa ldr r2, [r7, #12] 80066bc: 6812 ldr r2, [r2, #0] 80066be: 4293 cmp r3, r2 80066c0: d002 beq.n 80066c8 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80066c2: 693b ldr r3, [r7, #16] 80066c4: 2b00 cmp r3, #0 80066c6: d105 bne.n 80066d4 ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 80066c8: 68fb ldr r3, [r7, #12] 80066ca: 6d5b ldr r3, [r3, #84] @ 0x54 80066cc: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 80066d0: 68fb ldr r3, [r7, #12] 80066d2: 655a str r2, [r3, #84] @ 0x54 } /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 80066d4: 68fb ldr r3, [r7, #12] 80066d6: 6d5b ldr r3, [r3, #84] @ 0x54 80066d8: f403 5380 and.w r3, r3, #4096 @ 0x1000 80066dc: 2b00 cmp r3, #0 80066de: d006 beq.n 80066ee { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 80066e0: 68fb ldr r3, [r7, #12] 80066e2: 6d9b ldr r3, [r3, #88] @ 0x58 80066e4: f023 0206 bic.w r2, r3, #6 80066e8: 68fb ldr r3, [r7, #12] 80066ea: 659a str r2, [r3, #88] @ 0x58 80066ec: e002 b.n 80066f4 } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 80066ee: 68fb ldr r3, [r7, #12] 80066f0: 2200 movs r2, #0 80066f2: 659a str r2, [r3, #88] @ 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 80066f4: 68fb ldr r3, [r7, #12] 80066f6: 6cdb ldr r3, [r3, #76] @ 0x4c 80066f8: 4a28 ldr r2, [pc, #160] @ (800679c ) 80066fa: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 80066fc: 68fb ldr r3, [r7, #12] 80066fe: 6cdb ldr r3, [r3, #76] @ 0x4c 8006700: 4a27 ldr r2, [pc, #156] @ (80067a0 ) 8006702: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 8006704: 68fb ldr r3, [r7, #12] 8006706: 6cdb ldr r3, [r3, #76] @ 0x4c 8006708: 4a26 ldr r2, [pc, #152] @ (80067a4 ) 800670a: 64da str r2, [r3, #76] @ 0x4c /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 800670c: 68fb ldr r3, [r7, #12] 800670e: 681b ldr r3, [r3, #0] 8006710: 221c movs r2, #28 8006712: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 8006714: 68fb ldr r3, [r7, #12] 8006716: 2200 movs r2, #0 8006718: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 800671c: 68fb ldr r3, [r7, #12] 800671e: 681b ldr r3, [r3, #0] 8006720: 685a ldr r2, [r3, #4] 8006722: 68fb ldr r3, [r7, #12] 8006724: 681b ldr r3, [r3, #0] 8006726: f042 0210 orr.w r2, r2, #16 800672a: 605a str r2, [r3, #4] { LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); 800672c: 68fb ldr r3, [r7, #12] 800672e: 681a ldr r2, [r3, #0] 8006730: 68fb ldr r3, [r7, #12] 8006732: 6adb ldr r3, [r3, #44] @ 0x2c 8006734: 4619 mov r1, r3 8006736: 4610 mov r0, r2 8006738: f7ff fc89 bl 800604e #endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 800673c: 68fb ldr r3, [r7, #12] 800673e: 6cd8 ldr r0, [r3, #76] @ 0x4c 8006740: 68fb ldr r3, [r7, #12] 8006742: 681b ldr r3, [r3, #0] 8006744: 3340 adds r3, #64 @ 0x40 8006746: 4619 mov r1, r3 8006748: 68ba ldr r2, [r7, #8] 800674a: 687b ldr r3, [r7, #4] 800674c: f002 fa5e bl 8008c0c 8006750: 4603 mov r3, r0 8006752: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 8006754: 68fb ldr r3, [r7, #12] 8006756: 681b ldr r3, [r3, #0] 8006758: 4618 mov r0, r3 800675a: f7ff fd85 bl 8006268 if (tmp_hal_status == HAL_OK) 800675e: e00d b.n 800677c } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8006760: 68fb ldr r3, [r7, #12] 8006762: 2200 movs r2, #0 8006764: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (tmp_hal_status == HAL_OK) 8006768: e008 b.n 800677c } } else { tmp_hal_status = HAL_ERROR; 800676a: 2301 movs r3, #1 800676c: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 800676e: 68fb ldr r3, [r7, #12] 8006770: 2200 movs r2, #0 8006772: f883 2050 strb.w r2, [r3, #80] @ 0x50 8006776: e001 b.n 800677c } } else { tmp_hal_status = HAL_BUSY; 8006778: 2302 movs r3, #2 800677a: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 800677c: 7dfb ldrb r3, [r7, #23] } 800677e: 4618 mov r0, r3 8006780: 3718 adds r7, #24 8006782: 46bd mov sp, r7 8006784: bd80 pop {r7, pc} 8006786: bf00 nop 8006788: 40022000 .word 0x40022000 800678c: 40022100 .word 0x40022100 8006790: 40022300 .word 0x40022300 8006794: 58026300 .word 0x58026300 8006798: fffff0fe .word 0xfffff0fe 800679c: 0800705b .word 0x0800705b 80067a0: 08007133 .word 0x08007133 80067a4: 0800714f .word 0x0800714f 080067a8 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 80067a8: b480 push {r7} 80067aa: b083 sub sp, #12 80067ac: af00 add r7, sp, #0 80067ae: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 80067b0: bf00 nop 80067b2: 370c adds r7, #12 80067b4: 46bd mov sp, r7 80067b6: f85d 7b04 ldr.w r7, [sp], #4 80067ba: 4770 bx lr 080067bc : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 80067bc: b480 push {r7} 80067be: b083 sub sp, #12 80067c0: af00 add r7, sp, #0 80067c2: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 80067c4: bf00 nop 80067c6: 370c adds r7, #12 80067c8: 46bd mov sp, r7 80067ca: f85d 7b04 ldr.w r7, [sp], #4 80067ce: 4770 bx lr 080067d0 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 80067d0: b590 push {r4, r7, lr} 80067d2: b0a1 sub sp, #132 @ 0x84 80067d4: af00 add r7, sp, #0 80067d6: 6078 str r0, [r7, #4] 80067d8: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80067da: 2300 movs r3, #0 80067dc: f887 307f strb.w r3, [r7, #127] @ 0x7f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 80067e0: 2300 movs r3, #0 80067e2: 60bb str r3, [r7, #8] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 80067e4: 683b ldr r3, [r7, #0] 80067e6: 68db ldr r3, [r3, #12] 80067e8: 4a65 ldr r2, [pc, #404] @ (8006980 ) 80067ea: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 80067ec: 687b ldr r3, [r7, #4] 80067ee: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80067f2: 2b01 cmp r3, #1 80067f4: d101 bne.n 80067fa 80067f6: 2302 movs r3, #2 80067f8: e32e b.n 8006e58 80067fa: 687b ldr r3, [r7, #4] 80067fc: 2201 movs r2, #1 80067fe: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8006802: 687b ldr r3, [r7, #4] 8006804: 681b ldr r3, [r3, #0] 8006806: 4618 mov r0, r3 8006808: f7ff fd42 bl 8006290 800680c: 4603 mov r3, r0 800680e: 2b00 cmp r3, #0 8006810: f040 8313 bne.w 8006e3a { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 8006814: 683b ldr r3, [r7, #0] 8006816: 681b ldr r3, [r3, #0] 8006818: 2b00 cmp r3, #0 800681a: db2c blt.n 8006876 /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 800681c: 683b ldr r3, [r7, #0] 800681e: 681b ldr r3, [r3, #0] 8006820: f3c3 0313 ubfx r3, r3, #0, #20 8006824: 2b00 cmp r3, #0 8006826: d108 bne.n 800683a 8006828: 683b ldr r3, [r7, #0] 800682a: 681b ldr r3, [r3, #0] 800682c: 0e9b lsrs r3, r3, #26 800682e: f003 031f and.w r3, r3, #31 8006832: 2201 movs r2, #1 8006834: fa02 f303 lsl.w r3, r2, r3 8006838: e016 b.n 8006868 800683a: 683b ldr r3, [r7, #0] 800683c: 681b ldr r3, [r3, #0] 800683e: 667b str r3, [r7, #100] @ 0x64 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006840: 6e7b ldr r3, [r7, #100] @ 0x64 8006842: fa93 f3a3 rbit r3, r3 8006846: 663b str r3, [r7, #96] @ 0x60 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8006848: 6e3b ldr r3, [r7, #96] @ 0x60 800684a: 66bb str r3, [r7, #104] @ 0x68 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 800684c: 6ebb ldr r3, [r7, #104] @ 0x68 800684e: 2b00 cmp r3, #0 8006850: d101 bne.n 8006856 { return 32U; 8006852: 2320 movs r3, #32 8006854: e003 b.n 800685e } return __builtin_clz(value); 8006856: 6ebb ldr r3, [r7, #104] @ 0x68 8006858: fab3 f383 clz r3, r3 800685c: b2db uxtb r3, r3 800685e: f003 031f and.w r3, r3, #31 8006862: 2201 movs r2, #1 8006864: fa02 f303 lsl.w r3, r2, r3 8006868: 687a ldr r2, [r7, #4] 800686a: 6812 ldr r2, [r2, #0] 800686c: 69d1 ldr r1, [r2, #28] 800686e: 687a ldr r2, [r7, #4] 8006870: 6812 ldr r2, [r2, #0] 8006872: 430b orrs r3, r1 8006874: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 8006876: 687b ldr r3, [r7, #4] 8006878: 6818 ldr r0, [r3, #0] 800687a: 683b ldr r3, [r7, #0] 800687c: 6859 ldr r1, [r3, #4] 800687e: 683b ldr r3, [r7, #0] 8006880: 681b ldr r3, [r3, #0] 8006882: 461a mov r2, r3 8006884: f7ff fbb7 bl 8005ff6 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006888: 687b ldr r3, [r7, #4] 800688a: 681b ldr r3, [r3, #0] 800688c: 4618 mov r0, r3 800688e: f7ff fcff bl 8006290 8006892: 67b8 str r0, [r7, #120] @ 0x78 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 8006894: 687b ldr r3, [r7, #4] 8006896: 681b ldr r3, [r3, #0] 8006898: 4618 mov r0, r3 800689a: f7ff fd0c bl 80062b6 800689e: 6778 str r0, [r7, #116] @ 0x74 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 80068a0: 6fbb ldr r3, [r7, #120] @ 0x78 80068a2: 2b00 cmp r3, #0 80068a4: f040 80b8 bne.w 8006a18 && (tmp_adc_is_conversion_on_going_injected == 0UL) 80068a8: 6f7b ldr r3, [r7, #116] @ 0x74 80068aa: 2b00 cmp r3, #0 80068ac: f040 80b4 bne.w 8006a18 ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 80068b0: 687b ldr r3, [r7, #4] 80068b2: 6818 ldr r0, [r3, #0] 80068b4: 683b ldr r3, [r7, #0] 80068b6: 6819 ldr r1, [r3, #0] 80068b8: 683b ldr r3, [r7, #0] 80068ba: 689b ldr r3, [r3, #8] 80068bc: 461a mov r2, r3 80068be: f7ff fbd9 bl 8006074 tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 80068c2: 4b30 ldr r3, [pc, #192] @ (8006984 ) 80068c4: 681b ldr r3, [r3, #0] 80068c6: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 80068ca: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80068ce: d10b bne.n 80068e8 80068d0: 683b ldr r3, [r7, #0] 80068d2: 695a ldr r2, [r3, #20] 80068d4: 687b ldr r3, [r7, #4] 80068d6: 681b ldr r3, [r3, #0] 80068d8: 68db ldr r3, [r3, #12] 80068da: 089b lsrs r3, r3, #2 80068dc: f003 0307 and.w r3, r3, #7 80068e0: 005b lsls r3, r3, #1 80068e2: fa02 f303 lsl.w r3, r2, r3 80068e6: e01d b.n 8006924 80068e8: 687b ldr r3, [r7, #4] 80068ea: 681b ldr r3, [r3, #0] 80068ec: 68db ldr r3, [r3, #12] 80068ee: f003 0310 and.w r3, r3, #16 80068f2: 2b00 cmp r3, #0 80068f4: d10b bne.n 800690e 80068f6: 683b ldr r3, [r7, #0] 80068f8: 695a ldr r2, [r3, #20] 80068fa: 687b ldr r3, [r7, #4] 80068fc: 681b ldr r3, [r3, #0] 80068fe: 68db ldr r3, [r3, #12] 8006900: 089b lsrs r3, r3, #2 8006902: f003 0307 and.w r3, r3, #7 8006906: 005b lsls r3, r3, #1 8006908: fa02 f303 lsl.w r3, r2, r3 800690c: e00a b.n 8006924 800690e: 683b ldr r3, [r7, #0] 8006910: 695a ldr r2, [r3, #20] 8006912: 687b ldr r3, [r7, #4] 8006914: 681b ldr r3, [r3, #0] 8006916: 68db ldr r3, [r3, #12] 8006918: 089b lsrs r3, r3, #2 800691a: f003 0304 and.w r3, r3, #4 800691e: 005b lsls r3, r3, #1 8006920: fa02 f303 lsl.w r3, r2, r3 8006924: 673b str r3, [r7, #112] @ 0x70 } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 8006926: 683b ldr r3, [r7, #0] 8006928: 691b ldr r3, [r3, #16] 800692a: 2b04 cmp r3, #4 800692c: d02c beq.n 8006988 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 800692e: 687b ldr r3, [r7, #4] 8006930: 6818 ldr r0, [r3, #0] 8006932: 683b ldr r3, [r7, #0] 8006934: 6919 ldr r1, [r3, #16] 8006936: 683b ldr r3, [r7, #0] 8006938: 681a ldr r2, [r3, #0] 800693a: 6f3b ldr r3, [r7, #112] @ 0x70 800693c: f7ff faf4 bl 8005f28 else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 8006940: 687b ldr r3, [r7, #4] 8006942: 6818 ldr r0, [r3, #0] 8006944: 683b ldr r3, [r7, #0] 8006946: 6919 ldr r1, [r3, #16] 8006948: 683b ldr r3, [r7, #0] 800694a: 7e5b ldrb r3, [r3, #25] 800694c: 2b01 cmp r3, #1 800694e: d102 bne.n 8006956 8006950: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 8006954: e000 b.n 8006958 8006956: 2300 movs r3, #0 8006958: 461a mov r2, r3 800695a: f7ff fb1e bl 8005f9a assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 800695e: 687b ldr r3, [r7, #4] 8006960: 6818 ldr r0, [r3, #0] 8006962: 683b ldr r3, [r7, #0] 8006964: 6919 ldr r1, [r3, #16] 8006966: 683b ldr r3, [r7, #0] 8006968: 7e1b ldrb r3, [r3, #24] 800696a: 2b01 cmp r3, #1 800696c: d102 bne.n 8006974 800696e: f44f 6300 mov.w r3, #2048 @ 0x800 8006972: e000 b.n 8006976 8006974: 2300 movs r3, #0 8006976: 461a mov r2, r3 8006978: f7ff faf6 bl 8005f68 800697c: e04c b.n 8006a18 800697e: bf00 nop 8006980: 47ff0000 .word 0x47ff0000 8006984: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006988: 687b ldr r3, [r7, #4] 800698a: 681b ldr r3, [r3, #0] 800698c: 6e1b ldr r3, [r3, #96] @ 0x60 800698e: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006992: 683b ldr r3, [r7, #0] 8006994: 681b ldr r3, [r3, #0] 8006996: 069b lsls r3, r3, #26 8006998: 429a cmp r2, r3 800699a: d107 bne.n 80069ac { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 800699c: 687b ldr r3, [r7, #4] 800699e: 681b ldr r3, [r3, #0] 80069a0: 6e1a ldr r2, [r3, #96] @ 0x60 80069a2: 687b ldr r3, [r7, #4] 80069a4: 681b ldr r3, [r3, #0] 80069a6: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069aa: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80069ac: 687b ldr r3, [r7, #4] 80069ae: 681b ldr r3, [r3, #0] 80069b0: 6e5b ldr r3, [r3, #100] @ 0x64 80069b2: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80069b6: 683b ldr r3, [r7, #0] 80069b8: 681b ldr r3, [r3, #0] 80069ba: 069b lsls r3, r3, #26 80069bc: 429a cmp r2, r3 80069be: d107 bne.n 80069d0 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 80069c0: 687b ldr r3, [r7, #4] 80069c2: 681b ldr r3, [r3, #0] 80069c4: 6e5a ldr r2, [r3, #100] @ 0x64 80069c6: 687b ldr r3, [r7, #4] 80069c8: 681b ldr r3, [r3, #0] 80069ca: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069ce: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80069d0: 687b ldr r3, [r7, #4] 80069d2: 681b ldr r3, [r3, #0] 80069d4: 6e9b ldr r3, [r3, #104] @ 0x68 80069d6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80069da: 683b ldr r3, [r7, #0] 80069dc: 681b ldr r3, [r3, #0] 80069de: 069b lsls r3, r3, #26 80069e0: 429a cmp r2, r3 80069e2: d107 bne.n 80069f4 { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 80069e4: 687b ldr r3, [r7, #4] 80069e6: 681b ldr r3, [r3, #0] 80069e8: 6e9a ldr r2, [r3, #104] @ 0x68 80069ea: 687b ldr r3, [r7, #4] 80069ec: 681b ldr r3, [r3, #0] 80069ee: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069f2: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80069f4: 687b ldr r3, [r7, #4] 80069f6: 681b ldr r3, [r3, #0] 80069f8: 6edb ldr r3, [r3, #108] @ 0x6c 80069fa: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80069fe: 683b ldr r3, [r7, #0] 8006a00: 681b ldr r3, [r3, #0] 8006a02: 069b lsls r3, r3, #26 8006a04: 429a cmp r2, r3 8006a06: d107 bne.n 8006a18 { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8006a08: 687b ldr r3, [r7, #4] 8006a0a: 681b ldr r3, [r3, #0] 8006a0c: 6eda ldr r2, [r3, #108] @ 0x6c 8006a0e: 687b ldr r3, [r7, #4] 8006a10: 681b ldr r3, [r3, #0] 8006a12: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006a16: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006a18: 687b ldr r3, [r7, #4] 8006a1a: 681b ldr r3, [r3, #0] 8006a1c: 4618 mov r0, r3 8006a1e: f7ff fbfd bl 800621c 8006a22: 4603 mov r3, r0 8006a24: 2b00 cmp r3, #0 8006a26: f040 8211 bne.w 8006e4c { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 8006a2a: 687b ldr r3, [r7, #4] 8006a2c: 6818 ldr r0, [r3, #0] 8006a2e: 683b ldr r3, [r7, #0] 8006a30: 6819 ldr r1, [r3, #0] 8006a32: 683b ldr r3, [r7, #0] 8006a34: 68db ldr r3, [r3, #12] 8006a36: 461a mov r2, r3 8006a38: f7ff fb48 bl 80060cc /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 8006a3c: 683b ldr r3, [r7, #0] 8006a3e: 68db ldr r3, [r3, #12] 8006a40: 4aa1 ldr r2, [pc, #644] @ (8006cc8 ) 8006a42: 4293 cmp r3, r2 8006a44: f040 812e bne.w 8006ca4 { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006a48: 687b ldr r3, [r7, #4] 8006a4a: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006a4c: 683b ldr r3, [r7, #0] 8006a4e: 681b ldr r3, [r3, #0] 8006a50: f3c3 0313 ubfx r3, r3, #0, #20 8006a54: 2b00 cmp r3, #0 8006a56: d10b bne.n 8006a70 8006a58: 683b ldr r3, [r7, #0] 8006a5a: 681b ldr r3, [r3, #0] 8006a5c: 0e9b lsrs r3, r3, #26 8006a5e: 3301 adds r3, #1 8006a60: f003 031f and.w r3, r3, #31 8006a64: 2b09 cmp r3, #9 8006a66: bf94 ite ls 8006a68: 2301 movls r3, #1 8006a6a: 2300 movhi r3, #0 8006a6c: b2db uxtb r3, r3 8006a6e: e019 b.n 8006aa4 8006a70: 683b ldr r3, [r7, #0] 8006a72: 681b ldr r3, [r3, #0] 8006a74: 65bb str r3, [r7, #88] @ 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006a76: 6dbb ldr r3, [r7, #88] @ 0x58 8006a78: fa93 f3a3 rbit r3, r3 8006a7c: 657b str r3, [r7, #84] @ 0x54 return result; 8006a7e: 6d7b ldr r3, [r7, #84] @ 0x54 8006a80: 65fb str r3, [r7, #92] @ 0x5c if (value == 0U) 8006a82: 6dfb ldr r3, [r7, #92] @ 0x5c 8006a84: 2b00 cmp r3, #0 8006a86: d101 bne.n 8006a8c return 32U; 8006a88: 2320 movs r3, #32 8006a8a: e003 b.n 8006a94 return __builtin_clz(value); 8006a8c: 6dfb ldr r3, [r7, #92] @ 0x5c 8006a8e: fab3 f383 clz r3, r3 8006a92: b2db uxtb r3, r3 8006a94: 3301 adds r3, #1 8006a96: f003 031f and.w r3, r3, #31 8006a9a: 2b09 cmp r3, #9 8006a9c: bf94 ite ls 8006a9e: 2301 movls r3, #1 8006aa0: 2300 movhi r3, #0 8006aa2: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006aa4: 2b00 cmp r3, #0 8006aa6: d079 beq.n 8006b9c (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006aa8: 683b ldr r3, [r7, #0] 8006aaa: 681b ldr r3, [r3, #0] 8006aac: f3c3 0313 ubfx r3, r3, #0, #20 8006ab0: 2b00 cmp r3, #0 8006ab2: d107 bne.n 8006ac4 8006ab4: 683b ldr r3, [r7, #0] 8006ab6: 681b ldr r3, [r3, #0] 8006ab8: 0e9b lsrs r3, r3, #26 8006aba: 3301 adds r3, #1 8006abc: 069b lsls r3, r3, #26 8006abe: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006ac2: e015 b.n 8006af0 8006ac4: 683b ldr r3, [r7, #0] 8006ac6: 681b ldr r3, [r3, #0] 8006ac8: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006aca: 6cfb ldr r3, [r7, #76] @ 0x4c 8006acc: fa93 f3a3 rbit r3, r3 8006ad0: 64bb str r3, [r7, #72] @ 0x48 return result; 8006ad2: 6cbb ldr r3, [r7, #72] @ 0x48 8006ad4: 653b str r3, [r7, #80] @ 0x50 if (value == 0U) 8006ad6: 6d3b ldr r3, [r7, #80] @ 0x50 8006ad8: 2b00 cmp r3, #0 8006ada: d101 bne.n 8006ae0 return 32U; 8006adc: 2320 movs r3, #32 8006ade: e003 b.n 8006ae8 return __builtin_clz(value); 8006ae0: 6d3b ldr r3, [r7, #80] @ 0x50 8006ae2: fab3 f383 clz r3, r3 8006ae6: b2db uxtb r3, r3 8006ae8: 3301 adds r3, #1 8006aea: 069b lsls r3, r3, #26 8006aec: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006af0: 683b ldr r3, [r7, #0] 8006af2: 681b ldr r3, [r3, #0] 8006af4: f3c3 0313 ubfx r3, r3, #0, #20 8006af8: 2b00 cmp r3, #0 8006afa: d109 bne.n 8006b10 8006afc: 683b ldr r3, [r7, #0] 8006afe: 681b ldr r3, [r3, #0] 8006b00: 0e9b lsrs r3, r3, #26 8006b02: 3301 adds r3, #1 8006b04: f003 031f and.w r3, r3, #31 8006b08: 2101 movs r1, #1 8006b0a: fa01 f303 lsl.w r3, r1, r3 8006b0e: e017 b.n 8006b40 8006b10: 683b ldr r3, [r7, #0] 8006b12: 681b ldr r3, [r3, #0] 8006b14: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006b16: 6c3b ldr r3, [r7, #64] @ 0x40 8006b18: fa93 f3a3 rbit r3, r3 8006b1c: 63fb str r3, [r7, #60] @ 0x3c return result; 8006b1e: 6bfb ldr r3, [r7, #60] @ 0x3c 8006b20: 647b str r3, [r7, #68] @ 0x44 if (value == 0U) 8006b22: 6c7b ldr r3, [r7, #68] @ 0x44 8006b24: 2b00 cmp r3, #0 8006b26: d101 bne.n 8006b2c return 32U; 8006b28: 2320 movs r3, #32 8006b2a: e003 b.n 8006b34 return __builtin_clz(value); 8006b2c: 6c7b ldr r3, [r7, #68] @ 0x44 8006b2e: fab3 f383 clz r3, r3 8006b32: b2db uxtb r3, r3 8006b34: 3301 adds r3, #1 8006b36: f003 031f and.w r3, r3, #31 8006b3a: 2101 movs r1, #1 8006b3c: fa01 f303 lsl.w r3, r1, r3 8006b40: ea42 0103 orr.w r1, r2, r3 8006b44: 683b ldr r3, [r7, #0] 8006b46: 681b ldr r3, [r3, #0] 8006b48: f3c3 0313 ubfx r3, r3, #0, #20 8006b4c: 2b00 cmp r3, #0 8006b4e: d10a bne.n 8006b66 8006b50: 683b ldr r3, [r7, #0] 8006b52: 681b ldr r3, [r3, #0] 8006b54: 0e9b lsrs r3, r3, #26 8006b56: 3301 adds r3, #1 8006b58: f003 021f and.w r2, r3, #31 8006b5c: 4613 mov r3, r2 8006b5e: 005b lsls r3, r3, #1 8006b60: 4413 add r3, r2 8006b62: 051b lsls r3, r3, #20 8006b64: e018 b.n 8006b98 8006b66: 683b ldr r3, [r7, #0] 8006b68: 681b ldr r3, [r3, #0] 8006b6a: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006b6c: 6b7b ldr r3, [r7, #52] @ 0x34 8006b6e: fa93 f3a3 rbit r3, r3 8006b72: 633b str r3, [r7, #48] @ 0x30 return result; 8006b74: 6b3b ldr r3, [r7, #48] @ 0x30 8006b76: 63bb str r3, [r7, #56] @ 0x38 if (value == 0U) 8006b78: 6bbb ldr r3, [r7, #56] @ 0x38 8006b7a: 2b00 cmp r3, #0 8006b7c: d101 bne.n 8006b82 return 32U; 8006b7e: 2320 movs r3, #32 8006b80: e003 b.n 8006b8a return __builtin_clz(value); 8006b82: 6bbb ldr r3, [r7, #56] @ 0x38 8006b84: fab3 f383 clz r3, r3 8006b88: b2db uxtb r3, r3 8006b8a: 3301 adds r3, #1 8006b8c: f003 021f and.w r2, r3, #31 8006b90: 4613 mov r3, r2 8006b92: 005b lsls r3, r3, #1 8006b94: 4413 add r3, r2 8006b96: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006b98: 430b orrs r3, r1 8006b9a: e07e b.n 8006c9a (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006b9c: 683b ldr r3, [r7, #0] 8006b9e: 681b ldr r3, [r3, #0] 8006ba0: f3c3 0313 ubfx r3, r3, #0, #20 8006ba4: 2b00 cmp r3, #0 8006ba6: d107 bne.n 8006bb8 8006ba8: 683b ldr r3, [r7, #0] 8006baa: 681b ldr r3, [r3, #0] 8006bac: 0e9b lsrs r3, r3, #26 8006bae: 3301 adds r3, #1 8006bb0: 069b lsls r3, r3, #26 8006bb2: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006bb6: e015 b.n 8006be4 8006bb8: 683b ldr r3, [r7, #0] 8006bba: 681b ldr r3, [r3, #0] 8006bbc: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006bbe: 6abb ldr r3, [r7, #40] @ 0x28 8006bc0: fa93 f3a3 rbit r3, r3 8006bc4: 627b str r3, [r7, #36] @ 0x24 return result; 8006bc6: 6a7b ldr r3, [r7, #36] @ 0x24 8006bc8: 62fb str r3, [r7, #44] @ 0x2c if (value == 0U) 8006bca: 6afb ldr r3, [r7, #44] @ 0x2c 8006bcc: 2b00 cmp r3, #0 8006bce: d101 bne.n 8006bd4 return 32U; 8006bd0: 2320 movs r3, #32 8006bd2: e003 b.n 8006bdc return __builtin_clz(value); 8006bd4: 6afb ldr r3, [r7, #44] @ 0x2c 8006bd6: fab3 f383 clz r3, r3 8006bda: b2db uxtb r3, r3 8006bdc: 3301 adds r3, #1 8006bde: 069b lsls r3, r3, #26 8006be0: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006be4: 683b ldr r3, [r7, #0] 8006be6: 681b ldr r3, [r3, #0] 8006be8: f3c3 0313 ubfx r3, r3, #0, #20 8006bec: 2b00 cmp r3, #0 8006bee: d109 bne.n 8006c04 8006bf0: 683b ldr r3, [r7, #0] 8006bf2: 681b ldr r3, [r3, #0] 8006bf4: 0e9b lsrs r3, r3, #26 8006bf6: 3301 adds r3, #1 8006bf8: f003 031f and.w r3, r3, #31 8006bfc: 2101 movs r1, #1 8006bfe: fa01 f303 lsl.w r3, r1, r3 8006c02: e017 b.n 8006c34 8006c04: 683b ldr r3, [r7, #0] 8006c06: 681b ldr r3, [r3, #0] 8006c08: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006c0a: 69fb ldr r3, [r7, #28] 8006c0c: fa93 f3a3 rbit r3, r3 8006c10: 61bb str r3, [r7, #24] return result; 8006c12: 69bb ldr r3, [r7, #24] 8006c14: 623b str r3, [r7, #32] if (value == 0U) 8006c16: 6a3b ldr r3, [r7, #32] 8006c18: 2b00 cmp r3, #0 8006c1a: d101 bne.n 8006c20 return 32U; 8006c1c: 2320 movs r3, #32 8006c1e: e003 b.n 8006c28 return __builtin_clz(value); 8006c20: 6a3b ldr r3, [r7, #32] 8006c22: fab3 f383 clz r3, r3 8006c26: b2db uxtb r3, r3 8006c28: 3301 adds r3, #1 8006c2a: f003 031f and.w r3, r3, #31 8006c2e: 2101 movs r1, #1 8006c30: fa01 f303 lsl.w r3, r1, r3 8006c34: ea42 0103 orr.w r1, r2, r3 8006c38: 683b ldr r3, [r7, #0] 8006c3a: 681b ldr r3, [r3, #0] 8006c3c: f3c3 0313 ubfx r3, r3, #0, #20 8006c40: 2b00 cmp r3, #0 8006c42: d10d bne.n 8006c60 8006c44: 683b ldr r3, [r7, #0] 8006c46: 681b ldr r3, [r3, #0] 8006c48: 0e9b lsrs r3, r3, #26 8006c4a: 3301 adds r3, #1 8006c4c: f003 021f and.w r2, r3, #31 8006c50: 4613 mov r3, r2 8006c52: 005b lsls r3, r3, #1 8006c54: 4413 add r3, r2 8006c56: 3b1e subs r3, #30 8006c58: 051b lsls r3, r3, #20 8006c5a: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8006c5e: e01b b.n 8006c98 8006c60: 683b ldr r3, [r7, #0] 8006c62: 681b ldr r3, [r3, #0] 8006c64: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006c66: 693b ldr r3, [r7, #16] 8006c68: fa93 f3a3 rbit r3, r3 8006c6c: 60fb str r3, [r7, #12] return result; 8006c6e: 68fb ldr r3, [r7, #12] 8006c70: 617b str r3, [r7, #20] if (value == 0U) 8006c72: 697b ldr r3, [r7, #20] 8006c74: 2b00 cmp r3, #0 8006c76: d101 bne.n 8006c7c return 32U; 8006c78: 2320 movs r3, #32 8006c7a: e003 b.n 8006c84 return __builtin_clz(value); 8006c7c: 697b ldr r3, [r7, #20] 8006c7e: fab3 f383 clz r3, r3 8006c82: b2db uxtb r3, r3 8006c84: 3301 adds r3, #1 8006c86: f003 021f and.w r2, r3, #31 8006c8a: 4613 mov r3, r2 8006c8c: 005b lsls r3, r3, #1 8006c8e: 4413 add r3, r2 8006c90: 3b1e subs r3, #30 8006c92: 051b lsls r3, r3, #20 8006c94: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006c98: 430b orrs r3, r1 8006c9a: 683a ldr r2, [r7, #0] 8006c9c: 6892 ldr r2, [r2, #8] 8006c9e: 4619 mov r1, r3 8006ca0: f7ff f9e8 bl 8006074 /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8006ca4: 683b ldr r3, [r7, #0] 8006ca6: 681b ldr r3, [r3, #0] 8006ca8: 2b00 cmp r3, #0 8006caa: f280 80cf bge.w 8006e4c { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006cae: 687b ldr r3, [r7, #4] 8006cb0: 681b ldr r3, [r3, #0] 8006cb2: 4a06 ldr r2, [pc, #24] @ (8006ccc ) 8006cb4: 4293 cmp r3, r2 8006cb6: d004 beq.n 8006cc2 8006cb8: 687b ldr r3, [r7, #4] 8006cba: 681b ldr r3, [r3, #0] 8006cbc: 4a04 ldr r2, [pc, #16] @ (8006cd0 ) 8006cbe: 4293 cmp r3, r2 8006cc0: d10a bne.n 8006cd8 8006cc2: 4b04 ldr r3, [pc, #16] @ (8006cd4 ) 8006cc4: e009 b.n 8006cda 8006cc6: bf00 nop 8006cc8: 47ff0000 .word 0x47ff0000 8006ccc: 40022000 .word 0x40022000 8006cd0: 40022100 .word 0x40022100 8006cd4: 40022300 .word 0x40022300 8006cd8: 4b61 ldr r3, [pc, #388] @ (8006e60 ) 8006cda: 4618 mov r0, r3 8006cdc: f7ff f916 bl 8005f0c 8006ce0: 66f8 str r0, [r7, #108] @ 0x6c /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006ce2: 687b ldr r3, [r7, #4] 8006ce4: 681b ldr r3, [r3, #0] 8006ce6: 4a5f ldr r2, [pc, #380] @ (8006e64 ) 8006ce8: 4293 cmp r3, r2 8006cea: d004 beq.n 8006cf6 8006cec: 687b ldr r3, [r7, #4] 8006cee: 681b ldr r3, [r3, #0] 8006cf0: 4a5d ldr r2, [pc, #372] @ (8006e68 ) 8006cf2: 4293 cmp r3, r2 8006cf4: d10e bne.n 8006d14 8006cf6: 485b ldr r0, [pc, #364] @ (8006e64 ) 8006cf8: f7ff fa90 bl 800621c 8006cfc: 4604 mov r4, r0 8006cfe: 485a ldr r0, [pc, #360] @ (8006e68 ) 8006d00: f7ff fa8c bl 800621c 8006d04: 4603 mov r3, r0 8006d06: 4323 orrs r3, r4 8006d08: 2b00 cmp r3, #0 8006d0a: bf0c ite eq 8006d0c: 2301 moveq r3, #1 8006d0e: 2300 movne r3, #0 8006d10: b2db uxtb r3, r3 8006d12: e008 b.n 8006d26 8006d14: 4855 ldr r0, [pc, #340] @ (8006e6c ) 8006d16: f7ff fa81 bl 800621c 8006d1a: 4603 mov r3, r0 8006d1c: 2b00 cmp r3, #0 8006d1e: bf0c ite eq 8006d20: 2301 moveq r3, #1 8006d22: 2300 movne r3, #0 8006d24: b2db uxtb r3, r3 8006d26: 2b00 cmp r3, #0 8006d28: d07d beq.n 8006e26 { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8006d2a: 683b ldr r3, [r7, #0] 8006d2c: 681b ldr r3, [r3, #0] 8006d2e: 4a50 ldr r2, [pc, #320] @ (8006e70 ) 8006d30: 4293 cmp r3, r2 8006d32: d130 bne.n 8006d96 8006d34: 6efb ldr r3, [r7, #108] @ 0x6c 8006d36: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006d3a: 2b00 cmp r3, #0 8006d3c: d12b bne.n 8006d96 { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006d3e: 687b ldr r3, [r7, #4] 8006d40: 681b ldr r3, [r3, #0] 8006d42: 4a4a ldr r2, [pc, #296] @ (8006e6c ) 8006d44: 4293 cmp r3, r2 8006d46: f040 8081 bne.w 8006e4c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 8006d4a: 687b ldr r3, [r7, #4] 8006d4c: 681b ldr r3, [r3, #0] 8006d4e: 4a45 ldr r2, [pc, #276] @ (8006e64 ) 8006d50: 4293 cmp r3, r2 8006d52: d004 beq.n 8006d5e 8006d54: 687b ldr r3, [r7, #4] 8006d56: 681b ldr r3, [r3, #0] 8006d58: 4a43 ldr r2, [pc, #268] @ (8006e68 ) 8006d5a: 4293 cmp r3, r2 8006d5c: d101 bne.n 8006d62 8006d5e: 4a45 ldr r2, [pc, #276] @ (8006e74 ) 8006d60: e000 b.n 8006d64 8006d62: 4a3f ldr r2, [pc, #252] @ (8006e60 ) 8006d64: 6efb ldr r3, [r7, #108] @ 0x6c 8006d66: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8006d6a: 4619 mov r1, r3 8006d6c: 4610 mov r0, r2 8006d6e: f7ff f8ba bl 8005ee6 /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006d72: 4b41 ldr r3, [pc, #260] @ (8006e78 ) 8006d74: 681b ldr r3, [r3, #0] 8006d76: 099b lsrs r3, r3, #6 8006d78: 4a40 ldr r2, [pc, #256] @ (8006e7c ) 8006d7a: fba2 2303 umull r2, r3, r2, r3 8006d7e: 099b lsrs r3, r3, #6 8006d80: 3301 adds r3, #1 8006d82: 005b lsls r3, r3, #1 8006d84: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006d86: e002 b.n 8006d8e { wait_loop_index--; 8006d88: 68bb ldr r3, [r7, #8] 8006d8a: 3b01 subs r3, #1 8006d8c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006d8e: 68bb ldr r3, [r7, #8] 8006d90: 2b00 cmp r3, #0 8006d92: d1f9 bne.n 8006d88 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006d94: e05a b.n 8006e4c } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8006d96: 683b ldr r3, [r7, #0] 8006d98: 681b ldr r3, [r3, #0] 8006d9a: 4a39 ldr r2, [pc, #228] @ (8006e80 ) 8006d9c: 4293 cmp r3, r2 8006d9e: d11e bne.n 8006dde 8006da0: 6efb ldr r3, [r7, #108] @ 0x6c 8006da2: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8006da6: 2b00 cmp r3, #0 8006da8: d119 bne.n 8006dde { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006daa: 687b ldr r3, [r7, #4] 8006dac: 681b ldr r3, [r3, #0] 8006dae: 4a2f ldr r2, [pc, #188] @ (8006e6c ) 8006db0: 4293 cmp r3, r2 8006db2: d14b bne.n 8006e4c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8006db4: 687b ldr r3, [r7, #4] 8006db6: 681b ldr r3, [r3, #0] 8006db8: 4a2a ldr r2, [pc, #168] @ (8006e64 ) 8006dba: 4293 cmp r3, r2 8006dbc: d004 beq.n 8006dc8 8006dbe: 687b ldr r3, [r7, #4] 8006dc0: 681b ldr r3, [r3, #0] 8006dc2: 4a29 ldr r2, [pc, #164] @ (8006e68 ) 8006dc4: 4293 cmp r3, r2 8006dc6: d101 bne.n 8006dcc 8006dc8: 4a2a ldr r2, [pc, #168] @ (8006e74 ) 8006dca: e000 b.n 8006dce 8006dcc: 4a24 ldr r2, [pc, #144] @ (8006e60 ) 8006dce: 6efb ldr r3, [r7, #108] @ 0x6c 8006dd0: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8006dd4: 4619 mov r1, r3 8006dd6: 4610 mov r0, r2 8006dd8: f7ff f885 bl 8005ee6 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006ddc: e036 b.n 8006e4c } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8006dde: 683b ldr r3, [r7, #0] 8006de0: 681b ldr r3, [r3, #0] 8006de2: 4a28 ldr r2, [pc, #160] @ (8006e84 ) 8006de4: 4293 cmp r3, r2 8006de6: d131 bne.n 8006e4c 8006de8: 6efb ldr r3, [r7, #108] @ 0x6c 8006dea: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8006dee: 2b00 cmp r3, #0 8006df0: d12c bne.n 8006e4c { if (ADC_VREFINT_INSTANCE(hadc)) 8006df2: 687b ldr r3, [r7, #4] 8006df4: 681b ldr r3, [r3, #0] 8006df6: 4a1d ldr r2, [pc, #116] @ (8006e6c ) 8006df8: 4293 cmp r3, r2 8006dfa: d127 bne.n 8006e4c { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 8006dfc: 687b ldr r3, [r7, #4] 8006dfe: 681b ldr r3, [r3, #0] 8006e00: 4a18 ldr r2, [pc, #96] @ (8006e64 ) 8006e02: 4293 cmp r3, r2 8006e04: d004 beq.n 8006e10 8006e06: 687b ldr r3, [r7, #4] 8006e08: 681b ldr r3, [r3, #0] 8006e0a: 4a17 ldr r2, [pc, #92] @ (8006e68 ) 8006e0c: 4293 cmp r3, r2 8006e0e: d101 bne.n 8006e14 8006e10: 4a18 ldr r2, [pc, #96] @ (8006e74 ) 8006e12: e000 b.n 8006e16 8006e14: 4a12 ldr r2, [pc, #72] @ (8006e60 ) 8006e16: 6efb ldr r3, [r7, #108] @ 0x6c 8006e18: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8006e1c: 4619 mov r1, r3 8006e1e: 4610 mov r0, r2 8006e20: f7ff f861 bl 8005ee6 8006e24: e012 b.n 8006e4c /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006e26: 687b ldr r3, [r7, #4] 8006e28: 6d5b ldr r3, [r3, #84] @ 0x54 8006e2a: f043 0220 orr.w r2, r3, #32 8006e2e: 687b ldr r3, [r7, #4] 8006e30: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006e32: 2301 movs r3, #1 8006e34: f887 307f strb.w r3, [r7, #127] @ 0x7f 8006e38: e008 b.n 8006e4c /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006e3a: 687b ldr r3, [r7, #4] 8006e3c: 6d5b ldr r3, [r3, #84] @ 0x54 8006e3e: f043 0220 orr.w r2, r3, #32 8006e42: 687b ldr r3, [r7, #4] 8006e44: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006e46: 2301 movs r3, #1 8006e48: f887 307f strb.w r3, [r7, #127] @ 0x7f } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006e4c: 687b ldr r3, [r7, #4] 8006e4e: 2200 movs r2, #0 8006e50: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006e54: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8006e58: 4618 mov r0, r3 8006e5a: 3784 adds r7, #132 @ 0x84 8006e5c: 46bd mov sp, r7 8006e5e: bd90 pop {r4, r7, pc} 8006e60: 58026300 .word 0x58026300 8006e64: 40022000 .word 0x40022000 8006e68: 40022100 .word 0x40022100 8006e6c: 58026000 .word 0x58026000 8006e70: cb840000 .word 0xcb840000 8006e74: 40022300 .word 0x40022300 8006e78: 24000034 .word 0x24000034 8006e7c: 053e2d63 .word 0x053e2d63 8006e80: c7520000 .word 0xc7520000 8006e84: cfb80000 .word 0xcfb80000 08006e88 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8006e88: b580 push {r7, lr} 8006e8a: b084 sub sp, #16 8006e8c: af00 add r7, sp, #0 8006e8e: 6078 str r0, [r7, #4] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006e90: 687b ldr r3, [r7, #4] 8006e92: 681b ldr r3, [r3, #0] 8006e94: 4618 mov r0, r3 8006e96: f7ff f9c1 bl 800621c 8006e9a: 4603 mov r3, r0 8006e9c: 2b00 cmp r3, #0 8006e9e: d16e bne.n 8006f7e { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8006ea0: 687b ldr r3, [r7, #4] 8006ea2: 681b ldr r3, [r3, #0] 8006ea4: 689a ldr r2, [r3, #8] 8006ea6: 4b38 ldr r3, [pc, #224] @ (8006f88 ) 8006ea8: 4013 ands r3, r2 8006eaa: 2b00 cmp r3, #0 8006eac: d00d beq.n 8006eca { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006eae: 687b ldr r3, [r7, #4] 8006eb0: 6d5b ldr r3, [r3, #84] @ 0x54 8006eb2: f043 0210 orr.w r2, r3, #16 8006eb6: 687b ldr r3, [r7, #4] 8006eb8: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006eba: 687b ldr r3, [r7, #4] 8006ebc: 6d9b ldr r3, [r3, #88] @ 0x58 8006ebe: f043 0201 orr.w r2, r3, #1 8006ec2: 687b ldr r3, [r7, #4] 8006ec4: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006ec6: 2301 movs r3, #1 8006ec8: e05a b.n 8006f80 } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 8006eca: 687b ldr r3, [r7, #4] 8006ecc: 681b ldr r3, [r3, #0] 8006ece: 4618 mov r0, r3 8006ed0: f7ff f97c bl 80061cc /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 8006ed4: f7fe ffa2 bl 8005e1c 8006ed8: 60f8 str r0, [r7, #12] /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006eda: 687b ldr r3, [r7, #4] 8006edc: 681b ldr r3, [r3, #0] 8006ede: 4a2b ldr r2, [pc, #172] @ (8006f8c ) 8006ee0: 4293 cmp r3, r2 8006ee2: d004 beq.n 8006eee 8006ee4: 687b ldr r3, [r7, #4] 8006ee6: 681b ldr r3, [r3, #0] 8006ee8: 4a29 ldr r2, [pc, #164] @ (8006f90 ) 8006eea: 4293 cmp r3, r2 8006eec: d101 bne.n 8006ef2 8006eee: 4b29 ldr r3, [pc, #164] @ (8006f94 ) 8006ef0: e000 b.n 8006ef4 8006ef2: 4b29 ldr r3, [pc, #164] @ (8006f98 ) 8006ef4: 4618 mov r0, r3 8006ef6: f7ff f90d bl 8006114 8006efa: 60b8 str r0, [r7, #8] if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8006efc: 687b ldr r3, [r7, #4] 8006efe: 681b ldr r3, [r3, #0] 8006f00: 4a23 ldr r2, [pc, #140] @ (8006f90 ) 8006f02: 4293 cmp r3, r2 8006f04: d002 beq.n 8006f0c 8006f06: 687b ldr r3, [r7, #4] 8006f08: 681b ldr r3, [r3, #0] 8006f0a: e000 b.n 8006f0e 8006f0c: 4b1f ldr r3, [pc, #124] @ (8006f8c ) 8006f0e: 687a ldr r2, [r7, #4] 8006f10: 6812 ldr r2, [r2, #0] 8006f12: 4293 cmp r3, r2 8006f14: d02c beq.n 8006f70 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006f16: 68bb ldr r3, [r7, #8] 8006f18: 2b00 cmp r3, #0 8006f1a: d130 bne.n 8006f7e ) { while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006f1c: e028 b.n 8006f70 The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006f1e: 687b ldr r3, [r7, #4] 8006f20: 681b ldr r3, [r3, #0] 8006f22: 4618 mov r0, r3 8006f24: f7ff f97a bl 800621c 8006f28: 4603 mov r3, r0 8006f2a: 2b00 cmp r3, #0 8006f2c: d104 bne.n 8006f38 { LL_ADC_Enable(hadc->Instance); 8006f2e: 687b ldr r3, [r7, #4] 8006f30: 681b ldr r3, [r3, #0] 8006f32: 4618 mov r0, r3 8006f34: f7ff f94a bl 80061cc } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8006f38: f7fe ff70 bl 8005e1c 8006f3c: 4602 mov r2, r0 8006f3e: 68fb ldr r3, [r7, #12] 8006f40: 1ad3 subs r3, r2, r3 8006f42: 2b02 cmp r3, #2 8006f44: d914 bls.n 8006f70 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006f46: 687b ldr r3, [r7, #4] 8006f48: 681b ldr r3, [r3, #0] 8006f4a: 681b ldr r3, [r3, #0] 8006f4c: f003 0301 and.w r3, r3, #1 8006f50: 2b01 cmp r3, #1 8006f52: d00d beq.n 8006f70 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006f54: 687b ldr r3, [r7, #4] 8006f56: 6d5b ldr r3, [r3, #84] @ 0x54 8006f58: f043 0210 orr.w r2, r3, #16 8006f5c: 687b ldr r3, [r7, #4] 8006f5e: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006f60: 687b ldr r3, [r7, #4] 8006f62: 6d9b ldr r3, [r3, #88] @ 0x58 8006f64: f043 0201 orr.w r2, r3, #1 8006f68: 687b ldr r3, [r7, #4] 8006f6a: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006f6c: 2301 movs r3, #1 8006f6e: e007 b.n 8006f80 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006f70: 687b ldr r3, [r7, #4] 8006f72: 681b ldr r3, [r3, #0] 8006f74: 681b ldr r3, [r3, #0] 8006f76: f003 0301 and.w r3, r3, #1 8006f7a: 2b01 cmp r3, #1 8006f7c: d1cf bne.n 8006f1e } } } /* Return HAL status */ return HAL_OK; 8006f7e: 2300 movs r3, #0 } 8006f80: 4618 mov r0, r3 8006f82: 3710 adds r7, #16 8006f84: 46bd mov sp, r7 8006f86: bd80 pop {r7, pc} 8006f88: 8000003f .word 0x8000003f 8006f8c: 40022000 .word 0x40022000 8006f90: 40022100 .word 0x40022100 8006f94: 40022300 .word 0x40022300 8006f98: 58026300 .word 0x58026300 08006f9c : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8006f9c: b580 push {r7, lr} 8006f9e: b084 sub sp, #16 8006fa0: af00 add r7, sp, #0 8006fa2: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8006fa4: 687b ldr r3, [r7, #4] 8006fa6: 681b ldr r3, [r3, #0] 8006fa8: 4618 mov r0, r3 8006faa: f7ff f94a bl 8006242 8006fae: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8006fb0: 687b ldr r3, [r7, #4] 8006fb2: 681b ldr r3, [r3, #0] 8006fb4: 4618 mov r0, r3 8006fb6: f7ff f931 bl 800621c 8006fba: 4603 mov r3, r0 8006fbc: 2b00 cmp r3, #0 8006fbe: d047 beq.n 8007050 && (tmp_adc_is_disable_on_going == 0UL) 8006fc0: 68fb ldr r3, [r7, #12] 8006fc2: 2b00 cmp r3, #0 8006fc4: d144 bne.n 8007050 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8006fc6: 687b ldr r3, [r7, #4] 8006fc8: 681b ldr r3, [r3, #0] 8006fca: 689b ldr r3, [r3, #8] 8006fcc: f003 030d and.w r3, r3, #13 8006fd0: 2b01 cmp r3, #1 8006fd2: d10c bne.n 8006fee { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8006fd4: 687b ldr r3, [r7, #4] 8006fd6: 681b ldr r3, [r3, #0] 8006fd8: 4618 mov r0, r3 8006fda: f7ff f90b bl 80061f4 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8006fde: 687b ldr r3, [r7, #4] 8006fe0: 681b ldr r3, [r3, #0] 8006fe2: 2203 movs r2, #3 8006fe4: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 8006fe6: f7fe ff19 bl 8005e1c 8006fea: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006fec: e029 b.n 8007042 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006fee: 687b ldr r3, [r7, #4] 8006ff0: 6d5b ldr r3, [r3, #84] @ 0x54 8006ff2: f043 0210 orr.w r2, r3, #16 8006ff6: 687b ldr r3, [r7, #4] 8006ff8: 655a str r2, [r3, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006ffa: 687b ldr r3, [r7, #4] 8006ffc: 6d9b ldr r3, [r3, #88] @ 0x58 8006ffe: f043 0201 orr.w r2, r3, #1 8007002: 687b ldr r3, [r7, #4] 8007004: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8007006: 2301 movs r3, #1 8007008: e023 b.n 8007052 { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 800700a: f7fe ff07 bl 8005e1c 800700e: 4602 mov r2, r0 8007010: 68bb ldr r3, [r7, #8] 8007012: 1ad3 subs r3, r2, r3 8007014: 2b02 cmp r3, #2 8007016: d914 bls.n 8007042 { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8007018: 687b ldr r3, [r7, #4] 800701a: 681b ldr r3, [r3, #0] 800701c: 689b ldr r3, [r3, #8] 800701e: f003 0301 and.w r3, r3, #1 8007022: 2b00 cmp r3, #0 8007024: d00d beq.n 8007042 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8007026: 687b ldr r3, [r7, #4] 8007028: 6d5b ldr r3, [r3, #84] @ 0x54 800702a: f043 0210 orr.w r2, r3, #16 800702e: 687b ldr r3, [r7, #4] 8007030: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8007032: 687b ldr r3, [r7, #4] 8007034: 6d9b ldr r3, [r3, #88] @ 0x58 8007036: f043 0201 orr.w r2, r3, #1 800703a: 687b ldr r3, [r7, #4] 800703c: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 800703e: 2301 movs r3, #1 8007040: e007 b.n 8007052 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8007042: 687b ldr r3, [r7, #4] 8007044: 681b ldr r3, [r3, #0] 8007046: 689b ldr r3, [r3, #8] 8007048: f003 0301 and.w r3, r3, #1 800704c: 2b00 cmp r3, #0 800704e: d1dc bne.n 800700a } } } /* Return HAL status */ return HAL_OK; 8007050: 2300 movs r3, #0 } 8007052: 4618 mov r0, r3 8007054: 3710 adds r7, #16 8007056: 46bd mov sp, r7 8007058: bd80 pop {r7, pc} 0800705a : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 800705a: b580 push {r7, lr} 800705c: b084 sub sp, #16 800705e: af00 add r7, sp, #0 8007060: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007062: 687b ldr r3, [r7, #4] 8007064: 6b9b ldr r3, [r3, #56] @ 0x38 8007066: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8007068: 68fb ldr r3, [r7, #12] 800706a: 6d5b ldr r3, [r3, #84] @ 0x54 800706c: f003 0350 and.w r3, r3, #80 @ 0x50 8007070: 2b00 cmp r3, #0 8007072: d14b bne.n 800710c { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 8007074: 68fb ldr r3, [r7, #12] 8007076: 6d5b ldr r3, [r3, #84] @ 0x54 8007078: f443 7200 orr.w r2, r3, #512 @ 0x200 800707c: 68fb ldr r3, [r7, #12] 800707e: 655a str r2, [r3, #84] @ 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8007080: 68fb ldr r3, [r7, #12] 8007082: 681b ldr r3, [r3, #0] 8007084: 681b ldr r3, [r3, #0] 8007086: f003 0308 and.w r3, r3, #8 800708a: 2b00 cmp r3, #0 800708c: d021 beq.n 80070d2 { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 800708e: 68fb ldr r3, [r7, #12] 8007090: 681b ldr r3, [r3, #0] 8007092: 4618 mov r0, r3 8007094: f7fe ff9c bl 8005fd0 8007098: 4603 mov r3, r0 800709a: 2b00 cmp r3, #0 800709c: d032 beq.n 8007104 { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 800709e: 68fb ldr r3, [r7, #12] 80070a0: 681b ldr r3, [r3, #0] 80070a2: 68db ldr r3, [r3, #12] 80070a4: f403 5300 and.w r3, r3, #8192 @ 0x2000 80070a8: 2b00 cmp r3, #0 80070aa: d12b bne.n 8007104 { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80070ac: 68fb ldr r3, [r7, #12] 80070ae: 6d5b ldr r3, [r3, #84] @ 0x54 80070b0: f423 7280 bic.w r2, r3, #256 @ 0x100 80070b4: 68fb ldr r3, [r7, #12] 80070b6: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 80070b8: 68fb ldr r3, [r7, #12] 80070ba: 6d5b ldr r3, [r3, #84] @ 0x54 80070bc: f403 5380 and.w r3, r3, #4096 @ 0x1000 80070c0: 2b00 cmp r3, #0 80070c2: d11f bne.n 8007104 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80070c4: 68fb ldr r3, [r7, #12] 80070c6: 6d5b ldr r3, [r3, #84] @ 0x54 80070c8: f043 0201 orr.w r2, r3, #1 80070cc: 68fb ldr r3, [r7, #12] 80070ce: 655a str r2, [r3, #84] @ 0x54 80070d0: e018 b.n 8007104 } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 80070d2: 68fb ldr r3, [r7, #12] 80070d4: 681b ldr r3, [r3, #0] 80070d6: 68db ldr r3, [r3, #12] 80070d8: f003 0303 and.w r3, r3, #3 80070dc: 2b00 cmp r3, #0 80070de: d111 bne.n 8007104 { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80070e0: 68fb ldr r3, [r7, #12] 80070e2: 6d5b ldr r3, [r3, #84] @ 0x54 80070e4: f423 7280 bic.w r2, r3, #256 @ 0x100 80070e8: 68fb ldr r3, [r7, #12] 80070ea: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 80070ec: 68fb ldr r3, [r7, #12] 80070ee: 6d5b ldr r3, [r3, #84] @ 0x54 80070f0: f403 5380 and.w r3, r3, #4096 @ 0x1000 80070f4: 2b00 cmp r3, #0 80070f6: d105 bne.n 8007104 { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80070f8: 68fb ldr r3, [r7, #12] 80070fa: 6d5b ldr r3, [r3, #84] @ 0x54 80070fc: f043 0201 orr.w r2, r3, #1 8007100: 68fb ldr r3, [r7, #12] 8007102: 655a str r2, [r3, #84] @ 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 8007104: 68f8 ldr r0, [r7, #12] 8007106: f7fa fb5f bl 80017c8 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 800710a: e00e b.n 800712a if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 800710c: 68fb ldr r3, [r7, #12] 800710e: 6d5b ldr r3, [r3, #84] @ 0x54 8007110: f003 0310 and.w r3, r3, #16 8007114: 2b00 cmp r3, #0 8007116: d003 beq.n 8007120 HAL_ADC_ErrorCallback(hadc); 8007118: 68f8 ldr r0, [r7, #12] 800711a: f7ff fb4f bl 80067bc } 800711e: e004 b.n 800712a hadc->DMA_Handle->XferErrorCallback(hdma); 8007120: 68fb ldr r3, [r7, #12] 8007122: 6cdb ldr r3, [r3, #76] @ 0x4c 8007124: 6cdb ldr r3, [r3, #76] @ 0x4c 8007126: 6878 ldr r0, [r7, #4] 8007128: 4798 blx r3 } 800712a: bf00 nop 800712c: 3710 adds r7, #16 800712e: 46bd mov sp, r7 8007130: bd80 pop {r7, pc} 08007132 : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 8007132: b580 push {r7, lr} 8007134: b084 sub sp, #16 8007136: af00 add r7, sp, #0 8007138: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800713a: 687b ldr r3, [r7, #4] 800713c: 6b9b ldr r3, [r3, #56] @ 0x38 800713e: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8007140: 68f8 ldr r0, [r7, #12] 8007142: f7ff fb31 bl 80067a8 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8007146: bf00 nop 8007148: 3710 adds r7, #16 800714a: 46bd mov sp, r7 800714c: bd80 pop {r7, pc} 0800714e : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 800714e: b580 push {r7, lr} 8007150: b084 sub sp, #16 8007152: af00 add r7, sp, #0 8007154: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007156: 687b ldr r3, [r7, #4] 8007158: 6b9b ldr r3, [r3, #56] @ 0x38 800715a: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 800715c: 68fb ldr r3, [r7, #12] 800715e: 6d5b ldr r3, [r3, #84] @ 0x54 8007160: f043 0240 orr.w r2, r3, #64 @ 0x40 8007164: 68fb ldr r3, [r7, #12] 8007166: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8007168: 68fb ldr r3, [r7, #12] 800716a: 6d9b ldr r3, [r3, #88] @ 0x58 800716c: f043 0204 orr.w r2, r3, #4 8007170: 68fb ldr r3, [r7, #12] 8007172: 659a str r2, [r3, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 8007174: 68f8 ldr r0, [r7, #12] 8007176: f7ff fb21 bl 80067bc #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800717a: bf00 nop 800717c: 3710 adds r7, #16 800717e: 46bd mov sp, r7 8007180: bd80 pop {r7, pc} ... 08007184 : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 8007184: b580 push {r7, lr} 8007186: b084 sub sp, #16 8007188: af00 add r7, sp, #0 800718a: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 800718c: 687b ldr r3, [r7, #4] 800718e: 681b ldr r3, [r3, #0] 8007190: 4a7a ldr r2, [pc, #488] @ (800737c ) 8007192: 4293 cmp r3, r2 8007194: d004 beq.n 80071a0 8007196: 687b ldr r3, [r7, #4] 8007198: 681b ldr r3, [r3, #0] 800719a: 4a79 ldr r2, [pc, #484] @ (8007380 ) 800719c: 4293 cmp r3, r2 800719e: d109 bne.n 80071b4 80071a0: 4b78 ldr r3, [pc, #480] @ (8007384 ) 80071a2: 689b ldr r3, [r3, #8] 80071a4: f403 3340 and.w r3, r3, #196608 @ 0x30000 80071a8: 2b00 cmp r3, #0 80071aa: bf14 ite ne 80071ac: 2301 movne r3, #1 80071ae: 2300 moveq r3, #0 80071b0: b2db uxtb r3, r3 80071b2: e008 b.n 80071c6 80071b4: 4b74 ldr r3, [pc, #464] @ (8007388 ) 80071b6: 689b ldr r3, [r3, #8] 80071b8: f403 3340 and.w r3, r3, #196608 @ 0x30000 80071bc: 2b00 cmp r3, #0 80071be: bf14 ite ne 80071c0: 2301 movne r3, #1 80071c2: 2300 moveq r3, #0 80071c4: b2db uxtb r3, r3 80071c6: 2b00 cmp r3, #0 80071c8: d01c beq.n 8007204 { freq = HAL_RCC_GetHCLKFreq(); 80071ca: f005 fb47 bl 800c85c 80071ce: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 80071d0: 687b ldr r3, [r7, #4] 80071d2: 685b ldr r3, [r3, #4] 80071d4: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 80071d8: d010 beq.n 80071fc 80071da: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 80071de: d873 bhi.n 80072c8 80071e0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80071e4: d002 beq.n 80071ec 80071e6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80071ea: d16d bne.n 80072c8 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 80071ec: 687b ldr r3, [r7, #4] 80071ee: 685b ldr r3, [r3, #4] 80071f0: 0c1b lsrs r3, r3, #16 80071f2: 68fa ldr r2, [r7, #12] 80071f4: fbb2 f3f3 udiv r3, r2, r3 80071f8: 60fb str r3, [r7, #12] break; 80071fa: e068 b.n 80072ce case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 80071fc: 68fb ldr r3, [r7, #12] 80071fe: 089b lsrs r3, r3, #2 8007200: 60fb str r3, [r7, #12] break; 8007202: e064 b.n 80072ce break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 8007204: f44f 2000 mov.w r0, #524288 @ 0x80000 8007208: f04f 0100 mov.w r1, #0 800720c: f006 fdb2 bl 800dd74 8007210: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 8007212: 687b ldr r3, [r7, #4] 8007214: 685b ldr r3, [r3, #4] 8007216: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 800721a: d051 beq.n 80072c0 800721c: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8007220: d854 bhi.n 80072cc 8007222: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8007226: d047 beq.n 80072b8 8007228: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 800722c: d84e bhi.n 80072cc 800722e: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8007232: d03d beq.n 80072b0 8007234: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8007238: d848 bhi.n 80072cc 800723a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800723e: d033 beq.n 80072a8 8007240: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8007244: d842 bhi.n 80072cc 8007246: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 800724a: d029 beq.n 80072a0 800724c: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8007250: d83c bhi.n 80072cc 8007252: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8007256: d01a beq.n 800728e 8007258: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 800725c: d836 bhi.n 80072cc 800725e: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8007262: d014 beq.n 800728e 8007264: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8007268: d830 bhi.n 80072cc 800726a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800726e: d00e beq.n 800728e 8007270: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8007274: d82a bhi.n 80072cc 8007276: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 800727a: d008 beq.n 800728e 800727c: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8007280: d824 bhi.n 80072cc 8007282: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8007286: d002 beq.n 800728e 8007288: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 800728c: d11e bne.n 80072cc case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 800728e: 687b ldr r3, [r7, #4] 8007290: 685b ldr r3, [r3, #4] 8007292: 0c9b lsrs r3, r3, #18 8007294: 005b lsls r3, r3, #1 8007296: 68fa ldr r2, [r7, #12] 8007298: fbb2 f3f3 udiv r3, r2, r3 800729c: 60fb str r3, [r7, #12] break; 800729e: e016 b.n 80072ce case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 80072a0: 68fb ldr r3, [r7, #12] 80072a2: 091b lsrs r3, r3, #4 80072a4: 60fb str r3, [r7, #12] break; 80072a6: e012 b.n 80072ce case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 80072a8: 68fb ldr r3, [r7, #12] 80072aa: 095b lsrs r3, r3, #5 80072ac: 60fb str r3, [r7, #12] break; 80072ae: e00e b.n 80072ce case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 80072b0: 68fb ldr r3, [r7, #12] 80072b2: 099b lsrs r3, r3, #6 80072b4: 60fb str r3, [r7, #12] break; 80072b6: e00a b.n 80072ce case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 80072b8: 68fb ldr r3, [r7, #12] 80072ba: 09db lsrs r3, r3, #7 80072bc: 60fb str r3, [r7, #12] break; 80072be: e006 b.n 80072ce case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 80072c0: 68fb ldr r3, [r7, #12] 80072c2: 0a1b lsrs r3, r3, #8 80072c4: 60fb str r3, [r7, #12] break; 80072c6: e002 b.n 80072ce break; 80072c8: bf00 nop 80072ca: e000 b.n 80072ce default: break; 80072cc: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 80072ce: f7fe fdb1 bl 8005e34 80072d2: 4603 mov r3, r0 80072d4: f241 0203 movw r2, #4099 @ 0x1003 80072d8: 4293 cmp r3, r2 80072da: d815 bhi.n 8007308 { if (freq > 20000000UL) 80072dc: 68fb ldr r3, [r7, #12] 80072de: 4a2b ldr r2, [pc, #172] @ (800738c ) 80072e0: 4293 cmp r3, r2 80072e2: d908 bls.n 80072f6 { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80072e4: 687b ldr r3, [r7, #4] 80072e6: 681b ldr r3, [r3, #0] 80072e8: 689a ldr r2, [r3, #8] 80072ea: 687b ldr r3, [r7, #4] 80072ec: 681b ldr r3, [r3, #0] 80072ee: f442 7280 orr.w r2, r2, #256 @ 0x100 80072f2: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 80072f4: e03e b.n 8007374 CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80072f6: 687b ldr r3, [r7, #4] 80072f8: 681b ldr r3, [r3, #0] 80072fa: 689a ldr r2, [r3, #8] 80072fc: 687b ldr r3, [r7, #4] 80072fe: 681b ldr r3, [r3, #0] 8007300: f422 7280 bic.w r2, r2, #256 @ 0x100 8007304: 609a str r2, [r3, #8] } 8007306: e035 b.n 8007374 freq /= 2U; /* divider by 2 for Rev.V */ 8007308: 68fb ldr r3, [r7, #12] 800730a: 085b lsrs r3, r3, #1 800730c: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 800730e: 68fb ldr r3, [r7, #12] 8007310: 4a1f ldr r2, [pc, #124] @ (8007390 ) 8007312: 4293 cmp r3, r2 8007314: d808 bhi.n 8007328 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 8007316: 687b ldr r3, [r7, #4] 8007318: 681b ldr r3, [r3, #0] 800731a: 689a ldr r2, [r3, #8] 800731c: 687b ldr r3, [r7, #4] 800731e: 681b ldr r3, [r3, #0] 8007320: f422 7240 bic.w r2, r2, #768 @ 0x300 8007324: 609a str r2, [r3, #8] } 8007326: e025 b.n 8007374 else if (freq <= 12500000UL) 8007328: 68fb ldr r3, [r7, #12] 800732a: 4a1a ldr r2, [pc, #104] @ (8007394 ) 800732c: 4293 cmp r3, r2 800732e: d80a bhi.n 8007346 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 8007330: 687b ldr r3, [r7, #4] 8007332: 681b ldr r3, [r3, #0] 8007334: 689b ldr r3, [r3, #8] 8007336: f423 7240 bic.w r2, r3, #768 @ 0x300 800733a: 687b ldr r3, [r7, #4] 800733c: 681b ldr r3, [r3, #0] 800733e: f442 7280 orr.w r2, r2, #256 @ 0x100 8007342: 609a str r2, [r3, #8] } 8007344: e016 b.n 8007374 else if (freq <= 25000000UL) 8007346: 68fb ldr r3, [r7, #12] 8007348: 4a13 ldr r2, [pc, #76] @ (8007398 ) 800734a: 4293 cmp r3, r2 800734c: d80a bhi.n 8007364 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 800734e: 687b ldr r3, [r7, #4] 8007350: 681b ldr r3, [r3, #0] 8007352: 689b ldr r3, [r3, #8] 8007354: f423 7240 bic.w r2, r3, #768 @ 0x300 8007358: 687b ldr r3, [r7, #4] 800735a: 681b ldr r3, [r3, #0] 800735c: f442 7200 orr.w r2, r2, #512 @ 0x200 8007360: 609a str r2, [r3, #8] } 8007362: e007 b.n 8007374 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 8007364: 687b ldr r3, [r7, #4] 8007366: 681b ldr r3, [r3, #0] 8007368: 689a ldr r2, [r3, #8] 800736a: 687b ldr r3, [r7, #4] 800736c: 681b ldr r3, [r3, #0] 800736e: f442 7240 orr.w r2, r2, #768 @ 0x300 8007372: 609a str r2, [r3, #8] } 8007374: bf00 nop 8007376: 3710 adds r7, #16 8007378: 46bd mov sp, r7 800737a: bd80 pop {r7, pc} 800737c: 40022000 .word 0x40022000 8007380: 40022100 .word 0x40022100 8007384: 40022300 .word 0x40022300 8007388: 58026300 .word 0x58026300 800738c: 01312d00 .word 0x01312d00 8007390: 005f5e10 .word 0x005f5e10 8007394: 00bebc20 .word 0x00bebc20 8007398: 017d7840 .word 0x017d7840 0800739c : { 800739c: b480 push {r7} 800739e: b083 sub sp, #12 80073a0: af00 add r7, sp, #0 80073a2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80073a4: 687b ldr r3, [r7, #4] 80073a6: 689b ldr r3, [r3, #8] 80073a8: f003 0301 and.w r3, r3, #1 80073ac: 2b01 cmp r3, #1 80073ae: d101 bne.n 80073b4 80073b0: 2301 movs r3, #1 80073b2: e000 b.n 80073b6 80073b4: 2300 movs r3, #0 } 80073b6: 4618 mov r0, r3 80073b8: 370c adds r7, #12 80073ba: 46bd mov sp, r7 80073bc: f85d 7b04 ldr.w r7, [sp], #4 80073c0: 4770 bx lr ... 080073c4 : { 80073c4: b480 push {r7} 80073c6: b085 sub sp, #20 80073c8: af00 add r7, sp, #0 80073ca: 60f8 str r0, [r7, #12] 80073cc: 60b9 str r1, [r7, #8] 80073ce: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CR, 80073d0: 68fb ldr r3, [r7, #12] 80073d2: 689a ldr r2, [r3, #8] 80073d4: 4b09 ldr r3, [pc, #36] @ (80073fc ) 80073d6: 4013 ands r3, r2 80073d8: 68ba ldr r2, [r7, #8] 80073da: f402 3180 and.w r1, r2, #65536 @ 0x10000 80073de: 687a ldr r2, [r7, #4] 80073e0: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80073e4: 430a orrs r2, r1 80073e6: 4313 orrs r3, r2 80073e8: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 80073ec: 68fb ldr r3, [r7, #12] 80073ee: 609a str r2, [r3, #8] } 80073f0: bf00 nop 80073f2: 3714 adds r7, #20 80073f4: 46bd mov sp, r7 80073f6: f85d 7b04 ldr.w r7, [sp], #4 80073fa: 4770 bx lr 80073fc: 3ffeffc0 .word 0x3ffeffc0 08007400 : { 8007400: b480 push {r7} 8007402: b083 sub sp, #12 8007404: af00 add r7, sp, #0 8007406: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8007408: 687b ldr r3, [r7, #4] 800740a: 689b ldr r3, [r3, #8] 800740c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007410: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007414: d101 bne.n 800741a 8007416: 2301 movs r3, #1 8007418: e000 b.n 800741c 800741a: 2300 movs r3, #0 } 800741c: 4618 mov r0, r3 800741e: 370c adds r7, #12 8007420: 46bd mov sp, r7 8007422: f85d 7b04 ldr.w r7, [sp], #4 8007426: 4770 bx lr 08007428 : { 8007428: b480 push {r7} 800742a: b083 sub sp, #12 800742c: af00 add r7, sp, #0 800742e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8007430: 687b ldr r3, [r7, #4] 8007432: 689b ldr r3, [r3, #8] 8007434: f003 0304 and.w r3, r3, #4 8007438: 2b04 cmp r3, #4 800743a: d101 bne.n 8007440 800743c: 2301 movs r3, #1 800743e: e000 b.n 8007442 8007440: 2300 movs r3, #0 } 8007442: 4618 mov r0, r3 8007444: 370c adds r7, #12 8007446: 46bd mov sp, r7 8007448: f85d 7b04 ldr.w r7, [sp], #4 800744c: 4770 bx lr ... 08007450 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 8007450: b580 push {r7, lr} 8007452: b086 sub sp, #24 8007454: af00 add r7, sp, #0 8007456: 60f8 str r0, [r7, #12] 8007458: 60b9 str r1, [r7, #8] 800745a: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 800745c: 2300 movs r3, #0 800745e: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 8007460: 68fb ldr r3, [r7, #12] 8007462: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007466: 2b01 cmp r3, #1 8007468: d101 bne.n 800746e 800746a: 2302 movs r3, #2 800746c: e04c b.n 8007508 800746e: 68fb ldr r3, [r7, #12] 8007470: 2201 movs r2, #1 8007472: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 8007476: 68f8 ldr r0, [r7, #12] 8007478: f7ff fd90 bl 8006f9c 800747c: 4603 mov r3, r0 800747e: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8007480: 7dfb ldrb r3, [r7, #23] 8007482: 2b00 cmp r3, #0 8007484: d135 bne.n 80074f2 { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 8007486: 68fb ldr r3, [r7, #12] 8007488: 6d5a ldr r2, [r3, #84] @ 0x54 800748a: 4b21 ldr r3, [pc, #132] @ (8007510 ) 800748c: 4013 ands r3, r2 800748e: f043 0202 orr.w r2, r3, #2 8007492: 68fb ldr r3, [r7, #12] 8007494: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 8007496: 68fb ldr r3, [r7, #12] 8007498: 681b ldr r3, [r3, #0] 800749a: 687a ldr r2, [r7, #4] 800749c: 68b9 ldr r1, [r7, #8] 800749e: 4618 mov r0, r3 80074a0: f7ff ff90 bl 80073c4 /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 80074a4: e014 b.n 80074d0 { wait_loop_index++; 80074a6: 693b ldr r3, [r7, #16] 80074a8: 3301 adds r3, #1 80074aa: 613b str r3, [r7, #16] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 80074ac: 693b ldr r3, [r7, #16] 80074ae: 4a19 ldr r2, [pc, #100] @ (8007514 ) 80074b0: 4293 cmp r3, r2 80074b2: d30d bcc.n 80074d0 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80074b4: 68fb ldr r3, [r7, #12] 80074b6: 6d5b ldr r3, [r3, #84] @ 0x54 80074b8: f023 0312 bic.w r3, r3, #18 80074bc: f043 0210 orr.w r2, r3, #16 80074c0: 68fb ldr r3, [r7, #12] 80074c2: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 80074c4: 68fb ldr r3, [r7, #12] 80074c6: 2200 movs r2, #0 80074c8: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 80074cc: 2301 movs r3, #1 80074ce: e01b b.n 8007508 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 80074d0: 68fb ldr r3, [r7, #12] 80074d2: 681b ldr r3, [r3, #0] 80074d4: 4618 mov r0, r3 80074d6: f7ff ff93 bl 8007400 80074da: 4603 mov r3, r0 80074dc: 2b00 cmp r3, #0 80074de: d1e2 bne.n 80074a6 } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80074e0: 68fb ldr r3, [r7, #12] 80074e2: 6d5b ldr r3, [r3, #84] @ 0x54 80074e4: f023 0303 bic.w r3, r3, #3 80074e8: f043 0201 orr.w r2, r3, #1 80074ec: 68fb ldr r3, [r7, #12] 80074ee: 655a str r2, [r3, #84] @ 0x54 80074f0: e005 b.n 80074fe HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80074f2: 68fb ldr r3, [r7, #12] 80074f4: 6d5b ldr r3, [r3, #84] @ 0x54 80074f6: f043 0210 orr.w r2, r3, #16 80074fa: 68fb ldr r3, [r7, #12] 80074fc: 655a str r2, [r3, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 80074fe: 68fb ldr r3, [r7, #12] 8007500: 2200 movs r2, #0 8007502: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8007506: 7dfb ldrb r3, [r7, #23] } 8007508: 4618 mov r0, r3 800750a: 3718 adds r7, #24 800750c: 46bd mov sp, r7 800750e: bd80 pop {r7, pc} 8007510: ffffeefd .word 0xffffeefd 8007514: 25c3f800 .word 0x25c3f800 08007518 : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 8007518: b590 push {r4, r7, lr} 800751a: b09f sub sp, #124 @ 0x7c 800751c: af00 add r7, sp, #0 800751e: 6078 str r0, [r7, #4] 8007520: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 8007522: 2300 movs r3, #0 8007524: f887 3077 strb.w r3, [r7, #119] @ 0x77 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8007528: 687b ldr r3, [r7, #4] 800752a: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 800752e: 2b01 cmp r3, #1 8007530: d101 bne.n 8007536 8007532: 2302 movs r3, #2 8007534: e0be b.n 80076b4 8007536: 687b ldr r3, [r7, #4] 8007538: 2201 movs r2, #1 800753a: f883 2050 strb.w r2, [r3, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 800753e: 2300 movs r3, #0 8007540: 65fb str r3, [r7, #92] @ 0x5c tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 8007542: 2300 movs r3, #0 8007544: 663b str r3, [r7, #96] @ 0x60 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 8007546: 687b ldr r3, [r7, #4] 8007548: 681b ldr r3, [r3, #0] 800754a: 4a5c ldr r2, [pc, #368] @ (80076bc ) 800754c: 4293 cmp r3, r2 800754e: d102 bne.n 8007556 8007550: 4b5b ldr r3, [pc, #364] @ (80076c0 ) 8007552: 60bb str r3, [r7, #8] 8007554: e001 b.n 800755a 8007556: 2300 movs r3, #0 8007558: 60bb str r3, [r7, #8] if (tmphadcSlave.Instance == NULL) 800755a: 68bb ldr r3, [r7, #8] 800755c: 2b00 cmp r3, #0 800755e: d10b bne.n 8007578 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8007560: 687b ldr r3, [r7, #4] 8007562: 6d5b ldr r3, [r3, #84] @ 0x54 8007564: f043 0220 orr.w r2, r3, #32 8007568: 687b ldr r3, [r7, #4] 800756a: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 800756c: 687b ldr r3, [r7, #4] 800756e: 2200 movs r2, #0 8007570: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 8007574: 2301 movs r3, #1 8007576: e09d b.n 80076b4 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); 8007578: 68bb ldr r3, [r7, #8] 800757a: 4618 mov r0, r3 800757c: f7ff ff54 bl 8007428 8007580: 6738 str r0, [r7, #112] @ 0x70 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8007582: 687b ldr r3, [r7, #4] 8007584: 681b ldr r3, [r3, #0] 8007586: 4618 mov r0, r3 8007588: f7ff ff4e bl 8007428 800758c: 4603 mov r3, r0 800758e: 2b00 cmp r3, #0 8007590: d17f bne.n 8007692 && (tmphadcSlave_conversion_on_going == 0UL)) 8007592: 6f3b ldr r3, [r7, #112] @ 0x70 8007594: 2b00 cmp r3, #0 8007596: d17c bne.n 8007692 { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 8007598: 687b ldr r3, [r7, #4] 800759a: 681b ldr r3, [r3, #0] 800759c: 4a47 ldr r2, [pc, #284] @ (80076bc ) 800759e: 4293 cmp r3, r2 80075a0: d004 beq.n 80075ac 80075a2: 687b ldr r3, [r7, #4] 80075a4: 681b ldr r3, [r3, #0] 80075a6: 4a46 ldr r2, [pc, #280] @ (80076c0 ) 80075a8: 4293 cmp r3, r2 80075aa: d101 bne.n 80075b0 80075ac: 4b45 ldr r3, [pc, #276] @ (80076c4 ) 80075ae: e000 b.n 80075b2 80075b0: 4b45 ldr r3, [pc, #276] @ (80076c8 ) 80075b2: 66fb str r3, [r7, #108] @ 0x6c /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 80075b4: 683b ldr r3, [r7, #0] 80075b6: 681b ldr r3, [r3, #0] 80075b8: 2b00 cmp r3, #0 80075ba: d039 beq.n 8007630 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 80075bc: 6efb ldr r3, [r7, #108] @ 0x6c 80075be: 689b ldr r3, [r3, #8] 80075c0: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80075c4: 683b ldr r3, [r7, #0] 80075c6: 685b ldr r3, [r3, #4] 80075c8: 431a orrs r2, r3 80075ca: 6efb ldr r3, [r7, #108] @ 0x6c 80075cc: 609a str r2, [r3, #8] /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80075ce: 687b ldr r3, [r7, #4] 80075d0: 681b ldr r3, [r3, #0] 80075d2: 4a3a ldr r2, [pc, #232] @ (80076bc ) 80075d4: 4293 cmp r3, r2 80075d6: d004 beq.n 80075e2 80075d8: 687b ldr r3, [r7, #4] 80075da: 681b ldr r3, [r3, #0] 80075dc: 4a38 ldr r2, [pc, #224] @ (80076c0 ) 80075de: 4293 cmp r3, r2 80075e0: d10e bne.n 8007600 80075e2: 4836 ldr r0, [pc, #216] @ (80076bc ) 80075e4: f7ff feda bl 800739c 80075e8: 4604 mov r4, r0 80075ea: 4835 ldr r0, [pc, #212] @ (80076c0 ) 80075ec: f7ff fed6 bl 800739c 80075f0: 4603 mov r3, r0 80075f2: 4323 orrs r3, r4 80075f4: 2b00 cmp r3, #0 80075f6: bf0c ite eq 80075f8: 2301 moveq r3, #1 80075fa: 2300 movne r3, #0 80075fc: b2db uxtb r3, r3 80075fe: e008 b.n 8007612 8007600: 4832 ldr r0, [pc, #200] @ (80076cc ) 8007602: f7ff fecb bl 800739c 8007606: 4603 mov r3, r0 8007608: 2b00 cmp r3, #0 800760a: bf0c ite eq 800760c: 2301 moveq r3, #1 800760e: 2300 movne r3, #0 8007610: b2db uxtb r3, r3 8007612: 2b00 cmp r3, #0 8007614: d047 beq.n 80076a6 { MODIFY_REG(tmpADC_Common->CCR, 8007616: 6efb ldr r3, [r7, #108] @ 0x6c 8007618: 689a ldr r2, [r3, #8] 800761a: 4b2d ldr r3, [pc, #180] @ (80076d0 ) 800761c: 4013 ands r3, r2 800761e: 683a ldr r2, [r7, #0] 8007620: 6811 ldr r1, [r2, #0] 8007622: 683a ldr r2, [r7, #0] 8007624: 6892 ldr r2, [r2, #8] 8007626: 430a orrs r2, r1 8007628: 431a orrs r2, r3 800762a: 6efb ldr r3, [r7, #108] @ 0x6c 800762c: 609a str r2, [r3, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 800762e: e03a b.n 80076a6 ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 8007630: 6efb ldr r3, [r7, #108] @ 0x6c 8007632: 689b ldr r3, [r3, #8] 8007634: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8007638: 6efb ldr r3, [r7, #108] @ 0x6c 800763a: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 800763c: 687b ldr r3, [r7, #4] 800763e: 681b ldr r3, [r3, #0] 8007640: 4a1e ldr r2, [pc, #120] @ (80076bc ) 8007642: 4293 cmp r3, r2 8007644: d004 beq.n 8007650 8007646: 687b ldr r3, [r7, #4] 8007648: 681b ldr r3, [r3, #0] 800764a: 4a1d ldr r2, [pc, #116] @ (80076c0 ) 800764c: 4293 cmp r3, r2 800764e: d10e bne.n 800766e 8007650: 481a ldr r0, [pc, #104] @ (80076bc ) 8007652: f7ff fea3 bl 800739c 8007656: 4604 mov r4, r0 8007658: 4819 ldr r0, [pc, #100] @ (80076c0 ) 800765a: f7ff fe9f bl 800739c 800765e: 4603 mov r3, r0 8007660: 4323 orrs r3, r4 8007662: 2b00 cmp r3, #0 8007664: bf0c ite eq 8007666: 2301 moveq r3, #1 8007668: 2300 movne r3, #0 800766a: b2db uxtb r3, r3 800766c: e008 b.n 8007680 800766e: 4817 ldr r0, [pc, #92] @ (80076cc ) 8007670: f7ff fe94 bl 800739c 8007674: 4603 mov r3, r0 8007676: 2b00 cmp r3, #0 8007678: bf0c ite eq 800767a: 2301 moveq r3, #1 800767c: 2300 movne r3, #0 800767e: b2db uxtb r3, r3 8007680: 2b00 cmp r3, #0 8007682: d010 beq.n 80076a6 { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 8007684: 6efb ldr r3, [r7, #108] @ 0x6c 8007686: 689a ldr r2, [r3, #8] 8007688: 4b11 ldr r3, [pc, #68] @ (80076d0 ) 800768a: 4013 ands r3, r2 800768c: 6efa ldr r2, [r7, #108] @ 0x6c 800768e: 6093 str r3, [r2, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007690: e009 b.n 80076a6 /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8007692: 687b ldr r3, [r7, #4] 8007694: 6d5b ldr r3, [r3, #84] @ 0x54 8007696: f043 0220 orr.w r2, r3, #32 800769a: 687b ldr r3, [r7, #4] 800769c: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 800769e: 2301 movs r3, #1 80076a0: f887 3077 strb.w r3, [r7, #119] @ 0x77 80076a4: e000 b.n 80076a8 if (multimode->Mode != ADC_MODE_INDEPENDENT) 80076a6: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 80076a8: 687b ldr r3, [r7, #4] 80076aa: 2200 movs r2, #0 80076ac: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 80076b0: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 80076b4: 4618 mov r0, r3 80076b6: 377c adds r7, #124 @ 0x7c 80076b8: 46bd mov sp, r7 80076ba: bd90 pop {r4, r7, pc} 80076bc: 40022000 .word 0x40022000 80076c0: 40022100 .word 0x40022100 80076c4: 40022300 .word 0x40022300 80076c8: 58026300 .word 0x58026300 80076cc: 58026000 .word 0x58026000 80076d0: fffff0e0 .word 0xfffff0e0 080076d4 : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 80076d4: b580 push {r7, lr} 80076d6: b088 sub sp, #32 80076d8: af00 add r7, sp, #0 80076da: 6078 str r0, [r7, #4] uint32_t tmp_csr ; uint32_t exti_line ; uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 80076dc: 2300 movs r3, #0 80076de: 60fb str r3, [r7, #12] HAL_StatusTypeDef status = HAL_OK; 80076e0: 2300 movs r3, #0 80076e2: 77fb strb r3, [r7, #31] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 80076e4: 687b ldr r3, [r7, #4] 80076e6: 2b00 cmp r3, #0 80076e8: d102 bne.n 80076f0 { status = HAL_ERROR; 80076ea: 2301 movs r3, #1 80076ec: 77fb strb r3, [r7, #31] 80076ee: e10e b.n 800790e } else if(__HAL_COMP_IS_LOCKED(hcomp)) 80076f0: 687b ldr r3, [r7, #4] 80076f2: 681b ldr r3, [r3, #0] 80076f4: 681b ldr r3, [r3, #0] 80076f6: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80076fa: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80076fe: d102 bne.n 8007706 { status = HAL_ERROR; 8007700: 2301 movs r3, #1 8007702: 77fb strb r3, [r7, #31] 8007704: e103 b.n 800790e assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) 8007706: 687b ldr r3, [r7, #4] 8007708: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 800770c: b2db uxtb r3, r3 800770e: 2b00 cmp r3, #0 8007710: d109 bne.n 8007726 { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; 8007712: 687b ldr r3, [r7, #4] 8007714: 2200 movs r2, #0 8007716: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); 800771a: 687b ldr r3, [r7, #4] 800771c: 2200 movs r2, #0 800771e: 629a str r2, [r3, #40] @ 0x28 /* Init the low level hardware */ hcomp->MspInitCallback(hcomp); #else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); 8007720: 6878 ldr r0, [r7, #4] 8007722: f7fc fca9 bl 8004078 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 8007726: 687b ldr r3, [r7, #4] 8007728: 681b ldr r3, [r3, #0] 800772a: 681b ldr r3, [r3, #0] 800772c: f003 0304 and.w r3, r3, #4 8007730: 61bb str r3, [r7, #24] /* Set BLANKING bits according to hcomp->Init.BlankingSrce value */ /* Set HYST bits according to hcomp->Init.Hysteresis value */ /* Set POLARITY bit according to hcomp->Init.OutputPol value */ /* Set POWERMODE bits according to hcomp->Init.Mode value */ tmp_csr = (hcomp->Init.InvertingInput | \ 8007732: 687b ldr r3, [r7, #4] 8007734: 691a ldr r2, [r3, #16] hcomp->Init.NonInvertingInput | \ 8007736: 687b ldr r3, [r7, #4] 8007738: 68db ldr r3, [r3, #12] tmp_csr = (hcomp->Init.InvertingInput | \ 800773a: 431a orrs r2, r3 hcomp->Init.BlankingSrce | \ 800773c: 687b ldr r3, [r7, #4] 800773e: 69db ldr r3, [r3, #28] hcomp->Init.NonInvertingInput | \ 8007740: 431a orrs r2, r3 hcomp->Init.Hysteresis | \ 8007742: 687b ldr r3, [r7, #4] 8007744: 695b ldr r3, [r3, #20] hcomp->Init.BlankingSrce | \ 8007746: 431a orrs r2, r3 hcomp->Init.OutputPol | \ 8007748: 687b ldr r3, [r7, #4] 800774a: 699b ldr r3, [r3, #24] hcomp->Init.Hysteresis | \ 800774c: 431a orrs r2, r3 hcomp->Init.Mode ); 800774e: 687b ldr r3, [r7, #4] 8007750: 689b ldr r3, [r3, #8] tmp_csr = (hcomp->Init.InvertingInput | \ 8007752: 4313 orrs r3, r2 8007754: 617b str r3, [r7, #20] COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST | COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN, tmp_csr ); #else MODIFY_REG(hcomp->Instance->CFGR, 8007756: 687b ldr r3, [r7, #4] 8007758: 681b ldr r3, [r3, #0] 800775a: 681a ldr r2, [r3, #0] 800775c: 4b6e ldr r3, [pc, #440] @ (8007918 ) 800775e: 4013 ands r3, r2 8007760: 687a ldr r2, [r7, #4] 8007762: 6812 ldr r2, [r2, #0] 8007764: 6979 ldr r1, [r7, #20] 8007766: 430b orrs r3, r1 8007768: 6013 str r3, [r2, #0] #endif /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 800776a: 687b ldr r3, [r7, #4] 800776c: 685b ldr r3, [r3, #4] 800776e: 2b10 cmp r3, #16 8007770: d108 bne.n 8007784 { SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8007772: 687b ldr r3, [r7, #4] 8007774: 681b ldr r3, [r3, #0] 8007776: 681a ldr r2, [r3, #0] 8007778: 687b ldr r3, [r7, #4] 800777a: 681b ldr r3, [r3, #0] 800777c: f042 0210 orr.w r2, r2, #16 8007780: 601a str r2, [r3, #0] 8007782: e007 b.n 8007794 } else { CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 8007784: 687b ldr r3, [r7, #4] 8007786: 681b ldr r3, [r3, #0] 8007788: 681a ldr r2, [r3, #0] 800778a: 687b ldr r3, [r7, #4] 800778c: 681b ldr r3, [r3, #0] 800778e: f022 0210 bic.w r2, r2, #16 8007792: 601a str r2, [r3, #0] } /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) && 8007794: 687b ldr r3, [r7, #4] 8007796: 681b ldr r3, [r3, #0] 8007798: 681b ldr r3, [r3, #0] 800779a: f003 0304 and.w r3, r3, #4 800779e: 2b00 cmp r3, #0 80077a0: d016 beq.n 80077d0 80077a2: 69bb ldr r3, [r7, #24] 80077a4: 2b00 cmp r3, #0 80077a6: d013 beq.n 80077d0 { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles.*/ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80077a8: 4b5c ldr r3, [pc, #368] @ (800791c ) 80077aa: 681b ldr r3, [r3, #0] 80077ac: 099b lsrs r3, r3, #6 80077ae: 4a5c ldr r2, [pc, #368] @ (8007920 ) 80077b0: fba2 2303 umull r2, r3, r2, r3 80077b4: 099b lsrs r3, r3, #6 80077b6: 1c5a adds r2, r3, #1 80077b8: 4613 mov r3, r2 80077ba: 009b lsls r3, r3, #2 80077bc: 4413 add r3, r2 80077be: 009b lsls r3, r3, #2 80077c0: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 80077c2: e002 b.n 80077ca { wait_loop_index --; 80077c4: 68fb ldr r3, [r7, #12] 80077c6: 3b01 subs r3, #1 80077c8: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 80077ca: 68fb ldr r3, [r7, #12] 80077cc: 2b00 cmp r3, #0 80077ce: d1f9 bne.n 80077c4 } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 80077d0: 687b ldr r3, [r7, #4] 80077d2: 681b ldr r3, [r3, #0] 80077d4: 4a53 ldr r2, [pc, #332] @ (8007924 ) 80077d6: 4293 cmp r3, r2 80077d8: d102 bne.n 80077e0 80077da: f44f 1380 mov.w r3, #1048576 @ 0x100000 80077de: e001 b.n 80077e4 80077e0: f44f 1300 mov.w r3, #2097152 @ 0x200000 80077e4: 613b str r3, [r7, #16] /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 80077e6: 687b ldr r3, [r7, #4] 80077e8: 6a1b ldr r3, [r3, #32] 80077ea: f003 0303 and.w r3, r3, #3 80077ee: 2b00 cmp r3, #0 80077f0: d06d beq.n 80078ce { /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 80077f2: 687b ldr r3, [r7, #4] 80077f4: 6a1b ldr r3, [r3, #32] 80077f6: f003 0310 and.w r3, r3, #16 80077fa: 2b00 cmp r3, #0 80077fc: d008 beq.n 8007810 { SET_BIT(EXTI->RTSR1, exti_line); 80077fe: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007802: 681a ldr r2, [r3, #0] 8007804: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007808: 693b ldr r3, [r7, #16] 800780a: 4313 orrs r3, r2 800780c: 600b str r3, [r1, #0] 800780e: e008 b.n 8007822 } else { CLEAR_BIT(EXTI->RTSR1, exti_line); 8007810: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007814: 681a ldr r2, [r3, #0] 8007816: 693b ldr r3, [r7, #16] 8007818: 43db mvns r3, r3 800781a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800781e: 4013 ands r3, r2 8007820: 600b str r3, [r1, #0] } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 8007822: 687b ldr r3, [r7, #4] 8007824: 6a1b ldr r3, [r3, #32] 8007826: f003 0320 and.w r3, r3, #32 800782a: 2b00 cmp r3, #0 800782c: d008 beq.n 8007840 { SET_BIT(EXTI->FTSR1, exti_line); 800782e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007832: 685a ldr r2, [r3, #4] 8007834: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007838: 693b ldr r3, [r7, #16] 800783a: 4313 orrs r3, r2 800783c: 604b str r3, [r1, #4] 800783e: e008 b.n 8007852 } else { CLEAR_BIT(EXTI->FTSR1, exti_line); 8007840: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007844: 685a ldr r2, [r3, #4] 8007846: 693b ldr r3, [r7, #16] 8007848: 43db mvns r3, r3 800784a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800784e: 4013 ands r3, r2 8007850: 604b str r3, [r1, #4] } #if !defined (CORE_CM4) /* Clear COMP EXTI pending bit (if any) */ WRITE_REG(EXTI->PR1, exti_line); 8007852: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 8007856: 693b ldr r3, [r7, #16] 8007858: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 800785c: 687b ldr r3, [r7, #4] 800785e: 6a1b ldr r3, [r3, #32] 8007860: f003 0302 and.w r3, r3, #2 8007864: 2b00 cmp r3, #0 8007866: d00a beq.n 800787e { SET_BIT(EXTI->EMR1, exti_line); 8007868: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800786c: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8007870: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007874: 693b ldr r3, [r7, #16] 8007876: 4313 orrs r3, r2 8007878: f8c1 3084 str.w r3, [r1, #132] @ 0x84 800787c: e00a b.n 8007894 } else { CLEAR_BIT(EXTI->EMR1, exti_line); 800787e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007882: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8007886: 693b ldr r3, [r7, #16] 8007888: 43db mvns r3, r3 800788a: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800788e: 4013 ands r3, r2 8007890: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 8007894: 687b ldr r3, [r7, #4] 8007896: 6a1b ldr r3, [r3, #32] 8007898: f003 0301 and.w r3, r3, #1 800789c: 2b00 cmp r3, #0 800789e: d00a beq.n 80078b6 { SET_BIT(EXTI->IMR1, exti_line); 80078a0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078a4: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 80078a8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078ac: 693b ldr r3, [r7, #16] 80078ae: 4313 orrs r3, r2 80078b0: f8c1 3080 str.w r3, [r1, #128] @ 0x80 80078b4: e021 b.n 80078fa } else { CLEAR_BIT(EXTI->IMR1, exti_line); 80078b6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078ba: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 80078be: 693b ldr r3, [r7, #16] 80078c0: 43db mvns r3, r3 80078c2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078c6: 4013 ands r3, r2 80078c8: f8c1 3080 str.w r3, [r1, #128] @ 0x80 80078cc: e015 b.n 80078fa } } else { /* Disable EXTI event mode */ CLEAR_BIT(EXTI->EMR1, exti_line); 80078ce: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078d2: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 80078d6: 693b ldr r3, [r7, #16] 80078d8: 43db mvns r3, r3 80078da: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078de: 4013 ands r3, r2 80078e0: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* Disable EXTI interrupt mode */ CLEAR_BIT(EXTI->IMR1, exti_line); 80078e4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078e8: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 80078ec: 693b ldr r3, [r7, #16] 80078ee: 43db mvns r3, r3 80078f0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078f4: 4013 ands r3, r2 80078f6: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } #endif /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ if (hcomp->State == HAL_COMP_STATE_RESET) 80078fa: 687b ldr r3, [r7, #4] 80078fc: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007900: b2db uxtb r3, r3 8007902: 2b00 cmp r3, #0 8007904: d103 bne.n 800790e { hcomp->State = HAL_COMP_STATE_READY; 8007906: 687b ldr r3, [r7, #4] 8007908: 2201 movs r2, #1 800790a: f883 2025 strb.w r2, [r3, #37] @ 0x25 } } return status; 800790e: 7ffb ldrb r3, [r7, #31] } 8007910: 4618 mov r0, r3 8007912: 3720 adds r7, #32 8007914: 46bd mov sp, r7 8007916: bd80 pop {r7, pc} 8007918: f0e8cce1 .word 0xf0e8cce1 800791c: 24000034 .word 0x24000034 8007920: 053e2d63 .word 0x053e2d63 8007924: 5800380c .word 0x5800380c 08007928 : * @brief Start the comparator. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { 8007928: b480 push {r7} 800792a: b085 sub sp, #20 800792c: af00 add r7, sp, #0 800792e: 6078 str r0, [r7, #4] __IO uint32_t wait_loop_index = 0UL; 8007930: 2300 movs r3, #0 8007932: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 8007934: 2300 movs r3, #0 8007936: 73fb strb r3, [r7, #15] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8007938: 687b ldr r3, [r7, #4] 800793a: 2b00 cmp r3, #0 800793c: d102 bne.n 8007944 { status = HAL_ERROR; 800793e: 2301 movs r3, #1 8007940: 73fb strb r3, [r7, #15] 8007942: e030 b.n 80079a6 } else if(__HAL_COMP_IS_LOCKED(hcomp)) 8007944: 687b ldr r3, [r7, #4] 8007946: 681b ldr r3, [r3, #0] 8007948: 681b ldr r3, [r3, #0] 800794a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800794e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007952: d102 bne.n 800795a { status = HAL_ERROR; 8007954: 2301 movs r3, #1 8007956: 73fb strb r3, [r7, #15] 8007958: e025 b.n 80079a6 else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if(hcomp->State == HAL_COMP_STATE_READY) 800795a: 687b ldr r3, [r7, #4] 800795c: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007960: b2db uxtb r3, r3 8007962: 2b01 cmp r3, #1 8007964: d11d bne.n 80079a2 { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 8007966: 687b ldr r3, [r7, #4] 8007968: 681b ldr r3, [r3, #0] 800796a: 681a ldr r2, [r3, #0] 800796c: 687b ldr r3, [r7, #4] 800796e: 681b ldr r3, [r3, #0] 8007970: f042 0201 orr.w r2, r2, #1 8007974: 601a str r2, [r3, #0] /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; 8007976: 687b ldr r3, [r7, #4] 8007978: 2202 movs r2, #2 800797a: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Delay for COMP startup time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 800797e: 4b0d ldr r3, [pc, #52] @ (80079b4 ) 8007980: 681b ldr r3, [r3, #0] 8007982: 099b lsrs r3, r3, #6 8007984: 4a0c ldr r2, [pc, #48] @ (80079b8 ) 8007986: fba2 2303 umull r2, r3, r2, r3 800798a: 099b lsrs r3, r3, #6 800798c: 3301 adds r3, #1 800798e: 00db lsls r3, r3, #3 8007990: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 8007992: e002 b.n 800799a { wait_loop_index--; 8007994: 68bb ldr r3, [r7, #8] 8007996: 3b01 subs r3, #1 8007998: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 800799a: 68bb ldr r3, [r7, #8] 800799c: 2b00 cmp r3, #0 800799e: d1f9 bne.n 8007994 80079a0: e001 b.n 80079a6 } } else { status = HAL_ERROR; 80079a2: 2301 movs r3, #1 80079a4: 73fb strb r3, [r7, #15] } } return status; 80079a6: 7bfb ldrb r3, [r7, #15] } 80079a8: 4618 mov r0, r3 80079aa: 3714 adds r7, #20 80079ac: 46bd mov sp, r7 80079ae: f85d 7b04 ldr.w r7, [sp], #4 80079b2: 4770 bx lr 80079b4: 24000034 .word 0x24000034 80079b8: 053e2d63 .word 0x053e2d63 080079bc : * @arg @ref COMP_OUTPUT_LEVEL_LOW * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { 80079bc: b480 push {r7} 80079be: b083 sub sp, #12 80079c0: af00 add r7, sp, #0 80079c2: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if (hcomp->Instance == COMP1) 80079c4: 687b ldr r3, [r7, #4] 80079c6: 681b ldr r3, [r3, #0] 80079c8: 4a09 ldr r2, [pc, #36] @ (80079f0 ) 80079ca: 4293 cmp r3, r2 80079cc: d104 bne.n 80079d8 { return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); 80079ce: 4b09 ldr r3, [pc, #36] @ (80079f4 ) 80079d0: 681b ldr r3, [r3, #0] 80079d2: f003 0301 and.w r3, r3, #1 80079d6: e004 b.n 80079e2 } else { return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL); 80079d8: 4b06 ldr r3, [pc, #24] @ (80079f4 ) 80079da: 681b ldr r3, [r3, #0] 80079dc: 085b lsrs r3, r3, #1 80079de: f003 0301 and.w r3, r3, #1 } } 80079e2: 4618 mov r0, r3 80079e4: 370c adds r7, #12 80079e6: 46bd mov sp, r7 80079e8: f85d 7b04 ldr.w r7, [sp], #4 80079ec: 4770 bx lr 80079ee: bf00 nop 80079f0: 5800380c .word 0x5800380c 80079f4: 58003800 .word 0x58003800 080079f8 <__NVIC_SetPriorityGrouping>: { 80079f8: b480 push {r7} 80079fa: b085 sub sp, #20 80079fc: af00 add r7, sp, #0 80079fe: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007a00: 687b ldr r3, [r7, #4] 8007a02: f003 0307 and.w r3, r3, #7 8007a06: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8007a08: 4b0b ldr r3, [pc, #44] @ (8007a38 <__NVIC_SetPriorityGrouping+0x40>) 8007a0a: 68db ldr r3, [r3, #12] 8007a0c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8007a0e: 68ba ldr r2, [r7, #8] 8007a10: f64f 03ff movw r3, #63743 @ 0xf8ff 8007a14: 4013 ands r3, r2 8007a16: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8007a18: 68fb ldr r3, [r7, #12] 8007a1a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8007a1c: 68bb ldr r3, [r7, #8] 8007a1e: 431a orrs r2, r3 reg_value = (reg_value | 8007a20: 4b06 ldr r3, [pc, #24] @ (8007a3c <__NVIC_SetPriorityGrouping+0x44>) 8007a22: 4313 orrs r3, r2 8007a24: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8007a26: 4a04 ldr r2, [pc, #16] @ (8007a38 <__NVIC_SetPriorityGrouping+0x40>) 8007a28: 68bb ldr r3, [r7, #8] 8007a2a: 60d3 str r3, [r2, #12] } 8007a2c: bf00 nop 8007a2e: 3714 adds r7, #20 8007a30: 46bd mov sp, r7 8007a32: f85d 7b04 ldr.w r7, [sp], #4 8007a36: 4770 bx lr 8007a38: e000ed00 .word 0xe000ed00 8007a3c: 05fa0000 .word 0x05fa0000 08007a40 <__NVIC_GetPriorityGrouping>: { 8007a40: b480 push {r7} 8007a42: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8007a44: 4b04 ldr r3, [pc, #16] @ (8007a58 <__NVIC_GetPriorityGrouping+0x18>) 8007a46: 68db ldr r3, [r3, #12] 8007a48: 0a1b lsrs r3, r3, #8 8007a4a: f003 0307 and.w r3, r3, #7 } 8007a4e: 4618 mov r0, r3 8007a50: 46bd mov sp, r7 8007a52: f85d 7b04 ldr.w r7, [sp], #4 8007a56: 4770 bx lr 8007a58: e000ed00 .word 0xe000ed00 08007a5c <__NVIC_EnableIRQ>: { 8007a5c: b480 push {r7} 8007a5e: b083 sub sp, #12 8007a60: af00 add r7, sp, #0 8007a62: 4603 mov r3, r0 8007a64: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007a66: f9b7 3006 ldrsh.w r3, [r7, #6] 8007a6a: 2b00 cmp r3, #0 8007a6c: db0b blt.n 8007a86 <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8007a6e: 88fb ldrh r3, [r7, #6] 8007a70: f003 021f and.w r2, r3, #31 8007a74: 4907 ldr r1, [pc, #28] @ (8007a94 <__NVIC_EnableIRQ+0x38>) 8007a76: f9b7 3006 ldrsh.w r3, [r7, #6] 8007a7a: 095b lsrs r3, r3, #5 8007a7c: 2001 movs r0, #1 8007a7e: fa00 f202 lsl.w r2, r0, r2 8007a82: f841 2023 str.w r2, [r1, r3, lsl #2] } 8007a86: bf00 nop 8007a88: 370c adds r7, #12 8007a8a: 46bd mov sp, r7 8007a8c: f85d 7b04 ldr.w r7, [sp], #4 8007a90: 4770 bx lr 8007a92: bf00 nop 8007a94: e000e100 .word 0xe000e100 08007a98 <__NVIC_SetPriority>: { 8007a98: b480 push {r7} 8007a9a: b083 sub sp, #12 8007a9c: af00 add r7, sp, #0 8007a9e: 4603 mov r3, r0 8007aa0: 6039 str r1, [r7, #0] 8007aa2: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007aa4: f9b7 3006 ldrsh.w r3, [r7, #6] 8007aa8: 2b00 cmp r3, #0 8007aaa: db0a blt.n 8007ac2 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007aac: 683b ldr r3, [r7, #0] 8007aae: b2da uxtb r2, r3 8007ab0: 490c ldr r1, [pc, #48] @ (8007ae4 <__NVIC_SetPriority+0x4c>) 8007ab2: f9b7 3006 ldrsh.w r3, [r7, #6] 8007ab6: 0112 lsls r2, r2, #4 8007ab8: b2d2 uxtb r2, r2 8007aba: 440b add r3, r1 8007abc: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8007ac0: e00a b.n 8007ad8 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007ac2: 683b ldr r3, [r7, #0] 8007ac4: b2da uxtb r2, r3 8007ac6: 4908 ldr r1, [pc, #32] @ (8007ae8 <__NVIC_SetPriority+0x50>) 8007ac8: 88fb ldrh r3, [r7, #6] 8007aca: f003 030f and.w r3, r3, #15 8007ace: 3b04 subs r3, #4 8007ad0: 0112 lsls r2, r2, #4 8007ad2: b2d2 uxtb r2, r2 8007ad4: 440b add r3, r1 8007ad6: 761a strb r2, [r3, #24] } 8007ad8: bf00 nop 8007ada: 370c adds r7, #12 8007adc: 46bd mov sp, r7 8007ade: f85d 7b04 ldr.w r7, [sp], #4 8007ae2: 4770 bx lr 8007ae4: e000e100 .word 0xe000e100 8007ae8: e000ed00 .word 0xe000ed00 08007aec : { 8007aec: b480 push {r7} 8007aee: b089 sub sp, #36 @ 0x24 8007af0: af00 add r7, sp, #0 8007af2: 60f8 str r0, [r7, #12] 8007af4: 60b9 str r1, [r7, #8] 8007af6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007af8: 68fb ldr r3, [r7, #12] 8007afa: f003 0307 and.w r3, r3, #7 8007afe: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8007b00: 69fb ldr r3, [r7, #28] 8007b02: f1c3 0307 rsb r3, r3, #7 8007b06: 2b04 cmp r3, #4 8007b08: bf28 it cs 8007b0a: 2304 movcs r3, #4 8007b0c: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8007b0e: 69fb ldr r3, [r7, #28] 8007b10: 3304 adds r3, #4 8007b12: 2b06 cmp r3, #6 8007b14: d902 bls.n 8007b1c 8007b16: 69fb ldr r3, [r7, #28] 8007b18: 3b03 subs r3, #3 8007b1a: e000 b.n 8007b1e 8007b1c: 2300 movs r3, #0 8007b1e: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007b20: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007b24: 69bb ldr r3, [r7, #24] 8007b26: fa02 f303 lsl.w r3, r2, r3 8007b2a: 43da mvns r2, r3 8007b2c: 68bb ldr r3, [r7, #8] 8007b2e: 401a ands r2, r3 8007b30: 697b ldr r3, [r7, #20] 8007b32: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8007b34: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8007b38: 697b ldr r3, [r7, #20] 8007b3a: fa01 f303 lsl.w r3, r1, r3 8007b3e: 43d9 mvns r1, r3 8007b40: 687b ldr r3, [r7, #4] 8007b42: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007b44: 4313 orrs r3, r2 } 8007b46: 4618 mov r0, r3 8007b48: 3724 adds r7, #36 @ 0x24 8007b4a: 46bd mov sp, r7 8007b4c: f85d 7b04 ldr.w r7, [sp], #4 8007b50: 4770 bx lr 08007b52 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8007b52: b580 push {r7, lr} 8007b54: b082 sub sp, #8 8007b56: af00 add r7, sp, #0 8007b58: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8007b5a: 6878 ldr r0, [r7, #4] 8007b5c: f7ff ff4c bl 80079f8 <__NVIC_SetPriorityGrouping> } 8007b60: bf00 nop 8007b62: 3708 adds r7, #8 8007b64: 46bd mov sp, r7 8007b66: bd80 pop {r7, pc} 08007b68 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8007b68: b580 push {r7, lr} 8007b6a: b086 sub sp, #24 8007b6c: af00 add r7, sp, #0 8007b6e: 4603 mov r3, r0 8007b70: 60b9 str r1, [r7, #8] 8007b72: 607a str r2, [r7, #4] 8007b74: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8007b76: f7ff ff63 bl 8007a40 <__NVIC_GetPriorityGrouping> 8007b7a: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8007b7c: 687a ldr r2, [r7, #4] 8007b7e: 68b9 ldr r1, [r7, #8] 8007b80: 6978 ldr r0, [r7, #20] 8007b82: f7ff ffb3 bl 8007aec 8007b86: 4602 mov r2, r0 8007b88: f9b7 300e ldrsh.w r3, [r7, #14] 8007b8c: 4611 mov r1, r2 8007b8e: 4618 mov r0, r3 8007b90: f7ff ff82 bl 8007a98 <__NVIC_SetPriority> } 8007b94: bf00 nop 8007b96: 3718 adds r7, #24 8007b98: 46bd mov sp, r7 8007b9a: bd80 pop {r7, pc} 08007b9c : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8007b9c: b580 push {r7, lr} 8007b9e: b082 sub sp, #8 8007ba0: af00 add r7, sp, #0 8007ba2: 4603 mov r3, r0 8007ba4: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8007ba6: f9b7 3006 ldrsh.w r3, [r7, #6] 8007baa: 4618 mov r0, r3 8007bac: f7ff ff56 bl 8007a5c <__NVIC_EnableIRQ> } 8007bb0: bf00 nop 8007bb2: 3708 adds r7, #8 8007bb4: 46bd mov sp, r7 8007bb6: bd80 pop {r7, pc} 08007bb8 : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 8007bb8: b480 push {r7} 8007bba: af00 add r7, sp, #0 __ASM volatile ("dmb 0xF":::"memory"); 8007bbc: f3bf 8f5f dmb sy } 8007bc0: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8007bc2: 4b07 ldr r3, [pc, #28] @ (8007be0 ) 8007bc4: 6a5b ldr r3, [r3, #36] @ 0x24 8007bc6: 4a06 ldr r2, [pc, #24] @ (8007be0 ) 8007bc8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007bcc: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 8007bce: 4b05 ldr r3, [pc, #20] @ (8007be4 ) 8007bd0: 2200 movs r2, #0 8007bd2: 605a str r2, [r3, #4] } 8007bd4: bf00 nop 8007bd6: 46bd mov sp, r7 8007bd8: f85d 7b04 ldr.w r7, [sp], #4 8007bdc: 4770 bx lr 8007bde: bf00 nop 8007be0: e000ed00 .word 0xe000ed00 8007be4: e000ed90 .word 0xe000ed90 08007be8 : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 8007be8: b480 push {r7} 8007bea: b083 sub sp, #12 8007bec: af00 add r7, sp, #0 8007bee: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8007bf0: 4a0b ldr r2, [pc, #44] @ (8007c20 ) 8007bf2: 687b ldr r3, [r7, #4] 8007bf4: f043 0301 orr.w r3, r3, #1 8007bf8: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 8007bfa: 4b0a ldr r3, [pc, #40] @ (8007c24 ) 8007bfc: 6a5b ldr r3, [r3, #36] @ 0x24 8007bfe: 4a09 ldr r2, [pc, #36] @ (8007c24 ) 8007c00: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007c04: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 8007c06: f3bf 8f4f dsb sy } 8007c0a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8007c0c: f3bf 8f6f isb sy } 8007c10: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8007c12: bf00 nop 8007c14: 370c adds r7, #12 8007c16: 46bd mov sp, r7 8007c18: f85d 7b04 ldr.w r7, [sp], #4 8007c1c: 4770 bx lr 8007c1e: bf00 nop 8007c20: e000ed90 .word 0xe000ed90 8007c24: e000ed00 .word 0xe000ed00 08007c28 : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 8007c28: b480 push {r7} 8007c2a: b083 sub sp, #12 8007c2c: af00 add r7, sp, #0 8007c2e: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8007c30: 687b ldr r3, [r7, #4] 8007c32: 785a ldrb r2, [r3, #1] 8007c34: 4b1b ldr r3, [pc, #108] @ (8007ca4 ) 8007c36: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 8007c38: 4b1a ldr r3, [pc, #104] @ (8007ca4 ) 8007c3a: 691b ldr r3, [r3, #16] 8007c3c: 4a19 ldr r2, [pc, #100] @ (8007ca4 ) 8007c3e: f023 0301 bic.w r3, r3, #1 8007c42: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 8007c44: 4a17 ldr r2, [pc, #92] @ (8007ca4 ) 8007c46: 687b ldr r3, [r7, #4] 8007c48: 685b ldr r3, [r3, #4] 8007c4a: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c4c: 687b ldr r3, [r7, #4] 8007c4e: 7b1b ldrb r3, [r3, #12] 8007c50: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007c52: 687b ldr r3, [r7, #4] 8007c54: 7adb ldrb r3, [r3, #11] 8007c56: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c58: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007c5a: 687b ldr r3, [r7, #4] 8007c5c: 7a9b ldrb r3, [r3, #10] 8007c5e: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007c60: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007c62: 687b ldr r3, [r7, #4] 8007c64: 7b5b ldrb r3, [r3, #13] 8007c66: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007c68: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007c6a: 687b ldr r3, [r7, #4] 8007c6c: 7b9b ldrb r3, [r3, #14] 8007c6e: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007c70: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007c72: 687b ldr r3, [r7, #4] 8007c74: 7bdb ldrb r3, [r3, #15] 8007c76: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007c78: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007c7a: 687b ldr r3, [r7, #4] 8007c7c: 7a5b ldrb r3, [r3, #9] 8007c7e: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007c80: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007c82: 687b ldr r3, [r7, #4] 8007c84: 7a1b ldrb r3, [r3, #8] 8007c86: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007c88: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 8007c8a: 687a ldr r2, [r7, #4] 8007c8c: 7812 ldrb r2, [r2, #0] 8007c8e: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c90: 4a04 ldr r2, [pc, #16] @ (8007ca4 ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007c92: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c94: 6113 str r3, [r2, #16] } 8007c96: bf00 nop 8007c98: 370c adds r7, #12 8007c9a: 46bd mov sp, r7 8007c9c: f85d 7b04 ldr.w r7, [sp], #4 8007ca0: 4770 bx lr 8007ca2: bf00 nop 8007ca4: e000ed90 .word 0xe000ed90 08007ca8 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 8007ca8: b580 push {r7, lr} 8007caa: b082 sub sp, #8 8007cac: af00 add r7, sp, #0 8007cae: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8007cb0: 687b ldr r3, [r7, #4] 8007cb2: 2b00 cmp r3, #0 8007cb4: d101 bne.n 8007cba { return HAL_ERROR; 8007cb6: 2301 movs r3, #1 8007cb8: e054 b.n 8007d64 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 8007cba: 687b ldr r3, [r7, #4] 8007cbc: 7f5b ldrb r3, [r3, #29] 8007cbe: b2db uxtb r3, r3 8007cc0: 2b00 cmp r3, #0 8007cc2: d105 bne.n 8007cd0 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8007cc4: 687b ldr r3, [r7, #4] 8007cc6: 2200 movs r2, #0 8007cc8: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 8007cca: 6878 ldr r0, [r7, #4] 8007ccc: f7fc fa1a bl 8004104 } hcrc->State = HAL_CRC_STATE_BUSY; 8007cd0: 687b ldr r3, [r7, #4] 8007cd2: 2202 movs r2, #2 8007cd4: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 8007cd6: 687b ldr r3, [r7, #4] 8007cd8: 791b ldrb r3, [r3, #4] 8007cda: 2b00 cmp r3, #0 8007cdc: d10c bne.n 8007cf8 { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 8007cde: 687b ldr r3, [r7, #4] 8007ce0: 681b ldr r3, [r3, #0] 8007ce2: 4a22 ldr r2, [pc, #136] @ (8007d6c ) 8007ce4: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 8007ce6: 687b ldr r3, [r7, #4] 8007ce8: 681b ldr r3, [r3, #0] 8007cea: 689a ldr r2, [r3, #8] 8007cec: 687b ldr r3, [r7, #4] 8007cee: 681b ldr r3, [r3, #0] 8007cf0: f022 0218 bic.w r2, r2, #24 8007cf4: 609a str r2, [r3, #8] 8007cf6: e00c b.n 8007d12 } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 8007cf8: 687b ldr r3, [r7, #4] 8007cfa: 6899 ldr r1, [r3, #8] 8007cfc: 687b ldr r3, [r7, #4] 8007cfe: 68db ldr r3, [r3, #12] 8007d00: 461a mov r2, r3 8007d02: 6878 ldr r0, [r7, #4] 8007d04: f000 f948 bl 8007f98 8007d08: 4603 mov r3, r0 8007d0a: 2b00 cmp r3, #0 8007d0c: d001 beq.n 8007d12 { return HAL_ERROR; 8007d0e: 2301 movs r3, #1 8007d10: e028 b.n 8007d64 } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 8007d12: 687b ldr r3, [r7, #4] 8007d14: 795b ldrb r3, [r3, #5] 8007d16: 2b00 cmp r3, #0 8007d18: d105 bne.n 8007d26 { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 8007d1a: 687b ldr r3, [r7, #4] 8007d1c: 681b ldr r3, [r3, #0] 8007d1e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007d22: 611a str r2, [r3, #16] 8007d24: e004 b.n 8007d30 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 8007d26: 687b ldr r3, [r7, #4] 8007d28: 681b ldr r3, [r3, #0] 8007d2a: 687a ldr r2, [r7, #4] 8007d2c: 6912 ldr r2, [r2, #16] 8007d2e: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8007d30: 687b ldr r3, [r7, #4] 8007d32: 681b ldr r3, [r3, #0] 8007d34: 689b ldr r3, [r3, #8] 8007d36: f023 0160 bic.w r1, r3, #96 @ 0x60 8007d3a: 687b ldr r3, [r7, #4] 8007d3c: 695a ldr r2, [r3, #20] 8007d3e: 687b ldr r3, [r7, #4] 8007d40: 681b ldr r3, [r3, #0] 8007d42: 430a orrs r2, r1 8007d44: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 8007d46: 687b ldr r3, [r7, #4] 8007d48: 681b ldr r3, [r3, #0] 8007d4a: 689b ldr r3, [r3, #8] 8007d4c: f023 0180 bic.w r1, r3, #128 @ 0x80 8007d50: 687b ldr r3, [r7, #4] 8007d52: 699a ldr r2, [r3, #24] 8007d54: 687b ldr r3, [r7, #4] 8007d56: 681b ldr r3, [r3, #0] 8007d58: 430a orrs r2, r1 8007d5a: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007d5c: 687b ldr r3, [r7, #4] 8007d5e: 2201 movs r2, #1 8007d60: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 8007d62: 2300 movs r3, #0 } 8007d64: 4618 mov r0, r3 8007d66: 3708 adds r7, #8 8007d68: 46bd mov sp, r7 8007d6a: bd80 pop {r7, pc} 8007d6c: 04c11db7 .word 0x04c11db7 08007d70 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 8007d70: b580 push {r7, lr} 8007d72: b086 sub sp, #24 8007d74: af00 add r7, sp, #0 8007d76: 60f8 str r0, [r7, #12] 8007d78: 60b9 str r1, [r7, #8] 8007d7a: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 8007d7c: 2300 movs r3, #0 8007d7e: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 8007d80: 68fb ldr r3, [r7, #12] 8007d82: 2202 movs r2, #2 8007d84: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 8007d86: 68fb ldr r3, [r7, #12] 8007d88: 681b ldr r3, [r3, #0] 8007d8a: 689a ldr r2, [r3, #8] 8007d8c: 68fb ldr r3, [r7, #12] 8007d8e: 681b ldr r3, [r3, #0] 8007d90: f042 0201 orr.w r2, r2, #1 8007d94: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 8007d96: 68fb ldr r3, [r7, #12] 8007d98: 6a1b ldr r3, [r3, #32] 8007d9a: 2b03 cmp r3, #3 8007d9c: d006 beq.n 8007dac 8007d9e: 2b03 cmp r3, #3 8007da0: d829 bhi.n 8007df6 8007da2: 2b01 cmp r3, #1 8007da4: d019 beq.n 8007dda 8007da6: 2b02 cmp r3, #2 8007da8: d01e beq.n 8007de8 /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 8007daa: e024 b.n 8007df6 for (index = 0U; index < BufferLength; index++) 8007dac: 2300 movs r3, #0 8007dae: 617b str r3, [r7, #20] 8007db0: e00a b.n 8007dc8 hcrc->Instance->DR = pBuffer[index]; 8007db2: 697b ldr r3, [r7, #20] 8007db4: 009b lsls r3, r3, #2 8007db6: 68ba ldr r2, [r7, #8] 8007db8: 441a add r2, r3 8007dba: 68fb ldr r3, [r7, #12] 8007dbc: 681b ldr r3, [r3, #0] 8007dbe: 6812 ldr r2, [r2, #0] 8007dc0: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 8007dc2: 697b ldr r3, [r7, #20] 8007dc4: 3301 adds r3, #1 8007dc6: 617b str r3, [r7, #20] 8007dc8: 697a ldr r2, [r7, #20] 8007dca: 687b ldr r3, [r7, #4] 8007dcc: 429a cmp r2, r3 8007dce: d3f0 bcc.n 8007db2 temp = hcrc->Instance->DR; 8007dd0: 68fb ldr r3, [r7, #12] 8007dd2: 681b ldr r3, [r3, #0] 8007dd4: 681b ldr r3, [r3, #0] 8007dd6: 613b str r3, [r7, #16] break; 8007dd8: e00e b.n 8007df8 temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 8007dda: 687a ldr r2, [r7, #4] 8007ddc: 68b9 ldr r1, [r7, #8] 8007dde: 68f8 ldr r0, [r7, #12] 8007de0: f000 f812 bl 8007e08 8007de4: 6138 str r0, [r7, #16] break; 8007de6: e007 b.n 8007df8 temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 8007de8: 687a ldr r2, [r7, #4] 8007dea: 68b9 ldr r1, [r7, #8] 8007dec: 68f8 ldr r0, [r7, #12] 8007dee: f000 f899 bl 8007f24 8007df2: 6138 str r0, [r7, #16] break; 8007df4: e000 b.n 8007df8 break; 8007df6: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007df8: 68fb ldr r3, [r7, #12] 8007dfa: 2201 movs r2, #1 8007dfc: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 8007dfe: 693b ldr r3, [r7, #16] } 8007e00: 4618 mov r0, r3 8007e02: 3718 adds r7, #24 8007e04: 46bd mov sp, r7 8007e06: bd80 pop {r7, pc} 08007e08 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 8007e08: b480 push {r7} 8007e0a: b089 sub sp, #36 @ 0x24 8007e0c: af00 add r7, sp, #0 8007e0e: 60f8 str r0, [r7, #12] 8007e10: 60b9 str r1, [r7, #8] 8007e12: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 8007e14: 2300 movs r3, #0 8007e16: 61fb str r3, [r7, #28] 8007e18: e023 b.n 8007e62 { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e1a: 69fb ldr r3, [r7, #28] 8007e1c: 009b lsls r3, r3, #2 8007e1e: 68ba ldr r2, [r7, #8] 8007e20: 4413 add r3, r2 8007e22: 781b ldrb r3, [r3, #0] 8007e24: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007e26: 69fb ldr r3, [r7, #28] 8007e28: 009b lsls r3, r3, #2 8007e2a: 3301 adds r3, #1 8007e2c: 68b9 ldr r1, [r7, #8] 8007e2e: 440b add r3, r1 8007e30: 781b ldrb r3, [r3, #0] 8007e32: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e34: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007e36: 69fb ldr r3, [r7, #28] 8007e38: 009b lsls r3, r3, #2 8007e3a: 3302 adds r3, #2 8007e3c: 68b9 ldr r1, [r7, #8] 8007e3e: 440b add r3, r1 8007e40: 781b ldrb r3, [r3, #0] 8007e42: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007e44: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 8007e46: 69fb ldr r3, [r7, #28] 8007e48: 009b lsls r3, r3, #2 8007e4a: 3303 adds r3, #3 8007e4c: 68b9 ldr r1, [r7, #8] 8007e4e: 440b add r3, r1 8007e50: 781b ldrb r3, [r3, #0] 8007e52: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e54: 68fb ldr r3, [r7, #12] 8007e56: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007e58: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e5a: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8007e5c: 69fb ldr r3, [r7, #28] 8007e5e: 3301 adds r3, #1 8007e60: 61fb str r3, [r7, #28] 8007e62: 687b ldr r3, [r7, #4] 8007e64: 089b lsrs r3, r3, #2 8007e66: 69fa ldr r2, [r7, #28] 8007e68: 429a cmp r2, r3 8007e6a: d3d6 bcc.n 8007e1a } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 8007e6c: 687b ldr r3, [r7, #4] 8007e6e: f003 0303 and.w r3, r3, #3 8007e72: 2b00 cmp r3, #0 8007e74: d04d beq.n 8007f12 { if ((BufferLength % 4U) == 1U) 8007e76: 687b ldr r3, [r7, #4] 8007e78: f003 0303 and.w r3, r3, #3 8007e7c: 2b01 cmp r3, #1 8007e7e: d107 bne.n 8007e90 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 8007e80: 69fb ldr r3, [r7, #28] 8007e82: 009b lsls r3, r3, #2 8007e84: 68ba ldr r2, [r7, #8] 8007e86: 4413 add r3, r2 8007e88: 68fa ldr r2, [r7, #12] 8007e8a: 6812 ldr r2, [r2, #0] 8007e8c: 781b ldrb r3, [r3, #0] 8007e8e: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 8007e90: 687b ldr r3, [r7, #4] 8007e92: f003 0303 and.w r3, r3, #3 8007e96: 2b02 cmp r3, #2 8007e98: d116 bne.n 8007ec8 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007e9a: 69fb ldr r3, [r7, #28] 8007e9c: 009b lsls r3, r3, #2 8007e9e: 68ba ldr r2, [r7, #8] 8007ea0: 4413 add r3, r2 8007ea2: 781b ldrb r3, [r3, #0] 8007ea4: 021b lsls r3, r3, #8 8007ea6: b21a sxth r2, r3 8007ea8: 69fb ldr r3, [r7, #28] 8007eaa: 009b lsls r3, r3, #2 8007eac: 3301 adds r3, #1 8007eae: 68b9 ldr r1, [r7, #8] 8007eb0: 440b add r3, r1 8007eb2: 781b ldrb r3, [r3, #0] 8007eb4: b21b sxth r3, r3 8007eb6: 4313 orrs r3, r2 8007eb8: b21b sxth r3, r3 8007eba: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007ebc: 68fb ldr r3, [r7, #12] 8007ebe: 681b ldr r3, [r3, #0] 8007ec0: 617b str r3, [r7, #20] *pReg = data; 8007ec2: 697b ldr r3, [r7, #20] 8007ec4: 8b7a ldrh r2, [r7, #26] 8007ec6: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 8007ec8: 687b ldr r3, [r7, #4] 8007eca: f003 0303 and.w r3, r3, #3 8007ece: 2b03 cmp r3, #3 8007ed0: d11f bne.n 8007f12 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007ed2: 69fb ldr r3, [r7, #28] 8007ed4: 009b lsls r3, r3, #2 8007ed6: 68ba ldr r2, [r7, #8] 8007ed8: 4413 add r3, r2 8007eda: 781b ldrb r3, [r3, #0] 8007edc: 021b lsls r3, r3, #8 8007ede: b21a sxth r2, r3 8007ee0: 69fb ldr r3, [r7, #28] 8007ee2: 009b lsls r3, r3, #2 8007ee4: 3301 adds r3, #1 8007ee6: 68b9 ldr r1, [r7, #8] 8007ee8: 440b add r3, r1 8007eea: 781b ldrb r3, [r3, #0] 8007eec: b21b sxth r3, r3 8007eee: 4313 orrs r3, r2 8007ef0: b21b sxth r3, r3 8007ef2: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007ef4: 68fb ldr r3, [r7, #12] 8007ef6: 681b ldr r3, [r3, #0] 8007ef8: 617b str r3, [r7, #20] *pReg = data; 8007efa: 697b ldr r3, [r7, #20] 8007efc: 8b7a ldrh r2, [r7, #26] 8007efe: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 8007f00: 69fb ldr r3, [r7, #28] 8007f02: 009b lsls r3, r3, #2 8007f04: 3302 adds r3, #2 8007f06: 68ba ldr r2, [r7, #8] 8007f08: 4413 add r3, r2 8007f0a: 68fa ldr r2, [r7, #12] 8007f0c: 6812 ldr r2, [r2, #0] 8007f0e: 781b ldrb r3, [r3, #0] 8007f10: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007f12: 68fb ldr r3, [r7, #12] 8007f14: 681b ldr r3, [r3, #0] 8007f16: 681b ldr r3, [r3, #0] } 8007f18: 4618 mov r0, r3 8007f1a: 3724 adds r7, #36 @ 0x24 8007f1c: 46bd mov sp, r7 8007f1e: f85d 7b04 ldr.w r7, [sp], #4 8007f22: 4770 bx lr 08007f24 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 8007f24: b480 push {r7} 8007f26: b087 sub sp, #28 8007f28: af00 add r7, sp, #0 8007f2a: 60f8 str r0, [r7, #12] 8007f2c: 60b9 str r1, [r7, #8] 8007f2e: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8007f30: 2300 movs r3, #0 8007f32: 617b str r3, [r7, #20] 8007f34: e013 b.n 8007f5e { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 8007f36: 697b ldr r3, [r7, #20] 8007f38: 009b lsls r3, r3, #2 8007f3a: 68ba ldr r2, [r7, #8] 8007f3c: 4413 add r3, r2 8007f3e: 881b ldrh r3, [r3, #0] 8007f40: 041a lsls r2, r3, #16 8007f42: 697b ldr r3, [r7, #20] 8007f44: 009b lsls r3, r3, #2 8007f46: 3302 adds r3, #2 8007f48: 68b9 ldr r1, [r7, #8] 8007f4a: 440b add r3, r1 8007f4c: 881b ldrh r3, [r3, #0] 8007f4e: 4619 mov r1, r3 8007f50: 68fb ldr r3, [r7, #12] 8007f52: 681b ldr r3, [r3, #0] 8007f54: 430a orrs r2, r1 8007f56: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 8007f58: 697b ldr r3, [r7, #20] 8007f5a: 3301 adds r3, #1 8007f5c: 617b str r3, [r7, #20] 8007f5e: 687b ldr r3, [r7, #4] 8007f60: 085b lsrs r3, r3, #1 8007f62: 697a ldr r2, [r7, #20] 8007f64: 429a cmp r2, r3 8007f66: d3e6 bcc.n 8007f36 } if ((BufferLength % 2U) != 0U) 8007f68: 687b ldr r3, [r7, #4] 8007f6a: f003 0301 and.w r3, r3, #1 8007f6e: 2b00 cmp r3, #0 8007f70: d009 beq.n 8007f86 { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007f72: 68fb ldr r3, [r7, #12] 8007f74: 681b ldr r3, [r3, #0] 8007f76: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 8007f78: 697b ldr r3, [r7, #20] 8007f7a: 009b lsls r3, r3, #2 8007f7c: 68ba ldr r2, [r7, #8] 8007f7e: 4413 add r3, r2 8007f80: 881a ldrh r2, [r3, #0] 8007f82: 693b ldr r3, [r7, #16] 8007f84: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007f86: 68fb ldr r3, [r7, #12] 8007f88: 681b ldr r3, [r3, #0] 8007f8a: 681b ldr r3, [r3, #0] } 8007f8c: 4618 mov r0, r3 8007f8e: 371c adds r7, #28 8007f90: 46bd mov sp, r7 8007f92: f85d 7b04 ldr.w r7, [sp], #4 8007f96: 4770 bx lr 08007f98 : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 8007f98: b480 push {r7} 8007f9a: b087 sub sp, #28 8007f9c: af00 add r7, sp, #0 8007f9e: 60f8 str r0, [r7, #12] 8007fa0: 60b9 str r1, [r7, #8] 8007fa2: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8007fa4: 2300 movs r3, #0 8007fa6: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 8007fa8: 231f movs r3, #31 8007faa: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 8007fac: 68bb ldr r3, [r7, #8] 8007fae: f003 0301 and.w r3, r3, #1 8007fb2: 2b00 cmp r3, #0 8007fb4: d102 bne.n 8007fbc { status = HAL_ERROR; 8007fb6: 2301 movs r3, #1 8007fb8: 75fb strb r3, [r7, #23] 8007fba: e063 b.n 8008084 * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 8007fbc: bf00 nop 8007fbe: 693b ldr r3, [r7, #16] 8007fc0: 1e5a subs r2, r3, #1 8007fc2: 613a str r2, [r7, #16] 8007fc4: 2b00 cmp r3, #0 8007fc6: d009 beq.n 8007fdc 8007fc8: 693b ldr r3, [r7, #16] 8007fca: f003 031f and.w r3, r3, #31 8007fce: 68ba ldr r2, [r7, #8] 8007fd0: fa22 f303 lsr.w r3, r2, r3 8007fd4: f003 0301 and.w r3, r3, #1 8007fd8: 2b00 cmp r3, #0 8007fda: d0f0 beq.n 8007fbe { } switch (PolyLength) 8007fdc: 687b ldr r3, [r7, #4] 8007fde: 2b18 cmp r3, #24 8007fe0: d846 bhi.n 8008070 8007fe2: a201 add r2, pc, #4 @ (adr r2, 8007fe8 ) 8007fe4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007fe8: 08008077 .word 0x08008077 8007fec: 08008071 .word 0x08008071 8007ff0: 08008071 .word 0x08008071 8007ff4: 08008071 .word 0x08008071 8007ff8: 08008071 .word 0x08008071 8007ffc: 08008071 .word 0x08008071 8008000: 08008071 .word 0x08008071 8008004: 08008071 .word 0x08008071 8008008: 08008065 .word 0x08008065 800800c: 08008071 .word 0x08008071 8008010: 08008071 .word 0x08008071 8008014: 08008071 .word 0x08008071 8008018: 08008071 .word 0x08008071 800801c: 08008071 .word 0x08008071 8008020: 08008071 .word 0x08008071 8008024: 08008071 .word 0x08008071 8008028: 08008059 .word 0x08008059 800802c: 08008071 .word 0x08008071 8008030: 08008071 .word 0x08008071 8008034: 08008071 .word 0x08008071 8008038: 08008071 .word 0x08008071 800803c: 08008071 .word 0x08008071 8008040: 08008071 .word 0x08008071 8008044: 08008071 .word 0x08008071 8008048: 0800804d .word 0x0800804d { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 800804c: 693b ldr r3, [r7, #16] 800804e: 2b06 cmp r3, #6 8008050: d913 bls.n 800807a { status = HAL_ERROR; 8008052: 2301 movs r3, #1 8008054: 75fb strb r3, [r7, #23] } break; 8008056: e010 b.n 800807a case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 8008058: 693b ldr r3, [r7, #16] 800805a: 2b07 cmp r3, #7 800805c: d90f bls.n 800807e { status = HAL_ERROR; 800805e: 2301 movs r3, #1 8008060: 75fb strb r3, [r7, #23] } break; 8008062: e00c b.n 800807e case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 8008064: 693b ldr r3, [r7, #16] 8008066: 2b0f cmp r3, #15 8008068: d90b bls.n 8008082 { status = HAL_ERROR; 800806a: 2301 movs r3, #1 800806c: 75fb strb r3, [r7, #23] } break; 800806e: e008 b.n 8008082 case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 8008070: 2301 movs r3, #1 8008072: 75fb strb r3, [r7, #23] break; 8008074: e006 b.n 8008084 break; 8008076: bf00 nop 8008078: e004 b.n 8008084 break; 800807a: bf00 nop 800807c: e002 b.n 8008084 break; 800807e: bf00 nop 8008080: e000 b.n 8008084 break; 8008082: bf00 nop } } if (status == HAL_OK) 8008084: 7dfb ldrb r3, [r7, #23] 8008086: 2b00 cmp r3, #0 8008088: d10d bne.n 80080a6 { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 800808a: 68fb ldr r3, [r7, #12] 800808c: 681b ldr r3, [r3, #0] 800808e: 68ba ldr r2, [r7, #8] 8008090: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 8008092: 68fb ldr r3, [r7, #12] 8008094: 681b ldr r3, [r3, #0] 8008096: 689b ldr r3, [r3, #8] 8008098: f023 0118 bic.w r1, r3, #24 800809c: 68fb ldr r3, [r7, #12] 800809e: 681b ldr r3, [r3, #0] 80080a0: 687a ldr r2, [r7, #4] 80080a2: 430a orrs r2, r1 80080a4: 609a str r2, [r3, #8] } /* Return function status */ return status; 80080a6: 7dfb ldrb r3, [r7, #23] } 80080a8: 4618 mov r0, r3 80080aa: 371c adds r7, #28 80080ac: 46bd mov sp, r7 80080ae: f85d 7b04 ldr.w r7, [sp], #4 80080b2: 4770 bx lr 080080b4 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 80080b4: b580 push {r7, lr} 80080b6: b082 sub sp, #8 80080b8: af00 add r7, sp, #0 80080ba: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 80080bc: 687b ldr r3, [r7, #4] 80080be: 2b00 cmp r3, #0 80080c0: d101 bne.n 80080c6 { return HAL_ERROR; 80080c2: 2301 movs r3, #1 80080c4: e014 b.n 80080f0 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 80080c6: 687b ldr r3, [r7, #4] 80080c8: 791b ldrb r3, [r3, #4] 80080ca: b2db uxtb r3, r3 80080cc: 2b00 cmp r3, #0 80080ce: d105 bne.n 80080dc hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 80080d0: 687b ldr r3, [r7, #4] 80080d2: 2200 movs r2, #0 80080d4: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 80080d6: 6878 ldr r0, [r7, #4] 80080d8: f7fc f836 bl 8004148 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 80080dc: 687b ldr r3, [r7, #4] 80080de: 2202 movs r2, #2 80080e0: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 80080e2: 687b ldr r3, [r7, #4] 80080e4: 2200 movs r2, #0 80080e6: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 80080e8: 687b ldr r3, [r7, #4] 80080ea: 2201 movs r2, #1 80080ec: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 80080ee: 2300 movs r3, #0 } 80080f0: 4618 mov r0, r3 80080f2: 3708 adds r7, #8 80080f4: 46bd mov sp, r7 80080f6: bd80 pop {r7, pc} 080080f8 : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 80080f8: b480 push {r7} 80080fa: b083 sub sp, #12 80080fc: af00 add r7, sp, #0 80080fe: 6078 str r0, [r7, #4] 8008100: 6039 str r1, [r7, #0] /* Check the DAC peripheral handle */ if (hdac == NULL) 8008102: 687b ldr r3, [r7, #4] 8008104: 2b00 cmp r3, #0 8008106: d101 bne.n 800810c { return HAL_ERROR; 8008108: 2301 movs r3, #1 800810a: e046 b.n 800819a /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 800810c: 687b ldr r3, [r7, #4] 800810e: 795b ldrb r3, [r3, #5] 8008110: 2b01 cmp r3, #1 8008112: d101 bne.n 8008118 8008114: 2302 movs r3, #2 8008116: e040 b.n 800819a 8008118: 687b ldr r3, [r7, #4] 800811a: 2201 movs r2, #1 800811c: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 800811e: 687b ldr r3, [r7, #4] 8008120: 2202 movs r2, #2 8008122: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 8008124: 687b ldr r3, [r7, #4] 8008126: 681b ldr r3, [r3, #0] 8008128: 6819 ldr r1, [r3, #0] 800812a: 683b ldr r3, [r7, #0] 800812c: f003 0310 and.w r3, r3, #16 8008130: 2201 movs r2, #1 8008132: 409a lsls r2, r3 8008134: 687b ldr r3, [r7, #4] 8008136: 681b ldr r3, [r3, #0] 8008138: 430a orrs r2, r1 800813a: 601a str r2, [r3, #0] if (Channel == DAC_CHANNEL_1) 800813c: 683b ldr r3, [r7, #0] 800813e: 2b00 cmp r3, #0 8008140: d10f bne.n 8008162 { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 8008142: 687b ldr r3, [r7, #4] 8008144: 681b ldr r3, [r3, #0] 8008146: 681b ldr r3, [r3, #0] 8008148: f003 033e and.w r3, r3, #62 @ 0x3e 800814c: 2b02 cmp r3, #2 800814e: d11d bne.n 800818c { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 8008150: 687b ldr r3, [r7, #4] 8008152: 681b ldr r3, [r3, #0] 8008154: 685a ldr r2, [r3, #4] 8008156: 687b ldr r3, [r7, #4] 8008158: 681b ldr r3, [r3, #0] 800815a: f042 0201 orr.w r2, r2, #1 800815e: 605a str r2, [r3, #4] 8008160: e014 b.n 800818c } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 8008162: 687b ldr r3, [r7, #4] 8008164: 681b ldr r3, [r3, #0] 8008166: 681b ldr r3, [r3, #0] 8008168: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 800816c: 683b ldr r3, [r7, #0] 800816e: f003 0310 and.w r3, r3, #16 8008172: 2102 movs r1, #2 8008174: fa01 f303 lsl.w r3, r1, r3 8008178: 429a cmp r2, r3 800817a: d107 bne.n 800818c { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 800817c: 687b ldr r3, [r7, #4] 800817e: 681b ldr r3, [r3, #0] 8008180: 685a ldr r2, [r3, #4] 8008182: 687b ldr r3, [r7, #4] 8008184: 681b ldr r3, [r3, #0] 8008186: f042 0202 orr.w r2, r2, #2 800818a: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 800818c: 687b ldr r3, [r7, #4] 800818e: 2201 movs r2, #1 8008190: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8008192: 687b ldr r3, [r7, #4] 8008194: 2200 movs r2, #0 8008196: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 8008198: 2300 movs r3, #0 } 800819a: 4618 mov r0, r3 800819c: 370c adds r7, #12 800819e: 46bd mov sp, r7 80081a0: f85d 7b04 ldr.w r7, [sp], #4 80081a4: 4770 bx lr 080081a6 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { 80081a6: b580 push {r7, lr} 80081a8: b084 sub sp, #16 80081aa: af00 add r7, sp, #0 80081ac: 6078 str r0, [r7, #4] uint32_t itsource = hdac->Instance->CR; 80081ae: 687b ldr r3, [r7, #4] 80081b0: 681b ldr r3, [r3, #0] 80081b2: 681b ldr r3, [r3, #0] 80081b4: 60fb str r3, [r7, #12] uint32_t itflag = hdac->Instance->SR; 80081b6: 687b ldr r3, [r7, #4] 80081b8: 681b ldr r3, [r3, #0] 80081ba: 6b5b ldr r3, [r3, #52] @ 0x34 80081bc: 60bb str r3, [r7, #8] if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 80081be: 68fb ldr r3, [r7, #12] 80081c0: f403 5300 and.w r3, r3, #8192 @ 0x2000 80081c4: 2b00 cmp r3, #0 80081c6: d01d beq.n 8008204 { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 80081c8: 68bb ldr r3, [r7, #8] 80081ca: f403 5300 and.w r3, r3, #8192 @ 0x2000 80081ce: 2b00 cmp r3, #0 80081d0: d018 beq.n 8008204 { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 80081d2: 687b ldr r3, [r7, #4] 80081d4: 2204 movs r2, #4 80081d6: 711a strb r2, [r3, #4] /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 80081d8: 687b ldr r3, [r7, #4] 80081da: 691b ldr r3, [r3, #16] 80081dc: f043 0201 orr.w r2, r3, #1 80081e0: 687b ldr r3, [r7, #4] 80081e2: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 80081e4: 687b ldr r3, [r7, #4] 80081e6: 681b ldr r3, [r3, #0] 80081e8: f44f 5200 mov.w r2, #8192 @ 0x2000 80081ec: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 80081ee: 687b ldr r3, [r7, #4] 80081f0: 681b ldr r3, [r3, #0] 80081f2: 681a ldr r2, [r3, #0] 80081f4: 687b ldr r3, [r7, #4] 80081f6: 681b ldr r3, [r3, #0] 80081f8: f422 5280 bic.w r2, r2, #4096 @ 0x1000 80081fc: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); 80081fe: 6878 ldr r0, [r7, #4] 8008200: f000 f851 bl 80082a6 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 8008204: 68fb ldr r3, [r7, #12] 8008206: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800820a: 2b00 cmp r3, #0 800820c: d01d beq.n 800824a { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 800820e: 68bb ldr r3, [r7, #8] 8008210: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8008214: 2b00 cmp r3, #0 8008216: d018 beq.n 800824a { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8008218: 687b ldr r3, [r7, #4] 800821a: 2204 movs r2, #4 800821c: 711a strb r2, [r3, #4] /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 800821e: 687b ldr r3, [r7, #4] 8008220: 691b ldr r3, [r3, #16] 8008222: f043 0202 orr.w r2, r3, #2 8008226: 687b ldr r3, [r7, #4] 8008228: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 800822a: 687b ldr r3, [r7, #4] 800822c: 681b ldr r3, [r3, #0] 800822e: f04f 5200 mov.w r2, #536870912 @ 0x20000000 8008232: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 8008234: 687b ldr r3, [r7, #4] 8008236: 681b ldr r3, [r3, #0] 8008238: 681a ldr r2, [r3, #0] 800823a: 687b ldr r3, [r7, #4] 800823c: 681b ldr r3, [r3, #0] 800823e: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 8008242: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 8008244: 6878 ldr r0, [r7, #4] 8008246: f000 f97b bl 8008540 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } 800824a: bf00 nop 800824c: 3710 adds r7, #16 800824e: 46bd mov sp, r7 8008250: bd80 pop {r7, pc} 08008252 : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 8008252: b480 push {r7} 8008254: b087 sub sp, #28 8008256: af00 add r7, sp, #0 8008258: 60f8 str r0, [r7, #12] 800825a: 60b9 str r1, [r7, #8] 800825c: 607a str r2, [r7, #4] 800825e: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 8008260: 2300 movs r3, #0 8008262: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 8008264: 68fb ldr r3, [r7, #12] 8008266: 2b00 cmp r3, #0 8008268: d101 bne.n 800826e { return HAL_ERROR; 800826a: 2301 movs r3, #1 800826c: e015 b.n 800829a /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 800826e: 68fb ldr r3, [r7, #12] 8008270: 681b ldr r3, [r3, #0] 8008272: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 8008274: 68bb ldr r3, [r7, #8] 8008276: 2b00 cmp r3, #0 8008278: d105 bne.n 8008286 { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 800827a: 697a ldr r2, [r7, #20] 800827c: 687b ldr r3, [r7, #4] 800827e: 4413 add r3, r2 8008280: 3308 adds r3, #8 8008282: 617b str r3, [r7, #20] 8008284: e004 b.n 8008290 } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 8008286: 697a ldr r2, [r7, #20] 8008288: 687b ldr r3, [r7, #4] 800828a: 4413 add r3, r2 800828c: 3314 adds r3, #20 800828e: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8008290: 697b ldr r3, [r7, #20] 8008292: 461a mov r2, r3 8008294: 683b ldr r3, [r7, #0] 8008296: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 8008298: 2300 movs r3, #0 } 800829a: 4618 mov r0, r3 800829c: 371c adds r7, #28 800829e: 46bd mov sp, r7 80082a0: f85d 7b04 ldr.w r7, [sp], #4 80082a4: 4770 bx lr 080082a6 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { 80082a6: b480 push {r7} 80082a8: b083 sub sp, #12 80082aa: af00 add r7, sp, #0 80082ac: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } 80082ae: bf00 nop 80082b0: 370c adds r7, #12 80082b2: 46bd mov sp, r7 80082b4: f85d 7b04 ldr.w r7, [sp], #4 80082b8: 4770 bx lr ... 080082bc : * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 80082bc: b580 push {r7, lr} 80082be: b08a sub sp, #40 @ 0x28 80082c0: af00 add r7, sp, #0 80082c2: 60f8 str r0, [r7, #12] 80082c4: 60b9 str r1, [r7, #8] 80082c6: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80082c8: 2300 movs r3, #0 80082ca: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 80082ce: 68fb ldr r3, [r7, #12] 80082d0: 2b00 cmp r3, #0 80082d2: d002 beq.n 80082da 80082d4: 68bb ldr r3, [r7, #8] 80082d6: 2b00 cmp r3, #0 80082d8: d101 bne.n 80082de { return HAL_ERROR; 80082da: 2301 movs r3, #1 80082dc: e12a b.n 8008534 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 80082de: 68fb ldr r3, [r7, #12] 80082e0: 795b ldrb r3, [r3, #5] 80082e2: 2b01 cmp r3, #1 80082e4: d101 bne.n 80082ea 80082e6: 2302 movs r3, #2 80082e8: e124 b.n 8008534 80082ea: 68fb ldr r3, [r7, #12] 80082ec: 2201 movs r2, #1 80082ee: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 80082f0: 68fb ldr r3, [r7, #12] 80082f2: 2202 movs r2, #2 80082f4: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 80082f6: 68bb ldr r3, [r7, #8] 80082f8: 681b ldr r3, [r3, #0] 80082fa: 2b04 cmp r3, #4 80082fc: d17a bne.n 80083f4 { /* Get timeout */ tickstart = HAL_GetTick(); 80082fe: f7fd fd8d bl 8005e1c 8008302: 61f8 str r0, [r7, #28] if (Channel == DAC_CHANNEL_1) 8008304: 687b ldr r3, [r7, #4] 8008306: 2b00 cmp r3, #0 8008308: d13d bne.n 8008386 { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800830a: e018 b.n 800833e { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 800830c: f7fd fd86 bl 8005e1c 8008310: 4602 mov r2, r0 8008312: 69fb ldr r3, [r7, #28] 8008314: 1ad3 subs r3, r2, r3 8008316: 2b01 cmp r3, #1 8008318: d911 bls.n 800833e { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800831a: 68fb ldr r3, [r7, #12] 800831c: 681b ldr r3, [r3, #0] 800831e: 6b5a ldr r2, [r3, #52] @ 0x34 8008320: 4b86 ldr r3, [pc, #536] @ (800853c ) 8008322: 4013 ands r3, r2 8008324: 2b00 cmp r3, #0 8008326: d00a beq.n 800833e { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8008328: 68fb ldr r3, [r7, #12] 800832a: 691b ldr r3, [r3, #16] 800832c: f043 0208 orr.w r2, r3, #8 8008330: 68fb ldr r3, [r7, #12] 8008332: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8008334: 68fb ldr r3, [r7, #12] 8008336: 2203 movs r2, #3 8008338: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 800833a: 2303 movs r3, #3 800833c: e0fa b.n 8008534 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 800833e: 68fb ldr r3, [r7, #12] 8008340: 681b ldr r3, [r3, #0] 8008342: 6b5a ldr r2, [r3, #52] @ 0x34 8008344: 4b7d ldr r3, [pc, #500] @ (800853c ) 8008346: 4013 ands r3, r2 8008348: 2b00 cmp r3, #0 800834a: d1df bne.n 800830c } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 800834c: 68fb ldr r3, [r7, #12] 800834e: 681b ldr r3, [r3, #0] 8008350: 68ba ldr r2, [r7, #8] 8008352: 6992 ldr r2, [r2, #24] 8008354: 641a str r2, [r3, #64] @ 0x40 8008356: e020 b.n 800839a { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8008358: f7fd fd60 bl 8005e1c 800835c: 4602 mov r2, r0 800835e: 69fb ldr r3, [r7, #28] 8008360: 1ad3 subs r3, r2, r3 8008362: 2b01 cmp r3, #1 8008364: d90f bls.n 8008386 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8008366: 68fb ldr r3, [r7, #12] 8008368: 681b ldr r3, [r3, #0] 800836a: 6b5b ldr r3, [r3, #52] @ 0x34 800836c: 2b00 cmp r3, #0 800836e: da0a bge.n 8008386 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8008370: 68fb ldr r3, [r7, #12] 8008372: 691b ldr r3, [r3, #16] 8008374: f043 0208 orr.w r2, r3, #8 8008378: 68fb ldr r3, [r7, #12] 800837a: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 800837c: 68fb ldr r3, [r7, #12] 800837e: 2203 movs r2, #3 8008380: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8008382: 2303 movs r3, #3 8008384: e0d6 b.n 8008534 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 8008386: 68fb ldr r3, [r7, #12] 8008388: 681b ldr r3, [r3, #0] 800838a: 6b5b ldr r3, [r3, #52] @ 0x34 800838c: 2b00 cmp r3, #0 800838e: dbe3 blt.n 8008358 } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8008390: 68fb ldr r3, [r7, #12] 8008392: 681b ldr r3, [r3, #0] 8008394: 68ba ldr r2, [r7, #8] 8008396: 6992 ldr r2, [r2, #24] 8008398: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 800839a: 68fb ldr r3, [r7, #12] 800839c: 681b ldr r3, [r3, #0] 800839e: 6c9a ldr r2, [r3, #72] @ 0x48 80083a0: 687b ldr r3, [r7, #4] 80083a2: f003 0310 and.w r3, r3, #16 80083a6: f240 31ff movw r1, #1023 @ 0x3ff 80083aa: fa01 f303 lsl.w r3, r1, r3 80083ae: 43db mvns r3, r3 80083b0: ea02 0103 and.w r1, r2, r3 80083b4: 68bb ldr r3, [r7, #8] 80083b6: 69da ldr r2, [r3, #28] 80083b8: 687b ldr r3, [r7, #4] 80083ba: f003 0310 and.w r3, r3, #16 80083be: 409a lsls r2, r3 80083c0: 68fb ldr r3, [r7, #12] 80083c2: 681b ldr r3, [r3, #0] 80083c4: 430a orrs r2, r1 80083c6: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 80083c8: 68fb ldr r3, [r7, #12] 80083ca: 681b ldr r3, [r3, #0] 80083cc: 6cda ldr r2, [r3, #76] @ 0x4c 80083ce: 687b ldr r3, [r7, #4] 80083d0: f003 0310 and.w r3, r3, #16 80083d4: 21ff movs r1, #255 @ 0xff 80083d6: fa01 f303 lsl.w r3, r1, r3 80083da: 43db mvns r3, r3 80083dc: ea02 0103 and.w r1, r2, r3 80083e0: 68bb ldr r3, [r7, #8] 80083e2: 6a1a ldr r2, [r3, #32] 80083e4: 687b ldr r3, [r7, #4] 80083e6: f003 0310 and.w r3, r3, #16 80083ea: 409a lsls r2, r3 80083ec: 68fb ldr r3, [r7, #12] 80083ee: 681b ldr r3, [r3, #0] 80083f0: 430a orrs r2, r1 80083f2: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 80083f4: 68bb ldr r3, [r7, #8] 80083f6: 691b ldr r3, [r3, #16] 80083f8: 2b01 cmp r3, #1 80083fa: d11d bne.n 8008438 /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 80083fc: 68fb ldr r3, [r7, #12] 80083fe: 681b ldr r3, [r3, #0] 8008400: 6b9b ldr r3, [r3, #56] @ 0x38 8008402: 61bb str r3, [r7, #24] /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 8008404: 687b ldr r3, [r7, #4] 8008406: f003 0310 and.w r3, r3, #16 800840a: 221f movs r2, #31 800840c: fa02 f303 lsl.w r3, r2, r3 8008410: 43db mvns r3, r3 8008412: 69ba ldr r2, [r7, #24] 8008414: 4013 ands r3, r2 8008416: 61bb str r3, [r7, #24] /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 8008418: 68bb ldr r3, [r7, #8] 800841a: 695b ldr r3, [r3, #20] 800841c: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 800841e: 687b ldr r3, [r7, #4] 8008420: f003 0310 and.w r3, r3, #16 8008424: 697a ldr r2, [r7, #20] 8008426: fa02 f303 lsl.w r3, r2, r3 800842a: 69ba ldr r2, [r7, #24] 800842c: 4313 orrs r3, r2 800842e: 61bb str r3, [r7, #24] /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 8008430: 68fb ldr r3, [r7, #12] 8008432: 681b ldr r3, [r3, #0] 8008434: 69ba ldr r2, [r7, #24] 8008436: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 8008438: 68fb ldr r3, [r7, #12] 800843a: 681b ldr r3, [r3, #0] 800843c: 6bdb ldr r3, [r3, #60] @ 0x3c 800843e: 61bb str r3, [r7, #24] /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 8008440: 687b ldr r3, [r7, #4] 8008442: f003 0310 and.w r3, r3, #16 8008446: 2207 movs r2, #7 8008448: fa02 f303 lsl.w r3, r2, r3 800844c: 43db mvns r3, r3 800844e: 69ba ldr r2, [r7, #24] 8008450: 4013 ands r3, r2 8008452: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 8008454: 68bb ldr r3, [r7, #8] 8008456: 68db ldr r3, [r3, #12] 8008458: 2b01 cmp r3, #1 800845a: d102 bne.n 8008462 { connectOnChip = 0x00000000UL; 800845c: 2300 movs r3, #0 800845e: 627b str r3, [r7, #36] @ 0x24 8008460: e00f b.n 8008482 } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 8008462: 68bb ldr r3, [r7, #8] 8008464: 68db ldr r3, [r3, #12] 8008466: 2b02 cmp r3, #2 8008468: d102 bne.n 8008470 { connectOnChip = DAC_MCR_MODE1_0; 800846a: 2301 movs r3, #1 800846c: 627b str r3, [r7, #36] @ 0x24 800846e: e008 b.n 8008482 } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 8008470: 68bb ldr r3, [r7, #8] 8008472: 689b ldr r3, [r3, #8] 8008474: 2b00 cmp r3, #0 8008476: d102 bne.n 800847e { connectOnChip = DAC_MCR_MODE1_0; 8008478: 2301 movs r3, #1 800847a: 627b str r3, [r7, #36] @ 0x24 800847c: e001 b.n 8008482 } else { connectOnChip = 0x00000000UL; 800847e: 2300 movs r3, #0 8008480: 627b str r3, [r7, #36] @ 0x24 } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 8008482: 68bb ldr r3, [r7, #8] 8008484: 681a ldr r2, [r3, #0] 8008486: 68bb ldr r3, [r7, #8] 8008488: 689b ldr r3, [r3, #8] 800848a: 4313 orrs r3, r2 800848c: 6a7a ldr r2, [r7, #36] @ 0x24 800848e: 4313 orrs r3, r2 8008490: 617b str r3, [r7, #20] /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8008492: 687b ldr r3, [r7, #4] 8008494: f003 0310 and.w r3, r3, #16 8008498: 697a ldr r2, [r7, #20] 800849a: fa02 f303 lsl.w r3, r2, r3 800849e: 69ba ldr r2, [r7, #24] 80084a0: 4313 orrs r3, r2 80084a2: 61bb str r3, [r7, #24] /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 80084a4: 68fb ldr r3, [r7, #12] 80084a6: 681b ldr r3, [r3, #0] 80084a8: 69ba ldr r2, [r7, #24] 80084aa: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 80084ac: 68fb ldr r3, [r7, #12] 80084ae: 681b ldr r3, [r3, #0] 80084b0: 6819 ldr r1, [r3, #0] 80084b2: 687b ldr r3, [r7, #4] 80084b4: f003 0310 and.w r3, r3, #16 80084b8: f44f 4280 mov.w r2, #16384 @ 0x4000 80084bc: fa02 f303 lsl.w r3, r2, r3 80084c0: 43da mvns r2, r3 80084c2: 68fb ldr r3, [r7, #12] 80084c4: 681b ldr r3, [r3, #0] 80084c6: 400a ands r2, r1 80084c8: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 80084ca: 68fb ldr r3, [r7, #12] 80084cc: 681b ldr r3, [r3, #0] 80084ce: 681b ldr r3, [r3, #0] 80084d0: 61bb str r3, [r7, #24] /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 80084d2: 687b ldr r3, [r7, #4] 80084d4: f003 0310 and.w r3, r3, #16 80084d8: f640 72fe movw r2, #4094 @ 0xffe 80084dc: fa02 f303 lsl.w r3, r2, r3 80084e0: 43db mvns r3, r3 80084e2: 69ba ldr r2, [r7, #24] 80084e4: 4013 ands r3, r2 80084e6: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 80084e8: 68bb ldr r3, [r7, #8] 80084ea: 685b ldr r3, [r3, #4] 80084ec: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80084ee: 687b ldr r3, [r7, #4] 80084f0: f003 0310 and.w r3, r3, #16 80084f4: 697a ldr r2, [r7, #20] 80084f6: fa02 f303 lsl.w r3, r2, r3 80084fa: 69ba ldr r2, [r7, #24] 80084fc: 4313 orrs r3, r2 80084fe: 61bb str r3, [r7, #24] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 8008500: 68fb ldr r3, [r7, #12] 8008502: 681b ldr r3, [r3, #0] 8008504: 69ba ldr r2, [r7, #24] 8008506: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 8008508: 68fb ldr r3, [r7, #12] 800850a: 681b ldr r3, [r3, #0] 800850c: 6819 ldr r1, [r3, #0] 800850e: 687b ldr r3, [r7, #4] 8008510: f003 0310 and.w r3, r3, #16 8008514: 22c0 movs r2, #192 @ 0xc0 8008516: fa02 f303 lsl.w r3, r2, r3 800851a: 43da mvns r2, r3 800851c: 68fb ldr r3, [r7, #12] 800851e: 681b ldr r3, [r3, #0] 8008520: 400a ands r2, r1 8008522: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8008524: 68fb ldr r3, [r7, #12] 8008526: 2201 movs r2, #1 8008528: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 800852a: 68fb ldr r3, [r7, #12] 800852c: 2200 movs r2, #0 800852e: 715a strb r2, [r3, #5] /* Return function status */ return status; 8008530: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 8008534: 4618 mov r0, r3 8008536: 3728 adds r7, #40 @ 0x28 8008538: 46bd mov sp, r7 800853a: bd80 pop {r7, pc} 800853c: 20008000 .word 0x20008000 08008540 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { 8008540: b480 push {r7} 8008542: b083 sub sp, #12 8008544: af00 add r7, sp, #0 8008546: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } 8008548: bf00 nop 800854a: 370c adds r7, #12 800854c: 46bd mov sp, r7 800854e: f85d 7b04 ldr.w r7, [sp], #4 8008552: 4770 bx lr 08008554 : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 8008554: b580 push {r7, lr} 8008556: b086 sub sp, #24 8008558: af00 add r7, sp, #0 800855a: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 800855c: f7fd fc5e bl 8005e1c 8008560: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8008562: 687b ldr r3, [r7, #4] 8008564: 2b00 cmp r3, #0 8008566: d101 bne.n 800856c { return HAL_ERROR; 8008568: 2301 movs r3, #1 800856a: e316 b.n 8008b9a assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800856c: 687b ldr r3, [r7, #4] 800856e: 681b ldr r3, [r3, #0] 8008570: 4a66 ldr r2, [pc, #408] @ (800870c ) 8008572: 4293 cmp r3, r2 8008574: d04a beq.n 800860c 8008576: 687b ldr r3, [r7, #4] 8008578: 681b ldr r3, [r3, #0] 800857a: 4a65 ldr r2, [pc, #404] @ (8008710 ) 800857c: 4293 cmp r3, r2 800857e: d045 beq.n 800860c 8008580: 687b ldr r3, [r7, #4] 8008582: 681b ldr r3, [r3, #0] 8008584: 4a63 ldr r2, [pc, #396] @ (8008714 ) 8008586: 4293 cmp r3, r2 8008588: d040 beq.n 800860c 800858a: 687b ldr r3, [r7, #4] 800858c: 681b ldr r3, [r3, #0] 800858e: 4a62 ldr r2, [pc, #392] @ (8008718 ) 8008590: 4293 cmp r3, r2 8008592: d03b beq.n 800860c 8008594: 687b ldr r3, [r7, #4] 8008596: 681b ldr r3, [r3, #0] 8008598: 4a60 ldr r2, [pc, #384] @ (800871c ) 800859a: 4293 cmp r3, r2 800859c: d036 beq.n 800860c 800859e: 687b ldr r3, [r7, #4] 80085a0: 681b ldr r3, [r3, #0] 80085a2: 4a5f ldr r2, [pc, #380] @ (8008720 ) 80085a4: 4293 cmp r3, r2 80085a6: d031 beq.n 800860c 80085a8: 687b ldr r3, [r7, #4] 80085aa: 681b ldr r3, [r3, #0] 80085ac: 4a5d ldr r2, [pc, #372] @ (8008724 ) 80085ae: 4293 cmp r3, r2 80085b0: d02c beq.n 800860c 80085b2: 687b ldr r3, [r7, #4] 80085b4: 681b ldr r3, [r3, #0] 80085b6: 4a5c ldr r2, [pc, #368] @ (8008728 ) 80085b8: 4293 cmp r3, r2 80085ba: d027 beq.n 800860c 80085bc: 687b ldr r3, [r7, #4] 80085be: 681b ldr r3, [r3, #0] 80085c0: 4a5a ldr r2, [pc, #360] @ (800872c ) 80085c2: 4293 cmp r3, r2 80085c4: d022 beq.n 800860c 80085c6: 687b ldr r3, [r7, #4] 80085c8: 681b ldr r3, [r3, #0] 80085ca: 4a59 ldr r2, [pc, #356] @ (8008730 ) 80085cc: 4293 cmp r3, r2 80085ce: d01d beq.n 800860c 80085d0: 687b ldr r3, [r7, #4] 80085d2: 681b ldr r3, [r3, #0] 80085d4: 4a57 ldr r2, [pc, #348] @ (8008734 ) 80085d6: 4293 cmp r3, r2 80085d8: d018 beq.n 800860c 80085da: 687b ldr r3, [r7, #4] 80085dc: 681b ldr r3, [r3, #0] 80085de: 4a56 ldr r2, [pc, #344] @ (8008738 ) 80085e0: 4293 cmp r3, r2 80085e2: d013 beq.n 800860c 80085e4: 687b ldr r3, [r7, #4] 80085e6: 681b ldr r3, [r3, #0] 80085e8: 4a54 ldr r2, [pc, #336] @ (800873c ) 80085ea: 4293 cmp r3, r2 80085ec: d00e beq.n 800860c 80085ee: 687b ldr r3, [r7, #4] 80085f0: 681b ldr r3, [r3, #0] 80085f2: 4a53 ldr r2, [pc, #332] @ (8008740 ) 80085f4: 4293 cmp r3, r2 80085f6: d009 beq.n 800860c 80085f8: 687b ldr r3, [r7, #4] 80085fa: 681b ldr r3, [r3, #0] 80085fc: 4a51 ldr r2, [pc, #324] @ (8008744 ) 80085fe: 4293 cmp r3, r2 8008600: d004 beq.n 800860c 8008602: 687b ldr r3, [r7, #4] 8008604: 681b ldr r3, [r3, #0] 8008606: 4a50 ldr r2, [pc, #320] @ (8008748 ) 8008608: 4293 cmp r3, r2 800860a: d101 bne.n 8008610 800860c: 2301 movs r3, #1 800860e: e000 b.n 8008612 8008610: 2300 movs r3, #0 8008612: 2b00 cmp r3, #0 8008614: f000 813b beq.w 800888e assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008618: 687b ldr r3, [r7, #4] 800861a: 2202 movs r2, #2 800861c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8008620: 687b ldr r3, [r7, #4] 8008622: 2200 movs r2, #0 8008624: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8008628: 687b ldr r3, [r7, #4] 800862a: 681b ldr r3, [r3, #0] 800862c: 4a37 ldr r2, [pc, #220] @ (800870c ) 800862e: 4293 cmp r3, r2 8008630: d04a beq.n 80086c8 8008632: 687b ldr r3, [r7, #4] 8008634: 681b ldr r3, [r3, #0] 8008636: 4a36 ldr r2, [pc, #216] @ (8008710 ) 8008638: 4293 cmp r3, r2 800863a: d045 beq.n 80086c8 800863c: 687b ldr r3, [r7, #4] 800863e: 681b ldr r3, [r3, #0] 8008640: 4a34 ldr r2, [pc, #208] @ (8008714 ) 8008642: 4293 cmp r3, r2 8008644: d040 beq.n 80086c8 8008646: 687b ldr r3, [r7, #4] 8008648: 681b ldr r3, [r3, #0] 800864a: 4a33 ldr r2, [pc, #204] @ (8008718 ) 800864c: 4293 cmp r3, r2 800864e: d03b beq.n 80086c8 8008650: 687b ldr r3, [r7, #4] 8008652: 681b ldr r3, [r3, #0] 8008654: 4a31 ldr r2, [pc, #196] @ (800871c ) 8008656: 4293 cmp r3, r2 8008658: d036 beq.n 80086c8 800865a: 687b ldr r3, [r7, #4] 800865c: 681b ldr r3, [r3, #0] 800865e: 4a30 ldr r2, [pc, #192] @ (8008720 ) 8008660: 4293 cmp r3, r2 8008662: d031 beq.n 80086c8 8008664: 687b ldr r3, [r7, #4] 8008666: 681b ldr r3, [r3, #0] 8008668: 4a2e ldr r2, [pc, #184] @ (8008724 ) 800866a: 4293 cmp r3, r2 800866c: d02c beq.n 80086c8 800866e: 687b ldr r3, [r7, #4] 8008670: 681b ldr r3, [r3, #0] 8008672: 4a2d ldr r2, [pc, #180] @ (8008728 ) 8008674: 4293 cmp r3, r2 8008676: d027 beq.n 80086c8 8008678: 687b ldr r3, [r7, #4] 800867a: 681b ldr r3, [r3, #0] 800867c: 4a2b ldr r2, [pc, #172] @ (800872c ) 800867e: 4293 cmp r3, r2 8008680: d022 beq.n 80086c8 8008682: 687b ldr r3, [r7, #4] 8008684: 681b ldr r3, [r3, #0] 8008686: 4a2a ldr r2, [pc, #168] @ (8008730 ) 8008688: 4293 cmp r3, r2 800868a: d01d beq.n 80086c8 800868c: 687b ldr r3, [r7, #4] 800868e: 681b ldr r3, [r3, #0] 8008690: 4a28 ldr r2, [pc, #160] @ (8008734 ) 8008692: 4293 cmp r3, r2 8008694: d018 beq.n 80086c8 8008696: 687b ldr r3, [r7, #4] 8008698: 681b ldr r3, [r3, #0] 800869a: 4a27 ldr r2, [pc, #156] @ (8008738 ) 800869c: 4293 cmp r3, r2 800869e: d013 beq.n 80086c8 80086a0: 687b ldr r3, [r7, #4] 80086a2: 681b ldr r3, [r3, #0] 80086a4: 4a25 ldr r2, [pc, #148] @ (800873c ) 80086a6: 4293 cmp r3, r2 80086a8: d00e beq.n 80086c8 80086aa: 687b ldr r3, [r7, #4] 80086ac: 681b ldr r3, [r3, #0] 80086ae: 4a24 ldr r2, [pc, #144] @ (8008740 ) 80086b0: 4293 cmp r3, r2 80086b2: d009 beq.n 80086c8 80086b4: 687b ldr r3, [r7, #4] 80086b6: 681b ldr r3, [r3, #0] 80086b8: 4a22 ldr r2, [pc, #136] @ (8008744 ) 80086ba: 4293 cmp r3, r2 80086bc: d004 beq.n 80086c8 80086be: 687b ldr r3, [r7, #4] 80086c0: 681b ldr r3, [r3, #0] 80086c2: 4a21 ldr r2, [pc, #132] @ (8008748 ) 80086c4: 4293 cmp r3, r2 80086c6: d108 bne.n 80086da 80086c8: 687b ldr r3, [r7, #4] 80086ca: 681b ldr r3, [r3, #0] 80086cc: 681a ldr r2, [r3, #0] 80086ce: 687b ldr r3, [r7, #4] 80086d0: 681b ldr r3, [r3, #0] 80086d2: f022 0201 bic.w r2, r2, #1 80086d6: 601a str r2, [r3, #0] 80086d8: e007 b.n 80086ea 80086da: 687b ldr r3, [r7, #4] 80086dc: 681b ldr r3, [r3, #0] 80086de: 681a ldr r2, [r3, #0] 80086e0: 687b ldr r3, [r7, #4] 80086e2: 681b ldr r3, [r3, #0] 80086e4: f022 0201 bic.w r2, r2, #1 80086e8: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80086ea: e02f b.n 800874c { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80086ec: f7fd fb96 bl 8005e1c 80086f0: 4602 mov r2, r0 80086f2: 693b ldr r3, [r7, #16] 80086f4: 1ad3 subs r3, r2, r3 80086f6: 2b05 cmp r3, #5 80086f8: d928 bls.n 800874c { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 80086fa: 687b ldr r3, [r7, #4] 80086fc: 2220 movs r2, #32 80086fe: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8008700: 687b ldr r3, [r7, #4] 8008702: 2203 movs r2, #3 8008704: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008708: 2301 movs r3, #1 800870a: e246 b.n 8008b9a 800870c: 40020010 .word 0x40020010 8008710: 40020028 .word 0x40020028 8008714: 40020040 .word 0x40020040 8008718: 40020058 .word 0x40020058 800871c: 40020070 .word 0x40020070 8008720: 40020088 .word 0x40020088 8008724: 400200a0 .word 0x400200a0 8008728: 400200b8 .word 0x400200b8 800872c: 40020410 .word 0x40020410 8008730: 40020428 .word 0x40020428 8008734: 40020440 .word 0x40020440 8008738: 40020458 .word 0x40020458 800873c: 40020470 .word 0x40020470 8008740: 40020488 .word 0x40020488 8008744: 400204a0 .word 0x400204a0 8008748: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800874c: 687b ldr r3, [r7, #4] 800874e: 681b ldr r3, [r3, #0] 8008750: 681b ldr r3, [r3, #0] 8008752: f003 0301 and.w r3, r3, #1 8008756: 2b00 cmp r3, #0 8008758: d1c8 bne.n 80086ec } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 800875a: 687b ldr r3, [r7, #4] 800875c: 681b ldr r3, [r3, #0] 800875e: 681b ldr r3, [r3, #0] 8008760: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 8008762: 697a ldr r2, [r7, #20] 8008764: 4b83 ldr r3, [pc, #524] @ (8008974 ) 8008766: 4013 ands r3, r2 8008768: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 800876a: 687b ldr r3, [r7, #4] 800876c: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 800876e: 687b ldr r3, [r7, #4] 8008770: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 8008772: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 8008774: 687b ldr r3, [r7, #4] 8008776: 691b ldr r3, [r3, #16] 8008778: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800877a: 687b ldr r3, [r7, #4] 800877c: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 800877e: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008780: 687b ldr r3, [r7, #4] 8008782: 699b ldr r3, [r3, #24] 8008784: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8008786: 687b ldr r3, [r7, #4] 8008788: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 800878a: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800878c: 687b ldr r3, [r7, #4] 800878e: 6a1b ldr r3, [r3, #32] 8008790: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 8008792: 697a ldr r2, [r7, #20] 8008794: 4313 orrs r3, r2 8008796: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8008798: 687b ldr r3, [r7, #4] 800879a: 6a5b ldr r3, [r3, #36] @ 0x24 800879c: 2b04 cmp r3, #4 800879e: d107 bne.n 80087b0 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 80087a0: 687b ldr r3, [r7, #4] 80087a2: 6ada ldr r2, [r3, #44] @ 0x2c 80087a4: 687b ldr r3, [r7, #4] 80087a6: 6b1b ldr r3, [r3, #48] @ 0x30 80087a8: 4313 orrs r3, r2 80087aa: 697a ldr r2, [r7, #20] 80087ac: 4313 orrs r3, r2 80087ae: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 80087b0: 4b71 ldr r3, [pc, #452] @ (8008978 ) 80087b2: 681a ldr r2, [r3, #0] 80087b4: 4b71 ldr r3, [pc, #452] @ (800897c ) 80087b6: 4013 ands r3, r2 80087b8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80087bc: d328 bcc.n 8008810 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 80087be: 687b ldr r3, [r7, #4] 80087c0: 685b ldr r3, [r3, #4] 80087c2: 2b28 cmp r3, #40 @ 0x28 80087c4: d903 bls.n 80087ce 80087c6: 687b ldr r3, [r7, #4] 80087c8: 685b ldr r3, [r3, #4] 80087ca: 2b2e cmp r3, #46 @ 0x2e 80087cc: d917 bls.n 80087fe 80087ce: 687b ldr r3, [r7, #4] 80087d0: 685b ldr r3, [r3, #4] 80087d2: 2b3e cmp r3, #62 @ 0x3e 80087d4: d903 bls.n 80087de 80087d6: 687b ldr r3, [r7, #4] 80087d8: 685b ldr r3, [r3, #4] 80087da: 2b42 cmp r3, #66 @ 0x42 80087dc: d90f bls.n 80087fe 80087de: 687b ldr r3, [r7, #4] 80087e0: 685b ldr r3, [r3, #4] 80087e2: 2b46 cmp r3, #70 @ 0x46 80087e4: d903 bls.n 80087ee 80087e6: 687b ldr r3, [r7, #4] 80087e8: 685b ldr r3, [r3, #4] 80087ea: 2b48 cmp r3, #72 @ 0x48 80087ec: d907 bls.n 80087fe 80087ee: 687b ldr r3, [r7, #4] 80087f0: 685b ldr r3, [r3, #4] 80087f2: 2b4e cmp r3, #78 @ 0x4e 80087f4: d905 bls.n 8008802 80087f6: 687b ldr r3, [r7, #4] 80087f8: 685b ldr r3, [r3, #4] 80087fa: 2b52 cmp r3, #82 @ 0x52 80087fc: d801 bhi.n 8008802 80087fe: 2301 movs r3, #1 8008800: e000 b.n 8008804 8008802: 2300 movs r3, #0 8008804: 2b00 cmp r3, #0 8008806: d003 beq.n 8008810 { registerValue |= DMA_SxCR_TRBUFF; 8008808: 697b ldr r3, [r7, #20] 800880a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800880e: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8008810: 687b ldr r3, [r7, #4] 8008812: 681b ldr r3, [r3, #0] 8008814: 697a ldr r2, [r7, #20] 8008816: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 8008818: 687b ldr r3, [r7, #4] 800881a: 681b ldr r3, [r3, #0] 800881c: 695b ldr r3, [r3, #20] 800881e: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8008820: 697b ldr r3, [r7, #20] 8008822: f023 0307 bic.w r3, r3, #7 8008826: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 8008828: 687b ldr r3, [r7, #4] 800882a: 6a5b ldr r3, [r3, #36] @ 0x24 800882c: 697a ldr r2, [r7, #20] 800882e: 4313 orrs r3, r2 8008830: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 8008832: 687b ldr r3, [r7, #4] 8008834: 6a5b ldr r3, [r3, #36] @ 0x24 8008836: 2b04 cmp r3, #4 8008838: d117 bne.n 800886a { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 800883a: 687b ldr r3, [r7, #4] 800883c: 6a9b ldr r3, [r3, #40] @ 0x28 800883e: 697a ldr r2, [r7, #20] 8008840: 4313 orrs r3, r2 8008842: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 8008844: 687b ldr r3, [r7, #4] 8008846: 6adb ldr r3, [r3, #44] @ 0x2c 8008848: 2b00 cmp r3, #0 800884a: d00e beq.n 800886a { if (DMA_CheckFifoParam(hdma) != HAL_OK) 800884c: 6878 ldr r0, [r7, #4] 800884e: f002 fb33 bl 800aeb8 8008852: 4603 mov r3, r0 8008854: 2b00 cmp r3, #0 8008856: d008 beq.n 800886a { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8008858: 687b ldr r3, [r7, #4] 800885a: 2240 movs r2, #64 @ 0x40 800885c: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800885e: 687b ldr r3, [r7, #4] 8008860: 2201 movs r2, #1 8008862: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008866: 2301 movs r3, #1 8008868: e197 b.n 8008b9a } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 800886a: 687b ldr r3, [r7, #4] 800886c: 681b ldr r3, [r3, #0] 800886e: 697a ldr r2, [r7, #20] 8008870: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8008872: 6878 ldr r0, [r7, #4] 8008874: f002 fa6e bl 800ad54 8008878: 4603 mov r3, r0 800887a: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800887c: 687b ldr r3, [r7, #4] 800887e: 6ddb ldr r3, [r3, #92] @ 0x5c 8008880: f003 031f and.w r3, r3, #31 8008884: 223f movs r2, #63 @ 0x3f 8008886: 409a lsls r2, r3 8008888: 68bb ldr r3, [r7, #8] 800888a: 609a str r2, [r3, #8] 800888c: e0cd b.n 8008a2a } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800888e: 687b ldr r3, [r7, #4] 8008890: 681b ldr r3, [r3, #0] 8008892: 4a3b ldr r2, [pc, #236] @ (8008980 ) 8008894: 4293 cmp r3, r2 8008896: d022 beq.n 80088de 8008898: 687b ldr r3, [r7, #4] 800889a: 681b ldr r3, [r3, #0] 800889c: 4a39 ldr r2, [pc, #228] @ (8008984 ) 800889e: 4293 cmp r3, r2 80088a0: d01d beq.n 80088de 80088a2: 687b ldr r3, [r7, #4] 80088a4: 681b ldr r3, [r3, #0] 80088a6: 4a38 ldr r2, [pc, #224] @ (8008988 ) 80088a8: 4293 cmp r3, r2 80088aa: d018 beq.n 80088de 80088ac: 687b ldr r3, [r7, #4] 80088ae: 681b ldr r3, [r3, #0] 80088b0: 4a36 ldr r2, [pc, #216] @ (800898c ) 80088b2: 4293 cmp r3, r2 80088b4: d013 beq.n 80088de 80088b6: 687b ldr r3, [r7, #4] 80088b8: 681b ldr r3, [r3, #0] 80088ba: 4a35 ldr r2, [pc, #212] @ (8008990 ) 80088bc: 4293 cmp r3, r2 80088be: d00e beq.n 80088de 80088c0: 687b ldr r3, [r7, #4] 80088c2: 681b ldr r3, [r3, #0] 80088c4: 4a33 ldr r2, [pc, #204] @ (8008994 ) 80088c6: 4293 cmp r3, r2 80088c8: d009 beq.n 80088de 80088ca: 687b ldr r3, [r7, #4] 80088cc: 681b ldr r3, [r3, #0] 80088ce: 4a32 ldr r2, [pc, #200] @ (8008998 ) 80088d0: 4293 cmp r3, r2 80088d2: d004 beq.n 80088de 80088d4: 687b ldr r3, [r7, #4] 80088d6: 681b ldr r3, [r3, #0] 80088d8: 4a30 ldr r2, [pc, #192] @ (800899c ) 80088da: 4293 cmp r3, r2 80088dc: d101 bne.n 80088e2 80088de: 2301 movs r3, #1 80088e0: e000 b.n 80088e4 80088e2: 2300 movs r3, #0 80088e4: 2b00 cmp r3, #0 80088e6: f000 8097 beq.w 8008a18 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80088ea: 687b ldr r3, [r7, #4] 80088ec: 681b ldr r3, [r3, #0] 80088ee: 4a24 ldr r2, [pc, #144] @ (8008980 ) 80088f0: 4293 cmp r3, r2 80088f2: d021 beq.n 8008938 80088f4: 687b ldr r3, [r7, #4] 80088f6: 681b ldr r3, [r3, #0] 80088f8: 4a22 ldr r2, [pc, #136] @ (8008984 ) 80088fa: 4293 cmp r3, r2 80088fc: d01c beq.n 8008938 80088fe: 687b ldr r3, [r7, #4] 8008900: 681b ldr r3, [r3, #0] 8008902: 4a21 ldr r2, [pc, #132] @ (8008988 ) 8008904: 4293 cmp r3, r2 8008906: d017 beq.n 8008938 8008908: 687b ldr r3, [r7, #4] 800890a: 681b ldr r3, [r3, #0] 800890c: 4a1f ldr r2, [pc, #124] @ (800898c ) 800890e: 4293 cmp r3, r2 8008910: d012 beq.n 8008938 8008912: 687b ldr r3, [r7, #4] 8008914: 681b ldr r3, [r3, #0] 8008916: 4a1e ldr r2, [pc, #120] @ (8008990 ) 8008918: 4293 cmp r3, r2 800891a: d00d beq.n 8008938 800891c: 687b ldr r3, [r7, #4] 800891e: 681b ldr r3, [r3, #0] 8008920: 4a1c ldr r2, [pc, #112] @ (8008994 ) 8008922: 4293 cmp r3, r2 8008924: d008 beq.n 8008938 8008926: 687b ldr r3, [r7, #4] 8008928: 681b ldr r3, [r3, #0] 800892a: 4a1b ldr r2, [pc, #108] @ (8008998 ) 800892c: 4293 cmp r3, r2 800892e: d003 beq.n 8008938 8008930: 687b ldr r3, [r7, #4] 8008932: 681b ldr r3, [r3, #0] 8008934: 4a19 ldr r2, [pc, #100] @ (800899c ) 8008936: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008938: 687b ldr r3, [r7, #4] 800893a: 2202 movs r2, #2 800893c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8008940: 687b ldr r3, [r7, #4] 8008942: 2200 movs r2, #0 8008944: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 8008948: 687b ldr r3, [r7, #4] 800894a: 681b ldr r3, [r3, #0] 800894c: 681b ldr r3, [r3, #0] 800894e: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8008950: 697a ldr r2, [r7, #20] 8008952: 4b13 ldr r3, [pc, #76] @ (80089a0 ) 8008954: 4013 ands r3, r2 8008956: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8008958: 687b ldr r3, [r7, #4] 800895a: 689b ldr r3, [r3, #8] 800895c: 2b40 cmp r3, #64 @ 0x40 800895e: d021 beq.n 80089a4 8008960: 687b ldr r3, [r7, #4] 8008962: 689b ldr r3, [r3, #8] 8008964: 2b80 cmp r3, #128 @ 0x80 8008966: d102 bne.n 800896e 8008968: f44f 4380 mov.w r3, #16384 @ 0x4000 800896c: e01b b.n 80089a6 800896e: 2300 movs r3, #0 8008970: e019 b.n 80089a6 8008972: bf00 nop 8008974: fe10803f .word 0xfe10803f 8008978: 5c001000 .word 0x5c001000 800897c: ffff0000 .word 0xffff0000 8008980: 58025408 .word 0x58025408 8008984: 5802541c .word 0x5802541c 8008988: 58025430 .word 0x58025430 800898c: 58025444 .word 0x58025444 8008990: 58025458 .word 0x58025458 8008994: 5802546c .word 0x5802546c 8008998: 58025480 .word 0x58025480 800899c: 58025494 .word 0x58025494 80089a0: fffe000f .word 0xfffe000f 80089a4: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 80089a6: 687a ldr r2, [r7, #4] 80089a8: 68d2 ldr r2, [r2, #12] 80089aa: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80089ac: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80089ae: 687b ldr r3, [r7, #4] 80089b0: 691b ldr r3, [r3, #16] 80089b2: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 80089b4: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80089b6: 687b ldr r3, [r7, #4] 80089b8: 695b ldr r3, [r3, #20] 80089ba: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80089bc: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80089be: 687b ldr r3, [r7, #4] 80089c0: 699b ldr r3, [r3, #24] 80089c2: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80089c4: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80089c6: 687b ldr r3, [r7, #4] 80089c8: 69db ldr r3, [r3, #28] 80089ca: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80089cc: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 80089ce: 687b ldr r3, [r7, #4] 80089d0: 6a1b ldr r3, [r3, #32] 80089d2: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80089d4: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80089d6: 697a ldr r2, [r7, #20] 80089d8: 4313 orrs r3, r2 80089da: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 80089dc: 687b ldr r3, [r7, #4] 80089de: 681b ldr r3, [r3, #0] 80089e0: 697a ldr r2, [r7, #20] 80089e2: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 80089e4: 687b ldr r3, [r7, #4] 80089e6: 681b ldr r3, [r3, #0] 80089e8: 461a mov r2, r3 80089ea: 4b6e ldr r3, [pc, #440] @ (8008ba4 ) 80089ec: 4413 add r3, r2 80089ee: 4a6e ldr r2, [pc, #440] @ (8008ba8 ) 80089f0: fba2 2303 umull r2, r3, r2, r3 80089f4: 091b lsrs r3, r3, #4 80089f6: 009a lsls r2, r3, #2 80089f8: 687b ldr r3, [r7, #4] 80089fa: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 80089fc: 6878 ldr r0, [r7, #4] 80089fe: f002 f9a9 bl 800ad54 8008a02: 4603 mov r3, r0 8008a04: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8008a06: 687b ldr r3, [r7, #4] 8008a08: 6ddb ldr r3, [r3, #92] @ 0x5c 8008a0a: f003 031f and.w r3, r3, #31 8008a0e: 2201 movs r2, #1 8008a10: 409a lsls r2, r3 8008a12: 68fb ldr r3, [r7, #12] 8008a14: 605a str r2, [r3, #4] 8008a16: e008 b.n 8008a2a } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8008a18: 687b ldr r3, [r7, #4] 8008a1a: 2240 movs r2, #64 @ 0x40 8008a1c: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8008a1e: 687b ldr r3, [r7, #4] 8008a20: 2203 movs r2, #3 8008a22: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008a26: 2301 movs r3, #1 8008a28: e0b7 b.n 8008b9a } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008a2a: 687b ldr r3, [r7, #4] 8008a2c: 681b ldr r3, [r3, #0] 8008a2e: 4a5f ldr r2, [pc, #380] @ (8008bac ) 8008a30: 4293 cmp r3, r2 8008a32: d072 beq.n 8008b1a 8008a34: 687b ldr r3, [r7, #4] 8008a36: 681b ldr r3, [r3, #0] 8008a38: 4a5d ldr r2, [pc, #372] @ (8008bb0 ) 8008a3a: 4293 cmp r3, r2 8008a3c: d06d beq.n 8008b1a 8008a3e: 687b ldr r3, [r7, #4] 8008a40: 681b ldr r3, [r3, #0] 8008a42: 4a5c ldr r2, [pc, #368] @ (8008bb4 ) 8008a44: 4293 cmp r3, r2 8008a46: d068 beq.n 8008b1a 8008a48: 687b ldr r3, [r7, #4] 8008a4a: 681b ldr r3, [r3, #0] 8008a4c: 4a5a ldr r2, [pc, #360] @ (8008bb8 ) 8008a4e: 4293 cmp r3, r2 8008a50: d063 beq.n 8008b1a 8008a52: 687b ldr r3, [r7, #4] 8008a54: 681b ldr r3, [r3, #0] 8008a56: 4a59 ldr r2, [pc, #356] @ (8008bbc ) 8008a58: 4293 cmp r3, r2 8008a5a: d05e beq.n 8008b1a 8008a5c: 687b ldr r3, [r7, #4] 8008a5e: 681b ldr r3, [r3, #0] 8008a60: 4a57 ldr r2, [pc, #348] @ (8008bc0 ) 8008a62: 4293 cmp r3, r2 8008a64: d059 beq.n 8008b1a 8008a66: 687b ldr r3, [r7, #4] 8008a68: 681b ldr r3, [r3, #0] 8008a6a: 4a56 ldr r2, [pc, #344] @ (8008bc4 ) 8008a6c: 4293 cmp r3, r2 8008a6e: d054 beq.n 8008b1a 8008a70: 687b ldr r3, [r7, #4] 8008a72: 681b ldr r3, [r3, #0] 8008a74: 4a54 ldr r2, [pc, #336] @ (8008bc8 ) 8008a76: 4293 cmp r3, r2 8008a78: d04f beq.n 8008b1a 8008a7a: 687b ldr r3, [r7, #4] 8008a7c: 681b ldr r3, [r3, #0] 8008a7e: 4a53 ldr r2, [pc, #332] @ (8008bcc ) 8008a80: 4293 cmp r3, r2 8008a82: d04a beq.n 8008b1a 8008a84: 687b ldr r3, [r7, #4] 8008a86: 681b ldr r3, [r3, #0] 8008a88: 4a51 ldr r2, [pc, #324] @ (8008bd0 ) 8008a8a: 4293 cmp r3, r2 8008a8c: d045 beq.n 8008b1a 8008a8e: 687b ldr r3, [r7, #4] 8008a90: 681b ldr r3, [r3, #0] 8008a92: 4a50 ldr r2, [pc, #320] @ (8008bd4 ) 8008a94: 4293 cmp r3, r2 8008a96: d040 beq.n 8008b1a 8008a98: 687b ldr r3, [r7, #4] 8008a9a: 681b ldr r3, [r3, #0] 8008a9c: 4a4e ldr r2, [pc, #312] @ (8008bd8 ) 8008a9e: 4293 cmp r3, r2 8008aa0: d03b beq.n 8008b1a 8008aa2: 687b ldr r3, [r7, #4] 8008aa4: 681b ldr r3, [r3, #0] 8008aa6: 4a4d ldr r2, [pc, #308] @ (8008bdc ) 8008aa8: 4293 cmp r3, r2 8008aaa: d036 beq.n 8008b1a 8008aac: 687b ldr r3, [r7, #4] 8008aae: 681b ldr r3, [r3, #0] 8008ab0: 4a4b ldr r2, [pc, #300] @ (8008be0 ) 8008ab2: 4293 cmp r3, r2 8008ab4: d031 beq.n 8008b1a 8008ab6: 687b ldr r3, [r7, #4] 8008ab8: 681b ldr r3, [r3, #0] 8008aba: 4a4a ldr r2, [pc, #296] @ (8008be4 ) 8008abc: 4293 cmp r3, r2 8008abe: d02c beq.n 8008b1a 8008ac0: 687b ldr r3, [r7, #4] 8008ac2: 681b ldr r3, [r3, #0] 8008ac4: 4a48 ldr r2, [pc, #288] @ (8008be8 ) 8008ac6: 4293 cmp r3, r2 8008ac8: d027 beq.n 8008b1a 8008aca: 687b ldr r3, [r7, #4] 8008acc: 681b ldr r3, [r3, #0] 8008ace: 4a47 ldr r2, [pc, #284] @ (8008bec ) 8008ad0: 4293 cmp r3, r2 8008ad2: d022 beq.n 8008b1a 8008ad4: 687b ldr r3, [r7, #4] 8008ad6: 681b ldr r3, [r3, #0] 8008ad8: 4a45 ldr r2, [pc, #276] @ (8008bf0 ) 8008ada: 4293 cmp r3, r2 8008adc: d01d beq.n 8008b1a 8008ade: 687b ldr r3, [r7, #4] 8008ae0: 681b ldr r3, [r3, #0] 8008ae2: 4a44 ldr r2, [pc, #272] @ (8008bf4 ) 8008ae4: 4293 cmp r3, r2 8008ae6: d018 beq.n 8008b1a 8008ae8: 687b ldr r3, [r7, #4] 8008aea: 681b ldr r3, [r3, #0] 8008aec: 4a42 ldr r2, [pc, #264] @ (8008bf8 ) 8008aee: 4293 cmp r3, r2 8008af0: d013 beq.n 8008b1a 8008af2: 687b ldr r3, [r7, #4] 8008af4: 681b ldr r3, [r3, #0] 8008af6: 4a41 ldr r2, [pc, #260] @ (8008bfc ) 8008af8: 4293 cmp r3, r2 8008afa: d00e beq.n 8008b1a 8008afc: 687b ldr r3, [r7, #4] 8008afe: 681b ldr r3, [r3, #0] 8008b00: 4a3f ldr r2, [pc, #252] @ (8008c00 ) 8008b02: 4293 cmp r3, r2 8008b04: d009 beq.n 8008b1a 8008b06: 687b ldr r3, [r7, #4] 8008b08: 681b ldr r3, [r3, #0] 8008b0a: 4a3e ldr r2, [pc, #248] @ (8008c04 ) 8008b0c: 4293 cmp r3, r2 8008b0e: d004 beq.n 8008b1a 8008b10: 687b ldr r3, [r7, #4] 8008b12: 681b ldr r3, [r3, #0] 8008b14: 4a3c ldr r2, [pc, #240] @ (8008c08 ) 8008b16: 4293 cmp r3, r2 8008b18: d101 bne.n 8008b1e 8008b1a: 2301 movs r3, #1 8008b1c: e000 b.n 8008b20 8008b1e: 2300 movs r3, #0 8008b20: 2b00 cmp r3, #0 8008b22: d032 beq.n 8008b8a { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8008b24: 6878 ldr r0, [r7, #4] 8008b26: f002 fa43 bl 800afb0 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8008b2a: 687b ldr r3, [r7, #4] 8008b2c: 689b ldr r3, [r3, #8] 8008b2e: 2b80 cmp r3, #128 @ 0x80 8008b30: d102 bne.n 8008b38 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8008b32: 687b ldr r3, [r7, #4] 8008b34: 2200 movs r2, #0 8008b36: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8008b38: 687b ldr r3, [r7, #4] 8008b3a: 685a ldr r2, [r3, #4] 8008b3c: 687b ldr r3, [r7, #4] 8008b3e: 6e1b ldr r3, [r3, #96] @ 0x60 8008b40: b2d2 uxtb r2, r2 8008b42: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8008b44: 687b ldr r3, [r7, #4] 8008b46: 6e5b ldr r3, [r3, #100] @ 0x64 8008b48: 687a ldr r2, [r7, #4] 8008b4a: 6e92 ldr r2, [r2, #104] @ 0x68 8008b4c: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8008b4e: 687b ldr r3, [r7, #4] 8008b50: 685b ldr r3, [r3, #4] 8008b52: 2b00 cmp r3, #0 8008b54: d010 beq.n 8008b78 8008b56: 687b ldr r3, [r7, #4] 8008b58: 685b ldr r3, [r3, #4] 8008b5a: 2b08 cmp r3, #8 8008b5c: d80c bhi.n 8008b78 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8008b5e: 6878 ldr r0, [r7, #4] 8008b60: f002 fac0 bl 800b0e4 /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8008b64: 687b ldr r3, [r7, #4] 8008b66: 6edb ldr r3, [r3, #108] @ 0x6c 8008b68: 2200 movs r2, #0 8008b6a: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8008b6c: 687b ldr r3, [r7, #4] 8008b6e: 6f1b ldr r3, [r3, #112] @ 0x70 8008b70: 687a ldr r2, [r7, #4] 8008b72: 6f52 ldr r2, [r2, #116] @ 0x74 8008b74: 605a str r2, [r3, #4] 8008b76: e008 b.n 8008b8a } else { hdma->DMAmuxRequestGen = 0U; 8008b78: 687b ldr r3, [r7, #4] 8008b7a: 2200 movs r2, #0 8008b7c: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8008b7e: 687b ldr r3, [r7, #4] 8008b80: 2200 movs r2, #0 8008b82: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8008b84: 687b ldr r3, [r7, #4] 8008b86: 2200 movs r2, #0 8008b88: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008b8a: 687b ldr r3, [r7, #4] 8008b8c: 2200 movs r2, #0 8008b8e: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008b90: 687b ldr r3, [r7, #4] 8008b92: 2201 movs r2, #1 8008b94: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8008b98: 2300 movs r3, #0 } 8008b9a: 4618 mov r0, r3 8008b9c: 3718 adds r7, #24 8008b9e: 46bd mov sp, r7 8008ba0: bd80 pop {r7, pc} 8008ba2: bf00 nop 8008ba4: a7fdabf8 .word 0xa7fdabf8 8008ba8: cccccccd .word 0xcccccccd 8008bac: 40020010 .word 0x40020010 8008bb0: 40020028 .word 0x40020028 8008bb4: 40020040 .word 0x40020040 8008bb8: 40020058 .word 0x40020058 8008bbc: 40020070 .word 0x40020070 8008bc0: 40020088 .word 0x40020088 8008bc4: 400200a0 .word 0x400200a0 8008bc8: 400200b8 .word 0x400200b8 8008bcc: 40020410 .word 0x40020410 8008bd0: 40020428 .word 0x40020428 8008bd4: 40020440 .word 0x40020440 8008bd8: 40020458 .word 0x40020458 8008bdc: 40020470 .word 0x40020470 8008be0: 40020488 .word 0x40020488 8008be4: 400204a0 .word 0x400204a0 8008be8: 400204b8 .word 0x400204b8 8008bec: 58025408 .word 0x58025408 8008bf0: 5802541c .word 0x5802541c 8008bf4: 58025430 .word 0x58025430 8008bf8: 58025444 .word 0x58025444 8008bfc: 58025458 .word 0x58025458 8008c00: 5802546c .word 0x5802546c 8008c04: 58025480 .word 0x58025480 8008c08: 58025494 .word 0x58025494 08008c0c : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8008c0c: b580 push {r7, lr} 8008c0e: b086 sub sp, #24 8008c10: af00 add r7, sp, #0 8008c12: 60f8 str r0, [r7, #12] 8008c14: 60b9 str r1, [r7, #8] 8008c16: 607a str r2, [r7, #4] 8008c18: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8008c1a: 2300 movs r3, #0 8008c1c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Check the DMA peripheral handle */ if(hdma == NULL) 8008c1e: 68fb ldr r3, [r7, #12] 8008c20: 2b00 cmp r3, #0 8008c22: d101 bne.n 8008c28 { return HAL_ERROR; 8008c24: 2301 movs r3, #1 8008c26: e226 b.n 8009076 } /* Process locked */ __HAL_LOCK(hdma); 8008c28: 68fb ldr r3, [r7, #12] 8008c2a: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8008c2e: 2b01 cmp r3, #1 8008c30: d101 bne.n 8008c36 8008c32: 2302 movs r3, #2 8008c34: e21f b.n 8009076 8008c36: 68fb ldr r3, [r7, #12] 8008c38: 2201 movs r2, #1 8008c3a: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8008c3e: 68fb ldr r3, [r7, #12] 8008c40: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008c44: b2db uxtb r3, r3 8008c46: 2b01 cmp r3, #1 8008c48: f040 820a bne.w 8009060 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008c4c: 68fb ldr r3, [r7, #12] 8008c4e: 2202 movs r2, #2 8008c50: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008c54: 68fb ldr r3, [r7, #12] 8008c56: 2200 movs r2, #0 8008c58: 655a str r2, [r3, #84] @ 0x54 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8008c5a: 68fb ldr r3, [r7, #12] 8008c5c: 681b ldr r3, [r3, #0] 8008c5e: 4a68 ldr r2, [pc, #416] @ (8008e00 ) 8008c60: 4293 cmp r3, r2 8008c62: d04a beq.n 8008cfa 8008c64: 68fb ldr r3, [r7, #12] 8008c66: 681b ldr r3, [r3, #0] 8008c68: 4a66 ldr r2, [pc, #408] @ (8008e04 ) 8008c6a: 4293 cmp r3, r2 8008c6c: d045 beq.n 8008cfa 8008c6e: 68fb ldr r3, [r7, #12] 8008c70: 681b ldr r3, [r3, #0] 8008c72: 4a65 ldr r2, [pc, #404] @ (8008e08 ) 8008c74: 4293 cmp r3, r2 8008c76: d040 beq.n 8008cfa 8008c78: 68fb ldr r3, [r7, #12] 8008c7a: 681b ldr r3, [r3, #0] 8008c7c: 4a63 ldr r2, [pc, #396] @ (8008e0c ) 8008c7e: 4293 cmp r3, r2 8008c80: d03b beq.n 8008cfa 8008c82: 68fb ldr r3, [r7, #12] 8008c84: 681b ldr r3, [r3, #0] 8008c86: 4a62 ldr r2, [pc, #392] @ (8008e10 ) 8008c88: 4293 cmp r3, r2 8008c8a: d036 beq.n 8008cfa 8008c8c: 68fb ldr r3, [r7, #12] 8008c8e: 681b ldr r3, [r3, #0] 8008c90: 4a60 ldr r2, [pc, #384] @ (8008e14 ) 8008c92: 4293 cmp r3, r2 8008c94: d031 beq.n 8008cfa 8008c96: 68fb ldr r3, [r7, #12] 8008c98: 681b ldr r3, [r3, #0] 8008c9a: 4a5f ldr r2, [pc, #380] @ (8008e18 ) 8008c9c: 4293 cmp r3, r2 8008c9e: d02c beq.n 8008cfa 8008ca0: 68fb ldr r3, [r7, #12] 8008ca2: 681b ldr r3, [r3, #0] 8008ca4: 4a5d ldr r2, [pc, #372] @ (8008e1c ) 8008ca6: 4293 cmp r3, r2 8008ca8: d027 beq.n 8008cfa 8008caa: 68fb ldr r3, [r7, #12] 8008cac: 681b ldr r3, [r3, #0] 8008cae: 4a5c ldr r2, [pc, #368] @ (8008e20 ) 8008cb0: 4293 cmp r3, r2 8008cb2: d022 beq.n 8008cfa 8008cb4: 68fb ldr r3, [r7, #12] 8008cb6: 681b ldr r3, [r3, #0] 8008cb8: 4a5a ldr r2, [pc, #360] @ (8008e24 ) 8008cba: 4293 cmp r3, r2 8008cbc: d01d beq.n 8008cfa 8008cbe: 68fb ldr r3, [r7, #12] 8008cc0: 681b ldr r3, [r3, #0] 8008cc2: 4a59 ldr r2, [pc, #356] @ (8008e28 ) 8008cc4: 4293 cmp r3, r2 8008cc6: d018 beq.n 8008cfa 8008cc8: 68fb ldr r3, [r7, #12] 8008cca: 681b ldr r3, [r3, #0] 8008ccc: 4a57 ldr r2, [pc, #348] @ (8008e2c ) 8008cce: 4293 cmp r3, r2 8008cd0: d013 beq.n 8008cfa 8008cd2: 68fb ldr r3, [r7, #12] 8008cd4: 681b ldr r3, [r3, #0] 8008cd6: 4a56 ldr r2, [pc, #344] @ (8008e30 ) 8008cd8: 4293 cmp r3, r2 8008cda: d00e beq.n 8008cfa 8008cdc: 68fb ldr r3, [r7, #12] 8008cde: 681b ldr r3, [r3, #0] 8008ce0: 4a54 ldr r2, [pc, #336] @ (8008e34 ) 8008ce2: 4293 cmp r3, r2 8008ce4: d009 beq.n 8008cfa 8008ce6: 68fb ldr r3, [r7, #12] 8008ce8: 681b ldr r3, [r3, #0] 8008cea: 4a53 ldr r2, [pc, #332] @ (8008e38 ) 8008cec: 4293 cmp r3, r2 8008cee: d004 beq.n 8008cfa 8008cf0: 68fb ldr r3, [r7, #12] 8008cf2: 681b ldr r3, [r3, #0] 8008cf4: 4a51 ldr r2, [pc, #324] @ (8008e3c ) 8008cf6: 4293 cmp r3, r2 8008cf8: d108 bne.n 8008d0c 8008cfa: 68fb ldr r3, [r7, #12] 8008cfc: 681b ldr r3, [r3, #0] 8008cfe: 681a ldr r2, [r3, #0] 8008d00: 68fb ldr r3, [r7, #12] 8008d02: 681b ldr r3, [r3, #0] 8008d04: f022 0201 bic.w r2, r2, #1 8008d08: 601a str r2, [r3, #0] 8008d0a: e007 b.n 8008d1c 8008d0c: 68fb ldr r3, [r7, #12] 8008d0e: 681b ldr r3, [r3, #0] 8008d10: 681a ldr r2, [r3, #0] 8008d12: 68fb ldr r3, [r7, #12] 8008d14: 681b ldr r3, [r3, #0] 8008d16: f022 0201 bic.w r2, r2, #1 8008d1a: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8008d1c: 683b ldr r3, [r7, #0] 8008d1e: 687a ldr r2, [r7, #4] 8008d20: 68b9 ldr r1, [r7, #8] 8008d22: 68f8 ldr r0, [r7, #12] 8008d24: f001 fe6a bl 800a9fc if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008d28: 68fb ldr r3, [r7, #12] 8008d2a: 681b ldr r3, [r3, #0] 8008d2c: 4a34 ldr r2, [pc, #208] @ (8008e00 ) 8008d2e: 4293 cmp r3, r2 8008d30: d04a beq.n 8008dc8 8008d32: 68fb ldr r3, [r7, #12] 8008d34: 681b ldr r3, [r3, #0] 8008d36: 4a33 ldr r2, [pc, #204] @ (8008e04 ) 8008d38: 4293 cmp r3, r2 8008d3a: d045 beq.n 8008dc8 8008d3c: 68fb ldr r3, [r7, #12] 8008d3e: 681b ldr r3, [r3, #0] 8008d40: 4a31 ldr r2, [pc, #196] @ (8008e08 ) 8008d42: 4293 cmp r3, r2 8008d44: d040 beq.n 8008dc8 8008d46: 68fb ldr r3, [r7, #12] 8008d48: 681b ldr r3, [r3, #0] 8008d4a: 4a30 ldr r2, [pc, #192] @ (8008e0c ) 8008d4c: 4293 cmp r3, r2 8008d4e: d03b beq.n 8008dc8 8008d50: 68fb ldr r3, [r7, #12] 8008d52: 681b ldr r3, [r3, #0] 8008d54: 4a2e ldr r2, [pc, #184] @ (8008e10 ) 8008d56: 4293 cmp r3, r2 8008d58: d036 beq.n 8008dc8 8008d5a: 68fb ldr r3, [r7, #12] 8008d5c: 681b ldr r3, [r3, #0] 8008d5e: 4a2d ldr r2, [pc, #180] @ (8008e14 ) 8008d60: 4293 cmp r3, r2 8008d62: d031 beq.n 8008dc8 8008d64: 68fb ldr r3, [r7, #12] 8008d66: 681b ldr r3, [r3, #0] 8008d68: 4a2b ldr r2, [pc, #172] @ (8008e18 ) 8008d6a: 4293 cmp r3, r2 8008d6c: d02c beq.n 8008dc8 8008d6e: 68fb ldr r3, [r7, #12] 8008d70: 681b ldr r3, [r3, #0] 8008d72: 4a2a ldr r2, [pc, #168] @ (8008e1c ) 8008d74: 4293 cmp r3, r2 8008d76: d027 beq.n 8008dc8 8008d78: 68fb ldr r3, [r7, #12] 8008d7a: 681b ldr r3, [r3, #0] 8008d7c: 4a28 ldr r2, [pc, #160] @ (8008e20 ) 8008d7e: 4293 cmp r3, r2 8008d80: d022 beq.n 8008dc8 8008d82: 68fb ldr r3, [r7, #12] 8008d84: 681b ldr r3, [r3, #0] 8008d86: 4a27 ldr r2, [pc, #156] @ (8008e24 ) 8008d88: 4293 cmp r3, r2 8008d8a: d01d beq.n 8008dc8 8008d8c: 68fb ldr r3, [r7, #12] 8008d8e: 681b ldr r3, [r3, #0] 8008d90: 4a25 ldr r2, [pc, #148] @ (8008e28 ) 8008d92: 4293 cmp r3, r2 8008d94: d018 beq.n 8008dc8 8008d96: 68fb ldr r3, [r7, #12] 8008d98: 681b ldr r3, [r3, #0] 8008d9a: 4a24 ldr r2, [pc, #144] @ (8008e2c ) 8008d9c: 4293 cmp r3, r2 8008d9e: d013 beq.n 8008dc8 8008da0: 68fb ldr r3, [r7, #12] 8008da2: 681b ldr r3, [r3, #0] 8008da4: 4a22 ldr r2, [pc, #136] @ (8008e30 ) 8008da6: 4293 cmp r3, r2 8008da8: d00e beq.n 8008dc8 8008daa: 68fb ldr r3, [r7, #12] 8008dac: 681b ldr r3, [r3, #0] 8008dae: 4a21 ldr r2, [pc, #132] @ (8008e34 ) 8008db0: 4293 cmp r3, r2 8008db2: d009 beq.n 8008dc8 8008db4: 68fb ldr r3, [r7, #12] 8008db6: 681b ldr r3, [r3, #0] 8008db8: 4a1f ldr r2, [pc, #124] @ (8008e38 ) 8008dba: 4293 cmp r3, r2 8008dbc: d004 beq.n 8008dc8 8008dbe: 68fb ldr r3, [r7, #12] 8008dc0: 681b ldr r3, [r3, #0] 8008dc2: 4a1e ldr r2, [pc, #120] @ (8008e3c ) 8008dc4: 4293 cmp r3, r2 8008dc6: d101 bne.n 8008dcc 8008dc8: 2301 movs r3, #1 8008dca: e000 b.n 8008dce 8008dcc: 2300 movs r3, #0 8008dce: 2b00 cmp r3, #0 8008dd0: d036 beq.n 8008e40 { /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8008dd2: 68fb ldr r3, [r7, #12] 8008dd4: 681b ldr r3, [r3, #0] 8008dd6: 681b ldr r3, [r3, #0] 8008dd8: f023 021e bic.w r2, r3, #30 8008ddc: 68fb ldr r3, [r7, #12] 8008dde: 681b ldr r3, [r3, #0] 8008de0: f042 0216 orr.w r2, r2, #22 8008de4: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008de6: 68fb ldr r3, [r7, #12] 8008de8: 6c1b ldr r3, [r3, #64] @ 0x40 8008dea: 2b00 cmp r3, #0 8008dec: d03e beq.n 8008e6c { /* Enable Half Transfer IT if corresponding Callback is set */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 8008dee: 68fb ldr r3, [r7, #12] 8008df0: 681b ldr r3, [r3, #0] 8008df2: 681a ldr r2, [r3, #0] 8008df4: 68fb ldr r3, [r7, #12] 8008df6: 681b ldr r3, [r3, #0] 8008df8: f042 0208 orr.w r2, r2, #8 8008dfc: 601a str r2, [r3, #0] 8008dfe: e035 b.n 8008e6c 8008e00: 40020010 .word 0x40020010 8008e04: 40020028 .word 0x40020028 8008e08: 40020040 .word 0x40020040 8008e0c: 40020058 .word 0x40020058 8008e10: 40020070 .word 0x40020070 8008e14: 40020088 .word 0x40020088 8008e18: 400200a0 .word 0x400200a0 8008e1c: 400200b8 .word 0x400200b8 8008e20: 40020410 .word 0x40020410 8008e24: 40020428 .word 0x40020428 8008e28: 40020440 .word 0x40020440 8008e2c: 40020458 .word 0x40020458 8008e30: 40020470 .word 0x40020470 8008e34: 40020488 .word 0x40020488 8008e38: 400204a0 .word 0x400204a0 8008e3c: 400204b8 .word 0x400204b8 } } else /* BDMA channel */ { /* Enable Common interrupts */ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8008e40: 68fb ldr r3, [r7, #12] 8008e42: 681b ldr r3, [r3, #0] 8008e44: 681b ldr r3, [r3, #0] 8008e46: f023 020e bic.w r2, r3, #14 8008e4a: 68fb ldr r3, [r7, #12] 8008e4c: 681b ldr r3, [r3, #0] 8008e4e: f042 020a orr.w r2, r2, #10 8008e52: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008e54: 68fb ldr r3, [r7, #12] 8008e56: 6c1b ldr r3, [r3, #64] @ 0x40 8008e58: 2b00 cmp r3, #0 8008e5a: d007 beq.n 8008e6c { /*Enable Half Transfer IT if corresponding Callback is set */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 8008e5c: 68fb ldr r3, [r7, #12] 8008e5e: 681b ldr r3, [r3, #0] 8008e60: 681a ldr r2, [r3, #0] 8008e62: 68fb ldr r3, [r7, #12] 8008e64: 681b ldr r3, [r3, #0] 8008e66: f042 0204 orr.w r2, r2, #4 8008e6a: 601a str r2, [r3, #0] } } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008e6c: 68fb ldr r3, [r7, #12] 8008e6e: 681b ldr r3, [r3, #0] 8008e70: 4a83 ldr r2, [pc, #524] @ (8009080 ) 8008e72: 4293 cmp r3, r2 8008e74: d072 beq.n 8008f5c 8008e76: 68fb ldr r3, [r7, #12] 8008e78: 681b ldr r3, [r3, #0] 8008e7a: 4a82 ldr r2, [pc, #520] @ (8009084 ) 8008e7c: 4293 cmp r3, r2 8008e7e: d06d beq.n 8008f5c 8008e80: 68fb ldr r3, [r7, #12] 8008e82: 681b ldr r3, [r3, #0] 8008e84: 4a80 ldr r2, [pc, #512] @ (8009088 ) 8008e86: 4293 cmp r3, r2 8008e88: d068 beq.n 8008f5c 8008e8a: 68fb ldr r3, [r7, #12] 8008e8c: 681b ldr r3, [r3, #0] 8008e8e: 4a7f ldr r2, [pc, #508] @ (800908c ) 8008e90: 4293 cmp r3, r2 8008e92: d063 beq.n 8008f5c 8008e94: 68fb ldr r3, [r7, #12] 8008e96: 681b ldr r3, [r3, #0] 8008e98: 4a7d ldr r2, [pc, #500] @ (8009090 ) 8008e9a: 4293 cmp r3, r2 8008e9c: d05e beq.n 8008f5c 8008e9e: 68fb ldr r3, [r7, #12] 8008ea0: 681b ldr r3, [r3, #0] 8008ea2: 4a7c ldr r2, [pc, #496] @ (8009094 ) 8008ea4: 4293 cmp r3, r2 8008ea6: d059 beq.n 8008f5c 8008ea8: 68fb ldr r3, [r7, #12] 8008eaa: 681b ldr r3, [r3, #0] 8008eac: 4a7a ldr r2, [pc, #488] @ (8009098 ) 8008eae: 4293 cmp r3, r2 8008eb0: d054 beq.n 8008f5c 8008eb2: 68fb ldr r3, [r7, #12] 8008eb4: 681b ldr r3, [r3, #0] 8008eb6: 4a79 ldr r2, [pc, #484] @ (800909c ) 8008eb8: 4293 cmp r3, r2 8008eba: d04f beq.n 8008f5c 8008ebc: 68fb ldr r3, [r7, #12] 8008ebe: 681b ldr r3, [r3, #0] 8008ec0: 4a77 ldr r2, [pc, #476] @ (80090a0 ) 8008ec2: 4293 cmp r3, r2 8008ec4: d04a beq.n 8008f5c 8008ec6: 68fb ldr r3, [r7, #12] 8008ec8: 681b ldr r3, [r3, #0] 8008eca: 4a76 ldr r2, [pc, #472] @ (80090a4 ) 8008ecc: 4293 cmp r3, r2 8008ece: d045 beq.n 8008f5c 8008ed0: 68fb ldr r3, [r7, #12] 8008ed2: 681b ldr r3, [r3, #0] 8008ed4: 4a74 ldr r2, [pc, #464] @ (80090a8 ) 8008ed6: 4293 cmp r3, r2 8008ed8: d040 beq.n 8008f5c 8008eda: 68fb ldr r3, [r7, #12] 8008edc: 681b ldr r3, [r3, #0] 8008ede: 4a73 ldr r2, [pc, #460] @ (80090ac ) 8008ee0: 4293 cmp r3, r2 8008ee2: d03b beq.n 8008f5c 8008ee4: 68fb ldr r3, [r7, #12] 8008ee6: 681b ldr r3, [r3, #0] 8008ee8: 4a71 ldr r2, [pc, #452] @ (80090b0 ) 8008eea: 4293 cmp r3, r2 8008eec: d036 beq.n 8008f5c 8008eee: 68fb ldr r3, [r7, #12] 8008ef0: 681b ldr r3, [r3, #0] 8008ef2: 4a70 ldr r2, [pc, #448] @ (80090b4 ) 8008ef4: 4293 cmp r3, r2 8008ef6: d031 beq.n 8008f5c 8008ef8: 68fb ldr r3, [r7, #12] 8008efa: 681b ldr r3, [r3, #0] 8008efc: 4a6e ldr r2, [pc, #440] @ (80090b8 ) 8008efe: 4293 cmp r3, r2 8008f00: d02c beq.n 8008f5c 8008f02: 68fb ldr r3, [r7, #12] 8008f04: 681b ldr r3, [r3, #0] 8008f06: 4a6d ldr r2, [pc, #436] @ (80090bc ) 8008f08: 4293 cmp r3, r2 8008f0a: d027 beq.n 8008f5c 8008f0c: 68fb ldr r3, [r7, #12] 8008f0e: 681b ldr r3, [r3, #0] 8008f10: 4a6b ldr r2, [pc, #428] @ (80090c0 ) 8008f12: 4293 cmp r3, r2 8008f14: d022 beq.n 8008f5c 8008f16: 68fb ldr r3, [r7, #12] 8008f18: 681b ldr r3, [r3, #0] 8008f1a: 4a6a ldr r2, [pc, #424] @ (80090c4 ) 8008f1c: 4293 cmp r3, r2 8008f1e: d01d beq.n 8008f5c 8008f20: 68fb ldr r3, [r7, #12] 8008f22: 681b ldr r3, [r3, #0] 8008f24: 4a68 ldr r2, [pc, #416] @ (80090c8 ) 8008f26: 4293 cmp r3, r2 8008f28: d018 beq.n 8008f5c 8008f2a: 68fb ldr r3, [r7, #12] 8008f2c: 681b ldr r3, [r3, #0] 8008f2e: 4a67 ldr r2, [pc, #412] @ (80090cc ) 8008f30: 4293 cmp r3, r2 8008f32: d013 beq.n 8008f5c 8008f34: 68fb ldr r3, [r7, #12] 8008f36: 681b ldr r3, [r3, #0] 8008f38: 4a65 ldr r2, [pc, #404] @ (80090d0 ) 8008f3a: 4293 cmp r3, r2 8008f3c: d00e beq.n 8008f5c 8008f3e: 68fb ldr r3, [r7, #12] 8008f40: 681b ldr r3, [r3, #0] 8008f42: 4a64 ldr r2, [pc, #400] @ (80090d4 ) 8008f44: 4293 cmp r3, r2 8008f46: d009 beq.n 8008f5c 8008f48: 68fb ldr r3, [r7, #12] 8008f4a: 681b ldr r3, [r3, #0] 8008f4c: 4a62 ldr r2, [pc, #392] @ (80090d8 ) 8008f4e: 4293 cmp r3, r2 8008f50: d004 beq.n 8008f5c 8008f52: 68fb ldr r3, [r7, #12] 8008f54: 681b ldr r3, [r3, #0] 8008f56: 4a61 ldr r2, [pc, #388] @ (80090dc ) 8008f58: 4293 cmp r3, r2 8008f5a: d101 bne.n 8008f60 8008f5c: 2301 movs r3, #1 8008f5e: e000 b.n 8008f62 8008f60: 2300 movs r3, #0 8008f62: 2b00 cmp r3, #0 8008f64: d01a beq.n 8008f9c { /* Check if DMAMUX Synchronization is enabled */ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8008f66: 68fb ldr r3, [r7, #12] 8008f68: 6e1b ldr r3, [r3, #96] @ 0x60 8008f6a: 681b ldr r3, [r3, #0] 8008f6c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008f70: 2b00 cmp r3, #0 8008f72: d007 beq.n 8008f84 { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8008f74: 68fb ldr r3, [r7, #12] 8008f76: 6e1b ldr r3, [r3, #96] @ 0x60 8008f78: 681a ldr r2, [r3, #0] 8008f7a: 68fb ldr r3, [r7, #12] 8008f7c: 6e1b ldr r3, [r3, #96] @ 0x60 8008f7e: f442 7280 orr.w r2, r2, #256 @ 0x100 8008f82: 601a str r2, [r3, #0] } if(hdma->DMAmuxRequestGen != 0U) 8008f84: 68fb ldr r3, [r7, #12] 8008f86: 6edb ldr r3, [r3, #108] @ 0x6c 8008f88: 2b00 cmp r3, #0 8008f8a: d007 beq.n 8008f9c { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8008f8c: 68fb ldr r3, [r7, #12] 8008f8e: 6edb ldr r3, [r3, #108] @ 0x6c 8008f90: 681a ldr r2, [r3, #0] 8008f92: 68fb ldr r3, [r7, #12] 8008f94: 6edb ldr r3, [r3, #108] @ 0x6c 8008f96: f442 7280 orr.w r2, r2, #256 @ 0x100 8008f9a: 601a str r2, [r3, #0] } } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8008f9c: 68fb ldr r3, [r7, #12] 8008f9e: 681b ldr r3, [r3, #0] 8008fa0: 4a37 ldr r2, [pc, #220] @ (8009080 ) 8008fa2: 4293 cmp r3, r2 8008fa4: d04a beq.n 800903c 8008fa6: 68fb ldr r3, [r7, #12] 8008fa8: 681b ldr r3, [r3, #0] 8008faa: 4a36 ldr r2, [pc, #216] @ (8009084 ) 8008fac: 4293 cmp r3, r2 8008fae: d045 beq.n 800903c 8008fb0: 68fb ldr r3, [r7, #12] 8008fb2: 681b ldr r3, [r3, #0] 8008fb4: 4a34 ldr r2, [pc, #208] @ (8009088 ) 8008fb6: 4293 cmp r3, r2 8008fb8: d040 beq.n 800903c 8008fba: 68fb ldr r3, [r7, #12] 8008fbc: 681b ldr r3, [r3, #0] 8008fbe: 4a33 ldr r2, [pc, #204] @ (800908c ) 8008fc0: 4293 cmp r3, r2 8008fc2: d03b beq.n 800903c 8008fc4: 68fb ldr r3, [r7, #12] 8008fc6: 681b ldr r3, [r3, #0] 8008fc8: 4a31 ldr r2, [pc, #196] @ (8009090 ) 8008fca: 4293 cmp r3, r2 8008fcc: d036 beq.n 800903c 8008fce: 68fb ldr r3, [r7, #12] 8008fd0: 681b ldr r3, [r3, #0] 8008fd2: 4a30 ldr r2, [pc, #192] @ (8009094 ) 8008fd4: 4293 cmp r3, r2 8008fd6: d031 beq.n 800903c 8008fd8: 68fb ldr r3, [r7, #12] 8008fda: 681b ldr r3, [r3, #0] 8008fdc: 4a2e ldr r2, [pc, #184] @ (8009098 ) 8008fde: 4293 cmp r3, r2 8008fe0: d02c beq.n 800903c 8008fe2: 68fb ldr r3, [r7, #12] 8008fe4: 681b ldr r3, [r3, #0] 8008fe6: 4a2d ldr r2, [pc, #180] @ (800909c ) 8008fe8: 4293 cmp r3, r2 8008fea: d027 beq.n 800903c 8008fec: 68fb ldr r3, [r7, #12] 8008fee: 681b ldr r3, [r3, #0] 8008ff0: 4a2b ldr r2, [pc, #172] @ (80090a0 ) 8008ff2: 4293 cmp r3, r2 8008ff4: d022 beq.n 800903c 8008ff6: 68fb ldr r3, [r7, #12] 8008ff8: 681b ldr r3, [r3, #0] 8008ffa: 4a2a ldr r2, [pc, #168] @ (80090a4 ) 8008ffc: 4293 cmp r3, r2 8008ffe: d01d beq.n 800903c 8009000: 68fb ldr r3, [r7, #12] 8009002: 681b ldr r3, [r3, #0] 8009004: 4a28 ldr r2, [pc, #160] @ (80090a8 ) 8009006: 4293 cmp r3, r2 8009008: d018 beq.n 800903c 800900a: 68fb ldr r3, [r7, #12] 800900c: 681b ldr r3, [r3, #0] 800900e: 4a27 ldr r2, [pc, #156] @ (80090ac ) 8009010: 4293 cmp r3, r2 8009012: d013 beq.n 800903c 8009014: 68fb ldr r3, [r7, #12] 8009016: 681b ldr r3, [r3, #0] 8009018: 4a25 ldr r2, [pc, #148] @ (80090b0 ) 800901a: 4293 cmp r3, r2 800901c: d00e beq.n 800903c 800901e: 68fb ldr r3, [r7, #12] 8009020: 681b ldr r3, [r3, #0] 8009022: 4a24 ldr r2, [pc, #144] @ (80090b4 ) 8009024: 4293 cmp r3, r2 8009026: d009 beq.n 800903c 8009028: 68fb ldr r3, [r7, #12] 800902a: 681b ldr r3, [r3, #0] 800902c: 4a22 ldr r2, [pc, #136] @ (80090b8 ) 800902e: 4293 cmp r3, r2 8009030: d004 beq.n 800903c 8009032: 68fb ldr r3, [r7, #12] 8009034: 681b ldr r3, [r3, #0] 8009036: 4a21 ldr r2, [pc, #132] @ (80090bc ) 8009038: 4293 cmp r3, r2 800903a: d108 bne.n 800904e 800903c: 68fb ldr r3, [r7, #12] 800903e: 681b ldr r3, [r3, #0] 8009040: 681a ldr r2, [r3, #0] 8009042: 68fb ldr r3, [r7, #12] 8009044: 681b ldr r3, [r3, #0] 8009046: f042 0201 orr.w r2, r2, #1 800904a: 601a str r2, [r3, #0] 800904c: e012 b.n 8009074 800904e: 68fb ldr r3, [r7, #12] 8009050: 681b ldr r3, [r3, #0] 8009052: 681a ldr r2, [r3, #0] 8009054: 68fb ldr r3, [r7, #12] 8009056: 681b ldr r3, [r3, #0] 8009058: f042 0201 orr.w r2, r2, #1 800905c: 601a str r2, [r3, #0] 800905e: e009 b.n 8009074 } else { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8009060: 68fb ldr r3, [r7, #12] 8009062: f44f 6200 mov.w r2, #2048 @ 0x800 8009066: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hdma); 8009068: 68fb ldr r3, [r7, #12] 800906a: 2200 movs r2, #0 800906c: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_ERROR; 8009070: 2301 movs r3, #1 8009072: 75fb strb r3, [r7, #23] } return status; 8009074: 7dfb ldrb r3, [r7, #23] } 8009076: 4618 mov r0, r3 8009078: 3718 adds r7, #24 800907a: 46bd mov sp, r7 800907c: bd80 pop {r7, pc} 800907e: bf00 nop 8009080: 40020010 .word 0x40020010 8009084: 40020028 .word 0x40020028 8009088: 40020040 .word 0x40020040 800908c: 40020058 .word 0x40020058 8009090: 40020070 .word 0x40020070 8009094: 40020088 .word 0x40020088 8009098: 400200a0 .word 0x400200a0 800909c: 400200b8 .word 0x400200b8 80090a0: 40020410 .word 0x40020410 80090a4: 40020428 .word 0x40020428 80090a8: 40020440 .word 0x40020440 80090ac: 40020458 .word 0x40020458 80090b0: 40020470 .word 0x40020470 80090b4: 40020488 .word 0x40020488 80090b8: 400204a0 .word 0x400204a0 80090bc: 400204b8 .word 0x400204b8 80090c0: 58025408 .word 0x58025408 80090c4: 5802541c .word 0x5802541c 80090c8: 58025430 .word 0x58025430 80090cc: 58025444 .word 0x58025444 80090d0: 58025458 .word 0x58025458 80090d4: 5802546c .word 0x5802546c 80090d8: 58025480 .word 0x58025480 80090dc: 58025494 .word 0x58025494 080090e0 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80090e0: b580 push {r7, lr} 80090e2: b086 sub sp, #24 80090e4: af00 add r7, sp, #0 80090e6: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 80090e8: f7fc fe98 bl 8005e1c 80090ec: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 80090ee: 687b ldr r3, [r7, #4] 80090f0: 2b00 cmp r3, #0 80090f2: d101 bne.n 80090f8 { return HAL_ERROR; 80090f4: 2301 movs r3, #1 80090f6: e2dc b.n 80096b2 } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 80090f8: 687b ldr r3, [r7, #4] 80090fa: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 80090fe: b2db uxtb r3, r3 8009100: 2b02 cmp r3, #2 8009102: d008 beq.n 8009116 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8009104: 687b ldr r3, [r7, #4] 8009106: 2280 movs r2, #128 @ 0x80 8009108: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800910a: 687b ldr r3, [r7, #4] 800910c: 2200 movs r2, #0 800910e: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8009112: 2301 movs r3, #1 8009114: e2cd b.n 80096b2 } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009116: 687b ldr r3, [r7, #4] 8009118: 681b ldr r3, [r3, #0] 800911a: 4a76 ldr r2, [pc, #472] @ (80092f4 ) 800911c: 4293 cmp r3, r2 800911e: d04a beq.n 80091b6 8009120: 687b ldr r3, [r7, #4] 8009122: 681b ldr r3, [r3, #0] 8009124: 4a74 ldr r2, [pc, #464] @ (80092f8 ) 8009126: 4293 cmp r3, r2 8009128: d045 beq.n 80091b6 800912a: 687b ldr r3, [r7, #4] 800912c: 681b ldr r3, [r3, #0] 800912e: 4a73 ldr r2, [pc, #460] @ (80092fc ) 8009130: 4293 cmp r3, r2 8009132: d040 beq.n 80091b6 8009134: 687b ldr r3, [r7, #4] 8009136: 681b ldr r3, [r3, #0] 8009138: 4a71 ldr r2, [pc, #452] @ (8009300 ) 800913a: 4293 cmp r3, r2 800913c: d03b beq.n 80091b6 800913e: 687b ldr r3, [r7, #4] 8009140: 681b ldr r3, [r3, #0] 8009142: 4a70 ldr r2, [pc, #448] @ (8009304 ) 8009144: 4293 cmp r3, r2 8009146: d036 beq.n 80091b6 8009148: 687b ldr r3, [r7, #4] 800914a: 681b ldr r3, [r3, #0] 800914c: 4a6e ldr r2, [pc, #440] @ (8009308 ) 800914e: 4293 cmp r3, r2 8009150: d031 beq.n 80091b6 8009152: 687b ldr r3, [r7, #4] 8009154: 681b ldr r3, [r3, #0] 8009156: 4a6d ldr r2, [pc, #436] @ (800930c ) 8009158: 4293 cmp r3, r2 800915a: d02c beq.n 80091b6 800915c: 687b ldr r3, [r7, #4] 800915e: 681b ldr r3, [r3, #0] 8009160: 4a6b ldr r2, [pc, #428] @ (8009310 ) 8009162: 4293 cmp r3, r2 8009164: d027 beq.n 80091b6 8009166: 687b ldr r3, [r7, #4] 8009168: 681b ldr r3, [r3, #0] 800916a: 4a6a ldr r2, [pc, #424] @ (8009314 ) 800916c: 4293 cmp r3, r2 800916e: d022 beq.n 80091b6 8009170: 687b ldr r3, [r7, #4] 8009172: 681b ldr r3, [r3, #0] 8009174: 4a68 ldr r2, [pc, #416] @ (8009318 ) 8009176: 4293 cmp r3, r2 8009178: d01d beq.n 80091b6 800917a: 687b ldr r3, [r7, #4] 800917c: 681b ldr r3, [r3, #0] 800917e: 4a67 ldr r2, [pc, #412] @ (800931c ) 8009180: 4293 cmp r3, r2 8009182: d018 beq.n 80091b6 8009184: 687b ldr r3, [r7, #4] 8009186: 681b ldr r3, [r3, #0] 8009188: 4a65 ldr r2, [pc, #404] @ (8009320 ) 800918a: 4293 cmp r3, r2 800918c: d013 beq.n 80091b6 800918e: 687b ldr r3, [r7, #4] 8009190: 681b ldr r3, [r3, #0] 8009192: 4a64 ldr r2, [pc, #400] @ (8009324 ) 8009194: 4293 cmp r3, r2 8009196: d00e beq.n 80091b6 8009198: 687b ldr r3, [r7, #4] 800919a: 681b ldr r3, [r3, #0] 800919c: 4a62 ldr r2, [pc, #392] @ (8009328 ) 800919e: 4293 cmp r3, r2 80091a0: d009 beq.n 80091b6 80091a2: 687b ldr r3, [r7, #4] 80091a4: 681b ldr r3, [r3, #0] 80091a6: 4a61 ldr r2, [pc, #388] @ (800932c ) 80091a8: 4293 cmp r3, r2 80091aa: d004 beq.n 80091b6 80091ac: 687b ldr r3, [r7, #4] 80091ae: 681b ldr r3, [r3, #0] 80091b0: 4a5f ldr r2, [pc, #380] @ (8009330 ) 80091b2: 4293 cmp r3, r2 80091b4: d101 bne.n 80091ba 80091b6: 2301 movs r3, #1 80091b8: e000 b.n 80091bc 80091ba: 2300 movs r3, #0 80091bc: 2b00 cmp r3, #0 80091be: d013 beq.n 80091e8 { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80091c0: 687b ldr r3, [r7, #4] 80091c2: 681b ldr r3, [r3, #0] 80091c4: 681a ldr r2, [r3, #0] 80091c6: 687b ldr r3, [r7, #4] 80091c8: 681b ldr r3, [r3, #0] 80091ca: f022 021e bic.w r2, r2, #30 80091ce: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80091d0: 687b ldr r3, [r7, #4] 80091d2: 681b ldr r3, [r3, #0] 80091d4: 695a ldr r2, [r3, #20] 80091d6: 687b ldr r3, [r7, #4] 80091d8: 681b ldr r3, [r3, #0] 80091da: f022 0280 bic.w r2, r2, #128 @ 0x80 80091de: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 80091e0: 687b ldr r3, [r7, #4] 80091e2: 681b ldr r3, [r3, #0] 80091e4: 617b str r3, [r7, #20] 80091e6: e00a b.n 80091fe } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80091e8: 687b ldr r3, [r7, #4] 80091ea: 681b ldr r3, [r3, #0] 80091ec: 681a ldr r2, [r3, #0] 80091ee: 687b ldr r3, [r7, #4] 80091f0: 681b ldr r3, [r3, #0] 80091f2: f022 020e bic.w r2, r2, #14 80091f6: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 80091f8: 687b ldr r3, [r7, #4] 80091fa: 681b ldr r3, [r3, #0] 80091fc: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80091fe: 687b ldr r3, [r7, #4] 8009200: 681b ldr r3, [r3, #0] 8009202: 4a3c ldr r2, [pc, #240] @ (80092f4 ) 8009204: 4293 cmp r3, r2 8009206: d072 beq.n 80092ee 8009208: 687b ldr r3, [r7, #4] 800920a: 681b ldr r3, [r3, #0] 800920c: 4a3a ldr r2, [pc, #232] @ (80092f8 ) 800920e: 4293 cmp r3, r2 8009210: d06d beq.n 80092ee 8009212: 687b ldr r3, [r7, #4] 8009214: 681b ldr r3, [r3, #0] 8009216: 4a39 ldr r2, [pc, #228] @ (80092fc ) 8009218: 4293 cmp r3, r2 800921a: d068 beq.n 80092ee 800921c: 687b ldr r3, [r7, #4] 800921e: 681b ldr r3, [r3, #0] 8009220: 4a37 ldr r2, [pc, #220] @ (8009300 ) 8009222: 4293 cmp r3, r2 8009224: d063 beq.n 80092ee 8009226: 687b ldr r3, [r7, #4] 8009228: 681b ldr r3, [r3, #0] 800922a: 4a36 ldr r2, [pc, #216] @ (8009304 ) 800922c: 4293 cmp r3, r2 800922e: d05e beq.n 80092ee 8009230: 687b ldr r3, [r7, #4] 8009232: 681b ldr r3, [r3, #0] 8009234: 4a34 ldr r2, [pc, #208] @ (8009308 ) 8009236: 4293 cmp r3, r2 8009238: d059 beq.n 80092ee 800923a: 687b ldr r3, [r7, #4] 800923c: 681b ldr r3, [r3, #0] 800923e: 4a33 ldr r2, [pc, #204] @ (800930c ) 8009240: 4293 cmp r3, r2 8009242: d054 beq.n 80092ee 8009244: 687b ldr r3, [r7, #4] 8009246: 681b ldr r3, [r3, #0] 8009248: 4a31 ldr r2, [pc, #196] @ (8009310 ) 800924a: 4293 cmp r3, r2 800924c: d04f beq.n 80092ee 800924e: 687b ldr r3, [r7, #4] 8009250: 681b ldr r3, [r3, #0] 8009252: 4a30 ldr r2, [pc, #192] @ (8009314 ) 8009254: 4293 cmp r3, r2 8009256: d04a beq.n 80092ee 8009258: 687b ldr r3, [r7, #4] 800925a: 681b ldr r3, [r3, #0] 800925c: 4a2e ldr r2, [pc, #184] @ (8009318 ) 800925e: 4293 cmp r3, r2 8009260: d045 beq.n 80092ee 8009262: 687b ldr r3, [r7, #4] 8009264: 681b ldr r3, [r3, #0] 8009266: 4a2d ldr r2, [pc, #180] @ (800931c ) 8009268: 4293 cmp r3, r2 800926a: d040 beq.n 80092ee 800926c: 687b ldr r3, [r7, #4] 800926e: 681b ldr r3, [r3, #0] 8009270: 4a2b ldr r2, [pc, #172] @ (8009320 ) 8009272: 4293 cmp r3, r2 8009274: d03b beq.n 80092ee 8009276: 687b ldr r3, [r7, #4] 8009278: 681b ldr r3, [r3, #0] 800927a: 4a2a ldr r2, [pc, #168] @ (8009324 ) 800927c: 4293 cmp r3, r2 800927e: d036 beq.n 80092ee 8009280: 687b ldr r3, [r7, #4] 8009282: 681b ldr r3, [r3, #0] 8009284: 4a28 ldr r2, [pc, #160] @ (8009328 ) 8009286: 4293 cmp r3, r2 8009288: d031 beq.n 80092ee 800928a: 687b ldr r3, [r7, #4] 800928c: 681b ldr r3, [r3, #0] 800928e: 4a27 ldr r2, [pc, #156] @ (800932c ) 8009290: 4293 cmp r3, r2 8009292: d02c beq.n 80092ee 8009294: 687b ldr r3, [r7, #4] 8009296: 681b ldr r3, [r3, #0] 8009298: 4a25 ldr r2, [pc, #148] @ (8009330 ) 800929a: 4293 cmp r3, r2 800929c: d027 beq.n 80092ee 800929e: 687b ldr r3, [r7, #4] 80092a0: 681b ldr r3, [r3, #0] 80092a2: 4a24 ldr r2, [pc, #144] @ (8009334 ) 80092a4: 4293 cmp r3, r2 80092a6: d022 beq.n 80092ee 80092a8: 687b ldr r3, [r7, #4] 80092aa: 681b ldr r3, [r3, #0] 80092ac: 4a22 ldr r2, [pc, #136] @ (8009338 ) 80092ae: 4293 cmp r3, r2 80092b0: d01d beq.n 80092ee 80092b2: 687b ldr r3, [r7, #4] 80092b4: 681b ldr r3, [r3, #0] 80092b6: 4a21 ldr r2, [pc, #132] @ (800933c ) 80092b8: 4293 cmp r3, r2 80092ba: d018 beq.n 80092ee 80092bc: 687b ldr r3, [r7, #4] 80092be: 681b ldr r3, [r3, #0] 80092c0: 4a1f ldr r2, [pc, #124] @ (8009340 ) 80092c2: 4293 cmp r3, r2 80092c4: d013 beq.n 80092ee 80092c6: 687b ldr r3, [r7, #4] 80092c8: 681b ldr r3, [r3, #0] 80092ca: 4a1e ldr r2, [pc, #120] @ (8009344 ) 80092cc: 4293 cmp r3, r2 80092ce: d00e beq.n 80092ee 80092d0: 687b ldr r3, [r7, #4] 80092d2: 681b ldr r3, [r3, #0] 80092d4: 4a1c ldr r2, [pc, #112] @ (8009348 ) 80092d6: 4293 cmp r3, r2 80092d8: d009 beq.n 80092ee 80092da: 687b ldr r3, [r7, #4] 80092dc: 681b ldr r3, [r3, #0] 80092de: 4a1b ldr r2, [pc, #108] @ (800934c ) 80092e0: 4293 cmp r3, r2 80092e2: d004 beq.n 80092ee 80092e4: 687b ldr r3, [r7, #4] 80092e6: 681b ldr r3, [r3, #0] 80092e8: 4a19 ldr r2, [pc, #100] @ (8009350 ) 80092ea: 4293 cmp r3, r2 80092ec: d132 bne.n 8009354 80092ee: 2301 movs r3, #1 80092f0: e031 b.n 8009356 80092f2: bf00 nop 80092f4: 40020010 .word 0x40020010 80092f8: 40020028 .word 0x40020028 80092fc: 40020040 .word 0x40020040 8009300: 40020058 .word 0x40020058 8009304: 40020070 .word 0x40020070 8009308: 40020088 .word 0x40020088 800930c: 400200a0 .word 0x400200a0 8009310: 400200b8 .word 0x400200b8 8009314: 40020410 .word 0x40020410 8009318: 40020428 .word 0x40020428 800931c: 40020440 .word 0x40020440 8009320: 40020458 .word 0x40020458 8009324: 40020470 .word 0x40020470 8009328: 40020488 .word 0x40020488 800932c: 400204a0 .word 0x400204a0 8009330: 400204b8 .word 0x400204b8 8009334: 58025408 .word 0x58025408 8009338: 5802541c .word 0x5802541c 800933c: 58025430 .word 0x58025430 8009340: 58025444 .word 0x58025444 8009344: 58025458 .word 0x58025458 8009348: 5802546c .word 0x5802546c 800934c: 58025480 .word 0x58025480 8009350: 58025494 .word 0x58025494 8009354: 2300 movs r3, #0 8009356: 2b00 cmp r3, #0 8009358: d007 beq.n 800936a { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 800935a: 687b ldr r3, [r7, #4] 800935c: 6e1b ldr r3, [r3, #96] @ 0x60 800935e: 681a ldr r2, [r3, #0] 8009360: 687b ldr r3, [r7, #4] 8009362: 6e1b ldr r3, [r3, #96] @ 0x60 8009364: f422 7280 bic.w r2, r2, #256 @ 0x100 8009368: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800936a: 687b ldr r3, [r7, #4] 800936c: 681b ldr r3, [r3, #0] 800936e: 4a6d ldr r2, [pc, #436] @ (8009524 ) 8009370: 4293 cmp r3, r2 8009372: d04a beq.n 800940a 8009374: 687b ldr r3, [r7, #4] 8009376: 681b ldr r3, [r3, #0] 8009378: 4a6b ldr r2, [pc, #428] @ (8009528 ) 800937a: 4293 cmp r3, r2 800937c: d045 beq.n 800940a 800937e: 687b ldr r3, [r7, #4] 8009380: 681b ldr r3, [r3, #0] 8009382: 4a6a ldr r2, [pc, #424] @ (800952c ) 8009384: 4293 cmp r3, r2 8009386: d040 beq.n 800940a 8009388: 687b ldr r3, [r7, #4] 800938a: 681b ldr r3, [r3, #0] 800938c: 4a68 ldr r2, [pc, #416] @ (8009530 ) 800938e: 4293 cmp r3, r2 8009390: d03b beq.n 800940a 8009392: 687b ldr r3, [r7, #4] 8009394: 681b ldr r3, [r3, #0] 8009396: 4a67 ldr r2, [pc, #412] @ (8009534 ) 8009398: 4293 cmp r3, r2 800939a: d036 beq.n 800940a 800939c: 687b ldr r3, [r7, #4] 800939e: 681b ldr r3, [r3, #0] 80093a0: 4a65 ldr r2, [pc, #404] @ (8009538 ) 80093a2: 4293 cmp r3, r2 80093a4: d031 beq.n 800940a 80093a6: 687b ldr r3, [r7, #4] 80093a8: 681b ldr r3, [r3, #0] 80093aa: 4a64 ldr r2, [pc, #400] @ (800953c ) 80093ac: 4293 cmp r3, r2 80093ae: d02c beq.n 800940a 80093b0: 687b ldr r3, [r7, #4] 80093b2: 681b ldr r3, [r3, #0] 80093b4: 4a62 ldr r2, [pc, #392] @ (8009540 ) 80093b6: 4293 cmp r3, r2 80093b8: d027 beq.n 800940a 80093ba: 687b ldr r3, [r7, #4] 80093bc: 681b ldr r3, [r3, #0] 80093be: 4a61 ldr r2, [pc, #388] @ (8009544 ) 80093c0: 4293 cmp r3, r2 80093c2: d022 beq.n 800940a 80093c4: 687b ldr r3, [r7, #4] 80093c6: 681b ldr r3, [r3, #0] 80093c8: 4a5f ldr r2, [pc, #380] @ (8009548 ) 80093ca: 4293 cmp r3, r2 80093cc: d01d beq.n 800940a 80093ce: 687b ldr r3, [r7, #4] 80093d0: 681b ldr r3, [r3, #0] 80093d2: 4a5e ldr r2, [pc, #376] @ (800954c ) 80093d4: 4293 cmp r3, r2 80093d6: d018 beq.n 800940a 80093d8: 687b ldr r3, [r7, #4] 80093da: 681b ldr r3, [r3, #0] 80093dc: 4a5c ldr r2, [pc, #368] @ (8009550 ) 80093de: 4293 cmp r3, r2 80093e0: d013 beq.n 800940a 80093e2: 687b ldr r3, [r7, #4] 80093e4: 681b ldr r3, [r3, #0] 80093e6: 4a5b ldr r2, [pc, #364] @ (8009554 ) 80093e8: 4293 cmp r3, r2 80093ea: d00e beq.n 800940a 80093ec: 687b ldr r3, [r7, #4] 80093ee: 681b ldr r3, [r3, #0] 80093f0: 4a59 ldr r2, [pc, #356] @ (8009558 ) 80093f2: 4293 cmp r3, r2 80093f4: d009 beq.n 800940a 80093f6: 687b ldr r3, [r7, #4] 80093f8: 681b ldr r3, [r3, #0] 80093fa: 4a58 ldr r2, [pc, #352] @ (800955c ) 80093fc: 4293 cmp r3, r2 80093fe: d004 beq.n 800940a 8009400: 687b ldr r3, [r7, #4] 8009402: 681b ldr r3, [r3, #0] 8009404: 4a56 ldr r2, [pc, #344] @ (8009560 ) 8009406: 4293 cmp r3, r2 8009408: d108 bne.n 800941c 800940a: 687b ldr r3, [r7, #4] 800940c: 681b ldr r3, [r3, #0] 800940e: 681a ldr r2, [r3, #0] 8009410: 687b ldr r3, [r7, #4] 8009412: 681b ldr r3, [r3, #0] 8009414: f022 0201 bic.w r2, r2, #1 8009418: 601a str r2, [r3, #0] 800941a: e007 b.n 800942c 800941c: 687b ldr r3, [r7, #4] 800941e: 681b ldr r3, [r3, #0] 8009420: 681a ldr r2, [r3, #0] 8009422: 687b ldr r3, [r7, #4] 8009424: 681b ldr r3, [r3, #0] 8009426: f022 0201 bic.w r2, r2, #1 800942a: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 800942c: e013 b.n 8009456 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 800942e: f7fc fcf5 bl 8005e1c 8009432: 4602 mov r2, r0 8009434: 693b ldr r3, [r7, #16] 8009436: 1ad3 subs r3, r2, r3 8009438: 2b05 cmp r3, #5 800943a: d90c bls.n 8009456 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 800943c: 687b ldr r3, [r7, #4] 800943e: 2220 movs r2, #32 8009440: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8009442: 687b ldr r3, [r7, #4] 8009444: 2203 movs r2, #3 8009446: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800944a: 687b ldr r3, [r7, #4] 800944c: 2200 movs r2, #0 800944e: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 8009452: 2301 movs r3, #1 8009454: e12d b.n 80096b2 while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8009456: 697b ldr r3, [r7, #20] 8009458: 681b ldr r3, [r3, #0] 800945a: f003 0301 and.w r3, r3, #1 800945e: 2b00 cmp r3, #0 8009460: d1e5 bne.n 800942e } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009462: 687b ldr r3, [r7, #4] 8009464: 681b ldr r3, [r3, #0] 8009466: 4a2f ldr r2, [pc, #188] @ (8009524 ) 8009468: 4293 cmp r3, r2 800946a: d04a beq.n 8009502 800946c: 687b ldr r3, [r7, #4] 800946e: 681b ldr r3, [r3, #0] 8009470: 4a2d ldr r2, [pc, #180] @ (8009528 ) 8009472: 4293 cmp r3, r2 8009474: d045 beq.n 8009502 8009476: 687b ldr r3, [r7, #4] 8009478: 681b ldr r3, [r3, #0] 800947a: 4a2c ldr r2, [pc, #176] @ (800952c ) 800947c: 4293 cmp r3, r2 800947e: d040 beq.n 8009502 8009480: 687b ldr r3, [r7, #4] 8009482: 681b ldr r3, [r3, #0] 8009484: 4a2a ldr r2, [pc, #168] @ (8009530 ) 8009486: 4293 cmp r3, r2 8009488: d03b beq.n 8009502 800948a: 687b ldr r3, [r7, #4] 800948c: 681b ldr r3, [r3, #0] 800948e: 4a29 ldr r2, [pc, #164] @ (8009534 ) 8009490: 4293 cmp r3, r2 8009492: d036 beq.n 8009502 8009494: 687b ldr r3, [r7, #4] 8009496: 681b ldr r3, [r3, #0] 8009498: 4a27 ldr r2, [pc, #156] @ (8009538 ) 800949a: 4293 cmp r3, r2 800949c: d031 beq.n 8009502 800949e: 687b ldr r3, [r7, #4] 80094a0: 681b ldr r3, [r3, #0] 80094a2: 4a26 ldr r2, [pc, #152] @ (800953c ) 80094a4: 4293 cmp r3, r2 80094a6: d02c beq.n 8009502 80094a8: 687b ldr r3, [r7, #4] 80094aa: 681b ldr r3, [r3, #0] 80094ac: 4a24 ldr r2, [pc, #144] @ (8009540 ) 80094ae: 4293 cmp r3, r2 80094b0: d027 beq.n 8009502 80094b2: 687b ldr r3, [r7, #4] 80094b4: 681b ldr r3, [r3, #0] 80094b6: 4a23 ldr r2, [pc, #140] @ (8009544 ) 80094b8: 4293 cmp r3, r2 80094ba: d022 beq.n 8009502 80094bc: 687b ldr r3, [r7, #4] 80094be: 681b ldr r3, [r3, #0] 80094c0: 4a21 ldr r2, [pc, #132] @ (8009548 ) 80094c2: 4293 cmp r3, r2 80094c4: d01d beq.n 8009502 80094c6: 687b ldr r3, [r7, #4] 80094c8: 681b ldr r3, [r3, #0] 80094ca: 4a20 ldr r2, [pc, #128] @ (800954c ) 80094cc: 4293 cmp r3, r2 80094ce: d018 beq.n 8009502 80094d0: 687b ldr r3, [r7, #4] 80094d2: 681b ldr r3, [r3, #0] 80094d4: 4a1e ldr r2, [pc, #120] @ (8009550 ) 80094d6: 4293 cmp r3, r2 80094d8: d013 beq.n 8009502 80094da: 687b ldr r3, [r7, #4] 80094dc: 681b ldr r3, [r3, #0] 80094de: 4a1d ldr r2, [pc, #116] @ (8009554 ) 80094e0: 4293 cmp r3, r2 80094e2: d00e beq.n 8009502 80094e4: 687b ldr r3, [r7, #4] 80094e6: 681b ldr r3, [r3, #0] 80094e8: 4a1b ldr r2, [pc, #108] @ (8009558 ) 80094ea: 4293 cmp r3, r2 80094ec: d009 beq.n 8009502 80094ee: 687b ldr r3, [r7, #4] 80094f0: 681b ldr r3, [r3, #0] 80094f2: 4a1a ldr r2, [pc, #104] @ (800955c ) 80094f4: 4293 cmp r3, r2 80094f6: d004 beq.n 8009502 80094f8: 687b ldr r3, [r7, #4] 80094fa: 681b ldr r3, [r3, #0] 80094fc: 4a18 ldr r2, [pc, #96] @ (8009560 ) 80094fe: 4293 cmp r3, r2 8009500: d101 bne.n 8009506 8009502: 2301 movs r3, #1 8009504: e000 b.n 8009508 8009506: 2300 movs r3, #0 8009508: 2b00 cmp r3, #0 800950a: d02b beq.n 8009564 { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800950c: 687b ldr r3, [r7, #4] 800950e: 6d9b ldr r3, [r3, #88] @ 0x58 8009510: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8009512: 687b ldr r3, [r7, #4] 8009514: 6ddb ldr r3, [r3, #92] @ 0x5c 8009516: f003 031f and.w r3, r3, #31 800951a: 223f movs r2, #63 @ 0x3f 800951c: 409a lsls r2, r3 800951e: 68bb ldr r3, [r7, #8] 8009520: 609a str r2, [r3, #8] 8009522: e02a b.n 800957a 8009524: 40020010 .word 0x40020010 8009528: 40020028 .word 0x40020028 800952c: 40020040 .word 0x40020040 8009530: 40020058 .word 0x40020058 8009534: 40020070 .word 0x40020070 8009538: 40020088 .word 0x40020088 800953c: 400200a0 .word 0x400200a0 8009540: 400200b8 .word 0x400200b8 8009544: 40020410 .word 0x40020410 8009548: 40020428 .word 0x40020428 800954c: 40020440 .word 0x40020440 8009550: 40020458 .word 0x40020458 8009554: 40020470 .word 0x40020470 8009558: 40020488 .word 0x40020488 800955c: 400204a0 .word 0x400204a0 8009560: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009564: 687b ldr r3, [r7, #4] 8009566: 6d9b ldr r3, [r3, #88] @ 0x58 8009568: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 800956a: 687b ldr r3, [r7, #4] 800956c: 6ddb ldr r3, [r3, #92] @ 0x5c 800956e: f003 031f and.w r3, r3, #31 8009572: 2201 movs r2, #1 8009574: 409a lsls r2, r3 8009576: 68fb ldr r3, [r7, #12] 8009578: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800957a: 687b ldr r3, [r7, #4] 800957c: 681b ldr r3, [r3, #0] 800957e: 4a4f ldr r2, [pc, #316] @ (80096bc ) 8009580: 4293 cmp r3, r2 8009582: d072 beq.n 800966a 8009584: 687b ldr r3, [r7, #4] 8009586: 681b ldr r3, [r3, #0] 8009588: 4a4d ldr r2, [pc, #308] @ (80096c0 ) 800958a: 4293 cmp r3, r2 800958c: d06d beq.n 800966a 800958e: 687b ldr r3, [r7, #4] 8009590: 681b ldr r3, [r3, #0] 8009592: 4a4c ldr r2, [pc, #304] @ (80096c4 ) 8009594: 4293 cmp r3, r2 8009596: d068 beq.n 800966a 8009598: 687b ldr r3, [r7, #4] 800959a: 681b ldr r3, [r3, #0] 800959c: 4a4a ldr r2, [pc, #296] @ (80096c8 ) 800959e: 4293 cmp r3, r2 80095a0: d063 beq.n 800966a 80095a2: 687b ldr r3, [r7, #4] 80095a4: 681b ldr r3, [r3, #0] 80095a6: 4a49 ldr r2, [pc, #292] @ (80096cc ) 80095a8: 4293 cmp r3, r2 80095aa: d05e beq.n 800966a 80095ac: 687b ldr r3, [r7, #4] 80095ae: 681b ldr r3, [r3, #0] 80095b0: 4a47 ldr r2, [pc, #284] @ (80096d0 ) 80095b2: 4293 cmp r3, r2 80095b4: d059 beq.n 800966a 80095b6: 687b ldr r3, [r7, #4] 80095b8: 681b ldr r3, [r3, #0] 80095ba: 4a46 ldr r2, [pc, #280] @ (80096d4 ) 80095bc: 4293 cmp r3, r2 80095be: d054 beq.n 800966a 80095c0: 687b ldr r3, [r7, #4] 80095c2: 681b ldr r3, [r3, #0] 80095c4: 4a44 ldr r2, [pc, #272] @ (80096d8 ) 80095c6: 4293 cmp r3, r2 80095c8: d04f beq.n 800966a 80095ca: 687b ldr r3, [r7, #4] 80095cc: 681b ldr r3, [r3, #0] 80095ce: 4a43 ldr r2, [pc, #268] @ (80096dc ) 80095d0: 4293 cmp r3, r2 80095d2: d04a beq.n 800966a 80095d4: 687b ldr r3, [r7, #4] 80095d6: 681b ldr r3, [r3, #0] 80095d8: 4a41 ldr r2, [pc, #260] @ (80096e0 ) 80095da: 4293 cmp r3, r2 80095dc: d045 beq.n 800966a 80095de: 687b ldr r3, [r7, #4] 80095e0: 681b ldr r3, [r3, #0] 80095e2: 4a40 ldr r2, [pc, #256] @ (80096e4 ) 80095e4: 4293 cmp r3, r2 80095e6: d040 beq.n 800966a 80095e8: 687b ldr r3, [r7, #4] 80095ea: 681b ldr r3, [r3, #0] 80095ec: 4a3e ldr r2, [pc, #248] @ (80096e8 ) 80095ee: 4293 cmp r3, r2 80095f0: d03b beq.n 800966a 80095f2: 687b ldr r3, [r7, #4] 80095f4: 681b ldr r3, [r3, #0] 80095f6: 4a3d ldr r2, [pc, #244] @ (80096ec ) 80095f8: 4293 cmp r3, r2 80095fa: d036 beq.n 800966a 80095fc: 687b ldr r3, [r7, #4] 80095fe: 681b ldr r3, [r3, #0] 8009600: 4a3b ldr r2, [pc, #236] @ (80096f0 ) 8009602: 4293 cmp r3, r2 8009604: d031 beq.n 800966a 8009606: 687b ldr r3, [r7, #4] 8009608: 681b ldr r3, [r3, #0] 800960a: 4a3a ldr r2, [pc, #232] @ (80096f4 ) 800960c: 4293 cmp r3, r2 800960e: d02c beq.n 800966a 8009610: 687b ldr r3, [r7, #4] 8009612: 681b ldr r3, [r3, #0] 8009614: 4a38 ldr r2, [pc, #224] @ (80096f8 ) 8009616: 4293 cmp r3, r2 8009618: d027 beq.n 800966a 800961a: 687b ldr r3, [r7, #4] 800961c: 681b ldr r3, [r3, #0] 800961e: 4a37 ldr r2, [pc, #220] @ (80096fc ) 8009620: 4293 cmp r3, r2 8009622: d022 beq.n 800966a 8009624: 687b ldr r3, [r7, #4] 8009626: 681b ldr r3, [r3, #0] 8009628: 4a35 ldr r2, [pc, #212] @ (8009700 ) 800962a: 4293 cmp r3, r2 800962c: d01d beq.n 800966a 800962e: 687b ldr r3, [r7, #4] 8009630: 681b ldr r3, [r3, #0] 8009632: 4a34 ldr r2, [pc, #208] @ (8009704 ) 8009634: 4293 cmp r3, r2 8009636: d018 beq.n 800966a 8009638: 687b ldr r3, [r7, #4] 800963a: 681b ldr r3, [r3, #0] 800963c: 4a32 ldr r2, [pc, #200] @ (8009708 ) 800963e: 4293 cmp r3, r2 8009640: d013 beq.n 800966a 8009642: 687b ldr r3, [r7, #4] 8009644: 681b ldr r3, [r3, #0] 8009646: 4a31 ldr r2, [pc, #196] @ (800970c ) 8009648: 4293 cmp r3, r2 800964a: d00e beq.n 800966a 800964c: 687b ldr r3, [r7, #4] 800964e: 681b ldr r3, [r3, #0] 8009650: 4a2f ldr r2, [pc, #188] @ (8009710 ) 8009652: 4293 cmp r3, r2 8009654: d009 beq.n 800966a 8009656: 687b ldr r3, [r7, #4] 8009658: 681b ldr r3, [r3, #0] 800965a: 4a2e ldr r2, [pc, #184] @ (8009714 ) 800965c: 4293 cmp r3, r2 800965e: d004 beq.n 800966a 8009660: 687b ldr r3, [r7, #4] 8009662: 681b ldr r3, [r3, #0] 8009664: 4a2c ldr r2, [pc, #176] @ (8009718 ) 8009666: 4293 cmp r3, r2 8009668: d101 bne.n 800966e 800966a: 2301 movs r3, #1 800966c: e000 b.n 8009670 800966e: 2300 movs r3, #0 8009670: 2b00 cmp r3, #0 8009672: d015 beq.n 80096a0 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009674: 687b ldr r3, [r7, #4] 8009676: 6e5b ldr r3, [r3, #100] @ 0x64 8009678: 687a ldr r2, [r7, #4] 800967a: 6e92 ldr r2, [r2, #104] @ 0x68 800967c: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800967e: 687b ldr r3, [r7, #4] 8009680: 6edb ldr r3, [r3, #108] @ 0x6c 8009682: 2b00 cmp r3, #0 8009684: d00c beq.n 80096a0 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8009686: 687b ldr r3, [r7, #4] 8009688: 6edb ldr r3, [r3, #108] @ 0x6c 800968a: 681a ldr r2, [r3, #0] 800968c: 687b ldr r3, [r7, #4] 800968e: 6edb ldr r3, [r3, #108] @ 0x6c 8009690: f422 7280 bic.w r2, r2, #256 @ 0x100 8009694: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009696: 687b ldr r3, [r7, #4] 8009698: 6f1b ldr r3, [r3, #112] @ 0x70 800969a: 687a ldr r2, [r7, #4] 800969c: 6f52 ldr r2, [r2, #116] @ 0x74 800969e: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80096a0: 687b ldr r3, [r7, #4] 80096a2: 2201 movs r2, #1 80096a4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80096a8: 687b ldr r3, [r7, #4] 80096aa: 2200 movs r2, #0 80096ac: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 80096b0: 2300 movs r3, #0 } 80096b2: 4618 mov r0, r3 80096b4: 3718 adds r7, #24 80096b6: 46bd mov sp, r7 80096b8: bd80 pop {r7, pc} 80096ba: bf00 nop 80096bc: 40020010 .word 0x40020010 80096c0: 40020028 .word 0x40020028 80096c4: 40020040 .word 0x40020040 80096c8: 40020058 .word 0x40020058 80096cc: 40020070 .word 0x40020070 80096d0: 40020088 .word 0x40020088 80096d4: 400200a0 .word 0x400200a0 80096d8: 400200b8 .word 0x400200b8 80096dc: 40020410 .word 0x40020410 80096e0: 40020428 .word 0x40020428 80096e4: 40020440 .word 0x40020440 80096e8: 40020458 .word 0x40020458 80096ec: 40020470 .word 0x40020470 80096f0: 40020488 .word 0x40020488 80096f4: 400204a0 .word 0x400204a0 80096f8: 400204b8 .word 0x400204b8 80096fc: 58025408 .word 0x58025408 8009700: 5802541c .word 0x5802541c 8009704: 58025430 .word 0x58025430 8009708: 58025444 .word 0x58025444 800970c: 58025458 .word 0x58025458 8009710: 5802546c .word 0x5802546c 8009714: 58025480 .word 0x58025480 8009718: 58025494 .word 0x58025494 0800971c : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 800971c: b580 push {r7, lr} 800971e: b084 sub sp, #16 8009720: af00 add r7, sp, #0 8009722: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 8009724: 687b ldr r3, [r7, #4] 8009726: 2b00 cmp r3, #0 8009728: d101 bne.n 800972e { return HAL_ERROR; 800972a: 2301 movs r3, #1 800972c: e237 b.n 8009b9e } if(hdma->State != HAL_DMA_STATE_BUSY) 800972e: 687b ldr r3, [r7, #4] 8009730: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8009734: b2db uxtb r3, r3 8009736: 2b02 cmp r3, #2 8009738: d004 beq.n 8009744 { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800973a: 687b ldr r3, [r7, #4] 800973c: 2280 movs r2, #128 @ 0x80 800973e: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8009740: 2301 movs r3, #1 8009742: e22c b.n 8009b9e } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009744: 687b ldr r3, [r7, #4] 8009746: 681b ldr r3, [r3, #0] 8009748: 4a5c ldr r2, [pc, #368] @ (80098bc ) 800974a: 4293 cmp r3, r2 800974c: d04a beq.n 80097e4 800974e: 687b ldr r3, [r7, #4] 8009750: 681b ldr r3, [r3, #0] 8009752: 4a5b ldr r2, [pc, #364] @ (80098c0 ) 8009754: 4293 cmp r3, r2 8009756: d045 beq.n 80097e4 8009758: 687b ldr r3, [r7, #4] 800975a: 681b ldr r3, [r3, #0] 800975c: 4a59 ldr r2, [pc, #356] @ (80098c4 ) 800975e: 4293 cmp r3, r2 8009760: d040 beq.n 80097e4 8009762: 687b ldr r3, [r7, #4] 8009764: 681b ldr r3, [r3, #0] 8009766: 4a58 ldr r2, [pc, #352] @ (80098c8 ) 8009768: 4293 cmp r3, r2 800976a: d03b beq.n 80097e4 800976c: 687b ldr r3, [r7, #4] 800976e: 681b ldr r3, [r3, #0] 8009770: 4a56 ldr r2, [pc, #344] @ (80098cc ) 8009772: 4293 cmp r3, r2 8009774: d036 beq.n 80097e4 8009776: 687b ldr r3, [r7, #4] 8009778: 681b ldr r3, [r3, #0] 800977a: 4a55 ldr r2, [pc, #340] @ (80098d0 ) 800977c: 4293 cmp r3, r2 800977e: d031 beq.n 80097e4 8009780: 687b ldr r3, [r7, #4] 8009782: 681b ldr r3, [r3, #0] 8009784: 4a53 ldr r2, [pc, #332] @ (80098d4 ) 8009786: 4293 cmp r3, r2 8009788: d02c beq.n 80097e4 800978a: 687b ldr r3, [r7, #4] 800978c: 681b ldr r3, [r3, #0] 800978e: 4a52 ldr r2, [pc, #328] @ (80098d8 ) 8009790: 4293 cmp r3, r2 8009792: d027 beq.n 80097e4 8009794: 687b ldr r3, [r7, #4] 8009796: 681b ldr r3, [r3, #0] 8009798: 4a50 ldr r2, [pc, #320] @ (80098dc ) 800979a: 4293 cmp r3, r2 800979c: d022 beq.n 80097e4 800979e: 687b ldr r3, [r7, #4] 80097a0: 681b ldr r3, [r3, #0] 80097a2: 4a4f ldr r2, [pc, #316] @ (80098e0 ) 80097a4: 4293 cmp r3, r2 80097a6: d01d beq.n 80097e4 80097a8: 687b ldr r3, [r7, #4] 80097aa: 681b ldr r3, [r3, #0] 80097ac: 4a4d ldr r2, [pc, #308] @ (80098e4 ) 80097ae: 4293 cmp r3, r2 80097b0: d018 beq.n 80097e4 80097b2: 687b ldr r3, [r7, #4] 80097b4: 681b ldr r3, [r3, #0] 80097b6: 4a4c ldr r2, [pc, #304] @ (80098e8 ) 80097b8: 4293 cmp r3, r2 80097ba: d013 beq.n 80097e4 80097bc: 687b ldr r3, [r7, #4] 80097be: 681b ldr r3, [r3, #0] 80097c0: 4a4a ldr r2, [pc, #296] @ (80098ec ) 80097c2: 4293 cmp r3, r2 80097c4: d00e beq.n 80097e4 80097c6: 687b ldr r3, [r7, #4] 80097c8: 681b ldr r3, [r3, #0] 80097ca: 4a49 ldr r2, [pc, #292] @ (80098f0 ) 80097cc: 4293 cmp r3, r2 80097ce: d009 beq.n 80097e4 80097d0: 687b ldr r3, [r7, #4] 80097d2: 681b ldr r3, [r3, #0] 80097d4: 4a47 ldr r2, [pc, #284] @ (80098f4 ) 80097d6: 4293 cmp r3, r2 80097d8: d004 beq.n 80097e4 80097da: 687b ldr r3, [r7, #4] 80097dc: 681b ldr r3, [r3, #0] 80097de: 4a46 ldr r2, [pc, #280] @ (80098f8 ) 80097e0: 4293 cmp r3, r2 80097e2: d101 bne.n 80097e8 80097e4: 2301 movs r3, #1 80097e6: e000 b.n 80097ea 80097e8: 2300 movs r3, #0 80097ea: 2b00 cmp r3, #0 80097ec: f000 8086 beq.w 80098fc { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 80097f0: 687b ldr r3, [r7, #4] 80097f2: 2204 movs r2, #4 80097f4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 80097f8: 687b ldr r3, [r7, #4] 80097fa: 681b ldr r3, [r3, #0] 80097fc: 4a2f ldr r2, [pc, #188] @ (80098bc ) 80097fe: 4293 cmp r3, r2 8009800: d04a beq.n 8009898 8009802: 687b ldr r3, [r7, #4] 8009804: 681b ldr r3, [r3, #0] 8009806: 4a2e ldr r2, [pc, #184] @ (80098c0 ) 8009808: 4293 cmp r3, r2 800980a: d045 beq.n 8009898 800980c: 687b ldr r3, [r7, #4] 800980e: 681b ldr r3, [r3, #0] 8009810: 4a2c ldr r2, [pc, #176] @ (80098c4 ) 8009812: 4293 cmp r3, r2 8009814: d040 beq.n 8009898 8009816: 687b ldr r3, [r7, #4] 8009818: 681b ldr r3, [r3, #0] 800981a: 4a2b ldr r2, [pc, #172] @ (80098c8 ) 800981c: 4293 cmp r3, r2 800981e: d03b beq.n 8009898 8009820: 687b ldr r3, [r7, #4] 8009822: 681b ldr r3, [r3, #0] 8009824: 4a29 ldr r2, [pc, #164] @ (80098cc ) 8009826: 4293 cmp r3, r2 8009828: d036 beq.n 8009898 800982a: 687b ldr r3, [r7, #4] 800982c: 681b ldr r3, [r3, #0] 800982e: 4a28 ldr r2, [pc, #160] @ (80098d0 ) 8009830: 4293 cmp r3, r2 8009832: d031 beq.n 8009898 8009834: 687b ldr r3, [r7, #4] 8009836: 681b ldr r3, [r3, #0] 8009838: 4a26 ldr r2, [pc, #152] @ (80098d4 ) 800983a: 4293 cmp r3, r2 800983c: d02c beq.n 8009898 800983e: 687b ldr r3, [r7, #4] 8009840: 681b ldr r3, [r3, #0] 8009842: 4a25 ldr r2, [pc, #148] @ (80098d8 ) 8009844: 4293 cmp r3, r2 8009846: d027 beq.n 8009898 8009848: 687b ldr r3, [r7, #4] 800984a: 681b ldr r3, [r3, #0] 800984c: 4a23 ldr r2, [pc, #140] @ (80098dc ) 800984e: 4293 cmp r3, r2 8009850: d022 beq.n 8009898 8009852: 687b ldr r3, [r7, #4] 8009854: 681b ldr r3, [r3, #0] 8009856: 4a22 ldr r2, [pc, #136] @ (80098e0 ) 8009858: 4293 cmp r3, r2 800985a: d01d beq.n 8009898 800985c: 687b ldr r3, [r7, #4] 800985e: 681b ldr r3, [r3, #0] 8009860: 4a20 ldr r2, [pc, #128] @ (80098e4 ) 8009862: 4293 cmp r3, r2 8009864: d018 beq.n 8009898 8009866: 687b ldr r3, [r7, #4] 8009868: 681b ldr r3, [r3, #0] 800986a: 4a1f ldr r2, [pc, #124] @ (80098e8 ) 800986c: 4293 cmp r3, r2 800986e: d013 beq.n 8009898 8009870: 687b ldr r3, [r7, #4] 8009872: 681b ldr r3, [r3, #0] 8009874: 4a1d ldr r2, [pc, #116] @ (80098ec ) 8009876: 4293 cmp r3, r2 8009878: d00e beq.n 8009898 800987a: 687b ldr r3, [r7, #4] 800987c: 681b ldr r3, [r3, #0] 800987e: 4a1c ldr r2, [pc, #112] @ (80098f0 ) 8009880: 4293 cmp r3, r2 8009882: d009 beq.n 8009898 8009884: 687b ldr r3, [r7, #4] 8009886: 681b ldr r3, [r3, #0] 8009888: 4a1a ldr r2, [pc, #104] @ (80098f4 ) 800988a: 4293 cmp r3, r2 800988c: d004 beq.n 8009898 800988e: 687b ldr r3, [r7, #4] 8009890: 681b ldr r3, [r3, #0] 8009892: 4a19 ldr r2, [pc, #100] @ (80098f8 ) 8009894: 4293 cmp r3, r2 8009896: d108 bne.n 80098aa 8009898: 687b ldr r3, [r7, #4] 800989a: 681b ldr r3, [r3, #0] 800989c: 681a ldr r2, [r3, #0] 800989e: 687b ldr r3, [r7, #4] 80098a0: 681b ldr r3, [r3, #0] 80098a2: f022 0201 bic.w r2, r2, #1 80098a6: 601a str r2, [r3, #0] 80098a8: e178 b.n 8009b9c 80098aa: 687b ldr r3, [r7, #4] 80098ac: 681b ldr r3, [r3, #0] 80098ae: 681a ldr r2, [r3, #0] 80098b0: 687b ldr r3, [r7, #4] 80098b2: 681b ldr r3, [r3, #0] 80098b4: f022 0201 bic.w r2, r2, #1 80098b8: 601a str r2, [r3, #0] 80098ba: e16f b.n 8009b9c 80098bc: 40020010 .word 0x40020010 80098c0: 40020028 .word 0x40020028 80098c4: 40020040 .word 0x40020040 80098c8: 40020058 .word 0x40020058 80098cc: 40020070 .word 0x40020070 80098d0: 40020088 .word 0x40020088 80098d4: 400200a0 .word 0x400200a0 80098d8: 400200b8 .word 0x400200b8 80098dc: 40020410 .word 0x40020410 80098e0: 40020428 .word 0x40020428 80098e4: 40020440 .word 0x40020440 80098e8: 40020458 .word 0x40020458 80098ec: 40020470 .word 0x40020470 80098f0: 40020488 .word 0x40020488 80098f4: 400204a0 .word 0x400204a0 80098f8: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80098fc: 687b ldr r3, [r7, #4] 80098fe: 681b ldr r3, [r3, #0] 8009900: 681a ldr r2, [r3, #0] 8009902: 687b ldr r3, [r7, #4] 8009904: 681b ldr r3, [r3, #0] 8009906: f022 020e bic.w r2, r2, #14 800990a: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 800990c: 687b ldr r3, [r7, #4] 800990e: 681b ldr r3, [r3, #0] 8009910: 4a6c ldr r2, [pc, #432] @ (8009ac4 ) 8009912: 4293 cmp r3, r2 8009914: d04a beq.n 80099ac 8009916: 687b ldr r3, [r7, #4] 8009918: 681b ldr r3, [r3, #0] 800991a: 4a6b ldr r2, [pc, #428] @ (8009ac8 ) 800991c: 4293 cmp r3, r2 800991e: d045 beq.n 80099ac 8009920: 687b ldr r3, [r7, #4] 8009922: 681b ldr r3, [r3, #0] 8009924: 4a69 ldr r2, [pc, #420] @ (8009acc ) 8009926: 4293 cmp r3, r2 8009928: d040 beq.n 80099ac 800992a: 687b ldr r3, [r7, #4] 800992c: 681b ldr r3, [r3, #0] 800992e: 4a68 ldr r2, [pc, #416] @ (8009ad0 ) 8009930: 4293 cmp r3, r2 8009932: d03b beq.n 80099ac 8009934: 687b ldr r3, [r7, #4] 8009936: 681b ldr r3, [r3, #0] 8009938: 4a66 ldr r2, [pc, #408] @ (8009ad4 ) 800993a: 4293 cmp r3, r2 800993c: d036 beq.n 80099ac 800993e: 687b ldr r3, [r7, #4] 8009940: 681b ldr r3, [r3, #0] 8009942: 4a65 ldr r2, [pc, #404] @ (8009ad8 ) 8009944: 4293 cmp r3, r2 8009946: d031 beq.n 80099ac 8009948: 687b ldr r3, [r7, #4] 800994a: 681b ldr r3, [r3, #0] 800994c: 4a63 ldr r2, [pc, #396] @ (8009adc ) 800994e: 4293 cmp r3, r2 8009950: d02c beq.n 80099ac 8009952: 687b ldr r3, [r7, #4] 8009954: 681b ldr r3, [r3, #0] 8009956: 4a62 ldr r2, [pc, #392] @ (8009ae0 ) 8009958: 4293 cmp r3, r2 800995a: d027 beq.n 80099ac 800995c: 687b ldr r3, [r7, #4] 800995e: 681b ldr r3, [r3, #0] 8009960: 4a60 ldr r2, [pc, #384] @ (8009ae4 ) 8009962: 4293 cmp r3, r2 8009964: d022 beq.n 80099ac 8009966: 687b ldr r3, [r7, #4] 8009968: 681b ldr r3, [r3, #0] 800996a: 4a5f ldr r2, [pc, #380] @ (8009ae8 ) 800996c: 4293 cmp r3, r2 800996e: d01d beq.n 80099ac 8009970: 687b ldr r3, [r7, #4] 8009972: 681b ldr r3, [r3, #0] 8009974: 4a5d ldr r2, [pc, #372] @ (8009aec ) 8009976: 4293 cmp r3, r2 8009978: d018 beq.n 80099ac 800997a: 687b ldr r3, [r7, #4] 800997c: 681b ldr r3, [r3, #0] 800997e: 4a5c ldr r2, [pc, #368] @ (8009af0 ) 8009980: 4293 cmp r3, r2 8009982: d013 beq.n 80099ac 8009984: 687b ldr r3, [r7, #4] 8009986: 681b ldr r3, [r3, #0] 8009988: 4a5a ldr r2, [pc, #360] @ (8009af4 ) 800998a: 4293 cmp r3, r2 800998c: d00e beq.n 80099ac 800998e: 687b ldr r3, [r7, #4] 8009990: 681b ldr r3, [r3, #0] 8009992: 4a59 ldr r2, [pc, #356] @ (8009af8 ) 8009994: 4293 cmp r3, r2 8009996: d009 beq.n 80099ac 8009998: 687b ldr r3, [r7, #4] 800999a: 681b ldr r3, [r3, #0] 800999c: 4a57 ldr r2, [pc, #348] @ (8009afc ) 800999e: 4293 cmp r3, r2 80099a0: d004 beq.n 80099ac 80099a2: 687b ldr r3, [r7, #4] 80099a4: 681b ldr r3, [r3, #0] 80099a6: 4a56 ldr r2, [pc, #344] @ (8009b00 ) 80099a8: 4293 cmp r3, r2 80099aa: d108 bne.n 80099be 80099ac: 687b ldr r3, [r7, #4] 80099ae: 681b ldr r3, [r3, #0] 80099b0: 681a ldr r2, [r3, #0] 80099b2: 687b ldr r3, [r7, #4] 80099b4: 681b ldr r3, [r3, #0] 80099b6: f022 0201 bic.w r2, r2, #1 80099ba: 601a str r2, [r3, #0] 80099bc: e007 b.n 80099ce 80099be: 687b ldr r3, [r7, #4] 80099c0: 681b ldr r3, [r3, #0] 80099c2: 681a ldr r2, [r3, #0] 80099c4: 687b ldr r3, [r7, #4] 80099c6: 681b ldr r3, [r3, #0] 80099c8: f022 0201 bic.w r2, r2, #1 80099cc: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80099ce: 687b ldr r3, [r7, #4] 80099d0: 681b ldr r3, [r3, #0] 80099d2: 4a3c ldr r2, [pc, #240] @ (8009ac4 ) 80099d4: 4293 cmp r3, r2 80099d6: d072 beq.n 8009abe 80099d8: 687b ldr r3, [r7, #4] 80099da: 681b ldr r3, [r3, #0] 80099dc: 4a3a ldr r2, [pc, #232] @ (8009ac8 ) 80099de: 4293 cmp r3, r2 80099e0: d06d beq.n 8009abe 80099e2: 687b ldr r3, [r7, #4] 80099e4: 681b ldr r3, [r3, #0] 80099e6: 4a39 ldr r2, [pc, #228] @ (8009acc ) 80099e8: 4293 cmp r3, r2 80099ea: d068 beq.n 8009abe 80099ec: 687b ldr r3, [r7, #4] 80099ee: 681b ldr r3, [r3, #0] 80099f0: 4a37 ldr r2, [pc, #220] @ (8009ad0 ) 80099f2: 4293 cmp r3, r2 80099f4: d063 beq.n 8009abe 80099f6: 687b ldr r3, [r7, #4] 80099f8: 681b ldr r3, [r3, #0] 80099fa: 4a36 ldr r2, [pc, #216] @ (8009ad4 ) 80099fc: 4293 cmp r3, r2 80099fe: d05e beq.n 8009abe 8009a00: 687b ldr r3, [r7, #4] 8009a02: 681b ldr r3, [r3, #0] 8009a04: 4a34 ldr r2, [pc, #208] @ (8009ad8 ) 8009a06: 4293 cmp r3, r2 8009a08: d059 beq.n 8009abe 8009a0a: 687b ldr r3, [r7, #4] 8009a0c: 681b ldr r3, [r3, #0] 8009a0e: 4a33 ldr r2, [pc, #204] @ (8009adc ) 8009a10: 4293 cmp r3, r2 8009a12: d054 beq.n 8009abe 8009a14: 687b ldr r3, [r7, #4] 8009a16: 681b ldr r3, [r3, #0] 8009a18: 4a31 ldr r2, [pc, #196] @ (8009ae0 ) 8009a1a: 4293 cmp r3, r2 8009a1c: d04f beq.n 8009abe 8009a1e: 687b ldr r3, [r7, #4] 8009a20: 681b ldr r3, [r3, #0] 8009a22: 4a30 ldr r2, [pc, #192] @ (8009ae4 ) 8009a24: 4293 cmp r3, r2 8009a26: d04a beq.n 8009abe 8009a28: 687b ldr r3, [r7, #4] 8009a2a: 681b ldr r3, [r3, #0] 8009a2c: 4a2e ldr r2, [pc, #184] @ (8009ae8 ) 8009a2e: 4293 cmp r3, r2 8009a30: d045 beq.n 8009abe 8009a32: 687b ldr r3, [r7, #4] 8009a34: 681b ldr r3, [r3, #0] 8009a36: 4a2d ldr r2, [pc, #180] @ (8009aec ) 8009a38: 4293 cmp r3, r2 8009a3a: d040 beq.n 8009abe 8009a3c: 687b ldr r3, [r7, #4] 8009a3e: 681b ldr r3, [r3, #0] 8009a40: 4a2b ldr r2, [pc, #172] @ (8009af0 ) 8009a42: 4293 cmp r3, r2 8009a44: d03b beq.n 8009abe 8009a46: 687b ldr r3, [r7, #4] 8009a48: 681b ldr r3, [r3, #0] 8009a4a: 4a2a ldr r2, [pc, #168] @ (8009af4 ) 8009a4c: 4293 cmp r3, r2 8009a4e: d036 beq.n 8009abe 8009a50: 687b ldr r3, [r7, #4] 8009a52: 681b ldr r3, [r3, #0] 8009a54: 4a28 ldr r2, [pc, #160] @ (8009af8 ) 8009a56: 4293 cmp r3, r2 8009a58: d031 beq.n 8009abe 8009a5a: 687b ldr r3, [r7, #4] 8009a5c: 681b ldr r3, [r3, #0] 8009a5e: 4a27 ldr r2, [pc, #156] @ (8009afc ) 8009a60: 4293 cmp r3, r2 8009a62: d02c beq.n 8009abe 8009a64: 687b ldr r3, [r7, #4] 8009a66: 681b ldr r3, [r3, #0] 8009a68: 4a25 ldr r2, [pc, #148] @ (8009b00 ) 8009a6a: 4293 cmp r3, r2 8009a6c: d027 beq.n 8009abe 8009a6e: 687b ldr r3, [r7, #4] 8009a70: 681b ldr r3, [r3, #0] 8009a72: 4a24 ldr r2, [pc, #144] @ (8009b04 ) 8009a74: 4293 cmp r3, r2 8009a76: d022 beq.n 8009abe 8009a78: 687b ldr r3, [r7, #4] 8009a7a: 681b ldr r3, [r3, #0] 8009a7c: 4a22 ldr r2, [pc, #136] @ (8009b08 ) 8009a7e: 4293 cmp r3, r2 8009a80: d01d beq.n 8009abe 8009a82: 687b ldr r3, [r7, #4] 8009a84: 681b ldr r3, [r3, #0] 8009a86: 4a21 ldr r2, [pc, #132] @ (8009b0c ) 8009a88: 4293 cmp r3, r2 8009a8a: d018 beq.n 8009abe 8009a8c: 687b ldr r3, [r7, #4] 8009a8e: 681b ldr r3, [r3, #0] 8009a90: 4a1f ldr r2, [pc, #124] @ (8009b10 ) 8009a92: 4293 cmp r3, r2 8009a94: d013 beq.n 8009abe 8009a96: 687b ldr r3, [r7, #4] 8009a98: 681b ldr r3, [r3, #0] 8009a9a: 4a1e ldr r2, [pc, #120] @ (8009b14 ) 8009a9c: 4293 cmp r3, r2 8009a9e: d00e beq.n 8009abe 8009aa0: 687b ldr r3, [r7, #4] 8009aa2: 681b ldr r3, [r3, #0] 8009aa4: 4a1c ldr r2, [pc, #112] @ (8009b18 ) 8009aa6: 4293 cmp r3, r2 8009aa8: d009 beq.n 8009abe 8009aaa: 687b ldr r3, [r7, #4] 8009aac: 681b ldr r3, [r3, #0] 8009aae: 4a1b ldr r2, [pc, #108] @ (8009b1c ) 8009ab0: 4293 cmp r3, r2 8009ab2: d004 beq.n 8009abe 8009ab4: 687b ldr r3, [r7, #4] 8009ab6: 681b ldr r3, [r3, #0] 8009ab8: 4a19 ldr r2, [pc, #100] @ (8009b20 ) 8009aba: 4293 cmp r3, r2 8009abc: d132 bne.n 8009b24 8009abe: 2301 movs r3, #1 8009ac0: e031 b.n 8009b26 8009ac2: bf00 nop 8009ac4: 40020010 .word 0x40020010 8009ac8: 40020028 .word 0x40020028 8009acc: 40020040 .word 0x40020040 8009ad0: 40020058 .word 0x40020058 8009ad4: 40020070 .word 0x40020070 8009ad8: 40020088 .word 0x40020088 8009adc: 400200a0 .word 0x400200a0 8009ae0: 400200b8 .word 0x400200b8 8009ae4: 40020410 .word 0x40020410 8009ae8: 40020428 .word 0x40020428 8009aec: 40020440 .word 0x40020440 8009af0: 40020458 .word 0x40020458 8009af4: 40020470 .word 0x40020470 8009af8: 40020488 .word 0x40020488 8009afc: 400204a0 .word 0x400204a0 8009b00: 400204b8 .word 0x400204b8 8009b04: 58025408 .word 0x58025408 8009b08: 5802541c .word 0x5802541c 8009b0c: 58025430 .word 0x58025430 8009b10: 58025444 .word 0x58025444 8009b14: 58025458 .word 0x58025458 8009b18: 5802546c .word 0x5802546c 8009b1c: 58025480 .word 0x58025480 8009b20: 58025494 .word 0x58025494 8009b24: 2300 movs r3, #0 8009b26: 2b00 cmp r3, #0 8009b28: d028 beq.n 8009b7c { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8009b2a: 687b ldr r3, [r7, #4] 8009b2c: 6e1b ldr r3, [r3, #96] @ 0x60 8009b2e: 681a ldr r2, [r3, #0] 8009b30: 687b ldr r3, [r7, #4] 8009b32: 6e1b ldr r3, [r3, #96] @ 0x60 8009b34: f422 7280 bic.w r2, r2, #256 @ 0x100 8009b38: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009b3a: 687b ldr r3, [r7, #4] 8009b3c: 6d9b ldr r3, [r3, #88] @ 0x58 8009b3e: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8009b40: 687b ldr r3, [r7, #4] 8009b42: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b44: f003 031f and.w r3, r3, #31 8009b48: 2201 movs r2, #1 8009b4a: 409a lsls r2, r3 8009b4c: 68fb ldr r3, [r7, #12] 8009b4e: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009b50: 687b ldr r3, [r7, #4] 8009b52: 6e5b ldr r3, [r3, #100] @ 0x64 8009b54: 687a ldr r2, [r7, #4] 8009b56: 6e92 ldr r2, [r2, #104] @ 0x68 8009b58: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8009b5a: 687b ldr r3, [r7, #4] 8009b5c: 6edb ldr r3, [r3, #108] @ 0x6c 8009b5e: 2b00 cmp r3, #0 8009b60: d00c beq.n 8009b7c { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8009b62: 687b ldr r3, [r7, #4] 8009b64: 6edb ldr r3, [r3, #108] @ 0x6c 8009b66: 681a ldr r2, [r3, #0] 8009b68: 687b ldr r3, [r7, #4] 8009b6a: 6edb ldr r3, [r3, #108] @ 0x6c 8009b6c: f422 7280 bic.w r2, r2, #256 @ 0x100 8009b70: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009b72: 687b ldr r3, [r7, #4] 8009b74: 6f1b ldr r3, [r3, #112] @ 0x70 8009b76: 687a ldr r2, [r7, #4] 8009b78: 6f52 ldr r2, [r2, #116] @ 0x74 8009b7a: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009b7c: 687b ldr r3, [r7, #4] 8009b7e: 2201 movs r2, #1 8009b80: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009b84: 687b ldr r3, [r7, #4] 8009b86: 2200 movs r2, #0 8009b88: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8009b8c: 687b ldr r3, [r7, #4] 8009b8e: 6d1b ldr r3, [r3, #80] @ 0x50 8009b90: 2b00 cmp r3, #0 8009b92: d003 beq.n 8009b9c { hdma->XferAbortCallback(hdma); 8009b94: 687b ldr r3, [r7, #4] 8009b96: 6d1b ldr r3, [r3, #80] @ 0x50 8009b98: 6878 ldr r0, [r7, #4] 8009b9a: 4798 blx r3 } } } return HAL_OK; 8009b9c: 2300 movs r3, #0 } 8009b9e: 4618 mov r0, r3 8009ba0: 3710 adds r7, #16 8009ba2: 46bd mov sp, r7 8009ba4: bd80 pop {r7, pc} 8009ba6: bf00 nop 08009ba8 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8009ba8: b580 push {r7, lr} 8009baa: b08a sub sp, #40 @ 0x28 8009bac: af00 add r7, sp, #0 8009bae: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8009bb0: 2300 movs r3, #0 8009bb2: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8009bb4: 4b67 ldr r3, [pc, #412] @ (8009d54 ) 8009bb6: 681b ldr r3, [r3, #0] 8009bb8: 4a67 ldr r2, [pc, #412] @ (8009d58 ) 8009bba: fba2 2303 umull r2, r3, r2, r3 8009bbe: 0a9b lsrs r3, r3, #10 8009bc0: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009bc2: 687b ldr r3, [r7, #4] 8009bc4: 6d9b ldr r3, [r3, #88] @ 0x58 8009bc6: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009bc8: 687b ldr r3, [r7, #4] 8009bca: 6d9b ldr r3, [r3, #88] @ 0x58 8009bcc: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8009bce: 6a3b ldr r3, [r7, #32] 8009bd0: 681b ldr r3, [r3, #0] 8009bd2: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8009bd4: 69fb ldr r3, [r7, #28] 8009bd6: 681b ldr r3, [r3, #0] 8009bd8: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009bda: 687b ldr r3, [r7, #4] 8009bdc: 681b ldr r3, [r3, #0] 8009bde: 4a5f ldr r2, [pc, #380] @ (8009d5c ) 8009be0: 4293 cmp r3, r2 8009be2: d04a beq.n 8009c7a 8009be4: 687b ldr r3, [r7, #4] 8009be6: 681b ldr r3, [r3, #0] 8009be8: 4a5d ldr r2, [pc, #372] @ (8009d60 ) 8009bea: 4293 cmp r3, r2 8009bec: d045 beq.n 8009c7a 8009bee: 687b ldr r3, [r7, #4] 8009bf0: 681b ldr r3, [r3, #0] 8009bf2: 4a5c ldr r2, [pc, #368] @ (8009d64 ) 8009bf4: 4293 cmp r3, r2 8009bf6: d040 beq.n 8009c7a 8009bf8: 687b ldr r3, [r7, #4] 8009bfa: 681b ldr r3, [r3, #0] 8009bfc: 4a5a ldr r2, [pc, #360] @ (8009d68 ) 8009bfe: 4293 cmp r3, r2 8009c00: d03b beq.n 8009c7a 8009c02: 687b ldr r3, [r7, #4] 8009c04: 681b ldr r3, [r3, #0] 8009c06: 4a59 ldr r2, [pc, #356] @ (8009d6c ) 8009c08: 4293 cmp r3, r2 8009c0a: d036 beq.n 8009c7a 8009c0c: 687b ldr r3, [r7, #4] 8009c0e: 681b ldr r3, [r3, #0] 8009c10: 4a57 ldr r2, [pc, #348] @ (8009d70 ) 8009c12: 4293 cmp r3, r2 8009c14: d031 beq.n 8009c7a 8009c16: 687b ldr r3, [r7, #4] 8009c18: 681b ldr r3, [r3, #0] 8009c1a: 4a56 ldr r2, [pc, #344] @ (8009d74 ) 8009c1c: 4293 cmp r3, r2 8009c1e: d02c beq.n 8009c7a 8009c20: 687b ldr r3, [r7, #4] 8009c22: 681b ldr r3, [r3, #0] 8009c24: 4a54 ldr r2, [pc, #336] @ (8009d78 ) 8009c26: 4293 cmp r3, r2 8009c28: d027 beq.n 8009c7a 8009c2a: 687b ldr r3, [r7, #4] 8009c2c: 681b ldr r3, [r3, #0] 8009c2e: 4a53 ldr r2, [pc, #332] @ (8009d7c ) 8009c30: 4293 cmp r3, r2 8009c32: d022 beq.n 8009c7a 8009c34: 687b ldr r3, [r7, #4] 8009c36: 681b ldr r3, [r3, #0] 8009c38: 4a51 ldr r2, [pc, #324] @ (8009d80 ) 8009c3a: 4293 cmp r3, r2 8009c3c: d01d beq.n 8009c7a 8009c3e: 687b ldr r3, [r7, #4] 8009c40: 681b ldr r3, [r3, #0] 8009c42: 4a50 ldr r2, [pc, #320] @ (8009d84 ) 8009c44: 4293 cmp r3, r2 8009c46: d018 beq.n 8009c7a 8009c48: 687b ldr r3, [r7, #4] 8009c4a: 681b ldr r3, [r3, #0] 8009c4c: 4a4e ldr r2, [pc, #312] @ (8009d88 ) 8009c4e: 4293 cmp r3, r2 8009c50: d013 beq.n 8009c7a 8009c52: 687b ldr r3, [r7, #4] 8009c54: 681b ldr r3, [r3, #0] 8009c56: 4a4d ldr r2, [pc, #308] @ (8009d8c ) 8009c58: 4293 cmp r3, r2 8009c5a: d00e beq.n 8009c7a 8009c5c: 687b ldr r3, [r7, #4] 8009c5e: 681b ldr r3, [r3, #0] 8009c60: 4a4b ldr r2, [pc, #300] @ (8009d90 ) 8009c62: 4293 cmp r3, r2 8009c64: d009 beq.n 8009c7a 8009c66: 687b ldr r3, [r7, #4] 8009c68: 681b ldr r3, [r3, #0] 8009c6a: 4a4a ldr r2, [pc, #296] @ (8009d94 ) 8009c6c: 4293 cmp r3, r2 8009c6e: d004 beq.n 8009c7a 8009c70: 687b ldr r3, [r7, #4] 8009c72: 681b ldr r3, [r3, #0] 8009c74: 4a48 ldr r2, [pc, #288] @ (8009d98 ) 8009c76: 4293 cmp r3, r2 8009c78: d101 bne.n 8009c7e 8009c7a: 2301 movs r3, #1 8009c7c: e000 b.n 8009c80 8009c7e: 2300 movs r3, #0 8009c80: 2b00 cmp r3, #0 8009c82: f000 842b beq.w 800a4dc { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009c86: 687b ldr r3, [r7, #4] 8009c88: 6ddb ldr r3, [r3, #92] @ 0x5c 8009c8a: f003 031f and.w r3, r3, #31 8009c8e: 2208 movs r2, #8 8009c90: 409a lsls r2, r3 8009c92: 69bb ldr r3, [r7, #24] 8009c94: 4013 ands r3, r2 8009c96: 2b00 cmp r3, #0 8009c98: f000 80a2 beq.w 8009de0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8009c9c: 687b ldr r3, [r7, #4] 8009c9e: 681b ldr r3, [r3, #0] 8009ca0: 4a2e ldr r2, [pc, #184] @ (8009d5c ) 8009ca2: 4293 cmp r3, r2 8009ca4: d04a beq.n 8009d3c 8009ca6: 687b ldr r3, [r7, #4] 8009ca8: 681b ldr r3, [r3, #0] 8009caa: 4a2d ldr r2, [pc, #180] @ (8009d60 ) 8009cac: 4293 cmp r3, r2 8009cae: d045 beq.n 8009d3c 8009cb0: 687b ldr r3, [r7, #4] 8009cb2: 681b ldr r3, [r3, #0] 8009cb4: 4a2b ldr r2, [pc, #172] @ (8009d64 ) 8009cb6: 4293 cmp r3, r2 8009cb8: d040 beq.n 8009d3c 8009cba: 687b ldr r3, [r7, #4] 8009cbc: 681b ldr r3, [r3, #0] 8009cbe: 4a2a ldr r2, [pc, #168] @ (8009d68 ) 8009cc0: 4293 cmp r3, r2 8009cc2: d03b beq.n 8009d3c 8009cc4: 687b ldr r3, [r7, #4] 8009cc6: 681b ldr r3, [r3, #0] 8009cc8: 4a28 ldr r2, [pc, #160] @ (8009d6c ) 8009cca: 4293 cmp r3, r2 8009ccc: d036 beq.n 8009d3c 8009cce: 687b ldr r3, [r7, #4] 8009cd0: 681b ldr r3, [r3, #0] 8009cd2: 4a27 ldr r2, [pc, #156] @ (8009d70 ) 8009cd4: 4293 cmp r3, r2 8009cd6: d031 beq.n 8009d3c 8009cd8: 687b ldr r3, [r7, #4] 8009cda: 681b ldr r3, [r3, #0] 8009cdc: 4a25 ldr r2, [pc, #148] @ (8009d74 ) 8009cde: 4293 cmp r3, r2 8009ce0: d02c beq.n 8009d3c 8009ce2: 687b ldr r3, [r7, #4] 8009ce4: 681b ldr r3, [r3, #0] 8009ce6: 4a24 ldr r2, [pc, #144] @ (8009d78 ) 8009ce8: 4293 cmp r3, r2 8009cea: d027 beq.n 8009d3c 8009cec: 687b ldr r3, [r7, #4] 8009cee: 681b ldr r3, [r3, #0] 8009cf0: 4a22 ldr r2, [pc, #136] @ (8009d7c ) 8009cf2: 4293 cmp r3, r2 8009cf4: d022 beq.n 8009d3c 8009cf6: 687b ldr r3, [r7, #4] 8009cf8: 681b ldr r3, [r3, #0] 8009cfa: 4a21 ldr r2, [pc, #132] @ (8009d80 ) 8009cfc: 4293 cmp r3, r2 8009cfe: d01d beq.n 8009d3c 8009d00: 687b ldr r3, [r7, #4] 8009d02: 681b ldr r3, [r3, #0] 8009d04: 4a1f ldr r2, [pc, #124] @ (8009d84 ) 8009d06: 4293 cmp r3, r2 8009d08: d018 beq.n 8009d3c 8009d0a: 687b ldr r3, [r7, #4] 8009d0c: 681b ldr r3, [r3, #0] 8009d0e: 4a1e ldr r2, [pc, #120] @ (8009d88 ) 8009d10: 4293 cmp r3, r2 8009d12: d013 beq.n 8009d3c 8009d14: 687b ldr r3, [r7, #4] 8009d16: 681b ldr r3, [r3, #0] 8009d18: 4a1c ldr r2, [pc, #112] @ (8009d8c ) 8009d1a: 4293 cmp r3, r2 8009d1c: d00e beq.n 8009d3c 8009d1e: 687b ldr r3, [r7, #4] 8009d20: 681b ldr r3, [r3, #0] 8009d22: 4a1b ldr r2, [pc, #108] @ (8009d90 ) 8009d24: 4293 cmp r3, r2 8009d26: d009 beq.n 8009d3c 8009d28: 687b ldr r3, [r7, #4] 8009d2a: 681b ldr r3, [r3, #0] 8009d2c: 4a19 ldr r2, [pc, #100] @ (8009d94 ) 8009d2e: 4293 cmp r3, r2 8009d30: d004 beq.n 8009d3c 8009d32: 687b ldr r3, [r7, #4] 8009d34: 681b ldr r3, [r3, #0] 8009d36: 4a18 ldr r2, [pc, #96] @ (8009d98 ) 8009d38: 4293 cmp r3, r2 8009d3a: d12f bne.n 8009d9c 8009d3c: 687b ldr r3, [r7, #4] 8009d3e: 681b ldr r3, [r3, #0] 8009d40: 681b ldr r3, [r3, #0] 8009d42: f003 0304 and.w r3, r3, #4 8009d46: 2b00 cmp r3, #0 8009d48: bf14 ite ne 8009d4a: 2301 movne r3, #1 8009d4c: 2300 moveq r3, #0 8009d4e: b2db uxtb r3, r3 8009d50: e02e b.n 8009db0 8009d52: bf00 nop 8009d54: 24000034 .word 0x24000034 8009d58: 1b4e81b5 .word 0x1b4e81b5 8009d5c: 40020010 .word 0x40020010 8009d60: 40020028 .word 0x40020028 8009d64: 40020040 .word 0x40020040 8009d68: 40020058 .word 0x40020058 8009d6c: 40020070 .word 0x40020070 8009d70: 40020088 .word 0x40020088 8009d74: 400200a0 .word 0x400200a0 8009d78: 400200b8 .word 0x400200b8 8009d7c: 40020410 .word 0x40020410 8009d80: 40020428 .word 0x40020428 8009d84: 40020440 .word 0x40020440 8009d88: 40020458 .word 0x40020458 8009d8c: 40020470 .word 0x40020470 8009d90: 40020488 .word 0x40020488 8009d94: 400204a0 .word 0x400204a0 8009d98: 400204b8 .word 0x400204b8 8009d9c: 687b ldr r3, [r7, #4] 8009d9e: 681b ldr r3, [r3, #0] 8009da0: 681b ldr r3, [r3, #0] 8009da2: f003 0308 and.w r3, r3, #8 8009da6: 2b00 cmp r3, #0 8009da8: bf14 ite ne 8009daa: 2301 movne r3, #1 8009dac: 2300 moveq r3, #0 8009dae: b2db uxtb r3, r3 8009db0: 2b00 cmp r3, #0 8009db2: d015 beq.n 8009de0 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8009db4: 687b ldr r3, [r7, #4] 8009db6: 681b ldr r3, [r3, #0] 8009db8: 681a ldr r2, [r3, #0] 8009dba: 687b ldr r3, [r7, #4] 8009dbc: 681b ldr r3, [r3, #0] 8009dbe: f022 0204 bic.w r2, r2, #4 8009dc2: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009dc4: 687b ldr r3, [r7, #4] 8009dc6: 6ddb ldr r3, [r3, #92] @ 0x5c 8009dc8: f003 031f and.w r3, r3, #31 8009dcc: 2208 movs r2, #8 8009dce: 409a lsls r2, r3 8009dd0: 6a3b ldr r3, [r7, #32] 8009dd2: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8009dd4: 687b ldr r3, [r7, #4] 8009dd6: 6d5b ldr r3, [r3, #84] @ 0x54 8009dd8: f043 0201 orr.w r2, r3, #1 8009ddc: 687b ldr r3, [r7, #4] 8009dde: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009de0: 687b ldr r3, [r7, #4] 8009de2: 6ddb ldr r3, [r3, #92] @ 0x5c 8009de4: f003 031f and.w r3, r3, #31 8009de8: 69ba ldr r2, [r7, #24] 8009dea: fa22 f303 lsr.w r3, r2, r3 8009dee: f003 0301 and.w r3, r3, #1 8009df2: 2b00 cmp r3, #0 8009df4: d06e beq.n 8009ed4 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8009df6: 687b ldr r3, [r7, #4] 8009df8: 681b ldr r3, [r3, #0] 8009dfa: 4a69 ldr r2, [pc, #420] @ (8009fa0 ) 8009dfc: 4293 cmp r3, r2 8009dfe: d04a beq.n 8009e96 8009e00: 687b ldr r3, [r7, #4] 8009e02: 681b ldr r3, [r3, #0] 8009e04: 4a67 ldr r2, [pc, #412] @ (8009fa4 ) 8009e06: 4293 cmp r3, r2 8009e08: d045 beq.n 8009e96 8009e0a: 687b ldr r3, [r7, #4] 8009e0c: 681b ldr r3, [r3, #0] 8009e0e: 4a66 ldr r2, [pc, #408] @ (8009fa8 ) 8009e10: 4293 cmp r3, r2 8009e12: d040 beq.n 8009e96 8009e14: 687b ldr r3, [r7, #4] 8009e16: 681b ldr r3, [r3, #0] 8009e18: 4a64 ldr r2, [pc, #400] @ (8009fac ) 8009e1a: 4293 cmp r3, r2 8009e1c: d03b beq.n 8009e96 8009e1e: 687b ldr r3, [r7, #4] 8009e20: 681b ldr r3, [r3, #0] 8009e22: 4a63 ldr r2, [pc, #396] @ (8009fb0 ) 8009e24: 4293 cmp r3, r2 8009e26: d036 beq.n 8009e96 8009e28: 687b ldr r3, [r7, #4] 8009e2a: 681b ldr r3, [r3, #0] 8009e2c: 4a61 ldr r2, [pc, #388] @ (8009fb4 ) 8009e2e: 4293 cmp r3, r2 8009e30: d031 beq.n 8009e96 8009e32: 687b ldr r3, [r7, #4] 8009e34: 681b ldr r3, [r3, #0] 8009e36: 4a60 ldr r2, [pc, #384] @ (8009fb8 ) 8009e38: 4293 cmp r3, r2 8009e3a: d02c beq.n 8009e96 8009e3c: 687b ldr r3, [r7, #4] 8009e3e: 681b ldr r3, [r3, #0] 8009e40: 4a5e ldr r2, [pc, #376] @ (8009fbc ) 8009e42: 4293 cmp r3, r2 8009e44: d027 beq.n 8009e96 8009e46: 687b ldr r3, [r7, #4] 8009e48: 681b ldr r3, [r3, #0] 8009e4a: 4a5d ldr r2, [pc, #372] @ (8009fc0 ) 8009e4c: 4293 cmp r3, r2 8009e4e: d022 beq.n 8009e96 8009e50: 687b ldr r3, [r7, #4] 8009e52: 681b ldr r3, [r3, #0] 8009e54: 4a5b ldr r2, [pc, #364] @ (8009fc4 ) 8009e56: 4293 cmp r3, r2 8009e58: d01d beq.n 8009e96 8009e5a: 687b ldr r3, [r7, #4] 8009e5c: 681b ldr r3, [r3, #0] 8009e5e: 4a5a ldr r2, [pc, #360] @ (8009fc8 ) 8009e60: 4293 cmp r3, r2 8009e62: d018 beq.n 8009e96 8009e64: 687b ldr r3, [r7, #4] 8009e66: 681b ldr r3, [r3, #0] 8009e68: 4a58 ldr r2, [pc, #352] @ (8009fcc ) 8009e6a: 4293 cmp r3, r2 8009e6c: d013 beq.n 8009e96 8009e6e: 687b ldr r3, [r7, #4] 8009e70: 681b ldr r3, [r3, #0] 8009e72: 4a57 ldr r2, [pc, #348] @ (8009fd0 ) 8009e74: 4293 cmp r3, r2 8009e76: d00e beq.n 8009e96 8009e78: 687b ldr r3, [r7, #4] 8009e7a: 681b ldr r3, [r3, #0] 8009e7c: 4a55 ldr r2, [pc, #340] @ (8009fd4 ) 8009e7e: 4293 cmp r3, r2 8009e80: d009 beq.n 8009e96 8009e82: 687b ldr r3, [r7, #4] 8009e84: 681b ldr r3, [r3, #0] 8009e86: 4a54 ldr r2, [pc, #336] @ (8009fd8 ) 8009e88: 4293 cmp r3, r2 8009e8a: d004 beq.n 8009e96 8009e8c: 687b ldr r3, [r7, #4] 8009e8e: 681b ldr r3, [r3, #0] 8009e90: 4a52 ldr r2, [pc, #328] @ (8009fdc ) 8009e92: 4293 cmp r3, r2 8009e94: d10a bne.n 8009eac 8009e96: 687b ldr r3, [r7, #4] 8009e98: 681b ldr r3, [r3, #0] 8009e9a: 695b ldr r3, [r3, #20] 8009e9c: f003 0380 and.w r3, r3, #128 @ 0x80 8009ea0: 2b00 cmp r3, #0 8009ea2: bf14 ite ne 8009ea4: 2301 movne r3, #1 8009ea6: 2300 moveq r3, #0 8009ea8: b2db uxtb r3, r3 8009eaa: e003 b.n 8009eb4 8009eac: 687b ldr r3, [r7, #4] 8009eae: 681b ldr r3, [r3, #0] 8009eb0: 681b ldr r3, [r3, #0] 8009eb2: 2300 movs r3, #0 8009eb4: 2b00 cmp r3, #0 8009eb6: d00d beq.n 8009ed4 { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009eb8: 687b ldr r3, [r7, #4] 8009eba: 6ddb ldr r3, [r3, #92] @ 0x5c 8009ebc: f003 031f and.w r3, r3, #31 8009ec0: 2201 movs r2, #1 8009ec2: 409a lsls r2, r3 8009ec4: 6a3b ldr r3, [r7, #32] 8009ec6: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8009ec8: 687b ldr r3, [r7, #4] 8009eca: 6d5b ldr r3, [r3, #84] @ 0x54 8009ecc: f043 0202 orr.w r2, r3, #2 8009ed0: 687b ldr r3, [r7, #4] 8009ed2: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009ed4: 687b ldr r3, [r7, #4] 8009ed6: 6ddb ldr r3, [r3, #92] @ 0x5c 8009ed8: f003 031f and.w r3, r3, #31 8009edc: 2204 movs r2, #4 8009ede: 409a lsls r2, r3 8009ee0: 69bb ldr r3, [r7, #24] 8009ee2: 4013 ands r3, r2 8009ee4: 2b00 cmp r3, #0 8009ee6: f000 808f beq.w 800a008 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8009eea: 687b ldr r3, [r7, #4] 8009eec: 681b ldr r3, [r3, #0] 8009eee: 4a2c ldr r2, [pc, #176] @ (8009fa0 ) 8009ef0: 4293 cmp r3, r2 8009ef2: d04a beq.n 8009f8a 8009ef4: 687b ldr r3, [r7, #4] 8009ef6: 681b ldr r3, [r3, #0] 8009ef8: 4a2a ldr r2, [pc, #168] @ (8009fa4 ) 8009efa: 4293 cmp r3, r2 8009efc: d045 beq.n 8009f8a 8009efe: 687b ldr r3, [r7, #4] 8009f00: 681b ldr r3, [r3, #0] 8009f02: 4a29 ldr r2, [pc, #164] @ (8009fa8 ) 8009f04: 4293 cmp r3, r2 8009f06: d040 beq.n 8009f8a 8009f08: 687b ldr r3, [r7, #4] 8009f0a: 681b ldr r3, [r3, #0] 8009f0c: 4a27 ldr r2, [pc, #156] @ (8009fac ) 8009f0e: 4293 cmp r3, r2 8009f10: d03b beq.n 8009f8a 8009f12: 687b ldr r3, [r7, #4] 8009f14: 681b ldr r3, [r3, #0] 8009f16: 4a26 ldr r2, [pc, #152] @ (8009fb0 ) 8009f18: 4293 cmp r3, r2 8009f1a: d036 beq.n 8009f8a 8009f1c: 687b ldr r3, [r7, #4] 8009f1e: 681b ldr r3, [r3, #0] 8009f20: 4a24 ldr r2, [pc, #144] @ (8009fb4 ) 8009f22: 4293 cmp r3, r2 8009f24: d031 beq.n 8009f8a 8009f26: 687b ldr r3, [r7, #4] 8009f28: 681b ldr r3, [r3, #0] 8009f2a: 4a23 ldr r2, [pc, #140] @ (8009fb8 ) 8009f2c: 4293 cmp r3, r2 8009f2e: d02c beq.n 8009f8a 8009f30: 687b ldr r3, [r7, #4] 8009f32: 681b ldr r3, [r3, #0] 8009f34: 4a21 ldr r2, [pc, #132] @ (8009fbc ) 8009f36: 4293 cmp r3, r2 8009f38: d027 beq.n 8009f8a 8009f3a: 687b ldr r3, [r7, #4] 8009f3c: 681b ldr r3, [r3, #0] 8009f3e: 4a20 ldr r2, [pc, #128] @ (8009fc0 ) 8009f40: 4293 cmp r3, r2 8009f42: d022 beq.n 8009f8a 8009f44: 687b ldr r3, [r7, #4] 8009f46: 681b ldr r3, [r3, #0] 8009f48: 4a1e ldr r2, [pc, #120] @ (8009fc4 ) 8009f4a: 4293 cmp r3, r2 8009f4c: d01d beq.n 8009f8a 8009f4e: 687b ldr r3, [r7, #4] 8009f50: 681b ldr r3, [r3, #0] 8009f52: 4a1d ldr r2, [pc, #116] @ (8009fc8 ) 8009f54: 4293 cmp r3, r2 8009f56: d018 beq.n 8009f8a 8009f58: 687b ldr r3, [r7, #4] 8009f5a: 681b ldr r3, [r3, #0] 8009f5c: 4a1b ldr r2, [pc, #108] @ (8009fcc ) 8009f5e: 4293 cmp r3, r2 8009f60: d013 beq.n 8009f8a 8009f62: 687b ldr r3, [r7, #4] 8009f64: 681b ldr r3, [r3, #0] 8009f66: 4a1a ldr r2, [pc, #104] @ (8009fd0 ) 8009f68: 4293 cmp r3, r2 8009f6a: d00e beq.n 8009f8a 8009f6c: 687b ldr r3, [r7, #4] 8009f6e: 681b ldr r3, [r3, #0] 8009f70: 4a18 ldr r2, [pc, #96] @ (8009fd4 ) 8009f72: 4293 cmp r3, r2 8009f74: d009 beq.n 8009f8a 8009f76: 687b ldr r3, [r7, #4] 8009f78: 681b ldr r3, [r3, #0] 8009f7a: 4a17 ldr r2, [pc, #92] @ (8009fd8 ) 8009f7c: 4293 cmp r3, r2 8009f7e: d004 beq.n 8009f8a 8009f80: 687b ldr r3, [r7, #4] 8009f82: 681b ldr r3, [r3, #0] 8009f84: 4a15 ldr r2, [pc, #84] @ (8009fdc ) 8009f86: 4293 cmp r3, r2 8009f88: d12a bne.n 8009fe0 8009f8a: 687b ldr r3, [r7, #4] 8009f8c: 681b ldr r3, [r3, #0] 8009f8e: 681b ldr r3, [r3, #0] 8009f90: f003 0302 and.w r3, r3, #2 8009f94: 2b00 cmp r3, #0 8009f96: bf14 ite ne 8009f98: 2301 movne r3, #1 8009f9a: 2300 moveq r3, #0 8009f9c: b2db uxtb r3, r3 8009f9e: e023 b.n 8009fe8 8009fa0: 40020010 .word 0x40020010 8009fa4: 40020028 .word 0x40020028 8009fa8: 40020040 .word 0x40020040 8009fac: 40020058 .word 0x40020058 8009fb0: 40020070 .word 0x40020070 8009fb4: 40020088 .word 0x40020088 8009fb8: 400200a0 .word 0x400200a0 8009fbc: 400200b8 .word 0x400200b8 8009fc0: 40020410 .word 0x40020410 8009fc4: 40020428 .word 0x40020428 8009fc8: 40020440 .word 0x40020440 8009fcc: 40020458 .word 0x40020458 8009fd0: 40020470 .word 0x40020470 8009fd4: 40020488 .word 0x40020488 8009fd8: 400204a0 .word 0x400204a0 8009fdc: 400204b8 .word 0x400204b8 8009fe0: 687b ldr r3, [r7, #4] 8009fe2: 681b ldr r3, [r3, #0] 8009fe4: 681b ldr r3, [r3, #0] 8009fe6: 2300 movs r3, #0 8009fe8: 2b00 cmp r3, #0 8009fea: d00d beq.n 800a008 { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009fec: 687b ldr r3, [r7, #4] 8009fee: 6ddb ldr r3, [r3, #92] @ 0x5c 8009ff0: f003 031f and.w r3, r3, #31 8009ff4: 2204 movs r2, #4 8009ff6: 409a lsls r2, r3 8009ff8: 6a3b ldr r3, [r7, #32] 8009ffa: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 8009ffc: 687b ldr r3, [r7, #4] 8009ffe: 6d5b ldr r3, [r3, #84] @ 0x54 800a000: f043 0204 orr.w r2, r3, #4 800a004: 687b ldr r3, [r7, #4] 800a006: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800a008: 687b ldr r3, [r7, #4] 800a00a: 6ddb ldr r3, [r3, #92] @ 0x5c 800a00c: f003 031f and.w r3, r3, #31 800a010: 2210 movs r2, #16 800a012: 409a lsls r2, r3 800a014: 69bb ldr r3, [r7, #24] 800a016: 4013 ands r3, r2 800a018: 2b00 cmp r3, #0 800a01a: f000 80a6 beq.w 800a16a { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 800a01e: 687b ldr r3, [r7, #4] 800a020: 681b ldr r3, [r3, #0] 800a022: 4a85 ldr r2, [pc, #532] @ (800a238 ) 800a024: 4293 cmp r3, r2 800a026: d04a beq.n 800a0be 800a028: 687b ldr r3, [r7, #4] 800a02a: 681b ldr r3, [r3, #0] 800a02c: 4a83 ldr r2, [pc, #524] @ (800a23c ) 800a02e: 4293 cmp r3, r2 800a030: d045 beq.n 800a0be 800a032: 687b ldr r3, [r7, #4] 800a034: 681b ldr r3, [r3, #0] 800a036: 4a82 ldr r2, [pc, #520] @ (800a240 ) 800a038: 4293 cmp r3, r2 800a03a: d040 beq.n 800a0be 800a03c: 687b ldr r3, [r7, #4] 800a03e: 681b ldr r3, [r3, #0] 800a040: 4a80 ldr r2, [pc, #512] @ (800a244 ) 800a042: 4293 cmp r3, r2 800a044: d03b beq.n 800a0be 800a046: 687b ldr r3, [r7, #4] 800a048: 681b ldr r3, [r3, #0] 800a04a: 4a7f ldr r2, [pc, #508] @ (800a248 ) 800a04c: 4293 cmp r3, r2 800a04e: d036 beq.n 800a0be 800a050: 687b ldr r3, [r7, #4] 800a052: 681b ldr r3, [r3, #0] 800a054: 4a7d ldr r2, [pc, #500] @ (800a24c ) 800a056: 4293 cmp r3, r2 800a058: d031 beq.n 800a0be 800a05a: 687b ldr r3, [r7, #4] 800a05c: 681b ldr r3, [r3, #0] 800a05e: 4a7c ldr r2, [pc, #496] @ (800a250 ) 800a060: 4293 cmp r3, r2 800a062: d02c beq.n 800a0be 800a064: 687b ldr r3, [r7, #4] 800a066: 681b ldr r3, [r3, #0] 800a068: 4a7a ldr r2, [pc, #488] @ (800a254 ) 800a06a: 4293 cmp r3, r2 800a06c: d027 beq.n 800a0be 800a06e: 687b ldr r3, [r7, #4] 800a070: 681b ldr r3, [r3, #0] 800a072: 4a79 ldr r2, [pc, #484] @ (800a258 ) 800a074: 4293 cmp r3, r2 800a076: d022 beq.n 800a0be 800a078: 687b ldr r3, [r7, #4] 800a07a: 681b ldr r3, [r3, #0] 800a07c: 4a77 ldr r2, [pc, #476] @ (800a25c ) 800a07e: 4293 cmp r3, r2 800a080: d01d beq.n 800a0be 800a082: 687b ldr r3, [r7, #4] 800a084: 681b ldr r3, [r3, #0] 800a086: 4a76 ldr r2, [pc, #472] @ (800a260 ) 800a088: 4293 cmp r3, r2 800a08a: d018 beq.n 800a0be 800a08c: 687b ldr r3, [r7, #4] 800a08e: 681b ldr r3, [r3, #0] 800a090: 4a74 ldr r2, [pc, #464] @ (800a264 ) 800a092: 4293 cmp r3, r2 800a094: d013 beq.n 800a0be 800a096: 687b ldr r3, [r7, #4] 800a098: 681b ldr r3, [r3, #0] 800a09a: 4a73 ldr r2, [pc, #460] @ (800a268 ) 800a09c: 4293 cmp r3, r2 800a09e: d00e beq.n 800a0be 800a0a0: 687b ldr r3, [r7, #4] 800a0a2: 681b ldr r3, [r3, #0] 800a0a4: 4a71 ldr r2, [pc, #452] @ (800a26c ) 800a0a6: 4293 cmp r3, r2 800a0a8: d009 beq.n 800a0be 800a0aa: 687b ldr r3, [r7, #4] 800a0ac: 681b ldr r3, [r3, #0] 800a0ae: 4a70 ldr r2, [pc, #448] @ (800a270 ) 800a0b0: 4293 cmp r3, r2 800a0b2: d004 beq.n 800a0be 800a0b4: 687b ldr r3, [r7, #4] 800a0b6: 681b ldr r3, [r3, #0] 800a0b8: 4a6e ldr r2, [pc, #440] @ (800a274 ) 800a0ba: 4293 cmp r3, r2 800a0bc: d10a bne.n 800a0d4 800a0be: 687b ldr r3, [r7, #4] 800a0c0: 681b ldr r3, [r3, #0] 800a0c2: 681b ldr r3, [r3, #0] 800a0c4: f003 0308 and.w r3, r3, #8 800a0c8: 2b00 cmp r3, #0 800a0ca: bf14 ite ne 800a0cc: 2301 movne r3, #1 800a0ce: 2300 moveq r3, #0 800a0d0: b2db uxtb r3, r3 800a0d2: e009 b.n 800a0e8 800a0d4: 687b ldr r3, [r7, #4] 800a0d6: 681b ldr r3, [r3, #0] 800a0d8: 681b ldr r3, [r3, #0] 800a0da: f003 0304 and.w r3, r3, #4 800a0de: 2b00 cmp r3, #0 800a0e0: bf14 ite ne 800a0e2: 2301 movne r3, #1 800a0e4: 2300 moveq r3, #0 800a0e6: b2db uxtb r3, r3 800a0e8: 2b00 cmp r3, #0 800a0ea: d03e beq.n 800a16a { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 800a0ec: 687b ldr r3, [r7, #4] 800a0ee: 6ddb ldr r3, [r3, #92] @ 0x5c 800a0f0: f003 031f and.w r3, r3, #31 800a0f4: 2210 movs r2, #16 800a0f6: 409a lsls r2, r3 800a0f8: 6a3b ldr r3, [r7, #32] 800a0fa: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a0fc: 687b ldr r3, [r7, #4] 800a0fe: 681b ldr r3, [r3, #0] 800a100: 681b ldr r3, [r3, #0] 800a102: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a106: 2b00 cmp r3, #0 800a108: d018 beq.n 800a13c { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a10a: 687b ldr r3, [r7, #4] 800a10c: 681b ldr r3, [r3, #0] 800a10e: 681b ldr r3, [r3, #0] 800a110: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a114: 2b00 cmp r3, #0 800a116: d108 bne.n 800a12a { if(hdma->XferHalfCpltCallback != NULL) 800a118: 687b ldr r3, [r7, #4] 800a11a: 6c1b ldr r3, [r3, #64] @ 0x40 800a11c: 2b00 cmp r3, #0 800a11e: d024 beq.n 800a16a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a120: 687b ldr r3, [r7, #4] 800a122: 6c1b ldr r3, [r3, #64] @ 0x40 800a124: 6878 ldr r0, [r7, #4] 800a126: 4798 blx r3 800a128: e01f b.n 800a16a } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800a12a: 687b ldr r3, [r7, #4] 800a12c: 6c9b ldr r3, [r3, #72] @ 0x48 800a12e: 2b00 cmp r3, #0 800a130: d01b beq.n 800a16a { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 800a132: 687b ldr r3, [r7, #4] 800a134: 6c9b ldr r3, [r3, #72] @ 0x48 800a136: 6878 ldr r0, [r7, #4] 800a138: 4798 blx r3 800a13a: e016 b.n 800a16a } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a13c: 687b ldr r3, [r7, #4] 800a13e: 681b ldr r3, [r3, #0] 800a140: 681b ldr r3, [r3, #0] 800a142: f403 7380 and.w r3, r3, #256 @ 0x100 800a146: 2b00 cmp r3, #0 800a148: d107 bne.n 800a15a { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a14a: 687b ldr r3, [r7, #4] 800a14c: 681b ldr r3, [r3, #0] 800a14e: 681a ldr r2, [r3, #0] 800a150: 687b ldr r3, [r7, #4] 800a152: 681b ldr r3, [r3, #0] 800a154: f022 0208 bic.w r2, r2, #8 800a158: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800a15a: 687b ldr r3, [r7, #4] 800a15c: 6c1b ldr r3, [r3, #64] @ 0x40 800a15e: 2b00 cmp r3, #0 800a160: d003 beq.n 800a16a { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a162: 687b ldr r3, [r7, #4] 800a164: 6c1b ldr r3, [r3, #64] @ 0x40 800a166: 6878 ldr r0, [r7, #4] 800a168: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800a16a: 687b ldr r3, [r7, #4] 800a16c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a16e: f003 031f and.w r3, r3, #31 800a172: 2220 movs r2, #32 800a174: 409a lsls r2, r3 800a176: 69bb ldr r3, [r7, #24] 800a178: 4013 ands r3, r2 800a17a: 2b00 cmp r3, #0 800a17c: f000 8110 beq.w 800a3a0 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 800a180: 687b ldr r3, [r7, #4] 800a182: 681b ldr r3, [r3, #0] 800a184: 4a2c ldr r2, [pc, #176] @ (800a238 ) 800a186: 4293 cmp r3, r2 800a188: d04a beq.n 800a220 800a18a: 687b ldr r3, [r7, #4] 800a18c: 681b ldr r3, [r3, #0] 800a18e: 4a2b ldr r2, [pc, #172] @ (800a23c ) 800a190: 4293 cmp r3, r2 800a192: d045 beq.n 800a220 800a194: 687b ldr r3, [r7, #4] 800a196: 681b ldr r3, [r3, #0] 800a198: 4a29 ldr r2, [pc, #164] @ (800a240 ) 800a19a: 4293 cmp r3, r2 800a19c: d040 beq.n 800a220 800a19e: 687b ldr r3, [r7, #4] 800a1a0: 681b ldr r3, [r3, #0] 800a1a2: 4a28 ldr r2, [pc, #160] @ (800a244 ) 800a1a4: 4293 cmp r3, r2 800a1a6: d03b beq.n 800a220 800a1a8: 687b ldr r3, [r7, #4] 800a1aa: 681b ldr r3, [r3, #0] 800a1ac: 4a26 ldr r2, [pc, #152] @ (800a248 ) 800a1ae: 4293 cmp r3, r2 800a1b0: d036 beq.n 800a220 800a1b2: 687b ldr r3, [r7, #4] 800a1b4: 681b ldr r3, [r3, #0] 800a1b6: 4a25 ldr r2, [pc, #148] @ (800a24c ) 800a1b8: 4293 cmp r3, r2 800a1ba: d031 beq.n 800a220 800a1bc: 687b ldr r3, [r7, #4] 800a1be: 681b ldr r3, [r3, #0] 800a1c0: 4a23 ldr r2, [pc, #140] @ (800a250 ) 800a1c2: 4293 cmp r3, r2 800a1c4: d02c beq.n 800a220 800a1c6: 687b ldr r3, [r7, #4] 800a1c8: 681b ldr r3, [r3, #0] 800a1ca: 4a22 ldr r2, [pc, #136] @ (800a254 ) 800a1cc: 4293 cmp r3, r2 800a1ce: d027 beq.n 800a220 800a1d0: 687b ldr r3, [r7, #4] 800a1d2: 681b ldr r3, [r3, #0] 800a1d4: 4a20 ldr r2, [pc, #128] @ (800a258 ) 800a1d6: 4293 cmp r3, r2 800a1d8: d022 beq.n 800a220 800a1da: 687b ldr r3, [r7, #4] 800a1dc: 681b ldr r3, [r3, #0] 800a1de: 4a1f ldr r2, [pc, #124] @ (800a25c ) 800a1e0: 4293 cmp r3, r2 800a1e2: d01d beq.n 800a220 800a1e4: 687b ldr r3, [r7, #4] 800a1e6: 681b ldr r3, [r3, #0] 800a1e8: 4a1d ldr r2, [pc, #116] @ (800a260 ) 800a1ea: 4293 cmp r3, r2 800a1ec: d018 beq.n 800a220 800a1ee: 687b ldr r3, [r7, #4] 800a1f0: 681b ldr r3, [r3, #0] 800a1f2: 4a1c ldr r2, [pc, #112] @ (800a264 ) 800a1f4: 4293 cmp r3, r2 800a1f6: d013 beq.n 800a220 800a1f8: 687b ldr r3, [r7, #4] 800a1fa: 681b ldr r3, [r3, #0] 800a1fc: 4a1a ldr r2, [pc, #104] @ (800a268 ) 800a1fe: 4293 cmp r3, r2 800a200: d00e beq.n 800a220 800a202: 687b ldr r3, [r7, #4] 800a204: 681b ldr r3, [r3, #0] 800a206: 4a19 ldr r2, [pc, #100] @ (800a26c ) 800a208: 4293 cmp r3, r2 800a20a: d009 beq.n 800a220 800a20c: 687b ldr r3, [r7, #4] 800a20e: 681b ldr r3, [r3, #0] 800a210: 4a17 ldr r2, [pc, #92] @ (800a270 ) 800a212: 4293 cmp r3, r2 800a214: d004 beq.n 800a220 800a216: 687b ldr r3, [r7, #4] 800a218: 681b ldr r3, [r3, #0] 800a21a: 4a16 ldr r2, [pc, #88] @ (800a274 ) 800a21c: 4293 cmp r3, r2 800a21e: d12b bne.n 800a278 800a220: 687b ldr r3, [r7, #4] 800a222: 681b ldr r3, [r3, #0] 800a224: 681b ldr r3, [r3, #0] 800a226: f003 0310 and.w r3, r3, #16 800a22a: 2b00 cmp r3, #0 800a22c: bf14 ite ne 800a22e: 2301 movne r3, #1 800a230: 2300 moveq r3, #0 800a232: b2db uxtb r3, r3 800a234: e02a b.n 800a28c 800a236: bf00 nop 800a238: 40020010 .word 0x40020010 800a23c: 40020028 .word 0x40020028 800a240: 40020040 .word 0x40020040 800a244: 40020058 .word 0x40020058 800a248: 40020070 .word 0x40020070 800a24c: 40020088 .word 0x40020088 800a250: 400200a0 .word 0x400200a0 800a254: 400200b8 .word 0x400200b8 800a258: 40020410 .word 0x40020410 800a25c: 40020428 .word 0x40020428 800a260: 40020440 .word 0x40020440 800a264: 40020458 .word 0x40020458 800a268: 40020470 .word 0x40020470 800a26c: 40020488 .word 0x40020488 800a270: 400204a0 .word 0x400204a0 800a274: 400204b8 .word 0x400204b8 800a278: 687b ldr r3, [r7, #4] 800a27a: 681b ldr r3, [r3, #0] 800a27c: 681b ldr r3, [r3, #0] 800a27e: f003 0302 and.w r3, r3, #2 800a282: 2b00 cmp r3, #0 800a284: bf14 ite ne 800a286: 2301 movne r3, #1 800a288: 2300 moveq r3, #0 800a28a: b2db uxtb r3, r3 800a28c: 2b00 cmp r3, #0 800a28e: f000 8087 beq.w 800a3a0 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 800a292: 687b ldr r3, [r7, #4] 800a294: 6ddb ldr r3, [r3, #92] @ 0x5c 800a296: f003 031f and.w r3, r3, #31 800a29a: 2220 movs r2, #32 800a29c: 409a lsls r2, r3 800a29e: 6a3b ldr r3, [r7, #32] 800a2a0: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800a2a2: 687b ldr r3, [r7, #4] 800a2a4: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800a2a8: b2db uxtb r3, r3 800a2aa: 2b04 cmp r3, #4 800a2ac: d139 bne.n 800a322 { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800a2ae: 687b ldr r3, [r7, #4] 800a2b0: 681b ldr r3, [r3, #0] 800a2b2: 681a ldr r2, [r3, #0] 800a2b4: 687b ldr r3, [r7, #4] 800a2b6: 681b ldr r3, [r3, #0] 800a2b8: f022 0216 bic.w r2, r2, #22 800a2bc: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800a2be: 687b ldr r3, [r7, #4] 800a2c0: 681b ldr r3, [r3, #0] 800a2c2: 695a ldr r2, [r3, #20] 800a2c4: 687b ldr r3, [r7, #4] 800a2c6: 681b ldr r3, [r3, #0] 800a2c8: f022 0280 bic.w r2, r2, #128 @ 0x80 800a2cc: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800a2ce: 687b ldr r3, [r7, #4] 800a2d0: 6c1b ldr r3, [r3, #64] @ 0x40 800a2d2: 2b00 cmp r3, #0 800a2d4: d103 bne.n 800a2de 800a2d6: 687b ldr r3, [r7, #4] 800a2d8: 6c9b ldr r3, [r3, #72] @ 0x48 800a2da: 2b00 cmp r3, #0 800a2dc: d007 beq.n 800a2ee { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a2de: 687b ldr r3, [r7, #4] 800a2e0: 681b ldr r3, [r3, #0] 800a2e2: 681a ldr r2, [r3, #0] 800a2e4: 687b ldr r3, [r7, #4] 800a2e6: 681b ldr r3, [r3, #0] 800a2e8: f022 0208 bic.w r2, r2, #8 800a2ec: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800a2ee: 687b ldr r3, [r7, #4] 800a2f0: 6ddb ldr r3, [r3, #92] @ 0x5c 800a2f2: f003 031f and.w r3, r3, #31 800a2f6: 223f movs r2, #63 @ 0x3f 800a2f8: 409a lsls r2, r3 800a2fa: 6a3b ldr r3, [r7, #32] 800a2fc: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a2fe: 687b ldr r3, [r7, #4] 800a300: 2201 movs r2, #1 800a302: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a306: 687b ldr r3, [r7, #4] 800a308: 2200 movs r2, #0 800a30a: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 800a30e: 687b ldr r3, [r7, #4] 800a310: 6d1b ldr r3, [r3, #80] @ 0x50 800a312: 2b00 cmp r3, #0 800a314: f000 834a beq.w 800a9ac { hdma->XferAbortCallback(hdma); 800a318: 687b ldr r3, [r7, #4] 800a31a: 6d1b ldr r3, [r3, #80] @ 0x50 800a31c: 6878 ldr r0, [r7, #4] 800a31e: 4798 blx r3 } return; 800a320: e344 b.n 800a9ac } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a322: 687b ldr r3, [r7, #4] 800a324: 681b ldr r3, [r3, #0] 800a326: 681b ldr r3, [r3, #0] 800a328: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a32c: 2b00 cmp r3, #0 800a32e: d018 beq.n 800a362 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a330: 687b ldr r3, [r7, #4] 800a332: 681b ldr r3, [r3, #0] 800a334: 681b ldr r3, [r3, #0] 800a336: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a33a: 2b00 cmp r3, #0 800a33c: d108 bne.n 800a350 { if(hdma->XferM1CpltCallback != NULL) 800a33e: 687b ldr r3, [r7, #4] 800a340: 6c5b ldr r3, [r3, #68] @ 0x44 800a342: 2b00 cmp r3, #0 800a344: d02c beq.n 800a3a0 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 800a346: 687b ldr r3, [r7, #4] 800a348: 6c5b ldr r3, [r3, #68] @ 0x44 800a34a: 6878 ldr r0, [r7, #4] 800a34c: 4798 blx r3 800a34e: e027 b.n 800a3a0 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a350: 687b ldr r3, [r7, #4] 800a352: 6bdb ldr r3, [r3, #60] @ 0x3c 800a354: 2b00 cmp r3, #0 800a356: d023 beq.n 800a3a0 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 800a358: 687b ldr r3, [r7, #4] 800a35a: 6bdb ldr r3, [r3, #60] @ 0x3c 800a35c: 6878 ldr r0, [r7, #4] 800a35e: 4798 blx r3 800a360: e01e b.n 800a3a0 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a362: 687b ldr r3, [r7, #4] 800a364: 681b ldr r3, [r3, #0] 800a366: 681b ldr r3, [r3, #0] 800a368: f403 7380 and.w r3, r3, #256 @ 0x100 800a36c: 2b00 cmp r3, #0 800a36e: d10f bne.n 800a390 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 800a370: 687b ldr r3, [r7, #4] 800a372: 681b ldr r3, [r3, #0] 800a374: 681a ldr r2, [r3, #0] 800a376: 687b ldr r3, [r7, #4] 800a378: 681b ldr r3, [r3, #0] 800a37a: f022 0210 bic.w r2, r2, #16 800a37e: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a380: 687b ldr r3, [r7, #4] 800a382: 2201 movs r2, #1 800a384: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a388: 687b ldr r3, [r7, #4] 800a38a: 2200 movs r2, #0 800a38c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a390: 687b ldr r3, [r7, #4] 800a392: 6bdb ldr r3, [r3, #60] @ 0x3c 800a394: 2b00 cmp r3, #0 800a396: d003 beq.n 800a3a0 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a398: 687b ldr r3, [r7, #4] 800a39a: 6bdb ldr r3, [r3, #60] @ 0x3c 800a39c: 6878 ldr r0, [r7, #4] 800a39e: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800a3a0: 687b ldr r3, [r7, #4] 800a3a2: 6d5b ldr r3, [r3, #84] @ 0x54 800a3a4: 2b00 cmp r3, #0 800a3a6: f000 8306 beq.w 800a9b6 { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800a3aa: 687b ldr r3, [r7, #4] 800a3ac: 6d5b ldr r3, [r3, #84] @ 0x54 800a3ae: f003 0301 and.w r3, r3, #1 800a3b2: 2b00 cmp r3, #0 800a3b4: f000 8088 beq.w 800a4c8 { hdma->State = HAL_DMA_STATE_ABORT; 800a3b8: 687b ldr r3, [r7, #4] 800a3ba: 2204 movs r2, #4 800a3bc: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800a3c0: 687b ldr r3, [r7, #4] 800a3c2: 681b ldr r3, [r3, #0] 800a3c4: 4a7a ldr r2, [pc, #488] @ (800a5b0 ) 800a3c6: 4293 cmp r3, r2 800a3c8: d04a beq.n 800a460 800a3ca: 687b ldr r3, [r7, #4] 800a3cc: 681b ldr r3, [r3, #0] 800a3ce: 4a79 ldr r2, [pc, #484] @ (800a5b4 ) 800a3d0: 4293 cmp r3, r2 800a3d2: d045 beq.n 800a460 800a3d4: 687b ldr r3, [r7, #4] 800a3d6: 681b ldr r3, [r3, #0] 800a3d8: 4a77 ldr r2, [pc, #476] @ (800a5b8 ) 800a3da: 4293 cmp r3, r2 800a3dc: d040 beq.n 800a460 800a3de: 687b ldr r3, [r7, #4] 800a3e0: 681b ldr r3, [r3, #0] 800a3e2: 4a76 ldr r2, [pc, #472] @ (800a5bc ) 800a3e4: 4293 cmp r3, r2 800a3e6: d03b beq.n 800a460 800a3e8: 687b ldr r3, [r7, #4] 800a3ea: 681b ldr r3, [r3, #0] 800a3ec: 4a74 ldr r2, [pc, #464] @ (800a5c0 ) 800a3ee: 4293 cmp r3, r2 800a3f0: d036 beq.n 800a460 800a3f2: 687b ldr r3, [r7, #4] 800a3f4: 681b ldr r3, [r3, #0] 800a3f6: 4a73 ldr r2, [pc, #460] @ (800a5c4 ) 800a3f8: 4293 cmp r3, r2 800a3fa: d031 beq.n 800a460 800a3fc: 687b ldr r3, [r7, #4] 800a3fe: 681b ldr r3, [r3, #0] 800a400: 4a71 ldr r2, [pc, #452] @ (800a5c8 ) 800a402: 4293 cmp r3, r2 800a404: d02c beq.n 800a460 800a406: 687b ldr r3, [r7, #4] 800a408: 681b ldr r3, [r3, #0] 800a40a: 4a70 ldr r2, [pc, #448] @ (800a5cc ) 800a40c: 4293 cmp r3, r2 800a40e: d027 beq.n 800a460 800a410: 687b ldr r3, [r7, #4] 800a412: 681b ldr r3, [r3, #0] 800a414: 4a6e ldr r2, [pc, #440] @ (800a5d0 ) 800a416: 4293 cmp r3, r2 800a418: d022 beq.n 800a460 800a41a: 687b ldr r3, [r7, #4] 800a41c: 681b ldr r3, [r3, #0] 800a41e: 4a6d ldr r2, [pc, #436] @ (800a5d4 ) 800a420: 4293 cmp r3, r2 800a422: d01d beq.n 800a460 800a424: 687b ldr r3, [r7, #4] 800a426: 681b ldr r3, [r3, #0] 800a428: 4a6b ldr r2, [pc, #428] @ (800a5d8 ) 800a42a: 4293 cmp r3, r2 800a42c: d018 beq.n 800a460 800a42e: 687b ldr r3, [r7, #4] 800a430: 681b ldr r3, [r3, #0] 800a432: 4a6a ldr r2, [pc, #424] @ (800a5dc ) 800a434: 4293 cmp r3, r2 800a436: d013 beq.n 800a460 800a438: 687b ldr r3, [r7, #4] 800a43a: 681b ldr r3, [r3, #0] 800a43c: 4a68 ldr r2, [pc, #416] @ (800a5e0 ) 800a43e: 4293 cmp r3, r2 800a440: d00e beq.n 800a460 800a442: 687b ldr r3, [r7, #4] 800a444: 681b ldr r3, [r3, #0] 800a446: 4a67 ldr r2, [pc, #412] @ (800a5e4 ) 800a448: 4293 cmp r3, r2 800a44a: d009 beq.n 800a460 800a44c: 687b ldr r3, [r7, #4] 800a44e: 681b ldr r3, [r3, #0] 800a450: 4a65 ldr r2, [pc, #404] @ (800a5e8 ) 800a452: 4293 cmp r3, r2 800a454: d004 beq.n 800a460 800a456: 687b ldr r3, [r7, #4] 800a458: 681b ldr r3, [r3, #0] 800a45a: 4a64 ldr r2, [pc, #400] @ (800a5ec ) 800a45c: 4293 cmp r3, r2 800a45e: d108 bne.n 800a472 800a460: 687b ldr r3, [r7, #4] 800a462: 681b ldr r3, [r3, #0] 800a464: 681a ldr r2, [r3, #0] 800a466: 687b ldr r3, [r7, #4] 800a468: 681b ldr r3, [r3, #0] 800a46a: f022 0201 bic.w r2, r2, #1 800a46e: 601a str r2, [r3, #0] 800a470: e007 b.n 800a482 800a472: 687b ldr r3, [r7, #4] 800a474: 681b ldr r3, [r3, #0] 800a476: 681a ldr r2, [r3, #0] 800a478: 687b ldr r3, [r7, #4] 800a47a: 681b ldr r3, [r3, #0] 800a47c: f022 0201 bic.w r2, r2, #1 800a480: 601a str r2, [r3, #0] do { if (++count > timeout) 800a482: 68fb ldr r3, [r7, #12] 800a484: 3301 adds r3, #1 800a486: 60fb str r3, [r7, #12] 800a488: 6a7a ldr r2, [r7, #36] @ 0x24 800a48a: 429a cmp r2, r3 800a48c: d307 bcc.n 800a49e { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800a48e: 687b ldr r3, [r7, #4] 800a490: 681b ldr r3, [r3, #0] 800a492: 681b ldr r3, [r3, #0] 800a494: f003 0301 and.w r3, r3, #1 800a498: 2b00 cmp r3, #0 800a49a: d1f2 bne.n 800a482 800a49c: e000 b.n 800a4a0 break; 800a49e: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800a4a0: 687b ldr r3, [r7, #4] 800a4a2: 681b ldr r3, [r3, #0] 800a4a4: 681b ldr r3, [r3, #0] 800a4a6: f003 0301 and.w r3, r3, #1 800a4aa: 2b00 cmp r3, #0 800a4ac: d004 beq.n 800a4b8 { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800a4ae: 687b ldr r3, [r7, #4] 800a4b0: 2203 movs r2, #3 800a4b2: f883 2035 strb.w r2, [r3, #53] @ 0x35 800a4b6: e003 b.n 800a4c0 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 800a4b8: 687b ldr r3, [r7, #4] 800a4ba: 2201 movs r2, #1 800a4bc: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a4c0: 687b ldr r3, [r7, #4] 800a4c2: 2200 movs r2, #0 800a4c4: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 800a4c8: 687b ldr r3, [r7, #4] 800a4ca: 6cdb ldr r3, [r3, #76] @ 0x4c 800a4cc: 2b00 cmp r3, #0 800a4ce: f000 8272 beq.w 800a9b6 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a4d2: 687b ldr r3, [r7, #4] 800a4d4: 6cdb ldr r3, [r3, #76] @ 0x4c 800a4d6: 6878 ldr r0, [r7, #4] 800a4d8: 4798 blx r3 800a4da: e26c b.n 800a9b6 } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800a4dc: 687b ldr r3, [r7, #4] 800a4de: 681b ldr r3, [r3, #0] 800a4e0: 4a43 ldr r2, [pc, #268] @ (800a5f0 ) 800a4e2: 4293 cmp r3, r2 800a4e4: d022 beq.n 800a52c 800a4e6: 687b ldr r3, [r7, #4] 800a4e8: 681b ldr r3, [r3, #0] 800a4ea: 4a42 ldr r2, [pc, #264] @ (800a5f4 ) 800a4ec: 4293 cmp r3, r2 800a4ee: d01d beq.n 800a52c 800a4f0: 687b ldr r3, [r7, #4] 800a4f2: 681b ldr r3, [r3, #0] 800a4f4: 4a40 ldr r2, [pc, #256] @ (800a5f8 ) 800a4f6: 4293 cmp r3, r2 800a4f8: d018 beq.n 800a52c 800a4fa: 687b ldr r3, [r7, #4] 800a4fc: 681b ldr r3, [r3, #0] 800a4fe: 4a3f ldr r2, [pc, #252] @ (800a5fc ) 800a500: 4293 cmp r3, r2 800a502: d013 beq.n 800a52c 800a504: 687b ldr r3, [r7, #4] 800a506: 681b ldr r3, [r3, #0] 800a508: 4a3d ldr r2, [pc, #244] @ (800a600 ) 800a50a: 4293 cmp r3, r2 800a50c: d00e beq.n 800a52c 800a50e: 687b ldr r3, [r7, #4] 800a510: 681b ldr r3, [r3, #0] 800a512: 4a3c ldr r2, [pc, #240] @ (800a604 ) 800a514: 4293 cmp r3, r2 800a516: d009 beq.n 800a52c 800a518: 687b ldr r3, [r7, #4] 800a51a: 681b ldr r3, [r3, #0] 800a51c: 4a3a ldr r2, [pc, #232] @ (800a608 ) 800a51e: 4293 cmp r3, r2 800a520: d004 beq.n 800a52c 800a522: 687b ldr r3, [r7, #4] 800a524: 681b ldr r3, [r3, #0] 800a526: 4a39 ldr r2, [pc, #228] @ (800a60c ) 800a528: 4293 cmp r3, r2 800a52a: d101 bne.n 800a530 800a52c: 2301 movs r3, #1 800a52e: e000 b.n 800a532 800a530: 2300 movs r3, #0 800a532: 2b00 cmp r3, #0 800a534: f000 823f beq.w 800a9b6 { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 800a538: 687b ldr r3, [r7, #4] 800a53a: 681b ldr r3, [r3, #0] 800a53c: 681b ldr r3, [r3, #0] 800a53e: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 800a540: 687b ldr r3, [r7, #4] 800a542: 6ddb ldr r3, [r3, #92] @ 0x5c 800a544: f003 031f and.w r3, r3, #31 800a548: 2204 movs r2, #4 800a54a: 409a lsls r2, r3 800a54c: 697b ldr r3, [r7, #20] 800a54e: 4013 ands r3, r2 800a550: 2b00 cmp r3, #0 800a552: f000 80cd beq.w 800a6f0 800a556: 693b ldr r3, [r7, #16] 800a558: f003 0304 and.w r3, r3, #4 800a55c: 2b00 cmp r3, #0 800a55e: f000 80c7 beq.w 800a6f0 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 800a562: 687b ldr r3, [r7, #4] 800a564: 6ddb ldr r3, [r3, #92] @ 0x5c 800a566: f003 031f and.w r3, r3, #31 800a56a: 2204 movs r2, #4 800a56c: 409a lsls r2, r3 800a56e: 69fb ldr r3, [r7, #28] 800a570: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a572: 693b ldr r3, [r7, #16] 800a574: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a578: 2b00 cmp r3, #0 800a57a: d049 beq.n 800a610 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a57c: 693b ldr r3, [r7, #16] 800a57e: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a582: 2b00 cmp r3, #0 800a584: d109 bne.n 800a59a { if(hdma->XferM1HalfCpltCallback != NULL) 800a586: 687b ldr r3, [r7, #4] 800a588: 6c9b ldr r3, [r3, #72] @ 0x48 800a58a: 2b00 cmp r3, #0 800a58c: f000 8210 beq.w 800a9b0 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 800a590: 687b ldr r3, [r7, #4] 800a592: 6c9b ldr r3, [r3, #72] @ 0x48 800a594: 6878 ldr r0, [r7, #4] 800a596: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a598: e20a b.n 800a9b0 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 800a59a: 687b ldr r3, [r7, #4] 800a59c: 6c1b ldr r3, [r3, #64] @ 0x40 800a59e: 2b00 cmp r3, #0 800a5a0: f000 8206 beq.w 800a9b0 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 800a5a4: 687b ldr r3, [r7, #4] 800a5a6: 6c1b ldr r3, [r3, #64] @ 0x40 800a5a8: 6878 ldr r0, [r7, #4] 800a5aa: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a5ac: e200 b.n 800a9b0 800a5ae: bf00 nop 800a5b0: 40020010 .word 0x40020010 800a5b4: 40020028 .word 0x40020028 800a5b8: 40020040 .word 0x40020040 800a5bc: 40020058 .word 0x40020058 800a5c0: 40020070 .word 0x40020070 800a5c4: 40020088 .word 0x40020088 800a5c8: 400200a0 .word 0x400200a0 800a5cc: 400200b8 .word 0x400200b8 800a5d0: 40020410 .word 0x40020410 800a5d4: 40020428 .word 0x40020428 800a5d8: 40020440 .word 0x40020440 800a5dc: 40020458 .word 0x40020458 800a5e0: 40020470 .word 0x40020470 800a5e4: 40020488 .word 0x40020488 800a5e8: 400204a0 .word 0x400204a0 800a5ec: 400204b8 .word 0x400204b8 800a5f0: 58025408 .word 0x58025408 800a5f4: 5802541c .word 0x5802541c 800a5f8: 58025430 .word 0x58025430 800a5fc: 58025444 .word 0x58025444 800a600: 58025458 .word 0x58025458 800a604: 5802546c .word 0x5802546c 800a608: 58025480 .word 0x58025480 800a60c: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a610: 693b ldr r3, [r7, #16] 800a612: f003 0320 and.w r3, r3, #32 800a616: 2b00 cmp r3, #0 800a618: d160 bne.n 800a6dc { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800a61a: 687b ldr r3, [r7, #4] 800a61c: 681b ldr r3, [r3, #0] 800a61e: 4a7f ldr r2, [pc, #508] @ (800a81c ) 800a620: 4293 cmp r3, r2 800a622: d04a beq.n 800a6ba 800a624: 687b ldr r3, [r7, #4] 800a626: 681b ldr r3, [r3, #0] 800a628: 4a7d ldr r2, [pc, #500] @ (800a820 ) 800a62a: 4293 cmp r3, r2 800a62c: d045 beq.n 800a6ba 800a62e: 687b ldr r3, [r7, #4] 800a630: 681b ldr r3, [r3, #0] 800a632: 4a7c ldr r2, [pc, #496] @ (800a824 ) 800a634: 4293 cmp r3, r2 800a636: d040 beq.n 800a6ba 800a638: 687b ldr r3, [r7, #4] 800a63a: 681b ldr r3, [r3, #0] 800a63c: 4a7a ldr r2, [pc, #488] @ (800a828 ) 800a63e: 4293 cmp r3, r2 800a640: d03b beq.n 800a6ba 800a642: 687b ldr r3, [r7, #4] 800a644: 681b ldr r3, [r3, #0] 800a646: 4a79 ldr r2, [pc, #484] @ (800a82c ) 800a648: 4293 cmp r3, r2 800a64a: d036 beq.n 800a6ba 800a64c: 687b ldr r3, [r7, #4] 800a64e: 681b ldr r3, [r3, #0] 800a650: 4a77 ldr r2, [pc, #476] @ (800a830 ) 800a652: 4293 cmp r3, r2 800a654: d031 beq.n 800a6ba 800a656: 687b ldr r3, [r7, #4] 800a658: 681b ldr r3, [r3, #0] 800a65a: 4a76 ldr r2, [pc, #472] @ (800a834 ) 800a65c: 4293 cmp r3, r2 800a65e: d02c beq.n 800a6ba 800a660: 687b ldr r3, [r7, #4] 800a662: 681b ldr r3, [r3, #0] 800a664: 4a74 ldr r2, [pc, #464] @ (800a838 ) 800a666: 4293 cmp r3, r2 800a668: d027 beq.n 800a6ba 800a66a: 687b ldr r3, [r7, #4] 800a66c: 681b ldr r3, [r3, #0] 800a66e: 4a73 ldr r2, [pc, #460] @ (800a83c ) 800a670: 4293 cmp r3, r2 800a672: d022 beq.n 800a6ba 800a674: 687b ldr r3, [r7, #4] 800a676: 681b ldr r3, [r3, #0] 800a678: 4a71 ldr r2, [pc, #452] @ (800a840 ) 800a67a: 4293 cmp r3, r2 800a67c: d01d beq.n 800a6ba 800a67e: 687b ldr r3, [r7, #4] 800a680: 681b ldr r3, [r3, #0] 800a682: 4a70 ldr r2, [pc, #448] @ (800a844 ) 800a684: 4293 cmp r3, r2 800a686: d018 beq.n 800a6ba 800a688: 687b ldr r3, [r7, #4] 800a68a: 681b ldr r3, [r3, #0] 800a68c: 4a6e ldr r2, [pc, #440] @ (800a848 ) 800a68e: 4293 cmp r3, r2 800a690: d013 beq.n 800a6ba 800a692: 687b ldr r3, [r7, #4] 800a694: 681b ldr r3, [r3, #0] 800a696: 4a6d ldr r2, [pc, #436] @ (800a84c ) 800a698: 4293 cmp r3, r2 800a69a: d00e beq.n 800a6ba 800a69c: 687b ldr r3, [r7, #4] 800a69e: 681b ldr r3, [r3, #0] 800a6a0: 4a6b ldr r2, [pc, #428] @ (800a850 ) 800a6a2: 4293 cmp r3, r2 800a6a4: d009 beq.n 800a6ba 800a6a6: 687b ldr r3, [r7, #4] 800a6a8: 681b ldr r3, [r3, #0] 800a6aa: 4a6a ldr r2, [pc, #424] @ (800a854 ) 800a6ac: 4293 cmp r3, r2 800a6ae: d004 beq.n 800a6ba 800a6b0: 687b ldr r3, [r7, #4] 800a6b2: 681b ldr r3, [r3, #0] 800a6b4: 4a68 ldr r2, [pc, #416] @ (800a858 ) 800a6b6: 4293 cmp r3, r2 800a6b8: d108 bne.n 800a6cc 800a6ba: 687b ldr r3, [r7, #4] 800a6bc: 681b ldr r3, [r3, #0] 800a6be: 681a ldr r2, [r3, #0] 800a6c0: 687b ldr r3, [r7, #4] 800a6c2: 681b ldr r3, [r3, #0] 800a6c4: f022 0208 bic.w r2, r2, #8 800a6c8: 601a str r2, [r3, #0] 800a6ca: e007 b.n 800a6dc 800a6cc: 687b ldr r3, [r7, #4] 800a6ce: 681b ldr r3, [r3, #0] 800a6d0: 681a ldr r2, [r3, #0] 800a6d2: 687b ldr r3, [r7, #4] 800a6d4: 681b ldr r3, [r3, #0] 800a6d6: f022 0204 bic.w r2, r2, #4 800a6da: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 800a6dc: 687b ldr r3, [r7, #4] 800a6de: 6c1b ldr r3, [r3, #64] @ 0x40 800a6e0: 2b00 cmp r3, #0 800a6e2: f000 8165 beq.w 800a9b0 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a6e6: 687b ldr r3, [r7, #4] 800a6e8: 6c1b ldr r3, [r3, #64] @ 0x40 800a6ea: 6878 ldr r0, [r7, #4] 800a6ec: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a6ee: e15f b.n 800a9b0 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 800a6f0: 687b ldr r3, [r7, #4] 800a6f2: 6ddb ldr r3, [r3, #92] @ 0x5c 800a6f4: f003 031f and.w r3, r3, #31 800a6f8: 2202 movs r2, #2 800a6fa: 409a lsls r2, r3 800a6fc: 697b ldr r3, [r7, #20] 800a6fe: 4013 ands r3, r2 800a700: 2b00 cmp r3, #0 800a702: f000 80c5 beq.w 800a890 800a706: 693b ldr r3, [r7, #16] 800a708: f003 0302 and.w r3, r3, #2 800a70c: 2b00 cmp r3, #0 800a70e: f000 80bf beq.w 800a890 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 800a712: 687b ldr r3, [r7, #4] 800a714: 6ddb ldr r3, [r3, #92] @ 0x5c 800a716: f003 031f and.w r3, r3, #31 800a71a: 2202 movs r2, #2 800a71c: 409a lsls r2, r3 800a71e: 69fb ldr r3, [r7, #28] 800a720: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a722: 693b ldr r3, [r7, #16] 800a724: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a728: 2b00 cmp r3, #0 800a72a: d018 beq.n 800a75e { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a72c: 693b ldr r3, [r7, #16] 800a72e: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a732: 2b00 cmp r3, #0 800a734: d109 bne.n 800a74a { if(hdma->XferM1CpltCallback != NULL) 800a736: 687b ldr r3, [r7, #4] 800a738: 6c5b ldr r3, [r3, #68] @ 0x44 800a73a: 2b00 cmp r3, #0 800a73c: f000 813a beq.w 800a9b4 { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 800a740: 687b ldr r3, [r7, #4] 800a742: 6c5b ldr r3, [r3, #68] @ 0x44 800a744: 6878 ldr r0, [r7, #4] 800a746: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a748: e134 b.n 800a9b4 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a74a: 687b ldr r3, [r7, #4] 800a74c: 6bdb ldr r3, [r3, #60] @ 0x3c 800a74e: 2b00 cmp r3, #0 800a750: f000 8130 beq.w 800a9b4 { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 800a754: 687b ldr r3, [r7, #4] 800a756: 6bdb ldr r3, [r3, #60] @ 0x3c 800a758: 6878 ldr r0, [r7, #4] 800a75a: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a75c: e12a b.n 800a9b4 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a75e: 693b ldr r3, [r7, #16] 800a760: f003 0320 and.w r3, r3, #32 800a764: 2b00 cmp r3, #0 800a766: f040 8089 bne.w 800a87c { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800a76a: 687b ldr r3, [r7, #4] 800a76c: 681b ldr r3, [r3, #0] 800a76e: 4a2b ldr r2, [pc, #172] @ (800a81c ) 800a770: 4293 cmp r3, r2 800a772: d04a beq.n 800a80a 800a774: 687b ldr r3, [r7, #4] 800a776: 681b ldr r3, [r3, #0] 800a778: 4a29 ldr r2, [pc, #164] @ (800a820 ) 800a77a: 4293 cmp r3, r2 800a77c: d045 beq.n 800a80a 800a77e: 687b ldr r3, [r7, #4] 800a780: 681b ldr r3, [r3, #0] 800a782: 4a28 ldr r2, [pc, #160] @ (800a824 ) 800a784: 4293 cmp r3, r2 800a786: d040 beq.n 800a80a 800a788: 687b ldr r3, [r7, #4] 800a78a: 681b ldr r3, [r3, #0] 800a78c: 4a26 ldr r2, [pc, #152] @ (800a828 ) 800a78e: 4293 cmp r3, r2 800a790: d03b beq.n 800a80a 800a792: 687b ldr r3, [r7, #4] 800a794: 681b ldr r3, [r3, #0] 800a796: 4a25 ldr r2, [pc, #148] @ (800a82c ) 800a798: 4293 cmp r3, r2 800a79a: d036 beq.n 800a80a 800a79c: 687b ldr r3, [r7, #4] 800a79e: 681b ldr r3, [r3, #0] 800a7a0: 4a23 ldr r2, [pc, #140] @ (800a830 ) 800a7a2: 4293 cmp r3, r2 800a7a4: d031 beq.n 800a80a 800a7a6: 687b ldr r3, [r7, #4] 800a7a8: 681b ldr r3, [r3, #0] 800a7aa: 4a22 ldr r2, [pc, #136] @ (800a834 ) 800a7ac: 4293 cmp r3, r2 800a7ae: d02c beq.n 800a80a 800a7b0: 687b ldr r3, [r7, #4] 800a7b2: 681b ldr r3, [r3, #0] 800a7b4: 4a20 ldr r2, [pc, #128] @ (800a838 ) 800a7b6: 4293 cmp r3, r2 800a7b8: d027 beq.n 800a80a 800a7ba: 687b ldr r3, [r7, #4] 800a7bc: 681b ldr r3, [r3, #0] 800a7be: 4a1f ldr r2, [pc, #124] @ (800a83c ) 800a7c0: 4293 cmp r3, r2 800a7c2: d022 beq.n 800a80a 800a7c4: 687b ldr r3, [r7, #4] 800a7c6: 681b ldr r3, [r3, #0] 800a7c8: 4a1d ldr r2, [pc, #116] @ (800a840 ) 800a7ca: 4293 cmp r3, r2 800a7cc: d01d beq.n 800a80a 800a7ce: 687b ldr r3, [r7, #4] 800a7d0: 681b ldr r3, [r3, #0] 800a7d2: 4a1c ldr r2, [pc, #112] @ (800a844 ) 800a7d4: 4293 cmp r3, r2 800a7d6: d018 beq.n 800a80a 800a7d8: 687b ldr r3, [r7, #4] 800a7da: 681b ldr r3, [r3, #0] 800a7dc: 4a1a ldr r2, [pc, #104] @ (800a848 ) 800a7de: 4293 cmp r3, r2 800a7e0: d013 beq.n 800a80a 800a7e2: 687b ldr r3, [r7, #4] 800a7e4: 681b ldr r3, [r3, #0] 800a7e6: 4a19 ldr r2, [pc, #100] @ (800a84c ) 800a7e8: 4293 cmp r3, r2 800a7ea: d00e beq.n 800a80a 800a7ec: 687b ldr r3, [r7, #4] 800a7ee: 681b ldr r3, [r3, #0] 800a7f0: 4a17 ldr r2, [pc, #92] @ (800a850 ) 800a7f2: 4293 cmp r3, r2 800a7f4: d009 beq.n 800a80a 800a7f6: 687b ldr r3, [r7, #4] 800a7f8: 681b ldr r3, [r3, #0] 800a7fa: 4a16 ldr r2, [pc, #88] @ (800a854 ) 800a7fc: 4293 cmp r3, r2 800a7fe: d004 beq.n 800a80a 800a800: 687b ldr r3, [r7, #4] 800a802: 681b ldr r3, [r3, #0] 800a804: 4a14 ldr r2, [pc, #80] @ (800a858 ) 800a806: 4293 cmp r3, r2 800a808: d128 bne.n 800a85c 800a80a: 687b ldr r3, [r7, #4] 800a80c: 681b ldr r3, [r3, #0] 800a80e: 681a ldr r2, [r3, #0] 800a810: 687b ldr r3, [r7, #4] 800a812: 681b ldr r3, [r3, #0] 800a814: f022 0214 bic.w r2, r2, #20 800a818: 601a str r2, [r3, #0] 800a81a: e027 b.n 800a86c 800a81c: 40020010 .word 0x40020010 800a820: 40020028 .word 0x40020028 800a824: 40020040 .word 0x40020040 800a828: 40020058 .word 0x40020058 800a82c: 40020070 .word 0x40020070 800a830: 40020088 .word 0x40020088 800a834: 400200a0 .word 0x400200a0 800a838: 400200b8 .word 0x400200b8 800a83c: 40020410 .word 0x40020410 800a840: 40020428 .word 0x40020428 800a844: 40020440 .word 0x40020440 800a848: 40020458 .word 0x40020458 800a84c: 40020470 .word 0x40020470 800a850: 40020488 .word 0x40020488 800a854: 400204a0 .word 0x400204a0 800a858: 400204b8 .word 0x400204b8 800a85c: 687b ldr r3, [r7, #4] 800a85e: 681b ldr r3, [r3, #0] 800a860: 681a ldr r2, [r3, #0] 800a862: 687b ldr r3, [r7, #4] 800a864: 681b ldr r3, [r3, #0] 800a866: f022 020a bic.w r2, r2, #10 800a86a: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a86c: 687b ldr r3, [r7, #4] 800a86e: 2201 movs r2, #1 800a870: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a874: 687b ldr r3, [r7, #4] 800a876: 2200 movs r2, #0 800a878: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a87c: 687b ldr r3, [r7, #4] 800a87e: 6bdb ldr r3, [r3, #60] @ 0x3c 800a880: 2b00 cmp r3, #0 800a882: f000 8097 beq.w 800a9b4 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a886: 687b ldr r3, [r7, #4] 800a888: 6bdb ldr r3, [r3, #60] @ 0x3c 800a88a: 6878 ldr r0, [r7, #4] 800a88c: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a88e: e091 b.n 800a9b4 } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 800a890: 687b ldr r3, [r7, #4] 800a892: 6ddb ldr r3, [r3, #92] @ 0x5c 800a894: f003 031f and.w r3, r3, #31 800a898: 2208 movs r2, #8 800a89a: 409a lsls r2, r3 800a89c: 697b ldr r3, [r7, #20] 800a89e: 4013 ands r3, r2 800a8a0: 2b00 cmp r3, #0 800a8a2: f000 8088 beq.w 800a9b6 800a8a6: 693b ldr r3, [r7, #16] 800a8a8: f003 0308 and.w r3, r3, #8 800a8ac: 2b00 cmp r3, #0 800a8ae: f000 8082 beq.w 800a9b6 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800a8b2: 687b ldr r3, [r7, #4] 800a8b4: 681b ldr r3, [r3, #0] 800a8b6: 4a41 ldr r2, [pc, #260] @ (800a9bc ) 800a8b8: 4293 cmp r3, r2 800a8ba: d04a beq.n 800a952 800a8bc: 687b ldr r3, [r7, #4] 800a8be: 681b ldr r3, [r3, #0] 800a8c0: 4a3f ldr r2, [pc, #252] @ (800a9c0 ) 800a8c2: 4293 cmp r3, r2 800a8c4: d045 beq.n 800a952 800a8c6: 687b ldr r3, [r7, #4] 800a8c8: 681b ldr r3, [r3, #0] 800a8ca: 4a3e ldr r2, [pc, #248] @ (800a9c4 ) 800a8cc: 4293 cmp r3, r2 800a8ce: d040 beq.n 800a952 800a8d0: 687b ldr r3, [r7, #4] 800a8d2: 681b ldr r3, [r3, #0] 800a8d4: 4a3c ldr r2, [pc, #240] @ (800a9c8 ) 800a8d6: 4293 cmp r3, r2 800a8d8: d03b beq.n 800a952 800a8da: 687b ldr r3, [r7, #4] 800a8dc: 681b ldr r3, [r3, #0] 800a8de: 4a3b ldr r2, [pc, #236] @ (800a9cc ) 800a8e0: 4293 cmp r3, r2 800a8e2: d036 beq.n 800a952 800a8e4: 687b ldr r3, [r7, #4] 800a8e6: 681b ldr r3, [r3, #0] 800a8e8: 4a39 ldr r2, [pc, #228] @ (800a9d0 ) 800a8ea: 4293 cmp r3, r2 800a8ec: d031 beq.n 800a952 800a8ee: 687b ldr r3, [r7, #4] 800a8f0: 681b ldr r3, [r3, #0] 800a8f2: 4a38 ldr r2, [pc, #224] @ (800a9d4 ) 800a8f4: 4293 cmp r3, r2 800a8f6: d02c beq.n 800a952 800a8f8: 687b ldr r3, [r7, #4] 800a8fa: 681b ldr r3, [r3, #0] 800a8fc: 4a36 ldr r2, [pc, #216] @ (800a9d8 ) 800a8fe: 4293 cmp r3, r2 800a900: d027 beq.n 800a952 800a902: 687b ldr r3, [r7, #4] 800a904: 681b ldr r3, [r3, #0] 800a906: 4a35 ldr r2, [pc, #212] @ (800a9dc ) 800a908: 4293 cmp r3, r2 800a90a: d022 beq.n 800a952 800a90c: 687b ldr r3, [r7, #4] 800a90e: 681b ldr r3, [r3, #0] 800a910: 4a33 ldr r2, [pc, #204] @ (800a9e0 ) 800a912: 4293 cmp r3, r2 800a914: d01d beq.n 800a952 800a916: 687b ldr r3, [r7, #4] 800a918: 681b ldr r3, [r3, #0] 800a91a: 4a32 ldr r2, [pc, #200] @ (800a9e4 ) 800a91c: 4293 cmp r3, r2 800a91e: d018 beq.n 800a952 800a920: 687b ldr r3, [r7, #4] 800a922: 681b ldr r3, [r3, #0] 800a924: 4a30 ldr r2, [pc, #192] @ (800a9e8 ) 800a926: 4293 cmp r3, r2 800a928: d013 beq.n 800a952 800a92a: 687b ldr r3, [r7, #4] 800a92c: 681b ldr r3, [r3, #0] 800a92e: 4a2f ldr r2, [pc, #188] @ (800a9ec ) 800a930: 4293 cmp r3, r2 800a932: d00e beq.n 800a952 800a934: 687b ldr r3, [r7, #4] 800a936: 681b ldr r3, [r3, #0] 800a938: 4a2d ldr r2, [pc, #180] @ (800a9f0 ) 800a93a: 4293 cmp r3, r2 800a93c: d009 beq.n 800a952 800a93e: 687b ldr r3, [r7, #4] 800a940: 681b ldr r3, [r3, #0] 800a942: 4a2c ldr r2, [pc, #176] @ (800a9f4 ) 800a944: 4293 cmp r3, r2 800a946: d004 beq.n 800a952 800a948: 687b ldr r3, [r7, #4] 800a94a: 681b ldr r3, [r3, #0] 800a94c: 4a2a ldr r2, [pc, #168] @ (800a9f8 ) 800a94e: 4293 cmp r3, r2 800a950: d108 bne.n 800a964 800a952: 687b ldr r3, [r7, #4] 800a954: 681b ldr r3, [r3, #0] 800a956: 681a ldr r2, [r3, #0] 800a958: 687b ldr r3, [r7, #4] 800a95a: 681b ldr r3, [r3, #0] 800a95c: f022 021c bic.w r2, r2, #28 800a960: 601a str r2, [r3, #0] 800a962: e007 b.n 800a974 800a964: 687b ldr r3, [r7, #4] 800a966: 681b ldr r3, [r3, #0] 800a968: 681a ldr r2, [r3, #0] 800a96a: 687b ldr r3, [r7, #4] 800a96c: 681b ldr r3, [r3, #0] 800a96e: f022 020e bic.w r2, r2, #14 800a972: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800a974: 687b ldr r3, [r7, #4] 800a976: 6ddb ldr r3, [r3, #92] @ 0x5c 800a978: f003 031f and.w r3, r3, #31 800a97c: 2201 movs r2, #1 800a97e: 409a lsls r2, r3 800a980: 69fb ldr r3, [r7, #28] 800a982: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 800a984: 687b ldr r3, [r7, #4] 800a986: 2201 movs r2, #1 800a988: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a98a: 687b ldr r3, [r7, #4] 800a98c: 2201 movs r2, #1 800a98e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a992: 687b ldr r3, [r7, #4] 800a994: 2200 movs r2, #0 800a996: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 800a99a: 687b ldr r3, [r7, #4] 800a99c: 6cdb ldr r3, [r3, #76] @ 0x4c 800a99e: 2b00 cmp r3, #0 800a9a0: d009 beq.n 800a9b6 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a9a2: 687b ldr r3, [r7, #4] 800a9a4: 6cdb ldr r3, [r3, #76] @ 0x4c 800a9a6: 6878 ldr r0, [r7, #4] 800a9a8: 4798 blx r3 800a9aa: e004 b.n 800a9b6 return; 800a9ac: bf00 nop 800a9ae: e002 b.n 800a9b6 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a9b0: bf00 nop 800a9b2: e000 b.n 800a9b6 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a9b4: bf00 nop } else { /* Nothing To Do */ } } 800a9b6: 3728 adds r7, #40 @ 0x28 800a9b8: 46bd mov sp, r7 800a9ba: bd80 pop {r7, pc} 800a9bc: 40020010 .word 0x40020010 800a9c0: 40020028 .word 0x40020028 800a9c4: 40020040 .word 0x40020040 800a9c8: 40020058 .word 0x40020058 800a9cc: 40020070 .word 0x40020070 800a9d0: 40020088 .word 0x40020088 800a9d4: 400200a0 .word 0x400200a0 800a9d8: 400200b8 .word 0x400200b8 800a9dc: 40020410 .word 0x40020410 800a9e0: 40020428 .word 0x40020428 800a9e4: 40020440 .word 0x40020440 800a9e8: 40020458 .word 0x40020458 800a9ec: 40020470 .word 0x40020470 800a9f0: 40020488 .word 0x40020488 800a9f4: 400204a0 .word 0x400204a0 800a9f8: 400204b8 .word 0x400204b8 0800a9fc : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800a9fc: b480 push {r7} 800a9fe: b087 sub sp, #28 800aa00: af00 add r7, sp, #0 800aa02: 60f8 str r0, [r7, #12] 800aa04: 60b9 str r1, [r7, #8] 800aa06: 607a str r2, [r7, #4] 800aa08: 603b str r3, [r7, #0] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800aa0a: 68fb ldr r3, [r7, #12] 800aa0c: 6d9b ldr r3, [r3, #88] @ 0x58 800aa0e: 617b str r3, [r7, #20] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800aa10: 68fb ldr r3, [r7, #12] 800aa12: 6d9b ldr r3, [r3, #88] @ 0x58 800aa14: 613b str r3, [r7, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800aa16: 68fb ldr r3, [r7, #12] 800aa18: 681b ldr r3, [r3, #0] 800aa1a: 4a7f ldr r2, [pc, #508] @ (800ac18 ) 800aa1c: 4293 cmp r3, r2 800aa1e: d072 beq.n 800ab06 800aa20: 68fb ldr r3, [r7, #12] 800aa22: 681b ldr r3, [r3, #0] 800aa24: 4a7d ldr r2, [pc, #500] @ (800ac1c ) 800aa26: 4293 cmp r3, r2 800aa28: d06d beq.n 800ab06 800aa2a: 68fb ldr r3, [r7, #12] 800aa2c: 681b ldr r3, [r3, #0] 800aa2e: 4a7c ldr r2, [pc, #496] @ (800ac20 ) 800aa30: 4293 cmp r3, r2 800aa32: d068 beq.n 800ab06 800aa34: 68fb ldr r3, [r7, #12] 800aa36: 681b ldr r3, [r3, #0] 800aa38: 4a7a ldr r2, [pc, #488] @ (800ac24 ) 800aa3a: 4293 cmp r3, r2 800aa3c: d063 beq.n 800ab06 800aa3e: 68fb ldr r3, [r7, #12] 800aa40: 681b ldr r3, [r3, #0] 800aa42: 4a79 ldr r2, [pc, #484] @ (800ac28 ) 800aa44: 4293 cmp r3, r2 800aa46: d05e beq.n 800ab06 800aa48: 68fb ldr r3, [r7, #12] 800aa4a: 681b ldr r3, [r3, #0] 800aa4c: 4a77 ldr r2, [pc, #476] @ (800ac2c ) 800aa4e: 4293 cmp r3, r2 800aa50: d059 beq.n 800ab06 800aa52: 68fb ldr r3, [r7, #12] 800aa54: 681b ldr r3, [r3, #0] 800aa56: 4a76 ldr r2, [pc, #472] @ (800ac30 ) 800aa58: 4293 cmp r3, r2 800aa5a: d054 beq.n 800ab06 800aa5c: 68fb ldr r3, [r7, #12] 800aa5e: 681b ldr r3, [r3, #0] 800aa60: 4a74 ldr r2, [pc, #464] @ (800ac34 ) 800aa62: 4293 cmp r3, r2 800aa64: d04f beq.n 800ab06 800aa66: 68fb ldr r3, [r7, #12] 800aa68: 681b ldr r3, [r3, #0] 800aa6a: 4a73 ldr r2, [pc, #460] @ (800ac38 ) 800aa6c: 4293 cmp r3, r2 800aa6e: d04a beq.n 800ab06 800aa70: 68fb ldr r3, [r7, #12] 800aa72: 681b ldr r3, [r3, #0] 800aa74: 4a71 ldr r2, [pc, #452] @ (800ac3c ) 800aa76: 4293 cmp r3, r2 800aa78: d045 beq.n 800ab06 800aa7a: 68fb ldr r3, [r7, #12] 800aa7c: 681b ldr r3, [r3, #0] 800aa7e: 4a70 ldr r2, [pc, #448] @ (800ac40 ) 800aa80: 4293 cmp r3, r2 800aa82: d040 beq.n 800ab06 800aa84: 68fb ldr r3, [r7, #12] 800aa86: 681b ldr r3, [r3, #0] 800aa88: 4a6e ldr r2, [pc, #440] @ (800ac44 ) 800aa8a: 4293 cmp r3, r2 800aa8c: d03b beq.n 800ab06 800aa8e: 68fb ldr r3, [r7, #12] 800aa90: 681b ldr r3, [r3, #0] 800aa92: 4a6d ldr r2, [pc, #436] @ (800ac48 ) 800aa94: 4293 cmp r3, r2 800aa96: d036 beq.n 800ab06 800aa98: 68fb ldr r3, [r7, #12] 800aa9a: 681b ldr r3, [r3, #0] 800aa9c: 4a6b ldr r2, [pc, #428] @ (800ac4c ) 800aa9e: 4293 cmp r3, r2 800aaa0: d031 beq.n 800ab06 800aaa2: 68fb ldr r3, [r7, #12] 800aaa4: 681b ldr r3, [r3, #0] 800aaa6: 4a6a ldr r2, [pc, #424] @ (800ac50 ) 800aaa8: 4293 cmp r3, r2 800aaaa: d02c beq.n 800ab06 800aaac: 68fb ldr r3, [r7, #12] 800aaae: 681b ldr r3, [r3, #0] 800aab0: 4a68 ldr r2, [pc, #416] @ (800ac54 ) 800aab2: 4293 cmp r3, r2 800aab4: d027 beq.n 800ab06 800aab6: 68fb ldr r3, [r7, #12] 800aab8: 681b ldr r3, [r3, #0] 800aaba: 4a67 ldr r2, [pc, #412] @ (800ac58 ) 800aabc: 4293 cmp r3, r2 800aabe: d022 beq.n 800ab06 800aac0: 68fb ldr r3, [r7, #12] 800aac2: 681b ldr r3, [r3, #0] 800aac4: 4a65 ldr r2, [pc, #404] @ (800ac5c ) 800aac6: 4293 cmp r3, r2 800aac8: d01d beq.n 800ab06 800aaca: 68fb ldr r3, [r7, #12] 800aacc: 681b ldr r3, [r3, #0] 800aace: 4a64 ldr r2, [pc, #400] @ (800ac60 ) 800aad0: 4293 cmp r3, r2 800aad2: d018 beq.n 800ab06 800aad4: 68fb ldr r3, [r7, #12] 800aad6: 681b ldr r3, [r3, #0] 800aad8: 4a62 ldr r2, [pc, #392] @ (800ac64 ) 800aada: 4293 cmp r3, r2 800aadc: d013 beq.n 800ab06 800aade: 68fb ldr r3, [r7, #12] 800aae0: 681b ldr r3, [r3, #0] 800aae2: 4a61 ldr r2, [pc, #388] @ (800ac68 ) 800aae4: 4293 cmp r3, r2 800aae6: d00e beq.n 800ab06 800aae8: 68fb ldr r3, [r7, #12] 800aaea: 681b ldr r3, [r3, #0] 800aaec: 4a5f ldr r2, [pc, #380] @ (800ac6c ) 800aaee: 4293 cmp r3, r2 800aaf0: d009 beq.n 800ab06 800aaf2: 68fb ldr r3, [r7, #12] 800aaf4: 681b ldr r3, [r3, #0] 800aaf6: 4a5e ldr r2, [pc, #376] @ (800ac70 ) 800aaf8: 4293 cmp r3, r2 800aafa: d004 beq.n 800ab06 800aafc: 68fb ldr r3, [r7, #12] 800aafe: 681b ldr r3, [r3, #0] 800ab00: 4a5c ldr r2, [pc, #368] @ (800ac74 ) 800ab02: 4293 cmp r3, r2 800ab04: d101 bne.n 800ab0a 800ab06: 2301 movs r3, #1 800ab08: e000 b.n 800ab0c 800ab0a: 2300 movs r3, #0 800ab0c: 2b00 cmp r3, #0 800ab0e: d00d beq.n 800ab2c { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800ab10: 68fb ldr r3, [r7, #12] 800ab12: 6e5b ldr r3, [r3, #100] @ 0x64 800ab14: 68fa ldr r2, [r7, #12] 800ab16: 6e92 ldr r2, [r2, #104] @ 0x68 800ab18: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800ab1a: 68fb ldr r3, [r7, #12] 800ab1c: 6edb ldr r3, [r3, #108] @ 0x6c 800ab1e: 2b00 cmp r3, #0 800ab20: d004 beq.n 800ab2c { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800ab22: 68fb ldr r3, [r7, #12] 800ab24: 6f1b ldr r3, [r3, #112] @ 0x70 800ab26: 68fa ldr r2, [r7, #12] 800ab28: 6f52 ldr r2, [r2, #116] @ 0x74 800ab2a: 605a str r2, [r3, #4] } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800ab2c: 68fb ldr r3, [r7, #12] 800ab2e: 681b ldr r3, [r3, #0] 800ab30: 4a39 ldr r2, [pc, #228] @ (800ac18 ) 800ab32: 4293 cmp r3, r2 800ab34: d04a beq.n 800abcc 800ab36: 68fb ldr r3, [r7, #12] 800ab38: 681b ldr r3, [r3, #0] 800ab3a: 4a38 ldr r2, [pc, #224] @ (800ac1c ) 800ab3c: 4293 cmp r3, r2 800ab3e: d045 beq.n 800abcc 800ab40: 68fb ldr r3, [r7, #12] 800ab42: 681b ldr r3, [r3, #0] 800ab44: 4a36 ldr r2, [pc, #216] @ (800ac20 ) 800ab46: 4293 cmp r3, r2 800ab48: d040 beq.n 800abcc 800ab4a: 68fb ldr r3, [r7, #12] 800ab4c: 681b ldr r3, [r3, #0] 800ab4e: 4a35 ldr r2, [pc, #212] @ (800ac24 ) 800ab50: 4293 cmp r3, r2 800ab52: d03b beq.n 800abcc 800ab54: 68fb ldr r3, [r7, #12] 800ab56: 681b ldr r3, [r3, #0] 800ab58: 4a33 ldr r2, [pc, #204] @ (800ac28 ) 800ab5a: 4293 cmp r3, r2 800ab5c: d036 beq.n 800abcc 800ab5e: 68fb ldr r3, [r7, #12] 800ab60: 681b ldr r3, [r3, #0] 800ab62: 4a32 ldr r2, [pc, #200] @ (800ac2c ) 800ab64: 4293 cmp r3, r2 800ab66: d031 beq.n 800abcc 800ab68: 68fb ldr r3, [r7, #12] 800ab6a: 681b ldr r3, [r3, #0] 800ab6c: 4a30 ldr r2, [pc, #192] @ (800ac30 ) 800ab6e: 4293 cmp r3, r2 800ab70: d02c beq.n 800abcc 800ab72: 68fb ldr r3, [r7, #12] 800ab74: 681b ldr r3, [r3, #0] 800ab76: 4a2f ldr r2, [pc, #188] @ (800ac34 ) 800ab78: 4293 cmp r3, r2 800ab7a: d027 beq.n 800abcc 800ab7c: 68fb ldr r3, [r7, #12] 800ab7e: 681b ldr r3, [r3, #0] 800ab80: 4a2d ldr r2, [pc, #180] @ (800ac38 ) 800ab82: 4293 cmp r3, r2 800ab84: d022 beq.n 800abcc 800ab86: 68fb ldr r3, [r7, #12] 800ab88: 681b ldr r3, [r3, #0] 800ab8a: 4a2c ldr r2, [pc, #176] @ (800ac3c ) 800ab8c: 4293 cmp r3, r2 800ab8e: d01d beq.n 800abcc 800ab90: 68fb ldr r3, [r7, #12] 800ab92: 681b ldr r3, [r3, #0] 800ab94: 4a2a ldr r2, [pc, #168] @ (800ac40 ) 800ab96: 4293 cmp r3, r2 800ab98: d018 beq.n 800abcc 800ab9a: 68fb ldr r3, [r7, #12] 800ab9c: 681b ldr r3, [r3, #0] 800ab9e: 4a29 ldr r2, [pc, #164] @ (800ac44 ) 800aba0: 4293 cmp r3, r2 800aba2: d013 beq.n 800abcc 800aba4: 68fb ldr r3, [r7, #12] 800aba6: 681b ldr r3, [r3, #0] 800aba8: 4a27 ldr r2, [pc, #156] @ (800ac48 ) 800abaa: 4293 cmp r3, r2 800abac: d00e beq.n 800abcc 800abae: 68fb ldr r3, [r7, #12] 800abb0: 681b ldr r3, [r3, #0] 800abb2: 4a26 ldr r2, [pc, #152] @ (800ac4c ) 800abb4: 4293 cmp r3, r2 800abb6: d009 beq.n 800abcc 800abb8: 68fb ldr r3, [r7, #12] 800abba: 681b ldr r3, [r3, #0] 800abbc: 4a24 ldr r2, [pc, #144] @ (800ac50 ) 800abbe: 4293 cmp r3, r2 800abc0: d004 beq.n 800abcc 800abc2: 68fb ldr r3, [r7, #12] 800abc4: 681b ldr r3, [r3, #0] 800abc6: 4a23 ldr r2, [pc, #140] @ (800ac54 ) 800abc8: 4293 cmp r3, r2 800abca: d101 bne.n 800abd0 800abcc: 2301 movs r3, #1 800abce: e000 b.n 800abd2 800abd0: 2300 movs r3, #0 800abd2: 2b00 cmp r3, #0 800abd4: d059 beq.n 800ac8a { /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800abd6: 68fb ldr r3, [r7, #12] 800abd8: 6ddb ldr r3, [r3, #92] @ 0x5c 800abda: f003 031f and.w r3, r3, #31 800abde: 223f movs r2, #63 @ 0x3f 800abe0: 409a lsls r2, r3 800abe2: 697b ldr r3, [r7, #20] 800abe4: 609a str r2, [r3, #8] /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 800abe6: 68fb ldr r3, [r7, #12] 800abe8: 681b ldr r3, [r3, #0] 800abea: 681a ldr r2, [r3, #0] 800abec: 68fb ldr r3, [r7, #12] 800abee: 681b ldr r3, [r3, #0] 800abf0: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800abf4: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 800abf6: 68fb ldr r3, [r7, #12] 800abf8: 681b ldr r3, [r3, #0] 800abfa: 683a ldr r2, [r7, #0] 800abfc: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800abfe: 68fb ldr r3, [r7, #12] 800ac00: 689b ldr r3, [r3, #8] 800ac02: 2b40 cmp r3, #64 @ 0x40 800ac04: d138 bne.n 800ac78 { /* Configure DMA Stream destination address */ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800ac06: 68fb ldr r3, [r7, #12] 800ac08: 681b ldr r3, [r3, #0] 800ac0a: 687a ldr r2, [r7, #4] 800ac0c: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 800ac0e: 68fb ldr r3, [r7, #12] 800ac10: 681b ldr r3, [r3, #0] 800ac12: 68ba ldr r2, [r7, #8] 800ac14: 60da str r2, [r3, #12] } else { /* Nothing To Do */ } } 800ac16: e086 b.n 800ad26 800ac18: 40020010 .word 0x40020010 800ac1c: 40020028 .word 0x40020028 800ac20: 40020040 .word 0x40020040 800ac24: 40020058 .word 0x40020058 800ac28: 40020070 .word 0x40020070 800ac2c: 40020088 .word 0x40020088 800ac30: 400200a0 .word 0x400200a0 800ac34: 400200b8 .word 0x400200b8 800ac38: 40020410 .word 0x40020410 800ac3c: 40020428 .word 0x40020428 800ac40: 40020440 .word 0x40020440 800ac44: 40020458 .word 0x40020458 800ac48: 40020470 .word 0x40020470 800ac4c: 40020488 .word 0x40020488 800ac50: 400204a0 .word 0x400204a0 800ac54: 400204b8 .word 0x400204b8 800ac58: 58025408 .word 0x58025408 800ac5c: 5802541c .word 0x5802541c 800ac60: 58025430 .word 0x58025430 800ac64: 58025444 .word 0x58025444 800ac68: 58025458 .word 0x58025458 800ac6c: 5802546c .word 0x5802546c 800ac70: 58025480 .word 0x58025480 800ac74: 58025494 .word 0x58025494 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 800ac78: 68fb ldr r3, [r7, #12] 800ac7a: 681b ldr r3, [r3, #0] 800ac7c: 68ba ldr r2, [r7, #8] 800ac7e: 609a str r2, [r3, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 800ac80: 68fb ldr r3, [r7, #12] 800ac82: 681b ldr r3, [r3, #0] 800ac84: 687a ldr r2, [r7, #4] 800ac86: 60da str r2, [r3, #12] } 800ac88: e04d b.n 800ad26 else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800ac8a: 68fb ldr r3, [r7, #12] 800ac8c: 681b ldr r3, [r3, #0] 800ac8e: 4a29 ldr r2, [pc, #164] @ (800ad34 ) 800ac90: 4293 cmp r3, r2 800ac92: d022 beq.n 800acda 800ac94: 68fb ldr r3, [r7, #12] 800ac96: 681b ldr r3, [r3, #0] 800ac98: 4a27 ldr r2, [pc, #156] @ (800ad38 ) 800ac9a: 4293 cmp r3, r2 800ac9c: d01d beq.n 800acda 800ac9e: 68fb ldr r3, [r7, #12] 800aca0: 681b ldr r3, [r3, #0] 800aca2: 4a26 ldr r2, [pc, #152] @ (800ad3c ) 800aca4: 4293 cmp r3, r2 800aca6: d018 beq.n 800acda 800aca8: 68fb ldr r3, [r7, #12] 800acaa: 681b ldr r3, [r3, #0] 800acac: 4a24 ldr r2, [pc, #144] @ (800ad40 ) 800acae: 4293 cmp r3, r2 800acb0: d013 beq.n 800acda 800acb2: 68fb ldr r3, [r7, #12] 800acb4: 681b ldr r3, [r3, #0] 800acb6: 4a23 ldr r2, [pc, #140] @ (800ad44 ) 800acb8: 4293 cmp r3, r2 800acba: d00e beq.n 800acda 800acbc: 68fb ldr r3, [r7, #12] 800acbe: 681b ldr r3, [r3, #0] 800acc0: 4a21 ldr r2, [pc, #132] @ (800ad48 ) 800acc2: 4293 cmp r3, r2 800acc4: d009 beq.n 800acda 800acc6: 68fb ldr r3, [r7, #12] 800acc8: 681b ldr r3, [r3, #0] 800acca: 4a20 ldr r2, [pc, #128] @ (800ad4c ) 800accc: 4293 cmp r3, r2 800acce: d004 beq.n 800acda 800acd0: 68fb ldr r3, [r7, #12] 800acd2: 681b ldr r3, [r3, #0] 800acd4: 4a1e ldr r2, [pc, #120] @ (800ad50 ) 800acd6: 4293 cmp r3, r2 800acd8: d101 bne.n 800acde 800acda: 2301 movs r3, #1 800acdc: e000 b.n 800ace0 800acde: 2300 movs r3, #0 800ace0: 2b00 cmp r3, #0 800ace2: d020 beq.n 800ad26 regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800ace4: 68fb ldr r3, [r7, #12] 800ace6: 6ddb ldr r3, [r3, #92] @ 0x5c 800ace8: f003 031f and.w r3, r3, #31 800acec: 2201 movs r2, #1 800acee: 409a lsls r2, r3 800acf0: 693b ldr r3, [r7, #16] 800acf2: 605a str r2, [r3, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 800acf4: 68fb ldr r3, [r7, #12] 800acf6: 681b ldr r3, [r3, #0] 800acf8: 683a ldr r2, [r7, #0] 800acfa: 605a str r2, [r3, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800acfc: 68fb ldr r3, [r7, #12] 800acfe: 689b ldr r3, [r3, #8] 800ad00: 2b40 cmp r3, #64 @ 0x40 800ad02: d108 bne.n 800ad16 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 800ad04: 68fb ldr r3, [r7, #12] 800ad06: 681b ldr r3, [r3, #0] 800ad08: 687a ldr r2, [r7, #4] 800ad0a: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 800ad0c: 68fb ldr r3, [r7, #12] 800ad0e: 681b ldr r3, [r3, #0] 800ad10: 68ba ldr r2, [r7, #8] 800ad12: 60da str r2, [r3, #12] } 800ad14: e007 b.n 800ad26 ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 800ad16: 68fb ldr r3, [r7, #12] 800ad18: 681b ldr r3, [r3, #0] 800ad1a: 68ba ldr r2, [r7, #8] 800ad1c: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 800ad1e: 68fb ldr r3, [r7, #12] 800ad20: 681b ldr r3, [r3, #0] 800ad22: 687a ldr r2, [r7, #4] 800ad24: 60da str r2, [r3, #12] } 800ad26: bf00 nop 800ad28: 371c adds r7, #28 800ad2a: 46bd mov sp, r7 800ad2c: f85d 7b04 ldr.w r7, [sp], #4 800ad30: 4770 bx lr 800ad32: bf00 nop 800ad34: 58025408 .word 0x58025408 800ad38: 5802541c .word 0x5802541c 800ad3c: 58025430 .word 0x58025430 800ad40: 58025444 .word 0x58025444 800ad44: 58025458 .word 0x58025458 800ad48: 5802546c .word 0x5802546c 800ad4c: 58025480 .word 0x58025480 800ad50: 58025494 .word 0x58025494 0800ad54 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800ad54: b480 push {r7} 800ad56: b085 sub sp, #20 800ad58: af00 add r7, sp, #0 800ad5a: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800ad5c: 687b ldr r3, [r7, #4] 800ad5e: 681b ldr r3, [r3, #0] 800ad60: 4a42 ldr r2, [pc, #264] @ (800ae6c ) 800ad62: 4293 cmp r3, r2 800ad64: d04a beq.n 800adfc 800ad66: 687b ldr r3, [r7, #4] 800ad68: 681b ldr r3, [r3, #0] 800ad6a: 4a41 ldr r2, [pc, #260] @ (800ae70 ) 800ad6c: 4293 cmp r3, r2 800ad6e: d045 beq.n 800adfc 800ad70: 687b ldr r3, [r7, #4] 800ad72: 681b ldr r3, [r3, #0] 800ad74: 4a3f ldr r2, [pc, #252] @ (800ae74 ) 800ad76: 4293 cmp r3, r2 800ad78: d040 beq.n 800adfc 800ad7a: 687b ldr r3, [r7, #4] 800ad7c: 681b ldr r3, [r3, #0] 800ad7e: 4a3e ldr r2, [pc, #248] @ (800ae78 ) 800ad80: 4293 cmp r3, r2 800ad82: d03b beq.n 800adfc 800ad84: 687b ldr r3, [r7, #4] 800ad86: 681b ldr r3, [r3, #0] 800ad88: 4a3c ldr r2, [pc, #240] @ (800ae7c ) 800ad8a: 4293 cmp r3, r2 800ad8c: d036 beq.n 800adfc 800ad8e: 687b ldr r3, [r7, #4] 800ad90: 681b ldr r3, [r3, #0] 800ad92: 4a3b ldr r2, [pc, #236] @ (800ae80 ) 800ad94: 4293 cmp r3, r2 800ad96: d031 beq.n 800adfc 800ad98: 687b ldr r3, [r7, #4] 800ad9a: 681b ldr r3, [r3, #0] 800ad9c: 4a39 ldr r2, [pc, #228] @ (800ae84 ) 800ad9e: 4293 cmp r3, r2 800ada0: d02c beq.n 800adfc 800ada2: 687b ldr r3, [r7, #4] 800ada4: 681b ldr r3, [r3, #0] 800ada6: 4a38 ldr r2, [pc, #224] @ (800ae88 ) 800ada8: 4293 cmp r3, r2 800adaa: d027 beq.n 800adfc 800adac: 687b ldr r3, [r7, #4] 800adae: 681b ldr r3, [r3, #0] 800adb0: 4a36 ldr r2, [pc, #216] @ (800ae8c ) 800adb2: 4293 cmp r3, r2 800adb4: d022 beq.n 800adfc 800adb6: 687b ldr r3, [r7, #4] 800adb8: 681b ldr r3, [r3, #0] 800adba: 4a35 ldr r2, [pc, #212] @ (800ae90 ) 800adbc: 4293 cmp r3, r2 800adbe: d01d beq.n 800adfc 800adc0: 687b ldr r3, [r7, #4] 800adc2: 681b ldr r3, [r3, #0] 800adc4: 4a33 ldr r2, [pc, #204] @ (800ae94 ) 800adc6: 4293 cmp r3, r2 800adc8: d018 beq.n 800adfc 800adca: 687b ldr r3, [r7, #4] 800adcc: 681b ldr r3, [r3, #0] 800adce: 4a32 ldr r2, [pc, #200] @ (800ae98 ) 800add0: 4293 cmp r3, r2 800add2: d013 beq.n 800adfc 800add4: 687b ldr r3, [r7, #4] 800add6: 681b ldr r3, [r3, #0] 800add8: 4a30 ldr r2, [pc, #192] @ (800ae9c ) 800adda: 4293 cmp r3, r2 800addc: d00e beq.n 800adfc 800adde: 687b ldr r3, [r7, #4] 800ade0: 681b ldr r3, [r3, #0] 800ade2: 4a2f ldr r2, [pc, #188] @ (800aea0 ) 800ade4: 4293 cmp r3, r2 800ade6: d009 beq.n 800adfc 800ade8: 687b ldr r3, [r7, #4] 800adea: 681b ldr r3, [r3, #0] 800adec: 4a2d ldr r2, [pc, #180] @ (800aea4 ) 800adee: 4293 cmp r3, r2 800adf0: d004 beq.n 800adfc 800adf2: 687b ldr r3, [r7, #4] 800adf4: 681b ldr r3, [r3, #0] 800adf6: 4a2c ldr r2, [pc, #176] @ (800aea8 ) 800adf8: 4293 cmp r3, r2 800adfa: d101 bne.n 800ae00 800adfc: 2301 movs r3, #1 800adfe: e000 b.n 800ae02 800ae00: 2300 movs r3, #0 800ae02: 2b00 cmp r3, #0 800ae04: d024 beq.n 800ae50 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800ae06: 687b ldr r3, [r7, #4] 800ae08: 681b ldr r3, [r3, #0] 800ae0a: b2db uxtb r3, r3 800ae0c: 3b10 subs r3, #16 800ae0e: 4a27 ldr r2, [pc, #156] @ (800aeac ) 800ae10: fba2 2303 umull r2, r3, r2, r3 800ae14: 091b lsrs r3, r3, #4 800ae16: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 800ae18: 68fb ldr r3, [r7, #12] 800ae1a: f003 0307 and.w r3, r3, #7 800ae1e: 4a24 ldr r2, [pc, #144] @ (800aeb0 ) 800ae20: 5cd3 ldrb r3, [r2, r3] 800ae22: 461a mov r2, r3 800ae24: 687b ldr r3, [r7, #4] 800ae26: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 800ae28: 68fb ldr r3, [r7, #12] 800ae2a: 2b03 cmp r3, #3 800ae2c: d908 bls.n 800ae40 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 800ae2e: 687b ldr r3, [r7, #4] 800ae30: 681b ldr r3, [r3, #0] 800ae32: 461a mov r2, r3 800ae34: 4b1f ldr r3, [pc, #124] @ (800aeb4 ) 800ae36: 4013 ands r3, r2 800ae38: 1d1a adds r2, r3, #4 800ae3a: 687b ldr r3, [r7, #4] 800ae3c: 659a str r2, [r3, #88] @ 0x58 800ae3e: e00d b.n 800ae5c } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 800ae40: 687b ldr r3, [r7, #4] 800ae42: 681b ldr r3, [r3, #0] 800ae44: 461a mov r2, r3 800ae46: 4b1b ldr r3, [pc, #108] @ (800aeb4 ) 800ae48: 4013 ands r3, r2 800ae4a: 687a ldr r2, [r7, #4] 800ae4c: 6593 str r3, [r2, #88] @ 0x58 800ae4e: e005 b.n 800ae5c } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 800ae50: 687b ldr r3, [r7, #4] 800ae52: 681b ldr r3, [r3, #0] 800ae54: f023 02ff bic.w r2, r3, #255 @ 0xff 800ae58: 687b ldr r3, [r7, #4] 800ae5a: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 800ae5c: 687b ldr r3, [r7, #4] 800ae5e: 6d9b ldr r3, [r3, #88] @ 0x58 } 800ae60: 4618 mov r0, r3 800ae62: 3714 adds r7, #20 800ae64: 46bd mov sp, r7 800ae66: f85d 7b04 ldr.w r7, [sp], #4 800ae6a: 4770 bx lr 800ae6c: 40020010 .word 0x40020010 800ae70: 40020028 .word 0x40020028 800ae74: 40020040 .word 0x40020040 800ae78: 40020058 .word 0x40020058 800ae7c: 40020070 .word 0x40020070 800ae80: 40020088 .word 0x40020088 800ae84: 400200a0 .word 0x400200a0 800ae88: 400200b8 .word 0x400200b8 800ae8c: 40020410 .word 0x40020410 800ae90: 40020428 .word 0x40020428 800ae94: 40020440 .word 0x40020440 800ae98: 40020458 .word 0x40020458 800ae9c: 40020470 .word 0x40020470 800aea0: 40020488 .word 0x40020488 800aea4: 400204a0 .word 0x400204a0 800aea8: 400204b8 .word 0x400204b8 800aeac: aaaaaaab .word 0xaaaaaaab 800aeb0: 0801870c .word 0x0801870c 800aeb4: fffffc00 .word 0xfffffc00 0800aeb8 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 800aeb8: b480 push {r7} 800aeba: b085 sub sp, #20 800aebc: af00 add r7, sp, #0 800aebe: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800aec0: 2300 movs r3, #0 800aec2: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800aec4: 687b ldr r3, [r7, #4] 800aec6: 699b ldr r3, [r3, #24] 800aec8: 2b00 cmp r3, #0 800aeca: d120 bne.n 800af0e { switch (hdma->Init.FIFOThreshold) 800aecc: 687b ldr r3, [r7, #4] 800aece: 6a9b ldr r3, [r3, #40] @ 0x28 800aed0: 2b03 cmp r3, #3 800aed2: d858 bhi.n 800af86 800aed4: a201 add r2, pc, #4 @ (adr r2, 800aedc ) 800aed6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800aeda: bf00 nop 800aedc: 0800aeed .word 0x0800aeed 800aee0: 0800aeff .word 0x0800aeff 800aee4: 0800aeed .word 0x0800aeed 800aee8: 0800af87 .word 0x0800af87 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800aeec: 687b ldr r3, [r7, #4] 800aeee: 6adb ldr r3, [r3, #44] @ 0x2c 800aef0: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800aef4: 2b00 cmp r3, #0 800aef6: d048 beq.n 800af8a { status = HAL_ERROR; 800aef8: 2301 movs r3, #1 800aefa: 73fb strb r3, [r7, #15] } break; 800aefc: e045 b.n 800af8a case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800aefe: 687b ldr r3, [r7, #4] 800af00: 6adb ldr r3, [r3, #44] @ 0x2c 800af02: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800af06: d142 bne.n 800af8e { status = HAL_ERROR; 800af08: 2301 movs r3, #1 800af0a: 73fb strb r3, [r7, #15] } break; 800af0c: e03f b.n 800af8e break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800af0e: 687b ldr r3, [r7, #4] 800af10: 699b ldr r3, [r3, #24] 800af12: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800af16: d123 bne.n 800af60 { switch (hdma->Init.FIFOThreshold) 800af18: 687b ldr r3, [r7, #4] 800af1a: 6a9b ldr r3, [r3, #40] @ 0x28 800af1c: 2b03 cmp r3, #3 800af1e: d838 bhi.n 800af92 800af20: a201 add r2, pc, #4 @ (adr r2, 800af28 ) 800af22: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800af26: bf00 nop 800af28: 0800af39 .word 0x0800af39 800af2c: 0800af3f .word 0x0800af3f 800af30: 0800af39 .word 0x0800af39 800af34: 0800af51 .word 0x0800af51 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800af38: 2301 movs r3, #1 800af3a: 73fb strb r3, [r7, #15] break; 800af3c: e030 b.n 800afa0 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800af3e: 687b ldr r3, [r7, #4] 800af40: 6adb ldr r3, [r3, #44] @ 0x2c 800af42: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800af46: 2b00 cmp r3, #0 800af48: d025 beq.n 800af96 { status = HAL_ERROR; 800af4a: 2301 movs r3, #1 800af4c: 73fb strb r3, [r7, #15] } break; 800af4e: e022 b.n 800af96 case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800af50: 687b ldr r3, [r7, #4] 800af52: 6adb ldr r3, [r3, #44] @ 0x2c 800af54: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800af58: d11f bne.n 800af9a { status = HAL_ERROR; 800af5a: 2301 movs r3, #1 800af5c: 73fb strb r3, [r7, #15] } break; 800af5e: e01c b.n 800af9a } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 800af60: 687b ldr r3, [r7, #4] 800af62: 6a9b ldr r3, [r3, #40] @ 0x28 800af64: 2b02 cmp r3, #2 800af66: d902 bls.n 800af6e 800af68: 2b03 cmp r3, #3 800af6a: d003 beq.n 800af74 status = HAL_ERROR; } break; default: break; 800af6c: e018 b.n 800afa0 status = HAL_ERROR; 800af6e: 2301 movs r3, #1 800af70: 73fb strb r3, [r7, #15] break; 800af72: e015 b.n 800afa0 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800af74: 687b ldr r3, [r7, #4] 800af76: 6adb ldr r3, [r3, #44] @ 0x2c 800af78: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800af7c: 2b00 cmp r3, #0 800af7e: d00e beq.n 800af9e status = HAL_ERROR; 800af80: 2301 movs r3, #1 800af82: 73fb strb r3, [r7, #15] break; 800af84: e00b b.n 800af9e break; 800af86: bf00 nop 800af88: e00a b.n 800afa0 break; 800af8a: bf00 nop 800af8c: e008 b.n 800afa0 break; 800af8e: bf00 nop 800af90: e006 b.n 800afa0 break; 800af92: bf00 nop 800af94: e004 b.n 800afa0 break; 800af96: bf00 nop 800af98: e002 b.n 800afa0 break; 800af9a: bf00 nop 800af9c: e000 b.n 800afa0 break; 800af9e: bf00 nop } } return status; 800afa0: 7bfb ldrb r3, [r7, #15] } 800afa2: 4618 mov r0, r3 800afa4: 3714 adds r7, #20 800afa6: 46bd mov sp, r7 800afa8: f85d 7b04 ldr.w r7, [sp], #4 800afac: 4770 bx lr 800afae: bf00 nop 0800afb0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800afb0: b480 push {r7} 800afb2: b085 sub sp, #20 800afb4: af00 add r7, sp, #0 800afb6: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 800afb8: 687b ldr r3, [r7, #4] 800afba: 681b ldr r3, [r3, #0] 800afbc: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800afbe: 687b ldr r3, [r7, #4] 800afc0: 681b ldr r3, [r3, #0] 800afc2: 4a38 ldr r2, [pc, #224] @ (800b0a4 ) 800afc4: 4293 cmp r3, r2 800afc6: d022 beq.n 800b00e 800afc8: 687b ldr r3, [r7, #4] 800afca: 681b ldr r3, [r3, #0] 800afcc: 4a36 ldr r2, [pc, #216] @ (800b0a8 ) 800afce: 4293 cmp r3, r2 800afd0: d01d beq.n 800b00e 800afd2: 687b ldr r3, [r7, #4] 800afd4: 681b ldr r3, [r3, #0] 800afd6: 4a35 ldr r2, [pc, #212] @ (800b0ac ) 800afd8: 4293 cmp r3, r2 800afda: d018 beq.n 800b00e 800afdc: 687b ldr r3, [r7, #4] 800afde: 681b ldr r3, [r3, #0] 800afe0: 4a33 ldr r2, [pc, #204] @ (800b0b0 ) 800afe2: 4293 cmp r3, r2 800afe4: d013 beq.n 800b00e 800afe6: 687b ldr r3, [r7, #4] 800afe8: 681b ldr r3, [r3, #0] 800afea: 4a32 ldr r2, [pc, #200] @ (800b0b4 ) 800afec: 4293 cmp r3, r2 800afee: d00e beq.n 800b00e 800aff0: 687b ldr r3, [r7, #4] 800aff2: 681b ldr r3, [r3, #0] 800aff4: 4a30 ldr r2, [pc, #192] @ (800b0b8 ) 800aff6: 4293 cmp r3, r2 800aff8: d009 beq.n 800b00e 800affa: 687b ldr r3, [r7, #4] 800affc: 681b ldr r3, [r3, #0] 800affe: 4a2f ldr r2, [pc, #188] @ (800b0bc ) 800b000: 4293 cmp r3, r2 800b002: d004 beq.n 800b00e 800b004: 687b ldr r3, [r7, #4] 800b006: 681b ldr r3, [r3, #0] 800b008: 4a2d ldr r2, [pc, #180] @ (800b0c0 ) 800b00a: 4293 cmp r3, r2 800b00c: d101 bne.n 800b012 800b00e: 2301 movs r3, #1 800b010: e000 b.n 800b014 800b012: 2300 movs r3, #0 800b014: 2b00 cmp r3, #0 800b016: d01a beq.n 800b04e { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 800b018: 687b ldr r3, [r7, #4] 800b01a: 681b ldr r3, [r3, #0] 800b01c: b2db uxtb r3, r3 800b01e: 3b08 subs r3, #8 800b020: 4a28 ldr r2, [pc, #160] @ (800b0c4 ) 800b022: fba2 2303 umull r2, r3, r2, r3 800b026: 091b lsrs r3, r3, #4 800b028: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 800b02a: 68fa ldr r2, [r7, #12] 800b02c: 4b26 ldr r3, [pc, #152] @ (800b0c8 ) 800b02e: 4413 add r3, r2 800b030: 009b lsls r3, r3, #2 800b032: 461a mov r2, r3 800b034: 687b ldr r3, [r7, #4] 800b036: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800b038: 687b ldr r3, [r7, #4] 800b03a: 4a24 ldr r2, [pc, #144] @ (800b0cc ) 800b03c: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800b03e: 68fb ldr r3, [r7, #12] 800b040: f003 031f and.w r3, r3, #31 800b044: 2201 movs r2, #1 800b046: 409a lsls r2, r3 800b048: 687b ldr r3, [r7, #4] 800b04a: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 800b04c: e024 b.n 800b098 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800b04e: 687b ldr r3, [r7, #4] 800b050: 681b ldr r3, [r3, #0] 800b052: b2db uxtb r3, r3 800b054: 3b10 subs r3, #16 800b056: 4a1e ldr r2, [pc, #120] @ (800b0d0 ) 800b058: fba2 2303 umull r2, r3, r2, r3 800b05c: 091b lsrs r3, r3, #4 800b05e: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800b060: 68bb ldr r3, [r7, #8] 800b062: 4a1c ldr r2, [pc, #112] @ (800b0d4 ) 800b064: 4293 cmp r3, r2 800b066: d806 bhi.n 800b076 800b068: 68bb ldr r3, [r7, #8] 800b06a: 4a1b ldr r2, [pc, #108] @ (800b0d8 ) 800b06c: 4293 cmp r3, r2 800b06e: d902 bls.n 800b076 stream_number += 8U; 800b070: 68fb ldr r3, [r7, #12] 800b072: 3308 adds r3, #8 800b074: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800b076: 68fa ldr r2, [r7, #12] 800b078: 4b18 ldr r3, [pc, #96] @ (800b0dc ) 800b07a: 4413 add r3, r2 800b07c: 009b lsls r3, r3, #2 800b07e: 461a mov r2, r3 800b080: 687b ldr r3, [r7, #4] 800b082: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800b084: 687b ldr r3, [r7, #4] 800b086: 4a16 ldr r2, [pc, #88] @ (800b0e0 ) 800b088: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800b08a: 68fb ldr r3, [r7, #12] 800b08c: f003 031f and.w r3, r3, #31 800b090: 2201 movs r2, #1 800b092: 409a lsls r2, r3 800b094: 687b ldr r3, [r7, #4] 800b096: 669a str r2, [r3, #104] @ 0x68 } 800b098: bf00 nop 800b09a: 3714 adds r7, #20 800b09c: 46bd mov sp, r7 800b09e: f85d 7b04 ldr.w r7, [sp], #4 800b0a2: 4770 bx lr 800b0a4: 58025408 .word 0x58025408 800b0a8: 5802541c .word 0x5802541c 800b0ac: 58025430 .word 0x58025430 800b0b0: 58025444 .word 0x58025444 800b0b4: 58025458 .word 0x58025458 800b0b8: 5802546c .word 0x5802546c 800b0bc: 58025480 .word 0x58025480 800b0c0: 58025494 .word 0x58025494 800b0c4: cccccccd .word 0xcccccccd 800b0c8: 16009600 .word 0x16009600 800b0cc: 58025880 .word 0x58025880 800b0d0: aaaaaaab .word 0xaaaaaaab 800b0d4: 400204b8 .word 0x400204b8 800b0d8: 4002040f .word 0x4002040f 800b0dc: 10008200 .word 0x10008200 800b0e0: 40020880 .word 0x40020880 0800b0e4 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 800b0e4: b480 push {r7} 800b0e6: b085 sub sp, #20 800b0e8: af00 add r7, sp, #0 800b0ea: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 800b0ec: 687b ldr r3, [r7, #4] 800b0ee: 685b ldr r3, [r3, #4] 800b0f0: b2db uxtb r3, r3 800b0f2: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 800b0f4: 68fb ldr r3, [r7, #12] 800b0f6: 2b00 cmp r3, #0 800b0f8: d04a beq.n 800b190 800b0fa: 68fb ldr r3, [r7, #12] 800b0fc: 2b08 cmp r3, #8 800b0fe: d847 bhi.n 800b190 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800b100: 687b ldr r3, [r7, #4] 800b102: 681b ldr r3, [r3, #0] 800b104: 4a25 ldr r2, [pc, #148] @ (800b19c ) 800b106: 4293 cmp r3, r2 800b108: d022 beq.n 800b150 800b10a: 687b ldr r3, [r7, #4] 800b10c: 681b ldr r3, [r3, #0] 800b10e: 4a24 ldr r2, [pc, #144] @ (800b1a0 ) 800b110: 4293 cmp r3, r2 800b112: d01d beq.n 800b150 800b114: 687b ldr r3, [r7, #4] 800b116: 681b ldr r3, [r3, #0] 800b118: 4a22 ldr r2, [pc, #136] @ (800b1a4 ) 800b11a: 4293 cmp r3, r2 800b11c: d018 beq.n 800b150 800b11e: 687b ldr r3, [r7, #4] 800b120: 681b ldr r3, [r3, #0] 800b122: 4a21 ldr r2, [pc, #132] @ (800b1a8 ) 800b124: 4293 cmp r3, r2 800b126: d013 beq.n 800b150 800b128: 687b ldr r3, [r7, #4] 800b12a: 681b ldr r3, [r3, #0] 800b12c: 4a1f ldr r2, [pc, #124] @ (800b1ac ) 800b12e: 4293 cmp r3, r2 800b130: d00e beq.n 800b150 800b132: 687b ldr r3, [r7, #4] 800b134: 681b ldr r3, [r3, #0] 800b136: 4a1e ldr r2, [pc, #120] @ (800b1b0 ) 800b138: 4293 cmp r3, r2 800b13a: d009 beq.n 800b150 800b13c: 687b ldr r3, [r7, #4] 800b13e: 681b ldr r3, [r3, #0] 800b140: 4a1c ldr r2, [pc, #112] @ (800b1b4 ) 800b142: 4293 cmp r3, r2 800b144: d004 beq.n 800b150 800b146: 687b ldr r3, [r7, #4] 800b148: 681b ldr r3, [r3, #0] 800b14a: 4a1b ldr r2, [pc, #108] @ (800b1b8 ) 800b14c: 4293 cmp r3, r2 800b14e: d101 bne.n 800b154 800b150: 2301 movs r3, #1 800b152: e000 b.n 800b156 800b154: 2300 movs r3, #0 800b156: 2b00 cmp r3, #0 800b158: d00a beq.n 800b170 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 800b15a: 68fa ldr r2, [r7, #12] 800b15c: 4b17 ldr r3, [pc, #92] @ (800b1bc ) 800b15e: 4413 add r3, r2 800b160: 009b lsls r3, r3, #2 800b162: 461a mov r2, r3 800b164: 687b ldr r3, [r7, #4] 800b166: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 800b168: 687b ldr r3, [r7, #4] 800b16a: 4a15 ldr r2, [pc, #84] @ (800b1c0 ) 800b16c: 671a str r2, [r3, #112] @ 0x70 800b16e: e009 b.n 800b184 } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800b170: 68fa ldr r2, [r7, #12] 800b172: 4b14 ldr r3, [pc, #80] @ (800b1c4 ) 800b174: 4413 add r3, r2 800b176: 009b lsls r3, r3, #2 800b178: 461a mov r2, r3 800b17a: 687b ldr r3, [r7, #4] 800b17c: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800b17e: 687b ldr r3, [r7, #4] 800b180: 4a11 ldr r2, [pc, #68] @ (800b1c8 ) 800b182: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 800b184: 68fb ldr r3, [r7, #12] 800b186: 3b01 subs r3, #1 800b188: 2201 movs r2, #1 800b18a: 409a lsls r2, r3 800b18c: 687b ldr r3, [r7, #4] 800b18e: 675a str r2, [r3, #116] @ 0x74 } } 800b190: bf00 nop 800b192: 3714 adds r7, #20 800b194: 46bd mov sp, r7 800b196: f85d 7b04 ldr.w r7, [sp], #4 800b19a: 4770 bx lr 800b19c: 58025408 .word 0x58025408 800b1a0: 5802541c .word 0x5802541c 800b1a4: 58025430 .word 0x58025430 800b1a8: 58025444 .word 0x58025444 800b1ac: 58025458 .word 0x58025458 800b1b0: 5802546c .word 0x5802546c 800b1b4: 58025480 .word 0x58025480 800b1b8: 58025494 .word 0x58025494 800b1bc: 1600963f .word 0x1600963f 800b1c0: 58025940 .word 0x58025940 800b1c4: 1000823f .word 0x1000823f 800b1c8: 40020940 .word 0x40020940 0800b1cc : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800b1cc: b480 push {r7} 800b1ce: b089 sub sp, #36 @ 0x24 800b1d0: af00 add r7, sp, #0 800b1d2: 6078 str r0, [r7, #4] 800b1d4: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 800b1d6: 2300 movs r3, #0 800b1d8: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 800b1da: 4b89 ldr r3, [pc, #548] @ (800b400 ) 800b1dc: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 800b1de: e194 b.n 800b50a { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 800b1e0: 683b ldr r3, [r7, #0] 800b1e2: 681a ldr r2, [r3, #0] 800b1e4: 2101 movs r1, #1 800b1e6: 69fb ldr r3, [r7, #28] 800b1e8: fa01 f303 lsl.w r3, r1, r3 800b1ec: 4013 ands r3, r2 800b1ee: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 800b1f0: 693b ldr r3, [r7, #16] 800b1f2: 2b00 cmp r3, #0 800b1f4: f000 8186 beq.w 800b504 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800b1f8: 683b ldr r3, [r7, #0] 800b1fa: 685b ldr r3, [r3, #4] 800b1fc: f003 0303 and.w r3, r3, #3 800b200: 2b01 cmp r3, #1 800b202: d005 beq.n 800b210 800b204: 683b ldr r3, [r7, #0] 800b206: 685b ldr r3, [r3, #4] 800b208: f003 0303 and.w r3, r3, #3 800b20c: 2b02 cmp r3, #2 800b20e: d130 bne.n 800b272 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800b210: 687b ldr r3, [r7, #4] 800b212: 689b ldr r3, [r3, #8] 800b214: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800b216: 69fb ldr r3, [r7, #28] 800b218: 005b lsls r3, r3, #1 800b21a: 2203 movs r2, #3 800b21c: fa02 f303 lsl.w r3, r2, r3 800b220: 43db mvns r3, r3 800b222: 69ba ldr r2, [r7, #24] 800b224: 4013 ands r3, r2 800b226: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800b228: 683b ldr r3, [r7, #0] 800b22a: 68da ldr r2, [r3, #12] 800b22c: 69fb ldr r3, [r7, #28] 800b22e: 005b lsls r3, r3, #1 800b230: fa02 f303 lsl.w r3, r2, r3 800b234: 69ba ldr r2, [r7, #24] 800b236: 4313 orrs r3, r2 800b238: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800b23a: 687b ldr r3, [r7, #4] 800b23c: 69ba ldr r2, [r7, #24] 800b23e: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800b240: 687b ldr r3, [r7, #4] 800b242: 685b ldr r3, [r3, #4] 800b244: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800b246: 2201 movs r2, #1 800b248: 69fb ldr r3, [r7, #28] 800b24a: fa02 f303 lsl.w r3, r2, r3 800b24e: 43db mvns r3, r3 800b250: 69ba ldr r2, [r7, #24] 800b252: 4013 ands r3, r2 800b254: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800b256: 683b ldr r3, [r7, #0] 800b258: 685b ldr r3, [r3, #4] 800b25a: 091b lsrs r3, r3, #4 800b25c: f003 0201 and.w r2, r3, #1 800b260: 69fb ldr r3, [r7, #28] 800b262: fa02 f303 lsl.w r3, r2, r3 800b266: 69ba ldr r2, [r7, #24] 800b268: 4313 orrs r3, r2 800b26a: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800b26c: 687b ldr r3, [r7, #4] 800b26e: 69ba ldr r2, [r7, #24] 800b270: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800b272: 683b ldr r3, [r7, #0] 800b274: 685b ldr r3, [r3, #4] 800b276: f003 0303 and.w r3, r3, #3 800b27a: 2b03 cmp r3, #3 800b27c: d017 beq.n 800b2ae { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800b27e: 687b ldr r3, [r7, #4] 800b280: 68db ldr r3, [r3, #12] 800b282: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 800b284: 69fb ldr r3, [r7, #28] 800b286: 005b lsls r3, r3, #1 800b288: 2203 movs r2, #3 800b28a: fa02 f303 lsl.w r3, r2, r3 800b28e: 43db mvns r3, r3 800b290: 69ba ldr r2, [r7, #24] 800b292: 4013 ands r3, r2 800b294: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800b296: 683b ldr r3, [r7, #0] 800b298: 689a ldr r2, [r3, #8] 800b29a: 69fb ldr r3, [r7, #28] 800b29c: 005b lsls r3, r3, #1 800b29e: fa02 f303 lsl.w r3, r2, r3 800b2a2: 69ba ldr r2, [r7, #24] 800b2a4: 4313 orrs r3, r2 800b2a6: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800b2a8: 687b ldr r3, [r7, #4] 800b2aa: 69ba ldr r2, [r7, #24] 800b2ac: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800b2ae: 683b ldr r3, [r7, #0] 800b2b0: 685b ldr r3, [r3, #4] 800b2b2: f003 0303 and.w r3, r3, #3 800b2b6: 2b02 cmp r3, #2 800b2b8: d123 bne.n 800b302 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800b2ba: 69fb ldr r3, [r7, #28] 800b2bc: 08da lsrs r2, r3, #3 800b2be: 687b ldr r3, [r7, #4] 800b2c0: 3208 adds r2, #8 800b2c2: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800b2c6: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800b2c8: 69fb ldr r3, [r7, #28] 800b2ca: f003 0307 and.w r3, r3, #7 800b2ce: 009b lsls r3, r3, #2 800b2d0: 220f movs r2, #15 800b2d2: fa02 f303 lsl.w r3, r2, r3 800b2d6: 43db mvns r3, r3 800b2d8: 69ba ldr r2, [r7, #24] 800b2da: 4013 ands r3, r2 800b2dc: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 800b2de: 683b ldr r3, [r7, #0] 800b2e0: 691a ldr r2, [r3, #16] 800b2e2: 69fb ldr r3, [r7, #28] 800b2e4: f003 0307 and.w r3, r3, #7 800b2e8: 009b lsls r3, r3, #2 800b2ea: fa02 f303 lsl.w r3, r2, r3 800b2ee: 69ba ldr r2, [r7, #24] 800b2f0: 4313 orrs r3, r2 800b2f2: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 800b2f4: 69fb ldr r3, [r7, #28] 800b2f6: 08da lsrs r2, r3, #3 800b2f8: 687b ldr r3, [r7, #4] 800b2fa: 3208 adds r2, #8 800b2fc: 69b9 ldr r1, [r7, #24] 800b2fe: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800b302: 687b ldr r3, [r7, #4] 800b304: 681b ldr r3, [r3, #0] 800b306: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800b308: 69fb ldr r3, [r7, #28] 800b30a: 005b lsls r3, r3, #1 800b30c: 2203 movs r2, #3 800b30e: fa02 f303 lsl.w r3, r2, r3 800b312: 43db mvns r3, r3 800b314: 69ba ldr r2, [r7, #24] 800b316: 4013 ands r3, r2 800b318: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800b31a: 683b ldr r3, [r7, #0] 800b31c: 685b ldr r3, [r3, #4] 800b31e: f003 0203 and.w r2, r3, #3 800b322: 69fb ldr r3, [r7, #28] 800b324: 005b lsls r3, r3, #1 800b326: fa02 f303 lsl.w r3, r2, r3 800b32a: 69ba ldr r2, [r7, #24] 800b32c: 4313 orrs r3, r2 800b32e: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 800b330: 687b ldr r3, [r7, #4] 800b332: 69ba ldr r2, [r7, #24] 800b334: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800b336: 683b ldr r3, [r7, #0] 800b338: 685b ldr r3, [r3, #4] 800b33a: f403 3340 and.w r3, r3, #196608 @ 0x30000 800b33e: 2b00 cmp r3, #0 800b340: f000 80e0 beq.w 800b504 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800b344: 4b2f ldr r3, [pc, #188] @ (800b404 ) 800b346: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b34a: 4a2e ldr r2, [pc, #184] @ (800b404 ) 800b34c: f043 0302 orr.w r3, r3, #2 800b350: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800b354: 4b2b ldr r3, [pc, #172] @ (800b404 ) 800b356: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b35a: f003 0302 and.w r3, r3, #2 800b35e: 60fb str r3, [r7, #12] 800b360: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800b362: 4a29 ldr r2, [pc, #164] @ (800b408 ) 800b364: 69fb ldr r3, [r7, #28] 800b366: 089b lsrs r3, r3, #2 800b368: 3302 adds r3, #2 800b36a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800b36e: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800b370: 69fb ldr r3, [r7, #28] 800b372: f003 0303 and.w r3, r3, #3 800b376: 009b lsls r3, r3, #2 800b378: 220f movs r2, #15 800b37a: fa02 f303 lsl.w r3, r2, r3 800b37e: 43db mvns r3, r3 800b380: 69ba ldr r2, [r7, #24] 800b382: 4013 ands r3, r2 800b384: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800b386: 687b ldr r3, [r7, #4] 800b388: 4a20 ldr r2, [pc, #128] @ (800b40c ) 800b38a: 4293 cmp r3, r2 800b38c: d052 beq.n 800b434 800b38e: 687b ldr r3, [r7, #4] 800b390: 4a1f ldr r2, [pc, #124] @ (800b410 ) 800b392: 4293 cmp r3, r2 800b394: d031 beq.n 800b3fa 800b396: 687b ldr r3, [r7, #4] 800b398: 4a1e ldr r2, [pc, #120] @ (800b414 ) 800b39a: 4293 cmp r3, r2 800b39c: d02b beq.n 800b3f6 800b39e: 687b ldr r3, [r7, #4] 800b3a0: 4a1d ldr r2, [pc, #116] @ (800b418 ) 800b3a2: 4293 cmp r3, r2 800b3a4: d025 beq.n 800b3f2 800b3a6: 687b ldr r3, [r7, #4] 800b3a8: 4a1c ldr r2, [pc, #112] @ (800b41c ) 800b3aa: 4293 cmp r3, r2 800b3ac: d01f beq.n 800b3ee 800b3ae: 687b ldr r3, [r7, #4] 800b3b0: 4a1b ldr r2, [pc, #108] @ (800b420 ) 800b3b2: 4293 cmp r3, r2 800b3b4: d019 beq.n 800b3ea 800b3b6: 687b ldr r3, [r7, #4] 800b3b8: 4a1a ldr r2, [pc, #104] @ (800b424 ) 800b3ba: 4293 cmp r3, r2 800b3bc: d013 beq.n 800b3e6 800b3be: 687b ldr r3, [r7, #4] 800b3c0: 4a19 ldr r2, [pc, #100] @ (800b428 ) 800b3c2: 4293 cmp r3, r2 800b3c4: d00d beq.n 800b3e2 800b3c6: 687b ldr r3, [r7, #4] 800b3c8: 4a18 ldr r2, [pc, #96] @ (800b42c ) 800b3ca: 4293 cmp r3, r2 800b3cc: d007 beq.n 800b3de 800b3ce: 687b ldr r3, [r7, #4] 800b3d0: 4a17 ldr r2, [pc, #92] @ (800b430 ) 800b3d2: 4293 cmp r3, r2 800b3d4: d101 bne.n 800b3da 800b3d6: 2309 movs r3, #9 800b3d8: e02d b.n 800b436 800b3da: 230a movs r3, #10 800b3dc: e02b b.n 800b436 800b3de: 2308 movs r3, #8 800b3e0: e029 b.n 800b436 800b3e2: 2307 movs r3, #7 800b3e4: e027 b.n 800b436 800b3e6: 2306 movs r3, #6 800b3e8: e025 b.n 800b436 800b3ea: 2305 movs r3, #5 800b3ec: e023 b.n 800b436 800b3ee: 2304 movs r3, #4 800b3f0: e021 b.n 800b436 800b3f2: 2303 movs r3, #3 800b3f4: e01f b.n 800b436 800b3f6: 2302 movs r3, #2 800b3f8: e01d b.n 800b436 800b3fa: 2301 movs r3, #1 800b3fc: e01b b.n 800b436 800b3fe: bf00 nop 800b400: 58000080 .word 0x58000080 800b404: 58024400 .word 0x58024400 800b408: 58000400 .word 0x58000400 800b40c: 58020000 .word 0x58020000 800b410: 58020400 .word 0x58020400 800b414: 58020800 .word 0x58020800 800b418: 58020c00 .word 0x58020c00 800b41c: 58021000 .word 0x58021000 800b420: 58021400 .word 0x58021400 800b424: 58021800 .word 0x58021800 800b428: 58021c00 .word 0x58021c00 800b42c: 58022000 .word 0x58022000 800b430: 58022400 .word 0x58022400 800b434: 2300 movs r3, #0 800b436: 69fa ldr r2, [r7, #28] 800b438: f002 0203 and.w r2, r2, #3 800b43c: 0092 lsls r2, r2, #2 800b43e: 4093 lsls r3, r2 800b440: 69ba ldr r2, [r7, #24] 800b442: 4313 orrs r3, r2 800b444: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800b446: 4938 ldr r1, [pc, #224] @ (800b528 ) 800b448: 69fb ldr r3, [r7, #28] 800b44a: 089b lsrs r3, r3, #2 800b44c: 3302 adds r3, #2 800b44e: 69ba ldr r2, [r7, #24] 800b450: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800b454: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b458: 681b ldr r3, [r3, #0] 800b45a: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b45c: 693b ldr r3, [r7, #16] 800b45e: 43db mvns r3, r3 800b460: 69ba ldr r2, [r7, #24] 800b462: 4013 ands r3, r2 800b464: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800b466: 683b ldr r3, [r7, #0] 800b468: 685b ldr r3, [r3, #4] 800b46a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800b46e: 2b00 cmp r3, #0 800b470: d003 beq.n 800b47a { temp |= iocurrent; 800b472: 69ba ldr r2, [r7, #24] 800b474: 693b ldr r3, [r7, #16] 800b476: 4313 orrs r3, r2 800b478: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 800b47a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b47e: 69bb ldr r3, [r7, #24] 800b480: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800b482: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b486: 685b ldr r3, [r3, #4] 800b488: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b48a: 693b ldr r3, [r7, #16] 800b48c: 43db mvns r3, r3 800b48e: 69ba ldr r2, [r7, #24] 800b490: 4013 ands r3, r2 800b492: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800b494: 683b ldr r3, [r7, #0] 800b496: 685b ldr r3, [r3, #4] 800b498: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800b49c: 2b00 cmp r3, #0 800b49e: d003 beq.n 800b4a8 { temp |= iocurrent; 800b4a0: 69ba ldr r2, [r7, #24] 800b4a2: 693b ldr r3, [r7, #16] 800b4a4: 4313 orrs r3, r2 800b4a6: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 800b4a8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b4ac: 69bb ldr r3, [r7, #24] 800b4ae: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800b4b0: 697b ldr r3, [r7, #20] 800b4b2: 685b ldr r3, [r3, #4] 800b4b4: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b4b6: 693b ldr r3, [r7, #16] 800b4b8: 43db mvns r3, r3 800b4ba: 69ba ldr r2, [r7, #24] 800b4bc: 4013 ands r3, r2 800b4be: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800b4c0: 683b ldr r3, [r7, #0] 800b4c2: 685b ldr r3, [r3, #4] 800b4c4: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b4c8: 2b00 cmp r3, #0 800b4ca: d003 beq.n 800b4d4 { temp |= iocurrent; 800b4cc: 69ba ldr r2, [r7, #24] 800b4ce: 693b ldr r3, [r7, #16] 800b4d0: 4313 orrs r3, r2 800b4d2: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 800b4d4: 697b ldr r3, [r7, #20] 800b4d6: 69ba ldr r2, [r7, #24] 800b4d8: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 800b4da: 697b ldr r3, [r7, #20] 800b4dc: 681b ldr r3, [r3, #0] 800b4de: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b4e0: 693b ldr r3, [r7, #16] 800b4e2: 43db mvns r3, r3 800b4e4: 69ba ldr r2, [r7, #24] 800b4e6: 4013 ands r3, r2 800b4e8: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 800b4ea: 683b ldr r3, [r7, #0] 800b4ec: 685b ldr r3, [r3, #4] 800b4ee: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b4f2: 2b00 cmp r3, #0 800b4f4: d003 beq.n 800b4fe { temp |= iocurrent; 800b4f6: 69ba ldr r2, [r7, #24] 800b4f8: 693b ldr r3, [r7, #16] 800b4fa: 4313 orrs r3, r2 800b4fc: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 800b4fe: 697b ldr r3, [r7, #20] 800b500: 69ba ldr r2, [r7, #24] 800b502: 601a str r2, [r3, #0] } } position++; 800b504: 69fb ldr r3, [r7, #28] 800b506: 3301 adds r3, #1 800b508: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 800b50a: 683b ldr r3, [r7, #0] 800b50c: 681a ldr r2, [r3, #0] 800b50e: 69fb ldr r3, [r7, #28] 800b510: fa22 f303 lsr.w r3, r2, r3 800b514: 2b00 cmp r3, #0 800b516: f47f ae63 bne.w 800b1e0 } } 800b51a: bf00 nop 800b51c: bf00 nop 800b51e: 3724 adds r7, #36 @ 0x24 800b520: 46bd mov sp, r7 800b522: f85d 7b04 ldr.w r7, [sp], #4 800b526: 4770 bx lr 800b528: 58000400 .word 0x58000400 0800b52c : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b52c: b480 push {r7} 800b52e: b085 sub sp, #20 800b530: af00 add r7, sp, #0 800b532: 6078 str r0, [r7, #4] 800b534: 460b mov r3, r1 800b536: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 800b538: 687b ldr r3, [r7, #4] 800b53a: 691a ldr r2, [r3, #16] 800b53c: 887b ldrh r3, [r7, #2] 800b53e: 4013 ands r3, r2 800b540: 2b00 cmp r3, #0 800b542: d002 beq.n 800b54a { bitstatus = GPIO_PIN_SET; 800b544: 2301 movs r3, #1 800b546: 73fb strb r3, [r7, #15] 800b548: e001 b.n 800b54e } else { bitstatus = GPIO_PIN_RESET; 800b54a: 2300 movs r3, #0 800b54c: 73fb strb r3, [r7, #15] } return bitstatus; 800b54e: 7bfb ldrb r3, [r7, #15] } 800b550: 4618 mov r0, r3 800b552: 3714 adds r7, #20 800b554: 46bd mov sp, r7 800b556: f85d 7b04 ldr.w r7, [sp], #4 800b55a: 4770 bx lr 0800b55c : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800b55c: b480 push {r7} 800b55e: b083 sub sp, #12 800b560: af00 add r7, sp, #0 800b562: 6078 str r0, [r7, #4] 800b564: 460b mov r3, r1 800b566: 807b strh r3, [r7, #2] 800b568: 4613 mov r3, r2 800b56a: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800b56c: 787b ldrb r3, [r7, #1] 800b56e: 2b00 cmp r3, #0 800b570: d003 beq.n 800b57a { GPIOx->BSRR = GPIO_Pin; 800b572: 887a ldrh r2, [r7, #2] 800b574: 687b ldr r3, [r7, #4] 800b576: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 800b578: e003 b.n 800b582 GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 800b57a: 887b ldrh r3, [r7, #2] 800b57c: 041a lsls r2, r3, #16 800b57e: 687b ldr r3, [r7, #4] 800b580: 619a str r2, [r3, #24] } 800b582: bf00 nop 800b584: 370c adds r7, #12 800b586: 46bd mov sp, r7 800b588: f85d 7b04 ldr.w r7, [sp], #4 800b58c: 4770 bx lr 0800b58e : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b58e: b480 push {r7} 800b590: b085 sub sp, #20 800b592: af00 add r7, sp, #0 800b594: 6078 str r0, [r7, #4] 800b596: 460b mov r3, r1 800b598: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 800b59a: 687b ldr r3, [r7, #4] 800b59c: 695b ldr r3, [r3, #20] 800b59e: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800b5a0: 887a ldrh r2, [r7, #2] 800b5a2: 68fb ldr r3, [r7, #12] 800b5a4: 4013 ands r3, r2 800b5a6: 041a lsls r2, r3, #16 800b5a8: 68fb ldr r3, [r7, #12] 800b5aa: 43d9 mvns r1, r3 800b5ac: 887b ldrh r3, [r7, #2] 800b5ae: 400b ands r3, r1 800b5b0: 431a orrs r2, r3 800b5b2: 687b ldr r3, [r7, #4] 800b5b4: 619a str r2, [r3, #24] } 800b5b6: bf00 nop 800b5b8: 3714 adds r7, #20 800b5ba: 46bd mov sp, r7 800b5bc: f85d 7b04 ldr.w r7, [sp], #4 800b5c0: 4770 bx lr 0800b5c2 : * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 800b5c2: b580 push {r7, lr} 800b5c4: b082 sub sp, #8 800b5c6: af00 add r7, sp, #0 800b5c8: 4603 mov r3, r0 800b5ca: 80fb strh r3, [r7, #6] __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 800b5cc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5d0: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800b5d4: 88fb ldrh r3, [r7, #6] 800b5d6: 4013 ands r3, r2 800b5d8: 2b00 cmp r3, #0 800b5da: d008 beq.n 800b5ee { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800b5dc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b5e0: 88fb ldrh r3, [r7, #6] 800b5e2: f8c2 3088 str.w r3, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 800b5e6: 88fb ldrh r3, [r7, #6] 800b5e8: 4618 mov r0, r3 800b5ea: f7f5 f813 bl 8000614 } #endif } 800b5ee: bf00 nop 800b5f0: 3708 adds r7, #8 800b5f2: 46bd mov sp, r7 800b5f4: bd80 pop {r7, pc} 0800b5f6 : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { 800b5f6: b580 push {r7, lr} 800b5f8: b084 sub sp, #16 800b5fa: af00 add r7, sp, #0 800b5fc: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) 800b5fe: 687b ldr r3, [r7, #4] 800b600: 2b00 cmp r3, #0 800b602: d101 bne.n 800b608 { return HAL_ERROR; 800b604: 2301 movs r3, #1 800b606: e041 b.n 800b68c assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); 800b608: 687b ldr r3, [r7, #4] 800b60a: 681b ldr r3, [r3, #0] 800b60c: f64c 42cc movw r2, #52428 @ 0xcccc 800b610: 601a str r2, [r3, #0] /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); 800b612: 687b ldr r3, [r7, #4] 800b614: 681b ldr r3, [r3, #0] 800b616: f245 5255 movw r2, #21845 @ 0x5555 800b61a: 601a str r2, [r3, #0] /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; 800b61c: 687b ldr r3, [r7, #4] 800b61e: 681b ldr r3, [r3, #0] 800b620: 687a ldr r2, [r7, #4] 800b622: 6852 ldr r2, [r2, #4] 800b624: 605a str r2, [r3, #4] hiwdg->Instance->RLR = hiwdg->Init.Reload; 800b626: 687b ldr r3, [r7, #4] 800b628: 681b ldr r3, [r3, #0] 800b62a: 687a ldr r2, [r7, #4] 800b62c: 6892 ldr r2, [r2, #8] 800b62e: 609a str r2, [r3, #8] /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); 800b630: f7fa fbf4 bl 8005e1c 800b634: 60f8 str r0, [r7, #12] /* Wait for register to be updated */ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b636: e00f b.n 800b658 { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) 800b638: f7fa fbf0 bl 8005e1c 800b63c: 4602 mov r2, r0 800b63e: 68fb ldr r3, [r7, #12] 800b640: 1ad3 subs r3, r2, r3 800b642: 2b31 cmp r3, #49 @ 0x31 800b644: d908 bls.n 800b658 { if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b646: 687b ldr r3, [r7, #4] 800b648: 681b ldr r3, [r3, #0] 800b64a: 68db ldr r3, [r3, #12] 800b64c: f003 0307 and.w r3, r3, #7 800b650: 2b00 cmp r3, #0 800b652: d001 beq.n 800b658 { return HAL_TIMEOUT; 800b654: 2303 movs r3, #3 800b656: e019 b.n 800b68c while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b658: 687b ldr r3, [r7, #4] 800b65a: 681b ldr r3, [r3, #0] 800b65c: 68db ldr r3, [r3, #12] 800b65e: f003 0307 and.w r3, r3, #7 800b662: 2b00 cmp r3, #0 800b664: d1e8 bne.n 800b638 } } /* If window parameter is different than current value, modify window register */ if (hiwdg->Instance->WINR != hiwdg->Init.Window) 800b666: 687b ldr r3, [r7, #4] 800b668: 681b ldr r3, [r3, #0] 800b66a: 691a ldr r2, [r3, #16] 800b66c: 687b ldr r3, [r7, #4] 800b66e: 68db ldr r3, [r3, #12] 800b670: 429a cmp r2, r3 800b672: d005 beq.n 800b680 { /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, even if window feature is disabled, Watchdog will be reloaded by writing windows register */ hiwdg->Instance->WINR = hiwdg->Init.Window; 800b674: 687b ldr r3, [r7, #4] 800b676: 681b ldr r3, [r3, #0] 800b678: 687a ldr r2, [r7, #4] 800b67a: 68d2 ldr r2, [r2, #12] 800b67c: 611a str r2, [r3, #16] 800b67e: e004 b.n 800b68a } else { /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b680: 687b ldr r3, [r7, #4] 800b682: 681b ldr r3, [r3, #0] 800b684: f64a 22aa movw r2, #43690 @ 0xaaaa 800b688: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800b68a: 2300 movs r3, #0 } 800b68c: 4618 mov r0, r3 800b68e: 3710 adds r7, #16 800b690: 46bd mov sp, r7 800b692: bd80 pop {r7, pc} 0800b694 : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { 800b694: b480 push {r7} 800b696: b083 sub sp, #12 800b698: af00 add r7, sp, #0 800b69a: 6078 str r0, [r7, #4] /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b69c: 687b ldr r3, [r7, #4] 800b69e: 681b ldr r3, [r3, #0] 800b6a0: f64a 22aa movw r2, #43690 @ 0xaaaa 800b6a4: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800b6a6: 2300 movs r3, #0 } 800b6a8: 4618 mov r0, r3 800b6aa: 370c adds r7, #12 800b6ac: 46bd mov sp, r7 800b6ae: f85d 7b04 ldr.w r7, [sp], #4 800b6b2: 4770 bx lr 0800b6b4 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { 800b6b4: b480 push {r7} 800b6b6: b083 sub sp, #12 800b6b8: af00 add r7, sp, #0 800b6ba: 6078 str r0, [r7, #4] /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 800b6bc: 687b ldr r3, [r7, #4] 800b6be: 2b00 cmp r3, #0 800b6c0: d069 beq.n 800b796 /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800b6c2: 4b38 ldr r3, [pc, #224] @ (800b7a4 ) 800b6c4: 681b ldr r3, [r3, #0] 800b6c6: f023 02e0 bic.w r2, r3, #224 @ 0xe0 800b6ca: 687b ldr r3, [r7, #4] 800b6cc: 681b ldr r3, [r3, #0] 800b6ce: 4935 ldr r1, [pc, #212] @ (800b7a4 ) 800b6d0: 4313 orrs r3, r2 800b6d2: 600b str r3, [r1, #0] /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 800b6d4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6d8: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b6dc: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6e0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6e4: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 800b6e8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6ec: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b6f0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6f4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6f8: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 800b6fc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b700: 681b ldr r3, [r3, #0] 800b702: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b706: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b70a: 6013 str r3, [r2, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 800b70c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b710: 685b ldr r3, [r3, #4] 800b712: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b716: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b71a: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 800b71c: 687b ldr r3, [r7, #4] 800b71e: 685b ldr r3, [r3, #4] 800b720: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b724: 2b00 cmp r3, #0 800b726: d009 beq.n 800b73c { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 800b728: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b72c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b730: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b734: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b738: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 800b73c: 687b ldr r3, [r7, #4] 800b73e: 685b ldr r3, [r3, #4] 800b740: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b744: 2b00 cmp r3, #0 800b746: d009 beq.n 800b75c { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 800b748: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b74c: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b750: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b754: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b758: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 800b75c: 687b ldr r3, [r7, #4] 800b75e: 685b ldr r3, [r3, #4] 800b760: f003 0301 and.w r3, r3, #1 800b764: 2b00 cmp r3, #0 800b766: d007 beq.n 800b778 { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 800b768: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b76c: 681b ldr r3, [r3, #0] 800b76e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b772: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b776: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 800b778: 687b ldr r3, [r7, #4] 800b77a: 685b ldr r3, [r3, #4] 800b77c: f003 0302 and.w r3, r3, #2 800b780: 2b00 cmp r3, #0 800b782: d009 beq.n 800b798 { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 800b784: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b788: 685b ldr r3, [r3, #4] 800b78a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b78e: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b792: 6053 str r3, [r2, #4] 800b794: e000 b.n 800b798 return; 800b796: bf00 nop } } 800b798: 370c adds r7, #12 800b79a: 46bd mov sp, r7 800b79c: f85d 7b04 ldr.w r7, [sp], #4 800b7a0: 4770 bx lr 800b7a2: bf00 nop 800b7a4: 58024800 .word 0x58024800 0800b7a8 : /** * @brief Enable the Programmable Voltage Detector (PVD). * @retval None. */ void HAL_PWR_EnablePVD (void) { 800b7a8: b480 push {r7} 800b7aa: af00 add r7, sp, #0 /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 800b7ac: 4b05 ldr r3, [pc, #20] @ (800b7c4 ) 800b7ae: 681b ldr r3, [r3, #0] 800b7b0: 4a04 ldr r2, [pc, #16] @ (800b7c4 ) 800b7b2: f043 0310 orr.w r3, r3, #16 800b7b6: 6013 str r3, [r2, #0] } 800b7b8: bf00 nop 800b7ba: 46bd mov sp, r7 800b7bc: f85d 7b04 ldr.w r7, [sp], #4 800b7c0: 4770 bx lr 800b7c2: bf00 nop 800b7c4: 58024800 .word 0x58024800 0800b7c8 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800b7c8: b580 push {r7, lr} 800b7ca: b084 sub sp, #16 800b7cc: af00 add r7, sp, #0 800b7ce: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800b7d0: 4b19 ldr r3, [pc, #100] @ (800b838 ) 800b7d2: 68db ldr r3, [r3, #12] 800b7d4: f003 0304 and.w r3, r3, #4 800b7d8: 2b04 cmp r3, #4 800b7da: d00a beq.n 800b7f2 #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800b7dc: 4b16 ldr r3, [pc, #88] @ (800b838 ) 800b7de: 68db ldr r3, [r3, #12] 800b7e0: f003 0307 and.w r3, r3, #7 800b7e4: 687a ldr r2, [r7, #4] 800b7e6: 429a cmp r2, r3 800b7e8: d001 beq.n 800b7ee { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800b7ea: 2301 movs r3, #1 800b7ec: e01f b.n 800b82e else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800b7ee: 2300 movs r3, #0 800b7f0: e01d b.n 800b82e } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800b7f2: 4b11 ldr r3, [pc, #68] @ (800b838 ) 800b7f4: 68db ldr r3, [r3, #12] 800b7f6: f023 0207 bic.w r2, r3, #7 800b7fa: 490f ldr r1, [pc, #60] @ (800b838 ) 800b7fc: 687b ldr r3, [r7, #4] 800b7fe: 4313 orrs r3, r2 800b800: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 800b802: f7fa fb0b bl 8005e1c 800b806: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b808: e009 b.n 800b81e { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800b80a: f7fa fb07 bl 8005e1c 800b80e: 4602 mov r2, r0 800b810: 68fb ldr r3, [r7, #12] 800b812: 1ad3 subs r3, r2, r3 800b814: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b818: d901 bls.n 800b81e { return HAL_ERROR; 800b81a: 2301 movs r3, #1 800b81c: e007 b.n 800b82e while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b81e: 4b06 ldr r3, [pc, #24] @ (800b838 ) 800b820: 685b ldr r3, [r3, #4] 800b822: f403 5300 and.w r3, r3, #8192 @ 0x2000 800b826: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800b82a: d1ee bne.n 800b80a } } } #endif /* defined (SMPS) */ return HAL_OK; 800b82c: 2300 movs r3, #0 } 800b82e: 4618 mov r0, r3 800b830: 3710 adds r7, #16 800b832: 46bd mov sp, r7 800b834: bd80 pop {r7, pc} 800b836: bf00 nop 800b838: 58024800 .word 0x58024800 0800b83c : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { 800b83c: b480 push {r7} 800b83e: b083 sub sp, #12 800b840: af00 add r7, sp, #0 800b842: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800b844: 4b37 ldr r3, [pc, #220] @ (800b924 ) 800b846: 681b ldr r3, [r3, #0] 800b848: f423 22c0 bic.w r2, r3, #393216 @ 0x60000 800b84c: 687b ldr r3, [r7, #4] 800b84e: 681b ldr r3, [r3, #0] 800b850: 4934 ldr r1, [pc, #208] @ (800b924 ) 800b852: 4313 orrs r3, r2 800b854: 600b str r3, [r1, #0] /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800b856: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b85a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b85e: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b862: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b866: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800b86a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b86e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b872: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b876: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b87a: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 800b87e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b882: 681b ldr r3, [r3, #0] 800b884: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b888: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b88c: 6013 str r3, [r2, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 800b88e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b892: 685b ldr r3, [r3, #4] 800b894: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b898: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b89c: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 800b89e: 687b ldr r3, [r7, #4] 800b8a0: 685b ldr r3, [r3, #4] 800b8a2: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b8a6: 2b00 cmp r3, #0 800b8a8: d009 beq.n 800b8be { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800b8aa: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8ae: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b8b2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8b6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b8ba: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800b8be: 687b ldr r3, [r7, #4] 800b8c0: 685b ldr r3, [r3, #4] 800b8c2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b8c6: 2b00 cmp r3, #0 800b8c8: d009 beq.n 800b8de { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800b8ca: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8ce: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b8d2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8d6: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b8da: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 800b8de: 687b ldr r3, [r7, #4] 800b8e0: 685b ldr r3, [r3, #4] 800b8e2: f003 0301 and.w r3, r3, #1 800b8e6: 2b00 cmp r3, #0 800b8e8: d007 beq.n 800b8fa { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 800b8ea: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8ee: 681b ldr r3, [r3, #0] 800b8f0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8f4: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b8f8: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 800b8fa: 687b ldr r3, [r7, #4] 800b8fc: 685b ldr r3, [r3, #4] 800b8fe: f003 0302 and.w r3, r3, #2 800b902: 2b00 cmp r3, #0 800b904: d007 beq.n 800b916 { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 800b906: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b90a: 685b ldr r3, [r3, #4] 800b90c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b910: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b914: 6053 str r3, [r2, #4] } } 800b916: bf00 nop 800b918: 370c adds r7, #12 800b91a: 46bd mov sp, r7 800b91c: f85d 7b04 ldr.w r7, [sp], #4 800b920: 4770 bx lr 800b922: bf00 nop 800b924: 58024800 .word 0x58024800 0800b928 : /** * @brief Enable the Analog Voltage Detector (AVD). * @retval None. */ void HAL_PWREx_EnableAVD (void) { 800b928: b480 push {r7} 800b92a: af00 add r7, sp, #0 /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 800b92c: 4b05 ldr r3, [pc, #20] @ (800b944 ) 800b92e: 681b ldr r3, [r3, #0] 800b930: 4a04 ldr r2, [pc, #16] @ (800b944 ) 800b932: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b936: 6013 str r3, [r2, #0] } 800b938: bf00 nop 800b93a: 46bd mov sp, r7 800b93c: f85d 7b04 ldr.w r7, [sp], #4 800b940: 4770 bx lr 800b942: bf00 nop 800b944: 58024800 .word 0x58024800 0800b948 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800b948: b580 push {r7, lr} 800b94a: b08c sub sp, #48 @ 0x30 800b94c: af00 add r7, sp, #0 800b94e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800b950: 687b ldr r3, [r7, #4] 800b952: 2b00 cmp r3, #0 800b954: d102 bne.n 800b95c { return HAL_ERROR; 800b956: 2301 movs r3, #1 800b958: f000 bc48 b.w 800c1ec } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800b95c: 687b ldr r3, [r7, #4] 800b95e: 681b ldr r3, [r3, #0] 800b960: f003 0301 and.w r3, r3, #1 800b964: 2b00 cmp r3, #0 800b966: f000 8088 beq.w 800ba7a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b96a: 4b99 ldr r3, [pc, #612] @ (800bbd0 ) 800b96c: 691b ldr r3, [r3, #16] 800b96e: f003 0338 and.w r3, r3, #56 @ 0x38 800b972: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b974: 4b96 ldr r3, [pc, #600] @ (800bbd0 ) 800b976: 6a9b ldr r3, [r3, #40] @ 0x28 800b978: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800b97a: 6afb ldr r3, [r7, #44] @ 0x2c 800b97c: 2b10 cmp r3, #16 800b97e: d007 beq.n 800b990 800b980: 6afb ldr r3, [r7, #44] @ 0x2c 800b982: 2b18 cmp r3, #24 800b984: d111 bne.n 800b9aa 800b986: 6abb ldr r3, [r7, #40] @ 0x28 800b988: f003 0303 and.w r3, r3, #3 800b98c: 2b02 cmp r3, #2 800b98e: d10c bne.n 800b9aa { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800b990: 4b8f ldr r3, [pc, #572] @ (800bbd0 ) 800b992: 681b ldr r3, [r3, #0] 800b994: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b998: 2b00 cmp r3, #0 800b99a: d06d beq.n 800ba78 800b99c: 687b ldr r3, [r7, #4] 800b99e: 685b ldr r3, [r3, #4] 800b9a0: 2b00 cmp r3, #0 800b9a2: d169 bne.n 800ba78 { return HAL_ERROR; 800b9a4: 2301 movs r3, #1 800b9a6: f000 bc21 b.w 800c1ec } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800b9aa: 687b ldr r3, [r7, #4] 800b9ac: 685b ldr r3, [r3, #4] 800b9ae: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b9b2: d106 bne.n 800b9c2 800b9b4: 4b86 ldr r3, [pc, #536] @ (800bbd0 ) 800b9b6: 681b ldr r3, [r3, #0] 800b9b8: 4a85 ldr r2, [pc, #532] @ (800bbd0 ) 800b9ba: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b9be: 6013 str r3, [r2, #0] 800b9c0: e02e b.n 800ba20 800b9c2: 687b ldr r3, [r7, #4] 800b9c4: 685b ldr r3, [r3, #4] 800b9c6: 2b00 cmp r3, #0 800b9c8: d10c bne.n 800b9e4 800b9ca: 4b81 ldr r3, [pc, #516] @ (800bbd0 ) 800b9cc: 681b ldr r3, [r3, #0] 800b9ce: 4a80 ldr r2, [pc, #512] @ (800bbd0 ) 800b9d0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b9d4: 6013 str r3, [r2, #0] 800b9d6: 4b7e ldr r3, [pc, #504] @ (800bbd0 ) 800b9d8: 681b ldr r3, [r3, #0] 800b9da: 4a7d ldr r2, [pc, #500] @ (800bbd0 ) 800b9dc: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800b9e0: 6013 str r3, [r2, #0] 800b9e2: e01d b.n 800ba20 800b9e4: 687b ldr r3, [r7, #4] 800b9e6: 685b ldr r3, [r3, #4] 800b9e8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800b9ec: d10c bne.n 800ba08 800b9ee: 4b78 ldr r3, [pc, #480] @ (800bbd0 ) 800b9f0: 681b ldr r3, [r3, #0] 800b9f2: 4a77 ldr r2, [pc, #476] @ (800bbd0 ) 800b9f4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800b9f8: 6013 str r3, [r2, #0] 800b9fa: 4b75 ldr r3, [pc, #468] @ (800bbd0 ) 800b9fc: 681b ldr r3, [r3, #0] 800b9fe: 4a74 ldr r2, [pc, #464] @ (800bbd0 ) 800ba00: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ba04: 6013 str r3, [r2, #0] 800ba06: e00b b.n 800ba20 800ba08: 4b71 ldr r3, [pc, #452] @ (800bbd0 ) 800ba0a: 681b ldr r3, [r3, #0] 800ba0c: 4a70 ldr r2, [pc, #448] @ (800bbd0 ) 800ba0e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ba12: 6013 str r3, [r2, #0] 800ba14: 4b6e ldr r3, [pc, #440] @ (800bbd0 ) 800ba16: 681b ldr r3, [r3, #0] 800ba18: 4a6d ldr r2, [pc, #436] @ (800bbd0 ) 800ba1a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800ba1e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800ba20: 687b ldr r3, [r7, #4] 800ba22: 685b ldr r3, [r3, #4] 800ba24: 2b00 cmp r3, #0 800ba26: d013 beq.n 800ba50 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba28: f7fa f9f8 bl 8005e1c 800ba2c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800ba2e: e008 b.n 800ba42 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800ba30: f7fa f9f4 bl 8005e1c 800ba34: 4602 mov r2, r0 800ba36: 6a7b ldr r3, [r7, #36] @ 0x24 800ba38: 1ad3 subs r3, r2, r3 800ba3a: 2b64 cmp r3, #100 @ 0x64 800ba3c: d901 bls.n 800ba42 { return HAL_TIMEOUT; 800ba3e: 2303 movs r3, #3 800ba40: e3d4 b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800ba42: 4b63 ldr r3, [pc, #396] @ (800bbd0 ) 800ba44: 681b ldr r3, [r3, #0] 800ba46: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ba4a: 2b00 cmp r3, #0 800ba4c: d0f0 beq.n 800ba30 800ba4e: e014 b.n 800ba7a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba50: f7fa f9e4 bl 8005e1c 800ba54: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800ba56: e008 b.n 800ba6a { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800ba58: f7fa f9e0 bl 8005e1c 800ba5c: 4602 mov r2, r0 800ba5e: 6a7b ldr r3, [r7, #36] @ 0x24 800ba60: 1ad3 subs r3, r2, r3 800ba62: 2b64 cmp r3, #100 @ 0x64 800ba64: d901 bls.n 800ba6a { return HAL_TIMEOUT; 800ba66: 2303 movs r3, #3 800ba68: e3c0 b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800ba6a: 4b59 ldr r3, [pc, #356] @ (800bbd0 ) 800ba6c: 681b ldr r3, [r3, #0] 800ba6e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ba72: 2b00 cmp r3, #0 800ba74: d1f0 bne.n 800ba58 800ba76: e000 b.n 800ba7a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800ba78: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800ba7a: 687b ldr r3, [r7, #4] 800ba7c: 681b ldr r3, [r3, #0] 800ba7e: f003 0302 and.w r3, r3, #2 800ba82: 2b00 cmp r3, #0 800ba84: f000 80ca beq.w 800bc1c /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800ba88: 4b51 ldr r3, [pc, #324] @ (800bbd0 ) 800ba8a: 691b ldr r3, [r3, #16] 800ba8c: f003 0338 and.w r3, r3, #56 @ 0x38 800ba90: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800ba92: 4b4f ldr r3, [pc, #316] @ (800bbd0 ) 800ba94: 6a9b ldr r3, [r3, #40] @ 0x28 800ba96: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800ba98: 6a3b ldr r3, [r7, #32] 800ba9a: 2b00 cmp r3, #0 800ba9c: d007 beq.n 800baae 800ba9e: 6a3b ldr r3, [r7, #32] 800baa0: 2b18 cmp r3, #24 800baa2: d156 bne.n 800bb52 800baa4: 69fb ldr r3, [r7, #28] 800baa6: f003 0303 and.w r3, r3, #3 800baaa: 2b00 cmp r3, #0 800baac: d151 bne.n 800bb52 { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800baae: 4b48 ldr r3, [pc, #288] @ (800bbd0 ) 800bab0: 681b ldr r3, [r3, #0] 800bab2: f003 0304 and.w r3, r3, #4 800bab6: 2b00 cmp r3, #0 800bab8: d005 beq.n 800bac6 800baba: 687b ldr r3, [r7, #4] 800babc: 68db ldr r3, [r3, #12] 800babe: 2b00 cmp r3, #0 800bac0: d101 bne.n 800bac6 { return HAL_ERROR; 800bac2: 2301 movs r3, #1 800bac4: e392 b.n 800c1ec } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800bac6: 4b42 ldr r3, [pc, #264] @ (800bbd0 ) 800bac8: 681b ldr r3, [r3, #0] 800baca: f023 0219 bic.w r2, r3, #25 800bace: 687b ldr r3, [r7, #4] 800bad0: 68db ldr r3, [r3, #12] 800bad2: 493f ldr r1, [pc, #252] @ (800bbd0 ) 800bad4: 4313 orrs r3, r2 800bad6: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bad8: f7fa f9a0 bl 8005e1c 800badc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bade: e008 b.n 800baf2 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bae0: f7fa f99c bl 8005e1c 800bae4: 4602 mov r2, r0 800bae6: 6a7b ldr r3, [r7, #36] @ 0x24 800bae8: 1ad3 subs r3, r2, r3 800baea: 2b02 cmp r3, #2 800baec: d901 bls.n 800baf2 { return HAL_TIMEOUT; 800baee: 2303 movs r3, #3 800baf0: e37c b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800baf2: 4b37 ldr r3, [pc, #220] @ (800bbd0 ) 800baf4: 681b ldr r3, [r3, #0] 800baf6: f003 0304 and.w r3, r3, #4 800bafa: 2b00 cmp r3, #0 800bafc: d0f0 beq.n 800bae0 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bafe: f7fa f999 bl 8005e34 800bb02: 4603 mov r3, r0 800bb04: f241 0203 movw r2, #4099 @ 0x1003 800bb08: 4293 cmp r3, r2 800bb0a: d817 bhi.n 800bb3c 800bb0c: 687b ldr r3, [r7, #4] 800bb0e: 691b ldr r3, [r3, #16] 800bb10: 2b40 cmp r3, #64 @ 0x40 800bb12: d108 bne.n 800bb26 800bb14: 4b2e ldr r3, [pc, #184] @ (800bbd0 ) 800bb16: 685b ldr r3, [r3, #4] 800bb18: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800bb1c: 4a2c ldr r2, [pc, #176] @ (800bbd0 ) 800bb1e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bb22: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb24: e07a b.n 800bc1c __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb26: 4b2a ldr r3, [pc, #168] @ (800bbd0 ) 800bb28: 685b ldr r3, [r3, #4] 800bb2a: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800bb2e: 687b ldr r3, [r7, #4] 800bb30: 691b ldr r3, [r3, #16] 800bb32: 031b lsls r3, r3, #12 800bb34: 4926 ldr r1, [pc, #152] @ (800bbd0 ) 800bb36: 4313 orrs r3, r2 800bb38: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb3a: e06f b.n 800bc1c __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb3c: 4b24 ldr r3, [pc, #144] @ (800bbd0 ) 800bb3e: 685b ldr r3, [r3, #4] 800bb40: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800bb44: 687b ldr r3, [r7, #4] 800bb46: 691b ldr r3, [r3, #16] 800bb48: 061b lsls r3, r3, #24 800bb4a: 4921 ldr r1, [pc, #132] @ (800bbd0 ) 800bb4c: 4313 orrs r3, r2 800bb4e: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb50: e064 b.n 800bc1c } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800bb52: 687b ldr r3, [r7, #4] 800bb54: 68db ldr r3, [r3, #12] 800bb56: 2b00 cmp r3, #0 800bb58: d047 beq.n 800bbea { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800bb5a: 4b1d ldr r3, [pc, #116] @ (800bbd0 ) 800bb5c: 681b ldr r3, [r3, #0] 800bb5e: f023 0219 bic.w r2, r3, #25 800bb62: 687b ldr r3, [r7, #4] 800bb64: 68db ldr r3, [r3, #12] 800bb66: 491a ldr r1, [pc, #104] @ (800bbd0 ) 800bb68: 4313 orrs r3, r2 800bb6a: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bb6c: f7fa f956 bl 8005e1c 800bb70: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bb72: e008 b.n 800bb86 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bb74: f7fa f952 bl 8005e1c 800bb78: 4602 mov r2, r0 800bb7a: 6a7b ldr r3, [r7, #36] @ 0x24 800bb7c: 1ad3 subs r3, r2, r3 800bb7e: 2b02 cmp r3, #2 800bb80: d901 bls.n 800bb86 { return HAL_TIMEOUT; 800bb82: 2303 movs r3, #3 800bb84: e332 b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bb86: 4b12 ldr r3, [pc, #72] @ (800bbd0 ) 800bb88: 681b ldr r3, [r3, #0] 800bb8a: f003 0304 and.w r3, r3, #4 800bb8e: 2b00 cmp r3, #0 800bb90: d0f0 beq.n 800bb74 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb92: f7fa f94f bl 8005e34 800bb96: 4603 mov r3, r0 800bb98: f241 0203 movw r2, #4099 @ 0x1003 800bb9c: 4293 cmp r3, r2 800bb9e: d819 bhi.n 800bbd4 800bba0: 687b ldr r3, [r7, #4] 800bba2: 691b ldr r3, [r3, #16] 800bba4: 2b40 cmp r3, #64 @ 0x40 800bba6: d108 bne.n 800bbba 800bba8: 4b09 ldr r3, [pc, #36] @ (800bbd0 ) 800bbaa: 685b ldr r3, [r3, #4] 800bbac: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800bbb0: 4a07 ldr r2, [pc, #28] @ (800bbd0 ) 800bbb2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bbb6: 6053 str r3, [r2, #4] 800bbb8: e030 b.n 800bc1c 800bbba: 4b05 ldr r3, [pc, #20] @ (800bbd0 ) 800bbbc: 685b ldr r3, [r3, #4] 800bbbe: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800bbc2: 687b ldr r3, [r7, #4] 800bbc4: 691b ldr r3, [r3, #16] 800bbc6: 031b lsls r3, r3, #12 800bbc8: 4901 ldr r1, [pc, #4] @ (800bbd0 ) 800bbca: 4313 orrs r3, r2 800bbcc: 604b str r3, [r1, #4] 800bbce: e025 b.n 800bc1c 800bbd0: 58024400 .word 0x58024400 800bbd4: 4b9a ldr r3, [pc, #616] @ (800be40 ) 800bbd6: 685b ldr r3, [r3, #4] 800bbd8: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800bbdc: 687b ldr r3, [r7, #4] 800bbde: 691b ldr r3, [r3, #16] 800bbe0: 061b lsls r3, r3, #24 800bbe2: 4997 ldr r1, [pc, #604] @ (800be40 ) 800bbe4: 4313 orrs r3, r2 800bbe6: 604b str r3, [r1, #4] 800bbe8: e018 b.n 800bc1c } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800bbea: 4b95 ldr r3, [pc, #596] @ (800be40 ) 800bbec: 681b ldr r3, [r3, #0] 800bbee: 4a94 ldr r2, [pc, #592] @ (800be40 ) 800bbf0: f023 0301 bic.w r3, r3, #1 800bbf4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bbf6: f7fa f911 bl 8005e1c 800bbfa: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800bbfc: e008 b.n 800bc10 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bbfe: f7fa f90d bl 8005e1c 800bc02: 4602 mov r2, r0 800bc04: 6a7b ldr r3, [r7, #36] @ 0x24 800bc06: 1ad3 subs r3, r2, r3 800bc08: 2b02 cmp r3, #2 800bc0a: d901 bls.n 800bc10 { return HAL_TIMEOUT; 800bc0c: 2303 movs r3, #3 800bc0e: e2ed b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800bc10: 4b8b ldr r3, [pc, #556] @ (800be40 ) 800bc12: 681b ldr r3, [r3, #0] 800bc14: f003 0304 and.w r3, r3, #4 800bc18: 2b00 cmp r3, #0 800bc1a: d1f0 bne.n 800bbfe } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800bc1c: 687b ldr r3, [r7, #4] 800bc1e: 681b ldr r3, [r3, #0] 800bc20: f003 0310 and.w r3, r3, #16 800bc24: 2b00 cmp r3, #0 800bc26: f000 80a9 beq.w 800bd7c /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800bc2a: 4b85 ldr r3, [pc, #532] @ (800be40 ) 800bc2c: 691b ldr r3, [r3, #16] 800bc2e: f003 0338 and.w r3, r3, #56 @ 0x38 800bc32: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800bc34: 4b82 ldr r3, [pc, #520] @ (800be40 ) 800bc36: 6a9b ldr r3, [r3, #40] @ 0x28 800bc38: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800bc3a: 69bb ldr r3, [r7, #24] 800bc3c: 2b08 cmp r3, #8 800bc3e: d007 beq.n 800bc50 800bc40: 69bb ldr r3, [r7, #24] 800bc42: 2b18 cmp r3, #24 800bc44: d13a bne.n 800bcbc 800bc46: 697b ldr r3, [r7, #20] 800bc48: f003 0303 and.w r3, r3, #3 800bc4c: 2b01 cmp r3, #1 800bc4e: d135 bne.n 800bcbc { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bc50: 4b7b ldr r3, [pc, #492] @ (800be40 ) 800bc52: 681b ldr r3, [r3, #0] 800bc54: f403 7380 and.w r3, r3, #256 @ 0x100 800bc58: 2b00 cmp r3, #0 800bc5a: d005 beq.n 800bc68 800bc5c: 687b ldr r3, [r7, #4] 800bc5e: 69db ldr r3, [r3, #28] 800bc60: 2b80 cmp r3, #128 @ 0x80 800bc62: d001 beq.n 800bc68 { return HAL_ERROR; 800bc64: 2301 movs r3, #1 800bc66: e2c1 b.n 800c1ec } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bc68: f7fa f8e4 bl 8005e34 800bc6c: 4603 mov r3, r0 800bc6e: f241 0203 movw r2, #4099 @ 0x1003 800bc72: 4293 cmp r3, r2 800bc74: d817 bhi.n 800bca6 800bc76: 687b ldr r3, [r7, #4] 800bc78: 6a1b ldr r3, [r3, #32] 800bc7a: 2b20 cmp r3, #32 800bc7c: d108 bne.n 800bc90 800bc7e: 4b70 ldr r3, [pc, #448] @ (800be40 ) 800bc80: 685b ldr r3, [r3, #4] 800bc82: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800bc86: 4a6e ldr r2, [pc, #440] @ (800be40 ) 800bc88: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800bc8c: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bc8e: e075 b.n 800bd7c __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bc90: 4b6b ldr r3, [pc, #428] @ (800be40 ) 800bc92: 685b ldr r3, [r3, #4] 800bc94: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800bc98: 687b ldr r3, [r7, #4] 800bc9a: 6a1b ldr r3, [r3, #32] 800bc9c: 069b lsls r3, r3, #26 800bc9e: 4968 ldr r1, [pc, #416] @ (800be40 ) 800bca0: 4313 orrs r3, r2 800bca2: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bca4: e06a b.n 800bd7c __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bca6: 4b66 ldr r3, [pc, #408] @ (800be40 ) 800bca8: 68db ldr r3, [r3, #12] 800bcaa: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800bcae: 687b ldr r3, [r7, #4] 800bcb0: 6a1b ldr r3, [r3, #32] 800bcb2: 061b lsls r3, r3, #24 800bcb4: 4962 ldr r1, [pc, #392] @ (800be40 ) 800bcb6: 4313 orrs r3, r2 800bcb8: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bcba: e05f b.n 800bd7c } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800bcbc: 687b ldr r3, [r7, #4] 800bcbe: 69db ldr r3, [r3, #28] 800bcc0: 2b00 cmp r3, #0 800bcc2: d042 beq.n 800bd4a { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800bcc4: 4b5e ldr r3, [pc, #376] @ (800be40 ) 800bcc6: 681b ldr r3, [r3, #0] 800bcc8: 4a5d ldr r2, [pc, #372] @ (800be40 ) 800bcca: f043 0380 orr.w r3, r3, #128 @ 0x80 800bcce: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bcd0: f7fa f8a4 bl 8005e1c 800bcd4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bcd6: e008 b.n 800bcea { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800bcd8: f7fa f8a0 bl 8005e1c 800bcdc: 4602 mov r2, r0 800bcde: 6a7b ldr r3, [r7, #36] @ 0x24 800bce0: 1ad3 subs r3, r2, r3 800bce2: 2b02 cmp r3, #2 800bce4: d901 bls.n 800bcea { return HAL_TIMEOUT; 800bce6: 2303 movs r3, #3 800bce8: e280 b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bcea: 4b55 ldr r3, [pc, #340] @ (800be40 ) 800bcec: 681b ldr r3, [r3, #0] 800bcee: f403 7380 and.w r3, r3, #256 @ 0x100 800bcf2: 2b00 cmp r3, #0 800bcf4: d0f0 beq.n 800bcd8 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bcf6: f7fa f89d bl 8005e34 800bcfa: 4603 mov r3, r0 800bcfc: f241 0203 movw r2, #4099 @ 0x1003 800bd00: 4293 cmp r3, r2 800bd02: d817 bhi.n 800bd34 800bd04: 687b ldr r3, [r7, #4] 800bd06: 6a1b ldr r3, [r3, #32] 800bd08: 2b20 cmp r3, #32 800bd0a: d108 bne.n 800bd1e 800bd0c: 4b4c ldr r3, [pc, #304] @ (800be40 ) 800bd0e: 685b ldr r3, [r3, #4] 800bd10: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800bd14: 4a4a ldr r2, [pc, #296] @ (800be40 ) 800bd16: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800bd1a: 6053 str r3, [r2, #4] 800bd1c: e02e b.n 800bd7c 800bd1e: 4b48 ldr r3, [pc, #288] @ (800be40 ) 800bd20: 685b ldr r3, [r3, #4] 800bd22: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800bd26: 687b ldr r3, [r7, #4] 800bd28: 6a1b ldr r3, [r3, #32] 800bd2a: 069b lsls r3, r3, #26 800bd2c: 4944 ldr r1, [pc, #272] @ (800be40 ) 800bd2e: 4313 orrs r3, r2 800bd30: 604b str r3, [r1, #4] 800bd32: e023 b.n 800bd7c 800bd34: 4b42 ldr r3, [pc, #264] @ (800be40 ) 800bd36: 68db ldr r3, [r3, #12] 800bd38: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800bd3c: 687b ldr r3, [r7, #4] 800bd3e: 6a1b ldr r3, [r3, #32] 800bd40: 061b lsls r3, r3, #24 800bd42: 493f ldr r1, [pc, #252] @ (800be40 ) 800bd44: 4313 orrs r3, r2 800bd46: 60cb str r3, [r1, #12] 800bd48: e018 b.n 800bd7c } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800bd4a: 4b3d ldr r3, [pc, #244] @ (800be40 ) 800bd4c: 681b ldr r3, [r3, #0] 800bd4e: 4a3c ldr r2, [pc, #240] @ (800be40 ) 800bd50: f023 0380 bic.w r3, r3, #128 @ 0x80 800bd54: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd56: f7fa f861 bl 8005e1c 800bd5a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800bd5c: e008 b.n 800bd70 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800bd5e: f7fa f85d bl 8005e1c 800bd62: 4602 mov r2, r0 800bd64: 6a7b ldr r3, [r7, #36] @ 0x24 800bd66: 1ad3 subs r3, r2, r3 800bd68: 2b02 cmp r3, #2 800bd6a: d901 bls.n 800bd70 { return HAL_TIMEOUT; 800bd6c: 2303 movs r3, #3 800bd6e: e23d b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800bd70: 4b33 ldr r3, [pc, #204] @ (800be40 ) 800bd72: 681b ldr r3, [r3, #0] 800bd74: f403 7380 and.w r3, r3, #256 @ 0x100 800bd78: 2b00 cmp r3, #0 800bd7a: d1f0 bne.n 800bd5e } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800bd7c: 687b ldr r3, [r7, #4] 800bd7e: 681b ldr r3, [r3, #0] 800bd80: f003 0308 and.w r3, r3, #8 800bd84: 2b00 cmp r3, #0 800bd86: d036 beq.n 800bdf6 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800bd88: 687b ldr r3, [r7, #4] 800bd8a: 695b ldr r3, [r3, #20] 800bd8c: 2b00 cmp r3, #0 800bd8e: d019 beq.n 800bdc4 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800bd90: 4b2b ldr r3, [pc, #172] @ (800be40 ) 800bd92: 6f5b ldr r3, [r3, #116] @ 0x74 800bd94: 4a2a ldr r2, [pc, #168] @ (800be40 ) 800bd96: f043 0301 orr.w r3, r3, #1 800bd9a: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd9c: f7fa f83e bl 8005e1c 800bda0: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800bda2: e008 b.n 800bdb6 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800bda4: f7fa f83a bl 8005e1c 800bda8: 4602 mov r2, r0 800bdaa: 6a7b ldr r3, [r7, #36] @ 0x24 800bdac: 1ad3 subs r3, r2, r3 800bdae: 2b02 cmp r3, #2 800bdb0: d901 bls.n 800bdb6 { return HAL_TIMEOUT; 800bdb2: 2303 movs r3, #3 800bdb4: e21a b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800bdb6: 4b22 ldr r3, [pc, #136] @ (800be40 ) 800bdb8: 6f5b ldr r3, [r3, #116] @ 0x74 800bdba: f003 0302 and.w r3, r3, #2 800bdbe: 2b00 cmp r3, #0 800bdc0: d0f0 beq.n 800bda4 800bdc2: e018 b.n 800bdf6 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800bdc4: 4b1e ldr r3, [pc, #120] @ (800be40 ) 800bdc6: 6f5b ldr r3, [r3, #116] @ 0x74 800bdc8: 4a1d ldr r2, [pc, #116] @ (800be40 ) 800bdca: f023 0301 bic.w r3, r3, #1 800bdce: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bdd0: f7fa f824 bl 8005e1c 800bdd4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800bdd6: e008 b.n 800bdea { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800bdd8: f7fa f820 bl 8005e1c 800bddc: 4602 mov r2, r0 800bdde: 6a7b ldr r3, [r7, #36] @ 0x24 800bde0: 1ad3 subs r3, r2, r3 800bde2: 2b02 cmp r3, #2 800bde4: d901 bls.n 800bdea { return HAL_TIMEOUT; 800bde6: 2303 movs r3, #3 800bde8: e200 b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800bdea: 4b15 ldr r3, [pc, #84] @ (800be40 ) 800bdec: 6f5b ldr r3, [r3, #116] @ 0x74 800bdee: f003 0302 and.w r3, r3, #2 800bdf2: 2b00 cmp r3, #0 800bdf4: d1f0 bne.n 800bdd8 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800bdf6: 687b ldr r3, [r7, #4] 800bdf8: 681b ldr r3, [r3, #0] 800bdfa: f003 0320 and.w r3, r3, #32 800bdfe: 2b00 cmp r3, #0 800be00: d039 beq.n 800be76 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 800be02: 687b ldr r3, [r7, #4] 800be04: 699b ldr r3, [r3, #24] 800be06: 2b00 cmp r3, #0 800be08: d01c beq.n 800be44 { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800be0a: 4b0d ldr r3, [pc, #52] @ (800be40 ) 800be0c: 681b ldr r3, [r3, #0] 800be0e: 4a0c ldr r2, [pc, #48] @ (800be40 ) 800be10: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800be14: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800be16: f7fa f801 bl 8005e1c 800be1a: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800be1c: e008 b.n 800be30 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800be1e: f7f9 fffd bl 8005e1c 800be22: 4602 mov r2, r0 800be24: 6a7b ldr r3, [r7, #36] @ 0x24 800be26: 1ad3 subs r3, r2, r3 800be28: 2b02 cmp r3, #2 800be2a: d901 bls.n 800be30 { return HAL_TIMEOUT; 800be2c: 2303 movs r3, #3 800be2e: e1dd b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800be30: 4b03 ldr r3, [pc, #12] @ (800be40 ) 800be32: 681b ldr r3, [r3, #0] 800be34: f403 5300 and.w r3, r3, #8192 @ 0x2000 800be38: 2b00 cmp r3, #0 800be3a: d0f0 beq.n 800be1e 800be3c: e01b b.n 800be76 800be3e: bf00 nop 800be40: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800be44: 4b9b ldr r3, [pc, #620] @ (800c0b4 ) 800be46: 681b ldr r3, [r3, #0] 800be48: 4a9a ldr r2, [pc, #616] @ (800c0b4 ) 800be4a: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800be4e: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800be50: f7f9 ffe4 bl 8005e1c 800be54: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800be56: e008 b.n 800be6a { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800be58: f7f9 ffe0 bl 8005e1c 800be5c: 4602 mov r2, r0 800be5e: 6a7b ldr r3, [r7, #36] @ 0x24 800be60: 1ad3 subs r3, r2, r3 800be62: 2b02 cmp r3, #2 800be64: d901 bls.n 800be6a { return HAL_TIMEOUT; 800be66: 2303 movs r3, #3 800be68: e1c0 b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800be6a: 4b92 ldr r3, [pc, #584] @ (800c0b4 ) 800be6c: 681b ldr r3, [r3, #0] 800be6e: f403 5300 and.w r3, r3, #8192 @ 0x2000 800be72: 2b00 cmp r3, #0 800be74: d1f0 bne.n 800be58 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800be76: 687b ldr r3, [r7, #4] 800be78: 681b ldr r3, [r3, #0] 800be7a: f003 0304 and.w r3, r3, #4 800be7e: 2b00 cmp r3, #0 800be80: f000 8081 beq.w 800bf86 { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 800be84: 4b8c ldr r3, [pc, #560] @ (800c0b8 ) 800be86: 681b ldr r3, [r3, #0] 800be88: 4a8b ldr r2, [pc, #556] @ (800c0b8 ) 800be8a: f443 7380 orr.w r3, r3, #256 @ 0x100 800be8e: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800be90: f7f9 ffc4 bl 8005e1c 800be94: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800be96: e008 b.n 800beaa { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800be98: f7f9 ffc0 bl 8005e1c 800be9c: 4602 mov r2, r0 800be9e: 6a7b ldr r3, [r7, #36] @ 0x24 800bea0: 1ad3 subs r3, r2, r3 800bea2: 2b64 cmp r3, #100 @ 0x64 800bea4: d901 bls.n 800beaa { return HAL_TIMEOUT; 800bea6: 2303 movs r3, #3 800bea8: e1a0 b.n 800c1ec while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800beaa: 4b83 ldr r3, [pc, #524] @ (800c0b8 ) 800beac: 681b ldr r3, [r3, #0] 800beae: f403 7380 and.w r3, r3, #256 @ 0x100 800beb2: 2b00 cmp r3, #0 800beb4: d0f0 beq.n 800be98 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800beb6: 687b ldr r3, [r7, #4] 800beb8: 689b ldr r3, [r3, #8] 800beba: 2b01 cmp r3, #1 800bebc: d106 bne.n 800becc 800bebe: 4b7d ldr r3, [pc, #500] @ (800c0b4 ) 800bec0: 6f1b ldr r3, [r3, #112] @ 0x70 800bec2: 4a7c ldr r2, [pc, #496] @ (800c0b4 ) 800bec4: f043 0301 orr.w r3, r3, #1 800bec8: 6713 str r3, [r2, #112] @ 0x70 800beca: e02d b.n 800bf28 800becc: 687b ldr r3, [r7, #4] 800bece: 689b ldr r3, [r3, #8] 800bed0: 2b00 cmp r3, #0 800bed2: d10c bne.n 800beee 800bed4: 4b77 ldr r3, [pc, #476] @ (800c0b4 ) 800bed6: 6f1b ldr r3, [r3, #112] @ 0x70 800bed8: 4a76 ldr r2, [pc, #472] @ (800c0b4 ) 800beda: f023 0301 bic.w r3, r3, #1 800bede: 6713 str r3, [r2, #112] @ 0x70 800bee0: 4b74 ldr r3, [pc, #464] @ (800c0b4 ) 800bee2: 6f1b ldr r3, [r3, #112] @ 0x70 800bee4: 4a73 ldr r2, [pc, #460] @ (800c0b4 ) 800bee6: f023 0304 bic.w r3, r3, #4 800beea: 6713 str r3, [r2, #112] @ 0x70 800beec: e01c b.n 800bf28 800beee: 687b ldr r3, [r7, #4] 800bef0: 689b ldr r3, [r3, #8] 800bef2: 2b05 cmp r3, #5 800bef4: d10c bne.n 800bf10 800bef6: 4b6f ldr r3, [pc, #444] @ (800c0b4 ) 800bef8: 6f1b ldr r3, [r3, #112] @ 0x70 800befa: 4a6e ldr r2, [pc, #440] @ (800c0b4 ) 800befc: f043 0304 orr.w r3, r3, #4 800bf00: 6713 str r3, [r2, #112] @ 0x70 800bf02: 4b6c ldr r3, [pc, #432] @ (800c0b4 ) 800bf04: 6f1b ldr r3, [r3, #112] @ 0x70 800bf06: 4a6b ldr r2, [pc, #428] @ (800c0b4 ) 800bf08: f043 0301 orr.w r3, r3, #1 800bf0c: 6713 str r3, [r2, #112] @ 0x70 800bf0e: e00b b.n 800bf28 800bf10: 4b68 ldr r3, [pc, #416] @ (800c0b4 ) 800bf12: 6f1b ldr r3, [r3, #112] @ 0x70 800bf14: 4a67 ldr r2, [pc, #412] @ (800c0b4 ) 800bf16: f023 0301 bic.w r3, r3, #1 800bf1a: 6713 str r3, [r2, #112] @ 0x70 800bf1c: 4b65 ldr r3, [pc, #404] @ (800c0b4 ) 800bf1e: 6f1b ldr r3, [r3, #112] @ 0x70 800bf20: 4a64 ldr r2, [pc, #400] @ (800c0b4 ) 800bf22: f023 0304 bic.w r3, r3, #4 800bf26: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800bf28: 687b ldr r3, [r7, #4] 800bf2a: 689b ldr r3, [r3, #8] 800bf2c: 2b00 cmp r3, #0 800bf2e: d015 beq.n 800bf5c { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf30: f7f9 ff74 bl 8005e1c 800bf34: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bf36: e00a b.n 800bf4e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bf38: f7f9 ff70 bl 8005e1c 800bf3c: 4602 mov r2, r0 800bf3e: 6a7b ldr r3, [r7, #36] @ 0x24 800bf40: 1ad3 subs r3, r2, r3 800bf42: f241 3288 movw r2, #5000 @ 0x1388 800bf46: 4293 cmp r3, r2 800bf48: d901 bls.n 800bf4e { return HAL_TIMEOUT; 800bf4a: 2303 movs r3, #3 800bf4c: e14e b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bf4e: 4b59 ldr r3, [pc, #356] @ (800c0b4 ) 800bf50: 6f1b ldr r3, [r3, #112] @ 0x70 800bf52: f003 0302 and.w r3, r3, #2 800bf56: 2b00 cmp r3, #0 800bf58: d0ee beq.n 800bf38 800bf5a: e014 b.n 800bf86 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf5c: f7f9 ff5e bl 8005e1c 800bf60: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bf62: e00a b.n 800bf7a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bf64: f7f9 ff5a bl 8005e1c 800bf68: 4602 mov r2, r0 800bf6a: 6a7b ldr r3, [r7, #36] @ 0x24 800bf6c: 1ad3 subs r3, r2, r3 800bf6e: f241 3288 movw r2, #5000 @ 0x1388 800bf72: 4293 cmp r3, r2 800bf74: d901 bls.n 800bf7a { return HAL_TIMEOUT; 800bf76: 2303 movs r3, #3 800bf78: e138 b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bf7a: 4b4e ldr r3, [pc, #312] @ (800c0b4 ) 800bf7c: 6f1b ldr r3, [r3, #112] @ 0x70 800bf7e: f003 0302 and.w r3, r3, #2 800bf82: 2b00 cmp r3, #0 800bf84: d1ee bne.n 800bf64 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800bf86: 687b ldr r3, [r7, #4] 800bf88: 6a5b ldr r3, [r3, #36] @ 0x24 800bf8a: 2b00 cmp r3, #0 800bf8c: f000 812d beq.w 800c1ea { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800bf90: 4b48 ldr r3, [pc, #288] @ (800c0b4 ) 800bf92: 691b ldr r3, [r3, #16] 800bf94: f003 0338 and.w r3, r3, #56 @ 0x38 800bf98: 2b18 cmp r3, #24 800bf9a: f000 80bd beq.w 800c118 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800bf9e: 687b ldr r3, [r7, #4] 800bfa0: 6a5b ldr r3, [r3, #36] @ 0x24 800bfa2: 2b02 cmp r3, #2 800bfa4: f040 809e bne.w 800c0e4 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bfa8: 4b42 ldr r3, [pc, #264] @ (800c0b4 ) 800bfaa: 681b ldr r3, [r3, #0] 800bfac: 4a41 ldr r2, [pc, #260] @ (800c0b4 ) 800bfae: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800bfb2: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bfb4: f7f9 ff32 bl 8005e1c 800bfb8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bfba: e008 b.n 800bfce { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bfbc: f7f9 ff2e bl 8005e1c 800bfc0: 4602 mov r2, r0 800bfc2: 6a7b ldr r3, [r7, #36] @ 0x24 800bfc4: 1ad3 subs r3, r2, r3 800bfc6: 2b02 cmp r3, #2 800bfc8: d901 bls.n 800bfce { return HAL_TIMEOUT; 800bfca: 2303 movs r3, #3 800bfcc: e10e b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bfce: 4b39 ldr r3, [pc, #228] @ (800c0b4 ) 800bfd0: 681b ldr r3, [r3, #0] 800bfd2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bfd6: 2b00 cmp r3, #0 800bfd8: d1f0 bne.n 800bfbc } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800bfda: 4b36 ldr r3, [pc, #216] @ (800c0b4 ) 800bfdc: 6a9a ldr r2, [r3, #40] @ 0x28 800bfde: 4b37 ldr r3, [pc, #220] @ (800c0bc ) 800bfe0: 4013 ands r3, r2 800bfe2: 687a ldr r2, [r7, #4] 800bfe4: 6a91 ldr r1, [r2, #40] @ 0x28 800bfe6: 687a ldr r2, [r7, #4] 800bfe8: 6ad2 ldr r2, [r2, #44] @ 0x2c 800bfea: 0112 lsls r2, r2, #4 800bfec: 430a orrs r2, r1 800bfee: 4931 ldr r1, [pc, #196] @ (800c0b4 ) 800bff0: 4313 orrs r3, r2 800bff2: 628b str r3, [r1, #40] @ 0x28 800bff4: 687b ldr r3, [r7, #4] 800bff6: 6b1b ldr r3, [r3, #48] @ 0x30 800bff8: 3b01 subs r3, #1 800bffa: f3c3 0208 ubfx r2, r3, #0, #9 800bffe: 687b ldr r3, [r7, #4] 800c000: 6b5b ldr r3, [r3, #52] @ 0x34 800c002: 3b01 subs r3, #1 800c004: 025b lsls r3, r3, #9 800c006: b29b uxth r3, r3 800c008: 431a orrs r2, r3 800c00a: 687b ldr r3, [r7, #4] 800c00c: 6b9b ldr r3, [r3, #56] @ 0x38 800c00e: 3b01 subs r3, #1 800c010: 041b lsls r3, r3, #16 800c012: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800c016: 431a orrs r2, r3 800c018: 687b ldr r3, [r7, #4] 800c01a: 6bdb ldr r3, [r3, #60] @ 0x3c 800c01c: 3b01 subs r3, #1 800c01e: 061b lsls r3, r3, #24 800c020: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800c024: 4923 ldr r1, [pc, #140] @ (800c0b4 ) 800c026: 4313 orrs r3, r2 800c028: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800c02a: 4b22 ldr r3, [pc, #136] @ (800c0b4 ) 800c02c: 6adb ldr r3, [r3, #44] @ 0x2c 800c02e: 4a21 ldr r2, [pc, #132] @ (800c0b4 ) 800c030: f023 0301 bic.w r3, r3, #1 800c034: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800c036: 4b1f ldr r3, [pc, #124] @ (800c0b4 ) 800c038: 6b5a ldr r2, [r3, #52] @ 0x34 800c03a: 4b21 ldr r3, [pc, #132] @ (800c0c0 ) 800c03c: 4013 ands r3, r2 800c03e: 687a ldr r2, [r7, #4] 800c040: 6c92 ldr r2, [r2, #72] @ 0x48 800c042: 00d2 lsls r2, r2, #3 800c044: 491b ldr r1, [pc, #108] @ (800c0b4 ) 800c046: 4313 orrs r3, r2 800c048: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800c04a: 4b1a ldr r3, [pc, #104] @ (800c0b4 ) 800c04c: 6adb ldr r3, [r3, #44] @ 0x2c 800c04e: f023 020c bic.w r2, r3, #12 800c052: 687b ldr r3, [r7, #4] 800c054: 6c1b ldr r3, [r3, #64] @ 0x40 800c056: 4917 ldr r1, [pc, #92] @ (800c0b4 ) 800c058: 4313 orrs r3, r2 800c05a: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800c05c: 4b15 ldr r3, [pc, #84] @ (800c0b4 ) 800c05e: 6adb ldr r3, [r3, #44] @ 0x2c 800c060: f023 0202 bic.w r2, r3, #2 800c064: 687b ldr r3, [r7, #4] 800c066: 6c5b ldr r3, [r3, #68] @ 0x44 800c068: 4912 ldr r1, [pc, #72] @ (800c0b4 ) 800c06a: 4313 orrs r3, r2 800c06c: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800c06e: 4b11 ldr r3, [pc, #68] @ (800c0b4 ) 800c070: 6adb ldr r3, [r3, #44] @ 0x2c 800c072: 4a10 ldr r2, [pc, #64] @ (800c0b4 ) 800c074: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c078: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c07a: 4b0e ldr r3, [pc, #56] @ (800c0b4 ) 800c07c: 6adb ldr r3, [r3, #44] @ 0x2c 800c07e: 4a0d ldr r2, [pc, #52] @ (800c0b4 ) 800c080: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c084: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800c086: 4b0b ldr r3, [pc, #44] @ (800c0b4 ) 800c088: 6adb ldr r3, [r3, #44] @ 0x2c 800c08a: 4a0a ldr r2, [pc, #40] @ (800c0b4 ) 800c08c: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800c090: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800c092: 4b08 ldr r3, [pc, #32] @ (800c0b4 ) 800c094: 6adb ldr r3, [r3, #44] @ 0x2c 800c096: 4a07 ldr r2, [pc, #28] @ (800c0b4 ) 800c098: f043 0301 orr.w r3, r3, #1 800c09c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800c09e: 4b05 ldr r3, [pc, #20] @ (800c0b4 ) 800c0a0: 681b ldr r3, [r3, #0] 800c0a2: 4a04 ldr r2, [pc, #16] @ (800c0b4 ) 800c0a4: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800c0a8: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c0aa: f7f9 feb7 bl 8005e1c 800c0ae: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c0b0: e011 b.n 800c0d6 800c0b2: bf00 nop 800c0b4: 58024400 .word 0x58024400 800c0b8: 58024800 .word 0x58024800 800c0bc: fffffc0c .word 0xfffffc0c 800c0c0: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c0c4: f7f9 feaa bl 8005e1c 800c0c8: 4602 mov r2, r0 800c0ca: 6a7b ldr r3, [r7, #36] @ 0x24 800c0cc: 1ad3 subs r3, r2, r3 800c0ce: 2b02 cmp r3, #2 800c0d0: d901 bls.n 800c0d6 { return HAL_TIMEOUT; 800c0d2: 2303 movs r3, #3 800c0d4: e08a b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c0d6: 4b47 ldr r3, [pc, #284] @ (800c1f4 ) 800c0d8: 681b ldr r3, [r3, #0] 800c0da: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c0de: 2b00 cmp r3, #0 800c0e0: d0f0 beq.n 800c0c4 800c0e2: e082 b.n 800c1ea } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800c0e4: 4b43 ldr r3, [pc, #268] @ (800c1f4 ) 800c0e6: 681b ldr r3, [r3, #0] 800c0e8: 4a42 ldr r2, [pc, #264] @ (800c1f4 ) 800c0ea: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800c0ee: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c0f0: f7f9 fe94 bl 8005e1c 800c0f4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c0f6: e008 b.n 800c10a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c0f8: f7f9 fe90 bl 8005e1c 800c0fc: 4602 mov r2, r0 800c0fe: 6a7b ldr r3, [r7, #36] @ 0x24 800c100: 1ad3 subs r3, r2, r3 800c102: 2b02 cmp r3, #2 800c104: d901 bls.n 800c10a { return HAL_TIMEOUT; 800c106: 2303 movs r3, #3 800c108: e070 b.n 800c1ec while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c10a: 4b3a ldr r3, [pc, #232] @ (800c1f4 ) 800c10c: 681b ldr r3, [r3, #0] 800c10e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c112: 2b00 cmp r3, #0 800c114: d1f0 bne.n 800c0f8 800c116: e068 b.n 800c1ea } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800c118: 4b36 ldr r3, [pc, #216] @ (800c1f4 ) 800c11a: 6a9b ldr r3, [r3, #40] @ 0x28 800c11c: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800c11e: 4b35 ldr r3, [pc, #212] @ (800c1f4 ) 800c120: 6b1b ldr r3, [r3, #48] @ 0x30 800c122: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800c124: 687b ldr r3, [r7, #4] 800c126: 6a5b ldr r3, [r3, #36] @ 0x24 800c128: 2b01 cmp r3, #1 800c12a: d031 beq.n 800c190 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800c12c: 693b ldr r3, [r7, #16] 800c12e: f003 0203 and.w r2, r3, #3 800c132: 687b ldr r3, [r7, #4] 800c134: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800c136: 429a cmp r2, r3 800c138: d12a bne.n 800c190 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800c13a: 693b ldr r3, [r7, #16] 800c13c: 091b lsrs r3, r3, #4 800c13e: f003 023f and.w r2, r3, #63 @ 0x3f 800c142: 687b ldr r3, [r7, #4] 800c144: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800c146: 429a cmp r2, r3 800c148: d122 bne.n 800c190 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800c14a: 68fb ldr r3, [r7, #12] 800c14c: f3c3 0208 ubfx r2, r3, #0, #9 800c150: 687b ldr r3, [r7, #4] 800c152: 6b1b ldr r3, [r3, #48] @ 0x30 800c154: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800c156: 429a cmp r2, r3 800c158: d11a bne.n 800c190 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800c15a: 68fb ldr r3, [r7, #12] 800c15c: 0a5b lsrs r3, r3, #9 800c15e: f003 027f and.w r2, r3, #127 @ 0x7f 800c162: 687b ldr r3, [r7, #4] 800c164: 6b5b ldr r3, [r3, #52] @ 0x34 800c166: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800c168: 429a cmp r2, r3 800c16a: d111 bne.n 800c190 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800c16c: 68fb ldr r3, [r7, #12] 800c16e: 0c1b lsrs r3, r3, #16 800c170: f003 027f and.w r2, r3, #127 @ 0x7f 800c174: 687b ldr r3, [r7, #4] 800c176: 6b9b ldr r3, [r3, #56] @ 0x38 800c178: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800c17a: 429a cmp r2, r3 800c17c: d108 bne.n 800c190 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800c17e: 68fb ldr r3, [r7, #12] 800c180: 0e1b lsrs r3, r3, #24 800c182: f003 027f and.w r2, r3, #127 @ 0x7f 800c186: 687b ldr r3, [r7, #4] 800c188: 6bdb ldr r3, [r3, #60] @ 0x3c 800c18a: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800c18c: 429a cmp r2, r3 800c18e: d001 beq.n 800c194 { return HAL_ERROR; 800c190: 2301 movs r3, #1 800c192: e02b b.n 800c1ec } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 800c194: 4b17 ldr r3, [pc, #92] @ (800c1f4 ) 800c196: 6b5b ldr r3, [r3, #52] @ 0x34 800c198: 08db lsrs r3, r3, #3 800c19a: f3c3 030c ubfx r3, r3, #0, #13 800c19e: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 800c1a0: 687b ldr r3, [r7, #4] 800c1a2: 6c9b ldr r3, [r3, #72] @ 0x48 800c1a4: 693a ldr r2, [r7, #16] 800c1a6: 429a cmp r2, r3 800c1a8: d01f beq.n 800c1ea { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800c1aa: 4b12 ldr r3, [pc, #72] @ (800c1f4 ) 800c1ac: 6adb ldr r3, [r3, #44] @ 0x2c 800c1ae: 4a11 ldr r2, [pc, #68] @ (800c1f4 ) 800c1b0: f023 0301 bic.w r3, r3, #1 800c1b4: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c1b6: f7f9 fe31 bl 8005e1c 800c1ba: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 800c1bc: bf00 nop 800c1be: f7f9 fe2d bl 8005e1c 800c1c2: 4602 mov r2, r0 800c1c4: 6a7b ldr r3, [r7, #36] @ 0x24 800c1c6: 4293 cmp r3, r2 800c1c8: d0f9 beq.n 800c1be { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800c1ca: 4b0a ldr r3, [pc, #40] @ (800c1f4 ) 800c1cc: 6b5a ldr r2, [r3, #52] @ 0x34 800c1ce: 4b0a ldr r3, [pc, #40] @ (800c1f8 ) 800c1d0: 4013 ands r3, r2 800c1d2: 687a ldr r2, [r7, #4] 800c1d4: 6c92 ldr r2, [r2, #72] @ 0x48 800c1d6: 00d2 lsls r2, r2, #3 800c1d8: 4906 ldr r1, [pc, #24] @ (800c1f4 ) 800c1da: 4313 orrs r3, r2 800c1dc: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 800c1de: 4b05 ldr r3, [pc, #20] @ (800c1f4 ) 800c1e0: 6adb ldr r3, [r3, #44] @ 0x2c 800c1e2: 4a04 ldr r2, [pc, #16] @ (800c1f4 ) 800c1e4: f043 0301 orr.w r3, r3, #1 800c1e8: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800c1ea: 2300 movs r3, #0 } 800c1ec: 4618 mov r0, r3 800c1ee: 3730 adds r7, #48 @ 0x30 800c1f0: 46bd mov sp, r7 800c1f2: bd80 pop {r7, pc} 800c1f4: 58024400 .word 0x58024400 800c1f8: ffff0007 .word 0xffff0007 0800c1fc : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800c1fc: b580 push {r7, lr} 800c1fe: b086 sub sp, #24 800c200: af00 add r7, sp, #0 800c202: 6078 str r0, [r7, #4] 800c204: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800c206: 687b ldr r3, [r7, #4] 800c208: 2b00 cmp r3, #0 800c20a: d101 bne.n 800c210 { return HAL_ERROR; 800c20c: 2301 movs r3, #1 800c20e: e19c b.n 800c54a /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800c210: 4b8a ldr r3, [pc, #552] @ (800c43c ) 800c212: 681b ldr r3, [r3, #0] 800c214: f003 030f and.w r3, r3, #15 800c218: 683a ldr r2, [r7, #0] 800c21a: 429a cmp r2, r3 800c21c: d910 bls.n 800c240 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c21e: 4b87 ldr r3, [pc, #540] @ (800c43c ) 800c220: 681b ldr r3, [r3, #0] 800c222: f023 020f bic.w r2, r3, #15 800c226: 4985 ldr r1, [pc, #532] @ (800c43c ) 800c228: 683b ldr r3, [r7, #0] 800c22a: 4313 orrs r3, r2 800c22c: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c22e: 4b83 ldr r3, [pc, #524] @ (800c43c ) 800c230: 681b ldr r3, [r3, #0] 800c232: f003 030f and.w r3, r3, #15 800c236: 683a ldr r2, [r7, #0] 800c238: 429a cmp r2, r3 800c23a: d001 beq.n 800c240 { return HAL_ERROR; 800c23c: 2301 movs r3, #1 800c23e: e184 b.n 800c54a } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c240: 687b ldr r3, [r7, #4] 800c242: 681b ldr r3, [r3, #0] 800c244: f003 0304 and.w r3, r3, #4 800c248: 2b00 cmp r3, #0 800c24a: d010 beq.n 800c26e { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c24c: 687b ldr r3, [r7, #4] 800c24e: 691a ldr r2, [r3, #16] 800c250: 4b7b ldr r3, [pc, #492] @ (800c440 ) 800c252: 699b ldr r3, [r3, #24] 800c254: f003 0370 and.w r3, r3, #112 @ 0x70 800c258: 429a cmp r2, r3 800c25a: d908 bls.n 800c26e { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c25c: 4b78 ldr r3, [pc, #480] @ (800c440 ) 800c25e: 699b ldr r3, [r3, #24] 800c260: f023 0270 bic.w r2, r3, #112 @ 0x70 800c264: 687b ldr r3, [r7, #4] 800c266: 691b ldr r3, [r3, #16] 800c268: 4975 ldr r1, [pc, #468] @ (800c440 ) 800c26a: 4313 orrs r3, r2 800c26c: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c26e: 687b ldr r3, [r7, #4] 800c270: 681b ldr r3, [r3, #0] 800c272: f003 0308 and.w r3, r3, #8 800c276: 2b00 cmp r3, #0 800c278: d010 beq.n 800c29c { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c27a: 687b ldr r3, [r7, #4] 800c27c: 695a ldr r2, [r3, #20] 800c27e: 4b70 ldr r3, [pc, #448] @ (800c440 ) 800c280: 69db ldr r3, [r3, #28] 800c282: f003 0370 and.w r3, r3, #112 @ 0x70 800c286: 429a cmp r2, r3 800c288: d908 bls.n 800c29c { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c28a: 4b6d ldr r3, [pc, #436] @ (800c440 ) 800c28c: 69db ldr r3, [r3, #28] 800c28e: f023 0270 bic.w r2, r3, #112 @ 0x70 800c292: 687b ldr r3, [r7, #4] 800c294: 695b ldr r3, [r3, #20] 800c296: 496a ldr r1, [pc, #424] @ (800c440 ) 800c298: 4313 orrs r3, r2 800c29a: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c29c: 687b ldr r3, [r7, #4] 800c29e: 681b ldr r3, [r3, #0] 800c2a0: f003 0310 and.w r3, r3, #16 800c2a4: 2b00 cmp r3, #0 800c2a6: d010 beq.n 800c2ca { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c2a8: 687b ldr r3, [r7, #4] 800c2aa: 699a ldr r2, [r3, #24] 800c2ac: 4b64 ldr r3, [pc, #400] @ (800c440 ) 800c2ae: 69db ldr r3, [r3, #28] 800c2b0: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c2b4: 429a cmp r2, r3 800c2b6: d908 bls.n 800c2ca { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c2b8: 4b61 ldr r3, [pc, #388] @ (800c440 ) 800c2ba: 69db ldr r3, [r3, #28] 800c2bc: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c2c0: 687b ldr r3, [r7, #4] 800c2c2: 699b ldr r3, [r3, #24] 800c2c4: 495e ldr r1, [pc, #376] @ (800c440 ) 800c2c6: 4313 orrs r3, r2 800c2c8: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c2ca: 687b ldr r3, [r7, #4] 800c2cc: 681b ldr r3, [r3, #0] 800c2ce: f003 0320 and.w r3, r3, #32 800c2d2: 2b00 cmp r3, #0 800c2d4: d010 beq.n 800c2f8 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c2d6: 687b ldr r3, [r7, #4] 800c2d8: 69da ldr r2, [r3, #28] 800c2da: 4b59 ldr r3, [pc, #356] @ (800c440 ) 800c2dc: 6a1b ldr r3, [r3, #32] 800c2de: f003 0370 and.w r3, r3, #112 @ 0x70 800c2e2: 429a cmp r2, r3 800c2e4: d908 bls.n 800c2f8 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c2e6: 4b56 ldr r3, [pc, #344] @ (800c440 ) 800c2e8: 6a1b ldr r3, [r3, #32] 800c2ea: f023 0270 bic.w r2, r3, #112 @ 0x70 800c2ee: 687b ldr r3, [r7, #4] 800c2f0: 69db ldr r3, [r3, #28] 800c2f2: 4953 ldr r1, [pc, #332] @ (800c440 ) 800c2f4: 4313 orrs r3, r2 800c2f6: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c2f8: 687b ldr r3, [r7, #4] 800c2fa: 681b ldr r3, [r3, #0] 800c2fc: f003 0302 and.w r3, r3, #2 800c300: 2b00 cmp r3, #0 800c302: d010 beq.n 800c326 { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c304: 687b ldr r3, [r7, #4] 800c306: 68da ldr r2, [r3, #12] 800c308: 4b4d ldr r3, [pc, #308] @ (800c440 ) 800c30a: 699b ldr r3, [r3, #24] 800c30c: f003 030f and.w r3, r3, #15 800c310: 429a cmp r2, r3 800c312: d908 bls.n 800c326 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c314: 4b4a ldr r3, [pc, #296] @ (800c440 ) 800c316: 699b ldr r3, [r3, #24] 800c318: f023 020f bic.w r2, r3, #15 800c31c: 687b ldr r3, [r7, #4] 800c31e: 68db ldr r3, [r3, #12] 800c320: 4947 ldr r1, [pc, #284] @ (800c440 ) 800c322: 4313 orrs r3, r2 800c324: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800c326: 687b ldr r3, [r7, #4] 800c328: 681b ldr r3, [r3, #0] 800c32a: f003 0301 and.w r3, r3, #1 800c32e: 2b00 cmp r3, #0 800c330: d055 beq.n 800c3de { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800c332: 4b43 ldr r3, [pc, #268] @ (800c440 ) 800c334: 699b ldr r3, [r3, #24] 800c336: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800c33a: 687b ldr r3, [r7, #4] 800c33c: 689b ldr r3, [r3, #8] 800c33e: 4940 ldr r1, [pc, #256] @ (800c440 ) 800c340: 4313 orrs r3, r2 800c342: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800c344: 687b ldr r3, [r7, #4] 800c346: 685b ldr r3, [r3, #4] 800c348: 2b02 cmp r3, #2 800c34a: d107 bne.n 800c35c { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800c34c: 4b3c ldr r3, [pc, #240] @ (800c440 ) 800c34e: 681b ldr r3, [r3, #0] 800c350: f403 3300 and.w r3, r3, #131072 @ 0x20000 800c354: 2b00 cmp r3, #0 800c356: d121 bne.n 800c39c { return HAL_ERROR; 800c358: 2301 movs r3, #1 800c35a: e0f6 b.n 800c54a } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800c35c: 687b ldr r3, [r7, #4] 800c35e: 685b ldr r3, [r3, #4] 800c360: 2b03 cmp r3, #3 800c362: d107 bne.n 800c374 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c364: 4b36 ldr r3, [pc, #216] @ (800c440 ) 800c366: 681b ldr r3, [r3, #0] 800c368: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c36c: 2b00 cmp r3, #0 800c36e: d115 bne.n 800c39c { return HAL_ERROR; 800c370: 2301 movs r3, #1 800c372: e0ea b.n 800c54a } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 800c374: 687b ldr r3, [r7, #4] 800c376: 685b ldr r3, [r3, #4] 800c378: 2b01 cmp r3, #1 800c37a: d107 bne.n 800c38c { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800c37c: 4b30 ldr r3, [pc, #192] @ (800c440 ) 800c37e: 681b ldr r3, [r3, #0] 800c380: f403 7380 and.w r3, r3, #256 @ 0x100 800c384: 2b00 cmp r3, #0 800c386: d109 bne.n 800c39c { return HAL_ERROR; 800c388: 2301 movs r3, #1 800c38a: e0de b.n 800c54a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800c38c: 4b2c ldr r3, [pc, #176] @ (800c440 ) 800c38e: 681b ldr r3, [r3, #0] 800c390: f003 0304 and.w r3, r3, #4 800c394: 2b00 cmp r3, #0 800c396: d101 bne.n 800c39c { return HAL_ERROR; 800c398: 2301 movs r3, #1 800c39a: e0d6 b.n 800c54a } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800c39c: 4b28 ldr r3, [pc, #160] @ (800c440 ) 800c39e: 691b ldr r3, [r3, #16] 800c3a0: f023 0207 bic.w r2, r3, #7 800c3a4: 687b ldr r3, [r7, #4] 800c3a6: 685b ldr r3, [r3, #4] 800c3a8: 4925 ldr r1, [pc, #148] @ (800c440 ) 800c3aa: 4313 orrs r3, r2 800c3ac: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c3ae: f7f9 fd35 bl 8005e1c 800c3b2: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c3b4: e00a b.n 800c3cc { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800c3b6: f7f9 fd31 bl 8005e1c 800c3ba: 4602 mov r2, r0 800c3bc: 697b ldr r3, [r7, #20] 800c3be: 1ad3 subs r3, r2, r3 800c3c0: f241 3288 movw r2, #5000 @ 0x1388 800c3c4: 4293 cmp r3, r2 800c3c6: d901 bls.n 800c3cc { return HAL_TIMEOUT; 800c3c8: 2303 movs r3, #3 800c3ca: e0be b.n 800c54a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c3cc: 4b1c ldr r3, [pc, #112] @ (800c440 ) 800c3ce: 691b ldr r3, [r3, #16] 800c3d0: f003 0238 and.w r2, r3, #56 @ 0x38 800c3d4: 687b ldr r3, [r7, #4] 800c3d6: 685b ldr r3, [r3, #4] 800c3d8: 00db lsls r3, r3, #3 800c3da: 429a cmp r2, r3 800c3dc: d1eb bne.n 800c3b6 } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c3de: 687b ldr r3, [r7, #4] 800c3e0: 681b ldr r3, [r3, #0] 800c3e2: f003 0302 and.w r3, r3, #2 800c3e6: 2b00 cmp r3, #0 800c3e8: d010 beq.n 800c40c { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c3ea: 687b ldr r3, [r7, #4] 800c3ec: 68da ldr r2, [r3, #12] 800c3ee: 4b14 ldr r3, [pc, #80] @ (800c440 ) 800c3f0: 699b ldr r3, [r3, #24] 800c3f2: f003 030f and.w r3, r3, #15 800c3f6: 429a cmp r2, r3 800c3f8: d208 bcs.n 800c40c { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c3fa: 4b11 ldr r3, [pc, #68] @ (800c440 ) 800c3fc: 699b ldr r3, [r3, #24] 800c3fe: f023 020f bic.w r2, r3, #15 800c402: 687b ldr r3, [r7, #4] 800c404: 68db ldr r3, [r3, #12] 800c406: 490e ldr r1, [pc, #56] @ (800c440 ) 800c408: 4313 orrs r3, r2 800c40a: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800c40c: 4b0b ldr r3, [pc, #44] @ (800c43c ) 800c40e: 681b ldr r3, [r3, #0] 800c410: f003 030f and.w r3, r3, #15 800c414: 683a ldr r2, [r7, #0] 800c416: 429a cmp r2, r3 800c418: d214 bcs.n 800c444 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c41a: 4b08 ldr r3, [pc, #32] @ (800c43c ) 800c41c: 681b ldr r3, [r3, #0] 800c41e: f023 020f bic.w r2, r3, #15 800c422: 4906 ldr r1, [pc, #24] @ (800c43c ) 800c424: 683b ldr r3, [r7, #0] 800c426: 4313 orrs r3, r2 800c428: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c42a: 4b04 ldr r3, [pc, #16] @ (800c43c ) 800c42c: 681b ldr r3, [r3, #0] 800c42e: f003 030f and.w r3, r3, #15 800c432: 683a ldr r2, [r7, #0] 800c434: 429a cmp r2, r3 800c436: d005 beq.n 800c444 { return HAL_ERROR; 800c438: 2301 movs r3, #1 800c43a: e086 b.n 800c54a 800c43c: 52002000 .word 0x52002000 800c440: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c444: 687b ldr r3, [r7, #4] 800c446: 681b ldr r3, [r3, #0] 800c448: f003 0304 and.w r3, r3, #4 800c44c: 2b00 cmp r3, #0 800c44e: d010 beq.n 800c472 { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c450: 687b ldr r3, [r7, #4] 800c452: 691a ldr r2, [r3, #16] 800c454: 4b3f ldr r3, [pc, #252] @ (800c554 ) 800c456: 699b ldr r3, [r3, #24] 800c458: f003 0370 and.w r3, r3, #112 @ 0x70 800c45c: 429a cmp r2, r3 800c45e: d208 bcs.n 800c472 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c460: 4b3c ldr r3, [pc, #240] @ (800c554 ) 800c462: 699b ldr r3, [r3, #24] 800c464: f023 0270 bic.w r2, r3, #112 @ 0x70 800c468: 687b ldr r3, [r7, #4] 800c46a: 691b ldr r3, [r3, #16] 800c46c: 4939 ldr r1, [pc, #228] @ (800c554 ) 800c46e: 4313 orrs r3, r2 800c470: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c472: 687b ldr r3, [r7, #4] 800c474: 681b ldr r3, [r3, #0] 800c476: f003 0308 and.w r3, r3, #8 800c47a: 2b00 cmp r3, #0 800c47c: d010 beq.n 800c4a0 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c47e: 687b ldr r3, [r7, #4] 800c480: 695a ldr r2, [r3, #20] 800c482: 4b34 ldr r3, [pc, #208] @ (800c554 ) 800c484: 69db ldr r3, [r3, #28] 800c486: f003 0370 and.w r3, r3, #112 @ 0x70 800c48a: 429a cmp r2, r3 800c48c: d208 bcs.n 800c4a0 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c48e: 4b31 ldr r3, [pc, #196] @ (800c554 ) 800c490: 69db ldr r3, [r3, #28] 800c492: f023 0270 bic.w r2, r3, #112 @ 0x70 800c496: 687b ldr r3, [r7, #4] 800c498: 695b ldr r3, [r3, #20] 800c49a: 492e ldr r1, [pc, #184] @ (800c554 ) 800c49c: 4313 orrs r3, r2 800c49e: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c4a0: 687b ldr r3, [r7, #4] 800c4a2: 681b ldr r3, [r3, #0] 800c4a4: f003 0310 and.w r3, r3, #16 800c4a8: 2b00 cmp r3, #0 800c4aa: d010 beq.n 800c4ce { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c4ac: 687b ldr r3, [r7, #4] 800c4ae: 699a ldr r2, [r3, #24] 800c4b0: 4b28 ldr r3, [pc, #160] @ (800c554 ) 800c4b2: 69db ldr r3, [r3, #28] 800c4b4: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c4b8: 429a cmp r2, r3 800c4ba: d208 bcs.n 800c4ce { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c4bc: 4b25 ldr r3, [pc, #148] @ (800c554 ) 800c4be: 69db ldr r3, [r3, #28] 800c4c0: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c4c4: 687b ldr r3, [r7, #4] 800c4c6: 699b ldr r3, [r3, #24] 800c4c8: 4922 ldr r1, [pc, #136] @ (800c554 ) 800c4ca: 4313 orrs r3, r2 800c4cc: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c4ce: 687b ldr r3, [r7, #4] 800c4d0: 681b ldr r3, [r3, #0] 800c4d2: f003 0320 and.w r3, r3, #32 800c4d6: 2b00 cmp r3, #0 800c4d8: d010 beq.n 800c4fc { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c4da: 687b ldr r3, [r7, #4] 800c4dc: 69da ldr r2, [r3, #28] 800c4de: 4b1d ldr r3, [pc, #116] @ (800c554 ) 800c4e0: 6a1b ldr r3, [r3, #32] 800c4e2: f003 0370 and.w r3, r3, #112 @ 0x70 800c4e6: 429a cmp r2, r3 800c4e8: d208 bcs.n 800c4fc { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c4ea: 4b1a ldr r3, [pc, #104] @ (800c554 ) 800c4ec: 6a1b ldr r3, [r3, #32] 800c4ee: f023 0270 bic.w r2, r3, #112 @ 0x70 800c4f2: 687b ldr r3, [r7, #4] 800c4f4: 69db ldr r3, [r3, #28] 800c4f6: 4917 ldr r1, [pc, #92] @ (800c554 ) 800c4f8: 4313 orrs r3, r2 800c4fa: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 800c4fc: f000 f834 bl 800c568 800c500: 4602 mov r2, r0 800c502: 4b14 ldr r3, [pc, #80] @ (800c554 ) 800c504: 699b ldr r3, [r3, #24] 800c506: 0a1b lsrs r3, r3, #8 800c508: f003 030f and.w r3, r3, #15 800c50c: 4912 ldr r1, [pc, #72] @ (800c558 ) 800c50e: 5ccb ldrb r3, [r1, r3] 800c510: f003 031f and.w r3, r3, #31 800c514: fa22 f303 lsr.w r3, r2, r3 800c518: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c51a: 4b0e ldr r3, [pc, #56] @ (800c554 ) 800c51c: 699b ldr r3, [r3, #24] 800c51e: f003 030f and.w r3, r3, #15 800c522: 4a0d ldr r2, [pc, #52] @ (800c558 ) 800c524: 5cd3 ldrb r3, [r2, r3] 800c526: f003 031f and.w r3, r3, #31 800c52a: 693a ldr r2, [r7, #16] 800c52c: fa22 f303 lsr.w r3, r2, r3 800c530: 4a0a ldr r2, [pc, #40] @ (800c55c ) 800c532: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c534: 4a0a ldr r2, [pc, #40] @ (800c560 ) 800c536: 693b ldr r3, [r7, #16] 800c538: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800c53a: 4b0a ldr r3, [pc, #40] @ (800c564 ) 800c53c: 681b ldr r3, [r3, #0] 800c53e: 4618 mov r0, r3 800c540: f7f8 f89c bl 800467c 800c544: 4603 mov r3, r0 800c546: 73fb strb r3, [r7, #15] return halstatus; 800c548: 7bfb ldrb r3, [r7, #15] } 800c54a: 4618 mov r0, r3 800c54c: 3718 adds r7, #24 800c54e: 46bd mov sp, r7 800c550: bd80 pop {r7, pc} 800c552: bf00 nop 800c554: 58024400 .word 0x58024400 800c558: 080186fc .word 0x080186fc 800c55c: 24000038 .word 0x24000038 800c560: 24000034 .word 0x24000034 800c564: 2400003c .word 0x2400003c 0800c568 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800c568: b480 push {r7} 800c56a: b089 sub sp, #36 @ 0x24 800c56c: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800c56e: 4bb3 ldr r3, [pc, #716] @ (800c83c ) 800c570: 691b ldr r3, [r3, #16] 800c572: f003 0338 and.w r3, r3, #56 @ 0x38 800c576: 2b18 cmp r3, #24 800c578: f200 8155 bhi.w 800c826 800c57c: a201 add r2, pc, #4 @ (adr r2, 800c584 ) 800c57e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c582: bf00 nop 800c584: 0800c5e9 .word 0x0800c5e9 800c588: 0800c827 .word 0x0800c827 800c58c: 0800c827 .word 0x0800c827 800c590: 0800c827 .word 0x0800c827 800c594: 0800c827 .word 0x0800c827 800c598: 0800c827 .word 0x0800c827 800c59c: 0800c827 .word 0x0800c827 800c5a0: 0800c827 .word 0x0800c827 800c5a4: 0800c60f .word 0x0800c60f 800c5a8: 0800c827 .word 0x0800c827 800c5ac: 0800c827 .word 0x0800c827 800c5b0: 0800c827 .word 0x0800c827 800c5b4: 0800c827 .word 0x0800c827 800c5b8: 0800c827 .word 0x0800c827 800c5bc: 0800c827 .word 0x0800c827 800c5c0: 0800c827 .word 0x0800c827 800c5c4: 0800c615 .word 0x0800c615 800c5c8: 0800c827 .word 0x0800c827 800c5cc: 0800c827 .word 0x0800c827 800c5d0: 0800c827 .word 0x0800c827 800c5d4: 0800c827 .word 0x0800c827 800c5d8: 0800c827 .word 0x0800c827 800c5dc: 0800c827 .word 0x0800c827 800c5e0: 0800c827 .word 0x0800c827 800c5e4: 0800c61b .word 0x0800c61b { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c5e8: 4b94 ldr r3, [pc, #592] @ (800c83c ) 800c5ea: 681b ldr r3, [r3, #0] 800c5ec: f003 0320 and.w r3, r3, #32 800c5f0: 2b00 cmp r3, #0 800c5f2: d009 beq.n 800c608 { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c5f4: 4b91 ldr r3, [pc, #580] @ (800c83c ) 800c5f6: 681b ldr r3, [r3, #0] 800c5f8: 08db lsrs r3, r3, #3 800c5fa: f003 0303 and.w r3, r3, #3 800c5fe: 4a90 ldr r2, [pc, #576] @ (800c840 ) 800c600: fa22 f303 lsr.w r3, r2, r3 800c604: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800c606: e111 b.n 800c82c sysclockfreq = (uint32_t) HSI_VALUE; 800c608: 4b8d ldr r3, [pc, #564] @ (800c840 ) 800c60a: 61bb str r3, [r7, #24] break; 800c60c: e10e b.n 800c82c case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 800c60e: 4b8d ldr r3, [pc, #564] @ (800c844 ) 800c610: 61bb str r3, [r7, #24] break; 800c612: e10b b.n 800c82c case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 800c614: 4b8c ldr r3, [pc, #560] @ (800c848 ) 800c616: 61bb str r3, [r7, #24] break; 800c618: e108 b.n 800c82c case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800c61a: 4b88 ldr r3, [pc, #544] @ (800c83c ) 800c61c: 6a9b ldr r3, [r3, #40] @ 0x28 800c61e: f003 0303 and.w r3, r3, #3 800c622: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800c624: 4b85 ldr r3, [pc, #532] @ (800c83c ) 800c626: 6a9b ldr r3, [r3, #40] @ 0x28 800c628: 091b lsrs r3, r3, #4 800c62a: f003 033f and.w r3, r3, #63 @ 0x3f 800c62e: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 800c630: 4b82 ldr r3, [pc, #520] @ (800c83c ) 800c632: 6adb ldr r3, [r3, #44] @ 0x2c 800c634: f003 0301 and.w r3, r3, #1 800c638: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800c63a: 4b80 ldr r3, [pc, #512] @ (800c83c ) 800c63c: 6b5b ldr r3, [r3, #52] @ 0x34 800c63e: 08db lsrs r3, r3, #3 800c640: f3c3 030c ubfx r3, r3, #0, #13 800c644: 68fa ldr r2, [r7, #12] 800c646: fb02 f303 mul.w r3, r2, r3 800c64a: ee07 3a90 vmov s15, r3 800c64e: eef8 7a67 vcvt.f32.u32 s15, s15 800c652: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800c656: 693b ldr r3, [r7, #16] 800c658: 2b00 cmp r3, #0 800c65a: f000 80e1 beq.w 800c820 800c65e: 697b ldr r3, [r7, #20] 800c660: 2b02 cmp r3, #2 800c662: f000 8083 beq.w 800c76c 800c666: 697b ldr r3, [r7, #20] 800c668: 2b02 cmp r3, #2 800c66a: f200 80a1 bhi.w 800c7b0 800c66e: 697b ldr r3, [r7, #20] 800c670: 2b00 cmp r3, #0 800c672: d003 beq.n 800c67c 800c674: 697b ldr r3, [r7, #20] 800c676: 2b01 cmp r3, #1 800c678: d056 beq.n 800c728 800c67a: e099 b.n 800c7b0 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c67c: 4b6f ldr r3, [pc, #444] @ (800c83c ) 800c67e: 681b ldr r3, [r3, #0] 800c680: f003 0320 and.w r3, r3, #32 800c684: 2b00 cmp r3, #0 800c686: d02d beq.n 800c6e4 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c688: 4b6c ldr r3, [pc, #432] @ (800c83c ) 800c68a: 681b ldr r3, [r3, #0] 800c68c: 08db lsrs r3, r3, #3 800c68e: f003 0303 and.w r3, r3, #3 800c692: 4a6b ldr r2, [pc, #428] @ (800c840 ) 800c694: fa22 f303 lsr.w r3, r2, r3 800c698: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c69a: 687b ldr r3, [r7, #4] 800c69c: ee07 3a90 vmov s15, r3 800c6a0: eef8 6a67 vcvt.f32.u32 s13, s15 800c6a4: 693b ldr r3, [r7, #16] 800c6a6: ee07 3a90 vmov s15, r3 800c6aa: eef8 7a67 vcvt.f32.u32 s15, s15 800c6ae: ee86 7aa7 vdiv.f32 s14, s13, s15 800c6b2: 4b62 ldr r3, [pc, #392] @ (800c83c ) 800c6b4: 6b1b ldr r3, [r3, #48] @ 0x30 800c6b6: f3c3 0308 ubfx r3, r3, #0, #9 800c6ba: ee07 3a90 vmov s15, r3 800c6be: eef8 6a67 vcvt.f32.u32 s13, s15 800c6c2: ed97 6a02 vldr s12, [r7, #8] 800c6c6: eddf 5a61 vldr s11, [pc, #388] @ 800c84c 800c6ca: eec6 7a25 vdiv.f32 s15, s12, s11 800c6ce: ee76 7aa7 vadd.f32 s15, s13, s15 800c6d2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c6d6: ee77 7aa6 vadd.f32 s15, s15, s13 800c6da: ee67 7a27 vmul.f32 s15, s14, s15 800c6de: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800c6e2: e087 b.n 800c7f4 pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c6e4: 693b ldr r3, [r7, #16] 800c6e6: ee07 3a90 vmov s15, r3 800c6ea: eef8 7a67 vcvt.f32.u32 s15, s15 800c6ee: eddf 6a58 vldr s13, [pc, #352] @ 800c850 800c6f2: ee86 7aa7 vdiv.f32 s14, s13, s15 800c6f6: 4b51 ldr r3, [pc, #324] @ (800c83c ) 800c6f8: 6b1b ldr r3, [r3, #48] @ 0x30 800c6fa: f3c3 0308 ubfx r3, r3, #0, #9 800c6fe: ee07 3a90 vmov s15, r3 800c702: eef8 6a67 vcvt.f32.u32 s13, s15 800c706: ed97 6a02 vldr s12, [r7, #8] 800c70a: eddf 5a50 vldr s11, [pc, #320] @ 800c84c 800c70e: eec6 7a25 vdiv.f32 s15, s12, s11 800c712: ee76 7aa7 vadd.f32 s15, s13, s15 800c716: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c71a: ee77 7aa6 vadd.f32 s15, s15, s13 800c71e: ee67 7a27 vmul.f32 s15, s14, s15 800c722: edc7 7a07 vstr s15, [r7, #28] break; 800c726: e065 b.n 800c7f4 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c728: 693b ldr r3, [r7, #16] 800c72a: ee07 3a90 vmov s15, r3 800c72e: eef8 7a67 vcvt.f32.u32 s15, s15 800c732: eddf 6a48 vldr s13, [pc, #288] @ 800c854 800c736: ee86 7aa7 vdiv.f32 s14, s13, s15 800c73a: 4b40 ldr r3, [pc, #256] @ (800c83c ) 800c73c: 6b1b ldr r3, [r3, #48] @ 0x30 800c73e: f3c3 0308 ubfx r3, r3, #0, #9 800c742: ee07 3a90 vmov s15, r3 800c746: eef8 6a67 vcvt.f32.u32 s13, s15 800c74a: ed97 6a02 vldr s12, [r7, #8] 800c74e: eddf 5a3f vldr s11, [pc, #252] @ 800c84c 800c752: eec6 7a25 vdiv.f32 s15, s12, s11 800c756: ee76 7aa7 vadd.f32 s15, s13, s15 800c75a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c75e: ee77 7aa6 vadd.f32 s15, s15, s13 800c762: ee67 7a27 vmul.f32 s15, s14, s15 800c766: edc7 7a07 vstr s15, [r7, #28] break; 800c76a: e043 b.n 800c7f4 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c76c: 693b ldr r3, [r7, #16] 800c76e: ee07 3a90 vmov s15, r3 800c772: eef8 7a67 vcvt.f32.u32 s15, s15 800c776: eddf 6a38 vldr s13, [pc, #224] @ 800c858 800c77a: ee86 7aa7 vdiv.f32 s14, s13, s15 800c77e: 4b2f ldr r3, [pc, #188] @ (800c83c ) 800c780: 6b1b ldr r3, [r3, #48] @ 0x30 800c782: f3c3 0308 ubfx r3, r3, #0, #9 800c786: ee07 3a90 vmov s15, r3 800c78a: eef8 6a67 vcvt.f32.u32 s13, s15 800c78e: ed97 6a02 vldr s12, [r7, #8] 800c792: eddf 5a2e vldr s11, [pc, #184] @ 800c84c 800c796: eec6 7a25 vdiv.f32 s15, s12, s11 800c79a: ee76 7aa7 vadd.f32 s15, s13, s15 800c79e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c7a2: ee77 7aa6 vadd.f32 s15, s15, s13 800c7a6: ee67 7a27 vmul.f32 s15, s14, s15 800c7aa: edc7 7a07 vstr s15, [r7, #28] break; 800c7ae: e021 b.n 800c7f4 default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c7b0: 693b ldr r3, [r7, #16] 800c7b2: ee07 3a90 vmov s15, r3 800c7b6: eef8 7a67 vcvt.f32.u32 s15, s15 800c7ba: eddf 6a26 vldr s13, [pc, #152] @ 800c854 800c7be: ee86 7aa7 vdiv.f32 s14, s13, s15 800c7c2: 4b1e ldr r3, [pc, #120] @ (800c83c ) 800c7c4: 6b1b ldr r3, [r3, #48] @ 0x30 800c7c6: f3c3 0308 ubfx r3, r3, #0, #9 800c7ca: ee07 3a90 vmov s15, r3 800c7ce: eef8 6a67 vcvt.f32.u32 s13, s15 800c7d2: ed97 6a02 vldr s12, [r7, #8] 800c7d6: eddf 5a1d vldr s11, [pc, #116] @ 800c84c 800c7da: eec6 7a25 vdiv.f32 s15, s12, s11 800c7de: ee76 7aa7 vadd.f32 s15, s13, s15 800c7e2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c7e6: ee77 7aa6 vadd.f32 s15, s15, s13 800c7ea: ee67 7a27 vmul.f32 s15, s14, s15 800c7ee: edc7 7a07 vstr s15, [r7, #28] break; 800c7f2: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800c7f4: 4b11 ldr r3, [pc, #68] @ (800c83c ) 800c7f6: 6b1b ldr r3, [r3, #48] @ 0x30 800c7f8: 0a5b lsrs r3, r3, #9 800c7fa: f003 037f and.w r3, r3, #127 @ 0x7f 800c7fe: 3301 adds r3, #1 800c800: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800c802: 683b ldr r3, [r7, #0] 800c804: ee07 3a90 vmov s15, r3 800c808: eeb8 7a67 vcvt.f32.u32 s14, s15 800c80c: edd7 6a07 vldr s13, [r7, #28] 800c810: eec6 7a87 vdiv.f32 s15, s13, s14 800c814: eefc 7ae7 vcvt.u32.f32 s15, s15 800c818: ee17 3a90 vmov r3, s15 800c81c: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 800c81e: e005 b.n 800c82c sysclockfreq = 0U; 800c820: 2300 movs r3, #0 800c822: 61bb str r3, [r7, #24] break; 800c824: e002 b.n 800c82c default: sysclockfreq = CSI_VALUE; 800c826: 4b07 ldr r3, [pc, #28] @ (800c844 ) 800c828: 61bb str r3, [r7, #24] break; 800c82a: bf00 nop } return sysclockfreq; 800c82c: 69bb ldr r3, [r7, #24] } 800c82e: 4618 mov r0, r3 800c830: 3724 adds r7, #36 @ 0x24 800c832: 46bd mov sp, r7 800c834: f85d 7b04 ldr.w r7, [sp], #4 800c838: 4770 bx lr 800c83a: bf00 nop 800c83c: 58024400 .word 0x58024400 800c840: 03d09000 .word 0x03d09000 800c844: 003d0900 .word 0x003d0900 800c848: 017d7840 .word 0x017d7840 800c84c: 46000000 .word 0x46000000 800c850: 4c742400 .word 0x4c742400 800c854: 4a742400 .word 0x4a742400 800c858: 4bbebc20 .word 0x4bbebc20 0800c85c : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800c85c: b580 push {r7, lr} 800c85e: b082 sub sp, #8 800c860: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 800c862: f7ff fe81 bl 800c568 800c866: 4602 mov r2, r0 800c868: 4b10 ldr r3, [pc, #64] @ (800c8ac ) 800c86a: 699b ldr r3, [r3, #24] 800c86c: 0a1b lsrs r3, r3, #8 800c86e: f003 030f and.w r3, r3, #15 800c872: 490f ldr r1, [pc, #60] @ (800c8b0 ) 800c874: 5ccb ldrb r3, [r1, r3] 800c876: f003 031f and.w r3, r3, #31 800c87a: fa22 f303 lsr.w r3, r2, r3 800c87e: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c880: 4b0a ldr r3, [pc, #40] @ (800c8ac ) 800c882: 699b ldr r3, [r3, #24] 800c884: f003 030f and.w r3, r3, #15 800c888: 4a09 ldr r2, [pc, #36] @ (800c8b0 ) 800c88a: 5cd3 ldrb r3, [r2, r3] 800c88c: f003 031f and.w r3, r3, #31 800c890: 687a ldr r2, [r7, #4] 800c892: fa22 f303 lsr.w r3, r2, r3 800c896: 4a07 ldr r2, [pc, #28] @ (800c8b4 ) 800c898: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c89a: 4a07 ldr r2, [pc, #28] @ (800c8b8 ) 800c89c: 687b ldr r3, [r7, #4] 800c89e: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800c8a0: 4b04 ldr r3, [pc, #16] @ (800c8b4 ) 800c8a2: 681b ldr r3, [r3, #0] } 800c8a4: 4618 mov r0, r3 800c8a6: 3708 adds r7, #8 800c8a8: 46bd mov sp, r7 800c8aa: bd80 pop {r7, pc} 800c8ac: 58024400 .word 0x58024400 800c8b0: 080186fc .word 0x080186fc 800c8b4: 24000038 .word 0x24000038 800c8b8: 24000034 .word 0x24000034 0800c8bc : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800c8bc: b580 push {r7, lr} 800c8be: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 800c8c0: f7ff ffcc bl 800c85c 800c8c4: 4602 mov r2, r0 800c8c6: 4b06 ldr r3, [pc, #24] @ (800c8e0 ) 800c8c8: 69db ldr r3, [r3, #28] 800c8ca: 091b lsrs r3, r3, #4 800c8cc: f003 0307 and.w r3, r3, #7 800c8d0: 4904 ldr r1, [pc, #16] @ (800c8e4 ) 800c8d2: 5ccb ldrb r3, [r1, r3] 800c8d4: f003 031f and.w r3, r3, #31 800c8d8: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 800c8dc: 4618 mov r0, r3 800c8de: bd80 pop {r7, pc} 800c8e0: 58024400 .word 0x58024400 800c8e4: 080186fc .word 0x080186fc 0800c8e8 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800c8e8: b580 push {r7, lr} 800c8ea: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 800c8ec: f7ff ffb6 bl 800c85c 800c8f0: 4602 mov r2, r0 800c8f2: 4b06 ldr r3, [pc, #24] @ (800c90c ) 800c8f4: 69db ldr r3, [r3, #28] 800c8f6: 0a1b lsrs r3, r3, #8 800c8f8: f003 0307 and.w r3, r3, #7 800c8fc: 4904 ldr r1, [pc, #16] @ (800c910 ) 800c8fe: 5ccb ldrb r3, [r1, r3] 800c900: f003 031f and.w r3, r3, #31 800c904: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800c908: 4618 mov r0, r3 800c90a: bd80 pop {r7, pc} 800c90c: 58024400 .word 0x58024400 800c910: 080186fc .word 0x080186fc 0800c914 : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800c914: b480 push {r7} 800c916: b083 sub sp, #12 800c918: af00 add r7, sp, #0 800c91a: 6078 str r0, [r7, #4] 800c91c: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 800c91e: 687b ldr r3, [r7, #4] 800c920: 223f movs r2, #63 @ 0x3f 800c922: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 800c924: 4b1a ldr r3, [pc, #104] @ (800c990 ) 800c926: 691b ldr r3, [r3, #16] 800c928: f003 0207 and.w r2, r3, #7 800c92c: 687b ldr r3, [r7, #4] 800c92e: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 800c930: 4b17 ldr r3, [pc, #92] @ (800c990 ) 800c932: 699b ldr r3, [r3, #24] 800c934: f403 6270 and.w r2, r3, #3840 @ 0xf00 800c938: 687b ldr r3, [r7, #4] 800c93a: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 800c93c: 4b14 ldr r3, [pc, #80] @ (800c990 ) 800c93e: 699b ldr r3, [r3, #24] 800c940: f003 020f and.w r2, r3, #15 800c944: 687b ldr r3, [r7, #4] 800c946: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800c948: 4b11 ldr r3, [pc, #68] @ (800c990 ) 800c94a: 699b ldr r3, [r3, #24] 800c94c: f003 0270 and.w r2, r3, #112 @ 0x70 800c950: 687b ldr r3, [r7, #4] 800c952: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 800c954: 4b0e ldr r3, [pc, #56] @ (800c990 ) 800c956: 69db ldr r3, [r3, #28] 800c958: f003 0270 and.w r2, r3, #112 @ 0x70 800c95c: 687b ldr r3, [r7, #4] 800c95e: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 800c960: 4b0b ldr r3, [pc, #44] @ (800c990 ) 800c962: 69db ldr r3, [r3, #28] 800c964: f403 62e0 and.w r2, r3, #1792 @ 0x700 800c968: 687b ldr r3, [r7, #4] 800c96a: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 800c96c: 4b08 ldr r3, [pc, #32] @ (800c990 ) 800c96e: 6a1b ldr r3, [r3, #32] 800c970: f003 0270 and.w r2, r3, #112 @ 0x70 800c974: 687b ldr r3, [r7, #4] 800c976: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800c978: 4b06 ldr r3, [pc, #24] @ (800c994 ) 800c97a: 681b ldr r3, [r3, #0] 800c97c: f003 020f and.w r2, r3, #15 800c980: 683b ldr r3, [r7, #0] 800c982: 601a str r2, [r3, #0] } 800c984: bf00 nop 800c986: 370c adds r7, #12 800c988: 46bd mov sp, r7 800c98a: f85d 7b04 ldr.w r7, [sp], #4 800c98e: 4770 bx lr 800c990: 58024400 .word 0x58024400 800c994: 52002000 .word 0x52002000 0800c998 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800c998: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800c99c: b0c8 sub sp, #288 @ 0x120 800c99e: af00 add r7, sp, #0 800c9a0: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800c9a4: 2300 movs r3, #0 800c9a6: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800c9aa: 2300 movs r3, #0 800c9ac: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800c9b0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9b4: e9d3 2300 ldrd r2, r3, [r3] 800c9b8: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800c9bc: 2500 movs r5, #0 800c9be: ea54 0305 orrs.w r3, r4, r5 800c9c2: d049 beq.n 800ca58 { switch (PeriphClkInit->SpdifrxClockSelection) 800c9c4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9c8: 6e9b ldr r3, [r3, #104] @ 0x68 800c9ca: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c9ce: d02f beq.n 800ca30 800c9d0: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c9d4: d828 bhi.n 800ca28 800c9d6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c9da: d01a beq.n 800ca12 800c9dc: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c9e0: d822 bhi.n 800ca28 800c9e2: 2b00 cmp r3, #0 800c9e4: d003 beq.n 800c9ee 800c9e6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800c9ea: d007 beq.n 800c9fc 800c9ec: e01c b.n 800ca28 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c9ee: 4bb8 ldr r3, [pc, #736] @ (800ccd0 ) 800c9f0: 6adb ldr r3, [r3, #44] @ 0x2c 800c9f2: 4ab7 ldr r2, [pc, #732] @ (800ccd0 ) 800c9f4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c9f8: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800c9fa: e01a b.n 800ca32 case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800c9fc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca00: 3308 adds r3, #8 800ca02: 2102 movs r1, #2 800ca04: 4618 mov r0, r3 800ca06: f002 fb45 bl 800f094 800ca0a: 4603 mov r3, r0 800ca0c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800ca10: e00f b.n 800ca32 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800ca12: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca16: 3328 adds r3, #40 @ 0x28 800ca18: 2102 movs r1, #2 800ca1a: 4618 mov r0, r3 800ca1c: f002 fbec bl 800f1f8 800ca20: 4603 mov r3, r0 800ca22: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800ca26: e004 b.n 800ca32 /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ca28: 2301 movs r3, #1 800ca2a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ca2e: e000 b.n 800ca32 break; 800ca30: bf00 nop } if (ret == HAL_OK) 800ca32: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca36: 2b00 cmp r3, #0 800ca38: d10a bne.n 800ca50 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800ca3a: 4ba5 ldr r3, [pc, #660] @ (800ccd0 ) 800ca3c: 6d1b ldr r3, [r3, #80] @ 0x50 800ca3e: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800ca42: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca46: 6e9b ldr r3, [r3, #104] @ 0x68 800ca48: 4aa1 ldr r2, [pc, #644] @ (800ccd0 ) 800ca4a: 430b orrs r3, r1 800ca4c: 6513 str r3, [r2, #80] @ 0x50 800ca4e: e003 b.n 800ca58 } else { /* set overall return value */ status = ret; 800ca50: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca54: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800ca58: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca5c: e9d3 2300 ldrd r2, r3, [r3] 800ca60: f402 7880 and.w r8, r2, #256 @ 0x100 800ca64: f04f 0900 mov.w r9, #0 800ca68: ea58 0309 orrs.w r3, r8, r9 800ca6c: d047 beq.n 800cafe { switch (PeriphClkInit->Sai1ClockSelection) 800ca6e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca72: 6d9b ldr r3, [r3, #88] @ 0x58 800ca74: 2b04 cmp r3, #4 800ca76: d82a bhi.n 800cace 800ca78: a201 add r2, pc, #4 @ (adr r2, 800ca80 ) 800ca7a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ca7e: bf00 nop 800ca80: 0800ca95 .word 0x0800ca95 800ca84: 0800caa3 .word 0x0800caa3 800ca88: 0800cab9 .word 0x0800cab9 800ca8c: 0800cad7 .word 0x0800cad7 800ca90: 0800cad7 .word 0x0800cad7 { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ca94: 4b8e ldr r3, [pc, #568] @ (800ccd0 ) 800ca96: 6adb ldr r3, [r3, #44] @ 0x2c 800ca98: 4a8d ldr r2, [pc, #564] @ (800ccd0 ) 800ca9a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ca9e: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800caa0: e01a b.n 800cad8 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800caa2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caa6: 3308 adds r3, #8 800caa8: 2100 movs r1, #0 800caaa: 4618 mov r0, r3 800caac: f002 faf2 bl 800f094 800cab0: 4603 mov r3, r0 800cab2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cab6: e00f b.n 800cad8 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cab8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cabc: 3328 adds r3, #40 @ 0x28 800cabe: 2100 movs r1, #0 800cac0: 4618 mov r0, r3 800cac2: f002 fb99 bl 800f1f8 800cac6: 4603 mov r3, r0 800cac8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cacc: e004 b.n 800cad8 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cace: 2301 movs r3, #1 800cad0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cad4: e000 b.n 800cad8 break; 800cad6: bf00 nop } if (ret == HAL_OK) 800cad8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cadc: 2b00 cmp r3, #0 800cade: d10a bne.n 800caf6 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800cae0: 4b7b ldr r3, [pc, #492] @ (800ccd0 ) 800cae2: 6d1b ldr r3, [r3, #80] @ 0x50 800cae4: f023 0107 bic.w r1, r3, #7 800cae8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caec: 6d9b ldr r3, [r3, #88] @ 0x58 800caee: 4a78 ldr r2, [pc, #480] @ (800ccd0 ) 800caf0: 430b orrs r3, r1 800caf2: 6513 str r3, [r2, #80] @ 0x50 800caf4: e003 b.n 800cafe } else { /* set overall return value */ status = ret; 800caf6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cafa: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800cafe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb02: e9d3 2300 ldrd r2, r3, [r3] 800cb06: f402 7a00 and.w sl, r2, #512 @ 0x200 800cb0a: f04f 0b00 mov.w fp, #0 800cb0e: ea5a 030b orrs.w r3, sl, fp 800cb12: d04c beq.n 800cbae { switch (PeriphClkInit->Sai23ClockSelection) 800cb14: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb18: 6ddb ldr r3, [r3, #92] @ 0x5c 800cb1a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cb1e: d030 beq.n 800cb82 800cb20: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cb24: d829 bhi.n 800cb7a 800cb26: 2bc0 cmp r3, #192 @ 0xc0 800cb28: d02d beq.n 800cb86 800cb2a: 2bc0 cmp r3, #192 @ 0xc0 800cb2c: d825 bhi.n 800cb7a 800cb2e: 2b80 cmp r3, #128 @ 0x80 800cb30: d018 beq.n 800cb64 800cb32: 2b80 cmp r3, #128 @ 0x80 800cb34: d821 bhi.n 800cb7a 800cb36: 2b00 cmp r3, #0 800cb38: d002 beq.n 800cb40 800cb3a: 2b40 cmp r3, #64 @ 0x40 800cb3c: d007 beq.n 800cb4e 800cb3e: e01c b.n 800cb7a { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cb40: 4b63 ldr r3, [pc, #396] @ (800ccd0 ) 800cb42: 6adb ldr r3, [r3, #44] @ 0x2c 800cb44: 4a62 ldr r2, [pc, #392] @ (800ccd0 ) 800cb46: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cb4a: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb4c: e01c b.n 800cb88 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cb4e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb52: 3308 adds r3, #8 800cb54: 2100 movs r1, #0 800cb56: 4618 mov r0, r3 800cb58: f002 fa9c bl 800f094 800cb5c: 4603 mov r3, r0 800cb5e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb62: e011 b.n 800cb88 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cb64: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb68: 3328 adds r3, #40 @ 0x28 800cb6a: 2100 movs r1, #0 800cb6c: 4618 mov r0, r3 800cb6e: f002 fb43 bl 800f1f8 800cb72: 4603 mov r3, r0 800cb74: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb78: e006 b.n 800cb88 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cb7a: 2301 movs r3, #1 800cb7c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cb80: e002 b.n 800cb88 break; 800cb82: bf00 nop 800cb84: e000 b.n 800cb88 break; 800cb86: bf00 nop } if (ret == HAL_OK) 800cb88: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb8c: 2b00 cmp r3, #0 800cb8e: d10a bne.n 800cba6 { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800cb90: 4b4f ldr r3, [pc, #316] @ (800ccd0 ) 800cb92: 6d1b ldr r3, [r3, #80] @ 0x50 800cb94: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 800cb98: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb9c: 6ddb ldr r3, [r3, #92] @ 0x5c 800cb9e: 4a4c ldr r2, [pc, #304] @ (800ccd0 ) 800cba0: 430b orrs r3, r1 800cba2: 6513 str r3, [r2, #80] @ 0x50 800cba4: e003 b.n 800cbae } else { /* set overall return value */ status = ret; 800cba6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cbaa: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800cbae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbb2: e9d3 2300 ldrd r2, r3, [r3] 800cbb6: f402 6380 and.w r3, r2, #1024 @ 0x400 800cbba: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800cbbe: 2300 movs r3, #0 800cbc0: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800cbc4: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 800cbc8: 460b mov r3, r1 800cbca: 4313 orrs r3, r2 800cbcc: d053 beq.n 800cc76 { switch (PeriphClkInit->Sai4AClockSelection) 800cbce: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbd2: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800cbd6: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800cbda: d035 beq.n 800cc48 800cbdc: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800cbe0: d82e bhi.n 800cc40 800cbe2: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800cbe6: d031 beq.n 800cc4c 800cbe8: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800cbec: d828 bhi.n 800cc40 800cbee: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800cbf2: d01a beq.n 800cc2a 800cbf4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800cbf8: d822 bhi.n 800cc40 800cbfa: 2b00 cmp r3, #0 800cbfc: d003 beq.n 800cc06 800cbfe: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800cc02: d007 beq.n 800cc14 800cc04: e01c b.n 800cc40 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cc06: 4b32 ldr r3, [pc, #200] @ (800ccd0 ) 800cc08: 6adb ldr r3, [r3, #44] @ 0x2c 800cc0a: 4a31 ldr r2, [pc, #196] @ (800ccd0 ) 800cc0c: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cc10: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800cc12: e01c b.n 800cc4e case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cc14: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc18: 3308 adds r3, #8 800cc1a: 2100 movs r1, #0 800cc1c: 4618 mov r0, r3 800cc1e: f002 fa39 bl 800f094 800cc22: 4603 mov r3, r0 800cc24: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800cc28: e011 b.n 800cc4e case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cc2a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc2e: 3328 adds r3, #40 @ 0x28 800cc30: 2100 movs r1, #0 800cc32: 4618 mov r0, r3 800cc34: f002 fae0 bl 800f1f8 800cc38: 4603 mov r3, r0 800cc3a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cc3e: e006 b.n 800cc4e /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800cc40: 2301 movs r3, #1 800cc42: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cc46: e002 b.n 800cc4e break; 800cc48: bf00 nop 800cc4a: e000 b.n 800cc4e break; 800cc4c: bf00 nop } if (ret == HAL_OK) 800cc4e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc52: 2b00 cmp r3, #0 800cc54: d10b bne.n 800cc6e { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800cc56: 4b1e ldr r3, [pc, #120] @ (800ccd0 ) 800cc58: 6d9b ldr r3, [r3, #88] @ 0x58 800cc5a: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 800cc5e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc62: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800cc66: 4a1a ldr r2, [pc, #104] @ (800ccd0 ) 800cc68: 430b orrs r3, r1 800cc6a: 6593 str r3, [r2, #88] @ 0x58 800cc6c: e003 b.n 800cc76 } else { /* set overall return value */ status = ret; 800cc6e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc72: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800cc76: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc7a: e9d3 2300 ldrd r2, r3, [r3] 800cc7e: f402 6300 and.w r3, r2, #2048 @ 0x800 800cc82: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800cc86: 2300 movs r3, #0 800cc88: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800cc8c: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 800cc90: 460b mov r3, r1 800cc92: 4313 orrs r3, r2 800cc94: d056 beq.n 800cd44 { switch (PeriphClkInit->Sai4BClockSelection) 800cc96: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc9a: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800cc9e: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800cca2: d038 beq.n 800cd16 800cca4: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800cca8: d831 bhi.n 800cd0e 800ccaa: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800ccae: d034 beq.n 800cd1a 800ccb0: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800ccb4: d82b bhi.n 800cd0e 800ccb6: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ccba: d01d beq.n 800ccf8 800ccbc: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ccc0: d825 bhi.n 800cd0e 800ccc2: 2b00 cmp r3, #0 800ccc4: d006 beq.n 800ccd4 800ccc6: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800ccca: d00a beq.n 800cce2 800cccc: e01f b.n 800cd0e 800ccce: bf00 nop 800ccd0: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ccd4: 4ba2 ldr r3, [pc, #648] @ (800cf60 ) 800ccd6: 6adb ldr r3, [r3, #44] @ 0x2c 800ccd8: 4aa1 ldr r2, [pc, #644] @ (800cf60 ) 800ccda: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ccde: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800cce0: e01c b.n 800cd1c case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cce2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cce6: 3308 adds r3, #8 800cce8: 2100 movs r1, #0 800ccea: 4618 mov r0, r3 800ccec: f002 f9d2 bl 800f094 800ccf0: 4603 mov r3, r0 800ccf2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800ccf6: e011 b.n 800cd1c case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800ccf8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccfc: 3328 adds r3, #40 @ 0x28 800ccfe: 2100 movs r1, #0 800cd00: 4618 mov r0, r3 800cd02: f002 fa79 bl 800f1f8 800cd06: 4603 mov r3, r0 800cd08: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cd0c: e006 b.n 800cd1c /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800cd0e: 2301 movs r3, #1 800cd10: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cd14: e002 b.n 800cd1c break; 800cd16: bf00 nop 800cd18: e000 b.n 800cd1c break; 800cd1a: bf00 nop } if (ret == HAL_OK) 800cd1c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd20: 2b00 cmp r3, #0 800cd22: d10b bne.n 800cd3c { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800cd24: 4b8e ldr r3, [pc, #568] @ (800cf60 ) 800cd26: 6d9b ldr r3, [r3, #88] @ 0x58 800cd28: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 800cd2c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd30: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800cd34: 4a8a ldr r2, [pc, #552] @ (800cf60 ) 800cd36: 430b orrs r3, r1 800cd38: 6593 str r3, [r2, #88] @ 0x58 800cd3a: e003 b.n 800cd44 } else { /* set overall return value */ status = ret; 800cd3c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd40: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800cd44: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd48: e9d3 2300 ldrd r2, r3, [r3] 800cd4c: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 800cd50: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800cd54: 2300 movs r3, #0 800cd56: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800cd5a: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 800cd5e: 460b mov r3, r1 800cd60: 4313 orrs r3, r2 800cd62: d03a beq.n 800cdda { switch (PeriphClkInit->QspiClockSelection) 800cd64: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd68: 6cdb ldr r3, [r3, #76] @ 0x4c 800cd6a: 2b30 cmp r3, #48 @ 0x30 800cd6c: d01f beq.n 800cdae 800cd6e: 2b30 cmp r3, #48 @ 0x30 800cd70: d819 bhi.n 800cda6 800cd72: 2b20 cmp r3, #32 800cd74: d00c beq.n 800cd90 800cd76: 2b20 cmp r3, #32 800cd78: d815 bhi.n 800cda6 800cd7a: 2b00 cmp r3, #0 800cd7c: d019 beq.n 800cdb2 800cd7e: 2b10 cmp r3, #16 800cd80: d111 bne.n 800cda6 { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cd82: 4b77 ldr r3, [pc, #476] @ (800cf60 ) 800cd84: 6adb ldr r3, [r3, #44] @ 0x2c 800cd86: 4a76 ldr r2, [pc, #472] @ (800cf60 ) 800cd88: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cd8c: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800cd8e: e011 b.n 800cdb4 case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800cd90: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd94: 3308 adds r3, #8 800cd96: 2102 movs r1, #2 800cd98: 4618 mov r0, r3 800cd9a: f002 f97b bl 800f094 800cd9e: 4603 mov r3, r0 800cda0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 800cda4: e006 b.n 800cdb4 case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800cda6: 2301 movs r3, #1 800cda8: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cdac: e002 b.n 800cdb4 break; 800cdae: bf00 nop 800cdb0: e000 b.n 800cdb4 break; 800cdb2: bf00 nop } if (ret == HAL_OK) 800cdb4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdb8: 2b00 cmp r3, #0 800cdba: d10a bne.n 800cdd2 { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800cdbc: 4b68 ldr r3, [pc, #416] @ (800cf60 ) 800cdbe: 6cdb ldr r3, [r3, #76] @ 0x4c 800cdc0: f023 0130 bic.w r1, r3, #48 @ 0x30 800cdc4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdc8: 6cdb ldr r3, [r3, #76] @ 0x4c 800cdca: 4a65 ldr r2, [pc, #404] @ (800cf60 ) 800cdcc: 430b orrs r3, r1 800cdce: 64d3 str r3, [r2, #76] @ 0x4c 800cdd0: e003 b.n 800cdda } else { /* set overall return value */ status = ret; 800cdd2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdd6: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800cdda: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdde: e9d3 2300 ldrd r2, r3, [r3] 800cde2: f402 5380 and.w r3, r2, #4096 @ 0x1000 800cde6: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800cdea: 2300 movs r3, #0 800cdec: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800cdf0: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 800cdf4: 460b mov r3, r1 800cdf6: 4313 orrs r3, r2 800cdf8: d051 beq.n 800ce9e { switch (PeriphClkInit->Spi123ClockSelection) 800cdfa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdfe: 6e1b ldr r3, [r3, #96] @ 0x60 800ce00: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800ce04: d035 beq.n 800ce72 800ce06: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800ce0a: d82e bhi.n 800ce6a 800ce0c: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800ce10: d031 beq.n 800ce76 800ce12: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800ce16: d828 bhi.n 800ce6a 800ce18: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ce1c: d01a beq.n 800ce54 800ce1e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ce22: d822 bhi.n 800ce6a 800ce24: 2b00 cmp r3, #0 800ce26: d003 beq.n 800ce30 800ce28: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800ce2c: d007 beq.n 800ce3e 800ce2e: e01c b.n 800ce6a { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ce30: 4b4b ldr r3, [pc, #300] @ (800cf60 ) 800ce32: 6adb ldr r3, [r3, #44] @ 0x2c 800ce34: 4a4a ldr r2, [pc, #296] @ (800cf60 ) 800ce36: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ce3a: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce3c: e01c b.n 800ce78 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800ce3e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce42: 3308 adds r3, #8 800ce44: 2100 movs r1, #0 800ce46: 4618 mov r0, r3 800ce48: f002 f924 bl 800f094 800ce4c: 4603 mov r3, r0 800ce4e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce52: e011 b.n 800ce78 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800ce54: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce58: 3328 adds r3, #40 @ 0x28 800ce5a: 2100 movs r1, #0 800ce5c: 4618 mov r0, r3 800ce5e: f002 f9cb bl 800f1f8 800ce62: 4603 mov r3, r0 800ce64: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce68: e006 b.n 800ce78 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ce6a: 2301 movs r3, #1 800ce6c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce70: e002 b.n 800ce78 break; 800ce72: bf00 nop 800ce74: e000 b.n 800ce78 break; 800ce76: bf00 nop } if (ret == HAL_OK) 800ce78: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce7c: 2b00 cmp r3, #0 800ce7e: d10a bne.n 800ce96 { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800ce80: 4b37 ldr r3, [pc, #220] @ (800cf60 ) 800ce82: 6d1b ldr r3, [r3, #80] @ 0x50 800ce84: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 800ce88: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce8c: 6e1b ldr r3, [r3, #96] @ 0x60 800ce8e: 4a34 ldr r2, [pc, #208] @ (800cf60 ) 800ce90: 430b orrs r3, r1 800ce92: 6513 str r3, [r2, #80] @ 0x50 800ce94: e003 b.n 800ce9e } else { /* set overall return value */ status = ret; 800ce96: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce9a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800ce9e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cea2: e9d3 2300 ldrd r2, r3, [r3] 800cea6: f402 5300 and.w r3, r2, #8192 @ 0x2000 800ceaa: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800ceae: 2300 movs r3, #0 800ceb0: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800ceb4: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 800ceb8: 460b mov r3, r1 800ceba: 4313 orrs r3, r2 800cebc: d056 beq.n 800cf6c { switch (PeriphClkInit->Spi45ClockSelection) 800cebe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cec2: 6e5b ldr r3, [r3, #100] @ 0x64 800cec4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cec8: d033 beq.n 800cf32 800ceca: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800cece: d82c bhi.n 800cf2a 800ced0: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800ced4: d02f beq.n 800cf36 800ced6: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800ceda: d826 bhi.n 800cf2a 800cedc: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cee0: d02b beq.n 800cf3a 800cee2: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cee6: d820 bhi.n 800cf2a 800cee8: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800ceec: d012 beq.n 800cf14 800ceee: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cef2: d81a bhi.n 800cf2a 800cef4: 2b00 cmp r3, #0 800cef6: d022 beq.n 800cf3e 800cef8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cefc: d115 bne.n 800cf2a /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cefe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf02: 3308 adds r3, #8 800cf04: 2101 movs r1, #1 800cf06: 4618 mov r0, r3 800cf08: f002 f8c4 bl 800f094 800cf0c: 4603 mov r3, r0 800cf0e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cf12: e015 b.n 800cf40 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cf14: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf18: 3328 adds r3, #40 @ 0x28 800cf1a: 2101 movs r1, #1 800cf1c: 4618 mov r0, r3 800cf1e: f002 f96b bl 800f1f8 800cf22: 4603 mov r3, r0 800cf24: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cf28: e00a b.n 800cf40 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cf2a: 2301 movs r3, #1 800cf2c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cf30: e006 b.n 800cf40 break; 800cf32: bf00 nop 800cf34: e004 b.n 800cf40 break; 800cf36: bf00 nop 800cf38: e002 b.n 800cf40 break; 800cf3a: bf00 nop 800cf3c: e000 b.n 800cf40 break; 800cf3e: bf00 nop } if (ret == HAL_OK) 800cf40: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf44: 2b00 cmp r3, #0 800cf46: d10d bne.n 800cf64 { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800cf48: 4b05 ldr r3, [pc, #20] @ (800cf60 ) 800cf4a: 6d1b ldr r3, [r3, #80] @ 0x50 800cf4c: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 800cf50: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf54: 6e5b ldr r3, [r3, #100] @ 0x64 800cf56: 4a02 ldr r2, [pc, #8] @ (800cf60 ) 800cf58: 430b orrs r3, r1 800cf5a: 6513 str r3, [r2, #80] @ 0x50 800cf5c: e006 b.n 800cf6c 800cf5e: bf00 nop 800cf60: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800cf64: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf68: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800cf6c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf70: e9d3 2300 ldrd r2, r3, [r3] 800cf74: f402 4380 and.w r3, r2, #16384 @ 0x4000 800cf78: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800cf7c: 2300 movs r3, #0 800cf7e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800cf82: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800cf86: 460b mov r3, r1 800cf88: 4313 orrs r3, r2 800cf8a: d055 beq.n 800d038 { switch (PeriphClkInit->Spi6ClockSelection) 800cf8c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf90: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800cf94: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cf98: d033 beq.n 800d002 800cf9a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cf9e: d82c bhi.n 800cffa 800cfa0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cfa4: d02f beq.n 800d006 800cfa6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cfaa: d826 bhi.n 800cffa 800cfac: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cfb0: d02b beq.n 800d00a 800cfb2: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cfb6: d820 bhi.n 800cffa 800cfb8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cfbc: d012 beq.n 800cfe4 800cfbe: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cfc2: d81a bhi.n 800cffa 800cfc4: 2b00 cmp r3, #0 800cfc6: d022 beq.n 800d00e 800cfc8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cfcc: d115 bne.n 800cffa /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cfce: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfd2: 3308 adds r3, #8 800cfd4: 2101 movs r1, #1 800cfd6: 4618 mov r0, r3 800cfd8: f002 f85c bl 800f094 800cfdc: 4603 mov r3, r0 800cfde: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800cfe2: e015 b.n 800d010 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cfe4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfe8: 3328 adds r3, #40 @ 0x28 800cfea: 2101 movs r1, #1 800cfec: 4618 mov r0, r3 800cfee: f002 f903 bl 800f1f8 800cff2: 4603 mov r3, r0 800cff4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800cff8: e00a b.n 800d010 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800cffa: 2301 movs r3, #1 800cffc: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d000: e006 b.n 800d010 break; 800d002: bf00 nop 800d004: e004 b.n 800d010 break; 800d006: bf00 nop 800d008: e002 b.n 800d010 break; 800d00a: bf00 nop 800d00c: e000 b.n 800d010 break; 800d00e: bf00 nop } if (ret == HAL_OK) 800d010: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d014: 2b00 cmp r3, #0 800d016: d10b bne.n 800d030 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800d018: 4ba3 ldr r3, [pc, #652] @ (800d2a8 ) 800d01a: 6d9b ldr r3, [r3, #88] @ 0x58 800d01c: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d020: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d024: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800d028: 4a9f ldr r2, [pc, #636] @ (800d2a8 ) 800d02a: 430b orrs r3, r1 800d02c: 6593 str r3, [r2, #88] @ 0x58 800d02e: e003 b.n 800d038 } else { /* set overall return value */ status = ret; 800d030: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d034: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800d038: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d03c: e9d3 2300 ldrd r2, r3, [r3] 800d040: f402 4300 and.w r3, r2, #32768 @ 0x8000 800d044: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800d048: 2300 movs r3, #0 800d04a: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800d04e: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 800d052: 460b mov r3, r1 800d054: 4313 orrs r3, r2 800d056: d037 beq.n 800d0c8 { switch (PeriphClkInit->FdcanClockSelection) 800d058: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d05c: 6f1b ldr r3, [r3, #112] @ 0x70 800d05e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d062: d00e beq.n 800d082 800d064: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d068: d816 bhi.n 800d098 800d06a: 2b00 cmp r3, #0 800d06c: d018 beq.n 800d0a0 800d06e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d072: d111 bne.n 800d098 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d074: 4b8c ldr r3, [pc, #560] @ (800d2a8 ) 800d076: 6adb ldr r3, [r3, #44] @ 0x2c 800d078: 4a8b ldr r2, [pc, #556] @ (800d2a8 ) 800d07a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d07e: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800d080: e00f b.n 800d0a2 case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d082: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d086: 3308 adds r3, #8 800d088: 2101 movs r1, #1 800d08a: 4618 mov r0, r3 800d08c: f002 f802 bl 800f094 800d090: 4603 mov r3, r0 800d092: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 800d096: e004 b.n 800d0a2 /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d098: 2301 movs r3, #1 800d09a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d09e: e000 b.n 800d0a2 break; 800d0a0: bf00 nop } if (ret == HAL_OK) 800d0a2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0a6: 2b00 cmp r3, #0 800d0a8: d10a bne.n 800d0c0 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800d0aa: 4b7f ldr r3, [pc, #508] @ (800d2a8 ) 800d0ac: 6d1b ldr r3, [r3, #80] @ 0x50 800d0ae: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800d0b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0b6: 6f1b ldr r3, [r3, #112] @ 0x70 800d0b8: 4a7b ldr r2, [pc, #492] @ (800d2a8 ) 800d0ba: 430b orrs r3, r1 800d0bc: 6513 str r3, [r2, #80] @ 0x50 800d0be: e003 b.n 800d0c8 } else { /* set overall return value */ status = ret; 800d0c0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0c4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 800d0c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0cc: e9d3 2300 ldrd r2, r3, [r3] 800d0d0: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 800d0d4: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800d0d8: 2300 movs r3, #0 800d0da: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800d0de: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 800d0e2: 460b mov r3, r1 800d0e4: 4313 orrs r3, r2 800d0e6: d039 beq.n 800d15c { switch (PeriphClkInit->FmcClockSelection) 800d0e8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0ec: 6c9b ldr r3, [r3, #72] @ 0x48 800d0ee: 2b03 cmp r3, #3 800d0f0: d81c bhi.n 800d12c 800d0f2: a201 add r2, pc, #4 @ (adr r2, 800d0f8 ) 800d0f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d0f8: 0800d135 .word 0x0800d135 800d0fc: 0800d109 .word 0x0800d109 800d100: 0800d117 .word 0x0800d117 800d104: 0800d135 .word 0x0800d135 { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d108: 4b67 ldr r3, [pc, #412] @ (800d2a8 ) 800d10a: 6adb ldr r3, [r3, #44] @ 0x2c 800d10c: 4a66 ldr r2, [pc, #408] @ (800d2a8 ) 800d10e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d112: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800d114: e00f b.n 800d136 case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d116: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d11a: 3308 adds r3, #8 800d11c: 2102 movs r1, #2 800d11e: 4618 mov r0, r3 800d120: f001 ffb8 bl 800f094 800d124: 4603 mov r3, r0 800d126: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 800d12a: e004 b.n 800d136 case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800d12c: 2301 movs r3, #1 800d12e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d132: e000 b.n 800d136 break; 800d134: bf00 nop } if (ret == HAL_OK) 800d136: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d13a: 2b00 cmp r3, #0 800d13c: d10a bne.n 800d154 { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800d13e: 4b5a ldr r3, [pc, #360] @ (800d2a8 ) 800d140: 6cdb ldr r3, [r3, #76] @ 0x4c 800d142: f023 0103 bic.w r1, r3, #3 800d146: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d14a: 6c9b ldr r3, [r3, #72] @ 0x48 800d14c: 4a56 ldr r2, [pc, #344] @ (800d2a8 ) 800d14e: 430b orrs r3, r1 800d150: 64d3 str r3, [r2, #76] @ 0x4c 800d152: e003 b.n 800d15c } else { /* set overall return value */ status = ret; 800d154: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d158: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800d15c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d160: e9d3 2300 ldrd r2, r3, [r3] 800d164: f402 0380 and.w r3, r2, #4194304 @ 0x400000 800d168: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800d16c: 2300 movs r3, #0 800d16e: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800d172: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800d176: 460b mov r3, r1 800d178: 4313 orrs r3, r2 800d17a: f000 809f beq.w 800d2bc { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800d17e: 4b4b ldr r3, [pc, #300] @ (800d2ac ) 800d180: 681b ldr r3, [r3, #0] 800d182: 4a4a ldr r2, [pc, #296] @ (800d2ac ) 800d184: f443 7380 orr.w r3, r3, #256 @ 0x100 800d188: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800d18a: f7f8 fe47 bl 8005e1c 800d18e: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800d192: e00b b.n 800d1ac { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800d194: f7f8 fe42 bl 8005e1c 800d198: 4602 mov r2, r0 800d19a: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800d19e: 1ad3 subs r3, r2, r3 800d1a0: 2b64 cmp r3, #100 @ 0x64 800d1a2: d903 bls.n 800d1ac { ret = HAL_TIMEOUT; 800d1a4: 2303 movs r3, #3 800d1a6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d1aa: e005 b.n 800d1b8 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800d1ac: 4b3f ldr r3, [pc, #252] @ (800d2ac ) 800d1ae: 681b ldr r3, [r3, #0] 800d1b0: f403 7380 and.w r3, r3, #256 @ 0x100 800d1b4: 2b00 cmp r3, #0 800d1b6: d0ed beq.n 800d194 } } if (ret == HAL_OK) 800d1b8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d1bc: 2b00 cmp r3, #0 800d1be: d179 bne.n 800d2b4 { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800d1c0: 4b39 ldr r3, [pc, #228] @ (800d2a8 ) 800d1c2: 6f1a ldr r2, [r3, #112] @ 0x70 800d1c4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1c8: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d1cc: 4053 eors r3, r2 800d1ce: f403 7340 and.w r3, r3, #768 @ 0x300 800d1d2: 2b00 cmp r3, #0 800d1d4: d015 beq.n 800d202 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800d1d6: 4b34 ldr r3, [pc, #208] @ (800d2a8 ) 800d1d8: 6f1b ldr r3, [r3, #112] @ 0x70 800d1da: f423 7340 bic.w r3, r3, #768 @ 0x300 800d1de: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800d1e2: 4b31 ldr r3, [pc, #196] @ (800d2a8 ) 800d1e4: 6f1b ldr r3, [r3, #112] @ 0x70 800d1e6: 4a30 ldr r2, [pc, #192] @ (800d2a8 ) 800d1e8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800d1ec: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800d1ee: 4b2e ldr r3, [pc, #184] @ (800d2a8 ) 800d1f0: 6f1b ldr r3, [r3, #112] @ 0x70 800d1f2: 4a2d ldr r2, [pc, #180] @ (800d2a8 ) 800d1f4: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800d1f8: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800d1fa: 4a2b ldr r2, [pc, #172] @ (800d2a8 ) 800d1fc: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800d200: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800d202: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d206: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d20a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d20e: d118 bne.n 800d242 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800d210: f7f8 fe04 bl 8005e1c 800d214: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800d218: e00d b.n 800d236 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800d21a: f7f8 fdff bl 8005e1c 800d21e: 4602 mov r2, r0 800d220: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800d224: 1ad2 subs r2, r2, r3 800d226: f241 3388 movw r3, #5000 @ 0x1388 800d22a: 429a cmp r2, r3 800d22c: d903 bls.n 800d236 { ret = HAL_TIMEOUT; 800d22e: 2303 movs r3, #3 800d230: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d234: e005 b.n 800d242 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800d236: 4b1c ldr r3, [pc, #112] @ (800d2a8 ) 800d238: 6f1b ldr r3, [r3, #112] @ 0x70 800d23a: f003 0302 and.w r3, r3, #2 800d23e: 2b00 cmp r3, #0 800d240: d0eb beq.n 800d21a } } } if (ret == HAL_OK) 800d242: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d246: 2b00 cmp r3, #0 800d248: d129 bne.n 800d29e { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800d24a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d24e: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d252: f403 7340 and.w r3, r3, #768 @ 0x300 800d256: f5b3 7f40 cmp.w r3, #768 @ 0x300 800d25a: d10e bne.n 800d27a 800d25c: 4b12 ldr r3, [pc, #72] @ (800d2a8 ) 800d25e: 691b ldr r3, [r3, #16] 800d260: f423 517c bic.w r1, r3, #16128 @ 0x3f00 800d264: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d268: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d26c: 091a lsrs r2, r3, #4 800d26e: 4b10 ldr r3, [pc, #64] @ (800d2b0 ) 800d270: 4013 ands r3, r2 800d272: 4a0d ldr r2, [pc, #52] @ (800d2a8 ) 800d274: 430b orrs r3, r1 800d276: 6113 str r3, [r2, #16] 800d278: e005 b.n 800d286 800d27a: 4b0b ldr r3, [pc, #44] @ (800d2a8 ) 800d27c: 691b ldr r3, [r3, #16] 800d27e: 4a0a ldr r2, [pc, #40] @ (800d2a8 ) 800d280: f423 537c bic.w r3, r3, #16128 @ 0x3f00 800d284: 6113 str r3, [r2, #16] 800d286: 4b08 ldr r3, [pc, #32] @ (800d2a8 ) 800d288: 6f19 ldr r1, [r3, #112] @ 0x70 800d28a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d28e: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d292: f3c3 030b ubfx r3, r3, #0, #12 800d296: 4a04 ldr r2, [pc, #16] @ (800d2a8 ) 800d298: 430b orrs r3, r1 800d29a: 6713 str r3, [r2, #112] @ 0x70 800d29c: e00e b.n 800d2bc } else { /* set overall return value */ status = ret; 800d29e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d2a2: f887 311e strb.w r3, [r7, #286] @ 0x11e 800d2a6: e009 b.n 800d2bc 800d2a8: 58024400 .word 0x58024400 800d2ac: 58024800 .word 0x58024800 800d2b0: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 800d2b4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d2b8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800d2bc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2c0: e9d3 2300 ldrd r2, r3, [r3] 800d2c4: f002 0301 and.w r3, r2, #1 800d2c8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800d2cc: 2300 movs r3, #0 800d2ce: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800d2d2: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 800d2d6: 460b mov r3, r1 800d2d8: 4313 orrs r3, r2 800d2da: f000 8089 beq.w 800d3f0 { switch (PeriphClkInit->Usart16ClockSelection) 800d2de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2e2: 6fdb ldr r3, [r3, #124] @ 0x7c 800d2e4: 2b28 cmp r3, #40 @ 0x28 800d2e6: d86b bhi.n 800d3c0 800d2e8: a201 add r2, pc, #4 @ (adr r2, 800d2f0 ) 800d2ea: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d2ee: bf00 nop 800d2f0: 0800d3c9 .word 0x0800d3c9 800d2f4: 0800d3c1 .word 0x0800d3c1 800d2f8: 0800d3c1 .word 0x0800d3c1 800d2fc: 0800d3c1 .word 0x0800d3c1 800d300: 0800d3c1 .word 0x0800d3c1 800d304: 0800d3c1 .word 0x0800d3c1 800d308: 0800d3c1 .word 0x0800d3c1 800d30c: 0800d3c1 .word 0x0800d3c1 800d310: 0800d395 .word 0x0800d395 800d314: 0800d3c1 .word 0x0800d3c1 800d318: 0800d3c1 .word 0x0800d3c1 800d31c: 0800d3c1 .word 0x0800d3c1 800d320: 0800d3c1 .word 0x0800d3c1 800d324: 0800d3c1 .word 0x0800d3c1 800d328: 0800d3c1 .word 0x0800d3c1 800d32c: 0800d3c1 .word 0x0800d3c1 800d330: 0800d3ab .word 0x0800d3ab 800d334: 0800d3c1 .word 0x0800d3c1 800d338: 0800d3c1 .word 0x0800d3c1 800d33c: 0800d3c1 .word 0x0800d3c1 800d340: 0800d3c1 .word 0x0800d3c1 800d344: 0800d3c1 .word 0x0800d3c1 800d348: 0800d3c1 .word 0x0800d3c1 800d34c: 0800d3c1 .word 0x0800d3c1 800d350: 0800d3c9 .word 0x0800d3c9 800d354: 0800d3c1 .word 0x0800d3c1 800d358: 0800d3c1 .word 0x0800d3c1 800d35c: 0800d3c1 .word 0x0800d3c1 800d360: 0800d3c1 .word 0x0800d3c1 800d364: 0800d3c1 .word 0x0800d3c1 800d368: 0800d3c1 .word 0x0800d3c1 800d36c: 0800d3c1 .word 0x0800d3c1 800d370: 0800d3c9 .word 0x0800d3c9 800d374: 0800d3c1 .word 0x0800d3c1 800d378: 0800d3c1 .word 0x0800d3c1 800d37c: 0800d3c1 .word 0x0800d3c1 800d380: 0800d3c1 .word 0x0800d3c1 800d384: 0800d3c1 .word 0x0800d3c1 800d388: 0800d3c1 .word 0x0800d3c1 800d38c: 0800d3c1 .word 0x0800d3c1 800d390: 0800d3c9 .word 0x0800d3c9 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d394: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d398: 3308 adds r3, #8 800d39a: 2101 movs r1, #1 800d39c: 4618 mov r0, r3 800d39e: f001 fe79 bl 800f094 800d3a2: 4603 mov r3, r0 800d3a4: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d3a8: e00f b.n 800d3ca case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d3aa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3ae: 3328 adds r3, #40 @ 0x28 800d3b0: 2101 movs r1, #1 800d3b2: 4618 mov r0, r3 800d3b4: f001 ff20 bl 800f1f8 800d3b8: 4603 mov r3, r0 800d3ba: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d3be: e004 b.n 800d3ca /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d3c0: 2301 movs r3, #1 800d3c2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d3c6: e000 b.n 800d3ca break; 800d3c8: bf00 nop } if (ret == HAL_OK) 800d3ca: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d3ce: 2b00 cmp r3, #0 800d3d0: d10a bne.n 800d3e8 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800d3d2: 4bbf ldr r3, [pc, #764] @ (800d6d0 ) 800d3d4: 6d5b ldr r3, [r3, #84] @ 0x54 800d3d6: f023 0138 bic.w r1, r3, #56 @ 0x38 800d3da: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3de: 6fdb ldr r3, [r3, #124] @ 0x7c 800d3e0: 4abb ldr r2, [pc, #748] @ (800d6d0 ) 800d3e2: 430b orrs r3, r1 800d3e4: 6553 str r3, [r2, #84] @ 0x54 800d3e6: e003 b.n 800d3f0 } else { /* set overall return value */ status = ret; 800d3e8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d3ec: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800d3f0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3f4: e9d3 2300 ldrd r2, r3, [r3] 800d3f8: f002 0302 and.w r3, r2, #2 800d3fc: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800d400: 2300 movs r3, #0 800d402: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800d406: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800d40a: 460b mov r3, r1 800d40c: 4313 orrs r3, r2 800d40e: d041 beq.n 800d494 { switch (PeriphClkInit->Usart234578ClockSelection) 800d410: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d414: 6f9b ldr r3, [r3, #120] @ 0x78 800d416: 2b05 cmp r3, #5 800d418: d824 bhi.n 800d464 800d41a: a201 add r2, pc, #4 @ (adr r2, 800d420 ) 800d41c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d420: 0800d46d .word 0x0800d46d 800d424: 0800d439 .word 0x0800d439 800d428: 0800d44f .word 0x0800d44f 800d42c: 0800d46d .word 0x0800d46d 800d430: 0800d46d .word 0x0800d46d 800d434: 0800d46d .word 0x0800d46d case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d438: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d43c: 3308 adds r3, #8 800d43e: 2101 movs r1, #1 800d440: 4618 mov r0, r3 800d442: f001 fe27 bl 800f094 800d446: 4603 mov r3, r0 800d448: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d44c: e00f b.n 800d46e case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d44e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d452: 3328 adds r3, #40 @ 0x28 800d454: 2101 movs r1, #1 800d456: 4618 mov r0, r3 800d458: f001 fece bl 800f1f8 800d45c: 4603 mov r3, r0 800d45e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d462: e004 b.n 800d46e /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d464: 2301 movs r3, #1 800d466: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d46a: e000 b.n 800d46e break; 800d46c: bf00 nop } if (ret == HAL_OK) 800d46e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d472: 2b00 cmp r3, #0 800d474: d10a bne.n 800d48c { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800d476: 4b96 ldr r3, [pc, #600] @ (800d6d0 ) 800d478: 6d5b ldr r3, [r3, #84] @ 0x54 800d47a: f023 0107 bic.w r1, r3, #7 800d47e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d482: 6f9b ldr r3, [r3, #120] @ 0x78 800d484: 4a92 ldr r2, [pc, #584] @ (800d6d0 ) 800d486: 430b orrs r3, r1 800d488: 6553 str r3, [r2, #84] @ 0x54 800d48a: e003 b.n 800d494 } else { /* set overall return value */ status = ret; 800d48c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d490: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800d494: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d498: e9d3 2300 ldrd r2, r3, [r3] 800d49c: f002 0304 and.w r3, r2, #4 800d4a0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800d4a4: 2300 movs r3, #0 800d4a6: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800d4aa: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 800d4ae: 460b mov r3, r1 800d4b0: 4313 orrs r3, r2 800d4b2: d044 beq.n 800d53e { switch (PeriphClkInit->Lpuart1ClockSelection) 800d4b4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4b8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d4bc: 2b05 cmp r3, #5 800d4be: d825 bhi.n 800d50c 800d4c0: a201 add r2, pc, #4 @ (adr r2, 800d4c8 ) 800d4c2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d4c6: bf00 nop 800d4c8: 0800d515 .word 0x0800d515 800d4cc: 0800d4e1 .word 0x0800d4e1 800d4d0: 0800d4f7 .word 0x0800d4f7 800d4d4: 0800d515 .word 0x0800d515 800d4d8: 0800d515 .word 0x0800d515 800d4dc: 0800d515 .word 0x0800d515 case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d4e0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4e4: 3308 adds r3, #8 800d4e6: 2101 movs r1, #1 800d4e8: 4618 mov r0, r3 800d4ea: f001 fdd3 bl 800f094 800d4ee: 4603 mov r3, r0 800d4f0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d4f4: e00f b.n 800d516 case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d4f6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4fa: 3328 adds r3, #40 @ 0x28 800d4fc: 2101 movs r1, #1 800d4fe: 4618 mov r0, r3 800d500: f001 fe7a bl 800f1f8 800d504: 4603 mov r3, r0 800d506: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d50a: e004 b.n 800d516 /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d50c: 2301 movs r3, #1 800d50e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d512: e000 b.n 800d516 break; 800d514: bf00 nop } if (ret == HAL_OK) 800d516: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d51a: 2b00 cmp r3, #0 800d51c: d10b bne.n 800d536 { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800d51e: 4b6c ldr r3, [pc, #432] @ (800d6d0 ) 800d520: 6d9b ldr r3, [r3, #88] @ 0x58 800d522: f023 0107 bic.w r1, r3, #7 800d526: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d52a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d52e: 4a68 ldr r2, [pc, #416] @ (800d6d0 ) 800d530: 430b orrs r3, r1 800d532: 6593 str r3, [r2, #88] @ 0x58 800d534: e003 b.n 800d53e } else { /* set overall return value */ status = ret; 800d536: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d53a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800d53e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d542: e9d3 2300 ldrd r2, r3, [r3] 800d546: f002 0320 and.w r3, r2, #32 800d54a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800d54e: 2300 movs r3, #0 800d550: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800d554: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800d558: 460b mov r3, r1 800d55a: 4313 orrs r3, r2 800d55c: d055 beq.n 800d60a { switch (PeriphClkInit->Lptim1ClockSelection) 800d55e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d562: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d566: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d56a: d033 beq.n 800d5d4 800d56c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d570: d82c bhi.n 800d5cc 800d572: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d576: d02f beq.n 800d5d8 800d578: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d57c: d826 bhi.n 800d5cc 800d57e: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d582: d02b beq.n 800d5dc 800d584: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d588: d820 bhi.n 800d5cc 800d58a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d58e: d012 beq.n 800d5b6 800d590: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d594: d81a bhi.n 800d5cc 800d596: 2b00 cmp r3, #0 800d598: d022 beq.n 800d5e0 800d59a: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d59e: d115 bne.n 800d5cc /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d5a0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5a4: 3308 adds r3, #8 800d5a6: 2100 movs r1, #0 800d5a8: 4618 mov r0, r3 800d5aa: f001 fd73 bl 800f094 800d5ae: 4603 mov r3, r0 800d5b0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d5b4: e015 b.n 800d5e2 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d5b6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5ba: 3328 adds r3, #40 @ 0x28 800d5bc: 2102 movs r1, #2 800d5be: 4618 mov r0, r3 800d5c0: f001 fe1a bl 800f1f8 800d5c4: 4603 mov r3, r0 800d5c6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d5ca: e00a b.n 800d5e2 /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d5cc: 2301 movs r3, #1 800d5ce: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d5d2: e006 b.n 800d5e2 break; 800d5d4: bf00 nop 800d5d6: e004 b.n 800d5e2 break; 800d5d8: bf00 nop 800d5da: e002 b.n 800d5e2 break; 800d5dc: bf00 nop 800d5de: e000 b.n 800d5e2 break; 800d5e0: bf00 nop } if (ret == HAL_OK) 800d5e2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5e6: 2b00 cmp r3, #0 800d5e8: d10b bne.n 800d602 { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800d5ea: 4b39 ldr r3, [pc, #228] @ (800d6d0 ) 800d5ec: 6d5b ldr r3, [r3, #84] @ 0x54 800d5ee: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d5f2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5f6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d5fa: 4a35 ldr r2, [pc, #212] @ (800d6d0 ) 800d5fc: 430b orrs r3, r1 800d5fe: 6553 str r3, [r2, #84] @ 0x54 800d600: e003 b.n 800d60a } else { /* set overall return value */ status = ret; 800d602: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d606: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800d60a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d60e: e9d3 2300 ldrd r2, r3, [r3] 800d612: f002 0340 and.w r3, r2, #64 @ 0x40 800d616: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800d61a: 2300 movs r3, #0 800d61c: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800d620: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 800d624: 460b mov r3, r1 800d626: 4313 orrs r3, r2 800d628: d058 beq.n 800d6dc { switch (PeriphClkInit->Lptim2ClockSelection) 800d62a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d62e: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d632: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d636: d033 beq.n 800d6a0 800d638: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d63c: d82c bhi.n 800d698 800d63e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d642: d02f beq.n 800d6a4 800d644: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d648: d826 bhi.n 800d698 800d64a: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d64e: d02b beq.n 800d6a8 800d650: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d654: d820 bhi.n 800d698 800d656: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d65a: d012 beq.n 800d682 800d65c: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d660: d81a bhi.n 800d698 800d662: 2b00 cmp r3, #0 800d664: d022 beq.n 800d6ac 800d666: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d66a: d115 bne.n 800d698 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d66c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d670: 3308 adds r3, #8 800d672: 2100 movs r1, #0 800d674: 4618 mov r0, r3 800d676: f001 fd0d bl 800f094 800d67a: 4603 mov r3, r0 800d67c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d680: e015 b.n 800d6ae case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d682: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d686: 3328 adds r3, #40 @ 0x28 800d688: 2102 movs r1, #2 800d68a: 4618 mov r0, r3 800d68c: f001 fdb4 bl 800f1f8 800d690: 4603 mov r3, r0 800d692: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d696: e00a b.n 800d6ae /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d698: 2301 movs r3, #1 800d69a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d69e: e006 b.n 800d6ae break; 800d6a0: bf00 nop 800d6a2: e004 b.n 800d6ae break; 800d6a4: bf00 nop 800d6a6: e002 b.n 800d6ae break; 800d6a8: bf00 nop 800d6aa: e000 b.n 800d6ae break; 800d6ac: bf00 nop } if (ret == HAL_OK) 800d6ae: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d6b2: 2b00 cmp r3, #0 800d6b4: d10e bne.n 800d6d4 { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800d6b6: 4b06 ldr r3, [pc, #24] @ (800d6d0 ) 800d6b8: 6d9b ldr r3, [r3, #88] @ 0x58 800d6ba: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 800d6be: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6c2: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d6c6: 4a02 ldr r2, [pc, #8] @ (800d6d0 ) 800d6c8: 430b orrs r3, r1 800d6ca: 6593 str r3, [r2, #88] @ 0x58 800d6cc: e006 b.n 800d6dc 800d6ce: bf00 nop 800d6d0: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800d6d4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d6d8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800d6dc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6e0: e9d3 2300 ldrd r2, r3, [r3] 800d6e4: f002 0380 and.w r3, r2, #128 @ 0x80 800d6e8: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800d6ec: 2300 movs r3, #0 800d6ee: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800d6f2: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800d6f6: 460b mov r3, r1 800d6f8: 4313 orrs r3, r2 800d6fa: d055 beq.n 800d7a8 { switch (PeriphClkInit->Lptim345ClockSelection) 800d6fc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d700: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d704: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d708: d033 beq.n 800d772 800d70a: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d70e: d82c bhi.n 800d76a 800d710: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d714: d02f beq.n 800d776 800d716: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d71a: d826 bhi.n 800d76a 800d71c: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d720: d02b beq.n 800d77a 800d722: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d726: d820 bhi.n 800d76a 800d728: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d72c: d012 beq.n 800d754 800d72e: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d732: d81a bhi.n 800d76a 800d734: 2b00 cmp r3, #0 800d736: d022 beq.n 800d77e 800d738: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d73c: d115 bne.n 800d76a case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d73e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d742: 3308 adds r3, #8 800d744: 2100 movs r1, #0 800d746: 4618 mov r0, r3 800d748: f001 fca4 bl 800f094 800d74c: 4603 mov r3, r0 800d74e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d752: e015 b.n 800d780 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d754: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d758: 3328 adds r3, #40 @ 0x28 800d75a: 2102 movs r1, #2 800d75c: 4618 mov r0, r3 800d75e: f001 fd4b bl 800f1f8 800d762: 4603 mov r3, r0 800d764: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d768: e00a b.n 800d780 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d76a: 2301 movs r3, #1 800d76c: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d770: e006 b.n 800d780 break; 800d772: bf00 nop 800d774: e004 b.n 800d780 break; 800d776: bf00 nop 800d778: e002 b.n 800d780 break; 800d77a: bf00 nop 800d77c: e000 b.n 800d780 break; 800d77e: bf00 nop } if (ret == HAL_OK) 800d780: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d784: 2b00 cmp r3, #0 800d786: d10b bne.n 800d7a0 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800d788: 4bbb ldr r3, [pc, #748] @ (800da78 ) 800d78a: 6d9b ldr r3, [r3, #88] @ 0x58 800d78c: f423 4160 bic.w r1, r3, #57344 @ 0xe000 800d790: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d794: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d798: 4ab7 ldr r2, [pc, #732] @ (800da78 ) 800d79a: 430b orrs r3, r1 800d79c: 6593 str r3, [r2, #88] @ 0x58 800d79e: e003 b.n 800d7a8 } else { /* set overall return value */ status = ret; 800d7a0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d7a4: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800d7a8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7ac: e9d3 2300 ldrd r2, r3, [r3] 800d7b0: f002 0308 and.w r3, r2, #8 800d7b4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800d7b8: 2300 movs r3, #0 800d7ba: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800d7be: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 800d7c2: 460b mov r3, r1 800d7c4: 4313 orrs r3, r2 800d7c6: d01e beq.n 800d806 { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 800d7c8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7cc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d7d0: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d7d4: d10c bne.n 800d7f0 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d7d6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7da: 3328 adds r3, #40 @ 0x28 800d7dc: 2102 movs r1, #2 800d7de: 4618 mov r0, r3 800d7e0: f001 fd0a bl 800f1f8 800d7e4: 4603 mov r3, r0 800d7e6: 2b00 cmp r3, #0 800d7e8: d002 beq.n 800d7f0 { status = HAL_ERROR; 800d7ea: 2301 movs r3, #1 800d7ec: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800d7f0: 4ba1 ldr r3, [pc, #644] @ (800da78 ) 800d7f2: 6d5b ldr r3, [r3, #84] @ 0x54 800d7f4: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800d7f8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7fc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d800: 4a9d ldr r2, [pc, #628] @ (800da78 ) 800d802: 430b orrs r3, r1 800d804: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800d806: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d80a: e9d3 2300 ldrd r2, r3, [r3] 800d80e: f002 0310 and.w r3, r2, #16 800d812: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800d816: 2300 movs r3, #0 800d818: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800d81c: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 800d820: 460b mov r3, r1 800d822: 4313 orrs r3, r2 800d824: d01e beq.n 800d864 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800d826: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d82a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d82e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d832: d10c bne.n 800d84e { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d834: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d838: 3328 adds r3, #40 @ 0x28 800d83a: 2102 movs r1, #2 800d83c: 4618 mov r0, r3 800d83e: f001 fcdb bl 800f1f8 800d842: 4603 mov r3, r0 800d844: 2b00 cmp r3, #0 800d846: d002 beq.n 800d84e { status = HAL_ERROR; 800d848: 2301 movs r3, #1 800d84a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800d84e: 4b8a ldr r3, [pc, #552] @ (800da78 ) 800d850: 6d9b ldr r3, [r3, #88] @ 0x58 800d852: f423 7140 bic.w r1, r3, #768 @ 0x300 800d856: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d85a: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d85e: 4a86 ldr r2, [pc, #536] @ (800da78 ) 800d860: 430b orrs r3, r1 800d862: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800d864: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d868: e9d3 2300 ldrd r2, r3, [r3] 800d86c: f402 2300 and.w r3, r2, #524288 @ 0x80000 800d870: 67bb str r3, [r7, #120] @ 0x78 800d872: 2300 movs r3, #0 800d874: 67fb str r3, [r7, #124] @ 0x7c 800d876: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800d87a: 460b mov r3, r1 800d87c: 4313 orrs r3, r2 800d87e: d03e beq.n 800d8fe { switch (PeriphClkInit->AdcClockSelection) 800d880: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d884: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d888: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d88c: d022 beq.n 800d8d4 800d88e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d892: d81b bhi.n 800d8cc 800d894: 2b00 cmp r3, #0 800d896: d003 beq.n 800d8a0 800d898: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d89c: d00b beq.n 800d8b6 800d89e: e015 b.n 800d8cc { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d8a0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8a4: 3308 adds r3, #8 800d8a6: 2100 movs r1, #0 800d8a8: 4618 mov r0, r3 800d8aa: f001 fbf3 bl 800f094 800d8ae: 4603 mov r3, r0 800d8b0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d8b4: e00f b.n 800d8d6 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d8b6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8ba: 3328 adds r3, #40 @ 0x28 800d8bc: 2102 movs r1, #2 800d8be: 4618 mov r0, r3 800d8c0: f001 fc9a bl 800f1f8 800d8c4: 4603 mov r3, r0 800d8c6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d8ca: e004 b.n 800d8d6 /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d8cc: 2301 movs r3, #1 800d8ce: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d8d2: e000 b.n 800d8d6 break; 800d8d4: bf00 nop } if (ret == HAL_OK) 800d8d6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8da: 2b00 cmp r3, #0 800d8dc: d10b bne.n 800d8f6 { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800d8de: 4b66 ldr r3, [pc, #408] @ (800da78 ) 800d8e0: 6d9b ldr r3, [r3, #88] @ 0x58 800d8e2: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800d8e6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8ea: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d8ee: 4a62 ldr r2, [pc, #392] @ (800da78 ) 800d8f0: 430b orrs r3, r1 800d8f2: 6593 str r3, [r2, #88] @ 0x58 800d8f4: e003 b.n 800d8fe } else { /* set overall return value */ status = ret; 800d8f6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8fa: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800d8fe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d902: e9d3 2300 ldrd r2, r3, [r3] 800d906: f402 2380 and.w r3, r2, #262144 @ 0x40000 800d90a: 673b str r3, [r7, #112] @ 0x70 800d90c: 2300 movs r3, #0 800d90e: 677b str r3, [r7, #116] @ 0x74 800d910: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800d914: 460b mov r3, r1 800d916: 4313 orrs r3, r2 800d918: d03b beq.n 800d992 { switch (PeriphClkInit->UsbClockSelection) 800d91a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d91e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d922: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d926: d01f beq.n 800d968 800d928: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d92c: d818 bhi.n 800d960 800d92e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800d932: d003 beq.n 800d93c 800d934: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800d938: d007 beq.n 800d94a 800d93a: e011 b.n 800d960 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d93c: 4b4e ldr r3, [pc, #312] @ (800da78 ) 800d93e: 6adb ldr r3, [r3, #44] @ 0x2c 800d940: 4a4d ldr r2, [pc, #308] @ (800da78 ) 800d942: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d946: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800d948: e00f b.n 800d96a case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d94a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d94e: 3328 adds r3, #40 @ 0x28 800d950: 2101 movs r1, #1 800d952: 4618 mov r0, r3 800d954: f001 fc50 bl 800f1f8 800d958: 4603 mov r3, r0 800d95a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 800d95e: e004 b.n 800d96a /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d960: 2301 movs r3, #1 800d962: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d966: e000 b.n 800d96a break; 800d968: bf00 nop } if (ret == HAL_OK) 800d96a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d96e: 2b00 cmp r3, #0 800d970: d10b bne.n 800d98a { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800d972: 4b41 ldr r3, [pc, #260] @ (800da78 ) 800d974: 6d5b ldr r3, [r3, #84] @ 0x54 800d976: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800d97a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d97e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d982: 4a3d ldr r2, [pc, #244] @ (800da78 ) 800d984: 430b orrs r3, r1 800d986: 6553 str r3, [r2, #84] @ 0x54 800d988: e003 b.n 800d992 } else { /* set overall return value */ status = ret; 800d98a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d98e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 800d992: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d996: e9d3 2300 ldrd r2, r3, [r3] 800d99a: f402 3380 and.w r3, r2, #65536 @ 0x10000 800d99e: 66bb str r3, [r7, #104] @ 0x68 800d9a0: 2300 movs r3, #0 800d9a2: 66fb str r3, [r7, #108] @ 0x6c 800d9a4: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 800d9a8: 460b mov r3, r1 800d9aa: 4313 orrs r3, r2 800d9ac: d031 beq.n 800da12 { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 800d9ae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9b2: 6d1b ldr r3, [r3, #80] @ 0x50 800d9b4: 2b00 cmp r3, #0 800d9b6: d003 beq.n 800d9c0 800d9b8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d9bc: d007 beq.n 800d9ce 800d9be: e011 b.n 800d9e4 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d9c0: 4b2d ldr r3, [pc, #180] @ (800da78 ) 800d9c2: 6adb ldr r3, [r3, #44] @ 0x2c 800d9c4: 4a2c ldr r2, [pc, #176] @ (800da78 ) 800d9c6: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d9ca: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 800d9cc: e00e b.n 800d9ec case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d9ce: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9d2: 3308 adds r3, #8 800d9d4: 2102 movs r1, #2 800d9d6: 4618 mov r0, r3 800d9d8: f001 fb5c bl 800f094 800d9dc: 4603 mov r3, r0 800d9de: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 800d9e2: e003 b.n 800d9ec default: ret = HAL_ERROR; 800d9e4: 2301 movs r3, #1 800d9e6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d9ea: bf00 nop } if (ret == HAL_OK) 800d9ec: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9f0: 2b00 cmp r3, #0 800d9f2: d10a bne.n 800da0a { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 800d9f4: 4b20 ldr r3, [pc, #128] @ (800da78 ) 800d9f6: 6cdb ldr r3, [r3, #76] @ 0x4c 800d9f8: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800d9fc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da00: 6d1b ldr r3, [r3, #80] @ 0x50 800da02: 4a1d ldr r2, [pc, #116] @ (800da78 ) 800da04: 430b orrs r3, r1 800da06: 64d3 str r3, [r2, #76] @ 0x4c 800da08: e003 b.n 800da12 } else { /* set overall return value */ status = ret; 800da0a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da0e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 800da12: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da16: e9d3 2300 ldrd r2, r3, [r3] 800da1a: f402 3300 and.w r3, r2, #131072 @ 0x20000 800da1e: 663b str r3, [r7, #96] @ 0x60 800da20: 2300 movs r3, #0 800da22: 667b str r3, [r7, #100] @ 0x64 800da24: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800da28: 460b mov r3, r1 800da2a: 4313 orrs r3, r2 800da2c: d03b beq.n 800daa6 { switch (PeriphClkInit->RngClockSelection) 800da2e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da32: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800da36: f5b3 7f40 cmp.w r3, #768 @ 0x300 800da3a: d018 beq.n 800da6e 800da3c: f5b3 7f40 cmp.w r3, #768 @ 0x300 800da40: d811 bhi.n 800da66 800da42: f5b3 7f00 cmp.w r3, #512 @ 0x200 800da46: d014 beq.n 800da72 800da48: f5b3 7f00 cmp.w r3, #512 @ 0x200 800da4c: d80b bhi.n 800da66 800da4e: 2b00 cmp r3, #0 800da50: d014 beq.n 800da7c 800da52: f5b3 7f80 cmp.w r3, #256 @ 0x100 800da56: d106 bne.n 800da66 { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800da58: 4b07 ldr r3, [pc, #28] @ (800da78 ) 800da5a: 6adb ldr r3, [r3, #44] @ 0x2c 800da5c: 4a06 ldr r2, [pc, #24] @ (800da78 ) 800da5e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800da62: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800da64: e00b b.n 800da7e /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800da66: 2301 movs r3, #1 800da68: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800da6c: e007 b.n 800da7e break; 800da6e: bf00 nop 800da70: e005 b.n 800da7e break; 800da72: bf00 nop 800da74: e003 b.n 800da7e 800da76: bf00 nop 800da78: 58024400 .word 0x58024400 break; 800da7c: bf00 nop } if (ret == HAL_OK) 800da7e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da82: 2b00 cmp r3, #0 800da84: d10b bne.n 800da9e { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800da86: 4bba ldr r3, [pc, #744] @ (800dd70 ) 800da88: 6d5b ldr r3, [r3, #84] @ 0x54 800da8a: f423 7140 bic.w r1, r3, #768 @ 0x300 800da8e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da92: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800da96: 4ab6 ldr r2, [pc, #728] @ (800dd70 ) 800da98: 430b orrs r3, r1 800da9a: 6553 str r3, [r2, #84] @ 0x54 800da9c: e003 b.n 800daa6 } else { /* set overall return value */ status = ret; 800da9e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800daa2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800daa6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800daaa: e9d3 2300 ldrd r2, r3, [r3] 800daae: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800dab2: 65bb str r3, [r7, #88] @ 0x58 800dab4: 2300 movs r3, #0 800dab6: 65fb str r3, [r7, #92] @ 0x5c 800dab8: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 800dabc: 460b mov r3, r1 800dabe: 4313 orrs r3, r2 800dac0: d009 beq.n 800dad6 { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800dac2: 4bab ldr r3, [pc, #684] @ (800dd70 ) 800dac4: 6d1b ldr r3, [r3, #80] @ 0x50 800dac6: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 800daca: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dace: 6f5b ldr r3, [r3, #116] @ 0x74 800dad0: 4aa7 ldr r2, [pc, #668] @ (800dd70 ) 800dad2: 430b orrs r3, r1 800dad4: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800dad6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dada: e9d3 2300 ldrd r2, r3, [r3] 800dade: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 800dae2: 653b str r3, [r7, #80] @ 0x50 800dae4: 2300 movs r3, #0 800dae6: 657b str r3, [r7, #84] @ 0x54 800dae8: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 800daec: 460b mov r3, r1 800daee: 4313 orrs r3, r2 800daf0: d00a beq.n 800db08 { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 800daf2: 4b9f ldr r3, [pc, #636] @ (800dd70 ) 800daf4: 691b ldr r3, [r3, #16] 800daf6: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800dafa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dafe: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 800db02: 4a9b ldr r2, [pc, #620] @ (800dd70 ) 800db04: 430b orrs r3, r1 800db06: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800db08: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db0c: e9d3 2300 ldrd r2, r3, [r3] 800db10: f402 1300 and.w r3, r2, #2097152 @ 0x200000 800db14: 64bb str r3, [r7, #72] @ 0x48 800db16: 2300 movs r3, #0 800db18: 64fb str r3, [r7, #76] @ 0x4c 800db1a: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 800db1e: 460b mov r3, r1 800db20: 4313 orrs r3, r2 800db22: d009 beq.n 800db38 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800db24: 4b92 ldr r3, [pc, #584] @ (800dd70 ) 800db26: 6d1b ldr r3, [r3, #80] @ 0x50 800db28: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 800db2c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db30: 6edb ldr r3, [r3, #108] @ 0x6c 800db32: 4a8f ldr r2, [pc, #572] @ (800dd70 ) 800db34: 430b orrs r3, r1 800db36: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800db38: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db3c: e9d3 2300 ldrd r2, r3, [r3] 800db40: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800db44: 643b str r3, [r7, #64] @ 0x40 800db46: 2300 movs r3, #0 800db48: 647b str r3, [r7, #68] @ 0x44 800db4a: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 800db4e: 460b mov r3, r1 800db50: 4313 orrs r3, r2 800db52: d00e beq.n 800db72 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800db54: 4b86 ldr r3, [pc, #536] @ (800dd70 ) 800db56: 691b ldr r3, [r3, #16] 800db58: 4a85 ldr r2, [pc, #532] @ (800dd70 ) 800db5a: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800db5e: 6113 str r3, [r2, #16] 800db60: 4b83 ldr r3, [pc, #524] @ (800dd70 ) 800db62: 6919 ldr r1, [r3, #16] 800db64: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db68: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 800db6c: 4a80 ldr r2, [pc, #512] @ (800dd70 ) 800db6e: 430b orrs r3, r1 800db70: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800db72: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db76: e9d3 2300 ldrd r2, r3, [r3] 800db7a: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 800db7e: 63bb str r3, [r7, #56] @ 0x38 800db80: 2300 movs r3, #0 800db82: 63fb str r3, [r7, #60] @ 0x3c 800db84: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 800db88: 460b mov r3, r1 800db8a: 4313 orrs r3, r2 800db8c: d009 beq.n 800dba2 { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800db8e: 4b78 ldr r3, [pc, #480] @ (800dd70 ) 800db90: 6cdb ldr r3, [r3, #76] @ 0x4c 800db92: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800db96: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db9a: 6d5b ldr r3, [r3, #84] @ 0x54 800db9c: 4a74 ldr r2, [pc, #464] @ (800dd70 ) 800db9e: 430b orrs r3, r1 800dba0: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800dba2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dba6: e9d3 2300 ldrd r2, r3, [r3] 800dbaa: f402 0300 and.w r3, r2, #8388608 @ 0x800000 800dbae: 633b str r3, [r7, #48] @ 0x30 800dbb0: 2300 movs r3, #0 800dbb2: 637b str r3, [r7, #52] @ 0x34 800dbb4: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 800dbb8: 460b mov r3, r1 800dbba: 4313 orrs r3, r2 800dbbc: d00a beq.n 800dbd4 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800dbbe: 4b6c ldr r3, [pc, #432] @ (800dd70 ) 800dbc0: 6d5b ldr r3, [r3, #84] @ 0x54 800dbc2: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 800dbc6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbca: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800dbce: 4a68 ldr r2, [pc, #416] @ (800dd70 ) 800dbd0: 430b orrs r3, r1 800dbd2: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 800dbd4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbd8: e9d3 2300 ldrd r2, r3, [r3] 800dbdc: 2100 movs r1, #0 800dbde: 62b9 str r1, [r7, #40] @ 0x28 800dbe0: f003 0301 and.w r3, r3, #1 800dbe4: 62fb str r3, [r7, #44] @ 0x2c 800dbe6: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800dbea: 460b mov r3, r1 800dbec: 4313 orrs r3, r2 800dbee: d011 beq.n 800dc14 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800dbf0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbf4: 3308 adds r3, #8 800dbf6: 2100 movs r1, #0 800dbf8: 4618 mov r0, r3 800dbfa: f001 fa4b bl 800f094 800dbfe: 4603 mov r3, r0 800dc00: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc04: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc08: 2b00 cmp r3, #0 800dc0a: d003 beq.n 800dc14 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc0c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc10: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800dc14: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc18: e9d3 2300 ldrd r2, r3, [r3] 800dc1c: 2100 movs r1, #0 800dc1e: 6239 str r1, [r7, #32] 800dc20: f003 0302 and.w r3, r3, #2 800dc24: 627b str r3, [r7, #36] @ 0x24 800dc26: e9d7 1208 ldrd r1, r2, [r7, #32] 800dc2a: 460b mov r3, r1 800dc2c: 4313 orrs r3, r2 800dc2e: d011 beq.n 800dc54 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800dc30: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc34: 3308 adds r3, #8 800dc36: 2101 movs r1, #1 800dc38: 4618 mov r0, r3 800dc3a: f001 fa2b bl 800f094 800dc3e: 4603 mov r3, r0 800dc40: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc44: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc48: 2b00 cmp r3, #0 800dc4a: d003 beq.n 800dc54 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc4c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc50: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800dc54: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc58: e9d3 2300 ldrd r2, r3, [r3] 800dc5c: 2100 movs r1, #0 800dc5e: 61b9 str r1, [r7, #24] 800dc60: f003 0304 and.w r3, r3, #4 800dc64: 61fb str r3, [r7, #28] 800dc66: e9d7 1206 ldrd r1, r2, [r7, #24] 800dc6a: 460b mov r3, r1 800dc6c: 4313 orrs r3, r2 800dc6e: d011 beq.n 800dc94 { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800dc70: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc74: 3308 adds r3, #8 800dc76: 2102 movs r1, #2 800dc78: 4618 mov r0, r3 800dc7a: f001 fa0b bl 800f094 800dc7e: 4603 mov r3, r0 800dc80: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc84: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc88: 2b00 cmp r3, #0 800dc8a: d003 beq.n 800dc94 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc8c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc90: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800dc94: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc98: e9d3 2300 ldrd r2, r3, [r3] 800dc9c: 2100 movs r1, #0 800dc9e: 6139 str r1, [r7, #16] 800dca0: f003 0308 and.w r3, r3, #8 800dca4: 617b str r3, [r7, #20] 800dca6: e9d7 1204 ldrd r1, r2, [r7, #16] 800dcaa: 460b mov r3, r1 800dcac: 4313 orrs r3, r2 800dcae: d011 beq.n 800dcd4 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800dcb0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcb4: 3328 adds r3, #40 @ 0x28 800dcb6: 2100 movs r1, #0 800dcb8: 4618 mov r0, r3 800dcba: f001 fa9d bl 800f1f8 800dcbe: 4603 mov r3, r0 800dcc0: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dcc4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dcc8: 2b00 cmp r3, #0 800dcca: d003 beq.n 800dcd4 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dccc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dcd0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800dcd4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcd8: e9d3 2300 ldrd r2, r3, [r3] 800dcdc: 2100 movs r1, #0 800dcde: 60b9 str r1, [r7, #8] 800dce0: f003 0310 and.w r3, r3, #16 800dce4: 60fb str r3, [r7, #12] 800dce6: e9d7 1202 ldrd r1, r2, [r7, #8] 800dcea: 460b mov r3, r1 800dcec: 4313 orrs r3, r2 800dcee: d011 beq.n 800dd14 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800dcf0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcf4: 3328 adds r3, #40 @ 0x28 800dcf6: 2101 movs r1, #1 800dcf8: 4618 mov r0, r3 800dcfa: f001 fa7d bl 800f1f8 800dcfe: 4603 mov r3, r0 800dd00: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dd04: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd08: 2b00 cmp r3, #0 800dd0a: d003 beq.n 800dd14 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dd0c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd10: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800dd14: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd18: e9d3 2300 ldrd r2, r3, [r3] 800dd1c: 2100 movs r1, #0 800dd1e: 6039 str r1, [r7, #0] 800dd20: f003 0320 and.w r3, r3, #32 800dd24: 607b str r3, [r7, #4] 800dd26: e9d7 1200 ldrd r1, r2, [r7] 800dd2a: 460b mov r3, r1 800dd2c: 4313 orrs r3, r2 800dd2e: d011 beq.n 800dd54 { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800dd30: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd34: 3328 adds r3, #40 @ 0x28 800dd36: 2102 movs r1, #2 800dd38: 4618 mov r0, r3 800dd3a: f001 fa5d bl 800f1f8 800dd3e: 4603 mov r3, r0 800dd40: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dd44: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd48: 2b00 cmp r3, #0 800dd4a: d003 beq.n 800dd54 /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dd4c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd50: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 800dd54: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800dd58: 2b00 cmp r3, #0 800dd5a: d101 bne.n 800dd60 { return HAL_OK; 800dd5c: 2300 movs r3, #0 800dd5e: e000 b.n 800dd62 } return HAL_ERROR; 800dd60: 2301 movs r3, #1 } 800dd62: 4618 mov r0, r3 800dd64: f507 7790 add.w r7, r7, #288 @ 0x120 800dd68: 46bd mov sp, r7 800dd6a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800dd6e: bf00 nop 800dd70: 58024400 .word 0x58024400 0800dd74 : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800dd74: b580 push {r7, lr} 800dd76: b090 sub sp, #64 @ 0x40 800dd78: af00 add r7, sp, #0 800dd7a: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 800dd7e: e9d7 2300 ldrd r2, r3, [r7] 800dd82: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800dd86: 430b orrs r3, r1 800dd88: f040 8094 bne.w 800deb4 { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800dd8c: 4b9e ldr r3, [pc, #632] @ (800e008 ) 800dd8e: 6d1b ldr r3, [r3, #80] @ 0x50 800dd90: f003 0307 and.w r3, r3, #7 800dd94: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800dd96: 6b3b ldr r3, [r7, #48] @ 0x30 800dd98: 2b04 cmp r3, #4 800dd9a: f200 8087 bhi.w 800deac 800dd9e: a201 add r2, pc, #4 @ (adr r2, 800dda4 ) 800dda0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800dda4: 0800ddb9 .word 0x0800ddb9 800dda8: 0800dde1 .word 0x0800dde1 800ddac: 0800de09 .word 0x0800de09 800ddb0: 0800dea5 .word 0x0800dea5 800ddb4: 0800de31 .word 0x0800de31 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800ddb8: 4b93 ldr r3, [pc, #588] @ (800e008 ) 800ddba: 681b ldr r3, [r3, #0] 800ddbc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800ddc0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ddc4: d108 bne.n 800ddd8 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800ddc6: f107 0324 add.w r3, r7, #36 @ 0x24 800ddca: 4618 mov r0, r3 800ddcc: f001 f810 bl 800edf0 frequency = pll1_clocks.PLL1_Q_Frequency; 800ddd0: 6abb ldr r3, [r7, #40] @ 0x28 800ddd2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ddd4: f000 bd45 b.w 800e862 frequency = 0; 800ddd8: 2300 movs r3, #0 800ddda: 63fb str r3, [r7, #60] @ 0x3c break; 800dddc: f000 bd41 b.w 800e862 } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dde0: 4b89 ldr r3, [pc, #548] @ (800e008 ) 800dde2: 681b ldr r3, [r3, #0] 800dde4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800dde8: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800ddec: d108 bne.n 800de00 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800ddee: f107 0318 add.w r3, r7, #24 800ddf2: 4618 mov r0, r3 800ddf4: f000 fd54 bl 800e8a0 frequency = pll2_clocks.PLL2_P_Frequency; 800ddf8: 69bb ldr r3, [r7, #24] 800ddfa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800ddfc: f000 bd31 b.w 800e862 frequency = 0; 800de00: 2300 movs r3, #0 800de02: 63fb str r3, [r7, #60] @ 0x3c break; 800de04: f000 bd2d b.w 800e862 } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800de08: 4b7f ldr r3, [pc, #508] @ (800e008 ) 800de0a: 681b ldr r3, [r3, #0] 800de0c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800de10: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800de14: d108 bne.n 800de28 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800de16: f107 030c add.w r3, r7, #12 800de1a: 4618 mov r0, r3 800de1c: f000 fe94 bl 800eb48 frequency = pll3_clocks.PLL3_P_Frequency; 800de20: 68fb ldr r3, [r7, #12] 800de22: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de24: f000 bd1d b.w 800e862 frequency = 0; 800de28: 2300 movs r3, #0 800de2a: 63fb str r3, [r7, #60] @ 0x3c break; 800de2c: f000 bd19 b.w 800e862 } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800de30: 4b75 ldr r3, [pc, #468] @ (800e008 ) 800de32: 6cdb ldr r3, [r3, #76] @ 0x4c 800de34: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800de38: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800de3a: 4b73 ldr r3, [pc, #460] @ (800e008 ) 800de3c: 681b ldr r3, [r3, #0] 800de3e: f003 0304 and.w r3, r3, #4 800de42: 2b04 cmp r3, #4 800de44: d10c bne.n 800de60 800de46: 6b7b ldr r3, [r7, #52] @ 0x34 800de48: 2b00 cmp r3, #0 800de4a: d109 bne.n 800de60 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800de4c: 4b6e ldr r3, [pc, #440] @ (800e008 ) 800de4e: 681b ldr r3, [r3, #0] 800de50: 08db lsrs r3, r3, #3 800de52: f003 0303 and.w r3, r3, #3 800de56: 4a6d ldr r2, [pc, #436] @ (800e00c ) 800de58: fa22 f303 lsr.w r3, r2, r3 800de5c: 63fb str r3, [r7, #60] @ 0x3c 800de5e: e01f b.n 800dea0 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800de60: 4b69 ldr r3, [pc, #420] @ (800e008 ) 800de62: 681b ldr r3, [r3, #0] 800de64: f403 7380 and.w r3, r3, #256 @ 0x100 800de68: f5b3 7f80 cmp.w r3, #256 @ 0x100 800de6c: d106 bne.n 800de7c 800de6e: 6b7b ldr r3, [r7, #52] @ 0x34 800de70: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800de74: d102 bne.n 800de7c { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800de76: 4b66 ldr r3, [pc, #408] @ (800e010 ) 800de78: 63fb str r3, [r7, #60] @ 0x3c 800de7a: e011 b.n 800dea0 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800de7c: 4b62 ldr r3, [pc, #392] @ (800e008 ) 800de7e: 681b ldr r3, [r3, #0] 800de80: f403 3300 and.w r3, r3, #131072 @ 0x20000 800de84: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800de88: d106 bne.n 800de98 800de8a: 6b7b ldr r3, [r7, #52] @ 0x34 800de8c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800de90: d102 bne.n 800de98 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800de92: 4b60 ldr r3, [pc, #384] @ (800e014 ) 800de94: 63fb str r3, [r7, #60] @ 0x3c 800de96: e003 b.n 800dea0 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800de98: 2300 movs r3, #0 800de9a: 63fb str r3, [r7, #60] @ 0x3c } break; 800de9c: f000 bce1 b.w 800e862 800dea0: f000 bcdf b.w 800e862 } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800dea4: 4b5c ldr r3, [pc, #368] @ (800e018 ) 800dea6: 63fb str r3, [r7, #60] @ 0x3c break; 800dea8: f000 bcdb b.w 800e862 } default : { frequency = 0; 800deac: 2300 movs r3, #0 800deae: 63fb str r3, [r7, #60] @ 0x3c break; 800deb0: f000 bcd7 b.w 800e862 } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800deb4: e9d7 2300 ldrd r2, r3, [r7] 800deb8: f5a2 7100 sub.w r1, r2, #512 @ 0x200 800debc: 430b orrs r3, r1 800debe: f040 80ad bne.w 800e01c { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800dec2: 4b51 ldr r3, [pc, #324] @ (800e008 ) 800dec4: 6d1b ldr r3, [r3, #80] @ 0x50 800dec6: f403 73e0 and.w r3, r3, #448 @ 0x1c0 800deca: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800decc: 6b3b ldr r3, [r7, #48] @ 0x30 800dece: f5b3 7f80 cmp.w r3, #256 @ 0x100 800ded2: d056 beq.n 800df82 800ded4: 6b3b ldr r3, [r7, #48] @ 0x30 800ded6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800deda: f200 8090 bhi.w 800dffe 800dede: 6b3b ldr r3, [r7, #48] @ 0x30 800dee0: 2bc0 cmp r3, #192 @ 0xc0 800dee2: f000 8088 beq.w 800dff6 800dee6: 6b3b ldr r3, [r7, #48] @ 0x30 800dee8: 2bc0 cmp r3, #192 @ 0xc0 800deea: f200 8088 bhi.w 800dffe 800deee: 6b3b ldr r3, [r7, #48] @ 0x30 800def0: 2b80 cmp r3, #128 @ 0x80 800def2: d032 beq.n 800df5a 800def4: 6b3b ldr r3, [r7, #48] @ 0x30 800def6: 2b80 cmp r3, #128 @ 0x80 800def8: f200 8081 bhi.w 800dffe 800defc: 6b3b ldr r3, [r7, #48] @ 0x30 800defe: 2b00 cmp r3, #0 800df00: d003 beq.n 800df0a 800df02: 6b3b ldr r3, [r7, #48] @ 0x30 800df04: 2b40 cmp r3, #64 @ 0x40 800df06: d014 beq.n 800df32 800df08: e079 b.n 800dffe { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800df0a: 4b3f ldr r3, [pc, #252] @ (800e008 ) 800df0c: 681b ldr r3, [r3, #0] 800df0e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800df12: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800df16: d108 bne.n 800df2a { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800df18: f107 0324 add.w r3, r7, #36 @ 0x24 800df1c: 4618 mov r0, r3 800df1e: f000 ff67 bl 800edf0 frequency = pll1_clocks.PLL1_Q_Frequency; 800df22: 6abb ldr r3, [r7, #40] @ 0x28 800df24: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df26: f000 bc9c b.w 800e862 frequency = 0; 800df2a: 2300 movs r3, #0 800df2c: 63fb str r3, [r7, #60] @ 0x3c break; 800df2e: f000 bc98 b.w 800e862 } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800df32: 4b35 ldr r3, [pc, #212] @ (800e008 ) 800df34: 681b ldr r3, [r3, #0] 800df36: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800df3a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800df3e: d108 bne.n 800df52 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800df40: f107 0318 add.w r3, r7, #24 800df44: 4618 mov r0, r3 800df46: f000 fcab bl 800e8a0 frequency = pll2_clocks.PLL2_P_Frequency; 800df4a: 69bb ldr r3, [r7, #24] 800df4c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df4e: f000 bc88 b.w 800e862 frequency = 0; 800df52: 2300 movs r3, #0 800df54: 63fb str r3, [r7, #60] @ 0x3c break; 800df56: f000 bc84 b.w 800e862 } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800df5a: 4b2b ldr r3, [pc, #172] @ (800e008 ) 800df5c: 681b ldr r3, [r3, #0] 800df5e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800df62: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800df66: d108 bne.n 800df7a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800df68: f107 030c add.w r3, r7, #12 800df6c: 4618 mov r0, r3 800df6e: f000 fdeb bl 800eb48 frequency = pll3_clocks.PLL3_P_Frequency; 800df72: 68fb ldr r3, [r7, #12] 800df74: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df76: f000 bc74 b.w 800e862 frequency = 0; 800df7a: 2300 movs r3, #0 800df7c: 63fb str r3, [r7, #60] @ 0x3c break; 800df7e: f000 bc70 b.w 800e862 } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800df82: 4b21 ldr r3, [pc, #132] @ (800e008 ) 800df84: 6cdb ldr r3, [r3, #76] @ 0x4c 800df86: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800df8a: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800df8c: 4b1e ldr r3, [pc, #120] @ (800e008 ) 800df8e: 681b ldr r3, [r3, #0] 800df90: f003 0304 and.w r3, r3, #4 800df94: 2b04 cmp r3, #4 800df96: d10c bne.n 800dfb2 800df98: 6b7b ldr r3, [r7, #52] @ 0x34 800df9a: 2b00 cmp r3, #0 800df9c: d109 bne.n 800dfb2 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800df9e: 4b1a ldr r3, [pc, #104] @ (800e008 ) 800dfa0: 681b ldr r3, [r3, #0] 800dfa2: 08db lsrs r3, r3, #3 800dfa4: f003 0303 and.w r3, r3, #3 800dfa8: 4a18 ldr r2, [pc, #96] @ (800e00c ) 800dfaa: fa22 f303 lsr.w r3, r2, r3 800dfae: 63fb str r3, [r7, #60] @ 0x3c 800dfb0: e01f b.n 800dff2 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dfb2: 4b15 ldr r3, [pc, #84] @ (800e008 ) 800dfb4: 681b ldr r3, [r3, #0] 800dfb6: f403 7380 and.w r3, r3, #256 @ 0x100 800dfba: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dfbe: d106 bne.n 800dfce 800dfc0: 6b7b ldr r3, [r7, #52] @ 0x34 800dfc2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dfc6: d102 bne.n 800dfce { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800dfc8: 4b11 ldr r3, [pc, #68] @ (800e010 ) 800dfca: 63fb str r3, [r7, #60] @ 0x3c 800dfcc: e011 b.n 800dff2 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dfce: 4b0e ldr r3, [pc, #56] @ (800e008 ) 800dfd0: 681b ldr r3, [r3, #0] 800dfd2: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dfd6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800dfda: d106 bne.n 800dfea 800dfdc: 6b7b ldr r3, [r7, #52] @ 0x34 800dfde: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dfe2: d102 bne.n 800dfea { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800dfe4: 4b0b ldr r3, [pc, #44] @ (800e014 ) 800dfe6: 63fb str r3, [r7, #60] @ 0x3c 800dfe8: e003 b.n 800dff2 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800dfea: 2300 movs r3, #0 800dfec: 63fb str r3, [r7, #60] @ 0x3c } break; 800dfee: f000 bc38 b.w 800e862 800dff2: f000 bc36 b.w 800e862 } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 800dff6: 4b08 ldr r3, [pc, #32] @ (800e018 ) 800dff8: 63fb str r3, [r7, #60] @ 0x3c break; 800dffa: f000 bc32 b.w 800e862 } default : { frequency = 0; 800dffe: 2300 movs r3, #0 800e000: 63fb str r3, [r7, #60] @ 0x3c break; 800e002: f000 bc2e b.w 800e862 800e006: bf00 nop 800e008: 58024400 .word 0x58024400 800e00c: 03d09000 .word 0x03d09000 800e010: 003d0900 .word 0x003d0900 800e014: 017d7840 .word 0x017d7840 800e018: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 800e01c: e9d7 2300 ldrd r2, r3, [r7] 800e020: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 800e024: 430b orrs r3, r1 800e026: f040 809c bne.w 800e162 { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 800e02a: 4b9e ldr r3, [pc, #632] @ (800e2a4 ) 800e02c: 6d9b ldr r3, [r3, #88] @ 0x58 800e02e: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800e032: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800e034: 6b3b ldr r3, [r7, #48] @ 0x30 800e036: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800e03a: d054 beq.n 800e0e6 800e03c: 6b3b ldr r3, [r7, #48] @ 0x30 800e03e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800e042: f200 808b bhi.w 800e15c 800e046: 6b3b ldr r3, [r7, #48] @ 0x30 800e048: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800e04c: f000 8083 beq.w 800e156 800e050: 6b3b ldr r3, [r7, #48] @ 0x30 800e052: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800e056: f200 8081 bhi.w 800e15c 800e05a: 6b3b ldr r3, [r7, #48] @ 0x30 800e05c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800e060: d02f beq.n 800e0c2 800e062: 6b3b ldr r3, [r7, #48] @ 0x30 800e064: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800e068: d878 bhi.n 800e15c 800e06a: 6b3b ldr r3, [r7, #48] @ 0x30 800e06c: 2b00 cmp r3, #0 800e06e: d004 beq.n 800e07a 800e070: 6b3b ldr r3, [r7, #48] @ 0x30 800e072: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800e076: d012 beq.n 800e09e 800e078: e070 b.n 800e15c { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e07a: 4b8a ldr r3, [pc, #552] @ (800e2a4 ) 800e07c: 681b ldr r3, [r3, #0] 800e07e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e082: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e086: d107 bne.n 800e098 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e088: f107 0324 add.w r3, r7, #36 @ 0x24 800e08c: 4618 mov r0, r3 800e08e: f000 feaf bl 800edf0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e092: 6abb ldr r3, [r7, #40] @ 0x28 800e094: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e096: e3e4 b.n 800e862 frequency = 0; 800e098: 2300 movs r3, #0 800e09a: 63fb str r3, [r7, #60] @ 0x3c break; 800e09c: e3e1 b.n 800e862 } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e09e: 4b81 ldr r3, [pc, #516] @ (800e2a4 ) 800e0a0: 681b ldr r3, [r3, #0] 800e0a2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e0a6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e0aa: d107 bne.n 800e0bc { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e0ac: f107 0318 add.w r3, r7, #24 800e0b0: 4618 mov r0, r3 800e0b2: f000 fbf5 bl 800e8a0 frequency = pll2_clocks.PLL2_P_Frequency; 800e0b6: 69bb ldr r3, [r7, #24] 800e0b8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e0ba: e3d2 b.n 800e862 frequency = 0; 800e0bc: 2300 movs r3, #0 800e0be: 63fb str r3, [r7, #60] @ 0x3c break; 800e0c0: e3cf b.n 800e862 } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e0c2: 4b78 ldr r3, [pc, #480] @ (800e2a4 ) 800e0c4: 681b ldr r3, [r3, #0] 800e0c6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e0ca: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e0ce: d107 bne.n 800e0e0 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e0d0: f107 030c add.w r3, r7, #12 800e0d4: 4618 mov r0, r3 800e0d6: f000 fd37 bl 800eb48 frequency = pll3_clocks.PLL3_P_Frequency; 800e0da: 68fb ldr r3, [r7, #12] 800e0dc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e0de: e3c0 b.n 800e862 frequency = 0; 800e0e0: 2300 movs r3, #0 800e0e2: 63fb str r3, [r7, #60] @ 0x3c break; 800e0e4: e3bd b.n 800e862 } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e0e6: 4b6f ldr r3, [pc, #444] @ (800e2a4 ) 800e0e8: 6cdb ldr r3, [r3, #76] @ 0x4c 800e0ea: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e0ee: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e0f0: 4b6c ldr r3, [pc, #432] @ (800e2a4 ) 800e0f2: 681b ldr r3, [r3, #0] 800e0f4: f003 0304 and.w r3, r3, #4 800e0f8: 2b04 cmp r3, #4 800e0fa: d10c bne.n 800e116 800e0fc: 6b7b ldr r3, [r7, #52] @ 0x34 800e0fe: 2b00 cmp r3, #0 800e100: d109 bne.n 800e116 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e102: 4b68 ldr r3, [pc, #416] @ (800e2a4 ) 800e104: 681b ldr r3, [r3, #0] 800e106: 08db lsrs r3, r3, #3 800e108: f003 0303 and.w r3, r3, #3 800e10c: 4a66 ldr r2, [pc, #408] @ (800e2a8 ) 800e10e: fa22 f303 lsr.w r3, r2, r3 800e112: 63fb str r3, [r7, #60] @ 0x3c 800e114: e01e b.n 800e154 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e116: 4b63 ldr r3, [pc, #396] @ (800e2a4 ) 800e118: 681b ldr r3, [r3, #0] 800e11a: f403 7380 and.w r3, r3, #256 @ 0x100 800e11e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e122: d106 bne.n 800e132 800e124: 6b7b ldr r3, [r7, #52] @ 0x34 800e126: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e12a: d102 bne.n 800e132 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e12c: 4b5f ldr r3, [pc, #380] @ (800e2ac ) 800e12e: 63fb str r3, [r7, #60] @ 0x3c 800e130: e010 b.n 800e154 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e132: 4b5c ldr r3, [pc, #368] @ (800e2a4 ) 800e134: 681b ldr r3, [r3, #0] 800e136: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e13a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e13e: d106 bne.n 800e14e 800e140: 6b7b ldr r3, [r7, #52] @ 0x34 800e142: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e146: d102 bne.n 800e14e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e148: 4b59 ldr r3, [pc, #356] @ (800e2b0 ) 800e14a: 63fb str r3, [r7, #60] @ 0x3c 800e14c: e002 b.n 800e154 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e14e: 2300 movs r3, #0 800e150: 63fb str r3, [r7, #60] @ 0x3c } break; 800e152: e386 b.n 800e862 800e154: e385 b.n 800e862 } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800e156: 4b57 ldr r3, [pc, #348] @ (800e2b4 ) 800e158: 63fb str r3, [r7, #60] @ 0x3c break; 800e15a: e382 b.n 800e862 } default : { frequency = 0; 800e15c: 2300 movs r3, #0 800e15e: 63fb str r3, [r7, #60] @ 0x3c break; 800e160: e37f b.n 800e862 } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800e162: e9d7 2300 ldrd r2, r3, [r7] 800e166: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 800e16a: 430b orrs r3, r1 800e16c: f040 80a7 bne.w 800e2be { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 800e170: 4b4c ldr r3, [pc, #304] @ (800e2a4 ) 800e172: 6d9b ldr r3, [r3, #88] @ 0x58 800e174: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 800e178: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800e17a: 6b3b ldr r3, [r7, #48] @ 0x30 800e17c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800e180: d055 beq.n 800e22e 800e182: 6b3b ldr r3, [r7, #48] @ 0x30 800e184: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800e188: f200 8096 bhi.w 800e2b8 800e18c: 6b3b ldr r3, [r7, #48] @ 0x30 800e18e: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800e192: f000 8084 beq.w 800e29e 800e196: 6b3b ldr r3, [r7, #48] @ 0x30 800e198: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800e19c: f200 808c bhi.w 800e2b8 800e1a0: 6b3b ldr r3, [r7, #48] @ 0x30 800e1a2: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e1a6: d030 beq.n 800e20a 800e1a8: 6b3b ldr r3, [r7, #48] @ 0x30 800e1aa: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e1ae: f200 8083 bhi.w 800e2b8 800e1b2: 6b3b ldr r3, [r7, #48] @ 0x30 800e1b4: 2b00 cmp r3, #0 800e1b6: d004 beq.n 800e1c2 800e1b8: 6b3b ldr r3, [r7, #48] @ 0x30 800e1ba: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800e1be: d012 beq.n 800e1e6 800e1c0: e07a b.n 800e2b8 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e1c2: 4b38 ldr r3, [pc, #224] @ (800e2a4 ) 800e1c4: 681b ldr r3, [r3, #0] 800e1c6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e1ca: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e1ce: d107 bne.n 800e1e0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e1d0: f107 0324 add.w r3, r7, #36 @ 0x24 800e1d4: 4618 mov r0, r3 800e1d6: f000 fe0b bl 800edf0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e1da: 6abb ldr r3, [r7, #40] @ 0x28 800e1dc: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e1de: e340 b.n 800e862 frequency = 0; 800e1e0: 2300 movs r3, #0 800e1e2: 63fb str r3, [r7, #60] @ 0x3c break; 800e1e4: e33d b.n 800e862 } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e1e6: 4b2f ldr r3, [pc, #188] @ (800e2a4 ) 800e1e8: 681b ldr r3, [r3, #0] 800e1ea: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e1ee: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e1f2: d107 bne.n 800e204 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e1f4: f107 0318 add.w r3, r7, #24 800e1f8: 4618 mov r0, r3 800e1fa: f000 fb51 bl 800e8a0 frequency = pll2_clocks.PLL2_P_Frequency; 800e1fe: 69bb ldr r3, [r7, #24] 800e200: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e202: e32e b.n 800e862 frequency = 0; 800e204: 2300 movs r3, #0 800e206: 63fb str r3, [r7, #60] @ 0x3c break; 800e208: e32b b.n 800e862 } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e20a: 4b26 ldr r3, [pc, #152] @ (800e2a4 ) 800e20c: 681b ldr r3, [r3, #0] 800e20e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e212: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e216: d107 bne.n 800e228 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e218: f107 030c add.w r3, r7, #12 800e21c: 4618 mov r0, r3 800e21e: f000 fc93 bl 800eb48 frequency = pll3_clocks.PLL3_P_Frequency; 800e222: 68fb ldr r3, [r7, #12] 800e224: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e226: e31c b.n 800e862 frequency = 0; 800e228: 2300 movs r3, #0 800e22a: 63fb str r3, [r7, #60] @ 0x3c break; 800e22c: e319 b.n 800e862 } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e22e: 4b1d ldr r3, [pc, #116] @ (800e2a4 ) 800e230: 6cdb ldr r3, [r3, #76] @ 0x4c 800e232: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e236: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e238: 4b1a ldr r3, [pc, #104] @ (800e2a4 ) 800e23a: 681b ldr r3, [r3, #0] 800e23c: f003 0304 and.w r3, r3, #4 800e240: 2b04 cmp r3, #4 800e242: d10c bne.n 800e25e 800e244: 6b7b ldr r3, [r7, #52] @ 0x34 800e246: 2b00 cmp r3, #0 800e248: d109 bne.n 800e25e { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e24a: 4b16 ldr r3, [pc, #88] @ (800e2a4 ) 800e24c: 681b ldr r3, [r3, #0] 800e24e: 08db lsrs r3, r3, #3 800e250: f003 0303 and.w r3, r3, #3 800e254: 4a14 ldr r2, [pc, #80] @ (800e2a8 ) 800e256: fa22 f303 lsr.w r3, r2, r3 800e25a: 63fb str r3, [r7, #60] @ 0x3c 800e25c: e01e b.n 800e29c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e25e: 4b11 ldr r3, [pc, #68] @ (800e2a4 ) 800e260: 681b ldr r3, [r3, #0] 800e262: f403 7380 and.w r3, r3, #256 @ 0x100 800e266: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e26a: d106 bne.n 800e27a 800e26c: 6b7b ldr r3, [r7, #52] @ 0x34 800e26e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e272: d102 bne.n 800e27a { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e274: 4b0d ldr r3, [pc, #52] @ (800e2ac ) 800e276: 63fb str r3, [r7, #60] @ 0x3c 800e278: e010 b.n 800e29c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e27a: 4b0a ldr r3, [pc, #40] @ (800e2a4 ) 800e27c: 681b ldr r3, [r3, #0] 800e27e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e282: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e286: d106 bne.n 800e296 800e288: 6b7b ldr r3, [r7, #52] @ 0x34 800e28a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e28e: d102 bne.n 800e296 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e290: 4b07 ldr r3, [pc, #28] @ (800e2b0 ) 800e292: 63fb str r3, [r7, #60] @ 0x3c 800e294: e002 b.n 800e29c } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e296: 2300 movs r3, #0 800e298: 63fb str r3, [r7, #60] @ 0x3c } break; 800e29a: e2e2 b.n 800e862 800e29c: e2e1 b.n 800e862 } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 800e29e: 4b05 ldr r3, [pc, #20] @ (800e2b4 ) 800e2a0: 63fb str r3, [r7, #60] @ 0x3c break; 800e2a2: e2de b.n 800e862 800e2a4: 58024400 .word 0x58024400 800e2a8: 03d09000 .word 0x03d09000 800e2ac: 003d0900 .word 0x003d0900 800e2b0: 017d7840 .word 0x017d7840 800e2b4: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 800e2b8: 2300 movs r3, #0 800e2ba: 63fb str r3, [r7, #60] @ 0x3c break; 800e2bc: e2d1 b.n 800e862 } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800e2be: e9d7 2300 ldrd r2, r3, [r7] 800e2c2: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800e2c6: 430b orrs r3, r1 800e2c8: f040 809c bne.w 800e404 { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800e2cc: 4b93 ldr r3, [pc, #588] @ (800e51c ) 800e2ce: 6d1b ldr r3, [r3, #80] @ 0x50 800e2d0: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e2d4: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e2d6: 6bbb ldr r3, [r7, #56] @ 0x38 800e2d8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800e2dc: d054 beq.n 800e388 800e2de: 6bbb ldr r3, [r7, #56] @ 0x38 800e2e0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800e2e4: f200 808b bhi.w 800e3fe 800e2e8: 6bbb ldr r3, [r7, #56] @ 0x38 800e2ea: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800e2ee: f000 8083 beq.w 800e3f8 800e2f2: 6bbb ldr r3, [r7, #56] @ 0x38 800e2f4: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800e2f8: f200 8081 bhi.w 800e3fe 800e2fc: 6bbb ldr r3, [r7, #56] @ 0x38 800e2fe: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e302: d02f beq.n 800e364 800e304: 6bbb ldr r3, [r7, #56] @ 0x38 800e306: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e30a: d878 bhi.n 800e3fe 800e30c: 6bbb ldr r3, [r7, #56] @ 0x38 800e30e: 2b00 cmp r3, #0 800e310: d004 beq.n 800e31c 800e312: 6bbb ldr r3, [r7, #56] @ 0x38 800e314: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800e318: d012 beq.n 800e340 800e31a: e070 b.n 800e3fe { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e31c: 4b7f ldr r3, [pc, #508] @ (800e51c ) 800e31e: 681b ldr r3, [r3, #0] 800e320: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e324: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e328: d107 bne.n 800e33a { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e32a: f107 0324 add.w r3, r7, #36 @ 0x24 800e32e: 4618 mov r0, r3 800e330: f000 fd5e bl 800edf0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e334: 6abb ldr r3, [r7, #40] @ 0x28 800e336: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e338: e293 b.n 800e862 frequency = 0; 800e33a: 2300 movs r3, #0 800e33c: 63fb str r3, [r7, #60] @ 0x3c break; 800e33e: e290 b.n 800e862 } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e340: 4b76 ldr r3, [pc, #472] @ (800e51c ) 800e342: 681b ldr r3, [r3, #0] 800e344: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e348: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e34c: d107 bne.n 800e35e { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e34e: f107 0318 add.w r3, r7, #24 800e352: 4618 mov r0, r3 800e354: f000 faa4 bl 800e8a0 frequency = pll2_clocks.PLL2_P_Frequency; 800e358: 69bb ldr r3, [r7, #24] 800e35a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e35c: e281 b.n 800e862 frequency = 0; 800e35e: 2300 movs r3, #0 800e360: 63fb str r3, [r7, #60] @ 0x3c break; 800e362: e27e b.n 800e862 } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e364: 4b6d ldr r3, [pc, #436] @ (800e51c ) 800e366: 681b ldr r3, [r3, #0] 800e368: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e36c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e370: d107 bne.n 800e382 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e372: f107 030c add.w r3, r7, #12 800e376: 4618 mov r0, r3 800e378: f000 fbe6 bl 800eb48 frequency = pll3_clocks.PLL3_P_Frequency; 800e37c: 68fb ldr r3, [r7, #12] 800e37e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e380: e26f b.n 800e862 frequency = 0; 800e382: 2300 movs r3, #0 800e384: 63fb str r3, [r7, #60] @ 0x3c break; 800e386: e26c b.n 800e862 } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e388: 4b64 ldr r3, [pc, #400] @ (800e51c ) 800e38a: 6cdb ldr r3, [r3, #76] @ 0x4c 800e38c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e390: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e392: 4b62 ldr r3, [pc, #392] @ (800e51c ) 800e394: 681b ldr r3, [r3, #0] 800e396: f003 0304 and.w r3, r3, #4 800e39a: 2b04 cmp r3, #4 800e39c: d10c bne.n 800e3b8 800e39e: 6b7b ldr r3, [r7, #52] @ 0x34 800e3a0: 2b00 cmp r3, #0 800e3a2: d109 bne.n 800e3b8 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e3a4: 4b5d ldr r3, [pc, #372] @ (800e51c ) 800e3a6: 681b ldr r3, [r3, #0] 800e3a8: 08db lsrs r3, r3, #3 800e3aa: f003 0303 and.w r3, r3, #3 800e3ae: 4a5c ldr r2, [pc, #368] @ (800e520 ) 800e3b0: fa22 f303 lsr.w r3, r2, r3 800e3b4: 63fb str r3, [r7, #60] @ 0x3c 800e3b6: e01e b.n 800e3f6 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e3b8: 4b58 ldr r3, [pc, #352] @ (800e51c ) 800e3ba: 681b ldr r3, [r3, #0] 800e3bc: f403 7380 and.w r3, r3, #256 @ 0x100 800e3c0: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e3c4: d106 bne.n 800e3d4 800e3c6: 6b7b ldr r3, [r7, #52] @ 0x34 800e3c8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e3cc: d102 bne.n 800e3d4 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e3ce: 4b55 ldr r3, [pc, #340] @ (800e524 ) 800e3d0: 63fb str r3, [r7, #60] @ 0x3c 800e3d2: e010 b.n 800e3f6 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e3d4: 4b51 ldr r3, [pc, #324] @ (800e51c ) 800e3d6: 681b ldr r3, [r3, #0] 800e3d8: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e3dc: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e3e0: d106 bne.n 800e3f0 800e3e2: 6b7b ldr r3, [r7, #52] @ 0x34 800e3e4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e3e8: d102 bne.n 800e3f0 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e3ea: 4b4f ldr r3, [pc, #316] @ (800e528 ) 800e3ec: 63fb str r3, [r7, #60] @ 0x3c 800e3ee: e002 b.n 800e3f6 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e3f0: 2300 movs r3, #0 800e3f2: 63fb str r3, [r7, #60] @ 0x3c } break; 800e3f4: e235 b.n 800e862 800e3f6: e234 b.n 800e862 } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800e3f8: 4b4c ldr r3, [pc, #304] @ (800e52c ) 800e3fa: 63fb str r3, [r7, #60] @ 0x3c break; 800e3fc: e231 b.n 800e862 } default : { frequency = 0; 800e3fe: 2300 movs r3, #0 800e400: 63fb str r3, [r7, #60] @ 0x3c break; 800e402: e22e b.n 800e862 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800e404: e9d7 2300 ldrd r2, r3, [r7] 800e408: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 800e40c: 430b orrs r3, r1 800e40e: f040 808f bne.w 800e530 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800e412: 4b42 ldr r3, [pc, #264] @ (800e51c ) 800e414: 6d1b ldr r3, [r3, #80] @ 0x50 800e416: f403 23e0 and.w r3, r3, #458752 @ 0x70000 800e41a: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e41c: 6bbb ldr r3, [r7, #56] @ 0x38 800e41e: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e422: d06b beq.n 800e4fc 800e424: 6bbb ldr r3, [r7, #56] @ 0x38 800e426: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e42a: d874 bhi.n 800e516 800e42c: 6bbb ldr r3, [r7, #56] @ 0x38 800e42e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e432: d056 beq.n 800e4e2 800e434: 6bbb ldr r3, [r7, #56] @ 0x38 800e436: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e43a: d86c bhi.n 800e516 800e43c: 6bbb ldr r3, [r7, #56] @ 0x38 800e43e: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e442: d03b beq.n 800e4bc 800e444: 6bbb ldr r3, [r7, #56] @ 0x38 800e446: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e44a: d864 bhi.n 800e516 800e44c: 6bbb ldr r3, [r7, #56] @ 0x38 800e44e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e452: d021 beq.n 800e498 800e454: 6bbb ldr r3, [r7, #56] @ 0x38 800e456: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e45a: d85c bhi.n 800e516 800e45c: 6bbb ldr r3, [r7, #56] @ 0x38 800e45e: 2b00 cmp r3, #0 800e460: d004 beq.n 800e46c 800e462: 6bbb ldr r3, [r7, #56] @ 0x38 800e464: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e468: d004 beq.n 800e474 800e46a: e054 b.n 800e516 { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 800e46c: f7fe fa26 bl 800c8bc 800e470: 63f8 str r0, [r7, #60] @ 0x3c break; 800e472: e1f6 b.n 800e862 } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e474: 4b29 ldr r3, [pc, #164] @ (800e51c ) 800e476: 681b ldr r3, [r3, #0] 800e478: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e47c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e480: d107 bne.n 800e492 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e482: f107 0318 add.w r3, r7, #24 800e486: 4618 mov r0, r3 800e488: f000 fa0a bl 800e8a0 frequency = pll2_clocks.PLL2_Q_Frequency; 800e48c: 69fb ldr r3, [r7, #28] 800e48e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e490: e1e7 b.n 800e862 frequency = 0; 800e492: 2300 movs r3, #0 800e494: 63fb str r3, [r7, #60] @ 0x3c break; 800e496: e1e4 b.n 800e862 } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e498: 4b20 ldr r3, [pc, #128] @ (800e51c ) 800e49a: 681b ldr r3, [r3, #0] 800e49c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e4a0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e4a4: d107 bne.n 800e4b6 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e4a6: f107 030c add.w r3, r7, #12 800e4aa: 4618 mov r0, r3 800e4ac: f000 fb4c bl 800eb48 frequency = pll3_clocks.PLL3_Q_Frequency; 800e4b0: 693b ldr r3, [r7, #16] 800e4b2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4b4: e1d5 b.n 800e862 frequency = 0; 800e4b6: 2300 movs r3, #0 800e4b8: 63fb str r3, [r7, #60] @ 0x3c break; 800e4ba: e1d2 b.n 800e862 } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e4bc: 4b17 ldr r3, [pc, #92] @ (800e51c ) 800e4be: 681b ldr r3, [r3, #0] 800e4c0: f003 0304 and.w r3, r3, #4 800e4c4: 2b04 cmp r3, #4 800e4c6: d109 bne.n 800e4dc { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e4c8: 4b14 ldr r3, [pc, #80] @ (800e51c ) 800e4ca: 681b ldr r3, [r3, #0] 800e4cc: 08db lsrs r3, r3, #3 800e4ce: f003 0303 and.w r3, r3, #3 800e4d2: 4a13 ldr r2, [pc, #76] @ (800e520 ) 800e4d4: fa22 f303 lsr.w r3, r2, r3 800e4d8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4da: e1c2 b.n 800e862 frequency = 0; 800e4dc: 2300 movs r3, #0 800e4de: 63fb str r3, [r7, #60] @ 0x3c break; 800e4e0: e1bf b.n 800e862 } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e4e2: 4b0e ldr r3, [pc, #56] @ (800e51c ) 800e4e4: 681b ldr r3, [r3, #0] 800e4e6: f403 7380 and.w r3, r3, #256 @ 0x100 800e4ea: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e4ee: d102 bne.n 800e4f6 { frequency = CSI_VALUE; 800e4f0: 4b0c ldr r3, [pc, #48] @ (800e524 ) 800e4f2: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4f4: e1b5 b.n 800e862 frequency = 0; 800e4f6: 2300 movs r3, #0 800e4f8: 63fb str r3, [r7, #60] @ 0x3c break; 800e4fa: e1b2 b.n 800e862 } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e4fc: 4b07 ldr r3, [pc, #28] @ (800e51c ) 800e4fe: 681b ldr r3, [r3, #0] 800e500: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e504: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e508: d102 bne.n 800e510 { frequency = HSE_VALUE; 800e50a: 4b07 ldr r3, [pc, #28] @ (800e528 ) 800e50c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e50e: e1a8 b.n 800e862 frequency = 0; 800e510: 2300 movs r3, #0 800e512: 63fb str r3, [r7, #60] @ 0x3c break; 800e514: e1a5 b.n 800e862 } default : { frequency = 0; 800e516: 2300 movs r3, #0 800e518: 63fb str r3, [r7, #60] @ 0x3c break; 800e51a: e1a2 b.n 800e862 800e51c: 58024400 .word 0x58024400 800e520: 03d09000 .word 0x03d09000 800e524: 003d0900 .word 0x003d0900 800e528: 017d7840 .word 0x017d7840 800e52c: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 800e530: e9d7 2300 ldrd r2, r3, [r7] 800e534: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 800e538: 430b orrs r3, r1 800e53a: d173 bne.n 800e624 { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 800e53c: 4b9c ldr r3, [pc, #624] @ (800e7b0 ) 800e53e: 6d9b ldr r3, [r3, #88] @ 0x58 800e540: f403 3340 and.w r3, r3, #196608 @ 0x30000 800e544: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e546: 6bbb ldr r3, [r7, #56] @ 0x38 800e548: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e54c: d02f beq.n 800e5ae 800e54e: 6bbb ldr r3, [r7, #56] @ 0x38 800e550: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e554: d863 bhi.n 800e61e 800e556: 6bbb ldr r3, [r7, #56] @ 0x38 800e558: 2b00 cmp r3, #0 800e55a: d004 beq.n 800e566 800e55c: 6bbb ldr r3, [r7, #56] @ 0x38 800e55e: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e562: d012 beq.n 800e58a 800e564: e05b b.n 800e61e { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e566: 4b92 ldr r3, [pc, #584] @ (800e7b0 ) 800e568: 681b ldr r3, [r3, #0] 800e56a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e56e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e572: d107 bne.n 800e584 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e574: f107 0318 add.w r3, r7, #24 800e578: 4618 mov r0, r3 800e57a: f000 f991 bl 800e8a0 frequency = pll2_clocks.PLL2_P_Frequency; 800e57e: 69bb ldr r3, [r7, #24] 800e580: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e582: e16e b.n 800e862 frequency = 0; 800e584: 2300 movs r3, #0 800e586: 63fb str r3, [r7, #60] @ 0x3c break; 800e588: e16b b.n 800e862 } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e58a: 4b89 ldr r3, [pc, #548] @ (800e7b0 ) 800e58c: 681b ldr r3, [r3, #0] 800e58e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e592: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e596: d107 bne.n 800e5a8 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e598: f107 030c add.w r3, r7, #12 800e59c: 4618 mov r0, r3 800e59e: f000 fad3 bl 800eb48 frequency = pll3_clocks.PLL3_R_Frequency; 800e5a2: 697b ldr r3, [r7, #20] 800e5a4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e5a6: e15c b.n 800e862 frequency = 0; 800e5a8: 2300 movs r3, #0 800e5aa: 63fb str r3, [r7, #60] @ 0x3c break; 800e5ac: e159 b.n 800e862 } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e5ae: 4b80 ldr r3, [pc, #512] @ (800e7b0 ) 800e5b0: 6cdb ldr r3, [r3, #76] @ 0x4c 800e5b2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e5b6: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e5b8: 4b7d ldr r3, [pc, #500] @ (800e7b0 ) 800e5ba: 681b ldr r3, [r3, #0] 800e5bc: f003 0304 and.w r3, r3, #4 800e5c0: 2b04 cmp r3, #4 800e5c2: d10c bne.n 800e5de 800e5c4: 6b7b ldr r3, [r7, #52] @ 0x34 800e5c6: 2b00 cmp r3, #0 800e5c8: d109 bne.n 800e5de { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e5ca: 4b79 ldr r3, [pc, #484] @ (800e7b0 ) 800e5cc: 681b ldr r3, [r3, #0] 800e5ce: 08db lsrs r3, r3, #3 800e5d0: f003 0303 and.w r3, r3, #3 800e5d4: 4a77 ldr r2, [pc, #476] @ (800e7b4 ) 800e5d6: fa22 f303 lsr.w r3, r2, r3 800e5da: 63fb str r3, [r7, #60] @ 0x3c 800e5dc: e01e b.n 800e61c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e5de: 4b74 ldr r3, [pc, #464] @ (800e7b0 ) 800e5e0: 681b ldr r3, [r3, #0] 800e5e2: f403 7380 and.w r3, r3, #256 @ 0x100 800e5e6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e5ea: d106 bne.n 800e5fa 800e5ec: 6b7b ldr r3, [r7, #52] @ 0x34 800e5ee: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e5f2: d102 bne.n 800e5fa { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e5f4: 4b70 ldr r3, [pc, #448] @ (800e7b8 ) 800e5f6: 63fb str r3, [r7, #60] @ 0x3c 800e5f8: e010 b.n 800e61c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e5fa: 4b6d ldr r3, [pc, #436] @ (800e7b0 ) 800e5fc: 681b ldr r3, [r3, #0] 800e5fe: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e602: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e606: d106 bne.n 800e616 800e608: 6b7b ldr r3, [r7, #52] @ 0x34 800e60a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e60e: d102 bne.n 800e616 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e610: 4b6a ldr r3, [pc, #424] @ (800e7bc ) 800e612: 63fb str r3, [r7, #60] @ 0x3c 800e614: e002 b.n 800e61c } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e616: 2300 movs r3, #0 800e618: 63fb str r3, [r7, #60] @ 0x3c } break; 800e61a: e122 b.n 800e862 800e61c: e121 b.n 800e862 } default : { frequency = 0; 800e61e: 2300 movs r3, #0 800e620: 63fb str r3, [r7, #60] @ 0x3c break; 800e622: e11e b.n 800e862 } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 800e624: e9d7 2300 ldrd r2, r3, [r7] 800e628: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 800e62c: 430b orrs r3, r1 800e62e: d133 bne.n 800e698 { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 800e630: 4b5f ldr r3, [pc, #380] @ (800e7b0 ) 800e632: 6cdb ldr r3, [r3, #76] @ 0x4c 800e634: f403 3380 and.w r3, r3, #65536 @ 0x10000 800e638: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e63a: 6bbb ldr r3, [r7, #56] @ 0x38 800e63c: 2b00 cmp r3, #0 800e63e: d004 beq.n 800e64a 800e640: 6bbb ldr r3, [r7, #56] @ 0x38 800e642: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e646: d012 beq.n 800e66e 800e648: e023 b.n 800e692 { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e64a: 4b59 ldr r3, [pc, #356] @ (800e7b0 ) 800e64c: 681b ldr r3, [r3, #0] 800e64e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e652: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e656: d107 bne.n 800e668 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e658: f107 0324 add.w r3, r7, #36 @ 0x24 800e65c: 4618 mov r0, r3 800e65e: f000 fbc7 bl 800edf0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e662: 6abb ldr r3, [r7, #40] @ 0x28 800e664: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e666: e0fc b.n 800e862 frequency = 0; 800e668: 2300 movs r3, #0 800e66a: 63fb str r3, [r7, #60] @ 0x3c break; 800e66c: e0f9 b.n 800e862 } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e66e: 4b50 ldr r3, [pc, #320] @ (800e7b0 ) 800e670: 681b ldr r3, [r3, #0] 800e672: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e676: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e67a: d107 bne.n 800e68c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e67c: f107 0318 add.w r3, r7, #24 800e680: 4618 mov r0, r3 800e682: f000 f90d bl 800e8a0 frequency = pll2_clocks.PLL2_R_Frequency; 800e686: 6a3b ldr r3, [r7, #32] 800e688: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e68a: e0ea b.n 800e862 frequency = 0; 800e68c: 2300 movs r3, #0 800e68e: 63fb str r3, [r7, #60] @ 0x3c break; 800e690: e0e7 b.n 800e862 } default : { frequency = 0; 800e692: 2300 movs r3, #0 800e694: 63fb str r3, [r7, #60] @ 0x3c break; 800e696: e0e4 b.n 800e862 } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800e698: e9d7 2300 ldrd r2, r3, [r7] 800e69c: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 800e6a0: 430b orrs r3, r1 800e6a2: f040 808d bne.w 800e7c0 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800e6a6: 4b42 ldr r3, [pc, #264] @ (800e7b0 ) 800e6a8: 6d9b ldr r3, [r3, #88] @ 0x58 800e6aa: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 800e6ae: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e6b0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6b2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e6b6: d06b beq.n 800e790 800e6b8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ba: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e6be: d874 bhi.n 800e7aa 800e6c0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6c2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e6c6: d056 beq.n 800e776 800e6c8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ca: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e6ce: d86c bhi.n 800e7aa 800e6d0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6d2: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e6d6: d03b beq.n 800e750 800e6d8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6da: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e6de: d864 bhi.n 800e7aa 800e6e0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6e2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e6e6: d021 beq.n 800e72c 800e6e8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ea: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e6ee: d85c bhi.n 800e7aa 800e6f0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6f2: 2b00 cmp r3, #0 800e6f4: d004 beq.n 800e700 800e6f6: 6bbb ldr r3, [r7, #56] @ 0x38 800e6f8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e6fc: d004 beq.n 800e708 800e6fe: e054 b.n 800e7aa { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800e700: f000 f8b8 bl 800e874 800e704: 63f8 str r0, [r7, #60] @ 0x3c break; 800e706: e0ac b.n 800e862 } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e708: 4b29 ldr r3, [pc, #164] @ (800e7b0 ) 800e70a: 681b ldr r3, [r3, #0] 800e70c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e710: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e714: d107 bne.n 800e726 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e716: f107 0318 add.w r3, r7, #24 800e71a: 4618 mov r0, r3 800e71c: f000 f8c0 bl 800e8a0 frequency = pll2_clocks.PLL2_Q_Frequency; 800e720: 69fb ldr r3, [r7, #28] 800e722: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e724: e09d b.n 800e862 frequency = 0; 800e726: 2300 movs r3, #0 800e728: 63fb str r3, [r7, #60] @ 0x3c break; 800e72a: e09a b.n 800e862 } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e72c: 4b20 ldr r3, [pc, #128] @ (800e7b0 ) 800e72e: 681b ldr r3, [r3, #0] 800e730: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e734: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e738: d107 bne.n 800e74a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e73a: f107 030c add.w r3, r7, #12 800e73e: 4618 mov r0, r3 800e740: f000 fa02 bl 800eb48 frequency = pll3_clocks.PLL3_Q_Frequency; 800e744: 693b ldr r3, [r7, #16] 800e746: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e748: e08b b.n 800e862 frequency = 0; 800e74a: 2300 movs r3, #0 800e74c: 63fb str r3, [r7, #60] @ 0x3c break; 800e74e: e088 b.n 800e862 } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e750: 4b17 ldr r3, [pc, #92] @ (800e7b0 ) 800e752: 681b ldr r3, [r3, #0] 800e754: f003 0304 and.w r3, r3, #4 800e758: 2b04 cmp r3, #4 800e75a: d109 bne.n 800e770 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e75c: 4b14 ldr r3, [pc, #80] @ (800e7b0 ) 800e75e: 681b ldr r3, [r3, #0] 800e760: 08db lsrs r3, r3, #3 800e762: f003 0303 and.w r3, r3, #3 800e766: 4a13 ldr r2, [pc, #76] @ (800e7b4 ) 800e768: fa22 f303 lsr.w r3, r2, r3 800e76c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e76e: e078 b.n 800e862 frequency = 0; 800e770: 2300 movs r3, #0 800e772: 63fb str r3, [r7, #60] @ 0x3c break; 800e774: e075 b.n 800e862 } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e776: 4b0e ldr r3, [pc, #56] @ (800e7b0 ) 800e778: 681b ldr r3, [r3, #0] 800e77a: f403 7380 and.w r3, r3, #256 @ 0x100 800e77e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e782: d102 bne.n 800e78a { frequency = CSI_VALUE; 800e784: 4b0c ldr r3, [pc, #48] @ (800e7b8 ) 800e786: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e788: e06b b.n 800e862 frequency = 0; 800e78a: 2300 movs r3, #0 800e78c: 63fb str r3, [r7, #60] @ 0x3c break; 800e78e: e068 b.n 800e862 } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e790: 4b07 ldr r3, [pc, #28] @ (800e7b0 ) 800e792: 681b ldr r3, [r3, #0] 800e794: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e798: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e79c: d102 bne.n 800e7a4 { frequency = HSE_VALUE; 800e79e: 4b07 ldr r3, [pc, #28] @ (800e7bc ) 800e7a0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e7a2: e05e b.n 800e862 frequency = 0; 800e7a4: 2300 movs r3, #0 800e7a6: 63fb str r3, [r7, #60] @ 0x3c break; 800e7a8: e05b b.n 800e862 break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 800e7aa: 2300 movs r3, #0 800e7ac: 63fb str r3, [r7, #60] @ 0x3c break; 800e7ae: e058 b.n 800e862 800e7b0: 58024400 .word 0x58024400 800e7b4: 03d09000 .word 0x03d09000 800e7b8: 003d0900 .word 0x003d0900 800e7bc: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800e7c0: e9d7 2300 ldrd r2, r3, [r7] 800e7c4: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 800e7c8: 430b orrs r3, r1 800e7ca: d148 bne.n 800e85e { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800e7cc: 4b27 ldr r3, [pc, #156] @ (800e86c ) 800e7ce: 6d1b ldr r3, [r3, #80] @ 0x50 800e7d0: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e7d4: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e7d6: 6bbb ldr r3, [r7, #56] @ 0x38 800e7d8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e7dc: d02a beq.n 800e834 800e7de: 6bbb ldr r3, [r7, #56] @ 0x38 800e7e0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e7e4: d838 bhi.n 800e858 800e7e6: 6bbb ldr r3, [r7, #56] @ 0x38 800e7e8: 2b00 cmp r3, #0 800e7ea: d004 beq.n 800e7f6 800e7ec: 6bbb ldr r3, [r7, #56] @ 0x38 800e7ee: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e7f2: d00d beq.n 800e810 800e7f4: e030 b.n 800e858 { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e7f6: 4b1d ldr r3, [pc, #116] @ (800e86c ) 800e7f8: 681b ldr r3, [r3, #0] 800e7fa: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e7fe: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e802: d102 bne.n 800e80a { frequency = HSE_VALUE; 800e804: 4b1a ldr r3, [pc, #104] @ (800e870 ) 800e806: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e808: e02b b.n 800e862 frequency = 0; 800e80a: 2300 movs r3, #0 800e80c: 63fb str r3, [r7, #60] @ 0x3c break; 800e80e: e028 b.n 800e862 } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e810: 4b16 ldr r3, [pc, #88] @ (800e86c ) 800e812: 681b ldr r3, [r3, #0] 800e814: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e818: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e81c: d107 bne.n 800e82e { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e81e: f107 0324 add.w r3, r7, #36 @ 0x24 800e822: 4618 mov r0, r3 800e824: f000 fae4 bl 800edf0 frequency = pll1_clocks.PLL1_Q_Frequency; 800e828: 6abb ldr r3, [r7, #40] @ 0x28 800e82a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e82c: e019 b.n 800e862 frequency = 0; 800e82e: 2300 movs r3, #0 800e830: 63fb str r3, [r7, #60] @ 0x3c break; 800e832: e016 b.n 800e862 } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e834: 4b0d ldr r3, [pc, #52] @ (800e86c ) 800e836: 681b ldr r3, [r3, #0] 800e838: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e83c: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e840: d107 bne.n 800e852 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e842: f107 0318 add.w r3, r7, #24 800e846: 4618 mov r0, r3 800e848: f000 f82a bl 800e8a0 frequency = pll2_clocks.PLL2_Q_Frequency; 800e84c: 69fb ldr r3, [r7, #28] 800e84e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e850: e007 b.n 800e862 frequency = 0; 800e852: 2300 movs r3, #0 800e854: 63fb str r3, [r7, #60] @ 0x3c break; 800e856: e004 b.n 800e862 } default : { frequency = 0; 800e858: 2300 movs r3, #0 800e85a: 63fb str r3, [r7, #60] @ 0x3c break; 800e85c: e001 b.n 800e862 } } } else { frequency = 0; 800e85e: 2300 movs r3, #0 800e860: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 800e862: 6bfb ldr r3, [r7, #60] @ 0x3c } 800e864: 4618 mov r0, r3 800e866: 3740 adds r7, #64 @ 0x40 800e868: 46bd mov sp, r7 800e86a: bd80 pop {r7, pc} 800e86c: 58024400 .word 0x58024400 800e870: 017d7840 .word 0x017d7840 0800e874 : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 800e874: b580 push {r7, lr} 800e876: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800e878: f7fd fff0 bl 800c85c 800e87c: 4602 mov r2, r0 800e87e: 4b06 ldr r3, [pc, #24] @ (800e898 ) 800e880: 6a1b ldr r3, [r3, #32] 800e882: 091b lsrs r3, r3, #4 800e884: f003 0307 and.w r3, r3, #7 800e888: 4904 ldr r1, [pc, #16] @ (800e89c ) 800e88a: 5ccb ldrb r3, [r1, r3] 800e88c: f003 031f and.w r3, r3, #31 800e890: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 800e894: 4618 mov r0, r3 800e896: bd80 pop {r7, pc} 800e898: 58024400 .word 0x58024400 800e89c: 080186fc .word 0x080186fc 0800e8a0 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 800e8a0: b480 push {r7} 800e8a2: b089 sub sp, #36 @ 0x24 800e8a4: af00 add r7, sp, #0 800e8a6: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e8a8: 4ba1 ldr r3, [pc, #644] @ (800eb30 ) 800e8aa: 6a9b ldr r3, [r3, #40] @ 0x28 800e8ac: f003 0303 and.w r3, r3, #3 800e8b0: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 800e8b2: 4b9f ldr r3, [pc, #636] @ (800eb30 ) 800e8b4: 6a9b ldr r3, [r3, #40] @ 0x28 800e8b6: 0b1b lsrs r3, r3, #12 800e8b8: f003 033f and.w r3, r3, #63 @ 0x3f 800e8bc: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 800e8be: 4b9c ldr r3, [pc, #624] @ (800eb30 ) 800e8c0: 6adb ldr r3, [r3, #44] @ 0x2c 800e8c2: 091b lsrs r3, r3, #4 800e8c4: f003 0301 and.w r3, r3, #1 800e8c8: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 800e8ca: 4b99 ldr r3, [pc, #612] @ (800eb30 ) 800e8cc: 6bdb ldr r3, [r3, #60] @ 0x3c 800e8ce: 08db lsrs r3, r3, #3 800e8d0: f3c3 030c ubfx r3, r3, #0, #13 800e8d4: 693a ldr r2, [r7, #16] 800e8d6: fb02 f303 mul.w r3, r2, r3 800e8da: ee07 3a90 vmov s15, r3 800e8de: eef8 7a67 vcvt.f32.u32 s15, s15 800e8e2: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 800e8e6: 697b ldr r3, [r7, #20] 800e8e8: 2b00 cmp r3, #0 800e8ea: f000 8111 beq.w 800eb10 { switch (pllsource) 800e8ee: 69bb ldr r3, [r7, #24] 800e8f0: 2b02 cmp r3, #2 800e8f2: f000 8083 beq.w 800e9fc 800e8f6: 69bb ldr r3, [r7, #24] 800e8f8: 2b02 cmp r3, #2 800e8fa: f200 80a1 bhi.w 800ea40 800e8fe: 69bb ldr r3, [r7, #24] 800e900: 2b00 cmp r3, #0 800e902: d003 beq.n 800e90c 800e904: 69bb ldr r3, [r7, #24] 800e906: 2b01 cmp r3, #1 800e908: d056 beq.n 800e9b8 800e90a: e099 b.n 800ea40 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e90c: 4b88 ldr r3, [pc, #544] @ (800eb30 ) 800e90e: 681b ldr r3, [r3, #0] 800e910: f003 0320 and.w r3, r3, #32 800e914: 2b00 cmp r3, #0 800e916: d02d beq.n 800e974 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e918: 4b85 ldr r3, [pc, #532] @ (800eb30 ) 800e91a: 681b ldr r3, [r3, #0] 800e91c: 08db lsrs r3, r3, #3 800e91e: f003 0303 and.w r3, r3, #3 800e922: 4a84 ldr r2, [pc, #528] @ (800eb34 ) 800e924: fa22 f303 lsr.w r3, r2, r3 800e928: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e92a: 68bb ldr r3, [r7, #8] 800e92c: ee07 3a90 vmov s15, r3 800e930: eef8 6a67 vcvt.f32.u32 s13, s15 800e934: 697b ldr r3, [r7, #20] 800e936: ee07 3a90 vmov s15, r3 800e93a: eef8 7a67 vcvt.f32.u32 s15, s15 800e93e: ee86 7aa7 vdiv.f32 s14, s13, s15 800e942: 4b7b ldr r3, [pc, #492] @ (800eb30 ) 800e944: 6b9b ldr r3, [r3, #56] @ 0x38 800e946: f3c3 0308 ubfx r3, r3, #0, #9 800e94a: ee07 3a90 vmov s15, r3 800e94e: eef8 6a67 vcvt.f32.u32 s13, s15 800e952: ed97 6a03 vldr s12, [r7, #12] 800e956: eddf 5a78 vldr s11, [pc, #480] @ 800eb38 800e95a: eec6 7a25 vdiv.f32 s15, s12, s11 800e95e: ee76 7aa7 vadd.f32 s15, s13, s15 800e962: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e966: ee77 7aa6 vadd.f32 s15, s15, s13 800e96a: ee67 7a27 vmul.f32 s15, s14, s15 800e96e: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800e972: e087 b.n 800ea84 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e974: 697b ldr r3, [r7, #20] 800e976: ee07 3a90 vmov s15, r3 800e97a: eef8 7a67 vcvt.f32.u32 s15, s15 800e97e: eddf 6a6f vldr s13, [pc, #444] @ 800eb3c 800e982: ee86 7aa7 vdiv.f32 s14, s13, s15 800e986: 4b6a ldr r3, [pc, #424] @ (800eb30 ) 800e988: 6b9b ldr r3, [r3, #56] @ 0x38 800e98a: f3c3 0308 ubfx r3, r3, #0, #9 800e98e: ee07 3a90 vmov s15, r3 800e992: eef8 6a67 vcvt.f32.u32 s13, s15 800e996: ed97 6a03 vldr s12, [r7, #12] 800e99a: eddf 5a67 vldr s11, [pc, #412] @ 800eb38 800e99e: eec6 7a25 vdiv.f32 s15, s12, s11 800e9a2: ee76 7aa7 vadd.f32 s15, s13, s15 800e9a6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e9aa: ee77 7aa6 vadd.f32 s15, s15, s13 800e9ae: ee67 7a27 vmul.f32 s15, s14, s15 800e9b2: edc7 7a07 vstr s15, [r7, #28] break; 800e9b6: e065 b.n 800ea84 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e9b8: 697b ldr r3, [r7, #20] 800e9ba: ee07 3a90 vmov s15, r3 800e9be: eef8 7a67 vcvt.f32.u32 s15, s15 800e9c2: eddf 6a5f vldr s13, [pc, #380] @ 800eb40 800e9c6: ee86 7aa7 vdiv.f32 s14, s13, s15 800e9ca: 4b59 ldr r3, [pc, #356] @ (800eb30 ) 800e9cc: 6b9b ldr r3, [r3, #56] @ 0x38 800e9ce: f3c3 0308 ubfx r3, r3, #0, #9 800e9d2: ee07 3a90 vmov s15, r3 800e9d6: eef8 6a67 vcvt.f32.u32 s13, s15 800e9da: ed97 6a03 vldr s12, [r7, #12] 800e9de: eddf 5a56 vldr s11, [pc, #344] @ 800eb38 800e9e2: eec6 7a25 vdiv.f32 s15, s12, s11 800e9e6: ee76 7aa7 vadd.f32 s15, s13, s15 800e9ea: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e9ee: ee77 7aa6 vadd.f32 s15, s15, s13 800e9f2: ee67 7a27 vmul.f32 s15, s14, s15 800e9f6: edc7 7a07 vstr s15, [r7, #28] break; 800e9fa: e043 b.n 800ea84 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e9fc: 697b ldr r3, [r7, #20] 800e9fe: ee07 3a90 vmov s15, r3 800ea02: eef8 7a67 vcvt.f32.u32 s15, s15 800ea06: eddf 6a4f vldr s13, [pc, #316] @ 800eb44 800ea0a: ee86 7aa7 vdiv.f32 s14, s13, s15 800ea0e: 4b48 ldr r3, [pc, #288] @ (800eb30 ) 800ea10: 6b9b ldr r3, [r3, #56] @ 0x38 800ea12: f3c3 0308 ubfx r3, r3, #0, #9 800ea16: ee07 3a90 vmov s15, r3 800ea1a: eef8 6a67 vcvt.f32.u32 s13, s15 800ea1e: ed97 6a03 vldr s12, [r7, #12] 800ea22: eddf 5a45 vldr s11, [pc, #276] @ 800eb38 800ea26: eec6 7a25 vdiv.f32 s15, s12, s11 800ea2a: ee76 7aa7 vadd.f32 s15, s13, s15 800ea2e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ea32: ee77 7aa6 vadd.f32 s15, s15, s13 800ea36: ee67 7a27 vmul.f32 s15, s14, s15 800ea3a: edc7 7a07 vstr s15, [r7, #28] break; 800ea3e: e021 b.n 800ea84 default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800ea40: 697b ldr r3, [r7, #20] 800ea42: ee07 3a90 vmov s15, r3 800ea46: eef8 7a67 vcvt.f32.u32 s15, s15 800ea4a: eddf 6a3d vldr s13, [pc, #244] @ 800eb40 800ea4e: ee86 7aa7 vdiv.f32 s14, s13, s15 800ea52: 4b37 ldr r3, [pc, #220] @ (800eb30 ) 800ea54: 6b9b ldr r3, [r3, #56] @ 0x38 800ea56: f3c3 0308 ubfx r3, r3, #0, #9 800ea5a: ee07 3a90 vmov s15, r3 800ea5e: eef8 6a67 vcvt.f32.u32 s13, s15 800ea62: ed97 6a03 vldr s12, [r7, #12] 800ea66: eddf 5a34 vldr s11, [pc, #208] @ 800eb38 800ea6a: eec6 7a25 vdiv.f32 s15, s12, s11 800ea6e: ee76 7aa7 vadd.f32 s15, s13, s15 800ea72: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ea76: ee77 7aa6 vadd.f32 s15, s15, s13 800ea7a: ee67 7a27 vmul.f32 s15, s14, s15 800ea7e: edc7 7a07 vstr s15, [r7, #28] break; 800ea82: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800ea84: 4b2a ldr r3, [pc, #168] @ (800eb30 ) 800ea86: 6b9b ldr r3, [r3, #56] @ 0x38 800ea88: 0a5b lsrs r3, r3, #9 800ea8a: f003 037f and.w r3, r3, #127 @ 0x7f 800ea8e: ee07 3a90 vmov s15, r3 800ea92: eef8 7a67 vcvt.f32.u32 s15, s15 800ea96: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ea9a: ee37 7a87 vadd.f32 s14, s15, s14 800ea9e: edd7 6a07 vldr s13, [r7, #28] 800eaa2: eec6 7a87 vdiv.f32 s15, s13, s14 800eaa6: eefc 7ae7 vcvt.u32.f32 s15, s15 800eaaa: ee17 2a90 vmov r2, s15 800eaae: 687b ldr r3, [r7, #4] 800eab0: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800eab2: 4b1f ldr r3, [pc, #124] @ (800eb30 ) 800eab4: 6b9b ldr r3, [r3, #56] @ 0x38 800eab6: 0c1b lsrs r3, r3, #16 800eab8: f003 037f and.w r3, r3, #127 @ 0x7f 800eabc: ee07 3a90 vmov s15, r3 800eac0: eef8 7a67 vcvt.f32.u32 s15, s15 800eac4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eac8: ee37 7a87 vadd.f32 s14, s15, s14 800eacc: edd7 6a07 vldr s13, [r7, #28] 800ead0: eec6 7a87 vdiv.f32 s15, s13, s14 800ead4: eefc 7ae7 vcvt.u32.f32 s15, s15 800ead8: ee17 2a90 vmov r2, s15 800eadc: 687b ldr r3, [r7, #4] 800eade: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800eae0: 4b13 ldr r3, [pc, #76] @ (800eb30 ) 800eae2: 6b9b ldr r3, [r3, #56] @ 0x38 800eae4: 0e1b lsrs r3, r3, #24 800eae6: f003 037f and.w r3, r3, #127 @ 0x7f 800eaea: ee07 3a90 vmov s15, r3 800eaee: eef8 7a67 vcvt.f32.u32 s15, s15 800eaf2: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eaf6: ee37 7a87 vadd.f32 s14, s15, s14 800eafa: edd7 6a07 vldr s13, [r7, #28] 800eafe: eec6 7a87 vdiv.f32 s15, s13, s14 800eb02: eefc 7ae7 vcvt.u32.f32 s15, s15 800eb06: ee17 2a90 vmov r2, s15 800eb0a: 687b ldr r3, [r7, #4] 800eb0c: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800eb0e: e008 b.n 800eb22 PLL2_Clocks->PLL2_P_Frequency = 0U; 800eb10: 687b ldr r3, [r7, #4] 800eb12: 2200 movs r2, #0 800eb14: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 800eb16: 687b ldr r3, [r7, #4] 800eb18: 2200 movs r2, #0 800eb1a: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 800eb1c: 687b ldr r3, [r7, #4] 800eb1e: 2200 movs r2, #0 800eb20: 609a str r2, [r3, #8] } 800eb22: bf00 nop 800eb24: 3724 adds r7, #36 @ 0x24 800eb26: 46bd mov sp, r7 800eb28: f85d 7b04 ldr.w r7, [sp], #4 800eb2c: 4770 bx lr 800eb2e: bf00 nop 800eb30: 58024400 .word 0x58024400 800eb34: 03d09000 .word 0x03d09000 800eb38: 46000000 .word 0x46000000 800eb3c: 4c742400 .word 0x4c742400 800eb40: 4a742400 .word 0x4a742400 800eb44: 4bbebc20 .word 0x4bbebc20 0800eb48 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 800eb48: b480 push {r7} 800eb4a: b089 sub sp, #36 @ 0x24 800eb4c: af00 add r7, sp, #0 800eb4e: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800eb50: 4ba1 ldr r3, [pc, #644] @ (800edd8 ) 800eb52: 6a9b ldr r3, [r3, #40] @ 0x28 800eb54: f003 0303 and.w r3, r3, #3 800eb58: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800eb5a: 4b9f ldr r3, [pc, #636] @ (800edd8 ) 800eb5c: 6a9b ldr r3, [r3, #40] @ 0x28 800eb5e: 0d1b lsrs r3, r3, #20 800eb60: f003 033f and.w r3, r3, #63 @ 0x3f 800eb64: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800eb66: 4b9c ldr r3, [pc, #624] @ (800edd8 ) 800eb68: 6adb ldr r3, [r3, #44] @ 0x2c 800eb6a: 0a1b lsrs r3, r3, #8 800eb6c: f003 0301 and.w r3, r3, #1 800eb70: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800eb72: 4b99 ldr r3, [pc, #612] @ (800edd8 ) 800eb74: 6c5b ldr r3, [r3, #68] @ 0x44 800eb76: 08db lsrs r3, r3, #3 800eb78: f3c3 030c ubfx r3, r3, #0, #13 800eb7c: 693a ldr r2, [r7, #16] 800eb7e: fb02 f303 mul.w r3, r2, r3 800eb82: ee07 3a90 vmov s15, r3 800eb86: eef8 7a67 vcvt.f32.u32 s15, s15 800eb8a: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800eb8e: 697b ldr r3, [r7, #20] 800eb90: 2b00 cmp r3, #0 800eb92: f000 8111 beq.w 800edb8 { switch (pllsource) 800eb96: 69bb ldr r3, [r7, #24] 800eb98: 2b02 cmp r3, #2 800eb9a: f000 8083 beq.w 800eca4 800eb9e: 69bb ldr r3, [r7, #24] 800eba0: 2b02 cmp r3, #2 800eba2: f200 80a1 bhi.w 800ece8 800eba6: 69bb ldr r3, [r7, #24] 800eba8: 2b00 cmp r3, #0 800ebaa: d003 beq.n 800ebb4 800ebac: 69bb ldr r3, [r7, #24] 800ebae: 2b01 cmp r3, #1 800ebb0: d056 beq.n 800ec60 800ebb2: e099 b.n 800ece8 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800ebb4: 4b88 ldr r3, [pc, #544] @ (800edd8 ) 800ebb6: 681b ldr r3, [r3, #0] 800ebb8: f003 0320 and.w r3, r3, #32 800ebbc: 2b00 cmp r3, #0 800ebbe: d02d beq.n 800ec1c { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ebc0: 4b85 ldr r3, [pc, #532] @ (800edd8 ) 800ebc2: 681b ldr r3, [r3, #0] 800ebc4: 08db lsrs r3, r3, #3 800ebc6: f003 0303 and.w r3, r3, #3 800ebca: 4a84 ldr r2, [pc, #528] @ (800eddc ) 800ebcc: fa22 f303 lsr.w r3, r2, r3 800ebd0: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ebd2: 68bb ldr r3, [r7, #8] 800ebd4: ee07 3a90 vmov s15, r3 800ebd8: eef8 6a67 vcvt.f32.u32 s13, s15 800ebdc: 697b ldr r3, [r7, #20] 800ebde: ee07 3a90 vmov s15, r3 800ebe2: eef8 7a67 vcvt.f32.u32 s15, s15 800ebe6: ee86 7aa7 vdiv.f32 s14, s13, s15 800ebea: 4b7b ldr r3, [pc, #492] @ (800edd8 ) 800ebec: 6c1b ldr r3, [r3, #64] @ 0x40 800ebee: f3c3 0308 ubfx r3, r3, #0, #9 800ebf2: ee07 3a90 vmov s15, r3 800ebf6: eef8 6a67 vcvt.f32.u32 s13, s15 800ebfa: ed97 6a03 vldr s12, [r7, #12] 800ebfe: eddf 5a78 vldr s11, [pc, #480] @ 800ede0 800ec02: eec6 7a25 vdiv.f32 s15, s12, s11 800ec06: ee76 7aa7 vadd.f32 s15, s13, s15 800ec0a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec0e: ee77 7aa6 vadd.f32 s15, s15, s13 800ec12: ee67 7a27 vmul.f32 s15, s14, s15 800ec16: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800ec1a: e087 b.n 800ed2c pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ec1c: 697b ldr r3, [r7, #20] 800ec1e: ee07 3a90 vmov s15, r3 800ec22: eef8 7a67 vcvt.f32.u32 s15, s15 800ec26: eddf 6a6f vldr s13, [pc, #444] @ 800ede4 800ec2a: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec2e: 4b6a ldr r3, [pc, #424] @ (800edd8 ) 800ec30: 6c1b ldr r3, [r3, #64] @ 0x40 800ec32: f3c3 0308 ubfx r3, r3, #0, #9 800ec36: ee07 3a90 vmov s15, r3 800ec3a: eef8 6a67 vcvt.f32.u32 s13, s15 800ec3e: ed97 6a03 vldr s12, [r7, #12] 800ec42: eddf 5a67 vldr s11, [pc, #412] @ 800ede0 800ec46: eec6 7a25 vdiv.f32 s15, s12, s11 800ec4a: ee76 7aa7 vadd.f32 s15, s13, s15 800ec4e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec52: ee77 7aa6 vadd.f32 s15, s15, s13 800ec56: ee67 7a27 vmul.f32 s15, s14, s15 800ec5a: edc7 7a07 vstr s15, [r7, #28] break; 800ec5e: e065 b.n 800ed2c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ec60: 697b ldr r3, [r7, #20] 800ec62: ee07 3a90 vmov s15, r3 800ec66: eef8 7a67 vcvt.f32.u32 s15, s15 800ec6a: eddf 6a5f vldr s13, [pc, #380] @ 800ede8 800ec6e: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec72: 4b59 ldr r3, [pc, #356] @ (800edd8 ) 800ec74: 6c1b ldr r3, [r3, #64] @ 0x40 800ec76: f3c3 0308 ubfx r3, r3, #0, #9 800ec7a: ee07 3a90 vmov s15, r3 800ec7e: eef8 6a67 vcvt.f32.u32 s13, s15 800ec82: ed97 6a03 vldr s12, [r7, #12] 800ec86: eddf 5a56 vldr s11, [pc, #344] @ 800ede0 800ec8a: eec6 7a25 vdiv.f32 s15, s12, s11 800ec8e: ee76 7aa7 vadd.f32 s15, s13, s15 800ec92: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec96: ee77 7aa6 vadd.f32 s15, s15, s13 800ec9a: ee67 7a27 vmul.f32 s15, s14, s15 800ec9e: edc7 7a07 vstr s15, [r7, #28] break; 800eca2: e043 b.n 800ed2c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800eca4: 697b ldr r3, [r7, #20] 800eca6: ee07 3a90 vmov s15, r3 800ecaa: eef8 7a67 vcvt.f32.u32 s15, s15 800ecae: eddf 6a4f vldr s13, [pc, #316] @ 800edec 800ecb2: ee86 7aa7 vdiv.f32 s14, s13, s15 800ecb6: 4b48 ldr r3, [pc, #288] @ (800edd8 ) 800ecb8: 6c1b ldr r3, [r3, #64] @ 0x40 800ecba: f3c3 0308 ubfx r3, r3, #0, #9 800ecbe: ee07 3a90 vmov s15, r3 800ecc2: eef8 6a67 vcvt.f32.u32 s13, s15 800ecc6: ed97 6a03 vldr s12, [r7, #12] 800ecca: eddf 5a45 vldr s11, [pc, #276] @ 800ede0 800ecce: eec6 7a25 vdiv.f32 s15, s12, s11 800ecd2: ee76 7aa7 vadd.f32 s15, s13, s15 800ecd6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ecda: ee77 7aa6 vadd.f32 s15, s15, s13 800ecde: ee67 7a27 vmul.f32 s15, s14, s15 800ece2: edc7 7a07 vstr s15, [r7, #28] break; 800ece6: e021 b.n 800ed2c default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ece8: 697b ldr r3, [r7, #20] 800ecea: ee07 3a90 vmov s15, r3 800ecee: eef8 7a67 vcvt.f32.u32 s15, s15 800ecf2: eddf 6a3d vldr s13, [pc, #244] @ 800ede8 800ecf6: ee86 7aa7 vdiv.f32 s14, s13, s15 800ecfa: 4b37 ldr r3, [pc, #220] @ (800edd8 ) 800ecfc: 6c1b ldr r3, [r3, #64] @ 0x40 800ecfe: f3c3 0308 ubfx r3, r3, #0, #9 800ed02: ee07 3a90 vmov s15, r3 800ed06: eef8 6a67 vcvt.f32.u32 s13, s15 800ed0a: ed97 6a03 vldr s12, [r7, #12] 800ed0e: eddf 5a34 vldr s11, [pc, #208] @ 800ede0 800ed12: eec6 7a25 vdiv.f32 s15, s12, s11 800ed16: ee76 7aa7 vadd.f32 s15, s13, s15 800ed1a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ed1e: ee77 7aa6 vadd.f32 s15, s15, s13 800ed22: ee67 7a27 vmul.f32 s15, s14, s15 800ed26: edc7 7a07 vstr s15, [r7, #28] break; 800ed2a: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800ed2c: 4b2a ldr r3, [pc, #168] @ (800edd8 ) 800ed2e: 6c1b ldr r3, [r3, #64] @ 0x40 800ed30: 0a5b lsrs r3, r3, #9 800ed32: f003 037f and.w r3, r3, #127 @ 0x7f 800ed36: ee07 3a90 vmov s15, r3 800ed3a: eef8 7a67 vcvt.f32.u32 s15, s15 800ed3e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed42: ee37 7a87 vadd.f32 s14, s15, s14 800ed46: edd7 6a07 vldr s13, [r7, #28] 800ed4a: eec6 7a87 vdiv.f32 s15, s13, s14 800ed4e: eefc 7ae7 vcvt.u32.f32 s15, s15 800ed52: ee17 2a90 vmov r2, s15 800ed56: 687b ldr r3, [r7, #4] 800ed58: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800ed5a: 4b1f ldr r3, [pc, #124] @ (800edd8 ) 800ed5c: 6c1b ldr r3, [r3, #64] @ 0x40 800ed5e: 0c1b lsrs r3, r3, #16 800ed60: f003 037f and.w r3, r3, #127 @ 0x7f 800ed64: ee07 3a90 vmov s15, r3 800ed68: eef8 7a67 vcvt.f32.u32 s15, s15 800ed6c: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed70: ee37 7a87 vadd.f32 s14, s15, s14 800ed74: edd7 6a07 vldr s13, [r7, #28] 800ed78: eec6 7a87 vdiv.f32 s15, s13, s14 800ed7c: eefc 7ae7 vcvt.u32.f32 s15, s15 800ed80: ee17 2a90 vmov r2, s15 800ed84: 687b ldr r3, [r7, #4] 800ed86: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800ed88: 4b13 ldr r3, [pc, #76] @ (800edd8 ) 800ed8a: 6c1b ldr r3, [r3, #64] @ 0x40 800ed8c: 0e1b lsrs r3, r3, #24 800ed8e: f003 037f and.w r3, r3, #127 @ 0x7f 800ed92: ee07 3a90 vmov s15, r3 800ed96: eef8 7a67 vcvt.f32.u32 s15, s15 800ed9a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed9e: ee37 7a87 vadd.f32 s14, s15, s14 800eda2: edd7 6a07 vldr s13, [r7, #28] 800eda6: eec6 7a87 vdiv.f32 s15, s13, s14 800edaa: eefc 7ae7 vcvt.u32.f32 s15, s15 800edae: ee17 2a90 vmov r2, s15 800edb2: 687b ldr r3, [r7, #4] 800edb4: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800edb6: e008 b.n 800edca PLL3_Clocks->PLL3_P_Frequency = 0U; 800edb8: 687b ldr r3, [r7, #4] 800edba: 2200 movs r2, #0 800edbc: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800edbe: 687b ldr r3, [r7, #4] 800edc0: 2200 movs r2, #0 800edc2: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800edc4: 687b ldr r3, [r7, #4] 800edc6: 2200 movs r2, #0 800edc8: 609a str r2, [r3, #8] } 800edca: bf00 nop 800edcc: 3724 adds r7, #36 @ 0x24 800edce: 46bd mov sp, r7 800edd0: f85d 7b04 ldr.w r7, [sp], #4 800edd4: 4770 bx lr 800edd6: bf00 nop 800edd8: 58024400 .word 0x58024400 800eddc: 03d09000 .word 0x03d09000 800ede0: 46000000 .word 0x46000000 800ede4: 4c742400 .word 0x4c742400 800ede8: 4a742400 .word 0x4a742400 800edec: 4bbebc20 .word 0x4bbebc20 0800edf0 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800edf0: b480 push {r7} 800edf2: b089 sub sp, #36 @ 0x24 800edf4: af00 add r7, sp, #0 800edf6: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800edf8: 4ba0 ldr r3, [pc, #640] @ (800f07c ) 800edfa: 6a9b ldr r3, [r3, #40] @ 0x28 800edfc: f003 0303 and.w r3, r3, #3 800ee00: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800ee02: 4b9e ldr r3, [pc, #632] @ (800f07c ) 800ee04: 6a9b ldr r3, [r3, #40] @ 0x28 800ee06: 091b lsrs r3, r3, #4 800ee08: f003 033f and.w r3, r3, #63 @ 0x3f 800ee0c: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800ee0e: 4b9b ldr r3, [pc, #620] @ (800f07c ) 800ee10: 6adb ldr r3, [r3, #44] @ 0x2c 800ee12: f003 0301 and.w r3, r3, #1 800ee16: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800ee18: 4b98 ldr r3, [pc, #608] @ (800f07c ) 800ee1a: 6b5b ldr r3, [r3, #52] @ 0x34 800ee1c: 08db lsrs r3, r3, #3 800ee1e: f3c3 030c ubfx r3, r3, #0, #13 800ee22: 693a ldr r2, [r7, #16] 800ee24: fb02 f303 mul.w r3, r2, r3 800ee28: ee07 3a90 vmov s15, r3 800ee2c: eef8 7a67 vcvt.f32.u32 s15, s15 800ee30: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800ee34: 697b ldr r3, [r7, #20] 800ee36: 2b00 cmp r3, #0 800ee38: f000 8111 beq.w 800f05e { switch (pllsource) 800ee3c: 69bb ldr r3, [r7, #24] 800ee3e: 2b02 cmp r3, #2 800ee40: f000 8083 beq.w 800ef4a 800ee44: 69bb ldr r3, [r7, #24] 800ee46: 2b02 cmp r3, #2 800ee48: f200 80a1 bhi.w 800ef8e 800ee4c: 69bb ldr r3, [r7, #24] 800ee4e: 2b00 cmp r3, #0 800ee50: d003 beq.n 800ee5a 800ee52: 69bb ldr r3, [r7, #24] 800ee54: 2b01 cmp r3, #1 800ee56: d056 beq.n 800ef06 800ee58: e099 b.n 800ef8e { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800ee5a: 4b88 ldr r3, [pc, #544] @ (800f07c ) 800ee5c: 681b ldr r3, [r3, #0] 800ee5e: f003 0320 and.w r3, r3, #32 800ee62: 2b00 cmp r3, #0 800ee64: d02d beq.n 800eec2 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ee66: 4b85 ldr r3, [pc, #532] @ (800f07c ) 800ee68: 681b ldr r3, [r3, #0] 800ee6a: 08db lsrs r3, r3, #3 800ee6c: f003 0303 and.w r3, r3, #3 800ee70: 4a83 ldr r2, [pc, #524] @ (800f080 ) 800ee72: fa22 f303 lsr.w r3, r2, r3 800ee76: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ee78: 68bb ldr r3, [r7, #8] 800ee7a: ee07 3a90 vmov s15, r3 800ee7e: eef8 6a67 vcvt.f32.u32 s13, s15 800ee82: 697b ldr r3, [r7, #20] 800ee84: ee07 3a90 vmov s15, r3 800ee88: eef8 7a67 vcvt.f32.u32 s15, s15 800ee8c: ee86 7aa7 vdiv.f32 s14, s13, s15 800ee90: 4b7a ldr r3, [pc, #488] @ (800f07c ) 800ee92: 6b1b ldr r3, [r3, #48] @ 0x30 800ee94: f3c3 0308 ubfx r3, r3, #0, #9 800ee98: ee07 3a90 vmov s15, r3 800ee9c: eef8 6a67 vcvt.f32.u32 s13, s15 800eea0: ed97 6a03 vldr s12, [r7, #12] 800eea4: eddf 5a77 vldr s11, [pc, #476] @ 800f084 800eea8: eec6 7a25 vdiv.f32 s15, s12, s11 800eeac: ee76 7aa7 vadd.f32 s15, s13, s15 800eeb0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eeb4: ee77 7aa6 vadd.f32 s15, s15, s13 800eeb8: ee67 7a27 vmul.f32 s15, s14, s15 800eebc: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800eec0: e087 b.n 800efd2 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eec2: 697b ldr r3, [r7, #20] 800eec4: ee07 3a90 vmov s15, r3 800eec8: eef8 7a67 vcvt.f32.u32 s15, s15 800eecc: eddf 6a6e vldr s13, [pc, #440] @ 800f088 800eed0: ee86 7aa7 vdiv.f32 s14, s13, s15 800eed4: 4b69 ldr r3, [pc, #420] @ (800f07c ) 800eed6: 6b1b ldr r3, [r3, #48] @ 0x30 800eed8: f3c3 0308 ubfx r3, r3, #0, #9 800eedc: ee07 3a90 vmov s15, r3 800eee0: eef8 6a67 vcvt.f32.u32 s13, s15 800eee4: ed97 6a03 vldr s12, [r7, #12] 800eee8: eddf 5a66 vldr s11, [pc, #408] @ 800f084 800eeec: eec6 7a25 vdiv.f32 s15, s12, s11 800eef0: ee76 7aa7 vadd.f32 s15, s13, s15 800eef4: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eef8: ee77 7aa6 vadd.f32 s15, s15, s13 800eefc: ee67 7a27 vmul.f32 s15, s14, s15 800ef00: edc7 7a07 vstr s15, [r7, #28] break; 800ef04: e065 b.n 800efd2 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef06: 697b ldr r3, [r7, #20] 800ef08: ee07 3a90 vmov s15, r3 800ef0c: eef8 7a67 vcvt.f32.u32 s15, s15 800ef10: eddf 6a5e vldr s13, [pc, #376] @ 800f08c 800ef14: ee86 7aa7 vdiv.f32 s14, s13, s15 800ef18: 4b58 ldr r3, [pc, #352] @ (800f07c ) 800ef1a: 6b1b ldr r3, [r3, #48] @ 0x30 800ef1c: f3c3 0308 ubfx r3, r3, #0, #9 800ef20: ee07 3a90 vmov s15, r3 800ef24: eef8 6a67 vcvt.f32.u32 s13, s15 800ef28: ed97 6a03 vldr s12, [r7, #12] 800ef2c: eddf 5a55 vldr s11, [pc, #340] @ 800f084 800ef30: eec6 7a25 vdiv.f32 s15, s12, s11 800ef34: ee76 7aa7 vadd.f32 s15, s13, s15 800ef38: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef3c: ee77 7aa6 vadd.f32 s15, s15, s13 800ef40: ee67 7a27 vmul.f32 s15, s14, s15 800ef44: edc7 7a07 vstr s15, [r7, #28] break; 800ef48: e043 b.n 800efd2 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef4a: 697b ldr r3, [r7, #20] 800ef4c: ee07 3a90 vmov s15, r3 800ef50: eef8 7a67 vcvt.f32.u32 s15, s15 800ef54: eddf 6a4e vldr s13, [pc, #312] @ 800f090 800ef58: ee86 7aa7 vdiv.f32 s14, s13, s15 800ef5c: 4b47 ldr r3, [pc, #284] @ (800f07c ) 800ef5e: 6b1b ldr r3, [r3, #48] @ 0x30 800ef60: f3c3 0308 ubfx r3, r3, #0, #9 800ef64: ee07 3a90 vmov s15, r3 800ef68: eef8 6a67 vcvt.f32.u32 s13, s15 800ef6c: ed97 6a03 vldr s12, [r7, #12] 800ef70: eddf 5a44 vldr s11, [pc, #272] @ 800f084 800ef74: eec6 7a25 vdiv.f32 s15, s12, s11 800ef78: ee76 7aa7 vadd.f32 s15, s13, s15 800ef7c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef80: ee77 7aa6 vadd.f32 s15, s15, s13 800ef84: ee67 7a27 vmul.f32 s15, s14, s15 800ef88: edc7 7a07 vstr s15, [r7, #28] break; 800ef8c: e021 b.n 800efd2 default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef8e: 697b ldr r3, [r7, #20] 800ef90: ee07 3a90 vmov s15, r3 800ef94: eef8 7a67 vcvt.f32.u32 s15, s15 800ef98: eddf 6a3b vldr s13, [pc, #236] @ 800f088 800ef9c: ee86 7aa7 vdiv.f32 s14, s13, s15 800efa0: 4b36 ldr r3, [pc, #216] @ (800f07c ) 800efa2: 6b1b ldr r3, [r3, #48] @ 0x30 800efa4: f3c3 0308 ubfx r3, r3, #0, #9 800efa8: ee07 3a90 vmov s15, r3 800efac: eef8 6a67 vcvt.f32.u32 s13, s15 800efb0: ed97 6a03 vldr s12, [r7, #12] 800efb4: eddf 5a33 vldr s11, [pc, #204] @ 800f084 800efb8: eec6 7a25 vdiv.f32 s15, s12, s11 800efbc: ee76 7aa7 vadd.f32 s15, s13, s15 800efc0: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800efc4: ee77 7aa6 vadd.f32 s15, s15, s13 800efc8: ee67 7a27 vmul.f32 s15, s14, s15 800efcc: edc7 7a07 vstr s15, [r7, #28] break; 800efd0: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800efd2: 4b2a ldr r3, [pc, #168] @ (800f07c ) 800efd4: 6b1b ldr r3, [r3, #48] @ 0x30 800efd6: 0a5b lsrs r3, r3, #9 800efd8: f003 037f and.w r3, r3, #127 @ 0x7f 800efdc: ee07 3a90 vmov s15, r3 800efe0: eef8 7a67 vcvt.f32.u32 s15, s15 800efe4: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800efe8: ee37 7a87 vadd.f32 s14, s15, s14 800efec: edd7 6a07 vldr s13, [r7, #28] 800eff0: eec6 7a87 vdiv.f32 s15, s13, s14 800eff4: eefc 7ae7 vcvt.u32.f32 s15, s15 800eff8: ee17 2a90 vmov r2, s15 800effc: 687b ldr r3, [r7, #4] 800effe: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800f000: 4b1e ldr r3, [pc, #120] @ (800f07c ) 800f002: 6b1b ldr r3, [r3, #48] @ 0x30 800f004: 0c1b lsrs r3, r3, #16 800f006: f003 037f and.w r3, r3, #127 @ 0x7f 800f00a: ee07 3a90 vmov s15, r3 800f00e: eef8 7a67 vcvt.f32.u32 s15, s15 800f012: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800f016: ee37 7a87 vadd.f32 s14, s15, s14 800f01a: edd7 6a07 vldr s13, [r7, #28] 800f01e: eec6 7a87 vdiv.f32 s15, s13, s14 800f022: eefc 7ae7 vcvt.u32.f32 s15, s15 800f026: ee17 2a90 vmov r2, s15 800f02a: 687b ldr r3, [r7, #4] 800f02c: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800f02e: 4b13 ldr r3, [pc, #76] @ (800f07c ) 800f030: 6b1b ldr r3, [r3, #48] @ 0x30 800f032: 0e1b lsrs r3, r3, #24 800f034: f003 037f and.w r3, r3, #127 @ 0x7f 800f038: ee07 3a90 vmov s15, r3 800f03c: eef8 7a67 vcvt.f32.u32 s15, s15 800f040: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800f044: ee37 7a87 vadd.f32 s14, s15, s14 800f048: edd7 6a07 vldr s13, [r7, #28] 800f04c: eec6 7a87 vdiv.f32 s15, s13, s14 800f050: eefc 7ae7 vcvt.u32.f32 s15, s15 800f054: ee17 2a90 vmov r2, s15 800f058: 687b ldr r3, [r7, #4] 800f05a: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800f05c: e008 b.n 800f070 PLL1_Clocks->PLL1_P_Frequency = 0U; 800f05e: 687b ldr r3, [r7, #4] 800f060: 2200 movs r2, #0 800f062: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800f064: 687b ldr r3, [r7, #4] 800f066: 2200 movs r2, #0 800f068: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800f06a: 687b ldr r3, [r7, #4] 800f06c: 2200 movs r2, #0 800f06e: 609a str r2, [r3, #8] } 800f070: bf00 nop 800f072: 3724 adds r7, #36 @ 0x24 800f074: 46bd mov sp, r7 800f076: f85d 7b04 ldr.w r7, [sp], #4 800f07a: 4770 bx lr 800f07c: 58024400 .word 0x58024400 800f080: 03d09000 .word 0x03d09000 800f084: 46000000 .word 0x46000000 800f088: 4c742400 .word 0x4c742400 800f08c: 4a742400 .word 0x4a742400 800f090: 4bbebc20 .word 0x4bbebc20 0800f094 : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800f094: b580 push {r7, lr} 800f096: b084 sub sp, #16 800f098: af00 add r7, sp, #0 800f09a: 6078 str r0, [r7, #4] 800f09c: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800f09e: 2300 movs r3, #0 800f0a0: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800f0a2: 4b53 ldr r3, [pc, #332] @ (800f1f0 ) 800f0a4: 6a9b ldr r3, [r3, #40] @ 0x28 800f0a6: f003 0303 and.w r3, r3, #3 800f0aa: 2b03 cmp r3, #3 800f0ac: d101 bne.n 800f0b2 { return HAL_ERROR; 800f0ae: 2301 movs r3, #1 800f0b0: e099 b.n 800f1e6 else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800f0b2: 4b4f ldr r3, [pc, #316] @ (800f1f0 ) 800f0b4: 681b ldr r3, [r3, #0] 800f0b6: 4a4e ldr r2, [pc, #312] @ (800f1f0 ) 800f0b8: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800f0bc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f0be: f7f6 fead bl 8005e1c 800f0c2: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800f0c4: e008 b.n 800f0d8 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800f0c6: f7f6 fea9 bl 8005e1c 800f0ca: 4602 mov r2, r0 800f0cc: 68bb ldr r3, [r7, #8] 800f0ce: 1ad3 subs r3, r2, r3 800f0d0: 2b02 cmp r3, #2 800f0d2: d901 bls.n 800f0d8 { return HAL_TIMEOUT; 800f0d4: 2303 movs r3, #3 800f0d6: e086 b.n 800f1e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800f0d8: 4b45 ldr r3, [pc, #276] @ (800f1f0 ) 800f0da: 681b ldr r3, [r3, #0] 800f0dc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f0e0: 2b00 cmp r3, #0 800f0e2: d1f0 bne.n 800f0c6 } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800f0e4: 4b42 ldr r3, [pc, #264] @ (800f1f0 ) 800f0e6: 6a9b ldr r3, [r3, #40] @ 0x28 800f0e8: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800f0ec: 687b ldr r3, [r7, #4] 800f0ee: 681b ldr r3, [r3, #0] 800f0f0: 031b lsls r3, r3, #12 800f0f2: 493f ldr r1, [pc, #252] @ (800f1f0 ) 800f0f4: 4313 orrs r3, r2 800f0f6: 628b str r3, [r1, #40] @ 0x28 800f0f8: 687b ldr r3, [r7, #4] 800f0fa: 685b ldr r3, [r3, #4] 800f0fc: 3b01 subs r3, #1 800f0fe: f3c3 0208 ubfx r2, r3, #0, #9 800f102: 687b ldr r3, [r7, #4] 800f104: 689b ldr r3, [r3, #8] 800f106: 3b01 subs r3, #1 800f108: 025b lsls r3, r3, #9 800f10a: b29b uxth r3, r3 800f10c: 431a orrs r2, r3 800f10e: 687b ldr r3, [r7, #4] 800f110: 68db ldr r3, [r3, #12] 800f112: 3b01 subs r3, #1 800f114: 041b lsls r3, r3, #16 800f116: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800f11a: 431a orrs r2, r3 800f11c: 687b ldr r3, [r7, #4] 800f11e: 691b ldr r3, [r3, #16] 800f120: 3b01 subs r3, #1 800f122: 061b lsls r3, r3, #24 800f124: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800f128: 4931 ldr r1, [pc, #196] @ (800f1f0 ) 800f12a: 4313 orrs r3, r2 800f12c: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800f12e: 4b30 ldr r3, [pc, #192] @ (800f1f0 ) 800f130: 6adb ldr r3, [r3, #44] @ 0x2c 800f132: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800f136: 687b ldr r3, [r7, #4] 800f138: 695b ldr r3, [r3, #20] 800f13a: 492d ldr r1, [pc, #180] @ (800f1f0 ) 800f13c: 4313 orrs r3, r2 800f13e: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800f140: 4b2b ldr r3, [pc, #172] @ (800f1f0 ) 800f142: 6adb ldr r3, [r3, #44] @ 0x2c 800f144: f023 0220 bic.w r2, r3, #32 800f148: 687b ldr r3, [r7, #4] 800f14a: 699b ldr r3, [r3, #24] 800f14c: 4928 ldr r1, [pc, #160] @ (800f1f0 ) 800f14e: 4313 orrs r3, r2 800f150: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800f152: 4b27 ldr r3, [pc, #156] @ (800f1f0 ) 800f154: 6adb ldr r3, [r3, #44] @ 0x2c 800f156: 4a26 ldr r2, [pc, #152] @ (800f1f0 ) 800f158: f023 0310 bic.w r3, r3, #16 800f15c: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800f15e: 4b24 ldr r3, [pc, #144] @ (800f1f0 ) 800f160: 6bda ldr r2, [r3, #60] @ 0x3c 800f162: 4b24 ldr r3, [pc, #144] @ (800f1f4 ) 800f164: 4013 ands r3, r2 800f166: 687a ldr r2, [r7, #4] 800f168: 69d2 ldr r2, [r2, #28] 800f16a: 00d2 lsls r2, r2, #3 800f16c: 4920 ldr r1, [pc, #128] @ (800f1f0 ) 800f16e: 4313 orrs r3, r2 800f170: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800f172: 4b1f ldr r3, [pc, #124] @ (800f1f0 ) 800f174: 6adb ldr r3, [r3, #44] @ 0x2c 800f176: 4a1e ldr r2, [pc, #120] @ (800f1f0 ) 800f178: f043 0310 orr.w r3, r3, #16 800f17c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800f17e: 683b ldr r3, [r7, #0] 800f180: 2b00 cmp r3, #0 800f182: d106 bne.n 800f192 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800f184: 4b1a ldr r3, [pc, #104] @ (800f1f0 ) 800f186: 6adb ldr r3, [r3, #44] @ 0x2c 800f188: 4a19 ldr r2, [pc, #100] @ (800f1f0 ) 800f18a: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800f18e: 62d3 str r3, [r2, #44] @ 0x2c 800f190: e00f b.n 800f1b2 } else if (Divider == DIVIDER_Q_UPDATE) 800f192: 683b ldr r3, [r7, #0] 800f194: 2b01 cmp r3, #1 800f196: d106 bne.n 800f1a6 { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800f198: 4b15 ldr r3, [pc, #84] @ (800f1f0 ) 800f19a: 6adb ldr r3, [r3, #44] @ 0x2c 800f19c: 4a14 ldr r2, [pc, #80] @ (800f1f0 ) 800f19e: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800f1a2: 62d3 str r3, [r2, #44] @ 0x2c 800f1a4: e005 b.n 800f1b2 } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800f1a6: 4b12 ldr r3, [pc, #72] @ (800f1f0 ) 800f1a8: 6adb ldr r3, [r3, #44] @ 0x2c 800f1aa: 4a11 ldr r2, [pc, #68] @ (800f1f0 ) 800f1ac: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800f1b0: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800f1b2: 4b0f ldr r3, [pc, #60] @ (800f1f0 ) 800f1b4: 681b ldr r3, [r3, #0] 800f1b6: 4a0e ldr r2, [pc, #56] @ (800f1f0 ) 800f1b8: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800f1bc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f1be: f7f6 fe2d bl 8005e1c 800f1c2: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800f1c4: e008 b.n 800f1d8 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800f1c6: f7f6 fe29 bl 8005e1c 800f1ca: 4602 mov r2, r0 800f1cc: 68bb ldr r3, [r7, #8] 800f1ce: 1ad3 subs r3, r2, r3 800f1d0: 2b02 cmp r3, #2 800f1d2: d901 bls.n 800f1d8 { return HAL_TIMEOUT; 800f1d4: 2303 movs r3, #3 800f1d6: e006 b.n 800f1e6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800f1d8: 4b05 ldr r3, [pc, #20] @ (800f1f0 ) 800f1da: 681b ldr r3, [r3, #0] 800f1dc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f1e0: 2b00 cmp r3, #0 800f1e2: d0f0 beq.n 800f1c6 } } return status; 800f1e4: 7bfb ldrb r3, [r7, #15] } 800f1e6: 4618 mov r0, r3 800f1e8: 3710 adds r7, #16 800f1ea: 46bd mov sp, r7 800f1ec: bd80 pop {r7, pc} 800f1ee: bf00 nop 800f1f0: 58024400 .word 0x58024400 800f1f4: ffff0007 .word 0xffff0007 0800f1f8 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800f1f8: b580 push {r7, lr} 800f1fa: b084 sub sp, #16 800f1fc: af00 add r7, sp, #0 800f1fe: 6078 str r0, [r7, #4] 800f200: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800f202: 2300 movs r3, #0 800f204: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800f206: 4b53 ldr r3, [pc, #332] @ (800f354 ) 800f208: 6a9b ldr r3, [r3, #40] @ 0x28 800f20a: f003 0303 and.w r3, r3, #3 800f20e: 2b03 cmp r3, #3 800f210: d101 bne.n 800f216 { return HAL_ERROR; 800f212: 2301 movs r3, #1 800f214: e099 b.n 800f34a else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800f216: 4b4f ldr r3, [pc, #316] @ (800f354 ) 800f218: 681b ldr r3, [r3, #0] 800f21a: 4a4e ldr r2, [pc, #312] @ (800f354 ) 800f21c: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800f220: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f222: f7f6 fdfb bl 8005e1c 800f226: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800f228: e008 b.n 800f23c { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f22a: f7f6 fdf7 bl 8005e1c 800f22e: 4602 mov r2, r0 800f230: 68bb ldr r3, [r7, #8] 800f232: 1ad3 subs r3, r2, r3 800f234: 2b02 cmp r3, #2 800f236: d901 bls.n 800f23c { return HAL_TIMEOUT; 800f238: 2303 movs r3, #3 800f23a: e086 b.n 800f34a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800f23c: 4b45 ldr r3, [pc, #276] @ (800f354 ) 800f23e: 681b ldr r3, [r3, #0] 800f240: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f244: 2b00 cmp r3, #0 800f246: d1f0 bne.n 800f22a } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800f248: 4b42 ldr r3, [pc, #264] @ (800f354 ) 800f24a: 6a9b ldr r3, [r3, #40] @ 0x28 800f24c: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 800f250: 687b ldr r3, [r7, #4] 800f252: 681b ldr r3, [r3, #0] 800f254: 051b lsls r3, r3, #20 800f256: 493f ldr r1, [pc, #252] @ (800f354 ) 800f258: 4313 orrs r3, r2 800f25a: 628b str r3, [r1, #40] @ 0x28 800f25c: 687b ldr r3, [r7, #4] 800f25e: 685b ldr r3, [r3, #4] 800f260: 3b01 subs r3, #1 800f262: f3c3 0208 ubfx r2, r3, #0, #9 800f266: 687b ldr r3, [r7, #4] 800f268: 689b ldr r3, [r3, #8] 800f26a: 3b01 subs r3, #1 800f26c: 025b lsls r3, r3, #9 800f26e: b29b uxth r3, r3 800f270: 431a orrs r2, r3 800f272: 687b ldr r3, [r7, #4] 800f274: 68db ldr r3, [r3, #12] 800f276: 3b01 subs r3, #1 800f278: 041b lsls r3, r3, #16 800f27a: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800f27e: 431a orrs r2, r3 800f280: 687b ldr r3, [r7, #4] 800f282: 691b ldr r3, [r3, #16] 800f284: 3b01 subs r3, #1 800f286: 061b lsls r3, r3, #24 800f288: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800f28c: 4931 ldr r1, [pc, #196] @ (800f354 ) 800f28e: 4313 orrs r3, r2 800f290: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800f292: 4b30 ldr r3, [pc, #192] @ (800f354 ) 800f294: 6adb ldr r3, [r3, #44] @ 0x2c 800f296: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800f29a: 687b ldr r3, [r7, #4] 800f29c: 695b ldr r3, [r3, #20] 800f29e: 492d ldr r1, [pc, #180] @ (800f354 ) 800f2a0: 4313 orrs r3, r2 800f2a2: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800f2a4: 4b2b ldr r3, [pc, #172] @ (800f354 ) 800f2a6: 6adb ldr r3, [r3, #44] @ 0x2c 800f2a8: f423 7200 bic.w r2, r3, #512 @ 0x200 800f2ac: 687b ldr r3, [r7, #4] 800f2ae: 699b ldr r3, [r3, #24] 800f2b0: 4928 ldr r1, [pc, #160] @ (800f354 ) 800f2b2: 4313 orrs r3, r2 800f2b4: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800f2b6: 4b27 ldr r3, [pc, #156] @ (800f354 ) 800f2b8: 6adb ldr r3, [r3, #44] @ 0x2c 800f2ba: 4a26 ldr r2, [pc, #152] @ (800f354 ) 800f2bc: f423 7380 bic.w r3, r3, #256 @ 0x100 800f2c0: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800f2c2: 4b24 ldr r3, [pc, #144] @ (800f354 ) 800f2c4: 6c5a ldr r2, [r3, #68] @ 0x44 800f2c6: 4b24 ldr r3, [pc, #144] @ (800f358 ) 800f2c8: 4013 ands r3, r2 800f2ca: 687a ldr r2, [r7, #4] 800f2cc: 69d2 ldr r2, [r2, #28] 800f2ce: 00d2 lsls r2, r2, #3 800f2d0: 4920 ldr r1, [pc, #128] @ (800f354 ) 800f2d2: 4313 orrs r3, r2 800f2d4: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800f2d6: 4b1f ldr r3, [pc, #124] @ (800f354 ) 800f2d8: 6adb ldr r3, [r3, #44] @ 0x2c 800f2da: 4a1e ldr r2, [pc, #120] @ (800f354 ) 800f2dc: f443 7380 orr.w r3, r3, #256 @ 0x100 800f2e0: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800f2e2: 683b ldr r3, [r7, #0] 800f2e4: 2b00 cmp r3, #0 800f2e6: d106 bne.n 800f2f6 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800f2e8: 4b1a ldr r3, [pc, #104] @ (800f354 ) 800f2ea: 6adb ldr r3, [r3, #44] @ 0x2c 800f2ec: 4a19 ldr r2, [pc, #100] @ (800f354 ) 800f2ee: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800f2f2: 62d3 str r3, [r2, #44] @ 0x2c 800f2f4: e00f b.n 800f316 } else if (Divider == DIVIDER_Q_UPDATE) 800f2f6: 683b ldr r3, [r7, #0] 800f2f8: 2b01 cmp r3, #1 800f2fa: d106 bne.n 800f30a { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800f2fc: 4b15 ldr r3, [pc, #84] @ (800f354 ) 800f2fe: 6adb ldr r3, [r3, #44] @ 0x2c 800f300: 4a14 ldr r2, [pc, #80] @ (800f354 ) 800f302: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800f306: 62d3 str r3, [r2, #44] @ 0x2c 800f308: e005 b.n 800f316 } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800f30a: 4b12 ldr r3, [pc, #72] @ (800f354 ) 800f30c: 6adb ldr r3, [r3, #44] @ 0x2c 800f30e: 4a11 ldr r2, [pc, #68] @ (800f354 ) 800f310: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800f314: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800f316: 4b0f ldr r3, [pc, #60] @ (800f354 ) 800f318: 681b ldr r3, [r3, #0] 800f31a: 4a0e ldr r2, [pc, #56] @ (800f354 ) 800f31c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800f320: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f322: f7f6 fd7b bl 8005e1c 800f326: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f328: e008 b.n 800f33c { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f32a: f7f6 fd77 bl 8005e1c 800f32e: 4602 mov r2, r0 800f330: 68bb ldr r3, [r7, #8] 800f332: 1ad3 subs r3, r2, r3 800f334: 2b02 cmp r3, #2 800f336: d901 bls.n 800f33c { return HAL_TIMEOUT; 800f338: 2303 movs r3, #3 800f33a: e006 b.n 800f34a while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f33c: 4b05 ldr r3, [pc, #20] @ (800f354 ) 800f33e: 681b ldr r3, [r3, #0] 800f340: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f344: 2b00 cmp r3, #0 800f346: d0f0 beq.n 800f32a } } return status; 800f348: 7bfb ldrb r3, [r7, #15] } 800f34a: 4618 mov r0, r3 800f34c: 3710 adds r7, #16 800f34e: 46bd mov sp, r7 800f350: bd80 pop {r7, pc} 800f352: bf00 nop 800f354: 58024400 .word 0x58024400 800f358: ffff0007 .word 0xffff0007 0800f35c : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 800f35c: b580 push {r7, lr} 800f35e: b084 sub sp, #16 800f360: af00 add r7, sp, #0 800f362: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 800f364: 687b ldr r3, [r7, #4] 800f366: 2b00 cmp r3, #0 800f368: d101 bne.n 800f36e { return HAL_ERROR; 800f36a: 2301 movs r3, #1 800f36c: e054 b.n 800f418 /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 800f36e: 687b ldr r3, [r7, #4] 800f370: 7a5b ldrb r3, [r3, #9] 800f372: b2db uxtb r3, r3 800f374: 2b00 cmp r3, #0 800f376: d105 bne.n 800f384 { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 800f378: 687b ldr r3, [r7, #4] 800f37a: 2200 movs r2, #0 800f37c: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 800f37e: 6878 ldr r0, [r7, #4] 800f380: f7f4 ff30 bl 80041e4 } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 800f384: 687b ldr r3, [r7, #4] 800f386: 2202 movs r2, #2 800f388: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800f38a: 687b ldr r3, [r7, #4] 800f38c: 681b ldr r3, [r3, #0] 800f38e: 681b ldr r3, [r3, #0] 800f390: f023 0120 bic.w r1, r3, #32 800f394: 687b ldr r3, [r7, #4] 800f396: 685a ldr r2, [r3, #4] 800f398: 687b ldr r3, [r7, #4] 800f39a: 681b ldr r3, [r3, #0] 800f39c: 430a orrs r2, r1 800f39e: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 800f3a0: 687b ldr r3, [r7, #4] 800f3a2: 681b ldr r3, [r3, #0] 800f3a4: 681a ldr r2, [r3, #0] 800f3a6: 687b ldr r3, [r7, #4] 800f3a8: 681b ldr r3, [r3, #0] 800f3aa: f042 0204 orr.w r2, r2, #4 800f3ae: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 800f3b0: 687b ldr r3, [r7, #4] 800f3b2: 681b ldr r3, [r3, #0] 800f3b4: 685b ldr r3, [r3, #4] 800f3b6: f003 0340 and.w r3, r3, #64 @ 0x40 800f3ba: 2b40 cmp r3, #64 @ 0x40 800f3bc: d104 bne.n 800f3c8 { hrng->State = HAL_RNG_STATE_ERROR; 800f3be: 687b ldr r3, [r7, #4] 800f3c0: 2204 movs r2, #4 800f3c2: 725a strb r2, [r3, #9] return HAL_ERROR; 800f3c4: 2301 movs r3, #1 800f3c6: e027 b.n 800f418 } /* Get tick */ tickstart = HAL_GetTick(); 800f3c8: f7f6 fd28 bl 8005e1c 800f3cc: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f3ce: e015 b.n 800f3fc { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800f3d0: f7f6 fd24 bl 8005e1c 800f3d4: 4602 mov r2, r0 800f3d6: 68fb ldr r3, [r7, #12] 800f3d8: 1ad3 subs r3, r2, r3 800f3da: 2b02 cmp r3, #2 800f3dc: d90e bls.n 800f3fc { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f3de: 687b ldr r3, [r7, #4] 800f3e0: 681b ldr r3, [r3, #0] 800f3e2: 685b ldr r3, [r3, #4] 800f3e4: f003 0304 and.w r3, r3, #4 800f3e8: 2b04 cmp r3, #4 800f3ea: d107 bne.n 800f3fc { hrng->State = HAL_RNG_STATE_ERROR; 800f3ec: 687b ldr r3, [r7, #4] 800f3ee: 2204 movs r2, #4 800f3f0: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800f3f2: 687b ldr r3, [r7, #4] 800f3f4: 2202 movs r2, #2 800f3f6: 60da str r2, [r3, #12] return HAL_ERROR; 800f3f8: 2301 movs r3, #1 800f3fa: e00d b.n 800f418 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f3fc: 687b ldr r3, [r7, #4] 800f3fe: 681b ldr r3, [r3, #0] 800f400: 685b ldr r3, [r3, #4] 800f402: f003 0304 and.w r3, r3, #4 800f406: 2b04 cmp r3, #4 800f408: d0e2 beq.n 800f3d0 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800f40a: 687b ldr r3, [r7, #4] 800f40c: 2201 movs r2, #1 800f40e: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800f410: 687b ldr r3, [r7, #4] 800f412: 2200 movs r2, #0 800f414: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 800f416: 2300 movs r3, #0 } 800f418: 4618 mov r0, r3 800f41a: 3710 adds r7, #16 800f41c: 46bd mov sp, r7 800f41e: bd80 pop {r7, pc} 0800f420 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800f420: b580 push {r7, lr} 800f422: b082 sub sp, #8 800f424: af00 add r7, sp, #0 800f426: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f428: 687b ldr r3, [r7, #4] 800f42a: 2b00 cmp r3, #0 800f42c: d101 bne.n 800f432 { return HAL_ERROR; 800f42e: 2301 movs r3, #1 800f430: e049 b.n 800f4c6 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f432: 687b ldr r3, [r7, #4] 800f434: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f438: b2db uxtb r3, r3 800f43a: 2b00 cmp r3, #0 800f43c: d106 bne.n 800f44c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f43e: 687b ldr r3, [r7, #4] 800f440: 2200 movs r2, #0 800f442: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800f446: 6878 ldr r0, [r7, #4] 800f448: f7f4 ff40 bl 80042cc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f44c: 687b ldr r3, [r7, #4] 800f44e: 2202 movs r2, #2 800f450: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f454: 687b ldr r3, [r7, #4] 800f456: 681a ldr r2, [r3, #0] 800f458: 687b ldr r3, [r7, #4] 800f45a: 3304 adds r3, #4 800f45c: 4619 mov r1, r3 800f45e: 4610 mov r0, r2 800f460: f001 f918 bl 8010694 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f464: 687b ldr r3, [r7, #4] 800f466: 2201 movs r2, #1 800f468: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f46c: 687b ldr r3, [r7, #4] 800f46e: 2201 movs r2, #1 800f470: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f474: 687b ldr r3, [r7, #4] 800f476: 2201 movs r2, #1 800f478: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f47c: 687b ldr r3, [r7, #4] 800f47e: 2201 movs r2, #1 800f480: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f484: 687b ldr r3, [r7, #4] 800f486: 2201 movs r2, #1 800f488: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f48c: 687b ldr r3, [r7, #4] 800f48e: 2201 movs r2, #1 800f490: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f494: 687b ldr r3, [r7, #4] 800f496: 2201 movs r2, #1 800f498: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f49c: 687b ldr r3, [r7, #4] 800f49e: 2201 movs r2, #1 800f4a0: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f4a4: 687b ldr r3, [r7, #4] 800f4a6: 2201 movs r2, #1 800f4a8: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f4ac: 687b ldr r3, [r7, #4] 800f4ae: 2201 movs r2, #1 800f4b0: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f4b4: 687b ldr r3, [r7, #4] 800f4b6: 2201 movs r2, #1 800f4b8: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f4bc: 687b ldr r3, [r7, #4] 800f4be: 2201 movs r2, #1 800f4c0: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f4c4: 2300 movs r3, #0 } 800f4c6: 4618 mov r0, r3 800f4c8: 3708 adds r7, #8 800f4ca: 46bd mov sp, r7 800f4cc: bd80 pop {r7, pc} ... 0800f4d0 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 800f4d0: b480 push {r7} 800f4d2: b085 sub sp, #20 800f4d4: af00 add r7, sp, #0 800f4d6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f4d8: 687b ldr r3, [r7, #4] 800f4da: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f4de: b2db uxtb r3, r3 800f4e0: 2b01 cmp r3, #1 800f4e2: d001 beq.n 800f4e8 { return HAL_ERROR; 800f4e4: 2301 movs r3, #1 800f4e6: e04c b.n 800f582 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f4e8: 687b ldr r3, [r7, #4] 800f4ea: 2202 movs r2, #2 800f4ec: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f4f0: 687b ldr r3, [r7, #4] 800f4f2: 681b ldr r3, [r3, #0] 800f4f4: 4a26 ldr r2, [pc, #152] @ (800f590 ) 800f4f6: 4293 cmp r3, r2 800f4f8: d022 beq.n 800f540 800f4fa: 687b ldr r3, [r7, #4] 800f4fc: 681b ldr r3, [r3, #0] 800f4fe: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f502: d01d beq.n 800f540 800f504: 687b ldr r3, [r7, #4] 800f506: 681b ldr r3, [r3, #0] 800f508: 4a22 ldr r2, [pc, #136] @ (800f594 ) 800f50a: 4293 cmp r3, r2 800f50c: d018 beq.n 800f540 800f50e: 687b ldr r3, [r7, #4] 800f510: 681b ldr r3, [r3, #0] 800f512: 4a21 ldr r2, [pc, #132] @ (800f598 ) 800f514: 4293 cmp r3, r2 800f516: d013 beq.n 800f540 800f518: 687b ldr r3, [r7, #4] 800f51a: 681b ldr r3, [r3, #0] 800f51c: 4a1f ldr r2, [pc, #124] @ (800f59c ) 800f51e: 4293 cmp r3, r2 800f520: d00e beq.n 800f540 800f522: 687b ldr r3, [r7, #4] 800f524: 681b ldr r3, [r3, #0] 800f526: 4a1e ldr r2, [pc, #120] @ (800f5a0 ) 800f528: 4293 cmp r3, r2 800f52a: d009 beq.n 800f540 800f52c: 687b ldr r3, [r7, #4] 800f52e: 681b ldr r3, [r3, #0] 800f530: 4a1c ldr r2, [pc, #112] @ (800f5a4 ) 800f532: 4293 cmp r3, r2 800f534: d004 beq.n 800f540 800f536: 687b ldr r3, [r7, #4] 800f538: 681b ldr r3, [r3, #0] 800f53a: 4a1b ldr r2, [pc, #108] @ (800f5a8 ) 800f53c: 4293 cmp r3, r2 800f53e: d115 bne.n 800f56c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f540: 687b ldr r3, [r7, #4] 800f542: 681b ldr r3, [r3, #0] 800f544: 689a ldr r2, [r3, #8] 800f546: 4b19 ldr r3, [pc, #100] @ (800f5ac ) 800f548: 4013 ands r3, r2 800f54a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f54c: 68fb ldr r3, [r7, #12] 800f54e: 2b06 cmp r3, #6 800f550: d015 beq.n 800f57e 800f552: 68fb ldr r3, [r7, #12] 800f554: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f558: d011 beq.n 800f57e { __HAL_TIM_ENABLE(htim); 800f55a: 687b ldr r3, [r7, #4] 800f55c: 681b ldr r3, [r3, #0] 800f55e: 681a ldr r2, [r3, #0] 800f560: 687b ldr r3, [r7, #4] 800f562: 681b ldr r3, [r3, #0] 800f564: f042 0201 orr.w r2, r2, #1 800f568: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f56a: e008 b.n 800f57e } } else { __HAL_TIM_ENABLE(htim); 800f56c: 687b ldr r3, [r7, #4] 800f56e: 681b ldr r3, [r3, #0] 800f570: 681a ldr r2, [r3, #0] 800f572: 687b ldr r3, [r7, #4] 800f574: 681b ldr r3, [r3, #0] 800f576: f042 0201 orr.w r2, r2, #1 800f57a: 601a str r2, [r3, #0] 800f57c: e000 b.n 800f580 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f57e: bf00 nop } /* Return function status */ return HAL_OK; 800f580: 2300 movs r3, #0 } 800f582: 4618 mov r0, r3 800f584: 3714 adds r7, #20 800f586: 46bd mov sp, r7 800f588: f85d 7b04 ldr.w r7, [sp], #4 800f58c: 4770 bx lr 800f58e: bf00 nop 800f590: 40010000 .word 0x40010000 800f594: 40000400 .word 0x40000400 800f598: 40000800 .word 0x40000800 800f59c: 40000c00 .word 0x40000c00 800f5a0: 40010400 .word 0x40010400 800f5a4: 40001800 .word 0x40001800 800f5a8: 40014000 .word 0x40014000 800f5ac: 00010007 .word 0x00010007 0800f5b0 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800f5b0: b480 push {r7} 800f5b2: b085 sub sp, #20 800f5b4: af00 add r7, sp, #0 800f5b6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f5b8: 687b ldr r3, [r7, #4] 800f5ba: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f5be: b2db uxtb r3, r3 800f5c0: 2b01 cmp r3, #1 800f5c2: d001 beq.n 800f5c8 { return HAL_ERROR; 800f5c4: 2301 movs r3, #1 800f5c6: e054 b.n 800f672 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f5c8: 687b ldr r3, [r7, #4] 800f5ca: 2202 movs r2, #2 800f5cc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800f5d0: 687b ldr r3, [r7, #4] 800f5d2: 681b ldr r3, [r3, #0] 800f5d4: 68da ldr r2, [r3, #12] 800f5d6: 687b ldr r3, [r7, #4] 800f5d8: 681b ldr r3, [r3, #0] 800f5da: f042 0201 orr.w r2, r2, #1 800f5de: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f5e0: 687b ldr r3, [r7, #4] 800f5e2: 681b ldr r3, [r3, #0] 800f5e4: 4a26 ldr r2, [pc, #152] @ (800f680 ) 800f5e6: 4293 cmp r3, r2 800f5e8: d022 beq.n 800f630 800f5ea: 687b ldr r3, [r7, #4] 800f5ec: 681b ldr r3, [r3, #0] 800f5ee: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f5f2: d01d beq.n 800f630 800f5f4: 687b ldr r3, [r7, #4] 800f5f6: 681b ldr r3, [r3, #0] 800f5f8: 4a22 ldr r2, [pc, #136] @ (800f684 ) 800f5fa: 4293 cmp r3, r2 800f5fc: d018 beq.n 800f630 800f5fe: 687b ldr r3, [r7, #4] 800f600: 681b ldr r3, [r3, #0] 800f602: 4a21 ldr r2, [pc, #132] @ (800f688 ) 800f604: 4293 cmp r3, r2 800f606: d013 beq.n 800f630 800f608: 687b ldr r3, [r7, #4] 800f60a: 681b ldr r3, [r3, #0] 800f60c: 4a1f ldr r2, [pc, #124] @ (800f68c ) 800f60e: 4293 cmp r3, r2 800f610: d00e beq.n 800f630 800f612: 687b ldr r3, [r7, #4] 800f614: 681b ldr r3, [r3, #0] 800f616: 4a1e ldr r2, [pc, #120] @ (800f690 ) 800f618: 4293 cmp r3, r2 800f61a: d009 beq.n 800f630 800f61c: 687b ldr r3, [r7, #4] 800f61e: 681b ldr r3, [r3, #0] 800f620: 4a1c ldr r2, [pc, #112] @ (800f694 ) 800f622: 4293 cmp r3, r2 800f624: d004 beq.n 800f630 800f626: 687b ldr r3, [r7, #4] 800f628: 681b ldr r3, [r3, #0] 800f62a: 4a1b ldr r2, [pc, #108] @ (800f698 ) 800f62c: 4293 cmp r3, r2 800f62e: d115 bne.n 800f65c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f630: 687b ldr r3, [r7, #4] 800f632: 681b ldr r3, [r3, #0] 800f634: 689a ldr r2, [r3, #8] 800f636: 4b19 ldr r3, [pc, #100] @ (800f69c ) 800f638: 4013 ands r3, r2 800f63a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f63c: 68fb ldr r3, [r7, #12] 800f63e: 2b06 cmp r3, #6 800f640: d015 beq.n 800f66e 800f642: 68fb ldr r3, [r7, #12] 800f644: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f648: d011 beq.n 800f66e { __HAL_TIM_ENABLE(htim); 800f64a: 687b ldr r3, [r7, #4] 800f64c: 681b ldr r3, [r3, #0] 800f64e: 681a ldr r2, [r3, #0] 800f650: 687b ldr r3, [r7, #4] 800f652: 681b ldr r3, [r3, #0] 800f654: f042 0201 orr.w r2, r2, #1 800f658: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f65a: e008 b.n 800f66e } } else { __HAL_TIM_ENABLE(htim); 800f65c: 687b ldr r3, [r7, #4] 800f65e: 681b ldr r3, [r3, #0] 800f660: 681a ldr r2, [r3, #0] 800f662: 687b ldr r3, [r7, #4] 800f664: 681b ldr r3, [r3, #0] 800f666: f042 0201 orr.w r2, r2, #1 800f66a: 601a str r2, [r3, #0] 800f66c: e000 b.n 800f670 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f66e: bf00 nop } /* Return function status */ return HAL_OK; 800f670: 2300 movs r3, #0 } 800f672: 4618 mov r0, r3 800f674: 3714 adds r7, #20 800f676: 46bd mov sp, r7 800f678: f85d 7b04 ldr.w r7, [sp], #4 800f67c: 4770 bx lr 800f67e: bf00 nop 800f680: 40010000 .word 0x40010000 800f684: 40000400 .word 0x40000400 800f688: 40000800 .word 0x40000800 800f68c: 40000c00 .word 0x40000c00 800f690: 40010400 .word 0x40010400 800f694: 40001800 .word 0x40001800 800f698: 40014000 .word 0x40014000 800f69c: 00010007 .word 0x00010007 0800f6a0 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800f6a0: b580 push {r7, lr} 800f6a2: b082 sub sp, #8 800f6a4: af00 add r7, sp, #0 800f6a6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f6a8: 687b ldr r3, [r7, #4] 800f6aa: 2b00 cmp r3, #0 800f6ac: d101 bne.n 800f6b2 { return HAL_ERROR; 800f6ae: 2301 movs r3, #1 800f6b0: e049 b.n 800f746 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f6b2: 687b ldr r3, [r7, #4] 800f6b4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f6b8: b2db uxtb r3, r3 800f6ba: 2b00 cmp r3, #0 800f6bc: d106 bne.n 800f6cc { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f6be: 687b ldr r3, [r7, #4] 800f6c0: 2200 movs r2, #0 800f6c2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800f6c6: 6878 ldr r0, [r7, #4] 800f6c8: f7f4 fdc6 bl 8004258 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f6cc: 687b ldr r3, [r7, #4] 800f6ce: 2202 movs r2, #2 800f6d0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f6d4: 687b ldr r3, [r7, #4] 800f6d6: 681a ldr r2, [r3, #0] 800f6d8: 687b ldr r3, [r7, #4] 800f6da: 3304 adds r3, #4 800f6dc: 4619 mov r1, r3 800f6de: 4610 mov r0, r2 800f6e0: f000 ffd8 bl 8010694 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f6e4: 687b ldr r3, [r7, #4] 800f6e6: 2201 movs r2, #1 800f6e8: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f6ec: 687b ldr r3, [r7, #4] 800f6ee: 2201 movs r2, #1 800f6f0: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f6f4: 687b ldr r3, [r7, #4] 800f6f6: 2201 movs r2, #1 800f6f8: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f6fc: 687b ldr r3, [r7, #4] 800f6fe: 2201 movs r2, #1 800f700: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f704: 687b ldr r3, [r7, #4] 800f706: 2201 movs r2, #1 800f708: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f70c: 687b ldr r3, [r7, #4] 800f70e: 2201 movs r2, #1 800f710: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f714: 687b ldr r3, [r7, #4] 800f716: 2201 movs r2, #1 800f718: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f71c: 687b ldr r3, [r7, #4] 800f71e: 2201 movs r2, #1 800f720: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f724: 687b ldr r3, [r7, #4] 800f726: 2201 movs r2, #1 800f728: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f72c: 687b ldr r3, [r7, #4] 800f72e: 2201 movs r2, #1 800f730: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f734: 687b ldr r3, [r7, #4] 800f736: 2201 movs r2, #1 800f738: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f73c: 687b ldr r3, [r7, #4] 800f73e: 2201 movs r2, #1 800f740: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f744: 2300 movs r3, #0 } 800f746: 4618 mov r0, r3 800f748: 3708 adds r7, #8 800f74a: 46bd mov sp, r7 800f74c: bd80 pop {r7, pc} ... 0800f750 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f750: b580 push {r7, lr} 800f752: b084 sub sp, #16 800f754: af00 add r7, sp, #0 800f756: 6078 str r0, [r7, #4] 800f758: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800f75a: 683b ldr r3, [r7, #0] 800f75c: 2b00 cmp r3, #0 800f75e: d109 bne.n 800f774 800f760: 687b ldr r3, [r7, #4] 800f762: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800f766: b2db uxtb r3, r3 800f768: 2b01 cmp r3, #1 800f76a: bf14 ite ne 800f76c: 2301 movne r3, #1 800f76e: 2300 moveq r3, #0 800f770: b2db uxtb r3, r3 800f772: e03c b.n 800f7ee 800f774: 683b ldr r3, [r7, #0] 800f776: 2b04 cmp r3, #4 800f778: d109 bne.n 800f78e 800f77a: 687b ldr r3, [r7, #4] 800f77c: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800f780: b2db uxtb r3, r3 800f782: 2b01 cmp r3, #1 800f784: bf14 ite ne 800f786: 2301 movne r3, #1 800f788: 2300 moveq r3, #0 800f78a: b2db uxtb r3, r3 800f78c: e02f b.n 800f7ee 800f78e: 683b ldr r3, [r7, #0] 800f790: 2b08 cmp r3, #8 800f792: d109 bne.n 800f7a8 800f794: 687b ldr r3, [r7, #4] 800f796: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800f79a: b2db uxtb r3, r3 800f79c: 2b01 cmp r3, #1 800f79e: bf14 ite ne 800f7a0: 2301 movne r3, #1 800f7a2: 2300 moveq r3, #0 800f7a4: b2db uxtb r3, r3 800f7a6: e022 b.n 800f7ee 800f7a8: 683b ldr r3, [r7, #0] 800f7aa: 2b0c cmp r3, #12 800f7ac: d109 bne.n 800f7c2 800f7ae: 687b ldr r3, [r7, #4] 800f7b0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800f7b4: b2db uxtb r3, r3 800f7b6: 2b01 cmp r3, #1 800f7b8: bf14 ite ne 800f7ba: 2301 movne r3, #1 800f7bc: 2300 moveq r3, #0 800f7be: b2db uxtb r3, r3 800f7c0: e015 b.n 800f7ee 800f7c2: 683b ldr r3, [r7, #0] 800f7c4: 2b10 cmp r3, #16 800f7c6: d109 bne.n 800f7dc 800f7c8: 687b ldr r3, [r7, #4] 800f7ca: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800f7ce: b2db uxtb r3, r3 800f7d0: 2b01 cmp r3, #1 800f7d2: bf14 ite ne 800f7d4: 2301 movne r3, #1 800f7d6: 2300 moveq r3, #0 800f7d8: b2db uxtb r3, r3 800f7da: e008 b.n 800f7ee 800f7dc: 687b ldr r3, [r7, #4] 800f7de: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800f7e2: b2db uxtb r3, r3 800f7e4: 2b01 cmp r3, #1 800f7e6: bf14 ite ne 800f7e8: 2301 movne r3, #1 800f7ea: 2300 moveq r3, #0 800f7ec: b2db uxtb r3, r3 800f7ee: 2b00 cmp r3, #0 800f7f0: d001 beq.n 800f7f6 { return HAL_ERROR; 800f7f2: 2301 movs r3, #1 800f7f4: e0a1 b.n 800f93a } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800f7f6: 683b ldr r3, [r7, #0] 800f7f8: 2b00 cmp r3, #0 800f7fa: d104 bne.n 800f806 800f7fc: 687b ldr r3, [r7, #4] 800f7fe: 2202 movs r2, #2 800f800: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f804: e023 b.n 800f84e 800f806: 683b ldr r3, [r7, #0] 800f808: 2b04 cmp r3, #4 800f80a: d104 bne.n 800f816 800f80c: 687b ldr r3, [r7, #4] 800f80e: 2202 movs r2, #2 800f810: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f814: e01b b.n 800f84e 800f816: 683b ldr r3, [r7, #0] 800f818: 2b08 cmp r3, #8 800f81a: d104 bne.n 800f826 800f81c: 687b ldr r3, [r7, #4] 800f81e: 2202 movs r2, #2 800f820: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f824: e013 b.n 800f84e 800f826: 683b ldr r3, [r7, #0] 800f828: 2b0c cmp r3, #12 800f82a: d104 bne.n 800f836 800f82c: 687b ldr r3, [r7, #4] 800f82e: 2202 movs r2, #2 800f830: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f834: e00b b.n 800f84e 800f836: 683b ldr r3, [r7, #0] 800f838: 2b10 cmp r3, #16 800f83a: d104 bne.n 800f846 800f83c: 687b ldr r3, [r7, #4] 800f83e: 2202 movs r2, #2 800f840: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f844: e003 b.n 800f84e 800f846: 687b ldr r3, [r7, #4] 800f848: 2202 movs r2, #2 800f84a: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800f84e: 687b ldr r3, [r7, #4] 800f850: 681b ldr r3, [r3, #0] 800f852: 2201 movs r2, #1 800f854: 6839 ldr r1, [r7, #0] 800f856: 4618 mov r0, r3 800f858: f001 fc60 bl 801111c if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f85c: 687b ldr r3, [r7, #4] 800f85e: 681b ldr r3, [r3, #0] 800f860: 4a38 ldr r2, [pc, #224] @ (800f944 ) 800f862: 4293 cmp r3, r2 800f864: d013 beq.n 800f88e 800f866: 687b ldr r3, [r7, #4] 800f868: 681b ldr r3, [r3, #0] 800f86a: 4a37 ldr r2, [pc, #220] @ (800f948 ) 800f86c: 4293 cmp r3, r2 800f86e: d00e beq.n 800f88e 800f870: 687b ldr r3, [r7, #4] 800f872: 681b ldr r3, [r3, #0] 800f874: 4a35 ldr r2, [pc, #212] @ (800f94c ) 800f876: 4293 cmp r3, r2 800f878: d009 beq.n 800f88e 800f87a: 687b ldr r3, [r7, #4] 800f87c: 681b ldr r3, [r3, #0] 800f87e: 4a34 ldr r2, [pc, #208] @ (800f950 ) 800f880: 4293 cmp r3, r2 800f882: d004 beq.n 800f88e 800f884: 687b ldr r3, [r7, #4] 800f886: 681b ldr r3, [r3, #0] 800f888: 4a32 ldr r2, [pc, #200] @ (800f954 ) 800f88a: 4293 cmp r3, r2 800f88c: d101 bne.n 800f892 800f88e: 2301 movs r3, #1 800f890: e000 b.n 800f894 800f892: 2300 movs r3, #0 800f894: 2b00 cmp r3, #0 800f896: d007 beq.n 800f8a8 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800f898: 687b ldr r3, [r7, #4] 800f89a: 681b ldr r3, [r3, #0] 800f89c: 6c5a ldr r2, [r3, #68] @ 0x44 800f89e: 687b ldr r3, [r7, #4] 800f8a0: 681b ldr r3, [r3, #0] 800f8a2: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800f8a6: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f8a8: 687b ldr r3, [r7, #4] 800f8aa: 681b ldr r3, [r3, #0] 800f8ac: 4a25 ldr r2, [pc, #148] @ (800f944 ) 800f8ae: 4293 cmp r3, r2 800f8b0: d022 beq.n 800f8f8 800f8b2: 687b ldr r3, [r7, #4] 800f8b4: 681b ldr r3, [r3, #0] 800f8b6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f8ba: d01d beq.n 800f8f8 800f8bc: 687b ldr r3, [r7, #4] 800f8be: 681b ldr r3, [r3, #0] 800f8c0: 4a25 ldr r2, [pc, #148] @ (800f958 ) 800f8c2: 4293 cmp r3, r2 800f8c4: d018 beq.n 800f8f8 800f8c6: 687b ldr r3, [r7, #4] 800f8c8: 681b ldr r3, [r3, #0] 800f8ca: 4a24 ldr r2, [pc, #144] @ (800f95c ) 800f8cc: 4293 cmp r3, r2 800f8ce: d013 beq.n 800f8f8 800f8d0: 687b ldr r3, [r7, #4] 800f8d2: 681b ldr r3, [r3, #0] 800f8d4: 4a22 ldr r2, [pc, #136] @ (800f960 ) 800f8d6: 4293 cmp r3, r2 800f8d8: d00e beq.n 800f8f8 800f8da: 687b ldr r3, [r7, #4] 800f8dc: 681b ldr r3, [r3, #0] 800f8de: 4a1a ldr r2, [pc, #104] @ (800f948 ) 800f8e0: 4293 cmp r3, r2 800f8e2: d009 beq.n 800f8f8 800f8e4: 687b ldr r3, [r7, #4] 800f8e6: 681b ldr r3, [r3, #0] 800f8e8: 4a1e ldr r2, [pc, #120] @ (800f964 ) 800f8ea: 4293 cmp r3, r2 800f8ec: d004 beq.n 800f8f8 800f8ee: 687b ldr r3, [r7, #4] 800f8f0: 681b ldr r3, [r3, #0] 800f8f2: 4a16 ldr r2, [pc, #88] @ (800f94c ) 800f8f4: 4293 cmp r3, r2 800f8f6: d115 bne.n 800f924 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f8f8: 687b ldr r3, [r7, #4] 800f8fa: 681b ldr r3, [r3, #0] 800f8fc: 689a ldr r2, [r3, #8] 800f8fe: 4b1a ldr r3, [pc, #104] @ (800f968 ) 800f900: 4013 ands r3, r2 800f902: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f904: 68fb ldr r3, [r7, #12] 800f906: 2b06 cmp r3, #6 800f908: d015 beq.n 800f936 800f90a: 68fb ldr r3, [r7, #12] 800f90c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f910: d011 beq.n 800f936 { __HAL_TIM_ENABLE(htim); 800f912: 687b ldr r3, [r7, #4] 800f914: 681b ldr r3, [r3, #0] 800f916: 681a ldr r2, [r3, #0] 800f918: 687b ldr r3, [r7, #4] 800f91a: 681b ldr r3, [r3, #0] 800f91c: f042 0201 orr.w r2, r2, #1 800f920: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f922: e008 b.n 800f936 } } else { __HAL_TIM_ENABLE(htim); 800f924: 687b ldr r3, [r7, #4] 800f926: 681b ldr r3, [r3, #0] 800f928: 681a ldr r2, [r3, #0] 800f92a: 687b ldr r3, [r7, #4] 800f92c: 681b ldr r3, [r3, #0] 800f92e: f042 0201 orr.w r2, r2, #1 800f932: 601a str r2, [r3, #0] 800f934: e000 b.n 800f938 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f936: bf00 nop } /* Return function status */ return HAL_OK; 800f938: 2300 movs r3, #0 } 800f93a: 4618 mov r0, r3 800f93c: 3710 adds r7, #16 800f93e: 46bd mov sp, r7 800f940: bd80 pop {r7, pc} 800f942: bf00 nop 800f944: 40010000 .word 0x40010000 800f948: 40010400 .word 0x40010400 800f94c: 40014000 .word 0x40014000 800f950: 40014400 .word 0x40014400 800f954: 40014800 .word 0x40014800 800f958: 40000400 .word 0x40000400 800f95c: 40000800 .word 0x40000800 800f960: 40000c00 .word 0x40000c00 800f964: 40001800 .word 0x40001800 800f968: 00010007 .word 0x00010007 0800f96c : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f96c: b580 push {r7, lr} 800f96e: b082 sub sp, #8 800f970: af00 add r7, sp, #0 800f972: 6078 str r0, [r7, #4] 800f974: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 800f976: 687b ldr r3, [r7, #4] 800f978: 681b ldr r3, [r3, #0] 800f97a: 2200 movs r2, #0 800f97c: 6839 ldr r1, [r7, #0] 800f97e: 4618 mov r0, r3 800f980: f001 fbcc bl 801111c if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f984: 687b ldr r3, [r7, #4] 800f986: 681b ldr r3, [r3, #0] 800f988: 4a3e ldr r2, [pc, #248] @ (800fa84 ) 800f98a: 4293 cmp r3, r2 800f98c: d013 beq.n 800f9b6 800f98e: 687b ldr r3, [r7, #4] 800f990: 681b ldr r3, [r3, #0] 800f992: 4a3d ldr r2, [pc, #244] @ (800fa88 ) 800f994: 4293 cmp r3, r2 800f996: d00e beq.n 800f9b6 800f998: 687b ldr r3, [r7, #4] 800f99a: 681b ldr r3, [r3, #0] 800f99c: 4a3b ldr r2, [pc, #236] @ (800fa8c ) 800f99e: 4293 cmp r3, r2 800f9a0: d009 beq.n 800f9b6 800f9a2: 687b ldr r3, [r7, #4] 800f9a4: 681b ldr r3, [r3, #0] 800f9a6: 4a3a ldr r2, [pc, #232] @ (800fa90 ) 800f9a8: 4293 cmp r3, r2 800f9aa: d004 beq.n 800f9b6 800f9ac: 687b ldr r3, [r7, #4] 800f9ae: 681b ldr r3, [r3, #0] 800f9b0: 4a38 ldr r2, [pc, #224] @ (800fa94 ) 800f9b2: 4293 cmp r3, r2 800f9b4: d101 bne.n 800f9ba 800f9b6: 2301 movs r3, #1 800f9b8: e000 b.n 800f9bc 800f9ba: 2300 movs r3, #0 800f9bc: 2b00 cmp r3, #0 800f9be: d017 beq.n 800f9f0 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 800f9c0: 687b ldr r3, [r7, #4] 800f9c2: 681b ldr r3, [r3, #0] 800f9c4: 6a1a ldr r2, [r3, #32] 800f9c6: f241 1311 movw r3, #4369 @ 0x1111 800f9ca: 4013 ands r3, r2 800f9cc: 2b00 cmp r3, #0 800f9ce: d10f bne.n 800f9f0 800f9d0: 687b ldr r3, [r7, #4] 800f9d2: 681b ldr r3, [r3, #0] 800f9d4: 6a1a ldr r2, [r3, #32] 800f9d6: f240 4344 movw r3, #1092 @ 0x444 800f9da: 4013 ands r3, r2 800f9dc: 2b00 cmp r3, #0 800f9de: d107 bne.n 800f9f0 800f9e0: 687b ldr r3, [r7, #4] 800f9e2: 681b ldr r3, [r3, #0] 800f9e4: 6c5a ldr r2, [r3, #68] @ 0x44 800f9e6: 687b ldr r3, [r7, #4] 800f9e8: 681b ldr r3, [r3, #0] 800f9ea: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800f9ee: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800f9f0: 687b ldr r3, [r7, #4] 800f9f2: 681b ldr r3, [r3, #0] 800f9f4: 6a1a ldr r2, [r3, #32] 800f9f6: f241 1311 movw r3, #4369 @ 0x1111 800f9fa: 4013 ands r3, r2 800f9fc: 2b00 cmp r3, #0 800f9fe: d10f bne.n 800fa20 800fa00: 687b ldr r3, [r7, #4] 800fa02: 681b ldr r3, [r3, #0] 800fa04: 6a1a ldr r2, [r3, #32] 800fa06: f240 4344 movw r3, #1092 @ 0x444 800fa0a: 4013 ands r3, r2 800fa0c: 2b00 cmp r3, #0 800fa0e: d107 bne.n 800fa20 800fa10: 687b ldr r3, [r7, #4] 800fa12: 681b ldr r3, [r3, #0] 800fa14: 681a ldr r2, [r3, #0] 800fa16: 687b ldr r3, [r7, #4] 800fa18: 681b ldr r3, [r3, #0] 800fa1a: f022 0201 bic.w r2, r2, #1 800fa1e: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 800fa20: 683b ldr r3, [r7, #0] 800fa22: 2b00 cmp r3, #0 800fa24: d104 bne.n 800fa30 800fa26: 687b ldr r3, [r7, #4] 800fa28: 2201 movs r2, #1 800fa2a: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fa2e: e023 b.n 800fa78 800fa30: 683b ldr r3, [r7, #0] 800fa32: 2b04 cmp r3, #4 800fa34: d104 bne.n 800fa40 800fa36: 687b ldr r3, [r7, #4] 800fa38: 2201 movs r2, #1 800fa3a: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fa3e: e01b b.n 800fa78 800fa40: 683b ldr r3, [r7, #0] 800fa42: 2b08 cmp r3, #8 800fa44: d104 bne.n 800fa50 800fa46: 687b ldr r3, [r7, #4] 800fa48: 2201 movs r2, #1 800fa4a: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fa4e: e013 b.n 800fa78 800fa50: 683b ldr r3, [r7, #0] 800fa52: 2b0c cmp r3, #12 800fa54: d104 bne.n 800fa60 800fa56: 687b ldr r3, [r7, #4] 800fa58: 2201 movs r2, #1 800fa5a: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fa5e: e00b b.n 800fa78 800fa60: 683b ldr r3, [r7, #0] 800fa62: 2b10 cmp r3, #16 800fa64: d104 bne.n 800fa70 800fa66: 687b ldr r3, [r7, #4] 800fa68: 2201 movs r2, #1 800fa6a: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fa6e: e003 b.n 800fa78 800fa70: 687b ldr r3, [r7, #4] 800fa72: 2201 movs r2, #1 800fa74: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Return function status */ return HAL_OK; 800fa78: 2300 movs r3, #0 } 800fa7a: 4618 mov r0, r3 800fa7c: 3708 adds r7, #8 800fa7e: 46bd mov sp, r7 800fa80: bd80 pop {r7, pc} 800fa82: bf00 nop 800fa84: 40010000 .word 0x40010000 800fa88: 40010400 .word 0x40010400 800fa8c: 40014000 .word 0x40014000 800fa90: 40014400 .word 0x40014400 800fa94: 40014800 .word 0x40014800 0800fa98 : * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { 800fa98: b580 push {r7, lr} 800fa9a: b082 sub sp, #8 800fa9c: af00 add r7, sp, #0 800fa9e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800faa0: 687b ldr r3, [r7, #4] 800faa2: 2b00 cmp r3, #0 800faa4: d101 bne.n 800faaa { return HAL_ERROR; 800faa6: 2301 movs r3, #1 800faa8: e049 b.n 800fb3e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800faaa: 687b ldr r3, [r7, #4] 800faac: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800fab0: b2db uxtb r3, r3 800fab2: 2b00 cmp r3, #0 800fab4: d106 bne.n 800fac4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800fab6: 687b ldr r3, [r7, #4] 800fab8: 2200 movs r2, #0 800faba: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); 800fabe: 6878 ldr r0, [r7, #4] 800fac0: f000 f841 bl 800fb46 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800fac4: 687b ldr r3, [r7, #4] 800fac6: 2202 movs r2, #2 800fac8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800facc: 687b ldr r3, [r7, #4] 800face: 681a ldr r2, [r3, #0] 800fad0: 687b ldr r3, [r7, #4] 800fad2: 3304 adds r3, #4 800fad4: 4619 mov r1, r3 800fad6: 4610 mov r0, r2 800fad8: f000 fddc bl 8010694 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800fadc: 687b ldr r3, [r7, #4] 800fade: 2201 movs r2, #1 800fae0: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800fae4: 687b ldr r3, [r7, #4] 800fae6: 2201 movs r2, #1 800fae8: f883 203e strb.w r2, [r3, #62] @ 0x3e 800faec: 687b ldr r3, [r7, #4] 800faee: 2201 movs r2, #1 800faf0: f883 203f strb.w r2, [r3, #63] @ 0x3f 800faf4: 687b ldr r3, [r7, #4] 800faf6: 2201 movs r2, #1 800faf8: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fafc: 687b ldr r3, [r7, #4] 800fafe: 2201 movs r2, #1 800fb00: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fb04: 687b ldr r3, [r7, #4] 800fb06: 2201 movs r2, #1 800fb08: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fb0c: 687b ldr r3, [r7, #4] 800fb0e: 2201 movs r2, #1 800fb10: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800fb14: 687b ldr r3, [r7, #4] 800fb16: 2201 movs r2, #1 800fb18: f883 2044 strb.w r2, [r3, #68] @ 0x44 800fb1c: 687b ldr r3, [r7, #4] 800fb1e: 2201 movs r2, #1 800fb20: f883 2045 strb.w r2, [r3, #69] @ 0x45 800fb24: 687b ldr r3, [r7, #4] 800fb26: 2201 movs r2, #1 800fb28: f883 2046 strb.w r2, [r3, #70] @ 0x46 800fb2c: 687b ldr r3, [r7, #4] 800fb2e: 2201 movs r2, #1 800fb30: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800fb34: 687b ldr r3, [r7, #4] 800fb36: 2201 movs r2, #1 800fb38: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800fb3c: 2300 movs r3, #0 } 800fb3e: 4618 mov r0, r3 800fb40: 3708 adds r7, #8 800fb42: 46bd mov sp, r7 800fb44: bd80 pop {r7, pc} 0800fb46 : * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { 800fb46: b480 push {r7} 800fb48: b083 sub sp, #12 800fb4a: af00 add r7, sp, #0 800fb4c: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } 800fb4e: bf00 nop 800fb50: 370c adds r7, #12 800fb52: 46bd mov sp, r7 800fb54: f85d 7b04 ldr.w r7, [sp], #4 800fb58: 4770 bx lr ... 0800fb5c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 800fb5c: b580 push {r7, lr} 800fb5e: b084 sub sp, #16 800fb60: af00 add r7, sp, #0 800fb62: 6078 str r0, [r7, #4] 800fb64: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800fb66: 2300 movs r3, #0 800fb68: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800fb6a: 683b ldr r3, [r7, #0] 800fb6c: 2b00 cmp r3, #0 800fb6e: d104 bne.n 800fb7a 800fb70: 687b ldr r3, [r7, #4] 800fb72: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800fb76: b2db uxtb r3, r3 800fb78: e023 b.n 800fbc2 800fb7a: 683b ldr r3, [r7, #0] 800fb7c: 2b04 cmp r3, #4 800fb7e: d104 bne.n 800fb8a 800fb80: 687b ldr r3, [r7, #4] 800fb82: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800fb86: b2db uxtb r3, r3 800fb88: e01b b.n 800fbc2 800fb8a: 683b ldr r3, [r7, #0] 800fb8c: 2b08 cmp r3, #8 800fb8e: d104 bne.n 800fb9a 800fb90: 687b ldr r3, [r7, #4] 800fb92: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800fb96: b2db uxtb r3, r3 800fb98: e013 b.n 800fbc2 800fb9a: 683b ldr r3, [r7, #0] 800fb9c: 2b0c cmp r3, #12 800fb9e: d104 bne.n 800fbaa 800fba0: 687b ldr r3, [r7, #4] 800fba2: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800fba6: b2db uxtb r3, r3 800fba8: e00b b.n 800fbc2 800fbaa: 683b ldr r3, [r7, #0] 800fbac: 2b10 cmp r3, #16 800fbae: d104 bne.n 800fbba 800fbb0: 687b ldr r3, [r7, #4] 800fbb2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800fbb6: b2db uxtb r3, r3 800fbb8: e003 b.n 800fbc2 800fbba: 687b ldr r3, [r7, #4] 800fbbc: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800fbc0: b2db uxtb r3, r3 800fbc2: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); 800fbc4: 683b ldr r3, [r7, #0] 800fbc6: 2b00 cmp r3, #0 800fbc8: d104 bne.n 800fbd4 800fbca: 687b ldr r3, [r7, #4] 800fbcc: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800fbd0: b2db uxtb r3, r3 800fbd2: e013 b.n 800fbfc 800fbd4: 683b ldr r3, [r7, #0] 800fbd6: 2b04 cmp r3, #4 800fbd8: d104 bne.n 800fbe4 800fbda: 687b ldr r3, [r7, #4] 800fbdc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800fbe0: b2db uxtb r3, r3 800fbe2: e00b b.n 800fbfc 800fbe4: 683b ldr r3, [r7, #0] 800fbe6: 2b08 cmp r3, #8 800fbe8: d104 bne.n 800fbf4 800fbea: 687b ldr r3, [r7, #4] 800fbec: f893 3046 ldrb.w r3, [r3, #70] @ 0x46 800fbf0: b2db uxtb r3, r3 800fbf2: e003 b.n 800fbfc 800fbf4: 687b ldr r3, [r7, #4] 800fbf6: f893 3047 ldrb.w r3, [r3, #71] @ 0x47 800fbfa: b2db uxtb r3, r3 800fbfc: 737b strb r3, [r7, #13] /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) 800fbfe: 7bbb ldrb r3, [r7, #14] 800fc00: 2b01 cmp r3, #1 800fc02: d102 bne.n 800fc0a || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) 800fc04: 7b7b ldrb r3, [r7, #13] 800fc06: 2b01 cmp r3, #1 800fc08: d001 beq.n 800fc0e { return HAL_ERROR; 800fc0a: 2301 movs r3, #1 800fc0c: e0e2 b.n 800fdd4 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800fc0e: 683b ldr r3, [r7, #0] 800fc10: 2b00 cmp r3, #0 800fc12: d104 bne.n 800fc1e 800fc14: 687b ldr r3, [r7, #4] 800fc16: 2202 movs r2, #2 800fc18: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fc1c: e023 b.n 800fc66 800fc1e: 683b ldr r3, [r7, #0] 800fc20: 2b04 cmp r3, #4 800fc22: d104 bne.n 800fc2e 800fc24: 687b ldr r3, [r7, #4] 800fc26: 2202 movs r2, #2 800fc28: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fc2c: e01b b.n 800fc66 800fc2e: 683b ldr r3, [r7, #0] 800fc30: 2b08 cmp r3, #8 800fc32: d104 bne.n 800fc3e 800fc34: 687b ldr r3, [r7, #4] 800fc36: 2202 movs r2, #2 800fc38: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fc3c: e013 b.n 800fc66 800fc3e: 683b ldr r3, [r7, #0] 800fc40: 2b0c cmp r3, #12 800fc42: d104 bne.n 800fc4e 800fc44: 687b ldr r3, [r7, #4] 800fc46: 2202 movs r2, #2 800fc48: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fc4c: e00b b.n 800fc66 800fc4e: 683b ldr r3, [r7, #0] 800fc50: 2b10 cmp r3, #16 800fc52: d104 bne.n 800fc5e 800fc54: 687b ldr r3, [r7, #4] 800fc56: 2202 movs r2, #2 800fc58: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fc5c: e003 b.n 800fc66 800fc5e: 687b ldr r3, [r7, #4] 800fc60: 2202 movs r2, #2 800fc62: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800fc66: 683b ldr r3, [r7, #0] 800fc68: 2b00 cmp r3, #0 800fc6a: d104 bne.n 800fc76 800fc6c: 687b ldr r3, [r7, #4] 800fc6e: 2202 movs r2, #2 800fc70: f883 2044 strb.w r2, [r3, #68] @ 0x44 800fc74: e013 b.n 800fc9e 800fc76: 683b ldr r3, [r7, #0] 800fc78: 2b04 cmp r3, #4 800fc7a: d104 bne.n 800fc86 800fc7c: 687b ldr r3, [r7, #4] 800fc7e: 2202 movs r2, #2 800fc80: f883 2045 strb.w r2, [r3, #69] @ 0x45 800fc84: e00b b.n 800fc9e 800fc86: 683b ldr r3, [r7, #0] 800fc88: 2b08 cmp r3, #8 800fc8a: d104 bne.n 800fc96 800fc8c: 687b ldr r3, [r7, #4] 800fc8e: 2202 movs r2, #2 800fc90: f883 2046 strb.w r2, [r3, #70] @ 0x46 800fc94: e003 b.n 800fc9e 800fc96: 687b ldr r3, [r7, #4] 800fc98: 2202 movs r2, #2 800fc9a: f883 2047 strb.w r2, [r3, #71] @ 0x47 switch (Channel) 800fc9e: 683b ldr r3, [r7, #0] 800fca0: 2b0c cmp r3, #12 800fca2: d841 bhi.n 800fd28 800fca4: a201 add r2, pc, #4 @ (adr r2, 800fcac ) 800fca6: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800fcaa: bf00 nop 800fcac: 0800fce1 .word 0x0800fce1 800fcb0: 0800fd29 .word 0x0800fd29 800fcb4: 0800fd29 .word 0x0800fd29 800fcb8: 0800fd29 .word 0x0800fd29 800fcbc: 0800fcf3 .word 0x0800fcf3 800fcc0: 0800fd29 .word 0x0800fd29 800fcc4: 0800fd29 .word 0x0800fd29 800fcc8: 0800fd29 .word 0x0800fd29 800fccc: 0800fd05 .word 0x0800fd05 800fcd0: 0800fd29 .word 0x0800fd29 800fcd4: 0800fd29 .word 0x0800fd29 800fcd8: 0800fd29 .word 0x0800fd29 800fcdc: 0800fd17 .word 0x0800fd17 { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 800fce0: 687b ldr r3, [r7, #4] 800fce2: 681b ldr r3, [r3, #0] 800fce4: 68da ldr r2, [r3, #12] 800fce6: 687b ldr r3, [r7, #4] 800fce8: 681b ldr r3, [r3, #0] 800fcea: f042 0202 orr.w r2, r2, #2 800fcee: 60da str r2, [r3, #12] break; 800fcf0: e01d b.n 800fd2e } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 800fcf2: 687b ldr r3, [r7, #4] 800fcf4: 681b ldr r3, [r3, #0] 800fcf6: 68da ldr r2, [r3, #12] 800fcf8: 687b ldr r3, [r7, #4] 800fcfa: 681b ldr r3, [r3, #0] 800fcfc: f042 0204 orr.w r2, r2, #4 800fd00: 60da str r2, [r3, #12] break; 800fd02: e014 b.n 800fd2e } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 800fd04: 687b ldr r3, [r7, #4] 800fd06: 681b ldr r3, [r3, #0] 800fd08: 68da ldr r2, [r3, #12] 800fd0a: 687b ldr r3, [r7, #4] 800fd0c: 681b ldr r3, [r3, #0] 800fd0e: f042 0208 orr.w r2, r2, #8 800fd12: 60da str r2, [r3, #12] break; 800fd14: e00b b.n 800fd2e } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 800fd16: 687b ldr r3, [r7, #4] 800fd18: 681b ldr r3, [r3, #0] 800fd1a: 68da ldr r2, [r3, #12] 800fd1c: 687b ldr r3, [r7, #4] 800fd1e: 681b ldr r3, [r3, #0] 800fd20: f042 0210 orr.w r2, r2, #16 800fd24: 60da str r2, [r3, #12] break; 800fd26: e002 b.n 800fd2e } default: status = HAL_ERROR; 800fd28: 2301 movs r3, #1 800fd2a: 73fb strb r3, [r7, #15] break; 800fd2c: bf00 nop } if (status == HAL_OK) 800fd2e: 7bfb ldrb r3, [r7, #15] 800fd30: 2b00 cmp r3, #0 800fd32: d14e bne.n 800fdd2 { /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800fd34: 687b ldr r3, [r7, #4] 800fd36: 681b ldr r3, [r3, #0] 800fd38: 2201 movs r2, #1 800fd3a: 6839 ldr r1, [r7, #0] 800fd3c: 4618 mov r0, r3 800fd3e: f001 f9ed bl 801111c /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800fd42: 687b ldr r3, [r7, #4] 800fd44: 681b ldr r3, [r3, #0] 800fd46: 4a25 ldr r2, [pc, #148] @ (800fddc ) 800fd48: 4293 cmp r3, r2 800fd4a: d022 beq.n 800fd92 800fd4c: 687b ldr r3, [r7, #4] 800fd4e: 681b ldr r3, [r3, #0] 800fd50: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fd54: d01d beq.n 800fd92 800fd56: 687b ldr r3, [r7, #4] 800fd58: 681b ldr r3, [r3, #0] 800fd5a: 4a21 ldr r2, [pc, #132] @ (800fde0 ) 800fd5c: 4293 cmp r3, r2 800fd5e: d018 beq.n 800fd92 800fd60: 687b ldr r3, [r7, #4] 800fd62: 681b ldr r3, [r3, #0] 800fd64: 4a1f ldr r2, [pc, #124] @ (800fde4 ) 800fd66: 4293 cmp r3, r2 800fd68: d013 beq.n 800fd92 800fd6a: 687b ldr r3, [r7, #4] 800fd6c: 681b ldr r3, [r3, #0] 800fd6e: 4a1e ldr r2, [pc, #120] @ (800fde8 ) 800fd70: 4293 cmp r3, r2 800fd72: d00e beq.n 800fd92 800fd74: 687b ldr r3, [r7, #4] 800fd76: 681b ldr r3, [r3, #0] 800fd78: 4a1c ldr r2, [pc, #112] @ (800fdec ) 800fd7a: 4293 cmp r3, r2 800fd7c: d009 beq.n 800fd92 800fd7e: 687b ldr r3, [r7, #4] 800fd80: 681b ldr r3, [r3, #0] 800fd82: 4a1b ldr r2, [pc, #108] @ (800fdf0 ) 800fd84: 4293 cmp r3, r2 800fd86: d004 beq.n 800fd92 800fd88: 687b ldr r3, [r7, #4] 800fd8a: 681b ldr r3, [r3, #0] 800fd8c: 4a19 ldr r2, [pc, #100] @ (800fdf4 ) 800fd8e: 4293 cmp r3, r2 800fd90: d115 bne.n 800fdbe { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800fd92: 687b ldr r3, [r7, #4] 800fd94: 681b ldr r3, [r3, #0] 800fd96: 689a ldr r2, [r3, #8] 800fd98: 4b17 ldr r3, [pc, #92] @ (800fdf8 ) 800fd9a: 4013 ands r3, r2 800fd9c: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fd9e: 68bb ldr r3, [r7, #8] 800fda0: 2b06 cmp r3, #6 800fda2: d015 beq.n 800fdd0 800fda4: 68bb ldr r3, [r7, #8] 800fda6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fdaa: d011 beq.n 800fdd0 { __HAL_TIM_ENABLE(htim); 800fdac: 687b ldr r3, [r7, #4] 800fdae: 681b ldr r3, [r3, #0] 800fdb0: 681a ldr r2, [r3, #0] 800fdb2: 687b ldr r3, [r7, #4] 800fdb4: 681b ldr r3, [r3, #0] 800fdb6: f042 0201 orr.w r2, r2, #1 800fdba: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fdbc: e008 b.n 800fdd0 } } else { __HAL_TIM_ENABLE(htim); 800fdbe: 687b ldr r3, [r7, #4] 800fdc0: 681b ldr r3, [r3, #0] 800fdc2: 681a ldr r2, [r3, #0] 800fdc4: 687b ldr r3, [r7, #4] 800fdc6: 681b ldr r3, [r3, #0] 800fdc8: f042 0201 orr.w r2, r2, #1 800fdcc: 601a str r2, [r3, #0] 800fdce: e000 b.n 800fdd2 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fdd0: bf00 nop } } /* Return function status */ return status; 800fdd2: 7bfb ldrb r3, [r7, #15] } 800fdd4: 4618 mov r0, r3 800fdd6: 3710 adds r7, #16 800fdd8: 46bd mov sp, r7 800fdda: bd80 pop {r7, pc} 800fddc: 40010000 .word 0x40010000 800fde0: 40000400 .word 0x40000400 800fde4: 40000800 .word 0x40000800 800fde8: 40000c00 .word 0x40000c00 800fdec: 40010400 .word 0x40010400 800fdf0: 40001800 .word 0x40001800 800fdf4: 40014000 .word 0x40014000 800fdf8: 00010007 .word 0x00010007 0800fdfc : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800fdfc: b580 push {r7, lr} 800fdfe: b084 sub sp, #16 800fe00: af00 add r7, sp, #0 800fe02: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800fe04: 687b ldr r3, [r7, #4] 800fe06: 681b ldr r3, [r3, #0] 800fe08: 68db ldr r3, [r3, #12] 800fe0a: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800fe0c: 687b ldr r3, [r7, #4] 800fe0e: 681b ldr r3, [r3, #0] 800fe10: 691b ldr r3, [r3, #16] 800fe12: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800fe14: 68bb ldr r3, [r7, #8] 800fe16: f003 0302 and.w r3, r3, #2 800fe1a: 2b00 cmp r3, #0 800fe1c: d020 beq.n 800fe60 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800fe1e: 68fb ldr r3, [r7, #12] 800fe20: f003 0302 and.w r3, r3, #2 800fe24: 2b00 cmp r3, #0 800fe26: d01b beq.n 800fe60 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800fe28: 687b ldr r3, [r7, #4] 800fe2a: 681b ldr r3, [r3, #0] 800fe2c: f06f 0202 mvn.w r2, #2 800fe30: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800fe32: 687b ldr r3, [r7, #4] 800fe34: 2201 movs r2, #1 800fe36: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800fe38: 687b ldr r3, [r7, #4] 800fe3a: 681b ldr r3, [r3, #0] 800fe3c: 699b ldr r3, [r3, #24] 800fe3e: f003 0303 and.w r3, r3, #3 800fe42: 2b00 cmp r3, #0 800fe44: d003 beq.n 800fe4e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fe46: 6878 ldr r0, [r7, #4] 800fe48: f7f1 fdb0 bl 80019ac 800fe4c: e005 b.n 800fe5a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fe4e: 6878 ldr r0, [r7, #4] 800fe50: f000 fbc8 bl 80105e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800fe54: 6878 ldr r0, [r7, #4] 800fe56: f000 fbcf bl 80105f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fe5a: 687b ldr r3, [r7, #4] 800fe5c: 2200 movs r2, #0 800fe5e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800fe60: 68bb ldr r3, [r7, #8] 800fe62: f003 0304 and.w r3, r3, #4 800fe66: 2b00 cmp r3, #0 800fe68: d020 beq.n 800feac { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800fe6a: 68fb ldr r3, [r7, #12] 800fe6c: f003 0304 and.w r3, r3, #4 800fe70: 2b00 cmp r3, #0 800fe72: d01b beq.n 800feac { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800fe74: 687b ldr r3, [r7, #4] 800fe76: 681b ldr r3, [r3, #0] 800fe78: f06f 0204 mvn.w r2, #4 800fe7c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800fe7e: 687b ldr r3, [r7, #4] 800fe80: 2202 movs r2, #2 800fe82: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800fe84: 687b ldr r3, [r7, #4] 800fe86: 681b ldr r3, [r3, #0] 800fe88: 699b ldr r3, [r3, #24] 800fe8a: f403 7340 and.w r3, r3, #768 @ 0x300 800fe8e: 2b00 cmp r3, #0 800fe90: d003 beq.n 800fe9a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fe92: 6878 ldr r0, [r7, #4] 800fe94: f7f1 fd8a bl 80019ac 800fe98: e005 b.n 800fea6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fe9a: 6878 ldr r0, [r7, #4] 800fe9c: f000 fba2 bl 80105e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800fea0: 6878 ldr r0, [r7, #4] 800fea2: f000 fba9 bl 80105f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fea6: 687b ldr r3, [r7, #4] 800fea8: 2200 movs r2, #0 800feaa: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800feac: 68bb ldr r3, [r7, #8] 800feae: f003 0308 and.w r3, r3, #8 800feb2: 2b00 cmp r3, #0 800feb4: d020 beq.n 800fef8 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800feb6: 68fb ldr r3, [r7, #12] 800feb8: f003 0308 and.w r3, r3, #8 800febc: 2b00 cmp r3, #0 800febe: d01b beq.n 800fef8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800fec0: 687b ldr r3, [r7, #4] 800fec2: 681b ldr r3, [r3, #0] 800fec4: f06f 0208 mvn.w r2, #8 800fec8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800feca: 687b ldr r3, [r7, #4] 800fecc: 2204 movs r2, #4 800fece: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800fed0: 687b ldr r3, [r7, #4] 800fed2: 681b ldr r3, [r3, #0] 800fed4: 69db ldr r3, [r3, #28] 800fed6: f003 0303 and.w r3, r3, #3 800feda: 2b00 cmp r3, #0 800fedc: d003 beq.n 800fee6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fede: 6878 ldr r0, [r7, #4] 800fee0: f7f1 fd64 bl 80019ac 800fee4: e005 b.n 800fef2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fee6: 6878 ldr r0, [r7, #4] 800fee8: f000 fb7c bl 80105e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800feec: 6878 ldr r0, [r7, #4] 800feee: f000 fb83 bl 80105f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fef2: 687b ldr r3, [r7, #4] 800fef4: 2200 movs r2, #0 800fef6: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800fef8: 68bb ldr r3, [r7, #8] 800fefa: f003 0310 and.w r3, r3, #16 800fefe: 2b00 cmp r3, #0 800ff00: d020 beq.n 800ff44 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800ff02: 68fb ldr r3, [r7, #12] 800ff04: f003 0310 and.w r3, r3, #16 800ff08: 2b00 cmp r3, #0 800ff0a: d01b beq.n 800ff44 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800ff0c: 687b ldr r3, [r7, #4] 800ff0e: 681b ldr r3, [r3, #0] 800ff10: f06f 0210 mvn.w r2, #16 800ff14: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800ff16: 687b ldr r3, [r7, #4] 800ff18: 2208 movs r2, #8 800ff1a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800ff1c: 687b ldr r3, [r7, #4] 800ff1e: 681b ldr r3, [r3, #0] 800ff20: 69db ldr r3, [r3, #28] 800ff22: f403 7340 and.w r3, r3, #768 @ 0x300 800ff26: 2b00 cmp r3, #0 800ff28: d003 beq.n 800ff32 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800ff2a: 6878 ldr r0, [r7, #4] 800ff2c: f7f1 fd3e bl 80019ac 800ff30: e005 b.n 800ff3e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800ff32: 6878 ldr r0, [r7, #4] 800ff34: f000 fb56 bl 80105e4 HAL_TIM_PWM_PulseFinishedCallback(htim); 800ff38: 6878 ldr r0, [r7, #4] 800ff3a: f000 fb5d bl 80105f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800ff3e: 687b ldr r3, [r7, #4] 800ff40: 2200 movs r2, #0 800ff42: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800ff44: 68bb ldr r3, [r7, #8] 800ff46: f003 0301 and.w r3, r3, #1 800ff4a: 2b00 cmp r3, #0 800ff4c: d00c beq.n 800ff68 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800ff4e: 68fb ldr r3, [r7, #12] 800ff50: f003 0301 and.w r3, r3, #1 800ff54: 2b00 cmp r3, #0 800ff56: d007 beq.n 800ff68 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800ff58: 687b ldr r3, [r7, #4] 800ff5a: 681b ldr r3, [r3, #0] 800ff5c: f06f 0201 mvn.w r2, #1 800ff60: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800ff62: 6878 ldr r0, [r7, #4] 800ff64: f7f1 ff7e bl 8001e64 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800ff68: 68bb ldr r3, [r7, #8] 800ff6a: f003 0380 and.w r3, r3, #128 @ 0x80 800ff6e: 2b00 cmp r3, #0 800ff70: d104 bne.n 800ff7c ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800ff72: 68bb ldr r3, [r7, #8] 800ff74: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800ff78: 2b00 cmp r3, #0 800ff7a: d00c beq.n 800ff96 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800ff7c: 68fb ldr r3, [r7, #12] 800ff7e: f003 0380 and.w r3, r3, #128 @ 0x80 800ff82: 2b00 cmp r3, #0 800ff84: d007 beq.n 800ff96 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800ff86: 687b ldr r3, [r7, #4] 800ff88: 681b ldr r3, [r3, #0] 800ff8a: f46f 5202 mvn.w r2, #8320 @ 0x2080 800ff8e: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800ff90: 6878 ldr r0, [r7, #4] 800ff92: f001 f9ff bl 8011394 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800ff96: 68bb ldr r3, [r7, #8] 800ff98: f403 7380 and.w r3, r3, #256 @ 0x100 800ff9c: 2b00 cmp r3, #0 800ff9e: d00c beq.n 800ffba { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800ffa0: 68fb ldr r3, [r7, #12] 800ffa2: f003 0380 and.w r3, r3, #128 @ 0x80 800ffa6: 2b00 cmp r3, #0 800ffa8: d007 beq.n 800ffba { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800ffaa: 687b ldr r3, [r7, #4] 800ffac: 681b ldr r3, [r3, #0] 800ffae: f46f 7280 mvn.w r2, #256 @ 0x100 800ffb2: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800ffb4: 6878 ldr r0, [r7, #4] 800ffb6: f001 f9f7 bl 80113a8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800ffba: 68bb ldr r3, [r7, #8] 800ffbc: f003 0340 and.w r3, r3, #64 @ 0x40 800ffc0: 2b00 cmp r3, #0 800ffc2: d00c beq.n 800ffde { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800ffc4: 68fb ldr r3, [r7, #12] 800ffc6: f003 0340 and.w r3, r3, #64 @ 0x40 800ffca: 2b00 cmp r3, #0 800ffcc: d007 beq.n 800ffde { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800ffce: 687b ldr r3, [r7, #4] 800ffd0: 681b ldr r3, [r3, #0] 800ffd2: f06f 0240 mvn.w r2, #64 @ 0x40 800ffd6: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800ffd8: 6878 ldr r0, [r7, #4] 800ffda: f000 fb17 bl 801060c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800ffde: 68bb ldr r3, [r7, #8] 800ffe0: f003 0320 and.w r3, r3, #32 800ffe4: 2b00 cmp r3, #0 800ffe6: d00c beq.n 8010002 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800ffe8: 68fb ldr r3, [r7, #12] 800ffea: f003 0320 and.w r3, r3, #32 800ffee: 2b00 cmp r3, #0 800fff0: d007 beq.n 8010002 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800fff2: 687b ldr r3, [r7, #4] 800fff4: 681b ldr r3, [r3, #0] 800fff6: f06f 0220 mvn.w r2, #32 800fffa: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800fffc: 6878 ldr r0, [r7, #4] 800fffe: f001 f9bf bl 8011380 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8010002: bf00 nop 8010004: 3710 adds r7, #16 8010006: 46bd mov sp, r7 8010008: bd80 pop {r7, pc} 0801000a : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { 801000a: b580 push {r7, lr} 801000c: b086 sub sp, #24 801000e: af00 add r7, sp, #0 8010010: 60f8 str r0, [r7, #12] 8010012: 60b9 str r1, [r7, #8] 8010014: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010016: 2300 movs r3, #0 8010018: 75fb strb r3, [r7, #23] assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); 801001a: 68fb ldr r3, [r7, #12] 801001c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010020: 2b01 cmp r3, #1 8010022: d101 bne.n 8010028 8010024: 2302 movs r3, #2 8010026: e088 b.n 801013a 8010028: 68fb ldr r3, [r7, #12] 801002a: 2201 movs r2, #1 801002c: f883 203c strb.w r2, [r3, #60] @ 0x3c if (Channel == TIM_CHANNEL_1) 8010030: 687b ldr r3, [r7, #4] 8010032: 2b00 cmp r3, #0 8010034: d11b bne.n 801006e { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, 8010036: 68fb ldr r3, [r7, #12] 8010038: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 801003a: 68bb ldr r3, [r7, #8] 801003c: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 801003e: 68bb ldr r3, [r7, #8] 8010040: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010042: 68bb ldr r3, [r7, #8] 8010044: 68db ldr r3, [r3, #12] TIM_TI1_SetConfig(htim->Instance, 8010046: f000 fea1 bl 8010d8c /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 801004a: 68fb ldr r3, [r7, #12] 801004c: 681b ldr r3, [r3, #0] 801004e: 699a ldr r2, [r3, #24] 8010050: 68fb ldr r3, [r7, #12] 8010052: 681b ldr r3, [r3, #0] 8010054: f022 020c bic.w r2, r2, #12 8010058: 619a str r2, [r3, #24] /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; 801005a: 68fb ldr r3, [r7, #12] 801005c: 681b ldr r3, [r3, #0] 801005e: 6999 ldr r1, [r3, #24] 8010060: 68bb ldr r3, [r7, #8] 8010062: 689a ldr r2, [r3, #8] 8010064: 68fb ldr r3, [r7, #12] 8010066: 681b ldr r3, [r3, #0] 8010068: 430a orrs r2, r1 801006a: 619a str r2, [r3, #24] 801006c: e060 b.n 8010130 } else if (Channel == TIM_CHANNEL_2) 801006e: 687b ldr r3, [r7, #4] 8010070: 2b04 cmp r3, #4 8010072: d11c bne.n 80100ae { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, 8010074: 68fb ldr r3, [r7, #12] 8010076: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 8010078: 68bb ldr r3, [r7, #8] 801007a: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 801007c: 68bb ldr r3, [r7, #8] 801007e: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010080: 68bb ldr r3, [r7, #8] 8010082: 68db ldr r3, [r3, #12] TIM_TI2_SetConfig(htim->Instance, 8010084: f000 ff25 bl 8010ed2 /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 8010088: 68fb ldr r3, [r7, #12] 801008a: 681b ldr r3, [r3, #0] 801008c: 699a ldr r2, [r3, #24] 801008e: 68fb ldr r3, [r7, #12] 8010090: 681b ldr r3, [r3, #0] 8010092: f422 6240 bic.w r2, r2, #3072 @ 0xc00 8010096: 619a str r2, [r3, #24] /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); 8010098: 68fb ldr r3, [r7, #12] 801009a: 681b ldr r3, [r3, #0] 801009c: 6999 ldr r1, [r3, #24] 801009e: 68bb ldr r3, [r7, #8] 80100a0: 689b ldr r3, [r3, #8] 80100a2: 021a lsls r2, r3, #8 80100a4: 68fb ldr r3, [r7, #12] 80100a6: 681b ldr r3, [r3, #0] 80100a8: 430a orrs r2, r1 80100aa: 619a str r2, [r3, #24] 80100ac: e040 b.n 8010130 } else if (Channel == TIM_CHANNEL_3) 80100ae: 687b ldr r3, [r7, #4] 80100b0: 2b08 cmp r3, #8 80100b2: d11b bne.n 80100ec { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, 80100b4: 68fb ldr r3, [r7, #12] 80100b6: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 80100b8: 68bb ldr r3, [r7, #8] 80100ba: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 80100bc: 68bb ldr r3, [r7, #8] 80100be: 685a ldr r2, [r3, #4] sConfig->ICFilter); 80100c0: 68bb ldr r3, [r7, #8] 80100c2: 68db ldr r3, [r3, #12] TIM_TI3_SetConfig(htim->Instance, 80100c4: f000 ff72 bl 8010fac /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 80100c8: 68fb ldr r3, [r7, #12] 80100ca: 681b ldr r3, [r3, #0] 80100cc: 69da ldr r2, [r3, #28] 80100ce: 68fb ldr r3, [r7, #12] 80100d0: 681b ldr r3, [r3, #0] 80100d2: f022 020c bic.w r2, r2, #12 80100d6: 61da str r2, [r3, #28] /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; 80100d8: 68fb ldr r3, [r7, #12] 80100da: 681b ldr r3, [r3, #0] 80100dc: 69d9 ldr r1, [r3, #28] 80100de: 68bb ldr r3, [r7, #8] 80100e0: 689a ldr r2, [r3, #8] 80100e2: 68fb ldr r3, [r7, #12] 80100e4: 681b ldr r3, [r3, #0] 80100e6: 430a orrs r2, r1 80100e8: 61da str r2, [r3, #28] 80100ea: e021 b.n 8010130 } else if (Channel == TIM_CHANNEL_4) 80100ec: 687b ldr r3, [r7, #4] 80100ee: 2b0c cmp r3, #12 80100f0: d11c bne.n 801012c { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, 80100f2: 68fb ldr r3, [r7, #12] 80100f4: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 80100f6: 68bb ldr r3, [r7, #8] 80100f8: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 80100fa: 68bb ldr r3, [r7, #8] 80100fc: 685a ldr r2, [r3, #4] sConfig->ICFilter); 80100fe: 68bb ldr r3, [r7, #8] 8010100: 68db ldr r3, [r3, #12] TIM_TI4_SetConfig(htim->Instance, 8010102: f000 ff8f bl 8011024 /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 8010106: 68fb ldr r3, [r7, #12] 8010108: 681b ldr r3, [r3, #0] 801010a: 69da ldr r2, [r3, #28] 801010c: 68fb ldr r3, [r7, #12] 801010e: 681b ldr r3, [r3, #0] 8010110: f422 6240 bic.w r2, r2, #3072 @ 0xc00 8010114: 61da str r2, [r3, #28] /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); 8010116: 68fb ldr r3, [r7, #12] 8010118: 681b ldr r3, [r3, #0] 801011a: 69d9 ldr r1, [r3, #28] 801011c: 68bb ldr r3, [r7, #8] 801011e: 689b ldr r3, [r3, #8] 8010120: 021a lsls r2, r3, #8 8010122: 68fb ldr r3, [r7, #12] 8010124: 681b ldr r3, [r3, #0] 8010126: 430a orrs r2, r1 8010128: 61da str r2, [r3, #28] 801012a: e001 b.n 8010130 } else { status = HAL_ERROR; 801012c: 2301 movs r3, #1 801012e: 75fb strb r3, [r7, #23] } __HAL_UNLOCK(htim); 8010130: 68fb ldr r3, [r7, #12] 8010132: 2200 movs r2, #0 8010134: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010138: 7dfb ldrb r3, [r7, #23] } 801013a: 4618 mov r0, r3 801013c: 3718 adds r7, #24 801013e: 46bd mov sp, r7 8010140: bd80 pop {r7, pc} ... 08010144 : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8010144: b580 push {r7, lr} 8010146: b086 sub sp, #24 8010148: af00 add r7, sp, #0 801014a: 60f8 str r0, [r7, #12] 801014c: 60b9 str r1, [r7, #8] 801014e: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010150: 2300 movs r3, #0 8010152: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8010154: 68fb ldr r3, [r7, #12] 8010156: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 801015a: 2b01 cmp r3, #1 801015c: d101 bne.n 8010162 801015e: 2302 movs r3, #2 8010160: e0ff b.n 8010362 8010162: 68fb ldr r3, [r7, #12] 8010164: 2201 movs r2, #1 8010166: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 801016a: 687b ldr r3, [r7, #4] 801016c: 2b14 cmp r3, #20 801016e: f200 80f0 bhi.w 8010352 8010172: a201 add r2, pc, #4 @ (adr r2, 8010178 ) 8010174: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010178: 080101cd .word 0x080101cd 801017c: 08010353 .word 0x08010353 8010180: 08010353 .word 0x08010353 8010184: 08010353 .word 0x08010353 8010188: 0801020d .word 0x0801020d 801018c: 08010353 .word 0x08010353 8010190: 08010353 .word 0x08010353 8010194: 08010353 .word 0x08010353 8010198: 0801024f .word 0x0801024f 801019c: 08010353 .word 0x08010353 80101a0: 08010353 .word 0x08010353 80101a4: 08010353 .word 0x08010353 80101a8: 0801028f .word 0x0801028f 80101ac: 08010353 .word 0x08010353 80101b0: 08010353 .word 0x08010353 80101b4: 08010353 .word 0x08010353 80101b8: 080102d1 .word 0x080102d1 80101bc: 08010353 .word 0x08010353 80101c0: 08010353 .word 0x08010353 80101c4: 08010353 .word 0x08010353 80101c8: 08010311 .word 0x08010311 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80101cc: 68fb ldr r3, [r7, #12] 80101ce: 681b ldr r3, [r3, #0] 80101d0: 68b9 ldr r1, [r7, #8] 80101d2: 4618 mov r0, r3 80101d4: f000 fb04 bl 80107e0 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 80101d8: 68fb ldr r3, [r7, #12] 80101da: 681b ldr r3, [r3, #0] 80101dc: 699a ldr r2, [r3, #24] 80101de: 68fb ldr r3, [r7, #12] 80101e0: 681b ldr r3, [r3, #0] 80101e2: f042 0208 orr.w r2, r2, #8 80101e6: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 80101e8: 68fb ldr r3, [r7, #12] 80101ea: 681b ldr r3, [r3, #0] 80101ec: 699a ldr r2, [r3, #24] 80101ee: 68fb ldr r3, [r7, #12] 80101f0: 681b ldr r3, [r3, #0] 80101f2: f022 0204 bic.w r2, r2, #4 80101f6: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 80101f8: 68fb ldr r3, [r7, #12] 80101fa: 681b ldr r3, [r3, #0] 80101fc: 6999 ldr r1, [r3, #24] 80101fe: 68bb ldr r3, [r7, #8] 8010200: 691a ldr r2, [r3, #16] 8010202: 68fb ldr r3, [r7, #12] 8010204: 681b ldr r3, [r3, #0] 8010206: 430a orrs r2, r1 8010208: 619a str r2, [r3, #24] break; 801020a: e0a5 b.n 8010358 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 801020c: 68fb ldr r3, [r7, #12] 801020e: 681b ldr r3, [r3, #0] 8010210: 68b9 ldr r1, [r7, #8] 8010212: 4618 mov r0, r3 8010214: f000 fb74 bl 8010900 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8010218: 68fb ldr r3, [r7, #12] 801021a: 681b ldr r3, [r3, #0] 801021c: 699a ldr r2, [r3, #24] 801021e: 68fb ldr r3, [r7, #12] 8010220: 681b ldr r3, [r3, #0] 8010222: f442 6200 orr.w r2, r2, #2048 @ 0x800 8010226: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8010228: 68fb ldr r3, [r7, #12] 801022a: 681b ldr r3, [r3, #0] 801022c: 699a ldr r2, [r3, #24] 801022e: 68fb ldr r3, [r7, #12] 8010230: 681b ldr r3, [r3, #0] 8010232: f422 6280 bic.w r2, r2, #1024 @ 0x400 8010236: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8010238: 68fb ldr r3, [r7, #12] 801023a: 681b ldr r3, [r3, #0] 801023c: 6999 ldr r1, [r3, #24] 801023e: 68bb ldr r3, [r7, #8] 8010240: 691b ldr r3, [r3, #16] 8010242: 021a lsls r2, r3, #8 8010244: 68fb ldr r3, [r7, #12] 8010246: 681b ldr r3, [r3, #0] 8010248: 430a orrs r2, r1 801024a: 619a str r2, [r3, #24] break; 801024c: e084 b.n 8010358 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 801024e: 68fb ldr r3, [r7, #12] 8010250: 681b ldr r3, [r3, #0] 8010252: 68b9 ldr r1, [r7, #8] 8010254: 4618 mov r0, r3 8010256: f000 fbdd bl 8010a14 /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 801025a: 68fb ldr r3, [r7, #12] 801025c: 681b ldr r3, [r3, #0] 801025e: 69da ldr r2, [r3, #28] 8010260: 68fb ldr r3, [r7, #12] 8010262: 681b ldr r3, [r3, #0] 8010264: f042 0208 orr.w r2, r2, #8 8010268: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 801026a: 68fb ldr r3, [r7, #12] 801026c: 681b ldr r3, [r3, #0] 801026e: 69da ldr r2, [r3, #28] 8010270: 68fb ldr r3, [r7, #12] 8010272: 681b ldr r3, [r3, #0] 8010274: f022 0204 bic.w r2, r2, #4 8010278: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 801027a: 68fb ldr r3, [r7, #12] 801027c: 681b ldr r3, [r3, #0] 801027e: 69d9 ldr r1, [r3, #28] 8010280: 68bb ldr r3, [r7, #8] 8010282: 691a ldr r2, [r3, #16] 8010284: 68fb ldr r3, [r7, #12] 8010286: 681b ldr r3, [r3, #0] 8010288: 430a orrs r2, r1 801028a: 61da str r2, [r3, #28] break; 801028c: e064 b.n 8010358 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 801028e: 68fb ldr r3, [r7, #12] 8010290: 681b ldr r3, [r3, #0] 8010292: 68b9 ldr r1, [r7, #8] 8010294: 4618 mov r0, r3 8010296: f000 fc45 bl 8010b24 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 801029a: 68fb ldr r3, [r7, #12] 801029c: 681b ldr r3, [r3, #0] 801029e: 69da ldr r2, [r3, #28] 80102a0: 68fb ldr r3, [r7, #12] 80102a2: 681b ldr r3, [r3, #0] 80102a4: f442 6200 orr.w r2, r2, #2048 @ 0x800 80102a8: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80102aa: 68fb ldr r3, [r7, #12] 80102ac: 681b ldr r3, [r3, #0] 80102ae: 69da ldr r2, [r3, #28] 80102b0: 68fb ldr r3, [r7, #12] 80102b2: 681b ldr r3, [r3, #0] 80102b4: f422 6280 bic.w r2, r2, #1024 @ 0x400 80102b8: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80102ba: 68fb ldr r3, [r7, #12] 80102bc: 681b ldr r3, [r3, #0] 80102be: 69d9 ldr r1, [r3, #28] 80102c0: 68bb ldr r3, [r7, #8] 80102c2: 691b ldr r3, [r3, #16] 80102c4: 021a lsls r2, r3, #8 80102c6: 68fb ldr r3, [r7, #12] 80102c8: 681b ldr r3, [r3, #0] 80102ca: 430a orrs r2, r1 80102cc: 61da str r2, [r3, #28] break; 80102ce: e043 b.n 8010358 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 80102d0: 68fb ldr r3, [r7, #12] 80102d2: 681b ldr r3, [r3, #0] 80102d4: 68b9 ldr r1, [r7, #8] 80102d6: 4618 mov r0, r3 80102d8: f000 fc8e bl 8010bf8 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 80102dc: 68fb ldr r3, [r7, #12] 80102de: 681b ldr r3, [r3, #0] 80102e0: 6d5a ldr r2, [r3, #84] @ 0x54 80102e2: 68fb ldr r3, [r7, #12] 80102e4: 681b ldr r3, [r3, #0] 80102e6: f042 0208 orr.w r2, r2, #8 80102ea: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 80102ec: 68fb ldr r3, [r7, #12] 80102ee: 681b ldr r3, [r3, #0] 80102f0: 6d5a ldr r2, [r3, #84] @ 0x54 80102f2: 68fb ldr r3, [r7, #12] 80102f4: 681b ldr r3, [r3, #0] 80102f6: f022 0204 bic.w r2, r2, #4 80102fa: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 80102fc: 68fb ldr r3, [r7, #12] 80102fe: 681b ldr r3, [r3, #0] 8010300: 6d59 ldr r1, [r3, #84] @ 0x54 8010302: 68bb ldr r3, [r7, #8] 8010304: 691a ldr r2, [r3, #16] 8010306: 68fb ldr r3, [r7, #12] 8010308: 681b ldr r3, [r3, #0] 801030a: 430a orrs r2, r1 801030c: 655a str r2, [r3, #84] @ 0x54 break; 801030e: e023 b.n 8010358 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 8010310: 68fb ldr r3, [r7, #12] 8010312: 681b ldr r3, [r3, #0] 8010314: 68b9 ldr r1, [r7, #8] 8010316: 4618 mov r0, r3 8010318: f000 fcd2 bl 8010cc0 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 801031c: 68fb ldr r3, [r7, #12] 801031e: 681b ldr r3, [r3, #0] 8010320: 6d5a ldr r2, [r3, #84] @ 0x54 8010322: 68fb ldr r3, [r7, #12] 8010324: 681b ldr r3, [r3, #0] 8010326: f442 6200 orr.w r2, r2, #2048 @ 0x800 801032a: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 801032c: 68fb ldr r3, [r7, #12] 801032e: 681b ldr r3, [r3, #0] 8010330: 6d5a ldr r2, [r3, #84] @ 0x54 8010332: 68fb ldr r3, [r7, #12] 8010334: 681b ldr r3, [r3, #0] 8010336: f422 6280 bic.w r2, r2, #1024 @ 0x400 801033a: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 801033c: 68fb ldr r3, [r7, #12] 801033e: 681b ldr r3, [r3, #0] 8010340: 6d59 ldr r1, [r3, #84] @ 0x54 8010342: 68bb ldr r3, [r7, #8] 8010344: 691b ldr r3, [r3, #16] 8010346: 021a lsls r2, r3, #8 8010348: 68fb ldr r3, [r7, #12] 801034a: 681b ldr r3, [r3, #0] 801034c: 430a orrs r2, r1 801034e: 655a str r2, [r3, #84] @ 0x54 break; 8010350: e002 b.n 8010358 } default: status = HAL_ERROR; 8010352: 2301 movs r3, #1 8010354: 75fb strb r3, [r7, #23] break; 8010356: bf00 nop } __HAL_UNLOCK(htim); 8010358: 68fb ldr r3, [r7, #12] 801035a: 2200 movs r2, #0 801035c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010360: 7dfb ldrb r3, [r7, #23] } 8010362: 4618 mov r0, r3 8010364: 3718 adds r7, #24 8010366: 46bd mov sp, r7 8010368: bd80 pop {r7, pc} 801036a: bf00 nop 0801036c : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 801036c: b580 push {r7, lr} 801036e: b084 sub sp, #16 8010370: af00 add r7, sp, #0 8010372: 6078 str r0, [r7, #4] 8010374: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8010376: 2300 movs r3, #0 8010378: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 801037a: 687b ldr r3, [r7, #4] 801037c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010380: 2b01 cmp r3, #1 8010382: d101 bne.n 8010388 8010384: 2302 movs r3, #2 8010386: e0dc b.n 8010542 8010388: 687b ldr r3, [r7, #4] 801038a: 2201 movs r2, #1 801038c: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8010390: 687b ldr r3, [r7, #4] 8010392: 2202 movs r2, #2 8010394: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8010398: 687b ldr r3, [r7, #4] 801039a: 681b ldr r3, [r3, #0] 801039c: 689b ldr r3, [r3, #8] 801039e: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 80103a0: 68ba ldr r2, [r7, #8] 80103a2: 4b6a ldr r3, [pc, #424] @ (801054c ) 80103a4: 4013 ands r3, r2 80103a6: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80103a8: 68bb ldr r3, [r7, #8] 80103aa: f423 437f bic.w r3, r3, #65280 @ 0xff00 80103ae: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 80103b0: 687b ldr r3, [r7, #4] 80103b2: 681b ldr r3, [r3, #0] 80103b4: 68ba ldr r2, [r7, #8] 80103b6: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80103b8: 683b ldr r3, [r7, #0] 80103ba: 681b ldr r3, [r3, #0] 80103bc: 4a64 ldr r2, [pc, #400] @ (8010550 ) 80103be: 4293 cmp r3, r2 80103c0: f000 80a9 beq.w 8010516 80103c4: 4a62 ldr r2, [pc, #392] @ (8010550 ) 80103c6: 4293 cmp r3, r2 80103c8: f200 80ae bhi.w 8010528 80103cc: 4a61 ldr r2, [pc, #388] @ (8010554 ) 80103ce: 4293 cmp r3, r2 80103d0: f000 80a1 beq.w 8010516 80103d4: 4a5f ldr r2, [pc, #380] @ (8010554 ) 80103d6: 4293 cmp r3, r2 80103d8: f200 80a6 bhi.w 8010528 80103dc: 4a5e ldr r2, [pc, #376] @ (8010558 ) 80103de: 4293 cmp r3, r2 80103e0: f000 8099 beq.w 8010516 80103e4: 4a5c ldr r2, [pc, #368] @ (8010558 ) 80103e6: 4293 cmp r3, r2 80103e8: f200 809e bhi.w 8010528 80103ec: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 80103f0: f000 8091 beq.w 8010516 80103f4: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 80103f8: f200 8096 bhi.w 8010528 80103fc: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8010400: f000 8089 beq.w 8010516 8010404: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8010408: f200 808e bhi.w 8010528 801040c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8010410: d03e beq.n 8010490 8010412: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8010416: f200 8087 bhi.w 8010528 801041a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801041e: f000 8086 beq.w 801052e 8010422: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010426: d87f bhi.n 8010528 8010428: 2b70 cmp r3, #112 @ 0x70 801042a: d01a beq.n 8010462 801042c: 2b70 cmp r3, #112 @ 0x70 801042e: d87b bhi.n 8010528 8010430: 2b60 cmp r3, #96 @ 0x60 8010432: d050 beq.n 80104d6 8010434: 2b60 cmp r3, #96 @ 0x60 8010436: d877 bhi.n 8010528 8010438: 2b50 cmp r3, #80 @ 0x50 801043a: d03c beq.n 80104b6 801043c: 2b50 cmp r3, #80 @ 0x50 801043e: d873 bhi.n 8010528 8010440: 2b40 cmp r3, #64 @ 0x40 8010442: d058 beq.n 80104f6 8010444: 2b40 cmp r3, #64 @ 0x40 8010446: d86f bhi.n 8010528 8010448: 2b30 cmp r3, #48 @ 0x30 801044a: d064 beq.n 8010516 801044c: 2b30 cmp r3, #48 @ 0x30 801044e: d86b bhi.n 8010528 8010450: 2b20 cmp r3, #32 8010452: d060 beq.n 8010516 8010454: 2b20 cmp r3, #32 8010456: d867 bhi.n 8010528 8010458: 2b00 cmp r3, #0 801045a: d05c beq.n 8010516 801045c: 2b10 cmp r3, #16 801045e: d05a beq.n 8010516 8010460: e062 b.n 8010528 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8010462: 687b ldr r3, [r7, #4] 8010464: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8010466: 683b ldr r3, [r7, #0] 8010468: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 801046a: 683b ldr r3, [r7, #0] 801046c: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801046e: 683b ldr r3, [r7, #0] 8010470: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8010472: f000 fe33 bl 80110dc /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8010476: 687b ldr r3, [r7, #4] 8010478: 681b ldr r3, [r3, #0] 801047a: 689b ldr r3, [r3, #8] 801047c: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 801047e: 68bb ldr r3, [r7, #8] 8010480: f043 0377 orr.w r3, r3, #119 @ 0x77 8010484: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8010486: 687b ldr r3, [r7, #4] 8010488: 681b ldr r3, [r3, #0] 801048a: 68ba ldr r2, [r7, #8] 801048c: 609a str r2, [r3, #8] break; 801048e: e04f b.n 8010530 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8010490: 687b ldr r3, [r7, #4] 8010492: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8010494: 683b ldr r3, [r7, #0] 8010496: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8010498: 683b ldr r3, [r7, #0] 801049a: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 801049c: 683b ldr r3, [r7, #0] 801049e: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80104a0: f000 fe1c bl 80110dc /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 80104a4: 687b ldr r3, [r7, #4] 80104a6: 681b ldr r3, [r3, #0] 80104a8: 689a ldr r2, [r3, #8] 80104aa: 687b ldr r3, [r7, #4] 80104ac: 681b ldr r3, [r3, #0] 80104ae: f442 4280 orr.w r2, r2, #16384 @ 0x4000 80104b2: 609a str r2, [r3, #8] break; 80104b4: e03c b.n 8010530 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80104b6: 687b ldr r3, [r7, #4] 80104b8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80104ba: 683b ldr r3, [r7, #0] 80104bc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80104be: 683b ldr r3, [r7, #0] 80104c0: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80104c2: 461a mov r2, r3 80104c4: f000 fcd6 bl 8010e74 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80104c8: 687b ldr r3, [r7, #4] 80104ca: 681b ldr r3, [r3, #0] 80104cc: 2150 movs r1, #80 @ 0x50 80104ce: 4618 mov r0, r3 80104d0: f000 fde6 bl 80110a0 break; 80104d4: e02c b.n 8010530 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80104d6: 687b ldr r3, [r7, #4] 80104d8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80104da: 683b ldr r3, [r7, #0] 80104dc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80104de: 683b ldr r3, [r7, #0] 80104e0: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 80104e2: 461a mov r2, r3 80104e4: f000 fd32 bl 8010f4c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80104e8: 687b ldr r3, [r7, #4] 80104ea: 681b ldr r3, [r3, #0] 80104ec: 2160 movs r1, #96 @ 0x60 80104ee: 4618 mov r0, r3 80104f0: f000 fdd6 bl 80110a0 break; 80104f4: e01c b.n 8010530 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80104f6: 687b ldr r3, [r7, #4] 80104f8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80104fa: 683b ldr r3, [r7, #0] 80104fc: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80104fe: 683b ldr r3, [r7, #0] 8010500: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8010502: 461a mov r2, r3 8010504: f000 fcb6 bl 8010e74 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8010508: 687b ldr r3, [r7, #4] 801050a: 681b ldr r3, [r3, #0] 801050c: 2140 movs r1, #64 @ 0x40 801050e: 4618 mov r0, r3 8010510: f000 fdc6 bl 80110a0 break; 8010514: e00c b.n 8010530 case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8010516: 687b ldr r3, [r7, #4] 8010518: 681a ldr r2, [r3, #0] 801051a: 683b ldr r3, [r7, #0] 801051c: 681b ldr r3, [r3, #0] 801051e: 4619 mov r1, r3 8010520: 4610 mov r0, r2 8010522: f000 fdbd bl 80110a0 break; 8010526: e003 b.n 8010530 } default: status = HAL_ERROR; 8010528: 2301 movs r3, #1 801052a: 73fb strb r3, [r7, #15] break; 801052c: e000 b.n 8010530 break; 801052e: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8010530: 687b ldr r3, [r7, #4] 8010532: 2201 movs r2, #1 8010534: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8010538: 687b ldr r3, [r7, #4] 801053a: 2200 movs r2, #0 801053c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010540: 7bfb ldrb r3, [r7, #15] } 8010542: 4618 mov r0, r3 8010544: 3710 adds r7, #16 8010546: 46bd mov sp, r7 8010548: bd80 pop {r7, pc} 801054a: bf00 nop 801054c: ffceff88 .word 0xffceff88 8010550: 00100040 .word 0x00100040 8010554: 00100030 .word 0x00100030 8010558: 00100020 .word 0x00100020 0801055c : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { 801055c: b480 push {r7} 801055e: b085 sub sp, #20 8010560: af00 add r7, sp, #0 8010562: 6078 str r0, [r7, #4] 8010564: 6039 str r1, [r7, #0] uint32_t tmpreg = 0U; 8010566: 2300 movs r3, #0 8010568: 60fb str r3, [r7, #12] switch (Channel) 801056a: 683b ldr r3, [r7, #0] 801056c: 2b0c cmp r3, #12 801056e: d831 bhi.n 80105d4 8010570: a201 add r2, pc, #4 @ (adr r2, 8010578 ) 8010572: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010576: bf00 nop 8010578: 080105ad .word 0x080105ad 801057c: 080105d5 .word 0x080105d5 8010580: 080105d5 .word 0x080105d5 8010584: 080105d5 .word 0x080105d5 8010588: 080105b7 .word 0x080105b7 801058c: 080105d5 .word 0x080105d5 8010590: 080105d5 .word 0x080105d5 8010594: 080105d5 .word 0x080105d5 8010598: 080105c1 .word 0x080105c1 801059c: 080105d5 .word 0x080105d5 80105a0: 080105d5 .word 0x080105d5 80105a4: 080105d5 .word 0x080105d5 80105a8: 080105cb .word 0x080105cb { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; 80105ac: 687b ldr r3, [r7, #4] 80105ae: 681b ldr r3, [r3, #0] 80105b0: 6b5b ldr r3, [r3, #52] @ 0x34 80105b2: 60fb str r3, [r7, #12] break; 80105b4: e00f b.n 80105d6 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; 80105b6: 687b ldr r3, [r7, #4] 80105b8: 681b ldr r3, [r3, #0] 80105ba: 6b9b ldr r3, [r3, #56] @ 0x38 80105bc: 60fb str r3, [r7, #12] break; 80105be: e00a b.n 80105d6 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; 80105c0: 687b ldr r3, [r7, #4] 80105c2: 681b ldr r3, [r3, #0] 80105c4: 6bdb ldr r3, [r3, #60] @ 0x3c 80105c6: 60fb str r3, [r7, #12] break; 80105c8: e005 b.n 80105d6 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; 80105ca: 687b ldr r3, [r7, #4] 80105cc: 681b ldr r3, [r3, #0] 80105ce: 6c1b ldr r3, [r3, #64] @ 0x40 80105d0: 60fb str r3, [r7, #12] break; 80105d2: e000 b.n 80105d6 } default: break; 80105d4: bf00 nop } return tmpreg; 80105d6: 68fb ldr r3, [r7, #12] } 80105d8: 4618 mov r0, r3 80105da: 3714 adds r7, #20 80105dc: 46bd mov sp, r7 80105de: f85d 7b04 ldr.w r7, [sp], #4 80105e2: 4770 bx lr 080105e4 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80105e4: b480 push {r7} 80105e6: b083 sub sp, #12 80105e8: af00 add r7, sp, #0 80105ea: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80105ec: bf00 nop 80105ee: 370c adds r7, #12 80105f0: 46bd mov sp, r7 80105f2: f85d 7b04 ldr.w r7, [sp], #4 80105f6: 4770 bx lr 080105f8 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80105f8: b480 push {r7} 80105fa: b083 sub sp, #12 80105fc: af00 add r7, sp, #0 80105fe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8010600: bf00 nop 8010602: 370c adds r7, #12 8010604: 46bd mov sp, r7 8010606: f85d 7b04 ldr.w r7, [sp], #4 801060a: 4770 bx lr 0801060c : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 801060c: b480 push {r7} 801060e: b083 sub sp, #12 8010610: af00 add r7, sp, #0 8010612: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8010614: bf00 nop 8010616: 370c adds r7, #12 8010618: 46bd mov sp, r7 801061a: f85d 7b04 ldr.w r7, [sp], #4 801061e: 4770 bx lr 08010620 : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 8010620: b480 push {r7} 8010622: b085 sub sp, #20 8010624: af00 add r7, sp, #0 8010626: 6078 str r0, [r7, #4] 8010628: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 801062a: 683b ldr r3, [r7, #0] 801062c: 2b00 cmp r3, #0 801062e: d104 bne.n 801063a 8010630: 687b ldr r3, [r7, #4] 8010632: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 8010636: b2db uxtb r3, r3 8010638: e023 b.n 8010682 801063a: 683b ldr r3, [r7, #0] 801063c: 2b04 cmp r3, #4 801063e: d104 bne.n 801064a 8010640: 687b ldr r3, [r7, #4] 8010642: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 8010646: b2db uxtb r3, r3 8010648: e01b b.n 8010682 801064a: 683b ldr r3, [r7, #0] 801064c: 2b08 cmp r3, #8 801064e: d104 bne.n 801065a 8010650: 687b ldr r3, [r7, #4] 8010652: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 8010656: b2db uxtb r3, r3 8010658: e013 b.n 8010682 801065a: 683b ldr r3, [r7, #0] 801065c: 2b0c cmp r3, #12 801065e: d104 bne.n 801066a 8010660: 687b ldr r3, [r7, #4] 8010662: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8010666: b2db uxtb r3, r3 8010668: e00b b.n 8010682 801066a: 683b ldr r3, [r7, #0] 801066c: 2b10 cmp r3, #16 801066e: d104 bne.n 801067a 8010670: 687b ldr r3, [r7, #4] 8010672: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 8010676: b2db uxtb r3, r3 8010678: e003 b.n 8010682 801067a: 687b ldr r3, [r7, #4] 801067c: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8010680: b2db uxtb r3, r3 8010682: 73fb strb r3, [r7, #15] return channel_state; 8010684: 7bfb ldrb r3, [r7, #15] } 8010686: 4618 mov r0, r3 8010688: 3714 adds r7, #20 801068a: 46bd mov sp, r7 801068c: f85d 7b04 ldr.w r7, [sp], #4 8010690: 4770 bx lr ... 08010694 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8010694: b480 push {r7} 8010696: b085 sub sp, #20 8010698: af00 add r7, sp, #0 801069a: 6078 str r0, [r7, #4] 801069c: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 801069e: 687b ldr r3, [r7, #4] 80106a0: 681b ldr r3, [r3, #0] 80106a2: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80106a4: 687b ldr r3, [r7, #4] 80106a6: 4a46 ldr r2, [pc, #280] @ (80107c0 ) 80106a8: 4293 cmp r3, r2 80106aa: d013 beq.n 80106d4 80106ac: 687b ldr r3, [r7, #4] 80106ae: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80106b2: d00f beq.n 80106d4 80106b4: 687b ldr r3, [r7, #4] 80106b6: 4a43 ldr r2, [pc, #268] @ (80107c4 ) 80106b8: 4293 cmp r3, r2 80106ba: d00b beq.n 80106d4 80106bc: 687b ldr r3, [r7, #4] 80106be: 4a42 ldr r2, [pc, #264] @ (80107c8 ) 80106c0: 4293 cmp r3, r2 80106c2: d007 beq.n 80106d4 80106c4: 687b ldr r3, [r7, #4] 80106c6: 4a41 ldr r2, [pc, #260] @ (80107cc ) 80106c8: 4293 cmp r3, r2 80106ca: d003 beq.n 80106d4 80106cc: 687b ldr r3, [r7, #4] 80106ce: 4a40 ldr r2, [pc, #256] @ (80107d0 ) 80106d0: 4293 cmp r3, r2 80106d2: d108 bne.n 80106e6 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80106d4: 68fb ldr r3, [r7, #12] 80106d6: f023 0370 bic.w r3, r3, #112 @ 0x70 80106da: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80106dc: 683b ldr r3, [r7, #0] 80106de: 685b ldr r3, [r3, #4] 80106e0: 68fa ldr r2, [r7, #12] 80106e2: 4313 orrs r3, r2 80106e4: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80106e6: 687b ldr r3, [r7, #4] 80106e8: 4a35 ldr r2, [pc, #212] @ (80107c0 ) 80106ea: 4293 cmp r3, r2 80106ec: d01f beq.n 801072e 80106ee: 687b ldr r3, [r7, #4] 80106f0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80106f4: d01b beq.n 801072e 80106f6: 687b ldr r3, [r7, #4] 80106f8: 4a32 ldr r2, [pc, #200] @ (80107c4 ) 80106fa: 4293 cmp r3, r2 80106fc: d017 beq.n 801072e 80106fe: 687b ldr r3, [r7, #4] 8010700: 4a31 ldr r2, [pc, #196] @ (80107c8 ) 8010702: 4293 cmp r3, r2 8010704: d013 beq.n 801072e 8010706: 687b ldr r3, [r7, #4] 8010708: 4a30 ldr r2, [pc, #192] @ (80107cc ) 801070a: 4293 cmp r3, r2 801070c: d00f beq.n 801072e 801070e: 687b ldr r3, [r7, #4] 8010710: 4a2f ldr r2, [pc, #188] @ (80107d0 ) 8010712: 4293 cmp r3, r2 8010714: d00b beq.n 801072e 8010716: 687b ldr r3, [r7, #4] 8010718: 4a2e ldr r2, [pc, #184] @ (80107d4 ) 801071a: 4293 cmp r3, r2 801071c: d007 beq.n 801072e 801071e: 687b ldr r3, [r7, #4] 8010720: 4a2d ldr r2, [pc, #180] @ (80107d8 ) 8010722: 4293 cmp r3, r2 8010724: d003 beq.n 801072e 8010726: 687b ldr r3, [r7, #4] 8010728: 4a2c ldr r2, [pc, #176] @ (80107dc ) 801072a: 4293 cmp r3, r2 801072c: d108 bne.n 8010740 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 801072e: 68fb ldr r3, [r7, #12] 8010730: f423 7340 bic.w r3, r3, #768 @ 0x300 8010734: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8010736: 683b ldr r3, [r7, #0] 8010738: 68db ldr r3, [r3, #12] 801073a: 68fa ldr r2, [r7, #12] 801073c: 4313 orrs r3, r2 801073e: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8010740: 68fb ldr r3, [r7, #12] 8010742: f023 0280 bic.w r2, r3, #128 @ 0x80 8010746: 683b ldr r3, [r7, #0] 8010748: 695b ldr r3, [r3, #20] 801074a: 4313 orrs r3, r2 801074c: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 801074e: 687b ldr r3, [r7, #4] 8010750: 68fa ldr r2, [r7, #12] 8010752: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8010754: 683b ldr r3, [r7, #0] 8010756: 689a ldr r2, [r3, #8] 8010758: 687b ldr r3, [r7, #4] 801075a: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 801075c: 683b ldr r3, [r7, #0] 801075e: 681a ldr r2, [r3, #0] 8010760: 687b ldr r3, [r7, #4] 8010762: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8010764: 687b ldr r3, [r7, #4] 8010766: 4a16 ldr r2, [pc, #88] @ (80107c0 ) 8010768: 4293 cmp r3, r2 801076a: d00f beq.n 801078c 801076c: 687b ldr r3, [r7, #4] 801076e: 4a18 ldr r2, [pc, #96] @ (80107d0 ) 8010770: 4293 cmp r3, r2 8010772: d00b beq.n 801078c 8010774: 687b ldr r3, [r7, #4] 8010776: 4a17 ldr r2, [pc, #92] @ (80107d4 ) 8010778: 4293 cmp r3, r2 801077a: d007 beq.n 801078c 801077c: 687b ldr r3, [r7, #4] 801077e: 4a16 ldr r2, [pc, #88] @ (80107d8 ) 8010780: 4293 cmp r3, r2 8010782: d003 beq.n 801078c 8010784: 687b ldr r3, [r7, #4] 8010786: 4a15 ldr r2, [pc, #84] @ (80107dc ) 8010788: 4293 cmp r3, r2 801078a: d103 bne.n 8010794 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 801078c: 683b ldr r3, [r7, #0] 801078e: 691a ldr r2, [r3, #16] 8010790: 687b ldr r3, [r7, #4] 8010792: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8010794: 687b ldr r3, [r7, #4] 8010796: 2201 movs r2, #1 8010798: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 801079a: 687b ldr r3, [r7, #4] 801079c: 691b ldr r3, [r3, #16] 801079e: f003 0301 and.w r3, r3, #1 80107a2: 2b01 cmp r3, #1 80107a4: d105 bne.n 80107b2 { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80107a6: 687b ldr r3, [r7, #4] 80107a8: 691b ldr r3, [r3, #16] 80107aa: f023 0201 bic.w r2, r3, #1 80107ae: 687b ldr r3, [r7, #4] 80107b0: 611a str r2, [r3, #16] } } 80107b2: bf00 nop 80107b4: 3714 adds r7, #20 80107b6: 46bd mov sp, r7 80107b8: f85d 7b04 ldr.w r7, [sp], #4 80107bc: 4770 bx lr 80107be: bf00 nop 80107c0: 40010000 .word 0x40010000 80107c4: 40000400 .word 0x40000400 80107c8: 40000800 .word 0x40000800 80107cc: 40000c00 .word 0x40000c00 80107d0: 40010400 .word 0x40010400 80107d4: 40014000 .word 0x40014000 80107d8: 40014400 .word 0x40014400 80107dc: 40014800 .word 0x40014800 080107e0 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80107e0: b480 push {r7} 80107e2: b087 sub sp, #28 80107e4: af00 add r7, sp, #0 80107e6: 6078 str r0, [r7, #4] 80107e8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80107ea: 687b ldr r3, [r7, #4] 80107ec: 6a1b ldr r3, [r3, #32] 80107ee: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80107f0: 687b ldr r3, [r7, #4] 80107f2: 6a1b ldr r3, [r3, #32] 80107f4: f023 0201 bic.w r2, r3, #1 80107f8: 687b ldr r3, [r7, #4] 80107fa: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80107fc: 687b ldr r3, [r7, #4] 80107fe: 685b ldr r3, [r3, #4] 8010800: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8010802: 687b ldr r3, [r7, #4] 8010804: 699b ldr r3, [r3, #24] 8010806: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8010808: 68fa ldr r2, [r7, #12] 801080a: 4b37 ldr r3, [pc, #220] @ (80108e8 ) 801080c: 4013 ands r3, r2 801080e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8010810: 68fb ldr r3, [r7, #12] 8010812: f023 0303 bic.w r3, r3, #3 8010816: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010818: 683b ldr r3, [r7, #0] 801081a: 681b ldr r3, [r3, #0] 801081c: 68fa ldr r2, [r7, #12] 801081e: 4313 orrs r3, r2 8010820: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8010822: 697b ldr r3, [r7, #20] 8010824: f023 0302 bic.w r3, r3, #2 8010828: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 801082a: 683b ldr r3, [r7, #0] 801082c: 689b ldr r3, [r3, #8] 801082e: 697a ldr r2, [r7, #20] 8010830: 4313 orrs r3, r2 8010832: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8010834: 687b ldr r3, [r7, #4] 8010836: 4a2d ldr r2, [pc, #180] @ (80108ec ) 8010838: 4293 cmp r3, r2 801083a: d00f beq.n 801085c 801083c: 687b ldr r3, [r7, #4] 801083e: 4a2c ldr r2, [pc, #176] @ (80108f0 ) 8010840: 4293 cmp r3, r2 8010842: d00b beq.n 801085c 8010844: 687b ldr r3, [r7, #4] 8010846: 4a2b ldr r2, [pc, #172] @ (80108f4 ) 8010848: 4293 cmp r3, r2 801084a: d007 beq.n 801085c 801084c: 687b ldr r3, [r7, #4] 801084e: 4a2a ldr r2, [pc, #168] @ (80108f8 ) 8010850: 4293 cmp r3, r2 8010852: d003 beq.n 801085c 8010854: 687b ldr r3, [r7, #4] 8010856: 4a29 ldr r2, [pc, #164] @ (80108fc ) 8010858: 4293 cmp r3, r2 801085a: d10c bne.n 8010876 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 801085c: 697b ldr r3, [r7, #20] 801085e: f023 0308 bic.w r3, r3, #8 8010862: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8010864: 683b ldr r3, [r7, #0] 8010866: 68db ldr r3, [r3, #12] 8010868: 697a ldr r2, [r7, #20] 801086a: 4313 orrs r3, r2 801086c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 801086e: 697b ldr r3, [r7, #20] 8010870: f023 0304 bic.w r3, r3, #4 8010874: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010876: 687b ldr r3, [r7, #4] 8010878: 4a1c ldr r2, [pc, #112] @ (80108ec ) 801087a: 4293 cmp r3, r2 801087c: d00f beq.n 801089e 801087e: 687b ldr r3, [r7, #4] 8010880: 4a1b ldr r2, [pc, #108] @ (80108f0 ) 8010882: 4293 cmp r3, r2 8010884: d00b beq.n 801089e 8010886: 687b ldr r3, [r7, #4] 8010888: 4a1a ldr r2, [pc, #104] @ (80108f4 ) 801088a: 4293 cmp r3, r2 801088c: d007 beq.n 801089e 801088e: 687b ldr r3, [r7, #4] 8010890: 4a19 ldr r2, [pc, #100] @ (80108f8 ) 8010892: 4293 cmp r3, r2 8010894: d003 beq.n 801089e 8010896: 687b ldr r3, [r7, #4] 8010898: 4a18 ldr r2, [pc, #96] @ (80108fc ) 801089a: 4293 cmp r3, r2 801089c: d111 bne.n 80108c2 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 801089e: 693b ldr r3, [r7, #16] 80108a0: f423 7380 bic.w r3, r3, #256 @ 0x100 80108a4: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80108a6: 693b ldr r3, [r7, #16] 80108a8: f423 7300 bic.w r3, r3, #512 @ 0x200 80108ac: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 80108ae: 683b ldr r3, [r7, #0] 80108b0: 695b ldr r3, [r3, #20] 80108b2: 693a ldr r2, [r7, #16] 80108b4: 4313 orrs r3, r2 80108b6: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 80108b8: 683b ldr r3, [r7, #0] 80108ba: 699b ldr r3, [r3, #24] 80108bc: 693a ldr r2, [r7, #16] 80108be: 4313 orrs r3, r2 80108c0: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80108c2: 687b ldr r3, [r7, #4] 80108c4: 693a ldr r2, [r7, #16] 80108c6: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80108c8: 687b ldr r3, [r7, #4] 80108ca: 68fa ldr r2, [r7, #12] 80108cc: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80108ce: 683b ldr r3, [r7, #0] 80108d0: 685a ldr r2, [r3, #4] 80108d2: 687b ldr r3, [r7, #4] 80108d4: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80108d6: 687b ldr r3, [r7, #4] 80108d8: 697a ldr r2, [r7, #20] 80108da: 621a str r2, [r3, #32] } 80108dc: bf00 nop 80108de: 371c adds r7, #28 80108e0: 46bd mov sp, r7 80108e2: f85d 7b04 ldr.w r7, [sp], #4 80108e6: 4770 bx lr 80108e8: fffeff8f .word 0xfffeff8f 80108ec: 40010000 .word 0x40010000 80108f0: 40010400 .word 0x40010400 80108f4: 40014000 .word 0x40014000 80108f8: 40014400 .word 0x40014400 80108fc: 40014800 .word 0x40014800 08010900 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010900: b480 push {r7} 8010902: b087 sub sp, #28 8010904: af00 add r7, sp, #0 8010906: 6078 str r0, [r7, #4] 8010908: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 801090a: 687b ldr r3, [r7, #4] 801090c: 6a1b ldr r3, [r3, #32] 801090e: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8010910: 687b ldr r3, [r7, #4] 8010912: 6a1b ldr r3, [r3, #32] 8010914: f023 0210 bic.w r2, r3, #16 8010918: 687b ldr r3, [r7, #4] 801091a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 801091c: 687b ldr r3, [r7, #4] 801091e: 685b ldr r3, [r3, #4] 8010920: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8010922: 687b ldr r3, [r7, #4] 8010924: 699b ldr r3, [r3, #24] 8010926: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8010928: 68fa ldr r2, [r7, #12] 801092a: 4b34 ldr r3, [pc, #208] @ (80109fc ) 801092c: 4013 ands r3, r2 801092e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8010930: 68fb ldr r3, [r7, #12] 8010932: f423 7340 bic.w r3, r3, #768 @ 0x300 8010936: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010938: 683b ldr r3, [r7, #0] 801093a: 681b ldr r3, [r3, #0] 801093c: 021b lsls r3, r3, #8 801093e: 68fa ldr r2, [r7, #12] 8010940: 4313 orrs r3, r2 8010942: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8010944: 697b ldr r3, [r7, #20] 8010946: f023 0320 bic.w r3, r3, #32 801094a: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 801094c: 683b ldr r3, [r7, #0] 801094e: 689b ldr r3, [r3, #8] 8010950: 011b lsls r3, r3, #4 8010952: 697a ldr r2, [r7, #20] 8010954: 4313 orrs r3, r2 8010956: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8010958: 687b ldr r3, [r7, #4] 801095a: 4a29 ldr r2, [pc, #164] @ (8010a00 ) 801095c: 4293 cmp r3, r2 801095e: d003 beq.n 8010968 8010960: 687b ldr r3, [r7, #4] 8010962: 4a28 ldr r2, [pc, #160] @ (8010a04 ) 8010964: 4293 cmp r3, r2 8010966: d10d bne.n 8010984 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8010968: 697b ldr r3, [r7, #20] 801096a: f023 0380 bic.w r3, r3, #128 @ 0x80 801096e: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8010970: 683b ldr r3, [r7, #0] 8010972: 68db ldr r3, [r3, #12] 8010974: 011b lsls r3, r3, #4 8010976: 697a ldr r2, [r7, #20] 8010978: 4313 orrs r3, r2 801097a: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 801097c: 697b ldr r3, [r7, #20] 801097e: f023 0340 bic.w r3, r3, #64 @ 0x40 8010982: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010984: 687b ldr r3, [r7, #4] 8010986: 4a1e ldr r2, [pc, #120] @ (8010a00 ) 8010988: 4293 cmp r3, r2 801098a: d00f beq.n 80109ac 801098c: 687b ldr r3, [r7, #4] 801098e: 4a1d ldr r2, [pc, #116] @ (8010a04 ) 8010990: 4293 cmp r3, r2 8010992: d00b beq.n 80109ac 8010994: 687b ldr r3, [r7, #4] 8010996: 4a1c ldr r2, [pc, #112] @ (8010a08 ) 8010998: 4293 cmp r3, r2 801099a: d007 beq.n 80109ac 801099c: 687b ldr r3, [r7, #4] 801099e: 4a1b ldr r2, [pc, #108] @ (8010a0c ) 80109a0: 4293 cmp r3, r2 80109a2: d003 beq.n 80109ac 80109a4: 687b ldr r3, [r7, #4] 80109a6: 4a1a ldr r2, [pc, #104] @ (8010a10 ) 80109a8: 4293 cmp r3, r2 80109aa: d113 bne.n 80109d4 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 80109ac: 693b ldr r3, [r7, #16] 80109ae: f423 6380 bic.w r3, r3, #1024 @ 0x400 80109b2: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 80109b4: 693b ldr r3, [r7, #16] 80109b6: f423 6300 bic.w r3, r3, #2048 @ 0x800 80109ba: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 80109bc: 683b ldr r3, [r7, #0] 80109be: 695b ldr r3, [r3, #20] 80109c0: 009b lsls r3, r3, #2 80109c2: 693a ldr r2, [r7, #16] 80109c4: 4313 orrs r3, r2 80109c6: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 80109c8: 683b ldr r3, [r7, #0] 80109ca: 699b ldr r3, [r3, #24] 80109cc: 009b lsls r3, r3, #2 80109ce: 693a ldr r2, [r7, #16] 80109d0: 4313 orrs r3, r2 80109d2: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80109d4: 687b ldr r3, [r7, #4] 80109d6: 693a ldr r2, [r7, #16] 80109d8: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80109da: 687b ldr r3, [r7, #4] 80109dc: 68fa ldr r2, [r7, #12] 80109de: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 80109e0: 683b ldr r3, [r7, #0] 80109e2: 685a ldr r2, [r3, #4] 80109e4: 687b ldr r3, [r7, #4] 80109e6: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80109e8: 687b ldr r3, [r7, #4] 80109ea: 697a ldr r2, [r7, #20] 80109ec: 621a str r2, [r3, #32] } 80109ee: bf00 nop 80109f0: 371c adds r7, #28 80109f2: 46bd mov sp, r7 80109f4: f85d 7b04 ldr.w r7, [sp], #4 80109f8: 4770 bx lr 80109fa: bf00 nop 80109fc: feff8fff .word 0xfeff8fff 8010a00: 40010000 .word 0x40010000 8010a04: 40010400 .word 0x40010400 8010a08: 40014000 .word 0x40014000 8010a0c: 40014400 .word 0x40014400 8010a10: 40014800 .word 0x40014800 08010a14 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010a14: b480 push {r7} 8010a16: b087 sub sp, #28 8010a18: af00 add r7, sp, #0 8010a1a: 6078 str r0, [r7, #4] 8010a1c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010a1e: 687b ldr r3, [r7, #4] 8010a20: 6a1b ldr r3, [r3, #32] 8010a22: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8010a24: 687b ldr r3, [r7, #4] 8010a26: 6a1b ldr r3, [r3, #32] 8010a28: f423 7280 bic.w r2, r3, #256 @ 0x100 8010a2c: 687b ldr r3, [r7, #4] 8010a2e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010a30: 687b ldr r3, [r7, #4] 8010a32: 685b ldr r3, [r3, #4] 8010a34: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8010a36: 687b ldr r3, [r7, #4] 8010a38: 69db ldr r3, [r3, #28] 8010a3a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8010a3c: 68fa ldr r2, [r7, #12] 8010a3e: 4b33 ldr r3, [pc, #204] @ (8010b0c ) 8010a40: 4013 ands r3, r2 8010a42: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8010a44: 68fb ldr r3, [r7, #12] 8010a46: f023 0303 bic.w r3, r3, #3 8010a4a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010a4c: 683b ldr r3, [r7, #0] 8010a4e: 681b ldr r3, [r3, #0] 8010a50: 68fa ldr r2, [r7, #12] 8010a52: 4313 orrs r3, r2 8010a54: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8010a56: 697b ldr r3, [r7, #20] 8010a58: f423 7300 bic.w r3, r3, #512 @ 0x200 8010a5c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8010a5e: 683b ldr r3, [r7, #0] 8010a60: 689b ldr r3, [r3, #8] 8010a62: 021b lsls r3, r3, #8 8010a64: 697a ldr r2, [r7, #20] 8010a66: 4313 orrs r3, r2 8010a68: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8010a6a: 687b ldr r3, [r7, #4] 8010a6c: 4a28 ldr r2, [pc, #160] @ (8010b10 ) 8010a6e: 4293 cmp r3, r2 8010a70: d003 beq.n 8010a7a 8010a72: 687b ldr r3, [r7, #4] 8010a74: 4a27 ldr r2, [pc, #156] @ (8010b14 ) 8010a76: 4293 cmp r3, r2 8010a78: d10d bne.n 8010a96 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8010a7a: 697b ldr r3, [r7, #20] 8010a7c: f423 6300 bic.w r3, r3, #2048 @ 0x800 8010a80: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8010a82: 683b ldr r3, [r7, #0] 8010a84: 68db ldr r3, [r3, #12] 8010a86: 021b lsls r3, r3, #8 8010a88: 697a ldr r2, [r7, #20] 8010a8a: 4313 orrs r3, r2 8010a8c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8010a8e: 697b ldr r3, [r7, #20] 8010a90: f423 6380 bic.w r3, r3, #1024 @ 0x400 8010a94: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010a96: 687b ldr r3, [r7, #4] 8010a98: 4a1d ldr r2, [pc, #116] @ (8010b10 ) 8010a9a: 4293 cmp r3, r2 8010a9c: d00f beq.n 8010abe 8010a9e: 687b ldr r3, [r7, #4] 8010aa0: 4a1c ldr r2, [pc, #112] @ (8010b14 ) 8010aa2: 4293 cmp r3, r2 8010aa4: d00b beq.n 8010abe 8010aa6: 687b ldr r3, [r7, #4] 8010aa8: 4a1b ldr r2, [pc, #108] @ (8010b18 ) 8010aaa: 4293 cmp r3, r2 8010aac: d007 beq.n 8010abe 8010aae: 687b ldr r3, [r7, #4] 8010ab0: 4a1a ldr r2, [pc, #104] @ (8010b1c ) 8010ab2: 4293 cmp r3, r2 8010ab4: d003 beq.n 8010abe 8010ab6: 687b ldr r3, [r7, #4] 8010ab8: 4a19 ldr r2, [pc, #100] @ (8010b20 ) 8010aba: 4293 cmp r3, r2 8010abc: d113 bne.n 8010ae6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8010abe: 693b ldr r3, [r7, #16] 8010ac0: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8010ac4: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8010ac6: 693b ldr r3, [r7, #16] 8010ac8: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010acc: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8010ace: 683b ldr r3, [r7, #0] 8010ad0: 695b ldr r3, [r3, #20] 8010ad2: 011b lsls r3, r3, #4 8010ad4: 693a ldr r2, [r7, #16] 8010ad6: 4313 orrs r3, r2 8010ad8: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8010ada: 683b ldr r3, [r7, #0] 8010adc: 699b ldr r3, [r3, #24] 8010ade: 011b lsls r3, r3, #4 8010ae0: 693a ldr r2, [r7, #16] 8010ae2: 4313 orrs r3, r2 8010ae4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010ae6: 687b ldr r3, [r7, #4] 8010ae8: 693a ldr r2, [r7, #16] 8010aea: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010aec: 687b ldr r3, [r7, #4] 8010aee: 68fa ldr r2, [r7, #12] 8010af0: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8010af2: 683b ldr r3, [r7, #0] 8010af4: 685a ldr r2, [r3, #4] 8010af6: 687b ldr r3, [r7, #4] 8010af8: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010afa: 687b ldr r3, [r7, #4] 8010afc: 697a ldr r2, [r7, #20] 8010afe: 621a str r2, [r3, #32] } 8010b00: bf00 nop 8010b02: 371c adds r7, #28 8010b04: 46bd mov sp, r7 8010b06: f85d 7b04 ldr.w r7, [sp], #4 8010b0a: 4770 bx lr 8010b0c: fffeff8f .word 0xfffeff8f 8010b10: 40010000 .word 0x40010000 8010b14: 40010400 .word 0x40010400 8010b18: 40014000 .word 0x40014000 8010b1c: 40014400 .word 0x40014400 8010b20: 40014800 .word 0x40014800 08010b24 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010b24: b480 push {r7} 8010b26: b087 sub sp, #28 8010b28: af00 add r7, sp, #0 8010b2a: 6078 str r0, [r7, #4] 8010b2c: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010b2e: 687b ldr r3, [r7, #4] 8010b30: 6a1b ldr r3, [r3, #32] 8010b32: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8010b34: 687b ldr r3, [r7, #4] 8010b36: 6a1b ldr r3, [r3, #32] 8010b38: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8010b3c: 687b ldr r3, [r7, #4] 8010b3e: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010b40: 687b ldr r3, [r7, #4] 8010b42: 685b ldr r3, [r3, #4] 8010b44: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8010b46: 687b ldr r3, [r7, #4] 8010b48: 69db ldr r3, [r3, #28] 8010b4a: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8010b4c: 68fa ldr r2, [r7, #12] 8010b4e: 4b24 ldr r3, [pc, #144] @ (8010be0 ) 8010b50: 4013 ands r3, r2 8010b52: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8010b54: 68fb ldr r3, [r7, #12] 8010b56: f423 7340 bic.w r3, r3, #768 @ 0x300 8010b5a: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010b5c: 683b ldr r3, [r7, #0] 8010b5e: 681b ldr r3, [r3, #0] 8010b60: 021b lsls r3, r3, #8 8010b62: 68fa ldr r2, [r7, #12] 8010b64: 4313 orrs r3, r2 8010b66: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8010b68: 693b ldr r3, [r7, #16] 8010b6a: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010b6e: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8010b70: 683b ldr r3, [r7, #0] 8010b72: 689b ldr r3, [r3, #8] 8010b74: 031b lsls r3, r3, #12 8010b76: 693a ldr r2, [r7, #16] 8010b78: 4313 orrs r3, r2 8010b7a: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010b7c: 687b ldr r3, [r7, #4] 8010b7e: 4a19 ldr r2, [pc, #100] @ (8010be4 ) 8010b80: 4293 cmp r3, r2 8010b82: d00f beq.n 8010ba4 8010b84: 687b ldr r3, [r7, #4] 8010b86: 4a18 ldr r2, [pc, #96] @ (8010be8 ) 8010b88: 4293 cmp r3, r2 8010b8a: d00b beq.n 8010ba4 8010b8c: 687b ldr r3, [r7, #4] 8010b8e: 4a17 ldr r2, [pc, #92] @ (8010bec ) 8010b90: 4293 cmp r3, r2 8010b92: d007 beq.n 8010ba4 8010b94: 687b ldr r3, [r7, #4] 8010b96: 4a16 ldr r2, [pc, #88] @ (8010bf0 ) 8010b98: 4293 cmp r3, r2 8010b9a: d003 beq.n 8010ba4 8010b9c: 687b ldr r3, [r7, #4] 8010b9e: 4a15 ldr r2, [pc, #84] @ (8010bf4 ) 8010ba0: 4293 cmp r3, r2 8010ba2: d109 bne.n 8010bb8 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8010ba4: 697b ldr r3, [r7, #20] 8010ba6: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010baa: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8010bac: 683b ldr r3, [r7, #0] 8010bae: 695b ldr r3, [r3, #20] 8010bb0: 019b lsls r3, r3, #6 8010bb2: 697a ldr r2, [r7, #20] 8010bb4: 4313 orrs r3, r2 8010bb6: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010bb8: 687b ldr r3, [r7, #4] 8010bba: 697a ldr r2, [r7, #20] 8010bbc: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010bbe: 687b ldr r3, [r7, #4] 8010bc0: 68fa ldr r2, [r7, #12] 8010bc2: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8010bc4: 683b ldr r3, [r7, #0] 8010bc6: 685a ldr r2, [r3, #4] 8010bc8: 687b ldr r3, [r7, #4] 8010bca: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010bcc: 687b ldr r3, [r7, #4] 8010bce: 693a ldr r2, [r7, #16] 8010bd0: 621a str r2, [r3, #32] } 8010bd2: bf00 nop 8010bd4: 371c adds r7, #28 8010bd6: 46bd mov sp, r7 8010bd8: f85d 7b04 ldr.w r7, [sp], #4 8010bdc: 4770 bx lr 8010bde: bf00 nop 8010be0: feff8fff .word 0xfeff8fff 8010be4: 40010000 .word 0x40010000 8010be8: 40010400 .word 0x40010400 8010bec: 40014000 .word 0x40014000 8010bf0: 40014400 .word 0x40014400 8010bf4: 40014800 .word 0x40014800 08010bf8 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010bf8: b480 push {r7} 8010bfa: b087 sub sp, #28 8010bfc: af00 add r7, sp, #0 8010bfe: 6078 str r0, [r7, #4] 8010c00: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010c02: 687b ldr r3, [r7, #4] 8010c04: 6a1b ldr r3, [r3, #32] 8010c06: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 8010c08: 687b ldr r3, [r7, #4] 8010c0a: 6a1b ldr r3, [r3, #32] 8010c0c: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8010c10: 687b ldr r3, [r7, #4] 8010c12: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010c14: 687b ldr r3, [r7, #4] 8010c16: 685b ldr r3, [r3, #4] 8010c18: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010c1a: 687b ldr r3, [r7, #4] 8010c1c: 6d5b ldr r3, [r3, #84] @ 0x54 8010c1e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8010c20: 68fa ldr r2, [r7, #12] 8010c22: 4b21 ldr r3, [pc, #132] @ (8010ca8 ) 8010c24: 4013 ands r3, r2 8010c26: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010c28: 683b ldr r3, [r7, #0] 8010c2a: 681b ldr r3, [r3, #0] 8010c2c: 68fa ldr r2, [r7, #12] 8010c2e: 4313 orrs r3, r2 8010c30: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 8010c32: 693b ldr r3, [r7, #16] 8010c34: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8010c38: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 8010c3a: 683b ldr r3, [r7, #0] 8010c3c: 689b ldr r3, [r3, #8] 8010c3e: 041b lsls r3, r3, #16 8010c40: 693a ldr r2, [r7, #16] 8010c42: 4313 orrs r3, r2 8010c44: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010c46: 687b ldr r3, [r7, #4] 8010c48: 4a18 ldr r2, [pc, #96] @ (8010cac ) 8010c4a: 4293 cmp r3, r2 8010c4c: d00f beq.n 8010c6e 8010c4e: 687b ldr r3, [r7, #4] 8010c50: 4a17 ldr r2, [pc, #92] @ (8010cb0 ) 8010c52: 4293 cmp r3, r2 8010c54: d00b beq.n 8010c6e 8010c56: 687b ldr r3, [r7, #4] 8010c58: 4a16 ldr r2, [pc, #88] @ (8010cb4 ) 8010c5a: 4293 cmp r3, r2 8010c5c: d007 beq.n 8010c6e 8010c5e: 687b ldr r3, [r7, #4] 8010c60: 4a15 ldr r2, [pc, #84] @ (8010cb8 ) 8010c62: 4293 cmp r3, r2 8010c64: d003 beq.n 8010c6e 8010c66: 687b ldr r3, [r7, #4] 8010c68: 4a14 ldr r2, [pc, #80] @ (8010cbc ) 8010c6a: 4293 cmp r3, r2 8010c6c: d109 bne.n 8010c82 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 8010c6e: 697b ldr r3, [r7, #20] 8010c70: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010c74: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 8010c76: 683b ldr r3, [r7, #0] 8010c78: 695b ldr r3, [r3, #20] 8010c7a: 021b lsls r3, r3, #8 8010c7c: 697a ldr r2, [r7, #20] 8010c7e: 4313 orrs r3, r2 8010c80: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010c82: 687b ldr r3, [r7, #4] 8010c84: 697a ldr r2, [r7, #20] 8010c86: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010c88: 687b ldr r3, [r7, #4] 8010c8a: 68fa ldr r2, [r7, #12] 8010c8c: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 8010c8e: 683b ldr r3, [r7, #0] 8010c90: 685a ldr r2, [r3, #4] 8010c92: 687b ldr r3, [r7, #4] 8010c94: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010c96: 687b ldr r3, [r7, #4] 8010c98: 693a ldr r2, [r7, #16] 8010c9a: 621a str r2, [r3, #32] } 8010c9c: bf00 nop 8010c9e: 371c adds r7, #28 8010ca0: 46bd mov sp, r7 8010ca2: f85d 7b04 ldr.w r7, [sp], #4 8010ca6: 4770 bx lr 8010ca8: fffeff8f .word 0xfffeff8f 8010cac: 40010000 .word 0x40010000 8010cb0: 40010400 .word 0x40010400 8010cb4: 40014000 .word 0x40014000 8010cb8: 40014400 .word 0x40014400 8010cbc: 40014800 .word 0x40014800 08010cc0 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010cc0: b480 push {r7} 8010cc2: b087 sub sp, #28 8010cc4: af00 add r7, sp, #0 8010cc6: 6078 str r0, [r7, #4] 8010cc8: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010cca: 687b ldr r3, [r7, #4] 8010ccc: 6a1b ldr r3, [r3, #32] 8010cce: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8010cd0: 687b ldr r3, [r7, #4] 8010cd2: 6a1b ldr r3, [r3, #32] 8010cd4: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8010cd8: 687b ldr r3, [r7, #4] 8010cda: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010cdc: 687b ldr r3, [r7, #4] 8010cde: 685b ldr r3, [r3, #4] 8010ce0: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010ce2: 687b ldr r3, [r7, #4] 8010ce4: 6d5b ldr r3, [r3, #84] @ 0x54 8010ce6: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 8010ce8: 68fa ldr r2, [r7, #12] 8010cea: 4b22 ldr r3, [pc, #136] @ (8010d74 ) 8010cec: 4013 ands r3, r2 8010cee: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010cf0: 683b ldr r3, [r7, #0] 8010cf2: 681b ldr r3, [r3, #0] 8010cf4: 021b lsls r3, r3, #8 8010cf6: 68fa ldr r2, [r7, #12] 8010cf8: 4313 orrs r3, r2 8010cfa: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8010cfc: 693b ldr r3, [r7, #16] 8010cfe: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8010d02: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 8010d04: 683b ldr r3, [r7, #0] 8010d06: 689b ldr r3, [r3, #8] 8010d08: 051b lsls r3, r3, #20 8010d0a: 693a ldr r2, [r7, #16] 8010d0c: 4313 orrs r3, r2 8010d0e: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010d10: 687b ldr r3, [r7, #4] 8010d12: 4a19 ldr r2, [pc, #100] @ (8010d78 ) 8010d14: 4293 cmp r3, r2 8010d16: d00f beq.n 8010d38 8010d18: 687b ldr r3, [r7, #4] 8010d1a: 4a18 ldr r2, [pc, #96] @ (8010d7c ) 8010d1c: 4293 cmp r3, r2 8010d1e: d00b beq.n 8010d38 8010d20: 687b ldr r3, [r7, #4] 8010d22: 4a17 ldr r2, [pc, #92] @ (8010d80 ) 8010d24: 4293 cmp r3, r2 8010d26: d007 beq.n 8010d38 8010d28: 687b ldr r3, [r7, #4] 8010d2a: 4a16 ldr r2, [pc, #88] @ (8010d84 ) 8010d2c: 4293 cmp r3, r2 8010d2e: d003 beq.n 8010d38 8010d30: 687b ldr r3, [r7, #4] 8010d32: 4a15 ldr r2, [pc, #84] @ (8010d88 ) 8010d34: 4293 cmp r3, r2 8010d36: d109 bne.n 8010d4c { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 8010d38: 697b ldr r3, [r7, #20] 8010d3a: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010d3e: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8010d40: 683b ldr r3, [r7, #0] 8010d42: 695b ldr r3, [r3, #20] 8010d44: 029b lsls r3, r3, #10 8010d46: 697a ldr r2, [r7, #20] 8010d48: 4313 orrs r3, r2 8010d4a: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010d4c: 687b ldr r3, [r7, #4] 8010d4e: 697a ldr r2, [r7, #20] 8010d50: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010d52: 687b ldr r3, [r7, #4] 8010d54: 68fa ldr r2, [r7, #12] 8010d56: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8010d58: 683b ldr r3, [r7, #0] 8010d5a: 685a ldr r2, [r3, #4] 8010d5c: 687b ldr r3, [r7, #4] 8010d5e: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010d60: 687b ldr r3, [r7, #4] 8010d62: 693a ldr r2, [r7, #16] 8010d64: 621a str r2, [r3, #32] } 8010d66: bf00 nop 8010d68: 371c adds r7, #28 8010d6a: 46bd mov sp, r7 8010d6c: f85d 7b04 ldr.w r7, [sp], #4 8010d70: 4770 bx lr 8010d72: bf00 nop 8010d74: feff8fff .word 0xfeff8fff 8010d78: 40010000 .word 0x40010000 8010d7c: 40010400 .word 0x40010400 8010d80: 40014000 .word 0x40014000 8010d84: 40014400 .word 0x40014400 8010d88: 40014800 .word 0x40014800 08010d8c : * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010d8c: b480 push {r7} 8010d8e: b087 sub sp, #28 8010d90: af00 add r7, sp, #0 8010d92: 60f8 str r0, [r7, #12] 8010d94: 60b9 str r1, [r7, #8] 8010d96: 607a str r2, [r7, #4] 8010d98: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010d9a: 68fb ldr r3, [r7, #12] 8010d9c: 6a1b ldr r3, [r3, #32] 8010d9e: 613b str r3, [r7, #16] TIMx->CCER &= ~TIM_CCER_CC1E; 8010da0: 68fb ldr r3, [r7, #12] 8010da2: 6a1b ldr r3, [r3, #32] 8010da4: f023 0201 bic.w r2, r3, #1 8010da8: 68fb ldr r3, [r7, #12] 8010daa: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010dac: 68fb ldr r3, [r7, #12] 8010dae: 699b ldr r3, [r3, #24] 8010db0: 617b str r3, [r7, #20] /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) 8010db2: 68fb ldr r3, [r7, #12] 8010db4: 4a28 ldr r2, [pc, #160] @ (8010e58 ) 8010db6: 4293 cmp r3, r2 8010db8: d01b beq.n 8010df2 8010dba: 68fb ldr r3, [r7, #12] 8010dbc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010dc0: d017 beq.n 8010df2 8010dc2: 68fb ldr r3, [r7, #12] 8010dc4: 4a25 ldr r2, [pc, #148] @ (8010e5c ) 8010dc6: 4293 cmp r3, r2 8010dc8: d013 beq.n 8010df2 8010dca: 68fb ldr r3, [r7, #12] 8010dcc: 4a24 ldr r2, [pc, #144] @ (8010e60 ) 8010dce: 4293 cmp r3, r2 8010dd0: d00f beq.n 8010df2 8010dd2: 68fb ldr r3, [r7, #12] 8010dd4: 4a23 ldr r2, [pc, #140] @ (8010e64 ) 8010dd6: 4293 cmp r3, r2 8010dd8: d00b beq.n 8010df2 8010dda: 68fb ldr r3, [r7, #12] 8010ddc: 4a22 ldr r2, [pc, #136] @ (8010e68 ) 8010dde: 4293 cmp r3, r2 8010de0: d007 beq.n 8010df2 8010de2: 68fb ldr r3, [r7, #12] 8010de4: 4a21 ldr r2, [pc, #132] @ (8010e6c ) 8010de6: 4293 cmp r3, r2 8010de8: d003 beq.n 8010df2 8010dea: 68fb ldr r3, [r7, #12] 8010dec: 4a20 ldr r2, [pc, #128] @ (8010e70 ) 8010dee: 4293 cmp r3, r2 8010df0: d101 bne.n 8010df6 8010df2: 2301 movs r3, #1 8010df4: e000 b.n 8010df8 8010df6: 2300 movs r3, #0 8010df8: 2b00 cmp r3, #0 8010dfa: d008 beq.n 8010e0e { tmpccmr1 &= ~TIM_CCMR1_CC1S; 8010dfc: 697b ldr r3, [r7, #20] 8010dfe: f023 0303 bic.w r3, r3, #3 8010e02: 617b str r3, [r7, #20] tmpccmr1 |= TIM_ICSelection; 8010e04: 697a ldr r2, [r7, #20] 8010e06: 687b ldr r3, [r7, #4] 8010e08: 4313 orrs r3, r2 8010e0a: 617b str r3, [r7, #20] 8010e0c: e003 b.n 8010e16 } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; 8010e0e: 697b ldr r3, [r7, #20] 8010e10: f043 0301 orr.w r3, r3, #1 8010e14: 617b str r3, [r7, #20] } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010e16: 697b ldr r3, [r7, #20] 8010e18: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010e1c: 617b str r3, [r7, #20] tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); 8010e1e: 683b ldr r3, [r7, #0] 8010e20: 011b lsls r3, r3, #4 8010e22: b2db uxtb r3, r3 8010e24: 697a ldr r2, [r7, #20] 8010e26: 4313 orrs r3, r2 8010e28: 617b str r3, [r7, #20] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010e2a: 693b ldr r3, [r7, #16] 8010e2c: f023 030a bic.w r3, r3, #10 8010e30: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 8010e32: 68bb ldr r3, [r7, #8] 8010e34: f003 030a and.w r3, r3, #10 8010e38: 693a ldr r2, [r7, #16] 8010e3a: 4313 orrs r3, r2 8010e3c: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010e3e: 68fb ldr r3, [r7, #12] 8010e40: 697a ldr r2, [r7, #20] 8010e42: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010e44: 68fb ldr r3, [r7, #12] 8010e46: 693a ldr r2, [r7, #16] 8010e48: 621a str r2, [r3, #32] } 8010e4a: bf00 nop 8010e4c: 371c adds r7, #28 8010e4e: 46bd mov sp, r7 8010e50: f85d 7b04 ldr.w r7, [sp], #4 8010e54: 4770 bx lr 8010e56: bf00 nop 8010e58: 40010000 .word 0x40010000 8010e5c: 40000400 .word 0x40000400 8010e60: 40000800 .word 0x40000800 8010e64: 40000c00 .word 0x40000c00 8010e68: 40010400 .word 0x40010400 8010e6c: 40001800 .word 0x40001800 8010e70: 40014000 .word 0x40014000 08010e74 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010e74: b480 push {r7} 8010e76: b087 sub sp, #28 8010e78: af00 add r7, sp, #0 8010e7a: 60f8 str r0, [r7, #12] 8010e7c: 60b9 str r1, [r7, #8] 8010e7e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010e80: 68fb ldr r3, [r7, #12] 8010e82: 6a1b ldr r3, [r3, #32] 8010e84: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8010e86: 68fb ldr r3, [r7, #12] 8010e88: 6a1b ldr r3, [r3, #32] 8010e8a: f023 0201 bic.w r2, r3, #1 8010e8e: 68fb ldr r3, [r7, #12] 8010e90: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010e92: 68fb ldr r3, [r7, #12] 8010e94: 699b ldr r3, [r3, #24] 8010e96: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010e98: 693b ldr r3, [r7, #16] 8010e9a: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010e9e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8010ea0: 687b ldr r3, [r7, #4] 8010ea2: 011b lsls r3, r3, #4 8010ea4: 693a ldr r2, [r7, #16] 8010ea6: 4313 orrs r3, r2 8010ea8: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010eaa: 697b ldr r3, [r7, #20] 8010eac: f023 030a bic.w r3, r3, #10 8010eb0: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8010eb2: 697a ldr r2, [r7, #20] 8010eb4: 68bb ldr r3, [r7, #8] 8010eb6: 4313 orrs r3, r2 8010eb8: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010eba: 68fb ldr r3, [r7, #12] 8010ebc: 693a ldr r2, [r7, #16] 8010ebe: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010ec0: 68fb ldr r3, [r7, #12] 8010ec2: 697a ldr r2, [r7, #20] 8010ec4: 621a str r2, [r3, #32] } 8010ec6: bf00 nop 8010ec8: 371c adds r7, #28 8010eca: 46bd mov sp, r7 8010ecc: f85d 7b04 ldr.w r7, [sp], #4 8010ed0: 4770 bx lr 08010ed2 : * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010ed2: b480 push {r7} 8010ed4: b087 sub sp, #28 8010ed6: af00 add r7, sp, #0 8010ed8: 60f8 str r0, [r7, #12] 8010eda: 60b9 str r1, [r7, #8] 8010edc: 607a str r2, [r7, #4] 8010ede: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8010ee0: 68fb ldr r3, [r7, #12] 8010ee2: 6a1b ldr r3, [r3, #32] 8010ee4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010ee6: 68fb ldr r3, [r7, #12] 8010ee8: 6a1b ldr r3, [r3, #32] 8010eea: f023 0210 bic.w r2, r3, #16 8010eee: 68fb ldr r3, [r7, #12] 8010ef0: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010ef2: 68fb ldr r3, [r7, #12] 8010ef4: 699b ldr r3, [r3, #24] 8010ef6: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; 8010ef8: 693b ldr r3, [r7, #16] 8010efa: f423 7340 bic.w r3, r3, #768 @ 0x300 8010efe: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICSelection << 8U); 8010f00: 687b ldr r3, [r7, #4] 8010f02: 021b lsls r3, r3, #8 8010f04: 693a ldr r2, [r7, #16] 8010f06: 4313 orrs r3, r2 8010f08: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010f0a: 693b ldr r3, [r7, #16] 8010f0c: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010f10: 613b str r3, [r7, #16] tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); 8010f12: 683b ldr r3, [r7, #0] 8010f14: 031b lsls r3, r3, #12 8010f16: b29b uxth r3, r3 8010f18: 693a ldr r2, [r7, #16] 8010f1a: 4313 orrs r3, r2 8010f1c: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010f1e: 697b ldr r3, [r7, #20] 8010f20: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8010f24: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 8010f26: 68bb ldr r3, [r7, #8] 8010f28: 011b lsls r3, r3, #4 8010f2a: f003 03a0 and.w r3, r3, #160 @ 0xa0 8010f2e: 697a ldr r2, [r7, #20] 8010f30: 4313 orrs r3, r2 8010f32: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010f34: 68fb ldr r3, [r7, #12] 8010f36: 693a ldr r2, [r7, #16] 8010f38: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010f3a: 68fb ldr r3, [r7, #12] 8010f3c: 697a ldr r2, [r7, #20] 8010f3e: 621a str r2, [r3, #32] } 8010f40: bf00 nop 8010f42: 371c adds r7, #28 8010f44: 46bd mov sp, r7 8010f46: f85d 7b04 ldr.w r7, [sp], #4 8010f4a: 4770 bx lr 08010f4c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010f4c: b480 push {r7} 8010f4e: b087 sub sp, #28 8010f50: af00 add r7, sp, #0 8010f52: 60f8 str r0, [r7, #12] 8010f54: 60b9 str r1, [r7, #8] 8010f56: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8010f58: 68fb ldr r3, [r7, #12] 8010f5a: 6a1b ldr r3, [r3, #32] 8010f5c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010f5e: 68fb ldr r3, [r7, #12] 8010f60: 6a1b ldr r3, [r3, #32] 8010f62: f023 0210 bic.w r2, r3, #16 8010f66: 68fb ldr r3, [r7, #12] 8010f68: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010f6a: 68fb ldr r3, [r7, #12] 8010f6c: 699b ldr r3, [r3, #24] 8010f6e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010f70: 693b ldr r3, [r7, #16] 8010f72: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010f76: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8010f78: 687b ldr r3, [r7, #4] 8010f7a: 031b lsls r3, r3, #12 8010f7c: 693a ldr r2, [r7, #16] 8010f7e: 4313 orrs r3, r2 8010f80: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010f82: 697b ldr r3, [r7, #20] 8010f84: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8010f88: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8010f8a: 68bb ldr r3, [r7, #8] 8010f8c: 011b lsls r3, r3, #4 8010f8e: 697a ldr r2, [r7, #20] 8010f90: 4313 orrs r3, r2 8010f92: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010f94: 68fb ldr r3, [r7, #12] 8010f96: 693a ldr r2, [r7, #16] 8010f98: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010f9a: 68fb ldr r3, [r7, #12] 8010f9c: 697a ldr r2, [r7, #20] 8010f9e: 621a str r2, [r3, #32] } 8010fa0: bf00 nop 8010fa2: 371c adds r7, #28 8010fa4: 46bd mov sp, r7 8010fa6: f85d 7b04 ldr.w r7, [sp], #4 8010faa: 4770 bx lr 08010fac : * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010fac: b480 push {r7} 8010fae: b087 sub sp, #28 8010fb0: af00 add r7, sp, #0 8010fb2: 60f8 str r0, [r7, #12] 8010fb4: 60b9 str r1, [r7, #8] 8010fb6: 607a str r2, [r7, #4] 8010fb8: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ tmpccer = TIMx->CCER; 8010fba: 68fb ldr r3, [r7, #12] 8010fbc: 6a1b ldr r3, [r3, #32] 8010fbe: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC3E; 8010fc0: 68fb ldr r3, [r7, #12] 8010fc2: 6a1b ldr r3, [r3, #32] 8010fc4: f423 7280 bic.w r2, r3, #256 @ 0x100 8010fc8: 68fb ldr r3, [r7, #12] 8010fca: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 8010fcc: 68fb ldr r3, [r7, #12] 8010fce: 69db ldr r3, [r3, #28] 8010fd0: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; 8010fd2: 693b ldr r3, [r7, #16] 8010fd4: f023 0303 bic.w r3, r3, #3 8010fd8: 613b str r3, [r7, #16] tmpccmr2 |= TIM_ICSelection; 8010fda: 693a ldr r2, [r7, #16] 8010fdc: 687b ldr r3, [r7, #4] 8010fde: 4313 orrs r3, r2 8010fe0: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; 8010fe2: 693b ldr r3, [r7, #16] 8010fe4: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010fe8: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); 8010fea: 683b ldr r3, [r7, #0] 8010fec: 011b lsls r3, r3, #4 8010fee: b2db uxtb r3, r3 8010ff0: 693a ldr r2, [r7, #16] 8010ff2: 4313 orrs r3, r2 8010ff4: 613b str r3, [r7, #16] /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 8010ff6: 697b ldr r3, [r7, #20] 8010ff8: f423 6320 bic.w r3, r3, #2560 @ 0xa00 8010ffc: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 8010ffe: 68bb ldr r3, [r7, #8] 8011000: 021b lsls r3, r3, #8 8011002: f403 6320 and.w r3, r3, #2560 @ 0xa00 8011006: 697a ldr r2, [r7, #20] 8011008: 4313 orrs r3, r2 801100a: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 801100c: 68fb ldr r3, [r7, #12] 801100e: 693a ldr r2, [r7, #16] 8011010: 61da str r2, [r3, #28] TIMx->CCER = tmpccer; 8011012: 68fb ldr r3, [r7, #12] 8011014: 697a ldr r2, [r7, #20] 8011016: 621a str r2, [r3, #32] } 8011018: bf00 nop 801101a: 371c adds r7, #28 801101c: 46bd mov sp, r7 801101e: f85d 7b04 ldr.w r7, [sp], #4 8011022: 4770 bx lr 08011024 : * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8011024: b480 push {r7} 8011026: b087 sub sp, #28 8011028: af00 add r7, sp, #0 801102a: 60f8 str r0, [r7, #12] 801102c: 60b9 str r1, [r7, #8] 801102e: 607a str r2, [r7, #4] 8011030: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ tmpccer = TIMx->CCER; 8011032: 68fb ldr r3, [r7, #12] 8011034: 6a1b ldr r3, [r3, #32] 8011036: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC4E; 8011038: 68fb ldr r3, [r7, #12] 801103a: 6a1b ldr r3, [r3, #32] 801103c: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8011040: 68fb ldr r3, [r7, #12] 8011042: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 8011044: 68fb ldr r3, [r7, #12] 8011046: 69db ldr r3, [r3, #28] 8011048: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; 801104a: 693b ldr r3, [r7, #16] 801104c: f423 7340 bic.w r3, r3, #768 @ 0x300 8011050: 613b str r3, [r7, #16] tmpccmr2 |= (TIM_ICSelection << 8U); 8011052: 687b ldr r3, [r7, #4] 8011054: 021b lsls r3, r3, #8 8011056: 693a ldr r2, [r7, #16] 8011058: 4313 orrs r3, r2 801105a: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; 801105c: 693b ldr r3, [r7, #16] 801105e: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8011062: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); 8011064: 683b ldr r3, [r7, #0] 8011066: 031b lsls r3, r3, #12 8011068: b29b uxth r3, r3 801106a: 693a ldr r2, [r7, #16] 801106c: 4313 orrs r3, r2 801106e: 613b str r3, [r7, #16] /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 8011070: 697b ldr r3, [r7, #20] 8011072: f423 4320 bic.w r3, r3, #40960 @ 0xa000 8011076: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 8011078: 68bb ldr r3, [r7, #8] 801107a: 031b lsls r3, r3, #12 801107c: f403 4320 and.w r3, r3, #40960 @ 0xa000 8011080: 697a ldr r2, [r7, #20] 8011082: 4313 orrs r3, r2 8011084: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 8011086: 68fb ldr r3, [r7, #12] 8011088: 693a ldr r2, [r7, #16] 801108a: 61da str r2, [r3, #28] TIMx->CCER = tmpccer ; 801108c: 68fb ldr r3, [r7, #12] 801108e: 697a ldr r2, [r7, #20] 8011090: 621a str r2, [r3, #32] } 8011092: bf00 nop 8011094: 371c adds r7, #28 8011096: 46bd mov sp, r7 8011098: f85d 7b04 ldr.w r7, [sp], #4 801109c: 4770 bx lr ... 080110a0 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 80110a0: b480 push {r7} 80110a2: b085 sub sp, #20 80110a4: af00 add r7, sp, #0 80110a6: 6078 str r0, [r7, #4] 80110a8: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80110aa: 687b ldr r3, [r7, #4] 80110ac: 689b ldr r3, [r3, #8] 80110ae: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80110b0: 68fa ldr r2, [r7, #12] 80110b2: 4b09 ldr r3, [pc, #36] @ (80110d8 ) 80110b4: 4013 ands r3, r2 80110b6: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80110b8: 683a ldr r2, [r7, #0] 80110ba: 68fb ldr r3, [r7, #12] 80110bc: 4313 orrs r3, r2 80110be: f043 0307 orr.w r3, r3, #7 80110c2: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80110c4: 687b ldr r3, [r7, #4] 80110c6: 68fa ldr r2, [r7, #12] 80110c8: 609a str r2, [r3, #8] } 80110ca: bf00 nop 80110cc: 3714 adds r7, #20 80110ce: 46bd mov sp, r7 80110d0: f85d 7b04 ldr.w r7, [sp], #4 80110d4: 4770 bx lr 80110d6: bf00 nop 80110d8: ffcfff8f .word 0xffcfff8f 080110dc : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 80110dc: b480 push {r7} 80110de: b087 sub sp, #28 80110e0: af00 add r7, sp, #0 80110e2: 60f8 str r0, [r7, #12] 80110e4: 60b9 str r1, [r7, #8] 80110e6: 607a str r2, [r7, #4] 80110e8: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 80110ea: 68fb ldr r3, [r7, #12] 80110ec: 689b ldr r3, [r3, #8] 80110ee: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80110f0: 697b ldr r3, [r7, #20] 80110f2: f423 437f bic.w r3, r3, #65280 @ 0xff00 80110f6: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 80110f8: 683b ldr r3, [r7, #0] 80110fa: 021a lsls r2, r3, #8 80110fc: 687b ldr r3, [r7, #4] 80110fe: 431a orrs r2, r3 8011100: 68bb ldr r3, [r7, #8] 8011102: 4313 orrs r3, r2 8011104: 697a ldr r2, [r7, #20] 8011106: 4313 orrs r3, r2 8011108: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 801110a: 68fb ldr r3, [r7, #12] 801110c: 697a ldr r2, [r7, #20] 801110e: 609a str r2, [r3, #8] } 8011110: bf00 nop 8011112: 371c adds r7, #28 8011114: 46bd mov sp, r7 8011116: f85d 7b04 ldr.w r7, [sp], #4 801111a: 4770 bx lr 0801111c : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 801111c: b480 push {r7} 801111e: b087 sub sp, #28 8011120: af00 add r7, sp, #0 8011122: 60f8 str r0, [r7, #12] 8011124: 60b9 str r1, [r7, #8] 8011126: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8011128: 68bb ldr r3, [r7, #8] 801112a: f003 031f and.w r3, r3, #31 801112e: 2201 movs r2, #1 8011130: fa02 f303 lsl.w r3, r2, r3 8011134: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 8011136: 68fb ldr r3, [r7, #12] 8011138: 6a1a ldr r2, [r3, #32] 801113a: 697b ldr r3, [r7, #20] 801113c: 43db mvns r3, r3 801113e: 401a ands r2, r3 8011140: 68fb ldr r3, [r7, #12] 8011142: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8011144: 68fb ldr r3, [r7, #12] 8011146: 6a1a ldr r2, [r3, #32] 8011148: 68bb ldr r3, [r7, #8] 801114a: f003 031f and.w r3, r3, #31 801114e: 6879 ldr r1, [r7, #4] 8011150: fa01 f303 lsl.w r3, r1, r3 8011154: 431a orrs r2, r3 8011156: 68fb ldr r3, [r7, #12] 8011158: 621a str r2, [r3, #32] } 801115a: bf00 nop 801115c: 371c adds r7, #28 801115e: 46bd mov sp, r7 8011160: f85d 7b04 ldr.w r7, [sp], #4 8011164: 4770 bx lr ... 08011168 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8011168: b480 push {r7} 801116a: b085 sub sp, #20 801116c: af00 add r7, sp, #0 801116e: 6078 str r0, [r7, #4] 8011170: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8011172: 687b ldr r3, [r7, #4] 8011174: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011178: 2b01 cmp r3, #1 801117a: d101 bne.n 8011180 801117c: 2302 movs r3, #2 801117e: e06d b.n 801125c 8011180: 687b ldr r3, [r7, #4] 8011182: 2201 movs r2, #1 8011184: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8011188: 687b ldr r3, [r7, #4] 801118a: 2202 movs r2, #2 801118c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8011190: 687b ldr r3, [r7, #4] 8011192: 681b ldr r3, [r3, #0] 8011194: 685b ldr r3, [r3, #4] 8011196: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8011198: 687b ldr r3, [r7, #4] 801119a: 681b ldr r3, [r3, #0] 801119c: 689b ldr r3, [r3, #8] 801119e: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80111a0: 687b ldr r3, [r7, #4] 80111a2: 681b ldr r3, [r3, #0] 80111a4: 4a30 ldr r2, [pc, #192] @ (8011268 ) 80111a6: 4293 cmp r3, r2 80111a8: d004 beq.n 80111b4 80111aa: 687b ldr r3, [r7, #4] 80111ac: 681b ldr r3, [r3, #0] 80111ae: 4a2f ldr r2, [pc, #188] @ (801126c ) 80111b0: 4293 cmp r3, r2 80111b2: d108 bne.n 80111c6 { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 80111b4: 68fb ldr r3, [r7, #12] 80111b6: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 80111ba: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 80111bc: 683b ldr r3, [r7, #0] 80111be: 685b ldr r3, [r3, #4] 80111c0: 68fa ldr r2, [r7, #12] 80111c2: 4313 orrs r3, r2 80111c4: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80111c6: 68fb ldr r3, [r7, #12] 80111c8: f023 0370 bic.w r3, r3, #112 @ 0x70 80111cc: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80111ce: 683b ldr r3, [r7, #0] 80111d0: 681b ldr r3, [r3, #0] 80111d2: 68fa ldr r2, [r7, #12] 80111d4: 4313 orrs r3, r2 80111d6: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80111d8: 687b ldr r3, [r7, #4] 80111da: 681b ldr r3, [r3, #0] 80111dc: 68fa ldr r2, [r7, #12] 80111de: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80111e0: 687b ldr r3, [r7, #4] 80111e2: 681b ldr r3, [r3, #0] 80111e4: 4a20 ldr r2, [pc, #128] @ (8011268 ) 80111e6: 4293 cmp r3, r2 80111e8: d022 beq.n 8011230 80111ea: 687b ldr r3, [r7, #4] 80111ec: 681b ldr r3, [r3, #0] 80111ee: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80111f2: d01d beq.n 8011230 80111f4: 687b ldr r3, [r7, #4] 80111f6: 681b ldr r3, [r3, #0] 80111f8: 4a1d ldr r2, [pc, #116] @ (8011270 ) 80111fa: 4293 cmp r3, r2 80111fc: d018 beq.n 8011230 80111fe: 687b ldr r3, [r7, #4] 8011200: 681b ldr r3, [r3, #0] 8011202: 4a1c ldr r2, [pc, #112] @ (8011274 ) 8011204: 4293 cmp r3, r2 8011206: d013 beq.n 8011230 8011208: 687b ldr r3, [r7, #4] 801120a: 681b ldr r3, [r3, #0] 801120c: 4a1a ldr r2, [pc, #104] @ (8011278 ) 801120e: 4293 cmp r3, r2 8011210: d00e beq.n 8011230 8011212: 687b ldr r3, [r7, #4] 8011214: 681b ldr r3, [r3, #0] 8011216: 4a15 ldr r2, [pc, #84] @ (801126c ) 8011218: 4293 cmp r3, r2 801121a: d009 beq.n 8011230 801121c: 687b ldr r3, [r7, #4] 801121e: 681b ldr r3, [r3, #0] 8011220: 4a16 ldr r2, [pc, #88] @ (801127c ) 8011222: 4293 cmp r3, r2 8011224: d004 beq.n 8011230 8011226: 687b ldr r3, [r7, #4] 8011228: 681b ldr r3, [r3, #0] 801122a: 4a15 ldr r2, [pc, #84] @ (8011280 ) 801122c: 4293 cmp r3, r2 801122e: d10c bne.n 801124a { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8011230: 68bb ldr r3, [r7, #8] 8011232: f023 0380 bic.w r3, r3, #128 @ 0x80 8011236: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8011238: 683b ldr r3, [r7, #0] 801123a: 689b ldr r3, [r3, #8] 801123c: 68ba ldr r2, [r7, #8] 801123e: 4313 orrs r3, r2 8011240: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8011242: 687b ldr r3, [r7, #4] 8011244: 681b ldr r3, [r3, #0] 8011246: 68ba ldr r2, [r7, #8] 8011248: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 801124a: 687b ldr r3, [r7, #4] 801124c: 2201 movs r2, #1 801124e: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8011252: 687b ldr r3, [r7, #4] 8011254: 2200 movs r2, #0 8011256: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801125a: 2300 movs r3, #0 } 801125c: 4618 mov r0, r3 801125e: 3714 adds r7, #20 8011260: 46bd mov sp, r7 8011262: f85d 7b04 ldr.w r7, [sp], #4 8011266: 4770 bx lr 8011268: 40010000 .word 0x40010000 801126c: 40010400 .word 0x40010400 8011270: 40000400 .word 0x40000400 8011274: 40000800 .word 0x40000800 8011278: 40000c00 .word 0x40000c00 801127c: 40001800 .word 0x40001800 8011280: 40014000 .word 0x40014000 08011284 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 8011284: b480 push {r7} 8011286: b085 sub sp, #20 8011288: af00 add r7, sp, #0 801128a: 6078 str r0, [r7, #4] 801128c: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 801128e: 2300 movs r3, #0 8011290: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 8011292: 687b ldr r3, [r7, #4] 8011294: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011298: 2b01 cmp r3, #1 801129a: d101 bne.n 80112a0 801129c: 2302 movs r3, #2 801129e: e065 b.n 801136c 80112a0: 687b ldr r3, [r7, #4] 80112a2: 2201 movs r2, #1 80112a4: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 80112a8: 68fb ldr r3, [r7, #12] 80112aa: f023 02ff bic.w r2, r3, #255 @ 0xff 80112ae: 683b ldr r3, [r7, #0] 80112b0: 68db ldr r3, [r3, #12] 80112b2: 4313 orrs r3, r2 80112b4: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 80112b6: 68fb ldr r3, [r7, #12] 80112b8: f423 7240 bic.w r2, r3, #768 @ 0x300 80112bc: 683b ldr r3, [r7, #0] 80112be: 689b ldr r3, [r3, #8] 80112c0: 4313 orrs r3, r2 80112c2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 80112c4: 68fb ldr r3, [r7, #12] 80112c6: f423 6280 bic.w r2, r3, #1024 @ 0x400 80112ca: 683b ldr r3, [r7, #0] 80112cc: 685b ldr r3, [r3, #4] 80112ce: 4313 orrs r3, r2 80112d0: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 80112d2: 68fb ldr r3, [r7, #12] 80112d4: f423 6200 bic.w r2, r3, #2048 @ 0x800 80112d8: 683b ldr r3, [r7, #0] 80112da: 681b ldr r3, [r3, #0] 80112dc: 4313 orrs r3, r2 80112de: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 80112e0: 68fb ldr r3, [r7, #12] 80112e2: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80112e6: 683b ldr r3, [r7, #0] 80112e8: 691b ldr r3, [r3, #16] 80112ea: 4313 orrs r3, r2 80112ec: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 80112ee: 68fb ldr r3, [r7, #12] 80112f0: f423 5200 bic.w r2, r3, #8192 @ 0x2000 80112f4: 683b ldr r3, [r7, #0] 80112f6: 695b ldr r3, [r3, #20] 80112f8: 4313 orrs r3, r2 80112fa: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 80112fc: 68fb ldr r3, [r7, #12] 80112fe: f423 4280 bic.w r2, r3, #16384 @ 0x4000 8011302: 683b ldr r3, [r7, #0] 8011304: 6a9b ldr r3, [r3, #40] @ 0x28 8011306: 4313 orrs r3, r2 8011308: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 801130a: 68fb ldr r3, [r7, #12] 801130c: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8011310: 683b ldr r3, [r7, #0] 8011312: 699b ldr r3, [r3, #24] 8011314: 041b lsls r3, r3, #16 8011316: 4313 orrs r3, r2 8011318: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 801131a: 687b ldr r3, [r7, #4] 801131c: 681b ldr r3, [r3, #0] 801131e: 4a16 ldr r2, [pc, #88] @ (8011378 ) 8011320: 4293 cmp r3, r2 8011322: d004 beq.n 801132e 8011324: 687b ldr r3, [r7, #4] 8011326: 681b ldr r3, [r3, #0] 8011328: 4a14 ldr r2, [pc, #80] @ (801137c ) 801132a: 4293 cmp r3, r2 801132c: d115 bne.n 801135a #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 801132e: 68fb ldr r3, [r7, #12] 8011330: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000 8011334: 683b ldr r3, [r7, #0] 8011336: 6a5b ldr r3, [r3, #36] @ 0x24 8011338: 051b lsls r3, r3, #20 801133a: 4313 orrs r3, r2 801133c: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 801133e: 68fb ldr r3, [r7, #12] 8011340: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 8011344: 683b ldr r3, [r7, #0] 8011346: 69db ldr r3, [r3, #28] 8011348: 4313 orrs r3, r2 801134a: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 801134c: 68fb ldr r3, [r7, #12] 801134e: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 8011352: 683b ldr r3, [r7, #0] 8011354: 6a1b ldr r3, [r3, #32] 8011356: 4313 orrs r3, r2 8011358: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 801135a: 687b ldr r3, [r7, #4] 801135c: 681b ldr r3, [r3, #0] 801135e: 68fa ldr r2, [r7, #12] 8011360: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 8011362: 687b ldr r3, [r7, #4] 8011364: 2200 movs r2, #0 8011366: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 801136a: 2300 movs r3, #0 } 801136c: 4618 mov r0, r3 801136e: 3714 adds r7, #20 8011370: 46bd mov sp, r7 8011372: f85d 7b04 ldr.w r7, [sp], #4 8011376: 4770 bx lr 8011378: 40010000 .word 0x40010000 801137c: 40010400 .word 0x40010400 08011380 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8011380: b480 push {r7} 8011382: b083 sub sp, #12 8011384: af00 add r7, sp, #0 8011386: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8011388: bf00 nop 801138a: 370c adds r7, #12 801138c: 46bd mov sp, r7 801138e: f85d 7b04 ldr.w r7, [sp], #4 8011392: 4770 bx lr 08011394 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8011394: b480 push {r7} 8011396: b083 sub sp, #12 8011398: af00 add r7, sp, #0 801139a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 801139c: bf00 nop 801139e: 370c adds r7, #12 80113a0: 46bd mov sp, r7 80113a2: f85d 7b04 ldr.w r7, [sp], #4 80113a6: 4770 bx lr 080113a8 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 80113a8: b480 push {r7} 80113aa: b083 sub sp, #12 80113ac: af00 add r7, sp, #0 80113ae: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 80113b0: bf00 nop 80113b2: 370c adds r7, #12 80113b4: 46bd mov sp, r7 80113b6: f85d 7b04 ldr.w r7, [sp], #4 80113ba: 4770 bx lr 080113bc : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80113bc: b580 push {r7, lr} 80113be: b082 sub sp, #8 80113c0: af00 add r7, sp, #0 80113c2: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80113c4: 687b ldr r3, [r7, #4] 80113c6: 2b00 cmp r3, #0 80113c8: d101 bne.n 80113ce { return HAL_ERROR; 80113ca: 2301 movs r3, #1 80113cc: e042 b.n 8011454 { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 80113ce: 687b ldr r3, [r7, #4] 80113d0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80113d4: 2b00 cmp r3, #0 80113d6: d106 bne.n 80113e6 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80113d8: 687b ldr r3, [r7, #4] 80113da: 2200 movs r2, #0 80113dc: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80113e0: 6878 ldr r0, [r7, #4] 80113e2: f7f3 f881 bl 80044e8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80113e6: 687b ldr r3, [r7, #4] 80113e8: 2224 movs r2, #36 @ 0x24 80113ea: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 80113ee: 687b ldr r3, [r7, #4] 80113f0: 681b ldr r3, [r3, #0] 80113f2: 681a ldr r2, [r3, #0] 80113f4: 687b ldr r3, [r7, #4] 80113f6: 681b ldr r3, [r3, #0] 80113f8: f022 0201 bic.w r2, r2, #1 80113fc: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80113fe: 687b ldr r3, [r7, #4] 8011400: 6a9b ldr r3, [r3, #40] @ 0x28 8011402: 2b00 cmp r3, #0 8011404: d002 beq.n 801140c { UART_AdvFeatureConfig(huart); 8011406: 6878 ldr r0, [r7, #4] 8011408: f001 f9e8 bl 80127dc } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 801140c: 6878 ldr r0, [r7, #4] 801140e: f000 fc7d bl 8011d0c 8011412: 4603 mov r3, r0 8011414: 2b01 cmp r3, #1 8011416: d101 bne.n 801141c { return HAL_ERROR; 8011418: 2301 movs r3, #1 801141a: e01b b.n 8011454 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 801141c: 687b ldr r3, [r7, #4] 801141e: 681b ldr r3, [r3, #0] 8011420: 685a ldr r2, [r3, #4] 8011422: 687b ldr r3, [r7, #4] 8011424: 681b ldr r3, [r3, #0] 8011426: f422 4290 bic.w r2, r2, #18432 @ 0x4800 801142a: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 801142c: 687b ldr r3, [r7, #4] 801142e: 681b ldr r3, [r3, #0] 8011430: 689a ldr r2, [r3, #8] 8011432: 687b ldr r3, [r7, #4] 8011434: 681b ldr r3, [r3, #0] 8011436: f022 022a bic.w r2, r2, #42 @ 0x2a 801143a: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 801143c: 687b ldr r3, [r7, #4] 801143e: 681b ldr r3, [r3, #0] 8011440: 681a ldr r2, [r3, #0] 8011442: 687b ldr r3, [r7, #4] 8011444: 681b ldr r3, [r3, #0] 8011446: f042 0201 orr.w r2, r2, #1 801144a: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 801144c: 6878 ldr r0, [r7, #4] 801144e: f001 fa67 bl 8012920 8011452: 4603 mov r3, r0 } 8011454: 4618 mov r0, r3 8011456: 3708 adds r7, #8 8011458: 46bd mov sp, r7 801145a: bd80 pop {r7, pc} 0801145c : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 801145c: b480 push {r7} 801145e: b091 sub sp, #68 @ 0x44 8011460: af00 add r7, sp, #0 8011462: 60f8 str r0, [r7, #12] 8011464: 60b9 str r1, [r7, #8] 8011466: 4613 mov r3, r2 8011468: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 801146a: 68fb ldr r3, [r7, #12] 801146c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8011470: 2b20 cmp r3, #32 8011472: d178 bne.n 8011566 { if ((pData == NULL) || (Size == 0U)) 8011474: 68bb ldr r3, [r7, #8] 8011476: 2b00 cmp r3, #0 8011478: d002 beq.n 8011480 801147a: 88fb ldrh r3, [r7, #6] 801147c: 2b00 cmp r3, #0 801147e: d101 bne.n 8011484 { return HAL_ERROR; 8011480: 2301 movs r3, #1 8011482: e071 b.n 8011568 } huart->pTxBuffPtr = pData; 8011484: 68fb ldr r3, [r7, #12] 8011486: 68ba ldr r2, [r7, #8] 8011488: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 801148a: 68fb ldr r3, [r7, #12] 801148c: 88fa ldrh r2, [r7, #6] 801148e: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 8011492: 68fb ldr r3, [r7, #12] 8011494: 88fa ldrh r2, [r7, #6] 8011496: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 801149a: 68fb ldr r3, [r7, #12] 801149c: 2200 movs r2, #0 801149e: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 80114a0: 68fb ldr r3, [r7, #12] 80114a2: 2200 movs r2, #0 80114a4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 80114a8: 68fb ldr r3, [r7, #12] 80114aa: 2221 movs r2, #33 @ 0x21 80114ac: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 80114b0: 68fb ldr r3, [r7, #12] 80114b2: 6e5b ldr r3, [r3, #100] @ 0x64 80114b4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80114b8: d12a bne.n 8011510 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80114ba: 68fb ldr r3, [r7, #12] 80114bc: 689b ldr r3, [r3, #8] 80114be: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80114c2: d107 bne.n 80114d4 80114c4: 68fb ldr r3, [r7, #12] 80114c6: 691b ldr r3, [r3, #16] 80114c8: 2b00 cmp r3, #0 80114ca: d103 bne.n 80114d4 { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 80114cc: 68fb ldr r3, [r7, #12] 80114ce: 4a29 ldr r2, [pc, #164] @ (8011574 ) 80114d0: 679a str r2, [r3, #120] @ 0x78 80114d2: e002 b.n 80114da } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 80114d4: 68fb ldr r3, [r7, #12] 80114d6: 4a28 ldr r2, [pc, #160] @ (8011578 ) 80114d8: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 80114da: 68fb ldr r3, [r7, #12] 80114dc: 681b ldr r3, [r3, #0] 80114de: 3308 adds r3, #8 80114e0: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80114e2: 6abb ldr r3, [r7, #40] @ 0x28 80114e4: e853 3f00 ldrex r3, [r3] 80114e8: 627b str r3, [r7, #36] @ 0x24 return(result); 80114ea: 6a7b ldr r3, [r7, #36] @ 0x24 80114ec: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80114f0: 63bb str r3, [r7, #56] @ 0x38 80114f2: 68fb ldr r3, [r7, #12] 80114f4: 681b ldr r3, [r3, #0] 80114f6: 3308 adds r3, #8 80114f8: 6bba ldr r2, [r7, #56] @ 0x38 80114fa: 637a str r2, [r7, #52] @ 0x34 80114fc: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80114fe: 6b39 ldr r1, [r7, #48] @ 0x30 8011500: 6b7a ldr r2, [r7, #52] @ 0x34 8011502: e841 2300 strex r3, r2, [r1] 8011506: 62fb str r3, [r7, #44] @ 0x2c return(result); 8011508: 6afb ldr r3, [r7, #44] @ 0x2c 801150a: 2b00 cmp r3, #0 801150c: d1e5 bne.n 80114da 801150e: e028 b.n 8011562 } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8011510: 68fb ldr r3, [r7, #12] 8011512: 689b ldr r3, [r3, #8] 8011514: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8011518: d107 bne.n 801152a 801151a: 68fb ldr r3, [r7, #12] 801151c: 691b ldr r3, [r3, #16] 801151e: 2b00 cmp r3, #0 8011520: d103 bne.n 801152a { huart->TxISR = UART_TxISR_16BIT; 8011522: 68fb ldr r3, [r7, #12] 8011524: 4a15 ldr r2, [pc, #84] @ (801157c ) 8011526: 679a str r2, [r3, #120] @ 0x78 8011528: e002 b.n 8011530 } else { huart->TxISR = UART_TxISR_8BIT; 801152a: 68fb ldr r3, [r7, #12] 801152c: 4a14 ldr r2, [pc, #80] @ (8011580 ) 801152e: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8011530: 68fb ldr r3, [r7, #12] 8011532: 681b ldr r3, [r3, #0] 8011534: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011536: 697b ldr r3, [r7, #20] 8011538: e853 3f00 ldrex r3, [r3] 801153c: 613b str r3, [r7, #16] return(result); 801153e: 693b ldr r3, [r7, #16] 8011540: f043 0380 orr.w r3, r3, #128 @ 0x80 8011544: 63fb str r3, [r7, #60] @ 0x3c 8011546: 68fb ldr r3, [r7, #12] 8011548: 681b ldr r3, [r3, #0] 801154a: 461a mov r2, r3 801154c: 6bfb ldr r3, [r7, #60] @ 0x3c 801154e: 623b str r3, [r7, #32] 8011550: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011552: 69f9 ldr r1, [r7, #28] 8011554: 6a3a ldr r2, [r7, #32] 8011556: e841 2300 strex r3, r2, [r1] 801155a: 61bb str r3, [r7, #24] return(result); 801155c: 69bb ldr r3, [r7, #24] 801155e: 2b00 cmp r3, #0 8011560: d1e6 bne.n 8011530 } return HAL_OK; 8011562: 2300 movs r3, #0 8011564: e000 b.n 8011568 } else { return HAL_BUSY; 8011566: 2302 movs r3, #2 } } 8011568: 4618 mov r0, r3 801156a: 3744 adds r7, #68 @ 0x44 801156c: 46bd mov sp, r7 801156e: f85d 7b04 ldr.w r7, [sp], #4 8011572: 4770 bx lr 8011574: 080130e7 .word 0x080130e7 8011578: 08013007 .word 0x08013007 801157c: 08012f45 .word 0x08012f45 8011580: 08012e8d .word 0x08012e8d 08011584 : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 8011584: b580 push {r7, lr} 8011586: b0ba sub sp, #232 @ 0xe8 8011588: af00 add r7, sp, #0 801158a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 801158c: 687b ldr r3, [r7, #4] 801158e: 681b ldr r3, [r3, #0] 8011590: 69db ldr r3, [r3, #28] 8011592: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8011596: 687b ldr r3, [r7, #4] 8011598: 681b ldr r3, [r3, #0] 801159a: 681b ldr r3, [r3, #0] 801159c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80115a0: 687b ldr r3, [r7, #4] 80115a2: 681b ldr r3, [r3, #0] 80115a4: 689b ldr r3, [r3, #8] 80115a6: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 80115aa: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 80115ae: f640 030f movw r3, #2063 @ 0x80f 80115b2: 4013 ands r3, r2 80115b4: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 80115b8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80115bc: 2b00 cmp r3, #0 80115be: d11b bne.n 80115f8 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 80115c0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80115c4: f003 0320 and.w r3, r3, #32 80115c8: 2b00 cmp r3, #0 80115ca: d015 beq.n 80115f8 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 80115cc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80115d0: f003 0320 and.w r3, r3, #32 80115d4: 2b00 cmp r3, #0 80115d6: d105 bne.n 80115e4 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 80115d8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80115dc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80115e0: 2b00 cmp r3, #0 80115e2: d009 beq.n 80115f8 { if (huart->RxISR != NULL) 80115e4: 687b ldr r3, [r7, #4] 80115e6: 6f5b ldr r3, [r3, #116] @ 0x74 80115e8: 2b00 cmp r3, #0 80115ea: f000 8377 beq.w 8011cdc { huart->RxISR(huart); 80115ee: 687b ldr r3, [r7, #4] 80115f0: 6f5b ldr r3, [r3, #116] @ 0x74 80115f2: 6878 ldr r0, [r7, #4] 80115f4: 4798 blx r3 } return; 80115f6: e371 b.n 8011cdc } } /* If some errors occur */ if ((errorflags != 0U) 80115f8: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80115fc: 2b00 cmp r3, #0 80115fe: f000 8123 beq.w 8011848 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 8011602: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 8011606: 4b8d ldr r3, [pc, #564] @ (801183c ) 8011608: 4013 ands r3, r2 801160a: 2b00 cmp r3, #0 801160c: d106 bne.n 801161c || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 801160e: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 8011612: 4b8b ldr r3, [pc, #556] @ (8011840 ) 8011614: 4013 ands r3, r2 8011616: 2b00 cmp r3, #0 8011618: f000 8116 beq.w 8011848 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 801161c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011620: f003 0301 and.w r3, r3, #1 8011624: 2b00 cmp r3, #0 8011626: d011 beq.n 801164c 8011628: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801162c: f403 7380 and.w r3, r3, #256 @ 0x100 8011630: 2b00 cmp r3, #0 8011632: d00b beq.n 801164c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8011634: 687b ldr r3, [r7, #4] 8011636: 681b ldr r3, [r3, #0] 8011638: 2201 movs r2, #1 801163a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 801163c: 687b ldr r3, [r7, #4] 801163e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011642: f043 0201 orr.w r2, r3, #1 8011646: 687b ldr r3, [r7, #4] 8011648: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 801164c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011650: f003 0302 and.w r3, r3, #2 8011654: 2b00 cmp r3, #0 8011656: d011 beq.n 801167c 8011658: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 801165c: f003 0301 and.w r3, r3, #1 8011660: 2b00 cmp r3, #0 8011662: d00b beq.n 801167c { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8011664: 687b ldr r3, [r7, #4] 8011666: 681b ldr r3, [r3, #0] 8011668: 2202 movs r2, #2 801166a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 801166c: 687b ldr r3, [r7, #4] 801166e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011672: f043 0204 orr.w r2, r3, #4 8011676: 687b ldr r3, [r7, #4] 8011678: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 801167c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011680: f003 0304 and.w r3, r3, #4 8011684: 2b00 cmp r3, #0 8011686: d011 beq.n 80116ac 8011688: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 801168c: f003 0301 and.w r3, r3, #1 8011690: 2b00 cmp r3, #0 8011692: d00b beq.n 80116ac { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8011694: 687b ldr r3, [r7, #4] 8011696: 681b ldr r3, [r3, #0] 8011698: 2204 movs r2, #4 801169a: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 801169c: 687b ldr r3, [r7, #4] 801169e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80116a2: f043 0202 orr.w r2, r3, #2 80116a6: 687b ldr r3, [r7, #4] 80116a8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 80116ac: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80116b0: f003 0308 and.w r3, r3, #8 80116b4: 2b00 cmp r3, #0 80116b6: d017 beq.n 80116e8 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80116b8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80116bc: f003 0320 and.w r3, r3, #32 80116c0: 2b00 cmp r3, #0 80116c2: d105 bne.n 80116d0 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 80116c4: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 80116c8: 4b5c ldr r3, [pc, #368] @ (801183c ) 80116ca: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80116cc: 2b00 cmp r3, #0 80116ce: d00b beq.n 80116e8 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80116d0: 687b ldr r3, [r7, #4] 80116d2: 681b ldr r3, [r3, #0] 80116d4: 2208 movs r2, #8 80116d6: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 80116d8: 687b ldr r3, [r7, #4] 80116da: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80116de: f043 0208 orr.w r2, r3, #8 80116e2: 687b ldr r3, [r7, #4] 80116e4: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 80116e8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80116ec: f403 6300 and.w r3, r3, #2048 @ 0x800 80116f0: 2b00 cmp r3, #0 80116f2: d012 beq.n 801171a 80116f4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80116f8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80116fc: 2b00 cmp r3, #0 80116fe: d00c beq.n 801171a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8011700: 687b ldr r3, [r7, #4] 8011702: 681b ldr r3, [r3, #0] 8011704: f44f 6200 mov.w r2, #2048 @ 0x800 8011708: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 801170a: 687b ldr r3, [r7, #4] 801170c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011710: f043 0220 orr.w r2, r3, #32 8011714: 687b ldr r3, [r7, #4] 8011716: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 801171a: 687b ldr r3, [r7, #4] 801171c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011720: 2b00 cmp r3, #0 8011722: f000 82dd beq.w 8011ce0 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 8011726: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801172a: f003 0320 and.w r3, r3, #32 801172e: 2b00 cmp r3, #0 8011730: d013 beq.n 801175a && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 8011732: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011736: f003 0320 and.w r3, r3, #32 801173a: 2b00 cmp r3, #0 801173c: d105 bne.n 801174a || ((cr3its & USART_CR3_RXFTIE) != 0U))) 801173e: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011742: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8011746: 2b00 cmp r3, #0 8011748: d007 beq.n 801175a { if (huart->RxISR != NULL) 801174a: 687b ldr r3, [r7, #4] 801174c: 6f5b ldr r3, [r3, #116] @ 0x74 801174e: 2b00 cmp r3, #0 8011750: d003 beq.n 801175a { huart->RxISR(huart); 8011752: 687b ldr r3, [r7, #4] 8011754: 6f5b ldr r3, [r3, #116] @ 0x74 8011756: 6878 ldr r0, [r7, #4] 8011758: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 801175a: 687b ldr r3, [r7, #4] 801175c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011760: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8011764: 687b ldr r3, [r7, #4] 8011766: 681b ldr r3, [r3, #0] 8011768: 689b ldr r3, [r3, #8] 801176a: f003 0340 and.w r3, r3, #64 @ 0x40 801176e: 2b40 cmp r3, #64 @ 0x40 8011770: d005 beq.n 801177e ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 8011772: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 8011776: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 801177a: 2b00 cmp r3, #0 801177c: d054 beq.n 8011828 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 801177e: 6878 ldr r0, [r7, #4] 8011780: f001 fb08 bl 8012d94 /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011784: 687b ldr r3, [r7, #4] 8011786: 681b ldr r3, [r3, #0] 8011788: 689b ldr r3, [r3, #8] 801178a: f003 0340 and.w r3, r3, #64 @ 0x40 801178e: 2b40 cmp r3, #64 @ 0x40 8011790: d146 bne.n 8011820 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8011792: 687b ldr r3, [r7, #4] 8011794: 681b ldr r3, [r3, #0] 8011796: 3308 adds r3, #8 8011798: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801179c: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80117a0: e853 3f00 ldrex r3, [r3] 80117a4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 80117a8: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80117ac: f023 0340 bic.w r3, r3, #64 @ 0x40 80117b0: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80117b4: 687b ldr r3, [r7, #4] 80117b6: 681b ldr r3, [r3, #0] 80117b8: 3308 adds r3, #8 80117ba: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80117be: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80117c2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80117c6: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80117ca: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80117ce: e841 2300 strex r3, r2, [r1] 80117d2: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80117d6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80117da: 2b00 cmp r3, #0 80117dc: d1d9 bne.n 8011792 /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80117de: 687b ldr r3, [r7, #4] 80117e0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117e4: 2b00 cmp r3, #0 80117e6: d017 beq.n 8011818 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80117e8: 687b ldr r3, [r7, #4] 80117ea: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117ee: 4a15 ldr r2, [pc, #84] @ (8011844 ) 80117f0: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80117f2: 687b ldr r3, [r7, #4] 80117f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117f8: 4618 mov r0, r3 80117fa: f7f7 ff8f bl 800971c 80117fe: 4603 mov r3, r0 8011800: 2b00 cmp r3, #0 8011802: d019 beq.n 8011838 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 8011804: 687b ldr r3, [r7, #4] 8011806: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801180a: 6d1b ldr r3, [r3, #80] @ 0x50 801180c: 687a ldr r2, [r7, #4] 801180e: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 8011812: 4610 mov r0, r2 8011814: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011816: e00f b.n 8011838 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011818: 6878 ldr r0, [r7, #4] 801181a: f000 fa6d bl 8011cf8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801181e: e00b b.n 8011838 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011820: 6878 ldr r0, [r7, #4] 8011822: f000 fa69 bl 8011cf8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011826: e007 b.n 8011838 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011828: 6878 ldr r0, [r7, #4] 801182a: f000 fa65 bl 8011cf8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 801182e: 687b ldr r3, [r7, #4] 8011830: 2200 movs r2, #0 8011832: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 8011836: e253 b.n 8011ce0 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011838: bf00 nop return; 801183a: e251 b.n 8011ce0 801183c: 10000001 .word 0x10000001 8011840: 04000120 .word 0x04000120 8011844: 08012e61 .word 0x08012e61 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011848: 687b ldr r3, [r7, #4] 801184a: 6edb ldr r3, [r3, #108] @ 0x6c 801184c: 2b01 cmp r3, #1 801184e: f040 81e7 bne.w 8011c20 && ((isrflags & USART_ISR_IDLE) != 0U) 8011852: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011856: f003 0310 and.w r3, r3, #16 801185a: 2b00 cmp r3, #0 801185c: f000 81e0 beq.w 8011c20 && ((cr1its & USART_ISR_IDLE) != 0U)) 8011860: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011864: f003 0310 and.w r3, r3, #16 8011868: 2b00 cmp r3, #0 801186a: f000 81d9 beq.w 8011c20 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 801186e: 687b ldr r3, [r7, #4] 8011870: 681b ldr r3, [r3, #0] 8011872: 2210 movs r2, #16 8011874: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011876: 687b ldr r3, [r7, #4] 8011878: 681b ldr r3, [r3, #0] 801187a: 689b ldr r3, [r3, #8] 801187c: f003 0340 and.w r3, r3, #64 @ 0x40 8011880: 2b40 cmp r3, #64 @ 0x40 8011882: f040 8151 bne.w 8011b28 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 8011886: 687b ldr r3, [r7, #4] 8011888: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801188c: 681b ldr r3, [r3, #0] 801188e: 4a96 ldr r2, [pc, #600] @ (8011ae8 ) 8011890: 4293 cmp r3, r2 8011892: d068 beq.n 8011966 8011894: 687b ldr r3, [r7, #4] 8011896: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801189a: 681b ldr r3, [r3, #0] 801189c: 4a93 ldr r2, [pc, #588] @ (8011aec ) 801189e: 4293 cmp r3, r2 80118a0: d061 beq.n 8011966 80118a2: 687b ldr r3, [r7, #4] 80118a4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118a8: 681b ldr r3, [r3, #0] 80118aa: 4a91 ldr r2, [pc, #580] @ (8011af0 ) 80118ac: 4293 cmp r3, r2 80118ae: d05a beq.n 8011966 80118b0: 687b ldr r3, [r7, #4] 80118b2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118b6: 681b ldr r3, [r3, #0] 80118b8: 4a8e ldr r2, [pc, #568] @ (8011af4 ) 80118ba: 4293 cmp r3, r2 80118bc: d053 beq.n 8011966 80118be: 687b ldr r3, [r7, #4] 80118c0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118c4: 681b ldr r3, [r3, #0] 80118c6: 4a8c ldr r2, [pc, #560] @ (8011af8 ) 80118c8: 4293 cmp r3, r2 80118ca: d04c beq.n 8011966 80118cc: 687b ldr r3, [r7, #4] 80118ce: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118d2: 681b ldr r3, [r3, #0] 80118d4: 4a89 ldr r2, [pc, #548] @ (8011afc ) 80118d6: 4293 cmp r3, r2 80118d8: d045 beq.n 8011966 80118da: 687b ldr r3, [r7, #4] 80118dc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118e0: 681b ldr r3, [r3, #0] 80118e2: 4a87 ldr r2, [pc, #540] @ (8011b00 ) 80118e4: 4293 cmp r3, r2 80118e6: d03e beq.n 8011966 80118e8: 687b ldr r3, [r7, #4] 80118ea: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118ee: 681b ldr r3, [r3, #0] 80118f0: 4a84 ldr r2, [pc, #528] @ (8011b04 ) 80118f2: 4293 cmp r3, r2 80118f4: d037 beq.n 8011966 80118f6: 687b ldr r3, [r7, #4] 80118f8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118fc: 681b ldr r3, [r3, #0] 80118fe: 4a82 ldr r2, [pc, #520] @ (8011b08 ) 8011900: 4293 cmp r3, r2 8011902: d030 beq.n 8011966 8011904: 687b ldr r3, [r7, #4] 8011906: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801190a: 681b ldr r3, [r3, #0] 801190c: 4a7f ldr r2, [pc, #508] @ (8011b0c ) 801190e: 4293 cmp r3, r2 8011910: d029 beq.n 8011966 8011912: 687b ldr r3, [r7, #4] 8011914: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011918: 681b ldr r3, [r3, #0] 801191a: 4a7d ldr r2, [pc, #500] @ (8011b10 ) 801191c: 4293 cmp r3, r2 801191e: d022 beq.n 8011966 8011920: 687b ldr r3, [r7, #4] 8011922: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011926: 681b ldr r3, [r3, #0] 8011928: 4a7a ldr r2, [pc, #488] @ (8011b14 ) 801192a: 4293 cmp r3, r2 801192c: d01b beq.n 8011966 801192e: 687b ldr r3, [r7, #4] 8011930: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011934: 681b ldr r3, [r3, #0] 8011936: 4a78 ldr r2, [pc, #480] @ (8011b18 ) 8011938: 4293 cmp r3, r2 801193a: d014 beq.n 8011966 801193c: 687b ldr r3, [r7, #4] 801193e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011942: 681b ldr r3, [r3, #0] 8011944: 4a75 ldr r2, [pc, #468] @ (8011b1c ) 8011946: 4293 cmp r3, r2 8011948: d00d beq.n 8011966 801194a: 687b ldr r3, [r7, #4] 801194c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011950: 681b ldr r3, [r3, #0] 8011952: 4a73 ldr r2, [pc, #460] @ (8011b20 ) 8011954: 4293 cmp r3, r2 8011956: d006 beq.n 8011966 8011958: 687b ldr r3, [r7, #4] 801195a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801195e: 681b ldr r3, [r3, #0] 8011960: 4a70 ldr r2, [pc, #448] @ (8011b24 ) 8011962: 4293 cmp r3, r2 8011964: d106 bne.n 8011974 8011966: 687b ldr r3, [r7, #4] 8011968: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801196c: 681b ldr r3, [r3, #0] 801196e: 685b ldr r3, [r3, #4] 8011970: b29b uxth r3, r3 8011972: e005 b.n 8011980 8011974: 687b ldr r3, [r7, #4] 8011976: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801197a: 681b ldr r3, [r3, #0] 801197c: 685b ldr r3, [r3, #4] 801197e: b29b uxth r3, r3 8011980: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 8011984: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8011988: 2b00 cmp r3, #0 801198a: f000 81ab beq.w 8011ce4 && (nb_remaining_rx_data < huart->RxXferSize)) 801198e: 687b ldr r3, [r7, #4] 8011990: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8011994: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 8011998: 429a cmp r2, r3 801199a: f080 81a3 bcs.w 8011ce4 { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 801199e: 687b ldr r3, [r7, #4] 80119a0: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80119a4: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 80119a8: 687b ldr r3, [r7, #4] 80119aa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119ae: 69db ldr r3, [r3, #28] 80119b0: f5b3 7f80 cmp.w r3, #256 @ 0x100 80119b4: f000 8087 beq.w 8011ac6 { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80119b8: 687b ldr r3, [r7, #4] 80119ba: 681b ldr r3, [r3, #0] 80119bc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80119c0: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80119c4: e853 3f00 ldrex r3, [r3] 80119c8: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80119cc: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80119d0: f423 7380 bic.w r3, r3, #256 @ 0x100 80119d4: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80119d8: 687b ldr r3, [r7, #4] 80119da: 681b ldr r3, [r3, #0] 80119dc: 461a mov r2, r3 80119de: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 80119e2: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80119e6: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80119ea: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 80119ee: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80119f2: e841 2300 strex r3, r2, [r1] 80119f6: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 80119fa: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80119fe: 2b00 cmp r3, #0 8011a00: d1da bne.n 80119b8 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8011a02: 687b ldr r3, [r7, #4] 8011a04: 681b ldr r3, [r3, #0] 8011a06: 3308 adds r3, #8 8011a08: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a0a: 6f7b ldr r3, [r7, #116] @ 0x74 8011a0c: e853 3f00 ldrex r3, [r3] 8011a10: 673b str r3, [r7, #112] @ 0x70 return(result); 8011a12: 6f3b ldr r3, [r7, #112] @ 0x70 8011a14: f023 0301 bic.w r3, r3, #1 8011a18: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8011a1c: 687b ldr r3, [r7, #4] 8011a1e: 681b ldr r3, [r3, #0] 8011a20: 3308 adds r3, #8 8011a22: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8011a26: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8011a2a: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a2c: 6ff9 ldr r1, [r7, #124] @ 0x7c 8011a2e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8011a32: e841 2300 strex r3, r2, [r1] 8011a36: 67bb str r3, [r7, #120] @ 0x78 return(result); 8011a38: 6fbb ldr r3, [r7, #120] @ 0x78 8011a3a: 2b00 cmp r3, #0 8011a3c: d1e1 bne.n 8011a02 /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8011a3e: 687b ldr r3, [r7, #4] 8011a40: 681b ldr r3, [r3, #0] 8011a42: 3308 adds r3, #8 8011a44: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a46: 6e3b ldr r3, [r7, #96] @ 0x60 8011a48: e853 3f00 ldrex r3, [r3] 8011a4c: 65fb str r3, [r7, #92] @ 0x5c return(result); 8011a4e: 6dfb ldr r3, [r7, #92] @ 0x5c 8011a50: f023 0340 bic.w r3, r3, #64 @ 0x40 8011a54: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8011a58: 687b ldr r3, [r7, #4] 8011a5a: 681b ldr r3, [r3, #0] 8011a5c: 3308 adds r3, #8 8011a5e: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8011a62: 66fa str r2, [r7, #108] @ 0x6c 8011a64: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a66: 6eb9 ldr r1, [r7, #104] @ 0x68 8011a68: 6efa ldr r2, [r7, #108] @ 0x6c 8011a6a: e841 2300 strex r3, r2, [r1] 8011a6e: 667b str r3, [r7, #100] @ 0x64 return(result); 8011a70: 6e7b ldr r3, [r7, #100] @ 0x64 8011a72: 2b00 cmp r3, #0 8011a74: d1e3 bne.n 8011a3e /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011a76: 687b ldr r3, [r7, #4] 8011a78: 2220 movs r2, #32 8011a7a: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011a7e: 687b ldr r3, [r7, #4] 8011a80: 2200 movs r2, #0 8011a82: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011a84: 687b ldr r3, [r7, #4] 8011a86: 681b ldr r3, [r3, #0] 8011a88: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a8a: 6cfb ldr r3, [r7, #76] @ 0x4c 8011a8c: e853 3f00 ldrex r3, [r3] 8011a90: 64bb str r3, [r7, #72] @ 0x48 return(result); 8011a92: 6cbb ldr r3, [r7, #72] @ 0x48 8011a94: f023 0310 bic.w r3, r3, #16 8011a98: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8011a9c: 687b ldr r3, [r7, #4] 8011a9e: 681b ldr r3, [r3, #0] 8011aa0: 461a mov r2, r3 8011aa2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8011aa6: 65bb str r3, [r7, #88] @ 0x58 8011aa8: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011aaa: 6d79 ldr r1, [r7, #84] @ 0x54 8011aac: 6dba ldr r2, [r7, #88] @ 0x58 8011aae: e841 2300 strex r3, r2, [r1] 8011ab2: 653b str r3, [r7, #80] @ 0x50 return(result); 8011ab4: 6d3b ldr r3, [r7, #80] @ 0x50 8011ab6: 2b00 cmp r3, #0 8011ab8: d1e4 bne.n 8011a84 /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8011aba: 687b ldr r3, [r7, #4] 8011abc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011ac0: 4618 mov r0, r3 8011ac2: f7f7 fb0d bl 80090e0 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011ac6: 687b ldr r3, [r7, #4] 8011ac8: 2202 movs r2, #2 8011aca: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8011acc: 687b ldr r3, [r7, #4] 8011ace: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011ad2: 687b ldr r3, [r7, #4] 8011ad4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011ad8: b29b uxth r3, r3 8011ada: 1ad3 subs r3, r2, r3 8011adc: b29b uxth r3, r3 8011ade: 4619 mov r1, r3 8011ae0: 6878 ldr r0, [r7, #4] 8011ae2: f7f2 ffff bl 8004ae4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011ae6: e0fd b.n 8011ce4 8011ae8: 40020010 .word 0x40020010 8011aec: 40020028 .word 0x40020028 8011af0: 40020040 .word 0x40020040 8011af4: 40020058 .word 0x40020058 8011af8: 40020070 .word 0x40020070 8011afc: 40020088 .word 0x40020088 8011b00: 400200a0 .word 0x400200a0 8011b04: 400200b8 .word 0x400200b8 8011b08: 40020410 .word 0x40020410 8011b0c: 40020428 .word 0x40020428 8011b10: 40020440 .word 0x40020440 8011b14: 40020458 .word 0x40020458 8011b18: 40020470 .word 0x40020470 8011b1c: 40020488 .word 0x40020488 8011b20: 400204a0 .word 0x400204a0 8011b24: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8011b28: 687b ldr r3, [r7, #4] 8011b2a: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011b2e: 687b ldr r3, [r7, #4] 8011b30: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011b34: b29b uxth r3, r3 8011b36: 1ad3 subs r3, r2, r3 8011b38: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8011b3c: 687b ldr r3, [r7, #4] 8011b3e: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011b42: b29b uxth r3, r3 8011b44: 2b00 cmp r3, #0 8011b46: f000 80cf beq.w 8011ce8 && (nb_rx_data > 0U)) 8011b4a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011b4e: 2b00 cmp r3, #0 8011b50: f000 80ca beq.w 8011ce8 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011b54: 687b ldr r3, [r7, #4] 8011b56: 681b ldr r3, [r3, #0] 8011b58: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011b5a: 6bbb ldr r3, [r7, #56] @ 0x38 8011b5c: e853 3f00 ldrex r3, [r3] 8011b60: 637b str r3, [r7, #52] @ 0x34 return(result); 8011b62: 6b7b ldr r3, [r7, #52] @ 0x34 8011b64: f423 7390 bic.w r3, r3, #288 @ 0x120 8011b68: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8011b6c: 687b ldr r3, [r7, #4] 8011b6e: 681b ldr r3, [r3, #0] 8011b70: 461a mov r2, r3 8011b72: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8011b76: 647b str r3, [r7, #68] @ 0x44 8011b78: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011b7a: 6c39 ldr r1, [r7, #64] @ 0x40 8011b7c: 6c7a ldr r2, [r7, #68] @ 0x44 8011b7e: e841 2300 strex r3, r2, [r1] 8011b82: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011b84: 6bfb ldr r3, [r7, #60] @ 0x3c 8011b86: 2b00 cmp r3, #0 8011b88: d1e4 bne.n 8011b54 /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8011b8a: 687b ldr r3, [r7, #4] 8011b8c: 681b ldr r3, [r3, #0] 8011b8e: 3308 adds r3, #8 8011b90: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011b92: 6a7b ldr r3, [r7, #36] @ 0x24 8011b94: e853 3f00 ldrex r3, [r3] 8011b98: 623b str r3, [r7, #32] return(result); 8011b9a: 6a3a ldr r2, [r7, #32] 8011b9c: 4b55 ldr r3, [pc, #340] @ (8011cf4 ) 8011b9e: 4013 ands r3, r2 8011ba0: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8011ba4: 687b ldr r3, [r7, #4] 8011ba6: 681b ldr r3, [r3, #0] 8011ba8: 3308 adds r3, #8 8011baa: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8011bae: 633a str r2, [r7, #48] @ 0x30 8011bb0: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011bb2: 6af9 ldr r1, [r7, #44] @ 0x2c 8011bb4: 6b3a ldr r2, [r7, #48] @ 0x30 8011bb6: e841 2300 strex r3, r2, [r1] 8011bba: 62bb str r3, [r7, #40] @ 0x28 return(result); 8011bbc: 6abb ldr r3, [r7, #40] @ 0x28 8011bbe: 2b00 cmp r3, #0 8011bc0: d1e3 bne.n 8011b8a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011bc2: 687b ldr r3, [r7, #4] 8011bc4: 2220 movs r2, #32 8011bc6: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011bca: 687b ldr r3, [r7, #4] 8011bcc: 2200 movs r2, #0 8011bce: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8011bd0: 687b ldr r3, [r7, #4] 8011bd2: 2200 movs r2, #0 8011bd4: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011bd6: 687b ldr r3, [r7, #4] 8011bd8: 681b ldr r3, [r3, #0] 8011bda: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011bdc: 693b ldr r3, [r7, #16] 8011bde: e853 3f00 ldrex r3, [r3] 8011be2: 60fb str r3, [r7, #12] return(result); 8011be4: 68fb ldr r3, [r7, #12] 8011be6: f023 0310 bic.w r3, r3, #16 8011bea: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8011bee: 687b ldr r3, [r7, #4] 8011bf0: 681b ldr r3, [r3, #0] 8011bf2: 461a mov r2, r3 8011bf4: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8011bf8: 61fb str r3, [r7, #28] 8011bfa: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011bfc: 69b9 ldr r1, [r7, #24] 8011bfe: 69fa ldr r2, [r7, #28] 8011c00: e841 2300 strex r3, r2, [r1] 8011c04: 617b str r3, [r7, #20] return(result); 8011c06: 697b ldr r3, [r7, #20] 8011c08: 2b00 cmp r3, #0 8011c0a: d1e4 bne.n 8011bd6 /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011c0c: 687b ldr r3, [r7, #4] 8011c0e: 2202 movs r2, #2 8011c10: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8011c12: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011c16: 4619 mov r1, r3 8011c18: 6878 ldr r0, [r7, #4] 8011c1a: f7f2 ff63 bl 8004ae4 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011c1e: e063 b.n 8011ce8 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8011c20: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c24: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8011c28: 2b00 cmp r3, #0 8011c2a: d00e beq.n 8011c4a 8011c2c: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011c30: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011c34: 2b00 cmp r3, #0 8011c36: d008 beq.n 8011c4a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8011c38: 687b ldr r3, [r7, #4] 8011c3a: 681b ldr r3, [r3, #0] 8011c3c: f44f 1280 mov.w r2, #1048576 @ 0x100000 8011c40: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8011c42: 6878 ldr r0, [r7, #4] 8011c44: f002 f80c bl 8013c60 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011c48: e051 b.n 8011cee } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 8011c4a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c4e: f003 0380 and.w r3, r3, #128 @ 0x80 8011c52: 2b00 cmp r3, #0 8011c54: d014 beq.n 8011c80 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8011c56: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011c5a: f003 0380 and.w r3, r3, #128 @ 0x80 8011c5e: 2b00 cmp r3, #0 8011c60: d105 bne.n 8011c6e || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8011c62: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011c66: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011c6a: 2b00 cmp r3, #0 8011c6c: d008 beq.n 8011c80 { if (huart->TxISR != NULL) 8011c6e: 687b ldr r3, [r7, #4] 8011c70: 6f9b ldr r3, [r3, #120] @ 0x78 8011c72: 2b00 cmp r3, #0 8011c74: d03a beq.n 8011cec { huart->TxISR(huart); 8011c76: 687b ldr r3, [r7, #4] 8011c78: 6f9b ldr r3, [r3, #120] @ 0x78 8011c7a: 6878 ldr r0, [r7, #4] 8011c7c: 4798 blx r3 } return; 8011c7e: e035 b.n 8011cec } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8011c80: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c84: f003 0340 and.w r3, r3, #64 @ 0x40 8011c88: 2b00 cmp r3, #0 8011c8a: d009 beq.n 8011ca0 8011c8c: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011c90: f003 0340 and.w r3, r3, #64 @ 0x40 8011c94: 2b00 cmp r3, #0 8011c96: d003 beq.n 8011ca0 { UART_EndTransmit_IT(huart); 8011c98: 6878 ldr r0, [r7, #4] 8011c9a: f001 fa99 bl 80131d0 return; 8011c9e: e026 b.n 8011cee } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8011ca0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011ca4: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011ca8: 2b00 cmp r3, #0 8011caa: d009 beq.n 8011cc0 8011cac: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011cb0: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8011cb4: 2b00 cmp r3, #0 8011cb6: d003 beq.n 8011cc0 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 8011cb8: 6878 ldr r0, [r7, #4] 8011cba: f001 ffe5 bl 8013c88 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011cbe: e016 b.n 8011cee } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8011cc0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011cc4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8011cc8: 2b00 cmp r3, #0 8011cca: d010 beq.n 8011cee 8011ccc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011cd0: 2b00 cmp r3, #0 8011cd2: da0c bge.n 8011cee #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8011cd4: 6878 ldr r0, [r7, #4] 8011cd6: f001 ffcd bl 8013c74 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011cda: e008 b.n 8011cee return; 8011cdc: bf00 nop 8011cde: e006 b.n 8011cee return; 8011ce0: bf00 nop 8011ce2: e004 b.n 8011cee return; 8011ce4: bf00 nop 8011ce6: e002 b.n 8011cee return; 8011ce8: bf00 nop 8011cea: e000 b.n 8011cee return; 8011cec: bf00 nop } } 8011cee: 37e8 adds r7, #232 @ 0xe8 8011cf0: 46bd mov sp, r7 8011cf2: bd80 pop {r7, pc} 8011cf4: effffffe .word 0xeffffffe 08011cf8 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8011cf8: b480 push {r7} 8011cfa: b083 sub sp, #12 8011cfc: af00 add r7, sp, #0 8011cfe: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8011d00: bf00 nop 8011d02: 370c adds r7, #12 8011d04: 46bd mov sp, r7 8011d06: f85d 7b04 ldr.w r7, [sp], #4 8011d0a: 4770 bx lr 08011d0c : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8011d0c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8011d10: b092 sub sp, #72 @ 0x48 8011d12: af00 add r7, sp, #0 8011d14: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8011d16: 2300 movs r3, #0 8011d18: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8011d1c: 697b ldr r3, [r7, #20] 8011d1e: 689a ldr r2, [r3, #8] 8011d20: 697b ldr r3, [r7, #20] 8011d22: 691b ldr r3, [r3, #16] 8011d24: 431a orrs r2, r3 8011d26: 697b ldr r3, [r7, #20] 8011d28: 695b ldr r3, [r3, #20] 8011d2a: 431a orrs r2, r3 8011d2c: 697b ldr r3, [r7, #20] 8011d2e: 69db ldr r3, [r3, #28] 8011d30: 4313 orrs r3, r2 8011d32: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8011d34: 697b ldr r3, [r7, #20] 8011d36: 681b ldr r3, [r3, #0] 8011d38: 681a ldr r2, [r3, #0] 8011d3a: 4bbe ldr r3, [pc, #760] @ (8012034 ) 8011d3c: 4013 ands r3, r2 8011d3e: 697a ldr r2, [r7, #20] 8011d40: 6812 ldr r2, [r2, #0] 8011d42: 6c79 ldr r1, [r7, #68] @ 0x44 8011d44: 430b orrs r3, r1 8011d46: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8011d48: 697b ldr r3, [r7, #20] 8011d4a: 681b ldr r3, [r3, #0] 8011d4c: 685b ldr r3, [r3, #4] 8011d4e: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8011d52: 697b ldr r3, [r7, #20] 8011d54: 68da ldr r2, [r3, #12] 8011d56: 697b ldr r3, [r7, #20] 8011d58: 681b ldr r3, [r3, #0] 8011d5a: 430a orrs r2, r1 8011d5c: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8011d5e: 697b ldr r3, [r7, #20] 8011d60: 699b ldr r3, [r3, #24] 8011d62: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 8011d64: 697b ldr r3, [r7, #20] 8011d66: 681b ldr r3, [r3, #0] 8011d68: 4ab3 ldr r2, [pc, #716] @ (8012038 ) 8011d6a: 4293 cmp r3, r2 8011d6c: d004 beq.n 8011d78 { tmpreg |= huart->Init.OneBitSampling; 8011d6e: 697b ldr r3, [r7, #20] 8011d70: 6a1b ldr r3, [r3, #32] 8011d72: 6c7a ldr r2, [r7, #68] @ 0x44 8011d74: 4313 orrs r3, r2 8011d76: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8011d78: 697b ldr r3, [r7, #20] 8011d7a: 681b ldr r3, [r3, #0] 8011d7c: 689a ldr r2, [r3, #8] 8011d7e: 4baf ldr r3, [pc, #700] @ (801203c ) 8011d80: 4013 ands r3, r2 8011d82: 697a ldr r2, [r7, #20] 8011d84: 6812 ldr r2, [r2, #0] 8011d86: 6c79 ldr r1, [r7, #68] @ 0x44 8011d88: 430b orrs r3, r1 8011d8a: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8011d8c: 697b ldr r3, [r7, #20] 8011d8e: 681b ldr r3, [r3, #0] 8011d90: 6adb ldr r3, [r3, #44] @ 0x2c 8011d92: f023 010f bic.w r1, r3, #15 8011d96: 697b ldr r3, [r7, #20] 8011d98: 6a5a ldr r2, [r3, #36] @ 0x24 8011d9a: 697b ldr r3, [r7, #20] 8011d9c: 681b ldr r3, [r3, #0] 8011d9e: 430a orrs r2, r1 8011da0: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8011da2: 697b ldr r3, [r7, #20] 8011da4: 681b ldr r3, [r3, #0] 8011da6: 4aa6 ldr r2, [pc, #664] @ (8012040 ) 8011da8: 4293 cmp r3, r2 8011daa: d177 bne.n 8011e9c 8011dac: 4ba5 ldr r3, [pc, #660] @ (8012044 ) 8011dae: 6d5b ldr r3, [r3, #84] @ 0x54 8011db0: f003 0338 and.w r3, r3, #56 @ 0x38 8011db4: 2b28 cmp r3, #40 @ 0x28 8011db6: d86d bhi.n 8011e94 8011db8: a201 add r2, pc, #4 @ (adr r2, 8011dc0 ) 8011dba: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011dbe: bf00 nop 8011dc0: 08011e65 .word 0x08011e65 8011dc4: 08011e95 .word 0x08011e95 8011dc8: 08011e95 .word 0x08011e95 8011dcc: 08011e95 .word 0x08011e95 8011dd0: 08011e95 .word 0x08011e95 8011dd4: 08011e95 .word 0x08011e95 8011dd8: 08011e95 .word 0x08011e95 8011ddc: 08011e95 .word 0x08011e95 8011de0: 08011e6d .word 0x08011e6d 8011de4: 08011e95 .word 0x08011e95 8011de8: 08011e95 .word 0x08011e95 8011dec: 08011e95 .word 0x08011e95 8011df0: 08011e95 .word 0x08011e95 8011df4: 08011e95 .word 0x08011e95 8011df8: 08011e95 .word 0x08011e95 8011dfc: 08011e95 .word 0x08011e95 8011e00: 08011e75 .word 0x08011e75 8011e04: 08011e95 .word 0x08011e95 8011e08: 08011e95 .word 0x08011e95 8011e0c: 08011e95 .word 0x08011e95 8011e10: 08011e95 .word 0x08011e95 8011e14: 08011e95 .word 0x08011e95 8011e18: 08011e95 .word 0x08011e95 8011e1c: 08011e95 .word 0x08011e95 8011e20: 08011e7d .word 0x08011e7d 8011e24: 08011e95 .word 0x08011e95 8011e28: 08011e95 .word 0x08011e95 8011e2c: 08011e95 .word 0x08011e95 8011e30: 08011e95 .word 0x08011e95 8011e34: 08011e95 .word 0x08011e95 8011e38: 08011e95 .word 0x08011e95 8011e3c: 08011e95 .word 0x08011e95 8011e40: 08011e85 .word 0x08011e85 8011e44: 08011e95 .word 0x08011e95 8011e48: 08011e95 .word 0x08011e95 8011e4c: 08011e95 .word 0x08011e95 8011e50: 08011e95 .word 0x08011e95 8011e54: 08011e95 .word 0x08011e95 8011e58: 08011e95 .word 0x08011e95 8011e5c: 08011e95 .word 0x08011e95 8011e60: 08011e8d .word 0x08011e8d 8011e64: 2301 movs r3, #1 8011e66: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e6a: e222 b.n 80122b2 8011e6c: 2304 movs r3, #4 8011e6e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e72: e21e b.n 80122b2 8011e74: 2308 movs r3, #8 8011e76: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e7a: e21a b.n 80122b2 8011e7c: 2310 movs r3, #16 8011e7e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e82: e216 b.n 80122b2 8011e84: 2320 movs r3, #32 8011e86: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e8a: e212 b.n 80122b2 8011e8c: 2340 movs r3, #64 @ 0x40 8011e8e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e92: e20e b.n 80122b2 8011e94: 2380 movs r3, #128 @ 0x80 8011e96: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e9a: e20a b.n 80122b2 8011e9c: 697b ldr r3, [r7, #20] 8011e9e: 681b ldr r3, [r3, #0] 8011ea0: 4a69 ldr r2, [pc, #420] @ (8012048 ) 8011ea2: 4293 cmp r3, r2 8011ea4: d130 bne.n 8011f08 8011ea6: 4b67 ldr r3, [pc, #412] @ (8012044 ) 8011ea8: 6d5b ldr r3, [r3, #84] @ 0x54 8011eaa: f003 0307 and.w r3, r3, #7 8011eae: 2b05 cmp r3, #5 8011eb0: d826 bhi.n 8011f00 8011eb2: a201 add r2, pc, #4 @ (adr r2, 8011eb8 ) 8011eb4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011eb8: 08011ed1 .word 0x08011ed1 8011ebc: 08011ed9 .word 0x08011ed9 8011ec0: 08011ee1 .word 0x08011ee1 8011ec4: 08011ee9 .word 0x08011ee9 8011ec8: 08011ef1 .word 0x08011ef1 8011ecc: 08011ef9 .word 0x08011ef9 8011ed0: 2300 movs r3, #0 8011ed2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ed6: e1ec b.n 80122b2 8011ed8: 2304 movs r3, #4 8011eda: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ede: e1e8 b.n 80122b2 8011ee0: 2308 movs r3, #8 8011ee2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ee6: e1e4 b.n 80122b2 8011ee8: 2310 movs r3, #16 8011eea: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011eee: e1e0 b.n 80122b2 8011ef0: 2320 movs r3, #32 8011ef2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ef6: e1dc b.n 80122b2 8011ef8: 2340 movs r3, #64 @ 0x40 8011efa: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011efe: e1d8 b.n 80122b2 8011f00: 2380 movs r3, #128 @ 0x80 8011f02: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f06: e1d4 b.n 80122b2 8011f08: 697b ldr r3, [r7, #20] 8011f0a: 681b ldr r3, [r3, #0] 8011f0c: 4a4f ldr r2, [pc, #316] @ (801204c ) 8011f0e: 4293 cmp r3, r2 8011f10: d130 bne.n 8011f74 8011f12: 4b4c ldr r3, [pc, #304] @ (8012044 ) 8011f14: 6d5b ldr r3, [r3, #84] @ 0x54 8011f16: f003 0307 and.w r3, r3, #7 8011f1a: 2b05 cmp r3, #5 8011f1c: d826 bhi.n 8011f6c 8011f1e: a201 add r2, pc, #4 @ (adr r2, 8011f24 ) 8011f20: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011f24: 08011f3d .word 0x08011f3d 8011f28: 08011f45 .word 0x08011f45 8011f2c: 08011f4d .word 0x08011f4d 8011f30: 08011f55 .word 0x08011f55 8011f34: 08011f5d .word 0x08011f5d 8011f38: 08011f65 .word 0x08011f65 8011f3c: 2300 movs r3, #0 8011f3e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f42: e1b6 b.n 80122b2 8011f44: 2304 movs r3, #4 8011f46: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f4a: e1b2 b.n 80122b2 8011f4c: 2308 movs r3, #8 8011f4e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f52: e1ae b.n 80122b2 8011f54: 2310 movs r3, #16 8011f56: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f5a: e1aa b.n 80122b2 8011f5c: 2320 movs r3, #32 8011f5e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f62: e1a6 b.n 80122b2 8011f64: 2340 movs r3, #64 @ 0x40 8011f66: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f6a: e1a2 b.n 80122b2 8011f6c: 2380 movs r3, #128 @ 0x80 8011f6e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f72: e19e b.n 80122b2 8011f74: 697b ldr r3, [r7, #20] 8011f76: 681b ldr r3, [r3, #0] 8011f78: 4a35 ldr r2, [pc, #212] @ (8012050 ) 8011f7a: 4293 cmp r3, r2 8011f7c: d130 bne.n 8011fe0 8011f7e: 4b31 ldr r3, [pc, #196] @ (8012044 ) 8011f80: 6d5b ldr r3, [r3, #84] @ 0x54 8011f82: f003 0307 and.w r3, r3, #7 8011f86: 2b05 cmp r3, #5 8011f88: d826 bhi.n 8011fd8 8011f8a: a201 add r2, pc, #4 @ (adr r2, 8011f90 ) 8011f8c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011f90: 08011fa9 .word 0x08011fa9 8011f94: 08011fb1 .word 0x08011fb1 8011f98: 08011fb9 .word 0x08011fb9 8011f9c: 08011fc1 .word 0x08011fc1 8011fa0: 08011fc9 .word 0x08011fc9 8011fa4: 08011fd1 .word 0x08011fd1 8011fa8: 2300 movs r3, #0 8011faa: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fae: e180 b.n 80122b2 8011fb0: 2304 movs r3, #4 8011fb2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fb6: e17c b.n 80122b2 8011fb8: 2308 movs r3, #8 8011fba: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fbe: e178 b.n 80122b2 8011fc0: 2310 movs r3, #16 8011fc2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fc6: e174 b.n 80122b2 8011fc8: 2320 movs r3, #32 8011fca: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fce: e170 b.n 80122b2 8011fd0: 2340 movs r3, #64 @ 0x40 8011fd2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fd6: e16c b.n 80122b2 8011fd8: 2380 movs r3, #128 @ 0x80 8011fda: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fde: e168 b.n 80122b2 8011fe0: 697b ldr r3, [r7, #20] 8011fe2: 681b ldr r3, [r3, #0] 8011fe4: 4a1b ldr r2, [pc, #108] @ (8012054 ) 8011fe6: 4293 cmp r3, r2 8011fe8: d142 bne.n 8012070 8011fea: 4b16 ldr r3, [pc, #88] @ (8012044 ) 8011fec: 6d5b ldr r3, [r3, #84] @ 0x54 8011fee: f003 0307 and.w r3, r3, #7 8011ff2: 2b05 cmp r3, #5 8011ff4: d838 bhi.n 8012068 8011ff6: a201 add r2, pc, #4 @ (adr r2, 8011ffc ) 8011ff8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011ffc: 08012015 .word 0x08012015 8012000: 0801201d .word 0x0801201d 8012004: 08012025 .word 0x08012025 8012008: 0801202d .word 0x0801202d 801200c: 08012059 .word 0x08012059 8012010: 08012061 .word 0x08012061 8012014: 2300 movs r3, #0 8012016: f887 3043 strb.w r3, [r7, #67] @ 0x43 801201a: e14a b.n 80122b2 801201c: 2304 movs r3, #4 801201e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012022: e146 b.n 80122b2 8012024: 2308 movs r3, #8 8012026: f887 3043 strb.w r3, [r7, #67] @ 0x43 801202a: e142 b.n 80122b2 801202c: 2310 movs r3, #16 801202e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012032: e13e b.n 80122b2 8012034: cfff69f3 .word 0xcfff69f3 8012038: 58000c00 .word 0x58000c00 801203c: 11fff4ff .word 0x11fff4ff 8012040: 40011000 .word 0x40011000 8012044: 58024400 .word 0x58024400 8012048: 40004400 .word 0x40004400 801204c: 40004800 .word 0x40004800 8012050: 40004c00 .word 0x40004c00 8012054: 40005000 .word 0x40005000 8012058: 2320 movs r3, #32 801205a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801205e: e128 b.n 80122b2 8012060: 2340 movs r3, #64 @ 0x40 8012062: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012066: e124 b.n 80122b2 8012068: 2380 movs r3, #128 @ 0x80 801206a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801206e: e120 b.n 80122b2 8012070: 697b ldr r3, [r7, #20] 8012072: 681b ldr r3, [r3, #0] 8012074: 4acb ldr r2, [pc, #812] @ (80123a4 ) 8012076: 4293 cmp r3, r2 8012078: d176 bne.n 8012168 801207a: 4bcb ldr r3, [pc, #812] @ (80123a8 ) 801207c: 6d5b ldr r3, [r3, #84] @ 0x54 801207e: f003 0338 and.w r3, r3, #56 @ 0x38 8012082: 2b28 cmp r3, #40 @ 0x28 8012084: d86c bhi.n 8012160 8012086: a201 add r2, pc, #4 @ (adr r2, 801208c ) 8012088: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801208c: 08012131 .word 0x08012131 8012090: 08012161 .word 0x08012161 8012094: 08012161 .word 0x08012161 8012098: 08012161 .word 0x08012161 801209c: 08012161 .word 0x08012161 80120a0: 08012161 .word 0x08012161 80120a4: 08012161 .word 0x08012161 80120a8: 08012161 .word 0x08012161 80120ac: 08012139 .word 0x08012139 80120b0: 08012161 .word 0x08012161 80120b4: 08012161 .word 0x08012161 80120b8: 08012161 .word 0x08012161 80120bc: 08012161 .word 0x08012161 80120c0: 08012161 .word 0x08012161 80120c4: 08012161 .word 0x08012161 80120c8: 08012161 .word 0x08012161 80120cc: 08012141 .word 0x08012141 80120d0: 08012161 .word 0x08012161 80120d4: 08012161 .word 0x08012161 80120d8: 08012161 .word 0x08012161 80120dc: 08012161 .word 0x08012161 80120e0: 08012161 .word 0x08012161 80120e4: 08012161 .word 0x08012161 80120e8: 08012161 .word 0x08012161 80120ec: 08012149 .word 0x08012149 80120f0: 08012161 .word 0x08012161 80120f4: 08012161 .word 0x08012161 80120f8: 08012161 .word 0x08012161 80120fc: 08012161 .word 0x08012161 8012100: 08012161 .word 0x08012161 8012104: 08012161 .word 0x08012161 8012108: 08012161 .word 0x08012161 801210c: 08012151 .word 0x08012151 8012110: 08012161 .word 0x08012161 8012114: 08012161 .word 0x08012161 8012118: 08012161 .word 0x08012161 801211c: 08012161 .word 0x08012161 8012120: 08012161 .word 0x08012161 8012124: 08012161 .word 0x08012161 8012128: 08012161 .word 0x08012161 801212c: 08012159 .word 0x08012159 8012130: 2301 movs r3, #1 8012132: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012136: e0bc b.n 80122b2 8012138: 2304 movs r3, #4 801213a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801213e: e0b8 b.n 80122b2 8012140: 2308 movs r3, #8 8012142: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012146: e0b4 b.n 80122b2 8012148: 2310 movs r3, #16 801214a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801214e: e0b0 b.n 80122b2 8012150: 2320 movs r3, #32 8012152: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012156: e0ac b.n 80122b2 8012158: 2340 movs r3, #64 @ 0x40 801215a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801215e: e0a8 b.n 80122b2 8012160: 2380 movs r3, #128 @ 0x80 8012162: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012166: e0a4 b.n 80122b2 8012168: 697b ldr r3, [r7, #20] 801216a: 681b ldr r3, [r3, #0] 801216c: 4a8f ldr r2, [pc, #572] @ (80123ac ) 801216e: 4293 cmp r3, r2 8012170: d130 bne.n 80121d4 8012172: 4b8d ldr r3, [pc, #564] @ (80123a8 ) 8012174: 6d5b ldr r3, [r3, #84] @ 0x54 8012176: f003 0307 and.w r3, r3, #7 801217a: 2b05 cmp r3, #5 801217c: d826 bhi.n 80121cc 801217e: a201 add r2, pc, #4 @ (adr r2, 8012184 ) 8012180: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012184: 0801219d .word 0x0801219d 8012188: 080121a5 .word 0x080121a5 801218c: 080121ad .word 0x080121ad 8012190: 080121b5 .word 0x080121b5 8012194: 080121bd .word 0x080121bd 8012198: 080121c5 .word 0x080121c5 801219c: 2300 movs r3, #0 801219e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121a2: e086 b.n 80122b2 80121a4: 2304 movs r3, #4 80121a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121aa: e082 b.n 80122b2 80121ac: 2308 movs r3, #8 80121ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121b2: e07e b.n 80122b2 80121b4: 2310 movs r3, #16 80121b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121ba: e07a b.n 80122b2 80121bc: 2320 movs r3, #32 80121be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121c2: e076 b.n 80122b2 80121c4: 2340 movs r3, #64 @ 0x40 80121c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121ca: e072 b.n 80122b2 80121cc: 2380 movs r3, #128 @ 0x80 80121ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121d2: e06e b.n 80122b2 80121d4: 697b ldr r3, [r7, #20] 80121d6: 681b ldr r3, [r3, #0] 80121d8: 4a75 ldr r2, [pc, #468] @ (80123b0 ) 80121da: 4293 cmp r3, r2 80121dc: d130 bne.n 8012240 80121de: 4b72 ldr r3, [pc, #456] @ (80123a8 ) 80121e0: 6d5b ldr r3, [r3, #84] @ 0x54 80121e2: f003 0307 and.w r3, r3, #7 80121e6: 2b05 cmp r3, #5 80121e8: d826 bhi.n 8012238 80121ea: a201 add r2, pc, #4 @ (adr r2, 80121f0 ) 80121ec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80121f0: 08012209 .word 0x08012209 80121f4: 08012211 .word 0x08012211 80121f8: 08012219 .word 0x08012219 80121fc: 08012221 .word 0x08012221 8012200: 08012229 .word 0x08012229 8012204: 08012231 .word 0x08012231 8012208: 2300 movs r3, #0 801220a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801220e: e050 b.n 80122b2 8012210: 2304 movs r3, #4 8012212: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012216: e04c b.n 80122b2 8012218: 2308 movs r3, #8 801221a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801221e: e048 b.n 80122b2 8012220: 2310 movs r3, #16 8012222: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012226: e044 b.n 80122b2 8012228: 2320 movs r3, #32 801222a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801222e: e040 b.n 80122b2 8012230: 2340 movs r3, #64 @ 0x40 8012232: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012236: e03c b.n 80122b2 8012238: 2380 movs r3, #128 @ 0x80 801223a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801223e: e038 b.n 80122b2 8012240: 697b ldr r3, [r7, #20] 8012242: 681b ldr r3, [r3, #0] 8012244: 4a5b ldr r2, [pc, #364] @ (80123b4 ) 8012246: 4293 cmp r3, r2 8012248: d130 bne.n 80122ac 801224a: 4b57 ldr r3, [pc, #348] @ (80123a8 ) 801224c: 6d9b ldr r3, [r3, #88] @ 0x58 801224e: f003 0307 and.w r3, r3, #7 8012252: 2b05 cmp r3, #5 8012254: d826 bhi.n 80122a4 8012256: a201 add r2, pc, #4 @ (adr r2, 801225c ) 8012258: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801225c: 08012275 .word 0x08012275 8012260: 0801227d .word 0x0801227d 8012264: 08012285 .word 0x08012285 8012268: 0801228d .word 0x0801228d 801226c: 08012295 .word 0x08012295 8012270: 0801229d .word 0x0801229d 8012274: 2302 movs r3, #2 8012276: f887 3043 strb.w r3, [r7, #67] @ 0x43 801227a: e01a b.n 80122b2 801227c: 2304 movs r3, #4 801227e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012282: e016 b.n 80122b2 8012284: 2308 movs r3, #8 8012286: f887 3043 strb.w r3, [r7, #67] @ 0x43 801228a: e012 b.n 80122b2 801228c: 2310 movs r3, #16 801228e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012292: e00e b.n 80122b2 8012294: 2320 movs r3, #32 8012296: f887 3043 strb.w r3, [r7, #67] @ 0x43 801229a: e00a b.n 80122b2 801229c: 2340 movs r3, #64 @ 0x40 801229e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122a2: e006 b.n 80122b2 80122a4: 2380 movs r3, #128 @ 0x80 80122a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122aa: e002 b.n 80122b2 80122ac: 2380 movs r3, #128 @ 0x80 80122ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 80122b2: 697b ldr r3, [r7, #20] 80122b4: 681b ldr r3, [r3, #0] 80122b6: 4a3f ldr r2, [pc, #252] @ (80123b4 ) 80122b8: 4293 cmp r3, r2 80122ba: f040 80f8 bne.w 80124ae { /* Retrieve frequency clock */ switch (clocksource) 80122be: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80122c2: 2b20 cmp r3, #32 80122c4: dc46 bgt.n 8012354 80122c6: 2b02 cmp r3, #2 80122c8: f2c0 8082 blt.w 80123d0 80122cc: 3b02 subs r3, #2 80122ce: 2b1e cmp r3, #30 80122d0: d87e bhi.n 80123d0 80122d2: a201 add r2, pc, #4 @ (adr r2, 80122d8 ) 80122d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80122d8: 0801235b .word 0x0801235b 80122dc: 080123d1 .word 0x080123d1 80122e0: 08012363 .word 0x08012363 80122e4: 080123d1 .word 0x080123d1 80122e8: 080123d1 .word 0x080123d1 80122ec: 080123d1 .word 0x080123d1 80122f0: 08012373 .word 0x08012373 80122f4: 080123d1 .word 0x080123d1 80122f8: 080123d1 .word 0x080123d1 80122fc: 080123d1 .word 0x080123d1 8012300: 080123d1 .word 0x080123d1 8012304: 080123d1 .word 0x080123d1 8012308: 080123d1 .word 0x080123d1 801230c: 080123d1 .word 0x080123d1 8012310: 08012383 .word 0x08012383 8012314: 080123d1 .word 0x080123d1 8012318: 080123d1 .word 0x080123d1 801231c: 080123d1 .word 0x080123d1 8012320: 080123d1 .word 0x080123d1 8012324: 080123d1 .word 0x080123d1 8012328: 080123d1 .word 0x080123d1 801232c: 080123d1 .word 0x080123d1 8012330: 080123d1 .word 0x080123d1 8012334: 080123d1 .word 0x080123d1 8012338: 080123d1 .word 0x080123d1 801233c: 080123d1 .word 0x080123d1 8012340: 080123d1 .word 0x080123d1 8012344: 080123d1 .word 0x080123d1 8012348: 080123d1 .word 0x080123d1 801234c: 080123d1 .word 0x080123d1 8012350: 080123c3 .word 0x080123c3 8012354: 2b40 cmp r3, #64 @ 0x40 8012356: d037 beq.n 80123c8 8012358: e03a b.n 80123d0 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 801235a: f7fc fa8b bl 800e874 801235e: 63f8 str r0, [r7, #60] @ 0x3c break; 8012360: e03c b.n 80123dc case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8012362: f107 0324 add.w r3, r7, #36 @ 0x24 8012366: 4618 mov r0, r3 8012368: f7fc fa9a bl 800e8a0 pclk = pll2_clocks.PLL2_Q_Frequency; 801236c: 6abb ldr r3, [r7, #40] @ 0x28 801236e: 63fb str r3, [r7, #60] @ 0x3c break; 8012370: e034 b.n 80123dc case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8012372: f107 0318 add.w r3, r7, #24 8012376: 4618 mov r0, r3 8012378: f7fc fbe6 bl 800eb48 pclk = pll3_clocks.PLL3_Q_Frequency; 801237c: 69fb ldr r3, [r7, #28] 801237e: 63fb str r3, [r7, #60] @ 0x3c break; 8012380: e02c b.n 80123dc case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8012382: 4b09 ldr r3, [pc, #36] @ (80123a8 ) 8012384: 681b ldr r3, [r3, #0] 8012386: f003 0320 and.w r3, r3, #32 801238a: 2b00 cmp r3, #0 801238c: d016 beq.n 80123bc { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 801238e: 4b06 ldr r3, [pc, #24] @ (80123a8 ) 8012390: 681b ldr r3, [r3, #0] 8012392: 08db lsrs r3, r3, #3 8012394: f003 0303 and.w r3, r3, #3 8012398: 4a07 ldr r2, [pc, #28] @ (80123b8 ) 801239a: fa22 f303 lsr.w r3, r2, r3 801239e: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80123a0: e01c b.n 80123dc 80123a2: bf00 nop 80123a4: 40011400 .word 0x40011400 80123a8: 58024400 .word 0x58024400 80123ac: 40007800 .word 0x40007800 80123b0: 40007c00 .word 0x40007c00 80123b4: 58000c00 .word 0x58000c00 80123b8: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 80123bc: 4b9d ldr r3, [pc, #628] @ (8012634 ) 80123be: 63fb str r3, [r7, #60] @ 0x3c break; 80123c0: e00c b.n 80123dc case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80123c2: 4b9d ldr r3, [pc, #628] @ (8012638 ) 80123c4: 63fb str r3, [r7, #60] @ 0x3c break; 80123c6: e009 b.n 80123dc case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80123c8: f44f 4300 mov.w r3, #32768 @ 0x8000 80123cc: 63fb str r3, [r7, #60] @ 0x3c break; 80123ce: e005 b.n 80123dc default: pclk = 0U; 80123d0: 2300 movs r3, #0 80123d2: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80123d4: 2301 movs r3, #1 80123d6: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80123da: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 80123dc: 6bfb ldr r3, [r7, #60] @ 0x3c 80123de: 2b00 cmp r3, #0 80123e0: f000 81de beq.w 80127a0 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 80123e4: 697b ldr r3, [r7, #20] 80123e6: 6a5b ldr r3, [r3, #36] @ 0x24 80123e8: 4a94 ldr r2, [pc, #592] @ (801263c ) 80123ea: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80123ee: 461a mov r2, r3 80123f0: 6bfb ldr r3, [r7, #60] @ 0x3c 80123f2: fbb3 f3f2 udiv r3, r3, r2 80123f6: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 80123f8: 697b ldr r3, [r7, #20] 80123fa: 685a ldr r2, [r3, #4] 80123fc: 4613 mov r3, r2 80123fe: 005b lsls r3, r3, #1 8012400: 4413 add r3, r2 8012402: 6b3a ldr r2, [r7, #48] @ 0x30 8012404: 429a cmp r2, r3 8012406: d305 bcc.n 8012414 (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8012408: 697b ldr r3, [r7, #20] 801240a: 685b ldr r3, [r3, #4] 801240c: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 801240e: 6b3a ldr r2, [r7, #48] @ 0x30 8012410: 429a cmp r2, r3 8012412: d903 bls.n 801241c { ret = HAL_ERROR; 8012414: 2301 movs r3, #1 8012416: f887 3042 strb.w r3, [r7, #66] @ 0x42 801241a: e1c1 b.n 80127a0 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 801241c: 6bfb ldr r3, [r7, #60] @ 0x3c 801241e: 2200 movs r2, #0 8012420: 60bb str r3, [r7, #8] 8012422: 60fa str r2, [r7, #12] 8012424: 697b ldr r3, [r7, #20] 8012426: 6a5b ldr r3, [r3, #36] @ 0x24 8012428: 4a84 ldr r2, [pc, #528] @ (801263c ) 801242a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 801242e: b29b uxth r3, r3 8012430: 2200 movs r2, #0 8012432: 603b str r3, [r7, #0] 8012434: 607a str r2, [r7, #4] 8012436: e9d7 2300 ldrd r2, r3, [r7] 801243a: e9d7 0102 ldrd r0, r1, [r7, #8] 801243e: f7ed ff4f bl 80002e0 <__aeabi_uldivmod> 8012442: 4602 mov r2, r0 8012444: 460b mov r3, r1 8012446: 4610 mov r0, r2 8012448: 4619 mov r1, r3 801244a: f04f 0200 mov.w r2, #0 801244e: f04f 0300 mov.w r3, #0 8012452: 020b lsls r3, r1, #8 8012454: ea43 6310 orr.w r3, r3, r0, lsr #24 8012458: 0202 lsls r2, r0, #8 801245a: 6979 ldr r1, [r7, #20] 801245c: 6849 ldr r1, [r1, #4] 801245e: 0849 lsrs r1, r1, #1 8012460: 2000 movs r0, #0 8012462: 460c mov r4, r1 8012464: 4605 mov r5, r0 8012466: eb12 0804 adds.w r8, r2, r4 801246a: eb43 0905 adc.w r9, r3, r5 801246e: 697b ldr r3, [r7, #20] 8012470: 685b ldr r3, [r3, #4] 8012472: 2200 movs r2, #0 8012474: 469a mov sl, r3 8012476: 4693 mov fp, r2 8012478: 4652 mov r2, sl 801247a: 465b mov r3, fp 801247c: 4640 mov r0, r8 801247e: 4649 mov r1, r9 8012480: f7ed ff2e bl 80002e0 <__aeabi_uldivmod> 8012484: 4602 mov r2, r0 8012486: 460b mov r3, r1 8012488: 4613 mov r3, r2 801248a: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 801248c: 6bbb ldr r3, [r7, #56] @ 0x38 801248e: f5b3 7f40 cmp.w r3, #768 @ 0x300 8012492: d308 bcc.n 80124a6 8012494: 6bbb ldr r3, [r7, #56] @ 0x38 8012496: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 801249a: d204 bcs.n 80124a6 { huart->Instance->BRR = usartdiv; 801249c: 697b ldr r3, [r7, #20] 801249e: 681b ldr r3, [r3, #0] 80124a0: 6bba ldr r2, [r7, #56] @ 0x38 80124a2: 60da str r2, [r3, #12] 80124a4: e17c b.n 80127a0 } else { ret = HAL_ERROR; 80124a6: 2301 movs r3, #1 80124a8: f887 3042 strb.w r3, [r7, #66] @ 0x42 80124ac: e178 b.n 80127a0 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 80124ae: 697b ldr r3, [r7, #20] 80124b0: 69db ldr r3, [r3, #28] 80124b2: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80124b6: f040 80c5 bne.w 8012644 { switch (clocksource) 80124ba: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80124be: 2b20 cmp r3, #32 80124c0: dc48 bgt.n 8012554 80124c2: 2b00 cmp r3, #0 80124c4: db7b blt.n 80125be 80124c6: 2b20 cmp r3, #32 80124c8: d879 bhi.n 80125be 80124ca: a201 add r2, pc, #4 @ (adr r2, 80124d0 ) 80124cc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80124d0: 0801255b .word 0x0801255b 80124d4: 08012563 .word 0x08012563 80124d8: 080125bf .word 0x080125bf 80124dc: 080125bf .word 0x080125bf 80124e0: 0801256b .word 0x0801256b 80124e4: 080125bf .word 0x080125bf 80124e8: 080125bf .word 0x080125bf 80124ec: 080125bf .word 0x080125bf 80124f0: 0801257b .word 0x0801257b 80124f4: 080125bf .word 0x080125bf 80124f8: 080125bf .word 0x080125bf 80124fc: 080125bf .word 0x080125bf 8012500: 080125bf .word 0x080125bf 8012504: 080125bf .word 0x080125bf 8012508: 080125bf .word 0x080125bf 801250c: 080125bf .word 0x080125bf 8012510: 0801258b .word 0x0801258b 8012514: 080125bf .word 0x080125bf 8012518: 080125bf .word 0x080125bf 801251c: 080125bf .word 0x080125bf 8012520: 080125bf .word 0x080125bf 8012524: 080125bf .word 0x080125bf 8012528: 080125bf .word 0x080125bf 801252c: 080125bf .word 0x080125bf 8012530: 080125bf .word 0x080125bf 8012534: 080125bf .word 0x080125bf 8012538: 080125bf .word 0x080125bf 801253c: 080125bf .word 0x080125bf 8012540: 080125bf .word 0x080125bf 8012544: 080125bf .word 0x080125bf 8012548: 080125bf .word 0x080125bf 801254c: 080125bf .word 0x080125bf 8012550: 080125b1 .word 0x080125b1 8012554: 2b40 cmp r3, #64 @ 0x40 8012556: d02e beq.n 80125b6 8012558: e031 b.n 80125be { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 801255a: f7fa f9af bl 800c8bc 801255e: 63f8 str r0, [r7, #60] @ 0x3c break; 8012560: e033 b.n 80125ca case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 8012562: f7fa f9c1 bl 800c8e8 8012566: 63f8 str r0, [r7, #60] @ 0x3c break; 8012568: e02f b.n 80125ca case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 801256a: f107 0324 add.w r3, r7, #36 @ 0x24 801256e: 4618 mov r0, r3 8012570: f7fc f996 bl 800e8a0 pclk = pll2_clocks.PLL2_Q_Frequency; 8012574: 6abb ldr r3, [r7, #40] @ 0x28 8012576: 63fb str r3, [r7, #60] @ 0x3c break; 8012578: e027 b.n 80125ca case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 801257a: f107 0318 add.w r3, r7, #24 801257e: 4618 mov r0, r3 8012580: f7fc fae2 bl 800eb48 pclk = pll3_clocks.PLL3_Q_Frequency; 8012584: 69fb ldr r3, [r7, #28] 8012586: 63fb str r3, [r7, #60] @ 0x3c break; 8012588: e01f b.n 80125ca case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 801258a: 4b2d ldr r3, [pc, #180] @ (8012640 ) 801258c: 681b ldr r3, [r3, #0] 801258e: f003 0320 and.w r3, r3, #32 8012592: 2b00 cmp r3, #0 8012594: d009 beq.n 80125aa { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8012596: 4b2a ldr r3, [pc, #168] @ (8012640 ) 8012598: 681b ldr r3, [r3, #0] 801259a: 08db lsrs r3, r3, #3 801259c: f003 0303 and.w r3, r3, #3 80125a0: 4a24 ldr r2, [pc, #144] @ (8012634 ) 80125a2: fa22 f303 lsr.w r3, r2, r3 80125a6: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80125a8: e00f b.n 80125ca pclk = (uint32_t) HSI_VALUE; 80125aa: 4b22 ldr r3, [pc, #136] @ (8012634 ) 80125ac: 63fb str r3, [r7, #60] @ 0x3c break; 80125ae: e00c b.n 80125ca case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80125b0: 4b21 ldr r3, [pc, #132] @ (8012638 ) 80125b2: 63fb str r3, [r7, #60] @ 0x3c break; 80125b4: e009 b.n 80125ca case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80125b6: f44f 4300 mov.w r3, #32768 @ 0x8000 80125ba: 63fb str r3, [r7, #60] @ 0x3c break; 80125bc: e005 b.n 80125ca default: pclk = 0U; 80125be: 2300 movs r3, #0 80125c0: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80125c2: 2301 movs r3, #1 80125c4: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80125c8: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 80125ca: 6bfb ldr r3, [r7, #60] @ 0x3c 80125cc: 2b00 cmp r3, #0 80125ce: f000 80e7 beq.w 80127a0 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80125d2: 697b ldr r3, [r7, #20] 80125d4: 6a5b ldr r3, [r3, #36] @ 0x24 80125d6: 4a19 ldr r2, [pc, #100] @ (801263c ) 80125d8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80125dc: 461a mov r2, r3 80125de: 6bfb ldr r3, [r7, #60] @ 0x3c 80125e0: fbb3 f3f2 udiv r3, r3, r2 80125e4: 005a lsls r2, r3, #1 80125e6: 697b ldr r3, [r7, #20] 80125e8: 685b ldr r3, [r3, #4] 80125ea: 085b lsrs r3, r3, #1 80125ec: 441a add r2, r3 80125ee: 697b ldr r3, [r7, #20] 80125f0: 685b ldr r3, [r3, #4] 80125f2: fbb2 f3f3 udiv r3, r2, r3 80125f6: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 80125f8: 6bbb ldr r3, [r7, #56] @ 0x38 80125fa: 2b0f cmp r3, #15 80125fc: d916 bls.n 801262c 80125fe: 6bbb ldr r3, [r7, #56] @ 0x38 8012600: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8012604: d212 bcs.n 801262c { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8012606: 6bbb ldr r3, [r7, #56] @ 0x38 8012608: b29b uxth r3, r3 801260a: f023 030f bic.w r3, r3, #15 801260e: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8012610: 6bbb ldr r3, [r7, #56] @ 0x38 8012612: 085b lsrs r3, r3, #1 8012614: b29b uxth r3, r3 8012616: f003 0307 and.w r3, r3, #7 801261a: b29a uxth r2, r3 801261c: 8efb ldrh r3, [r7, #54] @ 0x36 801261e: 4313 orrs r3, r2 8012620: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 8012622: 697b ldr r3, [r7, #20] 8012624: 681b ldr r3, [r3, #0] 8012626: 8efa ldrh r2, [r7, #54] @ 0x36 8012628: 60da str r2, [r3, #12] 801262a: e0b9 b.n 80127a0 } else { ret = HAL_ERROR; 801262c: 2301 movs r3, #1 801262e: f887 3042 strb.w r3, [r7, #66] @ 0x42 8012632: e0b5 b.n 80127a0 8012634: 03d09000 .word 0x03d09000 8012638: 003d0900 .word 0x003d0900 801263c: 08018714 .word 0x08018714 8012640: 58024400 .word 0x58024400 } } } else { switch (clocksource) 8012644: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8012648: 2b20 cmp r3, #32 801264a: dc49 bgt.n 80126e0 801264c: 2b00 cmp r3, #0 801264e: db7c blt.n 801274a 8012650: 2b20 cmp r3, #32 8012652: d87a bhi.n 801274a 8012654: a201 add r2, pc, #4 @ (adr r2, 801265c ) 8012656: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801265a: bf00 nop 801265c: 080126e7 .word 0x080126e7 8012660: 080126ef .word 0x080126ef 8012664: 0801274b .word 0x0801274b 8012668: 0801274b .word 0x0801274b 801266c: 080126f7 .word 0x080126f7 8012670: 0801274b .word 0x0801274b 8012674: 0801274b .word 0x0801274b 8012678: 0801274b .word 0x0801274b 801267c: 08012707 .word 0x08012707 8012680: 0801274b .word 0x0801274b 8012684: 0801274b .word 0x0801274b 8012688: 0801274b .word 0x0801274b 801268c: 0801274b .word 0x0801274b 8012690: 0801274b .word 0x0801274b 8012694: 0801274b .word 0x0801274b 8012698: 0801274b .word 0x0801274b 801269c: 08012717 .word 0x08012717 80126a0: 0801274b .word 0x0801274b 80126a4: 0801274b .word 0x0801274b 80126a8: 0801274b .word 0x0801274b 80126ac: 0801274b .word 0x0801274b 80126b0: 0801274b .word 0x0801274b 80126b4: 0801274b .word 0x0801274b 80126b8: 0801274b .word 0x0801274b 80126bc: 0801274b .word 0x0801274b 80126c0: 0801274b .word 0x0801274b 80126c4: 0801274b .word 0x0801274b 80126c8: 0801274b .word 0x0801274b 80126cc: 0801274b .word 0x0801274b 80126d0: 0801274b .word 0x0801274b 80126d4: 0801274b .word 0x0801274b 80126d8: 0801274b .word 0x0801274b 80126dc: 0801273d .word 0x0801273d 80126e0: 2b40 cmp r3, #64 @ 0x40 80126e2: d02e beq.n 8012742 80126e4: e031 b.n 801274a { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80126e6: f7fa f8e9 bl 800c8bc 80126ea: 63f8 str r0, [r7, #60] @ 0x3c break; 80126ec: e033 b.n 8012756 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 80126ee: f7fa f8fb bl 800c8e8 80126f2: 63f8 str r0, [r7, #60] @ 0x3c break; 80126f4: e02f b.n 8012756 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80126f6: f107 0324 add.w r3, r7, #36 @ 0x24 80126fa: 4618 mov r0, r3 80126fc: f7fc f8d0 bl 800e8a0 pclk = pll2_clocks.PLL2_Q_Frequency; 8012700: 6abb ldr r3, [r7, #40] @ 0x28 8012702: 63fb str r3, [r7, #60] @ 0x3c break; 8012704: e027 b.n 8012756 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8012706: f107 0318 add.w r3, r7, #24 801270a: 4618 mov r0, r3 801270c: f7fc fa1c bl 800eb48 pclk = pll3_clocks.PLL3_Q_Frequency; 8012710: 69fb ldr r3, [r7, #28] 8012712: 63fb str r3, [r7, #60] @ 0x3c break; 8012714: e01f b.n 8012756 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8012716: 4b2d ldr r3, [pc, #180] @ (80127cc ) 8012718: 681b ldr r3, [r3, #0] 801271a: f003 0320 and.w r3, r3, #32 801271e: 2b00 cmp r3, #0 8012720: d009 beq.n 8012736 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8012722: 4b2a ldr r3, [pc, #168] @ (80127cc ) 8012724: 681b ldr r3, [r3, #0] 8012726: 08db lsrs r3, r3, #3 8012728: f003 0303 and.w r3, r3, #3 801272c: 4a28 ldr r2, [pc, #160] @ (80127d0 ) 801272e: fa22 f303 lsr.w r3, r2, r3 8012732: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 8012734: e00f b.n 8012756 pclk = (uint32_t) HSI_VALUE; 8012736: 4b26 ldr r3, [pc, #152] @ (80127d0 ) 8012738: 63fb str r3, [r7, #60] @ 0x3c break; 801273a: e00c b.n 8012756 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 801273c: 4b25 ldr r3, [pc, #148] @ (80127d4 ) 801273e: 63fb str r3, [r7, #60] @ 0x3c break; 8012740: e009 b.n 8012756 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8012742: f44f 4300 mov.w r3, #32768 @ 0x8000 8012746: 63fb str r3, [r7, #60] @ 0x3c break; 8012748: e005 b.n 8012756 default: pclk = 0U; 801274a: 2300 movs r3, #0 801274c: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 801274e: 2301 movs r3, #1 8012750: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 8012754: bf00 nop } if (pclk != 0U) 8012756: 6bfb ldr r3, [r7, #60] @ 0x3c 8012758: 2b00 cmp r3, #0 801275a: d021 beq.n 80127a0 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 801275c: 697b ldr r3, [r7, #20] 801275e: 6a5b ldr r3, [r3, #36] @ 0x24 8012760: 4a1d ldr r2, [pc, #116] @ (80127d8 ) 8012762: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8012766: 461a mov r2, r3 8012768: 6bfb ldr r3, [r7, #60] @ 0x3c 801276a: fbb3 f2f2 udiv r2, r3, r2 801276e: 697b ldr r3, [r7, #20] 8012770: 685b ldr r3, [r3, #4] 8012772: 085b lsrs r3, r3, #1 8012774: 441a add r2, r3 8012776: 697b ldr r3, [r7, #20] 8012778: 685b ldr r3, [r3, #4] 801277a: fbb2 f3f3 udiv r3, r2, r3 801277e: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8012780: 6bbb ldr r3, [r7, #56] @ 0x38 8012782: 2b0f cmp r3, #15 8012784: d909 bls.n 801279a 8012786: 6bbb ldr r3, [r7, #56] @ 0x38 8012788: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801278c: d205 bcs.n 801279a { huart->Instance->BRR = (uint16_t)usartdiv; 801278e: 6bbb ldr r3, [r7, #56] @ 0x38 8012790: b29a uxth r2, r3 8012792: 697b ldr r3, [r7, #20] 8012794: 681b ldr r3, [r3, #0] 8012796: 60da str r2, [r3, #12] 8012798: e002 b.n 80127a0 } else { ret = HAL_ERROR; 801279a: 2301 movs r3, #1 801279c: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 80127a0: 697b ldr r3, [r7, #20] 80127a2: 2201 movs r2, #1 80127a4: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 80127a8: 697b ldr r3, [r7, #20] 80127aa: 2201 movs r2, #1 80127ac: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 80127b0: 697b ldr r3, [r7, #20] 80127b2: 2200 movs r2, #0 80127b4: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 80127b6: 697b ldr r3, [r7, #20] 80127b8: 2200 movs r2, #0 80127ba: 679a str r2, [r3, #120] @ 0x78 return ret; 80127bc: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 80127c0: 4618 mov r0, r3 80127c2: 3748 adds r7, #72 @ 0x48 80127c4: 46bd mov sp, r7 80127c6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80127ca: bf00 nop 80127cc: 58024400 .word 0x58024400 80127d0: 03d09000 .word 0x03d09000 80127d4: 003d0900 .word 0x003d0900 80127d8: 08018714 .word 0x08018714 080127dc : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 80127dc: b480 push {r7} 80127de: b083 sub sp, #12 80127e0: af00 add r7, sp, #0 80127e2: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 80127e4: 687b ldr r3, [r7, #4] 80127e6: 6a9b ldr r3, [r3, #40] @ 0x28 80127e8: f003 0308 and.w r3, r3, #8 80127ec: 2b00 cmp r3, #0 80127ee: d00a beq.n 8012806 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 80127f0: 687b ldr r3, [r7, #4] 80127f2: 681b ldr r3, [r3, #0] 80127f4: 685b ldr r3, [r3, #4] 80127f6: f423 4100 bic.w r1, r3, #32768 @ 0x8000 80127fa: 687b ldr r3, [r7, #4] 80127fc: 6b9a ldr r2, [r3, #56] @ 0x38 80127fe: 687b ldr r3, [r7, #4] 8012800: 681b ldr r3, [r3, #0] 8012802: 430a orrs r2, r1 8012804: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 8012806: 687b ldr r3, [r7, #4] 8012808: 6a9b ldr r3, [r3, #40] @ 0x28 801280a: f003 0301 and.w r3, r3, #1 801280e: 2b00 cmp r3, #0 8012810: d00a beq.n 8012828 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8012812: 687b ldr r3, [r7, #4] 8012814: 681b ldr r3, [r3, #0] 8012816: 685b ldr r3, [r3, #4] 8012818: f423 3100 bic.w r1, r3, #131072 @ 0x20000 801281c: 687b ldr r3, [r7, #4] 801281e: 6ada ldr r2, [r3, #44] @ 0x2c 8012820: 687b ldr r3, [r7, #4] 8012822: 681b ldr r3, [r3, #0] 8012824: 430a orrs r2, r1 8012826: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8012828: 687b ldr r3, [r7, #4] 801282a: 6a9b ldr r3, [r3, #40] @ 0x28 801282c: f003 0302 and.w r3, r3, #2 8012830: 2b00 cmp r3, #0 8012832: d00a beq.n 801284a { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8012834: 687b ldr r3, [r7, #4] 8012836: 681b ldr r3, [r3, #0] 8012838: 685b ldr r3, [r3, #4] 801283a: f423 3180 bic.w r1, r3, #65536 @ 0x10000 801283e: 687b ldr r3, [r7, #4] 8012840: 6b1a ldr r2, [r3, #48] @ 0x30 8012842: 687b ldr r3, [r7, #4] 8012844: 681b ldr r3, [r3, #0] 8012846: 430a orrs r2, r1 8012848: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 801284a: 687b ldr r3, [r7, #4] 801284c: 6a9b ldr r3, [r3, #40] @ 0x28 801284e: f003 0304 and.w r3, r3, #4 8012852: 2b00 cmp r3, #0 8012854: d00a beq.n 801286c { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8012856: 687b ldr r3, [r7, #4] 8012858: 681b ldr r3, [r3, #0] 801285a: 685b ldr r3, [r3, #4] 801285c: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8012860: 687b ldr r3, [r7, #4] 8012862: 6b5a ldr r2, [r3, #52] @ 0x34 8012864: 687b ldr r3, [r7, #4] 8012866: 681b ldr r3, [r3, #0] 8012868: 430a orrs r2, r1 801286a: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 801286c: 687b ldr r3, [r7, #4] 801286e: 6a9b ldr r3, [r3, #40] @ 0x28 8012870: f003 0310 and.w r3, r3, #16 8012874: 2b00 cmp r3, #0 8012876: d00a beq.n 801288e { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8012878: 687b ldr r3, [r7, #4] 801287a: 681b ldr r3, [r3, #0] 801287c: 689b ldr r3, [r3, #8] 801287e: f423 5180 bic.w r1, r3, #4096 @ 0x1000 8012882: 687b ldr r3, [r7, #4] 8012884: 6bda ldr r2, [r3, #60] @ 0x3c 8012886: 687b ldr r3, [r7, #4] 8012888: 681b ldr r3, [r3, #0] 801288a: 430a orrs r2, r1 801288c: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 801288e: 687b ldr r3, [r7, #4] 8012890: 6a9b ldr r3, [r3, #40] @ 0x28 8012892: f003 0320 and.w r3, r3, #32 8012896: 2b00 cmp r3, #0 8012898: d00a beq.n 80128b0 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 801289a: 687b ldr r3, [r7, #4] 801289c: 681b ldr r3, [r3, #0] 801289e: 689b ldr r3, [r3, #8] 80128a0: f423 5100 bic.w r1, r3, #8192 @ 0x2000 80128a4: 687b ldr r3, [r7, #4] 80128a6: 6c1a ldr r2, [r3, #64] @ 0x40 80128a8: 687b ldr r3, [r7, #4] 80128aa: 681b ldr r3, [r3, #0] 80128ac: 430a orrs r2, r1 80128ae: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 80128b0: 687b ldr r3, [r7, #4] 80128b2: 6a9b ldr r3, [r3, #40] @ 0x28 80128b4: f003 0340 and.w r3, r3, #64 @ 0x40 80128b8: 2b00 cmp r3, #0 80128ba: d01a beq.n 80128f2 { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 80128bc: 687b ldr r3, [r7, #4] 80128be: 681b ldr r3, [r3, #0] 80128c0: 685b ldr r3, [r3, #4] 80128c2: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 80128c6: 687b ldr r3, [r7, #4] 80128c8: 6c5a ldr r2, [r3, #68] @ 0x44 80128ca: 687b ldr r3, [r7, #4] 80128cc: 681b ldr r3, [r3, #0] 80128ce: 430a orrs r2, r1 80128d0: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 80128d2: 687b ldr r3, [r7, #4] 80128d4: 6c5b ldr r3, [r3, #68] @ 0x44 80128d6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80128da: d10a bne.n 80128f2 { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 80128dc: 687b ldr r3, [r7, #4] 80128de: 681b ldr r3, [r3, #0] 80128e0: 685b ldr r3, [r3, #4] 80128e2: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 80128e6: 687b ldr r3, [r7, #4] 80128e8: 6c9a ldr r2, [r3, #72] @ 0x48 80128ea: 687b ldr r3, [r7, #4] 80128ec: 681b ldr r3, [r3, #0] 80128ee: 430a orrs r2, r1 80128f0: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 80128f2: 687b ldr r3, [r7, #4] 80128f4: 6a9b ldr r3, [r3, #40] @ 0x28 80128f6: f003 0380 and.w r3, r3, #128 @ 0x80 80128fa: 2b00 cmp r3, #0 80128fc: d00a beq.n 8012914 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 80128fe: 687b ldr r3, [r7, #4] 8012900: 681b ldr r3, [r3, #0] 8012902: 685b ldr r3, [r3, #4] 8012904: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8012908: 687b ldr r3, [r7, #4] 801290a: 6cda ldr r2, [r3, #76] @ 0x4c 801290c: 687b ldr r3, [r7, #4] 801290e: 681b ldr r3, [r3, #0] 8012910: 430a orrs r2, r1 8012912: 605a str r2, [r3, #4] } } 8012914: bf00 nop 8012916: 370c adds r7, #12 8012918: 46bd mov sp, r7 801291a: f85d 7b04 ldr.w r7, [sp], #4 801291e: 4770 bx lr 08012920 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8012920: b580 push {r7, lr} 8012922: b098 sub sp, #96 @ 0x60 8012924: af02 add r7, sp, #8 8012926: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012928: 687b ldr r3, [r7, #4] 801292a: 2200 movs r2, #0 801292c: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8012930: f7f3 fa74 bl 8005e1c 8012934: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8012936: 687b ldr r3, [r7, #4] 8012938: 681b ldr r3, [r3, #0] 801293a: 681b ldr r3, [r3, #0] 801293c: f003 0308 and.w r3, r3, #8 8012940: 2b08 cmp r3, #8 8012942: d12f bne.n 80129a4 { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8012944: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8012948: 9300 str r3, [sp, #0] 801294a: 6d7b ldr r3, [r7, #84] @ 0x54 801294c: 2200 movs r2, #0 801294e: f44f 1100 mov.w r1, #2097152 @ 0x200000 8012952: 6878 ldr r0, [r7, #4] 8012954: f000 f88e bl 8012a74 8012958: 4603 mov r3, r0 801295a: 2b00 cmp r3, #0 801295c: d022 beq.n 80129a4 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 801295e: 687b ldr r3, [r7, #4] 8012960: 681b ldr r3, [r3, #0] 8012962: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012964: 6bbb ldr r3, [r7, #56] @ 0x38 8012966: e853 3f00 ldrex r3, [r3] 801296a: 637b str r3, [r7, #52] @ 0x34 return(result); 801296c: 6b7b ldr r3, [r7, #52] @ 0x34 801296e: f023 0380 bic.w r3, r3, #128 @ 0x80 8012972: 653b str r3, [r7, #80] @ 0x50 8012974: 687b ldr r3, [r7, #4] 8012976: 681b ldr r3, [r3, #0] 8012978: 461a mov r2, r3 801297a: 6d3b ldr r3, [r7, #80] @ 0x50 801297c: 647b str r3, [r7, #68] @ 0x44 801297e: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012980: 6c39 ldr r1, [r7, #64] @ 0x40 8012982: 6c7a ldr r2, [r7, #68] @ 0x44 8012984: e841 2300 strex r3, r2, [r1] 8012988: 63fb str r3, [r7, #60] @ 0x3c return(result); 801298a: 6bfb ldr r3, [r7, #60] @ 0x3c 801298c: 2b00 cmp r3, #0 801298e: d1e6 bne.n 801295e huart->gState = HAL_UART_STATE_READY; 8012990: 687b ldr r3, [r7, #4] 8012992: 2220 movs r2, #32 8012994: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 8012998: 687b ldr r3, [r7, #4] 801299a: 2200 movs r2, #0 801299c: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 80129a0: 2303 movs r3, #3 80129a2: e063 b.n 8012a6c } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 80129a4: 687b ldr r3, [r7, #4] 80129a6: 681b ldr r3, [r3, #0] 80129a8: 681b ldr r3, [r3, #0] 80129aa: f003 0304 and.w r3, r3, #4 80129ae: 2b04 cmp r3, #4 80129b0: d149 bne.n 8012a46 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 80129b2: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 80129b6: 9300 str r3, [sp, #0] 80129b8: 6d7b ldr r3, [r7, #84] @ 0x54 80129ba: 2200 movs r2, #0 80129bc: f44f 0180 mov.w r1, #4194304 @ 0x400000 80129c0: 6878 ldr r0, [r7, #4] 80129c2: f000 f857 bl 8012a74 80129c6: 4603 mov r3, r0 80129c8: 2b00 cmp r3, #0 80129ca: d03c beq.n 8012a46 { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80129cc: 687b ldr r3, [r7, #4] 80129ce: 681b ldr r3, [r3, #0] 80129d0: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129d2: 6a7b ldr r3, [r7, #36] @ 0x24 80129d4: e853 3f00 ldrex r3, [r3] 80129d8: 623b str r3, [r7, #32] return(result); 80129da: 6a3b ldr r3, [r7, #32] 80129dc: f423 7390 bic.w r3, r3, #288 @ 0x120 80129e0: 64fb str r3, [r7, #76] @ 0x4c 80129e2: 687b ldr r3, [r7, #4] 80129e4: 681b ldr r3, [r3, #0] 80129e6: 461a mov r2, r3 80129e8: 6cfb ldr r3, [r7, #76] @ 0x4c 80129ea: 633b str r3, [r7, #48] @ 0x30 80129ec: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80129ee: 6af9 ldr r1, [r7, #44] @ 0x2c 80129f0: 6b3a ldr r2, [r7, #48] @ 0x30 80129f2: e841 2300 strex r3, r2, [r1] 80129f6: 62bb str r3, [r7, #40] @ 0x28 return(result); 80129f8: 6abb ldr r3, [r7, #40] @ 0x28 80129fa: 2b00 cmp r3, #0 80129fc: d1e6 bne.n 80129cc ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80129fe: 687b ldr r3, [r7, #4] 8012a00: 681b ldr r3, [r3, #0] 8012a02: 3308 adds r3, #8 8012a04: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a06: 693b ldr r3, [r7, #16] 8012a08: e853 3f00 ldrex r3, [r3] 8012a0c: 60fb str r3, [r7, #12] return(result); 8012a0e: 68fb ldr r3, [r7, #12] 8012a10: f023 0301 bic.w r3, r3, #1 8012a14: 64bb str r3, [r7, #72] @ 0x48 8012a16: 687b ldr r3, [r7, #4] 8012a18: 681b ldr r3, [r3, #0] 8012a1a: 3308 adds r3, #8 8012a1c: 6cba ldr r2, [r7, #72] @ 0x48 8012a1e: 61fa str r2, [r7, #28] 8012a20: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a22: 69b9 ldr r1, [r7, #24] 8012a24: 69fa ldr r2, [r7, #28] 8012a26: e841 2300 strex r3, r2, [r1] 8012a2a: 617b str r3, [r7, #20] return(result); 8012a2c: 697b ldr r3, [r7, #20] 8012a2e: 2b00 cmp r3, #0 8012a30: d1e5 bne.n 80129fe huart->RxState = HAL_UART_STATE_READY; 8012a32: 687b ldr r3, [r7, #4] 8012a34: 2220 movs r2, #32 8012a36: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8012a3a: 687b ldr r3, [r7, #4] 8012a3c: 2200 movs r2, #0 8012a3e: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8012a42: 2303 movs r3, #3 8012a44: e012 b.n 8012a6c } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8012a46: 687b ldr r3, [r7, #4] 8012a48: 2220 movs r2, #32 8012a4a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8012a4e: 687b ldr r3, [r7, #4] 8012a50: 2220 movs r2, #32 8012a52: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012a56: 687b ldr r3, [r7, #4] 8012a58: 2200 movs r2, #0 8012a5a: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8012a5c: 687b ldr r3, [r7, #4] 8012a5e: 2200 movs r2, #0 8012a60: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8012a62: 687b ldr r3, [r7, #4] 8012a64: 2200 movs r2, #0 8012a66: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8012a6a: 2300 movs r3, #0 } 8012a6c: 4618 mov r0, r3 8012a6e: 3758 adds r7, #88 @ 0x58 8012a70: 46bd mov sp, r7 8012a72: bd80 pop {r7, pc} 08012a74 : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8012a74: b580 push {r7, lr} 8012a76: b084 sub sp, #16 8012a78: af00 add r7, sp, #0 8012a7a: 60f8 str r0, [r7, #12] 8012a7c: 60b9 str r1, [r7, #8] 8012a7e: 603b str r3, [r7, #0] 8012a80: 4613 mov r3, r2 8012a82: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012a84: e04f b.n 8012b26 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8012a86: 69bb ldr r3, [r7, #24] 8012a88: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8012a8c: d04b beq.n 8012b26 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8012a8e: f7f3 f9c5 bl 8005e1c 8012a92: 4602 mov r2, r0 8012a94: 683b ldr r3, [r7, #0] 8012a96: 1ad3 subs r3, r2, r3 8012a98: 69ba ldr r2, [r7, #24] 8012a9a: 429a cmp r2, r3 8012a9c: d302 bcc.n 8012aa4 8012a9e: 69bb ldr r3, [r7, #24] 8012aa0: 2b00 cmp r3, #0 8012aa2: d101 bne.n 8012aa8 { return HAL_TIMEOUT; 8012aa4: 2303 movs r3, #3 8012aa6: e04e b.n 8012b46 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8012aa8: 68fb ldr r3, [r7, #12] 8012aaa: 681b ldr r3, [r3, #0] 8012aac: 681b ldr r3, [r3, #0] 8012aae: f003 0304 and.w r3, r3, #4 8012ab2: 2b00 cmp r3, #0 8012ab4: d037 beq.n 8012b26 8012ab6: 68bb ldr r3, [r7, #8] 8012ab8: 2b80 cmp r3, #128 @ 0x80 8012aba: d034 beq.n 8012b26 8012abc: 68bb ldr r3, [r7, #8] 8012abe: 2b40 cmp r3, #64 @ 0x40 8012ac0: d031 beq.n 8012b26 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8012ac2: 68fb ldr r3, [r7, #12] 8012ac4: 681b ldr r3, [r3, #0] 8012ac6: 69db ldr r3, [r3, #28] 8012ac8: f003 0308 and.w r3, r3, #8 8012acc: 2b08 cmp r3, #8 8012ace: d110 bne.n 8012af2 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8012ad0: 68fb ldr r3, [r7, #12] 8012ad2: 681b ldr r3, [r3, #0] 8012ad4: 2208 movs r2, #8 8012ad6: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012ad8: 68f8 ldr r0, [r7, #12] 8012ada: f000 f95b bl 8012d94 huart->ErrorCode = HAL_UART_ERROR_ORE; 8012ade: 68fb ldr r3, [r7, #12] 8012ae0: 2208 movs r2, #8 8012ae2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012ae6: 68fb ldr r3, [r7, #12] 8012ae8: 2200 movs r2, #0 8012aea: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8012aee: 2301 movs r3, #1 8012af0: e029 b.n 8012b46 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8012af2: 68fb ldr r3, [r7, #12] 8012af4: 681b ldr r3, [r3, #0] 8012af6: 69db ldr r3, [r3, #28] 8012af8: f403 6300 and.w r3, r3, #2048 @ 0x800 8012afc: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8012b00: d111 bne.n 8012b26 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8012b02: 68fb ldr r3, [r7, #12] 8012b04: 681b ldr r3, [r3, #0] 8012b06: f44f 6200 mov.w r2, #2048 @ 0x800 8012b0a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012b0c: 68f8 ldr r0, [r7, #12] 8012b0e: f000 f941 bl 8012d94 huart->ErrorCode = HAL_UART_ERROR_RTO; 8012b12: 68fb ldr r3, [r7, #12] 8012b14: 2220 movs r2, #32 8012b16: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012b1a: 68fb ldr r3, [r7, #12] 8012b1c: 2200 movs r2, #0 8012b1e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8012b22: 2303 movs r3, #3 8012b24: e00f b.n 8012b46 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012b26: 68fb ldr r3, [r7, #12] 8012b28: 681b ldr r3, [r3, #0] 8012b2a: 69da ldr r2, [r3, #28] 8012b2c: 68bb ldr r3, [r7, #8] 8012b2e: 4013 ands r3, r2 8012b30: 68ba ldr r2, [r7, #8] 8012b32: 429a cmp r2, r3 8012b34: bf0c ite eq 8012b36: 2301 moveq r3, #1 8012b38: 2300 movne r3, #0 8012b3a: b2db uxtb r3, r3 8012b3c: 461a mov r2, r3 8012b3e: 79fb ldrb r3, [r7, #7] 8012b40: 429a cmp r2, r3 8012b42: d0a0 beq.n 8012a86 } } } } return HAL_OK; 8012b44: 2300 movs r3, #0 } 8012b46: 4618 mov r0, r3 8012b48: 3710 adds r7, #16 8012b4a: 46bd mov sp, r7 8012b4c: bd80 pop {r7, pc} ... 08012b50 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012b50: b480 push {r7} 8012b52: b0a3 sub sp, #140 @ 0x8c 8012b54: af00 add r7, sp, #0 8012b56: 60f8 str r0, [r7, #12] 8012b58: 60b9 str r1, [r7, #8] 8012b5a: 4613 mov r3, r2 8012b5c: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8012b5e: 68fb ldr r3, [r7, #12] 8012b60: 68ba ldr r2, [r7, #8] 8012b62: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8012b64: 68fb ldr r3, [r7, #12] 8012b66: 88fa ldrh r2, [r7, #6] 8012b68: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 8012b6c: 68fb ldr r3, [r7, #12] 8012b6e: 88fa ldrh r2, [r7, #6] 8012b70: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8012b74: 68fb ldr r3, [r7, #12] 8012b76: 2200 movs r2, #0 8012b78: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 8012b7a: 68fb ldr r3, [r7, #12] 8012b7c: 689b ldr r3, [r3, #8] 8012b7e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012b82: d10e bne.n 8012ba2 8012b84: 68fb ldr r3, [r7, #12] 8012b86: 691b ldr r3, [r3, #16] 8012b88: 2b00 cmp r3, #0 8012b8a: d105 bne.n 8012b98 8012b8c: 68fb ldr r3, [r7, #12] 8012b8e: f240 12ff movw r2, #511 @ 0x1ff 8012b92: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012b96: e02d b.n 8012bf4 8012b98: 68fb ldr r3, [r7, #12] 8012b9a: 22ff movs r2, #255 @ 0xff 8012b9c: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012ba0: e028 b.n 8012bf4 8012ba2: 68fb ldr r3, [r7, #12] 8012ba4: 689b ldr r3, [r3, #8] 8012ba6: 2b00 cmp r3, #0 8012ba8: d10d bne.n 8012bc6 8012baa: 68fb ldr r3, [r7, #12] 8012bac: 691b ldr r3, [r3, #16] 8012bae: 2b00 cmp r3, #0 8012bb0: d104 bne.n 8012bbc 8012bb2: 68fb ldr r3, [r7, #12] 8012bb4: 22ff movs r2, #255 @ 0xff 8012bb6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012bba: e01b b.n 8012bf4 8012bbc: 68fb ldr r3, [r7, #12] 8012bbe: 227f movs r2, #127 @ 0x7f 8012bc0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012bc4: e016 b.n 8012bf4 8012bc6: 68fb ldr r3, [r7, #12] 8012bc8: 689b ldr r3, [r3, #8] 8012bca: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8012bce: d10d bne.n 8012bec 8012bd0: 68fb ldr r3, [r7, #12] 8012bd2: 691b ldr r3, [r3, #16] 8012bd4: 2b00 cmp r3, #0 8012bd6: d104 bne.n 8012be2 8012bd8: 68fb ldr r3, [r7, #12] 8012bda: 227f movs r2, #127 @ 0x7f 8012bdc: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012be0: e008 b.n 8012bf4 8012be2: 68fb ldr r3, [r7, #12] 8012be4: 223f movs r2, #63 @ 0x3f 8012be6: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012bea: e003 b.n 8012bf4 8012bec: 68fb ldr r3, [r7, #12] 8012bee: 2200 movs r2, #0 8012bf0: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012bf4: 68fb ldr r3, [r7, #12] 8012bf6: 2200 movs r2, #0 8012bf8: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 8012bfc: 68fb ldr r3, [r7, #12] 8012bfe: 2222 movs r2, #34 @ 0x22 8012c00: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012c04: 68fb ldr r3, [r7, #12] 8012c06: 681b ldr r3, [r3, #0] 8012c08: 3308 adds r3, #8 8012c0a: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c0c: 6e7b ldr r3, [r7, #100] @ 0x64 8012c0e: e853 3f00 ldrex r3, [r3] 8012c12: 663b str r3, [r7, #96] @ 0x60 return(result); 8012c14: 6e3b ldr r3, [r7, #96] @ 0x60 8012c16: f043 0301 orr.w r3, r3, #1 8012c1a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012c1e: 68fb ldr r3, [r7, #12] 8012c20: 681b ldr r3, [r3, #0] 8012c22: 3308 adds r3, #8 8012c24: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012c28: 673a str r2, [r7, #112] @ 0x70 8012c2a: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c2c: 6ef9 ldr r1, [r7, #108] @ 0x6c 8012c2e: 6f3a ldr r2, [r7, #112] @ 0x70 8012c30: e841 2300 strex r3, r2, [r1] 8012c34: 66bb str r3, [r7, #104] @ 0x68 return(result); 8012c36: 6ebb ldr r3, [r7, #104] @ 0x68 8012c38: 2b00 cmp r3, #0 8012c3a: d1e3 bne.n 8012c04 /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 8012c3c: 68fb ldr r3, [r7, #12] 8012c3e: 6e5b ldr r3, [r3, #100] @ 0x64 8012c40: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8012c44: d14f bne.n 8012ce6 8012c46: 68fb ldr r3, [r7, #12] 8012c48: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012c4c: 88fa ldrh r2, [r7, #6] 8012c4e: 429a cmp r2, r3 8012c50: d349 bcc.n 8012ce6 { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012c52: 68fb ldr r3, [r7, #12] 8012c54: 689b ldr r3, [r3, #8] 8012c56: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012c5a: d107 bne.n 8012c6c 8012c5c: 68fb ldr r3, [r7, #12] 8012c5e: 691b ldr r3, [r3, #16] 8012c60: 2b00 cmp r3, #0 8012c62: d103 bne.n 8012c6c { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8012c64: 68fb ldr r3, [r7, #12] 8012c66: 4a47 ldr r2, [pc, #284] @ (8012d84 ) 8012c68: 675a str r2, [r3, #116] @ 0x74 8012c6a: e002 b.n 8012c72 } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 8012c6c: 68fb ldr r3, [r7, #12] 8012c6e: 4a46 ldr r2, [pc, #280] @ (8012d88 ) 8012c70: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012c72: 68fb ldr r3, [r7, #12] 8012c74: 691b ldr r3, [r3, #16] 8012c76: 2b00 cmp r3, #0 8012c78: d01a beq.n 8012cb0 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012c7a: 68fb ldr r3, [r7, #12] 8012c7c: 681b ldr r3, [r3, #0] 8012c7e: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c80: 6d3b ldr r3, [r7, #80] @ 0x50 8012c82: e853 3f00 ldrex r3, [r3] 8012c86: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012c88: 6cfb ldr r3, [r7, #76] @ 0x4c 8012c8a: f443 7380 orr.w r3, r3, #256 @ 0x100 8012c8e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012c92: 68fb ldr r3, [r7, #12] 8012c94: 681b ldr r3, [r3, #0] 8012c96: 461a mov r2, r3 8012c98: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8012c9c: 65fb str r3, [r7, #92] @ 0x5c 8012c9e: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ca0: 6db9 ldr r1, [r7, #88] @ 0x58 8012ca2: 6dfa ldr r2, [r7, #92] @ 0x5c 8012ca4: e841 2300 strex r3, r2, [r1] 8012ca8: 657b str r3, [r7, #84] @ 0x54 return(result); 8012caa: 6d7b ldr r3, [r7, #84] @ 0x54 8012cac: 2b00 cmp r3, #0 8012cae: d1e4 bne.n 8012c7a } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8012cb0: 68fb ldr r3, [r7, #12] 8012cb2: 681b ldr r3, [r3, #0] 8012cb4: 3308 adds r3, #8 8012cb6: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012cb8: 6bfb ldr r3, [r7, #60] @ 0x3c 8012cba: e853 3f00 ldrex r3, [r3] 8012cbe: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012cc0: 6bbb ldr r3, [r7, #56] @ 0x38 8012cc2: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8012cc6: 67fb str r3, [r7, #124] @ 0x7c 8012cc8: 68fb ldr r3, [r7, #12] 8012cca: 681b ldr r3, [r3, #0] 8012ccc: 3308 adds r3, #8 8012cce: 6ffa ldr r2, [r7, #124] @ 0x7c 8012cd0: 64ba str r2, [r7, #72] @ 0x48 8012cd2: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012cd4: 6c79 ldr r1, [r7, #68] @ 0x44 8012cd6: 6cba ldr r2, [r7, #72] @ 0x48 8012cd8: e841 2300 strex r3, r2, [r1] 8012cdc: 643b str r3, [r7, #64] @ 0x40 return(result); 8012cde: 6c3b ldr r3, [r7, #64] @ 0x40 8012ce0: 2b00 cmp r3, #0 8012ce2: d1e5 bne.n 8012cb0 8012ce4: e046 b.n 8012d74 } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012ce6: 68fb ldr r3, [r7, #12] 8012ce8: 689b ldr r3, [r3, #8] 8012cea: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012cee: d107 bne.n 8012d00 8012cf0: 68fb ldr r3, [r7, #12] 8012cf2: 691b ldr r3, [r3, #16] 8012cf4: 2b00 cmp r3, #0 8012cf6: d103 bne.n 8012d00 { huart->RxISR = UART_RxISR_16BIT; 8012cf8: 68fb ldr r3, [r7, #12] 8012cfa: 4a24 ldr r2, [pc, #144] @ (8012d8c ) 8012cfc: 675a str r2, [r3, #116] @ 0x74 8012cfe: e002 b.n 8012d06 } else { huart->RxISR = UART_RxISR_8BIT; 8012d00: 68fb ldr r3, [r7, #12] 8012d02: 4a23 ldr r2, [pc, #140] @ (8012d90 ) 8012d04: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012d06: 68fb ldr r3, [r7, #12] 8012d08: 691b ldr r3, [r3, #16] 8012d0a: 2b00 cmp r3, #0 8012d0c: d019 beq.n 8012d42 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 8012d0e: 68fb ldr r3, [r7, #12] 8012d10: 681b ldr r3, [r3, #0] 8012d12: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d14: 6abb ldr r3, [r7, #40] @ 0x28 8012d16: e853 3f00 ldrex r3, [r3] 8012d1a: 627b str r3, [r7, #36] @ 0x24 return(result); 8012d1c: 6a7b ldr r3, [r7, #36] @ 0x24 8012d1e: f443 7390 orr.w r3, r3, #288 @ 0x120 8012d22: 677b str r3, [r7, #116] @ 0x74 8012d24: 68fb ldr r3, [r7, #12] 8012d26: 681b ldr r3, [r3, #0] 8012d28: 461a mov r2, r3 8012d2a: 6f7b ldr r3, [r7, #116] @ 0x74 8012d2c: 637b str r3, [r7, #52] @ 0x34 8012d2e: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d30: 6b39 ldr r1, [r7, #48] @ 0x30 8012d32: 6b7a ldr r2, [r7, #52] @ 0x34 8012d34: e841 2300 strex r3, r2, [r1] 8012d38: 62fb str r3, [r7, #44] @ 0x2c return(result); 8012d3a: 6afb ldr r3, [r7, #44] @ 0x2c 8012d3c: 2b00 cmp r3, #0 8012d3e: d1e6 bne.n 8012d0e 8012d40: e018 b.n 8012d74 } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012d42: 68fb ldr r3, [r7, #12] 8012d44: 681b ldr r3, [r3, #0] 8012d46: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d48: 697b ldr r3, [r7, #20] 8012d4a: e853 3f00 ldrex r3, [r3] 8012d4e: 613b str r3, [r7, #16] return(result); 8012d50: 693b ldr r3, [r7, #16] 8012d52: f043 0320 orr.w r3, r3, #32 8012d56: 67bb str r3, [r7, #120] @ 0x78 8012d58: 68fb ldr r3, [r7, #12] 8012d5a: 681b ldr r3, [r3, #0] 8012d5c: 461a mov r2, r3 8012d5e: 6fbb ldr r3, [r7, #120] @ 0x78 8012d60: 623b str r3, [r7, #32] 8012d62: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d64: 69f9 ldr r1, [r7, #28] 8012d66: 6a3a ldr r2, [r7, #32] 8012d68: e841 2300 strex r3, r2, [r1] 8012d6c: 61bb str r3, [r7, #24] return(result); 8012d6e: 69bb ldr r3, [r7, #24] 8012d70: 2b00 cmp r3, #0 8012d72: d1e6 bne.n 8012d42 } } return HAL_OK; 8012d74: 2300 movs r3, #0 } 8012d76: 4618 mov r0, r3 8012d78: 378c adds r7, #140 @ 0x8c 8012d7a: 46bd mov sp, r7 8012d7c: f85d 7b04 ldr.w r7, [sp], #4 8012d80: 4770 bx lr 8012d82: bf00 nop 8012d84: 080138f9 .word 0x080138f9 8012d88: 08013599 .word 0x08013599 8012d8c: 080133e1 .word 0x080133e1 8012d90: 08013229 .word 0x08013229 08012d94 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012d94: b480 push {r7} 8012d96: b095 sub sp, #84 @ 0x54 8012d98: af00 add r7, sp, #0 8012d9a: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012d9c: 687b ldr r3, [r7, #4] 8012d9e: 681b ldr r3, [r3, #0] 8012da0: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012da2: 6b7b ldr r3, [r7, #52] @ 0x34 8012da4: e853 3f00 ldrex r3, [r3] 8012da8: 633b str r3, [r7, #48] @ 0x30 return(result); 8012daa: 6b3b ldr r3, [r7, #48] @ 0x30 8012dac: f423 7390 bic.w r3, r3, #288 @ 0x120 8012db0: 64fb str r3, [r7, #76] @ 0x4c 8012db2: 687b ldr r3, [r7, #4] 8012db4: 681b ldr r3, [r3, #0] 8012db6: 461a mov r2, r3 8012db8: 6cfb ldr r3, [r7, #76] @ 0x4c 8012dba: 643b str r3, [r7, #64] @ 0x40 8012dbc: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dbe: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012dc0: 6c3a ldr r2, [r7, #64] @ 0x40 8012dc2: e841 2300 strex r3, r2, [r1] 8012dc6: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012dc8: 6bbb ldr r3, [r7, #56] @ 0x38 8012dca: 2b00 cmp r3, #0 8012dcc: d1e6 bne.n 8012d9c ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012dce: 687b ldr r3, [r7, #4] 8012dd0: 681b ldr r3, [r3, #0] 8012dd2: 3308 adds r3, #8 8012dd4: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012dd6: 6a3b ldr r3, [r7, #32] 8012dd8: e853 3f00 ldrex r3, [r3] 8012ddc: 61fb str r3, [r7, #28] return(result); 8012dde: 69fa ldr r2, [r7, #28] 8012de0: 4b1e ldr r3, [pc, #120] @ (8012e5c ) 8012de2: 4013 ands r3, r2 8012de4: 64bb str r3, [r7, #72] @ 0x48 8012de6: 687b ldr r3, [r7, #4] 8012de8: 681b ldr r3, [r3, #0] 8012dea: 3308 adds r3, #8 8012dec: 6cba ldr r2, [r7, #72] @ 0x48 8012dee: 62fa str r2, [r7, #44] @ 0x2c 8012df0: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012df2: 6ab9 ldr r1, [r7, #40] @ 0x28 8012df4: 6afa ldr r2, [r7, #44] @ 0x2c 8012df6: e841 2300 strex r3, r2, [r1] 8012dfa: 627b str r3, [r7, #36] @ 0x24 return(result); 8012dfc: 6a7b ldr r3, [r7, #36] @ 0x24 8012dfe: 2b00 cmp r3, #0 8012e00: d1e5 bne.n 8012dce /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012e02: 687b ldr r3, [r7, #4] 8012e04: 6edb ldr r3, [r3, #108] @ 0x6c 8012e06: 2b01 cmp r3, #1 8012e08: d118 bne.n 8012e3c { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012e0a: 687b ldr r3, [r7, #4] 8012e0c: 681b ldr r3, [r3, #0] 8012e0e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e10: 68fb ldr r3, [r7, #12] 8012e12: e853 3f00 ldrex r3, [r3] 8012e16: 60bb str r3, [r7, #8] return(result); 8012e18: 68bb ldr r3, [r7, #8] 8012e1a: f023 0310 bic.w r3, r3, #16 8012e1e: 647b str r3, [r7, #68] @ 0x44 8012e20: 687b ldr r3, [r7, #4] 8012e22: 681b ldr r3, [r3, #0] 8012e24: 461a mov r2, r3 8012e26: 6c7b ldr r3, [r7, #68] @ 0x44 8012e28: 61bb str r3, [r7, #24] 8012e2a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012e2c: 6979 ldr r1, [r7, #20] 8012e2e: 69ba ldr r2, [r7, #24] 8012e30: e841 2300 strex r3, r2, [r1] 8012e34: 613b str r3, [r7, #16] return(result); 8012e36: 693b ldr r3, [r7, #16] 8012e38: 2b00 cmp r3, #0 8012e3a: d1e6 bne.n 8012e0a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012e3c: 687b ldr r3, [r7, #4] 8012e3e: 2220 movs r2, #32 8012e40: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012e44: 687b ldr r3, [r7, #4] 8012e46: 2200 movs r2, #0 8012e48: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8012e4a: 687b ldr r3, [r7, #4] 8012e4c: 2200 movs r2, #0 8012e4e: 675a str r2, [r3, #116] @ 0x74 } 8012e50: bf00 nop 8012e52: 3754 adds r7, #84 @ 0x54 8012e54: 46bd mov sp, r7 8012e56: f85d 7b04 ldr.w r7, [sp], #4 8012e5a: 4770 bx lr 8012e5c: effffffe .word 0xeffffffe 08012e60 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012e60: b580 push {r7, lr} 8012e62: b084 sub sp, #16 8012e64: af00 add r7, sp, #0 8012e66: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8012e68: 687b ldr r3, [r7, #4] 8012e6a: 6b9b ldr r3, [r3, #56] @ 0x38 8012e6c: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 8012e6e: 68fb ldr r3, [r7, #12] 8012e70: 2200 movs r2, #0 8012e72: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 8012e76: 68fb ldr r3, [r7, #12] 8012e78: 2200 movs r2, #0 8012e7a: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012e7e: 68f8 ldr r0, [r7, #12] 8012e80: f7fe ff3a bl 8011cf8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012e84: bf00 nop 8012e86: 3710 adds r7, #16 8012e88: 46bd mov sp, r7 8012e8a: bd80 pop {r7, pc} 08012e8c : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 8012e8c: b480 push {r7} 8012e8e: b08f sub sp, #60 @ 0x3c 8012e90: af00 add r7, sp, #0 8012e92: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012e94: 687b ldr r3, [r7, #4] 8012e96: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012e9a: 2b21 cmp r3, #33 @ 0x21 8012e9c: d14c bne.n 8012f38 { if (huart->TxXferCount == 0U) 8012e9e: 687b ldr r3, [r7, #4] 8012ea0: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012ea4: b29b uxth r3, r3 8012ea6: 2b00 cmp r3, #0 8012ea8: d132 bne.n 8012f10 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012eaa: 687b ldr r3, [r7, #4] 8012eac: 681b ldr r3, [r3, #0] 8012eae: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012eb0: 6a3b ldr r3, [r7, #32] 8012eb2: e853 3f00 ldrex r3, [r3] 8012eb6: 61fb str r3, [r7, #28] return(result); 8012eb8: 69fb ldr r3, [r7, #28] 8012eba: f023 0380 bic.w r3, r3, #128 @ 0x80 8012ebe: 637b str r3, [r7, #52] @ 0x34 8012ec0: 687b ldr r3, [r7, #4] 8012ec2: 681b ldr r3, [r3, #0] 8012ec4: 461a mov r2, r3 8012ec6: 6b7b ldr r3, [r7, #52] @ 0x34 8012ec8: 62fb str r3, [r7, #44] @ 0x2c 8012eca: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ecc: 6ab9 ldr r1, [r7, #40] @ 0x28 8012ece: 6afa ldr r2, [r7, #44] @ 0x2c 8012ed0: e841 2300 strex r3, r2, [r1] 8012ed4: 627b str r3, [r7, #36] @ 0x24 return(result); 8012ed6: 6a7b ldr r3, [r7, #36] @ 0x24 8012ed8: 2b00 cmp r3, #0 8012eda: d1e6 bne.n 8012eaa /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012edc: 687b ldr r3, [r7, #4] 8012ede: 681b ldr r3, [r3, #0] 8012ee0: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012ee2: 68fb ldr r3, [r7, #12] 8012ee4: e853 3f00 ldrex r3, [r3] 8012ee8: 60bb str r3, [r7, #8] return(result); 8012eea: 68bb ldr r3, [r7, #8] 8012eec: f043 0340 orr.w r3, r3, #64 @ 0x40 8012ef0: 633b str r3, [r7, #48] @ 0x30 8012ef2: 687b ldr r3, [r7, #4] 8012ef4: 681b ldr r3, [r3, #0] 8012ef6: 461a mov r2, r3 8012ef8: 6b3b ldr r3, [r7, #48] @ 0x30 8012efa: 61bb str r3, [r7, #24] 8012efc: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012efe: 6979 ldr r1, [r7, #20] 8012f00: 69ba ldr r2, [r7, #24] 8012f02: e841 2300 strex r3, r2, [r1] 8012f06: 613b str r3, [r7, #16] return(result); 8012f08: 693b ldr r3, [r7, #16] 8012f0a: 2b00 cmp r3, #0 8012f0c: d1e6 bne.n 8012edc huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 8012f0e: e013 b.n 8012f38 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8012f10: 687b ldr r3, [r7, #4] 8012f12: 6d1b ldr r3, [r3, #80] @ 0x50 8012f14: 781a ldrb r2, [r3, #0] 8012f16: 687b ldr r3, [r7, #4] 8012f18: 681b ldr r3, [r3, #0] 8012f1a: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 8012f1c: 687b ldr r3, [r7, #4] 8012f1e: 6d1b ldr r3, [r3, #80] @ 0x50 8012f20: 1c5a adds r2, r3, #1 8012f22: 687b ldr r3, [r7, #4] 8012f24: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012f26: 687b ldr r3, [r7, #4] 8012f28: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012f2c: b29b uxth r3, r3 8012f2e: 3b01 subs r3, #1 8012f30: b29a uxth r2, r3 8012f32: 687b ldr r3, [r7, #4] 8012f34: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8012f38: bf00 nop 8012f3a: 373c adds r7, #60 @ 0x3c 8012f3c: 46bd mov sp, r7 8012f3e: f85d 7b04 ldr.w r7, [sp], #4 8012f42: 4770 bx lr 08012f44 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 8012f44: b480 push {r7} 8012f46: b091 sub sp, #68 @ 0x44 8012f48: af00 add r7, sp, #0 8012f4a: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012f4c: 687b ldr r3, [r7, #4] 8012f4e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012f52: 2b21 cmp r3, #33 @ 0x21 8012f54: d151 bne.n 8012ffa { if (huart->TxXferCount == 0U) 8012f56: 687b ldr r3, [r7, #4] 8012f58: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012f5c: b29b uxth r3, r3 8012f5e: 2b00 cmp r3, #0 8012f60: d132 bne.n 8012fc8 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012f62: 687b ldr r3, [r7, #4] 8012f64: 681b ldr r3, [r3, #0] 8012f66: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f68: 6a7b ldr r3, [r7, #36] @ 0x24 8012f6a: e853 3f00 ldrex r3, [r3] 8012f6e: 623b str r3, [r7, #32] return(result); 8012f70: 6a3b ldr r3, [r7, #32] 8012f72: f023 0380 bic.w r3, r3, #128 @ 0x80 8012f76: 63bb str r3, [r7, #56] @ 0x38 8012f78: 687b ldr r3, [r7, #4] 8012f7a: 681b ldr r3, [r3, #0] 8012f7c: 461a mov r2, r3 8012f7e: 6bbb ldr r3, [r7, #56] @ 0x38 8012f80: 633b str r3, [r7, #48] @ 0x30 8012f82: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f84: 6af9 ldr r1, [r7, #44] @ 0x2c 8012f86: 6b3a ldr r2, [r7, #48] @ 0x30 8012f88: e841 2300 strex r3, r2, [r1] 8012f8c: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012f8e: 6abb ldr r3, [r7, #40] @ 0x28 8012f90: 2b00 cmp r3, #0 8012f92: d1e6 bne.n 8012f62 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012f94: 687b ldr r3, [r7, #4] 8012f96: 681b ldr r3, [r3, #0] 8012f98: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f9a: 693b ldr r3, [r7, #16] 8012f9c: e853 3f00 ldrex r3, [r3] 8012fa0: 60fb str r3, [r7, #12] return(result); 8012fa2: 68fb ldr r3, [r7, #12] 8012fa4: f043 0340 orr.w r3, r3, #64 @ 0x40 8012fa8: 637b str r3, [r7, #52] @ 0x34 8012faa: 687b ldr r3, [r7, #4] 8012fac: 681b ldr r3, [r3, #0] 8012fae: 461a mov r2, r3 8012fb0: 6b7b ldr r3, [r7, #52] @ 0x34 8012fb2: 61fb str r3, [r7, #28] 8012fb4: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012fb6: 69b9 ldr r1, [r7, #24] 8012fb8: 69fa ldr r2, [r7, #28] 8012fba: e841 2300 strex r3, r2, [r1] 8012fbe: 617b str r3, [r7, #20] return(result); 8012fc0: 697b ldr r3, [r7, #20] 8012fc2: 2b00 cmp r3, #0 8012fc4: d1e6 bne.n 8012f94 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 8012fc6: e018 b.n 8012ffa tmp = (const uint16_t *) huart->pTxBuffPtr; 8012fc8: 687b ldr r3, [r7, #4] 8012fca: 6d1b ldr r3, [r3, #80] @ 0x50 8012fcc: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 8012fce: 6bfb ldr r3, [r7, #60] @ 0x3c 8012fd0: 881b ldrh r3, [r3, #0] 8012fd2: 461a mov r2, r3 8012fd4: 687b ldr r3, [r7, #4] 8012fd6: 681b ldr r3, [r3, #0] 8012fd8: f3c2 0208 ubfx r2, r2, #0, #9 8012fdc: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 8012fde: 687b ldr r3, [r7, #4] 8012fe0: 6d1b ldr r3, [r3, #80] @ 0x50 8012fe2: 1c9a adds r2, r3, #2 8012fe4: 687b ldr r3, [r7, #4] 8012fe6: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012fe8: 687b ldr r3, [r7, #4] 8012fea: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012fee: b29b uxth r3, r3 8012ff0: 3b01 subs r3, #1 8012ff2: b29a uxth r2, r3 8012ff4: 687b ldr r3, [r7, #4] 8012ff6: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8012ffa: bf00 nop 8012ffc: 3744 adds r7, #68 @ 0x44 8012ffe: 46bd mov sp, r7 8013000: f85d 7b04 ldr.w r7, [sp], #4 8013004: 4770 bx lr 08013006 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8013006: b480 push {r7} 8013008: b091 sub sp, #68 @ 0x44 801300a: af00 add r7, sp, #0 801300c: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 801300e: 687b ldr r3, [r7, #4] 8013010: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8013014: 2b21 cmp r3, #33 @ 0x21 8013016: d160 bne.n 80130da { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8013018: 687b ldr r3, [r7, #4] 801301a: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 801301e: 87fb strh r3, [r7, #62] @ 0x3e 8013020: e057 b.n 80130d2 { if (huart->TxXferCount == 0U) 8013022: 687b ldr r3, [r7, #4] 8013024: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013028: b29b uxth r3, r3 801302a: 2b00 cmp r3, #0 801302c: d133 bne.n 8013096 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801302e: 687b ldr r3, [r7, #4] 8013030: 681b ldr r3, [r3, #0] 8013032: 3308 adds r3, #8 8013034: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013036: 6a7b ldr r3, [r7, #36] @ 0x24 8013038: e853 3f00 ldrex r3, [r3] 801303c: 623b str r3, [r7, #32] return(result); 801303e: 6a3b ldr r3, [r7, #32] 8013040: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8013044: 63bb str r3, [r7, #56] @ 0x38 8013046: 687b ldr r3, [r7, #4] 8013048: 681b ldr r3, [r3, #0] 801304a: 3308 adds r3, #8 801304c: 6bba ldr r2, [r7, #56] @ 0x38 801304e: 633a str r2, [r7, #48] @ 0x30 8013050: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013052: 6af9 ldr r1, [r7, #44] @ 0x2c 8013054: 6b3a ldr r2, [r7, #48] @ 0x30 8013056: e841 2300 strex r3, r2, [r1] 801305a: 62bb str r3, [r7, #40] @ 0x28 return(result); 801305c: 6abb ldr r3, [r7, #40] @ 0x28 801305e: 2b00 cmp r3, #0 8013060: d1e5 bne.n 801302e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8013062: 687b ldr r3, [r7, #4] 8013064: 681b ldr r3, [r3, #0] 8013066: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013068: 693b ldr r3, [r7, #16] 801306a: e853 3f00 ldrex r3, [r3] 801306e: 60fb str r3, [r7, #12] return(result); 8013070: 68fb ldr r3, [r7, #12] 8013072: f043 0340 orr.w r3, r3, #64 @ 0x40 8013076: 637b str r3, [r7, #52] @ 0x34 8013078: 687b ldr r3, [r7, #4] 801307a: 681b ldr r3, [r3, #0] 801307c: 461a mov r2, r3 801307e: 6b7b ldr r3, [r7, #52] @ 0x34 8013080: 61fb str r3, [r7, #28] 8013082: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013084: 69b9 ldr r1, [r7, #24] 8013086: 69fa ldr r2, [r7, #28] 8013088: e841 2300 strex r3, r2, [r1] 801308c: 617b str r3, [r7, #20] return(result); 801308e: 697b ldr r3, [r7, #20] 8013090: 2b00 cmp r3, #0 8013092: d1e6 bne.n 8013062 break; /* force exit loop */ 8013094: e021 b.n 80130da } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8013096: 687b ldr r3, [r7, #4] 8013098: 681b ldr r3, [r3, #0] 801309a: 69db ldr r3, [r3, #28] 801309c: f003 0380 and.w r3, r3, #128 @ 0x80 80130a0: 2b00 cmp r3, #0 80130a2: d013 beq.n 80130cc { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 80130a4: 687b ldr r3, [r7, #4] 80130a6: 6d1b ldr r3, [r3, #80] @ 0x50 80130a8: 781a ldrb r2, [r3, #0] 80130aa: 687b ldr r3, [r7, #4] 80130ac: 681b ldr r3, [r3, #0] 80130ae: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 80130b0: 687b ldr r3, [r7, #4] 80130b2: 6d1b ldr r3, [r3, #80] @ 0x50 80130b4: 1c5a adds r2, r3, #1 80130b6: 687b ldr r3, [r7, #4] 80130b8: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80130ba: 687b ldr r3, [r7, #4] 80130bc: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80130c0: b29b uxth r3, r3 80130c2: 3b01 subs r3, #1 80130c4: b29a uxth r2, r3 80130c6: 687b ldr r3, [r7, #4] 80130c8: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80130cc: 8ffb ldrh r3, [r7, #62] @ 0x3e 80130ce: 3b01 subs r3, #1 80130d0: 87fb strh r3, [r7, #62] @ 0x3e 80130d2: 8ffb ldrh r3, [r7, #62] @ 0x3e 80130d4: 2b00 cmp r3, #0 80130d6: d1a4 bne.n 8013022 { /* Nothing to do */ } } } } 80130d8: e7ff b.n 80130da 80130da: bf00 nop 80130dc: 3744 adds r7, #68 @ 0x44 80130de: 46bd mov sp, r7 80130e0: f85d 7b04 ldr.w r7, [sp], #4 80130e4: 4770 bx lr 080130e6 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 80130e6: b480 push {r7} 80130e8: b091 sub sp, #68 @ 0x44 80130ea: af00 add r7, sp, #0 80130ec: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80130ee: 687b ldr r3, [r7, #4] 80130f0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80130f4: 2b21 cmp r3, #33 @ 0x21 80130f6: d165 bne.n 80131c4 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80130f8: 687b ldr r3, [r7, #4] 80130fa: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 80130fe: 87fb strh r3, [r7, #62] @ 0x3e 8013100: e05c b.n 80131bc { if (huart->TxXferCount == 0U) 8013102: 687b ldr r3, [r7, #4] 8013104: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013108: b29b uxth r3, r3 801310a: 2b00 cmp r3, #0 801310c: d133 bne.n 8013176 { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 801310e: 687b ldr r3, [r7, #4] 8013110: 681b ldr r3, [r3, #0] 8013112: 3308 adds r3, #8 8013114: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013116: 6a3b ldr r3, [r7, #32] 8013118: e853 3f00 ldrex r3, [r3] 801311c: 61fb str r3, [r7, #28] return(result); 801311e: 69fb ldr r3, [r7, #28] 8013120: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 8013124: 637b str r3, [r7, #52] @ 0x34 8013126: 687b ldr r3, [r7, #4] 8013128: 681b ldr r3, [r3, #0] 801312a: 3308 adds r3, #8 801312c: 6b7a ldr r2, [r7, #52] @ 0x34 801312e: 62fa str r2, [r7, #44] @ 0x2c 8013130: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013132: 6ab9 ldr r1, [r7, #40] @ 0x28 8013134: 6afa ldr r2, [r7, #44] @ 0x2c 8013136: e841 2300 strex r3, r2, [r1] 801313a: 627b str r3, [r7, #36] @ 0x24 return(result); 801313c: 6a7b ldr r3, [r7, #36] @ 0x24 801313e: 2b00 cmp r3, #0 8013140: d1e5 bne.n 801310e /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8013142: 687b ldr r3, [r7, #4] 8013144: 681b ldr r3, [r3, #0] 8013146: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013148: 68fb ldr r3, [r7, #12] 801314a: e853 3f00 ldrex r3, [r3] 801314e: 60bb str r3, [r7, #8] return(result); 8013150: 68bb ldr r3, [r7, #8] 8013152: f043 0340 orr.w r3, r3, #64 @ 0x40 8013156: 633b str r3, [r7, #48] @ 0x30 8013158: 687b ldr r3, [r7, #4] 801315a: 681b ldr r3, [r3, #0] 801315c: 461a mov r2, r3 801315e: 6b3b ldr r3, [r7, #48] @ 0x30 8013160: 61bb str r3, [r7, #24] 8013162: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013164: 6979 ldr r1, [r7, #20] 8013166: 69ba ldr r2, [r7, #24] 8013168: e841 2300 strex r3, r2, [r1] 801316c: 613b str r3, [r7, #16] return(result); 801316e: 693b ldr r3, [r7, #16] 8013170: 2b00 cmp r3, #0 8013172: d1e6 bne.n 8013142 break; /* force exit loop */ 8013174: e026 b.n 80131c4 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 8013176: 687b ldr r3, [r7, #4] 8013178: 681b ldr r3, [r3, #0] 801317a: 69db ldr r3, [r3, #28] 801317c: f003 0380 and.w r3, r3, #128 @ 0x80 8013180: 2b00 cmp r3, #0 8013182: d018 beq.n 80131b6 { tmp = (const uint16_t *) huart->pTxBuffPtr; 8013184: 687b ldr r3, [r7, #4] 8013186: 6d1b ldr r3, [r3, #80] @ 0x50 8013188: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 801318a: 6bbb ldr r3, [r7, #56] @ 0x38 801318c: 881b ldrh r3, [r3, #0] 801318e: 461a mov r2, r3 8013190: 687b ldr r3, [r7, #4] 8013192: 681b ldr r3, [r3, #0] 8013194: f3c2 0208 ubfx r2, r2, #0, #9 8013198: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 801319a: 687b ldr r3, [r7, #4] 801319c: 6d1b ldr r3, [r3, #80] @ 0x50 801319e: 1c9a adds r2, r3, #2 80131a0: 687b ldr r3, [r7, #4] 80131a2: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80131a4: 687b ldr r3, [r7, #4] 80131a6: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80131aa: b29b uxth r3, r3 80131ac: 3b01 subs r3, #1 80131ae: b29a uxth r2, r3 80131b0: 687b ldr r3, [r7, #4] 80131b2: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80131b6: 8ffb ldrh r3, [r7, #62] @ 0x3e 80131b8: 3b01 subs r3, #1 80131ba: 87fb strh r3, [r7, #62] @ 0x3e 80131bc: 8ffb ldrh r3, [r7, #62] @ 0x3e 80131be: 2b00 cmp r3, #0 80131c0: d19f bne.n 8013102 { /* Nothing to do */ } } } } 80131c2: e7ff b.n 80131c4 80131c4: bf00 nop 80131c6: 3744 adds r7, #68 @ 0x44 80131c8: 46bd mov sp, r7 80131ca: f85d 7b04 ldr.w r7, [sp], #4 80131ce: 4770 bx lr 080131d0 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80131d0: b580 push {r7, lr} 80131d2: b088 sub sp, #32 80131d4: af00 add r7, sp, #0 80131d6: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80131d8: 687b ldr r3, [r7, #4] 80131da: 681b ldr r3, [r3, #0] 80131dc: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131de: 68fb ldr r3, [r7, #12] 80131e0: e853 3f00 ldrex r3, [r3] 80131e4: 60bb str r3, [r7, #8] return(result); 80131e6: 68bb ldr r3, [r7, #8] 80131e8: f023 0340 bic.w r3, r3, #64 @ 0x40 80131ec: 61fb str r3, [r7, #28] 80131ee: 687b ldr r3, [r7, #4] 80131f0: 681b ldr r3, [r3, #0] 80131f2: 461a mov r2, r3 80131f4: 69fb ldr r3, [r7, #28] 80131f6: 61bb str r3, [r7, #24] 80131f8: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80131fa: 6979 ldr r1, [r7, #20] 80131fc: 69ba ldr r2, [r7, #24] 80131fe: e841 2300 strex r3, r2, [r1] 8013202: 613b str r3, [r7, #16] return(result); 8013204: 693b ldr r3, [r7, #16] 8013206: 2b00 cmp r3, #0 8013208: d1e6 bne.n 80131d8 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 801320a: 687b ldr r3, [r7, #4] 801320c: 2220 movs r2, #32 801320e: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 8013212: 687b ldr r3, [r7, #4] 8013214: 2200 movs r2, #0 8013216: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8013218: 6878 ldr r0, [r7, #4] 801321a: f7f1 fc8d bl 8004b38 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 801321e: bf00 nop 8013220: 3720 adds r7, #32 8013222: 46bd mov sp, r7 8013224: bd80 pop {r7, pc} ... 08013228 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8013228: b580 push {r7, lr} 801322a: b09c sub sp, #112 @ 0x70 801322c: af00 add r7, sp, #0 801322e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8013230: 687b ldr r3, [r7, #4] 8013232: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8013236: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 801323a: 687b ldr r3, [r7, #4] 801323c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013240: 2b22 cmp r3, #34 @ 0x22 8013242: f040 80be bne.w 80133c2 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8013246: 687b ldr r3, [r7, #4] 8013248: 681b ldr r3, [r3, #0] 801324a: 6a5b ldr r3, [r3, #36] @ 0x24 801324c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8013250: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 8013254: b2d9 uxtb r1, r3 8013256: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 801325a: b2da uxtb r2, r3 801325c: 687b ldr r3, [r7, #4] 801325e: 6d9b ldr r3, [r3, #88] @ 0x58 8013260: 400a ands r2, r1 8013262: b2d2 uxtb r2, r2 8013264: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8013266: 687b ldr r3, [r7, #4] 8013268: 6d9b ldr r3, [r3, #88] @ 0x58 801326a: 1c5a adds r2, r3, #1 801326c: 687b ldr r3, [r7, #4] 801326e: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013270: 687b ldr r3, [r7, #4] 8013272: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013276: b29b uxth r3, r3 8013278: 3b01 subs r3, #1 801327a: b29a uxth r2, r3 801327c: 687b ldr r3, [r7, #4] 801327e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8013282: 687b ldr r3, [r7, #4] 8013284: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013288: b29b uxth r3, r3 801328a: 2b00 cmp r3, #0 801328c: f040 80a1 bne.w 80133d2 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8013290: 687b ldr r3, [r7, #4] 8013292: 681b ldr r3, [r3, #0] 8013294: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013296: 6cfb ldr r3, [r7, #76] @ 0x4c 8013298: e853 3f00 ldrex r3, [r3] 801329c: 64bb str r3, [r7, #72] @ 0x48 return(result); 801329e: 6cbb ldr r3, [r7, #72] @ 0x48 80132a0: f423 7390 bic.w r3, r3, #288 @ 0x120 80132a4: 66bb str r3, [r7, #104] @ 0x68 80132a6: 687b ldr r3, [r7, #4] 80132a8: 681b ldr r3, [r3, #0] 80132aa: 461a mov r2, r3 80132ac: 6ebb ldr r3, [r7, #104] @ 0x68 80132ae: 65bb str r3, [r7, #88] @ 0x58 80132b0: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132b2: 6d79 ldr r1, [r7, #84] @ 0x54 80132b4: 6dba ldr r2, [r7, #88] @ 0x58 80132b6: e841 2300 strex r3, r2, [r1] 80132ba: 653b str r3, [r7, #80] @ 0x50 return(result); 80132bc: 6d3b ldr r3, [r7, #80] @ 0x50 80132be: 2b00 cmp r3, #0 80132c0: d1e6 bne.n 8013290 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80132c2: 687b ldr r3, [r7, #4] 80132c4: 681b ldr r3, [r3, #0] 80132c6: 3308 adds r3, #8 80132c8: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80132ca: 6bbb ldr r3, [r7, #56] @ 0x38 80132cc: e853 3f00 ldrex r3, [r3] 80132d0: 637b str r3, [r7, #52] @ 0x34 return(result); 80132d2: 6b7b ldr r3, [r7, #52] @ 0x34 80132d4: f023 0301 bic.w r3, r3, #1 80132d8: 667b str r3, [r7, #100] @ 0x64 80132da: 687b ldr r3, [r7, #4] 80132dc: 681b ldr r3, [r3, #0] 80132de: 3308 adds r3, #8 80132e0: 6e7a ldr r2, [r7, #100] @ 0x64 80132e2: 647a str r2, [r7, #68] @ 0x44 80132e4: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132e6: 6c39 ldr r1, [r7, #64] @ 0x40 80132e8: 6c7a ldr r2, [r7, #68] @ 0x44 80132ea: e841 2300 strex r3, r2, [r1] 80132ee: 63fb str r3, [r7, #60] @ 0x3c return(result); 80132f0: 6bfb ldr r3, [r7, #60] @ 0x3c 80132f2: 2b00 cmp r3, #0 80132f4: d1e5 bne.n 80132c2 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80132f6: 687b ldr r3, [r7, #4] 80132f8: 2220 movs r2, #32 80132fa: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80132fe: 687b ldr r3, [r7, #4] 8013300: 2200 movs r2, #0 8013302: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013304: 687b ldr r3, [r7, #4] 8013306: 2200 movs r2, #0 8013308: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801330a: 687b ldr r3, [r7, #4] 801330c: 681b ldr r3, [r3, #0] 801330e: 4a33 ldr r2, [pc, #204] @ (80133dc ) 8013310: 4293 cmp r3, r2 8013312: d01f beq.n 8013354 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013314: 687b ldr r3, [r7, #4] 8013316: 681b ldr r3, [r3, #0] 8013318: 685b ldr r3, [r3, #4] 801331a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801331e: 2b00 cmp r3, #0 8013320: d018 beq.n 8013354 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013322: 687b ldr r3, [r7, #4] 8013324: 681b ldr r3, [r3, #0] 8013326: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013328: 6a7b ldr r3, [r7, #36] @ 0x24 801332a: e853 3f00 ldrex r3, [r3] 801332e: 623b str r3, [r7, #32] return(result); 8013330: 6a3b ldr r3, [r7, #32] 8013332: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013336: 663b str r3, [r7, #96] @ 0x60 8013338: 687b ldr r3, [r7, #4] 801333a: 681b ldr r3, [r3, #0] 801333c: 461a mov r2, r3 801333e: 6e3b ldr r3, [r7, #96] @ 0x60 8013340: 633b str r3, [r7, #48] @ 0x30 8013342: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013344: 6af9 ldr r1, [r7, #44] @ 0x2c 8013346: 6b3a ldr r2, [r7, #48] @ 0x30 8013348: e841 2300 strex r3, r2, [r1] 801334c: 62bb str r3, [r7, #40] @ 0x28 return(result); 801334e: 6abb ldr r3, [r7, #40] @ 0x28 8013350: 2b00 cmp r3, #0 8013352: d1e6 bne.n 8013322 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013354: 687b ldr r3, [r7, #4] 8013356: 6edb ldr r3, [r3, #108] @ 0x6c 8013358: 2b01 cmp r3, #1 801335a: d12e bne.n 80133ba { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801335c: 687b ldr r3, [r7, #4] 801335e: 2200 movs r2, #0 8013360: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013362: 687b ldr r3, [r7, #4] 8013364: 681b ldr r3, [r3, #0] 8013366: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013368: 693b ldr r3, [r7, #16] 801336a: e853 3f00 ldrex r3, [r3] 801336e: 60fb str r3, [r7, #12] return(result); 8013370: 68fb ldr r3, [r7, #12] 8013372: f023 0310 bic.w r3, r3, #16 8013376: 65fb str r3, [r7, #92] @ 0x5c 8013378: 687b ldr r3, [r7, #4] 801337a: 681b ldr r3, [r3, #0] 801337c: 461a mov r2, r3 801337e: 6dfb ldr r3, [r7, #92] @ 0x5c 8013380: 61fb str r3, [r7, #28] 8013382: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013384: 69b9 ldr r1, [r7, #24] 8013386: 69fa ldr r2, [r7, #28] 8013388: e841 2300 strex r3, r2, [r1] 801338c: 617b str r3, [r7, #20] return(result); 801338e: 697b ldr r3, [r7, #20] 8013390: 2b00 cmp r3, #0 8013392: d1e6 bne.n 8013362 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013394: 687b ldr r3, [r7, #4] 8013396: 681b ldr r3, [r3, #0] 8013398: 69db ldr r3, [r3, #28] 801339a: f003 0310 and.w r3, r3, #16 801339e: 2b10 cmp r3, #16 80133a0: d103 bne.n 80133aa { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80133a2: 687b ldr r3, [r7, #4] 80133a4: 681b ldr r3, [r3, #0] 80133a6: 2210 movs r2, #16 80133a8: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80133aa: 687b ldr r3, [r7, #4] 80133ac: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80133b0: 4619 mov r1, r3 80133b2: 6878 ldr r0, [r7, #4] 80133b4: f7f1 fb96 bl 8004ae4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80133b8: e00b b.n 80133d2 HAL_UART_RxCpltCallback(huart); 80133ba: 6878 ldr r0, [r7, #4] 80133bc: f7f1 fb88 bl 8004ad0 } 80133c0: e007 b.n 80133d2 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80133c2: 687b ldr r3, [r7, #4] 80133c4: 681b ldr r3, [r3, #0] 80133c6: 699a ldr r2, [r3, #24] 80133c8: 687b ldr r3, [r7, #4] 80133ca: 681b ldr r3, [r3, #0] 80133cc: f042 0208 orr.w r2, r2, #8 80133d0: 619a str r2, [r3, #24] } 80133d2: bf00 nop 80133d4: 3770 adds r7, #112 @ 0x70 80133d6: 46bd mov sp, r7 80133d8: bd80 pop {r7, pc} 80133da: bf00 nop 80133dc: 58000c00 .word 0x58000c00 080133e0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 80133e0: b580 push {r7, lr} 80133e2: b09c sub sp, #112 @ 0x70 80133e4: af00 add r7, sp, #0 80133e6: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 80133e8: 687b ldr r3, [r7, #4] 80133ea: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80133ee: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80133f2: 687b ldr r3, [r7, #4] 80133f4: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80133f8: 2b22 cmp r3, #34 @ 0x22 80133fa: f040 80be bne.w 801357a { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80133fe: 687b ldr r3, [r7, #4] 8013400: 681b ldr r3, [r3, #0] 8013402: 6a5b ldr r3, [r3, #36] @ 0x24 8013404: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 8013408: 687b ldr r3, [r7, #4] 801340a: 6d9b ldr r3, [r3, #88] @ 0x58 801340c: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 801340e: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 8013412: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 8013416: 4013 ands r3, r2 8013418: b29a uxth r2, r3 801341a: 6ebb ldr r3, [r7, #104] @ 0x68 801341c: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 801341e: 687b ldr r3, [r7, #4] 8013420: 6d9b ldr r3, [r3, #88] @ 0x58 8013422: 1c9a adds r2, r3, #2 8013424: 687b ldr r3, [r7, #4] 8013426: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013428: 687b ldr r3, [r7, #4] 801342a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 801342e: b29b uxth r3, r3 8013430: 3b01 subs r3, #1 8013432: b29a uxth r2, r3 8013434: 687b ldr r3, [r7, #4] 8013436: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 801343a: 687b ldr r3, [r7, #4] 801343c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013440: b29b uxth r3, r3 8013442: 2b00 cmp r3, #0 8013444: f040 80a1 bne.w 801358a { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8013448: 687b ldr r3, [r7, #4] 801344a: 681b ldr r3, [r3, #0] 801344c: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801344e: 6cbb ldr r3, [r7, #72] @ 0x48 8013450: e853 3f00 ldrex r3, [r3] 8013454: 647b str r3, [r7, #68] @ 0x44 return(result); 8013456: 6c7b ldr r3, [r7, #68] @ 0x44 8013458: f423 7390 bic.w r3, r3, #288 @ 0x120 801345c: 667b str r3, [r7, #100] @ 0x64 801345e: 687b ldr r3, [r7, #4] 8013460: 681b ldr r3, [r3, #0] 8013462: 461a mov r2, r3 8013464: 6e7b ldr r3, [r7, #100] @ 0x64 8013466: 657b str r3, [r7, #84] @ 0x54 8013468: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801346a: 6d39 ldr r1, [r7, #80] @ 0x50 801346c: 6d7a ldr r2, [r7, #84] @ 0x54 801346e: e841 2300 strex r3, r2, [r1] 8013472: 64fb str r3, [r7, #76] @ 0x4c return(result); 8013474: 6cfb ldr r3, [r7, #76] @ 0x4c 8013476: 2b00 cmp r3, #0 8013478: d1e6 bne.n 8013448 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 801347a: 687b ldr r3, [r7, #4] 801347c: 681b ldr r3, [r3, #0] 801347e: 3308 adds r3, #8 8013480: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013482: 6b7b ldr r3, [r7, #52] @ 0x34 8013484: e853 3f00 ldrex r3, [r3] 8013488: 633b str r3, [r7, #48] @ 0x30 return(result); 801348a: 6b3b ldr r3, [r7, #48] @ 0x30 801348c: f023 0301 bic.w r3, r3, #1 8013490: 663b str r3, [r7, #96] @ 0x60 8013492: 687b ldr r3, [r7, #4] 8013494: 681b ldr r3, [r3, #0] 8013496: 3308 adds r3, #8 8013498: 6e3a ldr r2, [r7, #96] @ 0x60 801349a: 643a str r2, [r7, #64] @ 0x40 801349c: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801349e: 6bf9 ldr r1, [r7, #60] @ 0x3c 80134a0: 6c3a ldr r2, [r7, #64] @ 0x40 80134a2: e841 2300 strex r3, r2, [r1] 80134a6: 63bb str r3, [r7, #56] @ 0x38 return(result); 80134a8: 6bbb ldr r3, [r7, #56] @ 0x38 80134aa: 2b00 cmp r3, #0 80134ac: d1e5 bne.n 801347a /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80134ae: 687b ldr r3, [r7, #4] 80134b0: 2220 movs r2, #32 80134b2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80134b6: 687b ldr r3, [r7, #4] 80134b8: 2200 movs r2, #0 80134ba: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80134bc: 687b ldr r3, [r7, #4] 80134be: 2200 movs r2, #0 80134c0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80134c2: 687b ldr r3, [r7, #4] 80134c4: 681b ldr r3, [r3, #0] 80134c6: 4a33 ldr r2, [pc, #204] @ (8013594 ) 80134c8: 4293 cmp r3, r2 80134ca: d01f beq.n 801350c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80134cc: 687b ldr r3, [r7, #4] 80134ce: 681b ldr r3, [r3, #0] 80134d0: 685b ldr r3, [r3, #4] 80134d2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80134d6: 2b00 cmp r3, #0 80134d8: d018 beq.n 801350c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80134da: 687b ldr r3, [r7, #4] 80134dc: 681b ldr r3, [r3, #0] 80134de: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80134e0: 6a3b ldr r3, [r7, #32] 80134e2: e853 3f00 ldrex r3, [r3] 80134e6: 61fb str r3, [r7, #28] return(result); 80134e8: 69fb ldr r3, [r7, #28] 80134ea: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80134ee: 65fb str r3, [r7, #92] @ 0x5c 80134f0: 687b ldr r3, [r7, #4] 80134f2: 681b ldr r3, [r3, #0] 80134f4: 461a mov r2, r3 80134f6: 6dfb ldr r3, [r7, #92] @ 0x5c 80134f8: 62fb str r3, [r7, #44] @ 0x2c 80134fa: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134fc: 6ab9 ldr r1, [r7, #40] @ 0x28 80134fe: 6afa ldr r2, [r7, #44] @ 0x2c 8013500: e841 2300 strex r3, r2, [r1] 8013504: 627b str r3, [r7, #36] @ 0x24 return(result); 8013506: 6a7b ldr r3, [r7, #36] @ 0x24 8013508: 2b00 cmp r3, #0 801350a: d1e6 bne.n 80134da } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801350c: 687b ldr r3, [r7, #4] 801350e: 6edb ldr r3, [r3, #108] @ 0x6c 8013510: 2b01 cmp r3, #1 8013512: d12e bne.n 8013572 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013514: 687b ldr r3, [r7, #4] 8013516: 2200 movs r2, #0 8013518: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801351a: 687b ldr r3, [r7, #4] 801351c: 681b ldr r3, [r3, #0] 801351e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013520: 68fb ldr r3, [r7, #12] 8013522: e853 3f00 ldrex r3, [r3] 8013526: 60bb str r3, [r7, #8] return(result); 8013528: 68bb ldr r3, [r7, #8] 801352a: f023 0310 bic.w r3, r3, #16 801352e: 65bb str r3, [r7, #88] @ 0x58 8013530: 687b ldr r3, [r7, #4] 8013532: 681b ldr r3, [r3, #0] 8013534: 461a mov r2, r3 8013536: 6dbb ldr r3, [r7, #88] @ 0x58 8013538: 61bb str r3, [r7, #24] 801353a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801353c: 6979 ldr r1, [r7, #20] 801353e: 69ba ldr r2, [r7, #24] 8013540: e841 2300 strex r3, r2, [r1] 8013544: 613b str r3, [r7, #16] return(result); 8013546: 693b ldr r3, [r7, #16] 8013548: 2b00 cmp r3, #0 801354a: d1e6 bne.n 801351a if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 801354c: 687b ldr r3, [r7, #4] 801354e: 681b ldr r3, [r3, #0] 8013550: 69db ldr r3, [r3, #28] 8013552: f003 0310 and.w r3, r3, #16 8013556: 2b10 cmp r3, #16 8013558: d103 bne.n 8013562 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 801355a: 687b ldr r3, [r7, #4] 801355c: 681b ldr r3, [r3, #0] 801355e: 2210 movs r2, #16 8013560: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013562: 687b ldr r3, [r7, #4] 8013564: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013568: 4619 mov r1, r3 801356a: 6878 ldr r0, [r7, #4] 801356c: f7f1 faba bl 8004ae4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013570: e00b b.n 801358a HAL_UART_RxCpltCallback(huart); 8013572: 6878 ldr r0, [r7, #4] 8013574: f7f1 faac bl 8004ad0 } 8013578: e007 b.n 801358a __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 801357a: 687b ldr r3, [r7, #4] 801357c: 681b ldr r3, [r3, #0] 801357e: 699a ldr r2, [r3, #24] 8013580: 687b ldr r3, [r7, #4] 8013582: 681b ldr r3, [r3, #0] 8013584: f042 0208 orr.w r2, r2, #8 8013588: 619a str r2, [r3, #24] } 801358a: bf00 nop 801358c: 3770 adds r7, #112 @ 0x70 801358e: 46bd mov sp, r7 8013590: bd80 pop {r7, pc} 8013592: bf00 nop 8013594: 58000c00 .word 0x58000c00 08013598 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 8013598: b580 push {r7, lr} 801359a: b0ac sub sp, #176 @ 0xb0 801359c: af00 add r7, sp, #0 801359e: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 80135a0: 687b ldr r3, [r7, #4] 80135a2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80135a6: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 80135aa: 687b ldr r3, [r7, #4] 80135ac: 681b ldr r3, [r3, #0] 80135ae: 69db ldr r3, [r3, #28] 80135b0: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 80135b4: 687b ldr r3, [r7, #4] 80135b6: 681b ldr r3, [r3, #0] 80135b8: 681b ldr r3, [r3, #0] 80135ba: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80135be: 687b ldr r3, [r7, #4] 80135c0: 681b ldr r3, [r3, #0] 80135c2: 689b ldr r3, [r3, #8] 80135c4: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80135c8: 687b ldr r3, [r7, #4] 80135ca: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80135ce: 2b22 cmp r3, #34 @ 0x22 80135d0: f040 8180 bne.w 80138d4 { nb_rx_data = huart->NbRxDataToProcess; 80135d4: 687b ldr r3, [r7, #4] 80135d6: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80135da: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80135de: e123 b.n 8013828 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80135e0: 687b ldr r3, [r7, #4] 80135e2: 681b ldr r3, [r3, #0] 80135e4: 6a5b ldr r3, [r3, #36] @ 0x24 80135e6: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 80135ea: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 80135ee: b2d9 uxtb r1, r3 80135f0: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 80135f4: b2da uxtb r2, r3 80135f6: 687b ldr r3, [r7, #4] 80135f8: 6d9b ldr r3, [r3, #88] @ 0x58 80135fa: 400a ands r2, r1 80135fc: b2d2 uxtb r2, r2 80135fe: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8013600: 687b ldr r3, [r7, #4] 8013602: 6d9b ldr r3, [r3, #88] @ 0x58 8013604: 1c5a adds r2, r3, #1 8013606: 687b ldr r3, [r7, #4] 8013608: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 801360a: 687b ldr r3, [r7, #4] 801360c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013610: b29b uxth r3, r3 8013612: 3b01 subs r3, #1 8013614: b29a uxth r2, r3 8013616: 687b ldr r3, [r7, #4] 8013618: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 801361c: 687b ldr r3, [r7, #4] 801361e: 681b ldr r3, [r3, #0] 8013620: 69db ldr r3, [r3, #28] 8013622: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8013626: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801362a: f003 0307 and.w r3, r3, #7 801362e: 2b00 cmp r3, #0 8013630: d053 beq.n 80136da { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8013632: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013636: f003 0301 and.w r3, r3, #1 801363a: 2b00 cmp r3, #0 801363c: d011 beq.n 8013662 801363e: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 8013642: f403 7380 and.w r3, r3, #256 @ 0x100 8013646: 2b00 cmp r3, #0 8013648: d00b beq.n 8013662 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 801364a: 687b ldr r3, [r7, #4] 801364c: 681b ldr r3, [r3, #0] 801364e: 2201 movs r2, #1 8013650: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8013652: 687b ldr r3, [r7, #4] 8013654: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013658: f043 0201 orr.w r2, r3, #1 801365c: 687b ldr r3, [r7, #4] 801365e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8013662: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013666: f003 0302 and.w r3, r3, #2 801366a: 2b00 cmp r3, #0 801366c: d011 beq.n 8013692 801366e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8013672: f003 0301 and.w r3, r3, #1 8013676: 2b00 cmp r3, #0 8013678: d00b beq.n 8013692 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 801367a: 687b ldr r3, [r7, #4] 801367c: 681b ldr r3, [r3, #0] 801367e: 2202 movs r2, #2 8013680: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8013682: 687b ldr r3, [r7, #4] 8013684: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013688: f043 0204 orr.w r2, r3, #4 801368c: 687b ldr r3, [r7, #4] 801368e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8013692: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013696: f003 0304 and.w r3, r3, #4 801369a: 2b00 cmp r3, #0 801369c: d011 beq.n 80136c2 801369e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80136a2: f003 0301 and.w r3, r3, #1 80136a6: 2b00 cmp r3, #0 80136a8: d00b beq.n 80136c2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 80136aa: 687b ldr r3, [r7, #4] 80136ac: 681b ldr r3, [r3, #0] 80136ae: 2204 movs r2, #4 80136b0: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80136b2: 687b ldr r3, [r7, #4] 80136b4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80136b8: f043 0202 orr.w r2, r3, #2 80136bc: 687b ldr r3, [r7, #4] 80136be: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80136c2: 687b ldr r3, [r7, #4] 80136c4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80136c8: 2b00 cmp r3, #0 80136ca: d006 beq.n 80136da #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80136cc: 6878 ldr r0, [r7, #4] 80136ce: f7fe fb13 bl 8011cf8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80136d2: 687b ldr r3, [r7, #4] 80136d4: 2200 movs r2, #0 80136d6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 80136da: 687b ldr r3, [r7, #4] 80136dc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80136e0: b29b uxth r3, r3 80136e2: 2b00 cmp r3, #0 80136e4: f040 80a0 bne.w 8013828 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80136e8: 687b ldr r3, [r7, #4] 80136ea: 681b ldr r3, [r3, #0] 80136ec: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136ee: 6f3b ldr r3, [r7, #112] @ 0x70 80136f0: e853 3f00 ldrex r3, [r3] 80136f4: 66fb str r3, [r7, #108] @ 0x6c return(result); 80136f6: 6efb ldr r3, [r7, #108] @ 0x6c 80136f8: f423 7380 bic.w r3, r3, #256 @ 0x100 80136fc: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8013700: 687b ldr r3, [r7, #4] 8013702: 681b ldr r3, [r3, #0] 8013704: 461a mov r2, r3 8013706: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 801370a: 67fb str r3, [r7, #124] @ 0x7c 801370c: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801370e: 6fb9 ldr r1, [r7, #120] @ 0x78 8013710: 6ffa ldr r2, [r7, #124] @ 0x7c 8013712: e841 2300 strex r3, r2, [r1] 8013716: 677b str r3, [r7, #116] @ 0x74 return(result); 8013718: 6f7b ldr r3, [r7, #116] @ 0x74 801371a: 2b00 cmp r3, #0 801371c: d1e4 bne.n 80136e8 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 801371e: 687b ldr r3, [r7, #4] 8013720: 681b ldr r3, [r3, #0] 8013722: 3308 adds r3, #8 8013724: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013726: 6dfb ldr r3, [r7, #92] @ 0x5c 8013728: e853 3f00 ldrex r3, [r3] 801372c: 65bb str r3, [r7, #88] @ 0x58 return(result); 801372e: 6dba ldr r2, [r7, #88] @ 0x58 8013730: 4b6e ldr r3, [pc, #440] @ (80138ec ) 8013732: 4013 ands r3, r2 8013734: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013738: 687b ldr r3, [r7, #4] 801373a: 681b ldr r3, [r3, #0] 801373c: 3308 adds r3, #8 801373e: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 8013742: 66ba str r2, [r7, #104] @ 0x68 8013744: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013746: 6e79 ldr r1, [r7, #100] @ 0x64 8013748: 6eba ldr r2, [r7, #104] @ 0x68 801374a: e841 2300 strex r3, r2, [r1] 801374e: 663b str r3, [r7, #96] @ 0x60 return(result); 8013750: 6e3b ldr r3, [r7, #96] @ 0x60 8013752: 2b00 cmp r3, #0 8013754: d1e3 bne.n 801371e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013756: 687b ldr r3, [r7, #4] 8013758: 2220 movs r2, #32 801375a: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 801375e: 687b ldr r3, [r7, #4] 8013760: 2200 movs r2, #0 8013762: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013764: 687b ldr r3, [r7, #4] 8013766: 2200 movs r2, #0 8013768: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 801376a: 687b ldr r3, [r7, #4] 801376c: 681b ldr r3, [r3, #0] 801376e: 4a60 ldr r2, [pc, #384] @ (80138f0 ) 8013770: 4293 cmp r3, r2 8013772: d021 beq.n 80137b8 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013774: 687b ldr r3, [r7, #4] 8013776: 681b ldr r3, [r3, #0] 8013778: 685b ldr r3, [r3, #4] 801377a: f403 0300 and.w r3, r3, #8388608 @ 0x800000 801377e: 2b00 cmp r3, #0 8013780: d01a beq.n 80137b8 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013782: 687b ldr r3, [r7, #4] 8013784: 681b ldr r3, [r3, #0] 8013786: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013788: 6cbb ldr r3, [r7, #72] @ 0x48 801378a: e853 3f00 ldrex r3, [r3] 801378e: 647b str r3, [r7, #68] @ 0x44 return(result); 8013790: 6c7b ldr r3, [r7, #68] @ 0x44 8013792: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013796: f8c7 3090 str.w r3, [r7, #144] @ 0x90 801379a: 687b ldr r3, [r7, #4] 801379c: 681b ldr r3, [r3, #0] 801379e: 461a mov r2, r3 80137a0: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80137a4: 657b str r3, [r7, #84] @ 0x54 80137a6: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137a8: 6d39 ldr r1, [r7, #80] @ 0x50 80137aa: 6d7a ldr r2, [r7, #84] @ 0x54 80137ac: e841 2300 strex r3, r2, [r1] 80137b0: 64fb str r3, [r7, #76] @ 0x4c return(result); 80137b2: 6cfb ldr r3, [r7, #76] @ 0x4c 80137b4: 2b00 cmp r3, #0 80137b6: d1e4 bne.n 8013782 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80137b8: 687b ldr r3, [r7, #4] 80137ba: 6edb ldr r3, [r3, #108] @ 0x6c 80137bc: 2b01 cmp r3, #1 80137be: d130 bne.n 8013822 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80137c0: 687b ldr r3, [r7, #4] 80137c2: 2200 movs r2, #0 80137c4: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80137c6: 687b ldr r3, [r7, #4] 80137c8: 681b ldr r3, [r3, #0] 80137ca: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137cc: 6b7b ldr r3, [r7, #52] @ 0x34 80137ce: e853 3f00 ldrex r3, [r3] 80137d2: 633b str r3, [r7, #48] @ 0x30 return(result); 80137d4: 6b3b ldr r3, [r7, #48] @ 0x30 80137d6: f023 0310 bic.w r3, r3, #16 80137da: f8c7 308c str.w r3, [r7, #140] @ 0x8c 80137de: 687b ldr r3, [r7, #4] 80137e0: 681b ldr r3, [r3, #0] 80137e2: 461a mov r2, r3 80137e4: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80137e8: 643b str r3, [r7, #64] @ 0x40 80137ea: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137ec: 6bf9 ldr r1, [r7, #60] @ 0x3c 80137ee: 6c3a ldr r2, [r7, #64] @ 0x40 80137f0: e841 2300 strex r3, r2, [r1] 80137f4: 63bb str r3, [r7, #56] @ 0x38 return(result); 80137f6: 6bbb ldr r3, [r7, #56] @ 0x38 80137f8: 2b00 cmp r3, #0 80137fa: d1e4 bne.n 80137c6 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 80137fc: 687b ldr r3, [r7, #4] 80137fe: 681b ldr r3, [r3, #0] 8013800: 69db ldr r3, [r3, #28] 8013802: f003 0310 and.w r3, r3, #16 8013806: 2b10 cmp r3, #16 8013808: d103 bne.n 8013812 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 801380a: 687b ldr r3, [r7, #4] 801380c: 681b ldr r3, [r3, #0] 801380e: 2210 movs r2, #16 8013810: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013812: 687b ldr r3, [r7, #4] 8013814: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013818: 4619 mov r1, r3 801381a: 6878 ldr r0, [r7, #4] 801381c: f7f1 f962 bl 8004ae4 8013820: e002 b.n 8013828 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8013822: 6878 ldr r0, [r7, #4] 8013824: f7f1 f954 bl 8004ad0 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013828: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 801382c: 2b00 cmp r3, #0 801382e: d006 beq.n 801383e 8013830: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013834: f003 0320 and.w r3, r3, #32 8013838: 2b00 cmp r3, #0 801383a: f47f aed1 bne.w 80135e0 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 801383e: 687b ldr r3, [r7, #4] 8013840: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013844: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8013848: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 801384c: 2b00 cmp r3, #0 801384e: d049 beq.n 80138e4 8013850: 687b ldr r3, [r7, #4] 8013852: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013856: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 801385a: 429a cmp r2, r3 801385c: d242 bcs.n 80138e4 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 801385e: 687b ldr r3, [r7, #4] 8013860: 681b ldr r3, [r3, #0] 8013862: 3308 adds r3, #8 8013864: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013866: 6a3b ldr r3, [r7, #32] 8013868: e853 3f00 ldrex r3, [r3] 801386c: 61fb str r3, [r7, #28] return(result); 801386e: 69fb ldr r3, [r7, #28] 8013870: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8013874: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013878: 687b ldr r3, [r7, #4] 801387a: 681b ldr r3, [r3, #0] 801387c: 3308 adds r3, #8 801387e: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8013882: 62fa str r2, [r7, #44] @ 0x2c 8013884: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013886: 6ab9 ldr r1, [r7, #40] @ 0x28 8013888: 6afa ldr r2, [r7, #44] @ 0x2c 801388a: e841 2300 strex r3, r2, [r1] 801388e: 627b str r3, [r7, #36] @ 0x24 return(result); 8013890: 6a7b ldr r3, [r7, #36] @ 0x24 8013892: 2b00 cmp r3, #0 8013894: d1e3 bne.n 801385e /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 8013896: 687b ldr r3, [r7, #4] 8013898: 4a16 ldr r2, [pc, #88] @ (80138f4 ) 801389a: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 801389c: 687b ldr r3, [r7, #4] 801389e: 681b ldr r3, [r3, #0] 80138a0: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80138a2: 68fb ldr r3, [r7, #12] 80138a4: e853 3f00 ldrex r3, [r3] 80138a8: 60bb str r3, [r7, #8] return(result); 80138aa: 68bb ldr r3, [r7, #8] 80138ac: f043 0320 orr.w r3, r3, #32 80138b0: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80138b4: 687b ldr r3, [r7, #4] 80138b6: 681b ldr r3, [r3, #0] 80138b8: 461a mov r2, r3 80138ba: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80138be: 61bb str r3, [r7, #24] 80138c0: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80138c2: 6979 ldr r1, [r7, #20] 80138c4: 69ba ldr r2, [r7, #24] 80138c6: e841 2300 strex r3, r2, [r1] 80138ca: 613b str r3, [r7, #16] return(result); 80138cc: 693b ldr r3, [r7, #16] 80138ce: 2b00 cmp r3, #0 80138d0: d1e4 bne.n 801389c else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80138d2: e007 b.n 80138e4 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80138d4: 687b ldr r3, [r7, #4] 80138d6: 681b ldr r3, [r3, #0] 80138d8: 699a ldr r2, [r3, #24] 80138da: 687b ldr r3, [r7, #4] 80138dc: 681b ldr r3, [r3, #0] 80138de: f042 0208 orr.w r2, r2, #8 80138e2: 619a str r2, [r3, #24] } 80138e4: bf00 nop 80138e6: 37b0 adds r7, #176 @ 0xb0 80138e8: 46bd mov sp, r7 80138ea: bd80 pop {r7, pc} 80138ec: effffffe .word 0xeffffffe 80138f0: 58000c00 .word 0x58000c00 80138f4: 08013229 .word 0x08013229 080138f8 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 80138f8: b580 push {r7, lr} 80138fa: b0ae sub sp, #184 @ 0xb8 80138fc: af00 add r7, sp, #0 80138fe: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8013900: 687b ldr r3, [r7, #4] 8013902: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 8013906: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 801390a: 687b ldr r3, [r7, #4] 801390c: 681b ldr r3, [r3, #0] 801390e: 69db ldr r3, [r3, #28] 8013910: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 8013914: 687b ldr r3, [r7, #4] 8013916: 681b ldr r3, [r3, #0] 8013918: 681b ldr r3, [r3, #0] 801391a: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 801391e: 687b ldr r3, [r7, #4] 8013920: 681b ldr r3, [r3, #0] 8013922: 689b ldr r3, [r3, #8] 8013924: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8013928: 687b ldr r3, [r7, #4] 801392a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 801392e: 2b22 cmp r3, #34 @ 0x22 8013930: f040 8184 bne.w 8013c3c { nb_rx_data = huart->NbRxDataToProcess; 8013934: 687b ldr r3, [r7, #4] 8013936: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 801393a: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 801393e: e127 b.n 8013b90 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8013940: 687b ldr r3, [r7, #4] 8013942: 681b ldr r3, [r3, #0] 8013944: 6a5b ldr r3, [r3, #36] @ 0x24 8013946: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 801394a: 687b ldr r3, [r7, #4] 801394c: 6d9b ldr r3, [r3, #88] @ 0x58 801394e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 8013952: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 8013956: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 801395a: 4013 ands r3, r2 801395c: b29a uxth r2, r3 801395e: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 8013962: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8013964: 687b ldr r3, [r7, #4] 8013966: 6d9b ldr r3, [r3, #88] @ 0x58 8013968: 1c9a adds r2, r3, #2 801396a: 687b ldr r3, [r7, #4] 801396c: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 801396e: 687b ldr r3, [r7, #4] 8013970: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013974: b29b uxth r3, r3 8013976: 3b01 subs r3, #1 8013978: b29a uxth r2, r3 801397a: 687b ldr r3, [r7, #4] 801397c: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8013980: 687b ldr r3, [r7, #4] 8013982: 681b ldr r3, [r3, #0] 8013984: 69db ldr r3, [r3, #28] 8013986: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 801398a: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 801398e: f003 0307 and.w r3, r3, #7 8013992: 2b00 cmp r3, #0 8013994: d053 beq.n 8013a3e { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8013996: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 801399a: f003 0301 and.w r3, r3, #1 801399e: 2b00 cmp r3, #0 80139a0: d011 beq.n 80139c6 80139a2: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80139a6: f403 7380 and.w r3, r3, #256 @ 0x100 80139aa: 2b00 cmp r3, #0 80139ac: d00b beq.n 80139c6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 80139ae: 687b ldr r3, [r7, #4] 80139b0: 681b ldr r3, [r3, #0] 80139b2: 2201 movs r2, #1 80139b4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 80139b6: 687b ldr r3, [r7, #4] 80139b8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80139bc: f043 0201 orr.w r2, r3, #1 80139c0: 687b ldr r3, [r7, #4] 80139c2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80139c6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80139ca: f003 0302 and.w r3, r3, #2 80139ce: 2b00 cmp r3, #0 80139d0: d011 beq.n 80139f6 80139d2: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80139d6: f003 0301 and.w r3, r3, #1 80139da: 2b00 cmp r3, #0 80139dc: d00b beq.n 80139f6 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 80139de: 687b ldr r3, [r7, #4] 80139e0: 681b ldr r3, [r3, #0] 80139e2: 2202 movs r2, #2 80139e4: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 80139e6: 687b ldr r3, [r7, #4] 80139e8: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80139ec: f043 0204 orr.w r2, r3, #4 80139f0: 687b ldr r3, [r7, #4] 80139f2: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80139f6: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80139fa: f003 0304 and.w r3, r3, #4 80139fe: 2b00 cmp r3, #0 8013a00: d011 beq.n 8013a26 8013a02: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8013a06: f003 0301 and.w r3, r3, #1 8013a0a: 2b00 cmp r3, #0 8013a0c: d00b beq.n 8013a26 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8013a0e: 687b ldr r3, [r7, #4] 8013a10: 681b ldr r3, [r3, #0] 8013a12: 2204 movs r2, #4 8013a14: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8013a16: 687b ldr r3, [r7, #4] 8013a18: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013a1c: f043 0202 orr.w r2, r3, #2 8013a20: 687b ldr r3, [r7, #4] 8013a22: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8013a26: 687b ldr r3, [r7, #4] 8013a28: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013a2c: 2b00 cmp r3, #0 8013a2e: d006 beq.n 8013a3e #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013a30: 6878 ldr r0, [r7, #4] 8013a32: f7fe f961 bl 8011cf8 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013a36: 687b ldr r3, [r7, #4] 8013a38: 2200 movs r2, #0 8013a3a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8013a3e: 687b ldr r3, [r7, #4] 8013a40: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013a44: b29b uxth r3, r3 8013a46: 2b00 cmp r3, #0 8013a48: f040 80a2 bne.w 8013b90 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013a4c: 687b ldr r3, [r7, #4] 8013a4e: 681b ldr r3, [r3, #0] 8013a50: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a52: 6f7b ldr r3, [r7, #116] @ 0x74 8013a54: e853 3f00 ldrex r3, [r3] 8013a58: 673b str r3, [r7, #112] @ 0x70 return(result); 8013a5a: 6f3b ldr r3, [r7, #112] @ 0x70 8013a5c: f423 7380 bic.w r3, r3, #256 @ 0x100 8013a60: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8013a64: 687b ldr r3, [r7, #4] 8013a66: 681b ldr r3, [r3, #0] 8013a68: 461a mov r2, r3 8013a6a: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8013a6e: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8013a72: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a74: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013a76: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8013a7a: e841 2300 strex r3, r2, [r1] 8013a7e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8013a80: 6fbb ldr r3, [r7, #120] @ 0x78 8013a82: 2b00 cmp r3, #0 8013a84: d1e2 bne.n 8013a4c /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8013a86: 687b ldr r3, [r7, #4] 8013a88: 681b ldr r3, [r3, #0] 8013a8a: 3308 adds r3, #8 8013a8c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a8e: 6e3b ldr r3, [r7, #96] @ 0x60 8013a90: e853 3f00 ldrex r3, [r3] 8013a94: 65fb str r3, [r7, #92] @ 0x5c return(result); 8013a96: 6dfa ldr r2, [r7, #92] @ 0x5c 8013a98: 4b6e ldr r3, [pc, #440] @ (8013c54 ) 8013a9a: 4013 ands r3, r2 8013a9c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8013aa0: 687b ldr r3, [r7, #4] 8013aa2: 681b ldr r3, [r3, #0] 8013aa4: 3308 adds r3, #8 8013aa6: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 8013aaa: 66fa str r2, [r7, #108] @ 0x6c 8013aac: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013aae: 6eb9 ldr r1, [r7, #104] @ 0x68 8013ab0: 6efa ldr r2, [r7, #108] @ 0x6c 8013ab2: e841 2300 strex r3, r2, [r1] 8013ab6: 667b str r3, [r7, #100] @ 0x64 return(result); 8013ab8: 6e7b ldr r3, [r7, #100] @ 0x64 8013aba: 2b00 cmp r3, #0 8013abc: d1e3 bne.n 8013a86 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013abe: 687b ldr r3, [r7, #4] 8013ac0: 2220 movs r2, #32 8013ac2: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8013ac6: 687b ldr r3, [r7, #4] 8013ac8: 2200 movs r2, #0 8013aca: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013acc: 687b ldr r3, [r7, #4] 8013ace: 2200 movs r2, #0 8013ad0: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8013ad2: 687b ldr r3, [r7, #4] 8013ad4: 681b ldr r3, [r3, #0] 8013ad6: 4a60 ldr r2, [pc, #384] @ (8013c58 ) 8013ad8: 4293 cmp r3, r2 8013ada: d021 beq.n 8013b20 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013adc: 687b ldr r3, [r7, #4] 8013ade: 681b ldr r3, [r3, #0] 8013ae0: 685b ldr r3, [r3, #4] 8013ae2: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8013ae6: 2b00 cmp r3, #0 8013ae8: d01a beq.n 8013b20 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013aea: 687b ldr r3, [r7, #4] 8013aec: 681b ldr r3, [r3, #0] 8013aee: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013af0: 6cfb ldr r3, [r7, #76] @ 0x4c 8013af2: e853 3f00 ldrex r3, [r3] 8013af6: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013af8: 6cbb ldr r3, [r7, #72] @ 0x48 8013afa: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013afe: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013b02: 687b ldr r3, [r7, #4] 8013b04: 681b ldr r3, [r3, #0] 8013b06: 461a mov r2, r3 8013b08: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 8013b0c: 65bb str r3, [r7, #88] @ 0x58 8013b0e: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b10: 6d79 ldr r1, [r7, #84] @ 0x54 8013b12: 6dba ldr r2, [r7, #88] @ 0x58 8013b14: e841 2300 strex r3, r2, [r1] 8013b18: 653b str r3, [r7, #80] @ 0x50 return(result); 8013b1a: 6d3b ldr r3, [r7, #80] @ 0x50 8013b1c: 2b00 cmp r3, #0 8013b1e: d1e4 bne.n 8013aea } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013b20: 687b ldr r3, [r7, #4] 8013b22: 6edb ldr r3, [r3, #108] @ 0x6c 8013b24: 2b01 cmp r3, #1 8013b26: d130 bne.n 8013b8a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013b28: 687b ldr r3, [r7, #4] 8013b2a: 2200 movs r2, #0 8013b2c: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013b2e: 687b ldr r3, [r7, #4] 8013b30: 681b ldr r3, [r3, #0] 8013b32: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013b34: 6bbb ldr r3, [r7, #56] @ 0x38 8013b36: e853 3f00 ldrex r3, [r3] 8013b3a: 637b str r3, [r7, #52] @ 0x34 return(result); 8013b3c: 6b7b ldr r3, [r7, #52] @ 0x34 8013b3e: f023 0310 bic.w r3, r3, #16 8013b42: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8013b46: 687b ldr r3, [r7, #4] 8013b48: 681b ldr r3, [r3, #0] 8013b4a: 461a mov r2, r3 8013b4c: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8013b50: 647b str r3, [r7, #68] @ 0x44 8013b52: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b54: 6c39 ldr r1, [r7, #64] @ 0x40 8013b56: 6c7a ldr r2, [r7, #68] @ 0x44 8013b58: e841 2300 strex r3, r2, [r1] 8013b5c: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013b5e: 6bfb ldr r3, [r7, #60] @ 0x3c 8013b60: 2b00 cmp r3, #0 8013b62: d1e4 bne.n 8013b2e if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013b64: 687b ldr r3, [r7, #4] 8013b66: 681b ldr r3, [r3, #0] 8013b68: 69db ldr r3, [r3, #28] 8013b6a: f003 0310 and.w r3, r3, #16 8013b6e: 2b10 cmp r3, #16 8013b70: d103 bne.n 8013b7a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013b72: 687b ldr r3, [r7, #4] 8013b74: 681b ldr r3, [r3, #0] 8013b76: 2210 movs r2, #16 8013b78: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013b7a: 687b ldr r3, [r7, #4] 8013b7c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013b80: 4619 mov r1, r3 8013b82: 6878 ldr r0, [r7, #4] 8013b84: f7f0 ffae bl 8004ae4 8013b88: e002 b.n 8013b90 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8013b8a: 6878 ldr r0, [r7, #4] 8013b8c: f7f0 ffa0 bl 8004ad0 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013b90: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8013b94: 2b00 cmp r3, #0 8013b96: d006 beq.n 8013ba6 8013b98: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013b9c: f003 0320 and.w r3, r3, #32 8013ba0: 2b00 cmp r3, #0 8013ba2: f47f aecd bne.w 8013940 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8013ba6: 687b ldr r3, [r7, #4] 8013ba8: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013bac: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8013bb0: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8013bb4: 2b00 cmp r3, #0 8013bb6: d049 beq.n 8013c4c 8013bb8: 687b ldr r3, [r7, #4] 8013bba: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013bbe: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 8013bc2: 429a cmp r2, r3 8013bc4: d242 bcs.n 8013c4c { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8013bc6: 687b ldr r3, [r7, #4] 8013bc8: 681b ldr r3, [r3, #0] 8013bca: 3308 adds r3, #8 8013bcc: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013bce: 6a7b ldr r3, [r7, #36] @ 0x24 8013bd0: e853 3f00 ldrex r3, [r3] 8013bd4: 623b str r3, [r7, #32] return(result); 8013bd6: 6a3b ldr r3, [r7, #32] 8013bd8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8013bdc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8013be0: 687b ldr r3, [r7, #4] 8013be2: 681b ldr r3, [r3, #0] 8013be4: 3308 adds r3, #8 8013be6: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 8013bea: 633a str r2, [r7, #48] @ 0x30 8013bec: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013bee: 6af9 ldr r1, [r7, #44] @ 0x2c 8013bf0: 6b3a ldr r2, [r7, #48] @ 0x30 8013bf2: e841 2300 strex r3, r2, [r1] 8013bf6: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013bf8: 6abb ldr r3, [r7, #40] @ 0x28 8013bfa: 2b00 cmp r3, #0 8013bfc: d1e3 bne.n 8013bc6 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 8013bfe: 687b ldr r3, [r7, #4] 8013c00: 4a16 ldr r2, [pc, #88] @ (8013c5c ) 8013c02: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8013c04: 687b ldr r3, [r7, #4] 8013c06: 681b ldr r3, [r3, #0] 8013c08: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013c0a: 693b ldr r3, [r7, #16] 8013c0c: e853 3f00 ldrex r3, [r3] 8013c10: 60fb str r3, [r7, #12] return(result); 8013c12: 68fb ldr r3, [r7, #12] 8013c14: f043 0320 orr.w r3, r3, #32 8013c18: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013c1c: 687b ldr r3, [r7, #4] 8013c1e: 681b ldr r3, [r3, #0] 8013c20: 461a mov r2, r3 8013c22: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013c26: 61fb str r3, [r7, #28] 8013c28: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c2a: 69b9 ldr r1, [r7, #24] 8013c2c: 69fa ldr r2, [r7, #28] 8013c2e: e841 2300 strex r3, r2, [r1] 8013c32: 617b str r3, [r7, #20] return(result); 8013c34: 697b ldr r3, [r7, #20] 8013c36: 2b00 cmp r3, #0 8013c38: d1e4 bne.n 8013c04 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013c3a: e007 b.n 8013c4c __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8013c3c: 687b ldr r3, [r7, #4] 8013c3e: 681b ldr r3, [r3, #0] 8013c40: 699a ldr r2, [r3, #24] 8013c42: 687b ldr r3, [r7, #4] 8013c44: 681b ldr r3, [r3, #0] 8013c46: f042 0208 orr.w r2, r2, #8 8013c4a: 619a str r2, [r3, #24] } 8013c4c: bf00 nop 8013c4e: 37b8 adds r7, #184 @ 0xb8 8013c50: 46bd mov sp, r7 8013c52: bd80 pop {r7, pc} 8013c54: effffffe .word 0xeffffffe 8013c58: 58000c00 .word 0x58000c00 8013c5c: 080133e1 .word 0x080133e1 08013c60 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8013c60: b480 push {r7} 8013c62: b083 sub sp, #12 8013c64: af00 add r7, sp, #0 8013c66: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8013c68: bf00 nop 8013c6a: 370c adds r7, #12 8013c6c: 46bd mov sp, r7 8013c6e: f85d 7b04 ldr.w r7, [sp], #4 8013c72: 4770 bx lr 08013c74 : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8013c74: b480 push {r7} 8013c76: b083 sub sp, #12 8013c78: af00 add r7, sp, #0 8013c7a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8013c7c: bf00 nop 8013c7e: 370c adds r7, #12 8013c80: 46bd mov sp, r7 8013c82: f85d 7b04 ldr.w r7, [sp], #4 8013c86: 4770 bx lr 08013c88 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8013c88: b480 push {r7} 8013c8a: b083 sub sp, #12 8013c8c: af00 add r7, sp, #0 8013c8e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8013c90: bf00 nop 8013c92: 370c adds r7, #12 8013c94: 46bd mov sp, r7 8013c96: f85d 7b04 ldr.w r7, [sp], #4 8013c9a: 4770 bx lr 08013c9c : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8013c9c: b480 push {r7} 8013c9e: b085 sub sp, #20 8013ca0: af00 add r7, sp, #0 8013ca2: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8013ca4: 687b ldr r3, [r7, #4] 8013ca6: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013caa: 2b01 cmp r3, #1 8013cac: d101 bne.n 8013cb2 8013cae: 2302 movs r3, #2 8013cb0: e027 b.n 8013d02 8013cb2: 687b ldr r3, [r7, #4] 8013cb4: 2201 movs r2, #1 8013cb6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013cba: 687b ldr r3, [r7, #4] 8013cbc: 2224 movs r2, #36 @ 0x24 8013cbe: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013cc2: 687b ldr r3, [r7, #4] 8013cc4: 681b ldr r3, [r3, #0] 8013cc6: 681b ldr r3, [r3, #0] 8013cc8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013cca: 687b ldr r3, [r7, #4] 8013ccc: 681b ldr r3, [r3, #0] 8013cce: 681a ldr r2, [r3, #0] 8013cd0: 687b ldr r3, [r7, #4] 8013cd2: 681b ldr r3, [r3, #0] 8013cd4: f022 0201 bic.w r2, r2, #1 8013cd8: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 8013cda: 68fb ldr r3, [r7, #12] 8013cdc: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8013ce0: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8013ce2: 687b ldr r3, [r7, #4] 8013ce4: 2200 movs r2, #0 8013ce6: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013ce8: 687b ldr r3, [r7, #4] 8013cea: 681b ldr r3, [r3, #0] 8013cec: 68fa ldr r2, [r7, #12] 8013cee: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013cf0: 687b ldr r3, [r7, #4] 8013cf2: 2220 movs r2, #32 8013cf4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013cf8: 687b ldr r3, [r7, #4] 8013cfa: 2200 movs r2, #0 8013cfc: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013d00: 2300 movs r3, #0 } 8013d02: 4618 mov r0, r3 8013d04: 3714 adds r7, #20 8013d06: 46bd mov sp, r7 8013d08: f85d 7b04 ldr.w r7, [sp], #4 8013d0c: 4770 bx lr 08013d0e : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013d0e: b580 push {r7, lr} 8013d10: b084 sub sp, #16 8013d12: af00 add r7, sp, #0 8013d14: 6078 str r0, [r7, #4] 8013d16: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013d18: 687b ldr r3, [r7, #4] 8013d1a: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013d1e: 2b01 cmp r3, #1 8013d20: d101 bne.n 8013d26 8013d22: 2302 movs r3, #2 8013d24: e02d b.n 8013d82 8013d26: 687b ldr r3, [r7, #4] 8013d28: 2201 movs r2, #1 8013d2a: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013d2e: 687b ldr r3, [r7, #4] 8013d30: 2224 movs r2, #36 @ 0x24 8013d32: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013d36: 687b ldr r3, [r7, #4] 8013d38: 681b ldr r3, [r3, #0] 8013d3a: 681b ldr r3, [r3, #0] 8013d3c: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013d3e: 687b ldr r3, [r7, #4] 8013d40: 681b ldr r3, [r3, #0] 8013d42: 681a ldr r2, [r3, #0] 8013d44: 687b ldr r3, [r7, #4] 8013d46: 681b ldr r3, [r3, #0] 8013d48: f022 0201 bic.w r2, r2, #1 8013d4c: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8013d4e: 687b ldr r3, [r7, #4] 8013d50: 681b ldr r3, [r3, #0] 8013d52: 689b ldr r3, [r3, #8] 8013d54: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8013d58: 687b ldr r3, [r7, #4] 8013d5a: 681b ldr r3, [r3, #0] 8013d5c: 683a ldr r2, [r7, #0] 8013d5e: 430a orrs r2, r1 8013d60: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013d62: 6878 ldr r0, [r7, #4] 8013d64: f000 f8a0 bl 8013ea8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013d68: 687b ldr r3, [r7, #4] 8013d6a: 681b ldr r3, [r3, #0] 8013d6c: 68fa ldr r2, [r7, #12] 8013d6e: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013d70: 687b ldr r3, [r7, #4] 8013d72: 2220 movs r2, #32 8013d74: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013d78: 687b ldr r3, [r7, #4] 8013d7a: 2200 movs r2, #0 8013d7c: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013d80: 2300 movs r3, #0 } 8013d82: 4618 mov r0, r3 8013d84: 3710 adds r7, #16 8013d86: 46bd mov sp, r7 8013d88: bd80 pop {r7, pc} 08013d8a : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013d8a: b580 push {r7, lr} 8013d8c: b084 sub sp, #16 8013d8e: af00 add r7, sp, #0 8013d90: 6078 str r0, [r7, #4] 8013d92: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013d94: 687b ldr r3, [r7, #4] 8013d96: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013d9a: 2b01 cmp r3, #1 8013d9c: d101 bne.n 8013da2 8013d9e: 2302 movs r3, #2 8013da0: e02d b.n 8013dfe 8013da2: 687b ldr r3, [r7, #4] 8013da4: 2201 movs r2, #1 8013da6: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013daa: 687b ldr r3, [r7, #4] 8013dac: 2224 movs r2, #36 @ 0x24 8013dae: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013db2: 687b ldr r3, [r7, #4] 8013db4: 681b ldr r3, [r3, #0] 8013db6: 681b ldr r3, [r3, #0] 8013db8: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013dba: 687b ldr r3, [r7, #4] 8013dbc: 681b ldr r3, [r3, #0] 8013dbe: 681a ldr r2, [r3, #0] 8013dc0: 687b ldr r3, [r7, #4] 8013dc2: 681b ldr r3, [r3, #0] 8013dc4: f022 0201 bic.w r2, r2, #1 8013dc8: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8013dca: 687b ldr r3, [r7, #4] 8013dcc: 681b ldr r3, [r3, #0] 8013dce: 689b ldr r3, [r3, #8] 8013dd0: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8013dd4: 687b ldr r3, [r7, #4] 8013dd6: 681b ldr r3, [r3, #0] 8013dd8: 683a ldr r2, [r7, #0] 8013dda: 430a orrs r2, r1 8013ddc: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013dde: 6878 ldr r0, [r7, #4] 8013de0: f000 f862 bl 8013ea8 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013de4: 687b ldr r3, [r7, #4] 8013de6: 681b ldr r3, [r3, #0] 8013de8: 68fa ldr r2, [r7, #12] 8013dea: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013dec: 687b ldr r3, [r7, #4] 8013dee: 2220 movs r2, #32 8013df0: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013df4: 687b ldr r3, [r7, #4] 8013df6: 2200 movs r2, #0 8013df8: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013dfc: 2300 movs r3, #0 } 8013dfe: 4618 mov r0, r3 8013e00: 3710 adds r7, #16 8013e02: 46bd mov sp, r7 8013e04: bd80 pop {r7, pc} 08013e06 : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013e06: b580 push {r7, lr} 8013e08: b08c sub sp, #48 @ 0x30 8013e0a: af00 add r7, sp, #0 8013e0c: 60f8 str r0, [r7, #12] 8013e0e: 60b9 str r1, [r7, #8] 8013e10: 4613 mov r3, r2 8013e12: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 8013e14: 2300 movs r3, #0 8013e16: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8013e1a: 68fb ldr r3, [r7, #12] 8013e1c: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013e20: 2b20 cmp r3, #32 8013e22: d13b bne.n 8013e9c { if ((pData == NULL) || (Size == 0U)) 8013e24: 68bb ldr r3, [r7, #8] 8013e26: 2b00 cmp r3, #0 8013e28: d002 beq.n 8013e30 8013e2a: 88fb ldrh r3, [r7, #6] 8013e2c: 2b00 cmp r3, #0 8013e2e: d101 bne.n 8013e34 { return HAL_ERROR; 8013e30: 2301 movs r3, #1 8013e32: e034 b.n 8013e9e } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013e34: 68fb ldr r3, [r7, #12] 8013e36: 2201 movs r2, #1 8013e38: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8013e3a: 68fb ldr r3, [r7, #12] 8013e3c: 2200 movs r2, #0 8013e3e: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 8013e40: 88fb ldrh r3, [r7, #6] 8013e42: 461a mov r2, r3 8013e44: 68b9 ldr r1, [r7, #8] 8013e46: 68f8 ldr r0, [r7, #12] 8013e48: f7fe fe82 bl 8012b50 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013e4c: 68fb ldr r3, [r7, #12] 8013e4e: 6edb ldr r3, [r3, #108] @ 0x6c 8013e50: 2b01 cmp r3, #1 8013e52: d11d bne.n 8013e90 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013e54: 68fb ldr r3, [r7, #12] 8013e56: 681b ldr r3, [r3, #0] 8013e58: 2210 movs r2, #16 8013e5a: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013e5c: 68fb ldr r3, [r7, #12] 8013e5e: 681b ldr r3, [r3, #0] 8013e60: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e62: 69bb ldr r3, [r7, #24] 8013e64: e853 3f00 ldrex r3, [r3] 8013e68: 617b str r3, [r7, #20] return(result); 8013e6a: 697b ldr r3, [r7, #20] 8013e6c: f043 0310 orr.w r3, r3, #16 8013e70: 62bb str r3, [r7, #40] @ 0x28 8013e72: 68fb ldr r3, [r7, #12] 8013e74: 681b ldr r3, [r3, #0] 8013e76: 461a mov r2, r3 8013e78: 6abb ldr r3, [r7, #40] @ 0x28 8013e7a: 627b str r3, [r7, #36] @ 0x24 8013e7c: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e7e: 6a39 ldr r1, [r7, #32] 8013e80: 6a7a ldr r2, [r7, #36] @ 0x24 8013e82: e841 2300 strex r3, r2, [r1] 8013e86: 61fb str r3, [r7, #28] return(result); 8013e88: 69fb ldr r3, [r7, #28] 8013e8a: 2b00 cmp r3, #0 8013e8c: d1e6 bne.n 8013e5c 8013e8e: e002 b.n 8013e96 { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013e90: 2301 movs r3, #1 8013e92: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 8013e96: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8013e9a: e000 b.n 8013e9e } else { return HAL_BUSY; 8013e9c: 2302 movs r3, #2 } } 8013e9e: 4618 mov r0, r3 8013ea0: 3730 adds r7, #48 @ 0x30 8013ea2: 46bd mov sp, r7 8013ea4: bd80 pop {r7, pc} ... 08013ea8 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 8013ea8: b480 push {r7} 8013eaa: b085 sub sp, #20 8013eac: af00 add r7, sp, #0 8013eae: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8013eb0: 687b ldr r3, [r7, #4] 8013eb2: 6e5b ldr r3, [r3, #100] @ 0x64 8013eb4: 2b00 cmp r3, #0 8013eb6: d108 bne.n 8013eca { huart->NbTxDataToProcess = 1U; 8013eb8: 687b ldr r3, [r7, #4] 8013eba: 2201 movs r2, #1 8013ebc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 8013ec0: 687b ldr r3, [r7, #4] 8013ec2: 2201 movs r2, #1 8013ec4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 8013ec8: e031 b.n 8013f2e rx_fifo_depth = RX_FIFO_DEPTH; 8013eca: 2310 movs r3, #16 8013ecc: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 8013ece: 2310 movs r3, #16 8013ed0: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8013ed2: 687b ldr r3, [r7, #4] 8013ed4: 681b ldr r3, [r3, #0] 8013ed6: 689b ldr r3, [r3, #8] 8013ed8: 0e5b lsrs r3, r3, #25 8013eda: b2db uxtb r3, r3 8013edc: f003 0307 and.w r3, r3, #7 8013ee0: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8013ee2: 687b ldr r3, [r7, #4] 8013ee4: 681b ldr r3, [r3, #0] 8013ee6: 689b ldr r3, [r3, #8] 8013ee8: 0f5b lsrs r3, r3, #29 8013eea: b2db uxtb r3, r3 8013eec: f003 0307 and.w r3, r3, #7 8013ef0: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013ef2: 7bbb ldrb r3, [r7, #14] 8013ef4: 7b3a ldrb r2, [r7, #12] 8013ef6: 4911 ldr r1, [pc, #68] @ (8013f3c ) 8013ef8: 5c8a ldrb r2, [r1, r2] 8013efa: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 8013efe: 7b3a ldrb r2, [r7, #12] 8013f00: 490f ldr r1, [pc, #60] @ (8013f40 ) 8013f02: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013f04: fb93 f3f2 sdiv r3, r3, r2 8013f08: b29a uxth r2, r3 8013f0a: 687b ldr r3, [r7, #4] 8013f0c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013f10: 7bfb ldrb r3, [r7, #15] 8013f12: 7b7a ldrb r2, [r7, #13] 8013f14: 4909 ldr r1, [pc, #36] @ (8013f3c ) 8013f16: 5c8a ldrb r2, [r1, r2] 8013f18: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 8013f1c: 7b7a ldrb r2, [r7, #13] 8013f1e: 4908 ldr r1, [pc, #32] @ (8013f40 ) 8013f20: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013f22: fb93 f3f2 sdiv r3, r3, r2 8013f26: b29a uxth r2, r3 8013f28: 687b ldr r3, [r7, #4] 8013f2a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 8013f2e: bf00 nop 8013f30: 3714 adds r7, #20 8013f32: 46bd mov sp, r7 8013f34: f85d 7b04 ldr.w r7, [sp], #4 8013f38: 4770 bx lr 8013f3a: bf00 nop 8013f3c: 0801872c .word 0x0801872c 8013f40: 08018734 .word 0x08018734 08013f44 <__NVIC_SetPriority>: { 8013f44: b480 push {r7} 8013f46: b083 sub sp, #12 8013f48: af00 add r7, sp, #0 8013f4a: 4603 mov r3, r0 8013f4c: 6039 str r1, [r7, #0] 8013f4e: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8013f50: f9b7 3006 ldrsh.w r3, [r7, #6] 8013f54: 2b00 cmp r3, #0 8013f56: db0a blt.n 8013f6e <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013f58: 683b ldr r3, [r7, #0] 8013f5a: b2da uxtb r2, r3 8013f5c: 490c ldr r1, [pc, #48] @ (8013f90 <__NVIC_SetPriority+0x4c>) 8013f5e: f9b7 3006 ldrsh.w r3, [r7, #6] 8013f62: 0112 lsls r2, r2, #4 8013f64: b2d2 uxtb r2, r2 8013f66: 440b add r3, r1 8013f68: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8013f6c: e00a b.n 8013f84 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013f6e: 683b ldr r3, [r7, #0] 8013f70: b2da uxtb r2, r3 8013f72: 4908 ldr r1, [pc, #32] @ (8013f94 <__NVIC_SetPriority+0x50>) 8013f74: 88fb ldrh r3, [r7, #6] 8013f76: f003 030f and.w r3, r3, #15 8013f7a: 3b04 subs r3, #4 8013f7c: 0112 lsls r2, r2, #4 8013f7e: b2d2 uxtb r2, r2 8013f80: 440b add r3, r1 8013f82: 761a strb r2, [r3, #24] } 8013f84: bf00 nop 8013f86: 370c adds r7, #12 8013f88: 46bd mov sp, r7 8013f8a: f85d 7b04 ldr.w r7, [sp], #4 8013f8e: 4770 bx lr 8013f90: e000e100 .word 0xe000e100 8013f94: e000ed00 .word 0xe000ed00 08013f98 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 8013f98: b580 push {r7, lr} 8013f9a: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 8013f9c: 4b05 ldr r3, [pc, #20] @ (8013fb4 ) 8013f9e: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 8013fa0: f002 fd1e bl 80169e0 8013fa4: 4603 mov r3, r0 8013fa6: 2b01 cmp r3, #1 8013fa8: d001 beq.n 8013fae /* Call tick handler */ xPortSysTickHandler(); 8013faa: f003 ff2d bl 8017e08 } } 8013fae: bf00 nop 8013fb0: bd80 pop {r7, pc} 8013fb2: bf00 nop 8013fb4: e000e010 .word 0xe000e010 08013fb8 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 8013fb8: b580 push {r7, lr} 8013fba: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 8013fbc: 2100 movs r1, #0 8013fbe: f06f 0004 mvn.w r0, #4 8013fc2: f7ff ffbf bl 8013f44 <__NVIC_SetPriority> #endif } 8013fc6: bf00 nop 8013fc8: bd80 pop {r7, pc} ... 08013fcc : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 8013fcc: b480 push {r7} 8013fce: b083 sub sp, #12 8013fd0: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013fd2: f3ef 8305 mrs r3, IPSR 8013fd6: 603b str r3, [r7, #0] return(result); 8013fd8: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8013fda: 2b00 cmp r3, #0 8013fdc: d003 beq.n 8013fe6 stat = osErrorISR; 8013fde: f06f 0305 mvn.w r3, #5 8013fe2: 607b str r3, [r7, #4] 8013fe4: e00c b.n 8014000 } else { if (KernelState == osKernelInactive) { 8013fe6: 4b0a ldr r3, [pc, #40] @ (8014010 ) 8013fe8: 681b ldr r3, [r3, #0] 8013fea: 2b00 cmp r3, #0 8013fec: d105 bne.n 8013ffa EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 8013fee: 4b08 ldr r3, [pc, #32] @ (8014010 ) 8013ff0: 2201 movs r2, #1 8013ff2: 601a str r2, [r3, #0] stat = osOK; 8013ff4: 2300 movs r3, #0 8013ff6: 607b str r3, [r7, #4] 8013ff8: e002 b.n 8014000 } else { stat = osError; 8013ffa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8013ffe: 607b str r3, [r7, #4] } } return (stat); 8014000: 687b ldr r3, [r7, #4] } 8014002: 4618 mov r0, r3 8014004: 370c adds r7, #12 8014006: 46bd mov sp, r7 8014008: f85d 7b04 ldr.w r7, [sp], #4 801400c: 4770 bx lr 801400e: bf00 nop 8014010: 24001064 .word 0x24001064 08014014 : } return (state); } osStatus_t osKernelStart (void) { 8014014: b580 push {r7, lr} 8014016: b082 sub sp, #8 8014018: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801401a: f3ef 8305 mrs r3, IPSR 801401e: 603b str r3, [r7, #0] return(result); 8014020: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8014022: 2b00 cmp r3, #0 8014024: d003 beq.n 801402e stat = osErrorISR; 8014026: f06f 0305 mvn.w r3, #5 801402a: 607b str r3, [r7, #4] 801402c: e010 b.n 8014050 } else { if (KernelState == osKernelReady) { 801402e: 4b0b ldr r3, [pc, #44] @ (801405c ) 8014030: 681b ldr r3, [r3, #0] 8014032: 2b01 cmp r3, #1 8014034: d109 bne.n 801404a /* Ensure SVC priority is at the reset value */ SVC_Setup(); 8014036: f7ff ffbf bl 8013fb8 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 801403a: 4b08 ldr r3, [pc, #32] @ (801405c ) 801403c: 2202 movs r2, #2 801403e: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 8014040: f002 f824 bl 801608c stat = osOK; 8014044: 2300 movs r3, #0 8014046: 607b str r3, [r7, #4] 8014048: e002 b.n 8014050 } else { stat = osError; 801404a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801404e: 607b str r3, [r7, #4] } } return (stat); 8014050: 687b ldr r3, [r7, #4] } 8014052: 4618 mov r0, r3 8014054: 3708 adds r7, #8 8014056: 46bd mov sp, r7 8014058: bd80 pop {r7, pc} 801405a: bf00 nop 801405c: 24001064 .word 0x24001064 08014060 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 8014060: b580 push {r7, lr} 8014062: b08e sub sp, #56 @ 0x38 8014064: af04 add r7, sp, #16 8014066: 60f8 str r0, [r7, #12] 8014068: 60b9 str r1, [r7, #8] 801406a: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 801406c: 2300 movs r3, #0 801406e: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014070: f3ef 8305 mrs r3, IPSR 8014074: 617b str r3, [r7, #20] return(result); 8014076: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 8014078: 2b00 cmp r3, #0 801407a: d17f bne.n 801417c 801407c: 68fb ldr r3, [r7, #12] 801407e: 2b00 cmp r3, #0 8014080: d07c beq.n 801417c stack = configMINIMAL_STACK_SIZE; 8014082: f44f 7300 mov.w r3, #512 @ 0x200 8014086: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 8014088: 2318 movs r3, #24 801408a: 61fb str r3, [r7, #28] name = NULL; 801408c: 2300 movs r3, #0 801408e: 627b str r3, [r7, #36] @ 0x24 mem = -1; 8014090: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014094: 61bb str r3, [r7, #24] if (attr != NULL) { 8014096: 687b ldr r3, [r7, #4] 8014098: 2b00 cmp r3, #0 801409a: d045 beq.n 8014128 if (attr->name != NULL) { 801409c: 687b ldr r3, [r7, #4] 801409e: 681b ldr r3, [r3, #0] 80140a0: 2b00 cmp r3, #0 80140a2: d002 beq.n 80140aa name = attr->name; 80140a4: 687b ldr r3, [r7, #4] 80140a6: 681b ldr r3, [r3, #0] 80140a8: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 80140aa: 687b ldr r3, [r7, #4] 80140ac: 699b ldr r3, [r3, #24] 80140ae: 2b00 cmp r3, #0 80140b0: d002 beq.n 80140b8 prio = (UBaseType_t)attr->priority; 80140b2: 687b ldr r3, [r7, #4] 80140b4: 699b ldr r3, [r3, #24] 80140b6: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 80140b8: 69fb ldr r3, [r7, #28] 80140ba: 2b00 cmp r3, #0 80140bc: d008 beq.n 80140d0 80140be: 69fb ldr r3, [r7, #28] 80140c0: 2b38 cmp r3, #56 @ 0x38 80140c2: d805 bhi.n 80140d0 80140c4: 687b ldr r3, [r7, #4] 80140c6: 685b ldr r3, [r3, #4] 80140c8: f003 0301 and.w r3, r3, #1 80140cc: 2b00 cmp r3, #0 80140ce: d001 beq.n 80140d4 return (NULL); 80140d0: 2300 movs r3, #0 80140d2: e054 b.n 801417e } if (attr->stack_size > 0U) { 80140d4: 687b ldr r3, [r7, #4] 80140d6: 695b ldr r3, [r3, #20] 80140d8: 2b00 cmp r3, #0 80140da: d003 beq.n 80140e4 /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 80140dc: 687b ldr r3, [r7, #4] 80140de: 695b ldr r3, [r3, #20] 80140e0: 089b lsrs r3, r3, #2 80140e2: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80140e4: 687b ldr r3, [r7, #4] 80140e6: 689b ldr r3, [r3, #8] 80140e8: 2b00 cmp r3, #0 80140ea: d00e beq.n 801410a 80140ec: 687b ldr r3, [r7, #4] 80140ee: 68db ldr r3, [r3, #12] 80140f0: 2ba7 cmp r3, #167 @ 0xa7 80140f2: d90a bls.n 801410a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80140f4: 687b ldr r3, [r7, #4] 80140f6: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80140f8: 2b00 cmp r3, #0 80140fa: d006 beq.n 801410a (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80140fc: 687b ldr r3, [r7, #4] 80140fe: 695b ldr r3, [r3, #20] 8014100: 2b00 cmp r3, #0 8014102: d002 beq.n 801410a mem = 1; 8014104: 2301 movs r3, #1 8014106: 61bb str r3, [r7, #24] 8014108: e010 b.n 801412c } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 801410a: 687b ldr r3, [r7, #4] 801410c: 689b ldr r3, [r3, #8] 801410e: 2b00 cmp r3, #0 8014110: d10c bne.n 801412c 8014112: 687b ldr r3, [r7, #4] 8014114: 68db ldr r3, [r3, #12] 8014116: 2b00 cmp r3, #0 8014118: d108 bne.n 801412c 801411a: 687b ldr r3, [r7, #4] 801411c: 691b ldr r3, [r3, #16] 801411e: 2b00 cmp r3, #0 8014120: d104 bne.n 801412c mem = 0; 8014122: 2300 movs r3, #0 8014124: 61bb str r3, [r7, #24] 8014126: e001 b.n 801412c } } } else { mem = 0; 8014128: 2300 movs r3, #0 801412a: 61bb str r3, [r7, #24] } if (mem == 1) { 801412c: 69bb ldr r3, [r7, #24] 801412e: 2b01 cmp r3, #1 8014130: d110 bne.n 8014154 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8014132: 687b ldr r3, [r7, #4] 8014134: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 8014136: 687a ldr r2, [r7, #4] 8014138: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 801413a: 9202 str r2, [sp, #8] 801413c: 9301 str r3, [sp, #4] 801413e: 69fb ldr r3, [r7, #28] 8014140: 9300 str r3, [sp, #0] 8014142: 68bb ldr r3, [r7, #8] 8014144: 6a3a ldr r2, [r7, #32] 8014146: 6a79 ldr r1, [r7, #36] @ 0x24 8014148: 68f8 ldr r0, [r7, #12] 801414a: f001 fdac bl 8015ca6 801414e: 4603 mov r3, r0 8014150: 613b str r3, [r7, #16] 8014152: e013 b.n 801417c #endif } else { if (mem == 0) { 8014154: 69bb ldr r3, [r7, #24] 8014156: 2b00 cmp r3, #0 8014158: d110 bne.n 801417c #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 801415a: 6a3b ldr r3, [r7, #32] 801415c: b29a uxth r2, r3 801415e: f107 0310 add.w r3, r7, #16 8014162: 9301 str r3, [sp, #4] 8014164: 69fb ldr r3, [r7, #28] 8014166: 9300 str r3, [sp, #0] 8014168: 68bb ldr r3, [r7, #8] 801416a: 6a79 ldr r1, [r7, #36] @ 0x24 801416c: 68f8 ldr r0, [r7, #12] 801416e: f001 fdfa bl 8015d66 8014172: 4603 mov r3, r0 8014174: 2b01 cmp r3, #1 8014176: d001 beq.n 801417c hTask = NULL; 8014178: 2300 movs r3, #0 801417a: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 801417c: 693b ldr r3, [r7, #16] } 801417e: 4618 mov r0, r3 8014180: 3728 adds r7, #40 @ 0x28 8014182: 46bd mov sp, r7 8014184: bd80 pop {r7, pc} 08014186 : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 8014186: b580 push {r7, lr} 8014188: b084 sub sp, #16 801418a: af00 add r7, sp, #0 801418c: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801418e: f3ef 8305 mrs r3, IPSR 8014192: 60bb str r3, [r7, #8] return(result); 8014194: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 8014196: 2b00 cmp r3, #0 8014198: d003 beq.n 80141a2 stat = osErrorISR; 801419a: f06f 0305 mvn.w r3, #5 801419e: 60fb str r3, [r7, #12] 80141a0: e007 b.n 80141b2 } else { stat = osOK; 80141a2: 2300 movs r3, #0 80141a4: 60fb str r3, [r7, #12] if (ticks != 0U) { 80141a6: 687b ldr r3, [r7, #4] 80141a8: 2b00 cmp r3, #0 80141aa: d002 beq.n 80141b2 vTaskDelay(ticks); 80141ac: 6878 ldr r0, [r7, #4] 80141ae: f001 ff37 bl 8016020 } } return (stat); 80141b2: 68fb ldr r3, [r7, #12] } 80141b4: 4618 mov r0, r3 80141b6: 3710 adds r7, #16 80141b8: 46bd mov sp, r7 80141ba: bd80 pop {r7, pc} 080141bc : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 80141bc: b580 push {r7, lr} 80141be: b084 sub sp, #16 80141c0: af00 add r7, sp, #0 80141c2: 6078 str r0, [r7, #4] TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 80141c4: 6878 ldr r0, [r7, #4] 80141c6: f003 fc3d bl 8017a44 80141ca: 60f8 str r0, [r7, #12] if (callb != NULL) { 80141cc: 68fb ldr r3, [r7, #12] 80141ce: 2b00 cmp r3, #0 80141d0: d005 beq.n 80141de callb->func (callb->arg); 80141d2: 68fb ldr r3, [r7, #12] 80141d4: 681b ldr r3, [r3, #0] 80141d6: 68fa ldr r2, [r7, #12] 80141d8: 6852 ldr r2, [r2, #4] 80141da: 4610 mov r0, r2 80141dc: 4798 blx r3 } } 80141de: bf00 nop 80141e0: 3710 adds r7, #16 80141e2: 46bd mov sp, r7 80141e4: bd80 pop {r7, pc} ... 080141e8 : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 80141e8: b580 push {r7, lr} 80141ea: b08c sub sp, #48 @ 0x30 80141ec: af02 add r7, sp, #8 80141ee: 60f8 str r0, [r7, #12] 80141f0: 607a str r2, [r7, #4] 80141f2: 603b str r3, [r7, #0] 80141f4: 460b mov r3, r1 80141f6: 72fb strb r3, [r7, #11] TimerHandle_t hTimer; TimerCallback_t *callb; UBaseType_t reload; int32_t mem; hTimer = NULL; 80141f8: 2300 movs r3, #0 80141fa: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80141fc: f3ef 8305 mrs r3, IPSR 8014200: 613b str r3, [r7, #16] return(result); 8014202: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (func != NULL)) { 8014204: 2b00 cmp r3, #0 8014206: d163 bne.n 80142d0 8014208: 68fb ldr r3, [r7, #12] 801420a: 2b00 cmp r3, #0 801420c: d060 beq.n 80142d0 /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 801420e: 2008 movs r0, #8 8014210: f003 fe8c bl 8017f2c 8014214: 6178 str r0, [r7, #20] if (callb != NULL) { 8014216: 697b ldr r3, [r7, #20] 8014218: 2b00 cmp r3, #0 801421a: d059 beq.n 80142d0 callb->func = func; 801421c: 697b ldr r3, [r7, #20] 801421e: 68fa ldr r2, [r7, #12] 8014220: 601a str r2, [r3, #0] callb->arg = argument; 8014222: 697b ldr r3, [r7, #20] 8014224: 687a ldr r2, [r7, #4] 8014226: 605a str r2, [r3, #4] if (type == osTimerOnce) { 8014228: 7afb ldrb r3, [r7, #11] 801422a: 2b00 cmp r3, #0 801422c: d102 bne.n 8014234 reload = pdFALSE; 801422e: 2300 movs r3, #0 8014230: 61fb str r3, [r7, #28] 8014232: e001 b.n 8014238 } else { reload = pdTRUE; 8014234: 2301 movs r3, #1 8014236: 61fb str r3, [r7, #28] } mem = -1; 8014238: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801423c: 61bb str r3, [r7, #24] name = NULL; 801423e: 2300 movs r3, #0 8014240: 627b str r3, [r7, #36] @ 0x24 if (attr != NULL) { 8014242: 683b ldr r3, [r7, #0] 8014244: 2b00 cmp r3, #0 8014246: d01c beq.n 8014282 if (attr->name != NULL) { 8014248: 683b ldr r3, [r7, #0] 801424a: 681b ldr r3, [r3, #0] 801424c: 2b00 cmp r3, #0 801424e: d002 beq.n 8014256 name = attr->name; 8014250: 683b ldr r3, [r7, #0] 8014252: 681b ldr r3, [r3, #0] 8014254: 627b str r3, [r7, #36] @ 0x24 } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 8014256: 683b ldr r3, [r7, #0] 8014258: 689b ldr r3, [r3, #8] 801425a: 2b00 cmp r3, #0 801425c: d006 beq.n 801426c 801425e: 683b ldr r3, [r7, #0] 8014260: 68db ldr r3, [r3, #12] 8014262: 2b2b cmp r3, #43 @ 0x2b 8014264: d902 bls.n 801426c mem = 1; 8014266: 2301 movs r3, #1 8014268: 61bb str r3, [r7, #24] 801426a: e00c b.n 8014286 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 801426c: 683b ldr r3, [r7, #0] 801426e: 689b ldr r3, [r3, #8] 8014270: 2b00 cmp r3, #0 8014272: d108 bne.n 8014286 8014274: 683b ldr r3, [r7, #0] 8014276: 68db ldr r3, [r3, #12] 8014278: 2b00 cmp r3, #0 801427a: d104 bne.n 8014286 mem = 0; 801427c: 2300 movs r3, #0 801427e: 61bb str r3, [r7, #24] 8014280: e001 b.n 8014286 } } } else { mem = 0; 8014282: 2300 movs r3, #0 8014284: 61bb str r3, [r7, #24] } if (mem == 1) { 8014286: 69bb ldr r3, [r7, #24] 8014288: 2b01 cmp r3, #1 801428a: d10c bne.n 80142a6 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 801428c: 683b ldr r3, [r7, #0] 801428e: 689b ldr r3, [r3, #8] 8014290: 9301 str r3, [sp, #4] 8014292: 4b12 ldr r3, [pc, #72] @ (80142dc ) 8014294: 9300 str r3, [sp, #0] 8014296: 697b ldr r3, [r7, #20] 8014298: 69fa ldr r2, [r7, #28] 801429a: 2101 movs r1, #1 801429c: 6a78 ldr r0, [r7, #36] @ 0x24 801429e: f003 f81a bl 80172d6 80142a2: 6238 str r0, [r7, #32] 80142a4: e00b b.n 80142be #endif } else { if (mem == 0) { 80142a6: 69bb ldr r3, [r7, #24] 80142a8: 2b00 cmp r3, #0 80142aa: d108 bne.n 80142be #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 80142ac: 4b0b ldr r3, [pc, #44] @ (80142dc ) 80142ae: 9300 str r3, [sp, #0] 80142b0: 697b ldr r3, [r7, #20] 80142b2: 69fa ldr r2, [r7, #28] 80142b4: 2101 movs r1, #1 80142b6: 6a78 ldr r0, [r7, #36] @ 0x24 80142b8: f002 ffec bl 8017294 80142bc: 6238 str r0, [r7, #32] #endif } } if ((hTimer == NULL) && (callb != NULL)) { 80142be: 6a3b ldr r3, [r7, #32] 80142c0: 2b00 cmp r3, #0 80142c2: d105 bne.n 80142d0 80142c4: 697b ldr r3, [r7, #20] 80142c6: 2b00 cmp r3, #0 80142c8: d002 beq.n 80142d0 vPortFree (callb); 80142ca: 6978 ldr r0, [r7, #20] 80142cc: f003 fefc bl 80180c8 } } } return ((osTimerId_t)hTimer); 80142d0: 6a3b ldr r3, [r7, #32] } 80142d2: 4618 mov r0, r3 80142d4: 3728 adds r7, #40 @ 0x28 80142d6: 46bd mov sp, r7 80142d8: bd80 pop {r7, pc} 80142da: bf00 nop 80142dc: 080141bd .word 0x080141bd 080142e0 : } return (p); } osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 80142e0: b580 push {r7, lr} 80142e2: b088 sub sp, #32 80142e4: af02 add r7, sp, #8 80142e6: 6078 str r0, [r7, #4] 80142e8: 6039 str r1, [r7, #0] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 80142ea: 687b ldr r3, [r7, #4] 80142ec: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80142ee: f3ef 8305 mrs r3, IPSR 80142f2: 60fb str r3, [r7, #12] return(result); 80142f4: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 80142f6: 2b00 cmp r3, #0 80142f8: d003 beq.n 8014302 stat = osErrorISR; 80142fa: f06f 0305 mvn.w r3, #5 80142fe: 617b str r3, [r7, #20] 8014300: e017 b.n 8014332 } else if (hTimer == NULL) { 8014302: 693b ldr r3, [r7, #16] 8014304: 2b00 cmp r3, #0 8014306: d103 bne.n 8014310 stat = osErrorParameter; 8014308: f06f 0303 mvn.w r3, #3 801430c: 617b str r3, [r7, #20] 801430e: e010 b.n 8014332 } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 8014310: 2300 movs r3, #0 8014312: 9300 str r3, [sp, #0] 8014314: 2300 movs r3, #0 8014316: 683a ldr r2, [r7, #0] 8014318: 2104 movs r1, #4 801431a: 6938 ldr r0, [r7, #16] 801431c: f003 f858 bl 80173d0 8014320: 4603 mov r3, r0 8014322: 2b01 cmp r3, #1 8014324: d102 bne.n 801432c stat = osOK; 8014326: 2300 movs r3, #0 8014328: 617b str r3, [r7, #20] 801432a: e002 b.n 8014332 } else { stat = osErrorResource; 801432c: f06f 0302 mvn.w r3, #2 8014330: 617b str r3, [r7, #20] } } return (stat); 8014332: 697b ldr r3, [r7, #20] } 8014334: 4618 mov r0, r3 8014336: 3718 adds r7, #24 8014338: 46bd mov sp, r7 801433a: bd80 pop {r7, pc} 0801433c : osStatus_t osTimerStop (osTimerId_t timer_id) { 801433c: b580 push {r7, lr} 801433e: b088 sub sp, #32 8014340: af02 add r7, sp, #8 8014342: 6078 str r0, [r7, #4] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 8014344: 687b ldr r3, [r7, #4] 8014346: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014348: f3ef 8305 mrs r3, IPSR 801434c: 60fb str r3, [r7, #12] return(result); 801434e: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 8014350: 2b00 cmp r3, #0 8014352: d003 beq.n 801435c stat = osErrorISR; 8014354: f06f 0305 mvn.w r3, #5 8014358: 617b str r3, [r7, #20] 801435a: e021 b.n 80143a0 } else if (hTimer == NULL) { 801435c: 693b ldr r3, [r7, #16] 801435e: 2b00 cmp r3, #0 8014360: d103 bne.n 801436a stat = osErrorParameter; 8014362: f06f 0303 mvn.w r3, #3 8014366: 617b str r3, [r7, #20] 8014368: e01a b.n 80143a0 } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 801436a: 6938 ldr r0, [r7, #16] 801436c: f003 fb40 bl 80179f0 8014370: 4603 mov r3, r0 8014372: 2b00 cmp r3, #0 8014374: d103 bne.n 801437e stat = osErrorResource; 8014376: f06f 0302 mvn.w r3, #2 801437a: 617b str r3, [r7, #20] 801437c: e010 b.n 80143a0 } else { if (xTimerStop (hTimer, 0) == pdPASS) { 801437e: 2300 movs r3, #0 8014380: 9300 str r3, [sp, #0] 8014382: 2300 movs r3, #0 8014384: 2200 movs r2, #0 8014386: 2103 movs r1, #3 8014388: 6938 ldr r0, [r7, #16] 801438a: f003 f821 bl 80173d0 801438e: 4603 mov r3, r0 8014390: 2b01 cmp r3, #1 8014392: d102 bne.n 801439a stat = osOK; 8014394: 2300 movs r3, #0 8014396: 617b str r3, [r7, #20] 8014398: e002 b.n 80143a0 } else { stat = osError; 801439a: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801439e: 617b str r3, [r7, #20] } } } return (stat); 80143a0: 697b ldr r3, [r7, #20] } 80143a2: 4618 mov r0, r3 80143a4: 3718 adds r7, #24 80143a6: 46bd mov sp, r7 80143a8: bd80 pop {r7, pc} 080143aa : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 80143aa: b580 push {r7, lr} 80143ac: b088 sub sp, #32 80143ae: af00 add r7, sp, #0 80143b0: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 80143b2: 2300 movs r3, #0 80143b4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80143b6: f3ef 8305 mrs r3, IPSR 80143ba: 60bb str r3, [r7, #8] return(result); 80143bc: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 80143be: 2b00 cmp r3, #0 80143c0: d174 bne.n 80144ac if (attr != NULL) { 80143c2: 687b ldr r3, [r7, #4] 80143c4: 2b00 cmp r3, #0 80143c6: d003 beq.n 80143d0 type = attr->attr_bits; 80143c8: 687b ldr r3, [r7, #4] 80143ca: 685b ldr r3, [r3, #4] 80143cc: 61bb str r3, [r7, #24] 80143ce: e001 b.n 80143d4 } else { type = 0U; 80143d0: 2300 movs r3, #0 80143d2: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 80143d4: 69bb ldr r3, [r7, #24] 80143d6: f003 0301 and.w r3, r3, #1 80143da: 2b00 cmp r3, #0 80143dc: d002 beq.n 80143e4 rmtx = 1U; 80143de: 2301 movs r3, #1 80143e0: 617b str r3, [r7, #20] 80143e2: e001 b.n 80143e8 } else { rmtx = 0U; 80143e4: 2300 movs r3, #0 80143e6: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 80143e8: 69bb ldr r3, [r7, #24] 80143ea: f003 0308 and.w r3, r3, #8 80143ee: 2b00 cmp r3, #0 80143f0: d15c bne.n 80144ac mem = -1; 80143f2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80143f6: 613b str r3, [r7, #16] if (attr != NULL) { 80143f8: 687b ldr r3, [r7, #4] 80143fa: 2b00 cmp r3, #0 80143fc: d015 beq.n 801442a if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 80143fe: 687b ldr r3, [r7, #4] 8014400: 689b ldr r3, [r3, #8] 8014402: 2b00 cmp r3, #0 8014404: d006 beq.n 8014414 8014406: 687b ldr r3, [r7, #4] 8014408: 68db ldr r3, [r3, #12] 801440a: 2b4f cmp r3, #79 @ 0x4f 801440c: d902 bls.n 8014414 mem = 1; 801440e: 2301 movs r3, #1 8014410: 613b str r3, [r7, #16] 8014412: e00c b.n 801442e } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8014414: 687b ldr r3, [r7, #4] 8014416: 689b ldr r3, [r3, #8] 8014418: 2b00 cmp r3, #0 801441a: d108 bne.n 801442e 801441c: 687b ldr r3, [r7, #4] 801441e: 68db ldr r3, [r3, #12] 8014420: 2b00 cmp r3, #0 8014422: d104 bne.n 801442e mem = 0; 8014424: 2300 movs r3, #0 8014426: 613b str r3, [r7, #16] 8014428: e001 b.n 801442e } } } else { mem = 0; 801442a: 2300 movs r3, #0 801442c: 613b str r3, [r7, #16] } if (mem == 1) { 801442e: 693b ldr r3, [r7, #16] 8014430: 2b01 cmp r3, #1 8014432: d112 bne.n 801445a #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 8014434: 697b ldr r3, [r7, #20] 8014436: 2b00 cmp r3, #0 8014438: d007 beq.n 801444a #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 801443a: 687b ldr r3, [r7, #4] 801443c: 689b ldr r3, [r3, #8] 801443e: 4619 mov r1, r3 8014440: 2004 movs r0, #4 8014442: f000 fc50 bl 8014ce6 8014446: 61f8 str r0, [r7, #28] 8014448: e016 b.n 8014478 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 801444a: 687b ldr r3, [r7, #4] 801444c: 689b ldr r3, [r3, #8] 801444e: 4619 mov r1, r3 8014450: 2001 movs r0, #1 8014452: f000 fc48 bl 8014ce6 8014456: 61f8 str r0, [r7, #28] 8014458: e00e b.n 8014478 } #endif } else { if (mem == 0) { 801445a: 693b ldr r3, [r7, #16] 801445c: 2b00 cmp r3, #0 801445e: d10b bne.n 8014478 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 8014460: 697b ldr r3, [r7, #20] 8014462: 2b00 cmp r3, #0 8014464: d004 beq.n 8014470 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 8014466: 2004 movs r0, #4 8014468: f000 fc25 bl 8014cb6 801446c: 61f8 str r0, [r7, #28] 801446e: e003 b.n 8014478 #endif } else { hMutex = xSemaphoreCreateMutex (); 8014470: 2001 movs r0, #1 8014472: f000 fc20 bl 8014cb6 8014476: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8014478: 69fb ldr r3, [r7, #28] 801447a: 2b00 cmp r3, #0 801447c: d00c beq.n 8014498 if (attr != NULL) { 801447e: 687b ldr r3, [r7, #4] 8014480: 2b00 cmp r3, #0 8014482: d003 beq.n 801448c name = attr->name; 8014484: 687b ldr r3, [r7, #4] 8014486: 681b ldr r3, [r3, #0] 8014488: 60fb str r3, [r7, #12] 801448a: e001 b.n 8014490 } else { name = NULL; 801448c: 2300 movs r3, #0 801448e: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 8014490: 68f9 ldr r1, [r7, #12] 8014492: 69f8 ldr r0, [r7, #28] 8014494: f001 f9ea bl 801586c } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 8014498: 69fb ldr r3, [r7, #28] 801449a: 2b00 cmp r3, #0 801449c: d006 beq.n 80144ac 801449e: 697b ldr r3, [r7, #20] 80144a0: 2b00 cmp r3, #0 80144a2: d003 beq.n 80144ac hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 80144a4: 69fb ldr r3, [r7, #28] 80144a6: f043 0301 orr.w r3, r3, #1 80144aa: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 80144ac: 69fb ldr r3, [r7, #28] } 80144ae: 4618 mov r0, r3 80144b0: 3720 adds r7, #32 80144b2: 46bd mov sp, r7 80144b4: bd80 pop {r7, pc} 080144b6 : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 80144b6: b580 push {r7, lr} 80144b8: b086 sub sp, #24 80144ba: af00 add r7, sp, #0 80144bc: 6078 str r0, [r7, #4] 80144be: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 80144c0: 687b ldr r3, [r7, #4] 80144c2: f023 0301 bic.w r3, r3, #1 80144c6: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 80144c8: 687b ldr r3, [r7, #4] 80144ca: f003 0301 and.w r3, r3, #1 80144ce: 60fb str r3, [r7, #12] stat = osOK; 80144d0: 2300 movs r3, #0 80144d2: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80144d4: f3ef 8305 mrs r3, IPSR 80144d8: 60bb str r3, [r7, #8] return(result); 80144da: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 80144dc: 2b00 cmp r3, #0 80144de: d003 beq.n 80144e8 stat = osErrorISR; 80144e0: f06f 0305 mvn.w r3, #5 80144e4: 617b str r3, [r7, #20] 80144e6: e02c b.n 8014542 } else if (hMutex == NULL) { 80144e8: 693b ldr r3, [r7, #16] 80144ea: 2b00 cmp r3, #0 80144ec: d103 bne.n 80144f6 stat = osErrorParameter; 80144ee: f06f 0303 mvn.w r3, #3 80144f2: 617b str r3, [r7, #20] 80144f4: e025 b.n 8014542 } else { if (rmtx != 0U) { 80144f6: 68fb ldr r3, [r7, #12] 80144f8: 2b00 cmp r3, #0 80144fa: d011 beq.n 8014520 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 80144fc: 6839 ldr r1, [r7, #0] 80144fe: 6938 ldr r0, [r7, #16] 8014500: f000 fc41 bl 8014d86 8014504: 4603 mov r3, r0 8014506: 2b01 cmp r3, #1 8014508: d01b beq.n 8014542 if (timeout != 0U) { 801450a: 683b ldr r3, [r7, #0] 801450c: 2b00 cmp r3, #0 801450e: d003 beq.n 8014518 stat = osErrorTimeout; 8014510: f06f 0301 mvn.w r3, #1 8014514: 617b str r3, [r7, #20] 8014516: e014 b.n 8014542 } else { stat = osErrorResource; 8014518: f06f 0302 mvn.w r3, #2 801451c: 617b str r3, [r7, #20] 801451e: e010 b.n 8014542 } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 8014520: 6839 ldr r1, [r7, #0] 8014522: 6938 ldr r0, [r7, #16] 8014524: f000 fee8 bl 80152f8 8014528: 4603 mov r3, r0 801452a: 2b01 cmp r3, #1 801452c: d009 beq.n 8014542 if (timeout != 0U) { 801452e: 683b ldr r3, [r7, #0] 8014530: 2b00 cmp r3, #0 8014532: d003 beq.n 801453c stat = osErrorTimeout; 8014534: f06f 0301 mvn.w r3, #1 8014538: 617b str r3, [r7, #20] 801453a: e002 b.n 8014542 } else { stat = osErrorResource; 801453c: f06f 0302 mvn.w r3, #2 8014540: 617b str r3, [r7, #20] } } } } return (stat); 8014542: 697b ldr r3, [r7, #20] } 8014544: 4618 mov r0, r3 8014546: 3718 adds r7, #24 8014548: 46bd mov sp, r7 801454a: bd80 pop {r7, pc} 0801454c : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 801454c: b580 push {r7, lr} 801454e: b086 sub sp, #24 8014550: af00 add r7, sp, #0 8014552: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 8014554: 687b ldr r3, [r7, #4] 8014556: f023 0301 bic.w r3, r3, #1 801455a: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 801455c: 687b ldr r3, [r7, #4] 801455e: f003 0301 and.w r3, r3, #1 8014562: 60fb str r3, [r7, #12] stat = osOK; 8014564: 2300 movs r3, #0 8014566: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014568: f3ef 8305 mrs r3, IPSR 801456c: 60bb str r3, [r7, #8] return(result); 801456e: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8014570: 2b00 cmp r3, #0 8014572: d003 beq.n 801457c stat = osErrorISR; 8014574: f06f 0305 mvn.w r3, #5 8014578: 617b str r3, [r7, #20] 801457a: e01f b.n 80145bc } else if (hMutex == NULL) { 801457c: 693b ldr r3, [r7, #16] 801457e: 2b00 cmp r3, #0 8014580: d103 bne.n 801458a stat = osErrorParameter; 8014582: f06f 0303 mvn.w r3, #3 8014586: 617b str r3, [r7, #20] 8014588: e018 b.n 80145bc } else { if (rmtx != 0U) { 801458a: 68fb ldr r3, [r7, #12] 801458c: 2b00 cmp r3, #0 801458e: d009 beq.n 80145a4 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 8014590: 6938 ldr r0, [r7, #16] 8014592: f000 fbc3 bl 8014d1c 8014596: 4603 mov r3, r0 8014598: 2b01 cmp r3, #1 801459a: d00f beq.n 80145bc stat = osErrorResource; 801459c: f06f 0302 mvn.w r3, #2 80145a0: 617b str r3, [r7, #20] 80145a2: e00b b.n 80145bc } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 80145a4: 2300 movs r3, #0 80145a6: 2200 movs r2, #0 80145a8: 2100 movs r1, #0 80145aa: 6938 ldr r0, [r7, #16] 80145ac: f000 fc22 bl 8014df4 80145b0: 4603 mov r3, r0 80145b2: 2b01 cmp r3, #1 80145b4: d002 beq.n 80145bc stat = osErrorResource; 80145b6: f06f 0302 mvn.w r3, #2 80145ba: 617b str r3, [r7, #20] } } } return (stat); 80145bc: 697b ldr r3, [r7, #20] } 80145be: 4618 mov r0, r3 80145c0: 3718 adds r7, #24 80145c2: 46bd mov sp, r7 80145c4: bd80 pop {r7, pc} 080145c6 : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 80145c6: b580 push {r7, lr} 80145c8: b08a sub sp, #40 @ 0x28 80145ca: af02 add r7, sp, #8 80145cc: 60f8 str r0, [r7, #12] 80145ce: 60b9 str r1, [r7, #8] 80145d0: 607a str r2, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hQueue = NULL; 80145d2: 2300 movs r3, #0 80145d4: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80145d6: f3ef 8305 mrs r3, IPSR 80145da: 613b str r3, [r7, #16] return(result); 80145dc: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 80145de: 2b00 cmp r3, #0 80145e0: d15f bne.n 80146a2 80145e2: 68fb ldr r3, [r7, #12] 80145e4: 2b00 cmp r3, #0 80145e6: d05c beq.n 80146a2 80145e8: 68bb ldr r3, [r7, #8] 80145ea: 2b00 cmp r3, #0 80145ec: d059 beq.n 80146a2 mem = -1; 80145ee: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80145f2: 61bb str r3, [r7, #24] if (attr != NULL) { 80145f4: 687b ldr r3, [r7, #4] 80145f6: 2b00 cmp r3, #0 80145f8: d029 beq.n 801464e if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 80145fa: 687b ldr r3, [r7, #4] 80145fc: 689b ldr r3, [r3, #8] 80145fe: 2b00 cmp r3, #0 8014600: d012 beq.n 8014628 8014602: 687b ldr r3, [r7, #4] 8014604: 68db ldr r3, [r3, #12] 8014606: 2b4f cmp r3, #79 @ 0x4f 8014608: d90e bls.n 8014628 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 801460a: 687b ldr r3, [r7, #4] 801460c: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 801460e: 2b00 cmp r3, #0 8014610: d00a beq.n 8014628 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8014612: 687b ldr r3, [r7, #4] 8014614: 695a ldr r2, [r3, #20] 8014616: 68fb ldr r3, [r7, #12] 8014618: 68b9 ldr r1, [r7, #8] 801461a: fb01 f303 mul.w r3, r1, r3 801461e: 429a cmp r2, r3 8014620: d302 bcc.n 8014628 mem = 1; 8014622: 2301 movs r3, #1 8014624: 61bb str r3, [r7, #24] 8014626: e014 b.n 8014652 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8014628: 687b ldr r3, [r7, #4] 801462a: 689b ldr r3, [r3, #8] 801462c: 2b00 cmp r3, #0 801462e: d110 bne.n 8014652 8014630: 687b ldr r3, [r7, #4] 8014632: 68db ldr r3, [r3, #12] 8014634: 2b00 cmp r3, #0 8014636: d10c bne.n 8014652 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8014638: 687b ldr r3, [r7, #4] 801463a: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 801463c: 2b00 cmp r3, #0 801463e: d108 bne.n 8014652 (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8014640: 687b ldr r3, [r7, #4] 8014642: 695b ldr r3, [r3, #20] 8014644: 2b00 cmp r3, #0 8014646: d104 bne.n 8014652 mem = 0; 8014648: 2300 movs r3, #0 801464a: 61bb str r3, [r7, #24] 801464c: e001 b.n 8014652 } } } else { mem = 0; 801464e: 2300 movs r3, #0 8014650: 61bb str r3, [r7, #24] } if (mem == 1) { 8014652: 69bb ldr r3, [r7, #24] 8014654: 2b01 cmp r3, #1 8014656: d10b bne.n 8014670 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8014658: 687b ldr r3, [r7, #4] 801465a: 691a ldr r2, [r3, #16] 801465c: 687b ldr r3, [r7, #4] 801465e: 689b ldr r3, [r3, #8] 8014660: 2100 movs r1, #0 8014662: 9100 str r1, [sp, #0] 8014664: 68b9 ldr r1, [r7, #8] 8014666: 68f8 ldr r0, [r7, #12] 8014668: f000 fa30 bl 8014acc 801466c: 61f8 str r0, [r7, #28] 801466e: e008 b.n 8014682 #endif } else { if (mem == 0) { 8014670: 69bb ldr r3, [r7, #24] 8014672: 2b00 cmp r3, #0 8014674: d105 bne.n 8014682 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 8014676: 2200 movs r2, #0 8014678: 68b9 ldr r1, [r7, #8] 801467a: 68f8 ldr r0, [r7, #12] 801467c: f000 faa3 bl 8014bc6 8014680: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 8014682: 69fb ldr r3, [r7, #28] 8014684: 2b00 cmp r3, #0 8014686: d00c beq.n 80146a2 if (attr != NULL) { 8014688: 687b ldr r3, [r7, #4] 801468a: 2b00 cmp r3, #0 801468c: d003 beq.n 8014696 name = attr->name; 801468e: 687b ldr r3, [r7, #4] 8014690: 681b ldr r3, [r3, #0] 8014692: 617b str r3, [r7, #20] 8014694: e001 b.n 801469a } else { name = NULL; 8014696: 2300 movs r3, #0 8014698: 617b str r3, [r7, #20] } vQueueAddToRegistry (hQueue, name); 801469a: 6979 ldr r1, [r7, #20] 801469c: 69f8 ldr r0, [r7, #28] 801469e: f001 f8e5 bl 801586c } #endif } return ((osMessageQueueId_t)hQueue); 80146a2: 69fb ldr r3, [r7, #28] } 80146a4: 4618 mov r0, r3 80146a6: 3720 adds r7, #32 80146a8: 46bd mov sp, r7 80146aa: bd80 pop {r7, pc} 080146ac : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 80146ac: b580 push {r7, lr} 80146ae: b088 sub sp, #32 80146b0: af00 add r7, sp, #0 80146b2: 60f8 str r0, [r7, #12] 80146b4: 60b9 str r1, [r7, #8] 80146b6: 603b str r3, [r7, #0] 80146b8: 4613 mov r3, r2 80146ba: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 80146bc: 68fb ldr r3, [r7, #12] 80146be: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 80146c0: 2300 movs r3, #0 80146c2: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80146c4: f3ef 8305 mrs r3, IPSR 80146c8: 617b str r3, [r7, #20] return(result); 80146ca: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 80146cc: 2b00 cmp r3, #0 80146ce: d028 beq.n 8014722 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 80146d0: 69bb ldr r3, [r7, #24] 80146d2: 2b00 cmp r3, #0 80146d4: d005 beq.n 80146e2 80146d6: 68bb ldr r3, [r7, #8] 80146d8: 2b00 cmp r3, #0 80146da: d002 beq.n 80146e2 80146dc: 683b ldr r3, [r7, #0] 80146de: 2b00 cmp r3, #0 80146e0: d003 beq.n 80146ea stat = osErrorParameter; 80146e2: f06f 0303 mvn.w r3, #3 80146e6: 61fb str r3, [r7, #28] 80146e8: e038 b.n 801475c } else { yield = pdFALSE; 80146ea: 2300 movs r3, #0 80146ec: 613b str r3, [r7, #16] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 80146ee: f107 0210 add.w r2, r7, #16 80146f2: 2300 movs r3, #0 80146f4: 68b9 ldr r1, [r7, #8] 80146f6: 69b8 ldr r0, [r7, #24] 80146f8: f000 fc7e bl 8014ff8 80146fc: 4603 mov r3, r0 80146fe: 2b01 cmp r3, #1 8014700: d003 beq.n 801470a stat = osErrorResource; 8014702: f06f 0302 mvn.w r3, #2 8014706: 61fb str r3, [r7, #28] 8014708: e028 b.n 801475c } else { portYIELD_FROM_ISR (yield); 801470a: 693b ldr r3, [r7, #16] 801470c: 2b00 cmp r3, #0 801470e: d025 beq.n 801475c 8014710: 4b15 ldr r3, [pc, #84] @ (8014768 ) 8014712: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014716: 601a str r2, [r3, #0] 8014718: f3bf 8f4f dsb sy 801471c: f3bf 8f6f isb sy 8014720: e01c b.n 801475c } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 8014722: 69bb ldr r3, [r7, #24] 8014724: 2b00 cmp r3, #0 8014726: d002 beq.n 801472e 8014728: 68bb ldr r3, [r7, #8] 801472a: 2b00 cmp r3, #0 801472c: d103 bne.n 8014736 stat = osErrorParameter; 801472e: f06f 0303 mvn.w r3, #3 8014732: 61fb str r3, [r7, #28] 8014734: e012 b.n 801475c } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 8014736: 2300 movs r3, #0 8014738: 683a ldr r2, [r7, #0] 801473a: 68b9 ldr r1, [r7, #8] 801473c: 69b8 ldr r0, [r7, #24] 801473e: f000 fb59 bl 8014df4 8014742: 4603 mov r3, r0 8014744: 2b01 cmp r3, #1 8014746: d009 beq.n 801475c if (timeout != 0U) { 8014748: 683b ldr r3, [r7, #0] 801474a: 2b00 cmp r3, #0 801474c: d003 beq.n 8014756 stat = osErrorTimeout; 801474e: f06f 0301 mvn.w r3, #1 8014752: 61fb str r3, [r7, #28] 8014754: e002 b.n 801475c } else { stat = osErrorResource; 8014756: f06f 0302 mvn.w r3, #2 801475a: 61fb str r3, [r7, #28] } } } } return (stat); 801475c: 69fb ldr r3, [r7, #28] } 801475e: 4618 mov r0, r3 8014760: 3720 adds r7, #32 8014762: 46bd mov sp, r7 8014764: bd80 pop {r7, pc} 8014766: bf00 nop 8014768: e000ed04 .word 0xe000ed04 0801476c : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 801476c: b580 push {r7, lr} 801476e: b088 sub sp, #32 8014770: af00 add r7, sp, #0 8014772: 60f8 str r0, [r7, #12] 8014774: 60b9 str r1, [r7, #8] 8014776: 607a str r2, [r7, #4] 8014778: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 801477a: 68fb ldr r3, [r7, #12] 801477c: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 801477e: 2300 movs r3, #0 8014780: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014782: f3ef 8305 mrs r3, IPSR 8014786: 617b str r3, [r7, #20] return(result); 8014788: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 801478a: 2b00 cmp r3, #0 801478c: d028 beq.n 80147e0 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 801478e: 69bb ldr r3, [r7, #24] 8014790: 2b00 cmp r3, #0 8014792: d005 beq.n 80147a0 8014794: 68bb ldr r3, [r7, #8] 8014796: 2b00 cmp r3, #0 8014798: d002 beq.n 80147a0 801479a: 683b ldr r3, [r7, #0] 801479c: 2b00 cmp r3, #0 801479e: d003 beq.n 80147a8 stat = osErrorParameter; 80147a0: f06f 0303 mvn.w r3, #3 80147a4: 61fb str r3, [r7, #28] 80147a6: e037 b.n 8014818 } else { yield = pdFALSE; 80147a8: 2300 movs r3, #0 80147aa: 613b str r3, [r7, #16] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 80147ac: f107 0310 add.w r3, r7, #16 80147b0: 461a mov r2, r3 80147b2: 68b9 ldr r1, [r7, #8] 80147b4: 69b8 ldr r0, [r7, #24] 80147b6: f000 feaf bl 8015518 80147ba: 4603 mov r3, r0 80147bc: 2b01 cmp r3, #1 80147be: d003 beq.n 80147c8 stat = osErrorResource; 80147c0: f06f 0302 mvn.w r3, #2 80147c4: 61fb str r3, [r7, #28] 80147c6: e027 b.n 8014818 } else { portYIELD_FROM_ISR (yield); 80147c8: 693b ldr r3, [r7, #16] 80147ca: 2b00 cmp r3, #0 80147cc: d024 beq.n 8014818 80147ce: 4b15 ldr r3, [pc, #84] @ (8014824 ) 80147d0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80147d4: 601a str r2, [r3, #0] 80147d6: f3bf 8f4f dsb sy 80147da: f3bf 8f6f isb sy 80147de: e01b b.n 8014818 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 80147e0: 69bb ldr r3, [r7, #24] 80147e2: 2b00 cmp r3, #0 80147e4: d002 beq.n 80147ec 80147e6: 68bb ldr r3, [r7, #8] 80147e8: 2b00 cmp r3, #0 80147ea: d103 bne.n 80147f4 stat = osErrorParameter; 80147ec: f06f 0303 mvn.w r3, #3 80147f0: 61fb str r3, [r7, #28] 80147f2: e011 b.n 8014818 } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 80147f4: 683a ldr r2, [r7, #0] 80147f6: 68b9 ldr r1, [r7, #8] 80147f8: 69b8 ldr r0, [r7, #24] 80147fa: f000 fc9b bl 8015134 80147fe: 4603 mov r3, r0 8014800: 2b01 cmp r3, #1 8014802: d009 beq.n 8014818 if (timeout != 0U) { 8014804: 683b ldr r3, [r7, #0] 8014806: 2b00 cmp r3, #0 8014808: d003 beq.n 8014812 stat = osErrorTimeout; 801480a: f06f 0301 mvn.w r3, #1 801480e: 61fb str r3, [r7, #28] 8014810: e002 b.n 8014818 } else { stat = osErrorResource; 8014812: f06f 0302 mvn.w r3, #2 8014816: 61fb str r3, [r7, #28] } } } } return (stat); 8014818: 69fb ldr r3, [r7, #28] } 801481a: 4618 mov r0, r3 801481c: 3720 adds r7, #32 801481e: 46bd mov sp, r7 8014820: bd80 pop {r7, pc} 8014822: bf00 nop 8014824: e000ed04 .word 0xe000ed04 08014828 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 8014828: b480 push {r7} 801482a: b085 sub sp, #20 801482c: af00 add r7, sp, #0 801482e: 60f8 str r0, [r7, #12] 8014830: 60b9 str r1, [r7, #8] 8014832: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 8014834: 68fb ldr r3, [r7, #12] 8014836: 4a07 ldr r2, [pc, #28] @ (8014854 ) 8014838: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 801483a: 68bb ldr r3, [r7, #8] 801483c: 4a06 ldr r2, [pc, #24] @ (8014858 ) 801483e: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8014840: 687b ldr r3, [r7, #4] 8014842: f44f 7200 mov.w r2, #512 @ 0x200 8014846: 601a str r2, [r3, #0] } 8014848: bf00 nop 801484a: 3714 adds r7, #20 801484c: 46bd mov sp, r7 801484e: f85d 7b04 ldr.w r7, [sp], #4 8014852: 4770 bx lr 8014854: 24001068 .word 0x24001068 8014858: 24001110 .word 0x24001110 0801485c : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 801485c: b480 push {r7} 801485e: b085 sub sp, #20 8014860: af00 add r7, sp, #0 8014862: 60f8 str r0, [r7, #12] 8014864: 60b9 str r1, [r7, #8] 8014866: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 8014868: 68fb ldr r3, [r7, #12] 801486a: 4a07 ldr r2, [pc, #28] @ (8014888 ) 801486c: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 801486e: 68bb ldr r3, [r7, #8] 8014870: 4a06 ldr r2, [pc, #24] @ (801488c ) 8014872: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 8014874: 687b ldr r3, [r7, #4] 8014876: f44f 6280 mov.w r2, #1024 @ 0x400 801487a: 601a str r2, [r3, #0] } 801487c: bf00 nop 801487e: 3714 adds r7, #20 8014880: 46bd mov sp, r7 8014882: f85d 7b04 ldr.w r7, [sp], #4 8014886: 4770 bx lr 8014888: 24001910 .word 0x24001910 801488c: 240019b8 .word 0x240019b8 08014890 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8014890: b480 push {r7} 8014892: b083 sub sp, #12 8014894: af00 add r7, sp, #0 8014896: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 8014898: 687b ldr r3, [r7, #4] 801489a: f103 0208 add.w r2, r3, #8 801489e: 687b ldr r3, [r7, #4] 80148a0: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 80148a2: 687b ldr r3, [r7, #4] 80148a4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80148a8: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80148aa: 687b ldr r3, [r7, #4] 80148ac: f103 0208 add.w r2, r3, #8 80148b0: 687b ldr r3, [r7, #4] 80148b2: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80148b4: 687b ldr r3, [r7, #4] 80148b6: f103 0208 add.w r2, r3, #8 80148ba: 687b ldr r3, [r7, #4] 80148bc: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 80148be: 687b ldr r3, [r7, #4] 80148c0: 2200 movs r2, #0 80148c2: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 80148c4: bf00 nop 80148c6: 370c adds r7, #12 80148c8: 46bd mov sp, r7 80148ca: f85d 7b04 ldr.w r7, [sp], #4 80148ce: 4770 bx lr 080148d0 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 80148d0: b480 push {r7} 80148d2: b083 sub sp, #12 80148d4: af00 add r7, sp, #0 80148d6: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 80148d8: 687b ldr r3, [r7, #4] 80148da: 2200 movs r2, #0 80148dc: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 80148de: bf00 nop 80148e0: 370c adds r7, #12 80148e2: 46bd mov sp, r7 80148e4: f85d 7b04 ldr.w r7, [sp], #4 80148e8: 4770 bx lr 080148ea : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 80148ea: b480 push {r7} 80148ec: b085 sub sp, #20 80148ee: af00 add r7, sp, #0 80148f0: 6078 str r0, [r7, #4] 80148f2: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 80148f4: 687b ldr r3, [r7, #4] 80148f6: 685b ldr r3, [r3, #4] 80148f8: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 80148fa: 683b ldr r3, [r7, #0] 80148fc: 68fa ldr r2, [r7, #12] 80148fe: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8014900: 68fb ldr r3, [r7, #12] 8014902: 689a ldr r2, [r3, #8] 8014904: 683b ldr r3, [r7, #0] 8014906: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8014908: 68fb ldr r3, [r7, #12] 801490a: 689b ldr r3, [r3, #8] 801490c: 683a ldr r2, [r7, #0] 801490e: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8014910: 68fb ldr r3, [r7, #12] 8014912: 683a ldr r2, [r7, #0] 8014914: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8014916: 683b ldr r3, [r7, #0] 8014918: 687a ldr r2, [r7, #4] 801491a: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 801491c: 687b ldr r3, [r7, #4] 801491e: 681b ldr r3, [r3, #0] 8014920: 1c5a adds r2, r3, #1 8014922: 687b ldr r3, [r7, #4] 8014924: 601a str r2, [r3, #0] } 8014926: bf00 nop 8014928: 3714 adds r7, #20 801492a: 46bd mov sp, r7 801492c: f85d 7b04 ldr.w r7, [sp], #4 8014930: 4770 bx lr 08014932 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8014932: b480 push {r7} 8014934: b085 sub sp, #20 8014936: af00 add r7, sp, #0 8014938: 6078 str r0, [r7, #4] 801493a: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 801493c: 683b ldr r3, [r7, #0] 801493e: 681b ldr r3, [r3, #0] 8014940: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8014942: 68bb ldr r3, [r7, #8] 8014944: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014948: d103 bne.n 8014952 { pxIterator = pxList->xListEnd.pxPrevious; 801494a: 687b ldr r3, [r7, #4] 801494c: 691b ldr r3, [r3, #16] 801494e: 60fb str r3, [r7, #12] 8014950: e00c b.n 801496c 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8014952: 687b ldr r3, [r7, #4] 8014954: 3308 adds r3, #8 8014956: 60fb str r3, [r7, #12] 8014958: e002 b.n 8014960 801495a: 68fb ldr r3, [r7, #12] 801495c: 685b ldr r3, [r3, #4] 801495e: 60fb str r3, [r7, #12] 8014960: 68fb ldr r3, [r7, #12] 8014962: 685b ldr r3, [r3, #4] 8014964: 681b ldr r3, [r3, #0] 8014966: 68ba ldr r2, [r7, #8] 8014968: 429a cmp r2, r3 801496a: d2f6 bcs.n 801495a /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 801496c: 68fb ldr r3, [r7, #12] 801496e: 685a ldr r2, [r3, #4] 8014970: 683b ldr r3, [r7, #0] 8014972: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8014974: 683b ldr r3, [r7, #0] 8014976: 685b ldr r3, [r3, #4] 8014978: 683a ldr r2, [r7, #0] 801497a: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 801497c: 683b ldr r3, [r7, #0] 801497e: 68fa ldr r2, [r7, #12] 8014980: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8014982: 68fb ldr r3, [r7, #12] 8014984: 683a ldr r2, [r7, #0] 8014986: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8014988: 683b ldr r3, [r7, #0] 801498a: 687a ldr r2, [r7, #4] 801498c: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 801498e: 687b ldr r3, [r7, #4] 8014990: 681b ldr r3, [r3, #0] 8014992: 1c5a adds r2, r3, #1 8014994: 687b ldr r3, [r7, #4] 8014996: 601a str r2, [r3, #0] } 8014998: bf00 nop 801499a: 3714 adds r7, #20 801499c: 46bd mov sp, r7 801499e: f85d 7b04 ldr.w r7, [sp], #4 80149a2: 4770 bx lr 080149a4 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 80149a4: b480 push {r7} 80149a6: b085 sub sp, #20 80149a8: af00 add r7, sp, #0 80149aa: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 80149ac: 687b ldr r3, [r7, #4] 80149ae: 691b ldr r3, [r3, #16] 80149b0: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 80149b2: 687b ldr r3, [r7, #4] 80149b4: 685b ldr r3, [r3, #4] 80149b6: 687a ldr r2, [r7, #4] 80149b8: 6892 ldr r2, [r2, #8] 80149ba: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 80149bc: 687b ldr r3, [r7, #4] 80149be: 689b ldr r3, [r3, #8] 80149c0: 687a ldr r2, [r7, #4] 80149c2: 6852 ldr r2, [r2, #4] 80149c4: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 80149c6: 68fb ldr r3, [r7, #12] 80149c8: 685b ldr r3, [r3, #4] 80149ca: 687a ldr r2, [r7, #4] 80149cc: 429a cmp r2, r3 80149ce: d103 bne.n 80149d8 { pxList->pxIndex = pxItemToRemove->pxPrevious; 80149d0: 687b ldr r3, [r7, #4] 80149d2: 689a ldr r2, [r3, #8] 80149d4: 68fb ldr r3, [r7, #12] 80149d6: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 80149d8: 687b ldr r3, [r7, #4] 80149da: 2200 movs r2, #0 80149dc: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 80149de: 68fb ldr r3, [r7, #12] 80149e0: 681b ldr r3, [r3, #0] 80149e2: 1e5a subs r2, r3, #1 80149e4: 68fb ldr r3, [r7, #12] 80149e6: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 80149e8: 68fb ldr r3, [r7, #12] 80149ea: 681b ldr r3, [r3, #0] } 80149ec: 4618 mov r0, r3 80149ee: 3714 adds r7, #20 80149f0: 46bd mov sp, r7 80149f2: f85d 7b04 ldr.w r7, [sp], #4 80149f6: 4770 bx lr 080149f8 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 80149f8: b580 push {r7, lr} 80149fa: b084 sub sp, #16 80149fc: af00 add r7, sp, #0 80149fe: 6078 str r0, [r7, #4] 8014a00: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 8014a02: 687b ldr r3, [r7, #4] 8014a04: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 8014a06: 68fb ldr r3, [r7, #12] 8014a08: 2b00 cmp r3, #0 8014a0a: d10b bne.n 8014a24 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8014a0c: f04f 0350 mov.w r3, #80 @ 0x50 8014a10: f383 8811 msr BASEPRI, r3 8014a14: f3bf 8f6f isb sy 8014a18: f3bf 8f4f dsb sy 8014a1c: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8014a1e: bf00 nop 8014a20: bf00 nop 8014a22: e7fd b.n 8014a20 taskENTER_CRITICAL(); 8014a24: f003 f960 bl 8017ce8 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014a28: 68fb ldr r3, [r7, #12] 8014a2a: 681a ldr r2, [r3, #0] 8014a2c: 68fb ldr r3, [r7, #12] 8014a2e: 6bdb ldr r3, [r3, #60] @ 0x3c 8014a30: 68f9 ldr r1, [r7, #12] 8014a32: 6c09 ldr r1, [r1, #64] @ 0x40 8014a34: fb01 f303 mul.w r3, r1, r3 8014a38: 441a add r2, r3 8014a3a: 68fb ldr r3, [r7, #12] 8014a3c: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8014a3e: 68fb ldr r3, [r7, #12] 8014a40: 2200 movs r2, #0 8014a42: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8014a44: 68fb ldr r3, [r7, #12] 8014a46: 681a ldr r2, [r3, #0] 8014a48: 68fb ldr r3, [r7, #12] 8014a4a: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014a4c: 68fb ldr r3, [r7, #12] 8014a4e: 681a ldr r2, [r3, #0] 8014a50: 68fb ldr r3, [r7, #12] 8014a52: 6bdb ldr r3, [r3, #60] @ 0x3c 8014a54: 3b01 subs r3, #1 8014a56: 68f9 ldr r1, [r7, #12] 8014a58: 6c09 ldr r1, [r1, #64] @ 0x40 8014a5a: fb01 f303 mul.w r3, r1, r3 8014a5e: 441a add r2, r3 8014a60: 68fb ldr r3, [r7, #12] 8014a62: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8014a64: 68fb ldr r3, [r7, #12] 8014a66: 22ff movs r2, #255 @ 0xff 8014a68: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8014a6c: 68fb ldr r3, [r7, #12] 8014a6e: 22ff movs r2, #255 @ 0xff 8014a70: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8014a74: 683b ldr r3, [r7, #0] 8014a76: 2b00 cmp r3, #0 8014a78: d114 bne.n 8014aa4 /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014a7a: 68fb ldr r3, [r7, #12] 8014a7c: 691b ldr r3, [r3, #16] 8014a7e: 2b00 cmp r3, #0 8014a80: d01a beq.n 8014ab8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014a82: 68fb ldr r3, [r7, #12] 8014a84: 3310 adds r3, #16 8014a86: 4618 mov r0, r3 8014a88: f001 fdac bl 80165e4 8014a8c: 4603 mov r3, r0 8014a8e: 2b00 cmp r3, #0 8014a90: d012 beq.n 8014ab8 { queueYIELD_IF_USING_PREEMPTION(); 8014a92: 4b0d ldr r3, [pc, #52] @ (8014ac8 ) 8014a94: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014a98: 601a str r2, [r3, #0] 8014a9a: f3bf 8f4f dsb sy 8014a9e: f3bf 8f6f isb sy 8014aa2: e009 b.n 8014ab8 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8014aa4: 68fb ldr r3, [r7, #12] 8014aa6: 3310 adds r3, #16 8014aa8: 4618 mov r0, r3 8014aaa: f7ff fef1 bl 8014890 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8014aae: 68fb ldr r3, [r7, #12] 8014ab0: 3324 adds r3, #36 @ 0x24 8014ab2: 4618 mov r0, r3 8014ab4: f7ff feec bl 8014890 } } taskEXIT_CRITICAL(); 8014ab8: f003 f948 bl 8017d4c /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 8014abc: 2301 movs r3, #1 } 8014abe: 4618 mov r0, r3 8014ac0: 3710 adds r7, #16 8014ac2: 46bd mov sp, r7 8014ac4: bd80 pop {r7, pc} 8014ac6: bf00 nop 8014ac8: e000ed04 .word 0xe000ed04 08014acc : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 8014acc: b580 push {r7, lr} 8014ace: b08e sub sp, #56 @ 0x38 8014ad0: af02 add r7, sp, #8 8014ad2: 60f8 str r0, [r7, #12] 8014ad4: 60b9 str r1, [r7, #8] 8014ad6: 607a str r2, [r7, #4] 8014ad8: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014ada: 68fb ldr r3, [r7, #12] 8014adc: 2b00 cmp r3, #0 8014ade: d10b bne.n 8014af8 __asm volatile 8014ae0: f04f 0350 mov.w r3, #80 @ 0x50 8014ae4: f383 8811 msr BASEPRI, r3 8014ae8: f3bf 8f6f isb sy 8014aec: f3bf 8f4f dsb sy 8014af0: 62bb str r3, [r7, #40] @ 0x28 } 8014af2: bf00 nop 8014af4: bf00 nop 8014af6: e7fd b.n 8014af4 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 8014af8: 683b ldr r3, [r7, #0] 8014afa: 2b00 cmp r3, #0 8014afc: d10b bne.n 8014b16 __asm volatile 8014afe: f04f 0350 mov.w r3, #80 @ 0x50 8014b02: f383 8811 msr BASEPRI, r3 8014b06: f3bf 8f6f isb sy 8014b0a: f3bf 8f4f dsb sy 8014b0e: 627b str r3, [r7, #36] @ 0x24 } 8014b10: bf00 nop 8014b12: bf00 nop 8014b14: e7fd b.n 8014b12 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 8014b16: 687b ldr r3, [r7, #4] 8014b18: 2b00 cmp r3, #0 8014b1a: d002 beq.n 8014b22 8014b1c: 68bb ldr r3, [r7, #8] 8014b1e: 2b00 cmp r3, #0 8014b20: d001 beq.n 8014b26 8014b22: 2301 movs r3, #1 8014b24: e000 b.n 8014b28 8014b26: 2300 movs r3, #0 8014b28: 2b00 cmp r3, #0 8014b2a: d10b bne.n 8014b44 __asm volatile 8014b2c: f04f 0350 mov.w r3, #80 @ 0x50 8014b30: f383 8811 msr BASEPRI, r3 8014b34: f3bf 8f6f isb sy 8014b38: f3bf 8f4f dsb sy 8014b3c: 623b str r3, [r7, #32] } 8014b3e: bf00 nop 8014b40: bf00 nop 8014b42: e7fd b.n 8014b40 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8014b44: 687b ldr r3, [r7, #4] 8014b46: 2b00 cmp r3, #0 8014b48: d102 bne.n 8014b50 8014b4a: 68bb ldr r3, [r7, #8] 8014b4c: 2b00 cmp r3, #0 8014b4e: d101 bne.n 8014b54 8014b50: 2301 movs r3, #1 8014b52: e000 b.n 8014b56 8014b54: 2300 movs r3, #0 8014b56: 2b00 cmp r3, #0 8014b58: d10b bne.n 8014b72 __asm volatile 8014b5a: f04f 0350 mov.w r3, #80 @ 0x50 8014b5e: f383 8811 msr BASEPRI, r3 8014b62: f3bf 8f6f isb sy 8014b66: f3bf 8f4f dsb sy 8014b6a: 61fb str r3, [r7, #28] } 8014b6c: bf00 nop 8014b6e: bf00 nop 8014b70: e7fd b.n 8014b6e #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8014b72: 2350 movs r3, #80 @ 0x50 8014b74: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 8014b76: 697b ldr r3, [r7, #20] 8014b78: 2b50 cmp r3, #80 @ 0x50 8014b7a: d00b beq.n 8014b94 __asm volatile 8014b7c: f04f 0350 mov.w r3, #80 @ 0x50 8014b80: f383 8811 msr BASEPRI, r3 8014b84: f3bf 8f6f isb sy 8014b88: f3bf 8f4f dsb sy 8014b8c: 61bb str r3, [r7, #24] } 8014b8e: bf00 nop 8014b90: bf00 nop 8014b92: e7fd b.n 8014b90 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8014b94: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8014b96: 683b ldr r3, [r7, #0] 8014b98: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 8014b9a: 6afb ldr r3, [r7, #44] @ 0x2c 8014b9c: 2b00 cmp r3, #0 8014b9e: d00d beq.n 8014bbc #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8014ba0: 6afb ldr r3, [r7, #44] @ 0x2c 8014ba2: 2201 movs r2, #1 8014ba4: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014ba8: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 8014bac: 6afb ldr r3, [r7, #44] @ 0x2c 8014bae: 9300 str r3, [sp, #0] 8014bb0: 4613 mov r3, r2 8014bb2: 687a ldr r2, [r7, #4] 8014bb4: 68b9 ldr r1, [r7, #8] 8014bb6: 68f8 ldr r0, [r7, #12] 8014bb8: f000 f840 bl 8014c3c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014bbc: 6afb ldr r3, [r7, #44] @ 0x2c } 8014bbe: 4618 mov r0, r3 8014bc0: 3730 adds r7, #48 @ 0x30 8014bc2: 46bd mov sp, r7 8014bc4: bd80 pop {r7, pc} 08014bc6 : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 8014bc6: b580 push {r7, lr} 8014bc8: b08a sub sp, #40 @ 0x28 8014bca: af02 add r7, sp, #8 8014bcc: 60f8 str r0, [r7, #12] 8014bce: 60b9 str r1, [r7, #8] 8014bd0: 4613 mov r3, r2 8014bd2: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014bd4: 68fb ldr r3, [r7, #12] 8014bd6: 2b00 cmp r3, #0 8014bd8: d10b bne.n 8014bf2 __asm volatile 8014bda: f04f 0350 mov.w r3, #80 @ 0x50 8014bde: f383 8811 msr BASEPRI, r3 8014be2: f3bf 8f6f isb sy 8014be6: f3bf 8f4f dsb sy 8014bea: 613b str r3, [r7, #16] } 8014bec: bf00 nop 8014bee: bf00 nop 8014bf0: e7fd b.n 8014bee /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014bf2: 68fb ldr r3, [r7, #12] 8014bf4: 68ba ldr r2, [r7, #8] 8014bf6: fb02 f303 mul.w r3, r2, r3 8014bfa: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 8014bfc: 69fb ldr r3, [r7, #28] 8014bfe: 3350 adds r3, #80 @ 0x50 8014c00: 4618 mov r0, r3 8014c02: f003 f993 bl 8017f2c 8014c06: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 8014c08: 69bb ldr r3, [r7, #24] 8014c0a: 2b00 cmp r3, #0 8014c0c: d011 beq.n 8014c32 { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 8014c0e: 69bb ldr r3, [r7, #24] 8014c10: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014c12: 697b ldr r3, [r7, #20] 8014c14: 3350 adds r3, #80 @ 0x50 8014c16: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8014c18: 69bb ldr r3, [r7, #24] 8014c1a: 2200 movs r2, #0 8014c1c: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014c20: 79fa ldrb r2, [r7, #7] 8014c22: 69bb ldr r3, [r7, #24] 8014c24: 9300 str r3, [sp, #0] 8014c26: 4613 mov r3, r2 8014c28: 697a ldr r2, [r7, #20] 8014c2a: 68b9 ldr r1, [r7, #8] 8014c2c: 68f8 ldr r0, [r7, #12] 8014c2e: f000 f805 bl 8014c3c { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014c32: 69bb ldr r3, [r7, #24] } 8014c34: 4618 mov r0, r3 8014c36: 3720 adds r7, #32 8014c38: 46bd mov sp, r7 8014c3a: bd80 pop {r7, pc} 08014c3c : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 8014c3c: b580 push {r7, lr} 8014c3e: b084 sub sp, #16 8014c40: af00 add r7, sp, #0 8014c42: 60f8 str r0, [r7, #12] 8014c44: 60b9 str r1, [r7, #8] 8014c46: 607a str r2, [r7, #4] 8014c48: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 8014c4a: 68bb ldr r3, [r7, #8] 8014c4c: 2b00 cmp r3, #0 8014c4e: d103 bne.n 8014c58 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8014c50: 69bb ldr r3, [r7, #24] 8014c52: 69ba ldr r2, [r7, #24] 8014c54: 601a str r2, [r3, #0] 8014c56: e002 b.n 8014c5e } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8014c58: 69bb ldr r3, [r7, #24] 8014c5a: 687a ldr r2, [r7, #4] 8014c5c: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 8014c5e: 69bb ldr r3, [r7, #24] 8014c60: 68fa ldr r2, [r7, #12] 8014c62: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8014c64: 69bb ldr r3, [r7, #24] 8014c66: 68ba ldr r2, [r7, #8] 8014c68: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 8014c6a: 2101 movs r1, #1 8014c6c: 69b8 ldr r0, [r7, #24] 8014c6e: f7ff fec3 bl 80149f8 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8014c72: 69bb ldr r3, [r7, #24] 8014c74: 78fa ldrb r2, [r7, #3] 8014c76: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 8014c7a: bf00 nop 8014c7c: 3710 adds r7, #16 8014c7e: 46bd mov sp, r7 8014c80: bd80 pop {r7, pc} 08014c82 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 8014c82: b580 push {r7, lr} 8014c84: b082 sub sp, #8 8014c86: af00 add r7, sp, #0 8014c88: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 8014c8a: 687b ldr r3, [r7, #4] 8014c8c: 2b00 cmp r3, #0 8014c8e: d00e beq.n 8014cae { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8014c90: 687b ldr r3, [r7, #4] 8014c92: 2200 movs r2, #0 8014c94: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8014c96: 687b ldr r3, [r7, #4] 8014c98: 2200 movs r2, #0 8014c9a: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 8014c9c: 687b ldr r3, [r7, #4] 8014c9e: 2200 movs r2, #0 8014ca0: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8014ca2: 2300 movs r3, #0 8014ca4: 2200 movs r2, #0 8014ca6: 2100 movs r1, #0 8014ca8: 6878 ldr r0, [r7, #4] 8014caa: f000 f8a3 bl 8014df4 } else { traceCREATE_MUTEX_FAILED(); } } 8014cae: bf00 nop 8014cb0: 3708 adds r7, #8 8014cb2: 46bd mov sp, r7 8014cb4: bd80 pop {r7, pc} 08014cb6 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 8014cb6: b580 push {r7, lr} 8014cb8: b086 sub sp, #24 8014cba: af00 add r7, sp, #0 8014cbc: 4603 mov r3, r0 8014cbe: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014cc0: 2301 movs r3, #1 8014cc2: 617b str r3, [r7, #20] 8014cc4: 2300 movs r3, #0 8014cc6: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 8014cc8: 79fb ldrb r3, [r7, #7] 8014cca: 461a mov r2, r3 8014ccc: 6939 ldr r1, [r7, #16] 8014cce: 6978 ldr r0, [r7, #20] 8014cd0: f7ff ff79 bl 8014bc6 8014cd4: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014cd6: 68f8 ldr r0, [r7, #12] 8014cd8: f7ff ffd3 bl 8014c82 return xNewQueue; 8014cdc: 68fb ldr r3, [r7, #12] } 8014cde: 4618 mov r0, r3 8014ce0: 3718 adds r7, #24 8014ce2: 46bd mov sp, r7 8014ce4: bd80 pop {r7, pc} 08014ce6 : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 8014ce6: b580 push {r7, lr} 8014ce8: b088 sub sp, #32 8014cea: af02 add r7, sp, #8 8014cec: 4603 mov r3, r0 8014cee: 6039 str r1, [r7, #0] 8014cf0: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014cf2: 2301 movs r3, #1 8014cf4: 617b str r3, [r7, #20] 8014cf6: 2300 movs r3, #0 8014cf8: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 8014cfa: 79fb ldrb r3, [r7, #7] 8014cfc: 9300 str r3, [sp, #0] 8014cfe: 683b ldr r3, [r7, #0] 8014d00: 2200 movs r2, #0 8014d02: 6939 ldr r1, [r7, #16] 8014d04: 6978 ldr r0, [r7, #20] 8014d06: f7ff fee1 bl 8014acc 8014d0a: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014d0c: 68f8 ldr r0, [r7, #12] 8014d0e: f7ff ffb8 bl 8014c82 return xNewQueue; 8014d12: 68fb ldr r3, [r7, #12] } 8014d14: 4618 mov r0, r3 8014d16: 3718 adds r7, #24 8014d18: 46bd mov sp, r7 8014d1a: bd80 pop {r7, pc} 08014d1c : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 8014d1c: b590 push {r4, r7, lr} 8014d1e: b087 sub sp, #28 8014d20: af00 add r7, sp, #0 8014d22: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014d24: 687b ldr r3, [r7, #4] 8014d26: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014d28: 693b ldr r3, [r7, #16] 8014d2a: 2b00 cmp r3, #0 8014d2c: d10b bne.n 8014d46 __asm volatile 8014d2e: f04f 0350 mov.w r3, #80 @ 0x50 8014d32: f383 8811 msr BASEPRI, r3 8014d36: f3bf 8f6f isb sy 8014d3a: f3bf 8f4f dsb sy 8014d3e: 60fb str r3, [r7, #12] } 8014d40: bf00 nop 8014d42: bf00 nop 8014d44: e7fd b.n 8014d42 change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014d46: 693b ldr r3, [r7, #16] 8014d48: 689c ldr r4, [r3, #8] 8014d4a: f001 fe39 bl 80169c0 8014d4e: 4603 mov r3, r0 8014d50: 429c cmp r4, r3 8014d52: d111 bne.n 8014d78 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8014d54: 693b ldr r3, [r7, #16] 8014d56: 68db ldr r3, [r3, #12] 8014d58: 1e5a subs r2, r3, #1 8014d5a: 693b ldr r3, [r7, #16] 8014d5c: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 8014d5e: 693b ldr r3, [r7, #16] 8014d60: 68db ldr r3, [r3, #12] 8014d62: 2b00 cmp r3, #0 8014d64: d105 bne.n 8014d72 { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8014d66: 2300 movs r3, #0 8014d68: 2200 movs r2, #0 8014d6a: 2100 movs r1, #0 8014d6c: 6938 ldr r0, [r7, #16] 8014d6e: f000 f841 bl 8014df4 else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8014d72: 2301 movs r3, #1 8014d74: 617b str r3, [r7, #20] 8014d76: e001 b.n 8014d7c } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 8014d78: 2300 movs r3, #0 8014d7a: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 8014d7c: 697b ldr r3, [r7, #20] } 8014d7e: 4618 mov r0, r3 8014d80: 371c adds r7, #28 8014d82: 46bd mov sp, r7 8014d84: bd90 pop {r4, r7, pc} 08014d86 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 8014d86: b590 push {r4, r7, lr} 8014d88: b087 sub sp, #28 8014d8a: af00 add r7, sp, #0 8014d8c: 6078 str r0, [r7, #4] 8014d8e: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014d90: 687b ldr r3, [r7, #4] 8014d92: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014d94: 693b ldr r3, [r7, #16] 8014d96: 2b00 cmp r3, #0 8014d98: d10b bne.n 8014db2 __asm volatile 8014d9a: f04f 0350 mov.w r3, #80 @ 0x50 8014d9e: f383 8811 msr BASEPRI, r3 8014da2: f3bf 8f6f isb sy 8014da6: f3bf 8f4f dsb sy 8014daa: 60fb str r3, [r7, #12] } 8014dac: bf00 nop 8014dae: bf00 nop 8014db0: e7fd b.n 8014dae /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014db2: 693b ldr r3, [r7, #16] 8014db4: 689c ldr r4, [r3, #8] 8014db6: f001 fe03 bl 80169c0 8014dba: 4603 mov r3, r0 8014dbc: 429c cmp r4, r3 8014dbe: d107 bne.n 8014dd0 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014dc0: 693b ldr r3, [r7, #16] 8014dc2: 68db ldr r3, [r3, #12] 8014dc4: 1c5a adds r2, r3, #1 8014dc6: 693b ldr r3, [r7, #16] 8014dc8: 60da str r2, [r3, #12] xReturn = pdPASS; 8014dca: 2301 movs r3, #1 8014dcc: 617b str r3, [r7, #20] 8014dce: e00c b.n 8014dea } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 8014dd0: 6839 ldr r1, [r7, #0] 8014dd2: 6938 ldr r0, [r7, #16] 8014dd4: f000 fa90 bl 80152f8 8014dd8: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 8014dda: 697b ldr r3, [r7, #20] 8014ddc: 2b00 cmp r3, #0 8014dde: d004 beq.n 8014dea { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014de0: 693b ldr r3, [r7, #16] 8014de2: 68db ldr r3, [r3, #12] 8014de4: 1c5a adds r2, r3, #1 8014de6: 693b ldr r3, [r7, #16] 8014de8: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 8014dea: 697b ldr r3, [r7, #20] } 8014dec: 4618 mov r0, r3 8014dee: 371c adds r7, #28 8014df0: 46bd mov sp, r7 8014df2: bd90 pop {r4, r7, pc} 08014df4 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8014df4: b580 push {r7, lr} 8014df6: b08e sub sp, #56 @ 0x38 8014df8: af00 add r7, sp, #0 8014dfa: 60f8 str r0, [r7, #12] 8014dfc: 60b9 str r1, [r7, #8] 8014dfe: 607a str r2, [r7, #4] 8014e00: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8014e02: 2300 movs r3, #0 8014e04: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014e06: 68fb ldr r3, [r7, #12] 8014e08: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8014e0a: 6b3b ldr r3, [r7, #48] @ 0x30 8014e0c: 2b00 cmp r3, #0 8014e0e: d10b bne.n 8014e28 __asm volatile 8014e10: f04f 0350 mov.w r3, #80 @ 0x50 8014e14: f383 8811 msr BASEPRI, r3 8014e18: f3bf 8f6f isb sy 8014e1c: f3bf 8f4f dsb sy 8014e20: 62bb str r3, [r7, #40] @ 0x28 } 8014e22: bf00 nop 8014e24: bf00 nop 8014e26: e7fd b.n 8014e24 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014e28: 68bb ldr r3, [r7, #8] 8014e2a: 2b00 cmp r3, #0 8014e2c: d103 bne.n 8014e36 8014e2e: 6b3b ldr r3, [r7, #48] @ 0x30 8014e30: 6c1b ldr r3, [r3, #64] @ 0x40 8014e32: 2b00 cmp r3, #0 8014e34: d101 bne.n 8014e3a 8014e36: 2301 movs r3, #1 8014e38: e000 b.n 8014e3c 8014e3a: 2300 movs r3, #0 8014e3c: 2b00 cmp r3, #0 8014e3e: d10b bne.n 8014e58 __asm volatile 8014e40: f04f 0350 mov.w r3, #80 @ 0x50 8014e44: f383 8811 msr BASEPRI, r3 8014e48: f3bf 8f6f isb sy 8014e4c: f3bf 8f4f dsb sy 8014e50: 627b str r3, [r7, #36] @ 0x24 } 8014e52: bf00 nop 8014e54: bf00 nop 8014e56: e7fd b.n 8014e54 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014e58: 683b ldr r3, [r7, #0] 8014e5a: 2b02 cmp r3, #2 8014e5c: d103 bne.n 8014e66 8014e5e: 6b3b ldr r3, [r7, #48] @ 0x30 8014e60: 6bdb ldr r3, [r3, #60] @ 0x3c 8014e62: 2b01 cmp r3, #1 8014e64: d101 bne.n 8014e6a 8014e66: 2301 movs r3, #1 8014e68: e000 b.n 8014e6c 8014e6a: 2300 movs r3, #0 8014e6c: 2b00 cmp r3, #0 8014e6e: d10b bne.n 8014e88 __asm volatile 8014e70: f04f 0350 mov.w r3, #80 @ 0x50 8014e74: f383 8811 msr BASEPRI, r3 8014e78: f3bf 8f6f isb sy 8014e7c: f3bf 8f4f dsb sy 8014e80: 623b str r3, [r7, #32] } 8014e82: bf00 nop 8014e84: bf00 nop 8014e86: e7fd b.n 8014e84 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014e88: f001 fdaa bl 80169e0 8014e8c: 4603 mov r3, r0 8014e8e: 2b00 cmp r3, #0 8014e90: d102 bne.n 8014e98 8014e92: 687b ldr r3, [r7, #4] 8014e94: 2b00 cmp r3, #0 8014e96: d101 bne.n 8014e9c 8014e98: 2301 movs r3, #1 8014e9a: e000 b.n 8014e9e 8014e9c: 2300 movs r3, #0 8014e9e: 2b00 cmp r3, #0 8014ea0: d10b bne.n 8014eba __asm volatile 8014ea2: f04f 0350 mov.w r3, #80 @ 0x50 8014ea6: f383 8811 msr BASEPRI, r3 8014eaa: f3bf 8f6f isb sy 8014eae: f3bf 8f4f dsb sy 8014eb2: 61fb str r3, [r7, #28] } 8014eb4: bf00 nop 8014eb6: bf00 nop 8014eb8: e7fd b.n 8014eb6 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8014eba: f002 ff15 bl 8017ce8 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014ebe: 6b3b ldr r3, [r7, #48] @ 0x30 8014ec0: 6b9a ldr r2, [r3, #56] @ 0x38 8014ec2: 6b3b ldr r3, [r7, #48] @ 0x30 8014ec4: 6bdb ldr r3, [r3, #60] @ 0x3c 8014ec6: 429a cmp r2, r3 8014ec8: d302 bcc.n 8014ed0 8014eca: 683b ldr r3, [r7, #0] 8014ecc: 2b02 cmp r3, #2 8014ece: d129 bne.n 8014f24 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8014ed0: 683a ldr r2, [r7, #0] 8014ed2: 68b9 ldr r1, [r7, #8] 8014ed4: 6b38 ldr r0, [r7, #48] @ 0x30 8014ed6: f000 fbb9 bl 801564c 8014eda: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014edc: 6b3b ldr r3, [r7, #48] @ 0x30 8014ede: 6a5b ldr r3, [r3, #36] @ 0x24 8014ee0: 2b00 cmp r3, #0 8014ee2: d010 beq.n 8014f06 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014ee4: 6b3b ldr r3, [r7, #48] @ 0x30 8014ee6: 3324 adds r3, #36 @ 0x24 8014ee8: 4618 mov r0, r3 8014eea: f001 fb7b bl 80165e4 8014eee: 4603 mov r3, r0 8014ef0: 2b00 cmp r3, #0 8014ef2: d013 beq.n 8014f1c { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8014ef4: 4b3f ldr r3, [pc, #252] @ (8014ff4 ) 8014ef6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014efa: 601a str r2, [r3, #0] 8014efc: f3bf 8f4f dsb sy 8014f00: f3bf 8f6f isb sy 8014f04: e00a b.n 8014f1c else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8014f06: 6afb ldr r3, [r7, #44] @ 0x2c 8014f08: 2b00 cmp r3, #0 8014f0a: d007 beq.n 8014f1c { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8014f0c: 4b39 ldr r3, [pc, #228] @ (8014ff4 ) 8014f0e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014f12: 601a str r2, [r3, #0] 8014f14: f3bf 8f4f dsb sy 8014f18: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8014f1c: f002 ff16 bl 8017d4c return pdPASS; 8014f20: 2301 movs r3, #1 8014f22: e063 b.n 8014fec } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014f24: 687b ldr r3, [r7, #4] 8014f26: 2b00 cmp r3, #0 8014f28: d103 bne.n 8014f32 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014f2a: f002 ff0f bl 8017d4c /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014f2e: 2300 movs r3, #0 8014f30: e05c b.n 8014fec } else if( xEntryTimeSet == pdFALSE ) 8014f32: 6b7b ldr r3, [r7, #52] @ 0x34 8014f34: 2b00 cmp r3, #0 8014f36: d106 bne.n 8014f46 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014f38: f107 0314 add.w r3, r7, #20 8014f3c: 4618 mov r0, r3 8014f3e: f001 fbdd bl 80166fc xEntryTimeSet = pdTRUE; 8014f42: 2301 movs r3, #1 8014f44: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014f46: f002 ff01 bl 8017d4c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8014f4a: f001 f90f bl 801616c prvLockQueue( pxQueue ); 8014f4e: f002 fecb bl 8017ce8 8014f52: 6b3b ldr r3, [r7, #48] @ 0x30 8014f54: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014f58: b25b sxtb r3, r3 8014f5a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f5e: d103 bne.n 8014f68 8014f60: 6b3b ldr r3, [r7, #48] @ 0x30 8014f62: 2200 movs r2, #0 8014f64: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014f68: 6b3b ldr r3, [r7, #48] @ 0x30 8014f6a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014f6e: b25b sxtb r3, r3 8014f70: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f74: d103 bne.n 8014f7e 8014f76: 6b3b ldr r3, [r7, #48] @ 0x30 8014f78: 2200 movs r2, #0 8014f7a: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014f7e: f002 fee5 bl 8017d4c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014f82: 1d3a adds r2, r7, #4 8014f84: f107 0314 add.w r3, r7, #20 8014f88: 4611 mov r1, r2 8014f8a: 4618 mov r0, r3 8014f8c: f001 fbcc bl 8016728 8014f90: 4603 mov r3, r0 8014f92: 2b00 cmp r3, #0 8014f94: d124 bne.n 8014fe0 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 8014f96: 6b38 ldr r0, [r7, #48] @ 0x30 8014f98: f000 fc50 bl 801583c 8014f9c: 4603 mov r3, r0 8014f9e: 2b00 cmp r3, #0 8014fa0: d018 beq.n 8014fd4 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 8014fa2: 6b3b ldr r3, [r7, #48] @ 0x30 8014fa4: 3310 adds r3, #16 8014fa6: 687a ldr r2, [r7, #4] 8014fa8: 4611 mov r1, r2 8014faa: 4618 mov r0, r3 8014fac: f001 fac8 bl 8016540 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8014fb0: 6b38 ldr r0, [r7, #48] @ 0x30 8014fb2: f000 fbdb bl 801576c /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 8014fb6: f001 f8e7 bl 8016188 8014fba: 4603 mov r3, r0 8014fbc: 2b00 cmp r3, #0 8014fbe: f47f af7c bne.w 8014eba { portYIELD_WITHIN_API(); 8014fc2: 4b0c ldr r3, [pc, #48] @ (8014ff4 ) 8014fc4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014fc8: 601a str r2, [r3, #0] 8014fca: f3bf 8f4f dsb sy 8014fce: f3bf 8f6f isb sy 8014fd2: e772 b.n 8014eba } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 8014fd4: 6b38 ldr r0, [r7, #48] @ 0x30 8014fd6: f000 fbc9 bl 801576c ( void ) xTaskResumeAll(); 8014fda: f001 f8d5 bl 8016188 8014fde: e76c b.n 8014eba } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8014fe0: 6b38 ldr r0, [r7, #48] @ 0x30 8014fe2: f000 fbc3 bl 801576c ( void ) xTaskResumeAll(); 8014fe6: f001 f8cf bl 8016188 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014fea: 2300 movs r3, #0 } } /*lint -restore */ } 8014fec: 4618 mov r0, r3 8014fee: 3738 adds r7, #56 @ 0x38 8014ff0: 46bd mov sp, r7 8014ff2: bd80 pop {r7, pc} 8014ff4: e000ed04 .word 0xe000ed04 08014ff8 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8014ff8: b580 push {r7, lr} 8014ffa: b090 sub sp, #64 @ 0x40 8014ffc: af00 add r7, sp, #0 8014ffe: 60f8 str r0, [r7, #12] 8015000: 60b9 str r1, [r7, #8] 8015002: 607a str r2, [r7, #4] 8015004: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8015006: 68fb ldr r3, [r7, #12] 8015008: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 801500a: 6bbb ldr r3, [r7, #56] @ 0x38 801500c: 2b00 cmp r3, #0 801500e: d10b bne.n 8015028 __asm volatile 8015010: f04f 0350 mov.w r3, #80 @ 0x50 8015014: f383 8811 msr BASEPRI, r3 8015018: f3bf 8f6f isb sy 801501c: f3bf 8f4f dsb sy 8015020: 62bb str r3, [r7, #40] @ 0x28 } 8015022: bf00 nop 8015024: bf00 nop 8015026: e7fd b.n 8015024 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8015028: 68bb ldr r3, [r7, #8] 801502a: 2b00 cmp r3, #0 801502c: d103 bne.n 8015036 801502e: 6bbb ldr r3, [r7, #56] @ 0x38 8015030: 6c1b ldr r3, [r3, #64] @ 0x40 8015032: 2b00 cmp r3, #0 8015034: d101 bne.n 801503a 8015036: 2301 movs r3, #1 8015038: e000 b.n 801503c 801503a: 2300 movs r3, #0 801503c: 2b00 cmp r3, #0 801503e: d10b bne.n 8015058 __asm volatile 8015040: f04f 0350 mov.w r3, #80 @ 0x50 8015044: f383 8811 msr BASEPRI, r3 8015048: f3bf 8f6f isb sy 801504c: f3bf 8f4f dsb sy 8015050: 627b str r3, [r7, #36] @ 0x24 } 8015052: bf00 nop 8015054: bf00 nop 8015056: e7fd b.n 8015054 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8015058: 683b ldr r3, [r7, #0] 801505a: 2b02 cmp r3, #2 801505c: d103 bne.n 8015066 801505e: 6bbb ldr r3, [r7, #56] @ 0x38 8015060: 6bdb ldr r3, [r3, #60] @ 0x3c 8015062: 2b01 cmp r3, #1 8015064: d101 bne.n 801506a 8015066: 2301 movs r3, #1 8015068: e000 b.n 801506c 801506a: 2300 movs r3, #0 801506c: 2b00 cmp r3, #0 801506e: d10b bne.n 8015088 __asm volatile 8015070: f04f 0350 mov.w r3, #80 @ 0x50 8015074: f383 8811 msr BASEPRI, r3 8015078: f3bf 8f6f isb sy 801507c: f3bf 8f4f dsb sy 8015080: 623b str r3, [r7, #32] } 8015082: bf00 nop 8015084: bf00 nop 8015086: e7fd b.n 8015084 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8015088: f002 ff0e bl 8017ea8 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 801508c: f3ef 8211 mrs r2, BASEPRI 8015090: f04f 0350 mov.w r3, #80 @ 0x50 8015094: f383 8811 msr BASEPRI, r3 8015098: f3bf 8f6f isb sy 801509c: f3bf 8f4f dsb sy 80150a0: 61fa str r2, [r7, #28] 80150a2: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 80150a4: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80150a6: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80150a8: 6bbb ldr r3, [r7, #56] @ 0x38 80150aa: 6b9a ldr r2, [r3, #56] @ 0x38 80150ac: 6bbb ldr r3, [r7, #56] @ 0x38 80150ae: 6bdb ldr r3, [r3, #60] @ 0x3c 80150b0: 429a cmp r2, r3 80150b2: d302 bcc.n 80150ba 80150b4: 683b ldr r3, [r7, #0] 80150b6: 2b02 cmp r3, #2 80150b8: d12f bne.n 801511a { const int8_t cTxLock = pxQueue->cTxLock; 80150ba: 6bbb ldr r3, [r7, #56] @ 0x38 80150bc: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80150c0: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 80150c4: 6bbb ldr r3, [r7, #56] @ 0x38 80150c6: 6b9b ldr r3, [r3, #56] @ 0x38 80150c8: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80150ca: 683a ldr r2, [r7, #0] 80150cc: 68b9 ldr r1, [r7, #8] 80150ce: 6bb8 ldr r0, [r7, #56] @ 0x38 80150d0: f000 fabc bl 801564c /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80150d4: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 80150d8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80150dc: d112 bne.n 8015104 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80150de: 6bbb ldr r3, [r7, #56] @ 0x38 80150e0: 6a5b ldr r3, [r3, #36] @ 0x24 80150e2: 2b00 cmp r3, #0 80150e4: d016 beq.n 8015114 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80150e6: 6bbb ldr r3, [r7, #56] @ 0x38 80150e8: 3324 adds r3, #36 @ 0x24 80150ea: 4618 mov r0, r3 80150ec: f001 fa7a bl 80165e4 80150f0: 4603 mov r3, r0 80150f2: 2b00 cmp r3, #0 80150f4: d00e beq.n 8015114 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80150f6: 687b ldr r3, [r7, #4] 80150f8: 2b00 cmp r3, #0 80150fa: d00b beq.n 8015114 { *pxHigherPriorityTaskWoken = pdTRUE; 80150fc: 687b ldr r3, [r7, #4] 80150fe: 2201 movs r2, #1 8015100: 601a str r2, [r3, #0] 8015102: e007 b.n 8015114 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 8015104: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8015108: 3301 adds r3, #1 801510a: b2db uxtb r3, r3 801510c: b25a sxtb r2, r3 801510e: 6bbb ldr r3, [r7, #56] @ 0x38 8015110: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8015114: 2301 movs r3, #1 8015116: 63fb str r3, [r7, #60] @ 0x3c { 8015118: e001 b.n 801511e } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 801511a: 2300 movs r3, #0 801511c: 63fb str r3, [r7, #60] @ 0x3c 801511e: 6b7b ldr r3, [r7, #52] @ 0x34 8015120: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8015122: 697b ldr r3, [r7, #20] 8015124: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 8015128: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801512a: 6bfb ldr r3, [r7, #60] @ 0x3c } 801512c: 4618 mov r0, r3 801512e: 3740 adds r7, #64 @ 0x40 8015130: 46bd mov sp, r7 8015132: bd80 pop {r7, pc} 08015134 : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 8015134: b580 push {r7, lr} 8015136: b08c sub sp, #48 @ 0x30 8015138: af00 add r7, sp, #0 801513a: 60f8 str r0, [r7, #12] 801513c: 60b9 str r1, [r7, #8] 801513e: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 8015140: 2300 movs r3, #0 8015142: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8015144: 68fb ldr r3, [r7, #12] 8015146: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8015148: 6abb ldr r3, [r7, #40] @ 0x28 801514a: 2b00 cmp r3, #0 801514c: d10b bne.n 8015166 __asm volatile 801514e: f04f 0350 mov.w r3, #80 @ 0x50 8015152: f383 8811 msr BASEPRI, r3 8015156: f3bf 8f6f isb sy 801515a: f3bf 8f4f dsb sy 801515e: 623b str r3, [r7, #32] } 8015160: bf00 nop 8015162: bf00 nop 8015164: e7fd b.n 8015162 /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8015166: 68bb ldr r3, [r7, #8] 8015168: 2b00 cmp r3, #0 801516a: d103 bne.n 8015174 801516c: 6abb ldr r3, [r7, #40] @ 0x28 801516e: 6c1b ldr r3, [r3, #64] @ 0x40 8015170: 2b00 cmp r3, #0 8015172: d101 bne.n 8015178 8015174: 2301 movs r3, #1 8015176: e000 b.n 801517a 8015178: 2300 movs r3, #0 801517a: 2b00 cmp r3, #0 801517c: d10b bne.n 8015196 __asm volatile 801517e: f04f 0350 mov.w r3, #80 @ 0x50 8015182: f383 8811 msr BASEPRI, r3 8015186: f3bf 8f6f isb sy 801518a: f3bf 8f4f dsb sy 801518e: 61fb str r3, [r7, #28] } 8015190: bf00 nop 8015192: bf00 nop 8015194: e7fd b.n 8015192 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8015196: f001 fc23 bl 80169e0 801519a: 4603 mov r3, r0 801519c: 2b00 cmp r3, #0 801519e: d102 bne.n 80151a6 80151a0: 687b ldr r3, [r7, #4] 80151a2: 2b00 cmp r3, #0 80151a4: d101 bne.n 80151aa 80151a6: 2301 movs r3, #1 80151a8: e000 b.n 80151ac 80151aa: 2300 movs r3, #0 80151ac: 2b00 cmp r3, #0 80151ae: d10b bne.n 80151c8 __asm volatile 80151b0: f04f 0350 mov.w r3, #80 @ 0x50 80151b4: f383 8811 msr BASEPRI, r3 80151b8: f3bf 8f6f isb sy 80151bc: f3bf 8f4f dsb sy 80151c0: 61bb str r3, [r7, #24] } 80151c2: bf00 nop 80151c4: bf00 nop 80151c6: e7fd b.n 80151c4 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80151c8: f002 fd8e bl 8017ce8 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80151cc: 6abb ldr r3, [r7, #40] @ 0x28 80151ce: 6b9b ldr r3, [r3, #56] @ 0x38 80151d0: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80151d2: 6a7b ldr r3, [r7, #36] @ 0x24 80151d4: 2b00 cmp r3, #0 80151d6: d01f beq.n 8015218 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 80151d8: 68b9 ldr r1, [r7, #8] 80151da: 6ab8 ldr r0, [r7, #40] @ 0x28 80151dc: f000 faa0 bl 8015720 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80151e0: 6a7b ldr r3, [r7, #36] @ 0x24 80151e2: 1e5a subs r2, r3, #1 80151e4: 6abb ldr r3, [r7, #40] @ 0x28 80151e6: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80151e8: 6abb ldr r3, [r7, #40] @ 0x28 80151ea: 691b ldr r3, [r3, #16] 80151ec: 2b00 cmp r3, #0 80151ee: d00f beq.n 8015210 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80151f0: 6abb ldr r3, [r7, #40] @ 0x28 80151f2: 3310 adds r3, #16 80151f4: 4618 mov r0, r3 80151f6: f001 f9f5 bl 80165e4 80151fa: 4603 mov r3, r0 80151fc: 2b00 cmp r3, #0 80151fe: d007 beq.n 8015210 { queueYIELD_IF_USING_PREEMPTION(); 8015200: 4b3c ldr r3, [pc, #240] @ (80152f4 ) 8015202: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015206: 601a str r2, [r3, #0] 8015208: f3bf 8f4f dsb sy 801520c: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8015210: f002 fd9c bl 8017d4c return pdPASS; 8015214: 2301 movs r3, #1 8015216: e069 b.n 80152ec } else { if( xTicksToWait == ( TickType_t ) 0 ) 8015218: 687b ldr r3, [r7, #4] 801521a: 2b00 cmp r3, #0 801521c: d103 bne.n 8015226 { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 801521e: f002 fd95 bl 8017d4c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015222: 2300 movs r3, #0 8015224: e062 b.n 80152ec } else if( xEntryTimeSet == pdFALSE ) 8015226: 6afb ldr r3, [r7, #44] @ 0x2c 8015228: 2b00 cmp r3, #0 801522a: d106 bne.n 801523a { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801522c: f107 0310 add.w r3, r7, #16 8015230: 4618 mov r0, r3 8015232: f001 fa63 bl 80166fc xEntryTimeSet = pdTRUE; 8015236: 2301 movs r3, #1 8015238: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 801523a: f002 fd87 bl 8017d4c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 801523e: f000 ff95 bl 801616c prvLockQueue( pxQueue ); 8015242: f002 fd51 bl 8017ce8 8015246: 6abb ldr r3, [r7, #40] @ 0x28 8015248: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801524c: b25b sxtb r3, r3 801524e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015252: d103 bne.n 801525c 8015254: 6abb ldr r3, [r7, #40] @ 0x28 8015256: 2200 movs r2, #0 8015258: f883 2044 strb.w r2, [r3, #68] @ 0x44 801525c: 6abb ldr r3, [r7, #40] @ 0x28 801525e: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015262: b25b sxtb r3, r3 8015264: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015268: d103 bne.n 8015272 801526a: 6abb ldr r3, [r7, #40] @ 0x28 801526c: 2200 movs r2, #0 801526e: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015272: f002 fd6b bl 8017d4c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8015276: 1d3a adds r2, r7, #4 8015278: f107 0310 add.w r3, r7, #16 801527c: 4611 mov r1, r2 801527e: 4618 mov r0, r3 8015280: f001 fa52 bl 8016728 8015284: 4603 mov r3, r0 8015286: 2b00 cmp r3, #0 8015288: d123 bne.n 80152d2 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 801528a: 6ab8 ldr r0, [r7, #40] @ 0x28 801528c: f000 fac0 bl 8015810 8015290: 4603 mov r3, r0 8015292: 2b00 cmp r3, #0 8015294: d017 beq.n 80152c6 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8015296: 6abb ldr r3, [r7, #40] @ 0x28 8015298: 3324 adds r3, #36 @ 0x24 801529a: 687a ldr r2, [r7, #4] 801529c: 4611 mov r1, r2 801529e: 4618 mov r0, r3 80152a0: f001 f94e bl 8016540 prvUnlockQueue( pxQueue ); 80152a4: 6ab8 ldr r0, [r7, #40] @ 0x28 80152a6: f000 fa61 bl 801576c if( xTaskResumeAll() == pdFALSE ) 80152aa: f000 ff6d bl 8016188 80152ae: 4603 mov r3, r0 80152b0: 2b00 cmp r3, #0 80152b2: d189 bne.n 80151c8 { portYIELD_WITHIN_API(); 80152b4: 4b0f ldr r3, [pc, #60] @ (80152f4 ) 80152b6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80152ba: 601a str r2, [r3, #0] 80152bc: f3bf 8f4f dsb sy 80152c0: f3bf 8f6f isb sy 80152c4: e780 b.n 80151c8 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 80152c6: 6ab8 ldr r0, [r7, #40] @ 0x28 80152c8: f000 fa50 bl 801576c ( void ) xTaskResumeAll(); 80152cc: f000 ff5c bl 8016188 80152d0: e77a b.n 80151c8 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 80152d2: 6ab8 ldr r0, [r7, #40] @ 0x28 80152d4: f000 fa4a bl 801576c ( void ) xTaskResumeAll(); 80152d8: f000 ff56 bl 8016188 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80152dc: 6ab8 ldr r0, [r7, #40] @ 0x28 80152de: f000 fa97 bl 8015810 80152e2: 4603 mov r3, r0 80152e4: 2b00 cmp r3, #0 80152e6: f43f af6f beq.w 80151c8 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80152ea: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 80152ec: 4618 mov r0, r3 80152ee: 3730 adds r7, #48 @ 0x30 80152f0: 46bd mov sp, r7 80152f2: bd80 pop {r7, pc} 80152f4: e000ed04 .word 0xe000ed04 080152f8 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 80152f8: b580 push {r7, lr} 80152fa: b08e sub sp, #56 @ 0x38 80152fc: af00 add r7, sp, #0 80152fe: 6078 str r0, [r7, #4] 8015300: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 8015302: 2300 movs r3, #0 8015304: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8015306: 687b ldr r3, [r7, #4] 8015308: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 801530a: 2300 movs r3, #0 801530c: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 801530e: 6afb ldr r3, [r7, #44] @ 0x2c 8015310: 2b00 cmp r3, #0 8015312: d10b bne.n 801532c __asm volatile 8015314: f04f 0350 mov.w r3, #80 @ 0x50 8015318: f383 8811 msr BASEPRI, r3 801531c: f3bf 8f6f isb sy 8015320: f3bf 8f4f dsb sy 8015324: 623b str r3, [r7, #32] } 8015326: bf00 nop 8015328: bf00 nop 801532a: e7fd b.n 8015328 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 801532c: 6afb ldr r3, [r7, #44] @ 0x2c 801532e: 6c1b ldr r3, [r3, #64] @ 0x40 8015330: 2b00 cmp r3, #0 8015332: d00b beq.n 801534c __asm volatile 8015334: f04f 0350 mov.w r3, #80 @ 0x50 8015338: f383 8811 msr BASEPRI, r3 801533c: f3bf 8f6f isb sy 8015340: f3bf 8f4f dsb sy 8015344: 61fb str r3, [r7, #28] } 8015346: bf00 nop 8015348: bf00 nop 801534a: e7fd b.n 8015348 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801534c: f001 fb48 bl 80169e0 8015350: 4603 mov r3, r0 8015352: 2b00 cmp r3, #0 8015354: d102 bne.n 801535c 8015356: 683b ldr r3, [r7, #0] 8015358: 2b00 cmp r3, #0 801535a: d101 bne.n 8015360 801535c: 2301 movs r3, #1 801535e: e000 b.n 8015362 8015360: 2300 movs r3, #0 8015362: 2b00 cmp r3, #0 8015364: d10b bne.n 801537e __asm volatile 8015366: f04f 0350 mov.w r3, #80 @ 0x50 801536a: f383 8811 msr BASEPRI, r3 801536e: f3bf 8f6f isb sy 8015372: f3bf 8f4f dsb sy 8015376: 61bb str r3, [r7, #24] } 8015378: bf00 nop 801537a: bf00 nop 801537c: e7fd b.n 801537a /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 801537e: f002 fcb3 bl 8017ce8 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 8015382: 6afb ldr r3, [r7, #44] @ 0x2c 8015384: 6b9b ldr r3, [r3, #56] @ 0x38 8015386: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 8015388: 6abb ldr r3, [r7, #40] @ 0x28 801538a: 2b00 cmp r3, #0 801538c: d024 beq.n 80153d8 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 801538e: 6abb ldr r3, [r7, #40] @ 0x28 8015390: 1e5a subs r2, r3, #1 8015392: 6afb ldr r3, [r7, #44] @ 0x2c 8015394: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8015396: 6afb ldr r3, [r7, #44] @ 0x2c 8015398: 681b ldr r3, [r3, #0] 801539a: 2b00 cmp r3, #0 801539c: d104 bne.n 80153a8 { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 801539e: f001 fc99 bl 8016cd4 80153a2: 4602 mov r2, r0 80153a4: 6afb ldr r3, [r7, #44] @ 0x2c 80153a6: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80153a8: 6afb ldr r3, [r7, #44] @ 0x2c 80153aa: 691b ldr r3, [r3, #16] 80153ac: 2b00 cmp r3, #0 80153ae: d00f beq.n 80153d0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80153b0: 6afb ldr r3, [r7, #44] @ 0x2c 80153b2: 3310 adds r3, #16 80153b4: 4618 mov r0, r3 80153b6: f001 f915 bl 80165e4 80153ba: 4603 mov r3, r0 80153bc: 2b00 cmp r3, #0 80153be: d007 beq.n 80153d0 { queueYIELD_IF_USING_PREEMPTION(); 80153c0: 4b54 ldr r3, [pc, #336] @ (8015514 ) 80153c2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80153c6: 601a str r2, [r3, #0] 80153c8: f3bf 8f4f dsb sy 80153cc: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80153d0: f002 fcbc bl 8017d4c return pdPASS; 80153d4: 2301 movs r3, #1 80153d6: e098 b.n 801550a } else { if( xTicksToWait == ( TickType_t ) 0 ) 80153d8: 683b ldr r3, [r7, #0] 80153da: 2b00 cmp r3, #0 80153dc: d112 bne.n 8015404 /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 80153de: 6b3b ldr r3, [r7, #48] @ 0x30 80153e0: 2b00 cmp r3, #0 80153e2: d00b beq.n 80153fc __asm volatile 80153e4: f04f 0350 mov.w r3, #80 @ 0x50 80153e8: f383 8811 msr BASEPRI, r3 80153ec: f3bf 8f6f isb sy 80153f0: f3bf 8f4f dsb sy 80153f4: 617b str r3, [r7, #20] } 80153f6: bf00 nop 80153f8: bf00 nop 80153fa: e7fd b.n 80153f8 } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 80153fc: f002 fca6 bl 8017d4c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015400: 2300 movs r3, #0 8015402: e082 b.n 801550a } else if( xEntryTimeSet == pdFALSE ) 8015404: 6b7b ldr r3, [r7, #52] @ 0x34 8015406: 2b00 cmp r3, #0 8015408: d106 bne.n 8015418 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 801540a: f107 030c add.w r3, r7, #12 801540e: 4618 mov r0, r3 8015410: f001 f974 bl 80166fc xEntryTimeSet = pdTRUE; 8015414: 2301 movs r3, #1 8015416: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8015418: f002 fc98 bl 8017d4c /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 801541c: f000 fea6 bl 801616c prvLockQueue( pxQueue ); 8015420: f002 fc62 bl 8017ce8 8015424: 6afb ldr r3, [r7, #44] @ 0x2c 8015426: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 801542a: b25b sxtb r3, r3 801542c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015430: d103 bne.n 801543a 8015432: 6afb ldr r3, [r7, #44] @ 0x2c 8015434: 2200 movs r2, #0 8015436: f883 2044 strb.w r2, [r3, #68] @ 0x44 801543a: 6afb ldr r3, [r7, #44] @ 0x2c 801543c: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015440: b25b sxtb r3, r3 8015442: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015446: d103 bne.n 8015450 8015448: 6afb ldr r3, [r7, #44] @ 0x2c 801544a: 2200 movs r2, #0 801544c: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015450: f002 fc7c bl 8017d4c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8015454: 463a mov r2, r7 8015456: f107 030c add.w r3, r7, #12 801545a: 4611 mov r1, r2 801545c: 4618 mov r0, r3 801545e: f001 f963 bl 8016728 8015462: 4603 mov r3, r0 8015464: 2b00 cmp r3, #0 8015466: d132 bne.n 80154ce { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8015468: 6af8 ldr r0, [r7, #44] @ 0x2c 801546a: f000 f9d1 bl 8015810 801546e: 4603 mov r3, r0 8015470: 2b00 cmp r3, #0 8015472: d026 beq.n 80154c2 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8015474: 6afb ldr r3, [r7, #44] @ 0x2c 8015476: 681b ldr r3, [r3, #0] 8015478: 2b00 cmp r3, #0 801547a: d109 bne.n 8015490 { taskENTER_CRITICAL(); 801547c: f002 fc34 bl 8017ce8 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 8015480: 6afb ldr r3, [r7, #44] @ 0x2c 8015482: 689b ldr r3, [r3, #8] 8015484: 4618 mov r0, r3 8015486: f001 fac9 bl 8016a1c 801548a: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 801548c: f002 fc5e bl 8017d4c mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8015490: 6afb ldr r3, [r7, #44] @ 0x2c 8015492: 3324 adds r3, #36 @ 0x24 8015494: 683a ldr r2, [r7, #0] 8015496: 4611 mov r1, r2 8015498: 4618 mov r0, r3 801549a: f001 f851 bl 8016540 prvUnlockQueue( pxQueue ); 801549e: 6af8 ldr r0, [r7, #44] @ 0x2c 80154a0: f000 f964 bl 801576c if( xTaskResumeAll() == pdFALSE ) 80154a4: f000 fe70 bl 8016188 80154a8: 4603 mov r3, r0 80154aa: 2b00 cmp r3, #0 80154ac: f47f af67 bne.w 801537e { portYIELD_WITHIN_API(); 80154b0: 4b18 ldr r3, [pc, #96] @ (8015514 ) 80154b2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80154b6: 601a str r2, [r3, #0] 80154b8: f3bf 8f4f dsb sy 80154bc: f3bf 8f6f isb sy 80154c0: e75d b.n 801537e } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 80154c2: 6af8 ldr r0, [r7, #44] @ 0x2c 80154c4: f000 f952 bl 801576c ( void ) xTaskResumeAll(); 80154c8: f000 fe5e bl 8016188 80154cc: e757 b.n 801537e } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 80154ce: 6af8 ldr r0, [r7, #44] @ 0x2c 80154d0: f000 f94c bl 801576c ( void ) xTaskResumeAll(); 80154d4: f000 fe58 bl 8016188 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80154d8: 6af8 ldr r0, [r7, #44] @ 0x2c 80154da: f000 f999 bl 8015810 80154de: 4603 mov r3, r0 80154e0: 2b00 cmp r3, #0 80154e2: f43f af4c beq.w 801537e #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 80154e6: 6b3b ldr r3, [r7, #48] @ 0x30 80154e8: 2b00 cmp r3, #0 80154ea: d00d beq.n 8015508 { taskENTER_CRITICAL(); 80154ec: f002 fbfc bl 8017ce8 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 80154f0: 6af8 ldr r0, [r7, #44] @ 0x2c 80154f2: f000 f893 bl 801561c 80154f6: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 80154f8: 6afb ldr r3, [r7, #44] @ 0x2c 80154fa: 689b ldr r3, [r3, #8] 80154fc: 6a79 ldr r1, [r7, #36] @ 0x24 80154fe: 4618 mov r0, r3 8015500: f001 fb64 bl 8016bcc } taskEXIT_CRITICAL(); 8015504: f002 fc22 bl 8017d4c } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015508: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 801550a: 4618 mov r0, r3 801550c: 3738 adds r7, #56 @ 0x38 801550e: 46bd mov sp, r7 8015510: bd80 pop {r7, pc} 8015512: bf00 nop 8015514: e000ed04 .word 0xe000ed04 08015518 : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 8015518: b580 push {r7, lr} 801551a: b08e sub sp, #56 @ 0x38 801551c: af00 add r7, sp, #0 801551e: 60f8 str r0, [r7, #12] 8015520: 60b9 str r1, [r7, #8] 8015522: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8015524: 68fb ldr r3, [r7, #12] 8015526: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8015528: 6b3b ldr r3, [r7, #48] @ 0x30 801552a: 2b00 cmp r3, #0 801552c: d10b bne.n 8015546 __asm volatile 801552e: f04f 0350 mov.w r3, #80 @ 0x50 8015532: f383 8811 msr BASEPRI, r3 8015536: f3bf 8f6f isb sy 801553a: f3bf 8f4f dsb sy 801553e: 623b str r3, [r7, #32] } 8015540: bf00 nop 8015542: bf00 nop 8015544: e7fd b.n 8015542 configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8015546: 68bb ldr r3, [r7, #8] 8015548: 2b00 cmp r3, #0 801554a: d103 bne.n 8015554 801554c: 6b3b ldr r3, [r7, #48] @ 0x30 801554e: 6c1b ldr r3, [r3, #64] @ 0x40 8015550: 2b00 cmp r3, #0 8015552: d101 bne.n 8015558 8015554: 2301 movs r3, #1 8015556: e000 b.n 801555a 8015558: 2300 movs r3, #0 801555a: 2b00 cmp r3, #0 801555c: d10b bne.n 8015576 __asm volatile 801555e: f04f 0350 mov.w r3, #80 @ 0x50 8015562: f383 8811 msr BASEPRI, r3 8015566: f3bf 8f6f isb sy 801556a: f3bf 8f4f dsb sy 801556e: 61fb str r3, [r7, #28] } 8015570: bf00 nop 8015572: bf00 nop 8015574: e7fd b.n 8015572 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8015576: f002 fc97 bl 8017ea8 __asm volatile 801557a: f3ef 8211 mrs r2, BASEPRI 801557e: f04f 0350 mov.w r3, #80 @ 0x50 8015582: f383 8811 msr BASEPRI, r3 8015586: f3bf 8f6f isb sy 801558a: f3bf 8f4f dsb sy 801558e: 61ba str r2, [r7, #24] 8015590: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 8015592: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8015594: 62fb str r3, [r7, #44] @ 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8015596: 6b3b ldr r3, [r7, #48] @ 0x30 8015598: 6b9b ldr r3, [r3, #56] @ 0x38 801559a: 62bb str r3, [r7, #40] @ 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 801559c: 6abb ldr r3, [r7, #40] @ 0x28 801559e: 2b00 cmp r3, #0 80155a0: d02f beq.n 8015602 { const int8_t cRxLock = pxQueue->cRxLock; 80155a2: 6b3b ldr r3, [r7, #48] @ 0x30 80155a4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80155a8: f887 3027 strb.w r3, [r7, #39] @ 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 80155ac: 68b9 ldr r1, [r7, #8] 80155ae: 6b38 ldr r0, [r7, #48] @ 0x30 80155b0: f000 f8b6 bl 8015720 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80155b4: 6abb ldr r3, [r7, #40] @ 0x28 80155b6: 1e5a subs r2, r3, #1 80155b8: 6b3b ldr r3, [r7, #48] @ 0x30 80155ba: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 80155bc: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 80155c0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80155c4: d112 bne.n 80155ec { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80155c6: 6b3b ldr r3, [r7, #48] @ 0x30 80155c8: 691b ldr r3, [r3, #16] 80155ca: 2b00 cmp r3, #0 80155cc: d016 beq.n 80155fc { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80155ce: 6b3b ldr r3, [r7, #48] @ 0x30 80155d0: 3310 adds r3, #16 80155d2: 4618 mov r0, r3 80155d4: f001 f806 bl 80165e4 80155d8: 4603 mov r3, r0 80155da: 2b00 cmp r3, #0 80155dc: d00e beq.n 80155fc { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 80155de: 687b ldr r3, [r7, #4] 80155e0: 2b00 cmp r3, #0 80155e2: d00b beq.n 80155fc { *pxHigherPriorityTaskWoken = pdTRUE; 80155e4: 687b ldr r3, [r7, #4] 80155e6: 2201 movs r2, #1 80155e8: 601a str r2, [r3, #0] 80155ea: e007 b.n 80155fc } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 80155ec: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80155f0: 3301 adds r3, #1 80155f2: b2db uxtb r3, r3 80155f4: b25a sxtb r2, r3 80155f6: 6b3b ldr r3, [r7, #48] @ 0x30 80155f8: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 80155fc: 2301 movs r3, #1 80155fe: 637b str r3, [r7, #52] @ 0x34 8015600: e001 b.n 8015606 } else { xReturn = pdFAIL; 8015602: 2300 movs r3, #0 8015604: 637b str r3, [r7, #52] @ 0x34 8015606: 6afb ldr r3, [r7, #44] @ 0x2c 8015608: 613b str r3, [r7, #16] __asm volatile 801560a: 693b ldr r3, [r7, #16] 801560c: f383 8811 msr BASEPRI, r3 } 8015610: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8015612: 6b7b ldr r3, [r7, #52] @ 0x34 } 8015614: 4618 mov r0, r3 8015616: 3738 adds r7, #56 @ 0x38 8015618: 46bd mov sp, r7 801561a: bd80 pop {r7, pc} 0801561c : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 801561c: b480 push {r7} 801561e: b085 sub sp, #20 8015620: af00 add r7, sp, #0 8015622: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 8015624: 687b ldr r3, [r7, #4] 8015626: 6a5b ldr r3, [r3, #36] @ 0x24 8015628: 2b00 cmp r3, #0 801562a: d006 beq.n 801563a { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 801562c: 687b ldr r3, [r7, #4] 801562e: 6b1b ldr r3, [r3, #48] @ 0x30 8015630: 681b ldr r3, [r3, #0] 8015632: f1c3 0338 rsb r3, r3, #56 @ 0x38 8015636: 60fb str r3, [r7, #12] 8015638: e001 b.n 801563e } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 801563a: 2300 movs r3, #0 801563c: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 801563e: 68fb ldr r3, [r7, #12] } 8015640: 4618 mov r0, r3 8015642: 3714 adds r7, #20 8015644: 46bd mov sp, r7 8015646: f85d 7b04 ldr.w r7, [sp], #4 801564a: 4770 bx lr 0801564c : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 801564c: b580 push {r7, lr} 801564e: b086 sub sp, #24 8015650: af00 add r7, sp, #0 8015652: 60f8 str r0, [r7, #12] 8015654: 60b9 str r1, [r7, #8] 8015656: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8015658: 2300 movs r3, #0 801565a: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 801565c: 68fb ldr r3, [r7, #12] 801565e: 6b9b ldr r3, [r3, #56] @ 0x38 8015660: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 8015662: 68fb ldr r3, [r7, #12] 8015664: 6c1b ldr r3, [r3, #64] @ 0x40 8015666: 2b00 cmp r3, #0 8015668: d10d bne.n 8015686 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801566a: 68fb ldr r3, [r7, #12] 801566c: 681b ldr r3, [r3, #0] 801566e: 2b00 cmp r3, #0 8015670: d14d bne.n 801570e { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 8015672: 68fb ldr r3, [r7, #12] 8015674: 689b ldr r3, [r3, #8] 8015676: 4618 mov r0, r3 8015678: f001 fa38 bl 8016aec 801567c: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 801567e: 68fb ldr r3, [r7, #12] 8015680: 2200 movs r2, #0 8015682: 609a str r2, [r3, #8] 8015684: e043 b.n 801570e mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8015686: 687b ldr r3, [r7, #4] 8015688: 2b00 cmp r3, #0 801568a: d119 bne.n 80156c0 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 801568c: 68fb ldr r3, [r7, #12] 801568e: 6858 ldr r0, [r3, #4] 8015690: 68fb ldr r3, [r7, #12] 8015692: 6c1b ldr r3, [r3, #64] @ 0x40 8015694: 461a mov r2, r3 8015696: 68b9 ldr r1, [r7, #8] 8015698: f002 fec0 bl 801841c pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 801569c: 68fb ldr r3, [r7, #12] 801569e: 685a ldr r2, [r3, #4] 80156a0: 68fb ldr r3, [r7, #12] 80156a2: 6c1b ldr r3, [r3, #64] @ 0x40 80156a4: 441a add r2, r3 80156a6: 68fb ldr r3, [r7, #12] 80156a8: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80156aa: 68fb ldr r3, [r7, #12] 80156ac: 685a ldr r2, [r3, #4] 80156ae: 68fb ldr r3, [r7, #12] 80156b0: 689b ldr r3, [r3, #8] 80156b2: 429a cmp r2, r3 80156b4: d32b bcc.n 801570e { pxQueue->pcWriteTo = pxQueue->pcHead; 80156b6: 68fb ldr r3, [r7, #12] 80156b8: 681a ldr r2, [r3, #0] 80156ba: 68fb ldr r3, [r7, #12] 80156bc: 605a str r2, [r3, #4] 80156be: e026 b.n 801570e mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 80156c0: 68fb ldr r3, [r7, #12] 80156c2: 68d8 ldr r0, [r3, #12] 80156c4: 68fb ldr r3, [r7, #12] 80156c6: 6c1b ldr r3, [r3, #64] @ 0x40 80156c8: 461a mov r2, r3 80156ca: 68b9 ldr r1, [r7, #8] 80156cc: f002 fea6 bl 801841c pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 80156d0: 68fb ldr r3, [r7, #12] 80156d2: 68da ldr r2, [r3, #12] 80156d4: 68fb ldr r3, [r7, #12] 80156d6: 6c1b ldr r3, [r3, #64] @ 0x40 80156d8: 425b negs r3, r3 80156da: 441a add r2, r3 80156dc: 68fb ldr r3, [r7, #12] 80156de: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80156e0: 68fb ldr r3, [r7, #12] 80156e2: 68da ldr r2, [r3, #12] 80156e4: 68fb ldr r3, [r7, #12] 80156e6: 681b ldr r3, [r3, #0] 80156e8: 429a cmp r2, r3 80156ea: d207 bcs.n 80156fc { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 80156ec: 68fb ldr r3, [r7, #12] 80156ee: 689a ldr r2, [r3, #8] 80156f0: 68fb ldr r3, [r7, #12] 80156f2: 6c1b ldr r3, [r3, #64] @ 0x40 80156f4: 425b negs r3, r3 80156f6: 441a add r2, r3 80156f8: 68fb ldr r3, [r7, #12] 80156fa: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 80156fc: 687b ldr r3, [r7, #4] 80156fe: 2b02 cmp r3, #2 8015700: d105 bne.n 801570e { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8015702: 693b ldr r3, [r7, #16] 8015704: 2b00 cmp r3, #0 8015706: d002 beq.n 801570e { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8015708: 693b ldr r3, [r7, #16] 801570a: 3b01 subs r3, #1 801570c: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 801570e: 693b ldr r3, [r7, #16] 8015710: 1c5a adds r2, r3, #1 8015712: 68fb ldr r3, [r7, #12] 8015714: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8015716: 697b ldr r3, [r7, #20] } 8015718: 4618 mov r0, r3 801571a: 3718 adds r7, #24 801571c: 46bd mov sp, r7 801571e: bd80 pop {r7, pc} 08015720 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8015720: b580 push {r7, lr} 8015722: b082 sub sp, #8 8015724: af00 add r7, sp, #0 8015726: 6078 str r0, [r7, #4] 8015728: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 801572a: 687b ldr r3, [r7, #4] 801572c: 6c1b ldr r3, [r3, #64] @ 0x40 801572e: 2b00 cmp r3, #0 8015730: d018 beq.n 8015764 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 8015732: 687b ldr r3, [r7, #4] 8015734: 68da ldr r2, [r3, #12] 8015736: 687b ldr r3, [r7, #4] 8015738: 6c1b ldr r3, [r3, #64] @ 0x40 801573a: 441a add r2, r3 801573c: 687b ldr r3, [r7, #4] 801573e: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8015740: 687b ldr r3, [r7, #4] 8015742: 68da ldr r2, [r3, #12] 8015744: 687b ldr r3, [r7, #4] 8015746: 689b ldr r3, [r3, #8] 8015748: 429a cmp r2, r3 801574a: d303 bcc.n 8015754 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 801574c: 687b ldr r3, [r7, #4] 801574e: 681a ldr r2, [r3, #0] 8015750: 687b ldr r3, [r7, #4] 8015752: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8015754: 687b ldr r3, [r7, #4] 8015756: 68d9 ldr r1, [r3, #12] 8015758: 687b ldr r3, [r7, #4] 801575a: 6c1b ldr r3, [r3, #64] @ 0x40 801575c: 461a mov r2, r3 801575e: 6838 ldr r0, [r7, #0] 8015760: f002 fe5c bl 801841c } } 8015764: bf00 nop 8015766: 3708 adds r7, #8 8015768: 46bd mov sp, r7 801576a: bd80 pop {r7, pc} 0801576c : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 801576c: b580 push {r7, lr} 801576e: b084 sub sp, #16 8015770: af00 add r7, sp, #0 8015772: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 8015774: f002 fab8 bl 8017ce8 { int8_t cTxLock = pxQueue->cTxLock; 8015778: 687b ldr r3, [r7, #4] 801577a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801577e: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8015780: e011 b.n 80157a6 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8015782: 687b ldr r3, [r7, #4] 8015784: 6a5b ldr r3, [r3, #36] @ 0x24 8015786: 2b00 cmp r3, #0 8015788: d012 beq.n 80157b0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 801578a: 687b ldr r3, [r7, #4] 801578c: 3324 adds r3, #36 @ 0x24 801578e: 4618 mov r0, r3 8015790: f000 ff28 bl 80165e4 8015794: 4603 mov r3, r0 8015796: 2b00 cmp r3, #0 8015798: d001 beq.n 801579e { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 801579a: f001 f829 bl 80167f0 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 801579e: 7bfb ldrb r3, [r7, #15] 80157a0: 3b01 subs r3, #1 80157a2: b2db uxtb r3, r3 80157a4: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 80157a6: f997 300f ldrsb.w r3, [r7, #15] 80157aa: 2b00 cmp r3, #0 80157ac: dce9 bgt.n 8015782 80157ae: e000 b.n 80157b2 break; 80157b0: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 80157b2: 687b ldr r3, [r7, #4] 80157b4: 22ff movs r2, #255 @ 0xff 80157b6: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 80157ba: f002 fac7 bl 8017d4c /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 80157be: f002 fa93 bl 8017ce8 { int8_t cRxLock = pxQueue->cRxLock; 80157c2: 687b ldr r3, [r7, #4] 80157c4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80157c8: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80157ca: e011 b.n 80157f0 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80157cc: 687b ldr r3, [r7, #4] 80157ce: 691b ldr r3, [r3, #16] 80157d0: 2b00 cmp r3, #0 80157d2: d012 beq.n 80157fa { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80157d4: 687b ldr r3, [r7, #4] 80157d6: 3310 adds r3, #16 80157d8: 4618 mov r0, r3 80157da: f000 ff03 bl 80165e4 80157de: 4603 mov r3, r0 80157e0: 2b00 cmp r3, #0 80157e2: d001 beq.n 80157e8 { vTaskMissedYield(); 80157e4: f001 f804 bl 80167f0 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 80157e8: 7bbb ldrb r3, [r7, #14] 80157ea: 3b01 subs r3, #1 80157ec: b2db uxtb r3, r3 80157ee: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80157f0: f997 300e ldrsb.w r3, [r7, #14] 80157f4: 2b00 cmp r3, #0 80157f6: dce9 bgt.n 80157cc 80157f8: e000 b.n 80157fc } else { break; 80157fa: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 80157fc: 687b ldr r3, [r7, #4] 80157fe: 22ff movs r2, #255 @ 0xff 8015800: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 8015804: f002 faa2 bl 8017d4c } 8015808: bf00 nop 801580a: 3710 adds r7, #16 801580c: 46bd mov sp, r7 801580e: bd80 pop {r7, pc} 08015810 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 8015810: b580 push {r7, lr} 8015812: b084 sub sp, #16 8015814: af00 add r7, sp, #0 8015816: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8015818: f002 fa66 bl 8017ce8 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 801581c: 687b ldr r3, [r7, #4] 801581e: 6b9b ldr r3, [r3, #56] @ 0x38 8015820: 2b00 cmp r3, #0 8015822: d102 bne.n 801582a { xReturn = pdTRUE; 8015824: 2301 movs r3, #1 8015826: 60fb str r3, [r7, #12] 8015828: e001 b.n 801582e } else { xReturn = pdFALSE; 801582a: 2300 movs r3, #0 801582c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 801582e: f002 fa8d bl 8017d4c return xReturn; 8015832: 68fb ldr r3, [r7, #12] } 8015834: 4618 mov r0, r3 8015836: 3710 adds r7, #16 8015838: 46bd mov sp, r7 801583a: bd80 pop {r7, pc} 0801583c : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 801583c: b580 push {r7, lr} 801583e: b084 sub sp, #16 8015840: af00 add r7, sp, #0 8015842: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8015844: f002 fa50 bl 8017ce8 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8015848: 687b ldr r3, [r7, #4] 801584a: 6b9a ldr r2, [r3, #56] @ 0x38 801584c: 687b ldr r3, [r7, #4] 801584e: 6bdb ldr r3, [r3, #60] @ 0x3c 8015850: 429a cmp r2, r3 8015852: d102 bne.n 801585a { xReturn = pdTRUE; 8015854: 2301 movs r3, #1 8015856: 60fb str r3, [r7, #12] 8015858: e001 b.n 801585e } else { xReturn = pdFALSE; 801585a: 2300 movs r3, #0 801585c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 801585e: f002 fa75 bl 8017d4c return xReturn; 8015862: 68fb ldr r3, [r7, #12] } 8015864: 4618 mov r0, r3 8015866: 3710 adds r7, #16 8015868: 46bd mov sp, r7 801586a: bd80 pop {r7, pc} 0801586c : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 801586c: b480 push {r7} 801586e: b085 sub sp, #20 8015870: af00 add r7, sp, #0 8015872: 6078 str r0, [r7, #4] 8015874: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 8015876: 2300 movs r3, #0 8015878: 60fb str r3, [r7, #12] 801587a: e014 b.n 80158a6 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 801587c: 4a0f ldr r2, [pc, #60] @ (80158bc ) 801587e: 68fb ldr r3, [r7, #12] 8015880: f852 3033 ldr.w r3, [r2, r3, lsl #3] 8015884: 2b00 cmp r3, #0 8015886: d10b bne.n 80158a0 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8015888: 490c ldr r1, [pc, #48] @ (80158bc ) 801588a: 68fb ldr r3, [r7, #12] 801588c: 683a ldr r2, [r7, #0] 801588e: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 8015892: 4a0a ldr r2, [pc, #40] @ (80158bc ) 8015894: 68fb ldr r3, [r7, #12] 8015896: 00db lsls r3, r3, #3 8015898: 4413 add r3, r2 801589a: 687a ldr r2, [r7, #4] 801589c: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 801589e: e006 b.n 80158ae for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 80158a0: 68fb ldr r3, [r7, #12] 80158a2: 3301 adds r3, #1 80158a4: 60fb str r3, [r7, #12] 80158a6: 68fb ldr r3, [r7, #12] 80158a8: 2b07 cmp r3, #7 80158aa: d9e7 bls.n 801587c else { mtCOVERAGE_TEST_MARKER(); } } } 80158ac: bf00 nop 80158ae: bf00 nop 80158b0: 3714 adds r7, #20 80158b2: 46bd mov sp, r7 80158b4: f85d 7b04 ldr.w r7, [sp], #4 80158b8: 4770 bx lr 80158ba: bf00 nop 80158bc: 240029b8 .word 0x240029b8 080158c0 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 80158c0: b580 push {r7, lr} 80158c2: b086 sub sp, #24 80158c4: af00 add r7, sp, #0 80158c6: 60f8 str r0, [r7, #12] 80158c8: 60b9 str r1, [r7, #8] 80158ca: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 80158cc: 68fb ldr r3, [r7, #12] 80158ce: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 80158d0: f002 fa0a bl 8017ce8 80158d4: 697b ldr r3, [r7, #20] 80158d6: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80158da: b25b sxtb r3, r3 80158dc: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80158e0: d103 bne.n 80158ea 80158e2: 697b ldr r3, [r7, #20] 80158e4: 2200 movs r2, #0 80158e6: f883 2044 strb.w r2, [r3, #68] @ 0x44 80158ea: 697b ldr r3, [r7, #20] 80158ec: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80158f0: b25b sxtb r3, r3 80158f2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80158f6: d103 bne.n 8015900 80158f8: 697b ldr r3, [r7, #20] 80158fa: 2200 movs r2, #0 80158fc: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015900: f002 fa24 bl 8017d4c if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 8015904: 697b ldr r3, [r7, #20] 8015906: 6b9b ldr r3, [r3, #56] @ 0x38 8015908: 2b00 cmp r3, #0 801590a: d106 bne.n 801591a { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 801590c: 697b ldr r3, [r7, #20] 801590e: 3324 adds r3, #36 @ 0x24 8015910: 687a ldr r2, [r7, #4] 8015912: 68b9 ldr r1, [r7, #8] 8015914: 4618 mov r0, r3 8015916: f000 fe39 bl 801658c } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 801591a: 6978 ldr r0, [r7, #20] 801591c: f7ff ff26 bl 801576c } 8015920: bf00 nop 8015922: 3718 adds r7, #24 8015924: 46bd mov sp, r7 8015926: bd80 pop {r7, pc} 08015928 : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 8015928: b480 push {r7} 801592a: b087 sub sp, #28 801592c: af00 add r7, sp, #0 801592e: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8015930: 687b ldr r3, [r7, #4] 8015932: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 8015934: 693b ldr r3, [r7, #16] 8015936: 2b00 cmp r3, #0 8015938: d10b bne.n 8015952 __asm volatile 801593a: f04f 0350 mov.w r3, #80 @ 0x50 801593e: f383 8811 msr BASEPRI, r3 8015942: f3bf 8f6f isb sy 8015946: f3bf 8f4f dsb sy 801594a: 60fb str r3, [r7, #12] } 801594c: bf00 nop 801594e: bf00 nop 8015950: e7fd b.n 801594e xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 8015952: 693b ldr r3, [r7, #16] 8015954: 689a ldr r2, [r3, #8] 8015956: 693b ldr r3, [r7, #16] 8015958: 681b ldr r3, [r3, #0] 801595a: 4413 add r3, r2 801595c: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 801595e: 693b ldr r3, [r7, #16] 8015960: 685b ldr r3, [r3, #4] 8015962: 697a ldr r2, [r7, #20] 8015964: 1ad3 subs r3, r2, r3 8015966: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 8015968: 697b ldr r3, [r7, #20] 801596a: 3b01 subs r3, #1 801596c: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 801596e: 693b ldr r3, [r7, #16] 8015970: 689b ldr r3, [r3, #8] 8015972: 697a ldr r2, [r7, #20] 8015974: 429a cmp r2, r3 8015976: d304 bcc.n 8015982 { xSpace -= pxStreamBuffer->xLength; 8015978: 693b ldr r3, [r7, #16] 801597a: 689b ldr r3, [r3, #8] 801597c: 697a ldr r2, [r7, #20] 801597e: 1ad3 subs r3, r2, r3 8015980: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 8015982: 697b ldr r3, [r7, #20] } 8015984: 4618 mov r0, r3 8015986: 371c adds r7, #28 8015988: 46bd mov sp, r7 801598a: f85d 7b04 ldr.w r7, [sp], #4 801598e: 4770 bx lr 08015990 : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 8015990: b580 push {r7, lr} 8015992: b090 sub sp, #64 @ 0x40 8015994: af02 add r7, sp, #8 8015996: 60f8 str r0, [r7, #12] 8015998: 60b9 str r1, [r7, #8] 801599a: 607a str r2, [r7, #4] 801599c: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 801599e: 68fb ldr r3, [r7, #12] 80159a0: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 80159a2: 2300 movs r3, #0 80159a4: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 80159a6: 687b ldr r3, [r7, #4] 80159a8: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 80159aa: 68bb ldr r3, [r7, #8] 80159ac: 2b00 cmp r3, #0 80159ae: d10b bne.n 80159c8 __asm volatile 80159b0: f04f 0350 mov.w r3, #80 @ 0x50 80159b4: f383 8811 msr BASEPRI, r3 80159b8: f3bf 8f6f isb sy 80159bc: f3bf 8f4f dsb sy 80159c0: 627b str r3, [r7, #36] @ 0x24 } 80159c2: bf00 nop 80159c4: bf00 nop 80159c6: e7fd b.n 80159c4 configASSERT( pxStreamBuffer ); 80159c8: 6afb ldr r3, [r7, #44] @ 0x2c 80159ca: 2b00 cmp r3, #0 80159cc: d10b bne.n 80159e6 __asm volatile 80159ce: f04f 0350 mov.w r3, #80 @ 0x50 80159d2: f383 8811 msr BASEPRI, r3 80159d6: f3bf 8f6f isb sy 80159da: f3bf 8f4f dsb sy 80159de: 623b str r3, [r7, #32] } 80159e0: bf00 nop 80159e2: bf00 nop 80159e4: e7fd b.n 80159e2 /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 80159e6: 6afb ldr r3, [r7, #44] @ 0x2c 80159e8: 7f1b ldrb r3, [r3, #28] 80159ea: f003 0301 and.w r3, r3, #1 80159ee: 2b00 cmp r3, #0 80159f0: d012 beq.n 8015a18 { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 80159f2: 6b3b ldr r3, [r7, #48] @ 0x30 80159f4: 3304 adds r3, #4 80159f6: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 80159f8: 6b3a ldr r2, [r7, #48] @ 0x30 80159fa: 687b ldr r3, [r7, #4] 80159fc: 429a cmp r2, r3 80159fe: d80b bhi.n 8015a18 __asm volatile 8015a00: f04f 0350 mov.w r3, #80 @ 0x50 8015a04: f383 8811 msr BASEPRI, r3 8015a08: f3bf 8f6f isb sy 8015a0c: f3bf 8f4f dsb sy 8015a10: 61fb str r3, [r7, #28] } 8015a12: bf00 nop 8015a14: bf00 nop 8015a16: e7fd b.n 8015a14 else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 8015a18: 683b ldr r3, [r7, #0] 8015a1a: 2b00 cmp r3, #0 8015a1c: d03f beq.n 8015a9e { vTaskSetTimeOutState( &xTimeOut ); 8015a1e: f107 0310 add.w r3, r7, #16 8015a22: 4618 mov r0, r3 8015a24: f000 fe42 bl 80166ac do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 8015a28: f002 f95e bl 8017ce8 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015a2c: 6af8 ldr r0, [r7, #44] @ 0x2c 8015a2e: f7ff ff7b bl 8015928 8015a32: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 8015a34: 6b7a ldr r2, [r7, #52] @ 0x34 8015a36: 6b3b ldr r3, [r7, #48] @ 0x30 8015a38: 429a cmp r2, r3 8015a3a: d218 bcs.n 8015a6e { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 8015a3c: 2000 movs r0, #0 8015a3e: f001 fb65 bl 801710c /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 8015a42: 6afb ldr r3, [r7, #44] @ 0x2c 8015a44: 695b ldr r3, [r3, #20] 8015a46: 2b00 cmp r3, #0 8015a48: d00b beq.n 8015a62 __asm volatile 8015a4a: f04f 0350 mov.w r3, #80 @ 0x50 8015a4e: f383 8811 msr BASEPRI, r3 8015a52: f3bf 8f6f isb sy 8015a56: f3bf 8f4f dsb sy 8015a5a: 61bb str r3, [r7, #24] } 8015a5c: bf00 nop 8015a5e: bf00 nop 8015a60: e7fd b.n 8015a5e pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 8015a62: f000 ffad bl 80169c0 8015a66: 4602 mov r2, r0 8015a68: 6afb ldr r3, [r7, #44] @ 0x2c 8015a6a: 615a str r2, [r3, #20] 8015a6c: e002 b.n 8015a74 } else { taskEXIT_CRITICAL(); 8015a6e: f002 f96d bl 8017d4c break; 8015a72: e014 b.n 8015a9e } } taskEXIT_CRITICAL(); 8015a74: f002 f96a bl 8017d4c traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 8015a78: 683b ldr r3, [r7, #0] 8015a7a: 2200 movs r2, #0 8015a7c: 2100 movs r1, #0 8015a7e: 2000 movs r0, #0 8015a80: f001 f93c bl 8016cfc pxStreamBuffer->xTaskWaitingToSend = NULL; 8015a84: 6afb ldr r3, [r7, #44] @ 0x2c 8015a86: 2200 movs r2, #0 8015a88: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 8015a8a: 463a mov r2, r7 8015a8c: f107 0310 add.w r3, r7, #16 8015a90: 4611 mov r1, r2 8015a92: 4618 mov r0, r3 8015a94: f000 fe48 bl 8016728 8015a98: 4603 mov r3, r0 8015a9a: 2b00 cmp r3, #0 8015a9c: d0c4 beq.n 8015a28 else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 8015a9e: 6b7b ldr r3, [r7, #52] @ 0x34 8015aa0: 2b00 cmp r3, #0 8015aa2: d103 bne.n 8015aac { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015aa4: 6af8 ldr r0, [r7, #44] @ 0x2c 8015aa6: f7ff ff3f bl 8015928 8015aaa: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 8015aac: 6b3b ldr r3, [r7, #48] @ 0x30 8015aae: 9300 str r3, [sp, #0] 8015ab0: 6b7b ldr r3, [r7, #52] @ 0x34 8015ab2: 687a ldr r2, [r7, #4] 8015ab4: 68b9 ldr r1, [r7, #8] 8015ab6: 6af8 ldr r0, [r7, #44] @ 0x2c 8015ab8: f000 f823 bl 8015b02 8015abc: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 8015abe: 6abb ldr r3, [r7, #40] @ 0x28 8015ac0: 2b00 cmp r3, #0 8015ac2: d019 beq.n 8015af8 { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 8015ac4: 6af8 ldr r0, [r7, #44] @ 0x2c 8015ac6: f000 f8ce bl 8015c66 8015aca: 4602 mov r2, r0 8015acc: 6afb ldr r3, [r7, #44] @ 0x2c 8015ace: 68db ldr r3, [r3, #12] 8015ad0: 429a cmp r2, r3 8015ad2: d311 bcc.n 8015af8 { sbSEND_COMPLETED( pxStreamBuffer ); 8015ad4: f000 fb4a bl 801616c 8015ad8: 6afb ldr r3, [r7, #44] @ 0x2c 8015ada: 691b ldr r3, [r3, #16] 8015adc: 2b00 cmp r3, #0 8015ade: d009 beq.n 8015af4 8015ae0: 6afb ldr r3, [r7, #44] @ 0x2c 8015ae2: 6918 ldr r0, [r3, #16] 8015ae4: 2300 movs r3, #0 8015ae6: 2200 movs r2, #0 8015ae8: 2100 movs r1, #0 8015aea: f001 f967 bl 8016dbc 8015aee: 6afb ldr r3, [r7, #44] @ 0x2c 8015af0: 2200 movs r2, #0 8015af2: 611a str r2, [r3, #16] 8015af4: f000 fb48 bl 8016188 { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 8015af8: 6abb ldr r3, [r7, #40] @ 0x28 } 8015afa: 4618 mov r0, r3 8015afc: 3738 adds r7, #56 @ 0x38 8015afe: 46bd mov sp, r7 8015b00: bd80 pop {r7, pc} 08015b02 : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 8015b02: b580 push {r7, lr} 8015b04: b086 sub sp, #24 8015b06: af00 add r7, sp, #0 8015b08: 60f8 str r0, [r7, #12] 8015b0a: 60b9 str r1, [r7, #8] 8015b0c: 607a str r2, [r7, #4] 8015b0e: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 8015b10: 683b ldr r3, [r7, #0] 8015b12: 2b00 cmp r3, #0 8015b14: d102 bne.n 8015b1c { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 8015b16: 2300 movs r3, #0 8015b18: 617b str r3, [r7, #20] 8015b1a: e01d b.n 8015b58 } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 8015b1c: 68fb ldr r3, [r7, #12] 8015b1e: 7f1b ldrb r3, [r3, #28] 8015b20: f003 0301 and.w r3, r3, #1 8015b24: 2b00 cmp r3, #0 8015b26: d108 bne.n 8015b3a { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 8015b28: 2301 movs r3, #1 8015b2a: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 8015b2c: 687a ldr r2, [r7, #4] 8015b2e: 683b ldr r3, [r7, #0] 8015b30: 4293 cmp r3, r2 8015b32: bf28 it cs 8015b34: 4613 movcs r3, r2 8015b36: 607b str r3, [r7, #4] 8015b38: e00e b.n 8015b58 } else if( xSpace >= xRequiredSpace ) 8015b3a: 683a ldr r2, [r7, #0] 8015b3c: 6a3b ldr r3, [r7, #32] 8015b3e: 429a cmp r2, r3 8015b40: d308 bcc.n 8015b54 { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 8015b42: 2301 movs r3, #1 8015b44: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 8015b46: 1d3b adds r3, r7, #4 8015b48: 2204 movs r2, #4 8015b4a: 4619 mov r1, r3 8015b4c: 68f8 ldr r0, [r7, #12] 8015b4e: f000 f815 bl 8015b7c 8015b52: e001 b.n 8015b58 } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 8015b54: 2300 movs r3, #0 8015b56: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 8015b58: 697b ldr r3, [r7, #20] 8015b5a: 2b00 cmp r3, #0 8015b5c: d007 beq.n 8015b6e { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 8015b5e: 687b ldr r3, [r7, #4] 8015b60: 461a mov r2, r3 8015b62: 68b9 ldr r1, [r7, #8] 8015b64: 68f8 ldr r0, [r7, #12] 8015b66: f000 f809 bl 8015b7c 8015b6a: 6138 str r0, [r7, #16] 8015b6c: e001 b.n 8015b72 } else { xReturn = 0; 8015b6e: 2300 movs r3, #0 8015b70: 613b str r3, [r7, #16] } return xReturn; 8015b72: 693b ldr r3, [r7, #16] } 8015b74: 4618 mov r0, r3 8015b76: 3718 adds r7, #24 8015b78: 46bd mov sp, r7 8015b7a: bd80 pop {r7, pc} 08015b7c : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 8015b7c: b580 push {r7, lr} 8015b7e: b08a sub sp, #40 @ 0x28 8015b80: af00 add r7, sp, #0 8015b82: 60f8 str r0, [r7, #12] 8015b84: 60b9 str r1, [r7, #8] 8015b86: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 8015b88: 687b ldr r3, [r7, #4] 8015b8a: 2b00 cmp r3, #0 8015b8c: d10b bne.n 8015ba6 __asm volatile 8015b8e: f04f 0350 mov.w r3, #80 @ 0x50 8015b92: f383 8811 msr BASEPRI, r3 8015b96: f3bf 8f6f isb sy 8015b9a: f3bf 8f4f dsb sy 8015b9e: 61fb str r3, [r7, #28] } 8015ba0: bf00 nop 8015ba2: bf00 nop 8015ba4: e7fd b.n 8015ba2 xNextHead = pxStreamBuffer->xHead; 8015ba6: 68fb ldr r3, [r7, #12] 8015ba8: 685b ldr r3, [r3, #4] 8015baa: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 8015bac: 68fb ldr r3, [r7, #12] 8015bae: 689a ldr r2, [r3, #8] 8015bb0: 6a7b ldr r3, [r7, #36] @ 0x24 8015bb2: 1ad3 subs r3, r2, r3 8015bb4: 687a ldr r2, [r7, #4] 8015bb6: 4293 cmp r3, r2 8015bb8: bf28 it cs 8015bba: 4613 movcs r3, r2 8015bbc: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 8015bbe: 6a7a ldr r2, [r7, #36] @ 0x24 8015bc0: 6a3b ldr r3, [r7, #32] 8015bc2: 441a add r2, r3 8015bc4: 68fb ldr r3, [r7, #12] 8015bc6: 689b ldr r3, [r3, #8] 8015bc8: 429a cmp r2, r3 8015bca: d90b bls.n 8015be4 __asm volatile 8015bcc: f04f 0350 mov.w r3, #80 @ 0x50 8015bd0: f383 8811 msr BASEPRI, r3 8015bd4: f3bf 8f6f isb sy 8015bd8: f3bf 8f4f dsb sy 8015bdc: 61bb str r3, [r7, #24] } 8015bde: bf00 nop 8015be0: bf00 nop 8015be2: e7fd b.n 8015be0 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015be4: 68fb ldr r3, [r7, #12] 8015be6: 699a ldr r2, [r3, #24] 8015be8: 6a7b ldr r3, [r7, #36] @ 0x24 8015bea: 4413 add r3, r2 8015bec: 6a3a ldr r2, [r7, #32] 8015bee: 68b9 ldr r1, [r7, #8] 8015bf0: 4618 mov r0, r3 8015bf2: f002 fc13 bl 801841c /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 8015bf6: 687a ldr r2, [r7, #4] 8015bf8: 6a3b ldr r3, [r7, #32] 8015bfa: 429a cmp r2, r3 8015bfc: d91d bls.n 8015c3a { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 8015bfe: 687a ldr r2, [r7, #4] 8015c00: 6a3b ldr r3, [r7, #32] 8015c02: 1ad2 subs r2, r2, r3 8015c04: 68fb ldr r3, [r7, #12] 8015c06: 689b ldr r3, [r3, #8] 8015c08: 429a cmp r2, r3 8015c0a: d90b bls.n 8015c24 __asm volatile 8015c0c: f04f 0350 mov.w r3, #80 @ 0x50 8015c10: f383 8811 msr BASEPRI, r3 8015c14: f3bf 8f6f isb sy 8015c18: f3bf 8f4f dsb sy 8015c1c: 617b str r3, [r7, #20] } 8015c1e: bf00 nop 8015c20: bf00 nop 8015c22: e7fd b.n 8015c20 ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015c24: 68fb ldr r3, [r7, #12] 8015c26: 6998 ldr r0, [r3, #24] 8015c28: 68ba ldr r2, [r7, #8] 8015c2a: 6a3b ldr r3, [r7, #32] 8015c2c: 18d1 adds r1, r2, r3 8015c2e: 687a ldr r2, [r7, #4] 8015c30: 6a3b ldr r3, [r7, #32] 8015c32: 1ad3 subs r3, r2, r3 8015c34: 461a mov r2, r3 8015c36: f002 fbf1 bl 801841c else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 8015c3a: 6a7a ldr r2, [r7, #36] @ 0x24 8015c3c: 687b ldr r3, [r7, #4] 8015c3e: 4413 add r3, r2 8015c40: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 8015c42: 68fb ldr r3, [r7, #12] 8015c44: 689b ldr r3, [r3, #8] 8015c46: 6a7a ldr r2, [r7, #36] @ 0x24 8015c48: 429a cmp r2, r3 8015c4a: d304 bcc.n 8015c56 { xNextHead -= pxStreamBuffer->xLength; 8015c4c: 68fb ldr r3, [r7, #12] 8015c4e: 689b ldr r3, [r3, #8] 8015c50: 6a7a ldr r2, [r7, #36] @ 0x24 8015c52: 1ad3 subs r3, r2, r3 8015c54: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 8015c56: 68fb ldr r3, [r7, #12] 8015c58: 6a7a ldr r2, [r7, #36] @ 0x24 8015c5a: 605a str r2, [r3, #4] return xCount; 8015c5c: 687b ldr r3, [r7, #4] } 8015c5e: 4618 mov r0, r3 8015c60: 3728 adds r7, #40 @ 0x28 8015c62: 46bd mov sp, r7 8015c64: bd80 pop {r7, pc} 08015c66 : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 8015c66: b480 push {r7} 8015c68: b085 sub sp, #20 8015c6a: af00 add r7, sp, #0 8015c6c: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 8015c6e: 687b ldr r3, [r7, #4] 8015c70: 689a ldr r2, [r3, #8] 8015c72: 687b ldr r3, [r7, #4] 8015c74: 685b ldr r3, [r3, #4] 8015c76: 4413 add r3, r2 8015c78: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 8015c7a: 687b ldr r3, [r7, #4] 8015c7c: 681b ldr r3, [r3, #0] 8015c7e: 68fa ldr r2, [r7, #12] 8015c80: 1ad3 subs r3, r2, r3 8015c82: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 8015c84: 687b ldr r3, [r7, #4] 8015c86: 689b ldr r3, [r3, #8] 8015c88: 68fa ldr r2, [r7, #12] 8015c8a: 429a cmp r2, r3 8015c8c: d304 bcc.n 8015c98 { xCount -= pxStreamBuffer->xLength; 8015c8e: 687b ldr r3, [r7, #4] 8015c90: 689b ldr r3, [r3, #8] 8015c92: 68fa ldr r2, [r7, #12] 8015c94: 1ad3 subs r3, r2, r3 8015c96: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 8015c98: 68fb ldr r3, [r7, #12] } 8015c9a: 4618 mov r0, r3 8015c9c: 3714 adds r7, #20 8015c9e: 46bd mov sp, r7 8015ca0: f85d 7b04 ldr.w r7, [sp], #4 8015ca4: 4770 bx lr 08015ca6 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8015ca6: b580 push {r7, lr} 8015ca8: b08e sub sp, #56 @ 0x38 8015caa: af04 add r7, sp, #16 8015cac: 60f8 str r0, [r7, #12] 8015cae: 60b9 str r1, [r7, #8] 8015cb0: 607a str r2, [r7, #4] 8015cb2: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8015cb4: 6b7b ldr r3, [r7, #52] @ 0x34 8015cb6: 2b00 cmp r3, #0 8015cb8: d10b bne.n 8015cd2 __asm volatile 8015cba: f04f 0350 mov.w r3, #80 @ 0x50 8015cbe: f383 8811 msr BASEPRI, r3 8015cc2: f3bf 8f6f isb sy 8015cc6: f3bf 8f4f dsb sy 8015cca: 623b str r3, [r7, #32] } 8015ccc: bf00 nop 8015cce: bf00 nop 8015cd0: e7fd b.n 8015cce configASSERT( pxTaskBuffer != NULL ); 8015cd2: 6bbb ldr r3, [r7, #56] @ 0x38 8015cd4: 2b00 cmp r3, #0 8015cd6: d10b bne.n 8015cf0 __asm volatile 8015cd8: f04f 0350 mov.w r3, #80 @ 0x50 8015cdc: f383 8811 msr BASEPRI, r3 8015ce0: f3bf 8f6f isb sy 8015ce4: f3bf 8f4f dsb sy 8015ce8: 61fb str r3, [r7, #28] } 8015cea: bf00 nop 8015cec: bf00 nop 8015cee: e7fd b.n 8015cec #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8015cf0: 23a8 movs r3, #168 @ 0xa8 8015cf2: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8015cf4: 693b ldr r3, [r7, #16] 8015cf6: 2ba8 cmp r3, #168 @ 0xa8 8015cf8: d00b beq.n 8015d12 __asm volatile 8015cfa: f04f 0350 mov.w r3, #80 @ 0x50 8015cfe: f383 8811 msr BASEPRI, r3 8015d02: f3bf 8f6f isb sy 8015d06: f3bf 8f4f dsb sy 8015d0a: 61bb str r3, [r7, #24] } 8015d0c: bf00 nop 8015d0e: bf00 nop 8015d10: e7fd b.n 8015d0e ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8015d12: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8015d14: 6bbb ldr r3, [r7, #56] @ 0x38 8015d16: 2b00 cmp r3, #0 8015d18: d01e beq.n 8015d58 8015d1a: 6b7b ldr r3, [r7, #52] @ 0x34 8015d1c: 2b00 cmp r3, #0 8015d1e: d01b beq.n 8015d58 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8015d20: 6bbb ldr r3, [r7, #56] @ 0x38 8015d22: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8015d24: 6a7b ldr r3, [r7, #36] @ 0x24 8015d26: 6b7a ldr r2, [r7, #52] @ 0x34 8015d28: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 8015d2a: 6a7b ldr r3, [r7, #36] @ 0x24 8015d2c: 2202 movs r2, #2 8015d2e: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8015d32: 2300 movs r3, #0 8015d34: 9303 str r3, [sp, #12] 8015d36: 6a7b ldr r3, [r7, #36] @ 0x24 8015d38: 9302 str r3, [sp, #8] 8015d3a: f107 0314 add.w r3, r7, #20 8015d3e: 9301 str r3, [sp, #4] 8015d40: 6b3b ldr r3, [r7, #48] @ 0x30 8015d42: 9300 str r3, [sp, #0] 8015d44: 683b ldr r3, [r7, #0] 8015d46: 687a ldr r2, [r7, #4] 8015d48: 68b9 ldr r1, [r7, #8] 8015d4a: 68f8 ldr r0, [r7, #12] 8015d4c: f000 f850 bl 8015df0 prvAddNewTaskToReadyList( pxNewTCB ); 8015d50: 6a78 ldr r0, [r7, #36] @ 0x24 8015d52: f000 f8f5 bl 8015f40 8015d56: e001 b.n 8015d5c } else { xReturn = NULL; 8015d58: 2300 movs r3, #0 8015d5a: 617b str r3, [r7, #20] } return xReturn; 8015d5c: 697b ldr r3, [r7, #20] } 8015d5e: 4618 mov r0, r3 8015d60: 3728 adds r7, #40 @ 0x28 8015d62: 46bd mov sp, r7 8015d64: bd80 pop {r7, pc} 08015d66 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8015d66: b580 push {r7, lr} 8015d68: b08c sub sp, #48 @ 0x30 8015d6a: af04 add r7, sp, #16 8015d6c: 60f8 str r0, [r7, #12] 8015d6e: 60b9 str r1, [r7, #8] 8015d70: 603b str r3, [r7, #0] 8015d72: 4613 mov r3, r2 8015d74: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8015d76: 88fb ldrh r3, [r7, #6] 8015d78: 009b lsls r3, r3, #2 8015d7a: 4618 mov r0, r3 8015d7c: f002 f8d6 bl 8017f2c 8015d80: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8015d82: 697b ldr r3, [r7, #20] 8015d84: 2b00 cmp r3, #0 8015d86: d00e beq.n 8015da6 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8015d88: 20a8 movs r0, #168 @ 0xa8 8015d8a: f002 f8cf bl 8017f2c 8015d8e: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8015d90: 69fb ldr r3, [r7, #28] 8015d92: 2b00 cmp r3, #0 8015d94: d003 beq.n 8015d9e { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8015d96: 69fb ldr r3, [r7, #28] 8015d98: 697a ldr r2, [r7, #20] 8015d9a: 631a str r2, [r3, #48] @ 0x30 8015d9c: e005 b.n 8015daa } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 8015d9e: 6978 ldr r0, [r7, #20] 8015da0: f002 f992 bl 80180c8 8015da4: e001 b.n 8015daa } } else { pxNewTCB = NULL; 8015da6: 2300 movs r3, #0 8015da8: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 8015daa: 69fb ldr r3, [r7, #28] 8015dac: 2b00 cmp r3, #0 8015dae: d017 beq.n 8015de0 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8015db0: 69fb ldr r3, [r7, #28] 8015db2: 2200 movs r2, #0 8015db4: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 8015db8: 88fa ldrh r2, [r7, #6] 8015dba: 2300 movs r3, #0 8015dbc: 9303 str r3, [sp, #12] 8015dbe: 69fb ldr r3, [r7, #28] 8015dc0: 9302 str r3, [sp, #8] 8015dc2: 6afb ldr r3, [r7, #44] @ 0x2c 8015dc4: 9301 str r3, [sp, #4] 8015dc6: 6abb ldr r3, [r7, #40] @ 0x28 8015dc8: 9300 str r3, [sp, #0] 8015dca: 683b ldr r3, [r7, #0] 8015dcc: 68b9 ldr r1, [r7, #8] 8015dce: 68f8 ldr r0, [r7, #12] 8015dd0: f000 f80e bl 8015df0 prvAddNewTaskToReadyList( pxNewTCB ); 8015dd4: 69f8 ldr r0, [r7, #28] 8015dd6: f000 f8b3 bl 8015f40 xReturn = pdPASS; 8015dda: 2301 movs r3, #1 8015ddc: 61bb str r3, [r7, #24] 8015dde: e002 b.n 8015de6 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8015de0: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015de4: 61bb str r3, [r7, #24] } return xReturn; 8015de6: 69bb ldr r3, [r7, #24] } 8015de8: 4618 mov r0, r3 8015dea: 3720 adds r7, #32 8015dec: 46bd mov sp, r7 8015dee: bd80 pop {r7, pc} 08015df0 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8015df0: b580 push {r7, lr} 8015df2: b088 sub sp, #32 8015df4: af00 add r7, sp, #0 8015df6: 60f8 str r0, [r7, #12] 8015df8: 60b9 str r1, [r7, #8] 8015dfa: 607a str r2, [r7, #4] 8015dfc: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 8015dfe: 6b3b ldr r3, [r7, #48] @ 0x30 8015e00: 6b18 ldr r0, [r3, #48] @ 0x30 8015e02: 687b ldr r3, [r7, #4] 8015e04: 009b lsls r3, r3, #2 8015e06: 461a mov r2, r3 8015e08: 21a5 movs r1, #165 @ 0xa5 8015e0a: f002 fa7d bl 8018308 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 8015e0e: 6b3b ldr r3, [r7, #48] @ 0x30 8015e10: 6b1a ldr r2, [r3, #48] @ 0x30 8015e12: 6879 ldr r1, [r7, #4] 8015e14: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 8015e18: 440b add r3, r1 8015e1a: 009b lsls r3, r3, #2 8015e1c: 4413 add r3, r2 8015e1e: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8015e20: 69bb ldr r3, [r7, #24] 8015e22: f023 0307 bic.w r3, r3, #7 8015e26: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8015e28: 69bb ldr r3, [r7, #24] 8015e2a: f003 0307 and.w r3, r3, #7 8015e2e: 2b00 cmp r3, #0 8015e30: d00b beq.n 8015e4a __asm volatile 8015e32: f04f 0350 mov.w r3, #80 @ 0x50 8015e36: f383 8811 msr BASEPRI, r3 8015e3a: f3bf 8f6f isb sy 8015e3e: f3bf 8f4f dsb sy 8015e42: 617b str r3, [r7, #20] } 8015e44: bf00 nop 8015e46: bf00 nop 8015e48: e7fd b.n 8015e46 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 8015e4a: 68bb ldr r3, [r7, #8] 8015e4c: 2b00 cmp r3, #0 8015e4e: d01f beq.n 8015e90 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015e50: 2300 movs r3, #0 8015e52: 61fb str r3, [r7, #28] 8015e54: e012 b.n 8015e7c { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8015e56: 68ba ldr r2, [r7, #8] 8015e58: 69fb ldr r3, [r7, #28] 8015e5a: 4413 add r3, r2 8015e5c: 7819 ldrb r1, [r3, #0] 8015e5e: 6b3a ldr r2, [r7, #48] @ 0x30 8015e60: 69fb ldr r3, [r7, #28] 8015e62: 4413 add r3, r2 8015e64: 3334 adds r3, #52 @ 0x34 8015e66: 460a mov r2, r1 8015e68: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 8015e6a: 68ba ldr r2, [r7, #8] 8015e6c: 69fb ldr r3, [r7, #28] 8015e6e: 4413 add r3, r2 8015e70: 781b ldrb r3, [r3, #0] 8015e72: 2b00 cmp r3, #0 8015e74: d006 beq.n 8015e84 for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015e76: 69fb ldr r3, [r7, #28] 8015e78: 3301 adds r3, #1 8015e7a: 61fb str r3, [r7, #28] 8015e7c: 69fb ldr r3, [r7, #28] 8015e7e: 2b0f cmp r3, #15 8015e80: d9e9 bls.n 8015e56 8015e82: e000 b.n 8015e86 { break; 8015e84: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 8015e86: 6b3b ldr r3, [r7, #48] @ 0x30 8015e88: 2200 movs r2, #0 8015e8a: f883 2043 strb.w r2, [r3, #67] @ 0x43 8015e8e: e003 b.n 8015e98 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 8015e90: 6b3b ldr r3, [r7, #48] @ 0x30 8015e92: 2200 movs r2, #0 8015e94: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8015e98: 6abb ldr r3, [r7, #40] @ 0x28 8015e9a: 2b37 cmp r3, #55 @ 0x37 8015e9c: d901 bls.n 8015ea2 { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8015e9e: 2337 movs r3, #55 @ 0x37 8015ea0: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 8015ea2: 6b3b ldr r3, [r7, #48] @ 0x30 8015ea4: 6aba ldr r2, [r7, #40] @ 0x28 8015ea6: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 8015ea8: 6b3b ldr r3, [r7, #48] @ 0x30 8015eaa: 6aba ldr r2, [r7, #40] @ 0x28 8015eac: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 8015eae: 6b3b ldr r3, [r7, #48] @ 0x30 8015eb0: 2200 movs r2, #0 8015eb2: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8015eb4: 6b3b ldr r3, [r7, #48] @ 0x30 8015eb6: 3304 adds r3, #4 8015eb8: 4618 mov r0, r3 8015eba: f7fe fd09 bl 80148d0 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8015ebe: 6b3b ldr r3, [r7, #48] @ 0x30 8015ec0: 3318 adds r3, #24 8015ec2: 4618 mov r0, r3 8015ec4: f7fe fd04 bl 80148d0 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 8015ec8: 6b3b ldr r3, [r7, #48] @ 0x30 8015eca: 6b3a ldr r2, [r7, #48] @ 0x30 8015ecc: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015ece: 6abb ldr r3, [r7, #40] @ 0x28 8015ed0: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015ed4: 6b3b ldr r3, [r7, #48] @ 0x30 8015ed6: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 8015ed8: 6b3b ldr r3, [r7, #48] @ 0x30 8015eda: 6b3a ldr r2, [r7, #48] @ 0x30 8015edc: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 8015ede: 6b3b ldr r3, [r7, #48] @ 0x30 8015ee0: 2200 movs r2, #0 8015ee2: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8015ee6: 6b3b ldr r3, [r7, #48] @ 0x30 8015ee8: 2200 movs r2, #0 8015eea: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 8015eee: 6b3b ldr r3, [r7, #48] @ 0x30 8015ef0: 3354 adds r3, #84 @ 0x54 8015ef2: 224c movs r2, #76 @ 0x4c 8015ef4: 2100 movs r1, #0 8015ef6: 4618 mov r0, r3 8015ef8: f002 fa06 bl 8018308 8015efc: 6b3b ldr r3, [r7, #48] @ 0x30 8015efe: 4a0d ldr r2, [pc, #52] @ (8015f34 ) 8015f00: 659a str r2, [r3, #88] @ 0x58 8015f02: 6b3b ldr r3, [r7, #48] @ 0x30 8015f04: 4a0c ldr r2, [pc, #48] @ (8015f38 ) 8015f06: 65da str r2, [r3, #92] @ 0x5c 8015f08: 6b3b ldr r3, [r7, #48] @ 0x30 8015f0a: 4a0c ldr r2, [pc, #48] @ (8015f3c ) 8015f0c: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 8015f0e: 683a ldr r2, [r7, #0] 8015f10: 68f9 ldr r1, [r7, #12] 8015f12: 69b8 ldr r0, [r7, #24] 8015f14: f001 fdb8 bl 8017a88 8015f18: 4602 mov r2, r0 8015f1a: 6b3b ldr r3, [r7, #48] @ 0x30 8015f1c: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 8015f1e: 6afb ldr r3, [r7, #44] @ 0x2c 8015f20: 2b00 cmp r3, #0 8015f22: d002 beq.n 8015f2a { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8015f24: 6afb ldr r3, [r7, #44] @ 0x2c 8015f26: 6b3a ldr r2, [r7, #48] @ 0x30 8015f28: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8015f2a: bf00 nop 8015f2c: 3720 adds r7, #32 8015f2e: 46bd mov sp, r7 8015f30: bd80 pop {r7, pc} 8015f32: bf00 nop 8015f34: 2401304c .word 0x2401304c 8015f38: 240130b4 .word 0x240130b4 8015f3c: 2401311c .word 0x2401311c 08015f40 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 8015f40: b580 push {r7, lr} 8015f42: b082 sub sp, #8 8015f44: af00 add r7, sp, #0 8015f46: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8015f48: f001 fece bl 8017ce8 { uxCurrentNumberOfTasks++; 8015f4c: 4b2d ldr r3, [pc, #180] @ (8016004 ) 8015f4e: 681b ldr r3, [r3, #0] 8015f50: 3301 adds r3, #1 8015f52: 4a2c ldr r2, [pc, #176] @ (8016004 ) 8015f54: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8015f56: 4b2c ldr r3, [pc, #176] @ (8016008 ) 8015f58: 681b ldr r3, [r3, #0] 8015f5a: 2b00 cmp r3, #0 8015f5c: d109 bne.n 8015f72 { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 8015f5e: 4a2a ldr r2, [pc, #168] @ (8016008 ) 8015f60: 687b ldr r3, [r7, #4] 8015f62: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8015f64: 4b27 ldr r3, [pc, #156] @ (8016004 ) 8015f66: 681b ldr r3, [r3, #0] 8015f68: 2b01 cmp r3, #1 8015f6a: d110 bne.n 8015f8e { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 8015f6c: f000 fc64 bl 8016838 8015f70: e00d b.n 8015f8e else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 8015f72: 4b26 ldr r3, [pc, #152] @ (801600c ) 8015f74: 681b ldr r3, [r3, #0] 8015f76: 2b00 cmp r3, #0 8015f78: d109 bne.n 8015f8e { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 8015f7a: 4b23 ldr r3, [pc, #140] @ (8016008 ) 8015f7c: 681b ldr r3, [r3, #0] 8015f7e: 6ada ldr r2, [r3, #44] @ 0x2c 8015f80: 687b ldr r3, [r7, #4] 8015f82: 6adb ldr r3, [r3, #44] @ 0x2c 8015f84: 429a cmp r2, r3 8015f86: d802 bhi.n 8015f8e { pxCurrentTCB = pxNewTCB; 8015f88: 4a1f ldr r2, [pc, #124] @ (8016008 ) 8015f8a: 687b ldr r3, [r7, #4] 8015f8c: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 8015f8e: 4b20 ldr r3, [pc, #128] @ (8016010 ) 8015f90: 681b ldr r3, [r3, #0] 8015f92: 3301 adds r3, #1 8015f94: 4a1e ldr r2, [pc, #120] @ (8016010 ) 8015f96: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 8015f98: 4b1d ldr r3, [pc, #116] @ (8016010 ) 8015f9a: 681a ldr r2, [r3, #0] 8015f9c: 687b ldr r3, [r7, #4] 8015f9e: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 8015fa0: 687b ldr r3, [r7, #4] 8015fa2: 6ada ldr r2, [r3, #44] @ 0x2c 8015fa4: 4b1b ldr r3, [pc, #108] @ (8016014 ) 8015fa6: 681b ldr r3, [r3, #0] 8015fa8: 429a cmp r2, r3 8015faa: d903 bls.n 8015fb4 8015fac: 687b ldr r3, [r7, #4] 8015fae: 6adb ldr r3, [r3, #44] @ 0x2c 8015fb0: 4a18 ldr r2, [pc, #96] @ (8016014 ) 8015fb2: 6013 str r3, [r2, #0] 8015fb4: 687b ldr r3, [r7, #4] 8015fb6: 6ada ldr r2, [r3, #44] @ 0x2c 8015fb8: 4613 mov r3, r2 8015fba: 009b lsls r3, r3, #2 8015fbc: 4413 add r3, r2 8015fbe: 009b lsls r3, r3, #2 8015fc0: 4a15 ldr r2, [pc, #84] @ (8016018 ) 8015fc2: 441a add r2, r3 8015fc4: 687b ldr r3, [r7, #4] 8015fc6: 3304 adds r3, #4 8015fc8: 4619 mov r1, r3 8015fca: 4610 mov r0, r2 8015fcc: f7fe fc8d bl 80148ea portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 8015fd0: f001 febc bl 8017d4c if( xSchedulerRunning != pdFALSE ) 8015fd4: 4b0d ldr r3, [pc, #52] @ (801600c ) 8015fd6: 681b ldr r3, [r3, #0] 8015fd8: 2b00 cmp r3, #0 8015fda: d00e beq.n 8015ffa { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8015fdc: 4b0a ldr r3, [pc, #40] @ (8016008 ) 8015fde: 681b ldr r3, [r3, #0] 8015fe0: 6ada ldr r2, [r3, #44] @ 0x2c 8015fe2: 687b ldr r3, [r7, #4] 8015fe4: 6adb ldr r3, [r3, #44] @ 0x2c 8015fe6: 429a cmp r2, r3 8015fe8: d207 bcs.n 8015ffa { taskYIELD_IF_USING_PREEMPTION(); 8015fea: 4b0c ldr r3, [pc, #48] @ (801601c ) 8015fec: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015ff0: 601a str r2, [r3, #0] 8015ff2: f3bf 8f4f dsb sy 8015ff6: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8015ffa: bf00 nop 8015ffc: 3708 adds r7, #8 8015ffe: 46bd mov sp, r7 8016000: bd80 pop {r7, pc} 8016002: bf00 nop 8016004: 24002ecc .word 0x24002ecc 8016008: 240029f8 .word 0x240029f8 801600c: 24002ed8 .word 0x24002ed8 8016010: 24002ee8 .word 0x24002ee8 8016014: 24002ed4 .word 0x24002ed4 8016018: 240029fc .word 0x240029fc 801601c: e000ed04 .word 0xe000ed04 08016020 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8016020: b580 push {r7, lr} 8016022: b084 sub sp, #16 8016024: af00 add r7, sp, #0 8016026: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 8016028: 2300 movs r3, #0 801602a: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 801602c: 687b ldr r3, [r7, #4] 801602e: 2b00 cmp r3, #0 8016030: d018 beq.n 8016064 { configASSERT( uxSchedulerSuspended == 0 ); 8016032: 4b14 ldr r3, [pc, #80] @ (8016084 ) 8016034: 681b ldr r3, [r3, #0] 8016036: 2b00 cmp r3, #0 8016038: d00b beq.n 8016052 __asm volatile 801603a: f04f 0350 mov.w r3, #80 @ 0x50 801603e: f383 8811 msr BASEPRI, r3 8016042: f3bf 8f6f isb sy 8016046: f3bf 8f4f dsb sy 801604a: 60bb str r3, [r7, #8] } 801604c: bf00 nop 801604e: bf00 nop 8016050: e7fd b.n 801604e vTaskSuspendAll(); 8016052: f000 f88b bl 801616c list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 8016056: 2100 movs r1, #0 8016058: 6878 ldr r0, [r7, #4] 801605a: f001 f87d bl 8017158 } xAlreadyYielded = xTaskResumeAll(); 801605e: f000 f893 bl 8016188 8016062: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 8016064: 68fb ldr r3, [r7, #12] 8016066: 2b00 cmp r3, #0 8016068: d107 bne.n 801607a { portYIELD_WITHIN_API(); 801606a: 4b07 ldr r3, [pc, #28] @ (8016088 ) 801606c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016070: 601a str r2, [r3, #0] 8016072: f3bf 8f4f dsb sy 8016076: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 801607a: bf00 nop 801607c: 3710 adds r7, #16 801607e: 46bd mov sp, r7 8016080: bd80 pop {r7, pc} 8016082: bf00 nop 8016084: 24002ef4 .word 0x24002ef4 8016088: e000ed04 .word 0xe000ed04 0801608c : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 801608c: b580 push {r7, lr} 801608e: b08a sub sp, #40 @ 0x28 8016090: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 8016092: 2300 movs r3, #0 8016094: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 8016096: 2300 movs r3, #0 8016098: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 801609a: 463a mov r2, r7 801609c: 1d39 adds r1, r7, #4 801609e: f107 0308 add.w r3, r7, #8 80160a2: 4618 mov r0, r3 80160a4: f7fe fbc0 bl 8014828 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 80160a8: 6839 ldr r1, [r7, #0] 80160aa: 687b ldr r3, [r7, #4] 80160ac: 68ba ldr r2, [r7, #8] 80160ae: 9202 str r2, [sp, #8] 80160b0: 9301 str r3, [sp, #4] 80160b2: 2300 movs r3, #0 80160b4: 9300 str r3, [sp, #0] 80160b6: 2300 movs r3, #0 80160b8: 460a mov r2, r1 80160ba: 4924 ldr r1, [pc, #144] @ (801614c ) 80160bc: 4824 ldr r0, [pc, #144] @ (8016150 ) 80160be: f7ff fdf2 bl 8015ca6 80160c2: 4603 mov r3, r0 80160c4: 4a23 ldr r2, [pc, #140] @ (8016154 ) 80160c6: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 80160c8: 4b22 ldr r3, [pc, #136] @ (8016154 ) 80160ca: 681b ldr r3, [r3, #0] 80160cc: 2b00 cmp r3, #0 80160ce: d002 beq.n 80160d6 { xReturn = pdPASS; 80160d0: 2301 movs r3, #1 80160d2: 617b str r3, [r7, #20] 80160d4: e001 b.n 80160da } else { xReturn = pdFAIL; 80160d6: 2300 movs r3, #0 80160d8: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 80160da: 697b ldr r3, [r7, #20] 80160dc: 2b01 cmp r3, #1 80160de: d102 bne.n 80160e6 { xReturn = xTimerCreateTimerTask(); 80160e0: f001 f88e bl 8017200 80160e4: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 80160e6: 697b ldr r3, [r7, #20] 80160e8: 2b01 cmp r3, #1 80160ea: d11b bne.n 8016124 __asm volatile 80160ec: f04f 0350 mov.w r3, #80 @ 0x50 80160f0: f383 8811 msr BASEPRI, r3 80160f4: f3bf 8f6f isb sy 80160f8: f3bf 8f4f dsb sy 80160fc: 613b str r3, [r7, #16] } 80160fe: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8016100: 4b15 ldr r3, [pc, #84] @ (8016158 ) 8016102: 681b ldr r3, [r3, #0] 8016104: 3354 adds r3, #84 @ 0x54 8016106: 4a15 ldr r2, [pc, #84] @ (801615c ) 8016108: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 801610a: 4b15 ldr r3, [pc, #84] @ (8016160 ) 801610c: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016110: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 8016112: 4b14 ldr r3, [pc, #80] @ (8016164 ) 8016114: 2201 movs r2, #1 8016116: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 8016118: 4b13 ldr r3, [pc, #76] @ (8016168 ) 801611a: 2200 movs r2, #0 801611c: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 801611e: f001 fd3f bl 8017ba0 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 8016122: e00f b.n 8016144 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 8016124: 697b ldr r3, [r7, #20] 8016126: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801612a: d10b bne.n 8016144 __asm volatile 801612c: f04f 0350 mov.w r3, #80 @ 0x50 8016130: f383 8811 msr BASEPRI, r3 8016134: f3bf 8f6f isb sy 8016138: f3bf 8f4f dsb sy 801613c: 60fb str r3, [r7, #12] } 801613e: bf00 nop 8016140: bf00 nop 8016142: e7fd b.n 8016140 } 8016144: bf00 nop 8016146: 3718 adds r7, #24 8016148: 46bd mov sp, r7 801614a: bd80 pop {r7, pc} 801614c: 08018680 .word 0x08018680 8016150: 08016809 .word 0x08016809 8016154: 24002ef0 .word 0x24002ef0 8016158: 240029f8 .word 0x240029f8 801615c: 24000048 .word 0x24000048 8016160: 24002eec .word 0x24002eec 8016164: 24002ed8 .word 0x24002ed8 8016168: 24002ed0 .word 0x24002ed0 0801616c : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 801616c: b480 push {r7} 801616e: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8016170: 4b04 ldr r3, [pc, #16] @ (8016184 ) 8016172: 681b ldr r3, [r3, #0] 8016174: 3301 adds r3, #1 8016176: 4a03 ldr r2, [pc, #12] @ (8016184 ) 8016178: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 801617a: bf00 nop 801617c: 46bd mov sp, r7 801617e: f85d 7b04 ldr.w r7, [sp], #4 8016182: 4770 bx lr 8016184: 24002ef4 .word 0x24002ef4 08016188 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 8016188: b580 push {r7, lr} 801618a: b084 sub sp, #16 801618c: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 801618e: 2300 movs r3, #0 8016190: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 8016192: 2300 movs r3, #0 8016194: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 8016196: 4b42 ldr r3, [pc, #264] @ (80162a0 ) 8016198: 681b ldr r3, [r3, #0] 801619a: 2b00 cmp r3, #0 801619c: d10b bne.n 80161b6 __asm volatile 801619e: f04f 0350 mov.w r3, #80 @ 0x50 80161a2: f383 8811 msr BASEPRI, r3 80161a6: f3bf 8f6f isb sy 80161aa: f3bf 8f4f dsb sy 80161ae: 603b str r3, [r7, #0] } 80161b0: bf00 nop 80161b2: bf00 nop 80161b4: e7fd b.n 80161b2 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 80161b6: f001 fd97 bl 8017ce8 { --uxSchedulerSuspended; 80161ba: 4b39 ldr r3, [pc, #228] @ (80162a0 ) 80161bc: 681b ldr r3, [r3, #0] 80161be: 3b01 subs r3, #1 80161c0: 4a37 ldr r2, [pc, #220] @ (80162a0 ) 80161c2: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80161c4: 4b36 ldr r3, [pc, #216] @ (80162a0 ) 80161c6: 681b ldr r3, [r3, #0] 80161c8: 2b00 cmp r3, #0 80161ca: d162 bne.n 8016292 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80161cc: 4b35 ldr r3, [pc, #212] @ (80162a4 ) 80161ce: 681b ldr r3, [r3, #0] 80161d0: 2b00 cmp r3, #0 80161d2: d05e beq.n 8016292 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80161d4: e02f b.n 8016236 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80161d6: 4b34 ldr r3, [pc, #208] @ (80162a8 ) 80161d8: 68db ldr r3, [r3, #12] 80161da: 68db ldr r3, [r3, #12] 80161dc: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80161de: 68fb ldr r3, [r7, #12] 80161e0: 3318 adds r3, #24 80161e2: 4618 mov r0, r3 80161e4: f7fe fbde bl 80149a4 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80161e8: 68fb ldr r3, [r7, #12] 80161ea: 3304 adds r3, #4 80161ec: 4618 mov r0, r3 80161ee: f7fe fbd9 bl 80149a4 prvAddTaskToReadyList( pxTCB ); 80161f2: 68fb ldr r3, [r7, #12] 80161f4: 6ada ldr r2, [r3, #44] @ 0x2c 80161f6: 4b2d ldr r3, [pc, #180] @ (80162ac ) 80161f8: 681b ldr r3, [r3, #0] 80161fa: 429a cmp r2, r3 80161fc: d903 bls.n 8016206 80161fe: 68fb ldr r3, [r7, #12] 8016200: 6adb ldr r3, [r3, #44] @ 0x2c 8016202: 4a2a ldr r2, [pc, #168] @ (80162ac ) 8016204: 6013 str r3, [r2, #0] 8016206: 68fb ldr r3, [r7, #12] 8016208: 6ada ldr r2, [r3, #44] @ 0x2c 801620a: 4613 mov r3, r2 801620c: 009b lsls r3, r3, #2 801620e: 4413 add r3, r2 8016210: 009b lsls r3, r3, #2 8016212: 4a27 ldr r2, [pc, #156] @ (80162b0 ) 8016214: 441a add r2, r3 8016216: 68fb ldr r3, [r7, #12] 8016218: 3304 adds r3, #4 801621a: 4619 mov r1, r3 801621c: 4610 mov r0, r2 801621e: f7fe fb64 bl 80148ea /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8016222: 68fb ldr r3, [r7, #12] 8016224: 6ada ldr r2, [r3, #44] @ 0x2c 8016226: 4b23 ldr r3, [pc, #140] @ (80162b4 ) 8016228: 681b ldr r3, [r3, #0] 801622a: 6adb ldr r3, [r3, #44] @ 0x2c 801622c: 429a cmp r2, r3 801622e: d302 bcc.n 8016236 { xYieldPending = pdTRUE; 8016230: 4b21 ldr r3, [pc, #132] @ (80162b8 ) 8016232: 2201 movs r2, #1 8016234: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8016236: 4b1c ldr r3, [pc, #112] @ (80162a8 ) 8016238: 681b ldr r3, [r3, #0] 801623a: 2b00 cmp r3, #0 801623c: d1cb bne.n 80161d6 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 801623e: 68fb ldr r3, [r7, #12] 8016240: 2b00 cmp r3, #0 8016242: d001 beq.n 8016248 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 8016244: f000 fb9c bl 8016980 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8016248: 4b1c ldr r3, [pc, #112] @ (80162bc ) 801624a: 681b ldr r3, [r3, #0] 801624c: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 801624e: 687b ldr r3, [r7, #4] 8016250: 2b00 cmp r3, #0 8016252: d010 beq.n 8016276 { do { if( xTaskIncrementTick() != pdFALSE ) 8016254: f000 f846 bl 80162e4 8016258: 4603 mov r3, r0 801625a: 2b00 cmp r3, #0 801625c: d002 beq.n 8016264 { xYieldPending = pdTRUE; 801625e: 4b16 ldr r3, [pc, #88] @ (80162b8 ) 8016260: 2201 movs r2, #1 8016262: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 8016264: 687b ldr r3, [r7, #4] 8016266: 3b01 subs r3, #1 8016268: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 801626a: 687b ldr r3, [r7, #4] 801626c: 2b00 cmp r3, #0 801626e: d1f1 bne.n 8016254 xPendedTicks = 0; 8016270: 4b12 ldr r3, [pc, #72] @ (80162bc ) 8016272: 2200 movs r2, #0 8016274: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8016276: 4b10 ldr r3, [pc, #64] @ (80162b8 ) 8016278: 681b ldr r3, [r3, #0] 801627a: 2b00 cmp r3, #0 801627c: d009 beq.n 8016292 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 801627e: 2301 movs r3, #1 8016280: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 8016282: 4b0f ldr r3, [pc, #60] @ (80162c0 ) 8016284: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016288: 601a str r2, [r3, #0] 801628a: f3bf 8f4f dsb sy 801628e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016292: f001 fd5b bl 8017d4c return xAlreadyYielded; 8016296: 68bb ldr r3, [r7, #8] } 8016298: 4618 mov r0, r3 801629a: 3710 adds r7, #16 801629c: 46bd mov sp, r7 801629e: bd80 pop {r7, pc} 80162a0: 24002ef4 .word 0x24002ef4 80162a4: 24002ecc .word 0x24002ecc 80162a8: 24002e8c .word 0x24002e8c 80162ac: 24002ed4 .word 0x24002ed4 80162b0: 240029fc .word 0x240029fc 80162b4: 240029f8 .word 0x240029f8 80162b8: 24002ee0 .word 0x24002ee0 80162bc: 24002edc .word 0x24002edc 80162c0: e000ed04 .word 0xe000ed04 080162c4 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 80162c4: b480 push {r7} 80162c6: b083 sub sp, #12 80162c8: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 80162ca: 4b05 ldr r3, [pc, #20] @ (80162e0 ) 80162cc: 681b ldr r3, [r3, #0] 80162ce: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 80162d0: 687b ldr r3, [r7, #4] } 80162d2: 4618 mov r0, r3 80162d4: 370c adds r7, #12 80162d6: 46bd mov sp, r7 80162d8: f85d 7b04 ldr.w r7, [sp], #4 80162dc: 4770 bx lr 80162de: bf00 nop 80162e0: 24002ed0 .word 0x24002ed0 080162e4 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 80162e4: b580 push {r7, lr} 80162e6: b086 sub sp, #24 80162e8: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 80162ea: 2300 movs r3, #0 80162ec: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80162ee: 4b4f ldr r3, [pc, #316] @ (801642c ) 80162f0: 681b ldr r3, [r3, #0] 80162f2: 2b00 cmp r3, #0 80162f4: f040 8090 bne.w 8016418 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 80162f8: 4b4d ldr r3, [pc, #308] @ (8016430 ) 80162fa: 681b ldr r3, [r3, #0] 80162fc: 3301 adds r3, #1 80162fe: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8016300: 4a4b ldr r2, [pc, #300] @ (8016430 ) 8016302: 693b ldr r3, [r7, #16] 8016304: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 8016306: 693b ldr r3, [r7, #16] 8016308: 2b00 cmp r3, #0 801630a: d121 bne.n 8016350 { taskSWITCH_DELAYED_LISTS(); 801630c: 4b49 ldr r3, [pc, #292] @ (8016434 ) 801630e: 681b ldr r3, [r3, #0] 8016310: 681b ldr r3, [r3, #0] 8016312: 2b00 cmp r3, #0 8016314: d00b beq.n 801632e __asm volatile 8016316: f04f 0350 mov.w r3, #80 @ 0x50 801631a: f383 8811 msr BASEPRI, r3 801631e: f3bf 8f6f isb sy 8016322: f3bf 8f4f dsb sy 8016326: 603b str r3, [r7, #0] } 8016328: bf00 nop 801632a: bf00 nop 801632c: e7fd b.n 801632a 801632e: 4b41 ldr r3, [pc, #260] @ (8016434 ) 8016330: 681b ldr r3, [r3, #0] 8016332: 60fb str r3, [r7, #12] 8016334: 4b40 ldr r3, [pc, #256] @ (8016438 ) 8016336: 681b ldr r3, [r3, #0] 8016338: 4a3e ldr r2, [pc, #248] @ (8016434 ) 801633a: 6013 str r3, [r2, #0] 801633c: 4a3e ldr r2, [pc, #248] @ (8016438 ) 801633e: 68fb ldr r3, [r7, #12] 8016340: 6013 str r3, [r2, #0] 8016342: 4b3e ldr r3, [pc, #248] @ (801643c ) 8016344: 681b ldr r3, [r3, #0] 8016346: 3301 adds r3, #1 8016348: 4a3c ldr r2, [pc, #240] @ (801643c ) 801634a: 6013 str r3, [r2, #0] 801634c: f000 fb18 bl 8016980 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8016350: 4b3b ldr r3, [pc, #236] @ (8016440 ) 8016352: 681b ldr r3, [r3, #0] 8016354: 693a ldr r2, [r7, #16] 8016356: 429a cmp r2, r3 8016358: d349 bcc.n 80163ee { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 801635a: 4b36 ldr r3, [pc, #216] @ (8016434 ) 801635c: 681b ldr r3, [r3, #0] 801635e: 681b ldr r3, [r3, #0] 8016360: 2b00 cmp r3, #0 8016362: d104 bne.n 801636e /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016364: 4b36 ldr r3, [pc, #216] @ (8016440 ) 8016366: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801636a: 601a str r2, [r3, #0] break; 801636c: e03f b.n 80163ee { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801636e: 4b31 ldr r3, [pc, #196] @ (8016434 ) 8016370: 681b ldr r3, [r3, #0] 8016372: 68db ldr r3, [r3, #12] 8016374: 68db ldr r3, [r3, #12] 8016376: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8016378: 68bb ldr r3, [r7, #8] 801637a: 685b ldr r3, [r3, #4] 801637c: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 801637e: 693a ldr r2, [r7, #16] 8016380: 687b ldr r3, [r7, #4] 8016382: 429a cmp r2, r3 8016384: d203 bcs.n 801638e /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 8016386: 4a2e ldr r2, [pc, #184] @ (8016440 ) 8016388: 687b ldr r3, [r7, #4] 801638a: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 801638c: e02f b.n 80163ee { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 801638e: 68bb ldr r3, [r7, #8] 8016390: 3304 adds r3, #4 8016392: 4618 mov r0, r3 8016394: f7fe fb06 bl 80149a4 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 8016398: 68bb ldr r3, [r7, #8] 801639a: 6a9b ldr r3, [r3, #40] @ 0x28 801639c: 2b00 cmp r3, #0 801639e: d004 beq.n 80163aa { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80163a0: 68bb ldr r3, [r7, #8] 80163a2: 3318 adds r3, #24 80163a4: 4618 mov r0, r3 80163a6: f7fe fafd bl 80149a4 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 80163aa: 68bb ldr r3, [r7, #8] 80163ac: 6ada ldr r2, [r3, #44] @ 0x2c 80163ae: 4b25 ldr r3, [pc, #148] @ (8016444 ) 80163b0: 681b ldr r3, [r3, #0] 80163b2: 429a cmp r2, r3 80163b4: d903 bls.n 80163be 80163b6: 68bb ldr r3, [r7, #8] 80163b8: 6adb ldr r3, [r3, #44] @ 0x2c 80163ba: 4a22 ldr r2, [pc, #136] @ (8016444 ) 80163bc: 6013 str r3, [r2, #0] 80163be: 68bb ldr r3, [r7, #8] 80163c0: 6ada ldr r2, [r3, #44] @ 0x2c 80163c2: 4613 mov r3, r2 80163c4: 009b lsls r3, r3, #2 80163c6: 4413 add r3, r2 80163c8: 009b lsls r3, r3, #2 80163ca: 4a1f ldr r2, [pc, #124] @ (8016448 ) 80163cc: 441a add r2, r3 80163ce: 68bb ldr r3, [r7, #8] 80163d0: 3304 adds r3, #4 80163d2: 4619 mov r1, r3 80163d4: 4610 mov r0, r2 80163d6: f7fe fa88 bl 80148ea { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80163da: 68bb ldr r3, [r7, #8] 80163dc: 6ada ldr r2, [r3, #44] @ 0x2c 80163de: 4b1b ldr r3, [pc, #108] @ (801644c ) 80163e0: 681b ldr r3, [r3, #0] 80163e2: 6adb ldr r3, [r3, #44] @ 0x2c 80163e4: 429a cmp r2, r3 80163e6: d3b8 bcc.n 801635a { xSwitchRequired = pdTRUE; 80163e8: 2301 movs r3, #1 80163ea: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80163ec: e7b5 b.n 801635a /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 80163ee: 4b17 ldr r3, [pc, #92] @ (801644c ) 80163f0: 681b ldr r3, [r3, #0] 80163f2: 6ada ldr r2, [r3, #44] @ 0x2c 80163f4: 4914 ldr r1, [pc, #80] @ (8016448 ) 80163f6: 4613 mov r3, r2 80163f8: 009b lsls r3, r3, #2 80163fa: 4413 add r3, r2 80163fc: 009b lsls r3, r3, #2 80163fe: 440b add r3, r1 8016400: 681b ldr r3, [r3, #0] 8016402: 2b01 cmp r3, #1 8016404: d901 bls.n 801640a { xSwitchRequired = pdTRUE; 8016406: 2301 movs r3, #1 8016408: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 801640a: 4b11 ldr r3, [pc, #68] @ (8016450 ) 801640c: 681b ldr r3, [r3, #0] 801640e: 2b00 cmp r3, #0 8016410: d007 beq.n 8016422 { xSwitchRequired = pdTRUE; 8016412: 2301 movs r3, #1 8016414: 617b str r3, [r7, #20] 8016416: e004 b.n 8016422 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 8016418: 4b0e ldr r3, [pc, #56] @ (8016454 ) 801641a: 681b ldr r3, [r3, #0] 801641c: 3301 adds r3, #1 801641e: 4a0d ldr r2, [pc, #52] @ (8016454 ) 8016420: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8016422: 697b ldr r3, [r7, #20] } 8016424: 4618 mov r0, r3 8016426: 3718 adds r7, #24 8016428: 46bd mov sp, r7 801642a: bd80 pop {r7, pc} 801642c: 24002ef4 .word 0x24002ef4 8016430: 24002ed0 .word 0x24002ed0 8016434: 24002e84 .word 0x24002e84 8016438: 24002e88 .word 0x24002e88 801643c: 24002ee4 .word 0x24002ee4 8016440: 24002eec .word 0x24002eec 8016444: 24002ed4 .word 0x24002ed4 8016448: 240029fc .word 0x240029fc 801644c: 240029f8 .word 0x240029f8 8016450: 24002ee0 .word 0x24002ee0 8016454: 24002edc .word 0x24002edc 08016458 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 8016458: b580 push {r7, lr} 801645a: b084 sub sp, #16 801645c: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 801645e: 4b32 ldr r3, [pc, #200] @ (8016528 ) 8016460: 681b ldr r3, [r3, #0] 8016462: 2b00 cmp r3, #0 8016464: d003 beq.n 801646e { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 8016466: 4b31 ldr r3, [pc, #196] @ (801652c ) 8016468: 2201 movs r2, #1 801646a: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 801646c: e058 b.n 8016520 xYieldPending = pdFALSE; 801646e: 4b2f ldr r3, [pc, #188] @ (801652c ) 8016470: 2200 movs r2, #0 8016472: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 8016474: 4b2e ldr r3, [pc, #184] @ (8016530 ) 8016476: 681b ldr r3, [r3, #0] 8016478: 681a ldr r2, [r3, #0] 801647a: 4b2d ldr r3, [pc, #180] @ (8016530 ) 801647c: 681b ldr r3, [r3, #0] 801647e: 6b1b ldr r3, [r3, #48] @ 0x30 8016480: 429a cmp r2, r3 8016482: d808 bhi.n 8016496 8016484: 4b2a ldr r3, [pc, #168] @ (8016530 ) 8016486: 681a ldr r2, [r3, #0] 8016488: 4b29 ldr r3, [pc, #164] @ (8016530 ) 801648a: 681b ldr r3, [r3, #0] 801648c: 3334 adds r3, #52 @ 0x34 801648e: 4619 mov r1, r3 8016490: 4610 mov r0, r2 8016492: f7ea f89d bl 80005d0 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016496: 4b27 ldr r3, [pc, #156] @ (8016534 ) 8016498: 681b ldr r3, [r3, #0] 801649a: 60fb str r3, [r7, #12] 801649c: e011 b.n 80164c2 801649e: 68fb ldr r3, [r7, #12] 80164a0: 2b00 cmp r3, #0 80164a2: d10b bne.n 80164bc __asm volatile 80164a4: f04f 0350 mov.w r3, #80 @ 0x50 80164a8: f383 8811 msr BASEPRI, r3 80164ac: f3bf 8f6f isb sy 80164b0: f3bf 8f4f dsb sy 80164b4: 607b str r3, [r7, #4] } 80164b6: bf00 nop 80164b8: bf00 nop 80164ba: e7fd b.n 80164b8 80164bc: 68fb ldr r3, [r7, #12] 80164be: 3b01 subs r3, #1 80164c0: 60fb str r3, [r7, #12] 80164c2: 491d ldr r1, [pc, #116] @ (8016538 ) 80164c4: 68fa ldr r2, [r7, #12] 80164c6: 4613 mov r3, r2 80164c8: 009b lsls r3, r3, #2 80164ca: 4413 add r3, r2 80164cc: 009b lsls r3, r3, #2 80164ce: 440b add r3, r1 80164d0: 681b ldr r3, [r3, #0] 80164d2: 2b00 cmp r3, #0 80164d4: d0e3 beq.n 801649e 80164d6: 68fa ldr r2, [r7, #12] 80164d8: 4613 mov r3, r2 80164da: 009b lsls r3, r3, #2 80164dc: 4413 add r3, r2 80164de: 009b lsls r3, r3, #2 80164e0: 4a15 ldr r2, [pc, #84] @ (8016538 ) 80164e2: 4413 add r3, r2 80164e4: 60bb str r3, [r7, #8] 80164e6: 68bb ldr r3, [r7, #8] 80164e8: 685b ldr r3, [r3, #4] 80164ea: 685a ldr r2, [r3, #4] 80164ec: 68bb ldr r3, [r7, #8] 80164ee: 605a str r2, [r3, #4] 80164f0: 68bb ldr r3, [r7, #8] 80164f2: 685a ldr r2, [r3, #4] 80164f4: 68bb ldr r3, [r7, #8] 80164f6: 3308 adds r3, #8 80164f8: 429a cmp r2, r3 80164fa: d104 bne.n 8016506 80164fc: 68bb ldr r3, [r7, #8] 80164fe: 685b ldr r3, [r3, #4] 8016500: 685a ldr r2, [r3, #4] 8016502: 68bb ldr r3, [r7, #8] 8016504: 605a str r2, [r3, #4] 8016506: 68bb ldr r3, [r7, #8] 8016508: 685b ldr r3, [r3, #4] 801650a: 68db ldr r3, [r3, #12] 801650c: 4a08 ldr r2, [pc, #32] @ (8016530 ) 801650e: 6013 str r3, [r2, #0] 8016510: 4a08 ldr r2, [pc, #32] @ (8016534 ) 8016512: 68fb ldr r3, [r7, #12] 8016514: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8016516: 4b06 ldr r3, [pc, #24] @ (8016530 ) 8016518: 681b ldr r3, [r3, #0] 801651a: 3354 adds r3, #84 @ 0x54 801651c: 4a07 ldr r2, [pc, #28] @ (801653c ) 801651e: 6013 str r3, [r2, #0] } 8016520: bf00 nop 8016522: 3710 adds r7, #16 8016524: 46bd mov sp, r7 8016526: bd80 pop {r7, pc} 8016528: 24002ef4 .word 0x24002ef4 801652c: 24002ee0 .word 0x24002ee0 8016530: 240029f8 .word 0x240029f8 8016534: 24002ed4 .word 0x24002ed4 8016538: 240029fc .word 0x240029fc 801653c: 24000048 .word 0x24000048 08016540 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8016540: b580 push {r7, lr} 8016542: b084 sub sp, #16 8016544: af00 add r7, sp, #0 8016546: 6078 str r0, [r7, #4] 8016548: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 801654a: 687b ldr r3, [r7, #4] 801654c: 2b00 cmp r3, #0 801654e: d10b bne.n 8016568 __asm volatile 8016550: f04f 0350 mov.w r3, #80 @ 0x50 8016554: f383 8811 msr BASEPRI, r3 8016558: f3bf 8f6f isb sy 801655c: f3bf 8f4f dsb sy 8016560: 60fb str r3, [r7, #12] } 8016562: bf00 nop 8016564: bf00 nop 8016566: e7fd b.n 8016564 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8016568: 4b07 ldr r3, [pc, #28] @ (8016588 ) 801656a: 681b ldr r3, [r3, #0] 801656c: 3318 adds r3, #24 801656e: 4619 mov r1, r3 8016570: 6878 ldr r0, [r7, #4] 8016572: f7fe f9de bl 8014932 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016576: 2101 movs r1, #1 8016578: 6838 ldr r0, [r7, #0] 801657a: f000 fded bl 8017158 } 801657e: bf00 nop 8016580: 3710 adds r7, #16 8016582: 46bd mov sp, r7 8016584: bd80 pop {r7, pc} 8016586: bf00 nop 8016588: 240029f8 .word 0x240029f8 0801658c : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 801658c: b580 push {r7, lr} 801658e: b086 sub sp, #24 8016590: af00 add r7, sp, #0 8016592: 60f8 str r0, [r7, #12] 8016594: 60b9 str r1, [r7, #8] 8016596: 607a str r2, [r7, #4] configASSERT( pxEventList ); 8016598: 68fb ldr r3, [r7, #12] 801659a: 2b00 cmp r3, #0 801659c: d10b bne.n 80165b6 __asm volatile 801659e: f04f 0350 mov.w r3, #80 @ 0x50 80165a2: f383 8811 msr BASEPRI, r3 80165a6: f3bf 8f6f isb sy 80165aa: f3bf 8f4f dsb sy 80165ae: 617b str r3, [r7, #20] } 80165b0: bf00 nop 80165b2: bf00 nop 80165b4: e7fd b.n 80165b2 /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80165b6: 4b0a ldr r3, [pc, #40] @ (80165e0 ) 80165b8: 681b ldr r3, [r3, #0] 80165ba: 3318 adds r3, #24 80165bc: 4619 mov r1, r3 80165be: 68f8 ldr r0, [r7, #12] 80165c0: f7fe f993 bl 80148ea /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 80165c4: 687b ldr r3, [r7, #4] 80165c6: 2b00 cmp r3, #0 80165c8: d002 beq.n 80165d0 { xTicksToWait = portMAX_DELAY; 80165ca: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80165ce: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 80165d0: 6879 ldr r1, [r7, #4] 80165d2: 68b8 ldr r0, [r7, #8] 80165d4: f000 fdc0 bl 8017158 } 80165d8: bf00 nop 80165da: 3718 adds r7, #24 80165dc: 46bd mov sp, r7 80165de: bd80 pop {r7, pc} 80165e0: 240029f8 .word 0x240029f8 080165e4 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 80165e4: b580 push {r7, lr} 80165e6: b086 sub sp, #24 80165e8: af00 add r7, sp, #0 80165ea: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80165ec: 687b ldr r3, [r7, #4] 80165ee: 68db ldr r3, [r3, #12] 80165f0: 68db ldr r3, [r3, #12] 80165f2: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 80165f4: 693b ldr r3, [r7, #16] 80165f6: 2b00 cmp r3, #0 80165f8: d10b bne.n 8016612 __asm volatile 80165fa: f04f 0350 mov.w r3, #80 @ 0x50 80165fe: f383 8811 msr BASEPRI, r3 8016602: f3bf 8f6f isb sy 8016606: f3bf 8f4f dsb sy 801660a: 60fb str r3, [r7, #12] } 801660c: bf00 nop 801660e: bf00 nop 8016610: e7fd b.n 801660e ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 8016612: 693b ldr r3, [r7, #16] 8016614: 3318 adds r3, #24 8016616: 4618 mov r0, r3 8016618: f7fe f9c4 bl 80149a4 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801661c: 4b1d ldr r3, [pc, #116] @ (8016694 ) 801661e: 681b ldr r3, [r3, #0] 8016620: 2b00 cmp r3, #0 8016622: d11d bne.n 8016660 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 8016624: 693b ldr r3, [r7, #16] 8016626: 3304 adds r3, #4 8016628: 4618 mov r0, r3 801662a: f7fe f9bb bl 80149a4 prvAddTaskToReadyList( pxUnblockedTCB ); 801662e: 693b ldr r3, [r7, #16] 8016630: 6ada ldr r2, [r3, #44] @ 0x2c 8016632: 4b19 ldr r3, [pc, #100] @ (8016698 ) 8016634: 681b ldr r3, [r3, #0] 8016636: 429a cmp r2, r3 8016638: d903 bls.n 8016642 801663a: 693b ldr r3, [r7, #16] 801663c: 6adb ldr r3, [r3, #44] @ 0x2c 801663e: 4a16 ldr r2, [pc, #88] @ (8016698 ) 8016640: 6013 str r3, [r2, #0] 8016642: 693b ldr r3, [r7, #16] 8016644: 6ada ldr r2, [r3, #44] @ 0x2c 8016646: 4613 mov r3, r2 8016648: 009b lsls r3, r3, #2 801664a: 4413 add r3, r2 801664c: 009b lsls r3, r3, #2 801664e: 4a13 ldr r2, [pc, #76] @ (801669c ) 8016650: 441a add r2, r3 8016652: 693b ldr r3, [r7, #16] 8016654: 3304 adds r3, #4 8016656: 4619 mov r1, r3 8016658: 4610 mov r0, r2 801665a: f7fe f946 bl 80148ea 801665e: e005 b.n 801666c } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8016660: 693b ldr r3, [r7, #16] 8016662: 3318 adds r3, #24 8016664: 4619 mov r1, r3 8016666: 480e ldr r0, [pc, #56] @ (80166a0 ) 8016668: f7fe f93f bl 80148ea } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 801666c: 693b ldr r3, [r7, #16] 801666e: 6ada ldr r2, [r3, #44] @ 0x2c 8016670: 4b0c ldr r3, [pc, #48] @ (80166a4 ) 8016672: 681b ldr r3, [r3, #0] 8016674: 6adb ldr r3, [r3, #44] @ 0x2c 8016676: 429a cmp r2, r3 8016678: d905 bls.n 8016686 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 801667a: 2301 movs r3, #1 801667c: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 801667e: 4b0a ldr r3, [pc, #40] @ (80166a8 ) 8016680: 2201 movs r2, #1 8016682: 601a str r2, [r3, #0] 8016684: e001 b.n 801668a } else { xReturn = pdFALSE; 8016686: 2300 movs r3, #0 8016688: 617b str r3, [r7, #20] } return xReturn; 801668a: 697b ldr r3, [r7, #20] } 801668c: 4618 mov r0, r3 801668e: 3718 adds r7, #24 8016690: 46bd mov sp, r7 8016692: bd80 pop {r7, pc} 8016694: 24002ef4 .word 0x24002ef4 8016698: 24002ed4 .word 0x24002ed4 801669c: 240029fc .word 0x240029fc 80166a0: 24002e8c .word 0x24002e8c 80166a4: 240029f8 .word 0x240029f8 80166a8: 24002ee0 .word 0x24002ee0 080166ac : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 80166ac: b580 push {r7, lr} 80166ae: b084 sub sp, #16 80166b0: af00 add r7, sp, #0 80166b2: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 80166b4: 687b ldr r3, [r7, #4] 80166b6: 2b00 cmp r3, #0 80166b8: d10b bne.n 80166d2 __asm volatile 80166ba: f04f 0350 mov.w r3, #80 @ 0x50 80166be: f383 8811 msr BASEPRI, r3 80166c2: f3bf 8f6f isb sy 80166c6: f3bf 8f4f dsb sy 80166ca: 60fb str r3, [r7, #12] } 80166cc: bf00 nop 80166ce: bf00 nop 80166d0: e7fd b.n 80166ce taskENTER_CRITICAL(); 80166d2: f001 fb09 bl 8017ce8 { pxTimeOut->xOverflowCount = xNumOfOverflows; 80166d6: 4b07 ldr r3, [pc, #28] @ (80166f4 ) 80166d8: 681a ldr r2, [r3, #0] 80166da: 687b ldr r3, [r7, #4] 80166dc: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 80166de: 4b06 ldr r3, [pc, #24] @ (80166f8 ) 80166e0: 681a ldr r2, [r3, #0] 80166e2: 687b ldr r3, [r7, #4] 80166e4: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 80166e6: f001 fb31 bl 8017d4c } 80166ea: bf00 nop 80166ec: 3710 adds r7, #16 80166ee: 46bd mov sp, r7 80166f0: bd80 pop {r7, pc} 80166f2: bf00 nop 80166f4: 24002ee4 .word 0x24002ee4 80166f8: 24002ed0 .word 0x24002ed0 080166fc : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 80166fc: b480 push {r7} 80166fe: b083 sub sp, #12 8016700: af00 add r7, sp, #0 8016702: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 8016704: 4b06 ldr r3, [pc, #24] @ (8016720 ) 8016706: 681a ldr r2, [r3, #0] 8016708: 687b ldr r3, [r7, #4] 801670a: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 801670c: 4b05 ldr r3, [pc, #20] @ (8016724 ) 801670e: 681a ldr r2, [r3, #0] 8016710: 687b ldr r3, [r7, #4] 8016712: 605a str r2, [r3, #4] } 8016714: bf00 nop 8016716: 370c adds r7, #12 8016718: 46bd mov sp, r7 801671a: f85d 7b04 ldr.w r7, [sp], #4 801671e: 4770 bx lr 8016720: 24002ee4 .word 0x24002ee4 8016724: 24002ed0 .word 0x24002ed0 08016728 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8016728: b580 push {r7, lr} 801672a: b088 sub sp, #32 801672c: af00 add r7, sp, #0 801672e: 6078 str r0, [r7, #4] 8016730: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 8016732: 687b ldr r3, [r7, #4] 8016734: 2b00 cmp r3, #0 8016736: d10b bne.n 8016750 __asm volatile 8016738: f04f 0350 mov.w r3, #80 @ 0x50 801673c: f383 8811 msr BASEPRI, r3 8016740: f3bf 8f6f isb sy 8016744: f3bf 8f4f dsb sy 8016748: 613b str r3, [r7, #16] } 801674a: bf00 nop 801674c: bf00 nop 801674e: e7fd b.n 801674c configASSERT( pxTicksToWait ); 8016750: 683b ldr r3, [r7, #0] 8016752: 2b00 cmp r3, #0 8016754: d10b bne.n 801676e __asm volatile 8016756: f04f 0350 mov.w r3, #80 @ 0x50 801675a: f383 8811 msr BASEPRI, r3 801675e: f3bf 8f6f isb sy 8016762: f3bf 8f4f dsb sy 8016766: 60fb str r3, [r7, #12] } 8016768: bf00 nop 801676a: bf00 nop 801676c: e7fd b.n 801676a taskENTER_CRITICAL(); 801676e: f001 fabb bl 8017ce8 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 8016772: 4b1d ldr r3, [pc, #116] @ (80167e8 ) 8016774: 681b ldr r3, [r3, #0] 8016776: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8016778: 687b ldr r3, [r7, #4] 801677a: 685b ldr r3, [r3, #4] 801677c: 69ba ldr r2, [r7, #24] 801677e: 1ad3 subs r3, r2, r3 8016780: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 8016782: 683b ldr r3, [r7, #0] 8016784: 681b ldr r3, [r3, #0] 8016786: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801678a: d102 bne.n 8016792 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 801678c: 2300 movs r3, #0 801678e: 61fb str r3, [r7, #28] 8016790: e023 b.n 80167da } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 8016792: 687b ldr r3, [r7, #4] 8016794: 681a ldr r2, [r3, #0] 8016796: 4b15 ldr r3, [pc, #84] @ (80167ec ) 8016798: 681b ldr r3, [r3, #0] 801679a: 429a cmp r2, r3 801679c: d007 beq.n 80167ae 801679e: 687b ldr r3, [r7, #4] 80167a0: 685b ldr r3, [r3, #4] 80167a2: 69ba ldr r2, [r7, #24] 80167a4: 429a cmp r2, r3 80167a6: d302 bcc.n 80167ae /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 80167a8: 2301 movs r3, #1 80167aa: 61fb str r3, [r7, #28] 80167ac: e015 b.n 80167da } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 80167ae: 683b ldr r3, [r7, #0] 80167b0: 681b ldr r3, [r3, #0] 80167b2: 697a ldr r2, [r7, #20] 80167b4: 429a cmp r2, r3 80167b6: d20b bcs.n 80167d0 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 80167b8: 683b ldr r3, [r7, #0] 80167ba: 681a ldr r2, [r3, #0] 80167bc: 697b ldr r3, [r7, #20] 80167be: 1ad2 subs r2, r2, r3 80167c0: 683b ldr r3, [r7, #0] 80167c2: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 80167c4: 6878 ldr r0, [r7, #4] 80167c6: f7ff ff99 bl 80166fc xReturn = pdFALSE; 80167ca: 2300 movs r3, #0 80167cc: 61fb str r3, [r7, #28] 80167ce: e004 b.n 80167da } else { *pxTicksToWait = 0; 80167d0: 683b ldr r3, [r7, #0] 80167d2: 2200 movs r2, #0 80167d4: 601a str r2, [r3, #0] xReturn = pdTRUE; 80167d6: 2301 movs r3, #1 80167d8: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 80167da: f001 fab7 bl 8017d4c return xReturn; 80167de: 69fb ldr r3, [r7, #28] } 80167e0: 4618 mov r0, r3 80167e2: 3720 adds r7, #32 80167e4: 46bd mov sp, r7 80167e6: bd80 pop {r7, pc} 80167e8: 24002ed0 .word 0x24002ed0 80167ec: 24002ee4 .word 0x24002ee4 080167f0 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 80167f0: b480 push {r7} 80167f2: af00 add r7, sp, #0 xYieldPending = pdTRUE; 80167f4: 4b03 ldr r3, [pc, #12] @ (8016804 ) 80167f6: 2201 movs r2, #1 80167f8: 601a str r2, [r3, #0] } 80167fa: bf00 nop 80167fc: 46bd mov sp, r7 80167fe: f85d 7b04 ldr.w r7, [sp], #4 8016802: 4770 bx lr 8016804: 24002ee0 .word 0x24002ee0 08016808 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8016808: b580 push {r7, lr} 801680a: b082 sub sp, #8 801680c: af00 add r7, sp, #0 801680e: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8016810: f000 f852 bl 80168b8 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 8016814: 4b06 ldr r3, [pc, #24] @ (8016830 ) 8016816: 681b ldr r3, [r3, #0] 8016818: 2b01 cmp r3, #1 801681a: d9f9 bls.n 8016810 { taskYIELD(); 801681c: 4b05 ldr r3, [pc, #20] @ (8016834 ) 801681e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016822: 601a str r2, [r3, #0] 8016824: f3bf 8f4f dsb sy 8016828: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 801682c: e7f0 b.n 8016810 801682e: bf00 nop 8016830: 240029fc .word 0x240029fc 8016834: e000ed04 .word 0xe000ed04 08016838 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8016838: b580 push {r7, lr} 801683a: b082 sub sp, #8 801683c: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 801683e: 2300 movs r3, #0 8016840: 607b str r3, [r7, #4] 8016842: e00c b.n 801685e { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 8016844: 687a ldr r2, [r7, #4] 8016846: 4613 mov r3, r2 8016848: 009b lsls r3, r3, #2 801684a: 4413 add r3, r2 801684c: 009b lsls r3, r3, #2 801684e: 4a12 ldr r2, [pc, #72] @ (8016898 ) 8016850: 4413 add r3, r2 8016852: 4618 mov r0, r3 8016854: f7fe f81c bl 8014890 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8016858: 687b ldr r3, [r7, #4] 801685a: 3301 adds r3, #1 801685c: 607b str r3, [r7, #4] 801685e: 687b ldr r3, [r7, #4] 8016860: 2b37 cmp r3, #55 @ 0x37 8016862: d9ef bls.n 8016844 } vListInitialise( &xDelayedTaskList1 ); 8016864: 480d ldr r0, [pc, #52] @ (801689c ) 8016866: f7fe f813 bl 8014890 vListInitialise( &xDelayedTaskList2 ); 801686a: 480d ldr r0, [pc, #52] @ (80168a0 ) 801686c: f7fe f810 bl 8014890 vListInitialise( &xPendingReadyList ); 8016870: 480c ldr r0, [pc, #48] @ (80168a4 ) 8016872: f7fe f80d bl 8014890 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 8016876: 480c ldr r0, [pc, #48] @ (80168a8 ) 8016878: f7fe f80a bl 8014890 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 801687c: 480b ldr r0, [pc, #44] @ (80168ac ) 801687e: f7fe f807 bl 8014890 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 8016882: 4b0b ldr r3, [pc, #44] @ (80168b0 ) 8016884: 4a05 ldr r2, [pc, #20] @ (801689c ) 8016886: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8016888: 4b0a ldr r3, [pc, #40] @ (80168b4 ) 801688a: 4a05 ldr r2, [pc, #20] @ (80168a0 ) 801688c: 601a str r2, [r3, #0] } 801688e: bf00 nop 8016890: 3708 adds r7, #8 8016892: 46bd mov sp, r7 8016894: bd80 pop {r7, pc} 8016896: bf00 nop 8016898: 240029fc .word 0x240029fc 801689c: 24002e5c .word 0x24002e5c 80168a0: 24002e70 .word 0x24002e70 80168a4: 24002e8c .word 0x24002e8c 80168a8: 24002ea0 .word 0x24002ea0 80168ac: 24002eb8 .word 0x24002eb8 80168b0: 24002e84 .word 0x24002e84 80168b4: 24002e88 .word 0x24002e88 080168b8 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 80168b8: b580 push {r7, lr} 80168ba: b082 sub sp, #8 80168bc: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 80168be: e019 b.n 80168f4 { taskENTER_CRITICAL(); 80168c0: f001 fa12 bl 8017ce8 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80168c4: 4b10 ldr r3, [pc, #64] @ (8016908 ) 80168c6: 68db ldr r3, [r3, #12] 80168c8: 68db ldr r3, [r3, #12] 80168ca: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80168cc: 687b ldr r3, [r7, #4] 80168ce: 3304 adds r3, #4 80168d0: 4618 mov r0, r3 80168d2: f7fe f867 bl 80149a4 --uxCurrentNumberOfTasks; 80168d6: 4b0d ldr r3, [pc, #52] @ (801690c ) 80168d8: 681b ldr r3, [r3, #0] 80168da: 3b01 subs r3, #1 80168dc: 4a0b ldr r2, [pc, #44] @ (801690c ) 80168de: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 80168e0: 4b0b ldr r3, [pc, #44] @ (8016910 ) 80168e2: 681b ldr r3, [r3, #0] 80168e4: 3b01 subs r3, #1 80168e6: 4a0a ldr r2, [pc, #40] @ (8016910 ) 80168e8: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 80168ea: f001 fa2f bl 8017d4c prvDeleteTCB( pxTCB ); 80168ee: 6878 ldr r0, [r7, #4] 80168f0: f000 f810 bl 8016914 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 80168f4: 4b06 ldr r3, [pc, #24] @ (8016910 ) 80168f6: 681b ldr r3, [r3, #0] 80168f8: 2b00 cmp r3, #0 80168fa: d1e1 bne.n 80168c0 } } #endif /* INCLUDE_vTaskDelete */ } 80168fc: bf00 nop 80168fe: bf00 nop 8016900: 3708 adds r7, #8 8016902: 46bd mov sp, r7 8016904: bd80 pop {r7, pc} 8016906: bf00 nop 8016908: 24002ea0 .word 0x24002ea0 801690c: 24002ecc .word 0x24002ecc 8016910: 24002eb4 .word 0x24002eb4 08016914 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 8016914: b580 push {r7, lr} 8016916: b084 sub sp, #16 8016918: af00 add r7, sp, #0 801691a: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 801691c: 687b ldr r3, [r7, #4] 801691e: 3354 adds r3, #84 @ 0x54 8016920: 4618 mov r0, r3 8016922: f001 fcf9 bl 8018318 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 8016926: 687b ldr r3, [r7, #4] 8016928: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 801692c: 2b00 cmp r3, #0 801692e: d108 bne.n 8016942 { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 8016930: 687b ldr r3, [r7, #4] 8016932: 6b1b ldr r3, [r3, #48] @ 0x30 8016934: 4618 mov r0, r3 8016936: f001 fbc7 bl 80180c8 vPortFree( pxTCB ); 801693a: 6878 ldr r0, [r7, #4] 801693c: f001 fbc4 bl 80180c8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8016940: e019 b.n 8016976 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 8016942: 687b ldr r3, [r7, #4] 8016944: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8016948: 2b01 cmp r3, #1 801694a: d103 bne.n 8016954 vPortFree( pxTCB ); 801694c: 6878 ldr r0, [r7, #4] 801694e: f001 fbbb bl 80180c8 } 8016952: e010 b.n 8016976 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 8016954: 687b ldr r3, [r7, #4] 8016956: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 801695a: 2b02 cmp r3, #2 801695c: d00b beq.n 8016976 __asm volatile 801695e: f04f 0350 mov.w r3, #80 @ 0x50 8016962: f383 8811 msr BASEPRI, r3 8016966: f3bf 8f6f isb sy 801696a: f3bf 8f4f dsb sy 801696e: 60fb str r3, [r7, #12] } 8016970: bf00 nop 8016972: bf00 nop 8016974: e7fd b.n 8016972 } 8016976: bf00 nop 8016978: 3710 adds r7, #16 801697a: 46bd mov sp, r7 801697c: bd80 pop {r7, pc} ... 08016980 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8016980: b480 push {r7} 8016982: b083 sub sp, #12 8016984: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8016986: 4b0c ldr r3, [pc, #48] @ (80169b8 ) 8016988: 681b ldr r3, [r3, #0] 801698a: 681b ldr r3, [r3, #0] 801698c: 2b00 cmp r3, #0 801698e: d104 bne.n 801699a { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8016990: 4b0a ldr r3, [pc, #40] @ (80169bc ) 8016992: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016996: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8016998: e008 b.n 80169ac ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801699a: 4b07 ldr r3, [pc, #28] @ (80169b8 ) 801699c: 681b ldr r3, [r3, #0] 801699e: 68db ldr r3, [r3, #12] 80169a0: 68db ldr r3, [r3, #12] 80169a2: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 80169a4: 687b ldr r3, [r7, #4] 80169a6: 685b ldr r3, [r3, #4] 80169a8: 4a04 ldr r2, [pc, #16] @ (80169bc ) 80169aa: 6013 str r3, [r2, #0] } 80169ac: bf00 nop 80169ae: 370c adds r7, #12 80169b0: 46bd mov sp, r7 80169b2: f85d 7b04 ldr.w r7, [sp], #4 80169b6: 4770 bx lr 80169b8: 24002e84 .word 0x24002e84 80169bc: 24002eec .word 0x24002eec 080169c0 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 80169c0: b480 push {r7} 80169c2: b083 sub sp, #12 80169c4: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 80169c6: 4b05 ldr r3, [pc, #20] @ (80169dc ) 80169c8: 681b ldr r3, [r3, #0] 80169ca: 607b str r3, [r7, #4] return xReturn; 80169cc: 687b ldr r3, [r7, #4] } 80169ce: 4618 mov r0, r3 80169d0: 370c adds r7, #12 80169d2: 46bd mov sp, r7 80169d4: f85d 7b04 ldr.w r7, [sp], #4 80169d8: 4770 bx lr 80169da: bf00 nop 80169dc: 240029f8 .word 0x240029f8 080169e0 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 80169e0: b480 push {r7} 80169e2: b083 sub sp, #12 80169e4: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 80169e6: 4b0b ldr r3, [pc, #44] @ (8016a14 ) 80169e8: 681b ldr r3, [r3, #0] 80169ea: 2b00 cmp r3, #0 80169ec: d102 bne.n 80169f4 { xReturn = taskSCHEDULER_NOT_STARTED; 80169ee: 2301 movs r3, #1 80169f0: 607b str r3, [r7, #4] 80169f2: e008 b.n 8016a06 } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80169f4: 4b08 ldr r3, [pc, #32] @ (8016a18 ) 80169f6: 681b ldr r3, [r3, #0] 80169f8: 2b00 cmp r3, #0 80169fa: d102 bne.n 8016a02 { xReturn = taskSCHEDULER_RUNNING; 80169fc: 2302 movs r3, #2 80169fe: 607b str r3, [r7, #4] 8016a00: e001 b.n 8016a06 } else { xReturn = taskSCHEDULER_SUSPENDED; 8016a02: 2300 movs r3, #0 8016a04: 607b str r3, [r7, #4] } } return xReturn; 8016a06: 687b ldr r3, [r7, #4] } 8016a08: 4618 mov r0, r3 8016a0a: 370c adds r7, #12 8016a0c: 46bd mov sp, r7 8016a0e: f85d 7b04 ldr.w r7, [sp], #4 8016a12: 4770 bx lr 8016a14: 24002ed8 .word 0x24002ed8 8016a18: 24002ef4 .word 0x24002ef4 08016a1c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8016a1c: b580 push {r7, lr} 8016a1e: b084 sub sp, #16 8016a20: af00 add r7, sp, #0 8016a22: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8016a24: 687b ldr r3, [r7, #4] 8016a26: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8016a28: 2300 movs r3, #0 8016a2a: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8016a2c: 687b ldr r3, [r7, #4] 8016a2e: 2b00 cmp r3, #0 8016a30: d051 beq.n 8016ad6 { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8016a32: 68bb ldr r3, [r7, #8] 8016a34: 6ada ldr r2, [r3, #44] @ 0x2c 8016a36: 4b2a ldr r3, [pc, #168] @ (8016ae0 ) 8016a38: 681b ldr r3, [r3, #0] 8016a3a: 6adb ldr r3, [r3, #44] @ 0x2c 8016a3c: 429a cmp r2, r3 8016a3e: d241 bcs.n 8016ac4 { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016a40: 68bb ldr r3, [r7, #8] 8016a42: 699b ldr r3, [r3, #24] 8016a44: 2b00 cmp r3, #0 8016a46: db06 blt.n 8016a56 { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016a48: 4b25 ldr r3, [pc, #148] @ (8016ae0 ) 8016a4a: 681b ldr r3, [r3, #0] 8016a4c: 6adb ldr r3, [r3, #44] @ 0x2c 8016a4e: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016a52: 68bb ldr r3, [r7, #8] 8016a54: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8016a56: 68bb ldr r3, [r7, #8] 8016a58: 6959 ldr r1, [r3, #20] 8016a5a: 68bb ldr r3, [r7, #8] 8016a5c: 6ada ldr r2, [r3, #44] @ 0x2c 8016a5e: 4613 mov r3, r2 8016a60: 009b lsls r3, r3, #2 8016a62: 4413 add r3, r2 8016a64: 009b lsls r3, r3, #2 8016a66: 4a1f ldr r2, [pc, #124] @ (8016ae4 ) 8016a68: 4413 add r3, r2 8016a6a: 4299 cmp r1, r3 8016a6c: d122 bne.n 8016ab4 { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016a6e: 68bb ldr r3, [r7, #8] 8016a70: 3304 adds r3, #4 8016a72: 4618 mov r0, r3 8016a74: f7fd ff96 bl 80149a4 { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016a78: 4b19 ldr r3, [pc, #100] @ (8016ae0 ) 8016a7a: 681b ldr r3, [r3, #0] 8016a7c: 6ada ldr r2, [r3, #44] @ 0x2c 8016a7e: 68bb ldr r3, [r7, #8] 8016a80: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 8016a82: 68bb ldr r3, [r7, #8] 8016a84: 6ada ldr r2, [r3, #44] @ 0x2c 8016a86: 4b18 ldr r3, [pc, #96] @ (8016ae8 ) 8016a88: 681b ldr r3, [r3, #0] 8016a8a: 429a cmp r2, r3 8016a8c: d903 bls.n 8016a96 8016a8e: 68bb ldr r3, [r7, #8] 8016a90: 6adb ldr r3, [r3, #44] @ 0x2c 8016a92: 4a15 ldr r2, [pc, #84] @ (8016ae8 ) 8016a94: 6013 str r3, [r2, #0] 8016a96: 68bb ldr r3, [r7, #8] 8016a98: 6ada ldr r2, [r3, #44] @ 0x2c 8016a9a: 4613 mov r3, r2 8016a9c: 009b lsls r3, r3, #2 8016a9e: 4413 add r3, r2 8016aa0: 009b lsls r3, r3, #2 8016aa2: 4a10 ldr r2, [pc, #64] @ (8016ae4 ) 8016aa4: 441a add r2, r3 8016aa6: 68bb ldr r3, [r7, #8] 8016aa8: 3304 adds r3, #4 8016aaa: 4619 mov r1, r3 8016aac: 4610 mov r0, r2 8016aae: f7fd ff1c bl 80148ea 8016ab2: e004 b.n 8016abe } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016ab4: 4b0a ldr r3, [pc, #40] @ (8016ae0 ) 8016ab6: 681b ldr r3, [r3, #0] 8016ab8: 6ada ldr r2, [r3, #44] @ 0x2c 8016aba: 68bb ldr r3, [r7, #8] 8016abc: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8016abe: 2301 movs r3, #1 8016ac0: 60fb str r3, [r7, #12] 8016ac2: e008 b.n 8016ad6 } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8016ac4: 68bb ldr r3, [r7, #8] 8016ac6: 6cda ldr r2, [r3, #76] @ 0x4c 8016ac8: 4b05 ldr r3, [pc, #20] @ (8016ae0 ) 8016aca: 681b ldr r3, [r3, #0] 8016acc: 6adb ldr r3, [r3, #44] @ 0x2c 8016ace: 429a cmp r2, r3 8016ad0: d201 bcs.n 8016ad6 current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 8016ad2: 2301 movs r3, #1 8016ad4: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016ad6: 68fb ldr r3, [r7, #12] } 8016ad8: 4618 mov r0, r3 8016ada: 3710 adds r7, #16 8016adc: 46bd mov sp, r7 8016ade: bd80 pop {r7, pc} 8016ae0: 240029f8 .word 0x240029f8 8016ae4: 240029fc .word 0x240029fc 8016ae8: 24002ed4 .word 0x24002ed4 08016aec : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8016aec: b580 push {r7, lr} 8016aee: b086 sub sp, #24 8016af0: af00 add r7, sp, #0 8016af2: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8016af4: 687b ldr r3, [r7, #4] 8016af6: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8016af8: 2300 movs r3, #0 8016afa: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016afc: 687b ldr r3, [r7, #4] 8016afe: 2b00 cmp r3, #0 8016b00: d058 beq.n 8016bb4 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8016b02: 4b2f ldr r3, [pc, #188] @ (8016bc0 ) 8016b04: 681b ldr r3, [r3, #0] 8016b06: 693a ldr r2, [r7, #16] 8016b08: 429a cmp r2, r3 8016b0a: d00b beq.n 8016b24 __asm volatile 8016b0c: f04f 0350 mov.w r3, #80 @ 0x50 8016b10: f383 8811 msr BASEPRI, r3 8016b14: f3bf 8f6f isb sy 8016b18: f3bf 8f4f dsb sy 8016b1c: 60fb str r3, [r7, #12] } 8016b1e: bf00 nop 8016b20: bf00 nop 8016b22: e7fd b.n 8016b20 configASSERT( pxTCB->uxMutexesHeld ); 8016b24: 693b ldr r3, [r7, #16] 8016b26: 6d1b ldr r3, [r3, #80] @ 0x50 8016b28: 2b00 cmp r3, #0 8016b2a: d10b bne.n 8016b44 __asm volatile 8016b2c: f04f 0350 mov.w r3, #80 @ 0x50 8016b30: f383 8811 msr BASEPRI, r3 8016b34: f3bf 8f6f isb sy 8016b38: f3bf 8f4f dsb sy 8016b3c: 60bb str r3, [r7, #8] } 8016b3e: bf00 nop 8016b40: bf00 nop 8016b42: e7fd b.n 8016b40 ( pxTCB->uxMutexesHeld )--; 8016b44: 693b ldr r3, [r7, #16] 8016b46: 6d1b ldr r3, [r3, #80] @ 0x50 8016b48: 1e5a subs r2, r3, #1 8016b4a: 693b ldr r3, [r7, #16] 8016b4c: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 8016b4e: 693b ldr r3, [r7, #16] 8016b50: 6ada ldr r2, [r3, #44] @ 0x2c 8016b52: 693b ldr r3, [r7, #16] 8016b54: 6cdb ldr r3, [r3, #76] @ 0x4c 8016b56: 429a cmp r2, r3 8016b58: d02c beq.n 8016bb4 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 8016b5a: 693b ldr r3, [r7, #16] 8016b5c: 6d1b ldr r3, [r3, #80] @ 0x50 8016b5e: 2b00 cmp r3, #0 8016b60: d128 bne.n 8016bb4 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016b62: 693b ldr r3, [r7, #16] 8016b64: 3304 adds r3, #4 8016b66: 4618 mov r0, r3 8016b68: f7fd ff1c bl 80149a4 } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8016b6c: 693b ldr r3, [r7, #16] 8016b6e: 6cda ldr r2, [r3, #76] @ 0x4c 8016b70: 693b ldr r3, [r7, #16] 8016b72: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016b74: 693b ldr r3, [r7, #16] 8016b76: 6adb ldr r3, [r3, #44] @ 0x2c 8016b78: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016b7c: 693b ldr r3, [r7, #16] 8016b7e: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8016b80: 693b ldr r3, [r7, #16] 8016b82: 6ada ldr r2, [r3, #44] @ 0x2c 8016b84: 4b0f ldr r3, [pc, #60] @ (8016bc4 ) 8016b86: 681b ldr r3, [r3, #0] 8016b88: 429a cmp r2, r3 8016b8a: d903 bls.n 8016b94 8016b8c: 693b ldr r3, [r7, #16] 8016b8e: 6adb ldr r3, [r3, #44] @ 0x2c 8016b90: 4a0c ldr r2, [pc, #48] @ (8016bc4 ) 8016b92: 6013 str r3, [r2, #0] 8016b94: 693b ldr r3, [r7, #16] 8016b96: 6ada ldr r2, [r3, #44] @ 0x2c 8016b98: 4613 mov r3, r2 8016b9a: 009b lsls r3, r3, #2 8016b9c: 4413 add r3, r2 8016b9e: 009b lsls r3, r3, #2 8016ba0: 4a09 ldr r2, [pc, #36] @ (8016bc8 ) 8016ba2: 441a add r2, r3 8016ba4: 693b ldr r3, [r7, #16] 8016ba6: 3304 adds r3, #4 8016ba8: 4619 mov r1, r3 8016baa: 4610 mov r0, r2 8016bac: f7fd fe9d bl 80148ea in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8016bb0: 2301 movs r3, #1 8016bb2: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016bb4: 697b ldr r3, [r7, #20] } 8016bb6: 4618 mov r0, r3 8016bb8: 3718 adds r7, #24 8016bba: 46bd mov sp, r7 8016bbc: bd80 pop {r7, pc} 8016bbe: bf00 nop 8016bc0: 240029f8 .word 0x240029f8 8016bc4: 24002ed4 .word 0x24002ed4 8016bc8: 240029fc .word 0x240029fc 08016bcc : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 8016bcc: b580 push {r7, lr} 8016bce: b088 sub sp, #32 8016bd0: af00 add r7, sp, #0 8016bd2: 6078 str r0, [r7, #4] 8016bd4: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 8016bd6: 687b ldr r3, [r7, #4] 8016bd8: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 8016bda: 2301 movs r3, #1 8016bdc: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016bde: 687b ldr r3, [r7, #4] 8016be0: 2b00 cmp r3, #0 8016be2: d06c beq.n 8016cbe { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8016be4: 69bb ldr r3, [r7, #24] 8016be6: 6d1b ldr r3, [r3, #80] @ 0x50 8016be8: 2b00 cmp r3, #0 8016bea: d10b bne.n 8016c04 __asm volatile 8016bec: f04f 0350 mov.w r3, #80 @ 0x50 8016bf0: f383 8811 msr BASEPRI, r3 8016bf4: f3bf 8f6f isb sy 8016bf8: f3bf 8f4f dsb sy 8016bfc: 60fb str r3, [r7, #12] } 8016bfe: bf00 nop 8016c00: bf00 nop 8016c02: e7fd b.n 8016c00 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8016c04: 69bb ldr r3, [r7, #24] 8016c06: 6cdb ldr r3, [r3, #76] @ 0x4c 8016c08: 683a ldr r2, [r7, #0] 8016c0a: 429a cmp r2, r3 8016c0c: d902 bls.n 8016c14 { uxPriorityToUse = uxHighestPriorityWaitingTask; 8016c0e: 683b ldr r3, [r7, #0] 8016c10: 61fb str r3, [r7, #28] 8016c12: e002 b.n 8016c1a } else { uxPriorityToUse = pxTCB->uxBasePriority; 8016c14: 69bb ldr r3, [r7, #24] 8016c16: 6cdb ldr r3, [r3, #76] @ 0x4c 8016c18: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 8016c1a: 69bb ldr r3, [r7, #24] 8016c1c: 6adb ldr r3, [r3, #44] @ 0x2c 8016c1e: 69fa ldr r2, [r7, #28] 8016c20: 429a cmp r2, r3 8016c22: d04c beq.n 8016cbe { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8016c24: 69bb ldr r3, [r7, #24] 8016c26: 6d1b ldr r3, [r3, #80] @ 0x50 8016c28: 697a ldr r2, [r7, #20] 8016c2a: 429a cmp r2, r3 8016c2c: d147 bne.n 8016cbe { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 8016c2e: 4b26 ldr r3, [pc, #152] @ (8016cc8 ) 8016c30: 681b ldr r3, [r3, #0] 8016c32: 69ba ldr r2, [r7, #24] 8016c34: 429a cmp r2, r3 8016c36: d10b bne.n 8016c50 __asm volatile 8016c38: f04f 0350 mov.w r3, #80 @ 0x50 8016c3c: f383 8811 msr BASEPRI, r3 8016c40: f3bf 8f6f isb sy 8016c44: f3bf 8f4f dsb sy 8016c48: 60bb str r3, [r7, #8] } 8016c4a: bf00 nop 8016c4c: bf00 nop 8016c4e: e7fd b.n 8016c4c /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 8016c50: 69bb ldr r3, [r7, #24] 8016c52: 6adb ldr r3, [r3, #44] @ 0x2c 8016c54: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 8016c56: 69bb ldr r3, [r7, #24] 8016c58: 69fa ldr r2, [r7, #28] 8016c5a: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016c5c: 69bb ldr r3, [r7, #24] 8016c5e: 699b ldr r3, [r3, #24] 8016c60: 2b00 cmp r3, #0 8016c62: db04 blt.n 8016c6e { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016c64: 69fb ldr r3, [r7, #28] 8016c66: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016c6a: 69bb ldr r3, [r7, #24] 8016c6c: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 8016c6e: 69bb ldr r3, [r7, #24] 8016c70: 6959 ldr r1, [r3, #20] 8016c72: 693a ldr r2, [r7, #16] 8016c74: 4613 mov r3, r2 8016c76: 009b lsls r3, r3, #2 8016c78: 4413 add r3, r2 8016c7a: 009b lsls r3, r3, #2 8016c7c: 4a13 ldr r2, [pc, #76] @ (8016ccc ) 8016c7e: 4413 add r3, r2 8016c80: 4299 cmp r1, r3 8016c82: d11c bne.n 8016cbe { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016c84: 69bb ldr r3, [r7, #24] 8016c86: 3304 adds r3, #4 8016c88: 4618 mov r0, r3 8016c8a: f7fd fe8b bl 80149a4 else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8016c8e: 69bb ldr r3, [r7, #24] 8016c90: 6ada ldr r2, [r3, #44] @ 0x2c 8016c92: 4b0f ldr r3, [pc, #60] @ (8016cd0 ) 8016c94: 681b ldr r3, [r3, #0] 8016c96: 429a cmp r2, r3 8016c98: d903 bls.n 8016ca2 8016c9a: 69bb ldr r3, [r7, #24] 8016c9c: 6adb ldr r3, [r3, #44] @ 0x2c 8016c9e: 4a0c ldr r2, [pc, #48] @ (8016cd0 ) 8016ca0: 6013 str r3, [r2, #0] 8016ca2: 69bb ldr r3, [r7, #24] 8016ca4: 6ada ldr r2, [r3, #44] @ 0x2c 8016ca6: 4613 mov r3, r2 8016ca8: 009b lsls r3, r3, #2 8016caa: 4413 add r3, r2 8016cac: 009b lsls r3, r3, #2 8016cae: 4a07 ldr r2, [pc, #28] @ (8016ccc ) 8016cb0: 441a add r2, r3 8016cb2: 69bb ldr r3, [r7, #24] 8016cb4: 3304 adds r3, #4 8016cb6: 4619 mov r1, r3 8016cb8: 4610 mov r0, r2 8016cba: f7fd fe16 bl 80148ea } else { mtCOVERAGE_TEST_MARKER(); } } 8016cbe: bf00 nop 8016cc0: 3720 adds r7, #32 8016cc2: 46bd mov sp, r7 8016cc4: bd80 pop {r7, pc} 8016cc6: bf00 nop 8016cc8: 240029f8 .word 0x240029f8 8016ccc: 240029fc .word 0x240029fc 8016cd0: 24002ed4 .word 0x24002ed4 08016cd4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 8016cd4: b480 push {r7} 8016cd6: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 8016cd8: 4b07 ldr r3, [pc, #28] @ (8016cf8 ) 8016cda: 681b ldr r3, [r3, #0] 8016cdc: 2b00 cmp r3, #0 8016cde: d004 beq.n 8016cea { ( pxCurrentTCB->uxMutexesHeld )++; 8016ce0: 4b05 ldr r3, [pc, #20] @ (8016cf8 ) 8016ce2: 681b ldr r3, [r3, #0] 8016ce4: 6d1a ldr r2, [r3, #80] @ 0x50 8016ce6: 3201 adds r2, #1 8016ce8: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 8016cea: 4b03 ldr r3, [pc, #12] @ (8016cf8 ) 8016cec: 681b ldr r3, [r3, #0] } 8016cee: 4618 mov r0, r3 8016cf0: 46bd mov sp, r7 8016cf2: f85d 7b04 ldr.w r7, [sp], #4 8016cf6: 4770 bx lr 8016cf8: 240029f8 .word 0x240029f8 08016cfc : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 8016cfc: b580 push {r7, lr} 8016cfe: b086 sub sp, #24 8016d00: af00 add r7, sp, #0 8016d02: 60f8 str r0, [r7, #12] 8016d04: 60b9 str r1, [r7, #8] 8016d06: 607a str r2, [r7, #4] 8016d08: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 8016d0a: f000 ffed bl 8017ce8 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016d0e: 4b29 ldr r3, [pc, #164] @ (8016db4 ) 8016d10: 681b ldr r3, [r3, #0] 8016d12: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016d16: b2db uxtb r3, r3 8016d18: 2b02 cmp r3, #2 8016d1a: d01c beq.n 8016d56 { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 8016d1c: 4b25 ldr r3, [pc, #148] @ (8016db4 ) 8016d1e: 681b ldr r3, [r3, #0] 8016d20: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016d24: 68fa ldr r2, [r7, #12] 8016d26: 43d2 mvns r2, r2 8016d28: 400a ands r2, r1 8016d2a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 8016d2e: 4b21 ldr r3, [pc, #132] @ (8016db4 ) 8016d30: 681b ldr r3, [r3, #0] 8016d32: 2201 movs r2, #1 8016d34: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 8016d38: 683b ldr r3, [r7, #0] 8016d3a: 2b00 cmp r3, #0 8016d3c: d00b beq.n 8016d56 { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016d3e: 2101 movs r1, #1 8016d40: 6838 ldr r0, [r7, #0] 8016d42: f000 fa09 bl 8017158 /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 8016d46: 4b1c ldr r3, [pc, #112] @ (8016db8 ) 8016d48: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016d4c: 601a str r2, [r3, #0] 8016d4e: f3bf 8f4f dsb sy 8016d52: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016d56: f000 fff9 bl 8017d4c taskENTER_CRITICAL(); 8016d5a: f000 ffc5 bl 8017ce8 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 8016d5e: 687b ldr r3, [r7, #4] 8016d60: 2b00 cmp r3, #0 8016d62: d005 beq.n 8016d70 { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 8016d64: 4b13 ldr r3, [pc, #76] @ (8016db4 ) 8016d66: 681b ldr r3, [r3, #0] 8016d68: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016d6c: 687b ldr r3, [r7, #4] 8016d6e: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016d70: 4b10 ldr r3, [pc, #64] @ (8016db4 ) 8016d72: 681b ldr r3, [r3, #0] 8016d74: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016d78: b2db uxtb r3, r3 8016d7a: 2b02 cmp r3, #2 8016d7c: d002 beq.n 8016d84 { /* A notification was not received. */ xReturn = pdFALSE; 8016d7e: 2300 movs r3, #0 8016d80: 617b str r3, [r7, #20] 8016d82: e00a b.n 8016d9a } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 8016d84: 4b0b ldr r3, [pc, #44] @ (8016db4 ) 8016d86: 681b ldr r3, [r3, #0] 8016d88: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016d8c: 68ba ldr r2, [r7, #8] 8016d8e: 43d2 mvns r2, r2 8016d90: 400a ands r2, r1 8016d92: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 8016d96: 2301 movs r3, #1 8016d98: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8016d9a: 4b06 ldr r3, [pc, #24] @ (8016db4 ) 8016d9c: 681b ldr r3, [r3, #0] 8016d9e: 2200 movs r2, #0 8016da0: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 8016da4: f000 ffd2 bl 8017d4c return xReturn; 8016da8: 697b ldr r3, [r7, #20] } 8016daa: 4618 mov r0, r3 8016dac: 3718 adds r7, #24 8016dae: 46bd mov sp, r7 8016db0: bd80 pop {r7, pc} 8016db2: bf00 nop 8016db4: 240029f8 .word 0x240029f8 8016db8: e000ed04 .word 0xe000ed04 08016dbc : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 8016dbc: b580 push {r7, lr} 8016dbe: b08a sub sp, #40 @ 0x28 8016dc0: af00 add r7, sp, #0 8016dc2: 60f8 str r0, [r7, #12] 8016dc4: 60b9 str r1, [r7, #8] 8016dc6: 603b str r3, [r7, #0] 8016dc8: 4613 mov r3, r2 8016dca: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 8016dcc: 2301 movs r3, #1 8016dce: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 8016dd0: 68fb ldr r3, [r7, #12] 8016dd2: 2b00 cmp r3, #0 8016dd4: d10b bne.n 8016dee __asm volatile 8016dd6: f04f 0350 mov.w r3, #80 @ 0x50 8016dda: f383 8811 msr BASEPRI, r3 8016dde: f3bf 8f6f isb sy 8016de2: f3bf 8f4f dsb sy 8016de6: 61bb str r3, [r7, #24] } 8016de8: bf00 nop 8016dea: bf00 nop 8016dec: e7fd b.n 8016dea pxTCB = xTaskToNotify; 8016dee: 68fb ldr r3, [r7, #12] 8016df0: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 8016df2: f000 ff79 bl 8017ce8 { if( pulPreviousNotificationValue != NULL ) 8016df6: 683b ldr r3, [r7, #0] 8016df8: 2b00 cmp r3, #0 8016dfa: d004 beq.n 8016e06 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016dfc: 6a3b ldr r3, [r7, #32] 8016dfe: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016e02: 683b ldr r3, [r7, #0] 8016e04: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016e06: 6a3b ldr r3, [r7, #32] 8016e08: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016e0c: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016e0e: 6a3b ldr r3, [r7, #32] 8016e10: 2202 movs r2, #2 8016e12: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016e16: 79fb ldrb r3, [r7, #7] 8016e18: 2b04 cmp r3, #4 8016e1a: d82e bhi.n 8016e7a 8016e1c: a201 add r2, pc, #4 @ (adr r2, 8016e24 ) 8016e1e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016e22: bf00 nop 8016e24: 08016e9f .word 0x08016e9f 8016e28: 08016e39 .word 0x08016e39 8016e2c: 08016e4b .word 0x08016e4b 8016e30: 08016e5b .word 0x08016e5b 8016e34: 08016e65 .word 0x08016e65 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016e38: 6a3b ldr r3, [r7, #32] 8016e3a: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016e3e: 68bb ldr r3, [r7, #8] 8016e40: 431a orrs r2, r3 8016e42: 6a3b ldr r3, [r7, #32] 8016e44: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e48: e02c b.n 8016ea4 case eIncrement : ( pxTCB->ulNotifiedValue )++; 8016e4a: 6a3b ldr r3, [r7, #32] 8016e4c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016e50: 1c5a adds r2, r3, #1 8016e52: 6a3b ldr r3, [r7, #32] 8016e54: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e58: e024 b.n 8016ea4 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 8016e5a: 6a3b ldr r3, [r7, #32] 8016e5c: 68ba ldr r2, [r7, #8] 8016e5e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e62: e01f b.n 8016ea4 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016e64: 7ffb ldrb r3, [r7, #31] 8016e66: 2b02 cmp r3, #2 8016e68: d004 beq.n 8016e74 { pxTCB->ulNotifiedValue = ulValue; 8016e6a: 6a3b ldr r3, [r7, #32] 8016e6c: 68ba ldr r2, [r7, #8] 8016e6e: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016e72: e017 b.n 8016ea4 xReturn = pdFAIL; 8016e74: 2300 movs r3, #0 8016e76: 627b str r3, [r7, #36] @ 0x24 break; 8016e78: e014 b.n 8016ea4 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 8016e7a: 6a3b ldr r3, [r7, #32] 8016e7c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016e80: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016e84: d00d beq.n 8016ea2 __asm volatile 8016e86: f04f 0350 mov.w r3, #80 @ 0x50 8016e8a: f383 8811 msr BASEPRI, r3 8016e8e: f3bf 8f6f isb sy 8016e92: f3bf 8f4f dsb sy 8016e96: 617b str r3, [r7, #20] } 8016e98: bf00 nop 8016e9a: bf00 nop 8016e9c: e7fd b.n 8016e9a break; 8016e9e: bf00 nop 8016ea0: e000 b.n 8016ea4 break; 8016ea2: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8016ea4: 7ffb ldrb r3, [r7, #31] 8016ea6: 2b01 cmp r3, #1 8016ea8: d13b bne.n 8016f22 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016eaa: 6a3b ldr r3, [r7, #32] 8016eac: 3304 adds r3, #4 8016eae: 4618 mov r0, r3 8016eb0: f7fd fd78 bl 80149a4 prvAddTaskToReadyList( pxTCB ); 8016eb4: 6a3b ldr r3, [r7, #32] 8016eb6: 6ada ldr r2, [r3, #44] @ 0x2c 8016eb8: 4b1d ldr r3, [pc, #116] @ (8016f30 ) 8016eba: 681b ldr r3, [r3, #0] 8016ebc: 429a cmp r2, r3 8016ebe: d903 bls.n 8016ec8 8016ec0: 6a3b ldr r3, [r7, #32] 8016ec2: 6adb ldr r3, [r3, #44] @ 0x2c 8016ec4: 4a1a ldr r2, [pc, #104] @ (8016f30 ) 8016ec6: 6013 str r3, [r2, #0] 8016ec8: 6a3b ldr r3, [r7, #32] 8016eca: 6ada ldr r2, [r3, #44] @ 0x2c 8016ecc: 4613 mov r3, r2 8016ece: 009b lsls r3, r3, #2 8016ed0: 4413 add r3, r2 8016ed2: 009b lsls r3, r3, #2 8016ed4: 4a17 ldr r2, [pc, #92] @ (8016f34 ) 8016ed6: 441a add r2, r3 8016ed8: 6a3b ldr r3, [r7, #32] 8016eda: 3304 adds r3, #4 8016edc: 4619 mov r1, r3 8016ede: 4610 mov r0, r2 8016ee0: f7fd fd03 bl 80148ea /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8016ee4: 6a3b ldr r3, [r7, #32] 8016ee6: 6a9b ldr r3, [r3, #40] @ 0x28 8016ee8: 2b00 cmp r3, #0 8016eea: d00b beq.n 8016f04 __asm volatile 8016eec: f04f 0350 mov.w r3, #80 @ 0x50 8016ef0: f383 8811 msr BASEPRI, r3 8016ef4: f3bf 8f6f isb sy 8016ef8: f3bf 8f4f dsb sy 8016efc: 613b str r3, [r7, #16] } 8016efe: bf00 nop 8016f00: bf00 nop 8016f02: e7fd b.n 8016f00 earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016f04: 6a3b ldr r3, [r7, #32] 8016f06: 6ada ldr r2, [r3, #44] @ 0x2c 8016f08: 4b0b ldr r3, [pc, #44] @ (8016f38 ) 8016f0a: 681b ldr r3, [r3, #0] 8016f0c: 6adb ldr r3, [r3, #44] @ 0x2c 8016f0e: 429a cmp r2, r3 8016f10: d907 bls.n 8016f22 { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016f12: 4b0a ldr r3, [pc, #40] @ (8016f3c ) 8016f14: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016f18: 601a str r2, [r3, #0] 8016f1a: f3bf 8f4f dsb sy 8016f1e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016f22: f000 ff13 bl 8017d4c return xReturn; 8016f26: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016f28: 4618 mov r0, r3 8016f2a: 3728 adds r7, #40 @ 0x28 8016f2c: 46bd mov sp, r7 8016f2e: bd80 pop {r7, pc} 8016f30: 24002ed4 .word 0x24002ed4 8016f34: 240029fc .word 0x240029fc 8016f38: 240029f8 .word 0x240029f8 8016f3c: e000ed04 .word 0xe000ed04 08016f40 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 8016f40: b580 push {r7, lr} 8016f42: b08e sub sp, #56 @ 0x38 8016f44: af00 add r7, sp, #0 8016f46: 60f8 str r0, [r7, #12] 8016f48: 60b9 str r1, [r7, #8] 8016f4a: 603b str r3, [r7, #0] 8016f4c: 4613 mov r3, r2 8016f4e: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8016f50: 2301 movs r3, #1 8016f52: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016f54: 68fb ldr r3, [r7, #12] 8016f56: 2b00 cmp r3, #0 8016f58: d10b bne.n 8016f72 __asm volatile 8016f5a: f04f 0350 mov.w r3, #80 @ 0x50 8016f5e: f383 8811 msr BASEPRI, r3 8016f62: f3bf 8f6f isb sy 8016f66: f3bf 8f4f dsb sy 8016f6a: 627b str r3, [r7, #36] @ 0x24 } 8016f6c: bf00 nop 8016f6e: bf00 nop 8016f70: e7fd b.n 8016f6e below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8016f72: f000 ff99 bl 8017ea8 pxTCB = xTaskToNotify; 8016f76: 68fb ldr r3, [r7, #12] 8016f78: 633b str r3, [r7, #48] @ 0x30 __asm volatile 8016f7a: f3ef 8211 mrs r2, BASEPRI 8016f7e: f04f 0350 mov.w r3, #80 @ 0x50 8016f82: f383 8811 msr BASEPRI, r3 8016f86: f3bf 8f6f isb sy 8016f8a: f3bf 8f4f dsb sy 8016f8e: 623a str r2, [r7, #32] 8016f90: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 8016f92: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8016f94: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 8016f96: 683b ldr r3, [r7, #0] 8016f98: 2b00 cmp r3, #0 8016f9a: d004 beq.n 8016fa6 { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016f9c: 6b3b ldr r3, [r7, #48] @ 0x30 8016f9e: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016fa2: 683b ldr r3, [r7, #0] 8016fa4: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016fa6: 6b3b ldr r3, [r7, #48] @ 0x30 8016fa8: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016fac: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016fb0: 6b3b ldr r3, [r7, #48] @ 0x30 8016fb2: 2202 movs r2, #2 8016fb4: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016fb8: 79fb ldrb r3, [r7, #7] 8016fba: 2b04 cmp r3, #4 8016fbc: d82e bhi.n 801701c 8016fbe: a201 add r2, pc, #4 @ (adr r2, 8016fc4 ) 8016fc0: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016fc4: 08017041 .word 0x08017041 8016fc8: 08016fd9 .word 0x08016fd9 8016fcc: 08016feb .word 0x08016feb 8016fd0: 08016ffb .word 0x08016ffb 8016fd4: 08017005 .word 0x08017005 { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016fd8: 6b3b ldr r3, [r7, #48] @ 0x30 8016fda: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016fde: 68bb ldr r3, [r7, #8] 8016fe0: 431a orrs r2, r3 8016fe2: 6b3b ldr r3, [r7, #48] @ 0x30 8016fe4: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016fe8: e02d b.n 8017046 case eIncrement : ( pxTCB->ulNotifiedValue )++; 8016fea: 6b3b ldr r3, [r7, #48] @ 0x30 8016fec: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016ff0: 1c5a adds r2, r3, #1 8016ff2: 6b3b ldr r3, [r7, #48] @ 0x30 8016ff4: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016ff8: e025 b.n 8017046 case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 8016ffa: 6b3b ldr r3, [r7, #48] @ 0x30 8016ffc: 68ba ldr r2, [r7, #8] 8016ffe: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8017002: e020 b.n 8017046 case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8017004: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8017008: 2b02 cmp r3, #2 801700a: d004 beq.n 8017016 { pxTCB->ulNotifiedValue = ulValue; 801700c: 6b3b ldr r3, [r7, #48] @ 0x30 801700e: 68ba ldr r2, [r7, #8] 8017010: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8017014: e017 b.n 8017046 xReturn = pdFAIL; 8017016: 2300 movs r3, #0 8017018: 637b str r3, [r7, #52] @ 0x34 break; 801701a: e014 b.n 8017046 default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 801701c: 6b3b ldr r3, [r7, #48] @ 0x30 801701e: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8017022: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017026: d00d beq.n 8017044 __asm volatile 8017028: f04f 0350 mov.w r3, #80 @ 0x50 801702c: f383 8811 msr BASEPRI, r3 8017030: f3bf 8f6f isb sy 8017034: f3bf 8f4f dsb sy 8017038: 61bb str r3, [r7, #24] } 801703a: bf00 nop 801703c: bf00 nop 801703e: e7fd b.n 801703c break; 8017040: bf00 nop 8017042: e000 b.n 8017046 break; 8017044: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8017046: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 801704a: 2b01 cmp r3, #1 801704c: d147 bne.n 80170de { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 801704e: 6b3b ldr r3, [r7, #48] @ 0x30 8017050: 6a9b ldr r3, [r3, #40] @ 0x28 8017052: 2b00 cmp r3, #0 8017054: d00b beq.n 801706e __asm volatile 8017056: f04f 0350 mov.w r3, #80 @ 0x50 801705a: f383 8811 msr BASEPRI, r3 801705e: f3bf 8f6f isb sy 8017062: f3bf 8f4f dsb sy 8017066: 617b str r3, [r7, #20] } 8017068: bf00 nop 801706a: bf00 nop 801706c: e7fd b.n 801706a if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 801706e: 4b21 ldr r3, [pc, #132] @ (80170f4 ) 8017070: 681b ldr r3, [r3, #0] 8017072: 2b00 cmp r3, #0 8017074: d11d bne.n 80170b2 { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8017076: 6b3b ldr r3, [r7, #48] @ 0x30 8017078: 3304 adds r3, #4 801707a: 4618 mov r0, r3 801707c: f7fd fc92 bl 80149a4 prvAddTaskToReadyList( pxTCB ); 8017080: 6b3b ldr r3, [r7, #48] @ 0x30 8017082: 6ada ldr r2, [r3, #44] @ 0x2c 8017084: 4b1c ldr r3, [pc, #112] @ (80170f8 ) 8017086: 681b ldr r3, [r3, #0] 8017088: 429a cmp r2, r3 801708a: d903 bls.n 8017094 801708c: 6b3b ldr r3, [r7, #48] @ 0x30 801708e: 6adb ldr r3, [r3, #44] @ 0x2c 8017090: 4a19 ldr r2, [pc, #100] @ (80170f8 ) 8017092: 6013 str r3, [r2, #0] 8017094: 6b3b ldr r3, [r7, #48] @ 0x30 8017096: 6ada ldr r2, [r3, #44] @ 0x2c 8017098: 4613 mov r3, r2 801709a: 009b lsls r3, r3, #2 801709c: 4413 add r3, r2 801709e: 009b lsls r3, r3, #2 80170a0: 4a16 ldr r2, [pc, #88] @ (80170fc ) 80170a2: 441a add r2, r3 80170a4: 6b3b ldr r3, [r7, #48] @ 0x30 80170a6: 3304 adds r3, #4 80170a8: 4619 mov r1, r3 80170aa: 4610 mov r0, r2 80170ac: f7fd fc1d bl 80148ea 80170b0: e005 b.n 80170be } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 80170b2: 6b3b ldr r3, [r7, #48] @ 0x30 80170b4: 3318 adds r3, #24 80170b6: 4619 mov r1, r3 80170b8: 4811 ldr r0, [pc, #68] @ (8017100 ) 80170ba: f7fd fc16 bl 80148ea } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80170be: 6b3b ldr r3, [r7, #48] @ 0x30 80170c0: 6ada ldr r2, [r3, #44] @ 0x2c 80170c2: 4b10 ldr r3, [pc, #64] @ (8017104 ) 80170c4: 681b ldr r3, [r3, #0] 80170c6: 6adb ldr r3, [r3, #44] @ 0x2c 80170c8: 429a cmp r2, r3 80170ca: d908 bls.n 80170de { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80170cc: 6c3b ldr r3, [r7, #64] @ 0x40 80170ce: 2b00 cmp r3, #0 80170d0: d002 beq.n 80170d8 { *pxHigherPriorityTaskWoken = pdTRUE; 80170d2: 6c3b ldr r3, [r7, #64] @ 0x40 80170d4: 2201 movs r2, #1 80170d6: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80170d8: 4b0b ldr r3, [pc, #44] @ (8017108 ) 80170da: 2201 movs r2, #1 80170dc: 601a str r2, [r3, #0] 80170de: 6afb ldr r3, [r7, #44] @ 0x2c 80170e0: 613b str r3, [r7, #16] __asm volatile 80170e2: 693b ldr r3, [r7, #16] 80170e4: f383 8811 msr BASEPRI, r3 } 80170e8: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 80170ea: 6b7b ldr r3, [r7, #52] @ 0x34 } 80170ec: 4618 mov r0, r3 80170ee: 3738 adds r7, #56 @ 0x38 80170f0: 46bd mov sp, r7 80170f2: bd80 pop {r7, pc} 80170f4: 24002ef4 .word 0x24002ef4 80170f8: 24002ed4 .word 0x24002ed4 80170fc: 240029fc .word 0x240029fc 8017100: 24002e8c .word 0x24002e8c 8017104: 240029f8 .word 0x240029f8 8017108: 24002ee0 .word 0x24002ee0 0801710c : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 801710c: b580 push {r7, lr} 801710e: b084 sub sp, #16 8017110: af00 add r7, sp, #0 8017112: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 8017114: 687b ldr r3, [r7, #4] 8017116: 2b00 cmp r3, #0 8017118: d102 bne.n 8017120 801711a: 4b0e ldr r3, [pc, #56] @ (8017154 ) 801711c: 681b ldr r3, [r3, #0] 801711e: e000 b.n 8017122 8017120: 687b ldr r3, [r7, #4] 8017122: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 8017124: f000 fde0 bl 8017ce8 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 8017128: 68bb ldr r3, [r7, #8] 801712a: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 801712e: b2db uxtb r3, r3 8017130: 2b02 cmp r3, #2 8017132: d106 bne.n 8017142 { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8017134: 68bb ldr r3, [r7, #8] 8017136: 2200 movs r2, #0 8017138: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 801713c: 2301 movs r3, #1 801713e: 60fb str r3, [r7, #12] 8017140: e001 b.n 8017146 } else { xReturn = pdFAIL; 8017142: 2300 movs r3, #0 8017144: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8017146: f000 fe01 bl 8017d4c return xReturn; 801714a: 68fb ldr r3, [r7, #12] } 801714c: 4618 mov r0, r3 801714e: 3710 adds r7, #16 8017150: 46bd mov sp, r7 8017152: bd80 pop {r7, pc} 8017154: 240029f8 .word 0x240029f8 08017158 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8017158: b580 push {r7, lr} 801715a: b084 sub sp, #16 801715c: af00 add r7, sp, #0 801715e: 6078 str r0, [r7, #4] 8017160: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8017162: 4b21 ldr r3, [pc, #132] @ (80171e8 ) 8017164: 681b ldr r3, [r3, #0] 8017166: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8017168: 4b20 ldr r3, [pc, #128] @ (80171ec ) 801716a: 681b ldr r3, [r3, #0] 801716c: 3304 adds r3, #4 801716e: 4618 mov r0, r3 8017170: f7fd fc18 bl 80149a4 mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8017174: 687b ldr r3, [r7, #4] 8017176: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801717a: d10a bne.n 8017192 801717c: 683b ldr r3, [r7, #0] 801717e: 2b00 cmp r3, #0 8017180: d007 beq.n 8017192 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8017182: 4b1a ldr r3, [pc, #104] @ (80171ec ) 8017184: 681b ldr r3, [r3, #0] 8017186: 3304 adds r3, #4 8017188: 4619 mov r1, r3 801718a: 4819 ldr r0, [pc, #100] @ (80171f0 ) 801718c: f7fd fbad bl 80148ea /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8017190: e026 b.n 80171e0 xTimeToWake = xConstTickCount + xTicksToWait; 8017192: 68fa ldr r2, [r7, #12] 8017194: 687b ldr r3, [r7, #4] 8017196: 4413 add r3, r2 8017198: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 801719a: 4b14 ldr r3, [pc, #80] @ (80171ec ) 801719c: 681b ldr r3, [r3, #0] 801719e: 68ba ldr r2, [r7, #8] 80171a0: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 80171a2: 68ba ldr r2, [r7, #8] 80171a4: 68fb ldr r3, [r7, #12] 80171a6: 429a cmp r2, r3 80171a8: d209 bcs.n 80171be vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80171aa: 4b12 ldr r3, [pc, #72] @ (80171f4 ) 80171ac: 681a ldr r2, [r3, #0] 80171ae: 4b0f ldr r3, [pc, #60] @ (80171ec ) 80171b0: 681b ldr r3, [r3, #0] 80171b2: 3304 adds r3, #4 80171b4: 4619 mov r1, r3 80171b6: 4610 mov r0, r2 80171b8: f7fd fbbb bl 8014932 } 80171bc: e010 b.n 80171e0 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80171be: 4b0e ldr r3, [pc, #56] @ (80171f8 ) 80171c0: 681a ldr r2, [r3, #0] 80171c2: 4b0a ldr r3, [pc, #40] @ (80171ec ) 80171c4: 681b ldr r3, [r3, #0] 80171c6: 3304 adds r3, #4 80171c8: 4619 mov r1, r3 80171ca: 4610 mov r0, r2 80171cc: f7fd fbb1 bl 8014932 if( xTimeToWake < xNextTaskUnblockTime ) 80171d0: 4b0a ldr r3, [pc, #40] @ (80171fc ) 80171d2: 681b ldr r3, [r3, #0] 80171d4: 68ba ldr r2, [r7, #8] 80171d6: 429a cmp r2, r3 80171d8: d202 bcs.n 80171e0 xNextTaskUnblockTime = xTimeToWake; 80171da: 4a08 ldr r2, [pc, #32] @ (80171fc ) 80171dc: 68bb ldr r3, [r7, #8] 80171de: 6013 str r3, [r2, #0] } 80171e0: bf00 nop 80171e2: 3710 adds r7, #16 80171e4: 46bd mov sp, r7 80171e6: bd80 pop {r7, pc} 80171e8: 24002ed0 .word 0x24002ed0 80171ec: 240029f8 .word 0x240029f8 80171f0: 24002eb8 .word 0x24002eb8 80171f4: 24002e88 .word 0x24002e88 80171f8: 24002e84 .word 0x24002e84 80171fc: 24002eec .word 0x24002eec 08017200 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8017200: b580 push {r7, lr} 8017202: b08a sub sp, #40 @ 0x28 8017204: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 8017206: 2300 movs r3, #0 8017208: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 801720a: f000 fbb1 bl 8017970 if( xTimerQueue != NULL ) 801720e: 4b1d ldr r3, [pc, #116] @ (8017284 ) 8017210: 681b ldr r3, [r3, #0] 8017212: 2b00 cmp r3, #0 8017214: d021 beq.n 801725a { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 8017216: 2300 movs r3, #0 8017218: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 801721a: 2300 movs r3, #0 801721c: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 801721e: 1d3a adds r2, r7, #4 8017220: f107 0108 add.w r1, r7, #8 8017224: f107 030c add.w r3, r7, #12 8017228: 4618 mov r0, r3 801722a: f7fd fb17 bl 801485c xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 801722e: 6879 ldr r1, [r7, #4] 8017230: 68bb ldr r3, [r7, #8] 8017232: 68fa ldr r2, [r7, #12] 8017234: 9202 str r2, [sp, #8] 8017236: 9301 str r3, [sp, #4] 8017238: 2302 movs r3, #2 801723a: 9300 str r3, [sp, #0] 801723c: 2300 movs r3, #0 801723e: 460a mov r2, r1 8017240: 4911 ldr r1, [pc, #68] @ (8017288 ) 8017242: 4812 ldr r0, [pc, #72] @ (801728c ) 8017244: f7fe fd2f bl 8015ca6 8017248: 4603 mov r3, r0 801724a: 4a11 ldr r2, [pc, #68] @ (8017290 ) 801724c: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 801724e: 4b10 ldr r3, [pc, #64] @ (8017290 ) 8017250: 681b ldr r3, [r3, #0] 8017252: 2b00 cmp r3, #0 8017254: d001 beq.n 801725a { xReturn = pdPASS; 8017256: 2301 movs r3, #1 8017258: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 801725a: 697b ldr r3, [r7, #20] 801725c: 2b00 cmp r3, #0 801725e: d10b bne.n 8017278 __asm volatile 8017260: f04f 0350 mov.w r3, #80 @ 0x50 8017264: f383 8811 msr BASEPRI, r3 8017268: f3bf 8f6f isb sy 801726c: f3bf 8f4f dsb sy 8017270: 613b str r3, [r7, #16] } 8017272: bf00 nop 8017274: bf00 nop 8017276: e7fd b.n 8017274 return xReturn; 8017278: 697b ldr r3, [r7, #20] } 801727a: 4618 mov r0, r3 801727c: 3718 adds r7, #24 801727e: 46bd mov sp, r7 8017280: bd80 pop {r7, pc} 8017282: bf00 nop 8017284: 24002f28 .word 0x24002f28 8017288: 08018688 .word 0x08018688 801728c: 08017509 .word 0x08017509 8017290: 24002f2c .word 0x24002f2c 08017294 : TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) { 8017294: b580 push {r7, lr} 8017296: b088 sub sp, #32 8017298: af02 add r7, sp, #8 801729a: 60f8 str r0, [r7, #12] 801729c: 60b9 str r1, [r7, #8] 801729e: 607a str r2, [r7, #4] 80172a0: 603b str r3, [r7, #0] Timer_t *pxNewTimer; pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 80172a2: 202c movs r0, #44 @ 0x2c 80172a4: f000 fe42 bl 8017f2c 80172a8: 6178 str r0, [r7, #20] if( pxNewTimer != NULL ) 80172aa: 697b ldr r3, [r7, #20] 80172ac: 2b00 cmp r3, #0 80172ae: d00d beq.n 80172cc { /* Status is thus far zero as the timer is not created statically and has not been started. The auto-reload bit may get set in prvInitialiseNewTimer. */ pxNewTimer->ucStatus = 0x00; 80172b0: 697b ldr r3, [r7, #20] 80172b2: 2200 movs r2, #0 80172b4: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 80172b8: 697b ldr r3, [r7, #20] 80172ba: 9301 str r3, [sp, #4] 80172bc: 6a3b ldr r3, [r7, #32] 80172be: 9300 str r3, [sp, #0] 80172c0: 683b ldr r3, [r7, #0] 80172c2: 687a ldr r2, [r7, #4] 80172c4: 68b9 ldr r1, [r7, #8] 80172c6: 68f8 ldr r0, [r7, #12] 80172c8: f000 f845 bl 8017356 } return pxNewTimer; 80172cc: 697b ldr r3, [r7, #20] } 80172ce: 4618 mov r0, r3 80172d0: 3718 adds r7, #24 80172d2: 46bd mov sp, r7 80172d4: bd80 pop {r7, pc} 080172d6 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) { 80172d6: b580 push {r7, lr} 80172d8: b08a sub sp, #40 @ 0x28 80172da: af02 add r7, sp, #8 80172dc: 60f8 str r0, [r7, #12] 80172de: 60b9 str r1, [r7, #8] 80172e0: 607a str r2, [r7, #4] 80172e2: 603b str r3, [r7, #0] #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTimer_t equals the size of the real timer structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); 80172e4: 232c movs r3, #44 @ 0x2c 80172e6: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( Timer_t ) ); 80172e8: 693b ldr r3, [r7, #16] 80172ea: 2b2c cmp r3, #44 @ 0x2c 80172ec: d00b beq.n 8017306 __asm volatile 80172ee: f04f 0350 mov.w r3, #80 @ 0x50 80172f2: f383 8811 msr BASEPRI, r3 80172f6: f3bf 8f6f isb sy 80172fa: f3bf 8f4f dsb sy 80172fe: 61bb str r3, [r7, #24] } 8017300: bf00 nop 8017302: bf00 nop 8017304: e7fd b.n 8017302 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8017306: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); 8017308: 6afb ldr r3, [r7, #44] @ 0x2c 801730a: 2b00 cmp r3, #0 801730c: d10b bne.n 8017326 __asm volatile 801730e: f04f 0350 mov.w r3, #80 @ 0x50 8017312: f383 8811 msr BASEPRI, r3 8017316: f3bf 8f6f isb sy 801731a: f3bf 8f4f dsb sy 801731e: 617b str r3, [r7, #20] } 8017320: bf00 nop 8017322: bf00 nop 8017324: e7fd b.n 8017322 pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ 8017326: 6afb ldr r3, [r7, #44] @ 0x2c 8017328: 61fb str r3, [r7, #28] if( pxNewTimer != NULL ) 801732a: 69fb ldr r3, [r7, #28] 801732c: 2b00 cmp r3, #0 801732e: d00d beq.n 801734c { /* Timers can be created statically or dynamically so note this timer was created statically in case it is later deleted. The auto-reload bit may get set in prvInitialiseNewTimer(). */ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 8017330: 69fb ldr r3, [r7, #28] 8017332: 2202 movs r2, #2 8017334: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 8017338: 69fb ldr r3, [r7, #28] 801733a: 9301 str r3, [sp, #4] 801733c: 6abb ldr r3, [r7, #40] @ 0x28 801733e: 9300 str r3, [sp, #0] 8017340: 683b ldr r3, [r7, #0] 8017342: 687a ldr r2, [r7, #4] 8017344: 68b9 ldr r1, [r7, #8] 8017346: 68f8 ldr r0, [r7, #12] 8017348: f000 f805 bl 8017356 } return pxNewTimer; 801734c: 69fb ldr r3, [r7, #28] } 801734e: 4618 mov r0, r3 8017350: 3720 adds r7, #32 8017352: 46bd mov sp, r7 8017354: bd80 pop {r7, pc} 08017356 : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) { 8017356: b580 push {r7, lr} 8017358: b086 sub sp, #24 801735a: af00 add r7, sp, #0 801735c: 60f8 str r0, [r7, #12] 801735e: 60b9 str r1, [r7, #8] 8017360: 607a str r2, [r7, #4] 8017362: 603b str r3, [r7, #0] /* 0 is not a valid value for xTimerPeriodInTicks. */ configASSERT( ( xTimerPeriodInTicks > 0 ) ); 8017364: 68bb ldr r3, [r7, #8] 8017366: 2b00 cmp r3, #0 8017368: d10b bne.n 8017382 __asm volatile 801736a: f04f 0350 mov.w r3, #80 @ 0x50 801736e: f383 8811 msr BASEPRI, r3 8017372: f3bf 8f6f isb sy 8017376: f3bf 8f4f dsb sy 801737a: 617b str r3, [r7, #20] } 801737c: bf00 nop 801737e: bf00 nop 8017380: e7fd b.n 801737e if( pxNewTimer != NULL ) 8017382: 6a7b ldr r3, [r7, #36] @ 0x24 8017384: 2b00 cmp r3, #0 8017386: d01e beq.n 80173c6 { /* Ensure the infrastructure used by the timer service task has been created/initialised. */ prvCheckForValidListAndQueue(); 8017388: f000 faf2 bl 8017970 /* Initialise the timer structure members using the function parameters. */ pxNewTimer->pcTimerName = pcTimerName; 801738c: 6a7b ldr r3, [r7, #36] @ 0x24 801738e: 68fa ldr r2, [r7, #12] 8017390: 601a str r2, [r3, #0] pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; 8017392: 6a7b ldr r3, [r7, #36] @ 0x24 8017394: 68ba ldr r2, [r7, #8] 8017396: 619a str r2, [r3, #24] pxNewTimer->pvTimerID = pvTimerID; 8017398: 6a7b ldr r3, [r7, #36] @ 0x24 801739a: 683a ldr r2, [r7, #0] 801739c: 61da str r2, [r3, #28] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 801739e: 6a7b ldr r3, [r7, #36] @ 0x24 80173a0: 6a3a ldr r2, [r7, #32] 80173a2: 621a str r2, [r3, #32] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 80173a4: 6a7b ldr r3, [r7, #36] @ 0x24 80173a6: 3304 adds r3, #4 80173a8: 4618 mov r0, r3 80173aa: f7fd fa91 bl 80148d0 if( uxAutoReload != pdFALSE ) 80173ae: 687b ldr r3, [r7, #4] 80173b0: 2b00 cmp r3, #0 80173b2: d008 beq.n 80173c6 { pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 80173b4: 6a7b ldr r3, [r7, #36] @ 0x24 80173b6: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80173ba: f043 0304 orr.w r3, r3, #4 80173be: b2da uxtb r2, r3 80173c0: 6a7b ldr r3, [r7, #36] @ 0x24 80173c2: f883 2028 strb.w r2, [r3, #40] @ 0x28 } traceTIMER_CREATE( pxNewTimer ); } } 80173c6: bf00 nop 80173c8: 3718 adds r7, #24 80173ca: 46bd mov sp, r7 80173cc: bd80 pop {r7, pc} ... 080173d0 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 80173d0: b580 push {r7, lr} 80173d2: b08a sub sp, #40 @ 0x28 80173d4: af00 add r7, sp, #0 80173d6: 60f8 str r0, [r7, #12] 80173d8: 60b9 str r1, [r7, #8] 80173da: 607a str r2, [r7, #4] 80173dc: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 80173de: 2300 movs r3, #0 80173e0: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 80173e2: 68fb ldr r3, [r7, #12] 80173e4: 2b00 cmp r3, #0 80173e6: d10b bne.n 8017400 __asm volatile 80173e8: f04f 0350 mov.w r3, #80 @ 0x50 80173ec: f383 8811 msr BASEPRI, r3 80173f0: f3bf 8f6f isb sy 80173f4: f3bf 8f4f dsb sy 80173f8: 623b str r3, [r7, #32] } 80173fa: bf00 nop 80173fc: bf00 nop 80173fe: e7fd b.n 80173fc /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8017400: 4b19 ldr r3, [pc, #100] @ (8017468 ) 8017402: 681b ldr r3, [r3, #0] 8017404: 2b00 cmp r3, #0 8017406: d02a beq.n 801745e { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 8017408: 68bb ldr r3, [r7, #8] 801740a: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 801740c: 687b ldr r3, [r7, #4] 801740e: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 8017410: 68fb ldr r3, [r7, #12] 8017412: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 8017414: 68bb ldr r3, [r7, #8] 8017416: 2b05 cmp r3, #5 8017418: dc18 bgt.n 801744c { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 801741a: f7ff fae1 bl 80169e0 801741e: 4603 mov r3, r0 8017420: 2b02 cmp r3, #2 8017422: d109 bne.n 8017438 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 8017424: 4b10 ldr r3, [pc, #64] @ (8017468 ) 8017426: 6818 ldr r0, [r3, #0] 8017428: f107 0110 add.w r1, r7, #16 801742c: 2300 movs r3, #0 801742e: 6b3a ldr r2, [r7, #48] @ 0x30 8017430: f7fd fce0 bl 8014df4 8017434: 6278 str r0, [r7, #36] @ 0x24 8017436: e012 b.n 801745e } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 8017438: 4b0b ldr r3, [pc, #44] @ (8017468 ) 801743a: 6818 ldr r0, [r3, #0] 801743c: f107 0110 add.w r1, r7, #16 8017440: 2300 movs r3, #0 8017442: 2200 movs r2, #0 8017444: f7fd fcd6 bl 8014df4 8017448: 6278 str r0, [r7, #36] @ 0x24 801744a: e008 b.n 801745e } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 801744c: 4b06 ldr r3, [pc, #24] @ (8017468 ) 801744e: 6818 ldr r0, [r3, #0] 8017450: f107 0110 add.w r1, r7, #16 8017454: 2300 movs r3, #0 8017456: 683a ldr r2, [r7, #0] 8017458: f7fd fdce bl 8014ff8 801745c: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 801745e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8017460: 4618 mov r0, r3 8017462: 3728 adds r7, #40 @ 0x28 8017464: 46bd mov sp, r7 8017466: bd80 pop {r7, pc} 8017468: 24002f28 .word 0x24002f28 0801746c : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 801746c: b580 push {r7, lr} 801746e: b088 sub sp, #32 8017470: af02 add r7, sp, #8 8017472: 6078 str r0, [r7, #4] 8017474: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8017476: 4b23 ldr r3, [pc, #140] @ (8017504 ) 8017478: 681b ldr r3, [r3, #0] 801747a: 68db ldr r3, [r3, #12] 801747c: 68db ldr r3, [r3, #12] 801747e: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8017480: 697b ldr r3, [r7, #20] 8017482: 3304 adds r3, #4 8017484: 4618 mov r0, r3 8017486: f7fd fa8d bl 80149a4 traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 801748a: 697b ldr r3, [r7, #20] 801748c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017490: f003 0304 and.w r3, r3, #4 8017494: 2b00 cmp r3, #0 8017496: d023 beq.n 80174e0 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 8017498: 697b ldr r3, [r7, #20] 801749a: 699a ldr r2, [r3, #24] 801749c: 687b ldr r3, [r7, #4] 801749e: 18d1 adds r1, r2, r3 80174a0: 687b ldr r3, [r7, #4] 80174a2: 683a ldr r2, [r7, #0] 80174a4: 6978 ldr r0, [r7, #20] 80174a6: f000 f8d5 bl 8017654 80174aa: 4603 mov r3, r0 80174ac: 2b00 cmp r3, #0 80174ae: d020 beq.n 80174f2 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 80174b0: 2300 movs r3, #0 80174b2: 9300 str r3, [sp, #0] 80174b4: 2300 movs r3, #0 80174b6: 687a ldr r2, [r7, #4] 80174b8: 2100 movs r1, #0 80174ba: 6978 ldr r0, [r7, #20] 80174bc: f7ff ff88 bl 80173d0 80174c0: 6138 str r0, [r7, #16] configASSERT( xResult ); 80174c2: 693b ldr r3, [r7, #16] 80174c4: 2b00 cmp r3, #0 80174c6: d114 bne.n 80174f2 __asm volatile 80174c8: f04f 0350 mov.w r3, #80 @ 0x50 80174cc: f383 8811 msr BASEPRI, r3 80174d0: f3bf 8f6f isb sy 80174d4: f3bf 8f4f dsb sy 80174d8: 60fb str r3, [r7, #12] } 80174da: bf00 nop 80174dc: bf00 nop 80174de: e7fd b.n 80174dc mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80174e0: 697b ldr r3, [r7, #20] 80174e2: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80174e6: f023 0301 bic.w r3, r3, #1 80174ea: b2da uxtb r2, r3 80174ec: 697b ldr r3, [r7, #20] 80174ee: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80174f2: 697b ldr r3, [r7, #20] 80174f4: 6a1b ldr r3, [r3, #32] 80174f6: 6978 ldr r0, [r7, #20] 80174f8: 4798 blx r3 } 80174fa: bf00 nop 80174fc: 3718 adds r7, #24 80174fe: 46bd mov sp, r7 8017500: bd80 pop {r7, pc} 8017502: bf00 nop 8017504: 24002f20 .word 0x24002f20 08017508 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8017508: b580 push {r7, lr} 801750a: b084 sub sp, #16 801750c: af00 add r7, sp, #0 801750e: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8017510: f107 0308 add.w r3, r7, #8 8017514: 4618 mov r0, r3 8017516: f000 f859 bl 80175cc 801751a: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 801751c: 68bb ldr r3, [r7, #8] 801751e: 4619 mov r1, r3 8017520: 68f8 ldr r0, [r7, #12] 8017522: f000 f805 bl 8017530 /* Empty the command queue. */ prvProcessReceivedCommands(); 8017526: f000 f8d7 bl 80176d8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 801752a: bf00 nop 801752c: e7f0 b.n 8017510 ... 08017530 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8017530: b580 push {r7, lr} 8017532: b084 sub sp, #16 8017534: af00 add r7, sp, #0 8017536: 6078 str r0, [r7, #4] 8017538: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 801753a: f7fe fe17 bl 801616c /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 801753e: f107 0308 add.w r3, r7, #8 8017542: 4618 mov r0, r3 8017544: f000 f866 bl 8017614 8017548: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 801754a: 68bb ldr r3, [r7, #8] 801754c: 2b00 cmp r3, #0 801754e: d130 bne.n 80175b2 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8017550: 683b ldr r3, [r7, #0] 8017552: 2b00 cmp r3, #0 8017554: d10a bne.n 801756c 8017556: 687a ldr r2, [r7, #4] 8017558: 68fb ldr r3, [r7, #12] 801755a: 429a cmp r2, r3 801755c: d806 bhi.n 801756c { ( void ) xTaskResumeAll(); 801755e: f7fe fe13 bl 8016188 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 8017562: 68f9 ldr r1, [r7, #12] 8017564: 6878 ldr r0, [r7, #4] 8017566: f7ff ff81 bl 801746c else { ( void ) xTaskResumeAll(); } } } 801756a: e024 b.n 80175b6 if( xListWasEmpty != pdFALSE ) 801756c: 683b ldr r3, [r7, #0] 801756e: 2b00 cmp r3, #0 8017570: d008 beq.n 8017584 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 8017572: 4b13 ldr r3, [pc, #76] @ (80175c0 ) 8017574: 681b ldr r3, [r3, #0] 8017576: 681b ldr r3, [r3, #0] 8017578: 2b00 cmp r3, #0 801757a: d101 bne.n 8017580 801757c: 2301 movs r3, #1 801757e: e000 b.n 8017582 8017580: 2300 movs r3, #0 8017582: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 8017584: 4b0f ldr r3, [pc, #60] @ (80175c4 ) 8017586: 6818 ldr r0, [r3, #0] 8017588: 687a ldr r2, [r7, #4] 801758a: 68fb ldr r3, [r7, #12] 801758c: 1ad3 subs r3, r2, r3 801758e: 683a ldr r2, [r7, #0] 8017590: 4619 mov r1, r3 8017592: f7fe f995 bl 80158c0 if( xTaskResumeAll() == pdFALSE ) 8017596: f7fe fdf7 bl 8016188 801759a: 4603 mov r3, r0 801759c: 2b00 cmp r3, #0 801759e: d10a bne.n 80175b6 portYIELD_WITHIN_API(); 80175a0: 4b09 ldr r3, [pc, #36] @ (80175c8 ) 80175a2: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80175a6: 601a str r2, [r3, #0] 80175a8: f3bf 8f4f dsb sy 80175ac: f3bf 8f6f isb sy } 80175b0: e001 b.n 80175b6 ( void ) xTaskResumeAll(); 80175b2: f7fe fde9 bl 8016188 } 80175b6: bf00 nop 80175b8: 3710 adds r7, #16 80175ba: 46bd mov sp, r7 80175bc: bd80 pop {r7, pc} 80175be: bf00 nop 80175c0: 24002f24 .word 0x24002f24 80175c4: 24002f28 .word 0x24002f28 80175c8: e000ed04 .word 0xe000ed04 080175cc : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 80175cc: b480 push {r7} 80175ce: b085 sub sp, #20 80175d0: af00 add r7, sp, #0 80175d2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 80175d4: 4b0e ldr r3, [pc, #56] @ (8017610 ) 80175d6: 681b ldr r3, [r3, #0] 80175d8: 681b ldr r3, [r3, #0] 80175da: 2b00 cmp r3, #0 80175dc: d101 bne.n 80175e2 80175de: 2201 movs r2, #1 80175e0: e000 b.n 80175e4 80175e2: 2200 movs r2, #0 80175e4: 687b ldr r3, [r7, #4] 80175e6: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 80175e8: 687b ldr r3, [r7, #4] 80175ea: 681b ldr r3, [r3, #0] 80175ec: 2b00 cmp r3, #0 80175ee: d105 bne.n 80175fc { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 80175f0: 4b07 ldr r3, [pc, #28] @ (8017610 ) 80175f2: 681b ldr r3, [r3, #0] 80175f4: 68db ldr r3, [r3, #12] 80175f6: 681b ldr r3, [r3, #0] 80175f8: 60fb str r3, [r7, #12] 80175fa: e001 b.n 8017600 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 80175fc: 2300 movs r3, #0 80175fe: 60fb str r3, [r7, #12] } return xNextExpireTime; 8017600: 68fb ldr r3, [r7, #12] } 8017602: 4618 mov r0, r3 8017604: 3714 adds r7, #20 8017606: 46bd mov sp, r7 8017608: f85d 7b04 ldr.w r7, [sp], #4 801760c: 4770 bx lr 801760e: bf00 nop 8017610: 24002f20 .word 0x24002f20 08017614 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 8017614: b580 push {r7, lr} 8017616: b084 sub sp, #16 8017618: af00 add r7, sp, #0 801761a: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 801761c: f7fe fe52 bl 80162c4 8017620: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 8017622: 4b0b ldr r3, [pc, #44] @ (8017650 ) 8017624: 681b ldr r3, [r3, #0] 8017626: 68fa ldr r2, [r7, #12] 8017628: 429a cmp r2, r3 801762a: d205 bcs.n 8017638 { prvSwitchTimerLists(); 801762c: f000 f93a bl 80178a4 *pxTimerListsWereSwitched = pdTRUE; 8017630: 687b ldr r3, [r7, #4] 8017632: 2201 movs r2, #1 8017634: 601a str r2, [r3, #0] 8017636: e002 b.n 801763e } else { *pxTimerListsWereSwitched = pdFALSE; 8017638: 687b ldr r3, [r7, #4] 801763a: 2200 movs r2, #0 801763c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 801763e: 4a04 ldr r2, [pc, #16] @ (8017650 ) 8017640: 68fb ldr r3, [r7, #12] 8017642: 6013 str r3, [r2, #0] return xTimeNow; 8017644: 68fb ldr r3, [r7, #12] } 8017646: 4618 mov r0, r3 8017648: 3710 adds r7, #16 801764a: 46bd mov sp, r7 801764c: bd80 pop {r7, pc} 801764e: bf00 nop 8017650: 24002f30 .word 0x24002f30 08017654 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 8017654: b580 push {r7, lr} 8017656: b086 sub sp, #24 8017658: af00 add r7, sp, #0 801765a: 60f8 str r0, [r7, #12] 801765c: 60b9 str r1, [r7, #8] 801765e: 607a str r2, [r7, #4] 8017660: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 8017662: 2300 movs r3, #0 8017664: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 8017666: 68fb ldr r3, [r7, #12] 8017668: 68ba ldr r2, [r7, #8] 801766a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 801766c: 68fb ldr r3, [r7, #12] 801766e: 68fa ldr r2, [r7, #12] 8017670: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 8017672: 68ba ldr r2, [r7, #8] 8017674: 687b ldr r3, [r7, #4] 8017676: 429a cmp r2, r3 8017678: d812 bhi.n 80176a0 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 801767a: 687a ldr r2, [r7, #4] 801767c: 683b ldr r3, [r7, #0] 801767e: 1ad2 subs r2, r2, r3 8017680: 68fb ldr r3, [r7, #12] 8017682: 699b ldr r3, [r3, #24] 8017684: 429a cmp r2, r3 8017686: d302 bcc.n 801768e { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8017688: 2301 movs r3, #1 801768a: 617b str r3, [r7, #20] 801768c: e01b b.n 80176c6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 801768e: 4b10 ldr r3, [pc, #64] @ (80176d0 ) 8017690: 681a ldr r2, [r3, #0] 8017692: 68fb ldr r3, [r7, #12] 8017694: 3304 adds r3, #4 8017696: 4619 mov r1, r3 8017698: 4610 mov r0, r2 801769a: f7fd f94a bl 8014932 801769e: e012 b.n 80176c6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 80176a0: 687a ldr r2, [r7, #4] 80176a2: 683b ldr r3, [r7, #0] 80176a4: 429a cmp r2, r3 80176a6: d206 bcs.n 80176b6 80176a8: 68ba ldr r2, [r7, #8] 80176aa: 683b ldr r3, [r7, #0] 80176ac: 429a cmp r2, r3 80176ae: d302 bcc.n 80176b6 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 80176b0: 2301 movs r3, #1 80176b2: 617b str r3, [r7, #20] 80176b4: e007 b.n 80176c6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80176b6: 4b07 ldr r3, [pc, #28] @ (80176d4 ) 80176b8: 681a ldr r2, [r3, #0] 80176ba: 68fb ldr r3, [r7, #12] 80176bc: 3304 adds r3, #4 80176be: 4619 mov r1, r3 80176c0: 4610 mov r0, r2 80176c2: f7fd f936 bl 8014932 } } return xProcessTimerNow; 80176c6: 697b ldr r3, [r7, #20] } 80176c8: 4618 mov r0, r3 80176ca: 3718 adds r7, #24 80176cc: 46bd mov sp, r7 80176ce: bd80 pop {r7, pc} 80176d0: 24002f24 .word 0x24002f24 80176d4: 24002f20 .word 0x24002f20 080176d8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 80176d8: b580 push {r7, lr} 80176da: b08e sub sp, #56 @ 0x38 80176dc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 80176de: e0ce b.n 801787e { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 80176e0: 687b ldr r3, [r7, #4] 80176e2: 2b00 cmp r3, #0 80176e4: da19 bge.n 801771a { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 80176e6: 1d3b adds r3, r7, #4 80176e8: 3304 adds r3, #4 80176ea: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 80176ec: 6afb ldr r3, [r7, #44] @ 0x2c 80176ee: 2b00 cmp r3, #0 80176f0: d10b bne.n 801770a __asm volatile 80176f2: f04f 0350 mov.w r3, #80 @ 0x50 80176f6: f383 8811 msr BASEPRI, r3 80176fa: f3bf 8f6f isb sy 80176fe: f3bf 8f4f dsb sy 8017702: 61fb str r3, [r7, #28] } 8017704: bf00 nop 8017706: bf00 nop 8017708: e7fd b.n 8017706 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 801770a: 6afb ldr r3, [r7, #44] @ 0x2c 801770c: 681b ldr r3, [r3, #0] 801770e: 6afa ldr r2, [r7, #44] @ 0x2c 8017710: 6850 ldr r0, [r2, #4] 8017712: 6afa ldr r2, [r7, #44] @ 0x2c 8017714: 6892 ldr r2, [r2, #8] 8017716: 4611 mov r1, r2 8017718: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 801771a: 687b ldr r3, [r7, #4] 801771c: 2b00 cmp r3, #0 801771e: f2c0 80ae blt.w 801787e { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 8017722: 68fb ldr r3, [r7, #12] 8017724: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 8017726: 6abb ldr r3, [r7, #40] @ 0x28 8017728: 695b ldr r3, [r3, #20] 801772a: 2b00 cmp r3, #0 801772c: d004 beq.n 8017738 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 801772e: 6abb ldr r3, [r7, #40] @ 0x28 8017730: 3304 adds r3, #4 8017732: 4618 mov r0, r3 8017734: f7fd f936 bl 80149a4 it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8017738: 463b mov r3, r7 801773a: 4618 mov r0, r3 801773c: f7ff ff6a bl 8017614 8017740: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 8017742: 687b ldr r3, [r7, #4] 8017744: 2b09 cmp r3, #9 8017746: f200 8097 bhi.w 8017878 801774a: a201 add r2, pc, #4 @ (adr r2, 8017750 ) 801774c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8017750: 08017779 .word 0x08017779 8017754: 08017779 .word 0x08017779 8017758: 08017779 .word 0x08017779 801775c: 080177ef .word 0x080177ef 8017760: 08017803 .word 0x08017803 8017764: 0801784f .word 0x0801784f 8017768: 08017779 .word 0x08017779 801776c: 08017779 .word 0x08017779 8017770: 080177ef .word 0x080177ef 8017774: 08017803 .word 0x08017803 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8017778: 6abb ldr r3, [r7, #40] @ 0x28 801777a: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801777e: f043 0301 orr.w r3, r3, #1 8017782: b2da uxtb r2, r3 8017784: 6abb ldr r3, [r7, #40] @ 0x28 8017786: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 801778a: 68ba ldr r2, [r7, #8] 801778c: 6abb ldr r3, [r7, #40] @ 0x28 801778e: 699b ldr r3, [r3, #24] 8017790: 18d1 adds r1, r2, r3 8017792: 68bb ldr r3, [r7, #8] 8017794: 6a7a ldr r2, [r7, #36] @ 0x24 8017796: 6ab8 ldr r0, [r7, #40] @ 0x28 8017798: f7ff ff5c bl 8017654 801779c: 4603 mov r3, r0 801779e: 2b00 cmp r3, #0 80177a0: d06c beq.n 801787c { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80177a2: 6abb ldr r3, [r7, #40] @ 0x28 80177a4: 6a1b ldr r3, [r3, #32] 80177a6: 6ab8 ldr r0, [r7, #40] @ 0x28 80177a8: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80177aa: 6abb ldr r3, [r7, #40] @ 0x28 80177ac: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80177b0: f003 0304 and.w r3, r3, #4 80177b4: 2b00 cmp r3, #0 80177b6: d061 beq.n 801787c { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 80177b8: 68ba ldr r2, [r7, #8] 80177ba: 6abb ldr r3, [r7, #40] @ 0x28 80177bc: 699b ldr r3, [r3, #24] 80177be: 441a add r2, r3 80177c0: 2300 movs r3, #0 80177c2: 9300 str r3, [sp, #0] 80177c4: 2300 movs r3, #0 80177c6: 2100 movs r1, #0 80177c8: 6ab8 ldr r0, [r7, #40] @ 0x28 80177ca: f7ff fe01 bl 80173d0 80177ce: 6238 str r0, [r7, #32] configASSERT( xResult ); 80177d0: 6a3b ldr r3, [r7, #32] 80177d2: 2b00 cmp r3, #0 80177d4: d152 bne.n 801787c __asm volatile 80177d6: f04f 0350 mov.w r3, #80 @ 0x50 80177da: f383 8811 msr BASEPRI, r3 80177de: f3bf 8f6f isb sy 80177e2: f3bf 8f4f dsb sy 80177e6: 61bb str r3, [r7, #24] } 80177e8: bf00 nop 80177ea: bf00 nop 80177ec: e7fd b.n 80177ea break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80177ee: 6abb ldr r3, [r7, #40] @ 0x28 80177f0: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80177f4: f023 0301 bic.w r3, r3, #1 80177f8: b2da uxtb r2, r3 80177fa: 6abb ldr r3, [r7, #40] @ 0x28 80177fc: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8017800: e03d b.n 801787e case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8017802: 6abb ldr r3, [r7, #40] @ 0x28 8017804: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017808: f043 0301 orr.w r3, r3, #1 801780c: b2da uxtb r2, r3 801780e: 6abb ldr r3, [r7, #40] @ 0x28 8017810: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 8017814: 68ba ldr r2, [r7, #8] 8017816: 6abb ldr r3, [r7, #40] @ 0x28 8017818: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 801781a: 6abb ldr r3, [r7, #40] @ 0x28 801781c: 699b ldr r3, [r3, #24] 801781e: 2b00 cmp r3, #0 8017820: d10b bne.n 801783a __asm volatile 8017822: f04f 0350 mov.w r3, #80 @ 0x50 8017826: f383 8811 msr BASEPRI, r3 801782a: f3bf 8f6f isb sy 801782e: f3bf 8f4f dsb sy 8017832: 617b str r3, [r7, #20] } 8017834: bf00 nop 8017836: bf00 nop 8017838: e7fd b.n 8017836 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 801783a: 6abb ldr r3, [r7, #40] @ 0x28 801783c: 699a ldr r2, [r3, #24] 801783e: 6a7b ldr r3, [r7, #36] @ 0x24 8017840: 18d1 adds r1, r2, r3 8017842: 6a7b ldr r3, [r7, #36] @ 0x24 8017844: 6a7a ldr r2, [r7, #36] @ 0x24 8017846: 6ab8 ldr r0, [r7, #40] @ 0x28 8017848: f7ff ff04 bl 8017654 break; 801784c: e017 b.n 801787e #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 801784e: 6abb ldr r3, [r7, #40] @ 0x28 8017850: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017854: f003 0302 and.w r3, r3, #2 8017858: 2b00 cmp r3, #0 801785a: d103 bne.n 8017864 { vPortFree( pxTimer ); 801785c: 6ab8 ldr r0, [r7, #40] @ 0x28 801785e: f000 fc33 bl 80180c8 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 8017862: e00c b.n 801787e pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 8017864: 6abb ldr r3, [r7, #40] @ 0x28 8017866: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801786a: f023 0301 bic.w r3, r3, #1 801786e: b2da uxtb r2, r3 8017870: 6abb ldr r3, [r7, #40] @ 0x28 8017872: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8017876: e002 b.n 801787e default : /* Don't expect to get here. */ break; 8017878: bf00 nop 801787a: e000 b.n 801787e break; 801787c: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 801787e: 4b08 ldr r3, [pc, #32] @ (80178a0 ) 8017880: 681b ldr r3, [r3, #0] 8017882: 1d39 adds r1, r7, #4 8017884: 2200 movs r2, #0 8017886: 4618 mov r0, r3 8017888: f7fd fc54 bl 8015134 801788c: 4603 mov r3, r0 801788e: 2b00 cmp r3, #0 8017890: f47f af26 bne.w 80176e0 } } } } 8017894: bf00 nop 8017896: bf00 nop 8017898: 3730 adds r7, #48 @ 0x30 801789a: 46bd mov sp, r7 801789c: bd80 pop {r7, pc} 801789e: bf00 nop 80178a0: 24002f28 .word 0x24002f28 080178a4 : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 80178a4: b580 push {r7, lr} 80178a6: b088 sub sp, #32 80178a8: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 80178aa: e049 b.n 8017940 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 80178ac: 4b2e ldr r3, [pc, #184] @ (8017968 ) 80178ae: 681b ldr r3, [r3, #0] 80178b0: 68db ldr r3, [r3, #12] 80178b2: 681b ldr r3, [r3, #0] 80178b4: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80178b6: 4b2c ldr r3, [pc, #176] @ (8017968 ) 80178b8: 681b ldr r3, [r3, #0] 80178ba: 68db ldr r3, [r3, #12] 80178bc: 68db ldr r3, [r3, #12] 80178be: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 80178c0: 68fb ldr r3, [r7, #12] 80178c2: 3304 adds r3, #4 80178c4: 4618 mov r0, r3 80178c6: f7fd f86d bl 80149a4 traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80178ca: 68fb ldr r3, [r7, #12] 80178cc: 6a1b ldr r3, [r3, #32] 80178ce: 68f8 ldr r0, [r7, #12] 80178d0: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80178d2: 68fb ldr r3, [r7, #12] 80178d4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80178d8: f003 0304 and.w r3, r3, #4 80178dc: 2b00 cmp r3, #0 80178de: d02f beq.n 8017940 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 80178e0: 68fb ldr r3, [r7, #12] 80178e2: 699b ldr r3, [r3, #24] 80178e4: 693a ldr r2, [r7, #16] 80178e6: 4413 add r3, r2 80178e8: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 80178ea: 68ba ldr r2, [r7, #8] 80178ec: 693b ldr r3, [r7, #16] 80178ee: 429a cmp r2, r3 80178f0: d90e bls.n 8017910 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 80178f2: 68fb ldr r3, [r7, #12] 80178f4: 68ba ldr r2, [r7, #8] 80178f6: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 80178f8: 68fb ldr r3, [r7, #12] 80178fa: 68fa ldr r2, [r7, #12] 80178fc: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80178fe: 4b1a ldr r3, [pc, #104] @ (8017968 ) 8017900: 681a ldr r2, [r3, #0] 8017902: 68fb ldr r3, [r7, #12] 8017904: 3304 adds r3, #4 8017906: 4619 mov r1, r3 8017908: 4610 mov r0, r2 801790a: f7fd f812 bl 8014932 801790e: e017 b.n 8017940 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8017910: 2300 movs r3, #0 8017912: 9300 str r3, [sp, #0] 8017914: 2300 movs r3, #0 8017916: 693a ldr r2, [r7, #16] 8017918: 2100 movs r1, #0 801791a: 68f8 ldr r0, [r7, #12] 801791c: f7ff fd58 bl 80173d0 8017920: 6078 str r0, [r7, #4] configASSERT( xResult ); 8017922: 687b ldr r3, [r7, #4] 8017924: 2b00 cmp r3, #0 8017926: d10b bne.n 8017940 __asm volatile 8017928: f04f 0350 mov.w r3, #80 @ 0x50 801792c: f383 8811 msr BASEPRI, r3 8017930: f3bf 8f6f isb sy 8017934: f3bf 8f4f dsb sy 8017938: 603b str r3, [r7, #0] } 801793a: bf00 nop 801793c: bf00 nop 801793e: e7fd b.n 801793c while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8017940: 4b09 ldr r3, [pc, #36] @ (8017968 ) 8017942: 681b ldr r3, [r3, #0] 8017944: 681b ldr r3, [r3, #0] 8017946: 2b00 cmp r3, #0 8017948: d1b0 bne.n 80178ac { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 801794a: 4b07 ldr r3, [pc, #28] @ (8017968 ) 801794c: 681b ldr r3, [r3, #0] 801794e: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8017950: 4b06 ldr r3, [pc, #24] @ (801796c ) 8017952: 681b ldr r3, [r3, #0] 8017954: 4a04 ldr r2, [pc, #16] @ (8017968 ) 8017956: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8017958: 4a04 ldr r2, [pc, #16] @ (801796c ) 801795a: 697b ldr r3, [r7, #20] 801795c: 6013 str r3, [r2, #0] } 801795e: bf00 nop 8017960: 3718 adds r7, #24 8017962: 46bd mov sp, r7 8017964: bd80 pop {r7, pc} 8017966: bf00 nop 8017968: 24002f20 .word 0x24002f20 801796c: 24002f24 .word 0x24002f24 08017970 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8017970: b580 push {r7, lr} 8017972: b082 sub sp, #8 8017974: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 8017976: f000 f9b7 bl 8017ce8 { if( xTimerQueue == NULL ) 801797a: 4b15 ldr r3, [pc, #84] @ (80179d0 ) 801797c: 681b ldr r3, [r3, #0] 801797e: 2b00 cmp r3, #0 8017980: d120 bne.n 80179c4 { vListInitialise( &xActiveTimerList1 ); 8017982: 4814 ldr r0, [pc, #80] @ (80179d4 ) 8017984: f7fc ff84 bl 8014890 vListInitialise( &xActiveTimerList2 ); 8017988: 4813 ldr r0, [pc, #76] @ (80179d8 ) 801798a: f7fc ff81 bl 8014890 pxCurrentTimerList = &xActiveTimerList1; 801798e: 4b13 ldr r3, [pc, #76] @ (80179dc ) 8017990: 4a10 ldr r2, [pc, #64] @ (80179d4 ) 8017992: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 8017994: 4b12 ldr r3, [pc, #72] @ (80179e0 ) 8017996: 4a10 ldr r2, [pc, #64] @ (80179d8 ) 8017998: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 801799a: 2300 movs r3, #0 801799c: 9300 str r3, [sp, #0] 801799e: 4b11 ldr r3, [pc, #68] @ (80179e4 ) 80179a0: 4a11 ldr r2, [pc, #68] @ (80179e8 ) 80179a2: 2110 movs r1, #16 80179a4: 200a movs r0, #10 80179a6: f7fd f891 bl 8014acc 80179aa: 4603 mov r3, r0 80179ac: 4a08 ldr r2, [pc, #32] @ (80179d0 ) 80179ae: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 80179b0: 4b07 ldr r3, [pc, #28] @ (80179d0 ) 80179b2: 681b ldr r3, [r3, #0] 80179b4: 2b00 cmp r3, #0 80179b6: d005 beq.n 80179c4 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 80179b8: 4b05 ldr r3, [pc, #20] @ (80179d0 ) 80179ba: 681b ldr r3, [r3, #0] 80179bc: 490b ldr r1, [pc, #44] @ (80179ec ) 80179be: 4618 mov r0, r3 80179c0: f7fd ff54 bl 801586c else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80179c4: f000 f9c2 bl 8017d4c } 80179c8: bf00 nop 80179ca: 46bd mov sp, r7 80179cc: bd80 pop {r7, pc} 80179ce: bf00 nop 80179d0: 24002f28 .word 0x24002f28 80179d4: 24002ef8 .word 0x24002ef8 80179d8: 24002f0c .word 0x24002f0c 80179dc: 24002f20 .word 0x24002f20 80179e0: 24002f24 .word 0x24002f24 80179e4: 24002fd4 .word 0x24002fd4 80179e8: 24002f34 .word 0x24002f34 80179ec: 08018690 .word 0x08018690 080179f0 : /*-----------------------------------------------------------*/ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { 80179f0: b580 push {r7, lr} 80179f2: b086 sub sp, #24 80179f4: af00 add r7, sp, #0 80179f6: 6078 str r0, [r7, #4] BaseType_t xReturn; Timer_t *pxTimer = xTimer; 80179f8: 687b ldr r3, [r7, #4] 80179fa: 613b str r3, [r7, #16] configASSERT( xTimer ); 80179fc: 687b ldr r3, [r7, #4] 80179fe: 2b00 cmp r3, #0 8017a00: d10b bne.n 8017a1a __asm volatile 8017a02: f04f 0350 mov.w r3, #80 @ 0x50 8017a06: f383 8811 msr BASEPRI, r3 8017a0a: f3bf 8f6f isb sy 8017a0e: f3bf 8f4f dsb sy 8017a12: 60fb str r3, [r7, #12] } 8017a14: bf00 nop 8017a16: bf00 nop 8017a18: e7fd b.n 8017a16 /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 8017a1a: f000 f965 bl 8017ce8 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 8017a1e: 693b ldr r3, [r7, #16] 8017a20: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017a24: f003 0301 and.w r3, r3, #1 8017a28: 2b00 cmp r3, #0 8017a2a: d102 bne.n 8017a32 { xReturn = pdFALSE; 8017a2c: 2300 movs r3, #0 8017a2e: 617b str r3, [r7, #20] 8017a30: e001 b.n 8017a36 } else { xReturn = pdTRUE; 8017a32: 2301 movs r3, #1 8017a34: 617b str r3, [r7, #20] } } taskEXIT_CRITICAL(); 8017a36: f000 f989 bl 8017d4c return xReturn; 8017a3a: 697b ldr r3, [r7, #20] } /*lint !e818 Can't be pointer to const due to the typedef. */ 8017a3c: 4618 mov r0, r3 8017a3e: 3718 adds r7, #24 8017a40: 46bd mov sp, r7 8017a42: bd80 pop {r7, pc} 08017a44 : /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { 8017a44: b580 push {r7, lr} 8017a46: b086 sub sp, #24 8017a48: af00 add r7, sp, #0 8017a4a: 6078 str r0, [r7, #4] Timer_t * const pxTimer = xTimer; 8017a4c: 687b ldr r3, [r7, #4] 8017a4e: 617b str r3, [r7, #20] void *pvReturn; configASSERT( xTimer ); 8017a50: 687b ldr r3, [r7, #4] 8017a52: 2b00 cmp r3, #0 8017a54: d10b bne.n 8017a6e __asm volatile 8017a56: f04f 0350 mov.w r3, #80 @ 0x50 8017a5a: f383 8811 msr BASEPRI, r3 8017a5e: f3bf 8f6f isb sy 8017a62: f3bf 8f4f dsb sy 8017a66: 60fb str r3, [r7, #12] } 8017a68: bf00 nop 8017a6a: bf00 nop 8017a6c: e7fd b.n 8017a6a taskENTER_CRITICAL(); 8017a6e: f000 f93b bl 8017ce8 { pvReturn = pxTimer->pvTimerID; 8017a72: 697b ldr r3, [r7, #20] 8017a74: 69db ldr r3, [r3, #28] 8017a76: 613b str r3, [r7, #16] } taskEXIT_CRITICAL(); 8017a78: f000 f968 bl 8017d4c return pvReturn; 8017a7c: 693b ldr r3, [r7, #16] } 8017a7e: 4618 mov r0, r3 8017a80: 3718 adds r7, #24 8017a82: 46bd mov sp, r7 8017a84: bd80 pop {r7, pc} ... 08017a88 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 8017a88: b480 push {r7} 8017a8a: b085 sub sp, #20 8017a8c: af00 add r7, sp, #0 8017a8e: 60f8 str r0, [r7, #12] 8017a90: 60b9 str r1, [r7, #8] 8017a92: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 8017a94: 68fb ldr r3, [r7, #12] 8017a96: 3b04 subs r3, #4 8017a98: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 8017a9a: 68fb ldr r3, [r7, #12] 8017a9c: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8017aa0: 601a str r2, [r3, #0] pxTopOfStack--; 8017aa2: 68fb ldr r3, [r7, #12] 8017aa4: 3b04 subs r3, #4 8017aa6: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 8017aa8: 68bb ldr r3, [r7, #8] 8017aaa: f023 0201 bic.w r2, r3, #1 8017aae: 68fb ldr r3, [r7, #12] 8017ab0: 601a str r2, [r3, #0] pxTopOfStack--; 8017ab2: 68fb ldr r3, [r7, #12] 8017ab4: 3b04 subs r3, #4 8017ab6: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 8017ab8: 4a0c ldr r2, [pc, #48] @ (8017aec ) 8017aba: 68fb ldr r3, [r7, #12] 8017abc: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8017abe: 68fb ldr r3, [r7, #12] 8017ac0: 3b14 subs r3, #20 8017ac2: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8017ac4: 687a ldr r2, [r7, #4] 8017ac6: 68fb ldr r3, [r7, #12] 8017ac8: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 8017aca: 68fb ldr r3, [r7, #12] 8017acc: 3b04 subs r3, #4 8017ace: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8017ad0: 68fb ldr r3, [r7, #12] 8017ad2: f06f 0202 mvn.w r2, #2 8017ad6: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8017ad8: 68fb ldr r3, [r7, #12] 8017ada: 3b20 subs r3, #32 8017adc: 60fb str r3, [r7, #12] return pxTopOfStack; 8017ade: 68fb ldr r3, [r7, #12] } 8017ae0: 4618 mov r0, r3 8017ae2: 3714 adds r7, #20 8017ae4: 46bd mov sp, r7 8017ae6: f85d 7b04 ldr.w r7, [sp], #4 8017aea: 4770 bx lr 8017aec: 08017af1 .word 0x08017af1 08017af0 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8017af0: b480 push {r7} 8017af2: b085 sub sp, #20 8017af4: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8017af6: 2300 movs r3, #0 8017af8: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8017afa: 4b13 ldr r3, [pc, #76] @ (8017b48 ) 8017afc: 681b ldr r3, [r3, #0] 8017afe: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017b02: d00b beq.n 8017b1c __asm volatile 8017b04: f04f 0350 mov.w r3, #80 @ 0x50 8017b08: f383 8811 msr BASEPRI, r3 8017b0c: f3bf 8f6f isb sy 8017b10: f3bf 8f4f dsb sy 8017b14: 60fb str r3, [r7, #12] } 8017b16: bf00 nop 8017b18: bf00 nop 8017b1a: e7fd b.n 8017b18 __asm volatile 8017b1c: f04f 0350 mov.w r3, #80 @ 0x50 8017b20: f383 8811 msr BASEPRI, r3 8017b24: f3bf 8f6f isb sy 8017b28: f3bf 8f4f dsb sy 8017b2c: 60bb str r3, [r7, #8] } 8017b2e: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8017b30: bf00 nop 8017b32: 687b ldr r3, [r7, #4] 8017b34: 2b00 cmp r3, #0 8017b36: d0fc beq.n 8017b32 about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 8017b38: bf00 nop 8017b3a: bf00 nop 8017b3c: 3714 adds r7, #20 8017b3e: 46bd mov sp, r7 8017b40: f85d 7b04 ldr.w r7, [sp], #4 8017b44: 4770 bx lr 8017b46: bf00 nop 8017b48: 24000044 .word 0x24000044 8017b4c: 00000000 .word 0x00000000 08017b50 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8017b50: 4b07 ldr r3, [pc, #28] @ (8017b70 ) 8017b52: 6819 ldr r1, [r3, #0] 8017b54: 6808 ldr r0, [r1, #0] 8017b56: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017b5a: f380 8809 msr PSP, r0 8017b5e: f3bf 8f6f isb sy 8017b62: f04f 0000 mov.w r0, #0 8017b66: f380 8811 msr BASEPRI, r0 8017b6a: 4770 bx lr 8017b6c: f3af 8000 nop.w 08017b70 : 8017b70: 240029f8 .word 0x240029f8 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8017b74: bf00 nop 8017b76: bf00 nop 08017b78 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 8017b78: 4808 ldr r0, [pc, #32] @ (8017b9c ) 8017b7a: 6800 ldr r0, [r0, #0] 8017b7c: 6800 ldr r0, [r0, #0] 8017b7e: f380 8808 msr MSP, r0 8017b82: f04f 0000 mov.w r0, #0 8017b86: f380 8814 msr CONTROL, r0 8017b8a: b662 cpsie i 8017b8c: b661 cpsie f 8017b8e: f3bf 8f4f dsb sy 8017b92: f3bf 8f6f isb sy 8017b96: df00 svc 0 8017b98: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 8017b9a: bf00 nop 8017b9c: e000ed08 .word 0xe000ed08 08017ba0 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 8017ba0: b580 push {r7, lr} 8017ba2: b086 sub sp, #24 8017ba4: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 8017ba6: 4b47 ldr r3, [pc, #284] @ (8017cc4 ) 8017ba8: 681b ldr r3, [r3, #0] 8017baa: 4a47 ldr r2, [pc, #284] @ (8017cc8 ) 8017bac: 4293 cmp r3, r2 8017bae: d10b bne.n 8017bc8 __asm volatile 8017bb0: f04f 0350 mov.w r3, #80 @ 0x50 8017bb4: f383 8811 msr BASEPRI, r3 8017bb8: f3bf 8f6f isb sy 8017bbc: f3bf 8f4f dsb sy 8017bc0: 613b str r3, [r7, #16] } 8017bc2: bf00 nop 8017bc4: bf00 nop 8017bc6: e7fd b.n 8017bc4 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 8017bc8: 4b3e ldr r3, [pc, #248] @ (8017cc4 ) 8017bca: 681b ldr r3, [r3, #0] 8017bcc: 4a3f ldr r2, [pc, #252] @ (8017ccc ) 8017bce: 4293 cmp r3, r2 8017bd0: d10b bne.n 8017bea __asm volatile 8017bd2: f04f 0350 mov.w r3, #80 @ 0x50 8017bd6: f383 8811 msr BASEPRI, r3 8017bda: f3bf 8f6f isb sy 8017bde: f3bf 8f4f dsb sy 8017be2: 60fb str r3, [r7, #12] } 8017be4: bf00 nop 8017be6: bf00 nop 8017be8: e7fd b.n 8017be6 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 8017bea: 4b39 ldr r3, [pc, #228] @ (8017cd0 ) 8017bec: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 8017bee: 697b ldr r3, [r7, #20] 8017bf0: 781b ldrb r3, [r3, #0] 8017bf2: b2db uxtb r3, r3 8017bf4: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8017bf6: 697b ldr r3, [r7, #20] 8017bf8: 22ff movs r2, #255 @ 0xff 8017bfa: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 8017bfc: 697b ldr r3, [r7, #20] 8017bfe: 781b ldrb r3, [r3, #0] 8017c00: b2db uxtb r3, r3 8017c02: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8017c04: 78fb ldrb r3, [r7, #3] 8017c06: b2db uxtb r3, r3 8017c08: f003 0350 and.w r3, r3, #80 @ 0x50 8017c0c: b2da uxtb r2, r3 8017c0e: 4b31 ldr r3, [pc, #196] @ (8017cd4 ) 8017c10: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8017c12: 4b31 ldr r3, [pc, #196] @ (8017cd8 ) 8017c14: 2207 movs r2, #7 8017c16: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017c18: e009 b.n 8017c2e { ulMaxPRIGROUPValue--; 8017c1a: 4b2f ldr r3, [pc, #188] @ (8017cd8 ) 8017c1c: 681b ldr r3, [r3, #0] 8017c1e: 3b01 subs r3, #1 8017c20: 4a2d ldr r2, [pc, #180] @ (8017cd8 ) 8017c22: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8017c24: 78fb ldrb r3, [r7, #3] 8017c26: b2db uxtb r3, r3 8017c28: 005b lsls r3, r3, #1 8017c2a: b2db uxtb r3, r3 8017c2c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017c2e: 78fb ldrb r3, [r7, #3] 8017c30: b2db uxtb r3, r3 8017c32: f003 0380 and.w r3, r3, #128 @ 0x80 8017c36: 2b80 cmp r3, #128 @ 0x80 8017c38: d0ef beq.n 8017c1a #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 8017c3a: 4b27 ldr r3, [pc, #156] @ (8017cd8 ) 8017c3c: 681b ldr r3, [r3, #0] 8017c3e: f1c3 0307 rsb r3, r3, #7 8017c42: 2b04 cmp r3, #4 8017c44: d00b beq.n 8017c5e __asm volatile 8017c46: f04f 0350 mov.w r3, #80 @ 0x50 8017c4a: f383 8811 msr BASEPRI, r3 8017c4e: f3bf 8f6f isb sy 8017c52: f3bf 8f4f dsb sy 8017c56: 60bb str r3, [r7, #8] } 8017c58: bf00 nop 8017c5a: bf00 nop 8017c5c: e7fd b.n 8017c5a } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 8017c5e: 4b1e ldr r3, [pc, #120] @ (8017cd8 ) 8017c60: 681b ldr r3, [r3, #0] 8017c62: 021b lsls r3, r3, #8 8017c64: 4a1c ldr r2, [pc, #112] @ (8017cd8 ) 8017c66: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8017c68: 4b1b ldr r3, [pc, #108] @ (8017cd8 ) 8017c6a: 681b ldr r3, [r3, #0] 8017c6c: f403 63e0 and.w r3, r3, #1792 @ 0x700 8017c70: 4a19 ldr r2, [pc, #100] @ (8017cd8 ) 8017c72: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 8017c74: 687b ldr r3, [r7, #4] 8017c76: b2da uxtb r2, r3 8017c78: 697b ldr r3, [r7, #20] 8017c7a: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 8017c7c: 4b17 ldr r3, [pc, #92] @ (8017cdc ) 8017c7e: 681b ldr r3, [r3, #0] 8017c80: 4a16 ldr r2, [pc, #88] @ (8017cdc ) 8017c82: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8017c86: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 8017c88: 4b14 ldr r3, [pc, #80] @ (8017cdc ) 8017c8a: 681b ldr r3, [r3, #0] 8017c8c: 4a13 ldr r2, [pc, #76] @ (8017cdc ) 8017c8e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 8017c92: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 8017c94: f000 f8da bl 8017e4c /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8017c98: 4b11 ldr r3, [pc, #68] @ (8017ce0 ) 8017c9a: 2200 movs r2, #0 8017c9c: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 8017c9e: f000 f8f9 bl 8017e94 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8017ca2: 4b10 ldr r3, [pc, #64] @ (8017ce4 ) 8017ca4: 681b ldr r3, [r3, #0] 8017ca6: 4a0f ldr r2, [pc, #60] @ (8017ce4 ) 8017ca8: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 8017cac: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 8017cae: f7ff ff63 bl 8017b78 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 8017cb2: f7fe fbd1 bl 8016458 prvTaskExitError(); 8017cb6: f7ff ff1b bl 8017af0 /* Should not get here! */ return 0; 8017cba: 2300 movs r3, #0 } 8017cbc: 4618 mov r0, r3 8017cbe: 3718 adds r7, #24 8017cc0: 46bd mov sp, r7 8017cc2: bd80 pop {r7, pc} 8017cc4: e000ed00 .word 0xe000ed00 8017cc8: 410fc271 .word 0x410fc271 8017ccc: 410fc270 .word 0x410fc270 8017cd0: e000e400 .word 0xe000e400 8017cd4: 24003024 .word 0x24003024 8017cd8: 24003028 .word 0x24003028 8017cdc: e000ed20 .word 0xe000ed20 8017ce0: 24000044 .word 0x24000044 8017ce4: e000ef34 .word 0xe000ef34 08017ce8 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8017ce8: b480 push {r7} 8017cea: b083 sub sp, #12 8017cec: af00 add r7, sp, #0 __asm volatile 8017cee: f04f 0350 mov.w r3, #80 @ 0x50 8017cf2: f383 8811 msr BASEPRI, r3 8017cf6: f3bf 8f6f isb sy 8017cfa: f3bf 8f4f dsb sy 8017cfe: 607b str r3, [r7, #4] } 8017d00: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8017d02: 4b10 ldr r3, [pc, #64] @ (8017d44 ) 8017d04: 681b ldr r3, [r3, #0] 8017d06: 3301 adds r3, #1 8017d08: 4a0e ldr r2, [pc, #56] @ (8017d44 ) 8017d0a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8017d0c: 4b0d ldr r3, [pc, #52] @ (8017d44 ) 8017d0e: 681b ldr r3, [r3, #0] 8017d10: 2b01 cmp r3, #1 8017d12: d110 bne.n 8017d36 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8017d14: 4b0c ldr r3, [pc, #48] @ (8017d48 ) 8017d16: 681b ldr r3, [r3, #0] 8017d18: b2db uxtb r3, r3 8017d1a: 2b00 cmp r3, #0 8017d1c: d00b beq.n 8017d36 __asm volatile 8017d1e: f04f 0350 mov.w r3, #80 @ 0x50 8017d22: f383 8811 msr BASEPRI, r3 8017d26: f3bf 8f6f isb sy 8017d2a: f3bf 8f4f dsb sy 8017d2e: 603b str r3, [r7, #0] } 8017d30: bf00 nop 8017d32: bf00 nop 8017d34: e7fd b.n 8017d32 } } 8017d36: bf00 nop 8017d38: 370c adds r7, #12 8017d3a: 46bd mov sp, r7 8017d3c: f85d 7b04 ldr.w r7, [sp], #4 8017d40: 4770 bx lr 8017d42: bf00 nop 8017d44: 24000044 .word 0x24000044 8017d48: e000ed04 .word 0xe000ed04 08017d4c : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8017d4c: b480 push {r7} 8017d4e: b083 sub sp, #12 8017d50: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8017d52: 4b12 ldr r3, [pc, #72] @ (8017d9c ) 8017d54: 681b ldr r3, [r3, #0] 8017d56: 2b00 cmp r3, #0 8017d58: d10b bne.n 8017d72 __asm volatile 8017d5a: f04f 0350 mov.w r3, #80 @ 0x50 8017d5e: f383 8811 msr BASEPRI, r3 8017d62: f3bf 8f6f isb sy 8017d66: f3bf 8f4f dsb sy 8017d6a: 607b str r3, [r7, #4] } 8017d6c: bf00 nop 8017d6e: bf00 nop 8017d70: e7fd b.n 8017d6e uxCriticalNesting--; 8017d72: 4b0a ldr r3, [pc, #40] @ (8017d9c ) 8017d74: 681b ldr r3, [r3, #0] 8017d76: 3b01 subs r3, #1 8017d78: 4a08 ldr r2, [pc, #32] @ (8017d9c ) 8017d7a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8017d7c: 4b07 ldr r3, [pc, #28] @ (8017d9c ) 8017d7e: 681b ldr r3, [r3, #0] 8017d80: 2b00 cmp r3, #0 8017d82: d105 bne.n 8017d90 8017d84: 2300 movs r3, #0 8017d86: 603b str r3, [r7, #0] __asm volatile 8017d88: 683b ldr r3, [r7, #0] 8017d8a: f383 8811 msr BASEPRI, r3 } 8017d8e: bf00 nop { portENABLE_INTERRUPTS(); } } 8017d90: bf00 nop 8017d92: 370c adds r7, #12 8017d94: 46bd mov sp, r7 8017d96: f85d 7b04 ldr.w r7, [sp], #4 8017d9a: 4770 bx lr 8017d9c: 24000044 .word 0x24000044 08017da0 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8017da0: f3ef 8009 mrs r0, PSP 8017da4: f3bf 8f6f isb sy 8017da8: 4b15 ldr r3, [pc, #84] @ (8017e00 ) 8017daa: 681a ldr r2, [r3, #0] 8017dac: f01e 0f10 tst.w lr, #16 8017db0: bf08 it eq 8017db2: ed20 8a10 vstmdbeq r0!, {s16-s31} 8017db6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017dba: 6010 str r0, [r2, #0] 8017dbc: e92d 0009 stmdb sp!, {r0, r3} 8017dc0: f04f 0050 mov.w r0, #80 @ 0x50 8017dc4: f380 8811 msr BASEPRI, r0 8017dc8: f3bf 8f4f dsb sy 8017dcc: f3bf 8f6f isb sy 8017dd0: f7fe fb42 bl 8016458 8017dd4: f04f 0000 mov.w r0, #0 8017dd8: f380 8811 msr BASEPRI, r0 8017ddc: bc09 pop {r0, r3} 8017dde: 6819 ldr r1, [r3, #0] 8017de0: 6808 ldr r0, [r1, #0] 8017de2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017de6: f01e 0f10 tst.w lr, #16 8017dea: bf08 it eq 8017dec: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8017df0: f380 8809 msr PSP, r0 8017df4: f3bf 8f6f isb sy 8017df8: 4770 bx lr 8017dfa: bf00 nop 8017dfc: f3af 8000 nop.w 08017e00 : 8017e00: 240029f8 .word 0x240029f8 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8017e04: bf00 nop 8017e06: bf00 nop 08017e08 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017e08: b580 push {r7, lr} 8017e0a: b082 sub sp, #8 8017e0c: af00 add r7, sp, #0 __asm volatile 8017e0e: f04f 0350 mov.w r3, #80 @ 0x50 8017e12: f383 8811 msr BASEPRI, r3 8017e16: f3bf 8f6f isb sy 8017e1a: f3bf 8f4f dsb sy 8017e1e: 607b str r3, [r7, #4] } 8017e20: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8017e22: f7fe fa5f bl 80162e4 8017e26: 4603 mov r3, r0 8017e28: 2b00 cmp r3, #0 8017e2a: d003 beq.n 8017e34 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 8017e2c: 4b06 ldr r3, [pc, #24] @ (8017e48 ) 8017e2e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8017e32: 601a str r2, [r3, #0] 8017e34: 2300 movs r3, #0 8017e36: 603b str r3, [r7, #0] __asm volatile 8017e38: 683b ldr r3, [r7, #0] 8017e3a: f383 8811 msr BASEPRI, r3 } 8017e3e: bf00 nop } } portENABLE_INTERRUPTS(); } 8017e40: bf00 nop 8017e42: 3708 adds r7, #8 8017e44: 46bd mov sp, r7 8017e46: bd80 pop {r7, pc} 8017e48: e000ed04 .word 0xe000ed04 08017e4c : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 8017e4c: b480 push {r7} 8017e4e: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8017e50: 4b0b ldr r3, [pc, #44] @ (8017e80 ) 8017e52: 2200 movs r2, #0 8017e54: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8017e56: 4b0b ldr r3, [pc, #44] @ (8017e84 ) 8017e58: 2200 movs r2, #0 8017e5a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 8017e5c: 4b0a ldr r3, [pc, #40] @ (8017e88 ) 8017e5e: 681b ldr r3, [r3, #0] 8017e60: 4a0a ldr r2, [pc, #40] @ (8017e8c ) 8017e62: fba2 2303 umull r2, r3, r2, r3 8017e66: 099b lsrs r3, r3, #6 8017e68: 4a09 ldr r2, [pc, #36] @ (8017e90 ) 8017e6a: 3b01 subs r3, #1 8017e6c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 8017e6e: 4b04 ldr r3, [pc, #16] @ (8017e80 ) 8017e70: 2207 movs r2, #7 8017e72: 601a str r2, [r3, #0] } 8017e74: bf00 nop 8017e76: 46bd mov sp, r7 8017e78: f85d 7b04 ldr.w r7, [sp], #4 8017e7c: 4770 bx lr 8017e7e: bf00 nop 8017e80: e000e010 .word 0xe000e010 8017e84: e000e018 .word 0xe000e018 8017e88: 24000034 .word 0x24000034 8017e8c: 10624dd3 .word 0x10624dd3 8017e90: e000e014 .word 0xe000e014 08017e94 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8017e94: f8df 000c ldr.w r0, [pc, #12] @ 8017ea4 8017e98: 6801 ldr r1, [r0, #0] 8017e9a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8017e9e: 6001 str r1, [r0, #0] 8017ea0: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 8017ea2: bf00 nop 8017ea4: e000ed88 .word 0xe000ed88 08017ea8 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8017ea8: b480 push {r7} 8017eaa: b085 sub sp, #20 8017eac: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 8017eae: f3ef 8305 mrs r3, IPSR 8017eb2: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8017eb4: 68fb ldr r3, [r7, #12] 8017eb6: 2b0f cmp r3, #15 8017eb8: d915 bls.n 8017ee6 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 8017eba: 4a18 ldr r2, [pc, #96] @ (8017f1c ) 8017ebc: 68fb ldr r3, [r7, #12] 8017ebe: 4413 add r3, r2 8017ec0: 781b ldrb r3, [r3, #0] 8017ec2: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8017ec4: 4b16 ldr r3, [pc, #88] @ (8017f20 ) 8017ec6: 781b ldrb r3, [r3, #0] 8017ec8: 7afa ldrb r2, [r7, #11] 8017eca: 429a cmp r2, r3 8017ecc: d20b bcs.n 8017ee6 __asm volatile 8017ece: f04f 0350 mov.w r3, #80 @ 0x50 8017ed2: f383 8811 msr BASEPRI, r3 8017ed6: f3bf 8f6f isb sy 8017eda: f3bf 8f4f dsb sy 8017ede: 607b str r3, [r7, #4] } 8017ee0: bf00 nop 8017ee2: bf00 nop 8017ee4: e7fd b.n 8017ee2 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8017ee6: 4b0f ldr r3, [pc, #60] @ (8017f24 ) 8017ee8: 681b ldr r3, [r3, #0] 8017eea: f403 62e0 and.w r2, r3, #1792 @ 0x700 8017eee: 4b0e ldr r3, [pc, #56] @ (8017f28 ) 8017ef0: 681b ldr r3, [r3, #0] 8017ef2: 429a cmp r2, r3 8017ef4: d90b bls.n 8017f0e __asm volatile 8017ef6: f04f 0350 mov.w r3, #80 @ 0x50 8017efa: f383 8811 msr BASEPRI, r3 8017efe: f3bf 8f6f isb sy 8017f02: f3bf 8f4f dsb sy 8017f06: 603b str r3, [r7, #0] } 8017f08: bf00 nop 8017f0a: bf00 nop 8017f0c: e7fd b.n 8017f0a } 8017f0e: bf00 nop 8017f10: 3714 adds r7, #20 8017f12: 46bd mov sp, r7 8017f14: f85d 7b04 ldr.w r7, [sp], #4 8017f18: 4770 bx lr 8017f1a: bf00 nop 8017f1c: e000e3f0 .word 0xe000e3f0 8017f20: 24003024 .word 0x24003024 8017f24: e000ed0c .word 0xe000ed0c 8017f28: 24003028 .word 0x24003028 08017f2c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 8017f2c: b580 push {r7, lr} 8017f2e: b08a sub sp, #40 @ 0x28 8017f30: af00 add r7, sp, #0 8017f32: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 8017f34: 2300 movs r3, #0 8017f36: 61fb str r3, [r7, #28] vTaskSuspendAll(); 8017f38: f7fe f918 bl 801616c { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 8017f3c: 4b5c ldr r3, [pc, #368] @ (80180b0 ) 8017f3e: 681b ldr r3, [r3, #0] 8017f40: 2b00 cmp r3, #0 8017f42: d101 bne.n 8017f48 { prvHeapInit(); 8017f44: f000 f924 bl 8018190 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 8017f48: 4b5a ldr r3, [pc, #360] @ (80180b4 ) 8017f4a: 681a ldr r2, [r3, #0] 8017f4c: 687b ldr r3, [r7, #4] 8017f4e: 4013 ands r3, r2 8017f50: 2b00 cmp r3, #0 8017f52: f040 8095 bne.w 8018080 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 8017f56: 687b ldr r3, [r7, #4] 8017f58: 2b00 cmp r3, #0 8017f5a: d01e beq.n 8017f9a { xWantedSize += xHeapStructSize; 8017f5c: 2208 movs r2, #8 8017f5e: 687b ldr r3, [r7, #4] 8017f60: 4413 add r3, r2 8017f62: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8017f64: 687b ldr r3, [r7, #4] 8017f66: f003 0307 and.w r3, r3, #7 8017f6a: 2b00 cmp r3, #0 8017f6c: d015 beq.n 8017f9a { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 8017f6e: 687b ldr r3, [r7, #4] 8017f70: f023 0307 bic.w r3, r3, #7 8017f74: 3308 adds r3, #8 8017f76: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017f78: 687b ldr r3, [r7, #4] 8017f7a: f003 0307 and.w r3, r3, #7 8017f7e: 2b00 cmp r3, #0 8017f80: d00b beq.n 8017f9a __asm volatile 8017f82: f04f 0350 mov.w r3, #80 @ 0x50 8017f86: f383 8811 msr BASEPRI, r3 8017f8a: f3bf 8f6f isb sy 8017f8e: f3bf 8f4f dsb sy 8017f92: 617b str r3, [r7, #20] } 8017f94: bf00 nop 8017f96: bf00 nop 8017f98: e7fd b.n 8017f96 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 8017f9a: 687b ldr r3, [r7, #4] 8017f9c: 2b00 cmp r3, #0 8017f9e: d06f beq.n 8018080 8017fa0: 4b45 ldr r3, [pc, #276] @ (80180b8 ) 8017fa2: 681b ldr r3, [r3, #0] 8017fa4: 687a ldr r2, [r7, #4] 8017fa6: 429a cmp r2, r3 8017fa8: d86a bhi.n 8018080 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 8017faa: 4b44 ldr r3, [pc, #272] @ (80180bc ) 8017fac: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 8017fae: 4b43 ldr r3, [pc, #268] @ (80180bc ) 8017fb0: 681b ldr r3, [r3, #0] 8017fb2: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017fb4: e004 b.n 8017fc0 { pxPreviousBlock = pxBlock; 8017fb6: 6a7b ldr r3, [r7, #36] @ 0x24 8017fb8: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 8017fba: 6a7b ldr r3, [r7, #36] @ 0x24 8017fbc: 681b ldr r3, [r3, #0] 8017fbe: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017fc0: 6a7b ldr r3, [r7, #36] @ 0x24 8017fc2: 685b ldr r3, [r3, #4] 8017fc4: 687a ldr r2, [r7, #4] 8017fc6: 429a cmp r2, r3 8017fc8: d903 bls.n 8017fd2 8017fca: 6a7b ldr r3, [r7, #36] @ 0x24 8017fcc: 681b ldr r3, [r3, #0] 8017fce: 2b00 cmp r3, #0 8017fd0: d1f1 bne.n 8017fb6 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 8017fd2: 4b37 ldr r3, [pc, #220] @ (80180b0 ) 8017fd4: 681b ldr r3, [r3, #0] 8017fd6: 6a7a ldr r2, [r7, #36] @ 0x24 8017fd8: 429a cmp r2, r3 8017fda: d051 beq.n 8018080 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 8017fdc: 6a3b ldr r3, [r7, #32] 8017fde: 681b ldr r3, [r3, #0] 8017fe0: 2208 movs r2, #8 8017fe2: 4413 add r3, r2 8017fe4: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8017fe6: 6a7b ldr r3, [r7, #36] @ 0x24 8017fe8: 681a ldr r2, [r3, #0] 8017fea: 6a3b ldr r3, [r7, #32] 8017fec: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 8017fee: 6a7b ldr r3, [r7, #36] @ 0x24 8017ff0: 685a ldr r2, [r3, #4] 8017ff2: 687b ldr r3, [r7, #4] 8017ff4: 1ad2 subs r2, r2, r3 8017ff6: 2308 movs r3, #8 8017ff8: 005b lsls r3, r3, #1 8017ffa: 429a cmp r2, r3 8017ffc: d920 bls.n 8018040 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 8017ffe: 6a7a ldr r2, [r7, #36] @ 0x24 8018000: 687b ldr r3, [r7, #4] 8018002: 4413 add r3, r2 8018004: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8018006: 69bb ldr r3, [r7, #24] 8018008: f003 0307 and.w r3, r3, #7 801800c: 2b00 cmp r3, #0 801800e: d00b beq.n 8018028 __asm volatile 8018010: f04f 0350 mov.w r3, #80 @ 0x50 8018014: f383 8811 msr BASEPRI, r3 8018018: f3bf 8f6f isb sy 801801c: f3bf 8f4f dsb sy 8018020: 613b str r3, [r7, #16] } 8018022: bf00 nop 8018024: bf00 nop 8018026: e7fd b.n 8018024 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8018028: 6a7b ldr r3, [r7, #36] @ 0x24 801802a: 685a ldr r2, [r3, #4] 801802c: 687b ldr r3, [r7, #4] 801802e: 1ad2 subs r2, r2, r3 8018030: 69bb ldr r3, [r7, #24] 8018032: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 8018034: 6a7b ldr r3, [r7, #36] @ 0x24 8018036: 687a ldr r2, [r7, #4] 8018038: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 801803a: 69b8 ldr r0, [r7, #24] 801803c: f000 f90a bl 8018254 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 8018040: 4b1d ldr r3, [pc, #116] @ (80180b8 ) 8018042: 681a ldr r2, [r3, #0] 8018044: 6a7b ldr r3, [r7, #36] @ 0x24 8018046: 685b ldr r3, [r3, #4] 8018048: 1ad3 subs r3, r2, r3 801804a: 4a1b ldr r2, [pc, #108] @ (80180b8 ) 801804c: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 801804e: 4b1a ldr r3, [pc, #104] @ (80180b8 ) 8018050: 681a ldr r2, [r3, #0] 8018052: 4b1b ldr r3, [pc, #108] @ (80180c0 ) 8018054: 681b ldr r3, [r3, #0] 8018056: 429a cmp r2, r3 8018058: d203 bcs.n 8018062 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 801805a: 4b17 ldr r3, [pc, #92] @ (80180b8 ) 801805c: 681b ldr r3, [r3, #0] 801805e: 4a18 ldr r2, [pc, #96] @ (80180c0 ) 8018060: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 8018062: 6a7b ldr r3, [r7, #36] @ 0x24 8018064: 685a ldr r2, [r3, #4] 8018066: 4b13 ldr r3, [pc, #76] @ (80180b4 ) 8018068: 681b ldr r3, [r3, #0] 801806a: 431a orrs r2, r3 801806c: 6a7b ldr r3, [r7, #36] @ 0x24 801806e: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 8018070: 6a7b ldr r3, [r7, #36] @ 0x24 8018072: 2200 movs r2, #0 8018074: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 8018076: 4b13 ldr r3, [pc, #76] @ (80180c4 ) 8018078: 681b ldr r3, [r3, #0] 801807a: 3301 adds r3, #1 801807c: 4a11 ldr r2, [pc, #68] @ (80180c4 ) 801807e: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 8018080: f7fe f882 bl 8016188 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 8018084: 69fb ldr r3, [r7, #28] 8018086: f003 0307 and.w r3, r3, #7 801808a: 2b00 cmp r3, #0 801808c: d00b beq.n 80180a6 __asm volatile 801808e: f04f 0350 mov.w r3, #80 @ 0x50 8018092: f383 8811 msr BASEPRI, r3 8018096: f3bf 8f6f isb sy 801809a: f3bf 8f4f dsb sy 801809e: 60fb str r3, [r7, #12] } 80180a0: bf00 nop 80180a2: bf00 nop 80180a4: e7fd b.n 80180a2 return pvReturn; 80180a6: 69fb ldr r3, [r7, #28] } 80180a8: 4618 mov r0, r3 80180aa: 3728 adds r7, #40 @ 0x28 80180ac: 46bd mov sp, r7 80180ae: bd80 pop {r7, pc} 80180b0: 24013034 .word 0x24013034 80180b4: 24013048 .word 0x24013048 80180b8: 24013038 .word 0x24013038 80180bc: 2401302c .word 0x2401302c 80180c0: 2401303c .word 0x2401303c 80180c4: 24013040 .word 0x24013040 080180c8 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 80180c8: b580 push {r7, lr} 80180ca: b086 sub sp, #24 80180cc: af00 add r7, sp, #0 80180ce: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 80180d0: 687b ldr r3, [r7, #4] 80180d2: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 80180d4: 687b ldr r3, [r7, #4] 80180d6: 2b00 cmp r3, #0 80180d8: d04f beq.n 801817a { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 80180da: 2308 movs r3, #8 80180dc: 425b negs r3, r3 80180de: 697a ldr r2, [r7, #20] 80180e0: 4413 add r3, r2 80180e2: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 80180e4: 697b ldr r3, [r7, #20] 80180e6: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 80180e8: 693b ldr r3, [r7, #16] 80180ea: 685a ldr r2, [r3, #4] 80180ec: 4b25 ldr r3, [pc, #148] @ (8018184 ) 80180ee: 681b ldr r3, [r3, #0] 80180f0: 4013 ands r3, r2 80180f2: 2b00 cmp r3, #0 80180f4: d10b bne.n 801810e __asm volatile 80180f6: f04f 0350 mov.w r3, #80 @ 0x50 80180fa: f383 8811 msr BASEPRI, r3 80180fe: f3bf 8f6f isb sy 8018102: f3bf 8f4f dsb sy 8018106: 60fb str r3, [r7, #12] } 8018108: bf00 nop 801810a: bf00 nop 801810c: e7fd b.n 801810a configASSERT( pxLink->pxNextFreeBlock == NULL ); 801810e: 693b ldr r3, [r7, #16] 8018110: 681b ldr r3, [r3, #0] 8018112: 2b00 cmp r3, #0 8018114: d00b beq.n 801812e __asm volatile 8018116: f04f 0350 mov.w r3, #80 @ 0x50 801811a: f383 8811 msr BASEPRI, r3 801811e: f3bf 8f6f isb sy 8018122: f3bf 8f4f dsb sy 8018126: 60bb str r3, [r7, #8] } 8018128: bf00 nop 801812a: bf00 nop 801812c: e7fd b.n 801812a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 801812e: 693b ldr r3, [r7, #16] 8018130: 685a ldr r2, [r3, #4] 8018132: 4b14 ldr r3, [pc, #80] @ (8018184 ) 8018134: 681b ldr r3, [r3, #0] 8018136: 4013 ands r3, r2 8018138: 2b00 cmp r3, #0 801813a: d01e beq.n 801817a { if( pxLink->pxNextFreeBlock == NULL ) 801813c: 693b ldr r3, [r7, #16] 801813e: 681b ldr r3, [r3, #0] 8018140: 2b00 cmp r3, #0 8018142: d11a bne.n 801817a { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 8018144: 693b ldr r3, [r7, #16] 8018146: 685a ldr r2, [r3, #4] 8018148: 4b0e ldr r3, [pc, #56] @ (8018184 ) 801814a: 681b ldr r3, [r3, #0] 801814c: 43db mvns r3, r3 801814e: 401a ands r2, r3 8018150: 693b ldr r3, [r7, #16] 8018152: 605a str r2, [r3, #4] vTaskSuspendAll(); 8018154: f7fe f80a bl 801616c { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 8018158: 693b ldr r3, [r7, #16] 801815a: 685a ldr r2, [r3, #4] 801815c: 4b0a ldr r3, [pc, #40] @ (8018188 ) 801815e: 681b ldr r3, [r3, #0] 8018160: 4413 add r3, r2 8018162: 4a09 ldr r2, [pc, #36] @ (8018188 ) 8018164: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 8018166: 6938 ldr r0, [r7, #16] 8018168: f000 f874 bl 8018254 xNumberOfSuccessfulFrees++; 801816c: 4b07 ldr r3, [pc, #28] @ (801818c ) 801816e: 681b ldr r3, [r3, #0] 8018170: 3301 adds r3, #1 8018172: 4a06 ldr r2, [pc, #24] @ (801818c ) 8018174: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8018176: f7fe f807 bl 8016188 else { mtCOVERAGE_TEST_MARKER(); } } } 801817a: bf00 nop 801817c: 3718 adds r7, #24 801817e: 46bd mov sp, r7 8018180: bd80 pop {r7, pc} 8018182: bf00 nop 8018184: 24013048 .word 0x24013048 8018188: 24013038 .word 0x24013038 801818c: 24013044 .word 0x24013044 08018190 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 8018190: b480 push {r7} 8018192: b085 sub sp, #20 8018194: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 8018196: f44f 3380 mov.w r3, #65536 @ 0x10000 801819a: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 801819c: 4b27 ldr r3, [pc, #156] @ (801823c ) 801819e: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 80181a0: 68fb ldr r3, [r7, #12] 80181a2: f003 0307 and.w r3, r3, #7 80181a6: 2b00 cmp r3, #0 80181a8: d00c beq.n 80181c4 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 80181aa: 68fb ldr r3, [r7, #12] 80181ac: 3307 adds r3, #7 80181ae: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80181b0: 68fb ldr r3, [r7, #12] 80181b2: f023 0307 bic.w r3, r3, #7 80181b6: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 80181b8: 68ba ldr r2, [r7, #8] 80181ba: 68fb ldr r3, [r7, #12] 80181bc: 1ad3 subs r3, r2, r3 80181be: 4a1f ldr r2, [pc, #124] @ (801823c ) 80181c0: 4413 add r3, r2 80181c2: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 80181c4: 68fb ldr r3, [r7, #12] 80181c6: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 80181c8: 4a1d ldr r2, [pc, #116] @ (8018240 ) 80181ca: 687b ldr r3, [r7, #4] 80181cc: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 80181ce: 4b1c ldr r3, [pc, #112] @ (8018240 ) 80181d0: 2200 movs r2, #0 80181d2: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 80181d4: 687b ldr r3, [r7, #4] 80181d6: 68ba ldr r2, [r7, #8] 80181d8: 4413 add r3, r2 80181da: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 80181dc: 2208 movs r2, #8 80181de: 68fb ldr r3, [r7, #12] 80181e0: 1a9b subs r3, r3, r2 80181e2: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80181e4: 68fb ldr r3, [r7, #12] 80181e6: f023 0307 bic.w r3, r3, #7 80181ea: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 80181ec: 68fb ldr r3, [r7, #12] 80181ee: 4a15 ldr r2, [pc, #84] @ (8018244 ) 80181f0: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 80181f2: 4b14 ldr r3, [pc, #80] @ (8018244 ) 80181f4: 681b ldr r3, [r3, #0] 80181f6: 2200 movs r2, #0 80181f8: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 80181fa: 4b12 ldr r3, [pc, #72] @ (8018244 ) 80181fc: 681b ldr r3, [r3, #0] 80181fe: 2200 movs r2, #0 8018200: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8018202: 687b ldr r3, [r7, #4] 8018204: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 8018206: 683b ldr r3, [r7, #0] 8018208: 68fa ldr r2, [r7, #12] 801820a: 1ad2 subs r2, r2, r3 801820c: 683b ldr r3, [r7, #0] 801820e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 8018210: 4b0c ldr r3, [pc, #48] @ (8018244 ) 8018212: 681a ldr r2, [r3, #0] 8018214: 683b ldr r3, [r7, #0] 8018216: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8018218: 683b ldr r3, [r7, #0] 801821a: 685b ldr r3, [r3, #4] 801821c: 4a0a ldr r2, [pc, #40] @ (8018248 ) 801821e: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8018220: 683b ldr r3, [r7, #0] 8018222: 685b ldr r3, [r3, #4] 8018224: 4a09 ldr r2, [pc, #36] @ (801824c ) 8018226: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 8018228: 4b09 ldr r3, [pc, #36] @ (8018250 ) 801822a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 801822e: 601a str r2, [r3, #0] } 8018230: bf00 nop 8018232: 3714 adds r7, #20 8018234: 46bd mov sp, r7 8018236: f85d 7b04 ldr.w r7, [sp], #4 801823a: 4770 bx lr 801823c: 2400302c .word 0x2400302c 8018240: 2401302c .word 0x2401302c 8018244: 24013034 .word 0x24013034 8018248: 2401303c .word 0x2401303c 801824c: 24013038 .word 0x24013038 8018250: 24013048 .word 0x24013048 08018254 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 8018254: b480 push {r7} 8018256: b085 sub sp, #20 8018258: af00 add r7, sp, #0 801825a: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 801825c: 4b28 ldr r3, [pc, #160] @ (8018300 ) 801825e: 60fb str r3, [r7, #12] 8018260: e002 b.n 8018268 8018262: 68fb ldr r3, [r7, #12] 8018264: 681b ldr r3, [r3, #0] 8018266: 60fb str r3, [r7, #12] 8018268: 68fb ldr r3, [r7, #12] 801826a: 681b ldr r3, [r3, #0] 801826c: 687a ldr r2, [r7, #4] 801826e: 429a cmp r2, r3 8018270: d8f7 bhi.n 8018262 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8018272: 68fb ldr r3, [r7, #12] 8018274: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8018276: 68fb ldr r3, [r7, #12] 8018278: 685b ldr r3, [r3, #4] 801827a: 68ba ldr r2, [r7, #8] 801827c: 4413 add r3, r2 801827e: 687a ldr r2, [r7, #4] 8018280: 429a cmp r2, r3 8018282: d108 bne.n 8018296 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 8018284: 68fb ldr r3, [r7, #12] 8018286: 685a ldr r2, [r3, #4] 8018288: 687b ldr r3, [r7, #4] 801828a: 685b ldr r3, [r3, #4] 801828c: 441a add r2, r3 801828e: 68fb ldr r3, [r7, #12] 8018290: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 8018292: 68fb ldr r3, [r7, #12] 8018294: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 8018296: 687b ldr r3, [r7, #4] 8018298: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 801829a: 687b ldr r3, [r7, #4] 801829c: 685b ldr r3, [r3, #4] 801829e: 68ba ldr r2, [r7, #8] 80182a0: 441a add r2, r3 80182a2: 68fb ldr r3, [r7, #12] 80182a4: 681b ldr r3, [r3, #0] 80182a6: 429a cmp r2, r3 80182a8: d118 bne.n 80182dc { if( pxIterator->pxNextFreeBlock != pxEnd ) 80182aa: 68fb ldr r3, [r7, #12] 80182ac: 681a ldr r2, [r3, #0] 80182ae: 4b15 ldr r3, [pc, #84] @ (8018304 ) 80182b0: 681b ldr r3, [r3, #0] 80182b2: 429a cmp r2, r3 80182b4: d00d beq.n 80182d2 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 80182b6: 687b ldr r3, [r7, #4] 80182b8: 685a ldr r2, [r3, #4] 80182ba: 68fb ldr r3, [r7, #12] 80182bc: 681b ldr r3, [r3, #0] 80182be: 685b ldr r3, [r3, #4] 80182c0: 441a add r2, r3 80182c2: 687b ldr r3, [r7, #4] 80182c4: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 80182c6: 68fb ldr r3, [r7, #12] 80182c8: 681b ldr r3, [r3, #0] 80182ca: 681a ldr r2, [r3, #0] 80182cc: 687b ldr r3, [r7, #4] 80182ce: 601a str r2, [r3, #0] 80182d0: e008 b.n 80182e4 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 80182d2: 4b0c ldr r3, [pc, #48] @ (8018304 ) 80182d4: 681a ldr r2, [r3, #0] 80182d6: 687b ldr r3, [r7, #4] 80182d8: 601a str r2, [r3, #0] 80182da: e003 b.n 80182e4 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 80182dc: 68fb ldr r3, [r7, #12] 80182de: 681a ldr r2, [r3, #0] 80182e0: 687b ldr r3, [r7, #4] 80182e2: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 80182e4: 68fa ldr r2, [r7, #12] 80182e6: 687b ldr r3, [r7, #4] 80182e8: 429a cmp r2, r3 80182ea: d002 beq.n 80182f2 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 80182ec: 68fb ldr r3, [r7, #12] 80182ee: 687a ldr r2, [r7, #4] 80182f0: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 80182f2: bf00 nop 80182f4: 3714 adds r7, #20 80182f6: 46bd mov sp, r7 80182f8: f85d 7b04 ldr.w r7, [sp], #4 80182fc: 4770 bx lr 80182fe: bf00 nop 8018300: 2401302c .word 0x2401302c 8018304: 24013034 .word 0x24013034 08018308 : 8018308: 4402 add r2, r0 801830a: 4603 mov r3, r0 801830c: 4293 cmp r3, r2 801830e: d100 bne.n 8018312 8018310: 4770 bx lr 8018312: f803 1b01 strb.w r1, [r3], #1 8018316: e7f9 b.n 801830c 08018318 <_reclaim_reent>: 8018318: 4b29 ldr r3, [pc, #164] @ (80183c0 <_reclaim_reent+0xa8>) 801831a: 681b ldr r3, [r3, #0] 801831c: 4283 cmp r3, r0 801831e: b570 push {r4, r5, r6, lr} 8018320: 4604 mov r4, r0 8018322: d04b beq.n 80183bc <_reclaim_reent+0xa4> 8018324: 69c3 ldr r3, [r0, #28] 8018326: b1ab cbz r3, 8018354 <_reclaim_reent+0x3c> 8018328: 68db ldr r3, [r3, #12] 801832a: b16b cbz r3, 8018348 <_reclaim_reent+0x30> 801832c: 2500 movs r5, #0 801832e: 69e3 ldr r3, [r4, #28] 8018330: 68db ldr r3, [r3, #12] 8018332: 5959 ldr r1, [r3, r5] 8018334: 2900 cmp r1, #0 8018336: d13b bne.n 80183b0 <_reclaim_reent+0x98> 8018338: 3504 adds r5, #4 801833a: 2d80 cmp r5, #128 @ 0x80 801833c: d1f7 bne.n 801832e <_reclaim_reent+0x16> 801833e: 69e3 ldr r3, [r4, #28] 8018340: 4620 mov r0, r4 8018342: 68d9 ldr r1, [r3, #12] 8018344: f000 f878 bl 8018438 <_free_r> 8018348: 69e3 ldr r3, [r4, #28] 801834a: 6819 ldr r1, [r3, #0] 801834c: b111 cbz r1, 8018354 <_reclaim_reent+0x3c> 801834e: 4620 mov r0, r4 8018350: f000 f872 bl 8018438 <_free_r> 8018354: 6961 ldr r1, [r4, #20] 8018356: b111 cbz r1, 801835e <_reclaim_reent+0x46> 8018358: 4620 mov r0, r4 801835a: f000 f86d bl 8018438 <_free_r> 801835e: 69e1 ldr r1, [r4, #28] 8018360: b111 cbz r1, 8018368 <_reclaim_reent+0x50> 8018362: 4620 mov r0, r4 8018364: f000 f868 bl 8018438 <_free_r> 8018368: 6b21 ldr r1, [r4, #48] @ 0x30 801836a: b111 cbz r1, 8018372 <_reclaim_reent+0x5a> 801836c: 4620 mov r0, r4 801836e: f000 f863 bl 8018438 <_free_r> 8018372: 6b61 ldr r1, [r4, #52] @ 0x34 8018374: b111 cbz r1, 801837c <_reclaim_reent+0x64> 8018376: 4620 mov r0, r4 8018378: f000 f85e bl 8018438 <_free_r> 801837c: 6ba1 ldr r1, [r4, #56] @ 0x38 801837e: b111 cbz r1, 8018386 <_reclaim_reent+0x6e> 8018380: 4620 mov r0, r4 8018382: f000 f859 bl 8018438 <_free_r> 8018386: 6ca1 ldr r1, [r4, #72] @ 0x48 8018388: b111 cbz r1, 8018390 <_reclaim_reent+0x78> 801838a: 4620 mov r0, r4 801838c: f000 f854 bl 8018438 <_free_r> 8018390: 6c61 ldr r1, [r4, #68] @ 0x44 8018392: b111 cbz r1, 801839a <_reclaim_reent+0x82> 8018394: 4620 mov r0, r4 8018396: f000 f84f bl 8018438 <_free_r> 801839a: 6ae1 ldr r1, [r4, #44] @ 0x2c 801839c: b111 cbz r1, 80183a4 <_reclaim_reent+0x8c> 801839e: 4620 mov r0, r4 80183a0: f000 f84a bl 8018438 <_free_r> 80183a4: 6a23 ldr r3, [r4, #32] 80183a6: b14b cbz r3, 80183bc <_reclaim_reent+0xa4> 80183a8: 4620 mov r0, r4 80183aa: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 80183ae: 4718 bx r3 80183b0: 680e ldr r6, [r1, #0] 80183b2: 4620 mov r0, r4 80183b4: f000 f840 bl 8018438 <_free_r> 80183b8: 4631 mov r1, r6 80183ba: e7bb b.n 8018334 <_reclaim_reent+0x1c> 80183bc: bd70 pop {r4, r5, r6, pc} 80183be: bf00 nop 80183c0: 24000048 .word 0x24000048 080183c4 <__errno>: 80183c4: 4b01 ldr r3, [pc, #4] @ (80183cc <__errno+0x8>) 80183c6: 6818 ldr r0, [r3, #0] 80183c8: 4770 bx lr 80183ca: bf00 nop 80183cc: 24000048 .word 0x24000048 080183d0 <__libc_init_array>: 80183d0: b570 push {r4, r5, r6, lr} 80183d2: 4d0d ldr r5, [pc, #52] @ (8018408 <__libc_init_array+0x38>) 80183d4: 4c0d ldr r4, [pc, #52] @ (801840c <__libc_init_array+0x3c>) 80183d6: 1b64 subs r4, r4, r5 80183d8: 10a4 asrs r4, r4, #2 80183da: 2600 movs r6, #0 80183dc: 42a6 cmp r6, r4 80183de: d109 bne.n 80183f4 <__libc_init_array+0x24> 80183e0: 4d0b ldr r5, [pc, #44] @ (8018410 <__libc_init_array+0x40>) 80183e2: 4c0c ldr r4, [pc, #48] @ (8018414 <__libc_init_array+0x44>) 80183e4: f000 f920 bl 8018628 <_init> 80183e8: 1b64 subs r4, r4, r5 80183ea: 10a4 asrs r4, r4, #2 80183ec: 2600 movs r6, #0 80183ee: 42a6 cmp r6, r4 80183f0: d105 bne.n 80183fe <__libc_init_array+0x2e> 80183f2: bd70 pop {r4, r5, r6, pc} 80183f4: f855 3b04 ldr.w r3, [r5], #4 80183f8: 4798 blx r3 80183fa: 3601 adds r6, #1 80183fc: e7ee b.n 80183dc <__libc_init_array+0xc> 80183fe: f855 3b04 ldr.w r3, [r5], #4 8018402: 4798 blx r3 8018404: 3601 adds r6, #1 8018406: e7f2 b.n 80183ee <__libc_init_array+0x1e> 8018408: 0801874c .word 0x0801874c 801840c: 0801874c .word 0x0801874c 8018410: 0801874c .word 0x0801874c 8018414: 08018750 .word 0x08018750 08018418 <__retarget_lock_acquire_recursive>: 8018418: 4770 bx lr 0801841a <__retarget_lock_release_recursive>: 801841a: 4770 bx lr 0801841c : 801841c: 440a add r2, r1 801841e: 4291 cmp r1, r2 8018420: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8018424: d100 bne.n 8018428 8018426: 4770 bx lr 8018428: b510 push {r4, lr} 801842a: f811 4b01 ldrb.w r4, [r1], #1 801842e: f803 4f01 strb.w r4, [r3, #1]! 8018432: 4291 cmp r1, r2 8018434: d1f9 bne.n 801842a 8018436: bd10 pop {r4, pc} 08018438 <_free_r>: 8018438: b538 push {r3, r4, r5, lr} 801843a: 4605 mov r5, r0 801843c: 2900 cmp r1, #0 801843e: d041 beq.n 80184c4 <_free_r+0x8c> 8018440: f851 3c04 ldr.w r3, [r1, #-4] 8018444: 1f0c subs r4, r1, #4 8018446: 2b00 cmp r3, #0 8018448: bfb8 it lt 801844a: 18e4 addlt r4, r4, r3 801844c: f000 f83e bl 80184cc <__malloc_lock> 8018450: 4a1d ldr r2, [pc, #116] @ (80184c8 <_free_r+0x90>) 8018452: 6813 ldr r3, [r2, #0] 8018454: b933 cbnz r3, 8018464 <_free_r+0x2c> 8018456: 6063 str r3, [r4, #4] 8018458: 6014 str r4, [r2, #0] 801845a: 4628 mov r0, r5 801845c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8018460: f000 b83a b.w 80184d8 <__malloc_unlock> 8018464: 42a3 cmp r3, r4 8018466: d908 bls.n 801847a <_free_r+0x42> 8018468: 6820 ldr r0, [r4, #0] 801846a: 1821 adds r1, r4, r0 801846c: 428b cmp r3, r1 801846e: bf01 itttt eq 8018470: 6819 ldreq r1, [r3, #0] 8018472: 685b ldreq r3, [r3, #4] 8018474: 1809 addeq r1, r1, r0 8018476: 6021 streq r1, [r4, #0] 8018478: e7ed b.n 8018456 <_free_r+0x1e> 801847a: 461a mov r2, r3 801847c: 685b ldr r3, [r3, #4] 801847e: b10b cbz r3, 8018484 <_free_r+0x4c> 8018480: 42a3 cmp r3, r4 8018482: d9fa bls.n 801847a <_free_r+0x42> 8018484: 6811 ldr r1, [r2, #0] 8018486: 1850 adds r0, r2, r1 8018488: 42a0 cmp r0, r4 801848a: d10b bne.n 80184a4 <_free_r+0x6c> 801848c: 6820 ldr r0, [r4, #0] 801848e: 4401 add r1, r0 8018490: 1850 adds r0, r2, r1 8018492: 4283 cmp r3, r0 8018494: 6011 str r1, [r2, #0] 8018496: d1e0 bne.n 801845a <_free_r+0x22> 8018498: 6818 ldr r0, [r3, #0] 801849a: 685b ldr r3, [r3, #4] 801849c: 6053 str r3, [r2, #4] 801849e: 4408 add r0, r1 80184a0: 6010 str r0, [r2, #0] 80184a2: e7da b.n 801845a <_free_r+0x22> 80184a4: d902 bls.n 80184ac <_free_r+0x74> 80184a6: 230c movs r3, #12 80184a8: 602b str r3, [r5, #0] 80184aa: e7d6 b.n 801845a <_free_r+0x22> 80184ac: 6820 ldr r0, [r4, #0] 80184ae: 1821 adds r1, r4, r0 80184b0: 428b cmp r3, r1 80184b2: bf04 itt eq 80184b4: 6819 ldreq r1, [r3, #0] 80184b6: 685b ldreq r3, [r3, #4] 80184b8: 6063 str r3, [r4, #4] 80184ba: bf04 itt eq 80184bc: 1809 addeq r1, r1, r0 80184be: 6021 streq r1, [r4, #0] 80184c0: 6054 str r4, [r2, #4] 80184c2: e7ca b.n 801845a <_free_r+0x22> 80184c4: bd38 pop {r3, r4, r5, pc} 80184c6: bf00 nop 80184c8: 24013188 .word 0x24013188 080184cc <__malloc_lock>: 80184cc: 4801 ldr r0, [pc, #4] @ (80184d4 <__malloc_lock+0x8>) 80184ce: f7ff bfa3 b.w 8018418 <__retarget_lock_acquire_recursive> 80184d2: bf00 nop 80184d4: 24013184 .word 0x24013184 080184d8 <__malloc_unlock>: 80184d8: 4801 ldr r0, [pc, #4] @ (80184e0 <__malloc_unlock+0x8>) 80184da: f7ff bf9e b.w 801841a <__retarget_lock_release_recursive> 80184de: bf00 nop 80184e0: 24013184 .word 0x24013184 080184e4 : 80184e4: b508 push {r3, lr} 80184e6: ed2d 8b02 vpush {d8} 80184ea: eef0 8a40 vmov.f32 s17, s0 80184ee: eeb0 8a60 vmov.f32 s16, s1 80184f2: f000 f817 bl 8018524 <__ieee754_fmodf> 80184f6: eef4 8a48 vcmp.f32 s17, s16 80184fa: eef1 fa10 vmrs APSR_nzcv, fpscr 80184fe: d60c bvs.n 801851a 8018500: eddf 8a07 vldr s17, [pc, #28] @ 8018520 8018504: eeb4 8a68 vcmp.f32 s16, s17 8018508: eef1 fa10 vmrs APSR_nzcv, fpscr 801850c: d105 bne.n 801851a 801850e: f7ff ff59 bl 80183c4 <__errno> 8018512: ee88 0aa8 vdiv.f32 s0, s17, s17 8018516: 2321 movs r3, #33 @ 0x21 8018518: 6003 str r3, [r0, #0] 801851a: ecbd 8b02 vpop {d8} 801851e: bd08 pop {r3, pc} 8018520: 00000000 .word 0x00000000 08018524 <__ieee754_fmodf>: 8018524: b5f0 push {r4, r5, r6, r7, lr} 8018526: ee10 5a90 vmov r5, s1 801852a: f025 4000 bic.w r0, r5, #2147483648 @ 0x80000000 801852e: 1e43 subs r3, r0, #1 8018530: f1b3 4fff cmp.w r3, #2139095040 @ 0x7f800000 8018534: d206 bcs.n 8018544 <__ieee754_fmodf+0x20> 8018536: ee10 3a10 vmov r3, s0 801853a: f023 4600 bic.w r6, r3, #2147483648 @ 0x80000000 801853e: f1b6 4fff cmp.w r6, #2139095040 @ 0x7f800000 8018542: d304 bcc.n 801854e <__ieee754_fmodf+0x2a> 8018544: ee60 0a20 vmul.f32 s1, s0, s1 8018548: ee80 0aa0 vdiv.f32 s0, s1, s1 801854c: bdf0 pop {r4, r5, r6, r7, pc} 801854e: 4286 cmp r6, r0 8018550: dbfc blt.n 801854c <__ieee754_fmodf+0x28> 8018552: f003 4400 and.w r4, r3, #2147483648 @ 0x80000000 8018556: d105 bne.n 8018564 <__ieee754_fmodf+0x40> 8018558: 4b32 ldr r3, [pc, #200] @ (8018624 <__ieee754_fmodf+0x100>) 801855a: eb03 7354 add.w r3, r3, r4, lsr #29 801855e: ed93 0a00 vldr s0, [r3] 8018562: e7f3 b.n 801854c <__ieee754_fmodf+0x28> 8018564: f013 4fff tst.w r3, #2139095040 @ 0x7f800000 8018568: d140 bne.n 80185ec <__ieee754_fmodf+0xc8> 801856a: 0232 lsls r2, r6, #8 801856c: f06f 017d mvn.w r1, #125 @ 0x7d 8018570: 2a00 cmp r2, #0 8018572: dc38 bgt.n 80185e6 <__ieee754_fmodf+0xc2> 8018574: f015 4fff tst.w r5, #2139095040 @ 0x7f800000 8018578: d13e bne.n 80185f8 <__ieee754_fmodf+0xd4> 801857a: 0207 lsls r7, r0, #8 801857c: f06f 027d mvn.w r2, #125 @ 0x7d 8018580: 2f00 cmp r7, #0 8018582: da36 bge.n 80185f2 <__ieee754_fmodf+0xce> 8018584: f111 0f7e cmn.w r1, #126 @ 0x7e 8018588: bfb9 ittee lt 801858a: f06f 037d mvnlt.w r3, #125 @ 0x7d 801858e: 1a5b sublt r3, r3, r1 8018590: f3c3 0316 ubfxge r3, r3, #0, #23 8018594: f443 0300 orrge.w r3, r3, #8388608 @ 0x800000 8018598: bfb8 it lt 801859a: fa06 f303 lsllt.w r3, r6, r3 801859e: f112 0f7e cmn.w r2, #126 @ 0x7e 80185a2: bfb5 itete lt 80185a4: f06f 057d mvnlt.w r5, #125 @ 0x7d 80185a8: f3c5 0516 ubfxge r5, r5, #0, #23 80185ac: 1aad sublt r5, r5, r2 80185ae: f445 0000 orrge.w r0, r5, #8388608 @ 0x800000 80185b2: bfb8 it lt 80185b4: 40a8 lsllt r0, r5 80185b6: 1a89 subs r1, r1, r2 80185b8: 1a1d subs r5, r3, r0 80185ba: bb01 cbnz r1, 80185fe <__ieee754_fmodf+0xda> 80185bc: ea13 0325 ands.w r3, r3, r5, asr #32 80185c0: bf38 it cc 80185c2: 462b movcc r3, r5 80185c4: 2b00 cmp r3, #0 80185c6: d0c7 beq.n 8018558 <__ieee754_fmodf+0x34> 80185c8: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 80185cc: db1f blt.n 801860e <__ieee754_fmodf+0xea> 80185ce: f112 0f7e cmn.w r2, #126 @ 0x7e 80185d2: db1f blt.n 8018614 <__ieee754_fmodf+0xf0> 80185d4: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 80185d8: 327f adds r2, #127 @ 0x7f 80185da: 4323 orrs r3, r4 80185dc: ea43 53c2 orr.w r3, r3, r2, lsl #23 80185e0: ee00 3a10 vmov s0, r3 80185e4: e7b2 b.n 801854c <__ieee754_fmodf+0x28> 80185e6: 3901 subs r1, #1 80185e8: 0052 lsls r2, r2, #1 80185ea: e7c1 b.n 8018570 <__ieee754_fmodf+0x4c> 80185ec: 15f1 asrs r1, r6, #23 80185ee: 397f subs r1, #127 @ 0x7f 80185f0: e7c0 b.n 8018574 <__ieee754_fmodf+0x50> 80185f2: 3a01 subs r2, #1 80185f4: 007f lsls r7, r7, #1 80185f6: e7c3 b.n 8018580 <__ieee754_fmodf+0x5c> 80185f8: 15c2 asrs r2, r0, #23 80185fa: 3a7f subs r2, #127 @ 0x7f 80185fc: e7c2 b.n 8018584 <__ieee754_fmodf+0x60> 80185fe: 2d00 cmp r5, #0 8018600: da02 bge.n 8018608 <__ieee754_fmodf+0xe4> 8018602: 005b lsls r3, r3, #1 8018604: 3901 subs r1, #1 8018606: e7d7 b.n 80185b8 <__ieee754_fmodf+0x94> 8018608: d0a6 beq.n 8018558 <__ieee754_fmodf+0x34> 801860a: 006b lsls r3, r5, #1 801860c: e7fa b.n 8018604 <__ieee754_fmodf+0xe0> 801860e: 005b lsls r3, r3, #1 8018610: 3a01 subs r2, #1 8018612: e7d9 b.n 80185c8 <__ieee754_fmodf+0xa4> 8018614: f1c2 22ff rsb r2, r2, #4278255360 @ 0xff00ff00 8018618: f502 027f add.w r2, r2, #16711680 @ 0xff0000 801861c: 3282 adds r2, #130 @ 0x82 801861e: 4113 asrs r3, r2 8018620: 4323 orrs r3, r4 8018622: e7dd b.n 80185e0 <__ieee754_fmodf+0xbc> 8018624: 0801873c .word 0x0801873c 08018628 <_init>: 8018628: b5f8 push {r3, r4, r5, r6, r7, lr} 801862a: bf00 nop 801862c: bcf8 pop {r3, r4, r5, r6, r7} 801862e: bc08 pop {r3} 8018630: 469e mov lr, r3 8018632: 4770 bx lr 08018634 <_fini>: 8018634: b5f8 push {r3, r4, r5, r6, r7, lr} 8018636: bf00 nop 8018638: bcf8 pop {r3, r4, r5, r6, r7} 801863a: bc08 pop {r3} 801863c: 469e mov lr, r3 801863e: 4770 bx lr