OZE_Sensor.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000298 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000183b0 080002a0 080002a0 000012a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000104 08018650 08018650 00019650 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM 00000008 08018754 08018754 00019754 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .init_array 00000004 0801875c 0801875c 0001975c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .fini_array 00000004 08018760 08018760 00019760 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .data 00000098 24000000 08018764 0001a000 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .bss 000130ec 240000a0 080187fc 0001a0a0 2**5 ALLOC 8 ._user_heap_stack 00000604 2401318c 080187fc 0001a18c 2**0 ALLOC 9 .ARM.attributes 0000002e 00000000 00000000 0001a098 2**0 CONTENTS, READONLY 10 .debug_info 0003514c 00000000 00000000 0001a0c6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_abbrev 00006452 00000000 00000000 0004f212 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_aranges 00002478 00000000 00000000 00055668 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_macro 0003ef10 00000000 00000000 00057ae0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_line 000317e9 00000000 00000000 000969f0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_str 00186a2c 00000000 00000000 000c81d9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .comment 00000043 00000000 00000000 0024ec05 2**0 CONTENTS, READONLY 17 .debug_rnglists 00001c1d 00000000 00000000 0024ec48 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_frame 00009d14 00000000 00000000 00250868 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_line_str 00000066 00000000 00000000 0025a57c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080002a0 <__do_global_dtors_aux>: 80002a0: b510 push {r4, lr} 80002a2: 4c05 ldr r4, [pc, #20] @ (80002b8 <__do_global_dtors_aux+0x18>) 80002a4: 7823 ldrb r3, [r4, #0] 80002a6: b933 cbnz r3, 80002b6 <__do_global_dtors_aux+0x16> 80002a8: 4b04 ldr r3, [pc, #16] @ (80002bc <__do_global_dtors_aux+0x1c>) 80002aa: b113 cbz r3, 80002b2 <__do_global_dtors_aux+0x12> 80002ac: 4804 ldr r0, [pc, #16] @ (80002c0 <__do_global_dtors_aux+0x20>) 80002ae: f3af 8000 nop.w 80002b2: 2301 movs r3, #1 80002b4: 7023 strb r3, [r4, #0] 80002b6: bd10 pop {r4, pc} 80002b8: 240000a0 .word 0x240000a0 80002bc: 00000000 .word 0x00000000 80002c0: 08018638 .word 0x08018638 080002c4 : 80002c4: b508 push {r3, lr} 80002c6: 4b03 ldr r3, [pc, #12] @ (80002d4 ) 80002c8: b11b cbz r3, 80002d2 80002ca: 4903 ldr r1, [pc, #12] @ (80002d8 ) 80002cc: 4803 ldr r0, [pc, #12] @ (80002dc ) 80002ce: f3af 8000 nop.w 80002d2: bd08 pop {r3, pc} 80002d4: 00000000 .word 0x00000000 80002d8: 240000a4 .word 0x240000a4 80002dc: 08018638 .word 0x08018638 080002e0 <__aeabi_uldivmod>: 80002e0: b953 cbnz r3, 80002f8 <__aeabi_uldivmod+0x18> 80002e2: b94a cbnz r2, 80002f8 <__aeabi_uldivmod+0x18> 80002e4: 2900 cmp r1, #0 80002e6: bf08 it eq 80002e8: 2800 cmpeq r0, #0 80002ea: bf1c itt ne 80002ec: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 80002f0: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 80002f4: f000 b96a b.w 80005cc <__aeabi_idiv0> 80002f8: f1ad 0c08 sub.w ip, sp, #8 80002fc: e96d ce04 strd ip, lr, [sp, #-16]! 8000300: f000 f806 bl 8000310 <__udivmoddi4> 8000304: f8dd e004 ldr.w lr, [sp, #4] 8000308: e9dd 2302 ldrd r2, r3, [sp, #8] 800030c: b004 add sp, #16 800030e: 4770 bx lr 08000310 <__udivmoddi4>: 8000310: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000314: 9d08 ldr r5, [sp, #32] 8000316: 460c mov r4, r1 8000318: 2b00 cmp r3, #0 800031a: d14e bne.n 80003ba <__udivmoddi4+0xaa> 800031c: 4694 mov ip, r2 800031e: 458c cmp ip, r1 8000320: 4686 mov lr, r0 8000322: fab2 f282 clz r2, r2 8000326: d962 bls.n 80003ee <__udivmoddi4+0xde> 8000328: b14a cbz r2, 800033e <__udivmoddi4+0x2e> 800032a: f1c2 0320 rsb r3, r2, #32 800032e: 4091 lsls r1, r2 8000330: fa20 f303 lsr.w r3, r0, r3 8000334: fa0c fc02 lsl.w ip, ip, r2 8000338: 4319 orrs r1, r3 800033a: fa00 fe02 lsl.w lr, r0, r2 800033e: ea4f 471c mov.w r7, ip, lsr #16 8000342: fa1f f68c uxth.w r6, ip 8000346: fbb1 f4f7 udiv r4, r1, r7 800034a: ea4f 431e mov.w r3, lr, lsr #16 800034e: fb07 1114 mls r1, r7, r4, r1 8000352: ea43 4301 orr.w r3, r3, r1, lsl #16 8000356: fb04 f106 mul.w r1, r4, r6 800035a: 4299 cmp r1, r3 800035c: d90a bls.n 8000374 <__udivmoddi4+0x64> 800035e: eb1c 0303 adds.w r3, ip, r3 8000362: f104 30ff add.w r0, r4, #4294967295 @ 0xffffffff 8000366: f080 8112 bcs.w 800058e <__udivmoddi4+0x27e> 800036a: 4299 cmp r1, r3 800036c: f240 810f bls.w 800058e <__udivmoddi4+0x27e> 8000370: 3c02 subs r4, #2 8000372: 4463 add r3, ip 8000374: 1a59 subs r1, r3, r1 8000376: fa1f f38e uxth.w r3, lr 800037a: fbb1 f0f7 udiv r0, r1, r7 800037e: fb07 1110 mls r1, r7, r0, r1 8000382: ea43 4301 orr.w r3, r3, r1, lsl #16 8000386: fb00 f606 mul.w r6, r0, r6 800038a: 429e cmp r6, r3 800038c: d90a bls.n 80003a4 <__udivmoddi4+0x94> 800038e: eb1c 0303 adds.w r3, ip, r3 8000392: f100 31ff add.w r1, r0, #4294967295 @ 0xffffffff 8000396: f080 80fc bcs.w 8000592 <__udivmoddi4+0x282> 800039a: 429e cmp r6, r3 800039c: f240 80f9 bls.w 8000592 <__udivmoddi4+0x282> 80003a0: 4463 add r3, ip 80003a2: 3802 subs r0, #2 80003a4: 1b9b subs r3, r3, r6 80003a6: ea40 4004 orr.w r0, r0, r4, lsl #16 80003aa: 2100 movs r1, #0 80003ac: b11d cbz r5, 80003b6 <__udivmoddi4+0xa6> 80003ae: 40d3 lsrs r3, r2 80003b0: 2200 movs r2, #0 80003b2: e9c5 3200 strd r3, r2, [r5] 80003b6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80003ba: 428b cmp r3, r1 80003bc: d905 bls.n 80003ca <__udivmoddi4+0xba> 80003be: b10d cbz r5, 80003c4 <__udivmoddi4+0xb4> 80003c0: e9c5 0100 strd r0, r1, [r5] 80003c4: 2100 movs r1, #0 80003c6: 4608 mov r0, r1 80003c8: e7f5 b.n 80003b6 <__udivmoddi4+0xa6> 80003ca: fab3 f183 clz r1, r3 80003ce: 2900 cmp r1, #0 80003d0: d146 bne.n 8000460 <__udivmoddi4+0x150> 80003d2: 42a3 cmp r3, r4 80003d4: d302 bcc.n 80003dc <__udivmoddi4+0xcc> 80003d6: 4290 cmp r0, r2 80003d8: f0c0 80f0 bcc.w 80005bc <__udivmoddi4+0x2ac> 80003dc: 1a86 subs r6, r0, r2 80003de: eb64 0303 sbc.w r3, r4, r3 80003e2: 2001 movs r0, #1 80003e4: 2d00 cmp r5, #0 80003e6: d0e6 beq.n 80003b6 <__udivmoddi4+0xa6> 80003e8: e9c5 6300 strd r6, r3, [r5] 80003ec: e7e3 b.n 80003b6 <__udivmoddi4+0xa6> 80003ee: 2a00 cmp r2, #0 80003f0: f040 8090 bne.w 8000514 <__udivmoddi4+0x204> 80003f4: eba1 040c sub.w r4, r1, ip 80003f8: ea4f 481c mov.w r8, ip, lsr #16 80003fc: fa1f f78c uxth.w r7, ip 8000400: 2101 movs r1, #1 8000402: fbb4 f6f8 udiv r6, r4, r8 8000406: ea4f 431e mov.w r3, lr, lsr #16 800040a: fb08 4416 mls r4, r8, r6, r4 800040e: ea43 4304 orr.w r3, r3, r4, lsl #16 8000412: fb07 f006 mul.w r0, r7, r6 8000416: 4298 cmp r0, r3 8000418: d908 bls.n 800042c <__udivmoddi4+0x11c> 800041a: eb1c 0303 adds.w r3, ip, r3 800041e: f106 34ff add.w r4, r6, #4294967295 @ 0xffffffff 8000422: d202 bcs.n 800042a <__udivmoddi4+0x11a> 8000424: 4298 cmp r0, r3 8000426: f200 80cd bhi.w 80005c4 <__udivmoddi4+0x2b4> 800042a: 4626 mov r6, r4 800042c: 1a1c subs r4, r3, r0 800042e: fa1f f38e uxth.w r3, lr 8000432: fbb4 f0f8 udiv r0, r4, r8 8000436: fb08 4410 mls r4, r8, r0, r4 800043a: ea43 4304 orr.w r3, r3, r4, lsl #16 800043e: fb00 f707 mul.w r7, r0, r7 8000442: 429f cmp r7, r3 8000444: d908 bls.n 8000458 <__udivmoddi4+0x148> 8000446: eb1c 0303 adds.w r3, ip, r3 800044a: f100 34ff add.w r4, r0, #4294967295 @ 0xffffffff 800044e: d202 bcs.n 8000456 <__udivmoddi4+0x146> 8000450: 429f cmp r7, r3 8000452: f200 80b0 bhi.w 80005b6 <__udivmoddi4+0x2a6> 8000456: 4620 mov r0, r4 8000458: 1bdb subs r3, r3, r7 800045a: ea40 4006 orr.w r0, r0, r6, lsl #16 800045e: e7a5 b.n 80003ac <__udivmoddi4+0x9c> 8000460: f1c1 0620 rsb r6, r1, #32 8000464: 408b lsls r3, r1 8000466: fa22 f706 lsr.w r7, r2, r6 800046a: 431f orrs r7, r3 800046c: fa20 fc06 lsr.w ip, r0, r6 8000470: fa04 f301 lsl.w r3, r4, r1 8000474: ea43 030c orr.w r3, r3, ip 8000478: 40f4 lsrs r4, r6 800047a: fa00 f801 lsl.w r8, r0, r1 800047e: 0c38 lsrs r0, r7, #16 8000480: ea4f 4913 mov.w r9, r3, lsr #16 8000484: fbb4 fef0 udiv lr, r4, r0 8000488: fa1f fc87 uxth.w ip, r7 800048c: fb00 441e mls r4, r0, lr, r4 8000490: ea49 4404 orr.w r4, r9, r4, lsl #16 8000494: fb0e f90c mul.w r9, lr, ip 8000498: 45a1 cmp r9, r4 800049a: fa02 f201 lsl.w r2, r2, r1 800049e: d90a bls.n 80004b6 <__udivmoddi4+0x1a6> 80004a0: 193c adds r4, r7, r4 80004a2: f10e 3aff add.w sl, lr, #4294967295 @ 0xffffffff 80004a6: f080 8084 bcs.w 80005b2 <__udivmoddi4+0x2a2> 80004aa: 45a1 cmp r9, r4 80004ac: f240 8081 bls.w 80005b2 <__udivmoddi4+0x2a2> 80004b0: f1ae 0e02 sub.w lr, lr, #2 80004b4: 443c add r4, r7 80004b6: eba4 0409 sub.w r4, r4, r9 80004ba: fa1f f983 uxth.w r9, r3 80004be: fbb4 f3f0 udiv r3, r4, r0 80004c2: fb00 4413 mls r4, r0, r3, r4 80004c6: ea49 4404 orr.w r4, r9, r4, lsl #16 80004ca: fb03 fc0c mul.w ip, r3, ip 80004ce: 45a4 cmp ip, r4 80004d0: d907 bls.n 80004e2 <__udivmoddi4+0x1d2> 80004d2: 193c adds r4, r7, r4 80004d4: f103 30ff add.w r0, r3, #4294967295 @ 0xffffffff 80004d8: d267 bcs.n 80005aa <__udivmoddi4+0x29a> 80004da: 45a4 cmp ip, r4 80004dc: d965 bls.n 80005aa <__udivmoddi4+0x29a> 80004de: 3b02 subs r3, #2 80004e0: 443c add r4, r7 80004e2: ea43 400e orr.w r0, r3, lr, lsl #16 80004e6: fba0 9302 umull r9, r3, r0, r2 80004ea: eba4 040c sub.w r4, r4, ip 80004ee: 429c cmp r4, r3 80004f0: 46ce mov lr, r9 80004f2: 469c mov ip, r3 80004f4: d351 bcc.n 800059a <__udivmoddi4+0x28a> 80004f6: d04e beq.n 8000596 <__udivmoddi4+0x286> 80004f8: b155 cbz r5, 8000510 <__udivmoddi4+0x200> 80004fa: ebb8 030e subs.w r3, r8, lr 80004fe: eb64 040c sbc.w r4, r4, ip 8000502: fa04 f606 lsl.w r6, r4, r6 8000506: 40cb lsrs r3, r1 8000508: 431e orrs r6, r3 800050a: 40cc lsrs r4, r1 800050c: e9c5 6400 strd r6, r4, [r5] 8000510: 2100 movs r1, #0 8000512: e750 b.n 80003b6 <__udivmoddi4+0xa6> 8000514: f1c2 0320 rsb r3, r2, #32 8000518: fa20 f103 lsr.w r1, r0, r3 800051c: fa0c fc02 lsl.w ip, ip, r2 8000520: fa24 f303 lsr.w r3, r4, r3 8000524: 4094 lsls r4, r2 8000526: 430c orrs r4, r1 8000528: ea4f 481c mov.w r8, ip, lsr #16 800052c: fa00 fe02 lsl.w lr, r0, r2 8000530: fa1f f78c uxth.w r7, ip 8000534: fbb3 f0f8 udiv r0, r3, r8 8000538: fb08 3110 mls r1, r8, r0, r3 800053c: 0c23 lsrs r3, r4, #16 800053e: ea43 4301 orr.w r3, r3, r1, lsl #16 8000542: fb00 f107 mul.w r1, r0, r7 8000546: 4299 cmp r1, r3 8000548: d908 bls.n 800055c <__udivmoddi4+0x24c> 800054a: eb1c 0303 adds.w r3, ip, r3 800054e: f100 36ff add.w r6, r0, #4294967295 @ 0xffffffff 8000552: d22c bcs.n 80005ae <__udivmoddi4+0x29e> 8000554: 4299 cmp r1, r3 8000556: d92a bls.n 80005ae <__udivmoddi4+0x29e> 8000558: 3802 subs r0, #2 800055a: 4463 add r3, ip 800055c: 1a5b subs r3, r3, r1 800055e: b2a4 uxth r4, r4 8000560: fbb3 f1f8 udiv r1, r3, r8 8000564: fb08 3311 mls r3, r8, r1, r3 8000568: ea44 4403 orr.w r4, r4, r3, lsl #16 800056c: fb01 f307 mul.w r3, r1, r7 8000570: 42a3 cmp r3, r4 8000572: d908 bls.n 8000586 <__udivmoddi4+0x276> 8000574: eb1c 0404 adds.w r4, ip, r4 8000578: f101 36ff add.w r6, r1, #4294967295 @ 0xffffffff 800057c: d213 bcs.n 80005a6 <__udivmoddi4+0x296> 800057e: 42a3 cmp r3, r4 8000580: d911 bls.n 80005a6 <__udivmoddi4+0x296> 8000582: 3902 subs r1, #2 8000584: 4464 add r4, ip 8000586: 1ae4 subs r4, r4, r3 8000588: ea41 4100 orr.w r1, r1, r0, lsl #16 800058c: e739 b.n 8000402 <__udivmoddi4+0xf2> 800058e: 4604 mov r4, r0 8000590: e6f0 b.n 8000374 <__udivmoddi4+0x64> 8000592: 4608 mov r0, r1 8000594: e706 b.n 80003a4 <__udivmoddi4+0x94> 8000596: 45c8 cmp r8, r9 8000598: d2ae bcs.n 80004f8 <__udivmoddi4+0x1e8> 800059a: ebb9 0e02 subs.w lr, r9, r2 800059e: eb63 0c07 sbc.w ip, r3, r7 80005a2: 3801 subs r0, #1 80005a4: e7a8 b.n 80004f8 <__udivmoddi4+0x1e8> 80005a6: 4631 mov r1, r6 80005a8: e7ed b.n 8000586 <__udivmoddi4+0x276> 80005aa: 4603 mov r3, r0 80005ac: e799 b.n 80004e2 <__udivmoddi4+0x1d2> 80005ae: 4630 mov r0, r6 80005b0: e7d4 b.n 800055c <__udivmoddi4+0x24c> 80005b2: 46d6 mov lr, sl 80005b4: e77f b.n 80004b6 <__udivmoddi4+0x1a6> 80005b6: 4463 add r3, ip 80005b8: 3802 subs r0, #2 80005ba: e74d b.n 8000458 <__udivmoddi4+0x148> 80005bc: 4606 mov r6, r0 80005be: 4623 mov r3, r4 80005c0: 4608 mov r0, r1 80005c2: e70f b.n 80003e4 <__udivmoddi4+0xd4> 80005c4: 3e02 subs r6, #2 80005c6: 4463 add r3, ip 80005c8: e730 b.n 800042c <__udivmoddi4+0x11c> 80005ca: bf00 nop 080005cc <__aeabi_idiv0>: 80005cc: 4770 bx lr 80005ce: bf00 nop 080005d0 : /* Hook prototypes */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName); /* USER CODE BEGIN 4 */ void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 80005d0: b480 push {r7} 80005d2: b083 sub sp, #12 80005d4: af00 add r7, sp, #0 80005d6: 6078 str r0, [r7, #4] 80005d8: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 80005da: bf00 nop 80005dc: 370c adds r7, #12 80005de: 46bd mov sp, r7 80005e0: f85d 7b04 ldr.w r7, [sp], #4 80005e4: 4770 bx lr ... 080005e8 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 80005e8: b480 push {r7} 80005ea: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 80005ec: f3bf 8f4f dsb sy } 80005f0: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 80005f2: 4b06 ldr r3, [pc, #24] @ (800060c <__NVIC_SystemReset+0x24>) 80005f4: 68db ldr r3, [r3, #12] 80005f6: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80005fa: 4904 ldr r1, [pc, #16] @ (800060c <__NVIC_SystemReset+0x24>) 80005fc: 4b04 ldr r3, [pc, #16] @ (8000610 <__NVIC_SystemReset+0x28>) 80005fe: 4313 orrs r3, r2 8000600: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 8000602: f3bf 8f4f dsb sy } 8000606: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 8000608: bf00 nop 800060a: e7fd b.n 8000608 <__NVIC_SystemReset+0x20> 800060c: e000ed00 .word 0xe000ed00 8000610: 05fa0004 .word 0x05fa0004 08000614 : #endif return ch; } void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 8000614: b580 push {r7, lr} 8000616: b084 sub sp, #16 8000618: af00 add r7, sp, #0 800061a: 4603 mov r3, r0 800061c: 80fb strh r3, [r7, #6] LimiterSwitchData limiterSwitchData = { 0 }; 800061e: 2300 movs r3, #0 8000620: 60fb str r3, [r7, #12] limiterSwitchData.gpioPin = GPIO_Pin; 8000622: 88fb ldrh r3, [r7, #6] 8000624: 81bb strh r3, [r7, #12] limiterSwitchData.pinState = HAL_GPIO_ReadPin(GPIOD, GPIO_Pin); 8000626: 88fb ldrh r3, [r7, #6] 8000628: 4619 mov r1, r3 800062a: 4808 ldr r0, [pc, #32] @ (800064c ) 800062c: f00a ff82 bl 800b534 8000630: 4603 mov r3, r0 8000632: 73bb strb r3, [r7, #14] osMessageQueuePut(limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8000634: 4b06 ldr r3, [pc, #24] @ (8000650 ) 8000636: 6818 ldr r0, [r3, #0] 8000638: f107 010c add.w r1, r7, #12 800063c: 2300 movs r3, #0 800063e: 2200 movs r2, #0 8000640: f014 f838 bl 80146b4 } 8000644: bf00 nop 8000646: 3710 adds r7, #16 8000648: 46bd mov sp, r7 800064a: bd80 pop {r7, pc} 800064c: 58020c00 .word 0x58020c00 8000650: 2400080c .word 0x2400080c 08000654
: /** * @brief The application entry point. * @retval int */ int main(void) { 8000654: b580 push {r7, lr} 8000656: b084 sub sp, #16 8000658: af00 add r7, sp, #0 /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MPU Configuration--------------------------------------------------------*/ MPU_Config(); 800065a: f001 fbb1 bl 8001dc0 \details Turns on I-Cache */ __STATIC_FORCEINLINE void SCB_EnableICache (void) { #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 800065e: 4b64 ldr r3, [pc, #400] @ (80007f0 ) 8000660: 695b ldr r3, [r3, #20] 8000662: f403 3300 and.w r3, r3, #131072 @ 0x20000 8000666: 2b00 cmp r3, #0 8000668: d11b bne.n 80006a2 __ASM volatile ("dsb 0xF":::"memory"); 800066a: f3bf 8f4f dsb sy } 800066e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000670: f3bf 8f6f isb sy } 8000674: bf00 nop __DSB(); __ISB(); SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 8000676: 4b5e ldr r3, [pc, #376] @ (80007f0 ) 8000678: 2200 movs r2, #0 800067a: f8c3 2250 str.w r2, [r3, #592] @ 0x250 __ASM volatile ("dsb 0xF":::"memory"); 800067e: f3bf 8f4f dsb sy } 8000682: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8000684: f3bf 8f6f isb sy } 8000688: bf00 nop __DSB(); __ISB(); SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 800068a: 4b59 ldr r3, [pc, #356] @ (80007f0 ) 800068c: 695b ldr r3, [r3, #20] 800068e: 4a58 ldr r2, [pc, #352] @ (80007f0 ) 8000690: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000694: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000696: f3bf 8f4f dsb sy } 800069a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800069c: f3bf 8f6f isb sy } 80006a0: e000 b.n 80006a4 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ 80006a2: bf00 nop #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) uint32_t ccsidr; uint32_t sets; uint32_t ways; if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 80006a4: 4b52 ldr r3, [pc, #328] @ (80007f0 ) 80006a6: 695b ldr r3, [r3, #20] 80006a8: f403 3380 and.w r3, r3, #65536 @ 0x10000 80006ac: 2b00 cmp r3, #0 80006ae: d138 bne.n 8000722 SCB->CSSELR = 0U; /* select Level 1 data cache */ 80006b0: 4b4f ldr r3, [pc, #316] @ (80007f0 ) 80006b2: 2200 movs r2, #0 80006b4: f8c3 2084 str.w r2, [r3, #132] @ 0x84 __ASM volatile ("dsb 0xF":::"memory"); 80006b8: f3bf 8f4f dsb sy } 80006bc: bf00 nop __DSB(); ccsidr = SCB->CCSIDR; 80006be: 4b4c ldr r3, [pc, #304] @ (80007f0 ) 80006c0: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80006c4: 60fb str r3, [r7, #12] /* invalidate D-Cache */ sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 80006c6: 68fb ldr r3, [r7, #12] 80006c8: 0b5b lsrs r3, r3, #13 80006ca: f3c3 030e ubfx r3, r3, #0, #15 80006ce: 60bb str r3, [r7, #8] do { ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 80006d0: 68fb ldr r3, [r7, #12] 80006d2: 08db lsrs r3, r3, #3 80006d4: f3c3 0309 ubfx r3, r3, #0, #10 80006d8: 607b str r3, [r7, #4] do { SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80006da: 68bb ldr r3, [r7, #8] 80006dc: 015a lsls r2, r3, #5 80006de: f643 73e0 movw r3, #16352 @ 0x3fe0 80006e2: 4013 ands r3, r2 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 80006e4: 687a ldr r2, [r7, #4] 80006e6: 0792 lsls r2, r2, #30 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 80006e8: 4941 ldr r1, [pc, #260] @ (80007f0 ) 80006ea: 4313 orrs r3, r2 80006ec: f8c1 3260 str.w r3, [r1, #608] @ 0x260 #if defined ( __CC_ARM ) __schedule_barrier(); #endif } while (ways-- != 0U); 80006f0: 687b ldr r3, [r7, #4] 80006f2: 1e5a subs r2, r3, #1 80006f4: 607a str r2, [r7, #4] 80006f6: 2b00 cmp r3, #0 80006f8: d1ef bne.n 80006da } while(sets-- != 0U); 80006fa: 68bb ldr r3, [r7, #8] 80006fc: 1e5a subs r2, r3, #1 80006fe: 60ba str r2, [r7, #8] 8000700: 2b00 cmp r3, #0 8000702: d1e5 bne.n 80006d0 __ASM volatile ("dsb 0xF":::"memory"); 8000704: f3bf 8f4f dsb sy } 8000708: bf00 nop __DSB(); SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 800070a: 4b39 ldr r3, [pc, #228] @ (80007f0 ) 800070c: 695b ldr r3, [r3, #20] 800070e: 4a38 ldr r2, [pc, #224] @ (80007f0 ) 8000710: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8000714: 6153 str r3, [r2, #20] __ASM volatile ("dsb 0xF":::"memory"); 8000716: f3bf 8f4f dsb sy } 800071a: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 800071c: f3bf 8f6f isb sy } 8000720: e000 b.n 8000724 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ 8000722: bf00 nop SCB_EnableDCache(); /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8000724: f005 fb2e bl 8005d84 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000728: f000 f884 bl 8000834 /* Configure the peripherals common clocks */ PeriphCommonClock_Config(); 800072c: f000 f900 bl 8000930 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000730: f000 ff88 bl 8001644 MX_DMA_Init(); 8000734: f000 ff56 bl 80015e4 MX_RNG_Init(); 8000738: f000 fc08 bl 8000f4c MX_USART1_UART_Init(); 800073c: f000 ff02 bl 8001544 MX_ADC1_Init(); 8000740: f000 f926 bl 8000990 MX_UART8_Init(); 8000744: f000 feb2 bl 80014ac MX_CRC_Init(); 8000748: f000 fb7e bl 8000e48 MX_ADC2_Init(); 800074c: f000 fa0a bl 8000b64 MX_ADC3_Init(); 8000750: f000 fa9c bl 8000c8c MX_TIM2_Init(); 8000754: f000 fcac bl 80010b0 MX_TIM1_Init(); 8000758: f000 fc0e bl 8000f78 MX_TIM3_Init(); 800075c: f000 fd26 bl 80011ac MX_DAC1_Init(); 8000760: f000 fb9c bl 8000e9c MX_COMP1_Init(); 8000764: f000 fb42 bl 8000dec MX_TIM4_Init(); 8000768: f000 fdcc bl 8001304 MX_TIM8_Init(); 800076c: f000 fe48 bl 8001400 #ifdef WATCHDOG_ENABLED MX_IWDG1_Init(); 8000770: f000 fbd0 bl 8000f14 #endif /* USER CODE BEGIN 2 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8000774: 481f ldr r0, [pc, #124] @ (80007f4 ) 8000776: f00a ff91 bl 800b69c #endif /* USER CODE END 2 */ /* Init scheduler */ osKernelInitialize(); 800077a: f013 fc2b bl 8013fd4 /* add semaphores, ... */ /* USER CODE END RTOS_SEMAPHORES */ /* Create the timer(s) */ /* creation of debugLedTimer */ debugLedTimerHandle = osTimerNew(debugLedTimerCallback, osTimerOnce, NULL, &debugLedTimer_attributes); 800077e: 4b1e ldr r3, [pc, #120] @ (80007f8 ) 8000780: 2200 movs r2, #0 8000782: 2100 movs r1, #0 8000784: 481d ldr r0, [pc, #116] @ (80007fc ) 8000786: f013 fd33 bl 80141f0 800078a: 4603 mov r3, r0 800078c: 4a1c ldr r2, [pc, #112] @ (8000800 ) 800078e: 6013 str r3, [r2, #0] /* creation of fanTimer */ fanTimerHandle = osTimerNew(fanTimerCallback, osTimerOnce, NULL, &fanTimer_attributes); 8000790: 4b1c ldr r3, [pc, #112] @ (8000804 ) 8000792: 2200 movs r2, #0 8000794: 2100 movs r1, #0 8000796: 481c ldr r0, [pc, #112] @ (8000808 ) 8000798: f013 fd2a bl 80141f0 800079c: 4603 mov r3, r0 800079e: 4a1b ldr r2, [pc, #108] @ (800080c ) 80007a0: 6013 str r3, [r2, #0] /* creation of motorXTimer */ motorXTimerHandle = osTimerNew(motorXTimerCallback, osTimerPeriodic, NULL, &motorXTimer_attributes); 80007a2: 4b1b ldr r3, [pc, #108] @ (8000810 ) 80007a4: 2200 movs r2, #0 80007a6: 2101 movs r1, #1 80007a8: 481a ldr r0, [pc, #104] @ (8000814 ) 80007aa: f013 fd21 bl 80141f0 80007ae: 4603 mov r3, r0 80007b0: 4a19 ldr r2, [pc, #100] @ (8000818 ) 80007b2: 6013 str r3, [r2, #0] /* creation of motorYTimer */ motorYTimerHandle = osTimerNew(motorYTimerCallback, osTimerPeriodic, NULL, &motorYTimer_attributes); 80007b4: 4b19 ldr r3, [pc, #100] @ (800081c ) 80007b6: 2200 movs r2, #0 80007b8: 2101 movs r1, #1 80007ba: 4819 ldr r0, [pc, #100] @ (8000820 ) 80007bc: f013 fd18 bl 80141f0 80007c0: 4603 mov r3, r0 80007c2: 4a18 ldr r2, [pc, #96] @ (8000824 ) 80007c4: 6013 str r3, [r2, #0] /* add queues, ... */ /* USER CODE END RTOS_QUEUES */ /* Create the thread(s) */ /* creation of defaultTask */ defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes); 80007c6: 4a18 ldr r2, [pc, #96] @ (8000828 ) 80007c8: 2100 movs r1, #0 80007ca: 4818 ldr r0, [pc, #96] @ (800082c ) 80007cc: f013 fc4c bl 8014068 80007d0: 4603 mov r3, r0 80007d2: 4a17 ldr r2, [pc, #92] @ (8000830 ) 80007d4: 6013 str r3, [r2, #0] /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 80007d6: 4807 ldr r0, [pc, #28] @ (80007f4 ) 80007d8: f00a ff60 bl 800b69c #endif UartTasksInit(); 80007dc: f004 f8f8 bl 80049d0 #ifdef USER_MOCKS MockMeasurmetsTaskInit(); #else MeasTasksInit(); 80007e0: f001 fb7a bl 8001ed8 #endif PositionControlTaskInit(); 80007e4: f002 fdb2 bl 800334c /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ /* USER CODE END RTOS_EVENTS */ /* Start scheduler */ osKernelStart(); 80007e8: f013 fc18 bl 801401c /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) 80007ec: bf00 nop 80007ee: e7fd b.n 80007ec 80007f0: e000ed00 .word 0xe000ed00 80007f4: 24000418 .word 0x24000418 80007f8: 080186cc .word 0x080186cc 80007fc: 08001d15 .word 0x08001d15 8000800: 240006e4 .word 0x240006e4 8000804: 080186dc .word 0x080186dc 8000808: 08001d2d .word 0x08001d2d 800080c: 24000714 .word 0x24000714 8000810: 080186ec .word 0x080186ec 8000814: 08001d49 .word 0x08001d49 8000818: 24000744 .word 0x24000744 800081c: 080186fc .word 0x080186fc 8000820: 08001d85 .word 0x08001d85 8000824: 24000774 .word 0x24000774 8000828: 080186a8 .word 0x080186a8 800082c: 08001b59 .word 0x08001b59 8000830: 240006e0 .word 0x240006e0 08000834 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 8000834: b580 push {r7, lr} 8000836: b09c sub sp, #112 @ 0x70 8000838: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 800083a: f107 0324 add.w r3, r7, #36 @ 0x24 800083e: 224c movs r2, #76 @ 0x4c 8000840: 2100 movs r1, #0 8000842: 4618 mov r0, r3 8000844: f017 fd68 bl 8018318 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000848: 1d3b adds r3, r7, #4 800084a: 2220 movs r2, #32 800084c: 2100 movs r1, #0 800084e: 4618 mov r0, r3 8000850: f017 fd62 bl 8018318 /** Supply configuration update enable */ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 8000854: 2002 movs r0, #2 8000856: f00a ffbb bl 800b7d0 /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 800085a: 2300 movs r3, #0 800085c: 603b str r3, [r7, #0] 800085e: 4b32 ldr r3, [pc, #200] @ (8000928 ) 8000860: 6adb ldr r3, [r3, #44] @ 0x2c 8000862: 4a31 ldr r2, [pc, #196] @ (8000928 ) 8000864: f023 0301 bic.w r3, r3, #1 8000868: 62d3 str r3, [r2, #44] @ 0x2c 800086a: 4b2f ldr r3, [pc, #188] @ (8000928 ) 800086c: 6adb ldr r3, [r3, #44] @ 0x2c 800086e: f003 0301 and.w r3, r3, #1 8000872: 603b str r3, [r7, #0] 8000874: 4b2d ldr r3, [pc, #180] @ (800092c ) 8000876: 699b ldr r3, [r3, #24] 8000878: 4a2c ldr r2, [pc, #176] @ (800092c ) 800087a: f443 4340 orr.w r3, r3, #49152 @ 0xc000 800087e: 6193 str r3, [r2, #24] 8000880: 4b2a ldr r3, [pc, #168] @ (800092c ) 8000882: 699b ldr r3, [r3, #24] 8000884: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000888: 603b str r3, [r7, #0] 800088a: 683b ldr r3, [r7, #0] while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 800088c: bf00 nop 800088e: 4b27 ldr r3, [pc, #156] @ (800092c ) 8000890: 699b ldr r3, [r3, #24] 8000892: f403 5300 and.w r3, r3, #8192 @ 0x2000 8000896: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800089a: d1f8 bne.n 800088e /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_LSI 800089c: 2329 movs r3, #41 @ 0x29 800089e: 627b str r3, [r7, #36] @ 0x24 |RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80008a0: f44f 3380 mov.w r3, #65536 @ 0x10000 80008a4: 62bb str r3, [r7, #40] @ 0x28 RCC_OscInitStruct.LSIState = RCC_LSI_ON; 80008a6: 2301 movs r3, #1 80008a8: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; 80008aa: 2301 movs r3, #1 80008ac: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80008ae: 2302 movs r3, #2 80008b0: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80008b2: 2302 movs r3, #2 80008b4: 64fb str r3, [r7, #76] @ 0x4c RCC_OscInitStruct.PLL.PLLM = 5; 80008b6: 2305 movs r3, #5 80008b8: 653b str r3, [r7, #80] @ 0x50 RCC_OscInitStruct.PLL.PLLN = 160; 80008ba: 23a0 movs r3, #160 @ 0xa0 80008bc: 657b str r3, [r7, #84] @ 0x54 RCC_OscInitStruct.PLL.PLLP = 2; 80008be: 2302 movs r3, #2 80008c0: 65bb str r3, [r7, #88] @ 0x58 RCC_OscInitStruct.PLL.PLLQ = 2; 80008c2: 2302 movs r3, #2 80008c4: 65fb str r3, [r7, #92] @ 0x5c RCC_OscInitStruct.PLL.PLLR = 2; 80008c6: 2302 movs r3, #2 80008c8: 663b str r3, [r7, #96] @ 0x60 RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; 80008ca: 2308 movs r3, #8 80008cc: 667b str r3, [r7, #100] @ 0x64 RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 80008ce: 2300 movs r3, #0 80008d0: 66bb str r3, [r7, #104] @ 0x68 RCC_OscInitStruct.PLL.PLLFRACN = 0; 80008d2: 2300 movs r3, #0 80008d4: 66fb str r3, [r7, #108] @ 0x6c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80008d6: f107 0324 add.w r3, r7, #36 @ 0x24 80008da: 4618 mov r0, r3 80008dc: f00b f838 bl 800b950 80008e0: 4603 mov r3, r0 80008e2: 2b00 cmp r3, #0 80008e4: d001 beq.n 80008ea { Error_Handler(); 80008e6: f001 faf1 bl 8001ecc } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80008ea: 233f movs r3, #63 @ 0x3f 80008ec: 607b str r3, [r7, #4] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80008ee: 2303 movs r3, #3 80008f0: 60bb str r3, [r7, #8] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80008f2: 2300 movs r3, #0 80008f4: 60fb str r3, [r7, #12] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; 80008f6: 2308 movs r3, #8 80008f8: 613b str r3, [r7, #16] RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; 80008fa: 2340 movs r3, #64 @ 0x40 80008fc: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; 80008fe: 2340 movs r3, #64 @ 0x40 8000900: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; 8000902: f44f 6380 mov.w r3, #1024 @ 0x400 8000906: 61fb str r3, [r7, #28] RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; 8000908: 2340 movs r3, #64 @ 0x40 800090a: 623b str r3, [r7, #32] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800090c: 1d3b adds r3, r7, #4 800090e: 2102 movs r1, #2 8000910: 4618 mov r0, r3 8000912: f00b fc77 bl 800c204 8000916: 4603 mov r3, r0 8000918: 2b00 cmp r3, #0 800091a: d001 beq.n 8000920 { Error_Handler(); 800091c: f001 fad6 bl 8001ecc } } 8000920: bf00 nop 8000922: 3770 adds r7, #112 @ 0x70 8000924: 46bd mov sp, r7 8000926: bd80 pop {r7, pc} 8000928: 58000400 .word 0x58000400 800092c: 58024800 .word 0x58024800 08000930 : /** * @brief Peripherals Common Clock Configuration * @retval None */ void PeriphCommonClock_Config(void) { 8000930: b580 push {r7, lr} 8000932: b0b0 sub sp, #192 @ 0xc0 8000934: af00 add r7, sp, #0 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000936: 463b mov r3, r7 8000938: 22c0 movs r2, #192 @ 0xc0 800093a: 2100 movs r1, #0 800093c: 4618 mov r0, r3 800093e: f017 fceb bl 8018318 /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC; 8000942: f44f 2200 mov.w r2, #524288 @ 0x80000 8000946: f04f 0300 mov.w r3, #0 800094a: e9c7 2300 strd r2, r3, [r7] PeriphClkInitStruct.PLL2.PLL2M = 5; 800094e: 2305 movs r3, #5 8000950: 60bb str r3, [r7, #8] PeriphClkInitStruct.PLL2.PLL2N = 52; 8000952: 2334 movs r3, #52 @ 0x34 8000954: 60fb str r3, [r7, #12] PeriphClkInitStruct.PLL2.PLL2P = 26; 8000956: 231a movs r3, #26 8000958: 613b str r3, [r7, #16] PeriphClkInitStruct.PLL2.PLL2Q = 2; 800095a: 2302 movs r3, #2 800095c: 617b str r3, [r7, #20] PeriphClkInitStruct.PLL2.PLL2R = 2; 800095e: 2302 movs r3, #2 8000960: 61bb str r3, [r7, #24] PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_2; 8000962: 2380 movs r3, #128 @ 0x80 8000964: 61fb str r3, [r7, #28] PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 8000966: 2300 movs r3, #0 8000968: 623b str r3, [r7, #32] PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 800096a: 2300 movs r3, #0 800096c: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 800096e: 2300 movs r3, #0 8000970: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000974: 463b mov r3, r7 8000976: 4618 mov r0, r3 8000978: f00c f812 bl 800c9a0 800097c: 4603 mov r3, r0 800097e: 2b00 cmp r3, #0 8000980: d001 beq.n 8000986 { Error_Handler(); 8000982: f001 faa3 bl 8001ecc } } 8000986: bf00 nop 8000988: 37c0 adds r7, #192 @ 0xc0 800098a: 46bd mov sp, r7 800098c: bd80 pop {r7, pc} ... 08000990 : * @brief ADC1 Initialization Function * @param None * @retval None */ static void MX_ADC1_Init(void) { 8000990: b580 push {r7, lr} 8000992: b08a sub sp, #40 @ 0x28 8000994: af00 add r7, sp, #0 /* USER CODE BEGIN ADC1_Init 0 */ /* USER CODE END ADC1_Init 0 */ ADC_MultiModeTypeDef multimode = {0}; 8000996: f107 031c add.w r3, r7, #28 800099a: 2200 movs r2, #0 800099c: 601a str r2, [r3, #0] 800099e: 605a str r2, [r3, #4] 80009a0: 609a str r2, [r3, #8] ADC_ChannelConfTypeDef sConfig = {0}; 80009a2: 463b mov r3, r7 80009a4: 2200 movs r2, #0 80009a6: 601a str r2, [r3, #0] 80009a8: 605a str r2, [r3, #4] 80009aa: 609a str r2, [r3, #8] 80009ac: 60da str r2, [r3, #12] 80009ae: 611a str r2, [r3, #16] 80009b0: 615a str r2, [r3, #20] 80009b2: 619a str r2, [r3, #24] /* USER CODE END ADC1_Init 1 */ /** Common config */ hadc1.Instance = ADC1; 80009b4: 4b62 ldr r3, [pc, #392] @ (8000b40 ) 80009b6: 4a63 ldr r2, [pc, #396] @ (8000b44 ) 80009b8: 601a str r2, [r3, #0] hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 80009ba: 4b61 ldr r3, [pc, #388] @ (8000b40 ) 80009bc: 2200 movs r2, #0 80009be: 605a str r2, [r3, #4] hadc1.Init.Resolution = ADC_RESOLUTION_16B; 80009c0: 4b5f ldr r3, [pc, #380] @ (8000b40 ) 80009c2: 2200 movs r2, #0 80009c4: 609a str r2, [r3, #8] hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; 80009c6: 4b5e ldr r3, [pc, #376] @ (8000b40 ) 80009c8: 2201 movs r2, #1 80009ca: 60da str r2, [r3, #12] hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; 80009cc: 4b5c ldr r3, [pc, #368] @ (8000b40 ) 80009ce: 2208 movs r2, #8 80009d0: 611a str r2, [r3, #16] hadc1.Init.LowPowerAutoWait = DISABLE; 80009d2: 4b5b ldr r3, [pc, #364] @ (8000b40 ) 80009d4: 2200 movs r2, #0 80009d6: 751a strb r2, [r3, #20] hadc1.Init.ContinuousConvMode = ENABLE; 80009d8: 4b59 ldr r3, [pc, #356] @ (8000b40 ) 80009da: 2201 movs r2, #1 80009dc: 755a strb r2, [r3, #21] hadc1.Init.NbrOfConversion = 7; 80009de: 4b58 ldr r3, [pc, #352] @ (8000b40 ) 80009e0: 2207 movs r2, #7 80009e2: 619a str r2, [r3, #24] hadc1.Init.DiscontinuousConvMode = DISABLE; 80009e4: 4b56 ldr r3, [pc, #344] @ (8000b40 ) 80009e6: 2200 movs r2, #0 80009e8: 771a strb r2, [r3, #28] hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 80009ea: 4b55 ldr r3, [pc, #340] @ (8000b40 ) 80009ec: f44f 629c mov.w r2, #1248 @ 0x4e0 80009f0: 625a str r2, [r3, #36] @ 0x24 hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 80009f2: 4b53 ldr r3, [pc, #332] @ (8000b40 ) 80009f4: f44f 6280 mov.w r2, #1024 @ 0x400 80009f8: 629a str r2, [r3, #40] @ 0x28 hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 80009fa: 4b51 ldr r3, [pc, #324] @ (8000b40 ) 80009fc: 2201 movs r2, #1 80009fe: 62da str r2, [r3, #44] @ 0x2c hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000a00: 4b4f ldr r3, [pc, #316] @ (8000b40 ) 8000a02: 2200 movs r2, #0 8000a04: 631a str r2, [r3, #48] @ 0x30 hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000a06: 4b4e ldr r3, [pc, #312] @ (8000b40 ) 8000a08: 2200 movs r2, #0 8000a0a: 635a str r2, [r3, #52] @ 0x34 hadc1.Init.OversamplingMode = DISABLE; 8000a0c: 4b4c ldr r3, [pc, #304] @ (8000b40 ) 8000a0e: 2200 movs r2, #0 8000a10: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc1) != HAL_OK) 8000a14: 484a ldr r0, [pc, #296] @ (8000b40 ) 8000a16: f005 fc65 bl 80062e4 8000a1a: 4603 mov r3, r0 8000a1c: 2b00 cmp r3, #0 8000a1e: d001 beq.n 8000a24 { Error_Handler(); 8000a20: f001 fa54 bl 8001ecc } /** Configure the ADC multi-mode */ multimode.Mode = ADC_MODE_INDEPENDENT; 8000a24: 2300 movs r3, #0 8000a26: 61fb str r3, [r7, #28] if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 8000a28: f107 031c add.w r3, r7, #28 8000a2c: 4619 mov r1, r3 8000a2e: 4844 ldr r0, [pc, #272] @ (8000b40 ) 8000a30: f006 fd76 bl 8007520 8000a34: 4603 mov r3, r0 8000a36: 2b00 cmp r3, #0 8000a38: d001 beq.n 8000a3e { Error_Handler(); 8000a3a: f001 fa47 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_8; 8000a3e: 4b42 ldr r3, [pc, #264] @ (8000b48 ) 8000a40: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_1; 8000a42: 2306 movs r3, #6 8000a44: 607b str r3, [r7, #4] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000a46: 2306 movs r3, #6 8000a48: 60bb str r3, [r7, #8] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000a4a: f240 73ff movw r3, #2047 @ 0x7ff 8000a4e: 60fb str r3, [r7, #12] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000a50: 2304 movs r3, #4 8000a52: 613b str r3, [r7, #16] sConfig.Offset = 0; 8000a54: 2300 movs r3, #0 8000a56: 617b str r3, [r7, #20] sConfig.OffsetSignedSaturation = DISABLE; 8000a58: 2300 movs r3, #0 8000a5a: 767b strb r3, [r7, #25] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a5c: 463b mov r3, r7 8000a5e: 4619 mov r1, r3 8000a60: 4837 ldr r0, [pc, #220] @ (8000b40 ) 8000a62: f005 feb9 bl 80067d8 8000a66: 4603 mov r3, r0 8000a68: 2b00 cmp r3, #0 8000a6a: d001 beq.n 8000a70 { Error_Handler(); 8000a6c: f001 fa2e bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_7; 8000a70: 4b36 ldr r3, [pc, #216] @ (8000b4c ) 8000a72: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_2; 8000a74: 230c movs r3, #12 8000a76: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a78: 463b mov r3, r7 8000a7a: 4619 mov r1, r3 8000a7c: 4830 ldr r0, [pc, #192] @ (8000b40 ) 8000a7e: f005 feab bl 80067d8 8000a82: 4603 mov r3, r0 8000a84: 2b00 cmp r3, #0 8000a86: d001 beq.n 8000a8c { Error_Handler(); 8000a88: f001 fa20 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_9; 8000a8c: 4b30 ldr r3, [pc, #192] @ (8000b50 ) 8000a8e: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_3; 8000a90: 2312 movs r3, #18 8000a92: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000a94: 463b mov r3, r7 8000a96: 4619 mov r1, r3 8000a98: 4829 ldr r0, [pc, #164] @ (8000b40 ) 8000a9a: f005 fe9d bl 80067d8 8000a9e: 4603 mov r3, r0 8000aa0: 2b00 cmp r3, #0 8000aa2: d001 beq.n 8000aa8 { Error_Handler(); 8000aa4: f001 fa12 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_16; 8000aa8: 4b2a ldr r3, [pc, #168] @ (8000b54 ) 8000aaa: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_4; 8000aac: 2318 movs r3, #24 8000aae: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ab0: 463b mov r3, r7 8000ab2: 4619 mov r1, r3 8000ab4: 4822 ldr r0, [pc, #136] @ (8000b40 ) 8000ab6: f005 fe8f bl 80067d8 8000aba: 4603 mov r3, r0 8000abc: 2b00 cmp r3, #0 8000abe: d001 beq.n 8000ac4 { Error_Handler(); 8000ac0: f001 fa04 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_17; 8000ac4: 4b24 ldr r3, [pc, #144] @ (8000b58 ) 8000ac6: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_5; 8000ac8: f44f 7380 mov.w r3, #256 @ 0x100 8000acc: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000ace: 463b mov r3, r7 8000ad0: 4619 mov r1, r3 8000ad2: 481b ldr r0, [pc, #108] @ (8000b40 ) 8000ad4: f005 fe80 bl 80067d8 8000ad8: 4603 mov r3, r0 8000ada: 2b00 cmp r3, #0 8000adc: d001 beq.n 8000ae2 { Error_Handler(); 8000ade: f001 f9f5 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_14; 8000ae2: 4b1e ldr r3, [pc, #120] @ (8000b5c ) 8000ae4: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_6; 8000ae6: f44f 7383 mov.w r3, #262 @ 0x106 8000aea: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000aec: 463b mov r3, r7 8000aee: 4619 mov r1, r3 8000af0: 4813 ldr r0, [pc, #76] @ (8000b40 ) 8000af2: f005 fe71 bl 80067d8 8000af6: 4603 mov r3, r0 8000af8: 2b00 cmp r3, #0 8000afa: d001 beq.n 8000b00 { Error_Handler(); 8000afc: f001 f9e6 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_15; 8000b00: 4b17 ldr r3, [pc, #92] @ (8000b60 ) 8000b02: 603b str r3, [r7, #0] sConfig.Rank = ADC_REGULAR_RANK_7; 8000b04: f44f 7386 mov.w r3, #268 @ 0x10c 8000b08: 607b str r3, [r7, #4] if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 8000b0a: 463b mov r3, r7 8000b0c: 4619 mov r1, r3 8000b0e: 480c ldr r0, [pc, #48] @ (8000b40 ) 8000b10: f005 fe62 bl 80067d8 8000b14: 4603 mov r3, r0 8000b16: 2b00 cmp r3, #0 8000b18: d001 beq.n 8000b1e { Error_Handler(); 8000b1a: f001 f9d7 bl 8001ecc } /* USER CODE BEGIN ADC1_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc1, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000b1e: f240 72ff movw r2, #2047 @ 0x7ff 8000b22: f04f 1101 mov.w r1, #65537 @ 0x10001 8000b26: 4806 ldr r0, [pc, #24] @ (8000b40 ) 8000b28: f006 fc96 bl 8007458 8000b2c: 4603 mov r3, r0 8000b2e: 2b00 cmp r3, #0 8000b30: d001 beq.n 8000b36 { Error_Handler(); 8000b32: f001 f9cb bl 8001ecc } /* USER CODE END ADC1_Init 2 */ } 8000b36: bf00 nop 8000b38: 3728 adds r7, #40 @ 0x28 8000b3a: 46bd mov sp, r7 8000b3c: bd80 pop {r7, pc} 8000b3e: bf00 nop 8000b40: 24000120 .word 0x24000120 8000b44: 40022000 .word 0x40022000 8000b48: 21800100 .word 0x21800100 8000b4c: 1d500080 .word 0x1d500080 8000b50: 25b00200 .word 0x25b00200 8000b54: 43210000 .word 0x43210000 8000b58: 47520000 .word 0x47520000 8000b5c: 3ac04000 .word 0x3ac04000 8000b60: 3ef08000 .word 0x3ef08000 08000b64 : * @brief ADC2 Initialization Function * @param None * @retval None */ static void MX_ADC2_Init(void) { 8000b64: b580 push {r7, lr} 8000b66: b088 sub sp, #32 8000b68: af00 add r7, sp, #0 /* USER CODE BEGIN ADC2_Init 0 */ /* USER CODE END ADC2_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000b6a: 1d3b adds r3, r7, #4 8000b6c: 2200 movs r2, #0 8000b6e: 601a str r2, [r3, #0] 8000b70: 605a str r2, [r3, #4] 8000b72: 609a str r2, [r3, #8] 8000b74: 60da str r2, [r3, #12] 8000b76: 611a str r2, [r3, #16] 8000b78: 615a str r2, [r3, #20] 8000b7a: 619a str r2, [r3, #24] /* USER CODE END ADC2_Init 1 */ /** Common config */ hadc2.Instance = ADC2; 8000b7c: 4b3e ldr r3, [pc, #248] @ (8000c78 ) 8000b7e: 4a3f ldr r2, [pc, #252] @ (8000c7c ) 8000b80: 601a str r2, [r3, #0] hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 8000b82: 4b3d ldr r3, [pc, #244] @ (8000c78 ) 8000b84: 2200 movs r2, #0 8000b86: 605a str r2, [r3, #4] hadc2.Init.Resolution = ADC_RESOLUTION_16B; 8000b88: 4b3b ldr r3, [pc, #236] @ (8000c78 ) 8000b8a: 2200 movs r2, #0 8000b8c: 609a str r2, [r3, #8] hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000b8e: 4b3a ldr r3, [pc, #232] @ (8000c78 ) 8000b90: 2201 movs r2, #1 8000b92: 60da str r2, [r3, #12] hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000b94: 4b38 ldr r3, [pc, #224] @ (8000c78 ) 8000b96: 2208 movs r2, #8 8000b98: 611a str r2, [r3, #16] hadc2.Init.LowPowerAutoWait = DISABLE; 8000b9a: 4b37 ldr r3, [pc, #220] @ (8000c78 ) 8000b9c: 2200 movs r2, #0 8000b9e: 751a strb r2, [r3, #20] hadc2.Init.ContinuousConvMode = ENABLE; 8000ba0: 4b35 ldr r3, [pc, #212] @ (8000c78 ) 8000ba2: 2201 movs r2, #1 8000ba4: 755a strb r2, [r3, #21] hadc2.Init.NbrOfConversion = 3; 8000ba6: 4b34 ldr r3, [pc, #208] @ (8000c78 ) 8000ba8: 2203 movs r2, #3 8000baa: 619a str r2, [r3, #24] hadc2.Init.DiscontinuousConvMode = DISABLE; 8000bac: 4b32 ldr r3, [pc, #200] @ (8000c78 ) 8000bae: 2200 movs r2, #0 8000bb0: 771a strb r2, [r3, #28] hadc2.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000bb2: 4b31 ldr r3, [pc, #196] @ (8000c78 ) 8000bb4: f44f 629c mov.w r2, #1248 @ 0x4e0 8000bb8: 625a str r2, [r3, #36] @ 0x24 hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000bba: 4b2f ldr r3, [pc, #188] @ (8000c78 ) 8000bbc: f44f 6280 mov.w r2, #1024 @ 0x400 8000bc0: 629a str r2, [r3, #40] @ 0x28 hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000bc2: 4b2d ldr r3, [pc, #180] @ (8000c78 ) 8000bc4: 2201 movs r2, #1 8000bc6: 62da str r2, [r3, #44] @ 0x2c hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000bc8: 4b2b ldr r3, [pc, #172] @ (8000c78 ) 8000bca: 2200 movs r2, #0 8000bcc: 631a str r2, [r3, #48] @ 0x30 hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000bce: 4b2a ldr r3, [pc, #168] @ (8000c78 ) 8000bd0: 2200 movs r2, #0 8000bd2: 635a str r2, [r3, #52] @ 0x34 hadc2.Init.OversamplingMode = DISABLE; 8000bd4: 4b28 ldr r3, [pc, #160] @ (8000c78 ) 8000bd6: 2200 movs r2, #0 8000bd8: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc2) != HAL_OK) 8000bdc: 4826 ldr r0, [pc, #152] @ (8000c78 ) 8000bde: f005 fb81 bl 80062e4 8000be2: 4603 mov r3, r0 8000be4: 2b00 cmp r3, #0 8000be6: d001 beq.n 8000bec { Error_Handler(); 8000be8: f001 f970 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_3; 8000bec: 4b24 ldr r3, [pc, #144] @ (8000c80 ) 8000bee: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000bf0: 2306 movs r3, #6 8000bf2: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000bf4: 2306 movs r3, #6 8000bf6: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000bf8: f240 73ff movw r3, #2047 @ 0x7ff 8000bfc: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000bfe: 2304 movs r3, #4 8000c00: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000c02: 2300 movs r3, #0 8000c04: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000c06: 2300 movs r3, #0 8000c08: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c0a: 1d3b adds r3, r7, #4 8000c0c: 4619 mov r1, r3 8000c0e: 481a ldr r0, [pc, #104] @ (8000c78 ) 8000c10: f005 fde2 bl 80067d8 8000c14: 4603 mov r3, r0 8000c16: 2b00 cmp r3, #0 8000c18: d001 beq.n 8000c1e { Error_Handler(); 8000c1a: f001 f957 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_4; 8000c1e: 4b19 ldr r3, [pc, #100] @ (8000c84 ) 8000c20: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000c22: 230c movs r3, #12 8000c24: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c26: 1d3b adds r3, r7, #4 8000c28: 4619 mov r1, r3 8000c2a: 4813 ldr r0, [pc, #76] @ (8000c78 ) 8000c2c: f005 fdd4 bl 80067d8 8000c30: 4603 mov r3, r0 8000c32: 2b00 cmp r3, #0 8000c34: d001 beq.n 8000c3a { Error_Handler(); 8000c36: f001 f949 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_5; 8000c3a: 4b13 ldr r3, [pc, #76] @ (8000c88 ) 8000c3c: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000c3e: 2312 movs r3, #18 8000c40: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 8000c42: 1d3b adds r3, r7, #4 8000c44: 4619 mov r1, r3 8000c46: 480c ldr r0, [pc, #48] @ (8000c78 ) 8000c48: f005 fdc6 bl 80067d8 8000c4c: 4603 mov r3, r0 8000c4e: 2b00 cmp r3, #0 8000c50: d001 beq.n 8000c56 { Error_Handler(); 8000c52: f001 f93b bl 8001ecc } /* USER CODE BEGIN ADC2_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc2, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000c56: f240 72ff movw r2, #2047 @ 0x7ff 8000c5a: f04f 1101 mov.w r1, #65537 @ 0x10001 8000c5e: 4806 ldr r0, [pc, #24] @ (8000c78 ) 8000c60: f006 fbfa bl 8007458 8000c64: 4603 mov r3, r0 8000c66: 2b00 cmp r3, #0 8000c68: d001 beq.n 8000c6e { Error_Handler(); 8000c6a: f001 f92f bl 8001ecc } /* USER CODE END ADC2_Init 2 */ } 8000c6e: bf00 nop 8000c70: 3720 adds r7, #32 8000c72: 46bd mov sp, r7 8000c74: bd80 pop {r7, pc} 8000c76: bf00 nop 8000c78: 24000184 .word 0x24000184 8000c7c: 40022100 .word 0x40022100 8000c80: 0c900008 .word 0x0c900008 8000c84: 10c00010 .word 0x10c00010 8000c88: 14f00020 .word 0x14f00020 08000c8c : * @brief ADC3 Initialization Function * @param None * @retval None */ static void MX_ADC3_Init(void) { 8000c8c: b580 push {r7, lr} 8000c8e: b088 sub sp, #32 8000c90: af00 add r7, sp, #0 /* USER CODE BEGIN ADC3_Init 0 */ /* USER CODE END ADC3_Init 0 */ ADC_ChannelConfTypeDef sConfig = {0}; 8000c92: 1d3b adds r3, r7, #4 8000c94: 2200 movs r2, #0 8000c96: 601a str r2, [r3, #0] 8000c98: 605a str r2, [r3, #4] 8000c9a: 609a str r2, [r3, #8] 8000c9c: 60da str r2, [r3, #12] 8000c9e: 611a str r2, [r3, #16] 8000ca0: 615a str r2, [r3, #20] 8000ca2: 619a str r2, [r3, #24] /* USER CODE END ADC3_Init 1 */ /** Common config */ hadc3.Instance = ADC3; 8000ca4: 4b4b ldr r3, [pc, #300] @ (8000dd4 ) 8000ca6: 4a4c ldr r2, [pc, #304] @ (8000dd8 ) 8000ca8: 601a str r2, [r3, #0] hadc3.Init.Resolution = ADC_RESOLUTION_16B; 8000caa: 4b4a ldr r3, [pc, #296] @ (8000dd4 ) 8000cac: 2200 movs r2, #0 8000cae: 609a str r2, [r3, #8] hadc3.Init.ScanConvMode = ADC_SCAN_ENABLE; 8000cb0: 4b48 ldr r3, [pc, #288] @ (8000dd4 ) 8000cb2: 2201 movs r2, #1 8000cb4: 60da str r2, [r3, #12] hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV; 8000cb6: 4b47 ldr r3, [pc, #284] @ (8000dd4 ) 8000cb8: 2208 movs r2, #8 8000cba: 611a str r2, [r3, #16] hadc3.Init.LowPowerAutoWait = DISABLE; 8000cbc: 4b45 ldr r3, [pc, #276] @ (8000dd4 ) 8000cbe: 2200 movs r2, #0 8000cc0: 751a strb r2, [r3, #20] hadc3.Init.ContinuousConvMode = ENABLE; 8000cc2: 4b44 ldr r3, [pc, #272] @ (8000dd4 ) 8000cc4: 2201 movs r2, #1 8000cc6: 755a strb r2, [r3, #21] hadc3.Init.NbrOfConversion = 5; 8000cc8: 4b42 ldr r3, [pc, #264] @ (8000dd4 ) 8000cca: 2205 movs r2, #5 8000ccc: 619a str r2, [r3, #24] hadc3.Init.DiscontinuousConvMode = DISABLE; 8000cce: 4b41 ldr r3, [pc, #260] @ (8000dd4 ) 8000cd0: 2200 movs r2, #0 8000cd2: 771a strb r2, [r3, #28] hadc3.Init.ExternalTrigConv = ADC_EXTERNALTRIG_T8_TRGO; 8000cd4: 4b3f ldr r3, [pc, #252] @ (8000dd4 ) 8000cd6: f44f 629c mov.w r2, #1248 @ 0x4e0 8000cda: 625a str r2, [r3, #36] @ 0x24 hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_RISING; 8000cdc: 4b3d ldr r3, [pc, #244] @ (8000dd4 ) 8000cde: f44f 6280 mov.w r2, #1024 @ 0x400 8000ce2: 629a str r2, [r3, #40] @ 0x28 hadc3.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DMA_ONESHOT; 8000ce4: 4b3b ldr r3, [pc, #236] @ (8000dd4 ) 8000ce6: 2201 movs r2, #1 8000ce8: 62da str r2, [r3, #44] @ 0x2c hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED; 8000cea: 4b3a ldr r3, [pc, #232] @ (8000dd4 ) 8000cec: 2200 movs r2, #0 8000cee: 631a str r2, [r3, #48] @ 0x30 hadc3.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 8000cf0: 4b38 ldr r3, [pc, #224] @ (8000dd4 ) 8000cf2: 2200 movs r2, #0 8000cf4: 635a str r2, [r3, #52] @ 0x34 hadc3.Init.OversamplingMode = DISABLE; 8000cf6: 4b37 ldr r3, [pc, #220] @ (8000dd4 ) 8000cf8: 2200 movs r2, #0 8000cfa: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (HAL_ADC_Init(&hadc3) != HAL_OK) 8000cfe: 4835 ldr r0, [pc, #212] @ (8000dd4 ) 8000d00: f005 faf0 bl 80062e4 8000d04: 4603 mov r3, r0 8000d06: 2b00 cmp r3, #0 8000d08: d001 beq.n 8000d0e { Error_Handler(); 8000d0a: f001 f8df bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_0; 8000d0e: 2301 movs r3, #1 8000d10: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_1; 8000d12: 2306 movs r3, #6 8000d14: 60bb str r3, [r7, #8] sConfig.SamplingTime = ADC_SAMPLETIME_387CYCLES_5; 8000d16: 2306 movs r3, #6 8000d18: 60fb str r3, [r7, #12] sConfig.SingleDiff = ADC_SINGLE_ENDED; 8000d1a: f240 73ff movw r3, #2047 @ 0x7ff 8000d1e: 613b str r3, [r7, #16] sConfig.OffsetNumber = ADC_OFFSET_NONE; 8000d20: 2304 movs r3, #4 8000d22: 617b str r3, [r7, #20] sConfig.Offset = 0; 8000d24: 2300 movs r3, #0 8000d26: 61bb str r3, [r7, #24] sConfig.OffsetSignedSaturation = DISABLE; 8000d28: 2300 movs r3, #0 8000d2a: 777b strb r3, [r7, #29] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d2c: 1d3b adds r3, r7, #4 8000d2e: 4619 mov r1, r3 8000d30: 4828 ldr r0, [pc, #160] @ (8000dd4 ) 8000d32: f005 fd51 bl 80067d8 8000d36: 4603 mov r3, r0 8000d38: 2b00 cmp r3, #0 8000d3a: d001 beq.n 8000d40 { Error_Handler(); 8000d3c: f001 f8c6 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_1; 8000d40: 4b26 ldr r3, [pc, #152] @ (8000ddc ) 8000d42: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_2; 8000d44: 230c movs r3, #12 8000d46: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d48: 1d3b adds r3, r7, #4 8000d4a: 4619 mov r1, r3 8000d4c: 4821 ldr r0, [pc, #132] @ (8000dd4 ) 8000d4e: f005 fd43 bl 80067d8 8000d52: 4603 mov r3, r0 8000d54: 2b00 cmp r3, #0 8000d56: d001 beq.n 8000d5c { Error_Handler(); 8000d58: f001 f8b8 bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_10; 8000d5c: 4b20 ldr r3, [pc, #128] @ (8000de0 ) 8000d5e: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_3; 8000d60: 2312 movs r3, #18 8000d62: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d64: 1d3b adds r3, r7, #4 8000d66: 4619 mov r1, r3 8000d68: 481a ldr r0, [pc, #104] @ (8000dd4 ) 8000d6a: f005 fd35 bl 80067d8 8000d6e: 4603 mov r3, r0 8000d70: 2b00 cmp r3, #0 8000d72: d001 beq.n 8000d78 { Error_Handler(); 8000d74: f001 f8aa bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_11; 8000d78: 4b1a ldr r3, [pc, #104] @ (8000de4 ) 8000d7a: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_4; 8000d7c: 2318 movs r3, #24 8000d7e: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d80: 1d3b adds r3, r7, #4 8000d82: 4619 mov r1, r3 8000d84: 4813 ldr r0, [pc, #76] @ (8000dd4 ) 8000d86: f005 fd27 bl 80067d8 8000d8a: 4603 mov r3, r0 8000d8c: 2b00 cmp r3, #0 8000d8e: d001 beq.n 8000d94 { Error_Handler(); 8000d90: f001 f89c bl 8001ecc } /** Configure Regular Channel */ sConfig.Channel = ADC_CHANNEL_VREFINT; 8000d94: 4b14 ldr r3, [pc, #80] @ (8000de8 ) 8000d96: 607b str r3, [r7, #4] sConfig.Rank = ADC_REGULAR_RANK_5; 8000d98: f44f 7380 mov.w r3, #256 @ 0x100 8000d9c: 60bb str r3, [r7, #8] if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) 8000d9e: 1d3b adds r3, r7, #4 8000da0: 4619 mov r1, r3 8000da2: 480c ldr r0, [pc, #48] @ (8000dd4 ) 8000da4: f005 fd18 bl 80067d8 8000da8: 4603 mov r3, r0 8000daa: 2b00 cmp r3, #0 8000dac: d001 beq.n 8000db2 { Error_Handler(); 8000dae: f001 f88d bl 8001ecc } /* USER CODE BEGIN ADC3_Init 2 */ if (HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET_LINEARITY, ADC_SINGLE_ENDED) != HAL_OK) 8000db2: f240 72ff movw r2, #2047 @ 0x7ff 8000db6: f04f 1101 mov.w r1, #65537 @ 0x10001 8000dba: 4806 ldr r0, [pc, #24] @ (8000dd4 ) 8000dbc: f006 fb4c bl 8007458 8000dc0: 4603 mov r3, r0 8000dc2: 2b00 cmp r3, #0 8000dc4: d001 beq.n 8000dca { Error_Handler(); 8000dc6: f001 f881 bl 8001ecc } /* USER CODE END ADC3_Init 2 */ } 8000dca: bf00 nop 8000dcc: 3720 adds r7, #32 8000dce: 46bd mov sp, r7 8000dd0: bd80 pop {r7, pc} 8000dd2: bf00 nop 8000dd4: 240001e8 .word 0x240001e8 8000dd8: 58026000 .word 0x58026000 8000ddc: 04300002 .word 0x04300002 8000de0: 2a000400 .word 0x2a000400 8000de4: 2e300800 .word 0x2e300800 8000de8: cfb80000 .word 0xcfb80000 08000dec : * @brief COMP1 Initialization Function * @param None * @retval None */ static void MX_COMP1_Init(void) { 8000dec: b580 push {r7, lr} 8000dee: af00 add r7, sp, #0 /* USER CODE END COMP1_Init 0 */ /* USER CODE BEGIN COMP1_Init 1 */ /* USER CODE END COMP1_Init 1 */ hcomp1.Instance = COMP1; 8000df0: 4b12 ldr r3, [pc, #72] @ (8000e3c ) 8000df2: 4a13 ldr r2, [pc, #76] @ (8000e40 ) 8000df4: 601a str r2, [r3, #0] hcomp1.Init.InvertingInput = COMP_INPUT_MINUS_3_4VREFINT; 8000df6: 4b11 ldr r3, [pc, #68] @ (8000e3c ) 8000df8: 4a12 ldr r2, [pc, #72] @ (8000e44 ) 8000dfa: 611a str r2, [r3, #16] hcomp1.Init.NonInvertingInput = COMP_INPUT_PLUS_IO2; 8000dfc: 4b0f ldr r3, [pc, #60] @ (8000e3c ) 8000dfe: f44f 1280 mov.w r2, #1048576 @ 0x100000 8000e02: 60da str r2, [r3, #12] hcomp1.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; 8000e04: 4b0d ldr r3, [pc, #52] @ (8000e3c ) 8000e06: 2200 movs r2, #0 8000e08: 619a str r2, [r3, #24] hcomp1.Init.Hysteresis = COMP_HYSTERESIS_NONE; 8000e0a: 4b0c ldr r3, [pc, #48] @ (8000e3c ) 8000e0c: 2200 movs r2, #0 8000e0e: 615a str r2, [r3, #20] hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; 8000e10: 4b0a ldr r3, [pc, #40] @ (8000e3c ) 8000e12: 2200 movs r2, #0 8000e14: 61da str r2, [r3, #28] hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED; 8000e16: 4b09 ldr r3, [pc, #36] @ (8000e3c ) 8000e18: 2200 movs r2, #0 8000e1a: 609a str r2, [r3, #8] hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; 8000e1c: 4b07 ldr r3, [pc, #28] @ (8000e3c ) 8000e1e: 2200 movs r2, #0 8000e20: 605a str r2, [r3, #4] hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; 8000e22: 4b06 ldr r3, [pc, #24] @ (8000e3c ) 8000e24: 2200 movs r2, #0 8000e26: 621a str r2, [r3, #32] if (HAL_COMP_Init(&hcomp1) != HAL_OK) 8000e28: 4804 ldr r0, [pc, #16] @ (8000e3c ) 8000e2a: f006 fc57 bl 80076dc 8000e2e: 4603 mov r3, r0 8000e30: 2b00 cmp r3, #0 8000e32: d001 beq.n 8000e38 { Error_Handler(); 8000e34: f001 f84a bl 8001ecc } /* USER CODE BEGIN COMP1_Init 2 */ /* USER CODE END COMP1_Init 2 */ } 8000e38: bf00 nop 8000e3a: bd80 pop {r7, pc} 8000e3c: 240003b4 .word 0x240003b4 8000e40: 5800380c .word 0x5800380c 8000e44: 00020006 .word 0x00020006 08000e48 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000e48: b580 push {r7, lr} 8000e4a: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000e4c: 4b11 ldr r3, [pc, #68] @ (8000e94 ) 8000e4e: 4a12 ldr r2, [pc, #72] @ (8000e98 ) 8000e50: 601a str r2, [r3, #0] hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_DISABLE; 8000e52: 4b10 ldr r3, [pc, #64] @ (8000e94 ) 8000e54: 2201 movs r2, #1 8000e56: 711a strb r2, [r3, #4] hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; 8000e58: 4b0e ldr r3, [pc, #56] @ (8000e94 ) 8000e5a: 2200 movs r2, #0 8000e5c: 715a strb r2, [r3, #5] hcrc.Init.GeneratingPolynomial = 4129; 8000e5e: 4b0d ldr r3, [pc, #52] @ (8000e94 ) 8000e60: f241 0221 movw r2, #4129 @ 0x1021 8000e64: 609a str r2, [r3, #8] hcrc.Init.CRCLength = CRC_POLYLENGTH_16B; 8000e66: 4b0b ldr r3, [pc, #44] @ (8000e94 ) 8000e68: 2208 movs r2, #8 8000e6a: 60da str r2, [r3, #12] hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; 8000e6c: 4b09 ldr r3, [pc, #36] @ (8000e94 ) 8000e6e: 2200 movs r2, #0 8000e70: 615a str r2, [r3, #20] hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; 8000e72: 4b08 ldr r3, [pc, #32] @ (8000e94 ) 8000e74: 2200 movs r2, #0 8000e76: 619a str r2, [r3, #24] hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; 8000e78: 4b06 ldr r3, [pc, #24] @ (8000e94 ) 8000e7a: 2201 movs r2, #1 8000e7c: 621a str r2, [r3, #32] if (HAL_CRC_Init(&hcrc) != HAL_OK) 8000e7e: 4805 ldr r0, [pc, #20] @ (8000e94 ) 8000e80: f006 ff16 bl 8007cb0 8000e84: 4603 mov r3, r0 8000e86: 2b00 cmp r3, #0 8000e88: d001 beq.n 8000e8e { Error_Handler(); 8000e8a: f001 f81f bl 8001ecc } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 8000e8e: bf00 nop 8000e90: bd80 pop {r7, pc} 8000e92: bf00 nop 8000e94: 240003e0 .word 0x240003e0 8000e98: 58024c00 .word 0x58024c00 08000e9c : * @brief DAC1 Initialization Function * @param None * @retval None */ static void MX_DAC1_Init(void) { 8000e9c: b580 push {r7, lr} 8000e9e: b08a sub sp, #40 @ 0x28 8000ea0: af00 add r7, sp, #0 /* USER CODE BEGIN DAC1_Init 0 */ /* USER CODE END DAC1_Init 0 */ DAC_ChannelConfTypeDef sConfig = {0}; 8000ea2: 1d3b adds r3, r7, #4 8000ea4: 2224 movs r2, #36 @ 0x24 8000ea6: 2100 movs r1, #0 8000ea8: 4618 mov r0, r3 8000eaa: f017 fa35 bl 8018318 /* USER CODE END DAC1_Init 1 */ /** DAC Initialization */ hdac1.Instance = DAC1; 8000eae: 4b17 ldr r3, [pc, #92] @ (8000f0c ) 8000eb0: 4a17 ldr r2, [pc, #92] @ (8000f10 ) 8000eb2: 601a str r2, [r3, #0] if (HAL_DAC_Init(&hdac1) != HAL_OK) 8000eb4: 4815 ldr r0, [pc, #84] @ (8000f0c ) 8000eb6: f007 f901 bl 80080bc 8000eba: 4603 mov r3, r0 8000ebc: 2b00 cmp r3, #0 8000ebe: d001 beq.n 8000ec4 { Error_Handler(); 8000ec0: f001 f804 bl 8001ecc } /** DAC channel OUT1 config */ sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; 8000ec4: 2300 movs r3, #0 8000ec6: 607b str r3, [r7, #4] sConfig.DAC_Trigger = DAC_TRIGGER_NONE; 8000ec8: 2300 movs r3, #0 8000eca: 60bb str r3, [r7, #8] sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 8000ecc: 2300 movs r3, #0 8000ece: 60fb str r3, [r7, #12] sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_DISABLE; 8000ed0: 2301 movs r3, #1 8000ed2: 613b str r3, [r7, #16] sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; 8000ed4: 2300 movs r3, #0 8000ed6: 617b str r3, [r7, #20] if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) 8000ed8: 1d3b adds r3, r7, #4 8000eda: 2200 movs r2, #0 8000edc: 4619 mov r1, r3 8000ede: 480b ldr r0, [pc, #44] @ (8000f0c ) 8000ee0: f007 f9f0 bl 80082c4 8000ee4: 4603 mov r3, r0 8000ee6: 2b00 cmp r3, #0 8000ee8: d001 beq.n 8000eee { Error_Handler(); 8000eea: f000 ffef bl 8001ecc } /** DAC channel OUT2 config */ if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK) 8000eee: 1d3b adds r3, r7, #4 8000ef0: 2210 movs r2, #16 8000ef2: 4619 mov r1, r3 8000ef4: 4805 ldr r0, [pc, #20] @ (8000f0c ) 8000ef6: f007 f9e5 bl 80082c4 8000efa: 4603 mov r3, r0 8000efc: 2b00 cmp r3, #0 8000efe: d001 beq.n 8000f04 { Error_Handler(); 8000f00: f000 ffe4 bl 8001ecc } /* USER CODE BEGIN DAC1_Init 2 */ /* USER CODE END DAC1_Init 2 */ } 8000f04: bf00 nop 8000f06: 3728 adds r7, #40 @ 0x28 8000f08: 46bd mov sp, r7 8000f0a: bd80 pop {r7, pc} 8000f0c: 24000404 .word 0x24000404 8000f10: 40007400 .word 0x40007400 08000f14 : * @brief IWDG1 Initialization Function * @param None * @retval None */ static void MX_IWDG1_Init(void) { 8000f14: b580 push {r7, lr} 8000f16: af00 add r7, sp, #0 /* USER CODE END IWDG1_Init 0 */ /* USER CODE BEGIN IWDG1_Init 1 */ /* USER CODE END IWDG1_Init 1 */ hiwdg1.Instance = IWDG1; 8000f18: 4b0a ldr r3, [pc, #40] @ (8000f44 ) 8000f1a: 4a0b ldr r2, [pc, #44] @ (8000f48 ) 8000f1c: 601a str r2, [r3, #0] hiwdg1.Init.Prescaler = IWDG_PRESCALER_64; 8000f1e: 4b09 ldr r3, [pc, #36] @ (8000f44 ) 8000f20: 2204 movs r2, #4 8000f22: 605a str r2, [r3, #4] hiwdg1.Init.Window = 249; 8000f24: 4b07 ldr r3, [pc, #28] @ (8000f44 ) 8000f26: 22f9 movs r2, #249 @ 0xf9 8000f28: 60da str r2, [r3, #12] hiwdg1.Init.Reload = 249; 8000f2a: 4b06 ldr r3, [pc, #24] @ (8000f44 ) 8000f2c: 22f9 movs r2, #249 @ 0xf9 8000f2e: 609a str r2, [r3, #8] if (HAL_IWDG_Init(&hiwdg1) != HAL_OK) 8000f30: 4804 ldr r0, [pc, #16] @ (8000f44 ) 8000f32: f00a fb64 bl 800b5fe 8000f36: 4603 mov r3, r0 8000f38: 2b00 cmp r3, #0 8000f3a: d001 beq.n 8000f40 { Error_Handler(); 8000f3c: f000 ffc6 bl 8001ecc } /* USER CODE BEGIN IWDG1_Init 2 */ /* USER CODE END IWDG1_Init 2 */ } 8000f40: bf00 nop 8000f42: bd80 pop {r7, pc} 8000f44: 24000418 .word 0x24000418 8000f48: 58004800 .word 0x58004800 08000f4c : * @brief RNG Initialization Function * @param None * @retval None */ static void MX_RNG_Init(void) { 8000f4c: b580 push {r7, lr} 8000f4e: af00 add r7, sp, #0 /* USER CODE END RNG_Init 0 */ /* USER CODE BEGIN RNG_Init 1 */ /* USER CODE END RNG_Init 1 */ hrng.Instance = RNG; 8000f50: 4b07 ldr r3, [pc, #28] @ (8000f70 ) 8000f52: 4a08 ldr r2, [pc, #32] @ (8000f74 ) 8000f54: 601a str r2, [r3, #0] hrng.Init.ClockErrorDetection = RNG_CED_ENABLE; 8000f56: 4b06 ldr r3, [pc, #24] @ (8000f70 ) 8000f58: 2200 movs r2, #0 8000f5a: 605a str r2, [r3, #4] if (HAL_RNG_Init(&hrng) != HAL_OK) 8000f5c: 4804 ldr r0, [pc, #16] @ (8000f70 ) 8000f5e: f00e fa01 bl 800f364 8000f62: 4603 mov r3, r0 8000f64: 2b00 cmp r3, #0 8000f66: d001 beq.n 8000f6c { Error_Handler(); 8000f68: f000 ffb0 bl 8001ecc } /* USER CODE BEGIN RNG_Init 2 */ /* USER CODE END RNG_Init 2 */ } 8000f6c: bf00 nop 8000f6e: bd80 pop {r7, pc} 8000f70: 24000428 .word 0x24000428 8000f74: 48021800 .word 0x48021800 08000f78 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000f78: b5b0 push {r4, r5, r7, lr} 8000f7a: b096 sub sp, #88 @ 0x58 8000f7c: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000f7e: f107 034c add.w r3, r7, #76 @ 0x4c 8000f82: 2200 movs r2, #0 8000f84: 601a str r2, [r3, #0] 8000f86: 605a str r2, [r3, #4] 8000f88: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 8000f8a: f107 0330 add.w r3, r7, #48 @ 0x30 8000f8e: 2200 movs r2, #0 8000f90: 601a str r2, [r3, #0] 8000f92: 605a str r2, [r3, #4] 8000f94: 609a str r2, [r3, #8] 8000f96: 60da str r2, [r3, #12] 8000f98: 611a str r2, [r3, #16] 8000f9a: 615a str r2, [r3, #20] 8000f9c: 619a str r2, [r3, #24] TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 8000f9e: 1d3b adds r3, r7, #4 8000fa0: 222c movs r2, #44 @ 0x2c 8000fa2: 2100 movs r1, #0 8000fa4: 4618 mov r0, r3 8000fa6: f017 f9b7 bl 8018318 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 8000faa: 4b3e ldr r3, [pc, #248] @ (80010a4 ) 8000fac: 4a3e ldr r2, [pc, #248] @ (80010a8 ) 8000fae: 601a str r2, [r3, #0] htim1.Init.Prescaler = 199; 8000fb0: 4b3c ldr r3, [pc, #240] @ (80010a4 ) 8000fb2: 22c7 movs r2, #199 @ 0xc7 8000fb4: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000fb6: 4b3b ldr r3, [pc, #236] @ (80010a4 ) 8000fb8: 2200 movs r2, #0 8000fba: 609a str r2, [r3, #8] htim1.Init.Period = 999; 8000fbc: 4b39 ldr r3, [pc, #228] @ (80010a4 ) 8000fbe: f240 32e7 movw r2, #999 @ 0x3e7 8000fc2: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000fc4: 4b37 ldr r3, [pc, #220] @ (80010a4 ) 8000fc6: 2200 movs r2, #0 8000fc8: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 8000fca: 4b36 ldr r3, [pc, #216] @ (80010a4 ) 8000fcc: 2200 movs r2, #0 8000fce: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8000fd0: 4b34 ldr r3, [pc, #208] @ (80010a4 ) 8000fd2: 2280 movs r2, #128 @ 0x80 8000fd4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8000fd6: 4833 ldr r0, [pc, #204] @ (80010a4 ) 8000fd8: f00e fb66 bl 800f6a8 8000fdc: 4603 mov r3, r0 8000fde: 2b00 cmp r3, #0 8000fe0: d001 beq.n 8000fe6 { Error_Handler(); 8000fe2: f000 ff73 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000fe6: 2300 movs r3, #0 8000fe8: 64fb str r3, [r7, #76] @ 0x4c sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 8000fea: 2300 movs r3, #0 8000fec: 653b str r3, [r7, #80] @ 0x50 sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000fee: 2300 movs r3, #0 8000ff0: 657b str r3, [r7, #84] @ 0x54 if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000ff2: f107 034c add.w r3, r7, #76 @ 0x4c 8000ff6: 4619 mov r1, r3 8000ff8: 482a ldr r0, [pc, #168] @ (80010a4 ) 8000ffa: f010 f8b9 bl 8011170 8000ffe: 4603 mov r3, r0 8001000: 2b00 cmp r3, #0 8001002: d001 beq.n 8001008 { Error_Handler(); 8001004: f000 ff62 bl 8001ecc } sConfigOC.OCMode = TIM_OCMODE_PWM1; 8001008: 2360 movs r3, #96 @ 0x60 800100a: 633b str r3, [r7, #48] @ 0x30 sConfigOC.Pulse = 99; 800100c: 2363 movs r3, #99 @ 0x63 800100e: 637b str r3, [r7, #52] @ 0x34 sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 8001010: 2300 movs r3, #0 8001012: 63bb str r3, [r7, #56] @ 0x38 sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 8001014: 2300 movs r3, #0 8001016: 63fb str r3, [r7, #60] @ 0x3c sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001018: 2300 movs r3, #0 800101a: 643b str r3, [r7, #64] @ 0x40 sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 800101c: 2300 movs r3, #0 800101e: 647b str r3, [r7, #68] @ 0x44 sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 8001020: 2300 movs r3, #0 8001022: 64bb str r3, [r7, #72] @ 0x48 if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001024: f107 0330 add.w r3, r7, #48 @ 0x30 8001028: 2204 movs r2, #4 800102a: 4619 mov r1, r3 800102c: 481d ldr r0, [pc, #116] @ (80010a4 ) 800102e: f00f f88d bl 801014c 8001032: 4603 mov r3, r0 8001034: 2b00 cmp r3, #0 8001036: d001 beq.n 800103c { Error_Handler(); 8001038: f000 ff48 bl 8001ecc } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 800103c: 2300 movs r3, #0 800103e: 607b str r3, [r7, #4] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8001040: 2300 movs r3, #0 8001042: 60bb str r3, [r7, #8] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 8001044: 2300 movs r3, #0 8001046: 60fb str r3, [r7, #12] sBreakDeadTimeConfig.DeadTime = 0; 8001048: 2300 movs r3, #0 800104a: 613b str r3, [r7, #16] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 800104c: 2300 movs r3, #0 800104e: 617b str r3, [r7, #20] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 8001050: f44f 5300 mov.w r3, #8192 @ 0x2000 8001054: 61bb str r3, [r7, #24] sBreakDeadTimeConfig.BreakFilter = 0; 8001056: 2300 movs r3, #0 8001058: 61fb str r3, [r7, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 800105a: 2300 movs r3, #0 800105c: 623b str r3, [r7, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 800105e: f04f 7300 mov.w r3, #33554432 @ 0x2000000 8001062: 627b str r3, [r7, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 8001064: 2300 movs r3, #0 8001066: 62bb str r3, [r7, #40] @ 0x28 sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 8001068: 2300 movs r3, #0 800106a: 62fb str r3, [r7, #44] @ 0x2c if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 800106c: 1d3b adds r3, r7, #4 800106e: 4619 mov r1, r3 8001070: 480c ldr r0, [pc, #48] @ (80010a4 ) 8001072: f010 f90b bl 801128c 8001076: 4603 mov r3, r0 8001078: 2b00 cmp r3, #0 800107a: d001 beq.n 8001080 { Error_Handler(); 800107c: f000 ff26 bl 8001ecc } /* USER CODE BEGIN TIM1_Init 2 */ memcpy(&fanTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 8001080: 4b0a ldr r3, [pc, #40] @ (80010ac ) 8001082: 461d mov r5, r3 8001084: f107 0430 add.w r4, r7, #48 @ 0x30 8001088: cc0f ldmia r4!, {r0, r1, r2, r3} 800108a: c50f stmia r5!, {r0, r1, r2, r3} 800108c: e894 0007 ldmia.w r4, {r0, r1, r2} 8001090: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 8001094: 4803 ldr r0, [pc, #12] @ (80010a4 ) 8001096: f003 f9c5 bl 8004424 } 800109a: bf00 nop 800109c: 3758 adds r7, #88 @ 0x58 800109e: 46bd mov sp, r7 80010a0: bdb0 pop {r4, r5, r7, pc} 80010a2: bf00 nop 80010a4: 2400043c .word 0x2400043c 80010a8: 40010000 .word 0x40010000 80010ac: 240007a4 .word 0x240007a4 080010b0 : * @brief TIM2 Initialization Function * @param None * @retval None */ static void MX_TIM2_Init(void) { 80010b0: b580 push {r7, lr} 80010b2: b08c sub sp, #48 @ 0x30 80010b4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80010b6: f107 0320 add.w r3, r7, #32 80010ba: 2200 movs r2, #0 80010bc: 601a str r2, [r3, #0] 80010be: 605a str r2, [r3, #4] 80010c0: 609a str r2, [r3, #8] 80010c2: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80010c4: f107 0314 add.w r3, r7, #20 80010c8: 2200 movs r2, #0 80010ca: 601a str r2, [r3, #0] 80010cc: 605a str r2, [r3, #4] 80010ce: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 80010d0: 1d3b adds r3, r7, #4 80010d2: 2200 movs r2, #0 80010d4: 601a str r2, [r3, #0] 80010d6: 605a str r2, [r3, #4] 80010d8: 609a str r2, [r3, #8] 80010da: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ htim2.Instance = TIM2; 80010dc: 4b32 ldr r3, [pc, #200] @ (80011a8 ) 80010de: f04f 4280 mov.w r2, #1073741824 @ 0x40000000 80010e2: 601a str r2, [r3, #0] htim2.Init.Prescaler = 9999; 80010e4: 4b30 ldr r3, [pc, #192] @ (80011a8 ) 80010e6: f242 720f movw r2, #9999 @ 0x270f 80010ea: 605a str r2, [r3, #4] htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 80010ec: 4b2e ldr r3, [pc, #184] @ (80011a8 ) 80010ee: 2200 movs r2, #0 80010f0: 609a str r2, [r3, #8] htim2.Init.Period = 2999; 80010f2: 4b2d ldr r3, [pc, #180] @ (80011a8 ) 80010f4: f640 32b7 movw r2, #2999 @ 0xbb7 80010f8: 60da str r2, [r3, #12] htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 80010fa: 4b2b ldr r3, [pc, #172] @ (80011a8 ) 80010fc: f44f 7280 mov.w r2, #256 @ 0x100 8001100: 611a str r2, [r3, #16] htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001102: 4b29 ldr r3, [pc, #164] @ (80011a8 ) 8001104: 2280 movs r2, #128 @ 0x80 8001106: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim2) != HAL_OK) 8001108: 4827 ldr r0, [pc, #156] @ (80011a8 ) 800110a: f00e f98d bl 800f428 800110e: 4603 mov r3, r0 8001110: 2b00 cmp r3, #0 8001112: d001 beq.n 8001118 { Error_Handler(); 8001114: f000 feda bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001118: f44f 5380 mov.w r3, #4096 @ 0x1000 800111c: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK) 800111e: f107 0320 add.w r3, r7, #32 8001122: 4619 mov r1, r3 8001124: 4820 ldr r0, [pc, #128] @ (80011a8 ) 8001126: f00f f925 bl 8010374 800112a: 4603 mov r3, r0 800112c: 2b00 cmp r3, #0 800112e: d001 beq.n 8001134 { Error_Handler(); 8001130: f000 fecc bl 8001ecc } if (HAL_TIM_IC_Init(&htim2) != HAL_OK) 8001134: 481c ldr r0, [pc, #112] @ (80011a8 ) 8001136: f00e fcb3 bl 800faa0 800113a: 4603 mov r3, r0 800113c: 2b00 cmp r3, #0 800113e: d001 beq.n 8001144 { Error_Handler(); 8001140: f000 fec4 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 8001144: 2320 movs r3, #32 8001146: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001148: 2380 movs r3, #128 @ 0x80 800114a: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 800114c: f107 0314 add.w r3, r7, #20 8001150: 4619 mov r1, r3 8001152: 4815 ldr r0, [pc, #84] @ (80011a8 ) 8001154: f010 f80c bl 8011170 8001158: 4603 mov r3, r0 800115a: 2b00 cmp r3, #0 800115c: d001 beq.n 8001162 { Error_Handler(); 800115e: f000 feb5 bl 8001ecc } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 8001162: 2300 movs r3, #0 8001164: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 8001166: 2301 movs r3, #1 8001168: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 800116a: 2300 movs r3, #0 800116c: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 800116e: 2300 movs r3, #0 8001170: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 8001172: 1d3b adds r3, r7, #4 8001174: 2208 movs r2, #8 8001176: 4619 mov r1, r3 8001178: 480b ldr r0, [pc, #44] @ (80011a8 ) 800117a: f00e ff4a bl 8010012 800117e: 4603 mov r3, r0 8001180: 2b00 cmp r3, #0 8001182: d001 beq.n 8001188 { Error_Handler(); 8001184: f000 fea2 bl 8001ecc } if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 8001188: 1d3b adds r3, r7, #4 800118a: 220c movs r2, #12 800118c: 4619 mov r1, r3 800118e: 4806 ldr r0, [pc, #24] @ (80011a8 ) 8001190: f00e ff3f bl 8010012 8001194: 4603 mov r3, r0 8001196: 2b00 cmp r3, #0 8001198: d001 beq.n 800119e { Error_Handler(); 800119a: f000 fe97 bl 8001ecc } /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */ } 800119e: bf00 nop 80011a0: 3730 adds r7, #48 @ 0x30 80011a2: 46bd mov sp, r7 80011a4: bd80 pop {r7, pc} 80011a6: bf00 nop 80011a8: 24000488 .word 0x24000488 080011ac : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 80011ac: b5b0 push {r4, r5, r7, lr} 80011ae: b08a sub sp, #40 @ 0x28 80011b0: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_MasterConfigTypeDef sMasterConfig = {0}; 80011b2: f107 031c add.w r3, r7, #28 80011b6: 2200 movs r2, #0 80011b8: 601a str r2, [r3, #0] 80011ba: 605a str r2, [r3, #4] 80011bc: 609a str r2, [r3, #8] TIM_OC_InitTypeDef sConfigOC = {0}; 80011be: 463b mov r3, r7 80011c0: 2200 movs r2, #0 80011c2: 601a str r2, [r3, #0] 80011c4: 605a str r2, [r3, #4] 80011c6: 609a str r2, [r3, #8] 80011c8: 60da str r2, [r3, #12] 80011ca: 611a str r2, [r3, #16] 80011cc: 615a str r2, [r3, #20] 80011ce: 619a str r2, [r3, #24] /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80011d0: 4b48 ldr r3, [pc, #288] @ (80012f4 ) 80011d2: 4a49 ldr r2, [pc, #292] @ (80012f8 ) 80011d4: 601a str r2, [r3, #0] htim3.Init.Prescaler = 199; 80011d6: 4b47 ldr r3, [pc, #284] @ (80012f4 ) 80011d8: 22c7 movs r2, #199 @ 0xc7 80011da: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 80011dc: 4b45 ldr r3, [pc, #276] @ (80012f4 ) 80011de: 2200 movs r2, #0 80011e0: 609a str r2, [r3, #8] htim3.Init.Period = 999; 80011e2: 4b44 ldr r3, [pc, #272] @ (80012f4 ) 80011e4: f240 32e7 movw r2, #999 @ 0x3e7 80011e8: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80011ea: 4b42 ldr r3, [pc, #264] @ (80012f4 ) 80011ec: 2200 movs r2, #0 80011ee: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 80011f0: 4b40 ldr r3, [pc, #256] @ (80012f4 ) 80011f2: 2280 movs r2, #128 @ 0x80 80011f4: 619a str r2, [r3, #24] if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) 80011f6: 483f ldr r0, [pc, #252] @ (80012f4 ) 80011f8: f00e fa56 bl 800f6a8 80011fc: 4603 mov r3, r0 80011fe: 2b00 cmp r3, #0 8001200: d001 beq.n 8001206 { Error_Handler(); 8001202: f000 fe63 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001206: 2300 movs r3, #0 8001208: 61fb str r3, [r7, #28] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800120a: 2300 movs r3, #0 800120c: 627b str r3, [r7, #36] @ 0x24 if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 800120e: f107 031c add.w r3, r7, #28 8001212: 4619 mov r1, r3 8001214: 4837 ldr r0, [pc, #220] @ (80012f4 ) 8001216: f00f ffab bl 8011170 800121a: 4603 mov r3, r0 800121c: 2b00 cmp r3, #0 800121e: d001 beq.n 8001224 { Error_Handler(); 8001220: f000 fe54 bl 8001ecc } sConfigOC.OCMode = TIM_OCMODE_COMBINED_PWM1; 8001224: 4b35 ldr r3, [pc, #212] @ (80012fc ) 8001226: 603b str r3, [r7, #0] sConfigOC.Pulse = 500; 8001228: f44f 73fa mov.w r3, #500 @ 0x1f4 800122c: 607b str r3, [r7, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 800122e: 2300 movs r3, #0 8001230: 60bb str r3, [r7, #8] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 8001232: 2300 movs r3, #0 8001234: 613b str r3, [r7, #16] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 8001236: 463b mov r3, r7 8001238: 2200 movs r2, #0 800123a: 4619 mov r1, r3 800123c: 482d ldr r0, [pc, #180] @ (80012f4 ) 800123e: f00e ff85 bl 801014c 8001242: 4603 mov r3, r0 8001244: 2b00 cmp r3, #0 8001246: d001 beq.n 800124c { Error_Handler(); 8001248: f000 fe40 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_1); 800124c: 4b29 ldr r3, [pc, #164] @ (80012f4 ) 800124e: 681b ldr r3, [r3, #0] 8001250: 699a ldr r2, [r3, #24] 8001252: 4b28 ldr r3, [pc, #160] @ (80012f4 ) 8001254: 681b ldr r3, [r3, #0] 8001256: f022 0208 bic.w r2, r2, #8 800125a: 619a str r2, [r3, #24] sConfigOC.OCMode = TIM_OCMODE_PWM1; 800125c: 2360 movs r3, #96 @ 0x60 800125e: 603b str r3, [r7, #0] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 8001260: 463b mov r3, r7 8001262: 2204 movs r2, #4 8001264: 4619 mov r1, r3 8001266: 4823 ldr r0, [pc, #140] @ (80012f4 ) 8001268: f00e ff70 bl 801014c 800126c: 4603 mov r3, r0 800126e: 2b00 cmp r3, #0 8001270: d001 beq.n 8001276 { Error_Handler(); 8001272: f000 fe2b bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_2); 8001276: 4b1f ldr r3, [pc, #124] @ (80012f4 ) 8001278: 681b ldr r3, [r3, #0] 800127a: 699a ldr r2, [r3, #24] 800127c: 4b1d ldr r3, [pc, #116] @ (80012f4 ) 800127e: 681b ldr r3, [r3, #0] 8001280: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001284: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8001286: 463b mov r3, r7 8001288: 2208 movs r2, #8 800128a: 4619 mov r1, r3 800128c: 4819 ldr r0, [pc, #100] @ (80012f4 ) 800128e: f00e ff5d bl 801014c 8001292: 4603 mov r3, r0 8001294: 2b00 cmp r3, #0 8001296: d001 beq.n 800129c { Error_Handler(); 8001298: f000 fe18 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_3); 800129c: 4b15 ldr r3, [pc, #84] @ (80012f4 ) 800129e: 681b ldr r3, [r3, #0] 80012a0: 69da ldr r2, [r3, #28] 80012a2: 4b14 ldr r3, [pc, #80] @ (80012f4 ) 80012a4: 681b ldr r3, [r3, #0] 80012a6: f022 0208 bic.w r2, r2, #8 80012aa: 61da str r2, [r3, #28] if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 80012ac: 463b mov r3, r7 80012ae: 220c movs r2, #12 80012b0: 4619 mov r1, r3 80012b2: 4810 ldr r0, [pc, #64] @ (80012f4 ) 80012b4: f00e ff4a bl 801014c 80012b8: 4603 mov r3, r0 80012ba: 2b00 cmp r3, #0 80012bc: d001 beq.n 80012c2 { Error_Handler(); 80012be: f000 fe05 bl 8001ecc } __HAL_TIM_DISABLE_OCxPRELOAD(&htim3, TIM_CHANNEL_4); 80012c2: 4b0c ldr r3, [pc, #48] @ (80012f4 ) 80012c4: 681b ldr r3, [r3, #0] 80012c6: 69da ldr r2, [r3, #28] 80012c8: 4b0a ldr r3, [pc, #40] @ (80012f4 ) 80012ca: 681b ldr r3, [r3, #0] 80012cc: f422 6200 bic.w r2, r2, #2048 @ 0x800 80012d0: 61da str r2, [r3, #28] /* USER CODE BEGIN TIM3_Init 2 */ memcpy(&motorXYTimerConfigOC, &sConfigOC, sizeof(TIM_OC_InitTypeDef)); 80012d2: 4b0b ldr r3, [pc, #44] @ (8001300 ) 80012d4: 461d mov r5, r3 80012d6: 463c mov r4, r7 80012d8: cc0f ldmia r4!, {r0, r1, r2, r3} 80012da: c50f stmia r5!, {r0, r1, r2, r3} 80012dc: e894 0007 ldmia.w r4, {r0, r1, r2} 80012e0: e885 0007 stmia.w r5, {r0, r1, r2} /* USER CODE END TIM3_Init 2 */ HAL_TIM_MspPostInit(&htim3); 80012e4: 4803 ldr r0, [pc, #12] @ (80012f4 ) 80012e6: f003 f89d bl 8004424 } 80012ea: bf00 nop 80012ec: 3728 adds r7, #40 @ 0x28 80012ee: 46bd mov sp, r7 80012f0: bdb0 pop {r4, r5, r7, pc} 80012f2: bf00 nop 80012f4: 240004d4 .word 0x240004d4 80012f8: 40000400 .word 0x40000400 80012fc: 00010040 .word 0x00010040 8001300: 240007c0 .word 0x240007c0 08001304 : * @brief TIM4 Initialization Function * @param None * @retval None */ static void MX_TIM4_Init(void) { 8001304: b580 push {r7, lr} 8001306: b08c sub sp, #48 @ 0x30 8001308: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_Init 0 */ /* USER CODE END TIM4_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 800130a: f107 0320 add.w r3, r7, #32 800130e: 2200 movs r2, #0 8001310: 601a str r2, [r3, #0] 8001312: 605a str r2, [r3, #4] 8001314: 609a str r2, [r3, #8] 8001316: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001318: f107 0314 add.w r3, r7, #20 800131c: 2200 movs r2, #0 800131e: 601a str r2, [r3, #0] 8001320: 605a str r2, [r3, #4] 8001322: 609a str r2, [r3, #8] TIM_IC_InitTypeDef sConfigIC = {0}; 8001324: 1d3b adds r3, r7, #4 8001326: 2200 movs r2, #0 8001328: 601a str r2, [r3, #0] 800132a: 605a str r2, [r3, #4] 800132c: 609a str r2, [r3, #8] 800132e: 60da str r2, [r3, #12] /* USER CODE BEGIN TIM4_Init 1 */ /* USER CODE END TIM4_Init 1 */ htim4.Instance = TIM4; 8001330: 4b31 ldr r3, [pc, #196] @ (80013f8 ) 8001332: 4a32 ldr r2, [pc, #200] @ (80013fc ) 8001334: 601a str r2, [r3, #0] htim4.Init.Prescaler = 9999; 8001336: 4b30 ldr r3, [pc, #192] @ (80013f8 ) 8001338: f242 720f movw r2, #9999 @ 0x270f 800133c: 605a str r2, [r3, #4] htim4.Init.CounterMode = TIM_COUNTERMODE_UP; 800133e: 4b2e ldr r3, [pc, #184] @ (80013f8 ) 8001340: 2200 movs r2, #0 8001342: 609a str r2, [r3, #8] htim4.Init.Period = 2999; 8001344: 4b2c ldr r3, [pc, #176] @ (80013f8 ) 8001346: f640 32b7 movw r2, #2999 @ 0xbb7 800134a: 60da str r2, [r3, #12] htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 800134c: 4b2a ldr r3, [pc, #168] @ (80013f8 ) 800134e: f44f 7280 mov.w r2, #256 @ 0x100 8001352: 611a str r2, [r3, #16] htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001354: 4b28 ldr r3, [pc, #160] @ (80013f8 ) 8001356: 2280 movs r2, #128 @ 0x80 8001358: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim4) != HAL_OK) 800135a: 4827 ldr r0, [pc, #156] @ (80013f8 ) 800135c: f00e f864 bl 800f428 8001360: 4603 mov r3, r0 8001362: 2b00 cmp r3, #0 8001364: d001 beq.n 800136a { Error_Handler(); 8001366: f000 fdb1 bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800136a: f44f 5380 mov.w r3, #4096 @ 0x1000 800136e: 623b str r3, [r7, #32] if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK) 8001370: f107 0320 add.w r3, r7, #32 8001374: 4619 mov r1, r3 8001376: 4820 ldr r0, [pc, #128] @ (80013f8 ) 8001378: f00e fffc bl 8010374 800137c: 4603 mov r3, r0 800137e: 2b00 cmp r3, #0 8001380: d001 beq.n 8001386 { Error_Handler(); 8001382: f000 fda3 bl 8001ecc } if (HAL_TIM_IC_Init(&htim4) != HAL_OK) 8001386: 481c ldr r0, [pc, #112] @ (80013f8 ) 8001388: f00e fb8a bl 800faa0 800138c: 4603 mov r3, r0 800138e: 2b00 cmp r3, #0 8001390: d001 beq.n 8001396 { Error_Handler(); 8001392: f000 fd9b bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001396: 2300 movs r3, #0 8001398: 617b str r3, [r7, #20] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800139a: 2300 movs r3, #0 800139c: 61fb str r3, [r7, #28] if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) 800139e: f107 0314 add.w r3, r7, #20 80013a2: 4619 mov r1, r3 80013a4: 4814 ldr r0, [pc, #80] @ (80013f8 ) 80013a6: f00f fee3 bl 8011170 80013aa: 4603 mov r3, r0 80013ac: 2b00 cmp r3, #0 80013ae: d001 beq.n 80013b4 { Error_Handler(); 80013b0: f000 fd8c bl 8001ecc } sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 80013b4: 2300 movs r3, #0 80013b6: 607b str r3, [r7, #4] sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 80013b8: 2301 movs r3, #1 80013ba: 60bb str r3, [r7, #8] sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 80013bc: 2300 movs r3, #0 80013be: 60fb str r3, [r7, #12] sConfigIC.ICFilter = 0; 80013c0: 2300 movs r3, #0 80013c2: 613b str r3, [r7, #16] if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_3) != HAL_OK) 80013c4: 1d3b adds r3, r7, #4 80013c6: 2208 movs r2, #8 80013c8: 4619 mov r1, r3 80013ca: 480b ldr r0, [pc, #44] @ (80013f8 ) 80013cc: f00e fe21 bl 8010012 80013d0: 4603 mov r3, r0 80013d2: 2b00 cmp r3, #0 80013d4: d001 beq.n 80013da { Error_Handler(); 80013d6: f000 fd79 bl 8001ecc } if (HAL_TIM_IC_ConfigChannel(&htim4, &sConfigIC, TIM_CHANNEL_4) != HAL_OK) 80013da: 1d3b adds r3, r7, #4 80013dc: 220c movs r2, #12 80013de: 4619 mov r1, r3 80013e0: 4805 ldr r0, [pc, #20] @ (80013f8 ) 80013e2: f00e fe16 bl 8010012 80013e6: 4603 mov r3, r0 80013e8: 2b00 cmp r3, #0 80013ea: d001 beq.n 80013f0 { Error_Handler(); 80013ec: f000 fd6e bl 8001ecc } /* USER CODE BEGIN TIM4_Init 2 */ /* USER CODE END TIM4_Init 2 */ } 80013f0: bf00 nop 80013f2: 3730 adds r7, #48 @ 0x30 80013f4: 46bd mov sp, r7 80013f6: bd80 pop {r7, pc} 80013f8: 24000520 .word 0x24000520 80013fc: 40000800 .word 0x40000800 08001400 : * @brief TIM8 Initialization Function * @param None * @retval None */ static void MX_TIM8_Init(void) { 8001400: b580 push {r7, lr} 8001402: b088 sub sp, #32 8001404: af00 add r7, sp, #0 /* USER CODE BEGIN TIM8_Init 0 */ /* USER CODE END TIM8_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8001406: f107 0310 add.w r3, r7, #16 800140a: 2200 movs r2, #0 800140c: 601a str r2, [r3, #0] 800140e: 605a str r2, [r3, #4] 8001410: 609a str r2, [r3, #8] 8001412: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8001414: 1d3b adds r3, r7, #4 8001416: 2200 movs r2, #0 8001418: 601a str r2, [r3, #0] 800141a: 605a str r2, [r3, #4] 800141c: 609a str r2, [r3, #8] /* USER CODE BEGIN TIM8_Init 1 */ /* USER CODE END TIM8_Init 1 */ htim8.Instance = TIM8; 800141e: 4b21 ldr r3, [pc, #132] @ (80014a4 ) 8001420: 4a21 ldr r2, [pc, #132] @ (80014a8 ) 8001422: 601a str r2, [r3, #0] htim8.Init.Prescaler = 9999; 8001424: 4b1f ldr r3, [pc, #124] @ (80014a4 ) 8001426: f242 720f movw r2, #9999 @ 0x270f 800142a: 605a str r2, [r3, #4] htim8.Init.CounterMode = TIM_COUNTERMODE_UP; 800142c: 4b1d ldr r3, [pc, #116] @ (80014a4 ) 800142e: 2200 movs r2, #0 8001430: 609a str r2, [r3, #8] htim8.Init.Period = 999; 8001432: 4b1c ldr r3, [pc, #112] @ (80014a4 ) 8001434: f240 32e7 movw r2, #999 @ 0x3e7 8001438: 60da str r2, [r3, #12] htim8.Init.ClockDivision = TIM_CLOCKDIVISION_DIV2; 800143a: 4b1a ldr r3, [pc, #104] @ (80014a4 ) 800143c: f44f 7280 mov.w r2, #256 @ 0x100 8001440: 611a str r2, [r3, #16] htim8.Init.RepetitionCounter = 0; 8001442: 4b18 ldr r3, [pc, #96] @ (80014a4 ) 8001444: 2200 movs r2, #0 8001446: 615a str r2, [r3, #20] htim8.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; 8001448: 4b16 ldr r3, [pc, #88] @ (80014a4 ) 800144a: 2280 movs r2, #128 @ 0x80 800144c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim8) != HAL_OK) 800144e: 4815 ldr r0, [pc, #84] @ (80014a4 ) 8001450: f00d ffea bl 800f428 8001454: 4603 mov r3, r0 8001456: 2b00 cmp r3, #0 8001458: d001 beq.n 800145e { Error_Handler(); 800145a: f000 fd37 bl 8001ecc } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 800145e: f44f 5380 mov.w r3, #4096 @ 0x1000 8001462: 613b str r3, [r7, #16] if (HAL_TIM_ConfigClockSource(&htim8, &sClockSourceConfig) != HAL_OK) 8001464: f107 0310 add.w r3, r7, #16 8001468: 4619 mov r1, r3 800146a: 480e ldr r0, [pc, #56] @ (80014a4 ) 800146c: f00e ff82 bl 8010374 8001470: 4603 mov r3, r0 8001472: 2b00 cmp r3, #0 8001474: d001 beq.n 800147a { Error_Handler(); 8001476: f000 fd29 bl 8001ecc } sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; 800147a: 2320 movs r3, #32 800147c: 607b str r3, [r7, #4] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 800147e: 2300 movs r3, #0 8001480: 60bb str r3, [r7, #8] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE; 8001482: 2380 movs r3, #128 @ 0x80 8001484: 60fb str r3, [r7, #12] if (HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig) != HAL_OK) 8001486: 1d3b adds r3, r7, #4 8001488: 4619 mov r1, r3 800148a: 4806 ldr r0, [pc, #24] @ (80014a4 ) 800148c: f00f fe70 bl 8011170 8001490: 4603 mov r3, r0 8001492: 2b00 cmp r3, #0 8001494: d001 beq.n 800149a { Error_Handler(); 8001496: f000 fd19 bl 8001ecc } /* USER CODE BEGIN TIM8_Init 2 */ /* USER CODE END TIM8_Init 2 */ } 800149a: bf00 nop 800149c: 3720 adds r7, #32 800149e: 46bd mov sp, r7 80014a0: bd80 pop {r7, pc} 80014a2: bf00 nop 80014a4: 2400056c .word 0x2400056c 80014a8: 40010400 .word 0x40010400 080014ac : * @brief UART8 Initialization Function * @param None * @retval None */ static void MX_UART8_Init(void) { 80014ac: b580 push {r7, lr} 80014ae: af00 add r7, sp, #0 /* USER CODE END UART8_Init 0 */ /* USER CODE BEGIN UART8_Init 1 */ /* USER CODE END UART8_Init 1 */ huart8.Instance = UART8; 80014b0: 4b22 ldr r3, [pc, #136] @ (800153c ) 80014b2: 4a23 ldr r2, [pc, #140] @ (8001540 ) 80014b4: 601a str r2, [r3, #0] huart8.Init.BaudRate = 115200; 80014b6: 4b21 ldr r3, [pc, #132] @ (800153c ) 80014b8: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80014bc: 605a str r2, [r3, #4] huart8.Init.WordLength = UART_WORDLENGTH_8B; 80014be: 4b1f ldr r3, [pc, #124] @ (800153c ) 80014c0: 2200 movs r2, #0 80014c2: 609a str r2, [r3, #8] huart8.Init.StopBits = UART_STOPBITS_1; 80014c4: 4b1d ldr r3, [pc, #116] @ (800153c ) 80014c6: 2200 movs r2, #0 80014c8: 60da str r2, [r3, #12] huart8.Init.Parity = UART_PARITY_NONE; 80014ca: 4b1c ldr r3, [pc, #112] @ (800153c ) 80014cc: 2200 movs r2, #0 80014ce: 611a str r2, [r3, #16] huart8.Init.Mode = UART_MODE_TX_RX; 80014d0: 4b1a ldr r3, [pc, #104] @ (800153c ) 80014d2: 220c movs r2, #12 80014d4: 615a str r2, [r3, #20] huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80014d6: 4b19 ldr r3, [pc, #100] @ (800153c ) 80014d8: 2200 movs r2, #0 80014da: 619a str r2, [r3, #24] huart8.Init.OverSampling = UART_OVERSAMPLING_16; 80014dc: 4b17 ldr r3, [pc, #92] @ (800153c ) 80014de: 2200 movs r2, #0 80014e0: 61da str r2, [r3, #28] huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80014e2: 4b16 ldr r3, [pc, #88] @ (800153c ) 80014e4: 2200 movs r2, #0 80014e6: 621a str r2, [r3, #32] huart8.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80014e8: 4b14 ldr r3, [pc, #80] @ (800153c ) 80014ea: 2200 movs r2, #0 80014ec: 625a str r2, [r3, #36] @ 0x24 huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80014ee: 4b13 ldr r3, [pc, #76] @ (800153c ) 80014f0: 2200 movs r2, #0 80014f2: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart8) != HAL_OK) 80014f4: 4811 ldr r0, [pc, #68] @ (800153c ) 80014f6: f00f ff65 bl 80113c4 80014fa: 4603 mov r3, r0 80014fc: 2b00 cmp r3, #0 80014fe: d001 beq.n 8001504 { Error_Handler(); 8001500: f000 fce4 bl 8001ecc } if (HAL_UARTEx_SetTxFifoThreshold(&huart8, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 8001504: 2100 movs r1, #0 8001506: 480d ldr r0, [pc, #52] @ (800153c ) 8001508: f012 fc05 bl 8013d16 800150c: 4603 mov r3, r0 800150e: 2b00 cmp r3, #0 8001510: d001 beq.n 8001516 { Error_Handler(); 8001512: f000 fcdb bl 8001ecc } if (HAL_UARTEx_SetRxFifoThreshold(&huart8, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 8001516: 2100 movs r1, #0 8001518: 4808 ldr r0, [pc, #32] @ (800153c ) 800151a: f012 fc3a bl 8013d92 800151e: 4603 mov r3, r0 8001520: 2b00 cmp r3, #0 8001522: d001 beq.n 8001528 { Error_Handler(); 8001524: f000 fcd2 bl 8001ecc } if (HAL_UARTEx_DisableFifoMode(&huart8) != HAL_OK) 8001528: 4804 ldr r0, [pc, #16] @ (800153c ) 800152a: f012 fbbb bl 8013ca4 800152e: 4603 mov r3, r0 8001530: 2b00 cmp r3, #0 8001532: d001 beq.n 8001538 { Error_Handler(); 8001534: f000 fcca bl 8001ecc } /* USER CODE BEGIN UART8_Init 2 */ /* USER CODE END UART8_Init 2 */ } 8001538: bf00 nop 800153a: bd80 pop {r7, pc} 800153c: 240005b8 .word 0x240005b8 8001540: 40007c00 .word 0x40007c00 08001544 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8001544: b580 push {r7, lr} 8001546: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8001548: 4b24 ldr r3, [pc, #144] @ (80015dc ) 800154a: 4a25 ldr r2, [pc, #148] @ (80015e0 ) 800154c: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 800154e: 4b23 ldr r3, [pc, #140] @ (80015dc ) 8001550: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8001554: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8001556: 4b21 ldr r3, [pc, #132] @ (80015dc ) 8001558: 2200 movs r2, #0 800155a: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 800155c: 4b1f ldr r3, [pc, #124] @ (80015dc ) 800155e: 2200 movs r2, #0 8001560: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8001562: 4b1e ldr r3, [pc, #120] @ (80015dc ) 8001564: 2200 movs r2, #0 8001566: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8001568: 4b1c ldr r3, [pc, #112] @ (80015dc ) 800156a: 220c movs r2, #12 800156c: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800156e: 4b1b ldr r3, [pc, #108] @ (80015dc ) 8001570: 2200 movs r2, #0 8001572: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8001574: 4b19 ldr r3, [pc, #100] @ (80015dc ) 8001576: 2200 movs r2, #0 8001578: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800157a: 4b18 ldr r3, [pc, #96] @ (80015dc ) 800157c: 2200 movs r2, #0 800157e: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001580: 4b16 ldr r3, [pc, #88] @ (80015dc ) 8001582: 2200 movs r2, #0 8001584: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_TXINVERT_INIT; 8001586: 4b15 ldr r3, [pc, #84] @ (80015dc ) 8001588: 2201 movs r2, #1 800158a: 629a str r2, [r3, #40] @ 0x28 huart1.AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; 800158c: 4b13 ldr r3, [pc, #76] @ (80015dc ) 800158e: f44f 3200 mov.w r2, #131072 @ 0x20000 8001592: 62da str r2, [r3, #44] @ 0x2c if (HAL_UART_Init(&huart1) != HAL_OK) 8001594: 4811 ldr r0, [pc, #68] @ (80015dc ) 8001596: f00f ff15 bl 80113c4 800159a: 4603 mov r3, r0 800159c: 2b00 cmp r3, #0 800159e: d001 beq.n 80015a4 { Error_Handler(); 80015a0: f000 fc94 bl 8001ecc } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 80015a4: 2100 movs r1, #0 80015a6: 480d ldr r0, [pc, #52] @ (80015dc ) 80015a8: f012 fbb5 bl 8013d16 80015ac: 4603 mov r3, r0 80015ae: 2b00 cmp r3, #0 80015b0: d001 beq.n 80015b6 { Error_Handler(); 80015b2: f000 fc8b bl 8001ecc } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80015b6: 2100 movs r1, #0 80015b8: 4808 ldr r0, [pc, #32] @ (80015dc ) 80015ba: f012 fbea bl 8013d92 80015be: 4603 mov r3, r0 80015c0: 2b00 cmp r3, #0 80015c2: d001 beq.n 80015c8 { Error_Handler(); 80015c4: f000 fc82 bl 8001ecc } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 80015c8: 4804 ldr r0, [pc, #16] @ (80015dc ) 80015ca: f012 fb6b bl 8013ca4 80015ce: 4603 mov r3, r0 80015d0: 2b00 cmp r3, #0 80015d2: d001 beq.n 80015d8 { Error_Handler(); 80015d4: f000 fc7a bl 8001ecc } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 80015d8: bf00 nop 80015da: bd80 pop {r7, pc} 80015dc: 2400064c .word 0x2400064c 80015e0: 40011000 .word 0x40011000 080015e4 : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80015e4: b580 push {r7, lr} 80015e6: b082 sub sp, #8 80015e8: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 80015ea: 4b15 ldr r3, [pc, #84] @ (8001640 ) 80015ec: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 80015f0: 4a13 ldr r2, [pc, #76] @ (8001640 ) 80015f2: f043 0301 orr.w r3, r3, #1 80015f6: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 80015fa: 4b11 ldr r3, [pc, #68] @ (8001640 ) 80015fc: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8001600: f003 0301 and.w r3, r3, #1 8001604: 607b str r3, [r7, #4] 8001606: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Stream0_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0); 8001608: 2200 movs r2, #0 800160a: 2105 movs r1, #5 800160c: 200b movs r0, #11 800160e: f006 faaf bl 8007b70 HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); 8001612: 200b movs r0, #11 8001614: f006 fac6 bl 8007ba4 /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); 8001618: 2200 movs r2, #0 800161a: 2105 movs r1, #5 800161c: 200c movs r0, #12 800161e: f006 faa7 bl 8007b70 HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); 8001622: 200c movs r0, #12 8001624: f006 fabe bl 8007ba4 /* DMA1_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); 8001628: 2200 movs r2, #0 800162a: 2105 movs r1, #5 800162c: 200d movs r0, #13 800162e: f006 fa9f bl 8007b70 HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); 8001632: 200d movs r0, #13 8001634: f006 fab6 bl 8007ba4 } 8001638: bf00 nop 800163a: 3708 adds r7, #8 800163c: 46bd mov sp, r7 800163e: bd80 pop {r7, pc} 8001640: 58024400 .word 0x58024400 08001644 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001644: b580 push {r7, lr} 8001646: b08c sub sp, #48 @ 0x30 8001648: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800164a: f107 031c add.w r3, r7, #28 800164e: 2200 movs r2, #0 8001650: 601a str r2, [r3, #0] 8001652: 605a str r2, [r3, #4] 8001654: 609a str r2, [r3, #8] 8001656: 60da str r2, [r3, #12] 8001658: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); 800165a: 4b58 ldr r3, [pc, #352] @ (80017bc ) 800165c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001660: 4a56 ldr r2, [pc, #344] @ (80017bc ) 8001662: f043 0380 orr.w r3, r3, #128 @ 0x80 8001666: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800166a: 4b54 ldr r3, [pc, #336] @ (80017bc ) 800166c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001670: f003 0380 and.w r3, r3, #128 @ 0x80 8001674: 61bb str r3, [r7, #24] 8001676: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001678: 4b50 ldr r3, [pc, #320] @ (80017bc ) 800167a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800167e: 4a4f ldr r2, [pc, #316] @ (80017bc ) 8001680: f043 0304 orr.w r3, r3, #4 8001684: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001688: 4b4c ldr r3, [pc, #304] @ (80017bc ) 800168a: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800168e: f003 0304 and.w r3, r3, #4 8001692: 617b str r3, [r7, #20] 8001694: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001696: 4b49 ldr r3, [pc, #292] @ (80017bc ) 8001698: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800169c: 4a47 ldr r2, [pc, #284] @ (80017bc ) 800169e: f043 0301 orr.w r3, r3, #1 80016a2: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016a6: 4b45 ldr r3, [pc, #276] @ (80017bc ) 80016a8: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ac: f003 0301 and.w r3, r3, #1 80016b0: 613b str r3, [r7, #16] 80016b2: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80016b4: 4b41 ldr r3, [pc, #260] @ (80017bc ) 80016b6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ba: 4a40 ldr r2, [pc, #256] @ (80017bc ) 80016bc: f043 0302 orr.w r3, r3, #2 80016c0: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016c4: 4b3d ldr r3, [pc, #244] @ (80017bc ) 80016c6: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016ca: f003 0302 and.w r3, r3, #2 80016ce: 60fb str r3, [r7, #12] 80016d0: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 80016d2: 4b3a ldr r3, [pc, #232] @ (80017bc ) 80016d4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016d8: 4a38 ldr r2, [pc, #224] @ (80017bc ) 80016da: f043 0310 orr.w r3, r3, #16 80016de: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80016e2: 4b36 ldr r3, [pc, #216] @ (80017bc ) 80016e4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016e8: f003 0310 and.w r3, r3, #16 80016ec: 60bb str r3, [r7, #8] 80016ee: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 80016f0: 4b32 ldr r3, [pc, #200] @ (80017bc ) 80016f2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80016f6: 4a31 ldr r2, [pc, #196] @ (80017bc ) 80016f8: f043 0308 orr.w r3, r3, #8 80016fc: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8001700: 4b2e ldr r3, [pc, #184] @ (80017bc ) 8001702: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8001706: f003 0308 and.w r3, r3, #8 800170a: 607b str r3, [r7, #4] 800170c: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 800170e: 2200 movs r2, #0 8001710: f24e 7180 movw r1, #59264 @ 0xe780 8001714: 482a ldr r0, [pc, #168] @ (80017c0 ) 8001716: f009 ff25 bl 800b564 |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7, GPIO_PIN_RESET); 800171a: 2200 movs r2, #0 800171c: 21f0 movs r1, #240 @ 0xf0 800171e: 4829 ldr r0, [pc, #164] @ (80017c4 ) 8001720: f009 ff20 bl 800b564 /*Configure GPIO pins : PE7 PE8 PE9 PE10 PE13 PE14 PE15 */ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 8001724: f24e 7380 movw r3, #59264 @ 0xe780 8001728: 61fb str r3, [r7, #28] |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800172a: 2301 movs r3, #1 800172c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800172e: 2300 movs r3, #0 8001730: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001732: 2300 movs r3, #0 8001734: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8001736: f107 031c add.w r3, r7, #28 800173a: 4619 mov r1, r3 800173c: 4820 ldr r0, [pc, #128] @ (80017c0 ) 800173e: f009 fd49 bl 800b1d4 /*Configure GPIO pins : PD8 PD9 PD10 PD11 PD12 PD13 */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 8001742: f44f 537c mov.w r3, #16128 @ 0x3f00 8001746: 61fb str r3, [r7, #28] |GPIO_PIN_12|GPIO_PIN_13; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 8001748: f44f 1344 mov.w r3, #3211264 @ 0x310000 800174c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800174e: 2300 movs r3, #0 8001750: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001752: f107 031c add.w r3, r7, #28 8001756: 4619 mov r1, r3 8001758: 481a ldr r0, [pc, #104] @ (80017c4 ) 800175a: f009 fd3b bl 800b1d4 /*Configure GPIO pin : PD3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 800175e: 2308 movs r3, #8 8001760: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8001762: 2300 movs r3, #0 8001764: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001766: 2300 movs r3, #0 8001768: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800176a: f107 031c add.w r3, r7, #28 800176e: 4619 mov r1, r3 8001770: 4814 ldr r0, [pc, #80] @ (80017c4 ) 8001772: f009 fd2f bl 800b1d4 /*Configure GPIO pins : PD4 PD5 PD6 PD7 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; 8001776: 23f0 movs r3, #240 @ 0xf0 8001778: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 800177a: 2301 movs r3, #1 800177c: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800177e: 2300 movs r3, #0 8001780: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001782: 2300 movs r3, #0 8001784: 62bb str r3, [r7, #40] @ 0x28 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8001786: f107 031c add.w r3, r7, #28 800178a: 4619 mov r1, r3 800178c: 480d ldr r0, [pc, #52] @ (80017c4 ) 800178e: f009 fd21 bl 800b1d4 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); 8001792: 2200 movs r2, #0 8001794: 2105 movs r1, #5 8001796: 2017 movs r0, #23 8001798: f006 f9ea bl 8007b70 HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); 800179c: 2017 movs r0, #23 800179e: f006 fa01 bl 8007ba4 HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); 80017a2: 2200 movs r2, #0 80017a4: 2105 movs r1, #5 80017a6: 2028 movs r0, #40 @ 0x28 80017a8: f006 f9e2 bl 8007b70 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 80017ac: 2028 movs r0, #40 @ 0x28 80017ae: f006 f9f9 bl 8007ba4 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 80017b2: bf00 nop 80017b4: 3730 adds r7, #48 @ 0x30 80017b6: 46bd mov sp, r7 80017b8: bd80 pop {r7, pc} 80017ba: bf00 nop 80017bc: 58024400 .word 0x58024400 80017c0: 58021000 .word 0x58021000 80017c4: 58020c00 .word 0x58020c00 080017c8 : /* USER CODE BEGIN 4 */ void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 80017c8: b580 push {r7, lr} 80017ca: b08e sub sp, #56 @ 0x38 80017cc: af00 add r7, sp, #0 80017ce: 6078 str r0, [r7, #4] if(hadc->Instance == ADC1) 80017d0: 687b ldr r3, [r7, #4] 80017d2: 681b ldr r3, [r3, #0] 80017d4: 4a67 ldr r2, [pc, #412] @ (8001974 ) 80017d6: 4293 cmp r3, r2 80017d8: d13f bne.n 800185a { DbgLEDToggle(DBG_LED4); 80017da: 2080 movs r0, #128 @ 0x80 80017dc: f001 fba6 bl 8002f2c SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc1Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80017e0: 4b65 ldr r3, [pc, #404] @ (8001978 ) 80017e2: f023 031f bic.w r3, r3, #31 80017e6: 637b str r3, [r7, #52] @ 0x34 80017e8: 2320 movs r3, #32 80017ea: 633b str r3, [r7, #48] @ 0x30 \param[in] dsize size of memory block (in number of bytes) */ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) if ( dsize > 0 ) { 80017ec: 6b3b ldr r3, [r7, #48] @ 0x30 80017ee: 2b00 cmp r3, #0 80017f0: dd1d ble.n 800182e int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80017f2: 6b7b ldr r3, [r7, #52] @ 0x34 80017f4: f003 021f and.w r2, r3, #31 80017f8: 6b3b ldr r3, [r7, #48] @ 0x30 80017fa: 4413 add r3, r2 80017fc: 62fb str r3, [r7, #44] @ 0x2c uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 80017fe: 6b7b ldr r3, [r7, #52] @ 0x34 8001800: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("dsb 0xF":::"memory"); 8001802: f3bf 8f4f dsb sy } 8001806: bf00 nop __DSB(); do { SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001808: 4a5c ldr r2, [pc, #368] @ (800197c ) 800180a: 6abb ldr r3, [r7, #40] @ 0x28 800180c: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001810: 6abb ldr r3, [r7, #40] @ 0x28 8001812: 3320 adds r3, #32 8001814: 62bb str r3, [r7, #40] @ 0x28 op_size -= __SCB_DCACHE_LINE_SIZE; 8001816: 6afb ldr r3, [r7, #44] @ 0x2c 8001818: 3b20 subs r3, #32 800181a: 62fb str r3, [r7, #44] @ 0x2c } while ( op_size > 0 ); 800181c: 6afb ldr r3, [r7, #44] @ 0x2c 800181e: 2b00 cmp r3, #0 8001820: dcf2 bgt.n 8001808 __ASM volatile ("dsb 0xF":::"memory"); 8001822: f3bf 8f4f dsb sy } 8001826: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001828: f3bf 8f6f isb sy } 800182c: bf00 nop __DSB(); __ISB(); } #endif } 800182e: bf00 nop if(adc1MeasDataQueue != NULL) 8001830: 4b53 ldr r3, [pc, #332] @ (8001980 ) 8001832: 681b ldr r3, [r3, #0] 8001834: 2b00 cmp r3, #0 8001836: d006 beq.n 8001846 { osMessageQueuePut(adc1MeasDataQueue, &adc1Data, 0, 0); 8001838: 4b51 ldr r3, [pc, #324] @ (8001980 ) 800183a: 6818 ldr r0, [r3, #0] 800183c: 2300 movs r3, #0 800183e: 2200 movs r2, #0 8001840: 494d ldr r1, [pc, #308] @ (8001978 ) 8001842: f012 ff37 bl 80146b4 } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001846: 2207 movs r2, #7 8001848: 494b ldr r1, [pc, #300] @ (8001978 ) 800184a: 484e ldr r0, [pc, #312] @ (8001984 ) 800184c: f004 feec bl 8006628 8001850: 4603 mov r3, r0 8001852: 2b00 cmp r3, #0 8001854: d001 beq.n 800185a { Error_Handler(); 8001856: f000 fb39 bl 8001ecc } } if(hadc->Instance == ADC2) 800185a: 687b ldr r3, [r7, #4] 800185c: 681b ldr r3, [r3, #0] 800185e: 4a4a ldr r2, [pc, #296] @ (8001988 ) 8001860: 4293 cmp r3, r2 8001862: d13c bne.n 80018de { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc2Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 8001864: 4b49 ldr r3, [pc, #292] @ (800198c ) 8001866: f023 031f bic.w r3, r3, #31 800186a: 627b str r3, [r7, #36] @ 0x24 800186c: 2320 movs r3, #32 800186e: 623b str r3, [r7, #32] if ( dsize > 0 ) { 8001870: 6a3b ldr r3, [r7, #32] 8001872: 2b00 cmp r3, #0 8001874: dd1d ble.n 80018b2 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 8001876: 6a7b ldr r3, [r7, #36] @ 0x24 8001878: f003 021f and.w r2, r3, #31 800187c: 6a3b ldr r3, [r7, #32] 800187e: 4413 add r3, r2 8001880: 61fb str r3, [r7, #28] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001882: 6a7b ldr r3, [r7, #36] @ 0x24 8001884: 61bb str r3, [r7, #24] __ASM volatile ("dsb 0xF":::"memory"); 8001886: f3bf 8f4f dsb sy } 800188a: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 800188c: 4a3b ldr r2, [pc, #236] @ (800197c ) 800188e: 69bb ldr r3, [r7, #24] 8001890: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001894: 69bb ldr r3, [r7, #24] 8001896: 3320 adds r3, #32 8001898: 61bb str r3, [r7, #24] op_size -= __SCB_DCACHE_LINE_SIZE; 800189a: 69fb ldr r3, [r7, #28] 800189c: 3b20 subs r3, #32 800189e: 61fb str r3, [r7, #28] } while ( op_size > 0 ); 80018a0: 69fb ldr r3, [r7, #28] 80018a2: 2b00 cmp r3, #0 80018a4: dcf2 bgt.n 800188c __ASM volatile ("dsb 0xF":::"memory"); 80018a6: f3bf 8f4f dsb sy } 80018aa: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 80018ac: f3bf 8f6f isb sy } 80018b0: bf00 nop } 80018b2: bf00 nop if(adc2MeasDataQueue != NULL) 80018b4: 4b36 ldr r3, [pc, #216] @ (8001990 ) 80018b6: 681b ldr r3, [r3, #0] 80018b8: 2b00 cmp r3, #0 80018ba: d006 beq.n 80018ca { osMessageQueuePut(adc2MeasDataQueue, &adc2Data, 0, 0); 80018bc: 4b34 ldr r3, [pc, #208] @ (8001990 ) 80018be: 6818 ldr r0, [r3, #0] 80018c0: 2300 movs r3, #0 80018c2: 2200 movs r2, #0 80018c4: 4931 ldr r1, [pc, #196] @ (800198c ) 80018c6: f012 fef5 bl 80146b4 } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 80018ca: 2203 movs r2, #3 80018cc: 492f ldr r1, [pc, #188] @ (800198c ) 80018ce: 4831 ldr r0, [pc, #196] @ (8001994 ) 80018d0: f004 feaa bl 8006628 80018d4: 4603 mov r3, r0 80018d6: 2b00 cmp r3, #0 80018d8: d001 beq.n 80018de { Error_Handler(); 80018da: f000 faf7 bl 8001ecc } } if(hadc->Instance == ADC3) 80018de: 687b ldr r3, [r7, #4] 80018e0: 681b ldr r3, [r3, #0] 80018e2: 4a2d ldr r2, [pc, #180] @ (8001998 ) 80018e4: 4293 cmp r3, r2 80018e6: d13c bne.n 8001962 { SCB_InvalidateDCache_by_Addr((uint32_t*)(((uint32_t)adc3Data.adcDataBuffer) & ~(uint32_t)0x1F), __SCB_DCACHE_LINE_SIZE); 80018e8: 4b2c ldr r3, [pc, #176] @ (800199c ) 80018ea: f023 031f bic.w r3, r3, #31 80018ee: 617b str r3, [r7, #20] 80018f0: 2320 movs r3, #32 80018f2: 613b str r3, [r7, #16] if ( dsize > 0 ) { 80018f4: 693b ldr r3, [r7, #16] 80018f6: 2b00 cmp r3, #0 80018f8: dd1d ble.n 8001936 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); 80018fa: 697b ldr r3, [r7, #20] 80018fc: f003 021f and.w r2, r3, #31 8001900: 693b ldr r3, [r7, #16] 8001902: 4413 add r3, r2 8001904: 60fb str r3, [r7, #12] uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; 8001906: 697b ldr r3, [r7, #20] 8001908: 60bb str r3, [r7, #8] __ASM volatile ("dsb 0xF":::"memory"); 800190a: f3bf 8f4f dsb sy } 800190e: bf00 nop SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ 8001910: 4a1a ldr r2, [pc, #104] @ (800197c ) 8001912: 68bb ldr r3, [r7, #8] 8001914: f8c2 325c str.w r3, [r2, #604] @ 0x25c op_addr += __SCB_DCACHE_LINE_SIZE; 8001918: 68bb ldr r3, [r7, #8] 800191a: 3320 adds r3, #32 800191c: 60bb str r3, [r7, #8] op_size -= __SCB_DCACHE_LINE_SIZE; 800191e: 68fb ldr r3, [r7, #12] 8001920: 3b20 subs r3, #32 8001922: 60fb str r3, [r7, #12] } while ( op_size > 0 ); 8001924: 68fb ldr r3, [r7, #12] 8001926: 2b00 cmp r3, #0 8001928: dcf2 bgt.n 8001910 __ASM volatile ("dsb 0xF":::"memory"); 800192a: f3bf 8f4f dsb sy } 800192e: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8001930: f3bf 8f6f isb sy } 8001934: bf00 nop } 8001936: bf00 nop if(adc3MeasDataQueue != NULL) 8001938: 4b19 ldr r3, [pc, #100] @ (80019a0 ) 800193a: 681b ldr r3, [r3, #0] 800193c: 2b00 cmp r3, #0 800193e: d006 beq.n 800194e { osMessageQueuePut(adc3MeasDataQueue, &adc3Data, 0, 0); 8001940: 4b17 ldr r3, [pc, #92] @ (80019a0 ) 8001942: 6818 ldr r0, [r3, #0] 8001944: 2300 movs r3, #0 8001946: 2200 movs r2, #0 8001948: 4914 ldr r1, [pc, #80] @ (800199c ) 800194a: f012 feb3 bl 80146b4 } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 800194e: 2205 movs r2, #5 8001950: 4912 ldr r1, [pc, #72] @ (800199c ) 8001952: 4814 ldr r0, [pc, #80] @ (80019a4 ) 8001954: f004 fe68 bl 8006628 8001958: 4603 mov r3, r0 800195a: 2b00 cmp r3, #0 800195c: d001 beq.n 8001962 { Error_Handler(); 800195e: f000 fab5 bl 8001ecc } }osTimerStop (debugLedTimerHandle); 8001962: 4b11 ldr r3, [pc, #68] @ (80019a8 ) 8001964: 681b ldr r3, [r3, #0] 8001966: 4618 mov r0, r3 8001968: f012 fcec bl 8014344 } 800196c: bf00 nop 800196e: 3738 adds r7, #56 @ 0x38 8001970: 46bd mov sp, r7 8001972: bd80 pop {r7, pc} 8001974: 40022000 .word 0x40022000 8001978: 240000c0 .word 0x240000c0 800197c: e000ed00 .word 0xe000ed00 8001980: 24000800 .word 0x24000800 8001984: 24000120 .word 0x24000120 8001988: 40022100 .word 0x40022100 800198c: 240000e0 .word 0x240000e0 8001990: 24000804 .word 0x24000804 8001994: 24000184 .word 0x24000184 8001998: 58026000 .word 0x58026000 800199c: 24000100 .word 0x24000100 80019a0: 24000808 .word 0x24000808 80019a4: 240001e8 .word 0x240001e8 80019a8: 240006e4 .word 0x240006e4 080019ac : void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80019ac: b580 push {r7, lr} 80019ae: b084 sub sp, #16 80019b0: af00 add r7, sp, #0 80019b2: 6078 str r0, [r7, #4] if (htim->Instance == TIM4) 80019b4: 687b ldr r3, [r7, #4] 80019b6: 681b ldr r3, [r3, #0] 80019b8: 4a61 ldr r2, [pc, #388] @ (8001b40 ) 80019ba: 4293 cmp r3, r2 80019bc: d15a bne.n 8001a74 { if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 80019be: 687b ldr r3, [r7, #4] 80019c0: 7f1b ldrb r3, [r3, #28] 80019c2: 2b04 cmp r3, #4 80019c4: d114 bne.n 80019f0 { if(encoderXChannelB > 0) 80019c6: 4b5f ldr r3, [pc, #380] @ (8001b44 ) 80019c8: 681b ldr r3, [r3, #0] 80019ca: 2b00 cmp r3, #0 80019cc: dd08 ble.n 80019e0 { encoderXChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 80019ce: 2108 movs r1, #8 80019d0: 6878 ldr r0, [r7, #4] 80019d2: f00e fdc7 bl 8010564 80019d6: 4603 mov r3, r0 80019d8: 461a mov r2, r3 80019da: 4b5b ldr r3, [pc, #364] @ (8001b48 ) 80019dc: 601a str r2, [r3, #0] 80019de: e01f b.n 8001a20 } else { encoderXChannelA = 1; 80019e0: 4b59 ldr r3, [pc, #356] @ (8001b48 ) 80019e2: 2201 movs r2, #1 80019e4: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 80019e6: 687b ldr r3, [r7, #4] 80019e8: 681b ldr r3, [r3, #0] 80019ea: 2200 movs r2, #0 80019ec: 625a str r2, [r3, #36] @ 0x24 80019ee: e017 b.n 8001a20 } } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 80019f0: 687b ldr r3, [r7, #4] 80019f2: 7f1b ldrb r3, [r3, #28] 80019f4: 2b08 cmp r3, #8 80019f6: d113 bne.n 8001a20 { if(encoderXChannelA > 0) 80019f8: 4b53 ldr r3, [pc, #332] @ (8001b48 ) 80019fa: 681b ldr r3, [r3, #0] 80019fc: 2b00 cmp r3, #0 80019fe: dd08 ble.n 8001a12 { encoderXChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001a00: 210c movs r1, #12 8001a02: 6878 ldr r0, [r7, #4] 8001a04: f00e fdae bl 8010564 8001a08: 4603 mov r3, r0 8001a0a: 461a mov r2, r3 8001a0c: 4b4d ldr r3, [pc, #308] @ (8001b44 ) 8001a0e: 601a str r2, [r3, #0] 8001a10: e006 b.n 8001a20 } else { encoderXChannelB = 1; 8001a12: 4b4c ldr r3, [pc, #304] @ (8001b44 ) 8001a14: 2201 movs r2, #1 8001a16: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001a18: 687b ldr r3, [r7, #4] 8001a1a: 681b ldr r3, [r3, #0] 8001a1c: 2200 movs r2, #0 8001a1e: 625a str r2, [r3, #36] @ 0x24 } } if((encoderXChannelA != 0) && (encoderXChannelB != 0)) 8001a20: 4b49 ldr r3, [pc, #292] @ (8001b48 ) 8001a22: 681b ldr r3, [r3, #0] 8001a24: 2b00 cmp r3, #0 8001a26: f000 8086 beq.w 8001b36 8001a2a: 4b46 ldr r3, [pc, #280] @ (8001b44 ) 8001a2c: 681b ldr r3, [r3, #0] 8001a2e: 2b00 cmp r3, #0 8001a30: f000 8081 beq.w 8001b36 { EncoderData encoderData = { 0 }; 8001a34: 2300 movs r3, #0 8001a36: 81bb strh r3, [r7, #12] encoderData.axe = encoderAxeX; 8001a38: 2300 movs r3, #0 8001a3a: 733b strb r3, [r7, #12] encoderData.direction = encoderXChannelA - encoderXChannelB < 0 ? encoderCW : encoderCCW; 8001a3c: 4b42 ldr r3, [pc, #264] @ (8001b48 ) 8001a3e: 681a ldr r2, [r3, #0] 8001a40: 4b40 ldr r3, [pc, #256] @ (8001b44 ) 8001a42: 681b ldr r3, [r3, #0] 8001a44: 1ad3 subs r3, r2, r3 8001a46: 43db mvns r3, r3 8001a48: 0fdb lsrs r3, r3, #31 8001a4a: b2db uxtb r3, r3 8001a4c: 737b strb r3, [r7, #13] if (encoderData.direction == encoderCCW) 8001a4e: 7b7b ldrb r3, [r7, #13] 8001a50: 2b01 cmp r3, #1 8001a52: d100 bne.n 8001a56 { asm("nop;"); 8001a54: bf00 nop } osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); 8001a56: 4b3d ldr r3, [pc, #244] @ (8001b4c ) 8001a58: 6818 ldr r0, [r3, #0] 8001a5a: f107 010c add.w r1, r7, #12 8001a5e: 2300 movs r3, #0 8001a60: 2200 movs r2, #0 8001a62: f012 fe27 bl 80146b4 encoderXChannelA = 0; 8001a66: 4b38 ldr r3, [pc, #224] @ (8001b48 ) 8001a68: 2200 movs r2, #0 8001a6a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001a6c: 4b35 ldr r3, [pc, #212] @ (8001b44 ) 8001a6e: 2200 movs r2, #0 8001a70: 601a str r2, [r3, #0] osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); encoderYChannelA = 0; encoderYChannelB = 0; } } } 8001a72: e060 b.n 8001b36 } else if (htim->Instance == TIM2) 8001a74: 687b ldr r3, [r7, #4] 8001a76: 681b ldr r3, [r3, #0] 8001a78: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001a7c: d15b bne.n 8001b36 if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_3) 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 7f1b ldrb r3, [r3, #28] 8001a82: 2b04 cmp r3, #4 8001a84: d114 bne.n 8001ab0 if(encoderYChannelB > 0) 8001a86: 4b32 ldr r3, [pc, #200] @ (8001b50 ) 8001a88: 681b ldr r3, [r3, #0] 8001a8a: 2b00 cmp r3, #0 8001a8c: dd08 ble.n 8001aa0 encoderYChannelA = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_3); 8001a8e: 2108 movs r1, #8 8001a90: 6878 ldr r0, [r7, #4] 8001a92: f00e fd67 bl 8010564 8001a96: 4603 mov r3, r0 8001a98: 461a mov r2, r3 8001a9a: 4b2e ldr r3, [pc, #184] @ (8001b54 ) 8001a9c: 601a str r2, [r3, #0] 8001a9e: e01f b.n 8001ae0 encoderYChannelA = 1; 8001aa0: 4b2c ldr r3, [pc, #176] @ (8001b54 ) 8001aa2: 2201 movs r2, #1 8001aa4: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001aa6: 687b ldr r3, [r7, #4] 8001aa8: 681b ldr r3, [r3, #0] 8001aaa: 2200 movs r2, #0 8001aac: 625a str r2, [r3, #36] @ 0x24 8001aae: e017 b.n 8001ae0 } else if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_4) 8001ab0: 687b ldr r3, [r7, #4] 8001ab2: 7f1b ldrb r3, [r3, #28] 8001ab4: 2b08 cmp r3, #8 8001ab6: d113 bne.n 8001ae0 if(encoderYChannelA > 0) 8001ab8: 4b26 ldr r3, [pc, #152] @ (8001b54 ) 8001aba: 681b ldr r3, [r3, #0] 8001abc: 2b00 cmp r3, #0 8001abe: dd08 ble.n 8001ad2 encoderYChannelB = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_4); 8001ac0: 210c movs r1, #12 8001ac2: 6878 ldr r0, [r7, #4] 8001ac4: f00e fd4e bl 8010564 8001ac8: 4603 mov r3, r0 8001aca: 461a mov r2, r3 8001acc: 4b20 ldr r3, [pc, #128] @ (8001b50 ) 8001ace: 601a str r2, [r3, #0] 8001ad0: e006 b.n 8001ae0 encoderYChannelB = 1; 8001ad2: 4b1f ldr r3, [pc, #124] @ (8001b50 ) 8001ad4: 2201 movs r2, #1 8001ad6: 601a str r2, [r3, #0] __HAL_TIM_SET_COUNTER(htim,0); 8001ad8: 687b ldr r3, [r7, #4] 8001ada: 681b ldr r3, [r3, #0] 8001adc: 2200 movs r2, #0 8001ade: 625a str r2, [r3, #36] @ 0x24 if((encoderYChannelA != 0) && (encoderYChannelB != 0)) 8001ae0: 4b1c ldr r3, [pc, #112] @ (8001b54 ) 8001ae2: 681b ldr r3, [r3, #0] 8001ae4: 2b00 cmp r3, #0 8001ae6: d026 beq.n 8001b36 8001ae8: 4b19 ldr r3, [pc, #100] @ (8001b50 ) 8001aea: 681b ldr r3, [r3, #0] 8001aec: 2b00 cmp r3, #0 8001aee: d022 beq.n 8001b36 EncoderData encoderData = { 0 }; 8001af0: 2300 movs r3, #0 8001af2: 813b strh r3, [r7, #8] encoderData.axe = encoderAxeY; 8001af4: 2301 movs r3, #1 8001af6: 723b strb r3, [r7, #8] encoderData.direction = encoderYChannelA - encoderYChannelB < 0 ? encoderCW : encoderCCW; 8001af8: 4b16 ldr r3, [pc, #88] @ (8001b54 ) 8001afa: 681a ldr r2, [r3, #0] 8001afc: 4b14 ldr r3, [pc, #80] @ (8001b50 ) 8001afe: 681b ldr r3, [r3, #0] 8001b00: 1ad3 subs r3, r2, r3 8001b02: 43db mvns r3, r3 8001b04: 0fdb lsrs r3, r3, #31 8001b06: b2db uxtb r3, r3 8001b08: 727b strb r3, [r7, #9] if (encoderData.direction == encoderCCW) 8001b0a: 7a7b ldrb r3, [r7, #9] 8001b0c: 2b01 cmp r3, #1 8001b0e: d100 bne.n 8001b12 asm("nop;"); 8001b10: bf00 nop if (encoderData.direction == encoderCW) 8001b12: 7a7b ldrb r3, [r7, #9] 8001b14: 2b00 cmp r3, #0 8001b16: d100 bne.n 8001b1a asm("nop;"); 8001b18: bf00 nop osMessageQueuePut(encoderDataQueue, &encoderData, 0, 0); 8001b1a: 4b0c ldr r3, [pc, #48] @ (8001b4c ) 8001b1c: 6818 ldr r0, [r3, #0] 8001b1e: f107 0108 add.w r1, r7, #8 8001b22: 2300 movs r3, #0 8001b24: 2200 movs r2, #0 8001b26: f012 fdc5 bl 80146b4 encoderYChannelA = 0; 8001b2a: 4b0a ldr r3, [pc, #40] @ (8001b54 ) 8001b2c: 2200 movs r2, #0 8001b2e: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001b30: 4b07 ldr r3, [pc, #28] @ (8001b50 ) 8001b32: 2200 movs r2, #0 8001b34: 601a str r2, [r3, #0] } 8001b36: bf00 nop 8001b38: 3710 adds r7, #16 8001b3a: 46bd mov sp, r7 8001b3c: bd80 pop {r7, pc} 8001b3e: bf00 nop 8001b40: 40000800 .word 0x40000800 8001b44: 240007e0 .word 0x240007e0 8001b48: 240007dc .word 0x240007dc 8001b4c: 24000810 .word 0x24000810 8001b50: 240007e8 .word 0x240007e8 8001b54: 240007e4 .word 0x240007e4 08001b58 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartDefaultTask */ void StartDefaultTask(void *argument) { 8001b58: b580 push {r7, lr} 8001b5a: b082 sub sp, #8 8001b5c: af00 add r7, sp, #0 8001b5e: 6078 str r0, [r7, #4] /* USER CODE BEGIN 5 */ #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001b60: 485e ldr r0, [pc, #376] @ (8001cdc ) 8001b62: f009 fd9b bl 800b69c #endif SelectCurrentSensorGain(CurrentSensorL1, csGain3); 8001b66: 2102 movs r1, #2 8001b68: 2000 movs r0, #0 8001b6a: f001 f9fd bl 8002f68 SelectCurrentSensorGain(CurrentSensorL2, csGain3); 8001b6e: 2102 movs r1, #2 8001b70: 2001 movs r0, #1 8001b72: f001 f9f9 bl 8002f68 SelectCurrentSensorGain(CurrentSensorL3, csGain3); 8001b76: 2102 movs r1, #2 8001b78: 2002 movs r0, #2 8001b7a: f001 f9f5 bl 8002f68 EnableCurrentSensors(); 8001b7e: f001 f9e7 bl 8002f50 osDelay(pdMS_TO_TICKS(100)); 8001b82: 2064 movs r0, #100 @ 0x64 8001b84: f012 fb03 bl 801418e #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001b88: 4854 ldr r0, [pc, #336] @ (8001cdc ) 8001b8a: f009 fd87 bl 800b69c #endif if(HAL_TIM_Base_Start(&htim8) != HAL_OK) 8001b8e: 4854 ldr r0, [pc, #336] @ (8001ce0 ) 8001b90: f00d fca2 bl 800f4d8 8001b94: 4603 mov r3, r0 8001b96: 2b00 cmp r3, #0 8001b98: d001 beq.n 8001b9e { Error_Handler(); 8001b9a: f000 f997 bl 8001ecc } if(HAL_TIM_Base_Start_IT(&htim2) != HAL_OK) 8001b9e: 4851 ldr r0, [pc, #324] @ (8001ce4 ) 8001ba0: f00d fd0a bl 800f5b8 8001ba4: 4603 mov r3, r0 8001ba6: 2b00 cmp r3, #0 8001ba8: d001 beq.n 8001bae { Error_Handler(); 8001baa: f000 f98f bl 8001ecc } if(HAL_TIM_Base_Start_IT(&htim4) != HAL_OK) 8001bae: 484e ldr r0, [pc, #312] @ (8001ce8 ) 8001bb0: f00d fd02 bl 800f5b8 8001bb4: 4603 mov r3, r0 8001bb6: 2b00 cmp r3, #0 8001bb8: d001 beq.n 8001bbe { Error_Handler(); 8001bba: f000 f987 bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_3) != HAL_OK) 8001bbe: 2108 movs r1, #8 8001bc0: 4849 ldr r0, [pc, #292] @ (8001ce8 ) 8001bc2: f00d ffcf bl 800fb64 8001bc6: 4603 mov r3, r0 8001bc8: 2b00 cmp r3, #0 8001bca: d001 beq.n 8001bd0 { Error_Handler(); 8001bcc: f000 f97e bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim4, TIM_CHANNEL_4) != HAL_OK) 8001bd0: 210c movs r1, #12 8001bd2: 4845 ldr r0, [pc, #276] @ (8001ce8 ) 8001bd4: f00d ffc6 bl 800fb64 8001bd8: 4603 mov r3, r0 8001bda: 2b00 cmp r3, #0 8001bdc: d001 beq.n 8001be2 { Error_Handler(); 8001bde: f000 f975 bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_3) != HAL_OK) 8001be2: 2108 movs r1, #8 8001be4: 483f ldr r0, [pc, #252] @ (8001ce4 ) 8001be6: f00d ffbd bl 800fb64 8001bea: 4603 mov r3, r0 8001bec: 2b00 cmp r3, #0 8001bee: d001 beq.n 8001bf4 { Error_Handler(); 8001bf0: f000 f96c bl 8001ecc } if(HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_4) != HAL_OK) 8001bf4: 210c movs r1, #12 8001bf6: 483b ldr r0, [pc, #236] @ (8001ce4 ) 8001bf8: f00d ffb4 bl 800fb64 8001bfc: 4603 mov r3, r0 8001bfe: 2b00 cmp r3, #0 8001c00: d001 beq.n 8001c06 { Error_Handler(); 8001c02: f000 f963 bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1Data.adcDataBuffer, ADC1LastData) != HAL_OK) 8001c06: 2207 movs r2, #7 8001c08: 4938 ldr r1, [pc, #224] @ (8001cec ) 8001c0a: 4839 ldr r0, [pc, #228] @ (8001cf0 ) 8001c0c: f004 fd0c bl 8006628 8001c10: 4603 mov r3, r0 8001c12: 2b00 cmp r3, #0 8001c14: d001 beq.n 8001c1a { Error_Handler(); 8001c16: f000 f959 bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2Data.adcDataBuffer, ADC2LastData) != HAL_OK) 8001c1a: 2203 movs r2, #3 8001c1c: 4935 ldr r1, [pc, #212] @ (8001cf4 ) 8001c1e: 4836 ldr r0, [pc, #216] @ (8001cf8 ) 8001c20: f004 fd02 bl 8006628 8001c24: 4603 mov r3, r0 8001c26: 2b00 cmp r3, #0 8001c28: d001 beq.n 8001c2e { Error_Handler(); 8001c2a: f000 f94f bl 8001ecc } if(HAL_ADC_Start_DMA(&hadc3, (uint32_t *)adc3Data.adcDataBuffer, ADC3LastData) != HAL_OK) 8001c2e: 2205 movs r2, #5 8001c30: 4932 ldr r1, [pc, #200] @ (8001cfc ) 8001c32: 4833 ldr r0, [pc, #204] @ (8001d00 ) 8001c34: f004 fcf8 bl 8006628 8001c38: 4603 mov r3, r0 8001c3a: 2b00 cmp r3, #0 8001c3c: d001 beq.n 8001c42 { Error_Handler(); 8001c3e: f000 f945 bl 8001ecc } HAL_COMP_Start(&hcomp1); 8001c42: 4830 ldr r0, [pc, #192] @ (8001d04 ) 8001c44: f005 fe74 bl 8007930 #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001c48: 4824 ldr r0, [pc, #144] @ (8001cdc ) 8001c4a: f009 fd27 bl 800b69c #endif /* Infinite loop */ for(;;) { osDelay(pdMS_TO_TICKS(100)); 8001c4e: 2064 movs r0, #100 @ 0x64 8001c50: f012 fa9d bl 801418e #ifdef WATCHDOG_ENABLED HAL_IWDG_Refresh(&hiwdg1); 8001c54: 4821 ldr r0, [pc, #132] @ (8001cdc ) 8001c56: f009 fd21 bl 800b69c #endif if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001c5a: 2100 movs r1, #0 8001c5c: 482a ldr r0, [pc, #168] @ (8001d08 ) 8001c5e: f00e fce3 bl 8010628 8001c62: 4603 mov r3, r0 8001c64: 2b01 cmp r3, #1 8001c66: d118 bne.n 8001c9a HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_2) == HAL_TIM_CHANNEL_STATE_READY) 8001c68: 2104 movs r1, #4 8001c6a: 4827 ldr r0, [pc, #156] @ (8001d08 ) 8001c6c: f00e fcdc bl 8010628 8001c70: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_1) == HAL_TIM_CHANNEL_STATE_READY && 8001c72: 2b01 cmp r3, #1 8001c74: d111 bne.n 8001c9a { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001c76: 4b25 ldr r3, [pc, #148] @ (8001d0c ) 8001c78: 681b ldr r3, [r3, #0] 8001c7a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001c7e: 4618 mov r0, r3 8001c80: f012 fc1d bl 80144be 8001c84: 4603 mov r3, r0 8001c86: 2b00 cmp r3, #0 8001c88: d107 bne.n 8001c9a { sensorsInfo.motorXStatus = 0; 8001c8a: 4b21 ldr r3, [pc, #132] @ (8001d10 ) 8001c8c: 2200 movs r2, #0 8001c8e: 751a strb r2, [r3, #20] osMutexRelease(sensorsInfoMutex); 8001c90: 4b1e ldr r3, [pc, #120] @ (8001d0c ) 8001c92: 681b ldr r3, [r3, #0] 8001c94: 4618 mov r0, r3 8001c96: f012 fc5d bl 8014554 } } if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001c9a: 2108 movs r1, #8 8001c9c: 481a ldr r0, [pc, #104] @ (8001d08 ) 8001c9e: f00e fcc3 bl 8010628 8001ca2: 4603 mov r3, r0 8001ca4: 2b01 cmp r3, #1 8001ca6: d1d2 bne.n 8001c4e HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_4) == HAL_TIM_CHANNEL_STATE_READY) 8001ca8: 210c movs r1, #12 8001caa: 4817 ldr r0, [pc, #92] @ (8001d08 ) 8001cac: f00e fcbc bl 8010628 8001cb0: 4603 mov r3, r0 if(HAL_TIM_GetChannelState(&htim3, TIM_CHANNEL_3) == HAL_TIM_CHANNEL_STATE_READY && 8001cb2: 2b01 cmp r3, #1 8001cb4: d1cb bne.n 8001c4e { if(osMutexAcquire(sensorsInfoMutex, osWaitForever) == osOK) 8001cb6: 4b15 ldr r3, [pc, #84] @ (8001d0c ) 8001cb8: 681b ldr r3, [r3, #0] 8001cba: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8001cbe: 4618 mov r0, r3 8001cc0: f012 fbfd bl 80144be 8001cc4: 4603 mov r3, r0 8001cc6: 2b00 cmp r3, #0 8001cc8: d1c1 bne.n 8001c4e { sensorsInfo.motorYStatus = 0; 8001cca: 4b11 ldr r3, [pc, #68] @ (8001d10 ) 8001ccc: 2200 movs r2, #0 8001cce: 755a strb r2, [r3, #21] osMutexRelease(sensorsInfoMutex); 8001cd0: 4b0e ldr r3, [pc, #56] @ (8001d0c ) 8001cd2: 681b ldr r3, [r3, #0] 8001cd4: 4618 mov r0, r3 8001cd6: f012 fc3d bl 8014554 osDelay(pdMS_TO_TICKS(100)); 8001cda: e7b8 b.n 8001c4e 8001cdc: 24000418 .word 0x24000418 8001ce0: 2400056c .word 0x2400056c 8001ce4: 24000488 .word 0x24000488 8001ce8: 24000520 .word 0x24000520 8001cec: 240000c0 .word 0x240000c0 8001cf0: 24000120 .word 0x24000120 8001cf4: 240000e0 .word 0x240000e0 8001cf8: 24000184 .word 0x24000184 8001cfc: 24000100 .word 0x24000100 8001d00: 240001e8 .word 0x240001e8 8001d04: 240003b4 .word 0x240003b4 8001d08: 240004d4 .word 0x240004d4 8001d0c: 2400081c .word 0x2400081c 8001d10: 24000860 .word 0x24000860 08001d14 : /* USER CODE END 5 */ } /* debugLedTimerCallback function */ void debugLedTimerCallback(void *argument) { 8001d14: b580 push {r7, lr} 8001d16: b082 sub sp, #8 8001d18: af00 add r7, sp, #0 8001d1a: 6078 str r0, [r7, #4] /* USER CODE BEGIN debugLedTimerCallback */ DbgLEDOff (DBG_LED1); 8001d1c: 2010 movs r0, #16 8001d1e: f001 f8f3 bl 8002f08 /* USER CODE END debugLedTimerCallback */ } 8001d22: bf00 nop 8001d24: 3708 adds r7, #8 8001d26: 46bd mov sp, r7 8001d28: bd80 pop {r7, pc} ... 08001d2c : /* fanTimerCallback function */ void fanTimerCallback(void *argument) { 8001d2c: b580 push {r7, lr} 8001d2e: b082 sub sp, #8 8001d30: af00 add r7, sp, #0 8001d32: 6078 str r0, [r7, #4] /* USER CODE BEGIN fanTimerCallback */ HAL_TIM_PWM_Stop(&htim1, TIM_CHANNEL_2); 8001d34: 2104 movs r1, #4 8001d36: 4803 ldr r0, [pc, #12] @ (8001d44 ) 8001d38: f00d fe1c bl 800f974 /* USER CODE END fanTimerCallback */ } 8001d3c: bf00 nop 8001d3e: 3708 adds r7, #8 8001d40: 46bd mov sp, r7 8001d42: bd80 pop {r7, pc} 8001d44: 2400043c .word 0x2400043c 08001d48 : /* motorXTimerCallback function */ void motorXTimerCallback(void *argument) { 8001d48: b580 push {r7, lr} 8001d4a: b084 sub sp, #16 8001d4c: af02 add r7, sp, #8 8001d4e: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorXTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, HiZ, 0); 8001d50: 2300 movs r3, #0 8001d52: 9301 str r3, [sp, #4] 8001d54: 2300 movs r3, #0 8001d56: 9300 str r3, [sp, #0] 8001d58: 2304 movs r3, #4 8001d5a: 2200 movs r2, #0 8001d5c: 4907 ldr r1, [pc, #28] @ (8001d7c ) 8001d5e: 4808 ldr r0, [pc, #32] @ (8001d80 ) 8001d60: f001 fa87 bl 8003272 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_1); 8001d64: 2100 movs r1, #0 8001d66: 4806 ldr r0, [pc, #24] @ (8001d80 ) 8001d68: f00d fe04 bl 800f974 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_2); 8001d6c: 2104 movs r1, #4 8001d6e: 4804 ldr r0, [pc, #16] @ (8001d80 ) 8001d70: f00d fe00 bl 800f974 /* USER CODE END motorXTimerCallback */ } 8001d74: bf00 nop 8001d76: 3708 adds r7, #8 8001d78: 46bd mov sp, r7 8001d7a: bd80 pop {r7, pc} 8001d7c: 240007c0 .word 0x240007c0 8001d80: 240004d4 .word 0x240004d4 08001d84 : /* motorYTimerCallback function */ void motorYTimerCallback(void *argument) { 8001d84: b580 push {r7, lr} 8001d86: b084 sub sp, #16 8001d88: af02 add r7, sp, #8 8001d8a: 6078 str r0, [r7, #4] /* USER CODE BEGIN motorYTimerCallback */ MotorAction(&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, HiZ, 0); 8001d8c: 2300 movs r3, #0 8001d8e: 9301 str r3, [sp, #4] 8001d90: 2300 movs r3, #0 8001d92: 9300 str r3, [sp, #0] 8001d94: 230c movs r3, #12 8001d96: 2208 movs r2, #8 8001d98: 4907 ldr r1, [pc, #28] @ (8001db8 ) 8001d9a: 4808 ldr r0, [pc, #32] @ (8001dbc ) 8001d9c: f001 fa69 bl 8003272 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_3); 8001da0: 2108 movs r1, #8 8001da2: 4806 ldr r0, [pc, #24] @ (8001dbc ) 8001da4: f00d fde6 bl 800f974 HAL_TIM_PWM_Stop(&htim3, TIM_CHANNEL_4); 8001da8: 210c movs r1, #12 8001daa: 4804 ldr r0, [pc, #16] @ (8001dbc ) 8001dac: f00d fde2 bl 800f974 /* USER CODE END motorYTimerCallback */ } 8001db0: bf00 nop 8001db2: 3708 adds r7, #8 8001db4: 46bd mov sp, r7 8001db6: bd80 pop {r7, pc} 8001db8: 240007c0 .word 0x240007c0 8001dbc: 240004d4 .word 0x240004d4 08001dc0 : /* MPU Configuration */ void MPU_Config(void) { 8001dc0: b580 push {r7, lr} 8001dc2: b084 sub sp, #16 8001dc4: af00 add r7, sp, #0 MPU_Region_InitTypeDef MPU_InitStruct = {0}; 8001dc6: 463b mov r3, r7 8001dc8: 2200 movs r2, #0 8001dca: 601a str r2, [r3, #0] 8001dcc: 605a str r2, [r3, #4] 8001dce: 609a str r2, [r3, #8] 8001dd0: 60da str r2, [r3, #12] /* Disables the MPU */ HAL_MPU_Disable(); 8001dd2: f005 fef5 bl 8007bc0 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Enable = MPU_REGION_ENABLE; 8001dd6: 2301 movs r3, #1 8001dd8: 703b strb r3, [r7, #0] MPU_InitStruct.Number = MPU_REGION_NUMBER0; 8001dda: 2300 movs r3, #0 8001ddc: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x0; 8001dde: 2300 movs r3, #0 8001de0: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; 8001de2: 231f movs r3, #31 8001de4: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x87; 8001de6: 2387 movs r3, #135 @ 0x87 8001de8: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001dea: 2300 movs r3, #0 8001dec: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; 8001dee: 2300 movs r3, #0 8001df0: 72fb strb r3, [r7, #11] MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; 8001df2: 2301 movs r3, #1 8001df4: 733b strb r3, [r7, #12] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001df6: 2301 movs r3, #1 8001df8: 737b strb r3, [r7, #13] MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; 8001dfa: 2300 movs r3, #0 8001dfc: 73bb strb r3, [r7, #14] MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; 8001dfe: 2300 movs r3, #0 8001e00: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e02: 463b mov r3, r7 8001e04: 4618 mov r0, r3 8001e06: f005 ff13 bl 8007c30 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER1; 8001e0a: 2301 movs r3, #1 8001e0c: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24020000; 8001e0e: 4b13 ldr r3, [pc, #76] @ (8001e5c ) 8001e10: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; 8001e12: 2310 movs r3, #16 8001e14: 723b strb r3, [r7, #8] MPU_InitStruct.SubRegionDisable = 0x0; 8001e16: 2300 movs r3, #0 8001e18: 727b strb r3, [r7, #9] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; 8001e1a: 2301 movs r3, #1 8001e1c: 72bb strb r3, [r7, #10] MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; 8001e1e: 2303 movs r3, #3 8001e20: 72fb strb r3, [r7, #11] MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; 8001e22: 2300 movs r3, #0 8001e24: 737b strb r3, [r7, #13] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e26: 463b mov r3, r7 8001e28: 4618 mov r0, r3 8001e2a: f005 ff01 bl 8007c30 /** Initializes and configures the Region and the memory to be protected */ MPU_InitStruct.Number = MPU_REGION_NUMBER2; 8001e2e: 2302 movs r3, #2 8001e30: 707b strb r3, [r7, #1] MPU_InitStruct.BaseAddress = 0x24040000; 8001e32: 4b0b ldr r3, [pc, #44] @ (8001e60 ) 8001e34: 607b str r3, [r7, #4] MPU_InitStruct.Size = MPU_REGION_SIZE_512B; 8001e36: 2308 movs r3, #8 8001e38: 723b strb r3, [r7, #8] MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; 8001e3a: 2300 movs r3, #0 8001e3c: 72bb strb r3, [r7, #10] MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; 8001e3e: 2301 movs r3, #1 8001e40: 737b strb r3, [r7, #13] MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; 8001e42: 2301 movs r3, #1 8001e44: 73fb strb r3, [r7, #15] HAL_MPU_ConfigRegion(&MPU_InitStruct); 8001e46: 463b mov r3, r7 8001e48: 4618 mov r0, r3 8001e4a: f005 fef1 bl 8007c30 /* Enables the MPU */ HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); 8001e4e: 2004 movs r0, #4 8001e50: f005 fece bl 8007bf0 } 8001e54: bf00 nop 8001e56: 3710 adds r7, #16 8001e58: 46bd mov sp, r7 8001e5a: bd80 pop {r7, pc} 8001e5c: 24020000 .word 0x24020000 8001e60: 24040000 .word 0x24040000 08001e64 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001e64: b580 push {r7, lr} 8001e66: b082 sub sp, #8 8001e68: af00 add r7, sp, #0 8001e6a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) { 8001e6c: 687b ldr r3, [r7, #4] 8001e6e: 681b ldr r3, [r3, #0] 8001e70: 4a10 ldr r2, [pc, #64] @ (8001eb4 ) 8001e72: 4293 cmp r3, r2 8001e74: d102 bne.n 8001e7c HAL_IncTick(); 8001e76: f003 ffc1 bl 8005dfc { encoderYChannelA = 0; encoderYChannelB = 0; } /* USER CODE END Callback 1 */ } 8001e7a: e016 b.n 8001eaa else if (htim->Instance == TIM4) 8001e7c: 687b ldr r3, [r7, #4] 8001e7e: 681b ldr r3, [r3, #0] 8001e80: 4a0d ldr r2, [pc, #52] @ (8001eb8 ) 8001e82: 4293 cmp r3, r2 8001e84: d106 bne.n 8001e94 encoderXChannelA = 0; 8001e86: 4b0d ldr r3, [pc, #52] @ (8001ebc ) 8001e88: 2200 movs r2, #0 8001e8a: 601a str r2, [r3, #0] encoderXChannelB = 0; 8001e8c: 4b0c ldr r3, [pc, #48] @ (8001ec0 ) 8001e8e: 2200 movs r2, #0 8001e90: 601a str r2, [r3, #0] } 8001e92: e00a b.n 8001eaa else if (htim->Instance == TIM2) 8001e94: 687b ldr r3, [r7, #4] 8001e96: 681b ldr r3, [r3, #0] 8001e98: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001e9c: d105 bne.n 8001eaa encoderYChannelA = 0; 8001e9e: 4b09 ldr r3, [pc, #36] @ (8001ec4 ) 8001ea0: 2200 movs r2, #0 8001ea2: 601a str r2, [r3, #0] encoderYChannelB = 0; 8001ea4: 4b08 ldr r3, [pc, #32] @ (8001ec8 ) 8001ea6: 2200 movs r2, #0 8001ea8: 601a str r2, [r3, #0] } 8001eaa: bf00 nop 8001eac: 3708 adds r7, #8 8001eae: 46bd mov sp, r7 8001eb0: bd80 pop {r7, pc} 8001eb2: bf00 nop 8001eb4: 40001000 .word 0x40001000 8001eb8: 40000800 .word 0x40000800 8001ebc: 240007dc .word 0x240007dc 8001ec0: 240007e0 .word 0x240007e0 8001ec4: 240007e4 .word 0x240007e4 8001ec8: 240007e8 .word 0x240007e8 08001ecc : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8001ecc: b580 push {r7, lr} 8001ece: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8001ed0: b672 cpsid i } 8001ed2: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); NVIC_SystemReset(); 8001ed4: f7fe fb88 bl 80005e8 <__NVIC_SystemReset> 08001ed8 : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; //extern osMutexId_t positionSettingMutex; void MeasTasksInit (void) { 8001ed8: b580 push {r7, lr} 8001eda: b0ae sub sp, #184 @ 0xb8 8001edc: af00 add r7, sp, #0 vRefmVMutex = osMutexNew (NULL); 8001ede: 2000 movs r0, #0 8001ee0: f012 fa67 bl 80143b2 8001ee4: 4603 mov r3, r0 8001ee6: 4a58 ldr r2, [pc, #352] @ (8002048 ) 8001ee8: 6013 str r3, [r2, #0] resMeasurementsMutex = osMutexNew (NULL); 8001eea: 2000 movs r0, #0 8001eec: f012 fa61 bl 80143b2 8001ef0: 4603 mov r3, r0 8001ef2: 4a56 ldr r2, [pc, #344] @ (800204c ) 8001ef4: 6013 str r3, [r2, #0] sensorsInfoMutex = osMutexNew (NULL); 8001ef6: 2000 movs r0, #0 8001ef8: f012 fa5b bl 80143b2 8001efc: 4603 mov r3, r0 8001efe: 4a54 ldr r2, [pc, #336] @ (8002050 ) 8001f00: 6013 str r3, [r2, #0] ILxRefMutex = osMutexNew (NULL); 8001f02: 2000 movs r0, #0 8001f04: f012 fa55 bl 80143b2 8001f08: 4603 mov r3, r0 8001f0a: 4a52 ldr r2, [pc, #328] @ (8002054 ) 8001f0c: 6013 str r3, [r2, #0] adc1MeasDataQueue = osMessageQueueNew (8, sizeof (ADC1_Data), NULL); 8001f0e: 2200 movs r2, #0 8001f10: 2120 movs r1, #32 8001f12: 2008 movs r0, #8 8001f14: f012 fb5b bl 80145ce 8001f18: 4603 mov r3, r0 8001f1a: 4a4f ldr r2, [pc, #316] @ (8002058 ) 8001f1c: 6013 str r3, [r2, #0] adc2MeasDataQueue = osMessageQueueNew (8, sizeof (ADC2_Data), NULL); 8001f1e: 2200 movs r2, #0 8001f20: 2120 movs r1, #32 8001f22: 2008 movs r0, #8 8001f24: f012 fb53 bl 80145ce 8001f28: 4603 mov r3, r0 8001f2a: 4a4c ldr r2, [pc, #304] @ (800205c ) 8001f2c: 6013 str r3, [r2, #0] adc3MeasDataQueue = osMessageQueueNew (8, sizeof (ADC3_Data), NULL); 8001f2e: 2200 movs r2, #0 8001f30: 2120 movs r1, #32 8001f32: 2008 movs r0, #8 8001f34: f012 fb4b bl 80145ce 8001f38: 4603 mov r3, r0 8001f3a: 4a49 ldr r2, [pc, #292] @ (8002060 ) 8001f3c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1MeasTask = { 0 }; 8001f3e: f107 0394 add.w r3, r7, #148 @ 0x94 8001f42: 2224 movs r2, #36 @ 0x24 8001f44: 2100 movs r1, #0 8001f46: 4618 mov r0, r3 8001f48: f016 f9e6 bl 8018318 osThreadAttr_t osThreadAttradc2MeasTask = { 0 }; 8001f4c: f107 0370 add.w r3, r7, #112 @ 0x70 8001f50: 2224 movs r2, #36 @ 0x24 8001f52: 2100 movs r1, #0 8001f54: 4618 mov r0, r3 8001f56: f016 f9df bl 8018318 osThreadAttr_t osThreadAttradc3MeasTask = { 0 }; 8001f5a: f107 034c add.w r3, r7, #76 @ 0x4c 8001f5e: 2224 movs r2, #36 @ 0x24 8001f60: 2100 movs r1, #0 8001f62: 4618 mov r0, r3 8001f64: f016 f9d8 bl 8018318 osThreadAttradc1MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f68: f44f 6380 mov.w r3, #1024 @ 0x400 8001f6c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 osThreadAttradc1MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001f70: 2330 movs r3, #48 @ 0x30 8001f72: f8c7 30ac str.w r3, [r7, #172] @ 0xac osThreadAttradc2MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f76: f44f 6380 mov.w r3, #1024 @ 0x400 8001f7a: f8c7 3084 str.w r3, [r7, #132] @ 0x84 osThreadAttradc2MeasTask.priority = (osPriority_t)osPriorityRealtime; 8001f7e: 2330 movs r3, #48 @ 0x30 8001f80: f8c7 3088 str.w r3, [r7, #136] @ 0x88 osThreadAttradc3MeasTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001f84: f44f 6380 mov.w r3, #1024 @ 0x400 8001f88: 663b str r3, [r7, #96] @ 0x60 osThreadAttradc3MeasTask.priority = (osPriority_t)osPriorityNormal; 8001f8a: 2318 movs r3, #24 8001f8c: 667b str r3, [r7, #100] @ 0x64 adc1MeasTaskHandle = osThreadNew (ADC1MeasTask, NULL, &osThreadAttradc1MeasTask); 8001f8e: f107 0394 add.w r3, r7, #148 @ 0x94 8001f92: 461a mov r2, r3 8001f94: 2100 movs r1, #0 8001f96: 4833 ldr r0, [pc, #204] @ (8002064 ) 8001f98: f012 f866 bl 8014068 8001f9c: 4603 mov r3, r0 8001f9e: 4a32 ldr r2, [pc, #200] @ (8002068 ) 8001fa0: 6013 str r3, [r2, #0] adc2MeasTaskHandle = osThreadNew (ADC2MeasTask, NULL, &osThreadAttradc2MeasTask); 8001fa2: f107 0370 add.w r3, r7, #112 @ 0x70 8001fa6: 461a mov r2, r3 8001fa8: 2100 movs r1, #0 8001faa: 4830 ldr r0, [pc, #192] @ (800206c ) 8001fac: f012 f85c bl 8014068 8001fb0: 4603 mov r3, r0 8001fb2: 4a2f ldr r2, [pc, #188] @ (8002070 ) 8001fb4: 6013 str r3, [r2, #0] adc3MeasTaskHandle = osThreadNew (ADC3MeasTask, NULL, &osThreadAttradc3MeasTask); 8001fb6: f107 034c add.w r3, r7, #76 @ 0x4c 8001fba: 461a mov r2, r3 8001fbc: 2100 movs r1, #0 8001fbe: 482d ldr r0, [pc, #180] @ (8002074 ) 8001fc0: f012 f852 bl 8014068 8001fc4: 4603 mov r3, r0 8001fc6: 4a2c ldr r2, [pc, #176] @ (8002078 ) 8001fc8: 6013 str r3, [r2, #0] limiterSwitchDataQueue = osMessageQueueNew (8, sizeof (LimiterSwitchData), NULL); 8001fca: 2200 movs r2, #0 8001fcc: 2104 movs r1, #4 8001fce: 2008 movs r0, #8 8001fd0: f012 fafd bl 80145ce 8001fd4: 4603 mov r3, r0 8001fd6: 4a29 ldr r2, [pc, #164] @ (800207c ) 8001fd8: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttradc1LimiterSwitchTask = { 0 }; 8001fda: f107 0328 add.w r3, r7, #40 @ 0x28 8001fde: 2224 movs r2, #36 @ 0x24 8001fe0: 2100 movs r1, #0 8001fe2: 4618 mov r0, r3 8001fe4: f016 f998 bl 8018318 osThreadAttradc1LimiterSwitchTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8001fe8: f44f 6380 mov.w r3, #1024 @ 0x400 8001fec: 63fb str r3, [r7, #60] @ 0x3c osThreadAttradc1LimiterSwitchTask.priority = (osPriority_t)osPriorityNormal; 8001fee: 2318 movs r3, #24 8001ff0: 643b str r3, [r7, #64] @ 0x40 limiterSwitchTaskHandle = osThreadNew (LimiterSwitchTask, NULL, &osThreadAttradc1LimiterSwitchTask); 8001ff2: f107 0328 add.w r3, r7, #40 @ 0x28 8001ff6: 461a mov r2, r3 8001ff8: 2100 movs r1, #0 8001ffa: 4821 ldr r0, [pc, #132] @ (8002080 ) 8001ffc: f012 f834 bl 8014068 8002000: 4603 mov r3, r0 8002002: 4a20 ldr r2, [pc, #128] @ (8002084 ) 8002004: 6013 str r3, [r2, #0] encoderDataQueue = osMessageQueueNew (16, sizeof (EncoderData), NULL); 8002006: 2200 movs r2, #0 8002008: 2102 movs r1, #2 800200a: 2010 movs r0, #16 800200c: f012 fadf bl 80145ce 8002010: 4603 mov r3, r0 8002012: 4a1d ldr r2, [pc, #116] @ (8002088 ) 8002014: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrEncoderTask = { 0 }; 8002016: 1d3b adds r3, r7, #4 8002018: 2224 movs r2, #36 @ 0x24 800201a: 2100 movs r1, #0 800201c: 4618 mov r0, r3 800201e: f016 f97b bl 8018318 osThreadAttrEncoderTask.stack_size = configMINIMAL_STACK_SIZE * 2; 8002022: f44f 6380 mov.w r3, #1024 @ 0x400 8002026: 61bb str r3, [r7, #24] osThreadAttrEncoderTask.priority = (osPriority_t)osPriorityNormal; 8002028: 2318 movs r3, #24 800202a: 61fb str r3, [r7, #28] encoderTaskHandle = osThreadNew (EncoderTask, encoderDataQueue, &osThreadAttrEncoderTask); 800202c: 4b16 ldr r3, [pc, #88] @ (8002088 ) 800202e: 681b ldr r3, [r3, #0] 8002030: 1d3a adds r2, r7, #4 8002032: 4619 mov r1, r3 8002034: 4815 ldr r0, [pc, #84] @ (800208c ) 8002036: f012 f817 bl 8014068 800203a: 4603 mov r3, r0 800203c: 4a14 ldr r2, [pc, #80] @ (8002090 ) 800203e: 6013 str r3, [r2, #0] } 8002040: bf00 nop 8002042: 37b8 adds r7, #184 @ 0xb8 8002044: 46bd mov sp, r7 8002046: bd80 pop {r7, pc} 8002048: 24000814 .word 0x24000814 800204c: 24000818 .word 0x24000818 8002050: 2400081c .word 0x2400081c 8002054: 24000820 .word 0x24000820 8002058: 24000800 .word 0x24000800 800205c: 24000804 .word 0x24000804 8002060: 24000808 .word 0x24000808 8002064: 08002099 .word 0x08002099 8002068: 240007ec .word 0x240007ec 800206c: 08002421 .word 0x08002421 8002070: 240007f0 .word 0x240007f0 8002074: 08002729 .word 0x08002729 8002078: 240007f4 .word 0x240007f4 800207c: 2400080c .word 0x2400080c 8002080: 08002aa5 .word 0x08002aa5 8002084: 240007f8 .word 0x240007f8 8002088: 24000810 .word 0x24000810 800208c: 08002d81 .word 0x08002d81 8002090: 240007fc .word 0x240007fc 8002094: 00000000 .word 0x00000000 08002098 : void ADC1MeasTask (void* arg) { 8002098: b580 push {r7, lr} 800209a: b09a sub sp, #104 @ 0x68 800209c: af00 add r7, sp, #0 800209e: 6078 str r0, [r7, #4] float circBuffer[VOLTAGES_COUNT][CIRC_BUFF_LEN] = { 0 }; 80020a0: f107 032c add.w r3, r7, #44 @ 0x2c 80020a4: 2228 movs r2, #40 @ 0x28 80020a6: 2100 movs r1, #0 80020a8: 4618 mov r0, r3 80020aa: f016 f935 bl 8018318 float rms[VOLTAGES_COUNT] = { 0 }; 80020ae: f04f 0300 mov.w r3, #0 80020b2: 62bb str r3, [r7, #40] @ 0x28 ; ADC1_Data adcData = { 0 }; 80020b4: f107 0308 add.w r3, r7, #8 80020b8: 2220 movs r2, #32 80020ba: 2100 movs r1, #0 80020bc: 4618 mov r0, r3 80020be: f016 f92b bl 8018318 uint32_t circBuffPos = 0; 80020c2: 2300 movs r3, #0 80020c4: 667b str r3, [r7, #100] @ 0x64 float gainCorrection = 1.0; 80020c6: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 80020ca: 663b str r3, [r7, #96] @ 0x60 while (pdTRUE) { osMessageQueueGet (adc1MeasDataQueue, &adcData, 0, osWaitForever); 80020cc: 4bc8 ldr r3, [pc, #800] @ (80023f0 ) 80020ce: 6818 ldr r0, [r3, #0] 80020d0: f107 0108 add.w r1, r7, #8 80020d4: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80020d8: 2200 movs r2, #0 80020da: f012 fb4b bl 8014774 #ifdef GAIN_AUTO_CORRECTION if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80020de: 4bc5 ldr r3, [pc, #788] @ (80023f4 ) 80020e0: 681b ldr r3, [r3, #0] 80020e2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80020e6: 4618 mov r0, r3 80020e8: f012 f9e9 bl 80144be 80020ec: 4603 mov r3, r0 80020ee: 2b00 cmp r3, #0 80020f0: d10c bne.n 800210c gainCorrection = (float)vRefmV; 80020f2: 4bc1 ldr r3, [pc, #772] @ (80023f8 ) 80020f4: 681b ldr r3, [r3, #0] 80020f6: ee07 3a90 vmov s15, r3 80020fa: eef8 7a67 vcvt.f32.u32 s15, s15 80020fe: edc7 7a18 vstr s15, [r7, #96] @ 0x60 osMutexRelease (vRefmVMutex); 8002102: 4bbc ldr r3, [pc, #752] @ (80023f4 ) 8002104: 681b ldr r3, [r3, #0] 8002106: 4618 mov r0, r3 8002108: f012 fa24 bl 8014554 } gainCorrection = gainCorrection / EXT_VREF_mV; 800210c: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8002110: eddf 6aba vldr s13, [pc, #744] @ 80023fc 8002114: eec7 7a26 vdiv.f32 s15, s14, s13 8002118: edc7 7a18 vstr s15, [r7, #96] @ 0x60 #endif for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 800211c: 2300 movs r3, #0 800211e: f887 305f strb.w r3, [r7, #95] @ 0x5f 8002122: e0e7 b.n 80022f4 float val = adcData.adcDataBuffer[i] * deltaADC * U_CHANNEL_CONST * gainCorrection * U_MeasCorrectionData[i].gain + U_MeasCorrectionData[i].offset; 8002124: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002128: 005b lsls r3, r3, #1 800212a: 3368 adds r3, #104 @ 0x68 800212c: 443b add r3, r7 800212e: f833 3c60 ldrh.w r3, [r3, #-96] 8002132: ee07 3a90 vmov s15, r3 8002136: eeb8 7be7 vcvt.f64.s32 d7, s15 800213a: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800213e: ee27 6b06 vmul.f64 d6, d7, d6 8002142: ed9f 5ba5 vldr d5, [pc, #660] @ 80023d8 8002146: ee86 7b05 vdiv.f64 d7, d6, d5 800214a: ed9f 6ba5 vldr d6, [pc, #660] @ 80023e0 800214e: ee27 6b06 vmul.f64 d6, d7, d6 8002152: edd7 7a18 vldr s15, [r7, #96] @ 0x60 8002156: eeb7 7ae7 vcvt.f64.f32 d7, s15 800215a: ee26 6b07 vmul.f64 d6, d6, d7 800215e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002162: 4aa7 ldr r2, [pc, #668] @ (8002400 ) 8002164: 00db lsls r3, r3, #3 8002166: 4413 add r3, r2 8002168: edd3 7a00 vldr s15, [r3] 800216c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002170: ee26 6b07 vmul.f64 d6, d6, d7 8002174: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002178: 4aa1 ldr r2, [pc, #644] @ (8002400 ) 800217a: 00db lsls r3, r3, #3 800217c: 4413 add r3, r2 800217e: 3304 adds r3, #4 8002180: edd3 7a00 vldr s15, [r3] 8002184: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002188: ee36 7b07 vadd.f64 d7, d6, d7 800218c: eef7 7bc7 vcvt.f32.f64 s15, d7 8002190: edc7 7a15 vstr s15, [r7, #84] @ 0x54 circBuffer[i][circBuffPos] = val; 8002194: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002198: 4613 mov r3, r2 800219a: 009b lsls r3, r3, #2 800219c: 4413 add r3, r2 800219e: 005b lsls r3, r3, #1 80021a0: 6e7a ldr r2, [r7, #100] @ 0x64 80021a2: 4413 add r3, r2 80021a4: 009b lsls r3, r3, #2 80021a6: 3368 adds r3, #104 @ 0x68 80021a8: 443b add r3, r7 80021aa: 3b3c subs r3, #60 @ 0x3c 80021ac: 6d7a ldr r2, [r7, #84] @ 0x54 80021ae: 601a str r2, [r3, #0] rms[i] = 0.0; 80021b0: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021b4: 009b lsls r3, r3, #2 80021b6: 3368 adds r3, #104 @ 0x68 80021b8: 443b add r3, r7 80021ba: 3b40 subs r3, #64 @ 0x40 80021bc: f04f 0200 mov.w r2, #0 80021c0: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80021c2: 2300 movs r3, #0 80021c4: f887 305e strb.w r3, [r7, #94] @ 0x5e 80021c8: e025 b.n 8002216 rms[i] += circBuffer[i][c]; 80021ca: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021ce: 009b lsls r3, r3, #2 80021d0: 3368 adds r3, #104 @ 0x68 80021d2: 443b add r3, r7 80021d4: 3b40 subs r3, #64 @ 0x40 80021d6: ed93 7a00 vldr s14, [r3] 80021da: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 80021de: f897 105e ldrb.w r1, [r7, #94] @ 0x5e 80021e2: 4613 mov r3, r2 80021e4: 009b lsls r3, r3, #2 80021e6: 4413 add r3, r2 80021e8: 005b lsls r3, r3, #1 80021ea: 440b add r3, r1 80021ec: 009b lsls r3, r3, #2 80021ee: 3368 adds r3, #104 @ 0x68 80021f0: 443b add r3, r7 80021f2: 3b3c subs r3, #60 @ 0x3c 80021f4: edd3 7a00 vldr s15, [r3] 80021f8: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80021fc: ee77 7a27 vadd.f32 s15, s14, s15 8002200: 009b lsls r3, r3, #2 8002202: 3368 adds r3, #104 @ 0x68 8002204: 443b add r3, r7 8002206: 3b40 subs r3, #64 @ 0x40 8002208: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 800220c: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 8002210: 3301 adds r3, #1 8002212: f887 305e strb.w r3, [r7, #94] @ 0x5e 8002216: f897 305e ldrb.w r3, [r7, #94] @ 0x5e 800221a: 2b09 cmp r3, #9 800221c: d9d5 bls.n 80021ca } rms[i] = rms[i] / CIRC_BUFF_LEN; 800221e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002222: 009b lsls r3, r3, #2 8002224: 3368 adds r3, #104 @ 0x68 8002226: 443b add r3, r7 8002228: 3b40 subs r3, #64 @ 0x40 800222a: ed93 7a00 vldr s14, [r3] 800222e: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002232: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002236: eec7 7a26 vdiv.f32 s15, s14, s13 800223a: 009b lsls r3, r3, #2 800223c: 3368 adds r3, #104 @ 0x68 800223e: 443b add r3, r7 8002240: 3b40 subs r3, #64 @ 0x40 8002242: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8002246: 4b6f ldr r3, [pc, #444] @ (8002404 ) 8002248: 681b ldr r3, [r3, #0] 800224a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800224e: 4618 mov r0, r3 8002250: f012 f935 bl 80144be 8002254: 4603 mov r3, r0 8002256: 2b00 cmp r3, #0 8002258: d147 bne.n 80022ea if (fabs (resMeasurements.voltagePeak[i]) < fabs (val)) { 800225a: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800225e: 4a6a ldr r2, [pc, #424] @ (8002408 ) 8002260: 3302 adds r3, #2 8002262: 009b lsls r3, r3, #2 8002264: 4413 add r3, r2 8002266: 3304 adds r3, #4 8002268: edd3 7a00 vldr s15, [r3] 800226c: eeb0 7ae7 vabs.f32 s14, s15 8002270: edd7 7a15 vldr s15, [r7, #84] @ 0x54 8002274: eef0 7ae7 vabs.f32 s15, s15 8002278: eeb4 7ae7 vcmpe.f32 s14, s15 800227c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002280: d508 bpl.n 8002294 resMeasurements.voltagePeak[i] = val; 8002282: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 8002286: 4a60 ldr r2, [pc, #384] @ (8002408 ) 8002288: 3302 adds r3, #2 800228a: 009b lsls r3, r3, #2 800228c: 4413 add r3, r2 800228e: 3304 adds r3, #4 8002290: 6d7a ldr r2, [r7, #84] @ 0x54 8002292: 601a str r2, [r3, #0] } resMeasurements.voltageRMS[i] = rms[i]; 8002294: f897 205f ldrb.w r2, [r7, #95] @ 0x5f 8002298: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 800229c: 0092 lsls r2, r2, #2 800229e: 3268 adds r2, #104 @ 0x68 80022a0: 443a add r2, r7 80022a2: 3a40 subs r2, #64 @ 0x40 80022a4: 6812 ldr r2, [r2, #0] 80022a6: 4958 ldr r1, [pc, #352] @ (8002408 ) 80022a8: 009b lsls r3, r3, #2 80022aa: 440b add r3, r1 80022ac: 601a str r2, [r3, #0] resMeasurements.power[i] = resMeasurements.voltageRMS[i] * resMeasurements.currentRMS[i]; 80022ae: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022b2: 4a55 ldr r2, [pc, #340] @ (8002408 ) 80022b4: 009b lsls r3, r3, #2 80022b6: 4413 add r3, r2 80022b8: ed93 7a00 vldr s14, [r3] 80022bc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022c0: 4a51 ldr r2, [pc, #324] @ (8002408 ) 80022c2: 3306 adds r3, #6 80022c4: 009b lsls r3, r3, #2 80022c6: 4413 add r3, r2 80022c8: edd3 7a00 vldr s15, [r3] 80022cc: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022d0: ee67 7a27 vmul.f32 s15, s14, s15 80022d4: 4a4c ldr r2, [pc, #304] @ (8002408 ) 80022d6: 330c adds r3, #12 80022d8: 009b lsls r3, r3, #2 80022da: 4413 add r3, r2 80022dc: edc3 7a00 vstr s15, [r3] osMutexRelease (resMeasurementsMutex); 80022e0: 4b48 ldr r3, [pc, #288] @ (8002404 ) 80022e2: 681b ldr r3, [r3, #0] 80022e4: 4618 mov r0, r3 80022e6: f012 f935 bl 8014554 for (uint8_t i = 0; i < VOLTAGES_COUNT; i++) { 80022ea: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022ee: 3301 adds r3, #1 80022f0: f887 305f strb.w r3, [r7, #95] @ 0x5f 80022f4: f897 305f ldrb.w r3, [r7, #95] @ 0x5f 80022f8: 2b00 cmp r3, #0 80022fa: f43f af13 beq.w 8002124 } } ++circBuffPos; 80022fe: 6e7b ldr r3, [r7, #100] @ 0x64 8002300: 3301 adds r3, #1 8002302: 667b str r3, [r7, #100] @ 0x64 circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002304: 6e7a ldr r2, [r7, #100] @ 0x64 8002306: 4b41 ldr r3, [pc, #260] @ (800240c ) 8002308: fba3 1302 umull r1, r3, r3, r2 800230c: 08d9 lsrs r1, r3, #3 800230e: 460b mov r3, r1 8002310: 009b lsls r3, r3, #2 8002312: 440b add r3, r1 8002314: 005b lsls r3, r3, #1 8002316: 1ad3 subs r3, r2, r3 8002318: 667b str r3, [r7, #100] @ 0x64 if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 800231a: 4b3d ldr r3, [pc, #244] @ (8002410 ) 800231c: 681b ldr r3, [r3, #0] 800231e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002322: 4618 mov r0, r3 8002324: f012 f8cb bl 80144be 8002328: 4603 mov r3, r0 800232a: 2b00 cmp r3, #0 800232c: d124 bne.n 8002378 uint8_t refIdx = 0; 800232e: 2300 movs r3, #0 8002330: f887 305d strb.w r3, [r7, #93] @ 0x5d for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 8002334: 2303 movs r3, #3 8002336: f887 305c strb.w r3, [r7, #92] @ 0x5c 800233a: e014 b.n 8002366 ILxRef[refIdx++] = adcData.adcDataBuffer[i]; 800233c: f897 205c ldrb.w r2, [r7, #92] @ 0x5c 8002340: f897 305d ldrb.w r3, [r7, #93] @ 0x5d 8002344: 1c59 adds r1, r3, #1 8002346: f887 105d strb.w r1, [r7, #93] @ 0x5d 800234a: 4619 mov r1, r3 800234c: 0053 lsls r3, r2, #1 800234e: 3368 adds r3, #104 @ 0x68 8002350: 443b add r3, r7 8002352: f833 2c60 ldrh.w r2, [r3, #-96] 8002356: 4b2f ldr r3, [pc, #188] @ (8002414 ) 8002358: f823 2011 strh.w r2, [r3, r1, lsl #1] for (uint8_t i = (uint8_t)IL1Ref; i <= (uint8_t)IL3Ref; i++) { 800235c: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 8002360: 3301 adds r3, #1 8002362: f887 305c strb.w r3, [r7, #92] @ 0x5c 8002366: f897 305c ldrb.w r3, [r7, #92] @ 0x5c 800236a: 2b05 cmp r3, #5 800236c: d9e6 bls.n 800233c } osMutexRelease (ILxRefMutex); 800236e: 4b28 ldr r3, [pc, #160] @ (8002410 ) 8002370: 681b ldr r3, [r3, #0] 8002372: 4618 mov r0, r3 8002374: f012 f8ee bl 8014554 } float fanFBVoltage = adcData.adcDataBuffer[FanFB] * deltaADC * -4.35 + 12; 8002378: 8abb ldrh r3, [r7, #20] 800237a: ee07 3a90 vmov s15, r3 800237e: eeb8 7be7 vcvt.f64.s32 d7, s15 8002382: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002386: ee27 6b06 vmul.f64 d6, d7, d6 800238a: ed9f 5b13 vldr d5, [pc, #76] @ 80023d8 800238e: ee86 7b05 vdiv.f64 d7, d6, d5 8002392: ed9f 6b15 vldr d6, [pc, #84] @ 80023e8 8002396: ee27 7b06 vmul.f64 d7, d7, d6 800239a: eeb2 6b08 vmov.f64 d6, #40 @ 0x41400000 12.0 800239e: ee37 7b06 vadd.f64 d7, d7, d6 80023a2: eef7 7bc7 vcvt.f32.f64 s15, d7 80023a6: edc7 7a16 vstr s15, [r7, #88] @ 0x58 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80023aa: 4b1b ldr r3, [pc, #108] @ (8002418 ) 80023ac: 681b ldr r3, [r3, #0] 80023ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80023b2: 4618 mov r0, r3 80023b4: f012 f883 bl 80144be 80023b8: 4603 mov r3, r0 80023ba: 2b00 cmp r3, #0 80023bc: f47f ae86 bne.w 80020cc sensorsInfo.fanVoltage = fanFBVoltage; 80023c0: 4a16 ldr r2, [pc, #88] @ (800241c ) 80023c2: 6dbb ldr r3, [r7, #88] @ 0x58 80023c4: 6093 str r3, [r2, #8] osMutexRelease (sensorsInfoMutex); 80023c6: 4b14 ldr r3, [pc, #80] @ (8002418 ) 80023c8: 681b ldr r3, [r3, #0] 80023ca: 4618 mov r0, r3 80023cc: f012 f8c2 bl 8014554 while (pdTRUE) { 80023d0: e67c b.n 80020cc 80023d2: bf00 nop 80023d4: f3af 8000 nop.w 80023d8: 00000000 .word 0x00000000 80023dc: 40efffe0 .word 0x40efffe0 80023e0: f5c28f5c .word 0xf5c28f5c 80023e4: 401e5c28 .word 0x401e5c28 80023e8: 66666666 .word 0x66666666 80023ec: c0116666 .word 0xc0116666 80023f0: 24000800 .word 0x24000800 80023f4: 24000814 .word 0x24000814 80023f8: 24000030 .word 0x24000030 80023fc: 453b8000 .word 0x453b8000 8002400: 24000000 .word 0x24000000 8002404: 24000818 .word 0x24000818 8002408: 24000824 .word 0x24000824 800240c: cccccccd .word 0xcccccccd 8002410: 24000820 .word 0x24000820 8002414: 2400089c .word 0x2400089c 8002418: 2400081c .word 0x2400081c 800241c: 24000860 .word 0x24000860 08002420 : } } } void ADC2MeasTask (void* arg) { 8002420: b580 push {r7, lr} 8002422: b09c sub sp, #112 @ 0x70 8002424: af00 add r7, sp, #0 8002426: 6078 str r0, [r7, #4] float circBuffer[CURRENTS_COUNT][CIRC_BUFF_LEN] = { 0 }; 8002428: f107 0334 add.w r3, r7, #52 @ 0x34 800242c: 2228 movs r2, #40 @ 0x28 800242e: 2100 movs r1, #0 8002430: 4618 mov r0, r3 8002432: f015 ff71 bl 8018318 float rms[CURRENTS_COUNT] = { 0 }; 8002436: f04f 0300 mov.w r3, #0 800243a: 633b str r3, [r7, #48] @ 0x30 ADC2_Data adcData = { 0 }; 800243c: f107 0310 add.w r3, r7, #16 8002440: 2220 movs r2, #32 8002442: 2100 movs r1, #0 8002444: 4618 mov r0, r3 8002446: f015 ff67 bl 8018318 uint32_t circBuffPos = 0; 800244a: 2300 movs r3, #0 800244c: 66fb str r3, [r7, #108] @ 0x6c float gainCorrection = 1.0; 800244e: f04f 537e mov.w r3, #1065353216 @ 0x3f800000 8002452: 66bb str r3, [r7, #104] @ 0x68 while (pdTRUE) { osMessageQueueGet (adc2MeasDataQueue, &adcData, 0, osWaitForever); 8002454: 4baa ldr r3, [pc, #680] @ (8002700 ) 8002456: 6818 ldr r0, [r3, #0] 8002458: f107 0110 add.w r1, r7, #16 800245c: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002460: 2200 movs r2, #0 8002462: f012 f987 bl 8014774 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 8002466: 4ba7 ldr r3, [pc, #668] @ (8002704 ) 8002468: 681b ldr r3, [r3, #0] 800246a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800246e: 4618 mov r0, r3 8002470: f012 f825 bl 80144be 8002474: 4603 mov r3, r0 8002476: 2b00 cmp r3, #0 8002478: d10c bne.n 8002494 gainCorrection = (float)vRefmV; 800247a: 4ba3 ldr r3, [pc, #652] @ (8002708 ) 800247c: 681b ldr r3, [r3, #0] 800247e: ee07 3a90 vmov s15, r3 8002482: eef8 7a67 vcvt.f32.u32 s15, s15 8002486: edc7 7a1a vstr s15, [r7, #104] @ 0x68 osMutexRelease (vRefmVMutex); 800248a: 4b9e ldr r3, [pc, #632] @ (8002704 ) 800248c: 681b ldr r3, [r3, #0] 800248e: 4618 mov r0, r3 8002490: f012 f860 bl 8014554 } gainCorrection = gainCorrection / EXT_VREF_mV; 8002494: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8002498: eddf 6a9c vldr s13, [pc, #624] @ 800270c 800249c: eec7 7a26 vdiv.f32 s15, s14, s13 80024a0: edc7 7a1a vstr s15, [r7, #104] @ 0x68 float ref[CURRENTS_COUNT] = { 0 }; 80024a4: f04f 0300 mov.w r3, #0 80024a8: 60fb str r3, [r7, #12] if (osMutexAcquire (ILxRefMutex, osWaitForever) == osOK) { 80024aa: 4b99 ldr r3, [pc, #612] @ (8002710 ) 80024ac: 681b ldr r3, [r3, #0] 80024ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80024b2: 4618 mov r0, r3 80024b4: f012 f803 bl 80144be 80024b8: 4603 mov r3, r0 80024ba: 2b00 cmp r3, #0 80024bc: d122 bne.n 8002504 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80024be: 2300 movs r3, #0 80024c0: f887 3067 strb.w r3, [r7, #103] @ 0x67 80024c4: e015 b.n 80024f2 ref[i] = (float)ILxRef[i]; 80024c6: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024ca: 4a92 ldr r2, [pc, #584] @ (8002714 ) 80024cc: f832 2013 ldrh.w r2, [r2, r3, lsl #1] 80024d0: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024d4: ee07 2a90 vmov s15, r2 80024d8: eef8 7a67 vcvt.f32.u32 s15, s15 80024dc: 009b lsls r3, r3, #2 80024de: 3370 adds r3, #112 @ 0x70 80024e0: 443b add r3, r7 80024e2: 3b64 subs r3, #100 @ 0x64 80024e4: edc3 7a00 vstr s15, [r3] for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80024e8: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024ec: 3301 adds r3, #1 80024ee: f887 3067 strb.w r3, [r7, #103] @ 0x67 80024f2: f897 3067 ldrb.w r3, [r7, #103] @ 0x67 80024f6: 2b00 cmp r3, #0 80024f8: d0e5 beq.n 80024c6 } osMutexRelease (ILxRefMutex); 80024fa: 4b85 ldr r3, [pc, #532] @ (8002710 ) 80024fc: 681b ldr r3, [r3, #0] 80024fe: 4618 mov r0, r3 8002500: f012 f828 bl 8014554 } for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 8002504: 2300 movs r3, #0 8002506: f887 3066 strb.w r3, [r7, #102] @ 0x66 800250a: e0db b.n 80026c4 float adcVal = (float)adcData.adcDataBuffer[i]; 800250c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002510: 005b lsls r3, r3, #1 8002512: 3370 adds r3, #112 @ 0x70 8002514: 443b add r3, r7 8002516: f833 3c60 ldrh.w r3, [r3, #-96] 800251a: ee07 3a90 vmov s15, r3 800251e: eef8 7a67 vcvt.f32.u32 s15, s15 8002522: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float val = (adcVal - ref[i]) * deltaADC * I_CHANNEL_CONST * gainCorrection * I_MeasCorrectionData[i].gain + I_MeasCorrectionData[i].offset; 8002526: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800252a: 009b lsls r3, r3, #2 800252c: 3370 adds r3, #112 @ 0x70 800252e: 443b add r3, r7 8002530: 3b64 subs r3, #100 @ 0x64 8002532: edd3 7a00 vldr s15, [r3] 8002536: ed97 7a18 vldr s14, [r7, #96] @ 0x60 800253a: ee77 7a67 vsub.f32 s15, s14, s15 800253e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002542: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002546: ee27 6b06 vmul.f64 d6, d7, d6 800254a: ed9f 5b69 vldr d5, [pc, #420] @ 80026f0 800254e: ee86 7b05 vdiv.f64 d7, d6, d5 8002552: ed9f 6b69 vldr d6, [pc, #420] @ 80026f8 8002556: ee27 6b06 vmul.f64 d6, d7, d6 800255a: edd7 7a1a vldr s15, [r7, #104] @ 0x68 800255e: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002562: ee26 6b07 vmul.f64 d6, d6, d7 8002566: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800256a: 4a6b ldr r2, [pc, #428] @ (8002718 ) 800256c: 00db lsls r3, r3, #3 800256e: 4413 add r3, r2 8002570: edd3 7a00 vldr s15, [r3] 8002574: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002578: ee26 6b07 vmul.f64 d6, d6, d7 800257c: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002580: 4a65 ldr r2, [pc, #404] @ (8002718 ) 8002582: 00db lsls r3, r3, #3 8002584: 4413 add r3, r2 8002586: 3304 adds r3, #4 8002588: edd3 7a00 vldr s15, [r3] 800258c: eeb7 7ae7 vcvt.f64.f32 d7, s15 8002590: ee36 7b07 vadd.f64 d7, d6, d7 8002594: eef7 7bc7 vcvt.f32.f64 s15, d7 8002598: edc7 7a17 vstr s15, [r7, #92] @ 0x5c circBuffer[i][circBuffPos] = val; 800259c: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80025a0: 4613 mov r3, r2 80025a2: 009b lsls r3, r3, #2 80025a4: 4413 add r3, r2 80025a6: 005b lsls r3, r3, #1 80025a8: 6efa ldr r2, [r7, #108] @ 0x6c 80025aa: 4413 add r3, r2 80025ac: 009b lsls r3, r3, #2 80025ae: 3370 adds r3, #112 @ 0x70 80025b0: 443b add r3, r7 80025b2: 3b3c subs r3, #60 @ 0x3c 80025b4: 6dfa ldr r2, [r7, #92] @ 0x5c 80025b6: 601a str r2, [r3, #0] rms[i] = 0.0; 80025b8: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025bc: 009b lsls r3, r3, #2 80025be: 3370 adds r3, #112 @ 0x70 80025c0: 443b add r3, r7 80025c2: 3b40 subs r3, #64 @ 0x40 80025c4: f04f 0200 mov.w r2, #0 80025c8: 601a str r2, [r3, #0] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 80025ca: 2300 movs r3, #0 80025cc: f887 3065 strb.w r3, [r7, #101] @ 0x65 80025d0: e025 b.n 800261e rms[i] += circBuffer[i][c]; 80025d2: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80025d6: 009b lsls r3, r3, #2 80025d8: 3370 adds r3, #112 @ 0x70 80025da: 443b add r3, r7 80025dc: 3b40 subs r3, #64 @ 0x40 80025de: ed93 7a00 vldr s14, [r3] 80025e2: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 80025e6: f897 1065 ldrb.w r1, [r7, #101] @ 0x65 80025ea: 4613 mov r3, r2 80025ec: 009b lsls r3, r3, #2 80025ee: 4413 add r3, r2 80025f0: 005b lsls r3, r3, #1 80025f2: 440b add r3, r1 80025f4: 009b lsls r3, r3, #2 80025f6: 3370 adds r3, #112 @ 0x70 80025f8: 443b add r3, r7 80025fa: 3b3c subs r3, #60 @ 0x3c 80025fc: edd3 7a00 vldr s15, [r3] 8002600: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002604: ee77 7a27 vadd.f32 s15, s14, s15 8002608: 009b lsls r3, r3, #2 800260a: 3370 adds r3, #112 @ 0x70 800260c: 443b add r3, r7 800260e: 3b40 subs r3, #64 @ 0x40 8002610: edc3 7a00 vstr s15, [r3] for (uint8_t c = 0; c < CIRC_BUFF_LEN; c++) { 8002614: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002618: 3301 adds r3, #1 800261a: f887 3065 strb.w r3, [r7, #101] @ 0x65 800261e: f897 3065 ldrb.w r3, [r7, #101] @ 0x65 8002622: 2b09 cmp r3, #9 8002624: d9d5 bls.n 80025d2 } rms[i] = rms[i] / CIRC_BUFF_LEN; 8002626: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800262a: 009b lsls r3, r3, #2 800262c: 3370 adds r3, #112 @ 0x70 800262e: 443b add r3, r7 8002630: 3b40 subs r3, #64 @ 0x40 8002632: ed93 7a00 vldr s14, [r3] 8002636: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800263a: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 800263e: eec7 7a26 vdiv.f32 s15, s14, s13 8002642: 009b lsls r3, r3, #2 8002644: 3370 adds r3, #112 @ 0x70 8002646: 443b add r3, r7 8002648: 3b40 subs r3, #64 @ 0x40 800264a: edc3 7a00 vstr s15, [r3] if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800264e: 4b33 ldr r3, [pc, #204] @ (800271c ) 8002650: 681b ldr r3, [r3, #0] 8002652: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002656: 4618 mov r0, r3 8002658: f011 ff31 bl 80144be 800265c: 4603 mov r3, r0 800265e: 2b00 cmp r3, #0 8002660: d12b bne.n 80026ba if (resMeasurements.currentPeak[i] < val) { 8002662: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002666: 4a2e ldr r2, [pc, #184] @ (8002720 ) 8002668: 3308 adds r3, #8 800266a: 009b lsls r3, r3, #2 800266c: 4413 add r3, r2 800266e: 3304 adds r3, #4 8002670: edd3 7a00 vldr s15, [r3] 8002674: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8002678: eeb4 7ae7 vcmpe.f32 s14, s15 800267c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002680: dd08 ble.n 8002694 resMeasurements.currentPeak[i] = val; 8002682: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 8002686: 4a26 ldr r2, [pc, #152] @ (8002720 ) 8002688: 3308 adds r3, #8 800268a: 009b lsls r3, r3, #2 800268c: 4413 add r3, r2 800268e: 3304 adds r3, #4 8002690: 6dfa ldr r2, [r7, #92] @ 0x5c 8002692: 601a str r2, [r3, #0] } resMeasurements.currentRMS[i] = rms[i]; 8002694: f897 2066 ldrb.w r2, [r7, #102] @ 0x66 8002698: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 800269c: 0092 lsls r2, r2, #2 800269e: 3270 adds r2, #112 @ 0x70 80026a0: 443a add r2, r7 80026a2: 3a40 subs r2, #64 @ 0x40 80026a4: 6812 ldr r2, [r2, #0] 80026a6: 491e ldr r1, [pc, #120] @ (8002720 ) 80026a8: 3306 adds r3, #6 80026aa: 009b lsls r3, r3, #2 80026ac: 440b add r3, r1 80026ae: 601a str r2, [r3, #0] osMutexRelease (resMeasurementsMutex); 80026b0: 4b1a ldr r3, [pc, #104] @ (800271c ) 80026b2: 681b ldr r3, [r3, #0] 80026b4: 4618 mov r0, r3 80026b6: f011 ff4d bl 8014554 for (uint8_t i = 0; i < CURRENTS_COUNT; i++) { 80026ba: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80026be: 3301 adds r3, #1 80026c0: f887 3066 strb.w r3, [r7, #102] @ 0x66 80026c4: f897 3066 ldrb.w r3, [r7, #102] @ 0x66 80026c8: 2b00 cmp r3, #0 80026ca: f43f af1f beq.w 800250c } } ++circBuffPos; 80026ce: 6efb ldr r3, [r7, #108] @ 0x6c 80026d0: 3301 adds r3, #1 80026d2: 66fb str r3, [r7, #108] @ 0x6c circBuffPos = circBuffPos % CIRC_BUFF_LEN; 80026d4: 6efa ldr r2, [r7, #108] @ 0x6c 80026d6: 4b13 ldr r3, [pc, #76] @ (8002724 ) 80026d8: fba3 1302 umull r1, r3, r3, r2 80026dc: 08d9 lsrs r1, r3, #3 80026de: 460b mov r3, r1 80026e0: 009b lsls r3, r3, #2 80026e2: 440b add r3, r1 80026e4: 005b lsls r3, r3, #1 80026e6: 1ad3 subs r3, r2, r3 80026e8: 66fb str r3, [r7, #108] @ 0x6c while (pdTRUE) { 80026ea: e6b3 b.n 8002454 80026ec: f3af 8000 nop.w 80026f0: 00000000 .word 0x00000000 80026f4: 40efffe0 .word 0x40efffe0 80026f8: 83e425af .word 0x83e425af 80026fc: 401e4d9e .word 0x401e4d9e 8002700: 24000804 .word 0x24000804 8002704: 24000814 .word 0x24000814 8002708: 24000030 .word 0x24000030 800270c: 453b8000 .word 0x453b8000 8002710: 24000820 .word 0x24000820 8002714: 2400089c .word 0x2400089c 8002718: 24000018 .word 0x24000018 800271c: 24000818 .word 0x24000818 8002720: 24000824 .word 0x24000824 8002724: cccccccd .word 0xcccccccd 08002728 : } } void ADC3MeasTask (void* arg) { 8002728: b580 push {r7, lr} 800272a: b0bc sub sp, #240 @ 0xf0 800272c: af00 add r7, sp, #0 800272e: 6078 str r0, [r7, #4] float motorXSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 8002730: f107 03a4 add.w r3, r7, #164 @ 0xa4 8002734: 2228 movs r2, #40 @ 0x28 8002736: 2100 movs r1, #0 8002738: 4618 mov r0, r3 800273a: f015 fded bl 8018318 float motorYSensCircBuffer[CIRC_BUFF_LEN] = { 0 }; 800273e: f107 037c add.w r3, r7, #124 @ 0x7c 8002742: 2228 movs r2, #40 @ 0x28 8002744: 2100 movs r1, #0 8002746: 4618 mov r0, r3 8002748: f015 fde6 bl 8018318 float pvT1CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800274c: f107 0354 add.w r3, r7, #84 @ 0x54 8002750: 2228 movs r2, #40 @ 0x28 8002752: 2100 movs r1, #0 8002754: 4618 mov r0, r3 8002756: f015 fddf bl 8018318 float pvT2CircBuffer[CIRC_BUFF_LEN] = { 0 }; 800275a: f107 032c add.w r3, r7, #44 @ 0x2c 800275e: 2228 movs r2, #40 @ 0x28 8002760: 2100 movs r1, #0 8002762: 4618 mov r0, r3 8002764: f015 fdd8 bl 8018318 uint32_t circBuffPos = 0; 8002768: 2300 movs r3, #0 800276a: f8c7 30ec str.w r3, [r7, #236] @ 0xec ADC3_Data adcData = { 0 }; 800276e: f107 030c add.w r3, r7, #12 8002772: 2220 movs r2, #32 8002774: 2100 movs r1, #0 8002776: 4618 mov r0, r3 8002778: f015 fdce bl 8018318 while (pdTRUE) { osMessageQueueGet (adc3MeasDataQueue, &adcData, 0, osWaitForever); 800277c: 4bc2 ldr r3, [pc, #776] @ (8002a88 ) 800277e: 6818 ldr r0, [r3, #0] 8002780: f107 010c add.w r1, r7, #12 8002784: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002788: 2200 movs r2, #0 800278a: f011 fff3 bl 8014774 uint32_t vRef = __LL_ADC_CALC_VREFANALOG_VOLTAGE (adcData.adcDataBuffer[VrefInt], LL_ADC_RESOLUTION_16B); 800278e: 4bbf ldr r3, [pc, #764] @ (8002a8c ) 8002790: 881b ldrh r3, [r3, #0] 8002792: 461a mov r2, r3 8002794: f640 43e4 movw r3, #3300 @ 0xce4 8002798: fb02 f303 mul.w r3, r2, r3 800279c: 8aba ldrh r2, [r7, #20] 800279e: fbb3 f3f2 udiv r3, r3, r2 80027a2: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if (osMutexAcquire (vRefmVMutex, osWaitForever) == osOK) { 80027a6: 4bba ldr r3, [pc, #744] @ (8002a90 ) 80027a8: 681b ldr r3, [r3, #0] 80027aa: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80027ae: 4618 mov r0, r3 80027b0: f011 fe85 bl 80144be 80027b4: 4603 mov r3, r0 80027b6: 2b00 cmp r3, #0 80027b8: d108 bne.n 80027cc vRefmV = vRef; 80027ba: 4ab6 ldr r2, [pc, #728] @ (8002a94 ) 80027bc: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 80027c0: 6013 str r3, [r2, #0] osMutexRelease (vRefmVMutex); 80027c2: 4bb3 ldr r3, [pc, #716] @ (8002a90 ) 80027c4: 681b ldr r3, [r3, #0] 80027c6: 4618 mov r0, r3 80027c8: f011 fec4 bl 8014554 } float motorXCurrentSense = adcData.adcDataBuffer[motorXSense] * deltaADC * 10 / 8.33333; 80027cc: 8a3b ldrh r3, [r7, #16] 80027ce: ee07 3a90 vmov s15, r3 80027d2: eeb8 7be7 vcvt.f64.s32 d7, s15 80027d6: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80027da: ee27 6b06 vmul.f64 d6, d7, d6 80027de: ed9f 5ba2 vldr d5, [pc, #648] @ 8002a68 80027e2: ee86 7b05 vdiv.f64 d7, d6, d5 80027e6: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 80027ea: ee27 6b06 vmul.f64 d6, d7, d6 80027ee: ed9f 5ba0 vldr d5, [pc, #640] @ 8002a70 80027f2: ee86 7b05 vdiv.f64 d7, d6, d5 80027f6: eef7 7bc7 vcvt.f32.f64 s15, d7 80027fa: edc7 7a34 vstr s15, [r7, #208] @ 0xd0 float motorYCurrentSense = adcData.adcDataBuffer[motorYSense] * deltaADC * 10 / 8.33333; 80027fe: 8a7b ldrh r3, [r7, #18] 8002800: ee07 3a90 vmov s15, r3 8002804: eeb8 7be7 vcvt.f64.s32 d7, s15 8002808: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 800280c: ee27 6b06 vmul.f64 d6, d7, d6 8002810: ed9f 5b95 vldr d5, [pc, #596] @ 8002a68 8002814: ee86 7b05 vdiv.f64 d7, d6, d5 8002818: eeb2 6b04 vmov.f64 d6, #36 @ 0x41200000 10.0 800281c: ee27 6b06 vmul.f64 d6, d7, d6 8002820: ed9f 5b93 vldr d5, [pc, #588] @ 8002a70 8002824: ee86 7b05 vdiv.f64 d7, d6, d5 8002828: eef7 7bc7 vcvt.f32.f64 s15, d7 800282c: edc7 7a33 vstr s15, [r7, #204] @ 0xcc motorXSensCircBuffer[circBuffPos] = motorXCurrentSense; 8002830: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002834: 009b lsls r3, r3, #2 8002836: 33f0 adds r3, #240 @ 0xf0 8002838: 443b add r3, r7 800283a: 3b4c subs r3, #76 @ 0x4c 800283c: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 8002840: 601a str r2, [r3, #0] motorYSensCircBuffer[circBuffPos] = motorYCurrentSense; 8002842: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002846: 009b lsls r3, r3, #2 8002848: 33f0 adds r3, #240 @ 0xf0 800284a: 443b add r3, r7 800284c: 3b74 subs r3, #116 @ 0x74 800284e: f8d7 20cc ldr.w r2, [r7, #204] @ 0xcc 8002852: 601a str r2, [r3, #0] pvT1CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp1] * deltaADC * 45.33333333 - 63; 8002854: 89bb ldrh r3, [r7, #12] 8002856: ee07 3a90 vmov s15, r3 800285a: eeb8 7be7 vcvt.f64.s32 d7, s15 800285e: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 8002862: ee27 6b06 vmul.f64 d6, d7, d6 8002866: ed9f 5b80 vldr d5, [pc, #512] @ 8002a68 800286a: ee86 7b05 vdiv.f64 d7, d6, d5 800286e: ed9f 6b82 vldr d6, [pc, #520] @ 8002a78 8002872: ee27 7b06 vmul.f64 d7, d7, d6 8002876: ed9f 6b82 vldr d6, [pc, #520] @ 8002a80 800287a: ee37 7b46 vsub.f64 d7, d7, d6 800287e: eef7 7bc7 vcvt.f32.f64 s15, d7 8002882: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002886: 009b lsls r3, r3, #2 8002888: 33f0 adds r3, #240 @ 0xf0 800288a: 443b add r3, r7 800288c: 3b9c subs r3, #156 @ 0x9c 800288e: edc3 7a00 vstr s15, [r3] pvT2CircBuffer[circBuffPos] = adcData.adcDataBuffer[pvTemp2] * deltaADC * 45.33333333 - 63; 8002892: 89fb ldrh r3, [r7, #14] 8002894: ee07 3a90 vmov s15, r3 8002898: eeb8 7be7 vcvt.f64.s32 d7, s15 800289c: eeb0 6b08 vmov.f64 d6, #8 @ 0x40400000 3.0 80028a0: ee27 6b06 vmul.f64 d6, d7, d6 80028a4: ed9f 5b70 vldr d5, [pc, #448] @ 8002a68 80028a8: ee86 7b05 vdiv.f64 d7, d6, d5 80028ac: ed9f 6b72 vldr d6, [pc, #456] @ 8002a78 80028b0: ee27 7b06 vmul.f64 d7, d7, d6 80028b4: ed9f 6b72 vldr d6, [pc, #456] @ 8002a80 80028b8: ee37 7b46 vsub.f64 d7, d7, d6 80028bc: eef7 7bc7 vcvt.f32.f64 s15, d7 80028c0: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 80028c4: 009b lsls r3, r3, #2 80028c6: 33f0 adds r3, #240 @ 0xf0 80028c8: 443b add r3, r7 80028ca: 3bc4 subs r3, #196 @ 0xc4 80028cc: edc3 7a00 vstr s15, [r3] float motorXAveCurrent = 0; 80028d0: f04f 0300 mov.w r3, #0 80028d4: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 float motorYAveCurrent = 0; 80028d8: f04f 0300 mov.w r3, #0 80028dc: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 float pvT1AveTemp = 0; 80028e0: f04f 0300 mov.w r3, #0 80028e4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 float pvT2AveTemp = 0; 80028e8: f04f 0300 mov.w r3, #0 80028ec: f8c7 30dc str.w r3, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 80028f0: 2300 movs r3, #0 80028f2: f887 30db strb.w r3, [r7, #219] @ 0xdb 80028f6: e03c b.n 8002972 motorXAveCurrent += motorXSensCircBuffer[i]; 80028f8: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 80028fc: 009b lsls r3, r3, #2 80028fe: 33f0 adds r3, #240 @ 0xf0 8002900: 443b add r3, r7 8002902: 3b4c subs r3, #76 @ 0x4c 8002904: edd3 7a00 vldr s15, [r3] 8002908: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800290c: ee77 7a27 vadd.f32 s15, s14, s15 8002910: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent += motorYSensCircBuffer[i]; 8002914: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002918: 009b lsls r3, r3, #2 800291a: 33f0 adds r3, #240 @ 0xf0 800291c: 443b add r3, r7 800291e: 3b74 subs r3, #116 @ 0x74 8002920: edd3 7a00 vldr s15, [r3] 8002924: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 8002928: ee77 7a27 vadd.f32 s15, s14, s15 800292c: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 #ifdef PV_BOARD pvT1AveTemp += pvT1CircBuffer[i]; 8002930: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002934: 009b lsls r3, r3, #2 8002936: 33f0 adds r3, #240 @ 0xf0 8002938: 443b add r3, r7 800293a: 3b9c subs r3, #156 @ 0x9c 800293c: edd3 7a00 vldr s15, [r3] 8002940: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 8002944: ee77 7a27 vadd.f32 s15, s14, s15 8002948: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp += pvT2CircBuffer[i]; 800294c: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002950: 009b lsls r3, r3, #2 8002952: 33f0 adds r3, #240 @ 0xf0 8002954: 443b add r3, r7 8002956: 3bc4 subs r3, #196 @ 0xc4 8002958: edd3 7a00 vldr s15, [r3] 800295c: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 8002960: ee77 7a27 vadd.f32 s15, s14, s15 8002964: edc7 7a37 vstr s15, [r7, #220] @ 0xdc for (uint8_t i = 0; i < CIRC_BUFF_LEN; i++) { 8002968: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 800296c: 3301 adds r3, #1 800296e: f887 30db strb.w r3, [r7, #219] @ 0xdb 8002972: f897 30db ldrb.w r3, [r7, #219] @ 0xdb 8002976: 2b09 cmp r3, #9 8002978: d9be bls.n 80028f8 #endif } motorXAveCurrent /= CIRC_BUFF_LEN; 800297a: ed97 7a3a vldr s14, [r7, #232] @ 0xe8 800297e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002982: eec7 7a26 vdiv.f32 s15, s14, s13 8002986: edc7 7a3a vstr s15, [r7, #232] @ 0xe8 motorYAveCurrent /= CIRC_BUFF_LEN; 800298a: ed97 7a39 vldr s14, [r7, #228] @ 0xe4 800298e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 8002992: eec7 7a26 vdiv.f32 s15, s14, s13 8002996: edc7 7a39 vstr s15, [r7, #228] @ 0xe4 pvT1AveTemp /= CIRC_BUFF_LEN; 800299a: ed97 7a38 vldr s14, [r7, #224] @ 0xe0 800299e: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80029a2: eec7 7a26 vdiv.f32 s15, s14, s13 80029a6: edc7 7a38 vstr s15, [r7, #224] @ 0xe0 pvT2AveTemp /= CIRC_BUFF_LEN; 80029aa: ed97 7a37 vldr s14, [r7, #220] @ 0xdc 80029ae: eef2 6a04 vmov.f32 s13, #36 @ 0x41200000 10.0 80029b2: eec7 7a26 vdiv.f32 s15, s14, s13 80029b6: edc7 7a37 vstr s15, [r7, #220] @ 0xdc if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80029ba: 4b37 ldr r3, [pc, #220] @ (8002a98 ) 80029bc: 681b ldr r3, [r3, #0] 80029be: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80029c2: 4618 mov r0, r3 80029c4: f011 fd7b bl 80144be 80029c8: 4603 mov r3, r0 80029ca: 2b00 cmp r3, #0 80029cc: d138 bne.n 8002a40 if (sensorsInfo.motorXStatus == 1) { 80029ce: 4b33 ldr r3, [pc, #204] @ (8002a9c ) 80029d0: 7d1b ldrb r3, [r3, #20] 80029d2: 2b01 cmp r3, #1 80029d4: d111 bne.n 80029fa sensorsInfo.motorXAveCurrent = motorXAveCurrent; 80029d6: 4a31 ldr r2, [pc, #196] @ (8002a9c ) 80029d8: f8d7 30e8 ldr.w r3, [r7, #232] @ 0xe8 80029dc: 6193 str r3, [r2, #24] if (sensorsInfo.motorXPeakCurrent < motorXCurrentSense) { 80029de: 4b2f ldr r3, [pc, #188] @ (8002a9c ) 80029e0: edd3 7a08 vldr s15, [r3, #32] 80029e4: ed97 7a34 vldr s14, [r7, #208] @ 0xd0 80029e8: eeb4 7ae7 vcmpe.f32 s14, s15 80029ec: eef1 fa10 vmrs APSR_nzcv, fpscr 80029f0: dd03 ble.n 80029fa sensorsInfo.motorXPeakCurrent = motorXCurrentSense; 80029f2: 4a2a ldr r2, [pc, #168] @ (8002a9c ) 80029f4: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0 80029f8: 6213 str r3, [r2, #32] } } if (sensorsInfo.motorYStatus == 1) { 80029fa: 4b28 ldr r3, [pc, #160] @ (8002a9c ) 80029fc: 7d5b ldrb r3, [r3, #21] 80029fe: 2b01 cmp r3, #1 8002a00: d111 bne.n 8002a26 sensorsInfo.motorYAveCurrent = motorYAveCurrent; 8002a02: 4a26 ldr r2, [pc, #152] @ (8002a9c ) 8002a04: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8002a08: 61d3 str r3, [r2, #28] if (sensorsInfo.motorYPeakCurrent < motorYCurrentSense) { 8002a0a: 4b24 ldr r3, [pc, #144] @ (8002a9c ) 8002a0c: edd3 7a09 vldr s15, [r3, #36] @ 0x24 8002a10: ed97 7a33 vldr s14, [r7, #204] @ 0xcc 8002a14: eeb4 7ae7 vcmpe.f32 s14, s15 8002a18: eef1 fa10 vmrs APSR_nzcv, fpscr 8002a1c: dd03 ble.n 8002a26 sensorsInfo.motorYPeakCurrent = motorYCurrentSense; 8002a1e: 4a1f ldr r2, [pc, #124] @ (8002a9c ) 8002a20: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc 8002a24: 6253 str r3, [r2, #36] @ 0x24 } } sensorsInfo.pvTemperature[0] = pvT1AveTemp; 8002a26: 4a1d ldr r2, [pc, #116] @ (8002a9c ) 8002a28: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8002a2c: 6013 str r3, [r2, #0] sensorsInfo.pvTemperature[1] = pvT2AveTemp; 8002a2e: 4a1b ldr r2, [pc, #108] @ (8002a9c ) 8002a30: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8002a34: 6053 str r3, [r2, #4] osMutexRelease (sensorsInfoMutex); 8002a36: 4b18 ldr r3, [pc, #96] @ (8002a98 ) 8002a38: 681b ldr r3, [r3, #0] 8002a3a: 4618 mov r0, r3 8002a3c: f011 fd8a bl 8014554 } ++circBuffPos; 8002a40: f8d7 30ec ldr.w r3, [r7, #236] @ 0xec 8002a44: 3301 adds r3, #1 8002a46: f8c7 30ec str.w r3, [r7, #236] @ 0xec circBuffPos = circBuffPos % CIRC_BUFF_LEN; 8002a4a: f8d7 20ec ldr.w r2, [r7, #236] @ 0xec 8002a4e: 4b14 ldr r3, [pc, #80] @ (8002aa0 ) 8002a50: fba3 1302 umull r1, r3, r3, r2 8002a54: 08d9 lsrs r1, r3, #3 8002a56: 460b mov r3, r1 8002a58: 009b lsls r3, r3, #2 8002a5a: 440b add r3, r1 8002a5c: 005b lsls r3, r3, #1 8002a5e: 1ad3 subs r3, r2, r3 8002a60: f8c7 30ec str.w r3, [r7, #236] @ 0xec while (pdTRUE) { 8002a64: e68a b.n 800277c 8002a66: bf00 nop 8002a68: 00000000 .word 0x00000000 8002a6c: 40efffe0 .word 0x40efffe0 8002a70: 3ad18d26 .word 0x3ad18d26 8002a74: 4020aaaa .word 0x4020aaaa 8002a78: aaa38226 .word 0xaaa38226 8002a7c: 4046aaaa .word 0x4046aaaa 8002a80: 00000000 .word 0x00000000 8002a84: 404f8000 .word 0x404f8000 8002a88: 24000808 .word 0x24000808 8002a8c: 1ff1e860 .word 0x1ff1e860 8002a90: 24000814 .word 0x24000814 8002a94: 24000030 .word 0x24000030 8002a98: 2400081c .word 0x2400081c 8002a9c: 24000860 .word 0x24000860 8002aa0: cccccccd .word 0xcccccccd 08002aa4 : } } void LimiterSwitchTask (void* arg) { 8002aa4: b580 push {r7, lr} 8002aa6: b08a sub sp, #40 @ 0x28 8002aa8: af06 add r7, sp, #24 8002aaa: 6078 str r0, [r7, #4] LimiterSwitchData limiterSwitchData = { 0 }; 8002aac: 2300 movs r3, #0 8002aae: 60bb str r3, [r7, #8] limiterSwitchData.gpioPin = GPIO_PIN_8; 8002ab0: f44f 7380 mov.w r3, #256 @ 0x100 8002ab4: 813b strh r3, [r7, #8] for (uint8_t i = 0; i < 6; i++) { 8002ab6: 2300 movs r3, #0 8002ab8: 73fb strb r3, [r7, #15] 8002aba: e02c b.n 8002b16 limiterSwitchData.pinState = HAL_GPIO_ReadPin (GPIOD, limiterSwitchData.gpioPin); 8002abc: 893b ldrh r3, [r7, #8] 8002abe: 4619 mov r1, r3 8002ac0: 48a5 ldr r0, [pc, #660] @ (8002d58 ) 8002ac2: f008 fd37 bl 800b534 8002ac6: 4603 mov r3, r0 8002ac8: 72bb strb r3, [r7, #10] osMessageQueuePut (limiterSwitchDataQueue, &limiterSwitchData, 0, 0); 8002aca: 4ba4 ldr r3, [pc, #656] @ (8002d5c ) 8002acc: 6818 ldr r0, [r3, #0] 8002ace: f107 0108 add.w r1, r7, #8 8002ad2: 2300 movs r3, #0 8002ad4: 2200 movs r2, #0 8002ad6: f011 fded bl 80146b4 limiterSwitchData.gpioPin = limiterSwitchData.gpioPin << 1; 8002ada: 893b ldrh r3, [r7, #8] 8002adc: 005b lsls r3, r3, #1 8002ade: b29b uxth r3, r3 8002ae0: 813b strh r3, [r7, #8] if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002ae2: 4b9f ldr r3, [pc, #636] @ (8002d60 ) 8002ae4: 681b ldr r3, [r3, #0] 8002ae6: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002aea: 4618 mov r0, r3 8002aec: f011 fce7 bl 80144be 8002af0: 4603 mov r3, r0 8002af2: 2b00 cmp r3, #0 8002af4: d10c bne.n 8002b10 sensorsInfo.positionXWeak = 1; 8002af6: 4b9b ldr r3, [pc, #620] @ (8002d64 ) 8002af8: 2201 movs r2, #1 8002afa: f883 2038 strb.w r2, [r3, #56] @ 0x38 sensorsInfo.positionYWeak = 1; 8002afe: 4b99 ldr r3, [pc, #612] @ (8002d64 ) 8002b00: 2201 movs r2, #1 8002b02: f883 2039 strb.w r2, [r3, #57] @ 0x39 osMutexRelease (sensorsInfoMutex); 8002b06: 4b96 ldr r3, [pc, #600] @ (8002d60 ) 8002b08: 681b ldr r3, [r3, #0] 8002b0a: 4618 mov r0, r3 8002b0c: f011 fd22 bl 8014554 for (uint8_t i = 0; i < 6; i++) { 8002b10: 7bfb ldrb r3, [r7, #15] 8002b12: 3301 adds r3, #1 8002b14: 73fb strb r3, [r7, #15] 8002b16: 7bfb ldrb r3, [r7, #15] 8002b18: 2b05 cmp r3, #5 8002b1a: d9cf bls.n 8002abc } } while (pdTRUE) { osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002b1c: 4b8f ldr r3, [pc, #572] @ (8002d5c ) 8002b1e: 6818 ldr r0, [r3, #0] 8002b20: f107 0108 add.w r1, r7, #8 8002b24: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002b28: 2200 movs r2, #0 8002b2a: f011 fe23 bl 8014774 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002b2e: 4b8c ldr r3, [pc, #560] @ (8002d60 ) 8002b30: 681b ldr r3, [r3, #0] 8002b32: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002b36: 4618 mov r0, r3 8002b38: f011 fcc1 bl 80144be 8002b3c: 4603 mov r3, r0 8002b3e: 2b00 cmp r3, #0 8002b40: d1ec bne.n 8002b1c switch (limiterSwitchData.gpioPin) { 8002b42: 893b ldrh r3, [r7, #8] 8002b44: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002b48: f000 8094 beq.w 8002c74 8002b4c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8002b50: f300 80a8 bgt.w 8002ca4 8002b54: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002b58: d075 beq.n 8002c46 8002b5a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8002b5e: f300 80a1 bgt.w 8002ca4 8002b62: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002b66: d057 beq.n 8002c18 8002b68: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8002b6c: f300 809a bgt.w 8002ca4 8002b70: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b74: d039 beq.n 8002bea 8002b76: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002b7a: f300 8093 bgt.w 8002ca4 8002b7e: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002b82: d003 beq.n 8002b8c 8002b84: f5b3 7f00 cmp.w r3, #512 @ 0x200 8002b88: d017 beq.n 8002bba { sensorsInfo.currentXPosition = 0; sensorsInfo.positionXWeak = 0; } break; default: break; 8002b8a: e08b b.n 8002ca4 sensorsInfo.limitYSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002b8c: 7abb ldrb r3, [r7, #10] 8002b8e: 2b01 cmp r3, #1 8002b90: bf0c ite eq 8002b92: 2301 moveq r3, #1 8002b94: 2300 movne r3, #0 8002b96: b2db uxtb r3, r3 8002b98: 461a mov r2, r3 8002b9a: 4b72 ldr r3, [pc, #456] @ (8002d64 ) 8002b9c: f883 202d strb.w r2, [r3, #45] @ 0x2d if (sensorsInfo.limitYSwitchCenter == 1) 8002ba0: 4b70 ldr r3, [pc, #448] @ (8002d64 ) 8002ba2: f893 302d ldrb.w r3, [r3, #45] @ 0x2d 8002ba6: 2b01 cmp r3, #1 8002ba8: d17e bne.n 8002ca8 sensorsInfo.currentYPosition = AXE_Y_MIDDLE_VALUE; 8002baa: 4b6e ldr r3, [pc, #440] @ (8002d64 ) 8002bac: 4a6e ldr r2, [pc, #440] @ (8002d68 ) 8002bae: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002bb0: 4b6c ldr r3, [pc, #432] @ (8002d64 ) 8002bb2: 2200 movs r2, #0 8002bb4: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002bb8: e076 b.n 8002ca8 sensorsInfo.limitYSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002bba: 7abb ldrb r3, [r7, #10] 8002bbc: 2b01 cmp r3, #1 8002bbe: bf0c ite eq 8002bc0: 2301 moveq r3, #1 8002bc2: 2300 movne r3, #0 8002bc4: b2db uxtb r3, r3 8002bc6: 461a mov r2, r3 8002bc8: 4b66 ldr r3, [pc, #408] @ (8002d64 ) 8002bca: f883 202c strb.w r2, [r3, #44] @ 0x2c if (sensorsInfo.limitYSwitchDown == 1) 8002bce: 4b65 ldr r3, [pc, #404] @ (8002d64 ) 8002bd0: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002bd4: 2b01 cmp r3, #1 8002bd6: d169 bne.n 8002cac sensorsInfo.currentYPosition = 0; 8002bd8: 4b62 ldr r3, [pc, #392] @ (8002d64 ) 8002bda: f04f 0200 mov.w r2, #0 8002bde: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002be0: 4b60 ldr r3, [pc, #384] @ (8002d64 ) 8002be2: 2200 movs r2, #0 8002be4: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002be8: e060 b.n 8002cac sensorsInfo.limitXSwitchCenter = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002bea: 7abb ldrb r3, [r7, #10] 8002bec: 2b01 cmp r3, #1 8002bee: bf0c ite eq 8002bf0: 2301 moveq r3, #1 8002bf2: 2300 movne r3, #0 8002bf4: b2db uxtb r3, r3 8002bf6: 461a mov r2, r3 8002bf8: 4b5a ldr r3, [pc, #360] @ (8002d64 ) 8002bfa: f883 202a strb.w r2, [r3, #42] @ 0x2a if (sensorsInfo.limitXSwitchCenter == 1) 8002bfe: 4b59 ldr r3, [pc, #356] @ (8002d64 ) 8002c00: f893 302a ldrb.w r3, [r3, #42] @ 0x2a 8002c04: 2b01 cmp r3, #1 8002c06: d153 bne.n 8002cb0 sensorsInfo.currentXPosition = AXE_X_MIDDLE_VALUE; 8002c08: 4b56 ldr r3, [pc, #344] @ (8002d64 ) 8002c0a: 4a57 ldr r2, [pc, #348] @ (8002d68 ) 8002c0c: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c0e: 4b55 ldr r3, [pc, #340] @ (8002d64 ) 8002c10: 2200 movs r2, #0 8002c12: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002c16: e04b b.n 8002cb0 sensorsInfo.limitYSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c18: 7abb ldrb r3, [r7, #10] 8002c1a: 2b01 cmp r3, #1 8002c1c: bf0c ite eq 8002c1e: 2301 moveq r3, #1 8002c20: 2300 movne r3, #0 8002c22: b2db uxtb r3, r3 8002c24: 461a mov r2, r3 8002c26: 4b4f ldr r3, [pc, #316] @ (8002d64 ) 8002c28: f883 202b strb.w r2, [r3, #43] @ 0x2b if (sensorsInfo.limitYSwitchUp == 1) 8002c2c: 4b4d ldr r3, [pc, #308] @ (8002d64 ) 8002c2e: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002c32: 2b01 cmp r3, #1 8002c34: d13e bne.n 8002cb4 sensorsInfo.currentYPosition = 100; 8002c36: 4b4b ldr r3, [pc, #300] @ (8002d64 ) 8002c38: 4a4c ldr r2, [pc, #304] @ (8002d6c ) 8002c3a: 635a str r2, [r3, #52] @ 0x34 sensorsInfo.positionYWeak = 0; 8002c3c: 4b49 ldr r3, [pc, #292] @ (8002d64 ) 8002c3e: 2200 movs r2, #0 8002c40: f883 2039 strb.w r2, [r3, #57] @ 0x39 break; 8002c44: e036 b.n 8002cb4 sensorsInfo.limitXSwitchUp = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c46: 7abb ldrb r3, [r7, #10] 8002c48: 2b01 cmp r3, #1 8002c4a: bf0c ite eq 8002c4c: 2301 moveq r3, #1 8002c4e: 2300 movne r3, #0 8002c50: b2db uxtb r3, r3 8002c52: 461a mov r2, r3 8002c54: 4b43 ldr r3, [pc, #268] @ (8002d64 ) 8002c56: f883 2028 strb.w r2, [r3, #40] @ 0x28 if (sensorsInfo.limitXSwitchUp == 1) 8002c5a: 4b42 ldr r3, [pc, #264] @ (8002d64 ) 8002c5c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002c60: 2b01 cmp r3, #1 8002c62: d129 bne.n 8002cb8 sensorsInfo.currentXPosition = 100; 8002c64: 4b3f ldr r3, [pc, #252] @ (8002d64 ) 8002c66: 4a41 ldr r2, [pc, #260] @ (8002d6c ) 8002c68: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c6a: 4b3e ldr r3, [pc, #248] @ (8002d64 ) 8002c6c: 2200 movs r2, #0 8002c6e: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002c72: e021 b.n 8002cb8 sensorsInfo.limitXSwitchDown = limiterSwitchData.pinState == GPIO_PIN_SET ? 1 : 0; 8002c74: 7abb ldrb r3, [r7, #10] 8002c76: 2b01 cmp r3, #1 8002c78: bf0c ite eq 8002c7a: 2301 moveq r3, #1 8002c7c: 2300 movne r3, #0 8002c7e: b2db uxtb r3, r3 8002c80: 461a mov r2, r3 8002c82: 4b38 ldr r3, [pc, #224] @ (8002d64 ) 8002c84: f883 2029 strb.w r2, [r3, #41] @ 0x29 if (sensorsInfo.limitXSwitchDown == 1) 8002c88: 4b36 ldr r3, [pc, #216] @ (8002d64 ) 8002c8a: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002c8e: 2b01 cmp r3, #1 8002c90: d114 bne.n 8002cbc sensorsInfo.currentXPosition = 0; 8002c92: 4b34 ldr r3, [pc, #208] @ (8002d64 ) 8002c94: f04f 0200 mov.w r2, #0 8002c98: 631a str r2, [r3, #48] @ 0x30 sensorsInfo.positionXWeak = 0; 8002c9a: 4b32 ldr r3, [pc, #200] @ (8002d64 ) 8002c9c: 2200 movs r2, #0 8002c9e: f883 2038 strb.w r2, [r3, #56] @ 0x38 break; 8002ca2: e00b b.n 8002cbc default: break; 8002ca4: bf00 nop 8002ca6: e00a b.n 8002cbe break; 8002ca8: bf00 nop 8002caa: e008 b.n 8002cbe break; 8002cac: bf00 nop 8002cae: e006 b.n 8002cbe break; 8002cb0: bf00 nop 8002cb2: e004 b.n 8002cbe break; 8002cb4: bf00 nop 8002cb6: e002 b.n 8002cbe break; 8002cb8: bf00 nop 8002cba: e000 b.n 8002cbe break; 8002cbc: bf00 nop } if ((sensorsInfo.limitXSwitchDown == 1) || (sensorsInfo.limitXSwitchUp == 1)) { 8002cbe: 4b29 ldr r3, [pc, #164] @ (8002d64 ) 8002cc0: f893 3029 ldrb.w r3, [r3, #41] @ 0x29 8002cc4: 2b01 cmp r3, #1 8002cc6: d004 beq.n 8002cd2 8002cc8: 4b26 ldr r3, [pc, #152] @ (8002d64 ) 8002cca: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8002cce: 2b01 cmp r3, #1 8002cd0: d118 bne.n 8002d04 sensorsInfo.motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, 0, 0, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 8002cd2: 4b27 ldr r3, [pc, #156] @ (8002d70 ) 8002cd4: 681b ldr r3, [r3, #0] 8002cd6: 4a23 ldr r2, [pc, #140] @ (8002d64 ) 8002cd8: f892 2028 ldrb.w r2, [r2, #40] @ 0x28 8002cdc: 4921 ldr r1, [pc, #132] @ (8002d64 ) 8002cde: f891 1029 ldrb.w r1, [r1, #41] @ 0x29 8002ce2: 9104 str r1, [sp, #16] 8002ce4: 9203 str r2, [sp, #12] 8002ce6: 2200 movs r2, #0 8002ce8: 9202 str r2, [sp, #8] 8002cea: 2200 movs r2, #0 8002cec: 9201 str r2, [sp, #4] 8002cee: 9300 str r3, [sp, #0] 8002cf0: 2304 movs r3, #4 8002cf2: 2200 movs r2, #0 8002cf4: 491f ldr r1, [pc, #124] @ (8002d74 ) 8002cf6: 4820 ldr r0, [pc, #128] @ (8002d78 ) 8002cf8: f000 f982 bl 8003000 8002cfc: 4603 mov r3, r0 8002cfe: 461a mov r2, r3 8002d00: 4b18 ldr r3, [pc, #96] @ (8002d64 ) 8002d02: 751a strb r2, [r3, #20] } if ((sensorsInfo.limitYSwitchDown == 1) || (sensorsInfo.limitYSwitchUp == 1)) { 8002d04: 4b17 ldr r3, [pc, #92] @ (8002d64 ) 8002d06: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8002d0a: 2b01 cmp r3, #1 8002d0c: d004 beq.n 8002d18 8002d0e: 4b15 ldr r3, [pc, #84] @ (8002d64 ) 8002d10: f893 302b ldrb.w r3, [r3, #43] @ 0x2b 8002d14: 2b01 cmp r3, #1 8002d16: d118 bne.n 8002d4a sensorsInfo.motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, 0, 0, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 8002d18: 4b18 ldr r3, [pc, #96] @ (8002d7c ) 8002d1a: 681b ldr r3, [r3, #0] 8002d1c: 4a11 ldr r2, [pc, #68] @ (8002d64 ) 8002d1e: f892 202b ldrb.w r2, [r2, #43] @ 0x2b 8002d22: 4910 ldr r1, [pc, #64] @ (8002d64 ) 8002d24: f891 102c ldrb.w r1, [r1, #44] @ 0x2c 8002d28: 9104 str r1, [sp, #16] 8002d2a: 9203 str r2, [sp, #12] 8002d2c: 2200 movs r2, #0 8002d2e: 9202 str r2, [sp, #8] 8002d30: 2200 movs r2, #0 8002d32: 9201 str r2, [sp, #4] 8002d34: 9300 str r3, [sp, #0] 8002d36: 230c movs r3, #12 8002d38: 2208 movs r2, #8 8002d3a: 490e ldr r1, [pc, #56] @ (8002d74 ) 8002d3c: 480e ldr r0, [pc, #56] @ (8002d78 ) 8002d3e: f000 f95f bl 8003000 8002d42: 4603 mov r3, r0 8002d44: 461a mov r2, r3 8002d46: 4b07 ldr r3, [pc, #28] @ (8002d64 ) 8002d48: 755a strb r2, [r3, #21] } osMutexRelease (sensorsInfoMutex); 8002d4a: 4b05 ldr r3, [pc, #20] @ (8002d60 ) 8002d4c: 681b ldr r3, [r3, #0] 8002d4e: 4618 mov r0, r3 8002d50: f011 fc00 bl 8014554 osMessageQueueGet (limiterSwitchDataQueue, &limiterSwitchData, 0, osWaitForever); 8002d54: e6e2 b.n 8002b1c 8002d56: bf00 nop 8002d58: 58020c00 .word 0x58020c00 8002d5c: 2400080c .word 0x2400080c 8002d60: 2400081c .word 0x2400081c 8002d64: 24000860 .word 0x24000860 8002d68: 42480000 .word 0x42480000 8002d6c: 42c80000 .word 0x42c80000 8002d70: 24000744 .word 0x24000744 8002d74: 240007c0 .word 0x240007c0 8002d78: 240004d4 .word 0x240004d4 8002d7c: 24000774 .word 0x24000774 08002d80 : } } } void EncoderTask (void* arg) { 8002d80: b580 push {r7, lr} 8002d82: b086 sub sp, #24 8002d84: af00 add r7, sp, #0 8002d86: 6078 str r0, [r7, #4] EncoderData encoderData = { 0 }; 8002d88: 2300 movs r3, #0 8002d8a: 813b strh r3, [r7, #8] osMessageQueueId_t encoderQueue = (osMessageQueueId_t)arg; 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 617b str r3, [r7, #20] while (pdTRUE) { osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002d90: f107 0108 add.w r1, r7, #8 8002d94: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8002d98: 2200 movs r2, #0 8002d9a: 6978 ldr r0, [r7, #20] 8002d9c: f011 fcea bl 8014774 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8002da0: 4b4b ldr r3, [pc, #300] @ (8002ed0 ) 8002da2: 681b ldr r3, [r3, #0] 8002da4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8002da8: 4618 mov r0, r3 8002daa: f011 fb88 bl 80144be 8002dae: 4603 mov r3, r0 8002db0: 2b00 cmp r3, #0 8002db2: d1ed bne.n 8002d90 if (encoderData.axe == encoderAxeX) { 8002db4: 7a3b ldrb r3, [r7, #8] 8002db6: 2b00 cmp r3, #0 8002db8: d142 bne.n 8002e40 if (encoderData.direction == encoderCW) { 8002dba: 7a7b ldrb r3, [r7, #9] 8002dbc: 2b00 cmp r3, #0 8002dbe: d10a bne.n 8002dd6 sensorsInfo.pvEncoderX += 360.0 / ENCODER_X_IMP_PER_TURN; 8002dc0: 4b44 ldr r3, [pc, #272] @ (8002ed4 ) 8002dc2: edd3 7a03 vldr s15, [r3, #12] 8002dc6: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002dca: ee77 7a87 vadd.f32 s15, s15, s14 8002dce: 4b41 ldr r3, [pc, #260] @ (8002ed4 ) 8002dd0: edc3 7a03 vstr s15, [r3, #12] 8002dd4: e009 b.n 8002dea } else { sensorsInfo.pvEncoderX -= 360.0 / ENCODER_X_IMP_PER_TURN; 8002dd6: 4b3f ldr r3, [pc, #252] @ (8002ed4 ) 8002dd8: edd3 7a03 vldr s15, [r3, #12] 8002ddc: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002de0: ee77 7ac7 vsub.f32 s15, s15, s14 8002de4: 4b3b ldr r3, [pc, #236] @ (8002ed4 ) 8002de6: edc3 7a03 vstr s15, [r3, #12] } float currentPercentPos = 100 * sensorsInfo.pvEncoderX / MAX_X_AXE_ANGLE; 8002dea: 4b3a ldr r3, [pc, #232] @ (8002ed4 ) 8002dec: edd3 7a03 vldr s15, [r3, #12] 8002df0: ed9f 7a39 vldr s14, [pc, #228] @ 8002ed8 8002df4: ee27 7a87 vmul.f32 s14, s15, s14 8002df8: eddf 6a38 vldr s13, [pc, #224] @ 8002edc 8002dfc: eec7 7a26 vdiv.f32 s15, s14, s13 8002e00: edc7 7a03 vstr s15, [r7, #12] currentPercentPos = currentPercentPos < 0 ? 0 : currentPercentPos; 8002e04: edd7 7a03 vldr s15, [r7, #12] 8002e08: eef5 7ac0 vcmpe.f32 s15, #0.0 8002e0c: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e10: d502 bpl.n 8002e18 8002e12: f04f 0300 mov.w r3, #0 8002e16: e000 b.n 8002e1a 8002e18: 68fb ldr r3, [r7, #12] 8002e1a: 60fb str r3, [r7, #12] sensorsInfo.currentXPosition = currentPercentPos > 100 ? 100 : currentPercentPos; 8002e1c: edd7 7a03 vldr s15, [r7, #12] 8002e20: ed9f 7a2d vldr s14, [pc, #180] @ 8002ed8 8002e24: eef4 7ac7 vcmpe.f32 s15, s14 8002e28: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e2c: dd01 ble.n 8002e32 8002e2e: 4b2c ldr r3, [pc, #176] @ (8002ee0 ) 8002e30: e000 b.n 8002e34 8002e32: 68fb ldr r3, [r7, #12] 8002e34: 4a27 ldr r2, [pc, #156] @ (8002ed4 ) 8002e36: 6313 str r3, [r2, #48] @ 0x30 DbgLEDToggle(DBG_LED2); 8002e38: 2020 movs r0, #32 8002e3a: f000 f877 bl 8002f2c 8002e3e: e041 b.n 8002ec4 } else { if (encoderData.direction == encoderCW) { 8002e40: 7a7b ldrb r3, [r7, #9] 8002e42: 2b00 cmp r3, #0 8002e44: d10a bne.n 8002e5c sensorsInfo.pvEncoderY += 360.0 / ENCODER_Y_IMP_PER_TURN; 8002e46: 4b23 ldr r3, [pc, #140] @ (8002ed4 ) 8002e48: edd3 7a04 vldr s15, [r3, #16] 8002e4c: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002e50: ee77 7a87 vadd.f32 s15, s15, s14 8002e54: 4b1f ldr r3, [pc, #124] @ (8002ed4 ) 8002e56: edc3 7a04 vstr s15, [r3, #16] 8002e5a: e009 b.n 8002e70 } else { sensorsInfo.pvEncoderY -= 360.0 / ENCODER_Y_IMP_PER_TURN; 8002e5c: 4b1d ldr r3, [pc, #116] @ (8002ed4 ) 8002e5e: edd3 7a04 vldr s15, [r3, #16] 8002e62: eeb3 7a02 vmov.f32 s14, #50 @ 0x41900000 18.0 8002e66: ee77 7ac7 vsub.f32 s15, s15, s14 8002e6a: 4b1a ldr r3, [pc, #104] @ (8002ed4 ) 8002e6c: edc3 7a04 vstr s15, [r3, #16] } float currentPercentPos = 100 * sensorsInfo.pvEncoderY / MAX_X_AXE_ANGLE; 8002e70: 4b18 ldr r3, [pc, #96] @ (8002ed4 ) 8002e72: edd3 7a04 vldr s15, [r3, #16] 8002e76: ed9f 7a18 vldr s14, [pc, #96] @ 8002ed8 8002e7a: ee27 7a87 vmul.f32 s14, s15, s14 8002e7e: eddf 6a17 vldr s13, [pc, #92] @ 8002edc 8002e82: eec7 7a26 vdiv.f32 s15, s14, s13 8002e86: edc7 7a04 vstr s15, [r7, #16] currentPercentPos = currentPercentPos < 0 ? 0 : currentPercentPos; 8002e8a: edd7 7a04 vldr s15, [r7, #16] 8002e8e: eef5 7ac0 vcmpe.f32 s15, #0.0 8002e92: eef1 fa10 vmrs APSR_nzcv, fpscr 8002e96: d502 bpl.n 8002e9e 8002e98: f04f 0300 mov.w r3, #0 8002e9c: e000 b.n 8002ea0 8002e9e: 693b ldr r3, [r7, #16] 8002ea0: 613b str r3, [r7, #16] sensorsInfo.currentXPosition = currentPercentPos > 100 ? 100 : currentPercentPos; 8002ea2: edd7 7a04 vldr s15, [r7, #16] 8002ea6: ed9f 7a0c vldr s14, [pc, #48] @ 8002ed8 8002eaa: eef4 7ac7 vcmpe.f32 s15, s14 8002eae: eef1 fa10 vmrs APSR_nzcv, fpscr 8002eb2: dd01 ble.n 8002eb8 8002eb4: 4b0a ldr r3, [pc, #40] @ (8002ee0 ) 8002eb6: e000 b.n 8002eba 8002eb8: 693b ldr r3, [r7, #16] 8002eba: 4a06 ldr r2, [pc, #24] @ (8002ed4 ) 8002ebc: 6313 str r3, [r2, #48] @ 0x30 DbgLEDToggle(DBG_LED3); 8002ebe: 2040 movs r0, #64 @ 0x40 8002ec0: f000 f834 bl 8002f2c } osMutexRelease (sensorsInfoMutex); 8002ec4: 4b02 ldr r3, [pc, #8] @ (8002ed0 ) 8002ec6: 681b ldr r3, [r3, #0] 8002ec8: 4618 mov r0, r3 8002eca: f011 fb43 bl 8014554 osMessageQueueGet (encoderQueue, &encoderData, 0, osWaitForever); 8002ece: e75f b.n 8002d90 8002ed0: 2400081c .word 0x2400081c 8002ed4: 24000860 .word 0x24000860 8002ed8: 42c80000 .word 0x42c80000 8002edc: 43b40000 .word 0x43b40000 8002ee0: 42c80000 .word 0x42c80000 08002ee4 : #include #include "peripherial.h" void DbgLEDOn (uint8_t ledNumber) { 8002ee4: b580 push {r7, lr} 8002ee6: b082 sub sp, #8 8002ee8: af00 add r7, sp, #0 8002eea: 4603 mov r3, r0 8002eec: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_SET); 8002eee: 79fb ldrb r3, [r7, #7] 8002ef0: b29b uxth r3, r3 8002ef2: 2201 movs r2, #1 8002ef4: 4619 mov r1, r3 8002ef6: 4803 ldr r0, [pc, #12] @ (8002f04 ) 8002ef8: f008 fb34 bl 800b564 } 8002efc: bf00 nop 8002efe: 3708 adds r7, #8 8002f00: 46bd mov sp, r7 8002f02: bd80 pop {r7, pc} 8002f04: 58020c00 .word 0x58020c00 08002f08 : void DbgLEDOff (uint8_t ledNumber) { 8002f08: b580 push {r7, lr} 8002f0a: b082 sub sp, #8 8002f0c: af00 add r7, sp, #0 8002f0e: 4603 mov r3, r0 8002f10: 71fb strb r3, [r7, #7] HAL_GPIO_WritePin (GPIOD, ledNumber, GPIO_PIN_RESET); 8002f12: 79fb ldrb r3, [r7, #7] 8002f14: b29b uxth r3, r3 8002f16: 2200 movs r2, #0 8002f18: 4619 mov r1, r3 8002f1a: 4803 ldr r0, [pc, #12] @ (8002f28 ) 8002f1c: f008 fb22 bl 800b564 } 8002f20: bf00 nop 8002f22: 3708 adds r7, #8 8002f24: 46bd mov sp, r7 8002f26: bd80 pop {r7, pc} 8002f28: 58020c00 .word 0x58020c00 08002f2c : void DbgLEDToggle (uint8_t ledNumber) { 8002f2c: b580 push {r7, lr} 8002f2e: b082 sub sp, #8 8002f30: af00 add r7, sp, #0 8002f32: 4603 mov r3, r0 8002f34: 71fb strb r3, [r7, #7] HAL_GPIO_TogglePin (GPIOD, ledNumber); 8002f36: 79fb ldrb r3, [r7, #7] 8002f38: b29b uxth r3, r3 8002f3a: 4619 mov r1, r3 8002f3c: 4803 ldr r0, [pc, #12] @ (8002f4c ) 8002f3e: f008 fb2a bl 800b596 } 8002f42: bf00 nop 8002f44: 3708 adds r7, #8 8002f46: 46bd mov sp, r7 8002f48: bd80 pop {r7, pc} 8002f4a: bf00 nop 8002f4c: 58020c00 .word 0x58020c00 08002f50 : void EnableCurrentSensors (void) { 8002f50: b580 push {r7, lr} 8002f52: af00 add r7, sp, #0 HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_SET); 8002f54: 2201 movs r2, #1 8002f56: f44f 4100 mov.w r1, #32768 @ 0x8000 8002f5a: 4802 ldr r0, [pc, #8] @ (8002f64 ) 8002f5c: f008 fb02 bl 800b564 } 8002f60: bf00 nop 8002f62: bd80 pop {r7, pc} 8002f64: 58021000 .word 0x58021000 08002f68 : void DisableCurrentSensors (void) { HAL_GPIO_WritePin (GPIOE, MCU_CS_PWR_EN, GPIO_PIN_RESET); } void SelectCurrentSensorGain (CurrentSensor sensor, CurrentSensorGain gain) { 8002f68: b580 push {r7, lr} 8002f6a: b084 sub sp, #16 8002f6c: af00 add r7, sp, #0 8002f6e: 4603 mov r3, r0 8002f70: 460a mov r2, r1 8002f72: 71fb strb r3, [r7, #7] 8002f74: 4613 mov r3, r2 8002f76: 71bb strb r3, [r7, #6] uint8_t gpioOffset = 0; 8002f78: 2300 movs r3, #0 8002f7a: 73fb strb r3, [r7, #15] switch (sensor) { 8002f7c: 79fb ldrb r3, [r7, #7] 8002f7e: 2b02 cmp r3, #2 8002f80: d00c beq.n 8002f9c 8002f82: 2b02 cmp r3, #2 8002f84: dc0d bgt.n 8002fa2 8002f86: 2b00 cmp r3, #0 8002f88: d002 beq.n 8002f90 8002f8a: 2b01 cmp r3, #1 8002f8c: d003 beq.n 8002f96 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; default: break; 8002f8e: e008 b.n 8002fa2 case CurrentSensorL1: gpioOffset = CURRENT_SENSOR_L1_GPIO_OFFSET; break; 8002f90: 2307 movs r3, #7 8002f92: 73fb strb r3, [r7, #15] 8002f94: e006 b.n 8002fa4 case CurrentSensorL2: gpioOffset = CURRENT_SENSOR_L2_GPIO_OFFSET; break; 8002f96: 2309 movs r3, #9 8002f98: 73fb strb r3, [r7, #15] 8002f9a: e003 b.n 8002fa4 case CurrentSensorL3: gpioOffset = CURRENT_SENSOR_L3_GPIO_OFFSET; break; 8002f9c: 230d movs r3, #13 8002f9e: 73fb strb r3, [r7, #15] 8002fa0: e000 b.n 8002fa4 default: break; 8002fa2: bf00 nop } if (gpioOffset > 0) { 8002fa4: 7bfb ldrb r3, [r7, #15] 8002fa6: 2b00 cmp r3, #0 8002fa8: d023 beq.n 8002ff2 uint16_t gain0Gpio = 1 << gpioOffset; 8002faa: 7bfb ldrb r3, [r7, #15] 8002fac: 2201 movs r2, #1 8002fae: fa02 f303 lsl.w r3, r2, r3 8002fb2: 81bb strh r3, [r7, #12] uint16_t gain1Gpio = 1 << (gpioOffset + 1); 8002fb4: 7bfb ldrb r3, [r7, #15] 8002fb6: 3301 adds r3, #1 8002fb8: 2201 movs r2, #1 8002fba: fa02 f303 lsl.w r3, r2, r3 8002fbe: 817b strh r3, [r7, #10] uint16_t gpioState = ((uint16_t)gain) & 0x0001; 8002fc0: 79bb ldrb r3, [r7, #6] 8002fc2: b29b uxth r3, r3 8002fc4: f003 0301 and.w r3, r3, #1 8002fc8: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain0Gpio, gpioState); 8002fca: 893b ldrh r3, [r7, #8] 8002fcc: b2da uxtb r2, r3 8002fce: 89bb ldrh r3, [r7, #12] 8002fd0: 4619 mov r1, r3 8002fd2: 480a ldr r0, [pc, #40] @ (8002ffc ) 8002fd4: f008 fac6 bl 800b564 gpioState = (((uint16_t)gain) >> 1) & 0x0001; 8002fd8: 79bb ldrb r3, [r7, #6] 8002fda: 085b lsrs r3, r3, #1 8002fdc: b2db uxtb r3, r3 8002fde: f003 0301 and.w r3, r3, #1 8002fe2: 813b strh r3, [r7, #8] HAL_GPIO_WritePin (GPIOE, gain1Gpio, gpioState); 8002fe4: 893b ldrh r3, [r7, #8] 8002fe6: b2da uxtb r2, r3 8002fe8: 897b ldrh r3, [r7, #10] 8002fea: 4619 mov r1, r3 8002fec: 4803 ldr r0, [pc, #12] @ (8002ffc ) 8002fee: f008 fab9 bl 800b564 } } 8002ff2: bf00 nop 8002ff4: 3710 adds r7, #16 8002ff6: 46bd mov sp, r7 8002ff8: bd80 pop {r7, pc} 8002ffa: bf00 nop 8002ffc: 58021000 .word 0x58021000 08003000 : uint8_t MotorControl (TIM_HandleTypeDef* htim, TIM_OC_InitTypeDef* motorTimerConfigOC, uint8_t channel1, uint8_t channel2, osTimerId_t motorTimerHandle, int32_t motorPWMPulse, int32_t motorTimerPeriod, uint8_t switchLimiterUpStat, uint8_t switchLimiterDownStat) { 8003000: b580 push {r7, lr} 8003002: b088 sub sp, #32 8003004: af02 add r7, sp, #8 8003006: 60f8 str r0, [r7, #12] 8003008: 60b9 str r1, [r7, #8] 800300a: 4611 mov r1, r2 800300c: 461a mov r2, r3 800300e: 460b mov r3, r1 8003010: 71fb strb r3, [r7, #7] 8003012: 4613 mov r3, r2 8003014: 71bb strb r3, [r7, #6] uint32_t motorStatus = 0; 8003016: 2300 movs r3, #0 8003018: 617b str r3, [r7, #20] MotorDriverState setMotorState = HiZ; 800301a: 2300 movs r3, #0 800301c: 74fb strb r3, [r7, #19] HAL_TIM_PWM_Stop (htim, channel1); 800301e: 79fb ldrb r3, [r7, #7] 8003020: 4619 mov r1, r3 8003022: 68f8 ldr r0, [r7, #12] 8003024: f00c fca6 bl 800f974 HAL_TIM_PWM_Stop (htim, channel2); 8003028: 79bb ldrb r3, [r7, #6] 800302a: 4619 mov r1, r3 800302c: 68f8 ldr r0, [r7, #12] 800302e: f00c fca1 bl 800f974 if (motorTimerPeriod > 0) { 8003032: 6abb ldr r3, [r7, #40] @ 0x28 8003034: 2b00 cmp r3, #0 8003036: f340 808c ble.w 8003152 if (motorPWMPulse > 0) { 800303a: 6a7b ldr r3, [r7, #36] @ 0x24 800303c: 2b00 cmp r3, #0 800303e: dd2c ble.n 800309a // Forward if (switchLimiterUpStat == 0) { 8003040: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 8003044: 2b00 cmp r3, #0 8003046: d11d bne.n 8003084 setMotorState = Forward; 8003048: 2301 movs r3, #1 800304a: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800304c: 79f9 ldrb r1, [r7, #7] 800304e: 79b8 ldrb r0, [r7, #6] 8003050: 6a7b ldr r3, [r7, #36] @ 0x24 8003052: ea83 72e3 eor.w r2, r3, r3, asr #31 8003056: eba2 72e3 sub.w r2, r2, r3, asr #31 800305a: 4613 mov r3, r2 800305c: 009b lsls r3, r3, #2 800305e: 4413 add r3, r2 8003060: 005b lsls r3, r3, #1 8003062: 9301 str r3, [sp, #4] 8003064: 7cfb ldrb r3, [r7, #19] 8003066: 9300 str r3, [sp, #0] 8003068: 4603 mov r3, r0 800306a: 460a mov r2, r1 800306c: 68b9 ldr r1, [r7, #8] 800306e: 68f8 ldr r0, [r7, #12] 8003070: f000 f8ff bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 8003074: 79fb ldrb r3, [r7, #7] 8003076: 4619 mov r1, r3 8003078: 68f8 ldr r0, [r7, #12] 800307a: f00c fb6d bl 800f758 motorStatus = 1; 800307e: 2301 movs r3, #1 8003080: 617b str r3, [r7, #20] 8003082: e004 b.n 800308e } else { HAL_TIM_PWM_Stop (htim, channel1); 8003084: 79fb ldrb r3, [r7, #7] 8003086: 4619 mov r1, r3 8003088: 68f8 ldr r0, [r7, #12] 800308a: f00c fc73 bl 800f974 } HAL_TIM_PWM_Stop (htim, channel2); 800308e: 79bb ldrb r3, [r7, #6] 8003090: 4619 mov r1, r3 8003092: 68f8 ldr r0, [r7, #12] 8003094: f00c fc6e bl 800f974 8003098: e051 b.n 800313e } else if (motorPWMPulse < 0) { 800309a: 6a7b ldr r3, [r7, #36] @ 0x24 800309c: 2b00 cmp r3, #0 800309e: da2c bge.n 80030fa // Reverse if (switchLimiterDownStat == 0) { 80030a0: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 80030a4: 2b00 cmp r3, #0 80030a6: d11d bne.n 80030e4 setMotorState = Reverse; 80030a8: 2302 movs r3, #2 80030aa: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80030ac: 79f9 ldrb r1, [r7, #7] 80030ae: 79b8 ldrb r0, [r7, #6] 80030b0: 6a7b ldr r3, [r7, #36] @ 0x24 80030b2: ea83 72e3 eor.w r2, r3, r3, asr #31 80030b6: eba2 72e3 sub.w r2, r2, r3, asr #31 80030ba: 4613 mov r3, r2 80030bc: 009b lsls r3, r3, #2 80030be: 4413 add r3, r2 80030c0: 005b lsls r3, r3, #1 80030c2: 9301 str r3, [sp, #4] 80030c4: 7cfb ldrb r3, [r7, #19] 80030c6: 9300 str r3, [sp, #0] 80030c8: 4603 mov r3, r0 80030ca: 460a mov r2, r1 80030cc: 68b9 ldr r1, [r7, #8] 80030ce: 68f8 ldr r0, [r7, #12] 80030d0: f000 f8cf bl 8003272 HAL_TIM_PWM_Start (htim, channel2); 80030d4: 79bb ldrb r3, [r7, #6] 80030d6: 4619 mov r1, r3 80030d8: 68f8 ldr r0, [r7, #12] 80030da: f00c fb3d bl 800f758 motorStatus = 1; 80030de: 2301 movs r3, #1 80030e0: 617b str r3, [r7, #20] 80030e2: e004 b.n 80030ee } else { HAL_TIM_PWM_Stop (htim, channel2); 80030e4: 79bb ldrb r3, [r7, #6] 80030e6: 4619 mov r1, r3 80030e8: 68f8 ldr r0, [r7, #12] 80030ea: f00c fc43 bl 800f974 } HAL_TIM_PWM_Stop (htim, channel1); 80030ee: 79fb ldrb r3, [r7, #7] 80030f0: 4619 mov r1, r3 80030f2: 68f8 ldr r0, [r7, #12] 80030f4: f00c fc3e bl 800f974 80030f8: e021 b.n 800313e } else { // Brake setMotorState = Brake; 80030fa: 2303 movs r3, #3 80030fc: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80030fe: 79f9 ldrb r1, [r7, #7] 8003100: 79b8 ldrb r0, [r7, #6] 8003102: 6a7b ldr r3, [r7, #36] @ 0x24 8003104: ea83 72e3 eor.w r2, r3, r3, asr #31 8003108: eba2 72e3 sub.w r2, r2, r3, asr #31 800310c: 4613 mov r3, r2 800310e: 009b lsls r3, r3, #2 8003110: 4413 add r3, r2 8003112: 005b lsls r3, r3, #1 8003114: 9301 str r3, [sp, #4] 8003116: 7cfb ldrb r3, [r7, #19] 8003118: 9300 str r3, [sp, #0] 800311a: 4603 mov r3, r0 800311c: 460a mov r2, r1 800311e: 68b9 ldr r1, [r7, #8] 8003120: 68f8 ldr r0, [r7, #12] 8003122: f000 f8a6 bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 8003126: 79fb ldrb r3, [r7, #7] 8003128: 4619 mov r1, r3 800312a: 68f8 ldr r0, [r7, #12] 800312c: f00c fb14 bl 800f758 HAL_TIM_PWM_Start (htim, channel2); 8003130: 79bb ldrb r3, [r7, #6] 8003132: 4619 mov r1, r3 8003134: 68f8 ldr r0, [r7, #12] 8003136: f00c fb0f bl 800f758 motorStatus = 0; 800313a: 2300 movs r3, #0 800313c: 617b str r3, [r7, #20] } osTimerStart (motorTimerHandle, motorTimerPeriod * 1000); 800313e: 6abb ldr r3, [r7, #40] @ 0x28 8003140: f44f 727a mov.w r2, #1000 @ 0x3e8 8003144: fb02 f303 mul.w r3, r2, r3 8003148: 4619 mov r1, r3 800314a: 6a38 ldr r0, [r7, #32] 800314c: f011 f8cc bl 80142e8 8003150: e089 b.n 8003266 } else if ((motorTimerPeriod == 0) && (motorPWMPulse == 0)) { 8003152: 6abb ldr r3, [r7, #40] @ 0x28 8003154: 2b00 cmp r3, #0 8003156: d126 bne.n 80031a6 8003158: 6a7b ldr r3, [r7, #36] @ 0x24 800315a: 2b00 cmp r3, #0 800315c: d123 bne.n 80031a6 MotorAction (htim, motorTimerConfigOC, channel1, channel2, HiZ, abs (motorPWMPulse) * 10); 800315e: 79f9 ldrb r1, [r7, #7] 8003160: 79b8 ldrb r0, [r7, #6] 8003162: 6a7b ldr r3, [r7, #36] @ 0x24 8003164: ea83 72e3 eor.w r2, r3, r3, asr #31 8003168: eba2 72e3 sub.w r2, r2, r3, asr #31 800316c: 4613 mov r3, r2 800316e: 009b lsls r3, r3, #2 8003170: 4413 add r3, r2 8003172: 005b lsls r3, r3, #1 8003174: 9301 str r3, [sp, #4] 8003176: 2300 movs r3, #0 8003178: 9300 str r3, [sp, #0] 800317a: 4603 mov r3, r0 800317c: 460a mov r2, r1 800317e: 68b9 ldr r1, [r7, #8] 8003180: 68f8 ldr r0, [r7, #12] 8003182: f000 f876 bl 8003272 HAL_TIM_PWM_Stop (htim, channel1); 8003186: 79fb ldrb r3, [r7, #7] 8003188: 4619 mov r1, r3 800318a: 68f8 ldr r0, [r7, #12] 800318c: f00c fbf2 bl 800f974 HAL_TIM_PWM_Stop (htim, channel2); 8003190: 79bb ldrb r3, [r7, #6] 8003192: 4619 mov r1, r3 8003194: 68f8 ldr r0, [r7, #12] 8003196: f00c fbed bl 800f974 osTimerStop (motorTimerHandle); 800319a: 6a38 ldr r0, [r7, #32] 800319c: f011 f8d2 bl 8014344 motorStatus = 0; 80031a0: 2300 movs r3, #0 80031a2: 617b str r3, [r7, #20] 80031a4: e05f b.n 8003266 } else if (motorTimerPeriod == -1) { 80031a6: 6abb ldr r3, [r7, #40] @ 0x28 80031a8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80031ac: d15b bne.n 8003266 if (motorPWMPulse > 0) { 80031ae: 6a7b ldr r3, [r7, #36] @ 0x24 80031b0: 2b00 cmp r3, #0 80031b2: dd2c ble.n 800320e // Forward if (switchLimiterUpStat == 0) { 80031b4: f897 302c ldrb.w r3, [r7, #44] @ 0x2c 80031b8: 2b00 cmp r3, #0 80031ba: d11d bne.n 80031f8 setMotorState = Forward; 80031bc: 2301 movs r3, #1 80031be: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 80031c0: 79f9 ldrb r1, [r7, #7] 80031c2: 79b8 ldrb r0, [r7, #6] 80031c4: 6a7b ldr r3, [r7, #36] @ 0x24 80031c6: ea83 72e3 eor.w r2, r3, r3, asr #31 80031ca: eba2 72e3 sub.w r2, r2, r3, asr #31 80031ce: 4613 mov r3, r2 80031d0: 009b lsls r3, r3, #2 80031d2: 4413 add r3, r2 80031d4: 005b lsls r3, r3, #1 80031d6: 9301 str r3, [sp, #4] 80031d8: 7cfb ldrb r3, [r7, #19] 80031da: 9300 str r3, [sp, #0] 80031dc: 4603 mov r3, r0 80031de: 460a mov r2, r1 80031e0: 68b9 ldr r1, [r7, #8] 80031e2: 68f8 ldr r0, [r7, #12] 80031e4: f000 f845 bl 8003272 HAL_TIM_PWM_Start (htim, channel1); 80031e8: 79fb ldrb r3, [r7, #7] 80031ea: 4619 mov r1, r3 80031ec: 68f8 ldr r0, [r7, #12] 80031ee: f00c fab3 bl 800f758 motorStatus = 1; 80031f2: 2301 movs r3, #1 80031f4: 617b str r3, [r7, #20] 80031f6: e004 b.n 8003202 } else { HAL_TIM_PWM_Stop (htim, channel1); 80031f8: 79fb ldrb r3, [r7, #7] 80031fa: 4619 mov r1, r3 80031fc: 68f8 ldr r0, [r7, #12] 80031fe: f00c fbb9 bl 800f974 } HAL_TIM_PWM_Stop (htim, channel2); 8003202: 79bb ldrb r3, [r7, #6] 8003204: 4619 mov r1, r3 8003206: 68f8 ldr r0, [r7, #12] 8003208: f00c fbb4 bl 800f974 800320c: e02b b.n 8003266 } else { // Reverse if (switchLimiterDownStat == 0) { 800320e: f897 3030 ldrb.w r3, [r7, #48] @ 0x30 8003212: 2b00 cmp r3, #0 8003214: d11d bne.n 8003252 setMotorState = Reverse; 8003216: 2302 movs r3, #2 8003218: 74fb strb r3, [r7, #19] MotorAction (htim, motorTimerConfigOC, channel1, channel2, setMotorState, abs (motorPWMPulse) * 10); 800321a: 79f9 ldrb r1, [r7, #7] 800321c: 79b8 ldrb r0, [r7, #6] 800321e: 6a7b ldr r3, [r7, #36] @ 0x24 8003220: ea83 72e3 eor.w r2, r3, r3, asr #31 8003224: eba2 72e3 sub.w r2, r2, r3, asr #31 8003228: 4613 mov r3, r2 800322a: 009b lsls r3, r3, #2 800322c: 4413 add r3, r2 800322e: 005b lsls r3, r3, #1 8003230: 9301 str r3, [sp, #4] 8003232: 7cfb ldrb r3, [r7, #19] 8003234: 9300 str r3, [sp, #0] 8003236: 4603 mov r3, r0 8003238: 460a mov r2, r1 800323a: 68b9 ldr r1, [r7, #8] 800323c: 68f8 ldr r0, [r7, #12] 800323e: f000 f818 bl 8003272 HAL_TIM_PWM_Start (htim, channel2); 8003242: 79bb ldrb r3, [r7, #6] 8003244: 4619 mov r1, r3 8003246: 68f8 ldr r0, [r7, #12] 8003248: f00c fa86 bl 800f758 motorStatus = 1; 800324c: 2301 movs r3, #1 800324e: 617b str r3, [r7, #20] 8003250: e004 b.n 800325c } else { HAL_TIM_PWM_Stop (htim, channel2); 8003252: 79bb ldrb r3, [r7, #6] 8003254: 4619 mov r1, r3 8003256: 68f8 ldr r0, [r7, #12] 8003258: f00c fb8c bl 800f974 } HAL_TIM_PWM_Stop (htim, channel1); 800325c: 79fb ldrb r3, [r7, #7] 800325e: 4619 mov r1, r3 8003260: 68f8 ldr r0, [r7, #12] 8003262: f00c fb87 bl 800f974 } } return motorStatus; 8003266: 697b ldr r3, [r7, #20] 8003268: b2db uxtb r3, r3 } 800326a: 4618 mov r0, r3 800326c: 3718 adds r7, #24 800326e: 46bd mov sp, r7 8003270: bd80 pop {r7, pc} 08003272 : void MotorAction (TIM_HandleTypeDef* tim, TIM_OC_InitTypeDef* timerConf, uint32_t channel1, uint32_t channel2, MotorDriverState setState, uint32_t pulse) { 8003272: b580 push {r7, lr} 8003274: b084 sub sp, #16 8003276: af00 add r7, sp, #0 8003278: 60f8 str r0, [r7, #12] 800327a: 60b9 str r1, [r7, #8] 800327c: 607a str r2, [r7, #4] 800327e: 603b str r3, [r7, #0] timerConf->Pulse = pulse; 8003280: 68bb ldr r3, [r7, #8] 8003282: 69fa ldr r2, [r7, #28] 8003284: 605a str r2, [r3, #4] switch (setState) { 8003286: 7e3b ldrb r3, [r7, #24] 8003288: 2b02 cmp r3, #2 800328a: dc02 bgt.n 8003292 800328c: 2b00 cmp r3, #0 800328e: da03 bge.n 8003298 8003290: e038 b.n 8003304 8003292: 2b03 cmp r3, #3 8003294: d01b beq.n 80032ce 8003296: e035 b.n 8003304 case Forward: case Reverse: case HiZ: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003298: 68bb ldr r3, [r7, #8] 800329a: 2200 movs r2, #0 800329c: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800329e: 687a ldr r2, [r7, #4] 80032a0: 68b9 ldr r1, [r7, #8] 80032a2: 68f8 ldr r0, [r7, #12] 80032a4: f00c ff52 bl 801014c 80032a8: 4603 mov r3, r0 80032aa: 2b00 cmp r3, #0 80032ac: d001 beq.n 80032b2 Error_Handler (); 80032ae: f7fe fe0d bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 80032b2: 68bb ldr r3, [r7, #8] 80032b4: 2200 movs r2, #0 80032b6: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80032b8: 683a ldr r2, [r7, #0] 80032ba: 68b9 ldr r1, [r7, #8] 80032bc: 68f8 ldr r0, [r7, #12] 80032be: f00c ff45 bl 801014c 80032c2: 4603 mov r3, r0 80032c4: 2b00 cmp r3, #0 80032c6: d038 beq.n 800333a Error_Handler (); 80032c8: f7fe fe00 bl 8001ecc } break; 80032cc: e035 b.n 800333a case Brake: timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80032ce: 68bb ldr r3, [r7, #8] 80032d0: 2202 movs r2, #2 80032d2: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 80032d4: 687a ldr r2, [r7, #4] 80032d6: 68b9 ldr r1, [r7, #8] 80032d8: 68f8 ldr r0, [r7, #12] 80032da: f00c ff37 bl 801014c 80032de: 4603 mov r3, r0 80032e0: 2b00 cmp r3, #0 80032e2: d001 beq.n 80032e8 Error_Handler (); 80032e4: f7fe fdf2 bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_LOW; 80032e8: 68bb ldr r3, [r7, #8] 80032ea: 2202 movs r2, #2 80032ec: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 80032ee: 683a ldr r2, [r7, #0] 80032f0: 68b9 ldr r1, [r7, #8] 80032f2: 68f8 ldr r0, [r7, #12] 80032f4: f00c ff2a bl 801014c 80032f8: 4603 mov r3, r0 80032fa: 2b00 cmp r3, #0 80032fc: d01f beq.n 800333e Error_Handler (); 80032fe: f7fe fde5 bl 8001ecc } break; 8003302: e01c b.n 800333e default: timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 8003304: 68bb ldr r3, [r7, #8] 8003306: 2200 movs r2, #0 8003308: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel1) != HAL_OK) { 800330a: 687a ldr r2, [r7, #4] 800330c: 68b9 ldr r1, [r7, #8] 800330e: 68f8 ldr r0, [r7, #12] 8003310: f00c ff1c bl 801014c 8003314: 4603 mov r3, r0 8003316: 2b00 cmp r3, #0 8003318: d001 beq.n 800331e Error_Handler (); 800331a: f7fe fdd7 bl 8001ecc } timerConf->OCPolarity = TIM_OCPOLARITY_HIGH; 800331e: 68bb ldr r3, [r7, #8] 8003320: 2200 movs r2, #0 8003322: 609a str r2, [r3, #8] if (HAL_TIM_PWM_ConfigChannel (tim, timerConf, channel2) != HAL_OK) { 8003324: 683a ldr r2, [r7, #0] 8003326: 68b9 ldr r1, [r7, #8] 8003328: 68f8 ldr r0, [r7, #12] 800332a: f00c ff0f bl 801014c 800332e: 4603 mov r3, r0 8003330: 2b00 cmp r3, #0 8003332: d006 beq.n 8003342 Error_Handler (); 8003334: f7fe fdca bl 8001ecc } break; 8003338: e003 b.n 8003342 break; 800333a: bf00 nop 800333c: e002 b.n 8003344 break; 800333e: bf00 nop 8003340: e000 b.n 8003344 break; 8003342: bf00 nop } } 8003344: bf00 nop 8003346: 3710 adds r7, #16 8003348: 46bd mov sp, r7 800334a: bd80 pop {r7, pc} 0800334c : extern osTimerId_t motorXTimerHandle; extern osTimerId_t motorYTimerHandle; extern TIM_HandleTypeDef htim3; extern TIM_OC_InitTypeDef motorXYTimerConfigOC; void PositionControlTaskInit (void) { 800334c: b580 push {r7, lr} 800334e: b08a sub sp, #40 @ 0x28 8003350: af00 add r7, sp, #0 positionSettingMutex = osMutexNew (NULL); 8003352: 2000 movs r0, #0 8003354: f011 f82d bl 80143b2 8003358: 4603 mov r3, r0 800335a: 4a42 ldr r2, [pc, #264] @ (8003464 ) 800335c: 6013 str r3, [r2, #0] osThreadAttr_t osThreadAttrPositionControlTask = { 0 }; 800335e: 1d3b adds r3, r7, #4 8003360: 2224 movs r2, #36 @ 0x24 8003362: 2100 movs r1, #0 8003364: 4618 mov r0, r3 8003366: f014 ffd7 bl 8018318 osThreadAttrPositionControlTask.stack_size = configMINIMAL_STACK_SIZE * 2; 800336a: f44f 6380 mov.w r3, #1024 @ 0x400 800336e: 61bb str r3, [r7, #24] osThreadAttrPositionControlTask.priority = (osPriority_t)osPriorityNormal; 8003370: 2318 movs r3, #24 8003372: 61fb str r3, [r7, #28] positionXControlTaskInitArg.channel1 = TIM_CHANNEL_1; 8003374: 4b3c ldr r3, [pc, #240] @ (8003468 ) 8003376: 2200 movs r2, #0 8003378: 721a strb r2, [r3, #8] positionXControlTaskInitArg.channel2 = TIM_CHANNEL_2; 800337a: 4b3b ldr r3, [pc, #236] @ (8003468 ) 800337c: 2204 movs r2, #4 800337e: 725a strb r2, [r3, #9] positionXControlTaskInitArg.htim = &htim3; 8003380: 4b39 ldr r3, [pc, #228] @ (8003468 ) 8003382: 4a3a ldr r2, [pc, #232] @ (800346c ) 8003384: 601a str r2, [r3, #0] positionXControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 8003386: 4b38 ldr r3, [pc, #224] @ (8003468 ) 8003388: 4a39 ldr r2, [pc, #228] @ (8003470 ) 800338a: 605a str r2, [r3, #4] positionXControlTaskInitArg.motorTimerHandle = motorXTimerHandle; 800338c: 4b39 ldr r3, [pc, #228] @ (8003474 ) 800338e: 681b ldr r3, [r3, #0] 8003390: 4a35 ldr r2, [pc, #212] @ (8003468 ) 8003392: 60d3 str r3, [r2, #12] positionXControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 8003394: 2200 movs r2, #0 8003396: 2104 movs r1, #4 8003398: 2010 movs r0, #16 800339a: f011 f918 bl 80145ce 800339e: 4603 mov r3, r0 80033a0: 4a31 ldr r2, [pc, #196] @ (8003468 ) 80033a2: 6113 str r3, [r2, #16] positionXControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitXSwitchCenter); 80033a4: 4b30 ldr r3, [pc, #192] @ (8003468 ) 80033a6: 4a34 ldr r2, [pc, #208] @ (8003478 ) 80033a8: 61da str r2, [r3, #28] positionXControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitXSwitchUp); 80033aa: 4b2f ldr r3, [pc, #188] @ (8003468 ) 80033ac: 4a33 ldr r2, [pc, #204] @ (800347c ) 80033ae: 615a str r2, [r3, #20] positionXControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitXSwitchDown); 80033b0: 4b2d ldr r3, [pc, #180] @ (8003468 ) 80033b2: 4a33 ldr r2, [pc, #204] @ (8003480 ) 80033b4: 619a str r2, [r3, #24] positionXControlTaskInitArg.currentPosition = &(sensorsInfo.currentXPosition); 80033b6: 4b2c ldr r3, [pc, #176] @ (8003468 ) 80033b8: 4a32 ldr r2, [pc, #200] @ (8003484 ) 80033ba: 621a str r2, [r3, #32] positionXControlTaskInitArg.motorStatus = &(sensorsInfo.motorXStatus); 80033bc: 4b2a ldr r3, [pc, #168] @ (8003468 ) 80033be: 4a32 ldr r2, [pc, #200] @ (8003488 ) 80033c0: 629a str r2, [r3, #40] @ 0x28 positionXControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorXPeakCurrent); 80033c2: 4b29 ldr r3, [pc, #164] @ (8003468 ) 80033c4: 4a31 ldr r2, [pc, #196] @ (800348c ) 80033c6: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionXSetting; 80033c8: 4b27 ldr r3, [pc, #156] @ (8003468 ) 80033ca: 4a31 ldr r2, [pc, #196] @ (8003490 ) 80033cc: 625a str r2, [r3, #36] @ 0x24 positionXControlTaskInitArg.axe = 'X'; 80033ce: 4b26 ldr r3, [pc, #152] @ (8003468 ) 80033d0: 2258 movs r2, #88 @ 0x58 80033d2: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionYControlTaskInitArg.channel1 = TIM_CHANNEL_3; 80033d6: 4b2f ldr r3, [pc, #188] @ (8003494 ) 80033d8: 2208 movs r2, #8 80033da: 721a strb r2, [r3, #8] positionYControlTaskInitArg.channel2 = TIM_CHANNEL_4; 80033dc: 4b2d ldr r3, [pc, #180] @ (8003494 ) 80033de: 220c movs r2, #12 80033e0: 725a strb r2, [r3, #9] positionYControlTaskInitArg.htim = &htim3; 80033e2: 4b2c ldr r3, [pc, #176] @ (8003494 ) 80033e4: 4a21 ldr r2, [pc, #132] @ (800346c ) 80033e6: 601a str r2, [r3, #0] positionYControlTaskInitArg.motorTimerConfigOC = &motorXYTimerConfigOC; 80033e8: 4b2a ldr r3, [pc, #168] @ (8003494 ) 80033ea: 4a21 ldr r2, [pc, #132] @ (8003470 ) 80033ec: 605a str r2, [r3, #4] positionYControlTaskInitArg.motorTimerHandle = motorYTimerHandle; 80033ee: 4b2a ldr r3, [pc, #168] @ (8003498 ) 80033f0: 681b ldr r3, [r3, #0] 80033f2: 4a28 ldr r2, [pc, #160] @ (8003494 ) 80033f4: 60d3 str r3, [r2, #12] positionYControlTaskInitArg.positionSettingQueue = osMessageQueueNew (16, sizeof (PositionControlTaskData), NULL); 80033f6: 2200 movs r2, #0 80033f8: 2104 movs r1, #4 80033fa: 2010 movs r0, #16 80033fc: f011 f8e7 bl 80145ce 8003400: 4603 mov r3, r0 8003402: 4a24 ldr r2, [pc, #144] @ (8003494 ) 8003404: 6113 str r3, [r2, #16] positionYControlTaskInitArg.switchLimiterCenterStat = &(sensorsInfo.limitYSwitchCenter); 8003406: 4b23 ldr r3, [pc, #140] @ (8003494 ) 8003408: 4a24 ldr r2, [pc, #144] @ (800349c ) 800340a: 61da str r2, [r3, #28] positionYControlTaskInitArg.switchLimiterUpStat = &(sensorsInfo.limitYSwitchUp); 800340c: 4b21 ldr r3, [pc, #132] @ (8003494 ) 800340e: 4a24 ldr r2, [pc, #144] @ (80034a0 ) 8003410: 615a str r2, [r3, #20] positionYControlTaskInitArg.switchLimiterDownStat = &(sensorsInfo.limitYSwitchDown); 8003412: 4b20 ldr r3, [pc, #128] @ (8003494 ) 8003414: 4a23 ldr r2, [pc, #140] @ (80034a4 ) 8003416: 619a str r2, [r3, #24] positionYControlTaskInitArg.currentPosition = &(sensorsInfo.currentYPosition); 8003418: 4b1e ldr r3, [pc, #120] @ (8003494 ) 800341a: 4a23 ldr r2, [pc, #140] @ (80034a8 ) 800341c: 621a str r2, [r3, #32] positionYControlTaskInitArg.motorStatus = &(sensorsInfo.motorYStatus); 800341e: 4b1d ldr r3, [pc, #116] @ (8003494 ) 8003420: 4a22 ldr r2, [pc, #136] @ (80034ac ) 8003422: 629a str r2, [r3, #40] @ 0x28 positionYControlTaskInitArg.motorPeakCurrent = &(sensorsInfo.motorYPeakCurrent); 8003424: 4b1b ldr r3, [pc, #108] @ (8003494 ) 8003426: 4a22 ldr r2, [pc, #136] @ (80034b0 ) 8003428: 62da str r2, [r3, #44] @ 0x2c positionXControlTaskInitArg.positionSetting = &positionYSetting; 800342a: 4b0f ldr r3, [pc, #60] @ (8003468 ) 800342c: 4a21 ldr r2, [pc, #132] @ (80034b4 ) 800342e: 625a str r2, [r3, #36] @ 0x24 positionYControlTaskInitArg.axe = 'Y'; 8003430: 4b18 ldr r3, [pc, #96] @ (8003494 ) 8003432: 2259 movs r2, #89 @ 0x59 8003434: f883 2030 strb.w r2, [r3, #48] @ 0x30 positionXControlTaskHandle = osThreadNew (PositionControlTask, &positionXControlTaskInitArg, &osThreadAttrPositionControlTask); 8003438: 1d3b adds r3, r7, #4 800343a: 461a mov r2, r3 800343c: 490a ldr r1, [pc, #40] @ (8003468 ) 800343e: 481e ldr r0, [pc, #120] @ (80034b8 ) 8003440: f010 fe12 bl 8014068 8003444: 4603 mov r3, r0 8003446: 4a1d ldr r2, [pc, #116] @ (80034bc ) 8003448: 6013 str r3, [r2, #0] positionYControlTaskHandle = osThreadNew (PositionControlTask, &positionYControlTaskInitArg, &osThreadAttrPositionControlTask); 800344a: 1d3b adds r3, r7, #4 800344c: 461a mov r2, r3 800344e: 4911 ldr r1, [pc, #68] @ (8003494 ) 8003450: 4819 ldr r0, [pc, #100] @ (80034b8 ) 8003452: f010 fe09 bl 8014068 8003456: 4603 mov r3, r0 8003458: 4a19 ldr r2, [pc, #100] @ (80034c0 ) 800345a: 6013 str r3, [r2, #0] } 800345c: bf00 nop 800345e: 3728 adds r7, #40 @ 0x28 8003460: 46bd mov sp, r7 8003462: bd80 pop {r7, pc} 8003464: 240008a8 .word 0x240008a8 8003468: 240008b4 .word 0x240008b4 800346c: 240004d4 .word 0x240004d4 8003470: 240007c0 .word 0x240007c0 8003474: 24000744 .word 0x24000744 8003478: 2400088a .word 0x2400088a 800347c: 24000888 .word 0x24000888 8003480: 24000889 .word 0x24000889 8003484: 24000890 .word 0x24000890 8003488: 24000874 .word 0x24000874 800348c: 24000880 .word 0x24000880 8003490: 240008a0 .word 0x240008a0 8003494: 240008e8 .word 0x240008e8 8003498: 24000774 .word 0x24000774 800349c: 2400088d .word 0x2400088d 80034a0: 2400088b .word 0x2400088b 80034a4: 2400088c .word 0x2400088c 80034a8: 24000894 .word 0x24000894 80034ac: 24000875 .word 0x24000875 80034b0: 24000884 .word 0x24000884 80034b4: 240008a4 .word 0x240008a4 80034b8: 080034c5 .word 0x080034c5 80034bc: 240008ac .word 0x240008ac 80034c0: 240008b0 .word 0x240008b0 080034c4 : void PositionControlTask (void* argument) { 80034c4: b5f0 push {r4, r5, r6, r7, lr} 80034c6: b097 sub sp, #92 @ 0x5c 80034c8: af06 add r7, sp, #24 80034ca: 6078 str r0, [r7, #4] const int32_t PositionControlTaskTimeOut = 100; 80034cc: 2364 movs r3, #100 @ 0x64 80034ce: 623b str r3, [r7, #32] PositionControlTaskInitArg* posCtrlTaskArg = (PositionControlTaskInitArg*)argument; 80034d0: 687b ldr r3, [r7, #4] 80034d2: 61fb str r3, [r7, #28] PositionControlTaskData posCtrlData = { 0 }; 80034d4: f04f 0300 mov.w r3, #0 80034d8: 60bb str r3, [r7, #8] uint32_t motorStatus = 0; 80034da: 2300 movs r3, #0 80034dc: 61bb str r3, [r7, #24] osStatus_t queueSatus; int32_t pwmValue = MOTOR_START_STOP_PWM_VALUE; 80034de: 233c movs r3, #60 @ 0x3c 80034e0: 63fb str r3, [r7, #60] @ 0x3c int32_t sign = 0; 80034e2: 2300 movs r3, #0 80034e4: 63bb str r3, [r7, #56] @ 0x38 MovementPhases movementPhase = idlePhase; 80034e6: 2300 movs r3, #0 80034e8: f887 3037 strb.w r3, [r7, #55] @ 0x37 float startPosition = 0; 80034ec: f04f 0300 mov.w r3, #0 80034f0: 633b str r3, [r7, #48] @ 0x30 float prevPosition = 0; 80034f2: f04f 0300 mov.w r3, #0 80034f6: 62fb str r3, [r7, #44] @ 0x2c int32_t timeLeftMS = 0; 80034f8: 2300 movs r3, #0 80034fa: 62bb str r3, [r7, #40] @ 0x28 int32_t moveCmdTimeoutCounter = 0; 80034fc: 2300 movs r3, #0 80034fe: 627b str r3, [r7, #36] @ 0x24 while (pdTRUE) { queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 8003500: 69fb ldr r3, [r7, #28] 8003502: 6918 ldr r0, [r3, #16] 8003504: 6a3b ldr r3, [r7, #32] 8003506: f44f 727a mov.w r2, #1000 @ 0x3e8 800350a: fb02 f303 mul.w r3, r2, r3 800350e: 4aa1 ldr r2, [pc, #644] @ (8003794 ) 8003510: fba2 2303 umull r2, r3, r2, r3 8003514: 099b lsrs r3, r3, #6 8003516: f107 0108 add.w r1, r7, #8 800351a: 2200 movs r2, #0 800351c: f011 f92a bl 8014774 8003520: 6178 str r0, [r7, #20] if (queueSatus == osOK) { 8003522: 697b ldr r3, [r7, #20] 8003524: 2b00 cmp r3, #0 8003526: d14a bne.n 80035be if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8003528: 4b9b ldr r3, [pc, #620] @ (8003798 ) 800352a: 681b ldr r3, [r3, #0] 800352c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003530: 4618 mov r0, r3 8003532: f010 ffc4 bl 80144be 8003536: 4603 mov r3, r0 8003538: 2b00 cmp r3, #0 800353a: d1e1 bne.n 8003500 float posDiff = posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition; 800353c: ed97 7a02 vldr s14, [r7, #8] 8003540: 69fb ldr r3, [r7, #28] 8003542: 6a1b ldr r3, [r3, #32] 8003544: edd3 7a00 vldr s15, [r3] 8003548: ee77 7a67 vsub.f32 s15, s14, s15 800354c: edc7 7a03 vstr s15, [r7, #12] if (posDiff != 0) { 8003550: edd7 7a03 vldr s15, [r7, #12] 8003554: eef5 7a40 vcmp.f32 s15, #0.0 8003558: eef1 fa10 vmrs APSR_nzcv, fpscr 800355c: d016 beq.n 800358c sign = posDiff > 0 ? 1 : -1; 800355e: edd7 7a03 vldr s15, [r7, #12] 8003562: eef5 7ac0 vcmpe.f32 s15, #0.0 8003566: eef1 fa10 vmrs APSR_nzcv, fpscr 800356a: dd01 ble.n 8003570 800356c: 2301 movs r3, #1 800356e: e001 b.n 8003574 8003570: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8003574: 63bb str r3, [r7, #56] @ 0x38 startPosition = *posCtrlTaskArg->currentPosition; 8003576: 69fb ldr r3, [r7, #28] 8003578: 6a1b ldr r3, [r3, #32] 800357a: 681b ldr r3, [r3, #0] 800357c: 633b str r3, [r7, #48] @ 0x30 movementPhase = startPhase; 800357e: 2301 movs r3, #1 8003580: f887 3037 strb.w r3, [r7, #55] @ 0x37 moveCmdTimeoutCounter = 0; 8003584: 2300 movs r3, #0 8003586: 627b str r3, [r7, #36] @ 0x24 timeLeftMS = 0; 8003588: 2300 movs r3, #0 800358a: 62bb str r3, [r7, #40] @ 0x28 #ifdef DBG_POSITION printf ("Axe %c start phase\n", posCtrlTaskArg->axe); #endif } osMutexRelease (sensorsInfoMutex); 800358c: 4b82 ldr r3, [pc, #520] @ (8003798 ) 800358e: 681b ldr r3, [r3, #0] 8003590: 4618 mov r0, r3 8003592: f010 ffdf bl 8014554 if (osMutexAcquire (positionSettingMutex, osWaitForever) == osOK) { 8003596: 4b81 ldr r3, [pc, #516] @ (800379c ) 8003598: 681b ldr r3, [r3, #0] 800359a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800359e: 4618 mov r0, r3 80035a0: f010 ff8d bl 80144be 80035a4: 4603 mov r3, r0 80035a6: 2b00 cmp r3, #0 80035a8: d1aa bne.n 8003500 *positionXControlTaskInitArg.positionSetting = posCtrlData.positionSettingValue; 80035aa: 4b7d ldr r3, [pc, #500] @ (80037a0 ) 80035ac: 6a5b ldr r3, [r3, #36] @ 0x24 80035ae: 68ba ldr r2, [r7, #8] 80035b0: 601a str r2, [r3, #0] osMutexRelease (positionSettingMutex); 80035b2: 4b7a ldr r3, [pc, #488] @ (800379c ) 80035b4: 681b ldr r3, [r3, #0] 80035b6: 4618 mov r0, r3 80035b8: f010 ffcc bl 8014554 80035bc: e7a0 b.n 8003500 } } } else if (queueSatus == osErrorTimeout) { 80035be: 697b ldr r3, [r7, #20] 80035c0: f113 0f02 cmn.w r3, #2 80035c4: d19c bne.n 8003500 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80035c6: 4b74 ldr r3, [pc, #464] @ (8003798 ) 80035c8: 681b ldr r3, [r3, #0] 80035ca: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80035ce: 4618 mov r0, r3 80035d0: f010 ff75 bl 80144be 80035d4: 4603 mov r3, r0 80035d6: 2b00 cmp r3, #0 80035d8: d192 bne.n 8003500 if (((*posCtrlTaskArg->motorStatus != 0) && (movementPhase != idlePhase)) || (movementPhase == startPhase) ) { 80035da: 69fb ldr r3, [r7, #28] 80035dc: 6a9b ldr r3, [r3, #40] @ 0x28 80035de: 781b ldrb r3, [r3, #0] 80035e0: 2b00 cmp r3, #0 80035e2: d003 beq.n 80035ec 80035e4: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80035e8: 2b00 cmp r3, #0 80035ea: d104 bne.n 80035f6 80035ec: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80035f0: 2b01 cmp r3, #1 80035f2: f040 81c4 bne.w 800397e if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 80035f6: 69fb ldr r3, [r7, #28] 80035f8: 699b ldr r3, [r3, #24] 80035fa: 781b ldrb r3, [r3, #0] 80035fc: 2b01 cmp r3, #1 80035fe: d104 bne.n 800360a 8003600: 69fb ldr r3, [r7, #28] 8003602: 695b ldr r3, [r3, #20] 8003604: 781b ldrb r3, [r3, #0] 8003606: 2b01 cmp r3, #1 8003608: d009 beq.n 800361e ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 800360a: 69fb ldr r3, [r7, #28] 800360c: 695b ldr r3, [r3, #20] 800360e: 781b ldrb r3, [r3, #0] if (((*posCtrlTaskArg->switchLimiterDownStat == 1) && (*posCtrlTaskArg->switchLimiterUpStat == 1)) || 8003610: 2b01 cmp r3, #1 8003612: d12a bne.n 800366a ((*posCtrlTaskArg->switchLimiterUpStat == 1) && (*posCtrlTaskArg->switchLimiterCenterStat == 1))) { 8003614: 69fb ldr r3, [r7, #28] 8003616: 69db ldr r3, [r3, #28] 8003618: 781b ldrb r3, [r3, #0] 800361a: 2b01 cmp r3, #1 800361c: d125 bne.n 800366a movementPhase = idlePhase; 800361e: 2300 movs r3, #0 8003620: f887 3037 strb.w r3, [r7, #55] @ 0x37 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003624: 69fb ldr r3, [r7, #28] 8003626: 6818 ldr r0, [r3, #0] 8003628: 69fb ldr r3, [r7, #28] 800362a: 685c ldr r4, [r3, #4] 800362c: 69fb ldr r3, [r7, #28] 800362e: 7a1d ldrb r5, [r3, #8] 8003630: 69fb ldr r3, [r7, #28] 8003632: 7a5e ldrb r6, [r3, #9] 8003634: 69fb ldr r3, [r7, #28] 8003636: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003638: 69fa ldr r2, [r7, #28] 800363a: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 800363c: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800363e: 69f9 ldr r1, [r7, #28] 8003640: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 8003642: 7809 ldrb r1, [r1, #0] 8003644: 9104 str r1, [sp, #16] 8003646: 9203 str r2, [sp, #12] 8003648: 2200 movs r2, #0 800364a: 9202 str r2, [sp, #8] 800364c: 2200 movs r2, #0 800364e: 9201 str r2, [sp, #4] 8003650: 9300 str r3, [sp, #0] 8003652: 4633 mov r3, r6 8003654: 462a mov r2, r5 8003656: 4621 mov r1, r4 8003658: f7ff fcd2 bl 8003000 800365c: 4603 mov r3, r0 800365e: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003660: 69fb ldr r3, [r7, #28] 8003662: 6a9b ldr r3, [r3, #40] @ 0x28 8003664: 69ba ldr r2, [r7, #24] 8003666: b2d2 uxtb r2, r2 8003668: 701a strb r2, [r3, #0] printf ("Axe %c limiters wrong state - idle phase\n", posCtrlTaskArg->axe); #endif } timeLeftMS += PositionControlTaskTimeOut; 800366a: 6aba ldr r2, [r7, #40] @ 0x28 800366c: 6a3b ldr r3, [r7, #32] 800366e: 4413 add r3, r2 8003670: 62bb str r3, [r7, #40] @ 0x28 if (prevPosition == *posCtrlTaskArg->currentPosition) { 8003672: 69fb ldr r3, [r7, #28] 8003674: 6a1b ldr r3, [r3, #32] 8003676: edd3 7a00 vldr s15, [r3] 800367a: ed97 7a0b vldr s14, [r7, #44] @ 0x2c 800367e: eeb4 7a67 vcmp.f32 s14, s15 8003682: eef1 fa10 vmrs APSR_nzcv, fpscr 8003686: d104 bne.n 8003692 moveCmdTimeoutCounter += PositionControlTaskTimeOut; 8003688: 6a7a ldr r2, [r7, #36] @ 0x24 800368a: 6a3b ldr r3, [r7, #32] 800368c: 4413 add r3, r2 800368e: 627b str r3, [r7, #36] @ 0x24 8003690: e001 b.n 8003696 } else { moveCmdTimeoutCounter = 0; 8003692: 2300 movs r3, #0 8003694: 627b str r3, [r7, #36] @ 0x24 } prevPosition = *posCtrlTaskArg->currentPosition; 8003696: 69fb ldr r3, [r7, #28] 8003698: 6a1b ldr r3, [r3, #32] 800369a: 681b ldr r3, [r3, #0] 800369c: 62fb str r3, [r7, #44] @ 0x2c if (moveCmdTimeoutCounter > NO_MOVE_TIMEOUT_MS) { 800369e: 6a7b ldr r3, [r7, #36] @ 0x24 80036a0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80036a4: dd25 ble.n 80036f2 movementPhase = idlePhase; 80036a6: 2300 movs r3, #0 80036a8: f887 3037 strb.w r3, [r7, #55] @ 0x37 motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036ac: 69fb ldr r3, [r7, #28] 80036ae: 6818 ldr r0, [r3, #0] 80036b0: 69fb ldr r3, [r7, #28] 80036b2: 685c ldr r4, [r3, #4] 80036b4: 69fb ldr r3, [r7, #28] 80036b6: 7a1d ldrb r5, [r3, #8] 80036b8: 69fb ldr r3, [r7, #28] 80036ba: 7a5e ldrb r6, [r3, #9] 80036bc: 69fb ldr r3, [r7, #28] 80036be: 68db ldr r3, [r3, #12] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80036c0: 69fa ldr r2, [r7, #28] 80036c2: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036c4: 7812 ldrb r2, [r2, #0] 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80036c6: 69f9 ldr r1, [r7, #28] 80036c8: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 0, 80036ca: 7809 ldrb r1, [r1, #0] 80036cc: 9104 str r1, [sp, #16] 80036ce: 9203 str r2, [sp, #12] 80036d0: 2200 movs r2, #0 80036d2: 9202 str r2, [sp, #8] 80036d4: 2200 movs r2, #0 80036d6: 9201 str r2, [sp, #4] 80036d8: 9300 str r3, [sp, #0] 80036da: 4633 mov r3, r6 80036dc: 462a mov r2, r5 80036de: 4621 mov r1, r4 80036e0: f7ff fc8e bl 8003000 80036e4: 4603 mov r3, r0 80036e6: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80036e8: 69fb ldr r3, [r7, #28] 80036ea: 6a9b ldr r3, [r3, #40] @ 0x28 80036ec: 69ba ldr r2, [r7, #24] 80036ee: b2d2 uxtb r2, r2 80036f0: 701a strb r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c no movement idle phase\n", posCtrlTaskArg->axe); #endif } switch (movementPhase) { 80036f2: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 80036f6: 3b01 subs r3, #1 80036f8: 2b04 cmp r3, #4 80036fa: f200 8138 bhi.w 800396e 80036fe: a201 add r2, pc, #4 @ (adr r2, 8003704 ) 8003700: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8003704: 08003719 .word 0x08003719 8003708: 080037a5 .word 0x080037a5 800370c: 0800382f .word 0x0800382f 8003710: 0800387d .word 0x0800387d 8003714: 080038df .word 0x080038df case startPhase: motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003718: 69fb ldr r3, [r7, #28] 800371a: 681c ldr r4, [r3, #0] 800371c: 69fb ldr r3, [r7, #28] 800371e: 685d ldr r5, [r3, #4] 8003720: 69fb ldr r3, [r7, #28] 8003722: 7a1e ldrb r6, [r3, #8] 8003724: 69fb ldr r3, [r7, #28] 8003726: f893 c009 ldrb.w ip, [r3, #9] 800372a: 69fb ldr r3, [r7, #28] 800372c: 68db ldr r3, [r3, #12] 800372e: 6bba ldr r2, [r7, #56] @ 0x38 8003730: 6bf9 ldr r1, [r7, #60] @ 0x3c 8003732: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003736: 69f9 ldr r1, [r7, #28] 8003738: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800373a: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800373c: 69f8 ldr r0, [r7, #28] 800373e: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003740: 7800 ldrb r0, [r0, #0] 8003742: 9004 str r0, [sp, #16] 8003744: 9103 str r1, [sp, #12] 8003746: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800374a: 9102 str r1, [sp, #8] 800374c: 9201 str r2, [sp, #4] 800374e: 9300 str r3, [sp, #0] 8003750: 4663 mov r3, ip 8003752: 4632 mov r2, r6 8003754: 4629 mov r1, r5 8003756: 4620 mov r0, r4 8003758: f7ff fc52 bl 8003000 800375c: 4603 mov r3, r0 800375e: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 8003760: 69fb ldr r3, [r7, #28] 8003762: 6a9b ldr r3, [r3, #40] @ 0x28 8003764: 69ba ldr r2, [r7, #24] 8003766: b2d2 uxtb r2, r2 8003768: 701a strb r2, [r3, #0] if (motorStatus == 1) { 800376a: 69bb ldr r3, [r7, #24] 800376c: 2b01 cmp r3, #1 800376e: d10c bne.n 800378a *posCtrlTaskArg->motorPeakCurrent = 0.0; 8003770: 69fb ldr r3, [r7, #28] 8003772: 6adb ldr r3, [r3, #44] @ 0x2c 8003774: f04f 0200 mov.w r2, #0 8003778: 601a str r2, [r3, #0] #ifdef DBG_POSITION printf ("Axe %c speed up phase\n", posCtrlTaskArg->axe); #endif movementPhase = speedUpPhase; 800377a: 2302 movs r3, #2 800377c: f887 3037 strb.w r3, [r7, #55] @ 0x37 timeLeftMS = 0; 8003780: 2300 movs r3, #0 8003782: 62bb str r3, [r7, #40] @ 0x28 moveCmdTimeoutCounter = 0; 8003784: 2300 movs r3, #0 8003786: 627b str r3, [r7, #36] @ 0x24 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 8003788: e0f8 b.n 800397c movementPhase = idlePhase; 800378a: 2300 movs r3, #0 800378c: f887 3037 strb.w r3, [r7, #55] @ 0x37 break; 8003790: e0f4 b.n 800397c 8003792: bf00 nop 8003794: 10624dd3 .word 0x10624dd3 8003798: 2400081c .word 0x2400081c 800379c: 240008a8 .word 0x240008a8 80037a0: 240008b4 .word 0x240008b4 case speedUpPhase: if ((abs (*posCtrlTaskArg->currentPosition - startPosition) >= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 80037a4: 69fb ldr r3, [r7, #28] 80037a6: 6a1b ldr r3, [r3, #32] 80037a8: ed93 7a00 vldr s14, [r3] 80037ac: edd7 7a0c vldr s15, [r7, #48] @ 0x30 80037b0: ee77 7a67 vsub.f32 s15, s14, s15 80037b4: eefd 7ae7 vcvt.s32.f32 s15, s15 80037b8: ee17 3a90 vmov r3, s15 80037bc: 2b00 cmp r3, #0 80037be: bfb8 it lt 80037c0: 425b neglt r3, r3 80037c2: 2b04 cmp r3, #4 80037c4: dc04 bgt.n 80037d0 80037c6: 6abb ldr r3, [r7, #40] @ 0x28 80037c8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80037cc: f2c0 80d1 blt.w 8003972 pwmValue = MOTOR_HIGH_SPEED_PWM_VALUE; 80037d0: 2364 movs r3, #100 @ 0x64 80037d2: 63fb str r3, [r7, #60] @ 0x3c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037d4: 69fb ldr r3, [r7, #28] 80037d6: 681c ldr r4, [r3, #0] 80037d8: 69fb ldr r3, [r7, #28] 80037da: 685d ldr r5, [r3, #4] 80037dc: 69fb ldr r3, [r7, #28] 80037de: 7a1e ldrb r6, [r3, #8] 80037e0: 69fb ldr r3, [r7, #28] 80037e2: f893 c009 ldrb.w ip, [r3, #9] 80037e6: 69fb ldr r3, [r7, #28] 80037e8: 68db ldr r3, [r3, #12] 80037ea: 6bba ldr r2, [r7, #56] @ 0x38 80037ec: 6bf9 ldr r1, [r7, #60] @ 0x3c 80037ee: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037f2: 69f9 ldr r1, [r7, #28] 80037f4: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037f6: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80037f8: 69f8 ldr r0, [r7, #28] 80037fa: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80037fc: 7800 ldrb r0, [r0, #0] 80037fe: 9004 str r0, [sp, #16] 8003800: 9103 str r1, [sp, #12] 8003802: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8003806: 9102 str r1, [sp, #8] 8003808: 9201 str r2, [sp, #4] 800380a: 9300 str r3, [sp, #0] 800380c: 4663 mov r3, ip 800380e: 4632 mov r2, r6 8003810: 4629 mov r1, r5 8003812: 4620 mov r0, r4 8003814: f7ff fbf4 bl 8003000 8003818: 4603 mov r3, r0 800381a: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 800381c: 69fb ldr r3, [r7, #28] 800381e: 6a9b ldr r3, [r3, #40] @ 0x28 8003820: 69ba ldr r2, [r7, #24] 8003822: b2d2 uxtb r2, r2 8003824: 701a strb r2, [r3, #0] movementPhase = movePhase; 8003826: 2303 movs r3, #3 8003828: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c move phase\n", posCtrlTaskArg->axe); #endif } break; 800382c: e0a1 b.n 8003972 case movePhase: if (abs (*posCtrlTaskArg->currentPosition - *posCtrlTaskArg->positionSetting) <= ANGLE_RANGE_FOR_MOTOR_SPEED_LIMIT) { 800382e: 69fb ldr r3, [r7, #28] 8003830: 6a1b ldr r3, [r3, #32] 8003832: ed93 7a00 vldr s14, [r3] 8003836: 69fb ldr r3, [r7, #28] 8003838: 6a5b ldr r3, [r3, #36] @ 0x24 800383a: edd3 7a00 vldr s15, [r3] 800383e: ee77 7a67 vsub.f32 s15, s14, s15 8003842: eefd 7ae7 vcvt.s32.f32 s15, s15 8003846: ee17 3a90 vmov r3, s15 800384a: f113 0f05 cmn.w r3, #5 800384e: f2c0 8092 blt.w 8003976 8003852: 69fb ldr r3, [r7, #28] 8003854: 6a1b ldr r3, [r3, #32] 8003856: ed93 7a00 vldr s14, [r3] 800385a: 69fb ldr r3, [r7, #28] 800385c: 6a5b ldr r3, [r3, #36] @ 0x24 800385e: edd3 7a00 vldr s15, [r3] 8003862: ee77 7a67 vsub.f32 s15, s14, s15 8003866: eefd 7ae7 vcvt.s32.f32 s15, s15 800386a: ee17 3a90 vmov r3, s15 800386e: 2b05 cmp r3, #5 8003870: f300 8081 bgt.w 8003976 movementPhase = slowDownPhase; 8003874: 2304 movs r3, #4 8003876: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c slow down phase\n", posCtrlTaskArg->axe); #endif } break; 800387a: e07c b.n 8003976 case slowDownPhase: pwmValue = MOTOR_START_STOP_PWM_VALUE; 800387c: 233c movs r3, #60 @ 0x3c 800387e: 63fb str r3, [r7, #60] @ 0x3c motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003880: 69fb ldr r3, [r7, #28] 8003882: 681c ldr r4, [r3, #0] 8003884: 69fb ldr r3, [r7, #28] 8003886: 685d ldr r5, [r3, #4] 8003888: 69fb ldr r3, [r7, #28] 800388a: 7a1e ldrb r6, [r3, #8] 800388c: 69fb ldr r3, [r7, #28] 800388e: f893 c009 ldrb.w ip, [r3, #9] 8003892: 69fb ldr r3, [r7, #28] 8003894: 68db ldr r3, [r3, #12] 8003896: 6bba ldr r2, [r7, #56] @ 0x38 8003898: 6bf9 ldr r1, [r7, #60] @ 0x3c 800389a: fb01 f202 mul.w r2, r1, r2 sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800389e: 69f9 ldr r1, [r7, #28] 80038a0: 6949 ldr r1, [r1, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80038a2: 7809 ldrb r1, [r1, #0] sign * pwmValue, -1, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 80038a4: 69f8 ldr r0, [r7, #28] 80038a6: 6980 ldr r0, [r0, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 80038a8: 7800 ldrb r0, [r0, #0] 80038aa: 9004 str r0, [sp, #16] 80038ac: 9103 str r1, [sp, #12] 80038ae: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80038b2: 9102 str r1, [sp, #8] 80038b4: 9201 str r2, [sp, #4] 80038b6: 9300 str r3, [sp, #0] 80038b8: 4663 mov r3, ip 80038ba: 4632 mov r2, r6 80038bc: 4629 mov r1, r5 80038be: 4620 mov r0, r4 80038c0: f7ff fb9e bl 8003000 80038c4: 4603 mov r3, r0 80038c6: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 80038c8: 69fb ldr r3, [r7, #28] 80038ca: 6a9b ldr r3, [r3, #40] @ 0x28 80038cc: 69ba ldr r2, [r7, #24] 80038ce: b2d2 uxtb r2, r2 80038d0: 701a strb r2, [r3, #0] movementPhase = stopPhase; 80038d2: 2305 movs r3, #5 80038d4: f887 3037 strb.w r3, [r7, #55] @ 0x37 timeLeftMS = 0; 80038d8: 2300 movs r3, #0 80038da: 62bb str r3, [r7, #40] @ 0x28 #ifdef DBG_POSITION printf ("Axe %c stop phase\n", posCtrlTaskArg->axe); #endif break; 80038dc: e04e b.n 800397c case stopPhase: float posDiff = sign > 0 ? posCtrlData.positionSettingValue - *posCtrlTaskArg->currentPosition : *posCtrlTaskArg->currentPosition - posCtrlData.positionSettingValue; 80038de: 6bbb ldr r3, [r7, #56] @ 0x38 80038e0: 2b00 cmp r3, #0 80038e2: dd08 ble.n 80038f6 80038e4: ed97 7a02 vldr s14, [r7, #8] 80038e8: 69fb ldr r3, [r7, #28] 80038ea: 6a1b ldr r3, [r3, #32] 80038ec: edd3 7a00 vldr s15, [r3] 80038f0: ee77 7a67 vsub.f32 s15, s14, s15 80038f4: e007 b.n 8003906 80038f6: 69fb ldr r3, [r7, #28] 80038f8: 6a1b ldr r3, [r3, #32] 80038fa: ed93 7a00 vldr s14, [r3] 80038fe: edd7 7a02 vldr s15, [r7, #8] 8003902: ee77 7a67 vsub.f32 s15, s14, s15 8003906: edc7 7a04 vstr s15, [r7, #16] if ((posDiff <= 0) || (timeLeftMS >= TIME_MS_FOR_MOTOR_SPEED_LIMIT)) { 800390a: edd7 7a04 vldr s15, [r7, #16] 800390e: eef5 7ac0 vcmpe.f32 s15, #0.0 8003912: eef1 fa10 vmrs APSR_nzcv, fpscr 8003916: d903 bls.n 8003920 8003918: 6abb ldr r3, [r7, #40] @ 0x28 800391a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800391e: db2c blt.n 800397a motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003920: 69fb ldr r3, [r7, #28] 8003922: 6818 ldr r0, [r3, #0] 8003924: 69fb ldr r3, [r7, #28] 8003926: 685c ldr r4, [r3, #4] 8003928: 69fb ldr r3, [r7, #28] 800392a: 7a1d ldrb r5, [r3, #8] 800392c: 69fb ldr r3, [r7, #28] 800392e: 7a5e ldrb r6, [r3, #9] 8003930: 69fb ldr r3, [r7, #28] 8003932: 68db ldr r3, [r3, #12] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 8003934: 69fa ldr r2, [r7, #28] 8003936: 6952 ldr r2, [r2, #20] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 8003938: 7812 ldrb r2, [r2, #0] 0, 0, *posCtrlTaskArg->switchLimiterUpStat, *posCtrlTaskArg->switchLimiterDownStat); 800393a: 69f9 ldr r1, [r7, #28] 800393c: 6989 ldr r1, [r1, #24] motorStatus = MotorControl (posCtrlTaskArg->htim, posCtrlTaskArg->motorTimerConfigOC, posCtrlTaskArg->channel1, posCtrlTaskArg->channel2, posCtrlTaskArg->motorTimerHandle, 800393e: 7809 ldrb r1, [r1, #0] 8003940: 9104 str r1, [sp, #16] 8003942: 9203 str r2, [sp, #12] 8003944: 2200 movs r2, #0 8003946: 9202 str r2, [sp, #8] 8003948: 2200 movs r2, #0 800394a: 9201 str r2, [sp, #4] 800394c: 9300 str r3, [sp, #0] 800394e: 4633 mov r3, r6 8003950: 462a mov r2, r5 8003952: 4621 mov r1, r4 8003954: f7ff fb54 bl 8003000 8003958: 4603 mov r3, r0 800395a: 61bb str r3, [r7, #24] *posCtrlTaskArg->motorStatus = motorStatus; 800395c: 69fb ldr r3, [r7, #28] 800395e: 6a9b ldr r3, [r3, #40] @ 0x28 8003960: 69ba ldr r2, [r7, #24] 8003962: b2d2 uxtb r2, r2 8003964: 701a strb r2, [r3, #0] movementPhase = idlePhase; 8003966: 2300 movs r3, #0 8003968: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } break; 800396c: e005 b.n 800397a default: break; 800396e: bf00 nop 8003970: e011 b.n 8003996 break; 8003972: bf00 nop 8003974: e00f b.n 8003996 break; 8003976: bf00 nop 8003978: e00d b.n 8003996 break; 800397a: bf00 nop switch (movementPhase) { 800397c: e00b b.n 8003996 } } else { if ((*posCtrlTaskArg->motorStatus == 0) && (movementPhase != idlePhase)) { 800397e: 69fb ldr r3, [r7, #28] 8003980: 6a9b ldr r3, [r3, #40] @ 0x28 8003982: 781b ldrb r3, [r3, #0] 8003984: 2b00 cmp r3, #0 8003986: d106 bne.n 8003996 8003988: f897 3037 ldrb.w r3, [r7, #55] @ 0x37 800398c: 2b00 cmp r3, #0 800398e: d002 beq.n 8003996 movementPhase = idlePhase; 8003990: 2300 movs r3, #0 8003992: f887 3037 strb.w r3, [r7, #55] @ 0x37 #ifdef DBG_POSITION printf ("Axe %c idle phase\n", posCtrlTaskArg->axe); #endif } } osMutexRelease (sensorsInfoMutex); 8003996: 4b03 ldr r3, [pc, #12] @ (80039a4 ) 8003998: 681b ldr r3, [r3, #0] 800399a: 4618 mov r0, r3 800399c: f010 fdda bl 8014554 queueSatus = osMessageQueueGet (posCtrlTaskArg->positionSettingQueue, &posCtrlData, 0, pdMS_TO_TICKS (PositionControlTaskTimeOut)); 80039a0: e5ae b.n 8003500 80039a2: bf00 nop 80039a4: 2400081c .word 0x2400081c 080039a8 : buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); } *buffPos = newBuffPos; } void WriteDataToBuffer (uint8_t* buff, uint16_t* buffPos, void* data, uint8_t dataSize) { 80039a8: b480 push {r7} 80039aa: b089 sub sp, #36 @ 0x24 80039ac: af00 add r7, sp, #0 80039ae: 60f8 str r0, [r7, #12] 80039b0: 60b9 str r1, [r7, #8] 80039b2: 607a str r2, [r7, #4] 80039b4: 70fb strb r3, [r7, #3] uint32_t* uDataPtr = data; 80039b6: 687b ldr r3, [r7, #4] 80039b8: 61bb str r3, [r7, #24] uint32_t uData = *uDataPtr; 80039ba: 69bb ldr r3, [r7, #24] 80039bc: 681b ldr r3, [r3, #0] 80039be: 617b str r3, [r7, #20] uint8_t i = 0; 80039c0: 2300 movs r3, #0 80039c2: 77fb strb r3, [r7, #31] uint8_t newBuffPos = *buffPos; 80039c4: 68bb ldr r3, [r7, #8] 80039c6: 881b ldrh r3, [r3, #0] 80039c8: 77bb strb r3, [r7, #30] for (i = 0; i < dataSize; i++) { 80039ca: 2300 movs r3, #0 80039cc: 77fb strb r3, [r7, #31] 80039ce: e00e b.n 80039ee buff[newBuffPos++] = (uint8_t)((uData >> (i * 8)) & 0xFF); 80039d0: 7ffb ldrb r3, [r7, #31] 80039d2: 00db lsls r3, r3, #3 80039d4: 697a ldr r2, [r7, #20] 80039d6: 40da lsrs r2, r3 80039d8: 7fbb ldrb r3, [r7, #30] 80039da: 1c59 adds r1, r3, #1 80039dc: 77b9 strb r1, [r7, #30] 80039de: 4619 mov r1, r3 80039e0: 68fb ldr r3, [r7, #12] 80039e2: 440b add r3, r1 80039e4: b2d2 uxtb r2, r2 80039e6: 701a strb r2, [r3, #0] for (i = 0; i < dataSize; i++) { 80039e8: 7ffb ldrb r3, [r7, #31] 80039ea: 3301 adds r3, #1 80039ec: 77fb strb r3, [r7, #31] 80039ee: 7ffa ldrb r2, [r7, #31] 80039f0: 78fb ldrb r3, [r7, #3] 80039f2: 429a cmp r2, r3 80039f4: d3ec bcc.n 80039d0 } *buffPos = newBuffPos; 80039f6: 7fbb ldrb r3, [r7, #30] 80039f8: b29a uxth r2, r3 80039fa: 68bb ldr r3, [r7, #8] 80039fc: 801a strh r2, [r3, #0] } 80039fe: bf00 nop 8003a00: 3724 adds r7, #36 @ 0x24 8003a02: 46bd mov sp, r7 8003a04: f85d 7b04 ldr.w r7, [sp], #4 8003a08: 4770 bx lr 08003a0a : void ReadFloatFromBuffer(uint8_t* buff, uint16_t* buffPos, float* data) { 8003a0a: b480 push {r7} 8003a0c: b087 sub sp, #28 8003a0e: af00 add r7, sp, #0 8003a10: 60f8 str r0, [r7, #12] 8003a12: 60b9 str r1, [r7, #8] 8003a14: 607a str r2, [r7, #4] uint32_t* word = (uint32_t *)data; 8003a16: 687b ldr r3, [r7, #4] 8003a18: 617b str r3, [r7, #20] *word = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8003a1a: 68bb ldr r3, [r7, #8] 8003a1c: 881b ldrh r3, [r3, #0] 8003a1e: 3303 adds r3, #3 8003a20: 68fa ldr r2, [r7, #12] 8003a22: 4413 add r3, r2 8003a24: 781b ldrb r3, [r3, #0] 8003a26: 061a lsls r2, r3, #24 8003a28: 68bb ldr r3, [r7, #8] 8003a2a: 881b ldrh r3, [r3, #0] 8003a2c: 3302 adds r3, #2 8003a2e: 68f9 ldr r1, [r7, #12] 8003a30: 440b add r3, r1 8003a32: 781b ldrb r3, [r3, #0] 8003a34: 041b lsls r3, r3, #16 8003a36: 431a orrs r2, r3 8003a38: 68bb ldr r3, [r7, #8] 8003a3a: 881b ldrh r3, [r3, #0] 8003a3c: 3301 adds r3, #1 8003a3e: 68f9 ldr r1, [r7, #12] 8003a40: 440b add r3, r1 8003a42: 781b ldrb r3, [r3, #0] 8003a44: 021b lsls r3, r3, #8 8003a46: 4313 orrs r3, r2 8003a48: 68ba ldr r2, [r7, #8] 8003a4a: 8812 ldrh r2, [r2, #0] 8003a4c: 4611 mov r1, r2 8003a4e: 68fa ldr r2, [r7, #12] 8003a50: 440a add r2, r1 8003a52: 7812 ldrb r2, [r2, #0] 8003a54: 4313 orrs r3, r2 8003a56: 461a mov r2, r3 8003a58: 697b ldr r3, [r7, #20] 8003a5a: 601a str r2, [r3, #0] *buffPos += sizeof(float); 8003a5c: 68bb ldr r3, [r7, #8] 8003a5e: 881b ldrh r3, [r3, #0] 8003a60: 3304 adds r3, #4 8003a62: b29a uxth r2, r3 8003a64: 68bb ldr r3, [r7, #8] 8003a66: 801a strh r2, [r3, #0] } 8003a68: bf00 nop 8003a6a: 371c adds r7, #28 8003a6c: 46bd mov sp, r7 8003a6e: f85d 7b04 ldr.w r7, [sp], #4 8003a72: 4770 bx lr 08003a74 : *data = CONVERT_BYTES_TO_SHORT_WORD(&buff[*buffPos]); *buffPos += sizeof(uint16_t); } void ReadWordFromBufer(uint8_t* buff, uint16_t* buffPos, uint32_t* data) { 8003a74: b480 push {r7} 8003a76: b085 sub sp, #20 8003a78: af00 add r7, sp, #0 8003a7a: 60f8 str r0, [r7, #12] 8003a7c: 60b9 str r1, [r7, #8] 8003a7e: 607a str r2, [r7, #4] *data = CONVERT_BYTES_TO_WORD(&buff[*buffPos]); 8003a80: 68bb ldr r3, [r7, #8] 8003a82: 881b ldrh r3, [r3, #0] 8003a84: 3303 adds r3, #3 8003a86: 68fa ldr r2, [r7, #12] 8003a88: 4413 add r3, r2 8003a8a: 781b ldrb r3, [r3, #0] 8003a8c: 061a lsls r2, r3, #24 8003a8e: 68bb ldr r3, [r7, #8] 8003a90: 881b ldrh r3, [r3, #0] 8003a92: 3302 adds r3, #2 8003a94: 68f9 ldr r1, [r7, #12] 8003a96: 440b add r3, r1 8003a98: 781b ldrb r3, [r3, #0] 8003a9a: 041b lsls r3, r3, #16 8003a9c: 431a orrs r2, r3 8003a9e: 68bb ldr r3, [r7, #8] 8003aa0: 881b ldrh r3, [r3, #0] 8003aa2: 3301 adds r3, #1 8003aa4: 68f9 ldr r1, [r7, #12] 8003aa6: 440b add r3, r1 8003aa8: 781b ldrb r3, [r3, #0] 8003aaa: 021b lsls r3, r3, #8 8003aac: 4313 orrs r3, r2 8003aae: 68ba ldr r2, [r7, #8] 8003ab0: 8812 ldrh r2, [r2, #0] 8003ab2: 4611 mov r1, r2 8003ab4: 68fa ldr r2, [r7, #12] 8003ab6: 440a add r2, r1 8003ab8: 7812 ldrb r2, [r2, #0] 8003aba: 4313 orrs r3, r2 8003abc: 461a mov r2, r3 8003abe: 687b ldr r3, [r7, #4] 8003ac0: 601a str r2, [r3, #0] *buffPos += sizeof(uint32_t); 8003ac2: 68bb ldr r3, [r7, #8] 8003ac4: 881b ldrh r3, [r3, #0] 8003ac6: 3304 adds r3, #4 8003ac8: b29a uxth r2, r3 8003aca: 68bb ldr r3, [r7, #8] 8003acc: 801a strh r2, [r3, #0] } 8003ace: bf00 nop 8003ad0: 3714 adds r7, #20 8003ad2: 46bd mov sp, r7 8003ad4: f85d 7b04 ldr.w r7, [sp], #4 8003ad8: 4770 bx lr ... 08003adc : txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); return txBufferPos; } uint16_t PrepareRespFrame (uint8_t* txBuffer, uint16_t frameId, SerialProtocolCommands frameCommand, SerialProtocolRespStatus respStatus, uint8_t* dataBuffer, uint16_t dataLength) { 8003adc: b580 push {r7, lr} 8003ade: b084 sub sp, #16 8003ae0: af00 add r7, sp, #0 8003ae2: 6078 str r0, [r7, #4] 8003ae4: 4608 mov r0, r1 8003ae6: 4611 mov r1, r2 8003ae8: 461a mov r2, r3 8003aea: 4603 mov r3, r0 8003aec: 807b strh r3, [r7, #2] 8003aee: 460b mov r3, r1 8003af0: 707b strb r3, [r7, #1] 8003af2: 4613 mov r3, r2 8003af4: 703b strb r3, [r7, #0] uint16_t crc = 0; 8003af6: 2300 movs r3, #0 8003af8: 81bb strh r3, [r7, #12] uint16_t txBufferPos = 0; 8003afa: 2300 movs r3, #0 8003afc: 81fb strh r3, [r7, #14] uint16_t frameCmd = ((uint16_t)frameCommand) | 0x8000; // MSB set means response 8003afe: 787b ldrb r3, [r7, #1] 8003b00: b21a sxth r2, r3 8003b02: 4b43 ldr r3, [pc, #268] @ (8003c10 ) 8003b04: 4313 orrs r3, r2 8003b06: b21b sxth r3, r3 8003b08: 817b strh r3, [r7, #10] memset (txBuffer, 0x00, dataLength); 8003b0a: 8bbb ldrh r3, [r7, #28] 8003b0c: 461a mov r2, r3 8003b0e: 2100 movs r1, #0 8003b10: 6878 ldr r0, [r7, #4] 8003b12: f014 fc01 bl 8018318 txBuffer[txBufferPos++] = FRAME_INDICATOR; 8003b16: 89fb ldrh r3, [r7, #14] 8003b18: 1c5a adds r2, r3, #1 8003b1a: 81fa strh r2, [r7, #14] 8003b1c: 461a mov r2, r3 8003b1e: 687b ldr r3, [r7, #4] 8003b20: 4413 add r3, r2 8003b22: 22aa movs r2, #170 @ 0xaa 8003b24: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameId); 8003b26: 89fb ldrh r3, [r7, #14] 8003b28: 1c5a adds r2, r3, #1 8003b2a: 81fa strh r2, [r7, #14] 8003b2c: 461a mov r2, r3 8003b2e: 687b ldr r3, [r7, #4] 8003b30: 4413 add r3, r2 8003b32: 887a ldrh r2, [r7, #2] 8003b34: b2d2 uxtb r2, r2 8003b36: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameId); 8003b38: 887b ldrh r3, [r7, #2] 8003b3a: 0a1b lsrs r3, r3, #8 8003b3c: b29a uxth r2, r3 8003b3e: 89fb ldrh r3, [r7, #14] 8003b40: 1c59 adds r1, r3, #1 8003b42: 81f9 strh r1, [r7, #14] 8003b44: 4619 mov r1, r3 8003b46: 687b ldr r3, [r7, #4] 8003b48: 440b add r3, r1 8003b4a: b2d2 uxtb r2, r2 8003b4c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (frameCmd); 8003b4e: 89fb ldrh r3, [r7, #14] 8003b50: 1c5a adds r2, r3, #1 8003b52: 81fa strh r2, [r7, #14] 8003b54: 461a mov r2, r3 8003b56: 687b ldr r3, [r7, #4] 8003b58: 4413 add r3, r2 8003b5a: 897a ldrh r2, [r7, #10] 8003b5c: b2d2 uxtb r2, r2 8003b5e: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (frameCmd); 8003b60: 897b ldrh r3, [r7, #10] 8003b62: 0a1b lsrs r3, r3, #8 8003b64: b29a uxth r2, r3 8003b66: 89fb ldrh r3, [r7, #14] 8003b68: 1c59 adds r1, r3, #1 8003b6a: 81f9 strh r1, [r7, #14] 8003b6c: 4619 mov r1, r3 8003b6e: 687b ldr r3, [r7, #4] 8003b70: 440b add r3, r1 8003b72: b2d2 uxtb r2, r2 8003b74: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (dataLength); 8003b76: 89fb ldrh r3, [r7, #14] 8003b78: 1c5a adds r2, r3, #1 8003b7a: 81fa strh r2, [r7, #14] 8003b7c: 461a mov r2, r3 8003b7e: 687b ldr r3, [r7, #4] 8003b80: 4413 add r3, r2 8003b82: 8bba ldrh r2, [r7, #28] 8003b84: b2d2 uxtb r2, r2 8003b86: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (dataLength); 8003b88: 8bbb ldrh r3, [r7, #28] 8003b8a: 0a1b lsrs r3, r3, #8 8003b8c: b29a uxth r2, r3 8003b8e: 89fb ldrh r3, [r7, #14] 8003b90: 1c59 adds r1, r3, #1 8003b92: 81f9 strh r1, [r7, #14] 8003b94: 4619 mov r1, r3 8003b96: 687b ldr r3, [r7, #4] 8003b98: 440b add r3, r1 8003b9a: b2d2 uxtb r2, r2 8003b9c: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = (uint8_t)respStatus; 8003b9e: 89fb ldrh r3, [r7, #14] 8003ba0: 1c5a adds r2, r3, #1 8003ba2: 81fa strh r2, [r7, #14] 8003ba4: 461a mov r2, r3 8003ba6: 687b ldr r3, [r7, #4] 8003ba8: 4413 add r3, r2 8003baa: 783a ldrb r2, [r7, #0] 8003bac: 701a strb r2, [r3, #0] if (dataLength > 0) { 8003bae: 8bbb ldrh r3, [r7, #28] 8003bb0: 2b00 cmp r3, #0 8003bb2: d00b beq.n 8003bcc memcpy (&txBuffer[txBufferPos], dataBuffer, dataLength); 8003bb4: 89fb ldrh r3, [r7, #14] 8003bb6: 687a ldr r2, [r7, #4] 8003bb8: 4413 add r3, r2 8003bba: 8bba ldrh r2, [r7, #28] 8003bbc: 69b9 ldr r1, [r7, #24] 8003bbe: 4618 mov r0, r3 8003bc0: f014 fc34 bl 801842c txBufferPos += dataLength; 8003bc4: 89fa ldrh r2, [r7, #14] 8003bc6: 8bbb ldrh r3, [r7, #28] 8003bc8: 4413 add r3, r2 8003bca: 81fb strh r3, [r7, #14] } crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)txBuffer, txBufferPos); 8003bcc: 89fb ldrh r3, [r7, #14] 8003bce: 461a mov r2, r3 8003bd0: 6879 ldr r1, [r7, #4] 8003bd2: 4810 ldr r0, [pc, #64] @ (8003c14 ) 8003bd4: f004 f8d0 bl 8007d78 8003bd8: 4603 mov r3, r0 8003bda: 81bb strh r3, [r7, #12] txBuffer[txBufferPos++] = GET_SHORT_WORD_FIRST_BYTE (crc); 8003bdc: 89fb ldrh r3, [r7, #14] 8003bde: 1c5a adds r2, r3, #1 8003be0: 81fa strh r2, [r7, #14] 8003be2: 461a mov r2, r3 8003be4: 687b ldr r3, [r7, #4] 8003be6: 4413 add r3, r2 8003be8: 89ba ldrh r2, [r7, #12] 8003bea: b2d2 uxtb r2, r2 8003bec: 701a strb r2, [r3, #0] txBuffer[txBufferPos++] = GET_SHORT_WORD_SECOND_BYTE (crc); 8003bee: 89bb ldrh r3, [r7, #12] 8003bf0: 0a1b lsrs r3, r3, #8 8003bf2: b29a uxth r2, r3 8003bf4: 89fb ldrh r3, [r7, #14] 8003bf6: 1c59 adds r1, r3, #1 8003bf8: 81f9 strh r1, [r7, #14] 8003bfa: 4619 mov r1, r3 8003bfc: 687b ldr r3, [r7, #4] 8003bfe: 440b add r3, r1 8003c00: b2d2 uxtb r2, r2 8003c02: 701a strb r2, [r3, #0] return txBufferPos; 8003c04: 89fb ldrh r3, [r7, #14] } 8003c06: 4618 mov r0, r3 8003c08: 3710 adds r7, #16 8003c0a: 46bd mov sp, r7 8003c0c: bd80 pop {r7, pc} 8003c0e: bf00 nop 8003c10: ffff8000 .word 0xffff8000 8003c14: 240003e0 .word 0x240003e0 08003c18 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8003c18: b580 push {r7, lr} 8003c1a: b086 sub sp, #24 8003c1c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ PWREx_AVDTypeDef sConfigAVD = {0}; 8003c1e: f107 0310 add.w r3, r7, #16 8003c22: 2200 movs r2, #0 8003c24: 601a str r2, [r3, #0] 8003c26: 605a str r2, [r3, #4] PWR_PVDTypeDef sConfigPVD = {0}; 8003c28: f107 0308 add.w r3, r7, #8 8003c2c: 2200 movs r2, #0 8003c2e: 601a str r2, [r3, #0] 8003c30: 605a str r2, [r3, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); 8003c32: 4b26 ldr r3, [pc, #152] @ (8003ccc ) 8003c34: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c38: 4a24 ldr r2, [pc, #144] @ (8003ccc ) 8003c3a: f043 0302 orr.w r3, r3, #2 8003c3e: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003c42: 4b22 ldr r3, [pc, #136] @ (8003ccc ) 8003c44: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003c48: f003 0302 and.w r3, r3, #2 8003c4c: 607b str r3, [r7, #4] 8003c4e: 687b ldr r3, [r7, #4] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8003c50: 2200 movs r2, #0 8003c52: 210f movs r1, #15 8003c54: f06f 0001 mvn.w r0, #1 8003c58: f003 ff8a bl 8007b70 /* Peripheral interrupt init */ /* RCC_IRQn interrupt configuration */ HAL_NVIC_SetPriority(RCC_IRQn, 5, 0); 8003c5c: 2200 movs r2, #0 8003c5e: 2105 movs r1, #5 8003c60: 2005 movs r0, #5 8003c62: f003 ff85 bl 8007b70 HAL_NVIC_EnableIRQ(RCC_IRQn); 8003c66: 2005 movs r0, #5 8003c68: f003 ff9c bl 8007ba4 /** AVD Configuration */ sConfigAVD.AVDLevel = PWR_AVDLEVEL_3; 8003c6c: f44f 23c0 mov.w r3, #393216 @ 0x60000 8003c70: 613b str r3, [r7, #16] sConfigAVD.Mode = PWR_AVD_MODE_NORMAL; 8003c72: 2300 movs r3, #0 8003c74: 617b str r3, [r7, #20] HAL_PWREx_ConfigAVD(&sConfigAVD); 8003c76: f107 0310 add.w r3, r7, #16 8003c7a: 4618 mov r0, r3 8003c7c: f007 fde2 bl 800b844 /** Enable the AVD Output */ HAL_PWREx_EnableAVD(); 8003c80: f007 fe56 bl 800b930 /** PVD Configuration */ sConfigPVD.PVDLevel = PWR_PVDLEVEL_6; 8003c84: 23c0 movs r3, #192 @ 0xc0 8003c86: 60bb str r3, [r7, #8] sConfigPVD.Mode = PWR_PVD_MODE_NORMAL; 8003c88: 2300 movs r3, #0 8003c8a: 60fb str r3, [r7, #12] HAL_PWR_ConfigPVD(&sConfigPVD); 8003c8c: f107 0308 add.w r3, r7, #8 8003c90: 4618 mov r0, r3 8003c92: f007 fd13 bl 800b6bc /** Enable the PVD Output */ HAL_PWR_EnablePVD(); 8003c96: f007 fd8b bl 800b7b0 /** Enable the VREF clock */ __HAL_RCC_VREF_CLK_ENABLE(); 8003c9a: 4b0c ldr r3, [pc, #48] @ (8003ccc ) 8003c9c: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003ca0: 4a0a ldr r2, [pc, #40] @ (8003ccc ) 8003ca2: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8003ca6: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 8003caa: 4b08 ldr r3, [pc, #32] @ (8003ccc ) 8003cac: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 8003cb0: f403 4300 and.w r3, r3, #32768 @ 0x8000 8003cb4: 603b str r3, [r7, #0] 8003cb6: 683b ldr r3, [r7, #0] /** Disable the Internal Voltage Reference buffer */ HAL_SYSCFG_DisableVREFBUF(); 8003cb8: f002 f8e0 bl 8005e7c /** Configure the internal voltage reference buffer high impedance mode */ HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE); 8003cbc: 2002 movs r0, #2 8003cbe: f002 f8c9 bl 8005e54 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8003cc2: bf00 nop 8003cc4: 3718 adds r7, #24 8003cc6: 46bd mov sp, r7 8003cc8: bd80 pop {r7, pc} 8003cca: bf00 nop 8003ccc: 58024400 .word 0x58024400 08003cd0 : * This function configures the hardware resources used in this example * @param hadc: ADC handle pointer * @retval None */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { 8003cd0: b580 push {r7, lr} 8003cd2: b092 sub sp, #72 @ 0x48 8003cd4: af00 add r7, sp, #0 8003cd6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003cd8: f107 0334 add.w r3, r7, #52 @ 0x34 8003cdc: 2200 movs r2, #0 8003cde: 601a str r2, [r3, #0] 8003ce0: 605a str r2, [r3, #4] 8003ce2: 609a str r2, [r3, #8] 8003ce4: 60da str r2, [r3, #12] 8003ce6: 611a str r2, [r3, #16] if(hadc->Instance==ADC1) 8003ce8: 687b ldr r3, [r7, #4] 8003cea: 681b ldr r3, [r3, #0] 8003cec: 4a9d ldr r2, [pc, #628] @ (8003f64 ) 8003cee: 4293 cmp r3, r2 8003cf0: f040 8099 bne.w 8003e26 { /* USER CODE BEGIN ADC1_MspInit 0 */ /* USER CODE END ADC1_MspInit 0 */ /* Peripheral clock enable */ HAL_RCC_ADC12_CLK_ENABLED++; 8003cf4: 4b9c ldr r3, [pc, #624] @ (8003f68 ) 8003cf6: 681b ldr r3, [r3, #0] 8003cf8: 3301 adds r3, #1 8003cfa: 4a9b ldr r2, [pc, #620] @ (8003f68 ) 8003cfc: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003cfe: 4b9a ldr r3, [pc, #616] @ (8003f68 ) 8003d00: 681b ldr r3, [r3, #0] 8003d02: 2b01 cmp r3, #1 8003d04: d10e bne.n 8003d24 __HAL_RCC_ADC12_CLK_ENABLE(); 8003d06: 4b99 ldr r3, [pc, #612] @ (8003f6c ) 8003d08: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003d0c: 4a97 ldr r2, [pc, #604] @ (8003f6c ) 8003d0e: f043 0320 orr.w r3, r3, #32 8003d12: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003d16: 4b95 ldr r3, [pc, #596] @ (8003f6c ) 8003d18: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003d1c: f003 0320 and.w r3, r3, #32 8003d20: 633b str r3, [r7, #48] @ 0x30 8003d22: 6b3b ldr r3, [r7, #48] @ 0x30 } __HAL_RCC_GPIOA_CLK_ENABLE(); 8003d24: 4b91 ldr r3, [pc, #580] @ (8003f6c ) 8003d26: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d2a: 4a90 ldr r2, [pc, #576] @ (8003f6c ) 8003d2c: f043 0301 orr.w r3, r3, #1 8003d30: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d34: 4b8d ldr r3, [pc, #564] @ (8003f6c ) 8003d36: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d3a: f003 0301 and.w r3, r3, #1 8003d3e: 62fb str r3, [r7, #44] @ 0x2c 8003d40: 6afb ldr r3, [r7, #44] @ 0x2c __HAL_RCC_GPIOC_CLK_ENABLE(); 8003d42: 4b8a ldr r3, [pc, #552] @ (8003f6c ) 8003d44: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d48: 4a88 ldr r2, [pc, #544] @ (8003f6c ) 8003d4a: f043 0304 orr.w r3, r3, #4 8003d4e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d52: 4b86 ldr r3, [pc, #536] @ (8003f6c ) 8003d54: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d58: f003 0304 and.w r3, r3, #4 8003d5c: 62bb str r3, [r7, #40] @ 0x28 8003d5e: 6abb ldr r3, [r7, #40] @ 0x28 __HAL_RCC_GPIOB_CLK_ENABLE(); 8003d60: 4b82 ldr r3, [pc, #520] @ (8003f6c ) 8003d62: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d66: 4a81 ldr r2, [pc, #516] @ (8003f6c ) 8003d68: f043 0302 orr.w r3, r3, #2 8003d6c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003d70: 4b7e ldr r3, [pc, #504] @ (8003f6c ) 8003d72: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003d76: f003 0302 and.w r3, r3, #2 8003d7a: 627b str r3, [r7, #36] @ 0x24 8003d7c: 6a7b ldr r3, [r7, #36] @ 0x24 PA3 ------> ADC1_INP15 PA7 ------> ADC1_INP7 PC5 ------> ADC1_INP8 PB0 ------> ADC1_INP9 */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 8003d7e: 238f movs r3, #143 @ 0x8f 8003d80: 637b str r3, [r7, #52] @ 0x34 |GPIO_PIN_7; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003d82: 2303 movs r3, #3 8003d84: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d86: 2300 movs r3, #0 8003d88: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003d8a: f107 0334 add.w r3, r7, #52 @ 0x34 8003d8e: 4619 mov r1, r3 8003d90: 4877 ldr r0, [pc, #476] @ (8003f70 ) 8003d92: f007 fa1f bl 800b1d4 GPIO_InitStruct.Pin = GPIO_PIN_5; 8003d96: 2320 movs r3, #32 8003d98: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003d9a: 2303 movs r3, #3 8003d9c: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d9e: 2300 movs r3, #0 8003da0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003da2: f107 0334 add.w r3, r7, #52 @ 0x34 8003da6: 4619 mov r1, r3 8003da8: 4872 ldr r0, [pc, #456] @ (8003f74 ) 8003daa: f007 fa13 bl 800b1d4 GPIO_InitStruct.Pin = GPIO_PIN_0; 8003dae: 2301 movs r3, #1 8003db0: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003db2: 2303 movs r3, #3 8003db4: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003db6: 2300 movs r3, #0 8003db8: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003dba: f107 0334 add.w r3, r7, #52 @ 0x34 8003dbe: 4619 mov r1, r3 8003dc0: 486d ldr r0, [pc, #436] @ (8003f78 ) 8003dc2: f007 fa07 bl 800b1d4 /* ADC1 DMA Init */ /* ADC1 Init */ hdma_adc1.Instance = DMA1_Stream0; 8003dc6: 4b6d ldr r3, [pc, #436] @ (8003f7c ) 8003dc8: 4a6d ldr r2, [pc, #436] @ (8003f80 ) 8003dca: 601a str r2, [r3, #0] hdma_adc1.Init.Request = DMA_REQUEST_ADC1; 8003dcc: 4b6b ldr r3, [pc, #428] @ (8003f7c ) 8003dce: 2209 movs r2, #9 8003dd0: 605a str r2, [r3, #4] hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003dd2: 4b6a ldr r3, [pc, #424] @ (8003f7c ) 8003dd4: 2200 movs r2, #0 8003dd6: 609a str r2, [r3, #8] hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; 8003dd8: 4b68 ldr r3, [pc, #416] @ (8003f7c ) 8003dda: 2200 movs r2, #0 8003ddc: 60da str r2, [r3, #12] hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; 8003dde: 4b67 ldr r3, [pc, #412] @ (8003f7c ) 8003de0: f44f 6280 mov.w r2, #1024 @ 0x400 8003de4: 611a str r2, [r3, #16] hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003de6: 4b65 ldr r3, [pc, #404] @ (8003f7c ) 8003de8: f44f 6200 mov.w r2, #2048 @ 0x800 8003dec: 615a str r2, [r3, #20] hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003dee: 4b63 ldr r3, [pc, #396] @ (8003f7c ) 8003df0: f44f 5200 mov.w r2, #8192 @ 0x2000 8003df4: 619a str r2, [r3, #24] hdma_adc1.Init.Mode = DMA_NORMAL; 8003df6: 4b61 ldr r3, [pc, #388] @ (8003f7c ) 8003df8: 2200 movs r2, #0 8003dfa: 61da str r2, [r3, #28] hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; 8003dfc: 4b5f ldr r3, [pc, #380] @ (8003f7c ) 8003dfe: 2200 movs r2, #0 8003e00: 621a str r2, [r3, #32] hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003e02: 4b5e ldr r3, [pc, #376] @ (8003f7c ) 8003e04: 2200 movs r2, #0 8003e06: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) 8003e08: 485c ldr r0, [pc, #368] @ (8003f7c ) 8003e0a: f004 fba7 bl 800855c 8003e0e: 4603 mov r3, r0 8003e10: 2b00 cmp r3, #0 8003e12: d001 beq.n 8003e18 { Error_Handler(); 8003e14: f7fe f85a bl 8001ecc } __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc1); 8003e18: 687b ldr r3, [r7, #4] 8003e1a: 4a58 ldr r2, [pc, #352] @ (8003f7c ) 8003e1c: 64da str r2, [r3, #76] @ 0x4c 8003e1e: 4a57 ldr r2, [pc, #348] @ (8003f7c ) 8003e20: 687b ldr r3, [r7, #4] 8003e22: 6393 str r3, [r2, #56] @ 0x38 /* USER CODE BEGIN ADC3_MspInit 1 */ /* USER CODE END ADC3_MspInit 1 */ } } 8003e24: e11e b.n 8004064 else if(hadc->Instance==ADC2) 8003e26: 687b ldr r3, [r7, #4] 8003e28: 681b ldr r3, [r3, #0] 8003e2a: 4a56 ldr r2, [pc, #344] @ (8003f84 ) 8003e2c: 4293 cmp r3, r2 8003e2e: f040 80af bne.w 8003f90 HAL_RCC_ADC12_CLK_ENABLED++; 8003e32: 4b4d ldr r3, [pc, #308] @ (8003f68 ) 8003e34: 681b ldr r3, [r3, #0] 8003e36: 3301 adds r3, #1 8003e38: 4a4b ldr r2, [pc, #300] @ (8003f68 ) 8003e3a: 6013 str r3, [r2, #0] if(HAL_RCC_ADC12_CLK_ENABLED==1){ 8003e3c: 4b4a ldr r3, [pc, #296] @ (8003f68 ) 8003e3e: 681b ldr r3, [r3, #0] 8003e40: 2b01 cmp r3, #1 8003e42: d10e bne.n 8003e62 __HAL_RCC_ADC12_CLK_ENABLE(); 8003e44: 4b49 ldr r3, [pc, #292] @ (8003f6c ) 8003e46: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003e4a: 4a48 ldr r2, [pc, #288] @ (8003f6c ) 8003e4c: f043 0320 orr.w r3, r3, #32 8003e50: f8c2 30d8 str.w r3, [r2, #216] @ 0xd8 8003e54: 4b45 ldr r3, [pc, #276] @ (8003f6c ) 8003e56: f8d3 30d8 ldr.w r3, [r3, #216] @ 0xd8 8003e5a: f003 0320 and.w r3, r3, #32 8003e5e: 623b str r3, [r7, #32] 8003e60: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003e62: 4b42 ldr r3, [pc, #264] @ (8003f6c ) 8003e64: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e68: 4a40 ldr r2, [pc, #256] @ (8003f6c ) 8003e6a: f043 0301 orr.w r3, r3, #1 8003e6e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e72: 4b3e ldr r3, [pc, #248] @ (8003f6c ) 8003e74: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e78: f003 0301 and.w r3, r3, #1 8003e7c: 61fb str r3, [r7, #28] 8003e7e: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003e80: 4b3a ldr r3, [pc, #232] @ (8003f6c ) 8003e82: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e86: 4a39 ldr r2, [pc, #228] @ (8003f6c ) 8003e88: f043 0304 orr.w r3, r3, #4 8003e8c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003e90: 4b36 ldr r3, [pc, #216] @ (8003f6c ) 8003e92: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003e96: f003 0304 and.w r3, r3, #4 8003e9a: 61bb str r3, [r7, #24] 8003e9c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003e9e: 4b33 ldr r3, [pc, #204] @ (8003f6c ) 8003ea0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003ea4: 4a31 ldr r2, [pc, #196] @ (8003f6c ) 8003ea6: f043 0302 orr.w r3, r3, #2 8003eaa: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003eae: 4b2f ldr r3, [pc, #188] @ (8003f6c ) 8003eb0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003eb4: f003 0302 and.w r3, r3, #2 8003eb8: 617b str r3, [r7, #20] 8003eba: 697b ldr r3, [r7, #20] GPIO_InitStruct.Pin = GPIO_PIN_6; 8003ebc: 2340 movs r3, #64 @ 0x40 8003ebe: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003ec0: 2303 movs r3, #3 8003ec2: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003ec4: 2300 movs r3, #0 8003ec6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003ec8: f107 0334 add.w r3, r7, #52 @ 0x34 8003ecc: 4619 mov r1, r3 8003ece: 4828 ldr r0, [pc, #160] @ (8003f70 ) 8003ed0: f007 f980 bl 800b1d4 GPIO_InitStruct.Pin = GPIO_PIN_4; 8003ed4: 2310 movs r3, #16 8003ed6: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003ed8: 2303 movs r3, #3 8003eda: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003edc: 2300 movs r3, #0 8003ede: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003ee0: f107 0334 add.w r3, r7, #52 @ 0x34 8003ee4: 4619 mov r1, r3 8003ee6: 4823 ldr r0, [pc, #140] @ (8003f74 ) 8003ee8: f007 f974 bl 800b1d4 GPIO_InitStruct.Pin = GPIO_PIN_1; 8003eec: 2302 movs r3, #2 8003eee: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003ef0: 2303 movs r3, #3 8003ef2: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003ef4: 2300 movs r3, #0 8003ef6: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003ef8: f107 0334 add.w r3, r7, #52 @ 0x34 8003efc: 4619 mov r1, r3 8003efe: 481e ldr r0, [pc, #120] @ (8003f78 ) 8003f00: f007 f968 bl 800b1d4 hdma_adc2.Instance = DMA1_Stream1; 8003f04: 4b20 ldr r3, [pc, #128] @ (8003f88 ) 8003f06: 4a21 ldr r2, [pc, #132] @ (8003f8c ) 8003f08: 601a str r2, [r3, #0] hdma_adc2.Init.Request = DMA_REQUEST_ADC2; 8003f0a: 4b1f ldr r3, [pc, #124] @ (8003f88 ) 8003f0c: 220a movs r2, #10 8003f0e: 605a str r2, [r3, #4] hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003f10: 4b1d ldr r3, [pc, #116] @ (8003f88 ) 8003f12: 2200 movs r2, #0 8003f14: 609a str r2, [r3, #8] hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; 8003f16: 4b1c ldr r3, [pc, #112] @ (8003f88 ) 8003f18: 2200 movs r2, #0 8003f1a: 60da str r2, [r3, #12] hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; 8003f1c: 4b1a ldr r3, [pc, #104] @ (8003f88 ) 8003f1e: f44f 6280 mov.w r2, #1024 @ 0x400 8003f22: 611a str r2, [r3, #16] hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8003f24: 4b18 ldr r3, [pc, #96] @ (8003f88 ) 8003f26: f44f 6200 mov.w r2, #2048 @ 0x800 8003f2a: 615a str r2, [r3, #20] hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 8003f2c: 4b16 ldr r3, [pc, #88] @ (8003f88 ) 8003f2e: f44f 5200 mov.w r2, #8192 @ 0x2000 8003f32: 619a str r2, [r3, #24] hdma_adc2.Init.Mode = DMA_NORMAL; 8003f34: 4b14 ldr r3, [pc, #80] @ (8003f88 ) 8003f36: 2200 movs r2, #0 8003f38: 61da str r2, [r3, #28] hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; 8003f3a: 4b13 ldr r3, [pc, #76] @ (8003f88 ) 8003f3c: 2200 movs r2, #0 8003f3e: 621a str r2, [r3, #32] hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8003f40: 4b11 ldr r3, [pc, #68] @ (8003f88 ) 8003f42: 2200 movs r2, #0 8003f44: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) 8003f46: 4810 ldr r0, [pc, #64] @ (8003f88 ) 8003f48: f004 fb08 bl 800855c 8003f4c: 4603 mov r3, r0 8003f4e: 2b00 cmp r3, #0 8003f50: d001 beq.n 8003f56 Error_Handler(); 8003f52: f7fd ffbb bl 8001ecc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc2); 8003f56: 687b ldr r3, [r7, #4] 8003f58: 4a0b ldr r2, [pc, #44] @ (8003f88 ) 8003f5a: 64da str r2, [r3, #76] @ 0x4c 8003f5c: 4a0a ldr r2, [pc, #40] @ (8003f88 ) 8003f5e: 687b ldr r3, [r7, #4] 8003f60: 6393 str r3, [r2, #56] @ 0x38 } 8003f62: e07f b.n 8004064 8003f64: 40022000 .word 0x40022000 8003f68: 2400091c .word 0x2400091c 8003f6c: 58024400 .word 0x58024400 8003f70: 58020000 .word 0x58020000 8003f74: 58020800 .word 0x58020800 8003f78: 58020400 .word 0x58020400 8003f7c: 2400024c .word 0x2400024c 8003f80: 40020010 .word 0x40020010 8003f84: 40022100 .word 0x40022100 8003f88: 240002c4 .word 0x240002c4 8003f8c: 40020028 .word 0x40020028 else if(hadc->Instance==ADC3) 8003f90: 687b ldr r3, [r7, #4] 8003f92: 681b ldr r3, [r3, #0] 8003f94: 4a35 ldr r2, [pc, #212] @ (800406c ) 8003f96: 4293 cmp r3, r2 8003f98: d164 bne.n 8004064 __HAL_RCC_ADC3_CLK_ENABLE(); 8003f9a: 4b35 ldr r3, [pc, #212] @ (8004070 ) 8003f9c: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fa0: 4a33 ldr r2, [pc, #204] @ (8004070 ) 8003fa2: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8003fa6: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003faa: 4b31 ldr r3, [pc, #196] @ (8004070 ) 8003fac: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fb0: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8003fb4: 613b str r3, [r7, #16] 8003fb6: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003fb8: 4b2d ldr r3, [pc, #180] @ (8004070 ) 8003fba: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fbe: 4a2c ldr r2, [pc, #176] @ (8004070 ) 8003fc0: f043 0304 orr.w r3, r3, #4 8003fc4: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8003fc8: 4b29 ldr r3, [pc, #164] @ (8004070 ) 8003fca: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8003fce: f003 0304 and.w r3, r3, #4 8003fd2: 60fb str r3, [r7, #12] 8003fd4: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8003fd6: 2303 movs r3, #3 8003fd8: 637b str r3, [r7, #52] @ 0x34 GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 8003fda: 2303 movs r3, #3 8003fdc: 63bb str r3, [r7, #56] @ 0x38 GPIO_InitStruct.Pull = GPIO_NOPULL; 8003fde: 2300 movs r3, #0 8003fe0: 63fb str r3, [r7, #60] @ 0x3c HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003fe2: f107 0334 add.w r3, r7, #52 @ 0x34 8003fe6: 4619 mov r1, r3 8003fe8: 4822 ldr r0, [pc, #136] @ (8004074 ) 8003fea: f007 f8f3 bl 800b1d4 HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); 8003fee: f04f 6180 mov.w r1, #67108864 @ 0x4000000 8003ff2: f04f 6080 mov.w r0, #67108864 @ 0x4000000 8003ff6: f001 ff51 bl 8005e9c HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); 8003ffa: f04f 6100 mov.w r1, #134217728 @ 0x8000000 8003ffe: f04f 6000 mov.w r0, #134217728 @ 0x8000000 8004002: f001 ff4b bl 8005e9c hdma_adc3.Instance = DMA1_Stream2; 8004006: 4b1c ldr r3, [pc, #112] @ (8004078 ) 8004008: 4a1c ldr r2, [pc, #112] @ (800407c ) 800400a: 601a str r2, [r3, #0] hdma_adc3.Init.Request = DMA_REQUEST_ADC3; 800400c: 4b1a ldr r3, [pc, #104] @ (8004078 ) 800400e: 2273 movs r2, #115 @ 0x73 8004010: 605a str r2, [r3, #4] hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY; 8004012: 4b19 ldr r3, [pc, #100] @ (8004078 ) 8004014: 2200 movs r2, #0 8004016: 609a str r2, [r3, #8] hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE; 8004018: 4b17 ldr r3, [pc, #92] @ (8004078 ) 800401a: 2200 movs r2, #0 800401c: 60da str r2, [r3, #12] hdma_adc3.Init.MemInc = DMA_MINC_ENABLE; 800401e: 4b16 ldr r3, [pc, #88] @ (8004078 ) 8004020: f44f 6280 mov.w r2, #1024 @ 0x400 8004024: 611a str r2, [r3, #16] hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 8004026: 4b14 ldr r3, [pc, #80] @ (8004078 ) 8004028: f44f 6200 mov.w r2, #2048 @ 0x800 800402c: 615a str r2, [r3, #20] hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 800402e: 4b12 ldr r3, [pc, #72] @ (8004078 ) 8004030: f44f 5200 mov.w r2, #8192 @ 0x2000 8004034: 619a str r2, [r3, #24] hdma_adc3.Init.Mode = DMA_NORMAL; 8004036: 4b10 ldr r3, [pc, #64] @ (8004078 ) 8004038: 2200 movs r2, #0 800403a: 61da str r2, [r3, #28] hdma_adc3.Init.Priority = DMA_PRIORITY_LOW; 800403c: 4b0e ldr r3, [pc, #56] @ (8004078 ) 800403e: 2200 movs r2, #0 8004040: 621a str r2, [r3, #32] hdma_adc3.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 8004042: 4b0d ldr r3, [pc, #52] @ (8004078 ) 8004044: 2200 movs r2, #0 8004046: 625a str r2, [r3, #36] @ 0x24 if (HAL_DMA_Init(&hdma_adc3) != HAL_OK) 8004048: 480b ldr r0, [pc, #44] @ (8004078 ) 800404a: f004 fa87 bl 800855c 800404e: 4603 mov r3, r0 8004050: 2b00 cmp r3, #0 8004052: d001 beq.n 8004058 Error_Handler(); 8004054: f7fd ff3a bl 8001ecc __HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3); 8004058: 687b ldr r3, [r7, #4] 800405a: 4a07 ldr r2, [pc, #28] @ (8004078 ) 800405c: 64da str r2, [r3, #76] @ 0x4c 800405e: 4a06 ldr r2, [pc, #24] @ (8004078 ) 8004060: 687b ldr r3, [r7, #4] 8004062: 6393 str r3, [r2, #56] @ 0x38 } 8004064: bf00 nop 8004066: 3748 adds r7, #72 @ 0x48 8004068: 46bd mov sp, r7 800406a: bd80 pop {r7, pc} 800406c: 58026000 .word 0x58026000 8004070: 58024400 .word 0x58024400 8004074: 58020800 .word 0x58020800 8004078: 2400033c .word 0x2400033c 800407c: 40020040 .word 0x40020040 08004080 : * This function configures the hardware resources used in this example * @param hcomp: COMP handle pointer * @retval None */ void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp) { 8004080: b580 push {r7, lr} 8004082: b08a sub sp, #40 @ 0x28 8004084: af00 add r7, sp, #0 8004086: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004088: f107 0314 add.w r3, r7, #20 800408c: 2200 movs r2, #0 800408e: 601a str r2, [r3, #0] 8004090: 605a str r2, [r3, #4] 8004092: 609a str r2, [r3, #8] 8004094: 60da str r2, [r3, #12] 8004096: 611a str r2, [r3, #16] if(hcomp->Instance==COMP1) 8004098: 687b ldr r3, [r7, #4] 800409a: 681b ldr r3, [r3, #0] 800409c: 4a18 ldr r2, [pc, #96] @ (8004100 ) 800409e: 4293 cmp r3, r2 80040a0: d129 bne.n 80040f6 { /* USER CODE BEGIN COMP1_MspInit 0 */ /* USER CODE END COMP1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_COMP12_CLK_ENABLE(); 80040a2: 4b18 ldr r3, [pc, #96] @ (8004104 ) 80040a4: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80040a8: 4a16 ldr r2, [pc, #88] @ (8004104 ) 80040aa: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80040ae: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 80040b2: 4b14 ldr r3, [pc, #80] @ (8004104 ) 80040b4: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 80040b8: f403 4380 and.w r3, r3, #16384 @ 0x4000 80040bc: 613b str r3, [r7, #16] 80040be: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 80040c0: 4b10 ldr r3, [pc, #64] @ (8004104 ) 80040c2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80040c6: 4a0f ldr r2, [pc, #60] @ (8004104 ) 80040c8: f043 0302 orr.w r3, r3, #2 80040cc: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80040d0: 4b0c ldr r3, [pc, #48] @ (8004104 ) 80040d2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80040d6: f003 0302 and.w r3, r3, #2 80040da: 60fb str r3, [r7, #12] 80040dc: 68fb ldr r3, [r7, #12] /**COMP1 GPIO Configuration PB2 ------> COMP1_INP */ GPIO_InitStruct.Pin = GPIO_PIN_2; 80040de: 2304 movs r3, #4 80040e0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80040e2: 2303 movs r3, #3 80040e4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80040e6: 2300 movs r3, #0 80040e8: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80040ea: f107 0314 add.w r3, r7, #20 80040ee: 4619 mov r1, r3 80040f0: 4805 ldr r0, [pc, #20] @ (8004108 ) 80040f2: f007 f86f bl 800b1d4 /* USER CODE BEGIN COMP1_MspInit 1 */ /* USER CODE END COMP1_MspInit 1 */ } } 80040f6: bf00 nop 80040f8: 3728 adds r7, #40 @ 0x28 80040fa: 46bd mov sp, r7 80040fc: bd80 pop {r7, pc} 80040fe: bf00 nop 8004100: 5800380c .word 0x5800380c 8004104: 58024400 .word 0x58024400 8004108: 58020400 .word 0x58020400 0800410c : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 800410c: b480 push {r7} 800410e: b085 sub sp, #20 8004110: af00 add r7, sp, #0 8004112: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8004114: 687b ldr r3, [r7, #4] 8004116: 681b ldr r3, [r3, #0] 8004118: 4a0b ldr r2, [pc, #44] @ (8004148 ) 800411a: 4293 cmp r3, r2 800411c: d10e bne.n 800413c { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 800411e: 4b0b ldr r3, [pc, #44] @ (800414c ) 8004120: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004124: 4a09 ldr r2, [pc, #36] @ (800414c ) 8004126: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800412a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800412e: 4b07 ldr r3, [pc, #28] @ (800414c ) 8004130: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004134: f403 2300 and.w r3, r3, #524288 @ 0x80000 8004138: 60fb str r3, [r7, #12] 800413a: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN CRC_MspInit 1 */ /* USER CODE END CRC_MspInit 1 */ } } 800413c: bf00 nop 800413e: 3714 adds r7, #20 8004140: 46bd mov sp, r7 8004142: f85d 7b04 ldr.w r7, [sp], #4 8004146: 4770 bx lr 8004148: 58024c00 .word 0x58024c00 800414c: 58024400 .word 0x58024400 08004150 : * This function configures the hardware resources used in this example * @param hdac: DAC handle pointer * @retval None */ void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) { 8004150: b580 push {r7, lr} 8004152: b08a sub sp, #40 @ 0x28 8004154: af00 add r7, sp, #0 8004156: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8004158: f107 0314 add.w r3, r7, #20 800415c: 2200 movs r2, #0 800415e: 601a str r2, [r3, #0] 8004160: 605a str r2, [r3, #4] 8004162: 609a str r2, [r3, #8] 8004164: 60da str r2, [r3, #12] 8004166: 611a str r2, [r3, #16] if(hdac->Instance==DAC1) 8004168: 687b ldr r3, [r7, #4] 800416a: 681b ldr r3, [r3, #0] 800416c: 4a1c ldr r2, [pc, #112] @ (80041e0 ) 800416e: 4293 cmp r3, r2 8004170: d131 bne.n 80041d6 { /* USER CODE BEGIN DAC1_MspInit 0 */ /* USER CODE END DAC1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DAC12_CLK_ENABLE(); 8004172: 4b1c ldr r3, [pc, #112] @ (80041e4 ) 8004174: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004178: 4a1a ldr r2, [pc, #104] @ (80041e4 ) 800417a: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 800417e: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004182: 4b18 ldr r3, [pc, #96] @ (80041e4 ) 8004184: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004188: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800418c: 613b str r3, [r7, #16] 800418e: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8004190: 4b14 ldr r3, [pc, #80] @ (80041e4 ) 8004192: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004196: 4a13 ldr r2, [pc, #76] @ (80041e4 ) 8004198: f043 0301 orr.w r3, r3, #1 800419c: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80041a0: 4b10 ldr r3, [pc, #64] @ (80041e4 ) 80041a2: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80041a6: f003 0301 and.w r3, r3, #1 80041aa: 60fb str r3, [r7, #12] 80041ac: 68fb ldr r3, [r7, #12] /**DAC1 GPIO Configuration PA4 ------> DAC1_OUT1 PA5 ------> DAC1_OUT2 */ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; 80041ae: 2330 movs r3, #48 @ 0x30 80041b0: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; 80041b2: 2303 movs r3, #3 80041b4: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80041b6: 2300 movs r3, #0 80041b8: 61fb str r3, [r7, #28] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80041ba: f107 0314 add.w r3, r7, #20 80041be: 4619 mov r1, r3 80041c0: 4809 ldr r0, [pc, #36] @ (80041e8 ) 80041c2: f007 f807 bl 800b1d4 /* DAC1 interrupt Init */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, 5, 0); 80041c6: 2200 movs r2, #0 80041c8: 2105 movs r1, #5 80041ca: 2036 movs r0, #54 @ 0x36 80041cc: f003 fcd0 bl 8007b70 HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 80041d0: 2036 movs r0, #54 @ 0x36 80041d2: f003 fce7 bl 8007ba4 /* USER CODE BEGIN DAC1_MspInit 1 */ /* USER CODE END DAC1_MspInit 1 */ } } 80041d6: bf00 nop 80041d8: 3728 adds r7, #40 @ 0x28 80041da: 46bd mov sp, r7 80041dc: bd80 pop {r7, pc} 80041de: bf00 nop 80041e0: 40007400 .word 0x40007400 80041e4: 58024400 .word 0x58024400 80041e8: 58020000 .word 0x58020000 080041ec : * This function configures the hardware resources used in this example * @param hrng: RNG handle pointer * @retval None */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { 80041ec: b580 push {r7, lr} 80041ee: b0b4 sub sp, #208 @ 0xd0 80041f0: af00 add r7, sp, #0 80041f2: 6078 str r0, [r7, #4] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 80041f4: f107 0310 add.w r3, r7, #16 80041f8: 22c0 movs r2, #192 @ 0xc0 80041fa: 2100 movs r1, #0 80041fc: 4618 mov r0, r3 80041fe: f014 f88b bl 8018318 if(hrng->Instance==RNG) 8004202: 687b ldr r3, [r7, #4] 8004204: 681b ldr r3, [r3, #0] 8004206: 4a14 ldr r2, [pc, #80] @ (8004258 ) 8004208: 4293 cmp r3, r2 800420a: d121 bne.n 8004250 /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG; 800420c: f44f 3200 mov.w r2, #131072 @ 0x20000 8004210: f04f 0300 mov.w r3, #0 8004214: e9c7 2304 strd r2, r3, [r7, #16] PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; 8004218: 2300 movs r3, #0 800421a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 800421e: f107 0310 add.w r3, r7, #16 8004222: 4618 mov r0, r3 8004224: f008 fbbc bl 800c9a0 8004228: 4603 mov r3, r0 800422a: 2b00 cmp r3, #0 800422c: d001 beq.n 8004232 { Error_Handler(); 800422e: f7fd fe4d bl 8001ecc } /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); 8004232: 4b0a ldr r3, [pc, #40] @ (800425c ) 8004234: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8004238: 4a08 ldr r2, [pc, #32] @ (800425c ) 800423a: f043 0340 orr.w r3, r3, #64 @ 0x40 800423e: f8c2 30dc str.w r3, [r2, #220] @ 0xdc 8004242: 4b06 ldr r3, [pc, #24] @ (800425c ) 8004244: f8d3 30dc ldr.w r3, [r3, #220] @ 0xdc 8004248: f003 0340 and.w r3, r3, #64 @ 0x40 800424c: 60fb str r3, [r7, #12] 800424e: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN RNG_MspInit 1 */ /* USER CODE END RNG_MspInit 1 */ } } 8004250: bf00 nop 8004252: 37d0 adds r7, #208 @ 0xd0 8004254: 46bd mov sp, r7 8004256: bd80 pop {r7, pc} 8004258: 48021800 .word 0x48021800 800425c: 58024400 .word 0x58024400 08004260 : * This function configures the hardware resources used in this example * @param htim_pwm: TIM_PWM handle pointer * @retval None */ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) { 8004260: b480 push {r7} 8004262: b085 sub sp, #20 8004264: af00 add r7, sp, #0 8004266: 6078 str r0, [r7, #4] if(htim_pwm->Instance==TIM1) 8004268: 687b ldr r3, [r7, #4] 800426a: 681b ldr r3, [r3, #0] 800426c: 4a16 ldr r2, [pc, #88] @ (80042c8 ) 800426e: 4293 cmp r3, r2 8004270: d10f bne.n 8004292 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8004272: 4b16 ldr r3, [pc, #88] @ (80042cc ) 8004274: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004278: 4a14 ldr r2, [pc, #80] @ (80042cc ) 800427a: f043 0301 orr.w r3, r3, #1 800427e: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 8004282: 4b12 ldr r3, [pc, #72] @ (80042cc ) 8004284: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004288: f003 0301 and.w r3, r3, #1 800428c: 60fb str r3, [r7, #12] 800428e: 68fb ldr r3, [r7, #12] /* USER CODE BEGIN TIM3_MspInit 1 */ /* USER CODE END TIM3_MspInit 1 */ } } 8004290: e013 b.n 80042ba else if(htim_pwm->Instance==TIM3) 8004292: 687b ldr r3, [r7, #4] 8004294: 681b ldr r3, [r3, #0] 8004296: 4a0e ldr r2, [pc, #56] @ (80042d0 ) 8004298: 4293 cmp r3, r2 800429a: d10e bne.n 80042ba __HAL_RCC_TIM3_CLK_ENABLE(); 800429c: 4b0b ldr r3, [pc, #44] @ (80042cc ) 800429e: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80042a2: 4a0a ldr r2, [pc, #40] @ (80042cc ) 80042a4: f043 0302 orr.w r3, r3, #2 80042a8: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80042ac: 4b07 ldr r3, [pc, #28] @ (80042cc ) 80042ae: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80042b2: f003 0302 and.w r3, r3, #2 80042b6: 60bb str r3, [r7, #8] 80042b8: 68bb ldr r3, [r7, #8] } 80042ba: bf00 nop 80042bc: 3714 adds r7, #20 80042be: 46bd mov sp, r7 80042c0: f85d 7b04 ldr.w r7, [sp], #4 80042c4: 4770 bx lr 80042c6: bf00 nop 80042c8: 40010000 .word 0x40010000 80042cc: 58024400 .word 0x58024400 80042d0: 40000400 .word 0x40000400 080042d4 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80042d4: b580 push {r7, lr} 80042d6: b08c sub sp, #48 @ 0x30 80042d8: af00 add r7, sp, #0 80042da: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80042dc: f107 031c add.w r3, r7, #28 80042e0: 2200 movs r2, #0 80042e2: 601a str r2, [r3, #0] 80042e4: 605a str r2, [r3, #4] 80042e6: 609a str r2, [r3, #8] 80042e8: 60da str r2, [r3, #12] 80042ea: 611a str r2, [r3, #16] if(htim_base->Instance==TIM2) 80042ec: 687b ldr r3, [r7, #4] 80042ee: 681b ldr r3, [r3, #0] 80042f0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80042f4: d137 bne.n 8004366 { /* USER CODE BEGIN TIM2_MspInit 0 */ /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); 80042f6: 4b46 ldr r3, [pc, #280] @ (8004410 ) 80042f8: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80042fc: 4a44 ldr r2, [pc, #272] @ (8004410 ) 80042fe: f043 0301 orr.w r3, r3, #1 8004302: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004306: 4b42 ldr r3, [pc, #264] @ (8004410 ) 8004308: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800430c: f003 0301 and.w r3, r3, #1 8004310: 61bb str r3, [r7, #24] 8004312: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8004314: 4b3e ldr r3, [pc, #248] @ (8004410 ) 8004316: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800431a: 4a3d ldr r2, [pc, #244] @ (8004410 ) 800431c: f043 0302 orr.w r3, r3, #2 8004320: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004324: 4b3a ldr r3, [pc, #232] @ (8004410 ) 8004326: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800432a: f003 0302 and.w r3, r3, #2 800432e: 617b str r3, [r7, #20] 8004330: 697b ldr r3, [r7, #20] /**TIM2 GPIO Configuration PB10 ------> TIM2_CH3 PB11 ------> TIM2_CH4 */ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11; 8004332: f44f 6340 mov.w r3, #3072 @ 0xc00 8004336: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004338: 2302 movs r3, #2 800433a: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 800433c: 2300 movs r3, #0 800433e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004340: 2300 movs r3, #0 8004342: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; 8004344: 2301 movs r3, #1 8004346: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8004348: f107 031c add.w r3, r7, #28 800434c: 4619 mov r1, r3 800434e: 4831 ldr r0, [pc, #196] @ (8004414 ) 8004350: f006 ff40 bl 800b1d4 /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0); 8004354: 2200 movs r2, #0 8004356: 2105 movs r1, #5 8004358: 201c movs r0, #28 800435a: f003 fc09 bl 8007b70 HAL_NVIC_EnableIRQ(TIM2_IRQn); 800435e: 201c movs r0, #28 8004360: f003 fc20 bl 8007ba4 /* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE END TIM8_MspInit 1 */ } } 8004364: e050 b.n 8004408 else if(htim_base->Instance==TIM4) 8004366: 687b ldr r3, [r7, #4] 8004368: 681b ldr r3, [r3, #0] 800436a: 4a2b ldr r2, [pc, #172] @ (8004418 ) 800436c: 4293 cmp r3, r2 800436e: d137 bne.n 80043e0 __HAL_RCC_TIM4_CLK_ENABLE(); 8004370: 4b27 ldr r3, [pc, #156] @ (8004410 ) 8004372: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004376: 4a26 ldr r2, [pc, #152] @ (8004410 ) 8004378: f043 0304 orr.w r3, r3, #4 800437c: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004380: 4b23 ldr r3, [pc, #140] @ (8004410 ) 8004382: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 8004386: f003 0304 and.w r3, r3, #4 800438a: 613b str r3, [r7, #16] 800438c: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); 800438e: 4b20 ldr r3, [pc, #128] @ (8004410 ) 8004390: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004394: 4a1e ldr r2, [pc, #120] @ (8004410 ) 8004396: f043 0308 orr.w r3, r3, #8 800439a: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800439e: 4b1c ldr r3, [pc, #112] @ (8004410 ) 80043a0: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80043a4: f003 0308 and.w r3, r3, #8 80043a8: 60fb str r3, [r7, #12] 80043aa: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 80043ac: f44f 4340 mov.w r3, #49152 @ 0xc000 80043b0: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80043b2: 2302 movs r3, #2 80043b4: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; 80043b6: 2300 movs r3, #0 80043b8: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80043ba: 2300 movs r3, #0 80043bc: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; 80043be: 2302 movs r3, #2 80043c0: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80043c2: f107 031c add.w r3, r7, #28 80043c6: 4619 mov r1, r3 80043c8: 4814 ldr r0, [pc, #80] @ (800441c ) 80043ca: f006 ff03 bl 800b1d4 HAL_NVIC_SetPriority(TIM4_IRQn, 5, 0); 80043ce: 2200 movs r2, #0 80043d0: 2105 movs r1, #5 80043d2: 201e movs r0, #30 80043d4: f003 fbcc bl 8007b70 HAL_NVIC_EnableIRQ(TIM4_IRQn); 80043d8: 201e movs r0, #30 80043da: f003 fbe3 bl 8007ba4 } 80043de: e013 b.n 8004408 else if(htim_base->Instance==TIM8) 80043e0: 687b ldr r3, [r7, #4] 80043e2: 681b ldr r3, [r3, #0] 80043e4: 4a0e ldr r2, [pc, #56] @ (8004420 ) 80043e6: 4293 cmp r3, r2 80043e8: d10e bne.n 8004408 __HAL_RCC_TIM8_CLK_ENABLE(); 80043ea: 4b09 ldr r3, [pc, #36] @ (8004410 ) 80043ec: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80043f0: 4a07 ldr r2, [pc, #28] @ (8004410 ) 80043f2: f043 0302 orr.w r3, r3, #2 80043f6: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80043fa: 4b05 ldr r3, [pc, #20] @ (8004410 ) 80043fc: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004400: f003 0302 and.w r3, r3, #2 8004404: 60bb str r3, [r7, #8] 8004406: 68bb ldr r3, [r7, #8] } 8004408: bf00 nop 800440a: 3730 adds r7, #48 @ 0x30 800440c: 46bd mov sp, r7 800440e: bd80 pop {r7, pc} 8004410: 58024400 .word 0x58024400 8004414: 58020400 .word 0x58020400 8004418: 40000800 .word 0x40000800 800441c: 58020c00 .word 0x58020c00 8004420: 40010400 .word 0x40010400 08004424 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8004424: b580 push {r7, lr} 8004426: b08a sub sp, #40 @ 0x28 8004428: af00 add r7, sp, #0 800442a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 800442c: f107 0314 add.w r3, r7, #20 8004430: 2200 movs r2, #0 8004432: 601a str r2, [r3, #0] 8004434: 605a str r2, [r3, #4] 8004436: 609a str r2, [r3, #8] 8004438: 60da str r2, [r3, #12] 800443a: 611a str r2, [r3, #16] if(htim->Instance==TIM1) 800443c: 687b ldr r3, [r7, #4] 800443e: 681b ldr r3, [r3, #0] 8004440: 4a26 ldr r2, [pc, #152] @ (80044dc ) 8004442: 4293 cmp r3, r2 8004444: d120 bne.n 8004488 { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8004446: 4b26 ldr r3, [pc, #152] @ (80044e0 ) 8004448: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800444c: 4a24 ldr r2, [pc, #144] @ (80044e0 ) 800444e: f043 0301 orr.w r3, r3, #1 8004452: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004456: 4b22 ldr r3, [pc, #136] @ (80044e0 ) 8004458: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800445c: f003 0301 and.w r3, r3, #1 8004460: 613b str r3, [r7, #16] 8004462: 693b ldr r3, [r7, #16] /**TIM1 GPIO Configuration PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = GPIO_PIN_9; 8004464: f44f 7300 mov.w r3, #512 @ 0x200 8004468: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800446a: 2302 movs r3, #2 800446c: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800446e: 2300 movs r3, #0 8004470: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004472: 2300 movs r3, #0 8004474: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; 8004476: 2301 movs r3, #1 8004478: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800447a: f107 0314 add.w r3, r7, #20 800447e: 4619 mov r1, r3 8004480: 4818 ldr r0, [pc, #96] @ (80044e4 ) 8004482: f006 fea7 bl 800b1d4 /* USER CODE BEGIN TIM3_MspPostInit 1 */ /* USER CODE END TIM3_MspPostInit 1 */ } } 8004486: e024 b.n 80044d2 else if(htim->Instance==TIM3) 8004488: 687b ldr r3, [r7, #4] 800448a: 681b ldr r3, [r3, #0] 800448c: 4a16 ldr r2, [pc, #88] @ (80044e8 ) 800448e: 4293 cmp r3, r2 8004490: d11f bne.n 80044d2 __HAL_RCC_GPIOC_CLK_ENABLE(); 8004492: 4b13 ldr r3, [pc, #76] @ (80044e0 ) 8004494: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004498: 4a11 ldr r2, [pc, #68] @ (80044e0 ) 800449a: f043 0304 orr.w r3, r3, #4 800449e: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 80044a2: 4b0f ldr r3, [pc, #60] @ (80044e0 ) 80044a4: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 80044a8: f003 0304 and.w r3, r3, #4 80044ac: 60fb str r3, [r7, #12] 80044ae: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9; 80044b0: f44f 7370 mov.w r3, #960 @ 0x3c0 80044b4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80044b6: 2302 movs r3, #2 80044b8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80044ba: 2300 movs r3, #0 80044bc: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM; 80044be: 2301 movs r3, #1 80044c0: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; 80044c2: 2302 movs r3, #2 80044c4: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80044c6: f107 0314 add.w r3, r7, #20 80044ca: 4619 mov r1, r3 80044cc: 4807 ldr r0, [pc, #28] @ (80044ec ) 80044ce: f006 fe81 bl 800b1d4 } 80044d2: bf00 nop 80044d4: 3728 adds r7, #40 @ 0x28 80044d6: 46bd mov sp, r7 80044d8: bd80 pop {r7, pc} 80044da: bf00 nop 80044dc: 40010000 .word 0x40010000 80044e0: 58024400 .word 0x58024400 80044e4: 58020000 .word 0x58020000 80044e8: 40000400 .word 0x40000400 80044ec: 58020800 .word 0x58020800 080044f0 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 80044f0: b580 push {r7, lr} 80044f2: b0bc sub sp, #240 @ 0xf0 80044f4: af00 add r7, sp, #0 80044f6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80044f8: f107 03dc add.w r3, r7, #220 @ 0xdc 80044fc: 2200 movs r2, #0 80044fe: 601a str r2, [r3, #0] 8004500: 605a str r2, [r3, #4] 8004502: 609a str r2, [r3, #8] 8004504: 60da str r2, [r3, #12] 8004506: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8004508: f107 0318 add.w r3, r7, #24 800450c: 22c0 movs r2, #192 @ 0xc0 800450e: 2100 movs r1, #0 8004510: 4618 mov r0, r3 8004512: f013 ff01 bl 8018318 if(huart->Instance==UART8) 8004516: 687b ldr r3, [r7, #4] 8004518: 681b ldr r3, [r3, #0] 800451a: 4a55 ldr r2, [pc, #340] @ (8004670 ) 800451c: 4293 cmp r3, r2 800451e: d14e bne.n 80045be /* USER CODE END UART8_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; 8004520: f04f 0202 mov.w r2, #2 8004524: f04f 0300 mov.w r3, #0 8004528: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; 800452c: 2300 movs r3, #0 800452e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8004532: f107 0318 add.w r3, r7, #24 8004536: 4618 mov r0, r3 8004538: f008 fa32 bl 800c9a0 800453c: 4603 mov r3, r0 800453e: 2b00 cmp r3, #0 8004540: d001 beq.n 8004546 { Error_Handler(); 8004542: f7fd fcc3 bl 8001ecc } /* Peripheral clock enable */ __HAL_RCC_UART8_CLK_ENABLE(); 8004546: 4b4b ldr r3, [pc, #300] @ (8004674 ) 8004548: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800454c: 4a49 ldr r2, [pc, #292] @ (8004674 ) 800454e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8004552: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 8004556: 4b47 ldr r3, [pc, #284] @ (8004674 ) 8004558: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 800455c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8004560: 617b str r3, [r7, #20] 8004562: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOE_CLK_ENABLE(); 8004564: 4b43 ldr r3, [pc, #268] @ (8004674 ) 8004566: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800456a: 4a42 ldr r2, [pc, #264] @ (8004674 ) 800456c: f043 0310 orr.w r3, r3, #16 8004570: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 8004574: 4b3f ldr r3, [pc, #252] @ (8004674 ) 8004576: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 800457a: f003 0310 and.w r3, r3, #16 800457e: 613b str r3, [r7, #16] 8004580: 693b ldr r3, [r7, #16] /**UART8 GPIO Configuration PE0 ------> UART8_RX PE1 ------> UART8_TX */ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; 8004582: 2303 movs r3, #3 8004584: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004588: 2302 movs r3, #2 800458a: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 800458e: 2300 movs r3, #0 8004590: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8004594: 2300 movs r3, #0 8004596: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF8_UART8; 800459a: 2308 movs r3, #8 800459c: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80045a0: f107 03dc add.w r3, r7, #220 @ 0xdc 80045a4: 4619 mov r1, r3 80045a6: 4834 ldr r0, [pc, #208] @ (8004678 ) 80045a8: f006 fe14 bl 800b1d4 /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); 80045ac: 2200 movs r2, #0 80045ae: 2105 movs r1, #5 80045b0: 2053 movs r0, #83 @ 0x53 80045b2: f003 fadd bl 8007b70 HAL_NVIC_EnableIRQ(UART8_IRQn); 80045b6: 2053 movs r0, #83 @ 0x53 80045b8: f003 faf4 bl 8007ba4 /* USER CODE BEGIN USART1_MspInit 1 */ /* USER CODE END USART1_MspInit 1 */ } } 80045bc: e053 b.n 8004666 else if(huart->Instance==USART1) 80045be: 687b ldr r3, [r7, #4] 80045c0: 681b ldr r3, [r3, #0] 80045c2: 4a2e ldr r2, [pc, #184] @ (800467c ) 80045c4: 4293 cmp r3, r2 80045c6: d14e bne.n 8004666 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; 80045c8: f04f 0201 mov.w r2, #1 80045cc: f04f 0300 mov.w r3, #0 80045d0: e9c7 2306 strd r2, r3, [r7, #24] PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; 80045d4: 2300 movs r3, #0 80045d6: f8c7 3094 str.w r3, [r7, #148] @ 0x94 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 80045da: f107 0318 add.w r3, r7, #24 80045de: 4618 mov r0, r3 80045e0: f008 f9de bl 800c9a0 80045e4: 4603 mov r3, r0 80045e6: 2b00 cmp r3, #0 80045e8: d001 beq.n 80045ee Error_Handler(); 80045ea: f7fd fc6f bl 8001ecc __HAL_RCC_USART1_CLK_ENABLE(); 80045ee: 4b21 ldr r3, [pc, #132] @ (8004674 ) 80045f0: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 80045f4: 4a1f ldr r2, [pc, #124] @ (8004674 ) 80045f6: f043 0310 orr.w r3, r3, #16 80045fa: f8c2 30f0 str.w r3, [r2, #240] @ 0xf0 80045fe: 4b1d ldr r3, [pc, #116] @ (8004674 ) 8004600: f8d3 30f0 ldr.w r3, [r3, #240] @ 0xf0 8004604: f003 0310 and.w r3, r3, #16 8004608: 60fb str r3, [r7, #12] 800460a: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOB_CLK_ENABLE(); 800460c: 4b19 ldr r3, [pc, #100] @ (8004674 ) 800460e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004612: 4a18 ldr r2, [pc, #96] @ (8004674 ) 8004614: f043 0302 orr.w r3, r3, #2 8004618: f8c2 30e0 str.w r3, [r2, #224] @ 0xe0 800461c: 4b15 ldr r3, [pc, #84] @ (8004674 ) 800461e: f8d3 30e0 ldr.w r3, [r3, #224] @ 0xe0 8004622: f003 0302 and.w r3, r3, #2 8004626: 60bb str r3, [r7, #8] 8004628: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; 800462a: f44f 4340 mov.w r3, #49152 @ 0xc000 800462e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8004632: 2302 movs r3, #2 8004634: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 GPIO_InitStruct.Pull = GPIO_NOPULL; 8004638: 2300 movs r3, #0 800463a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800463e: 2300 movs r3, #0 8004640: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 GPIO_InitStruct.Alternate = GPIO_AF4_USART1; 8004644: 2304 movs r3, #4 8004646: f8c7 30ec str.w r3, [r7, #236] @ 0xec HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800464a: f107 03dc add.w r3, r7, #220 @ 0xdc 800464e: 4619 mov r1, r3 8004650: 480b ldr r0, [pc, #44] @ (8004680 ) 8004652: f006 fdbf bl 800b1d4 HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); 8004656: 2200 movs r2, #0 8004658: 2105 movs r1, #5 800465a: 2025 movs r0, #37 @ 0x25 800465c: f003 fa88 bl 8007b70 HAL_NVIC_EnableIRQ(USART1_IRQn); 8004660: 2025 movs r0, #37 @ 0x25 8004662: f003 fa9f bl 8007ba4 } 8004666: bf00 nop 8004668: 37f0 adds r7, #240 @ 0xf0 800466a: 46bd mov sp, r7 800466c: bd80 pop {r7, pc} 800466e: bf00 nop 8004670: 40007c00 .word 0x40007c00 8004674: 58024400 .word 0x58024400 8004678: 58021000 .word 0x58021000 800467c: 40011000 .word 0x40011000 8004680: 58020400 .word 0x58020400 08004684 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8004684: b580 push {r7, lr} 8004686: b090 sub sp, #64 @ 0x40 8004688: af00 add r7, sp, #0 800468a: 6078 str r0, [r7, #4] uint32_t uwTimclock, uwAPB1Prescaler; uint32_t uwPrescalerValue; uint32_t pFLatency; /*Configure the TIM6 IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800468c: 687b ldr r3, [r7, #4] 800468e: 2b0f cmp r3, #15 8004690: d827 bhi.n 80046e2 { HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U); 8004692: 2200 movs r2, #0 8004694: 6879 ldr r1, [r7, #4] 8004696: 2036 movs r0, #54 @ 0x36 8004698: f003 fa6a bl 8007b70 /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 800469c: 2036 movs r0, #54 @ 0x36 800469e: f003 fa81 bl 8007ba4 uwTickPrio = TickPriority; 80046a2: 4a29 ldr r2, [pc, #164] @ (8004748 ) 80046a4: 687b ldr r3, [r7, #4] 80046a6: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 80046a8: 4b28 ldr r3, [pc, #160] @ (800474c ) 80046aa: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80046ae: 4a27 ldr r2, [pc, #156] @ (800474c ) 80046b0: f043 0310 orr.w r3, r3, #16 80046b4: f8c2 30e8 str.w r3, [r2, #232] @ 0xe8 80046b8: 4b24 ldr r3, [pc, #144] @ (800474c ) 80046ba: f8d3 30e8 ldr.w r3, [r3, #232] @ 0xe8 80046be: f003 0310 and.w r3, r3, #16 80046c2: 60fb str r3, [r7, #12] 80046c4: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 80046c6: f107 0210 add.w r2, r7, #16 80046ca: f107 0314 add.w r3, r7, #20 80046ce: 4611 mov r1, r2 80046d0: 4618 mov r0, r3 80046d2: f008 f923 bl 800c91c /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 80046d6: 6abb ldr r3, [r7, #40] @ 0x28 80046d8: 63bb str r3, [r7, #56] @ 0x38 /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 80046da: 6bbb ldr r3, [r7, #56] @ 0x38 80046dc: 2b00 cmp r3, #0 80046de: d106 bne.n 80046ee 80046e0: e001 b.n 80046e6 return HAL_ERROR; 80046e2: 2301 movs r3, #1 80046e4: e02b b.n 800473e { uwTimclock = HAL_RCC_GetPCLK1Freq(); 80046e6: f008 f8ed bl 800c8c4 80046ea: 63f8 str r0, [r7, #60] @ 0x3c 80046ec: e004 b.n 80046f8 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 80046ee: f008 f8e9 bl 800c8c4 80046f2: 4603 mov r3, r0 80046f4: 005b lsls r3, r3, #1 80046f6: 63fb str r3, [r7, #60] @ 0x3c } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 80046f8: 6bfb ldr r3, [r7, #60] @ 0x3c 80046fa: 4a15 ldr r2, [pc, #84] @ (8004750 ) 80046fc: fba2 2303 umull r2, r3, r2, r3 8004700: 0c9b lsrs r3, r3, #18 8004702: 3b01 subs r3, #1 8004704: 637b str r3, [r7, #52] @ 0x34 /* Initialize TIM6 */ htim6.Instance = TIM6; 8004706: 4b13 ldr r3, [pc, #76] @ (8004754 ) 8004708: 4a13 ldr r2, [pc, #76] @ (8004758 ) 800470a: 601a str r2, [r3, #0] + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 800470c: 4b11 ldr r3, [pc, #68] @ (8004754 ) 800470e: f240 32e7 movw r2, #999 @ 0x3e7 8004712: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8004714: 4a0f ldr r2, [pc, #60] @ (8004754 ) 8004716: 6b7b ldr r3, [r7, #52] @ 0x34 8004718: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 800471a: 4b0e ldr r3, [pc, #56] @ (8004754 ) 800471c: 2200 movs r2, #0 800471e: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8004720: 4b0c ldr r3, [pc, #48] @ (8004754 ) 8004722: 2200 movs r2, #0 8004724: 609a str r2, [r3, #8] if(HAL_TIM_Base_Init(&htim6) == HAL_OK) 8004726: 480b ldr r0, [pc, #44] @ (8004754 ) 8004728: f00a fe7e bl 800f428 800472c: 4603 mov r3, r0 800472e: 2b00 cmp r3, #0 8004730: d104 bne.n 800473c { /* Start the TIM time Base generation in interrupt mode */ return HAL_TIM_Base_Start_IT(&htim6); 8004732: 4808 ldr r0, [pc, #32] @ (8004754 ) 8004734: f00a ff40 bl 800f5b8 8004738: 4603 mov r3, r0 800473a: e000 b.n 800473e } /* Return function status */ return HAL_ERROR; 800473c: 2301 movs r3, #1 } 800473e: 4618 mov r0, r3 8004740: 3740 adds r7, #64 @ 0x40 8004742: 46bd mov sp, r7 8004744: bd80 pop {r7, pc} 8004746: bf00 nop 8004748: 2400003c .word 0x2400003c 800474c: 58024400 .word 0x58024400 8004750: 431bde83 .word 0x431bde83 8004754: 24000920 .word 0x24000920 8004758: 40001000 .word 0x40001000 0800475c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 800475c: b480 push {r7} 800475e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8004760: bf00 nop 8004762: e7fd b.n 8004760 08004764 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8004764: b480 push {r7} 8004766: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8004768: bf00 nop 800476a: e7fd b.n 8004768 0800476c : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 800476c: b480 push {r7} 800476e: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8004770: bf00 nop 8004772: e7fd b.n 8004770 08004774 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8004774: b480 push {r7} 8004776: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8004778: bf00 nop 800477a: e7fd b.n 8004778 0800477c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800477c: b480 push {r7} 800477e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8004780: bf00 nop 8004782: e7fd b.n 8004780 08004784 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8004784: b480 push {r7} 8004786: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8004788: bf00 nop 800478a: 46bd mov sp, r7 800478c: f85d 7b04 ldr.w r7, [sp], #4 8004790: 4770 bx lr 08004792 : /** * @brief This function handles RCC global interrupt. */ void RCC_IRQHandler(void) { 8004792: b480 push {r7} 8004794: af00 add r7, sp, #0 /* USER CODE END RCC_IRQn 0 */ /* USER CODE BEGIN RCC_IRQn 1 */ /* USER CODE END RCC_IRQn 1 */ } 8004796: bf00 nop 8004798: 46bd mov sp, r7 800479a: f85d 7b04 ldr.w r7, [sp], #4 800479e: 4770 bx lr 080047a0 : /** * @brief This function handles DMA1 stream0 global interrupt. */ void DMA1_Stream0_IRQHandler(void) { 80047a0: b580 push {r7, lr} 80047a2: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ /* USER CODE END DMA1_Stream0_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc1); 80047a4: 4802 ldr r0, [pc, #8] @ (80047b0 ) 80047a6: f005 fa03 bl 8009bb0 /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ /* USER CODE END DMA1_Stream0_IRQn 1 */ } 80047aa: bf00 nop 80047ac: bd80 pop {r7, pc} 80047ae: bf00 nop 80047b0: 2400024c .word 0x2400024c 080047b4 : /** * @brief This function handles DMA1 stream1 global interrupt. */ void DMA1_Stream1_IRQHandler(void) { 80047b4: b580 push {r7, lr} 80047b6: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream1_IRQn 0 */ /* USER CODE END DMA1_Stream1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc2); 80047b8: 4802 ldr r0, [pc, #8] @ (80047c4 ) 80047ba: f005 f9f9 bl 8009bb0 /* USER CODE BEGIN DMA1_Stream1_IRQn 1 */ /* USER CODE END DMA1_Stream1_IRQn 1 */ } 80047be: bf00 nop 80047c0: bd80 pop {r7, pc} 80047c2: bf00 nop 80047c4: 240002c4 .word 0x240002c4 080047c8 : /** * @brief This function handles DMA1 stream2 global interrupt. */ void DMA1_Stream2_IRQHandler(void) { 80047c8: b580 push {r7, lr} 80047ca: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ /* USER CODE END DMA1_Stream2_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_adc3); 80047cc: 4802 ldr r0, [pc, #8] @ (80047d8 ) 80047ce: f005 f9ef bl 8009bb0 /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ /* USER CODE END DMA1_Stream2_IRQn 1 */ } 80047d2: bf00 nop 80047d4: bd80 pop {r7, pc} 80047d6: bf00 nop 80047d8: 2400033c .word 0x2400033c 080047dc : /** * @brief This function handles EXTI line[9:5] interrupts. */ void EXTI9_5_IRQHandler(void) { 80047dc: b580 push {r7, lr} 80047de: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI9_5_IRQn 0 */ /* USER CODE END EXTI9_5_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); 80047e0: f44f 7080 mov.w r0, #256 @ 0x100 80047e4: f006 fef1 bl 800b5ca HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); 80047e8: f44f 7000 mov.w r0, #512 @ 0x200 80047ec: f006 feed bl 800b5ca /* USER CODE BEGIN EXTI9_5_IRQn 1 */ /* USER CODE END EXTI9_5_IRQn 1 */ } 80047f0: bf00 nop 80047f2: bd80 pop {r7, pc} 080047f4 : /** * @brief This function handles TIM2 global interrupt. */ void TIM2_IRQHandler(void) { 80047f4: b580 push {r7, lr} 80047f6: af00 add r7, sp, #0 /* USER CODE BEGIN TIM2_IRQn 0 */ /* USER CODE END TIM2_IRQn 0 */ HAL_TIM_IRQHandler(&htim2); 80047f8: 4802 ldr r0, [pc, #8] @ (8004804 ) 80047fa: f00b fb03 bl 800fe04 /* USER CODE BEGIN TIM2_IRQn 1 */ /* USER CODE END TIM2_IRQn 1 */ } 80047fe: bf00 nop 8004800: bd80 pop {r7, pc} 8004802: bf00 nop 8004804: 24000488 .word 0x24000488 08004808 : /** * @brief This function handles TIM4 global interrupt. */ void TIM4_IRQHandler(void) { 8004808: b580 push {r7, lr} 800480a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM4_IRQn 0 */ /* USER CODE END TIM4_IRQn 0 */ HAL_TIM_IRQHandler(&htim4); 800480c: 4802 ldr r0, [pc, #8] @ (8004818 ) 800480e: f00b faf9 bl 800fe04 /* USER CODE BEGIN TIM4_IRQn 1 */ /* USER CODE END TIM4_IRQn 1 */ } 8004812: bf00 nop 8004814: bd80 pop {r7, pc} 8004816: bf00 nop 8004818: 24000520 .word 0x24000520 0800481c : /** * @brief This function handles USART1 global interrupt. */ void USART1_IRQHandler(void) { 800481c: b580 push {r7, lr} 800481e: af00 add r7, sp, #0 /* USER CODE BEGIN USART1_IRQn 0 */ /* USER CODE END USART1_IRQn 0 */ HAL_UART_IRQHandler(&huart1); 8004820: 4802 ldr r0, [pc, #8] @ (800482c ) 8004822: f00c feb3 bl 801158c /* USER CODE BEGIN USART1_IRQn 1 */ /* USER CODE END USART1_IRQn 1 */ } 8004826: bf00 nop 8004828: bd80 pop {r7, pc} 800482a: bf00 nop 800482c: 2400064c .word 0x2400064c 08004830 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8004830: b580 push {r7, lr} 8004832: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); 8004834: f44f 6080 mov.w r0, #1024 @ 0x400 8004838: f006 fec7 bl 800b5ca HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); 800483c: f44f 6000 mov.w r0, #2048 @ 0x800 8004840: f006 fec3 bl 800b5ca HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); 8004844: f44f 5080 mov.w r0, #4096 @ 0x1000 8004848: f006 febf bl 800b5ca HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); 800484c: f44f 5000 mov.w r0, #8192 @ 0x2000 8004850: f006 febb bl 800b5ca /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 8004854: bf00 nop 8004856: bd80 pop {r7, pc} 08004858 : /** * @brief This function handles TIM6 global interrupt, DAC1_CH1 and DAC1_CH2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8004858: b580 push {r7, lr} 800485a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ if (hdac1.State != HAL_DAC_STATE_RESET) { 800485c: 4b06 ldr r3, [pc, #24] @ (8004878 ) 800485e: 791b ldrb r3, [r3, #4] 8004860: b2db uxtb r3, r3 8004862: 2b00 cmp r3, #0 8004864: d002 beq.n 800486c HAL_DAC_IRQHandler(&hdac1); 8004866: 4804 ldr r0, [pc, #16] @ (8004878 ) 8004868: f003 fca1 bl 80081ae } HAL_TIM_IRQHandler(&htim6); 800486c: 4803 ldr r0, [pc, #12] @ (800487c ) 800486e: f00b fac9 bl 800fe04 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8004872: bf00 nop 8004874: bd80 pop {r7, pc} 8004876: bf00 nop 8004878: 24000404 .word 0x24000404 800487c: 24000920 .word 0x24000920 08004880 : /** * @brief This function handles UART8 global interrupt. */ void UART8_IRQHandler(void) { 8004880: b580 push {r7, lr} 8004882: af00 add r7, sp, #0 /* USER CODE BEGIN UART8_IRQn 0 */ /* USER CODE END UART8_IRQn 0 */ HAL_UART_IRQHandler(&huart8); 8004884: 4802 ldr r0, [pc, #8] @ (8004890 ) 8004886: f00c fe81 bl 801158c /* USER CODE BEGIN UART8_IRQn 1 */ /* USER CODE END UART8_IRQn 1 */ } 800488a: bf00 nop 800488c: bd80 pop {r7, pc} 800488e: bf00 nop 8004890: 240005b8 .word 0x240005b8 08004894 : * configuration. * @param None * @retval None */ void SystemInit (void) { 8004894: b480 push {r7} 8004896: af00 add r7, sp, #0 __IO uint32_t tmpreg; #endif /* DATA_IN_D2_SRAM */ /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ 8004898: 4b37 ldr r3, [pc, #220] @ (8004978 ) 800489a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800489e: 4a36 ldr r2, [pc, #216] @ (8004978 ) 80048a0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 80048a4: f8c2 3088 str.w r3, [r2, #136] @ 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Increasing the CPU frequency */ if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80048a8: 4b34 ldr r3, [pc, #208] @ (800497c ) 80048aa: 681b ldr r3, [r3, #0] 80048ac: f003 030f and.w r3, r3, #15 80048b0: 2b06 cmp r3, #6 80048b2: d807 bhi.n 80048c4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80048b4: 4b31 ldr r3, [pc, #196] @ (800497c ) 80048b6: 681b ldr r3, [r3, #0] 80048b8: f023 030f bic.w r3, r3, #15 80048bc: 4a2f ldr r2, [pc, #188] @ (800497c ) 80048be: f043 0307 orr.w r3, r3, #7 80048c2: 6013 str r3, [r2, #0] } /* Set HSION bit */ RCC->CR |= RCC_CR_HSION; 80048c4: 4b2e ldr r3, [pc, #184] @ (8004980 ) 80048c6: 681b ldr r3, [r3, #0] 80048c8: 4a2d ldr r2, [pc, #180] @ (8004980 ) 80048ca: f043 0301 orr.w r3, r3, #1 80048ce: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 80048d0: 4b2b ldr r3, [pc, #172] @ (8004980 ) 80048d2: 2200 movs r2, #0 80048d4: 611a str r2, [r3, #16] /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ RCC->CR &= 0xEAF6ED7FU; 80048d6: 4b2a ldr r3, [pc, #168] @ (8004980 ) 80048d8: 681a ldr r2, [r3, #0] 80048da: 4929 ldr r1, [pc, #164] @ (8004980 ) 80048dc: 4b29 ldr r3, [pc, #164] @ (8004984 ) 80048de: 4013 ands r3, r2 80048e0: 600b str r3, [r1, #0] /* Decreasing the number of wait states because of lower CPU frequency */ if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) 80048e2: 4b26 ldr r3, [pc, #152] @ (800497c ) 80048e4: 681b ldr r3, [r3, #0] 80048e6: f003 0308 and.w r3, r3, #8 80048ea: 2b00 cmp r3, #0 80048ec: d007 beq.n 80048fe { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); 80048ee: 4b23 ldr r3, [pc, #140] @ (800497c ) 80048f0: 681b ldr r3, [r3, #0] 80048f2: f023 030f bic.w r3, r3, #15 80048f6: 4a21 ldr r2, [pc, #132] @ (800497c ) 80048f8: f043 0307 orr.w r3, r3, #7 80048fc: 6013 str r3, [r2, #0] } #if defined(D3_SRAM_BASE) /* Reset D1CFGR register */ RCC->D1CFGR = 0x00000000; 80048fe: 4b20 ldr r3, [pc, #128] @ (8004980 ) 8004900: 2200 movs r2, #0 8004902: 619a str r2, [r3, #24] /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; 8004904: 4b1e ldr r3, [pc, #120] @ (8004980 ) 8004906: 2200 movs r2, #0 8004908: 61da str r2, [r3, #28] /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; 800490a: 4b1d ldr r3, [pc, #116] @ (8004980 ) 800490c: 2200 movs r2, #0 800490e: 621a str r2, [r3, #32] /* Reset SRDCFGR register */ RCC->SRDCFGR = 0x00000000; #endif /* Reset PLLCKSELR register */ RCC->PLLCKSELR = 0x02020200; 8004910: 4b1b ldr r3, [pc, #108] @ (8004980 ) 8004912: 4a1d ldr r2, [pc, #116] @ (8004988 ) 8004914: 629a str r2, [r3, #40] @ 0x28 /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x01FF0000; 8004916: 4b1a ldr r3, [pc, #104] @ (8004980 ) 8004918: 4a1c ldr r2, [pc, #112] @ (800498c ) 800491a: 62da str r2, [r3, #44] @ 0x2c /* Reset PLL1DIVR register */ RCC->PLL1DIVR = 0x01010280; 800491c: 4b18 ldr r3, [pc, #96] @ (8004980 ) 800491e: 4a1c ldr r2, [pc, #112] @ (8004990 ) 8004920: 631a str r2, [r3, #48] @ 0x30 /* Reset PLL1FRACR register */ RCC->PLL1FRACR = 0x00000000; 8004922: 4b17 ldr r3, [pc, #92] @ (8004980 ) 8004924: 2200 movs r2, #0 8004926: 635a str r2, [r3, #52] @ 0x34 /* Reset PLL2DIVR register */ RCC->PLL2DIVR = 0x01010280; 8004928: 4b15 ldr r3, [pc, #84] @ (8004980 ) 800492a: 4a19 ldr r2, [pc, #100] @ (8004990 ) 800492c: 639a str r2, [r3, #56] @ 0x38 /* Reset PLL2FRACR register */ RCC->PLL2FRACR = 0x00000000; 800492e: 4b14 ldr r3, [pc, #80] @ (8004980 ) 8004930: 2200 movs r2, #0 8004932: 63da str r2, [r3, #60] @ 0x3c /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x01010280; 8004934: 4b12 ldr r3, [pc, #72] @ (8004980 ) 8004936: 4a16 ldr r2, [pc, #88] @ (8004990 ) 8004938: 641a str r2, [r3, #64] @ 0x40 /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; 800493a: 4b11 ldr r3, [pc, #68] @ (8004980 ) 800493c: 2200 movs r2, #0 800493e: 645a str r2, [r3, #68] @ 0x44 /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; 8004940: 4b0f ldr r3, [pc, #60] @ (8004980 ) 8004942: 681b ldr r3, [r3, #0] 8004944: 4a0e ldr r2, [pc, #56] @ (8004980 ) 8004946: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800494a: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 800494c: 4b0c ldr r3, [pc, #48] @ (8004980 ) 800494e: 2200 movs r2, #0 8004950: 661a str r2, [r3, #96] @ 0x60 #if (STM32H7_DEV_ID == 0x450UL) /* dual core CM7 or single core line */ if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) 8004952: 4b10 ldr r3, [pc, #64] @ (8004994 ) 8004954: 681a ldr r2, [r3, #0] 8004956: 4b10 ldr r3, [pc, #64] @ (8004998 ) 8004958: 4013 ands r3, r2 800495a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800495e: d202 bcs.n 8004966 { /* if stm32h7 revY*/ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; 8004960: 4b0e ldr r3, [pc, #56] @ (800499c ) 8004962: 2201 movs r2, #1 8004964: 601a str r2, [r3, #0] /* * Disable the FMC bank1 (enabled after reset). * This, prevents CPU speculation access on this bank which blocks the use of FMC during * 24us. During this time the others FMC master (such as LTDC) cannot use it! */ FMC_Bank1_R->BTCR[0] = 0x000030D2; 8004966: 4b0e ldr r3, [pc, #56] @ (80049a0 ) 8004968: f243 02d2 movw r2, #12498 @ 0x30d2 800496c: 601a str r2, [r3, #0] #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ #endif /* USER_VECT_TAB_ADDRESS */ #endif /*DUAL_CORE && CORE_CM4*/ } 800496e: bf00 nop 8004970: 46bd mov sp, r7 8004972: f85d 7b04 ldr.w r7, [sp], #4 8004976: 4770 bx lr 8004978: e000ed00 .word 0xe000ed00 800497c: 52002000 .word 0x52002000 8004980: 58024400 .word 0x58024400 8004984: eaf6ed7f .word 0xeaf6ed7f 8004988: 02020200 .word 0x02020200 800498c: 01ff0000 .word 0x01ff0000 8004990: 01010280 .word 0x01010280 8004994: 5c001000 .word 0x5c001000 8004998: ffff0000 .word 0xffff0000 800499c: 51008108 .word 0x51008108 80049a0: 52004000 .word 0x52004000 080049a4 <__NVIC_SystemReset>: { 80049a4: b480 push {r7} 80049a6: af00 add r7, sp, #0 __ASM volatile ("dsb 0xF":::"memory"); 80049a8: f3bf 8f4f dsb sy } 80049ac: bf00 nop (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 80049ae: 4b06 ldr r3, [pc, #24] @ (80049c8 <__NVIC_SystemReset+0x24>) 80049b0: 68db ldr r3, [r3, #12] 80049b2: f403 62e0 and.w r2, r3, #1792 @ 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80049b6: 4904 ldr r1, [pc, #16] @ (80049c8 <__NVIC_SystemReset+0x24>) 80049b8: 4b04 ldr r3, [pc, #16] @ (80049cc <__NVIC_SystemReset+0x28>) 80049ba: 4313 orrs r3, r2 80049bc: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); 80049be: f3bf 8f4f dsb sy } 80049c2: bf00 nop __NOP(); 80049c4: bf00 nop 80049c6: e7fd b.n 80049c4 <__NVIC_SystemReset+0x20> 80049c8: e000ed00 .word 0xe000ed00 80049cc: 05fa0004 .word 0x05fa0004 080049d0 : uint8_t outputDataBuffer[OUTPUT_DATA_BUFF_SIZE]; uint16_t outputDataBufferPos = 0; extern RNG_HandleTypeDef hrng; void UartTasksInit (void) { 80049d0: b580 push {r7, lr} 80049d2: af00 add r7, sp, #0 uart1TaskData.uartRxBuffer = uart1RxBuffer; 80049d4: 4b24 ldr r3, [pc, #144] @ (8004a68 ) 80049d6: 4a25 ldr r2, [pc, #148] @ (8004a6c ) 80049d8: 601a str r2, [r3, #0] uart1TaskData.uartRxBufferLen = UART1_RX_BUFF_SIZE; 80049da: 4b23 ldr r3, [pc, #140] @ (8004a68 ) 80049dc: f44f 7280 mov.w r2, #256 @ 0x100 80049e0: 809a strh r2, [r3, #4] uart1TaskData.uartTxBuffer = uart1TxBuffer; 80049e2: 4b21 ldr r3, [pc, #132] @ (8004a68 ) 80049e4: 4a22 ldr r2, [pc, #136] @ (8004a70 ) 80049e6: 609a str r2, [r3, #8] uart1TaskData.uartRxBufferLen = UART1_TX_BUFF_SIZE; 80049e8: 4b1f ldr r3, [pc, #124] @ (8004a68 ) 80049ea: f44f 7280 mov.w r2, #256 @ 0x100 80049ee: 809a strh r2, [r3, #4] uart1TaskData.frameData = uart1TaskFrameData; 80049f0: 4b1d ldr r3, [pc, #116] @ (8004a68 ) 80049f2: 4a20 ldr r2, [pc, #128] @ (8004a74 ) 80049f4: 611a str r2, [r3, #16] uart1TaskData.frameDataLen = UART1_RX_BUFF_SIZE; 80049f6: 4b1c ldr r3, [pc, #112] @ (8004a68 ) 80049f8: f44f 7280 mov.w r2, #256 @ 0x100 80049fc: 829a strh r2, [r3, #20] uart1TaskData.huart = &huart1; 80049fe: 4b1a ldr r3, [pc, #104] @ (8004a68 ) 8004a00: 4a1d ldr r2, [pc, #116] @ (8004a78 ) 8004a02: 631a str r2, [r3, #48] @ 0x30 uart1TaskData.uartNumber = 1; 8004a04: 4b18 ldr r3, [pc, #96] @ (8004a68 ) 8004a06: 2201 movs r2, #1 8004a08: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart1TaskData.processDataCb = Uart1ReceivedDataProcessCallback; 8004a0c: 4b16 ldr r3, [pc, #88] @ (8004a68 ) 8004a0e: 4a1b ldr r2, [pc, #108] @ (8004a7c ) 8004a10: 629a str r2, [r3, #40] @ 0x28 uart1TaskData.processRxDataMsgBuffer = NULL; 8004a12: 4b15 ldr r3, [pc, #84] @ (8004a68 ) 8004a14: 2200 movs r2, #0 8004a16: 625a str r2, [r3, #36] @ 0x24 uart8TaskData.uartRxBuffer = uart8RxBuffer; 8004a18: 4b19 ldr r3, [pc, #100] @ (8004a80 ) 8004a1a: 4a1a ldr r2, [pc, #104] @ (8004a84 ) 8004a1c: 601a str r2, [r3, #0] uart8TaskData.uartRxBufferLen = UART8_RX_BUFF_SIZE; 8004a1e: 4b18 ldr r3, [pc, #96] @ (8004a80 ) 8004a20: f44f 7280 mov.w r2, #256 @ 0x100 8004a24: 809a strh r2, [r3, #4] uart8TaskData.uartTxBuffer = uart8TxBuffer; 8004a26: 4b16 ldr r3, [pc, #88] @ (8004a80 ) 8004a28: 4a17 ldr r2, [pc, #92] @ (8004a88 ) 8004a2a: 609a str r2, [r3, #8] uart8TaskData.uartRxBufferLen = UART8_TX_BUFF_SIZE; 8004a2c: 4b14 ldr r3, [pc, #80] @ (8004a80 ) 8004a2e: f44f 7280 mov.w r2, #256 @ 0x100 8004a32: 809a strh r2, [r3, #4] uart8TaskData.frameData = uart8TaskFrameData; 8004a34: 4b12 ldr r3, [pc, #72] @ (8004a80 ) 8004a36: 4a15 ldr r2, [pc, #84] @ (8004a8c ) 8004a38: 611a str r2, [r3, #16] uart8TaskData.frameDataLen = UART8_RX_BUFF_SIZE; 8004a3a: 4b11 ldr r3, [pc, #68] @ (8004a80 ) 8004a3c: f44f 7280 mov.w r2, #256 @ 0x100 8004a40: 829a strh r2, [r3, #20] uart8TaskData.huart = &huart8; 8004a42: 4b0f ldr r3, [pc, #60] @ (8004a80 ) 8004a44: 4a12 ldr r2, [pc, #72] @ (8004a90 ) 8004a46: 631a str r2, [r3, #48] @ 0x30 uart8TaskData.uartNumber = 8; 8004a48: 4b0d ldr r3, [pc, #52] @ (8004a80 ) 8004a4a: 2208 movs r2, #8 8004a4c: f883 2034 strb.w r2, [r3, #52] @ 0x34 uart8TaskData.processDataCb = Uart8ReceivedDataProcessCallback; 8004a50: 4b0b ldr r3, [pc, #44] @ (8004a80 ) 8004a52: 4a10 ldr r2, [pc, #64] @ (8004a94 ) 8004a54: 629a str r2, [r3, #40] @ 0x28 uart8TaskData.processRxDataMsgBuffer = NULL; 8004a56: 4b0a ldr r3, [pc, #40] @ (8004a80 ) 8004a58: 2200 movs r2, #0 8004a5a: 625a str r2, [r3, #36] @ 0x24 #ifdef USE_UART8_INSTEAD_UART1 UartTaskCreate (&uart8TaskData); #else UartTaskCreate (&uart1TaskData); 8004a5c: 4802 ldr r0, [pc, #8] @ (8004a68 ) 8004a5e: f000 f81b bl 8004a98 #endif } 8004a62: bf00 nop 8004a64: bd80 pop {r7, pc} 8004a66: bf00 nop 8004a68: 24000f6c .word 0x24000f6c 8004a6c: 2400096c .word 0x2400096c 8004a70: 24000a6c .word 0x24000a6c 8004a74: 24000b6c .word 0x24000b6c 8004a78: 2400064c .word 0x2400064c 8004a7c: 08005141 .word 0x08005141 8004a80: 24000fa4 .word 0x24000fa4 8004a84: 24000c6c .word 0x24000c6c 8004a88: 24000d6c .word 0x24000d6c 8004a8c: 24000e6c .word 0x24000e6c 8004a90: 240005b8 .word 0x240005b8 8004a94: 08005125 .word 0x08005125 08004a98 : void UartTaskCreate (UartTaskData* uartTaskData) { 8004a98: b580 push {r7, lr} 8004a9a: b08c sub sp, #48 @ 0x30 8004a9c: af00 add r7, sp, #0 8004a9e: 6078 str r0, [r7, #4] osThreadAttr_t osThreadAttrRxUart = { 0 }; 8004aa0: f107 030c add.w r3, r7, #12 8004aa4: 2224 movs r2, #36 @ 0x24 8004aa6: 2100 movs r1, #0 8004aa8: 4618 mov r0, r3 8004aaa: f013 fc35 bl 8018318 osThreadAttrRxUart.stack_size = configMINIMAL_STACK_SIZE * 2; 8004aae: f44f 6380 mov.w r3, #1024 @ 0x400 8004ab2: 623b str r3, [r7, #32] osThreadAttrRxUart.priority = (osPriority_t)osPriorityHigh; 8004ab4: 2328 movs r3, #40 @ 0x28 8004ab6: 627b str r3, [r7, #36] @ 0x24 uartTaskData->uartRecieveTaskHandle = osThreadNew (UartRxTask, uartTaskData, &osThreadAttrRxUart); 8004ab8: f107 030c add.w r3, r7, #12 8004abc: 461a mov r2, r3 8004abe: 6879 ldr r1, [r7, #4] 8004ac0: 4804 ldr r0, [pc, #16] @ (8004ad4 ) 8004ac2: f00f fad1 bl 8014068 8004ac6: 4602 mov r2, r0 8004ac8: 687b ldr r3, [r7, #4] 8004aca: 619a str r2, [r3, #24] } 8004acc: bf00 nop 8004ace: 3730 adds r7, #48 @ 0x30 8004ad0: 46bd mov sp, r7 8004ad2: bd80 pop {r7, pc} 8004ad4: 08004bed .word 0x08004bed 08004ad8 : void HAL_UART_RxCpltCallback (UART_HandleTypeDef* huart) { 8004ad8: b480 push {r7} 8004ada: b083 sub sp, #12 8004adc: af00 add r7, sp, #0 8004ade: 6078 str r0, [r7, #4] } 8004ae0: bf00 nop 8004ae2: 370c adds r7, #12 8004ae4: 46bd mov sp, r7 8004ae6: f85d 7b04 ldr.w r7, [sp], #4 8004aea: 4770 bx lr 08004aec : void HAL_UARTEx_RxEventCallback (UART_HandleTypeDef* huart, uint16_t Size) { 8004aec: b580 push {r7, lr} 8004aee: b082 sub sp, #8 8004af0: af00 add r7, sp, #0 8004af2: 6078 str r0, [r7, #4] 8004af4: 460b mov r3, r1 8004af6: 807b strh r3, [r7, #2] if (huart->Instance == USART1) { 8004af8: 687b ldr r3, [r7, #4] 8004afa: 681b ldr r3, [r3, #0] 8004afc: 4a0c ldr r2, [pc, #48] @ (8004b30 ) 8004afe: 4293 cmp r3, r2 8004b00: d106 bne.n 8004b10 HandleUartRxCallback (&uart1TaskData, huart, Size); 8004b02: 887b ldrh r3, [r7, #2] 8004b04: 461a mov r2, r3 8004b06: 6879 ldr r1, [r7, #4] 8004b08: 480a ldr r0, [pc, #40] @ (8004b34 ) 8004b0a: f000 f823 bl 8004b54 } else if (huart->Instance == UART8) { HandleUartRxCallback (&uart8TaskData, huart, Size); } } 8004b0e: e00a b.n 8004b26 } else if (huart->Instance == UART8) { 8004b10: 687b ldr r3, [r7, #4] 8004b12: 681b ldr r3, [r3, #0] 8004b14: 4a08 ldr r2, [pc, #32] @ (8004b38 ) 8004b16: 4293 cmp r3, r2 8004b18: d105 bne.n 8004b26 HandleUartRxCallback (&uart8TaskData, huart, Size); 8004b1a: 887b ldrh r3, [r7, #2] 8004b1c: 461a mov r2, r3 8004b1e: 6879 ldr r1, [r7, #4] 8004b20: 4806 ldr r0, [pc, #24] @ (8004b3c ) 8004b22: f000 f817 bl 8004b54 } 8004b26: bf00 nop 8004b28: 3708 adds r7, #8 8004b2a: 46bd mov sp, r7 8004b2c: bd80 pop {r7, pc} 8004b2e: bf00 nop 8004b30: 40011000 .word 0x40011000 8004b34: 24000f6c .word 0x24000f6c 8004b38: 40007c00 .word 0x40007c00 8004b3c: 24000fa4 .word 0x24000fa4 08004b40 : void HAL_UART_TxCpltCallback (UART_HandleTypeDef* huart) { 8004b40: b480 push {r7} 8004b42: b083 sub sp, #12 8004b44: af00 add r7, sp, #0 8004b46: 6078 str r0, [r7, #4] if (huart->Instance == UART8) { } } 8004b48: bf00 nop 8004b4a: 370c adds r7, #12 8004b4c: 46bd mov sp, r7 8004b4e: f85d 7b04 ldr.w r7, [sp], #4 8004b52: 4770 bx lr 08004b54 : void HandleUartRxCallback (UartTaskData* uartTaskData, UART_HandleTypeDef* huart, uint16_t Size) { 8004b54: b580 push {r7, lr} 8004b56: b088 sub sp, #32 8004b58: af02 add r7, sp, #8 8004b5a: 60f8 str r0, [r7, #12] 8004b5c: 60b9 str r1, [r7, #8] 8004b5e: 4613 mov r3, r2 8004b60: 80fb strh r3, [r7, #6] BaseType_t pxHigherPriorityTaskWoken = pdFALSE; 8004b62: 2300 movs r3, #0 8004b64: 617b str r3, [r7, #20] osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004b66: 68fb ldr r3, [r7, #12] 8004b68: 6a1b ldr r3, [r3, #32] 8004b6a: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004b6e: 4618 mov r0, r3 8004b70: f00f fca5 bl 80144be memcpy (&(uartTaskData->frameData[uartTaskData->frameBytesCount]), uartTaskData->uartRxBuffer, Size); 8004b74: 68fb ldr r3, [r7, #12] 8004b76: 691b ldr r3, [r3, #16] 8004b78: 68fa ldr r2, [r7, #12] 8004b7a: 8ad2 ldrh r2, [r2, #22] 8004b7c: 1898 adds r0, r3, r2 8004b7e: 68fb ldr r3, [r7, #12] 8004b80: 681b ldr r3, [r3, #0] 8004b82: 88fa ldrh r2, [r7, #6] 8004b84: 4619 mov r1, r3 8004b86: f013 fc51 bl 801842c uartTaskData->frameBytesCount += Size; 8004b8a: 68fb ldr r3, [r7, #12] 8004b8c: 8ada ldrh r2, [r3, #22] 8004b8e: 88fb ldrh r3, [r7, #6] 8004b90: 4413 add r3, r2 8004b92: b29a uxth r2, r3 8004b94: 68fb ldr r3, [r7, #12] 8004b96: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 8004b98: 68fb ldr r3, [r7, #12] 8004b9a: 6a1b ldr r3, [r3, #32] 8004b9c: 4618 mov r0, r3 8004b9e: f00f fcd9 bl 8014554 xTaskNotifyFromISR (uartTaskData->uartRecieveTaskHandle, Size, eSetValueWithOverwrite, &pxHigherPriorityTaskWoken); 8004ba2: 68fb ldr r3, [r7, #12] 8004ba4: 6998 ldr r0, [r3, #24] 8004ba6: 88f9 ldrh r1, [r7, #6] 8004ba8: f107 0314 add.w r3, r7, #20 8004bac: 9300 str r3, [sp, #0] 8004bae: 2300 movs r3, #0 8004bb0: 2203 movs r2, #3 8004bb2: f012 f9c9 bl 8016f48 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004bb6: 68fb ldr r3, [r7, #12] 8004bb8: 6b18 ldr r0, [r3, #48] @ 0x30 8004bba: 68fb ldr r3, [r7, #12] 8004bbc: 6819 ldr r1, [r3, #0] 8004bbe: 68fb ldr r3, [r7, #12] 8004bc0: 889b ldrh r3, [r3, #4] 8004bc2: 461a mov r2, r3 8004bc4: f00f f923 bl 8013e0e portEND_SWITCHING_ISR (pxHigherPriorityTaskWoken); 8004bc8: 697b ldr r3, [r7, #20] 8004bca: 2b00 cmp r3, #0 8004bcc: d007 beq.n 8004bde 8004bce: 4b06 ldr r3, [pc, #24] @ (8004be8 ) 8004bd0: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8004bd4: 601a str r2, [r3, #0] 8004bd6: f3bf 8f4f dsb sy 8004bda: f3bf 8f6f isb sy } 8004bde: bf00 nop 8004be0: 3718 adds r7, #24 8004be2: 46bd mov sp, r7 8004be4: bd80 pop {r7, pc} 8004be6: bf00 nop 8004be8: e000ed04 .word 0xe000ed04 08004bec : void UartRxTask (void* argument) { 8004bec: b580 push {r7, lr} 8004bee: b0d2 sub sp, #328 @ 0x148 8004bf0: af02 add r7, sp, #8 8004bf2: f507 73a0 add.w r3, r7, #320 @ 0x140 8004bf6: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004bfa: 6018 str r0, [r3, #0] UartTaskData* uartTaskData = (UartTaskData*)argument; 8004bfc: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c00: f5a3 739e sub.w r3, r3, #316 @ 0x13c 8004c04: 681b ldr r3, [r3, #0] 8004c06: f8c7 312c str.w r3, [r7, #300] @ 0x12c SerialProtocolFrameData spFrameData = { 0 }; 8004c0a: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c0e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004c12: 4618 mov r0, r3 8004c14: f44f 7386 mov.w r3, #268 @ 0x10c 8004c18: 461a mov r2, r3 8004c1a: 2100 movs r1, #0 8004c1c: f013 fb7c bl 8018318 uint32_t bytesRec = 0; 8004c20: f507 73a0 add.w r3, r7, #320 @ 0x140 8004c24: f5a3 739a sub.w r3, r3, #308 @ 0x134 8004c28: 2200 movs r2, #0 8004c2a: 601a str r2, [r3, #0] uint32_t crc = 0; 8004c2c: 2300 movs r3, #0 8004c2e: f8c7 3128 str.w r3, [r7, #296] @ 0x128 uint16_t frameCommandRaw = 0x0000; 8004c32: 2300 movs r3, #0 8004c34: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 uint16_t frameBytesCount = 0; 8004c38: 2300 movs r3, #0 8004c3a: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 uint16_t frameCrc = 0; 8004c3e: 2300 movs r3, #0 8004c40: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 uint16_t frameTotalLength = 0; 8004c44: 2300 movs r3, #0 8004c46: f8a7 313e strh.w r3, [r7, #318] @ 0x13e uint16_t dataToSend = 0; 8004c4a: 2300 movs r3, #0 8004c4c: f8a7 313c strh.w r3, [r7, #316] @ 0x13c portBASE_TYPE crcPass = pdFAIL; 8004c50: 2300 movs r3, #0 8004c52: f8c7 3138 str.w r3, [r7, #312] @ 0x138 portBASE_TYPE proceed = pdFALSE; 8004c56: 2300 movs r3, #0 8004c58: f8c7 3134 str.w r3, [r7, #308] @ 0x134 portBASE_TYPE frameTimeout = pdFAIL; 8004c5c: 2300 movs r3, #0 8004c5e: f8c7 311c str.w r3, [r7, #284] @ 0x11c enum SerialReceiverStates receverState = srWaitForHeader; 8004c62: 2300 movs r3, #0 8004c64: f887 3133 strb.w r3, [r7, #307] @ 0x133 uartTaskData->rxDataBufferMutex = osMutexNew (NULL); 8004c68: 2000 movs r0, #0 8004c6a: f00f fba2 bl 80143b2 8004c6e: 4602 mov r2, r0 8004c70: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c74: 621a str r2, [r3, #32] HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004c76: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c7a: 6b18 ldr r0, [r3, #48] @ 0x30 8004c7c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c80: 6819 ldr r1, [r3, #0] 8004c82: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004c86: 889b ldrh r3, [r3, #4] 8004c88: 461a mov r2, r3 8004c8a: f00f f8c0 bl 8013e0e while (pdTRUE) { frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 8004c8e: f107 020c add.w r2, r7, #12 8004c92: f44f 63fa mov.w r3, #2000 @ 0x7d0 8004c96: 2100 movs r1, #0 8004c98: 2000 movs r0, #0 8004c9a: f012 f833 bl 8016d04 8004c9e: 4603 mov r3, r0 8004ca0: 2b00 cmp r3, #0 8004ca2: bf0c ite eq 8004ca4: 2301 moveq r3, #1 8004ca6: 2300 movne r3, #0 8004ca8: b2db uxtb r3, r3 8004caa: f8c7 311c str.w r3, [r7, #284] @ 0x11c osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004cae: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cb2: 6a1b ldr r3, [r3, #32] 8004cb4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004cb8: 4618 mov r0, r3 8004cba: f00f fc00 bl 80144be frameBytesCount = uartTaskData->frameBytesCount; 8004cbe: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004cc2: 8adb ldrh r3, [r3, #22] 8004cc4: f8a7 3124 strh.w r3, [r7, #292] @ 0x124 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004cc8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ccc: 6a1b ldr r3, [r3, #32] 8004cce: 4618 mov r0, r3 8004cd0: f00f fc40 bl 8014554 if ((frameTimeout == pdTRUE) && (frameBytesCount > 0)) { 8004cd4: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004cd8: 2b01 cmp r3, #1 8004cda: d10a bne.n 8004cf2 8004cdc: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004ce0: 2b00 cmp r3, #0 8004ce2: d006 beq.n 8004cf2 receverState = srFail; 8004ce4: 2304 movs r3, #4 8004ce6: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdTRUE; 8004cea: 2301 movs r3, #1 8004cec: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004cf0: e01b b.n 8004d2a } else { if (frameTimeout == pdFALSE) { 8004cf2: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004cf6: 2b00 cmp r3, #0 8004cf8: d103 bne.n 8004d02 proceed = pdTRUE; 8004cfa: 2301 movs r3, #1 8004cfc: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004d00: e206 b.n 8005110 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX bytes received: %ld\n", uartTaskData->uartNumber, bytesRec); #endif } else { if (uartTaskData->huart->RxState == HAL_UART_STATE_READY) { 8004d02: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d06: 6b1b ldr r3, [r3, #48] @ 0x30 8004d08: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004d0c: 2b20 cmp r3, #32 8004d0e: f040 81ff bne.w 8005110 HAL_UARTEx_ReceiveToIdle_IT (uartTaskData->huart, uartTaskData->uartRxBuffer, uartTaskData->uartRxBufferLen); 8004d12: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d16: 6b18 ldr r0, [r3, #48] @ 0x30 8004d18: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d1c: 6819 ldr r1, [r3, #0] 8004d1e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d22: 889b ldrh r3, [r3, #4] 8004d24: 461a mov r2, r3 8004d26: f00f f872 bl 8013e0e } } } while (proceed) { 8004d2a: e1f1 b.n 8005110 switch (receverState) { 8004d2c: f897 3133 ldrb.w r3, [r7, #307] @ 0x133 8004d30: 2b04 cmp r3, #4 8004d32: f200 81c8 bhi.w 80050c6 8004d36: a201 add r2, pc, #4 @ (adr r2, 8004d3c ) 8004d38: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8004d3c: 08004d51 .word 0x08004d51 8004d40: 08004eb3 .word 0x08004eb3 8004d44: 08004e97 .word 0x08004e97 8004d48: 08004f43 .word 0x08004f43 8004d4c: 08004fef .word 0x08004fef case srWaitForHeader: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004d50: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d54: 6a1b ldr r3, [r3, #32] 8004d56: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004d5a: 4618 mov r0, r3 8004d5c: f00f fbaf bl 80144be if (uartTaskData->frameData[0] == FRAME_INDICATOR) { 8004d60: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d64: 691b ldr r3, [r3, #16] 8004d66: 781b ldrb r3, [r3, #0] 8004d68: 2baa cmp r3, #170 @ 0xaa 8004d6a: f040 8082 bne.w 8004e72 if (frameBytesCount > FRAME_ID_LENGTH) { 8004d6e: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004d72: 2b02 cmp r3, #2 8004d74: d914 bls.n 8004da0 spFrameData.frameHeader.frameId = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_ID_LENGTH - FRAME_COMMAND_LENGTH])); 8004d76: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d7a: 691b ldr r3, [r3, #16] 8004d7c: 3302 adds r3, #2 8004d7e: 781b ldrb r3, [r3, #0] 8004d80: 021b lsls r3, r3, #8 8004d82: b21a sxth r2, r3 8004d84: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004d88: 691b ldr r3, [r3, #16] 8004d8a: 3301 adds r3, #1 8004d8c: 781b ldrb r3, [r3, #0] 8004d8e: b21b sxth r3, r3 8004d90: 4313 orrs r3, r2 8004d92: b21b sxth r3, r3 8004d94: b29a uxth r2, r3 spFrameData.frameHeader.frameId = 8004d96: f507 73a0 add.w r3, r7, #320 @ 0x140 8004d9a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004d9e: 801a strh r2, [r3, #0] } if (frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH) { 8004da0: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004da4: 2b04 cmp r3, #4 8004da6: d923 bls.n 8004df0 frameCommandRaw = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH - FRAME_COMMAND_LENGTH])); 8004da8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004dac: 691b ldr r3, [r3, #16] 8004dae: 3304 adds r3, #4 8004db0: 781b ldrb r3, [r3, #0] 8004db2: 021b lsls r3, r3, #8 8004db4: b21a sxth r2, r3 8004db6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004dba: 691b ldr r3, [r3, #16] 8004dbc: 3303 adds r3, #3 8004dbe: 781b ldrb r3, [r3, #0] 8004dc0: b21b sxth r3, r3 8004dc2: 4313 orrs r3, r2 8004dc4: b21b sxth r3, r3 8004dc6: f8a7 3126 strh.w r3, [r7, #294] @ 0x126 spFrameData.frameHeader.frameCommand = (SerialProtocolCommands)(frameCommandRaw & 0x7FFF); 8004dca: f8b7 3126 ldrh.w r3, [r7, #294] @ 0x126 8004dce: b2da uxtb r2, r3 8004dd0: f507 73a0 add.w r3, r7, #320 @ 0x140 8004dd4: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004dd8: 709a strb r2, [r3, #2] spFrameData.frameHeader.isResponseFrame = (frameCommandRaw & 0x8000) != 0 ? pdTRUE : pdFALSE; 8004dda: f9b7 3126 ldrsh.w r3, [r7, #294] @ 0x126 8004dde: 13db asrs r3, r3, #15 8004de0: b21b sxth r3, r3 8004de2: f003 0201 and.w r2, r3, #1 8004de6: f507 73a0 add.w r3, r7, #320 @ 0x140 8004dea: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004dee: 609a str r2, [r3, #8] } if ((frameBytesCount > FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH) && ((spFrameData.frameHeader.frameCommand & 0x8000) != 0)) { 8004df0: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004df4: 2b05 cmp r3, #5 8004df6: d913 bls.n 8004e20 8004df8: f507 73a0 add.w r3, r7, #320 @ 0x140 8004dfc: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e00: 789b ldrb r3, [r3, #2] 8004e02: f403 4300 and.w r3, r3, #32768 @ 0x8000 8004e06: 2b00 cmp r3, #0 8004e08: d00a beq.n 8004e20 spFrameData.frameHeader.respStatus = (SerialProtocolRespStatus)(uartTaskData->frameData[FRAME_ID_LENGTH + FRAME_COMMAND_LENGTH + FRAME_RESP_STAT_LENGTH]); 8004e0a: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e0e: 691b ldr r3, [r3, #16] 8004e10: 3305 adds r3, #5 8004e12: 781b ldrb r3, [r3, #0] 8004e14: b25a sxtb r2, r3 8004e16: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e1a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e1e: 70da strb r2, [r3, #3] } if (frameBytesCount >= FRAME_HEADER_LENGTH) { 8004e20: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004e24: 2b07 cmp r3, #7 8004e26: d920 bls.n 8004e6a spFrameData.frameHeader.frameDataLength = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[FRAME_HEADER_LENGTH - FRAME_RESP_STAT_LENGTH - FRAME_DATALEN_LENGTH])); 8004e28: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e2c: 691b ldr r3, [r3, #16] 8004e2e: 3306 adds r3, #6 8004e30: 781b ldrb r3, [r3, #0] 8004e32: 021b lsls r3, r3, #8 8004e34: b21a sxth r2, r3 8004e36: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e3a: 691b ldr r3, [r3, #16] 8004e3c: 3305 adds r3, #5 8004e3e: 781b ldrb r3, [r3, #0] 8004e40: b21b sxth r3, r3 8004e42: 4313 orrs r3, r2 8004e44: b21b sxth r3, r3 8004e46: b29a uxth r2, r3 8004e48: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e4c: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e50: 809a strh r2, [r3, #4] frameTotalLength = FRAME_HEADER_LENGTH + spFrameData.frameHeader.frameDataLength + FRAME_CRC_LENGTH; 8004e52: f507 73a0 add.w r3, r7, #320 @ 0x140 8004e56: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004e5a: 889b ldrh r3, [r3, #4] 8004e5c: 330a adds r3, #10 8004e5e: f8a7 313e strh.w r3, [r7, #318] @ 0x13e receverState = srRecieveData; 8004e62: 2302 movs r3, #2 8004e64: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004e68: e00e b.n 8004e88 } else { proceed = pdFALSE; 8004e6a: 2300 movs r3, #0 8004e6c: f8c7 3134 str.w r3, [r7, #308] @ 0x134 8004e70: e00a b.n 8004e88 } } else { if (frameBytesCount > 0) { 8004e72: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8004e76: 2b00 cmp r3, #0 8004e78: d003 beq.n 8004e82 receverState = srFail; 8004e7a: 2304 movs r3, #4 8004e7c: f887 3133 strb.w r3, [r7, #307] @ 0x133 8004e80: e002 b.n 8004e88 } else { proceed = pdFALSE; 8004e82: 2300 movs r3, #0 8004e84: f8c7 3134 str.w r3, [r7, #308] @ 0x134 } } osMutexRelease (uartTaskData->rxDataBufferMutex); 8004e88: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004e8c: 6a1b ldr r3, [r3, #32] 8004e8e: 4618 mov r0, r3 8004e90: f00f fb60 bl 8014554 break; 8004e94: e13c b.n 8005110 case srRecieveData: if (frameBytesCount >= frameTotalLength) { 8004e96: f8b7 2124 ldrh.w r2, [r7, #292] @ 0x124 8004e9a: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004e9e: 429a cmp r2, r3 8004ea0: d303 bcc.n 8004eaa receverState = srCheckCrc; 8004ea2: 2301 movs r3, #1 8004ea4: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { proceed = pdFALSE; } break; 8004ea8: e132 b.n 8005110 proceed = pdFALSE; 8004eaa: 2300 movs r3, #0 8004eac: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 8004eb0: e12e b.n 8005110 case srCheckCrc: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004eb2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004eb6: 6a1b ldr r3, [r3, #32] 8004eb8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004ebc: 4618 mov r0, r3 8004ebe: f00f fafe bl 80144be frameCrc = CONVERT_BYTES_TO_SHORT_WORD (&(uartTaskData->frameData[frameTotalLength - FRAME_CRC_LENGTH])); 8004ec2: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ec6: 691a ldr r2, [r3, #16] 8004ec8: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004ecc: 3b01 subs r3, #1 8004ece: 4413 add r3, r2 8004ed0: 781b ldrb r3, [r3, #0] 8004ed2: 021b lsls r3, r3, #8 8004ed4: b21a sxth r2, r3 8004ed6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004eda: 6919 ldr r1, [r3, #16] 8004edc: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004ee0: 3b02 subs r3, #2 8004ee2: 440b add r3, r1 8004ee4: 781b ldrb r3, [r3, #0] 8004ee6: b21b sxth r3, r3 8004ee8: 4313 orrs r3, r2 8004eea: b21b sxth r3, r3 8004eec: f8a7 3122 strh.w r3, [r7, #290] @ 0x122 crc = HAL_CRC_Calculate (&hcrc, (uint32_t*)(uartTaskData->frameData), frameTotalLength - FRAME_CRC_LENGTH); 8004ef0: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004ef4: 6919 ldr r1, [r3, #16] 8004ef6: f8b7 313e ldrh.w r3, [r7, #318] @ 0x13e 8004efa: 3b02 subs r3, #2 8004efc: 461a mov r2, r3 8004efe: 4887 ldr r0, [pc, #540] @ (800511c ) 8004f00: f002 ff3a bl 8007d78 8004f04: f8c7 0128 str.w r0, [r7, #296] @ 0x128 osMutexRelease (uartTaskData->rxDataBufferMutex); 8004f08: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f0c: 6a1b ldr r3, [r3, #32] 8004f0e: 4618 mov r0, r3 8004f10: f00f fb20 bl 8014554 crcPass = frameCrc == crc; 8004f14: f8b7 3122 ldrh.w r3, [r7, #290] @ 0x122 8004f18: f8d7 2128 ldr.w r2, [r7, #296] @ 0x128 8004f1c: 429a cmp r2, r3 8004f1e: bf0c ite eq 8004f20: 2301 moveq r3, #1 8004f22: 2300 movne r3, #0 8004f24: b2db uxtb r3, r3 8004f26: f8c7 3138 str.w r3, [r7, #312] @ 0x138 if (crcPass) { 8004f2a: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 8004f2e: 2b00 cmp r3, #0 8004f30: d003 beq.n 8004f3a #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC PASS\n", uartTaskData->uartNumber); #endif receverState = srExecuteCmd; 8004f32: 2303 movs r3, #3 8004f34: f887 3133 strb.w r3, [r7, #307] @ 0x133 } else { receverState = srFail; } break; 8004f38: e0ea b.n 8005110 receverState = srFail; 8004f3a: 2304 movs r3, #4 8004f3c: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004f40: e0e6 b.n 8005110 case srExecuteCmd: if ((uartTaskData->processDataCb != NULL) || (uartTaskData->processRxDataMsgBuffer != NULL)) { 8004f42: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f46: 6a9b ldr r3, [r3, #40] @ 0x28 8004f48: 2b00 cmp r3, #0 8004f4a: d104 bne.n 8004f56 8004f4c: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f50: 6a5b ldr r3, [r3, #36] @ 0x24 8004f52: 2b00 cmp r3, #0 8004f54: d01e beq.n 8004f94 osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 8004f56: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f5a: 6a1b ldr r3, [r3, #32] 8004f5c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8004f60: 4618 mov r0, r3 8004f62: f00f faac bl 80144be memcpy (spFrameData.dataBuffer, &(uartTaskData->frameData[FRAME_HEADER_LENGTH]), spFrameData.frameHeader.frameDataLength); 8004f66: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f6a: 691b ldr r3, [r3, #16] 8004f6c: f103 0108 add.w r1, r3, #8 8004f70: f507 73a0 add.w r3, r7, #320 @ 0x140 8004f74: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004f78: 889b ldrh r3, [r3, #4] 8004f7a: 461a mov r2, r3 8004f7c: f107 0310 add.w r3, r7, #16 8004f80: 330c adds r3, #12 8004f82: 4618 mov r0, r3 8004f84: f013 fa52 bl 801842c osMutexRelease (uartTaskData->rxDataBufferMutex); 8004f88: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f8c: 6a1b ldr r3, [r3, #32] 8004f8e: 4618 mov r0, r3 8004f90: f00f fae0 bl 8014554 } if (uartTaskData->processRxDataMsgBuffer != NULL) { 8004f94: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004f98: 6a5b ldr r3, [r3, #36] @ 0x24 8004f9a: 2b00 cmp r3, #0 8004f9c: d015 beq.n 8004fca if (xMessageBufferSend (uartTaskData->processRxDataMsgBuffer, &spFrameData, sizeof (SerialProtocolFrameHeader) + spFrameData.frameHeader.frameDataLength, pdMS_TO_TICKS (200)) == pdFALSE) { 8004f9e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fa2: 6a58 ldr r0, [r3, #36] @ 0x24 8004fa4: f507 73a0 add.w r3, r7, #320 @ 0x140 8004fa8: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8004fac: 889b ldrh r3, [r3, #4] 8004fae: f103 020c add.w r2, r3, #12 8004fb2: f107 0110 add.w r1, r7, #16 8004fb6: 23c8 movs r3, #200 @ 0xc8 8004fb8: f010 fcee bl 8015998 8004fbc: 4603 mov r3, r0 8004fbe: 2b00 cmp r3, #0 8004fc0: d103 bne.n 8004fca receverState = srFail; 8004fc2: 2304 movs r3, #4 8004fc4: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004fc8: e0a2 b.n 8005110 } } if (uartTaskData->processDataCb != NULL) { 8004fca: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fce: 6a9b ldr r3, [r3, #40] @ 0x28 8004fd0: 2b00 cmp r3, #0 8004fd2: d008 beq.n 8004fe6 uartTaskData->processDataCb (uartTaskData, &spFrameData); 8004fd4: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8004fd8: 6a9b ldr r3, [r3, #40] @ 0x28 8004fda: f107 0210 add.w r2, r7, #16 8004fde: 4611 mov r1, r2 8004fe0: f8d7 012c ldr.w r0, [r7, #300] @ 0x12c 8004fe4: 4798 blx r3 } receverState = srFinish; 8004fe6: 2305 movs r3, #5 8004fe8: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 8004fec: e090 b.n 8005110 case srFail: dataToSend = 0; 8004fee: 2300 movs r3, #0 8004ff0: f8a7 313c strh.w r3, [r7, #316] @ 0x13c if ((frameTimeout == pdTRUE) && (frameBytesCount > 2)) { 8004ff4: f8d7 311c ldr.w r3, [r7, #284] @ 0x11c 8004ff8: 2b01 cmp r3, #1 8004ffa: d11c bne.n 8005036 8004ffc: f8b7 3124 ldrh.w r3, [r7, #292] @ 0x124 8005000: 2b02 cmp r3, #2 8005002: d918 bls.n 8005036 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spTimeout, NULL, 0); 8005004: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005008: 6898 ldr r0, [r3, #8] 800500a: f507 73a0 add.w r3, r7, #320 @ 0x140 800500e: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005012: 8819 ldrh r1, [r3, #0] 8005014: f507 73a0 add.w r3, r7, #320 @ 0x140 8005018: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800501c: 789a ldrb r2, [r3, #2] 800501e: 2300 movs r3, #0 8005020: 9301 str r3, [sp, #4] 8005022: 2300 movs r3, #0 8005024: 9300 str r3, [sp, #0] 8005026: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 800502a: f7fe fd57 bl 8003adc 800502e: 4603 mov r3, r0 8005030: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 8005034: e034 b.n 80050a0 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: RX data receiver timeout!\n", uartTaskData->uartNumber); #endif } else if (!crcPass) { 8005036: f8d7 3138 ldr.w r3, [r7, #312] @ 0x138 800503a: 2b00 cmp r3, #0 800503c: d118 bne.n 8005070 dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spCrcFail, NULL, 0); 800503e: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005042: 6898 ldr r0, [r3, #8] 8005044: f507 73a0 add.w r3, r7, #320 @ 0x140 8005048: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800504c: 8819 ldrh r1, [r3, #0] 800504e: f507 73a0 add.w r3, r7, #320 @ 0x140 8005052: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005056: 789a ldrb r2, [r3, #2] 8005058: 2300 movs r3, #0 800505a: 9301 str r3, [sp, #4] 800505c: 2300 movs r3, #0 800505e: 9300 str r3, [sp, #0] 8005060: f06f 0301 mvn.w r3, #1 8005064: f7fe fd3a bl 8003adc 8005068: 4603 mov r3, r0 800506a: f8a7 313c strh.w r3, [r7, #316] @ 0x13c 800506e: e017 b.n 80050a0 #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: Frame CRC FAIL\n", uartTaskData->uartNumber); #endif } else { dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData.frameHeader.frameId, spFrameData.frameHeader.frameCommand, spInternalError, NULL, 0); 8005070: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 8005074: 6898 ldr r0, [r3, #8] 8005076: f507 73a0 add.w r3, r7, #320 @ 0x140 800507a: f5a3 7398 sub.w r3, r3, #304 @ 0x130 800507e: 8819 ldrh r1, [r3, #0] 8005080: f507 73a0 add.w r3, r7, #320 @ 0x140 8005084: f5a3 7398 sub.w r3, r3, #304 @ 0x130 8005088: 789a ldrb r2, [r3, #2] 800508a: 2300 movs r3, #0 800508c: 9301 str r3, [sp, #4] 800508e: 2300 movs r3, #0 8005090: 9300 str r3, [sp, #0] 8005092: f06f 0303 mvn.w r3, #3 8005096: f7fe fd21 bl 8003adc 800509a: 4603 mov r3, r0 800509c: f8a7 313c strh.w r3, [r7, #316] @ 0x13c } if (dataToSend > 0) { 80050a0: f8b7 313c ldrh.w r3, [r7, #316] @ 0x13c 80050a4: 2b00 cmp r3, #0 80050a6: d00a beq.n 80050be HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 80050a8: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050ac: 6b18 ldr r0, [r3, #48] @ 0x30 80050ae: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050b2: 689b ldr r3, [r3, #8] 80050b4: f8b7 213c ldrh.w r2, [r7, #316] @ 0x13c 80050b8: 4619 mov r1, r3 80050ba: f00c f9d3 bl 8011464 } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", dataToSend, uartTaskData->uartNumber); #endif receverState = srFinish; 80050be: 2305 movs r3, #5 80050c0: f887 3133 strb.w r3, [r7, #307] @ 0x133 break; 80050c4: e024 b.n 8005110 case srFinish: default: osMutexAcquire (uartTaskData->rxDataBufferMutex, osWaitForever); 80050c6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050ca: 6a1b ldr r3, [r3, #32] 80050cc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80050d0: 4618 mov r0, r3 80050d2: f00f f9f4 bl 80144be uartTaskData->frameBytesCount = 0; 80050d6: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050da: 2200 movs r2, #0 80050dc: 82da strh r2, [r3, #22] osMutexRelease (uartTaskData->rxDataBufferMutex); 80050de: f8d7 312c ldr.w r3, [r7, #300] @ 0x12c 80050e2: 6a1b ldr r3, [r3, #32] 80050e4: 4618 mov r0, r3 80050e6: f00f fa35 bl 8014554 spFrameData.frameHeader.frameCommand = spUnknown; 80050ea: f507 73a0 add.w r3, r7, #320 @ 0x140 80050ee: f5a3 7398 sub.w r3, r3, #304 @ 0x130 80050f2: 2212 movs r2, #18 80050f4: 709a strb r2, [r3, #2] frameTotalLength = 0; 80050f6: 2300 movs r3, #0 80050f8: f8a7 313e strh.w r3, [r7, #318] @ 0x13e outputDataBufferPos = 0; 80050fc: 4b08 ldr r3, [pc, #32] @ (8005120 ) 80050fe: 2200 movs r2, #0 8005100: 801a strh r2, [r3, #0] receverState = srWaitForHeader; 8005102: 2300 movs r3, #0 8005104: f887 3133 strb.w r3, [r7, #307] @ 0x133 proceed = pdFALSE; 8005108: 2300 movs r3, #0 800510a: f8c7 3134 str.w r3, [r7, #308] @ 0x134 break; 800510e: bf00 nop while (proceed) { 8005110: f8d7 3134 ldr.w r3, [r7, #308] @ 0x134 8005114: 2b00 cmp r3, #0 8005116: f47f ae09 bne.w 8004d2c frameTimeout = !(xTaskNotifyWait (0, 0, &bytesRec, pdMS_TO_TICKS (FRAME_TIMEOUT_MS))); 800511a: e5b8 b.n 8004c8e 800511c: 240003e0 .word 0x240003e0 8005120: 2400105c .word 0x2400105c 08005124 : } } } } void Uart8ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8005124: b580 push {r7, lr} 8005126: b082 sub sp, #8 8005128: af00 add r7, sp, #0 800512a: 6078 str r0, [r7, #4] 800512c: 6039 str r1, [r7, #0] Uart1ReceivedDataProcessCallback (arg, spFrameData); 800512e: 6839 ldr r1, [r7, #0] 8005130: 6878 ldr r0, [r7, #4] 8005132: f000 f805 bl 8005140 } 8005136: bf00 nop 8005138: 3708 adds r7, #8 800513a: 46bd mov sp, r7 800513c: bd80 pop {r7, pc} ... 08005140 : void Uart1ReceivedDataProcessCallback (void* arg, SerialProtocolFrameData* spFrameData) { 8005140: b590 push {r4, r7, lr} 8005142: b0ad sub sp, #180 @ 0xb4 8005144: af06 add r7, sp, #24 8005146: 6078 str r0, [r7, #4] 8005148: 6039 str r1, [r7, #0] UartTaskData* uartTaskData = (UartTaskData*)arg; 800514a: 687b ldr r3, [r7, #4] 800514c: 677b str r3, [r7, #116] @ 0x74 uint16_t dataToSend = 0; 800514e: 2300 movs r3, #0 8005150: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 outputDataBufferPos = 0; 8005154: 4b64 ldr r3, [pc, #400] @ (80052e8 ) 8005156: 2200 movs r2, #0 8005158: 801a strh r2, [r3, #0] uint16_t inputDataBufferPos = 0; 800515a: 2300 movs r3, #0 800515c: f8a7 3044 strh.w r3, [r7, #68] @ 0x44 SerialProtocolRespStatus respStatus = spUnknownCommand; 8005160: 23fd movs r3, #253 @ 0xfd 8005162: f887 3097 strb.w r3, [r7, #151] @ 0x97 switch (spFrameData->frameHeader.frameCommand) { 8005166: 683b ldr r3, [r7, #0] 8005168: 789b ldrb r3, [r3, #2] 800516a: 2b11 cmp r3, #17 800516c: f200 85a2 bhi.w 8005cb4 8005170: a201 add r2, pc, #4 @ (adr r2, 8005178 ) 8005172: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8005176: bf00 nop 8005178: 080051c1 .word 0x080051c1 800517c: 080052f9 .word 0x080052f9 8005180: 08005473 .word 0x08005473 8005184: 080055a9 .word 0x080055a9 8005188: 0800564b .word 0x0800564b 800518c: 08005769 .word 0x08005769 8005190: 080057bf .word 0x080057bf 8005194: 080056ed .word 0x080056ed 8005198: 08005815 .word 0x08005815 800519c: 080058b5 .word 0x080058b5 80051a0: 08005901 .word 0x08005901 80051a4: 0800594d .word 0x0800594d 80051a8: 080059af .word 0x080059af 80051ac: 08005a13 .word 0x08005a13 80051b0: 08005a75 .word 0x08005a75 80051b4: 08005ad9 .word 0x08005ad9 80051b8: 08005ae1 .word 0x08005ae1 80051bc: 08005be5 .word 0x08005be5 case spGetElectricalMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80051c0: 4b4a ldr r3, [pc, #296] @ (80052ec ) 80051c2: 681b ldr r3, [r3, #0] 80051c4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80051c8: 4618 mov r0, r3 80051ca: f00f f978 bl 80144be 80051ce: 4603 mov r3, r0 80051d0: 2b00 cmp r3, #0 80051d2: f040 8083 bne.w 80052dc for (int i = 0; i < 3; i++) { 80051d6: 2300 movs r3, #0 80051d8: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80051dc: e00e b.n 80051fc WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltageRMS[i], sizeof (float)); 80051de: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80051e2: 009b lsls r3, r3, #2 80051e4: 4a42 ldr r2, [pc, #264] @ (80052f0 ) 80051e6: 441a add r2, r3 80051e8: 2304 movs r3, #4 80051ea: 493f ldr r1, [pc, #252] @ (80052e8 ) 80051ec: 4841 ldr r0, [pc, #260] @ (80052f4 ) 80051ee: f7fe fbdb bl 80039a8 for (int i = 0; i < 3; i++) { 80051f2: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80051f6: 3301 adds r3, #1 80051f8: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80051fc: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8005200: 2b02 cmp r3, #2 8005202: ddec ble.n 80051de } for (int i = 0; i < 3; i++) { 8005204: 2300 movs r3, #0 8005206: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800520a: e010 b.n 800522e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.voltagePeak[i], sizeof (float)); 800520c: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005210: 3302 adds r3, #2 8005212: 009b lsls r3, r3, #2 8005214: 4a36 ldr r2, [pc, #216] @ (80052f0 ) 8005216: 4413 add r3, r2 8005218: 1d1a adds r2, r3, #4 800521a: 2304 movs r3, #4 800521c: 4932 ldr r1, [pc, #200] @ (80052e8 ) 800521e: 4835 ldr r0, [pc, #212] @ (80052f4 ) 8005220: f7fe fbc2 bl 80039a8 for (int i = 0; i < 3; i++) { 8005224: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005228: 3301 adds r3, #1 800522a: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800522e: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8005232: 2b02 cmp r3, #2 8005234: ddea ble.n 800520c } for (int i = 0; i < 3; i++) { 8005236: 2300 movs r3, #0 8005238: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800523c: e00f b.n 800525e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentRMS[i], sizeof (float)); 800523e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005242: 3306 adds r3, #6 8005244: 009b lsls r3, r3, #2 8005246: 4a2a ldr r2, [pc, #168] @ (80052f0 ) 8005248: 441a add r2, r3 800524a: 2304 movs r3, #4 800524c: 4926 ldr r1, [pc, #152] @ (80052e8 ) 800524e: 4829 ldr r0, [pc, #164] @ (80052f4 ) 8005250: f7fe fbaa bl 80039a8 for (int i = 0; i < 3; i++) { 8005254: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005258: 3301 adds r3, #1 800525a: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800525e: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 8005262: 2b02 cmp r3, #2 8005264: ddeb ble.n 800523e } for (int i = 0; i < 3; i++) { 8005266: 2300 movs r3, #0 8005268: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800526c: e010 b.n 8005290 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.currentPeak[i], sizeof (float)); 800526e: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005272: 3308 adds r3, #8 8005274: 009b lsls r3, r3, #2 8005276: 4a1e ldr r2, [pc, #120] @ (80052f0 ) 8005278: 4413 add r3, r2 800527a: 1d1a adds r2, r3, #4 800527c: 2304 movs r3, #4 800527e: 491a ldr r1, [pc, #104] @ (80052e8 ) 8005280: 481c ldr r0, [pc, #112] @ (80052f4 ) 8005282: f7fe fb91 bl 80039a8 for (int i = 0; i < 3; i++) { 8005286: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 800528a: 3301 adds r3, #1 800528c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8005290: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8005294: 2b02 cmp r3, #2 8005296: ddea ble.n 800526e } for (int i = 0; i < 3; i++) { 8005298: 2300 movs r3, #0 800529a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800529e: e00f b.n 80052c0 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &resMeasurements.power[i], sizeof (float)); 80052a0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80052a4: 330c adds r3, #12 80052a6: 009b lsls r3, r3, #2 80052a8: 4a11 ldr r2, [pc, #68] @ (80052f0 ) 80052aa: 441a add r2, r3 80052ac: 2304 movs r3, #4 80052ae: 490e ldr r1, [pc, #56] @ (80052e8 ) 80052b0: 4810 ldr r0, [pc, #64] @ (80052f4 ) 80052b2: f7fe fb79 bl 80039a8 for (int i = 0; i < 3; i++) { 80052b6: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80052ba: 3301 adds r3, #1 80052bc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80052c0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80052c4: 2b02 cmp r3, #2 80052c6: ddeb ble.n 80052a0 } osMutexRelease (resMeasurementsMutex); 80052c8: 4b08 ldr r3, [pc, #32] @ (80052ec ) 80052ca: 681b ldr r3, [r3, #0] 80052cc: 4618 mov r0, r3 80052ce: f00f f941 bl 8014554 respStatus = spOK; 80052d2: 2300 movs r3, #0 80052d4: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80052d8: f000 bcf3 b.w 8005cc2 respStatus = spInternalError; 80052dc: 23fc movs r3, #252 @ 0xfc 80052de: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80052e2: f000 bcee b.w 8005cc2 80052e6: bf00 nop 80052e8: 2400105c .word 0x2400105c 80052ec: 24000818 .word 0x24000818 80052f0: 24000824 .word 0x24000824 80052f4: 24000fdc .word 0x24000fdc case spGetSensorMeasurments: if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80052f8: 4b8d ldr r3, [pc, #564] @ (8005530 ) 80052fa: 681b ldr r3, [r3, #0] 80052fc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005300: 4618 mov r0, r3 8005302: f00f f8dc bl 80144be 8005306: 4603 mov r3, r0 8005308: 2b00 cmp r3, #0 800530a: f040 80ad bne.w 8005468 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[0], sizeof (float)); 800530e: 2304 movs r3, #4 8005310: 4a88 ldr r2, [pc, #544] @ (8005534 ) 8005312: 4989 ldr r1, [pc, #548] @ (8005538 ) 8005314: 4889 ldr r0, [pc, #548] @ (800553c ) 8005316: f7fe fb47 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvTemperature[1], sizeof (float)); 800531a: 2304 movs r3, #4 800531c: 4a88 ldr r2, [pc, #544] @ (8005540 ) 800531e: 4986 ldr r1, [pc, #536] @ (8005538 ) 8005320: 4886 ldr r0, [pc, #536] @ (800553c ) 8005322: f7fe fb41 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.fanVoltage, sizeof (float)); 8005326: 2304 movs r3, #4 8005328: 4a86 ldr r2, [pc, #536] @ (8005544 ) 800532a: 4983 ldr r1, [pc, #524] @ (8005538 ) 800532c: 4883 ldr r0, [pc, #524] @ (800553c ) 800532e: f7fe fb3b bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderX, sizeof (float)); 8005332: 2304 movs r3, #4 8005334: 4a84 ldr r2, [pc, #528] @ (8005548 ) 8005336: 4980 ldr r1, [pc, #512] @ (8005538 ) 8005338: 4880 ldr r0, [pc, #512] @ (800553c ) 800533a: f7fe fb35 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.pvEncoderY, sizeof (float)); 800533e: 2304 movs r3, #4 8005340: 4a82 ldr r2, [pc, #520] @ (800554c ) 8005342: 497d ldr r1, [pc, #500] @ (8005538 ) 8005344: 487d ldr r0, [pc, #500] @ (800553c ) 8005346: f7fe fb2f bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXStatus, sizeof (uint8_t)); 800534a: 2301 movs r3, #1 800534c: 4a80 ldr r2, [pc, #512] @ (8005550 ) 800534e: 497a ldr r1, [pc, #488] @ (8005538 ) 8005350: 487a ldr r0, [pc, #488] @ (800553c ) 8005352: f7fe fb29 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYStatus, sizeof (uint8_t)); 8005356: 2301 movs r3, #1 8005358: 4a7e ldr r2, [pc, #504] @ (8005554 ) 800535a: 4977 ldr r1, [pc, #476] @ (8005538 ) 800535c: 4877 ldr r0, [pc, #476] @ (800553c ) 800535e: f7fe fb23 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXAveCurrent, sizeof (float)); 8005362: 2304 movs r3, #4 8005364: 4a7c ldr r2, [pc, #496] @ (8005558 ) 8005366: 4974 ldr r1, [pc, #464] @ (8005538 ) 8005368: 4874 ldr r0, [pc, #464] @ (800553c ) 800536a: f7fe fb1d bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYAveCurrent, sizeof (float)); 800536e: 2304 movs r3, #4 8005370: 4a7a ldr r2, [pc, #488] @ (800555c ) 8005372: 4971 ldr r1, [pc, #452] @ (8005538 ) 8005374: 4871 ldr r0, [pc, #452] @ (800553c ) 8005376: f7fe fb17 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorXPeakCurrent, sizeof (float)); 800537a: 2304 movs r3, #4 800537c: 4a78 ldr r2, [pc, #480] @ (8005560 ) 800537e: 496e ldr r1, [pc, #440] @ (8005538 ) 8005380: 486e ldr r0, [pc, #440] @ (800553c ) 8005382: f7fe fb11 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.motorYPeakCurrent, sizeof (float)); 8005386: 2304 movs r3, #4 8005388: 4a76 ldr r2, [pc, #472] @ (8005564 ) 800538a: 496b ldr r1, [pc, #428] @ (8005538 ) 800538c: 486b ldr r0, [pc, #428] @ (800553c ) 800538e: f7fe fb0b bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchUp, sizeof (uint8_t)); 8005392: 2301 movs r3, #1 8005394: 4a74 ldr r2, [pc, #464] @ (8005568 ) 8005396: 4968 ldr r1, [pc, #416] @ (8005538 ) 8005398: 4868 ldr r0, [pc, #416] @ (800553c ) 800539a: f7fe fb05 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchDown, sizeof (uint8_t)); 800539e: 2301 movs r3, #1 80053a0: 4a72 ldr r2, [pc, #456] @ (800556c ) 80053a2: 4965 ldr r1, [pc, #404] @ (8005538 ) 80053a4: 4865 ldr r0, [pc, #404] @ (800553c ) 80053a6: f7fe faff bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitXSwitchCenter, sizeof (uint8_t)); 80053aa: 2301 movs r3, #1 80053ac: 4a70 ldr r2, [pc, #448] @ (8005570 ) 80053ae: 4962 ldr r1, [pc, #392] @ (8005538 ) 80053b0: 4862 ldr r0, [pc, #392] @ (800553c ) 80053b2: f7fe faf9 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchUp, sizeof (uint8_t)); 80053b6: 2301 movs r3, #1 80053b8: 4a6e ldr r2, [pc, #440] @ (8005574 ) 80053ba: 495f ldr r1, [pc, #380] @ (8005538 ) 80053bc: 485f ldr r0, [pc, #380] @ (800553c ) 80053be: f7fe faf3 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchDown, sizeof (uint8_t)); 80053c2: 2301 movs r3, #1 80053c4: 4a6c ldr r2, [pc, #432] @ (8005578 ) 80053c6: 495c ldr r1, [pc, #368] @ (8005538 ) 80053c8: 485c ldr r0, [pc, #368] @ (800553c ) 80053ca: f7fe faed bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.limitYSwitchCenter, sizeof (uint8_t)); 80053ce: 2301 movs r3, #1 80053d0: 4a6a ldr r2, [pc, #424] @ (800557c ) 80053d2: 4959 ldr r1, [pc, #356] @ (8005538 ) 80053d4: 4859 ldr r0, [pc, #356] @ (800553c ) 80053d6: f7fe fae7 bl 80039a8 uint8_t comparatorOutput = HAL_COMP_GetOutputLevel (&hcomp1) == COMP_OUTPUT_LEVEL_HIGH ? 1 : 0; 80053da: 4869 ldr r0, [pc, #420] @ (8005580 ) 80053dc: f002 faf2 bl 80079c4 80053e0: 4603 mov r3, r0 80053e2: 2b01 cmp r3, #1 80053e4: bf0c ite eq 80053e6: 2301 moveq r3, #1 80053e8: 2300 movne r3, #0 80053ea: b2db uxtb r3, r3 80053ec: f887 3047 strb.w r3, [r7, #71] @ 0x47 sensorsInfo.powerSupplyFailMask = ~((comparatorOutput << 1) | HAL_GPIO_ReadPin (GPIOD, GPIO_PIN_3)) & 0x01; 80053f0: f897 3047 ldrb.w r3, [r7, #71] @ 0x47 80053f4: 005c lsls r4, r3, #1 80053f6: 2108 movs r1, #8 80053f8: 4862 ldr r0, [pc, #392] @ (8005584 ) 80053fa: f006 f89b bl 800b534 80053fe: 4603 mov r3, r0 8005400: 4323 orrs r3, r4 8005402: f003 0301 and.w r3, r3, #1 8005406: 2b00 cmp r3, #0 8005408: bf0c ite eq 800540a: 2301 moveq r3, #1 800540c: 2300 movne r3, #0 800540e: b2db uxtb r3, r3 8005410: 461a mov r2, r3 8005412: 4b48 ldr r3, [pc, #288] @ (8005534 ) 8005414: f883 202e strb.w r2, [r3, #46] @ 0x2e WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.powerSupplyFailMask, sizeof (uint8_t)); 8005418: 2301 movs r3, #1 800541a: 4a5b ldr r2, [pc, #364] @ (8005588 ) 800541c: 4946 ldr r1, [pc, #280] @ (8005538 ) 800541e: 4847 ldr r0, [pc, #284] @ (800553c ) 8005420: f7fe fac2 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentXPosition, sizeof (float)); 8005424: 2304 movs r3, #4 8005426: 4a59 ldr r2, [pc, #356] @ (800558c ) 8005428: 4943 ldr r1, [pc, #268] @ (8005538 ) 800542a: 4844 ldr r0, [pc, #272] @ (800553c ) 800542c: f7fe fabc bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.currentYPosition, sizeof (float)); 8005430: 2304 movs r3, #4 8005432: 4a57 ldr r2, [pc, #348] @ (8005590 ) 8005434: 4940 ldr r1, [pc, #256] @ (8005538 ) 8005436: 4841 ldr r0, [pc, #260] @ (800553c ) 8005438: f7fe fab6 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionXWeak, sizeof (uint8_t)); 800543c: 2301 movs r3, #1 800543e: 4a55 ldr r2, [pc, #340] @ (8005594 ) 8005440: 493d ldr r1, [pc, #244] @ (8005538 ) 8005442: 483e ldr r0, [pc, #248] @ (800553c ) 8005444: f7fe fab0 bl 80039a8 WriteDataToBuffer (outputDataBuffer, &outputDataBufferPos, &sensorsInfo.positionYWeak, sizeof (uint8_t)); 8005448: 2301 movs r3, #1 800544a: 4a53 ldr r2, [pc, #332] @ (8005598 ) 800544c: 493a ldr r1, [pc, #232] @ (8005538 ) 800544e: 483b ldr r0, [pc, #236] @ (800553c ) 8005450: f7fe faaa bl 80039a8 osMutexRelease (sensorsInfoMutex); 8005454: 4b36 ldr r3, [pc, #216] @ (8005530 ) 8005456: 681b ldr r3, [r3, #0] 8005458: 4618 mov r0, r3 800545a: f00f f87b bl 8014554 respStatus = spOK; 800545e: 2300 movs r3, #0 8005460: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005464: f000 bc2d b.w 8005cc2 respStatus = spInternalError; 8005468: 23fc movs r3, #252 @ 0xfc 800546a: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800546e: f000 bc28 b.w 8005cc2 case spSetFanSpeed: osTimerStop (fanTimerHandle); 8005472: 4b4a ldr r3, [pc, #296] @ (800559c ) 8005474: 681b ldr r3, [r3, #0] 8005476: 4618 mov r0, r3 8005478: f00e ff64 bl 8014344 int32_t fanTimerPeriod = 0; 800547c: 2300 movs r3, #0 800547e: 643b str r3, [r7, #64] @ 0x40 uint32_t pulse = 0; 8005480: 2300 movs r3, #0 8005482: 63fb str r3, [r7, #60] @ 0x3c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, &pulse); 8005484: 683b ldr r3, [r7, #0] 8005486: 330c adds r3, #12 8005488: f107 023c add.w r2, r7, #60 @ 0x3c 800548c: f107 0144 add.w r1, r7, #68 @ 0x44 8005490: 4618 mov r0, r3 8005492: f7fe faef bl 8003a74 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&fanTimerPeriod); 8005496: 683b ldr r3, [r7, #0] 8005498: 330c adds r3, #12 800549a: f107 0240 add.w r2, r7, #64 @ 0x40 800549e: f107 0144 add.w r1, r7, #68 @ 0x44 80054a2: 4618 mov r0, r3 80054a4: f7fe fae6 bl 8003a74 fanTimerConfigOC.Pulse = pulse * 10; 80054a8: 6bfa ldr r2, [r7, #60] @ 0x3c 80054aa: 4613 mov r3, r2 80054ac: 009b lsls r3, r3, #2 80054ae: 4413 add r3, r2 80054b0: 005b lsls r3, r3, #1 80054b2: 461a mov r2, r3 80054b4: 4b3a ldr r3, [pc, #232] @ (80055a0 ) 80054b6: 605a str r2, [r3, #4] if (HAL_TIM_PWM_ConfigChannel (&htim1, &fanTimerConfigOC, TIM_CHANNEL_2) != HAL_OK) { 80054b8: 2204 movs r2, #4 80054ba: 4939 ldr r1, [pc, #228] @ (80055a0 ) 80054bc: 4839 ldr r0, [pc, #228] @ (80055a4 ) 80054be: f00a fe45 bl 801014c 80054c2: 4603 mov r3, r0 80054c4: 2b00 cmp r3, #0 80054c6: d001 beq.n 80054cc Error_Handler (); 80054c8: f7fc fd00 bl 8001ecc } if (fanTimerPeriod > 0) { 80054cc: 6c3b ldr r3, [r7, #64] @ 0x40 80054ce: 2b00 cmp r3, #0 80054d0: dd0f ble.n 80054f2 osTimerStart (fanTimerHandle, fanTimerPeriod * 1000); 80054d2: 4b32 ldr r3, [pc, #200] @ (800559c ) 80054d4: 681a ldr r2, [r3, #0] 80054d6: 6c3b ldr r3, [r7, #64] @ 0x40 80054d8: f44f 717a mov.w r1, #1000 @ 0x3e8 80054dc: fb01 f303 mul.w r3, r1, r3 80054e0: 4619 mov r1, r3 80054e2: 4610 mov r0, r2 80054e4: f00e ff00 bl 80142e8 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 80054e8: 2104 movs r1, #4 80054ea: 482e ldr r0, [pc, #184] @ (80055a4 ) 80054ec: f00a f934 bl 800f758 80054f0: e019 b.n 8005526 } else if (fanTimerPeriod == 0) { 80054f2: 6c3b ldr r3, [r7, #64] @ 0x40 80054f4: 2b00 cmp r3, #0 80054f6: d109 bne.n 800550c osTimerStop (fanTimerHandle); 80054f8: 4b28 ldr r3, [pc, #160] @ (800559c ) 80054fa: 681b ldr r3, [r3, #0] 80054fc: 4618 mov r0, r3 80054fe: f00e ff21 bl 8014344 HAL_TIM_PWM_Stop (&htim1, TIM_CHANNEL_2); 8005502: 2104 movs r1, #4 8005504: 4827 ldr r0, [pc, #156] @ (80055a4 ) 8005506: f00a fa35 bl 800f974 800550a: e00c b.n 8005526 } else if (fanTimerPeriod == -1) { 800550c: 6c3b ldr r3, [r7, #64] @ 0x40 800550e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8005512: d108 bne.n 8005526 osTimerStop (fanTimerHandle); 8005514: 4b21 ldr r3, [pc, #132] @ (800559c ) 8005516: 681b ldr r3, [r3, #0] 8005518: 4618 mov r0, r3 800551a: f00e ff13 bl 8014344 HAL_TIM_PWM_Start (&htim1, TIM_CHANNEL_2); 800551e: 2104 movs r1, #4 8005520: 4820 ldr r0, [pc, #128] @ (80055a4 ) 8005522: f00a f919 bl 800f758 } respStatus = spOK; 8005526: 2300 movs r3, #0 8005528: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800552c: e3c9 b.n 8005cc2 800552e: bf00 nop 8005530: 2400081c .word 0x2400081c 8005534: 24000860 .word 0x24000860 8005538: 2400105c .word 0x2400105c 800553c: 24000fdc .word 0x24000fdc 8005540: 24000864 .word 0x24000864 8005544: 24000868 .word 0x24000868 8005548: 2400086c .word 0x2400086c 800554c: 24000870 .word 0x24000870 8005550: 24000874 .word 0x24000874 8005554: 24000875 .word 0x24000875 8005558: 24000878 .word 0x24000878 800555c: 2400087c .word 0x2400087c 8005560: 24000880 .word 0x24000880 8005564: 24000884 .word 0x24000884 8005568: 24000888 .word 0x24000888 800556c: 24000889 .word 0x24000889 8005570: 2400088a .word 0x2400088a 8005574: 2400088b .word 0x2400088b 8005578: 2400088c .word 0x2400088c 800557c: 2400088d .word 0x2400088d 8005580: 240003b4 .word 0x240003b4 8005584: 58020c00 .word 0x58020c00 8005588: 2400088e .word 0x2400088e 800558c: 24000890 .word 0x24000890 8005590: 24000894 .word 0x24000894 8005594: 24000898 .word 0x24000898 8005598: 24000899 .word 0x24000899 800559c: 24000714 .word 0x24000714 80055a0: 240007a4 .word 0x240007a4 80055a4: 2400043c .word 0x2400043c case spSetMotorXOn: int32_t motorXPWMPulse = 0; 80055a8: 2300 movs r3, #0 80055aa: 63bb str r3, [r7, #56] @ 0x38 int32_t motorXTimerPeriod = 0; 80055ac: 2300 movs r3, #0 80055ae: 637b str r3, [r7, #52] @ 0x34 uint32_t motorXStatus = 0; 80055b0: 2300 movs r3, #0 80055b2: 64bb str r3, [r7, #72] @ 0x48 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXPWMPulse); 80055b4: 683b ldr r3, [r7, #0] 80055b6: 330c adds r3, #12 80055b8: f107 0238 add.w r2, r7, #56 @ 0x38 80055bc: f107 0144 add.w r1, r7, #68 @ 0x44 80055c0: 4618 mov r0, r3 80055c2: f7fe fa57 bl 8003a74 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXTimerPeriod); 80055c6: 683b ldr r3, [r7, #0] 80055c8: 330c adds r3, #12 80055ca: f107 0234 add.w r2, r7, #52 @ 0x34 80055ce: f107 0144 add.w r1, r7, #68 @ 0x44 80055d2: 4618 mov r0, r3 80055d4: f7fe fa4e bl 8003a74 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80055d8: 4bab ldr r3, [pc, #684] @ (8005888 ) 80055da: 681b ldr r3, [r3, #0] 80055dc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80055e0: 4618 mov r0, r3 80055e2: f00e ff6c bl 80144be 80055e6: 4603 mov r3, r0 80055e8: 2b00 cmp r3, #0 80055ea: d12a bne.n 8005642 motorXStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_1, TIM_CHANNEL_2, motorXTimerHandle, motorXPWMPulse, motorXTimerPeriod, sensorsInfo.limitXSwitchUp, sensorsInfo.limitXSwitchDown); 80055ec: 4ba7 ldr r3, [pc, #668] @ (800588c ) 80055ee: 681b ldr r3, [r3, #0] 80055f0: 6bba ldr r2, [r7, #56] @ 0x38 80055f2: 6b79 ldr r1, [r7, #52] @ 0x34 80055f4: 48a6 ldr r0, [pc, #664] @ (8005890 ) 80055f6: f890 0028 ldrb.w r0, [r0, #40] @ 0x28 80055fa: 4ca5 ldr r4, [pc, #660] @ (8005890 ) 80055fc: f894 4029 ldrb.w r4, [r4, #41] @ 0x29 8005600: 9404 str r4, [sp, #16] 8005602: 9003 str r0, [sp, #12] 8005604: 9102 str r1, [sp, #8] 8005606: 9201 str r2, [sp, #4] 8005608: 9300 str r3, [sp, #0] 800560a: 2304 movs r3, #4 800560c: 2200 movs r2, #0 800560e: 49a1 ldr r1, [pc, #644] @ (8005894 ) 8005610: 48a1 ldr r0, [pc, #644] @ (8005898 ) 8005612: f7fd fcf5 bl 8003000 8005616: 4603 mov r3, r0 motorXStatus = 8005618: 64bb str r3, [r7, #72] @ 0x48 sensorsInfo.motorXStatus = motorXStatus; 800561a: 6cbb ldr r3, [r7, #72] @ 0x48 800561c: b2da uxtb r2, r3 800561e: 4b9c ldr r3, [pc, #624] @ (8005890 ) 8005620: 751a strb r2, [r3, #20] if (motorXStatus == 1) { 8005622: 6cbb ldr r3, [r7, #72] @ 0x48 8005624: 2b01 cmp r3, #1 8005626: d103 bne.n 8005630 sensorsInfo.motorXPeakCurrent = 0.0; 8005628: 4b99 ldr r3, [pc, #612] @ (8005890 ) 800562a: f04f 0200 mov.w r2, #0 800562e: 621a str r2, [r3, #32] } osMutexRelease (sensorsInfoMutex); 8005630: 4b95 ldr r3, [pc, #596] @ (8005888 ) 8005632: 681b ldr r3, [r3, #0] 8005634: 4618 mov r0, r3 8005636: f00e ff8d bl 8014554 respStatus = spOK; 800563a: 2300 movs r3, #0 800563c: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005640: e33f b.n 8005cc2 respStatus = spInternalError; 8005642: 23fc movs r3, #252 @ 0xfc 8005644: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005648: e33b b.n 8005cc2 case spSetMotorYOn: int32_t motorYPWMPulse = 0; 800564a: 2300 movs r3, #0 800564c: 633b str r3, [r7, #48] @ 0x30 int32_t motorYTimerPeriod = 0; 800564e: 2300 movs r3, #0 8005650: 62fb str r3, [r7, #44] @ 0x2c uint32_t motorYStatus = 0; 8005652: 2300 movs r3, #0 8005654: 64fb str r3, [r7, #76] @ 0x4c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYPWMPulse); 8005656: 683b ldr r3, [r7, #0] 8005658: 330c adds r3, #12 800565a: f107 0230 add.w r2, r7, #48 @ 0x30 800565e: f107 0144 add.w r1, r7, #68 @ 0x44 8005662: 4618 mov r0, r3 8005664: f7fe fa06 bl 8003a74 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYTimerPeriod); 8005668: 683b ldr r3, [r7, #0] 800566a: 330c adds r3, #12 800566c: f107 022c add.w r2, r7, #44 @ 0x2c 8005670: f107 0144 add.w r1, r7, #68 @ 0x44 8005674: 4618 mov r0, r3 8005676: f7fe f9fd bl 8003a74 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 800567a: 4b83 ldr r3, [pc, #524] @ (8005888 ) 800567c: 681b ldr r3, [r3, #0] 800567e: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005682: 4618 mov r0, r3 8005684: f00e ff1b bl 80144be 8005688: 4603 mov r3, r0 800568a: 2b00 cmp r3, #0 800568c: d12a bne.n 80056e4 motorYStatus = MotorControl (&htim3, &motorXYTimerConfigOC, TIM_CHANNEL_3, TIM_CHANNEL_4, motorYTimerHandle, motorYPWMPulse, motorYTimerPeriod, sensorsInfo.limitYSwitchUp, sensorsInfo.limitYSwitchDown); 800568e: 4b83 ldr r3, [pc, #524] @ (800589c ) 8005690: 681b ldr r3, [r3, #0] 8005692: 6b3a ldr r2, [r7, #48] @ 0x30 8005694: 6af9 ldr r1, [r7, #44] @ 0x2c 8005696: 487e ldr r0, [pc, #504] @ (8005890 ) 8005698: f890 002b ldrb.w r0, [r0, #43] @ 0x2b 800569c: 4c7c ldr r4, [pc, #496] @ (8005890 ) 800569e: f894 402c ldrb.w r4, [r4, #44] @ 0x2c 80056a2: 9404 str r4, [sp, #16] 80056a4: 9003 str r0, [sp, #12] 80056a6: 9102 str r1, [sp, #8] 80056a8: 9201 str r2, [sp, #4] 80056aa: 9300 str r3, [sp, #0] 80056ac: 230c movs r3, #12 80056ae: 2208 movs r2, #8 80056b0: 4978 ldr r1, [pc, #480] @ (8005894 ) 80056b2: 4879 ldr r0, [pc, #484] @ (8005898 ) 80056b4: f7fd fca4 bl 8003000 80056b8: 4603 mov r3, r0 motorYStatus = 80056ba: 64fb str r3, [r7, #76] @ 0x4c sensorsInfo.motorYStatus = motorYStatus; 80056bc: 6cfb ldr r3, [r7, #76] @ 0x4c 80056be: b2da uxtb r2, r3 80056c0: 4b73 ldr r3, [pc, #460] @ (8005890 ) 80056c2: 755a strb r2, [r3, #21] if (motorYStatus == 1) { 80056c4: 6cfb ldr r3, [r7, #76] @ 0x4c 80056c6: 2b01 cmp r3, #1 80056c8: d103 bne.n 80056d2 sensorsInfo.motorYPeakCurrent = 0.0; 80056ca: 4b71 ldr r3, [pc, #452] @ (8005890 ) 80056cc: f04f 0200 mov.w r2, #0 80056d0: 625a str r2, [r3, #36] @ 0x24 } osMutexRelease (sensorsInfoMutex); 80056d2: 4b6d ldr r3, [pc, #436] @ (8005888 ) 80056d4: 681b ldr r3, [r3, #0] 80056d6: 4618 mov r0, r3 80056d8: f00e ff3c bl 8014554 respStatus = spOK; 80056dc: 2300 movs r3, #0 80056de: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80056e2: e2ee b.n 8005cc2 respStatus = spInternalError; 80056e4: 23fc movs r3, #252 @ 0xfc 80056e6: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80056ea: e2ea b.n 8005cc2 case spSetDiodeOn: osTimerStop (debugLedTimerHandle); 80056ec: 4b6c ldr r3, [pc, #432] @ (80058a0 ) 80056ee: 681b ldr r3, [r3, #0] 80056f0: 4618 mov r0, r3 80056f2: f00e fe27 bl 8014344 int32_t dbgLedTimerPeriod = 0; 80056f6: 2300 movs r3, #0 80056f8: 62bb str r3, [r7, #40] @ 0x28 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&dbgLedTimerPeriod); 80056fa: 683b ldr r3, [r7, #0] 80056fc: 330c adds r3, #12 80056fe: f107 0228 add.w r2, r7, #40 @ 0x28 8005702: f107 0144 add.w r1, r7, #68 @ 0x44 8005706: 4618 mov r0, r3 8005708: f7fe f9b4 bl 8003a74 if (dbgLedTimerPeriod > 0) { 800570c: 6abb ldr r3, [r7, #40] @ 0x28 800570e: 2b00 cmp r3, #0 8005710: dd0e ble.n 8005730 osTimerStart (debugLedTimerHandle, dbgLedTimerPeriod * 1000); 8005712: 4b63 ldr r3, [pc, #396] @ (80058a0 ) 8005714: 681a ldr r2, [r3, #0] 8005716: 6abb ldr r3, [r7, #40] @ 0x28 8005718: f44f 717a mov.w r1, #1000 @ 0x3e8 800571c: fb01 f303 mul.w r3, r1, r3 8005720: 4619 mov r1, r3 8005722: 4610 mov r0, r2 8005724: f00e fde0 bl 80142e8 DbgLEDOn (DBG_LED1); 8005728: 2010 movs r0, #16 800572a: f7fd fbdb bl 8002ee4 800572e: e017 b.n 8005760 } else if (dbgLedTimerPeriod == 0) { 8005730: 6abb ldr r3, [r7, #40] @ 0x28 8005732: 2b00 cmp r3, #0 8005734: d108 bne.n 8005748 osTimerStop (debugLedTimerHandle); 8005736: 4b5a ldr r3, [pc, #360] @ (80058a0 ) 8005738: 681b ldr r3, [r3, #0] 800573a: 4618 mov r0, r3 800573c: f00e fe02 bl 8014344 DbgLEDOff (DBG_LED1); 8005740: 2010 movs r0, #16 8005742: f7fd fbe1 bl 8002f08 8005746: e00b b.n 8005760 } else if (dbgLedTimerPeriod == -1) { 8005748: 6abb ldr r3, [r7, #40] @ 0x28 800574a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 800574e: d107 bne.n 8005760 osTimerStop (debugLedTimerHandle); 8005750: 4b53 ldr r3, [pc, #332] @ (80058a0 ) 8005752: 681b ldr r3, [r3, #0] 8005754: 4618 mov r0, r3 8005756: f00e fdf5 bl 8014344 DbgLEDOn (DBG_LED1); 800575a: 2010 movs r0, #16 800575c: f7fd fbc2 bl 8002ee4 } respStatus = spOK; 8005760: 2300 movs r3, #0 8005762: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005766: e2ac b.n 8005cc2 case spSetmotorXMaxCurrent: float motorXMaxCurrent = 0; 8005768: f04f 0300 mov.w r3, #0 800576c: 627b str r3, [r7, #36] @ 0x24 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorXMaxCurrent); 800576e: 683b ldr r3, [r7, #0] 8005770: 330c adds r3, #12 8005772: f107 0224 add.w r2, r7, #36 @ 0x24 8005776: f107 0144 add.w r1, r7, #68 @ 0x44 800577a: 4618 mov r0, r3 800577c: f7fe f97a bl 8003a74 uint32_t dacDataCh1 = (uint32_t)(4095 * motorXMaxCurrent / (EXT_VREF_mV * 0.001)); 8005780: edd7 7a09 vldr s15, [r7, #36] @ 0x24 8005784: ed9f 7a47 vldr s14, [pc, #284] @ 80058a4 8005788: ee67 7a87 vmul.f32 s15, s15, s14 800578c: eeb7 6ae7 vcvt.f64.f32 d6, s15 8005790: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 8005794: ee86 7b05 vdiv.f64 d7, d6, d5 8005798: eefc 7bc7 vcvt.u32.f64 s15, d7 800579c: ee17 3a90 vmov r3, s15 80057a0: 653b str r3, [r7, #80] @ 0x50 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dacDataCh1); 80057a2: 6d3b ldr r3, [r7, #80] @ 0x50 80057a4: 2200 movs r2, #0 80057a6: 2100 movs r1, #0 80057a8: 483f ldr r0, [pc, #252] @ (80058a8 ) 80057aa: f002 fd56 bl 800825a HAL_DAC_Start (&hdac1, DAC_CHANNEL_1); 80057ae: 2100 movs r1, #0 80057b0: 483d ldr r0, [pc, #244] @ (80058a8 ) 80057b2: f002 fca5 bl 8008100 respStatus = spOK; 80057b6: 2300 movs r3, #0 80057b8: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80057bc: e281 b.n 8005cc2 case spSetmotorYMaxCurrent: float motorYMaxCurrent = 0; 80057be: f04f 0300 mov.w r3, #0 80057c2: 623b str r3, [r7, #32] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&motorYMaxCurrent); 80057c4: 683b ldr r3, [r7, #0] 80057c6: 330c adds r3, #12 80057c8: f107 0220 add.w r2, r7, #32 80057cc: f107 0144 add.w r1, r7, #68 @ 0x44 80057d0: 4618 mov r0, r3 80057d2: f7fe f94f bl 8003a74 uint32_t dacDataCh2 = (uint32_t)(4095 * motorYMaxCurrent / (EXT_VREF_mV * 0.001)); 80057d6: edd7 7a08 vldr s15, [r7, #32] 80057da: ed9f 7a32 vldr s14, [pc, #200] @ 80058a4 80057de: ee67 7a87 vmul.f32 s15, s15, s14 80057e2: eeb7 6ae7 vcvt.f64.f32 d6, s15 80057e6: eeb0 5b08 vmov.f64 d5, #8 @ 0x40400000 3.0 80057ea: ee86 7b05 vdiv.f64 d7, d6, d5 80057ee: eefc 7bc7 vcvt.u32.f64 s15, d7 80057f2: ee17 3a90 vmov r3, s15 80057f6: 657b str r3, [r7, #84] @ 0x54 HAL_DAC_SetValue (&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dacDataCh2); 80057f8: 6d7b ldr r3, [r7, #84] @ 0x54 80057fa: 2200 movs r2, #0 80057fc: 2110 movs r1, #16 80057fe: 482a ldr r0, [pc, #168] @ (80058a8 ) 8005800: f002 fd2b bl 800825a HAL_DAC_Start (&hdac1, DAC_CHANNEL_2); 8005804: 2110 movs r1, #16 8005806: 4828 ldr r0, [pc, #160] @ (80058a8 ) 8005808: f002 fc7a bl 8008100 respStatus = spOK; 800580c: 2300 movs r3, #0 800580e: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005812: e256 b.n 8005cc2 case spClearPeakMeasurments: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005814: 4b25 ldr r3, [pc, #148] @ (80058ac ) 8005816: 681b ldr r3, [r3, #0] 8005818: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800581c: 4618 mov r0, r3 800581e: f00e fe4e bl 80144be 8005822: 4603 mov r3, r0 8005824: 2b00 cmp r3, #0 8005826: d12a bne.n 800587e for (int i = 0; i < 3; i++) { 8005828: 2300 movs r3, #0 800582a: 67fb str r3, [r7, #124] @ 0x7c 800582c: e01b b.n 8005866 resMeasurements.voltagePeak[i] = resMeasurements.voltageRMS[i]; 800582e: 4a20 ldr r2, [pc, #128] @ (80058b0 ) 8005830: 6ffb ldr r3, [r7, #124] @ 0x7c 8005832: 009b lsls r3, r3, #2 8005834: 4413 add r3, r2 8005836: 681a ldr r2, [r3, #0] 8005838: 491d ldr r1, [pc, #116] @ (80058b0 ) 800583a: 6ffb ldr r3, [r7, #124] @ 0x7c 800583c: 3302 adds r3, #2 800583e: 009b lsls r3, r3, #2 8005840: 440b add r3, r1 8005842: 3304 adds r3, #4 8005844: 601a str r2, [r3, #0] resMeasurements.currentPeak[i] = resMeasurements.currentRMS[i]; 8005846: 4a1a ldr r2, [pc, #104] @ (80058b0 ) 8005848: 6ffb ldr r3, [r7, #124] @ 0x7c 800584a: 3306 adds r3, #6 800584c: 009b lsls r3, r3, #2 800584e: 4413 add r3, r2 8005850: 681a ldr r2, [r3, #0] 8005852: 4917 ldr r1, [pc, #92] @ (80058b0 ) 8005854: 6ffb ldr r3, [r7, #124] @ 0x7c 8005856: 3308 adds r3, #8 8005858: 009b lsls r3, r3, #2 800585a: 440b add r3, r1 800585c: 3304 adds r3, #4 800585e: 601a str r2, [r3, #0] for (int i = 0; i < 3; i++) { 8005860: 6ffb ldr r3, [r7, #124] @ 0x7c 8005862: 3301 adds r3, #1 8005864: 67fb str r3, [r7, #124] @ 0x7c 8005866: 6ffb ldr r3, [r7, #124] @ 0x7c 8005868: 2b02 cmp r3, #2 800586a: dde0 ble.n 800582e } osMutexRelease (resMeasurementsMutex); 800586c: 4b0f ldr r3, [pc, #60] @ (80058ac ) 800586e: 681b ldr r3, [r3, #0] 8005870: 4618 mov r0, r3 8005872: f00e fe6f bl 8014554 respStatus = spOK; 8005876: 2300 movs r3, #0 8005878: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 800587c: e221 b.n 8005cc2 respStatus = spInternalError; 800587e: 23fc movs r3, #252 @ 0xfc 8005880: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005884: e21d b.n 8005cc2 8005886: bf00 nop 8005888: 2400081c .word 0x2400081c 800588c: 24000744 .word 0x24000744 8005890: 24000860 .word 0x24000860 8005894: 240007c0 .word 0x240007c0 8005898: 240004d4 .word 0x240004d4 800589c: 24000774 .word 0x24000774 80058a0: 240006e4 .word 0x240006e4 80058a4: 457ff000 .word 0x457ff000 80058a8: 24000404 .word 0x24000404 80058ac: 24000818 .word 0x24000818 80058b0: 24000824 .word 0x24000824 case spSetEncoderXValue: float enocoderXValue = 0; 80058b4: f04f 0300 mov.w r3, #0 80058b8: 61fb str r3, [r7, #28] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderXValue); 80058ba: 683b ldr r3, [r7, #0] 80058bc: 330c adds r3, #12 80058be: f107 021c add.w r2, r7, #28 80058c2: f107 0144 add.w r1, r7, #68 @ 0x44 80058c6: 4618 mov r0, r3 80058c8: f7fe f8d4 bl 8003a74 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 80058cc: 4bbc ldr r3, [pc, #752] @ (8005bc0 ) 80058ce: 681b ldr r3, [r3, #0] 80058d0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80058d4: 4618 mov r0, r3 80058d6: f00e fdf2 bl 80144be 80058da: 4603 mov r3, r0 80058dc: 2b00 cmp r3, #0 80058de: d10b bne.n 80058f8 sensorsInfo.pvEncoderX = enocoderXValue; 80058e0: 69fb ldr r3, [r7, #28] 80058e2: 4ab8 ldr r2, [pc, #736] @ (8005bc4 ) 80058e4: 60d3 str r3, [r2, #12] osMutexRelease (sensorsInfoMutex); 80058e6: 4bb6 ldr r3, [pc, #728] @ (8005bc0 ) 80058e8: 681b ldr r3, [r3, #0] 80058ea: 4618 mov r0, r3 80058ec: f00e fe32 bl 8014554 respStatus = spOK; 80058f0: 2300 movs r3, #0 80058f2: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80058f6: e1e4 b.n 8005cc2 respStatus = spInternalError; 80058f8: 23fc movs r3, #252 @ 0xfc 80058fa: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80058fe: e1e0 b.n 8005cc2 case spSetEncoderYValue: float enocoderYValue = 0; 8005900: f04f 0300 mov.w r3, #0 8005904: 61bb str r3, [r7, #24] ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&enocoderYValue); 8005906: 683b ldr r3, [r7, #0] 8005908: 330c adds r3, #12 800590a: f107 0218 add.w r2, r7, #24 800590e: f107 0144 add.w r1, r7, #68 @ 0x44 8005912: 4618 mov r0, r3 8005914: f7fe f8ae bl 8003a74 if (osMutexAcquire (sensorsInfoMutex, osWaitForever) == osOK) { 8005918: 4ba9 ldr r3, [pc, #676] @ (8005bc0 ) 800591a: 681b ldr r3, [r3, #0] 800591c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005920: 4618 mov r0, r3 8005922: f00e fdcc bl 80144be 8005926: 4603 mov r3, r0 8005928: 2b00 cmp r3, #0 800592a: d10b bne.n 8005944 sensorsInfo.pvEncoderY = enocoderYValue; 800592c: 69bb ldr r3, [r7, #24] 800592e: 4aa5 ldr r2, [pc, #660] @ (8005bc4 ) 8005930: 6113 str r3, [r2, #16] osMutexRelease (sensorsInfoMutex); 8005932: 4ba3 ldr r3, [pc, #652] @ (8005bc0 ) 8005934: 681b ldr r3, [r3, #0] 8005936: 4618 mov r0, r3 8005938: f00e fe0c bl 8014554 respStatus = spOK; 800593c: 2300 movs r3, #0 800593e: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005942: e1be b.n 8005cc2 respStatus = spInternalError; 8005944: 23fc movs r3, #252 @ 0xfc 8005946: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 800594a: e1ba b.n 8005cc2 case spSetVoltageMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 800594c: 4b9e ldr r3, [pc, #632] @ (8005bc8 ) 800594e: 681b ldr r3, [r3, #0] 8005950: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005954: 4618 mov r0, r3 8005956: f00e fdb2 bl 80144be 800595a: 4603 mov r3, r0 800595c: 2b00 cmp r3, #0 800595e: d122 bne.n 80059a6 for (uint8_t i = 0; i < 3; i++) { 8005960: 2300 movs r3, #0 8005962: f887 307b strb.w r3, [r7, #123] @ 0x7b 8005966: e011 b.n 800598c ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].gain); 8005968: 683b ldr r3, [r7, #0] 800596a: f103 000c add.w r0, r3, #12 800596e: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 8005972: 00db lsls r3, r3, #3 8005974: 4a95 ldr r2, [pc, #596] @ (8005bcc ) 8005976: 441a add r2, r3 8005978: f107 0344 add.w r3, r7, #68 @ 0x44 800597c: 4619 mov r1, r3 800597e: f7fe f879 bl 8003a74 for (uint8_t i = 0; i < 3; i++) { 8005982: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 8005986: 3301 adds r3, #1 8005988: f887 307b strb.w r3, [r7, #123] @ 0x7b 800598c: f897 307b ldrb.w r3, [r7, #123] @ 0x7b 8005990: 2b02 cmp r3, #2 8005992: d9e9 bls.n 8005968 } osMutexRelease (resMeasurementsMutex); 8005994: 4b8c ldr r3, [pc, #560] @ (8005bc8 ) 8005996: 681b ldr r3, [r3, #0] 8005998: 4618 mov r0, r3 800599a: f00e fddb bl 8014554 respStatus = spOK; 800599e: 2300 movs r3, #0 80059a0: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 80059a4: e18d b.n 8005cc2 respStatus = spInternalError; 80059a6: 23fc movs r3, #252 @ 0xfc 80059a8: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 80059ac: e189 b.n 8005cc2 case spSetVoltageMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 80059ae: 4b86 ldr r3, [pc, #536] @ (8005bc8 ) 80059b0: 681b ldr r3, [r3, #0] 80059b2: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80059b6: 4618 mov r0, r3 80059b8: f00e fd81 bl 80144be 80059bc: 4603 mov r3, r0 80059be: 2b00 cmp r3, #0 80059c0: d123 bne.n 8005a0a for (uint8_t i = 0; i < 3; i++) { 80059c2: 2300 movs r3, #0 80059c4: f887 307a strb.w r3, [r7, #122] @ 0x7a 80059c8: e012 b.n 80059f0 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&U_MeasCorrectionData[i].offset); 80059ca: 683b ldr r3, [r7, #0] 80059cc: f103 000c add.w r0, r3, #12 80059d0: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059d4: 00db lsls r3, r3, #3 80059d6: 4a7d ldr r2, [pc, #500] @ (8005bcc ) 80059d8: 4413 add r3, r2 80059da: 1d1a adds r2, r3, #4 80059dc: f107 0344 add.w r3, r7, #68 @ 0x44 80059e0: 4619 mov r1, r3 80059e2: f7fe f847 bl 8003a74 for (uint8_t i = 0; i < 3; i++) { 80059e6: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059ea: 3301 adds r3, #1 80059ec: f887 307a strb.w r3, [r7, #122] @ 0x7a 80059f0: f897 307a ldrb.w r3, [r7, #122] @ 0x7a 80059f4: 2b02 cmp r3, #2 80059f6: d9e8 bls.n 80059ca } osMutexRelease (resMeasurementsMutex); 80059f8: 4b73 ldr r3, [pc, #460] @ (8005bc8 ) 80059fa: 681b ldr r3, [r3, #0] 80059fc: 4618 mov r0, r3 80059fe: f00e fda9 bl 8014554 respStatus = spOK; 8005a02: 2300 movs r3, #0 8005a04: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005a08: e15b b.n 8005cc2 respStatus = spInternalError; 8005a0a: 23fc movs r3, #252 @ 0xfc 8005a0c: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005a10: e157 b.n 8005cc2 case spSetCurrentMeasGains: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005a12: 4b6d ldr r3, [pc, #436] @ (8005bc8 ) 8005a14: 681b ldr r3, [r3, #0] 8005a16: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005a1a: 4618 mov r0, r3 8005a1c: f00e fd4f bl 80144be 8005a20: 4603 mov r3, r0 8005a22: 2b00 cmp r3, #0 8005a24: d122 bne.n 8005a6c for (uint8_t i = 0; i < 3; i++) { 8005a26: 2300 movs r3, #0 8005a28: f887 3079 strb.w r3, [r7, #121] @ 0x79 8005a2c: e011 b.n 8005a52 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].gain); 8005a2e: 683b ldr r3, [r7, #0] 8005a30: f103 000c add.w r0, r3, #12 8005a34: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a38: 00db lsls r3, r3, #3 8005a3a: 4a65 ldr r2, [pc, #404] @ (8005bd0 ) 8005a3c: 441a add r2, r3 8005a3e: f107 0344 add.w r3, r7, #68 @ 0x44 8005a42: 4619 mov r1, r3 8005a44: f7fe f816 bl 8003a74 for (uint8_t i = 0; i < 3; i++) { 8005a48: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a4c: 3301 adds r3, #1 8005a4e: f887 3079 strb.w r3, [r7, #121] @ 0x79 8005a52: f897 3079 ldrb.w r3, [r7, #121] @ 0x79 8005a56: 2b02 cmp r3, #2 8005a58: d9e9 bls.n 8005a2e } osMutexRelease (resMeasurementsMutex); 8005a5a: 4b5b ldr r3, [pc, #364] @ (8005bc8 ) 8005a5c: 681b ldr r3, [r3, #0] 8005a5e: 4618 mov r0, r3 8005a60: f00e fd78 bl 8014554 respStatus = spOK; 8005a64: 2300 movs r3, #0 8005a66: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005a6a: e12a b.n 8005cc2 respStatus = spInternalError; 8005a6c: 23fc movs r3, #252 @ 0xfc 8005a6e: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005a72: e126 b.n 8005cc2 case spSetCurrentMeasOffsets: if (osMutexAcquire (resMeasurementsMutex, osWaitForever) == osOK) { 8005a74: 4b54 ldr r3, [pc, #336] @ (8005bc8 ) 8005a76: 681b ldr r3, [r3, #0] 8005a78: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8005a7c: 4618 mov r0, r3 8005a7e: f00e fd1e bl 80144be 8005a82: 4603 mov r3, r0 8005a84: 2b00 cmp r3, #0 8005a86: d123 bne.n 8005ad0 for (uint8_t i = 0; i < 3; i++) { 8005a88: 2300 movs r3, #0 8005a8a: f887 3078 strb.w r3, [r7, #120] @ 0x78 8005a8e: e012 b.n 8005ab6 ReadWordFromBufer (spFrameData->dataBuffer, &inputDataBufferPos, (uint32_t*)&I_MeasCorrectionData[i].offset); 8005a90: 683b ldr r3, [r7, #0] 8005a92: f103 000c add.w r0, r3, #12 8005a96: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005a9a: 00db lsls r3, r3, #3 8005a9c: 4a4c ldr r2, [pc, #304] @ (8005bd0 ) 8005a9e: 4413 add r3, r2 8005aa0: 1d1a adds r2, r3, #4 8005aa2: f107 0344 add.w r3, r7, #68 @ 0x44 8005aa6: 4619 mov r1, r3 8005aa8: f7fd ffe4 bl 8003a74 for (uint8_t i = 0; i < 3; i++) { 8005aac: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005ab0: 3301 adds r3, #1 8005ab2: f887 3078 strb.w r3, [r7, #120] @ 0x78 8005ab6: f897 3078 ldrb.w r3, [r7, #120] @ 0x78 8005aba: 2b02 cmp r3, #2 8005abc: d9e8 bls.n 8005a90 } osMutexRelease (resMeasurementsMutex); 8005abe: 4b42 ldr r3, [pc, #264] @ (8005bc8 ) 8005ac0: 681b ldr r3, [r3, #0] 8005ac2: 4618 mov r0, r3 8005ac4: f00e fd46 bl 8014554 respStatus = spOK; 8005ac8: 2300 movs r3, #0 8005aca: f887 3097 strb.w r3, [r7, #151] @ 0x97 } else { respStatus = spInternalError; } break; 8005ace: e0f8 b.n 8005cc2 respStatus = spInternalError; 8005ad0: 23fc movs r3, #252 @ 0xfc 8005ad2: f887 3097 strb.w r3, [r7, #151] @ 0x97 break; 8005ad6: e0f4 b.n 8005cc2 __ASM volatile ("cpsid i" : : : "memory"); 8005ad8: b672 cpsid i } 8005ada: bf00 nop case spResetSystem: __disable_irq(); NVIC_SystemReset(); 8005adc: f7fe ff62 bl 80049a4 <__NVIC_SystemReset> break; case spSetPositonX: PositionControlTaskData posXData = { 0 }; 8005ae0: f04f 0300 mov.w r3, #0 8005ae4: 617b str r3, [r7, #20] if (positionXControlTaskInitArg.positionSettingQueue != NULL) 8005ae6: 4b3b ldr r3, [pc, #236] @ (8005bd4 ) 8005ae8: 691b ldr r3, [r3, #16] 8005aea: 2b00 cmp r3, #0 8005aec: f000 80e6 beq.w 8005cbc { float posXPercent = 0; 8005af0: f04f 0300 mov.w r3, #0 8005af4: 60fb str r3, [r7, #12] ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posXPercent); 8005af6: 683b ldr r3, [r7, #0] 8005af8: 330c adds r3, #12 8005afa: f107 020c add.w r2, r7, #12 8005afe: f107 0144 add.w r1, r7, #68 @ 0x44 8005b02: 4618 mov r0, r3 8005b04: f7fd ff81 bl 8003a0a float posXDegress = MAX_X_AXE_ANGLE * posXPercent * 0.01; 8005b08: edd7 7a03 vldr s15, [r7, #12] 8005b0c: ed9f 7a32 vldr s14, [pc, #200] @ 8005bd8 8005b10: ee67 7a87 vmul.f32 s15, s15, s14 8005b14: eeb7 7ae7 vcvt.f64.f32 d7, s15 8005b18: ed9f 6b27 vldr d6, [pc, #156] @ 8005bb8 8005b1c: ee27 7b06 vmul.f64 d7, d7, d6 8005b20: eef7 7bc7 vcvt.f32.f64 s15, d7 8005b24: edc7 7a18 vstr s15, [r7, #96] @ 0x60 float angleDelta = 360 / ENCODER_X_IMP_PER_TURN; 8005b28: 4b2c ldr r3, [pc, #176] @ (8005bdc ) 8005b2a: 65fb str r3, [r7, #92] @ 0x5c float rest = fmodf(posXDegress, angleDelta); 8005b2c: edd7 0a17 vldr s1, [r7, #92] @ 0x5c 8005b30: ed97 0a18 vldr s0, [r7, #96] @ 0x60 8005b34: f012 fcde bl 80184f4 8005b38: ed87 0a16 vstr s0, [r7, #88] @ 0x58 if ( rest > (angleDelta/2)) 8005b3c: ed97 7a17 vldr s14, [r7, #92] @ 0x5c 8005b40: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0 8005b44: eec7 7a26 vdiv.f32 s15, s14, s13 8005b48: ed97 7a16 vldr s14, [r7, #88] @ 0x58 8005b4c: eeb4 7ae7 vcmpe.f32 s14, s15 8005b50: eef1 fa10 vmrs APSR_nzcv, fpscr 8005b54: dd14 ble.n 8005b80 { posXData.positionSettingValue = 100 * (posXDegress - rest + angleDelta) / MAX_X_AXE_ANGLE; 8005b56: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005b5a: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8005b5e: ee37 7a67 vsub.f32 s14, s14, s15 8005b62: edd7 7a17 vldr s15, [r7, #92] @ 0x5c 8005b66: ee77 7a27 vadd.f32 s15, s14, s15 8005b6a: ed9f 7a1d vldr s14, [pc, #116] @ 8005be0 8005b6e: ee27 7a87 vmul.f32 s14, s15, s14 8005b72: eddf 6a19 vldr s13, [pc, #100] @ 8005bd8 8005b76: eec7 7a26 vdiv.f32 s15, s14, s13 8005b7a: edc7 7a05 vstr s15, [r7, #20] 8005b7e: e00f b.n 8005ba0 } else { posXData.positionSettingValue = 100 * (posXDegress - rest) / MAX_X_AXE_ANGLE; 8005b80: ed97 7a18 vldr s14, [r7, #96] @ 0x60 8005b84: edd7 7a16 vldr s15, [r7, #88] @ 0x58 8005b88: ee77 7a67 vsub.f32 s15, s14, s15 8005b8c: ed9f 7a14 vldr s14, [pc, #80] @ 8005be0 8005b90: ee27 7a87 vmul.f32 s14, s15, s14 8005b94: eddf 6a10 vldr s13, [pc, #64] @ 8005bd8 8005b98: eec7 7a26 vdiv.f32 s15, s14, s13 8005b9c: edc7 7a05 vstr s15, [r7, #20] } osMessageQueuePut(positionXControlTaskInitArg.positionSettingQueue, &posXData, 0, 0); 8005ba0: 4b0c ldr r3, [pc, #48] @ (8005bd4 ) 8005ba2: 6918 ldr r0, [r3, #16] 8005ba4: f107 0114 add.w r1, r7, #20 8005ba8: 2300 movs r3, #0 8005baa: 2200 movs r2, #0 8005bac: f00e fd82 bl 80146b4 } break; 8005bb0: e084 b.n 8005cbc 8005bb2: bf00 nop 8005bb4: f3af 8000 nop.w 8005bb8: 47ae147b .word 0x47ae147b 8005bbc: 3f847ae1 .word 0x3f847ae1 8005bc0: 2400081c .word 0x2400081c 8005bc4: 24000860 .word 0x24000860 8005bc8: 24000818 .word 0x24000818 8005bcc: 24000000 .word 0x24000000 8005bd0: 24000018 .word 0x24000018 8005bd4: 240008b4 .word 0x240008b4 8005bd8: 43b40000 .word 0x43b40000 8005bdc: 41900000 .word 0x41900000 8005be0: 42c80000 .word 0x42c80000 case spSetPositonY: PositionControlTaskData posYData = { 0 }; 8005be4: f04f 0300 mov.w r3, #0 8005be8: 613b str r3, [r7, #16] if (positionYControlTaskInitArg.positionSettingQueue != NULL) 8005bea: 4b4b ldr r3, [pc, #300] @ (8005d18 ) 8005bec: 691b ldr r3, [r3, #16] 8005bee: 2b00 cmp r3, #0 8005bf0: d066 beq.n 8005cc0 { float posYPercent = 0; 8005bf2: f04f 0300 mov.w r3, #0 8005bf6: 60bb str r3, [r7, #8] ReadFloatFromBuffer(spFrameData->dataBuffer, &inputDataBufferPos, &posYPercent); 8005bf8: 683b ldr r3, [r7, #0] 8005bfa: 330c adds r3, #12 8005bfc: f107 0208 add.w r2, r7, #8 8005c00: f107 0144 add.w r1, r7, #68 @ 0x44 8005c04: 4618 mov r0, r3 8005c06: f7fd ff00 bl 8003a0a float posYDegress = MAX_Y_AXE_ANGLE * posYPercent * 0.01; 8005c0a: edd7 7a02 vldr s15, [r7, #8] 8005c0e: ed9f 7a43 vldr s14, [pc, #268] @ 8005d1c 8005c12: ee67 7a87 vmul.f32 s15, s15, s14 8005c16: eeb7 7ae7 vcvt.f64.f32 d7, s15 8005c1a: ed9f 6b3d vldr d6, [pc, #244] @ 8005d10 8005c1e: ee27 7b06 vmul.f64 d7, d7, d6 8005c22: eef7 7bc7 vcvt.f32.f64 s15, d7 8005c26: edc7 7a1b vstr s15, [r7, #108] @ 0x6c float angleDelta = 360 / ENCODER_Y_IMP_PER_TURN; 8005c2a: 4b3d ldr r3, [pc, #244] @ (8005d20 ) 8005c2c: 66bb str r3, [r7, #104] @ 0x68 float rest = fmodf(posYDegress, angleDelta); 8005c2e: edd7 0a1a vldr s1, [r7, #104] @ 0x68 8005c32: ed97 0a1b vldr s0, [r7, #108] @ 0x6c 8005c36: f012 fc5d bl 80184f4 8005c3a: ed87 0a19 vstr s0, [r7, #100] @ 0x64 if ( rest > (angleDelta/2)) 8005c3e: ed97 7a1a vldr s14, [r7, #104] @ 0x68 8005c42: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0 8005c46: eec7 7a26 vdiv.f32 s15, s14, s13 8005c4a: ed97 7a19 vldr s14, [r7, #100] @ 0x64 8005c4e: eeb4 7ae7 vcmpe.f32 s14, s15 8005c52: eef1 fa10 vmrs APSR_nzcv, fpscr 8005c56: dd14 ble.n 8005c82 { posYData.positionSettingValue = 100 * (posYDegress - rest + angleDelta) / MAX_Y_AXE_ANGLE; 8005c58: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8005c5c: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8005c60: ee37 7a67 vsub.f32 s14, s14, s15 8005c64: edd7 7a1a vldr s15, [r7, #104] @ 0x68 8005c68: ee77 7a27 vadd.f32 s15, s14, s15 8005c6c: ed9f 7a2d vldr s14, [pc, #180] @ 8005d24 8005c70: ee27 7a87 vmul.f32 s14, s15, s14 8005c74: eddf 6a29 vldr s13, [pc, #164] @ 8005d1c 8005c78: eec7 7a26 vdiv.f32 s15, s14, s13 8005c7c: edc7 7a04 vstr s15, [r7, #16] 8005c80: e00f b.n 8005ca2 } else { posYData.positionSettingValue = 100 * (posYDegress - rest) / MAX_Y_AXE_ANGLE; 8005c82: ed97 7a1b vldr s14, [r7, #108] @ 0x6c 8005c86: edd7 7a19 vldr s15, [r7, #100] @ 0x64 8005c8a: ee77 7a67 vsub.f32 s15, s14, s15 8005c8e: ed9f 7a25 vldr s14, [pc, #148] @ 8005d24 8005c92: ee27 7a87 vmul.f32 s14, s15, s14 8005c96: eddf 6a21 vldr s13, [pc, #132] @ 8005d1c 8005c9a: eec7 7a26 vdiv.f32 s15, s14, s13 8005c9e: edc7 7a04 vstr s15, [r7, #16] } osMessageQueuePut(positionYControlTaskInitArg.positionSettingQueue, &posYData, 0, 0); 8005ca2: 4b1d ldr r3, [pc, #116] @ (8005d18 ) 8005ca4: 6918 ldr r0, [r3, #16] 8005ca6: f107 0110 add.w r1, r7, #16 8005caa: 2300 movs r3, #0 8005cac: 2200 movs r2, #0 8005cae: f00e fd01 bl 80146b4 } break; 8005cb2: e005 b.n 8005cc0 default: respStatus = spUnknownCommand; break; 8005cb4: 23fd movs r3, #253 @ 0xfd 8005cb6: f887 3097 strb.w r3, [r7, #151] @ 0x97 8005cba: e002 b.n 8005cc2 break; 8005cbc: bf00 nop 8005cbe: e000 b.n 8005cc2 break; 8005cc0: bf00 nop } dataToSend = PrepareRespFrame (uartTaskData->uartTxBuffer, spFrameData->frameHeader.frameId, spFrameData->frameHeader.frameCommand, respStatus, outputDataBuffer, outputDataBufferPos); 8005cc2: 6f7b ldr r3, [r7, #116] @ 0x74 8005cc4: 6898 ldr r0, [r3, #8] 8005cc6: 683b ldr r3, [r7, #0] 8005cc8: 8819 ldrh r1, [r3, #0] 8005cca: 683b ldr r3, [r7, #0] 8005ccc: 789a ldrb r2, [r3, #2] 8005cce: 4b16 ldr r3, [pc, #88] @ (8005d28 ) 8005cd0: 881b ldrh r3, [r3, #0] 8005cd2: f997 4097 ldrsb.w r4, [r7, #151] @ 0x97 8005cd6: 9301 str r3, [sp, #4] 8005cd8: 4b14 ldr r3, [pc, #80] @ (8005d2c ) 8005cda: 9300 str r3, [sp, #0] 8005cdc: 4623 mov r3, r4 8005cde: f7fd fefd bl 8003adc 8005ce2: 4603 mov r3, r0 8005ce4: f8a7 3072 strh.w r3, [r7, #114] @ 0x72 if (dataToSend > 0) { 8005ce8: f8b7 3072 ldrh.w r3, [r7, #114] @ 0x72 8005cec: 2b00 cmp r3, #0 8005cee: d008 beq.n 8005d02 HAL_UART_Transmit_IT (uartTaskData->huart, uartTaskData->uartTxBuffer, dataToSend); 8005cf0: 6f7b ldr r3, [r7, #116] @ 0x74 8005cf2: 6b18 ldr r0, [r3, #48] @ 0x30 8005cf4: 6f7b ldr r3, [r7, #116] @ 0x74 8005cf6: 689b ldr r3, [r3, #8] 8005cf8: f8b7 2072 ldrh.w r2, [r7, #114] @ 0x72 8005cfc: 4619 mov r1, r3 8005cfe: f00b fbb1 bl 8011464 } #ifdef SERIAL_PROTOCOL_DBG printf ("Uart%d: TX bytes sent: %d\n", uartTaskData->uartNumber, dataToSend); #endif } 8005d02: bf00 nop 8005d04: 379c adds r7, #156 @ 0x9c 8005d06: 46bd mov sp, r7 8005d08: bd90 pop {r4, r7, pc} 8005d0a: bf00 nop 8005d0c: f3af 8000 nop.w 8005d10: 47ae147b .word 0x47ae147b 8005d14: 3f847ae1 .word 0x3f847ae1 8005d18: 240008e8 .word 0x240008e8 8005d1c: 43b40000 .word 0x43b40000 8005d20: 41900000 .word 0x41900000 8005d24: 42c80000 .word 0x42c80000 8005d28: 2400105c .word 0x2400105c 8005d2c: 24000fdc .word 0x24000fdc 08005d30 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8005d30: f8df d034 ldr.w sp, [pc, #52] @ 8005d68 /* Call the clock system initialization function.*/ bl SystemInit 8005d34: f7fe fdae bl 8004894 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8005d38: 480c ldr r0, [pc, #48] @ (8005d6c ) ldr r1, =_edata 8005d3a: 490d ldr r1, [pc, #52] @ (8005d70 ) ldr r2, =_sidata 8005d3c: 4a0d ldr r2, [pc, #52] @ (8005d74 ) movs r3, #0 8005d3e: 2300 movs r3, #0 b LoopCopyDataInit 8005d40: e002 b.n 8005d48 08005d42 : CopyDataInit: ldr r4, [r2, r3] 8005d42: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8005d44: 50c4 str r4, [r0, r3] adds r3, r3, #4 8005d46: 3304 adds r3, #4 08005d48 : LoopCopyDataInit: adds r4, r0, r3 8005d48: 18c4 adds r4, r0, r3 cmp r4, r1 8005d4a: 428c cmp r4, r1 bcc CopyDataInit 8005d4c: d3f9 bcc.n 8005d42 /* Zero fill the bss segment. */ ldr r2, =_sbss 8005d4e: 4a0a ldr r2, [pc, #40] @ (8005d78 ) ldr r4, =_ebss 8005d50: 4c0a ldr r4, [pc, #40] @ (8005d7c ) movs r3, #0 8005d52: 2300 movs r3, #0 b LoopFillZerobss 8005d54: e001 b.n 8005d5a 08005d56 : FillZerobss: str r3, [r2] 8005d56: 6013 str r3, [r2, #0] adds r2, r2, #4 8005d58: 3204 adds r2, #4 08005d5a : LoopFillZerobss: cmp r2, r4 8005d5a: 42a2 cmp r2, r4 bcc FillZerobss 8005d5c: d3fb bcc.n 8005d56 /* Call static constructors */ bl __libc_init_array 8005d5e: f012 fb3f bl 80183e0 <__libc_init_array> /* Call the application's entry point.*/ bl main 8005d62: f7fa fc77 bl 8000654
bx lr 8005d66: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8005d68: 24060000 .word 0x24060000 ldr r0, =_sdata 8005d6c: 24000000 .word 0x24000000 ldr r1, =_edata 8005d70: 24000098 .word 0x24000098 ldr r2, =_sidata 8005d74: 08018764 .word 0x08018764 ldr r2, =_sbss 8005d78: 240000a0 .word 0x240000a0 ldr r4, =_ebss 8005d7c: 2401318c .word 0x2401318c 08005d80 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8005d80: e7fe b.n 8005d80 ... 08005d84 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8005d84: b580 push {r7, lr} 8005d86: b082 sub sp, #8 8005d88: af00 add r7, sp, #0 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ #endif /* DUAL_CORE && CORE_CM4 */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8005d8a: 2003 movs r0, #3 8005d8c: f001 fee5 bl 8007b5a /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 8005d90: f006 fbee bl 800c570 8005d94: 4602 mov r2, r0 8005d96: 4b15 ldr r3, [pc, #84] @ (8005dec ) 8005d98: 699b ldr r3, [r3, #24] 8005d9a: 0a1b lsrs r3, r3, #8 8005d9c: f003 030f and.w r3, r3, #15 8005da0: 4913 ldr r1, [pc, #76] @ (8005df0 ) 8005da2: 5ccb ldrb r3, [r1, r3] 8005da4: f003 031f and.w r3, r3, #31 8005da8: fa22 f303 lsr.w r3, r2, r3 8005dac: 607b str r3, [r7, #4] common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 8005dae: 4b0f ldr r3, [pc, #60] @ (8005dec ) 8005db0: 699b ldr r3, [r3, #24] 8005db2: f003 030f and.w r3, r3, #15 8005db6: 4a0e ldr r2, [pc, #56] @ (8005df0 ) 8005db8: 5cd3 ldrb r3, [r2, r3] 8005dba: f003 031f and.w r3, r3, #31 8005dbe: 687a ldr r2, [r7, #4] 8005dc0: fa22 f303 lsr.w r3, r2, r3 8005dc4: 4a0b ldr r2, [pc, #44] @ (8005df4 ) 8005dc6: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 8005dc8: 4a0b ldr r2, [pc, #44] @ (8005df8 ) 8005dca: 687b ldr r3, [r7, #4] 8005dcc: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8005dce: 2005 movs r0, #5 8005dd0: f7fe fc58 bl 8004684 8005dd4: 4603 mov r3, r0 8005dd6: 2b00 cmp r3, #0 8005dd8: d001 beq.n 8005dde { return HAL_ERROR; 8005dda: 2301 movs r3, #1 8005ddc: e002 b.n 8005de4 } /* Init the low level hardware */ HAL_MspInit(); 8005dde: f7fd ff1b bl 8003c18 /* Return function status */ return HAL_OK; 8005de2: 2300 movs r3, #0 } 8005de4: 4618 mov r0, r3 8005de6: 3708 adds r7, #8 8005de8: 46bd mov sp, r7 8005dea: bd80 pop {r7, pc} 8005dec: 58024400 .word 0x58024400 8005df0: 0801870c .word 0x0801870c 8005df4: 24000038 .word 0x24000038 8005df8: 24000034 .word 0x24000034 08005dfc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8005dfc: b480 push {r7} 8005dfe: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 8005e00: 4b06 ldr r3, [pc, #24] @ (8005e1c ) 8005e02: 781b ldrb r3, [r3, #0] 8005e04: 461a mov r2, r3 8005e06: 4b06 ldr r3, [pc, #24] @ (8005e20 ) 8005e08: 681b ldr r3, [r3, #0] 8005e0a: 4413 add r3, r2 8005e0c: 4a04 ldr r2, [pc, #16] @ (8005e20 ) 8005e0e: 6013 str r3, [r2, #0] } 8005e10: bf00 nop 8005e12: 46bd mov sp, r7 8005e14: f85d 7b04 ldr.w r7, [sp], #4 8005e18: 4770 bx lr 8005e1a: bf00 nop 8005e1c: 24000040 .word 0x24000040 8005e20: 24001060 .word 0x24001060 08005e24 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8005e24: b480 push {r7} 8005e26: af00 add r7, sp, #0 return uwTick; 8005e28: 4b03 ldr r3, [pc, #12] @ (8005e38 ) 8005e2a: 681b ldr r3, [r3, #0] } 8005e2c: 4618 mov r0, r3 8005e2e: 46bd mov sp, r7 8005e30: f85d 7b04 ldr.w r7, [sp], #4 8005e34: 4770 bx lr 8005e36: bf00 nop 8005e38: 24001060 .word 0x24001060 08005e3c : /** * @brief Returns the device revision identifier. * @retval Device revision identifier */ uint32_t HAL_GetREVID(void) { 8005e3c: b480 push {r7} 8005e3e: af00 add r7, sp, #0 return((DBGMCU->IDCODE) >> 16); 8005e40: 4b03 ldr r3, [pc, #12] @ (8005e50 ) 8005e42: 681b ldr r3, [r3, #0] 8005e44: 0c1b lsrs r3, r3, #16 } 8005e46: 4618 mov r0, r3 8005e48: 46bd mov sp, r7 8005e4a: f85d 7b04 ldr.w r7, [sp], #4 8005e4e: 4770 bx lr 8005e50: 5c001000 .word 0x5c001000 08005e54 : * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. * @retval None */ void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) { 8005e54: b480 push {r7} 8005e56: b083 sub sp, #12 8005e58: af00 add r7, sp, #0 8005e5a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); 8005e5c: 4b06 ldr r3, [pc, #24] @ (8005e78 ) 8005e5e: 681b ldr r3, [r3, #0] 8005e60: f023 0202 bic.w r2, r3, #2 8005e64: 4904 ldr r1, [pc, #16] @ (8005e78 ) 8005e66: 687b ldr r3, [r7, #4] 8005e68: 4313 orrs r3, r2 8005e6a: 600b str r3, [r1, #0] } 8005e6c: bf00 nop 8005e6e: 370c adds r7, #12 8005e70: 46bd mov sp, r7 8005e72: f85d 7b04 ldr.w r7, [sp], #4 8005e76: 4770 bx lr 8005e78: 58003c00 .word 0x58003c00 08005e7c : * @brief Disable the Internal Voltage Reference buffer (VREFBUF). * * @retval None */ void HAL_SYSCFG_DisableVREFBUF(void) { 8005e7c: b480 push {r7} 8005e7e: af00 add r7, sp, #0 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); 8005e80: 4b05 ldr r3, [pc, #20] @ (8005e98 ) 8005e82: 681b ldr r3, [r3, #0] 8005e84: 4a04 ldr r2, [pc, #16] @ (8005e98 ) 8005e86: f023 0301 bic.w r3, r3, #1 8005e8a: 6013 str r3, [r2, #0] } 8005e8c: bf00 nop 8005e8e: 46bd mov sp, r7 8005e90: f85d 7b04 ldr.w r7, [sp], #4 8005e94: 4770 bx lr 8005e96: bf00 nop 8005e98: 58003c00 .word 0x58003c00 08005e9c : * @arg SYSCFG_SWITCH_PC3_CLOSE * @retval None */ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) { 8005e9c: b480 push {r7} 8005e9e: b083 sub sp, #12 8005ea0: af00 add r7, sp, #0 8005ea2: 6078 str r0, [r7, #4] 8005ea4: 6039 str r1, [r7, #0] /* Check the parameter */ assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); 8005ea6: 4b07 ldr r3, [pc, #28] @ (8005ec4 ) 8005ea8: 685a ldr r2, [r3, #4] 8005eaa: 687b ldr r3, [r7, #4] 8005eac: 43db mvns r3, r3 8005eae: 401a ands r2, r3 8005eb0: 4904 ldr r1, [pc, #16] @ (8005ec4 ) 8005eb2: 683b ldr r3, [r7, #0] 8005eb4: 4313 orrs r3, r2 8005eb6: 604b str r3, [r1, #4] } 8005eb8: bf00 nop 8005eba: 370c adds r7, #12 8005ebc: 46bd mov sp, r7 8005ebe: f85d 7b04 ldr.w r7, [sp], #4 8005ec2: 4770 bx lr 8005ec4: 58000400 .word 0x58000400 08005ec8 : * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) { 8005ec8: b480 push {r7} 8005eca: b083 sub sp, #12 8005ecc: af00 add r7, sp, #0 8005ece: 6078 str r0, [r7, #4] 8005ed0: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock); 8005ed2: 687b ldr r3, [r7, #4] 8005ed4: 689b ldr r3, [r3, #8] 8005ed6: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000 8005eda: 683b ldr r3, [r7, #0] 8005edc: 431a orrs r2, r3 8005ede: 687b ldr r3, [r7, #4] 8005ee0: 609a str r2, [r3, #8] } 8005ee2: bf00 nop 8005ee4: 370c adds r7, #12 8005ee6: 46bd mov sp, r7 8005ee8: f85d 7b04 ldr.w r7, [sp], #4 8005eec: 4770 bx lr 08005eee : * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT * @retval None */ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) { 8005eee: b480 push {r7} 8005ef0: b083 sub sp, #12 8005ef2: af00 add r7, sp, #0 8005ef4: 6078 str r0, [r7, #4] 8005ef6: 6039 str r1, [r7, #0] MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); 8005ef8: 687b ldr r3, [r7, #4] 8005efa: 689b ldr r3, [r3, #8] 8005efc: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000 8005f00: 683b ldr r3, [r7, #0] 8005f02: 431a orrs r2, r3 8005f04: 687b ldr r3, [r7, #4] 8005f06: 609a str r2, [r3, #8] } 8005f08: bf00 nop 8005f0a: 370c adds r7, #12 8005f0c: 46bd mov sp, r7 8005f0e: f85d 7b04 ldr.w r7, [sp], #4 8005f12: 4770 bx lr 08005f14 : * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) { 8005f14: b480 push {r7} 8005f16: b083 sub sp, #12 8005f18: af00 add r7, sp, #0 8005f1a: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); 8005f1c: 687b ldr r3, [r7, #4] 8005f1e: 689b ldr r3, [r3, #8] 8005f20: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000 } 8005f24: 4618 mov r0, r3 8005f26: 370c adds r7, #12 8005f28: 46bd mov sp, r7 8005f2a: f85d 7b04 ldr.w r7, [sp], #4 8005f2e: 4770 bx lr 08005f30 : * Other channels are slow channels (conversion rate: refer to reference manual). * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) { 8005f30: b480 push {r7} 8005f32: b087 sub sp, #28 8005f34: af00 add r7, sp, #0 8005f36: 60f8 str r0, [r7, #12] 8005f38: 60b9 str r1, [r7, #8] 8005f3a: 607a str r2, [r7, #4] 8005f3c: 603b str r3, [r7, #0] __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005f3e: 68fb ldr r3, [r7, #12] 8005f40: 3360 adds r3, #96 @ 0x60 8005f42: 461a mov r2, r3 8005f44: 68bb ldr r3, [r7, #8] 8005f46: 009b lsls r3, r3, #2 8005f48: 4413 add r3, r2 8005f4a: 617b str r3, [r7, #20] ADC3_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } else #endif /* ADC_VER_V5_V90 */ { MODIFY_REG(*preg, 8005f4c: 697b ldr r3, [r7, #20] 8005f4e: 681b ldr r3, [r3, #0] 8005f50: f003 4200 and.w r2, r3, #2147483648 @ 0x80000000 8005f54: 687b ldr r3, [r7, #4] 8005f56: f003 41f8 and.w r1, r3, #2080374784 @ 0x7c000000 8005f5a: 683b ldr r3, [r7, #0] 8005f5c: 430b orrs r3, r1 8005f5e: 431a orrs r2, r3 8005f60: 697b ldr r3, [r7, #20] 8005f62: 601a str r2, [r3, #0] ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1, (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel); } } 8005f64: bf00 nop 8005f66: 371c adds r7, #28 8005f68: 46bd mov sp, r7 8005f6a: f85d 7b04 ldr.w r7, [sp], #4 8005f6e: 4770 bx lr 08005f70 : * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift) { 8005f70: b480 push {r7} 8005f72: b085 sub sp, #20 8005f74: af00 add r7, sp, #0 8005f76: 60f8 str r0, [r7, #12] 8005f78: 60b9 str r1, [r7, #8] 8005f7a: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL)); 8005f7c: 68fb ldr r3, [r7, #12] 8005f7e: 691b ldr r3, [r3, #16] 8005f80: f423 42f0 bic.w r2, r3, #30720 @ 0x7800 8005f84: 68bb ldr r3, [r7, #8] 8005f86: f003 031f and.w r3, r3, #31 8005f8a: 6879 ldr r1, [r7, #4] 8005f8c: fa01 f303 lsl.w r3, r1, r3 8005f90: 431a orrs r2, r3 8005f92: 68fb ldr r3, [r7, #12] 8005f94: 611a str r2, [r3, #16] } 8005f96: bf00 nop 8005f98: 3714 adds r7, #20 8005f9a: 46bd mov sp, r7 8005f9c: f85d 7b04 ldr.w r7, [sp], #4 8005fa0: 4770 bx lr 08005fa2 : * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE * @retval Returned None */ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation) { 8005fa2: b480 push {r7} 8005fa4: b087 sub sp, #28 8005fa6: af00 add r7, sp, #0 8005fa8: 60f8 str r0, [r7, #12] 8005faa: 60b9 str r1, [r7, #8] 8005fac: 607a str r2, [r7, #4] /* Function not available on this instance */ } else #endif /* ADC_VER_V5_V90 */ { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); 8005fae: 68fb ldr r3, [r7, #12] 8005fb0: 3360 adds r3, #96 @ 0x60 8005fb2: 461a mov r2, r3 8005fb4: 68bb ldr r3, [r7, #8] 8005fb6: 009b lsls r3, r3, #2 8005fb8: 4413 add r3, r2 8005fba: 617b str r3, [r7, #20] MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation); 8005fbc: 697b ldr r3, [r7, #20] 8005fbe: 681b ldr r3, [r3, #0] 8005fc0: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000 8005fc4: 687b ldr r3, [r7, #4] 8005fc6: 431a orrs r2, r3 8005fc8: 697b ldr r3, [r7, #20] 8005fca: 601a str r2, [r3, #0] } } 8005fcc: bf00 nop 8005fce: 371c adds r7, #28 8005fd0: 46bd mov sp, r7 8005fd2: f85d 7b04 ldr.w r7, [sp], #4 8005fd6: 4770 bx lr 08005fd8 : * @param ADCx ADC instance * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) { 8005fd8: b480 push {r7} 8005fda: b083 sub sp, #12 8005fdc: af00 add r7, sp, #0 8005fde: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); 8005fe0: 687b ldr r3, [r7, #4] 8005fe2: 68db ldr r3, [r3, #12] 8005fe4: f403 6340 and.w r3, r3, #3072 @ 0xc00 8005fe8: 2b00 cmp r3, #0 8005fea: d101 bne.n 8005ff0 8005fec: 2301 movs r3, #1 8005fee: e000 b.n 8005ff2 8005ff0: 2300 movs r3, #0 } 8005ff2: 4618 mov r0, r3 8005ff4: 370c adds r7, #12 8005ff6: 46bd mov sp, r7 8005ff8: f85d 7b04 ldr.w r7, [sp], #4 8005ffc: 4770 bx lr 08005ffe : * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) { 8005ffe: b480 push {r7} 8006000: b087 sub sp, #28 8006002: af00 add r7, sp, #0 8006004: 60f8 str r0, [r7, #12] 8006006: 60b9 str r1, [r7, #8] 8006008: 607a str r2, [r7, #4] /* Set bits with content of parameter "Channel" with bits position */ /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); 800600a: 68fb ldr r3, [r7, #12] 800600c: 3330 adds r3, #48 @ 0x30 800600e: 461a mov r2, r3 8006010: 68bb ldr r3, [r7, #8] 8006012: 0a1b lsrs r3, r3, #8 8006014: 009b lsls r3, r3, #2 8006016: f003 030c and.w r3, r3, #12 800601a: 4413 add r3, r2 800601c: 617b str r3, [r7, #20] MODIFY_REG(*preg, 800601e: 697b ldr r3, [r7, #20] 8006020: 681a ldr r2, [r3, #0] 8006022: 68bb ldr r3, [r7, #8] 8006024: f003 031f and.w r3, r3, #31 8006028: 211f movs r1, #31 800602a: fa01 f303 lsl.w r3, r1, r3 800602e: 43db mvns r3, r3 8006030: 401a ands r2, r3 8006032: 687b ldr r3, [r7, #4] 8006034: 0e9b lsrs r3, r3, #26 8006036: f003 011f and.w r1, r3, #31 800603a: 68bb ldr r3, [r7, #8] 800603c: f003 031f and.w r3, r3, #31 8006040: fa01 f303 lsl.w r3, r1, r3 8006044: 431a orrs r2, r3 8006046: 697b ldr r3, [r7, #20] 8006048: 601a str r2, [r3, #0] ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } 800604a: bf00 nop 800604c: 371c adds r7, #28 800604e: 46bd mov sp, r7 8006050: f85d 7b04 ldr.w r7, [sp], #4 8006054: 4770 bx lr 08006056 : * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration * @retval None */ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode) { 8006056: b480 push {r7} 8006058: b083 sub sp, #12 800605a: af00 add r7, sp, #0 800605c: 6078 str r0, [r7, #4] 800605e: 6039 str r1, [r7, #0] MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode); 8006060: 687b ldr r3, [r7, #4] 8006062: 68db ldr r3, [r3, #12] 8006064: f023 0203 bic.w r2, r3, #3 8006068: 683b ldr r3, [r7, #0] 800606a: 431a orrs r2, r3 800606c: 687b ldr r3, [r7, #4] 800606e: 60da str r2, [r3, #12] } 8006070: bf00 nop 8006072: 370c adds r7, #12 8006074: 46bd mov sp, r7 8006076: f85d 7b04 ldr.w r7, [sp], #4 800607a: 4770 bx lr 0800607c : * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) { 800607c: b480 push {r7} 800607e: b087 sub sp, #28 8006080: af00 add r7, sp, #0 8006082: 60f8 str r0, [r7, #12] 8006084: 60b9 str r1, [r7, #8] 8006086: 607a str r2, [r7, #4] /* Set bits with content of parameter "SamplingTime" with bits position */ /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); 8006088: 68fb ldr r3, [r7, #12] 800608a: 3314 adds r3, #20 800608c: 461a mov r2, r3 800608e: 68bb ldr r3, [r7, #8] 8006090: 0e5b lsrs r3, r3, #25 8006092: 009b lsls r3, r3, #2 8006094: f003 0304 and.w r3, r3, #4 8006098: 4413 add r3, r2 800609a: 617b str r3, [r7, #20] MODIFY_REG(*preg, 800609c: 697b ldr r3, [r7, #20] 800609e: 681a ldr r2, [r3, #0] 80060a0: 68bb ldr r3, [r7, #8] 80060a2: 0d1b lsrs r3, r3, #20 80060a4: f003 031f and.w r3, r3, #31 80060a8: 2107 movs r1, #7 80060aa: fa01 f303 lsl.w r3, r1, r3 80060ae: 43db mvns r3, r3 80060b0: 401a ands r2, r3 80060b2: 68bb ldr r3, [r7, #8] 80060b4: 0d1b lsrs r3, r3, #20 80060b6: f003 031f and.w r3, r3, #31 80060ba: 6879 ldr r1, [r7, #4] 80060bc: fa01 f303 lsl.w r3, r1, r3 80060c0: 431a orrs r2, r3 80060c2: 697b ldr r3, [r7, #20] 80060c4: 601a str r2, [r3, #0] ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS), SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)); } 80060c6: bf00 nop 80060c8: 371c adds r7, #28 80060ca: 46bd mov sp, r7 80060cc: f85d 7b04 ldr.w r7, [sp], #4 80060d0: 4770 bx lr ... 080060d4 : * @arg @ref LL_ADC_SINGLE_ENDED * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval None */ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff) { 80060d4: b480 push {r7} 80060d6: b085 sub sp, #20 80060d8: af00 add r7, sp, #0 80060da: 60f8 str r0, [r7, #12] 80060dc: 60b9 str r1, [r7, #8] 80060de: 607a str r2, [r7, #4] } #else /* ADC_VER_V5_V90 */ /* Bits of channels in single or differential mode are set only for */ /* differential mode (for single mode, mask of bits allowed to be set is */ /* shifted out of range of bits of channels in single or differential mode. */ MODIFY_REG(ADCx->DIFSEL, 80060e0: 68fb ldr r3, [r7, #12] 80060e2: f8d3 20c0 ldr.w r2, [r3, #192] @ 0xc0 80060e6: 68bb ldr r3, [r7, #8] 80060e8: f3c3 0313 ubfx r3, r3, #0, #20 80060ec: 43db mvns r3, r3 80060ee: 401a ands r2, r3 80060f0: 687b ldr r3, [r7, #4] 80060f2: f003 0318 and.w r3, r3, #24 80060f6: 4908 ldr r1, [pc, #32] @ (8006118 ) 80060f8: 40d9 lsrs r1, r3 80060fa: 68bb ldr r3, [r7, #8] 80060fc: 400b ands r3, r1 80060fe: f3c3 0313 ubfx r3, r3, #0, #20 8006102: 431a orrs r2, r3 8006104: 68fb ldr r3, [r7, #12] 8006106: f8c3 20c0 str.w r2, [r3, #192] @ 0xc0 Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); #endif /* ADC_VER_V5_V90 */ } 800610a: bf00 nop 800610c: 3714 adds r7, #20 800610e: 46bd mov sp, r7 8006110: f85d 7b04 ldr.w r7, [sp], #4 8006114: 4770 bx lr 8006116: bf00 nop 8006118: 000fffff .word 0x000fffff 0800611c : * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) { 800611c: b480 push {r7} 800611e: b083 sub sp, #12 8006120: af00 add r7, sp, #0 8006122: 6078 str r0, [r7, #4] return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); 8006124: 687b ldr r3, [r7, #4] 8006126: 689b ldr r3, [r3, #8] 8006128: f003 031f and.w r3, r3, #31 } 800612c: 4618 mov r0, r3 800612e: 370c adds r7, #12 8006130: 46bd mov sp, r7 8006132: f85d 7b04 ldr.w r7, [sp], #4 8006136: 4770 bx lr 08006138 : * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) { 8006138: b480 push {r7} 800613a: b083 sub sp, #12 800613c: af00 add r7, sp, #0 800613e: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS)); 8006140: 687b ldr r3, [r7, #4] 8006142: 689a ldr r2, [r3, #8] 8006144: 4b04 ldr r3, [pc, #16] @ (8006158 ) 8006146: 4013 ands r3, r2 8006148: 687a ldr r2, [r7, #4] 800614a: 6093 str r3, [r2, #8] } 800614c: bf00 nop 800614e: 370c adds r7, #12 8006150: 46bd mov sp, r7 8006152: f85d 7b04 ldr.w r7, [sp], #4 8006156: 4770 bx lr 8006158: 5fffffc0 .word 0x5fffffc0 0800615c : * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) { 800615c: b480 push {r7} 800615e: b083 sub sp, #12 8006160: af00 add r7, sp, #0 8006162: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); 8006164: 687b ldr r3, [r7, #4] 8006166: 689b ldr r3, [r3, #8] 8006168: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800616c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8006170: d101 bne.n 8006176 8006172: 2301 movs r3, #1 8006174: e000 b.n 8006178 8006176: 2300 movs r3, #0 } 8006178: 4618 mov r0, r3 800617a: 370c adds r7, #12 800617c: 46bd mov sp, r7 800617e: f85d 7b04 ldr.w r7, [sp], #4 8006182: 4770 bx lr 08006184 : * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) { 8006184: b480 push {r7} 8006186: b083 sub sp, #12 8006188: af00 add r7, sp, #0 800618a: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 800618c: 687b ldr r3, [r7, #4] 800618e: 689a ldr r2, [r3, #8] 8006190: 4b05 ldr r3, [pc, #20] @ (80061a8 ) 8006192: 4013 ands r3, r2 8006194: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000 8006198: 687b ldr r3, [r7, #4] 800619a: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADVREGEN); } 800619c: bf00 nop 800619e: 370c adds r7, #12 80061a0: 46bd mov sp, r7 80061a2: f85d 7b04 ldr.w r7, [sp], #4 80061a6: 4770 bx lr 80061a8: 6fffffc0 .word 0x6fffffc0 080061ac : * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) { 80061ac: b480 push {r7} 80061ae: b083 sub sp, #12 80061b0: af00 add r7, sp, #0 80061b2: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); 80061b4: 687b ldr r3, [r7, #4] 80061b6: 689b ldr r3, [r3, #8] 80061b8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80061bc: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80061c0: d101 bne.n 80061c6 80061c2: 2301 movs r3, #1 80061c4: e000 b.n 80061c8 80061c6: 2300 movs r3, #0 } 80061c8: 4618 mov r0, r3 80061ca: 370c adds r7, #12 80061cc: 46bd mov sp, r7 80061ce: f85d 7b04 ldr.w r7, [sp], #4 80061d2: 4770 bx lr 080061d4 : * @rmtoll CR ADEN LL_ADC_Enable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) { 80061d4: b480 push {r7} 80061d6: b083 sub sp, #12 80061d8: af00 add r7, sp, #0 80061da: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 80061dc: 687b ldr r3, [r7, #4] 80061de: 689a ldr r2, [r3, #8] 80061e0: 4b05 ldr r3, [pc, #20] @ (80061f8 ) 80061e2: 4013 ands r3, r2 80061e4: f043 0201 orr.w r2, r3, #1 80061e8: 687b ldr r3, [r7, #4] 80061ea: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADEN); } 80061ec: bf00 nop 80061ee: 370c adds r7, #12 80061f0: 46bd mov sp, r7 80061f2: f85d 7b04 ldr.w r7, [sp], #4 80061f6: 4770 bx lr 80061f8: 7fffffc0 .word 0x7fffffc0 080061fc : * @rmtoll CR ADDIS LL_ADC_Disable * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) { 80061fc: b480 push {r7} 80061fe: b083 sub sp, #12 8006200: af00 add r7, sp, #0 8006202: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8006204: 687b ldr r3, [r7, #4] 8006206: 689a ldr r2, [r3, #8] 8006208: 4b05 ldr r3, [pc, #20] @ (8006220 ) 800620a: 4013 ands r3, r2 800620c: f043 0202 orr.w r2, r3, #2 8006210: 687b ldr r3, [r7, #4] 8006212: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADDIS); } 8006214: bf00 nop 8006216: 370c adds r7, #12 8006218: 46bd mov sp, r7 800621a: f85d 7b04 ldr.w r7, [sp], #4 800621e: 4770 bx lr 8006220: 7fffffc0 .word 0x7fffffc0 08006224 : * @rmtoll CR ADEN LL_ADC_IsEnabled * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) { 8006224: b480 push {r7} 8006226: b083 sub sp, #12 8006228: af00 add r7, sp, #0 800622a: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 800622c: 687b ldr r3, [r7, #4] 800622e: 689b ldr r3, [r3, #8] 8006230: f003 0301 and.w r3, r3, #1 8006234: 2b01 cmp r3, #1 8006236: d101 bne.n 800623c 8006238: 2301 movs r3, #1 800623a: e000 b.n 800623e 800623c: 2300 movs r3, #0 } 800623e: 4618 mov r0, r3 8006240: 370c adds r7, #12 8006242: 46bd mov sp, r7 8006244: f85d 7b04 ldr.w r7, [sp], #4 8006248: 4770 bx lr 0800624a : * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) { 800624a: b480 push {r7} 800624c: b083 sub sp, #12 800624e: af00 add r7, sp, #0 8006250: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); 8006252: 687b ldr r3, [r7, #4] 8006254: 689b ldr r3, [r3, #8] 8006256: f003 0302 and.w r3, r3, #2 800625a: 2b02 cmp r3, #2 800625c: d101 bne.n 8006262 800625e: 2301 movs r3, #1 8006260: e000 b.n 8006264 8006262: 2300 movs r3, #0 } 8006264: 4618 mov r0, r3 8006266: 370c adds r7, #12 8006268: 46bd mov sp, r7 800626a: f85d 7b04 ldr.w r7, [sp], #4 800626e: 4770 bx lr 08006270 : * @rmtoll CR ADSTART LL_ADC_REG_StartConversion * @param ADCx ADC instance * @retval None */ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) { 8006270: b480 push {r7} 8006272: b083 sub sp, #12 8006274: af00 add r7, sp, #0 8006276: 6078 str r0, [r7, #4] /* Note: Write register with some additional bits forced to state reset */ /* instead of modifying only the selected bit for this function, */ /* to not interfere with bits with HW property "rs". */ MODIFY_REG(ADCx->CR, 8006278: 687b ldr r3, [r7, #4] 800627a: 689a ldr r2, [r3, #8] 800627c: 4b05 ldr r3, [pc, #20] @ (8006294 ) 800627e: 4013 ands r3, r2 8006280: f043 0204 orr.w r2, r3, #4 8006284: 687b ldr r3, [r7, #4] 8006286: 609a str r2, [r3, #8] ADC_CR_BITS_PROPERTY_RS, ADC_CR_ADSTART); } 8006288: bf00 nop 800628a: 370c adds r7, #12 800628c: 46bd mov sp, r7 800628e: f85d 7b04 ldr.w r7, [sp], #4 8006292: 4770 bx lr 8006294: 7fffffc0 .word 0x7fffffc0 08006298 : * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) { 8006298: b480 push {r7} 800629a: b083 sub sp, #12 800629c: af00 add r7, sp, #0 800629e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 80062a0: 687b ldr r3, [r7, #4] 80062a2: 689b ldr r3, [r3, #8] 80062a4: f003 0304 and.w r3, r3, #4 80062a8: 2b04 cmp r3, #4 80062aa: d101 bne.n 80062b0 80062ac: 2301 movs r3, #1 80062ae: e000 b.n 80062b2 80062b0: 2300 movs r3, #0 } 80062b2: 4618 mov r0, r3 80062b4: 370c adds r7, #12 80062b6: 46bd mov sp, r7 80062b8: f85d 7b04 ldr.w r7, [sp], #4 80062bc: 4770 bx lr 080062be : * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) { 80062be: b480 push {r7} 80062c0: b083 sub sp, #12 80062c2: af00 add r7, sp, #0 80062c4: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); 80062c6: 687b ldr r3, [r7, #4] 80062c8: 689b ldr r3, [r3, #8] 80062ca: f003 0308 and.w r3, r3, #8 80062ce: 2b08 cmp r3, #8 80062d0: d101 bne.n 80062d6 80062d2: 2301 movs r3, #1 80062d4: e000 b.n 80062d8 80062d6: 2300 movs r3, #0 } 80062d8: 4618 mov r0, r3 80062da: 370c adds r7, #12 80062dc: 46bd mov sp, r7 80062de: f85d 7b04 ldr.w r7, [sp], #4 80062e2: 4770 bx lr 080062e4 : * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { 80062e4: b590 push {r4, r7, lr} 80062e6: b089 sub sp, #36 @ 0x24 80062e8: af00 add r7, sp, #0 80062ea: 6078 str r0, [r7, #4] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80062ec: 2300 movs r3, #0 80062ee: 77fb strb r3, [r7, #31] uint32_t tmpCFGR; uint32_t tmp_adc_reg_is_conversion_on_going; __IO uint32_t wait_loop_index = 0UL; 80062f0: 2300 movs r3, #0 80062f2: 60bb str r3, [r7, #8] uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; /* Check ADC handle */ if (hadc == NULL) 80062f4: 687b ldr r3, [r7, #4] 80062f6: 2b00 cmp r3, #0 80062f8: d101 bne.n 80062fe { return HAL_ERROR; 80062fa: 2301 movs r3, #1 80062fc: e18f b.n 800661e assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 80062fe: 687b ldr r3, [r7, #4] 8006300: 68db ldr r3, [r3, #12] 8006302: 2b00 cmp r3, #0 /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ if (hadc->State == HAL_ADC_STATE_RESET) 8006304: 687b ldr r3, [r7, #4] 8006306: 6d5b ldr r3, [r3, #84] @ 0x54 8006308: 2b00 cmp r3, #0 800630a: d109 bne.n 8006320 /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); 800630c: 6878 ldr r0, [r7, #4] 800630e: f7fd fcdf bl 8003cd0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); 8006312: 687b ldr r3, [r7, #4] 8006314: 2200 movs r2, #0 8006316: 659a str r2, [r3, #88] @ 0x58 /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; 8006318: 687b ldr r3, [r7, #4] 800631a: 2200 movs r2, #0 800631c: f883 2050 strb.w r2, [r3, #80] @ 0x50 } /* - Exit from deep-power-down mode and ADC voltage regulator enable */ if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) 8006320: 687b ldr r3, [r7, #4] 8006322: 681b ldr r3, [r3, #0] 8006324: 4618 mov r0, r3 8006326: f7ff ff19 bl 800615c 800632a: 4603 mov r3, r0 800632c: 2b00 cmp r3, #0 800632e: d004 beq.n 800633a { /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); 8006330: 687b ldr r3, [r7, #4] 8006332: 681b ldr r3, [r3, #0] 8006334: 4618 mov r0, r3 8006336: f7ff feff bl 8006138 /* System was in deep power down mode, calibration must be relaunched or a previously saved calibration factor re-applied once the ADC voltage regulator is enabled */ } if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 800633a: 687b ldr r3, [r7, #4] 800633c: 681b ldr r3, [r3, #0] 800633e: 4618 mov r0, r3 8006340: f7ff ff34 bl 80061ac 8006344: 4603 mov r3, r0 8006346: 2b00 cmp r3, #0 8006348: d114 bne.n 8006374 { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); 800634a: 687b ldr r3, [r7, #4] 800634c: 681b ldr r3, [r3, #0] 800634e: 4618 mov r0, r3 8006350: f7ff ff18 bl 8006184 /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006354: 4b87 ldr r3, [pc, #540] @ (8006574 ) 8006356: 681b ldr r3, [r3, #0] 8006358: 099b lsrs r3, r3, #6 800635a: 4a87 ldr r2, [pc, #540] @ (8006578 ) 800635c: fba2 2303 umull r2, r3, r2, r3 8006360: 099b lsrs r3, r3, #6 8006362: 3301 adds r3, #1 8006364: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006366: e002 b.n 800636e { wait_loop_index--; 8006368: 68bb ldr r3, [r7, #8] 800636a: 3b01 subs r3, #1 800636c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 800636e: 68bb ldr r3, [r7, #8] 8006370: 2b00 cmp r3, #0 8006372: d1f9 bne.n 8006368 } /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) 8006374: 687b ldr r3, [r7, #4] 8006376: 681b ldr r3, [r3, #0] 8006378: 4618 mov r0, r3 800637a: f7ff ff17 bl 80061ac 800637e: 4603 mov r3, r0 8006380: 2b00 cmp r3, #0 8006382: d10d bne.n 80063a0 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006384: 687b ldr r3, [r7, #4] 8006386: 6d5b ldr r3, [r3, #84] @ 0x54 8006388: f043 0210 orr.w r2, r3, #16 800638c: 687b ldr r3, [r7, #4] 800638e: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006390: 687b ldr r3, [r7, #4] 8006392: 6d9b ldr r3, [r3, #88] @ 0x58 8006394: f043 0201 orr.w r2, r3, #1 8006398: 687b ldr r3, [r7, #4] 800639a: 659a str r2, [r3, #88] @ 0x58 tmp_hal_status = HAL_ERROR; 800639c: 2301 movs r3, #1 800639e: 77fb strb r3, [r7, #31] /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80063a0: 687b ldr r3, [r7, #4] 80063a2: 681b ldr r3, [r3, #0] 80063a4: 4618 mov r0, r3 80063a6: f7ff ff77 bl 8006298 80063aa: 6178 str r0, [r7, #20] if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) 80063ac: 687b ldr r3, [r7, #4] 80063ae: 6d5b ldr r3, [r3, #84] @ 0x54 80063b0: f003 0310 and.w r3, r3, #16 80063b4: 2b00 cmp r3, #0 80063b6: f040 8129 bne.w 800660c && (tmp_adc_reg_is_conversion_on_going == 0UL) 80063ba: 697b ldr r3, [r7, #20] 80063bc: 2b00 cmp r3, #0 80063be: f040 8125 bne.w 800660c ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80063c2: 687b ldr r3, [r7, #4] 80063c4: 6d5b ldr r3, [r3, #84] @ 0x54 80063c6: f423 7381 bic.w r3, r3, #258 @ 0x102 80063ca: f043 0202 orr.w r2, r3, #2 80063ce: 687b ldr r3, [r7, #4] 80063d0: 655a str r2, [r3, #84] @ 0x54 /* Configuration of common ADC parameters */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 80063d2: 687b ldr r3, [r7, #4] 80063d4: 681b ldr r3, [r3, #0] 80063d6: 4618 mov r0, r3 80063d8: f7ff ff24 bl 8006224 80063dc: 4603 mov r3, r0 80063de: 2b00 cmp r3, #0 80063e0: d136 bne.n 8006450 { if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80063e2: 687b ldr r3, [r7, #4] 80063e4: 681b ldr r3, [r3, #0] 80063e6: 4a65 ldr r2, [pc, #404] @ (800657c ) 80063e8: 4293 cmp r3, r2 80063ea: d004 beq.n 80063f6 80063ec: 687b ldr r3, [r7, #4] 80063ee: 681b ldr r3, [r3, #0] 80063f0: 4a63 ldr r2, [pc, #396] @ (8006580 ) 80063f2: 4293 cmp r3, r2 80063f4: d10e bne.n 8006414 80063f6: 4861 ldr r0, [pc, #388] @ (800657c ) 80063f8: f7ff ff14 bl 8006224 80063fc: 4604 mov r4, r0 80063fe: 4860 ldr r0, [pc, #384] @ (8006580 ) 8006400: f7ff ff10 bl 8006224 8006404: 4603 mov r3, r0 8006406: 4323 orrs r3, r4 8006408: 2b00 cmp r3, #0 800640a: bf0c ite eq 800640c: 2301 moveq r3, #1 800640e: 2300 movne r3, #0 8006410: b2db uxtb r3, r3 8006412: e008 b.n 8006426 8006414: 485b ldr r0, [pc, #364] @ (8006584 ) 8006416: f7ff ff05 bl 8006224 800641a: 4603 mov r3, r0 800641c: 2b00 cmp r3, #0 800641e: bf0c ite eq 8006420: 2301 moveq r3, #1 8006422: 2300 movne r3, #0 8006424: b2db uxtb r3, r3 8006426: 2b00 cmp r3, #0 8006428: d012 beq.n 8006450 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ /* HAL_ADCEx_MultiModeConfigChannel() ) */ /* - internal measurement paths: Vbat, temperature sensor, Vref */ /* (set into HAL_ADC_ConfigChannel() or */ /* HAL_ADCEx_InjectedConfigChannel() ) */ LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 800642a: 687b ldr r3, [r7, #4] 800642c: 681b ldr r3, [r3, #0] 800642e: 4a53 ldr r2, [pc, #332] @ (800657c ) 8006430: 4293 cmp r3, r2 8006432: d004 beq.n 800643e 8006434: 687b ldr r3, [r7, #4] 8006436: 681b ldr r3, [r3, #0] 8006438: 4a51 ldr r2, [pc, #324] @ (8006580 ) 800643a: 4293 cmp r3, r2 800643c: d101 bne.n 8006442 800643e: 4a52 ldr r2, [pc, #328] @ (8006588 ) 8006440: e000 b.n 8006444 8006442: 4a52 ldr r2, [pc, #328] @ (800658c ) 8006444: 687b ldr r3, [r7, #4] 8006446: 685b ldr r3, [r3, #4] 8006448: 4619 mov r1, r3 800644a: 4610 mov r0, r2 800644c: f7ff fd3c bl 8005ec8 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); } #else if ((HAL_GetREVID() > REV_ID_Y) && (ADC_RESOLUTION_8B == hadc->Init.Resolution)) 8006450: f7ff fcf4 bl 8005e3c 8006454: 4603 mov r3, r0 8006456: f241 0203 movw r2, #4099 @ 0x1003 800645a: 4293 cmp r3, r2 800645c: d914 bls.n 8006488 800645e: 687b ldr r3, [r7, #4] 8006460: 689b ldr r3, [r3, #8] 8006462: 2b10 cmp r3, #16 8006464: d110 bne.n 8006488 { /* for STM32H7 silicon rev.B and above , ADC_CFGR_RES value for 8bits resolution is : b111 */ tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006466: 687b ldr r3, [r7, #4] 8006468: 7d5b ldrb r3, [r3, #21] 800646a: 035a lsls r2, r3, #13 hadc->Init.Overrun | 800646c: 687b ldr r3, [r7, #4] 800646e: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006470: 431a orrs r2, r3 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 8006472: 687b ldr r3, [r7, #4] 8006474: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8006476: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 8006478: 687b ldr r3, [r7, #4] 800647a: 7f1b ldrb r3, [r3, #28] 800647c: 041b lsls r3, r3, #16 hadc->Init.Resolution | (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) | 800647e: 4313 orrs r3, r2 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006480: f043 030c orr.w r3, r3, #12 8006484: 61bb str r3, [r7, #24] 8006486: e00d b.n 80064a4 } else { tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006488: 687b ldr r3, [r7, #4] 800648a: 7d5b ldrb r3, [r3, #21] 800648c: 035a lsls r2, r3, #13 hadc->Init.Overrun | 800648e: 687b ldr r3, [r7, #4] 8006490: 6b1b ldr r3, [r3, #48] @ 0x30 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 8006492: 431a orrs r2, r3 hadc->Init.Resolution | 8006494: 687b ldr r3, [r7, #4] 8006496: 689b ldr r3, [r3, #8] hadc->Init.Overrun | 8006498: 431a orrs r2, r3 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode)); 800649a: 687b ldr r3, [r7, #4] 800649c: 7f1b ldrb r3, [r3, #28] 800649e: 041b lsls r3, r3, #16 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | 80064a0: 4313 orrs r3, r2 80064a2: 61bb str r3, [r7, #24] } #endif /* ADC_VER_V5_3 */ if (hadc->Init.DiscontinuousConvMode == ENABLE) 80064a4: 687b ldr r3, [r7, #4] 80064a6: 7f1b ldrb r3, [r3, #28] 80064a8: 2b01 cmp r3, #1 80064aa: d106 bne.n 80064ba { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 80064ac: 687b ldr r3, [r7, #4] 80064ae: 6a1b ldr r3, [r3, #32] 80064b0: 3b01 subs r3, #1 80064b2: 045b lsls r3, r3, #17 80064b4: 69ba ldr r2, [r7, #24] 80064b6: 4313 orrs r3, r2 80064b8: 61bb str r3, [r7, #24] /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 80064ba: 687b ldr r3, [r7, #4] 80064bc: 6a5b ldr r3, [r3, #36] @ 0x24 80064be: 2b00 cmp r3, #0 80064c0: d009 beq.n 80064d6 { tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 80064c2: 687b ldr r3, [r7, #4] 80064c4: 6a5b ldr r3, [r3, #36] @ 0x24 80064c6: f403 7278 and.w r2, r3, #992 @ 0x3e0 | hadc->Init.ExternalTrigConvEdge 80064ca: 687b ldr r3, [r7, #4] 80064cc: 6a9b ldr r3, [r3, #40] @ 0x28 80064ce: 4313 orrs r3, r2 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 80064d0: 69ba ldr r2, [r7, #24] 80064d2: 4313 orrs r3, r2 80064d4: 61bb str r3, [r7, #24] /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); } #else /* Update Configuration Register CFGR */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 80064d6: 687b ldr r3, [r7, #4] 80064d8: 681b ldr r3, [r3, #0] 80064da: 68da ldr r2, [r3, #12] 80064dc: 4b2c ldr r3, [pc, #176] @ (8006590 ) 80064de: 4013 ands r3, r2 80064e0: 687a ldr r2, [r7, #4] 80064e2: 6812 ldr r2, [r2, #0] 80064e4: 69b9 ldr r1, [r7, #24] 80064e6: 430b orrs r3, r1 80064e8: 60d3 str r3, [r2, #12] /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ /* - Conversion data management Init.ConversionDataManagement */ /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 80064ea: 687b ldr r3, [r7, #4] 80064ec: 681b ldr r3, [r3, #0] 80064ee: 4618 mov r0, r3 80064f0: f7ff fed2 bl 8006298 80064f4: 6138 str r0, [r7, #16] tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 80064f6: 687b ldr r3, [r7, #4] 80064f8: 681b ldr r3, [r3, #0] 80064fa: 4618 mov r0, r3 80064fc: f7ff fedf bl 80062be 8006500: 60f8 str r0, [r7, #12] if ((tmp_adc_is_conversion_on_going_regular == 0UL) 8006502: 693b ldr r3, [r7, #16] 8006504: 2b00 cmp r3, #0 8006506: d15f bne.n 80065c8 && (tmp_adc_is_conversion_on_going_injected == 0UL) 8006508: 68fb ldr r3, [r7, #12] 800650a: 2b00 cmp r3, #0 800650c: d15c bne.n 80065c8 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else tmpCFGR = ( ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | 800650e: 687b ldr r3, [r7, #4] 8006510: 7d1b ldrb r3, [r3, #20] 8006512: 039a lsls r2, r3, #14 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); 8006514: 687b ldr r3, [r7, #4] 8006516: 6adb ldr r3, [r3, #44] @ 0x2c tmpCFGR = ( 8006518: 4313 orrs r3, r2 800651a: 61bb str r3, [r7, #24] #endif MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 800651c: 687b ldr r3, [r7, #4] 800651e: 681b ldr r3, [r3, #0] 8006520: 68da ldr r2, [r3, #12] 8006522: 4b1c ldr r3, [pc, #112] @ (8006594 ) 8006524: 4013 ands r3, r2 8006526: 687a ldr r2, [r7, #4] 8006528: 6812 ldr r2, [r2, #0] 800652a: 69b9 ldr r1, [r7, #24] 800652c: 430b orrs r3, r1 800652e: 60d3 str r3, [r2, #12] if (hadc->Init.OversamplingMode == ENABLE) 8006530: 687b ldr r3, [r7, #4] 8006532: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8006536: 2b01 cmp r3, #1 8006538: d130 bne.n 800659c #endif assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) 800653a: 687b ldr r3, [r7, #4] 800653c: 6a5b ldr r3, [r3, #36] @ 0x24 800653e: 2b00 cmp r3, #0 /* - Oversampling Ratio */ /* - Right bit shift */ /* - Left bit shift */ /* - Triggered mode */ /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 8006540: 687b ldr r3, [r7, #4] 8006542: 681b ldr r3, [r3, #0] 8006544: 691a ldr r2, [r3, #16] 8006546: 4b14 ldr r3, [pc, #80] @ (8006598 ) 8006548: 4013 ands r3, r2 800654a: 687a ldr r2, [r7, #4] 800654c: 6bd2 ldr r2, [r2, #60] @ 0x3c 800654e: 3a01 subs r2, #1 8006550: 0411 lsls r1, r2, #16 8006552: 687a ldr r2, [r7, #4] 8006554: 6c12 ldr r2, [r2, #64] @ 0x40 8006556: 4311 orrs r1, r2 8006558: 687a ldr r2, [r7, #4] 800655a: 6c52 ldr r2, [r2, #68] @ 0x44 800655c: 4311 orrs r1, r2 800655e: 687a ldr r2, [r7, #4] 8006560: 6c92 ldr r2, [r2, #72] @ 0x48 8006562: 430a orrs r2, r1 8006564: 431a orrs r2, r3 8006566: 687b ldr r3, [r7, #4] 8006568: 681b ldr r3, [r3, #0] 800656a: f042 0201 orr.w r2, r2, #1 800656e: 611a str r2, [r3, #16] 8006570: e01c b.n 80065ac 8006572: bf00 nop 8006574: 24000034 .word 0x24000034 8006578: 053e2d63 .word 0x053e2d63 800657c: 40022000 .word 0x40022000 8006580: 40022100 .word 0x40022100 8006584: 58026000 .word 0x58026000 8006588: 40022300 .word 0x40022300 800658c: 58026300 .word 0x58026300 8006590: fff0c003 .word 0xfff0c003 8006594: ffffbffc .word 0xffffbffc 8006598: fc00f81e .word 0xfc00f81e } else { /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 800659c: 687b ldr r3, [r7, #4] 800659e: 681b ldr r3, [r3, #0] 80065a0: 691a ldr r2, [r3, #16] 80065a2: 687b ldr r3, [r7, #4] 80065a4: 681b ldr r3, [r3, #0] 80065a6: f022 0201 bic.w r2, r2, #1 80065aa: 611a str r2, [r3, #16] } /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); 80065ac: 687b ldr r3, [r7, #4] 80065ae: 681b ldr r3, [r3, #0] 80065b0: 691b ldr r3, [r3, #16] 80065b2: f023 4170 bic.w r1, r3, #4026531840 @ 0xf0000000 80065b6: 687b ldr r3, [r7, #4] 80065b8: 6b5a ldr r2, [r3, #52] @ 0x34 80065ba: 687b ldr r3, [r7, #4] 80065bc: 681b ldr r3, [r3, #0] 80065be: 430a orrs r2, r1 80065c0: 611a str r2, [r3, #16] /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } #else /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); 80065c2: 6878 ldr r0, [r7, #4] 80065c4: f000 fde2 bl 800718c /* Note: Scan mode is not present by hardware on this device, but */ /* emulated by software for alignment over all STM32 devices. */ /* - if scan mode is enabled, regular channels sequence length is set to */ /* parameter "NbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 80065c8: 687b ldr r3, [r7, #4] 80065ca: 68db ldr r3, [r3, #12] 80065cc: 2b01 cmp r3, #1 80065ce: d10c bne.n 80065ea { /* Set number of ranks in regular group sequencer */ MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 80065d0: 687b ldr r3, [r7, #4] 80065d2: 681b ldr r3, [r3, #0] 80065d4: 6b1b ldr r3, [r3, #48] @ 0x30 80065d6: f023 010f bic.w r1, r3, #15 80065da: 687b ldr r3, [r7, #4] 80065dc: 699b ldr r3, [r3, #24] 80065de: 1e5a subs r2, r3, #1 80065e0: 687b ldr r3, [r7, #4] 80065e2: 681b ldr r3, [r3, #0] 80065e4: 430a orrs r2, r1 80065e6: 631a str r2, [r3, #48] @ 0x30 80065e8: e007 b.n 80065fa } else { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 80065ea: 687b ldr r3, [r7, #4] 80065ec: 681b ldr r3, [r3, #0] 80065ee: 6b1a ldr r2, [r3, #48] @ 0x30 80065f0: 687b ldr r3, [r7, #4] 80065f2: 681b ldr r3, [r3, #0] 80065f4: f022 020f bic.w r2, r2, #15 80065f8: 631a str r2, [r3, #48] @ 0x30 } /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 80065fa: 687b ldr r3, [r7, #4] 80065fc: 6d5b ldr r3, [r3, #84] @ 0x54 80065fe: f023 0303 bic.w r3, r3, #3 8006602: f043 0201 orr.w r2, r3, #1 8006606: 687b ldr r3, [r7, #4] 8006608: 655a str r2, [r3, #84] @ 0x54 800660a: e007 b.n 800661c } else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800660c: 687b ldr r3, [r7, #4] 800660e: 6d5b ldr r3, [r3, #84] @ 0x54 8006610: f043 0210 orr.w r2, r3, #16 8006614: 687b ldr r3, [r7, #4] 8006616: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006618: 2301 movs r3, #1 800661a: 77fb strb r3, [r7, #31] } /* Return function status */ return tmp_hal_status; 800661c: 7ffb ldrb r3, [r7, #31] } 800661e: 4618 mov r0, r3 8006620: 3724 adds r7, #36 @ 0x24 8006622: 46bd mov sp, r7 8006624: bd90 pop {r4, r7, pc} 8006626: bf00 nop 08006628 : * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { 8006628: b580 push {r7, lr} 800662a: b086 sub sp, #24 800662c: af00 add r7, sp, #0 800662e: 60f8 str r0, [r7, #12] 8006630: 60b9 str r1, [r7, #8] 8006632: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006634: 68fb ldr r3, [r7, #12] 8006636: 681b ldr r3, [r3, #0] 8006638: 4a55 ldr r2, [pc, #340] @ (8006790 ) 800663a: 4293 cmp r3, r2 800663c: d004 beq.n 8006648 800663e: 68fb ldr r3, [r7, #12] 8006640: 681b ldr r3, [r3, #0] 8006642: 4a54 ldr r2, [pc, #336] @ (8006794 ) 8006644: 4293 cmp r3, r2 8006646: d101 bne.n 800664c 8006648: 4b53 ldr r3, [pc, #332] @ (8006798 ) 800664a: e000 b.n 800664e 800664c: 4b53 ldr r3, [pc, #332] @ (800679c ) 800664e: 4618 mov r0, r3 8006650: f7ff fd64 bl 800611c 8006654: 6138 str r0, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 8006656: 68fb ldr r3, [r7, #12] 8006658: 681b ldr r3, [r3, #0] 800665a: 4618 mov r0, r3 800665c: f7ff fe1c bl 8006298 8006660: 4603 mov r3, r0 8006662: 2b00 cmp r3, #0 8006664: f040 808c bne.w 8006780 { /* Process locked */ __HAL_LOCK(hadc); 8006668: 68fb ldr r3, [r7, #12] 800666a: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 800666e: 2b01 cmp r3, #1 8006670: d101 bne.n 8006676 8006672: 2302 movs r3, #2 8006674: e087 b.n 8006786 8006676: 68fb ldr r3, [r7, #12] 8006678: 2201 movs r2, #1 800667a: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 800667e: 693b ldr r3, [r7, #16] 8006680: 2b00 cmp r3, #0 8006682: d005 beq.n 8006690 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) 8006684: 693b ldr r3, [r7, #16] 8006686: 2b05 cmp r3, #5 8006688: d002 beq.n 8006690 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) 800668a: 693b ldr r3, [r7, #16] 800668c: 2b09 cmp r3, #9 800668e: d170 bne.n 8006772 ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); 8006690: 68f8 ldr r0, [r7, #12] 8006692: f000 fbfd bl 8006e90 8006696: 4603 mov r3, r0 8006698: 75fb strb r3, [r7, #23] /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) 800669a: 7dfb ldrb r3, [r7, #23] 800669c: 2b00 cmp r3, #0 800669e: d163 bne.n 8006768 { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular operation */ ADC_STATE_CLR_SET(hadc->State, 80066a0: 68fb ldr r3, [r7, #12] 80066a2: 6d5a ldr r2, [r3, #84] @ 0x54 80066a4: 4b3e ldr r3, [pc, #248] @ (80067a0 ) 80066a6: 4013 ands r3, r2 80066a8: f443 7280 orr.w r2, r3, #256 @ 0x100 80066ac: 68fb ldr r3, [r7, #12] 80066ae: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY); /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 80066b0: 68fb ldr r3, [r7, #12] 80066b2: 681b ldr r3, [r3, #0] 80066b4: 4a37 ldr r2, [pc, #220] @ (8006794 ) 80066b6: 4293 cmp r3, r2 80066b8: d002 beq.n 80066c0 80066ba: 68fb ldr r3, [r7, #12] 80066bc: 681b ldr r3, [r3, #0] 80066be: e000 b.n 80066c2 80066c0: 4b33 ldr r3, [pc, #204] @ (8006790 ) 80066c2: 68fa ldr r2, [r7, #12] 80066c4: 6812 ldr r2, [r2, #0] 80066c6: 4293 cmp r3, r2 80066c8: d002 beq.n 80066d0 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 80066ca: 693b ldr r3, [r7, #16] 80066cc: 2b00 cmp r3, #0 80066ce: d105 bne.n 80066dc ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 80066d0: 68fb ldr r3, [r7, #12] 80066d2: 6d5b ldr r3, [r3, #84] @ 0x54 80066d4: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 80066d8: 68fb ldr r3, [r7, #12] 80066da: 655a str r2, [r3, #84] @ 0x54 } /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) 80066dc: 68fb ldr r3, [r7, #12] 80066de: 6d5b ldr r3, [r3, #84] @ 0x54 80066e0: f403 5380 and.w r3, r3, #4096 @ 0x1000 80066e4: 2b00 cmp r3, #0 80066e6: d006 beq.n 80066f6 { /* Reset ADC error code fields related to regular conversions only */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 80066e8: 68fb ldr r3, [r7, #12] 80066ea: 6d9b ldr r3, [r3, #88] @ 0x58 80066ec: f023 0206 bic.w r2, r3, #6 80066f0: 68fb ldr r3, [r7, #12] 80066f2: 659a str r2, [r3, #88] @ 0x58 80066f4: e002 b.n 80066fc } else { /* Reset all ADC error code fields */ ADC_CLEAR_ERRORCODE(hadc); 80066f6: 68fb ldr r3, [r7, #12] 80066f8: 2200 movs r2, #0 80066fa: 659a str r2, [r3, #88] @ 0x58 } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 80066fc: 68fb ldr r3, [r7, #12] 80066fe: 6cdb ldr r3, [r3, #76] @ 0x4c 8006700: 4a28 ldr r2, [pc, #160] @ (80067a4 ) 8006702: 63da str r2, [r3, #60] @ 0x3c /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 8006704: 68fb ldr r3, [r7, #12] 8006706: 6cdb ldr r3, [r3, #76] @ 0x4c 8006708: 4a27 ldr r2, [pc, #156] @ (80067a8 ) 800670a: 641a str r2, [r3, #64] @ 0x40 /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 800670c: 68fb ldr r3, [r7, #12] 800670e: 6cdb ldr r3, [r3, #76] @ 0x4c 8006710: 4a26 ldr r2, [pc, #152] @ (80067ac ) 8006712: 64da str r2, [r3, #76] @ 0x4c /* ADC start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 8006714: 68fb ldr r3, [r7, #12] 8006716: 681b ldr r3, [r3, #0] 8006718: 221c movs r2, #28 800671a: 601a str r2, [r3, #0] /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); 800671c: 68fb ldr r3, [r7, #12] 800671e: 2200 movs r2, #0 8006720: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* With DMA, overrun event is always considered as an error even if hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 8006724: 68fb ldr r3, [r7, #12] 8006726: 681b ldr r3, [r3, #0] 8006728: 685a ldr r2, [r3, #4] 800672a: 68fb ldr r3, [r7, #12] 800672c: 681b ldr r3, [r3, #0] 800672e: f042 0210 orr.w r2, r2, #16 8006732: 605a str r2, [r3, #4] { LL_ADC_REG_SetDataTransferMode(hadc->Instance, ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); } #else LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement); 8006734: 68fb ldr r3, [r7, #12] 8006736: 681a ldr r2, [r3, #0] 8006738: 68fb ldr r3, [r7, #12] 800673a: 6adb ldr r3, [r3, #44] @ 0x2c 800673c: 4619 mov r1, r3 800673e: 4610 mov r0, r2 8006740: f7ff fc89 bl 8006056 #endif /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 8006744: 68fb ldr r3, [r7, #12] 8006746: 6cd8 ldr r0, [r3, #76] @ 0x4c 8006748: 68fb ldr r3, [r7, #12] 800674a: 681b ldr r3, [r3, #0] 800674c: 3340 adds r3, #64 @ 0x40 800674e: 4619 mov r1, r3 8006750: 68ba ldr r2, [r7, #8] 8006752: 687b ldr r3, [r7, #4] 8006754: f002 fa5e bl 8008c14 8006758: 4603 mov r3, r0 800675a: 75fb strb r3, [r7, #23] /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); 800675c: 68fb ldr r3, [r7, #12] 800675e: 681b ldr r3, [r3, #0] 8006760: 4618 mov r0, r3 8006762: f7ff fd85 bl 8006270 if (tmp_hal_status == HAL_OK) 8006766: e00d b.n 8006784 } else { /* Process unlocked */ __HAL_UNLOCK(hadc); 8006768: 68fb ldr r3, [r7, #12] 800676a: 2200 movs r2, #0 800676c: f883 2050 strb.w r2, [r3, #80] @ 0x50 if (tmp_hal_status == HAL_OK) 8006770: e008 b.n 8006784 } } else { tmp_hal_status = HAL_ERROR; 8006772: 2301 movs r3, #1 8006774: 75fb strb r3, [r7, #23] /* Process unlocked */ __HAL_UNLOCK(hadc); 8006776: 68fb ldr r3, [r7, #12] 8006778: 2200 movs r2, #0 800677a: f883 2050 strb.w r2, [r3, #80] @ 0x50 800677e: e001 b.n 8006784 } } else { tmp_hal_status = HAL_BUSY; 8006780: 2302 movs r3, #2 8006782: 75fb strb r3, [r7, #23] } /* Return function status */ return tmp_hal_status; 8006784: 7dfb ldrb r3, [r7, #23] } 8006786: 4618 mov r0, r3 8006788: 3718 adds r7, #24 800678a: 46bd mov sp, r7 800678c: bd80 pop {r7, pc} 800678e: bf00 nop 8006790: 40022000 .word 0x40022000 8006794: 40022100 .word 0x40022100 8006798: 40022300 .word 0x40022300 800679c: 58026300 .word 0x58026300 80067a0: fffff0fe .word 0xfffff0fe 80067a4: 08007063 .word 0x08007063 80067a8: 0800713b .word 0x0800713b 80067ac: 08007157 .word 0x08007157 080067b0 : * @brief Conversion DMA half-transfer callback in non-blocking mode. * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { 80067b0: b480 push {r7} 80067b2: b083 sub sp, #12 80067b4: af00 add r7, sp, #0 80067b6: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. */ } 80067b8: bf00 nop 80067ba: 370c adds r7, #12 80067bc: 46bd mov sp, r7 80067be: f85d 7b04 ldr.w r7, [sp], #4 80067c2: 4770 bx lr 080067c4 : * (this function is also clearing overrun flag) * @param hadc ADC handle * @retval None */ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) { 80067c4: b480 push {r7} 80067c6: b083 sub sp, #12 80067c8: af00 add r7, sp, #0 80067ca: 6078 str r0, [r7, #4] UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_ErrorCallback must be implemented in the user file. */ } 80067cc: bf00 nop 80067ce: 370c adds r7, #12 80067d0: 46bd mov sp, r7 80067d2: f85d 7b04 ldr.w r7, [sp], #4 80067d6: 4770 bx lr 080067d8 : * @param hadc ADC handle * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { 80067d8: b590 push {r4, r7, lr} 80067da: b0a1 sub sp, #132 @ 0x84 80067dc: af00 add r7, sp, #0 80067de: 6078 str r0, [r7, #4] 80067e0: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 80067e2: 2300 movs r3, #0 80067e4: f887 307f strb.w r3, [r7, #127] @ 0x7f uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; __IO uint32_t wait_loop_index = 0; 80067e8: 2300 movs r3, #0 80067ea: 60bb str r3, [r7, #8] /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 80067ec: 683b ldr r3, [r7, #0] 80067ee: 68db ldr r3, [r3, #12] 80067f0: 4a65 ldr r2, [pc, #404] @ (8006988 ) 80067f2: 4293 cmp r3, r2 } #endif } /* Process locked */ __HAL_LOCK(hadc); 80067f4: 687b ldr r3, [r7, #4] 80067f6: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 80067fa: 2b01 cmp r3, #1 80067fc: d101 bne.n 8006802 80067fe: 2302 movs r3, #2 8006800: e32e b.n 8006e60 8006802: 687b ldr r3, [r7, #4] 8006804: 2201 movs r2, #1 8006806: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel number */ /* - Channel rank */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800680a: 687b ldr r3, [r7, #4] 800680c: 681b ldr r3, [r3, #0] 800680e: 4618 mov r0, r3 8006810: f7ff fd42 bl 8006298 8006814: 4603 mov r3, r0 8006816: 2b00 cmp r3, #0 8006818: f040 8313 bne.w 8006e42 { if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))) 800681c: 683b ldr r3, [r7, #0] 800681e: 681b ldr r3, [r3, #0] 8006820: 2b00 cmp r3, #0 8006822: db2c blt.n 800687e /* ADC channels preselection */ hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); } #else /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); 8006824: 683b ldr r3, [r7, #0] 8006826: 681b ldr r3, [r3, #0] 8006828: f3c3 0313 ubfx r3, r3, #0, #20 800682c: 2b00 cmp r3, #0 800682e: d108 bne.n 8006842 8006830: 683b ldr r3, [r7, #0] 8006832: 681b ldr r3, [r3, #0] 8006834: 0e9b lsrs r3, r3, #26 8006836: f003 031f and.w r3, r3, #31 800683a: 2201 movs r2, #1 800683c: fa02 f303 lsl.w r3, r2, r3 8006840: e016 b.n 8006870 8006842: 683b ldr r3, [r7, #0] 8006844: 681b ldr r3, [r3, #0] 8006846: 667b str r3, [r7, #100] @ 0x64 uint32_t result; #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006848: 6e7b ldr r3, [r7, #100] @ 0x64 800684a: fa93 f3a3 rbit r3, r3 800684e: 663b str r3, [r7, #96] @ 0x60 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return result; 8006850: 6e3b ldr r3, [r7, #96] @ 0x60 8006852: 66bb str r3, [r7, #104] @ 0x68 optimisations using the logic "value was passed to __builtin_clz, so it is non-zero". ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a single CLZ instruction. */ if (value == 0U) 8006854: 6ebb ldr r3, [r7, #104] @ 0x68 8006856: 2b00 cmp r3, #0 8006858: d101 bne.n 800685e { return 32U; 800685a: 2320 movs r3, #32 800685c: e003 b.n 8006866 } return __builtin_clz(value); 800685e: 6ebb ldr r3, [r7, #104] @ 0x68 8006860: fab3 f383 clz r3, r3 8006864: b2db uxtb r3, r3 8006866: f003 031f and.w r3, r3, #31 800686a: 2201 movs r2, #1 800686c: fa02 f303 lsl.w r3, r2, r3 8006870: 687a ldr r2, [r7, #4] 8006872: 6812 ldr r2, [r2, #0] 8006874: 69d1 ldr r1, [r2, #28] 8006876: 687a ldr r2, [r7, #4] 8006878: 6812 ldr r2, [r2, #0] 800687a: 430b orrs r3, r1 800687c: 61d3 str r3, [r2, #28] #endif /* ADC_VER_V5_V90 */ } /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 800687e: 687b ldr r3, [r7, #4] 8006880: 6818 ldr r0, [r3, #0] 8006882: 683b ldr r3, [r7, #0] 8006884: 6859 ldr r1, [r3, #4] 8006886: 683b ldr r3, [r7, #0] 8006888: 681b ldr r3, [r3, #0] 800688a: 461a mov r2, r3 800688c: f7ff fbb7 bl 8005ffe /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Channel sampling time */ /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); 8006890: 687b ldr r3, [r7, #4] 8006892: 681b ldr r3, [r3, #0] 8006894: 4618 mov r0, r3 8006896: f7ff fcff bl 8006298 800689a: 67b8 str r0, [r7, #120] @ 0x78 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); 800689c: 687b ldr r3, [r7, #4] 800689e: 681b ldr r3, [r3, #0] 80068a0: 4618 mov r0, r3 80068a2: f7ff fd0c bl 80062be 80068a6: 6778 str r0, [r7, #116] @ 0x74 if ((tmp_adc_is_conversion_on_going_regular == 0UL) 80068a8: 6fbb ldr r3, [r7, #120] @ 0x78 80068aa: 2b00 cmp r3, #0 80068ac: f040 80b8 bne.w 8006a20 && (tmp_adc_is_conversion_on_going_injected == 0UL) 80068b0: 6f7b ldr r3, [r7, #116] @ 0x74 80068b2: 2b00 cmp r3, #0 80068b4: f040 80b4 bne.w 8006a20 ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 80068b8: 687b ldr r3, [r7, #4] 80068ba: 6818 ldr r0, [r3, #0] 80068bc: 683b ldr r3, [r7, #0] 80068be: 6819 ldr r1, [r3, #0] 80068c0: 683b ldr r3, [r7, #0] 80068c2: 689b ldr r3, [r3, #8] 80068c4: 461a mov r2, r3 80068c6: f7ff fbd9 bl 800607c tmpOffsetShifted = ADC3_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); } else #endif /* ADC_VER_V5_V90 */ { tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); 80068ca: 4b30 ldr r3, [pc, #192] @ (800698c ) 80068cc: 681b ldr r3, [r3, #0] 80068ce: f003 4370 and.w r3, r3, #4026531840 @ 0xf0000000 80068d2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 80068d6: d10b bne.n 80068f0 80068d8: 683b ldr r3, [r7, #0] 80068da: 695a ldr r2, [r3, #20] 80068dc: 687b ldr r3, [r7, #4] 80068de: 681b ldr r3, [r3, #0] 80068e0: 68db ldr r3, [r3, #12] 80068e2: 089b lsrs r3, r3, #2 80068e4: f003 0307 and.w r3, r3, #7 80068e8: 005b lsls r3, r3, #1 80068ea: fa02 f303 lsl.w r3, r2, r3 80068ee: e01d b.n 800692c 80068f0: 687b ldr r3, [r7, #4] 80068f2: 681b ldr r3, [r3, #0] 80068f4: 68db ldr r3, [r3, #12] 80068f6: f003 0310 and.w r3, r3, #16 80068fa: 2b00 cmp r3, #0 80068fc: d10b bne.n 8006916 80068fe: 683b ldr r3, [r7, #0] 8006900: 695a ldr r2, [r3, #20] 8006902: 687b ldr r3, [r7, #4] 8006904: 681b ldr r3, [r3, #0] 8006906: 68db ldr r3, [r3, #12] 8006908: 089b lsrs r3, r3, #2 800690a: f003 0307 and.w r3, r3, #7 800690e: 005b lsls r3, r3, #1 8006910: fa02 f303 lsl.w r3, r2, r3 8006914: e00a b.n 800692c 8006916: 683b ldr r3, [r7, #0] 8006918: 695a ldr r2, [r3, #20] 800691a: 687b ldr r3, [r7, #4] 800691c: 681b ldr r3, [r3, #0] 800691e: 68db ldr r3, [r3, #12] 8006920: 089b lsrs r3, r3, #2 8006922: f003 0304 and.w r3, r3, #4 8006926: 005b lsls r3, r3, #1 8006928: fa02 f303 lsl.w r3, r2, r3 800692c: 673b str r3, [r7, #112] @ 0x70 } if (sConfig->OffsetNumber != ADC_OFFSET_NONE) 800692e: 683b ldr r3, [r7, #0] 8006930: 691b ldr r3, [r3, #16] 8006932: 2b04 cmp r3, #4 8006934: d02c beq.n 8006990 { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 8006936: 687b ldr r3, [r7, #4] 8006938: 6818 ldr r0, [r3, #0] 800693a: 683b ldr r3, [r7, #0] 800693c: 6919 ldr r1, [r3, #16] 800693e: 683b ldr r3, [r7, #0] 8006940: 681a ldr r2, [r3, #0] 8006942: 6f3b ldr r3, [r7, #112] @ 0x70 8006944: f7ff faf4 bl 8005f30 else #endif /* ADC_VER_V5_V90 */ { assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); 8006948: 687b ldr r3, [r7, #4] 800694a: 6818 ldr r0, [r3, #0] 800694c: 683b ldr r3, [r7, #0] 800694e: 6919 ldr r1, [r3, #16] 8006950: 683b ldr r3, [r7, #0] 8006952: 7e5b ldrb r3, [r3, #25] 8006954: 2b01 cmp r3, #1 8006956: d102 bne.n 800695e 8006958: f04f 4300 mov.w r3, #2147483648 @ 0x80000000 800695c: e000 b.n 8006960 800695e: 2300 movs r3, #0 8006960: 461a mov r2, r3 8006962: f7ff fb1e bl 8005fa2 assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); /* Set ADC selected offset right shift */ LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); 8006966: 687b ldr r3, [r7, #4] 8006968: 6818 ldr r0, [r3, #0] 800696a: 683b ldr r3, [r7, #0] 800696c: 6919 ldr r1, [r3, #16] 800696e: 683b ldr r3, [r7, #0] 8006970: 7e1b ldrb r3, [r3, #24] 8006972: 2b01 cmp r3, #1 8006974: d102 bne.n 800697c 8006976: f44f 6300 mov.w r3, #2048 @ 0x800 800697a: e000 b.n 800697e 800697c: 2300 movs r3, #0 800697e: 461a mov r2, r3 8006980: f7ff faf6 bl 8005f70 8006984: e04c b.n 8006a20 8006986: bf00 nop 8006988: 47ff0000 .word 0x47ff0000 800698c: 5c001000 .word 0x5c001000 } } else #endif /* ADC_VER_V5_V90 */ { if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 8006990: 687b ldr r3, [r7, #4] 8006992: 681b ldr r3, [r3, #0] 8006994: 6e1b ldr r3, [r3, #96] @ 0x60 8006996: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 800699a: 683b ldr r3, [r7, #0] 800699c: 681b ldr r3, [r3, #0] 800699e: 069b lsls r3, r3, #26 80069a0: 429a cmp r2, r3 80069a2: d107 bne.n 80069b4 { CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE); 80069a4: 687b ldr r3, [r7, #4] 80069a6: 681b ldr r3, [r3, #0] 80069a8: 6e1a ldr r2, [r3, #96] @ 0x60 80069aa: 687b ldr r3, [r7, #4] 80069ac: 681b ldr r3, [r3, #0] 80069ae: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069b2: 661a str r2, [r3, #96] @ 0x60 } if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80069b4: 687b ldr r3, [r7, #4] 80069b6: 681b ldr r3, [r3, #0] 80069b8: 6e5b ldr r3, [r3, #100] @ 0x64 80069ba: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80069be: 683b ldr r3, [r7, #0] 80069c0: 681b ldr r3, [r3, #0] 80069c2: 069b lsls r3, r3, #26 80069c4: 429a cmp r2, r3 80069c6: d107 bne.n 80069d8 { CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE); 80069c8: 687b ldr r3, [r7, #4] 80069ca: 681b ldr r3, [r3, #0] 80069cc: 6e5a ldr r2, [r3, #100] @ 0x64 80069ce: 687b ldr r3, [r7, #4] 80069d0: 681b ldr r3, [r3, #0] 80069d2: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069d6: 665a str r2, [r3, #100] @ 0x64 } if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80069d8: 687b ldr r3, [r7, #4] 80069da: 681b ldr r3, [r3, #0] 80069dc: 6e9b ldr r3, [r3, #104] @ 0x68 80069de: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 80069e2: 683b ldr r3, [r7, #0] 80069e4: 681b ldr r3, [r3, #0] 80069e6: 069b lsls r3, r3, #26 80069e8: 429a cmp r2, r3 80069ea: d107 bne.n 80069fc { CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE); 80069ec: 687b ldr r3, [r7, #4] 80069ee: 681b ldr r3, [r3, #0] 80069f0: 6e9a ldr r2, [r3, #104] @ 0x68 80069f2: 687b ldr r3, [r7, #4] 80069f4: 681b ldr r3, [r3, #0] 80069f6: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 80069fa: 669a str r2, [r3, #104] @ 0x68 } if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel)) 80069fc: 687b ldr r3, [r7, #4] 80069fe: 681b ldr r3, [r3, #0] 8006a00: 6edb ldr r3, [r3, #108] @ 0x6c 8006a02: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006a06: 683b ldr r3, [r7, #0] 8006a08: 681b ldr r3, [r3, #0] 8006a0a: 069b lsls r3, r3, #26 8006a0c: 429a cmp r2, r3 8006a0e: d107 bne.n 8006a20 { CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE); 8006a10: 687b ldr r3, [r7, #4] 8006a12: 681b ldr r3, [r3, #0] 8006a14: 6eda ldr r2, [r3, #108] @ 0x6c 8006a16: 687b ldr r3, [r7, #4] 8006a18: 681b ldr r3, [r3, #0] 8006a1a: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000 8006a1e: 66da str r2, [r3, #108] @ 0x6c /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006a20: 687b ldr r3, [r7, #4] 8006a22: 681b ldr r3, [r3, #0] 8006a24: 4618 mov r0, r3 8006a26: f7ff fbfd bl 8006224 8006a2a: 4603 mov r3, r0 8006a2c: 2b00 cmp r3, #0 8006a2e: f040 8211 bne.w 8006e54 { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 8006a32: 687b ldr r3, [r7, #4] 8006a34: 6818 ldr r0, [r3, #0] 8006a36: 683b ldr r3, [r7, #0] 8006a38: 6819 ldr r1, [r3, #0] 8006a3a: 683b ldr r3, [r7, #0] 8006a3c: 68db ldr r3, [r3, #12] 8006a3e: 461a mov r2, r3 8006a40: f7ff fb48 bl 80060d4 /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 8006a44: 683b ldr r3, [r7, #0] 8006a46: 68db ldr r3, [r3, #12] 8006a48: 4aa1 ldr r2, [pc, #644] @ (8006cd0 ) 8006a4a: 4293 cmp r3, r2 8006a4c: f040 812e bne.w 8006cac { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006a50: 687b ldr r3, [r7, #4] 8006a52: 6818 ldr r0, [r3, #0] (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006a54: 683b ldr r3, [r7, #0] 8006a56: 681b ldr r3, [r3, #0] 8006a58: f3c3 0313 ubfx r3, r3, #0, #20 8006a5c: 2b00 cmp r3, #0 8006a5e: d10b bne.n 8006a78 8006a60: 683b ldr r3, [r7, #0] 8006a62: 681b ldr r3, [r3, #0] 8006a64: 0e9b lsrs r3, r3, #26 8006a66: 3301 adds r3, #1 8006a68: f003 031f and.w r3, r3, #31 8006a6c: 2b09 cmp r3, #9 8006a6e: bf94 ite ls 8006a70: 2301 movls r3, #1 8006a72: 2300 movhi r3, #0 8006a74: b2db uxtb r3, r3 8006a76: e019 b.n 8006aac 8006a78: 683b ldr r3, [r7, #0] 8006a7a: 681b ldr r3, [r3, #0] 8006a7c: 65bb str r3, [r7, #88] @ 0x58 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006a7e: 6dbb ldr r3, [r7, #88] @ 0x58 8006a80: fa93 f3a3 rbit r3, r3 8006a84: 657b str r3, [r7, #84] @ 0x54 return result; 8006a86: 6d7b ldr r3, [r7, #84] @ 0x54 8006a88: 65fb str r3, [r7, #92] @ 0x5c if (value == 0U) 8006a8a: 6dfb ldr r3, [r7, #92] @ 0x5c 8006a8c: 2b00 cmp r3, #0 8006a8e: d101 bne.n 8006a94 return 32U; 8006a90: 2320 movs r3, #32 8006a92: e003 b.n 8006a9c return __builtin_clz(value); 8006a94: 6dfb ldr r3, [r7, #92] @ 0x5c 8006a96: fab3 f383 clz r3, r3 8006a9a: b2db uxtb r3, r3 8006a9c: 3301 adds r3, #1 8006a9e: f003 031f and.w r3, r3, #31 8006aa2: 2b09 cmp r3, #9 8006aa4: bf94 ite ls 8006aa6: 2301 movls r3, #1 8006aa8: 2300 movhi r3, #0 8006aaa: b2db uxtb r3, r3 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006aac: 2b00 cmp r3, #0 8006aae: d079 beq.n 8006ba4 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006ab0: 683b ldr r3, [r7, #0] 8006ab2: 681b ldr r3, [r3, #0] 8006ab4: f3c3 0313 ubfx r3, r3, #0, #20 8006ab8: 2b00 cmp r3, #0 8006aba: d107 bne.n 8006acc 8006abc: 683b ldr r3, [r7, #0] 8006abe: 681b ldr r3, [r3, #0] 8006ac0: 0e9b lsrs r3, r3, #26 8006ac2: 3301 adds r3, #1 8006ac4: 069b lsls r3, r3, #26 8006ac6: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006aca: e015 b.n 8006af8 8006acc: 683b ldr r3, [r7, #0] 8006ace: 681b ldr r3, [r3, #0] 8006ad0: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006ad2: 6cfb ldr r3, [r7, #76] @ 0x4c 8006ad4: fa93 f3a3 rbit r3, r3 8006ad8: 64bb str r3, [r7, #72] @ 0x48 return result; 8006ada: 6cbb ldr r3, [r7, #72] @ 0x48 8006adc: 653b str r3, [r7, #80] @ 0x50 if (value == 0U) 8006ade: 6d3b ldr r3, [r7, #80] @ 0x50 8006ae0: 2b00 cmp r3, #0 8006ae2: d101 bne.n 8006ae8 return 32U; 8006ae4: 2320 movs r3, #32 8006ae6: e003 b.n 8006af0 return __builtin_clz(value); 8006ae8: 6d3b ldr r3, [r7, #80] @ 0x50 8006aea: fab3 f383 clz r3, r3 8006aee: b2db uxtb r3, r3 8006af0: 3301 adds r3, #1 8006af2: 069b lsls r3, r3, #26 8006af4: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006af8: 683b ldr r3, [r7, #0] 8006afa: 681b ldr r3, [r3, #0] 8006afc: f3c3 0313 ubfx r3, r3, #0, #20 8006b00: 2b00 cmp r3, #0 8006b02: d109 bne.n 8006b18 8006b04: 683b ldr r3, [r7, #0] 8006b06: 681b ldr r3, [r3, #0] 8006b08: 0e9b lsrs r3, r3, #26 8006b0a: 3301 adds r3, #1 8006b0c: f003 031f and.w r3, r3, #31 8006b10: 2101 movs r1, #1 8006b12: fa01 f303 lsl.w r3, r1, r3 8006b16: e017 b.n 8006b48 8006b18: 683b ldr r3, [r7, #0] 8006b1a: 681b ldr r3, [r3, #0] 8006b1c: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006b1e: 6c3b ldr r3, [r7, #64] @ 0x40 8006b20: fa93 f3a3 rbit r3, r3 8006b24: 63fb str r3, [r7, #60] @ 0x3c return result; 8006b26: 6bfb ldr r3, [r7, #60] @ 0x3c 8006b28: 647b str r3, [r7, #68] @ 0x44 if (value == 0U) 8006b2a: 6c7b ldr r3, [r7, #68] @ 0x44 8006b2c: 2b00 cmp r3, #0 8006b2e: d101 bne.n 8006b34 return 32U; 8006b30: 2320 movs r3, #32 8006b32: e003 b.n 8006b3c return __builtin_clz(value); 8006b34: 6c7b ldr r3, [r7, #68] @ 0x44 8006b36: fab3 f383 clz r3, r3 8006b3a: b2db uxtb r3, r3 8006b3c: 3301 adds r3, #1 8006b3e: f003 031f and.w r3, r3, #31 8006b42: 2101 movs r1, #1 8006b44: fa01 f303 lsl.w r3, r1, r3 8006b48: ea42 0103 orr.w r1, r2, r3 8006b4c: 683b ldr r3, [r7, #0] 8006b4e: 681b ldr r3, [r3, #0] 8006b50: f3c3 0313 ubfx r3, r3, #0, #20 8006b54: 2b00 cmp r3, #0 8006b56: d10a bne.n 8006b6e 8006b58: 683b ldr r3, [r7, #0] 8006b5a: 681b ldr r3, [r3, #0] 8006b5c: 0e9b lsrs r3, r3, #26 8006b5e: 3301 adds r3, #1 8006b60: f003 021f and.w r2, r3, #31 8006b64: 4613 mov r3, r2 8006b66: 005b lsls r3, r3, #1 8006b68: 4413 add r3, r2 8006b6a: 051b lsls r3, r3, #20 8006b6c: e018 b.n 8006ba0 8006b6e: 683b ldr r3, [r7, #0] 8006b70: 681b ldr r3, [r3, #0] 8006b72: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006b74: 6b7b ldr r3, [r7, #52] @ 0x34 8006b76: fa93 f3a3 rbit r3, r3 8006b7a: 633b str r3, [r7, #48] @ 0x30 return result; 8006b7c: 6b3b ldr r3, [r7, #48] @ 0x30 8006b7e: 63bb str r3, [r7, #56] @ 0x38 if (value == 0U) 8006b80: 6bbb ldr r3, [r7, #56] @ 0x38 8006b82: 2b00 cmp r3, #0 8006b84: d101 bne.n 8006b8a return 32U; 8006b86: 2320 movs r3, #32 8006b88: e003 b.n 8006b92 return __builtin_clz(value); 8006b8a: 6bbb ldr r3, [r7, #56] @ 0x38 8006b8c: fab3 f383 clz r3, r3 8006b90: b2db uxtb r3, r3 8006b92: 3301 adds r3, #1 8006b94: f003 021f and.w r2, r3, #31 8006b98: 4613 mov r3, r2 8006b9a: 005b lsls r3, r3, #1 8006b9c: 4413 add r3, r2 8006b9e: 051b lsls r3, r3, #20 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006ba0: 430b orrs r3, r1 8006ba2: e07e b.n 8006ca2 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), 8006ba4: 683b ldr r3, [r7, #0] 8006ba6: 681b ldr r3, [r3, #0] 8006ba8: f3c3 0313 ubfx r3, r3, #0, #20 8006bac: 2b00 cmp r3, #0 8006bae: d107 bne.n 8006bc0 8006bb0: 683b ldr r3, [r7, #0] 8006bb2: 681b ldr r3, [r3, #0] 8006bb4: 0e9b lsrs r3, r3, #26 8006bb6: 3301 adds r3, #1 8006bb8: 069b lsls r3, r3, #26 8006bba: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006bbe: e015 b.n 8006bec 8006bc0: 683b ldr r3, [r7, #0] 8006bc2: 681b ldr r3, [r3, #0] 8006bc4: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006bc6: 6abb ldr r3, [r7, #40] @ 0x28 8006bc8: fa93 f3a3 rbit r3, r3 8006bcc: 627b str r3, [r7, #36] @ 0x24 return result; 8006bce: 6a7b ldr r3, [r7, #36] @ 0x24 8006bd0: 62fb str r3, [r7, #44] @ 0x2c if (value == 0U) 8006bd2: 6afb ldr r3, [r7, #44] @ 0x2c 8006bd4: 2b00 cmp r3, #0 8006bd6: d101 bne.n 8006bdc return 32U; 8006bd8: 2320 movs r3, #32 8006bda: e003 b.n 8006be4 return __builtin_clz(value); 8006bdc: 6afb ldr r3, [r7, #44] @ 0x2c 8006bde: fab3 f383 clz r3, r3 8006be2: b2db uxtb r3, r3 8006be4: 3301 adds r3, #1 8006be6: 069b lsls r3, r3, #26 8006be8: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000 8006bec: 683b ldr r3, [r7, #0] 8006bee: 681b ldr r3, [r3, #0] 8006bf0: f3c3 0313 ubfx r3, r3, #0, #20 8006bf4: 2b00 cmp r3, #0 8006bf6: d109 bne.n 8006c0c 8006bf8: 683b ldr r3, [r7, #0] 8006bfa: 681b ldr r3, [r3, #0] 8006bfc: 0e9b lsrs r3, r3, #26 8006bfe: 3301 adds r3, #1 8006c00: f003 031f and.w r3, r3, #31 8006c04: 2101 movs r1, #1 8006c06: fa01 f303 lsl.w r3, r1, r3 8006c0a: e017 b.n 8006c3c 8006c0c: 683b ldr r3, [r7, #0] 8006c0e: 681b ldr r3, [r3, #0] 8006c10: 61fb str r3, [r7, #28] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006c12: 69fb ldr r3, [r7, #28] 8006c14: fa93 f3a3 rbit r3, r3 8006c18: 61bb str r3, [r7, #24] return result; 8006c1a: 69bb ldr r3, [r7, #24] 8006c1c: 623b str r3, [r7, #32] if (value == 0U) 8006c1e: 6a3b ldr r3, [r7, #32] 8006c20: 2b00 cmp r3, #0 8006c22: d101 bne.n 8006c28 return 32U; 8006c24: 2320 movs r3, #32 8006c26: e003 b.n 8006c30 return __builtin_clz(value); 8006c28: 6a3b ldr r3, [r7, #32] 8006c2a: fab3 f383 clz r3, r3 8006c2e: b2db uxtb r3, r3 8006c30: 3301 adds r3, #1 8006c32: f003 031f and.w r3, r3, #31 8006c36: 2101 movs r1, #1 8006c38: fa01 f303 lsl.w r3, r1, r3 8006c3c: ea42 0103 orr.w r1, r2, r3 8006c40: 683b ldr r3, [r7, #0] 8006c42: 681b ldr r3, [r3, #0] 8006c44: f3c3 0313 ubfx r3, r3, #0, #20 8006c48: 2b00 cmp r3, #0 8006c4a: d10d bne.n 8006c68 8006c4c: 683b ldr r3, [r7, #0] 8006c4e: 681b ldr r3, [r3, #0] 8006c50: 0e9b lsrs r3, r3, #26 8006c52: 3301 adds r3, #1 8006c54: f003 021f and.w r2, r3, #31 8006c58: 4613 mov r3, r2 8006c5a: 005b lsls r3, r3, #1 8006c5c: 4413 add r3, r2 8006c5e: 3b1e subs r3, #30 8006c60: 051b lsls r3, r3, #20 8006c62: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 8006c66: e01b b.n 8006ca0 8006c68: 683b ldr r3, [r7, #0] 8006c6a: 681b ldr r3, [r3, #0] 8006c6c: 613b str r3, [r7, #16] __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8006c6e: 693b ldr r3, [r7, #16] 8006c70: fa93 f3a3 rbit r3, r3 8006c74: 60fb str r3, [r7, #12] return result; 8006c76: 68fb ldr r3, [r7, #12] 8006c78: 617b str r3, [r7, #20] if (value == 0U) 8006c7a: 697b ldr r3, [r7, #20] 8006c7c: 2b00 cmp r3, #0 8006c7e: d101 bne.n 8006c84 return 32U; 8006c80: 2320 movs r3, #32 8006c82: e003 b.n 8006c8c return __builtin_clz(value); 8006c84: 697b ldr r3, [r7, #20] 8006c86: fab3 f383 clz r3, r3 8006c8a: b2db uxtb r3, r3 8006c8c: 3301 adds r3, #1 8006c8e: f003 021f and.w r2, r3, #31 8006c92: 4613 mov r3, r2 8006c94: 005b lsls r3, r3, #1 8006c96: 4413 add r3, r2 8006c98: 3b1e subs r3, #30 8006c9a: 051b lsls r3, r3, #20 8006c9c: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000 LL_ADC_SetChannelSamplingTime(hadc->Instance, 8006ca0: 430b orrs r3, r1 8006ca2: 683a ldr r2, [r7, #0] 8006ca4: 6892 ldr r2, [r2, #8] 8006ca6: 4619 mov r1, r3 8006ca8: f7ff f9e8 bl 800607c /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) 8006cac: 683b ldr r3, [r7, #0] 8006cae: 681b ldr r3, [r3, #0] 8006cb0: 2b00 cmp r3, #0 8006cb2: f280 80cf bge.w 8006e54 { /* Configuration of common ADC parameters */ tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006cb6: 687b ldr r3, [r7, #4] 8006cb8: 681b ldr r3, [r3, #0] 8006cba: 4a06 ldr r2, [pc, #24] @ (8006cd4 ) 8006cbc: 4293 cmp r3, r2 8006cbe: d004 beq.n 8006cca 8006cc0: 687b ldr r3, [r7, #4] 8006cc2: 681b ldr r3, [r3, #0] 8006cc4: 4a04 ldr r2, [pc, #16] @ (8006cd8 ) 8006cc6: 4293 cmp r3, r2 8006cc8: d10a bne.n 8006ce0 8006cca: 4b04 ldr r3, [pc, #16] @ (8006cdc ) 8006ccc: e009 b.n 8006ce2 8006cce: bf00 nop 8006cd0: 47ff0000 .word 0x47ff0000 8006cd4: 40022000 .word 0x40022000 8006cd8: 40022100 .word 0x40022100 8006cdc: 40022300 .word 0x40022300 8006ce0: 4b61 ldr r3, [pc, #388] @ (8006e68 ) 8006ce2: 4618 mov r0, r3 8006ce4: f7ff f916 bl 8005f14 8006ce8: 66f8 str r0, [r7, #108] @ 0x6c /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8006cea: 687b ldr r3, [r7, #4] 8006cec: 681b ldr r3, [r3, #0] 8006cee: 4a5f ldr r2, [pc, #380] @ (8006e6c ) 8006cf0: 4293 cmp r3, r2 8006cf2: d004 beq.n 8006cfe 8006cf4: 687b ldr r3, [r7, #4] 8006cf6: 681b ldr r3, [r3, #0] 8006cf8: 4a5d ldr r2, [pc, #372] @ (8006e70 ) 8006cfa: 4293 cmp r3, r2 8006cfc: d10e bne.n 8006d1c 8006cfe: 485b ldr r0, [pc, #364] @ (8006e6c ) 8006d00: f7ff fa90 bl 8006224 8006d04: 4604 mov r4, r0 8006d06: 485a ldr r0, [pc, #360] @ (8006e70 ) 8006d08: f7ff fa8c bl 8006224 8006d0c: 4603 mov r3, r0 8006d0e: 4323 orrs r3, r4 8006d10: 2b00 cmp r3, #0 8006d12: bf0c ite eq 8006d14: 2301 moveq r3, #1 8006d16: 2300 movne r3, #0 8006d18: b2db uxtb r3, r3 8006d1a: e008 b.n 8006d2e 8006d1c: 4855 ldr r0, [pc, #340] @ (8006e74 ) 8006d1e: f7ff fa81 bl 8006224 8006d22: 4603 mov r3, r0 8006d24: 2b00 cmp r3, #0 8006d26: bf0c ite eq 8006d28: 2301 moveq r3, #1 8006d2a: 2300 movne r3, #0 8006d2c: b2db uxtb r3, r3 8006d2e: 2b00 cmp r3, #0 8006d30: d07d beq.n 8006e2e { /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) 8006d32: 683b ldr r3, [r7, #0] 8006d34: 681b ldr r3, [r3, #0] 8006d36: 4a50 ldr r2, [pc, #320] @ (8006e78 ) 8006d38: 4293 cmp r3, r2 8006d3a: d130 bne.n 8006d9e 8006d3c: 6efb ldr r3, [r7, #108] @ 0x6c 8006d3e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8006d42: 2b00 cmp r3, #0 8006d44: d12b bne.n 8006d9e { if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006d46: 687b ldr r3, [r7, #4] 8006d48: 681b ldr r3, [r3, #0] 8006d4a: 4a4a ldr r2, [pc, #296] @ (8006e74 ) 8006d4c: 4293 cmp r3, r2 8006d4e: f040 8081 bne.w 8006e54 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); 8006d52: 687b ldr r3, [r7, #4] 8006d54: 681b ldr r3, [r3, #0] 8006d56: 4a45 ldr r2, [pc, #276] @ (8006e6c ) 8006d58: 4293 cmp r3, r2 8006d5a: d004 beq.n 8006d66 8006d5c: 687b ldr r3, [r7, #4] 8006d5e: 681b ldr r3, [r3, #0] 8006d60: 4a43 ldr r2, [pc, #268] @ (8006e70 ) 8006d62: 4293 cmp r3, r2 8006d64: d101 bne.n 8006d6a 8006d66: 4a45 ldr r2, [pc, #276] @ (8006e7c ) 8006d68: e000 b.n 8006d6c 8006d6a: 4a3f ldr r2, [pc, #252] @ (8006e68 ) 8006d6c: 6efb ldr r3, [r7, #108] @ 0x6c 8006d6e: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8006d72: 4619 mov r1, r3 8006d74: 4610 mov r0, r2 8006d76: f7ff f8ba bl 8005eee /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8006d7a: 4b41 ldr r3, [pc, #260] @ (8006e80 ) 8006d7c: 681b ldr r3, [r3, #0] 8006d7e: 099b lsrs r3, r3, #6 8006d80: 4a40 ldr r2, [pc, #256] @ (8006e84 ) 8006d82: fba2 2303 umull r2, r3, r2, r3 8006d86: 099b lsrs r3, r3, #6 8006d88: 3301 adds r3, #1 8006d8a: 005b lsls r3, r3, #1 8006d8c: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006d8e: e002 b.n 8006d96 { wait_loop_index--; 8006d90: 68bb ldr r3, [r7, #8] 8006d92: 3b01 subs r3, #1 8006d94: 60bb str r3, [r7, #8] while (wait_loop_index != 0UL) 8006d96: 68bb ldr r3, [r7, #8] 8006d98: 2b00 cmp r3, #0 8006d9a: d1f9 bne.n 8006d90 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 8006d9c: e05a b.n 8006e54 } } } else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) 8006d9e: 683b ldr r3, [r7, #0] 8006da0: 681b ldr r3, [r3, #0] 8006da2: 4a39 ldr r2, [pc, #228] @ (8006e88 ) 8006da4: 4293 cmp r3, r2 8006da6: d11e bne.n 8006de6 8006da8: 6efb ldr r3, [r7, #108] @ 0x6c 8006daa: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8006dae: 2b00 cmp r3, #0 8006db0: d119 bne.n 8006de6 { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006db2: 687b ldr r3, [r7, #4] 8006db4: 681b ldr r3, [r3, #0] 8006db6: 4a2f ldr r2, [pc, #188] @ (8006e74 ) 8006db8: 4293 cmp r3, r2 8006dba: d14b bne.n 8006e54 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); 8006dbc: 687b ldr r3, [r7, #4] 8006dbe: 681b ldr r3, [r3, #0] 8006dc0: 4a2a ldr r2, [pc, #168] @ (8006e6c ) 8006dc2: 4293 cmp r3, r2 8006dc4: d004 beq.n 8006dd0 8006dc6: 687b ldr r3, [r7, #4] 8006dc8: 681b ldr r3, [r3, #0] 8006dca: 4a29 ldr r2, [pc, #164] @ (8006e70 ) 8006dcc: 4293 cmp r3, r2 8006dce: d101 bne.n 8006dd4 8006dd0: 4a2a ldr r2, [pc, #168] @ (8006e7c ) 8006dd2: e000 b.n 8006dd6 8006dd4: 4a24 ldr r2, [pc, #144] @ (8006e68 ) 8006dd6: 6efb ldr r3, [r7, #108] @ 0x6c 8006dd8: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 8006ddc: 4619 mov r1, r3 8006dde: 4610 mov r0, r2 8006de0: f7ff f885 bl 8005eee if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 8006de4: e036 b.n 8006e54 } } else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) 8006de6: 683b ldr r3, [r7, #0] 8006de8: 681b ldr r3, [r3, #0] 8006dea: 4a28 ldr r2, [pc, #160] @ (8006e8c ) 8006dec: 4293 cmp r3, r2 8006dee: d131 bne.n 8006e54 8006df0: 6efb ldr r3, [r7, #108] @ 0x6c 8006df2: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8006df6: 2b00 cmp r3, #0 8006df8: d12c bne.n 8006e54 { if (ADC_VREFINT_INSTANCE(hadc)) 8006dfa: 687b ldr r3, [r7, #4] 8006dfc: 681b ldr r3, [r3, #0] 8006dfe: 4a1d ldr r2, [pc, #116] @ (8006e74 ) 8006e00: 4293 cmp r3, r2 8006e02: d127 bne.n 8006e54 { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); 8006e04: 687b ldr r3, [r7, #4] 8006e06: 681b ldr r3, [r3, #0] 8006e08: 4a18 ldr r2, [pc, #96] @ (8006e6c ) 8006e0a: 4293 cmp r3, r2 8006e0c: d004 beq.n 8006e18 8006e0e: 687b ldr r3, [r7, #4] 8006e10: 681b ldr r3, [r3, #0] 8006e12: 4a17 ldr r2, [pc, #92] @ (8006e70 ) 8006e14: 4293 cmp r3, r2 8006e16: d101 bne.n 8006e1c 8006e18: 4a18 ldr r2, [pc, #96] @ (8006e7c ) 8006e1a: e000 b.n 8006e1e 8006e1c: 4a12 ldr r2, [pc, #72] @ (8006e68 ) 8006e1e: 6efb ldr r3, [r7, #108] @ 0x6c 8006e20: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 8006e24: 4619 mov r1, r3 8006e26: 4610 mov r0, r2 8006e28: f7ff f861 bl 8005eee 8006e2c: e012 b.n 8006e54 /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006e2e: 687b ldr r3, [r7, #4] 8006e30: 6d5b ldr r3, [r3, #84] @ 0x54 8006e32: f043 0220 orr.w r2, r3, #32 8006e36: 687b ldr r3, [r7, #4] 8006e38: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006e3a: 2301 movs r3, #1 8006e3c: f887 307f strb.w r3, [r7, #127] @ 0x7f 8006e40: e008 b.n 8006e54 /* channel could be done on neither of the channel configuration structure */ /* parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8006e42: 687b ldr r3, [r7, #4] 8006e44: 6d5b ldr r3, [r3, #84] @ 0x54 8006e46: f043 0220 orr.w r2, r3, #32 8006e4a: 687b ldr r3, [r7, #4] 8006e4c: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 8006e4e: 2301 movs r3, #1 8006e50: f887 307f strb.w r3, [r7, #127] @ 0x7f } /* Process unlocked */ __HAL_UNLOCK(hadc); 8006e54: 687b ldr r3, [r7, #4] 8006e56: 2200 movs r2, #0 8006e58: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 8006e5c: f897 307f ldrb.w r3, [r7, #127] @ 0x7f } 8006e60: 4618 mov r0, r3 8006e62: 3784 adds r7, #132 @ 0x84 8006e64: 46bd mov sp, r7 8006e66: bd90 pop {r4, r7, pc} 8006e68: 58026300 .word 0x58026300 8006e6c: 40022000 .word 0x40022000 8006e70: 40022100 .word 0x40022100 8006e74: 58026000 .word 0x58026000 8006e78: cb840000 .word 0xcb840000 8006e7c: 40022300 .word 0x40022300 8006e80: 24000034 .word 0x24000034 8006e84: 053e2d63 .word 0x053e2d63 8006e88: c7520000 .word 0xc7520000 8006e8c: cfb80000 .word 0xcfb80000 08006e90 : * and voltage regulator must be enabled (done into HAL_ADC_Init()). * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { 8006e90: b580 push {r7, lr} 8006e92: b084 sub sp, #16 8006e94: af00 add r7, sp, #0 8006e96: 6078 str r0, [r7, #4] /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006e98: 687b ldr r3, [r7, #4] 8006e9a: 681b ldr r3, [r3, #0] 8006e9c: 4618 mov r0, r3 8006e9e: f7ff f9c1 bl 8006224 8006ea2: 4603 mov r3, r0 8006ea4: 2b00 cmp r3, #0 8006ea6: d16e bne.n 8006f86 { /* Check if conditions to enable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) 8006ea8: 687b ldr r3, [r7, #4] 8006eaa: 681b ldr r3, [r3, #0] 8006eac: 689a ldr r2, [r3, #8] 8006eae: 4b38 ldr r3, [pc, #224] @ (8006f90 ) 8006eb0: 4013 ands r3, r2 8006eb2: 2b00 cmp r3, #0 8006eb4: d00d beq.n 8006ed2 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006eb6: 687b ldr r3, [r7, #4] 8006eb8: 6d5b ldr r3, [r3, #84] @ 0x54 8006eba: f043 0210 orr.w r2, r3, #16 8006ebe: 687b ldr r3, [r7, #4] 8006ec0: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006ec2: 687b ldr r3, [r7, #4] 8006ec4: 6d9b ldr r3, [r3, #88] @ 0x58 8006ec6: f043 0201 orr.w r2, r3, #1 8006eca: 687b ldr r3, [r7, #4] 8006ecc: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006ece: 2301 movs r3, #1 8006ed0: e05a b.n 8006f88 } /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); 8006ed2: 687b ldr r3, [r7, #4] 8006ed4: 681b ldr r3, [r3, #0] 8006ed6: 4618 mov r0, r3 8006ed8: f7ff f97c bl 80061d4 /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); 8006edc: f7fe ffa2 bl 8005e24 8006ee0: 60f8 str r0, [r7, #12] /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); 8006ee2: 687b ldr r3, [r7, #4] 8006ee4: 681b ldr r3, [r3, #0] 8006ee6: 4a2b ldr r2, [pc, #172] @ (8006f94 ) 8006ee8: 4293 cmp r3, r2 8006eea: d004 beq.n 8006ef6 8006eec: 687b ldr r3, [r7, #4] 8006eee: 681b ldr r3, [r3, #0] 8006ef0: 4a29 ldr r2, [pc, #164] @ (8006f98 ) 8006ef2: 4293 cmp r3, r2 8006ef4: d101 bne.n 8006efa 8006ef6: 4b29 ldr r3, [pc, #164] @ (8006f9c ) 8006ef8: e000 b.n 8006efc 8006efa: 4b29 ldr r3, [pc, #164] @ (8006fa0 ) 8006efc: 4618 mov r0, r3 8006efe: f7ff f90d bl 800611c 8006f02: 60b8 str r0, [r7, #8] if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) 8006f04: 687b ldr r3, [r7, #4] 8006f06: 681b ldr r3, [r3, #0] 8006f08: 4a23 ldr r2, [pc, #140] @ (8006f98 ) 8006f0a: 4293 cmp r3, r2 8006f0c: d002 beq.n 8006f14 8006f0e: 687b ldr r3, [r7, #4] 8006f10: 681b ldr r3, [r3, #0] 8006f12: e000 b.n 8006f16 8006f14: 4b1f ldr r3, [pc, #124] @ (8006f94 ) 8006f16: 687a ldr r2, [r7, #4] 8006f18: 6812 ldr r2, [r2, #0] 8006f1a: 4293 cmp r3, r2 8006f1c: d02c beq.n 8006f78 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) 8006f1e: 68bb ldr r3, [r7, #8] 8006f20: 2b00 cmp r3, #0 8006f22: d130 bne.n 8006f86 ) { while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006f24: e028 b.n 8006f78 The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 4 ADC clock cycle duration */ /* Note: Test of ADC enabled required due to hardware constraint to */ /* not enable ADC if already enabled. */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 8006f26: 687b ldr r3, [r7, #4] 8006f28: 681b ldr r3, [r3, #0] 8006f2a: 4618 mov r0, r3 8006f2c: f7ff f97a bl 8006224 8006f30: 4603 mov r3, r0 8006f32: 2b00 cmp r3, #0 8006f34: d104 bne.n 8006f40 { LL_ADC_Enable(hadc->Instance); 8006f36: 687b ldr r3, [r7, #4] 8006f38: 681b ldr r3, [r3, #0] 8006f3a: 4618 mov r0, r3 8006f3c: f7ff f94a bl 80061d4 } if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 8006f40: f7fe ff70 bl 8005e24 8006f44: 4602 mov r2, r0 8006f46: 68fb ldr r3, [r7, #12] 8006f48: 1ad3 subs r3, r2, r3 8006f4a: 2b02 cmp r3, #2 8006f4c: d914 bls.n 8006f78 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006f4e: 687b ldr r3, [r7, #4] 8006f50: 681b ldr r3, [r3, #0] 8006f52: 681b ldr r3, [r3, #0] 8006f54: f003 0301 and.w r3, r3, #1 8006f58: 2b01 cmp r3, #1 8006f5a: d00d beq.n 8006f78 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006f5c: 687b ldr r3, [r7, #4] 8006f5e: 6d5b ldr r3, [r3, #84] @ 0x54 8006f60: f043 0210 orr.w r2, r3, #16 8006f64: 687b ldr r3, [r7, #4] 8006f66: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8006f68: 687b ldr r3, [r7, #4] 8006f6a: 6d9b ldr r3, [r3, #88] @ 0x58 8006f6c: f043 0201 orr.w r2, r3, #1 8006f70: 687b ldr r3, [r7, #4] 8006f72: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8006f74: 2301 movs r3, #1 8006f76: e007 b.n 8006f88 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) 8006f78: 687b ldr r3, [r7, #4] 8006f7a: 681b ldr r3, [r3, #0] 8006f7c: 681b ldr r3, [r3, #0] 8006f7e: f003 0301 and.w r3, r3, #1 8006f82: 2b01 cmp r3, #1 8006f84: d1cf bne.n 8006f26 } } } /* Return HAL status */ return HAL_OK; 8006f86: 2300 movs r3, #0 } 8006f88: 4618 mov r0, r3 8006f8a: 3710 adds r7, #16 8006f8c: 46bd mov sp, r7 8006f8e: bd80 pop {r7, pc} 8006f90: 8000003f .word 0x8000003f 8006f94: 40022000 .word 0x40022000 8006f98: 40022100 .word 0x40022100 8006f9c: 40022300 .word 0x40022300 8006fa0: 58026300 .word 0x58026300 08006fa4 : * stopped. * @param hadc ADC handle * @retval HAL status. */ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { 8006fa4: b580 push {r7, lr} 8006fa6: b084 sub sp, #16 8006fa8: af00 add r7, sp, #0 8006faa: 6078 str r0, [r7, #4] uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); 8006fac: 687b ldr r3, [r7, #4] 8006fae: 681b ldr r3, [r3, #0] 8006fb0: 4618 mov r0, r3 8006fb2: f7ff f94a bl 800624a 8006fb6: 60f8 str r0, [r7, #12] /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) 8006fb8: 687b ldr r3, [r7, #4] 8006fba: 681b ldr r3, [r3, #0] 8006fbc: 4618 mov r0, r3 8006fbe: f7ff f931 bl 8006224 8006fc2: 4603 mov r3, r0 8006fc4: 2b00 cmp r3, #0 8006fc6: d047 beq.n 8007058 && (tmp_adc_is_disable_on_going == 0UL) 8006fc8: 68fb ldr r3, [r7, #12] 8006fca: 2b00 cmp r3, #0 8006fcc: d144 bne.n 8007058 ) { /* Check if conditions to disable the ADC are fulfilled */ if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) 8006fce: 687b ldr r3, [r7, #4] 8006fd0: 681b ldr r3, [r3, #0] 8006fd2: 689b ldr r3, [r3, #8] 8006fd4: f003 030d and.w r3, r3, #13 8006fd8: 2b01 cmp r3, #1 8006fda: d10c bne.n 8006ff6 { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); 8006fdc: 687b ldr r3, [r7, #4] 8006fde: 681b ldr r3, [r3, #0] 8006fe0: 4618 mov r0, r3 8006fe2: f7ff f90b bl 80061fc __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 8006fe6: 687b ldr r3, [r7, #4] 8006fe8: 681b ldr r3, [r3, #0] 8006fea: 2203 movs r2, #3 8006fec: 601a str r2, [r3, #0] return HAL_ERROR; } /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); 8006fee: f7fe ff19 bl 8005e24 8006ff2: 60b8 str r0, [r7, #8] while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8006ff4: e029 b.n 800704a SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 8006ff6: 687b ldr r3, [r7, #4] 8006ff8: 6d5b ldr r3, [r3, #84] @ 0x54 8006ffa: f043 0210 orr.w r2, r3, #16 8006ffe: 687b ldr r3, [r7, #4] 8007000: 655a str r2, [r3, #84] @ 0x54 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 8007002: 687b ldr r3, [r7, #4] 8007004: 6d9b ldr r3, [r3, #88] @ 0x58 8007006: f043 0201 orr.w r2, r3, #1 800700a: 687b ldr r3, [r7, #4] 800700c: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 800700e: 2301 movs r3, #1 8007010: e023 b.n 800705a { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 8007012: f7fe ff07 bl 8005e24 8007016: 4602 mov r2, r0 8007018: 68bb ldr r3, [r7, #8] 800701a: 1ad3 subs r3, r2, r3 800701c: 2b02 cmp r3, #2 800701e: d914 bls.n 800704a { /* New check to avoid false timeout detection in case of preemption */ if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 8007020: 687b ldr r3, [r7, #4] 8007022: 681b ldr r3, [r3, #0] 8007024: 689b ldr r3, [r3, #8] 8007026: f003 0301 and.w r3, r3, #1 800702a: 2b00 cmp r3, #0 800702c: d00d beq.n 800704a { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 800702e: 687b ldr r3, [r7, #4] 8007030: 6d5b ldr r3, [r3, #84] @ 0x54 8007032: f043 0210 orr.w r2, r3, #16 8007036: 687b ldr r3, [r7, #4] 8007038: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 800703a: 687b ldr r3, [r7, #4] 800703c: 6d9b ldr r3, [r3, #88] @ 0x58 800703e: f043 0201 orr.w r2, r3, #1 8007042: 687b ldr r3, [r7, #4] 8007044: 659a str r2, [r3, #88] @ 0x58 return HAL_ERROR; 8007046: 2301 movs r3, #1 8007048: e007 b.n 800705a while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) 800704a: 687b ldr r3, [r7, #4] 800704c: 681b ldr r3, [r3, #0] 800704e: 689b ldr r3, [r3, #8] 8007050: f003 0301 and.w r3, r3, #1 8007054: 2b00 cmp r3, #0 8007056: d1dc bne.n 8007012 } } } /* Return HAL status */ return HAL_OK; 8007058: 2300 movs r3, #0 } 800705a: 4618 mov r0, r3 800705c: 3710 adds r7, #16 800705e: 46bd mov sp, r7 8007060: bd80 pop {r7, pc} 08007062 : * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { 8007062: b580 push {r7, lr} 8007064: b084 sub sp, #16 8007066: af00 add r7, sp, #0 8007068: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800706a: 687b ldr r3, [r7, #4] 800706c: 6b9b ldr r3, [r3, #56] @ 0x38 800706e: 60fb str r3, [r7, #12] /* Update state machine on conversion status if not in error state */ if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) 8007070: 68fb ldr r3, [r7, #12] 8007072: 6d5b ldr r3, [r3, #84] @ 0x54 8007074: f003 0350 and.w r3, r3, #80 @ 0x50 8007078: 2b00 cmp r3, #0 800707a: d14b bne.n 8007114 { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 800707c: 68fb ldr r3, [r7, #12] 800707e: 6d5b ldr r3, [r3, #84] @ 0x54 8007080: f443 7200 orr.w r2, r3, #512 @ 0x200 8007084: 68fb ldr r3, [r7, #12] 8007086: 655a str r2, [r3, #84] @ 0x54 /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ /* Is it the end of the regular sequence ? */ if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) 8007088: 68fb ldr r3, [r7, #12] 800708a: 681b ldr r3, [r3, #0] 800708c: 681b ldr r3, [r3, #0] 800708e: f003 0308 and.w r3, r3, #8 8007092: 2b00 cmp r3, #0 8007094: d021 beq.n 80070da { /* Are conversions software-triggered ? */ if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) 8007096: 68fb ldr r3, [r7, #12] 8007098: 681b ldr r3, [r3, #0] 800709a: 4618 mov r0, r3 800709c: f7fe ff9c bl 8005fd8 80070a0: 4603 mov r3, r0 80070a2: 2b00 cmp r3, #0 80070a4: d032 beq.n 800710c { /* Is CONT bit set ? */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) 80070a6: 68fb ldr r3, [r7, #12] 80070a8: 681b ldr r3, [r3, #0] 80070aa: 68db ldr r3, [r3, #12] 80070ac: f403 5300 and.w r3, r3, #8192 @ 0x2000 80070b0: 2b00 cmp r3, #0 80070b2: d12b bne.n 800710c { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80070b4: 68fb ldr r3, [r7, #12] 80070b6: 6d5b ldr r3, [r3, #84] @ 0x54 80070b8: f423 7280 bic.w r2, r3, #256 @ 0x100 80070bc: 68fb ldr r3, [r7, #12] 80070be: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 80070c0: 68fb ldr r3, [r7, #12] 80070c2: 6d5b ldr r3, [r3, #84] @ 0x54 80070c4: f403 5380 and.w r3, r3, #4096 @ 0x1000 80070c8: 2b00 cmp r3, #0 80070ca: d11f bne.n 800710c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 80070cc: 68fb ldr r3, [r7, #12] 80070ce: 6d5b ldr r3, [r3, #84] @ 0x54 80070d0: f043 0201 orr.w r2, r3, #1 80070d4: 68fb ldr r3, [r7, #12] 80070d6: 655a str r2, [r3, #84] @ 0x54 80070d8: e018 b.n 800710c } else { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) 80070da: 68fb ldr r3, [r7, #12] 80070dc: 681b ldr r3, [r3, #0] 80070de: 68db ldr r3, [r3, #12] 80070e0: f003 0303 and.w r3, r3, #3 80070e4: 2b00 cmp r3, #0 80070e6: d111 bne.n 800710c { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 80070e8: 68fb ldr r3, [r7, #12] 80070ea: 6d5b ldr r3, [r3, #84] @ 0x54 80070ec: f423 7280 bic.w r2, r3, #256 @ 0x100 80070f0: 68fb ldr r3, [r7, #12] 80070f2: 655a str r2, [r3, #84] @ 0x54 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) 80070f4: 68fb ldr r3, [r7, #12] 80070f6: 6d5b ldr r3, [r3, #84] @ 0x54 80070f8: f403 5380 and.w r3, r3, #4096 @ 0x1000 80070fc: 2b00 cmp r3, #0 80070fe: d105 bne.n 800710c { SET_BIT(hadc->State, HAL_ADC_STATE_READY); 8007100: 68fb ldr r3, [r7, #12] 8007102: 6d5b ldr r3, [r3, #84] @ 0x54 8007104: f043 0201 orr.w r2, r3, #1 8007108: 68fb ldr r3, [r7, #12] 800710a: 655a str r2, [r3, #84] @ 0x54 /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); 800710c: 68f8 ldr r0, [r7, #12] 800710e: f7fa fb5b bl 80017c8 { /* Call ADC DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } } } 8007112: e00e b.n 8007132 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) 8007114: 68fb ldr r3, [r7, #12] 8007116: 6d5b ldr r3, [r3, #84] @ 0x54 8007118: f003 0310 and.w r3, r3, #16 800711c: 2b00 cmp r3, #0 800711e: d003 beq.n 8007128 HAL_ADC_ErrorCallback(hadc); 8007120: 68f8 ldr r0, [r7, #12] 8007122: f7ff fb4f bl 80067c4 } 8007126: e004 b.n 8007132 hadc->DMA_Handle->XferErrorCallback(hdma); 8007128: 68fb ldr r3, [r7, #12] 800712a: 6cdb ldr r3, [r3, #76] @ 0x4c 800712c: 6cdb ldr r3, [r3, #76] @ 0x4c 800712e: 6878 ldr r0, [r7, #4] 8007130: 4798 blx r3 } 8007132: bf00 nop 8007134: 3710 adds r7, #16 8007136: 46bd mov sp, r7 8007138: bd80 pop {r7, pc} 0800713a : * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { 800713a: b580 push {r7, lr} 800713c: b084 sub sp, #16 800713e: af00 add r7, sp, #0 8007140: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 8007142: 687b ldr r3, [r7, #4] 8007144: 6b9b ldr r3, [r3, #56] @ 0x38 8007146: 60fb str r3, [r7, #12] /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else HAL_ADC_ConvHalfCpltCallback(hadc); 8007148: 68f8 ldr r0, [r7, #12] 800714a: f7ff fb31 bl 80067b0 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 800714e: bf00 nop 8007150: 3710 adds r7, #16 8007152: 46bd mov sp, r7 8007154: bd80 pop {r7, pc} 08007156 : * @brief DMA error callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAError(DMA_HandleTypeDef *hdma) { 8007156: b580 push {r7, lr} 8007158: b084 sub sp, #16 800715a: af00 add r7, sp, #0 800715c: 6078 str r0, [r7, #4] /* Retrieve ADC handle corresponding to current DMA handle */ ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; 800715e: 687b ldr r3, [r7, #4] 8007160: 6b9b ldr r3, [r3, #56] @ 0x38 8007162: 60fb str r3, [r7, #12] /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 8007164: 68fb ldr r3, [r7, #12] 8007166: 6d5b ldr r3, [r3, #84] @ 0x54 8007168: f043 0240 orr.w r2, r3, #64 @ 0x40 800716c: 68fb ldr r3, [r7, #12] 800716e: 655a str r2, [r3, #84] @ 0x54 /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 8007170: 68fb ldr r3, [r7, #12] 8007172: 6d9b ldr r3, [r3, #88] @ 0x58 8007174: f043 0204 orr.w r2, r3, #4 8007178: 68fb ldr r3, [r7, #12] 800717a: 659a str r2, [r3, #88] @ 0x58 /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else HAL_ADC_ErrorCallback(hadc); 800717c: 68f8 ldr r0, [r7, #12] 800717e: f7ff fb21 bl 80067c4 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } 8007182: bf00 nop 8007184: 3710 adds r7, #16 8007186: 46bd mov sp, r7 8007188: bd80 pop {r7, pc} ... 0800718c : * stopped. * @param hadc ADC handle * @retval None. */ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc) { 800718c: b580 push {r7, lr} 800718e: b084 sub sp, #16 8007190: af00 add r7, sp, #0 8007192: 6078 str r0, [r7, #4] uint32_t freq; if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc)) 8007194: 687b ldr r3, [r7, #4] 8007196: 681b ldr r3, [r3, #0] 8007198: 4a7a ldr r2, [pc, #488] @ (8007384 ) 800719a: 4293 cmp r3, r2 800719c: d004 beq.n 80071a8 800719e: 687b ldr r3, [r7, #4] 80071a0: 681b ldr r3, [r3, #0] 80071a2: 4a79 ldr r2, [pc, #484] @ (8007388 ) 80071a4: 4293 cmp r3, r2 80071a6: d109 bne.n 80071bc 80071a8: 4b78 ldr r3, [pc, #480] @ (800738c ) 80071aa: 689b ldr r3, [r3, #8] 80071ac: f403 3340 and.w r3, r3, #196608 @ 0x30000 80071b0: 2b00 cmp r3, #0 80071b2: bf14 ite ne 80071b4: 2301 movne r3, #1 80071b6: 2300 moveq r3, #0 80071b8: b2db uxtb r3, r3 80071ba: e008 b.n 80071ce 80071bc: 4b74 ldr r3, [pc, #464] @ (8007390 ) 80071be: 689b ldr r3, [r3, #8] 80071c0: f403 3340 and.w r3, r3, #196608 @ 0x30000 80071c4: 2b00 cmp r3, #0 80071c6: bf14 ite ne 80071c8: 2301 movne r3, #1 80071ca: 2300 moveq r3, #0 80071cc: b2db uxtb r3, r3 80071ce: 2b00 cmp r3, #0 80071d0: d01c beq.n 800720c { freq = HAL_RCC_GetHCLKFreq(); 80071d2: f005 fb47 bl 800c864 80071d6: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 80071d8: 687b ldr r3, [r7, #4] 80071da: 685b ldr r3, [r3, #4] 80071dc: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 80071e0: d010 beq.n 8007204 80071e2: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 80071e6: d873 bhi.n 80072d0 80071e8: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80071ec: d002 beq.n 80071f4 80071ee: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 80071f2: d16d bne.n 80072d0 { case ADC_CLOCK_SYNC_PCLK_DIV1: case ADC_CLOCK_SYNC_PCLK_DIV2: freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos); 80071f4: 687b ldr r3, [r7, #4] 80071f6: 685b ldr r3, [r3, #4] 80071f8: 0c1b lsrs r3, r3, #16 80071fa: 68fa ldr r2, [r7, #12] 80071fc: fbb2 f3f3 udiv r3, r2, r3 8007200: 60fb str r3, [r7, #12] break; 8007202: e068 b.n 80072d6 case ADC_CLOCK_SYNC_PCLK_DIV4: freq /= 4UL; 8007204: 68fb ldr r3, [r7, #12] 8007206: 089b lsrs r3, r3, #2 8007208: 60fb str r3, [r7, #12] break; 800720a: e064 b.n 80072d6 break; } } else { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC); 800720c: f44f 2000 mov.w r0, #524288 @ 0x80000 8007210: f04f 0100 mov.w r1, #0 8007214: f006 fdb2 bl 800dd7c 8007218: 60f8 str r0, [r7, #12] switch (hadc->Init.ClockPrescaler) 800721a: 687b ldr r3, [r7, #4] 800721c: 685b ldr r3, [r3, #4] 800721e: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8007222: d051 beq.n 80072c8 8007224: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000 8007228: d854 bhi.n 80072d4 800722a: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 800722e: d047 beq.n 80072c0 8007230: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000 8007234: d84e bhi.n 80072d4 8007236: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 800723a: d03d beq.n 80072b8 800723c: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000 8007240: d848 bhi.n 80072d4 8007242: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8007246: d033 beq.n 80072b0 8007248: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800724c: d842 bhi.n 80072d4 800724e: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8007252: d029 beq.n 80072a8 8007254: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000 8007258: d83c bhi.n 80072d4 800725a: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 800725e: d01a beq.n 8007296 8007260: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000 8007264: d836 bhi.n 80072d4 8007266: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 800726a: d014 beq.n 8007296 800726c: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000 8007270: d830 bhi.n 80072d4 8007272: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8007276: d00e beq.n 8007296 8007278: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800727c: d82a bhi.n 80072d4 800727e: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8007282: d008 beq.n 8007296 8007284: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000 8007288: d824 bhi.n 80072d4 800728a: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800728e: d002 beq.n 8007296 8007290: f5b3 2f00 cmp.w r3, #524288 @ 0x80000 8007294: d11e bne.n 80072d4 case ADC_CLOCK_ASYNC_DIV4: case ADC_CLOCK_ASYNC_DIV6: case ADC_CLOCK_ASYNC_DIV8: case ADC_CLOCK_ASYNC_DIV10: case ADC_CLOCK_ASYNC_DIV12: freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL); 8007296: 687b ldr r3, [r7, #4] 8007298: 685b ldr r3, [r3, #4] 800729a: 0c9b lsrs r3, r3, #18 800729c: 005b lsls r3, r3, #1 800729e: 68fa ldr r2, [r7, #12] 80072a0: fbb2 f3f3 udiv r3, r2, r3 80072a4: 60fb str r3, [r7, #12] break; 80072a6: e016 b.n 80072d6 case ADC_CLOCK_ASYNC_DIV16: freq /= 16UL; 80072a8: 68fb ldr r3, [r7, #12] 80072aa: 091b lsrs r3, r3, #4 80072ac: 60fb str r3, [r7, #12] break; 80072ae: e012 b.n 80072d6 case ADC_CLOCK_ASYNC_DIV32: freq /= 32UL; 80072b0: 68fb ldr r3, [r7, #12] 80072b2: 095b lsrs r3, r3, #5 80072b4: 60fb str r3, [r7, #12] break; 80072b6: e00e b.n 80072d6 case ADC_CLOCK_ASYNC_DIV64: freq /= 64UL; 80072b8: 68fb ldr r3, [r7, #12] 80072ba: 099b lsrs r3, r3, #6 80072bc: 60fb str r3, [r7, #12] break; 80072be: e00a b.n 80072d6 case ADC_CLOCK_ASYNC_DIV128: freq /= 128UL; 80072c0: 68fb ldr r3, [r7, #12] 80072c2: 09db lsrs r3, r3, #7 80072c4: 60fb str r3, [r7, #12] break; 80072c6: e006 b.n 80072d6 case ADC_CLOCK_ASYNC_DIV256: freq /= 256UL; 80072c8: 68fb ldr r3, [r7, #12] 80072ca: 0a1b lsrs r3, r3, #8 80072cc: 60fb str r3, [r7, #12] break; 80072ce: e002 b.n 80072d6 break; 80072d0: bf00 nop 80072d2: e000 b.n 80072d6 default: break; 80072d4: bf00 nop else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } #else if (HAL_GetREVID() <= REV_ID_Y) /* STM32H7 silicon Rev.Y */ 80072d6: f7fe fdb1 bl 8005e3c 80072da: 4603 mov r3, r0 80072dc: f241 0203 movw r2, #4099 @ 0x1003 80072e0: 4293 cmp r3, r2 80072e2: d815 bhi.n 8007310 { if (freq > 20000000UL) 80072e4: 68fb ldr r3, [r7, #12] 80072e6: 4a2b ldr r2, [pc, #172] @ (8007394 ) 80072e8: 4293 cmp r3, r2 80072ea: d908 bls.n 80072fe { SET_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80072ec: 687b ldr r3, [r7, #4] 80072ee: 681b ldr r3, [r3, #0] 80072f0: 689a ldr r2, [r3, #8] 80072f2: 687b ldr r3, [r7, #4] 80072f4: 681b ldr r3, [r3, #0] 80072f6: f442 7280 orr.w r2, r2, #256 @ 0x100 80072fa: 609a str r2, [r3, #8] { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } } #endif /* ADC_VER_V5_3 */ } 80072fc: e03e b.n 800737c CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); 80072fe: 687b ldr r3, [r7, #4] 8007300: 681b ldr r3, [r3, #0] 8007302: 689a ldr r2, [r3, #8] 8007304: 687b ldr r3, [r7, #4] 8007306: 681b ldr r3, [r3, #0] 8007308: f422 7280 bic.w r2, r2, #256 @ 0x100 800730c: 609a str r2, [r3, #8] } 800730e: e035 b.n 800737c freq /= 2U; /* divider by 2 for Rev.V */ 8007310: 68fb ldr r3, [r7, #12] 8007312: 085b lsrs r3, r3, #1 8007314: 60fb str r3, [r7, #12] if (freq <= 6250000UL) 8007316: 68fb ldr r3, [r7, #12] 8007318: 4a1f ldr r2, [pc, #124] @ (8007398 ) 800731a: 4293 cmp r3, r2 800731c: d808 bhi.n 8007330 MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); 800731e: 687b ldr r3, [r7, #4] 8007320: 681b ldr r3, [r3, #0] 8007322: 689a ldr r2, [r3, #8] 8007324: 687b ldr r3, [r7, #4] 8007326: 681b ldr r3, [r3, #0] 8007328: f422 7240 bic.w r2, r2, #768 @ 0x300 800732c: 609a str r2, [r3, #8] } 800732e: e025 b.n 800737c else if (freq <= 12500000UL) 8007330: 68fb ldr r3, [r7, #12] 8007332: 4a1a ldr r2, [pc, #104] @ (800739c ) 8007334: 4293 cmp r3, r2 8007336: d80a bhi.n 800734e MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); 8007338: 687b ldr r3, [r7, #4] 800733a: 681b ldr r3, [r3, #0] 800733c: 689b ldr r3, [r3, #8] 800733e: f423 7240 bic.w r2, r3, #768 @ 0x300 8007342: 687b ldr r3, [r7, #4] 8007344: 681b ldr r3, [r3, #0] 8007346: f442 7280 orr.w r2, r2, #256 @ 0x100 800734a: 609a str r2, [r3, #8] } 800734c: e016 b.n 800737c else if (freq <= 25000000UL) 800734e: 68fb ldr r3, [r7, #12] 8007350: 4a13 ldr r2, [pc, #76] @ (80073a0 ) 8007352: 4293 cmp r3, r2 8007354: d80a bhi.n 800736c MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); 8007356: 687b ldr r3, [r7, #4] 8007358: 681b ldr r3, [r3, #0] 800735a: 689b ldr r3, [r3, #8] 800735c: f423 7240 bic.w r2, r3, #768 @ 0x300 8007360: 687b ldr r3, [r7, #4] 8007362: 681b ldr r3, [r3, #0] 8007364: f442 7200 orr.w r2, r2, #512 @ 0x200 8007368: 609a str r2, [r3, #8] } 800736a: e007 b.n 800737c MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); 800736c: 687b ldr r3, [r7, #4] 800736e: 681b ldr r3, [r3, #0] 8007370: 689a ldr r2, [r3, #8] 8007372: 687b ldr r3, [r7, #4] 8007374: 681b ldr r3, [r3, #0] 8007376: f442 7240 orr.w r2, r2, #768 @ 0x300 800737a: 609a str r2, [r3, #8] } 800737c: bf00 nop 800737e: 3710 adds r7, #16 8007380: 46bd mov sp, r7 8007382: bd80 pop {r7, pc} 8007384: 40022000 .word 0x40022000 8007388: 40022100 .word 0x40022100 800738c: 40022300 .word 0x40022300 8007390: 58026300 .word 0x58026300 8007394: 01312d00 .word 0x01312d00 8007398: 005f5e10 .word 0x005f5e10 800739c: 00bebc20 .word 0x00bebc20 80073a0: 017d7840 .word 0x017d7840 080073a4 : { 80073a4: b480 push {r7} 80073a6: b083 sub sp, #12 80073a8: af00 add r7, sp, #0 80073aa: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); 80073ac: 687b ldr r3, [r7, #4] 80073ae: 689b ldr r3, [r3, #8] 80073b0: f003 0301 and.w r3, r3, #1 80073b4: 2b01 cmp r3, #1 80073b6: d101 bne.n 80073bc 80073b8: 2301 movs r3, #1 80073ba: e000 b.n 80073be 80073bc: 2300 movs r3, #0 } 80073be: 4618 mov r0, r3 80073c0: 370c adds r7, #12 80073c2: 46bd mov sp, r7 80073c4: f85d 7b04 ldr.w r7, [sp], #4 80073c8: 4770 bx lr ... 080073cc : { 80073cc: b480 push {r7} 80073ce: b085 sub sp, #20 80073d0: af00 add r7, sp, #0 80073d2: 60f8 str r0, [r7, #12] 80073d4: 60b9 str r1, [r7, #8] 80073d6: 607a str r2, [r7, #4] MODIFY_REG(ADCx->CR, 80073d8: 68fb ldr r3, [r7, #12] 80073da: 689a ldr r2, [r3, #8] 80073dc: 4b09 ldr r3, [pc, #36] @ (8007404 ) 80073de: 4013 ands r3, r2 80073e0: 68ba ldr r2, [r7, #8] 80073e2: f402 3180 and.w r1, r2, #65536 @ 0x10000 80073e6: 687a ldr r2, [r7, #4] 80073e8: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000 80073ec: 430a orrs r2, r1 80073ee: 4313 orrs r3, r2 80073f0: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000 80073f4: 68fb ldr r3, [r7, #12] 80073f6: 609a str r2, [r3, #8] } 80073f8: bf00 nop 80073fa: 3714 adds r7, #20 80073fc: 46bd mov sp, r7 80073fe: f85d 7b04 ldr.w r7, [sp], #4 8007402: 4770 bx lr 8007404: 3ffeffc0 .word 0x3ffeffc0 08007408 : { 8007408: b480 push {r7} 800740a: b083 sub sp, #12 800740c: af00 add r7, sp, #0 800740e: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); 8007410: 687b ldr r3, [r7, #4] 8007412: 689b ldr r3, [r3, #8] 8007414: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007418: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800741c: d101 bne.n 8007422 800741e: 2301 movs r3, #1 8007420: e000 b.n 8007424 8007422: 2300 movs r3, #0 } 8007424: 4618 mov r0, r3 8007426: 370c adds r7, #12 8007428: 46bd mov sp, r7 800742a: f85d 7b04 ldr.w r7, [sp], #4 800742e: 4770 bx lr 08007430 : { 8007430: b480 push {r7} 8007432: b083 sub sp, #12 8007434: af00 add r7, sp, #0 8007436: 6078 str r0, [r7, #4] return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); 8007438: 687b ldr r3, [r7, #4] 800743a: 689b ldr r3, [r3, #8] 800743c: f003 0304 and.w r3, r3, #4 8007440: 2b04 cmp r3, #4 8007442: d101 bne.n 8007448 8007444: 2301 movs r3, #1 8007446: e000 b.n 800744a 8007448: 2300 movs r3, #0 } 800744a: 4618 mov r0, r3 800744c: 370c adds r7, #12 800744e: 46bd mov sp, r7 8007450: f85d 7b04 ldr.w r7, [sp], #4 8007454: 4770 bx lr ... 08007458 : * @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { 8007458: b580 push {r7, lr} 800745a: b086 sub sp, #24 800745c: af00 add r7, sp, #0 800745e: 60f8 str r0, [r7, #12] 8007460: 60b9 str r1, [r7, #8] 8007462: 607a str r2, [r7, #4] HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; 8007464: 2300 movs r3, #0 8007466: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); /* Process locked */ __HAL_LOCK(hadc); 8007468: 68fb ldr r3, [r7, #12] 800746a: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 800746e: 2b01 cmp r3, #1 8007470: d101 bne.n 8007476 8007472: 2302 movs r3, #2 8007474: e04c b.n 8007510 8007476: 68fb ldr r3, [r7, #12] 8007478: 2201 movs r2, #1 800747a: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Calibration prerequisite: ADC must be disabled. */ /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); 800747e: 68f8 ldr r0, [r7, #12] 8007480: f7ff fd90 bl 8006fa4 8007484: 4603 mov r3, r0 8007486: 75fb strb r3, [r7, #23] /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) 8007488: 7dfb ldrb r3, [r7, #23] 800748a: 2b00 cmp r3, #0 800748c: d135 bne.n 80074fa { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 800748e: 68fb ldr r3, [r7, #12] 8007490: 6d5a ldr r2, [r3, #84] @ 0x54 8007492: 4b21 ldr r3, [pc, #132] @ (8007518 ) 8007494: 4013 ands r3, r2 8007496: f043 0202 orr.w r2, r3, #2 800749a: 68fb ldr r3, [r7, #12] 800749c: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance, CalibrationMode, SingleDiff); 800749e: 68fb ldr r3, [r7, #12] 80074a0: 681b ldr r3, [r3, #0] 80074a2: 687a ldr r2, [r7, #4] 80074a4: 68b9 ldr r1, [r7, #8] 80074a6: 4618 mov r0, r3 80074a8: f7ff ff90 bl 80073cc /* Wait for calibration completion */ while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 80074ac: e014 b.n 80074d8 { wait_loop_index++; 80074ae: 693b ldr r3, [r7, #16] 80074b0: 3301 adds r3, #1 80074b2: 613b str r3, [r7, #16] if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) 80074b4: 693b ldr r3, [r7, #16] 80074b6: 4a19 ldr r2, [pc, #100] @ (800751c ) 80074b8: 4293 cmp r3, r2 80074ba: d30d bcc.n 80074d8 { /* Update ADC state machine to error */ ADC_STATE_CLR_SET(hadc->State, 80074bc: 68fb ldr r3, [r7, #12] 80074be: 6d5b ldr r3, [r3, #84] @ 0x54 80074c0: f023 0312 bic.w r3, r3, #18 80074c4: f043 0210 orr.w r2, r3, #16 80074c8: 68fb ldr r3, [r7, #12] 80074ca: 655a str r2, [r3, #84] @ 0x54 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); /* Process unlocked */ __HAL_UNLOCK(hadc); 80074cc: 68fb ldr r3, [r7, #12] 80074ce: 2200 movs r2, #0 80074d0: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 80074d4: 2301 movs r3, #1 80074d6: e01b b.n 8007510 while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) 80074d8: 68fb ldr r3, [r7, #12] 80074da: 681b ldr r3, [r3, #0] 80074dc: 4618 mov r0, r3 80074de: f7ff ff93 bl 8007408 80074e2: 4603 mov r3, r0 80074e4: 2b00 cmp r3, #0 80074e6: d1e2 bne.n 80074ae } } /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, 80074e8: 68fb ldr r3, [r7, #12] 80074ea: 6d5b ldr r3, [r3, #84] @ 0x54 80074ec: f023 0303 bic.w r3, r3, #3 80074f0: f043 0201 orr.w r2, r3, #1 80074f4: 68fb ldr r3, [r7, #12] 80074f6: 655a str r2, [r3, #84] @ 0x54 80074f8: e005 b.n 8007506 HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); } else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 80074fa: 68fb ldr r3, [r7, #12] 80074fc: 6d5b ldr r3, [r3, #84] @ 0x54 80074fe: f043 0210 orr.w r2, r3, #16 8007502: 68fb ldr r3, [r7, #12] 8007504: 655a str r2, [r3, #84] @ 0x54 /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } /* Process unlocked */ __HAL_UNLOCK(hadc); 8007506: 68fb ldr r3, [r7, #12] 8007508: 2200 movs r2, #0 800750a: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 800750e: 7dfb ldrb r3, [r7, #23] } 8007510: 4618 mov r0, r3 8007512: 3718 adds r7, #24 8007514: 46bd mov sp, r7 8007516: bd80 pop {r7, pc} 8007518: ffffeefd .word 0xffffeefd 800751c: 25c3f800 .word 0x25c3f800 08007520 : * @param hadc Master ADC handle * @param multimode Structure of ADC multimode configuration * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { 8007520: b590 push {r4, r7, lr} 8007522: b09f sub sp, #124 @ 0x7c 8007524: af00 add r7, sp, #0 8007526: 6078 str r0, [r7, #4] 8007528: 6039 str r1, [r7, #0] HAL_StatusTypeDef tmp_hal_status = HAL_OK; 800752a: 2300 movs r3, #0 800752c: f887 3077 strb.w r3, [r7, #119] @ 0x77 assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } /* Process locked */ __HAL_LOCK(hadc); 8007530: 687b ldr r3, [r7, #4] 8007532: f893 3050 ldrb.w r3, [r3, #80] @ 0x50 8007536: 2b01 cmp r3, #1 8007538: d101 bne.n 800753e 800753a: 2302 movs r3, #2 800753c: e0be b.n 80076bc 800753e: 687b ldr r3, [r7, #4] 8007540: 2201 movs r2, #1 8007542: f883 2050 strb.w r2, [r3, #80] @ 0x50 tmphadcSlave.State = HAL_ADC_STATE_RESET; 8007546: 2300 movs r3, #0 8007548: 65fb str r3, [r7, #92] @ 0x5c tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; 800754a: 2300 movs r3, #0 800754c: 663b str r3, [r7, #96] @ 0x60 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 800754e: 687b ldr r3, [r7, #4] 8007550: 681b ldr r3, [r3, #0] 8007552: 4a5c ldr r2, [pc, #368] @ (80076c4 ) 8007554: 4293 cmp r3, r2 8007556: d102 bne.n 800755e 8007558: 4b5b ldr r3, [pc, #364] @ (80076c8 ) 800755a: 60bb str r3, [r7, #8] 800755c: e001 b.n 8007562 800755e: 2300 movs r3, #0 8007560: 60bb str r3, [r7, #8] if (tmphadcSlave.Instance == NULL) 8007562: 68bb ldr r3, [r7, #8] 8007564: 2b00 cmp r3, #0 8007566: d10b bne.n 8007580 { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 8007568: 687b ldr r3, [r7, #4] 800756a: 6d5b ldr r3, [r3, #84] @ 0x54 800756c: f043 0220 orr.w r2, r3, #32 8007570: 687b ldr r3, [r7, #4] 8007572: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hadc); 8007574: 687b ldr r3, [r7, #4] 8007576: 2200 movs r2, #0 8007578: f883 2050 strb.w r2, [r3, #80] @ 0x50 return HAL_ERROR; 800757c: 2301 movs r3, #1 800757e: e09d b.n 80076bc /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); 8007580: 68bb ldr r3, [r7, #8] 8007582: 4618 mov r0, r3 8007584: f7ff ff54 bl 8007430 8007588: 6738 str r0, [r7, #112] @ 0x70 if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) 800758a: 687b ldr r3, [r7, #4] 800758c: 681b ldr r3, [r3, #0] 800758e: 4618 mov r0, r3 8007590: f7ff ff4e bl 8007430 8007594: 4603 mov r3, r0 8007596: 2b00 cmp r3, #0 8007598: d17f bne.n 800769a && (tmphadcSlave_conversion_on_going == 0UL)) 800759a: 6f3b ldr r3, [r7, #112] @ 0x70 800759c: 2b00 cmp r3, #0 800759e: d17c bne.n 800769a { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); 80075a0: 687b ldr r3, [r7, #4] 80075a2: 681b ldr r3, [r3, #0] 80075a4: 4a47 ldr r2, [pc, #284] @ (80076c4 ) 80075a6: 4293 cmp r3, r2 80075a8: d004 beq.n 80075b4 80075aa: 687b ldr r3, [r7, #4] 80075ac: 681b ldr r3, [r3, #0] 80075ae: 4a46 ldr r2, [pc, #280] @ (80076c8 ) 80075b0: 4293 cmp r3, r2 80075b2: d101 bne.n 80075b8 80075b4: 4b45 ldr r3, [pc, #276] @ (80076cc ) 80075b6: e000 b.n 80075ba 80075b8: 4b45 ldr r3, [pc, #276] @ (80076d0 ) 80075ba: 66fb str r3, [r7, #108] @ 0x6c /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ if (multimode->Mode != ADC_MODE_INDEPENDENT) 80075bc: 683b ldr r3, [r7, #0] 80075be: 681b ldr r3, [r3, #0] 80075c0: 2b00 cmp r3, #0 80075c2: d039 beq.n 8007638 { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); 80075c4: 6efb ldr r3, [r7, #108] @ 0x6c 80075c6: 689b ldr r3, [r3, #8] 80075c8: f423 4240 bic.w r2, r3, #49152 @ 0xc000 80075cc: 683b ldr r3, [r7, #0] 80075ce: 685b ldr r3, [r3, #4] 80075d0: 431a orrs r2, r3 80075d2: 6efb ldr r3, [r7, #108] @ 0x6c 80075d4: 609a str r2, [r3, #8] /* from 1 to 8 clock cycles for 12 bits */ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 80075d6: 687b ldr r3, [r7, #4] 80075d8: 681b ldr r3, [r3, #0] 80075da: 4a3a ldr r2, [pc, #232] @ (80076c4 ) 80075dc: 4293 cmp r3, r2 80075de: d004 beq.n 80075ea 80075e0: 687b ldr r3, [r7, #4] 80075e2: 681b ldr r3, [r3, #0] 80075e4: 4a38 ldr r2, [pc, #224] @ (80076c8 ) 80075e6: 4293 cmp r3, r2 80075e8: d10e bne.n 8007608 80075ea: 4836 ldr r0, [pc, #216] @ (80076c4 ) 80075ec: f7ff feda bl 80073a4 80075f0: 4604 mov r4, r0 80075f2: 4835 ldr r0, [pc, #212] @ (80076c8 ) 80075f4: f7ff fed6 bl 80073a4 80075f8: 4603 mov r3, r0 80075fa: 4323 orrs r3, r4 80075fc: 2b00 cmp r3, #0 80075fe: bf0c ite eq 8007600: 2301 moveq r3, #1 8007602: 2300 movne r3, #0 8007604: b2db uxtb r3, r3 8007606: e008 b.n 800761a 8007608: 4832 ldr r0, [pc, #200] @ (80076d4 ) 800760a: f7ff fecb bl 80073a4 800760e: 4603 mov r3, r0 8007610: 2b00 cmp r3, #0 8007612: bf0c ite eq 8007614: 2301 moveq r3, #1 8007616: 2300 movne r3, #0 8007618: b2db uxtb r3, r3 800761a: 2b00 cmp r3, #0 800761c: d047 beq.n 80076ae { MODIFY_REG(tmpADC_Common->CCR, 800761e: 6efb ldr r3, [r7, #108] @ 0x6c 8007620: 689a ldr r2, [r3, #8] 8007622: 4b2d ldr r3, [pc, #180] @ (80076d8 ) 8007624: 4013 ands r3, r2 8007626: 683a ldr r2, [r7, #0] 8007628: 6811 ldr r1, [r2, #0] 800762a: 683a ldr r2, [r7, #0] 800762c: 6892 ldr r2, [r2, #8] 800762e: 430a orrs r2, r1 8007630: 431a orrs r2, r3 8007632: 6efb ldr r3, [r7, #108] @ 0x6c 8007634: 609a str r2, [r3, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007636: e03a b.n 80076ae ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); 8007638: 6efb ldr r3, [r7, #108] @ 0x6c 800763a: 689b ldr r3, [r3, #8] 800763c: f423 4240 bic.w r2, r3, #49152 @ 0xc000 8007640: 6efb ldr r3, [r7, #108] @ 0x6c 8007642: 609a str r2, [r3, #8] /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) 8007644: 687b ldr r3, [r7, #4] 8007646: 681b ldr r3, [r3, #0] 8007648: 4a1e ldr r2, [pc, #120] @ (80076c4 ) 800764a: 4293 cmp r3, r2 800764c: d004 beq.n 8007658 800764e: 687b ldr r3, [r7, #4] 8007650: 681b ldr r3, [r3, #0] 8007652: 4a1d ldr r2, [pc, #116] @ (80076c8 ) 8007654: 4293 cmp r3, r2 8007656: d10e bne.n 8007676 8007658: 481a ldr r0, [pc, #104] @ (80076c4 ) 800765a: f7ff fea3 bl 80073a4 800765e: 4604 mov r4, r0 8007660: 4819 ldr r0, [pc, #100] @ (80076c8 ) 8007662: f7ff fe9f bl 80073a4 8007666: 4603 mov r3, r0 8007668: 4323 orrs r3, r4 800766a: 2b00 cmp r3, #0 800766c: bf0c ite eq 800766e: 2301 moveq r3, #1 8007670: 2300 movne r3, #0 8007672: b2db uxtb r3, r3 8007674: e008 b.n 8007688 8007676: 4817 ldr r0, [pc, #92] @ (80076d4 ) 8007678: f7ff fe94 bl 80073a4 800767c: 4603 mov r3, r0 800767e: 2b00 cmp r3, #0 8007680: bf0c ite eq 8007682: 2301 moveq r3, #1 8007684: 2300 movne r3, #0 8007686: b2db uxtb r3, r3 8007688: 2b00 cmp r3, #0 800768a: d010 beq.n 80076ae { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY); 800768c: 6efb ldr r3, [r7, #108] @ 0x6c 800768e: 689a ldr r2, [r3, #8] 8007690: 4b11 ldr r3, [pc, #68] @ (80076d8 ) 8007692: 4013 ands r3, r2 8007694: 6efa ldr r2, [r7, #108] @ 0x6c 8007696: 6093 str r3, [r2, #8] if (multimode->Mode != ADC_MODE_INDEPENDENT) 8007698: e009 b.n 80076ae /* If one of the ADC sharing the same common group is enabled, no update */ /* could be done on neither of the multimode structure parameters. */ else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 800769a: 687b ldr r3, [r7, #4] 800769c: 6d5b ldr r3, [r3, #84] @ 0x54 800769e: f043 0220 orr.w r2, r3, #32 80076a2: 687b ldr r3, [r7, #4] 80076a4: 655a str r2, [r3, #84] @ 0x54 tmp_hal_status = HAL_ERROR; 80076a6: 2301 movs r3, #1 80076a8: f887 3077 strb.w r3, [r7, #119] @ 0x77 80076ac: e000 b.n 80076b0 if (multimode->Mode != ADC_MODE_INDEPENDENT) 80076ae: bf00 nop } /* Process unlocked */ __HAL_UNLOCK(hadc); 80076b0: 687b ldr r3, [r7, #4] 80076b2: 2200 movs r2, #0 80076b4: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Return function status */ return tmp_hal_status; 80076b8: f897 3077 ldrb.w r3, [r7, #119] @ 0x77 } 80076bc: 4618 mov r0, r3 80076be: 377c adds r7, #124 @ 0x7c 80076c0: 46bd mov sp, r7 80076c2: bd90 pop {r4, r7, pc} 80076c4: 40022000 .word 0x40022000 80076c8: 40022100 .word 0x40022100 80076cc: 40022300 .word 0x40022300 80076d0: 58026300 .word 0x58026300 80076d4: 58026000 .word 0x58026000 80076d8: fffff0e0 .word 0xfffff0e0 080076dc : * To unlock the configuration, perform a system reset. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) { 80076dc: b580 push {r7, lr} 80076de: b088 sub sp, #32 80076e0: af00 add r7, sp, #0 80076e2: 6078 str r0, [r7, #4] uint32_t tmp_csr ; uint32_t exti_line ; uint32_t comp_voltage_scaler_initialized; /* Value "0" is comparator voltage scaler is not initialized */ __IO uint32_t wait_loop_index = 0UL; 80076e4: 2300 movs r3, #0 80076e6: 60fb str r3, [r7, #12] HAL_StatusTypeDef status = HAL_OK; 80076e8: 2300 movs r3, #0 80076ea: 77fb strb r3, [r7, #31] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 80076ec: 687b ldr r3, [r7, #4] 80076ee: 2b00 cmp r3, #0 80076f0: d102 bne.n 80076f8 { status = HAL_ERROR; 80076f2: 2301 movs r3, #1 80076f4: 77fb strb r3, [r7, #31] 80076f6: e10e b.n 8007916 } else if(__HAL_COMP_IS_LOCKED(hcomp)) 80076f8: 687b ldr r3, [r7, #4] 80076fa: 681b ldr r3, [r3, #0] 80076fc: 681b ldr r3, [r3, #0] 80076fe: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007702: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8007706: d102 bne.n 800770e { status = HAL_ERROR; 8007708: 2301 movs r3, #1 800770a: 77fb strb r3, [r7, #31] 800770c: e103 b.n 8007916 assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); if(hcomp->State == HAL_COMP_STATE_RESET) 800770e: 687b ldr r3, [r7, #4] 8007710: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007714: b2db uxtb r3, r3 8007716: 2b00 cmp r3, #0 8007718: d109 bne.n 800772e { /* Allocate lock resource and initialize it */ hcomp->Lock = HAL_UNLOCKED; 800771a: 687b ldr r3, [r7, #4] 800771c: 2200 movs r2, #0 800771e: f883 2024 strb.w r2, [r3, #36] @ 0x24 /* Set COMP error code to none */ COMP_CLEAR_ERRORCODE(hcomp); 8007722: 687b ldr r3, [r7, #4] 8007724: 2200 movs r2, #0 8007726: 629a str r2, [r3, #40] @ 0x28 /* Init the low level hardware */ hcomp->MspInitCallback(hcomp); #else /* Init the low level hardware */ HAL_COMP_MspInit(hcomp); 8007728: 6878 ldr r0, [r7, #4] 800772a: f7fc fca9 bl 8004080 #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ } /* Memorize voltage scaler state before initialization */ comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN); 800772e: 687b ldr r3, [r7, #4] 8007730: 681b ldr r3, [r3, #0] 8007732: 681b ldr r3, [r3, #0] 8007734: f003 0304 and.w r3, r3, #4 8007738: 61bb str r3, [r7, #24] /* Set BLANKING bits according to hcomp->Init.BlankingSrce value */ /* Set HYST bits according to hcomp->Init.Hysteresis value */ /* Set POLARITY bit according to hcomp->Init.OutputPol value */ /* Set POWERMODE bits according to hcomp->Init.Mode value */ tmp_csr = (hcomp->Init.InvertingInput | \ 800773a: 687b ldr r3, [r7, #4] 800773c: 691a ldr r2, [r3, #16] hcomp->Init.NonInvertingInput | \ 800773e: 687b ldr r3, [r7, #4] 8007740: 68db ldr r3, [r3, #12] tmp_csr = (hcomp->Init.InvertingInput | \ 8007742: 431a orrs r2, r3 hcomp->Init.BlankingSrce | \ 8007744: 687b ldr r3, [r7, #4] 8007746: 69db ldr r3, [r3, #28] hcomp->Init.NonInvertingInput | \ 8007748: 431a orrs r2, r3 hcomp->Init.Hysteresis | \ 800774a: 687b ldr r3, [r7, #4] 800774c: 695b ldr r3, [r3, #20] hcomp->Init.BlankingSrce | \ 800774e: 431a orrs r2, r3 hcomp->Init.OutputPol | \ 8007750: 687b ldr r3, [r7, #4] 8007752: 699b ldr r3, [r3, #24] hcomp->Init.Hysteresis | \ 8007754: 431a orrs r2, r3 hcomp->Init.Mode ); 8007756: 687b ldr r3, [r7, #4] 8007758: 689b ldr r3, [r3, #8] tmp_csr = (hcomp->Init.InvertingInput | \ 800775a: 4313 orrs r3, r2 800775c: 617b str r3, [r7, #20] COMP_CFGRx_INP2SEL | COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST | COMP_CFGRx_BLANKING | COMP_CFGRx_BRGEN | COMP_CFGRx_SCALEN, tmp_csr ); #else MODIFY_REG(hcomp->Instance->CFGR, 800775e: 687b ldr r3, [r7, #4] 8007760: 681b ldr r3, [r3, #0] 8007762: 681a ldr r2, [r3, #0] 8007764: 4b6e ldr r3, [pc, #440] @ (8007920 ) 8007766: 4013 ands r3, r2 8007768: 687a ldr r2, [r7, #4] 800776a: 6812 ldr r2, [r2, #0] 800776c: 6979 ldr r1, [r7, #20] 800776e: 430b orrs r3, r1 8007770: 6013 str r3, [r2, #0] #endif /* Set window mode */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* instances. Therefore, this function can update another COMP */ /* instance that the one currently selected. */ if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) 8007772: 687b ldr r3, [r7, #4] 8007774: 685b ldr r3, [r3, #4] 8007776: 2b10 cmp r3, #16 8007778: d108 bne.n 800778c { SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 800777a: 687b ldr r3, [r7, #4] 800777c: 681b ldr r3, [r3, #0] 800777e: 681a ldr r2, [r3, #0] 8007780: 687b ldr r3, [r7, #4] 8007782: 681b ldr r3, [r3, #0] 8007784: f042 0210 orr.w r2, r2, #16 8007788: 601a str r2, [r3, #0] 800778a: e007 b.n 800779c } else { CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_WINMODE); 800778c: 687b ldr r3, [r7, #4] 800778e: 681b ldr r3, [r3, #0] 8007790: 681a ldr r2, [r3, #0] 8007792: 687b ldr r3, [r7, #4] 8007794: 681b ldr r3, [r3, #0] 8007796: f022 0210 bic.w r2, r2, #16 800779a: 601a str r2, [r3, #0] } /* Delay for COMP scaler bridge voltage stabilization */ /* Apply the delay if voltage scaler bridge is enabled for the first time */ if ((READ_BIT(hcomp->Instance->CFGR, COMP_CFGRx_SCALEN) != 0UL) && 800779c: 687b ldr r3, [r7, #4] 800779e: 681b ldr r3, [r3, #0] 80077a0: 681b ldr r3, [r3, #0] 80077a2: f003 0304 and.w r3, r3, #4 80077a6: 2b00 cmp r3, #0 80077a8: d016 beq.n 80077d8 80077aa: 69bb ldr r3, [r7, #24] 80077ac: 2b00 cmp r3, #0 80077ae: d013 beq.n 80077d8 { /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles.*/ wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 80077b0: 4b5c ldr r3, [pc, #368] @ (8007924 ) 80077b2: 681b ldr r3, [r3, #0] 80077b4: 099b lsrs r3, r3, #6 80077b6: 4a5c ldr r2, [pc, #368] @ (8007928 ) 80077b8: fba2 2303 umull r2, r3, r2, r3 80077bc: 099b lsrs r3, r3, #6 80077be: 1c5a adds r2, r3, #1 80077c0: 4613 mov r3, r2 80077c2: 009b lsls r3, r3, #2 80077c4: 4413 add r3, r2 80077c6: 009b lsls r3, r3, #2 80077c8: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 80077ca: e002 b.n 80077d2 { wait_loop_index --; 80077cc: 68fb ldr r3, [r7, #12] 80077ce: 3b01 subs r3, #1 80077d0: 60fb str r3, [r7, #12] while(wait_loop_index != 0UL) 80077d2: 68fb ldr r3, [r7, #12] 80077d4: 2b00 cmp r3, #0 80077d6: d1f9 bne.n 80077cc } } /* Get the EXTI line corresponding to the selected COMP instance */ exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); 80077d8: 687b ldr r3, [r7, #4] 80077da: 681b ldr r3, [r3, #0] 80077dc: 4a53 ldr r2, [pc, #332] @ (800792c ) 80077de: 4293 cmp r3, r2 80077e0: d102 bne.n 80077e8 80077e2: f44f 1380 mov.w r3, #1048576 @ 0x100000 80077e6: e001 b.n 80077ec 80077e8: f44f 1300 mov.w r3, #2097152 @ 0x200000 80077ec: 613b str r3, [r7, #16] /* Manage EXTI settings */ if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) 80077ee: 687b ldr r3, [r7, #4] 80077f0: 6a1b ldr r3, [r3, #32] 80077f2: f003 0303 and.w r3, r3, #3 80077f6: 2b00 cmp r3, #0 80077f8: d06d beq.n 80078d6 { /* Configure EXTI rising edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) 80077fa: 687b ldr r3, [r7, #4] 80077fc: 6a1b ldr r3, [r3, #32] 80077fe: f003 0310 and.w r3, r3, #16 8007802: 2b00 cmp r3, #0 8007804: d008 beq.n 8007818 { SET_BIT(EXTI->RTSR1, exti_line); 8007806: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800780a: 681a ldr r2, [r3, #0] 800780c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007810: 693b ldr r3, [r7, #16] 8007812: 4313 orrs r3, r2 8007814: 600b str r3, [r1, #0] 8007816: e008 b.n 800782a } else { CLEAR_BIT(EXTI->RTSR1, exti_line); 8007818: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800781c: 681a ldr r2, [r3, #0] 800781e: 693b ldr r3, [r7, #16] 8007820: 43db mvns r3, r3 8007822: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007826: 4013 ands r3, r2 8007828: 600b str r3, [r1, #0] } /* Configure EXTI falling edge */ if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) 800782a: 687b ldr r3, [r7, #4] 800782c: 6a1b ldr r3, [r3, #32] 800782e: f003 0320 and.w r3, r3, #32 8007832: 2b00 cmp r3, #0 8007834: d008 beq.n 8007848 { SET_BIT(EXTI->FTSR1, exti_line); 8007836: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800783a: 685a ldr r2, [r3, #4] 800783c: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007840: 693b ldr r3, [r7, #16] 8007842: 4313 orrs r3, r2 8007844: 604b str r3, [r1, #4] 8007846: e008 b.n 800785a } else { CLEAR_BIT(EXTI->FTSR1, exti_line); 8007848: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800784c: 685a ldr r2, [r3, #4] 800784e: 693b ldr r3, [r7, #16] 8007850: 43db mvns r3, r3 8007852: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007856: 4013 ands r3, r2 8007858: 604b str r3, [r1, #4] } #if !defined (CORE_CM4) /* Clear COMP EXTI pending bit (if any) */ WRITE_REG(EXTI->PR1, exti_line); 800785a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800785e: 693b ldr r3, [r7, #16] 8007860: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure EXTI event mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) 8007864: 687b ldr r3, [r7, #4] 8007866: 6a1b ldr r3, [r3, #32] 8007868: f003 0302 and.w r3, r3, #2 800786c: 2b00 cmp r3, #0 800786e: d00a beq.n 8007886 { SET_BIT(EXTI->EMR1, exti_line); 8007870: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 8007874: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 8007878: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 800787c: 693b ldr r3, [r7, #16] 800787e: 4313 orrs r3, r2 8007880: f8c1 3084 str.w r3, [r1, #132] @ 0x84 8007884: e00a b.n 800789c } else { CLEAR_BIT(EXTI->EMR1, exti_line); 8007886: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800788a: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 800788e: 693b ldr r3, [r7, #16] 8007890: 43db mvns r3, r3 8007892: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 8007896: 4013 ands r3, r2 8007898: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /* Configure EXTI interrupt mode */ if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) 800789c: 687b ldr r3, [r7, #4] 800789e: 6a1b ldr r3, [r3, #32] 80078a0: f003 0301 and.w r3, r3, #1 80078a4: 2b00 cmp r3, #0 80078a6: d00a beq.n 80078be { SET_BIT(EXTI->IMR1, exti_line); 80078a8: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078ac: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 80078b0: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078b4: 693b ldr r3, [r7, #16] 80078b6: 4313 orrs r3, r2 80078b8: f8c1 3080 str.w r3, [r1, #128] @ 0x80 80078bc: e021 b.n 8007902 } else { CLEAR_BIT(EXTI->IMR1, exti_line); 80078be: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078c2: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 80078c6: 693b ldr r3, [r7, #16] 80078c8: 43db mvns r3, r3 80078ca: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078ce: 4013 ands r3, r2 80078d0: f8c1 3080 str.w r3, [r1, #128] @ 0x80 80078d4: e015 b.n 8007902 } } else { /* Disable EXTI event mode */ CLEAR_BIT(EXTI->EMR1, exti_line); 80078d6: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078da: f8d3 2084 ldr.w r2, [r3, #132] @ 0x84 80078de: 693b ldr r3, [r7, #16] 80078e0: 43db mvns r3, r3 80078e2: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078e6: 4013 ands r3, r2 80078e8: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* Disable EXTI interrupt mode */ CLEAR_BIT(EXTI->IMR1, exti_line); 80078ec: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 80078f0: f8d3 2080 ldr.w r2, [r3, #128] @ 0x80 80078f4: 693b ldr r3, [r7, #16] 80078f6: 43db mvns r3, r3 80078f8: f04f 41b0 mov.w r1, #1476395008 @ 0x58000000 80078fc: 4013 ands r3, r2 80078fe: f8c1 3080 str.w r3, [r1, #128] @ 0x80 } #endif /* Set HAL COMP handle state */ /* Note: Transition from state reset to state ready, */ /* otherwise (coming from state ready or busy) no state update. */ if (hcomp->State == HAL_COMP_STATE_RESET) 8007902: 687b ldr r3, [r7, #4] 8007904: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007908: b2db uxtb r3, r3 800790a: 2b00 cmp r3, #0 800790c: d103 bne.n 8007916 { hcomp->State = HAL_COMP_STATE_READY; 800790e: 687b ldr r3, [r7, #4] 8007910: 2201 movs r2, #1 8007912: f883 2025 strb.w r2, [r3, #37] @ 0x25 } } return status; 8007916: 7ffb ldrb r3, [r7, #31] } 8007918: 4618 mov r0, r3 800791a: 3720 adds r7, #32 800791c: 46bd mov sp, r7 800791e: bd80 pop {r7, pc} 8007920: f0e8cce1 .word 0xf0e8cce1 8007924: 24000034 .word 0x24000034 8007928: 053e2d63 .word 0x053e2d63 800792c: 5800380c .word 0x5800380c 08007930 : * @brief Start the comparator. * @param hcomp COMP handle * @retval HAL status */ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) { 8007930: b480 push {r7} 8007932: b085 sub sp, #20 8007934: af00 add r7, sp, #0 8007936: 6078 str r0, [r7, #4] __IO uint32_t wait_loop_index = 0UL; 8007938: 2300 movs r3, #0 800793a: 60bb str r3, [r7, #8] HAL_StatusTypeDef status = HAL_OK; 800793c: 2300 movs r3, #0 800793e: 73fb strb r3, [r7, #15] /* Check the COMP handle allocation and lock status */ if(hcomp == NULL) 8007940: 687b ldr r3, [r7, #4] 8007942: 2b00 cmp r3, #0 8007944: d102 bne.n 800794c { status = HAL_ERROR; 8007946: 2301 movs r3, #1 8007948: 73fb strb r3, [r7, #15] 800794a: e030 b.n 80079ae } else if(__HAL_COMP_IS_LOCKED(hcomp)) 800794c: 687b ldr r3, [r7, #4] 800794e: 681b ldr r3, [r3, #0] 8007950: 681b ldr r3, [r3, #0] 8007952: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 8007956: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 800795a: d102 bne.n 8007962 { status = HAL_ERROR; 800795c: 2301 movs r3, #1 800795e: 73fb strb r3, [r7, #15] 8007960: e025 b.n 80079ae else { /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if(hcomp->State == HAL_COMP_STATE_READY) 8007962: 687b ldr r3, [r7, #4] 8007964: f893 3025 ldrb.w r3, [r3, #37] @ 0x25 8007968: b2db uxtb r3, r3 800796a: 2b01 cmp r3, #1 800796c: d11d bne.n 80079aa { /* Enable the selected comparator */ SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_EN); 800796e: 687b ldr r3, [r7, #4] 8007970: 681b ldr r3, [r3, #0] 8007972: 681a ldr r2, [r3, #0] 8007974: 687b ldr r3, [r7, #4] 8007976: 681b ldr r3, [r3, #0] 8007978: f042 0201 orr.w r2, r2, #1 800797c: 601a str r2, [r3, #0] /* Set HAL COMP handle state */ hcomp->State = HAL_COMP_STATE_BUSY; 800797e: 687b ldr r3, [r7, #4] 8007980: 2202 movs r2, #2 8007982: f883 2025 strb.w r2, [r3, #37] @ 0x25 /* Delay for COMP startup time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); 8007986: 4b0d ldr r3, [pc, #52] @ (80079bc ) 8007988: 681b ldr r3, [r3, #0] 800798a: 099b lsrs r3, r3, #6 800798c: 4a0c ldr r2, [pc, #48] @ (80079c0 ) 800798e: fba2 2303 umull r2, r3, r2, r3 8007992: 099b lsrs r3, r3, #6 8007994: 3301 adds r3, #1 8007996: 00db lsls r3, r3, #3 8007998: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 800799a: e002 b.n 80079a2 { wait_loop_index--; 800799c: 68bb ldr r3, [r7, #8] 800799e: 3b01 subs r3, #1 80079a0: 60bb str r3, [r7, #8] while(wait_loop_index != 0UL) 80079a2: 68bb ldr r3, [r7, #8] 80079a4: 2b00 cmp r3, #0 80079a6: d1f9 bne.n 800799c 80079a8: e001 b.n 80079ae } } else { status = HAL_ERROR; 80079aa: 2301 movs r3, #1 80079ac: 73fb strb r3, [r7, #15] } } return status; 80079ae: 7bfb ldrb r3, [r7, #15] } 80079b0: 4618 mov r0, r3 80079b2: 3714 adds r7, #20 80079b4: 46bd mov sp, r7 80079b6: f85d 7b04 ldr.w r7, [sp], #4 80079ba: 4770 bx lr 80079bc: 24000034 .word 0x24000034 80079c0: 053e2d63 .word 0x053e2d63 080079c4 : * @arg @ref COMP_OUTPUT_LEVEL_LOW * @arg @ref COMP_OUTPUT_LEVEL_HIGH * */ uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) { 80079c4: b480 push {r7} 80079c6: b083 sub sp, #12 80079c8: af00 add r7, sp, #0 80079ca: 6078 str r0, [r7, #4] /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); if (hcomp->Instance == COMP1) 80079cc: 687b ldr r3, [r7, #4] 80079ce: 681b ldr r3, [r3, #0] 80079d0: 4a09 ldr r2, [pc, #36] @ (80079f8 ) 80079d2: 4293 cmp r3, r2 80079d4: d104 bne.n 80079e0 { return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL)); 80079d6: 4b09 ldr r3, [pc, #36] @ (80079fc ) 80079d8: 681b ldr r3, [r3, #0] 80079da: f003 0301 and.w r3, r3, #1 80079de: e004 b.n 80079ea } else { return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1UL); 80079e0: 4b06 ldr r3, [pc, #24] @ (80079fc ) 80079e2: 681b ldr r3, [r3, #0] 80079e4: 085b lsrs r3, r3, #1 80079e6: f003 0301 and.w r3, r3, #1 } } 80079ea: 4618 mov r0, r3 80079ec: 370c adds r7, #12 80079ee: 46bd mov sp, r7 80079f0: f85d 7b04 ldr.w r7, [sp], #4 80079f4: 4770 bx lr 80079f6: bf00 nop 80079f8: 5800380c .word 0x5800380c 80079fc: 58003800 .word 0x58003800 08007a00 <__NVIC_SetPriorityGrouping>: { 8007a00: b480 push {r7} 8007a02: b085 sub sp, #20 8007a04: af00 add r7, sp, #0 8007a06: 6078 str r0, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007a08: 687b ldr r3, [r7, #4] 8007a0a: f003 0307 and.w r3, r3, #7 8007a0e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8007a10: 4b0b ldr r3, [pc, #44] @ (8007a40 <__NVIC_SetPriorityGrouping+0x40>) 8007a12: 68db ldr r3, [r3, #12] 8007a14: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8007a16: 68ba ldr r2, [r7, #8] 8007a18: f64f 03ff movw r3, #63743 @ 0xf8ff 8007a1c: 4013 ands r3, r2 8007a1e: 60bb str r3, [r7, #8] (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8007a20: 68fb ldr r3, [r7, #12] 8007a22: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8007a24: 68bb ldr r3, [r7, #8] 8007a26: 431a orrs r2, r3 reg_value = (reg_value | 8007a28: 4b06 ldr r3, [pc, #24] @ (8007a44 <__NVIC_SetPriorityGrouping+0x44>) 8007a2a: 4313 orrs r3, r2 8007a2c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8007a2e: 4a04 ldr r2, [pc, #16] @ (8007a40 <__NVIC_SetPriorityGrouping+0x40>) 8007a30: 68bb ldr r3, [r7, #8] 8007a32: 60d3 str r3, [r2, #12] } 8007a34: bf00 nop 8007a36: 3714 adds r7, #20 8007a38: 46bd mov sp, r7 8007a3a: f85d 7b04 ldr.w r7, [sp], #4 8007a3e: 4770 bx lr 8007a40: e000ed00 .word 0xe000ed00 8007a44: 05fa0000 .word 0x05fa0000 08007a48 <__NVIC_GetPriorityGrouping>: { 8007a48: b480 push {r7} 8007a4a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8007a4c: 4b04 ldr r3, [pc, #16] @ (8007a60 <__NVIC_GetPriorityGrouping+0x18>) 8007a4e: 68db ldr r3, [r3, #12] 8007a50: 0a1b lsrs r3, r3, #8 8007a52: f003 0307 and.w r3, r3, #7 } 8007a56: 4618 mov r0, r3 8007a58: 46bd mov sp, r7 8007a5a: f85d 7b04 ldr.w r7, [sp], #4 8007a5e: 4770 bx lr 8007a60: e000ed00 .word 0xe000ed00 08007a64 <__NVIC_EnableIRQ>: { 8007a64: b480 push {r7} 8007a66: b083 sub sp, #12 8007a68: af00 add r7, sp, #0 8007a6a: 4603 mov r3, r0 8007a6c: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007a6e: f9b7 3006 ldrsh.w r3, [r7, #6] 8007a72: 2b00 cmp r3, #0 8007a74: db0b blt.n 8007a8e <__NVIC_EnableIRQ+0x2a> NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8007a76: 88fb ldrh r3, [r7, #6] 8007a78: f003 021f and.w r2, r3, #31 8007a7c: 4907 ldr r1, [pc, #28] @ (8007a9c <__NVIC_EnableIRQ+0x38>) 8007a7e: f9b7 3006 ldrsh.w r3, [r7, #6] 8007a82: 095b lsrs r3, r3, #5 8007a84: 2001 movs r0, #1 8007a86: fa00 f202 lsl.w r2, r0, r2 8007a8a: f841 2023 str.w r2, [r1, r3, lsl #2] } 8007a8e: bf00 nop 8007a90: 370c adds r7, #12 8007a92: 46bd mov sp, r7 8007a94: f85d 7b04 ldr.w r7, [sp], #4 8007a98: 4770 bx lr 8007a9a: bf00 nop 8007a9c: e000e100 .word 0xe000e100 08007aa0 <__NVIC_SetPriority>: { 8007aa0: b480 push {r7} 8007aa2: b083 sub sp, #12 8007aa4: af00 add r7, sp, #0 8007aa6: 4603 mov r3, r0 8007aa8: 6039 str r1, [r7, #0] 8007aaa: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8007aac: f9b7 3006 ldrsh.w r3, [r7, #6] 8007ab0: 2b00 cmp r3, #0 8007ab2: db0a blt.n 8007aca <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007ab4: 683b ldr r3, [r7, #0] 8007ab6: b2da uxtb r2, r3 8007ab8: 490c ldr r1, [pc, #48] @ (8007aec <__NVIC_SetPriority+0x4c>) 8007aba: f9b7 3006 ldrsh.w r3, [r7, #6] 8007abe: 0112 lsls r2, r2, #4 8007ac0: b2d2 uxtb r2, r2 8007ac2: 440b add r3, r1 8007ac4: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8007ac8: e00a b.n 8007ae0 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8007aca: 683b ldr r3, [r7, #0] 8007acc: b2da uxtb r2, r3 8007ace: 4908 ldr r1, [pc, #32] @ (8007af0 <__NVIC_SetPriority+0x50>) 8007ad0: 88fb ldrh r3, [r7, #6] 8007ad2: f003 030f and.w r3, r3, #15 8007ad6: 3b04 subs r3, #4 8007ad8: 0112 lsls r2, r2, #4 8007ada: b2d2 uxtb r2, r2 8007adc: 440b add r3, r1 8007ade: 761a strb r2, [r3, #24] } 8007ae0: bf00 nop 8007ae2: 370c adds r7, #12 8007ae4: 46bd mov sp, r7 8007ae6: f85d 7b04 ldr.w r7, [sp], #4 8007aea: 4770 bx lr 8007aec: e000e100 .word 0xe000e100 8007af0: e000ed00 .word 0xe000ed00 08007af4 : { 8007af4: b480 push {r7} 8007af6: b089 sub sp, #36 @ 0x24 8007af8: af00 add r7, sp, #0 8007afa: 60f8 str r0, [r7, #12] 8007afc: 60b9 str r1, [r7, #8] 8007afe: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8007b00: 68fb ldr r3, [r7, #12] 8007b02: f003 0307 and.w r3, r3, #7 8007b06: 61fb str r3, [r7, #28] PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8007b08: 69fb ldr r3, [r7, #28] 8007b0a: f1c3 0307 rsb r3, r3, #7 8007b0e: 2b04 cmp r3, #4 8007b10: bf28 it cs 8007b12: 2304 movcs r3, #4 8007b14: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8007b16: 69fb ldr r3, [r7, #28] 8007b18: 3304 adds r3, #4 8007b1a: 2b06 cmp r3, #6 8007b1c: d902 bls.n 8007b24 8007b1e: 69fb ldr r3, [r7, #28] 8007b20: 3b03 subs r3, #3 8007b22: e000 b.n 8007b26 8007b24: 2300 movs r3, #0 8007b26: 617b str r3, [r7, #20] ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007b28: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007b2c: 69bb ldr r3, [r7, #24] 8007b2e: fa02 f303 lsl.w r3, r2, r3 8007b32: 43da mvns r2, r3 8007b34: 68bb ldr r3, [r7, #8] 8007b36: 401a ands r2, r3 8007b38: 697b ldr r3, [r7, #20] 8007b3a: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8007b3c: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8007b40: 697b ldr r3, [r7, #20] 8007b42: fa01 f303 lsl.w r3, r1, r3 8007b46: 43d9 mvns r1, r3 8007b48: 687b ldr r3, [r7, #4] 8007b4a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8007b4c: 4313 orrs r3, r2 } 8007b4e: 4618 mov r0, r3 8007b50: 3724 adds r7, #36 @ 0x24 8007b52: 46bd mov sp, r7 8007b54: f85d 7b04 ldr.w r7, [sp], #4 8007b58: 4770 bx lr 08007b5a : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8007b5a: b580 push {r7, lr} 8007b5c: b082 sub sp, #8 8007b5e: af00 add r7, sp, #0 8007b60: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8007b62: 6878 ldr r0, [r7, #4] 8007b64: f7ff ff4c bl 8007a00 <__NVIC_SetPriorityGrouping> } 8007b68: bf00 nop 8007b6a: 3708 adds r7, #8 8007b6c: 46bd mov sp, r7 8007b6e: bd80 pop {r7, pc} 08007b70 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8007b70: b580 push {r7, lr} 8007b72: b086 sub sp, #24 8007b74: af00 add r7, sp, #0 8007b76: 4603 mov r3, r0 8007b78: 60b9 str r1, [r7, #8] 8007b7a: 607a str r2, [r7, #4] 8007b7c: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8007b7e: f7ff ff63 bl 8007a48 <__NVIC_GetPriorityGrouping> 8007b82: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8007b84: 687a ldr r2, [r7, #4] 8007b86: 68b9 ldr r1, [r7, #8] 8007b88: 6978 ldr r0, [r7, #20] 8007b8a: f7ff ffb3 bl 8007af4 8007b8e: 4602 mov r2, r0 8007b90: f9b7 300e ldrsh.w r3, [r7, #14] 8007b94: 4611 mov r1, r2 8007b96: 4618 mov r0, r3 8007b98: f7ff ff82 bl 8007aa0 <__NVIC_SetPriority> } 8007b9c: bf00 nop 8007b9e: 3718 adds r7, #24 8007ba0: 46bd mov sp, r7 8007ba2: bd80 pop {r7, pc} 08007ba4 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8007ba4: b580 push {r7, lr} 8007ba6: b082 sub sp, #8 8007ba8: af00 add r7, sp, #0 8007baa: 4603 mov r3, r0 8007bac: 80fb strh r3, [r7, #6] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8007bae: f9b7 3006 ldrsh.w r3, [r7, #6] 8007bb2: 4618 mov r0, r3 8007bb4: f7ff ff56 bl 8007a64 <__NVIC_EnableIRQ> } 8007bb8: bf00 nop 8007bba: 3708 adds r7, #8 8007bbc: 46bd mov sp, r7 8007bbe: bd80 pop {r7, pc} 08007bc0 : /** * @brief Disables the MPU * @retval None */ void HAL_MPU_Disable(void) { 8007bc0: b480 push {r7} 8007bc2: af00 add r7, sp, #0 __ASM volatile ("dmb 0xF":::"memory"); 8007bc4: f3bf 8f5f dmb sy } 8007bc8: bf00 nop /* Make sure outstanding transfers are done */ __DMB(); /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 8007bca: 4b07 ldr r3, [pc, #28] @ (8007be8 ) 8007bcc: 6a5b ldr r3, [r3, #36] @ 0x24 8007bce: 4a06 ldr r2, [pc, #24] @ (8007be8 ) 8007bd0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8007bd4: 6253 str r3, [r2, #36] @ 0x24 /* Disable the MPU and clear the control register*/ MPU->CTRL = 0; 8007bd6: 4b05 ldr r3, [pc, #20] @ (8007bec ) 8007bd8: 2200 movs r2, #0 8007bda: 605a str r2, [r3, #4] } 8007bdc: bf00 nop 8007bde: 46bd mov sp, r7 8007be0: f85d 7b04 ldr.w r7, [sp], #4 8007be4: 4770 bx lr 8007be6: bf00 nop 8007be8: e000ed00 .word 0xe000ed00 8007bec: e000ed90 .word 0xe000ed90 08007bf0 : * @arg MPU_PRIVILEGED_DEFAULT * @arg MPU_HFNMI_PRIVDEF * @retval None */ void HAL_MPU_Enable(uint32_t MPU_Control) { 8007bf0: b480 push {r7} 8007bf2: b083 sub sp, #12 8007bf4: af00 add r7, sp, #0 8007bf6: 6078 str r0, [r7, #4] /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 8007bf8: 4a0b ldr r2, [pc, #44] @ (8007c28 ) 8007bfa: 687b ldr r3, [r7, #4] 8007bfc: f043 0301 orr.w r3, r3, #1 8007c00: 6053 str r3, [r2, #4] /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 8007c02: 4b0a ldr r3, [pc, #40] @ (8007c2c ) 8007c04: 6a5b ldr r3, [r3, #36] @ 0x24 8007c06: 4a09 ldr r2, [pc, #36] @ (8007c2c ) 8007c08: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8007c0c: 6253 str r3, [r2, #36] @ 0x24 __ASM volatile ("dsb 0xF":::"memory"); 8007c0e: f3bf 8f4f dsb sy } 8007c12: bf00 nop __ASM volatile ("isb 0xF":::"memory"); 8007c14: f3bf 8f6f isb sy } 8007c18: bf00 nop /* Ensure MPU setting take effects */ __DSB(); __ISB(); } 8007c1a: bf00 nop 8007c1c: 370c adds r7, #12 8007c1e: 46bd mov sp, r7 8007c20: f85d 7b04 ldr.w r7, [sp], #4 8007c24: 4770 bx lr 8007c26: bf00 nop 8007c28: e000ed90 .word 0xe000ed90 8007c2c: e000ed00 .word 0xe000ed00 08007c30 : * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) { 8007c30: b480 push {r7} 8007c32: b083 sub sp, #12 8007c34: af00 add r7, sp, #0 8007c36: 6078 str r0, [r7, #4] assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; 8007c38: 687b ldr r3, [r7, #4] 8007c3a: 785a ldrb r2, [r3, #1] 8007c3c: 4b1b ldr r3, [pc, #108] @ (8007cac ) 8007c3e: 609a str r2, [r3, #8] /* Disable the Region */ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 8007c40: 4b1a ldr r3, [pc, #104] @ (8007cac ) 8007c42: 691b ldr r3, [r3, #16] 8007c44: 4a19 ldr r2, [pc, #100] @ (8007cac ) 8007c46: f023 0301 bic.w r3, r3, #1 8007c4a: 6113 str r3, [r2, #16] /* Apply configuration */ MPU->RBAR = MPU_Init->BaseAddress; 8007c4c: 4a17 ldr r2, [pc, #92] @ (8007cac ) 8007c4e: 687b ldr r3, [r7, #4] 8007c50: 685b ldr r3, [r3, #4] 8007c52: 60d3 str r3, [r2, #12] MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c54: 687b ldr r3, [r7, #4] 8007c56: 7b1b ldrb r3, [r3, #12] 8007c58: 071a lsls r2, r3, #28 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007c5a: 687b ldr r3, [r7, #4] 8007c5c: 7adb ldrb r3, [r3, #11] 8007c5e: 061b lsls r3, r3, #24 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c60: 431a orrs r2, r3 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007c62: 687b ldr r3, [r7, #4] 8007c64: 7a9b ldrb r3, [r3, #10] 8007c66: 04db lsls r3, r3, #19 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 8007c68: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007c6a: 687b ldr r3, [r7, #4] 8007c6c: 7b5b ldrb r3, [r3, #13] 8007c6e: 049b lsls r3, r3, #18 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 8007c70: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007c72: 687b ldr r3, [r7, #4] 8007c74: 7b9b ldrb r3, [r3, #14] 8007c76: 045b lsls r3, r3, #17 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 8007c78: 431a orrs r2, r3 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007c7a: 687b ldr r3, [r7, #4] 8007c7c: 7bdb ldrb r3, [r3, #15] 8007c7e: 041b lsls r3, r3, #16 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 8007c80: 431a orrs r2, r3 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007c82: 687b ldr r3, [r7, #4] 8007c84: 7a5b ldrb r3, [r3, #9] 8007c86: 021b lsls r3, r3, #8 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 8007c88: 431a orrs r2, r3 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007c8a: 687b ldr r3, [r7, #4] 8007c8c: 7a1b ldrb r3, [r3, #8] 8007c8e: 005b lsls r3, r3, #1 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 8007c90: 4313 orrs r3, r2 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 8007c92: 687a ldr r2, [r7, #4] 8007c94: 7812 ldrb r2, [r2, #0] 8007c96: 4611 mov r1, r2 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c98: 4a04 ldr r2, [pc, #16] @ (8007cac ) ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 8007c9a: 430b orrs r3, r1 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 8007c9c: 6113 str r3, [r2, #16] } 8007c9e: bf00 nop 8007ca0: 370c adds r7, #12 8007ca2: 46bd mov sp, r7 8007ca4: f85d 7b04 ldr.w r7, [sp], #4 8007ca8: 4770 bx lr 8007caa: bf00 nop 8007cac: e000ed90 .word 0xe000ed90 08007cb0 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 8007cb0: b580 push {r7, lr} 8007cb2: b082 sub sp, #8 8007cb4: af00 add r7, sp, #0 8007cb6: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8007cb8: 687b ldr r3, [r7, #4] 8007cba: 2b00 cmp r3, #0 8007cbc: d101 bne.n 8007cc2 { return HAL_ERROR; 8007cbe: 2301 movs r3, #1 8007cc0: e054 b.n 8007d6c } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 8007cc2: 687b ldr r3, [r7, #4] 8007cc4: 7f5b ldrb r3, [r3, #29] 8007cc6: b2db uxtb r3, r3 8007cc8: 2b00 cmp r3, #0 8007cca: d105 bne.n 8007cd8 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8007ccc: 687b ldr r3, [r7, #4] 8007cce: 2200 movs r2, #0 8007cd0: 771a strb r2, [r3, #28] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 8007cd2: 6878 ldr r0, [r7, #4] 8007cd4: f7fc fa1a bl 800410c } hcrc->State = HAL_CRC_STATE_BUSY; 8007cd8: 687b ldr r3, [r7, #4] 8007cda: 2202 movs r2, #2 8007cdc: 775a strb r2, [r3, #29] /* check whether or not non-default generating polynomial has been * picked up by user */ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) 8007cde: 687b ldr r3, [r7, #4] 8007ce0: 791b ldrb r3, [r3, #4] 8007ce2: 2b00 cmp r3, #0 8007ce4: d10c bne.n 8007d00 { /* initialize peripheral with default generating polynomial */ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); 8007ce6: 687b ldr r3, [r7, #4] 8007ce8: 681b ldr r3, [r3, #0] 8007cea: 4a22 ldr r2, [pc, #136] @ (8007d74 ) 8007cec: 615a str r2, [r3, #20] MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); 8007cee: 687b ldr r3, [r7, #4] 8007cf0: 681b ldr r3, [r3, #0] 8007cf2: 689a ldr r2, [r3, #8] 8007cf4: 687b ldr r3, [r7, #4] 8007cf6: 681b ldr r3, [r3, #0] 8007cf8: f022 0218 bic.w r2, r2, #24 8007cfc: 609a str r2, [r3, #8] 8007cfe: e00c b.n 8007d1a } else { /* initialize CRC peripheral with generating polynomial defined by user */ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) 8007d00: 687b ldr r3, [r7, #4] 8007d02: 6899 ldr r1, [r3, #8] 8007d04: 687b ldr r3, [r7, #4] 8007d06: 68db ldr r3, [r3, #12] 8007d08: 461a mov r2, r3 8007d0a: 6878 ldr r0, [r7, #4] 8007d0c: f000 f948 bl 8007fa0 8007d10: 4603 mov r3, r0 8007d12: 2b00 cmp r3, #0 8007d14: d001 beq.n 8007d1a { return HAL_ERROR; 8007d16: 2301 movs r3, #1 8007d18: e028 b.n 8007d6c } /* check whether or not non-default CRC initial value has been * picked up by user */ assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) 8007d1a: 687b ldr r3, [r7, #4] 8007d1c: 795b ldrb r3, [r3, #5] 8007d1e: 2b00 cmp r3, #0 8007d20: d105 bne.n 8007d2e { WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); 8007d22: 687b ldr r3, [r7, #4] 8007d24: 681b ldr r3, [r3, #0] 8007d26: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007d2a: 611a str r2, [r3, #16] 8007d2c: e004 b.n 8007d38 } else { WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); 8007d2e: 687b ldr r3, [r7, #4] 8007d30: 681b ldr r3, [r3, #0] 8007d32: 687a ldr r2, [r7, #4] 8007d34: 6912 ldr r2, [r2, #16] 8007d36: 611a str r2, [r3, #16] } /* set input data inversion mode */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); 8007d38: 687b ldr r3, [r7, #4] 8007d3a: 681b ldr r3, [r3, #0] 8007d3c: 689b ldr r3, [r3, #8] 8007d3e: f023 0160 bic.w r1, r3, #96 @ 0x60 8007d42: 687b ldr r3, [r7, #4] 8007d44: 695a ldr r2, [r3, #20] 8007d46: 687b ldr r3, [r7, #4] 8007d48: 681b ldr r3, [r3, #0] 8007d4a: 430a orrs r2, r1 8007d4c: 609a str r2, [r3, #8] /* set output data inversion mode */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); 8007d4e: 687b ldr r3, [r7, #4] 8007d50: 681b ldr r3, [r3, #0] 8007d52: 689b ldr r3, [r3, #8] 8007d54: f023 0180 bic.w r1, r3, #128 @ 0x80 8007d58: 687b ldr r3, [r7, #4] 8007d5a: 699a ldr r2, [r3, #24] 8007d5c: 687b ldr r3, [r7, #4] 8007d5e: 681b ldr r3, [r3, #0] 8007d60: 430a orrs r2, r1 8007d62: 609a str r2, [r3, #8] /* makes sure the input data format (bytes, halfwords or words stream) * is properly specified by user */ assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007d64: 687b ldr r3, [r7, #4] 8007d66: 2201 movs r2, #1 8007d68: 775a strb r2, [r3, #29] /* Return function status */ return HAL_OK; 8007d6a: 2300 movs r3, #0 } 8007d6c: 4618 mov r0, r3 8007d6e: 3708 adds r7, #8 8007d70: 46bd mov sp, r7 8007d72: bd80 pop {r7, pc} 8007d74: 04c11db7 .word 0x04c11db7 08007d78 : * and the API will internally adjust its input data processing based on the * handle field hcrc->InputDataFormat. * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { 8007d78: b580 push {r7, lr} 8007d7a: b086 sub sp, #24 8007d7c: af00 add r7, sp, #0 8007d7e: 60f8 str r0, [r7, #12] 8007d80: 60b9 str r1, [r7, #8] 8007d82: 607a str r2, [r7, #4] uint32_t index; /* CRC input data buffer index */ uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ 8007d84: 2300 movs r3, #0 8007d86: 613b str r3, [r7, #16] /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; 8007d88: 68fb ldr r3, [r7, #12] 8007d8a: 2202 movs r2, #2 8007d8c: 775a strb r2, [r3, #29] /* Reset CRC Calculation Unit (hcrc->Instance->INIT is * written in hcrc->Instance->DR) */ __HAL_CRC_DR_RESET(hcrc); 8007d8e: 68fb ldr r3, [r7, #12] 8007d90: 681b ldr r3, [r3, #0] 8007d92: 689a ldr r2, [r3, #8] 8007d94: 68fb ldr r3, [r7, #12] 8007d96: 681b ldr r3, [r3, #0] 8007d98: f042 0201 orr.w r2, r2, #1 8007d9c: 609a str r2, [r3, #8] switch (hcrc->InputDataFormat) 8007d9e: 68fb ldr r3, [r7, #12] 8007da0: 6a1b ldr r3, [r3, #32] 8007da2: 2b03 cmp r3, #3 8007da4: d006 beq.n 8007db4 8007da6: 2b03 cmp r3, #3 8007da8: d829 bhi.n 8007dfe 8007daa: 2b01 cmp r3, #1 8007dac: d019 beq.n 8007de2 8007dae: 2b02 cmp r3, #2 8007db0: d01e beq.n 8007df0 /* Specific 16-bit input data handling */ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ break; default: break; 8007db2: e024 b.n 8007dfe for (index = 0U; index < BufferLength; index++) 8007db4: 2300 movs r3, #0 8007db6: 617b str r3, [r7, #20] 8007db8: e00a b.n 8007dd0 hcrc->Instance->DR = pBuffer[index]; 8007dba: 697b ldr r3, [r7, #20] 8007dbc: 009b lsls r3, r3, #2 8007dbe: 68ba ldr r2, [r7, #8] 8007dc0: 441a add r2, r3 8007dc2: 68fb ldr r3, [r7, #12] 8007dc4: 681b ldr r3, [r3, #0] 8007dc6: 6812 ldr r2, [r2, #0] 8007dc8: 601a str r2, [r3, #0] for (index = 0U; index < BufferLength; index++) 8007dca: 697b ldr r3, [r7, #20] 8007dcc: 3301 adds r3, #1 8007dce: 617b str r3, [r7, #20] 8007dd0: 697a ldr r2, [r7, #20] 8007dd2: 687b ldr r3, [r7, #4] 8007dd4: 429a cmp r2, r3 8007dd6: d3f0 bcc.n 8007dba temp = hcrc->Instance->DR; 8007dd8: 68fb ldr r3, [r7, #12] 8007dda: 681b ldr r3, [r3, #0] 8007ddc: 681b ldr r3, [r3, #0] 8007dde: 613b str r3, [r7, #16] break; 8007de0: e00e b.n 8007e00 temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); 8007de2: 687a ldr r2, [r7, #4] 8007de4: 68b9 ldr r1, [r7, #8] 8007de6: 68f8 ldr r0, [r7, #12] 8007de8: f000 f812 bl 8007e10 8007dec: 6138 str r0, [r7, #16] break; 8007dee: e007 b.n 8007e00 temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ 8007df0: 687a ldr r2, [r7, #4] 8007df2: 68b9 ldr r1, [r7, #8] 8007df4: 68f8 ldr r0, [r7, #12] 8007df6: f000 f899 bl 8007f2c 8007dfa: 6138 str r0, [r7, #16] break; 8007dfc: e000 b.n 8007e00 break; 8007dfe: bf00 nop } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 8007e00: 68fb ldr r3, [r7, #12] 8007e02: 2201 movs r2, #1 8007e04: 775a strb r2, [r3, #29] /* Return the CRC computed value */ return temp; 8007e06: 693b ldr r3, [r7, #16] } 8007e08: 4618 mov r0, r3 8007e0a: 3718 adds r7, #24 8007e0c: 46bd mov sp, r7 8007e0e: bd80 pop {r7, pc} 08007e10 : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { 8007e10: b480 push {r7} 8007e12: b089 sub sp, #36 @ 0x24 8007e14: af00 add r7, sp, #0 8007e16: 60f8 str r0, [r7, #12] 8007e18: 60b9 str r1, [r7, #8] 8007e1a: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the peripheral */ for (i = 0U; i < (BufferLength / 4U); i++) 8007e1c: 2300 movs r3, #0 8007e1e: 61fb str r3, [r7, #28] 8007e20: e023 b.n 8007e6a { hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e22: 69fb ldr r3, [r7, #28] 8007e24: 009b lsls r3, r3, #2 8007e26: 68ba ldr r2, [r7, #8] 8007e28: 4413 add r3, r2 8007e2a: 781b ldrb r3, [r3, #0] 8007e2c: 061a lsls r2, r3, #24 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007e2e: 69fb ldr r3, [r7, #28] 8007e30: 009b lsls r3, r3, #2 8007e32: 3301 adds r3, #1 8007e34: 68b9 ldr r1, [r7, #8] 8007e36: 440b add r3, r1 8007e38: 781b ldrb r3, [r3, #0] 8007e3a: 041b lsls r3, r3, #16 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e3c: 431a orrs r2, r3 ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007e3e: 69fb ldr r3, [r7, #28] 8007e40: 009b lsls r3, r3, #2 8007e42: 3302 adds r3, #2 8007e44: 68b9 ldr r1, [r7, #8] 8007e46: 440b add r3, r1 8007e48: 781b ldrb r3, [r3, #0] 8007e4a: 021b lsls r3, r3, #8 ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ 8007e4c: 431a orrs r2, r3 (uint32_t)pBuffer[(4U * i) + 3U]; 8007e4e: 69fb ldr r3, [r7, #28] 8007e50: 009b lsls r3, r3, #2 8007e52: 3303 adds r3, #3 8007e54: 68b9 ldr r1, [r7, #8] 8007e56: 440b add r3, r1 8007e58: 781b ldrb r3, [r3, #0] 8007e5a: 4619 mov r1, r3 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e5c: 68fb ldr r3, [r7, #12] 8007e5e: 681b ldr r3, [r3, #0] ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ 8007e60: 430a orrs r2, r1 hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ 8007e62: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 4U); i++) 8007e64: 69fb ldr r3, [r7, #28] 8007e66: 3301 adds r3, #1 8007e68: 61fb str r3, [r7, #28] 8007e6a: 687b ldr r3, [r7, #4] 8007e6c: 089b lsrs r3, r3, #2 8007e6e: 69fa ldr r2, [r7, #28] 8007e70: 429a cmp r2, r3 8007e72: d3d6 bcc.n 8007e22 } /* last bytes specific handling */ if ((BufferLength % 4U) != 0U) 8007e74: 687b ldr r3, [r7, #4] 8007e76: f003 0303 and.w r3, r3, #3 8007e7a: 2b00 cmp r3, #0 8007e7c: d04d beq.n 8007f1a { if ((BufferLength % 4U) == 1U) 8007e7e: 687b ldr r3, [r7, #4] 8007e80: f003 0303 and.w r3, r3, #3 8007e84: 2b01 cmp r3, #1 8007e86: d107 bne.n 8007e98 { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ 8007e88: 69fb ldr r3, [r7, #28] 8007e8a: 009b lsls r3, r3, #2 8007e8c: 68ba ldr r2, [r7, #8] 8007e8e: 4413 add r3, r2 8007e90: 68fa ldr r2, [r7, #12] 8007e92: 6812 ldr r2, [r2, #0] 8007e94: 781b ldrb r3, [r3, #0] 8007e96: 7013 strb r3, [r2, #0] } if ((BufferLength % 4U) == 2U) 8007e98: 687b ldr r3, [r7, #4] 8007e9a: f003 0303 and.w r3, r3, #3 8007e9e: 2b02 cmp r3, #2 8007ea0: d116 bne.n 8007ed0 { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007ea2: 69fb ldr r3, [r7, #28] 8007ea4: 009b lsls r3, r3, #2 8007ea6: 68ba ldr r2, [r7, #8] 8007ea8: 4413 add r3, r2 8007eaa: 781b ldrb r3, [r3, #0] 8007eac: 021b lsls r3, r3, #8 8007eae: b21a sxth r2, r3 8007eb0: 69fb ldr r3, [r7, #28] 8007eb2: 009b lsls r3, r3, #2 8007eb4: 3301 adds r3, #1 8007eb6: 68b9 ldr r1, [r7, #8] 8007eb8: 440b add r3, r1 8007eba: 781b ldrb r3, [r3, #0] 8007ebc: b21b sxth r3, r3 8007ebe: 4313 orrs r3, r2 8007ec0: b21b sxth r3, r3 8007ec2: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007ec4: 68fb ldr r3, [r7, #12] 8007ec6: 681b ldr r3, [r3, #0] 8007ec8: 617b str r3, [r7, #20] *pReg = data; 8007eca: 697b ldr r3, [r7, #20] 8007ecc: 8b7a ldrh r2, [r7, #26] 8007ece: 801a strh r2, [r3, #0] } if ((BufferLength % 4U) == 3U) 8007ed0: 687b ldr r3, [r7, #4] 8007ed2: f003 0303 and.w r3, r3, #3 8007ed6: 2b03 cmp r3, #3 8007ed8: d11f bne.n 8007f1a { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; 8007eda: 69fb ldr r3, [r7, #28] 8007edc: 009b lsls r3, r3, #2 8007ede: 68ba ldr r2, [r7, #8] 8007ee0: 4413 add r3, r2 8007ee2: 781b ldrb r3, [r3, #0] 8007ee4: 021b lsls r3, r3, #8 8007ee6: b21a sxth r2, r3 8007ee8: 69fb ldr r3, [r7, #28] 8007eea: 009b lsls r3, r3, #2 8007eec: 3301 adds r3, #1 8007eee: 68b9 ldr r1, [r7, #8] 8007ef0: 440b add r3, r1 8007ef2: 781b ldrb r3, [r3, #0] 8007ef4: b21b sxth r3, r3 8007ef6: 4313 orrs r3, r2 8007ef8: b21b sxth r3, r3 8007efa: 837b strh r3, [r7, #26] pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007efc: 68fb ldr r3, [r7, #12] 8007efe: 681b ldr r3, [r3, #0] 8007f00: 617b str r3, [r7, #20] *pReg = data; 8007f02: 697b ldr r3, [r7, #20] 8007f04: 8b7a ldrh r2, [r7, #26] 8007f06: 801a strh r2, [r3, #0] *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ 8007f08: 69fb ldr r3, [r7, #28] 8007f0a: 009b lsls r3, r3, #2 8007f0c: 3302 adds r3, #2 8007f0e: 68ba ldr r2, [r7, #8] 8007f10: 4413 add r3, r2 8007f12: 68fa ldr r2, [r7, #12] 8007f14: 6812 ldr r2, [r2, #0] 8007f16: 781b ldrb r3, [r3, #0] 8007f18: 7013 strb r3, [r2, #0] } } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007f1a: 68fb ldr r3, [r7, #12] 8007f1c: 681b ldr r3, [r3, #0] 8007f1e: 681b ldr r3, [r3, #0] } 8007f20: 4618 mov r0, r3 8007f22: 3724 adds r7, #36 @ 0x24 8007f24: 46bd mov sp, r7 8007f26: f85d 7b04 ldr.w r7, [sp], #4 8007f2a: 4770 bx lr 08007f2c : * @param pBuffer pointer to the input data buffer * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { 8007f2c: b480 push {r7} 8007f2e: b087 sub sp, #28 8007f30: af00 add r7, sp, #0 8007f32: 60f8 str r0, [r7, #12] 8007f34: 60b9 str r1, [r7, #8] 8007f36: 607a str r2, [r7, #4] __IO uint16_t *pReg; /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the peripheral */ for (i = 0U; i < (BufferLength / 2U); i++) 8007f38: 2300 movs r3, #0 8007f3a: 617b str r3, [r7, #20] 8007f3c: e013 b.n 8007f66 { hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; 8007f3e: 697b ldr r3, [r7, #20] 8007f40: 009b lsls r3, r3, #2 8007f42: 68ba ldr r2, [r7, #8] 8007f44: 4413 add r3, r2 8007f46: 881b ldrh r3, [r3, #0] 8007f48: 041a lsls r2, r3, #16 8007f4a: 697b ldr r3, [r7, #20] 8007f4c: 009b lsls r3, r3, #2 8007f4e: 3302 adds r3, #2 8007f50: 68b9 ldr r1, [r7, #8] 8007f52: 440b add r3, r1 8007f54: 881b ldrh r3, [r3, #0] 8007f56: 4619 mov r1, r3 8007f58: 68fb ldr r3, [r7, #12] 8007f5a: 681b ldr r3, [r3, #0] 8007f5c: 430a orrs r2, r1 8007f5e: 601a str r2, [r3, #0] for (i = 0U; i < (BufferLength / 2U); i++) 8007f60: 697b ldr r3, [r7, #20] 8007f62: 3301 adds r3, #1 8007f64: 617b str r3, [r7, #20] 8007f66: 687b ldr r3, [r7, #4] 8007f68: 085b lsrs r3, r3, #1 8007f6a: 697a ldr r2, [r7, #20] 8007f6c: 429a cmp r2, r3 8007f6e: d3e6 bcc.n 8007f3e } if ((BufferLength % 2U) != 0U) 8007f70: 687b ldr r3, [r7, #4] 8007f72: f003 0301 and.w r3, r3, #1 8007f76: 2b00 cmp r3, #0 8007f78: d009 beq.n 8007f8e { pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ 8007f7a: 68fb ldr r3, [r7, #12] 8007f7c: 681b ldr r3, [r3, #0] 8007f7e: 613b str r3, [r7, #16] *pReg = pBuffer[2U * i]; 8007f80: 697b ldr r3, [r7, #20] 8007f82: 009b lsls r3, r3, #2 8007f84: 68ba ldr r2, [r7, #8] 8007f86: 4413 add r3, r2 8007f88: 881a ldrh r2, [r3, #0] 8007f8a: 693b ldr r3, [r7, #16] 8007f8c: 801a strh r2, [r3, #0] } /* Return the CRC computed value */ return hcrc->Instance->DR; 8007f8e: 68fb ldr r3, [r7, #12] 8007f90: 681b ldr r3, [r3, #0] 8007f92: 681b ldr r3, [r3, #0] } 8007f94: 4618 mov r0, r3 8007f96: 371c adds r7, #28 8007f98: 46bd mov sp, r7 8007f9a: f85d 7b04 ldr.w r7, [sp], #4 8007f9e: 4770 bx lr 08007fa0 : * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) { 8007fa0: b480 push {r7} 8007fa2: b087 sub sp, #28 8007fa4: af00 add r7, sp, #0 8007fa6: 60f8 str r0, [r7, #12] 8007fa8: 60b9 str r1, [r7, #8] 8007faa: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8007fac: 2300 movs r3, #0 8007fae: 75fb strb r3, [r7, #23] uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ 8007fb0: 231f movs r3, #31 8007fb2: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); /* Ensure that the generating polynomial is odd */ if ((Pol & (uint32_t)(0x1U)) == 0U) 8007fb4: 68bb ldr r3, [r7, #8] 8007fb6: f003 0301 and.w r3, r3, #1 8007fba: 2b00 cmp r3, #0 8007fbc: d102 bne.n 8007fc4 { status = HAL_ERROR; 8007fbe: 2301 movs r3, #1 8007fc0: 75fb strb r3, [r7, #23] 8007fc2: e063 b.n 800808c * definition. HAL_ERROR is reported if Pol degree is * larger than that indicated by PolyLength. * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) 8007fc4: bf00 nop 8007fc6: 693b ldr r3, [r7, #16] 8007fc8: 1e5a subs r2, r3, #1 8007fca: 613a str r2, [r7, #16] 8007fcc: 2b00 cmp r3, #0 8007fce: d009 beq.n 8007fe4 8007fd0: 693b ldr r3, [r7, #16] 8007fd2: f003 031f and.w r3, r3, #31 8007fd6: 68ba ldr r2, [r7, #8] 8007fd8: fa22 f303 lsr.w r3, r2, r3 8007fdc: f003 0301 and.w r3, r3, #1 8007fe0: 2b00 cmp r3, #0 8007fe2: d0f0 beq.n 8007fc6 { } switch (PolyLength) 8007fe4: 687b ldr r3, [r7, #4] 8007fe6: 2b18 cmp r3, #24 8007fe8: d846 bhi.n 8008078 8007fea: a201 add r2, pc, #4 @ (adr r2, 8007ff0 ) 8007fec: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007ff0: 0800807f .word 0x0800807f 8007ff4: 08008079 .word 0x08008079 8007ff8: 08008079 .word 0x08008079 8007ffc: 08008079 .word 0x08008079 8008000: 08008079 .word 0x08008079 8008004: 08008079 .word 0x08008079 8008008: 08008079 .word 0x08008079 800800c: 08008079 .word 0x08008079 8008010: 0800806d .word 0x0800806d 8008014: 08008079 .word 0x08008079 8008018: 08008079 .word 0x08008079 800801c: 08008079 .word 0x08008079 8008020: 08008079 .word 0x08008079 8008024: 08008079 .word 0x08008079 8008028: 08008079 .word 0x08008079 800802c: 08008079 .word 0x08008079 8008030: 08008061 .word 0x08008061 8008034: 08008079 .word 0x08008079 8008038: 08008079 .word 0x08008079 800803c: 08008079 .word 0x08008079 8008040: 08008079 .word 0x08008079 8008044: 08008079 .word 0x08008079 8008048: 08008079 .word 0x08008079 800804c: 08008079 .word 0x08008079 8008050: 08008055 .word 0x08008055 { case CRC_POLYLENGTH_7B: if (msb >= HAL_CRC_LENGTH_7B) 8008054: 693b ldr r3, [r7, #16] 8008056: 2b06 cmp r3, #6 8008058: d913 bls.n 8008082 { status = HAL_ERROR; 800805a: 2301 movs r3, #1 800805c: 75fb strb r3, [r7, #23] } break; 800805e: e010 b.n 8008082 case CRC_POLYLENGTH_8B: if (msb >= HAL_CRC_LENGTH_8B) 8008060: 693b ldr r3, [r7, #16] 8008062: 2b07 cmp r3, #7 8008064: d90f bls.n 8008086 { status = HAL_ERROR; 8008066: 2301 movs r3, #1 8008068: 75fb strb r3, [r7, #23] } break; 800806a: e00c b.n 8008086 case CRC_POLYLENGTH_16B: if (msb >= HAL_CRC_LENGTH_16B) 800806c: 693b ldr r3, [r7, #16] 800806e: 2b0f cmp r3, #15 8008070: d90b bls.n 800808a { status = HAL_ERROR; 8008072: 2301 movs r3, #1 8008074: 75fb strb r3, [r7, #23] } break; 8008076: e008 b.n 800808a case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ break; default: status = HAL_ERROR; 8008078: 2301 movs r3, #1 800807a: 75fb strb r3, [r7, #23] break; 800807c: e006 b.n 800808c break; 800807e: bf00 nop 8008080: e004 b.n 800808c break; 8008082: bf00 nop 8008084: e002 b.n 800808c break; 8008086: bf00 nop 8008088: e000 b.n 800808c break; 800808a: bf00 nop } } if (status == HAL_OK) 800808c: 7dfb ldrb r3, [r7, #23] 800808e: 2b00 cmp r3, #0 8008090: d10d bne.n 80080ae { /* set generating polynomial */ WRITE_REG(hcrc->Instance->POL, Pol); 8008092: 68fb ldr r3, [r7, #12] 8008094: 681b ldr r3, [r3, #0] 8008096: 68ba ldr r2, [r7, #8] 8008098: 615a str r2, [r3, #20] /* set generating polynomial size */ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); 800809a: 68fb ldr r3, [r7, #12] 800809c: 681b ldr r3, [r3, #0] 800809e: 689b ldr r3, [r3, #8] 80080a0: f023 0118 bic.w r1, r3, #24 80080a4: 68fb ldr r3, [r7, #12] 80080a6: 681b ldr r3, [r3, #0] 80080a8: 687a ldr r2, [r7, #4] 80080aa: 430a orrs r2, r1 80080ac: 609a str r2, [r3, #8] } /* Return function status */ return status; 80080ae: 7dfb ldrb r3, [r7, #23] } 80080b0: 4618 mov r0, r3 80080b2: 371c adds r7, #28 80080b4: 46bd mov sp, r7 80080b6: f85d 7b04 ldr.w r7, [sp], #4 80080ba: 4770 bx lr 080080bc : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) { 80080bc: b580 push {r7, lr} 80080be: b082 sub sp, #8 80080c0: af00 add r7, sp, #0 80080c2: 6078 str r0, [r7, #4] /* Check the DAC peripheral handle */ if (hdac == NULL) 80080c4: 687b ldr r3, [r7, #4] 80080c6: 2b00 cmp r3, #0 80080c8: d101 bne.n 80080ce { return HAL_ERROR; 80080ca: 2301 movs r3, #1 80080cc: e014 b.n 80080f8 } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if (hdac->State == HAL_DAC_STATE_RESET) 80080ce: 687b ldr r3, [r7, #4] 80080d0: 791b ldrb r3, [r3, #4] 80080d2: b2db uxtb r3, r3 80080d4: 2b00 cmp r3, #0 80080d6: d105 bne.n 80080e4 hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /* Allocate lock resource and initialize it */ hdac->Lock = HAL_UNLOCKED; 80080d8: 687b ldr r3, [r7, #4] 80080da: 2200 movs r2, #0 80080dc: 715a strb r2, [r3, #5] #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); #else /* Init the low level hardware */ HAL_DAC_MspInit(hdac); 80080de: 6878 ldr r0, [r7, #4] 80080e0: f7fc f836 bl 8004150 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; 80080e4: 687b ldr r3, [r7, #4] 80080e6: 2202 movs r2, #2 80080e8: 711a strb r2, [r3, #4] /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; 80080ea: 687b ldr r3, [r7, #4] 80080ec: 2200 movs r2, #0 80080ee: 611a str r2, [r3, #16] /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; 80080f0: 687b ldr r3, [r7, #4] 80080f2: 2201 movs r2, #1 80080f4: 711a strb r2, [r3, #4] /* Return function status */ return HAL_OK; 80080f6: 2300 movs r3, #0 } 80080f8: 4618 mov r0, r3 80080fa: 3708 adds r7, #8 80080fc: 46bd mov sp, r7 80080fe: bd80 pop {r7, pc} 08008100 : * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { 8008100: b480 push {r7} 8008102: b083 sub sp, #12 8008104: af00 add r7, sp, #0 8008106: 6078 str r0, [r7, #4] 8008108: 6039 str r1, [r7, #0] /* Check the DAC peripheral handle */ if (hdac == NULL) 800810a: 687b ldr r3, [r7, #4] 800810c: 2b00 cmp r3, #0 800810e: d101 bne.n 8008114 { return HAL_ERROR; 8008110: 2301 movs r3, #1 8008112: e046 b.n 80081a2 /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 8008114: 687b ldr r3, [r7, #4] 8008116: 795b ldrb r3, [r3, #5] 8008118: 2b01 cmp r3, #1 800811a: d101 bne.n 8008120 800811c: 2302 movs r3, #2 800811e: e040 b.n 80081a2 8008120: 687b ldr r3, [r7, #4] 8008122: 2201 movs r2, #1 8008124: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 8008126: 687b ldr r3, [r7, #4] 8008128: 2202 movs r2, #2 800812a: 711a strb r2, [r3, #4] /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); 800812c: 687b ldr r3, [r7, #4] 800812e: 681b ldr r3, [r3, #0] 8008130: 6819 ldr r1, [r3, #0] 8008132: 683b ldr r3, [r7, #0] 8008134: f003 0310 and.w r3, r3, #16 8008138: 2201 movs r2, #1 800813a: 409a lsls r2, r3 800813c: 687b ldr r3, [r7, #4] 800813e: 681b ldr r3, [r3, #0] 8008140: 430a orrs r2, r1 8008142: 601a str r2, [r3, #0] if (Channel == DAC_CHANNEL_1) 8008144: 683b ldr r3, [r7, #0] 8008146: 2b00 cmp r3, #0 8008148: d10f bne.n 800816a { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) 800814a: 687b ldr r3, [r7, #4] 800814c: 681b ldr r3, [r3, #0] 800814e: 681b ldr r3, [r3, #0] 8008150: f003 033e and.w r3, r3, #62 @ 0x3e 8008154: 2b02 cmp r3, #2 8008156: d11d bne.n 8008194 { /* Enable the selected DAC software conversion */ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 8008158: 687b ldr r3, [r7, #4] 800815a: 681b ldr r3, [r3, #0] 800815c: 685a ldr r2, [r3, #4] 800815e: 687b ldr r3, [r7, #4] 8008160: 681b ldr r3, [r3, #0] 8008162: f042 0201 orr.w r2, r2, #1 8008166: 605a str r2, [r3, #4] 8008168: e014 b.n 8008194 } else { /* Check if software trigger enabled */ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) 800816a: 687b ldr r3, [r7, #4] 800816c: 681b ldr r3, [r3, #0] 800816e: 681b ldr r3, [r3, #0] 8008170: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000 8008174: 683b ldr r3, [r7, #0] 8008176: f003 0310 and.w r3, r3, #16 800817a: 2102 movs r1, #2 800817c: fa01 f303 lsl.w r3, r1, r3 8008180: 429a cmp r2, r3 8008182: d107 bne.n 8008194 { /* Enable the selected DAC software conversion*/ SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 8008184: 687b ldr r3, [r7, #4] 8008186: 681b ldr r3, [r3, #0] 8008188: 685a ldr r2, [r3, #4] 800818a: 687b ldr r3, [r7, #4] 800818c: 681b ldr r3, [r3, #0] 800818e: f042 0202 orr.w r2, r2, #2 8008192: 605a str r2, [r3, #4] } } /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 8008194: 687b ldr r3, [r7, #4] 8008196: 2201 movs r2, #1 8008198: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 800819a: 687b ldr r3, [r7, #4] 800819c: 2200 movs r2, #0 800819e: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 80081a0: 2300 movs r3, #0 } 80081a2: 4618 mov r0, r3 80081a4: 370c adds r7, #12 80081a6: 46bd mov sp, r7 80081a8: f85d 7b04 ldr.w r7, [sp], #4 80081ac: 4770 bx lr 080081ae : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { 80081ae: b580 push {r7, lr} 80081b0: b084 sub sp, #16 80081b2: af00 add r7, sp, #0 80081b4: 6078 str r0, [r7, #4] uint32_t itsource = hdac->Instance->CR; 80081b6: 687b ldr r3, [r7, #4] 80081b8: 681b ldr r3, [r3, #0] 80081ba: 681b ldr r3, [r3, #0] 80081bc: 60fb str r3, [r7, #12] uint32_t itflag = hdac->Instance->SR; 80081be: 687b ldr r3, [r7, #4] 80081c0: 681b ldr r3, [r3, #0] 80081c2: 6b5b ldr r3, [r3, #52] @ 0x34 80081c4: 60bb str r3, [r7, #8] if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) 80081c6: 68fb ldr r3, [r7, #12] 80081c8: f403 5300 and.w r3, r3, #8192 @ 0x2000 80081cc: 2b00 cmp r3, #0 80081ce: d01d beq.n 800820c { /* Check underrun flag of DAC channel 1 */ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) 80081d0: 68bb ldr r3, [r7, #8] 80081d2: f403 5300 and.w r3, r3, #8192 @ 0x2000 80081d6: 2b00 cmp r3, #0 80081d8: d018 beq.n 800820c { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 80081da: 687b ldr r3, [r7, #4] 80081dc: 2204 movs r2, #4 80081de: 711a strb r2, [r3, #4] /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 80081e0: 687b ldr r3, [r7, #4] 80081e2: 691b ldr r3, [r3, #16] 80081e4: f043 0201 orr.w r2, r3, #1 80081e8: 687b ldr r3, [r7, #4] 80081ea: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); 80081ec: 687b ldr r3, [r7, #4] 80081ee: 681b ldr r3, [r3, #0] 80081f0: f44f 5200 mov.w r2, #8192 @ 0x2000 80081f4: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel1 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); 80081f6: 687b ldr r3, [r7, #4] 80081f8: 681b ldr r3, [r3, #0] 80081fa: 681a ldr r2, [r3, #0] 80081fc: 687b ldr r3, [r7, #4] 80081fe: 681b ldr r3, [r3, #0] 8008200: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8008204: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else HAL_DAC_DMAUnderrunCallbackCh1(hdac); 8008206: 6878 ldr r0, [r7, #4] 8008208: f000 f851 bl 80082ae #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) 800820c: 68fb ldr r3, [r7, #12] 800820e: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8008212: 2b00 cmp r3, #0 8008214: d01d beq.n 8008252 { /* Check underrun flag of DAC channel 2 */ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) 8008216: 68bb ldr r3, [r7, #8] 8008218: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800821c: 2b00 cmp r3, #0 800821e: d018 beq.n 8008252 { /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; 8008220: 687b ldr r3, [r7, #4] 8008222: 2204 movs r2, #4 8008224: 711a strb r2, [r3, #4] /* Set DAC error code to channel2 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 8008226: 687b ldr r3, [r7, #4] 8008228: 691b ldr r3, [r3, #16] 800822a: f043 0202 orr.w r2, r3, #2 800822e: 687b ldr r3, [r7, #4] 8008230: 611a str r2, [r3, #16] /* Clear the underrun flag */ __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); 8008232: 687b ldr r3, [r7, #4] 8008234: 681b ldr r3, [r3, #0] 8008236: f04f 5200 mov.w r2, #536870912 @ 0x20000000 800823a: 635a str r2, [r3, #52] @ 0x34 /* Disable the selected DAC channel2 DMA request */ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); 800823c: 687b ldr r3, [r7, #4] 800823e: 681b ldr r3, [r3, #0] 8008240: 681a ldr r2, [r3, #0] 8008242: 687b ldr r3, [r7, #4] 8008244: 681b ldr r3, [r3, #0] 8008246: f022 5280 bic.w r2, r2, #268435456 @ 0x10000000 800824a: 601a str r2, [r3, #0] /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 800824c: 6878 ldr r0, [r7, #4] 800824e: f000 f97b bl 8008548 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } } 8008252: bf00 nop 8008254: 3710 adds r7, #16 8008256: 46bd mov sp, r7 8008258: bd80 pop {r7, pc} 0800825a : * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { 800825a: b480 push {r7} 800825c: b087 sub sp, #28 800825e: af00 add r7, sp, #0 8008260: 60f8 str r0, [r7, #12] 8008262: 60b9 str r1, [r7, #8] 8008264: 607a str r2, [r7, #4] 8008266: 603b str r3, [r7, #0] __IO uint32_t tmp = 0UL; 8008268: 2300 movs r3, #0 800826a: 617b str r3, [r7, #20] /* Check the DAC peripheral handle */ if (hdac == NULL) 800826c: 68fb ldr r3, [r7, #12] 800826e: 2b00 cmp r3, #0 8008270: d101 bne.n 8008276 { return HAL_ERROR; 8008272: 2301 movs r3, #1 8008274: e015 b.n 80082a2 /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)hdac->Instance; 8008276: 68fb ldr r3, [r7, #12] 8008278: 681b ldr r3, [r3, #0] 800827a: 617b str r3, [r7, #20] if (Channel == DAC_CHANNEL_1) 800827c: 68bb ldr r3, [r7, #8] 800827e: 2b00 cmp r3, #0 8008280: d105 bne.n 800828e { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 8008282: 697a ldr r2, [r7, #20] 8008284: 687b ldr r3, [r7, #4] 8008286: 4413 add r3, r2 8008288: 3308 adds r3, #8 800828a: 617b str r3, [r7, #20] 800828c: e004 b.n 8008298 } else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 800828e: 697a ldr r2, [r7, #20] 8008290: 687b ldr r3, [r7, #4] 8008292: 4413 add r3, r2 8008294: 3314 adds r3, #20 8008296: 617b str r3, [r7, #20] } /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; 8008298: 697b ldr r3, [r7, #20] 800829a: 461a mov r2, r3 800829c: 683b ldr r3, [r7, #0] 800829e: 6013 str r3, [r2, #0] /* Return function status */ return HAL_OK; 80082a0: 2300 movs r3, #0 } 80082a2: 4618 mov r0, r3 80082a4: 371c adds r7, #28 80082a6: 46bd mov sp, r7 80082a8: f85d 7b04 ldr.w r7, [sp], #4 80082ac: 4770 bx lr 080082ae : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { 80082ae: b480 push {r7} 80082b0: b083 sub sp, #12 80082b2: af00 add r7, sp, #0 80082b4: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } 80082b6: bf00 nop 80082b8: 370c adds r7, #12 80082ba: 46bd mov sp, r7 80082bc: f85d 7b04 ldr.w r7, [sp], #4 80082c0: 4770 bx lr ... 080082c4 : * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { 80082c4: b580 push {r7, lr} 80082c6: b08a sub sp, #40 @ 0x28 80082c8: af00 add r7, sp, #0 80082ca: 60f8 str r0, [r7, #12] 80082cc: 60b9 str r1, [r7, #8] 80082ce: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 80082d0: 2300 movs r3, #0 80082d2: f887 3023 strb.w r3, [r7, #35] @ 0x23 uint32_t tmpreg2; uint32_t tickstart; uint32_t connectOnChip; /* Check the DAC peripheral handle and channel configuration struct */ if ((hdac == NULL) || (sConfig == NULL)) 80082d6: 68fb ldr r3, [r7, #12] 80082d8: 2b00 cmp r3, #0 80082da: d002 beq.n 80082e2 80082dc: 68bb ldr r3, [r7, #8] 80082de: 2b00 cmp r3, #0 80082e0: d101 bne.n 80082e6 { return HAL_ERROR; 80082e2: 2301 movs r3, #1 80082e4: e12a b.n 800853c assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); 80082e6: 68fb ldr r3, [r7, #12] 80082e8: 795b ldrb r3, [r3, #5] 80082ea: 2b01 cmp r3, #1 80082ec: d101 bne.n 80082f2 80082ee: 2302 movs r3, #2 80082f0: e124 b.n 800853c 80082f2: 68fb ldr r3, [r7, #12] 80082f4: 2201 movs r2, #1 80082f6: 715a strb r2, [r3, #5] /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; 80082f8: 68fb ldr r3, [r7, #12] 80082fa: 2202 movs r2, #2 80082fc: 711a strb r2, [r3, #4] /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 80082fe: 68bb ldr r3, [r7, #8] 8008300: 681b ldr r3, [r3, #0] 8008302: 2b04 cmp r3, #4 8008304: d17a bne.n 80083fc { /* Get timeout */ tickstart = HAL_GetTick(); 8008306: f7fd fd8d bl 8005e24 800830a: 61f8 str r0, [r7, #28] if (Channel == DAC_CHANNEL_1) 800830c: 687b ldr r3, [r7, #4] 800830e: 2b00 cmp r3, #0 8008310: d13d bne.n 800838e { /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8008312: e018 b.n 8008346 { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8008314: f7fd fd86 bl 8005e24 8008318: 4602 mov r2, r0 800831a: 69fb ldr r3, [r7, #28] 800831c: 1ad3 subs r3, r2, r3 800831e: 2b01 cmp r3, #1 8008320: d911 bls.n 8008346 { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8008322: 68fb ldr r3, [r7, #12] 8008324: 681b ldr r3, [r3, #0] 8008326: 6b5a ldr r2, [r3, #52] @ 0x34 8008328: 4b86 ldr r3, [pc, #536] @ (8008544 ) 800832a: 4013 ands r3, r2 800832c: 2b00 cmp r3, #0 800832e: d00a beq.n 8008346 { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8008330: 68fb ldr r3, [r7, #12] 8008332: 691b ldr r3, [r3, #16] 8008334: f043 0208 orr.w r2, r3, #8 8008338: 68fb ldr r3, [r7, #12] 800833a: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 800833c: 68fb ldr r3, [r7, #12] 800833e: 2203 movs r2, #3 8008340: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 8008342: 2303 movs r3, #3 8008344: e0fa b.n 800853c while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) 8008346: 68fb ldr r3, [r7, #12] 8008348: 681b ldr r3, [r3, #0] 800834a: 6b5a ldr r2, [r3, #52] @ 0x34 800834c: 4b7d ldr r3, [pc, #500] @ (8008544 ) 800834e: 4013 ands r3, r2 8008350: 2b00 cmp r3, #0 8008352: d1df bne.n 8008314 } } } hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8008354: 68fb ldr r3, [r7, #12] 8008356: 681b ldr r3, [r3, #0] 8008358: 68ba ldr r2, [r7, #8] 800835a: 6992 ldr r2, [r2, #24] 800835c: 641a str r2, [r3, #64] @ 0x40 800835e: e020 b.n 80083a2 { /* SHSR2 can be written when BWST2 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 8008360: f7fd fd60 bl 8005e24 8008364: 4602 mov r2, r0 8008366: 69fb ldr r3, [r7, #28] 8008368: 1ad3 subs r3, r2, r3 800836a: 2b01 cmp r3, #1 800836c: d90f bls.n 800838e { /* New check to avoid false timeout detection in case of preemption */ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 800836e: 68fb ldr r3, [r7, #12] 8008370: 681b ldr r3, [r3, #0] 8008372: 6b5b ldr r3, [r3, #52] @ 0x34 8008374: 2b00 cmp r3, #0 8008376: da0a bge.n 800838e { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 8008378: 68fb ldr r3, [r7, #12] 800837a: 691b ldr r3, [r3, #16] 800837c: f043 0208 orr.w r2, r3, #8 8008380: 68fb ldr r3, [r7, #12] 8008382: 611a str r2, [r3, #16] /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; 8008384: 68fb ldr r3, [r7, #12] 8008386: 2203 movs r2, #3 8008388: 711a strb r2, [r3, #4] return HAL_TIMEOUT; 800838a: 2303 movs r3, #3 800838c: e0d6 b.n 800853c while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) 800838e: 68fb ldr r3, [r7, #12] 8008390: 681b ldr r3, [r3, #0] 8008392: 6b5b ldr r3, [r3, #52] @ 0x34 8008394: 2b00 cmp r3, #0 8008396: dbe3 blt.n 8008360 } } } hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 8008398: 68fb ldr r3, [r7, #12] 800839a: 681b ldr r3, [r3, #0] 800839c: 68ba ldr r2, [r7, #8] 800839e: 6992 ldr r2, [r2, #24] 80083a0: 645a str r2, [r3, #68] @ 0x44 } /* HoldTime */ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), 80083a2: 68fb ldr r3, [r7, #12] 80083a4: 681b ldr r3, [r3, #0] 80083a6: 6c9a ldr r2, [r3, #72] @ 0x48 80083a8: 687b ldr r3, [r7, #4] 80083aa: f003 0310 and.w r3, r3, #16 80083ae: f240 31ff movw r1, #1023 @ 0x3ff 80083b2: fa01 f303 lsl.w r3, r1, r3 80083b6: 43db mvns r3, r3 80083b8: ea02 0103 and.w r1, r2, r3 80083bc: 68bb ldr r3, [r7, #8] 80083be: 69da ldr r2, [r3, #28] 80083c0: 687b ldr r3, [r7, #4] 80083c2: f003 0310 and.w r3, r3, #16 80083c6: 409a lsls r2, r3 80083c8: 68fb ldr r3, [r7, #12] 80083ca: 681b ldr r3, [r3, #0] 80083cc: 430a orrs r2, r1 80083ce: 649a str r2, [r3, #72] @ 0x48 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), 80083d0: 68fb ldr r3, [r7, #12] 80083d2: 681b ldr r3, [r3, #0] 80083d4: 6cda ldr r2, [r3, #76] @ 0x4c 80083d6: 687b ldr r3, [r7, #4] 80083d8: f003 0310 and.w r3, r3, #16 80083dc: 21ff movs r1, #255 @ 0xff 80083de: fa01 f303 lsl.w r3, r1, r3 80083e2: 43db mvns r3, r3 80083e4: ea02 0103 and.w r1, r2, r3 80083e8: 68bb ldr r3, [r7, #8] 80083ea: 6a1a ldr r2, [r3, #32] 80083ec: 687b ldr r3, [r7, #4] 80083ee: f003 0310 and.w r3, r3, #16 80083f2: 409a lsls r2, r3 80083f4: 68fb ldr r3, [r7, #12] 80083f6: 681b ldr r3, [r3, #0] 80083f8: 430a orrs r2, r1 80083fa: 64da str r2, [r3, #76] @ 0x4c (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 80083fc: 68bb ldr r3, [r7, #8] 80083fe: 691b ldr r3, [r3, #16] 8008400: 2b01 cmp r3, #1 8008402: d11d bne.n 8008440 /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; 8008404: 68fb ldr r3, [r7, #12] 8008406: 681b ldr r3, [r3, #0] 8008408: 6b9b ldr r3, [r3, #56] @ 0x38 800840a: 61bb str r3, [r7, #24] /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); 800840c: 687b ldr r3, [r7, #4] 800840e: f003 0310 and.w r3, r3, #16 8008412: 221f movs r2, #31 8008414: fa02 f303 lsl.w r3, r2, r3 8008418: 43db mvns r3, r3 800841a: 69ba ldr r2, [r7, #24] 800841c: 4013 ands r3, r2 800841e: 61bb str r3, [r7, #24] /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; 8008420: 68bb ldr r3, [r7, #8] 8008422: 695b ldr r3, [r3, #20] 8008424: 617b str r3, [r7, #20] /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 8008426: 687b ldr r3, [r7, #4] 8008428: f003 0310 and.w r3, r3, #16 800842c: 697a ldr r2, [r7, #20] 800842e: fa02 f303 lsl.w r3, r2, r3 8008432: 69ba ldr r2, [r7, #24] 8008434: 4313 orrs r3, r2 8008436: 61bb str r3, [r7, #24] /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; 8008438: 68fb ldr r3, [r7, #12] 800843a: 681b ldr r3, [r3, #0] 800843c: 69ba ldr r2, [r7, #24] 800843e: 639a str r2, [r3, #56] @ 0x38 } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; 8008440: 68fb ldr r3, [r7, #12] 8008442: 681b ldr r3, [r3, #0] 8008444: 6bdb ldr r3, [r3, #60] @ 0x3c 8008446: 61bb str r3, [r7, #24] /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); 8008448: 687b ldr r3, [r7, #4] 800844a: f003 0310 and.w r3, r3, #16 800844e: 2207 movs r2, #7 8008450: fa02 f303 lsl.w r3, r2, r3 8008454: 43db mvns r3, r3 8008456: 69ba ldr r2, [r7, #24] 8008458: 4013 ands r3, r2 800845a: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) 800845c: 68bb ldr r3, [r7, #8] 800845e: 68db ldr r3, [r3, #12] 8008460: 2b01 cmp r3, #1 8008462: d102 bne.n 800846a { connectOnChip = 0x00000000UL; 8008464: 2300 movs r3, #0 8008466: 627b str r3, [r7, #36] @ 0x24 8008468: e00f b.n 800848a } else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) 800846a: 68bb ldr r3, [r7, #8] 800846c: 68db ldr r3, [r3, #12] 800846e: 2b02 cmp r3, #2 8008470: d102 bne.n 8008478 { connectOnChip = DAC_MCR_MODE1_0; 8008472: 2301 movs r3, #1 8008474: 627b str r3, [r7, #36] @ 0x24 8008476: e008 b.n 800848a } else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) 8008478: 68bb ldr r3, [r7, #8] 800847a: 689b ldr r3, [r3, #8] 800847c: 2b00 cmp r3, #0 800847e: d102 bne.n 8008486 { connectOnChip = DAC_MCR_MODE1_0; 8008480: 2301 movs r3, #1 8008482: 627b str r3, [r7, #36] @ 0x24 8008484: e001 b.n 800848a } else { connectOnChip = 0x00000000UL; 8008486: 2300 movs r3, #0 8008488: 627b str r3, [r7, #36] @ 0x24 } } tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip); 800848a: 68bb ldr r3, [r7, #8] 800848c: 681a ldr r2, [r3, #0] 800848e: 68bb ldr r3, [r7, #8] 8008490: 689b ldr r3, [r3, #8] 8008492: 4313 orrs r3, r2 8008494: 6a7a ldr r2, [r7, #36] @ 0x24 8008496: 4313 orrs r3, r2 8008498: 617b str r3, [r7, #20] /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 800849a: 687b ldr r3, [r7, #4] 800849c: f003 0310 and.w r3, r3, #16 80084a0: 697a ldr r2, [r7, #20] 80084a2: fa02 f303 lsl.w r3, r2, r3 80084a6: 69ba ldr r2, [r7, #24] 80084a8: 4313 orrs r3, r2 80084aa: 61bb str r3, [r7, #24] /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; 80084ac: 68fb ldr r3, [r7, #12] 80084ae: 681b ldr r3, [r3, #0] 80084b0: 69ba ldr r2, [r7, #24] 80084b2: 63da str r2, [r3, #60] @ 0x3c /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); 80084b4: 68fb ldr r3, [r7, #12] 80084b6: 681b ldr r3, [r3, #0] 80084b8: 6819 ldr r1, [r3, #0] 80084ba: 687b ldr r3, [r7, #4] 80084bc: f003 0310 and.w r3, r3, #16 80084c0: f44f 4280 mov.w r2, #16384 @ 0x4000 80084c4: fa02 f303 lsl.w r3, r2, r3 80084c8: 43da mvns r2, r3 80084ca: 68fb ldr r3, [r7, #12] 80084cc: 681b ldr r3, [r3, #0] 80084ce: 400a ands r2, r1 80084d0: 601a str r2, [r3, #0] /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; 80084d2: 68fb ldr r3, [r7, #12] 80084d4: 681b ldr r3, [r3, #0] 80084d6: 681b ldr r3, [r3, #0] 80084d8: 61bb str r3, [r7, #24] /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); 80084da: 687b ldr r3, [r7, #4] 80084dc: f003 0310 and.w r3, r3, #16 80084e0: f640 72fe movw r2, #4094 @ 0xffe 80084e4: fa02 f303 lsl.w r3, r2, r3 80084e8: 43db mvns r3, r3 80084ea: 69ba ldr r2, [r7, #24] 80084ec: 4013 ands r3, r2 80084ee: 61bb str r3, [r7, #24] /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = sConfig->DAC_Trigger; 80084f0: 68bb ldr r3, [r7, #8] 80084f2: 685b ldr r3, [r3, #4] 80084f4: 617b str r3, [r7, #20] /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << (Channel & 0x10UL); 80084f6: 687b ldr r3, [r7, #4] 80084f8: f003 0310 and.w r3, r3, #16 80084fc: 697a ldr r2, [r7, #20] 80084fe: fa02 f303 lsl.w r3, r2, r3 8008502: 69ba ldr r2, [r7, #24] 8008504: 4313 orrs r3, r2 8008506: 61bb str r3, [r7, #24] /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; 8008508: 68fb ldr r3, [r7, #12] 800850a: 681b ldr r3, [r3, #0] 800850c: 69ba ldr r2, [r7, #24] 800850e: 601a str r2, [r3, #0] /* Disable wave generation */ CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); 8008510: 68fb ldr r3, [r7, #12] 8008512: 681b ldr r3, [r3, #0] 8008514: 6819 ldr r1, [r3, #0] 8008516: 687b ldr r3, [r7, #4] 8008518: f003 0310 and.w r3, r3, #16 800851c: 22c0 movs r2, #192 @ 0xc0 800851e: fa02 f303 lsl.w r3, r2, r3 8008522: 43da mvns r2, r3 8008524: 68fb ldr r3, [r7, #12] 8008526: 681b ldr r3, [r3, #0] 8008528: 400a ands r2, r1 800852a: 601a str r2, [r3, #0] /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; 800852c: 68fb ldr r3, [r7, #12] 800852e: 2201 movs r2, #1 8008530: 711a strb r2, [r3, #4] /* Process unlocked */ __HAL_UNLOCK(hdac); 8008532: 68fb ldr r3, [r7, #12] 8008534: 2200 movs r2, #0 8008536: 715a strb r2, [r3, #5] /* Return function status */ return status; 8008538: f897 3023 ldrb.w r3, [r7, #35] @ 0x23 } 800853c: 4618 mov r0, r3 800853e: 3728 adds r7, #40 @ 0x28 8008540: 46bd mov sp, r7 8008542: bd80 pop {r7, pc} 8008544: 20008000 .word 0x20008000 08008548 : * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { 8008548: b480 push {r7} 800854a: b083 sub sp, #12 800854c: af00 add r7, sp, #0 800854e: 6078 str r0, [r7, #4] UNUSED(hdac); /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } 8008550: bf00 nop 8008552: 370c adds r7, #12 8008554: 46bd mov sp, r7 8008556: f85d 7b04 ldr.w r7, [sp], #4 800855a: 4770 bx lr 0800855c : * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 800855c: b580 push {r7, lr} 800855e: b086 sub sp, #24 8008560: af00 add r7, sp, #0 8008562: 6078 str r0, [r7, #4] uint32_t registerValue; uint32_t tickstart = HAL_GetTick(); 8008564: f7fd fc5e bl 8005e24 8008568: 6138 str r0, [r7, #16] DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 800856a: 687b ldr r3, [r7, #4] 800856c: 2b00 cmp r3, #0 800856e: d101 bne.n 8008574 { return HAL_ERROR; 8008570: 2301 movs r3, #1 8008572: e316 b.n 8008ba2 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008574: 687b ldr r3, [r7, #4] 8008576: 681b ldr r3, [r3, #0] 8008578: 4a66 ldr r2, [pc, #408] @ (8008714 ) 800857a: 4293 cmp r3, r2 800857c: d04a beq.n 8008614 800857e: 687b ldr r3, [r7, #4] 8008580: 681b ldr r3, [r3, #0] 8008582: 4a65 ldr r2, [pc, #404] @ (8008718 ) 8008584: 4293 cmp r3, r2 8008586: d045 beq.n 8008614 8008588: 687b ldr r3, [r7, #4] 800858a: 681b ldr r3, [r3, #0] 800858c: 4a63 ldr r2, [pc, #396] @ (800871c ) 800858e: 4293 cmp r3, r2 8008590: d040 beq.n 8008614 8008592: 687b ldr r3, [r7, #4] 8008594: 681b ldr r3, [r3, #0] 8008596: 4a62 ldr r2, [pc, #392] @ (8008720 ) 8008598: 4293 cmp r3, r2 800859a: d03b beq.n 8008614 800859c: 687b ldr r3, [r7, #4] 800859e: 681b ldr r3, [r3, #0] 80085a0: 4a60 ldr r2, [pc, #384] @ (8008724 ) 80085a2: 4293 cmp r3, r2 80085a4: d036 beq.n 8008614 80085a6: 687b ldr r3, [r7, #4] 80085a8: 681b ldr r3, [r3, #0] 80085aa: 4a5f ldr r2, [pc, #380] @ (8008728 ) 80085ac: 4293 cmp r3, r2 80085ae: d031 beq.n 8008614 80085b0: 687b ldr r3, [r7, #4] 80085b2: 681b ldr r3, [r3, #0] 80085b4: 4a5d ldr r2, [pc, #372] @ (800872c ) 80085b6: 4293 cmp r3, r2 80085b8: d02c beq.n 8008614 80085ba: 687b ldr r3, [r7, #4] 80085bc: 681b ldr r3, [r3, #0] 80085be: 4a5c ldr r2, [pc, #368] @ (8008730 ) 80085c0: 4293 cmp r3, r2 80085c2: d027 beq.n 8008614 80085c4: 687b ldr r3, [r7, #4] 80085c6: 681b ldr r3, [r3, #0] 80085c8: 4a5a ldr r2, [pc, #360] @ (8008734 ) 80085ca: 4293 cmp r3, r2 80085cc: d022 beq.n 8008614 80085ce: 687b ldr r3, [r7, #4] 80085d0: 681b ldr r3, [r3, #0] 80085d2: 4a59 ldr r2, [pc, #356] @ (8008738 ) 80085d4: 4293 cmp r3, r2 80085d6: d01d beq.n 8008614 80085d8: 687b ldr r3, [r7, #4] 80085da: 681b ldr r3, [r3, #0] 80085dc: 4a57 ldr r2, [pc, #348] @ (800873c ) 80085de: 4293 cmp r3, r2 80085e0: d018 beq.n 8008614 80085e2: 687b ldr r3, [r7, #4] 80085e4: 681b ldr r3, [r3, #0] 80085e6: 4a56 ldr r2, [pc, #344] @ (8008740 ) 80085e8: 4293 cmp r3, r2 80085ea: d013 beq.n 8008614 80085ec: 687b ldr r3, [r7, #4] 80085ee: 681b ldr r3, [r3, #0] 80085f0: 4a54 ldr r2, [pc, #336] @ (8008744 ) 80085f2: 4293 cmp r3, r2 80085f4: d00e beq.n 8008614 80085f6: 687b ldr r3, [r7, #4] 80085f8: 681b ldr r3, [r3, #0] 80085fa: 4a53 ldr r2, [pc, #332] @ (8008748 ) 80085fc: 4293 cmp r3, r2 80085fe: d009 beq.n 8008614 8008600: 687b ldr r3, [r7, #4] 8008602: 681b ldr r3, [r3, #0] 8008604: 4a51 ldr r2, [pc, #324] @ (800874c ) 8008606: 4293 cmp r3, r2 8008608: d004 beq.n 8008614 800860a: 687b ldr r3, [r7, #4] 800860c: 681b ldr r3, [r3, #0] 800860e: 4a50 ldr r2, [pc, #320] @ (8008750 ) 8008610: 4293 cmp r3, r2 8008612: d101 bne.n 8008618 8008614: 2301 movs r3, #1 8008616: e000 b.n 800861a 8008618: 2300 movs r3, #0 800861a: 2b00 cmp r3, #0 800861c: f000 813b beq.w 8008896 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008620: 687b ldr r3, [r7, #4] 8008622: 2202 movs r2, #2 8008624: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8008628: 687b ldr r3, [r7, #4] 800862a: 2200 movs r2, #0 800862c: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8008630: 687b ldr r3, [r7, #4] 8008632: 681b ldr r3, [r3, #0] 8008634: 4a37 ldr r2, [pc, #220] @ (8008714 ) 8008636: 4293 cmp r3, r2 8008638: d04a beq.n 80086d0 800863a: 687b ldr r3, [r7, #4] 800863c: 681b ldr r3, [r3, #0] 800863e: 4a36 ldr r2, [pc, #216] @ (8008718 ) 8008640: 4293 cmp r3, r2 8008642: d045 beq.n 80086d0 8008644: 687b ldr r3, [r7, #4] 8008646: 681b ldr r3, [r3, #0] 8008648: 4a34 ldr r2, [pc, #208] @ (800871c ) 800864a: 4293 cmp r3, r2 800864c: d040 beq.n 80086d0 800864e: 687b ldr r3, [r7, #4] 8008650: 681b ldr r3, [r3, #0] 8008652: 4a33 ldr r2, [pc, #204] @ (8008720 ) 8008654: 4293 cmp r3, r2 8008656: d03b beq.n 80086d0 8008658: 687b ldr r3, [r7, #4] 800865a: 681b ldr r3, [r3, #0] 800865c: 4a31 ldr r2, [pc, #196] @ (8008724 ) 800865e: 4293 cmp r3, r2 8008660: d036 beq.n 80086d0 8008662: 687b ldr r3, [r7, #4] 8008664: 681b ldr r3, [r3, #0] 8008666: 4a30 ldr r2, [pc, #192] @ (8008728 ) 8008668: 4293 cmp r3, r2 800866a: d031 beq.n 80086d0 800866c: 687b ldr r3, [r7, #4] 800866e: 681b ldr r3, [r3, #0] 8008670: 4a2e ldr r2, [pc, #184] @ (800872c ) 8008672: 4293 cmp r3, r2 8008674: d02c beq.n 80086d0 8008676: 687b ldr r3, [r7, #4] 8008678: 681b ldr r3, [r3, #0] 800867a: 4a2d ldr r2, [pc, #180] @ (8008730 ) 800867c: 4293 cmp r3, r2 800867e: d027 beq.n 80086d0 8008680: 687b ldr r3, [r7, #4] 8008682: 681b ldr r3, [r3, #0] 8008684: 4a2b ldr r2, [pc, #172] @ (8008734 ) 8008686: 4293 cmp r3, r2 8008688: d022 beq.n 80086d0 800868a: 687b ldr r3, [r7, #4] 800868c: 681b ldr r3, [r3, #0] 800868e: 4a2a ldr r2, [pc, #168] @ (8008738 ) 8008690: 4293 cmp r3, r2 8008692: d01d beq.n 80086d0 8008694: 687b ldr r3, [r7, #4] 8008696: 681b ldr r3, [r3, #0] 8008698: 4a28 ldr r2, [pc, #160] @ (800873c ) 800869a: 4293 cmp r3, r2 800869c: d018 beq.n 80086d0 800869e: 687b ldr r3, [r7, #4] 80086a0: 681b ldr r3, [r3, #0] 80086a2: 4a27 ldr r2, [pc, #156] @ (8008740 ) 80086a4: 4293 cmp r3, r2 80086a6: d013 beq.n 80086d0 80086a8: 687b ldr r3, [r7, #4] 80086aa: 681b ldr r3, [r3, #0] 80086ac: 4a25 ldr r2, [pc, #148] @ (8008744 ) 80086ae: 4293 cmp r3, r2 80086b0: d00e beq.n 80086d0 80086b2: 687b ldr r3, [r7, #4] 80086b4: 681b ldr r3, [r3, #0] 80086b6: 4a24 ldr r2, [pc, #144] @ (8008748 ) 80086b8: 4293 cmp r3, r2 80086ba: d009 beq.n 80086d0 80086bc: 687b ldr r3, [r7, #4] 80086be: 681b ldr r3, [r3, #0] 80086c0: 4a22 ldr r2, [pc, #136] @ (800874c ) 80086c2: 4293 cmp r3, r2 80086c4: d004 beq.n 80086d0 80086c6: 687b ldr r3, [r7, #4] 80086c8: 681b ldr r3, [r3, #0] 80086ca: 4a21 ldr r2, [pc, #132] @ (8008750 ) 80086cc: 4293 cmp r3, r2 80086ce: d108 bne.n 80086e2 80086d0: 687b ldr r3, [r7, #4] 80086d2: 681b ldr r3, [r3, #0] 80086d4: 681a ldr r2, [r3, #0] 80086d6: 687b ldr r3, [r7, #4] 80086d8: 681b ldr r3, [r3, #0] 80086da: f022 0201 bic.w r2, r2, #1 80086de: 601a str r2, [r3, #0] 80086e0: e007 b.n 80086f2 80086e2: 687b ldr r3, [r7, #4] 80086e4: 681b ldr r3, [r3, #0] 80086e6: 681a ldr r2, [r3, #0] 80086e8: 687b ldr r3, [r7, #4] 80086ea: 681b ldr r3, [r3, #0] 80086ec: f022 0201 bic.w r2, r2, #1 80086f0: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 80086f2: e02f b.n 8008754 { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 80086f4: f7fd fb96 bl 8005e24 80086f8: 4602 mov r2, r0 80086fa: 693b ldr r3, [r7, #16] 80086fc: 1ad3 subs r3, r2, r3 80086fe: 2b05 cmp r3, #5 8008700: d928 bls.n 8008754 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8008702: 687b ldr r3, [r7, #4] 8008704: 2220 movs r2, #32 8008706: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 8008708: 687b ldr r3, [r7, #4] 800870a: 2203 movs r2, #3 800870c: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008710: 2301 movs r3, #1 8008712: e246 b.n 8008ba2 8008714: 40020010 .word 0x40020010 8008718: 40020028 .word 0x40020028 800871c: 40020040 .word 0x40020040 8008720: 40020058 .word 0x40020058 8008724: 40020070 .word 0x40020070 8008728: 40020088 .word 0x40020088 800872c: 400200a0 .word 0x400200a0 8008730: 400200b8 .word 0x400200b8 8008734: 40020410 .word 0x40020410 8008738: 40020428 .word 0x40020428 800873c: 40020440 .word 0x40020440 8008740: 40020458 .word 0x40020458 8008744: 40020470 .word 0x40020470 8008748: 40020488 .word 0x40020488 800874c: 400204a0 .word 0x400204a0 8008750: 400204b8 .word 0x400204b8 while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 8008754: 687b ldr r3, [r7, #4] 8008756: 681b ldr r3, [r3, #0] 8008758: 681b ldr r3, [r3, #0] 800875a: f003 0301 and.w r3, r3, #1 800875e: 2b00 cmp r3, #0 8008760: d1c8 bne.n 80086f4 } } /* Get the CR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; 8008762: 687b ldr r3, [r7, #4] 8008764: 681b ldr r3, [r3, #0] 8008766: 681b ldr r3, [r3, #0] 8008768: 617b str r3, [r7, #20] /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ 800876a: 697a ldr r2, [r7, #20] 800876c: 4b83 ldr r3, [pc, #524] @ (800897c ) 800876e: 4013 ands r3, r2 8008770: 617b str r3, [r7, #20] DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ registerValue |= hdma->Init.Direction | 8008772: 687b ldr r3, [r7, #4] 8008774: 689a ldr r2, [r3, #8] hdma->Init.PeriphInc | hdma->Init.MemInc | 8008776: 687b ldr r3, [r7, #4] 8008778: 68db ldr r3, [r3, #12] registerValue |= hdma->Init.Direction | 800877a: 431a orrs r2, r3 hdma->Init.PeriphInc | hdma->Init.MemInc | 800877c: 687b ldr r3, [r7, #4] 800877e: 691b ldr r3, [r3, #16] 8008780: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008782: 687b ldr r3, [r7, #4] 8008784: 695b ldr r3, [r3, #20] hdma->Init.PeriphInc | hdma->Init.MemInc | 8008786: 431a orrs r2, r3 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008788: 687b ldr r3, [r7, #4] 800878a: 699b ldr r3, [r3, #24] 800878c: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 800878e: 687b ldr r3, [r7, #4] 8008790: 69db ldr r3, [r3, #28] hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 8008792: 431a orrs r2, r3 hdma->Init.Mode | hdma->Init.Priority; 8008794: 687b ldr r3, [r7, #4] 8008796: 6a1b ldr r3, [r3, #32] 8008798: 4313 orrs r3, r2 registerValue |= hdma->Init.Direction | 800879a: 697a ldr r2, [r7, #20] 800879c: 4313 orrs r3, r2 800879e: 617b str r3, [r7, #20] /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 80087a0: 687b ldr r3, [r7, #4] 80087a2: 6a5b ldr r3, [r3, #36] @ 0x24 80087a4: 2b04 cmp r3, #4 80087a6: d107 bne.n 80087b8 { /* Get memory burst and peripheral burst */ registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; 80087a8: 687b ldr r3, [r7, #4] 80087aa: 6ada ldr r2, [r3, #44] @ 0x2c 80087ac: 687b ldr r3, [r7, #4] 80087ae: 6b1b ldr r3, [r3, #48] @ 0x30 80087b0: 4313 orrs r3, r2 80087b2: 697a ldr r2, [r7, #20] 80087b4: 4313 orrs r3, r2 80087b6: 617b str r3, [r7, #20] } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) 80087b8: 4b71 ldr r3, [pc, #452] @ (8008980 ) 80087ba: 681a ldr r2, [r3, #0] 80087bc: 4b71 ldr r3, [pc, #452] @ (8008984 ) 80087be: 4013 ands r3, r2 80087c0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80087c4: d328 bcc.n 8008818 { #endif /* STM32H7_DEV_ID == 0x450UL */ if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) 80087c6: 687b ldr r3, [r7, #4] 80087c8: 685b ldr r3, [r3, #4] 80087ca: 2b28 cmp r3, #40 @ 0x28 80087cc: d903 bls.n 80087d6 80087ce: 687b ldr r3, [r7, #4] 80087d0: 685b ldr r3, [r3, #4] 80087d2: 2b2e cmp r3, #46 @ 0x2e 80087d4: d917 bls.n 8008806 80087d6: 687b ldr r3, [r7, #4] 80087d8: 685b ldr r3, [r3, #4] 80087da: 2b3e cmp r3, #62 @ 0x3e 80087dc: d903 bls.n 80087e6 80087de: 687b ldr r3, [r7, #4] 80087e0: 685b ldr r3, [r3, #4] 80087e2: 2b42 cmp r3, #66 @ 0x42 80087e4: d90f bls.n 8008806 80087e6: 687b ldr r3, [r7, #4] 80087e8: 685b ldr r3, [r3, #4] 80087ea: 2b46 cmp r3, #70 @ 0x46 80087ec: d903 bls.n 80087f6 80087ee: 687b ldr r3, [r7, #4] 80087f0: 685b ldr r3, [r3, #4] 80087f2: 2b48 cmp r3, #72 @ 0x48 80087f4: d907 bls.n 8008806 80087f6: 687b ldr r3, [r7, #4] 80087f8: 685b ldr r3, [r3, #4] 80087fa: 2b4e cmp r3, #78 @ 0x4e 80087fc: d905 bls.n 800880a 80087fe: 687b ldr r3, [r7, #4] 8008800: 685b ldr r3, [r3, #4] 8008802: 2b52 cmp r3, #82 @ 0x52 8008804: d801 bhi.n 800880a 8008806: 2301 movs r3, #1 8008808: e000 b.n 800880c 800880a: 2300 movs r3, #0 800880c: 2b00 cmp r3, #0 800880e: d003 beq.n 8008818 { registerValue |= DMA_SxCR_TRBUFF; 8008810: 697b ldr r3, [r7, #20] 8008812: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8008816: 617b str r3, [r7, #20] #if (STM32H7_DEV_ID == 0x450UL) } #endif /* STM32H7_DEV_ID == 0x450UL */ /* Write to DMA Stream CR register */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; 8008818: 687b ldr r3, [r7, #4] 800881a: 681b ldr r3, [r3, #0] 800881c: 697a ldr r2, [r7, #20] 800881e: 601a str r2, [r3, #0] /* Get the FCR register value */ registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; 8008820: 687b ldr r3, [r7, #4] 8008822: 681b ldr r3, [r3, #0] 8008824: 695b ldr r3, [r3, #20] 8008826: 617b str r3, [r7, #20] /* Clear Direct mode and FIFO threshold bits */ registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); 8008828: 697b ldr r3, [r7, #20] 800882a: f023 0307 bic.w r3, r3, #7 800882e: 617b str r3, [r7, #20] /* Prepare the DMA Stream FIFO configuration */ registerValue |= hdma->Init.FIFOMode; 8008830: 687b ldr r3, [r7, #4] 8008832: 6a5b ldr r3, [r3, #36] @ 0x24 8008834: 697a ldr r2, [r7, #20] 8008836: 4313 orrs r3, r2 8008838: 617b str r3, [r7, #20] /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) 800883a: 687b ldr r3, [r7, #4] 800883c: 6a5b ldr r3, [r3, #36] @ 0x24 800883e: 2b04 cmp r3, #4 8008840: d117 bne.n 8008872 { /* Get the FIFO threshold */ registerValue |= hdma->Init.FIFOThreshold; 8008842: 687b ldr r3, [r7, #4] 8008844: 6a9b ldr r3, [r3, #40] @ 0x28 8008846: 697a ldr r2, [r7, #20] 8008848: 4313 orrs r3, r2 800884a: 617b str r3, [r7, #20] /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 */ if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) 800884c: 687b ldr r3, [r7, #4] 800884e: 6adb ldr r3, [r3, #44] @ 0x2c 8008850: 2b00 cmp r3, #0 8008852: d00e beq.n 8008872 { if (DMA_CheckFifoParam(hdma) != HAL_OK) 8008854: 6878 ldr r0, [r7, #4] 8008856: f002 fb33 bl 800aec0 800885a: 4603 mov r3, r0 800885c: 2b00 cmp r3, #0 800885e: d008 beq.n 8008872 { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8008860: 687b ldr r3, [r7, #4] 8008862: 2240 movs r2, #64 @ 0x40 8008864: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008866: 687b ldr r3, [r7, #4] 8008868: 2201 movs r2, #1 800886a: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 800886e: 2301 movs r3, #1 8008870: e197 b.n 8008ba2 } } } /* Write to DMA Stream FCR */ ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; 8008872: 687b ldr r3, [r7, #4] 8008874: 681b ldr r3, [r3, #0] 8008876: 697a ldr r2, [r7, #20] 8008878: 615a str r2, [r3, #20] /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 800887a: 6878 ldr r0, [r7, #4] 800887c: f002 fa6e bl 800ad5c 8008880: 4603 mov r3, r0 8008882: 60bb str r3, [r7, #8] /* Clear all interrupt flags */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 8008884: 687b ldr r3, [r7, #4] 8008886: 6ddb ldr r3, [r3, #92] @ 0x5c 8008888: f003 031f and.w r3, r3, #31 800888c: 223f movs r2, #63 @ 0x3f 800888e: 409a lsls r2, r3 8008890: 68bb ldr r3, [r7, #8] 8008892: 609a str r2, [r3, #8] 8008894: e0cd b.n 8008a32 } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 8008896: 687b ldr r3, [r7, #4] 8008898: 681b ldr r3, [r3, #0] 800889a: 4a3b ldr r2, [pc, #236] @ (8008988 ) 800889c: 4293 cmp r3, r2 800889e: d022 beq.n 80088e6 80088a0: 687b ldr r3, [r7, #4] 80088a2: 681b ldr r3, [r3, #0] 80088a4: 4a39 ldr r2, [pc, #228] @ (800898c ) 80088a6: 4293 cmp r3, r2 80088a8: d01d beq.n 80088e6 80088aa: 687b ldr r3, [r7, #4] 80088ac: 681b ldr r3, [r3, #0] 80088ae: 4a38 ldr r2, [pc, #224] @ (8008990 ) 80088b0: 4293 cmp r3, r2 80088b2: d018 beq.n 80088e6 80088b4: 687b ldr r3, [r7, #4] 80088b6: 681b ldr r3, [r3, #0] 80088b8: 4a36 ldr r2, [pc, #216] @ (8008994 ) 80088ba: 4293 cmp r3, r2 80088bc: d013 beq.n 80088e6 80088be: 687b ldr r3, [r7, #4] 80088c0: 681b ldr r3, [r3, #0] 80088c2: 4a35 ldr r2, [pc, #212] @ (8008998 ) 80088c4: 4293 cmp r3, r2 80088c6: d00e beq.n 80088e6 80088c8: 687b ldr r3, [r7, #4] 80088ca: 681b ldr r3, [r3, #0] 80088cc: 4a33 ldr r2, [pc, #204] @ (800899c ) 80088ce: 4293 cmp r3, r2 80088d0: d009 beq.n 80088e6 80088d2: 687b ldr r3, [r7, #4] 80088d4: 681b ldr r3, [r3, #0] 80088d6: 4a32 ldr r2, [pc, #200] @ (80089a0 ) 80088d8: 4293 cmp r3, r2 80088da: d004 beq.n 80088e6 80088dc: 687b ldr r3, [r7, #4] 80088de: 681b ldr r3, [r3, #0] 80088e0: 4a30 ldr r2, [pc, #192] @ (80089a4 ) 80088e2: 4293 cmp r3, r2 80088e4: d101 bne.n 80088ea 80088e6: 2301 movs r3, #1 80088e8: e000 b.n 80088ec 80088ea: 2300 movs r3, #0 80088ec: 2b00 cmp r3, #0 80088ee: f000 8097 beq.w 8008a20 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 80088f2: 687b ldr r3, [r7, #4] 80088f4: 681b ldr r3, [r3, #0] 80088f6: 4a24 ldr r2, [pc, #144] @ (8008988 ) 80088f8: 4293 cmp r3, r2 80088fa: d021 beq.n 8008940 80088fc: 687b ldr r3, [r7, #4] 80088fe: 681b ldr r3, [r3, #0] 8008900: 4a22 ldr r2, [pc, #136] @ (800898c ) 8008902: 4293 cmp r3, r2 8008904: d01c beq.n 8008940 8008906: 687b ldr r3, [r7, #4] 8008908: 681b ldr r3, [r3, #0] 800890a: 4a21 ldr r2, [pc, #132] @ (8008990 ) 800890c: 4293 cmp r3, r2 800890e: d017 beq.n 8008940 8008910: 687b ldr r3, [r7, #4] 8008912: 681b ldr r3, [r3, #0] 8008914: 4a1f ldr r2, [pc, #124] @ (8008994 ) 8008916: 4293 cmp r3, r2 8008918: d012 beq.n 8008940 800891a: 687b ldr r3, [r7, #4] 800891c: 681b ldr r3, [r3, #0] 800891e: 4a1e ldr r2, [pc, #120] @ (8008998 ) 8008920: 4293 cmp r3, r2 8008922: d00d beq.n 8008940 8008924: 687b ldr r3, [r7, #4] 8008926: 681b ldr r3, [r3, #0] 8008928: 4a1c ldr r2, [pc, #112] @ (800899c ) 800892a: 4293 cmp r3, r2 800892c: d008 beq.n 8008940 800892e: 687b ldr r3, [r7, #4] 8008930: 681b ldr r3, [r3, #0] 8008932: 4a1b ldr r2, [pc, #108] @ (80089a0 ) 8008934: 4293 cmp r3, r2 8008936: d003 beq.n 8008940 8008938: 687b ldr r3, [r7, #4] 800893a: 681b ldr r3, [r3, #0] 800893c: 4a19 ldr r2, [pc, #100] @ (80089a4 ) 800893e: 4293 cmp r3, r2 /* Check the request parameter */ assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); } /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008940: 687b ldr r3, [r7, #4] 8008942: 2202 movs r2, #2 8008944: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Allocate lock resource */ __HAL_UNLOCK(hdma); 8008948: 687b ldr r3, [r7, #4] 800894a: 2200 movs r2, #0 800894c: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Get the CR register value */ registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; 8008950: 687b ldr r3, [r7, #4] 8008952: 681b ldr r3, [r3, #0] 8008954: 681b ldr r3, [r3, #0] 8008956: 617b str r3, [r7, #20] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ 8008958: 697a ldr r2, [r7, #20] 800895a: 4b13 ldr r3, [pc, #76] @ (80089a8 ) 800895c: 4013 ands r3, r2 800895e: 617b str r3, [r7, #20] BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ BDMA_CCR_CT)); /* Prepare the DMA Channel configuration */ registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 8008960: 687b ldr r3, [r7, #4] 8008962: 689b ldr r3, [r3, #8] 8008964: 2b40 cmp r3, #64 @ 0x40 8008966: d021 beq.n 80089ac 8008968: 687b ldr r3, [r7, #4] 800896a: 689b ldr r3, [r3, #8] 800896c: 2b80 cmp r3, #128 @ 0x80 800896e: d102 bne.n 8008976 8008970: f44f 4380 mov.w r3, #16384 @ 0x4000 8008974: e01b b.n 80089ae 8008976: 2300 movs r3, #0 8008978: e019 b.n 80089ae 800897a: bf00 nop 800897c: fe10803f .word 0xfe10803f 8008980: 5c001000 .word 0x5c001000 8008984: ffff0000 .word 0xffff0000 8008988: 58025408 .word 0x58025408 800898c: 5802541c .word 0x5802541c 8008990: 58025430 .word 0x58025430 8008994: 58025444 .word 0x58025444 8008998: 58025458 .word 0x58025458 800899c: 5802546c .word 0x5802546c 80089a0: 58025480 .word 0x58025480 80089a4: 58025494 .word 0x58025494 80089a8: fffe000f .word 0xfffe000f 80089ac: 2310 movs r3, #16 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 80089ae: 687a ldr r2, [r7, #4] 80089b0: 68d2 ldr r2, [r2, #12] 80089b2: 08d2 lsrs r2, r2, #3 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80089b4: 431a orrs r2, r3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80089b6: 687b ldr r3, [r7, #4] 80089b8: 691b ldr r3, [r3, #16] 80089ba: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | 80089bc: 431a orrs r2, r3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80089be: 687b ldr r3, [r7, #4] 80089c0: 695b ldr r3, [r3, #20] 80089c2: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | 80089c4: 431a orrs r2, r3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80089c6: 687b ldr r3, [r7, #4] 80089c8: 699b ldr r3, [r3, #24] 80089ca: 08db lsrs r3, r3, #3 DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | 80089cc: 431a orrs r2, r3 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80089ce: 687b ldr r3, [r7, #4] 80089d0: 69db ldr r3, [r3, #28] 80089d2: 08db lsrs r3, r3, #3 DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | 80089d4: 431a orrs r2, r3 DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); 80089d6: 687b ldr r3, [r7, #4] 80089d8: 6a1b ldr r3, [r3, #32] 80089da: 091b lsrs r3, r3, #4 DMA_TO_BDMA_MODE(hdma->Init.Mode) | 80089dc: 4313 orrs r3, r2 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | 80089de: 697a ldr r2, [r7, #20] 80089e0: 4313 orrs r3, r2 80089e2: 617b str r3, [r7, #20] /* Write to DMA Channel CR register */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; 80089e4: 687b ldr r3, [r7, #4] 80089e6: 681b ldr r3, [r3, #0] 80089e8: 697a ldr r2, [r7, #20] 80089ea: 601a str r2, [r3, #0] /* calculation of the channel index */ hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; 80089ec: 687b ldr r3, [r7, #4] 80089ee: 681b ldr r3, [r3, #0] 80089f0: 461a mov r2, r3 80089f2: 4b6e ldr r3, [pc, #440] @ (8008bac ) 80089f4: 4413 add r3, r2 80089f6: 4a6e ldr r2, [pc, #440] @ (8008bb0 ) 80089f8: fba2 2303 umull r2, r3, r2, r3 80089fc: 091b lsrs r3, r3, #4 80089fe: 009a lsls r2, r3, #2 8008a00: 687b ldr r3, [r7, #4] 8008a02: 65da str r2, [r3, #92] @ 0x5c /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); 8008a04: 6878 ldr r0, [r7, #4] 8008a06: f002 f9a9 bl 800ad5c 8008a0a: 4603 mov r3, r0 8008a0c: 60fb str r3, [r7, #12] /* Clear all interrupt flags */ regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8008a0e: 687b ldr r3, [r7, #4] 8008a10: 6ddb ldr r3, [r3, #92] @ 0x5c 8008a12: f003 031f and.w r3, r3, #31 8008a16: 2201 movs r2, #1 8008a18: 409a lsls r2, r3 8008a1a: 68fb ldr r3, [r7, #12] 8008a1c: 605a str r2, [r3, #4] 8008a1e: e008 b.n 8008a32 } else { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; 8008a20: 687b ldr r3, [r7, #4] 8008a22: 2240 movs r2, #64 @ 0x40 8008a24: 655a str r2, [r3, #84] @ 0x54 hdma->State = HAL_DMA_STATE_ERROR; 8008a26: 687b ldr r3, [r7, #4] 8008a28: 2203 movs r2, #3 8008a2a: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_ERROR; 8008a2e: 2301 movs r3, #1 8008a30: e0b7 b.n 8008ba2 } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008a32: 687b ldr r3, [r7, #4] 8008a34: 681b ldr r3, [r3, #0] 8008a36: 4a5f ldr r2, [pc, #380] @ (8008bb4 ) 8008a38: 4293 cmp r3, r2 8008a3a: d072 beq.n 8008b22 8008a3c: 687b ldr r3, [r7, #4] 8008a3e: 681b ldr r3, [r3, #0] 8008a40: 4a5d ldr r2, [pc, #372] @ (8008bb8 ) 8008a42: 4293 cmp r3, r2 8008a44: d06d beq.n 8008b22 8008a46: 687b ldr r3, [r7, #4] 8008a48: 681b ldr r3, [r3, #0] 8008a4a: 4a5c ldr r2, [pc, #368] @ (8008bbc ) 8008a4c: 4293 cmp r3, r2 8008a4e: d068 beq.n 8008b22 8008a50: 687b ldr r3, [r7, #4] 8008a52: 681b ldr r3, [r3, #0] 8008a54: 4a5a ldr r2, [pc, #360] @ (8008bc0 ) 8008a56: 4293 cmp r3, r2 8008a58: d063 beq.n 8008b22 8008a5a: 687b ldr r3, [r7, #4] 8008a5c: 681b ldr r3, [r3, #0] 8008a5e: 4a59 ldr r2, [pc, #356] @ (8008bc4 ) 8008a60: 4293 cmp r3, r2 8008a62: d05e beq.n 8008b22 8008a64: 687b ldr r3, [r7, #4] 8008a66: 681b ldr r3, [r3, #0] 8008a68: 4a57 ldr r2, [pc, #348] @ (8008bc8 ) 8008a6a: 4293 cmp r3, r2 8008a6c: d059 beq.n 8008b22 8008a6e: 687b ldr r3, [r7, #4] 8008a70: 681b ldr r3, [r3, #0] 8008a72: 4a56 ldr r2, [pc, #344] @ (8008bcc ) 8008a74: 4293 cmp r3, r2 8008a76: d054 beq.n 8008b22 8008a78: 687b ldr r3, [r7, #4] 8008a7a: 681b ldr r3, [r3, #0] 8008a7c: 4a54 ldr r2, [pc, #336] @ (8008bd0 ) 8008a7e: 4293 cmp r3, r2 8008a80: d04f beq.n 8008b22 8008a82: 687b ldr r3, [r7, #4] 8008a84: 681b ldr r3, [r3, #0] 8008a86: 4a53 ldr r2, [pc, #332] @ (8008bd4 ) 8008a88: 4293 cmp r3, r2 8008a8a: d04a beq.n 8008b22 8008a8c: 687b ldr r3, [r7, #4] 8008a8e: 681b ldr r3, [r3, #0] 8008a90: 4a51 ldr r2, [pc, #324] @ (8008bd8 ) 8008a92: 4293 cmp r3, r2 8008a94: d045 beq.n 8008b22 8008a96: 687b ldr r3, [r7, #4] 8008a98: 681b ldr r3, [r3, #0] 8008a9a: 4a50 ldr r2, [pc, #320] @ (8008bdc ) 8008a9c: 4293 cmp r3, r2 8008a9e: d040 beq.n 8008b22 8008aa0: 687b ldr r3, [r7, #4] 8008aa2: 681b ldr r3, [r3, #0] 8008aa4: 4a4e ldr r2, [pc, #312] @ (8008be0 ) 8008aa6: 4293 cmp r3, r2 8008aa8: d03b beq.n 8008b22 8008aaa: 687b ldr r3, [r7, #4] 8008aac: 681b ldr r3, [r3, #0] 8008aae: 4a4d ldr r2, [pc, #308] @ (8008be4 ) 8008ab0: 4293 cmp r3, r2 8008ab2: d036 beq.n 8008b22 8008ab4: 687b ldr r3, [r7, #4] 8008ab6: 681b ldr r3, [r3, #0] 8008ab8: 4a4b ldr r2, [pc, #300] @ (8008be8 ) 8008aba: 4293 cmp r3, r2 8008abc: d031 beq.n 8008b22 8008abe: 687b ldr r3, [r7, #4] 8008ac0: 681b ldr r3, [r3, #0] 8008ac2: 4a4a ldr r2, [pc, #296] @ (8008bec ) 8008ac4: 4293 cmp r3, r2 8008ac6: d02c beq.n 8008b22 8008ac8: 687b ldr r3, [r7, #4] 8008aca: 681b ldr r3, [r3, #0] 8008acc: 4a48 ldr r2, [pc, #288] @ (8008bf0 ) 8008ace: 4293 cmp r3, r2 8008ad0: d027 beq.n 8008b22 8008ad2: 687b ldr r3, [r7, #4] 8008ad4: 681b ldr r3, [r3, #0] 8008ad6: 4a47 ldr r2, [pc, #284] @ (8008bf4 ) 8008ad8: 4293 cmp r3, r2 8008ada: d022 beq.n 8008b22 8008adc: 687b ldr r3, [r7, #4] 8008ade: 681b ldr r3, [r3, #0] 8008ae0: 4a45 ldr r2, [pc, #276] @ (8008bf8 ) 8008ae2: 4293 cmp r3, r2 8008ae4: d01d beq.n 8008b22 8008ae6: 687b ldr r3, [r7, #4] 8008ae8: 681b ldr r3, [r3, #0] 8008aea: 4a44 ldr r2, [pc, #272] @ (8008bfc ) 8008aec: 4293 cmp r3, r2 8008aee: d018 beq.n 8008b22 8008af0: 687b ldr r3, [r7, #4] 8008af2: 681b ldr r3, [r3, #0] 8008af4: 4a42 ldr r2, [pc, #264] @ (8008c00 ) 8008af6: 4293 cmp r3, r2 8008af8: d013 beq.n 8008b22 8008afa: 687b ldr r3, [r7, #4] 8008afc: 681b ldr r3, [r3, #0] 8008afe: 4a41 ldr r2, [pc, #260] @ (8008c04 ) 8008b00: 4293 cmp r3, r2 8008b02: d00e beq.n 8008b22 8008b04: 687b ldr r3, [r7, #4] 8008b06: 681b ldr r3, [r3, #0] 8008b08: 4a3f ldr r2, [pc, #252] @ (8008c08 ) 8008b0a: 4293 cmp r3, r2 8008b0c: d009 beq.n 8008b22 8008b0e: 687b ldr r3, [r7, #4] 8008b10: 681b ldr r3, [r3, #0] 8008b12: 4a3e ldr r2, [pc, #248] @ (8008c0c ) 8008b14: 4293 cmp r3, r2 8008b16: d004 beq.n 8008b22 8008b18: 687b ldr r3, [r7, #4] 8008b1a: 681b ldr r3, [r3, #0] 8008b1c: 4a3c ldr r2, [pc, #240] @ (8008c10 ) 8008b1e: 4293 cmp r3, r2 8008b20: d101 bne.n 8008b26 8008b22: 2301 movs r3, #1 8008b24: e000 b.n 8008b28 8008b26: 2300 movs r3, #0 8008b28: 2b00 cmp r3, #0 8008b2a: d032 beq.n 8008b92 { /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 8008b2c: 6878 ldr r0, [r7, #4] 8008b2e: f002 fa43 bl 800afb8 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 8008b32: 687b ldr r3, [r7, #4] 8008b34: 689b ldr r3, [r3, #8] 8008b36: 2b80 cmp r3, #128 @ 0x80 8008b38: d102 bne.n 8008b40 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 8008b3a: 687b ldr r3, [r7, #4] 8008b3c: 2200 movs r2, #0 8008b3e: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 8008b40: 687b ldr r3, [r7, #4] 8008b42: 685a ldr r2, [r3, #4] 8008b44: 687b ldr r3, [r7, #4] 8008b46: 6e1b ldr r3, [r3, #96] @ 0x60 8008b48: b2d2 uxtb r2, r2 8008b4a: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8008b4c: 687b ldr r3, [r7, #4] 8008b4e: 6e5b ldr r3, [r3, #100] @ 0x64 8008b50: 687a ldr r2, [r7, #4] 8008b52: 6e92 ldr r2, [r2, #104] @ 0x68 8008b54: 605a str r2, [r3, #4] /* Initialize parameters for DMAMUX request generator : if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 */ if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) 8008b56: 687b ldr r3, [r7, #4] 8008b58: 685b ldr r3, [r3, #4] 8008b5a: 2b00 cmp r3, #0 8008b5c: d010 beq.n 8008b80 8008b5e: 687b ldr r3, [r7, #4] 8008b60: 685b ldr r3, [r3, #4] 8008b62: 2b08 cmp r3, #8 8008b64: d80c bhi.n 8008b80 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 8008b66: 6878 ldr r0, [r7, #4] 8008b68: f002 fac0 bl 800b0ec /* Reset the DMAMUX request generator register */ hdma->DMAmuxRequestGen->RGCR = 0U; 8008b6c: 687b ldr r3, [r7, #4] 8008b6e: 6edb ldr r3, [r3, #108] @ 0x6c 8008b70: 2200 movs r2, #0 8008b72: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8008b74: 687b ldr r3, [r7, #4] 8008b76: 6f1b ldr r3, [r3, #112] @ 0x70 8008b78: 687a ldr r2, [r7, #4] 8008b7a: 6f52 ldr r2, [r2, #116] @ 0x74 8008b7c: 605a str r2, [r3, #4] 8008b7e: e008 b.n 8008b92 } else { hdma->DMAmuxRequestGen = 0U; 8008b80: 687b ldr r3, [r7, #4] 8008b82: 2200 movs r2, #0 8008b84: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = 0U; 8008b86: 687b ldr r3, [r7, #4] 8008b88: 2200 movs r2, #0 8008b8a: 671a str r2, [r3, #112] @ 0x70 hdma->DMAmuxRequestGenStatusMask = 0U; 8008b8c: 687b ldr r3, [r7, #4] 8008b8e: 2200 movs r2, #0 8008b90: 675a str r2, [r3, #116] @ 0x74 } } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008b92: 687b ldr r3, [r7, #4] 8008b94: 2200 movs r2, #0 8008b96: 655a str r2, [r3, #84] @ 0x54 /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8008b98: 687b ldr r3, [r7, #4] 8008b9a: 2201 movs r2, #1 8008b9c: f883 2035 strb.w r2, [r3, #53] @ 0x35 return HAL_OK; 8008ba0: 2300 movs r3, #0 } 8008ba2: 4618 mov r0, r3 8008ba4: 3718 adds r7, #24 8008ba6: 46bd mov sp, r7 8008ba8: bd80 pop {r7, pc} 8008baa: bf00 nop 8008bac: a7fdabf8 .word 0xa7fdabf8 8008bb0: cccccccd .word 0xcccccccd 8008bb4: 40020010 .word 0x40020010 8008bb8: 40020028 .word 0x40020028 8008bbc: 40020040 .word 0x40020040 8008bc0: 40020058 .word 0x40020058 8008bc4: 40020070 .word 0x40020070 8008bc8: 40020088 .word 0x40020088 8008bcc: 400200a0 .word 0x400200a0 8008bd0: 400200b8 .word 0x400200b8 8008bd4: 40020410 .word 0x40020410 8008bd8: 40020428 .word 0x40020428 8008bdc: 40020440 .word 0x40020440 8008be0: 40020458 .word 0x40020458 8008be4: 40020470 .word 0x40020470 8008be8: 40020488 .word 0x40020488 8008bec: 400204a0 .word 0x400204a0 8008bf0: 400204b8 .word 0x400204b8 8008bf4: 58025408 .word 0x58025408 8008bf8: 5802541c .word 0x5802541c 8008bfc: 58025430 .word 0x58025430 8008c00: 58025444 .word 0x58025444 8008c04: 58025458 .word 0x58025458 8008c08: 5802546c .word 0x5802546c 8008c0c: 58025480 .word 0x58025480 8008c10: 58025494 .word 0x58025494 08008c14 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8008c14: b580 push {r7, lr} 8008c16: b086 sub sp, #24 8008c18: af00 add r7, sp, #0 8008c1a: 60f8 str r0, [r7, #12] 8008c1c: 60b9 str r1, [r7, #8] 8008c1e: 607a str r2, [r7, #4] 8008c20: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8008c22: 2300 movs r3, #0 8008c24: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Check the DMA peripheral handle */ if(hdma == NULL) 8008c26: 68fb ldr r3, [r7, #12] 8008c28: 2b00 cmp r3, #0 8008c2a: d101 bne.n 8008c30 { return HAL_ERROR; 8008c2c: 2301 movs r3, #1 8008c2e: e226 b.n 800907e } /* Process locked */ __HAL_LOCK(hdma); 8008c30: 68fb ldr r3, [r7, #12] 8008c32: f893 3034 ldrb.w r3, [r3, #52] @ 0x34 8008c36: 2b01 cmp r3, #1 8008c38: d101 bne.n 8008c3e 8008c3a: 2302 movs r3, #2 8008c3c: e21f b.n 800907e 8008c3e: 68fb ldr r3, [r7, #12] 8008c40: 2201 movs r2, #1 8008c42: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(HAL_DMA_STATE_READY == hdma->State) 8008c46: 68fb ldr r3, [r7, #12] 8008c48: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8008c4c: b2db uxtb r3, r3 8008c4e: 2b01 cmp r3, #1 8008c50: f040 820a bne.w 8009068 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8008c54: 68fb ldr r3, [r7, #12] 8008c56: 2202 movs r2, #2 8008c58: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8008c5c: 68fb ldr r3, [r7, #12] 8008c5e: 2200 movs r2, #0 8008c60: 655a str r2, [r3, #84] @ 0x54 /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8008c62: 68fb ldr r3, [r7, #12] 8008c64: 681b ldr r3, [r3, #0] 8008c66: 4a68 ldr r2, [pc, #416] @ (8008e08 ) 8008c68: 4293 cmp r3, r2 8008c6a: d04a beq.n 8008d02 8008c6c: 68fb ldr r3, [r7, #12] 8008c6e: 681b ldr r3, [r3, #0] 8008c70: 4a66 ldr r2, [pc, #408] @ (8008e0c ) 8008c72: 4293 cmp r3, r2 8008c74: d045 beq.n 8008d02 8008c76: 68fb ldr r3, [r7, #12] 8008c78: 681b ldr r3, [r3, #0] 8008c7a: 4a65 ldr r2, [pc, #404] @ (8008e10 ) 8008c7c: 4293 cmp r3, r2 8008c7e: d040 beq.n 8008d02 8008c80: 68fb ldr r3, [r7, #12] 8008c82: 681b ldr r3, [r3, #0] 8008c84: 4a63 ldr r2, [pc, #396] @ (8008e14 ) 8008c86: 4293 cmp r3, r2 8008c88: d03b beq.n 8008d02 8008c8a: 68fb ldr r3, [r7, #12] 8008c8c: 681b ldr r3, [r3, #0] 8008c8e: 4a62 ldr r2, [pc, #392] @ (8008e18 ) 8008c90: 4293 cmp r3, r2 8008c92: d036 beq.n 8008d02 8008c94: 68fb ldr r3, [r7, #12] 8008c96: 681b ldr r3, [r3, #0] 8008c98: 4a60 ldr r2, [pc, #384] @ (8008e1c ) 8008c9a: 4293 cmp r3, r2 8008c9c: d031 beq.n 8008d02 8008c9e: 68fb ldr r3, [r7, #12] 8008ca0: 681b ldr r3, [r3, #0] 8008ca2: 4a5f ldr r2, [pc, #380] @ (8008e20 ) 8008ca4: 4293 cmp r3, r2 8008ca6: d02c beq.n 8008d02 8008ca8: 68fb ldr r3, [r7, #12] 8008caa: 681b ldr r3, [r3, #0] 8008cac: 4a5d ldr r2, [pc, #372] @ (8008e24 ) 8008cae: 4293 cmp r3, r2 8008cb0: d027 beq.n 8008d02 8008cb2: 68fb ldr r3, [r7, #12] 8008cb4: 681b ldr r3, [r3, #0] 8008cb6: 4a5c ldr r2, [pc, #368] @ (8008e28 ) 8008cb8: 4293 cmp r3, r2 8008cba: d022 beq.n 8008d02 8008cbc: 68fb ldr r3, [r7, #12] 8008cbe: 681b ldr r3, [r3, #0] 8008cc0: 4a5a ldr r2, [pc, #360] @ (8008e2c ) 8008cc2: 4293 cmp r3, r2 8008cc4: d01d beq.n 8008d02 8008cc6: 68fb ldr r3, [r7, #12] 8008cc8: 681b ldr r3, [r3, #0] 8008cca: 4a59 ldr r2, [pc, #356] @ (8008e30 ) 8008ccc: 4293 cmp r3, r2 8008cce: d018 beq.n 8008d02 8008cd0: 68fb ldr r3, [r7, #12] 8008cd2: 681b ldr r3, [r3, #0] 8008cd4: 4a57 ldr r2, [pc, #348] @ (8008e34 ) 8008cd6: 4293 cmp r3, r2 8008cd8: d013 beq.n 8008d02 8008cda: 68fb ldr r3, [r7, #12] 8008cdc: 681b ldr r3, [r3, #0] 8008cde: 4a56 ldr r2, [pc, #344] @ (8008e38 ) 8008ce0: 4293 cmp r3, r2 8008ce2: d00e beq.n 8008d02 8008ce4: 68fb ldr r3, [r7, #12] 8008ce6: 681b ldr r3, [r3, #0] 8008ce8: 4a54 ldr r2, [pc, #336] @ (8008e3c ) 8008cea: 4293 cmp r3, r2 8008cec: d009 beq.n 8008d02 8008cee: 68fb ldr r3, [r7, #12] 8008cf0: 681b ldr r3, [r3, #0] 8008cf2: 4a53 ldr r2, [pc, #332] @ (8008e40 ) 8008cf4: 4293 cmp r3, r2 8008cf6: d004 beq.n 8008d02 8008cf8: 68fb ldr r3, [r7, #12] 8008cfa: 681b ldr r3, [r3, #0] 8008cfc: 4a51 ldr r2, [pc, #324] @ (8008e44 ) 8008cfe: 4293 cmp r3, r2 8008d00: d108 bne.n 8008d14 8008d02: 68fb ldr r3, [r7, #12] 8008d04: 681b ldr r3, [r3, #0] 8008d06: 681a ldr r2, [r3, #0] 8008d08: 68fb ldr r3, [r7, #12] 8008d0a: 681b ldr r3, [r3, #0] 8008d0c: f022 0201 bic.w r2, r2, #1 8008d10: 601a str r2, [r3, #0] 8008d12: e007 b.n 8008d24 8008d14: 68fb ldr r3, [r7, #12] 8008d16: 681b ldr r3, [r3, #0] 8008d18: 681a ldr r2, [r3, #0] 8008d1a: 68fb ldr r3, [r7, #12] 8008d1c: 681b ldr r3, [r3, #0] 8008d1e: f022 0201 bic.w r2, r2, #1 8008d22: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8008d24: 683b ldr r3, [r7, #0] 8008d26: 687a ldr r2, [r7, #4] 8008d28: 68b9 ldr r1, [r7, #8] 8008d2a: 68f8 ldr r0, [r7, #12] 8008d2c: f001 fe6a bl 800aa04 if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8008d30: 68fb ldr r3, [r7, #12] 8008d32: 681b ldr r3, [r3, #0] 8008d34: 4a34 ldr r2, [pc, #208] @ (8008e08 ) 8008d36: 4293 cmp r3, r2 8008d38: d04a beq.n 8008dd0 8008d3a: 68fb ldr r3, [r7, #12] 8008d3c: 681b ldr r3, [r3, #0] 8008d3e: 4a33 ldr r2, [pc, #204] @ (8008e0c ) 8008d40: 4293 cmp r3, r2 8008d42: d045 beq.n 8008dd0 8008d44: 68fb ldr r3, [r7, #12] 8008d46: 681b ldr r3, [r3, #0] 8008d48: 4a31 ldr r2, [pc, #196] @ (8008e10 ) 8008d4a: 4293 cmp r3, r2 8008d4c: d040 beq.n 8008dd0 8008d4e: 68fb ldr r3, [r7, #12] 8008d50: 681b ldr r3, [r3, #0] 8008d52: 4a30 ldr r2, [pc, #192] @ (8008e14 ) 8008d54: 4293 cmp r3, r2 8008d56: d03b beq.n 8008dd0 8008d58: 68fb ldr r3, [r7, #12] 8008d5a: 681b ldr r3, [r3, #0] 8008d5c: 4a2e ldr r2, [pc, #184] @ (8008e18 ) 8008d5e: 4293 cmp r3, r2 8008d60: d036 beq.n 8008dd0 8008d62: 68fb ldr r3, [r7, #12] 8008d64: 681b ldr r3, [r3, #0] 8008d66: 4a2d ldr r2, [pc, #180] @ (8008e1c ) 8008d68: 4293 cmp r3, r2 8008d6a: d031 beq.n 8008dd0 8008d6c: 68fb ldr r3, [r7, #12] 8008d6e: 681b ldr r3, [r3, #0] 8008d70: 4a2b ldr r2, [pc, #172] @ (8008e20 ) 8008d72: 4293 cmp r3, r2 8008d74: d02c beq.n 8008dd0 8008d76: 68fb ldr r3, [r7, #12] 8008d78: 681b ldr r3, [r3, #0] 8008d7a: 4a2a ldr r2, [pc, #168] @ (8008e24 ) 8008d7c: 4293 cmp r3, r2 8008d7e: d027 beq.n 8008dd0 8008d80: 68fb ldr r3, [r7, #12] 8008d82: 681b ldr r3, [r3, #0] 8008d84: 4a28 ldr r2, [pc, #160] @ (8008e28 ) 8008d86: 4293 cmp r3, r2 8008d88: d022 beq.n 8008dd0 8008d8a: 68fb ldr r3, [r7, #12] 8008d8c: 681b ldr r3, [r3, #0] 8008d8e: 4a27 ldr r2, [pc, #156] @ (8008e2c ) 8008d90: 4293 cmp r3, r2 8008d92: d01d beq.n 8008dd0 8008d94: 68fb ldr r3, [r7, #12] 8008d96: 681b ldr r3, [r3, #0] 8008d98: 4a25 ldr r2, [pc, #148] @ (8008e30 ) 8008d9a: 4293 cmp r3, r2 8008d9c: d018 beq.n 8008dd0 8008d9e: 68fb ldr r3, [r7, #12] 8008da0: 681b ldr r3, [r3, #0] 8008da2: 4a24 ldr r2, [pc, #144] @ (8008e34 ) 8008da4: 4293 cmp r3, r2 8008da6: d013 beq.n 8008dd0 8008da8: 68fb ldr r3, [r7, #12] 8008daa: 681b ldr r3, [r3, #0] 8008dac: 4a22 ldr r2, [pc, #136] @ (8008e38 ) 8008dae: 4293 cmp r3, r2 8008db0: d00e beq.n 8008dd0 8008db2: 68fb ldr r3, [r7, #12] 8008db4: 681b ldr r3, [r3, #0] 8008db6: 4a21 ldr r2, [pc, #132] @ (8008e3c ) 8008db8: 4293 cmp r3, r2 8008dba: d009 beq.n 8008dd0 8008dbc: 68fb ldr r3, [r7, #12] 8008dbe: 681b ldr r3, [r3, #0] 8008dc0: 4a1f ldr r2, [pc, #124] @ (8008e40 ) 8008dc2: 4293 cmp r3, r2 8008dc4: d004 beq.n 8008dd0 8008dc6: 68fb ldr r3, [r7, #12] 8008dc8: 681b ldr r3, [r3, #0] 8008dca: 4a1e ldr r2, [pc, #120] @ (8008e44 ) 8008dcc: 4293 cmp r3, r2 8008dce: d101 bne.n 8008dd4 8008dd0: 2301 movs r3, #1 8008dd2: e000 b.n 8008dd6 8008dd4: 2300 movs r3, #0 8008dd6: 2b00 cmp r3, #0 8008dd8: d036 beq.n 8008e48 { /* Enable Common interrupts*/ MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); 8008dda: 68fb ldr r3, [r7, #12] 8008ddc: 681b ldr r3, [r3, #0] 8008dde: 681b ldr r3, [r3, #0] 8008de0: f023 021e bic.w r2, r3, #30 8008de4: 68fb ldr r3, [r7, #12] 8008de6: 681b ldr r3, [r3, #0] 8008de8: f042 0216 orr.w r2, r2, #22 8008dec: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008dee: 68fb ldr r3, [r7, #12] 8008df0: 6c1b ldr r3, [r3, #64] @ 0x40 8008df2: 2b00 cmp r3, #0 8008df4: d03e beq.n 8008e74 { /* Enable Half Transfer IT if corresponding Callback is set */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; 8008df6: 68fb ldr r3, [r7, #12] 8008df8: 681b ldr r3, [r3, #0] 8008dfa: 681a ldr r2, [r3, #0] 8008dfc: 68fb ldr r3, [r7, #12] 8008dfe: 681b ldr r3, [r3, #0] 8008e00: f042 0208 orr.w r2, r2, #8 8008e04: 601a str r2, [r3, #0] 8008e06: e035 b.n 8008e74 8008e08: 40020010 .word 0x40020010 8008e0c: 40020028 .word 0x40020028 8008e10: 40020040 .word 0x40020040 8008e14: 40020058 .word 0x40020058 8008e18: 40020070 .word 0x40020070 8008e1c: 40020088 .word 0x40020088 8008e20: 400200a0 .word 0x400200a0 8008e24: 400200b8 .word 0x400200b8 8008e28: 40020410 .word 0x40020410 8008e2c: 40020428 .word 0x40020428 8008e30: 40020440 .word 0x40020440 8008e34: 40020458 .word 0x40020458 8008e38: 40020470 .word 0x40020470 8008e3c: 40020488 .word 0x40020488 8008e40: 400204a0 .word 0x400204a0 8008e44: 400204b8 .word 0x400204b8 } } else /* BDMA channel */ { /* Enable Common interrupts */ MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); 8008e48: 68fb ldr r3, [r7, #12] 8008e4a: 681b ldr r3, [r3, #0] 8008e4c: 681b ldr r3, [r3, #0] 8008e4e: f023 020e bic.w r2, r3, #14 8008e52: 68fb ldr r3, [r7, #12] 8008e54: 681b ldr r3, [r3, #0] 8008e56: f042 020a orr.w r2, r2, #10 8008e5a: 601a str r2, [r3, #0] if(hdma->XferHalfCpltCallback != NULL) 8008e5c: 68fb ldr r3, [r7, #12] 8008e5e: 6c1b ldr r3, [r3, #64] @ 0x40 8008e60: 2b00 cmp r3, #0 8008e62: d007 beq.n 8008e74 { /*Enable Half Transfer IT if corresponding Callback is set */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; 8008e64: 68fb ldr r3, [r7, #12] 8008e66: 681b ldr r3, [r3, #0] 8008e68: 681a ldr r2, [r3, #0] 8008e6a: 68fb ldr r3, [r7, #12] 8008e6c: 681b ldr r3, [r3, #0] 8008e6e: f042 0204 orr.w r2, r2, #4 8008e72: 601a str r2, [r3, #0] } } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8008e74: 68fb ldr r3, [r7, #12] 8008e76: 681b ldr r3, [r3, #0] 8008e78: 4a83 ldr r2, [pc, #524] @ (8009088 ) 8008e7a: 4293 cmp r3, r2 8008e7c: d072 beq.n 8008f64 8008e7e: 68fb ldr r3, [r7, #12] 8008e80: 681b ldr r3, [r3, #0] 8008e82: 4a82 ldr r2, [pc, #520] @ (800908c ) 8008e84: 4293 cmp r3, r2 8008e86: d06d beq.n 8008f64 8008e88: 68fb ldr r3, [r7, #12] 8008e8a: 681b ldr r3, [r3, #0] 8008e8c: 4a80 ldr r2, [pc, #512] @ (8009090 ) 8008e8e: 4293 cmp r3, r2 8008e90: d068 beq.n 8008f64 8008e92: 68fb ldr r3, [r7, #12] 8008e94: 681b ldr r3, [r3, #0] 8008e96: 4a7f ldr r2, [pc, #508] @ (8009094 ) 8008e98: 4293 cmp r3, r2 8008e9a: d063 beq.n 8008f64 8008e9c: 68fb ldr r3, [r7, #12] 8008e9e: 681b ldr r3, [r3, #0] 8008ea0: 4a7d ldr r2, [pc, #500] @ (8009098 ) 8008ea2: 4293 cmp r3, r2 8008ea4: d05e beq.n 8008f64 8008ea6: 68fb ldr r3, [r7, #12] 8008ea8: 681b ldr r3, [r3, #0] 8008eaa: 4a7c ldr r2, [pc, #496] @ (800909c ) 8008eac: 4293 cmp r3, r2 8008eae: d059 beq.n 8008f64 8008eb0: 68fb ldr r3, [r7, #12] 8008eb2: 681b ldr r3, [r3, #0] 8008eb4: 4a7a ldr r2, [pc, #488] @ (80090a0 ) 8008eb6: 4293 cmp r3, r2 8008eb8: d054 beq.n 8008f64 8008eba: 68fb ldr r3, [r7, #12] 8008ebc: 681b ldr r3, [r3, #0] 8008ebe: 4a79 ldr r2, [pc, #484] @ (80090a4 ) 8008ec0: 4293 cmp r3, r2 8008ec2: d04f beq.n 8008f64 8008ec4: 68fb ldr r3, [r7, #12] 8008ec6: 681b ldr r3, [r3, #0] 8008ec8: 4a77 ldr r2, [pc, #476] @ (80090a8 ) 8008eca: 4293 cmp r3, r2 8008ecc: d04a beq.n 8008f64 8008ece: 68fb ldr r3, [r7, #12] 8008ed0: 681b ldr r3, [r3, #0] 8008ed2: 4a76 ldr r2, [pc, #472] @ (80090ac ) 8008ed4: 4293 cmp r3, r2 8008ed6: d045 beq.n 8008f64 8008ed8: 68fb ldr r3, [r7, #12] 8008eda: 681b ldr r3, [r3, #0] 8008edc: 4a74 ldr r2, [pc, #464] @ (80090b0 ) 8008ede: 4293 cmp r3, r2 8008ee0: d040 beq.n 8008f64 8008ee2: 68fb ldr r3, [r7, #12] 8008ee4: 681b ldr r3, [r3, #0] 8008ee6: 4a73 ldr r2, [pc, #460] @ (80090b4 ) 8008ee8: 4293 cmp r3, r2 8008eea: d03b beq.n 8008f64 8008eec: 68fb ldr r3, [r7, #12] 8008eee: 681b ldr r3, [r3, #0] 8008ef0: 4a71 ldr r2, [pc, #452] @ (80090b8 ) 8008ef2: 4293 cmp r3, r2 8008ef4: d036 beq.n 8008f64 8008ef6: 68fb ldr r3, [r7, #12] 8008ef8: 681b ldr r3, [r3, #0] 8008efa: 4a70 ldr r2, [pc, #448] @ (80090bc ) 8008efc: 4293 cmp r3, r2 8008efe: d031 beq.n 8008f64 8008f00: 68fb ldr r3, [r7, #12] 8008f02: 681b ldr r3, [r3, #0] 8008f04: 4a6e ldr r2, [pc, #440] @ (80090c0 ) 8008f06: 4293 cmp r3, r2 8008f08: d02c beq.n 8008f64 8008f0a: 68fb ldr r3, [r7, #12] 8008f0c: 681b ldr r3, [r3, #0] 8008f0e: 4a6d ldr r2, [pc, #436] @ (80090c4 ) 8008f10: 4293 cmp r3, r2 8008f12: d027 beq.n 8008f64 8008f14: 68fb ldr r3, [r7, #12] 8008f16: 681b ldr r3, [r3, #0] 8008f18: 4a6b ldr r2, [pc, #428] @ (80090c8 ) 8008f1a: 4293 cmp r3, r2 8008f1c: d022 beq.n 8008f64 8008f1e: 68fb ldr r3, [r7, #12] 8008f20: 681b ldr r3, [r3, #0] 8008f22: 4a6a ldr r2, [pc, #424] @ (80090cc ) 8008f24: 4293 cmp r3, r2 8008f26: d01d beq.n 8008f64 8008f28: 68fb ldr r3, [r7, #12] 8008f2a: 681b ldr r3, [r3, #0] 8008f2c: 4a68 ldr r2, [pc, #416] @ (80090d0 ) 8008f2e: 4293 cmp r3, r2 8008f30: d018 beq.n 8008f64 8008f32: 68fb ldr r3, [r7, #12] 8008f34: 681b ldr r3, [r3, #0] 8008f36: 4a67 ldr r2, [pc, #412] @ (80090d4 ) 8008f38: 4293 cmp r3, r2 8008f3a: d013 beq.n 8008f64 8008f3c: 68fb ldr r3, [r7, #12] 8008f3e: 681b ldr r3, [r3, #0] 8008f40: 4a65 ldr r2, [pc, #404] @ (80090d8 ) 8008f42: 4293 cmp r3, r2 8008f44: d00e beq.n 8008f64 8008f46: 68fb ldr r3, [r7, #12] 8008f48: 681b ldr r3, [r3, #0] 8008f4a: 4a64 ldr r2, [pc, #400] @ (80090dc ) 8008f4c: 4293 cmp r3, r2 8008f4e: d009 beq.n 8008f64 8008f50: 68fb ldr r3, [r7, #12] 8008f52: 681b ldr r3, [r3, #0] 8008f54: 4a62 ldr r2, [pc, #392] @ (80090e0 ) 8008f56: 4293 cmp r3, r2 8008f58: d004 beq.n 8008f64 8008f5a: 68fb ldr r3, [r7, #12] 8008f5c: 681b ldr r3, [r3, #0] 8008f5e: 4a61 ldr r2, [pc, #388] @ (80090e4 ) 8008f60: 4293 cmp r3, r2 8008f62: d101 bne.n 8008f68 8008f64: 2301 movs r3, #1 8008f66: e000 b.n 8008f6a 8008f68: 2300 movs r3, #0 8008f6a: 2b00 cmp r3, #0 8008f6c: d01a beq.n 8008fa4 { /* Check if DMAMUX Synchronization is enabled */ if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 8008f6e: 68fb ldr r3, [r7, #12] 8008f70: 6e1b ldr r3, [r3, #96] @ 0x60 8008f72: 681b ldr r3, [r3, #0] 8008f74: f403 3380 and.w r3, r3, #65536 @ 0x10000 8008f78: 2b00 cmp r3, #0 8008f7a: d007 beq.n 8008f8c { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 8008f7c: 68fb ldr r3, [r7, #12] 8008f7e: 6e1b ldr r3, [r3, #96] @ 0x60 8008f80: 681a ldr r2, [r3, #0] 8008f82: 68fb ldr r3, [r7, #12] 8008f84: 6e1b ldr r3, [r3, #96] @ 0x60 8008f86: f442 7280 orr.w r2, r2, #256 @ 0x100 8008f8a: 601a str r2, [r3, #0] } if(hdma->DMAmuxRequestGen != 0U) 8008f8c: 68fb ldr r3, [r7, #12] 8008f8e: 6edb ldr r3, [r3, #108] @ 0x6c 8008f90: 2b00 cmp r3, #0 8008f92: d007 beq.n 8008fa4 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8008f94: 68fb ldr r3, [r7, #12] 8008f96: 6edb ldr r3, [r3, #108] @ 0x6c 8008f98: 681a ldr r2, [r3, #0] 8008f9a: 68fb ldr r3, [r7, #12] 8008f9c: 6edb ldr r3, [r3, #108] @ 0x6c 8008f9e: f442 7280 orr.w r2, r2, #256 @ 0x100 8008fa2: 601a str r2, [r3, #0] } } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8008fa4: 68fb ldr r3, [r7, #12] 8008fa6: 681b ldr r3, [r3, #0] 8008fa8: 4a37 ldr r2, [pc, #220] @ (8009088 ) 8008faa: 4293 cmp r3, r2 8008fac: d04a beq.n 8009044 8008fae: 68fb ldr r3, [r7, #12] 8008fb0: 681b ldr r3, [r3, #0] 8008fb2: 4a36 ldr r2, [pc, #216] @ (800908c ) 8008fb4: 4293 cmp r3, r2 8008fb6: d045 beq.n 8009044 8008fb8: 68fb ldr r3, [r7, #12] 8008fba: 681b ldr r3, [r3, #0] 8008fbc: 4a34 ldr r2, [pc, #208] @ (8009090 ) 8008fbe: 4293 cmp r3, r2 8008fc0: d040 beq.n 8009044 8008fc2: 68fb ldr r3, [r7, #12] 8008fc4: 681b ldr r3, [r3, #0] 8008fc6: 4a33 ldr r2, [pc, #204] @ (8009094 ) 8008fc8: 4293 cmp r3, r2 8008fca: d03b beq.n 8009044 8008fcc: 68fb ldr r3, [r7, #12] 8008fce: 681b ldr r3, [r3, #0] 8008fd0: 4a31 ldr r2, [pc, #196] @ (8009098 ) 8008fd2: 4293 cmp r3, r2 8008fd4: d036 beq.n 8009044 8008fd6: 68fb ldr r3, [r7, #12] 8008fd8: 681b ldr r3, [r3, #0] 8008fda: 4a30 ldr r2, [pc, #192] @ (800909c ) 8008fdc: 4293 cmp r3, r2 8008fde: d031 beq.n 8009044 8008fe0: 68fb ldr r3, [r7, #12] 8008fe2: 681b ldr r3, [r3, #0] 8008fe4: 4a2e ldr r2, [pc, #184] @ (80090a0 ) 8008fe6: 4293 cmp r3, r2 8008fe8: d02c beq.n 8009044 8008fea: 68fb ldr r3, [r7, #12] 8008fec: 681b ldr r3, [r3, #0] 8008fee: 4a2d ldr r2, [pc, #180] @ (80090a4 ) 8008ff0: 4293 cmp r3, r2 8008ff2: d027 beq.n 8009044 8008ff4: 68fb ldr r3, [r7, #12] 8008ff6: 681b ldr r3, [r3, #0] 8008ff8: 4a2b ldr r2, [pc, #172] @ (80090a8 ) 8008ffa: 4293 cmp r3, r2 8008ffc: d022 beq.n 8009044 8008ffe: 68fb ldr r3, [r7, #12] 8009000: 681b ldr r3, [r3, #0] 8009002: 4a2a ldr r2, [pc, #168] @ (80090ac ) 8009004: 4293 cmp r3, r2 8009006: d01d beq.n 8009044 8009008: 68fb ldr r3, [r7, #12] 800900a: 681b ldr r3, [r3, #0] 800900c: 4a28 ldr r2, [pc, #160] @ (80090b0 ) 800900e: 4293 cmp r3, r2 8009010: d018 beq.n 8009044 8009012: 68fb ldr r3, [r7, #12] 8009014: 681b ldr r3, [r3, #0] 8009016: 4a27 ldr r2, [pc, #156] @ (80090b4 ) 8009018: 4293 cmp r3, r2 800901a: d013 beq.n 8009044 800901c: 68fb ldr r3, [r7, #12] 800901e: 681b ldr r3, [r3, #0] 8009020: 4a25 ldr r2, [pc, #148] @ (80090b8 ) 8009022: 4293 cmp r3, r2 8009024: d00e beq.n 8009044 8009026: 68fb ldr r3, [r7, #12] 8009028: 681b ldr r3, [r3, #0] 800902a: 4a24 ldr r2, [pc, #144] @ (80090bc ) 800902c: 4293 cmp r3, r2 800902e: d009 beq.n 8009044 8009030: 68fb ldr r3, [r7, #12] 8009032: 681b ldr r3, [r3, #0] 8009034: 4a22 ldr r2, [pc, #136] @ (80090c0 ) 8009036: 4293 cmp r3, r2 8009038: d004 beq.n 8009044 800903a: 68fb ldr r3, [r7, #12] 800903c: 681b ldr r3, [r3, #0] 800903e: 4a21 ldr r2, [pc, #132] @ (80090c4 ) 8009040: 4293 cmp r3, r2 8009042: d108 bne.n 8009056 8009044: 68fb ldr r3, [r7, #12] 8009046: 681b ldr r3, [r3, #0] 8009048: 681a ldr r2, [r3, #0] 800904a: 68fb ldr r3, [r7, #12] 800904c: 681b ldr r3, [r3, #0] 800904e: f042 0201 orr.w r2, r2, #1 8009052: 601a str r2, [r3, #0] 8009054: e012 b.n 800907c 8009056: 68fb ldr r3, [r7, #12] 8009058: 681b ldr r3, [r3, #0] 800905a: 681a ldr r2, [r3, #0] 800905c: 68fb ldr r3, [r7, #12] 800905e: 681b ldr r3, [r3, #0] 8009060: f042 0201 orr.w r2, r2, #1 8009064: 601a str r2, [r3, #0] 8009066: e009 b.n 800907c } else { /* Set the error code to busy */ hdma->ErrorCode = HAL_DMA_ERROR_BUSY; 8009068: 68fb ldr r3, [r7, #12] 800906a: f44f 6200 mov.w r2, #2048 @ 0x800 800906e: 655a str r2, [r3, #84] @ 0x54 /* Process unlocked */ __HAL_UNLOCK(hdma); 8009070: 68fb ldr r3, [r7, #12] 8009072: 2200 movs r2, #0 8009074: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Return error status */ status = HAL_ERROR; 8009078: 2301 movs r3, #1 800907a: 75fb strb r3, [r7, #23] } return status; 800907c: 7dfb ldrb r3, [r7, #23] } 800907e: 4618 mov r0, r3 8009080: 3718 adds r7, #24 8009082: 46bd mov sp, r7 8009084: bd80 pop {r7, pc} 8009086: bf00 nop 8009088: 40020010 .word 0x40020010 800908c: 40020028 .word 0x40020028 8009090: 40020040 .word 0x40020040 8009094: 40020058 .word 0x40020058 8009098: 40020070 .word 0x40020070 800909c: 40020088 .word 0x40020088 80090a0: 400200a0 .word 0x400200a0 80090a4: 400200b8 .word 0x400200b8 80090a8: 40020410 .word 0x40020410 80090ac: 40020428 .word 0x40020428 80090b0: 40020440 .word 0x40020440 80090b4: 40020458 .word 0x40020458 80090b8: 40020470 .word 0x40020470 80090bc: 40020488 .word 0x40020488 80090c0: 400204a0 .word 0x400204a0 80090c4: 400204b8 .word 0x400204b8 80090c8: 58025408 .word 0x58025408 80090cc: 5802541c .word 0x5802541c 80090d0: 58025430 .word 0x58025430 80090d4: 58025444 .word 0x58025444 80090d8: 58025458 .word 0x58025458 80090dc: 5802546c .word 0x5802546c 80090e0: 58025480 .word 0x58025480 80090e4: 58025494 .word 0x58025494 080090e8 : * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { 80090e8: b580 push {r7, lr} 80090ea: b086 sub sp, #24 80090ec: af00 add r7, sp, #0 80090ee: 6078 str r0, [r7, #4] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma; BDMA_Base_Registers *regs_bdma; const __IO uint32_t *enableRegister; uint32_t tickstart = HAL_GetTick(); 80090f0: f7fc fe98 bl 8005e24 80090f4: 6138 str r0, [r7, #16] /* Check the DMA peripheral handle */ if(hdma == NULL) 80090f6: 687b ldr r3, [r7, #4] 80090f8: 2b00 cmp r3, #0 80090fa: d101 bne.n 8009100 { return HAL_ERROR; 80090fc: 2301 movs r3, #1 80090fe: e2dc b.n 80096ba } /* Check the DMA peripheral state */ if(hdma->State != HAL_DMA_STATE_BUSY) 8009100: 687b ldr r3, [r7, #4] 8009102: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8009106: b2db uxtb r3, r3 8009108: 2b02 cmp r3, #2 800910a: d008 beq.n 800911e { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 800910c: 687b ldr r3, [r7, #4] 800910e: 2280 movs r2, #128 @ 0x80 8009110: 655a str r2, [r3, #84] @ 0x54 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009112: 687b ldr r3, [r7, #4] 8009114: 2200 movs r2, #0 8009116: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 800911a: 2301 movs r3, #1 800911c: e2cd b.n 80096ba } else { /* Disable all the transfer interrupts */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800911e: 687b ldr r3, [r7, #4] 8009120: 681b ldr r3, [r3, #0] 8009122: 4a76 ldr r2, [pc, #472] @ (80092fc ) 8009124: 4293 cmp r3, r2 8009126: d04a beq.n 80091be 8009128: 687b ldr r3, [r7, #4] 800912a: 681b ldr r3, [r3, #0] 800912c: 4a74 ldr r2, [pc, #464] @ (8009300 ) 800912e: 4293 cmp r3, r2 8009130: d045 beq.n 80091be 8009132: 687b ldr r3, [r7, #4] 8009134: 681b ldr r3, [r3, #0] 8009136: 4a73 ldr r2, [pc, #460] @ (8009304 ) 8009138: 4293 cmp r3, r2 800913a: d040 beq.n 80091be 800913c: 687b ldr r3, [r7, #4] 800913e: 681b ldr r3, [r3, #0] 8009140: 4a71 ldr r2, [pc, #452] @ (8009308 ) 8009142: 4293 cmp r3, r2 8009144: d03b beq.n 80091be 8009146: 687b ldr r3, [r7, #4] 8009148: 681b ldr r3, [r3, #0] 800914a: 4a70 ldr r2, [pc, #448] @ (800930c ) 800914c: 4293 cmp r3, r2 800914e: d036 beq.n 80091be 8009150: 687b ldr r3, [r7, #4] 8009152: 681b ldr r3, [r3, #0] 8009154: 4a6e ldr r2, [pc, #440] @ (8009310 ) 8009156: 4293 cmp r3, r2 8009158: d031 beq.n 80091be 800915a: 687b ldr r3, [r7, #4] 800915c: 681b ldr r3, [r3, #0] 800915e: 4a6d ldr r2, [pc, #436] @ (8009314 ) 8009160: 4293 cmp r3, r2 8009162: d02c beq.n 80091be 8009164: 687b ldr r3, [r7, #4] 8009166: 681b ldr r3, [r3, #0] 8009168: 4a6b ldr r2, [pc, #428] @ (8009318 ) 800916a: 4293 cmp r3, r2 800916c: d027 beq.n 80091be 800916e: 687b ldr r3, [r7, #4] 8009170: 681b ldr r3, [r3, #0] 8009172: 4a6a ldr r2, [pc, #424] @ (800931c ) 8009174: 4293 cmp r3, r2 8009176: d022 beq.n 80091be 8009178: 687b ldr r3, [r7, #4] 800917a: 681b ldr r3, [r3, #0] 800917c: 4a68 ldr r2, [pc, #416] @ (8009320 ) 800917e: 4293 cmp r3, r2 8009180: d01d beq.n 80091be 8009182: 687b ldr r3, [r7, #4] 8009184: 681b ldr r3, [r3, #0] 8009186: 4a67 ldr r2, [pc, #412] @ (8009324 ) 8009188: 4293 cmp r3, r2 800918a: d018 beq.n 80091be 800918c: 687b ldr r3, [r7, #4] 800918e: 681b ldr r3, [r3, #0] 8009190: 4a65 ldr r2, [pc, #404] @ (8009328 ) 8009192: 4293 cmp r3, r2 8009194: d013 beq.n 80091be 8009196: 687b ldr r3, [r7, #4] 8009198: 681b ldr r3, [r3, #0] 800919a: 4a64 ldr r2, [pc, #400] @ (800932c ) 800919c: 4293 cmp r3, r2 800919e: d00e beq.n 80091be 80091a0: 687b ldr r3, [r7, #4] 80091a2: 681b ldr r3, [r3, #0] 80091a4: 4a62 ldr r2, [pc, #392] @ (8009330 ) 80091a6: 4293 cmp r3, r2 80091a8: d009 beq.n 80091be 80091aa: 687b ldr r3, [r7, #4] 80091ac: 681b ldr r3, [r3, #0] 80091ae: 4a61 ldr r2, [pc, #388] @ (8009334 ) 80091b0: 4293 cmp r3, r2 80091b2: d004 beq.n 80091be 80091b4: 687b ldr r3, [r7, #4] 80091b6: 681b ldr r3, [r3, #0] 80091b8: 4a5f ldr r2, [pc, #380] @ (8009338 ) 80091ba: 4293 cmp r3, r2 80091bc: d101 bne.n 80091c2 80091be: 2301 movs r3, #1 80091c0: e000 b.n 80091c4 80091c2: 2300 movs r3, #0 80091c4: 2b00 cmp r3, #0 80091c6: d013 beq.n 80091f0 { /* Disable DMA All Interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); 80091c8: 687b ldr r3, [r7, #4] 80091ca: 681b ldr r3, [r3, #0] 80091cc: 681a ldr r2, [r3, #0] 80091ce: 687b ldr r3, [r7, #4] 80091d0: 681b ldr r3, [r3, #0] 80091d2: f022 021e bic.w r2, r2, #30 80091d6: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 80091d8: 687b ldr r3, [r7, #4] 80091da: 681b ldr r3, [r3, #0] 80091dc: 695a ldr r2, [r3, #20] 80091de: 687b ldr r3, [r7, #4] 80091e0: 681b ldr r3, [r3, #0] 80091e2: f022 0280 bic.w r2, r2, #128 @ 0x80 80091e6: 615a str r2, [r3, #20] enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); 80091e8: 687b ldr r3, [r7, #4] 80091ea: 681b ldr r3, [r3, #0] 80091ec: 617b str r3, [r7, #20] 80091ee: e00a b.n 8009206 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 80091f0: 687b ldr r3, [r7, #4] 80091f2: 681b ldr r3, [r3, #0] 80091f4: 681a ldr r2, [r3, #0] 80091f6: 687b ldr r3, [r7, #4] 80091f8: 681b ldr r3, [r3, #0] 80091fa: f022 020e bic.w r2, r2, #14 80091fe: 601a str r2, [r3, #0] enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); 8009200: 687b ldr r3, [r7, #4] 8009202: 681b ldr r3, [r3, #0] 8009204: 617b str r3, [r7, #20] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8009206: 687b ldr r3, [r7, #4] 8009208: 681b ldr r3, [r3, #0] 800920a: 4a3c ldr r2, [pc, #240] @ (80092fc ) 800920c: 4293 cmp r3, r2 800920e: d072 beq.n 80092f6 8009210: 687b ldr r3, [r7, #4] 8009212: 681b ldr r3, [r3, #0] 8009214: 4a3a ldr r2, [pc, #232] @ (8009300 ) 8009216: 4293 cmp r3, r2 8009218: d06d beq.n 80092f6 800921a: 687b ldr r3, [r7, #4] 800921c: 681b ldr r3, [r3, #0] 800921e: 4a39 ldr r2, [pc, #228] @ (8009304 ) 8009220: 4293 cmp r3, r2 8009222: d068 beq.n 80092f6 8009224: 687b ldr r3, [r7, #4] 8009226: 681b ldr r3, [r3, #0] 8009228: 4a37 ldr r2, [pc, #220] @ (8009308 ) 800922a: 4293 cmp r3, r2 800922c: d063 beq.n 80092f6 800922e: 687b ldr r3, [r7, #4] 8009230: 681b ldr r3, [r3, #0] 8009232: 4a36 ldr r2, [pc, #216] @ (800930c ) 8009234: 4293 cmp r3, r2 8009236: d05e beq.n 80092f6 8009238: 687b ldr r3, [r7, #4] 800923a: 681b ldr r3, [r3, #0] 800923c: 4a34 ldr r2, [pc, #208] @ (8009310 ) 800923e: 4293 cmp r3, r2 8009240: d059 beq.n 80092f6 8009242: 687b ldr r3, [r7, #4] 8009244: 681b ldr r3, [r3, #0] 8009246: 4a33 ldr r2, [pc, #204] @ (8009314 ) 8009248: 4293 cmp r3, r2 800924a: d054 beq.n 80092f6 800924c: 687b ldr r3, [r7, #4] 800924e: 681b ldr r3, [r3, #0] 8009250: 4a31 ldr r2, [pc, #196] @ (8009318 ) 8009252: 4293 cmp r3, r2 8009254: d04f beq.n 80092f6 8009256: 687b ldr r3, [r7, #4] 8009258: 681b ldr r3, [r3, #0] 800925a: 4a30 ldr r2, [pc, #192] @ (800931c ) 800925c: 4293 cmp r3, r2 800925e: d04a beq.n 80092f6 8009260: 687b ldr r3, [r7, #4] 8009262: 681b ldr r3, [r3, #0] 8009264: 4a2e ldr r2, [pc, #184] @ (8009320 ) 8009266: 4293 cmp r3, r2 8009268: d045 beq.n 80092f6 800926a: 687b ldr r3, [r7, #4] 800926c: 681b ldr r3, [r3, #0] 800926e: 4a2d ldr r2, [pc, #180] @ (8009324 ) 8009270: 4293 cmp r3, r2 8009272: d040 beq.n 80092f6 8009274: 687b ldr r3, [r7, #4] 8009276: 681b ldr r3, [r3, #0] 8009278: 4a2b ldr r2, [pc, #172] @ (8009328 ) 800927a: 4293 cmp r3, r2 800927c: d03b beq.n 80092f6 800927e: 687b ldr r3, [r7, #4] 8009280: 681b ldr r3, [r3, #0] 8009282: 4a2a ldr r2, [pc, #168] @ (800932c ) 8009284: 4293 cmp r3, r2 8009286: d036 beq.n 80092f6 8009288: 687b ldr r3, [r7, #4] 800928a: 681b ldr r3, [r3, #0] 800928c: 4a28 ldr r2, [pc, #160] @ (8009330 ) 800928e: 4293 cmp r3, r2 8009290: d031 beq.n 80092f6 8009292: 687b ldr r3, [r7, #4] 8009294: 681b ldr r3, [r3, #0] 8009296: 4a27 ldr r2, [pc, #156] @ (8009334 ) 8009298: 4293 cmp r3, r2 800929a: d02c beq.n 80092f6 800929c: 687b ldr r3, [r7, #4] 800929e: 681b ldr r3, [r3, #0] 80092a0: 4a25 ldr r2, [pc, #148] @ (8009338 ) 80092a2: 4293 cmp r3, r2 80092a4: d027 beq.n 80092f6 80092a6: 687b ldr r3, [r7, #4] 80092a8: 681b ldr r3, [r3, #0] 80092aa: 4a24 ldr r2, [pc, #144] @ (800933c ) 80092ac: 4293 cmp r3, r2 80092ae: d022 beq.n 80092f6 80092b0: 687b ldr r3, [r7, #4] 80092b2: 681b ldr r3, [r3, #0] 80092b4: 4a22 ldr r2, [pc, #136] @ (8009340 ) 80092b6: 4293 cmp r3, r2 80092b8: d01d beq.n 80092f6 80092ba: 687b ldr r3, [r7, #4] 80092bc: 681b ldr r3, [r3, #0] 80092be: 4a21 ldr r2, [pc, #132] @ (8009344 ) 80092c0: 4293 cmp r3, r2 80092c2: d018 beq.n 80092f6 80092c4: 687b ldr r3, [r7, #4] 80092c6: 681b ldr r3, [r3, #0] 80092c8: 4a1f ldr r2, [pc, #124] @ (8009348 ) 80092ca: 4293 cmp r3, r2 80092cc: d013 beq.n 80092f6 80092ce: 687b ldr r3, [r7, #4] 80092d0: 681b ldr r3, [r3, #0] 80092d2: 4a1e ldr r2, [pc, #120] @ (800934c ) 80092d4: 4293 cmp r3, r2 80092d6: d00e beq.n 80092f6 80092d8: 687b ldr r3, [r7, #4] 80092da: 681b ldr r3, [r3, #0] 80092dc: 4a1c ldr r2, [pc, #112] @ (8009350 ) 80092de: 4293 cmp r3, r2 80092e0: d009 beq.n 80092f6 80092e2: 687b ldr r3, [r7, #4] 80092e4: 681b ldr r3, [r3, #0] 80092e6: 4a1b ldr r2, [pc, #108] @ (8009354 ) 80092e8: 4293 cmp r3, r2 80092ea: d004 beq.n 80092f6 80092ec: 687b ldr r3, [r7, #4] 80092ee: 681b ldr r3, [r3, #0] 80092f0: 4a19 ldr r2, [pc, #100] @ (8009358 ) 80092f2: 4293 cmp r3, r2 80092f4: d132 bne.n 800935c 80092f6: 2301 movs r3, #1 80092f8: e031 b.n 800935e 80092fa: bf00 nop 80092fc: 40020010 .word 0x40020010 8009300: 40020028 .word 0x40020028 8009304: 40020040 .word 0x40020040 8009308: 40020058 .word 0x40020058 800930c: 40020070 .word 0x40020070 8009310: 40020088 .word 0x40020088 8009314: 400200a0 .word 0x400200a0 8009318: 400200b8 .word 0x400200b8 800931c: 40020410 .word 0x40020410 8009320: 40020428 .word 0x40020428 8009324: 40020440 .word 0x40020440 8009328: 40020458 .word 0x40020458 800932c: 40020470 .word 0x40020470 8009330: 40020488 .word 0x40020488 8009334: 400204a0 .word 0x400204a0 8009338: 400204b8 .word 0x400204b8 800933c: 58025408 .word 0x58025408 8009340: 5802541c .word 0x5802541c 8009344: 58025430 .word 0x58025430 8009348: 58025444 .word 0x58025444 800934c: 58025458 .word 0x58025458 8009350: 5802546c .word 0x5802546c 8009354: 58025480 .word 0x58025480 8009358: 58025494 .word 0x58025494 800935c: 2300 movs r3, #0 800935e: 2b00 cmp r3, #0 8009360: d007 beq.n 8009372 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8009362: 687b ldr r3, [r7, #4] 8009364: 6e1b ldr r3, [r3, #96] @ 0x60 8009366: 681a ldr r2, [r3, #0] 8009368: 687b ldr r3, [r7, #4] 800936a: 6e1b ldr r3, [r3, #96] @ 0x60 800936c: f422 7280 bic.w r2, r2, #256 @ 0x100 8009370: 601a str r2, [r3, #0] } /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8009372: 687b ldr r3, [r7, #4] 8009374: 681b ldr r3, [r3, #0] 8009376: 4a6d ldr r2, [pc, #436] @ (800952c ) 8009378: 4293 cmp r3, r2 800937a: d04a beq.n 8009412 800937c: 687b ldr r3, [r7, #4] 800937e: 681b ldr r3, [r3, #0] 8009380: 4a6b ldr r2, [pc, #428] @ (8009530 ) 8009382: 4293 cmp r3, r2 8009384: d045 beq.n 8009412 8009386: 687b ldr r3, [r7, #4] 8009388: 681b ldr r3, [r3, #0] 800938a: 4a6a ldr r2, [pc, #424] @ (8009534 ) 800938c: 4293 cmp r3, r2 800938e: d040 beq.n 8009412 8009390: 687b ldr r3, [r7, #4] 8009392: 681b ldr r3, [r3, #0] 8009394: 4a68 ldr r2, [pc, #416] @ (8009538 ) 8009396: 4293 cmp r3, r2 8009398: d03b beq.n 8009412 800939a: 687b ldr r3, [r7, #4] 800939c: 681b ldr r3, [r3, #0] 800939e: 4a67 ldr r2, [pc, #412] @ (800953c ) 80093a0: 4293 cmp r3, r2 80093a2: d036 beq.n 8009412 80093a4: 687b ldr r3, [r7, #4] 80093a6: 681b ldr r3, [r3, #0] 80093a8: 4a65 ldr r2, [pc, #404] @ (8009540 ) 80093aa: 4293 cmp r3, r2 80093ac: d031 beq.n 8009412 80093ae: 687b ldr r3, [r7, #4] 80093b0: 681b ldr r3, [r3, #0] 80093b2: 4a64 ldr r2, [pc, #400] @ (8009544 ) 80093b4: 4293 cmp r3, r2 80093b6: d02c beq.n 8009412 80093b8: 687b ldr r3, [r7, #4] 80093ba: 681b ldr r3, [r3, #0] 80093bc: 4a62 ldr r2, [pc, #392] @ (8009548 ) 80093be: 4293 cmp r3, r2 80093c0: d027 beq.n 8009412 80093c2: 687b ldr r3, [r7, #4] 80093c4: 681b ldr r3, [r3, #0] 80093c6: 4a61 ldr r2, [pc, #388] @ (800954c ) 80093c8: 4293 cmp r3, r2 80093ca: d022 beq.n 8009412 80093cc: 687b ldr r3, [r7, #4] 80093ce: 681b ldr r3, [r3, #0] 80093d0: 4a5f ldr r2, [pc, #380] @ (8009550 ) 80093d2: 4293 cmp r3, r2 80093d4: d01d beq.n 8009412 80093d6: 687b ldr r3, [r7, #4] 80093d8: 681b ldr r3, [r3, #0] 80093da: 4a5e ldr r2, [pc, #376] @ (8009554 ) 80093dc: 4293 cmp r3, r2 80093de: d018 beq.n 8009412 80093e0: 687b ldr r3, [r7, #4] 80093e2: 681b ldr r3, [r3, #0] 80093e4: 4a5c ldr r2, [pc, #368] @ (8009558 ) 80093e6: 4293 cmp r3, r2 80093e8: d013 beq.n 8009412 80093ea: 687b ldr r3, [r7, #4] 80093ec: 681b ldr r3, [r3, #0] 80093ee: 4a5b ldr r2, [pc, #364] @ (800955c ) 80093f0: 4293 cmp r3, r2 80093f2: d00e beq.n 8009412 80093f4: 687b ldr r3, [r7, #4] 80093f6: 681b ldr r3, [r3, #0] 80093f8: 4a59 ldr r2, [pc, #356] @ (8009560 ) 80093fa: 4293 cmp r3, r2 80093fc: d009 beq.n 8009412 80093fe: 687b ldr r3, [r7, #4] 8009400: 681b ldr r3, [r3, #0] 8009402: 4a58 ldr r2, [pc, #352] @ (8009564 ) 8009404: 4293 cmp r3, r2 8009406: d004 beq.n 8009412 8009408: 687b ldr r3, [r7, #4] 800940a: 681b ldr r3, [r3, #0] 800940c: 4a56 ldr r2, [pc, #344] @ (8009568 ) 800940e: 4293 cmp r3, r2 8009410: d108 bne.n 8009424 8009412: 687b ldr r3, [r7, #4] 8009414: 681b ldr r3, [r3, #0] 8009416: 681a ldr r2, [r3, #0] 8009418: 687b ldr r3, [r7, #4] 800941a: 681b ldr r3, [r3, #0] 800941c: f022 0201 bic.w r2, r2, #1 8009420: 601a str r2, [r3, #0] 8009422: e007 b.n 8009434 8009424: 687b ldr r3, [r7, #4] 8009426: 681b ldr r3, [r3, #0] 8009428: 681a ldr r2, [r3, #0] 800942a: 687b ldr r3, [r7, #4] 800942c: 681b ldr r3, [r3, #0] 800942e: f022 0201 bic.w r2, r2, #1 8009432: 601a str r2, [r3, #0] /* Check if the DMA Stream is effectively disabled */ while(((*enableRegister) & DMA_SxCR_EN) != 0U) 8009434: e013 b.n 800945e { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) 8009436: f7fc fcf5 bl 8005e24 800943a: 4602 mov r2, r0 800943c: 693b ldr r3, [r7, #16] 800943e: 1ad3 subs r3, r2, r3 8009440: 2b05 cmp r3, #5 8009442: d90c bls.n 800945e { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 8009444: 687b ldr r3, [r7, #4] 8009446: 2220 movs r2, #32 8009448: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_ERROR; 800944a: 687b ldr r3, [r7, #4] 800944c: 2203 movs r2, #3 800944e: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009452: 687b ldr r3, [r7, #4] 8009454: 2200 movs r2, #0 8009456: f883 2034 strb.w r2, [r3, #52] @ 0x34 return HAL_ERROR; 800945a: 2301 movs r3, #1 800945c: e12d b.n 80096ba while(((*enableRegister) & DMA_SxCR_EN) != 0U) 800945e: 697b ldr r3, [r7, #20] 8009460: 681b ldr r3, [r3, #0] 8009462: f003 0301 and.w r3, r3, #1 8009466: 2b00 cmp r3, #0 8009468: d1e5 bne.n 8009436 } } /* Clear all interrupt flags at correct offset within the register */ if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800946a: 687b ldr r3, [r7, #4] 800946c: 681b ldr r3, [r3, #0] 800946e: 4a2f ldr r2, [pc, #188] @ (800952c ) 8009470: 4293 cmp r3, r2 8009472: d04a beq.n 800950a 8009474: 687b ldr r3, [r7, #4] 8009476: 681b ldr r3, [r3, #0] 8009478: 4a2d ldr r2, [pc, #180] @ (8009530 ) 800947a: 4293 cmp r3, r2 800947c: d045 beq.n 800950a 800947e: 687b ldr r3, [r7, #4] 8009480: 681b ldr r3, [r3, #0] 8009482: 4a2c ldr r2, [pc, #176] @ (8009534 ) 8009484: 4293 cmp r3, r2 8009486: d040 beq.n 800950a 8009488: 687b ldr r3, [r7, #4] 800948a: 681b ldr r3, [r3, #0] 800948c: 4a2a ldr r2, [pc, #168] @ (8009538 ) 800948e: 4293 cmp r3, r2 8009490: d03b beq.n 800950a 8009492: 687b ldr r3, [r7, #4] 8009494: 681b ldr r3, [r3, #0] 8009496: 4a29 ldr r2, [pc, #164] @ (800953c ) 8009498: 4293 cmp r3, r2 800949a: d036 beq.n 800950a 800949c: 687b ldr r3, [r7, #4] 800949e: 681b ldr r3, [r3, #0] 80094a0: 4a27 ldr r2, [pc, #156] @ (8009540 ) 80094a2: 4293 cmp r3, r2 80094a4: d031 beq.n 800950a 80094a6: 687b ldr r3, [r7, #4] 80094a8: 681b ldr r3, [r3, #0] 80094aa: 4a26 ldr r2, [pc, #152] @ (8009544 ) 80094ac: 4293 cmp r3, r2 80094ae: d02c beq.n 800950a 80094b0: 687b ldr r3, [r7, #4] 80094b2: 681b ldr r3, [r3, #0] 80094b4: 4a24 ldr r2, [pc, #144] @ (8009548 ) 80094b6: 4293 cmp r3, r2 80094b8: d027 beq.n 800950a 80094ba: 687b ldr r3, [r7, #4] 80094bc: 681b ldr r3, [r3, #0] 80094be: 4a23 ldr r2, [pc, #140] @ (800954c ) 80094c0: 4293 cmp r3, r2 80094c2: d022 beq.n 800950a 80094c4: 687b ldr r3, [r7, #4] 80094c6: 681b ldr r3, [r3, #0] 80094c8: 4a21 ldr r2, [pc, #132] @ (8009550 ) 80094ca: 4293 cmp r3, r2 80094cc: d01d beq.n 800950a 80094ce: 687b ldr r3, [r7, #4] 80094d0: 681b ldr r3, [r3, #0] 80094d2: 4a20 ldr r2, [pc, #128] @ (8009554 ) 80094d4: 4293 cmp r3, r2 80094d6: d018 beq.n 800950a 80094d8: 687b ldr r3, [r7, #4] 80094da: 681b ldr r3, [r3, #0] 80094dc: 4a1e ldr r2, [pc, #120] @ (8009558 ) 80094de: 4293 cmp r3, r2 80094e0: d013 beq.n 800950a 80094e2: 687b ldr r3, [r7, #4] 80094e4: 681b ldr r3, [r3, #0] 80094e6: 4a1d ldr r2, [pc, #116] @ (800955c ) 80094e8: 4293 cmp r3, r2 80094ea: d00e beq.n 800950a 80094ec: 687b ldr r3, [r7, #4] 80094ee: 681b ldr r3, [r3, #0] 80094f0: 4a1b ldr r2, [pc, #108] @ (8009560 ) 80094f2: 4293 cmp r3, r2 80094f4: d009 beq.n 800950a 80094f6: 687b ldr r3, [r7, #4] 80094f8: 681b ldr r3, [r3, #0] 80094fa: 4a1a ldr r2, [pc, #104] @ (8009564 ) 80094fc: 4293 cmp r3, r2 80094fe: d004 beq.n 800950a 8009500: 687b ldr r3, [r7, #4] 8009502: 681b ldr r3, [r3, #0] 8009504: 4a18 ldr r2, [pc, #96] @ (8009568 ) 8009506: 4293 cmp r3, r2 8009508: d101 bne.n 800950e 800950a: 2301 movs r3, #1 800950c: e000 b.n 8009510 800950e: 2300 movs r3, #0 8009510: 2b00 cmp r3, #0 8009512: d02b beq.n 800956c { regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009514: 687b ldr r3, [r7, #4] 8009516: 6d9b ldr r3, [r3, #88] @ 0x58 8009518: 60bb str r3, [r7, #8] regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800951a: 687b ldr r3, [r7, #4] 800951c: 6ddb ldr r3, [r3, #92] @ 0x5c 800951e: f003 031f and.w r3, r3, #31 8009522: 223f movs r2, #63 @ 0x3f 8009524: 409a lsls r2, r3 8009526: 68bb ldr r3, [r7, #8] 8009528: 609a str r2, [r3, #8] 800952a: e02a b.n 8009582 800952c: 40020010 .word 0x40020010 8009530: 40020028 .word 0x40020028 8009534: 40020040 .word 0x40020040 8009538: 40020058 .word 0x40020058 800953c: 40020070 .word 0x40020070 8009540: 40020088 .word 0x40020088 8009544: 400200a0 .word 0x400200a0 8009548: 400200b8 .word 0x400200b8 800954c: 40020410 .word 0x40020410 8009550: 40020428 .word 0x40020428 8009554: 40020440 .word 0x40020440 8009558: 40020458 .word 0x40020458 800955c: 40020470 .word 0x40020470 8009560: 40020488 .word 0x40020488 8009564: 400204a0 .word 0x400204a0 8009568: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800956c: 687b ldr r3, [r7, #4] 800956e: 6d9b ldr r3, [r3, #88] @ 0x58 8009570: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8009572: 687b ldr r3, [r7, #4] 8009574: 6ddb ldr r3, [r3, #92] @ 0x5c 8009576: f003 031f and.w r3, r3, #31 800957a: 2201 movs r2, #1 800957c: 409a lsls r2, r3 800957e: 68fb ldr r3, [r7, #12] 8009580: 605a str r2, [r3, #4] } if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 8009582: 687b ldr r3, [r7, #4] 8009584: 681b ldr r3, [r3, #0] 8009586: 4a4f ldr r2, [pc, #316] @ (80096c4 ) 8009588: 4293 cmp r3, r2 800958a: d072 beq.n 8009672 800958c: 687b ldr r3, [r7, #4] 800958e: 681b ldr r3, [r3, #0] 8009590: 4a4d ldr r2, [pc, #308] @ (80096c8 ) 8009592: 4293 cmp r3, r2 8009594: d06d beq.n 8009672 8009596: 687b ldr r3, [r7, #4] 8009598: 681b ldr r3, [r3, #0] 800959a: 4a4c ldr r2, [pc, #304] @ (80096cc ) 800959c: 4293 cmp r3, r2 800959e: d068 beq.n 8009672 80095a0: 687b ldr r3, [r7, #4] 80095a2: 681b ldr r3, [r3, #0] 80095a4: 4a4a ldr r2, [pc, #296] @ (80096d0 ) 80095a6: 4293 cmp r3, r2 80095a8: d063 beq.n 8009672 80095aa: 687b ldr r3, [r7, #4] 80095ac: 681b ldr r3, [r3, #0] 80095ae: 4a49 ldr r2, [pc, #292] @ (80096d4 ) 80095b0: 4293 cmp r3, r2 80095b2: d05e beq.n 8009672 80095b4: 687b ldr r3, [r7, #4] 80095b6: 681b ldr r3, [r3, #0] 80095b8: 4a47 ldr r2, [pc, #284] @ (80096d8 ) 80095ba: 4293 cmp r3, r2 80095bc: d059 beq.n 8009672 80095be: 687b ldr r3, [r7, #4] 80095c0: 681b ldr r3, [r3, #0] 80095c2: 4a46 ldr r2, [pc, #280] @ (80096dc ) 80095c4: 4293 cmp r3, r2 80095c6: d054 beq.n 8009672 80095c8: 687b ldr r3, [r7, #4] 80095ca: 681b ldr r3, [r3, #0] 80095cc: 4a44 ldr r2, [pc, #272] @ (80096e0 ) 80095ce: 4293 cmp r3, r2 80095d0: d04f beq.n 8009672 80095d2: 687b ldr r3, [r7, #4] 80095d4: 681b ldr r3, [r3, #0] 80095d6: 4a43 ldr r2, [pc, #268] @ (80096e4 ) 80095d8: 4293 cmp r3, r2 80095da: d04a beq.n 8009672 80095dc: 687b ldr r3, [r7, #4] 80095de: 681b ldr r3, [r3, #0] 80095e0: 4a41 ldr r2, [pc, #260] @ (80096e8 ) 80095e2: 4293 cmp r3, r2 80095e4: d045 beq.n 8009672 80095e6: 687b ldr r3, [r7, #4] 80095e8: 681b ldr r3, [r3, #0] 80095ea: 4a40 ldr r2, [pc, #256] @ (80096ec ) 80095ec: 4293 cmp r3, r2 80095ee: d040 beq.n 8009672 80095f0: 687b ldr r3, [r7, #4] 80095f2: 681b ldr r3, [r3, #0] 80095f4: 4a3e ldr r2, [pc, #248] @ (80096f0 ) 80095f6: 4293 cmp r3, r2 80095f8: d03b beq.n 8009672 80095fa: 687b ldr r3, [r7, #4] 80095fc: 681b ldr r3, [r3, #0] 80095fe: 4a3d ldr r2, [pc, #244] @ (80096f4 ) 8009600: 4293 cmp r3, r2 8009602: d036 beq.n 8009672 8009604: 687b ldr r3, [r7, #4] 8009606: 681b ldr r3, [r3, #0] 8009608: 4a3b ldr r2, [pc, #236] @ (80096f8 ) 800960a: 4293 cmp r3, r2 800960c: d031 beq.n 8009672 800960e: 687b ldr r3, [r7, #4] 8009610: 681b ldr r3, [r3, #0] 8009612: 4a3a ldr r2, [pc, #232] @ (80096fc ) 8009614: 4293 cmp r3, r2 8009616: d02c beq.n 8009672 8009618: 687b ldr r3, [r7, #4] 800961a: 681b ldr r3, [r3, #0] 800961c: 4a38 ldr r2, [pc, #224] @ (8009700 ) 800961e: 4293 cmp r3, r2 8009620: d027 beq.n 8009672 8009622: 687b ldr r3, [r7, #4] 8009624: 681b ldr r3, [r3, #0] 8009626: 4a37 ldr r2, [pc, #220] @ (8009704 ) 8009628: 4293 cmp r3, r2 800962a: d022 beq.n 8009672 800962c: 687b ldr r3, [r7, #4] 800962e: 681b ldr r3, [r3, #0] 8009630: 4a35 ldr r2, [pc, #212] @ (8009708 ) 8009632: 4293 cmp r3, r2 8009634: d01d beq.n 8009672 8009636: 687b ldr r3, [r7, #4] 8009638: 681b ldr r3, [r3, #0] 800963a: 4a34 ldr r2, [pc, #208] @ (800970c ) 800963c: 4293 cmp r3, r2 800963e: d018 beq.n 8009672 8009640: 687b ldr r3, [r7, #4] 8009642: 681b ldr r3, [r3, #0] 8009644: 4a32 ldr r2, [pc, #200] @ (8009710 ) 8009646: 4293 cmp r3, r2 8009648: d013 beq.n 8009672 800964a: 687b ldr r3, [r7, #4] 800964c: 681b ldr r3, [r3, #0] 800964e: 4a31 ldr r2, [pc, #196] @ (8009714 ) 8009650: 4293 cmp r3, r2 8009652: d00e beq.n 8009672 8009654: 687b ldr r3, [r7, #4] 8009656: 681b ldr r3, [r3, #0] 8009658: 4a2f ldr r2, [pc, #188] @ (8009718 ) 800965a: 4293 cmp r3, r2 800965c: d009 beq.n 8009672 800965e: 687b ldr r3, [r7, #4] 8009660: 681b ldr r3, [r3, #0] 8009662: 4a2e ldr r2, [pc, #184] @ (800971c ) 8009664: 4293 cmp r3, r2 8009666: d004 beq.n 8009672 8009668: 687b ldr r3, [r7, #4] 800966a: 681b ldr r3, [r3, #0] 800966c: 4a2c ldr r2, [pc, #176] @ (8009720 ) 800966e: 4293 cmp r3, r2 8009670: d101 bne.n 8009676 8009672: 2301 movs r3, #1 8009674: e000 b.n 8009678 8009676: 2300 movs r3, #0 8009678: 2b00 cmp r3, #0 800967a: d015 beq.n 80096a8 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800967c: 687b ldr r3, [r7, #4] 800967e: 6e5b ldr r3, [r3, #100] @ 0x64 8009680: 687a ldr r2, [r7, #4] 8009682: 6e92 ldr r2, [r2, #104] @ 0x68 8009684: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8009686: 687b ldr r3, [r7, #4] 8009688: 6edb ldr r3, [r3, #108] @ 0x6c 800968a: 2b00 cmp r3, #0 800968c: d00c beq.n 80096a8 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 800968e: 687b ldr r3, [r7, #4] 8009690: 6edb ldr r3, [r3, #108] @ 0x6c 8009692: 681a ldr r2, [r3, #0] 8009694: 687b ldr r3, [r7, #4] 8009696: 6edb ldr r3, [r3, #108] @ 0x6c 8009698: f422 7280 bic.w r2, r2, #256 @ 0x100 800969c: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800969e: 687b ldr r3, [r7, #4] 80096a0: 6f1b ldr r3, [r3, #112] @ 0x70 80096a2: 687a ldr r2, [r7, #4] 80096a4: 6f52 ldr r2, [r2, #116] @ 0x74 80096a6: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 80096a8: 687b ldr r3, [r7, #4] 80096aa: 2201 movs r2, #1 80096ac: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 80096b0: 687b ldr r3, [r7, #4] 80096b2: 2200 movs r2, #0 80096b4: f883 2034 strb.w r2, [r3, #52] @ 0x34 } return HAL_OK; 80096b8: 2300 movs r3, #0 } 80096ba: 4618 mov r0, r3 80096bc: 3718 adds r7, #24 80096be: 46bd mov sp, r7 80096c0: bd80 pop {r7, pc} 80096c2: bf00 nop 80096c4: 40020010 .word 0x40020010 80096c8: 40020028 .word 0x40020028 80096cc: 40020040 .word 0x40020040 80096d0: 40020058 .word 0x40020058 80096d4: 40020070 .word 0x40020070 80096d8: 40020088 .word 0x40020088 80096dc: 400200a0 .word 0x400200a0 80096e0: 400200b8 .word 0x400200b8 80096e4: 40020410 .word 0x40020410 80096e8: 40020428 .word 0x40020428 80096ec: 40020440 .word 0x40020440 80096f0: 40020458 .word 0x40020458 80096f4: 40020470 .word 0x40020470 80096f8: 40020488 .word 0x40020488 80096fc: 400204a0 .word 0x400204a0 8009700: 400204b8 .word 0x400204b8 8009704: 58025408 .word 0x58025408 8009708: 5802541c .word 0x5802541c 800970c: 58025430 .word 0x58025430 8009710: 58025444 .word 0x58025444 8009714: 58025458 .word 0x58025458 8009718: 5802546c .word 0x5802546c 800971c: 58025480 .word 0x58025480 8009720: 58025494 .word 0x58025494 08009724 : * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { 8009724: b580 push {r7, lr} 8009726: b084 sub sp, #16 8009728: af00 add r7, sp, #0 800972a: 6078 str r0, [r7, #4] BDMA_Base_Registers *regs_bdma; /* Check the DMA peripheral handle */ if(hdma == NULL) 800972c: 687b ldr r3, [r7, #4] 800972e: 2b00 cmp r3, #0 8009730: d101 bne.n 8009736 { return HAL_ERROR; 8009732: 2301 movs r3, #1 8009734: e237 b.n 8009ba6 } if(hdma->State != HAL_DMA_STATE_BUSY) 8009736: 687b ldr r3, [r7, #4] 8009738: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800973c: b2db uxtb r3, r3 800973e: 2b02 cmp r3, #2 8009740: d004 beq.n 800974c { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 8009742: 687b ldr r3, [r7, #4] 8009744: 2280 movs r2, #128 @ 0x80 8009746: 655a str r2, [r3, #84] @ 0x54 return HAL_ERROR; 8009748: 2301 movs r3, #1 800974a: e22c b.n 8009ba6 } else { if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800974c: 687b ldr r3, [r7, #4] 800974e: 681b ldr r3, [r3, #0] 8009750: 4a5c ldr r2, [pc, #368] @ (80098c4 ) 8009752: 4293 cmp r3, r2 8009754: d04a beq.n 80097ec 8009756: 687b ldr r3, [r7, #4] 8009758: 681b ldr r3, [r3, #0] 800975a: 4a5b ldr r2, [pc, #364] @ (80098c8 ) 800975c: 4293 cmp r3, r2 800975e: d045 beq.n 80097ec 8009760: 687b ldr r3, [r7, #4] 8009762: 681b ldr r3, [r3, #0] 8009764: 4a59 ldr r2, [pc, #356] @ (80098cc ) 8009766: 4293 cmp r3, r2 8009768: d040 beq.n 80097ec 800976a: 687b ldr r3, [r7, #4] 800976c: 681b ldr r3, [r3, #0] 800976e: 4a58 ldr r2, [pc, #352] @ (80098d0 ) 8009770: 4293 cmp r3, r2 8009772: d03b beq.n 80097ec 8009774: 687b ldr r3, [r7, #4] 8009776: 681b ldr r3, [r3, #0] 8009778: 4a56 ldr r2, [pc, #344] @ (80098d4 ) 800977a: 4293 cmp r3, r2 800977c: d036 beq.n 80097ec 800977e: 687b ldr r3, [r7, #4] 8009780: 681b ldr r3, [r3, #0] 8009782: 4a55 ldr r2, [pc, #340] @ (80098d8 ) 8009784: 4293 cmp r3, r2 8009786: d031 beq.n 80097ec 8009788: 687b ldr r3, [r7, #4] 800978a: 681b ldr r3, [r3, #0] 800978c: 4a53 ldr r2, [pc, #332] @ (80098dc ) 800978e: 4293 cmp r3, r2 8009790: d02c beq.n 80097ec 8009792: 687b ldr r3, [r7, #4] 8009794: 681b ldr r3, [r3, #0] 8009796: 4a52 ldr r2, [pc, #328] @ (80098e0 ) 8009798: 4293 cmp r3, r2 800979a: d027 beq.n 80097ec 800979c: 687b ldr r3, [r7, #4] 800979e: 681b ldr r3, [r3, #0] 80097a0: 4a50 ldr r2, [pc, #320] @ (80098e4 ) 80097a2: 4293 cmp r3, r2 80097a4: d022 beq.n 80097ec 80097a6: 687b ldr r3, [r7, #4] 80097a8: 681b ldr r3, [r3, #0] 80097aa: 4a4f ldr r2, [pc, #316] @ (80098e8 ) 80097ac: 4293 cmp r3, r2 80097ae: d01d beq.n 80097ec 80097b0: 687b ldr r3, [r7, #4] 80097b2: 681b ldr r3, [r3, #0] 80097b4: 4a4d ldr r2, [pc, #308] @ (80098ec ) 80097b6: 4293 cmp r3, r2 80097b8: d018 beq.n 80097ec 80097ba: 687b ldr r3, [r7, #4] 80097bc: 681b ldr r3, [r3, #0] 80097be: 4a4c ldr r2, [pc, #304] @ (80098f0 ) 80097c0: 4293 cmp r3, r2 80097c2: d013 beq.n 80097ec 80097c4: 687b ldr r3, [r7, #4] 80097c6: 681b ldr r3, [r3, #0] 80097c8: 4a4a ldr r2, [pc, #296] @ (80098f4 ) 80097ca: 4293 cmp r3, r2 80097cc: d00e beq.n 80097ec 80097ce: 687b ldr r3, [r7, #4] 80097d0: 681b ldr r3, [r3, #0] 80097d2: 4a49 ldr r2, [pc, #292] @ (80098f8 ) 80097d4: 4293 cmp r3, r2 80097d6: d009 beq.n 80097ec 80097d8: 687b ldr r3, [r7, #4] 80097da: 681b ldr r3, [r3, #0] 80097dc: 4a47 ldr r2, [pc, #284] @ (80098fc ) 80097de: 4293 cmp r3, r2 80097e0: d004 beq.n 80097ec 80097e2: 687b ldr r3, [r7, #4] 80097e4: 681b ldr r3, [r3, #0] 80097e6: 4a46 ldr r2, [pc, #280] @ (8009900 ) 80097e8: 4293 cmp r3, r2 80097ea: d101 bne.n 80097f0 80097ec: 2301 movs r3, #1 80097ee: e000 b.n 80097f2 80097f0: 2300 movs r3, #0 80097f2: 2b00 cmp r3, #0 80097f4: f000 8086 beq.w 8009904 { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; 80097f8: 687b ldr r3, [r7, #4] 80097fa: 2204 movs r2, #4 80097fc: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 8009800: 687b ldr r3, [r7, #4] 8009802: 681b ldr r3, [r3, #0] 8009804: 4a2f ldr r2, [pc, #188] @ (80098c4 ) 8009806: 4293 cmp r3, r2 8009808: d04a beq.n 80098a0 800980a: 687b ldr r3, [r7, #4] 800980c: 681b ldr r3, [r3, #0] 800980e: 4a2e ldr r2, [pc, #184] @ (80098c8 ) 8009810: 4293 cmp r3, r2 8009812: d045 beq.n 80098a0 8009814: 687b ldr r3, [r7, #4] 8009816: 681b ldr r3, [r3, #0] 8009818: 4a2c ldr r2, [pc, #176] @ (80098cc ) 800981a: 4293 cmp r3, r2 800981c: d040 beq.n 80098a0 800981e: 687b ldr r3, [r7, #4] 8009820: 681b ldr r3, [r3, #0] 8009822: 4a2b ldr r2, [pc, #172] @ (80098d0 ) 8009824: 4293 cmp r3, r2 8009826: d03b beq.n 80098a0 8009828: 687b ldr r3, [r7, #4] 800982a: 681b ldr r3, [r3, #0] 800982c: 4a29 ldr r2, [pc, #164] @ (80098d4 ) 800982e: 4293 cmp r3, r2 8009830: d036 beq.n 80098a0 8009832: 687b ldr r3, [r7, #4] 8009834: 681b ldr r3, [r3, #0] 8009836: 4a28 ldr r2, [pc, #160] @ (80098d8 ) 8009838: 4293 cmp r3, r2 800983a: d031 beq.n 80098a0 800983c: 687b ldr r3, [r7, #4] 800983e: 681b ldr r3, [r3, #0] 8009840: 4a26 ldr r2, [pc, #152] @ (80098dc ) 8009842: 4293 cmp r3, r2 8009844: d02c beq.n 80098a0 8009846: 687b ldr r3, [r7, #4] 8009848: 681b ldr r3, [r3, #0] 800984a: 4a25 ldr r2, [pc, #148] @ (80098e0 ) 800984c: 4293 cmp r3, r2 800984e: d027 beq.n 80098a0 8009850: 687b ldr r3, [r7, #4] 8009852: 681b ldr r3, [r3, #0] 8009854: 4a23 ldr r2, [pc, #140] @ (80098e4 ) 8009856: 4293 cmp r3, r2 8009858: d022 beq.n 80098a0 800985a: 687b ldr r3, [r7, #4] 800985c: 681b ldr r3, [r3, #0] 800985e: 4a22 ldr r2, [pc, #136] @ (80098e8 ) 8009860: 4293 cmp r3, r2 8009862: d01d beq.n 80098a0 8009864: 687b ldr r3, [r7, #4] 8009866: 681b ldr r3, [r3, #0] 8009868: 4a20 ldr r2, [pc, #128] @ (80098ec ) 800986a: 4293 cmp r3, r2 800986c: d018 beq.n 80098a0 800986e: 687b ldr r3, [r7, #4] 8009870: 681b ldr r3, [r3, #0] 8009872: 4a1f ldr r2, [pc, #124] @ (80098f0 ) 8009874: 4293 cmp r3, r2 8009876: d013 beq.n 80098a0 8009878: 687b ldr r3, [r7, #4] 800987a: 681b ldr r3, [r3, #0] 800987c: 4a1d ldr r2, [pc, #116] @ (80098f4 ) 800987e: 4293 cmp r3, r2 8009880: d00e beq.n 80098a0 8009882: 687b ldr r3, [r7, #4] 8009884: 681b ldr r3, [r3, #0] 8009886: 4a1c ldr r2, [pc, #112] @ (80098f8 ) 8009888: 4293 cmp r3, r2 800988a: d009 beq.n 80098a0 800988c: 687b ldr r3, [r7, #4] 800988e: 681b ldr r3, [r3, #0] 8009890: 4a1a ldr r2, [pc, #104] @ (80098fc ) 8009892: 4293 cmp r3, r2 8009894: d004 beq.n 80098a0 8009896: 687b ldr r3, [r7, #4] 8009898: 681b ldr r3, [r3, #0] 800989a: 4a19 ldr r2, [pc, #100] @ (8009900 ) 800989c: 4293 cmp r3, r2 800989e: d108 bne.n 80098b2 80098a0: 687b ldr r3, [r7, #4] 80098a2: 681b ldr r3, [r3, #0] 80098a4: 681a ldr r2, [r3, #0] 80098a6: 687b ldr r3, [r7, #4] 80098a8: 681b ldr r3, [r3, #0] 80098aa: f022 0201 bic.w r2, r2, #1 80098ae: 601a str r2, [r3, #0] 80098b0: e178 b.n 8009ba4 80098b2: 687b ldr r3, [r7, #4] 80098b4: 681b ldr r3, [r3, #0] 80098b6: 681a ldr r2, [r3, #0] 80098b8: 687b ldr r3, [r7, #4] 80098ba: 681b ldr r3, [r3, #0] 80098bc: f022 0201 bic.w r2, r2, #1 80098c0: 601a str r2, [r3, #0] 80098c2: e16f b.n 8009ba4 80098c4: 40020010 .word 0x40020010 80098c8: 40020028 .word 0x40020028 80098cc: 40020040 .word 0x40020040 80098d0: 40020058 .word 0x40020058 80098d4: 40020070 .word 0x40020070 80098d8: 40020088 .word 0x40020088 80098dc: 400200a0 .word 0x400200a0 80098e0: 400200b8 .word 0x400200b8 80098e4: 40020410 .word 0x40020410 80098e8: 40020428 .word 0x40020428 80098ec: 40020440 .word 0x40020440 80098f0: 40020458 .word 0x40020458 80098f4: 40020470 .word 0x40020470 80098f8: 40020488 .word 0x40020488 80098fc: 400204a0 .word 0x400204a0 8009900: 400204b8 .word 0x400204b8 } else /* BDMA channel */ { /* Disable DMA All Interrupts */ ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); 8009904: 687b ldr r3, [r7, #4] 8009906: 681b ldr r3, [r3, #0] 8009908: 681a ldr r2, [r3, #0] 800990a: 687b ldr r3, [r7, #4] 800990c: 681b ldr r3, [r3, #0] 800990e: f022 020e bic.w r2, r2, #14 8009912: 601a str r2, [r3, #0] /* Disable the channel */ __HAL_DMA_DISABLE(hdma); 8009914: 687b ldr r3, [r7, #4] 8009916: 681b ldr r3, [r3, #0] 8009918: 4a6c ldr r2, [pc, #432] @ (8009acc ) 800991a: 4293 cmp r3, r2 800991c: d04a beq.n 80099b4 800991e: 687b ldr r3, [r7, #4] 8009920: 681b ldr r3, [r3, #0] 8009922: 4a6b ldr r2, [pc, #428] @ (8009ad0 ) 8009924: 4293 cmp r3, r2 8009926: d045 beq.n 80099b4 8009928: 687b ldr r3, [r7, #4] 800992a: 681b ldr r3, [r3, #0] 800992c: 4a69 ldr r2, [pc, #420] @ (8009ad4 ) 800992e: 4293 cmp r3, r2 8009930: d040 beq.n 80099b4 8009932: 687b ldr r3, [r7, #4] 8009934: 681b ldr r3, [r3, #0] 8009936: 4a68 ldr r2, [pc, #416] @ (8009ad8 ) 8009938: 4293 cmp r3, r2 800993a: d03b beq.n 80099b4 800993c: 687b ldr r3, [r7, #4] 800993e: 681b ldr r3, [r3, #0] 8009940: 4a66 ldr r2, [pc, #408] @ (8009adc ) 8009942: 4293 cmp r3, r2 8009944: d036 beq.n 80099b4 8009946: 687b ldr r3, [r7, #4] 8009948: 681b ldr r3, [r3, #0] 800994a: 4a65 ldr r2, [pc, #404] @ (8009ae0 ) 800994c: 4293 cmp r3, r2 800994e: d031 beq.n 80099b4 8009950: 687b ldr r3, [r7, #4] 8009952: 681b ldr r3, [r3, #0] 8009954: 4a63 ldr r2, [pc, #396] @ (8009ae4 ) 8009956: 4293 cmp r3, r2 8009958: d02c beq.n 80099b4 800995a: 687b ldr r3, [r7, #4] 800995c: 681b ldr r3, [r3, #0] 800995e: 4a62 ldr r2, [pc, #392] @ (8009ae8 ) 8009960: 4293 cmp r3, r2 8009962: d027 beq.n 80099b4 8009964: 687b ldr r3, [r7, #4] 8009966: 681b ldr r3, [r3, #0] 8009968: 4a60 ldr r2, [pc, #384] @ (8009aec ) 800996a: 4293 cmp r3, r2 800996c: d022 beq.n 80099b4 800996e: 687b ldr r3, [r7, #4] 8009970: 681b ldr r3, [r3, #0] 8009972: 4a5f ldr r2, [pc, #380] @ (8009af0 ) 8009974: 4293 cmp r3, r2 8009976: d01d beq.n 80099b4 8009978: 687b ldr r3, [r7, #4] 800997a: 681b ldr r3, [r3, #0] 800997c: 4a5d ldr r2, [pc, #372] @ (8009af4 ) 800997e: 4293 cmp r3, r2 8009980: d018 beq.n 80099b4 8009982: 687b ldr r3, [r7, #4] 8009984: 681b ldr r3, [r3, #0] 8009986: 4a5c ldr r2, [pc, #368] @ (8009af8 ) 8009988: 4293 cmp r3, r2 800998a: d013 beq.n 80099b4 800998c: 687b ldr r3, [r7, #4] 800998e: 681b ldr r3, [r3, #0] 8009990: 4a5a ldr r2, [pc, #360] @ (8009afc ) 8009992: 4293 cmp r3, r2 8009994: d00e beq.n 80099b4 8009996: 687b ldr r3, [r7, #4] 8009998: 681b ldr r3, [r3, #0] 800999a: 4a59 ldr r2, [pc, #356] @ (8009b00 ) 800999c: 4293 cmp r3, r2 800999e: d009 beq.n 80099b4 80099a0: 687b ldr r3, [r7, #4] 80099a2: 681b ldr r3, [r3, #0] 80099a4: 4a57 ldr r2, [pc, #348] @ (8009b04 ) 80099a6: 4293 cmp r3, r2 80099a8: d004 beq.n 80099b4 80099aa: 687b ldr r3, [r7, #4] 80099ac: 681b ldr r3, [r3, #0] 80099ae: 4a56 ldr r2, [pc, #344] @ (8009b08 ) 80099b0: 4293 cmp r3, r2 80099b2: d108 bne.n 80099c6 80099b4: 687b ldr r3, [r7, #4] 80099b6: 681b ldr r3, [r3, #0] 80099b8: 681a ldr r2, [r3, #0] 80099ba: 687b ldr r3, [r7, #4] 80099bc: 681b ldr r3, [r3, #0] 80099be: f022 0201 bic.w r2, r2, #1 80099c2: 601a str r2, [r3, #0] 80099c4: e007 b.n 80099d6 80099c6: 687b ldr r3, [r7, #4] 80099c8: 681b ldr r3, [r3, #0] 80099ca: 681a ldr r2, [r3, #0] 80099cc: 687b ldr r3, [r7, #4] 80099ce: 681b ldr r3, [r3, #0] 80099d0: f022 0201 bic.w r2, r2, #1 80099d4: 601a str r2, [r3, #0] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 80099d6: 687b ldr r3, [r7, #4] 80099d8: 681b ldr r3, [r3, #0] 80099da: 4a3c ldr r2, [pc, #240] @ (8009acc ) 80099dc: 4293 cmp r3, r2 80099de: d072 beq.n 8009ac6 80099e0: 687b ldr r3, [r7, #4] 80099e2: 681b ldr r3, [r3, #0] 80099e4: 4a3a ldr r2, [pc, #232] @ (8009ad0 ) 80099e6: 4293 cmp r3, r2 80099e8: d06d beq.n 8009ac6 80099ea: 687b ldr r3, [r7, #4] 80099ec: 681b ldr r3, [r3, #0] 80099ee: 4a39 ldr r2, [pc, #228] @ (8009ad4 ) 80099f0: 4293 cmp r3, r2 80099f2: d068 beq.n 8009ac6 80099f4: 687b ldr r3, [r7, #4] 80099f6: 681b ldr r3, [r3, #0] 80099f8: 4a37 ldr r2, [pc, #220] @ (8009ad8 ) 80099fa: 4293 cmp r3, r2 80099fc: d063 beq.n 8009ac6 80099fe: 687b ldr r3, [r7, #4] 8009a00: 681b ldr r3, [r3, #0] 8009a02: 4a36 ldr r2, [pc, #216] @ (8009adc ) 8009a04: 4293 cmp r3, r2 8009a06: d05e beq.n 8009ac6 8009a08: 687b ldr r3, [r7, #4] 8009a0a: 681b ldr r3, [r3, #0] 8009a0c: 4a34 ldr r2, [pc, #208] @ (8009ae0 ) 8009a0e: 4293 cmp r3, r2 8009a10: d059 beq.n 8009ac6 8009a12: 687b ldr r3, [r7, #4] 8009a14: 681b ldr r3, [r3, #0] 8009a16: 4a33 ldr r2, [pc, #204] @ (8009ae4 ) 8009a18: 4293 cmp r3, r2 8009a1a: d054 beq.n 8009ac6 8009a1c: 687b ldr r3, [r7, #4] 8009a1e: 681b ldr r3, [r3, #0] 8009a20: 4a31 ldr r2, [pc, #196] @ (8009ae8 ) 8009a22: 4293 cmp r3, r2 8009a24: d04f beq.n 8009ac6 8009a26: 687b ldr r3, [r7, #4] 8009a28: 681b ldr r3, [r3, #0] 8009a2a: 4a30 ldr r2, [pc, #192] @ (8009aec ) 8009a2c: 4293 cmp r3, r2 8009a2e: d04a beq.n 8009ac6 8009a30: 687b ldr r3, [r7, #4] 8009a32: 681b ldr r3, [r3, #0] 8009a34: 4a2e ldr r2, [pc, #184] @ (8009af0 ) 8009a36: 4293 cmp r3, r2 8009a38: d045 beq.n 8009ac6 8009a3a: 687b ldr r3, [r7, #4] 8009a3c: 681b ldr r3, [r3, #0] 8009a3e: 4a2d ldr r2, [pc, #180] @ (8009af4 ) 8009a40: 4293 cmp r3, r2 8009a42: d040 beq.n 8009ac6 8009a44: 687b ldr r3, [r7, #4] 8009a46: 681b ldr r3, [r3, #0] 8009a48: 4a2b ldr r2, [pc, #172] @ (8009af8 ) 8009a4a: 4293 cmp r3, r2 8009a4c: d03b beq.n 8009ac6 8009a4e: 687b ldr r3, [r7, #4] 8009a50: 681b ldr r3, [r3, #0] 8009a52: 4a2a ldr r2, [pc, #168] @ (8009afc ) 8009a54: 4293 cmp r3, r2 8009a56: d036 beq.n 8009ac6 8009a58: 687b ldr r3, [r7, #4] 8009a5a: 681b ldr r3, [r3, #0] 8009a5c: 4a28 ldr r2, [pc, #160] @ (8009b00 ) 8009a5e: 4293 cmp r3, r2 8009a60: d031 beq.n 8009ac6 8009a62: 687b ldr r3, [r7, #4] 8009a64: 681b ldr r3, [r3, #0] 8009a66: 4a27 ldr r2, [pc, #156] @ (8009b04 ) 8009a68: 4293 cmp r3, r2 8009a6a: d02c beq.n 8009ac6 8009a6c: 687b ldr r3, [r7, #4] 8009a6e: 681b ldr r3, [r3, #0] 8009a70: 4a25 ldr r2, [pc, #148] @ (8009b08 ) 8009a72: 4293 cmp r3, r2 8009a74: d027 beq.n 8009ac6 8009a76: 687b ldr r3, [r7, #4] 8009a78: 681b ldr r3, [r3, #0] 8009a7a: 4a24 ldr r2, [pc, #144] @ (8009b0c ) 8009a7c: 4293 cmp r3, r2 8009a7e: d022 beq.n 8009ac6 8009a80: 687b ldr r3, [r7, #4] 8009a82: 681b ldr r3, [r3, #0] 8009a84: 4a22 ldr r2, [pc, #136] @ (8009b10 ) 8009a86: 4293 cmp r3, r2 8009a88: d01d beq.n 8009ac6 8009a8a: 687b ldr r3, [r7, #4] 8009a8c: 681b ldr r3, [r3, #0] 8009a8e: 4a21 ldr r2, [pc, #132] @ (8009b14 ) 8009a90: 4293 cmp r3, r2 8009a92: d018 beq.n 8009ac6 8009a94: 687b ldr r3, [r7, #4] 8009a96: 681b ldr r3, [r3, #0] 8009a98: 4a1f ldr r2, [pc, #124] @ (8009b18 ) 8009a9a: 4293 cmp r3, r2 8009a9c: d013 beq.n 8009ac6 8009a9e: 687b ldr r3, [r7, #4] 8009aa0: 681b ldr r3, [r3, #0] 8009aa2: 4a1e ldr r2, [pc, #120] @ (8009b1c ) 8009aa4: 4293 cmp r3, r2 8009aa6: d00e beq.n 8009ac6 8009aa8: 687b ldr r3, [r7, #4] 8009aaa: 681b ldr r3, [r3, #0] 8009aac: 4a1c ldr r2, [pc, #112] @ (8009b20 ) 8009aae: 4293 cmp r3, r2 8009ab0: d009 beq.n 8009ac6 8009ab2: 687b ldr r3, [r7, #4] 8009ab4: 681b ldr r3, [r3, #0] 8009ab6: 4a1b ldr r2, [pc, #108] @ (8009b24 ) 8009ab8: 4293 cmp r3, r2 8009aba: d004 beq.n 8009ac6 8009abc: 687b ldr r3, [r7, #4] 8009abe: 681b ldr r3, [r3, #0] 8009ac0: 4a19 ldr r2, [pc, #100] @ (8009b28 ) 8009ac2: 4293 cmp r3, r2 8009ac4: d132 bne.n 8009b2c 8009ac6: 2301 movs r3, #1 8009ac8: e031 b.n 8009b2e 8009aca: bf00 nop 8009acc: 40020010 .word 0x40020010 8009ad0: 40020028 .word 0x40020028 8009ad4: 40020040 .word 0x40020040 8009ad8: 40020058 .word 0x40020058 8009adc: 40020070 .word 0x40020070 8009ae0: 40020088 .word 0x40020088 8009ae4: 400200a0 .word 0x400200a0 8009ae8: 400200b8 .word 0x400200b8 8009aec: 40020410 .word 0x40020410 8009af0: 40020428 .word 0x40020428 8009af4: 40020440 .word 0x40020440 8009af8: 40020458 .word 0x40020458 8009afc: 40020470 .word 0x40020470 8009b00: 40020488 .word 0x40020488 8009b04: 400204a0 .word 0x400204a0 8009b08: 400204b8 .word 0x400204b8 8009b0c: 58025408 .word 0x58025408 8009b10: 5802541c .word 0x5802541c 8009b14: 58025430 .word 0x58025430 8009b18: 58025444 .word 0x58025444 8009b1c: 58025458 .word 0x58025458 8009b20: 5802546c .word 0x5802546c 8009b24: 58025480 .word 0x58025480 8009b28: 58025494 .word 0x58025494 8009b2c: 2300 movs r3, #0 8009b2e: 2b00 cmp r3, #0 8009b30: d028 beq.n 8009b84 { /* disable the DMAMUX sync overrun IT */ hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 8009b32: 687b ldr r3, [r7, #4] 8009b34: 6e1b ldr r3, [r3, #96] @ 0x60 8009b36: 681a ldr r2, [r3, #0] 8009b38: 687b ldr r3, [r7, #4] 8009b3a: 6e1b ldr r3, [r3, #96] @ 0x60 8009b3c: f422 7280 bic.w r2, r2, #256 @ 0x100 8009b40: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009b42: 687b ldr r3, [r7, #4] 8009b44: 6d9b ldr r3, [r3, #88] @ 0x58 8009b46: 60fb str r3, [r7, #12] regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); 8009b48: 687b ldr r3, [r7, #4] 8009b4a: 6ddb ldr r3, [r3, #92] @ 0x5c 8009b4c: f003 031f and.w r3, r3, #31 8009b50: 2201 movs r2, #1 8009b52: 409a lsls r2, r3 8009b54: 68fb ldr r3, [r7, #12] 8009b56: 605a str r2, [r3, #4] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 8009b58: 687b ldr r3, [r7, #4] 8009b5a: 6e5b ldr r3, [r3, #100] @ 0x64 8009b5c: 687a ldr r2, [r7, #4] 8009b5e: 6e92 ldr r2, [r2, #104] @ 0x68 8009b60: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 8009b62: 687b ldr r3, [r7, #4] 8009b64: 6edb ldr r3, [r3, #108] @ 0x6c 8009b66: 2b00 cmp r3, #0 8009b68: d00c beq.n 8009b84 { /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ /* disable the request gen overrun IT */ hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 8009b6a: 687b ldr r3, [r7, #4] 8009b6c: 6edb ldr r3, [r3, #108] @ 0x6c 8009b6e: 681a ldr r2, [r3, #0] 8009b70: 687b ldr r3, [r7, #4] 8009b72: 6edb ldr r3, [r3, #108] @ 0x6c 8009b74: f422 7280 bic.w r2, r2, #256 @ 0x100 8009b78: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 8009b7a: 687b ldr r3, [r7, #4] 8009b7c: 6f1b ldr r3, [r3, #112] @ 0x70 8009b7e: 687a ldr r2, [r7, #4] 8009b80: 6f52 ldr r2, [r2, #116] @ 0x74 8009b82: 605a str r2, [r3, #4] } } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8009b84: 687b ldr r3, [r7, #4] 8009b86: 2201 movs r2, #1 8009b88: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 8009b8c: 687b ldr r3, [r7, #4] 8009b8e: 2200 movs r2, #0 8009b90: f883 2034 strb.w r2, [r3, #52] @ 0x34 /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) 8009b94: 687b ldr r3, [r7, #4] 8009b96: 6d1b ldr r3, [r3, #80] @ 0x50 8009b98: 2b00 cmp r3, #0 8009b9a: d003 beq.n 8009ba4 { hdma->XferAbortCallback(hdma); 8009b9c: 687b ldr r3, [r7, #4] 8009b9e: 6d1b ldr r3, [r3, #80] @ 0x50 8009ba0: 6878 ldr r0, [r7, #4] 8009ba2: 4798 blx r3 } } } return HAL_OK; 8009ba4: 2300 movs r3, #0 } 8009ba6: 4618 mov r0, r3 8009ba8: 3710 adds r7, #16 8009baa: 46bd mov sp, r7 8009bac: bd80 pop {r7, pc} 8009bae: bf00 nop 08009bb0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8009bb0: b580 push {r7, lr} 8009bb2: b08a sub sp, #40 @ 0x28 8009bb4: af00 add r7, sp, #0 8009bb6: 6078 str r0, [r7, #4] uint32_t tmpisr_dma, tmpisr_bdma; uint32_t ccr_reg; __IO uint32_t count = 0U; 8009bb8: 2300 movs r3, #0 8009bba: 60fb str r3, [r7, #12] uint32_t timeout = SystemCoreClock / 9600U; 8009bbc: 4b67 ldr r3, [pc, #412] @ (8009d5c ) 8009bbe: 681b ldr r3, [r3, #0] 8009bc0: 4a67 ldr r2, [pc, #412] @ (8009d60 ) 8009bc2: fba2 2303 umull r2, r3, r2, r3 8009bc6: 0a9b lsrs r3, r3, #10 8009bc8: 627b str r3, [r7, #36] @ 0x24 /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 8009bca: 687b ldr r3, [r7, #4] 8009bcc: 6d9b ldr r3, [r3, #88] @ 0x58 8009bce: 623b str r3, [r7, #32] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 8009bd0: 687b ldr r3, [r7, #4] 8009bd2: 6d9b ldr r3, [r3, #88] @ 0x58 8009bd4: 61fb str r3, [r7, #28] tmpisr_dma = regs_dma->ISR; 8009bd6: 6a3b ldr r3, [r7, #32] 8009bd8: 681b ldr r3, [r3, #0] 8009bda: 61bb str r3, [r7, #24] tmpisr_bdma = regs_bdma->ISR; 8009bdc: 69fb ldr r3, [r7, #28] 8009bde: 681b ldr r3, [r3, #0] 8009be0: 617b str r3, [r7, #20] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 8009be2: 687b ldr r3, [r7, #4] 8009be4: 681b ldr r3, [r3, #0] 8009be6: 4a5f ldr r2, [pc, #380] @ (8009d64 ) 8009be8: 4293 cmp r3, r2 8009bea: d04a beq.n 8009c82 8009bec: 687b ldr r3, [r7, #4] 8009bee: 681b ldr r3, [r3, #0] 8009bf0: 4a5d ldr r2, [pc, #372] @ (8009d68 ) 8009bf2: 4293 cmp r3, r2 8009bf4: d045 beq.n 8009c82 8009bf6: 687b ldr r3, [r7, #4] 8009bf8: 681b ldr r3, [r3, #0] 8009bfa: 4a5c ldr r2, [pc, #368] @ (8009d6c ) 8009bfc: 4293 cmp r3, r2 8009bfe: d040 beq.n 8009c82 8009c00: 687b ldr r3, [r7, #4] 8009c02: 681b ldr r3, [r3, #0] 8009c04: 4a5a ldr r2, [pc, #360] @ (8009d70 ) 8009c06: 4293 cmp r3, r2 8009c08: d03b beq.n 8009c82 8009c0a: 687b ldr r3, [r7, #4] 8009c0c: 681b ldr r3, [r3, #0] 8009c0e: 4a59 ldr r2, [pc, #356] @ (8009d74 ) 8009c10: 4293 cmp r3, r2 8009c12: d036 beq.n 8009c82 8009c14: 687b ldr r3, [r7, #4] 8009c16: 681b ldr r3, [r3, #0] 8009c18: 4a57 ldr r2, [pc, #348] @ (8009d78 ) 8009c1a: 4293 cmp r3, r2 8009c1c: d031 beq.n 8009c82 8009c1e: 687b ldr r3, [r7, #4] 8009c20: 681b ldr r3, [r3, #0] 8009c22: 4a56 ldr r2, [pc, #344] @ (8009d7c ) 8009c24: 4293 cmp r3, r2 8009c26: d02c beq.n 8009c82 8009c28: 687b ldr r3, [r7, #4] 8009c2a: 681b ldr r3, [r3, #0] 8009c2c: 4a54 ldr r2, [pc, #336] @ (8009d80 ) 8009c2e: 4293 cmp r3, r2 8009c30: d027 beq.n 8009c82 8009c32: 687b ldr r3, [r7, #4] 8009c34: 681b ldr r3, [r3, #0] 8009c36: 4a53 ldr r2, [pc, #332] @ (8009d84 ) 8009c38: 4293 cmp r3, r2 8009c3a: d022 beq.n 8009c82 8009c3c: 687b ldr r3, [r7, #4] 8009c3e: 681b ldr r3, [r3, #0] 8009c40: 4a51 ldr r2, [pc, #324] @ (8009d88 ) 8009c42: 4293 cmp r3, r2 8009c44: d01d beq.n 8009c82 8009c46: 687b ldr r3, [r7, #4] 8009c48: 681b ldr r3, [r3, #0] 8009c4a: 4a50 ldr r2, [pc, #320] @ (8009d8c ) 8009c4c: 4293 cmp r3, r2 8009c4e: d018 beq.n 8009c82 8009c50: 687b ldr r3, [r7, #4] 8009c52: 681b ldr r3, [r3, #0] 8009c54: 4a4e ldr r2, [pc, #312] @ (8009d90 ) 8009c56: 4293 cmp r3, r2 8009c58: d013 beq.n 8009c82 8009c5a: 687b ldr r3, [r7, #4] 8009c5c: 681b ldr r3, [r3, #0] 8009c5e: 4a4d ldr r2, [pc, #308] @ (8009d94 ) 8009c60: 4293 cmp r3, r2 8009c62: d00e beq.n 8009c82 8009c64: 687b ldr r3, [r7, #4] 8009c66: 681b ldr r3, [r3, #0] 8009c68: 4a4b ldr r2, [pc, #300] @ (8009d98 ) 8009c6a: 4293 cmp r3, r2 8009c6c: d009 beq.n 8009c82 8009c6e: 687b ldr r3, [r7, #4] 8009c70: 681b ldr r3, [r3, #0] 8009c72: 4a4a ldr r2, [pc, #296] @ (8009d9c ) 8009c74: 4293 cmp r3, r2 8009c76: d004 beq.n 8009c82 8009c78: 687b ldr r3, [r7, #4] 8009c7a: 681b ldr r3, [r3, #0] 8009c7c: 4a48 ldr r2, [pc, #288] @ (8009da0 ) 8009c7e: 4293 cmp r3, r2 8009c80: d101 bne.n 8009c86 8009c82: 2301 movs r3, #1 8009c84: e000 b.n 8009c88 8009c86: 2300 movs r3, #0 8009c88: 2b00 cmp r3, #0 8009c8a: f000 842b beq.w 800a4e4 { /* Transfer Error Interrupt management ***************************************/ if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009c8e: 687b ldr r3, [r7, #4] 8009c90: 6ddb ldr r3, [r3, #92] @ 0x5c 8009c92: f003 031f and.w r3, r3, #31 8009c96: 2208 movs r2, #8 8009c98: 409a lsls r2, r3 8009c9a: 69bb ldr r3, [r7, #24] 8009c9c: 4013 ands r3, r2 8009c9e: 2b00 cmp r3, #0 8009ca0: f000 80a2 beq.w 8009de8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) 8009ca4: 687b ldr r3, [r7, #4] 8009ca6: 681b ldr r3, [r3, #0] 8009ca8: 4a2e ldr r2, [pc, #184] @ (8009d64 ) 8009caa: 4293 cmp r3, r2 8009cac: d04a beq.n 8009d44 8009cae: 687b ldr r3, [r7, #4] 8009cb0: 681b ldr r3, [r3, #0] 8009cb2: 4a2d ldr r2, [pc, #180] @ (8009d68 ) 8009cb4: 4293 cmp r3, r2 8009cb6: d045 beq.n 8009d44 8009cb8: 687b ldr r3, [r7, #4] 8009cba: 681b ldr r3, [r3, #0] 8009cbc: 4a2b ldr r2, [pc, #172] @ (8009d6c ) 8009cbe: 4293 cmp r3, r2 8009cc0: d040 beq.n 8009d44 8009cc2: 687b ldr r3, [r7, #4] 8009cc4: 681b ldr r3, [r3, #0] 8009cc6: 4a2a ldr r2, [pc, #168] @ (8009d70 ) 8009cc8: 4293 cmp r3, r2 8009cca: d03b beq.n 8009d44 8009ccc: 687b ldr r3, [r7, #4] 8009cce: 681b ldr r3, [r3, #0] 8009cd0: 4a28 ldr r2, [pc, #160] @ (8009d74 ) 8009cd2: 4293 cmp r3, r2 8009cd4: d036 beq.n 8009d44 8009cd6: 687b ldr r3, [r7, #4] 8009cd8: 681b ldr r3, [r3, #0] 8009cda: 4a27 ldr r2, [pc, #156] @ (8009d78 ) 8009cdc: 4293 cmp r3, r2 8009cde: d031 beq.n 8009d44 8009ce0: 687b ldr r3, [r7, #4] 8009ce2: 681b ldr r3, [r3, #0] 8009ce4: 4a25 ldr r2, [pc, #148] @ (8009d7c ) 8009ce6: 4293 cmp r3, r2 8009ce8: d02c beq.n 8009d44 8009cea: 687b ldr r3, [r7, #4] 8009cec: 681b ldr r3, [r3, #0] 8009cee: 4a24 ldr r2, [pc, #144] @ (8009d80 ) 8009cf0: 4293 cmp r3, r2 8009cf2: d027 beq.n 8009d44 8009cf4: 687b ldr r3, [r7, #4] 8009cf6: 681b ldr r3, [r3, #0] 8009cf8: 4a22 ldr r2, [pc, #136] @ (8009d84 ) 8009cfa: 4293 cmp r3, r2 8009cfc: d022 beq.n 8009d44 8009cfe: 687b ldr r3, [r7, #4] 8009d00: 681b ldr r3, [r3, #0] 8009d02: 4a21 ldr r2, [pc, #132] @ (8009d88 ) 8009d04: 4293 cmp r3, r2 8009d06: d01d beq.n 8009d44 8009d08: 687b ldr r3, [r7, #4] 8009d0a: 681b ldr r3, [r3, #0] 8009d0c: 4a1f ldr r2, [pc, #124] @ (8009d8c ) 8009d0e: 4293 cmp r3, r2 8009d10: d018 beq.n 8009d44 8009d12: 687b ldr r3, [r7, #4] 8009d14: 681b ldr r3, [r3, #0] 8009d16: 4a1e ldr r2, [pc, #120] @ (8009d90 ) 8009d18: 4293 cmp r3, r2 8009d1a: d013 beq.n 8009d44 8009d1c: 687b ldr r3, [r7, #4] 8009d1e: 681b ldr r3, [r3, #0] 8009d20: 4a1c ldr r2, [pc, #112] @ (8009d94 ) 8009d22: 4293 cmp r3, r2 8009d24: d00e beq.n 8009d44 8009d26: 687b ldr r3, [r7, #4] 8009d28: 681b ldr r3, [r3, #0] 8009d2a: 4a1b ldr r2, [pc, #108] @ (8009d98 ) 8009d2c: 4293 cmp r3, r2 8009d2e: d009 beq.n 8009d44 8009d30: 687b ldr r3, [r7, #4] 8009d32: 681b ldr r3, [r3, #0] 8009d34: 4a19 ldr r2, [pc, #100] @ (8009d9c ) 8009d36: 4293 cmp r3, r2 8009d38: d004 beq.n 8009d44 8009d3a: 687b ldr r3, [r7, #4] 8009d3c: 681b ldr r3, [r3, #0] 8009d3e: 4a18 ldr r2, [pc, #96] @ (8009da0 ) 8009d40: 4293 cmp r3, r2 8009d42: d12f bne.n 8009da4 8009d44: 687b ldr r3, [r7, #4] 8009d46: 681b ldr r3, [r3, #0] 8009d48: 681b ldr r3, [r3, #0] 8009d4a: f003 0304 and.w r3, r3, #4 8009d4e: 2b00 cmp r3, #0 8009d50: bf14 ite ne 8009d52: 2301 movne r3, #1 8009d54: 2300 moveq r3, #0 8009d56: b2db uxtb r3, r3 8009d58: e02e b.n 8009db8 8009d5a: bf00 nop 8009d5c: 24000034 .word 0x24000034 8009d60: 1b4e81b5 .word 0x1b4e81b5 8009d64: 40020010 .word 0x40020010 8009d68: 40020028 .word 0x40020028 8009d6c: 40020040 .word 0x40020040 8009d70: 40020058 .word 0x40020058 8009d74: 40020070 .word 0x40020070 8009d78: 40020088 .word 0x40020088 8009d7c: 400200a0 .word 0x400200a0 8009d80: 400200b8 .word 0x400200b8 8009d84: 40020410 .word 0x40020410 8009d88: 40020428 .word 0x40020428 8009d8c: 40020440 .word 0x40020440 8009d90: 40020458 .word 0x40020458 8009d94: 40020470 .word 0x40020470 8009d98: 40020488 .word 0x40020488 8009d9c: 400204a0 .word 0x400204a0 8009da0: 400204b8 .word 0x400204b8 8009da4: 687b ldr r3, [r7, #4] 8009da6: 681b ldr r3, [r3, #0] 8009da8: 681b ldr r3, [r3, #0] 8009daa: f003 0308 and.w r3, r3, #8 8009dae: 2b00 cmp r3, #0 8009db0: bf14 ite ne 8009db2: 2301 movne r3, #1 8009db4: 2300 moveq r3, #0 8009db6: b2db uxtb r3, r3 8009db8: 2b00 cmp r3, #0 8009dba: d015 beq.n 8009de8 { /* Disable the transfer error interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); 8009dbc: 687b ldr r3, [r7, #4] 8009dbe: 681b ldr r3, [r3, #0] 8009dc0: 681a ldr r2, [r3, #0] 8009dc2: 687b ldr r3, [r7, #4] 8009dc4: 681b ldr r3, [r3, #0] 8009dc6: f022 0204 bic.w r2, r2, #4 8009dca: 601a str r2, [r3, #0] /* Clear the transfer error flag */ regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009dcc: 687b ldr r3, [r7, #4] 8009dce: 6ddb ldr r3, [r3, #92] @ 0x5c 8009dd0: f003 031f and.w r3, r3, #31 8009dd4: 2208 movs r2, #8 8009dd6: 409a lsls r2, r3 8009dd8: 6a3b ldr r3, [r7, #32] 8009dda: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; 8009ddc: 687b ldr r3, [r7, #4] 8009dde: 6d5b ldr r3, [r3, #84] @ 0x54 8009de0: f043 0201 orr.w r2, r3, #1 8009de4: 687b ldr r3, [r7, #4] 8009de6: 655a str r2, [r3, #84] @ 0x54 } } /* FIFO Error Interrupt management ******************************************/ if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009de8: 687b ldr r3, [r7, #4] 8009dea: 6ddb ldr r3, [r3, #92] @ 0x5c 8009dec: f003 031f and.w r3, r3, #31 8009df0: 69ba ldr r2, [r7, #24] 8009df2: fa22 f303 lsr.w r3, r2, r3 8009df6: f003 0301 and.w r3, r3, #1 8009dfa: 2b00 cmp r3, #0 8009dfc: d06e beq.n 8009edc { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) 8009dfe: 687b ldr r3, [r7, #4] 8009e00: 681b ldr r3, [r3, #0] 8009e02: 4a69 ldr r2, [pc, #420] @ (8009fa8 ) 8009e04: 4293 cmp r3, r2 8009e06: d04a beq.n 8009e9e 8009e08: 687b ldr r3, [r7, #4] 8009e0a: 681b ldr r3, [r3, #0] 8009e0c: 4a67 ldr r2, [pc, #412] @ (8009fac ) 8009e0e: 4293 cmp r3, r2 8009e10: d045 beq.n 8009e9e 8009e12: 687b ldr r3, [r7, #4] 8009e14: 681b ldr r3, [r3, #0] 8009e16: 4a66 ldr r2, [pc, #408] @ (8009fb0 ) 8009e18: 4293 cmp r3, r2 8009e1a: d040 beq.n 8009e9e 8009e1c: 687b ldr r3, [r7, #4] 8009e1e: 681b ldr r3, [r3, #0] 8009e20: 4a64 ldr r2, [pc, #400] @ (8009fb4 ) 8009e22: 4293 cmp r3, r2 8009e24: d03b beq.n 8009e9e 8009e26: 687b ldr r3, [r7, #4] 8009e28: 681b ldr r3, [r3, #0] 8009e2a: 4a63 ldr r2, [pc, #396] @ (8009fb8 ) 8009e2c: 4293 cmp r3, r2 8009e2e: d036 beq.n 8009e9e 8009e30: 687b ldr r3, [r7, #4] 8009e32: 681b ldr r3, [r3, #0] 8009e34: 4a61 ldr r2, [pc, #388] @ (8009fbc ) 8009e36: 4293 cmp r3, r2 8009e38: d031 beq.n 8009e9e 8009e3a: 687b ldr r3, [r7, #4] 8009e3c: 681b ldr r3, [r3, #0] 8009e3e: 4a60 ldr r2, [pc, #384] @ (8009fc0 ) 8009e40: 4293 cmp r3, r2 8009e42: d02c beq.n 8009e9e 8009e44: 687b ldr r3, [r7, #4] 8009e46: 681b ldr r3, [r3, #0] 8009e48: 4a5e ldr r2, [pc, #376] @ (8009fc4 ) 8009e4a: 4293 cmp r3, r2 8009e4c: d027 beq.n 8009e9e 8009e4e: 687b ldr r3, [r7, #4] 8009e50: 681b ldr r3, [r3, #0] 8009e52: 4a5d ldr r2, [pc, #372] @ (8009fc8 ) 8009e54: 4293 cmp r3, r2 8009e56: d022 beq.n 8009e9e 8009e58: 687b ldr r3, [r7, #4] 8009e5a: 681b ldr r3, [r3, #0] 8009e5c: 4a5b ldr r2, [pc, #364] @ (8009fcc ) 8009e5e: 4293 cmp r3, r2 8009e60: d01d beq.n 8009e9e 8009e62: 687b ldr r3, [r7, #4] 8009e64: 681b ldr r3, [r3, #0] 8009e66: 4a5a ldr r2, [pc, #360] @ (8009fd0 ) 8009e68: 4293 cmp r3, r2 8009e6a: d018 beq.n 8009e9e 8009e6c: 687b ldr r3, [r7, #4] 8009e6e: 681b ldr r3, [r3, #0] 8009e70: 4a58 ldr r2, [pc, #352] @ (8009fd4 ) 8009e72: 4293 cmp r3, r2 8009e74: d013 beq.n 8009e9e 8009e76: 687b ldr r3, [r7, #4] 8009e78: 681b ldr r3, [r3, #0] 8009e7a: 4a57 ldr r2, [pc, #348] @ (8009fd8 ) 8009e7c: 4293 cmp r3, r2 8009e7e: d00e beq.n 8009e9e 8009e80: 687b ldr r3, [r7, #4] 8009e82: 681b ldr r3, [r3, #0] 8009e84: 4a55 ldr r2, [pc, #340] @ (8009fdc ) 8009e86: 4293 cmp r3, r2 8009e88: d009 beq.n 8009e9e 8009e8a: 687b ldr r3, [r7, #4] 8009e8c: 681b ldr r3, [r3, #0] 8009e8e: 4a54 ldr r2, [pc, #336] @ (8009fe0 ) 8009e90: 4293 cmp r3, r2 8009e92: d004 beq.n 8009e9e 8009e94: 687b ldr r3, [r7, #4] 8009e96: 681b ldr r3, [r3, #0] 8009e98: 4a52 ldr r2, [pc, #328] @ (8009fe4 ) 8009e9a: 4293 cmp r3, r2 8009e9c: d10a bne.n 8009eb4 8009e9e: 687b ldr r3, [r7, #4] 8009ea0: 681b ldr r3, [r3, #0] 8009ea2: 695b ldr r3, [r3, #20] 8009ea4: f003 0380 and.w r3, r3, #128 @ 0x80 8009ea8: 2b00 cmp r3, #0 8009eaa: bf14 ite ne 8009eac: 2301 movne r3, #1 8009eae: 2300 moveq r3, #0 8009eb0: b2db uxtb r3, r3 8009eb2: e003 b.n 8009ebc 8009eb4: 687b ldr r3, [r7, #4] 8009eb6: 681b ldr r3, [r3, #0] 8009eb8: 681b ldr r3, [r3, #0] 8009eba: 2300 movs r3, #0 8009ebc: 2b00 cmp r3, #0 8009ebe: d00d beq.n 8009edc { /* Clear the FIFO error flag */ regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009ec0: 687b ldr r3, [r7, #4] 8009ec2: 6ddb ldr r3, [r3, #92] @ 0x5c 8009ec4: f003 031f and.w r3, r3, #31 8009ec8: 2201 movs r2, #1 8009eca: 409a lsls r2, r3 8009ecc: 6a3b ldr r3, [r7, #32] 8009ece: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; 8009ed0: 687b ldr r3, [r7, #4] 8009ed2: 6d5b ldr r3, [r3, #84] @ 0x54 8009ed4: f043 0202 orr.w r2, r3, #2 8009ed8: 687b ldr r3, [r7, #4] 8009eda: 655a str r2, [r3, #84] @ 0x54 } } /* Direct Mode Error Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 8009edc: 687b ldr r3, [r7, #4] 8009ede: 6ddb ldr r3, [r3, #92] @ 0x5c 8009ee0: f003 031f and.w r3, r3, #31 8009ee4: 2204 movs r2, #4 8009ee6: 409a lsls r2, r3 8009ee8: 69bb ldr r3, [r7, #24] 8009eea: 4013 ands r3, r2 8009eec: 2b00 cmp r3, #0 8009eee: f000 808f beq.w 800a010 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) 8009ef2: 687b ldr r3, [r7, #4] 8009ef4: 681b ldr r3, [r3, #0] 8009ef6: 4a2c ldr r2, [pc, #176] @ (8009fa8 ) 8009ef8: 4293 cmp r3, r2 8009efa: d04a beq.n 8009f92 8009efc: 687b ldr r3, [r7, #4] 8009efe: 681b ldr r3, [r3, #0] 8009f00: 4a2a ldr r2, [pc, #168] @ (8009fac ) 8009f02: 4293 cmp r3, r2 8009f04: d045 beq.n 8009f92 8009f06: 687b ldr r3, [r7, #4] 8009f08: 681b ldr r3, [r3, #0] 8009f0a: 4a29 ldr r2, [pc, #164] @ (8009fb0 ) 8009f0c: 4293 cmp r3, r2 8009f0e: d040 beq.n 8009f92 8009f10: 687b ldr r3, [r7, #4] 8009f12: 681b ldr r3, [r3, #0] 8009f14: 4a27 ldr r2, [pc, #156] @ (8009fb4 ) 8009f16: 4293 cmp r3, r2 8009f18: d03b beq.n 8009f92 8009f1a: 687b ldr r3, [r7, #4] 8009f1c: 681b ldr r3, [r3, #0] 8009f1e: 4a26 ldr r2, [pc, #152] @ (8009fb8 ) 8009f20: 4293 cmp r3, r2 8009f22: d036 beq.n 8009f92 8009f24: 687b ldr r3, [r7, #4] 8009f26: 681b ldr r3, [r3, #0] 8009f28: 4a24 ldr r2, [pc, #144] @ (8009fbc ) 8009f2a: 4293 cmp r3, r2 8009f2c: d031 beq.n 8009f92 8009f2e: 687b ldr r3, [r7, #4] 8009f30: 681b ldr r3, [r3, #0] 8009f32: 4a23 ldr r2, [pc, #140] @ (8009fc0 ) 8009f34: 4293 cmp r3, r2 8009f36: d02c beq.n 8009f92 8009f38: 687b ldr r3, [r7, #4] 8009f3a: 681b ldr r3, [r3, #0] 8009f3c: 4a21 ldr r2, [pc, #132] @ (8009fc4 ) 8009f3e: 4293 cmp r3, r2 8009f40: d027 beq.n 8009f92 8009f42: 687b ldr r3, [r7, #4] 8009f44: 681b ldr r3, [r3, #0] 8009f46: 4a20 ldr r2, [pc, #128] @ (8009fc8 ) 8009f48: 4293 cmp r3, r2 8009f4a: d022 beq.n 8009f92 8009f4c: 687b ldr r3, [r7, #4] 8009f4e: 681b ldr r3, [r3, #0] 8009f50: 4a1e ldr r2, [pc, #120] @ (8009fcc ) 8009f52: 4293 cmp r3, r2 8009f54: d01d beq.n 8009f92 8009f56: 687b ldr r3, [r7, #4] 8009f58: 681b ldr r3, [r3, #0] 8009f5a: 4a1d ldr r2, [pc, #116] @ (8009fd0 ) 8009f5c: 4293 cmp r3, r2 8009f5e: d018 beq.n 8009f92 8009f60: 687b ldr r3, [r7, #4] 8009f62: 681b ldr r3, [r3, #0] 8009f64: 4a1b ldr r2, [pc, #108] @ (8009fd4 ) 8009f66: 4293 cmp r3, r2 8009f68: d013 beq.n 8009f92 8009f6a: 687b ldr r3, [r7, #4] 8009f6c: 681b ldr r3, [r3, #0] 8009f6e: 4a1a ldr r2, [pc, #104] @ (8009fd8 ) 8009f70: 4293 cmp r3, r2 8009f72: d00e beq.n 8009f92 8009f74: 687b ldr r3, [r7, #4] 8009f76: 681b ldr r3, [r3, #0] 8009f78: 4a18 ldr r2, [pc, #96] @ (8009fdc ) 8009f7a: 4293 cmp r3, r2 8009f7c: d009 beq.n 8009f92 8009f7e: 687b ldr r3, [r7, #4] 8009f80: 681b ldr r3, [r3, #0] 8009f82: 4a17 ldr r2, [pc, #92] @ (8009fe0 ) 8009f84: 4293 cmp r3, r2 8009f86: d004 beq.n 8009f92 8009f88: 687b ldr r3, [r7, #4] 8009f8a: 681b ldr r3, [r3, #0] 8009f8c: 4a15 ldr r2, [pc, #84] @ (8009fe4 ) 8009f8e: 4293 cmp r3, r2 8009f90: d12a bne.n 8009fe8 8009f92: 687b ldr r3, [r7, #4] 8009f94: 681b ldr r3, [r3, #0] 8009f96: 681b ldr r3, [r3, #0] 8009f98: f003 0302 and.w r3, r3, #2 8009f9c: 2b00 cmp r3, #0 8009f9e: bf14 ite ne 8009fa0: 2301 movne r3, #1 8009fa2: 2300 moveq r3, #0 8009fa4: b2db uxtb r3, r3 8009fa6: e023 b.n 8009ff0 8009fa8: 40020010 .word 0x40020010 8009fac: 40020028 .word 0x40020028 8009fb0: 40020040 .word 0x40020040 8009fb4: 40020058 .word 0x40020058 8009fb8: 40020070 .word 0x40020070 8009fbc: 40020088 .word 0x40020088 8009fc0: 400200a0 .word 0x400200a0 8009fc4: 400200b8 .word 0x400200b8 8009fc8: 40020410 .word 0x40020410 8009fcc: 40020428 .word 0x40020428 8009fd0: 40020440 .word 0x40020440 8009fd4: 40020458 .word 0x40020458 8009fd8: 40020470 .word 0x40020470 8009fdc: 40020488 .word 0x40020488 8009fe0: 400204a0 .word 0x400204a0 8009fe4: 400204b8 .word 0x400204b8 8009fe8: 687b ldr r3, [r7, #4] 8009fea: 681b ldr r3, [r3, #0] 8009fec: 681b ldr r3, [r3, #0] 8009fee: 2300 movs r3, #0 8009ff0: 2b00 cmp r3, #0 8009ff2: d00d beq.n 800a010 { /* Clear the direct mode error flag */ regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); 8009ff4: 687b ldr r3, [r7, #4] 8009ff6: 6ddb ldr r3, [r3, #92] @ 0x5c 8009ff8: f003 031f and.w r3, r3, #31 8009ffc: 2204 movs r2, #4 8009ffe: 409a lsls r2, r3 800a000: 6a3b ldr r3, [r7, #32] 800a002: 609a str r2, [r3, #8] /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; 800a004: 687b ldr r3, [r7, #4] 800a006: 6d5b ldr r3, [r3, #84] @ 0x54 800a008: f043 0204 orr.w r2, r3, #4 800a00c: 687b ldr r3, [r7, #4] 800a00e: 655a str r2, [r3, #84] @ 0x54 } } /* Half Transfer Complete Interrupt management ******************************/ if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800a010: 687b ldr r3, [r7, #4] 800a012: 6ddb ldr r3, [r3, #92] @ 0x5c 800a014: f003 031f and.w r3, r3, #31 800a018: 2210 movs r2, #16 800a01a: 409a lsls r2, r3 800a01c: 69bb ldr r3, [r7, #24] 800a01e: 4013 ands r3, r2 800a020: 2b00 cmp r3, #0 800a022: f000 80a6 beq.w 800a172 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) 800a026: 687b ldr r3, [r7, #4] 800a028: 681b ldr r3, [r3, #0] 800a02a: 4a85 ldr r2, [pc, #532] @ (800a240 ) 800a02c: 4293 cmp r3, r2 800a02e: d04a beq.n 800a0c6 800a030: 687b ldr r3, [r7, #4] 800a032: 681b ldr r3, [r3, #0] 800a034: 4a83 ldr r2, [pc, #524] @ (800a244 ) 800a036: 4293 cmp r3, r2 800a038: d045 beq.n 800a0c6 800a03a: 687b ldr r3, [r7, #4] 800a03c: 681b ldr r3, [r3, #0] 800a03e: 4a82 ldr r2, [pc, #520] @ (800a248 ) 800a040: 4293 cmp r3, r2 800a042: d040 beq.n 800a0c6 800a044: 687b ldr r3, [r7, #4] 800a046: 681b ldr r3, [r3, #0] 800a048: 4a80 ldr r2, [pc, #512] @ (800a24c ) 800a04a: 4293 cmp r3, r2 800a04c: d03b beq.n 800a0c6 800a04e: 687b ldr r3, [r7, #4] 800a050: 681b ldr r3, [r3, #0] 800a052: 4a7f ldr r2, [pc, #508] @ (800a250 ) 800a054: 4293 cmp r3, r2 800a056: d036 beq.n 800a0c6 800a058: 687b ldr r3, [r7, #4] 800a05a: 681b ldr r3, [r3, #0] 800a05c: 4a7d ldr r2, [pc, #500] @ (800a254 ) 800a05e: 4293 cmp r3, r2 800a060: d031 beq.n 800a0c6 800a062: 687b ldr r3, [r7, #4] 800a064: 681b ldr r3, [r3, #0] 800a066: 4a7c ldr r2, [pc, #496] @ (800a258 ) 800a068: 4293 cmp r3, r2 800a06a: d02c beq.n 800a0c6 800a06c: 687b ldr r3, [r7, #4] 800a06e: 681b ldr r3, [r3, #0] 800a070: 4a7a ldr r2, [pc, #488] @ (800a25c ) 800a072: 4293 cmp r3, r2 800a074: d027 beq.n 800a0c6 800a076: 687b ldr r3, [r7, #4] 800a078: 681b ldr r3, [r3, #0] 800a07a: 4a79 ldr r2, [pc, #484] @ (800a260 ) 800a07c: 4293 cmp r3, r2 800a07e: d022 beq.n 800a0c6 800a080: 687b ldr r3, [r7, #4] 800a082: 681b ldr r3, [r3, #0] 800a084: 4a77 ldr r2, [pc, #476] @ (800a264 ) 800a086: 4293 cmp r3, r2 800a088: d01d beq.n 800a0c6 800a08a: 687b ldr r3, [r7, #4] 800a08c: 681b ldr r3, [r3, #0] 800a08e: 4a76 ldr r2, [pc, #472] @ (800a268 ) 800a090: 4293 cmp r3, r2 800a092: d018 beq.n 800a0c6 800a094: 687b ldr r3, [r7, #4] 800a096: 681b ldr r3, [r3, #0] 800a098: 4a74 ldr r2, [pc, #464] @ (800a26c ) 800a09a: 4293 cmp r3, r2 800a09c: d013 beq.n 800a0c6 800a09e: 687b ldr r3, [r7, #4] 800a0a0: 681b ldr r3, [r3, #0] 800a0a2: 4a73 ldr r2, [pc, #460] @ (800a270 ) 800a0a4: 4293 cmp r3, r2 800a0a6: d00e beq.n 800a0c6 800a0a8: 687b ldr r3, [r7, #4] 800a0aa: 681b ldr r3, [r3, #0] 800a0ac: 4a71 ldr r2, [pc, #452] @ (800a274 ) 800a0ae: 4293 cmp r3, r2 800a0b0: d009 beq.n 800a0c6 800a0b2: 687b ldr r3, [r7, #4] 800a0b4: 681b ldr r3, [r3, #0] 800a0b6: 4a70 ldr r2, [pc, #448] @ (800a278 ) 800a0b8: 4293 cmp r3, r2 800a0ba: d004 beq.n 800a0c6 800a0bc: 687b ldr r3, [r7, #4] 800a0be: 681b ldr r3, [r3, #0] 800a0c0: 4a6e ldr r2, [pc, #440] @ (800a27c ) 800a0c2: 4293 cmp r3, r2 800a0c4: d10a bne.n 800a0dc 800a0c6: 687b ldr r3, [r7, #4] 800a0c8: 681b ldr r3, [r3, #0] 800a0ca: 681b ldr r3, [r3, #0] 800a0cc: f003 0308 and.w r3, r3, #8 800a0d0: 2b00 cmp r3, #0 800a0d2: bf14 ite ne 800a0d4: 2301 movne r3, #1 800a0d6: 2300 moveq r3, #0 800a0d8: b2db uxtb r3, r3 800a0da: e009 b.n 800a0f0 800a0dc: 687b ldr r3, [r7, #4] 800a0de: 681b ldr r3, [r3, #0] 800a0e0: 681b ldr r3, [r3, #0] 800a0e2: f003 0304 and.w r3, r3, #4 800a0e6: 2b00 cmp r3, #0 800a0e8: bf14 ite ne 800a0ea: 2301 movne r3, #1 800a0ec: 2300 moveq r3, #0 800a0ee: b2db uxtb r3, r3 800a0f0: 2b00 cmp r3, #0 800a0f2: d03e beq.n 800a172 { /* Clear the half transfer complete flag */ regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); 800a0f4: 687b ldr r3, [r7, #4] 800a0f6: 6ddb ldr r3, [r3, #92] @ 0x5c 800a0f8: f003 031f and.w r3, r3, #31 800a0fc: 2210 movs r2, #16 800a0fe: 409a lsls r2, r3 800a100: 6a3b ldr r3, [r7, #32] 800a102: 609a str r2, [r3, #8] /* Multi_Buffering mode enabled */ if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a104: 687b ldr r3, [r7, #4] 800a106: 681b ldr r3, [r3, #0] 800a108: 681b ldr r3, [r3, #0] 800a10a: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a10e: 2b00 cmp r3, #0 800a110: d018 beq.n 800a144 { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a112: 687b ldr r3, [r7, #4] 800a114: 681b ldr r3, [r3, #0] 800a116: 681b ldr r3, [r3, #0] 800a118: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a11c: 2b00 cmp r3, #0 800a11e: d108 bne.n 800a132 { if(hdma->XferHalfCpltCallback != NULL) 800a120: 687b ldr r3, [r7, #4] 800a122: 6c1b ldr r3, [r3, #64] @ 0x40 800a124: 2b00 cmp r3, #0 800a126: d024 beq.n 800a172 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a128: 687b ldr r3, [r7, #4] 800a12a: 6c1b ldr r3, [r3, #64] @ 0x40 800a12c: 6878 ldr r0, [r7, #4] 800a12e: 4798 blx r3 800a130: e01f b.n 800a172 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferM1HalfCpltCallback != NULL) 800a132: 687b ldr r3, [r7, #4] 800a134: 6c9b ldr r3, [r3, #72] @ 0x48 800a136: 2b00 cmp r3, #0 800a138: d01b beq.n 800a172 { /* Half transfer callback */ hdma->XferM1HalfCpltCallback(hdma); 800a13a: 687b ldr r3, [r7, #4] 800a13c: 6c9b ldr r3, [r3, #72] @ 0x48 800a13e: 6878 ldr r0, [r7, #4] 800a140: 4798 blx r3 800a142: e016 b.n 800a172 } } else { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a144: 687b ldr r3, [r7, #4] 800a146: 681b ldr r3, [r3, #0] 800a148: 681b ldr r3, [r3, #0] 800a14a: f403 7380 and.w r3, r3, #256 @ 0x100 800a14e: 2b00 cmp r3, #0 800a150: d107 bne.n 800a162 { /* Disable the half transfer interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a152: 687b ldr r3, [r7, #4] 800a154: 681b ldr r3, [r3, #0] 800a156: 681a ldr r2, [r3, #0] 800a158: 687b ldr r3, [r7, #4] 800a15a: 681b ldr r3, [r3, #0] 800a15c: f022 0208 bic.w r2, r2, #8 800a160: 601a str r2, [r3, #0] } if(hdma->XferHalfCpltCallback != NULL) 800a162: 687b ldr r3, [r7, #4] 800a164: 6c1b ldr r3, [r3, #64] @ 0x40 800a166: 2b00 cmp r3, #0 800a168: d003 beq.n 800a172 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a16a: 687b ldr r3, [r7, #4] 800a16c: 6c1b ldr r3, [r3, #64] @ 0x40 800a16e: 6878 ldr r0, [r7, #4] 800a170: 4798 blx r3 } } } } /* Transfer Complete Interrupt management ***********************************/ if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) 800a172: 687b ldr r3, [r7, #4] 800a174: 6ddb ldr r3, [r3, #92] @ 0x5c 800a176: f003 031f and.w r3, r3, #31 800a17a: 2220 movs r2, #32 800a17c: 409a lsls r2, r3 800a17e: 69bb ldr r3, [r7, #24] 800a180: 4013 ands r3, r2 800a182: 2b00 cmp r3, #0 800a184: f000 8110 beq.w 800a3a8 { if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) 800a188: 687b ldr r3, [r7, #4] 800a18a: 681b ldr r3, [r3, #0] 800a18c: 4a2c ldr r2, [pc, #176] @ (800a240 ) 800a18e: 4293 cmp r3, r2 800a190: d04a beq.n 800a228 800a192: 687b ldr r3, [r7, #4] 800a194: 681b ldr r3, [r3, #0] 800a196: 4a2b ldr r2, [pc, #172] @ (800a244 ) 800a198: 4293 cmp r3, r2 800a19a: d045 beq.n 800a228 800a19c: 687b ldr r3, [r7, #4] 800a19e: 681b ldr r3, [r3, #0] 800a1a0: 4a29 ldr r2, [pc, #164] @ (800a248 ) 800a1a2: 4293 cmp r3, r2 800a1a4: d040 beq.n 800a228 800a1a6: 687b ldr r3, [r7, #4] 800a1a8: 681b ldr r3, [r3, #0] 800a1aa: 4a28 ldr r2, [pc, #160] @ (800a24c ) 800a1ac: 4293 cmp r3, r2 800a1ae: d03b beq.n 800a228 800a1b0: 687b ldr r3, [r7, #4] 800a1b2: 681b ldr r3, [r3, #0] 800a1b4: 4a26 ldr r2, [pc, #152] @ (800a250 ) 800a1b6: 4293 cmp r3, r2 800a1b8: d036 beq.n 800a228 800a1ba: 687b ldr r3, [r7, #4] 800a1bc: 681b ldr r3, [r3, #0] 800a1be: 4a25 ldr r2, [pc, #148] @ (800a254 ) 800a1c0: 4293 cmp r3, r2 800a1c2: d031 beq.n 800a228 800a1c4: 687b ldr r3, [r7, #4] 800a1c6: 681b ldr r3, [r3, #0] 800a1c8: 4a23 ldr r2, [pc, #140] @ (800a258 ) 800a1ca: 4293 cmp r3, r2 800a1cc: d02c beq.n 800a228 800a1ce: 687b ldr r3, [r7, #4] 800a1d0: 681b ldr r3, [r3, #0] 800a1d2: 4a22 ldr r2, [pc, #136] @ (800a25c ) 800a1d4: 4293 cmp r3, r2 800a1d6: d027 beq.n 800a228 800a1d8: 687b ldr r3, [r7, #4] 800a1da: 681b ldr r3, [r3, #0] 800a1dc: 4a20 ldr r2, [pc, #128] @ (800a260 ) 800a1de: 4293 cmp r3, r2 800a1e0: d022 beq.n 800a228 800a1e2: 687b ldr r3, [r7, #4] 800a1e4: 681b ldr r3, [r3, #0] 800a1e6: 4a1f ldr r2, [pc, #124] @ (800a264 ) 800a1e8: 4293 cmp r3, r2 800a1ea: d01d beq.n 800a228 800a1ec: 687b ldr r3, [r7, #4] 800a1ee: 681b ldr r3, [r3, #0] 800a1f0: 4a1d ldr r2, [pc, #116] @ (800a268 ) 800a1f2: 4293 cmp r3, r2 800a1f4: d018 beq.n 800a228 800a1f6: 687b ldr r3, [r7, #4] 800a1f8: 681b ldr r3, [r3, #0] 800a1fa: 4a1c ldr r2, [pc, #112] @ (800a26c ) 800a1fc: 4293 cmp r3, r2 800a1fe: d013 beq.n 800a228 800a200: 687b ldr r3, [r7, #4] 800a202: 681b ldr r3, [r3, #0] 800a204: 4a1a ldr r2, [pc, #104] @ (800a270 ) 800a206: 4293 cmp r3, r2 800a208: d00e beq.n 800a228 800a20a: 687b ldr r3, [r7, #4] 800a20c: 681b ldr r3, [r3, #0] 800a20e: 4a19 ldr r2, [pc, #100] @ (800a274 ) 800a210: 4293 cmp r3, r2 800a212: d009 beq.n 800a228 800a214: 687b ldr r3, [r7, #4] 800a216: 681b ldr r3, [r3, #0] 800a218: 4a17 ldr r2, [pc, #92] @ (800a278 ) 800a21a: 4293 cmp r3, r2 800a21c: d004 beq.n 800a228 800a21e: 687b ldr r3, [r7, #4] 800a220: 681b ldr r3, [r3, #0] 800a222: 4a16 ldr r2, [pc, #88] @ (800a27c ) 800a224: 4293 cmp r3, r2 800a226: d12b bne.n 800a280 800a228: 687b ldr r3, [r7, #4] 800a22a: 681b ldr r3, [r3, #0] 800a22c: 681b ldr r3, [r3, #0] 800a22e: f003 0310 and.w r3, r3, #16 800a232: 2b00 cmp r3, #0 800a234: bf14 ite ne 800a236: 2301 movne r3, #1 800a238: 2300 moveq r3, #0 800a23a: b2db uxtb r3, r3 800a23c: e02a b.n 800a294 800a23e: bf00 nop 800a240: 40020010 .word 0x40020010 800a244: 40020028 .word 0x40020028 800a248: 40020040 .word 0x40020040 800a24c: 40020058 .word 0x40020058 800a250: 40020070 .word 0x40020070 800a254: 40020088 .word 0x40020088 800a258: 400200a0 .word 0x400200a0 800a25c: 400200b8 .word 0x400200b8 800a260: 40020410 .word 0x40020410 800a264: 40020428 .word 0x40020428 800a268: 40020440 .word 0x40020440 800a26c: 40020458 .word 0x40020458 800a270: 40020470 .word 0x40020470 800a274: 40020488 .word 0x40020488 800a278: 400204a0 .word 0x400204a0 800a27c: 400204b8 .word 0x400204b8 800a280: 687b ldr r3, [r7, #4] 800a282: 681b ldr r3, [r3, #0] 800a284: 681b ldr r3, [r3, #0] 800a286: f003 0302 and.w r3, r3, #2 800a28a: 2b00 cmp r3, #0 800a28c: bf14 ite ne 800a28e: 2301 movne r3, #1 800a290: 2300 moveq r3, #0 800a292: b2db uxtb r3, r3 800a294: 2b00 cmp r3, #0 800a296: f000 8087 beq.w 800a3a8 { /* Clear the transfer complete flag */ regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); 800a29a: 687b ldr r3, [r7, #4] 800a29c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a29e: f003 031f and.w r3, r3, #31 800a2a2: 2220 movs r2, #32 800a2a4: 409a lsls r2, r3 800a2a6: 6a3b ldr r3, [r7, #32] 800a2a8: 609a str r2, [r3, #8] if(HAL_DMA_STATE_ABORT == hdma->State) 800a2aa: 687b ldr r3, [r7, #4] 800a2ac: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 800a2b0: b2db uxtb r3, r3 800a2b2: 2b04 cmp r3, #4 800a2b4: d139 bne.n 800a32a { /* Disable all the transfer interrupts */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); 800a2b6: 687b ldr r3, [r7, #4] 800a2b8: 681b ldr r3, [r3, #0] 800a2ba: 681a ldr r2, [r3, #0] 800a2bc: 687b ldr r3, [r7, #4] 800a2be: 681b ldr r3, [r3, #0] 800a2c0: f022 0216 bic.w r2, r2, #22 800a2c4: 601a str r2, [r3, #0] ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); 800a2c6: 687b ldr r3, [r7, #4] 800a2c8: 681b ldr r3, [r3, #0] 800a2ca: 695a ldr r2, [r3, #20] 800a2cc: 687b ldr r3, [r7, #4] 800a2ce: 681b ldr r3, [r3, #0] 800a2d0: f022 0280 bic.w r2, r2, #128 @ 0x80 800a2d4: 615a str r2, [r3, #20] if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) 800a2d6: 687b ldr r3, [r7, #4] 800a2d8: 6c1b ldr r3, [r3, #64] @ 0x40 800a2da: 2b00 cmp r3, #0 800a2dc: d103 bne.n 800a2e6 800a2de: 687b ldr r3, [r7, #4] 800a2e0: 6c9b ldr r3, [r3, #72] @ 0x48 800a2e2: 2b00 cmp r3, #0 800a2e4: d007 beq.n 800a2f6 { ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); 800a2e6: 687b ldr r3, [r7, #4] 800a2e8: 681b ldr r3, [r3, #0] 800a2ea: 681a ldr r2, [r3, #0] 800a2ec: 687b ldr r3, [r7, #4] 800a2ee: 681b ldr r3, [r3, #0] 800a2f0: f022 0208 bic.w r2, r2, #8 800a2f4: 601a str r2, [r3, #0] } /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800a2f6: 687b ldr r3, [r7, #4] 800a2f8: 6ddb ldr r3, [r3, #92] @ 0x5c 800a2fa: f003 031f and.w r3, r3, #31 800a2fe: 223f movs r2, #63 @ 0x3f 800a300: 409a lsls r2, r3 800a302: 6a3b ldr r3, [r7, #32] 800a304: 609a str r2, [r3, #8] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a306: 687b ldr r3, [r7, #4] 800a308: 2201 movs r2, #1 800a30a: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a30e: 687b ldr r3, [r7, #4] 800a310: 2200 movs r2, #0 800a312: f883 2034 strb.w r2, [r3, #52] @ 0x34 if(hdma->XferAbortCallback != NULL) 800a316: 687b ldr r3, [r7, #4] 800a318: 6d1b ldr r3, [r3, #80] @ 0x50 800a31a: 2b00 cmp r3, #0 800a31c: f000 834a beq.w 800a9b4 { hdma->XferAbortCallback(hdma); 800a320: 687b ldr r3, [r7, #4] 800a322: 6d1b ldr r3, [r3, #80] @ 0x50 800a324: 6878 ldr r0, [r7, #4] 800a326: 4798 blx r3 } return; 800a328: e344 b.n 800a9b4 } if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) 800a32a: 687b ldr r3, [r7, #4] 800a32c: 681b ldr r3, [r3, #0] 800a32e: 681b ldr r3, [r3, #0] 800a330: f403 2380 and.w r3, r3, #262144 @ 0x40000 800a334: 2b00 cmp r3, #0 800a336: d018 beq.n 800a36a { /* Current memory buffer used is Memory 0 */ if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) 800a338: 687b ldr r3, [r7, #4] 800a33a: 681b ldr r3, [r3, #0] 800a33c: 681b ldr r3, [r3, #0] 800a33e: f403 2300 and.w r3, r3, #524288 @ 0x80000 800a342: 2b00 cmp r3, #0 800a344: d108 bne.n 800a358 { if(hdma->XferM1CpltCallback != NULL) 800a346: 687b ldr r3, [r7, #4] 800a348: 6c5b ldr r3, [r3, #68] @ 0x44 800a34a: 2b00 cmp r3, #0 800a34c: d02c beq.n 800a3a8 { /* Transfer complete Callback for memory1 */ hdma->XferM1CpltCallback(hdma); 800a34e: 687b ldr r3, [r7, #4] 800a350: 6c5b ldr r3, [r3, #68] @ 0x44 800a352: 6878 ldr r0, [r7, #4] 800a354: 4798 blx r3 800a356: e027 b.n 800a3a8 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a358: 687b ldr r3, [r7, #4] 800a35a: 6bdb ldr r3, [r3, #60] @ 0x3c 800a35c: 2b00 cmp r3, #0 800a35e: d023 beq.n 800a3a8 { /* Transfer complete Callback for memory0 */ hdma->XferCpltCallback(hdma); 800a360: 687b ldr r3, [r7, #4] 800a362: 6bdb ldr r3, [r3, #60] @ 0x3c 800a364: 6878 ldr r0, [r7, #4] 800a366: 4798 blx r3 800a368: e01e b.n 800a3a8 } } /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) 800a36a: 687b ldr r3, [r7, #4] 800a36c: 681b ldr r3, [r3, #0] 800a36e: 681b ldr r3, [r3, #0] 800a370: f403 7380 and.w r3, r3, #256 @ 0x100 800a374: 2b00 cmp r3, #0 800a376: d10f bne.n 800a398 { /* Disable the transfer complete interrupt */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); 800a378: 687b ldr r3, [r7, #4] 800a37a: 681b ldr r3, [r3, #0] 800a37c: 681a ldr r2, [r3, #0] 800a37e: 687b ldr r3, [r7, #4] 800a380: 681b ldr r3, [r3, #0] 800a382: f022 0210 bic.w r2, r2, #16 800a386: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a388: 687b ldr r3, [r7, #4] 800a38a: 2201 movs r2, #1 800a38c: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a390: 687b ldr r3, [r7, #4] 800a392: 2200 movs r2, #0 800a394: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a398: 687b ldr r3, [r7, #4] 800a39a: 6bdb ldr r3, [r3, #60] @ 0x3c 800a39c: 2b00 cmp r3, #0 800a39e: d003 beq.n 800a3a8 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a3a0: 687b ldr r3, [r7, #4] 800a3a2: 6bdb ldr r3, [r3, #60] @ 0x3c 800a3a4: 6878 ldr r0, [r7, #4] 800a3a6: 4798 blx r3 } } } /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) 800a3a8: 687b ldr r3, [r7, #4] 800a3aa: 6d5b ldr r3, [r3, #84] @ 0x54 800a3ac: 2b00 cmp r3, #0 800a3ae: f000 8306 beq.w 800a9be { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) 800a3b2: 687b ldr r3, [r7, #4] 800a3b4: 6d5b ldr r3, [r3, #84] @ 0x54 800a3b6: f003 0301 and.w r3, r3, #1 800a3ba: 2b00 cmp r3, #0 800a3bc: f000 8088 beq.w 800a4d0 { hdma->State = HAL_DMA_STATE_ABORT; 800a3c0: 687b ldr r3, [r7, #4] 800a3c2: 2204 movs r2, #4 800a3c4: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Disable the stream */ __HAL_DMA_DISABLE(hdma); 800a3c8: 687b ldr r3, [r7, #4] 800a3ca: 681b ldr r3, [r3, #0] 800a3cc: 4a7a ldr r2, [pc, #488] @ (800a5b8 ) 800a3ce: 4293 cmp r3, r2 800a3d0: d04a beq.n 800a468 800a3d2: 687b ldr r3, [r7, #4] 800a3d4: 681b ldr r3, [r3, #0] 800a3d6: 4a79 ldr r2, [pc, #484] @ (800a5bc ) 800a3d8: 4293 cmp r3, r2 800a3da: d045 beq.n 800a468 800a3dc: 687b ldr r3, [r7, #4] 800a3de: 681b ldr r3, [r3, #0] 800a3e0: 4a77 ldr r2, [pc, #476] @ (800a5c0 ) 800a3e2: 4293 cmp r3, r2 800a3e4: d040 beq.n 800a468 800a3e6: 687b ldr r3, [r7, #4] 800a3e8: 681b ldr r3, [r3, #0] 800a3ea: 4a76 ldr r2, [pc, #472] @ (800a5c4 ) 800a3ec: 4293 cmp r3, r2 800a3ee: d03b beq.n 800a468 800a3f0: 687b ldr r3, [r7, #4] 800a3f2: 681b ldr r3, [r3, #0] 800a3f4: 4a74 ldr r2, [pc, #464] @ (800a5c8 ) 800a3f6: 4293 cmp r3, r2 800a3f8: d036 beq.n 800a468 800a3fa: 687b ldr r3, [r7, #4] 800a3fc: 681b ldr r3, [r3, #0] 800a3fe: 4a73 ldr r2, [pc, #460] @ (800a5cc ) 800a400: 4293 cmp r3, r2 800a402: d031 beq.n 800a468 800a404: 687b ldr r3, [r7, #4] 800a406: 681b ldr r3, [r3, #0] 800a408: 4a71 ldr r2, [pc, #452] @ (800a5d0 ) 800a40a: 4293 cmp r3, r2 800a40c: d02c beq.n 800a468 800a40e: 687b ldr r3, [r7, #4] 800a410: 681b ldr r3, [r3, #0] 800a412: 4a70 ldr r2, [pc, #448] @ (800a5d4 ) 800a414: 4293 cmp r3, r2 800a416: d027 beq.n 800a468 800a418: 687b ldr r3, [r7, #4] 800a41a: 681b ldr r3, [r3, #0] 800a41c: 4a6e ldr r2, [pc, #440] @ (800a5d8 ) 800a41e: 4293 cmp r3, r2 800a420: d022 beq.n 800a468 800a422: 687b ldr r3, [r7, #4] 800a424: 681b ldr r3, [r3, #0] 800a426: 4a6d ldr r2, [pc, #436] @ (800a5dc ) 800a428: 4293 cmp r3, r2 800a42a: d01d beq.n 800a468 800a42c: 687b ldr r3, [r7, #4] 800a42e: 681b ldr r3, [r3, #0] 800a430: 4a6b ldr r2, [pc, #428] @ (800a5e0 ) 800a432: 4293 cmp r3, r2 800a434: d018 beq.n 800a468 800a436: 687b ldr r3, [r7, #4] 800a438: 681b ldr r3, [r3, #0] 800a43a: 4a6a ldr r2, [pc, #424] @ (800a5e4 ) 800a43c: 4293 cmp r3, r2 800a43e: d013 beq.n 800a468 800a440: 687b ldr r3, [r7, #4] 800a442: 681b ldr r3, [r3, #0] 800a444: 4a68 ldr r2, [pc, #416] @ (800a5e8 ) 800a446: 4293 cmp r3, r2 800a448: d00e beq.n 800a468 800a44a: 687b ldr r3, [r7, #4] 800a44c: 681b ldr r3, [r3, #0] 800a44e: 4a67 ldr r2, [pc, #412] @ (800a5ec ) 800a450: 4293 cmp r3, r2 800a452: d009 beq.n 800a468 800a454: 687b ldr r3, [r7, #4] 800a456: 681b ldr r3, [r3, #0] 800a458: 4a65 ldr r2, [pc, #404] @ (800a5f0 ) 800a45a: 4293 cmp r3, r2 800a45c: d004 beq.n 800a468 800a45e: 687b ldr r3, [r7, #4] 800a460: 681b ldr r3, [r3, #0] 800a462: 4a64 ldr r2, [pc, #400] @ (800a5f4 ) 800a464: 4293 cmp r3, r2 800a466: d108 bne.n 800a47a 800a468: 687b ldr r3, [r7, #4] 800a46a: 681b ldr r3, [r3, #0] 800a46c: 681a ldr r2, [r3, #0] 800a46e: 687b ldr r3, [r7, #4] 800a470: 681b ldr r3, [r3, #0] 800a472: f022 0201 bic.w r2, r2, #1 800a476: 601a str r2, [r3, #0] 800a478: e007 b.n 800a48a 800a47a: 687b ldr r3, [r7, #4] 800a47c: 681b ldr r3, [r3, #0] 800a47e: 681a ldr r2, [r3, #0] 800a480: 687b ldr r3, [r7, #4] 800a482: 681b ldr r3, [r3, #0] 800a484: f022 0201 bic.w r2, r2, #1 800a488: 601a str r2, [r3, #0] do { if (++count > timeout) 800a48a: 68fb ldr r3, [r7, #12] 800a48c: 3301 adds r3, #1 800a48e: 60fb str r3, [r7, #12] 800a490: 6a7a ldr r2, [r7, #36] @ 0x24 800a492: 429a cmp r2, r3 800a494: d307 bcc.n 800a4a6 { break; } } while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); 800a496: 687b ldr r3, [r7, #4] 800a498: 681b ldr r3, [r3, #0] 800a49a: 681b ldr r3, [r3, #0] 800a49c: f003 0301 and.w r3, r3, #1 800a4a0: 2b00 cmp r3, #0 800a4a2: d1f2 bne.n 800a48a 800a4a4: e000 b.n 800a4a8 break; 800a4a6: bf00 nop if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) 800a4a8: 687b ldr r3, [r7, #4] 800a4aa: 681b ldr r3, [r3, #0] 800a4ac: 681b ldr r3, [r3, #0] 800a4ae: f003 0301 and.w r3, r3, #1 800a4b2: 2b00 cmp r3, #0 800a4b4: d004 beq.n 800a4c0 { /* Change the DMA state to error if DMA disable fails */ hdma->State = HAL_DMA_STATE_ERROR; 800a4b6: 687b ldr r3, [r7, #4] 800a4b8: 2203 movs r2, #3 800a4ba: f883 2035 strb.w r2, [r3, #53] @ 0x35 800a4be: e003 b.n 800a4c8 } else { /* Change the DMA state to Ready if DMA disable success */ hdma->State = HAL_DMA_STATE_READY; 800a4c0: 687b ldr r3, [r7, #4] 800a4c2: 2201 movs r2, #1 800a4c4: f883 2035 strb.w r2, [r3, #53] @ 0x35 } /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a4c8: 687b ldr r3, [r7, #4] 800a4ca: 2200 movs r2, #0 800a4cc: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferErrorCallback != NULL) 800a4d0: 687b ldr r3, [r7, #4] 800a4d2: 6cdb ldr r3, [r3, #76] @ 0x4c 800a4d4: 2b00 cmp r3, #0 800a4d6: f000 8272 beq.w 800a9be { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a4da: 687b ldr r3, [r7, #4] 800a4dc: 6cdb ldr r3, [r3, #76] @ 0x4c 800a4de: 6878 ldr r0, [r7, #4] 800a4e0: 4798 blx r3 800a4e2: e26c b.n 800a9be } } } else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800a4e4: 687b ldr r3, [r7, #4] 800a4e6: 681b ldr r3, [r3, #0] 800a4e8: 4a43 ldr r2, [pc, #268] @ (800a5f8 ) 800a4ea: 4293 cmp r3, r2 800a4ec: d022 beq.n 800a534 800a4ee: 687b ldr r3, [r7, #4] 800a4f0: 681b ldr r3, [r3, #0] 800a4f2: 4a42 ldr r2, [pc, #264] @ (800a5fc ) 800a4f4: 4293 cmp r3, r2 800a4f6: d01d beq.n 800a534 800a4f8: 687b ldr r3, [r7, #4] 800a4fa: 681b ldr r3, [r3, #0] 800a4fc: 4a40 ldr r2, [pc, #256] @ (800a600 ) 800a4fe: 4293 cmp r3, r2 800a500: d018 beq.n 800a534 800a502: 687b ldr r3, [r7, #4] 800a504: 681b ldr r3, [r3, #0] 800a506: 4a3f ldr r2, [pc, #252] @ (800a604 ) 800a508: 4293 cmp r3, r2 800a50a: d013 beq.n 800a534 800a50c: 687b ldr r3, [r7, #4] 800a50e: 681b ldr r3, [r3, #0] 800a510: 4a3d ldr r2, [pc, #244] @ (800a608 ) 800a512: 4293 cmp r3, r2 800a514: d00e beq.n 800a534 800a516: 687b ldr r3, [r7, #4] 800a518: 681b ldr r3, [r3, #0] 800a51a: 4a3c ldr r2, [pc, #240] @ (800a60c ) 800a51c: 4293 cmp r3, r2 800a51e: d009 beq.n 800a534 800a520: 687b ldr r3, [r7, #4] 800a522: 681b ldr r3, [r3, #0] 800a524: 4a3a ldr r2, [pc, #232] @ (800a610 ) 800a526: 4293 cmp r3, r2 800a528: d004 beq.n 800a534 800a52a: 687b ldr r3, [r7, #4] 800a52c: 681b ldr r3, [r3, #0] 800a52e: 4a39 ldr r2, [pc, #228] @ (800a614 ) 800a530: 4293 cmp r3, r2 800a532: d101 bne.n 800a538 800a534: 2301 movs r3, #1 800a536: e000 b.n 800a53a 800a538: 2300 movs r3, #0 800a53a: 2b00 cmp r3, #0 800a53c: f000 823f beq.w 800a9be { ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); 800a540: 687b ldr r3, [r7, #4] 800a542: 681b ldr r3, [r3, #0] 800a544: 681b ldr r3, [r3, #0] 800a546: 613b str r3, [r7, #16] /* Half Transfer Complete Interrupt management ******************************/ if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) 800a548: 687b ldr r3, [r7, #4] 800a54a: 6ddb ldr r3, [r3, #92] @ 0x5c 800a54c: f003 031f and.w r3, r3, #31 800a550: 2204 movs r2, #4 800a552: 409a lsls r2, r3 800a554: 697b ldr r3, [r7, #20] 800a556: 4013 ands r3, r2 800a558: 2b00 cmp r3, #0 800a55a: f000 80cd beq.w 800a6f8 800a55e: 693b ldr r3, [r7, #16] 800a560: f003 0304 and.w r3, r3, #4 800a564: 2b00 cmp r3, #0 800a566: f000 80c7 beq.w 800a6f8 { /* Clear the half transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); 800a56a: 687b ldr r3, [r7, #4] 800a56c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a56e: f003 031f and.w r3, r3, #31 800a572: 2204 movs r2, #4 800a574: 409a lsls r2, r3 800a576: 69fb ldr r3, [r7, #28] 800a578: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a57a: 693b ldr r3, [r7, #16] 800a57c: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a580: 2b00 cmp r3, #0 800a582: d049 beq.n 800a618 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a584: 693b ldr r3, [r7, #16] 800a586: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a58a: 2b00 cmp r3, #0 800a58c: d109 bne.n 800a5a2 { if(hdma->XferM1HalfCpltCallback != NULL) 800a58e: 687b ldr r3, [r7, #4] 800a590: 6c9b ldr r3, [r3, #72] @ 0x48 800a592: 2b00 cmp r3, #0 800a594: f000 8210 beq.w 800a9b8 { /* Half transfer Callback for Memory 1 */ hdma->XferM1HalfCpltCallback(hdma); 800a598: 687b ldr r3, [r7, #4] 800a59a: 6c9b ldr r3, [r3, #72] @ 0x48 800a59c: 6878 ldr r0, [r7, #4] 800a59e: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a5a0: e20a b.n 800a9b8 } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferHalfCpltCallback != NULL) 800a5a2: 687b ldr r3, [r7, #4] 800a5a4: 6c1b ldr r3, [r3, #64] @ 0x40 800a5a6: 2b00 cmp r3, #0 800a5a8: f000 8206 beq.w 800a9b8 { /* Half transfer Callback for Memory 0 */ hdma->XferHalfCpltCallback(hdma); 800a5ac: 687b ldr r3, [r7, #4] 800a5ae: 6c1b ldr r3, [r3, #64] @ 0x40 800a5b0: 6878 ldr r0, [r7, #4] 800a5b2: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a5b4: e200 b.n 800a9b8 800a5b6: bf00 nop 800a5b8: 40020010 .word 0x40020010 800a5bc: 40020028 .word 0x40020028 800a5c0: 40020040 .word 0x40020040 800a5c4: 40020058 .word 0x40020058 800a5c8: 40020070 .word 0x40020070 800a5cc: 40020088 .word 0x40020088 800a5d0: 400200a0 .word 0x400200a0 800a5d4: 400200b8 .word 0x400200b8 800a5d8: 40020410 .word 0x40020410 800a5dc: 40020428 .word 0x40020428 800a5e0: 40020440 .word 0x40020440 800a5e4: 40020458 .word 0x40020458 800a5e8: 40020470 .word 0x40020470 800a5ec: 40020488 .word 0x40020488 800a5f0: 400204a0 .word 0x400204a0 800a5f4: 400204b8 .word 0x400204b8 800a5f8: 58025408 .word 0x58025408 800a5fc: 5802541c .word 0x5802541c 800a600: 58025430 .word 0x58025430 800a604: 58025444 .word 0x58025444 800a608: 58025458 .word 0x58025458 800a60c: 5802546c .word 0x5802546c 800a610: 58025480 .word 0x58025480 800a614: 58025494 .word 0x58025494 } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a618: 693b ldr r3, [r7, #16] 800a61a: f003 0320 and.w r3, r3, #32 800a61e: 2b00 cmp r3, #0 800a620: d160 bne.n 800a6e4 { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800a622: 687b ldr r3, [r7, #4] 800a624: 681b ldr r3, [r3, #0] 800a626: 4a7f ldr r2, [pc, #508] @ (800a824 ) 800a628: 4293 cmp r3, r2 800a62a: d04a beq.n 800a6c2 800a62c: 687b ldr r3, [r7, #4] 800a62e: 681b ldr r3, [r3, #0] 800a630: 4a7d ldr r2, [pc, #500] @ (800a828 ) 800a632: 4293 cmp r3, r2 800a634: d045 beq.n 800a6c2 800a636: 687b ldr r3, [r7, #4] 800a638: 681b ldr r3, [r3, #0] 800a63a: 4a7c ldr r2, [pc, #496] @ (800a82c ) 800a63c: 4293 cmp r3, r2 800a63e: d040 beq.n 800a6c2 800a640: 687b ldr r3, [r7, #4] 800a642: 681b ldr r3, [r3, #0] 800a644: 4a7a ldr r2, [pc, #488] @ (800a830 ) 800a646: 4293 cmp r3, r2 800a648: d03b beq.n 800a6c2 800a64a: 687b ldr r3, [r7, #4] 800a64c: 681b ldr r3, [r3, #0] 800a64e: 4a79 ldr r2, [pc, #484] @ (800a834 ) 800a650: 4293 cmp r3, r2 800a652: d036 beq.n 800a6c2 800a654: 687b ldr r3, [r7, #4] 800a656: 681b ldr r3, [r3, #0] 800a658: 4a77 ldr r2, [pc, #476] @ (800a838 ) 800a65a: 4293 cmp r3, r2 800a65c: d031 beq.n 800a6c2 800a65e: 687b ldr r3, [r7, #4] 800a660: 681b ldr r3, [r3, #0] 800a662: 4a76 ldr r2, [pc, #472] @ (800a83c ) 800a664: 4293 cmp r3, r2 800a666: d02c beq.n 800a6c2 800a668: 687b ldr r3, [r7, #4] 800a66a: 681b ldr r3, [r3, #0] 800a66c: 4a74 ldr r2, [pc, #464] @ (800a840 ) 800a66e: 4293 cmp r3, r2 800a670: d027 beq.n 800a6c2 800a672: 687b ldr r3, [r7, #4] 800a674: 681b ldr r3, [r3, #0] 800a676: 4a73 ldr r2, [pc, #460] @ (800a844 ) 800a678: 4293 cmp r3, r2 800a67a: d022 beq.n 800a6c2 800a67c: 687b ldr r3, [r7, #4] 800a67e: 681b ldr r3, [r3, #0] 800a680: 4a71 ldr r2, [pc, #452] @ (800a848 ) 800a682: 4293 cmp r3, r2 800a684: d01d beq.n 800a6c2 800a686: 687b ldr r3, [r7, #4] 800a688: 681b ldr r3, [r3, #0] 800a68a: 4a70 ldr r2, [pc, #448] @ (800a84c ) 800a68c: 4293 cmp r3, r2 800a68e: d018 beq.n 800a6c2 800a690: 687b ldr r3, [r7, #4] 800a692: 681b ldr r3, [r3, #0] 800a694: 4a6e ldr r2, [pc, #440] @ (800a850 ) 800a696: 4293 cmp r3, r2 800a698: d013 beq.n 800a6c2 800a69a: 687b ldr r3, [r7, #4] 800a69c: 681b ldr r3, [r3, #0] 800a69e: 4a6d ldr r2, [pc, #436] @ (800a854 ) 800a6a0: 4293 cmp r3, r2 800a6a2: d00e beq.n 800a6c2 800a6a4: 687b ldr r3, [r7, #4] 800a6a6: 681b ldr r3, [r3, #0] 800a6a8: 4a6b ldr r2, [pc, #428] @ (800a858 ) 800a6aa: 4293 cmp r3, r2 800a6ac: d009 beq.n 800a6c2 800a6ae: 687b ldr r3, [r7, #4] 800a6b0: 681b ldr r3, [r3, #0] 800a6b2: 4a6a ldr r2, [pc, #424] @ (800a85c ) 800a6b4: 4293 cmp r3, r2 800a6b6: d004 beq.n 800a6c2 800a6b8: 687b ldr r3, [r7, #4] 800a6ba: 681b ldr r3, [r3, #0] 800a6bc: 4a68 ldr r2, [pc, #416] @ (800a860 ) 800a6be: 4293 cmp r3, r2 800a6c0: d108 bne.n 800a6d4 800a6c2: 687b ldr r3, [r7, #4] 800a6c4: 681b ldr r3, [r3, #0] 800a6c6: 681a ldr r2, [r3, #0] 800a6c8: 687b ldr r3, [r7, #4] 800a6ca: 681b ldr r3, [r3, #0] 800a6cc: f022 0208 bic.w r2, r2, #8 800a6d0: 601a str r2, [r3, #0] 800a6d2: e007 b.n 800a6e4 800a6d4: 687b ldr r3, [r7, #4] 800a6d6: 681b ldr r3, [r3, #0] 800a6d8: 681a ldr r2, [r3, #0] 800a6da: 687b ldr r3, [r7, #4] 800a6dc: 681b ldr r3, [r3, #0] 800a6de: f022 0204 bic.w r2, r2, #4 800a6e2: 601a str r2, [r3, #0] } /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if(hdma->XferHalfCpltCallback != NULL) 800a6e4: 687b ldr r3, [r7, #4] 800a6e6: 6c1b ldr r3, [r3, #64] @ 0x40 800a6e8: 2b00 cmp r3, #0 800a6ea: f000 8165 beq.w 800a9b8 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 800a6ee: 687b ldr r3, [r7, #4] 800a6f0: 6c1b ldr r3, [r3, #64] @ 0x40 800a6f2: 6878 ldr r0, [r7, #4] 800a6f4: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a6f6: e15f b.n 800a9b8 } } } /* Transfer Complete Interrupt management ***********************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) 800a6f8: 687b ldr r3, [r7, #4] 800a6fa: 6ddb ldr r3, [r3, #92] @ 0x5c 800a6fc: f003 031f and.w r3, r3, #31 800a700: 2202 movs r2, #2 800a702: 409a lsls r2, r3 800a704: 697b ldr r3, [r7, #20] 800a706: 4013 ands r3, r2 800a708: 2b00 cmp r3, #0 800a70a: f000 80c5 beq.w 800a898 800a70e: 693b ldr r3, [r7, #16] 800a710: f003 0302 and.w r3, r3, #2 800a714: 2b00 cmp r3, #0 800a716: f000 80bf beq.w 800a898 { /* Clear the transfer complete flag */ regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); 800a71a: 687b ldr r3, [r7, #4] 800a71c: 6ddb ldr r3, [r3, #92] @ 0x5c 800a71e: f003 031f and.w r3, r3, #31 800a722: 2202 movs r2, #2 800a724: 409a lsls r2, r3 800a726: 69fb ldr r3, [r7, #28] 800a728: 605a str r2, [r3, #4] /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a72a: 693b ldr r3, [r7, #16] 800a72c: f403 4300 and.w r3, r3, #32768 @ 0x8000 800a730: 2b00 cmp r3, #0 800a732: d018 beq.n 800a766 { /* Current memory buffer used is Memory 0 */ if((ccr_reg & BDMA_CCR_CT) == 0U) 800a734: 693b ldr r3, [r7, #16] 800a736: f403 3380 and.w r3, r3, #65536 @ 0x10000 800a73a: 2b00 cmp r3, #0 800a73c: d109 bne.n 800a752 { if(hdma->XferM1CpltCallback != NULL) 800a73e: 687b ldr r3, [r7, #4] 800a740: 6c5b ldr r3, [r3, #68] @ 0x44 800a742: 2b00 cmp r3, #0 800a744: f000 813a beq.w 800a9bc { /* Transfer complete Callback for Memory 1 */ hdma->XferM1CpltCallback(hdma); 800a748: 687b ldr r3, [r7, #4] 800a74a: 6c5b ldr r3, [r3, #68] @ 0x44 800a74c: 6878 ldr r0, [r7, #4] 800a74e: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a750: e134 b.n 800a9bc } } /* Current memory buffer used is Memory 1 */ else { if(hdma->XferCpltCallback != NULL) 800a752: 687b ldr r3, [r7, #4] 800a754: 6bdb ldr r3, [r3, #60] @ 0x3c 800a756: 2b00 cmp r3, #0 800a758: f000 8130 beq.w 800a9bc { /* Transfer complete Callback for Memory 0 */ hdma->XferCpltCallback(hdma); 800a75c: 687b ldr r3, [r7, #4] 800a75e: 6bdb ldr r3, [r3, #60] @ 0x3c 800a760: 6878 ldr r0, [r7, #4] 800a762: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a764: e12a b.n 800a9bc } } } else { if((ccr_reg & BDMA_CCR_CIRC) == 0U) 800a766: 693b ldr r3, [r7, #16] 800a768: f003 0320 and.w r3, r3, #32 800a76c: 2b00 cmp r3, #0 800a76e: f040 8089 bne.w 800a884 { /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 800a772: 687b ldr r3, [r7, #4] 800a774: 681b ldr r3, [r3, #0] 800a776: 4a2b ldr r2, [pc, #172] @ (800a824 ) 800a778: 4293 cmp r3, r2 800a77a: d04a beq.n 800a812 800a77c: 687b ldr r3, [r7, #4] 800a77e: 681b ldr r3, [r3, #0] 800a780: 4a29 ldr r2, [pc, #164] @ (800a828 ) 800a782: 4293 cmp r3, r2 800a784: d045 beq.n 800a812 800a786: 687b ldr r3, [r7, #4] 800a788: 681b ldr r3, [r3, #0] 800a78a: 4a28 ldr r2, [pc, #160] @ (800a82c ) 800a78c: 4293 cmp r3, r2 800a78e: d040 beq.n 800a812 800a790: 687b ldr r3, [r7, #4] 800a792: 681b ldr r3, [r3, #0] 800a794: 4a26 ldr r2, [pc, #152] @ (800a830 ) 800a796: 4293 cmp r3, r2 800a798: d03b beq.n 800a812 800a79a: 687b ldr r3, [r7, #4] 800a79c: 681b ldr r3, [r3, #0] 800a79e: 4a25 ldr r2, [pc, #148] @ (800a834 ) 800a7a0: 4293 cmp r3, r2 800a7a2: d036 beq.n 800a812 800a7a4: 687b ldr r3, [r7, #4] 800a7a6: 681b ldr r3, [r3, #0] 800a7a8: 4a23 ldr r2, [pc, #140] @ (800a838 ) 800a7aa: 4293 cmp r3, r2 800a7ac: d031 beq.n 800a812 800a7ae: 687b ldr r3, [r7, #4] 800a7b0: 681b ldr r3, [r3, #0] 800a7b2: 4a22 ldr r2, [pc, #136] @ (800a83c ) 800a7b4: 4293 cmp r3, r2 800a7b6: d02c beq.n 800a812 800a7b8: 687b ldr r3, [r7, #4] 800a7ba: 681b ldr r3, [r3, #0] 800a7bc: 4a20 ldr r2, [pc, #128] @ (800a840 ) 800a7be: 4293 cmp r3, r2 800a7c0: d027 beq.n 800a812 800a7c2: 687b ldr r3, [r7, #4] 800a7c4: 681b ldr r3, [r3, #0] 800a7c6: 4a1f ldr r2, [pc, #124] @ (800a844 ) 800a7c8: 4293 cmp r3, r2 800a7ca: d022 beq.n 800a812 800a7cc: 687b ldr r3, [r7, #4] 800a7ce: 681b ldr r3, [r3, #0] 800a7d0: 4a1d ldr r2, [pc, #116] @ (800a848 ) 800a7d2: 4293 cmp r3, r2 800a7d4: d01d beq.n 800a812 800a7d6: 687b ldr r3, [r7, #4] 800a7d8: 681b ldr r3, [r3, #0] 800a7da: 4a1c ldr r2, [pc, #112] @ (800a84c ) 800a7dc: 4293 cmp r3, r2 800a7de: d018 beq.n 800a812 800a7e0: 687b ldr r3, [r7, #4] 800a7e2: 681b ldr r3, [r3, #0] 800a7e4: 4a1a ldr r2, [pc, #104] @ (800a850 ) 800a7e6: 4293 cmp r3, r2 800a7e8: d013 beq.n 800a812 800a7ea: 687b ldr r3, [r7, #4] 800a7ec: 681b ldr r3, [r3, #0] 800a7ee: 4a19 ldr r2, [pc, #100] @ (800a854 ) 800a7f0: 4293 cmp r3, r2 800a7f2: d00e beq.n 800a812 800a7f4: 687b ldr r3, [r7, #4] 800a7f6: 681b ldr r3, [r3, #0] 800a7f8: 4a17 ldr r2, [pc, #92] @ (800a858 ) 800a7fa: 4293 cmp r3, r2 800a7fc: d009 beq.n 800a812 800a7fe: 687b ldr r3, [r7, #4] 800a800: 681b ldr r3, [r3, #0] 800a802: 4a16 ldr r2, [pc, #88] @ (800a85c ) 800a804: 4293 cmp r3, r2 800a806: d004 beq.n 800a812 800a808: 687b ldr r3, [r7, #4] 800a80a: 681b ldr r3, [r3, #0] 800a80c: 4a14 ldr r2, [pc, #80] @ (800a860 ) 800a80e: 4293 cmp r3, r2 800a810: d128 bne.n 800a864 800a812: 687b ldr r3, [r7, #4] 800a814: 681b ldr r3, [r3, #0] 800a816: 681a ldr r2, [r3, #0] 800a818: 687b ldr r3, [r7, #4] 800a81a: 681b ldr r3, [r3, #0] 800a81c: f022 0214 bic.w r2, r2, #20 800a820: 601a str r2, [r3, #0] 800a822: e027 b.n 800a874 800a824: 40020010 .word 0x40020010 800a828: 40020028 .word 0x40020028 800a82c: 40020040 .word 0x40020040 800a830: 40020058 .word 0x40020058 800a834: 40020070 .word 0x40020070 800a838: 40020088 .word 0x40020088 800a83c: 400200a0 .word 0x400200a0 800a840: 400200b8 .word 0x400200b8 800a844: 40020410 .word 0x40020410 800a848: 40020428 .word 0x40020428 800a84c: 40020440 .word 0x40020440 800a850: 40020458 .word 0x40020458 800a854: 40020470 .word 0x40020470 800a858: 40020488 .word 0x40020488 800a85c: 400204a0 .word 0x400204a0 800a860: 400204b8 .word 0x400204b8 800a864: 687b ldr r3, [r7, #4] 800a866: 681b ldr r3, [r3, #0] 800a868: 681a ldr r2, [r3, #0] 800a86a: 687b ldr r3, [r7, #4] 800a86c: 681b ldr r3, [r3, #0] 800a86e: f022 020a bic.w r2, r2, #10 800a872: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a874: 687b ldr r3, [r7, #4] 800a876: 2201 movs r2, #1 800a878: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a87c: 687b ldr r3, [r7, #4] 800a87e: 2200 movs r2, #0 800a880: f883 2034 strb.w r2, [r3, #52] @ 0x34 } if(hdma->XferCpltCallback != NULL) 800a884: 687b ldr r3, [r7, #4] 800a886: 6bdb ldr r3, [r3, #60] @ 0x3c 800a888: 2b00 cmp r3, #0 800a88a: f000 8097 beq.w 800a9bc { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 800a88e: 687b ldr r3, [r7, #4] 800a890: 6bdb ldr r3, [r3, #60] @ 0x3c 800a892: 6878 ldr r0, [r7, #4] 800a894: 4798 blx r3 if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a896: e091 b.n 800a9bc } } } /* Transfer Error Interrupt management **************************************/ else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) 800a898: 687b ldr r3, [r7, #4] 800a89a: 6ddb ldr r3, [r3, #92] @ 0x5c 800a89c: f003 031f and.w r3, r3, #31 800a8a0: 2208 movs r2, #8 800a8a2: 409a lsls r2, r3 800a8a4: 697b ldr r3, [r7, #20] 800a8a6: 4013 ands r3, r2 800a8a8: 2b00 cmp r3, #0 800a8aa: f000 8088 beq.w 800a9be 800a8ae: 693b ldr r3, [r7, #16] 800a8b0: f003 0308 and.w r3, r3, #8 800a8b4: 2b00 cmp r3, #0 800a8b6: f000 8082 beq.w 800a9be { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 800a8ba: 687b ldr r3, [r7, #4] 800a8bc: 681b ldr r3, [r3, #0] 800a8be: 4a41 ldr r2, [pc, #260] @ (800a9c4 ) 800a8c0: 4293 cmp r3, r2 800a8c2: d04a beq.n 800a95a 800a8c4: 687b ldr r3, [r7, #4] 800a8c6: 681b ldr r3, [r3, #0] 800a8c8: 4a3f ldr r2, [pc, #252] @ (800a9c8 ) 800a8ca: 4293 cmp r3, r2 800a8cc: d045 beq.n 800a95a 800a8ce: 687b ldr r3, [r7, #4] 800a8d0: 681b ldr r3, [r3, #0] 800a8d2: 4a3e ldr r2, [pc, #248] @ (800a9cc ) 800a8d4: 4293 cmp r3, r2 800a8d6: d040 beq.n 800a95a 800a8d8: 687b ldr r3, [r7, #4] 800a8da: 681b ldr r3, [r3, #0] 800a8dc: 4a3c ldr r2, [pc, #240] @ (800a9d0 ) 800a8de: 4293 cmp r3, r2 800a8e0: d03b beq.n 800a95a 800a8e2: 687b ldr r3, [r7, #4] 800a8e4: 681b ldr r3, [r3, #0] 800a8e6: 4a3b ldr r2, [pc, #236] @ (800a9d4 ) 800a8e8: 4293 cmp r3, r2 800a8ea: d036 beq.n 800a95a 800a8ec: 687b ldr r3, [r7, #4] 800a8ee: 681b ldr r3, [r3, #0] 800a8f0: 4a39 ldr r2, [pc, #228] @ (800a9d8 ) 800a8f2: 4293 cmp r3, r2 800a8f4: d031 beq.n 800a95a 800a8f6: 687b ldr r3, [r7, #4] 800a8f8: 681b ldr r3, [r3, #0] 800a8fa: 4a38 ldr r2, [pc, #224] @ (800a9dc ) 800a8fc: 4293 cmp r3, r2 800a8fe: d02c beq.n 800a95a 800a900: 687b ldr r3, [r7, #4] 800a902: 681b ldr r3, [r3, #0] 800a904: 4a36 ldr r2, [pc, #216] @ (800a9e0 ) 800a906: 4293 cmp r3, r2 800a908: d027 beq.n 800a95a 800a90a: 687b ldr r3, [r7, #4] 800a90c: 681b ldr r3, [r3, #0] 800a90e: 4a35 ldr r2, [pc, #212] @ (800a9e4 ) 800a910: 4293 cmp r3, r2 800a912: d022 beq.n 800a95a 800a914: 687b ldr r3, [r7, #4] 800a916: 681b ldr r3, [r3, #0] 800a918: 4a33 ldr r2, [pc, #204] @ (800a9e8 ) 800a91a: 4293 cmp r3, r2 800a91c: d01d beq.n 800a95a 800a91e: 687b ldr r3, [r7, #4] 800a920: 681b ldr r3, [r3, #0] 800a922: 4a32 ldr r2, [pc, #200] @ (800a9ec ) 800a924: 4293 cmp r3, r2 800a926: d018 beq.n 800a95a 800a928: 687b ldr r3, [r7, #4] 800a92a: 681b ldr r3, [r3, #0] 800a92c: 4a30 ldr r2, [pc, #192] @ (800a9f0 ) 800a92e: 4293 cmp r3, r2 800a930: d013 beq.n 800a95a 800a932: 687b ldr r3, [r7, #4] 800a934: 681b ldr r3, [r3, #0] 800a936: 4a2f ldr r2, [pc, #188] @ (800a9f4 ) 800a938: 4293 cmp r3, r2 800a93a: d00e beq.n 800a95a 800a93c: 687b ldr r3, [r7, #4] 800a93e: 681b ldr r3, [r3, #0] 800a940: 4a2d ldr r2, [pc, #180] @ (800a9f8 ) 800a942: 4293 cmp r3, r2 800a944: d009 beq.n 800a95a 800a946: 687b ldr r3, [r7, #4] 800a948: 681b ldr r3, [r3, #0] 800a94a: 4a2c ldr r2, [pc, #176] @ (800a9fc ) 800a94c: 4293 cmp r3, r2 800a94e: d004 beq.n 800a95a 800a950: 687b ldr r3, [r7, #4] 800a952: 681b ldr r3, [r3, #0] 800a954: 4a2a ldr r2, [pc, #168] @ (800aa00 ) 800a956: 4293 cmp r3, r2 800a958: d108 bne.n 800a96c 800a95a: 687b ldr r3, [r7, #4] 800a95c: 681b ldr r3, [r3, #0] 800a95e: 681a ldr r2, [r3, #0] 800a960: 687b ldr r3, [r7, #4] 800a962: 681b ldr r3, [r3, #0] 800a964: f022 021c bic.w r2, r2, #28 800a968: 601a str r2, [r3, #0] 800a96a: e007 b.n 800a97c 800a96c: 687b ldr r3, [r7, #4] 800a96e: 681b ldr r3, [r3, #0] 800a970: 681a ldr r2, [r3, #0] 800a972: 687b ldr r3, [r7, #4] 800a974: 681b ldr r3, [r3, #0] 800a976: f022 020e bic.w r2, r2, #14 800a97a: 601a str r2, [r3, #0] /* Clear all flags */ regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800a97c: 687b ldr r3, [r7, #4] 800a97e: 6ddb ldr r3, [r3, #92] @ 0x5c 800a980: f003 031f and.w r3, r3, #31 800a984: 2201 movs r2, #1 800a986: 409a lsls r2, r3 800a988: 69fb ldr r3, [r7, #28] 800a98a: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 800a98c: 687b ldr r3, [r7, #4] 800a98e: 2201 movs r2, #1 800a990: 655a str r2, [r3, #84] @ 0x54 /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 800a992: 687b ldr r3, [r7, #4] 800a994: 2201 movs r2, #1 800a996: f883 2035 strb.w r2, [r3, #53] @ 0x35 /* Process Unlocked */ __HAL_UNLOCK(hdma); 800a99a: 687b ldr r3, [r7, #4] 800a99c: 2200 movs r2, #0 800a99e: f883 2034 strb.w r2, [r3, #52] @ 0x34 if (hdma->XferErrorCallback != NULL) 800a9a2: 687b ldr r3, [r7, #4] 800a9a4: 6cdb ldr r3, [r3, #76] @ 0x4c 800a9a6: 2b00 cmp r3, #0 800a9a8: d009 beq.n 800a9be { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800a9aa: 687b ldr r3, [r7, #4] 800a9ac: 6cdb ldr r3, [r3, #76] @ 0x4c 800a9ae: 6878 ldr r0, [r7, #4] 800a9b0: 4798 blx r3 800a9b2: e004 b.n 800a9be return; 800a9b4: bf00 nop 800a9b6: e002 b.n 800a9be if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a9b8: bf00 nop 800a9ba: e000 b.n 800a9be if((ccr_reg & BDMA_CCR_DBM) != 0U) 800a9bc: bf00 nop } else { /* Nothing To Do */ } } 800a9be: 3728 adds r7, #40 @ 0x28 800a9c0: 46bd mov sp, r7 800a9c2: bd80 pop {r7, pc} 800a9c4: 40020010 .word 0x40020010 800a9c8: 40020028 .word 0x40020028 800a9cc: 40020040 .word 0x40020040 800a9d0: 40020058 .word 0x40020058 800a9d4: 40020070 .word 0x40020070 800a9d8: 40020088 .word 0x40020088 800a9dc: 400200a0 .word 0x400200a0 800a9e0: 400200b8 .word 0x400200b8 800a9e4: 40020410 .word 0x40020410 800a9e8: 40020428 .word 0x40020428 800a9ec: 40020440 .word 0x40020440 800a9f0: 40020458 .word 0x40020458 800a9f4: 40020470 .word 0x40020470 800a9f8: 40020488 .word 0x40020488 800a9fc: 400204a0 .word 0x400204a0 800aa00: 400204b8 .word 0x400204b8 0800aa04 : * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination * @retval None */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 800aa04: b480 push {r7} 800aa06: b087 sub sp, #28 800aa08: af00 add r7, sp, #0 800aa0a: 60f8 str r0, [r7, #12] 800aa0c: 60b9 str r1, [r7, #8] 800aa0e: 607a str r2, [r7, #4] 800aa10: 603b str r3, [r7, #0] /* calculate DMA base and stream number */ DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; 800aa12: 68fb ldr r3, [r7, #12] 800aa14: 6d9b ldr r3, [r3, #88] @ 0x58 800aa16: 617b str r3, [r7, #20] BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; 800aa18: 68fb ldr r3, [r7, #12] 800aa1a: 6d9b ldr r3, [r3, #88] @ 0x58 800aa1c: 613b str r3, [r7, #16] if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ 800aa1e: 68fb ldr r3, [r7, #12] 800aa20: 681b ldr r3, [r3, #0] 800aa22: 4a7f ldr r2, [pc, #508] @ (800ac20 ) 800aa24: 4293 cmp r3, r2 800aa26: d072 beq.n 800ab0e 800aa28: 68fb ldr r3, [r7, #12] 800aa2a: 681b ldr r3, [r3, #0] 800aa2c: 4a7d ldr r2, [pc, #500] @ (800ac24 ) 800aa2e: 4293 cmp r3, r2 800aa30: d06d beq.n 800ab0e 800aa32: 68fb ldr r3, [r7, #12] 800aa34: 681b ldr r3, [r3, #0] 800aa36: 4a7c ldr r2, [pc, #496] @ (800ac28 ) 800aa38: 4293 cmp r3, r2 800aa3a: d068 beq.n 800ab0e 800aa3c: 68fb ldr r3, [r7, #12] 800aa3e: 681b ldr r3, [r3, #0] 800aa40: 4a7a ldr r2, [pc, #488] @ (800ac2c ) 800aa42: 4293 cmp r3, r2 800aa44: d063 beq.n 800ab0e 800aa46: 68fb ldr r3, [r7, #12] 800aa48: 681b ldr r3, [r3, #0] 800aa4a: 4a79 ldr r2, [pc, #484] @ (800ac30 ) 800aa4c: 4293 cmp r3, r2 800aa4e: d05e beq.n 800ab0e 800aa50: 68fb ldr r3, [r7, #12] 800aa52: 681b ldr r3, [r3, #0] 800aa54: 4a77 ldr r2, [pc, #476] @ (800ac34 ) 800aa56: 4293 cmp r3, r2 800aa58: d059 beq.n 800ab0e 800aa5a: 68fb ldr r3, [r7, #12] 800aa5c: 681b ldr r3, [r3, #0] 800aa5e: 4a76 ldr r2, [pc, #472] @ (800ac38 ) 800aa60: 4293 cmp r3, r2 800aa62: d054 beq.n 800ab0e 800aa64: 68fb ldr r3, [r7, #12] 800aa66: 681b ldr r3, [r3, #0] 800aa68: 4a74 ldr r2, [pc, #464] @ (800ac3c ) 800aa6a: 4293 cmp r3, r2 800aa6c: d04f beq.n 800ab0e 800aa6e: 68fb ldr r3, [r7, #12] 800aa70: 681b ldr r3, [r3, #0] 800aa72: 4a73 ldr r2, [pc, #460] @ (800ac40 ) 800aa74: 4293 cmp r3, r2 800aa76: d04a beq.n 800ab0e 800aa78: 68fb ldr r3, [r7, #12] 800aa7a: 681b ldr r3, [r3, #0] 800aa7c: 4a71 ldr r2, [pc, #452] @ (800ac44 ) 800aa7e: 4293 cmp r3, r2 800aa80: d045 beq.n 800ab0e 800aa82: 68fb ldr r3, [r7, #12] 800aa84: 681b ldr r3, [r3, #0] 800aa86: 4a70 ldr r2, [pc, #448] @ (800ac48 ) 800aa88: 4293 cmp r3, r2 800aa8a: d040 beq.n 800ab0e 800aa8c: 68fb ldr r3, [r7, #12] 800aa8e: 681b ldr r3, [r3, #0] 800aa90: 4a6e ldr r2, [pc, #440] @ (800ac4c ) 800aa92: 4293 cmp r3, r2 800aa94: d03b beq.n 800ab0e 800aa96: 68fb ldr r3, [r7, #12] 800aa98: 681b ldr r3, [r3, #0] 800aa9a: 4a6d ldr r2, [pc, #436] @ (800ac50 ) 800aa9c: 4293 cmp r3, r2 800aa9e: d036 beq.n 800ab0e 800aaa0: 68fb ldr r3, [r7, #12] 800aaa2: 681b ldr r3, [r3, #0] 800aaa4: 4a6b ldr r2, [pc, #428] @ (800ac54 ) 800aaa6: 4293 cmp r3, r2 800aaa8: d031 beq.n 800ab0e 800aaaa: 68fb ldr r3, [r7, #12] 800aaac: 681b ldr r3, [r3, #0] 800aaae: 4a6a ldr r2, [pc, #424] @ (800ac58 ) 800aab0: 4293 cmp r3, r2 800aab2: d02c beq.n 800ab0e 800aab4: 68fb ldr r3, [r7, #12] 800aab6: 681b ldr r3, [r3, #0] 800aab8: 4a68 ldr r2, [pc, #416] @ (800ac5c ) 800aaba: 4293 cmp r3, r2 800aabc: d027 beq.n 800ab0e 800aabe: 68fb ldr r3, [r7, #12] 800aac0: 681b ldr r3, [r3, #0] 800aac2: 4a67 ldr r2, [pc, #412] @ (800ac60 ) 800aac4: 4293 cmp r3, r2 800aac6: d022 beq.n 800ab0e 800aac8: 68fb ldr r3, [r7, #12] 800aaca: 681b ldr r3, [r3, #0] 800aacc: 4a65 ldr r2, [pc, #404] @ (800ac64 ) 800aace: 4293 cmp r3, r2 800aad0: d01d beq.n 800ab0e 800aad2: 68fb ldr r3, [r7, #12] 800aad4: 681b ldr r3, [r3, #0] 800aad6: 4a64 ldr r2, [pc, #400] @ (800ac68 ) 800aad8: 4293 cmp r3, r2 800aada: d018 beq.n 800ab0e 800aadc: 68fb ldr r3, [r7, #12] 800aade: 681b ldr r3, [r3, #0] 800aae0: 4a62 ldr r2, [pc, #392] @ (800ac6c ) 800aae2: 4293 cmp r3, r2 800aae4: d013 beq.n 800ab0e 800aae6: 68fb ldr r3, [r7, #12] 800aae8: 681b ldr r3, [r3, #0] 800aaea: 4a61 ldr r2, [pc, #388] @ (800ac70 ) 800aaec: 4293 cmp r3, r2 800aaee: d00e beq.n 800ab0e 800aaf0: 68fb ldr r3, [r7, #12] 800aaf2: 681b ldr r3, [r3, #0] 800aaf4: 4a5f ldr r2, [pc, #380] @ (800ac74 ) 800aaf6: 4293 cmp r3, r2 800aaf8: d009 beq.n 800ab0e 800aafa: 68fb ldr r3, [r7, #12] 800aafc: 681b ldr r3, [r3, #0] 800aafe: 4a5e ldr r2, [pc, #376] @ (800ac78 ) 800ab00: 4293 cmp r3, r2 800ab02: d004 beq.n 800ab0e 800ab04: 68fb ldr r3, [r7, #12] 800ab06: 681b ldr r3, [r3, #0] 800ab08: 4a5c ldr r2, [pc, #368] @ (800ac7c ) 800ab0a: 4293 cmp r3, r2 800ab0c: d101 bne.n 800ab12 800ab0e: 2301 movs r3, #1 800ab10: e000 b.n 800ab14 800ab12: 2300 movs r3, #0 800ab14: 2b00 cmp r3, #0 800ab16: d00d beq.n 800ab34 { /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 800ab18: 68fb ldr r3, [r7, #12] 800ab1a: 6e5b ldr r3, [r3, #100] @ 0x64 800ab1c: 68fa ldr r2, [r7, #12] 800ab1e: 6e92 ldr r2, [r2, #104] @ 0x68 800ab20: 605a str r2, [r3, #4] if(hdma->DMAmuxRequestGen != 0U) 800ab22: 68fb ldr r3, [r7, #12] 800ab24: 6edb ldr r3, [r3, #108] @ 0x6c 800ab26: 2b00 cmp r3, #0 800ab28: d004 beq.n 800ab34 { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 800ab2a: 68fb ldr r3, [r7, #12] 800ab2c: 6f1b ldr r3, [r3, #112] @ 0x70 800ab2e: 68fa ldr r2, [r7, #12] 800ab30: 6f52 ldr r2, [r2, #116] @ 0x74 800ab32: 605a str r2, [r3, #4] } } if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800ab34: 68fb ldr r3, [r7, #12] 800ab36: 681b ldr r3, [r3, #0] 800ab38: 4a39 ldr r2, [pc, #228] @ (800ac20 ) 800ab3a: 4293 cmp r3, r2 800ab3c: d04a beq.n 800abd4 800ab3e: 68fb ldr r3, [r7, #12] 800ab40: 681b ldr r3, [r3, #0] 800ab42: 4a38 ldr r2, [pc, #224] @ (800ac24 ) 800ab44: 4293 cmp r3, r2 800ab46: d045 beq.n 800abd4 800ab48: 68fb ldr r3, [r7, #12] 800ab4a: 681b ldr r3, [r3, #0] 800ab4c: 4a36 ldr r2, [pc, #216] @ (800ac28 ) 800ab4e: 4293 cmp r3, r2 800ab50: d040 beq.n 800abd4 800ab52: 68fb ldr r3, [r7, #12] 800ab54: 681b ldr r3, [r3, #0] 800ab56: 4a35 ldr r2, [pc, #212] @ (800ac2c ) 800ab58: 4293 cmp r3, r2 800ab5a: d03b beq.n 800abd4 800ab5c: 68fb ldr r3, [r7, #12] 800ab5e: 681b ldr r3, [r3, #0] 800ab60: 4a33 ldr r2, [pc, #204] @ (800ac30 ) 800ab62: 4293 cmp r3, r2 800ab64: d036 beq.n 800abd4 800ab66: 68fb ldr r3, [r7, #12] 800ab68: 681b ldr r3, [r3, #0] 800ab6a: 4a32 ldr r2, [pc, #200] @ (800ac34 ) 800ab6c: 4293 cmp r3, r2 800ab6e: d031 beq.n 800abd4 800ab70: 68fb ldr r3, [r7, #12] 800ab72: 681b ldr r3, [r3, #0] 800ab74: 4a30 ldr r2, [pc, #192] @ (800ac38 ) 800ab76: 4293 cmp r3, r2 800ab78: d02c beq.n 800abd4 800ab7a: 68fb ldr r3, [r7, #12] 800ab7c: 681b ldr r3, [r3, #0] 800ab7e: 4a2f ldr r2, [pc, #188] @ (800ac3c ) 800ab80: 4293 cmp r3, r2 800ab82: d027 beq.n 800abd4 800ab84: 68fb ldr r3, [r7, #12] 800ab86: 681b ldr r3, [r3, #0] 800ab88: 4a2d ldr r2, [pc, #180] @ (800ac40 ) 800ab8a: 4293 cmp r3, r2 800ab8c: d022 beq.n 800abd4 800ab8e: 68fb ldr r3, [r7, #12] 800ab90: 681b ldr r3, [r3, #0] 800ab92: 4a2c ldr r2, [pc, #176] @ (800ac44 ) 800ab94: 4293 cmp r3, r2 800ab96: d01d beq.n 800abd4 800ab98: 68fb ldr r3, [r7, #12] 800ab9a: 681b ldr r3, [r3, #0] 800ab9c: 4a2a ldr r2, [pc, #168] @ (800ac48 ) 800ab9e: 4293 cmp r3, r2 800aba0: d018 beq.n 800abd4 800aba2: 68fb ldr r3, [r7, #12] 800aba4: 681b ldr r3, [r3, #0] 800aba6: 4a29 ldr r2, [pc, #164] @ (800ac4c ) 800aba8: 4293 cmp r3, r2 800abaa: d013 beq.n 800abd4 800abac: 68fb ldr r3, [r7, #12] 800abae: 681b ldr r3, [r3, #0] 800abb0: 4a27 ldr r2, [pc, #156] @ (800ac50 ) 800abb2: 4293 cmp r3, r2 800abb4: d00e beq.n 800abd4 800abb6: 68fb ldr r3, [r7, #12] 800abb8: 681b ldr r3, [r3, #0] 800abba: 4a26 ldr r2, [pc, #152] @ (800ac54 ) 800abbc: 4293 cmp r3, r2 800abbe: d009 beq.n 800abd4 800abc0: 68fb ldr r3, [r7, #12] 800abc2: 681b ldr r3, [r3, #0] 800abc4: 4a24 ldr r2, [pc, #144] @ (800ac58 ) 800abc6: 4293 cmp r3, r2 800abc8: d004 beq.n 800abd4 800abca: 68fb ldr r3, [r7, #12] 800abcc: 681b ldr r3, [r3, #0] 800abce: 4a23 ldr r2, [pc, #140] @ (800ac5c ) 800abd0: 4293 cmp r3, r2 800abd2: d101 bne.n 800abd8 800abd4: 2301 movs r3, #1 800abd6: e000 b.n 800abda 800abd8: 2300 movs r3, #0 800abda: 2b00 cmp r3, #0 800abdc: d059 beq.n 800ac92 { /* Clear all interrupt flags at correct offset within the register */ regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); 800abde: 68fb ldr r3, [r7, #12] 800abe0: 6ddb ldr r3, [r3, #92] @ 0x5c 800abe2: f003 031f and.w r3, r3, #31 800abe6: 223f movs r2, #63 @ 0x3f 800abe8: 409a lsls r2, r3 800abea: 697b ldr r3, [r7, #20] 800abec: 609a str r2, [r3, #8] /* Clear DBM bit */ ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); 800abee: 68fb ldr r3, [r7, #12] 800abf0: 681b ldr r3, [r3, #0] 800abf2: 681a ldr r2, [r3, #0] 800abf4: 68fb ldr r3, [r7, #12] 800abf6: 681b ldr r3, [r3, #0] 800abf8: f422 2280 bic.w r2, r2, #262144 @ 0x40000 800abfc: 601a str r2, [r3, #0] /* Configure DMA Stream data length */ ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; 800abfe: 68fb ldr r3, [r7, #12] 800ac00: 681b ldr r3, [r3, #0] 800ac02: 683a ldr r2, [r7, #0] 800ac04: 605a str r2, [r3, #4] /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800ac06: 68fb ldr r3, [r7, #12] 800ac08: 689b ldr r3, [r3, #8] 800ac0a: 2b40 cmp r3, #64 @ 0x40 800ac0c: d138 bne.n 800ac80 { /* Configure DMA Stream destination address */ ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; 800ac0e: 68fb ldr r3, [r7, #12] 800ac10: 681b ldr r3, [r3, #0] 800ac12: 687a ldr r2, [r7, #4] 800ac14: 609a str r2, [r3, #8] /* Configure DMA Stream source address */ ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; 800ac16: 68fb ldr r3, [r7, #12] 800ac18: 681b ldr r3, [r3, #0] 800ac1a: 68ba ldr r2, [r7, #8] 800ac1c: 60da str r2, [r3, #12] } else { /* Nothing To Do */ } } 800ac1e: e086 b.n 800ad2e 800ac20: 40020010 .word 0x40020010 800ac24: 40020028 .word 0x40020028 800ac28: 40020040 .word 0x40020040 800ac2c: 40020058 .word 0x40020058 800ac30: 40020070 .word 0x40020070 800ac34: 40020088 .word 0x40020088 800ac38: 400200a0 .word 0x400200a0 800ac3c: 400200b8 .word 0x400200b8 800ac40: 40020410 .word 0x40020410 800ac44: 40020428 .word 0x40020428 800ac48: 40020440 .word 0x40020440 800ac4c: 40020458 .word 0x40020458 800ac50: 40020470 .word 0x40020470 800ac54: 40020488 .word 0x40020488 800ac58: 400204a0 .word 0x400204a0 800ac5c: 400204b8 .word 0x400204b8 800ac60: 58025408 .word 0x58025408 800ac64: 5802541c .word 0x5802541c 800ac68: 58025430 .word 0x58025430 800ac6c: 58025444 .word 0x58025444 800ac70: 58025458 .word 0x58025458 800ac74: 5802546c .word 0x5802546c 800ac78: 58025480 .word 0x58025480 800ac7c: 58025494 .word 0x58025494 ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; 800ac80: 68fb ldr r3, [r7, #12] 800ac82: 681b ldr r3, [r3, #0] 800ac84: 68ba ldr r2, [r7, #8] 800ac86: 609a str r2, [r3, #8] ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; 800ac88: 68fb ldr r3, [r7, #12] 800ac8a: 681b ldr r3, [r3, #0] 800ac8c: 687a ldr r2, [r7, #4] 800ac8e: 60da str r2, [r3, #12] } 800ac90: e04d b.n 800ad2e else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ 800ac92: 68fb ldr r3, [r7, #12] 800ac94: 681b ldr r3, [r3, #0] 800ac96: 4a29 ldr r2, [pc, #164] @ (800ad3c ) 800ac98: 4293 cmp r3, r2 800ac9a: d022 beq.n 800ace2 800ac9c: 68fb ldr r3, [r7, #12] 800ac9e: 681b ldr r3, [r3, #0] 800aca0: 4a27 ldr r2, [pc, #156] @ (800ad40 ) 800aca2: 4293 cmp r3, r2 800aca4: d01d beq.n 800ace2 800aca6: 68fb ldr r3, [r7, #12] 800aca8: 681b ldr r3, [r3, #0] 800acaa: 4a26 ldr r2, [pc, #152] @ (800ad44 ) 800acac: 4293 cmp r3, r2 800acae: d018 beq.n 800ace2 800acb0: 68fb ldr r3, [r7, #12] 800acb2: 681b ldr r3, [r3, #0] 800acb4: 4a24 ldr r2, [pc, #144] @ (800ad48 ) 800acb6: 4293 cmp r3, r2 800acb8: d013 beq.n 800ace2 800acba: 68fb ldr r3, [r7, #12] 800acbc: 681b ldr r3, [r3, #0] 800acbe: 4a23 ldr r2, [pc, #140] @ (800ad4c ) 800acc0: 4293 cmp r3, r2 800acc2: d00e beq.n 800ace2 800acc4: 68fb ldr r3, [r7, #12] 800acc6: 681b ldr r3, [r3, #0] 800acc8: 4a21 ldr r2, [pc, #132] @ (800ad50 ) 800acca: 4293 cmp r3, r2 800accc: d009 beq.n 800ace2 800acce: 68fb ldr r3, [r7, #12] 800acd0: 681b ldr r3, [r3, #0] 800acd2: 4a20 ldr r2, [pc, #128] @ (800ad54 ) 800acd4: 4293 cmp r3, r2 800acd6: d004 beq.n 800ace2 800acd8: 68fb ldr r3, [r7, #12] 800acda: 681b ldr r3, [r3, #0] 800acdc: 4a1e ldr r2, [pc, #120] @ (800ad58 ) 800acde: 4293 cmp r3, r2 800ace0: d101 bne.n 800ace6 800ace2: 2301 movs r3, #1 800ace4: e000 b.n 800ace8 800ace6: 2300 movs r3, #0 800ace8: 2b00 cmp r3, #0 800acea: d020 beq.n 800ad2e regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); 800acec: 68fb ldr r3, [r7, #12] 800acee: 6ddb ldr r3, [r3, #92] @ 0x5c 800acf0: f003 031f and.w r3, r3, #31 800acf4: 2201 movs r2, #1 800acf6: 409a lsls r2, r3 800acf8: 693b ldr r3, [r7, #16] 800acfa: 605a str r2, [r3, #4] ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; 800acfc: 68fb ldr r3, [r7, #12] 800acfe: 681b ldr r3, [r3, #0] 800ad00: 683a ldr r2, [r7, #0] 800ad02: 605a str r2, [r3, #4] if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 800ad04: 68fb ldr r3, [r7, #12] 800ad06: 689b ldr r3, [r3, #8] 800ad08: 2b40 cmp r3, #64 @ 0x40 800ad0a: d108 bne.n 800ad1e ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; 800ad0c: 68fb ldr r3, [r7, #12] 800ad0e: 681b ldr r3, [r3, #0] 800ad10: 687a ldr r2, [r7, #4] 800ad12: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; 800ad14: 68fb ldr r3, [r7, #12] 800ad16: 681b ldr r3, [r3, #0] 800ad18: 68ba ldr r2, [r7, #8] 800ad1a: 60da str r2, [r3, #12] } 800ad1c: e007 b.n 800ad2e ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; 800ad1e: 68fb ldr r3, [r7, #12] 800ad20: 681b ldr r3, [r3, #0] 800ad22: 68ba ldr r2, [r7, #8] 800ad24: 609a str r2, [r3, #8] ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; 800ad26: 68fb ldr r3, [r7, #12] 800ad28: 681b ldr r3, [r3, #0] 800ad2a: 687a ldr r2, [r7, #4] 800ad2c: 60da str r2, [r3, #12] } 800ad2e: bf00 nop 800ad30: 371c adds r7, #28 800ad32: 46bd mov sp, r7 800ad34: f85d 7b04 ldr.w r7, [sp], #4 800ad38: 4770 bx lr 800ad3a: bf00 nop 800ad3c: 58025408 .word 0x58025408 800ad40: 5802541c .word 0x5802541c 800ad44: 58025430 .word 0x58025430 800ad48: 58025444 .word 0x58025444 800ad4c: 58025458 .word 0x58025458 800ad50: 5802546c .word 0x5802546c 800ad54: 58025480 .word 0x58025480 800ad58: 58025494 .word 0x58025494 0800ad5c : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { 800ad5c: b480 push {r7} 800ad5e: b085 sub sp, #20 800ad60: af00 add r7, sp, #0 800ad62: 6078 str r0, [r7, #4] if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ 800ad64: 687b ldr r3, [r7, #4] 800ad66: 681b ldr r3, [r3, #0] 800ad68: 4a42 ldr r2, [pc, #264] @ (800ae74 ) 800ad6a: 4293 cmp r3, r2 800ad6c: d04a beq.n 800ae04 800ad6e: 687b ldr r3, [r7, #4] 800ad70: 681b ldr r3, [r3, #0] 800ad72: 4a41 ldr r2, [pc, #260] @ (800ae78 ) 800ad74: 4293 cmp r3, r2 800ad76: d045 beq.n 800ae04 800ad78: 687b ldr r3, [r7, #4] 800ad7a: 681b ldr r3, [r3, #0] 800ad7c: 4a3f ldr r2, [pc, #252] @ (800ae7c ) 800ad7e: 4293 cmp r3, r2 800ad80: d040 beq.n 800ae04 800ad82: 687b ldr r3, [r7, #4] 800ad84: 681b ldr r3, [r3, #0] 800ad86: 4a3e ldr r2, [pc, #248] @ (800ae80 ) 800ad88: 4293 cmp r3, r2 800ad8a: d03b beq.n 800ae04 800ad8c: 687b ldr r3, [r7, #4] 800ad8e: 681b ldr r3, [r3, #0] 800ad90: 4a3c ldr r2, [pc, #240] @ (800ae84 ) 800ad92: 4293 cmp r3, r2 800ad94: d036 beq.n 800ae04 800ad96: 687b ldr r3, [r7, #4] 800ad98: 681b ldr r3, [r3, #0] 800ad9a: 4a3b ldr r2, [pc, #236] @ (800ae88 ) 800ad9c: 4293 cmp r3, r2 800ad9e: d031 beq.n 800ae04 800ada0: 687b ldr r3, [r7, #4] 800ada2: 681b ldr r3, [r3, #0] 800ada4: 4a39 ldr r2, [pc, #228] @ (800ae8c ) 800ada6: 4293 cmp r3, r2 800ada8: d02c beq.n 800ae04 800adaa: 687b ldr r3, [r7, #4] 800adac: 681b ldr r3, [r3, #0] 800adae: 4a38 ldr r2, [pc, #224] @ (800ae90 ) 800adb0: 4293 cmp r3, r2 800adb2: d027 beq.n 800ae04 800adb4: 687b ldr r3, [r7, #4] 800adb6: 681b ldr r3, [r3, #0] 800adb8: 4a36 ldr r2, [pc, #216] @ (800ae94 ) 800adba: 4293 cmp r3, r2 800adbc: d022 beq.n 800ae04 800adbe: 687b ldr r3, [r7, #4] 800adc0: 681b ldr r3, [r3, #0] 800adc2: 4a35 ldr r2, [pc, #212] @ (800ae98 ) 800adc4: 4293 cmp r3, r2 800adc6: d01d beq.n 800ae04 800adc8: 687b ldr r3, [r7, #4] 800adca: 681b ldr r3, [r3, #0] 800adcc: 4a33 ldr r2, [pc, #204] @ (800ae9c ) 800adce: 4293 cmp r3, r2 800add0: d018 beq.n 800ae04 800add2: 687b ldr r3, [r7, #4] 800add4: 681b ldr r3, [r3, #0] 800add6: 4a32 ldr r2, [pc, #200] @ (800aea0 ) 800add8: 4293 cmp r3, r2 800adda: d013 beq.n 800ae04 800addc: 687b ldr r3, [r7, #4] 800adde: 681b ldr r3, [r3, #0] 800ade0: 4a30 ldr r2, [pc, #192] @ (800aea4 ) 800ade2: 4293 cmp r3, r2 800ade4: d00e beq.n 800ae04 800ade6: 687b ldr r3, [r7, #4] 800ade8: 681b ldr r3, [r3, #0] 800adea: 4a2f ldr r2, [pc, #188] @ (800aea8 ) 800adec: 4293 cmp r3, r2 800adee: d009 beq.n 800ae04 800adf0: 687b ldr r3, [r7, #4] 800adf2: 681b ldr r3, [r3, #0] 800adf4: 4a2d ldr r2, [pc, #180] @ (800aeac ) 800adf6: 4293 cmp r3, r2 800adf8: d004 beq.n 800ae04 800adfa: 687b ldr r3, [r7, #4] 800adfc: 681b ldr r3, [r3, #0] 800adfe: 4a2c ldr r2, [pc, #176] @ (800aeb0 ) 800ae00: 4293 cmp r3, r2 800ae02: d101 bne.n 800ae08 800ae04: 2301 movs r3, #1 800ae06: e000 b.n 800ae0a 800ae08: 2300 movs r3, #0 800ae0a: 2b00 cmp r3, #0 800ae0c: d024 beq.n 800ae58 { uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800ae0e: 687b ldr r3, [r7, #4] 800ae10: 681b ldr r3, [r3, #0] 800ae12: b2db uxtb r3, r3 800ae14: 3b10 subs r3, #16 800ae16: 4a27 ldr r2, [pc, #156] @ (800aeb4 ) 800ae18: fba2 2303 umull r2, r3, r2, r3 800ae1c: 091b lsrs r3, r3, #4 800ae1e: 60fb str r3, [r7, #12] /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; 800ae20: 68fb ldr r3, [r7, #12] 800ae22: f003 0307 and.w r3, r3, #7 800ae26: 4a24 ldr r2, [pc, #144] @ (800aeb8 ) 800ae28: 5cd3 ldrb r3, [r2, r3] 800ae2a: 461a mov r2, r3 800ae2c: 687b ldr r3, [r7, #4] 800ae2e: 65da str r2, [r3, #92] @ 0x5c if (stream_number > 3U) 800ae30: 68fb ldr r3, [r7, #12] 800ae32: 2b03 cmp r3, #3 800ae34: d908 bls.n 800ae48 { /* return pointer to HISR and HIFCR */ hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); 800ae36: 687b ldr r3, [r7, #4] 800ae38: 681b ldr r3, [r3, #0] 800ae3a: 461a mov r2, r3 800ae3c: 4b1f ldr r3, [pc, #124] @ (800aebc ) 800ae3e: 4013 ands r3, r2 800ae40: 1d1a adds r2, r3, #4 800ae42: 687b ldr r3, [r7, #4] 800ae44: 659a str r2, [r3, #88] @ 0x58 800ae46: e00d b.n 800ae64 } else { /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); 800ae48: 687b ldr r3, [r7, #4] 800ae4a: 681b ldr r3, [r3, #0] 800ae4c: 461a mov r2, r3 800ae4e: 4b1b ldr r3, [pc, #108] @ (800aebc ) 800ae50: 4013 ands r3, r2 800ae52: 687a ldr r2, [r7, #4] 800ae54: 6593 str r3, [r2, #88] @ 0x58 800ae56: e005 b.n 800ae64 } } else /* BDMA instance(s) */ { /* return pointer to ISR and IFCR */ hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); 800ae58: 687b ldr r3, [r7, #4] 800ae5a: 681b ldr r3, [r3, #0] 800ae5c: f023 02ff bic.w r2, r3, #255 @ 0xff 800ae60: 687b ldr r3, [r7, #4] 800ae62: 659a str r2, [r3, #88] @ 0x58 } return hdma->StreamBaseAddress; 800ae64: 687b ldr r3, [r7, #4] 800ae66: 6d9b ldr r3, [r3, #88] @ 0x58 } 800ae68: 4618 mov r0, r3 800ae6a: 3714 adds r7, #20 800ae6c: 46bd mov sp, r7 800ae6e: f85d 7b04 ldr.w r7, [sp], #4 800ae72: 4770 bx lr 800ae74: 40020010 .word 0x40020010 800ae78: 40020028 .word 0x40020028 800ae7c: 40020040 .word 0x40020040 800ae80: 40020058 .word 0x40020058 800ae84: 40020070 .word 0x40020070 800ae88: 40020088 .word 0x40020088 800ae8c: 400200a0 .word 0x400200a0 800ae90: 400200b8 .word 0x400200b8 800ae94: 40020410 .word 0x40020410 800ae98: 40020428 .word 0x40020428 800ae9c: 40020440 .word 0x40020440 800aea0: 40020458 .word 0x40020458 800aea4: 40020470 .word 0x40020470 800aea8: 40020488 .word 0x40020488 800aeac: 400204a0 .word 0x400204a0 800aeb0: 400204b8 .word 0x400204b8 800aeb4: aaaaaaab .word 0xaaaaaaab 800aeb8: 0801871c .word 0x0801871c 800aebc: fffffc00 .word 0xfffffc00 0800aec0 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { 800aec0: b480 push {r7} 800aec2: b085 sub sp, #20 800aec4: af00 add r7, sp, #0 800aec6: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 800aec8: 2300 movs r3, #0 800aeca: 73fb strb r3, [r7, #15] /* Memory Data size equal to Byte */ if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) 800aecc: 687b ldr r3, [r7, #4] 800aece: 699b ldr r3, [r3, #24] 800aed0: 2b00 cmp r3, #0 800aed2: d120 bne.n 800af16 { switch (hdma->Init.FIFOThreshold) 800aed4: 687b ldr r3, [r7, #4] 800aed6: 6a9b ldr r3, [r3, #40] @ 0x28 800aed8: 2b03 cmp r3, #3 800aeda: d858 bhi.n 800af8e 800aedc: a201 add r2, pc, #4 @ (adr r2, 800aee4 ) 800aede: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800aee2: bf00 nop 800aee4: 0800aef5 .word 0x0800aef5 800aee8: 0800af07 .word 0x0800af07 800aeec: 0800aef5 .word 0x0800aef5 800aef0: 0800af8f .word 0x0800af8f { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800aef4: 687b ldr r3, [r7, #4] 800aef6: 6adb ldr r3, [r3, #44] @ 0x2c 800aef8: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800aefc: 2b00 cmp r3, #0 800aefe: d048 beq.n 800af92 { status = HAL_ERROR; 800af00: 2301 movs r3, #1 800af02: 73fb strb r3, [r7, #15] } break; 800af04: e045 b.n 800af92 case DMA_FIFO_THRESHOLD_HALFFULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800af06: 687b ldr r3, [r7, #4] 800af08: 6adb ldr r3, [r3, #44] @ 0x2c 800af0a: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800af0e: d142 bne.n 800af96 { status = HAL_ERROR; 800af10: 2301 movs r3, #1 800af12: 73fb strb r3, [r7, #15] } break; 800af14: e03f b.n 800af96 break; } } /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) 800af16: 687b ldr r3, [r7, #4] 800af18: 699b ldr r3, [r3, #24] 800af1a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800af1e: d123 bne.n 800af68 { switch (hdma->Init.FIFOThreshold) 800af20: 687b ldr r3, [r7, #4] 800af22: 6a9b ldr r3, [r3, #40] @ 0x28 800af24: 2b03 cmp r3, #3 800af26: d838 bhi.n 800af9a 800af28: a201 add r2, pc, #4 @ (adr r2, 800af30 ) 800af2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800af2e: bf00 nop 800af30: 0800af41 .word 0x0800af41 800af34: 0800af47 .word 0x0800af47 800af38: 0800af41 .word 0x0800af41 800af3c: 0800af59 .word 0x0800af59 { case DMA_FIFO_THRESHOLD_1QUARTERFULL: case DMA_FIFO_THRESHOLD_3QUARTERSFULL: status = HAL_ERROR; 800af40: 2301 movs r3, #1 800af42: 73fb strb r3, [r7, #15] break; 800af44: e030 b.n 800afa8 case DMA_FIFO_THRESHOLD_HALFFULL: if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800af46: 687b ldr r3, [r7, #4] 800af48: 6adb ldr r3, [r3, #44] @ 0x2c 800af4a: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800af4e: 2b00 cmp r3, #0 800af50: d025 beq.n 800af9e { status = HAL_ERROR; 800af52: 2301 movs r3, #1 800af54: 73fb strb r3, [r7, #15] } break; 800af56: e022 b.n 800af9e case DMA_FIFO_THRESHOLD_FULL: if (hdma->Init.MemBurst == DMA_MBURST_INC16) 800af58: 687b ldr r3, [r7, #4] 800af5a: 6adb ldr r3, [r3, #44] @ 0x2c 800af5c: f1b3 7fc0 cmp.w r3, #25165824 @ 0x1800000 800af60: d11f bne.n 800afa2 { status = HAL_ERROR; 800af62: 2301 movs r3, #1 800af64: 73fb strb r3, [r7, #15] } break; 800af66: e01c b.n 800afa2 } /* Memory Data size equal to Word */ else { switch (hdma->Init.FIFOThreshold) 800af68: 687b ldr r3, [r7, #4] 800af6a: 6a9b ldr r3, [r3, #40] @ 0x28 800af6c: 2b02 cmp r3, #2 800af6e: d902 bls.n 800af76 800af70: 2b03 cmp r3, #3 800af72: d003 beq.n 800af7c status = HAL_ERROR; } break; default: break; 800af74: e018 b.n 800afa8 status = HAL_ERROR; 800af76: 2301 movs r3, #1 800af78: 73fb strb r3, [r7, #15] break; 800af7a: e015 b.n 800afa8 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) 800af7c: 687b ldr r3, [r7, #4] 800af7e: 6adb ldr r3, [r3, #44] @ 0x2c 800af80: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 800af84: 2b00 cmp r3, #0 800af86: d00e beq.n 800afa6 status = HAL_ERROR; 800af88: 2301 movs r3, #1 800af8a: 73fb strb r3, [r7, #15] break; 800af8c: e00b b.n 800afa6 break; 800af8e: bf00 nop 800af90: e00a b.n 800afa8 break; 800af92: bf00 nop 800af94: e008 b.n 800afa8 break; 800af96: bf00 nop 800af98: e006 b.n 800afa8 break; 800af9a: bf00 nop 800af9c: e004 b.n 800afa8 break; 800af9e: bf00 nop 800afa0: e002 b.n 800afa8 break; 800afa2: bf00 nop 800afa4: e000 b.n 800afa8 break; 800afa6: bf00 nop } } return status; 800afa8: 7bfb ldrb r3, [r7, #15] } 800afaa: 4618 mov r0, r3 800afac: 3714 adds r7, #20 800afae: 46bd mov sp, r7 800afb0: f85d 7b04 ldr.w r7, [sp], #4 800afb4: 4770 bx lr 800afb6: bf00 nop 0800afb8 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 800afb8: b480 push {r7} 800afba: b085 sub sp, #20 800afbc: af00 add r7, sp, #0 800afbe: 6078 str r0, [r7, #4] uint32_t stream_number; uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); 800afc0: 687b ldr r3, [r7, #4] 800afc2: 681b ldr r3, [r3, #0] 800afc4: 60bb str r3, [r7, #8] if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800afc6: 687b ldr r3, [r7, #4] 800afc8: 681b ldr r3, [r3, #0] 800afca: 4a38 ldr r2, [pc, #224] @ (800b0ac ) 800afcc: 4293 cmp r3, r2 800afce: d022 beq.n 800b016 800afd0: 687b ldr r3, [r7, #4] 800afd2: 681b ldr r3, [r3, #0] 800afd4: 4a36 ldr r2, [pc, #216] @ (800b0b0 ) 800afd6: 4293 cmp r3, r2 800afd8: d01d beq.n 800b016 800afda: 687b ldr r3, [r7, #4] 800afdc: 681b ldr r3, [r3, #0] 800afde: 4a35 ldr r2, [pc, #212] @ (800b0b4 ) 800afe0: 4293 cmp r3, r2 800afe2: d018 beq.n 800b016 800afe4: 687b ldr r3, [r7, #4] 800afe6: 681b ldr r3, [r3, #0] 800afe8: 4a33 ldr r2, [pc, #204] @ (800b0b8 ) 800afea: 4293 cmp r3, r2 800afec: d013 beq.n 800b016 800afee: 687b ldr r3, [r7, #4] 800aff0: 681b ldr r3, [r3, #0] 800aff2: 4a32 ldr r2, [pc, #200] @ (800b0bc ) 800aff4: 4293 cmp r3, r2 800aff6: d00e beq.n 800b016 800aff8: 687b ldr r3, [r7, #4] 800affa: 681b ldr r3, [r3, #0] 800affc: 4a30 ldr r2, [pc, #192] @ (800b0c0 ) 800affe: 4293 cmp r3, r2 800b000: d009 beq.n 800b016 800b002: 687b ldr r3, [r7, #4] 800b004: 681b ldr r3, [r3, #0] 800b006: 4a2f ldr r2, [pc, #188] @ (800b0c4 ) 800b008: 4293 cmp r3, r2 800b00a: d004 beq.n 800b016 800b00c: 687b ldr r3, [r7, #4] 800b00e: 681b ldr r3, [r3, #0] 800b010: 4a2d ldr r2, [pc, #180] @ (800b0c8 ) 800b012: 4293 cmp r3, r2 800b014: d101 bne.n 800b01a 800b016: 2301 movs r3, #1 800b018: e000 b.n 800b01c 800b01a: 2300 movs r3, #0 800b01c: 2b00 cmp r3, #0 800b01e: d01a beq.n 800b056 { /* BDMA Channels are connected to DMAMUX2 channels */ stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; 800b020: 687b ldr r3, [r7, #4] 800b022: 681b ldr r3, [r3, #0] 800b024: b2db uxtb r3, r3 800b026: 3b08 subs r3, #8 800b028: 4a28 ldr r2, [pc, #160] @ (800b0cc ) 800b02a: fba2 2303 umull r2, r3, r2, r3 800b02e: 091b lsrs r3, r3, #4 800b030: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); 800b032: 68fa ldr r2, [r7, #12] 800b034: 4b26 ldr r3, [pc, #152] @ (800b0d0 ) 800b036: 4413 add r3, r2 800b038: 009b lsls r3, r3, #2 800b03a: 461a mov r2, r3 800b03c: 687b ldr r3, [r7, #4] 800b03e: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; 800b040: 687b ldr r3, [r7, #4] 800b042: 4a24 ldr r2, [pc, #144] @ (800b0d4 ) 800b044: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800b046: 68fb ldr r3, [r7, #12] 800b048: f003 031f and.w r3, r3, #31 800b04c: 2201 movs r2, #1 800b04e: 409a lsls r2, r3 800b050: 687b ldr r3, [r7, #4] 800b052: 669a str r2, [r3, #104] @ 0x68 } hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); } } 800b054: e024 b.n 800b0a0 stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; 800b056: 687b ldr r3, [r7, #4] 800b058: 681b ldr r3, [r3, #0] 800b05a: b2db uxtb r3, r3 800b05c: 3b10 subs r3, #16 800b05e: 4a1e ldr r2, [pc, #120] @ (800b0d8 ) 800b060: fba2 2303 umull r2, r3, r2, r3 800b064: 091b lsrs r3, r3, #4 800b066: 60fb str r3, [r7, #12] if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ 800b068: 68bb ldr r3, [r7, #8] 800b06a: 4a1c ldr r2, [pc, #112] @ (800b0dc ) 800b06c: 4293 cmp r3, r2 800b06e: d806 bhi.n 800b07e 800b070: 68bb ldr r3, [r7, #8] 800b072: 4a1b ldr r2, [pc, #108] @ (800b0e0 ) 800b074: 4293 cmp r3, r2 800b076: d902 bls.n 800b07e stream_number += 8U; 800b078: 68fb ldr r3, [r7, #12] 800b07a: 3308 adds r3, #8 800b07c: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); 800b07e: 68fa ldr r2, [r7, #12] 800b080: 4b18 ldr r3, [pc, #96] @ (800b0e4 ) 800b082: 4413 add r3, r2 800b084: 009b lsls r3, r3, #2 800b086: 461a mov r2, r3 800b088: 687b ldr r3, [r7, #4] 800b08a: 661a str r2, [r3, #96] @ 0x60 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 800b08c: 687b ldr r3, [r7, #4] 800b08e: 4a16 ldr r2, [pc, #88] @ (800b0e8 ) 800b090: 665a str r2, [r3, #100] @ 0x64 hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); 800b092: 68fb ldr r3, [r7, #12] 800b094: f003 031f and.w r3, r3, #31 800b098: 2201 movs r2, #1 800b09a: 409a lsls r2, r3 800b09c: 687b ldr r3, [r7, #4] 800b09e: 669a str r2, [r3, #104] @ 0x68 } 800b0a0: bf00 nop 800b0a2: 3714 adds r7, #20 800b0a4: 46bd mov sp, r7 800b0a6: f85d 7b04 ldr.w r7, [sp], #4 800b0aa: 4770 bx lr 800b0ac: 58025408 .word 0x58025408 800b0b0: 5802541c .word 0x5802541c 800b0b4: 58025430 .word 0x58025430 800b0b8: 58025444 .word 0x58025444 800b0bc: 58025458 .word 0x58025458 800b0c0: 5802546c .word 0x5802546c 800b0c4: 58025480 .word 0x58025480 800b0c8: 58025494 .word 0x58025494 800b0cc: cccccccd .word 0xcccccccd 800b0d0: 16009600 .word 0x16009600 800b0d4: 58025880 .word 0x58025880 800b0d8: aaaaaaab .word 0xaaaaaaab 800b0dc: 400204b8 .word 0x400204b8 800b0e0: 4002040f .word 0x4002040f 800b0e4: 10008200 .word 0x10008200 800b0e8: 40020880 .word 0x40020880 0800b0ec : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 800b0ec: b480 push {r7} 800b0ee: b085 sub sp, #20 800b0f0: af00 add r7, sp, #0 800b0f2: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 800b0f4: 687b ldr r3, [r7, #4] 800b0f6: 685b ldr r3, [r3, #4] 800b0f8: b2db uxtb r3, r3 800b0fa: 60fb str r3, [r7, #12] if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) 800b0fc: 68fb ldr r3, [r7, #12] 800b0fe: 2b00 cmp r3, #0 800b100: d04a beq.n 800b198 800b102: 68fb ldr r3, [r7, #12] 800b104: 2b08 cmp r3, #8 800b106: d847 bhi.n 800b198 { if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) 800b108: 687b ldr r3, [r7, #4] 800b10a: 681b ldr r3, [r3, #0] 800b10c: 4a25 ldr r2, [pc, #148] @ (800b1a4 ) 800b10e: 4293 cmp r3, r2 800b110: d022 beq.n 800b158 800b112: 687b ldr r3, [r7, #4] 800b114: 681b ldr r3, [r3, #0] 800b116: 4a24 ldr r2, [pc, #144] @ (800b1a8 ) 800b118: 4293 cmp r3, r2 800b11a: d01d beq.n 800b158 800b11c: 687b ldr r3, [r7, #4] 800b11e: 681b ldr r3, [r3, #0] 800b120: 4a22 ldr r2, [pc, #136] @ (800b1ac ) 800b122: 4293 cmp r3, r2 800b124: d018 beq.n 800b158 800b126: 687b ldr r3, [r7, #4] 800b128: 681b ldr r3, [r3, #0] 800b12a: 4a21 ldr r2, [pc, #132] @ (800b1b0 ) 800b12c: 4293 cmp r3, r2 800b12e: d013 beq.n 800b158 800b130: 687b ldr r3, [r7, #4] 800b132: 681b ldr r3, [r3, #0] 800b134: 4a1f ldr r2, [pc, #124] @ (800b1b4 ) 800b136: 4293 cmp r3, r2 800b138: d00e beq.n 800b158 800b13a: 687b ldr r3, [r7, #4] 800b13c: 681b ldr r3, [r3, #0] 800b13e: 4a1e ldr r2, [pc, #120] @ (800b1b8 ) 800b140: 4293 cmp r3, r2 800b142: d009 beq.n 800b158 800b144: 687b ldr r3, [r7, #4] 800b146: 681b ldr r3, [r3, #0] 800b148: 4a1c ldr r2, [pc, #112] @ (800b1bc ) 800b14a: 4293 cmp r3, r2 800b14c: d004 beq.n 800b158 800b14e: 687b ldr r3, [r7, #4] 800b150: 681b ldr r3, [r3, #0] 800b152: 4a1b ldr r2, [pc, #108] @ (800b1c0 ) 800b154: 4293 cmp r3, r2 800b156: d101 bne.n 800b15c 800b158: 2301 movs r3, #1 800b15a: e000 b.n 800b15e 800b15c: 2300 movs r3, #0 800b15e: 2b00 cmp r3, #0 800b160: d00a beq.n 800b178 { /* BDMA Channels are connected to DMAMUX2 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); 800b162: 68fa ldr r2, [r7, #12] 800b164: 4b17 ldr r3, [pc, #92] @ (800b1c4 ) 800b166: 4413 add r3, r2 800b168: 009b lsls r3, r3, #2 800b16a: 461a mov r2, r3 800b16c: 687b ldr r3, [r7, #4] 800b16e: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; 800b170: 687b ldr r3, [r7, #4] 800b172: 4a15 ldr r2, [pc, #84] @ (800b1c8 ) 800b174: 671a str r2, [r3, #112] @ 0x70 800b176: e009 b.n 800b18c } else { /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 800b178: 68fa ldr r2, [r7, #12] 800b17a: 4b14 ldr r3, [pc, #80] @ (800b1cc ) 800b17c: 4413 add r3, r2 800b17e: 009b lsls r3, r3, #2 800b180: 461a mov r2, r3 800b182: 687b ldr r3, [r7, #4] 800b184: 66da str r2, [r3, #108] @ 0x6c hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 800b186: 687b ldr r3, [r7, #4] 800b188: 4a11 ldr r2, [pc, #68] @ (800b1d0 ) 800b18a: 671a str r2, [r3, #112] @ 0x70 } hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); 800b18c: 68fb ldr r3, [r7, #12] 800b18e: 3b01 subs r3, #1 800b190: 2201 movs r2, #1 800b192: 409a lsls r2, r3 800b194: 687b ldr r3, [r7, #4] 800b196: 675a str r2, [r3, #116] @ 0x74 } } 800b198: bf00 nop 800b19a: 3714 adds r7, #20 800b19c: 46bd mov sp, r7 800b19e: f85d 7b04 ldr.w r7, [sp], #4 800b1a2: 4770 bx lr 800b1a4: 58025408 .word 0x58025408 800b1a8: 5802541c .word 0x5802541c 800b1ac: 58025430 .word 0x58025430 800b1b0: 58025444 .word 0x58025444 800b1b4: 58025458 .word 0x58025458 800b1b8: 5802546c .word 0x5802546c 800b1bc: 58025480 .word 0x58025480 800b1c0: 58025494 .word 0x58025494 800b1c4: 1600963f .word 0x1600963f 800b1c8: 58025940 .word 0x58025940 800b1cc: 1000823f .word 0x1000823f 800b1d0: 40020940 .word 0x40020940 0800b1d4 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 800b1d4: b480 push {r7} 800b1d6: b089 sub sp, #36 @ 0x24 800b1d8: af00 add r7, sp, #0 800b1da: 6078 str r0, [r7, #4] 800b1dc: 6039 str r1, [r7, #0] uint32_t position = 0x00U; 800b1de: 2300 movs r3, #0 800b1e0: 61fb str r3, [r7, #28] EXTI_Core_TypeDef *EXTI_CurrentCPU; #if defined(DUAL_CORE) && defined(CORE_CM4) EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ #else EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ 800b1e2: 4b89 ldr r3, [pc, #548] @ (800b408 ) 800b1e4: 617b str r3, [r7, #20] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != 0x00U) 800b1e6: e194 b.n 800b512 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1UL << position); 800b1e8: 683b ldr r3, [r7, #0] 800b1ea: 681a ldr r2, [r3, #0] 800b1ec: 2101 movs r1, #1 800b1ee: 69fb ldr r3, [r7, #28] 800b1f0: fa01 f303 lsl.w r3, r1, r3 800b1f4: 4013 ands r3, r2 800b1f6: 613b str r3, [r7, #16] if (iocurrent != 0x00U) 800b1f8: 693b ldr r3, [r7, #16] 800b1fa: 2b00 cmp r3, #0 800b1fc: f000 8186 beq.w 800b50c { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) 800b200: 683b ldr r3, [r7, #0] 800b202: 685b ldr r3, [r3, #4] 800b204: f003 0303 and.w r3, r3, #3 800b208: 2b01 cmp r3, #1 800b20a: d005 beq.n 800b218 800b20c: 683b ldr r3, [r7, #0] 800b20e: 685b ldr r3, [r3, #4] 800b210: f003 0303 and.w r3, r3, #3 800b214: 2b02 cmp r3, #2 800b216: d130 bne.n 800b27a { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 800b218: 687b ldr r3, [r7, #4] 800b21a: 689b ldr r3, [r3, #8] 800b21c: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); 800b21e: 69fb ldr r3, [r7, #28] 800b220: 005b lsls r3, r3, #1 800b222: 2203 movs r2, #3 800b224: fa02 f303 lsl.w r3, r2, r3 800b228: 43db mvns r3, r3 800b22a: 69ba ldr r2, [r7, #24] 800b22c: 4013 ands r3, r2 800b22e: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 800b230: 683b ldr r3, [r7, #0] 800b232: 68da ldr r2, [r3, #12] 800b234: 69fb ldr r3, [r7, #28] 800b236: 005b lsls r3, r3, #1 800b238: fa02 f303 lsl.w r3, r2, r3 800b23c: 69ba ldr r2, [r7, #24] 800b23e: 4313 orrs r3, r2 800b240: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 800b242: 687b ldr r3, [r7, #4] 800b244: 69ba ldr r2, [r7, #24] 800b246: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800b248: 687b ldr r3, [r7, #4] 800b24a: 685b ldr r3, [r3, #4] 800b24c: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT0 << position) ; 800b24e: 2201 movs r2, #1 800b250: 69fb ldr r3, [r7, #28] 800b252: fa02 f303 lsl.w r3, r2, r3 800b256: 43db mvns r3, r3 800b258: 69ba ldr r2, [r7, #24] 800b25a: 4013 ands r3, r2 800b25c: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 800b25e: 683b ldr r3, [r7, #0] 800b260: 685b ldr r3, [r3, #4] 800b262: 091b lsrs r3, r3, #4 800b264: f003 0201 and.w r2, r3, #1 800b268: 69fb ldr r3, [r7, #28] 800b26a: fa02 f303 lsl.w r3, r2, r3 800b26e: 69ba ldr r2, [r7, #24] 800b270: 4313 orrs r3, r2 800b272: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 800b274: 687b ldr r3, [r7, #4] 800b276: 69ba ldr r2, [r7, #24] 800b278: 605a str r2, [r3, #4] } if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 800b27a: 683b ldr r3, [r7, #0] 800b27c: 685b ldr r3, [r3, #4] 800b27e: f003 0303 and.w r3, r3, #3 800b282: 2b03 cmp r3, #3 800b284: d017 beq.n 800b2b6 { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800b286: 687b ldr r3, [r7, #4] 800b288: 68db ldr r3, [r3, #12] 800b28a: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); 800b28c: 69fb ldr r3, [r7, #28] 800b28e: 005b lsls r3, r3, #1 800b290: 2203 movs r2, #3 800b292: fa02 f303 lsl.w r3, r2, r3 800b296: 43db mvns r3, r3 800b298: 69ba ldr r2, [r7, #24] 800b29a: 4013 ands r3, r2 800b29c: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 800b29e: 683b ldr r3, [r7, #0] 800b2a0: 689a ldr r2, [r3, #8] 800b2a2: 69fb ldr r3, [r7, #28] 800b2a4: 005b lsls r3, r3, #1 800b2a6: fa02 f303 lsl.w r3, r2, r3 800b2aa: 69ba ldr r2, [r7, #24] 800b2ac: 4313 orrs r3, r2 800b2ae: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 800b2b0: 687b ldr r3, [r7, #4] 800b2b2: 69ba ldr r2, [r7, #24] 800b2b4: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 800b2b6: 683b ldr r3, [r7, #0] 800b2b8: 685b ldr r3, [r3, #4] 800b2ba: f003 0303 and.w r3, r3, #3 800b2be: 2b02 cmp r3, #2 800b2c0: d123 bne.n 800b30a /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 800b2c2: 69fb ldr r3, [r7, #28] 800b2c4: 08da lsrs r2, r3, #3 800b2c6: 687b ldr r3, [r7, #4] 800b2c8: 3208 adds r2, #8 800b2ca: f853 3022 ldr.w r3, [r3, r2, lsl #2] 800b2ce: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((position & 0x07U) * 4U)); 800b2d0: 69fb ldr r3, [r7, #28] 800b2d2: f003 0307 and.w r3, r3, #7 800b2d6: 009b lsls r3, r3, #2 800b2d8: 220f movs r2, #15 800b2da: fa02 f303 lsl.w r3, r2, r3 800b2de: 43db mvns r3, r3 800b2e0: 69ba ldr r2, [r7, #24] 800b2e2: 4013 ands r3, r2 800b2e4: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); 800b2e6: 683b ldr r3, [r7, #0] 800b2e8: 691a ldr r2, [r3, #16] 800b2ea: 69fb ldr r3, [r7, #28] 800b2ec: f003 0307 and.w r3, r3, #7 800b2f0: 009b lsls r3, r3, #2 800b2f2: fa02 f303 lsl.w r3, r2, r3 800b2f6: 69ba ldr r2, [r7, #24] 800b2f8: 4313 orrs r3, r2 800b2fa: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 800b2fc: 69fb ldr r3, [r7, #28] 800b2fe: 08da lsrs r2, r3, #3 800b300: 687b ldr r3, [r7, #4] 800b302: 3208 adds r2, #8 800b304: 69b9 ldr r1, [r7, #24] 800b306: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 800b30a: 687b ldr r3, [r7, #4] 800b30c: 681b ldr r3, [r3, #0] 800b30e: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); 800b310: 69fb ldr r3, [r7, #28] 800b312: 005b lsls r3, r3, #1 800b314: 2203 movs r2, #3 800b316: fa02 f303 lsl.w r3, r2, r3 800b31a: 43db mvns r3, r3 800b31c: 69ba ldr r2, [r7, #24] 800b31e: 4013 ands r3, r2 800b320: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 800b322: 683b ldr r3, [r7, #0] 800b324: 685b ldr r3, [r3, #4] 800b326: f003 0203 and.w r2, r3, #3 800b32a: 69fb ldr r3, [r7, #28] 800b32c: 005b lsls r3, r3, #1 800b32e: fa02 f303 lsl.w r3, r2, r3 800b332: 69ba ldr r2, [r7, #24] 800b334: 4313 orrs r3, r2 800b336: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 800b338: 687b ldr r3, [r7, #4] 800b33a: 69ba ldr r2, [r7, #24] 800b33c: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 800b33e: 683b ldr r3, [r7, #0] 800b340: 685b ldr r3, [r3, #4] 800b342: f403 3340 and.w r3, r3, #196608 @ 0x30000 800b346: 2b00 cmp r3, #0 800b348: f000 80e0 beq.w 800b50c { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 800b34c: 4b2f ldr r3, [pc, #188] @ (800b40c ) 800b34e: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b352: 4a2e ldr r2, [pc, #184] @ (800b40c ) 800b354: f043 0302 orr.w r3, r3, #2 800b358: f8c2 30f4 str.w r3, [r2, #244] @ 0xf4 800b35c: 4b2b ldr r3, [pc, #172] @ (800b40c ) 800b35e: f8d3 30f4 ldr.w r3, [r3, #244] @ 0xf4 800b362: f003 0302 and.w r3, r3, #2 800b366: 60fb str r3, [r7, #12] 800b368: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 800b36a: 4a29 ldr r2, [pc, #164] @ (800b410 ) 800b36c: 69fb ldr r3, [r7, #28] 800b36e: 089b lsrs r3, r3, #2 800b370: 3302 adds r3, #2 800b372: f852 3023 ldr.w r3, [r2, r3, lsl #2] 800b376: 61bb str r3, [r7, #24] temp &= ~(0x0FUL << (4U * (position & 0x03U))); 800b378: 69fb ldr r3, [r7, #28] 800b37a: f003 0303 and.w r3, r3, #3 800b37e: 009b lsls r3, r3, #2 800b380: 220f movs r2, #15 800b382: fa02 f303 lsl.w r3, r2, r3 800b386: 43db mvns r3, r3 800b388: 69ba ldr r2, [r7, #24] 800b38a: 4013 ands r3, r2 800b38c: 61bb str r3, [r7, #24] temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); 800b38e: 687b ldr r3, [r7, #4] 800b390: 4a20 ldr r2, [pc, #128] @ (800b414 ) 800b392: 4293 cmp r3, r2 800b394: d052 beq.n 800b43c 800b396: 687b ldr r3, [r7, #4] 800b398: 4a1f ldr r2, [pc, #124] @ (800b418 ) 800b39a: 4293 cmp r3, r2 800b39c: d031 beq.n 800b402 800b39e: 687b ldr r3, [r7, #4] 800b3a0: 4a1e ldr r2, [pc, #120] @ (800b41c ) 800b3a2: 4293 cmp r3, r2 800b3a4: d02b beq.n 800b3fe 800b3a6: 687b ldr r3, [r7, #4] 800b3a8: 4a1d ldr r2, [pc, #116] @ (800b420 ) 800b3aa: 4293 cmp r3, r2 800b3ac: d025 beq.n 800b3fa 800b3ae: 687b ldr r3, [r7, #4] 800b3b0: 4a1c ldr r2, [pc, #112] @ (800b424 ) 800b3b2: 4293 cmp r3, r2 800b3b4: d01f beq.n 800b3f6 800b3b6: 687b ldr r3, [r7, #4] 800b3b8: 4a1b ldr r2, [pc, #108] @ (800b428 ) 800b3ba: 4293 cmp r3, r2 800b3bc: d019 beq.n 800b3f2 800b3be: 687b ldr r3, [r7, #4] 800b3c0: 4a1a ldr r2, [pc, #104] @ (800b42c ) 800b3c2: 4293 cmp r3, r2 800b3c4: d013 beq.n 800b3ee 800b3c6: 687b ldr r3, [r7, #4] 800b3c8: 4a19 ldr r2, [pc, #100] @ (800b430 ) 800b3ca: 4293 cmp r3, r2 800b3cc: d00d beq.n 800b3ea 800b3ce: 687b ldr r3, [r7, #4] 800b3d0: 4a18 ldr r2, [pc, #96] @ (800b434 ) 800b3d2: 4293 cmp r3, r2 800b3d4: d007 beq.n 800b3e6 800b3d6: 687b ldr r3, [r7, #4] 800b3d8: 4a17 ldr r2, [pc, #92] @ (800b438 ) 800b3da: 4293 cmp r3, r2 800b3dc: d101 bne.n 800b3e2 800b3de: 2309 movs r3, #9 800b3e0: e02d b.n 800b43e 800b3e2: 230a movs r3, #10 800b3e4: e02b b.n 800b43e 800b3e6: 2308 movs r3, #8 800b3e8: e029 b.n 800b43e 800b3ea: 2307 movs r3, #7 800b3ec: e027 b.n 800b43e 800b3ee: 2306 movs r3, #6 800b3f0: e025 b.n 800b43e 800b3f2: 2305 movs r3, #5 800b3f4: e023 b.n 800b43e 800b3f6: 2304 movs r3, #4 800b3f8: e021 b.n 800b43e 800b3fa: 2303 movs r3, #3 800b3fc: e01f b.n 800b43e 800b3fe: 2302 movs r3, #2 800b400: e01d b.n 800b43e 800b402: 2301 movs r3, #1 800b404: e01b b.n 800b43e 800b406: bf00 nop 800b408: 58000080 .word 0x58000080 800b40c: 58024400 .word 0x58024400 800b410: 58000400 .word 0x58000400 800b414: 58020000 .word 0x58020000 800b418: 58020400 .word 0x58020400 800b41c: 58020800 .word 0x58020800 800b420: 58020c00 .word 0x58020c00 800b424: 58021000 .word 0x58021000 800b428: 58021400 .word 0x58021400 800b42c: 58021800 .word 0x58021800 800b430: 58021c00 .word 0x58021c00 800b434: 58022000 .word 0x58022000 800b438: 58022400 .word 0x58022400 800b43c: 2300 movs r3, #0 800b43e: 69fa ldr r2, [r7, #28] 800b440: f002 0203 and.w r2, r2, #3 800b444: 0092 lsls r2, r2, #2 800b446: 4093 lsls r3, r2 800b448: 69ba ldr r2, [r7, #24] 800b44a: 4313 orrs r3, r2 800b44c: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 800b44e: 4938 ldr r1, [pc, #224] @ (800b530 ) 800b450: 69fb ldr r3, [r7, #28] 800b452: 089b lsrs r3, r3, #2 800b454: 3302 adds r3, #2 800b456: 69ba ldr r2, [r7, #24] 800b458: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800b45c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b460: 681b ldr r3, [r3, #0] 800b462: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b464: 693b ldr r3, [r7, #16] 800b466: 43db mvns r3, r3 800b468: 69ba ldr r2, [r7, #24] 800b46a: 4013 ands r3, r2 800b46c: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 800b46e: 683b ldr r3, [r7, #0] 800b470: 685b ldr r3, [r3, #4] 800b472: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800b476: 2b00 cmp r3, #0 800b478: d003 beq.n 800b482 { temp |= iocurrent; 800b47a: 69ba ldr r2, [r7, #24] 800b47c: 693b ldr r3, [r7, #16] 800b47e: 4313 orrs r3, r2 800b480: 61bb str r3, [r7, #24] } EXTI->RTSR1 = temp; 800b482: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b486: 69bb ldr r3, [r7, #24] 800b488: 6013 str r3, [r2, #0] temp = EXTI->FTSR1; 800b48a: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b48e: 685b ldr r3, [r3, #4] 800b490: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b492: 693b ldr r3, [r7, #16] 800b494: 43db mvns r3, r3 800b496: 69ba ldr r2, [r7, #24] 800b498: 4013 ands r3, r2 800b49a: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800b49c: 683b ldr r3, [r7, #0] 800b49e: 685b ldr r3, [r3, #4] 800b4a0: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800b4a4: 2b00 cmp r3, #0 800b4a6: d003 beq.n 800b4b0 { temp |= iocurrent; 800b4a8: 69ba ldr r2, [r7, #24] 800b4aa: 693b ldr r3, [r7, #16] 800b4ac: 4313 orrs r3, r2 800b4ae: 61bb str r3, [r7, #24] } EXTI->FTSR1 = temp; 800b4b0: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b4b4: 69bb ldr r3, [r7, #24] 800b4b6: 6053 str r3, [r2, #4] temp = EXTI_CurrentCPU->EMR1; 800b4b8: 697b ldr r3, [r7, #20] 800b4ba: 685b ldr r3, [r3, #4] 800b4bc: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b4be: 693b ldr r3, [r7, #16] 800b4c0: 43db mvns r3, r3 800b4c2: 69ba ldr r2, [r7, #24] 800b4c4: 4013 ands r3, r2 800b4c6: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 800b4c8: 683b ldr r3, [r7, #0] 800b4ca: 685b ldr r3, [r3, #4] 800b4cc: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b4d0: 2b00 cmp r3, #0 800b4d2: d003 beq.n 800b4dc { temp |= iocurrent; 800b4d4: 69ba ldr r2, [r7, #24] 800b4d6: 693b ldr r3, [r7, #16] 800b4d8: 4313 orrs r3, r2 800b4da: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->EMR1 = temp; 800b4dc: 697b ldr r3, [r7, #20] 800b4de: 69ba ldr r2, [r7, #24] 800b4e0: 605a str r2, [r3, #4] /* Clear EXTI line configuration */ temp = EXTI_CurrentCPU->IMR1; 800b4e2: 697b ldr r3, [r7, #20] 800b4e4: 681b ldr r3, [r3, #0] 800b4e6: 61bb str r3, [r7, #24] temp &= ~(iocurrent); 800b4e8: 693b ldr r3, [r7, #16] 800b4ea: 43db mvns r3, r3 800b4ec: 69ba ldr r2, [r7, #24] 800b4ee: 4013 ands r3, r2 800b4f0: 61bb str r3, [r7, #24] if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) 800b4f2: 683b ldr r3, [r7, #0] 800b4f4: 685b ldr r3, [r3, #4] 800b4f6: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b4fa: 2b00 cmp r3, #0 800b4fc: d003 beq.n 800b506 { temp |= iocurrent; 800b4fe: 69ba ldr r2, [r7, #24] 800b500: 693b ldr r3, [r7, #16] 800b502: 4313 orrs r3, r2 800b504: 61bb str r3, [r7, #24] } EXTI_CurrentCPU->IMR1 = temp; 800b506: 697b ldr r3, [r7, #20] 800b508: 69ba ldr r2, [r7, #24] 800b50a: 601a str r2, [r3, #0] } } position++; 800b50c: 69fb ldr r3, [r7, #28] 800b50e: 3301 adds r3, #1 800b510: 61fb str r3, [r7, #28] while (((GPIO_Init->Pin) >> position) != 0x00U) 800b512: 683b ldr r3, [r7, #0] 800b514: 681a ldr r2, [r3, #0] 800b516: 69fb ldr r3, [r7, #28] 800b518: fa22 f303 lsr.w r3, r2, r3 800b51c: 2b00 cmp r3, #0 800b51e: f47f ae63 bne.w 800b1e8 } } 800b522: bf00 nop 800b524: bf00 nop 800b526: 3724 adds r7, #36 @ 0x24 800b528: 46bd mov sp, r7 800b52a: f85d 7b04 ldr.w r7, [sp], #4 800b52e: 4770 bx lr 800b530: 58000400 .word 0x58000400 0800b534 : * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b534: b480 push {r7} 800b536: b085 sub sp, #20 800b538: af00 add r7, sp, #0 800b53a: 6078 str r0, [r7, #4] 800b53c: 460b mov r3, r1 800b53e: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0x00U) 800b540: 687b ldr r3, [r7, #4] 800b542: 691a ldr r2, [r3, #16] 800b544: 887b ldrh r3, [r7, #2] 800b546: 4013 ands r3, r2 800b548: 2b00 cmp r3, #0 800b54a: d002 beq.n 800b552 { bitstatus = GPIO_PIN_SET; 800b54c: 2301 movs r3, #1 800b54e: 73fb strb r3, [r7, #15] 800b550: e001 b.n 800b556 } else { bitstatus = GPIO_PIN_RESET; 800b552: 2300 movs r3, #0 800b554: 73fb strb r3, [r7, #15] } return bitstatus; 800b556: 7bfb ldrb r3, [r7, #15] } 800b558: 4618 mov r0, r3 800b55a: 3714 adds r7, #20 800b55c: 46bd mov sp, r7 800b55e: f85d 7b04 ldr.w r7, [sp], #4 800b562: 4770 bx lr 0800b564 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 800b564: b480 push {r7} 800b566: b083 sub sp, #12 800b568: af00 add r7, sp, #0 800b56a: 6078 str r0, [r7, #4] 800b56c: 460b mov r3, r1 800b56e: 807b strh r3, [r7, #2] 800b570: 4613 mov r3, r2 800b572: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 800b574: 787b ldrb r3, [r7, #1] 800b576: 2b00 cmp r3, #0 800b578: d003 beq.n 800b582 { GPIOx->BSRR = GPIO_Pin; 800b57a: 887a ldrh r2, [r7, #2] 800b57c: 687b ldr r3, [r7, #4] 800b57e: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; } } 800b580: e003 b.n 800b58a GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; 800b582: 887b ldrh r3, [r7, #2] 800b584: 041a lsls r2, r3, #16 800b586: 687b ldr r3, [r7, #4] 800b588: 619a str r2, [r3, #24] } 800b58a: bf00 nop 800b58c: 370c adds r7, #12 800b58e: 46bd mov sp, r7 800b590: f85d 7b04 ldr.w r7, [sp], #4 800b594: 4770 bx lr 0800b596 : * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 800b596: b480 push {r7} 800b598: b085 sub sp, #20 800b59a: af00 add r7, sp, #0 800b59c: 6078 str r0, [r7, #4] 800b59e: 460b mov r3, r1 800b5a0: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 800b5a2: 687b ldr r3, [r7, #4] 800b5a4: 695b ldr r3, [r3, #20] 800b5a6: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800b5a8: 887a ldrh r2, [r7, #2] 800b5aa: 68fb ldr r3, [r7, #12] 800b5ac: 4013 ands r3, r2 800b5ae: 041a lsls r2, r3, #16 800b5b0: 68fb ldr r3, [r7, #12] 800b5b2: 43d9 mvns r1, r3 800b5b4: 887b ldrh r3, [r7, #2] 800b5b6: 400b ands r3, r1 800b5b8: 431a orrs r2, r3 800b5ba: 687b ldr r3, [r7, #4] 800b5bc: 619a str r2, [r3, #24] } 800b5be: bf00 nop 800b5c0: 3714 adds r7, #20 800b5c2: 46bd mov sp, r7 800b5c4: f85d 7b04 ldr.w r7, [sp], #4 800b5c8: 4770 bx lr 0800b5ca : * @brief Handle EXTI interrupt request. * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 800b5ca: b580 push {r7, lr} 800b5cc: b082 sub sp, #8 800b5ce: af00 add r7, sp, #0 800b5d0: 4603 mov r3, r0 800b5d2: 80fb strh r3, [r7, #6] __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } #else /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) 800b5d4: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b5d8: f8d3 2088 ldr.w r2, [r3, #136] @ 0x88 800b5dc: 88fb ldrh r3, [r7, #6] 800b5de: 4013 ands r3, r2 800b5e0: 2b00 cmp r3, #0 800b5e2: d008 beq.n 800b5f6 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 800b5e4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b5e8: 88fb ldrh r3, [r7, #6] 800b5ea: f8c2 3088 str.w r3, [r2, #136] @ 0x88 HAL_GPIO_EXTI_Callback(GPIO_Pin); 800b5ee: 88fb ldrh r3, [r7, #6] 800b5f0: 4618 mov r0, r3 800b5f2: f7f5 f80f bl 8000614 } #endif } 800b5f6: bf00 nop 800b5f8: 3708 adds r7, #8 800b5fa: 46bd mov sp, r7 800b5fc: bd80 pop {r7, pc} 0800b5fe : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { 800b5fe: b580 push {r7, lr} 800b600: b084 sub sp, #16 800b602: af00 add r7, sp, #0 800b604: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the IWDG handle allocation */ if (hiwdg == NULL) 800b606: 687b ldr r3, [r7, #4] 800b608: 2b00 cmp r3, #0 800b60a: d101 bne.n 800b610 { return HAL_ERROR; 800b60c: 2301 movs r3, #1 800b60e: e041 b.n 800b694 assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); /* Enable IWDG. LSI is turned on automatically */ __HAL_IWDG_START(hiwdg); 800b610: 687b ldr r3, [r7, #4] 800b612: 681b ldr r3, [r3, #0] 800b614: f64c 42cc movw r2, #52428 @ 0xcccc 800b618: 601a str r2, [r3, #0] /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing 0x5555 in KR */ IWDG_ENABLE_WRITE_ACCESS(hiwdg); 800b61a: 687b ldr r3, [r7, #4] 800b61c: 681b ldr r3, [r3, #0] 800b61e: f245 5255 movw r2, #21845 @ 0x5555 800b622: 601a str r2, [r3, #0] /* Write to IWDG registers the Prescaler & Reload values to work with */ hiwdg->Instance->PR = hiwdg->Init.Prescaler; 800b624: 687b ldr r3, [r7, #4] 800b626: 681b ldr r3, [r3, #0] 800b628: 687a ldr r2, [r7, #4] 800b62a: 6852 ldr r2, [r2, #4] 800b62c: 605a str r2, [r3, #4] hiwdg->Instance->RLR = hiwdg->Init.Reload; 800b62e: 687b ldr r3, [r7, #4] 800b630: 681b ldr r3, [r3, #0] 800b632: 687a ldr r2, [r7, #4] 800b634: 6892 ldr r2, [r2, #8] 800b636: 609a str r2, [r3, #8] /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); 800b638: f7fa fbf4 bl 8005e24 800b63c: 60f8 str r0, [r7, #12] /* Wait for register to be updated */ while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b63e: e00f b.n 800b660 { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) 800b640: f7fa fbf0 bl 8005e24 800b644: 4602 mov r2, r0 800b646: 68fb ldr r3, [r7, #12] 800b648: 1ad3 subs r3, r2, r3 800b64a: 2b31 cmp r3, #49 @ 0x31 800b64c: d908 bls.n 800b660 { if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b64e: 687b ldr r3, [r7, #4] 800b650: 681b ldr r3, [r3, #0] 800b652: 68db ldr r3, [r3, #12] 800b654: f003 0307 and.w r3, r3, #7 800b658: 2b00 cmp r3, #0 800b65a: d001 beq.n 800b660 { return HAL_TIMEOUT; 800b65c: 2303 movs r3, #3 800b65e: e019 b.n 800b694 while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) 800b660: 687b ldr r3, [r7, #4] 800b662: 681b ldr r3, [r3, #0] 800b664: 68db ldr r3, [r3, #12] 800b666: f003 0307 and.w r3, r3, #7 800b66a: 2b00 cmp r3, #0 800b66c: d1e8 bne.n 800b640 } } /* If window parameter is different than current value, modify window register */ if (hiwdg->Instance->WINR != hiwdg->Init.Window) 800b66e: 687b ldr r3, [r7, #4] 800b670: 681b ldr r3, [r3, #0] 800b672: 691a ldr r2, [r3, #16] 800b674: 687b ldr r3, [r7, #4] 800b676: 68db ldr r3, [r3, #12] 800b678: 429a cmp r2, r3 800b67a: d005 beq.n 800b688 { /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, even if window feature is disabled, Watchdog will be reloaded by writing windows register */ hiwdg->Instance->WINR = hiwdg->Init.Window; 800b67c: 687b ldr r3, [r7, #4] 800b67e: 681b ldr r3, [r3, #0] 800b680: 687a ldr r2, [r7, #4] 800b682: 68d2 ldr r2, [r2, #12] 800b684: 611a str r2, [r3, #16] 800b686: e004 b.n 800b692 } else { /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b688: 687b ldr r3, [r7, #4] 800b68a: 681b ldr r3, [r3, #0] 800b68c: f64a 22aa movw r2, #43690 @ 0xaaaa 800b690: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800b692: 2300 movs r3, #0 } 800b694: 4618 mov r0, r3 800b696: 3710 adds r7, #16 800b698: 46bd mov sp, r7 800b69a: bd80 pop {r7, pc} 0800b69c : * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { 800b69c: b480 push {r7} 800b69e: b083 sub sp, #12 800b6a0: af00 add r7, sp, #0 800b6a2: 6078 str r0, [r7, #4] /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); 800b6a4: 687b ldr r3, [r7, #4] 800b6a6: 681b ldr r3, [r3, #0] 800b6a8: f64a 22aa movw r2, #43690 @ 0xaaaa 800b6ac: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 800b6ae: 2300 movs r3, #0 } 800b6b0: 4618 mov r0, r3 800b6b2: 370c adds r7, #12 800b6b4: 46bd mov sp, r7 800b6b6: f85d 7b04 ldr.w r7, [sp], #4 800b6ba: 4770 bx lr 0800b6bc : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) { 800b6bc: b480 push {r7} 800b6be: b083 sub sp, #12 800b6c0: af00 add r7, sp, #0 800b6c2: 6078 str r0, [r7, #4] /* Check the PVD configuration parameter */ if (sConfigPVD == NULL) 800b6c4: 687b ldr r3, [r7, #4] 800b6c6: 2b00 cmp r3, #0 800b6c8: d069 beq.n 800b79e /* Check the parameters */ assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); 800b6ca: 4b38 ldr r3, [pc, #224] @ (800b7ac ) 800b6cc: 681b ldr r3, [r3, #0] 800b6ce: f023 02e0 bic.w r2, r3, #224 @ 0xe0 800b6d2: 687b ldr r3, [r7, #4] 800b6d4: 681b ldr r3, [r3, #0] 800b6d6: 4935 ldr r1, [pc, #212] @ (800b7ac ) 800b6d8: 4313 orrs r3, r2 800b6da: 600b str r3, [r1, #0] /* Clear previous config */ #if !defined (DUAL_CORE) __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); 800b6dc: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6e0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b6e4: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6e8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b6ec: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_PVD_EXTI_DISABLE_IT (); 800b6f0: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b6f4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b6f8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b6fc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b700: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); 800b704: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b708: 681b ldr r3, [r3, #0] 800b70a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b70e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b712: 6013 str r3, [r2, #0] __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); 800b714: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b718: 685b ldr r3, [r3, #4] 800b71a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b71e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b722: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Interrupt mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 800b724: 687b ldr r3, [r7, #4] 800b726: 685b ldr r3, [r3, #4] 800b728: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b72c: 2b00 cmp r3, #0 800b72e: d009 beq.n 800b744 { __HAL_PWR_PVD_EXTI_ENABLE_IT (); 800b730: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b734: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b738: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b73c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b740: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Event mode configuration */ if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 800b744: 687b ldr r3, [r7, #4] 800b746: 685b ldr r3, [r3, #4] 800b748: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b74c: 2b00 cmp r3, #0 800b74e: d009 beq.n 800b764 { __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); 800b750: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b754: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b758: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b75c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b760: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 800b764: 687b ldr r3, [r7, #4] 800b766: 685b ldr r3, [r3, #4] 800b768: f003 0301 and.w r3, r3, #1 800b76c: 2b00 cmp r3, #0 800b76e: d007 beq.n 800b780 { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); 800b770: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b774: 681b ldr r3, [r3, #0] 800b776: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b77a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b77e: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 800b780: 687b ldr r3, [r7, #4] 800b782: 685b ldr r3, [r3, #4] 800b784: f003 0302 and.w r3, r3, #2 800b788: 2b00 cmp r3, #0 800b78a: d009 beq.n 800b7a0 { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); 800b78c: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b790: 685b ldr r3, [r3, #4] 800b792: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b796: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b79a: 6053 str r3, [r2, #4] 800b79c: e000 b.n 800b7a0 return; 800b79e: bf00 nop } } 800b7a0: 370c adds r7, #12 800b7a2: 46bd mov sp, r7 800b7a4: f85d 7b04 ldr.w r7, [sp], #4 800b7a8: 4770 bx lr 800b7aa: bf00 nop 800b7ac: 58024800 .word 0x58024800 0800b7b0 : /** * @brief Enable the Programmable Voltage Detector (PVD). * @retval None. */ void HAL_PWR_EnablePVD (void) { 800b7b0: b480 push {r7} 800b7b2: af00 add r7, sp, #0 /* Enable the power voltage detector */ SET_BIT (PWR->CR1, PWR_CR1_PVDEN); 800b7b4: 4b05 ldr r3, [pc, #20] @ (800b7cc ) 800b7b6: 681b ldr r3, [r3, #0] 800b7b8: 4a04 ldr r2, [pc, #16] @ (800b7cc ) 800b7ba: f043 0310 orr.w r3, r3, #16 800b7be: 6013 str r3, [r2, #0] } 800b7c0: bf00 nop 800b7c2: 46bd mov sp, r7 800b7c4: f85d 7b04 ldr.w r7, [sp], #4 800b7c8: 4770 bx lr 800b7ca: bf00 nop 800b7cc: 58024800 .word 0x58024800 0800b7d0 : * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * regulator. * @retval HAL status. */ HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) { 800b7d0: b580 push {r7, lr} 800b7d2: b084 sub sp, #16 800b7d4: af00 add r7, sp, #0 800b7d6: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_SUPPLY (SupplySource)); /* Check if supply source was configured */ #if defined (PWR_FLAG_SCUEN) if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) 800b7d8: 4b19 ldr r3, [pc, #100] @ (800b840 ) 800b7da: 68db ldr r3, [r3, #12] 800b7dc: f003 0304 and.w r3, r3, #4 800b7e0: 2b04 cmp r3, #4 800b7e2: d00a beq.n 800b7fa #else if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) #endif /* defined (PWR_FLAG_SCUEN) */ { /* Check supply configuration */ if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) 800b7e4: 4b16 ldr r3, [pc, #88] @ (800b840 ) 800b7e6: 68db ldr r3, [r3, #12] 800b7e8: f003 0307 and.w r3, r3, #7 800b7ec: 687a ldr r2, [r7, #4] 800b7ee: 429a cmp r2, r3 800b7f0: d001 beq.n 800b7f6 { /* Supply configuration update locked, can't apply a new supply config */ return HAL_ERROR; 800b7f2: 2301 movs r3, #1 800b7f4: e01f b.n 800b836 else { /* Supply configuration update locked, but new supply configuration matches with old supply configuration : nothing to do */ return HAL_OK; 800b7f6: 2300 movs r3, #0 800b7f8: e01d b.n 800b836 } } /* Set the power supply configuration */ MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); 800b7fa: 4b11 ldr r3, [pc, #68] @ (800b840 ) 800b7fc: 68db ldr r3, [r3, #12] 800b7fe: f023 0207 bic.w r2, r3, #7 800b802: 490f ldr r1, [pc, #60] @ (800b840 ) 800b804: 687b ldr r3, [r7, #4] 800b806: 4313 orrs r3, r2 800b808: 60cb str r3, [r1, #12] /* Get tick */ tickstart = HAL_GetTick (); 800b80a: f7fa fb0b bl 8005e24 800b80e: 60f8 str r0, [r7, #12] /* Wait till voltage level flag is set */ while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b810: e009 b.n 800b826 { if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) 800b812: f7fa fb07 bl 8005e24 800b816: 4602 mov r2, r0 800b818: 68fb ldr r3, [r7, #12] 800b81a: 1ad3 subs r3, r2, r3 800b81c: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800b820: d901 bls.n 800b826 { return HAL_ERROR; 800b822: 2301 movs r3, #1 800b824: e007 b.n 800b836 while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) 800b826: 4b06 ldr r3, [pc, #24] @ (800b840 ) 800b828: 685b ldr r3, [r3, #4] 800b82a: f403 5300 and.w r3, r3, #8192 @ 0x2000 800b82e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800b832: d1ee bne.n 800b812 } } } #endif /* defined (SMPS) */ return HAL_OK; 800b834: 2300 movs r3, #0 } 800b836: 4618 mov r0, r3 800b838: 3710 adds r7, #16 800b83a: 46bd mov sp, r7 800b83c: bd80 pop {r7, pc} 800b83e: bf00 nop 800b840: 58024800 .word 0x58024800 0800b844 : * driver. All combination are allowed: wake up only Cortex-M7, wake up * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * @retval None. */ void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) { 800b844: b480 push {r7} 800b846: b083 sub sp, #12 800b848: af00 add r7, sp, #0 800b84a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); /* Set the ALS[18:17] bits according to AVDLevel value */ MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); 800b84c: 4b37 ldr r3, [pc, #220] @ (800b92c ) 800b84e: 681b ldr r3, [r3, #0] 800b850: f423 22c0 bic.w r2, r3, #393216 @ 0x60000 800b854: 687b ldr r3, [r7, #4] 800b856: 681b ldr r3, [r3, #0] 800b858: 4934 ldr r1, [pc, #208] @ (800b92c ) 800b85a: 4313 orrs r3, r2 800b85c: 600b str r3, [r1, #0] /* Clear any previous config */ #if !defined (DUAL_CORE) __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); 800b85e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b862: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b866: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b86a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b86e: f8c2 3084 str.w r3, [r2, #132] @ 0x84 __HAL_PWR_AVD_EXTI_DISABLE_IT (); 800b872: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b876: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b87a: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b87e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b882: f8c2 3080 str.w r3, [r2, #128] @ 0x80 #endif /* !defined (DUAL_CORE) */ __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); 800b886: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b88a: 681b ldr r3, [r3, #0] 800b88c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b890: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b894: 6013 str r3, [r2, #0] __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); 800b896: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b89a: 685b ldr r3, [r3, #4] 800b89c: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8a0: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b8a4: 6053 str r3, [r2, #4] #if !defined (DUAL_CORE) /* Configure the interrupt mode */ if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) 800b8a6: 687b ldr r3, [r7, #4] 800b8a8: 685b ldr r3, [r3, #4] 800b8aa: f403 3380 and.w r3, r3, #65536 @ 0x10000 800b8ae: 2b00 cmp r3, #0 800b8b0: d009 beq.n 800b8c6 { __HAL_PWR_AVD_EXTI_ENABLE_IT (); 800b8b2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8b6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800b8ba: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8be: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b8c2: f8c2 3080 str.w r3, [r2, #128] @ 0x80 } /* Configure the event mode */ if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) 800b8c6: 687b ldr r3, [r7, #4] 800b8c8: 685b ldr r3, [r3, #4] 800b8ca: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b8ce: 2b00 cmp r3, #0 800b8d0: d009 beq.n 800b8e6 { __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); 800b8d2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8d6: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800b8da: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8de: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b8e2: f8c2 3084 str.w r3, [r2, #132] @ 0x84 } #endif /* !defined (DUAL_CORE) */ /* Rising edge configuration */ if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) 800b8e6: 687b ldr r3, [r7, #4] 800b8e8: 685b ldr r3, [r3, #4] 800b8ea: f003 0301 and.w r3, r3, #1 800b8ee: 2b00 cmp r3, #0 800b8f0: d007 beq.n 800b902 { __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); 800b8f2: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b8f6: 681b ldr r3, [r3, #0] 800b8f8: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b8fc: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b900: 6013 str r3, [r2, #0] } /* Falling edge configuration */ if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) 800b902: 687b ldr r3, [r7, #4] 800b904: 685b ldr r3, [r3, #4] 800b906: f003 0302 and.w r3, r3, #2 800b90a: 2b00 cmp r3, #0 800b90c: d007 beq.n 800b91e { __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); 800b90e: f04f 43b0 mov.w r3, #1476395008 @ 0x58000000 800b912: 685b ldr r3, [r3, #4] 800b914: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000 800b918: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b91c: 6053 str r3, [r2, #4] } } 800b91e: bf00 nop 800b920: 370c adds r7, #12 800b922: 46bd mov sp, r7 800b924: f85d 7b04 ldr.w r7, [sp], #4 800b928: 4770 bx lr 800b92a: bf00 nop 800b92c: 58024800 .word 0x58024800 0800b930 : /** * @brief Enable the Analog Voltage Detector (AVD). * @retval None. */ void HAL_PWREx_EnableAVD (void) { 800b930: b480 push {r7} 800b932: af00 add r7, sp, #0 /* Enable the Analog Voltage Detector */ SET_BIT (PWR->CR1, PWR_CR1_AVDEN); 800b934: 4b05 ldr r3, [pc, #20] @ (800b94c ) 800b936: 681b ldr r3, [r3, #0] 800b938: 4a04 ldr r2, [pc, #16] @ (800b94c ) 800b93a: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b93e: 6013 str r3, [r2, #0] } 800b940: bf00 nop 800b942: 46bd mov sp, r7 800b944: f85d 7b04 ldr.w r7, [sp], #4 800b948: 4770 bx lr 800b94a: bf00 nop 800b94c: 58024800 .word 0x58024800 0800b950 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 800b950: b580 push {r7, lr} 800b952: b08c sub sp, #48 @ 0x30 800b954: af00 add r7, sp, #0 800b956: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800b958: 687b ldr r3, [r7, #4] 800b95a: 2b00 cmp r3, #0 800b95c: d102 bne.n 800b964 { return HAL_ERROR; 800b95e: 2301 movs r3, #1 800b960: f000 bc48 b.w 800c1f4 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800b964: 687b ldr r3, [r7, #4] 800b966: 681b ldr r3, [r3, #0] 800b968: f003 0301 and.w r3, r3, #1 800b96c: 2b00 cmp r3, #0 800b96e: f000 8088 beq.w 800ba82 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800b972: 4b99 ldr r3, [pc, #612] @ (800bbd8 ) 800b974: 691b ldr r3, [r3, #16] 800b976: f003 0338 and.w r3, r3, #56 @ 0x38 800b97a: 62fb str r3, [r7, #44] @ 0x2c const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800b97c: 4b96 ldr r3, [pc, #600] @ (800bbd8 ) 800b97e: 6a9b ldr r3, [r3, #40] @ 0x28 800b980: 62bb str r3, [r7, #40] @ 0x28 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) 800b982: 6afb ldr r3, [r7, #44] @ 0x2c 800b984: 2b10 cmp r3, #16 800b986: d007 beq.n 800b998 800b988: 6afb ldr r3, [r7, #44] @ 0x2c 800b98a: 2b18 cmp r3, #24 800b98c: d111 bne.n 800b9b2 800b98e: 6abb ldr r3, [r7, #40] @ 0x28 800b990: f003 0303 and.w r3, r3, #3 800b994: 2b02 cmp r3, #2 800b996: d10c bne.n 800b9b2 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800b998: 4b8f ldr r3, [pc, #572] @ (800bbd8 ) 800b99a: 681b ldr r3, [r3, #0] 800b99c: f403 3300 and.w r3, r3, #131072 @ 0x20000 800b9a0: 2b00 cmp r3, #0 800b9a2: d06d beq.n 800ba80 800b9a4: 687b ldr r3, [r7, #4] 800b9a6: 685b ldr r3, [r3, #4] 800b9a8: 2b00 cmp r3, #0 800b9aa: d169 bne.n 800ba80 { return HAL_ERROR; 800b9ac: 2301 movs r3, #1 800b9ae: f000 bc21 b.w 800c1f4 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800b9b2: 687b ldr r3, [r7, #4] 800b9b4: 685b ldr r3, [r3, #4] 800b9b6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800b9ba: d106 bne.n 800b9ca 800b9bc: 4b86 ldr r3, [pc, #536] @ (800bbd8 ) 800b9be: 681b ldr r3, [r3, #0] 800b9c0: 4a85 ldr r2, [pc, #532] @ (800bbd8 ) 800b9c2: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800b9c6: 6013 str r3, [r2, #0] 800b9c8: e02e b.n 800ba28 800b9ca: 687b ldr r3, [r7, #4] 800b9cc: 685b ldr r3, [r3, #4] 800b9ce: 2b00 cmp r3, #0 800b9d0: d10c bne.n 800b9ec 800b9d2: 4b81 ldr r3, [pc, #516] @ (800bbd8 ) 800b9d4: 681b ldr r3, [r3, #0] 800b9d6: 4a80 ldr r2, [pc, #512] @ (800bbd8 ) 800b9d8: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800b9dc: 6013 str r3, [r2, #0] 800b9de: 4b7e ldr r3, [pc, #504] @ (800bbd8 ) 800b9e0: 681b ldr r3, [r3, #0] 800b9e2: 4a7d ldr r2, [pc, #500] @ (800bbd8 ) 800b9e4: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800b9e8: 6013 str r3, [r2, #0] 800b9ea: e01d b.n 800ba28 800b9ec: 687b ldr r3, [r7, #4] 800b9ee: 685b ldr r3, [r3, #4] 800b9f0: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800b9f4: d10c bne.n 800ba10 800b9f6: 4b78 ldr r3, [pc, #480] @ (800bbd8 ) 800b9f8: 681b ldr r3, [r3, #0] 800b9fa: 4a77 ldr r2, [pc, #476] @ (800bbd8 ) 800b9fc: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800ba00: 6013 str r3, [r2, #0] 800ba02: 4b75 ldr r3, [pc, #468] @ (800bbd8 ) 800ba04: 681b ldr r3, [r3, #0] 800ba06: 4a74 ldr r2, [pc, #464] @ (800bbd8 ) 800ba08: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800ba0c: 6013 str r3, [r2, #0] 800ba0e: e00b b.n 800ba28 800ba10: 4b71 ldr r3, [pc, #452] @ (800bbd8 ) 800ba12: 681b ldr r3, [r3, #0] 800ba14: 4a70 ldr r2, [pc, #448] @ (800bbd8 ) 800ba16: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800ba1a: 6013 str r3, [r2, #0] 800ba1c: 4b6e ldr r3, [pc, #440] @ (800bbd8 ) 800ba1e: 681b ldr r3, [r3, #0] 800ba20: 4a6d ldr r2, [pc, #436] @ (800bbd8 ) 800ba22: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800ba26: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 800ba28: 687b ldr r3, [r7, #4] 800ba2a: 685b ldr r3, [r3, #4] 800ba2c: 2b00 cmp r3, #0 800ba2e: d013 beq.n 800ba58 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba30: f7fa f9f8 bl 8005e24 800ba34: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800ba36: e008 b.n 800ba4a { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800ba38: f7fa f9f4 bl 8005e24 800ba3c: 4602 mov r2, r0 800ba3e: 6a7b ldr r3, [r7, #36] @ 0x24 800ba40: 1ad3 subs r3, r2, r3 800ba42: 2b64 cmp r3, #100 @ 0x64 800ba44: d901 bls.n 800ba4a { return HAL_TIMEOUT; 800ba46: 2303 movs r3, #3 800ba48: e3d4 b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800ba4a: 4b63 ldr r3, [pc, #396] @ (800bbd8 ) 800ba4c: 681b ldr r3, [r3, #0] 800ba4e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ba52: 2b00 cmp r3, #0 800ba54: d0f0 beq.n 800ba38 800ba56: e014 b.n 800ba82 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800ba58: f7fa f9e4 bl 8005e24 800ba5c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800ba5e: e008 b.n 800ba72 { if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800ba60: f7fa f9e0 bl 8005e24 800ba64: 4602 mov r2, r0 800ba66: 6a7b ldr r3, [r7, #36] @ 0x24 800ba68: 1ad3 subs r3, r2, r3 800ba6a: 2b64 cmp r3, #100 @ 0x64 800ba6c: d901 bls.n 800ba72 { return HAL_TIMEOUT; 800ba6e: 2303 movs r3, #3 800ba70: e3c0 b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) 800ba72: 4b59 ldr r3, [pc, #356] @ (800bbd8 ) 800ba74: 681b ldr r3, [r3, #0] 800ba76: f403 3300 and.w r3, r3, #131072 @ 0x20000 800ba7a: 2b00 cmp r3, #0 800ba7c: d1f0 bne.n 800ba60 800ba7e: e000 b.n 800ba82 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800ba80: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800ba82: 687b ldr r3, [r7, #4] 800ba84: 681b ldr r3, [r3, #0] 800ba86: f003 0302 and.w r3, r3, #2 800ba8a: 2b00 cmp r3, #0 800ba8c: f000 80ca beq.w 800bc24 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800ba90: 4b51 ldr r3, [pc, #324] @ (800bbd8 ) 800ba92: 691b ldr r3, [r3, #16] 800ba94: f003 0338 and.w r3, r3, #56 @ 0x38 800ba98: 623b str r3, [r7, #32] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800ba9a: 4b4f ldr r3, [pc, #316] @ (800bbd8 ) 800ba9c: 6a9b ldr r3, [r3, #40] @ 0x28 800ba9e: 61fb str r3, [r7, #28] if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) 800baa0: 6a3b ldr r3, [r7, #32] 800baa2: 2b00 cmp r3, #0 800baa4: d007 beq.n 800bab6 800baa6: 6a3b ldr r3, [r7, #32] 800baa8: 2b18 cmp r3, #24 800baaa: d156 bne.n 800bb5a 800baac: 69fb ldr r3, [r7, #28] 800baae: f003 0303 and.w r3, r3, #3 800bab2: 2b00 cmp r3, #0 800bab4: d151 bne.n 800bb5a { /* When HSI is used as system clock it will not be disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bab6: 4b48 ldr r3, [pc, #288] @ (800bbd8 ) 800bab8: 681b ldr r3, [r3, #0] 800baba: f003 0304 and.w r3, r3, #4 800babe: 2b00 cmp r3, #0 800bac0: d005 beq.n 800bace 800bac2: 687b ldr r3, [r7, #4] 800bac4: 68db ldr r3, [r3, #12] 800bac6: 2b00 cmp r3, #0 800bac8: d101 bne.n 800bace { return HAL_ERROR; 800baca: 2301 movs r3, #1 800bacc: e392 b.n 800c1f4 } /* Otherwise, only HSI division and calibration are allowed */ else { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800bace: 4b42 ldr r3, [pc, #264] @ (800bbd8 ) 800bad0: 681b ldr r3, [r3, #0] 800bad2: f023 0219 bic.w r2, r3, #25 800bad6: 687b ldr r3, [r7, #4] 800bad8: 68db ldr r3, [r3, #12] 800bada: 493f ldr r1, [pc, #252] @ (800bbd8 ) 800badc: 4313 orrs r3, r2 800bade: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bae0: f7fa f9a0 bl 8005e24 800bae4: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bae6: e008 b.n 800bafa { if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bae8: f7fa f99c bl 8005e24 800baec: 4602 mov r2, r0 800baee: 6a7b ldr r3, [r7, #36] @ 0x24 800baf0: 1ad3 subs r3, r2, r3 800baf2: 2b02 cmp r3, #2 800baf4: d901 bls.n 800bafa { return HAL_TIMEOUT; 800baf6: 2303 movs r3, #3 800baf8: e37c b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bafa: 4b37 ldr r3, [pc, #220] @ (800bbd8 ) 800bafc: 681b ldr r3, [r3, #0] 800bafe: f003 0304 and.w r3, r3, #4 800bb02: 2b00 cmp r3, #0 800bb04: d0f0 beq.n 800bae8 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb06: f7fa f999 bl 8005e3c 800bb0a: 4603 mov r3, r0 800bb0c: f241 0203 movw r2, #4099 @ 0x1003 800bb10: 4293 cmp r3, r2 800bb12: d817 bhi.n 800bb44 800bb14: 687b ldr r3, [r7, #4] 800bb16: 691b ldr r3, [r3, #16] 800bb18: 2b40 cmp r3, #64 @ 0x40 800bb1a: d108 bne.n 800bb2e 800bb1c: 4b2e ldr r3, [pc, #184] @ (800bbd8 ) 800bb1e: 685b ldr r3, [r3, #4] 800bb20: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800bb24: 4a2c ldr r2, [pc, #176] @ (800bbd8 ) 800bb26: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bb2a: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb2c: e07a b.n 800bc24 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb2e: 4b2a ldr r3, [pc, #168] @ (800bbd8 ) 800bb30: 685b ldr r3, [r3, #4] 800bb32: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800bb36: 687b ldr r3, [r7, #4] 800bb38: 691b ldr r3, [r3, #16] 800bb3a: 031b lsls r3, r3, #12 800bb3c: 4926 ldr r1, [pc, #152] @ (800bbd8 ) 800bb3e: 4313 orrs r3, r2 800bb40: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb42: e06f b.n 800bc24 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb44: 4b24 ldr r3, [pc, #144] @ (800bbd8 ) 800bb46: 685b ldr r3, [r3, #4] 800bb48: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800bb4c: 687b ldr r3, [r7, #4] 800bb4e: 691b ldr r3, [r3, #16] 800bb50: 061b lsls r3, r3, #24 800bb52: 4921 ldr r1, [pc, #132] @ (800bbd8 ) 800bb54: 4313 orrs r3, r2 800bb56: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 800bb58: e064 b.n 800bc24 } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800bb5a: 687b ldr r3, [r7, #4] 800bb5c: 68db ldr r3, [r3, #12] 800bb5e: 2b00 cmp r3, #0 800bb60: d047 beq.n 800bbf2 { /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); 800bb62: 4b1d ldr r3, [pc, #116] @ (800bbd8 ) 800bb64: 681b ldr r3, [r3, #0] 800bb66: f023 0219 bic.w r2, r3, #25 800bb6a: 687b ldr r3, [r7, #4] 800bb6c: 68db ldr r3, [r3, #12] 800bb6e: 491a ldr r1, [pc, #104] @ (800bbd8 ) 800bb70: 4313 orrs r3, r2 800bb72: 600b str r3, [r1, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bb74: f7fa f956 bl 8005e24 800bb78: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bb7a: e008 b.n 800bb8e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bb7c: f7fa f952 bl 8005e24 800bb80: 4602 mov r2, r0 800bb82: 6a7b ldr r3, [r7, #36] @ 0x24 800bb84: 1ad3 subs r3, r2, r3 800bb86: 2b02 cmp r3, #2 800bb88: d901 bls.n 800bb8e { return HAL_TIMEOUT; 800bb8a: 2303 movs r3, #3 800bb8c: e332 b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800bb8e: 4b12 ldr r3, [pc, #72] @ (800bbd8 ) 800bb90: 681b ldr r3, [r3, #0] 800bb92: f003 0304 and.w r3, r3, #4 800bb96: 2b00 cmp r3, #0 800bb98: d0f0 beq.n 800bb7c } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 800bb9a: f7fa f94f bl 8005e3c 800bb9e: 4603 mov r3, r0 800bba0: f241 0203 movw r2, #4099 @ 0x1003 800bba4: 4293 cmp r3, r2 800bba6: d819 bhi.n 800bbdc 800bba8: 687b ldr r3, [r7, #4] 800bbaa: 691b ldr r3, [r3, #16] 800bbac: 2b40 cmp r3, #64 @ 0x40 800bbae: d108 bne.n 800bbc2 800bbb0: 4b09 ldr r3, [pc, #36] @ (800bbd8 ) 800bbb2: 685b ldr r3, [r3, #4] 800bbb4: f423 337c bic.w r3, r3, #258048 @ 0x3f000 800bbb8: 4a07 ldr r2, [pc, #28] @ (800bbd8 ) 800bbba: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800bbbe: 6053 str r3, [r2, #4] 800bbc0: e030 b.n 800bc24 800bbc2: 4b05 ldr r3, [pc, #20] @ (800bbd8 ) 800bbc4: 685b ldr r3, [r3, #4] 800bbc6: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800bbca: 687b ldr r3, [r7, #4] 800bbcc: 691b ldr r3, [r3, #16] 800bbce: 031b lsls r3, r3, #12 800bbd0: 4901 ldr r1, [pc, #4] @ (800bbd8 ) 800bbd2: 4313 orrs r3, r2 800bbd4: 604b str r3, [r1, #4] 800bbd6: e025 b.n 800bc24 800bbd8: 58024400 .word 0x58024400 800bbdc: 4b9a ldr r3, [pc, #616] @ (800be48 ) 800bbde: 685b ldr r3, [r3, #4] 800bbe0: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000 800bbe4: 687b ldr r3, [r7, #4] 800bbe6: 691b ldr r3, [r3, #16] 800bbe8: 061b lsls r3, r3, #24 800bbea: 4997 ldr r1, [pc, #604] @ (800be48 ) 800bbec: 4313 orrs r3, r2 800bbee: 604b str r3, [r1, #4] 800bbf0: e018 b.n 800bc24 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800bbf2: 4b95 ldr r3, [pc, #596] @ (800be48 ) 800bbf4: 681b ldr r3, [r3, #0] 800bbf6: 4a94 ldr r2, [pc, #592] @ (800be48 ) 800bbf8: f023 0301 bic.w r3, r3, #1 800bbfc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bbfe: f7fa f911 bl 8005e24 800bc02: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800bc04: e008 b.n 800bc18 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800bc06: f7fa f90d bl 8005e24 800bc0a: 4602 mov r2, r0 800bc0c: 6a7b ldr r3, [r7, #36] @ 0x24 800bc0e: 1ad3 subs r3, r2, r3 800bc10: 2b02 cmp r3, #2 800bc12: d901 bls.n 800bc18 { return HAL_TIMEOUT; 800bc14: 2303 movs r3, #3 800bc16: e2ed b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) 800bc18: 4b8b ldr r3, [pc, #556] @ (800be48 ) 800bc1a: 681b ldr r3, [r3, #0] 800bc1c: f003 0304 and.w r3, r3, #4 800bc20: 2b00 cmp r3, #0 800bc22: d1f0 bne.n 800bc06 } } } } /*----------------------------- CSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) 800bc24: 687b ldr r3, [r7, #4] 800bc26: 681b ldr r3, [r3, #0] 800bc28: f003 0310 and.w r3, r3, #16 800bc2c: 2b00 cmp r3, #0 800bc2e: f000 80a9 beq.w 800bd84 /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 800bc32: 4b85 ldr r3, [pc, #532] @ (800be48 ) 800bc34: 691b ldr r3, [r3, #16] 800bc36: f003 0338 and.w r3, r3, #56 @ 0x38 800bc3a: 61bb str r3, [r7, #24] const uint32_t temp_pllckselr = RCC->PLLCKSELR; 800bc3c: 4b82 ldr r3, [pc, #520] @ (800be48 ) 800bc3e: 6a9b ldr r3, [r3, #40] @ 0x28 800bc40: 617b str r3, [r7, #20] if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) 800bc42: 69bb ldr r3, [r7, #24] 800bc44: 2b08 cmp r3, #8 800bc46: d007 beq.n 800bc58 800bc48: 69bb ldr r3, [r7, #24] 800bc4a: 2b18 cmp r3, #24 800bc4c: d13a bne.n 800bcc4 800bc4e: 697b ldr r3, [r7, #20] 800bc50: f003 0303 and.w r3, r3, #3 800bc54: 2b01 cmp r3, #1 800bc56: d135 bne.n 800bcc4 { /* When CSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bc58: 4b7b ldr r3, [pc, #492] @ (800be48 ) 800bc5a: 681b ldr r3, [r3, #0] 800bc5c: f403 7380 and.w r3, r3, #256 @ 0x100 800bc60: 2b00 cmp r3, #0 800bc62: d005 beq.n 800bc70 800bc64: 687b ldr r3, [r7, #4] 800bc66: 69db ldr r3, [r3, #28] 800bc68: 2b80 cmp r3, #128 @ 0x80 800bc6a: d001 beq.n 800bc70 { return HAL_ERROR; 800bc6c: 2301 movs r3, #1 800bc6e: e2c1 b.n 800c1f4 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bc70: f7fa f8e4 bl 8005e3c 800bc74: 4603 mov r3, r0 800bc76: f241 0203 movw r2, #4099 @ 0x1003 800bc7a: 4293 cmp r3, r2 800bc7c: d817 bhi.n 800bcae 800bc7e: 687b ldr r3, [r7, #4] 800bc80: 6a1b ldr r3, [r3, #32] 800bc82: 2b20 cmp r3, #32 800bc84: d108 bne.n 800bc98 800bc86: 4b70 ldr r3, [pc, #448] @ (800be48 ) 800bc88: 685b ldr r3, [r3, #4] 800bc8a: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800bc8e: 4a6e ldr r2, [pc, #440] @ (800be48 ) 800bc90: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800bc94: 6053 str r3, [r2, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bc96: e075 b.n 800bd84 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bc98: 4b6b ldr r3, [pc, #428] @ (800be48 ) 800bc9a: 685b ldr r3, [r3, #4] 800bc9c: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800bca0: 687b ldr r3, [r7, #4] 800bca2: 6a1b ldr r3, [r3, #32] 800bca4: 069b lsls r3, r3, #26 800bca6: 4968 ldr r1, [pc, #416] @ (800be48 ) 800bca8: 4313 orrs r3, r2 800bcaa: 604b str r3, [r1, #4] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bcac: e06a b.n 800bd84 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bcae: 4b66 ldr r3, [pc, #408] @ (800be48 ) 800bcb0: 68db ldr r3, [r3, #12] 800bcb2: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800bcb6: 687b ldr r3, [r7, #4] 800bcb8: 6a1b ldr r3, [r3, #32] 800bcba: 061b lsls r3, r3, #24 800bcbc: 4962 ldr r1, [pc, #392] @ (800be48 ) 800bcbe: 4313 orrs r3, r2 800bcc0: 60cb str r3, [r1, #12] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) 800bcc2: e05f b.n 800bd84 } } else { /* Check the CSI State */ if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) 800bcc4: 687b ldr r3, [r7, #4] 800bcc6: 69db ldr r3, [r3, #28] 800bcc8: 2b00 cmp r3, #0 800bcca: d042 beq.n 800bd52 { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); 800bccc: 4b5e ldr r3, [pc, #376] @ (800be48 ) 800bcce: 681b ldr r3, [r3, #0] 800bcd0: 4a5d ldr r2, [pc, #372] @ (800be48 ) 800bcd2: f043 0380 orr.w r3, r3, #128 @ 0x80 800bcd6: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bcd8: f7fa f8a4 bl 8005e24 800bcdc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bcde: e008 b.n 800bcf2 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800bce0: f7fa f8a0 bl 8005e24 800bce4: 4602 mov r2, r0 800bce6: 6a7b ldr r3, [r7, #36] @ 0x24 800bce8: 1ad3 subs r3, r2, r3 800bcea: 2b02 cmp r3, #2 800bcec: d901 bls.n 800bcf2 { return HAL_TIMEOUT; 800bcee: 2303 movs r3, #3 800bcf0: e280 b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800bcf2: 4b55 ldr r3, [pc, #340] @ (800be48 ) 800bcf4: 681b ldr r3, [r3, #0] 800bcf6: f403 7380 and.w r3, r3, #256 @ 0x100 800bcfa: 2b00 cmp r3, #0 800bcfc: d0f0 beq.n 800bce0 } } /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); 800bcfe: f7fa f89d bl 8005e3c 800bd02: 4603 mov r3, r0 800bd04: f241 0203 movw r2, #4099 @ 0x1003 800bd08: 4293 cmp r3, r2 800bd0a: d817 bhi.n 800bd3c 800bd0c: 687b ldr r3, [r7, #4] 800bd0e: 6a1b ldr r3, [r3, #32] 800bd10: 2b20 cmp r3, #32 800bd12: d108 bne.n 800bd26 800bd14: 4b4c ldr r3, [pc, #304] @ (800be48 ) 800bd16: 685b ldr r3, [r3, #4] 800bd18: f023 43f8 bic.w r3, r3, #2080374784 @ 0x7c000000 800bd1c: 4a4a ldr r2, [pc, #296] @ (800be48 ) 800bd1e: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800bd22: 6053 str r3, [r2, #4] 800bd24: e02e b.n 800bd84 800bd26: 4b48 ldr r3, [pc, #288] @ (800be48 ) 800bd28: 685b ldr r3, [r3, #4] 800bd2a: f023 42f8 bic.w r2, r3, #2080374784 @ 0x7c000000 800bd2e: 687b ldr r3, [r7, #4] 800bd30: 6a1b ldr r3, [r3, #32] 800bd32: 069b lsls r3, r3, #26 800bd34: 4944 ldr r1, [pc, #272] @ (800be48 ) 800bd36: 4313 orrs r3, r2 800bd38: 604b str r3, [r1, #4] 800bd3a: e023 b.n 800bd84 800bd3c: 4b42 ldr r3, [pc, #264] @ (800be48 ) 800bd3e: 68db ldr r3, [r3, #12] 800bd40: f023 527c bic.w r2, r3, #1056964608 @ 0x3f000000 800bd44: 687b ldr r3, [r7, #4] 800bd46: 6a1b ldr r3, [r3, #32] 800bd48: 061b lsls r3, r3, #24 800bd4a: 493f ldr r1, [pc, #252] @ (800be48 ) 800bd4c: 4313 orrs r3, r2 800bd4e: 60cb str r3, [r1, #12] 800bd50: e018 b.n 800bd84 } else { /* Disable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_DISABLE(); 800bd52: 4b3d ldr r3, [pc, #244] @ (800be48 ) 800bd54: 681b ldr r3, [r3, #0] 800bd56: 4a3c ldr r2, [pc, #240] @ (800be48 ) 800bd58: f023 0380 bic.w r3, r3, #128 @ 0x80 800bd5c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bd5e: f7fa f861 bl 8005e24 800bd62: 6278 str r0, [r7, #36] @ 0x24 /* Wait till CSI is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800bd64: e008 b.n 800bd78 { if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) 800bd66: f7fa f85d bl 8005e24 800bd6a: 4602 mov r2, r0 800bd6c: 6a7b ldr r3, [r7, #36] @ 0x24 800bd6e: 1ad3 subs r3, r2, r3 800bd70: 2b02 cmp r3, #2 800bd72: d901 bls.n 800bd78 { return HAL_TIMEOUT; 800bd74: 2303 movs r3, #3 800bd76: e23d b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) 800bd78: 4b33 ldr r3, [pc, #204] @ (800be48 ) 800bd7a: 681b ldr r3, [r3, #0] 800bd7c: f403 7380 and.w r3, r3, #256 @ 0x100 800bd80: 2b00 cmp r3, #0 800bd82: d1f0 bne.n 800bd66 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800bd84: 687b ldr r3, [r7, #4] 800bd86: 681b ldr r3, [r3, #0] 800bd88: f003 0308 and.w r3, r3, #8 800bd8c: 2b00 cmp r3, #0 800bd8e: d036 beq.n 800bdfe { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800bd90: 687b ldr r3, [r7, #4] 800bd92: 695b ldr r3, [r3, #20] 800bd94: 2b00 cmp r3, #0 800bd96: d019 beq.n 800bdcc { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800bd98: 4b2b ldr r3, [pc, #172] @ (800be48 ) 800bd9a: 6f5b ldr r3, [r3, #116] @ 0x74 800bd9c: 4a2a ldr r2, [pc, #168] @ (800be48 ) 800bd9e: f043 0301 orr.w r3, r3, #1 800bda2: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bda4: f7fa f83e bl 8005e24 800bda8: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800bdaa: e008 b.n 800bdbe { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800bdac: f7fa f83a bl 8005e24 800bdb0: 4602 mov r2, r0 800bdb2: 6a7b ldr r3, [r7, #36] @ 0x24 800bdb4: 1ad3 subs r3, r2, r3 800bdb6: 2b02 cmp r3, #2 800bdb8: d901 bls.n 800bdbe { return HAL_TIMEOUT; 800bdba: 2303 movs r3, #3 800bdbc: e21a b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) 800bdbe: 4b22 ldr r3, [pc, #136] @ (800be48 ) 800bdc0: 6f5b ldr r3, [r3, #116] @ 0x74 800bdc2: f003 0302 and.w r3, r3, #2 800bdc6: 2b00 cmp r3, #0 800bdc8: d0f0 beq.n 800bdac 800bdca: e018 b.n 800bdfe } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800bdcc: 4b1e ldr r3, [pc, #120] @ (800be48 ) 800bdce: 6f5b ldr r3, [r3, #116] @ 0x74 800bdd0: 4a1d ldr r2, [pc, #116] @ (800be48 ) 800bdd2: f023 0301 bic.w r3, r3, #1 800bdd6: 6753 str r3, [r2, #116] @ 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bdd8: f7fa f824 bl 8005e24 800bddc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800bdde: e008 b.n 800bdf2 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800bde0: f7fa f820 bl 8005e24 800bde4: 4602 mov r2, r0 800bde6: 6a7b ldr r3, [r7, #36] @ 0x24 800bde8: 1ad3 subs r3, r2, r3 800bdea: 2b02 cmp r3, #2 800bdec: d901 bls.n 800bdf2 { return HAL_TIMEOUT; 800bdee: 2303 movs r3, #3 800bdf0: e200 b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) 800bdf2: 4b15 ldr r3, [pc, #84] @ (800be48 ) 800bdf4: 6f5b ldr r3, [r3, #116] @ 0x74 800bdf6: f003 0302 and.w r3, r3, #2 800bdfa: 2b00 cmp r3, #0 800bdfc: d1f0 bne.n 800bde0 } } } /*------------------------------ HSI48 Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 800bdfe: 687b ldr r3, [r7, #4] 800be00: 681b ldr r3, [r3, #0] 800be02: f003 0320 and.w r3, r3, #32 800be06: 2b00 cmp r3, #0 800be08: d039 beq.n 800be7e { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) 800be0a: 687b ldr r3, [r7, #4] 800be0c: 699b ldr r3, [r3, #24] 800be0e: 2b00 cmp r3, #0 800be10: d01c beq.n 800be4c { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 800be12: 4b0d ldr r3, [pc, #52] @ (800be48 ) 800be14: 681b ldr r3, [r3, #0] 800be16: 4a0c ldr r2, [pc, #48] @ (800be48 ) 800be18: f443 5380 orr.w r3, r3, #4096 @ 0x1000 800be1c: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800be1e: f7fa f801 bl 8005e24 800be22: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800be24: e008 b.n 800be38 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800be26: f7f9 fffd bl 8005e24 800be2a: 4602 mov r2, r0 800be2c: 6a7b ldr r3, [r7, #36] @ 0x24 800be2e: 1ad3 subs r3, r2, r3 800be30: 2b02 cmp r3, #2 800be32: d901 bls.n 800be38 { return HAL_TIMEOUT; 800be34: 2303 movs r3, #3 800be36: e1dd b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) 800be38: 4b03 ldr r3, [pc, #12] @ (800be48 ) 800be3a: 681b ldr r3, [r3, #0] 800be3c: f403 5300 and.w r3, r3, #8192 @ 0x2000 800be40: 2b00 cmp r3, #0 800be42: d0f0 beq.n 800be26 800be44: e01b b.n 800be7e 800be46: bf00 nop 800be48: 58024400 .word 0x58024400 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 800be4c: 4b9b ldr r3, [pc, #620] @ (800c0bc ) 800be4e: 681b ldr r3, [r3, #0] 800be50: 4a9a ldr r2, [pc, #616] @ (800c0bc ) 800be52: f423 5380 bic.w r3, r3, #4096 @ 0x1000 800be56: 6013 str r3, [r2, #0] /* Get time-out */ tickstart = HAL_GetTick(); 800be58: f7f9 ffe4 bl 8005e24 800be5c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till HSI48 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800be5e: e008 b.n 800be72 { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 800be60: f7f9 ffe0 bl 8005e24 800be64: 4602 mov r2, r0 800be66: 6a7b ldr r3, [r7, #36] @ 0x24 800be68: 1ad3 subs r3, r2, r3 800be6a: 2b02 cmp r3, #2 800be6c: d901 bls.n 800be72 { return HAL_TIMEOUT; 800be6e: 2303 movs r3, #3 800be70: e1c0 b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) 800be72: 4b92 ldr r3, [pc, #584] @ (800c0bc ) 800be74: 681b ldr r3, [r3, #0] 800be76: f403 5300 and.w r3, r3, #8192 @ 0x2000 800be7a: 2b00 cmp r3, #0 800be7c: d1f0 bne.n 800be60 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800be7e: 687b ldr r3, [r7, #4] 800be80: 681b ldr r3, [r3, #0] 800be82: f003 0304 and.w r3, r3, #4 800be86: 2b00 cmp r3, #0 800be88: f000 8081 beq.w 800bf8e { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; 800be8c: 4b8c ldr r3, [pc, #560] @ (800c0c0 ) 800be8e: 681b ldr r3, [r3, #0] 800be90: 4a8b ldr r2, [pc, #556] @ (800c0c0 ) 800be92: f443 7380 orr.w r3, r3, #256 @ 0x100 800be96: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800be98: f7f9 ffc4 bl 8005e24 800be9c: 6278 str r0, [r7, #36] @ 0x24 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800be9e: e008 b.n 800beb2 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800bea0: f7f9 ffc0 bl 8005e24 800bea4: 4602 mov r2, r0 800bea6: 6a7b ldr r3, [r7, #36] @ 0x24 800bea8: 1ad3 subs r3, r2, r3 800beaa: 2b64 cmp r3, #100 @ 0x64 800beac: d901 bls.n 800beb2 { return HAL_TIMEOUT; 800beae: 2303 movs r3, #3 800beb0: e1a0 b.n 800c1f4 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800beb2: 4b83 ldr r3, [pc, #524] @ (800c0c0 ) 800beb4: 681b ldr r3, [r3, #0] 800beb6: f403 7380 and.w r3, r3, #256 @ 0x100 800beba: 2b00 cmp r3, #0 800bebc: d0f0 beq.n 800bea0 } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 800bebe: 687b ldr r3, [r7, #4] 800bec0: 689b ldr r3, [r3, #8] 800bec2: 2b01 cmp r3, #1 800bec4: d106 bne.n 800bed4 800bec6: 4b7d ldr r3, [pc, #500] @ (800c0bc ) 800bec8: 6f1b ldr r3, [r3, #112] @ 0x70 800beca: 4a7c ldr r2, [pc, #496] @ (800c0bc ) 800becc: f043 0301 orr.w r3, r3, #1 800bed0: 6713 str r3, [r2, #112] @ 0x70 800bed2: e02d b.n 800bf30 800bed4: 687b ldr r3, [r7, #4] 800bed6: 689b ldr r3, [r3, #8] 800bed8: 2b00 cmp r3, #0 800beda: d10c bne.n 800bef6 800bedc: 4b77 ldr r3, [pc, #476] @ (800c0bc ) 800bede: 6f1b ldr r3, [r3, #112] @ 0x70 800bee0: 4a76 ldr r2, [pc, #472] @ (800c0bc ) 800bee2: f023 0301 bic.w r3, r3, #1 800bee6: 6713 str r3, [r2, #112] @ 0x70 800bee8: 4b74 ldr r3, [pc, #464] @ (800c0bc ) 800beea: 6f1b ldr r3, [r3, #112] @ 0x70 800beec: 4a73 ldr r2, [pc, #460] @ (800c0bc ) 800beee: f023 0304 bic.w r3, r3, #4 800bef2: 6713 str r3, [r2, #112] @ 0x70 800bef4: e01c b.n 800bf30 800bef6: 687b ldr r3, [r7, #4] 800bef8: 689b ldr r3, [r3, #8] 800befa: 2b05 cmp r3, #5 800befc: d10c bne.n 800bf18 800befe: 4b6f ldr r3, [pc, #444] @ (800c0bc ) 800bf00: 6f1b ldr r3, [r3, #112] @ 0x70 800bf02: 4a6e ldr r2, [pc, #440] @ (800c0bc ) 800bf04: f043 0304 orr.w r3, r3, #4 800bf08: 6713 str r3, [r2, #112] @ 0x70 800bf0a: 4b6c ldr r3, [pc, #432] @ (800c0bc ) 800bf0c: 6f1b ldr r3, [r3, #112] @ 0x70 800bf0e: 4a6b ldr r2, [pc, #428] @ (800c0bc ) 800bf10: f043 0301 orr.w r3, r3, #1 800bf14: 6713 str r3, [r2, #112] @ 0x70 800bf16: e00b b.n 800bf30 800bf18: 4b68 ldr r3, [pc, #416] @ (800c0bc ) 800bf1a: 6f1b ldr r3, [r3, #112] @ 0x70 800bf1c: 4a67 ldr r2, [pc, #412] @ (800c0bc ) 800bf1e: f023 0301 bic.w r3, r3, #1 800bf22: 6713 str r3, [r2, #112] @ 0x70 800bf24: 4b65 ldr r3, [pc, #404] @ (800c0bc ) 800bf26: 6f1b ldr r3, [r3, #112] @ 0x70 800bf28: 4a64 ldr r2, [pc, #400] @ (800c0bc ) 800bf2a: f023 0304 bic.w r3, r3, #4 800bf2e: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 800bf30: 687b ldr r3, [r7, #4] 800bf32: 689b ldr r3, [r3, #8] 800bf34: 2b00 cmp r3, #0 800bf36: d015 beq.n 800bf64 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf38: f7f9 ff74 bl 8005e24 800bf3c: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bf3e: e00a b.n 800bf56 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bf40: f7f9 ff70 bl 8005e24 800bf44: 4602 mov r2, r0 800bf46: 6a7b ldr r3, [r7, #36] @ 0x24 800bf48: 1ad3 subs r3, r2, r3 800bf4a: f241 3288 movw r2, #5000 @ 0x1388 800bf4e: 4293 cmp r3, r2 800bf50: d901 bls.n 800bf56 { return HAL_TIMEOUT; 800bf52: 2303 movs r3, #3 800bf54: e14e b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800bf56: 4b59 ldr r3, [pc, #356] @ (800c0bc ) 800bf58: 6f1b ldr r3, [r3, #112] @ 0x70 800bf5a: f003 0302 and.w r3, r3, #2 800bf5e: 2b00 cmp r3, #0 800bf60: d0ee beq.n 800bf40 800bf62: e014 b.n 800bf8e } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bf64: f7f9 ff5e bl 8005e24 800bf68: 6278 str r0, [r7, #36] @ 0x24 /* Wait till LSE is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bf6a: e00a b.n 800bf82 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800bf6c: f7f9 ff5a bl 8005e24 800bf70: 4602 mov r2, r0 800bf72: 6a7b ldr r3, [r7, #36] @ 0x24 800bf74: 1ad3 subs r3, r2, r3 800bf76: f241 3288 movw r2, #5000 @ 0x1388 800bf7a: 4293 cmp r3, r2 800bf7c: d901 bls.n 800bf82 { return HAL_TIMEOUT; 800bf7e: 2303 movs r3, #3 800bf80: e138 b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) 800bf82: 4b4e ldr r3, [pc, #312] @ (800c0bc ) 800bf84: 6f1b ldr r3, [r3, #112] @ 0x70 800bf86: f003 0302 and.w r3, r3, #2 800bf8a: 2b00 cmp r3, #0 800bf8c: d1ee bne.n 800bf6c } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 800bf8e: 687b ldr r3, [r7, #4] 800bf90: 6a5b ldr r3, [r3, #36] @ 0x24 800bf92: 2b00 cmp r3, #0 800bf94: f000 812d beq.w 800c1f2 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) 800bf98: 4b48 ldr r3, [pc, #288] @ (800c0bc ) 800bf9a: 691b ldr r3, [r3, #16] 800bf9c: f003 0338 and.w r3, r3, #56 @ 0x38 800bfa0: 2b18 cmp r3, #24 800bfa2: f000 80bd beq.w 800c120 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 800bfa6: 687b ldr r3, [r7, #4] 800bfa8: 6a5b ldr r3, [r3, #36] @ 0x24 800bfaa: 2b02 cmp r3, #2 800bfac: f040 809e bne.w 800c0ec assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800bfb0: 4b42 ldr r3, [pc, #264] @ (800c0bc ) 800bfb2: 681b ldr r3, [r3, #0] 800bfb4: 4a41 ldr r2, [pc, #260] @ (800c0bc ) 800bfb6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800bfba: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800bfbc: f7f9 ff32 bl 8005e24 800bfc0: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bfc2: e008 b.n 800bfd6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800bfc4: f7f9 ff2e bl 8005e24 800bfc8: 4602 mov r2, r0 800bfca: 6a7b ldr r3, [r7, #36] @ 0x24 800bfcc: 1ad3 subs r3, r2, r3 800bfce: 2b02 cmp r3, #2 800bfd0: d901 bls.n 800bfd6 { return HAL_TIMEOUT; 800bfd2: 2303 movs r3, #3 800bfd4: e10e b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800bfd6: 4b39 ldr r3, [pc, #228] @ (800c0bc ) 800bfd8: 681b ldr r3, [r3, #0] 800bfda: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800bfde: 2b00 cmp r3, #0 800bfe0: d1f0 bne.n 800bfc4 } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 800bfe2: 4b36 ldr r3, [pc, #216] @ (800c0bc ) 800bfe4: 6a9a ldr r2, [r3, #40] @ 0x28 800bfe6: 4b37 ldr r3, [pc, #220] @ (800c0c4 ) 800bfe8: 4013 ands r3, r2 800bfea: 687a ldr r2, [r7, #4] 800bfec: 6a91 ldr r1, [r2, #40] @ 0x28 800bfee: 687a ldr r2, [r7, #4] 800bff0: 6ad2 ldr r2, [r2, #44] @ 0x2c 800bff2: 0112 lsls r2, r2, #4 800bff4: 430a orrs r2, r1 800bff6: 4931 ldr r1, [pc, #196] @ (800c0bc ) 800bff8: 4313 orrs r3, r2 800bffa: 628b str r3, [r1, #40] @ 0x28 800bffc: 687b ldr r3, [r7, #4] 800bffe: 6b1b ldr r3, [r3, #48] @ 0x30 800c000: 3b01 subs r3, #1 800c002: f3c3 0208 ubfx r2, r3, #0, #9 800c006: 687b ldr r3, [r7, #4] 800c008: 6b5b ldr r3, [r3, #52] @ 0x34 800c00a: 3b01 subs r3, #1 800c00c: 025b lsls r3, r3, #9 800c00e: b29b uxth r3, r3 800c010: 431a orrs r2, r3 800c012: 687b ldr r3, [r7, #4] 800c014: 6b9b ldr r3, [r3, #56] @ 0x38 800c016: 3b01 subs r3, #1 800c018: 041b lsls r3, r3, #16 800c01a: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800c01e: 431a orrs r2, r3 800c020: 687b ldr r3, [r7, #4] 800c022: 6bdb ldr r3, [r3, #60] @ 0x3c 800c024: 3b01 subs r3, #1 800c026: 061b lsls r3, r3, #24 800c028: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800c02c: 4923 ldr r1, [pc, #140] @ (800c0bc ) 800c02e: 4313 orrs r3, r2 800c030: 630b str r3, [r1, #48] @ 0x30 RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Disable PLLFRACN . */ __HAL_RCC_PLLFRACN_DISABLE(); 800c032: 4b22 ldr r3, [pc, #136] @ (800c0bc ) 800c034: 6adb ldr r3, [r3, #44] @ 0x2c 800c036: 4a21 ldr r2, [pc, #132] @ (800c0bc ) 800c038: f023 0301 bic.w r3, r3, #1 800c03c: 62d3 str r3, [r2, #44] @ 0x2c /* Configure PLL PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800c03e: 4b1f ldr r3, [pc, #124] @ (800c0bc ) 800c040: 6b5a ldr r2, [r3, #52] @ 0x34 800c042: 4b21 ldr r3, [pc, #132] @ (800c0c8 ) 800c044: 4013 ands r3, r2 800c046: 687a ldr r2, [r7, #4] 800c048: 6c92 ldr r2, [r2, #72] @ 0x48 800c04a: 00d2 lsls r2, r2, #3 800c04c: 491b ldr r1, [pc, #108] @ (800c0bc ) 800c04e: 4313 orrs r3, r2 800c050: 634b str r3, [r1, #52] @ 0x34 /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; 800c052: 4b1a ldr r3, [pc, #104] @ (800c0bc ) 800c054: 6adb ldr r3, [r3, #44] @ 0x2c 800c056: f023 020c bic.w r2, r3, #12 800c05a: 687b ldr r3, [r7, #4] 800c05c: 6c1b ldr r3, [r3, #64] @ 0x40 800c05e: 4917 ldr r1, [pc, #92] @ (800c0bc ) 800c060: 4313 orrs r3, r2 800c062: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL1 output frequency range : VCO */ __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; 800c064: 4b15 ldr r3, [pc, #84] @ (800c0bc ) 800c066: 6adb ldr r3, [r3, #44] @ 0x2c 800c068: f023 0202 bic.w r2, r3, #2 800c06c: 687b ldr r3, [r7, #4] 800c06e: 6c5b ldr r3, [r3, #68] @ 0x44 800c070: 4912 ldr r1, [pc, #72] @ (800c0bc ) 800c072: 4313 orrs r3, r2 800c074: 62cb str r3, [r1, #44] @ 0x2c /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); 800c076: 4b11 ldr r3, [pc, #68] @ (800c0bc ) 800c078: 6adb ldr r3, [r3, #44] @ 0x2c 800c07a: 4a10 ldr r2, [pc, #64] @ (800c0bc ) 800c07c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800c080: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1Q Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c082: 4b0e ldr r3, [pc, #56] @ (800c0bc ) 800c084: 6adb ldr r3, [r3, #44] @ 0x2c 800c086: 4a0d ldr r2, [pc, #52] @ (800c0bc ) 800c088: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800c08c: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1R Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); 800c08e: 4b0b ldr r3, [pc, #44] @ (800c0bc ) 800c090: 6adb ldr r3, [r3, #44] @ 0x2c 800c092: 4a0a ldr r2, [pc, #40] @ (800c0bc ) 800c094: f443 2380 orr.w r3, r3, #262144 @ 0x40000 800c098: 62d3 str r3, [r2, #44] @ 0x2c /* Enable PLL1FRACN . */ __HAL_RCC_PLLFRACN_ENABLE(); 800c09a: 4b08 ldr r3, [pc, #32] @ (800c0bc ) 800c09c: 6adb ldr r3, [r3, #44] @ 0x2c 800c09e: 4a07 ldr r2, [pc, #28] @ (800c0bc ) 800c0a0: f043 0301 orr.w r3, r3, #1 800c0a4: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800c0a6: 4b05 ldr r3, [pc, #20] @ (800c0bc ) 800c0a8: 681b ldr r3, [r3, #0] 800c0aa: 4a04 ldr r2, [pc, #16] @ (800c0bc ) 800c0ac: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800c0b0: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c0b2: f7f9 feb7 bl 8005e24 800c0b6: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c0b8: e011 b.n 800c0de 800c0ba: bf00 nop 800c0bc: 58024400 .word 0x58024400 800c0c0: 58024800 .word 0x58024800 800c0c4: fffffc0c .word 0xfffffc0c 800c0c8: ffff0007 .word 0xffff0007 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c0cc: f7f9 feaa bl 8005e24 800c0d0: 4602 mov r2, r0 800c0d2: 6a7b ldr r3, [r7, #36] @ 0x24 800c0d4: 1ad3 subs r3, r2, r3 800c0d6: 2b02 cmp r3, #2 800c0d8: d901 bls.n 800c0de { return HAL_TIMEOUT; 800c0da: 2303 movs r3, #3 800c0dc: e08a b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c0de: 4b47 ldr r3, [pc, #284] @ (800c1fc ) 800c0e0: 681b ldr r3, [r3, #0] 800c0e2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c0e6: 2b00 cmp r3, #0 800c0e8: d0f0 beq.n 800c0cc 800c0ea: e082 b.n 800c1f2 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800c0ec: 4b43 ldr r3, [pc, #268] @ (800c1fc ) 800c0ee: 681b ldr r3, [r3, #0] 800c0f0: 4a42 ldr r2, [pc, #264] @ (800c1fc ) 800c0f2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000 800c0f6: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c0f8: f7f9 fe94 bl 8005e24 800c0fc: 6278 str r0, [r7, #36] @ 0x24 /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c0fe: e008 b.n 800c112 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800c100: f7f9 fe90 bl 8005e24 800c104: 4602 mov r2, r0 800c106: 6a7b ldr r3, [r7, #36] @ 0x24 800c108: 1ad3 subs r3, r2, r3 800c10a: 2b02 cmp r3, #2 800c10c: d901 bls.n 800c112 { return HAL_TIMEOUT; 800c10e: 2303 movs r3, #3 800c110: e070 b.n 800c1f4 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) 800c112: 4b3a ldr r3, [pc, #232] @ (800c1fc ) 800c114: 681b ldr r3, [r3, #0] 800c116: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c11a: 2b00 cmp r3, #0 800c11c: d1f0 bne.n 800c100 800c11e: e068 b.n 800c1f2 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; 800c120: 4b36 ldr r3, [pc, #216] @ (800c1fc ) 800c122: 6a9b ldr r3, [r3, #40] @ 0x28 800c124: 613b str r3, [r7, #16] temp2_pllckcfg = RCC->PLL1DIVR; 800c126: 4b35 ldr r3, [pc, #212] @ (800c1fc ) 800c128: 6b1b ldr r3, [r3, #48] @ 0x30 800c12a: 60fb str r3, [r7, #12] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800c12c: 687b ldr r3, [r7, #4] 800c12e: 6a5b ldr r3, [r3, #36] @ 0x24 800c130: 2b01 cmp r3, #1 800c132: d031 beq.n 800c198 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800c134: 693b ldr r3, [r7, #16] 800c136: f003 0203 and.w r2, r3, #3 800c13a: 687b ldr r3, [r7, #4] 800c13c: 6a9b ldr r3, [r3, #40] @ 0x28 if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 800c13e: 429a cmp r2, r3 800c140: d12a bne.n 800c198 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800c142: 693b ldr r3, [r7, #16] 800c144: 091b lsrs r3, r3, #4 800c146: f003 023f and.w r2, r3, #63 @ 0x3f 800c14a: 687b ldr r3, [r7, #4] 800c14c: 6adb ldr r3, [r3, #44] @ 0x2c (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 800c14e: 429a cmp r2, r3 800c150: d122 bne.n 800c198 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800c152: 68fb ldr r3, [r7, #12] 800c154: f3c3 0208 ubfx r2, r3, #0, #9 800c158: 687b ldr r3, [r7, #4] 800c15a: 6b1b ldr r3, [r3, #48] @ 0x30 800c15c: 3b01 subs r3, #1 ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || 800c15e: 429a cmp r2, r3 800c160: d11a bne.n 800c198 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800c162: 68fb ldr r3, [r7, #12] 800c164: 0a5b lsrs r3, r3, #9 800c166: f003 027f and.w r2, r3, #127 @ 0x7f 800c16a: 687b ldr r3, [r7, #4] 800c16c: 6b5b ldr r3, [r3, #52] @ 0x34 800c16e: 3b01 subs r3, #1 (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || 800c170: 429a cmp r2, r3 800c172: d111 bne.n 800c198 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800c174: 68fb ldr r3, [r7, #12] 800c176: 0c1b lsrs r3, r3, #16 800c178: f003 027f and.w r2, r3, #127 @ 0x7f 800c17c: 687b ldr r3, [r7, #4] 800c17e: 6b9b ldr r3, [r3, #56] @ 0x38 800c180: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || 800c182: 429a cmp r2, r3 800c184: d108 bne.n 800c198 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) 800c186: 68fb ldr r3, [r7, #12] 800c188: 0e1b lsrs r3, r3, #24 800c18a: f003 027f and.w r2, r3, #127 @ 0x7f 800c18e: 687b ldr r3, [r7, #4] 800c190: 6bdb ldr r3, [r3, #60] @ 0x3c 800c192: 3b01 subs r3, #1 ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || 800c194: 429a cmp r2, r3 800c196: d001 beq.n 800c19c { return HAL_ERROR; 800c198: 2301 movs r3, #1 800c19a: e02b b.n 800c1f4 } else { /* Check if only fractional part needs to be updated */ temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); 800c19c: 4b17 ldr r3, [pc, #92] @ (800c1fc ) 800c19e: 6b5b ldr r3, [r3, #52] @ 0x34 800c1a0: 08db lsrs r3, r3, #3 800c1a2: f3c3 030c ubfx r3, r3, #0, #13 800c1a6: 613b str r3, [r7, #16] if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) 800c1a8: 687b ldr r3, [r7, #4] 800c1aa: 6c9b ldr r3, [r3, #72] @ 0x48 800c1ac: 693a ldr r2, [r7, #16] 800c1ae: 429a cmp r2, r3 800c1b0: d01f beq.n 800c1f2 { assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); /* Disable PLL1FRACEN */ __HAL_RCC_PLLFRACN_DISABLE(); 800c1b2: 4b12 ldr r3, [pc, #72] @ (800c1fc ) 800c1b4: 6adb ldr r3, [r3, #44] @ 0x2c 800c1b6: 4a11 ldr r2, [pc, #68] @ (800c1fc ) 800c1b8: f023 0301 bic.w r3, r3, #1 800c1bc: 62d3 str r3, [r2, #44] @ 0x2c /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c1be: f7f9 fe31 bl 8005e24 800c1c2: 6278 str r0, [r7, #36] @ 0x24 /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) 800c1c4: bf00 nop 800c1c6: f7f9 fe2d bl 8005e24 800c1ca: 4602 mov r2, r0 800c1cc: 6a7b ldr r3, [r7, #36] @ 0x24 800c1ce: 4293 cmp r3, r2 800c1d0: d0f9 beq.n 800c1c6 { } /* Configure PLL1 PLL1FRACN */ __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); 800c1d2: 4b0a ldr r3, [pc, #40] @ (800c1fc ) 800c1d4: 6b5a ldr r2, [r3, #52] @ 0x34 800c1d6: 4b0a ldr r3, [pc, #40] @ (800c200 ) 800c1d8: 4013 ands r3, r2 800c1da: 687a ldr r2, [r7, #4] 800c1dc: 6c92 ldr r2, [r2, #72] @ 0x48 800c1de: 00d2 lsls r2, r2, #3 800c1e0: 4906 ldr r1, [pc, #24] @ (800c1fc ) 800c1e2: 4313 orrs r3, r2 800c1e4: 634b str r3, [r1, #52] @ 0x34 /* Enable PLL1FRACEN to latch new value. */ __HAL_RCC_PLLFRACN_ENABLE(); 800c1e6: 4b05 ldr r3, [pc, #20] @ (800c1fc ) 800c1e8: 6adb ldr r3, [r3, #44] @ 0x2c 800c1ea: 4a04 ldr r2, [pc, #16] @ (800c1fc ) 800c1ec: f043 0301 orr.w r3, r3, #1 800c1f0: 62d3 str r3, [r2, #44] @ 0x2c } } } } return HAL_OK; 800c1f2: 2300 movs r3, #0 } 800c1f4: 4618 mov r0, r3 800c1f6: 3730 adds r7, #48 @ 0x30 800c1f8: 46bd mov sp, r7 800c1fa: bd80 pop {r7, pc} 800c1fc: 58024400 .word 0x58024400 800c200: ffff0007 .word 0xffff0007 0800c204 : * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800c204: b580 push {r7, lr} 800c206: b086 sub sp, #24 800c208: af00 add r7, sp, #0 800c20a: 6078 str r0, [r7, #4] 800c20c: 6039 str r1, [r7, #0] HAL_StatusTypeDef halstatus; uint32_t tickstart; uint32_t common_system_clock; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800c20e: 687b ldr r3, [r7, #4] 800c210: 2b00 cmp r3, #0 800c212: d101 bne.n 800c218 { return HAL_ERROR; 800c214: 2301 movs r3, #1 800c216: e19c b.n 800c552 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 800c218: 4b8a ldr r3, [pc, #552] @ (800c444 ) 800c21a: 681b ldr r3, [r3, #0] 800c21c: f003 030f and.w r3, r3, #15 800c220: 683a ldr r2, [r7, #0] 800c222: 429a cmp r2, r3 800c224: d910 bls.n 800c248 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c226: 4b87 ldr r3, [pc, #540] @ (800c444 ) 800c228: 681b ldr r3, [r3, #0] 800c22a: f023 020f bic.w r2, r3, #15 800c22e: 4985 ldr r1, [pc, #532] @ (800c444 ) 800c230: 683b ldr r3, [r7, #0] 800c232: 4313 orrs r3, r2 800c234: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c236: 4b83 ldr r3, [pc, #524] @ (800c444 ) 800c238: 681b ldr r3, [r3, #0] 800c23a: f003 030f and.w r3, r3, #15 800c23e: 683a ldr r2, [r7, #0] 800c240: 429a cmp r2, r3 800c242: d001 beq.n 800c248 { return HAL_ERROR; 800c244: 2301 movs r3, #1 800c246: e184 b.n 800c552 } /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c248: 687b ldr r3, [r7, #4] 800c24a: 681b ldr r3, [r3, #0] 800c24c: f003 0304 and.w r3, r3, #4 800c250: 2b00 cmp r3, #0 800c252: d010 beq.n 800c276 { #if defined (RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c254: 687b ldr r3, [r7, #4] 800c256: 691a ldr r2, [r3, #16] 800c258: 4b7b ldr r3, [pc, #492] @ (800c448 ) 800c25a: 699b ldr r3, [r3, #24] 800c25c: f003 0370 and.w r3, r3, #112 @ 0x70 800c260: 429a cmp r2, r3 800c262: d908 bls.n 800c276 { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c264: 4b78 ldr r3, [pc, #480] @ (800c448 ) 800c266: 699b ldr r3, [r3, #24] 800c268: f023 0270 bic.w r2, r3, #112 @ 0x70 800c26c: 687b ldr r3, [r7, #4] 800c26e: 691b ldr r3, [r3, #16] 800c270: 4975 ldr r1, [pc, #468] @ (800c448 ) 800c272: 4313 orrs r3, r2 800c274: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c276: 687b ldr r3, [r7, #4] 800c278: 681b ldr r3, [r3, #0] 800c27a: f003 0308 and.w r3, r3, #8 800c27e: 2b00 cmp r3, #0 800c280: d010 beq.n 800c2a4 { #if defined (RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c282: 687b ldr r3, [r7, #4] 800c284: 695a ldr r2, [r3, #20] 800c286: 4b70 ldr r3, [pc, #448] @ (800c448 ) 800c288: 69db ldr r3, [r3, #28] 800c28a: f003 0370 and.w r3, r3, #112 @ 0x70 800c28e: 429a cmp r2, r3 800c290: d908 bls.n 800c2a4 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c292: 4b6d ldr r3, [pc, #436] @ (800c448 ) 800c294: 69db ldr r3, [r3, #28] 800c296: f023 0270 bic.w r2, r3, #112 @ 0x70 800c29a: 687b ldr r3, [r7, #4] 800c29c: 695b ldr r3, [r3, #20] 800c29e: 496a ldr r1, [pc, #424] @ (800c448 ) 800c2a0: 4313 orrs r3, r2 800c2a2: 61cb str r3, [r1, #28] MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c2a4: 687b ldr r3, [r7, #4] 800c2a6: 681b ldr r3, [r3, #0] 800c2a8: f003 0310 and.w r3, r3, #16 800c2ac: 2b00 cmp r3, #0 800c2ae: d010 beq.n 800c2d2 { #if defined(RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c2b0: 687b ldr r3, [r7, #4] 800c2b2: 699a ldr r2, [r3, #24] 800c2b4: 4b64 ldr r3, [pc, #400] @ (800c448 ) 800c2b6: 69db ldr r3, [r3, #28] 800c2b8: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c2bc: 429a cmp r2, r3 800c2be: d908 bls.n 800c2d2 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c2c0: 4b61 ldr r3, [pc, #388] @ (800c448 ) 800c2c2: 69db ldr r3, [r3, #28] 800c2c4: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c2c8: 687b ldr r3, [r7, #4] 800c2ca: 699b ldr r3, [r3, #24] 800c2cc: 495e ldr r1, [pc, #376] @ (800c448 ) 800c2ce: 4313 orrs r3, r2 800c2d0: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c2d2: 687b ldr r3, [r7, #4] 800c2d4: 681b ldr r3, [r3, #0] 800c2d6: f003 0320 and.w r3, r3, #32 800c2da: 2b00 cmp r3, #0 800c2dc: d010 beq.n 800c300 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c2de: 687b ldr r3, [r7, #4] 800c2e0: 69da ldr r2, [r3, #28] 800c2e2: 4b59 ldr r3, [pc, #356] @ (800c448 ) 800c2e4: 6a1b ldr r3, [r3, #32] 800c2e6: f003 0370 and.w r3, r3, #112 @ 0x70 800c2ea: 429a cmp r2, r3 800c2ec: d908 bls.n 800c300 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c2ee: 4b56 ldr r3, [pc, #344] @ (800c448 ) 800c2f0: 6a1b ldr r3, [r3, #32] 800c2f2: f023 0270 bic.w r2, r3, #112 @ 0x70 800c2f6: 687b ldr r3, [r7, #4] 800c2f8: 69db ldr r3, [r3, #28] 800c2fa: 4953 ldr r1, [pc, #332] @ (800c448 ) 800c2fc: 4313 orrs r3, r2 800c2fe: 620b str r3, [r1, #32] } #endif } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c300: 687b ldr r3, [r7, #4] 800c302: 681b ldr r3, [r3, #0] 800c304: f003 0302 and.w r3, r3, #2 800c308: 2b00 cmp r3, #0 800c30a: d010 beq.n 800c32e { #if defined (RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c30c: 687b ldr r3, [r7, #4] 800c30e: 68da ldr r2, [r3, #12] 800c310: 4b4d ldr r3, [pc, #308] @ (800c448 ) 800c312: 699b ldr r3, [r3, #24] 800c314: f003 030f and.w r3, r3, #15 800c318: 429a cmp r2, r3 800c31a: d908 bls.n 800c32e { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c31c: 4b4a ldr r3, [pc, #296] @ (800c448 ) 800c31e: 699b ldr r3, [r3, #24] 800c320: f023 020f bic.w r2, r3, #15 800c324: 687b ldr r3, [r7, #4] 800c326: 68db ldr r3, [r3, #12] 800c328: 4947 ldr r1, [pc, #284] @ (800c448 ) 800c32a: 4313 orrs r3, r2 800c32c: 618b str r3, [r1, #24] } #endif } /*------------------------- SYSCLK Configuration -------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 800c32e: 687b ldr r3, [r7, #4] 800c330: 681b ldr r3, [r3, #0] 800c332: f003 0301 and.w r3, r3, #1 800c336: 2b00 cmp r3, #0 800c338: d055 beq.n 800c3e6 { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); 800c33a: 4b43 ldr r3, [pc, #268] @ (800c448 ) 800c33c: 699b ldr r3, [r3, #24] 800c33e: f423 6270 bic.w r2, r3, #3840 @ 0xf00 800c342: 687b ldr r3, [r7, #4] 800c344: 689b ldr r3, [r3, #8] 800c346: 4940 ldr r1, [pc, #256] @ (800c448 ) 800c348: 4313 orrs r3, r2 800c34a: 618b str r3, [r1, #24] #else MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 800c34c: 687b ldr r3, [r7, #4] 800c34e: 685b ldr r3, [r3, #4] 800c350: 2b02 cmp r3, #2 800c352: d107 bne.n 800c364 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) 800c354: 4b3c ldr r3, [pc, #240] @ (800c448 ) 800c356: 681b ldr r3, [r3, #0] 800c358: f403 3300 and.w r3, r3, #131072 @ 0x20000 800c35c: 2b00 cmp r3, #0 800c35e: d121 bne.n 800c3a4 { return HAL_ERROR; 800c360: 2301 movs r3, #1 800c362: e0f6 b.n 800c552 } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 800c364: 687b ldr r3, [r7, #4] 800c366: 685b ldr r3, [r3, #4] 800c368: 2b03 cmp r3, #3 800c36a: d107 bne.n 800c37c { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) 800c36c: 4b36 ldr r3, [pc, #216] @ (800c448 ) 800c36e: 681b ldr r3, [r3, #0] 800c370: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800c374: 2b00 cmp r3, #0 800c376: d115 bne.n 800c3a4 { return HAL_ERROR; 800c378: 2301 movs r3, #1 800c37a: e0ea b.n 800c552 } } /* CSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) 800c37c: 687b ldr r3, [r7, #4] 800c37e: 685b ldr r3, [r3, #4] 800c380: 2b01 cmp r3, #1 800c382: d107 bne.n 800c394 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) 800c384: 4b30 ldr r3, [pc, #192] @ (800c448 ) 800c386: 681b ldr r3, [r3, #0] 800c388: f403 7380 and.w r3, r3, #256 @ 0x100 800c38c: 2b00 cmp r3, #0 800c38e: d109 bne.n 800c3a4 { return HAL_ERROR; 800c390: 2301 movs r3, #1 800c392: e0de b.n 800c552 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) 800c394: 4b2c ldr r3, [pc, #176] @ (800c448 ) 800c396: 681b ldr r3, [r3, #0] 800c398: f003 0304 and.w r3, r3, #4 800c39c: 2b00 cmp r3, #0 800c39e: d101 bne.n 800c3a4 { return HAL_ERROR; 800c3a0: 2301 movs r3, #1 800c3a2: e0d6 b.n 800c552 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800c3a4: 4b28 ldr r3, [pc, #160] @ (800c448 ) 800c3a6: 691b ldr r3, [r3, #16] 800c3a8: f023 0207 bic.w r2, r3, #7 800c3ac: 687b ldr r3, [r7, #4] 800c3ae: 685b ldr r3, [r3, #4] 800c3b0: 4925 ldr r1, [pc, #148] @ (800c448 ) 800c3b2: 4313 orrs r3, r2 800c3b4: 610b str r3, [r1, #16] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800c3b6: f7f9 fd35 bl 8005e24 800c3ba: 6178 str r0, [r7, #20] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c3bc: e00a b.n 800c3d4 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800c3be: f7f9 fd31 bl 8005e24 800c3c2: 4602 mov r2, r0 800c3c4: 697b ldr r3, [r7, #20] 800c3c6: 1ad3 subs r3, r2, r3 800c3c8: f241 3288 movw r2, #5000 @ 0x1388 800c3cc: 4293 cmp r3, r2 800c3ce: d901 bls.n 800c3d4 { return HAL_TIMEOUT; 800c3d0: 2303 movs r3, #3 800c3d2: e0be b.n 800c552 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800c3d4: 4b1c ldr r3, [pc, #112] @ (800c448 ) 800c3d6: 691b ldr r3, [r3, #16] 800c3d8: f003 0238 and.w r2, r3, #56 @ 0x38 800c3dc: 687b ldr r3, [r7, #4] 800c3de: 685b ldr r3, [r3, #4] 800c3e0: 00db lsls r3, r3, #3 800c3e2: 429a cmp r2, r3 800c3e4: d1eb bne.n 800c3be } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800c3e6: 687b ldr r3, [r7, #4] 800c3e8: 681b ldr r3, [r3, #0] 800c3ea: f003 0302 and.w r3, r3, #2 800c3ee: 2b00 cmp r3, #0 800c3f0: d010 beq.n 800c414 { #if defined(RCC_D1CFGR_HPRE) if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) 800c3f2: 687b ldr r3, [r7, #4] 800c3f4: 68da ldr r2, [r3, #12] 800c3f6: 4b14 ldr r3, [pc, #80] @ (800c448 ) 800c3f8: 699b ldr r3, [r3, #24] 800c3fa: f003 030f and.w r3, r3, #15 800c3fe: 429a cmp r2, r3 800c400: d208 bcs.n 800c414 { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 800c402: 4b11 ldr r3, [pc, #68] @ (800c448 ) 800c404: 699b ldr r3, [r3, #24] 800c406: f023 020f bic.w r2, r3, #15 800c40a: 687b ldr r3, [r7, #4] 800c40c: 68db ldr r3, [r3, #12] 800c40e: 490e ldr r1, [pc, #56] @ (800c448 ) 800c410: 4313 orrs r3, r2 800c412: 618b str r3, [r1, #24] } #endif } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 800c414: 4b0b ldr r3, [pc, #44] @ (800c444 ) 800c416: 681b ldr r3, [r3, #0] 800c418: f003 030f and.w r3, r3, #15 800c41c: 683a ldr r2, [r7, #0] 800c41e: 429a cmp r2, r3 800c420: d214 bcs.n 800c44c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800c422: 4b08 ldr r3, [pc, #32] @ (800c444 ) 800c424: 681b ldr r3, [r3, #0] 800c426: f023 020f bic.w r2, r3, #15 800c42a: 4906 ldr r1, [pc, #24] @ (800c444 ) 800c42c: 683b ldr r3, [r7, #0] 800c42e: 4313 orrs r3, r2 800c430: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800c432: 4b04 ldr r3, [pc, #16] @ (800c444 ) 800c434: 681b ldr r3, [r3, #0] 800c436: f003 030f and.w r3, r3, #15 800c43a: 683a ldr r2, [r7, #0] 800c43c: 429a cmp r2, r3 800c43e: d005 beq.n 800c44c { return HAL_ERROR; 800c440: 2301 movs r3, #1 800c442: e086 b.n 800c552 800c444: 52002000 .word 0x52002000 800c448: 58024400 .word 0x58024400 } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) 800c44c: 687b ldr r3, [r7, #4] 800c44e: 681b ldr r3, [r3, #0] 800c450: f003 0304 and.w r3, r3, #4 800c454: 2b00 cmp r3, #0 800c456: d010 beq.n 800c47a { #if defined(RCC_D1CFGR_D1PPRE) if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) 800c458: 687b ldr r3, [r7, #4] 800c45a: 691a ldr r2, [r3, #16] 800c45c: 4b3f ldr r3, [pc, #252] @ (800c55c ) 800c45e: 699b ldr r3, [r3, #24] 800c460: f003 0370 and.w r3, r3, #112 @ 0x70 800c464: 429a cmp r2, r3 800c466: d208 bcs.n 800c47a { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); 800c468: 4b3c ldr r3, [pc, #240] @ (800c55c ) 800c46a: 699b ldr r3, [r3, #24] 800c46c: f023 0270 bic.w r2, r3, #112 @ 0x70 800c470: 687b ldr r3, [r7, #4] 800c472: 691b ldr r3, [r3, #16] 800c474: 4939 ldr r1, [pc, #228] @ (800c55c ) 800c476: 4313 orrs r3, r2 800c478: 618b str r3, [r1, #24] } #endif } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 800c47a: 687b ldr r3, [r7, #4] 800c47c: 681b ldr r3, [r3, #0] 800c47e: f003 0308 and.w r3, r3, #8 800c482: 2b00 cmp r3, #0 800c484: d010 beq.n 800c4a8 { #if defined(RCC_D2CFGR_D2PPRE1) if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) 800c486: 687b ldr r3, [r7, #4] 800c488: 695a ldr r2, [r3, #20] 800c48a: 4b34 ldr r3, [pc, #208] @ (800c55c ) 800c48c: 69db ldr r3, [r3, #28] 800c48e: f003 0370 and.w r3, r3, #112 @ 0x70 800c492: 429a cmp r2, r3 800c494: d208 bcs.n 800c4a8 { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); 800c496: 4b31 ldr r3, [pc, #196] @ (800c55c ) 800c498: 69db ldr r3, [r3, #28] 800c49a: f023 0270 bic.w r2, r3, #112 @ 0x70 800c49e: 687b ldr r3, [r7, #4] 800c4a0: 695b ldr r3, [r3, #20] 800c4a2: 492e ldr r1, [pc, #184] @ (800c55c ) 800c4a4: 4313 orrs r3, r2 800c4a6: 61cb str r3, [r1, #28] } #endif } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 800c4a8: 687b ldr r3, [r7, #4] 800c4aa: 681b ldr r3, [r3, #0] 800c4ac: f003 0310 and.w r3, r3, #16 800c4b0: 2b00 cmp r3, #0 800c4b2: d010 beq.n 800c4d6 { #if defined (RCC_D2CFGR_D2PPRE2) if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) 800c4b4: 687b ldr r3, [r7, #4] 800c4b6: 699a ldr r2, [r3, #24] 800c4b8: 4b28 ldr r3, [pc, #160] @ (800c55c ) 800c4ba: 69db ldr r3, [r3, #28] 800c4bc: f403 63e0 and.w r3, r3, #1792 @ 0x700 800c4c0: 429a cmp r2, r3 800c4c2: d208 bcs.n 800c4d6 { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); 800c4c4: 4b25 ldr r3, [pc, #148] @ (800c55c ) 800c4c6: 69db ldr r3, [r3, #28] 800c4c8: f423 62e0 bic.w r2, r3, #1792 @ 0x700 800c4cc: 687b ldr r3, [r7, #4] 800c4ce: 699b ldr r3, [r3, #24] 800c4d0: 4922 ldr r1, [pc, #136] @ (800c55c ) 800c4d2: 4313 orrs r3, r2 800c4d4: 61cb str r3, [r1, #28] } #endif } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) 800c4d6: 687b ldr r3, [r7, #4] 800c4d8: 681b ldr r3, [r3, #0] 800c4da: f003 0320 and.w r3, r3, #32 800c4de: 2b00 cmp r3, #0 800c4e0: d010 beq.n 800c504 { #if defined(RCC_D3CFGR_D3PPRE) if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) 800c4e2: 687b ldr r3, [r7, #4] 800c4e4: 69da ldr r2, [r3, #28] 800c4e6: 4b1d ldr r3, [pc, #116] @ (800c55c ) 800c4e8: 6a1b ldr r3, [r3, #32] 800c4ea: f003 0370 and.w r3, r3, #112 @ 0x70 800c4ee: 429a cmp r2, r3 800c4f0: d208 bcs.n 800c504 { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); 800c4f2: 4b1a ldr r3, [pc, #104] @ (800c55c ) 800c4f4: 6a1b ldr r3, [r3, #32] 800c4f6: f023 0270 bic.w r2, r3, #112 @ 0x70 800c4fa: 687b ldr r3, [r7, #4] 800c4fc: 69db ldr r3, [r3, #28] 800c4fe: 4917 ldr r1, [pc, #92] @ (800c55c ) 800c500: 4313 orrs r3, r2 800c502: 620b str r3, [r1, #32] #endif } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); 800c504: f000 f834 bl 800c570 800c508: 4602 mov r2, r0 800c50a: 4b14 ldr r3, [pc, #80] @ (800c55c ) 800c50c: 699b ldr r3, [r3, #24] 800c50e: 0a1b lsrs r3, r3, #8 800c510: f003 030f and.w r3, r3, #15 800c514: 4912 ldr r1, [pc, #72] @ (800c560 ) 800c516: 5ccb ldrb r3, [r1, r3] 800c518: f003 031f and.w r3, r3, #31 800c51c: fa22 f303 lsr.w r3, r2, r3 800c520: 613b str r3, [r7, #16] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c522: 4b0e ldr r3, [pc, #56] @ (800c55c ) 800c524: 699b ldr r3, [r3, #24] 800c526: f003 030f and.w r3, r3, #15 800c52a: 4a0d ldr r2, [pc, #52] @ (800c560 ) 800c52c: 5cd3 ldrb r3, [r2, r3] 800c52e: f003 031f and.w r3, r3, #31 800c532: 693a ldr r2, [r7, #16] 800c534: fa22 f303 lsr.w r3, r2, r3 800c538: 4a0a ldr r2, [pc, #40] @ (800c564 ) 800c53a: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c53c: 4a0a ldr r2, [pc, #40] @ (800c568 ) 800c53e: 693b ldr r3, [r7, #16] 800c540: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ halstatus = HAL_InitTick(uwTickPrio); 800c542: 4b0a ldr r3, [pc, #40] @ (800c56c ) 800c544: 681b ldr r3, [r3, #0] 800c546: 4618 mov r0, r3 800c548: f7f8 f89c bl 8004684 800c54c: 4603 mov r3, r0 800c54e: 73fb strb r3, [r7, #15] return halstatus; 800c550: 7bfb ldrb r3, [r7, #15] } 800c552: 4618 mov r0, r3 800c554: 3718 adds r7, #24 800c556: 46bd mov sp, r7 800c558: bd80 pop {r7, pc} 800c55a: bf00 nop 800c55c: 58024400 .word 0x58024400 800c560: 0801870c .word 0x0801870c 800c564: 24000038 .word 0x24000038 800c568: 24000034 .word 0x24000034 800c56c: 2400003c .word 0x2400003c 0800c570 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 800c570: b480 push {r7} 800c572: b089 sub sp, #36 @ 0x24 800c574: af00 add r7, sp, #0 float_t fracn1, pllvco; uint32_t sysclockfreq; /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 800c576: 4bb3 ldr r3, [pc, #716] @ (800c844 ) 800c578: 691b ldr r3, [r3, #16] 800c57a: f003 0338 and.w r3, r3, #56 @ 0x38 800c57e: 2b18 cmp r3, #24 800c580: f200 8155 bhi.w 800c82e 800c584: a201 add r2, pc, #4 @ (adr r2, 800c58c ) 800c586: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800c58a: bf00 nop 800c58c: 0800c5f1 .word 0x0800c5f1 800c590: 0800c82f .word 0x0800c82f 800c594: 0800c82f .word 0x0800c82f 800c598: 0800c82f .word 0x0800c82f 800c59c: 0800c82f .word 0x0800c82f 800c5a0: 0800c82f .word 0x0800c82f 800c5a4: 0800c82f .word 0x0800c82f 800c5a8: 0800c82f .word 0x0800c82f 800c5ac: 0800c617 .word 0x0800c617 800c5b0: 0800c82f .word 0x0800c82f 800c5b4: 0800c82f .word 0x0800c82f 800c5b8: 0800c82f .word 0x0800c82f 800c5bc: 0800c82f .word 0x0800c82f 800c5c0: 0800c82f .word 0x0800c82f 800c5c4: 0800c82f .word 0x0800c82f 800c5c8: 0800c82f .word 0x0800c82f 800c5cc: 0800c61d .word 0x0800c61d 800c5d0: 0800c82f .word 0x0800c82f 800c5d4: 0800c82f .word 0x0800c82f 800c5d8: 0800c82f .word 0x0800c82f 800c5dc: 0800c82f .word 0x0800c82f 800c5e0: 0800c82f .word 0x0800c82f 800c5e4: 0800c82f .word 0x0800c82f 800c5e8: 0800c82f .word 0x0800c82f 800c5ec: 0800c623 .word 0x0800c623 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c5f0: 4b94 ldr r3, [pc, #592] @ (800c844 ) 800c5f2: 681b ldr r3, [r3, #0] 800c5f4: f003 0320 and.w r3, r3, #32 800c5f8: 2b00 cmp r3, #0 800c5fa: d009 beq.n 800c610 { sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c5fc: 4b91 ldr r3, [pc, #580] @ (800c844 ) 800c5fe: 681b ldr r3, [r3, #0] 800c600: 08db lsrs r3, r3, #3 800c602: f003 0303 and.w r3, r3, #3 800c606: 4a90 ldr r2, [pc, #576] @ (800c848 ) 800c608: fa22 f303 lsr.w r3, r2, r3 800c60c: 61bb str r3, [r7, #24] else { sysclockfreq = (uint32_t) HSI_VALUE; } break; 800c60e: e111 b.n 800c834 sysclockfreq = (uint32_t) HSI_VALUE; 800c610: 4b8d ldr r3, [pc, #564] @ (800c848 ) 800c612: 61bb str r3, [r7, #24] break; 800c614: e10e b.n 800c834 case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ sysclockfreq = CSI_VALUE; 800c616: 4b8d ldr r3, [pc, #564] @ (800c84c ) 800c618: 61bb str r3, [r7, #24] break; 800c61a: e10b b.n 800c834 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 800c61c: 4b8c ldr r3, [pc, #560] @ (800c850 ) 800c61e: 61bb str r3, [r7, #24] break; 800c620: e108 b.n 800c834 case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800c622: 4b88 ldr r3, [pc, #544] @ (800c844 ) 800c624: 6a9b ldr r3, [r3, #40] @ 0x28 800c626: f003 0303 and.w r3, r3, #3 800c62a: 617b str r3, [r7, #20] pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; 800c62c: 4b85 ldr r3, [pc, #532] @ (800c844 ) 800c62e: 6a9b ldr r3, [r3, #40] @ 0x28 800c630: 091b lsrs r3, r3, #4 800c632: f003 033f and.w r3, r3, #63 @ 0x3f 800c636: 613b str r3, [r7, #16] pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); 800c638: 4b82 ldr r3, [pc, #520] @ (800c844 ) 800c63a: 6adb ldr r3, [r3, #44] @ 0x2c 800c63c: f003 0301 and.w r3, r3, #1 800c640: 60fb str r3, [r7, #12] fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800c642: 4b80 ldr r3, [pc, #512] @ (800c844 ) 800c644: 6b5b ldr r3, [r3, #52] @ 0x34 800c646: 08db lsrs r3, r3, #3 800c648: f3c3 030c ubfx r3, r3, #0, #13 800c64c: 68fa ldr r2, [r7, #12] 800c64e: fb02 f303 mul.w r3, r2, r3 800c652: ee07 3a90 vmov s15, r3 800c656: eef8 7a67 vcvt.f32.u32 s15, s15 800c65a: edc7 7a02 vstr s15, [r7, #8] if (pllm != 0U) 800c65e: 693b ldr r3, [r7, #16] 800c660: 2b00 cmp r3, #0 800c662: f000 80e1 beq.w 800c828 800c666: 697b ldr r3, [r7, #20] 800c668: 2b02 cmp r3, #2 800c66a: f000 8083 beq.w 800c774 800c66e: 697b ldr r3, [r7, #20] 800c670: 2b02 cmp r3, #2 800c672: f200 80a1 bhi.w 800c7b8 800c676: 697b ldr r3, [r7, #20] 800c678: 2b00 cmp r3, #0 800c67a: d003 beq.n 800c684 800c67c: 697b ldr r3, [r7, #20] 800c67e: 2b01 cmp r3, #1 800c680: d056 beq.n 800c730 800c682: e099 b.n 800c7b8 { switch (pllsource) { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800c684: 4b6f ldr r3, [pc, #444] @ (800c844 ) 800c686: 681b ldr r3, [r3, #0] 800c688: f003 0320 and.w r3, r3, #32 800c68c: 2b00 cmp r3, #0 800c68e: d02d beq.n 800c6ec { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800c690: 4b6c ldr r3, [pc, #432] @ (800c844 ) 800c692: 681b ldr r3, [r3, #0] 800c694: 08db lsrs r3, r3, #3 800c696: f003 0303 and.w r3, r3, #3 800c69a: 4a6b ldr r2, [pc, #428] @ (800c848 ) 800c69c: fa22 f303 lsr.w r3, r2, r3 800c6a0: 607b str r3, [r7, #4] pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c6a2: 687b ldr r3, [r7, #4] 800c6a4: ee07 3a90 vmov s15, r3 800c6a8: eef8 6a67 vcvt.f32.u32 s13, s15 800c6ac: 693b ldr r3, [r7, #16] 800c6ae: ee07 3a90 vmov s15, r3 800c6b2: eef8 7a67 vcvt.f32.u32 s15, s15 800c6b6: ee86 7aa7 vdiv.f32 s14, s13, s15 800c6ba: 4b62 ldr r3, [pc, #392] @ (800c844 ) 800c6bc: 6b1b ldr r3, [r3, #48] @ 0x30 800c6be: f3c3 0308 ubfx r3, r3, #0, #9 800c6c2: ee07 3a90 vmov s15, r3 800c6c6: eef8 6a67 vcvt.f32.u32 s13, s15 800c6ca: ed97 6a02 vldr s12, [r7, #8] 800c6ce: eddf 5a61 vldr s11, [pc, #388] @ 800c854 800c6d2: eec6 7a25 vdiv.f32 s15, s12, s11 800c6d6: ee76 7aa7 vadd.f32 s15, s13, s15 800c6da: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c6de: ee77 7aa6 vadd.f32 s15, s15, s13 800c6e2: ee67 7a27 vmul.f32 s15, s14, s15 800c6e6: edc7 7a07 vstr s15, [r7, #28] } else { pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800c6ea: e087 b.n 800c7fc pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c6ec: 693b ldr r3, [r7, #16] 800c6ee: ee07 3a90 vmov s15, r3 800c6f2: eef8 7a67 vcvt.f32.u32 s15, s15 800c6f6: eddf 6a58 vldr s13, [pc, #352] @ 800c858 800c6fa: ee86 7aa7 vdiv.f32 s14, s13, s15 800c6fe: 4b51 ldr r3, [pc, #324] @ (800c844 ) 800c700: 6b1b ldr r3, [r3, #48] @ 0x30 800c702: f3c3 0308 ubfx r3, r3, #0, #9 800c706: ee07 3a90 vmov s15, r3 800c70a: eef8 6a67 vcvt.f32.u32 s13, s15 800c70e: ed97 6a02 vldr s12, [r7, #8] 800c712: eddf 5a50 vldr s11, [pc, #320] @ 800c854 800c716: eec6 7a25 vdiv.f32 s15, s12, s11 800c71a: ee76 7aa7 vadd.f32 s15, s13, s15 800c71e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c722: ee77 7aa6 vadd.f32 s15, s15, s13 800c726: ee67 7a27 vmul.f32 s15, s14, s15 800c72a: edc7 7a07 vstr s15, [r7, #28] break; 800c72e: e065 b.n 800c7fc case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c730: 693b ldr r3, [r7, #16] 800c732: ee07 3a90 vmov s15, r3 800c736: eef8 7a67 vcvt.f32.u32 s15, s15 800c73a: eddf 6a48 vldr s13, [pc, #288] @ 800c85c 800c73e: ee86 7aa7 vdiv.f32 s14, s13, s15 800c742: 4b40 ldr r3, [pc, #256] @ (800c844 ) 800c744: 6b1b ldr r3, [r3, #48] @ 0x30 800c746: f3c3 0308 ubfx r3, r3, #0, #9 800c74a: ee07 3a90 vmov s15, r3 800c74e: eef8 6a67 vcvt.f32.u32 s13, s15 800c752: ed97 6a02 vldr s12, [r7, #8] 800c756: eddf 5a3f vldr s11, [pc, #252] @ 800c854 800c75a: eec6 7a25 vdiv.f32 s15, s12, s11 800c75e: ee76 7aa7 vadd.f32 s15, s13, s15 800c762: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c766: ee77 7aa6 vadd.f32 s15, s15, s13 800c76a: ee67 7a27 vmul.f32 s15, s14, s15 800c76e: edc7 7a07 vstr s15, [r7, #28] break; 800c772: e043 b.n 800c7fc case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c774: 693b ldr r3, [r7, #16] 800c776: ee07 3a90 vmov s15, r3 800c77a: eef8 7a67 vcvt.f32.u32 s15, s15 800c77e: eddf 6a38 vldr s13, [pc, #224] @ 800c860 800c782: ee86 7aa7 vdiv.f32 s14, s13, s15 800c786: 4b2f ldr r3, [pc, #188] @ (800c844 ) 800c788: 6b1b ldr r3, [r3, #48] @ 0x30 800c78a: f3c3 0308 ubfx r3, r3, #0, #9 800c78e: ee07 3a90 vmov s15, r3 800c792: eef8 6a67 vcvt.f32.u32 s13, s15 800c796: ed97 6a02 vldr s12, [r7, #8] 800c79a: eddf 5a2e vldr s11, [pc, #184] @ 800c854 800c79e: eec6 7a25 vdiv.f32 s15, s12, s11 800c7a2: ee76 7aa7 vadd.f32 s15, s13, s15 800c7a6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c7aa: ee77 7aa6 vadd.f32 s15, s15, s13 800c7ae: ee67 7a27 vmul.f32 s15, s14, s15 800c7b2: edc7 7a07 vstr s15, [r7, #28] break; 800c7b6: e021 b.n 800c7fc default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800c7b8: 693b ldr r3, [r7, #16] 800c7ba: ee07 3a90 vmov s15, r3 800c7be: eef8 7a67 vcvt.f32.u32 s15, s15 800c7c2: eddf 6a26 vldr s13, [pc, #152] @ 800c85c 800c7c6: ee86 7aa7 vdiv.f32 s14, s13, s15 800c7ca: 4b1e ldr r3, [pc, #120] @ (800c844 ) 800c7cc: 6b1b ldr r3, [r3, #48] @ 0x30 800c7ce: f3c3 0308 ubfx r3, r3, #0, #9 800c7d2: ee07 3a90 vmov s15, r3 800c7d6: eef8 6a67 vcvt.f32.u32 s13, s15 800c7da: ed97 6a02 vldr s12, [r7, #8] 800c7de: eddf 5a1d vldr s11, [pc, #116] @ 800c854 800c7e2: eec6 7a25 vdiv.f32 s15, s12, s11 800c7e6: ee76 7aa7 vadd.f32 s15, s13, s15 800c7ea: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800c7ee: ee77 7aa6 vadd.f32 s15, s15, s13 800c7f2: ee67 7a27 vmul.f32 s15, s14, s15 800c7f6: edc7 7a07 vstr s15, [r7, #28] break; 800c7fa: bf00 nop } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; 800c7fc: 4b11 ldr r3, [pc, #68] @ (800c844 ) 800c7fe: 6b1b ldr r3, [r3, #48] @ 0x30 800c800: 0a5b lsrs r3, r3, #9 800c802: f003 037f and.w r3, r3, #127 @ 0x7f 800c806: 3301 adds r3, #1 800c808: 603b str r3, [r7, #0] sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); 800c80a: 683b ldr r3, [r7, #0] 800c80c: ee07 3a90 vmov s15, r3 800c810: eeb8 7a67 vcvt.f32.u32 s14, s15 800c814: edd7 6a07 vldr s13, [r7, #28] 800c818: eec6 7a87 vdiv.f32 s15, s13, s14 800c81c: eefc 7ae7 vcvt.u32.f32 s15, s15 800c820: ee17 3a90 vmov r3, s15 800c824: 61bb str r3, [r7, #24] } else { sysclockfreq = 0U; } break; 800c826: e005 b.n 800c834 sysclockfreq = 0U; 800c828: 2300 movs r3, #0 800c82a: 61bb str r3, [r7, #24] break; 800c82c: e002 b.n 800c834 default: sysclockfreq = CSI_VALUE; 800c82e: 4b07 ldr r3, [pc, #28] @ (800c84c ) 800c830: 61bb str r3, [r7, #24] break; 800c832: bf00 nop } return sysclockfreq; 800c834: 69bb ldr r3, [r7, #24] } 800c836: 4618 mov r0, r3 800c838: 3724 adds r7, #36 @ 0x24 800c83a: 46bd mov sp, r7 800c83c: f85d 7b04 ldr.w r7, [sp], #4 800c840: 4770 bx lr 800c842: bf00 nop 800c844: 58024400 .word 0x58024400 800c848: 03d09000 .word 0x03d09000 800c84c: 003d0900 .word 0x003d0900 800c850: 017d7840 .word 0x017d7840 800c854: 46000000 .word 0x46000000 800c858: 4c742400 .word 0x4c742400 800c85c: 4a742400 .word 0x4a742400 800c860: 4bbebc20 .word 0x4bbebc20 0800c864 : * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 800c864: b580 push {r7, lr} 800c866: b082 sub sp, #8 800c868: af00 add r7, sp, #0 uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); 800c86a: f7ff fe81 bl 800c570 800c86e: 4602 mov r2, r0 800c870: 4b10 ldr r3, [pc, #64] @ (800c8b4 ) 800c872: 699b ldr r3, [r3, #24] 800c874: 0a1b lsrs r3, r3, #8 800c876: f003 030f and.w r3, r3, #15 800c87a: 490f ldr r1, [pc, #60] @ (800c8b8 ) 800c87c: 5ccb ldrb r3, [r1, r3] 800c87e: f003 031f and.w r3, r3, #31 800c882: fa22 f303 lsr.w r3, r2, r3 800c886: 607b str r3, [r7, #4] #else common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); 800c888: 4b0a ldr r3, [pc, #40] @ (800c8b4 ) 800c88a: 699b ldr r3, [r3, #24] 800c88c: f003 030f and.w r3, r3, #15 800c890: 4a09 ldr r2, [pc, #36] @ (800c8b8 ) 800c892: 5cd3 ldrb r3, [r2, r3] 800c894: f003 031f and.w r3, r3, #31 800c898: 687a ldr r2, [r7, #4] 800c89a: fa22 f303 lsr.w r3, r2, r3 800c89e: 4a07 ldr r2, [pc, #28] @ (800c8bc ) 800c8a0: 6013 str r3, [r2, #0] #endif #if defined(DUAL_CORE) && defined(CORE_CM4) SystemCoreClock = SystemD2Clock; #else SystemCoreClock = common_system_clock; 800c8a2: 4a07 ldr r2, [pc, #28] @ (800c8c0 ) 800c8a4: 687b ldr r3, [r7, #4] 800c8a6: 6013 str r3, [r2, #0] #endif /* DUAL_CORE && CORE_CM4 */ return SystemD2Clock; 800c8a8: 4b04 ldr r3, [pc, #16] @ (800c8bc ) 800c8aa: 681b ldr r3, [r3, #0] } 800c8ac: 4618 mov r0, r3 800c8ae: 3708 adds r7, #8 800c8b0: 46bd mov sp, r7 800c8b2: bd80 pop {r7, pc} 800c8b4: 58024400 .word 0x58024400 800c8b8: 0801870c .word 0x0801870c 800c8bc: 24000038 .word 0x24000038 800c8c0: 24000034 .word 0x24000034 0800c8c4 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800c8c4: b580 push {r7, lr} 800c8c6: af00 add r7, sp, #0 #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); 800c8c8: f7ff ffcc bl 800c864 800c8cc: 4602 mov r2, r0 800c8ce: 4b06 ldr r3, [pc, #24] @ (800c8e8 ) 800c8d0: 69db ldr r3, [r3, #28] 800c8d2: 091b lsrs r3, r3, #4 800c8d4: f003 0307 and.w r3, r3, #7 800c8d8: 4904 ldr r1, [pc, #16] @ (800c8ec ) 800c8da: 5ccb ldrb r3, [r1, r3] 800c8dc: f003 031f and.w r3, r3, #31 800c8e0: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } 800c8e4: 4618 mov r0, r3 800c8e6: bd80 pop {r7, pc} 800c8e8: 58024400 .word 0x58024400 800c8ec: 0801870c .word 0x0801870c 0800c8f0 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 800c8f0: b580 push {r7, lr} 800c8f2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); 800c8f4: f7ff ffb6 bl 800c864 800c8f8: 4602 mov r2, r0 800c8fa: 4b06 ldr r3, [pc, #24] @ (800c914 ) 800c8fc: 69db ldr r3, [r3, #28] 800c8fe: 0a1b lsrs r3, r3, #8 800c900: f003 0307 and.w r3, r3, #7 800c904: 4904 ldr r1, [pc, #16] @ (800c918 ) 800c906: 5ccb ldrb r3, [r1, r3] 800c908: f003 031f and.w r3, r3, #31 800c90c: fa22 f303 lsr.w r3, r2, r3 #else return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } 800c910: 4618 mov r0, r3 800c912: bd80 pop {r7, pc} 800c914: 58024400 .word 0x58024400 800c918: 0801870c .word 0x0801870c 0800c91c : * will be configured. * @param pFLatency: Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 800c91c: b480 push {r7} 800c91e: b083 sub sp, #12 800c920: af00 add r7, sp, #0 800c922: 6078 str r0, [r7, #4] 800c924: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | 800c926: 687b ldr r3, [r7, #4] 800c928: 223f movs r2, #63 @ 0x3f 800c92a: 601a str r2, [r3, #0] RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 800c92c: 4b1a ldr r3, [pc, #104] @ (800c998 ) 800c92e: 691b ldr r3, [r3, #16] 800c930: f003 0207 and.w r2, r3, #7 800c934: 687b ldr r3, [r7, #4] 800c936: 605a str r2, [r3, #4] #if defined(RCC_D1CFGR_D1CPRE) /* Get the SYSCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); 800c938: 4b17 ldr r3, [pc, #92] @ (800c998 ) 800c93a: 699b ldr r3, [r3, #24] 800c93c: f403 6270 and.w r2, r3, #3840 @ 0xf00 800c940: 687b ldr r3, [r7, #4] 800c942: 609a str r2, [r3, #8] /* Get the D1HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); 800c944: 4b14 ldr r3, [pc, #80] @ (800c998 ) 800c946: 699b ldr r3, [r3, #24] 800c948: f003 020f and.w r2, r3, #15 800c94c: 687b ldr r3, [r7, #4] 800c94e: 60da str r2, [r3, #12] /* Get the APB3 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); 800c950: 4b11 ldr r3, [pc, #68] @ (800c998 ) 800c952: 699b ldr r3, [r3, #24] 800c954: f003 0270 and.w r2, r3, #112 @ 0x70 800c958: 687b ldr r3, [r7, #4] 800c95a: 611a str r2, [r3, #16] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); 800c95c: 4b0e ldr r3, [pc, #56] @ (800c998 ) 800c95e: 69db ldr r3, [r3, #28] 800c960: f003 0270 and.w r2, r3, #112 @ 0x70 800c964: 687b ldr r3, [r7, #4] 800c966: 615a str r2, [r3, #20] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); 800c968: 4b0b ldr r3, [pc, #44] @ (800c998 ) 800c96a: 69db ldr r3, [r3, #28] 800c96c: f403 62e0 and.w r2, r3, #1792 @ 0x700 800c970: 687b ldr r3, [r7, #4] 800c972: 619a str r2, [r3, #24] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); 800c974: 4b08 ldr r3, [pc, #32] @ (800c998 ) 800c976: 6a1b ldr r3, [r3, #32] 800c978: f003 0270 and.w r2, r3, #112 @ 0x70 800c97c: 687b ldr r3, [r7, #4] 800c97e: 61da str r2, [r3, #28] /* Get the APB4 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); #endif /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 800c980: 4b06 ldr r3, [pc, #24] @ (800c99c ) 800c982: 681b ldr r3, [r3, #0] 800c984: f003 020f and.w r2, r3, #15 800c988: 683b ldr r3, [r7, #0] 800c98a: 601a str r2, [r3, #0] } 800c98c: bf00 nop 800c98e: 370c adds r7, #12 800c990: 46bd mov sp, r7 800c992: f85d 7b04 ldr.w r7, [sp], #4 800c996: 4770 bx lr 800c998: 58024400 .word 0x58024400 800c99c: 52002000 .word 0x52002000 0800c9a0 : * (*) : Available on some STM32H7 lines only. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800c9a0: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 800c9a4: b0c8 sub sp, #288 @ 0x120 800c9a6: af00 add r7, sp, #0 800c9a8: f8c7 010c str.w r0, [r7, #268] @ 0x10c uint32_t tmpreg; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 800c9ac: 2300 movs r3, #0 800c9ae: f887 311f strb.w r3, [r7, #287] @ 0x11f HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800c9b2: 2300 movs r3, #0 800c9b4: f887 311e strb.w r3, [r7, #286] @ 0x11e /*---------------------------- SPDIFRX configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) 800c9b8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9bc: e9d3 2300 ldrd r2, r3, [r3] 800c9c0: f002 6400 and.w r4, r2, #134217728 @ 0x8000000 800c9c4: 2500 movs r5, #0 800c9c6: ea54 0305 orrs.w r3, r4, r5 800c9ca: d049 beq.n 800ca60 { switch (PeriphClkInit->SpdifrxClockSelection) 800c9cc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800c9d0: 6e9b ldr r3, [r3, #104] @ 0x68 800c9d2: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c9d6: d02f beq.n 800ca38 800c9d8: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800c9dc: d828 bhi.n 800ca30 800c9de: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c9e2: d01a beq.n 800ca1a 800c9e4: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800c9e8: d822 bhi.n 800ca30 800c9ea: 2b00 cmp r3, #0 800c9ec: d003 beq.n 800c9f6 800c9ee: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800c9f2: d007 beq.n 800ca04 800c9f4: e01c b.n 800ca30 { case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ /* Enable PLL1Q Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800c9f6: 4bb8 ldr r3, [pc, #736] @ (800ccd8 ) 800c9f8: 6adb ldr r3, [r3, #44] @ 0x2c 800c9fa: 4ab7 ldr r2, [pc, #732] @ (800ccd8 ) 800c9fc: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ca00: 62d3 str r3, [r2, #44] @ 0x2c /* SPDIFRX clock source configuration done later after clock selection check */ break; 800ca02: e01a b.n 800ca3a case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800ca04: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca08: 3308 adds r3, #8 800ca0a: 2102 movs r1, #2 800ca0c: 4618 mov r0, r3 800ca0e: f002 fb45 bl 800f09c 800ca12: 4603 mov r3, r0 800ca14: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800ca18: e00f b.n 800ca3a case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800ca1a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca1e: 3328 adds r3, #40 @ 0x28 800ca20: 2102 movs r1, #2 800ca22: 4618 mov r0, r3 800ca24: f002 fbec bl 800f200 800ca28: 4603 mov r3, r0 800ca2a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPDIFRX clock source configuration done later after clock selection check */ break; 800ca2e: e004 b.n 800ca3a /* Internal OSC clock is used as source of SPDIFRX clock*/ /* SPDIFRX clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ca30: 2301 movs r3, #1 800ca32: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ca36: e000 b.n 800ca3a break; 800ca38: bf00 nop } if (ret == HAL_OK) 800ca3a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca3e: 2b00 cmp r3, #0 800ca40: d10a bne.n 800ca58 { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); 800ca42: 4ba5 ldr r3, [pc, #660] @ (800ccd8 ) 800ca44: 6d1b ldr r3, [r3, #80] @ 0x50 800ca46: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800ca4a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca4e: 6e9b ldr r3, [r3, #104] @ 0x68 800ca50: 4aa1 ldr r2, [pc, #644] @ (800ccd8 ) 800ca52: 430b orrs r3, r1 800ca54: 6513 str r3, [r2, #80] @ 0x50 800ca56: e003 b.n 800ca60 } else { /* set overall return value */ status = ret; 800ca58: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ca5c: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) 800ca60: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca64: e9d3 2300 ldrd r2, r3, [r3] 800ca68: f402 7880 and.w r8, r2, #256 @ 0x100 800ca6c: f04f 0900 mov.w r9, #0 800ca70: ea58 0309 orrs.w r3, r8, r9 800ca74: d047 beq.n 800cb06 { switch (PeriphClkInit->Sai1ClockSelection) 800ca76: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ca7a: 6d9b ldr r3, [r3, #88] @ 0x58 800ca7c: 2b04 cmp r3, #4 800ca7e: d82a bhi.n 800cad6 800ca80: a201 add r2, pc, #4 @ (adr r2, 800ca88 ) 800ca82: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ca86: bf00 nop 800ca88: 0800ca9d .word 0x0800ca9d 800ca8c: 0800caab .word 0x0800caab 800ca90: 0800cac1 .word 0x0800cac1 800ca94: 0800cadf .word 0x0800cadf 800ca98: 0800cadf .word 0x0800cadf { case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ca9c: 4b8e ldr r3, [pc, #568] @ (800ccd8 ) 800ca9e: 6adb ldr r3, [r3, #44] @ 0x2c 800caa0: 4a8d ldr r2, [pc, #564] @ (800ccd8 ) 800caa2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800caa6: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800caa8: e01a b.n 800cae0 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800caaa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caae: 3308 adds r3, #8 800cab0: 2100 movs r1, #0 800cab2: 4618 mov r0, r3 800cab4: f002 faf2 bl 800f09c 800cab8: 4603 mov r3, r0 800caba: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cabe: e00f b.n 800cae0 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cac0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cac4: 3328 adds r3, #40 @ 0x28 800cac6: 2100 movs r1, #0 800cac8: 4618 mov r0, r3 800caca: f002 fb99 bl 800f200 800cace: 4603 mov r3, r0 800cad0: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cad4: e004 b.n 800cae0 /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ /* SAI1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cad6: 2301 movs r3, #1 800cad8: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cadc: e000 b.n 800cae0 break; 800cade: bf00 nop } if (ret == HAL_OK) 800cae0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cae4: 2b00 cmp r3, #0 800cae6: d10a bne.n 800cafe { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 800cae8: 4b7b ldr r3, [pc, #492] @ (800ccd8 ) 800caea: 6d1b ldr r3, [r3, #80] @ 0x50 800caec: f023 0107 bic.w r1, r3, #7 800caf0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800caf4: 6d9b ldr r3, [r3, #88] @ 0x58 800caf6: 4a78 ldr r2, [pc, #480] @ (800ccd8 ) 800caf8: 430b orrs r3, r1 800cafa: 6513 str r3, [r2, #80] @ 0x50 800cafc: e003 b.n 800cb06 } else { /* set overall return value */ status = ret; 800cafe: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb02: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) 800cb06: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb0a: e9d3 2300 ldrd r2, r3, [r3] 800cb0e: f402 7a00 and.w sl, r2, #512 @ 0x200 800cb12: f04f 0b00 mov.w fp, #0 800cb16: ea5a 030b orrs.w r3, sl, fp 800cb1a: d04c beq.n 800cbb6 { switch (PeriphClkInit->Sai23ClockSelection) 800cb1c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb20: 6ddb ldr r3, [r3, #92] @ 0x5c 800cb22: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cb26: d030 beq.n 800cb8a 800cb28: f5b3 7f80 cmp.w r3, #256 @ 0x100 800cb2c: d829 bhi.n 800cb82 800cb2e: 2bc0 cmp r3, #192 @ 0xc0 800cb30: d02d beq.n 800cb8e 800cb32: 2bc0 cmp r3, #192 @ 0xc0 800cb34: d825 bhi.n 800cb82 800cb36: 2b80 cmp r3, #128 @ 0x80 800cb38: d018 beq.n 800cb6c 800cb3a: 2b80 cmp r3, #128 @ 0x80 800cb3c: d821 bhi.n 800cb82 800cb3e: 2b00 cmp r3, #0 800cb40: d002 beq.n 800cb48 800cb42: 2b40 cmp r3, #64 @ 0x40 800cb44: d007 beq.n 800cb56 800cb46: e01c b.n 800cb82 { case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cb48: 4b63 ldr r3, [pc, #396] @ (800ccd8 ) 800cb4a: 6adb ldr r3, [r3, #44] @ 0x2c 800cb4c: 4a62 ldr r2, [pc, #392] @ (800ccd8 ) 800cb4e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cb52: 62d3 str r3, [r2, #44] @ 0x2c /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb54: e01c b.n 800cb90 case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cb56: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb5a: 3308 adds r3, #8 800cb5c: 2100 movs r1, #0 800cb5e: 4618 mov r0, r3 800cb60: f002 fa9c bl 800f09c 800cb64: 4603 mov r3, r0 800cb66: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb6a: e011 b.n 800cb90 case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cb6c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cb70: 3328 adds r3, #40 @ 0x28 800cb72: 2100 movs r1, #0 800cb74: 4618 mov r0, r3 800cb76: f002 fb43 bl 800f200 800cb7a: 4603 mov r3, r0 800cb7c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2/3 clock source configuration done later after clock selection check */ break; 800cb80: e006 b.n 800cb90 /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ /* SAI2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cb82: 2301 movs r3, #1 800cb84: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cb88: e002 b.n 800cb90 break; 800cb8a: bf00 nop 800cb8c: e000 b.n 800cb90 break; 800cb8e: bf00 nop } if (ret == HAL_OK) 800cb90: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cb94: 2b00 cmp r3, #0 800cb96: d10a bne.n 800cbae { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); 800cb98: 4b4f ldr r3, [pc, #316] @ (800ccd8 ) 800cb9a: 6d1b ldr r3, [r3, #80] @ 0x50 800cb9c: f423 71e0 bic.w r1, r3, #448 @ 0x1c0 800cba0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cba4: 6ddb ldr r3, [r3, #92] @ 0x5c 800cba6: 4a4c ldr r2, [pc, #304] @ (800ccd8 ) 800cba8: 430b orrs r3, r1 800cbaa: 6513 str r3, [r2, #80] @ 0x50 800cbac: e003 b.n 800cbb6 } else { /* set overall return value */ status = ret; 800cbae: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cbb2: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI2B*/ #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) 800cbb6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbba: e9d3 2300 ldrd r2, r3, [r3] 800cbbe: f402 6380 and.w r3, r2, #1024 @ 0x400 800cbc2: f8c7 3100 str.w r3, [r7, #256] @ 0x100 800cbc6: 2300 movs r3, #0 800cbc8: f8c7 3104 str.w r3, [r7, #260] @ 0x104 800cbcc: e9d7 1240 ldrd r1, r2, [r7, #256] @ 0x100 800cbd0: 460b mov r3, r1 800cbd2: 4313 orrs r3, r2 800cbd4: d053 beq.n 800cc7e { switch (PeriphClkInit->Sai4AClockSelection) 800cbd6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cbda: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800cbde: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800cbe2: d035 beq.n 800cc50 800cbe4: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800cbe8: d82e bhi.n 800cc48 800cbea: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800cbee: d031 beq.n 800cc54 800cbf0: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800cbf4: d828 bhi.n 800cc48 800cbf6: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800cbfa: d01a beq.n 800cc32 800cbfc: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800cc00: d822 bhi.n 800cc48 800cc02: 2b00 cmp r3, #0 800cc04: d003 beq.n 800cc0e 800cc06: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800cc0a: d007 beq.n 800cc1c 800cc0c: e01c b.n 800cc48 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cc0e: 4b32 ldr r3, [pc, #200] @ (800ccd8 ) 800cc10: 6adb ldr r3, [r3, #44] @ 0x2c 800cc12: 4a31 ldr r2, [pc, #196] @ (800ccd8 ) 800cc14: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cc18: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800cc1a: e01c b.n 800cc56 case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800cc1c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc20: 3308 adds r3, #8 800cc22: 2100 movs r1, #0 800cc24: 4618 mov r0, r3 800cc26: f002 fa39 bl 800f09c 800cc2a: 4603 mov r3, r0 800cc2c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800cc30: e011 b.n 800cc56 case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cc32: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc36: 3328 adds r3, #40 @ 0x28 800cc38: 2100 movs r1, #0 800cc3a: 4618 mov r0, r3 800cc3c: f002 fae0 bl 800f200 800cc40: 4603 mov r3, r0 800cc42: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cc46: e006 b.n 800cc56 /* SAI4A clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800cc48: 2301 movs r3, #1 800cc4a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cc4e: e002 b.n 800cc56 break; 800cc50: bf00 nop 800cc52: e000 b.n 800cc56 break; 800cc54: bf00 nop } if (ret == HAL_OK) 800cc56: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc5a: 2b00 cmp r3, #0 800cc5c: d10b bne.n 800cc76 { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); 800cc5e: 4b1e ldr r3, [pc, #120] @ (800ccd8 ) 800cc60: 6d9b ldr r3, [r3, #88] @ 0x58 800cc62: f423 0160 bic.w r1, r3, #14680064 @ 0xe00000 800cc66: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc6a: f8d3 30a8 ldr.w r3, [r3, #168] @ 0xa8 800cc6e: 4a1a ldr r2, [pc, #104] @ (800ccd8 ) 800cc70: 430b orrs r3, r1 800cc72: 6593 str r3, [r2, #88] @ 0x58 800cc74: e003 b.n 800cc7e } else { /* set overall return value */ status = ret; 800cc76: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cc7a: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SAI4B configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) 800cc7e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cc82: e9d3 2300 ldrd r2, r3, [r3] 800cc86: f402 6300 and.w r3, r2, #2048 @ 0x800 800cc8a: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 800cc8e: 2300 movs r3, #0 800cc90: f8c7 30fc str.w r3, [r7, #252] @ 0xfc 800cc94: e9d7 123e ldrd r1, r2, [r7, #248] @ 0xf8 800cc98: 460b mov r3, r1 800cc9a: 4313 orrs r3, r2 800cc9c: d056 beq.n 800cd4c { switch (PeriphClkInit->Sai4BClockSelection) 800cc9e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cca2: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800cca6: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800ccaa: d038 beq.n 800cd1e 800ccac: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800ccb0: d831 bhi.n 800cd16 800ccb2: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800ccb6: d034 beq.n 800cd22 800ccb8: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800ccbc: d82b bhi.n 800cd16 800ccbe: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ccc2: d01d beq.n 800cd00 800ccc4: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ccc8: d825 bhi.n 800cd16 800ccca: 2b00 cmp r3, #0 800cccc: d006 beq.n 800ccdc 800ccce: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800ccd2: d00a beq.n 800ccea 800ccd4: e01f b.n 800cd16 800ccd6: bf00 nop 800ccd8: 58024400 .word 0x58024400 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ /* Enable SAI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ccdc: 4ba2 ldr r3, [pc, #648] @ (800cf68 ) 800ccde: 6adb ldr r3, [r3, #44] @ 0x2c 800cce0: 4aa1 ldr r2, [pc, #644] @ (800cf68 ) 800cce2: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cce6: 62d3 str r3, [r2, #44] @ 0x2c /* SAI1 clock source configuration done later after clock selection check */ break; 800cce8: e01c b.n 800cd24 case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800ccea: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ccee: 3308 adds r3, #8 800ccf0: 2100 movs r1, #0 800ccf2: 4618 mov r0, r3 800ccf4: f002 f9d2 bl 800f09c 800ccf8: 4603 mov r3, r0 800ccfa: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI2 clock source configuration done later after clock selection check */ break; 800ccfe: e011 b.n 800cd24 case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800cd00: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd04: 3328 adds r3, #40 @ 0x28 800cd06: 2100 movs r1, #0 800cd08: 4618 mov r0, r3 800cd0a: f002 fa79 bl 800f200 800cd0e: 4603 mov r3, r0 800cd10: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SAI1 clock source configuration done later after clock selection check */ break; 800cd14: e006 b.n 800cd24 /* SAI4B clock source configuration done later after clock selection check */ break; #endif /* RCC_VER_3_0 */ default: ret = HAL_ERROR; 800cd16: 2301 movs r3, #1 800cd18: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cd1c: e002 b.n 800cd24 break; 800cd1e: bf00 nop 800cd20: e000 b.n 800cd24 break; 800cd22: bf00 nop } if (ret == HAL_OK) 800cd24: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd28: 2b00 cmp r3, #0 800cd2a: d10b bne.n 800cd44 { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); 800cd2c: 4b8e ldr r3, [pc, #568] @ (800cf68 ) 800cd2e: 6d9b ldr r3, [r3, #88] @ 0x58 800cd30: f023 61e0 bic.w r1, r3, #117440512 @ 0x7000000 800cd34: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd38: f8d3 30ac ldr.w r3, [r3, #172] @ 0xac 800cd3c: 4a8a ldr r2, [pc, #552] @ (800cf68 ) 800cd3e: 430b orrs r3, r1 800cd40: 6593 str r3, [r2, #88] @ 0x58 800cd42: e003 b.n 800cd4c } else { /* set overall return value */ status = ret; 800cd44: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cd48: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*SAI4*/ #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) 800cd4c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd50: e9d3 2300 ldrd r2, r3, [r3] 800cd54: f002 7300 and.w r3, r2, #33554432 @ 0x2000000 800cd58: f8c7 30f0 str.w r3, [r7, #240] @ 0xf0 800cd5c: 2300 movs r3, #0 800cd5e: f8c7 30f4 str.w r3, [r7, #244] @ 0xf4 800cd62: e9d7 123c ldrd r1, r2, [r7, #240] @ 0xf0 800cd66: 460b mov r3, r1 800cd68: 4313 orrs r3, r2 800cd6a: d03a beq.n 800cde2 { switch (PeriphClkInit->QspiClockSelection) 800cd6c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd70: 6cdb ldr r3, [r3, #76] @ 0x4c 800cd72: 2b30 cmp r3, #48 @ 0x30 800cd74: d01f beq.n 800cdb6 800cd76: 2b30 cmp r3, #48 @ 0x30 800cd78: d819 bhi.n 800cdae 800cd7a: 2b20 cmp r3, #32 800cd7c: d00c beq.n 800cd98 800cd7e: 2b20 cmp r3, #32 800cd80: d815 bhi.n 800cdae 800cd82: 2b00 cmp r3, #0 800cd84: d019 beq.n 800cdba 800cd86: 2b10 cmp r3, #16 800cd88: d111 bne.n 800cdae { case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ /* Enable QSPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800cd8a: 4b77 ldr r3, [pc, #476] @ (800cf68 ) 800cd8c: 6adb ldr r3, [r3, #44] @ 0x2c 800cd8e: 4a76 ldr r2, [pc, #472] @ (800cf68 ) 800cd90: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800cd94: 62d3 str r3, [r2, #44] @ 0x2c /* QSPI clock source configuration done later after clock selection check */ break; 800cd96: e011 b.n 800cdbc case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800cd98: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cd9c: 3308 adds r3, #8 800cd9e: 2102 movs r1, #2 800cda0: 4618 mov r0, r3 800cda2: f002 f97b bl 800f09c 800cda6: 4603 mov r3, r0 800cda8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* QSPI clock source configuration done later after clock selection check */ break; 800cdac: e006 b.n 800cdbc case RCC_QSPICLKSOURCE_D1HCLK: /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ break; default: ret = HAL_ERROR; 800cdae: 2301 movs r3, #1 800cdb0: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cdb4: e002 b.n 800cdbc break; 800cdb6: bf00 nop 800cdb8: e000 b.n 800cdbc break; 800cdba: bf00 nop } if (ret == HAL_OK) 800cdbc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdc0: 2b00 cmp r3, #0 800cdc2: d10a bne.n 800cdda { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); 800cdc4: 4b68 ldr r3, [pc, #416] @ (800cf68 ) 800cdc6: 6cdb ldr r3, [r3, #76] @ 0x4c 800cdc8: f023 0130 bic.w r1, r3, #48 @ 0x30 800cdcc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cdd0: 6cdb ldr r3, [r3, #76] @ 0x4c 800cdd2: 4a65 ldr r2, [pc, #404] @ (800cf68 ) 800cdd4: 430b orrs r3, r1 800cdd6: 64d3 str r3, [r2, #76] @ 0x4c 800cdd8: e003 b.n 800cde2 } else { /* set overall return value */ status = ret; 800cdda: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cdde: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) 800cde2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cde6: e9d3 2300 ldrd r2, r3, [r3] 800cdea: f402 5380 and.w r3, r2, #4096 @ 0x1000 800cdee: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 800cdf2: 2300 movs r3, #0 800cdf4: f8c7 30ec str.w r3, [r7, #236] @ 0xec 800cdf8: e9d7 123a ldrd r1, r2, [r7, #232] @ 0xe8 800cdfc: 460b mov r3, r1 800cdfe: 4313 orrs r3, r2 800ce00: d051 beq.n 800cea6 { switch (PeriphClkInit->Spi123ClockSelection) 800ce02: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce06: 6e1b ldr r3, [r3, #96] @ 0x60 800ce08: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800ce0c: d035 beq.n 800ce7a 800ce0e: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800ce12: d82e bhi.n 800ce72 800ce14: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800ce18: d031 beq.n 800ce7e 800ce1a: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800ce1e: d828 bhi.n 800ce72 800ce20: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ce24: d01a beq.n 800ce5c 800ce26: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800ce2a: d822 bhi.n 800ce72 800ce2c: 2b00 cmp r3, #0 800ce2e: d003 beq.n 800ce38 800ce30: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800ce34: d007 beq.n 800ce46 800ce36: e01c b.n 800ce72 { case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ /* Enable SPI Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800ce38: 4b4b ldr r3, [pc, #300] @ (800cf68 ) 800ce3a: 6adb ldr r3, [r3, #44] @ 0x2c 800ce3c: 4a4a ldr r2, [pc, #296] @ (800cf68 ) 800ce3e: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800ce42: 62d3 str r3, [r2, #44] @ 0x2c /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce44: e01c b.n 800ce80 case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800ce46: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce4a: 3308 adds r3, #8 800ce4c: 2100 movs r1, #0 800ce4e: 4618 mov r0, r3 800ce50: f002 f924 bl 800f09c 800ce54: 4603 mov r3, r0 800ce56: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce5a: e011 b.n 800ce80 case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800ce5c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce60: 3328 adds r3, #40 @ 0x28 800ce62: 2100 movs r1, #0 800ce64: 4618 mov r0, r3 800ce66: f002 f9cb bl 800f200 800ce6a: 4603 mov r3, r0 800ce6c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI1/2/3 clock source configuration done later after clock selection check */ break; 800ce70: e006 b.n 800ce80 /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ /* SPI1/2/3 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800ce72: 2301 movs r3, #1 800ce74: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800ce78: e002 b.n 800ce80 break; 800ce7a: bf00 nop 800ce7c: e000 b.n 800ce80 break; 800ce7e: bf00 nop } if (ret == HAL_OK) 800ce80: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800ce84: 2b00 cmp r3, #0 800ce86: d10a bne.n 800ce9e { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); 800ce88: 4b37 ldr r3, [pc, #220] @ (800cf68 ) 800ce8a: 6d1b ldr r3, [r3, #80] @ 0x50 800ce8c: f423 41e0 bic.w r1, r3, #28672 @ 0x7000 800ce90: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ce94: 6e1b ldr r3, [r3, #96] @ 0x60 800ce96: 4a34 ldr r2, [pc, #208] @ (800cf68 ) 800ce98: 430b orrs r3, r1 800ce9a: 6513 str r3, [r2, #80] @ 0x50 800ce9c: e003 b.n 800cea6 } else { /* set overall return value */ status = ret; 800ce9e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cea2: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI4/5 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) 800cea6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ceaa: e9d3 2300 ldrd r2, r3, [r3] 800ceae: f402 5300 and.w r3, r2, #8192 @ 0x2000 800ceb2: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 800ceb6: 2300 movs r3, #0 800ceb8: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 800cebc: e9d7 1238 ldrd r1, r2, [r7, #224] @ 0xe0 800cec0: 460b mov r3, r1 800cec2: 4313 orrs r3, r2 800cec4: d056 beq.n 800cf74 { switch (PeriphClkInit->Spi45ClockSelection) 800cec6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800ceca: 6e5b ldr r3, [r3, #100] @ 0x64 800cecc: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800ced0: d033 beq.n 800cf3a 800ced2: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800ced6: d82c bhi.n 800cf32 800ced8: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cedc: d02f beq.n 800cf3e 800cede: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800cee2: d826 bhi.n 800cf32 800cee4: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800cee8: d02b beq.n 800cf42 800ceea: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800ceee: d820 bhi.n 800cf32 800cef0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cef4: d012 beq.n 800cf1c 800cef6: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800cefa: d81a bhi.n 800cf32 800cefc: 2b00 cmp r3, #0 800cefe: d022 beq.n 800cf46 800cf00: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800cf04: d115 bne.n 800cf32 /* SPI4/5 clock source configuration done later after clock selection check */ break; case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cf06: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf0a: 3308 adds r3, #8 800cf0c: 2101 movs r1, #1 800cf0e: 4618 mov r0, r3 800cf10: f002 f8c4 bl 800f09c 800cf14: 4603 mov r3, r0 800cf16: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cf1a: e015 b.n 800cf48 case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cf1c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf20: 3328 adds r3, #40 @ 0x28 800cf22: 2101 movs r1, #1 800cf24: 4618 mov r0, r3 800cf26: f002 f96b bl 800f200 800cf2a: 4603 mov r3, r0 800cf2c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI4/5 clock source configuration done later after clock selection check */ break; 800cf30: e00a b.n 800cf48 /* HSE, oscillator is used as source of SPI4/5 clock */ /* SPI4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800cf32: 2301 movs r3, #1 800cf34: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800cf38: e006 b.n 800cf48 break; 800cf3a: bf00 nop 800cf3c: e004 b.n 800cf48 break; 800cf3e: bf00 nop 800cf40: e002 b.n 800cf48 break; 800cf42: bf00 nop 800cf44: e000 b.n 800cf48 break; 800cf46: bf00 nop } if (ret == HAL_OK) 800cf48: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf4c: 2b00 cmp r3, #0 800cf4e: d10d bne.n 800cf6c { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); 800cf50: 4b05 ldr r3, [pc, #20] @ (800cf68 ) 800cf52: 6d1b ldr r3, [r3, #80] @ 0x50 800cf54: f423 21e0 bic.w r1, r3, #458752 @ 0x70000 800cf58: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf5c: 6e5b ldr r3, [r3, #100] @ 0x64 800cf5e: 4a02 ldr r2, [pc, #8] @ (800cf68 ) 800cf60: 430b orrs r3, r1 800cf62: 6513 str r3, [r2, #80] @ 0x50 800cf64: e006 b.n 800cf74 800cf66: bf00 nop 800cf68: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800cf6c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800cf70: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- SPI6 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) 800cf74: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf78: e9d3 2300 ldrd r2, r3, [r3] 800cf7c: f402 4380 and.w r3, r2, #16384 @ 0x4000 800cf80: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 800cf84: 2300 movs r3, #0 800cf86: f8c7 30dc str.w r3, [r7, #220] @ 0xdc 800cf8a: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 800cf8e: 460b mov r3, r1 800cf90: 4313 orrs r3, r2 800cf92: d055 beq.n 800d040 { switch (PeriphClkInit->Spi6ClockSelection) 800cf94: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cf98: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800cf9c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cfa0: d033 beq.n 800d00a 800cfa2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800cfa6: d82c bhi.n 800d002 800cfa8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cfac: d02f beq.n 800d00e 800cfae: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800cfb2: d826 bhi.n 800d002 800cfb4: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cfb8: d02b beq.n 800d012 800cfba: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800cfbe: d820 bhi.n 800d002 800cfc0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cfc4: d012 beq.n 800cfec 800cfc6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800cfca: d81a bhi.n 800d002 800cfcc: 2b00 cmp r3, #0 800cfce: d022 beq.n 800d016 800cfd0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800cfd4: d115 bne.n 800d002 /* SPI6 clock source configuration done later after clock selection check */ break; case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800cfd6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cfda: 3308 adds r3, #8 800cfdc: 2101 movs r1, #1 800cfde: 4618 mov r0, r3 800cfe0: f002 f85c bl 800f09c 800cfe4: 4603 mov r3, r0 800cfe6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800cfea: e015 b.n 800d018 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800cfec: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800cff0: 3328 adds r3, #40 @ 0x28 800cff2: 2101 movs r1, #1 800cff4: 4618 mov r0, r3 800cff6: f002 f903 bl 800f200 800cffa: 4603 mov r3, r0 800cffc: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SPI6 clock source configuration done later after clock selection check */ break; 800d000: e00a b.n 800d018 /* SPI6 clock source configuration done later after clock selection check */ break; #endif default: ret = HAL_ERROR; 800d002: 2301 movs r3, #1 800d004: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d008: e006 b.n 800d018 break; 800d00a: bf00 nop 800d00c: e004 b.n 800d018 break; 800d00e: bf00 nop 800d010: e002 b.n 800d018 break; 800d012: bf00 nop 800d014: e000 b.n 800d018 break; 800d016: bf00 nop } if (ret == HAL_OK) 800d018: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d01c: 2b00 cmp r3, #0 800d01e: d10b bne.n 800d038 { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); 800d020: 4ba3 ldr r3, [pc, #652] @ (800d2b0 ) 800d022: 6d9b ldr r3, [r3, #88] @ 0x58 800d024: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d028: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d02c: f8d3 30b0 ldr.w r3, [r3, #176] @ 0xb0 800d030: 4a9f ldr r2, [pc, #636] @ (800d2b0 ) 800d032: 430b orrs r3, r1 800d034: 6593 str r3, [r2, #88] @ 0x58 800d036: e003 b.n 800d040 } else { /* set overall return value */ status = ret; 800d038: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d03c: f887 311e strb.w r3, [r7, #286] @ 0x11e } #endif /*DSI*/ #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) 800d040: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d044: e9d3 2300 ldrd r2, r3, [r3] 800d048: f402 4300 and.w r3, r2, #32768 @ 0x8000 800d04c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 800d050: 2300 movs r3, #0 800d052: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 800d056: e9d7 1234 ldrd r1, r2, [r7, #208] @ 0xd0 800d05a: 460b mov r3, r1 800d05c: 4313 orrs r3, r2 800d05e: d037 beq.n 800d0d0 { switch (PeriphClkInit->FdcanClockSelection) 800d060: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d064: 6f1b ldr r3, [r3, #112] @ 0x70 800d066: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d06a: d00e beq.n 800d08a 800d06c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d070: d816 bhi.n 800d0a0 800d072: 2b00 cmp r3, #0 800d074: d018 beq.n 800d0a8 800d076: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d07a: d111 bne.n 800d0a0 { case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ /* Enable FDCAN Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d07c: 4b8c ldr r3, [pc, #560] @ (800d2b0 ) 800d07e: 6adb ldr r3, [r3, #44] @ 0x2c 800d080: 4a8b ldr r2, [pc, #556] @ (800d2b0 ) 800d082: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d086: 62d3 str r3, [r2, #44] @ 0x2c /* FDCAN clock source configuration done later after clock selection check */ break; 800d088: e00f b.n 800d0aa case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d08a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d08e: 3308 adds r3, #8 800d090: 2101 movs r1, #1 800d092: 4618 mov r0, r3 800d094: f002 f802 bl 800f09c 800d098: 4603 mov r3, r0 800d09a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FDCAN clock source configuration done later after clock selection check */ break; 800d09e: e004 b.n 800d0aa /* HSE is used as clock source for FDCAN*/ /* FDCAN clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d0a0: 2301 movs r3, #1 800d0a2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d0a6: e000 b.n 800d0aa break; 800d0a8: bf00 nop } if (ret == HAL_OK) 800d0aa: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0ae: 2b00 cmp r3, #0 800d0b0: d10a bne.n 800d0c8 { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); 800d0b2: 4b7f ldr r3, [pc, #508] @ (800d2b0 ) 800d0b4: 6d1b ldr r3, [r3, #80] @ 0x50 800d0b6: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800d0ba: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0be: 6f1b ldr r3, [r3, #112] @ 0x70 800d0c0: 4a7b ldr r2, [pc, #492] @ (800d2b0 ) 800d0c2: 430b orrs r3, r1 800d0c4: 6513 str r3, [r2, #80] @ 0x50 800d0c6: e003 b.n 800d0d0 } else { /* set overall return value */ status = ret; 800d0c8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d0cc: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) 800d0d0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0d4: e9d3 2300 ldrd r2, r3, [r3] 800d0d8: f002 7380 and.w r3, r2, #16777216 @ 0x1000000 800d0dc: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 800d0e0: 2300 movs r3, #0 800d0e2: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 800d0e6: e9d7 1232 ldrd r1, r2, [r7, #200] @ 0xc8 800d0ea: 460b mov r3, r1 800d0ec: 4313 orrs r3, r2 800d0ee: d039 beq.n 800d164 { switch (PeriphClkInit->FmcClockSelection) 800d0f0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d0f4: 6c9b ldr r3, [r3, #72] @ 0x48 800d0f6: 2b03 cmp r3, #3 800d0f8: d81c bhi.n 800d134 800d0fa: a201 add r2, pc, #4 @ (adr r2, 800d100 ) 800d0fc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d100: 0800d13d .word 0x0800d13d 800d104: 0800d111 .word 0x0800d111 800d108: 0800d11f .word 0x0800d11f 800d10c: 0800d13d .word 0x0800d13d { case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ /* Enable FMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d110: 4b67 ldr r3, [pc, #412] @ (800d2b0 ) 800d112: 6adb ldr r3, [r3, #44] @ 0x2c 800d114: 4a66 ldr r2, [pc, #408] @ (800d2b0 ) 800d116: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d11a: 62d3 str r3, [r2, #44] @ 0x2c /* FMC clock source configuration done later after clock selection check */ break; 800d11c: e00f b.n 800d13e case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d11e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d122: 3308 adds r3, #8 800d124: 2102 movs r1, #2 800d126: 4618 mov r0, r3 800d128: f001 ffb8 bl 800f09c 800d12c: 4603 mov r3, r0 800d12e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* FMC clock source configuration done later after clock selection check */ break; 800d132: e004 b.n 800d13e case RCC_FMCCLKSOURCE_HCLK: /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ break; default: ret = HAL_ERROR; 800d134: 2301 movs r3, #1 800d136: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d13a: e000 b.n 800d13e break; 800d13c: bf00 nop } if (ret == HAL_OK) 800d13e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d142: 2b00 cmp r3, #0 800d144: d10a bne.n 800d15c { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); 800d146: 4b5a ldr r3, [pc, #360] @ (800d2b0 ) 800d148: 6cdb ldr r3, [r3, #76] @ 0x4c 800d14a: f023 0103 bic.w r1, r3, #3 800d14e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d152: 6c9b ldr r3, [r3, #72] @ 0x48 800d154: 4a56 ldr r2, [pc, #344] @ (800d2b0 ) 800d156: 430b orrs r3, r1 800d158: 64d3 str r3, [r2, #76] @ 0x4c 800d15a: e003 b.n 800d164 } else { /* set overall return value */ status = ret; 800d15c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d160: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- RTC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800d164: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d168: e9d3 2300 ldrd r2, r3, [r3] 800d16c: f402 0380 and.w r3, r2, #4194304 @ 0x400000 800d170: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 800d174: 2300 movs r3, #0 800d176: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 800d17a: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 800d17e: 460b mov r3, r1 800d180: 4313 orrs r3, r2 800d182: f000 809f beq.w 800d2c4 { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 800d186: 4b4b ldr r3, [pc, #300] @ (800d2b4 ) 800d188: 681b ldr r3, [r3, #0] 800d18a: 4a4a ldr r2, [pc, #296] @ (800d2b4 ) 800d18c: f443 7380 orr.w r3, r3, #256 @ 0x100 800d190: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800d192: f7f8 fe47 bl 8005e24 800d196: f8c7 0118 str.w r0, [r7, #280] @ 0x118 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800d19a: e00b b.n 800d1b4 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800d19c: f7f8 fe42 bl 8005e24 800d1a0: 4602 mov r2, r0 800d1a2: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800d1a6: 1ad3 subs r3, r2, r3 800d1a8: 2b64 cmp r3, #100 @ 0x64 800d1aa: d903 bls.n 800d1b4 { ret = HAL_TIMEOUT; 800d1ac: 2303 movs r3, #3 800d1ae: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d1b2: e005 b.n 800d1c0 while ((PWR->CR1 & PWR_CR1_DBP) == 0U) 800d1b4: 4b3f ldr r3, [pc, #252] @ (800d2b4 ) 800d1b6: 681b ldr r3, [r3, #0] 800d1b8: f403 7380 and.w r3, r3, #256 @ 0x100 800d1bc: 2b00 cmp r3, #0 800d1be: d0ed beq.n 800d19c } } if (ret == HAL_OK) 800d1c0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d1c4: 2b00 cmp r3, #0 800d1c6: d179 bne.n 800d2bc { /* Reset the Backup domain only if the RTC Clock source selection is modified */ if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) 800d1c8: 4b39 ldr r3, [pc, #228] @ (800d2b0 ) 800d1ca: 6f1a ldr r2, [r3, #112] @ 0x70 800d1cc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d1d0: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d1d4: 4053 eors r3, r2 800d1d6: f403 7340 and.w r3, r3, #768 @ 0x300 800d1da: 2b00 cmp r3, #0 800d1dc: d015 beq.n 800d20a { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800d1de: 4b34 ldr r3, [pc, #208] @ (800d2b0 ) 800d1e0: 6f1b ldr r3, [r3, #112] @ 0x70 800d1e2: f423 7340 bic.w r3, r3, #768 @ 0x300 800d1e6: f8c7 3114 str.w r3, [r7, #276] @ 0x114 /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 800d1ea: 4b31 ldr r3, [pc, #196] @ (800d2b0 ) 800d1ec: 6f1b ldr r3, [r3, #112] @ 0x70 800d1ee: 4a30 ldr r2, [pc, #192] @ (800d2b0 ) 800d1f0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 800d1f4: 6713 str r3, [r2, #112] @ 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); 800d1f6: 4b2e ldr r3, [pc, #184] @ (800d2b0 ) 800d1f8: 6f1b ldr r3, [r3, #112] @ 0x70 800d1fa: 4a2d ldr r2, [pc, #180] @ (800d2b0 ) 800d1fc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800d200: 6713 str r3, [r2, #112] @ 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg; 800d202: 4a2b ldr r2, [pc, #172] @ (800d2b0 ) 800d204: f8d7 3114 ldr.w r3, [r7, #276] @ 0x114 800d208: 6713 str r3, [r2, #112] @ 0x70 } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) 800d20a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d20e: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d212: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d216: d118 bne.n 800d24a { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800d218: f7f8 fe04 bl 8005e24 800d21c: f8c7 0118 str.w r0, [r7, #280] @ 0x118 /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800d220: e00d b.n 800d23e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800d222: f7f8 fdff bl 8005e24 800d226: 4602 mov r2, r0 800d228: f8d7 3118 ldr.w r3, [r7, #280] @ 0x118 800d22c: 1ad2 subs r2, r2, r3 800d22e: f241 3388 movw r3, #5000 @ 0x1388 800d232: 429a cmp r2, r3 800d234: d903 bls.n 800d23e { ret = HAL_TIMEOUT; 800d236: 2303 movs r3, #3 800d238: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d23c: e005 b.n 800d24a while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) 800d23e: 4b1c ldr r3, [pc, #112] @ (800d2b0 ) 800d240: 6f1b ldr r3, [r3, #112] @ 0x70 800d242: f003 0302 and.w r3, r3, #2 800d246: 2b00 cmp r3, #0 800d248: d0eb beq.n 800d222 } } } if (ret == HAL_OK) 800d24a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d24e: 2b00 cmp r3, #0 800d250: d129 bne.n 800d2a6 { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800d252: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d256: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d25a: f403 7340 and.w r3, r3, #768 @ 0x300 800d25e: f5b3 7f40 cmp.w r3, #768 @ 0x300 800d262: d10e bne.n 800d282 800d264: 4b12 ldr r3, [pc, #72] @ (800d2b0 ) 800d266: 691b ldr r3, [r3, #16] 800d268: f423 517c bic.w r1, r3, #16128 @ 0x3f00 800d26c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d270: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d274: 091a lsrs r2, r3, #4 800d276: 4b10 ldr r3, [pc, #64] @ (800d2b8 ) 800d278: 4013 ands r3, r2 800d27a: 4a0d ldr r2, [pc, #52] @ (800d2b0 ) 800d27c: 430b orrs r3, r1 800d27e: 6113 str r3, [r2, #16] 800d280: e005 b.n 800d28e 800d282: 4b0b ldr r3, [pc, #44] @ (800d2b0 ) 800d284: 691b ldr r3, [r3, #16] 800d286: 4a0a ldr r2, [pc, #40] @ (800d2b0 ) 800d288: f423 537c bic.w r3, r3, #16128 @ 0x3f00 800d28c: 6113 str r3, [r2, #16] 800d28e: 4b08 ldr r3, [pc, #32] @ (800d2b0 ) 800d290: 6f19 ldr r1, [r3, #112] @ 0x70 800d292: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d296: f8d3 30b4 ldr.w r3, [r3, #180] @ 0xb4 800d29a: f3c3 030b ubfx r3, r3, #0, #12 800d29e: 4a04 ldr r2, [pc, #16] @ (800d2b0 ) 800d2a0: 430b orrs r3, r1 800d2a2: 6713 str r3, [r2, #112] @ 0x70 800d2a4: e00e b.n 800d2c4 } else { /* set overall return value */ status = ret; 800d2a6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d2aa: f887 311e strb.w r3, [r7, #286] @ 0x11e 800d2ae: e009 b.n 800d2c4 800d2b0: 58024400 .word 0x58024400 800d2b4: 58024800 .word 0x58024800 800d2b8: 00ffffcf .word 0x00ffffcf } } else { /* set overall return value */ status = ret; 800d2bc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d2c0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART1/6 configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) 800d2c4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2c8: e9d3 2300 ldrd r2, r3, [r3] 800d2cc: f002 0301 and.w r3, r2, #1 800d2d0: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 800d2d4: 2300 movs r3, #0 800d2d6: f8c7 30bc str.w r3, [r7, #188] @ 0xbc 800d2da: e9d7 122e ldrd r1, r2, [r7, #184] @ 0xb8 800d2de: 460b mov r3, r1 800d2e0: 4313 orrs r3, r2 800d2e2: f000 8089 beq.w 800d3f8 { switch (PeriphClkInit->Usart16ClockSelection) 800d2e6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d2ea: 6fdb ldr r3, [r3, #124] @ 0x7c 800d2ec: 2b28 cmp r3, #40 @ 0x28 800d2ee: d86b bhi.n 800d3c8 800d2f0: a201 add r2, pc, #4 @ (adr r2, 800d2f8 ) 800d2f2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d2f6: bf00 nop 800d2f8: 0800d3d1 .word 0x0800d3d1 800d2fc: 0800d3c9 .word 0x0800d3c9 800d300: 0800d3c9 .word 0x0800d3c9 800d304: 0800d3c9 .word 0x0800d3c9 800d308: 0800d3c9 .word 0x0800d3c9 800d30c: 0800d3c9 .word 0x0800d3c9 800d310: 0800d3c9 .word 0x0800d3c9 800d314: 0800d3c9 .word 0x0800d3c9 800d318: 0800d39d .word 0x0800d39d 800d31c: 0800d3c9 .word 0x0800d3c9 800d320: 0800d3c9 .word 0x0800d3c9 800d324: 0800d3c9 .word 0x0800d3c9 800d328: 0800d3c9 .word 0x0800d3c9 800d32c: 0800d3c9 .word 0x0800d3c9 800d330: 0800d3c9 .word 0x0800d3c9 800d334: 0800d3c9 .word 0x0800d3c9 800d338: 0800d3b3 .word 0x0800d3b3 800d33c: 0800d3c9 .word 0x0800d3c9 800d340: 0800d3c9 .word 0x0800d3c9 800d344: 0800d3c9 .word 0x0800d3c9 800d348: 0800d3c9 .word 0x0800d3c9 800d34c: 0800d3c9 .word 0x0800d3c9 800d350: 0800d3c9 .word 0x0800d3c9 800d354: 0800d3c9 .word 0x0800d3c9 800d358: 0800d3d1 .word 0x0800d3d1 800d35c: 0800d3c9 .word 0x0800d3c9 800d360: 0800d3c9 .word 0x0800d3c9 800d364: 0800d3c9 .word 0x0800d3c9 800d368: 0800d3c9 .word 0x0800d3c9 800d36c: 0800d3c9 .word 0x0800d3c9 800d370: 0800d3c9 .word 0x0800d3c9 800d374: 0800d3c9 .word 0x0800d3c9 800d378: 0800d3d1 .word 0x0800d3d1 800d37c: 0800d3c9 .word 0x0800d3c9 800d380: 0800d3c9 .word 0x0800d3c9 800d384: 0800d3c9 .word 0x0800d3c9 800d388: 0800d3c9 .word 0x0800d3c9 800d38c: 0800d3c9 .word 0x0800d3c9 800d390: 0800d3c9 .word 0x0800d3c9 800d394: 0800d3c9 .word 0x0800d3c9 800d398: 0800d3d1 .word 0x0800d3d1 case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ /* USART1/6 clock source configuration done later after clock selection check */ break; case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d39c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3a0: 3308 adds r3, #8 800d3a2: 2101 movs r1, #1 800d3a4: 4618 mov r0, r3 800d3a6: f001 fe79 bl 800f09c 800d3aa: 4603 mov r3, r0 800d3ac: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d3b0: e00f b.n 800d3d2 case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d3b2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3b6: 3328 adds r3, #40 @ 0x28 800d3b8: 2101 movs r1, #1 800d3ba: 4618 mov r0, r3 800d3bc: f001 ff20 bl 800f200 800d3c0: 4603 mov r3, r0 800d3c2: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART1/6 clock source configuration done later after clock selection check */ break; 800d3c6: e004 b.n 800d3d2 /* LSE, oscillator is used as source of USART1/6 clock */ /* USART1/6 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d3c8: 2301 movs r3, #1 800d3ca: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d3ce: e000 b.n 800d3d2 break; 800d3d0: bf00 nop } if (ret == HAL_OK) 800d3d2: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d3d6: 2b00 cmp r3, #0 800d3d8: d10a bne.n 800d3f0 { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); 800d3da: 4bbf ldr r3, [pc, #764] @ (800d6d8 ) 800d3dc: 6d5b ldr r3, [r3, #84] @ 0x54 800d3de: f023 0138 bic.w r1, r3, #56 @ 0x38 800d3e2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3e6: 6fdb ldr r3, [r3, #124] @ 0x7c 800d3e8: 4abb ldr r2, [pc, #748] @ (800d6d8 ) 800d3ea: 430b orrs r3, r1 800d3ec: 6553 str r3, [r2, #84] @ 0x54 800d3ee: e003 b.n 800d3f8 } else { /* set overall return value */ status = ret; 800d3f0: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d3f4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) 800d3f8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d3fc: e9d3 2300 ldrd r2, r3, [r3] 800d400: f002 0302 and.w r3, r2, #2 800d404: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 800d408: 2300 movs r3, #0 800d40a: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 800d40e: e9d7 122c ldrd r1, r2, [r7, #176] @ 0xb0 800d412: 460b mov r3, r1 800d414: 4313 orrs r3, r2 800d416: d041 beq.n 800d49c { switch (PeriphClkInit->Usart234578ClockSelection) 800d418: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d41c: 6f9b ldr r3, [r3, #120] @ 0x78 800d41e: 2b05 cmp r3, #5 800d420: d824 bhi.n 800d46c 800d422: a201 add r2, pc, #4 @ (adr r2, 800d428 ) 800d424: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d428: 0800d475 .word 0x0800d475 800d42c: 0800d441 .word 0x0800d441 800d430: 0800d457 .word 0x0800d457 800d434: 0800d475 .word 0x0800d475 800d438: 0800d475 .word 0x0800d475 800d43c: 0800d475 .word 0x0800d475 case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d440: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d444: 3308 adds r3, #8 800d446: 2101 movs r1, #1 800d448: 4618 mov r0, r3 800d44a: f001 fe27 bl 800f09c 800d44e: 4603 mov r3, r0 800d450: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d454: e00f b.n 800d476 case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d456: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d45a: 3328 adds r3, #40 @ 0x28 800d45c: 2101 movs r1, #1 800d45e: 4618 mov r0, r3 800d460: f001 fece bl 800f200 800d464: 4603 mov r3, r0 800d466: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; 800d46a: e004 b.n 800d476 /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d46c: 2301 movs r3, #1 800d46e: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d472: e000 b.n 800d476 break; 800d474: bf00 nop } if (ret == HAL_OK) 800d476: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d47a: 2b00 cmp r3, #0 800d47c: d10a bne.n 800d494 { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); 800d47e: 4b96 ldr r3, [pc, #600] @ (800d6d8 ) 800d480: 6d5b ldr r3, [r3, #84] @ 0x54 800d482: f023 0107 bic.w r1, r3, #7 800d486: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d48a: 6f9b ldr r3, [r3, #120] @ 0x78 800d48c: 4a92 ldr r2, [pc, #584] @ (800d6d8 ) 800d48e: 430b orrs r3, r1 800d490: 6553 str r3, [r2, #84] @ 0x54 800d492: e003 b.n 800d49c } else { /* set overall return value */ status = ret; 800d494: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d498: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*-------------------------- LPUART1 Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 800d49c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4a0: e9d3 2300 ldrd r2, r3, [r3] 800d4a4: f002 0304 and.w r3, r2, #4 800d4a8: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 800d4ac: 2300 movs r3, #0 800d4ae: f8c7 30ac str.w r3, [r7, #172] @ 0xac 800d4b2: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 800d4b6: 460b mov r3, r1 800d4b8: 4313 orrs r3, r2 800d4ba: d044 beq.n 800d546 { switch (PeriphClkInit->Lpuart1ClockSelection) 800d4bc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4c0: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d4c4: 2b05 cmp r3, #5 800d4c6: d825 bhi.n 800d514 800d4c8: a201 add r2, pc, #4 @ (adr r2, 800d4d0 ) 800d4ca: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800d4ce: bf00 nop 800d4d0: 0800d51d .word 0x0800d51d 800d4d4: 0800d4e9 .word 0x0800d4e9 800d4d8: 0800d4ff .word 0x0800d4ff 800d4dc: 0800d51d .word 0x0800d51d 800d4e0: 0800d51d .word 0x0800d51d 800d4e4: 0800d51d .word 0x0800d51d case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ /* LPUART1 clock source configuration done later after clock selection check */ break; case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800d4e8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d4ec: 3308 adds r3, #8 800d4ee: 2101 movs r1, #1 800d4f0: 4618 mov r0, r3 800d4f2: f001 fdd3 bl 800f09c 800d4f6: 4603 mov r3, r0 800d4f8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d4fc: e00f b.n 800d51e case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d4fe: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d502: 3328 adds r3, #40 @ 0x28 800d504: 2101 movs r1, #1 800d506: 4618 mov r0, r3 800d508: f001 fe7a bl 800f200 800d50c: 4603 mov r3, r0 800d50e: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPUART1 clock source configuration done later after clock selection check */ break; 800d512: e004 b.n 800d51e /* LSE, oscillator is used as source of LPUART1 clock */ /* LPUART1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d514: 2301 movs r3, #1 800d516: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d51a: e000 b.n 800d51e break; 800d51c: bf00 nop } if (ret == HAL_OK) 800d51e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d522: 2b00 cmp r3, #0 800d524: d10b bne.n 800d53e { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 800d526: 4b6c ldr r3, [pc, #432] @ (800d6d8 ) 800d528: 6d9b ldr r3, [r3, #88] @ 0x58 800d52a: f023 0107 bic.w r1, r3, #7 800d52e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d532: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94 800d536: 4a68 ldr r2, [pc, #416] @ (800d6d8 ) 800d538: 430b orrs r3, r1 800d53a: 6593 str r3, [r2, #88] @ 0x58 800d53c: e003 b.n 800d546 } else { /* set overall return value */ status = ret; 800d53e: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d542: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM1 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) 800d546: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d54a: e9d3 2300 ldrd r2, r3, [r3] 800d54e: f002 0320 and.w r3, r2, #32 800d552: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800d556: 2300 movs r3, #0 800d558: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 800d55c: e9d7 1228 ldrd r1, r2, [r7, #160] @ 0xa0 800d560: 460b mov r3, r1 800d562: 4313 orrs r3, r2 800d564: d055 beq.n 800d612 { switch (PeriphClkInit->Lptim1ClockSelection) 800d566: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d56a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d56e: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d572: d033 beq.n 800d5dc 800d574: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800d578: d82c bhi.n 800d5d4 800d57a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d57e: d02f beq.n 800d5e0 800d580: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800d584: d826 bhi.n 800d5d4 800d586: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d58a: d02b beq.n 800d5e4 800d58c: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800d590: d820 bhi.n 800d5d4 800d592: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d596: d012 beq.n 800d5be 800d598: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800d59c: d81a bhi.n 800d5d4 800d59e: 2b00 cmp r3, #0 800d5a0: d022 beq.n 800d5e8 800d5a2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800d5a6: d115 bne.n 800d5d4 /* LPTIM1 clock source configuration done later after clock selection check */ break; case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d5a8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5ac: 3308 adds r3, #8 800d5ae: 2100 movs r1, #0 800d5b0: 4618 mov r0, r3 800d5b2: f001 fd73 bl 800f09c 800d5b6: 4603 mov r3, r0 800d5b8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d5bc: e015 b.n 800d5ea case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d5be: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5c2: 3328 adds r3, #40 @ 0x28 800d5c4: 2102 movs r1, #2 800d5c6: 4618 mov r0, r3 800d5c8: f001 fe1a bl 800f200 800d5cc: 4603 mov r3, r0 800d5ce: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM1 clock source configuration done later after clock selection check */ break; 800d5d2: e00a b.n 800d5ea /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ /* LPTIM1 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d5d4: 2301 movs r3, #1 800d5d6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d5da: e006 b.n 800d5ea break; 800d5dc: bf00 nop 800d5de: e004 b.n 800d5ea break; 800d5e0: bf00 nop 800d5e2: e002 b.n 800d5ea break; 800d5e4: bf00 nop 800d5e6: e000 b.n 800d5ea break; 800d5e8: bf00 nop } if (ret == HAL_OK) 800d5ea: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d5ee: 2b00 cmp r3, #0 800d5f0: d10b bne.n 800d60a { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 800d5f2: 4b39 ldr r3, [pc, #228] @ (800d6d8 ) 800d5f4: 6d5b ldr r3, [r3, #84] @ 0x54 800d5f6: f023 41e0 bic.w r1, r3, #1879048192 @ 0x70000000 800d5fa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d5fe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 800d602: 4a35 ldr r2, [pc, #212] @ (800d6d8 ) 800d604: 430b orrs r3, r1 800d606: 6553 str r3, [r2, #84] @ 0x54 800d608: e003 b.n 800d612 } else { /* set overall return value */ status = ret; 800d60a: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d60e: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) 800d612: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d616: e9d3 2300 ldrd r2, r3, [r3] 800d61a: f002 0340 and.w r3, r2, #64 @ 0x40 800d61e: f8c7 3098 str.w r3, [r7, #152] @ 0x98 800d622: 2300 movs r3, #0 800d624: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800d628: e9d7 1226 ldrd r1, r2, [r7, #152] @ 0x98 800d62c: 460b mov r3, r1 800d62e: 4313 orrs r3, r2 800d630: d058 beq.n 800d6e4 { switch (PeriphClkInit->Lptim2ClockSelection) 800d632: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d636: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d63a: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d63e: d033 beq.n 800d6a8 800d640: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400 800d644: d82c bhi.n 800d6a0 800d646: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d64a: d02f beq.n 800d6ac 800d64c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d650: d826 bhi.n 800d6a0 800d652: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d656: d02b beq.n 800d6b0 800d658: f5b3 6f40 cmp.w r3, #3072 @ 0xc00 800d65c: d820 bhi.n 800d6a0 800d65e: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d662: d012 beq.n 800d68a 800d664: f5b3 6f00 cmp.w r3, #2048 @ 0x800 800d668: d81a bhi.n 800d6a0 800d66a: 2b00 cmp r3, #0 800d66c: d022 beq.n 800d6b4 800d66e: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800d672: d115 bne.n 800d6a0 /* LPTIM2 clock source configuration done later after clock selection check */ break; case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d674: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d678: 3308 adds r3, #8 800d67a: 2100 movs r1, #0 800d67c: 4618 mov r0, r3 800d67e: f001 fd0d bl 800f09c 800d682: 4603 mov r3, r0 800d684: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d688: e015 b.n 800d6b6 case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d68a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d68e: 3328 adds r3, #40 @ 0x28 800d690: 2102 movs r1, #2 800d692: 4618 mov r0, r3 800d694: f001 fdb4 bl 800f200 800d698: 4603 mov r3, r0 800d69a: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM2 clock source configuration done later after clock selection check */ break; 800d69e: e00a b.n 800d6b6 /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ /* LPTIM2 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d6a0: 2301 movs r3, #1 800d6a2: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d6a6: e006 b.n 800d6b6 break; 800d6a8: bf00 nop 800d6aa: e004 b.n 800d6b6 break; 800d6ac: bf00 nop 800d6ae: e002 b.n 800d6b6 break; 800d6b0: bf00 nop 800d6b2: e000 b.n 800d6b6 break; 800d6b4: bf00 nop } if (ret == HAL_OK) 800d6b6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d6ba: 2b00 cmp r3, #0 800d6bc: d10e bne.n 800d6dc { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 800d6be: 4b06 ldr r3, [pc, #24] @ (800d6d8 ) 800d6c0: 6d9b ldr r3, [r3, #88] @ 0x58 800d6c2: f423 51e0 bic.w r1, r3, #7168 @ 0x1c00 800d6c6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6ca: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c 800d6ce: 4a02 ldr r2, [pc, #8] @ (800d6d8 ) 800d6d0: 430b orrs r3, r1 800d6d2: 6593 str r3, [r2, #88] @ 0x58 800d6d4: e006 b.n 800d6e4 800d6d6: bf00 nop 800d6d8: 58024400 .word 0x58024400 } else { /* set overall return value */ status = ret; 800d6dc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d6e0: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- LPTIM345 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) 800d6e4: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d6e8: e9d3 2300 ldrd r2, r3, [r3] 800d6ec: f002 0380 and.w r3, r2, #128 @ 0x80 800d6f0: f8c7 3090 str.w r3, [r7, #144] @ 0x90 800d6f4: 2300 movs r3, #0 800d6f6: f8c7 3094 str.w r3, [r7, #148] @ 0x94 800d6fa: e9d7 1224 ldrd r1, r2, [r7, #144] @ 0x90 800d6fe: 460b mov r3, r1 800d700: 4313 orrs r3, r2 800d702: d055 beq.n 800d7b0 { switch (PeriphClkInit->Lptim345ClockSelection) 800d704: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d708: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d70c: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d710: d033 beq.n 800d77a 800d712: f5b3 4f20 cmp.w r3, #40960 @ 0xa000 800d716: d82c bhi.n 800d772 800d718: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d71c: d02f beq.n 800d77e 800d71e: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 800d722: d826 bhi.n 800d772 800d724: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d728: d02b beq.n 800d782 800d72a: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000 800d72e: d820 bhi.n 800d772 800d730: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d734: d012 beq.n 800d75c 800d736: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800d73a: d81a bhi.n 800d772 800d73c: 2b00 cmp r3, #0 800d73e: d022 beq.n 800d786 800d740: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800d744: d115 bne.n 800d772 case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d746: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d74a: 3308 adds r3, #8 800d74c: 2100 movs r1, #0 800d74e: 4618 mov r0, r3 800d750: f001 fca4 bl 800f09c 800d754: 4603 mov r3, r0 800d756: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d75a: e015 b.n 800d788 case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d75c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d760: 3328 adds r3, #40 @ 0x28 800d762: 2102 movs r1, #2 800d764: 4618 mov r0, r3 800d766: f001 fd4b bl 800f200 800d76a: 4603 mov r3, r0 800d76c: f887 311f strb.w r3, [r7, #287] @ 0x11f /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; 800d770: e00a b.n 800d788 /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ /* LPTIM3/4/5 clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d772: 2301 movs r3, #1 800d774: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d778: e006 b.n 800d788 break; 800d77a: bf00 nop 800d77c: e004 b.n 800d788 break; 800d77e: bf00 nop 800d780: e002 b.n 800d788 break; 800d782: bf00 nop 800d784: e000 b.n 800d788 break; 800d786: bf00 nop } if (ret == HAL_OK) 800d788: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d78c: 2b00 cmp r3, #0 800d78e: d10b bne.n 800d7a8 { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); 800d790: 4bbb ldr r3, [pc, #748] @ (800da80 ) 800d792: 6d9b ldr r3, [r3, #88] @ 0x58 800d794: f423 4160 bic.w r1, r3, #57344 @ 0xe000 800d798: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d79c: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 800d7a0: 4ab7 ldr r2, [pc, #732] @ (800da80 ) 800d7a2: 430b orrs r3, r1 800d7a4: 6593 str r3, [r2, #88] @ 0x58 800d7a6: e003 b.n 800d7b0 } else { /* set overall return value */ status = ret; 800d7a8: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d7ac: f887 311e strb.w r3, [r7, #286] @ 0x11e __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) 800d7b0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7b4: e9d3 2300 ldrd r2, r3, [r3] 800d7b8: f002 0308 and.w r3, r2, #8 800d7bc: f8c7 3088 str.w r3, [r7, #136] @ 0x88 800d7c0: 2300 movs r3, #0 800d7c2: f8c7 308c str.w r3, [r7, #140] @ 0x8c 800d7c6: e9d7 1222 ldrd r1, r2, [r7, #136] @ 0x88 800d7ca: 460b mov r3, r1 800d7cc: 4313 orrs r3, r2 800d7ce: d01e beq.n 800d80e { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) 800d7d0: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7d4: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d7d8: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800d7dc: d10c bne.n 800d7f8 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d7de: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d7e2: 3328 adds r3, #40 @ 0x28 800d7e4: 2102 movs r1, #2 800d7e6: 4618 mov r0, r3 800d7e8: f001 fd0a bl 800f200 800d7ec: 4603 mov r3, r0 800d7ee: 2b00 cmp r3, #0 800d7f0: d002 beq.n 800d7f8 { status = HAL_ERROR; 800d7f2: 2301 movs r3, #1 800d7f4: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); 800d7f8: 4ba1 ldr r3, [pc, #644] @ (800da80 ) 800d7fa: 6d5b ldr r3, [r3, #84] @ 0x54 800d7fc: f423 5140 bic.w r1, r3, #12288 @ 0x3000 800d800: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d804: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 800d808: 4a9d ldr r2, [pc, #628] @ (800da80 ) 800d80a: 430b orrs r3, r1 800d80c: 6553 str r3, [r2, #84] @ 0x54 } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) 800d80e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d812: e9d3 2300 ldrd r2, r3, [r3] 800d816: f002 0310 and.w r3, r2, #16 800d81a: f8c7 3080 str.w r3, [r7, #128] @ 0x80 800d81e: 2300 movs r3, #0 800d820: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800d824: e9d7 1220 ldrd r1, r2, [r7, #128] @ 0x80 800d828: 460b mov r3, r1 800d82a: 4313 orrs r3, r2 800d82c: d01e beq.n 800d86c { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) 800d82e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d832: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d836: f5b3 7f80 cmp.w r3, #256 @ 0x100 800d83a: d10c bne.n 800d856 { if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) 800d83c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d840: 3328 adds r3, #40 @ 0x28 800d842: 2102 movs r1, #2 800d844: 4618 mov r0, r3 800d846: f001 fcdb bl 800f200 800d84a: 4603 mov r3, r0 800d84c: 2b00 cmp r3, #0 800d84e: d002 beq.n 800d856 { status = HAL_ERROR; 800d850: 2301 movs r3, #1 800d852: f887 311e strb.w r3, [r7, #286] @ 0x11e } } __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); 800d856: 4b8a ldr r3, [pc, #552] @ (800da80 ) 800d858: 6d9b ldr r3, [r3, #88] @ 0x58 800d85a: f423 7140 bic.w r1, r3, #768 @ 0x300 800d85e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d862: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98 800d866: 4a86 ldr r2, [pc, #536] @ (800da80 ) 800d868: 430b orrs r3, r1 800d86a: 6593 str r3, [r2, #88] @ 0x58 } /*---------------------------- ADC configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 800d86c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d870: e9d3 2300 ldrd r2, r3, [r3] 800d874: f402 2300 and.w r3, r2, #524288 @ 0x80000 800d878: 67bb str r3, [r7, #120] @ 0x78 800d87a: 2300 movs r3, #0 800d87c: 67fb str r3, [r7, #124] @ 0x7c 800d87e: e9d7 121e ldrd r1, r2, [r7, #120] @ 0x78 800d882: 460b mov r3, r1 800d884: 4313 orrs r3, r2 800d886: d03e beq.n 800d906 { switch (PeriphClkInit->AdcClockSelection) 800d888: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d88c: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d890: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d894: d022 beq.n 800d8dc 800d896: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800d89a: d81b bhi.n 800d8d4 800d89c: 2b00 cmp r3, #0 800d89e: d003 beq.n 800d8a8 800d8a0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d8a4: d00b beq.n 800d8be 800d8a6: e015 b.n 800d8d4 { case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800d8a8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8ac: 3308 adds r3, #8 800d8ae: 2100 movs r1, #0 800d8b0: 4618 mov r0, r3 800d8b2: f001 fbf3 bl 800f09c 800d8b6: 4603 mov r3, r0 800d8b8: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d8bc: e00f b.n 800d8de case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800d8be: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8c2: 3328 adds r3, #40 @ 0x28 800d8c4: 2102 movs r1, #2 800d8c6: 4618 mov r0, r3 800d8c8: f001 fc9a bl 800f200 800d8cc: 4603 mov r3, r0 800d8ce: f887 311f strb.w r3, [r7, #287] @ 0x11f /* ADC clock source configuration done later after clock selection check */ break; 800d8d2: e004 b.n 800d8de /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ /* ADC clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d8d4: 2301 movs r3, #1 800d8d6: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d8da: e000 b.n 800d8de break; 800d8dc: bf00 nop } if (ret == HAL_OK) 800d8de: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d8e2: 2b00 cmp r3, #0 800d8e4: d10b bne.n 800d8fe { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 800d8e6: 4b66 ldr r3, [pc, #408] @ (800da80 ) 800d8e8: 6d9b ldr r3, [r3, #88] @ 0x58 800d8ea: f423 3140 bic.w r1, r3, #196608 @ 0x30000 800d8ee: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d8f2: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 800d8f6: 4a62 ldr r2, [pc, #392] @ (800da80 ) 800d8f8: 430b orrs r3, r1 800d8fa: 6593 str r3, [r2, #88] @ 0x58 800d8fc: e003 b.n 800d906 } else { /* set overall return value */ status = ret; 800d8fe: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d902: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ USB Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) 800d906: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d90a: e9d3 2300 ldrd r2, r3, [r3] 800d90e: f402 2380 and.w r3, r2, #262144 @ 0x40000 800d912: 673b str r3, [r7, #112] @ 0x70 800d914: 2300 movs r3, #0 800d916: 677b str r3, [r7, #116] @ 0x74 800d918: e9d7 121c ldrd r1, r2, [r7, #112] @ 0x70 800d91c: 460b mov r3, r1 800d91e: 4313 orrs r3, r2 800d920: d03b beq.n 800d99a { switch (PeriphClkInit->UsbClockSelection) 800d922: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d926: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d92a: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d92e: d01f beq.n 800d970 800d930: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000 800d934: d818 bhi.n 800d968 800d936: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 800d93a: d003 beq.n 800d944 800d93c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800d940: d007 beq.n 800d952 800d942: e011 b.n 800d968 { case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ /* Enable USB Clock output generated form System USB . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d944: 4b4e ldr r3, [pc, #312] @ (800da80 ) 800d946: 6adb ldr r3, [r3, #44] @ 0x2c 800d948: 4a4d ldr r2, [pc, #308] @ (800da80 ) 800d94a: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d94e: 62d3 str r3, [r2, #44] @ 0x2c /* USB clock source configuration done later after clock selection check */ break; 800d950: e00f b.n 800d972 case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800d952: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d956: 3328 adds r3, #40 @ 0x28 800d958: 2101 movs r1, #1 800d95a: 4618 mov r0, r3 800d95c: f001 fc50 bl 800f200 800d960: 4603 mov r3, r0 800d962: f887 311f strb.w r3, [r7, #287] @ 0x11f /* USB clock source configuration done later after clock selection check */ break; 800d966: e004 b.n 800d972 /* HSI48 oscillator is used as source of USB clock */ /* USB clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800d968: 2301 movs r3, #1 800d96a: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d96e: e000 b.n 800d972 break; 800d970: bf00 nop } if (ret == HAL_OK) 800d972: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d976: 2b00 cmp r3, #0 800d978: d10b bne.n 800d992 { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800d97a: 4b41 ldr r3, [pc, #260] @ (800da80 ) 800d97c: 6d5b ldr r3, [r3, #84] @ 0x54 800d97e: f423 1140 bic.w r1, r3, #3145728 @ 0x300000 800d982: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d986: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800d98a: 4a3d ldr r2, [pc, #244] @ (800da80 ) 800d98c: 430b orrs r3, r1 800d98e: 6553 str r3, [r2, #84] @ 0x54 800d990: e003 b.n 800d99a } else { /* set overall return value */ status = ret; 800d992: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d996: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------------- SDMMC Configuration ------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) 800d99a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d99e: e9d3 2300 ldrd r2, r3, [r3] 800d9a2: f402 3380 and.w r3, r2, #65536 @ 0x10000 800d9a6: 66bb str r3, [r7, #104] @ 0x68 800d9a8: 2300 movs r3, #0 800d9aa: 66fb str r3, [r7, #108] @ 0x6c 800d9ac: e9d7 121a ldrd r1, r2, [r7, #104] @ 0x68 800d9b0: 460b mov r3, r1 800d9b2: 4313 orrs r3, r2 800d9b4: d031 beq.n 800da1a { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); switch (PeriphClkInit->SdmmcClockSelection) 800d9b6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9ba: 6d1b ldr r3, [r3, #80] @ 0x50 800d9bc: 2b00 cmp r3, #0 800d9be: d003 beq.n 800d9c8 800d9c0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800d9c4: d007 beq.n 800d9d6 800d9c6: e011 b.n 800d9ec { case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ /* Enable SDMMC Clock output generated form System PLL . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800d9c8: 4b2d ldr r3, [pc, #180] @ (800da80 ) 800d9ca: 6adb ldr r3, [r3, #44] @ 0x2c 800d9cc: 4a2c ldr r2, [pc, #176] @ (800da80 ) 800d9ce: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800d9d2: 62d3 str r3, [r2, #44] @ 0x2c /* SDMMC clock source configuration done later after clock selection check */ break; 800d9d4: e00e b.n 800d9f4 case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800d9d6: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800d9da: 3308 adds r3, #8 800d9dc: 2102 movs r1, #2 800d9de: 4618 mov r0, r3 800d9e0: f001 fb5c bl 800f09c 800d9e4: 4603 mov r3, r0 800d9e6: f887 311f strb.w r3, [r7, #287] @ 0x11f /* SDMMC clock source configuration done later after clock selection check */ break; 800d9ea: e003 b.n 800d9f4 default: ret = HAL_ERROR; 800d9ec: 2301 movs r3, #1 800d9ee: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800d9f2: bf00 nop } if (ret == HAL_OK) 800d9f4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800d9f8: 2b00 cmp r3, #0 800d9fa: d10a bne.n 800da12 { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); 800d9fc: 4b20 ldr r3, [pc, #128] @ (800da80 ) 800d9fe: 6cdb ldr r3, [r3, #76] @ 0x4c 800da00: f423 3180 bic.w r1, r3, #65536 @ 0x10000 800da04: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da08: 6d1b ldr r3, [r3, #80] @ 0x50 800da0a: 4a1d ldr r2, [pc, #116] @ (800da80 ) 800da0c: 430b orrs r3, r1 800da0e: 64d3 str r3, [r2, #76] @ 0x4c 800da10: e003 b.n 800da1a } else { /* set overall return value */ status = ret; 800da12: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da16: f887 311e strb.w r3, [r7, #286] @ 0x11e } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) 800da1a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da1e: e9d3 2300 ldrd r2, r3, [r3] 800da22: f402 3300 and.w r3, r2, #131072 @ 0x20000 800da26: 663b str r3, [r7, #96] @ 0x60 800da28: 2300 movs r3, #0 800da2a: 667b str r3, [r7, #100] @ 0x64 800da2c: e9d7 1218 ldrd r1, r2, [r7, #96] @ 0x60 800da30: 460b mov r3, r1 800da32: 4313 orrs r3, r2 800da34: d03b beq.n 800daae { switch (PeriphClkInit->RngClockSelection) 800da36: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da3a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800da3e: f5b3 7f40 cmp.w r3, #768 @ 0x300 800da42: d018 beq.n 800da76 800da44: f5b3 7f40 cmp.w r3, #768 @ 0x300 800da48: d811 bhi.n 800da6e 800da4a: f5b3 7f00 cmp.w r3, #512 @ 0x200 800da4e: d014 beq.n 800da7a 800da50: f5b3 7f00 cmp.w r3, #512 @ 0x200 800da54: d80b bhi.n 800da6e 800da56: 2b00 cmp r3, #0 800da58: d014 beq.n 800da84 800da5a: f5b3 7f80 cmp.w r3, #256 @ 0x100 800da5e: d106 bne.n 800da6e { case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ /* Enable RNG Clock output generated form System RNG . */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); 800da60: 4b07 ldr r3, [pc, #28] @ (800da80 ) 800da62: 6adb ldr r3, [r3, #44] @ 0x2c 800da64: 4a06 ldr r2, [pc, #24] @ (800da80 ) 800da66: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800da6a: 62d3 str r3, [r2, #44] @ 0x2c /* RNG clock source configuration done later after clock selection check */ break; 800da6c: e00b b.n 800da86 /* HSI48 oscillator is used as source of RNG clock */ /* RNG clock source configuration done later after clock selection check */ break; default: ret = HAL_ERROR; 800da6e: 2301 movs r3, #1 800da70: f887 311f strb.w r3, [r7, #287] @ 0x11f break; 800da74: e007 b.n 800da86 break; 800da76: bf00 nop 800da78: e005 b.n 800da86 break; 800da7a: bf00 nop 800da7c: e003 b.n 800da86 800da7e: bf00 nop 800da80: 58024400 .word 0x58024400 break; 800da84: bf00 nop } if (ret == HAL_OK) 800da86: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800da8a: 2b00 cmp r3, #0 800da8c: d10b bne.n 800daa6 { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 800da8e: 4bba ldr r3, [pc, #744] @ (800dd78 ) 800da90: 6d5b ldr r3, [r3, #84] @ 0x54 800da92: f423 7140 bic.w r1, r3, #768 @ 0x300 800da96: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800da9a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 800da9e: 4ab6 ldr r2, [pc, #728] @ (800dd78 ) 800daa0: 430b orrs r3, r1 800daa2: 6553 str r3, [r2, #84] @ 0x54 800daa4: e003 b.n 800daae } else { /* set overall return value */ status = ret; 800daa6: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800daaa: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*------------------------------ SWPMI1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800daae: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dab2: e9d3 2300 ldrd r2, r3, [r3] 800dab6: f402 1380 and.w r3, r2, #1048576 @ 0x100000 800daba: 65bb str r3, [r7, #88] @ 0x58 800dabc: 2300 movs r3, #0 800dabe: 65fb str r3, [r7, #92] @ 0x5c 800dac0: e9d7 1216 ldrd r1, r2, [r7, #88] @ 0x58 800dac4: 460b mov r3, r1 800dac6: 4313 orrs r3, r2 800dac8: d009 beq.n 800dade { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 interface clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 800daca: 4bab ldr r3, [pc, #684] @ (800dd78 ) 800dacc: 6d1b ldr r3, [r3, #80] @ 0x50 800dace: f023 4100 bic.w r1, r3, #2147483648 @ 0x80000000 800dad2: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dad6: 6f5b ldr r3, [r3, #116] @ 0x74 800dad8: 4aa7 ldr r2, [pc, #668] @ (800dd78 ) 800dada: 430b orrs r3, r1 800dadc: 6513 str r3, [r2, #80] @ 0x50 } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) 800dade: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dae2: e9d3 2300 ldrd r2, r3, [r3] 800dae6: f002 5380 and.w r3, r2, #268435456 @ 0x10000000 800daea: 653b str r3, [r7, #80] @ 0x50 800daec: 2300 movs r3, #0 800daee: 657b str r3, [r7, #84] @ 0x54 800daf0: e9d7 1214 ldrd r1, r2, [r7, #80] @ 0x50 800daf4: 460b mov r3, r1 800daf6: 4313 orrs r3, r2 800daf8: d00a beq.n 800db10 { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); /* Configure the HRTIM1 clock source */ __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); 800dafa: 4b9f ldr r3, [pc, #636] @ (800dd78 ) 800dafc: 691b ldr r3, [r3, #16] 800dafe: f423 4180 bic.w r1, r3, #16384 @ 0x4000 800db02: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db06: f8d3 30b8 ldr.w r3, [r3, #184] @ 0xb8 800db0a: 4a9b ldr r2, [pc, #620] @ (800dd78 ) 800db0c: 430b orrs r3, r1 800db0e: 6113 str r3, [r2, #16] } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) 800db10: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db14: e9d3 2300 ldrd r2, r3, [r3] 800db18: f402 1300 and.w r3, r2, #2097152 @ 0x200000 800db1c: 64bb str r3, [r7, #72] @ 0x48 800db1e: 2300 movs r3, #0 800db20: 64fb str r3, [r7, #76] @ 0x4c 800db22: e9d7 1212 ldrd r1, r2, [r7, #72] @ 0x48 800db26: 460b mov r3, r1 800db28: 4313 orrs r3, r2 800db2a: d009 beq.n 800db40 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); 800db2c: 4b92 ldr r3, [pc, #584] @ (800dd78 ) 800db2e: 6d1b ldr r3, [r3, #80] @ 0x50 800db30: f023 7180 bic.w r1, r3, #16777216 @ 0x1000000 800db34: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db38: 6edb ldr r3, [r3, #108] @ 0x6c 800db3a: 4a8f ldr r2, [pc, #572] @ (800dd78 ) 800db3c: 430b orrs r3, r1 800db3e: 6513 str r3, [r2, #80] @ 0x50 __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); } #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) 800db40: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db44: e9d3 2300 ldrd r2, r3, [r3] 800db48: f002 4380 and.w r3, r2, #1073741824 @ 0x40000000 800db4c: 643b str r3, [r7, #64] @ 0x40 800db4e: 2300 movs r3, #0 800db50: 647b str r3, [r7, #68] @ 0x44 800db52: e9d7 1210 ldrd r1, r2, [r7, #64] @ 0x40 800db56: 460b mov r3, r1 800db58: 4313 orrs r3, r2 800db5a: d00e beq.n 800db7a { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800db5c: 4b86 ldr r3, [pc, #536] @ (800dd78 ) 800db5e: 691b ldr r3, [r3, #16] 800db60: 4a85 ldr r2, [pc, #532] @ (800dd78 ) 800db62: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800db66: 6113 str r3, [r2, #16] 800db68: 4b83 ldr r3, [pc, #524] @ (800dd78 ) 800db6a: 6919 ldr r1, [r3, #16] 800db6c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db70: f8d3 30bc ldr.w r3, [r3, #188] @ 0xbc 800db74: 4a80 ldr r2, [pc, #512] @ (800dd78 ) 800db76: 430b orrs r3, r1 800db78: 6113 str r3, [r2, #16] } /*------------------------------------ CKPER configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) 800db7a: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800db7e: e9d3 2300 ldrd r2, r3, [r3] 800db82: f002 4300 and.w r3, r2, #2147483648 @ 0x80000000 800db86: 63bb str r3, [r7, #56] @ 0x38 800db88: 2300 movs r3, #0 800db8a: 63fb str r3, [r7, #60] @ 0x3c 800db8c: e9d7 120e ldrd r1, r2, [r7, #56] @ 0x38 800db90: 460b mov r3, r1 800db92: 4313 orrs r3, r2 800db94: d009 beq.n 800dbaa { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); /* Configure the CKPER clock source */ __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); 800db96: 4b78 ldr r3, [pc, #480] @ (800dd78 ) 800db98: 6cdb ldr r3, [r3, #76] @ 0x4c 800db9a: f023 5140 bic.w r1, r3, #805306368 @ 0x30000000 800db9e: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dba2: 6d5b ldr r3, [r3, #84] @ 0x54 800dba4: 4a74 ldr r2, [pc, #464] @ (800dd78 ) 800dba6: 430b orrs r3, r1 800dba8: 64d3 str r3, [r2, #76] @ 0x4c } /*------------------------------ CEC Configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) 800dbaa: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbae: e9d3 2300 ldrd r2, r3, [r3] 800dbb2: f402 0300 and.w r3, r2, #8388608 @ 0x800000 800dbb6: 633b str r3, [r7, #48] @ 0x30 800dbb8: 2300 movs r3, #0 800dbba: 637b str r3, [r7, #52] @ 0x34 800dbbc: e9d7 120c ldrd r1, r2, [r7, #48] @ 0x30 800dbc0: 460b mov r3, r1 800dbc2: 4313 orrs r3, r2 800dbc4: d00a beq.n 800dbdc { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC interface clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); 800dbc6: 4b6c ldr r3, [pc, #432] @ (800dd78 ) 800dbc8: 6d5b ldr r3, [r3, #84] @ 0x54 800dbca: f423 0140 bic.w r1, r3, #12582912 @ 0xc00000 800dbce: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbd2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 800dbd6: 4a68 ldr r2, [pc, #416] @ (800dd78 ) 800dbd8: 430b orrs r3, r1 800dbda: 6553 str r3, [r2, #84] @ 0x54 } /*---------------------------- PLL2 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) 800dbdc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbe0: e9d3 2300 ldrd r2, r3, [r3] 800dbe4: 2100 movs r1, #0 800dbe6: 62b9 str r1, [r7, #40] @ 0x28 800dbe8: f003 0301 and.w r3, r3, #1 800dbec: 62fb str r3, [r7, #44] @ 0x2c 800dbee: e9d7 120a ldrd r1, r2, [r7, #40] @ 0x28 800dbf2: 460b mov r3, r1 800dbf4: 4313 orrs r3, r2 800dbf6: d011 beq.n 800dc1c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); 800dbf8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dbfc: 3308 adds r3, #8 800dbfe: 2100 movs r1, #0 800dc00: 4618 mov r0, r3 800dc02: f001 fa4b bl 800f09c 800dc06: 4603 mov r3, r0 800dc08: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc0c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc10: 2b00 cmp r3, #0 800dc12: d003 beq.n 800dc1c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc14: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc18: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) 800dc1c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc20: e9d3 2300 ldrd r2, r3, [r3] 800dc24: 2100 movs r1, #0 800dc26: 6239 str r1, [r7, #32] 800dc28: f003 0302 and.w r3, r3, #2 800dc2c: 627b str r3, [r7, #36] @ 0x24 800dc2e: e9d7 1208 ldrd r1, r2, [r7, #32] 800dc32: 460b mov r3, r1 800dc34: 4313 orrs r3, r2 800dc36: d011 beq.n 800dc5c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); 800dc38: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc3c: 3308 adds r3, #8 800dc3e: 2101 movs r1, #1 800dc40: 4618 mov r0, r3 800dc42: f001 fa2b bl 800f09c 800dc46: 4603 mov r3, r0 800dc48: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc4c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc50: 2b00 cmp r3, #0 800dc52: d003 beq.n 800dc5c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc54: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc58: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) 800dc5c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc60: e9d3 2300 ldrd r2, r3, [r3] 800dc64: 2100 movs r1, #0 800dc66: 61b9 str r1, [r7, #24] 800dc68: f003 0304 and.w r3, r3, #4 800dc6c: 61fb str r3, [r7, #28] 800dc6e: e9d7 1206 ldrd r1, r2, [r7, #24] 800dc72: 460b mov r3, r1 800dc74: 4313 orrs r3, r2 800dc76: d011 beq.n 800dc9c { ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); 800dc78: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dc7c: 3308 adds r3, #8 800dc7e: 2102 movs r1, #2 800dc80: 4618 mov r0, r3 800dc82: f001 fa0b bl 800f09c 800dc86: 4603 mov r3, r0 800dc88: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dc8c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc90: 2b00 cmp r3, #0 800dc92: d003 beq.n 800dc9c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dc94: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dc98: f887 311e strb.w r3, [r7, #286] @ 0x11e } } /*---------------------------- PLL3 configuration -------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) 800dc9c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dca0: e9d3 2300 ldrd r2, r3, [r3] 800dca4: 2100 movs r1, #0 800dca6: 6139 str r1, [r7, #16] 800dca8: f003 0308 and.w r3, r3, #8 800dcac: 617b str r3, [r7, #20] 800dcae: e9d7 1204 ldrd r1, r2, [r7, #16] 800dcb2: 460b mov r3, r1 800dcb4: 4313 orrs r3, r2 800dcb6: d011 beq.n 800dcdc { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); 800dcb8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcbc: 3328 adds r3, #40 @ 0x28 800dcbe: 2100 movs r1, #0 800dcc0: 4618 mov r0, r3 800dcc2: f001 fa9d bl 800f200 800dcc6: 4603 mov r3, r0 800dcc8: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dccc: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dcd0: 2b00 cmp r3, #0 800dcd2: d003 beq.n 800dcdc /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dcd4: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dcd8: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) 800dcdc: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dce0: e9d3 2300 ldrd r2, r3, [r3] 800dce4: 2100 movs r1, #0 800dce6: 60b9 str r1, [r7, #8] 800dce8: f003 0310 and.w r3, r3, #16 800dcec: 60fb str r3, [r7, #12] 800dcee: e9d7 1202 ldrd r1, r2, [r7, #8] 800dcf2: 460b mov r3, r1 800dcf4: 4313 orrs r3, r2 800dcf6: d011 beq.n 800dd1c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); 800dcf8: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dcfc: 3328 adds r3, #40 @ 0x28 800dcfe: 2101 movs r1, #1 800dd00: 4618 mov r0, r3 800dd02: f001 fa7d bl 800f200 800dd06: 4603 mov r3, r0 800dd08: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dd0c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd10: 2b00 cmp r3, #0 800dd12: d003 beq.n 800dd1c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dd14: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd18: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) 800dd1c: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd20: e9d3 2300 ldrd r2, r3, [r3] 800dd24: 2100 movs r1, #0 800dd26: 6039 str r1, [r7, #0] 800dd28: f003 0320 and.w r3, r3, #32 800dd2c: 607b str r3, [r7, #4] 800dd2e: e9d7 1200 ldrd r1, r2, [r7] 800dd32: 460b mov r3, r1 800dd34: 4313 orrs r3, r2 800dd36: d011 beq.n 800dd5c { ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); 800dd38: f8d7 310c ldr.w r3, [r7, #268] @ 0x10c 800dd3c: 3328 adds r3, #40 @ 0x28 800dd3e: 2102 movs r1, #2 800dd40: 4618 mov r0, r3 800dd42: f001 fa5d bl 800f200 800dd46: 4603 mov r3, r0 800dd48: f887 311f strb.w r3, [r7, #287] @ 0x11f if (ret == HAL_OK) 800dd4c: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd50: 2b00 cmp r3, #0 800dd52: d003 beq.n 800dd5c /*Nothing to do*/ } else { /* set overall return value */ status = ret; 800dd54: f897 311f ldrb.w r3, [r7, #287] @ 0x11f 800dd58: f887 311e strb.w r3, [r7, #286] @ 0x11e } } if (status == HAL_OK) 800dd5c: f897 311e ldrb.w r3, [r7, #286] @ 0x11e 800dd60: 2b00 cmp r3, #0 800dd62: d101 bne.n 800dd68 { return HAL_OK; 800dd64: 2300 movs r3, #0 800dd66: e000 b.n 800dd6a } return HAL_ERROR; 800dd68: 2301 movs r3, #1 } 800dd6a: 4618 mov r0, r3 800dd6c: f507 7790 add.w r7, r7, #288 @ 0x120 800dd70: 46bd mov sp, r7 800dd72: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800dd76: bf00 nop 800dd78: 58024400 .word 0x58024400 0800dd7c : * @retval Frequency in KHz * * (*) : Available on some STM32H7 lines only. */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { 800dd7c: b580 push {r7, lr} 800dd7e: b090 sub sp, #64 @ 0x40 800dd80: af00 add r7, sp, #0 800dd82: e9c7 0100 strd r0, r1, [r7] /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; uint32_t ckpclocksource; uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) 800dd86: e9d7 2300 ldrd r2, r3, [r7] 800dd8a: f5a2 7180 sub.w r1, r2, #256 @ 0x100 800dd8e: 430b orrs r3, r1 800dd90: f040 8094 bne.w 800debc { saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); 800dd94: 4b9e ldr r3, [pc, #632] @ (800e010 ) 800dd96: 6d1b ldr r3, [r3, #80] @ 0x50 800dd98: f003 0307 and.w r3, r3, #7 800dd9c: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800dd9e: 6b3b ldr r3, [r7, #48] @ 0x30 800dda0: 2b04 cmp r3, #4 800dda2: f200 8087 bhi.w 800deb4 800dda6: a201 add r2, pc, #4 @ (adr r2, 800ddac ) 800dda8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800ddac: 0800ddc1 .word 0x0800ddc1 800ddb0: 0800dde9 .word 0x0800dde9 800ddb4: 0800de11 .word 0x0800de11 800ddb8: 0800dead .word 0x0800dead 800ddbc: 0800de39 .word 0x0800de39 { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800ddc0: 4b93 ldr r3, [pc, #588] @ (800e010 ) 800ddc2: 681b ldr r3, [r3, #0] 800ddc4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800ddc8: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800ddcc: d108 bne.n 800dde0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800ddce: f107 0324 add.w r3, r7, #36 @ 0x24 800ddd2: 4618 mov r0, r3 800ddd4: f001 f810 bl 800edf8 frequency = pll1_clocks.PLL1_Q_Frequency; 800ddd8: 6abb ldr r3, [r7, #40] @ 0x28 800ddda: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800dddc: f000 bd45 b.w 800e86a frequency = 0; 800dde0: 2300 movs r3, #0 800dde2: 63fb str r3, [r7, #60] @ 0x3c break; 800dde4: f000 bd41 b.w 800e86a } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800dde8: 4b89 ldr r3, [pc, #548] @ (800e010 ) 800ddea: 681b ldr r3, [r3, #0] 800ddec: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800ddf0: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800ddf4: d108 bne.n 800de08 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800ddf6: f107 0318 add.w r3, r7, #24 800ddfa: 4618 mov r0, r3 800ddfc: f000 fd54 bl 800e8a8 frequency = pll2_clocks.PLL2_P_Frequency; 800de00: 69bb ldr r3, [r7, #24] 800de02: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de04: f000 bd31 b.w 800e86a frequency = 0; 800de08: 2300 movs r3, #0 800de0a: 63fb str r3, [r7, #60] @ 0x3c break; 800de0c: f000 bd2d b.w 800e86a } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800de10: 4b7f ldr r3, [pc, #508] @ (800e010 ) 800de12: 681b ldr r3, [r3, #0] 800de14: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800de18: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800de1c: d108 bne.n 800de30 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800de1e: f107 030c add.w r3, r7, #12 800de22: 4618 mov r0, r3 800de24: f000 fe94 bl 800eb50 frequency = pll3_clocks.PLL3_P_Frequency; 800de28: 68fb ldr r3, [r7, #12] 800de2a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800de2c: f000 bd1d b.w 800e86a frequency = 0; 800de30: 2300 movs r3, #0 800de32: 63fb str r3, [r7, #60] @ 0x3c break; 800de34: f000 bd19 b.w 800e86a } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800de38: 4b75 ldr r3, [pc, #468] @ (800e010 ) 800de3a: 6cdb ldr r3, [r3, #76] @ 0x4c 800de3c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800de40: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800de42: 4b73 ldr r3, [pc, #460] @ (800e010 ) 800de44: 681b ldr r3, [r3, #0] 800de46: f003 0304 and.w r3, r3, #4 800de4a: 2b04 cmp r3, #4 800de4c: d10c bne.n 800de68 800de4e: 6b7b ldr r3, [r7, #52] @ 0x34 800de50: 2b00 cmp r3, #0 800de52: d109 bne.n 800de68 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800de54: 4b6e ldr r3, [pc, #440] @ (800e010 ) 800de56: 681b ldr r3, [r3, #0] 800de58: 08db lsrs r3, r3, #3 800de5a: f003 0303 and.w r3, r3, #3 800de5e: 4a6d ldr r2, [pc, #436] @ (800e014 ) 800de60: fa22 f303 lsr.w r3, r2, r3 800de64: 63fb str r3, [r7, #60] @ 0x3c 800de66: e01f b.n 800dea8 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800de68: 4b69 ldr r3, [pc, #420] @ (800e010 ) 800de6a: 681b ldr r3, [r3, #0] 800de6c: f403 7380 and.w r3, r3, #256 @ 0x100 800de70: f5b3 7f80 cmp.w r3, #256 @ 0x100 800de74: d106 bne.n 800de84 800de76: 6b7b ldr r3, [r7, #52] @ 0x34 800de78: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800de7c: d102 bne.n 800de84 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800de7e: 4b66 ldr r3, [pc, #408] @ (800e018 ) 800de80: 63fb str r3, [r7, #60] @ 0x3c 800de82: e011 b.n 800dea8 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800de84: 4b62 ldr r3, [pc, #392] @ (800e010 ) 800de86: 681b ldr r3, [r3, #0] 800de88: f403 3300 and.w r3, r3, #131072 @ 0x20000 800de8c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800de90: d106 bne.n 800dea0 800de92: 6b7b ldr r3, [r7, #52] @ 0x34 800de94: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800de98: d102 bne.n 800dea0 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800de9a: 4b60 ldr r3, [pc, #384] @ (800e01c ) 800de9c: 63fb str r3, [r7, #60] @ 0x3c 800de9e: e003 b.n 800dea8 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800dea0: 2300 movs r3, #0 800dea2: 63fb str r3, [r7, #60] @ 0x3c } break; 800dea4: f000 bce1 b.w 800e86a 800dea8: f000 bcdf b.w 800e86a } case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ { frequency = EXTERNAL_CLOCK_VALUE; 800deac: 4b5c ldr r3, [pc, #368] @ (800e020 ) 800deae: 63fb str r3, [r7, #60] @ 0x3c break; 800deb0: f000 bcdb b.w 800e86a } default : { frequency = 0; 800deb4: 2300 movs r3, #0 800deb6: 63fb str r3, [r7, #60] @ 0x3c break; 800deb8: f000 bcd7 b.w 800e86a } } } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) 800debc: e9d7 2300 ldrd r2, r3, [r7] 800dec0: f5a2 7100 sub.w r1, r2, #512 @ 0x200 800dec4: 430b orrs r3, r1 800dec6: f040 80ad bne.w 800e024 { saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); 800deca: 4b51 ldr r3, [pc, #324] @ (800e010 ) 800decc: 6d1b ldr r3, [r3, #80] @ 0x50 800dece: f403 73e0 and.w r3, r3, #448 @ 0x1c0 800ded2: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800ded4: 6b3b ldr r3, [r7, #48] @ 0x30 800ded6: f5b3 7f80 cmp.w r3, #256 @ 0x100 800deda: d056 beq.n 800df8a 800dedc: 6b3b ldr r3, [r7, #48] @ 0x30 800dede: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dee2: f200 8090 bhi.w 800e006 800dee6: 6b3b ldr r3, [r7, #48] @ 0x30 800dee8: 2bc0 cmp r3, #192 @ 0xc0 800deea: f000 8088 beq.w 800dffe 800deee: 6b3b ldr r3, [r7, #48] @ 0x30 800def0: 2bc0 cmp r3, #192 @ 0xc0 800def2: f200 8088 bhi.w 800e006 800def6: 6b3b ldr r3, [r7, #48] @ 0x30 800def8: 2b80 cmp r3, #128 @ 0x80 800defa: d032 beq.n 800df62 800defc: 6b3b ldr r3, [r7, #48] @ 0x30 800defe: 2b80 cmp r3, #128 @ 0x80 800df00: f200 8081 bhi.w 800e006 800df04: 6b3b ldr r3, [r7, #48] @ 0x30 800df06: 2b00 cmp r3, #0 800df08: d003 beq.n 800df12 800df0a: 6b3b ldr r3, [r7, #48] @ 0x30 800df0c: 2b40 cmp r3, #64 @ 0x40 800df0e: d014 beq.n 800df3a 800df10: e079 b.n 800e006 { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800df12: 4b3f ldr r3, [pc, #252] @ (800e010 ) 800df14: 681b ldr r3, [r3, #0] 800df16: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800df1a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800df1e: d108 bne.n 800df32 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800df20: f107 0324 add.w r3, r7, #36 @ 0x24 800df24: 4618 mov r0, r3 800df26: f000 ff67 bl 800edf8 frequency = pll1_clocks.PLL1_Q_Frequency; 800df2a: 6abb ldr r3, [r7, #40] @ 0x28 800df2c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df2e: f000 bc9c b.w 800e86a frequency = 0; 800df32: 2300 movs r3, #0 800df34: 63fb str r3, [r7, #60] @ 0x3c break; 800df36: f000 bc98 b.w 800e86a } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800df3a: 4b35 ldr r3, [pc, #212] @ (800e010 ) 800df3c: 681b ldr r3, [r3, #0] 800df3e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800df42: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800df46: d108 bne.n 800df5a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800df48: f107 0318 add.w r3, r7, #24 800df4c: 4618 mov r0, r3 800df4e: f000 fcab bl 800e8a8 frequency = pll2_clocks.PLL2_P_Frequency; 800df52: 69bb ldr r3, [r7, #24] 800df54: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df56: f000 bc88 b.w 800e86a frequency = 0; 800df5a: 2300 movs r3, #0 800df5c: 63fb str r3, [r7, #60] @ 0x3c break; 800df5e: f000 bc84 b.w 800e86a } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800df62: 4b2b ldr r3, [pc, #172] @ (800e010 ) 800df64: 681b ldr r3, [r3, #0] 800df66: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800df6a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800df6e: d108 bne.n 800df82 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800df70: f107 030c add.w r3, r7, #12 800df74: 4618 mov r0, r3 800df76: f000 fdeb bl 800eb50 frequency = pll3_clocks.PLL3_P_Frequency; 800df7a: 68fb ldr r3, [r7, #12] 800df7c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800df7e: f000 bc74 b.w 800e86a frequency = 0; 800df82: 2300 movs r3, #0 800df84: 63fb str r3, [r7, #60] @ 0x3c break; 800df86: f000 bc70 b.w 800e86a } case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800df8a: 4b21 ldr r3, [pc, #132] @ (800e010 ) 800df8c: 6cdb ldr r3, [r3, #76] @ 0x4c 800df8e: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800df92: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800df94: 4b1e ldr r3, [pc, #120] @ (800e010 ) 800df96: 681b ldr r3, [r3, #0] 800df98: f003 0304 and.w r3, r3, #4 800df9c: 2b04 cmp r3, #4 800df9e: d10c bne.n 800dfba 800dfa0: 6b7b ldr r3, [r7, #52] @ 0x34 800dfa2: 2b00 cmp r3, #0 800dfa4: d109 bne.n 800dfba { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800dfa6: 4b1a ldr r3, [pc, #104] @ (800e010 ) 800dfa8: 681b ldr r3, [r3, #0] 800dfaa: 08db lsrs r3, r3, #3 800dfac: f003 0303 and.w r3, r3, #3 800dfb0: 4a18 ldr r2, [pc, #96] @ (800e014 ) 800dfb2: fa22 f303 lsr.w r3, r2, r3 800dfb6: 63fb str r3, [r7, #60] @ 0x3c 800dfb8: e01f b.n 800dffa } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800dfba: 4b15 ldr r3, [pc, #84] @ (800e010 ) 800dfbc: 681b ldr r3, [r3, #0] 800dfbe: f403 7380 and.w r3, r3, #256 @ 0x100 800dfc2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800dfc6: d106 bne.n 800dfd6 800dfc8: 6b7b ldr r3, [r7, #52] @ 0x34 800dfca: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800dfce: d102 bne.n 800dfd6 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800dfd0: 4b11 ldr r3, [pc, #68] @ (800e018 ) 800dfd2: 63fb str r3, [r7, #60] @ 0x3c 800dfd4: e011 b.n 800dffa } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800dfd6: 4b0e ldr r3, [pc, #56] @ (800e010 ) 800dfd8: 681b ldr r3, [r3, #0] 800dfda: f403 3300 and.w r3, r3, #131072 @ 0x20000 800dfde: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800dfe2: d106 bne.n 800dff2 800dfe4: 6b7b ldr r3, [r7, #52] @ 0x34 800dfe6: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800dfea: d102 bne.n 800dff2 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800dfec: 4b0b ldr r3, [pc, #44] @ (800e01c ) 800dfee: 63fb str r3, [r7, #60] @ 0x3c 800dff0: e003 b.n 800dffa } else { /* In Case the CKPER is disabled*/ frequency = 0; 800dff2: 2300 movs r3, #0 800dff4: 63fb str r3, [r7, #60] @ 0x3c } break; 800dff6: f000 bc38 b.w 800e86a 800dffa: f000 bc36 b.w 800e86a } case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ { frequency = EXTERNAL_CLOCK_VALUE; 800dffe: 4b08 ldr r3, [pc, #32] @ (800e020 ) 800e000: 63fb str r3, [r7, #60] @ 0x3c break; 800e002: f000 bc32 b.w 800e86a } default : { frequency = 0; 800e006: 2300 movs r3, #0 800e008: 63fb str r3, [r7, #60] @ 0x3c break; 800e00a: f000 bc2e b.w 800e86a 800e00e: bf00 nop 800e010: 58024400 .word 0x58024400 800e014: 03d09000 .word 0x03d09000 800e018: 003d0900 .word 0x003d0900 800e01c: 017d7840 .word 0x017d7840 800e020: 00bb8000 .word 0x00bb8000 } } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) 800e024: e9d7 2300 ldrd r2, r3, [r7] 800e028: f5a2 6180 sub.w r1, r2, #1024 @ 0x400 800e02c: 430b orrs r3, r1 800e02e: f040 809c bne.w 800e16a { saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); 800e032: 4b9e ldr r3, [pc, #632] @ (800e2ac ) 800e034: 6d9b ldr r3, [r3, #88] @ 0x58 800e036: f403 0360 and.w r3, r3, #14680064 @ 0xe00000 800e03a: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800e03c: 6b3b ldr r3, [r7, #48] @ 0x30 800e03e: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800e042: d054 beq.n 800e0ee 800e044: 6b3b ldr r3, [r7, #48] @ 0x30 800e046: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 800e04a: f200 808b bhi.w 800e164 800e04e: 6b3b ldr r3, [r7, #48] @ 0x30 800e050: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800e054: f000 8083 beq.w 800e15e 800e058: 6b3b ldr r3, [r7, #48] @ 0x30 800e05a: f5b3 0fc0 cmp.w r3, #6291456 @ 0x600000 800e05e: f200 8081 bhi.w 800e164 800e062: 6b3b ldr r3, [r7, #48] @ 0x30 800e064: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800e068: d02f beq.n 800e0ca 800e06a: 6b3b ldr r3, [r7, #48] @ 0x30 800e06c: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 800e070: d878 bhi.n 800e164 800e072: 6b3b ldr r3, [r7, #48] @ 0x30 800e074: 2b00 cmp r3, #0 800e076: d004 beq.n 800e082 800e078: 6b3b ldr r3, [r7, #48] @ 0x30 800e07a: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 800e07e: d012 beq.n 800e0a6 800e080: e070 b.n 800e164 { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e082: 4b8a ldr r3, [pc, #552] @ (800e2ac ) 800e084: 681b ldr r3, [r3, #0] 800e086: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e08a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e08e: d107 bne.n 800e0a0 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e090: f107 0324 add.w r3, r7, #36 @ 0x24 800e094: 4618 mov r0, r3 800e096: f000 feaf bl 800edf8 frequency = pll1_clocks.PLL1_Q_Frequency; 800e09a: 6abb ldr r3, [r7, #40] @ 0x28 800e09c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e09e: e3e4 b.n 800e86a frequency = 0; 800e0a0: 2300 movs r3, #0 800e0a2: 63fb str r3, [r7, #60] @ 0x3c break; 800e0a4: e3e1 b.n 800e86a } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e0a6: 4b81 ldr r3, [pc, #516] @ (800e2ac ) 800e0a8: 681b ldr r3, [r3, #0] 800e0aa: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e0ae: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e0b2: d107 bne.n 800e0c4 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e0b4: f107 0318 add.w r3, r7, #24 800e0b8: 4618 mov r0, r3 800e0ba: f000 fbf5 bl 800e8a8 frequency = pll2_clocks.PLL2_P_Frequency; 800e0be: 69bb ldr r3, [r7, #24] 800e0c0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e0c2: e3d2 b.n 800e86a frequency = 0; 800e0c4: 2300 movs r3, #0 800e0c6: 63fb str r3, [r7, #60] @ 0x3c break; 800e0c8: e3cf b.n 800e86a } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e0ca: 4b78 ldr r3, [pc, #480] @ (800e2ac ) 800e0cc: 681b ldr r3, [r3, #0] 800e0ce: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e0d2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e0d6: d107 bne.n 800e0e8 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e0d8: f107 030c add.w r3, r7, #12 800e0dc: 4618 mov r0, r3 800e0de: f000 fd37 bl 800eb50 frequency = pll3_clocks.PLL3_P_Frequency; 800e0e2: 68fb ldr r3, [r7, #12] 800e0e4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e0e6: e3c0 b.n 800e86a frequency = 0; 800e0e8: 2300 movs r3, #0 800e0ea: 63fb str r3, [r7, #60] @ 0x3c break; 800e0ec: e3bd b.n 800e86a } case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e0ee: 4b6f ldr r3, [pc, #444] @ (800e2ac ) 800e0f0: 6cdb ldr r3, [r3, #76] @ 0x4c 800e0f2: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e0f6: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e0f8: 4b6c ldr r3, [pc, #432] @ (800e2ac ) 800e0fa: 681b ldr r3, [r3, #0] 800e0fc: f003 0304 and.w r3, r3, #4 800e100: 2b04 cmp r3, #4 800e102: d10c bne.n 800e11e 800e104: 6b7b ldr r3, [r7, #52] @ 0x34 800e106: 2b00 cmp r3, #0 800e108: d109 bne.n 800e11e { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e10a: 4b68 ldr r3, [pc, #416] @ (800e2ac ) 800e10c: 681b ldr r3, [r3, #0] 800e10e: 08db lsrs r3, r3, #3 800e110: f003 0303 and.w r3, r3, #3 800e114: 4a66 ldr r2, [pc, #408] @ (800e2b0 ) 800e116: fa22 f303 lsr.w r3, r2, r3 800e11a: 63fb str r3, [r7, #60] @ 0x3c 800e11c: e01e b.n 800e15c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e11e: 4b63 ldr r3, [pc, #396] @ (800e2ac ) 800e120: 681b ldr r3, [r3, #0] 800e122: f403 7380 and.w r3, r3, #256 @ 0x100 800e126: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e12a: d106 bne.n 800e13a 800e12c: 6b7b ldr r3, [r7, #52] @ 0x34 800e12e: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e132: d102 bne.n 800e13a { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e134: 4b5f ldr r3, [pc, #380] @ (800e2b4 ) 800e136: 63fb str r3, [r7, #60] @ 0x3c 800e138: e010 b.n 800e15c } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e13a: 4b5c ldr r3, [pc, #368] @ (800e2ac ) 800e13c: 681b ldr r3, [r3, #0] 800e13e: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e142: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e146: d106 bne.n 800e156 800e148: 6b7b ldr r3, [r7, #52] @ 0x34 800e14a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e14e: d102 bne.n 800e156 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e150: 4b59 ldr r3, [pc, #356] @ (800e2b8 ) 800e152: 63fb str r3, [r7, #60] @ 0x3c 800e154: e002 b.n 800e15c } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e156: 2300 movs r3, #0 800e158: 63fb str r3, [r7, #60] @ 0x3c } break; 800e15a: e386 b.n 800e86a 800e15c: e385 b.n 800e86a } case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; 800e15e: 4b57 ldr r3, [pc, #348] @ (800e2bc ) 800e160: 63fb str r3, [r7, #60] @ 0x3c break; 800e162: e382 b.n 800e86a } default : { frequency = 0; 800e164: 2300 movs r3, #0 800e166: 63fb str r3, [r7, #60] @ 0x3c break; 800e168: e37f b.n 800e86a } } } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) 800e16a: e9d7 2300 ldrd r2, r3, [r7] 800e16e: f5a2 6100 sub.w r1, r2, #2048 @ 0x800 800e172: 430b orrs r3, r1 800e174: f040 80a7 bne.w 800e2c6 { saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); 800e178: 4b4c ldr r3, [pc, #304] @ (800e2ac ) 800e17a: 6d9b ldr r3, [r3, #88] @ 0x58 800e17c: f003 63e0 and.w r3, r3, #117440512 @ 0x7000000 800e180: 633b str r3, [r7, #48] @ 0x30 switch (saiclocksource) 800e182: 6b3b ldr r3, [r7, #48] @ 0x30 800e184: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800e188: d055 beq.n 800e236 800e18a: 6b3b ldr r3, [r7, #48] @ 0x30 800e18c: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 800e190: f200 8096 bhi.w 800e2c0 800e194: 6b3b ldr r3, [r7, #48] @ 0x30 800e196: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800e19a: f000 8084 beq.w 800e2a6 800e19e: 6b3b ldr r3, [r7, #48] @ 0x30 800e1a0: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000 800e1a4: f200 808c bhi.w 800e2c0 800e1a8: 6b3b ldr r3, [r7, #48] @ 0x30 800e1aa: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e1ae: d030 beq.n 800e212 800e1b0: 6b3b ldr r3, [r7, #48] @ 0x30 800e1b2: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e1b6: f200 8083 bhi.w 800e2c0 800e1ba: 6b3b ldr r3, [r7, #48] @ 0x30 800e1bc: 2b00 cmp r3, #0 800e1be: d004 beq.n 800e1ca 800e1c0: 6b3b ldr r3, [r7, #48] @ 0x30 800e1c2: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 800e1c6: d012 beq.n 800e1ee 800e1c8: e07a b.n 800e2c0 { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e1ca: 4b38 ldr r3, [pc, #224] @ (800e2ac ) 800e1cc: 681b ldr r3, [r3, #0] 800e1ce: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e1d2: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e1d6: d107 bne.n 800e1e8 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e1d8: f107 0324 add.w r3, r7, #36 @ 0x24 800e1dc: 4618 mov r0, r3 800e1de: f000 fe0b bl 800edf8 frequency = pll1_clocks.PLL1_Q_Frequency; 800e1e2: 6abb ldr r3, [r7, #40] @ 0x28 800e1e4: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e1e6: e340 b.n 800e86a frequency = 0; 800e1e8: 2300 movs r3, #0 800e1ea: 63fb str r3, [r7, #60] @ 0x3c break; 800e1ec: e33d b.n 800e86a } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e1ee: 4b2f ldr r3, [pc, #188] @ (800e2ac ) 800e1f0: 681b ldr r3, [r3, #0] 800e1f2: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e1f6: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e1fa: d107 bne.n 800e20c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e1fc: f107 0318 add.w r3, r7, #24 800e200: 4618 mov r0, r3 800e202: f000 fb51 bl 800e8a8 frequency = pll2_clocks.PLL2_P_Frequency; 800e206: 69bb ldr r3, [r7, #24] 800e208: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e20a: e32e b.n 800e86a frequency = 0; 800e20c: 2300 movs r3, #0 800e20e: 63fb str r3, [r7, #60] @ 0x3c break; 800e210: e32b b.n 800e86a } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e212: 4b26 ldr r3, [pc, #152] @ (800e2ac ) 800e214: 681b ldr r3, [r3, #0] 800e216: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e21a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e21e: d107 bne.n 800e230 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e220: f107 030c add.w r3, r7, #12 800e224: 4618 mov r0, r3 800e226: f000 fc93 bl 800eb50 frequency = pll3_clocks.PLL3_P_Frequency; 800e22a: 68fb ldr r3, [r7, #12] 800e22c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e22e: e31c b.n 800e86a frequency = 0; 800e230: 2300 movs r3, #0 800e232: 63fb str r3, [r7, #60] @ 0x3c break; 800e234: e319 b.n 800e86a } case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e236: 4b1d ldr r3, [pc, #116] @ (800e2ac ) 800e238: 6cdb ldr r3, [r3, #76] @ 0x4c 800e23a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e23e: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e240: 4b1a ldr r3, [pc, #104] @ (800e2ac ) 800e242: 681b ldr r3, [r3, #0] 800e244: f003 0304 and.w r3, r3, #4 800e248: 2b04 cmp r3, #4 800e24a: d10c bne.n 800e266 800e24c: 6b7b ldr r3, [r7, #52] @ 0x34 800e24e: 2b00 cmp r3, #0 800e250: d109 bne.n 800e266 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e252: 4b16 ldr r3, [pc, #88] @ (800e2ac ) 800e254: 681b ldr r3, [r3, #0] 800e256: 08db lsrs r3, r3, #3 800e258: f003 0303 and.w r3, r3, #3 800e25c: 4a14 ldr r2, [pc, #80] @ (800e2b0 ) 800e25e: fa22 f303 lsr.w r3, r2, r3 800e262: 63fb str r3, [r7, #60] @ 0x3c 800e264: e01e b.n 800e2a4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e266: 4b11 ldr r3, [pc, #68] @ (800e2ac ) 800e268: 681b ldr r3, [r3, #0] 800e26a: f403 7380 and.w r3, r3, #256 @ 0x100 800e26e: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e272: d106 bne.n 800e282 800e274: 6b7b ldr r3, [r7, #52] @ 0x34 800e276: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e27a: d102 bne.n 800e282 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e27c: 4b0d ldr r3, [pc, #52] @ (800e2b4 ) 800e27e: 63fb str r3, [r7, #60] @ 0x3c 800e280: e010 b.n 800e2a4 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e282: 4b0a ldr r3, [pc, #40] @ (800e2ac ) 800e284: 681b ldr r3, [r3, #0] 800e286: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e28a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e28e: d106 bne.n 800e29e 800e290: 6b7b ldr r3, [r7, #52] @ 0x34 800e292: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e296: d102 bne.n 800e29e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e298: 4b07 ldr r3, [pc, #28] @ (800e2b8 ) 800e29a: 63fb str r3, [r7, #60] @ 0x3c 800e29c: e002 b.n 800e2a4 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e29e: 2300 movs r3, #0 800e2a0: 63fb str r3, [r7, #60] @ 0x3c } break; 800e2a2: e2e2 b.n 800e86a 800e2a4: e2e1 b.n 800e86a } case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; 800e2a6: 4b05 ldr r3, [pc, #20] @ (800e2bc ) 800e2a8: 63fb str r3, [r7, #60] @ 0x3c break; 800e2aa: e2de b.n 800e86a 800e2ac: 58024400 .word 0x58024400 800e2b0: 03d09000 .word 0x03d09000 800e2b4: 003d0900 .word 0x003d0900 800e2b8: 017d7840 .word 0x017d7840 800e2bc: 00bb8000 .word 0x00bb8000 } default : { frequency = 0; 800e2c0: 2300 movs r3, #0 800e2c2: 63fb str r3, [r7, #60] @ 0x3c break; 800e2c4: e2d1 b.n 800e86a } } } #endif /*SAI4*/ else if (PeriphClk == RCC_PERIPHCLK_SPI123) 800e2c6: e9d7 2300 ldrd r2, r3, [r7] 800e2ca: f5a2 5180 sub.w r1, r2, #4096 @ 0x1000 800e2ce: 430b orrs r3, r1 800e2d0: f040 809c bne.w 800e40c { /* Get SPI1/2/3 clock source */ srcclk = __HAL_RCC_GET_SPI123_SOURCE(); 800e2d4: 4b93 ldr r3, [pc, #588] @ (800e524 ) 800e2d6: 6d1b ldr r3, [r3, #80] @ 0x50 800e2d8: f403 43e0 and.w r3, r3, #28672 @ 0x7000 800e2dc: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e2de: 6bbb ldr r3, [r7, #56] @ 0x38 800e2e0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800e2e4: d054 beq.n 800e390 800e2e6: 6bbb ldr r3, [r7, #56] @ 0x38 800e2e8: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 800e2ec: f200 808b bhi.w 800e406 800e2f0: 6bbb ldr r3, [r7, #56] @ 0x38 800e2f2: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800e2f6: f000 8083 beq.w 800e400 800e2fa: 6bbb ldr r3, [r7, #56] @ 0x38 800e2fc: f5b3 5f40 cmp.w r3, #12288 @ 0x3000 800e300: f200 8081 bhi.w 800e406 800e304: 6bbb ldr r3, [r7, #56] @ 0x38 800e306: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e30a: d02f beq.n 800e36c 800e30c: 6bbb ldr r3, [r7, #56] @ 0x38 800e30e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800e312: d878 bhi.n 800e406 800e314: 6bbb ldr r3, [r7, #56] @ 0x38 800e316: 2b00 cmp r3, #0 800e318: d004 beq.n 800e324 800e31a: 6bbb ldr r3, [r7, #56] @ 0x38 800e31c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800e320: d012 beq.n 800e348 800e322: e070 b.n 800e406 { case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e324: 4b7f ldr r3, [pc, #508] @ (800e524 ) 800e326: 681b ldr r3, [r3, #0] 800e328: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e32c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e330: d107 bne.n 800e342 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e332: f107 0324 add.w r3, r7, #36 @ 0x24 800e336: 4618 mov r0, r3 800e338: f000 fd5e bl 800edf8 frequency = pll1_clocks.PLL1_Q_Frequency; 800e33c: 6abb ldr r3, [r7, #40] @ 0x28 800e33e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e340: e293 b.n 800e86a frequency = 0; 800e342: 2300 movs r3, #0 800e344: 63fb str r3, [r7, #60] @ 0x3c break; 800e346: e290 b.n 800e86a } case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e348: 4b76 ldr r3, [pc, #472] @ (800e524 ) 800e34a: 681b ldr r3, [r3, #0] 800e34c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e350: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e354: d107 bne.n 800e366 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e356: f107 0318 add.w r3, r7, #24 800e35a: 4618 mov r0, r3 800e35c: f000 faa4 bl 800e8a8 frequency = pll2_clocks.PLL2_P_Frequency; 800e360: 69bb ldr r3, [r7, #24] 800e362: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e364: e281 b.n 800e86a frequency = 0; 800e366: 2300 movs r3, #0 800e368: 63fb str r3, [r7, #60] @ 0x3c break; 800e36a: e27e b.n 800e86a } case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e36c: 4b6d ldr r3, [pc, #436] @ (800e524 ) 800e36e: 681b ldr r3, [r3, #0] 800e370: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e374: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e378: d107 bne.n 800e38a { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e37a: f107 030c add.w r3, r7, #12 800e37e: 4618 mov r0, r3 800e380: f000 fbe6 bl 800eb50 frequency = pll3_clocks.PLL3_P_Frequency; 800e384: 68fb ldr r3, [r7, #12] 800e386: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e388: e26f b.n 800e86a frequency = 0; 800e38a: 2300 movs r3, #0 800e38c: 63fb str r3, [r7, #60] @ 0x3c break; 800e38e: e26c b.n 800e86a } case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e390: 4b64 ldr r3, [pc, #400] @ (800e524 ) 800e392: 6cdb ldr r3, [r3, #76] @ 0x4c 800e394: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e398: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e39a: 4b62 ldr r3, [pc, #392] @ (800e524 ) 800e39c: 681b ldr r3, [r3, #0] 800e39e: f003 0304 and.w r3, r3, #4 800e3a2: 2b04 cmp r3, #4 800e3a4: d10c bne.n 800e3c0 800e3a6: 6b7b ldr r3, [r7, #52] @ 0x34 800e3a8: 2b00 cmp r3, #0 800e3aa: d109 bne.n 800e3c0 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e3ac: 4b5d ldr r3, [pc, #372] @ (800e524 ) 800e3ae: 681b ldr r3, [r3, #0] 800e3b0: 08db lsrs r3, r3, #3 800e3b2: f003 0303 and.w r3, r3, #3 800e3b6: 4a5c ldr r2, [pc, #368] @ (800e528 ) 800e3b8: fa22 f303 lsr.w r3, r2, r3 800e3bc: 63fb str r3, [r7, #60] @ 0x3c 800e3be: e01e b.n 800e3fe } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e3c0: 4b58 ldr r3, [pc, #352] @ (800e524 ) 800e3c2: 681b ldr r3, [r3, #0] 800e3c4: f403 7380 and.w r3, r3, #256 @ 0x100 800e3c8: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e3cc: d106 bne.n 800e3dc 800e3ce: 6b7b ldr r3, [r7, #52] @ 0x34 800e3d0: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e3d4: d102 bne.n 800e3dc { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e3d6: 4b55 ldr r3, [pc, #340] @ (800e52c ) 800e3d8: 63fb str r3, [r7, #60] @ 0x3c 800e3da: e010 b.n 800e3fe } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e3dc: 4b51 ldr r3, [pc, #324] @ (800e524 ) 800e3de: 681b ldr r3, [r3, #0] 800e3e0: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e3e4: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e3e8: d106 bne.n 800e3f8 800e3ea: 6b7b ldr r3, [r7, #52] @ 0x34 800e3ec: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e3f0: d102 bne.n 800e3f8 { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e3f2: 4b4f ldr r3, [pc, #316] @ (800e530 ) 800e3f4: 63fb str r3, [r7, #60] @ 0x3c 800e3f6: e002 b.n 800e3fe } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e3f8: 2300 movs r3, #0 800e3fa: 63fb str r3, [r7, #60] @ 0x3c } break; 800e3fc: e235 b.n 800e86a 800e3fe: e234 b.n 800e86a } case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ { frequency = EXTERNAL_CLOCK_VALUE; 800e400: 4b4c ldr r3, [pc, #304] @ (800e534 ) 800e402: 63fb str r3, [r7, #60] @ 0x3c break; 800e404: e231 b.n 800e86a } default : { frequency = 0; 800e406: 2300 movs r3, #0 800e408: 63fb str r3, [r7, #60] @ 0x3c break; 800e40a: e22e b.n 800e86a } } } else if (PeriphClk == RCC_PERIPHCLK_SPI45) 800e40c: e9d7 2300 ldrd r2, r3, [r7] 800e410: f5a2 5100 sub.w r1, r2, #8192 @ 0x2000 800e414: 430b orrs r3, r1 800e416: f040 808f bne.w 800e538 { /* Get SPI45 clock source */ srcclk = __HAL_RCC_GET_SPI45_SOURCE(); 800e41a: 4b42 ldr r3, [pc, #264] @ (800e524 ) 800e41c: 6d1b ldr r3, [r3, #80] @ 0x50 800e41e: f403 23e0 and.w r3, r3, #458752 @ 0x70000 800e422: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e424: 6bbb ldr r3, [r7, #56] @ 0x38 800e426: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e42a: d06b beq.n 800e504 800e42c: 6bbb ldr r3, [r7, #56] @ 0x38 800e42e: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 800e432: d874 bhi.n 800e51e 800e434: 6bbb ldr r3, [r7, #56] @ 0x38 800e436: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e43a: d056 beq.n 800e4ea 800e43c: 6bbb ldr r3, [r7, #56] @ 0x38 800e43e: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 800e442: d86c bhi.n 800e51e 800e444: 6bbb ldr r3, [r7, #56] @ 0x38 800e446: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e44a: d03b beq.n 800e4c4 800e44c: 6bbb ldr r3, [r7, #56] @ 0x38 800e44e: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 800e452: d864 bhi.n 800e51e 800e454: 6bbb ldr r3, [r7, #56] @ 0x38 800e456: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e45a: d021 beq.n 800e4a0 800e45c: 6bbb ldr r3, [r7, #56] @ 0x38 800e45e: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e462: d85c bhi.n 800e51e 800e464: 6bbb ldr r3, [r7, #56] @ 0x38 800e466: 2b00 cmp r3, #0 800e468: d004 beq.n 800e474 800e46a: 6bbb ldr r3, [r7, #56] @ 0x38 800e46c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e470: d004 beq.n 800e47c 800e472: e054 b.n 800e51e { case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ { frequency = HAL_RCC_GetPCLK1Freq(); 800e474: f7fe fa26 bl 800c8c4 800e478: 63f8 str r0, [r7, #60] @ 0x3c break; 800e47a: e1f6 b.n 800e86a } case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e47c: 4b29 ldr r3, [pc, #164] @ (800e524 ) 800e47e: 681b ldr r3, [r3, #0] 800e480: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e484: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e488: d107 bne.n 800e49a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e48a: f107 0318 add.w r3, r7, #24 800e48e: 4618 mov r0, r3 800e490: f000 fa0a bl 800e8a8 frequency = pll2_clocks.PLL2_Q_Frequency; 800e494: 69fb ldr r3, [r7, #28] 800e496: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e498: e1e7 b.n 800e86a frequency = 0; 800e49a: 2300 movs r3, #0 800e49c: 63fb str r3, [r7, #60] @ 0x3c break; 800e49e: e1e4 b.n 800e86a } case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e4a0: 4b20 ldr r3, [pc, #128] @ (800e524 ) 800e4a2: 681b ldr r3, [r3, #0] 800e4a4: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e4a8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e4ac: d107 bne.n 800e4be { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e4ae: f107 030c add.w r3, r7, #12 800e4b2: 4618 mov r0, r3 800e4b4: f000 fb4c bl 800eb50 frequency = pll3_clocks.PLL3_Q_Frequency; 800e4b8: 693b ldr r3, [r7, #16] 800e4ba: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4bc: e1d5 b.n 800e86a frequency = 0; 800e4be: 2300 movs r3, #0 800e4c0: 63fb str r3, [r7, #60] @ 0x3c break; 800e4c2: e1d2 b.n 800e86a } case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e4c4: 4b17 ldr r3, [pc, #92] @ (800e524 ) 800e4c6: 681b ldr r3, [r3, #0] 800e4c8: f003 0304 and.w r3, r3, #4 800e4cc: 2b04 cmp r3, #4 800e4ce: d109 bne.n 800e4e4 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e4d0: 4b14 ldr r3, [pc, #80] @ (800e524 ) 800e4d2: 681b ldr r3, [r3, #0] 800e4d4: 08db lsrs r3, r3, #3 800e4d6: f003 0303 and.w r3, r3, #3 800e4da: 4a13 ldr r2, [pc, #76] @ (800e528 ) 800e4dc: fa22 f303 lsr.w r3, r2, r3 800e4e0: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4e2: e1c2 b.n 800e86a frequency = 0; 800e4e4: 2300 movs r3, #0 800e4e6: 63fb str r3, [r7, #60] @ 0x3c break; 800e4e8: e1bf b.n 800e86a } case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e4ea: 4b0e ldr r3, [pc, #56] @ (800e524 ) 800e4ec: 681b ldr r3, [r3, #0] 800e4ee: f403 7380 and.w r3, r3, #256 @ 0x100 800e4f2: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e4f6: d102 bne.n 800e4fe { frequency = CSI_VALUE; 800e4f8: 4b0c ldr r3, [pc, #48] @ (800e52c ) 800e4fa: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e4fc: e1b5 b.n 800e86a frequency = 0; 800e4fe: 2300 movs r3, #0 800e500: 63fb str r3, [r7, #60] @ 0x3c break; 800e502: e1b2 b.n 800e86a } case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e504: 4b07 ldr r3, [pc, #28] @ (800e524 ) 800e506: 681b ldr r3, [r3, #0] 800e508: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e50c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e510: d102 bne.n 800e518 { frequency = HSE_VALUE; 800e512: 4b07 ldr r3, [pc, #28] @ (800e530 ) 800e514: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e516: e1a8 b.n 800e86a frequency = 0; 800e518: 2300 movs r3, #0 800e51a: 63fb str r3, [r7, #60] @ 0x3c break; 800e51c: e1a5 b.n 800e86a } default : { frequency = 0; 800e51e: 2300 movs r3, #0 800e520: 63fb str r3, [r7, #60] @ 0x3c break; 800e522: e1a2 b.n 800e86a 800e524: 58024400 .word 0x58024400 800e528: 03d09000 .word 0x03d09000 800e52c: 003d0900 .word 0x003d0900 800e530: 017d7840 .word 0x017d7840 800e534: 00bb8000 .word 0x00bb8000 } } } else if (PeriphClk == RCC_PERIPHCLK_ADC) 800e538: e9d7 2300 ldrd r2, r3, [r7] 800e53c: f5a2 2100 sub.w r1, r2, #524288 @ 0x80000 800e540: 430b orrs r3, r1 800e542: d173 bne.n 800e62c { /* Get ADC clock source */ srcclk = __HAL_RCC_GET_ADC_SOURCE(); 800e544: 4b9c ldr r3, [pc, #624] @ (800e7b8 ) 800e546: 6d9b ldr r3, [r3, #88] @ 0x58 800e548: f403 3340 and.w r3, r3, #196608 @ 0x30000 800e54c: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e54e: 6bbb ldr r3, [r7, #56] @ 0x38 800e550: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e554: d02f beq.n 800e5b6 800e556: 6bbb ldr r3, [r7, #56] @ 0x38 800e558: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e55c: d863 bhi.n 800e626 800e55e: 6bbb ldr r3, [r7, #56] @ 0x38 800e560: 2b00 cmp r3, #0 800e562: d004 beq.n 800e56e 800e564: 6bbb ldr r3, [r7, #56] @ 0x38 800e566: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e56a: d012 beq.n 800e592 800e56c: e05b b.n 800e626 { case RCC_ADCCLKSOURCE_PLL2: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e56e: 4b92 ldr r3, [pc, #584] @ (800e7b8 ) 800e570: 681b ldr r3, [r3, #0] 800e572: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e576: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e57a: d107 bne.n 800e58c { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e57c: f107 0318 add.w r3, r7, #24 800e580: 4618 mov r0, r3 800e582: f000 f991 bl 800e8a8 frequency = pll2_clocks.PLL2_P_Frequency; 800e586: 69bb ldr r3, [r7, #24] 800e588: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e58a: e16e b.n 800e86a frequency = 0; 800e58c: 2300 movs r3, #0 800e58e: 63fb str r3, [r7, #60] @ 0x3c break; 800e590: e16b b.n 800e86a } case RCC_ADCCLKSOURCE_PLL3: { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e592: 4b89 ldr r3, [pc, #548] @ (800e7b8 ) 800e594: 681b ldr r3, [r3, #0] 800e596: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e59a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e59e: d107 bne.n 800e5b0 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e5a0: f107 030c add.w r3, r7, #12 800e5a4: 4618 mov r0, r3 800e5a6: f000 fad3 bl 800eb50 frequency = pll3_clocks.PLL3_R_Frequency; 800e5aa: 697b ldr r3, [r7, #20] 800e5ac: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e5ae: e15c b.n 800e86a frequency = 0; 800e5b0: 2300 movs r3, #0 800e5b2: 63fb str r3, [r7, #60] @ 0x3c break; 800e5b4: e159 b.n 800e86a } case RCC_ADCCLKSOURCE_CLKP: { ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); 800e5b6: 4b80 ldr r3, [pc, #512] @ (800e7b8 ) 800e5b8: 6cdb ldr r3, [r3, #76] @ 0x4c 800e5ba: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e5be: 637b str r3, [r7, #52] @ 0x34 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) 800e5c0: 4b7d ldr r3, [pc, #500] @ (800e7b8 ) 800e5c2: 681b ldr r3, [r3, #0] 800e5c4: f003 0304 and.w r3, r3, #4 800e5c8: 2b04 cmp r3, #4 800e5ca: d10c bne.n 800e5e6 800e5cc: 6b7b ldr r3, [r7, #52] @ 0x34 800e5ce: 2b00 cmp r3, #0 800e5d0: d109 bne.n 800e5e6 { /* In Case the CKPER Source is HSI */ frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e5d2: 4b79 ldr r3, [pc, #484] @ (800e7b8 ) 800e5d4: 681b ldr r3, [r3, #0] 800e5d6: 08db lsrs r3, r3, #3 800e5d8: f003 0303 and.w r3, r3, #3 800e5dc: 4a77 ldr r2, [pc, #476] @ (800e7bc ) 800e5de: fa22 f303 lsr.w r3, r2, r3 800e5e2: 63fb str r3, [r7, #60] @ 0x3c 800e5e4: e01e b.n 800e624 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) 800e5e6: 4b74 ldr r3, [pc, #464] @ (800e7b8 ) 800e5e8: 681b ldr r3, [r3, #0] 800e5ea: f403 7380 and.w r3, r3, #256 @ 0x100 800e5ee: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e5f2: d106 bne.n 800e602 800e5f4: 6b7b ldr r3, [r7, #52] @ 0x34 800e5f6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e5fa: d102 bne.n 800e602 { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; 800e5fc: 4b70 ldr r3, [pc, #448] @ (800e7c0 ) 800e5fe: 63fb str r3, [r7, #60] @ 0x3c 800e600: e010 b.n 800e624 } else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) 800e602: 4b6d ldr r3, [pc, #436] @ (800e7b8 ) 800e604: 681b ldr r3, [r3, #0] 800e606: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e60a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e60e: d106 bne.n 800e61e 800e610: 6b7b ldr r3, [r7, #52] @ 0x34 800e612: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e616: d102 bne.n 800e61e { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; 800e618: 4b6a ldr r3, [pc, #424] @ (800e7c4 ) 800e61a: 63fb str r3, [r7, #60] @ 0x3c 800e61c: e002 b.n 800e624 } else { /* In Case the CKPER is disabled*/ frequency = 0; 800e61e: 2300 movs r3, #0 800e620: 63fb str r3, [r7, #60] @ 0x3c } break; 800e622: e122 b.n 800e86a 800e624: e121 b.n 800e86a } default : { frequency = 0; 800e626: 2300 movs r3, #0 800e628: 63fb str r3, [r7, #60] @ 0x3c break; 800e62a: e11e b.n 800e86a } } } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) 800e62c: e9d7 2300 ldrd r2, r3, [r7] 800e630: f5a2 3180 sub.w r1, r2, #65536 @ 0x10000 800e634: 430b orrs r3, r1 800e636: d133 bne.n 800e6a0 { /* Get SDMMC clock source */ srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); 800e638: 4b5f ldr r3, [pc, #380] @ (800e7b8 ) 800e63a: 6cdb ldr r3, [r3, #76] @ 0x4c 800e63c: f403 3380 and.w r3, r3, #65536 @ 0x10000 800e640: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e642: 6bbb ldr r3, [r7, #56] @ 0x38 800e644: 2b00 cmp r3, #0 800e646: d004 beq.n 800e652 800e648: 6bbb ldr r3, [r7, #56] @ 0x38 800e64a: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800e64e: d012 beq.n 800e676 800e650: e023 b.n 800e69a { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e652: 4b59 ldr r3, [pc, #356] @ (800e7b8 ) 800e654: 681b ldr r3, [r3, #0] 800e656: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e65a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e65e: d107 bne.n 800e670 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e660: f107 0324 add.w r3, r7, #36 @ 0x24 800e664: 4618 mov r0, r3 800e666: f000 fbc7 bl 800edf8 frequency = pll1_clocks.PLL1_Q_Frequency; 800e66a: 6abb ldr r3, [r7, #40] @ 0x28 800e66c: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e66e: e0fc b.n 800e86a frequency = 0; 800e670: 2300 movs r3, #0 800e672: 63fb str r3, [r7, #60] @ 0x3c break; 800e674: e0f9 b.n 800e86a } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e676: 4b50 ldr r3, [pc, #320] @ (800e7b8 ) 800e678: 681b ldr r3, [r3, #0] 800e67a: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e67e: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e682: d107 bne.n 800e694 { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e684: f107 0318 add.w r3, r7, #24 800e688: 4618 mov r0, r3 800e68a: f000 f90d bl 800e8a8 frequency = pll2_clocks.PLL2_R_Frequency; 800e68e: 6a3b ldr r3, [r7, #32] 800e690: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e692: e0ea b.n 800e86a frequency = 0; 800e694: 2300 movs r3, #0 800e696: 63fb str r3, [r7, #60] @ 0x3c break; 800e698: e0e7 b.n 800e86a } default : { frequency = 0; 800e69a: 2300 movs r3, #0 800e69c: 63fb str r3, [r7, #60] @ 0x3c break; 800e69e: e0e4 b.n 800e86a } } } else if (PeriphClk == RCC_PERIPHCLK_SPI6) 800e6a0: e9d7 2300 ldrd r2, r3, [r7] 800e6a4: f5a2 4180 sub.w r1, r2, #16384 @ 0x4000 800e6a8: 430b orrs r3, r1 800e6aa: f040 808d bne.w 800e7c8 { /* Get SPI6 clock source */ srcclk = __HAL_RCC_GET_SPI6_SOURCE(); 800e6ae: 4b42 ldr r3, [pc, #264] @ (800e7b8 ) 800e6b0: 6d9b ldr r3, [r3, #88] @ 0x58 800e6b2: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000 800e6b6: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e6b8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ba: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e6be: d06b beq.n 800e798 800e6c0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6c2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000 800e6c6: d874 bhi.n 800e7b2 800e6c8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ca: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e6ce: d056 beq.n 800e77e 800e6d0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6d2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800e6d6: d86c bhi.n 800e7b2 800e6d8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6da: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e6de: d03b beq.n 800e758 800e6e0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6e2: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000 800e6e6: d864 bhi.n 800e7b2 800e6e8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6ea: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e6ee: d021 beq.n 800e734 800e6f0: 6bbb ldr r3, [r7, #56] @ 0x38 800e6f2: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e6f6: d85c bhi.n 800e7b2 800e6f8: 6bbb ldr r3, [r7, #56] @ 0x38 800e6fa: 2b00 cmp r3, #0 800e6fc: d004 beq.n 800e708 800e6fe: 6bbb ldr r3, [r7, #56] @ 0x38 800e700: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e704: d004 beq.n 800e710 800e706: e054 b.n 800e7b2 { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ { frequency = HAL_RCCEx_GetD3PCLK1Freq(); 800e708: f000 f8b8 bl 800e87c 800e70c: 63f8 str r0, [r7, #60] @ 0x3c break; 800e70e: e0ac b.n 800e86a } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e710: 4b29 ldr r3, [pc, #164] @ (800e7b8 ) 800e712: 681b ldr r3, [r3, #0] 800e714: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e718: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e71c: d107 bne.n 800e72e { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e71e: f107 0318 add.w r3, r7, #24 800e722: 4618 mov r0, r3 800e724: f000 f8c0 bl 800e8a8 frequency = pll2_clocks.PLL2_Q_Frequency; 800e728: 69fb ldr r3, [r7, #28] 800e72a: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e72c: e09d b.n 800e86a frequency = 0; 800e72e: 2300 movs r3, #0 800e730: 63fb str r3, [r7, #60] @ 0x3c break; 800e732: e09a b.n 800e86a } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) 800e734: 4b20 ldr r3, [pc, #128] @ (800e7b8 ) 800e736: 681b ldr r3, [r3, #0] 800e738: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800e73c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e740: d107 bne.n 800e752 { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 800e742: f107 030c add.w r3, r7, #12 800e746: 4618 mov r0, r3 800e748: f000 fa02 bl 800eb50 frequency = pll3_clocks.PLL3_Q_Frequency; 800e74c: 693b ldr r3, [r7, #16] 800e74e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e750: e08b b.n 800e86a frequency = 0; 800e752: 2300 movs r3, #0 800e754: 63fb str r3, [r7, #60] @ 0x3c break; 800e756: e088 b.n 800e86a } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) 800e758: 4b17 ldr r3, [pc, #92] @ (800e7b8 ) 800e75a: 681b ldr r3, [r3, #0] 800e75c: f003 0304 and.w r3, r3, #4 800e760: 2b04 cmp r3, #4 800e762: d109 bne.n 800e778 { frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e764: 4b14 ldr r3, [pc, #80] @ (800e7b8 ) 800e766: 681b ldr r3, [r3, #0] 800e768: 08db lsrs r3, r3, #3 800e76a: f003 0303 and.w r3, r3, #3 800e76e: 4a13 ldr r2, [pc, #76] @ (800e7bc ) 800e770: fa22 f303 lsr.w r3, r2, r3 800e774: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e776: e078 b.n 800e86a frequency = 0; 800e778: 2300 movs r3, #0 800e77a: 63fb str r3, [r7, #60] @ 0x3c break; 800e77c: e075 b.n 800e86a } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) 800e77e: 4b0e ldr r3, [pc, #56] @ (800e7b8 ) 800e780: 681b ldr r3, [r3, #0] 800e782: f403 7380 and.w r3, r3, #256 @ 0x100 800e786: f5b3 7f80 cmp.w r3, #256 @ 0x100 800e78a: d102 bne.n 800e792 { frequency = CSI_VALUE; 800e78c: 4b0c ldr r3, [pc, #48] @ (800e7c0 ) 800e78e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e790: e06b b.n 800e86a frequency = 0; 800e792: 2300 movs r3, #0 800e794: 63fb str r3, [r7, #60] @ 0x3c break; 800e796: e068 b.n 800e86a } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e798: 4b07 ldr r3, [pc, #28] @ (800e7b8 ) 800e79a: 681b ldr r3, [r3, #0] 800e79c: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e7a0: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e7a4: d102 bne.n 800e7ac { frequency = HSE_VALUE; 800e7a6: 4b07 ldr r3, [pc, #28] @ (800e7c4 ) 800e7a8: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e7aa: e05e b.n 800e86a frequency = 0; 800e7ac: 2300 movs r3, #0 800e7ae: 63fb str r3, [r7, #60] @ 0x3c break; 800e7b0: e05b b.n 800e86a break; } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : { frequency = 0; 800e7b2: 2300 movs r3, #0 800e7b4: 63fb str r3, [r7, #60] @ 0x3c break; 800e7b6: e058 b.n 800e86a 800e7b8: 58024400 .word 0x58024400 800e7bc: 03d09000 .word 0x03d09000 800e7c0: 003d0900 .word 0x003d0900 800e7c4: 017d7840 .word 0x017d7840 } } } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) 800e7c8: e9d7 2300 ldrd r2, r3, [r7] 800e7cc: f5a2 4100 sub.w r1, r2, #32768 @ 0x8000 800e7d0: 430b orrs r3, r1 800e7d2: d148 bne.n 800e866 { /* Get FDCAN clock source */ srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); 800e7d4: 4b27 ldr r3, [pc, #156] @ (800e874 ) 800e7d6: 6d1b ldr r3, [r3, #80] @ 0x50 800e7d8: f003 5340 and.w r3, r3, #805306368 @ 0x30000000 800e7dc: 63bb str r3, [r7, #56] @ 0x38 switch (srcclk) 800e7de: 6bbb ldr r3, [r7, #56] @ 0x38 800e7e0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e7e4: d02a beq.n 800e83c 800e7e6: 6bbb ldr r3, [r7, #56] @ 0x38 800e7e8: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800e7ec: d838 bhi.n 800e860 800e7ee: 6bbb ldr r3, [r7, #56] @ 0x38 800e7f0: 2b00 cmp r3, #0 800e7f2: d004 beq.n 800e7fe 800e7f4: 6bbb ldr r3, [r7, #56] @ 0x38 800e7f6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 800e7fa: d00d beq.n 800e818 800e7fc: e030 b.n 800e860 { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) 800e7fe: 4b1d ldr r3, [pc, #116] @ (800e874 ) 800e800: 681b ldr r3, [r3, #0] 800e802: f403 3300 and.w r3, r3, #131072 @ 0x20000 800e806: f5b3 3f00 cmp.w r3, #131072 @ 0x20000 800e80a: d102 bne.n 800e812 { frequency = HSE_VALUE; 800e80c: 4b1a ldr r3, [pc, #104] @ (800e878 ) 800e80e: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e810: e02b b.n 800e86a frequency = 0; 800e812: 2300 movs r3, #0 800e814: 63fb str r3, [r7, #60] @ 0x3c break; 800e816: e028 b.n 800e86a } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) 800e818: 4b16 ldr r3, [pc, #88] @ (800e874 ) 800e81a: 681b ldr r3, [r3, #0] 800e81c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800e820: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 800e824: d107 bne.n 800e836 { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); 800e826: f107 0324 add.w r3, r7, #36 @ 0x24 800e82a: 4618 mov r0, r3 800e82c: f000 fae4 bl 800edf8 frequency = pll1_clocks.PLL1_Q_Frequency; 800e830: 6abb ldr r3, [r7, #40] @ 0x28 800e832: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e834: e019 b.n 800e86a frequency = 0; 800e836: 2300 movs r3, #0 800e838: 63fb str r3, [r7, #60] @ 0x3c break; 800e83a: e016 b.n 800e86a } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ { if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) 800e83c: 4b0d ldr r3, [pc, #52] @ (800e874 ) 800e83e: 681b ldr r3, [r3, #0] 800e840: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800e844: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000 800e848: d107 bne.n 800e85a { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 800e84a: f107 0318 add.w r3, r7, #24 800e84e: 4618 mov r0, r3 800e850: f000 f82a bl 800e8a8 frequency = pll2_clocks.PLL2_Q_Frequency; 800e854: 69fb ldr r3, [r7, #28] 800e856: 63fb str r3, [r7, #60] @ 0x3c } else { frequency = 0; } break; 800e858: e007 b.n 800e86a frequency = 0; 800e85a: 2300 movs r3, #0 800e85c: 63fb str r3, [r7, #60] @ 0x3c break; 800e85e: e004 b.n 800e86a } default : { frequency = 0; 800e860: 2300 movs r3, #0 800e862: 63fb str r3, [r7, #60] @ 0x3c break; 800e864: e001 b.n 800e86a } } } else { frequency = 0; 800e866: 2300 movs r3, #0 800e868: 63fb str r3, [r7, #60] @ 0x3c } return frequency; 800e86a: 6bfb ldr r3, [r7, #60] @ 0x3c } 800e86c: 4618 mov r0, r3 800e86e: 3740 adds r7, #64 @ 0x40 800e870: 46bd mov sp, r7 800e872: bd80 pop {r7, pc} 800e874: 58024400 .word 0x58024400 800e878: 017d7840 .word 0x017d7840 0800e87c : * @note Each time D3PCLK1 changes, this function must be called to update the * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval D3PCLK1 frequency */ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { 800e87c: b580 push {r7, lr} 800e87e: af00 add r7, sp, #0 #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); 800e880: f7fd fff0 bl 800c864 800e884: 4602 mov r2, r0 800e886: 4b06 ldr r3, [pc, #24] @ (800e8a0 ) 800e888: 6a1b ldr r3, [r3, #32] 800e88a: 091b lsrs r3, r3, #4 800e88c: f003 0307 and.w r3, r3, #7 800e890: 4904 ldr r1, [pc, #16] @ (800e8a4 ) 800e892: 5ccb ldrb r3, [r1, r3] 800e894: f003 031f and.w r3, r3, #31 800e898: fa22 f303 lsr.w r3, r2, r3 #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } 800e89c: 4618 mov r0, r3 800e89e: bd80 pop {r7, pc} 800e8a0: 58024400 .word 0x58024400 800e8a4: 0801870c .word 0x0801870c 0800e8a8 : * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL2_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { 800e8a8: b480 push {r7} 800e8aa: b089 sub sp, #36 @ 0x24 800e8ac: af00 add r7, sp, #0 800e8ae: 6078 str r0, [r7, #4] float_t fracn2, pll2vco; /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800e8b0: 4ba1 ldr r3, [pc, #644] @ (800eb38 ) 800e8b2: 6a9b ldr r3, [r3, #40] @ 0x28 800e8b4: f003 0303 and.w r3, r3, #3 800e8b8: 61bb str r3, [r7, #24] pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); 800e8ba: 4b9f ldr r3, [pc, #636] @ (800eb38 ) 800e8bc: 6a9b ldr r3, [r3, #40] @ 0x28 800e8be: 0b1b lsrs r3, r3, #12 800e8c0: f003 033f and.w r3, r3, #63 @ 0x3f 800e8c4: 617b str r3, [r7, #20] pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; 800e8c6: 4b9c ldr r3, [pc, #624] @ (800eb38 ) 800e8c8: 6adb ldr r3, [r3, #44] @ 0x2c 800e8ca: 091b lsrs r3, r3, #4 800e8cc: f003 0301 and.w r3, r3, #1 800e8d0: 613b str r3, [r7, #16] fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); 800e8d2: 4b99 ldr r3, [pc, #612] @ (800eb38 ) 800e8d4: 6bdb ldr r3, [r3, #60] @ 0x3c 800e8d6: 08db lsrs r3, r3, #3 800e8d8: f3c3 030c ubfx r3, r3, #0, #13 800e8dc: 693a ldr r2, [r7, #16] 800e8de: fb02 f303 mul.w r3, r2, r3 800e8e2: ee07 3a90 vmov s15, r3 800e8e6: eef8 7a67 vcvt.f32.u32 s15, s15 800e8ea: edc7 7a03 vstr s15, [r7, #12] if (pll2m != 0U) 800e8ee: 697b ldr r3, [r7, #20] 800e8f0: 2b00 cmp r3, #0 800e8f2: f000 8111 beq.w 800eb18 { switch (pllsource) 800e8f6: 69bb ldr r3, [r7, #24] 800e8f8: 2b02 cmp r3, #2 800e8fa: f000 8083 beq.w 800ea04 800e8fe: 69bb ldr r3, [r7, #24] 800e900: 2b02 cmp r3, #2 800e902: f200 80a1 bhi.w 800ea48 800e906: 69bb ldr r3, [r7, #24] 800e908: 2b00 cmp r3, #0 800e90a: d003 beq.n 800e914 800e90c: 69bb ldr r3, [r7, #24] 800e90e: 2b01 cmp r3, #1 800e910: d056 beq.n 800e9c0 800e912: e099 b.n 800ea48 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800e914: 4b88 ldr r3, [pc, #544] @ (800eb38 ) 800e916: 681b ldr r3, [r3, #0] 800e918: f003 0320 and.w r3, r3, #32 800e91c: 2b00 cmp r3, #0 800e91e: d02d beq.n 800e97c { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800e920: 4b85 ldr r3, [pc, #532] @ (800eb38 ) 800e922: 681b ldr r3, [r3, #0] 800e924: 08db lsrs r3, r3, #3 800e926: f003 0303 and.w r3, r3, #3 800e92a: 4a84 ldr r2, [pc, #528] @ (800eb3c ) 800e92c: fa22 f303 lsr.w r3, r2, r3 800e930: 60bb str r3, [r7, #8] pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e932: 68bb ldr r3, [r7, #8] 800e934: ee07 3a90 vmov s15, r3 800e938: eef8 6a67 vcvt.f32.u32 s13, s15 800e93c: 697b ldr r3, [r7, #20] 800e93e: ee07 3a90 vmov s15, r3 800e942: eef8 7a67 vcvt.f32.u32 s15, s15 800e946: ee86 7aa7 vdiv.f32 s14, s13, s15 800e94a: 4b7b ldr r3, [pc, #492] @ (800eb38 ) 800e94c: 6b9b ldr r3, [r3, #56] @ 0x38 800e94e: f3c3 0308 ubfx r3, r3, #0, #9 800e952: ee07 3a90 vmov s15, r3 800e956: eef8 6a67 vcvt.f32.u32 s13, s15 800e95a: ed97 6a03 vldr s12, [r7, #12] 800e95e: eddf 5a78 vldr s11, [pc, #480] @ 800eb40 800e962: eec6 7a25 vdiv.f32 s15, s12, s11 800e966: ee76 7aa7 vadd.f32 s15, s13, s15 800e96a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e96e: ee77 7aa6 vadd.f32 s15, s15, s13 800e972: ee67 7a27 vmul.f32 s15, s14, s15 800e976: edc7 7a07 vstr s15, [r7, #28] } else { pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); } break; 800e97a: e087 b.n 800ea8c pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e97c: 697b ldr r3, [r7, #20] 800e97e: ee07 3a90 vmov s15, r3 800e982: eef8 7a67 vcvt.f32.u32 s15, s15 800e986: eddf 6a6f vldr s13, [pc, #444] @ 800eb44 800e98a: ee86 7aa7 vdiv.f32 s14, s13, s15 800e98e: 4b6a ldr r3, [pc, #424] @ (800eb38 ) 800e990: 6b9b ldr r3, [r3, #56] @ 0x38 800e992: f3c3 0308 ubfx r3, r3, #0, #9 800e996: ee07 3a90 vmov s15, r3 800e99a: eef8 6a67 vcvt.f32.u32 s13, s15 800e99e: ed97 6a03 vldr s12, [r7, #12] 800e9a2: eddf 5a67 vldr s11, [pc, #412] @ 800eb40 800e9a6: eec6 7a25 vdiv.f32 s15, s12, s11 800e9aa: ee76 7aa7 vadd.f32 s15, s13, s15 800e9ae: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e9b2: ee77 7aa6 vadd.f32 s15, s15, s13 800e9b6: ee67 7a27 vmul.f32 s15, s14, s15 800e9ba: edc7 7a07 vstr s15, [r7, #28] break; 800e9be: e065 b.n 800ea8c case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800e9c0: 697b ldr r3, [r7, #20] 800e9c2: ee07 3a90 vmov s15, r3 800e9c6: eef8 7a67 vcvt.f32.u32 s15, s15 800e9ca: eddf 6a5f vldr s13, [pc, #380] @ 800eb48 800e9ce: ee86 7aa7 vdiv.f32 s14, s13, s15 800e9d2: 4b59 ldr r3, [pc, #356] @ (800eb38 ) 800e9d4: 6b9b ldr r3, [r3, #56] @ 0x38 800e9d6: f3c3 0308 ubfx r3, r3, #0, #9 800e9da: ee07 3a90 vmov s15, r3 800e9de: eef8 6a67 vcvt.f32.u32 s13, s15 800e9e2: ed97 6a03 vldr s12, [r7, #12] 800e9e6: eddf 5a56 vldr s11, [pc, #344] @ 800eb40 800e9ea: eec6 7a25 vdiv.f32 s15, s12, s11 800e9ee: ee76 7aa7 vadd.f32 s15, s13, s15 800e9f2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800e9f6: ee77 7aa6 vadd.f32 s15, s15, s13 800e9fa: ee67 7a27 vmul.f32 s15, s14, s15 800e9fe: edc7 7a07 vstr s15, [r7, #28] break; 800ea02: e043 b.n 800ea8c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800ea04: 697b ldr r3, [r7, #20] 800ea06: ee07 3a90 vmov s15, r3 800ea0a: eef8 7a67 vcvt.f32.u32 s15, s15 800ea0e: eddf 6a4f vldr s13, [pc, #316] @ 800eb4c 800ea12: ee86 7aa7 vdiv.f32 s14, s13, s15 800ea16: 4b48 ldr r3, [pc, #288] @ (800eb38 ) 800ea18: 6b9b ldr r3, [r3, #56] @ 0x38 800ea1a: f3c3 0308 ubfx r3, r3, #0, #9 800ea1e: ee07 3a90 vmov s15, r3 800ea22: eef8 6a67 vcvt.f32.u32 s13, s15 800ea26: ed97 6a03 vldr s12, [r7, #12] 800ea2a: eddf 5a45 vldr s11, [pc, #276] @ 800eb40 800ea2e: eec6 7a25 vdiv.f32 s15, s12, s11 800ea32: ee76 7aa7 vadd.f32 s15, s13, s15 800ea36: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ea3a: ee77 7aa6 vadd.f32 s15, s15, s13 800ea3e: ee67 7a27 vmul.f32 s15, s14, s15 800ea42: edc7 7a07 vstr s15, [r7, #28] break; 800ea46: e021 b.n 800ea8c default: pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); 800ea48: 697b ldr r3, [r7, #20] 800ea4a: ee07 3a90 vmov s15, r3 800ea4e: eef8 7a67 vcvt.f32.u32 s15, s15 800ea52: eddf 6a3d vldr s13, [pc, #244] @ 800eb48 800ea56: ee86 7aa7 vdiv.f32 s14, s13, s15 800ea5a: 4b37 ldr r3, [pc, #220] @ (800eb38 ) 800ea5c: 6b9b ldr r3, [r3, #56] @ 0x38 800ea5e: f3c3 0308 ubfx r3, r3, #0, #9 800ea62: ee07 3a90 vmov s15, r3 800ea66: eef8 6a67 vcvt.f32.u32 s13, s15 800ea6a: ed97 6a03 vldr s12, [r7, #12] 800ea6e: eddf 5a34 vldr s11, [pc, #208] @ 800eb40 800ea72: eec6 7a25 vdiv.f32 s15, s12, s11 800ea76: ee76 7aa7 vadd.f32 s15, s13, s15 800ea7a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ea7e: ee77 7aa6 vadd.f32 s15, s15, s13 800ea82: ee67 7a27 vmul.f32 s15, s14, s15 800ea86: edc7 7a07 vstr s15, [r7, #28] break; 800ea8a: bf00 nop } PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; 800ea8c: 4b2a ldr r3, [pc, #168] @ (800eb38 ) 800ea8e: 6b9b ldr r3, [r3, #56] @ 0x38 800ea90: 0a5b lsrs r3, r3, #9 800ea92: f003 037f and.w r3, r3, #127 @ 0x7f 800ea96: ee07 3a90 vmov s15, r3 800ea9a: eef8 7a67 vcvt.f32.u32 s15, s15 800ea9e: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eaa2: ee37 7a87 vadd.f32 s14, s15, s14 800eaa6: edd7 6a07 vldr s13, [r7, #28] 800eaaa: eec6 7a87 vdiv.f32 s15, s13, s14 800eaae: eefc 7ae7 vcvt.u32.f32 s15, s15 800eab2: ee17 2a90 vmov r2, s15 800eab6: 687b ldr r3, [r7, #4] 800eab8: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; 800eaba: 4b1f ldr r3, [pc, #124] @ (800eb38 ) 800eabc: 6b9b ldr r3, [r3, #56] @ 0x38 800eabe: 0c1b lsrs r3, r3, #16 800eac0: f003 037f and.w r3, r3, #127 @ 0x7f 800eac4: ee07 3a90 vmov s15, r3 800eac8: eef8 7a67 vcvt.f32.u32 s15, s15 800eacc: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ead0: ee37 7a87 vadd.f32 s14, s15, s14 800ead4: edd7 6a07 vldr s13, [r7, #28] 800ead8: eec6 7a87 vdiv.f32 s15, s13, s14 800eadc: eefc 7ae7 vcvt.u32.f32 s15, s15 800eae0: ee17 2a90 vmov r2, s15 800eae4: 687b ldr r3, [r7, #4] 800eae6: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; 800eae8: 4b13 ldr r3, [pc, #76] @ (800eb38 ) 800eaea: 6b9b ldr r3, [r3, #56] @ 0x38 800eaec: 0e1b lsrs r3, r3, #24 800eaee: f003 037f and.w r3, r3, #127 @ 0x7f 800eaf2: ee07 3a90 vmov s15, r3 800eaf6: eef8 7a67 vcvt.f32.u32 s15, s15 800eafa: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eafe: ee37 7a87 vadd.f32 s14, s15, s14 800eb02: edd7 6a07 vldr s13, [r7, #28] 800eb06: eec6 7a87 vdiv.f32 s15, s13, s14 800eb0a: eefc 7ae7 vcvt.u32.f32 s15, s15 800eb0e: ee17 2a90 vmov r2, s15 800eb12: 687b ldr r3, [r7, #4] 800eb14: 609a str r2, [r3, #8] { PLL2_Clocks->PLL2_P_Frequency = 0U; PLL2_Clocks->PLL2_Q_Frequency = 0U; PLL2_Clocks->PLL2_R_Frequency = 0U; } } 800eb16: e008 b.n 800eb2a PLL2_Clocks->PLL2_P_Frequency = 0U; 800eb18: 687b ldr r3, [r7, #4] 800eb1a: 2200 movs r2, #0 800eb1c: 601a str r2, [r3, #0] PLL2_Clocks->PLL2_Q_Frequency = 0U; 800eb1e: 687b ldr r3, [r7, #4] 800eb20: 2200 movs r2, #0 800eb22: 605a str r2, [r3, #4] PLL2_Clocks->PLL2_R_Frequency = 0U; 800eb24: 687b ldr r3, [r7, #4] 800eb26: 2200 movs r2, #0 800eb28: 609a str r2, [r3, #8] } 800eb2a: bf00 nop 800eb2c: 3724 adds r7, #36 @ 0x24 800eb2e: 46bd mov sp, r7 800eb30: f85d 7b04 ldr.w r7, [sp], #4 800eb34: 4770 bx lr 800eb36: bf00 nop 800eb38: 58024400 .word 0x58024400 800eb3c: 03d09000 .word 0x03d09000 800eb40: 46000000 .word 0x46000000 800eb44: 4c742400 .word 0x4c742400 800eb48: 4a742400 .word 0x4a742400 800eb4c: 4bbebc20 .word 0x4bbebc20 0800eb50 : * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL3_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { 800eb50: b480 push {r7} 800eb52: b089 sub sp, #36 @ 0x24 800eb54: af00 add r7, sp, #0 800eb56: 6078 str r0, [r7, #4] float_t fracn3, pll3vco; /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800eb58: 4ba1 ldr r3, [pc, #644] @ (800ede0 ) 800eb5a: 6a9b ldr r3, [r3, #40] @ 0x28 800eb5c: f003 0303 and.w r3, r3, #3 800eb60: 61bb str r3, [r7, #24] pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; 800eb62: 4b9f ldr r3, [pc, #636] @ (800ede0 ) 800eb64: 6a9b ldr r3, [r3, #40] @ 0x28 800eb66: 0d1b lsrs r3, r3, #20 800eb68: f003 033f and.w r3, r3, #63 @ 0x3f 800eb6c: 617b str r3, [r7, #20] pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; 800eb6e: 4b9c ldr r3, [pc, #624] @ (800ede0 ) 800eb70: 6adb ldr r3, [r3, #44] @ 0x2c 800eb72: 0a1b lsrs r3, r3, #8 800eb74: f003 0301 and.w r3, r3, #1 800eb78: 613b str r3, [r7, #16] fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); 800eb7a: 4b99 ldr r3, [pc, #612] @ (800ede0 ) 800eb7c: 6c5b ldr r3, [r3, #68] @ 0x44 800eb7e: 08db lsrs r3, r3, #3 800eb80: f3c3 030c ubfx r3, r3, #0, #13 800eb84: 693a ldr r2, [r7, #16] 800eb86: fb02 f303 mul.w r3, r2, r3 800eb8a: ee07 3a90 vmov s15, r3 800eb8e: eef8 7a67 vcvt.f32.u32 s15, s15 800eb92: edc7 7a03 vstr s15, [r7, #12] if (pll3m != 0U) 800eb96: 697b ldr r3, [r7, #20] 800eb98: 2b00 cmp r3, #0 800eb9a: f000 8111 beq.w 800edc0 { switch (pllsource) 800eb9e: 69bb ldr r3, [r7, #24] 800eba0: 2b02 cmp r3, #2 800eba2: f000 8083 beq.w 800ecac 800eba6: 69bb ldr r3, [r7, #24] 800eba8: 2b02 cmp r3, #2 800ebaa: f200 80a1 bhi.w 800ecf0 800ebae: 69bb ldr r3, [r7, #24] 800ebb0: 2b00 cmp r3, #0 800ebb2: d003 beq.n 800ebbc 800ebb4: 69bb ldr r3, [r7, #24] 800ebb6: 2b01 cmp r3, #1 800ebb8: d056 beq.n 800ec68 800ebba: e099 b.n 800ecf0 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800ebbc: 4b88 ldr r3, [pc, #544] @ (800ede0 ) 800ebbe: 681b ldr r3, [r3, #0] 800ebc0: f003 0320 and.w r3, r3, #32 800ebc4: 2b00 cmp r3, #0 800ebc6: d02d beq.n 800ec24 { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ebc8: 4b85 ldr r3, [pc, #532] @ (800ede0 ) 800ebca: 681b ldr r3, [r3, #0] 800ebcc: 08db lsrs r3, r3, #3 800ebce: f003 0303 and.w r3, r3, #3 800ebd2: 4a84 ldr r2, [pc, #528] @ (800ede4 ) 800ebd4: fa22 f303 lsr.w r3, r2, r3 800ebd8: 60bb str r3, [r7, #8] pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ebda: 68bb ldr r3, [r7, #8] 800ebdc: ee07 3a90 vmov s15, r3 800ebe0: eef8 6a67 vcvt.f32.u32 s13, s15 800ebe4: 697b ldr r3, [r7, #20] 800ebe6: ee07 3a90 vmov s15, r3 800ebea: eef8 7a67 vcvt.f32.u32 s15, s15 800ebee: ee86 7aa7 vdiv.f32 s14, s13, s15 800ebf2: 4b7b ldr r3, [pc, #492] @ (800ede0 ) 800ebf4: 6c1b ldr r3, [r3, #64] @ 0x40 800ebf6: f3c3 0308 ubfx r3, r3, #0, #9 800ebfa: ee07 3a90 vmov s15, r3 800ebfe: eef8 6a67 vcvt.f32.u32 s13, s15 800ec02: ed97 6a03 vldr s12, [r7, #12] 800ec06: eddf 5a78 vldr s11, [pc, #480] @ 800ede8 800ec0a: eec6 7a25 vdiv.f32 s15, s12, s11 800ec0e: ee76 7aa7 vadd.f32 s15, s13, s15 800ec12: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec16: ee77 7aa6 vadd.f32 s15, s15, s13 800ec1a: ee67 7a27 vmul.f32 s15, s14, s15 800ec1e: edc7 7a07 vstr s15, [r7, #28] } else { pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); } break; 800ec22: e087 b.n 800ed34 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ec24: 697b ldr r3, [r7, #20] 800ec26: ee07 3a90 vmov s15, r3 800ec2a: eef8 7a67 vcvt.f32.u32 s15, s15 800ec2e: eddf 6a6f vldr s13, [pc, #444] @ 800edec 800ec32: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec36: 4b6a ldr r3, [pc, #424] @ (800ede0 ) 800ec38: 6c1b ldr r3, [r3, #64] @ 0x40 800ec3a: f3c3 0308 ubfx r3, r3, #0, #9 800ec3e: ee07 3a90 vmov s15, r3 800ec42: eef8 6a67 vcvt.f32.u32 s13, s15 800ec46: ed97 6a03 vldr s12, [r7, #12] 800ec4a: eddf 5a67 vldr s11, [pc, #412] @ 800ede8 800ec4e: eec6 7a25 vdiv.f32 s15, s12, s11 800ec52: ee76 7aa7 vadd.f32 s15, s13, s15 800ec56: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec5a: ee77 7aa6 vadd.f32 s15, s15, s13 800ec5e: ee67 7a27 vmul.f32 s15, s14, s15 800ec62: edc7 7a07 vstr s15, [r7, #28] break; 800ec66: e065 b.n 800ed34 case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ec68: 697b ldr r3, [r7, #20] 800ec6a: ee07 3a90 vmov s15, r3 800ec6e: eef8 7a67 vcvt.f32.u32 s15, s15 800ec72: eddf 6a5f vldr s13, [pc, #380] @ 800edf0 800ec76: ee86 7aa7 vdiv.f32 s14, s13, s15 800ec7a: 4b59 ldr r3, [pc, #356] @ (800ede0 ) 800ec7c: 6c1b ldr r3, [r3, #64] @ 0x40 800ec7e: f3c3 0308 ubfx r3, r3, #0, #9 800ec82: ee07 3a90 vmov s15, r3 800ec86: eef8 6a67 vcvt.f32.u32 s13, s15 800ec8a: ed97 6a03 vldr s12, [r7, #12] 800ec8e: eddf 5a56 vldr s11, [pc, #344] @ 800ede8 800ec92: eec6 7a25 vdiv.f32 s15, s12, s11 800ec96: ee76 7aa7 vadd.f32 s15, s13, s15 800ec9a: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ec9e: ee77 7aa6 vadd.f32 s15, s15, s13 800eca2: ee67 7a27 vmul.f32 s15, s14, s15 800eca6: edc7 7a07 vstr s15, [r7, #28] break; 800ecaa: e043 b.n 800ed34 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ecac: 697b ldr r3, [r7, #20] 800ecae: ee07 3a90 vmov s15, r3 800ecb2: eef8 7a67 vcvt.f32.u32 s15, s15 800ecb6: eddf 6a4f vldr s13, [pc, #316] @ 800edf4 800ecba: ee86 7aa7 vdiv.f32 s14, s13, s15 800ecbe: 4b48 ldr r3, [pc, #288] @ (800ede0 ) 800ecc0: 6c1b ldr r3, [r3, #64] @ 0x40 800ecc2: f3c3 0308 ubfx r3, r3, #0, #9 800ecc6: ee07 3a90 vmov s15, r3 800ecca: eef8 6a67 vcvt.f32.u32 s13, s15 800ecce: ed97 6a03 vldr s12, [r7, #12] 800ecd2: eddf 5a45 vldr s11, [pc, #276] @ 800ede8 800ecd6: eec6 7a25 vdiv.f32 s15, s12, s11 800ecda: ee76 7aa7 vadd.f32 s15, s13, s15 800ecde: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ece2: ee77 7aa6 vadd.f32 s15, s15, s13 800ece6: ee67 7a27 vmul.f32 s15, s14, s15 800ecea: edc7 7a07 vstr s15, [r7, #28] break; 800ecee: e021 b.n 800ed34 default: pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); 800ecf0: 697b ldr r3, [r7, #20] 800ecf2: ee07 3a90 vmov s15, r3 800ecf6: eef8 7a67 vcvt.f32.u32 s15, s15 800ecfa: eddf 6a3d vldr s13, [pc, #244] @ 800edf0 800ecfe: ee86 7aa7 vdiv.f32 s14, s13, s15 800ed02: 4b37 ldr r3, [pc, #220] @ (800ede0 ) 800ed04: 6c1b ldr r3, [r3, #64] @ 0x40 800ed06: f3c3 0308 ubfx r3, r3, #0, #9 800ed0a: ee07 3a90 vmov s15, r3 800ed0e: eef8 6a67 vcvt.f32.u32 s13, s15 800ed12: ed97 6a03 vldr s12, [r7, #12] 800ed16: eddf 5a34 vldr s11, [pc, #208] @ 800ede8 800ed1a: eec6 7a25 vdiv.f32 s15, s12, s11 800ed1e: ee76 7aa7 vadd.f32 s15, s13, s15 800ed22: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ed26: ee77 7aa6 vadd.f32 s15, s15, s13 800ed2a: ee67 7a27 vmul.f32 s15, s14, s15 800ed2e: edc7 7a07 vstr s15, [r7, #28] break; 800ed32: bf00 nop } PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; 800ed34: 4b2a ldr r3, [pc, #168] @ (800ede0 ) 800ed36: 6c1b ldr r3, [r3, #64] @ 0x40 800ed38: 0a5b lsrs r3, r3, #9 800ed3a: f003 037f and.w r3, r3, #127 @ 0x7f 800ed3e: ee07 3a90 vmov s15, r3 800ed42: eef8 7a67 vcvt.f32.u32 s15, s15 800ed46: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed4a: ee37 7a87 vadd.f32 s14, s15, s14 800ed4e: edd7 6a07 vldr s13, [r7, #28] 800ed52: eec6 7a87 vdiv.f32 s15, s13, s14 800ed56: eefc 7ae7 vcvt.u32.f32 s15, s15 800ed5a: ee17 2a90 vmov r2, s15 800ed5e: 687b ldr r3, [r7, #4] 800ed60: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; 800ed62: 4b1f ldr r3, [pc, #124] @ (800ede0 ) 800ed64: 6c1b ldr r3, [r3, #64] @ 0x40 800ed66: 0c1b lsrs r3, r3, #16 800ed68: f003 037f and.w r3, r3, #127 @ 0x7f 800ed6c: ee07 3a90 vmov s15, r3 800ed70: eef8 7a67 vcvt.f32.u32 s15, s15 800ed74: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800ed78: ee37 7a87 vadd.f32 s14, s15, s14 800ed7c: edd7 6a07 vldr s13, [r7, #28] 800ed80: eec6 7a87 vdiv.f32 s15, s13, s14 800ed84: eefc 7ae7 vcvt.u32.f32 s15, s15 800ed88: ee17 2a90 vmov r2, s15 800ed8c: 687b ldr r3, [r7, #4] 800ed8e: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; 800ed90: 4b13 ldr r3, [pc, #76] @ (800ede0 ) 800ed92: 6c1b ldr r3, [r3, #64] @ 0x40 800ed94: 0e1b lsrs r3, r3, #24 800ed96: f003 037f and.w r3, r3, #127 @ 0x7f 800ed9a: ee07 3a90 vmov s15, r3 800ed9e: eef8 7a67 vcvt.f32.u32 s15, s15 800eda2: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eda6: ee37 7a87 vadd.f32 s14, s15, s14 800edaa: edd7 6a07 vldr s13, [r7, #28] 800edae: eec6 7a87 vdiv.f32 s15, s13, s14 800edb2: eefc 7ae7 vcvt.u32.f32 s15, s15 800edb6: ee17 2a90 vmov r2, s15 800edba: 687b ldr r3, [r7, #4] 800edbc: 609a str r2, [r3, #8] PLL3_Clocks->PLL3_P_Frequency = 0U; PLL3_Clocks->PLL3_Q_Frequency = 0U; PLL3_Clocks->PLL3_R_Frequency = 0U; } } 800edbe: e008 b.n 800edd2 PLL3_Clocks->PLL3_P_Frequency = 0U; 800edc0: 687b ldr r3, [r7, #4] 800edc2: 2200 movs r2, #0 800edc4: 601a str r2, [r3, #0] PLL3_Clocks->PLL3_Q_Frequency = 0U; 800edc6: 687b ldr r3, [r7, #4] 800edc8: 2200 movs r2, #0 800edca: 605a str r2, [r3, #4] PLL3_Clocks->PLL3_R_Frequency = 0U; 800edcc: 687b ldr r3, [r7, #4] 800edce: 2200 movs r2, #0 800edd0: 609a str r2, [r3, #8] } 800edd2: bf00 nop 800edd4: 3724 adds r7, #36 @ 0x24 800edd6: 46bd mov sp, r7 800edd8: f85d 7b04 ldr.w r7, [sp], #4 800eddc: 4770 bx lr 800edde: bf00 nop 800ede0: 58024400 .word 0x58024400 800ede4: 03d09000 .word 0x03d09000 800ede8: 46000000 .word 0x46000000 800edec: 4c742400 .word 0x4c742400 800edf0: 4a742400 .word 0x4a742400 800edf4: 4bbebc20 .word 0x4bbebc20 0800edf8 : * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. * @param PLL1_Clocks structure. * @retval None */ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { 800edf8: b480 push {r7} 800edfa: b089 sub sp, #36 @ 0x24 800edfc: af00 add r7, sp, #0 800edfe: 6078 str r0, [r7, #4] uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); 800ee00: 4ba0 ldr r3, [pc, #640] @ (800f084 ) 800ee02: 6a9b ldr r3, [r3, #40] @ 0x28 800ee04: f003 0303 and.w r3, r3, #3 800ee08: 61bb str r3, [r7, #24] pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); 800ee0a: 4b9e ldr r3, [pc, #632] @ (800f084 ) 800ee0c: 6a9b ldr r3, [r3, #40] @ 0x28 800ee0e: 091b lsrs r3, r3, #4 800ee10: f003 033f and.w r3, r3, #63 @ 0x3f 800ee14: 617b str r3, [r7, #20] pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; 800ee16: 4b9b ldr r3, [pc, #620] @ (800f084 ) 800ee18: 6adb ldr r3, [r3, #44] @ 0x2c 800ee1a: f003 0301 and.w r3, r3, #1 800ee1e: 613b str r3, [r7, #16] fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); 800ee20: 4b98 ldr r3, [pc, #608] @ (800f084 ) 800ee22: 6b5b ldr r3, [r3, #52] @ 0x34 800ee24: 08db lsrs r3, r3, #3 800ee26: f3c3 030c ubfx r3, r3, #0, #13 800ee2a: 693a ldr r2, [r7, #16] 800ee2c: fb02 f303 mul.w r3, r2, r3 800ee30: ee07 3a90 vmov s15, r3 800ee34: eef8 7a67 vcvt.f32.u32 s15, s15 800ee38: edc7 7a03 vstr s15, [r7, #12] if (pll1m != 0U) 800ee3c: 697b ldr r3, [r7, #20] 800ee3e: 2b00 cmp r3, #0 800ee40: f000 8111 beq.w 800f066 { switch (pllsource) 800ee44: 69bb ldr r3, [r7, #24] 800ee46: 2b02 cmp r3, #2 800ee48: f000 8083 beq.w 800ef52 800ee4c: 69bb ldr r3, [r7, #24] 800ee4e: 2b02 cmp r3, #2 800ee50: f200 80a1 bhi.w 800ef96 800ee54: 69bb ldr r3, [r7, #24] 800ee56: 2b00 cmp r3, #0 800ee58: d003 beq.n 800ee62 800ee5a: 69bb ldr r3, [r7, #24] 800ee5c: 2b01 cmp r3, #1 800ee5e: d056 beq.n 800ef0e 800ee60: e099 b.n 800ef96 { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 800ee62: 4b88 ldr r3, [pc, #544] @ (800f084 ) 800ee64: 681b ldr r3, [r3, #0] 800ee66: f003 0320 and.w r3, r3, #32 800ee6a: 2b00 cmp r3, #0 800ee6c: d02d beq.n 800eeca { hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); 800ee6e: 4b85 ldr r3, [pc, #532] @ (800f084 ) 800ee70: 681b ldr r3, [r3, #0] 800ee72: 08db lsrs r3, r3, #3 800ee74: f003 0303 and.w r3, r3, #3 800ee78: 4a83 ldr r2, [pc, #524] @ (800f088 ) 800ee7a: fa22 f303 lsr.w r3, r2, r3 800ee7e: 60bb str r3, [r7, #8] pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ee80: 68bb ldr r3, [r7, #8] 800ee82: ee07 3a90 vmov s15, r3 800ee86: eef8 6a67 vcvt.f32.u32 s13, s15 800ee8a: 697b ldr r3, [r7, #20] 800ee8c: ee07 3a90 vmov s15, r3 800ee90: eef8 7a67 vcvt.f32.u32 s15, s15 800ee94: ee86 7aa7 vdiv.f32 s14, s13, s15 800ee98: 4b7a ldr r3, [pc, #488] @ (800f084 ) 800ee9a: 6b1b ldr r3, [r3, #48] @ 0x30 800ee9c: f3c3 0308 ubfx r3, r3, #0, #9 800eea0: ee07 3a90 vmov s15, r3 800eea4: eef8 6a67 vcvt.f32.u32 s13, s15 800eea8: ed97 6a03 vldr s12, [r7, #12] 800eeac: eddf 5a77 vldr s11, [pc, #476] @ 800f08c 800eeb0: eec6 7a25 vdiv.f32 s15, s12, s11 800eeb4: ee76 7aa7 vadd.f32 s15, s13, s15 800eeb8: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800eebc: ee77 7aa6 vadd.f32 s15, s15, s13 800eec0: ee67 7a27 vmul.f32 s15, s14, s15 800eec4: edc7 7a07 vstr s15, [r7, #28] } else { pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); } break; 800eec8: e087 b.n 800efda pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800eeca: 697b ldr r3, [r7, #20] 800eecc: ee07 3a90 vmov s15, r3 800eed0: eef8 7a67 vcvt.f32.u32 s15, s15 800eed4: eddf 6a6e vldr s13, [pc, #440] @ 800f090 800eed8: ee86 7aa7 vdiv.f32 s14, s13, s15 800eedc: 4b69 ldr r3, [pc, #420] @ (800f084 ) 800eede: 6b1b ldr r3, [r3, #48] @ 0x30 800eee0: f3c3 0308 ubfx r3, r3, #0, #9 800eee4: ee07 3a90 vmov s15, r3 800eee8: eef8 6a67 vcvt.f32.u32 s13, s15 800eeec: ed97 6a03 vldr s12, [r7, #12] 800eef0: eddf 5a66 vldr s11, [pc, #408] @ 800f08c 800eef4: eec6 7a25 vdiv.f32 s15, s12, s11 800eef8: ee76 7aa7 vadd.f32 s15, s13, s15 800eefc: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef00: ee77 7aa6 vadd.f32 s15, s15, s13 800ef04: ee67 7a27 vmul.f32 s15, s14, s15 800ef08: edc7 7a07 vstr s15, [r7, #28] break; 800ef0c: e065 b.n 800efda case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef0e: 697b ldr r3, [r7, #20] 800ef10: ee07 3a90 vmov s15, r3 800ef14: eef8 7a67 vcvt.f32.u32 s15, s15 800ef18: eddf 6a5e vldr s13, [pc, #376] @ 800f094 800ef1c: ee86 7aa7 vdiv.f32 s14, s13, s15 800ef20: 4b58 ldr r3, [pc, #352] @ (800f084 ) 800ef22: 6b1b ldr r3, [r3, #48] @ 0x30 800ef24: f3c3 0308 ubfx r3, r3, #0, #9 800ef28: ee07 3a90 vmov s15, r3 800ef2c: eef8 6a67 vcvt.f32.u32 s13, s15 800ef30: ed97 6a03 vldr s12, [r7, #12] 800ef34: eddf 5a55 vldr s11, [pc, #340] @ 800f08c 800ef38: eec6 7a25 vdiv.f32 s15, s12, s11 800ef3c: ee76 7aa7 vadd.f32 s15, s13, s15 800ef40: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef44: ee77 7aa6 vadd.f32 s15, s15, s13 800ef48: ee67 7a27 vmul.f32 s15, s14, s15 800ef4c: edc7 7a07 vstr s15, [r7, #28] break; 800ef50: e043 b.n 800efda case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef52: 697b ldr r3, [r7, #20] 800ef54: ee07 3a90 vmov s15, r3 800ef58: eef8 7a67 vcvt.f32.u32 s15, s15 800ef5c: eddf 6a4e vldr s13, [pc, #312] @ 800f098 800ef60: ee86 7aa7 vdiv.f32 s14, s13, s15 800ef64: 4b47 ldr r3, [pc, #284] @ (800f084 ) 800ef66: 6b1b ldr r3, [r3, #48] @ 0x30 800ef68: f3c3 0308 ubfx r3, r3, #0, #9 800ef6c: ee07 3a90 vmov s15, r3 800ef70: eef8 6a67 vcvt.f32.u32 s13, s15 800ef74: ed97 6a03 vldr s12, [r7, #12] 800ef78: eddf 5a44 vldr s11, [pc, #272] @ 800f08c 800ef7c: eec6 7a25 vdiv.f32 s15, s12, s11 800ef80: ee76 7aa7 vadd.f32 s15, s13, s15 800ef84: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800ef88: ee77 7aa6 vadd.f32 s15, s15, s13 800ef8c: ee67 7a27 vmul.f32 s15, s14, s15 800ef90: edc7 7a07 vstr s15, [r7, #28] break; 800ef94: e021 b.n 800efda default: pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); 800ef96: 697b ldr r3, [r7, #20] 800ef98: ee07 3a90 vmov s15, r3 800ef9c: eef8 7a67 vcvt.f32.u32 s15, s15 800efa0: eddf 6a3b vldr s13, [pc, #236] @ 800f090 800efa4: ee86 7aa7 vdiv.f32 s14, s13, s15 800efa8: 4b36 ldr r3, [pc, #216] @ (800f084 ) 800efaa: 6b1b ldr r3, [r3, #48] @ 0x30 800efac: f3c3 0308 ubfx r3, r3, #0, #9 800efb0: ee07 3a90 vmov s15, r3 800efb4: eef8 6a67 vcvt.f32.u32 s13, s15 800efb8: ed97 6a03 vldr s12, [r7, #12] 800efbc: eddf 5a33 vldr s11, [pc, #204] @ 800f08c 800efc0: eec6 7a25 vdiv.f32 s15, s12, s11 800efc4: ee76 7aa7 vadd.f32 s15, s13, s15 800efc8: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0 800efcc: ee77 7aa6 vadd.f32 s15, s15, s13 800efd0: ee67 7a27 vmul.f32 s15, s14, s15 800efd4: edc7 7a07 vstr s15, [r7, #28] break; 800efd8: bf00 nop } PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; 800efda: 4b2a ldr r3, [pc, #168] @ (800f084 ) 800efdc: 6b1b ldr r3, [r3, #48] @ 0x30 800efde: 0a5b lsrs r3, r3, #9 800efe0: f003 037f and.w r3, r3, #127 @ 0x7f 800efe4: ee07 3a90 vmov s15, r3 800efe8: eef8 7a67 vcvt.f32.u32 s15, s15 800efec: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800eff0: ee37 7a87 vadd.f32 s14, s15, s14 800eff4: edd7 6a07 vldr s13, [r7, #28] 800eff8: eec6 7a87 vdiv.f32 s15, s13, s14 800effc: eefc 7ae7 vcvt.u32.f32 s15, s15 800f000: ee17 2a90 vmov r2, s15 800f004: 687b ldr r3, [r7, #4] 800f006: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; 800f008: 4b1e ldr r3, [pc, #120] @ (800f084 ) 800f00a: 6b1b ldr r3, [r3, #48] @ 0x30 800f00c: 0c1b lsrs r3, r3, #16 800f00e: f003 037f and.w r3, r3, #127 @ 0x7f 800f012: ee07 3a90 vmov s15, r3 800f016: eef8 7a67 vcvt.f32.u32 s15, s15 800f01a: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800f01e: ee37 7a87 vadd.f32 s14, s15, s14 800f022: edd7 6a07 vldr s13, [r7, #28] 800f026: eec6 7a87 vdiv.f32 s15, s13, s14 800f02a: eefc 7ae7 vcvt.u32.f32 s15, s15 800f02e: ee17 2a90 vmov r2, s15 800f032: 687b ldr r3, [r7, #4] 800f034: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; 800f036: 4b13 ldr r3, [pc, #76] @ (800f084 ) 800f038: 6b1b ldr r3, [r3, #48] @ 0x30 800f03a: 0e1b lsrs r3, r3, #24 800f03c: f003 037f and.w r3, r3, #127 @ 0x7f 800f040: ee07 3a90 vmov s15, r3 800f044: eef8 7a67 vcvt.f32.u32 s15, s15 800f048: eeb7 7a00 vmov.f32 s14, #112 @ 0x3f800000 1.0 800f04c: ee37 7a87 vadd.f32 s14, s15, s14 800f050: edd7 6a07 vldr s13, [r7, #28] 800f054: eec6 7a87 vdiv.f32 s15, s13, s14 800f058: eefc 7ae7 vcvt.u32.f32 s15, s15 800f05c: ee17 2a90 vmov r2, s15 800f060: 687b ldr r3, [r7, #4] 800f062: 609a str r2, [r3, #8] PLL1_Clocks->PLL1_P_Frequency = 0U; PLL1_Clocks->PLL1_Q_Frequency = 0U; PLL1_Clocks->PLL1_R_Frequency = 0U; } } 800f064: e008 b.n 800f078 PLL1_Clocks->PLL1_P_Frequency = 0U; 800f066: 687b ldr r3, [r7, #4] 800f068: 2200 movs r2, #0 800f06a: 601a str r2, [r3, #0] PLL1_Clocks->PLL1_Q_Frequency = 0U; 800f06c: 687b ldr r3, [r7, #4] 800f06e: 2200 movs r2, #0 800f070: 605a str r2, [r3, #4] PLL1_Clocks->PLL1_R_Frequency = 0U; 800f072: 687b ldr r3, [r7, #4] 800f074: 2200 movs r2, #0 800f076: 609a str r2, [r3, #8] } 800f078: bf00 nop 800f07a: 3724 adds r7, #36 @ 0x24 800f07c: 46bd mov sp, r7 800f07e: f85d 7b04 ldr.w r7, [sp], #4 800f082: 4770 bx lr 800f084: 58024400 .word 0x58024400 800f088: 03d09000 .word 0x03d09000 800f08c: 46000000 .word 0x46000000 800f090: 4c742400 .word 0x4c742400 800f094: 4a742400 .word 0x4a742400 800f098: 4bbebc20 .word 0x4bbebc20 0800f09c : * @note PLL2 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) { 800f09c: b580 push {r7, lr} 800f09e: b084 sub sp, #16 800f0a0: af00 add r7, sp, #0 800f0a2: 6078 str r0, [r7, #4] 800f0a4: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800f0a6: 2300 movs r3, #0 800f0a8: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800f0aa: 4b53 ldr r3, [pc, #332] @ (800f1f8 ) 800f0ac: 6a9b ldr r3, [r3, #40] @ 0x28 800f0ae: f003 0303 and.w r3, r3, #3 800f0b2: 2b03 cmp r3, #3 800f0b4: d101 bne.n 800f0ba { return HAL_ERROR; 800f0b6: 2301 movs r3, #1 800f0b8: e099 b.n 800f1ee else { /* Disable PLL2. */ __HAL_RCC_PLL2_DISABLE(); 800f0ba: 4b4f ldr r3, [pc, #316] @ (800f1f8 ) 800f0bc: 681b ldr r3, [r3, #0] 800f0be: 4a4e ldr r2, [pc, #312] @ (800f1f8 ) 800f0c0: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 800f0c4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f0c6: f7f6 fead bl 8005e24 800f0ca: 60b8 str r0, [r7, #8] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800f0cc: e008 b.n 800f0e0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800f0ce: f7f6 fea9 bl 8005e24 800f0d2: 4602 mov r2, r0 800f0d4: 68bb ldr r3, [r7, #8] 800f0d6: 1ad3 subs r3, r2, r3 800f0d8: 2b02 cmp r3, #2 800f0da: d901 bls.n 800f0e0 { return HAL_TIMEOUT; 800f0dc: 2303 movs r3, #3 800f0de: e086 b.n 800f1ee while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) 800f0e0: 4b45 ldr r3, [pc, #276] @ (800f1f8 ) 800f0e2: 681b ldr r3, [r3, #0] 800f0e4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f0e8: 2b00 cmp r3, #0 800f0ea: d1f0 bne.n 800f0ce } } /* Configure PLL2 multiplication and division factors. */ __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, 800f0ec: 4b42 ldr r3, [pc, #264] @ (800f1f8 ) 800f0ee: 6a9b ldr r3, [r3, #40] @ 0x28 800f0f0: f423 327c bic.w r2, r3, #258048 @ 0x3f000 800f0f4: 687b ldr r3, [r7, #4] 800f0f6: 681b ldr r3, [r3, #0] 800f0f8: 031b lsls r3, r3, #12 800f0fa: 493f ldr r1, [pc, #252] @ (800f1f8 ) 800f0fc: 4313 orrs r3, r2 800f0fe: 628b str r3, [r1, #40] @ 0x28 800f100: 687b ldr r3, [r7, #4] 800f102: 685b ldr r3, [r3, #4] 800f104: 3b01 subs r3, #1 800f106: f3c3 0208 ubfx r2, r3, #0, #9 800f10a: 687b ldr r3, [r7, #4] 800f10c: 689b ldr r3, [r3, #8] 800f10e: 3b01 subs r3, #1 800f110: 025b lsls r3, r3, #9 800f112: b29b uxth r3, r3 800f114: 431a orrs r2, r3 800f116: 687b ldr r3, [r7, #4] 800f118: 68db ldr r3, [r3, #12] 800f11a: 3b01 subs r3, #1 800f11c: 041b lsls r3, r3, #16 800f11e: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800f122: 431a orrs r2, r3 800f124: 687b ldr r3, [r7, #4] 800f126: 691b ldr r3, [r3, #16] 800f128: 3b01 subs r3, #1 800f12a: 061b lsls r3, r3, #24 800f12c: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800f130: 4931 ldr r1, [pc, #196] @ (800f1f8 ) 800f132: 4313 orrs r3, r2 800f134: 638b str r3, [r1, #56] @ 0x38 pll2->PLL2P, pll2->PLL2Q, pll2->PLL2R); /* Select PLL2 input reference frequency range: VCI */ __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; 800f136: 4b30 ldr r3, [pc, #192] @ (800f1f8 ) 800f138: 6adb ldr r3, [r3, #44] @ 0x2c 800f13a: f023 02c0 bic.w r2, r3, #192 @ 0xc0 800f13e: 687b ldr r3, [r7, #4] 800f140: 695b ldr r3, [r3, #20] 800f142: 492d ldr r1, [pc, #180] @ (800f1f8 ) 800f144: 4313 orrs r3, r2 800f146: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL2 output frequency range : VCO */ __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; 800f148: 4b2b ldr r3, [pc, #172] @ (800f1f8 ) 800f14a: 6adb ldr r3, [r3, #44] @ 0x2c 800f14c: f023 0220 bic.w r2, r3, #32 800f150: 687b ldr r3, [r7, #4] 800f152: 699b ldr r3, [r3, #24] 800f154: 4928 ldr r1, [pc, #160] @ (800f1f8 ) 800f156: 4313 orrs r3, r2 800f158: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_DISABLE(); 800f15a: 4b27 ldr r3, [pc, #156] @ (800f1f8 ) 800f15c: 6adb ldr r3, [r3, #44] @ 0x2c 800f15e: 4a26 ldr r2, [pc, #152] @ (800f1f8 ) 800f160: f023 0310 bic.w r3, r3, #16 800f164: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); 800f166: 4b24 ldr r3, [pc, #144] @ (800f1f8 ) 800f168: 6bda ldr r2, [r3, #60] @ 0x3c 800f16a: 4b24 ldr r3, [pc, #144] @ (800f1fc ) 800f16c: 4013 ands r3, r2 800f16e: 687a ldr r2, [r7, #4] 800f170: 69d2 ldr r2, [r2, #28] 800f172: 00d2 lsls r2, r2, #3 800f174: 4920 ldr r1, [pc, #128] @ (800f1f8 ) 800f176: 4313 orrs r3, r2 800f178: 63cb str r3, [r1, #60] @ 0x3c /* Enable PLL2FRACN . */ __HAL_RCC_PLL2FRACN_ENABLE(); 800f17a: 4b1f ldr r3, [pc, #124] @ (800f1f8 ) 800f17c: 6adb ldr r3, [r3, #44] @ 0x2c 800f17e: 4a1e ldr r2, [pc, #120] @ (800f1f8 ) 800f180: f043 0310 orr.w r3, r3, #16 800f184: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL2 clock output */ if (Divider == DIVIDER_P_UPDATE) 800f186: 683b ldr r3, [r7, #0] 800f188: 2b00 cmp r3, #0 800f18a: d106 bne.n 800f19a { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); 800f18c: 4b1a ldr r3, [pc, #104] @ (800f1f8 ) 800f18e: 6adb ldr r3, [r3, #44] @ 0x2c 800f190: 4a19 ldr r2, [pc, #100] @ (800f1f8 ) 800f192: f443 2300 orr.w r3, r3, #524288 @ 0x80000 800f196: 62d3 str r3, [r2, #44] @ 0x2c 800f198: e00f b.n 800f1ba } else if (Divider == DIVIDER_Q_UPDATE) 800f19a: 683b ldr r3, [r7, #0] 800f19c: 2b01 cmp r3, #1 800f19e: d106 bne.n 800f1ae { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); 800f1a0: 4b15 ldr r3, [pc, #84] @ (800f1f8 ) 800f1a2: 6adb ldr r3, [r3, #44] @ 0x2c 800f1a4: 4a14 ldr r2, [pc, #80] @ (800f1f8 ) 800f1a6: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 800f1aa: 62d3 str r3, [r2, #44] @ 0x2c 800f1ac: e005 b.n 800f1ba } else { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); 800f1ae: 4b12 ldr r3, [pc, #72] @ (800f1f8 ) 800f1b0: 6adb ldr r3, [r3, #44] @ 0x2c 800f1b2: 4a11 ldr r2, [pc, #68] @ (800f1f8 ) 800f1b4: f443 1300 orr.w r3, r3, #2097152 @ 0x200000 800f1b8: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL2. */ __HAL_RCC_PLL2_ENABLE(); 800f1ba: 4b0f ldr r3, [pc, #60] @ (800f1f8 ) 800f1bc: 681b ldr r3, [r3, #0] 800f1be: 4a0e ldr r2, [pc, #56] @ (800f1f8 ) 800f1c0: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 800f1c4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f1c6: f7f6 fe2d bl 8005e24 800f1ca: 60b8 str r0, [r7, #8] /* Wait till PLL2 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800f1cc: e008 b.n 800f1e0 { if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) 800f1ce: f7f6 fe29 bl 8005e24 800f1d2: 4602 mov r2, r0 800f1d4: 68bb ldr r3, [r7, #8] 800f1d6: 1ad3 subs r3, r2, r3 800f1d8: 2b02 cmp r3, #2 800f1da: d901 bls.n 800f1e0 { return HAL_TIMEOUT; 800f1dc: 2303 movs r3, #3 800f1de: e006 b.n 800f1ee while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) 800f1e0: 4b05 ldr r3, [pc, #20] @ (800f1f8 ) 800f1e2: 681b ldr r3, [r3, #0] 800f1e4: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800f1e8: 2b00 cmp r3, #0 800f1ea: d0f0 beq.n 800f1ce } } return status; 800f1ec: 7bfb ldrb r3, [r7, #15] } 800f1ee: 4618 mov r0, r3 800f1f0: 3710 adds r7, #16 800f1f2: 46bd mov sp, r7 800f1f4: bd80 pop {r7, pc} 800f1f6: bf00 nop 800f1f8: 58024400 .word 0x58024400 800f1fc: ffff0007 .word 0xffff0007 0800f200 : * @note PLL3 is temporary disabled to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) { 800f200: b580 push {r7, lr} 800f202: b084 sub sp, #16 800f204: af00 add r7, sp, #0 800f206: 6078 str r0, [r7, #4] 800f208: 6039 str r1, [r7, #0] uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; 800f20a: 2300 movs r3, #0 800f20c: 73fb strb r3, [r7, #15] assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) 800f20e: 4b53 ldr r3, [pc, #332] @ (800f35c ) 800f210: 6a9b ldr r3, [r3, #40] @ 0x28 800f212: f003 0303 and.w r3, r3, #3 800f216: 2b03 cmp r3, #3 800f218: d101 bne.n 800f21e { return HAL_ERROR; 800f21a: 2301 movs r3, #1 800f21c: e099 b.n 800f352 else { /* Disable PLL3. */ __HAL_RCC_PLL3_DISABLE(); 800f21e: 4b4f ldr r3, [pc, #316] @ (800f35c ) 800f220: 681b ldr r3, [r3, #0] 800f222: 4a4e ldr r2, [pc, #312] @ (800f35c ) 800f224: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800f228: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f22a: f7f6 fdfb bl 8005e24 800f22e: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800f230: e008 b.n 800f244 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f232: f7f6 fdf7 bl 8005e24 800f236: 4602 mov r2, r0 800f238: 68bb ldr r3, [r7, #8] 800f23a: 1ad3 subs r3, r2, r3 800f23c: 2b02 cmp r3, #2 800f23e: d901 bls.n 800f244 { return HAL_TIMEOUT; 800f240: 2303 movs r3, #3 800f242: e086 b.n 800f352 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) 800f244: 4b45 ldr r3, [pc, #276] @ (800f35c ) 800f246: 681b ldr r3, [r3, #0] 800f248: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f24c: 2b00 cmp r3, #0 800f24e: d1f0 bne.n 800f232 } } /* Configure the PLL3 multiplication and division factors. */ __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, 800f250: 4b42 ldr r3, [pc, #264] @ (800f35c ) 800f252: 6a9b ldr r3, [r3, #40] @ 0x28 800f254: f023 727c bic.w r2, r3, #66060288 @ 0x3f00000 800f258: 687b ldr r3, [r7, #4] 800f25a: 681b ldr r3, [r3, #0] 800f25c: 051b lsls r3, r3, #20 800f25e: 493f ldr r1, [pc, #252] @ (800f35c ) 800f260: 4313 orrs r3, r2 800f262: 628b str r3, [r1, #40] @ 0x28 800f264: 687b ldr r3, [r7, #4] 800f266: 685b ldr r3, [r3, #4] 800f268: 3b01 subs r3, #1 800f26a: f3c3 0208 ubfx r2, r3, #0, #9 800f26e: 687b ldr r3, [r7, #4] 800f270: 689b ldr r3, [r3, #8] 800f272: 3b01 subs r3, #1 800f274: 025b lsls r3, r3, #9 800f276: b29b uxth r3, r3 800f278: 431a orrs r2, r3 800f27a: 687b ldr r3, [r7, #4] 800f27c: 68db ldr r3, [r3, #12] 800f27e: 3b01 subs r3, #1 800f280: 041b lsls r3, r3, #16 800f282: f403 03fe and.w r3, r3, #8323072 @ 0x7f0000 800f286: 431a orrs r2, r3 800f288: 687b ldr r3, [r7, #4] 800f28a: 691b ldr r3, [r3, #16] 800f28c: 3b01 subs r3, #1 800f28e: 061b lsls r3, r3, #24 800f290: f003 43fe and.w r3, r3, #2130706432 @ 0x7f000000 800f294: 4931 ldr r1, [pc, #196] @ (800f35c ) 800f296: 4313 orrs r3, r2 800f298: 640b str r3, [r1, #64] @ 0x40 pll3->PLL3P, pll3->PLL3Q, pll3->PLL3R); /* Select PLL3 input reference frequency range: VCI */ __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; 800f29a: 4b30 ldr r3, [pc, #192] @ (800f35c ) 800f29c: 6adb ldr r3, [r3, #44] @ 0x2c 800f29e: f423 6240 bic.w r2, r3, #3072 @ 0xc00 800f2a2: 687b ldr r3, [r7, #4] 800f2a4: 695b ldr r3, [r3, #20] 800f2a6: 492d ldr r1, [pc, #180] @ (800f35c ) 800f2a8: 4313 orrs r3, r2 800f2aa: 62cb str r3, [r1, #44] @ 0x2c /* Select PLL3 output frequency range : VCO */ __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; 800f2ac: 4b2b ldr r3, [pc, #172] @ (800f35c ) 800f2ae: 6adb ldr r3, [r3, #44] @ 0x2c 800f2b0: f423 7200 bic.w r2, r3, #512 @ 0x200 800f2b4: 687b ldr r3, [r7, #4] 800f2b6: 699b ldr r3, [r3, #24] 800f2b8: 4928 ldr r1, [pc, #160] @ (800f35c ) 800f2ba: 4313 orrs r3, r2 800f2bc: 62cb str r3, [r1, #44] @ 0x2c /* Disable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_DISABLE(); 800f2be: 4b27 ldr r3, [pc, #156] @ (800f35c ) 800f2c0: 6adb ldr r3, [r3, #44] @ 0x2c 800f2c2: 4a26 ldr r2, [pc, #152] @ (800f35c ) 800f2c4: f423 7380 bic.w r3, r3, #256 @ 0x100 800f2c8: 62d3 str r3, [r2, #44] @ 0x2c /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); 800f2ca: 4b24 ldr r3, [pc, #144] @ (800f35c ) 800f2cc: 6c5a ldr r2, [r3, #68] @ 0x44 800f2ce: 4b24 ldr r3, [pc, #144] @ (800f360 ) 800f2d0: 4013 ands r3, r2 800f2d2: 687a ldr r2, [r7, #4] 800f2d4: 69d2 ldr r2, [r2, #28] 800f2d6: 00d2 lsls r2, r2, #3 800f2d8: 4920 ldr r1, [pc, #128] @ (800f35c ) 800f2da: 4313 orrs r3, r2 800f2dc: 644b str r3, [r1, #68] @ 0x44 /* Enable PLL3FRACN . */ __HAL_RCC_PLL3FRACN_ENABLE(); 800f2de: 4b1f ldr r3, [pc, #124] @ (800f35c ) 800f2e0: 6adb ldr r3, [r3, #44] @ 0x2c 800f2e2: 4a1e ldr r2, [pc, #120] @ (800f35c ) 800f2e4: f443 7380 orr.w r3, r3, #256 @ 0x100 800f2e8: 62d3 str r3, [r2, #44] @ 0x2c /* Enable the PLL3 clock output */ if (Divider == DIVIDER_P_UPDATE) 800f2ea: 683b ldr r3, [r7, #0] 800f2ec: 2b00 cmp r3, #0 800f2ee: d106 bne.n 800f2fe { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); 800f2f0: 4b1a ldr r3, [pc, #104] @ (800f35c ) 800f2f2: 6adb ldr r3, [r3, #44] @ 0x2c 800f2f4: 4a19 ldr r2, [pc, #100] @ (800f35c ) 800f2f6: f443 0380 orr.w r3, r3, #4194304 @ 0x400000 800f2fa: 62d3 str r3, [r2, #44] @ 0x2c 800f2fc: e00f b.n 800f31e } else if (Divider == DIVIDER_Q_UPDATE) 800f2fe: 683b ldr r3, [r7, #0] 800f300: 2b01 cmp r3, #1 800f302: d106 bne.n 800f312 { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); 800f304: 4b15 ldr r3, [pc, #84] @ (800f35c ) 800f306: 6adb ldr r3, [r3, #44] @ 0x2c 800f308: 4a14 ldr r2, [pc, #80] @ (800f35c ) 800f30a: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 800f30e: 62d3 str r3, [r2, #44] @ 0x2c 800f310: e005 b.n 800f31e } else { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); 800f312: 4b12 ldr r3, [pc, #72] @ (800f35c ) 800f314: 6adb ldr r3, [r3, #44] @ 0x2c 800f316: 4a11 ldr r2, [pc, #68] @ (800f35c ) 800f318: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000 800f31c: 62d3 str r3, [r2, #44] @ 0x2c } /* Enable PLL3. */ __HAL_RCC_PLL3_ENABLE(); 800f31e: 4b0f ldr r3, [pc, #60] @ (800f35c ) 800f320: 681b ldr r3, [r3, #0] 800f322: 4a0e ldr r2, [pc, #56] @ (800f35c ) 800f324: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800f328: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800f32a: f7f6 fd7b bl 8005e24 800f32e: 60b8 str r0, [r7, #8] /* Wait till PLL3 is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f330: e008 b.n 800f344 { if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) 800f332: f7f6 fd77 bl 8005e24 800f336: 4602 mov r2, r0 800f338: 68bb ldr r3, [r7, #8] 800f33a: 1ad3 subs r3, r2, r3 800f33c: 2b02 cmp r3, #2 800f33e: d901 bls.n 800f344 { return HAL_TIMEOUT; 800f340: 2303 movs r3, #3 800f342: e006 b.n 800f352 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) 800f344: 4b05 ldr r3, [pc, #20] @ (800f35c ) 800f346: 681b ldr r3, [r3, #0] 800f348: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 800f34c: 2b00 cmp r3, #0 800f34e: d0f0 beq.n 800f332 } } return status; 800f350: 7bfb ldrb r3, [r7, #15] } 800f352: 4618 mov r0, r3 800f354: 3710 adds r7, #16 800f356: 46bd mov sp, r7 800f358: bd80 pop {r7, pc} 800f35a: bf00 nop 800f35c: 58024400 .word 0x58024400 800f360: ffff0007 .word 0xffff0007 0800f364 : * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { 800f364: b580 push {r7, lr} 800f366: b084 sub sp, #16 800f368: af00 add r7, sp, #0 800f36a: 6078 str r0, [r7, #4] uint32_t tickstart; /* Check the RNG handle allocation */ if (hrng == NULL) 800f36c: 687b ldr r3, [r7, #4] 800f36e: 2b00 cmp r3, #0 800f370: d101 bne.n 800f376 { return HAL_ERROR; 800f372: 2301 movs r3, #1 800f374: e054 b.n 800f420 /* Init the low level hardware */ hrng->MspInitCallback(hrng); } #else if (hrng->State == HAL_RNG_STATE_RESET) 800f376: 687b ldr r3, [r7, #4] 800f378: 7a5b ldrb r3, [r3, #9] 800f37a: b2db uxtb r3, r3 800f37c: 2b00 cmp r3, #0 800f37e: d105 bne.n 800f38c { /* Allocate lock resource and initialize it */ hrng->Lock = HAL_UNLOCKED; 800f380: 687b ldr r3, [r7, #4] 800f382: 2200 movs r2, #0 800f384: 721a strb r2, [r3, #8] /* Init the low level hardware */ HAL_RNG_MspInit(hrng); 800f386: 6878 ldr r0, [r7, #4] 800f388: f7f4 ff30 bl 80041ec } #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; 800f38c: 687b ldr r3, [r7, #4] 800f38e: 2202 movs r2, #2 800f390: 725a strb r2, [r3, #9] } } } #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); 800f392: 687b ldr r3, [r7, #4] 800f394: 681b ldr r3, [r3, #0] 800f396: 681b ldr r3, [r3, #0] 800f398: f023 0120 bic.w r1, r3, #32 800f39c: 687b ldr r3, [r7, #4] 800f39e: 685a ldr r2, [r3, #4] 800f3a0: 687b ldr r3, [r7, #4] 800f3a2: 681b ldr r3, [r3, #0] 800f3a4: 430a orrs r2, r1 800f3a6: 601a str r2, [r3, #0] #endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); 800f3a8: 687b ldr r3, [r7, #4] 800f3aa: 681b ldr r3, [r3, #0] 800f3ac: 681a ldr r2, [r3, #0] 800f3ae: 687b ldr r3, [r7, #4] 800f3b0: 681b ldr r3, [r3, #0] 800f3b2: f042 0204 orr.w r2, r2, #4 800f3b6: 601a str r2, [r3, #0] /* verify that no seed error */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) 800f3b8: 687b ldr r3, [r7, #4] 800f3ba: 681b ldr r3, [r3, #0] 800f3bc: 685b ldr r3, [r3, #4] 800f3be: f003 0340 and.w r3, r3, #64 @ 0x40 800f3c2: 2b40 cmp r3, #64 @ 0x40 800f3c4: d104 bne.n 800f3d0 { hrng->State = HAL_RNG_STATE_ERROR; 800f3c6: 687b ldr r3, [r7, #4] 800f3c8: 2204 movs r2, #4 800f3ca: 725a strb r2, [r3, #9] return HAL_ERROR; 800f3cc: 2301 movs r3, #1 800f3ce: e027 b.n 800f420 } /* Get tick */ tickstart = HAL_GetTick(); 800f3d0: f7f6 fd28 bl 8005e24 800f3d4: 60f8 str r0, [r7, #12] /* Check if data register contains valid random data */ while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f3d6: e015 b.n 800f404 { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) 800f3d8: f7f6 fd24 bl 8005e24 800f3dc: 4602 mov r2, r0 800f3de: 68fb ldr r3, [r7, #12] 800f3e0: 1ad3 subs r3, r2, r3 800f3e2: 2b02 cmp r3, #2 800f3e4: d90e bls.n 800f404 { /* New check to avoid false timeout detection in case of preemption */ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f3e6: 687b ldr r3, [r7, #4] 800f3e8: 681b ldr r3, [r3, #0] 800f3ea: 685b ldr r3, [r3, #4] 800f3ec: f003 0304 and.w r3, r3, #4 800f3f0: 2b04 cmp r3, #4 800f3f2: d107 bne.n 800f404 { hrng->State = HAL_RNG_STATE_ERROR; 800f3f4: 687b ldr r3, [r7, #4] 800f3f6: 2204 movs r2, #4 800f3f8: 725a strb r2, [r3, #9] hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; 800f3fa: 687b ldr r3, [r7, #4] 800f3fc: 2202 movs r2, #2 800f3fe: 60da str r2, [r3, #12] return HAL_ERROR; 800f400: 2301 movs r3, #1 800f402: e00d b.n 800f420 while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) 800f404: 687b ldr r3, [r7, #4] 800f406: 681b ldr r3, [r3, #0] 800f408: 685b ldr r3, [r3, #4] 800f40a: f003 0304 and.w r3, r3, #4 800f40e: 2b04 cmp r3, #4 800f410: d0e2 beq.n 800f3d8 } } } /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; 800f412: 687b ldr r3, [r7, #4] 800f414: 2201 movs r2, #1 800f416: 725a strb r2, [r3, #9] /* Initialise the error code */ hrng->ErrorCode = HAL_RNG_ERROR_NONE; 800f418: 687b ldr r3, [r7, #4] 800f41a: 2200 movs r2, #0 800f41c: 60da str r2, [r3, #12] /* Return function status */ return HAL_OK; 800f41e: 2300 movs r3, #0 } 800f420: 4618 mov r0, r3 800f422: 3710 adds r7, #16 800f424: 46bd mov sp, r7 800f426: bd80 pop {r7, pc} 0800f428 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800f428: b580 push {r7, lr} 800f42a: b082 sub sp, #8 800f42c: af00 add r7, sp, #0 800f42e: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f430: 687b ldr r3, [r7, #4] 800f432: 2b00 cmp r3, #0 800f434: d101 bne.n 800f43a { return HAL_ERROR; 800f436: 2301 movs r3, #1 800f438: e049 b.n 800f4ce assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f43a: 687b ldr r3, [r7, #4] 800f43c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f440: b2db uxtb r3, r3 800f442: 2b00 cmp r3, #0 800f444: d106 bne.n 800f454 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f446: 687b ldr r3, [r7, #4] 800f448: 2200 movs r2, #0 800f44a: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800f44e: 6878 ldr r0, [r7, #4] 800f450: f7f4 ff40 bl 80042d4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f454: 687b ldr r3, [r7, #4] 800f456: 2202 movs r2, #2 800f458: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f45c: 687b ldr r3, [r7, #4] 800f45e: 681a ldr r2, [r3, #0] 800f460: 687b ldr r3, [r7, #4] 800f462: 3304 adds r3, #4 800f464: 4619 mov r1, r3 800f466: 4610 mov r0, r2 800f468: f001 f918 bl 801069c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f46c: 687b ldr r3, [r7, #4] 800f46e: 2201 movs r2, #1 800f470: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f474: 687b ldr r3, [r7, #4] 800f476: 2201 movs r2, #1 800f478: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f47c: 687b ldr r3, [r7, #4] 800f47e: 2201 movs r2, #1 800f480: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f484: 687b ldr r3, [r7, #4] 800f486: 2201 movs r2, #1 800f488: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f48c: 687b ldr r3, [r7, #4] 800f48e: 2201 movs r2, #1 800f490: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f494: 687b ldr r3, [r7, #4] 800f496: 2201 movs r2, #1 800f498: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f49c: 687b ldr r3, [r7, #4] 800f49e: 2201 movs r2, #1 800f4a0: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f4a4: 687b ldr r3, [r7, #4] 800f4a6: 2201 movs r2, #1 800f4a8: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f4ac: 687b ldr r3, [r7, #4] 800f4ae: 2201 movs r2, #1 800f4b0: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f4b4: 687b ldr r3, [r7, #4] 800f4b6: 2201 movs r2, #1 800f4b8: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f4bc: 687b ldr r3, [r7, #4] 800f4be: 2201 movs r2, #1 800f4c0: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f4c4: 687b ldr r3, [r7, #4] 800f4c6: 2201 movs r2, #1 800f4c8: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f4cc: 2300 movs r3, #0 } 800f4ce: 4618 mov r0, r3 800f4d0: 3708 adds r7, #8 800f4d2: 46bd mov sp, r7 800f4d4: bd80 pop {r7, pc} ... 0800f4d8 : * @brief Starts the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { 800f4d8: b480 push {r7} 800f4da: b085 sub sp, #20 800f4dc: af00 add r7, sp, #0 800f4de: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f4e0: 687b ldr r3, [r7, #4] 800f4e2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f4e6: b2db uxtb r3, r3 800f4e8: 2b01 cmp r3, #1 800f4ea: d001 beq.n 800f4f0 { return HAL_ERROR; 800f4ec: 2301 movs r3, #1 800f4ee: e04c b.n 800f58a } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f4f0: 687b ldr r3, [r7, #4] 800f4f2: 2202 movs r2, #2 800f4f4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f4f8: 687b ldr r3, [r7, #4] 800f4fa: 681b ldr r3, [r3, #0] 800f4fc: 4a26 ldr r2, [pc, #152] @ (800f598 ) 800f4fe: 4293 cmp r3, r2 800f500: d022 beq.n 800f548 800f502: 687b ldr r3, [r7, #4] 800f504: 681b ldr r3, [r3, #0] 800f506: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f50a: d01d beq.n 800f548 800f50c: 687b ldr r3, [r7, #4] 800f50e: 681b ldr r3, [r3, #0] 800f510: 4a22 ldr r2, [pc, #136] @ (800f59c ) 800f512: 4293 cmp r3, r2 800f514: d018 beq.n 800f548 800f516: 687b ldr r3, [r7, #4] 800f518: 681b ldr r3, [r3, #0] 800f51a: 4a21 ldr r2, [pc, #132] @ (800f5a0 ) 800f51c: 4293 cmp r3, r2 800f51e: d013 beq.n 800f548 800f520: 687b ldr r3, [r7, #4] 800f522: 681b ldr r3, [r3, #0] 800f524: 4a1f ldr r2, [pc, #124] @ (800f5a4 ) 800f526: 4293 cmp r3, r2 800f528: d00e beq.n 800f548 800f52a: 687b ldr r3, [r7, #4] 800f52c: 681b ldr r3, [r3, #0] 800f52e: 4a1e ldr r2, [pc, #120] @ (800f5a8 ) 800f530: 4293 cmp r3, r2 800f532: d009 beq.n 800f548 800f534: 687b ldr r3, [r7, #4] 800f536: 681b ldr r3, [r3, #0] 800f538: 4a1c ldr r2, [pc, #112] @ (800f5ac ) 800f53a: 4293 cmp r3, r2 800f53c: d004 beq.n 800f548 800f53e: 687b ldr r3, [r7, #4] 800f540: 681b ldr r3, [r3, #0] 800f542: 4a1b ldr r2, [pc, #108] @ (800f5b0 ) 800f544: 4293 cmp r3, r2 800f546: d115 bne.n 800f574 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f548: 687b ldr r3, [r7, #4] 800f54a: 681b ldr r3, [r3, #0] 800f54c: 689a ldr r2, [r3, #8] 800f54e: 4b19 ldr r3, [pc, #100] @ (800f5b4 ) 800f550: 4013 ands r3, r2 800f552: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f554: 68fb ldr r3, [r7, #12] 800f556: 2b06 cmp r3, #6 800f558: d015 beq.n 800f586 800f55a: 68fb ldr r3, [r7, #12] 800f55c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f560: d011 beq.n 800f586 { __HAL_TIM_ENABLE(htim); 800f562: 687b ldr r3, [r7, #4] 800f564: 681b ldr r3, [r3, #0] 800f566: 681a ldr r2, [r3, #0] 800f568: 687b ldr r3, [r7, #4] 800f56a: 681b ldr r3, [r3, #0] 800f56c: f042 0201 orr.w r2, r2, #1 800f570: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f572: e008 b.n 800f586 } } else { __HAL_TIM_ENABLE(htim); 800f574: 687b ldr r3, [r7, #4] 800f576: 681b ldr r3, [r3, #0] 800f578: 681a ldr r2, [r3, #0] 800f57a: 687b ldr r3, [r7, #4] 800f57c: 681b ldr r3, [r3, #0] 800f57e: f042 0201 orr.w r2, r2, #1 800f582: 601a str r2, [r3, #0] 800f584: e000 b.n 800f588 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f586: bf00 nop } /* Return function status */ return HAL_OK; 800f588: 2300 movs r3, #0 } 800f58a: 4618 mov r0, r3 800f58c: 3714 adds r7, #20 800f58e: 46bd mov sp, r7 800f590: f85d 7b04 ldr.w r7, [sp], #4 800f594: 4770 bx lr 800f596: bf00 nop 800f598: 40010000 .word 0x40010000 800f59c: 40000400 .word 0x40000400 800f5a0: 40000800 .word 0x40000800 800f5a4: 40000c00 .word 0x40000c00 800f5a8: 40010400 .word 0x40010400 800f5ac: 40001800 .word 0x40001800 800f5b0: 40014000 .word 0x40014000 800f5b4: 00010007 .word 0x00010007 0800f5b8 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 800f5b8: b480 push {r7} 800f5ba: b085 sub sp, #20 800f5bc: af00 add r7, sp, #0 800f5be: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 800f5c0: 687b ldr r3, [r7, #4] 800f5c2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f5c6: b2db uxtb r3, r3 800f5c8: 2b01 cmp r3, #1 800f5ca: d001 beq.n 800f5d0 { return HAL_ERROR; 800f5cc: 2301 movs r3, #1 800f5ce: e054 b.n 800f67a } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f5d0: 687b ldr r3, [r7, #4] 800f5d2: 2202 movs r2, #2 800f5d4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 800f5d8: 687b ldr r3, [r7, #4] 800f5da: 681b ldr r3, [r3, #0] 800f5dc: 68da ldr r2, [r3, #12] 800f5de: 687b ldr r3, [r7, #4] 800f5e0: 681b ldr r3, [r3, #0] 800f5e2: f042 0201 orr.w r2, r2, #1 800f5e6: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f5e8: 687b ldr r3, [r7, #4] 800f5ea: 681b ldr r3, [r3, #0] 800f5ec: 4a26 ldr r2, [pc, #152] @ (800f688 ) 800f5ee: 4293 cmp r3, r2 800f5f0: d022 beq.n 800f638 800f5f2: 687b ldr r3, [r7, #4] 800f5f4: 681b ldr r3, [r3, #0] 800f5f6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f5fa: d01d beq.n 800f638 800f5fc: 687b ldr r3, [r7, #4] 800f5fe: 681b ldr r3, [r3, #0] 800f600: 4a22 ldr r2, [pc, #136] @ (800f68c ) 800f602: 4293 cmp r3, r2 800f604: d018 beq.n 800f638 800f606: 687b ldr r3, [r7, #4] 800f608: 681b ldr r3, [r3, #0] 800f60a: 4a21 ldr r2, [pc, #132] @ (800f690 ) 800f60c: 4293 cmp r3, r2 800f60e: d013 beq.n 800f638 800f610: 687b ldr r3, [r7, #4] 800f612: 681b ldr r3, [r3, #0] 800f614: 4a1f ldr r2, [pc, #124] @ (800f694 ) 800f616: 4293 cmp r3, r2 800f618: d00e beq.n 800f638 800f61a: 687b ldr r3, [r7, #4] 800f61c: 681b ldr r3, [r3, #0] 800f61e: 4a1e ldr r2, [pc, #120] @ (800f698 ) 800f620: 4293 cmp r3, r2 800f622: d009 beq.n 800f638 800f624: 687b ldr r3, [r7, #4] 800f626: 681b ldr r3, [r3, #0] 800f628: 4a1c ldr r2, [pc, #112] @ (800f69c ) 800f62a: 4293 cmp r3, r2 800f62c: d004 beq.n 800f638 800f62e: 687b ldr r3, [r7, #4] 800f630: 681b ldr r3, [r3, #0] 800f632: 4a1b ldr r2, [pc, #108] @ (800f6a0 ) 800f634: 4293 cmp r3, r2 800f636: d115 bne.n 800f664 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f638: 687b ldr r3, [r7, #4] 800f63a: 681b ldr r3, [r3, #0] 800f63c: 689a ldr r2, [r3, #8] 800f63e: 4b19 ldr r3, [pc, #100] @ (800f6a4 ) 800f640: 4013 ands r3, r2 800f642: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f644: 68fb ldr r3, [r7, #12] 800f646: 2b06 cmp r3, #6 800f648: d015 beq.n 800f676 800f64a: 68fb ldr r3, [r7, #12] 800f64c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f650: d011 beq.n 800f676 { __HAL_TIM_ENABLE(htim); 800f652: 687b ldr r3, [r7, #4] 800f654: 681b ldr r3, [r3, #0] 800f656: 681a ldr r2, [r3, #0] 800f658: 687b ldr r3, [r7, #4] 800f65a: 681b ldr r3, [r3, #0] 800f65c: f042 0201 orr.w r2, r2, #1 800f660: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f662: e008 b.n 800f676 } } else { __HAL_TIM_ENABLE(htim); 800f664: 687b ldr r3, [r7, #4] 800f666: 681b ldr r3, [r3, #0] 800f668: 681a ldr r2, [r3, #0] 800f66a: 687b ldr r3, [r7, #4] 800f66c: 681b ldr r3, [r3, #0] 800f66e: f042 0201 orr.w r2, r2, #1 800f672: 601a str r2, [r3, #0] 800f674: e000 b.n 800f678 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f676: bf00 nop } /* Return function status */ return HAL_OK; 800f678: 2300 movs r3, #0 } 800f67a: 4618 mov r0, r3 800f67c: 3714 adds r7, #20 800f67e: 46bd mov sp, r7 800f680: f85d 7b04 ldr.w r7, [sp], #4 800f684: 4770 bx lr 800f686: bf00 nop 800f688: 40010000 .word 0x40010000 800f68c: 40000400 .word 0x40000400 800f690: 40000800 .word 0x40000800 800f694: 40000c00 .word 0x40000c00 800f698: 40010400 .word 0x40010400 800f69c: 40001800 .word 0x40001800 800f6a0: 40014000 .word 0x40014000 800f6a4: 00010007 .word 0x00010007 0800f6a8 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 800f6a8: b580 push {r7, lr} 800f6aa: b082 sub sp, #8 800f6ac: af00 add r7, sp, #0 800f6ae: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800f6b0: 687b ldr r3, [r7, #4] 800f6b2: 2b00 cmp r3, #0 800f6b4: d101 bne.n 800f6ba { return HAL_ERROR; 800f6b6: 2301 movs r3, #1 800f6b8: e049 b.n 800f74e assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800f6ba: 687b ldr r3, [r7, #4] 800f6bc: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800f6c0: b2db uxtb r3, r3 800f6c2: 2b00 cmp r3, #0 800f6c4: d106 bne.n 800f6d4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800f6c6: 687b ldr r3, [r7, #4] 800f6c8: 2200 movs r2, #0 800f6ca: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800f6ce: 6878 ldr r0, [r7, #4] 800f6d0: f7f4 fdc6 bl 8004260 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800f6d4: 687b ldr r3, [r7, #4] 800f6d6: 2202 movs r2, #2 800f6d8: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800f6dc: 687b ldr r3, [r7, #4] 800f6de: 681a ldr r2, [r3, #0] 800f6e0: 687b ldr r3, [r7, #4] 800f6e2: 3304 adds r3, #4 800f6e4: 4619 mov r1, r3 800f6e6: 4610 mov r0, r2 800f6e8: f000 ffd8 bl 801069c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800f6ec: 687b ldr r3, [r7, #4] 800f6ee: 2201 movs r2, #1 800f6f0: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f6f4: 687b ldr r3, [r7, #4] 800f6f6: 2201 movs r2, #1 800f6f8: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f6fc: 687b ldr r3, [r7, #4] 800f6fe: 2201 movs r2, #1 800f700: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f704: 687b ldr r3, [r7, #4] 800f706: 2201 movs r2, #1 800f708: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f70c: 687b ldr r3, [r7, #4] 800f70e: 2201 movs r2, #1 800f710: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f714: 687b ldr r3, [r7, #4] 800f716: 2201 movs r2, #1 800f718: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f71c: 687b ldr r3, [r7, #4] 800f71e: 2201 movs r2, #1 800f720: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800f724: 687b ldr r3, [r7, #4] 800f726: 2201 movs r2, #1 800f728: f883 2044 strb.w r2, [r3, #68] @ 0x44 800f72c: 687b ldr r3, [r7, #4] 800f72e: 2201 movs r2, #1 800f730: f883 2045 strb.w r2, [r3, #69] @ 0x45 800f734: 687b ldr r3, [r7, #4] 800f736: 2201 movs r2, #1 800f738: f883 2046 strb.w r2, [r3, #70] @ 0x46 800f73c: 687b ldr r3, [r7, #4] 800f73e: 2201 movs r2, #1 800f740: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800f744: 687b ldr r3, [r7, #4] 800f746: 2201 movs r2, #1 800f748: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800f74c: 2300 movs r3, #0 } 800f74e: 4618 mov r0, r3 800f750: 3708 adds r7, #8 800f752: 46bd mov sp, r7 800f754: bd80 pop {r7, pc} ... 0800f758 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f758: b580 push {r7, lr} 800f75a: b084 sub sp, #16 800f75c: af00 add r7, sp, #0 800f75e: 6078 str r0, [r7, #4] 800f760: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 800f762: 683b ldr r3, [r7, #0] 800f764: 2b00 cmp r3, #0 800f766: d109 bne.n 800f77c 800f768: 687b ldr r3, [r7, #4] 800f76a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800f76e: b2db uxtb r3, r3 800f770: 2b01 cmp r3, #1 800f772: bf14 ite ne 800f774: 2301 movne r3, #1 800f776: 2300 moveq r3, #0 800f778: b2db uxtb r3, r3 800f77a: e03c b.n 800f7f6 800f77c: 683b ldr r3, [r7, #0] 800f77e: 2b04 cmp r3, #4 800f780: d109 bne.n 800f796 800f782: 687b ldr r3, [r7, #4] 800f784: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800f788: b2db uxtb r3, r3 800f78a: 2b01 cmp r3, #1 800f78c: bf14 ite ne 800f78e: 2301 movne r3, #1 800f790: 2300 moveq r3, #0 800f792: b2db uxtb r3, r3 800f794: e02f b.n 800f7f6 800f796: 683b ldr r3, [r7, #0] 800f798: 2b08 cmp r3, #8 800f79a: d109 bne.n 800f7b0 800f79c: 687b ldr r3, [r7, #4] 800f79e: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800f7a2: b2db uxtb r3, r3 800f7a4: 2b01 cmp r3, #1 800f7a6: bf14 ite ne 800f7a8: 2301 movne r3, #1 800f7aa: 2300 moveq r3, #0 800f7ac: b2db uxtb r3, r3 800f7ae: e022 b.n 800f7f6 800f7b0: 683b ldr r3, [r7, #0] 800f7b2: 2b0c cmp r3, #12 800f7b4: d109 bne.n 800f7ca 800f7b6: 687b ldr r3, [r7, #4] 800f7b8: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800f7bc: b2db uxtb r3, r3 800f7be: 2b01 cmp r3, #1 800f7c0: bf14 ite ne 800f7c2: 2301 movne r3, #1 800f7c4: 2300 moveq r3, #0 800f7c6: b2db uxtb r3, r3 800f7c8: e015 b.n 800f7f6 800f7ca: 683b ldr r3, [r7, #0] 800f7cc: 2b10 cmp r3, #16 800f7ce: d109 bne.n 800f7e4 800f7d0: 687b ldr r3, [r7, #4] 800f7d2: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800f7d6: b2db uxtb r3, r3 800f7d8: 2b01 cmp r3, #1 800f7da: bf14 ite ne 800f7dc: 2301 movne r3, #1 800f7de: 2300 moveq r3, #0 800f7e0: b2db uxtb r3, r3 800f7e2: e008 b.n 800f7f6 800f7e4: 687b ldr r3, [r7, #4] 800f7e6: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800f7ea: b2db uxtb r3, r3 800f7ec: 2b01 cmp r3, #1 800f7ee: bf14 ite ne 800f7f0: 2301 movne r3, #1 800f7f2: 2300 moveq r3, #0 800f7f4: b2db uxtb r3, r3 800f7f6: 2b00 cmp r3, #0 800f7f8: d001 beq.n 800f7fe { return HAL_ERROR; 800f7fa: 2301 movs r3, #1 800f7fc: e0a1 b.n 800f942 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800f7fe: 683b ldr r3, [r7, #0] 800f800: 2b00 cmp r3, #0 800f802: d104 bne.n 800f80e 800f804: 687b ldr r3, [r7, #4] 800f806: 2202 movs r2, #2 800f808: f883 203e strb.w r2, [r3, #62] @ 0x3e 800f80c: e023 b.n 800f856 800f80e: 683b ldr r3, [r7, #0] 800f810: 2b04 cmp r3, #4 800f812: d104 bne.n 800f81e 800f814: 687b ldr r3, [r7, #4] 800f816: 2202 movs r2, #2 800f818: f883 203f strb.w r2, [r3, #63] @ 0x3f 800f81c: e01b b.n 800f856 800f81e: 683b ldr r3, [r7, #0] 800f820: 2b08 cmp r3, #8 800f822: d104 bne.n 800f82e 800f824: 687b ldr r3, [r7, #4] 800f826: 2202 movs r2, #2 800f828: f883 2040 strb.w r2, [r3, #64] @ 0x40 800f82c: e013 b.n 800f856 800f82e: 683b ldr r3, [r7, #0] 800f830: 2b0c cmp r3, #12 800f832: d104 bne.n 800f83e 800f834: 687b ldr r3, [r7, #4] 800f836: 2202 movs r2, #2 800f838: f883 2041 strb.w r2, [r3, #65] @ 0x41 800f83c: e00b b.n 800f856 800f83e: 683b ldr r3, [r7, #0] 800f840: 2b10 cmp r3, #16 800f842: d104 bne.n 800f84e 800f844: 687b ldr r3, [r7, #4] 800f846: 2202 movs r2, #2 800f848: f883 2042 strb.w r2, [r3, #66] @ 0x42 800f84c: e003 b.n 800f856 800f84e: 687b ldr r3, [r7, #4] 800f850: 2202 movs r2, #2 800f852: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800f856: 687b ldr r3, [r7, #4] 800f858: 681b ldr r3, [r3, #0] 800f85a: 2201 movs r2, #1 800f85c: 6839 ldr r1, [r7, #0] 800f85e: 4618 mov r0, r3 800f860: f001 fc60 bl 8011124 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f864: 687b ldr r3, [r7, #4] 800f866: 681b ldr r3, [r3, #0] 800f868: 4a38 ldr r2, [pc, #224] @ (800f94c ) 800f86a: 4293 cmp r3, r2 800f86c: d013 beq.n 800f896 800f86e: 687b ldr r3, [r7, #4] 800f870: 681b ldr r3, [r3, #0] 800f872: 4a37 ldr r2, [pc, #220] @ (800f950 ) 800f874: 4293 cmp r3, r2 800f876: d00e beq.n 800f896 800f878: 687b ldr r3, [r7, #4] 800f87a: 681b ldr r3, [r3, #0] 800f87c: 4a35 ldr r2, [pc, #212] @ (800f954 ) 800f87e: 4293 cmp r3, r2 800f880: d009 beq.n 800f896 800f882: 687b ldr r3, [r7, #4] 800f884: 681b ldr r3, [r3, #0] 800f886: 4a34 ldr r2, [pc, #208] @ (800f958 ) 800f888: 4293 cmp r3, r2 800f88a: d004 beq.n 800f896 800f88c: 687b ldr r3, [r7, #4] 800f88e: 681b ldr r3, [r3, #0] 800f890: 4a32 ldr r2, [pc, #200] @ (800f95c ) 800f892: 4293 cmp r3, r2 800f894: d101 bne.n 800f89a 800f896: 2301 movs r3, #1 800f898: e000 b.n 800f89c 800f89a: 2300 movs r3, #0 800f89c: 2b00 cmp r3, #0 800f89e: d007 beq.n 800f8b0 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 800f8a0: 687b ldr r3, [r7, #4] 800f8a2: 681b ldr r3, [r3, #0] 800f8a4: 6c5a ldr r2, [r3, #68] @ 0x44 800f8a6: 687b ldr r3, [r7, #4] 800f8a8: 681b ldr r3, [r3, #0] 800f8aa: f442 4200 orr.w r2, r2, #32768 @ 0x8000 800f8ae: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800f8b0: 687b ldr r3, [r7, #4] 800f8b2: 681b ldr r3, [r3, #0] 800f8b4: 4a25 ldr r2, [pc, #148] @ (800f94c ) 800f8b6: 4293 cmp r3, r2 800f8b8: d022 beq.n 800f900 800f8ba: 687b ldr r3, [r7, #4] 800f8bc: 681b ldr r3, [r3, #0] 800f8be: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800f8c2: d01d beq.n 800f900 800f8c4: 687b ldr r3, [r7, #4] 800f8c6: 681b ldr r3, [r3, #0] 800f8c8: 4a25 ldr r2, [pc, #148] @ (800f960 ) 800f8ca: 4293 cmp r3, r2 800f8cc: d018 beq.n 800f900 800f8ce: 687b ldr r3, [r7, #4] 800f8d0: 681b ldr r3, [r3, #0] 800f8d2: 4a24 ldr r2, [pc, #144] @ (800f964 ) 800f8d4: 4293 cmp r3, r2 800f8d6: d013 beq.n 800f900 800f8d8: 687b ldr r3, [r7, #4] 800f8da: 681b ldr r3, [r3, #0] 800f8dc: 4a22 ldr r2, [pc, #136] @ (800f968 ) 800f8de: 4293 cmp r3, r2 800f8e0: d00e beq.n 800f900 800f8e2: 687b ldr r3, [r7, #4] 800f8e4: 681b ldr r3, [r3, #0] 800f8e6: 4a1a ldr r2, [pc, #104] @ (800f950 ) 800f8e8: 4293 cmp r3, r2 800f8ea: d009 beq.n 800f900 800f8ec: 687b ldr r3, [r7, #4] 800f8ee: 681b ldr r3, [r3, #0] 800f8f0: 4a1e ldr r2, [pc, #120] @ (800f96c ) 800f8f2: 4293 cmp r3, r2 800f8f4: d004 beq.n 800f900 800f8f6: 687b ldr r3, [r7, #4] 800f8f8: 681b ldr r3, [r3, #0] 800f8fa: 4a16 ldr r2, [pc, #88] @ (800f954 ) 800f8fc: 4293 cmp r3, r2 800f8fe: d115 bne.n 800f92c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800f900: 687b ldr r3, [r7, #4] 800f902: 681b ldr r3, [r3, #0] 800f904: 689a ldr r2, [r3, #8] 800f906: 4b1a ldr r3, [pc, #104] @ (800f970 ) 800f908: 4013 ands r3, r2 800f90a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f90c: 68fb ldr r3, [r7, #12] 800f90e: 2b06 cmp r3, #6 800f910: d015 beq.n 800f93e 800f912: 68fb ldr r3, [r7, #12] 800f914: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800f918: d011 beq.n 800f93e { __HAL_TIM_ENABLE(htim); 800f91a: 687b ldr r3, [r7, #4] 800f91c: 681b ldr r3, [r3, #0] 800f91e: 681a ldr r2, [r3, #0] 800f920: 687b ldr r3, [r7, #4] 800f922: 681b ldr r3, [r3, #0] 800f924: f042 0201 orr.w r2, r2, #1 800f928: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f92a: e008 b.n 800f93e } } else { __HAL_TIM_ENABLE(htim); 800f92c: 687b ldr r3, [r7, #4] 800f92e: 681b ldr r3, [r3, #0] 800f930: 681a ldr r2, [r3, #0] 800f932: 687b ldr r3, [r7, #4] 800f934: 681b ldr r3, [r3, #0] 800f936: f042 0201 orr.w r2, r2, #1 800f93a: 601a str r2, [r3, #0] 800f93c: e000 b.n 800f940 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800f93e: bf00 nop } /* Return function status */ return HAL_OK; 800f940: 2300 movs r3, #0 } 800f942: 4618 mov r0, r3 800f944: 3710 adds r7, #16 800f946: 46bd mov sp, r7 800f948: bd80 pop {r7, pc} 800f94a: bf00 nop 800f94c: 40010000 .word 0x40010000 800f950: 40010400 .word 0x40010400 800f954: 40014000 .word 0x40014000 800f958: 40014400 .word 0x40014400 800f95c: 40014800 .word 0x40014800 800f960: 40000400 .word 0x40000400 800f964: 40000800 .word 0x40000800 800f968: 40000c00 .word 0x40000c00 800f96c: 40001800 .word 0x40001800 800f970: 00010007 .word 0x00010007 0800f974 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { 800f974: b580 push {r7, lr} 800f976: b082 sub sp, #8 800f978: af00 add r7, sp, #0 800f97a: 6078 str r0, [r7, #4] 800f97c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 800f97e: 687b ldr r3, [r7, #4] 800f980: 681b ldr r3, [r3, #0] 800f982: 2200 movs r2, #0 800f984: 6839 ldr r1, [r7, #0] 800f986: 4618 mov r0, r3 800f988: f001 fbcc bl 8011124 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 800f98c: 687b ldr r3, [r7, #4] 800f98e: 681b ldr r3, [r3, #0] 800f990: 4a3e ldr r2, [pc, #248] @ (800fa8c ) 800f992: 4293 cmp r3, r2 800f994: d013 beq.n 800f9be 800f996: 687b ldr r3, [r7, #4] 800f998: 681b ldr r3, [r3, #0] 800f99a: 4a3d ldr r2, [pc, #244] @ (800fa90 ) 800f99c: 4293 cmp r3, r2 800f99e: d00e beq.n 800f9be 800f9a0: 687b ldr r3, [r7, #4] 800f9a2: 681b ldr r3, [r3, #0] 800f9a4: 4a3b ldr r2, [pc, #236] @ (800fa94 ) 800f9a6: 4293 cmp r3, r2 800f9a8: d009 beq.n 800f9be 800f9aa: 687b ldr r3, [r7, #4] 800f9ac: 681b ldr r3, [r3, #0] 800f9ae: 4a3a ldr r2, [pc, #232] @ (800fa98 ) 800f9b0: 4293 cmp r3, r2 800f9b2: d004 beq.n 800f9be 800f9b4: 687b ldr r3, [r7, #4] 800f9b6: 681b ldr r3, [r3, #0] 800f9b8: 4a38 ldr r2, [pc, #224] @ (800fa9c ) 800f9ba: 4293 cmp r3, r2 800f9bc: d101 bne.n 800f9c2 800f9be: 2301 movs r3, #1 800f9c0: e000 b.n 800f9c4 800f9c2: 2300 movs r3, #0 800f9c4: 2b00 cmp r3, #0 800f9c6: d017 beq.n 800f9f8 { /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); 800f9c8: 687b ldr r3, [r7, #4] 800f9ca: 681b ldr r3, [r3, #0] 800f9cc: 6a1a ldr r2, [r3, #32] 800f9ce: f241 1311 movw r3, #4369 @ 0x1111 800f9d2: 4013 ands r3, r2 800f9d4: 2b00 cmp r3, #0 800f9d6: d10f bne.n 800f9f8 800f9d8: 687b ldr r3, [r7, #4] 800f9da: 681b ldr r3, [r3, #0] 800f9dc: 6a1a ldr r2, [r3, #32] 800f9de: f240 4344 movw r3, #1092 @ 0x444 800f9e2: 4013 ands r3, r2 800f9e4: 2b00 cmp r3, #0 800f9e6: d107 bne.n 800f9f8 800f9e8: 687b ldr r3, [r7, #4] 800f9ea: 681b ldr r3, [r3, #0] 800f9ec: 6c5a ldr r2, [r3, #68] @ 0x44 800f9ee: 687b ldr r3, [r7, #4] 800f9f0: 681b ldr r3, [r3, #0] 800f9f2: f422 4200 bic.w r2, r2, #32768 @ 0x8000 800f9f6: 645a str r2, [r3, #68] @ 0x44 } /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800f9f8: 687b ldr r3, [r7, #4] 800f9fa: 681b ldr r3, [r3, #0] 800f9fc: 6a1a ldr r2, [r3, #32] 800f9fe: f241 1311 movw r3, #4369 @ 0x1111 800fa02: 4013 ands r3, r2 800fa04: 2b00 cmp r3, #0 800fa06: d10f bne.n 800fa28 800fa08: 687b ldr r3, [r7, #4] 800fa0a: 681b ldr r3, [r3, #0] 800fa0c: 6a1a ldr r2, [r3, #32] 800fa0e: f240 4344 movw r3, #1092 @ 0x444 800fa12: 4013 ands r3, r2 800fa14: 2b00 cmp r3, #0 800fa16: d107 bne.n 800fa28 800fa18: 687b ldr r3, [r7, #4] 800fa1a: 681b ldr r3, [r3, #0] 800fa1c: 681a ldr r2, [r3, #0] 800fa1e: 687b ldr r3, [r7, #4] 800fa20: 681b ldr r3, [r3, #0] 800fa22: f022 0201 bic.w r2, r2, #1 800fa26: 601a str r2, [r3, #0] /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); 800fa28: 683b ldr r3, [r7, #0] 800fa2a: 2b00 cmp r3, #0 800fa2c: d104 bne.n 800fa38 800fa2e: 687b ldr r3, [r7, #4] 800fa30: 2201 movs r2, #1 800fa32: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fa36: e023 b.n 800fa80 800fa38: 683b ldr r3, [r7, #0] 800fa3a: 2b04 cmp r3, #4 800fa3c: d104 bne.n 800fa48 800fa3e: 687b ldr r3, [r7, #4] 800fa40: 2201 movs r2, #1 800fa42: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fa46: e01b b.n 800fa80 800fa48: 683b ldr r3, [r7, #0] 800fa4a: 2b08 cmp r3, #8 800fa4c: d104 bne.n 800fa58 800fa4e: 687b ldr r3, [r7, #4] 800fa50: 2201 movs r2, #1 800fa52: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fa56: e013 b.n 800fa80 800fa58: 683b ldr r3, [r7, #0] 800fa5a: 2b0c cmp r3, #12 800fa5c: d104 bne.n 800fa68 800fa5e: 687b ldr r3, [r7, #4] 800fa60: 2201 movs r2, #1 800fa62: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fa66: e00b b.n 800fa80 800fa68: 683b ldr r3, [r7, #0] 800fa6a: 2b10 cmp r3, #16 800fa6c: d104 bne.n 800fa78 800fa6e: 687b ldr r3, [r7, #4] 800fa70: 2201 movs r2, #1 800fa72: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fa76: e003 b.n 800fa80 800fa78: 687b ldr r3, [r7, #4] 800fa7a: 2201 movs r2, #1 800fa7c: f883 2043 strb.w r2, [r3, #67] @ 0x43 /* Return function status */ return HAL_OK; 800fa80: 2300 movs r3, #0 } 800fa82: 4618 mov r0, r3 800fa84: 3708 adds r7, #8 800fa86: 46bd mov sp, r7 800fa88: bd80 pop {r7, pc} 800fa8a: bf00 nop 800fa8c: 40010000 .word 0x40010000 800fa90: 40010400 .word 0x40010400 800fa94: 40014000 .word 0x40014000 800fa98: 40014400 .word 0x40014400 800fa9c: 40014800 .word 0x40014800 0800faa0 : * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() * @param htim TIM Input Capture handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) { 800faa0: b580 push {r7, lr} 800faa2: b082 sub sp, #8 800faa4: af00 add r7, sp, #0 800faa6: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800faa8: 687b ldr r3, [r7, #4] 800faaa: 2b00 cmp r3, #0 800faac: d101 bne.n 800fab2 { return HAL_ERROR; 800faae: 2301 movs r3, #1 800fab0: e049 b.n 800fb46 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800fab2: 687b ldr r3, [r7, #4] 800fab4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800fab8: b2db uxtb r3, r3 800faba: 2b00 cmp r3, #0 800fabc: d106 bne.n 800facc { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 800fabe: 687b ldr r3, [r7, #4] 800fac0: 2200 movs r2, #0 800fac2: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->IC_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); 800fac6: 6878 ldr r0, [r7, #4] 800fac8: f000 f841 bl 800fb4e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 800facc: 687b ldr r3, [r7, #4] 800face: 2202 movs r2, #2 800fad0: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800fad4: 687b ldr r3, [r7, #4] 800fad6: 681a ldr r2, [r3, #0] 800fad8: 687b ldr r3, [r7, #4] 800fada: 3304 adds r3, #4 800fadc: 4619 mov r1, r3 800fade: 4610 mov r0, r2 800fae0: f000 fddc bl 801069c /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800fae4: 687b ldr r3, [r7, #4] 800fae6: 2201 movs r2, #1 800fae8: f883 2048 strb.w r2, [r3, #72] @ 0x48 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800faec: 687b ldr r3, [r7, #4] 800faee: 2201 movs r2, #1 800faf0: f883 203e strb.w r2, [r3, #62] @ 0x3e 800faf4: 687b ldr r3, [r7, #4] 800faf6: 2201 movs r2, #1 800faf8: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fafc: 687b ldr r3, [r7, #4] 800fafe: 2201 movs r2, #1 800fb00: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fb04: 687b ldr r3, [r7, #4] 800fb06: 2201 movs r2, #1 800fb08: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fb0c: 687b ldr r3, [r7, #4] 800fb0e: 2201 movs r2, #1 800fb10: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fb14: 687b ldr r3, [r7, #4] 800fb16: 2201 movs r2, #1 800fb18: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800fb1c: 687b ldr r3, [r7, #4] 800fb1e: 2201 movs r2, #1 800fb20: f883 2044 strb.w r2, [r3, #68] @ 0x44 800fb24: 687b ldr r3, [r7, #4] 800fb26: 2201 movs r2, #1 800fb28: f883 2045 strb.w r2, [r3, #69] @ 0x45 800fb2c: 687b ldr r3, [r7, #4] 800fb2e: 2201 movs r2, #1 800fb30: f883 2046 strb.w r2, [r3, #70] @ 0x46 800fb34: 687b ldr r3, [r7, #4] 800fb36: 2201 movs r2, #1 800fb38: f883 2047 strb.w r2, [r3, #71] @ 0x47 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800fb3c: 687b ldr r3, [r7, #4] 800fb3e: 2201 movs r2, #1 800fb40: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800fb44: 2300 movs r3, #0 } 800fb46: 4618 mov r0, r3 800fb48: 3708 adds r7, #8 800fb4a: 46bd mov sp, r7 800fb4c: bd80 pop {r7, pc} 0800fb4e : * @brief Initializes the TIM Input Capture MSP. * @param htim TIM Input Capture handle * @retval None */ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) { 800fb4e: b480 push {r7} 800fb50: b083 sub sp, #12 800fb52: af00 add r7, sp, #0 800fb54: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_MspInit could be implemented in the user file */ } 800fb56: bf00 nop 800fb58: 370c adds r7, #12 800fb5a: 46bd mov sp, r7 800fb5c: f85d 7b04 ldr.w r7, [sp], #4 800fb60: 4770 bx lr ... 0800fb64 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { 800fb64: b580 push {r7, lr} 800fb66: b084 sub sp, #16 800fb68: af00 add r7, sp, #0 800fb6a: 6078 str r0, [r7, #4] 800fb6c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800fb6e: 2300 movs r3, #0 800fb70: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 800fb72: 683b ldr r3, [r7, #0] 800fb74: 2b00 cmp r3, #0 800fb76: d104 bne.n 800fb82 800fb78: 687b ldr r3, [r7, #4] 800fb7a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 800fb7e: b2db uxtb r3, r3 800fb80: e023 b.n 800fbca 800fb82: 683b ldr r3, [r7, #0] 800fb84: 2b04 cmp r3, #4 800fb86: d104 bne.n 800fb92 800fb88: 687b ldr r3, [r7, #4] 800fb8a: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 800fb8e: b2db uxtb r3, r3 800fb90: e01b b.n 800fbca 800fb92: 683b ldr r3, [r7, #0] 800fb94: 2b08 cmp r3, #8 800fb96: d104 bne.n 800fba2 800fb98: 687b ldr r3, [r7, #4] 800fb9a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 800fb9e: b2db uxtb r3, r3 800fba0: e013 b.n 800fbca 800fba2: 683b ldr r3, [r7, #0] 800fba4: 2b0c cmp r3, #12 800fba6: d104 bne.n 800fbb2 800fba8: 687b ldr r3, [r7, #4] 800fbaa: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 800fbae: b2db uxtb r3, r3 800fbb0: e00b b.n 800fbca 800fbb2: 683b ldr r3, [r7, #0] 800fbb4: 2b10 cmp r3, #16 800fbb6: d104 bne.n 800fbc2 800fbb8: 687b ldr r3, [r7, #4] 800fbba: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 800fbbe: b2db uxtb r3, r3 800fbc0: e003 b.n 800fbca 800fbc2: 687b ldr r3, [r7, #4] 800fbc4: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 800fbc8: b2db uxtb r3, r3 800fbca: 73bb strb r3, [r7, #14] HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); 800fbcc: 683b ldr r3, [r7, #0] 800fbce: 2b00 cmp r3, #0 800fbd0: d104 bne.n 800fbdc 800fbd2: 687b ldr r3, [r7, #4] 800fbd4: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 800fbd8: b2db uxtb r3, r3 800fbda: e013 b.n 800fc04 800fbdc: 683b ldr r3, [r7, #0] 800fbde: 2b04 cmp r3, #4 800fbe0: d104 bne.n 800fbec 800fbe2: 687b ldr r3, [r7, #4] 800fbe4: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800fbe8: b2db uxtb r3, r3 800fbea: e00b b.n 800fc04 800fbec: 683b ldr r3, [r7, #0] 800fbee: 2b08 cmp r3, #8 800fbf0: d104 bne.n 800fbfc 800fbf2: 687b ldr r3, [r7, #4] 800fbf4: f893 3046 ldrb.w r3, [r3, #70] @ 0x46 800fbf8: b2db uxtb r3, r3 800fbfa: e003 b.n 800fc04 800fbfc: 687b ldr r3, [r7, #4] 800fbfe: f893 3047 ldrb.w r3, [r3, #71] @ 0x47 800fc02: b2db uxtb r3, r3 800fc04: 737b strb r3, [r7, #13] /* Check the parameters */ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) 800fc06: 7bbb ldrb r3, [r7, #14] 800fc08: 2b01 cmp r3, #1 800fc0a: d102 bne.n 800fc12 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) 800fc0c: 7b7b ldrb r3, [r7, #13] 800fc0e: 2b01 cmp r3, #1 800fc10: d001 beq.n 800fc16 { return HAL_ERROR; 800fc12: 2301 movs r3, #1 800fc14: e0e2 b.n 800fddc } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800fc16: 683b ldr r3, [r7, #0] 800fc18: 2b00 cmp r3, #0 800fc1a: d104 bne.n 800fc26 800fc1c: 687b ldr r3, [r7, #4] 800fc1e: 2202 movs r2, #2 800fc20: f883 203e strb.w r2, [r3, #62] @ 0x3e 800fc24: e023 b.n 800fc6e 800fc26: 683b ldr r3, [r7, #0] 800fc28: 2b04 cmp r3, #4 800fc2a: d104 bne.n 800fc36 800fc2c: 687b ldr r3, [r7, #4] 800fc2e: 2202 movs r2, #2 800fc30: f883 203f strb.w r2, [r3, #63] @ 0x3f 800fc34: e01b b.n 800fc6e 800fc36: 683b ldr r3, [r7, #0] 800fc38: 2b08 cmp r3, #8 800fc3a: d104 bne.n 800fc46 800fc3c: 687b ldr r3, [r7, #4] 800fc3e: 2202 movs r2, #2 800fc40: f883 2040 strb.w r2, [r3, #64] @ 0x40 800fc44: e013 b.n 800fc6e 800fc46: 683b ldr r3, [r7, #0] 800fc48: 2b0c cmp r3, #12 800fc4a: d104 bne.n 800fc56 800fc4c: 687b ldr r3, [r7, #4] 800fc4e: 2202 movs r2, #2 800fc50: f883 2041 strb.w r2, [r3, #65] @ 0x41 800fc54: e00b b.n 800fc6e 800fc56: 683b ldr r3, [r7, #0] 800fc58: 2b10 cmp r3, #16 800fc5a: d104 bne.n 800fc66 800fc5c: 687b ldr r3, [r7, #4] 800fc5e: 2202 movs r2, #2 800fc60: f883 2042 strb.w r2, [r3, #66] @ 0x42 800fc64: e003 b.n 800fc6e 800fc66: 687b ldr r3, [r7, #4] 800fc68: 2202 movs r2, #2 800fc6a: f883 2043 strb.w r2, [r3, #67] @ 0x43 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 800fc6e: 683b ldr r3, [r7, #0] 800fc70: 2b00 cmp r3, #0 800fc72: d104 bne.n 800fc7e 800fc74: 687b ldr r3, [r7, #4] 800fc76: 2202 movs r2, #2 800fc78: f883 2044 strb.w r2, [r3, #68] @ 0x44 800fc7c: e013 b.n 800fca6 800fc7e: 683b ldr r3, [r7, #0] 800fc80: 2b04 cmp r3, #4 800fc82: d104 bne.n 800fc8e 800fc84: 687b ldr r3, [r7, #4] 800fc86: 2202 movs r2, #2 800fc88: f883 2045 strb.w r2, [r3, #69] @ 0x45 800fc8c: e00b b.n 800fca6 800fc8e: 683b ldr r3, [r7, #0] 800fc90: 2b08 cmp r3, #8 800fc92: d104 bne.n 800fc9e 800fc94: 687b ldr r3, [r7, #4] 800fc96: 2202 movs r2, #2 800fc98: f883 2046 strb.w r2, [r3, #70] @ 0x46 800fc9c: e003 b.n 800fca6 800fc9e: 687b ldr r3, [r7, #4] 800fca0: 2202 movs r2, #2 800fca2: f883 2047 strb.w r2, [r3, #71] @ 0x47 switch (Channel) 800fca6: 683b ldr r3, [r7, #0] 800fca8: 2b0c cmp r3, #12 800fcaa: d841 bhi.n 800fd30 800fcac: a201 add r2, pc, #4 @ (adr r2, 800fcb4 ) 800fcae: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800fcb2: bf00 nop 800fcb4: 0800fce9 .word 0x0800fce9 800fcb8: 0800fd31 .word 0x0800fd31 800fcbc: 0800fd31 .word 0x0800fd31 800fcc0: 0800fd31 .word 0x0800fd31 800fcc4: 0800fcfb .word 0x0800fcfb 800fcc8: 0800fd31 .word 0x0800fd31 800fccc: 0800fd31 .word 0x0800fd31 800fcd0: 0800fd31 .word 0x0800fd31 800fcd4: 0800fd0d .word 0x0800fd0d 800fcd8: 0800fd31 .word 0x0800fd31 800fcdc: 0800fd31 .word 0x0800fd31 800fce0: 0800fd31 .word 0x0800fd31 800fce4: 0800fd1f .word 0x0800fd1f { case TIM_CHANNEL_1: { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 800fce8: 687b ldr r3, [r7, #4] 800fcea: 681b ldr r3, [r3, #0] 800fcec: 68da ldr r2, [r3, #12] 800fcee: 687b ldr r3, [r7, #4] 800fcf0: 681b ldr r3, [r3, #0] 800fcf2: f042 0202 orr.w r2, r2, #2 800fcf6: 60da str r2, [r3, #12] break; 800fcf8: e01d b.n 800fd36 } case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 800fcfa: 687b ldr r3, [r7, #4] 800fcfc: 681b ldr r3, [r3, #0] 800fcfe: 68da ldr r2, [r3, #12] 800fd00: 687b ldr r3, [r7, #4] 800fd02: 681b ldr r3, [r3, #0] 800fd04: f042 0204 orr.w r2, r2, #4 800fd08: 60da str r2, [r3, #12] break; 800fd0a: e014 b.n 800fd36 } case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 800fd0c: 687b ldr r3, [r7, #4] 800fd0e: 681b ldr r3, [r3, #0] 800fd10: 68da ldr r2, [r3, #12] 800fd12: 687b ldr r3, [r7, #4] 800fd14: 681b ldr r3, [r3, #0] 800fd16: f042 0208 orr.w r2, r2, #8 800fd1a: 60da str r2, [r3, #12] break; 800fd1c: e00b b.n 800fd36 } case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 800fd1e: 687b ldr r3, [r7, #4] 800fd20: 681b ldr r3, [r3, #0] 800fd22: 68da ldr r2, [r3, #12] 800fd24: 687b ldr r3, [r7, #4] 800fd26: 681b ldr r3, [r3, #0] 800fd28: f042 0210 orr.w r2, r2, #16 800fd2c: 60da str r2, [r3, #12] break; 800fd2e: e002 b.n 800fd36 } default: status = HAL_ERROR; 800fd30: 2301 movs r3, #1 800fd32: 73fb strb r3, [r7, #15] break; 800fd34: bf00 nop } if (status == HAL_OK) 800fd36: 7bfb ldrb r3, [r7, #15] 800fd38: 2b00 cmp r3, #0 800fd3a: d14e bne.n 800fdda { /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 800fd3c: 687b ldr r3, [r7, #4] 800fd3e: 681b ldr r3, [r3, #0] 800fd40: 2201 movs r2, #1 800fd42: 6839 ldr r1, [r7, #0] 800fd44: 4618 mov r0, r3 800fd46: f001 f9ed bl 8011124 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 800fd4a: 687b ldr r3, [r7, #4] 800fd4c: 681b ldr r3, [r3, #0] 800fd4e: 4a25 ldr r2, [pc, #148] @ (800fde4 ) 800fd50: 4293 cmp r3, r2 800fd52: d022 beq.n 800fd9a 800fd54: 687b ldr r3, [r7, #4] 800fd56: 681b ldr r3, [r3, #0] 800fd58: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800fd5c: d01d beq.n 800fd9a 800fd5e: 687b ldr r3, [r7, #4] 800fd60: 681b ldr r3, [r3, #0] 800fd62: 4a21 ldr r2, [pc, #132] @ (800fde8 ) 800fd64: 4293 cmp r3, r2 800fd66: d018 beq.n 800fd9a 800fd68: 687b ldr r3, [r7, #4] 800fd6a: 681b ldr r3, [r3, #0] 800fd6c: 4a1f ldr r2, [pc, #124] @ (800fdec ) 800fd6e: 4293 cmp r3, r2 800fd70: d013 beq.n 800fd9a 800fd72: 687b ldr r3, [r7, #4] 800fd74: 681b ldr r3, [r3, #0] 800fd76: 4a1e ldr r2, [pc, #120] @ (800fdf0 ) 800fd78: 4293 cmp r3, r2 800fd7a: d00e beq.n 800fd9a 800fd7c: 687b ldr r3, [r7, #4] 800fd7e: 681b ldr r3, [r3, #0] 800fd80: 4a1c ldr r2, [pc, #112] @ (800fdf4 ) 800fd82: 4293 cmp r3, r2 800fd84: d009 beq.n 800fd9a 800fd86: 687b ldr r3, [r7, #4] 800fd88: 681b ldr r3, [r3, #0] 800fd8a: 4a1b ldr r2, [pc, #108] @ (800fdf8 ) 800fd8c: 4293 cmp r3, r2 800fd8e: d004 beq.n 800fd9a 800fd90: 687b ldr r3, [r7, #4] 800fd92: 681b ldr r3, [r3, #0] 800fd94: 4a19 ldr r2, [pc, #100] @ (800fdfc ) 800fd96: 4293 cmp r3, r2 800fd98: d115 bne.n 800fdc6 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 800fd9a: 687b ldr r3, [r7, #4] 800fd9c: 681b ldr r3, [r3, #0] 800fd9e: 689a ldr r2, [r3, #8] 800fda0: 4b17 ldr r3, [pc, #92] @ (800fe00 ) 800fda2: 4013 ands r3, r2 800fda4: 60bb str r3, [r7, #8] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fda6: 68bb ldr r3, [r7, #8] 800fda8: 2b06 cmp r3, #6 800fdaa: d015 beq.n 800fdd8 800fdac: 68bb ldr r3, [r7, #8] 800fdae: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 800fdb2: d011 beq.n 800fdd8 { __HAL_TIM_ENABLE(htim); 800fdb4: 687b ldr r3, [r7, #4] 800fdb6: 681b ldr r3, [r3, #0] 800fdb8: 681a ldr r2, [r3, #0] 800fdba: 687b ldr r3, [r7, #4] 800fdbc: 681b ldr r3, [r3, #0] 800fdbe: f042 0201 orr.w r2, r2, #1 800fdc2: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fdc4: e008 b.n 800fdd8 } } else { __HAL_TIM_ENABLE(htim); 800fdc6: 687b ldr r3, [r7, #4] 800fdc8: 681b ldr r3, [r3, #0] 800fdca: 681a ldr r2, [r3, #0] 800fdcc: 687b ldr r3, [r7, #4] 800fdce: 681b ldr r3, [r3, #0] 800fdd0: f042 0201 orr.w r2, r2, #1 800fdd4: 601a str r2, [r3, #0] 800fdd6: e000 b.n 800fdda if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800fdd8: bf00 nop } } /* Return function status */ return status; 800fdda: 7bfb ldrb r3, [r7, #15] } 800fddc: 4618 mov r0, r3 800fdde: 3710 adds r7, #16 800fde0: 46bd mov sp, r7 800fde2: bd80 pop {r7, pc} 800fde4: 40010000 .word 0x40010000 800fde8: 40000400 .word 0x40000400 800fdec: 40000800 .word 0x40000800 800fdf0: 40000c00 .word 0x40000c00 800fdf4: 40010400 .word 0x40010400 800fdf8: 40001800 .word 0x40001800 800fdfc: 40014000 .word 0x40014000 800fe00: 00010007 .word 0x00010007 0800fe04 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 800fe04: b580 push {r7, lr} 800fe06: b084 sub sp, #16 800fe08: af00 add r7, sp, #0 800fe0a: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 800fe0c: 687b ldr r3, [r7, #4] 800fe0e: 681b ldr r3, [r3, #0] 800fe10: 68db ldr r3, [r3, #12] 800fe12: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 800fe14: 687b ldr r3, [r7, #4] 800fe16: 681b ldr r3, [r3, #0] 800fe18: 691b ldr r3, [r3, #16] 800fe1a: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 800fe1c: 68bb ldr r3, [r7, #8] 800fe1e: f003 0302 and.w r3, r3, #2 800fe22: 2b00 cmp r3, #0 800fe24: d020 beq.n 800fe68 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 800fe26: 68fb ldr r3, [r7, #12] 800fe28: f003 0302 and.w r3, r3, #2 800fe2c: 2b00 cmp r3, #0 800fe2e: d01b beq.n 800fe68 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800fe30: 687b ldr r3, [r7, #4] 800fe32: 681b ldr r3, [r3, #0] 800fe34: f06f 0202 mvn.w r2, #2 800fe38: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 800fe3a: 687b ldr r3, [r7, #4] 800fe3c: 2201 movs r2, #1 800fe3e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800fe40: 687b ldr r3, [r7, #4] 800fe42: 681b ldr r3, [r3, #0] 800fe44: 699b ldr r3, [r3, #24] 800fe46: f003 0303 and.w r3, r3, #3 800fe4a: 2b00 cmp r3, #0 800fe4c: d003 beq.n 800fe56 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fe4e: 6878 ldr r0, [r7, #4] 800fe50: f7f1 fdac bl 80019ac 800fe54: e005 b.n 800fe62 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fe56: 6878 ldr r0, [r7, #4] 800fe58: f000 fbc8 bl 80105ec HAL_TIM_PWM_PulseFinishedCallback(htim); 800fe5c: 6878 ldr r0, [r7, #4] 800fe5e: f000 fbcf bl 8010600 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fe62: 687b ldr r3, [r7, #4] 800fe64: 2200 movs r2, #0 800fe66: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 800fe68: 68bb ldr r3, [r7, #8] 800fe6a: f003 0304 and.w r3, r3, #4 800fe6e: 2b00 cmp r3, #0 800fe70: d020 beq.n 800feb4 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 800fe72: 68fb ldr r3, [r7, #12] 800fe74: f003 0304 and.w r3, r3, #4 800fe78: 2b00 cmp r3, #0 800fe7a: d01b beq.n 800feb4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 800fe7c: 687b ldr r3, [r7, #4] 800fe7e: 681b ldr r3, [r3, #0] 800fe80: f06f 0204 mvn.w r2, #4 800fe84: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800fe86: 687b ldr r3, [r7, #4] 800fe88: 2202 movs r2, #2 800fe8a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 800fe8c: 687b ldr r3, [r7, #4] 800fe8e: 681b ldr r3, [r3, #0] 800fe90: 699b ldr r3, [r3, #24] 800fe92: f403 7340 and.w r3, r3, #768 @ 0x300 800fe96: 2b00 cmp r3, #0 800fe98: d003 beq.n 800fea2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fe9a: 6878 ldr r0, [r7, #4] 800fe9c: f7f1 fd86 bl 80019ac 800fea0: e005 b.n 800feae { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800fea2: 6878 ldr r0, [r7, #4] 800fea4: f000 fba2 bl 80105ec HAL_TIM_PWM_PulseFinishedCallback(htim); 800fea8: 6878 ldr r0, [r7, #4] 800feaa: f000 fba9 bl 8010600 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800feae: 687b ldr r3, [r7, #4] 800feb0: 2200 movs r2, #0 800feb2: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 800feb4: 68bb ldr r3, [r7, #8] 800feb6: f003 0308 and.w r3, r3, #8 800feba: 2b00 cmp r3, #0 800febc: d020 beq.n 800ff00 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 800febe: 68fb ldr r3, [r7, #12] 800fec0: f003 0308 and.w r3, r3, #8 800fec4: 2b00 cmp r3, #0 800fec6: d01b beq.n 800ff00 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800fec8: 687b ldr r3, [r7, #4] 800feca: 681b ldr r3, [r3, #0] 800fecc: f06f 0208 mvn.w r2, #8 800fed0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800fed2: 687b ldr r3, [r7, #4] 800fed4: 2204 movs r2, #4 800fed6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800fed8: 687b ldr r3, [r7, #4] 800feda: 681b ldr r3, [r3, #0] 800fedc: 69db ldr r3, [r3, #28] 800fede: f003 0303 and.w r3, r3, #3 800fee2: 2b00 cmp r3, #0 800fee4: d003 beq.n 800feee { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800fee6: 6878 ldr r0, [r7, #4] 800fee8: f7f1 fd60 bl 80019ac 800feec: e005 b.n 800fefa { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800feee: 6878 ldr r0, [r7, #4] 800fef0: f000 fb7c bl 80105ec HAL_TIM_PWM_PulseFinishedCallback(htim); 800fef4: 6878 ldr r0, [r7, #4] 800fef6: f000 fb83 bl 8010600 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800fefa: 687b ldr r3, [r7, #4] 800fefc: 2200 movs r2, #0 800fefe: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800ff00: 68bb ldr r3, [r7, #8] 800ff02: f003 0310 and.w r3, r3, #16 800ff06: 2b00 cmp r3, #0 800ff08: d020 beq.n 800ff4c { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800ff0a: 68fb ldr r3, [r7, #12] 800ff0c: f003 0310 and.w r3, r3, #16 800ff10: 2b00 cmp r3, #0 800ff12: d01b beq.n 800ff4c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 800ff14: 687b ldr r3, [r7, #4] 800ff16: 681b ldr r3, [r3, #0] 800ff18: f06f 0210 mvn.w r2, #16 800ff1c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800ff1e: 687b ldr r3, [r7, #4] 800ff20: 2208 movs r2, #8 800ff22: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 800ff24: 687b ldr r3, [r7, #4] 800ff26: 681b ldr r3, [r3, #0] 800ff28: 69db ldr r3, [r3, #28] 800ff2a: f403 7340 and.w r3, r3, #768 @ 0x300 800ff2e: 2b00 cmp r3, #0 800ff30: d003 beq.n 800ff3a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800ff32: 6878 ldr r0, [r7, #4] 800ff34: f7f1 fd3a bl 80019ac 800ff38: e005 b.n 800ff46 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800ff3a: 6878 ldr r0, [r7, #4] 800ff3c: f000 fb56 bl 80105ec HAL_TIM_PWM_PulseFinishedCallback(htim); 800ff40: 6878 ldr r0, [r7, #4] 800ff42: f000 fb5d bl 8010600 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800ff46: 687b ldr r3, [r7, #4] 800ff48: 2200 movs r2, #0 800ff4a: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 800ff4c: 68bb ldr r3, [r7, #8] 800ff4e: f003 0301 and.w r3, r3, #1 800ff52: 2b00 cmp r3, #0 800ff54: d00c beq.n 800ff70 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 800ff56: 68fb ldr r3, [r7, #12] 800ff58: f003 0301 and.w r3, r3, #1 800ff5c: 2b00 cmp r3, #0 800ff5e: d007 beq.n 800ff70 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800ff60: 687b ldr r3, [r7, #4] 800ff62: 681b ldr r3, [r3, #0] 800ff64: f06f 0201 mvn.w r2, #1 800ff68: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 800ff6a: 6878 ldr r0, [r7, #4] 800ff6c: f7f1 ff7a bl 8001e64 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800ff70: 68bb ldr r3, [r7, #8] 800ff72: f003 0380 and.w r3, r3, #128 @ 0x80 800ff76: 2b00 cmp r3, #0 800ff78: d104 bne.n 800ff84 ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 800ff7a: 68bb ldr r3, [r7, #8] 800ff7c: f403 5300 and.w r3, r3, #8192 @ 0x2000 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 800ff80: 2b00 cmp r3, #0 800ff82: d00c beq.n 800ff9e { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800ff84: 68fb ldr r3, [r7, #12] 800ff86: f003 0380 and.w r3, r3, #128 @ 0x80 800ff8a: 2b00 cmp r3, #0 800ff8c: d007 beq.n 800ff9e { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 800ff8e: 687b ldr r3, [r7, #4] 800ff90: 681b ldr r3, [r3, #0] 800ff92: f46f 5202 mvn.w r2, #8320 @ 0x2080 800ff96: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 800ff98: 6878 ldr r0, [r7, #4] 800ff9a: f001 f9ff bl 801139c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 800ff9e: 68bb ldr r3, [r7, #8] 800ffa0: f403 7380 and.w r3, r3, #256 @ 0x100 800ffa4: 2b00 cmp r3, #0 800ffa6: d00c beq.n 800ffc2 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 800ffa8: 68fb ldr r3, [r7, #12] 800ffaa: f003 0380 and.w r3, r3, #128 @ 0x80 800ffae: 2b00 cmp r3, #0 800ffb0: d007 beq.n 800ffc2 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 800ffb2: 687b ldr r3, [r7, #4] 800ffb4: 681b ldr r3, [r3, #0] 800ffb6: f46f 7280 mvn.w r2, #256 @ 0x100 800ffba: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 800ffbc: 6878 ldr r0, [r7, #4] 800ffbe: f001 f9f7 bl 80113b0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 800ffc2: 68bb ldr r3, [r7, #8] 800ffc4: f003 0340 and.w r3, r3, #64 @ 0x40 800ffc8: 2b00 cmp r3, #0 800ffca: d00c beq.n 800ffe6 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 800ffcc: 68fb ldr r3, [r7, #12] 800ffce: f003 0340 and.w r3, r3, #64 @ 0x40 800ffd2: 2b00 cmp r3, #0 800ffd4: d007 beq.n 800ffe6 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800ffd6: 687b ldr r3, [r7, #4] 800ffd8: 681b ldr r3, [r3, #0] 800ffda: f06f 0240 mvn.w r2, #64 @ 0x40 800ffde: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 800ffe0: 6878 ldr r0, [r7, #4] 800ffe2: f000 fb17 bl 8010614 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800ffe6: 68bb ldr r3, [r7, #8] 800ffe8: f003 0320 and.w r3, r3, #32 800ffec: 2b00 cmp r3, #0 800ffee: d00c beq.n 801000a { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 800fff0: 68fb ldr r3, [r7, #12] 800fff2: f003 0320 and.w r3, r3, #32 800fff6: 2b00 cmp r3, #0 800fff8: d007 beq.n 801000a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 800fffa: 687b ldr r3, [r7, #4] 800fffc: 681b ldr r3, [r3, #0] 800fffe: f06f 0220 mvn.w r2, #32 8010002: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8010004: 6878 ldr r0, [r7, #4] 8010006: f001 f9bf bl 8011388 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 801000a: bf00 nop 801000c: 3710 adds r7, #16 801000e: 46bd mov sp, r7 8010010: bd80 pop {r7, pc} 08010012 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { 8010012: b580 push {r7, lr} 8010014: b086 sub sp, #24 8010016: af00 add r7, sp, #0 8010018: 60f8 str r0, [r7, #12] 801001a: 60b9 str r1, [r7, #8] 801001c: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 801001e: 2300 movs r3, #0 8010020: 75fb strb r3, [r7, #23] assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); /* Process Locked */ __HAL_LOCK(htim); 8010022: 68fb ldr r3, [r7, #12] 8010024: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010028: 2b01 cmp r3, #1 801002a: d101 bne.n 8010030 801002c: 2302 movs r3, #2 801002e: e088 b.n 8010142 8010030: 68fb ldr r3, [r7, #12] 8010032: 2201 movs r2, #1 8010034: f883 203c strb.w r2, [r3, #60] @ 0x3c if (Channel == TIM_CHANNEL_1) 8010038: 687b ldr r3, [r7, #4] 801003a: 2b00 cmp r3, #0 801003c: d11b bne.n 8010076 { /* TI1 Configuration */ TIM_TI1_SetConfig(htim->Instance, 801003e: 68fb ldr r3, [r7, #12] 8010040: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 8010042: 68bb ldr r3, [r7, #8] 8010044: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 8010046: 68bb ldr r3, [r7, #8] 8010048: 685a ldr r2, [r3, #4] sConfig->ICFilter); 801004a: 68bb ldr r3, [r7, #8] 801004c: 68db ldr r3, [r3, #12] TIM_TI1_SetConfig(htim->Instance, 801004e: f000 fea1 bl 8010d94 /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 8010052: 68fb ldr r3, [r7, #12] 8010054: 681b ldr r3, [r3, #0] 8010056: 699a ldr r2, [r3, #24] 8010058: 68fb ldr r3, [r7, #12] 801005a: 681b ldr r3, [r3, #0] 801005c: f022 020c bic.w r2, r2, #12 8010060: 619a str r2, [r3, #24] /* Set the IC1PSC value */ htim->Instance->CCMR1 |= sConfig->ICPrescaler; 8010062: 68fb ldr r3, [r7, #12] 8010064: 681b ldr r3, [r3, #0] 8010066: 6999 ldr r1, [r3, #24] 8010068: 68bb ldr r3, [r7, #8] 801006a: 689a ldr r2, [r3, #8] 801006c: 68fb ldr r3, [r7, #12] 801006e: 681b ldr r3, [r3, #0] 8010070: 430a orrs r2, r1 8010072: 619a str r2, [r3, #24] 8010074: e060 b.n 8010138 } else if (Channel == TIM_CHANNEL_2) 8010076: 687b ldr r3, [r7, #4] 8010078: 2b04 cmp r3, #4 801007a: d11c bne.n 80100b6 { /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); TIM_TI2_SetConfig(htim->Instance, 801007c: 68fb ldr r3, [r7, #12] 801007e: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 8010080: 68bb ldr r3, [r7, #8] 8010082: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 8010084: 68bb ldr r3, [r7, #8] 8010086: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010088: 68bb ldr r3, [r7, #8] 801008a: 68db ldr r3, [r3, #12] TIM_TI2_SetConfig(htim->Instance, 801008c: f000 ff25 bl 8010eda /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 8010090: 68fb ldr r3, [r7, #12] 8010092: 681b ldr r3, [r3, #0] 8010094: 699a ldr r2, [r3, #24] 8010096: 68fb ldr r3, [r7, #12] 8010098: 681b ldr r3, [r3, #0] 801009a: f422 6240 bic.w r2, r2, #3072 @ 0xc00 801009e: 619a str r2, [r3, #24] /* Set the IC2PSC value */ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); 80100a0: 68fb ldr r3, [r7, #12] 80100a2: 681b ldr r3, [r3, #0] 80100a4: 6999 ldr r1, [r3, #24] 80100a6: 68bb ldr r3, [r7, #8] 80100a8: 689b ldr r3, [r3, #8] 80100aa: 021a lsls r2, r3, #8 80100ac: 68fb ldr r3, [r7, #12] 80100ae: 681b ldr r3, [r3, #0] 80100b0: 430a orrs r2, r1 80100b2: 619a str r2, [r3, #24] 80100b4: e040 b.n 8010138 } else if (Channel == TIM_CHANNEL_3) 80100b6: 687b ldr r3, [r7, #4] 80100b8: 2b08 cmp r3, #8 80100ba: d11b bne.n 80100f4 { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); TIM_TI3_SetConfig(htim->Instance, 80100bc: 68fb ldr r3, [r7, #12] 80100be: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 80100c0: 68bb ldr r3, [r7, #8] 80100c2: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 80100c4: 68bb ldr r3, [r7, #8] 80100c6: 685a ldr r2, [r3, #4] sConfig->ICFilter); 80100c8: 68bb ldr r3, [r7, #8] 80100ca: 68db ldr r3, [r3, #12] TIM_TI3_SetConfig(htim->Instance, 80100cc: f000 ff72 bl 8010fb4 /* Reset the IC3PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 80100d0: 68fb ldr r3, [r7, #12] 80100d2: 681b ldr r3, [r3, #0] 80100d4: 69da ldr r2, [r3, #28] 80100d6: 68fb ldr r3, [r7, #12] 80100d8: 681b ldr r3, [r3, #0] 80100da: f022 020c bic.w r2, r2, #12 80100de: 61da str r2, [r3, #28] /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; 80100e0: 68fb ldr r3, [r7, #12] 80100e2: 681b ldr r3, [r3, #0] 80100e4: 69d9 ldr r1, [r3, #28] 80100e6: 68bb ldr r3, [r7, #8] 80100e8: 689a ldr r2, [r3, #8] 80100ea: 68fb ldr r3, [r7, #12] 80100ec: 681b ldr r3, [r3, #0] 80100ee: 430a orrs r2, r1 80100f0: 61da str r2, [r3, #28] 80100f2: e021 b.n 8010138 } else if (Channel == TIM_CHANNEL_4) 80100f4: 687b ldr r3, [r7, #4] 80100f6: 2b0c cmp r3, #12 80100f8: d11c bne.n 8010134 { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); TIM_TI4_SetConfig(htim->Instance, 80100fa: 68fb ldr r3, [r7, #12] 80100fc: 6818 ldr r0, [r3, #0] sConfig->ICPolarity, 80100fe: 68bb ldr r3, [r7, #8] 8010100: 6819 ldr r1, [r3, #0] sConfig->ICSelection, 8010102: 68bb ldr r3, [r7, #8] 8010104: 685a ldr r2, [r3, #4] sConfig->ICFilter); 8010106: 68bb ldr r3, [r7, #8] 8010108: 68db ldr r3, [r3, #12] TIM_TI4_SetConfig(htim->Instance, 801010a: f000 ff8f bl 801102c /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 801010e: 68fb ldr r3, [r7, #12] 8010110: 681b ldr r3, [r3, #0] 8010112: 69da ldr r2, [r3, #28] 8010114: 68fb ldr r3, [r7, #12] 8010116: 681b ldr r3, [r3, #0] 8010118: f422 6240 bic.w r2, r2, #3072 @ 0xc00 801011c: 61da str r2, [r3, #28] /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); 801011e: 68fb ldr r3, [r7, #12] 8010120: 681b ldr r3, [r3, #0] 8010122: 69d9 ldr r1, [r3, #28] 8010124: 68bb ldr r3, [r7, #8] 8010126: 689b ldr r3, [r3, #8] 8010128: 021a lsls r2, r3, #8 801012a: 68fb ldr r3, [r7, #12] 801012c: 681b ldr r3, [r3, #0] 801012e: 430a orrs r2, r1 8010130: 61da str r2, [r3, #28] 8010132: e001 b.n 8010138 } else { status = HAL_ERROR; 8010134: 2301 movs r3, #1 8010136: 75fb strb r3, [r7, #23] } __HAL_UNLOCK(htim); 8010138: 68fb ldr r3, [r7, #12] 801013a: 2200 movs r2, #0 801013c: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010140: 7dfb ldrb r3, [r7, #23] } 8010142: 4618 mov r0, r3 8010144: 3718 adds r7, #24 8010146: 46bd mov sp, r7 8010148: bd80 pop {r7, pc} ... 0801014c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 801014c: b580 push {r7, lr} 801014e: b086 sub sp, #24 8010150: af00 add r7, sp, #0 8010152: 60f8 str r0, [r7, #12] 8010154: 60b9 str r1, [r7, #8] 8010156: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8010158: 2300 movs r3, #0 801015a: 75fb strb r3, [r7, #23] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 801015c: 68fb ldr r3, [r7, #12] 801015e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010162: 2b01 cmp r3, #1 8010164: d101 bne.n 801016a 8010166: 2302 movs r3, #2 8010168: e0ff b.n 801036a 801016a: 68fb ldr r3, [r7, #12] 801016c: 2201 movs r2, #1 801016e: f883 203c strb.w r2, [r3, #60] @ 0x3c switch (Channel) 8010172: 687b ldr r3, [r7, #4] 8010174: 2b14 cmp r3, #20 8010176: f200 80f0 bhi.w 801035a 801017a: a201 add r2, pc, #4 @ (adr r2, 8010180 ) 801017c: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8010180: 080101d5 .word 0x080101d5 8010184: 0801035b .word 0x0801035b 8010188: 0801035b .word 0x0801035b 801018c: 0801035b .word 0x0801035b 8010190: 08010215 .word 0x08010215 8010194: 0801035b .word 0x0801035b 8010198: 0801035b .word 0x0801035b 801019c: 0801035b .word 0x0801035b 80101a0: 08010257 .word 0x08010257 80101a4: 0801035b .word 0x0801035b 80101a8: 0801035b .word 0x0801035b 80101ac: 0801035b .word 0x0801035b 80101b0: 08010297 .word 0x08010297 80101b4: 0801035b .word 0x0801035b 80101b8: 0801035b .word 0x0801035b 80101bc: 0801035b .word 0x0801035b 80101c0: 080102d9 .word 0x080102d9 80101c4: 0801035b .word 0x0801035b 80101c8: 0801035b .word 0x0801035b 80101cc: 0801035b .word 0x0801035b 80101d0: 08010319 .word 0x08010319 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 80101d4: 68fb ldr r3, [r7, #12] 80101d6: 681b ldr r3, [r3, #0] 80101d8: 68b9 ldr r1, [r7, #8] 80101da: 4618 mov r0, r3 80101dc: f000 fb04 bl 80107e8 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 80101e0: 68fb ldr r3, [r7, #12] 80101e2: 681b ldr r3, [r3, #0] 80101e4: 699a ldr r2, [r3, #24] 80101e6: 68fb ldr r3, [r7, #12] 80101e8: 681b ldr r3, [r3, #0] 80101ea: f042 0208 orr.w r2, r2, #8 80101ee: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 80101f0: 68fb ldr r3, [r7, #12] 80101f2: 681b ldr r3, [r3, #0] 80101f4: 699a ldr r2, [r3, #24] 80101f6: 68fb ldr r3, [r7, #12] 80101f8: 681b ldr r3, [r3, #0] 80101fa: f022 0204 bic.w r2, r2, #4 80101fe: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8010200: 68fb ldr r3, [r7, #12] 8010202: 681b ldr r3, [r3, #0] 8010204: 6999 ldr r1, [r3, #24] 8010206: 68bb ldr r3, [r7, #8] 8010208: 691a ldr r2, [r3, #16] 801020a: 68fb ldr r3, [r7, #12] 801020c: 681b ldr r3, [r3, #0] 801020e: 430a orrs r2, r1 8010210: 619a str r2, [r3, #24] break; 8010212: e0a5 b.n 8010360 { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8010214: 68fb ldr r3, [r7, #12] 8010216: 681b ldr r3, [r3, #0] 8010218: 68b9 ldr r1, [r7, #8] 801021a: 4618 mov r0, r3 801021c: f000 fb74 bl 8010908 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8010220: 68fb ldr r3, [r7, #12] 8010222: 681b ldr r3, [r3, #0] 8010224: 699a ldr r2, [r3, #24] 8010226: 68fb ldr r3, [r7, #12] 8010228: 681b ldr r3, [r3, #0] 801022a: f442 6200 orr.w r2, r2, #2048 @ 0x800 801022e: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8010230: 68fb ldr r3, [r7, #12] 8010232: 681b ldr r3, [r3, #0] 8010234: 699a ldr r2, [r3, #24] 8010236: 68fb ldr r3, [r7, #12] 8010238: 681b ldr r3, [r3, #0] 801023a: f422 6280 bic.w r2, r2, #1024 @ 0x400 801023e: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8010240: 68fb ldr r3, [r7, #12] 8010242: 681b ldr r3, [r3, #0] 8010244: 6999 ldr r1, [r3, #24] 8010246: 68bb ldr r3, [r7, #8] 8010248: 691b ldr r3, [r3, #16] 801024a: 021a lsls r2, r3, #8 801024c: 68fb ldr r3, [r7, #12] 801024e: 681b ldr r3, [r3, #0] 8010250: 430a orrs r2, r1 8010252: 619a str r2, [r3, #24] break; 8010254: e084 b.n 8010360 { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8010256: 68fb ldr r3, [r7, #12] 8010258: 681b ldr r3, [r3, #0] 801025a: 68b9 ldr r1, [r7, #8] 801025c: 4618 mov r0, r3 801025e: f000 fbdd bl 8010a1c /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8010262: 68fb ldr r3, [r7, #12] 8010264: 681b ldr r3, [r3, #0] 8010266: 69da ldr r2, [r3, #28] 8010268: 68fb ldr r3, [r7, #12] 801026a: 681b ldr r3, [r3, #0] 801026c: f042 0208 orr.w r2, r2, #8 8010270: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8010272: 68fb ldr r3, [r7, #12] 8010274: 681b ldr r3, [r3, #0] 8010276: 69da ldr r2, [r3, #28] 8010278: 68fb ldr r3, [r7, #12] 801027a: 681b ldr r3, [r3, #0] 801027c: f022 0204 bic.w r2, r2, #4 8010280: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8010282: 68fb ldr r3, [r7, #12] 8010284: 681b ldr r3, [r3, #0] 8010286: 69d9 ldr r1, [r3, #28] 8010288: 68bb ldr r3, [r7, #8] 801028a: 691a ldr r2, [r3, #16] 801028c: 68fb ldr r3, [r7, #12] 801028e: 681b ldr r3, [r3, #0] 8010290: 430a orrs r2, r1 8010292: 61da str r2, [r3, #28] break; 8010294: e064 b.n 8010360 { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8010296: 68fb ldr r3, [r7, #12] 8010298: 681b ldr r3, [r3, #0] 801029a: 68b9 ldr r1, [r7, #8] 801029c: 4618 mov r0, r3 801029e: f000 fc45 bl 8010b2c /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 80102a2: 68fb ldr r3, [r7, #12] 80102a4: 681b ldr r3, [r3, #0] 80102a6: 69da ldr r2, [r3, #28] 80102a8: 68fb ldr r3, [r7, #12] 80102aa: 681b ldr r3, [r3, #0] 80102ac: f442 6200 orr.w r2, r2, #2048 @ 0x800 80102b0: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 80102b2: 68fb ldr r3, [r7, #12] 80102b4: 681b ldr r3, [r3, #0] 80102b6: 69da ldr r2, [r3, #28] 80102b8: 68fb ldr r3, [r7, #12] 80102ba: 681b ldr r3, [r3, #0] 80102bc: f422 6280 bic.w r2, r2, #1024 @ 0x400 80102c0: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 80102c2: 68fb ldr r3, [r7, #12] 80102c4: 681b ldr r3, [r3, #0] 80102c6: 69d9 ldr r1, [r3, #28] 80102c8: 68bb ldr r3, [r7, #8] 80102ca: 691b ldr r3, [r3, #16] 80102cc: 021a lsls r2, r3, #8 80102ce: 68fb ldr r3, [r7, #12] 80102d0: 681b ldr r3, [r3, #0] 80102d2: 430a orrs r2, r1 80102d4: 61da str r2, [r3, #28] break; 80102d6: e043 b.n 8010360 { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 80102d8: 68fb ldr r3, [r7, #12] 80102da: 681b ldr r3, [r3, #0] 80102dc: 68b9 ldr r1, [r7, #8] 80102de: 4618 mov r0, r3 80102e0: f000 fc8e bl 8010c00 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 80102e4: 68fb ldr r3, [r7, #12] 80102e6: 681b ldr r3, [r3, #0] 80102e8: 6d5a ldr r2, [r3, #84] @ 0x54 80102ea: 68fb ldr r3, [r7, #12] 80102ec: 681b ldr r3, [r3, #0] 80102ee: f042 0208 orr.w r2, r2, #8 80102f2: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 80102f4: 68fb ldr r3, [r7, #12] 80102f6: 681b ldr r3, [r3, #0] 80102f8: 6d5a ldr r2, [r3, #84] @ 0x54 80102fa: 68fb ldr r3, [r7, #12] 80102fc: 681b ldr r3, [r3, #0] 80102fe: f022 0204 bic.w r2, r2, #4 8010302: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 8010304: 68fb ldr r3, [r7, #12] 8010306: 681b ldr r3, [r3, #0] 8010308: 6d59 ldr r1, [r3, #84] @ 0x54 801030a: 68bb ldr r3, [r7, #8] 801030c: 691a ldr r2, [r3, #16] 801030e: 68fb ldr r3, [r7, #12] 8010310: 681b ldr r3, [r3, #0] 8010312: 430a orrs r2, r1 8010314: 655a str r2, [r3, #84] @ 0x54 break; 8010316: e023 b.n 8010360 { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 8010318: 68fb ldr r3, [r7, #12] 801031a: 681b ldr r3, [r3, #0] 801031c: 68b9 ldr r1, [r7, #8] 801031e: 4618 mov r0, r3 8010320: f000 fcd2 bl 8010cc8 /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 8010324: 68fb ldr r3, [r7, #12] 8010326: 681b ldr r3, [r3, #0] 8010328: 6d5a ldr r2, [r3, #84] @ 0x54 801032a: 68fb ldr r3, [r7, #12] 801032c: 681b ldr r3, [r3, #0] 801032e: f442 6200 orr.w r2, r2, #2048 @ 0x800 8010332: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 8010334: 68fb ldr r3, [r7, #12] 8010336: 681b ldr r3, [r3, #0] 8010338: 6d5a ldr r2, [r3, #84] @ 0x54 801033a: 68fb ldr r3, [r7, #12] 801033c: 681b ldr r3, [r3, #0] 801033e: f422 6280 bic.w r2, r2, #1024 @ 0x400 8010342: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 8010344: 68fb ldr r3, [r7, #12] 8010346: 681b ldr r3, [r3, #0] 8010348: 6d59 ldr r1, [r3, #84] @ 0x54 801034a: 68bb ldr r3, [r7, #8] 801034c: 691b ldr r3, [r3, #16] 801034e: 021a lsls r2, r3, #8 8010350: 68fb ldr r3, [r7, #12] 8010352: 681b ldr r3, [r3, #0] 8010354: 430a orrs r2, r1 8010356: 655a str r2, [r3, #84] @ 0x54 break; 8010358: e002 b.n 8010360 } default: status = HAL_ERROR; 801035a: 2301 movs r3, #1 801035c: 75fb strb r3, [r7, #23] break; 801035e: bf00 nop } __HAL_UNLOCK(htim); 8010360: 68fb ldr r3, [r7, #12] 8010362: 2200 movs r2, #0 8010364: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010368: 7dfb ldrb r3, [r7, #23] } 801036a: 4618 mov r0, r3 801036c: 3718 adds r7, #24 801036e: 46bd mov sp, r7 8010370: bd80 pop {r7, pc} 8010372: bf00 nop 08010374 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8010374: b580 push {r7, lr} 8010376: b084 sub sp, #16 8010378: af00 add r7, sp, #0 801037a: 6078 str r0, [r7, #4] 801037c: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 801037e: 2300 movs r3, #0 8010380: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8010382: 687b ldr r3, [r7, #4] 8010384: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8010388: 2b01 cmp r3, #1 801038a: d101 bne.n 8010390 801038c: 2302 movs r3, #2 801038e: e0dc b.n 801054a 8010390: 687b ldr r3, [r7, #4] 8010392: 2201 movs r2, #1 8010394: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8010398: 687b ldr r3, [r7, #4] 801039a: 2202 movs r2, #2 801039c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 80103a0: 687b ldr r3, [r7, #4] 80103a2: 681b ldr r3, [r3, #0] 80103a4: 689b ldr r3, [r3, #8] 80103a6: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 80103a8: 68ba ldr r2, [r7, #8] 80103aa: 4b6a ldr r3, [pc, #424] @ (8010554 ) 80103ac: 4013 ands r3, r2 80103ae: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80103b0: 68bb ldr r3, [r7, #8] 80103b2: f423 437f bic.w r3, r3, #65280 @ 0xff00 80103b6: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 80103b8: 687b ldr r3, [r7, #4] 80103ba: 681b ldr r3, [r3, #0] 80103bc: 68ba ldr r2, [r7, #8] 80103be: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80103c0: 683b ldr r3, [r7, #0] 80103c2: 681b ldr r3, [r3, #0] 80103c4: 4a64 ldr r2, [pc, #400] @ (8010558 ) 80103c6: 4293 cmp r3, r2 80103c8: f000 80a9 beq.w 801051e 80103cc: 4a62 ldr r2, [pc, #392] @ (8010558 ) 80103ce: 4293 cmp r3, r2 80103d0: f200 80ae bhi.w 8010530 80103d4: 4a61 ldr r2, [pc, #388] @ (801055c ) 80103d6: 4293 cmp r3, r2 80103d8: f000 80a1 beq.w 801051e 80103dc: 4a5f ldr r2, [pc, #380] @ (801055c ) 80103de: 4293 cmp r3, r2 80103e0: f200 80a6 bhi.w 8010530 80103e4: 4a5e ldr r2, [pc, #376] @ (8010560 ) 80103e6: 4293 cmp r3, r2 80103e8: f000 8099 beq.w 801051e 80103ec: 4a5c ldr r2, [pc, #368] @ (8010560 ) 80103ee: 4293 cmp r3, r2 80103f0: f200 809e bhi.w 8010530 80103f4: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 80103f8: f000 8091 beq.w 801051e 80103fc: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010 8010400: f200 8096 bhi.w 8010530 8010404: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8010408: f000 8089 beq.w 801051e 801040c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 8010410: f200 808e bhi.w 8010530 8010414: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8010418: d03e beq.n 8010498 801041a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 801041e: f200 8087 bhi.w 8010530 8010422: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8010426: f000 8086 beq.w 8010536 801042a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 801042e: d87f bhi.n 8010530 8010430: 2b70 cmp r3, #112 @ 0x70 8010432: d01a beq.n 801046a 8010434: 2b70 cmp r3, #112 @ 0x70 8010436: d87b bhi.n 8010530 8010438: 2b60 cmp r3, #96 @ 0x60 801043a: d050 beq.n 80104de 801043c: 2b60 cmp r3, #96 @ 0x60 801043e: d877 bhi.n 8010530 8010440: 2b50 cmp r3, #80 @ 0x50 8010442: d03c beq.n 80104be 8010444: 2b50 cmp r3, #80 @ 0x50 8010446: d873 bhi.n 8010530 8010448: 2b40 cmp r3, #64 @ 0x40 801044a: d058 beq.n 80104fe 801044c: 2b40 cmp r3, #64 @ 0x40 801044e: d86f bhi.n 8010530 8010450: 2b30 cmp r3, #48 @ 0x30 8010452: d064 beq.n 801051e 8010454: 2b30 cmp r3, #48 @ 0x30 8010456: d86b bhi.n 8010530 8010458: 2b20 cmp r3, #32 801045a: d060 beq.n 801051e 801045c: 2b20 cmp r3, #32 801045e: d867 bhi.n 8010530 8010460: 2b00 cmp r3, #0 8010462: d05c beq.n 801051e 8010464: 2b10 cmp r3, #16 8010466: d05a beq.n 801051e 8010468: e062 b.n 8010530 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 801046a: 687b ldr r3, [r7, #4] 801046c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 801046e: 683b ldr r3, [r7, #0] 8010470: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8010472: 683b ldr r3, [r7, #0] 8010474: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8010476: 683b ldr r3, [r7, #0] 8010478: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 801047a: f000 fe33 bl 80110e4 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 801047e: 687b ldr r3, [r7, #4] 8010480: 681b ldr r3, [r3, #0] 8010482: 689b ldr r3, [r3, #8] 8010484: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8010486: 68bb ldr r3, [r7, #8] 8010488: f043 0377 orr.w r3, r3, #119 @ 0x77 801048c: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 801048e: 687b ldr r3, [r7, #4] 8010490: 681b ldr r3, [r3, #0] 8010492: 68ba ldr r2, [r7, #8] 8010494: 609a str r2, [r3, #8] break; 8010496: e04f b.n 8010538 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8010498: 687b ldr r3, [r7, #4] 801049a: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 801049c: 683b ldr r3, [r7, #0] 801049e: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80104a0: 683b ldr r3, [r7, #0] 80104a2: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80104a4: 683b ldr r3, [r7, #0] 80104a6: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80104a8: f000 fe1c bl 80110e4 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 80104ac: 687b ldr r3, [r7, #4] 80104ae: 681b ldr r3, [r3, #0] 80104b0: 689a ldr r2, [r3, #8] 80104b2: 687b ldr r3, [r7, #4] 80104b4: 681b ldr r3, [r3, #0] 80104b6: f442 4280 orr.w r2, r2, #16384 @ 0x4000 80104ba: 609a str r2, [r3, #8] break; 80104bc: e03c b.n 8010538 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80104be: 687b ldr r3, [r7, #4] 80104c0: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80104c2: 683b ldr r3, [r7, #0] 80104c4: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80104c6: 683b ldr r3, [r7, #0] 80104c8: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80104ca: 461a mov r2, r3 80104cc: f000 fcd6 bl 8010e7c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 80104d0: 687b ldr r3, [r7, #4] 80104d2: 681b ldr r3, [r3, #0] 80104d4: 2150 movs r1, #80 @ 0x50 80104d6: 4618 mov r0, r3 80104d8: f000 fde6 bl 80110a8 break; 80104dc: e02c b.n 8010538 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 80104de: 687b ldr r3, [r7, #4] 80104e0: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80104e2: 683b ldr r3, [r7, #0] 80104e4: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80104e6: 683b ldr r3, [r7, #0] 80104e8: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 80104ea: 461a mov r2, r3 80104ec: f000 fd32 bl 8010f54 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 80104f0: 687b ldr r3, [r7, #4] 80104f2: 681b ldr r3, [r3, #0] 80104f4: 2160 movs r1, #96 @ 0x60 80104f6: 4618 mov r0, r3 80104f8: f000 fdd6 bl 80110a8 break; 80104fc: e01c b.n 8010538 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80104fe: 687b ldr r3, [r7, #4] 8010500: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8010502: 683b ldr r3, [r7, #0] 8010504: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8010506: 683b ldr r3, [r7, #0] 8010508: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 801050a: 461a mov r2, r3 801050c: f000 fcb6 bl 8010e7c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8010510: 687b ldr r3, [r7, #4] 8010512: 681b ldr r3, [r3, #0] 8010514: 2140 movs r1, #64 @ 0x40 8010516: 4618 mov r0, r3 8010518: f000 fdc6 bl 80110a8 break; 801051c: e00c b.n 8010538 case TIM_CLOCKSOURCE_ITR8: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 801051e: 687b ldr r3, [r7, #4] 8010520: 681a ldr r2, [r3, #0] 8010522: 683b ldr r3, [r7, #0] 8010524: 681b ldr r3, [r3, #0] 8010526: 4619 mov r1, r3 8010528: 4610 mov r0, r2 801052a: f000 fdbd bl 80110a8 break; 801052e: e003 b.n 8010538 } default: status = HAL_ERROR; 8010530: 2301 movs r3, #1 8010532: 73fb strb r3, [r7, #15] break; 8010534: e000 b.n 8010538 break; 8010536: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8010538: 687b ldr r3, [r7, #4] 801053a: 2201 movs r2, #1 801053c: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8010540: 687b ldr r3, [r7, #4] 8010542: 2200 movs r2, #0 8010544: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 8010548: 7bfb ldrb r3, [r7, #15] } 801054a: 4618 mov r0, r3 801054c: 3710 adds r7, #16 801054e: 46bd mov sp, r7 8010550: bd80 pop {r7, pc} 8010552: bf00 nop 8010554: ffceff88 .word 0xffceff88 8010558: 00100040 .word 0x00100040 801055c: 00100030 .word 0x00100030 8010560: 00100020 .word 0x00100020 08010564 : * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { 8010564: b480 push {r7} 8010566: b085 sub sp, #20 8010568: af00 add r7, sp, #0 801056a: 6078 str r0, [r7, #4] 801056c: 6039 str r1, [r7, #0] uint32_t tmpreg = 0U; 801056e: 2300 movs r3, #0 8010570: 60fb str r3, [r7, #12] switch (Channel) 8010572: 683b ldr r3, [r7, #0] 8010574: 2b0c cmp r3, #12 8010576: d831 bhi.n 80105dc 8010578: a201 add r2, pc, #4 @ (adr r2, 8010580 ) 801057a: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801057e: bf00 nop 8010580: 080105b5 .word 0x080105b5 8010584: 080105dd .word 0x080105dd 8010588: 080105dd .word 0x080105dd 801058c: 080105dd .word 0x080105dd 8010590: 080105bf .word 0x080105bf 8010594: 080105dd .word 0x080105dd 8010598: 080105dd .word 0x080105dd 801059c: 080105dd .word 0x080105dd 80105a0: 080105c9 .word 0x080105c9 80105a4: 080105dd .word 0x080105dd 80105a8: 080105dd .word 0x080105dd 80105ac: 080105dd .word 0x080105dd 80105b0: 080105d3 .word 0x080105d3 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Return the capture 1 value */ tmpreg = htim->Instance->CCR1; 80105b4: 687b ldr r3, [r7, #4] 80105b6: 681b ldr r3, [r3, #0] 80105b8: 6b5b ldr r3, [r3, #52] @ 0x34 80105ba: 60fb str r3, [r7, #12] break; 80105bc: e00f b.n 80105de { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Return the capture 2 value */ tmpreg = htim->Instance->CCR2; 80105be: 687b ldr r3, [r7, #4] 80105c0: 681b ldr r3, [r3, #0] 80105c2: 6b9b ldr r3, [r3, #56] @ 0x38 80105c4: 60fb str r3, [r7, #12] break; 80105c6: e00a b.n 80105de { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Return the capture 3 value */ tmpreg = htim->Instance->CCR3; 80105c8: 687b ldr r3, [r7, #4] 80105ca: 681b ldr r3, [r3, #0] 80105cc: 6bdb ldr r3, [r3, #60] @ 0x3c 80105ce: 60fb str r3, [r7, #12] break; 80105d0: e005 b.n 80105de { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Return the capture 4 value */ tmpreg = htim->Instance->CCR4; 80105d2: 687b ldr r3, [r7, #4] 80105d4: 681b ldr r3, [r3, #0] 80105d6: 6c1b ldr r3, [r3, #64] @ 0x40 80105d8: 60fb str r3, [r7, #12] break; 80105da: e000 b.n 80105de } default: break; 80105dc: bf00 nop } return tmpreg; 80105de: 68fb ldr r3, [r7, #12] } 80105e0: 4618 mov r0, r3 80105e2: 3714 adds r7, #20 80105e4: 46bd mov sp, r7 80105e6: f85d 7b04 ldr.w r7, [sp], #4 80105ea: 4770 bx lr 080105ec : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80105ec: b480 push {r7} 80105ee: b083 sub sp, #12 80105f0: af00 add r7, sp, #0 80105f2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80105f4: bf00 nop 80105f6: 370c adds r7, #12 80105f8: 46bd mov sp, r7 80105fa: f85d 7b04 ldr.w r7, [sp], #4 80105fe: 4770 bx lr 08010600 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8010600: b480 push {r7} 8010602: b083 sub sp, #12 8010604: af00 add r7, sp, #0 8010606: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8010608: bf00 nop 801060a: 370c adds r7, #12 801060c: 46bd mov sp, r7 801060e: f85d 7b04 ldr.w r7, [sp], #4 8010612: 4770 bx lr 08010614 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8010614: b480 push {r7} 8010616: b083 sub sp, #12 8010618: af00 add r7, sp, #0 801061a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 801061c: bf00 nop 801061e: 370c adds r7, #12 8010620: 46bd mov sp, r7 8010622: f85d 7b04 ldr.w r7, [sp], #4 8010626: 4770 bx lr 08010628 : * @arg TIM_CHANNEL_5: TIM Channel 5 * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { 8010628: b480 push {r7} 801062a: b085 sub sp, #20 801062c: af00 add r7, sp, #0 801062e: 6078 str r0, [r7, #4] 8010630: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_state; /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); 8010632: 683b ldr r3, [r7, #0] 8010634: 2b00 cmp r3, #0 8010636: d104 bne.n 8010642 8010638: 687b ldr r3, [r7, #4] 801063a: f893 303e ldrb.w r3, [r3, #62] @ 0x3e 801063e: b2db uxtb r3, r3 8010640: e023 b.n 801068a 8010642: 683b ldr r3, [r7, #0] 8010644: 2b04 cmp r3, #4 8010646: d104 bne.n 8010652 8010648: 687b ldr r3, [r7, #4] 801064a: f893 303f ldrb.w r3, [r3, #63] @ 0x3f 801064e: b2db uxtb r3, r3 8010650: e01b b.n 801068a 8010652: 683b ldr r3, [r7, #0] 8010654: 2b08 cmp r3, #8 8010656: d104 bne.n 8010662 8010658: 687b ldr r3, [r7, #4] 801065a: f893 3040 ldrb.w r3, [r3, #64] @ 0x40 801065e: b2db uxtb r3, r3 8010660: e013 b.n 801068a 8010662: 683b ldr r3, [r7, #0] 8010664: 2b0c cmp r3, #12 8010666: d104 bne.n 8010672 8010668: 687b ldr r3, [r7, #4] 801066a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 801066e: b2db uxtb r3, r3 8010670: e00b b.n 801068a 8010672: 683b ldr r3, [r7, #0] 8010674: 2b10 cmp r3, #16 8010676: d104 bne.n 8010682 8010678: 687b ldr r3, [r7, #4] 801067a: f893 3042 ldrb.w r3, [r3, #66] @ 0x42 801067e: b2db uxtb r3, r3 8010680: e003 b.n 801068a 8010682: 687b ldr r3, [r7, #4] 8010684: f893 3043 ldrb.w r3, [r3, #67] @ 0x43 8010688: b2db uxtb r3, r3 801068a: 73fb strb r3, [r7, #15] return channel_state; 801068c: 7bfb ldrb r3, [r7, #15] } 801068e: 4618 mov r0, r3 8010690: 3714 adds r7, #20 8010692: 46bd mov sp, r7 8010694: f85d 7b04 ldr.w r7, [sp], #4 8010698: 4770 bx lr ... 0801069c : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 801069c: b480 push {r7} 801069e: b085 sub sp, #20 80106a0: af00 add r7, sp, #0 80106a2: 6078 str r0, [r7, #4] 80106a4: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 80106a6: 687b ldr r3, [r7, #4] 80106a8: 681b ldr r3, [r3, #0] 80106aa: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 80106ac: 687b ldr r3, [r7, #4] 80106ae: 4a46 ldr r2, [pc, #280] @ (80107c8 ) 80106b0: 4293 cmp r3, r2 80106b2: d013 beq.n 80106dc 80106b4: 687b ldr r3, [r7, #4] 80106b6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80106ba: d00f beq.n 80106dc 80106bc: 687b ldr r3, [r7, #4] 80106be: 4a43 ldr r2, [pc, #268] @ (80107cc ) 80106c0: 4293 cmp r3, r2 80106c2: d00b beq.n 80106dc 80106c4: 687b ldr r3, [r7, #4] 80106c6: 4a42 ldr r2, [pc, #264] @ (80107d0 ) 80106c8: 4293 cmp r3, r2 80106ca: d007 beq.n 80106dc 80106cc: 687b ldr r3, [r7, #4] 80106ce: 4a41 ldr r2, [pc, #260] @ (80107d4 ) 80106d0: 4293 cmp r3, r2 80106d2: d003 beq.n 80106dc 80106d4: 687b ldr r3, [r7, #4] 80106d6: 4a40 ldr r2, [pc, #256] @ (80107d8 ) 80106d8: 4293 cmp r3, r2 80106da: d108 bne.n 80106ee { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 80106dc: 68fb ldr r3, [r7, #12] 80106de: f023 0370 bic.w r3, r3, #112 @ 0x70 80106e2: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 80106e4: 683b ldr r3, [r7, #0] 80106e6: 685b ldr r3, [r3, #4] 80106e8: 68fa ldr r2, [r7, #12] 80106ea: 4313 orrs r3, r2 80106ec: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 80106ee: 687b ldr r3, [r7, #4] 80106f0: 4a35 ldr r2, [pc, #212] @ (80107c8 ) 80106f2: 4293 cmp r3, r2 80106f4: d01f beq.n 8010736 80106f6: 687b ldr r3, [r7, #4] 80106f8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80106fc: d01b beq.n 8010736 80106fe: 687b ldr r3, [r7, #4] 8010700: 4a32 ldr r2, [pc, #200] @ (80107cc ) 8010702: 4293 cmp r3, r2 8010704: d017 beq.n 8010736 8010706: 687b ldr r3, [r7, #4] 8010708: 4a31 ldr r2, [pc, #196] @ (80107d0 ) 801070a: 4293 cmp r3, r2 801070c: d013 beq.n 8010736 801070e: 687b ldr r3, [r7, #4] 8010710: 4a30 ldr r2, [pc, #192] @ (80107d4 ) 8010712: 4293 cmp r3, r2 8010714: d00f beq.n 8010736 8010716: 687b ldr r3, [r7, #4] 8010718: 4a2f ldr r2, [pc, #188] @ (80107d8 ) 801071a: 4293 cmp r3, r2 801071c: d00b beq.n 8010736 801071e: 687b ldr r3, [r7, #4] 8010720: 4a2e ldr r2, [pc, #184] @ (80107dc ) 8010722: 4293 cmp r3, r2 8010724: d007 beq.n 8010736 8010726: 687b ldr r3, [r7, #4] 8010728: 4a2d ldr r2, [pc, #180] @ (80107e0 ) 801072a: 4293 cmp r3, r2 801072c: d003 beq.n 8010736 801072e: 687b ldr r3, [r7, #4] 8010730: 4a2c ldr r2, [pc, #176] @ (80107e4 ) 8010732: 4293 cmp r3, r2 8010734: d108 bne.n 8010748 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8010736: 68fb ldr r3, [r7, #12] 8010738: f423 7340 bic.w r3, r3, #768 @ 0x300 801073c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 801073e: 683b ldr r3, [r7, #0] 8010740: 68db ldr r3, [r3, #12] 8010742: 68fa ldr r2, [r7, #12] 8010744: 4313 orrs r3, r2 8010746: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8010748: 68fb ldr r3, [r7, #12] 801074a: f023 0280 bic.w r2, r3, #128 @ 0x80 801074e: 683b ldr r3, [r7, #0] 8010750: 695b ldr r3, [r3, #20] 8010752: 4313 orrs r3, r2 8010754: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; 8010756: 687b ldr r3, [r7, #4] 8010758: 68fa ldr r2, [r7, #12] 801075a: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 801075c: 683b ldr r3, [r7, #0] 801075e: 689a ldr r2, [r3, #8] 8010760: 687b ldr r3, [r7, #4] 8010762: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8010764: 683b ldr r3, [r7, #0] 8010766: 681a ldr r2, [r3, #0] 8010768: 687b ldr r3, [r7, #4] 801076a: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 801076c: 687b ldr r3, [r7, #4] 801076e: 4a16 ldr r2, [pc, #88] @ (80107c8 ) 8010770: 4293 cmp r3, r2 8010772: d00f beq.n 8010794 8010774: 687b ldr r3, [r7, #4] 8010776: 4a18 ldr r2, [pc, #96] @ (80107d8 ) 8010778: 4293 cmp r3, r2 801077a: d00b beq.n 8010794 801077c: 687b ldr r3, [r7, #4] 801077e: 4a17 ldr r2, [pc, #92] @ (80107dc ) 8010780: 4293 cmp r3, r2 8010782: d007 beq.n 8010794 8010784: 687b ldr r3, [r7, #4] 8010786: 4a16 ldr r2, [pc, #88] @ (80107e0 ) 8010788: 4293 cmp r3, r2 801078a: d003 beq.n 8010794 801078c: 687b ldr r3, [r7, #4] 801078e: 4a15 ldr r2, [pc, #84] @ (80107e4 ) 8010790: 4293 cmp r3, r2 8010792: d103 bne.n 801079c { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8010794: 683b ldr r3, [r7, #0] 8010796: 691a ldr r2, [r3, #16] 8010798: 687b ldr r3, [r7, #4] 801079a: 631a str r2, [r3, #48] @ 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 801079c: 687b ldr r3, [r7, #4] 801079e: 2201 movs r2, #1 80107a0: 615a str r2, [r3, #20] /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) 80107a2: 687b ldr r3, [r7, #4] 80107a4: 691b ldr r3, [r3, #16] 80107a6: f003 0301 and.w r3, r3, #1 80107aa: 2b01 cmp r3, #1 80107ac: d105 bne.n 80107ba { /* Clear the update flag */ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); 80107ae: 687b ldr r3, [r7, #4] 80107b0: 691b ldr r3, [r3, #16] 80107b2: f023 0201 bic.w r2, r3, #1 80107b6: 687b ldr r3, [r7, #4] 80107b8: 611a str r2, [r3, #16] } } 80107ba: bf00 nop 80107bc: 3714 adds r7, #20 80107be: 46bd mov sp, r7 80107c0: f85d 7b04 ldr.w r7, [sp], #4 80107c4: 4770 bx lr 80107c6: bf00 nop 80107c8: 40010000 .word 0x40010000 80107cc: 40000400 .word 0x40000400 80107d0: 40000800 .word 0x40000800 80107d4: 40000c00 .word 0x40000c00 80107d8: 40010400 .word 0x40010400 80107dc: 40014000 .word 0x40014000 80107e0: 40014400 .word 0x40014400 80107e4: 40014800 .word 0x40014800 080107e8 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80107e8: b480 push {r7} 80107ea: b087 sub sp, #28 80107ec: af00 add r7, sp, #0 80107ee: 6078 str r0, [r7, #4] 80107f0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80107f2: 687b ldr r3, [r7, #4] 80107f4: 6a1b ldr r3, [r3, #32] 80107f6: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 80107f8: 687b ldr r3, [r7, #4] 80107fa: 6a1b ldr r3, [r3, #32] 80107fc: f023 0201 bic.w r2, r3, #1 8010800: 687b ldr r3, [r7, #4] 8010802: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010804: 687b ldr r3, [r7, #4] 8010806: 685b ldr r3, [r3, #4] 8010808: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 801080a: 687b ldr r3, [r7, #4] 801080c: 699b ldr r3, [r3, #24] 801080e: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 8010810: 68fa ldr r2, [r7, #12] 8010812: 4b37 ldr r3, [pc, #220] @ (80108f0 ) 8010814: 4013 ands r3, r2 8010816: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8010818: 68fb ldr r3, [r7, #12] 801081a: f023 0303 bic.w r3, r3, #3 801081e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010820: 683b ldr r3, [r7, #0] 8010822: 681b ldr r3, [r3, #0] 8010824: 68fa ldr r2, [r7, #12] 8010826: 4313 orrs r3, r2 8010828: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 801082a: 697b ldr r3, [r7, #20] 801082c: f023 0302 bic.w r3, r3, #2 8010830: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 8010832: 683b ldr r3, [r7, #0] 8010834: 689b ldr r3, [r3, #8] 8010836: 697a ldr r2, [r7, #20] 8010838: 4313 orrs r3, r2 801083a: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 801083c: 687b ldr r3, [r7, #4] 801083e: 4a2d ldr r2, [pc, #180] @ (80108f4 ) 8010840: 4293 cmp r3, r2 8010842: d00f beq.n 8010864 8010844: 687b ldr r3, [r7, #4] 8010846: 4a2c ldr r2, [pc, #176] @ (80108f8 ) 8010848: 4293 cmp r3, r2 801084a: d00b beq.n 8010864 801084c: 687b ldr r3, [r7, #4] 801084e: 4a2b ldr r2, [pc, #172] @ (80108fc ) 8010850: 4293 cmp r3, r2 8010852: d007 beq.n 8010864 8010854: 687b ldr r3, [r7, #4] 8010856: 4a2a ldr r2, [pc, #168] @ (8010900 ) 8010858: 4293 cmp r3, r2 801085a: d003 beq.n 8010864 801085c: 687b ldr r3, [r7, #4] 801085e: 4a29 ldr r2, [pc, #164] @ (8010904 ) 8010860: 4293 cmp r3, r2 8010862: d10c bne.n 801087e { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 8010864: 697b ldr r3, [r7, #20] 8010866: f023 0308 bic.w r3, r3, #8 801086a: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 801086c: 683b ldr r3, [r7, #0] 801086e: 68db ldr r3, [r3, #12] 8010870: 697a ldr r2, [r7, #20] 8010872: 4313 orrs r3, r2 8010874: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8010876: 697b ldr r3, [r7, #20] 8010878: f023 0304 bic.w r3, r3, #4 801087c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801087e: 687b ldr r3, [r7, #4] 8010880: 4a1c ldr r2, [pc, #112] @ (80108f4 ) 8010882: 4293 cmp r3, r2 8010884: d00f beq.n 80108a6 8010886: 687b ldr r3, [r7, #4] 8010888: 4a1b ldr r2, [pc, #108] @ (80108f8 ) 801088a: 4293 cmp r3, r2 801088c: d00b beq.n 80108a6 801088e: 687b ldr r3, [r7, #4] 8010890: 4a1a ldr r2, [pc, #104] @ (80108fc ) 8010892: 4293 cmp r3, r2 8010894: d007 beq.n 80108a6 8010896: 687b ldr r3, [r7, #4] 8010898: 4a19 ldr r2, [pc, #100] @ (8010900 ) 801089a: 4293 cmp r3, r2 801089c: d003 beq.n 80108a6 801089e: 687b ldr r3, [r7, #4] 80108a0: 4a18 ldr r2, [pc, #96] @ (8010904 ) 80108a2: 4293 cmp r3, r2 80108a4: d111 bne.n 80108ca /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 80108a6: 693b ldr r3, [r7, #16] 80108a8: f423 7380 bic.w r3, r3, #256 @ 0x100 80108ac: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80108ae: 693b ldr r3, [r7, #16] 80108b0: f423 7300 bic.w r3, r3, #512 @ 0x200 80108b4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 80108b6: 683b ldr r3, [r7, #0] 80108b8: 695b ldr r3, [r3, #20] 80108ba: 693a ldr r2, [r7, #16] 80108bc: 4313 orrs r3, r2 80108be: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 80108c0: 683b ldr r3, [r7, #0] 80108c2: 699b ldr r3, [r3, #24] 80108c4: 693a ldr r2, [r7, #16] 80108c6: 4313 orrs r3, r2 80108c8: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80108ca: 687b ldr r3, [r7, #4] 80108cc: 693a ldr r2, [r7, #16] 80108ce: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80108d0: 687b ldr r3, [r7, #4] 80108d2: 68fa ldr r2, [r7, #12] 80108d4: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80108d6: 683b ldr r3, [r7, #0] 80108d8: 685a ldr r2, [r3, #4] 80108da: 687b ldr r3, [r7, #4] 80108dc: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80108de: 687b ldr r3, [r7, #4] 80108e0: 697a ldr r2, [r7, #20] 80108e2: 621a str r2, [r3, #32] } 80108e4: bf00 nop 80108e6: 371c adds r7, #28 80108e8: 46bd mov sp, r7 80108ea: f85d 7b04 ldr.w r7, [sp], #4 80108ee: 4770 bx lr 80108f0: fffeff8f .word 0xfffeff8f 80108f4: 40010000 .word 0x40010000 80108f8: 40010400 .word 0x40010400 80108fc: 40014000 .word 0x40014000 8010900: 40014400 .word 0x40014400 8010904: 40014800 .word 0x40014800 08010908 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010908: b480 push {r7} 801090a: b087 sub sp, #28 801090c: af00 add r7, sp, #0 801090e: 6078 str r0, [r7, #4] 8010910: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010912: 687b ldr r3, [r7, #4] 8010914: 6a1b ldr r3, [r3, #32] 8010916: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8010918: 687b ldr r3, [r7, #4] 801091a: 6a1b ldr r3, [r3, #32] 801091c: f023 0210 bic.w r2, r3, #16 8010920: 687b ldr r3, [r7, #4] 8010922: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010924: 687b ldr r3, [r7, #4] 8010926: 685b ldr r3, [r3, #4] 8010928: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 801092a: 687b ldr r3, [r7, #4] 801092c: 699b ldr r3, [r3, #24] 801092e: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 8010930: 68fa ldr r2, [r7, #12] 8010932: 4b34 ldr r3, [pc, #208] @ (8010a04 ) 8010934: 4013 ands r3, r2 8010936: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8010938: 68fb ldr r3, [r7, #12] 801093a: f423 7340 bic.w r3, r3, #768 @ 0x300 801093e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010940: 683b ldr r3, [r7, #0] 8010942: 681b ldr r3, [r3, #0] 8010944: 021b lsls r3, r3, #8 8010946: 68fa ldr r2, [r7, #12] 8010948: 4313 orrs r3, r2 801094a: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 801094c: 697b ldr r3, [r7, #20] 801094e: f023 0320 bic.w r3, r3, #32 8010952: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 8010954: 683b ldr r3, [r7, #0] 8010956: 689b ldr r3, [r3, #8] 8010958: 011b lsls r3, r3, #4 801095a: 697a ldr r2, [r7, #20] 801095c: 4313 orrs r3, r2 801095e: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 8010960: 687b ldr r3, [r7, #4] 8010962: 4a29 ldr r2, [pc, #164] @ (8010a08 ) 8010964: 4293 cmp r3, r2 8010966: d003 beq.n 8010970 8010968: 687b ldr r3, [r7, #4] 801096a: 4a28 ldr r2, [pc, #160] @ (8010a0c ) 801096c: 4293 cmp r3, r2 801096e: d10d bne.n 801098c { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8010970: 697b ldr r3, [r7, #20] 8010972: f023 0380 bic.w r3, r3, #128 @ 0x80 8010976: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 8010978: 683b ldr r3, [r7, #0] 801097a: 68db ldr r3, [r3, #12] 801097c: 011b lsls r3, r3, #4 801097e: 697a ldr r2, [r7, #20] 8010980: 4313 orrs r3, r2 8010982: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8010984: 697b ldr r3, [r7, #20] 8010986: f023 0340 bic.w r3, r3, #64 @ 0x40 801098a: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 801098c: 687b ldr r3, [r7, #4] 801098e: 4a1e ldr r2, [pc, #120] @ (8010a08 ) 8010990: 4293 cmp r3, r2 8010992: d00f beq.n 80109b4 8010994: 687b ldr r3, [r7, #4] 8010996: 4a1d ldr r2, [pc, #116] @ (8010a0c ) 8010998: 4293 cmp r3, r2 801099a: d00b beq.n 80109b4 801099c: 687b ldr r3, [r7, #4] 801099e: 4a1c ldr r2, [pc, #112] @ (8010a10 ) 80109a0: 4293 cmp r3, r2 80109a2: d007 beq.n 80109b4 80109a4: 687b ldr r3, [r7, #4] 80109a6: 4a1b ldr r2, [pc, #108] @ (8010a14 ) 80109a8: 4293 cmp r3, r2 80109aa: d003 beq.n 80109b4 80109ac: 687b ldr r3, [r7, #4] 80109ae: 4a1a ldr r2, [pc, #104] @ (8010a18 ) 80109b0: 4293 cmp r3, r2 80109b2: d113 bne.n 80109dc /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 80109b4: 693b ldr r3, [r7, #16] 80109b6: f423 6380 bic.w r3, r3, #1024 @ 0x400 80109ba: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 80109bc: 693b ldr r3, [r7, #16] 80109be: f423 6300 bic.w r3, r3, #2048 @ 0x800 80109c2: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 80109c4: 683b ldr r3, [r7, #0] 80109c6: 695b ldr r3, [r3, #20] 80109c8: 009b lsls r3, r3, #2 80109ca: 693a ldr r2, [r7, #16] 80109cc: 4313 orrs r3, r2 80109ce: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 80109d0: 683b ldr r3, [r7, #0] 80109d2: 699b ldr r3, [r3, #24] 80109d4: 009b lsls r3, r3, #2 80109d6: 693a ldr r2, [r7, #16] 80109d8: 4313 orrs r3, r2 80109da: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80109dc: 687b ldr r3, [r7, #4] 80109de: 693a ldr r2, [r7, #16] 80109e0: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80109e2: 687b ldr r3, [r7, #4] 80109e4: 68fa ldr r2, [r7, #12] 80109e6: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 80109e8: 683b ldr r3, [r7, #0] 80109ea: 685a ldr r2, [r3, #4] 80109ec: 687b ldr r3, [r7, #4] 80109ee: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80109f0: 687b ldr r3, [r7, #4] 80109f2: 697a ldr r2, [r7, #20] 80109f4: 621a str r2, [r3, #32] } 80109f6: bf00 nop 80109f8: 371c adds r7, #28 80109fa: 46bd mov sp, r7 80109fc: f85d 7b04 ldr.w r7, [sp], #4 8010a00: 4770 bx lr 8010a02: bf00 nop 8010a04: feff8fff .word 0xfeff8fff 8010a08: 40010000 .word 0x40010000 8010a0c: 40010400 .word 0x40010400 8010a10: 40014000 .word 0x40014000 8010a14: 40014400 .word 0x40014400 8010a18: 40014800 .word 0x40014800 08010a1c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010a1c: b480 push {r7} 8010a1e: b087 sub sp, #28 8010a20: af00 add r7, sp, #0 8010a22: 6078 str r0, [r7, #4] 8010a24: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010a26: 687b ldr r3, [r7, #4] 8010a28: 6a1b ldr r3, [r3, #32] 8010a2a: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 8010a2c: 687b ldr r3, [r7, #4] 8010a2e: 6a1b ldr r3, [r3, #32] 8010a30: f423 7280 bic.w r2, r3, #256 @ 0x100 8010a34: 687b ldr r3, [r7, #4] 8010a36: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010a38: 687b ldr r3, [r7, #4] 8010a3a: 685b ldr r3, [r3, #4] 8010a3c: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8010a3e: 687b ldr r3, [r7, #4] 8010a40: 69db ldr r3, [r3, #28] 8010a42: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8010a44: 68fa ldr r2, [r7, #12] 8010a46: 4b33 ldr r3, [pc, #204] @ (8010b14 ) 8010a48: 4013 ands r3, r2 8010a4a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 8010a4c: 68fb ldr r3, [r7, #12] 8010a4e: f023 0303 bic.w r3, r3, #3 8010a52: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010a54: 683b ldr r3, [r7, #0] 8010a56: 681b ldr r3, [r3, #0] 8010a58: 68fa ldr r2, [r7, #12] 8010a5a: 4313 orrs r3, r2 8010a5c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 8010a5e: 697b ldr r3, [r7, #20] 8010a60: f423 7300 bic.w r3, r3, #512 @ 0x200 8010a64: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8010a66: 683b ldr r3, [r7, #0] 8010a68: 689b ldr r3, [r3, #8] 8010a6a: 021b lsls r3, r3, #8 8010a6c: 697a ldr r2, [r7, #20] 8010a6e: 4313 orrs r3, r2 8010a70: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8010a72: 687b ldr r3, [r7, #4] 8010a74: 4a28 ldr r2, [pc, #160] @ (8010b18 ) 8010a76: 4293 cmp r3, r2 8010a78: d003 beq.n 8010a82 8010a7a: 687b ldr r3, [r7, #4] 8010a7c: 4a27 ldr r2, [pc, #156] @ (8010b1c ) 8010a7e: 4293 cmp r3, r2 8010a80: d10d bne.n 8010a9e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 8010a82: 697b ldr r3, [r7, #20] 8010a84: f423 6300 bic.w r3, r3, #2048 @ 0x800 8010a88: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8010a8a: 683b ldr r3, [r7, #0] 8010a8c: 68db ldr r3, [r3, #12] 8010a8e: 021b lsls r3, r3, #8 8010a90: 697a ldr r2, [r7, #20] 8010a92: 4313 orrs r3, r2 8010a94: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 8010a96: 697b ldr r3, [r7, #20] 8010a98: f423 6380 bic.w r3, r3, #1024 @ 0x400 8010a9c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010a9e: 687b ldr r3, [r7, #4] 8010aa0: 4a1d ldr r2, [pc, #116] @ (8010b18 ) 8010aa2: 4293 cmp r3, r2 8010aa4: d00f beq.n 8010ac6 8010aa6: 687b ldr r3, [r7, #4] 8010aa8: 4a1c ldr r2, [pc, #112] @ (8010b1c ) 8010aaa: 4293 cmp r3, r2 8010aac: d00b beq.n 8010ac6 8010aae: 687b ldr r3, [r7, #4] 8010ab0: 4a1b ldr r2, [pc, #108] @ (8010b20 ) 8010ab2: 4293 cmp r3, r2 8010ab4: d007 beq.n 8010ac6 8010ab6: 687b ldr r3, [r7, #4] 8010ab8: 4a1a ldr r2, [pc, #104] @ (8010b24 ) 8010aba: 4293 cmp r3, r2 8010abc: d003 beq.n 8010ac6 8010abe: 687b ldr r3, [r7, #4] 8010ac0: 4a19 ldr r2, [pc, #100] @ (8010b28 ) 8010ac2: 4293 cmp r3, r2 8010ac4: d113 bne.n 8010aee /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 8010ac6: 693b ldr r3, [r7, #16] 8010ac8: f423 5380 bic.w r3, r3, #4096 @ 0x1000 8010acc: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8010ace: 693b ldr r3, [r7, #16] 8010ad0: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010ad4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 8010ad6: 683b ldr r3, [r7, #0] 8010ad8: 695b ldr r3, [r3, #20] 8010ada: 011b lsls r3, r3, #4 8010adc: 693a ldr r2, [r7, #16] 8010ade: 4313 orrs r3, r2 8010ae0: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 8010ae2: 683b ldr r3, [r7, #0] 8010ae4: 699b ldr r3, [r3, #24] 8010ae6: 011b lsls r3, r3, #4 8010ae8: 693a ldr r2, [r7, #16] 8010aea: 4313 orrs r3, r2 8010aec: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010aee: 687b ldr r3, [r7, #4] 8010af0: 693a ldr r2, [r7, #16] 8010af2: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010af4: 687b ldr r3, [r7, #4] 8010af6: 68fa ldr r2, [r7, #12] 8010af8: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 8010afa: 683b ldr r3, [r7, #0] 8010afc: 685a ldr r2, [r3, #4] 8010afe: 687b ldr r3, [r7, #4] 8010b00: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010b02: 687b ldr r3, [r7, #4] 8010b04: 697a ldr r2, [r7, #20] 8010b06: 621a str r2, [r3, #32] } 8010b08: bf00 nop 8010b0a: 371c adds r7, #28 8010b0c: 46bd mov sp, r7 8010b0e: f85d 7b04 ldr.w r7, [sp], #4 8010b12: 4770 bx lr 8010b14: fffeff8f .word 0xfffeff8f 8010b18: 40010000 .word 0x40010000 8010b1c: 40010400 .word 0x40010400 8010b20: 40014000 .word 0x40014000 8010b24: 40014400 .word 0x40014400 8010b28: 40014800 .word 0x40014800 08010b2c : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010b2c: b480 push {r7} 8010b2e: b087 sub sp, #28 8010b30: af00 add r7, sp, #0 8010b32: 6078 str r0, [r7, #4] 8010b34: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010b36: 687b ldr r3, [r7, #4] 8010b38: 6a1b ldr r3, [r3, #32] 8010b3a: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8010b3c: 687b ldr r3, [r7, #4] 8010b3e: 6a1b ldr r3, [r3, #32] 8010b40: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8010b44: 687b ldr r3, [r7, #4] 8010b46: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010b48: 687b ldr r3, [r7, #4] 8010b4a: 685b ldr r3, [r3, #4] 8010b4c: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8010b4e: 687b ldr r3, [r7, #4] 8010b50: 69db ldr r3, [r3, #28] 8010b52: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8010b54: 68fa ldr r2, [r7, #12] 8010b56: 4b24 ldr r3, [pc, #144] @ (8010be8 ) 8010b58: 4013 ands r3, r2 8010b5a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8010b5c: 68fb ldr r3, [r7, #12] 8010b5e: f423 7340 bic.w r3, r3, #768 @ 0x300 8010b62: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010b64: 683b ldr r3, [r7, #0] 8010b66: 681b ldr r3, [r3, #0] 8010b68: 021b lsls r3, r3, #8 8010b6a: 68fa ldr r2, [r7, #12] 8010b6c: 4313 orrs r3, r2 8010b6e: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8010b70: 693b ldr r3, [r7, #16] 8010b72: f423 5300 bic.w r3, r3, #8192 @ 0x2000 8010b76: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 8010b78: 683b ldr r3, [r7, #0] 8010b7a: 689b ldr r3, [r3, #8] 8010b7c: 031b lsls r3, r3, #12 8010b7e: 693a ldr r2, [r7, #16] 8010b80: 4313 orrs r3, r2 8010b82: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010b84: 687b ldr r3, [r7, #4] 8010b86: 4a19 ldr r2, [pc, #100] @ (8010bec ) 8010b88: 4293 cmp r3, r2 8010b8a: d00f beq.n 8010bac 8010b8c: 687b ldr r3, [r7, #4] 8010b8e: 4a18 ldr r2, [pc, #96] @ (8010bf0 ) 8010b90: 4293 cmp r3, r2 8010b92: d00b beq.n 8010bac 8010b94: 687b ldr r3, [r7, #4] 8010b96: 4a17 ldr r2, [pc, #92] @ (8010bf4 ) 8010b98: 4293 cmp r3, r2 8010b9a: d007 beq.n 8010bac 8010b9c: 687b ldr r3, [r7, #4] 8010b9e: 4a16 ldr r2, [pc, #88] @ (8010bf8 ) 8010ba0: 4293 cmp r3, r2 8010ba2: d003 beq.n 8010bac 8010ba4: 687b ldr r3, [r7, #4] 8010ba6: 4a15 ldr r2, [pc, #84] @ (8010bfc ) 8010ba8: 4293 cmp r3, r2 8010baa: d109 bne.n 8010bc0 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8010bac: 697b ldr r3, [r7, #20] 8010bae: f423 4380 bic.w r3, r3, #16384 @ 0x4000 8010bb2: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8010bb4: 683b ldr r3, [r7, #0] 8010bb6: 695b ldr r3, [r3, #20] 8010bb8: 019b lsls r3, r3, #6 8010bba: 697a ldr r2, [r7, #20] 8010bbc: 4313 orrs r3, r2 8010bbe: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010bc0: 687b ldr r3, [r7, #4] 8010bc2: 697a ldr r2, [r7, #20] 8010bc4: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 8010bc6: 687b ldr r3, [r7, #4] 8010bc8: 68fa ldr r2, [r7, #12] 8010bca: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8010bcc: 683b ldr r3, [r7, #0] 8010bce: 685a ldr r2, [r3, #4] 8010bd0: 687b ldr r3, [r7, #4] 8010bd2: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010bd4: 687b ldr r3, [r7, #4] 8010bd6: 693a ldr r2, [r7, #16] 8010bd8: 621a str r2, [r3, #32] } 8010bda: bf00 nop 8010bdc: 371c adds r7, #28 8010bde: 46bd mov sp, r7 8010be0: f85d 7b04 ldr.w r7, [sp], #4 8010be4: 4770 bx lr 8010be6: bf00 nop 8010be8: feff8fff .word 0xfeff8fff 8010bec: 40010000 .word 0x40010000 8010bf0: 40010400 .word 0x40010400 8010bf4: 40014000 .word 0x40014000 8010bf8: 40014400 .word 0x40014400 8010bfc: 40014800 .word 0x40014800 08010c00 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010c00: b480 push {r7} 8010c02: b087 sub sp, #28 8010c04: af00 add r7, sp, #0 8010c06: 6078 str r0, [r7, #4] 8010c08: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010c0a: 687b ldr r3, [r7, #4] 8010c0c: 6a1b ldr r3, [r3, #32] 8010c0e: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 8010c10: 687b ldr r3, [r7, #4] 8010c12: 6a1b ldr r3, [r3, #32] 8010c14: f423 3280 bic.w r2, r3, #65536 @ 0x10000 8010c18: 687b ldr r3, [r7, #4] 8010c1a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010c1c: 687b ldr r3, [r7, #4] 8010c1e: 685b ldr r3, [r3, #4] 8010c20: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010c22: 687b ldr r3, [r7, #4] 8010c24: 6d5b ldr r3, [r3, #84] @ 0x54 8010c26: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 8010c28: 68fa ldr r2, [r7, #12] 8010c2a: 4b21 ldr r3, [pc, #132] @ (8010cb0 ) 8010c2c: 4013 ands r3, r2 8010c2e: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8010c30: 683b ldr r3, [r7, #0] 8010c32: 681b ldr r3, [r3, #0] 8010c34: 68fa ldr r2, [r7, #12] 8010c36: 4313 orrs r3, r2 8010c38: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 8010c3a: 693b ldr r3, [r7, #16] 8010c3c: f423 3300 bic.w r3, r3, #131072 @ 0x20000 8010c40: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 8010c42: 683b ldr r3, [r7, #0] 8010c44: 689b ldr r3, [r3, #8] 8010c46: 041b lsls r3, r3, #16 8010c48: 693a ldr r2, [r7, #16] 8010c4a: 4313 orrs r3, r2 8010c4c: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010c4e: 687b ldr r3, [r7, #4] 8010c50: 4a18 ldr r2, [pc, #96] @ (8010cb4 ) 8010c52: 4293 cmp r3, r2 8010c54: d00f beq.n 8010c76 8010c56: 687b ldr r3, [r7, #4] 8010c58: 4a17 ldr r2, [pc, #92] @ (8010cb8 ) 8010c5a: 4293 cmp r3, r2 8010c5c: d00b beq.n 8010c76 8010c5e: 687b ldr r3, [r7, #4] 8010c60: 4a16 ldr r2, [pc, #88] @ (8010cbc ) 8010c62: 4293 cmp r3, r2 8010c64: d007 beq.n 8010c76 8010c66: 687b ldr r3, [r7, #4] 8010c68: 4a15 ldr r2, [pc, #84] @ (8010cc0 ) 8010c6a: 4293 cmp r3, r2 8010c6c: d003 beq.n 8010c76 8010c6e: 687b ldr r3, [r7, #4] 8010c70: 4a14 ldr r2, [pc, #80] @ (8010cc4 ) 8010c72: 4293 cmp r3, r2 8010c74: d109 bne.n 8010c8a { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 8010c76: 697b ldr r3, [r7, #20] 8010c78: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8010c7c: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 8010c7e: 683b ldr r3, [r7, #0] 8010c80: 695b ldr r3, [r3, #20] 8010c82: 021b lsls r3, r3, #8 8010c84: 697a ldr r2, [r7, #20] 8010c86: 4313 orrs r3, r2 8010c88: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010c8a: 687b ldr r3, [r7, #4] 8010c8c: 697a ldr r2, [r7, #20] 8010c8e: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010c90: 687b ldr r3, [r7, #4] 8010c92: 68fa ldr r2, [r7, #12] 8010c94: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 8010c96: 683b ldr r3, [r7, #0] 8010c98: 685a ldr r2, [r3, #4] 8010c9a: 687b ldr r3, [r7, #4] 8010c9c: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010c9e: 687b ldr r3, [r7, #4] 8010ca0: 693a ldr r2, [r7, #16] 8010ca2: 621a str r2, [r3, #32] } 8010ca4: bf00 nop 8010ca6: 371c adds r7, #28 8010ca8: 46bd mov sp, r7 8010caa: f85d 7b04 ldr.w r7, [sp], #4 8010cae: 4770 bx lr 8010cb0: fffeff8f .word 0xfffeff8f 8010cb4: 40010000 .word 0x40010000 8010cb8: 40010400 .word 0x40010400 8010cbc: 40014000 .word 0x40014000 8010cc0: 40014400 .word 0x40014400 8010cc4: 40014800 .word 0x40014800 08010cc8 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8010cc8: b480 push {r7} 8010cca: b087 sub sp, #28 8010ccc: af00 add r7, sp, #0 8010cce: 6078 str r0, [r7, #4] 8010cd0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8010cd2: 687b ldr r3, [r7, #4] 8010cd4: 6a1b ldr r3, [r3, #32] 8010cd6: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 8010cd8: 687b ldr r3, [r7, #4] 8010cda: 6a1b ldr r3, [r3, #32] 8010cdc: f423 1280 bic.w r2, r3, #1048576 @ 0x100000 8010ce0: 687b ldr r3, [r7, #4] 8010ce2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8010ce4: 687b ldr r3, [r7, #4] 8010ce6: 685b ldr r3, [r3, #4] 8010ce8: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 8010cea: 687b ldr r3, [r7, #4] 8010cec: 6d5b ldr r3, [r3, #84] @ 0x54 8010cee: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 8010cf0: 68fa ldr r2, [r7, #12] 8010cf2: 4b22 ldr r3, [pc, #136] @ (8010d7c ) 8010cf4: 4013 ands r3, r2 8010cf6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8010cf8: 683b ldr r3, [r7, #0] 8010cfa: 681b ldr r3, [r3, #0] 8010cfc: 021b lsls r3, r3, #8 8010cfe: 68fa ldr r2, [r7, #12] 8010d00: 4313 orrs r3, r2 8010d02: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 8010d04: 693b ldr r3, [r7, #16] 8010d06: f423 1300 bic.w r3, r3, #2097152 @ 0x200000 8010d0a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 8010d0c: 683b ldr r3, [r7, #0] 8010d0e: 689b ldr r3, [r3, #8] 8010d10: 051b lsls r3, r3, #20 8010d12: 693a ldr r2, [r7, #16] 8010d14: 4313 orrs r3, r2 8010d16: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8010d18: 687b ldr r3, [r7, #4] 8010d1a: 4a19 ldr r2, [pc, #100] @ (8010d80 ) 8010d1c: 4293 cmp r3, r2 8010d1e: d00f beq.n 8010d40 8010d20: 687b ldr r3, [r7, #4] 8010d22: 4a18 ldr r2, [pc, #96] @ (8010d84 ) 8010d24: 4293 cmp r3, r2 8010d26: d00b beq.n 8010d40 8010d28: 687b ldr r3, [r7, #4] 8010d2a: 4a17 ldr r2, [pc, #92] @ (8010d88 ) 8010d2c: 4293 cmp r3, r2 8010d2e: d007 beq.n 8010d40 8010d30: 687b ldr r3, [r7, #4] 8010d32: 4a16 ldr r2, [pc, #88] @ (8010d8c ) 8010d34: 4293 cmp r3, r2 8010d36: d003 beq.n 8010d40 8010d38: 687b ldr r3, [r7, #4] 8010d3a: 4a15 ldr r2, [pc, #84] @ (8010d90 ) 8010d3c: 4293 cmp r3, r2 8010d3e: d109 bne.n 8010d54 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 8010d40: 697b ldr r3, [r7, #20] 8010d42: f423 2380 bic.w r3, r3, #262144 @ 0x40000 8010d46: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 8010d48: 683b ldr r3, [r7, #0] 8010d4a: 695b ldr r3, [r3, #20] 8010d4c: 029b lsls r3, r3, #10 8010d4e: 697a ldr r2, [r7, #20] 8010d50: 4313 orrs r3, r2 8010d52: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8010d54: 687b ldr r3, [r7, #4] 8010d56: 697a ldr r2, [r7, #20] 8010d58: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8010d5a: 687b ldr r3, [r7, #4] 8010d5c: 68fa ldr r2, [r7, #12] 8010d5e: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8010d60: 683b ldr r3, [r7, #0] 8010d62: 685a ldr r2, [r3, #4] 8010d64: 687b ldr r3, [r7, #4] 8010d66: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8010d68: 687b ldr r3, [r7, #4] 8010d6a: 693a ldr r2, [r7, #16] 8010d6c: 621a str r2, [r3, #32] } 8010d6e: bf00 nop 8010d70: 371c adds r7, #28 8010d72: 46bd mov sp, r7 8010d74: f85d 7b04 ldr.w r7, [sp], #4 8010d78: 4770 bx lr 8010d7a: bf00 nop 8010d7c: feff8fff .word 0xfeff8fff 8010d80: 40010000 .word 0x40010000 8010d84: 40010400 .word 0x40010400 8010d88: 40014000 .word 0x40014000 8010d8c: 40014400 .word 0x40014400 8010d90: 40014800 .word 0x40014800 08010d94 : * (on channel2 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010d94: b480 push {r7} 8010d96: b087 sub sp, #28 8010d98: af00 add r7, sp, #0 8010d9a: 60f8 str r0, [r7, #12] 8010d9c: 60b9 str r1, [r7, #8] 8010d9e: 607a str r2, [r7, #4] 8010da0: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010da2: 68fb ldr r3, [r7, #12] 8010da4: 6a1b ldr r3, [r3, #32] 8010da6: 613b str r3, [r7, #16] TIMx->CCER &= ~TIM_CCER_CC1E; 8010da8: 68fb ldr r3, [r7, #12] 8010daa: 6a1b ldr r3, [r3, #32] 8010dac: f023 0201 bic.w r2, r3, #1 8010db0: 68fb ldr r3, [r7, #12] 8010db2: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010db4: 68fb ldr r3, [r7, #12] 8010db6: 699b ldr r3, [r3, #24] 8010db8: 617b str r3, [r7, #20] /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) 8010dba: 68fb ldr r3, [r7, #12] 8010dbc: 4a28 ldr r2, [pc, #160] @ (8010e60 ) 8010dbe: 4293 cmp r3, r2 8010dc0: d01b beq.n 8010dfa 8010dc2: 68fb ldr r3, [r7, #12] 8010dc4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8010dc8: d017 beq.n 8010dfa 8010dca: 68fb ldr r3, [r7, #12] 8010dcc: 4a25 ldr r2, [pc, #148] @ (8010e64 ) 8010dce: 4293 cmp r3, r2 8010dd0: d013 beq.n 8010dfa 8010dd2: 68fb ldr r3, [r7, #12] 8010dd4: 4a24 ldr r2, [pc, #144] @ (8010e68 ) 8010dd6: 4293 cmp r3, r2 8010dd8: d00f beq.n 8010dfa 8010dda: 68fb ldr r3, [r7, #12] 8010ddc: 4a23 ldr r2, [pc, #140] @ (8010e6c ) 8010dde: 4293 cmp r3, r2 8010de0: d00b beq.n 8010dfa 8010de2: 68fb ldr r3, [r7, #12] 8010de4: 4a22 ldr r2, [pc, #136] @ (8010e70 ) 8010de6: 4293 cmp r3, r2 8010de8: d007 beq.n 8010dfa 8010dea: 68fb ldr r3, [r7, #12] 8010dec: 4a21 ldr r2, [pc, #132] @ (8010e74 ) 8010dee: 4293 cmp r3, r2 8010df0: d003 beq.n 8010dfa 8010df2: 68fb ldr r3, [r7, #12] 8010df4: 4a20 ldr r2, [pc, #128] @ (8010e78 ) 8010df6: 4293 cmp r3, r2 8010df8: d101 bne.n 8010dfe 8010dfa: 2301 movs r3, #1 8010dfc: e000 b.n 8010e00 8010dfe: 2300 movs r3, #0 8010e00: 2b00 cmp r3, #0 8010e02: d008 beq.n 8010e16 { tmpccmr1 &= ~TIM_CCMR1_CC1S; 8010e04: 697b ldr r3, [r7, #20] 8010e06: f023 0303 bic.w r3, r3, #3 8010e0a: 617b str r3, [r7, #20] tmpccmr1 |= TIM_ICSelection; 8010e0c: 697a ldr r2, [r7, #20] 8010e0e: 687b ldr r3, [r7, #4] 8010e10: 4313 orrs r3, r2 8010e12: 617b str r3, [r7, #20] 8010e14: e003 b.n 8010e1e } else { tmpccmr1 |= TIM_CCMR1_CC1S_0; 8010e16: 697b ldr r3, [r7, #20] 8010e18: f043 0301 orr.w r3, r3, #1 8010e1c: 617b str r3, [r7, #20] } /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010e1e: 697b ldr r3, [r7, #20] 8010e20: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010e24: 617b str r3, [r7, #20] tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); 8010e26: 683b ldr r3, [r7, #0] 8010e28: 011b lsls r3, r3, #4 8010e2a: b2db uxtb r3, r3 8010e2c: 697a ldr r2, [r7, #20] 8010e2e: 4313 orrs r3, r2 8010e30: 617b str r3, [r7, #20] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010e32: 693b ldr r3, [r7, #16] 8010e34: f023 030a bic.w r3, r3, #10 8010e38: 613b str r3, [r7, #16] tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 8010e3a: 68bb ldr r3, [r7, #8] 8010e3c: f003 030a and.w r3, r3, #10 8010e40: 693a ldr r2, [r7, #16] 8010e42: 4313 orrs r3, r2 8010e44: 613b str r3, [r7, #16] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010e46: 68fb ldr r3, [r7, #12] 8010e48: 697a ldr r2, [r7, #20] 8010e4a: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010e4c: 68fb ldr r3, [r7, #12] 8010e4e: 693a ldr r2, [r7, #16] 8010e50: 621a str r2, [r3, #32] } 8010e52: bf00 nop 8010e54: 371c adds r7, #28 8010e56: 46bd mov sp, r7 8010e58: f85d 7b04 ldr.w r7, [sp], #4 8010e5c: 4770 bx lr 8010e5e: bf00 nop 8010e60: 40010000 .word 0x40010000 8010e64: 40000400 .word 0x40000400 8010e68: 40000800 .word 0x40000800 8010e6c: 40000c00 .word 0x40000c00 8010e70: 40010400 .word 0x40010400 8010e74: 40001800 .word 0x40001800 8010e78: 40014000 .word 0x40014000 08010e7c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010e7c: b480 push {r7} 8010e7e: b087 sub sp, #28 8010e80: af00 add r7, sp, #0 8010e82: 60f8 str r0, [r7, #12] 8010e84: 60b9 str r1, [r7, #8] 8010e86: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8010e88: 68fb ldr r3, [r7, #12] 8010e8a: 6a1b ldr r3, [r3, #32] 8010e8c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8010e8e: 68fb ldr r3, [r7, #12] 8010e90: 6a1b ldr r3, [r3, #32] 8010e92: f023 0201 bic.w r2, r3, #1 8010e96: 68fb ldr r3, [r7, #12] 8010e98: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010e9a: 68fb ldr r3, [r7, #12] 8010e9c: 699b ldr r3, [r3, #24] 8010e9e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8010ea0: 693b ldr r3, [r7, #16] 8010ea2: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010ea6: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8010ea8: 687b ldr r3, [r7, #4] 8010eaa: 011b lsls r3, r3, #4 8010eac: 693a ldr r2, [r7, #16] 8010eae: 4313 orrs r3, r2 8010eb0: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8010eb2: 697b ldr r3, [r7, #20] 8010eb4: f023 030a bic.w r3, r3, #10 8010eb8: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8010eba: 697a ldr r2, [r7, #20] 8010ebc: 68bb ldr r3, [r7, #8] 8010ebe: 4313 orrs r3, r2 8010ec0: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8010ec2: 68fb ldr r3, [r7, #12] 8010ec4: 693a ldr r2, [r7, #16] 8010ec6: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010ec8: 68fb ldr r3, [r7, #12] 8010eca: 697a ldr r2, [r7, #20] 8010ecc: 621a str r2, [r3, #32] } 8010ece: bf00 nop 8010ed0: 371c adds r7, #28 8010ed2: 46bd mov sp, r7 8010ed4: f85d 7b04 ldr.w r7, [sp], #4 8010ed8: 4770 bx lr 08010eda : * (on channel1 path) is used as the input signal. Therefore CCMR1 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010eda: b480 push {r7} 8010edc: b087 sub sp, #28 8010ede: af00 add r7, sp, #0 8010ee0: 60f8 str r0, [r7, #12] 8010ee2: 60b9 str r1, [r7, #8] 8010ee4: 607a str r2, [r7, #4] 8010ee6: 603b str r3, [r7, #0] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8010ee8: 68fb ldr r3, [r7, #12] 8010eea: 6a1b ldr r3, [r3, #32] 8010eec: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010eee: 68fb ldr r3, [r7, #12] 8010ef0: 6a1b ldr r3, [r3, #32] 8010ef2: f023 0210 bic.w r2, r3, #16 8010ef6: 68fb ldr r3, [r7, #12] 8010ef8: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010efa: 68fb ldr r3, [r7, #12] 8010efc: 699b ldr r3, [r3, #24] 8010efe: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; 8010f00: 693b ldr r3, [r7, #16] 8010f02: f423 7340 bic.w r3, r3, #768 @ 0x300 8010f06: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICSelection << 8U); 8010f08: 687b ldr r3, [r7, #4] 8010f0a: 021b lsls r3, r3, #8 8010f0c: 693a ldr r2, [r7, #16] 8010f0e: 4313 orrs r3, r2 8010f10: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010f12: 693b ldr r3, [r7, #16] 8010f14: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010f18: 613b str r3, [r7, #16] tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); 8010f1a: 683b ldr r3, [r7, #0] 8010f1c: 031b lsls r3, r3, #12 8010f1e: b29b uxth r3, r3 8010f20: 693a ldr r2, [r7, #16] 8010f22: 4313 orrs r3, r2 8010f24: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010f26: 697b ldr r3, [r7, #20] 8010f28: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8010f2c: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 8010f2e: 68bb ldr r3, [r7, #8] 8010f30: 011b lsls r3, r3, #4 8010f32: f003 03a0 and.w r3, r3, #160 @ 0xa0 8010f36: 697a ldr r2, [r7, #20] 8010f38: 4313 orrs r3, r2 8010f3a: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010f3c: 68fb ldr r3, [r7, #12] 8010f3e: 693a ldr r2, [r7, #16] 8010f40: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010f42: 68fb ldr r3, [r7, #12] 8010f44: 697a ldr r2, [r7, #20] 8010f46: 621a str r2, [r3, #32] } 8010f48: bf00 nop 8010f4a: 371c adds r7, #28 8010f4c: 46bd mov sp, r7 8010f4e: f85d 7b04 ldr.w r7, [sp], #4 8010f52: 4770 bx lr 08010f54 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8010f54: b480 push {r7} 8010f56: b087 sub sp, #28 8010f58: af00 add r7, sp, #0 8010f5a: 60f8 str r0, [r7, #12] 8010f5c: 60b9 str r1, [r7, #8] 8010f5e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8010f60: 68fb ldr r3, [r7, #12] 8010f62: 6a1b ldr r3, [r3, #32] 8010f64: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8010f66: 68fb ldr r3, [r7, #12] 8010f68: 6a1b ldr r3, [r3, #32] 8010f6a: f023 0210 bic.w r2, r3, #16 8010f6e: 68fb ldr r3, [r7, #12] 8010f70: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8010f72: 68fb ldr r3, [r7, #12] 8010f74: 699b ldr r3, [r3, #24] 8010f76: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8010f78: 693b ldr r3, [r7, #16] 8010f7a: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8010f7e: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8010f80: 687b ldr r3, [r7, #4] 8010f82: 031b lsls r3, r3, #12 8010f84: 693a ldr r2, [r7, #16] 8010f86: 4313 orrs r3, r2 8010f88: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8010f8a: 697b ldr r3, [r7, #20] 8010f8c: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8010f90: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8010f92: 68bb ldr r3, [r7, #8] 8010f94: 011b lsls r3, r3, #4 8010f96: 697a ldr r2, [r7, #20] 8010f98: 4313 orrs r3, r2 8010f9a: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8010f9c: 68fb ldr r3, [r7, #12] 8010f9e: 693a ldr r2, [r7, #16] 8010fa0: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8010fa2: 68fb ldr r3, [r7, #12] 8010fa4: 697a ldr r2, [r7, #20] 8010fa6: 621a str r2, [r3, #32] } 8010fa8: bf00 nop 8010faa: 371c adds r7, #28 8010fac: 46bd mov sp, r7 8010fae: f85d 7b04 ldr.w r7, [sp], #4 8010fb2: 4770 bx lr 08010fb4 : * (on channel1 path) is used as the input signal. Therefore CCMR2 must be * protected against un-initialized filter and polarity values. */ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 8010fb4: b480 push {r7} 8010fb6: b087 sub sp, #28 8010fb8: af00 add r7, sp, #0 8010fba: 60f8 str r0, [r7, #12] 8010fbc: 60b9 str r1, [r7, #8] 8010fbe: 607a str r2, [r7, #4] 8010fc0: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ tmpccer = TIMx->CCER; 8010fc2: 68fb ldr r3, [r7, #12] 8010fc4: 6a1b ldr r3, [r3, #32] 8010fc6: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC3E; 8010fc8: 68fb ldr r3, [r7, #12] 8010fca: 6a1b ldr r3, [r3, #32] 8010fcc: f423 7280 bic.w r2, r3, #256 @ 0x100 8010fd0: 68fb ldr r3, [r7, #12] 8010fd2: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 8010fd4: 68fb ldr r3, [r7, #12] 8010fd6: 69db ldr r3, [r3, #28] 8010fd8: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; 8010fda: 693b ldr r3, [r7, #16] 8010fdc: f023 0303 bic.w r3, r3, #3 8010fe0: 613b str r3, [r7, #16] tmpccmr2 |= TIM_ICSelection; 8010fe2: 693a ldr r2, [r7, #16] 8010fe4: 687b ldr r3, [r7, #4] 8010fe6: 4313 orrs r3, r2 8010fe8: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; 8010fea: 693b ldr r3, [r7, #16] 8010fec: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8010ff0: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); 8010ff2: 683b ldr r3, [r7, #0] 8010ff4: 011b lsls r3, r3, #4 8010ff6: b2db uxtb r3, r3 8010ff8: 693a ldr r2, [r7, #16] 8010ffa: 4313 orrs r3, r2 8010ffc: 613b str r3, [r7, #16] /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 8010ffe: 697b ldr r3, [r7, #20] 8011000: f423 6320 bic.w r3, r3, #2560 @ 0xa00 8011004: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 8011006: 68bb ldr r3, [r7, #8] 8011008: 021b lsls r3, r3, #8 801100a: f403 6320 and.w r3, r3, #2560 @ 0xa00 801100e: 697a ldr r2, [r7, #20] 8011010: 4313 orrs r3, r2 8011012: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 8011014: 68fb ldr r3, [r7, #12] 8011016: 693a ldr r2, [r7, #16] 8011018: 61da str r2, [r3, #28] TIMx->CCER = tmpccer; 801101a: 68fb ldr r3, [r7, #12] 801101c: 697a ldr r2, [r7, #20] 801101e: 621a str r2, [r3, #32] } 8011020: bf00 nop 8011022: 371c adds r7, #28 8011024: 46bd mov sp, r7 8011026: f85d 7b04 ldr.w r7, [sp], #4 801102a: 4770 bx lr 0801102c : * protected against un-initialized filter and polarity values. * @retval None */ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { 801102c: b480 push {r7} 801102e: b087 sub sp, #28 8011030: af00 add r7, sp, #0 8011032: 60f8 str r0, [r7, #12] 8011034: 60b9 str r1, [r7, #8] 8011036: 607a str r2, [r7, #4] 8011038: 603b str r3, [r7, #0] uint32_t tmpccmr2; uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ tmpccer = TIMx->CCER; 801103a: 68fb ldr r3, [r7, #12] 801103c: 6a1b ldr r3, [r3, #32] 801103e: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC4E; 8011040: 68fb ldr r3, [r7, #12] 8011042: 6a1b ldr r3, [r3, #32] 8011044: f423 5280 bic.w r2, r3, #4096 @ 0x1000 8011048: 68fb ldr r3, [r7, #12] 801104a: 621a str r2, [r3, #32] tmpccmr2 = TIMx->CCMR2; 801104c: 68fb ldr r3, [r7, #12] 801104e: 69db ldr r3, [r3, #28] 8011050: 613b str r3, [r7, #16] /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; 8011052: 693b ldr r3, [r7, #16] 8011054: f423 7340 bic.w r3, r3, #768 @ 0x300 8011058: 613b str r3, [r7, #16] tmpccmr2 |= (TIM_ICSelection << 8U); 801105a: 687b ldr r3, [r7, #4] 801105c: 021b lsls r3, r3, #8 801105e: 693a ldr r2, [r7, #16] 8011060: 4313 orrs r3, r2 8011062: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; 8011064: 693b ldr r3, [r7, #16] 8011066: f423 4370 bic.w r3, r3, #61440 @ 0xf000 801106a: 613b str r3, [r7, #16] tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); 801106c: 683b ldr r3, [r7, #0] 801106e: 031b lsls r3, r3, #12 8011070: b29b uxth r3, r3 8011072: 693a ldr r2, [r7, #16] 8011074: 4313 orrs r3, r2 8011076: 613b str r3, [r7, #16] /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 8011078: 697b ldr r3, [r7, #20] 801107a: f423 4320 bic.w r3, r3, #40960 @ 0xa000 801107e: 617b str r3, [r7, #20] tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 8011080: 68bb ldr r3, [r7, #8] 8011082: 031b lsls r3, r3, #12 8011084: f403 4320 and.w r3, r3, #40960 @ 0xa000 8011088: 697a ldr r2, [r7, #20] 801108a: 4313 orrs r3, r2 801108c: 617b str r3, [r7, #20] /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; 801108e: 68fb ldr r3, [r7, #12] 8011090: 693a ldr r2, [r7, #16] 8011092: 61da str r2, [r3, #28] TIMx->CCER = tmpccer ; 8011094: 68fb ldr r3, [r7, #12] 8011096: 697a ldr r2, [r7, #20] 8011098: 621a str r2, [r3, #32] } 801109a: bf00 nop 801109c: 371c adds r7, #28 801109e: 46bd mov sp, r7 80110a0: f85d 7b04 ldr.w r7, [sp], #4 80110a4: 4770 bx lr ... 080110a8 : * (*) Value not defined in all devices. * * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 80110a8: b480 push {r7} 80110aa: b085 sub sp, #20 80110ac: af00 add r7, sp, #0 80110ae: 6078 str r0, [r7, #4] 80110b0: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 80110b2: 687b ldr r3, [r7, #4] 80110b4: 689b ldr r3, [r3, #8] 80110b6: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 80110b8: 68fa ldr r2, [r7, #12] 80110ba: 4b09 ldr r3, [pc, #36] @ (80110e0 ) 80110bc: 4013 ands r3, r2 80110be: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 80110c0: 683a ldr r2, [r7, #0] 80110c2: 68fb ldr r3, [r7, #12] 80110c4: 4313 orrs r3, r2 80110c6: f043 0307 orr.w r3, r3, #7 80110ca: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 80110cc: 687b ldr r3, [r7, #4] 80110ce: 68fa ldr r2, [r7, #12] 80110d0: 609a str r2, [r3, #8] } 80110d2: bf00 nop 80110d4: 3714 adds r7, #20 80110d6: 46bd mov sp, r7 80110d8: f85d 7b04 ldr.w r7, [sp], #4 80110dc: 4770 bx lr 80110de: bf00 nop 80110e0: ffcfff8f .word 0xffcfff8f 080110e4 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 80110e4: b480 push {r7} 80110e6: b087 sub sp, #28 80110e8: af00 add r7, sp, #0 80110ea: 60f8 str r0, [r7, #12] 80110ec: 60b9 str r1, [r7, #8] 80110ee: 607a str r2, [r7, #4] 80110f0: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 80110f2: 68fb ldr r3, [r7, #12] 80110f4: 689b ldr r3, [r3, #8] 80110f6: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80110f8: 697b ldr r3, [r7, #20] 80110fa: f423 437f bic.w r3, r3, #65280 @ 0xff00 80110fe: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8011100: 683b ldr r3, [r7, #0] 8011102: 021a lsls r2, r3, #8 8011104: 687b ldr r3, [r7, #4] 8011106: 431a orrs r2, r3 8011108: 68bb ldr r3, [r7, #8] 801110a: 4313 orrs r3, r2 801110c: 697a ldr r2, [r7, #20] 801110e: 4313 orrs r3, r2 8011110: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8011112: 68fb ldr r3, [r7, #12] 8011114: 697a ldr r2, [r7, #20] 8011116: 609a str r2, [r3, #8] } 8011118: bf00 nop 801111a: 371c adds r7, #28 801111c: 46bd mov sp, r7 801111e: f85d 7b04 ldr.w r7, [sp], #4 8011122: 4770 bx lr 08011124 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8011124: b480 push {r7} 8011126: b087 sub sp, #28 8011128: af00 add r7, sp, #0 801112a: 60f8 str r0, [r7, #12] 801112c: 60b9 str r1, [r7, #8] 801112e: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 8011130: 68bb ldr r3, [r7, #8] 8011132: f003 031f and.w r3, r3, #31 8011136: 2201 movs r2, #1 8011138: fa02 f303 lsl.w r3, r2, r3 801113c: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 801113e: 68fb ldr r3, [r7, #12] 8011140: 6a1a ldr r2, [r3, #32] 8011142: 697b ldr r3, [r7, #20] 8011144: 43db mvns r3, r3 8011146: 401a ands r2, r3 8011148: 68fb ldr r3, [r7, #12] 801114a: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 801114c: 68fb ldr r3, [r7, #12] 801114e: 6a1a ldr r2, [r3, #32] 8011150: 68bb ldr r3, [r7, #8] 8011152: f003 031f and.w r3, r3, #31 8011156: 6879 ldr r1, [r7, #4] 8011158: fa01 f303 lsl.w r3, r1, r3 801115c: 431a orrs r2, r3 801115e: 68fb ldr r3, [r7, #12] 8011160: 621a str r2, [r3, #32] } 8011162: bf00 nop 8011164: 371c adds r7, #28 8011166: 46bd mov sp, r7 8011168: f85d 7b04 ldr.w r7, [sp], #4 801116c: 4770 bx lr ... 08011170 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8011170: b480 push {r7} 8011172: b085 sub sp, #20 8011174: af00 add r7, sp, #0 8011176: 6078 str r0, [r7, #4] 8011178: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 801117a: 687b ldr r3, [r7, #4] 801117c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8011180: 2b01 cmp r3, #1 8011182: d101 bne.n 8011188 8011184: 2302 movs r3, #2 8011186: e06d b.n 8011264 8011188: 687b ldr r3, [r7, #4] 801118a: 2201 movs r2, #1 801118c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8011190: 687b ldr r3, [r7, #4] 8011192: 2202 movs r2, #2 8011194: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8011198: 687b ldr r3, [r7, #4] 801119a: 681b ldr r3, [r3, #0] 801119c: 685b ldr r3, [r3, #4] 801119e: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80111a0: 687b ldr r3, [r7, #4] 80111a2: 681b ldr r3, [r3, #0] 80111a4: 689b ldr r3, [r3, #8] 80111a6: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80111a8: 687b ldr r3, [r7, #4] 80111aa: 681b ldr r3, [r3, #0] 80111ac: 4a30 ldr r2, [pc, #192] @ (8011270 ) 80111ae: 4293 cmp r3, r2 80111b0: d004 beq.n 80111bc 80111b2: 687b ldr r3, [r7, #4] 80111b4: 681b ldr r3, [r3, #0] 80111b6: 4a2f ldr r2, [pc, #188] @ (8011274 ) 80111b8: 4293 cmp r3, r2 80111ba: d108 bne.n 80111ce { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 80111bc: 68fb ldr r3, [r7, #12] 80111be: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 80111c2: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 80111c4: 683b ldr r3, [r7, #0] 80111c6: 685b ldr r3, [r3, #4] 80111c8: 68fa ldr r2, [r7, #12] 80111ca: 4313 orrs r3, r2 80111cc: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 80111ce: 68fb ldr r3, [r7, #12] 80111d0: f023 0370 bic.w r3, r3, #112 @ 0x70 80111d4: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 80111d6: 683b ldr r3, [r7, #0] 80111d8: 681b ldr r3, [r3, #0] 80111da: 68fa ldr r2, [r7, #12] 80111dc: 4313 orrs r3, r2 80111de: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 80111e0: 687b ldr r3, [r7, #4] 80111e2: 681b ldr r3, [r3, #0] 80111e4: 68fa ldr r2, [r7, #12] 80111e6: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80111e8: 687b ldr r3, [r7, #4] 80111ea: 681b ldr r3, [r3, #0] 80111ec: 4a20 ldr r2, [pc, #128] @ (8011270 ) 80111ee: 4293 cmp r3, r2 80111f0: d022 beq.n 8011238 80111f2: 687b ldr r3, [r7, #4] 80111f4: 681b ldr r3, [r3, #0] 80111f6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80111fa: d01d beq.n 8011238 80111fc: 687b ldr r3, [r7, #4] 80111fe: 681b ldr r3, [r3, #0] 8011200: 4a1d ldr r2, [pc, #116] @ (8011278 ) 8011202: 4293 cmp r3, r2 8011204: d018 beq.n 8011238 8011206: 687b ldr r3, [r7, #4] 8011208: 681b ldr r3, [r3, #0] 801120a: 4a1c ldr r2, [pc, #112] @ (801127c ) 801120c: 4293 cmp r3, r2 801120e: d013 beq.n 8011238 8011210: 687b ldr r3, [r7, #4] 8011212: 681b ldr r3, [r3, #0] 8011214: 4a1a ldr r2, [pc, #104] @ (8011280 ) 8011216: 4293 cmp r3, r2 8011218: d00e beq.n 8011238 801121a: 687b ldr r3, [r7, #4] 801121c: 681b ldr r3, [r3, #0] 801121e: 4a15 ldr r2, [pc, #84] @ (8011274 ) 8011220: 4293 cmp r3, r2 8011222: d009 beq.n 8011238 8011224: 687b ldr r3, [r7, #4] 8011226: 681b ldr r3, [r3, #0] 8011228: 4a16 ldr r2, [pc, #88] @ (8011284 ) 801122a: 4293 cmp r3, r2 801122c: d004 beq.n 8011238 801122e: 687b ldr r3, [r7, #4] 8011230: 681b ldr r3, [r3, #0] 8011232: 4a15 ldr r2, [pc, #84] @ (8011288 ) 8011234: 4293 cmp r3, r2 8011236: d10c bne.n 8011252 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8011238: 68bb ldr r3, [r7, #8] 801123a: f023 0380 bic.w r3, r3, #128 @ 0x80 801123e: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8011240: 683b ldr r3, [r7, #0] 8011242: 689b ldr r3, [r3, #8] 8011244: 68ba ldr r2, [r7, #8] 8011246: 4313 orrs r3, r2 8011248: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 801124a: 687b ldr r3, [r7, #4] 801124c: 681b ldr r3, [r3, #0] 801124e: 68ba ldr r2, [r7, #8] 8011250: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8011252: 687b ldr r3, [r7, #4] 8011254: 2201 movs r2, #1 8011256: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 801125a: 687b ldr r3, [r7, #4] 801125c: 2200 movs r2, #0 801125e: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8011262: 2300 movs r3, #0 } 8011264: 4618 mov r0, r3 8011266: 3714 adds r7, #20 8011268: 46bd mov sp, r7 801126a: f85d 7b04 ldr.w r7, [sp], #4 801126e: 4770 bx lr 8011270: 40010000 .word 0x40010000 8011274: 40010400 .word 0x40010400 8011278: 40000400 .word 0x40000400 801127c: 40000800 .word 0x40000800 8011280: 40000c00 .word 0x40000c00 8011284: 40001800 .word 0x40001800 8011288: 40014000 .word 0x40014000 0801128c : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 801128c: b480 push {r7} 801128e: b085 sub sp, #20 8011290: af00 add r7, sp, #0 8011292: 6078 str r0, [r7, #4] 8011294: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 8011296: 2300 movs r3, #0 8011298: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); #endif /* TIM_BDTR_BKBID */ /* Check input state */ __HAL_LOCK(htim); 801129a: 687b ldr r3, [r7, #4] 801129c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 80112a0: 2b01 cmp r3, #1 80112a2: d101 bne.n 80112a8 80112a4: 2302 movs r3, #2 80112a6: e065 b.n 8011374 80112a8: 687b ldr r3, [r7, #4] 80112aa: 2201 movs r2, #1 80112ac: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 80112b0: 68fb ldr r3, [r7, #12] 80112b2: f023 02ff bic.w r2, r3, #255 @ 0xff 80112b6: 683b ldr r3, [r7, #0] 80112b8: 68db ldr r3, [r3, #12] 80112ba: 4313 orrs r3, r2 80112bc: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 80112be: 68fb ldr r3, [r7, #12] 80112c0: f423 7240 bic.w r2, r3, #768 @ 0x300 80112c4: 683b ldr r3, [r7, #0] 80112c6: 689b ldr r3, [r3, #8] 80112c8: 4313 orrs r3, r2 80112ca: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 80112cc: 68fb ldr r3, [r7, #12] 80112ce: f423 6280 bic.w r2, r3, #1024 @ 0x400 80112d2: 683b ldr r3, [r7, #0] 80112d4: 685b ldr r3, [r3, #4] 80112d6: 4313 orrs r3, r2 80112d8: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 80112da: 68fb ldr r3, [r7, #12] 80112dc: f423 6200 bic.w r2, r3, #2048 @ 0x800 80112e0: 683b ldr r3, [r7, #0] 80112e2: 681b ldr r3, [r3, #0] 80112e4: 4313 orrs r3, r2 80112e6: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 80112e8: 68fb ldr r3, [r7, #12] 80112ea: f423 5280 bic.w r2, r3, #4096 @ 0x1000 80112ee: 683b ldr r3, [r7, #0] 80112f0: 691b ldr r3, [r3, #16] 80112f2: 4313 orrs r3, r2 80112f4: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 80112f6: 68fb ldr r3, [r7, #12] 80112f8: f423 5200 bic.w r2, r3, #8192 @ 0x2000 80112fc: 683b ldr r3, [r7, #0] 80112fe: 695b ldr r3, [r3, #20] 8011300: 4313 orrs r3, r2 8011302: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8011304: 68fb ldr r3, [r7, #12] 8011306: f423 4280 bic.w r2, r3, #16384 @ 0x4000 801130a: 683b ldr r3, [r7, #0] 801130c: 6a9b ldr r3, [r3, #40] @ 0x28 801130e: 4313 orrs r3, r2 8011310: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 8011312: 68fb ldr r3, [r7, #12] 8011314: f423 2270 bic.w r2, r3, #983040 @ 0xf0000 8011318: 683b ldr r3, [r7, #0] 801131a: 699b ldr r3, [r3, #24] 801131c: 041b lsls r3, r3, #16 801131e: 4313 orrs r3, r2 8011320: 60fb str r3, [r7, #12] #if defined(TIM_BDTR_BKBID) MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); #endif /* TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 8011322: 687b ldr r3, [r7, #4] 8011324: 681b ldr r3, [r3, #0] 8011326: 4a16 ldr r2, [pc, #88] @ (8011380 ) 8011328: 4293 cmp r3, r2 801132a: d004 beq.n 8011336 801132c: 687b ldr r3, [r7, #4] 801132e: 681b ldr r3, [r3, #0] 8011330: 4a14 ldr r2, [pc, #80] @ (8011384 ) 8011332: 4293 cmp r3, r2 8011334: d115 bne.n 8011362 #if defined(TIM_BDTR_BKBID) assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); #endif /* TIM_BDTR_BKBID */ /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 8011336: 68fb ldr r3, [r7, #12] 8011338: f423 0270 bic.w r2, r3, #15728640 @ 0xf00000 801133c: 683b ldr r3, [r7, #0] 801133e: 6a5b ldr r3, [r3, #36] @ 0x24 8011340: 051b lsls r3, r3, #20 8011342: 4313 orrs r3, r2 8011344: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 8011346: 68fb ldr r3, [r7, #12] 8011348: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000 801134c: 683b ldr r3, [r7, #0] 801134e: 69db ldr r3, [r3, #28] 8011350: 4313 orrs r3, r2 8011352: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 8011354: 68fb ldr r3, [r7, #12] 8011356: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000 801135a: 683b ldr r3, [r7, #0] 801135c: 6a1b ldr r3, [r3, #32] 801135e: 4313 orrs r3, r2 8011360: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); #endif /* TIM_BDTR_BKBID */ } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 8011362: 687b ldr r3, [r7, #4] 8011364: 681b ldr r3, [r3, #0] 8011366: 68fa ldr r2, [r7, #12] 8011368: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 801136a: 687b ldr r3, [r7, #4] 801136c: 2200 movs r2, #0 801136e: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8011372: 2300 movs r3, #0 } 8011374: 4618 mov r0, r3 8011376: 3714 adds r7, #20 8011378: 46bd mov sp, r7 801137a: f85d 7b04 ldr.w r7, [sp], #4 801137e: 4770 bx lr 8011380: 40010000 .word 0x40010000 8011384: 40010400 .word 0x40010400 08011388 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8011388: b480 push {r7} 801138a: b083 sub sp, #12 801138c: af00 add r7, sp, #0 801138e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8011390: bf00 nop 8011392: 370c adds r7, #12 8011394: 46bd mov sp, r7 8011396: f85d 7b04 ldr.w r7, [sp], #4 801139a: 4770 bx lr 0801139c : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 801139c: b480 push {r7} 801139e: b083 sub sp, #12 80113a0: af00 add r7, sp, #0 80113a2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 80113a4: bf00 nop 80113a6: 370c adds r7, #12 80113a8: 46bd mov sp, r7 80113aa: f85d 7b04 ldr.w r7, [sp], #4 80113ae: 4770 bx lr 080113b0 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 80113b0: b480 push {r7} 80113b2: b083 sub sp, #12 80113b4: af00 add r7, sp, #0 80113b6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 80113b8: bf00 nop 80113ba: 370c adds r7, #12 80113bc: 46bd mov sp, r7 80113be: f85d 7b04 ldr.w r7, [sp], #4 80113c2: 4770 bx lr 080113c4 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 80113c4: b580 push {r7, lr} 80113c6: b082 sub sp, #8 80113c8: af00 add r7, sp, #0 80113ca: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 80113cc: 687b ldr r3, [r7, #4] 80113ce: 2b00 cmp r3, #0 80113d0: d101 bne.n 80113d6 { return HAL_ERROR; 80113d2: 2301 movs r3, #1 80113d4: e042 b.n 801145c { /* Check the parameters */ assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); } if (huart->gState == HAL_UART_STATE_RESET) 80113d6: 687b ldr r3, [r7, #4] 80113d8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80113dc: 2b00 cmp r3, #0 80113de: d106 bne.n 80113ee { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80113e0: 687b ldr r3, [r7, #4] 80113e2: 2200 movs r2, #0 80113e4: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 80113e8: 6878 ldr r0, [r7, #4] 80113ea: f7f3 f881 bl 80044f0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80113ee: 687b ldr r3, [r7, #4] 80113f0: 2224 movs r2, #36 @ 0x24 80113f2: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UART_DISABLE(huart); 80113f6: 687b ldr r3, [r7, #4] 80113f8: 681b ldr r3, [r3, #0] 80113fa: 681a ldr r2, [r3, #0] 80113fc: 687b ldr r3, [r7, #4] 80113fe: 681b ldr r3, [r3, #0] 8011400: f022 0201 bic.w r2, r2, #1 8011404: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8011406: 687b ldr r3, [r7, #4] 8011408: 6a9b ldr r3, [r3, #40] @ 0x28 801140a: 2b00 cmp r3, #0 801140c: d002 beq.n 8011414 { UART_AdvFeatureConfig(huart); 801140e: 6878 ldr r0, [r7, #4] 8011410: f001 f9e8 bl 80127e4 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 8011414: 6878 ldr r0, [r7, #4] 8011416: f000 fc7d bl 8011d14 801141a: 4603 mov r3, r0 801141c: 2b01 cmp r3, #1 801141e: d101 bne.n 8011424 { return HAL_ERROR; 8011420: 2301 movs r3, #1 8011422: e01b b.n 801145c } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8011424: 687b ldr r3, [r7, #4] 8011426: 681b ldr r3, [r3, #0] 8011428: 685a ldr r2, [r3, #4] 801142a: 687b ldr r3, [r7, #4] 801142c: 681b ldr r3, [r3, #0] 801142e: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8011432: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8011434: 687b ldr r3, [r7, #4] 8011436: 681b ldr r3, [r3, #0] 8011438: 689a ldr r2, [r3, #8] 801143a: 687b ldr r3, [r7, #4] 801143c: 681b ldr r3, [r3, #0] 801143e: f022 022a bic.w r2, r2, #42 @ 0x2a 8011442: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 8011444: 687b ldr r3, [r7, #4] 8011446: 681b ldr r3, [r3, #0] 8011448: 681a ldr r2, [r3, #0] 801144a: 687b ldr r3, [r7, #4] 801144c: 681b ldr r3, [r3, #0] 801144e: f042 0201 orr.w r2, r2, #1 8011452: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 8011454: 6878 ldr r0, [r7, #4] 8011456: f001 fa67 bl 8012928 801145a: 4603 mov r3, r0 } 801145c: 4618 mov r0, r3 801145e: 3708 adds r7, #8 8011460: 46bd mov sp, r7 8011462: bd80 pop {r7, pc} 08011464 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { 8011464: b480 push {r7} 8011466: b091 sub sp, #68 @ 0x44 8011468: af00 add r7, sp, #0 801146a: 60f8 str r0, [r7, #12] 801146c: 60b9 str r1, [r7, #8] 801146e: 4613 mov r3, r2 8011470: 80fb strh r3, [r7, #6] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8011472: 68fb ldr r3, [r7, #12] 8011474: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8011478: 2b20 cmp r3, #32 801147a: d178 bne.n 801156e { if ((pData == NULL) || (Size == 0U)) 801147c: 68bb ldr r3, [r7, #8] 801147e: 2b00 cmp r3, #0 8011480: d002 beq.n 8011488 8011482: 88fb ldrh r3, [r7, #6] 8011484: 2b00 cmp r3, #0 8011486: d101 bne.n 801148c { return HAL_ERROR; 8011488: 2301 movs r3, #1 801148a: e071 b.n 8011570 } huart->pTxBuffPtr = pData; 801148c: 68fb ldr r3, [r7, #12] 801148e: 68ba ldr r2, [r7, #8] 8011490: 651a str r2, [r3, #80] @ 0x50 huart->TxXferSize = Size; 8011492: 68fb ldr r3, [r7, #12] 8011494: 88fa ldrh r2, [r7, #6] 8011496: f8a3 2054 strh.w r2, [r3, #84] @ 0x54 huart->TxXferCount = Size; 801149a: 68fb ldr r3, [r7, #12] 801149c: 88fa ldrh r2, [r7, #6] 801149e: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 huart->TxISR = NULL; 80114a2: 68fb ldr r3, [r7, #12] 80114a4: 2200 movs r2, #0 80114a6: 679a str r2, [r3, #120] @ 0x78 huart->ErrorCode = HAL_UART_ERROR_NONE; 80114a8: 68fb ldr r3, [r7, #12] 80114aa: 2200 movs r2, #0 80114ac: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->gState = HAL_UART_STATE_BUSY_TX; 80114b0: 68fb ldr r3, [r7, #12] 80114b2: 2221 movs r2, #33 @ 0x21 80114b4: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Configure Tx interrupt processing */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) 80114b8: 68fb ldr r3, [r7, #12] 80114ba: 6e5b ldr r3, [r3, #100] @ 0x64 80114bc: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80114c0: d12a bne.n 8011518 { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 80114c2: 68fb ldr r3, [r7, #12] 80114c4: 689b ldr r3, [r3, #8] 80114c6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80114ca: d107 bne.n 80114dc 80114cc: 68fb ldr r3, [r7, #12] 80114ce: 691b ldr r3, [r3, #16] 80114d0: 2b00 cmp r3, #0 80114d2: d103 bne.n 80114dc { huart->TxISR = UART_TxISR_16BIT_FIFOEN; 80114d4: 68fb ldr r3, [r7, #12] 80114d6: 4a29 ldr r2, [pc, #164] @ (801157c ) 80114d8: 679a str r2, [r3, #120] @ 0x78 80114da: e002 b.n 80114e2 } else { huart->TxISR = UART_TxISR_8BIT_FIFOEN; 80114dc: 68fb ldr r3, [r7, #12] 80114de: 4a28 ldr r2, [pc, #160] @ (8011580 ) 80114e0: 679a str r2, [r3, #120] @ 0x78 } /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 80114e2: 68fb ldr r3, [r7, #12] 80114e4: 681b ldr r3, [r3, #0] 80114e6: 3308 adds r3, #8 80114e8: 62bb str r3, [r7, #40] @ 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80114ea: 6abb ldr r3, [r7, #40] @ 0x28 80114ec: e853 3f00 ldrex r3, [r3] 80114f0: 627b str r3, [r7, #36] @ 0x24 return(result); 80114f2: 6a7b ldr r3, [r7, #36] @ 0x24 80114f4: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 80114f8: 63bb str r3, [r7, #56] @ 0x38 80114fa: 68fb ldr r3, [r7, #12] 80114fc: 681b ldr r3, [r3, #0] 80114fe: 3308 adds r3, #8 8011500: 6bba ldr r2, [r7, #56] @ 0x38 8011502: 637a str r2, [r7, #52] @ 0x34 8011504: 633b str r3, [r7, #48] @ 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011506: 6b39 ldr r1, [r7, #48] @ 0x30 8011508: 6b7a ldr r2, [r7, #52] @ 0x34 801150a: e841 2300 strex r3, r2, [r1] 801150e: 62fb str r3, [r7, #44] @ 0x2c return(result); 8011510: 6afb ldr r3, [r7, #44] @ 0x2c 8011512: 2b00 cmp r3, #0 8011514: d1e5 bne.n 80114e2 8011516: e028 b.n 801156a } else { /* Set the Tx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8011518: 68fb ldr r3, [r7, #12] 801151a: 689b ldr r3, [r3, #8] 801151c: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8011520: d107 bne.n 8011532 8011522: 68fb ldr r3, [r7, #12] 8011524: 691b ldr r3, [r3, #16] 8011526: 2b00 cmp r3, #0 8011528: d103 bne.n 8011532 { huart->TxISR = UART_TxISR_16BIT; 801152a: 68fb ldr r3, [r7, #12] 801152c: 4a15 ldr r2, [pc, #84] @ (8011584 ) 801152e: 679a str r2, [r3, #120] @ 0x78 8011530: e002 b.n 8011538 } else { huart->TxISR = UART_TxISR_8BIT; 8011532: 68fb ldr r3, [r7, #12] 8011534: 4a14 ldr r2, [pc, #80] @ (8011588 ) 8011536: 679a str r2, [r3, #120] @ 0x78 } /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8011538: 68fb ldr r3, [r7, #12] 801153a: 681b ldr r3, [r3, #0] 801153c: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801153e: 697b ldr r3, [r7, #20] 8011540: e853 3f00 ldrex r3, [r3] 8011544: 613b str r3, [r7, #16] return(result); 8011546: 693b ldr r3, [r7, #16] 8011548: f043 0380 orr.w r3, r3, #128 @ 0x80 801154c: 63fb str r3, [r7, #60] @ 0x3c 801154e: 68fb ldr r3, [r7, #12] 8011550: 681b ldr r3, [r3, #0] 8011552: 461a mov r2, r3 8011554: 6bfb ldr r3, [r7, #60] @ 0x3c 8011556: 623b str r3, [r7, #32] 8011558: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801155a: 69f9 ldr r1, [r7, #28] 801155c: 6a3a ldr r2, [r7, #32] 801155e: e841 2300 strex r3, r2, [r1] 8011562: 61bb str r3, [r7, #24] return(result); 8011564: 69bb ldr r3, [r7, #24] 8011566: 2b00 cmp r3, #0 8011568: d1e6 bne.n 8011538 } return HAL_OK; 801156a: 2300 movs r3, #0 801156c: e000 b.n 8011570 } else { return HAL_BUSY; 801156e: 2302 movs r3, #2 } } 8011570: 4618 mov r0, r3 8011572: 3744 adds r7, #68 @ 0x44 8011574: 46bd mov sp, r7 8011576: f85d 7b04 ldr.w r7, [sp], #4 801157a: 4770 bx lr 801157c: 080130ef .word 0x080130ef 8011580: 0801300f .word 0x0801300f 8011584: 08012f4d .word 0x08012f4d 8011588: 08012e95 .word 0x08012e95 0801158c : * @brief Handle UART interrupt request. * @param huart UART handle. * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { 801158c: b580 push {r7, lr} 801158e: b0ba sub sp, #232 @ 0xe8 8011590: af00 add r7, sp, #0 8011592: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(huart->Instance->ISR); 8011594: 687b ldr r3, [r7, #4] 8011596: 681b ldr r3, [r3, #0] 8011598: 69db ldr r3, [r3, #28] 801159a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 801159e: 687b ldr r3, [r7, #4] 80115a0: 681b ldr r3, [r3, #0] 80115a2: 681b ldr r3, [r3, #0] 80115a4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80115a8: 687b ldr r3, [r7, #4] 80115aa: 681b ldr r3, [r3, #0] 80115ac: 689b ldr r3, [r3, #8] 80115ae: f8c7 30dc str.w r3, [r7, #220] @ 0xdc uint32_t errorflags; uint32_t errorcode; /* If no error occurs */ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); 80115b2: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4 80115b6: f640 030f movw r3, #2063 @ 0x80f 80115ba: 4013 ands r3, r2 80115bc: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 if (errorflags == 0U) 80115c0: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 80115c4: 2b00 cmp r3, #0 80115c6: d11b bne.n 8011600 { /* UART in mode Receiver ---------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 80115c8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80115cc: f003 0320 and.w r3, r3, #32 80115d0: 2b00 cmp r3, #0 80115d2: d015 beq.n 8011600 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 80115d4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80115d8: f003 0320 and.w r3, r3, #32 80115dc: 2b00 cmp r3, #0 80115de: d105 bne.n 80115ec || ((cr3its & USART_CR3_RXFTIE) != 0U))) 80115e0: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 80115e4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80115e8: 2b00 cmp r3, #0 80115ea: d009 beq.n 8011600 { if (huart->RxISR != NULL) 80115ec: 687b ldr r3, [r7, #4] 80115ee: 6f5b ldr r3, [r3, #116] @ 0x74 80115f0: 2b00 cmp r3, #0 80115f2: f000 8377 beq.w 8011ce4 { huart->RxISR(huart); 80115f6: 687b ldr r3, [r7, #4] 80115f8: 6f5b ldr r3, [r3, #116] @ 0x74 80115fa: 6878 ldr r0, [r7, #4] 80115fc: 4798 blx r3 } return; 80115fe: e371 b.n 8011ce4 } } /* If some errors occur */ if ((errorflags != 0U) 8011600: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8 8011604: 2b00 cmp r3, #0 8011606: f000 8123 beq.w 8011850 && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) 801160a: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 801160e: 4b8d ldr r3, [pc, #564] @ (8011844 ) 8011610: 4013 ands r3, r2 8011612: 2b00 cmp r3, #0 8011614: d106 bne.n 8011624 || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) 8011616: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0 801161a: 4b8b ldr r3, [pc, #556] @ (8011848 ) 801161c: 4013 ands r3, r2 801161e: 2b00 cmp r3, #0 8011620: f000 8116 beq.w 8011850 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 8011624: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011628: f003 0301 and.w r3, r3, #1 801162c: 2b00 cmp r3, #0 801162e: d011 beq.n 8011654 8011630: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011634: f403 7380 and.w r3, r3, #256 @ 0x100 8011638: 2b00 cmp r3, #0 801163a: d00b beq.n 8011654 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 801163c: 687b ldr r3, [r7, #4] 801163e: 681b ldr r3, [r3, #0] 8011640: 2201 movs r2, #1 8011642: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 8011644: 687b ldr r3, [r7, #4] 8011646: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 801164a: f043 0201 orr.w r2, r3, #1 801164e: 687b ldr r3, [r7, #4] 8011650: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8011654: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011658: f003 0302 and.w r3, r3, #2 801165c: 2b00 cmp r3, #0 801165e: d011 beq.n 8011684 8011660: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011664: f003 0301 and.w r3, r3, #1 8011668: 2b00 cmp r3, #0 801166a: d00b beq.n 8011684 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 801166c: 687b ldr r3, [r7, #4] 801166e: 681b ldr r3, [r3, #0] 8011670: 2202 movs r2, #2 8011672: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 8011674: 687b ldr r3, [r7, #4] 8011676: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 801167a: f043 0204 orr.w r2, r3, #4 801167e: 687b ldr r3, [r7, #4] 8011680: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 8011684: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011688: f003 0304 and.w r3, r3, #4 801168c: 2b00 cmp r3, #0 801168e: d011 beq.n 80116b4 8011690: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011694: f003 0301 and.w r3, r3, #1 8011698: 2b00 cmp r3, #0 801169a: d00b beq.n 80116b4 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 801169c: 687b ldr r3, [r7, #4] 801169e: 681b ldr r3, [r3, #0] 80116a0: 2204 movs r2, #4 80116a2: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80116a4: 687b ldr r3, [r7, #4] 80116a6: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80116aa: f043 0202 orr.w r2, r3, #2 80116ae: 687b ldr r3, [r7, #4] 80116b0: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Over-Run interrupt occurred -----------------------------------------*/ if (((isrflags & USART_ISR_ORE) != 0U) 80116b4: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80116b8: f003 0308 and.w r3, r3, #8 80116bc: 2b00 cmp r3, #0 80116be: d017 beq.n 80116f0 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80116c0: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 80116c4: f003 0320 and.w r3, r3, #32 80116c8: 2b00 cmp r3, #0 80116ca: d105 bne.n 80116d8 ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) 80116cc: f8d7 20dc ldr.w r2, [r7, #220] @ 0xdc 80116d0: 4b5c ldr r3, [pc, #368] @ (8011844 ) 80116d2: 4013 ands r3, r2 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || 80116d4: 2b00 cmp r3, #0 80116d6: d00b beq.n 80116f0 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 80116d8: 687b ldr r3, [r7, #4] 80116da: 681b ldr r3, [r3, #0] 80116dc: 2208 movs r2, #8 80116de: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_ORE; 80116e0: 687b ldr r3, [r7, #4] 80116e2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80116e6: f043 0208 orr.w r2, r3, #8 80116ea: 687b ldr r3, [r7, #4] 80116ec: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART Receiver Timeout interrupt occurred ---------------------------------*/ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) 80116f0: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 80116f4: f403 6300 and.w r3, r3, #2048 @ 0x800 80116f8: 2b00 cmp r3, #0 80116fa: d012 beq.n 8011722 80116fc: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011700: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8011704: 2b00 cmp r3, #0 8011706: d00c beq.n 8011722 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8011708: 687b ldr r3, [r7, #4] 801170a: 681b ldr r3, [r3, #0] 801170c: f44f 6200 mov.w r2, #2048 @ 0x800 8011710: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_RTO; 8011712: 687b ldr r3, [r7, #4] 8011714: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011718: f043 0220 orr.w r2, r3, #32 801171c: 687b ldr r3, [r7, #4] 801171e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8011722: 687b ldr r3, [r7, #4] 8011724: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011728: 2b00 cmp r3, #0 801172a: f000 82dd beq.w 8011ce8 { /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) 801172e: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011732: f003 0320 and.w r3, r3, #32 8011736: 2b00 cmp r3, #0 8011738: d013 beq.n 8011762 && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) 801173a: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801173e: f003 0320 and.w r3, r3, #32 8011742: 2b00 cmp r3, #0 8011744: d105 bne.n 8011752 || ((cr3its & USART_CR3_RXFTIE) != 0U))) 8011746: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 801174a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 801174e: 2b00 cmp r3, #0 8011750: d007 beq.n 8011762 { if (huart->RxISR != NULL) 8011752: 687b ldr r3, [r7, #4] 8011754: 6f5b ldr r3, [r3, #116] @ 0x74 8011756: 2b00 cmp r3, #0 8011758: d003 beq.n 8011762 { huart->RxISR(huart); 801175a: 687b ldr r3, [r7, #4] 801175c: 6f5b ldr r3, [r3, #116] @ 0x74 801175e: 6878 ldr r0, [r7, #4] 8011760: 4798 blx r3 /* If Error is to be considered as blocking : - Receiver Timeout error in Reception - Overrun error in Reception - any error occurs in DMA mode reception */ errorcode = huart->ErrorCode; 8011762: 687b ldr r3, [r7, #4] 8011764: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8011768: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 801176c: 687b ldr r3, [r7, #4] 801176e: 681b ldr r3, [r3, #0] 8011770: 689b ldr r3, [r3, #8] 8011772: f003 0340 and.w r3, r3, #64 @ 0x40 8011776: 2b40 cmp r3, #64 @ 0x40 8011778: d005 beq.n 8011786 ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) 801177a: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4 801177e: f003 0328 and.w r3, r3, #40 @ 0x28 if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || 8011782: 2b00 cmp r3, #0 8011784: d054 beq.n 8011830 { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ UART_EndRxTransfer(huart); 8011786: 6878 ldr r0, [r7, #4] 8011788: f001 fb08 bl 8012d9c /* Abort the UART DMA Rx channel if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801178c: 687b ldr r3, [r7, #4] 801178e: 681b ldr r3, [r3, #0] 8011790: 689b ldr r3, [r3, #8] 8011792: f003 0340 and.w r3, r3, #64 @ 0x40 8011796: 2b40 cmp r3, #64 @ 0x40 8011798: d146 bne.n 8011828 { /* Disable the UART DMA Rx request if enabled */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 801179a: 687b ldr r3, [r7, #4] 801179c: 681b ldr r3, [r3, #0] 801179e: 3308 adds r3, #8 80117a0: f8c7 309c str.w r3, [r7, #156] @ 0x9c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80117a4: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 80117a8: e853 3f00 ldrex r3, [r3] 80117ac: f8c7 3098 str.w r3, [r7, #152] @ 0x98 return(result); 80117b0: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 80117b4: f023 0340 bic.w r3, r3, #64 @ 0x40 80117b8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 80117bc: 687b ldr r3, [r7, #4] 80117be: 681b ldr r3, [r3, #0] 80117c0: 3308 adds r3, #8 80117c2: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0 80117c6: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8 80117ca: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80117ce: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4 80117d2: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8 80117d6: e841 2300 strex r3, r2, [r1] 80117da: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 return(result); 80117de: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80117e2: 2b00 cmp r3, #0 80117e4: d1d9 bne.n 801179a /* Abort the UART DMA Rx channel */ if (huart->hdmarx != NULL) 80117e6: 687b ldr r3, [r7, #4] 80117e8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117ec: 2b00 cmp r3, #0 80117ee: d017 beq.n 8011820 { /* Set the UART DMA Abort callback : will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; 80117f0: 687b ldr r3, [r7, #4] 80117f2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80117f6: 4a15 ldr r2, [pc, #84] @ (801184c ) 80117f8: 651a str r2, [r3, #80] @ 0x50 /* Abort DMA RX */ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) 80117fa: 687b ldr r3, [r7, #4] 80117fc: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011800: 4618 mov r0, r3 8011802: f7f7 ff8f bl 8009724 8011806: 4603 mov r3, r0 8011808: 2b00 cmp r3, #0 801180a: d019 beq.n 8011840 { /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ huart->hdmarx->XferAbortCallback(huart->hdmarx); 801180c: 687b ldr r3, [r7, #4] 801180e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011812: 6d1b ldr r3, [r3, #80] @ 0x50 8011814: 687a ldr r2, [r7, #4] 8011816: f8d2 2080 ldr.w r2, [r2, #128] @ 0x80 801181a: 4610 mov r0, r2 801181c: 4798 blx r3 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801181e: e00f b.n 8011840 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011820: 6878 ldr r0, [r7, #4] 8011822: f000 fa6d bl 8011d00 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011826: e00b b.n 8011840 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011828: 6878 ldr r0, [r7, #4] 801182a: f000 fa69 bl 8011d00 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801182e: e007 b.n 8011840 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8011830: 6878 ldr r0, [r7, #4] 8011832: f000 fa65 bl 8011d00 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8011836: 687b ldr r3, [r7, #4] 8011838: 2200 movs r2, #0 801183a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } return; 801183e: e253 b.n 8011ce8 if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 8011840: bf00 nop return; 8011842: e251 b.n 8011ce8 8011844: 10000001 .word 0x10000001 8011848: 04000120 .word 0x04000120 801184c: 08012e69 .word 0x08012e69 } /* End if some error occurs */ /* Check current reception Mode : If Reception till IDLE event has been selected : */ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8011850: 687b ldr r3, [r7, #4] 8011852: 6edb ldr r3, [r3, #108] @ 0x6c 8011854: 2b01 cmp r3, #1 8011856: f040 81e7 bne.w 8011c28 && ((isrflags & USART_ISR_IDLE) != 0U) 801185a: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 801185e: f003 0310 and.w r3, r3, #16 8011862: 2b00 cmp r3, #0 8011864: f000 81e0 beq.w 8011c28 && ((cr1its & USART_ISR_IDLE) != 0U)) 8011868: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 801186c: f003 0310 and.w r3, r3, #16 8011870: 2b00 cmp r3, #0 8011872: f000 81d9 beq.w 8011c28 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8011876: 687b ldr r3, [r7, #4] 8011878: 681b ldr r3, [r3, #0] 801187a: 2210 movs r2, #16 801187c: 621a str r2, [r3, #32] /* Check if DMA mode is enabled in UART */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) 801187e: 687b ldr r3, [r7, #4] 8011880: 681b ldr r3, [r3, #0] 8011882: 689b ldr r3, [r3, #8] 8011884: f003 0340 and.w r3, r3, #64 @ 0x40 8011888: 2b40 cmp r3, #64 @ 0x40 801188a: f040 8151 bne.w 8011b30 { /* DMA mode enabled */ /* Check received length : If all expected data are received, do nothing, (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); 801188e: 687b ldr r3, [r7, #4] 8011890: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011894: 681b ldr r3, [r3, #0] 8011896: 4a96 ldr r2, [pc, #600] @ (8011af0 ) 8011898: 4293 cmp r3, r2 801189a: d068 beq.n 801196e 801189c: 687b ldr r3, [r7, #4] 801189e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118a2: 681b ldr r3, [r3, #0] 80118a4: 4a93 ldr r2, [pc, #588] @ (8011af4 ) 80118a6: 4293 cmp r3, r2 80118a8: d061 beq.n 801196e 80118aa: 687b ldr r3, [r7, #4] 80118ac: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118b0: 681b ldr r3, [r3, #0] 80118b2: 4a91 ldr r2, [pc, #580] @ (8011af8 ) 80118b4: 4293 cmp r3, r2 80118b6: d05a beq.n 801196e 80118b8: 687b ldr r3, [r7, #4] 80118ba: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118be: 681b ldr r3, [r3, #0] 80118c0: 4a8e ldr r2, [pc, #568] @ (8011afc ) 80118c2: 4293 cmp r3, r2 80118c4: d053 beq.n 801196e 80118c6: 687b ldr r3, [r7, #4] 80118c8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118cc: 681b ldr r3, [r3, #0] 80118ce: 4a8c ldr r2, [pc, #560] @ (8011b00 ) 80118d0: 4293 cmp r3, r2 80118d2: d04c beq.n 801196e 80118d4: 687b ldr r3, [r7, #4] 80118d6: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118da: 681b ldr r3, [r3, #0] 80118dc: 4a89 ldr r2, [pc, #548] @ (8011b04 ) 80118de: 4293 cmp r3, r2 80118e0: d045 beq.n 801196e 80118e2: 687b ldr r3, [r7, #4] 80118e4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118e8: 681b ldr r3, [r3, #0] 80118ea: 4a87 ldr r2, [pc, #540] @ (8011b08 ) 80118ec: 4293 cmp r3, r2 80118ee: d03e beq.n 801196e 80118f0: 687b ldr r3, [r7, #4] 80118f2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80118f6: 681b ldr r3, [r3, #0] 80118f8: 4a84 ldr r2, [pc, #528] @ (8011b0c ) 80118fa: 4293 cmp r3, r2 80118fc: d037 beq.n 801196e 80118fe: 687b ldr r3, [r7, #4] 8011900: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011904: 681b ldr r3, [r3, #0] 8011906: 4a82 ldr r2, [pc, #520] @ (8011b10 ) 8011908: 4293 cmp r3, r2 801190a: d030 beq.n 801196e 801190c: 687b ldr r3, [r7, #4] 801190e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011912: 681b ldr r3, [r3, #0] 8011914: 4a7f ldr r2, [pc, #508] @ (8011b14 ) 8011916: 4293 cmp r3, r2 8011918: d029 beq.n 801196e 801191a: 687b ldr r3, [r7, #4] 801191c: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011920: 681b ldr r3, [r3, #0] 8011922: 4a7d ldr r2, [pc, #500] @ (8011b18 ) 8011924: 4293 cmp r3, r2 8011926: d022 beq.n 801196e 8011928: 687b ldr r3, [r7, #4] 801192a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801192e: 681b ldr r3, [r3, #0] 8011930: 4a7a ldr r2, [pc, #488] @ (8011b1c ) 8011932: 4293 cmp r3, r2 8011934: d01b beq.n 801196e 8011936: 687b ldr r3, [r7, #4] 8011938: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801193c: 681b ldr r3, [r3, #0] 801193e: 4a78 ldr r2, [pc, #480] @ (8011b20 ) 8011940: 4293 cmp r3, r2 8011942: d014 beq.n 801196e 8011944: 687b ldr r3, [r7, #4] 8011946: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 801194a: 681b ldr r3, [r3, #0] 801194c: 4a75 ldr r2, [pc, #468] @ (8011b24 ) 801194e: 4293 cmp r3, r2 8011950: d00d beq.n 801196e 8011952: 687b ldr r3, [r7, #4] 8011954: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011958: 681b ldr r3, [r3, #0] 801195a: 4a73 ldr r2, [pc, #460] @ (8011b28 ) 801195c: 4293 cmp r3, r2 801195e: d006 beq.n 801196e 8011960: 687b ldr r3, [r7, #4] 8011962: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011966: 681b ldr r3, [r3, #0] 8011968: 4a70 ldr r2, [pc, #448] @ (8011b2c ) 801196a: 4293 cmp r3, r2 801196c: d106 bne.n 801197c 801196e: 687b ldr r3, [r7, #4] 8011970: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011974: 681b ldr r3, [r3, #0] 8011976: 685b ldr r3, [r3, #4] 8011978: b29b uxth r3, r3 801197a: e005 b.n 8011988 801197c: 687b ldr r3, [r7, #4] 801197e: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011982: 681b ldr r3, [r3, #0] 8011984: 685b ldr r3, [r3, #4] 8011986: b29b uxth r3, r3 8011988: f8a7 30be strh.w r3, [r7, #190] @ 0xbe if ((nb_remaining_rx_data > 0U) 801198c: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe 8011990: 2b00 cmp r3, #0 8011992: f000 81ab beq.w 8011cec && (nb_remaining_rx_data < huart->RxXferSize)) 8011996: 687b ldr r3, [r7, #4] 8011998: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 801199c: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80119a0: 429a cmp r2, r3 80119a2: f080 81a3 bcs.w 8011cec { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; 80119a6: 687b ldr r3, [r7, #4] 80119a8: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe 80119ac: f8a3 205e strh.w r2, [r3, #94] @ 0x5e /* In Normal mode, end DMA xfer and HAL UART Rx process*/ if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) 80119b0: 687b ldr r3, [r7, #4] 80119b2: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 80119b6: 69db ldr r3, [r3, #28] 80119b8: f5b3 7f80 cmp.w r3, #256 @ 0x100 80119bc: f000 8087 beq.w 8011ace { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80119c0: 687b ldr r3, [r7, #4] 80119c2: 681b ldr r3, [r3, #0] 80119c4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80119c8: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88 80119cc: e853 3f00 ldrex r3, [r3] 80119d0: f8c7 3084 str.w r3, [r7, #132] @ 0x84 return(result); 80119d4: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 80119d8: f423 7380 bic.w r3, r3, #256 @ 0x100 80119dc: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 80119e0: 687b ldr r3, [r7, #4] 80119e2: 681b ldr r3, [r3, #0] 80119e4: 461a mov r2, r3 80119e6: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8 80119ea: f8c7 3094 str.w r3, [r7, #148] @ 0x94 80119ee: f8c7 2090 str.w r2, [r7, #144] @ 0x90 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80119f2: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90 80119f6: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 80119fa: e841 2300 strex r3, r2, [r1] 80119fe: f8c7 308c str.w r3, [r7, #140] @ 0x8c return(result); 8011a02: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 8011a06: 2b00 cmp r3, #0 8011a08: d1da bne.n 80119c0 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8011a0a: 687b ldr r3, [r7, #4] 8011a0c: 681b ldr r3, [r3, #0] 8011a0e: 3308 adds r3, #8 8011a10: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a12: 6f7b ldr r3, [r7, #116] @ 0x74 8011a14: e853 3f00 ldrex r3, [r3] 8011a18: 673b str r3, [r7, #112] @ 0x70 return(result); 8011a1a: 6f3b ldr r3, [r7, #112] @ 0x70 8011a1c: f023 0301 bic.w r3, r3, #1 8011a20: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8011a24: 687b ldr r3, [r7, #4] 8011a26: 681b ldr r3, [r3, #0] 8011a28: 3308 adds r3, #8 8011a2a: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4 8011a2e: f8c7 2080 str.w r2, [r7, #128] @ 0x80 8011a32: 67fb str r3, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a34: 6ff9 ldr r1, [r7, #124] @ 0x7c 8011a36: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8011a3a: e841 2300 strex r3, r2, [r1] 8011a3e: 67bb str r3, [r7, #120] @ 0x78 return(result); 8011a40: 6fbb ldr r3, [r7, #120] @ 0x78 8011a42: 2b00 cmp r3, #0 8011a44: d1e1 bne.n 8011a0a /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 8011a46: 687b ldr r3, [r7, #4] 8011a48: 681b ldr r3, [r3, #0] 8011a4a: 3308 adds r3, #8 8011a4c: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a4e: 6e3b ldr r3, [r7, #96] @ 0x60 8011a50: e853 3f00 ldrex r3, [r3] 8011a54: 65fb str r3, [r7, #92] @ 0x5c return(result); 8011a56: 6dfb ldr r3, [r7, #92] @ 0x5c 8011a58: f023 0340 bic.w r3, r3, #64 @ 0x40 8011a5c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8011a60: 687b ldr r3, [r7, #4] 8011a62: 681b ldr r3, [r3, #0] 8011a64: 3308 adds r3, #8 8011a66: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0 8011a6a: 66fa str r2, [r7, #108] @ 0x6c 8011a6c: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011a6e: 6eb9 ldr r1, [r7, #104] @ 0x68 8011a70: 6efa ldr r2, [r7, #108] @ 0x6c 8011a72: e841 2300 strex r3, r2, [r1] 8011a76: 667b str r3, [r7, #100] @ 0x64 return(result); 8011a78: 6e7b ldr r3, [r7, #100] @ 0x64 8011a7a: 2b00 cmp r3, #0 8011a7c: d1e3 bne.n 8011a46 /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011a7e: 687b ldr r3, [r7, #4] 8011a80: 2220 movs r2, #32 8011a82: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011a86: 687b ldr r3, [r7, #4] 8011a88: 2200 movs r2, #0 8011a8a: 66da str r2, [r3, #108] @ 0x6c ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011a8c: 687b ldr r3, [r7, #4] 8011a8e: 681b ldr r3, [r3, #0] 8011a90: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011a92: 6cfb ldr r3, [r7, #76] @ 0x4c 8011a94: e853 3f00 ldrex r3, [r3] 8011a98: 64bb str r3, [r7, #72] @ 0x48 return(result); 8011a9a: 6cbb ldr r3, [r7, #72] @ 0x48 8011a9c: f023 0310 bic.w r3, r3, #16 8011aa0: f8c7 30ac str.w r3, [r7, #172] @ 0xac 8011aa4: 687b ldr r3, [r7, #4] 8011aa6: 681b ldr r3, [r3, #0] 8011aa8: 461a mov r2, r3 8011aaa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8011aae: 65bb str r3, [r7, #88] @ 0x58 8011ab0: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011ab2: 6d79 ldr r1, [r7, #84] @ 0x54 8011ab4: 6dba ldr r2, [r7, #88] @ 0x58 8011ab6: e841 2300 strex r3, r2, [r1] 8011aba: 653b str r3, [r7, #80] @ 0x50 return(result); 8011abc: 6d3b ldr r3, [r7, #80] @ 0x50 8011abe: 2b00 cmp r3, #0 8011ac0: d1e4 bne.n 8011a8c /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); 8011ac2: 687b ldr r3, [r7, #4] 8011ac4: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80 8011ac8: 4618 mov r0, r3 8011aca: f7f7 fb0d bl 80090e8 } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011ace: 687b ldr r3, [r7, #4] 8011ad0: 2202 movs r2, #2 8011ad2: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8011ad4: 687b ldr r3, [r7, #4] 8011ad6: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011ada: 687b ldr r3, [r7, #4] 8011adc: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011ae0: b29b uxth r3, r3 8011ae2: 1ad3 subs r3, r2, r3 8011ae4: b29b uxth r3, r3 8011ae6: 4619 mov r1, r3 8011ae8: 6878 ldr r0, [r7, #4] 8011aea: f7f2 ffff bl 8004aec #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011aee: e0fd b.n 8011cec 8011af0: 40020010 .word 0x40020010 8011af4: 40020028 .word 0x40020028 8011af8: 40020040 .word 0x40020040 8011afc: 40020058 .word 0x40020058 8011b00: 40020070 .word 0x40020070 8011b04: 40020088 .word 0x40020088 8011b08: 400200a0 .word 0x400200a0 8011b0c: 400200b8 .word 0x400200b8 8011b10: 40020410 .word 0x40020410 8011b14: 40020428 .word 0x40020428 8011b18: 40020440 .word 0x40020440 8011b1c: 40020458 .word 0x40020458 8011b20: 40020470 .word 0x40020470 8011b24: 40020488 .word 0x40020488 8011b28: 400204a0 .word 0x400204a0 8011b2c: 400204b8 .word 0x400204b8 else { /* DMA mode not enabled */ /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; 8011b30: 687b ldr r3, [r7, #4] 8011b32: f8b3 205c ldrh.w r2, [r3, #92] @ 0x5c 8011b36: 687b ldr r3, [r7, #4] 8011b38: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011b3c: b29b uxth r3, r3 8011b3e: 1ad3 subs r3, r2, r3 8011b40: f8a7 30ce strh.w r3, [r7, #206] @ 0xce if ((huart->RxXferCount > 0U) 8011b44: 687b ldr r3, [r7, #4] 8011b46: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8011b4a: b29b uxth r3, r3 8011b4c: 2b00 cmp r3, #0 8011b4e: f000 80cf beq.w 8011cf0 && (nb_rx_data > 0U)) 8011b52: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011b56: 2b00 cmp r3, #0 8011b58: f000 80ca beq.w 8011cf0 { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8011b5c: 687b ldr r3, [r7, #4] 8011b5e: 681b ldr r3, [r3, #0] 8011b60: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011b62: 6bbb ldr r3, [r7, #56] @ 0x38 8011b64: e853 3f00 ldrex r3, [r3] 8011b68: 637b str r3, [r7, #52] @ 0x34 return(result); 8011b6a: 6b7b ldr r3, [r7, #52] @ 0x34 8011b6c: f423 7390 bic.w r3, r3, #288 @ 0x120 8011b70: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8011b74: 687b ldr r3, [r7, #4] 8011b76: 681b ldr r3, [r3, #0] 8011b78: 461a mov r2, r3 8011b7a: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8 8011b7e: 647b str r3, [r7, #68] @ 0x44 8011b80: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011b82: 6c39 ldr r1, [r7, #64] @ 0x40 8011b84: 6c7a ldr r2, [r7, #68] @ 0x44 8011b86: e841 2300 strex r3, r2, [r1] 8011b8a: 63fb str r3, [r7, #60] @ 0x3c return(result); 8011b8c: 6bfb ldr r3, [r7, #60] @ 0x3c 8011b8e: 2b00 cmp r3, #0 8011b90: d1e4 bne.n 8011b5c /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8011b92: 687b ldr r3, [r7, #4] 8011b94: 681b ldr r3, [r3, #0] 8011b96: 3308 adds r3, #8 8011b98: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011b9a: 6a7b ldr r3, [r7, #36] @ 0x24 8011b9c: e853 3f00 ldrex r3, [r3] 8011ba0: 623b str r3, [r7, #32] return(result); 8011ba2: 6a3a ldr r2, [r7, #32] 8011ba4: 4b55 ldr r3, [pc, #340] @ (8011cfc ) 8011ba6: 4013 ands r3, r2 8011ba8: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4 8011bac: 687b ldr r3, [r7, #4] 8011bae: 681b ldr r3, [r3, #0] 8011bb0: 3308 adds r3, #8 8011bb2: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4 8011bb6: 633a str r2, [r7, #48] @ 0x30 8011bb8: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011bba: 6af9 ldr r1, [r7, #44] @ 0x2c 8011bbc: 6b3a ldr r2, [r7, #48] @ 0x30 8011bbe: e841 2300 strex r3, r2, [r1] 8011bc2: 62bb str r3, [r7, #40] @ 0x28 return(result); 8011bc4: 6abb ldr r3, [r7, #40] @ 0x28 8011bc6: 2b00 cmp r3, #0 8011bc8: d1e3 bne.n 8011b92 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8011bca: 687b ldr r3, [r7, #4] 8011bcc: 2220 movs r2, #32 8011bce: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8011bd2: 687b ldr r3, [r7, #4] 8011bd4: 2200 movs r2, #0 8011bd6: 66da str r2, [r3, #108] @ 0x6c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8011bd8: 687b ldr r3, [r7, #4] 8011bda: 2200 movs r2, #0 8011bdc: 675a str r2, [r3, #116] @ 0x74 ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8011bde: 687b ldr r3, [r7, #4] 8011be0: 681b ldr r3, [r3, #0] 8011be2: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8011be4: 693b ldr r3, [r7, #16] 8011be6: e853 3f00 ldrex r3, [r3] 8011bea: 60fb str r3, [r7, #12] return(result); 8011bec: 68fb ldr r3, [r7, #12] 8011bee: f023 0310 bic.w r3, r3, #16 8011bf2: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8011bf6: 687b ldr r3, [r7, #4] 8011bf8: 681b ldr r3, [r3, #0] 8011bfa: 461a mov r2, r3 8011bfc: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0 8011c00: 61fb str r3, [r7, #28] 8011c02: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8011c04: 69b9 ldr r1, [r7, #24] 8011c06: 69fa ldr r2, [r7, #28] 8011c08: e841 2300 strex r3, r2, [r1] 8011c0c: 617b str r3, [r7, #20] return(result); 8011c0e: 697b ldr r3, [r7, #20] 8011c10: 2b00 cmp r3, #0 8011c12: d1e4 bne.n 8011bde /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Idle Event */ huart->RxEventType = HAL_UART_RXEVENT_IDLE; 8011c14: 687b ldr r3, [r7, #4] 8011c16: 2202 movs r2, #2 8011c18: 671a str r2, [r3, #112] @ 0x70 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); 8011c1a: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce 8011c1e: 4619 mov r1, r3 8011c20: 6878 ldr r0, [r7, #4] 8011c22: f7f2 ff63 bl 8004aec #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } return; 8011c26: e063 b.n 8011cf0 } } /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) 8011c28: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c2c: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8011c30: 2b00 cmp r3, #0 8011c32: d00e beq.n 8011c52 8011c34: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011c38: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8011c3c: 2b00 cmp r3, #0 8011c3e: d008 beq.n 8011c52 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); 8011c40: 687b ldr r3, [r7, #4] 8011c42: 681b ldr r3, [r3, #0] 8011c44: f44f 1280 mov.w r2, #1048576 @ 0x100000 8011c48: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Wakeup Callback */ huart->WakeupCallback(huart); #else /* Call legacy weak Wakeup Callback */ HAL_UARTEx_WakeupCallback(huart); 8011c4a: 6878 ldr r0, [r7, #4] 8011c4c: f002 f80c bl 8013c68 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011c50: e051 b.n 8011cf6 } /* UART in mode Transmitter ------------------------------------------------*/ if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) 8011c52: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c56: f003 0380 and.w r3, r3, #128 @ 0x80 8011c5a: 2b00 cmp r3, #0 8011c5c: d014 beq.n 8011c88 && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) 8011c5e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011c62: f003 0380 and.w r3, r3, #128 @ 0x80 8011c66: 2b00 cmp r3, #0 8011c68: d105 bne.n 8011c76 || ((cr3its & USART_CR3_TXFTIE) != 0U))) 8011c6a: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc 8011c6e: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011c72: 2b00 cmp r3, #0 8011c74: d008 beq.n 8011c88 { if (huart->TxISR != NULL) 8011c76: 687b ldr r3, [r7, #4] 8011c78: 6f9b ldr r3, [r3, #120] @ 0x78 8011c7a: 2b00 cmp r3, #0 8011c7c: d03a beq.n 8011cf4 { huart->TxISR(huart); 8011c7e: 687b ldr r3, [r7, #4] 8011c80: 6f9b ldr r3, [r3, #120] @ 0x78 8011c82: 6878 ldr r0, [r7, #4] 8011c84: 4798 blx r3 } return; 8011c86: e035 b.n 8011cf4 } /* UART in mode Transmitter (transmission end) -----------------------------*/ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) 8011c88: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011c8c: f003 0340 and.w r3, r3, #64 @ 0x40 8011c90: 2b00 cmp r3, #0 8011c92: d009 beq.n 8011ca8 8011c94: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011c98: f003 0340 and.w r3, r3, #64 @ 0x40 8011c9c: 2b00 cmp r3, #0 8011c9e: d003 beq.n 8011ca8 { UART_EndTransmit_IT(huart); 8011ca0: 6878 ldr r0, [r7, #4] 8011ca2: f001 fa99 bl 80131d8 return; 8011ca6: e026 b.n 8011cf6 } /* UART TX Fifo Empty occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) 8011ca8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011cac: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8011cb0: 2b00 cmp r3, #0 8011cb2: d009 beq.n 8011cc8 8011cb4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011cb8: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000 8011cbc: 2b00 cmp r3, #0 8011cbe: d003 beq.n 8011cc8 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Tx Fifo Empty Callback */ huart->TxFifoEmptyCallback(huart); #else /* Call legacy weak Tx Fifo Empty Callback */ HAL_UARTEx_TxFifoEmptyCallback(huart); 8011cc0: 6878 ldr r0, [r7, #4] 8011cc2: f001 ffe5 bl 8013c90 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011cc6: e016 b.n 8011cf6 } /* UART RX Fifo Full occurred ----------------------------------------------*/ if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) 8011cc8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4 8011ccc: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8011cd0: 2b00 cmp r3, #0 8011cd2: d010 beq.n 8011cf6 8011cd4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0 8011cd8: 2b00 cmp r3, #0 8011cda: da0c bge.n 8011cf6 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /* Call registered Rx Fifo Full Callback */ huart->RxFifoFullCallback(huart); #else /* Call legacy weak Rx Fifo Full Callback */ HAL_UARTEx_RxFifoFullCallback(huart); 8011cdc: 6878 ldr r0, [r7, #4] 8011cde: f001 ffcd bl 8013c7c #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; 8011ce2: e008 b.n 8011cf6 return; 8011ce4: bf00 nop 8011ce6: e006 b.n 8011cf6 return; 8011ce8: bf00 nop 8011cea: e004 b.n 8011cf6 return; 8011cec: bf00 nop 8011cee: e002 b.n 8011cf6 return; 8011cf0: bf00 nop 8011cf2: e000 b.n 8011cf6 return; 8011cf4: bf00 nop } } 8011cf6: 37e8 adds r7, #232 @ 0xe8 8011cf8: 46bd mov sp, r7 8011cfa: bd80 pop {r7, pc} 8011cfc: effffffe .word 0xeffffffe 08011d00 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8011d00: b480 push {r7} 8011d02: b083 sub sp, #12 8011d04: af00 add r7, sp, #0 8011d06: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8011d08: bf00 nop 8011d0a: 370c adds r7, #12 8011d0c: 46bd mov sp, r7 8011d0e: f85d 7b04 ldr.w r7, [sp], #4 8011d12: 4770 bx lr 08011d14 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8011d14: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8011d18: b092 sub sp, #72 @ 0x48 8011d1a: af00 add r7, sp, #0 8011d1c: 6178 str r0, [r7, #20] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8011d1e: 2300 movs r3, #0 8011d20: f887 3042 strb.w r3, [r7, #66] @ 0x42 * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8011d24: 697b ldr r3, [r7, #20] 8011d26: 689a ldr r2, [r3, #8] 8011d28: 697b ldr r3, [r7, #20] 8011d2a: 691b ldr r3, [r3, #16] 8011d2c: 431a orrs r2, r3 8011d2e: 697b ldr r3, [r7, #20] 8011d30: 695b ldr r3, [r3, #20] 8011d32: 431a orrs r2, r3 8011d34: 697b ldr r3, [r7, #20] 8011d36: 69db ldr r3, [r3, #28] 8011d38: 4313 orrs r3, r2 8011d3a: 647b str r3, [r7, #68] @ 0x44 MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8011d3c: 697b ldr r3, [r7, #20] 8011d3e: 681b ldr r3, [r3, #0] 8011d40: 681a ldr r2, [r3, #0] 8011d42: 4bbe ldr r3, [pc, #760] @ (801203c ) 8011d44: 4013 ands r3, r2 8011d46: 697a ldr r2, [r7, #20] 8011d48: 6812 ldr r2, [r2, #0] 8011d4a: 6c79 ldr r1, [r7, #68] @ 0x44 8011d4c: 430b orrs r3, r1 8011d4e: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8011d50: 697b ldr r3, [r7, #20] 8011d52: 681b ldr r3, [r3, #0] 8011d54: 685b ldr r3, [r3, #4] 8011d56: f423 5140 bic.w r1, r3, #12288 @ 0x3000 8011d5a: 697b ldr r3, [r7, #20] 8011d5c: 68da ldr r2, [r3, #12] 8011d5e: 697b ldr r3, [r7, #20] 8011d60: 681b ldr r3, [r3, #0] 8011d62: 430a orrs r2, r1 8011d64: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8011d66: 697b ldr r3, [r7, #20] 8011d68: 699b ldr r3, [r3, #24] 8011d6a: 647b str r3, [r7, #68] @ 0x44 if (!(UART_INSTANCE_LOWPOWER(huart))) 8011d6c: 697b ldr r3, [r7, #20] 8011d6e: 681b ldr r3, [r3, #0] 8011d70: 4ab3 ldr r2, [pc, #716] @ (8012040 ) 8011d72: 4293 cmp r3, r2 8011d74: d004 beq.n 8011d80 { tmpreg |= huart->Init.OneBitSampling; 8011d76: 697b ldr r3, [r7, #20] 8011d78: 6a1b ldr r3, [r3, #32] 8011d7a: 6c7a ldr r2, [r7, #68] @ 0x44 8011d7c: 4313 orrs r3, r2 8011d7e: 647b str r3, [r7, #68] @ 0x44 } MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8011d80: 697b ldr r3, [r7, #20] 8011d82: 681b ldr r3, [r3, #0] 8011d84: 689a ldr r2, [r3, #8] 8011d86: 4baf ldr r3, [pc, #700] @ (8012044 ) 8011d88: 4013 ands r3, r2 8011d8a: 697a ldr r2, [r7, #20] 8011d8c: 6812 ldr r2, [r2, #0] 8011d8e: 6c79 ldr r1, [r7, #68] @ 0x44 8011d90: 430b orrs r3, r1 8011d92: 6093 str r3, [r2, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8011d94: 697b ldr r3, [r7, #20] 8011d96: 681b ldr r3, [r3, #0] 8011d98: 6adb ldr r3, [r3, #44] @ 0x2c 8011d9a: f023 010f bic.w r1, r3, #15 8011d9e: 697b ldr r3, [r7, #20] 8011da0: 6a5a ldr r2, [r3, #36] @ 0x24 8011da2: 697b ldr r3, [r7, #20] 8011da4: 681b ldr r3, [r3, #0] 8011da6: 430a orrs r2, r1 8011da8: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8011daa: 697b ldr r3, [r7, #20] 8011dac: 681b ldr r3, [r3, #0] 8011dae: 4aa6 ldr r2, [pc, #664] @ (8012048 ) 8011db0: 4293 cmp r3, r2 8011db2: d177 bne.n 8011ea4 8011db4: 4ba5 ldr r3, [pc, #660] @ (801204c ) 8011db6: 6d5b ldr r3, [r3, #84] @ 0x54 8011db8: f003 0338 and.w r3, r3, #56 @ 0x38 8011dbc: 2b28 cmp r3, #40 @ 0x28 8011dbe: d86d bhi.n 8011e9c 8011dc0: a201 add r2, pc, #4 @ (adr r2, 8011dc8 ) 8011dc2: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011dc6: bf00 nop 8011dc8: 08011e6d .word 0x08011e6d 8011dcc: 08011e9d .word 0x08011e9d 8011dd0: 08011e9d .word 0x08011e9d 8011dd4: 08011e9d .word 0x08011e9d 8011dd8: 08011e9d .word 0x08011e9d 8011ddc: 08011e9d .word 0x08011e9d 8011de0: 08011e9d .word 0x08011e9d 8011de4: 08011e9d .word 0x08011e9d 8011de8: 08011e75 .word 0x08011e75 8011dec: 08011e9d .word 0x08011e9d 8011df0: 08011e9d .word 0x08011e9d 8011df4: 08011e9d .word 0x08011e9d 8011df8: 08011e9d .word 0x08011e9d 8011dfc: 08011e9d .word 0x08011e9d 8011e00: 08011e9d .word 0x08011e9d 8011e04: 08011e9d .word 0x08011e9d 8011e08: 08011e7d .word 0x08011e7d 8011e0c: 08011e9d .word 0x08011e9d 8011e10: 08011e9d .word 0x08011e9d 8011e14: 08011e9d .word 0x08011e9d 8011e18: 08011e9d .word 0x08011e9d 8011e1c: 08011e9d .word 0x08011e9d 8011e20: 08011e9d .word 0x08011e9d 8011e24: 08011e9d .word 0x08011e9d 8011e28: 08011e85 .word 0x08011e85 8011e2c: 08011e9d .word 0x08011e9d 8011e30: 08011e9d .word 0x08011e9d 8011e34: 08011e9d .word 0x08011e9d 8011e38: 08011e9d .word 0x08011e9d 8011e3c: 08011e9d .word 0x08011e9d 8011e40: 08011e9d .word 0x08011e9d 8011e44: 08011e9d .word 0x08011e9d 8011e48: 08011e8d .word 0x08011e8d 8011e4c: 08011e9d .word 0x08011e9d 8011e50: 08011e9d .word 0x08011e9d 8011e54: 08011e9d .word 0x08011e9d 8011e58: 08011e9d .word 0x08011e9d 8011e5c: 08011e9d .word 0x08011e9d 8011e60: 08011e9d .word 0x08011e9d 8011e64: 08011e9d .word 0x08011e9d 8011e68: 08011e95 .word 0x08011e95 8011e6c: 2301 movs r3, #1 8011e6e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e72: e222 b.n 80122ba 8011e74: 2304 movs r3, #4 8011e76: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e7a: e21e b.n 80122ba 8011e7c: 2308 movs r3, #8 8011e7e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e82: e21a b.n 80122ba 8011e84: 2310 movs r3, #16 8011e86: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e8a: e216 b.n 80122ba 8011e8c: 2320 movs r3, #32 8011e8e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e92: e212 b.n 80122ba 8011e94: 2340 movs r3, #64 @ 0x40 8011e96: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011e9a: e20e b.n 80122ba 8011e9c: 2380 movs r3, #128 @ 0x80 8011e9e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ea2: e20a b.n 80122ba 8011ea4: 697b ldr r3, [r7, #20] 8011ea6: 681b ldr r3, [r3, #0] 8011ea8: 4a69 ldr r2, [pc, #420] @ (8012050 ) 8011eaa: 4293 cmp r3, r2 8011eac: d130 bne.n 8011f10 8011eae: 4b67 ldr r3, [pc, #412] @ (801204c ) 8011eb0: 6d5b ldr r3, [r3, #84] @ 0x54 8011eb2: f003 0307 and.w r3, r3, #7 8011eb6: 2b05 cmp r3, #5 8011eb8: d826 bhi.n 8011f08 8011eba: a201 add r2, pc, #4 @ (adr r2, 8011ec0 ) 8011ebc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011ec0: 08011ed9 .word 0x08011ed9 8011ec4: 08011ee1 .word 0x08011ee1 8011ec8: 08011ee9 .word 0x08011ee9 8011ecc: 08011ef1 .word 0x08011ef1 8011ed0: 08011ef9 .word 0x08011ef9 8011ed4: 08011f01 .word 0x08011f01 8011ed8: 2300 movs r3, #0 8011eda: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ede: e1ec b.n 80122ba 8011ee0: 2304 movs r3, #4 8011ee2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ee6: e1e8 b.n 80122ba 8011ee8: 2308 movs r3, #8 8011eea: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011eee: e1e4 b.n 80122ba 8011ef0: 2310 movs r3, #16 8011ef2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011ef6: e1e0 b.n 80122ba 8011ef8: 2320 movs r3, #32 8011efa: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011efe: e1dc b.n 80122ba 8011f00: 2340 movs r3, #64 @ 0x40 8011f02: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f06: e1d8 b.n 80122ba 8011f08: 2380 movs r3, #128 @ 0x80 8011f0a: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f0e: e1d4 b.n 80122ba 8011f10: 697b ldr r3, [r7, #20] 8011f12: 681b ldr r3, [r3, #0] 8011f14: 4a4f ldr r2, [pc, #316] @ (8012054 ) 8011f16: 4293 cmp r3, r2 8011f18: d130 bne.n 8011f7c 8011f1a: 4b4c ldr r3, [pc, #304] @ (801204c ) 8011f1c: 6d5b ldr r3, [r3, #84] @ 0x54 8011f1e: f003 0307 and.w r3, r3, #7 8011f22: 2b05 cmp r3, #5 8011f24: d826 bhi.n 8011f74 8011f26: a201 add r2, pc, #4 @ (adr r2, 8011f2c ) 8011f28: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011f2c: 08011f45 .word 0x08011f45 8011f30: 08011f4d .word 0x08011f4d 8011f34: 08011f55 .word 0x08011f55 8011f38: 08011f5d .word 0x08011f5d 8011f3c: 08011f65 .word 0x08011f65 8011f40: 08011f6d .word 0x08011f6d 8011f44: 2300 movs r3, #0 8011f46: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f4a: e1b6 b.n 80122ba 8011f4c: 2304 movs r3, #4 8011f4e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f52: e1b2 b.n 80122ba 8011f54: 2308 movs r3, #8 8011f56: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f5a: e1ae b.n 80122ba 8011f5c: 2310 movs r3, #16 8011f5e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f62: e1aa b.n 80122ba 8011f64: 2320 movs r3, #32 8011f66: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f6a: e1a6 b.n 80122ba 8011f6c: 2340 movs r3, #64 @ 0x40 8011f6e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f72: e1a2 b.n 80122ba 8011f74: 2380 movs r3, #128 @ 0x80 8011f76: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011f7a: e19e b.n 80122ba 8011f7c: 697b ldr r3, [r7, #20] 8011f7e: 681b ldr r3, [r3, #0] 8011f80: 4a35 ldr r2, [pc, #212] @ (8012058 ) 8011f82: 4293 cmp r3, r2 8011f84: d130 bne.n 8011fe8 8011f86: 4b31 ldr r3, [pc, #196] @ (801204c ) 8011f88: 6d5b ldr r3, [r3, #84] @ 0x54 8011f8a: f003 0307 and.w r3, r3, #7 8011f8e: 2b05 cmp r3, #5 8011f90: d826 bhi.n 8011fe0 8011f92: a201 add r2, pc, #4 @ (adr r2, 8011f98 ) 8011f94: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8011f98: 08011fb1 .word 0x08011fb1 8011f9c: 08011fb9 .word 0x08011fb9 8011fa0: 08011fc1 .word 0x08011fc1 8011fa4: 08011fc9 .word 0x08011fc9 8011fa8: 08011fd1 .word 0x08011fd1 8011fac: 08011fd9 .word 0x08011fd9 8011fb0: 2300 movs r3, #0 8011fb2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fb6: e180 b.n 80122ba 8011fb8: 2304 movs r3, #4 8011fba: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fbe: e17c b.n 80122ba 8011fc0: 2308 movs r3, #8 8011fc2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fc6: e178 b.n 80122ba 8011fc8: 2310 movs r3, #16 8011fca: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fce: e174 b.n 80122ba 8011fd0: 2320 movs r3, #32 8011fd2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fd6: e170 b.n 80122ba 8011fd8: 2340 movs r3, #64 @ 0x40 8011fda: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fde: e16c b.n 80122ba 8011fe0: 2380 movs r3, #128 @ 0x80 8011fe2: f887 3043 strb.w r3, [r7, #67] @ 0x43 8011fe6: e168 b.n 80122ba 8011fe8: 697b ldr r3, [r7, #20] 8011fea: 681b ldr r3, [r3, #0] 8011fec: 4a1b ldr r2, [pc, #108] @ (801205c ) 8011fee: 4293 cmp r3, r2 8011ff0: d142 bne.n 8012078 8011ff2: 4b16 ldr r3, [pc, #88] @ (801204c ) 8011ff4: 6d5b ldr r3, [r3, #84] @ 0x54 8011ff6: f003 0307 and.w r3, r3, #7 8011ffa: 2b05 cmp r3, #5 8011ffc: d838 bhi.n 8012070 8011ffe: a201 add r2, pc, #4 @ (adr r2, 8012004 ) 8012000: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012004: 0801201d .word 0x0801201d 8012008: 08012025 .word 0x08012025 801200c: 0801202d .word 0x0801202d 8012010: 08012035 .word 0x08012035 8012014: 08012061 .word 0x08012061 8012018: 08012069 .word 0x08012069 801201c: 2300 movs r3, #0 801201e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012022: e14a b.n 80122ba 8012024: 2304 movs r3, #4 8012026: f887 3043 strb.w r3, [r7, #67] @ 0x43 801202a: e146 b.n 80122ba 801202c: 2308 movs r3, #8 801202e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012032: e142 b.n 80122ba 8012034: 2310 movs r3, #16 8012036: f887 3043 strb.w r3, [r7, #67] @ 0x43 801203a: e13e b.n 80122ba 801203c: cfff69f3 .word 0xcfff69f3 8012040: 58000c00 .word 0x58000c00 8012044: 11fff4ff .word 0x11fff4ff 8012048: 40011000 .word 0x40011000 801204c: 58024400 .word 0x58024400 8012050: 40004400 .word 0x40004400 8012054: 40004800 .word 0x40004800 8012058: 40004c00 .word 0x40004c00 801205c: 40005000 .word 0x40005000 8012060: 2320 movs r3, #32 8012062: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012066: e128 b.n 80122ba 8012068: 2340 movs r3, #64 @ 0x40 801206a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801206e: e124 b.n 80122ba 8012070: 2380 movs r3, #128 @ 0x80 8012072: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012076: e120 b.n 80122ba 8012078: 697b ldr r3, [r7, #20] 801207a: 681b ldr r3, [r3, #0] 801207c: 4acb ldr r2, [pc, #812] @ (80123ac ) 801207e: 4293 cmp r3, r2 8012080: d176 bne.n 8012170 8012082: 4bcb ldr r3, [pc, #812] @ (80123b0 ) 8012084: 6d5b ldr r3, [r3, #84] @ 0x54 8012086: f003 0338 and.w r3, r3, #56 @ 0x38 801208a: 2b28 cmp r3, #40 @ 0x28 801208c: d86c bhi.n 8012168 801208e: a201 add r2, pc, #4 @ (adr r2, 8012094 ) 8012090: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012094: 08012139 .word 0x08012139 8012098: 08012169 .word 0x08012169 801209c: 08012169 .word 0x08012169 80120a0: 08012169 .word 0x08012169 80120a4: 08012169 .word 0x08012169 80120a8: 08012169 .word 0x08012169 80120ac: 08012169 .word 0x08012169 80120b0: 08012169 .word 0x08012169 80120b4: 08012141 .word 0x08012141 80120b8: 08012169 .word 0x08012169 80120bc: 08012169 .word 0x08012169 80120c0: 08012169 .word 0x08012169 80120c4: 08012169 .word 0x08012169 80120c8: 08012169 .word 0x08012169 80120cc: 08012169 .word 0x08012169 80120d0: 08012169 .word 0x08012169 80120d4: 08012149 .word 0x08012149 80120d8: 08012169 .word 0x08012169 80120dc: 08012169 .word 0x08012169 80120e0: 08012169 .word 0x08012169 80120e4: 08012169 .word 0x08012169 80120e8: 08012169 .word 0x08012169 80120ec: 08012169 .word 0x08012169 80120f0: 08012169 .word 0x08012169 80120f4: 08012151 .word 0x08012151 80120f8: 08012169 .word 0x08012169 80120fc: 08012169 .word 0x08012169 8012100: 08012169 .word 0x08012169 8012104: 08012169 .word 0x08012169 8012108: 08012169 .word 0x08012169 801210c: 08012169 .word 0x08012169 8012110: 08012169 .word 0x08012169 8012114: 08012159 .word 0x08012159 8012118: 08012169 .word 0x08012169 801211c: 08012169 .word 0x08012169 8012120: 08012169 .word 0x08012169 8012124: 08012169 .word 0x08012169 8012128: 08012169 .word 0x08012169 801212c: 08012169 .word 0x08012169 8012130: 08012169 .word 0x08012169 8012134: 08012161 .word 0x08012161 8012138: 2301 movs r3, #1 801213a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801213e: e0bc b.n 80122ba 8012140: 2304 movs r3, #4 8012142: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012146: e0b8 b.n 80122ba 8012148: 2308 movs r3, #8 801214a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801214e: e0b4 b.n 80122ba 8012150: 2310 movs r3, #16 8012152: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012156: e0b0 b.n 80122ba 8012158: 2320 movs r3, #32 801215a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801215e: e0ac b.n 80122ba 8012160: 2340 movs r3, #64 @ 0x40 8012162: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012166: e0a8 b.n 80122ba 8012168: 2380 movs r3, #128 @ 0x80 801216a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801216e: e0a4 b.n 80122ba 8012170: 697b ldr r3, [r7, #20] 8012172: 681b ldr r3, [r3, #0] 8012174: 4a8f ldr r2, [pc, #572] @ (80123b4 ) 8012176: 4293 cmp r3, r2 8012178: d130 bne.n 80121dc 801217a: 4b8d ldr r3, [pc, #564] @ (80123b0 ) 801217c: 6d5b ldr r3, [r3, #84] @ 0x54 801217e: f003 0307 and.w r3, r3, #7 8012182: 2b05 cmp r3, #5 8012184: d826 bhi.n 80121d4 8012186: a201 add r2, pc, #4 @ (adr r2, 801218c ) 8012188: f852 f023 ldr.w pc, [r2, r3, lsl #2] 801218c: 080121a5 .word 0x080121a5 8012190: 080121ad .word 0x080121ad 8012194: 080121b5 .word 0x080121b5 8012198: 080121bd .word 0x080121bd 801219c: 080121c5 .word 0x080121c5 80121a0: 080121cd .word 0x080121cd 80121a4: 2300 movs r3, #0 80121a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121aa: e086 b.n 80122ba 80121ac: 2304 movs r3, #4 80121ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121b2: e082 b.n 80122ba 80121b4: 2308 movs r3, #8 80121b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121ba: e07e b.n 80122ba 80121bc: 2310 movs r3, #16 80121be: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121c2: e07a b.n 80122ba 80121c4: 2320 movs r3, #32 80121c6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121ca: e076 b.n 80122ba 80121cc: 2340 movs r3, #64 @ 0x40 80121ce: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121d2: e072 b.n 80122ba 80121d4: 2380 movs r3, #128 @ 0x80 80121d6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80121da: e06e b.n 80122ba 80121dc: 697b ldr r3, [r7, #20] 80121de: 681b ldr r3, [r3, #0] 80121e0: 4a75 ldr r2, [pc, #468] @ (80123b8 ) 80121e2: 4293 cmp r3, r2 80121e4: d130 bne.n 8012248 80121e6: 4b72 ldr r3, [pc, #456] @ (80123b0 ) 80121e8: 6d5b ldr r3, [r3, #84] @ 0x54 80121ea: f003 0307 and.w r3, r3, #7 80121ee: 2b05 cmp r3, #5 80121f0: d826 bhi.n 8012240 80121f2: a201 add r2, pc, #4 @ (adr r2, 80121f8 ) 80121f4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80121f8: 08012211 .word 0x08012211 80121fc: 08012219 .word 0x08012219 8012200: 08012221 .word 0x08012221 8012204: 08012229 .word 0x08012229 8012208: 08012231 .word 0x08012231 801220c: 08012239 .word 0x08012239 8012210: 2300 movs r3, #0 8012212: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012216: e050 b.n 80122ba 8012218: 2304 movs r3, #4 801221a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801221e: e04c b.n 80122ba 8012220: 2308 movs r3, #8 8012222: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012226: e048 b.n 80122ba 8012228: 2310 movs r3, #16 801222a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801222e: e044 b.n 80122ba 8012230: 2320 movs r3, #32 8012232: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012236: e040 b.n 80122ba 8012238: 2340 movs r3, #64 @ 0x40 801223a: f887 3043 strb.w r3, [r7, #67] @ 0x43 801223e: e03c b.n 80122ba 8012240: 2380 movs r3, #128 @ 0x80 8012242: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012246: e038 b.n 80122ba 8012248: 697b ldr r3, [r7, #20] 801224a: 681b ldr r3, [r3, #0] 801224c: 4a5b ldr r2, [pc, #364] @ (80123bc ) 801224e: 4293 cmp r3, r2 8012250: d130 bne.n 80122b4 8012252: 4b57 ldr r3, [pc, #348] @ (80123b0 ) 8012254: 6d9b ldr r3, [r3, #88] @ 0x58 8012256: f003 0307 and.w r3, r3, #7 801225a: 2b05 cmp r3, #5 801225c: d826 bhi.n 80122ac 801225e: a201 add r2, pc, #4 @ (adr r2, 8012264 ) 8012260: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012264: 0801227d .word 0x0801227d 8012268: 08012285 .word 0x08012285 801226c: 0801228d .word 0x0801228d 8012270: 08012295 .word 0x08012295 8012274: 0801229d .word 0x0801229d 8012278: 080122a5 .word 0x080122a5 801227c: 2302 movs r3, #2 801227e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012282: e01a b.n 80122ba 8012284: 2304 movs r3, #4 8012286: f887 3043 strb.w r3, [r7, #67] @ 0x43 801228a: e016 b.n 80122ba 801228c: 2308 movs r3, #8 801228e: f887 3043 strb.w r3, [r7, #67] @ 0x43 8012292: e012 b.n 80122ba 8012294: 2310 movs r3, #16 8012296: f887 3043 strb.w r3, [r7, #67] @ 0x43 801229a: e00e b.n 80122ba 801229c: 2320 movs r3, #32 801229e: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122a2: e00a b.n 80122ba 80122a4: 2340 movs r3, #64 @ 0x40 80122a6: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122aa: e006 b.n 80122ba 80122ac: 2380 movs r3, #128 @ 0x80 80122ae: f887 3043 strb.w r3, [r7, #67] @ 0x43 80122b2: e002 b.n 80122ba 80122b4: 2380 movs r3, #128 @ 0x80 80122b6: f887 3043 strb.w r3, [r7, #67] @ 0x43 /* Check LPUART instance */ if (UART_INSTANCE_LOWPOWER(huart)) 80122ba: 697b ldr r3, [r7, #20] 80122bc: 681b ldr r3, [r3, #0] 80122be: 4a3f ldr r2, [pc, #252] @ (80123bc ) 80122c0: 4293 cmp r3, r2 80122c2: f040 80f8 bne.w 80124b6 { /* Retrieve frequency clock */ switch (clocksource) 80122c6: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80122ca: 2b20 cmp r3, #32 80122cc: dc46 bgt.n 801235c 80122ce: 2b02 cmp r3, #2 80122d0: f2c0 8082 blt.w 80123d8 80122d4: 3b02 subs r3, #2 80122d6: 2b1e cmp r3, #30 80122d8: d87e bhi.n 80123d8 80122da: a201 add r2, pc, #4 @ (adr r2, 80122e0 ) 80122dc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80122e0: 08012363 .word 0x08012363 80122e4: 080123d9 .word 0x080123d9 80122e8: 0801236b .word 0x0801236b 80122ec: 080123d9 .word 0x080123d9 80122f0: 080123d9 .word 0x080123d9 80122f4: 080123d9 .word 0x080123d9 80122f8: 0801237b .word 0x0801237b 80122fc: 080123d9 .word 0x080123d9 8012300: 080123d9 .word 0x080123d9 8012304: 080123d9 .word 0x080123d9 8012308: 080123d9 .word 0x080123d9 801230c: 080123d9 .word 0x080123d9 8012310: 080123d9 .word 0x080123d9 8012314: 080123d9 .word 0x080123d9 8012318: 0801238b .word 0x0801238b 801231c: 080123d9 .word 0x080123d9 8012320: 080123d9 .word 0x080123d9 8012324: 080123d9 .word 0x080123d9 8012328: 080123d9 .word 0x080123d9 801232c: 080123d9 .word 0x080123d9 8012330: 080123d9 .word 0x080123d9 8012334: 080123d9 .word 0x080123d9 8012338: 080123d9 .word 0x080123d9 801233c: 080123d9 .word 0x080123d9 8012340: 080123d9 .word 0x080123d9 8012344: 080123d9 .word 0x080123d9 8012348: 080123d9 .word 0x080123d9 801234c: 080123d9 .word 0x080123d9 8012350: 080123d9 .word 0x080123d9 8012354: 080123d9 .word 0x080123d9 8012358: 080123cb .word 0x080123cb 801235c: 2b40 cmp r3, #64 @ 0x40 801235e: d037 beq.n 80123d0 8012360: e03a b.n 80123d8 { case UART_CLOCKSOURCE_D3PCLK1: pclk = HAL_RCCEx_GetD3PCLK1Freq(); 8012362: f7fc fa8b bl 800e87c 8012366: 63f8 str r0, [r7, #60] @ 0x3c break; 8012368: e03c b.n 80123e4 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 801236a: f107 0324 add.w r3, r7, #36 @ 0x24 801236e: 4618 mov r0, r3 8012370: f7fc fa9a bl 800e8a8 pclk = pll2_clocks.PLL2_Q_Frequency; 8012374: 6abb ldr r3, [r7, #40] @ 0x28 8012376: 63fb str r3, [r7, #60] @ 0x3c break; 8012378: e034 b.n 80123e4 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 801237a: f107 0318 add.w r3, r7, #24 801237e: 4618 mov r0, r3 8012380: f7fc fbe6 bl 800eb50 pclk = pll3_clocks.PLL3_Q_Frequency; 8012384: 69fb ldr r3, [r7, #28] 8012386: 63fb str r3, [r7, #60] @ 0x3c break; 8012388: e02c b.n 80123e4 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 801238a: 4b09 ldr r3, [pc, #36] @ (80123b0 ) 801238c: 681b ldr r3, [r3, #0] 801238e: f003 0320 and.w r3, r3, #32 8012392: 2b00 cmp r3, #0 8012394: d016 beq.n 80123c4 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 8012396: 4b06 ldr r3, [pc, #24] @ (80123b0 ) 8012398: 681b ldr r3, [r3, #0] 801239a: 08db lsrs r3, r3, #3 801239c: f003 0303 and.w r3, r3, #3 80123a0: 4a07 ldr r2, [pc, #28] @ (80123c0 ) 80123a2: fa22 f303 lsr.w r3, r2, r3 80123a6: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80123a8: e01c b.n 80123e4 80123aa: bf00 nop 80123ac: 40011400 .word 0x40011400 80123b0: 58024400 .word 0x58024400 80123b4: 40007800 .word 0x40007800 80123b8: 40007c00 .word 0x40007c00 80123bc: 58000c00 .word 0x58000c00 80123c0: 03d09000 .word 0x03d09000 pclk = (uint32_t) HSI_VALUE; 80123c4: 4b9d ldr r3, [pc, #628] @ (801263c ) 80123c6: 63fb str r3, [r7, #60] @ 0x3c break; 80123c8: e00c b.n 80123e4 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80123ca: 4b9d ldr r3, [pc, #628] @ (8012640 ) 80123cc: 63fb str r3, [r7, #60] @ 0x3c break; 80123ce: e009 b.n 80123e4 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80123d0: f44f 4300 mov.w r3, #32768 @ 0x8000 80123d4: 63fb str r3, [r7, #60] @ 0x3c break; 80123d6: e005 b.n 80123e4 default: pclk = 0U; 80123d8: 2300 movs r3, #0 80123da: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80123dc: 2301 movs r3, #1 80123de: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80123e2: bf00 nop } /* If proper clock source reported */ if (pclk != 0U) 80123e4: 6bfb ldr r3, [r7, #60] @ 0x3c 80123e6: 2b00 cmp r3, #0 80123e8: f000 81de beq.w 80127a8 { /* Compute clock after Prescaler */ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); 80123ec: 697b ldr r3, [r7, #20] 80123ee: 6a5b ldr r3, [r3, #36] @ 0x24 80123f0: 4a94 ldr r2, [pc, #592] @ (8012644 ) 80123f2: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80123f6: 461a mov r2, r3 80123f8: 6bfb ldr r3, [r7, #60] @ 0x3c 80123fa: fbb3 f3f2 udiv r3, r3, r2 80123fe: 633b str r3, [r7, #48] @ 0x30 /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8012400: 697b ldr r3, [r7, #20] 8012402: 685a ldr r2, [r3, #4] 8012404: 4613 mov r3, r2 8012406: 005b lsls r3, r3, #1 8012408: 4413 add r3, r2 801240a: 6b3a ldr r2, [r7, #48] @ 0x30 801240c: 429a cmp r2, r3 801240e: d305 bcc.n 801241c (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) 8012410: 697b ldr r3, [r7, #20] 8012412: 685b ldr r3, [r3, #4] 8012414: 031b lsls r3, r3, #12 if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || 8012416: 6b3a ldr r2, [r7, #48] @ 0x30 8012418: 429a cmp r2, r3 801241a: d903 bls.n 8012424 { ret = HAL_ERROR; 801241c: 2301 movs r3, #1 801241e: f887 3042 strb.w r3, [r7, #66] @ 0x42 8012422: e1c1 b.n 80127a8 } else { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8012424: 6bfb ldr r3, [r7, #60] @ 0x3c 8012426: 2200 movs r2, #0 8012428: 60bb str r3, [r7, #8] 801242a: 60fa str r2, [r7, #12] 801242c: 697b ldr r3, [r7, #20] 801242e: 6a5b ldr r3, [r3, #36] @ 0x24 8012430: 4a84 ldr r2, [pc, #528] @ (8012644 ) 8012432: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 8012436: b29b uxth r3, r3 8012438: 2200 movs r2, #0 801243a: 603b str r3, [r7, #0] 801243c: 607a str r2, [r7, #4] 801243e: e9d7 2300 ldrd r2, r3, [r7] 8012442: e9d7 0102 ldrd r0, r1, [r7, #8] 8012446: f7ed ff4b bl 80002e0 <__aeabi_uldivmod> 801244a: 4602 mov r2, r0 801244c: 460b mov r3, r1 801244e: 4610 mov r0, r2 8012450: 4619 mov r1, r3 8012452: f04f 0200 mov.w r2, #0 8012456: f04f 0300 mov.w r3, #0 801245a: 020b lsls r3, r1, #8 801245c: ea43 6310 orr.w r3, r3, r0, lsr #24 8012460: 0202 lsls r2, r0, #8 8012462: 6979 ldr r1, [r7, #20] 8012464: 6849 ldr r1, [r1, #4] 8012466: 0849 lsrs r1, r1, #1 8012468: 2000 movs r0, #0 801246a: 460c mov r4, r1 801246c: 4605 mov r5, r0 801246e: eb12 0804 adds.w r8, r2, r4 8012472: eb43 0905 adc.w r9, r3, r5 8012476: 697b ldr r3, [r7, #20] 8012478: 685b ldr r3, [r3, #4] 801247a: 2200 movs r2, #0 801247c: 469a mov sl, r3 801247e: 4693 mov fp, r2 8012480: 4652 mov r2, sl 8012482: 465b mov r3, fp 8012484: 4640 mov r0, r8 8012486: 4649 mov r1, r9 8012488: f7ed ff2a bl 80002e0 <__aeabi_uldivmod> 801248c: 4602 mov r2, r0 801248e: 460b mov r3, r1 8012490: 4613 mov r3, r2 8012492: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) 8012494: 6bbb ldr r3, [r7, #56] @ 0x38 8012496: f5b3 7f40 cmp.w r3, #768 @ 0x300 801249a: d308 bcc.n 80124ae 801249c: 6bbb ldr r3, [r7, #56] @ 0x38 801249e: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80124a2: d204 bcs.n 80124ae { huart->Instance->BRR = usartdiv; 80124a4: 697b ldr r3, [r7, #20] 80124a6: 681b ldr r3, [r3, #0] 80124a8: 6bba ldr r2, [r7, #56] @ 0x38 80124aa: 60da str r2, [r3, #12] 80124ac: e17c b.n 80127a8 } else { ret = HAL_ERROR; 80124ae: 2301 movs r3, #1 80124b0: f887 3042 strb.w r3, [r7, #66] @ 0x42 80124b4: e178 b.n 80127a8 } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 80124b6: 697b ldr r3, [r7, #20] 80124b8: 69db ldr r3, [r3, #28] 80124ba: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80124be: f040 80c5 bne.w 801264c { switch (clocksource) 80124c2: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 80124c6: 2b20 cmp r3, #32 80124c8: dc48 bgt.n 801255c 80124ca: 2b00 cmp r3, #0 80124cc: db7b blt.n 80125c6 80124ce: 2b20 cmp r3, #32 80124d0: d879 bhi.n 80125c6 80124d2: a201 add r2, pc, #4 @ (adr r2, 80124d8 ) 80124d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80124d8: 08012563 .word 0x08012563 80124dc: 0801256b .word 0x0801256b 80124e0: 080125c7 .word 0x080125c7 80124e4: 080125c7 .word 0x080125c7 80124e8: 08012573 .word 0x08012573 80124ec: 080125c7 .word 0x080125c7 80124f0: 080125c7 .word 0x080125c7 80124f4: 080125c7 .word 0x080125c7 80124f8: 08012583 .word 0x08012583 80124fc: 080125c7 .word 0x080125c7 8012500: 080125c7 .word 0x080125c7 8012504: 080125c7 .word 0x080125c7 8012508: 080125c7 .word 0x080125c7 801250c: 080125c7 .word 0x080125c7 8012510: 080125c7 .word 0x080125c7 8012514: 080125c7 .word 0x080125c7 8012518: 08012593 .word 0x08012593 801251c: 080125c7 .word 0x080125c7 8012520: 080125c7 .word 0x080125c7 8012524: 080125c7 .word 0x080125c7 8012528: 080125c7 .word 0x080125c7 801252c: 080125c7 .word 0x080125c7 8012530: 080125c7 .word 0x080125c7 8012534: 080125c7 .word 0x080125c7 8012538: 080125c7 .word 0x080125c7 801253c: 080125c7 .word 0x080125c7 8012540: 080125c7 .word 0x080125c7 8012544: 080125c7 .word 0x080125c7 8012548: 080125c7 .word 0x080125c7 801254c: 080125c7 .word 0x080125c7 8012550: 080125c7 .word 0x080125c7 8012554: 080125c7 .word 0x080125c7 8012558: 080125b9 .word 0x080125b9 801255c: 2b40 cmp r3, #64 @ 0x40 801255e: d02e beq.n 80125be 8012560: e031 b.n 80125c6 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8012562: f7fa f9af bl 800c8c4 8012566: 63f8 str r0, [r7, #60] @ 0x3c break; 8012568: e033 b.n 80125d2 case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 801256a: f7fa f9c1 bl 800c8f0 801256e: 63f8 str r0, [r7, #60] @ 0x3c break; 8012570: e02f b.n 80125d2 case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 8012572: f107 0324 add.w r3, r7, #36 @ 0x24 8012576: 4618 mov r0, r3 8012578: f7fc f996 bl 800e8a8 pclk = pll2_clocks.PLL2_Q_Frequency; 801257c: 6abb ldr r3, [r7, #40] @ 0x28 801257e: 63fb str r3, [r7, #60] @ 0x3c break; 8012580: e027 b.n 80125d2 case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 8012582: f107 0318 add.w r3, r7, #24 8012586: 4618 mov r0, r3 8012588: f7fc fae2 bl 800eb50 pclk = pll3_clocks.PLL3_Q_Frequency; 801258c: 69fb ldr r3, [r7, #28] 801258e: 63fb str r3, [r7, #60] @ 0x3c break; 8012590: e01f b.n 80125d2 case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 8012592: 4b2d ldr r3, [pc, #180] @ (8012648 ) 8012594: 681b ldr r3, [r3, #0] 8012596: f003 0320 and.w r3, r3, #32 801259a: 2b00 cmp r3, #0 801259c: d009 beq.n 80125b2 { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 801259e: 4b2a ldr r3, [pc, #168] @ (8012648 ) 80125a0: 681b ldr r3, [r3, #0] 80125a2: 08db lsrs r3, r3, #3 80125a4: f003 0303 and.w r3, r3, #3 80125a8: 4a24 ldr r2, [pc, #144] @ (801263c ) 80125aa: fa22 f303 lsr.w r3, r2, r3 80125ae: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 80125b0: e00f b.n 80125d2 pclk = (uint32_t) HSI_VALUE; 80125b2: 4b22 ldr r3, [pc, #136] @ (801263c ) 80125b4: 63fb str r3, [r7, #60] @ 0x3c break; 80125b6: e00c b.n 80125d2 case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 80125b8: 4b21 ldr r3, [pc, #132] @ (8012640 ) 80125ba: 63fb str r3, [r7, #60] @ 0x3c break; 80125bc: e009 b.n 80125d2 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 80125be: f44f 4300 mov.w r3, #32768 @ 0x8000 80125c2: 63fb str r3, [r7, #60] @ 0x3c break; 80125c4: e005 b.n 80125d2 default: pclk = 0U; 80125c6: 2300 movs r3, #0 80125c8: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 80125ca: 2301 movs r3, #1 80125cc: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 80125d0: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 80125d2: 6bfb ldr r3, [r7, #60] @ 0x3c 80125d4: 2b00 cmp r3, #0 80125d6: f000 80e7 beq.w 80127a8 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 80125da: 697b ldr r3, [r7, #20] 80125dc: 6a5b ldr r3, [r3, #36] @ 0x24 80125de: 4a19 ldr r2, [pc, #100] @ (8012644 ) 80125e0: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 80125e4: 461a mov r2, r3 80125e6: 6bfb ldr r3, [r7, #60] @ 0x3c 80125e8: fbb3 f3f2 udiv r3, r3, r2 80125ec: 005a lsls r2, r3, #1 80125ee: 697b ldr r3, [r7, #20] 80125f0: 685b ldr r3, [r3, #4] 80125f2: 085b lsrs r3, r3, #1 80125f4: 441a add r2, r3 80125f6: 697b ldr r3, [r7, #20] 80125f8: 685b ldr r3, [r3, #4] 80125fa: fbb2 f3f3 udiv r3, r2, r3 80125fe: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8012600: 6bbb ldr r3, [r7, #56] @ 0x38 8012602: 2b0f cmp r3, #15 8012604: d916 bls.n 8012634 8012606: 6bbb ldr r3, [r7, #56] @ 0x38 8012608: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 801260c: d212 bcs.n 8012634 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 801260e: 6bbb ldr r3, [r7, #56] @ 0x38 8012610: b29b uxth r3, r3 8012612: f023 030f bic.w r3, r3, #15 8012616: 86fb strh r3, [r7, #54] @ 0x36 brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8012618: 6bbb ldr r3, [r7, #56] @ 0x38 801261a: 085b lsrs r3, r3, #1 801261c: b29b uxth r3, r3 801261e: f003 0307 and.w r3, r3, #7 8012622: b29a uxth r2, r3 8012624: 8efb ldrh r3, [r7, #54] @ 0x36 8012626: 4313 orrs r3, r2 8012628: 86fb strh r3, [r7, #54] @ 0x36 huart->Instance->BRR = brrtemp; 801262a: 697b ldr r3, [r7, #20] 801262c: 681b ldr r3, [r3, #0] 801262e: 8efa ldrh r2, [r7, #54] @ 0x36 8012630: 60da str r2, [r3, #12] 8012632: e0b9 b.n 80127a8 } else { ret = HAL_ERROR; 8012634: 2301 movs r3, #1 8012636: f887 3042 strb.w r3, [r7, #66] @ 0x42 801263a: e0b5 b.n 80127a8 801263c: 03d09000 .word 0x03d09000 8012640: 003d0900 .word 0x003d0900 8012644: 08018724 .word 0x08018724 8012648: 58024400 .word 0x58024400 } } } else { switch (clocksource) 801264c: f897 3043 ldrb.w r3, [r7, #67] @ 0x43 8012650: 2b20 cmp r3, #32 8012652: dc49 bgt.n 80126e8 8012654: 2b00 cmp r3, #0 8012656: db7c blt.n 8012752 8012658: 2b20 cmp r3, #32 801265a: d87a bhi.n 8012752 801265c: a201 add r2, pc, #4 @ (adr r2, 8012664 ) 801265e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8012662: bf00 nop 8012664: 080126ef .word 0x080126ef 8012668: 080126f7 .word 0x080126f7 801266c: 08012753 .word 0x08012753 8012670: 08012753 .word 0x08012753 8012674: 080126ff .word 0x080126ff 8012678: 08012753 .word 0x08012753 801267c: 08012753 .word 0x08012753 8012680: 08012753 .word 0x08012753 8012684: 0801270f .word 0x0801270f 8012688: 08012753 .word 0x08012753 801268c: 08012753 .word 0x08012753 8012690: 08012753 .word 0x08012753 8012694: 08012753 .word 0x08012753 8012698: 08012753 .word 0x08012753 801269c: 08012753 .word 0x08012753 80126a0: 08012753 .word 0x08012753 80126a4: 0801271f .word 0x0801271f 80126a8: 08012753 .word 0x08012753 80126ac: 08012753 .word 0x08012753 80126b0: 08012753 .word 0x08012753 80126b4: 08012753 .word 0x08012753 80126b8: 08012753 .word 0x08012753 80126bc: 08012753 .word 0x08012753 80126c0: 08012753 .word 0x08012753 80126c4: 08012753 .word 0x08012753 80126c8: 08012753 .word 0x08012753 80126cc: 08012753 .word 0x08012753 80126d0: 08012753 .word 0x08012753 80126d4: 08012753 .word 0x08012753 80126d8: 08012753 .word 0x08012753 80126dc: 08012753 .word 0x08012753 80126e0: 08012753 .word 0x08012753 80126e4: 08012745 .word 0x08012745 80126e8: 2b40 cmp r3, #64 @ 0x40 80126ea: d02e beq.n 801274a 80126ec: e031 b.n 8012752 { case UART_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 80126ee: f7fa f8e9 bl 800c8c4 80126f2: 63f8 str r0, [r7, #60] @ 0x3c break; 80126f4: e033 b.n 801275e case UART_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); 80126f6: f7fa f8fb bl 800c8f0 80126fa: 63f8 str r0, [r7, #60] @ 0x3c break; 80126fc: e02f b.n 801275e case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); 80126fe: f107 0324 add.w r3, r7, #36 @ 0x24 8012702: 4618 mov r0, r3 8012704: f7fc f8d0 bl 800e8a8 pclk = pll2_clocks.PLL2_Q_Frequency; 8012708: 6abb ldr r3, [r7, #40] @ 0x28 801270a: 63fb str r3, [r7, #60] @ 0x3c break; 801270c: e027 b.n 801275e case UART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); 801270e: f107 0318 add.w r3, r7, #24 8012712: 4618 mov r0, r3 8012714: f7fc fa1c bl 800eb50 pclk = pll3_clocks.PLL3_Q_Frequency; 8012718: 69fb ldr r3, [r7, #28] 801271a: 63fb str r3, [r7, #60] @ 0x3c break; 801271c: e01f b.n 801275e case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) 801271e: 4b2d ldr r3, [pc, #180] @ (80127d4 ) 8012720: 681b ldr r3, [r3, #0] 8012722: f003 0320 and.w r3, r3, #32 8012726: 2b00 cmp r3, #0 8012728: d009 beq.n 801273e { pclk = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)); 801272a: 4b2a ldr r3, [pc, #168] @ (80127d4 ) 801272c: 681b ldr r3, [r3, #0] 801272e: 08db lsrs r3, r3, #3 8012730: f003 0303 and.w r3, r3, #3 8012734: 4a28 ldr r2, [pc, #160] @ (80127d8 ) 8012736: fa22 f303 lsr.w r3, r2, r3 801273a: 63fb str r3, [r7, #60] @ 0x3c } else { pclk = (uint32_t) HSI_VALUE; } break; 801273c: e00f b.n 801275e pclk = (uint32_t) HSI_VALUE; 801273e: 4b26 ldr r3, [pc, #152] @ (80127d8 ) 8012740: 63fb str r3, [r7, #60] @ 0x3c break; 8012742: e00c b.n 801275e case UART_CLOCKSOURCE_CSI: pclk = (uint32_t) CSI_VALUE; 8012744: 4b25 ldr r3, [pc, #148] @ (80127dc ) 8012746: 63fb str r3, [r7, #60] @ 0x3c break; 8012748: e009 b.n 801275e case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 801274a: f44f 4300 mov.w r3, #32768 @ 0x8000 801274e: 63fb str r3, [r7, #60] @ 0x3c break; 8012750: e005 b.n 801275e default: pclk = 0U; 8012752: 2300 movs r3, #0 8012754: 63fb str r3, [r7, #60] @ 0x3c ret = HAL_ERROR; 8012756: 2301 movs r3, #1 8012758: f887 3042 strb.w r3, [r7, #66] @ 0x42 break; 801275c: bf00 nop } if (pclk != 0U) 801275e: 6bfb ldr r3, [r7, #60] @ 0x3c 8012760: 2b00 cmp r3, #0 8012762: d021 beq.n 80127a8 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8012764: 697b ldr r3, [r7, #20] 8012766: 6a5b ldr r3, [r3, #36] @ 0x24 8012768: 4a1d ldr r2, [pc, #116] @ (80127e0 ) 801276a: f832 3013 ldrh.w r3, [r2, r3, lsl #1] 801276e: 461a mov r2, r3 8012770: 6bfb ldr r3, [r7, #60] @ 0x3c 8012772: fbb3 f2f2 udiv r2, r3, r2 8012776: 697b ldr r3, [r7, #20] 8012778: 685b ldr r3, [r3, #4] 801277a: 085b lsrs r3, r3, #1 801277c: 441a add r2, r3 801277e: 697b ldr r3, [r7, #20] 8012780: 685b ldr r3, [r3, #4] 8012782: fbb2 f3f3 udiv r3, r2, r3 8012786: 63bb str r3, [r7, #56] @ 0x38 if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8012788: 6bbb ldr r3, [r7, #56] @ 0x38 801278a: 2b0f cmp r3, #15 801278c: d909 bls.n 80127a2 801278e: 6bbb ldr r3, [r7, #56] @ 0x38 8012790: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8012794: d205 bcs.n 80127a2 { huart->Instance->BRR = (uint16_t)usartdiv; 8012796: 6bbb ldr r3, [r7, #56] @ 0x38 8012798: b29a uxth r2, r3 801279a: 697b ldr r3, [r7, #20] 801279c: 681b ldr r3, [r3, #0] 801279e: 60da str r2, [r3, #12] 80127a0: e002 b.n 80127a8 } else { ret = HAL_ERROR; 80127a2: 2301 movs r3, #1 80127a4: f887 3042 strb.w r3, [r7, #66] @ 0x42 } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 80127a8: 697b ldr r3, [r7, #20] 80127aa: 2201 movs r2, #1 80127ac: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1; 80127b0: 697b ldr r3, [r7, #20] 80127b2: 2201 movs r2, #1 80127b4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 /* Clear ISR function pointers */ huart->RxISR = NULL; 80127b8: 697b ldr r3, [r7, #20] 80127ba: 2200 movs r2, #0 80127bc: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 80127be: 697b ldr r3, [r7, #20] 80127c0: 2200 movs r2, #0 80127c2: 679a str r2, [r3, #120] @ 0x78 return ret; 80127c4: f897 3042 ldrb.w r3, [r7, #66] @ 0x42 } 80127c8: 4618 mov r0, r3 80127ca: 3748 adds r7, #72 @ 0x48 80127cc: 46bd mov sp, r7 80127ce: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80127d2: bf00 nop 80127d4: 58024400 .word 0x58024400 80127d8: 03d09000 .word 0x03d09000 80127dc: 003d0900 .word 0x003d0900 80127e0: 08018724 .word 0x08018724 080127e4 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 80127e4: b480 push {r7} 80127e6: b083 sub sp, #12 80127e8: af00 add r7, sp, #0 80127ea: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 80127ec: 687b ldr r3, [r7, #4] 80127ee: 6a9b ldr r3, [r3, #40] @ 0x28 80127f0: f003 0308 and.w r3, r3, #8 80127f4: 2b00 cmp r3, #0 80127f6: d00a beq.n 801280e { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 80127f8: 687b ldr r3, [r7, #4] 80127fa: 681b ldr r3, [r3, #0] 80127fc: 685b ldr r3, [r3, #4] 80127fe: f423 4100 bic.w r1, r3, #32768 @ 0x8000 8012802: 687b ldr r3, [r7, #4] 8012804: 6b9a ldr r2, [r3, #56] @ 0x38 8012806: 687b ldr r3, [r7, #4] 8012808: 681b ldr r3, [r3, #0] 801280a: 430a orrs r2, r1 801280c: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 801280e: 687b ldr r3, [r7, #4] 8012810: 6a9b ldr r3, [r3, #40] @ 0x28 8012812: f003 0301 and.w r3, r3, #1 8012816: 2b00 cmp r3, #0 8012818: d00a beq.n 8012830 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 801281a: 687b ldr r3, [r7, #4] 801281c: 681b ldr r3, [r3, #0] 801281e: 685b ldr r3, [r3, #4] 8012820: f423 3100 bic.w r1, r3, #131072 @ 0x20000 8012824: 687b ldr r3, [r7, #4] 8012826: 6ada ldr r2, [r3, #44] @ 0x2c 8012828: 687b ldr r3, [r7, #4] 801282a: 681b ldr r3, [r3, #0] 801282c: 430a orrs r2, r1 801282e: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 8012830: 687b ldr r3, [r7, #4] 8012832: 6a9b ldr r3, [r3, #40] @ 0x28 8012834: f003 0302 and.w r3, r3, #2 8012838: 2b00 cmp r3, #0 801283a: d00a beq.n 8012852 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 801283c: 687b ldr r3, [r7, #4] 801283e: 681b ldr r3, [r3, #0] 8012840: 685b ldr r3, [r3, #4] 8012842: f423 3180 bic.w r1, r3, #65536 @ 0x10000 8012846: 687b ldr r3, [r7, #4] 8012848: 6b1a ldr r2, [r3, #48] @ 0x30 801284a: 687b ldr r3, [r7, #4] 801284c: 681b ldr r3, [r3, #0] 801284e: 430a orrs r2, r1 8012850: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 8012852: 687b ldr r3, [r7, #4] 8012854: 6a9b ldr r3, [r3, #40] @ 0x28 8012856: f003 0304 and.w r3, r3, #4 801285a: 2b00 cmp r3, #0 801285c: d00a beq.n 8012874 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 801285e: 687b ldr r3, [r7, #4] 8012860: 681b ldr r3, [r3, #0] 8012862: 685b ldr r3, [r3, #4] 8012864: f423 2180 bic.w r1, r3, #262144 @ 0x40000 8012868: 687b ldr r3, [r7, #4] 801286a: 6b5a ldr r2, [r3, #52] @ 0x34 801286c: 687b ldr r3, [r7, #4] 801286e: 681b ldr r3, [r3, #0] 8012870: 430a orrs r2, r1 8012872: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 8012874: 687b ldr r3, [r7, #4] 8012876: 6a9b ldr r3, [r3, #40] @ 0x28 8012878: f003 0310 and.w r3, r3, #16 801287c: 2b00 cmp r3, #0 801287e: d00a beq.n 8012896 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 8012880: 687b ldr r3, [r7, #4] 8012882: 681b ldr r3, [r3, #0] 8012884: 689b ldr r3, [r3, #8] 8012886: f423 5180 bic.w r1, r3, #4096 @ 0x1000 801288a: 687b ldr r3, [r7, #4] 801288c: 6bda ldr r2, [r3, #60] @ 0x3c 801288e: 687b ldr r3, [r7, #4] 8012890: 681b ldr r3, [r3, #0] 8012892: 430a orrs r2, r1 8012894: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 8012896: 687b ldr r3, [r7, #4] 8012898: 6a9b ldr r3, [r3, #40] @ 0x28 801289a: f003 0320 and.w r3, r3, #32 801289e: 2b00 cmp r3, #0 80128a0: d00a beq.n 80128b8 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 80128a2: 687b ldr r3, [r7, #4] 80128a4: 681b ldr r3, [r3, #0] 80128a6: 689b ldr r3, [r3, #8] 80128a8: f423 5100 bic.w r1, r3, #8192 @ 0x2000 80128ac: 687b ldr r3, [r7, #4] 80128ae: 6c1a ldr r2, [r3, #64] @ 0x40 80128b0: 687b ldr r3, [r7, #4] 80128b2: 681b ldr r3, [r3, #0] 80128b4: 430a orrs r2, r1 80128b6: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 80128b8: 687b ldr r3, [r7, #4] 80128ba: 6a9b ldr r3, [r3, #40] @ 0x28 80128bc: f003 0340 and.w r3, r3, #64 @ 0x40 80128c0: 2b00 cmp r3, #0 80128c2: d01a beq.n 80128fa { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 80128c4: 687b ldr r3, [r7, #4] 80128c6: 681b ldr r3, [r3, #0] 80128c8: 685b ldr r3, [r3, #4] 80128ca: f423 1180 bic.w r1, r3, #1048576 @ 0x100000 80128ce: 687b ldr r3, [r7, #4] 80128d0: 6c5a ldr r2, [r3, #68] @ 0x44 80128d2: 687b ldr r3, [r7, #4] 80128d4: 681b ldr r3, [r3, #0] 80128d6: 430a orrs r2, r1 80128d8: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 80128da: 687b ldr r3, [r7, #4] 80128dc: 6c5b ldr r3, [r3, #68] @ 0x44 80128de: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80128e2: d10a bne.n 80128fa { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 80128e4: 687b ldr r3, [r7, #4] 80128e6: 681b ldr r3, [r3, #0] 80128e8: 685b ldr r3, [r3, #4] 80128ea: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000 80128ee: 687b ldr r3, [r7, #4] 80128f0: 6c9a ldr r2, [r3, #72] @ 0x48 80128f2: 687b ldr r3, [r7, #4] 80128f4: 681b ldr r3, [r3, #0] 80128f6: 430a orrs r2, r1 80128f8: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 80128fa: 687b ldr r3, [r7, #4] 80128fc: 6a9b ldr r3, [r3, #40] @ 0x28 80128fe: f003 0380 and.w r3, r3, #128 @ 0x80 8012902: 2b00 cmp r3, #0 8012904: d00a beq.n 801291c { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8012906: 687b ldr r3, [r7, #4] 8012908: 681b ldr r3, [r3, #0] 801290a: 685b ldr r3, [r3, #4] 801290c: f423 2100 bic.w r1, r3, #524288 @ 0x80000 8012910: 687b ldr r3, [r7, #4] 8012912: 6cda ldr r2, [r3, #76] @ 0x4c 8012914: 687b ldr r3, [r7, #4] 8012916: 681b ldr r3, [r3, #0] 8012918: 430a orrs r2, r1 801291a: 605a str r2, [r3, #4] } } 801291c: bf00 nop 801291e: 370c adds r7, #12 8012920: 46bd mov sp, r7 8012922: f85d 7b04 ldr.w r7, [sp], #4 8012926: 4770 bx lr 08012928 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8012928: b580 push {r7, lr} 801292a: b098 sub sp, #96 @ 0x60 801292c: af02 add r7, sp, #8 801292e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8012930: 687b ldr r3, [r7, #4] 8012932: 2200 movs r2, #0 8012934: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8012938: f7f3 fa74 bl 8005e24 801293c: 6578 str r0, [r7, #84] @ 0x54 /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 801293e: 687b ldr r3, [r7, #4] 8012940: 681b ldr r3, [r3, #0] 8012942: 681b ldr r3, [r3, #0] 8012944: f003 0308 and.w r3, r3, #8 8012948: 2b08 cmp r3, #8 801294a: d12f bne.n 80129ac { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 801294c: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 8012950: 9300 str r3, [sp, #0] 8012952: 6d7b ldr r3, [r7, #84] @ 0x54 8012954: 2200 movs r2, #0 8012956: f44f 1100 mov.w r1, #2097152 @ 0x200000 801295a: 6878 ldr r0, [r7, #4] 801295c: f000 f88e bl 8012a7c 8012960: 4603 mov r3, r0 8012962: 2b00 cmp r3, #0 8012964: d022 beq.n 80129ac { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 8012966: 687b ldr r3, [r7, #4] 8012968: 681b ldr r3, [r3, #0] 801296a: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801296c: 6bbb ldr r3, [r7, #56] @ 0x38 801296e: e853 3f00 ldrex r3, [r3] 8012972: 637b str r3, [r7, #52] @ 0x34 return(result); 8012974: 6b7b ldr r3, [r7, #52] @ 0x34 8012976: f023 0380 bic.w r3, r3, #128 @ 0x80 801297a: 653b str r3, [r7, #80] @ 0x50 801297c: 687b ldr r3, [r7, #4] 801297e: 681b ldr r3, [r3, #0] 8012980: 461a mov r2, r3 8012982: 6d3b ldr r3, [r7, #80] @ 0x50 8012984: 647b str r3, [r7, #68] @ 0x44 8012986: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012988: 6c39 ldr r1, [r7, #64] @ 0x40 801298a: 6c7a ldr r2, [r7, #68] @ 0x44 801298c: e841 2300 strex r3, r2, [r1] 8012990: 63fb str r3, [r7, #60] @ 0x3c return(result); 8012992: 6bfb ldr r3, [r7, #60] @ 0x3c 8012994: 2b00 cmp r3, #0 8012996: d1e6 bne.n 8012966 huart->gState = HAL_UART_STATE_READY; 8012998: 687b ldr r3, [r7, #4] 801299a: 2220 movs r2, #32 801299c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 __HAL_UNLOCK(huart); 80129a0: 687b ldr r3, [r7, #4] 80129a2: 2200 movs r2, #0 80129a4: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 80129a8: 2303 movs r3, #3 80129aa: e063 b.n 8012a74 } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 80129ac: 687b ldr r3, [r7, #4] 80129ae: 681b ldr r3, [r3, #0] 80129b0: 681b ldr r3, [r3, #0] 80129b2: f003 0304 and.w r3, r3, #4 80129b6: 2b04 cmp r3, #4 80129b8: d149 bne.n 8012a4e { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 80129ba: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000 80129be: 9300 str r3, [sp, #0] 80129c0: 6d7b ldr r3, [r7, #84] @ 0x54 80129c2: 2200 movs r2, #0 80129c4: f44f 0180 mov.w r1, #4194304 @ 0x400000 80129c8: 6878 ldr r0, [r7, #4] 80129ca: f000 f857 bl 8012a7c 80129ce: 4603 mov r3, r0 80129d0: 2b00 cmp r3, #0 80129d2: d03c beq.n 8012a4e { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 80129d4: 687b ldr r3, [r7, #4] 80129d6: 681b ldr r3, [r3, #0] 80129d8: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80129da: 6a7b ldr r3, [r7, #36] @ 0x24 80129dc: e853 3f00 ldrex r3, [r3] 80129e0: 623b str r3, [r7, #32] return(result); 80129e2: 6a3b ldr r3, [r7, #32] 80129e4: f423 7390 bic.w r3, r3, #288 @ 0x120 80129e8: 64fb str r3, [r7, #76] @ 0x4c 80129ea: 687b ldr r3, [r7, #4] 80129ec: 681b ldr r3, [r3, #0] 80129ee: 461a mov r2, r3 80129f0: 6cfb ldr r3, [r7, #76] @ 0x4c 80129f2: 633b str r3, [r7, #48] @ 0x30 80129f4: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80129f6: 6af9 ldr r1, [r7, #44] @ 0x2c 80129f8: 6b3a ldr r2, [r7, #48] @ 0x30 80129fa: e841 2300 strex r3, r2, [r1] 80129fe: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012a00: 6abb ldr r3, [r7, #40] @ 0x28 8012a02: 2b00 cmp r3, #0 8012a04: d1e6 bne.n 80129d4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012a06: 687b ldr r3, [r7, #4] 8012a08: 681b ldr r3, [r3, #0] 8012a0a: 3308 adds r3, #8 8012a0c: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012a0e: 693b ldr r3, [r7, #16] 8012a10: e853 3f00 ldrex r3, [r3] 8012a14: 60fb str r3, [r7, #12] return(result); 8012a16: 68fb ldr r3, [r7, #12] 8012a18: f023 0301 bic.w r3, r3, #1 8012a1c: 64bb str r3, [r7, #72] @ 0x48 8012a1e: 687b ldr r3, [r7, #4] 8012a20: 681b ldr r3, [r3, #0] 8012a22: 3308 adds r3, #8 8012a24: 6cba ldr r2, [r7, #72] @ 0x48 8012a26: 61fa str r2, [r7, #28] 8012a28: 61bb str r3, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012a2a: 69b9 ldr r1, [r7, #24] 8012a2c: 69fa ldr r2, [r7, #28] 8012a2e: e841 2300 strex r3, r2, [r1] 8012a32: 617b str r3, [r7, #20] return(result); 8012a34: 697b ldr r3, [r7, #20] 8012a36: 2b00 cmp r3, #0 8012a38: d1e5 bne.n 8012a06 huart->RxState = HAL_UART_STATE_READY; 8012a3a: 687b ldr r3, [r7, #4] 8012a3c: 2220 movs r2, #32 8012a3e: f8c3 208c str.w r2, [r3, #140] @ 0x8c __HAL_UNLOCK(huart); 8012a42: 687b ldr r3, [r7, #4] 8012a44: 2200 movs r2, #0 8012a46: f883 2084 strb.w r2, [r3, #132] @ 0x84 /* Timeout occurred */ return HAL_TIMEOUT; 8012a4a: 2303 movs r3, #3 8012a4c: e012 b.n 8012a74 } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8012a4e: 687b ldr r3, [r7, #4] 8012a50: 2220 movs r2, #32 8012a52: f8c3 2088 str.w r2, [r3, #136] @ 0x88 huart->RxState = HAL_UART_STATE_READY; 8012a56: 687b ldr r3, [r7, #4] 8012a58: 2220 movs r2, #32 8012a5a: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012a5e: 687b ldr r3, [r7, #4] 8012a60: 2200 movs r2, #0 8012a62: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8012a64: 687b ldr r3, [r7, #4] 8012a66: 2200 movs r2, #0 8012a68: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 8012a6a: 687b ldr r3, [r7, #4] 8012a6c: 2200 movs r2, #0 8012a6e: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8012a72: 2300 movs r3, #0 } 8012a74: 4618 mov r0, r3 8012a76: 3758 adds r7, #88 @ 0x58 8012a78: 46bd mov sp, r7 8012a7a: bd80 pop {r7, pc} 08012a7c : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 8012a7c: b580 push {r7, lr} 8012a7e: b084 sub sp, #16 8012a80: af00 add r7, sp, #0 8012a82: 60f8 str r0, [r7, #12] 8012a84: 60b9 str r1, [r7, #8] 8012a86: 603b str r3, [r7, #0] 8012a88: 4613 mov r3, r2 8012a8a: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012a8c: e04f b.n 8012b2e { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 8012a8e: 69bb ldr r3, [r7, #24] 8012a90: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8012a94: d04b beq.n 8012b2e { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 8012a96: f7f3 f9c5 bl 8005e24 8012a9a: 4602 mov r2, r0 8012a9c: 683b ldr r3, [r7, #0] 8012a9e: 1ad3 subs r3, r2, r3 8012aa0: 69ba ldr r2, [r7, #24] 8012aa2: 429a cmp r2, r3 8012aa4: d302 bcc.n 8012aac 8012aa6: 69bb ldr r3, [r7, #24] 8012aa8: 2b00 cmp r3, #0 8012aaa: d101 bne.n 8012ab0 { return HAL_TIMEOUT; 8012aac: 2303 movs r3, #3 8012aae: e04e b.n 8012b4e } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 8012ab0: 68fb ldr r3, [r7, #12] 8012ab2: 681b ldr r3, [r3, #0] 8012ab4: 681b ldr r3, [r3, #0] 8012ab6: f003 0304 and.w r3, r3, #4 8012aba: 2b00 cmp r3, #0 8012abc: d037 beq.n 8012b2e 8012abe: 68bb ldr r3, [r7, #8] 8012ac0: 2b80 cmp r3, #128 @ 0x80 8012ac2: d034 beq.n 8012b2e 8012ac4: 68bb ldr r3, [r7, #8] 8012ac6: 2b40 cmp r3, #64 @ 0x40 8012ac8: d031 beq.n 8012b2e { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8012aca: 68fb ldr r3, [r7, #12] 8012acc: 681b ldr r3, [r3, #0] 8012ace: 69db ldr r3, [r3, #28] 8012ad0: f003 0308 and.w r3, r3, #8 8012ad4: 2b08 cmp r3, #8 8012ad6: d110 bne.n 8012afa { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8012ad8: 68fb ldr r3, [r7, #12] 8012ada: 681b ldr r3, [r3, #0] 8012adc: 2208 movs r2, #8 8012ade: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012ae0: 68f8 ldr r0, [r7, #12] 8012ae2: f000 f95b bl 8012d9c huart->ErrorCode = HAL_UART_ERROR_ORE; 8012ae6: 68fb ldr r3, [r7, #12] 8012ae8: 2208 movs r2, #8 8012aea: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012aee: 68fb ldr r3, [r7, #12] 8012af0: 2200 movs r2, #0 8012af2: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_ERROR; 8012af6: 2301 movs r3, #1 8012af8: e029 b.n 8012b4e } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8012afa: 68fb ldr r3, [r7, #12] 8012afc: 681b ldr r3, [r3, #0] 8012afe: 69db ldr r3, [r3, #28] 8012b00: f403 6300 and.w r3, r3, #2048 @ 0x800 8012b04: f5b3 6f00 cmp.w r3, #2048 @ 0x800 8012b08: d111 bne.n 8012b2e { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 8012b0a: 68fb ldr r3, [r7, #12] 8012b0c: 681b ldr r3, [r3, #0] 8012b0e: f44f 6200 mov.w r2, #2048 @ 0x800 8012b12: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8012b14: 68f8 ldr r0, [r7, #12] 8012b16: f000 f941 bl 8012d9c huart->ErrorCode = HAL_UART_ERROR_RTO; 8012b1a: 68fb ldr r3, [r7, #12] 8012b1c: 2220 movs r2, #32 8012b1e: f8c3 2090 str.w r2, [r3, #144] @ 0x90 /* Process Unlocked */ __HAL_UNLOCK(huart); 8012b22: 68fb ldr r3, [r7, #12] 8012b24: 2200 movs r2, #0 8012b26: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_TIMEOUT; 8012b2a: 2303 movs r3, #3 8012b2c: e00f b.n 8012b4e while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8012b2e: 68fb ldr r3, [r7, #12] 8012b30: 681b ldr r3, [r3, #0] 8012b32: 69da ldr r2, [r3, #28] 8012b34: 68bb ldr r3, [r7, #8] 8012b36: 4013 ands r3, r2 8012b38: 68ba ldr r2, [r7, #8] 8012b3a: 429a cmp r2, r3 8012b3c: bf0c ite eq 8012b3e: 2301 moveq r3, #1 8012b40: 2300 movne r3, #0 8012b42: b2db uxtb r3, r3 8012b44: 461a mov r2, r3 8012b46: 79fb ldrb r3, [r7, #7] 8012b48: 429a cmp r2, r3 8012b4a: d0a0 beq.n 8012a8e } } } } return HAL_OK; 8012b4c: 2300 movs r3, #0 } 8012b4e: 4618 mov r0, r3 8012b50: 3710 adds r7, #16 8012b52: 46bd mov sp, r7 8012b54: bd80 pop {r7, pc} ... 08012b58 : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8012b58: b480 push {r7} 8012b5a: b0a3 sub sp, #140 @ 0x8c 8012b5c: af00 add r7, sp, #0 8012b5e: 60f8 str r0, [r7, #12] 8012b60: 60b9 str r1, [r7, #8] 8012b62: 4613 mov r3, r2 8012b64: 80fb strh r3, [r7, #6] huart->pRxBuffPtr = pData; 8012b66: 68fb ldr r3, [r7, #12] 8012b68: 68ba ldr r2, [r7, #8] 8012b6a: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 8012b6c: 68fb ldr r3, [r7, #12] 8012b6e: 88fa ldrh r2, [r7, #6] 8012b70: f8a3 205c strh.w r2, [r3, #92] @ 0x5c huart->RxXferCount = Size; 8012b74: 68fb ldr r3, [r7, #12] 8012b76: 88fa ldrh r2, [r7, #6] 8012b78: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->RxISR = NULL; 8012b7c: 68fb ldr r3, [r7, #12] 8012b7e: 2200 movs r2, #0 8012b80: 675a str r2, [r3, #116] @ 0x74 /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); 8012b82: 68fb ldr r3, [r7, #12] 8012b84: 689b ldr r3, [r3, #8] 8012b86: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012b8a: d10e bne.n 8012baa 8012b8c: 68fb ldr r3, [r7, #12] 8012b8e: 691b ldr r3, [r3, #16] 8012b90: 2b00 cmp r3, #0 8012b92: d105 bne.n 8012ba0 8012b94: 68fb ldr r3, [r7, #12] 8012b96: f240 12ff movw r2, #511 @ 0x1ff 8012b9a: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012b9e: e02d b.n 8012bfc 8012ba0: 68fb ldr r3, [r7, #12] 8012ba2: 22ff movs r2, #255 @ 0xff 8012ba4: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012ba8: e028 b.n 8012bfc 8012baa: 68fb ldr r3, [r7, #12] 8012bac: 689b ldr r3, [r3, #8] 8012bae: 2b00 cmp r3, #0 8012bb0: d10d bne.n 8012bce 8012bb2: 68fb ldr r3, [r7, #12] 8012bb4: 691b ldr r3, [r3, #16] 8012bb6: 2b00 cmp r3, #0 8012bb8: d104 bne.n 8012bc4 8012bba: 68fb ldr r3, [r7, #12] 8012bbc: 22ff movs r2, #255 @ 0xff 8012bbe: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012bc2: e01b b.n 8012bfc 8012bc4: 68fb ldr r3, [r7, #12] 8012bc6: 227f movs r2, #127 @ 0x7f 8012bc8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012bcc: e016 b.n 8012bfc 8012bce: 68fb ldr r3, [r7, #12] 8012bd0: 689b ldr r3, [r3, #8] 8012bd2: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000 8012bd6: d10d bne.n 8012bf4 8012bd8: 68fb ldr r3, [r7, #12] 8012bda: 691b ldr r3, [r3, #16] 8012bdc: 2b00 cmp r3, #0 8012bde: d104 bne.n 8012bea 8012be0: 68fb ldr r3, [r7, #12] 8012be2: 227f movs r2, #127 @ 0x7f 8012be4: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012be8: e008 b.n 8012bfc 8012bea: 68fb ldr r3, [r7, #12] 8012bec: 223f movs r2, #63 @ 0x3f 8012bee: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 8012bf2: e003 b.n 8012bfc 8012bf4: 68fb ldr r3, [r7, #12] 8012bf6: 2200 movs r2, #0 8012bf8: f8a3 2060 strh.w r2, [r3, #96] @ 0x60 huart->ErrorCode = HAL_UART_ERROR_NONE; 8012bfc: 68fb ldr r3, [r7, #12] 8012bfe: 2200 movs r2, #0 8012c00: f8c3 2090 str.w r2, [r3, #144] @ 0x90 huart->RxState = HAL_UART_STATE_BUSY_RX; 8012c04: 68fb ldr r3, [r7, #12] 8012c06: 2222 movs r2, #34 @ 0x22 8012c08: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8012c0c: 68fb ldr r3, [r7, #12] 8012c0e: 681b ldr r3, [r3, #0] 8012c10: 3308 adds r3, #8 8012c12: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c14: 6e7b ldr r3, [r7, #100] @ 0x64 8012c16: e853 3f00 ldrex r3, [r3] 8012c1a: 663b str r3, [r7, #96] @ 0x60 return(result); 8012c1c: 6e3b ldr r3, [r7, #96] @ 0x60 8012c1e: f043 0301 orr.w r3, r3, #1 8012c22: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8012c26: 68fb ldr r3, [r7, #12] 8012c28: 681b ldr r3, [r3, #0] 8012c2a: 3308 adds r3, #8 8012c2c: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 8012c30: 673a str r2, [r7, #112] @ 0x70 8012c32: 66fb str r3, [r7, #108] @ 0x6c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012c34: 6ef9 ldr r1, [r7, #108] @ 0x6c 8012c36: 6f3a ldr r2, [r7, #112] @ 0x70 8012c38: e841 2300 strex r3, r2, [r1] 8012c3c: 66bb str r3, [r7, #104] @ 0x68 return(result); 8012c3e: 6ebb ldr r3, [r7, #104] @ 0x68 8012c40: 2b00 cmp r3, #0 8012c42: d1e3 bne.n 8012c0c /* Configure Rx interrupt processing */ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) 8012c44: 68fb ldr r3, [r7, #12] 8012c46: 6e5b ldr r3, [r3, #100] @ 0x64 8012c48: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8012c4c: d14f bne.n 8012cee 8012c4e: 68fb ldr r3, [r7, #12] 8012c50: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8012c54: 88fa ldrh r2, [r7, #6] 8012c56: 429a cmp r2, r3 8012c58: d349 bcc.n 8012cee { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012c5a: 68fb ldr r3, [r7, #12] 8012c5c: 689b ldr r3, [r3, #8] 8012c5e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012c62: d107 bne.n 8012c74 8012c64: 68fb ldr r3, [r7, #12] 8012c66: 691b ldr r3, [r3, #16] 8012c68: 2b00 cmp r3, #0 8012c6a: d103 bne.n 8012c74 { huart->RxISR = UART_RxISR_16BIT_FIFOEN; 8012c6c: 68fb ldr r3, [r7, #12] 8012c6e: 4a47 ldr r2, [pc, #284] @ (8012d8c ) 8012c70: 675a str r2, [r3, #116] @ 0x74 8012c72: e002 b.n 8012c7a } else { huart->RxISR = UART_RxISR_8BIT_FIFOEN; 8012c74: 68fb ldr r3, [r7, #12] 8012c76: 4a46 ldr r2, [pc, #280] @ (8012d90 ) 8012c78: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012c7a: 68fb ldr r3, [r7, #12] 8012c7c: 691b ldr r3, [r3, #16] 8012c7e: 2b00 cmp r3, #0 8012c80: d01a beq.n 8012cb8 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8012c82: 68fb ldr r3, [r7, #12] 8012c84: 681b ldr r3, [r3, #0] 8012c86: 653b str r3, [r7, #80] @ 0x50 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012c88: 6d3b ldr r3, [r7, #80] @ 0x50 8012c8a: e853 3f00 ldrex r3, [r3] 8012c8e: 64fb str r3, [r7, #76] @ 0x4c return(result); 8012c90: 6cfb ldr r3, [r7, #76] @ 0x4c 8012c92: f443 7380 orr.w r3, r3, #256 @ 0x100 8012c96: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8012c9a: 68fb ldr r3, [r7, #12] 8012c9c: 681b ldr r3, [r3, #0] 8012c9e: 461a mov r2, r3 8012ca0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 8012ca4: 65fb str r3, [r7, #92] @ 0x5c 8012ca6: 65ba str r2, [r7, #88] @ 0x58 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ca8: 6db9 ldr r1, [r7, #88] @ 0x58 8012caa: 6dfa ldr r2, [r7, #92] @ 0x5c 8012cac: e841 2300 strex r3, r2, [r1] 8012cb0: 657b str r3, [r7, #84] @ 0x54 return(result); 8012cb2: 6d7b ldr r3, [r7, #84] @ 0x54 8012cb4: 2b00 cmp r3, #0 8012cb6: d1e4 bne.n 8012c82 } ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8012cb8: 68fb ldr r3, [r7, #12] 8012cba: 681b ldr r3, [r3, #0] 8012cbc: 3308 adds r3, #8 8012cbe: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012cc0: 6bfb ldr r3, [r7, #60] @ 0x3c 8012cc2: e853 3f00 ldrex r3, [r3] 8012cc6: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012cc8: 6bbb ldr r3, [r7, #56] @ 0x38 8012cca: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8012cce: 67fb str r3, [r7, #124] @ 0x7c 8012cd0: 68fb ldr r3, [r7, #12] 8012cd2: 681b ldr r3, [r3, #0] 8012cd4: 3308 adds r3, #8 8012cd6: 6ffa ldr r2, [r7, #124] @ 0x7c 8012cd8: 64ba str r2, [r7, #72] @ 0x48 8012cda: 647b str r3, [r7, #68] @ 0x44 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012cdc: 6c79 ldr r1, [r7, #68] @ 0x44 8012cde: 6cba ldr r2, [r7, #72] @ 0x48 8012ce0: e841 2300 strex r3, r2, [r1] 8012ce4: 643b str r3, [r7, #64] @ 0x40 return(result); 8012ce6: 6c3b ldr r3, [r7, #64] @ 0x40 8012ce8: 2b00 cmp r3, #0 8012cea: d1e5 bne.n 8012cb8 8012cec: e046 b.n 8012d7c } else { /* Set the Rx ISR function pointer according to the data word length */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8012cee: 68fb ldr r3, [r7, #12] 8012cf0: 689b ldr r3, [r3, #8] 8012cf2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8012cf6: d107 bne.n 8012d08 8012cf8: 68fb ldr r3, [r7, #12] 8012cfa: 691b ldr r3, [r3, #16] 8012cfc: 2b00 cmp r3, #0 8012cfe: d103 bne.n 8012d08 { huart->RxISR = UART_RxISR_16BIT; 8012d00: 68fb ldr r3, [r7, #12] 8012d02: 4a24 ldr r2, [pc, #144] @ (8012d94 ) 8012d04: 675a str r2, [r3, #116] @ 0x74 8012d06: e002 b.n 8012d0e } else { huart->RxISR = UART_RxISR_8BIT; 8012d08: 68fb ldr r3, [r7, #12] 8012d0a: 4a23 ldr r2, [pc, #140] @ (8012d98 ) 8012d0c: 675a str r2, [r3, #116] @ 0x74 } /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8012d0e: 68fb ldr r3, [r7, #12] 8012d10: 691b ldr r3, [r3, #16] 8012d12: 2b00 cmp r3, #0 8012d14: d019 beq.n 8012d4a { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); 8012d16: 68fb ldr r3, [r7, #12] 8012d18: 681b ldr r3, [r3, #0] 8012d1a: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d1c: 6abb ldr r3, [r7, #40] @ 0x28 8012d1e: e853 3f00 ldrex r3, [r3] 8012d22: 627b str r3, [r7, #36] @ 0x24 return(result); 8012d24: 6a7b ldr r3, [r7, #36] @ 0x24 8012d26: f443 7390 orr.w r3, r3, #288 @ 0x120 8012d2a: 677b str r3, [r7, #116] @ 0x74 8012d2c: 68fb ldr r3, [r7, #12] 8012d2e: 681b ldr r3, [r3, #0] 8012d30: 461a mov r2, r3 8012d32: 6f7b ldr r3, [r7, #116] @ 0x74 8012d34: 637b str r3, [r7, #52] @ 0x34 8012d36: 633a str r2, [r7, #48] @ 0x30 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d38: 6b39 ldr r1, [r7, #48] @ 0x30 8012d3a: 6b7a ldr r2, [r7, #52] @ 0x34 8012d3c: e841 2300 strex r3, r2, [r1] 8012d40: 62fb str r3, [r7, #44] @ 0x2c return(result); 8012d42: 6afb ldr r3, [r7, #44] @ 0x2c 8012d44: 2b00 cmp r3, #0 8012d46: d1e6 bne.n 8012d16 8012d48: e018 b.n 8012d7c } else { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8012d4a: 68fb ldr r3, [r7, #12] 8012d4c: 681b ldr r3, [r3, #0] 8012d4e: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012d50: 697b ldr r3, [r7, #20] 8012d52: e853 3f00 ldrex r3, [r3] 8012d56: 613b str r3, [r7, #16] return(result); 8012d58: 693b ldr r3, [r7, #16] 8012d5a: f043 0320 orr.w r3, r3, #32 8012d5e: 67bb str r3, [r7, #120] @ 0x78 8012d60: 68fb ldr r3, [r7, #12] 8012d62: 681b ldr r3, [r3, #0] 8012d64: 461a mov r2, r3 8012d66: 6fbb ldr r3, [r7, #120] @ 0x78 8012d68: 623b str r3, [r7, #32] 8012d6a: 61fa str r2, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012d6c: 69f9 ldr r1, [r7, #28] 8012d6e: 6a3a ldr r2, [r7, #32] 8012d70: e841 2300 strex r3, r2, [r1] 8012d74: 61bb str r3, [r7, #24] return(result); 8012d76: 69bb ldr r3, [r7, #24] 8012d78: 2b00 cmp r3, #0 8012d7a: d1e6 bne.n 8012d4a } } return HAL_OK; 8012d7c: 2300 movs r3, #0 } 8012d7e: 4618 mov r0, r3 8012d80: 378c adds r7, #140 @ 0x8c 8012d82: 46bd mov sp, r7 8012d84: f85d 7b04 ldr.w r7, [sp], #4 8012d88: 4770 bx lr 8012d8a: bf00 nop 8012d8c: 08013901 .word 0x08013901 8012d90: 080135a1 .word 0x080135a1 8012d94: 080133e9 .word 0x080133e9 8012d98: 08013231 .word 0x08013231 08012d9c : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8012d9c: b480 push {r7} 8012d9e: b095 sub sp, #84 @ 0x54 8012da0: af00 add r7, sp, #0 8012da2: 6078 str r0, [r7, #4] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8012da4: 687b ldr r3, [r7, #4] 8012da6: 681b ldr r3, [r3, #0] 8012da8: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012daa: 6b7b ldr r3, [r7, #52] @ 0x34 8012dac: e853 3f00 ldrex r3, [r3] 8012db0: 633b str r3, [r7, #48] @ 0x30 return(result); 8012db2: 6b3b ldr r3, [r7, #48] @ 0x30 8012db4: f423 7390 bic.w r3, r3, #288 @ 0x120 8012db8: 64fb str r3, [r7, #76] @ 0x4c 8012dba: 687b ldr r3, [r7, #4] 8012dbc: 681b ldr r3, [r3, #0] 8012dbe: 461a mov r2, r3 8012dc0: 6cfb ldr r3, [r7, #76] @ 0x4c 8012dc2: 643b str r3, [r7, #64] @ 0x40 8012dc4: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dc6: 6bf9 ldr r1, [r7, #60] @ 0x3c 8012dc8: 6c3a ldr r2, [r7, #64] @ 0x40 8012dca: e841 2300 strex r3, r2, [r1] 8012dce: 63bb str r3, [r7, #56] @ 0x38 return(result); 8012dd0: 6bbb ldr r3, [r7, #56] @ 0x38 8012dd2: 2b00 cmp r3, #0 8012dd4: d1e6 bne.n 8012da4 ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8012dd6: 687b ldr r3, [r7, #4] 8012dd8: 681b ldr r3, [r3, #0] 8012dda: 3308 adds r3, #8 8012ddc: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012dde: 6a3b ldr r3, [r7, #32] 8012de0: e853 3f00 ldrex r3, [r3] 8012de4: 61fb str r3, [r7, #28] return(result); 8012de6: 69fa ldr r2, [r7, #28] 8012de8: 4b1e ldr r3, [pc, #120] @ (8012e64 ) 8012dea: 4013 ands r3, r2 8012dec: 64bb str r3, [r7, #72] @ 0x48 8012dee: 687b ldr r3, [r7, #4] 8012df0: 681b ldr r3, [r3, #0] 8012df2: 3308 adds r3, #8 8012df4: 6cba ldr r2, [r7, #72] @ 0x48 8012df6: 62fa str r2, [r7, #44] @ 0x2c 8012df8: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012dfa: 6ab9 ldr r1, [r7, #40] @ 0x28 8012dfc: 6afa ldr r2, [r7, #44] @ 0x2c 8012dfe: e841 2300 strex r3, r2, [r1] 8012e02: 627b str r3, [r7, #36] @ 0x24 return(result); 8012e04: 6a7b ldr r3, [r7, #36] @ 0x24 8012e06: 2b00 cmp r3, #0 8012e08: d1e5 bne.n 8012dd6 /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8012e0a: 687b ldr r3, [r7, #4] 8012e0c: 6edb ldr r3, [r3, #108] @ 0x6c 8012e0e: 2b01 cmp r3, #1 8012e10: d118 bne.n 8012e44 { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8012e12: 687b ldr r3, [r7, #4] 8012e14: 681b ldr r3, [r3, #0] 8012e16: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012e18: 68fb ldr r3, [r7, #12] 8012e1a: e853 3f00 ldrex r3, [r3] 8012e1e: 60bb str r3, [r7, #8] return(result); 8012e20: 68bb ldr r3, [r7, #8] 8012e22: f023 0310 bic.w r3, r3, #16 8012e26: 647b str r3, [r7, #68] @ 0x44 8012e28: 687b ldr r3, [r7, #4] 8012e2a: 681b ldr r3, [r3, #0] 8012e2c: 461a mov r2, r3 8012e2e: 6c7b ldr r3, [r7, #68] @ 0x44 8012e30: 61bb str r3, [r7, #24] 8012e32: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012e34: 6979 ldr r1, [r7, #20] 8012e36: 69ba ldr r2, [r7, #24] 8012e38: e841 2300 strex r3, r2, [r1] 8012e3c: 613b str r3, [r7, #16] return(result); 8012e3e: 693b ldr r3, [r7, #16] 8012e40: 2b00 cmp r3, #0 8012e42: d1e6 bne.n 8012e12 } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8012e44: 687b ldr r3, [r7, #4] 8012e46: 2220 movs r2, #32 8012e48: f8c3 208c str.w r2, [r3, #140] @ 0x8c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8012e4c: 687b ldr r3, [r7, #4] 8012e4e: 2200 movs r2, #0 8012e50: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 8012e52: 687b ldr r3, [r7, #4] 8012e54: 2200 movs r2, #0 8012e56: 675a str r2, [r3, #116] @ 0x74 } 8012e58: bf00 nop 8012e5a: 3754 adds r7, #84 @ 0x54 8012e5c: 46bd mov sp, r7 8012e5e: f85d 7b04 ldr.w r7, [sp], #4 8012e62: 4770 bx lr 8012e64: effffffe .word 0xeffffffe 08012e68 : * (To be called at end of DMA Abort procedure following error occurrence). * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { 8012e68: b580 push {r7, lr} 8012e6a: b084 sub sp, #16 8012e6c: af00 add r7, sp, #0 8012e6e: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8012e70: 687b ldr r3, [r7, #4] 8012e72: 6b9b ldr r3, [r3, #56] @ 0x38 8012e74: 60fb str r3, [r7, #12] huart->RxXferCount = 0U; 8012e76: 68fb ldr r3, [r7, #12] 8012e78: 2200 movs r2, #0 8012e7a: f8a3 205e strh.w r2, [r3, #94] @ 0x5e huart->TxXferCount = 0U; 8012e7e: 68fb ldr r3, [r7, #12] 8012e80: 2200 movs r2, #0 8012e82: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8012e86: 68f8 ldr r0, [r7, #12] 8012e88: f7fe ff3a bl 8011d00 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8012e8c: bf00 nop 8012e8e: 3710 adds r7, #16 8012e90: 46bd mov sp, r7 8012e92: bd80 pop {r7, pc} 08012e94 : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) { 8012e94: b480 push {r7} 8012e96: b08f sub sp, #60 @ 0x3c 8012e98: af00 add r7, sp, #0 8012e9a: 6078 str r0, [r7, #4] /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012e9c: 687b ldr r3, [r7, #4] 8012e9e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012ea2: 2b21 cmp r3, #33 @ 0x21 8012ea4: d14c bne.n 8012f40 { if (huart->TxXferCount == 0U) 8012ea6: 687b ldr r3, [r7, #4] 8012ea8: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012eac: b29b uxth r3, r3 8012eae: 2b00 cmp r3, #0 8012eb0: d132 bne.n 8012f18 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012eb2: 687b ldr r3, [r7, #4] 8012eb4: 681b ldr r3, [r3, #0] 8012eb6: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012eb8: 6a3b ldr r3, [r7, #32] 8012eba: e853 3f00 ldrex r3, [r3] 8012ebe: 61fb str r3, [r7, #28] return(result); 8012ec0: 69fb ldr r3, [r7, #28] 8012ec2: f023 0380 bic.w r3, r3, #128 @ 0x80 8012ec6: 637b str r3, [r7, #52] @ 0x34 8012ec8: 687b ldr r3, [r7, #4] 8012eca: 681b ldr r3, [r3, #0] 8012ecc: 461a mov r2, r3 8012ece: 6b7b ldr r3, [r7, #52] @ 0x34 8012ed0: 62fb str r3, [r7, #44] @ 0x2c 8012ed2: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012ed4: 6ab9 ldr r1, [r7, #40] @ 0x28 8012ed6: 6afa ldr r2, [r7, #44] @ 0x2c 8012ed8: e841 2300 strex r3, r2, [r1] 8012edc: 627b str r3, [r7, #36] @ 0x24 return(result); 8012ede: 6a7b ldr r3, [r7, #36] @ 0x24 8012ee0: 2b00 cmp r3, #0 8012ee2: d1e6 bne.n 8012eb2 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012ee4: 687b ldr r3, [r7, #4] 8012ee6: 681b ldr r3, [r3, #0] 8012ee8: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012eea: 68fb ldr r3, [r7, #12] 8012eec: e853 3f00 ldrex r3, [r3] 8012ef0: 60bb str r3, [r7, #8] return(result); 8012ef2: 68bb ldr r3, [r7, #8] 8012ef4: f043 0340 orr.w r3, r3, #64 @ 0x40 8012ef8: 633b str r3, [r7, #48] @ 0x30 8012efa: 687b ldr r3, [r7, #4] 8012efc: 681b ldr r3, [r3, #0] 8012efe: 461a mov r2, r3 8012f00: 6b3b ldr r3, [r7, #48] @ 0x30 8012f02: 61bb str r3, [r7, #24] 8012f04: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f06: 6979 ldr r1, [r7, #20] 8012f08: 69ba ldr r2, [r7, #24] 8012f0a: e841 2300 strex r3, r2, [r1] 8012f0e: 613b str r3, [r7, #16] return(result); 8012f10: 693b ldr r3, [r7, #16] 8012f12: 2b00 cmp r3, #0 8012f14: d1e6 bne.n 8012ee4 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); huart->pTxBuffPtr++; huart->TxXferCount--; } } } 8012f16: e013 b.n 8012f40 huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 8012f18: 687b ldr r3, [r7, #4] 8012f1a: 6d1b ldr r3, [r3, #80] @ 0x50 8012f1c: 781a ldrb r2, [r3, #0] 8012f1e: 687b ldr r3, [r7, #4] 8012f20: 681b ldr r3, [r3, #0] 8012f22: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 8012f24: 687b ldr r3, [r7, #4] 8012f26: 6d1b ldr r3, [r3, #80] @ 0x50 8012f28: 1c5a adds r2, r3, #1 8012f2a: 687b ldr r3, [r7, #4] 8012f2c: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012f2e: 687b ldr r3, [r7, #4] 8012f30: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012f34: b29b uxth r3, r3 8012f36: 3b01 subs r3, #1 8012f38: b29a uxth r2, r3 8012f3a: 687b ldr r3, [r7, #4] 8012f3c: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8012f40: bf00 nop 8012f42: 373c adds r7, #60 @ 0x3c 8012f44: 46bd mov sp, r7 8012f46: f85d 7b04 ldr.w r7, [sp], #4 8012f4a: 4770 bx lr 08012f4c : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) { 8012f4c: b480 push {r7} 8012f4e: b091 sub sp, #68 @ 0x44 8012f50: af00 add r7, sp, #0 8012f52: 6078 str r0, [r7, #4] const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8012f54: 687b ldr r3, [r7, #4] 8012f56: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8012f5a: 2b21 cmp r3, #33 @ 0x21 8012f5c: d151 bne.n 8013002 { if (huart->TxXferCount == 0U) 8012f5e: 687b ldr r3, [r7, #4] 8012f60: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012f64: b29b uxth r3, r3 8012f66: 2b00 cmp r3, #0 8012f68: d132 bne.n 8012fd0 { /* Disable the UART Transmit Data Register Empty Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); 8012f6a: 687b ldr r3, [r7, #4] 8012f6c: 681b ldr r3, [r3, #0] 8012f6e: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012f70: 6a7b ldr r3, [r7, #36] @ 0x24 8012f72: e853 3f00 ldrex r3, [r3] 8012f76: 623b str r3, [r7, #32] return(result); 8012f78: 6a3b ldr r3, [r7, #32] 8012f7a: f023 0380 bic.w r3, r3, #128 @ 0x80 8012f7e: 63bb str r3, [r7, #56] @ 0x38 8012f80: 687b ldr r3, [r7, #4] 8012f82: 681b ldr r3, [r3, #0] 8012f84: 461a mov r2, r3 8012f86: 6bbb ldr r3, [r7, #56] @ 0x38 8012f88: 633b str r3, [r7, #48] @ 0x30 8012f8a: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012f8c: 6af9 ldr r1, [r7, #44] @ 0x2c 8012f8e: 6b3a ldr r2, [r7, #48] @ 0x30 8012f90: e841 2300 strex r3, r2, [r1] 8012f94: 62bb str r3, [r7, #40] @ 0x28 return(result); 8012f96: 6abb ldr r3, [r7, #40] @ 0x28 8012f98: 2b00 cmp r3, #0 8012f9a: d1e6 bne.n 8012f6a /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 8012f9c: 687b ldr r3, [r7, #4] 8012f9e: 681b ldr r3, [r3, #0] 8012fa0: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8012fa2: 693b ldr r3, [r7, #16] 8012fa4: e853 3f00 ldrex r3, [r3] 8012fa8: 60fb str r3, [r7, #12] return(result); 8012faa: 68fb ldr r3, [r7, #12] 8012fac: f043 0340 orr.w r3, r3, #64 @ 0x40 8012fb0: 637b str r3, [r7, #52] @ 0x34 8012fb2: 687b ldr r3, [r7, #4] 8012fb4: 681b ldr r3, [r3, #0] 8012fb6: 461a mov r2, r3 8012fb8: 6b7b ldr r3, [r7, #52] @ 0x34 8012fba: 61fb str r3, [r7, #28] 8012fbc: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8012fbe: 69b9 ldr r1, [r7, #24] 8012fc0: 69fa ldr r2, [r7, #28] 8012fc2: e841 2300 strex r3, r2, [r1] 8012fc6: 617b str r3, [r7, #20] return(result); 8012fc8: 697b ldr r3, [r7, #20] 8012fca: 2b00 cmp r3, #0 8012fcc: d1e6 bne.n 8012f9c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); huart->pTxBuffPtr += 2U; huart->TxXferCount--; } } } 8012fce: e018 b.n 8013002 tmp = (const uint16_t *) huart->pTxBuffPtr; 8012fd0: 687b ldr r3, [r7, #4] 8012fd2: 6d1b ldr r3, [r3, #80] @ 0x50 8012fd4: 63fb str r3, [r7, #60] @ 0x3c huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 8012fd6: 6bfb ldr r3, [r7, #60] @ 0x3c 8012fd8: 881b ldrh r3, [r3, #0] 8012fda: 461a mov r2, r3 8012fdc: 687b ldr r3, [r7, #4] 8012fde: 681b ldr r3, [r3, #0] 8012fe0: f3c2 0208 ubfx r2, r2, #0, #9 8012fe4: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 8012fe6: 687b ldr r3, [r7, #4] 8012fe8: 6d1b ldr r3, [r3, #80] @ 0x50 8012fea: 1c9a adds r2, r3, #2 8012fec: 687b ldr r3, [r7, #4] 8012fee: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 8012ff0: 687b ldr r3, [r7, #4] 8012ff2: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8012ff6: b29b uxth r3, r3 8012ff8: 3b01 subs r3, #1 8012ffa: b29a uxth r2, r3 8012ffc: 687b ldr r3, [r7, #4] 8012ffe: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 } 8013002: bf00 nop 8013004: 3744 adds r7, #68 @ 0x44 8013006: 46bd mov sp, r7 8013008: f85d 7b04 ldr.w r7, [sp], #4 801300c: 4770 bx lr 0801300e : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 801300e: b480 push {r7} 8013010: b091 sub sp, #68 @ 0x44 8013012: af00 add r7, sp, #0 8013014: 6078 str r0, [r7, #4] uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 8013016: 687b ldr r3, [r7, #4] 8013018: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 801301c: 2b21 cmp r3, #33 @ 0x21 801301e: d160 bne.n 80130e2 { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8013020: 687b ldr r3, [r7, #4] 8013022: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 8013026: 87fb strh r3, [r7, #62] @ 0x3e 8013028: e057 b.n 80130da { if (huart->TxXferCount == 0U) 801302a: 687b ldr r3, [r7, #4] 801302c: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013030: b29b uxth r3, r3 8013032: 2b00 cmp r3, #0 8013034: d133 bne.n 801309e { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 8013036: 687b ldr r3, [r7, #4] 8013038: 681b ldr r3, [r3, #0] 801303a: 3308 adds r3, #8 801303c: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801303e: 6a7b ldr r3, [r7, #36] @ 0x24 8013040: e853 3f00 ldrex r3, [r3] 8013044: 623b str r3, [r7, #32] return(result); 8013046: 6a3b ldr r3, [r7, #32] 8013048: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 801304c: 63bb str r3, [r7, #56] @ 0x38 801304e: 687b ldr r3, [r7, #4] 8013050: 681b ldr r3, [r3, #0] 8013052: 3308 adds r3, #8 8013054: 6bba ldr r2, [r7, #56] @ 0x38 8013056: 633a str r2, [r7, #48] @ 0x30 8013058: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801305a: 6af9 ldr r1, [r7, #44] @ 0x2c 801305c: 6b3a ldr r2, [r7, #48] @ 0x30 801305e: e841 2300 strex r3, r2, [r1] 8013062: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013064: 6abb ldr r3, [r7, #40] @ 0x28 8013066: 2b00 cmp r3, #0 8013068: d1e5 bne.n 8013036 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 801306a: 687b ldr r3, [r7, #4] 801306c: 681b ldr r3, [r3, #0] 801306e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013070: 693b ldr r3, [r7, #16] 8013072: e853 3f00 ldrex r3, [r3] 8013076: 60fb str r3, [r7, #12] return(result); 8013078: 68fb ldr r3, [r7, #12] 801307a: f043 0340 orr.w r3, r3, #64 @ 0x40 801307e: 637b str r3, [r7, #52] @ 0x34 8013080: 687b ldr r3, [r7, #4] 8013082: 681b ldr r3, [r3, #0] 8013084: 461a mov r2, r3 8013086: 6b7b ldr r3, [r7, #52] @ 0x34 8013088: 61fb str r3, [r7, #28] 801308a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801308c: 69b9 ldr r1, [r7, #24] 801308e: 69fa ldr r2, [r7, #28] 8013090: e841 2300 strex r3, r2, [r1] 8013094: 617b str r3, [r7, #20] return(result); 8013096: 697b ldr r3, [r7, #20] 8013098: 2b00 cmp r3, #0 801309a: d1e6 bne.n 801306a break; /* force exit loop */ 801309c: e021 b.n 80130e2 } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 801309e: 687b ldr r3, [r7, #4] 80130a0: 681b ldr r3, [r3, #0] 80130a2: 69db ldr r3, [r3, #28] 80130a4: f003 0380 and.w r3, r3, #128 @ 0x80 80130a8: 2b00 cmp r3, #0 80130aa: d013 beq.n 80130d4 { huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); 80130ac: 687b ldr r3, [r7, #4] 80130ae: 6d1b ldr r3, [r3, #80] @ 0x50 80130b0: 781a ldrb r2, [r3, #0] 80130b2: 687b ldr r3, [r7, #4] 80130b4: 681b ldr r3, [r3, #0] 80130b6: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr++; 80130b8: 687b ldr r3, [r7, #4] 80130ba: 6d1b ldr r3, [r3, #80] @ 0x50 80130bc: 1c5a adds r2, r3, #1 80130be: 687b ldr r3, [r7, #4] 80130c0: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80130c2: 687b ldr r3, [r7, #4] 80130c4: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80130c8: b29b uxth r3, r3 80130ca: 3b01 subs r3, #1 80130cc: b29a uxth r2, r3 80130ce: 687b ldr r3, [r7, #4] 80130d0: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80130d4: 8ffb ldrh r3, [r7, #62] @ 0x3e 80130d6: 3b01 subs r3, #1 80130d8: 87fb strh r3, [r7, #62] @ 0x3e 80130da: 8ffb ldrh r3, [r7, #62] @ 0x3e 80130dc: 2b00 cmp r3, #0 80130de: d1a4 bne.n 801302a { /* Nothing to do */ } } } } 80130e0: e7ff b.n 80130e2 80130e2: bf00 nop 80130e4: 3744 adds r7, #68 @ 0x44 80130e6: 46bd mov sp, r7 80130e8: f85d 7b04 ldr.w r7, [sp], #4 80130ec: 4770 bx lr 080130ee : * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. * @retval None */ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 80130ee: b480 push {r7} 80130f0: b091 sub sp, #68 @ 0x44 80130f2: af00 add r7, sp, #0 80130f4: 6078 str r0, [r7, #4] const uint16_t *tmp; uint16_t nb_tx_data; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) 80130f6: 687b ldr r3, [r7, #4] 80130f8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80130fc: 2b21 cmp r3, #33 @ 0x21 80130fe: d165 bne.n 80131cc { for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 8013100: 687b ldr r3, [r7, #4] 8013102: f8b3 306a ldrh.w r3, [r3, #106] @ 0x6a 8013106: 87fb strh r3, [r7, #62] @ 0x3e 8013108: e05c b.n 80131c4 { if (huart->TxXferCount == 0U) 801310a: 687b ldr r3, [r7, #4] 801310c: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 8013110: b29b uxth r3, r3 8013112: 2b00 cmp r3, #0 8013114: d133 bne.n 801317e { /* Disable the TX FIFO threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); 8013116: 687b ldr r3, [r7, #4] 8013118: 681b ldr r3, [r3, #0] 801311a: 3308 adds r3, #8 801311c: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801311e: 6a3b ldr r3, [r7, #32] 8013120: e853 3f00 ldrex r3, [r3] 8013124: 61fb str r3, [r7, #28] return(result); 8013126: 69fb ldr r3, [r7, #28] 8013128: f423 0300 bic.w r3, r3, #8388608 @ 0x800000 801312c: 637b str r3, [r7, #52] @ 0x34 801312e: 687b ldr r3, [r7, #4] 8013130: 681b ldr r3, [r3, #0] 8013132: 3308 adds r3, #8 8013134: 6b7a ldr r2, [r7, #52] @ 0x34 8013136: 62fa str r2, [r7, #44] @ 0x2c 8013138: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801313a: 6ab9 ldr r1, [r7, #40] @ 0x28 801313c: 6afa ldr r2, [r7, #44] @ 0x2c 801313e: e841 2300 strex r3, r2, [r1] 8013142: 627b str r3, [r7, #36] @ 0x24 return(result); 8013144: 6a7b ldr r3, [r7, #36] @ 0x24 8013146: 2b00 cmp r3, #0 8013148: d1e5 bne.n 8013116 /* Enable the UART Transmit Complete Interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); 801314a: 687b ldr r3, [r7, #4] 801314c: 681b ldr r3, [r3, #0] 801314e: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013150: 68fb ldr r3, [r7, #12] 8013152: e853 3f00 ldrex r3, [r3] 8013156: 60bb str r3, [r7, #8] return(result); 8013158: 68bb ldr r3, [r7, #8] 801315a: f043 0340 orr.w r3, r3, #64 @ 0x40 801315e: 633b str r3, [r7, #48] @ 0x30 8013160: 687b ldr r3, [r7, #4] 8013162: 681b ldr r3, [r3, #0] 8013164: 461a mov r2, r3 8013166: 6b3b ldr r3, [r7, #48] @ 0x30 8013168: 61bb str r3, [r7, #24] 801316a: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801316c: 6979 ldr r1, [r7, #20] 801316e: 69ba ldr r2, [r7, #24] 8013170: e841 2300 strex r3, r2, [r1] 8013174: 613b str r3, [r7, #16] return(result); 8013176: 693b ldr r3, [r7, #16] 8013178: 2b00 cmp r3, #0 801317a: d1e6 bne.n 801314a break; /* force exit loop */ 801317c: e026 b.n 80131cc } else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) 801317e: 687b ldr r3, [r7, #4] 8013180: 681b ldr r3, [r3, #0] 8013182: 69db ldr r3, [r3, #28] 8013184: f003 0380 and.w r3, r3, #128 @ 0x80 8013188: 2b00 cmp r3, #0 801318a: d018 beq.n 80131be { tmp = (const uint16_t *) huart->pTxBuffPtr; 801318c: 687b ldr r3, [r7, #4] 801318e: 6d1b ldr r3, [r3, #80] @ 0x50 8013190: 63bb str r3, [r7, #56] @ 0x38 huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); 8013192: 6bbb ldr r3, [r7, #56] @ 0x38 8013194: 881b ldrh r3, [r3, #0] 8013196: 461a mov r2, r3 8013198: 687b ldr r3, [r7, #4] 801319a: 681b ldr r3, [r3, #0] 801319c: f3c2 0208 ubfx r2, r2, #0, #9 80131a0: 629a str r2, [r3, #40] @ 0x28 huart->pTxBuffPtr += 2U; 80131a2: 687b ldr r3, [r7, #4] 80131a4: 6d1b ldr r3, [r3, #80] @ 0x50 80131a6: 1c9a adds r2, r3, #2 80131a8: 687b ldr r3, [r7, #4] 80131aa: 651a str r2, [r3, #80] @ 0x50 huart->TxXferCount--; 80131ac: 687b ldr r3, [r7, #4] 80131ae: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56 80131b2: b29b uxth r3, r3 80131b4: 3b01 subs r3, #1 80131b6: b29a uxth r2, r3 80131b8: 687b ldr r3, [r7, #4] 80131ba: f8a3 2056 strh.w r2, [r3, #86] @ 0x56 for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) 80131be: 8ffb ldrh r3, [r7, #62] @ 0x3e 80131c0: 3b01 subs r3, #1 80131c2: 87fb strh r3, [r7, #62] @ 0x3e 80131c4: 8ffb ldrh r3, [r7, #62] @ 0x3e 80131c6: 2b00 cmp r3, #0 80131c8: d19f bne.n 801310a { /* Nothing to do */ } } } } 80131ca: e7ff b.n 80131cc 80131cc: bf00 nop 80131ce: 3744 adds r7, #68 @ 0x44 80131d0: 46bd mov sp, r7 80131d2: f85d 7b04 ldr.w r7, [sp], #4 80131d6: 4770 bx lr 080131d8 : * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) { 80131d8: b580 push {r7, lr} 80131da: b088 sub sp, #32 80131dc: af00 add r7, sp, #0 80131de: 6078 str r0, [r7, #4] /* Disable the UART Transmit Complete Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); 80131e0: 687b ldr r3, [r7, #4] 80131e2: 681b ldr r3, [r3, #0] 80131e4: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80131e6: 68fb ldr r3, [r7, #12] 80131e8: e853 3f00 ldrex r3, [r3] 80131ec: 60bb str r3, [r7, #8] return(result); 80131ee: 68bb ldr r3, [r7, #8] 80131f0: f023 0340 bic.w r3, r3, #64 @ 0x40 80131f4: 61fb str r3, [r7, #28] 80131f6: 687b ldr r3, [r7, #4] 80131f8: 681b ldr r3, [r3, #0] 80131fa: 461a mov r2, r3 80131fc: 69fb ldr r3, [r7, #28] 80131fe: 61bb str r3, [r7, #24] 8013200: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013202: 6979 ldr r1, [r7, #20] 8013204: 69ba ldr r2, [r7, #24] 8013206: e841 2300 strex r3, r2, [r1] 801320a: 613b str r3, [r7, #16] return(result); 801320c: 693b ldr r3, [r7, #16] 801320e: 2b00 cmp r3, #0 8013210: d1e6 bne.n 80131e0 /* Tx process is ended, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8013212: 687b ldr r3, [r7, #4] 8013214: 2220 movs r2, #32 8013216: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Cleat TxISR function pointer */ huart->TxISR = NULL; 801321a: 687b ldr r3, [r7, #4] 801321c: 2200 movs r2, #0 801321e: 679a str r2, [r3, #120] @ 0x78 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Tx complete callback*/ huart->TxCpltCallback(huart); #else /*Call legacy weak Tx complete callback*/ HAL_UART_TxCpltCallback(huart); 8013220: 6878 ldr r0, [r7, #4] 8013222: f7f1 fc8d bl 8004b40 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 8013226: bf00 nop 8013228: 3720 adds r7, #32 801322a: 46bd mov sp, r7 801322c: bd80 pop {r7, pc} ... 08013230 : * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) { 8013230: b580 push {r7, lr} 8013232: b09c sub sp, #112 @ 0x70 8013234: af00 add r7, sp, #0 8013236: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 8013238: 687b ldr r3, [r7, #4] 801323a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 801323e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8013242: 687b ldr r3, [r7, #4] 8013244: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013248: 2b22 cmp r3, #34 @ 0x22 801324a: f040 80be bne.w 80133ca { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 801324e: 687b ldr r3, [r7, #4] 8013250: 681b ldr r3, [r3, #0] 8013252: 6a5b ldr r3, [r3, #36] @ 0x24 8013254: f8a7 306c strh.w r3, [r7, #108] @ 0x6c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 8013258: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c 801325c: b2d9 uxtb r1, r3 801325e: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 8013262: b2da uxtb r2, r3 8013264: 687b ldr r3, [r7, #4] 8013266: 6d9b ldr r3, [r3, #88] @ 0x58 8013268: 400a ands r2, r1 801326a: b2d2 uxtb r2, r2 801326c: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 801326e: 687b ldr r3, [r7, #4] 8013270: 6d9b ldr r3, [r3, #88] @ 0x58 8013272: 1c5a adds r2, r3, #1 8013274: 687b ldr r3, [r7, #4] 8013276: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013278: 687b ldr r3, [r7, #4] 801327a: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 801327e: b29b uxth r3, r3 8013280: 3b01 subs r3, #1 8013282: b29a uxth r2, r3 8013284: 687b ldr r3, [r7, #4] 8013286: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 801328a: 687b ldr r3, [r7, #4] 801328c: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013290: b29b uxth r3, r3 8013292: 2b00 cmp r3, #0 8013294: f040 80a1 bne.w 80133da { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8013298: 687b ldr r3, [r7, #4] 801329a: 681b ldr r3, [r3, #0] 801329c: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801329e: 6cfb ldr r3, [r7, #76] @ 0x4c 80132a0: e853 3f00 ldrex r3, [r3] 80132a4: 64bb str r3, [r7, #72] @ 0x48 return(result); 80132a6: 6cbb ldr r3, [r7, #72] @ 0x48 80132a8: f423 7390 bic.w r3, r3, #288 @ 0x120 80132ac: 66bb str r3, [r7, #104] @ 0x68 80132ae: 687b ldr r3, [r7, #4] 80132b0: 681b ldr r3, [r3, #0] 80132b2: 461a mov r2, r3 80132b4: 6ebb ldr r3, [r7, #104] @ 0x68 80132b6: 65bb str r3, [r7, #88] @ 0x58 80132b8: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132ba: 6d79 ldr r1, [r7, #84] @ 0x54 80132bc: 6dba ldr r2, [r7, #88] @ 0x58 80132be: e841 2300 strex r3, r2, [r1] 80132c2: 653b str r3, [r7, #80] @ 0x50 return(result); 80132c4: 6d3b ldr r3, [r7, #80] @ 0x50 80132c6: 2b00 cmp r3, #0 80132c8: d1e6 bne.n 8013298 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80132ca: 687b ldr r3, [r7, #4] 80132cc: 681b ldr r3, [r3, #0] 80132ce: 3308 adds r3, #8 80132d0: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80132d2: 6bbb ldr r3, [r7, #56] @ 0x38 80132d4: e853 3f00 ldrex r3, [r3] 80132d8: 637b str r3, [r7, #52] @ 0x34 return(result); 80132da: 6b7b ldr r3, [r7, #52] @ 0x34 80132dc: f023 0301 bic.w r3, r3, #1 80132e0: 667b str r3, [r7, #100] @ 0x64 80132e2: 687b ldr r3, [r7, #4] 80132e4: 681b ldr r3, [r3, #0] 80132e6: 3308 adds r3, #8 80132e8: 6e7a ldr r2, [r7, #100] @ 0x64 80132ea: 647a str r2, [r7, #68] @ 0x44 80132ec: 643b str r3, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80132ee: 6c39 ldr r1, [r7, #64] @ 0x40 80132f0: 6c7a ldr r2, [r7, #68] @ 0x44 80132f2: e841 2300 strex r3, r2, [r1] 80132f6: 63fb str r3, [r7, #60] @ 0x3c return(result); 80132f8: 6bfb ldr r3, [r7, #60] @ 0x3c 80132fa: 2b00 cmp r3, #0 80132fc: d1e5 bne.n 80132ca /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80132fe: 687b ldr r3, [r7, #4] 8013300: 2220 movs r2, #32 8013302: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8013306: 687b ldr r3, [r7, #4] 8013308: 2200 movs r2, #0 801330a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 801330c: 687b ldr r3, [r7, #4] 801330e: 2200 movs r2, #0 8013310: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8013312: 687b ldr r3, [r7, #4] 8013314: 681b ldr r3, [r3, #0] 8013316: 4a33 ldr r2, [pc, #204] @ (80133e4 ) 8013318: 4293 cmp r3, r2 801331a: d01f beq.n 801335c { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 801331c: 687b ldr r3, [r7, #4] 801331e: 681b ldr r3, [r3, #0] 8013320: 685b ldr r3, [r3, #4] 8013322: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8013326: 2b00 cmp r3, #0 8013328: d018 beq.n 801335c { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 801332a: 687b ldr r3, [r7, #4] 801332c: 681b ldr r3, [r3, #0] 801332e: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013330: 6a7b ldr r3, [r7, #36] @ 0x24 8013332: e853 3f00 ldrex r3, [r3] 8013336: 623b str r3, [r7, #32] return(result); 8013338: 6a3b ldr r3, [r7, #32] 801333a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 801333e: 663b str r3, [r7, #96] @ 0x60 8013340: 687b ldr r3, [r7, #4] 8013342: 681b ldr r3, [r3, #0] 8013344: 461a mov r2, r3 8013346: 6e3b ldr r3, [r7, #96] @ 0x60 8013348: 633b str r3, [r7, #48] @ 0x30 801334a: 62fa str r2, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801334c: 6af9 ldr r1, [r7, #44] @ 0x2c 801334e: 6b3a ldr r2, [r7, #48] @ 0x30 8013350: e841 2300 strex r3, r2, [r1] 8013354: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013356: 6abb ldr r3, [r7, #40] @ 0x28 8013358: 2b00 cmp r3, #0 801335a: d1e6 bne.n 801332a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 801335c: 687b ldr r3, [r7, #4] 801335e: 6edb ldr r3, [r3, #108] @ 0x6c 8013360: 2b01 cmp r3, #1 8013362: d12e bne.n 80133c2 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013364: 687b ldr r3, [r7, #4] 8013366: 2200 movs r2, #0 8013368: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 801336a: 687b ldr r3, [r7, #4] 801336c: 681b ldr r3, [r3, #0] 801336e: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013370: 693b ldr r3, [r7, #16] 8013372: e853 3f00 ldrex r3, [r3] 8013376: 60fb str r3, [r7, #12] return(result); 8013378: 68fb ldr r3, [r7, #12] 801337a: f023 0310 bic.w r3, r3, #16 801337e: 65fb str r3, [r7, #92] @ 0x5c 8013380: 687b ldr r3, [r7, #4] 8013382: 681b ldr r3, [r3, #0] 8013384: 461a mov r2, r3 8013386: 6dfb ldr r3, [r7, #92] @ 0x5c 8013388: 61fb str r3, [r7, #28] 801338a: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801338c: 69b9 ldr r1, [r7, #24] 801338e: 69fa ldr r2, [r7, #28] 8013390: e841 2300 strex r3, r2, [r1] 8013394: 617b str r3, [r7, #20] return(result); 8013396: 697b ldr r3, [r7, #20] 8013398: 2b00 cmp r3, #0 801339a: d1e6 bne.n 801336a if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 801339c: 687b ldr r3, [r7, #4] 801339e: 681b ldr r3, [r3, #0] 80133a0: 69db ldr r3, [r3, #28] 80133a2: f003 0310 and.w r3, r3, #16 80133a6: 2b10 cmp r3, #16 80133a8: d103 bne.n 80133b2 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 80133aa: 687b ldr r3, [r7, #4] 80133ac: 681b ldr r3, [r3, #0] 80133ae: 2210 movs r2, #16 80133b0: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 80133b2: 687b ldr r3, [r7, #4] 80133b4: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 80133b8: 4619 mov r1, r3 80133ba: 6878 ldr r0, [r7, #4] 80133bc: f7f1 fb96 bl 8004aec else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80133c0: e00b b.n 80133da HAL_UART_RxCpltCallback(huart); 80133c2: 6878 ldr r0, [r7, #4] 80133c4: f7f1 fb88 bl 8004ad8 } 80133c8: e007 b.n 80133da __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80133ca: 687b ldr r3, [r7, #4] 80133cc: 681b ldr r3, [r3, #0] 80133ce: 699a ldr r2, [r3, #24] 80133d0: 687b ldr r3, [r7, #4] 80133d2: 681b ldr r3, [r3, #0] 80133d4: f042 0208 orr.w r2, r2, #8 80133d8: 619a str r2, [r3, #24] } 80133da: bf00 nop 80133dc: 3770 adds r7, #112 @ 0x70 80133de: 46bd mov sp, r7 80133e0: bd80 pop {r7, pc} 80133e2: bf00 nop 80133e4: 58000c00 .word 0x58000c00 080133e8 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) { 80133e8: b580 push {r7, lr} 80133ea: b09c sub sp, #112 @ 0x70 80133ec: af00 add r7, sp, #0 80133ee: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 80133f0: 687b ldr r3, [r7, #4] 80133f2: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80133f6: f8a7 306e strh.w r3, [r7, #110] @ 0x6e uint16_t uhdata; /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80133fa: 687b ldr r3, [r7, #4] 80133fc: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013400: 2b22 cmp r3, #34 @ 0x22 8013402: f040 80be bne.w 8013582 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8013406: 687b ldr r3, [r7, #4] 8013408: 681b ldr r3, [r3, #0] 801340a: 6a5b ldr r3, [r3, #36] @ 0x24 801340c: f8a7 306c strh.w r3, [r7, #108] @ 0x6c tmp = (uint16_t *) huart->pRxBuffPtr ; 8013410: 687b ldr r3, [r7, #4] 8013412: 6d9b ldr r3, [r3, #88] @ 0x58 8013414: 66bb str r3, [r7, #104] @ 0x68 *tmp = (uint16_t)(uhdata & uhMask); 8013416: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c 801341a: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e 801341e: 4013 ands r3, r2 8013420: b29a uxth r2, r3 8013422: 6ebb ldr r3, [r7, #104] @ 0x68 8013424: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 8013426: 687b ldr r3, [r7, #4] 8013428: 6d9b ldr r3, [r3, #88] @ 0x58 801342a: 1c9a adds r2, r3, #2 801342c: 687b ldr r3, [r7, #4] 801342e: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013430: 687b ldr r3, [r7, #4] 8013432: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013436: b29b uxth r3, r3 8013438: 3b01 subs r3, #1 801343a: b29a uxth r2, r3 801343c: 687b ldr r3, [r7, #4] 801343e: f8a3 205e strh.w r2, [r3, #94] @ 0x5e if (huart->RxXferCount == 0U) 8013442: 687b ldr r3, [r7, #4] 8013444: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013448: b29b uxth r3, r3 801344a: 2b00 cmp r3, #0 801344c: f040 80a1 bne.w 8013592 { /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8013450: 687b ldr r3, [r7, #4] 8013452: 681b ldr r3, [r3, #0] 8013454: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013456: 6cbb ldr r3, [r7, #72] @ 0x48 8013458: e853 3f00 ldrex r3, [r3] 801345c: 647b str r3, [r7, #68] @ 0x44 return(result); 801345e: 6c7b ldr r3, [r7, #68] @ 0x44 8013460: f423 7390 bic.w r3, r3, #288 @ 0x120 8013464: 667b str r3, [r7, #100] @ 0x64 8013466: 687b ldr r3, [r7, #4] 8013468: 681b ldr r3, [r3, #0] 801346a: 461a mov r2, r3 801346c: 6e7b ldr r3, [r7, #100] @ 0x64 801346e: 657b str r3, [r7, #84] @ 0x54 8013470: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013472: 6d39 ldr r1, [r7, #80] @ 0x50 8013474: 6d7a ldr r2, [r7, #84] @ 0x54 8013476: e841 2300 strex r3, r2, [r1] 801347a: 64fb str r3, [r7, #76] @ 0x4c return(result); 801347c: 6cfb ldr r3, [r7, #76] @ 0x4c 801347e: 2b00 cmp r3, #0 8013480: d1e6 bne.n 8013450 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8013482: 687b ldr r3, [r7, #4] 8013484: 681b ldr r3, [r3, #0] 8013486: 3308 adds r3, #8 8013488: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801348a: 6b7b ldr r3, [r7, #52] @ 0x34 801348c: e853 3f00 ldrex r3, [r3] 8013490: 633b str r3, [r7, #48] @ 0x30 return(result); 8013492: 6b3b ldr r3, [r7, #48] @ 0x30 8013494: f023 0301 bic.w r3, r3, #1 8013498: 663b str r3, [r7, #96] @ 0x60 801349a: 687b ldr r3, [r7, #4] 801349c: 681b ldr r3, [r3, #0] 801349e: 3308 adds r3, #8 80134a0: 6e3a ldr r2, [r7, #96] @ 0x60 80134a2: 643a str r2, [r7, #64] @ 0x40 80134a4: 63fb str r3, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80134a6: 6bf9 ldr r1, [r7, #60] @ 0x3c 80134a8: 6c3a ldr r2, [r7, #64] @ 0x40 80134aa: e841 2300 strex r3, r2, [r1] 80134ae: 63bb str r3, [r7, #56] @ 0x38 return(result); 80134b0: 6bbb ldr r3, [r7, #56] @ 0x38 80134b2: 2b00 cmp r3, #0 80134b4: d1e5 bne.n 8013482 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80134b6: 687b ldr r3, [r7, #4] 80134b8: 2220 movs r2, #32 80134ba: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 80134be: 687b ldr r3, [r7, #4] 80134c0: 2200 movs r2, #0 80134c2: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 80134c4: 687b ldr r3, [r7, #4] 80134c6: 2200 movs r2, #0 80134c8: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 80134ca: 687b ldr r3, [r7, #4] 80134cc: 681b ldr r3, [r3, #0] 80134ce: 4a33 ldr r2, [pc, #204] @ (801359c ) 80134d0: 4293 cmp r3, r2 80134d2: d01f beq.n 8013514 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 80134d4: 687b ldr r3, [r7, #4] 80134d6: 681b ldr r3, [r3, #0] 80134d8: 685b ldr r3, [r3, #4] 80134da: f403 0300 and.w r3, r3, #8388608 @ 0x800000 80134de: 2b00 cmp r3, #0 80134e0: d018 beq.n 8013514 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 80134e2: 687b ldr r3, [r7, #4] 80134e4: 681b ldr r3, [r3, #0] 80134e6: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80134e8: 6a3b ldr r3, [r7, #32] 80134ea: e853 3f00 ldrex r3, [r3] 80134ee: 61fb str r3, [r7, #28] return(result); 80134f0: 69fb ldr r3, [r7, #28] 80134f2: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 80134f6: 65fb str r3, [r7, #92] @ 0x5c 80134f8: 687b ldr r3, [r7, #4] 80134fa: 681b ldr r3, [r3, #0] 80134fc: 461a mov r2, r3 80134fe: 6dfb ldr r3, [r7, #92] @ 0x5c 8013500: 62fb str r3, [r7, #44] @ 0x2c 8013502: 62ba str r2, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013504: 6ab9 ldr r1, [r7, #40] @ 0x28 8013506: 6afa ldr r2, [r7, #44] @ 0x2c 8013508: e841 2300 strex r3, r2, [r1] 801350c: 627b str r3, [r7, #36] @ 0x24 return(result); 801350e: 6a7b ldr r3, [r7, #36] @ 0x24 8013510: 2b00 cmp r3, #0 8013512: d1e6 bne.n 80134e2 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013514: 687b ldr r3, [r7, #4] 8013516: 6edb ldr r3, [r3, #108] @ 0x6c 8013518: 2b01 cmp r3, #1 801351a: d12e bne.n 801357a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 801351c: 687b ldr r3, [r7, #4] 801351e: 2200 movs r2, #0 8013520: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013522: 687b ldr r3, [r7, #4] 8013524: 681b ldr r3, [r3, #0] 8013526: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013528: 68fb ldr r3, [r7, #12] 801352a: e853 3f00 ldrex r3, [r3] 801352e: 60bb str r3, [r7, #8] return(result); 8013530: 68bb ldr r3, [r7, #8] 8013532: f023 0310 bic.w r3, r3, #16 8013536: 65bb str r3, [r7, #88] @ 0x58 8013538: 687b ldr r3, [r7, #4] 801353a: 681b ldr r3, [r3, #0] 801353c: 461a mov r2, r3 801353e: 6dbb ldr r3, [r7, #88] @ 0x58 8013540: 61bb str r3, [r7, #24] 8013542: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013544: 6979 ldr r1, [r7, #20] 8013546: 69ba ldr r2, [r7, #24] 8013548: e841 2300 strex r3, r2, [r1] 801354c: 613b str r3, [r7, #16] return(result); 801354e: 693b ldr r3, [r7, #16] 8013550: 2b00 cmp r3, #0 8013552: d1e6 bne.n 8013522 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013554: 687b ldr r3, [r7, #4] 8013556: 681b ldr r3, [r3, #0] 8013558: 69db ldr r3, [r3, #28] 801355a: f003 0310 and.w r3, r3, #16 801355e: 2b10 cmp r3, #16 8013560: d103 bne.n 801356a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013562: 687b ldr r3, [r7, #4] 8013564: 681b ldr r3, [r3, #0] 8013566: 2210 movs r2, #16 8013568: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 801356a: 687b ldr r3, [r7, #4] 801356c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013570: 4619 mov r1, r3 8013572: 6878 ldr r0, [r7, #4] 8013574: f7f1 faba bl 8004aec else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013578: e00b b.n 8013592 HAL_UART_RxCpltCallback(huart); 801357a: 6878 ldr r0, [r7, #4] 801357c: f7f1 faac bl 8004ad8 } 8013580: e007 b.n 8013592 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8013582: 687b ldr r3, [r7, #4] 8013584: 681b ldr r3, [r3, #0] 8013586: 699a ldr r2, [r3, #24] 8013588: 687b ldr r3, [r7, #4] 801358a: 681b ldr r3, [r3, #0] 801358c: f042 0208 orr.w r2, r2, #8 8013590: 619a str r2, [r3, #24] } 8013592: bf00 nop 8013594: 3770 adds r7, #112 @ 0x70 8013596: 46bd mov sp, r7 8013598: bd80 pop {r7, pc} 801359a: bf00 nop 801359c: 58000c00 .word 0x58000c00 080135a0 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { 80135a0: b580 push {r7, lr} 80135a2: b0ac sub sp, #176 @ 0xb0 80135a4: af00 add r7, sp, #0 80135a6: 6078 str r0, [r7, #4] uint16_t uhMask = huart->Mask; 80135a8: 687b ldr r3, [r7, #4] 80135aa: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 80135ae: f8a7 30aa strh.w r3, [r7, #170] @ 0xaa uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 80135b2: 687b ldr r3, [r7, #4] 80135b4: 681b ldr r3, [r3, #0] 80135b6: 69db ldr r3, [r3, #28] 80135b8: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr1its = READ_REG(huart->Instance->CR1); 80135bc: 687b ldr r3, [r7, #4] 80135be: 681b ldr r3, [r3, #0] 80135c0: 681b ldr r3, [r3, #0] 80135c2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4 uint32_t cr3its = READ_REG(huart->Instance->CR3); 80135c6: 687b ldr r3, [r7, #4] 80135c8: 681b ldr r3, [r3, #0] 80135ca: 689b ldr r3, [r3, #8] 80135cc: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 80135d0: 687b ldr r3, [r7, #4] 80135d2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80135d6: 2b22 cmp r3, #34 @ 0x22 80135d8: f040 8180 bne.w 80138dc { nb_rx_data = huart->NbRxDataToProcess; 80135dc: 687b ldr r3, [r7, #4] 80135de: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 80135e2: f8a7 309e strh.w r3, [r7, #158] @ 0x9e while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 80135e6: e123 b.n 8013830 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 80135e8: 687b ldr r3, [r7, #4] 80135ea: 681b ldr r3, [r3, #0] 80135ec: 6a5b ldr r3, [r3, #36] @ 0x24 80135ee: f8a7 309c strh.w r3, [r7, #156] @ 0x9c *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); 80135f2: f8b7 309c ldrh.w r3, [r7, #156] @ 0x9c 80135f6: b2d9 uxtb r1, r3 80135f8: f8b7 30aa ldrh.w r3, [r7, #170] @ 0xaa 80135fc: b2da uxtb r2, r3 80135fe: 687b ldr r3, [r7, #4] 8013600: 6d9b ldr r3, [r3, #88] @ 0x58 8013602: 400a ands r2, r1 8013604: b2d2 uxtb r2, r2 8013606: 701a strb r2, [r3, #0] huart->pRxBuffPtr++; 8013608: 687b ldr r3, [r7, #4] 801360a: 6d9b ldr r3, [r3, #88] @ 0x58 801360c: 1c5a adds r2, r3, #1 801360e: 687b ldr r3, [r7, #4] 8013610: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013612: 687b ldr r3, [r7, #4] 8013614: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013618: b29b uxth r3, r3 801361a: 3b01 subs r3, #1 801361c: b29a uxth r2, r3 801361e: 687b ldr r3, [r7, #4] 8013620: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8013624: 687b ldr r3, [r7, #4] 8013626: 681b ldr r3, [r3, #0] 8013628: 69db ldr r3, [r3, #28] 801362a: f8c7 30ac str.w r3, [r7, #172] @ 0xac /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 801362e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 8013632: f003 0307 and.w r3, r3, #7 8013636: 2b00 cmp r3, #0 8013638: d053 beq.n 80136e2 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 801363a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801363e: f003 0301 and.w r3, r3, #1 8013642: 2b00 cmp r3, #0 8013644: d011 beq.n 801366a 8013646: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4 801364a: f403 7380 and.w r3, r3, #256 @ 0x100 801364e: 2b00 cmp r3, #0 8013650: d00b beq.n 801366a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 8013652: 687b ldr r3, [r7, #4] 8013654: 681b ldr r3, [r3, #0] 8013656: 2201 movs r2, #1 8013658: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 801365a: 687b ldr r3, [r7, #4] 801365c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013660: f043 0201 orr.w r2, r3, #1 8013664: 687b ldr r3, [r7, #4] 8013666: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 801366a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801366e: f003 0302 and.w r3, r3, #2 8013672: 2b00 cmp r3, #0 8013674: d011 beq.n 801369a 8013676: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801367a: f003 0301 and.w r3, r3, #1 801367e: 2b00 cmp r3, #0 8013680: d00b beq.n 801369a { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 8013682: 687b ldr r3, [r7, #4] 8013684: 681b ldr r3, [r3, #0] 8013686: 2202 movs r2, #2 8013688: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 801368a: 687b ldr r3, [r7, #4] 801368c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013690: f043 0204 orr.w r2, r3, #4 8013694: 687b ldr r3, [r7, #4] 8013696: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 801369a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801369e: f003 0304 and.w r3, r3, #4 80136a2: 2b00 cmp r3, #0 80136a4: d011 beq.n 80136ca 80136a6: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 80136aa: f003 0301 and.w r3, r3, #1 80136ae: 2b00 cmp r3, #0 80136b0: d00b beq.n 80136ca { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 80136b2: 687b ldr r3, [r7, #4] 80136b4: 681b ldr r3, [r3, #0] 80136b6: 2204 movs r2, #4 80136b8: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 80136ba: 687b ldr r3, [r7, #4] 80136bc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80136c0: f043 0202 orr.w r2, r3, #2 80136c4: 687b ldr r3, [r7, #4] 80136c6: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 80136ca: 687b ldr r3, [r7, #4] 80136cc: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80136d0: 2b00 cmp r3, #0 80136d2: d006 beq.n 80136e2 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80136d4: 6878 ldr r0, [r7, #4] 80136d6: f7fe fb13 bl 8011d00 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 80136da: 687b ldr r3, [r7, #4] 80136dc: 2200 movs r2, #0 80136de: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 80136e2: 687b ldr r3, [r7, #4] 80136e4: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 80136e8: b29b uxth r3, r3 80136ea: 2b00 cmp r3, #0 80136ec: f040 80a0 bne.w 8013830 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 80136f0: 687b ldr r3, [r7, #4] 80136f2: 681b ldr r3, [r3, #0] 80136f4: 673b str r3, [r7, #112] @ 0x70 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80136f6: 6f3b ldr r3, [r7, #112] @ 0x70 80136f8: e853 3f00 ldrex r3, [r3] 80136fc: 66fb str r3, [r7, #108] @ 0x6c return(result); 80136fe: 6efb ldr r3, [r7, #108] @ 0x6c 8013700: f423 7380 bic.w r3, r3, #256 @ 0x100 8013704: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8013708: 687b ldr r3, [r7, #4] 801370a: 681b ldr r3, [r3, #0] 801370c: 461a mov r2, r3 801370e: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98 8013712: 67fb str r3, [r7, #124] @ 0x7c 8013714: 67ba str r2, [r7, #120] @ 0x78 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013716: 6fb9 ldr r1, [r7, #120] @ 0x78 8013718: 6ffa ldr r2, [r7, #124] @ 0x7c 801371a: e841 2300 strex r3, r2, [r1] 801371e: 677b str r3, [r7, #116] @ 0x74 return(result); 8013720: 6f7b ldr r3, [r7, #116] @ 0x74 8013722: 2b00 cmp r3, #0 8013724: d1e4 bne.n 80136f0 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8013726: 687b ldr r3, [r7, #4] 8013728: 681b ldr r3, [r3, #0] 801372a: 3308 adds r3, #8 801372c: 65fb str r3, [r7, #92] @ 0x5c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801372e: 6dfb ldr r3, [r7, #92] @ 0x5c 8013730: e853 3f00 ldrex r3, [r3] 8013734: 65bb str r3, [r7, #88] @ 0x58 return(result); 8013736: 6dba ldr r2, [r7, #88] @ 0x58 8013738: 4b6e ldr r3, [pc, #440] @ (80138f4 ) 801373a: 4013 ands r3, r2 801373c: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013740: 687b ldr r3, [r7, #4] 8013742: 681b ldr r3, [r3, #0] 8013744: 3308 adds r3, #8 8013746: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94 801374a: 66ba str r2, [r7, #104] @ 0x68 801374c: 667b str r3, [r7, #100] @ 0x64 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801374e: 6e79 ldr r1, [r7, #100] @ 0x64 8013750: 6eba ldr r2, [r7, #104] @ 0x68 8013752: e841 2300 strex r3, r2, [r1] 8013756: 663b str r3, [r7, #96] @ 0x60 return(result); 8013758: 6e3b ldr r3, [r7, #96] @ 0x60 801375a: 2b00 cmp r3, #0 801375c: d1e3 bne.n 8013726 /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 801375e: 687b ldr r3, [r7, #4] 8013760: 2220 movs r2, #32 8013762: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8013766: 687b ldr r3, [r7, #4] 8013768: 2200 movs r2, #0 801376a: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 801376c: 687b ldr r3, [r7, #4] 801376e: 2200 movs r2, #0 8013770: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8013772: 687b ldr r3, [r7, #4] 8013774: 681b ldr r3, [r3, #0] 8013776: 4a60 ldr r2, [pc, #384] @ (80138f8 ) 8013778: 4293 cmp r3, r2 801377a: d021 beq.n 80137c0 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 801377c: 687b ldr r3, [r7, #4] 801377e: 681b ldr r3, [r3, #0] 8013780: 685b ldr r3, [r3, #4] 8013782: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8013786: 2b00 cmp r3, #0 8013788: d01a beq.n 80137c0 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 801378a: 687b ldr r3, [r7, #4] 801378c: 681b ldr r3, [r3, #0] 801378e: 64bb str r3, [r7, #72] @ 0x48 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013790: 6cbb ldr r3, [r7, #72] @ 0x48 8013792: e853 3f00 ldrex r3, [r3] 8013796: 647b str r3, [r7, #68] @ 0x44 return(result); 8013798: 6c7b ldr r3, [r7, #68] @ 0x44 801379a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 801379e: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80137a2: 687b ldr r3, [r7, #4] 80137a4: 681b ldr r3, [r3, #0] 80137a6: 461a mov r2, r3 80137a8: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 80137ac: 657b str r3, [r7, #84] @ 0x54 80137ae: 653a str r2, [r7, #80] @ 0x50 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137b0: 6d39 ldr r1, [r7, #80] @ 0x50 80137b2: 6d7a ldr r2, [r7, #84] @ 0x54 80137b4: e841 2300 strex r3, r2, [r1] 80137b8: 64fb str r3, [r7, #76] @ 0x4c return(result); 80137ba: 6cfb ldr r3, [r7, #76] @ 0x4c 80137bc: 2b00 cmp r3, #0 80137be: d1e4 bne.n 801378a } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80137c0: 687b ldr r3, [r7, #4] 80137c2: 6edb ldr r3, [r3, #108] @ 0x6c 80137c4: 2b01 cmp r3, #1 80137c6: d130 bne.n 801382a { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80137c8: 687b ldr r3, [r7, #4] 80137ca: 2200 movs r2, #0 80137cc: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80137ce: 687b ldr r3, [r7, #4] 80137d0: 681b ldr r3, [r3, #0] 80137d2: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80137d4: 6b7b ldr r3, [r7, #52] @ 0x34 80137d6: e853 3f00 ldrex r3, [r3] 80137da: 633b str r3, [r7, #48] @ 0x30 return(result); 80137dc: 6b3b ldr r3, [r7, #48] @ 0x30 80137de: f023 0310 bic.w r3, r3, #16 80137e2: f8c7 308c str.w r3, [r7, #140] @ 0x8c 80137e6: 687b ldr r3, [r7, #4] 80137e8: 681b ldr r3, [r3, #0] 80137ea: 461a mov r2, r3 80137ec: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c 80137f0: 643b str r3, [r7, #64] @ 0x40 80137f2: 63fa str r2, [r7, #60] @ 0x3c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80137f4: 6bf9 ldr r1, [r7, #60] @ 0x3c 80137f6: 6c3a ldr r2, [r7, #64] @ 0x40 80137f8: e841 2300 strex r3, r2, [r1] 80137fc: 63bb str r3, [r7, #56] @ 0x38 return(result); 80137fe: 6bbb ldr r3, [r7, #56] @ 0x38 8013800: 2b00 cmp r3, #0 8013802: d1e4 bne.n 80137ce if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013804: 687b ldr r3, [r7, #4] 8013806: 681b ldr r3, [r3, #0] 8013808: 69db ldr r3, [r3, #28] 801380a: f003 0310 and.w r3, r3, #16 801380e: 2b10 cmp r3, #16 8013810: d103 bne.n 801381a { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013812: 687b ldr r3, [r7, #4] 8013814: 681b ldr r3, [r3, #0] 8013816: 2210 movs r2, #16 8013818: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 801381a: 687b ldr r3, [r7, #4] 801381c: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013820: 4619 mov r1, r3 8013822: 6878 ldr r0, [r7, #4] 8013824: f7f1 f962 bl 8004aec 8013828: e002 b.n 8013830 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 801382a: 6878 ldr r0, [r7, #4] 801382c: f7f1 f954 bl 8004ad8 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013830: f8b7 309e ldrh.w r3, [r7, #158] @ 0x9e 8013834: 2b00 cmp r3, #0 8013836: d006 beq.n 8013846 8013838: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 801383c: f003 0320 and.w r3, r3, #32 8013840: 2b00 cmp r3, #0 8013842: f47f aed1 bne.w 80135e8 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8013846: 687b ldr r3, [r7, #4] 8013848: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 801384c: f8a7 308a strh.w r3, [r7, #138] @ 0x8a if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8013850: f8b7 308a ldrh.w r3, [r7, #138] @ 0x8a 8013854: 2b00 cmp r3, #0 8013856: d049 beq.n 80138ec 8013858: 687b ldr r3, [r7, #4] 801385a: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 801385e: f8b7 208a ldrh.w r2, [r7, #138] @ 0x8a 8013862: 429a cmp r2, r3 8013864: d242 bcs.n 80138ec { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8013866: 687b ldr r3, [r7, #4] 8013868: 681b ldr r3, [r3, #0] 801386a: 3308 adds r3, #8 801386c: 623b str r3, [r7, #32] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 801386e: 6a3b ldr r3, [r7, #32] 8013870: e853 3f00 ldrex r3, [r3] 8013874: 61fb str r3, [r7, #28] return(result); 8013876: 69fb ldr r3, [r7, #28] 8013878: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 801387c: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013880: 687b ldr r3, [r7, #4] 8013882: 681b ldr r3, [r3, #0] 8013884: 3308 adds r3, #8 8013886: f8d7 2084 ldr.w r2, [r7, #132] @ 0x84 801388a: 62fa str r2, [r7, #44] @ 0x2c 801388c: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 801388e: 6ab9 ldr r1, [r7, #40] @ 0x28 8013890: 6afa ldr r2, [r7, #44] @ 0x2c 8013892: e841 2300 strex r3, r2, [r1] 8013896: 627b str r3, [r7, #36] @ 0x24 return(result); 8013898: 6a7b ldr r3, [r7, #36] @ 0x24 801389a: 2b00 cmp r3, #0 801389c: d1e3 bne.n 8013866 /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_8BIT; 801389e: 687b ldr r3, [r7, #4] 80138a0: 4a16 ldr r2, [pc, #88] @ (80138fc ) 80138a2: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 80138a4: 687b ldr r3, [r7, #4] 80138a6: 681b ldr r3, [r3, #0] 80138a8: 60fb str r3, [r7, #12] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 80138aa: 68fb ldr r3, [r7, #12] 80138ac: e853 3f00 ldrex r3, [r3] 80138b0: 60bb str r3, [r7, #8] return(result); 80138b2: 68bb ldr r3, [r7, #8] 80138b4: f043 0320 orr.w r3, r3, #32 80138b8: f8c7 3080 str.w r3, [r7, #128] @ 0x80 80138bc: 687b ldr r3, [r7, #4] 80138be: 681b ldr r3, [r3, #0] 80138c0: 461a mov r2, r3 80138c2: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80 80138c6: 61bb str r3, [r7, #24] 80138c8: 617a str r2, [r7, #20] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 80138ca: 6979 ldr r1, [r7, #20] 80138cc: 69ba ldr r2, [r7, #24] 80138ce: e841 2300 strex r3, r2, [r1] 80138d2: 613b str r3, [r7, #16] return(result); 80138d4: 693b ldr r3, [r7, #16] 80138d6: 2b00 cmp r3, #0 80138d8: d1e4 bne.n 80138a4 else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 80138da: e007 b.n 80138ec __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 80138dc: 687b ldr r3, [r7, #4] 80138de: 681b ldr r3, [r3, #0] 80138e0: 699a ldr r2, [r3, #24] 80138e2: 687b ldr r3, [r7, #4] 80138e4: 681b ldr r3, [r3, #0] 80138e6: f042 0208 orr.w r2, r2, #8 80138ea: 619a str r2, [r3, #24] } 80138ec: bf00 nop 80138ee: 37b0 adds r7, #176 @ 0xb0 80138f0: 46bd mov sp, r7 80138f2: bd80 pop {r7, pc} 80138f4: effffffe .word 0xeffffffe 80138f8: 58000c00 .word 0x58000c00 80138fc: 08013231 .word 0x08013231 08013900 : * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. * @retval None */ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) { 8013900: b580 push {r7, lr} 8013902: b0ae sub sp, #184 @ 0xb8 8013904: af00 add r7, sp, #0 8013906: 6078 str r0, [r7, #4] uint16_t *tmp; uint16_t uhMask = huart->Mask; 8013908: 687b ldr r3, [r7, #4] 801390a: f8b3 3060 ldrh.w r3, [r3, #96] @ 0x60 801390e: f8a7 30b2 strh.w r3, [r7, #178] @ 0xb2 uint16_t uhdata; uint16_t nb_rx_data; uint16_t rxdatacount; uint32_t isrflags = READ_REG(huart->Instance->ISR); 8013912: 687b ldr r3, [r7, #4] 8013914: 681b ldr r3, [r3, #0] 8013916: 69db ldr r3, [r3, #28] 8013918: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 uint32_t cr1its = READ_REG(huart->Instance->CR1); 801391c: 687b ldr r3, [r7, #4] 801391e: 681b ldr r3, [r3, #0] 8013920: 681b ldr r3, [r3, #0] 8013922: f8c7 30ac str.w r3, [r7, #172] @ 0xac uint32_t cr3its = READ_REG(huart->Instance->CR3); 8013926: 687b ldr r3, [r7, #4] 8013928: 681b ldr r3, [r3, #0] 801392a: 689b ldr r3, [r3, #8] 801392c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) 8013930: 687b ldr r3, [r7, #4] 8013932: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013936: 2b22 cmp r3, #34 @ 0x22 8013938: f040 8184 bne.w 8013c44 { nb_rx_data = huart->NbRxDataToProcess; 801393c: 687b ldr r3, [r7, #4] 801393e: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013942: f8a7 30a6 strh.w r3, [r7, #166] @ 0xa6 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013946: e127 b.n 8013b98 { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); 8013948: 687b ldr r3, [r7, #4] 801394a: 681b ldr r3, [r3, #0] 801394c: 6a5b ldr r3, [r3, #36] @ 0x24 801394e: f8a7 30a4 strh.w r3, [r7, #164] @ 0xa4 tmp = (uint16_t *) huart->pRxBuffPtr ; 8013952: 687b ldr r3, [r7, #4] 8013954: 6d9b ldr r3, [r3, #88] @ 0x58 8013956: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 *tmp = (uint16_t)(uhdata & uhMask); 801395a: f8b7 20a4 ldrh.w r2, [r7, #164] @ 0xa4 801395e: f8b7 30b2 ldrh.w r3, [r7, #178] @ 0xb2 8013962: 4013 ands r3, r2 8013964: b29a uxth r2, r3 8013966: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0 801396a: 801a strh r2, [r3, #0] huart->pRxBuffPtr += 2U; 801396c: 687b ldr r3, [r7, #4] 801396e: 6d9b ldr r3, [r3, #88] @ 0x58 8013970: 1c9a adds r2, r3, #2 8013972: 687b ldr r3, [r7, #4] 8013974: 659a str r2, [r3, #88] @ 0x58 huart->RxXferCount--; 8013976: 687b ldr r3, [r7, #4] 8013978: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 801397c: b29b uxth r3, r3 801397e: 3b01 subs r3, #1 8013980: b29a uxth r2, r3 8013982: 687b ldr r3, [r7, #4] 8013984: f8a3 205e strh.w r2, [r3, #94] @ 0x5e isrflags = READ_REG(huart->Instance->ISR); 8013988: 687b ldr r3, [r7, #4] 801398a: 681b ldr r3, [r3, #0] 801398c: 69db ldr r3, [r3, #28] 801398e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 /* If some non blocking errors occurred */ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) 8013992: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013996: f003 0307 and.w r3, r3, #7 801399a: 2b00 cmp r3, #0 801399c: d053 beq.n 8013a46 { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) 801399e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80139a2: f003 0301 and.w r3, r3, #1 80139a6: 2b00 cmp r3, #0 80139a8: d011 beq.n 80139ce 80139aa: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac 80139ae: f403 7380 and.w r3, r3, #256 @ 0x100 80139b2: 2b00 cmp r3, #0 80139b4: d00b beq.n 80139ce { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); 80139b6: 687b ldr r3, [r7, #4] 80139b8: 681b ldr r3, [r3, #0] 80139ba: 2201 movs r2, #1 80139bc: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_PE; 80139be: 687b ldr r3, [r7, #4] 80139c0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80139c4: f043 0201 orr.w r2, r3, #1 80139c8: 687b ldr r3, [r7, #4] 80139ca: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART frame error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80139ce: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 80139d2: f003 0302 and.w r3, r3, #2 80139d6: 2b00 cmp r3, #0 80139d8: d011 beq.n 80139fe 80139da: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 80139de: f003 0301 and.w r3, r3, #1 80139e2: 2b00 cmp r3, #0 80139e4: d00b beq.n 80139fe { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); 80139e6: 687b ldr r3, [r7, #4] 80139e8: 681b ldr r3, [r3, #0] 80139ea: 2202 movs r2, #2 80139ec: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_FE; 80139ee: 687b ldr r3, [r7, #4] 80139f0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 80139f4: f043 0204 orr.w r2, r3, #4 80139f8: 687b ldr r3, [r7, #4] 80139fa: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* UART noise error interrupt occurred --------------------------------------*/ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) 80139fe: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013a02: f003 0304 and.w r3, r3, #4 8013a06: 2b00 cmp r3, #0 8013a08: d011 beq.n 8013a2e 8013a0a: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8 8013a0e: f003 0301 and.w r3, r3, #1 8013a12: 2b00 cmp r3, #0 8013a14: d00b beq.n 8013a2e { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); 8013a16: 687b ldr r3, [r7, #4] 8013a18: 681b ldr r3, [r3, #0] 8013a1a: 2204 movs r2, #4 8013a1c: 621a str r2, [r3, #32] huart->ErrorCode |= HAL_UART_ERROR_NE; 8013a1e: 687b ldr r3, [r7, #4] 8013a20: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013a24: f043 0202 orr.w r2, r3, #2 8013a28: 687b ldr r3, [r7, #4] 8013a2a: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) 8013a2e: 687b ldr r3, [r7, #4] 8013a30: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90 8013a34: 2b00 cmp r3, #0 8013a36: d006 beq.n 8013a46 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 8013a38: 6878 ldr r0, [r7, #4] 8013a3a: f7fe f961 bl 8011d00 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8013a3e: 687b ldr r3, [r7, #4] 8013a40: 2200 movs r2, #0 8013a42: f8c3 2090 str.w r2, [r3, #144] @ 0x90 } } if (huart->RxXferCount == 0U) 8013a46: 687b ldr r3, [r7, #4] 8013a48: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013a4c: b29b uxth r3, r3 8013a4e: 2b00 cmp r3, #0 8013a50: f040 80a2 bne.w 8013b98 { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8013a54: 687b ldr r3, [r7, #4] 8013a56: 681b ldr r3, [r3, #0] 8013a58: 677b str r3, [r7, #116] @ 0x74 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a5a: 6f7b ldr r3, [r7, #116] @ 0x74 8013a5c: e853 3f00 ldrex r3, [r3] 8013a60: 673b str r3, [r7, #112] @ 0x70 return(result); 8013a62: 6f3b ldr r3, [r7, #112] @ 0x70 8013a64: f423 7380 bic.w r3, r3, #256 @ 0x100 8013a68: f8c7 309c str.w r3, [r7, #156] @ 0x9c 8013a6c: 687b ldr r3, [r7, #4] 8013a6e: 681b ldr r3, [r3, #0] 8013a70: 461a mov r2, r3 8013a72: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c 8013a76: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8013a7a: 67fa str r2, [r7, #124] @ 0x7c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013a7c: 6ff9 ldr r1, [r7, #124] @ 0x7c 8013a7e: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80 8013a82: e841 2300 strex r3, r2, [r1] 8013a86: 67bb str r3, [r7, #120] @ 0x78 return(result); 8013a88: 6fbb ldr r3, [r7, #120] @ 0x78 8013a8a: 2b00 cmp r3, #0 8013a8c: d1e2 bne.n 8013a54 /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 8013a8e: 687b ldr r3, [r7, #4] 8013a90: 681b ldr r3, [r3, #0] 8013a92: 3308 adds r3, #8 8013a94: 663b str r3, [r7, #96] @ 0x60 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013a96: 6e3b ldr r3, [r7, #96] @ 0x60 8013a98: e853 3f00 ldrex r3, [r3] 8013a9c: 65fb str r3, [r7, #92] @ 0x5c return(result); 8013a9e: 6dfa ldr r2, [r7, #92] @ 0x5c 8013aa0: 4b6e ldr r3, [pc, #440] @ (8013c5c ) 8013aa2: 4013 ands r3, r2 8013aa4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8013aa8: 687b ldr r3, [r7, #4] 8013aaa: 681b ldr r3, [r3, #0] 8013aac: 3308 adds r3, #8 8013aae: f8d7 2098 ldr.w r2, [r7, #152] @ 0x98 8013ab2: 66fa str r2, [r7, #108] @ 0x6c 8013ab4: 66bb str r3, [r7, #104] @ 0x68 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013ab6: 6eb9 ldr r1, [r7, #104] @ 0x68 8013ab8: 6efa ldr r2, [r7, #108] @ 0x6c 8013aba: e841 2300 strex r3, r2, [r1] 8013abe: 667b str r3, [r7, #100] @ 0x64 return(result); 8013ac0: 6e7b ldr r3, [r7, #100] @ 0x64 8013ac2: 2b00 cmp r3, #0 8013ac4: d1e3 bne.n 8013a8e /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 8013ac6: 687b ldr r3, [r7, #4] 8013ac8: 2220 movs r2, #32 8013aca: f8c3 208c str.w r2, [r3, #140] @ 0x8c /* Clear RxISR function pointer */ huart->RxISR = NULL; 8013ace: 687b ldr r3, [r7, #4] 8013ad0: 2200 movs r2, #0 8013ad2: 675a str r2, [r3, #116] @ 0x74 /* Initialize type of RxEvent to Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 8013ad4: 687b ldr r3, [r7, #4] 8013ad6: 2200 movs r2, #0 8013ad8: 671a str r2, [r3, #112] @ 0x70 if (!(IS_LPUART_INSTANCE(huart->Instance))) 8013ada: 687b ldr r3, [r7, #4] 8013adc: 681b ldr r3, [r3, #0] 8013ade: 4a60 ldr r2, [pc, #384] @ (8013c60 ) 8013ae0: 4293 cmp r3, r2 8013ae2: d021 beq.n 8013b28 { /* Check that USART RTOEN bit is set */ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) 8013ae4: 687b ldr r3, [r7, #4] 8013ae6: 681b ldr r3, [r3, #0] 8013ae8: 685b ldr r3, [r3, #4] 8013aea: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8013aee: 2b00 cmp r3, #0 8013af0: d01a beq.n 8013b28 { /* Enable the UART Receiver Timeout Interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); 8013af2: 687b ldr r3, [r7, #4] 8013af4: 681b ldr r3, [r3, #0] 8013af6: 64fb str r3, [r7, #76] @ 0x4c __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013af8: 6cfb ldr r3, [r7, #76] @ 0x4c 8013afa: e853 3f00 ldrex r3, [r3] 8013afe: 64bb str r3, [r7, #72] @ 0x48 return(result); 8013b00: 6cbb ldr r3, [r7, #72] @ 0x48 8013b02: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000 8013b06: f8c7 3094 str.w r3, [r7, #148] @ 0x94 8013b0a: 687b ldr r3, [r7, #4] 8013b0c: 681b ldr r3, [r3, #0] 8013b0e: 461a mov r2, r3 8013b10: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94 8013b14: 65bb str r3, [r7, #88] @ 0x58 8013b16: 657a str r2, [r7, #84] @ 0x54 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b18: 6d79 ldr r1, [r7, #84] @ 0x54 8013b1a: 6dba ldr r2, [r7, #88] @ 0x58 8013b1c: e841 2300 strex r3, r2, [r1] 8013b20: 653b str r3, [r7, #80] @ 0x50 return(result); 8013b22: 6d3b ldr r3, [r7, #80] @ 0x50 8013b24: 2b00 cmp r3, #0 8013b26: d1e4 bne.n 8013af2 } } /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013b28: 687b ldr r3, [r7, #4] 8013b2a: 6edb ldr r3, [r3, #108] @ 0x6c 8013b2c: 2b01 cmp r3, #1 8013b2e: d130 bne.n 8013b92 { /* Set reception type to Standard */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8013b30: 687b ldr r3, [r7, #4] 8013b32: 2200 movs r2, #0 8013b34: 66da str r2, [r3, #108] @ 0x6c /* Disable IDLE interrupt */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013b36: 687b ldr r3, [r7, #4] 8013b38: 681b ldr r3, [r3, #0] 8013b3a: 63bb str r3, [r7, #56] @ 0x38 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013b3c: 6bbb ldr r3, [r7, #56] @ 0x38 8013b3e: e853 3f00 ldrex r3, [r3] 8013b42: 637b str r3, [r7, #52] @ 0x34 return(result); 8013b44: 6b7b ldr r3, [r7, #52] @ 0x34 8013b46: f023 0310 bic.w r3, r3, #16 8013b4a: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8013b4e: 687b ldr r3, [r7, #4] 8013b50: 681b ldr r3, [r3, #0] 8013b52: 461a mov r2, r3 8013b54: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90 8013b58: 647b str r3, [r7, #68] @ 0x44 8013b5a: 643a str r2, [r7, #64] @ 0x40 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013b5c: 6c39 ldr r1, [r7, #64] @ 0x40 8013b5e: 6c7a ldr r2, [r7, #68] @ 0x44 8013b60: e841 2300 strex r3, r2, [r1] 8013b64: 63fb str r3, [r7, #60] @ 0x3c return(result); 8013b66: 6bfb ldr r3, [r7, #60] @ 0x3c 8013b68: 2b00 cmp r3, #0 8013b6a: d1e4 bne.n 8013b36 if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) 8013b6c: 687b ldr r3, [r7, #4] 8013b6e: 681b ldr r3, [r3, #0] 8013b70: 69db ldr r3, [r3, #28] 8013b72: f003 0310 and.w r3, r3, #16 8013b76: 2b10 cmp r3, #16 8013b78: d103 bne.n 8013b82 { /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013b7a: 687b ldr r3, [r7, #4] 8013b7c: 681b ldr r3, [r3, #0] 8013b7e: 2210 movs r2, #16 8013b80: 621a str r2, [r3, #32] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); 8013b82: 687b ldr r3, [r7, #4] 8013b84: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c 8013b88: 4619 mov r1, r3 8013b8a: 6878 ldr r0, [r7, #4] 8013b8c: f7f0 ffae bl 8004aec 8013b90: e002 b.n 8013b98 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxCpltCallback(huart); #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); 8013b92: 6878 ldr r0, [r7, #4] 8013b94: f7f0 ffa0 bl 8004ad8 while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) 8013b98: f8b7 30a6 ldrh.w r3, [r7, #166] @ 0xa6 8013b9c: 2b00 cmp r3, #0 8013b9e: d006 beq.n 8013bae 8013ba0: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4 8013ba4: f003 0320 and.w r3, r3, #32 8013ba8: 2b00 cmp r3, #0 8013baa: f47f aecd bne.w 8013948 /* When remaining number of bytes to receive is less than the RX FIFO threshold, next incoming frames are processed as if FIFO mode was disabled (i.e. one interrupt per received frame). */ rxdatacount = huart->RxXferCount; 8013bae: 687b ldr r3, [r7, #4] 8013bb0: f8b3 305e ldrh.w r3, [r3, #94] @ 0x5e 8013bb4: f8a7 308e strh.w r3, [r7, #142] @ 0x8e if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) 8013bb8: f8b7 308e ldrh.w r3, [r7, #142] @ 0x8e 8013bbc: 2b00 cmp r3, #0 8013bbe: d049 beq.n 8013c54 8013bc0: 687b ldr r3, [r7, #4] 8013bc2: f8b3 3068 ldrh.w r3, [r3, #104] @ 0x68 8013bc6: f8b7 208e ldrh.w r2, [r7, #142] @ 0x8e 8013bca: 429a cmp r2, r3 8013bcc: d242 bcs.n 8013c54 { /* Disable the UART RXFT interrupt*/ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); 8013bce: 687b ldr r3, [r7, #4] 8013bd0: 681b ldr r3, [r3, #0] 8013bd2: 3308 adds r3, #8 8013bd4: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013bd6: 6a7b ldr r3, [r7, #36] @ 0x24 8013bd8: e853 3f00 ldrex r3, [r3] 8013bdc: 623b str r3, [r7, #32] return(result); 8013bde: 6a3b ldr r3, [r7, #32] 8013be0: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 8013be4: f8c7 3088 str.w r3, [r7, #136] @ 0x88 8013be8: 687b ldr r3, [r7, #4] 8013bea: 681b ldr r3, [r3, #0] 8013bec: 3308 adds r3, #8 8013bee: f8d7 2088 ldr.w r2, [r7, #136] @ 0x88 8013bf2: 633a str r2, [r7, #48] @ 0x30 8013bf4: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013bf6: 6af9 ldr r1, [r7, #44] @ 0x2c 8013bf8: 6b3a ldr r2, [r7, #48] @ 0x30 8013bfa: e841 2300 strex r3, r2, [r1] 8013bfe: 62bb str r3, [r7, #40] @ 0x28 return(result); 8013c00: 6abb ldr r3, [r7, #40] @ 0x28 8013c02: 2b00 cmp r3, #0 8013c04: d1e3 bne.n 8013bce /* Update the RxISR function pointer */ huart->RxISR = UART_RxISR_16BIT; 8013c06: 687b ldr r3, [r7, #4] 8013c08: 4a16 ldr r2, [pc, #88] @ (8013c64 ) 8013c0a: 675a str r2, [r3, #116] @ 0x74 /* Enable the UART Data Register Not Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); 8013c0c: 687b ldr r3, [r7, #4] 8013c0e: 681b ldr r3, [r3, #0] 8013c10: 613b str r3, [r7, #16] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013c12: 693b ldr r3, [r7, #16] 8013c14: e853 3f00 ldrex r3, [r3] 8013c18: 60fb str r3, [r7, #12] return(result); 8013c1a: 68fb ldr r3, [r7, #12] 8013c1c: f043 0320 orr.w r3, r3, #32 8013c20: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8013c24: 687b ldr r3, [r7, #4] 8013c26: 681b ldr r3, [r3, #0] 8013c28: 461a mov r2, r3 8013c2a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84 8013c2e: 61fb str r3, [r7, #28] 8013c30: 61ba str r2, [r7, #24] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013c32: 69b9 ldr r1, [r7, #24] 8013c34: 69fa ldr r2, [r7, #28] 8013c36: e841 2300 strex r3, r2, [r1] 8013c3a: 617b str r3, [r7, #20] return(result); 8013c3c: 697b ldr r3, [r7, #20] 8013c3e: 2b00 cmp r3, #0 8013c40: d1e4 bne.n 8013c0c else { /* Clear RXNE interrupt flag */ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); } } 8013c42: e007 b.n 8013c54 __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); 8013c44: 687b ldr r3, [r7, #4] 8013c46: 681b ldr r3, [r3, #0] 8013c48: 699a ldr r2, [r3, #24] 8013c4a: 687b ldr r3, [r7, #4] 8013c4c: 681b ldr r3, [r3, #0] 8013c4e: f042 0208 orr.w r2, r2, #8 8013c52: 619a str r2, [r3, #24] } 8013c54: bf00 nop 8013c56: 37b8 adds r7, #184 @ 0xb8 8013c58: 46bd mov sp, r7 8013c5a: bd80 pop {r7, pc} 8013c5c: effffffe .word 0xeffffffe 8013c60: 58000c00 .word 0x58000c00 8013c64: 080133e9 .word 0x080133e9 08013c68 : * @brief UART wakeup from Stop mode callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) { 8013c68: b480 push {r7} 8013c6a: b083 sub sp, #12 8013c6c: af00 add r7, sp, #0 8013c6e: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_WakeupCallback can be implemented in the user file. */ } 8013c70: bf00 nop 8013c72: 370c adds r7, #12 8013c74: 46bd mov sp, r7 8013c76: f85d 7b04 ldr.w r7, [sp], #4 8013c7a: 4770 bx lr 08013c7c : * @brief UART RX Fifo full callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) { 8013c7c: b480 push {r7} 8013c7e: b083 sub sp, #12 8013c80: af00 add r7, sp, #0 8013c82: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. */ } 8013c84: bf00 nop 8013c86: 370c adds r7, #12 8013c88: 46bd mov sp, r7 8013c8a: f85d 7b04 ldr.w r7, [sp], #4 8013c8e: 4770 bx lr 08013c90 : * @brief UART TX Fifo empty callback. * @param huart UART handle. * @retval None */ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) { 8013c90: b480 push {r7} 8013c92: b083 sub sp, #12 8013c94: af00 add r7, sp, #0 8013c96: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. */ } 8013c98: bf00 nop 8013c9a: 370c adds r7, #12 8013c9c: 46bd mov sp, r7 8013c9e: f85d 7b04 ldr.w r7, [sp], #4 8013ca2: 4770 bx lr 08013ca4 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8013ca4: b480 push {r7} 8013ca6: b085 sub sp, #20 8013ca8: af00 add r7, sp, #0 8013caa: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 8013cac: 687b ldr r3, [r7, #4] 8013cae: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013cb2: 2b01 cmp r3, #1 8013cb4: d101 bne.n 8013cba 8013cb6: 2302 movs r3, #2 8013cb8: e027 b.n 8013d0a 8013cba: 687b ldr r3, [r7, #4] 8013cbc: 2201 movs r2, #1 8013cbe: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013cc2: 687b ldr r3, [r7, #4] 8013cc4: 2224 movs r2, #36 @ 0x24 8013cc6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013cca: 687b ldr r3, [r7, #4] 8013ccc: 681b ldr r3, [r3, #0] 8013cce: 681b ldr r3, [r3, #0] 8013cd0: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013cd2: 687b ldr r3, [r7, #4] 8013cd4: 681b ldr r3, [r3, #0] 8013cd6: 681a ldr r2, [r3, #0] 8013cd8: 687b ldr r3, [r7, #4] 8013cda: 681b ldr r3, [r3, #0] 8013cdc: f022 0201 bic.w r2, r2, #1 8013ce0: 601a str r2, [r3, #0] /* Enable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 8013ce2: 68fb ldr r3, [r7, #12] 8013ce4: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000 8013ce8: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 8013cea: 687b ldr r3, [r7, #4] 8013cec: 2200 movs r2, #0 8013cee: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013cf0: 687b ldr r3, [r7, #4] 8013cf2: 681b ldr r3, [r3, #0] 8013cf4: 68fa ldr r2, [r7, #12] 8013cf6: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013cf8: 687b ldr r3, [r7, #4] 8013cfa: 2220 movs r2, #32 8013cfc: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013d00: 687b ldr r3, [r7, #4] 8013d02: 2200 movs r2, #0 8013d04: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013d08: 2300 movs r3, #0 } 8013d0a: 4618 mov r0, r3 8013d0c: 3714 adds r7, #20 8013d0e: 46bd mov sp, r7 8013d10: f85d 7b04 ldr.w r7, [sp], #4 8013d14: 4770 bx lr 08013d16 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013d16: b580 push {r7, lr} 8013d18: b084 sub sp, #16 8013d1a: af00 add r7, sp, #0 8013d1c: 6078 str r0, [r7, #4] 8013d1e: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013d20: 687b ldr r3, [r7, #4] 8013d22: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013d26: 2b01 cmp r3, #1 8013d28: d101 bne.n 8013d2e 8013d2a: 2302 movs r3, #2 8013d2c: e02d b.n 8013d8a 8013d2e: 687b ldr r3, [r7, #4] 8013d30: 2201 movs r2, #1 8013d32: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013d36: 687b ldr r3, [r7, #4] 8013d38: 2224 movs r2, #36 @ 0x24 8013d3a: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013d3e: 687b ldr r3, [r7, #4] 8013d40: 681b ldr r3, [r3, #0] 8013d42: 681b ldr r3, [r3, #0] 8013d44: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013d46: 687b ldr r3, [r7, #4] 8013d48: 681b ldr r3, [r3, #0] 8013d4a: 681a ldr r2, [r3, #0] 8013d4c: 687b ldr r3, [r7, #4] 8013d4e: 681b ldr r3, [r3, #0] 8013d50: f022 0201 bic.w r2, r2, #1 8013d54: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8013d56: 687b ldr r3, [r7, #4] 8013d58: 681b ldr r3, [r3, #0] 8013d5a: 689b ldr r3, [r3, #8] 8013d5c: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000 8013d60: 687b ldr r3, [r7, #4] 8013d62: 681b ldr r3, [r3, #0] 8013d64: 683a ldr r2, [r7, #0] 8013d66: 430a orrs r2, r1 8013d68: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013d6a: 6878 ldr r0, [r7, #4] 8013d6c: f000 f8a0 bl 8013eb0 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013d70: 687b ldr r3, [r7, #4] 8013d72: 681b ldr r3, [r3, #0] 8013d74: 68fa ldr r2, [r7, #12] 8013d76: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013d78: 687b ldr r3, [r7, #4] 8013d7a: 2220 movs r2, #32 8013d7c: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013d80: 687b ldr r3, [r7, #4] 8013d82: 2200 movs r2, #0 8013d84: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013d88: 2300 movs r3, #0 } 8013d8a: 4618 mov r0, r3 8013d8c: 3710 adds r7, #16 8013d8e: 46bd mov sp, r7 8013d90: bd80 pop {r7, pc} 08013d92 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8013d92: b580 push {r7, lr} 8013d94: b084 sub sp, #16 8013d96: af00 add r7, sp, #0 8013d98: 6078 str r0, [r7, #4] 8013d9a: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8013d9c: 687b ldr r3, [r7, #4] 8013d9e: f893 3084 ldrb.w r3, [r3, #132] @ 0x84 8013da2: 2b01 cmp r3, #1 8013da4: d101 bne.n 8013daa 8013da6: 2302 movs r3, #2 8013da8: e02d b.n 8013e06 8013daa: 687b ldr r3, [r7, #4] 8013dac: 2201 movs r2, #1 8013dae: f883 2084 strb.w r2, [r3, #132] @ 0x84 huart->gState = HAL_UART_STATE_BUSY; 8013db2: 687b ldr r3, [r7, #4] 8013db4: 2224 movs r2, #36 @ 0x24 8013db6: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8013dba: 687b ldr r3, [r7, #4] 8013dbc: 681b ldr r3, [r3, #0] 8013dbe: 681b ldr r3, [r3, #0] 8013dc0: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8013dc2: 687b ldr r3, [r7, #4] 8013dc4: 681b ldr r3, [r3, #0] 8013dc6: 681a ldr r2, [r3, #0] 8013dc8: 687b ldr r3, [r7, #4] 8013dca: 681b ldr r3, [r3, #0] 8013dcc: f022 0201 bic.w r2, r2, #1 8013dd0: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8013dd2: 687b ldr r3, [r7, #4] 8013dd4: 681b ldr r3, [r3, #0] 8013dd6: 689b ldr r3, [r3, #8] 8013dd8: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000 8013ddc: 687b ldr r3, [r7, #4] 8013dde: 681b ldr r3, [r3, #0] 8013de0: 683a ldr r2, [r7, #0] 8013de2: 430a orrs r2, r1 8013de4: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8013de6: 6878 ldr r0, [r7, #4] 8013de8: f000 f862 bl 8013eb0 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8013dec: 687b ldr r3, [r7, #4] 8013dee: 681b ldr r3, [r3, #0] 8013df0: 68fa ldr r2, [r7, #12] 8013df2: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8013df4: 687b ldr r3, [r7, #4] 8013df6: 2220 movs r2, #32 8013df8: f8c3 2088 str.w r2, [r3, #136] @ 0x88 /* Process Unlocked */ __HAL_UNLOCK(huart); 8013dfc: 687b ldr r3, [r7, #4] 8013dfe: 2200 movs r2, #0 8013e00: f883 2084 strb.w r2, [r3, #132] @ 0x84 return HAL_OK; 8013e04: 2300 movs r3, #0 } 8013e06: 4618 mov r0, r3 8013e08: 3710 adds r7, #16 8013e0a: 46bd mov sp, r7 8013e0c: bd80 pop {r7, pc} 08013e0e : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8013e0e: b580 push {r7, lr} 8013e10: b08c sub sp, #48 @ 0x30 8013e12: af00 add r7, sp, #0 8013e14: 60f8 str r0, [r7, #12] 8013e16: 60b9 str r1, [r7, #8] 8013e18: 4613 mov r3, r2 8013e1a: 80fb strh r3, [r7, #6] HAL_StatusTypeDef status = HAL_OK; 8013e1c: 2300 movs r3, #0 8013e1e: f887 302f strb.w r3, [r7, #47] @ 0x2f /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8013e22: 68fb ldr r3, [r7, #12] 8013e24: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8013e28: 2b20 cmp r3, #32 8013e2a: d13b bne.n 8013ea4 { if ((pData == NULL) || (Size == 0U)) 8013e2c: 68bb ldr r3, [r7, #8] 8013e2e: 2b00 cmp r3, #0 8013e30: d002 beq.n 8013e38 8013e32: 88fb ldrh r3, [r7, #6] 8013e34: 2b00 cmp r3, #0 8013e36: d101 bne.n 8013e3c { return HAL_ERROR; 8013e38: 2301 movs r3, #1 8013e3a: e034 b.n 8013ea6 } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8013e3c: 68fb ldr r3, [r7, #12] 8013e3e: 2201 movs r2, #1 8013e40: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8013e42: 68fb ldr r3, [r7, #12] 8013e44: 2200 movs r2, #0 8013e46: 671a str r2, [r3, #112] @ 0x70 (void)UART_Start_Receive_IT(huart, pData, Size); 8013e48: 88fb ldrh r3, [r7, #6] 8013e4a: 461a mov r2, r3 8013e4c: 68b9 ldr r1, [r7, #8] 8013e4e: 68f8 ldr r0, [r7, #12] 8013e50: f7fe fe82 bl 8012b58 if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8013e54: 68fb ldr r3, [r7, #12] 8013e56: 6edb ldr r3, [r3, #108] @ 0x6c 8013e58: 2b01 cmp r3, #1 8013e5a: d11d bne.n 8013e98 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8013e5c: 68fb ldr r3, [r7, #12] 8013e5e: 681b ldr r3, [r3, #0] 8013e60: 2210 movs r2, #16 8013e62: 621a str r2, [r3, #32] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8013e64: 68fb ldr r3, [r7, #12] 8013e66: 681b ldr r3, [r3, #0] 8013e68: 61bb str r3, [r7, #24] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 8013e6a: 69bb ldr r3, [r7, #24] 8013e6c: e853 3f00 ldrex r3, [r3] 8013e70: 617b str r3, [r7, #20] return(result); 8013e72: 697b ldr r3, [r7, #20] 8013e74: f043 0310 orr.w r3, r3, #16 8013e78: 62bb str r3, [r7, #40] @ 0x28 8013e7a: 68fb ldr r3, [r7, #12] 8013e7c: 681b ldr r3, [r3, #0] 8013e7e: 461a mov r2, r3 8013e80: 6abb ldr r3, [r7, #40] @ 0x28 8013e82: 627b str r3, [r7, #36] @ 0x24 8013e84: 623a str r2, [r7, #32] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 8013e86: 6a39 ldr r1, [r7, #32] 8013e88: 6a7a ldr r2, [r7, #36] @ 0x24 8013e8a: e841 2300 strex r3, r2, [r1] 8013e8e: 61fb str r3, [r7, #28] return(result); 8013e90: 69fb ldr r3, [r7, #28] 8013e92: 2b00 cmp r3, #0 8013e94: d1e6 bne.n 8013e64 8013e96: e002 b.n 8013e9e { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8013e98: 2301 movs r3, #1 8013e9a: f887 302f strb.w r3, [r7, #47] @ 0x2f } return status; 8013e9e: f897 302f ldrb.w r3, [r7, #47] @ 0x2f 8013ea2: e000 b.n 8013ea6 } else { return HAL_BUSY; 8013ea4: 2302 movs r3, #2 } } 8013ea6: 4618 mov r0, r3 8013ea8: 3730 adds r7, #48 @ 0x30 8013eaa: 46bd mov sp, r7 8013eac: bd80 pop {r7, pc} ... 08013eb0 : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 8013eb0: b480 push {r7} 8013eb2: b085 sub sp, #20 8013eb4: af00 add r7, sp, #0 8013eb6: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8013eb8: 687b ldr r3, [r7, #4] 8013eba: 6e5b ldr r3, [r3, #100] @ 0x64 8013ebc: 2b00 cmp r3, #0 8013ebe: d108 bne.n 8013ed2 { huart->NbTxDataToProcess = 1U; 8013ec0: 687b ldr r3, [r7, #4] 8013ec2: 2201 movs r2, #1 8013ec4: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = 1U; 8013ec8: 687b ldr r3, [r7, #4] 8013eca: 2201 movs r2, #1 8013ecc: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 8013ed0: e031 b.n 8013f36 rx_fifo_depth = RX_FIFO_DEPTH; 8013ed2: 2310 movs r3, #16 8013ed4: 73fb strb r3, [r7, #15] tx_fifo_depth = TX_FIFO_DEPTH; 8013ed6: 2310 movs r3, #16 8013ed8: 73bb strb r3, [r7, #14] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8013eda: 687b ldr r3, [r7, #4] 8013edc: 681b ldr r3, [r3, #0] 8013ede: 689b ldr r3, [r3, #8] 8013ee0: 0e5b lsrs r3, r3, #25 8013ee2: b2db uxtb r3, r3 8013ee4: f003 0307 and.w r3, r3, #7 8013ee8: 737b strb r3, [r7, #13] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8013eea: 687b ldr r3, [r7, #4] 8013eec: 681b ldr r3, [r3, #0] 8013eee: 689b ldr r3, [r3, #8] 8013ef0: 0f5b lsrs r3, r3, #29 8013ef2: b2db uxtb r3, r3 8013ef4: f003 0307 and.w r3, r3, #7 8013ef8: 733b strb r3, [r7, #12] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013efa: 7bbb ldrb r3, [r7, #14] 8013efc: 7b3a ldrb r2, [r7, #12] 8013efe: 4911 ldr r1, [pc, #68] @ (8013f44 ) 8013f00: 5c8a ldrb r2, [r1, r2] 8013f02: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[tx_fifo_threshold]; 8013f06: 7b3a ldrb r2, [r7, #12] 8013f08: 490f ldr r1, [pc, #60] @ (8013f48 ) 8013f0a: 5c8a ldrb r2, [r1, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8013f0c: fb93 f3f2 sdiv r3, r3, r2 8013f10: b29a uxth r2, r3 8013f12: 687b ldr r3, [r7, #4] 8013f14: f8a3 206a strh.w r2, [r3, #106] @ 0x6a huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013f18: 7bfb ldrb r3, [r7, #15] 8013f1a: 7b7a ldrb r2, [r7, #13] 8013f1c: 4909 ldr r1, [pc, #36] @ (8013f44 ) 8013f1e: 5c8a ldrb r2, [r1, r2] 8013f20: fb02 f303 mul.w r3, r2, r3 (uint16_t)denominator[rx_fifo_threshold]; 8013f24: 7b7a ldrb r2, [r7, #13] 8013f26: 4908 ldr r1, [pc, #32] @ (8013f48 ) 8013f28: 5c8a ldrb r2, [r1, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8013f2a: fb93 f3f2 sdiv r3, r3, r2 8013f2e: b29a uxth r2, r3 8013f30: 687b ldr r3, [r7, #4] 8013f32: f8a3 2068 strh.w r2, [r3, #104] @ 0x68 } 8013f36: bf00 nop 8013f38: 3714 adds r7, #20 8013f3a: 46bd mov sp, r7 8013f3c: f85d 7b04 ldr.w r7, [sp], #4 8013f40: 4770 bx lr 8013f42: bf00 nop 8013f44: 0801873c .word 0x0801873c 8013f48: 08018744 .word 0x08018744 08013f4c <__NVIC_SetPriority>: { 8013f4c: b480 push {r7} 8013f4e: b083 sub sp, #12 8013f50: af00 add r7, sp, #0 8013f52: 4603 mov r3, r0 8013f54: 6039 str r1, [r7, #0] 8013f56: 80fb strh r3, [r7, #6] if ((int32_t)(IRQn) >= 0) 8013f58: f9b7 3006 ldrsh.w r3, [r7, #6] 8013f5c: 2b00 cmp r3, #0 8013f5e: db0a blt.n 8013f76 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013f60: 683b ldr r3, [r7, #0] 8013f62: b2da uxtb r2, r3 8013f64: 490c ldr r1, [pc, #48] @ (8013f98 <__NVIC_SetPriority+0x4c>) 8013f66: f9b7 3006 ldrsh.w r3, [r7, #6] 8013f6a: 0112 lsls r2, r2, #4 8013f6c: b2d2 uxtb r2, r2 8013f6e: 440b add r3, r1 8013f70: f883 2300 strb.w r2, [r3, #768] @ 0x300 } 8013f74: e00a b.n 8013f8c <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8013f76: 683b ldr r3, [r7, #0] 8013f78: b2da uxtb r2, r3 8013f7a: 4908 ldr r1, [pc, #32] @ (8013f9c <__NVIC_SetPriority+0x50>) 8013f7c: 88fb ldrh r3, [r7, #6] 8013f7e: f003 030f and.w r3, r3, #15 8013f82: 3b04 subs r3, #4 8013f84: 0112 lsls r2, r2, #4 8013f86: b2d2 uxtb r2, r2 8013f88: 440b add r3, r1 8013f8a: 761a strb r2, [r3, #24] } 8013f8c: bf00 nop 8013f8e: 370c adds r7, #12 8013f90: 46bd mov sp, r7 8013f92: f85d 7b04 ldr.w r7, [sp], #4 8013f96: 4770 bx lr 8013f98: e000e100 .word 0xe000e100 8013f9c: e000ed00 .word 0xe000ed00 08013fa0 : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { 8013fa0: b580 push {r7, lr} 8013fa2: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; 8013fa4: 4b05 ldr r3, [pc, #20] @ (8013fbc ) 8013fa6: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { 8013fa8: f002 fd1e bl 80169e8 8013fac: 4603 mov r3, r0 8013fae: 2b01 cmp r3, #1 8013fb0: d001 beq.n 8013fb6 /* Call tick handler */ xPortSysTickHandler(); 8013fb2: f003 ff31 bl 8017e18 } } 8013fb6: bf00 nop 8013fb8: bd80 pop {r7, pc} 8013fba: bf00 nop 8013fbc: e000e010 .word 0xe000e010 08013fc0 : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { 8013fc0: b580 push {r7, lr} 8013fc2: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); 8013fc4: 2100 movs r1, #0 8013fc6: f06f 0004 mvn.w r0, #4 8013fca: f7ff ffbf bl 8013f4c <__NVIC_SetPriority> #endif } 8013fce: bf00 nop 8013fd0: bd80 pop {r7, pc} ... 08013fd4 : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { 8013fd4: b480 push {r7} 8013fd6: b083 sub sp, #12 8013fd8: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8013fda: f3ef 8305 mrs r3, IPSR 8013fde: 603b str r3, [r7, #0] return(result); 8013fe0: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 8013fe2: 2b00 cmp r3, #0 8013fe4: d003 beq.n 8013fee stat = osErrorISR; 8013fe6: f06f 0305 mvn.w r3, #5 8013fea: 607b str r3, [r7, #4] 8013fec: e00c b.n 8014008 } else { if (KernelState == osKernelInactive) { 8013fee: 4b0a ldr r3, [pc, #40] @ (8014018 ) 8013ff0: 681b ldr r3, [r3, #0] 8013ff2: 2b00 cmp r3, #0 8013ff4: d105 bne.n 8014002 EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; 8013ff6: 4b08 ldr r3, [pc, #32] @ (8014018 ) 8013ff8: 2201 movs r2, #1 8013ffa: 601a str r2, [r3, #0] stat = osOK; 8013ffc: 2300 movs r3, #0 8013ffe: 607b str r3, [r7, #4] 8014000: e002 b.n 8014008 } else { stat = osError; 8014002: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014006: 607b str r3, [r7, #4] } } return (stat); 8014008: 687b ldr r3, [r7, #4] } 801400a: 4618 mov r0, r3 801400c: 370c adds r7, #12 801400e: 46bd mov sp, r7 8014010: f85d 7b04 ldr.w r7, [sp], #4 8014014: 4770 bx lr 8014016: bf00 nop 8014018: 24001064 .word 0x24001064 0801401c : } return (state); } osStatus_t osKernelStart (void) { 801401c: b580 push {r7, lr} 801401e: b082 sub sp, #8 8014020: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014022: f3ef 8305 mrs r3, IPSR 8014026: 603b str r3, [r7, #0] return(result); 8014028: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { 801402a: 2b00 cmp r3, #0 801402c: d003 beq.n 8014036 stat = osErrorISR; 801402e: f06f 0305 mvn.w r3, #5 8014032: 607b str r3, [r7, #4] 8014034: e010 b.n 8014058 } else { if (KernelState == osKernelReady) { 8014036: 4b0b ldr r3, [pc, #44] @ (8014064 ) 8014038: 681b ldr r3, [r3, #0] 801403a: 2b01 cmp r3, #1 801403c: d109 bne.n 8014052 /* Ensure SVC priority is at the reset value */ SVC_Setup(); 801403e: f7ff ffbf bl 8013fc0 /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; 8014042: 4b08 ldr r3, [pc, #32] @ (8014064 ) 8014044: 2202 movs r2, #2 8014046: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); 8014048: f002 f824 bl 8016094 stat = osOK; 801404c: 2300 movs r3, #0 801404e: 607b str r3, [r7, #4] 8014050: e002 b.n 8014058 } else { stat = osError; 8014052: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014056: 607b str r3, [r7, #4] } } return (stat); 8014058: 687b ldr r3, [r7, #4] } 801405a: 4618 mov r0, r3 801405c: 3708 adds r7, #8 801405e: 46bd mov sp, r7 8014060: bd80 pop {r7, pc} 8014062: bf00 nop 8014064: 24001064 .word 0x24001064 08014068 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { 8014068: b580 push {r7, lr} 801406a: b08e sub sp, #56 @ 0x38 801406c: af04 add r7, sp, #16 801406e: 60f8 str r0, [r7, #12] 8014070: 60b9 str r1, [r7, #8] 8014072: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; 8014074: 2300 movs r3, #0 8014076: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014078: f3ef 8305 mrs r3, IPSR 801407c: 617b str r3, [r7, #20] return(result); 801407e: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { 8014080: 2b00 cmp r3, #0 8014082: d17f bne.n 8014184 8014084: 68fb ldr r3, [r7, #12] 8014086: 2b00 cmp r3, #0 8014088: d07c beq.n 8014184 stack = configMINIMAL_STACK_SIZE; 801408a: f44f 7300 mov.w r3, #512 @ 0x200 801408e: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; 8014090: 2318 movs r3, #24 8014092: 61fb str r3, [r7, #28] name = NULL; 8014094: 2300 movs r3, #0 8014096: 627b str r3, [r7, #36] @ 0x24 mem = -1; 8014098: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 801409c: 61bb str r3, [r7, #24] if (attr != NULL) { 801409e: 687b ldr r3, [r7, #4] 80140a0: 2b00 cmp r3, #0 80140a2: d045 beq.n 8014130 if (attr->name != NULL) { 80140a4: 687b ldr r3, [r7, #4] 80140a6: 681b ldr r3, [r3, #0] 80140a8: 2b00 cmp r3, #0 80140aa: d002 beq.n 80140b2 name = attr->name; 80140ac: 687b ldr r3, [r7, #4] 80140ae: 681b ldr r3, [r3, #0] 80140b0: 627b str r3, [r7, #36] @ 0x24 } if (attr->priority != osPriorityNone) { 80140b2: 687b ldr r3, [r7, #4] 80140b4: 699b ldr r3, [r3, #24] 80140b6: 2b00 cmp r3, #0 80140b8: d002 beq.n 80140c0 prio = (UBaseType_t)attr->priority; 80140ba: 687b ldr r3, [r7, #4] 80140bc: 699b ldr r3, [r3, #24] 80140be: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { 80140c0: 69fb ldr r3, [r7, #28] 80140c2: 2b00 cmp r3, #0 80140c4: d008 beq.n 80140d8 80140c6: 69fb ldr r3, [r7, #28] 80140c8: 2b38 cmp r3, #56 @ 0x38 80140ca: d805 bhi.n 80140d8 80140cc: 687b ldr r3, [r7, #4] 80140ce: 685b ldr r3, [r3, #4] 80140d0: f003 0301 and.w r3, r3, #1 80140d4: 2b00 cmp r3, #0 80140d6: d001 beq.n 80140dc return (NULL); 80140d8: 2300 movs r3, #0 80140da: e054 b.n 8014186 } if (attr->stack_size > 0U) { 80140dc: 687b ldr r3, [r7, #4] 80140de: 695b ldr r3, [r3, #20] 80140e0: 2b00 cmp r3, #0 80140e2: d003 beq.n 80140ec /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); 80140e4: 687b ldr r3, [r7, #4] 80140e6: 695b ldr r3, [r3, #20] 80140e8: 089b lsrs r3, r3, #2 80140ea: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 80140ec: 687b ldr r3, [r7, #4] 80140ee: 689b ldr r3, [r3, #8] 80140f0: 2b00 cmp r3, #0 80140f2: d00e beq.n 8014112 80140f4: 687b ldr r3, [r7, #4] 80140f6: 68db ldr r3, [r3, #12] 80140f8: 2ba7 cmp r3, #167 @ 0xa7 80140fa: d90a bls.n 8014112 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 80140fc: 687b ldr r3, [r7, #4] 80140fe: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && 8014100: 2b00 cmp r3, #0 8014102: d006 beq.n 8014112 (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { 8014104: 687b ldr r3, [r7, #4] 8014106: 695b ldr r3, [r3, #20] 8014108: 2b00 cmp r3, #0 801410a: d002 beq.n 8014112 mem = 1; 801410c: 2301 movs r3, #1 801410e: 61bb str r3, [r7, #24] 8014110: e010 b.n 8014134 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { 8014112: 687b ldr r3, [r7, #4] 8014114: 689b ldr r3, [r3, #8] 8014116: 2b00 cmp r3, #0 8014118: d10c bne.n 8014134 801411a: 687b ldr r3, [r7, #4] 801411c: 68db ldr r3, [r3, #12] 801411e: 2b00 cmp r3, #0 8014120: d108 bne.n 8014134 8014122: 687b ldr r3, [r7, #4] 8014124: 691b ldr r3, [r3, #16] 8014126: 2b00 cmp r3, #0 8014128: d104 bne.n 8014134 mem = 0; 801412a: 2300 movs r3, #0 801412c: 61bb str r3, [r7, #24] 801412e: e001 b.n 8014134 } } } else { mem = 0; 8014130: 2300 movs r3, #0 8014132: 61bb str r3, [r7, #24] } if (mem == 1) { 8014134: 69bb ldr r3, [r7, #24] 8014136: 2b01 cmp r3, #1 8014138: d110 bne.n 801415c #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 801413a: 687b ldr r3, [r7, #4] 801413c: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); 801413e: 687a ldr r2, [r7, #4] 8014140: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, 8014142: 9202 str r2, [sp, #8] 8014144: 9301 str r3, [sp, #4] 8014146: 69fb ldr r3, [r7, #28] 8014148: 9300 str r3, [sp, #0] 801414a: 68bb ldr r3, [r7, #8] 801414c: 6a3a ldr r2, [r7, #32] 801414e: 6a79 ldr r1, [r7, #36] @ 0x24 8014150: 68f8 ldr r0, [r7, #12] 8014152: f001 fdac bl 8015cae 8014156: 4603 mov r3, r0 8014158: 613b str r3, [r7, #16] 801415a: e013 b.n 8014184 #endif } else { if (mem == 0) { 801415c: 69bb ldr r3, [r7, #24] 801415e: 2b00 cmp r3, #0 8014160: d110 bne.n 8014184 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { 8014162: 6a3b ldr r3, [r7, #32] 8014164: b29a uxth r2, r3 8014166: f107 0310 add.w r3, r7, #16 801416a: 9301 str r3, [sp, #4] 801416c: 69fb ldr r3, [r7, #28] 801416e: 9300 str r3, [sp, #0] 8014170: 68bb ldr r3, [r7, #8] 8014172: 6a79 ldr r1, [r7, #36] @ 0x24 8014174: 68f8 ldr r0, [r7, #12] 8014176: f001 fdfa bl 8015d6e 801417a: 4603 mov r3, r0 801417c: 2b01 cmp r3, #1 801417e: d001 beq.n 8014184 hTask = NULL; 8014180: 2300 movs r3, #0 8014182: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); 8014184: 693b ldr r3, [r7, #16] } 8014186: 4618 mov r0, r3 8014188: 3728 adds r7, #40 @ 0x28 801418a: 46bd mov sp, r7 801418c: bd80 pop {r7, pc} 0801418e : /* Return flags before clearing */ return (rflags); } #endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ osStatus_t osDelay (uint32_t ticks) { 801418e: b580 push {r7, lr} 8014190: b084 sub sp, #16 8014192: af00 add r7, sp, #0 8014194: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014196: f3ef 8305 mrs r3, IPSR 801419a: 60bb str r3, [r7, #8] return(result); 801419c: 68bb ldr r3, [r7, #8] osStatus_t stat; if (IS_IRQ()) { 801419e: 2b00 cmp r3, #0 80141a0: d003 beq.n 80141aa stat = osErrorISR; 80141a2: f06f 0305 mvn.w r3, #5 80141a6: 60fb str r3, [r7, #12] 80141a8: e007 b.n 80141ba } else { stat = osOK; 80141aa: 2300 movs r3, #0 80141ac: 60fb str r3, [r7, #12] if (ticks != 0U) { 80141ae: 687b ldr r3, [r7, #4] 80141b0: 2b00 cmp r3, #0 80141b2: d002 beq.n 80141ba vTaskDelay(ticks); 80141b4: 6878 ldr r0, [r7, #4] 80141b6: f001 ff37 bl 8016028 } } return (stat); 80141ba: 68fb ldr r3, [r7, #12] } 80141bc: 4618 mov r0, r3 80141be: 3710 adds r7, #16 80141c0: 46bd mov sp, r7 80141c2: bd80 pop {r7, pc} 080141c4 : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_TIMER == 1) static void TimerCallback (TimerHandle_t hTimer) { 80141c4: b580 push {r7, lr} 80141c6: b084 sub sp, #16 80141c8: af00 add r7, sp, #0 80141ca: 6078 str r0, [r7, #4] TimerCallback_t *callb; callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); 80141cc: 6878 ldr r0, [r7, #4] 80141ce: f003 fc3d bl 8017a4c 80141d2: 60f8 str r0, [r7, #12] if (callb != NULL) { 80141d4: 68fb ldr r3, [r7, #12] 80141d6: 2b00 cmp r3, #0 80141d8: d005 beq.n 80141e6 callb->func (callb->arg); 80141da: 68fb ldr r3, [r7, #12] 80141dc: 681b ldr r3, [r3, #0] 80141de: 68fa ldr r2, [r7, #12] 80141e0: 6852 ldr r2, [r2, #4] 80141e2: 4610 mov r0, r2 80141e4: 4798 blx r3 } } 80141e6: bf00 nop 80141e8: 3710 adds r7, #16 80141ea: 46bd mov sp, r7 80141ec: bd80 pop {r7, pc} ... 080141f0 : osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { 80141f0: b580 push {r7, lr} 80141f2: b08c sub sp, #48 @ 0x30 80141f4: af02 add r7, sp, #8 80141f6: 60f8 str r0, [r7, #12] 80141f8: 607a str r2, [r7, #4] 80141fa: 603b str r3, [r7, #0] 80141fc: 460b mov r3, r1 80141fe: 72fb strb r3, [r7, #11] TimerHandle_t hTimer; TimerCallback_t *callb; UBaseType_t reload; int32_t mem; hTimer = NULL; 8014200: 2300 movs r3, #0 8014202: 623b str r3, [r7, #32] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014204: f3ef 8305 mrs r3, IPSR 8014208: 613b str r3, [r7, #16] return(result); 801420a: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (func != NULL)) { 801420c: 2b00 cmp r3, #0 801420e: d163 bne.n 80142d8 8014210: 68fb ldr r3, [r7, #12] 8014212: 2b00 cmp r3, #0 8014214: d060 beq.n 80142d8 /* Allocate memory to store callback function and argument */ callb = pvPortMalloc (sizeof(TimerCallback_t)); 8014216: 2008 movs r0, #8 8014218: f003 fe90 bl 8017f3c 801421c: 6178 str r0, [r7, #20] if (callb != NULL) { 801421e: 697b ldr r3, [r7, #20] 8014220: 2b00 cmp r3, #0 8014222: d059 beq.n 80142d8 callb->func = func; 8014224: 697b ldr r3, [r7, #20] 8014226: 68fa ldr r2, [r7, #12] 8014228: 601a str r2, [r3, #0] callb->arg = argument; 801422a: 697b ldr r3, [r7, #20] 801422c: 687a ldr r2, [r7, #4] 801422e: 605a str r2, [r3, #4] if (type == osTimerOnce) { 8014230: 7afb ldrb r3, [r7, #11] 8014232: 2b00 cmp r3, #0 8014234: d102 bne.n 801423c reload = pdFALSE; 8014236: 2300 movs r3, #0 8014238: 61fb str r3, [r7, #28] 801423a: e001 b.n 8014240 } else { reload = pdTRUE; 801423c: 2301 movs r3, #1 801423e: 61fb str r3, [r7, #28] } mem = -1; 8014240: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8014244: 61bb str r3, [r7, #24] name = NULL; 8014246: 2300 movs r3, #0 8014248: 627b str r3, [r7, #36] @ 0x24 if (attr != NULL) { 801424a: 683b ldr r3, [r7, #0] 801424c: 2b00 cmp r3, #0 801424e: d01c beq.n 801428a if (attr->name != NULL) { 8014250: 683b ldr r3, [r7, #0] 8014252: 681b ldr r3, [r3, #0] 8014254: 2b00 cmp r3, #0 8014256: d002 beq.n 801425e name = attr->name; 8014258: 683b ldr r3, [r7, #0] 801425a: 681b ldr r3, [r3, #0] 801425c: 627b str r3, [r7, #36] @ 0x24 } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { 801425e: 683b ldr r3, [r7, #0] 8014260: 689b ldr r3, [r3, #8] 8014262: 2b00 cmp r3, #0 8014264: d006 beq.n 8014274 8014266: 683b ldr r3, [r7, #0] 8014268: 68db ldr r3, [r3, #12] 801426a: 2b2b cmp r3, #43 @ 0x2b 801426c: d902 bls.n 8014274 mem = 1; 801426e: 2301 movs r3, #1 8014270: 61bb str r3, [r7, #24] 8014272: e00c b.n 801428e } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 8014274: 683b ldr r3, [r7, #0] 8014276: 689b ldr r3, [r3, #8] 8014278: 2b00 cmp r3, #0 801427a: d108 bne.n 801428e 801427c: 683b ldr r3, [r7, #0] 801427e: 68db ldr r3, [r3, #12] 8014280: 2b00 cmp r3, #0 8014282: d104 bne.n 801428e mem = 0; 8014284: 2300 movs r3, #0 8014286: 61bb str r3, [r7, #24] 8014288: e001 b.n 801428e } } } else { mem = 0; 801428a: 2300 movs r3, #0 801428c: 61bb str r3, [r7, #24] } if (mem == 1) { 801428e: 69bb ldr r3, [r7, #24] 8014290: 2b01 cmp r3, #1 8014292: d10c bne.n 80142ae #if (configSUPPORT_STATIC_ALLOCATION == 1) hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); 8014294: 683b ldr r3, [r7, #0] 8014296: 689b ldr r3, [r3, #8] 8014298: 9301 str r3, [sp, #4] 801429a: 4b12 ldr r3, [pc, #72] @ (80142e4 ) 801429c: 9300 str r3, [sp, #0] 801429e: 697b ldr r3, [r7, #20] 80142a0: 69fa ldr r2, [r7, #28] 80142a2: 2101 movs r1, #1 80142a4: 6a78 ldr r0, [r7, #36] @ 0x24 80142a6: f003 f81a bl 80172de 80142aa: 6238 str r0, [r7, #32] 80142ac: e00b b.n 80142c6 #endif } else { if (mem == 0) { 80142ae: 69bb ldr r3, [r7, #24] 80142b0: 2b00 cmp r3, #0 80142b2: d108 bne.n 80142c6 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); 80142b4: 4b0b ldr r3, [pc, #44] @ (80142e4 ) 80142b6: 9300 str r3, [sp, #0] 80142b8: 697b ldr r3, [r7, #20] 80142ba: 69fa ldr r2, [r7, #28] 80142bc: 2101 movs r1, #1 80142be: 6a78 ldr r0, [r7, #36] @ 0x24 80142c0: f002 ffec bl 801729c 80142c4: 6238 str r0, [r7, #32] #endif } } if ((hTimer == NULL) && (callb != NULL)) { 80142c6: 6a3b ldr r3, [r7, #32] 80142c8: 2b00 cmp r3, #0 80142ca: d105 bne.n 80142d8 80142cc: 697b ldr r3, [r7, #20] 80142ce: 2b00 cmp r3, #0 80142d0: d002 beq.n 80142d8 vPortFree (callb); 80142d2: 6978 ldr r0, [r7, #20] 80142d4: f003 ff00 bl 80180d8 } } } return ((osTimerId_t)hTimer); 80142d8: 6a3b ldr r3, [r7, #32] } 80142da: 4618 mov r0, r3 80142dc: 3728 adds r7, #40 @ 0x28 80142de: 46bd mov sp, r7 80142e0: bd80 pop {r7, pc} 80142e2: bf00 nop 80142e4: 080141c5 .word 0x080141c5 080142e8 : } return (p); } osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { 80142e8: b580 push {r7, lr} 80142ea: b088 sub sp, #32 80142ec: af02 add r7, sp, #8 80142ee: 6078 str r0, [r7, #4] 80142f0: 6039 str r1, [r7, #0] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 80142f2: 687b ldr r3, [r7, #4] 80142f4: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80142f6: f3ef 8305 mrs r3, IPSR 80142fa: 60fb str r3, [r7, #12] return(result); 80142fc: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 80142fe: 2b00 cmp r3, #0 8014300: d003 beq.n 801430a stat = osErrorISR; 8014302: f06f 0305 mvn.w r3, #5 8014306: 617b str r3, [r7, #20] 8014308: e017 b.n 801433a } else if (hTimer == NULL) { 801430a: 693b ldr r3, [r7, #16] 801430c: 2b00 cmp r3, #0 801430e: d103 bne.n 8014318 stat = osErrorParameter; 8014310: f06f 0303 mvn.w r3, #3 8014314: 617b str r3, [r7, #20] 8014316: e010 b.n 801433a } else { if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { 8014318: 2300 movs r3, #0 801431a: 9300 str r3, [sp, #0] 801431c: 2300 movs r3, #0 801431e: 683a ldr r2, [r7, #0] 8014320: 2104 movs r1, #4 8014322: 6938 ldr r0, [r7, #16] 8014324: f003 f858 bl 80173d8 8014328: 4603 mov r3, r0 801432a: 2b01 cmp r3, #1 801432c: d102 bne.n 8014334 stat = osOK; 801432e: 2300 movs r3, #0 8014330: 617b str r3, [r7, #20] 8014332: e002 b.n 801433a } else { stat = osErrorResource; 8014334: f06f 0302 mvn.w r3, #2 8014338: 617b str r3, [r7, #20] } } return (stat); 801433a: 697b ldr r3, [r7, #20] } 801433c: 4618 mov r0, r3 801433e: 3718 adds r7, #24 8014340: 46bd mov sp, r7 8014342: bd80 pop {r7, pc} 08014344 : osStatus_t osTimerStop (osTimerId_t timer_id) { 8014344: b580 push {r7, lr} 8014346: b088 sub sp, #32 8014348: af02 add r7, sp, #8 801434a: 6078 str r0, [r7, #4] TimerHandle_t hTimer = (TimerHandle_t)timer_id; 801434c: 687b ldr r3, [r7, #4] 801434e: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014350: f3ef 8305 mrs r3, IPSR 8014354: 60fb str r3, [r7, #12] return(result); 8014356: 68fb ldr r3, [r7, #12] osStatus_t stat; if (IS_IRQ()) { 8014358: 2b00 cmp r3, #0 801435a: d003 beq.n 8014364 stat = osErrorISR; 801435c: f06f 0305 mvn.w r3, #5 8014360: 617b str r3, [r7, #20] 8014362: e021 b.n 80143a8 } else if (hTimer == NULL) { 8014364: 693b ldr r3, [r7, #16] 8014366: 2b00 cmp r3, #0 8014368: d103 bne.n 8014372 stat = osErrorParameter; 801436a: f06f 0303 mvn.w r3, #3 801436e: 617b str r3, [r7, #20] 8014370: e01a b.n 80143a8 } else { if (xTimerIsTimerActive (hTimer) == pdFALSE) { 8014372: 6938 ldr r0, [r7, #16] 8014374: f003 fb40 bl 80179f8 8014378: 4603 mov r3, r0 801437a: 2b00 cmp r3, #0 801437c: d103 bne.n 8014386 stat = osErrorResource; 801437e: f06f 0302 mvn.w r3, #2 8014382: 617b str r3, [r7, #20] 8014384: e010 b.n 80143a8 } else { if (xTimerStop (hTimer, 0) == pdPASS) { 8014386: 2300 movs r3, #0 8014388: 9300 str r3, [sp, #0] 801438a: 2300 movs r3, #0 801438c: 2200 movs r2, #0 801438e: 2103 movs r1, #3 8014390: 6938 ldr r0, [r7, #16] 8014392: f003 f821 bl 80173d8 8014396: 4603 mov r3, r0 8014398: 2b01 cmp r3, #1 801439a: d102 bne.n 80143a2 stat = osOK; 801439c: 2300 movs r3, #0 801439e: 617b str r3, [r7, #20] 80143a0: e002 b.n 80143a8 } else { stat = osError; 80143a2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80143a6: 617b str r3, [r7, #20] } } } return (stat); 80143a8: 697b ldr r3, [r7, #20] } 80143aa: 4618 mov r0, r3 80143ac: 3718 adds r7, #24 80143ae: 46bd mov sp, r7 80143b0: bd80 pop {r7, pc} 080143b2 : } /*---------------------------------------------------------------------------*/ #if (configUSE_OS2_MUTEX == 1) osMutexId_t osMutexNew (const osMutexAttr_t *attr) { 80143b2: b580 push {r7, lr} 80143b4: b088 sub sp, #32 80143b6: af00 add r7, sp, #0 80143b8: 6078 str r0, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hMutex = NULL; 80143ba: 2300 movs r3, #0 80143bc: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80143be: f3ef 8305 mrs r3, IPSR 80143c2: 60bb str r3, [r7, #8] return(result); 80143c4: 68bb ldr r3, [r7, #8] if (!IS_IRQ()) { 80143c6: 2b00 cmp r3, #0 80143c8: d174 bne.n 80144b4 if (attr != NULL) { 80143ca: 687b ldr r3, [r7, #4] 80143cc: 2b00 cmp r3, #0 80143ce: d003 beq.n 80143d8 type = attr->attr_bits; 80143d0: 687b ldr r3, [r7, #4] 80143d2: 685b ldr r3, [r3, #4] 80143d4: 61bb str r3, [r7, #24] 80143d6: e001 b.n 80143dc } else { type = 0U; 80143d8: 2300 movs r3, #0 80143da: 61bb str r3, [r7, #24] } if ((type & osMutexRecursive) == osMutexRecursive) { 80143dc: 69bb ldr r3, [r7, #24] 80143de: f003 0301 and.w r3, r3, #1 80143e2: 2b00 cmp r3, #0 80143e4: d002 beq.n 80143ec rmtx = 1U; 80143e6: 2301 movs r3, #1 80143e8: 617b str r3, [r7, #20] 80143ea: e001 b.n 80143f0 } else { rmtx = 0U; 80143ec: 2300 movs r3, #0 80143ee: 617b str r3, [r7, #20] } if ((type & osMutexRobust) != osMutexRobust) { 80143f0: 69bb ldr r3, [r7, #24] 80143f2: f003 0308 and.w r3, r3, #8 80143f6: 2b00 cmp r3, #0 80143f8: d15c bne.n 80144b4 mem = -1; 80143fa: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80143fe: 613b str r3, [r7, #16] if (attr != NULL) { 8014400: 687b ldr r3, [r7, #4] 8014402: 2b00 cmp r3, #0 8014404: d015 beq.n 8014432 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { 8014406: 687b ldr r3, [r7, #4] 8014408: 689b ldr r3, [r3, #8] 801440a: 2b00 cmp r3, #0 801440c: d006 beq.n 801441c 801440e: 687b ldr r3, [r7, #4] 8014410: 68db ldr r3, [r3, #12] 8014412: 2b4f cmp r3, #79 @ 0x4f 8014414: d902 bls.n 801441c mem = 1; 8014416: 2301 movs r3, #1 8014418: 613b str r3, [r7, #16] 801441a: e00c b.n 8014436 } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { 801441c: 687b ldr r3, [r7, #4] 801441e: 689b ldr r3, [r3, #8] 8014420: 2b00 cmp r3, #0 8014422: d108 bne.n 8014436 8014424: 687b ldr r3, [r7, #4] 8014426: 68db ldr r3, [r3, #12] 8014428: 2b00 cmp r3, #0 801442a: d104 bne.n 8014436 mem = 0; 801442c: 2300 movs r3, #0 801442e: 613b str r3, [r7, #16] 8014430: e001 b.n 8014436 } } } else { mem = 0; 8014432: 2300 movs r3, #0 8014434: 613b str r3, [r7, #16] } if (mem == 1) { 8014436: 693b ldr r3, [r7, #16] 8014438: 2b01 cmp r3, #1 801443a: d112 bne.n 8014462 #if (configSUPPORT_STATIC_ALLOCATION == 1) if (rmtx != 0U) { 801443c: 697b ldr r3, [r7, #20] 801443e: 2b00 cmp r3, #0 8014440: d007 beq.n 8014452 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); 8014442: 687b ldr r3, [r7, #4] 8014444: 689b ldr r3, [r3, #8] 8014446: 4619 mov r1, r3 8014448: 2004 movs r0, #4 801444a: f000 fc50 bl 8014cee 801444e: 61f8 str r0, [r7, #28] 8014450: e016 b.n 8014480 #endif } else { hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); 8014452: 687b ldr r3, [r7, #4] 8014454: 689b ldr r3, [r3, #8] 8014456: 4619 mov r1, r3 8014458: 2001 movs r0, #1 801445a: f000 fc48 bl 8014cee 801445e: 61f8 str r0, [r7, #28] 8014460: e00e b.n 8014480 } #endif } else { if (mem == 0) { 8014462: 693b ldr r3, [r7, #16] 8014464: 2b00 cmp r3, #0 8014466: d10b bne.n 8014480 #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (rmtx != 0U) { 8014468: 697b ldr r3, [r7, #20] 801446a: 2b00 cmp r3, #0 801446c: d004 beq.n 8014478 #if (configUSE_RECURSIVE_MUTEXES == 1) hMutex = xSemaphoreCreateRecursiveMutex (); 801446e: 2004 movs r0, #4 8014470: f000 fc25 bl 8014cbe 8014474: 61f8 str r0, [r7, #28] 8014476: e003 b.n 8014480 #endif } else { hMutex = xSemaphoreCreateMutex (); 8014478: 2001 movs r0, #1 801447a: f000 fc20 bl 8014cbe 801447e: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hMutex != NULL) { 8014480: 69fb ldr r3, [r7, #28] 8014482: 2b00 cmp r3, #0 8014484: d00c beq.n 80144a0 if (attr != NULL) { 8014486: 687b ldr r3, [r7, #4] 8014488: 2b00 cmp r3, #0 801448a: d003 beq.n 8014494 name = attr->name; 801448c: 687b ldr r3, [r7, #4] 801448e: 681b ldr r3, [r3, #0] 8014490: 60fb str r3, [r7, #12] 8014492: e001 b.n 8014498 } else { name = NULL; 8014494: 2300 movs r3, #0 8014496: 60fb str r3, [r7, #12] } vQueueAddToRegistry (hMutex, name); 8014498: 68f9 ldr r1, [r7, #12] 801449a: 69f8 ldr r0, [r7, #28] 801449c: f001 f9ea bl 8015874 } #endif if ((hMutex != NULL) && (rmtx != 0U)) { 80144a0: 69fb ldr r3, [r7, #28] 80144a2: 2b00 cmp r3, #0 80144a4: d006 beq.n 80144b4 80144a6: 697b ldr r3, [r7, #20] 80144a8: 2b00 cmp r3, #0 80144aa: d003 beq.n 80144b4 hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); 80144ac: 69fb ldr r3, [r7, #28] 80144ae: f043 0301 orr.w r3, r3, #1 80144b2: 61fb str r3, [r7, #28] } } } return ((osMutexId_t)hMutex); 80144b4: 69fb ldr r3, [r7, #28] } 80144b6: 4618 mov r0, r3 80144b8: 3720 adds r7, #32 80144ba: 46bd mov sp, r7 80144bc: bd80 pop {r7, pc} 080144be : osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { 80144be: b580 push {r7, lr} 80144c0: b086 sub sp, #24 80144c2: af00 add r7, sp, #0 80144c4: 6078 str r0, [r7, #4] 80144c6: 6039 str r1, [r7, #0] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 80144c8: 687b ldr r3, [r7, #4] 80144ca: f023 0301 bic.w r3, r3, #1 80144ce: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 80144d0: 687b ldr r3, [r7, #4] 80144d2: f003 0301 and.w r3, r3, #1 80144d6: 60fb str r3, [r7, #12] stat = osOK; 80144d8: 2300 movs r3, #0 80144da: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80144dc: f3ef 8305 mrs r3, IPSR 80144e0: 60bb str r3, [r7, #8] return(result); 80144e2: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 80144e4: 2b00 cmp r3, #0 80144e6: d003 beq.n 80144f0 stat = osErrorISR; 80144e8: f06f 0305 mvn.w r3, #5 80144ec: 617b str r3, [r7, #20] 80144ee: e02c b.n 801454a } else if (hMutex == NULL) { 80144f0: 693b ldr r3, [r7, #16] 80144f2: 2b00 cmp r3, #0 80144f4: d103 bne.n 80144fe stat = osErrorParameter; 80144f6: f06f 0303 mvn.w r3, #3 80144fa: 617b str r3, [r7, #20] 80144fc: e025 b.n 801454a } else { if (rmtx != 0U) { 80144fe: 68fb ldr r3, [r7, #12] 8014500: 2b00 cmp r3, #0 8014502: d011 beq.n 8014528 #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { 8014504: 6839 ldr r1, [r7, #0] 8014506: 6938 ldr r0, [r7, #16] 8014508: f000 fc41 bl 8014d8e 801450c: 4603 mov r3, r0 801450e: 2b01 cmp r3, #1 8014510: d01b beq.n 801454a if (timeout != 0U) { 8014512: 683b ldr r3, [r7, #0] 8014514: 2b00 cmp r3, #0 8014516: d003 beq.n 8014520 stat = osErrorTimeout; 8014518: f06f 0301 mvn.w r3, #1 801451c: 617b str r3, [r7, #20] 801451e: e014 b.n 801454a } else { stat = osErrorResource; 8014520: f06f 0302 mvn.w r3, #2 8014524: 617b str r3, [r7, #20] 8014526: e010 b.n 801454a } } #endif } else { if (xSemaphoreTake (hMutex, timeout) != pdPASS) { 8014528: 6839 ldr r1, [r7, #0] 801452a: 6938 ldr r0, [r7, #16] 801452c: f000 fee8 bl 8015300 8014530: 4603 mov r3, r0 8014532: 2b01 cmp r3, #1 8014534: d009 beq.n 801454a if (timeout != 0U) { 8014536: 683b ldr r3, [r7, #0] 8014538: 2b00 cmp r3, #0 801453a: d003 beq.n 8014544 stat = osErrorTimeout; 801453c: f06f 0301 mvn.w r3, #1 8014540: 617b str r3, [r7, #20] 8014542: e002 b.n 801454a } else { stat = osErrorResource; 8014544: f06f 0302 mvn.w r3, #2 8014548: 617b str r3, [r7, #20] } } } } return (stat); 801454a: 697b ldr r3, [r7, #20] } 801454c: 4618 mov r0, r3 801454e: 3718 adds r7, #24 8014550: 46bd mov sp, r7 8014552: bd80 pop {r7, pc} 08014554 : osStatus_t osMutexRelease (osMutexId_t mutex_id) { 8014554: b580 push {r7, lr} 8014556: b086 sub sp, #24 8014558: af00 add r7, sp, #0 801455a: 6078 str r0, [r7, #4] SemaphoreHandle_t hMutex; osStatus_t stat; uint32_t rmtx; hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); 801455c: 687b ldr r3, [r7, #4] 801455e: f023 0301 bic.w r3, r3, #1 8014562: 613b str r3, [r7, #16] rmtx = (uint32_t)mutex_id & 1U; 8014564: 687b ldr r3, [r7, #4] 8014566: f003 0301 and.w r3, r3, #1 801456a: 60fb str r3, [r7, #12] stat = osOK; 801456c: 2300 movs r3, #0 801456e: 617b str r3, [r7, #20] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8014570: f3ef 8305 mrs r3, IPSR 8014574: 60bb str r3, [r7, #8] return(result); 8014576: 68bb ldr r3, [r7, #8] if (IS_IRQ()) { 8014578: 2b00 cmp r3, #0 801457a: d003 beq.n 8014584 stat = osErrorISR; 801457c: f06f 0305 mvn.w r3, #5 8014580: 617b str r3, [r7, #20] 8014582: e01f b.n 80145c4 } else if (hMutex == NULL) { 8014584: 693b ldr r3, [r7, #16] 8014586: 2b00 cmp r3, #0 8014588: d103 bne.n 8014592 stat = osErrorParameter; 801458a: f06f 0303 mvn.w r3, #3 801458e: 617b str r3, [r7, #20] 8014590: e018 b.n 80145c4 } else { if (rmtx != 0U) { 8014592: 68fb ldr r3, [r7, #12] 8014594: 2b00 cmp r3, #0 8014596: d009 beq.n 80145ac #if (configUSE_RECURSIVE_MUTEXES == 1) if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { 8014598: 6938 ldr r0, [r7, #16] 801459a: f000 fbc3 bl 8014d24 801459e: 4603 mov r3, r0 80145a0: 2b01 cmp r3, #1 80145a2: d00f beq.n 80145c4 stat = osErrorResource; 80145a4: f06f 0302 mvn.w r3, #2 80145a8: 617b str r3, [r7, #20] 80145aa: e00b b.n 80145c4 } #endif } else { if (xSemaphoreGive (hMutex) != pdPASS) { 80145ac: 2300 movs r3, #0 80145ae: 2200 movs r2, #0 80145b0: 2100 movs r1, #0 80145b2: 6938 ldr r0, [r7, #16] 80145b4: f000 fc22 bl 8014dfc 80145b8: 4603 mov r3, r0 80145ba: 2b01 cmp r3, #1 80145bc: d002 beq.n 80145c4 stat = osErrorResource; 80145be: f06f 0302 mvn.w r3, #2 80145c2: 617b str r3, [r7, #20] } } } return (stat); 80145c4: 697b ldr r3, [r7, #20] } 80145c6: 4618 mov r0, r3 80145c8: 3718 adds r7, #24 80145ca: 46bd mov sp, r7 80145cc: bd80 pop {r7, pc} 080145ce : return (stat); } /*---------------------------------------------------------------------------*/ osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { 80145ce: b580 push {r7, lr} 80145d0: b08a sub sp, #40 @ 0x28 80145d2: af02 add r7, sp, #8 80145d4: 60f8 str r0, [r7, #12] 80145d6: 60b9 str r1, [r7, #8] 80145d8: 607a str r2, [r7, #4] int32_t mem; #if (configQUEUE_REGISTRY_SIZE > 0) const char *name; #endif hQueue = NULL; 80145da: 2300 movs r3, #0 80145dc: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80145de: f3ef 8305 mrs r3, IPSR 80145e2: 613b str r3, [r7, #16] return(result); 80145e4: 693b ldr r3, [r7, #16] if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { 80145e6: 2b00 cmp r3, #0 80145e8: d15f bne.n 80146aa 80145ea: 68fb ldr r3, [r7, #12] 80145ec: 2b00 cmp r3, #0 80145ee: d05c beq.n 80146aa 80145f0: 68bb ldr r3, [r7, #8] 80145f2: 2b00 cmp r3, #0 80145f4: d059 beq.n 80146aa mem = -1; 80145f6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80145fa: 61bb str r3, [r7, #24] if (attr != NULL) { 80145fc: 687b ldr r3, [r7, #4] 80145fe: 2b00 cmp r3, #0 8014600: d029 beq.n 8014656 if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8014602: 687b ldr r3, [r7, #4] 8014604: 689b ldr r3, [r3, #8] 8014606: 2b00 cmp r3, #0 8014608: d012 beq.n 8014630 801460a: 687b ldr r3, [r7, #4] 801460c: 68db ldr r3, [r3, #12] 801460e: 2b4f cmp r3, #79 @ 0x4f 8014610: d90e bls.n 8014630 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 8014612: 687b ldr r3, [r7, #4] 8014614: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && 8014616: 2b00 cmp r3, #0 8014618: d00a beq.n 8014630 (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { 801461a: 687b ldr r3, [r7, #4] 801461c: 695a ldr r2, [r3, #20] 801461e: 68fb ldr r3, [r7, #12] 8014620: 68b9 ldr r1, [r7, #8] 8014622: fb01 f303 mul.w r3, r1, r3 8014626: 429a cmp r2, r3 8014628: d302 bcc.n 8014630 mem = 1; 801462a: 2301 movs r3, #1 801462c: 61bb str r3, [r7, #24] 801462e: e014 b.n 801465a } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8014630: 687b ldr r3, [r7, #4] 8014632: 689b ldr r3, [r3, #8] 8014634: 2b00 cmp r3, #0 8014636: d110 bne.n 801465a 8014638: 687b ldr r3, [r7, #4] 801463a: 68db ldr r3, [r3, #12] 801463c: 2b00 cmp r3, #0 801463e: d10c bne.n 801465a (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8014640: 687b ldr r3, [r7, #4] 8014642: 691b ldr r3, [r3, #16] if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && 8014644: 2b00 cmp r3, #0 8014646: d108 bne.n 801465a (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { 8014648: 687b ldr r3, [r7, #4] 801464a: 695b ldr r3, [r3, #20] 801464c: 2b00 cmp r3, #0 801464e: d104 bne.n 801465a mem = 0; 8014650: 2300 movs r3, #0 8014652: 61bb str r3, [r7, #24] 8014654: e001 b.n 801465a } } } else { mem = 0; 8014656: 2300 movs r3, #0 8014658: 61bb str r3, [r7, #24] } if (mem == 1) { 801465a: 69bb ldr r3, [r7, #24] 801465c: 2b01 cmp r3, #1 801465e: d10b bne.n 8014678 #if (configSUPPORT_STATIC_ALLOCATION == 1) hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); 8014660: 687b ldr r3, [r7, #4] 8014662: 691a ldr r2, [r3, #16] 8014664: 687b ldr r3, [r7, #4] 8014666: 689b ldr r3, [r3, #8] 8014668: 2100 movs r1, #0 801466a: 9100 str r1, [sp, #0] 801466c: 68b9 ldr r1, [r7, #8] 801466e: 68f8 ldr r0, [r7, #12] 8014670: f000 fa30 bl 8014ad4 8014674: 61f8 str r0, [r7, #28] 8014676: e008 b.n 801468a #endif } else { if (mem == 0) { 8014678: 69bb ldr r3, [r7, #24] 801467a: 2b00 cmp r3, #0 801467c: d105 bne.n 801468a #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) hQueue = xQueueCreate (msg_count, msg_size); 801467e: 2200 movs r2, #0 8014680: 68b9 ldr r1, [r7, #8] 8014682: 68f8 ldr r0, [r7, #12] 8014684: f000 faa3 bl 8014bce 8014688: 61f8 str r0, [r7, #28] #endif } } #if (configQUEUE_REGISTRY_SIZE > 0) if (hQueue != NULL) { 801468a: 69fb ldr r3, [r7, #28] 801468c: 2b00 cmp r3, #0 801468e: d00c beq.n 80146aa if (attr != NULL) { 8014690: 687b ldr r3, [r7, #4] 8014692: 2b00 cmp r3, #0 8014694: d003 beq.n 801469e name = attr->name; 8014696: 687b ldr r3, [r7, #4] 8014698: 681b ldr r3, [r3, #0] 801469a: 617b str r3, [r7, #20] 801469c: e001 b.n 80146a2 } else { name = NULL; 801469e: 2300 movs r3, #0 80146a0: 617b str r3, [r7, #20] } vQueueAddToRegistry (hQueue, name); 80146a2: 6979 ldr r1, [r7, #20] 80146a4: 69f8 ldr r0, [r7, #28] 80146a6: f001 f8e5 bl 8015874 } #endif } return ((osMessageQueueId_t)hQueue); 80146aa: 69fb ldr r3, [r7, #28] } 80146ac: 4618 mov r0, r3 80146ae: 3720 adds r7, #32 80146b0: 46bd mov sp, r7 80146b2: bd80 pop {r7, pc} 080146b4 : osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { 80146b4: b580 push {r7, lr} 80146b6: b088 sub sp, #32 80146b8: af00 add r7, sp, #0 80146ba: 60f8 str r0, [r7, #12] 80146bc: 60b9 str r1, [r7, #8] 80146be: 603b str r3, [r7, #0] 80146c0: 4613 mov r3, r2 80146c2: 71fb strb r3, [r7, #7] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 80146c4: 68fb ldr r3, [r7, #12] 80146c6: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 80146c8: 2300 movs r3, #0 80146ca: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 80146cc: f3ef 8305 mrs r3, IPSR 80146d0: 617b str r3, [r7, #20] return(result); 80146d2: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 80146d4: 2b00 cmp r3, #0 80146d6: d028 beq.n 801472a if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 80146d8: 69bb ldr r3, [r7, #24] 80146da: 2b00 cmp r3, #0 80146dc: d005 beq.n 80146ea 80146de: 68bb ldr r3, [r7, #8] 80146e0: 2b00 cmp r3, #0 80146e2: d002 beq.n 80146ea 80146e4: 683b ldr r3, [r7, #0] 80146e6: 2b00 cmp r3, #0 80146e8: d003 beq.n 80146f2 stat = osErrorParameter; 80146ea: f06f 0303 mvn.w r3, #3 80146ee: 61fb str r3, [r7, #28] 80146f0: e038 b.n 8014764 } else { yield = pdFALSE; 80146f2: 2300 movs r3, #0 80146f4: 613b str r3, [r7, #16] if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { 80146f6: f107 0210 add.w r2, r7, #16 80146fa: 2300 movs r3, #0 80146fc: 68b9 ldr r1, [r7, #8] 80146fe: 69b8 ldr r0, [r7, #24] 8014700: f000 fc7e bl 8015000 8014704: 4603 mov r3, r0 8014706: 2b01 cmp r3, #1 8014708: d003 beq.n 8014712 stat = osErrorResource; 801470a: f06f 0302 mvn.w r3, #2 801470e: 61fb str r3, [r7, #28] 8014710: e028 b.n 8014764 } else { portYIELD_FROM_ISR (yield); 8014712: 693b ldr r3, [r7, #16] 8014714: 2b00 cmp r3, #0 8014716: d025 beq.n 8014764 8014718: 4b15 ldr r3, [pc, #84] @ (8014770 ) 801471a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801471e: 601a str r2, [r3, #0] 8014720: f3bf 8f4f dsb sy 8014724: f3bf 8f6f isb sy 8014728: e01c b.n 8014764 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 801472a: 69bb ldr r3, [r7, #24] 801472c: 2b00 cmp r3, #0 801472e: d002 beq.n 8014736 8014730: 68bb ldr r3, [r7, #8] 8014732: 2b00 cmp r3, #0 8014734: d103 bne.n 801473e stat = osErrorParameter; 8014736: f06f 0303 mvn.w r3, #3 801473a: 61fb str r3, [r7, #28] 801473c: e012 b.n 8014764 } else { if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 801473e: 2300 movs r3, #0 8014740: 683a ldr r2, [r7, #0] 8014742: 68b9 ldr r1, [r7, #8] 8014744: 69b8 ldr r0, [r7, #24] 8014746: f000 fb59 bl 8014dfc 801474a: 4603 mov r3, r0 801474c: 2b01 cmp r3, #1 801474e: d009 beq.n 8014764 if (timeout != 0U) { 8014750: 683b ldr r3, [r7, #0] 8014752: 2b00 cmp r3, #0 8014754: d003 beq.n 801475e stat = osErrorTimeout; 8014756: f06f 0301 mvn.w r3, #1 801475a: 61fb str r3, [r7, #28] 801475c: e002 b.n 8014764 } else { stat = osErrorResource; 801475e: f06f 0302 mvn.w r3, #2 8014762: 61fb str r3, [r7, #28] } } } } return (stat); 8014764: 69fb ldr r3, [r7, #28] } 8014766: 4618 mov r0, r3 8014768: 3720 adds r7, #32 801476a: 46bd mov sp, r7 801476c: bd80 pop {r7, pc} 801476e: bf00 nop 8014770: e000ed04 .word 0xe000ed04 08014774 : osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { 8014774: b580 push {r7, lr} 8014776: b088 sub sp, #32 8014778: af00 add r7, sp, #0 801477a: 60f8 str r0, [r7, #12] 801477c: 60b9 str r1, [r7, #8] 801477e: 607a str r2, [r7, #4] 8014780: 603b str r3, [r7, #0] QueueHandle_t hQueue = (QueueHandle_t)mq_id; 8014782: 68fb ldr r3, [r7, #12] 8014784: 61bb str r3, [r7, #24] osStatus_t stat; BaseType_t yield; (void)msg_prio; /* Message priority is ignored */ stat = osOK; 8014786: 2300 movs r3, #0 8014788: 61fb str r3, [r7, #28] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 801478a: f3ef 8305 mrs r3, IPSR 801478e: 617b str r3, [r7, #20] return(result); 8014790: 697b ldr r3, [r7, #20] if (IS_IRQ()) { 8014792: 2b00 cmp r3, #0 8014794: d028 beq.n 80147e8 if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { 8014796: 69bb ldr r3, [r7, #24] 8014798: 2b00 cmp r3, #0 801479a: d005 beq.n 80147a8 801479c: 68bb ldr r3, [r7, #8] 801479e: 2b00 cmp r3, #0 80147a0: d002 beq.n 80147a8 80147a2: 683b ldr r3, [r7, #0] 80147a4: 2b00 cmp r3, #0 80147a6: d003 beq.n 80147b0 stat = osErrorParameter; 80147a8: f06f 0303 mvn.w r3, #3 80147ac: 61fb str r3, [r7, #28] 80147ae: e037 b.n 8014820 } else { yield = pdFALSE; 80147b0: 2300 movs r3, #0 80147b2: 613b str r3, [r7, #16] if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { 80147b4: f107 0310 add.w r3, r7, #16 80147b8: 461a mov r2, r3 80147ba: 68b9 ldr r1, [r7, #8] 80147bc: 69b8 ldr r0, [r7, #24] 80147be: f000 feaf bl 8015520 80147c2: 4603 mov r3, r0 80147c4: 2b01 cmp r3, #1 80147c6: d003 beq.n 80147d0 stat = osErrorResource; 80147c8: f06f 0302 mvn.w r3, #2 80147cc: 61fb str r3, [r7, #28] 80147ce: e027 b.n 8014820 } else { portYIELD_FROM_ISR (yield); 80147d0: 693b ldr r3, [r7, #16] 80147d2: 2b00 cmp r3, #0 80147d4: d024 beq.n 8014820 80147d6: 4b15 ldr r3, [pc, #84] @ (801482c ) 80147d8: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80147dc: 601a str r2, [r3, #0] 80147de: f3bf 8f4f dsb sy 80147e2: f3bf 8f6f isb sy 80147e6: e01b b.n 8014820 } } } else { if ((hQueue == NULL) || (msg_ptr == NULL)) { 80147e8: 69bb ldr r3, [r7, #24] 80147ea: 2b00 cmp r3, #0 80147ec: d002 beq.n 80147f4 80147ee: 68bb ldr r3, [r7, #8] 80147f0: 2b00 cmp r3, #0 80147f2: d103 bne.n 80147fc stat = osErrorParameter; 80147f4: f06f 0303 mvn.w r3, #3 80147f8: 61fb str r3, [r7, #28] 80147fa: e011 b.n 8014820 } else { if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { 80147fc: 683a ldr r2, [r7, #0] 80147fe: 68b9 ldr r1, [r7, #8] 8014800: 69b8 ldr r0, [r7, #24] 8014802: f000 fc9b bl 801513c 8014806: 4603 mov r3, r0 8014808: 2b01 cmp r3, #1 801480a: d009 beq.n 8014820 if (timeout != 0U) { 801480c: 683b ldr r3, [r7, #0] 801480e: 2b00 cmp r3, #0 8014810: d003 beq.n 801481a stat = osErrorTimeout; 8014812: f06f 0301 mvn.w r3, #1 8014816: 61fb str r3, [r7, #28] 8014818: e002 b.n 8014820 } else { stat = osErrorResource; 801481a: f06f 0302 mvn.w r3, #2 801481e: 61fb str r3, [r7, #28] } } } } return (stat); 8014820: 69fb ldr r3, [r7, #28] } 8014822: 4618 mov r0, r3 8014824: 3720 adds r7, #32 8014826: 46bd mov sp, r7 8014828: bd80 pop {r7, pc} 801482a: bf00 nop 801482c: e000ed04 .word 0xe000ed04 08014830 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { 8014830: b480 push {r7} 8014832: b085 sub sp, #20 8014834: af00 add r7, sp, #0 8014836: 60f8 str r0, [r7, #12] 8014838: 60b9 str r1, [r7, #8] 801483a: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; 801483c: 68fb ldr r3, [r7, #12] 801483e: 4a07 ldr r2, [pc, #28] @ (801485c ) 8014840: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; 8014842: 68bb ldr r3, [r7, #8] 8014844: 4a06 ldr r2, [pc, #24] @ (8014860 ) 8014846: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; 8014848: 687b ldr r3, [r7, #4] 801484a: f44f 7200 mov.w r2, #512 @ 0x200 801484e: 601a str r2, [r3, #0] } 8014850: bf00 nop 8014852: 3714 adds r7, #20 8014854: 46bd mov sp, r7 8014856: f85d 7b04 ldr.w r7, [sp], #4 801485a: 4770 bx lr 801485c: 24001068 .word 0x24001068 8014860: 24001110 .word 0x24001110 08014864 : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { 8014864: b480 push {r7} 8014866: b085 sub sp, #20 8014868: af00 add r7, sp, #0 801486a: 60f8 str r0, [r7, #12] 801486c: 60b9 str r1, [r7, #8] 801486e: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; 8014870: 68fb ldr r3, [r7, #12] 8014872: 4a07 ldr r2, [pc, #28] @ (8014890 ) 8014874: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; 8014876: 68bb ldr r3, [r7, #8] 8014878: 4a06 ldr r2, [pc, #24] @ (8014894 ) 801487a: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; 801487c: 687b ldr r3, [r7, #4] 801487e: f44f 6280 mov.w r2, #1024 @ 0x400 8014882: 601a str r2, [r3, #0] } 8014884: bf00 nop 8014886: 3714 adds r7, #20 8014888: 46bd mov sp, r7 801488a: f85d 7b04 ldr.w r7, [sp], #4 801488e: 4770 bx lr 8014890: 24001910 .word 0x24001910 8014894: 240019b8 .word 0x240019b8 08014898 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { 8014898: b480 push {r7} 801489a: b083 sub sp, #12 801489c: af00 add r7, sp, #0 801489e: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80148a0: 687b ldr r3, [r7, #4] 80148a2: f103 0208 add.w r2, r3, #8 80148a6: 687b ldr r3, [r7, #4] 80148a8: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; 80148aa: 687b ldr r3, [r7, #4] 80148ac: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80148b0: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80148b2: 687b ldr r3, [r7, #4] 80148b4: f103 0208 add.w r2, r3, #8 80148b8: 687b ldr r3, [r7, #4] 80148ba: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ 80148bc: 687b ldr r3, [r7, #4] 80148be: f103 0208 add.w r2, r3, #8 80148c2: 687b ldr r3, [r7, #4] 80148c4: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; 80148c6: 687b ldr r3, [r7, #4] 80148c8: 2200 movs r2, #0 80148ca: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } 80148cc: bf00 nop 80148ce: 370c adds r7, #12 80148d0: 46bd mov sp, r7 80148d2: f85d 7b04 ldr.w r7, [sp], #4 80148d6: 4770 bx lr 080148d8 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { 80148d8: b480 push {r7} 80148da: b083 sub sp, #12 80148dc: af00 add r7, sp, #0 80148de: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; 80148e0: 687b ldr r3, [r7, #4] 80148e2: 2200 movs r2, #0 80148e4: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } 80148e6: bf00 nop 80148e8: 370c adds r7, #12 80148ea: 46bd mov sp, r7 80148ec: f85d 7b04 ldr.w r7, [sp], #4 80148f0: 4770 bx lr 080148f2 : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 80148f2: b480 push {r7} 80148f4: b085 sub sp, #20 80148f6: af00 add r7, sp, #0 80148f8: 6078 str r0, [r7, #4] 80148fa: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 80148fc: 687b ldr r3, [r7, #4] 80148fe: 685b ldr r3, [r3, #4] 8014900: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8014902: 683b ldr r3, [r7, #0] 8014904: 68fa ldr r2, [r7, #12] 8014906: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8014908: 68fb ldr r3, [r7, #12] 801490a: 689a ldr r2, [r3, #8] 801490c: 683b ldr r3, [r7, #0] 801490e: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8014910: 68fb ldr r3, [r7, #12] 8014912: 689b ldr r3, [r3, #8] 8014914: 683a ldr r2, [r7, #0] 8014916: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8014918: 68fb ldr r3, [r7, #12] 801491a: 683a ldr r2, [r7, #0] 801491c: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 801491e: 683b ldr r3, [r7, #0] 8014920: 687a ldr r2, [r7, #4] 8014922: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8014924: 687b ldr r3, [r7, #4] 8014926: 681b ldr r3, [r3, #0] 8014928: 1c5a adds r2, r3, #1 801492a: 687b ldr r3, [r7, #4] 801492c: 601a str r2, [r3, #0] } 801492e: bf00 nop 8014930: 3714 adds r7, #20 8014932: 46bd mov sp, r7 8014934: f85d 7b04 ldr.w r7, [sp], #4 8014938: 4770 bx lr 0801493a : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 801493a: b480 push {r7} 801493c: b085 sub sp, #20 801493e: af00 add r7, sp, #0 8014940: 6078 str r0, [r7, #4] 8014942: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8014944: 683b ldr r3, [r7, #0] 8014946: 681b ldr r3, [r3, #0] 8014948: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 801494a: 68bb ldr r3, [r7, #8] 801494c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014950: d103 bne.n 801495a { pxIterator = pxList->xListEnd.pxPrevious; 8014952: 687b ldr r3, [r7, #4] 8014954: 691b ldr r3, [r3, #16] 8014956: 60fb str r3, [r7, #12] 8014958: e00c b.n 8014974 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 801495a: 687b ldr r3, [r7, #4] 801495c: 3308 adds r3, #8 801495e: 60fb str r3, [r7, #12] 8014960: e002 b.n 8014968 8014962: 68fb ldr r3, [r7, #12] 8014964: 685b ldr r3, [r3, #4] 8014966: 60fb str r3, [r7, #12] 8014968: 68fb ldr r3, [r7, #12] 801496a: 685b ldr r3, [r3, #4] 801496c: 681b ldr r3, [r3, #0] 801496e: 68ba ldr r2, [r7, #8] 8014970: 429a cmp r2, r3 8014972: d2f6 bcs.n 8014962 /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8014974: 68fb ldr r3, [r7, #12] 8014976: 685a ldr r2, [r3, #4] 8014978: 683b ldr r3, [r7, #0] 801497a: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 801497c: 683b ldr r3, [r7, #0] 801497e: 685b ldr r3, [r3, #4] 8014980: 683a ldr r2, [r7, #0] 8014982: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8014984: 683b ldr r3, [r7, #0] 8014986: 68fa ldr r2, [r7, #12] 8014988: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 801498a: 68fb ldr r3, [r7, #12] 801498c: 683a ldr r2, [r7, #0] 801498e: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8014990: 683b ldr r3, [r7, #0] 8014992: 687a ldr r2, [r7, #4] 8014994: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8014996: 687b ldr r3, [r7, #4] 8014998: 681b ldr r3, [r3, #0] 801499a: 1c5a adds r2, r3, #1 801499c: 687b ldr r3, [r7, #4] 801499e: 601a str r2, [r3, #0] } 80149a0: bf00 nop 80149a2: 3714 adds r7, #20 80149a4: 46bd mov sp, r7 80149a6: f85d 7b04 ldr.w r7, [sp], #4 80149aa: 4770 bx lr 080149ac : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 80149ac: b480 push {r7} 80149ae: b085 sub sp, #20 80149b0: af00 add r7, sp, #0 80149b2: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 80149b4: 687b ldr r3, [r7, #4] 80149b6: 691b ldr r3, [r3, #16] 80149b8: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 80149ba: 687b ldr r3, [r7, #4] 80149bc: 685b ldr r3, [r3, #4] 80149be: 687a ldr r2, [r7, #4] 80149c0: 6892 ldr r2, [r2, #8] 80149c2: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 80149c4: 687b ldr r3, [r7, #4] 80149c6: 689b ldr r3, [r3, #8] 80149c8: 687a ldr r2, [r7, #4] 80149ca: 6852 ldr r2, [r2, #4] 80149cc: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 80149ce: 68fb ldr r3, [r7, #12] 80149d0: 685b ldr r3, [r3, #4] 80149d2: 687a ldr r2, [r7, #4] 80149d4: 429a cmp r2, r3 80149d6: d103 bne.n 80149e0 { pxList->pxIndex = pxItemToRemove->pxPrevious; 80149d8: 687b ldr r3, [r7, #4] 80149da: 689a ldr r2, [r3, #8] 80149dc: 68fb ldr r3, [r7, #12] 80149de: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 80149e0: 687b ldr r3, [r7, #4] 80149e2: 2200 movs r2, #0 80149e4: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 80149e6: 68fb ldr r3, [r7, #12] 80149e8: 681b ldr r3, [r3, #0] 80149ea: 1e5a subs r2, r3, #1 80149ec: 68fb ldr r3, [r7, #12] 80149ee: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 80149f0: 68fb ldr r3, [r7, #12] 80149f2: 681b ldr r3, [r3, #0] } 80149f4: 4618 mov r0, r3 80149f6: 3714 adds r7, #20 80149f8: 46bd mov sp, r7 80149fa: f85d 7b04 ldr.w r7, [sp], #4 80149fe: 4770 bx lr 08014a00 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { 8014a00: b580 push {r7, lr} 8014a02: b084 sub sp, #16 8014a04: af00 add r7, sp, #0 8014a06: 6078 str r0, [r7, #4] 8014a08: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; 8014a0a: 687b ldr r3, [r7, #4] 8014a0c: 60fb str r3, [r7, #12] configASSERT( pxQueue ); 8014a0e: 68fb ldr r3, [r7, #12] 8014a10: 2b00 cmp r3, #0 8014a12: d10b bne.n 8014a2c portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8014a14: f04f 0350 mov.w r3, #80 @ 0x50 8014a18: f383 8811 msr BASEPRI, r3 8014a1c: f3bf 8f6f isb sy 8014a20: f3bf 8f4f dsb sy 8014a24: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8014a26: bf00 nop 8014a28: bf00 nop 8014a2a: e7fd b.n 8014a28 taskENTER_CRITICAL(); 8014a2c: f003 f964 bl 8017cf8 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014a30: 68fb ldr r3, [r7, #12] 8014a32: 681a ldr r2, [r3, #0] 8014a34: 68fb ldr r3, [r7, #12] 8014a36: 6bdb ldr r3, [r3, #60] @ 0x3c 8014a38: 68f9 ldr r1, [r7, #12] 8014a3a: 6c09 ldr r1, [r1, #64] @ 0x40 8014a3c: fb01 f303 mul.w r3, r1, r3 8014a40: 441a add r2, r3 8014a42: 68fb ldr r3, [r7, #12] 8014a44: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; 8014a46: 68fb ldr r3, [r7, #12] 8014a48: 2200 movs r2, #0 8014a4a: 639a str r2, [r3, #56] @ 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; 8014a4c: 68fb ldr r3, [r7, #12] 8014a4e: 681a ldr r2, [r3, #0] 8014a50: 68fb ldr r3, [r7, #12] 8014a52: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014a54: 68fb ldr r3, [r7, #12] 8014a56: 681a ldr r2, [r3, #0] 8014a58: 68fb ldr r3, [r7, #12] 8014a5a: 6bdb ldr r3, [r3, #60] @ 0x3c 8014a5c: 3b01 subs r3, #1 8014a5e: 68f9 ldr r1, [r7, #12] 8014a60: 6c09 ldr r1, [r1, #64] @ 0x40 8014a62: fb01 f303 mul.w r3, r1, r3 8014a66: 441a add r2, r3 8014a68: 68fb ldr r3, [r7, #12] 8014a6a: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; 8014a6c: 68fb ldr r3, [r7, #12] 8014a6e: 22ff movs r2, #255 @ 0xff 8014a70: f883 2044 strb.w r2, [r3, #68] @ 0x44 pxQueue->cTxLock = queueUNLOCKED; 8014a74: 68fb ldr r3, [r7, #12] 8014a76: 22ff movs r2, #255 @ 0xff 8014a78: f883 2045 strb.w r2, [r3, #69] @ 0x45 if( xNewQueue == pdFALSE ) 8014a7c: 683b ldr r3, [r7, #0] 8014a7e: 2b00 cmp r3, #0 8014a80: d114 bne.n 8014aac /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 8014a82: 68fb ldr r3, [r7, #12] 8014a84: 691b ldr r3, [r3, #16] 8014a86: 2b00 cmp r3, #0 8014a88: d01a beq.n 8014ac0 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8014a8a: 68fb ldr r3, [r7, #12] 8014a8c: 3310 adds r3, #16 8014a8e: 4618 mov r0, r3 8014a90: f001 fdac bl 80165ec 8014a94: 4603 mov r3, r0 8014a96: 2b00 cmp r3, #0 8014a98: d012 beq.n 8014ac0 { queueYIELD_IF_USING_PREEMPTION(); 8014a9a: 4b0d ldr r3, [pc, #52] @ (8014ad0 ) 8014a9c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014aa0: 601a str r2, [r3, #0] 8014aa2: f3bf 8f4f dsb sy 8014aa6: f3bf 8f6f isb sy 8014aaa: e009 b.n 8014ac0 } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); 8014aac: 68fb ldr r3, [r7, #12] 8014aae: 3310 adds r3, #16 8014ab0: 4618 mov r0, r3 8014ab2: f7ff fef1 bl 8014898 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); 8014ab6: 68fb ldr r3, [r7, #12] 8014ab8: 3324 adds r3, #36 @ 0x24 8014aba: 4618 mov r0, r3 8014abc: f7ff feec bl 8014898 } } taskEXIT_CRITICAL(); 8014ac0: f003 f94c bl 8017d5c /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; 8014ac4: 2301 movs r3, #1 } 8014ac6: 4618 mov r0, r3 8014ac8: 3710 adds r7, #16 8014aca: 46bd mov sp, r7 8014acc: bd80 pop {r7, pc} 8014ace: bf00 nop 8014ad0: e000ed04 .word 0xe000ed04 08014ad4 : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { 8014ad4: b580 push {r7, lr} 8014ad6: b08e sub sp, #56 @ 0x38 8014ad8: af02 add r7, sp, #8 8014ada: 60f8 str r0, [r7, #12] 8014adc: 60b9 str r1, [r7, #8] 8014ade: 607a str r2, [r7, #4] 8014ae0: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014ae2: 68fb ldr r3, [r7, #12] 8014ae4: 2b00 cmp r3, #0 8014ae6: d10b bne.n 8014b00 __asm volatile 8014ae8: f04f 0350 mov.w r3, #80 @ 0x50 8014aec: f383 8811 msr BASEPRI, r3 8014af0: f3bf 8f6f isb sy 8014af4: f3bf 8f4f dsb sy 8014af8: 62bb str r3, [r7, #40] @ 0x28 } 8014afa: bf00 nop 8014afc: bf00 nop 8014afe: e7fd b.n 8014afc /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); 8014b00: 683b ldr r3, [r7, #0] 8014b02: 2b00 cmp r3, #0 8014b04: d10b bne.n 8014b1e __asm volatile 8014b06: f04f 0350 mov.w r3, #80 @ 0x50 8014b0a: f383 8811 msr BASEPRI, r3 8014b0e: f3bf 8f6f isb sy 8014b12: f3bf 8f4f dsb sy 8014b16: 627b str r3, [r7, #36] @ 0x24 } 8014b18: bf00 nop 8014b1a: bf00 nop 8014b1c: e7fd b.n 8014b1a /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); 8014b1e: 687b ldr r3, [r7, #4] 8014b20: 2b00 cmp r3, #0 8014b22: d002 beq.n 8014b2a 8014b24: 68bb ldr r3, [r7, #8] 8014b26: 2b00 cmp r3, #0 8014b28: d001 beq.n 8014b2e 8014b2a: 2301 movs r3, #1 8014b2c: e000 b.n 8014b30 8014b2e: 2300 movs r3, #0 8014b30: 2b00 cmp r3, #0 8014b32: d10b bne.n 8014b4c __asm volatile 8014b34: f04f 0350 mov.w r3, #80 @ 0x50 8014b38: f383 8811 msr BASEPRI, r3 8014b3c: f3bf 8f6f isb sy 8014b40: f3bf 8f4f dsb sy 8014b44: 623b str r3, [r7, #32] } 8014b46: bf00 nop 8014b48: bf00 nop 8014b4a: e7fd b.n 8014b48 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); 8014b4c: 687b ldr r3, [r7, #4] 8014b4e: 2b00 cmp r3, #0 8014b50: d102 bne.n 8014b58 8014b52: 68bb ldr r3, [r7, #8] 8014b54: 2b00 cmp r3, #0 8014b56: d101 bne.n 8014b5c 8014b58: 2301 movs r3, #1 8014b5a: e000 b.n 8014b5e 8014b5c: 2300 movs r3, #0 8014b5e: 2b00 cmp r3, #0 8014b60: d10b bne.n 8014b7a __asm volatile 8014b62: f04f 0350 mov.w r3, #80 @ 0x50 8014b66: f383 8811 msr BASEPRI, r3 8014b6a: f3bf 8f6f isb sy 8014b6e: f3bf 8f4f dsb sy 8014b72: 61fb str r3, [r7, #28] } 8014b74: bf00 nop 8014b76: bf00 nop 8014b78: e7fd b.n 8014b76 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); 8014b7a: 2350 movs r3, #80 @ 0x50 8014b7c: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); 8014b7e: 697b ldr r3, [r7, #20] 8014b80: 2b50 cmp r3, #80 @ 0x50 8014b82: d00b beq.n 8014b9c __asm volatile 8014b84: f04f 0350 mov.w r3, #80 @ 0x50 8014b88: f383 8811 msr BASEPRI, r3 8014b8c: f3bf 8f6f isb sy 8014b90: f3bf 8f4f dsb sy 8014b94: 61bb str r3, [r7, #24] } 8014b96: bf00 nop 8014b98: bf00 nop 8014b9a: e7fd b.n 8014b98 ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 8014b9c: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8014b9e: 683b ldr r3, [r7, #0] 8014ba0: 62fb str r3, [r7, #44] @ 0x2c if( pxNewQueue != NULL ) 8014ba2: 6afb ldr r3, [r7, #44] @ 0x2c 8014ba4: 2b00 cmp r3, #0 8014ba6: d00d beq.n 8014bc4 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; 8014ba8: 6afb ldr r3, [r7, #44] @ 0x2c 8014baa: 2201 movs r2, #1 8014bac: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014bb0: f897 2038 ldrb.w r2, [r7, #56] @ 0x38 8014bb4: 6afb ldr r3, [r7, #44] @ 0x2c 8014bb6: 9300 str r3, [sp, #0] 8014bb8: 4613 mov r3, r2 8014bba: 687a ldr r2, [r7, #4] 8014bbc: 68b9 ldr r1, [r7, #8] 8014bbe: 68f8 ldr r0, [r7, #12] 8014bc0: f000 f840 bl 8014c44 { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014bc4: 6afb ldr r3, [r7, #44] @ 0x2c } 8014bc6: 4618 mov r0, r3 8014bc8: 3730 adds r7, #48 @ 0x30 8014bca: 46bd mov sp, r7 8014bcc: bd80 pop {r7, pc} 08014bce : /*-----------------------------------------------------------*/ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) { 8014bce: b580 push {r7, lr} 8014bd0: b08a sub sp, #40 @ 0x28 8014bd2: af02 add r7, sp, #8 8014bd4: 60f8 str r0, [r7, #12] 8014bd6: 60b9 str r1, [r7, #8] 8014bd8: 4613 mov r3, r2 8014bda: 71fb strb r3, [r7, #7] Queue_t *pxNewQueue; size_t xQueueSizeInBytes; uint8_t *pucQueueStorage; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); 8014bdc: 68fb ldr r3, [r7, #12] 8014bde: 2b00 cmp r3, #0 8014be0: d10b bne.n 8014bfa __asm volatile 8014be2: f04f 0350 mov.w r3, #80 @ 0x50 8014be6: f383 8811 msr BASEPRI, r3 8014bea: f3bf 8f6f isb sy 8014bee: f3bf 8f4f dsb sy 8014bf2: 613b str r3, [r7, #16] } 8014bf4: bf00 nop 8014bf6: bf00 nop 8014bf8: e7fd b.n 8014bf6 /* Allocate enough space to hold the maximum number of items that can be in the queue at any time. It is valid for uxItemSize to be zero in the case the queue is used as a semaphore. */ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8014bfa: 68fb ldr r3, [r7, #12] 8014bfc: 68ba ldr r2, [r7, #8] 8014bfe: fb02 f303 mul.w r3, r2, r3 8014c02: 61fb str r3, [r7, #28] alignment requirements of the Queue_t structure - which in this case is an int8_t *. Therefore, whenever the stack alignment requirements are greater than or equal to the pointer to char requirements the cast is safe. In other cases alignment requirements are not strict (one or two bytes). */ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ 8014c04: 69fb ldr r3, [r7, #28] 8014c06: 3350 adds r3, #80 @ 0x50 8014c08: 4618 mov r0, r3 8014c0a: f003 f997 bl 8017f3c 8014c0e: 61b8 str r0, [r7, #24] if( pxNewQueue != NULL ) 8014c10: 69bb ldr r3, [r7, #24] 8014c12: 2b00 cmp r3, #0 8014c14: d011 beq.n 8014c3a { /* Jump past the queue structure to find the location of the queue storage area. */ pucQueueStorage = ( uint8_t * ) pxNewQueue; 8014c16: 69bb ldr r3, [r7, #24] 8014c18: 617b str r3, [r7, #20] pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ 8014c1a: 697b ldr r3, [r7, #20] 8014c1c: 3350 adds r3, #80 @ 0x50 8014c1e: 617b str r3, [r7, #20] #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { /* Queues can be created either statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdFALSE; 8014c20: 69bb ldr r3, [r7, #24] 8014c22: 2200 movs r2, #0 8014c24: f883 2046 strb.w r2, [r3, #70] @ 0x46 } #endif /* configSUPPORT_STATIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); 8014c28: 79fa ldrb r2, [r7, #7] 8014c2a: 69bb ldr r3, [r7, #24] 8014c2c: 9300 str r3, [sp, #0] 8014c2e: 4613 mov r3, r2 8014c30: 697a ldr r2, [r7, #20] 8014c32: 68b9 ldr r1, [r7, #8] 8014c34: 68f8 ldr r0, [r7, #12] 8014c36: f000 f805 bl 8014c44 { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; 8014c3a: 69bb ldr r3, [r7, #24] } 8014c3c: 4618 mov r0, r3 8014c3e: 3720 adds r7, #32 8014c40: 46bd mov sp, r7 8014c42: bd80 pop {r7, pc} 08014c44 : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { 8014c44: b580 push {r7, lr} 8014c46: b084 sub sp, #16 8014c48: af00 add r7, sp, #0 8014c4a: 60f8 str r0, [r7, #12] 8014c4c: 60b9 str r1, [r7, #8] 8014c4e: 607a str r2, [r7, #4] 8014c50: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) 8014c52: 68bb ldr r3, [r7, #8] 8014c54: 2b00 cmp r3, #0 8014c56: d103 bne.n 8014c60 { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; 8014c58: 69bb ldr r3, [r7, #24] 8014c5a: 69ba ldr r2, [r7, #24] 8014c5c: 601a str r2, [r3, #0] 8014c5e: e002 b.n 8014c66 } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; 8014c60: 69bb ldr r3, [r7, #24] 8014c62: 687a ldr r2, [r7, #4] 8014c64: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; 8014c66: 69bb ldr r3, [r7, #24] 8014c68: 68fa ldr r2, [r7, #12] 8014c6a: 63da str r2, [r3, #60] @ 0x3c pxNewQueue->uxItemSize = uxItemSize; 8014c6c: 69bb ldr r3, [r7, #24] 8014c6e: 68ba ldr r2, [r7, #8] 8014c70: 641a str r2, [r3, #64] @ 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); 8014c72: 2101 movs r1, #1 8014c74: 69b8 ldr r0, [r7, #24] 8014c76: f7ff fec3 bl 8014a00 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; 8014c7a: 69bb ldr r3, [r7, #24] 8014c7c: 78fa ldrb r2, [r7, #3] 8014c7e: f883 204c strb.w r2, [r3, #76] @ 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } 8014c82: bf00 nop 8014c84: 3710 adds r7, #16 8014c86: 46bd mov sp, r7 8014c88: bd80 pop {r7, pc} 08014c8a : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static void prvInitialiseMutex( Queue_t *pxNewQueue ) { 8014c8a: b580 push {r7, lr} 8014c8c: b082 sub sp, #8 8014c8e: af00 add r7, sp, #0 8014c90: 6078 str r0, [r7, #4] if( pxNewQueue != NULL ) 8014c92: 687b ldr r3, [r7, #4] 8014c94: 2b00 cmp r3, #0 8014c96: d00e beq.n 8014cb6 { /* The queue create function will set all the queue structure members correctly for a generic queue, but this function is creating a mutex. Overwrite those members that need to be set differently - in particular the information required for priority inheritance. */ pxNewQueue->u.xSemaphore.xMutexHolder = NULL; 8014c98: 687b ldr r3, [r7, #4] 8014c9a: 2200 movs r2, #0 8014c9c: 609a str r2, [r3, #8] pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; 8014c9e: 687b ldr r3, [r7, #4] 8014ca0: 2200 movs r2, #0 8014ca2: 601a str r2, [r3, #0] /* In case this is a recursive mutex. */ pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; 8014ca4: 687b ldr r3, [r7, #4] 8014ca6: 2200 movs r2, #0 8014ca8: 60da str r2, [r3, #12] traceCREATE_MUTEX( pxNewQueue ); /* Start with the semaphore in the expected state. */ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); 8014caa: 2300 movs r3, #0 8014cac: 2200 movs r2, #0 8014cae: 2100 movs r1, #0 8014cb0: 6878 ldr r0, [r7, #4] 8014cb2: f000 f8a3 bl 8014dfc } else { traceCREATE_MUTEX_FAILED(); } } 8014cb6: bf00 nop 8014cb8: 3708 adds r7, #8 8014cba: 46bd mov sp, r7 8014cbc: bd80 pop {r7, pc} 08014cbe : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) { 8014cbe: b580 push {r7, lr} 8014cc0: b086 sub sp, #24 8014cc2: af00 add r7, sp, #0 8014cc4: 4603 mov r3, r0 8014cc6: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014cc8: 2301 movs r3, #1 8014cca: 617b str r3, [r7, #20] 8014ccc: 2300 movs r3, #0 8014cce: 613b str r3, [r7, #16] xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); 8014cd0: 79fb ldrb r3, [r7, #7] 8014cd2: 461a mov r2, r3 8014cd4: 6939 ldr r1, [r7, #16] 8014cd6: 6978 ldr r0, [r7, #20] 8014cd8: f7ff ff79 bl 8014bce 8014cdc: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014cde: 68f8 ldr r0, [r7, #12] 8014ce0: f7ff ffd3 bl 8014c8a return xNewQueue; 8014ce4: 68fb ldr r3, [r7, #12] } 8014ce6: 4618 mov r0, r3 8014ce8: 3718 adds r7, #24 8014cea: 46bd mov sp, r7 8014cec: bd80 pop {r7, pc} 08014cee : /*-----------------------------------------------------------*/ #if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) { 8014cee: b580 push {r7, lr} 8014cf0: b088 sub sp, #32 8014cf2: af02 add r7, sp, #8 8014cf4: 4603 mov r3, r0 8014cf6: 6039 str r1, [r7, #0] 8014cf8: 71fb strb r3, [r7, #7] QueueHandle_t xNewQueue; const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; 8014cfa: 2301 movs r3, #1 8014cfc: 617b str r3, [r7, #20] 8014cfe: 2300 movs r3, #0 8014d00: 613b str r3, [r7, #16] /* Prevent compiler warnings about unused parameters if configUSE_TRACE_FACILITY does not equal 1. */ ( void ) ucQueueType; xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); 8014d02: 79fb ldrb r3, [r7, #7] 8014d04: 9300 str r3, [sp, #0] 8014d06: 683b ldr r3, [r7, #0] 8014d08: 2200 movs r2, #0 8014d0a: 6939 ldr r1, [r7, #16] 8014d0c: 6978 ldr r0, [r7, #20] 8014d0e: f7ff fee1 bl 8014ad4 8014d12: 60f8 str r0, [r7, #12] prvInitialiseMutex( ( Queue_t * ) xNewQueue ); 8014d14: 68f8 ldr r0, [r7, #12] 8014d16: f7ff ffb8 bl 8014c8a return xNewQueue; 8014d1a: 68fb ldr r3, [r7, #12] } 8014d1c: 4618 mov r0, r3 8014d1e: 3718 adds r7, #24 8014d20: 46bd mov sp, r7 8014d22: bd80 pop {r7, pc} 08014d24 : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) { 8014d24: b590 push {r4, r7, lr} 8014d26: b087 sub sp, #28 8014d28: af00 add r7, sp, #0 8014d2a: 6078 str r0, [r7, #4] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014d2c: 687b ldr r3, [r7, #4] 8014d2e: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014d30: 693b ldr r3, [r7, #16] 8014d32: 2b00 cmp r3, #0 8014d34: d10b bne.n 8014d4e __asm volatile 8014d36: f04f 0350 mov.w r3, #80 @ 0x50 8014d3a: f383 8811 msr BASEPRI, r3 8014d3e: f3bf 8f6f isb sy 8014d42: f3bf 8f4f dsb sy 8014d46: 60fb str r3, [r7, #12] } 8014d48: bf00 nop 8014d4a: bf00 nop 8014d4c: e7fd b.n 8014d4a change outside of this task. If this task does not hold the mutex then pxMutexHolder can never coincidentally equal the tasks handle, and as this is the only condition we are interested in it does not matter if pxMutexHolder is accessed simultaneously by another task. Therefore no mutual exclusion is required to test the pxMutexHolder variable. */ if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014d4e: 693b ldr r3, [r7, #16] 8014d50: 689c ldr r4, [r3, #8] 8014d52: f001 fe39 bl 80169c8 8014d56: 4603 mov r3, r0 8014d58: 429c cmp r4, r3 8014d5a: d111 bne.n 8014d80 /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to the task handle, therefore no underflow check is required. Also, uxRecursiveCallCount is only modified by the mutex holder, and as there can only be one, no mutual exclusion is required to modify the uxRecursiveCallCount member. */ ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; 8014d5c: 693b ldr r3, [r7, #16] 8014d5e: 68db ldr r3, [r3, #12] 8014d60: 1e5a subs r2, r3, #1 8014d62: 693b ldr r3, [r7, #16] 8014d64: 60da str r2, [r3, #12] /* Has the recursive call count unwound to 0? */ if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) 8014d66: 693b ldr r3, [r7, #16] 8014d68: 68db ldr r3, [r3, #12] 8014d6a: 2b00 cmp r3, #0 8014d6c: d105 bne.n 8014d7a { /* Return the mutex. This will automatically unblock any other task that might be waiting to access the mutex. */ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); 8014d6e: 2300 movs r3, #0 8014d70: 2200 movs r2, #0 8014d72: 2100 movs r1, #0 8014d74: 6938 ldr r0, [r7, #16] 8014d76: f000 f841 bl 8014dfc else { mtCOVERAGE_TEST_MARKER(); } xReturn = pdPASS; 8014d7a: 2301 movs r3, #1 8014d7c: 617b str r3, [r7, #20] 8014d7e: e001 b.n 8014d84 } else { /* The mutex cannot be given because the calling task is not the holder. */ xReturn = pdFAIL; 8014d80: 2300 movs r3, #0 8014d82: 617b str r3, [r7, #20] traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); } return xReturn; 8014d84: 697b ldr r3, [r7, #20] } 8014d86: 4618 mov r0, r3 8014d88: 371c adds r7, #28 8014d8a: 46bd mov sp, r7 8014d8c: bd90 pop {r4, r7, pc} 08014d8e : /*-----------------------------------------------------------*/ #if ( configUSE_RECURSIVE_MUTEXES == 1 ) BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) { 8014d8e: b590 push {r4, r7, lr} 8014d90: b087 sub sp, #28 8014d92: af00 add r7, sp, #0 8014d94: 6078 str r0, [r7, #4] 8014d96: 6039 str r1, [r7, #0] BaseType_t xReturn; Queue_t * const pxMutex = ( Queue_t * ) xMutex; 8014d98: 687b ldr r3, [r7, #4] 8014d9a: 613b str r3, [r7, #16] configASSERT( pxMutex ); 8014d9c: 693b ldr r3, [r7, #16] 8014d9e: 2b00 cmp r3, #0 8014da0: d10b bne.n 8014dba __asm volatile 8014da2: f04f 0350 mov.w r3, #80 @ 0x50 8014da6: f383 8811 msr BASEPRI, r3 8014daa: f3bf 8f6f isb sy 8014dae: f3bf 8f4f dsb sy 8014db2: 60fb str r3, [r7, #12] } 8014db4: bf00 nop 8014db6: bf00 nop 8014db8: e7fd b.n 8014db6 /* Comments regarding mutual exclusion as per those within xQueueGiveMutexRecursive(). */ traceTAKE_MUTEX_RECURSIVE( pxMutex ); if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) 8014dba: 693b ldr r3, [r7, #16] 8014dbc: 689c ldr r4, [r3, #8] 8014dbe: f001 fe03 bl 80169c8 8014dc2: 4603 mov r3, r0 8014dc4: 429c cmp r4, r3 8014dc6: d107 bne.n 8014dd8 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014dc8: 693b ldr r3, [r7, #16] 8014dca: 68db ldr r3, [r3, #12] 8014dcc: 1c5a adds r2, r3, #1 8014dce: 693b ldr r3, [r7, #16] 8014dd0: 60da str r2, [r3, #12] xReturn = pdPASS; 8014dd2: 2301 movs r3, #1 8014dd4: 617b str r3, [r7, #20] 8014dd6: e00c b.n 8014df2 } else { xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); 8014dd8: 6839 ldr r1, [r7, #0] 8014dda: 6938 ldr r0, [r7, #16] 8014ddc: f000 fa90 bl 8015300 8014de0: 6178 str r0, [r7, #20] /* pdPASS will only be returned if the mutex was successfully obtained. The calling task may have entered the Blocked state before reaching here. */ if( xReturn != pdFAIL ) 8014de2: 697b ldr r3, [r7, #20] 8014de4: 2b00 cmp r3, #0 8014de6: d004 beq.n 8014df2 { ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; 8014de8: 693b ldr r3, [r7, #16] 8014dea: 68db ldr r3, [r3, #12] 8014dec: 1c5a adds r2, r3, #1 8014dee: 693b ldr r3, [r7, #16] 8014df0: 60da str r2, [r3, #12] { traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); } } return xReturn; 8014df2: 697b ldr r3, [r7, #20] } 8014df4: 4618 mov r0, r3 8014df6: 371c adds r7, #28 8014df8: 46bd mov sp, r7 8014dfa: bd90 pop {r4, r7, pc} 08014dfc : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8014dfc: b580 push {r7, lr} 8014dfe: b08e sub sp, #56 @ 0x38 8014e00: af00 add r7, sp, #0 8014e02: 60f8 str r0, [r7, #12] 8014e04: 60b9 str r1, [r7, #8] 8014e06: 607a str r2, [r7, #4] 8014e08: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8014e0a: 2300 movs r3, #0 8014e0c: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8014e0e: 68fb ldr r3, [r7, #12] 8014e10: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8014e12: 6b3b ldr r3, [r7, #48] @ 0x30 8014e14: 2b00 cmp r3, #0 8014e16: d10b bne.n 8014e30 __asm volatile 8014e18: f04f 0350 mov.w r3, #80 @ 0x50 8014e1c: f383 8811 msr BASEPRI, r3 8014e20: f3bf 8f6f isb sy 8014e24: f3bf 8f4f dsb sy 8014e28: 62bb str r3, [r7, #40] @ 0x28 } 8014e2a: bf00 nop 8014e2c: bf00 nop 8014e2e: e7fd b.n 8014e2c configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8014e30: 68bb ldr r3, [r7, #8] 8014e32: 2b00 cmp r3, #0 8014e34: d103 bne.n 8014e3e 8014e36: 6b3b ldr r3, [r7, #48] @ 0x30 8014e38: 6c1b ldr r3, [r3, #64] @ 0x40 8014e3a: 2b00 cmp r3, #0 8014e3c: d101 bne.n 8014e42 8014e3e: 2301 movs r3, #1 8014e40: e000 b.n 8014e44 8014e42: 2300 movs r3, #0 8014e44: 2b00 cmp r3, #0 8014e46: d10b bne.n 8014e60 __asm volatile 8014e48: f04f 0350 mov.w r3, #80 @ 0x50 8014e4c: f383 8811 msr BASEPRI, r3 8014e50: f3bf 8f6f isb sy 8014e54: f3bf 8f4f dsb sy 8014e58: 627b str r3, [r7, #36] @ 0x24 } 8014e5a: bf00 nop 8014e5c: bf00 nop 8014e5e: e7fd b.n 8014e5c configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8014e60: 683b ldr r3, [r7, #0] 8014e62: 2b02 cmp r3, #2 8014e64: d103 bne.n 8014e6e 8014e66: 6b3b ldr r3, [r7, #48] @ 0x30 8014e68: 6bdb ldr r3, [r3, #60] @ 0x3c 8014e6a: 2b01 cmp r3, #1 8014e6c: d101 bne.n 8014e72 8014e6e: 2301 movs r3, #1 8014e70: e000 b.n 8014e74 8014e72: 2300 movs r3, #0 8014e74: 2b00 cmp r3, #0 8014e76: d10b bne.n 8014e90 __asm volatile 8014e78: f04f 0350 mov.w r3, #80 @ 0x50 8014e7c: f383 8811 msr BASEPRI, r3 8014e80: f3bf 8f6f isb sy 8014e84: f3bf 8f4f dsb sy 8014e88: 623b str r3, [r7, #32] } 8014e8a: bf00 nop 8014e8c: bf00 nop 8014e8e: e7fd b.n 8014e8c #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8014e90: f001 fdaa bl 80169e8 8014e94: 4603 mov r3, r0 8014e96: 2b00 cmp r3, #0 8014e98: d102 bne.n 8014ea0 8014e9a: 687b ldr r3, [r7, #4] 8014e9c: 2b00 cmp r3, #0 8014e9e: d101 bne.n 8014ea4 8014ea0: 2301 movs r3, #1 8014ea2: e000 b.n 8014ea6 8014ea4: 2300 movs r3, #0 8014ea6: 2b00 cmp r3, #0 8014ea8: d10b bne.n 8014ec2 __asm volatile 8014eaa: f04f 0350 mov.w r3, #80 @ 0x50 8014eae: f383 8811 msr BASEPRI, r3 8014eb2: f3bf 8f6f isb sy 8014eb6: f3bf 8f4f dsb sy 8014eba: 61fb str r3, [r7, #28] } 8014ebc: bf00 nop 8014ebe: bf00 nop 8014ec0: e7fd b.n 8014ebe /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8014ec2: f002 ff19 bl 8017cf8 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8014ec6: 6b3b ldr r3, [r7, #48] @ 0x30 8014ec8: 6b9a ldr r2, [r3, #56] @ 0x38 8014eca: 6b3b ldr r3, [r7, #48] @ 0x30 8014ecc: 6bdb ldr r3, [r3, #60] @ 0x3c 8014ece: 429a cmp r2, r3 8014ed0: d302 bcc.n 8014ed8 8014ed2: 683b ldr r3, [r7, #0] 8014ed4: 2b02 cmp r3, #2 8014ed6: d129 bne.n 8014f2c } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8014ed8: 683a ldr r2, [r7, #0] 8014eda: 68b9 ldr r1, [r7, #8] 8014edc: 6b38 ldr r0, [r7, #48] @ 0x30 8014ede: f000 fbb9 bl 8015654 8014ee2: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8014ee4: 6b3b ldr r3, [r7, #48] @ 0x30 8014ee6: 6a5b ldr r3, [r3, #36] @ 0x24 8014ee8: 2b00 cmp r3, #0 8014eea: d010 beq.n 8014f0e { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8014eec: 6b3b ldr r3, [r7, #48] @ 0x30 8014eee: 3324 adds r3, #36 @ 0x24 8014ef0: 4618 mov r0, r3 8014ef2: f001 fb7b bl 80165ec 8014ef6: 4603 mov r3, r0 8014ef8: 2b00 cmp r3, #0 8014efa: d013 beq.n 8014f24 { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8014efc: 4b3f ldr r3, [pc, #252] @ (8014ffc ) 8014efe: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014f02: 601a str r2, [r3, #0] 8014f04: f3bf 8f4f dsb sy 8014f08: f3bf 8f6f isb sy 8014f0c: e00a b.n 8014f24 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8014f0e: 6afb ldr r3, [r7, #44] @ 0x2c 8014f10: 2b00 cmp r3, #0 8014f12: d007 beq.n 8014f24 { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8014f14: 4b39 ldr r3, [pc, #228] @ (8014ffc ) 8014f16: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014f1a: 601a str r2, [r3, #0] 8014f1c: f3bf 8f4f dsb sy 8014f20: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8014f24: f002 ff1a bl 8017d5c return pdPASS; 8014f28: 2301 movs r3, #1 8014f2a: e063 b.n 8014ff4 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8014f2c: 687b ldr r3, [r7, #4] 8014f2e: 2b00 cmp r3, #0 8014f30: d103 bne.n 8014f3a { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8014f32: f002 ff13 bl 8017d5c /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014f36: 2300 movs r3, #0 8014f38: e05c b.n 8014ff4 } else if( xEntryTimeSet == pdFALSE ) 8014f3a: 6b7b ldr r3, [r7, #52] @ 0x34 8014f3c: 2b00 cmp r3, #0 8014f3e: d106 bne.n 8014f4e { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8014f40: f107 0314 add.w r3, r7, #20 8014f44: 4618 mov r0, r3 8014f46: f001 fbdd bl 8016704 xEntryTimeSet = pdTRUE; 8014f4a: 2301 movs r3, #1 8014f4c: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8014f4e: f002 ff05 bl 8017d5c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8014f52: f001 f90f bl 8016174 prvLockQueue( pxQueue ); 8014f56: f002 fecf bl 8017cf8 8014f5a: 6b3b ldr r3, [r7, #48] @ 0x30 8014f5c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8014f60: b25b sxtb r3, r3 8014f62: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f66: d103 bne.n 8014f70 8014f68: 6b3b ldr r3, [r7, #48] @ 0x30 8014f6a: 2200 movs r2, #0 8014f6c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8014f70: 6b3b ldr r3, [r7, #48] @ 0x30 8014f72: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8014f76: b25b sxtb r3, r3 8014f78: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8014f7c: d103 bne.n 8014f86 8014f7e: 6b3b ldr r3, [r7, #48] @ 0x30 8014f80: 2200 movs r2, #0 8014f82: f883 2045 strb.w r2, [r3, #69] @ 0x45 8014f86: f002 fee9 bl 8017d5c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8014f8a: 1d3a adds r2, r7, #4 8014f8c: f107 0314 add.w r3, r7, #20 8014f90: 4611 mov r1, r2 8014f92: 4618 mov r0, r3 8014f94: f001 fbcc bl 8016730 8014f98: 4603 mov r3, r0 8014f9a: 2b00 cmp r3, #0 8014f9c: d124 bne.n 8014fe8 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 8014f9e: 6b38 ldr r0, [r7, #48] @ 0x30 8014fa0: f000 fc50 bl 8015844 8014fa4: 4603 mov r3, r0 8014fa6: 2b00 cmp r3, #0 8014fa8: d018 beq.n 8014fdc { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 8014faa: 6b3b ldr r3, [r7, #48] @ 0x30 8014fac: 3310 adds r3, #16 8014fae: 687a ldr r2, [r7, #4] 8014fb0: 4611 mov r1, r2 8014fb2: 4618 mov r0, r3 8014fb4: f001 fac8 bl 8016548 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8014fb8: 6b38 ldr r0, [r7, #48] @ 0x30 8014fba: f000 fbdb bl 8015774 /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 8014fbe: f001 f8e7 bl 8016190 8014fc2: 4603 mov r3, r0 8014fc4: 2b00 cmp r3, #0 8014fc6: f47f af7c bne.w 8014ec2 { portYIELD_WITHIN_API(); 8014fca: 4b0c ldr r3, [pc, #48] @ (8014ffc ) 8014fcc: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8014fd0: 601a str r2, [r3, #0] 8014fd2: f3bf 8f4f dsb sy 8014fd6: f3bf 8f6f isb sy 8014fda: e772 b.n 8014ec2 } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 8014fdc: 6b38 ldr r0, [r7, #48] @ 0x30 8014fde: f000 fbc9 bl 8015774 ( void ) xTaskResumeAll(); 8014fe2: f001 f8d5 bl 8016190 8014fe6: e76c b.n 8014ec2 } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8014fe8: 6b38 ldr r0, [r7, #48] @ 0x30 8014fea: f000 fbc3 bl 8015774 ( void ) xTaskResumeAll(); 8014fee: f001 f8cf bl 8016190 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8014ff2: 2300 movs r3, #0 } } /*lint -restore */ } 8014ff4: 4618 mov r0, r3 8014ff6: 3738 adds r7, #56 @ 0x38 8014ff8: 46bd mov sp, r7 8014ffa: bd80 pop {r7, pc} 8014ffc: e000ed04 .word 0xe000ed04 08015000 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8015000: b580 push {r7, lr} 8015002: b090 sub sp, #64 @ 0x40 8015004: af00 add r7, sp, #0 8015006: 60f8 str r0, [r7, #12] 8015008: 60b9 str r1, [r7, #8] 801500a: 607a str r2, [r7, #4] 801500c: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 801500e: 68fb ldr r3, [r7, #12] 8015010: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 8015012: 6bbb ldr r3, [r7, #56] @ 0x38 8015014: 2b00 cmp r3, #0 8015016: d10b bne.n 8015030 __asm volatile 8015018: f04f 0350 mov.w r3, #80 @ 0x50 801501c: f383 8811 msr BASEPRI, r3 8015020: f3bf 8f6f isb sy 8015024: f3bf 8f4f dsb sy 8015028: 62bb str r3, [r7, #40] @ 0x28 } 801502a: bf00 nop 801502c: bf00 nop 801502e: e7fd b.n 801502c configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8015030: 68bb ldr r3, [r7, #8] 8015032: 2b00 cmp r3, #0 8015034: d103 bne.n 801503e 8015036: 6bbb ldr r3, [r7, #56] @ 0x38 8015038: 6c1b ldr r3, [r3, #64] @ 0x40 801503a: 2b00 cmp r3, #0 801503c: d101 bne.n 8015042 801503e: 2301 movs r3, #1 8015040: e000 b.n 8015044 8015042: 2300 movs r3, #0 8015044: 2b00 cmp r3, #0 8015046: d10b bne.n 8015060 __asm volatile 8015048: f04f 0350 mov.w r3, #80 @ 0x50 801504c: f383 8811 msr BASEPRI, r3 8015050: f3bf 8f6f isb sy 8015054: f3bf 8f4f dsb sy 8015058: 627b str r3, [r7, #36] @ 0x24 } 801505a: bf00 nop 801505c: bf00 nop 801505e: e7fd b.n 801505c configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8015060: 683b ldr r3, [r7, #0] 8015062: 2b02 cmp r3, #2 8015064: d103 bne.n 801506e 8015066: 6bbb ldr r3, [r7, #56] @ 0x38 8015068: 6bdb ldr r3, [r3, #60] @ 0x3c 801506a: 2b01 cmp r3, #1 801506c: d101 bne.n 8015072 801506e: 2301 movs r3, #1 8015070: e000 b.n 8015074 8015072: 2300 movs r3, #0 8015074: 2b00 cmp r3, #0 8015076: d10b bne.n 8015090 __asm volatile 8015078: f04f 0350 mov.w r3, #80 @ 0x50 801507c: f383 8811 msr BASEPRI, r3 8015080: f3bf 8f6f isb sy 8015084: f3bf 8f4f dsb sy 8015088: 623b str r3, [r7, #32] } 801508a: bf00 nop 801508c: bf00 nop 801508e: e7fd b.n 801508c that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8015090: f002 ff12 bl 8017eb8 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 8015094: f3ef 8211 mrs r2, BASEPRI 8015098: f04f 0350 mov.w r3, #80 @ 0x50 801509c: f383 8811 msr BASEPRI, r3 80150a0: f3bf 8f6f isb sy 80150a4: f3bf 8f4f dsb sy 80150a8: 61fa str r2, [r7, #28] 80150aa: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 80150ac: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 80150ae: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 80150b0: 6bbb ldr r3, [r7, #56] @ 0x38 80150b2: 6b9a ldr r2, [r3, #56] @ 0x38 80150b4: 6bbb ldr r3, [r7, #56] @ 0x38 80150b6: 6bdb ldr r3, [r3, #60] @ 0x3c 80150b8: 429a cmp r2, r3 80150ba: d302 bcc.n 80150c2 80150bc: 683b ldr r3, [r7, #0] 80150be: 2b02 cmp r3, #2 80150c0: d12f bne.n 8015122 { const int8_t cTxLock = pxQueue->cTxLock; 80150c2: 6bbb ldr r3, [r7, #56] @ 0x38 80150c4: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80150c8: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 80150cc: 6bbb ldr r3, [r7, #56] @ 0x38 80150ce: 6b9b ldr r3, [r3, #56] @ 0x38 80150d0: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80150d2: 683a ldr r2, [r7, #0] 80150d4: 68b9 ldr r1, [r7, #8] 80150d6: 6bb8 ldr r0, [r7, #56] @ 0x38 80150d8: f000 fabc bl 8015654 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80150dc: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 80150e0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80150e4: d112 bne.n 801510c } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80150e6: 6bbb ldr r3, [r7, #56] @ 0x38 80150e8: 6a5b ldr r3, [r3, #36] @ 0x24 80150ea: 2b00 cmp r3, #0 80150ec: d016 beq.n 801511c { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80150ee: 6bbb ldr r3, [r7, #56] @ 0x38 80150f0: 3324 adds r3, #36 @ 0x24 80150f2: 4618 mov r0, r3 80150f4: f001 fa7a bl 80165ec 80150f8: 4603 mov r3, r0 80150fa: 2b00 cmp r3, #0 80150fc: d00e beq.n 801511c { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80150fe: 687b ldr r3, [r7, #4] 8015100: 2b00 cmp r3, #0 8015102: d00b beq.n 801511c { *pxHigherPriorityTaskWoken = pdTRUE; 8015104: 687b ldr r3, [r7, #4] 8015106: 2201 movs r2, #1 8015108: 601a str r2, [r3, #0] 801510a: e007 b.n 801511c } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 801510c: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8015110: 3301 adds r3, #1 8015112: b2db uxtb r3, r3 8015114: b25a sxtb r2, r3 8015116: 6bbb ldr r3, [r7, #56] @ 0x38 8015118: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 801511c: 2301 movs r3, #1 801511e: 63fb str r3, [r7, #60] @ 0x3c { 8015120: e001 b.n 8015126 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 8015122: 2300 movs r3, #0 8015124: 63fb str r3, [r7, #60] @ 0x3c 8015126: 6b7b ldr r3, [r7, #52] @ 0x34 8015128: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 801512a: 697b ldr r3, [r7, #20] 801512c: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 8015130: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 8015132: 6bfb ldr r3, [r7, #60] @ 0x3c } 8015134: 4618 mov r0, r3 8015136: 3740 adds r7, #64 @ 0x40 8015138: 46bd mov sp, r7 801513a: bd80 pop {r7, pc} 0801513c : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { 801513c: b580 push {r7, lr} 801513e: b08c sub sp, #48 @ 0x30 8015140: af00 add r7, sp, #0 8015142: 60f8 str r0, [r7, #12] 8015144: 60b9 str r1, [r7, #8] 8015146: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; 8015148: 2300 movs r3, #0 801514a: 62fb str r3, [r7, #44] @ 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801514c: 68fb ldr r3, [r7, #12] 801514e: 62bb str r3, [r7, #40] @ 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8015150: 6abb ldr r3, [r7, #40] @ 0x28 8015152: 2b00 cmp r3, #0 8015154: d10b bne.n 801516e __asm volatile 8015156: f04f 0350 mov.w r3, #80 @ 0x50 801515a: f383 8811 msr BASEPRI, r3 801515e: f3bf 8f6f isb sy 8015162: f3bf 8f4f dsb sy 8015166: 623b str r3, [r7, #32] } 8015168: bf00 nop 801516a: bf00 nop 801516c: e7fd b.n 801516a /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); 801516e: 68bb ldr r3, [r7, #8] 8015170: 2b00 cmp r3, #0 8015172: d103 bne.n 801517c 8015174: 6abb ldr r3, [r7, #40] @ 0x28 8015176: 6c1b ldr r3, [r3, #64] @ 0x40 8015178: 2b00 cmp r3, #0 801517a: d101 bne.n 8015180 801517c: 2301 movs r3, #1 801517e: e000 b.n 8015182 8015180: 2300 movs r3, #0 8015182: 2b00 cmp r3, #0 8015184: d10b bne.n 801519e __asm volatile 8015186: f04f 0350 mov.w r3, #80 @ 0x50 801518a: f383 8811 msr BASEPRI, r3 801518e: f3bf 8f6f isb sy 8015192: f3bf 8f4f dsb sy 8015196: 61fb str r3, [r7, #28] } 8015198: bf00 nop 801519a: bf00 nop 801519c: e7fd b.n 801519a /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 801519e: f001 fc23 bl 80169e8 80151a2: 4603 mov r3, r0 80151a4: 2b00 cmp r3, #0 80151a6: d102 bne.n 80151ae 80151a8: 687b ldr r3, [r7, #4] 80151aa: 2b00 cmp r3, #0 80151ac: d101 bne.n 80151b2 80151ae: 2301 movs r3, #1 80151b0: e000 b.n 80151b4 80151b2: 2300 movs r3, #0 80151b4: 2b00 cmp r3, #0 80151b6: d10b bne.n 80151d0 __asm volatile 80151b8: f04f 0350 mov.w r3, #80 @ 0x50 80151bc: f383 8811 msr BASEPRI, r3 80151c0: f3bf 8f6f isb sy 80151c4: f3bf 8f4f dsb sy 80151c8: 61bb str r3, [r7, #24] } 80151ca: bf00 nop 80151cc: bf00 nop 80151ce: e7fd b.n 80151cc /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 80151d0: f002 fd92 bl 8017cf8 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80151d4: 6abb ldr r3, [r7, #40] @ 0x28 80151d6: 6b9b ldr r3, [r3, #56] @ 0x38 80151d8: 627b str r3, [r7, #36] @ 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80151da: 6a7b ldr r3, [r7, #36] @ 0x24 80151dc: 2b00 cmp r3, #0 80151de: d01f beq.n 8015220 { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); 80151e0: 68b9 ldr r1, [r7, #8] 80151e2: 6ab8 ldr r0, [r7, #40] @ 0x28 80151e4: f000 faa0 bl 8015728 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80151e8: 6a7b ldr r3, [r7, #36] @ 0x24 80151ea: 1e5a subs r2, r3, #1 80151ec: 6abb ldr r3, [r7, #40] @ 0x28 80151ee: 639a str r2, [r3, #56] @ 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80151f0: 6abb ldr r3, [r7, #40] @ 0x28 80151f2: 691b ldr r3, [r3, #16] 80151f4: 2b00 cmp r3, #0 80151f6: d00f beq.n 8015218 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80151f8: 6abb ldr r3, [r7, #40] @ 0x28 80151fa: 3310 adds r3, #16 80151fc: 4618 mov r0, r3 80151fe: f001 f9f5 bl 80165ec 8015202: 4603 mov r3, r0 8015204: 2b00 cmp r3, #0 8015206: d007 beq.n 8015218 { queueYIELD_IF_USING_PREEMPTION(); 8015208: 4b3c ldr r3, [pc, #240] @ (80152fc ) 801520a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801520e: 601a str r2, [r3, #0] 8015210: f3bf 8f4f dsb sy 8015214: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 8015218: f002 fda0 bl 8017d5c return pdPASS; 801521c: 2301 movs r3, #1 801521e: e069 b.n 80152f4 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8015220: 687b ldr r3, [r7, #4] 8015222: 2b00 cmp r3, #0 8015224: d103 bne.n 801522e { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8015226: f002 fd99 bl 8017d5c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 801522a: 2300 movs r3, #0 801522c: e062 b.n 80152f4 } else if( xEntryTimeSet == pdFALSE ) 801522e: 6afb ldr r3, [r7, #44] @ 0x2c 8015230: 2b00 cmp r3, #0 8015232: d106 bne.n 8015242 { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8015234: f107 0310 add.w r3, r7, #16 8015238: 4618 mov r0, r3 801523a: f001 fa63 bl 8016704 xEntryTimeSet = pdTRUE; 801523e: 2301 movs r3, #1 8015240: 62fb str r3, [r7, #44] @ 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8015242: f002 fd8b bl 8017d5c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8015246: f000 ff95 bl 8016174 prvLockQueue( pxQueue ); 801524a: f002 fd55 bl 8017cf8 801524e: 6abb ldr r3, [r7, #40] @ 0x28 8015250: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8015254: b25b sxtb r3, r3 8015256: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801525a: d103 bne.n 8015264 801525c: 6abb ldr r3, [r7, #40] @ 0x28 801525e: 2200 movs r2, #0 8015260: f883 2044 strb.w r2, [r3, #68] @ 0x44 8015264: 6abb ldr r3, [r7, #40] @ 0x28 8015266: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 801526a: b25b sxtb r3, r3 801526c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015270: d103 bne.n 801527a 8015272: 6abb ldr r3, [r7, #40] @ 0x28 8015274: 2200 movs r2, #0 8015276: f883 2045 strb.w r2, [r3, #69] @ 0x45 801527a: f002 fd6f bl 8017d5c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 801527e: 1d3a adds r2, r7, #4 8015280: f107 0310 add.w r3, r7, #16 8015284: 4611 mov r1, r2 8015286: 4618 mov r0, r3 8015288: f001 fa52 bl 8016730 801528c: 4603 mov r3, r0 801528e: 2b00 cmp r3, #0 8015290: d123 bne.n 80152da { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8015292: 6ab8 ldr r0, [r7, #40] @ 0x28 8015294: f000 fac0 bl 8015818 8015298: 4603 mov r3, r0 801529a: 2b00 cmp r3, #0 801529c: d017 beq.n 80152ce { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 801529e: 6abb ldr r3, [r7, #40] @ 0x28 80152a0: 3324 adds r3, #36 @ 0x24 80152a2: 687a ldr r2, [r7, #4] 80152a4: 4611 mov r1, r2 80152a6: 4618 mov r0, r3 80152a8: f001 f94e bl 8016548 prvUnlockQueue( pxQueue ); 80152ac: 6ab8 ldr r0, [r7, #40] @ 0x28 80152ae: f000 fa61 bl 8015774 if( xTaskResumeAll() == pdFALSE ) 80152b2: f000 ff6d bl 8016190 80152b6: 4603 mov r3, r0 80152b8: 2b00 cmp r3, #0 80152ba: d189 bne.n 80151d0 { portYIELD_WITHIN_API(); 80152bc: 4b0f ldr r3, [pc, #60] @ (80152fc ) 80152be: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80152c2: 601a str r2, [r3, #0] 80152c4: f3bf 8f4f dsb sy 80152c8: f3bf 8f6f isb sy 80152cc: e780 b.n 80151d0 } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); 80152ce: 6ab8 ldr r0, [r7, #40] @ 0x28 80152d0: f000 fa50 bl 8015774 ( void ) xTaskResumeAll(); 80152d4: f000 ff5c bl 8016190 80152d8: e77a b.n 80151d0 } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); 80152da: 6ab8 ldr r0, [r7, #40] @ 0x28 80152dc: f000 fa4a bl 8015774 ( void ) xTaskResumeAll(); 80152e0: f000 ff56 bl 8016190 if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80152e4: 6ab8 ldr r0, [r7, #40] @ 0x28 80152e6: f000 fa97 bl 8015818 80152ea: 4603 mov r3, r0 80152ec: 2b00 cmp r3, #0 80152ee: f43f af6f beq.w 80151d0 { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 80152f2: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 80152f4: 4618 mov r0, r3 80152f6: 3730 adds r7, #48 @ 0x30 80152f8: 46bd mov sp, r7 80152fa: bd80 pop {r7, pc} 80152fc: e000ed04 .word 0xe000ed04 08015300 : /*-----------------------------------------------------------*/ BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) { 8015300: b580 push {r7, lr} 8015302: b08e sub sp, #56 @ 0x38 8015304: af00 add r7, sp, #0 8015306: 6078 str r0, [r7, #4] 8015308: 6039 str r1, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE; 801530a: 2300 movs r3, #0 801530c: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 801530e: 687b ldr r3, [r7, #4] 8015310: 62fb str r3, [r7, #44] @ 0x2c #if( configUSE_MUTEXES == 1 ) BaseType_t xInheritanceOccurred = pdFALSE; 8015312: 2300 movs r3, #0 8015314: 633b str r3, [r7, #48] @ 0x30 #endif /* Check the queue pointer is not NULL. */ configASSERT( ( pxQueue ) ); 8015316: 6afb ldr r3, [r7, #44] @ 0x2c 8015318: 2b00 cmp r3, #0 801531a: d10b bne.n 8015334 __asm volatile 801531c: f04f 0350 mov.w r3, #80 @ 0x50 8015320: f383 8811 msr BASEPRI, r3 8015324: f3bf 8f6f isb sy 8015328: f3bf 8f4f dsb sy 801532c: 623b str r3, [r7, #32] } 801532e: bf00 nop 8015330: bf00 nop 8015332: e7fd b.n 8015330 /* Check this really is a semaphore, in which case the item size will be 0. */ configASSERT( pxQueue->uxItemSize == 0 ); 8015334: 6afb ldr r3, [r7, #44] @ 0x2c 8015336: 6c1b ldr r3, [r3, #64] @ 0x40 8015338: 2b00 cmp r3, #0 801533a: d00b beq.n 8015354 __asm volatile 801533c: f04f 0350 mov.w r3, #80 @ 0x50 8015340: f383 8811 msr BASEPRI, r3 8015344: f3bf 8f6f isb sy 8015348: f3bf 8f4f dsb sy 801534c: 61fb str r3, [r7, #28] } 801534e: bf00 nop 8015350: bf00 nop 8015352: e7fd b.n 8015350 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8015354: f001 fb48 bl 80169e8 8015358: 4603 mov r3, r0 801535a: 2b00 cmp r3, #0 801535c: d102 bne.n 8015364 801535e: 683b ldr r3, [r7, #0] 8015360: 2b00 cmp r3, #0 8015362: d101 bne.n 8015368 8015364: 2301 movs r3, #1 8015366: e000 b.n 801536a 8015368: 2300 movs r3, #0 801536a: 2b00 cmp r3, #0 801536c: d10b bne.n 8015386 __asm volatile 801536e: f04f 0350 mov.w r3, #80 @ 0x50 8015372: f383 8811 msr BASEPRI, r3 8015376: f3bf 8f6f isb sy 801537a: f3bf 8f4f dsb sy 801537e: 61bb str r3, [r7, #24] } 8015380: bf00 nop 8015382: bf00 nop 8015384: e7fd b.n 8015382 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8015386: f002 fcb7 bl 8017cf8 { /* Semaphores are queues with an item size of 0, and where the number of messages in the queue is the semaphore's count value. */ const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; 801538a: 6afb ldr r3, [r7, #44] @ 0x2c 801538c: 6b9b ldr r3, [r3, #56] @ 0x38 801538e: 62bb str r3, [r7, #40] @ 0x28 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxSemaphoreCount > ( UBaseType_t ) 0 ) 8015390: 6abb ldr r3, [r7, #40] @ 0x28 8015392: 2b00 cmp r3, #0 8015394: d024 beq.n 80153e0 { traceQUEUE_RECEIVE( pxQueue ); /* Semaphores are queues with a data size of zero and where the messages waiting is the semaphore's count. Reduce the count. */ pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; 8015396: 6abb ldr r3, [r7, #40] @ 0x28 8015398: 1e5a subs r2, r3, #1 801539a: 6afb ldr r3, [r7, #44] @ 0x2c 801539c: 639a str r2, [r3, #56] @ 0x38 #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801539e: 6afb ldr r3, [r7, #44] @ 0x2c 80153a0: 681b ldr r3, [r3, #0] 80153a2: 2b00 cmp r3, #0 80153a4: d104 bne.n 80153b0 { /* Record the information required to implement priority inheritance should it become necessary. */ pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); 80153a6: f001 fc99 bl 8016cdc 80153aa: 4602 mov r2, r0 80153ac: 6afb ldr r3, [r7, #44] @ 0x2c 80153ae: 609a str r2, [r3, #8] } #endif /* configUSE_MUTEXES */ /* Check to see if other tasks are blocked waiting to give the semaphore, and if so, unblock the highest priority such task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80153b0: 6afb ldr r3, [r7, #44] @ 0x2c 80153b2: 691b ldr r3, [r3, #16] 80153b4: 2b00 cmp r3, #0 80153b6: d00f beq.n 80153d8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80153b8: 6afb ldr r3, [r7, #44] @ 0x2c 80153ba: 3310 adds r3, #16 80153bc: 4618 mov r0, r3 80153be: f001 f915 bl 80165ec 80153c2: 4603 mov r3, r0 80153c4: 2b00 cmp r3, #0 80153c6: d007 beq.n 80153d8 { queueYIELD_IF_USING_PREEMPTION(); 80153c8: 4b54 ldr r3, [pc, #336] @ (801551c ) 80153ca: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80153ce: 601a str r2, [r3, #0] 80153d0: f3bf 8f4f dsb sy 80153d4: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); 80153d8: f002 fcc0 bl 8017d5c return pdPASS; 80153dc: 2301 movs r3, #1 80153de: e098 b.n 8015512 } else { if( xTicksToWait == ( TickType_t ) 0 ) 80153e0: 683b ldr r3, [r7, #0] 80153e2: 2b00 cmp r3, #0 80153e4: d112 bne.n 801540c /* For inheritance to have occurred there must have been an initial timeout, and an adjusted timeout cannot become 0, as if it were 0 the function would have exited. */ #if( configUSE_MUTEXES == 1 ) { configASSERT( xInheritanceOccurred == pdFALSE ); 80153e6: 6b3b ldr r3, [r7, #48] @ 0x30 80153e8: 2b00 cmp r3, #0 80153ea: d00b beq.n 8015404 __asm volatile 80153ec: f04f 0350 mov.w r3, #80 @ 0x50 80153f0: f383 8811 msr BASEPRI, r3 80153f4: f3bf 8f6f isb sy 80153f8: f3bf 8f4f dsb sy 80153fc: 617b str r3, [r7, #20] } 80153fe: bf00 nop 8015400: bf00 nop 8015402: e7fd b.n 8015400 } #endif /* configUSE_MUTEXES */ /* The semaphore count was 0 and no block time is specified (or the block time has expired) so exit now. */ taskEXIT_CRITICAL(); 8015404: f002 fcaa bl 8017d5c traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015408: 2300 movs r3, #0 801540a: e082 b.n 8015512 } else if( xEntryTimeSet == pdFALSE ) 801540c: 6b7b ldr r3, [r7, #52] @ 0x34 801540e: 2b00 cmp r3, #0 8015410: d106 bne.n 8015420 { /* The semaphore count was 0 and a block time was specified so configure the timeout structure ready to block. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8015412: f107 030c add.w r3, r7, #12 8015416: 4618 mov r0, r3 8015418: f001 f974 bl 8016704 xEntryTimeSet = pdTRUE; 801541c: 2301 movs r3, #1 801541e: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8015420: f002 fc9c bl 8017d5c /* Interrupts and other tasks can give to and take from the semaphore now the critical section has been exited. */ vTaskSuspendAll(); 8015424: f000 fea6 bl 8016174 prvLockQueue( pxQueue ); 8015428: f002 fc66 bl 8017cf8 801542c: 6afb ldr r3, [r7, #44] @ 0x2c 801542e: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8015432: b25b sxtb r3, r3 8015434: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8015438: d103 bne.n 8015442 801543a: 6afb ldr r3, [r7, #44] @ 0x2c 801543c: 2200 movs r2, #0 801543e: f883 2044 strb.w r2, [r3, #68] @ 0x44 8015442: 6afb ldr r3, [r7, #44] @ 0x2c 8015444: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015448: b25b sxtb r3, r3 801544a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801544e: d103 bne.n 8015458 8015450: 6afb ldr r3, [r7, #44] @ 0x2c 8015452: 2200 movs r2, #0 8015454: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015458: f002 fc80 bl 8017d5c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 801545c: 463a mov r2, r7 801545e: f107 030c add.w r3, r7, #12 8015462: 4611 mov r1, r2 8015464: 4618 mov r0, r3 8015466: f001 f963 bl 8016730 801546a: 4603 mov r3, r0 801546c: 2b00 cmp r3, #0 801546e: d132 bne.n 80154d6 { /* A block time is specified and not expired. If the semaphore count is 0 then enter the Blocked state to wait for a semaphore to become available. As semaphores are implemented with queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 8015470: 6af8 ldr r0, [r7, #44] @ 0x2c 8015472: f000 f9d1 bl 8015818 8015476: 4603 mov r3, r0 8015478: 2b00 cmp r3, #0 801547a: d026 beq.n 80154ca { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 801547c: 6afb ldr r3, [r7, #44] @ 0x2c 801547e: 681b ldr r3, [r3, #0] 8015480: 2b00 cmp r3, #0 8015482: d109 bne.n 8015498 { taskENTER_CRITICAL(); 8015484: f002 fc38 bl 8017cf8 { xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); 8015488: 6afb ldr r3, [r7, #44] @ 0x2c 801548a: 689b ldr r3, [r3, #8] 801548c: 4618 mov r0, r3 801548e: f001 fac9 bl 8016a24 8015492: 6338 str r0, [r7, #48] @ 0x30 } taskEXIT_CRITICAL(); 8015494: f002 fc62 bl 8017d5c mtCOVERAGE_TEST_MARKER(); } } #endif vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); 8015498: 6afb ldr r3, [r7, #44] @ 0x2c 801549a: 3324 adds r3, #36 @ 0x24 801549c: 683a ldr r2, [r7, #0] 801549e: 4611 mov r1, r2 80154a0: 4618 mov r0, r3 80154a2: f001 f851 bl 8016548 prvUnlockQueue( pxQueue ); 80154a6: 6af8 ldr r0, [r7, #44] @ 0x2c 80154a8: f000 f964 bl 8015774 if( xTaskResumeAll() == pdFALSE ) 80154ac: f000 fe70 bl 8016190 80154b0: 4603 mov r3, r0 80154b2: 2b00 cmp r3, #0 80154b4: f47f af67 bne.w 8015386 { portYIELD_WITHIN_API(); 80154b8: 4b18 ldr r3, [pc, #96] @ (801551c ) 80154ba: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80154be: 601a str r2, [r3, #0] 80154c0: f3bf 8f4f dsb sy 80154c4: f3bf 8f6f isb sy 80154c8: e75d b.n 8015386 } else { /* There was no timeout and the semaphore count was not 0, so attempt to take the semaphore again. */ prvUnlockQueue( pxQueue ); 80154ca: 6af8 ldr r0, [r7, #44] @ 0x2c 80154cc: f000 f952 bl 8015774 ( void ) xTaskResumeAll(); 80154d0: f000 fe5e bl 8016190 80154d4: e757 b.n 8015386 } } else { /* Timed out. */ prvUnlockQueue( pxQueue ); 80154d6: 6af8 ldr r0, [r7, #44] @ 0x2c 80154d8: f000 f94c bl 8015774 ( void ) xTaskResumeAll(); 80154dc: f000 fe58 bl 8016190 /* If the semaphore count is 0 exit now as the timeout has expired. Otherwise return to attempt to take the semaphore that is known to be available. As semaphores are implemented by queues the queue being empty is equivalent to the semaphore count being 0. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) 80154e0: 6af8 ldr r0, [r7, #44] @ 0x2c 80154e2: f000 f999 bl 8015818 80154e6: 4603 mov r3, r0 80154e8: 2b00 cmp r3, #0 80154ea: f43f af4c beq.w 8015386 #if ( configUSE_MUTEXES == 1 ) { /* xInheritanceOccurred could only have be set if pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to test the mutex type again to check it is actually a mutex. */ if( xInheritanceOccurred != pdFALSE ) 80154ee: 6b3b ldr r3, [r7, #48] @ 0x30 80154f0: 2b00 cmp r3, #0 80154f2: d00d beq.n 8015510 { taskENTER_CRITICAL(); 80154f4: f002 fc00 bl 8017cf8 /* This task blocking on the mutex caused another task to inherit this task's priority. Now this task has timed out the priority should be disinherited again, but only as low as the next highest priority task that is waiting for the same mutex. */ uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); 80154f8: 6af8 ldr r0, [r7, #44] @ 0x2c 80154fa: f000 f893 bl 8015624 80154fe: 6278 str r0, [r7, #36] @ 0x24 vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); 8015500: 6afb ldr r3, [r7, #44] @ 0x2c 8015502: 689b ldr r3, [r3, #8] 8015504: 6a79 ldr r1, [r7, #36] @ 0x24 8015506: 4618 mov r0, r3 8015508: f001 fb64 bl 8016bd4 } taskEXIT_CRITICAL(); 801550c: f002 fc26 bl 8017d5c } } #endif /* configUSE_MUTEXES */ traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; 8015510: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } 8015512: 4618 mov r0, r3 8015514: 3738 adds r7, #56 @ 0x38 8015516: 46bd mov sp, r7 8015518: bd80 pop {r7, pc} 801551a: bf00 nop 801551c: e000ed04 .word 0xe000ed04 08015520 : } /*lint -restore */ } /*-----------------------------------------------------------*/ BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) { 8015520: b580 push {r7, lr} 8015522: b08e sub sp, #56 @ 0x38 8015524: af00 add r7, sp, #0 8015526: 60f8 str r0, [r7, #12] 8015528: 60b9 str r1, [r7, #8] 801552a: 607a str r2, [r7, #4] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 801552c: 68fb ldr r3, [r7, #12] 801552e: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8015530: 6b3b ldr r3, [r7, #48] @ 0x30 8015532: 2b00 cmp r3, #0 8015534: d10b bne.n 801554e __asm volatile 8015536: f04f 0350 mov.w r3, #80 @ 0x50 801553a: f383 8811 msr BASEPRI, r3 801553e: f3bf 8f6f isb sy 8015542: f3bf 8f4f dsb sy 8015546: 623b str r3, [r7, #32] } 8015548: bf00 nop 801554a: bf00 nop 801554c: e7fd b.n 801554a configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 801554e: 68bb ldr r3, [r7, #8] 8015550: 2b00 cmp r3, #0 8015552: d103 bne.n 801555c 8015554: 6b3b ldr r3, [r7, #48] @ 0x30 8015556: 6c1b ldr r3, [r3, #64] @ 0x40 8015558: 2b00 cmp r3, #0 801555a: d101 bne.n 8015560 801555c: 2301 movs r3, #1 801555e: e000 b.n 8015562 8015560: 2300 movs r3, #0 8015562: 2b00 cmp r3, #0 8015564: d10b bne.n 801557e __asm volatile 8015566: f04f 0350 mov.w r3, #80 @ 0x50 801556a: f383 8811 msr BASEPRI, r3 801556e: f3bf 8f6f isb sy 8015572: f3bf 8f4f dsb sy 8015576: 61fb str r3, [r7, #28] } 8015578: bf00 nop 801557a: bf00 nop 801557c: e7fd b.n 801557a that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 801557e: f002 fc9b bl 8017eb8 __asm volatile 8015582: f3ef 8211 mrs r2, BASEPRI 8015586: f04f 0350 mov.w r3, #80 @ 0x50 801558a: f383 8811 msr BASEPRI, r3 801558e: f3bf 8f6f isb sy 8015592: f3bf 8f4f dsb sy 8015596: 61ba str r2, [r7, #24] 8015598: 617b str r3, [r7, #20] return ulOriginalBASEPRI; 801559a: 69bb ldr r3, [r7, #24] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 801559c: 62fb str r3, [r7, #44] @ 0x2c { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; 801559e: 6b3b ldr r3, [r7, #48] @ 0x30 80155a0: 6b9b ldr r3, [r3, #56] @ 0x38 80155a2: 62bb str r3, [r7, #40] @ 0x28 /* Cannot block in an ISR, so check there is data available. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 80155a4: 6abb ldr r3, [r7, #40] @ 0x28 80155a6: 2b00 cmp r3, #0 80155a8: d02f beq.n 801560a { const int8_t cRxLock = pxQueue->cRxLock; 80155aa: 6b3b ldr r3, [r7, #48] @ 0x30 80155ac: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80155b0: f887 3027 strb.w r3, [r7, #39] @ 0x27 traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); prvCopyDataFromQueue( pxQueue, pvBuffer ); 80155b4: 68b9 ldr r1, [r7, #8] 80155b6: 6b38 ldr r0, [r7, #48] @ 0x30 80155b8: f000 f8b6 bl 8015728 pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; 80155bc: 6abb ldr r3, [r7, #40] @ 0x28 80155be: 1e5a subs r2, r3, #1 80155c0: 6b3b ldr r3, [r7, #48] @ 0x30 80155c2: 639a str r2, [r3, #56] @ 0x38 /* If the queue is locked the event list will not be modified. Instead update the lock count so the task that unlocks the queue will know that an ISR has removed data while the queue was locked. */ if( cRxLock == queueUNLOCKED ) 80155c4: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27 80155c8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80155cc: d112 bne.n 80155f4 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80155ce: 6b3b ldr r3, [r7, #48] @ 0x30 80155d0: 691b ldr r3, [r3, #16] 80155d2: 2b00 cmp r3, #0 80155d4: d016 beq.n 8015604 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80155d6: 6b3b ldr r3, [r7, #48] @ 0x30 80155d8: 3310 adds r3, #16 80155da: 4618 mov r0, r3 80155dc: f001 f806 bl 80165ec 80155e0: 4603 mov r3, r0 80155e2: 2b00 cmp r3, #0 80155e4: d00e beq.n 8015604 { /* The task waiting has a higher priority than us so force a context switch. */ if( pxHigherPriorityTaskWoken != NULL ) 80155e6: 687b ldr r3, [r7, #4] 80155e8: 2b00 cmp r3, #0 80155ea: d00b beq.n 8015604 { *pxHigherPriorityTaskWoken = pdTRUE; 80155ec: 687b ldr r3, [r7, #4] 80155ee: 2201 movs r2, #1 80155f0: 601a str r2, [r3, #0] 80155f2: e007 b.n 8015604 } else { /* Increment the lock count so the task that unlocks the queue knows that data was removed while it was locked. */ pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 ); 80155f4: f897 3027 ldrb.w r3, [r7, #39] @ 0x27 80155f8: 3301 adds r3, #1 80155fa: b2db uxtb r3, r3 80155fc: b25a sxtb r2, r3 80155fe: 6b3b ldr r3, [r7, #48] @ 0x30 8015600: f883 2044 strb.w r2, [r3, #68] @ 0x44 } xReturn = pdPASS; 8015604: 2301 movs r3, #1 8015606: 637b str r3, [r7, #52] @ 0x34 8015608: e001 b.n 801560e } else { xReturn = pdFAIL; 801560a: 2300 movs r3, #0 801560c: 637b str r3, [r7, #52] @ 0x34 801560e: 6afb ldr r3, [r7, #44] @ 0x2c 8015610: 613b str r3, [r7, #16] __asm volatile 8015612: 693b ldr r3, [r7, #16] 8015614: f383 8811 msr BASEPRI, r3 } 8015618: bf00 nop traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 801561a: 6b7b ldr r3, [r7, #52] @ 0x34 } 801561c: 4618 mov r0, r3 801561e: 3738 adds r7, #56 @ 0x38 8015620: 46bd mov sp, r7 8015622: bd80 pop {r7, pc} 08015624 : /*-----------------------------------------------------------*/ #if( configUSE_MUTEXES == 1 ) static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) { 8015624: b480 push {r7} 8015626: b085 sub sp, #20 8015628: af00 add r7, sp, #0 801562a: 6078 str r0, [r7, #4] priority, but the waiting task times out, then the holder should disinherit the priority - but only down to the highest priority of any other tasks that are waiting for the same mutex. For this purpose, return the priority of the highest priority task that is waiting for the mutex. */ if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) 801562c: 687b ldr r3, [r7, #4] 801562e: 6a5b ldr r3, [r3, #36] @ 0x24 8015630: 2b00 cmp r3, #0 8015632: d006 beq.n 8015642 { uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); 8015634: 687b ldr r3, [r7, #4] 8015636: 6b1b ldr r3, [r3, #48] @ 0x30 8015638: 681b ldr r3, [r3, #0] 801563a: f1c3 0338 rsb r3, r3, #56 @ 0x38 801563e: 60fb str r3, [r7, #12] 8015640: e001 b.n 8015646 } else { uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; 8015642: 2300 movs r3, #0 8015644: 60fb str r3, [r7, #12] } return uxHighestPriorityOfWaitingTasks; 8015646: 68fb ldr r3, [r7, #12] } 8015648: 4618 mov r0, r3 801564a: 3714 adds r7, #20 801564c: 46bd mov sp, r7 801564e: f85d 7b04 ldr.w r7, [sp], #4 8015652: 4770 bx lr 08015654 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 8015654: b580 push {r7, lr} 8015656: b086 sub sp, #24 8015658: af00 add r7, sp, #0 801565a: 60f8 str r0, [r7, #12] 801565c: 60b9 str r1, [r7, #8] 801565e: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8015660: 2300 movs r3, #0 8015662: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8015664: 68fb ldr r3, [r7, #12] 8015666: 6b9b ldr r3, [r3, #56] @ 0x38 8015668: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 801566a: 68fb ldr r3, [r7, #12] 801566c: 6c1b ldr r3, [r3, #64] @ 0x40 801566e: 2b00 cmp r3, #0 8015670: d10d bne.n 801568e { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8015672: 68fb ldr r3, [r7, #12] 8015674: 681b ldr r3, [r3, #0] 8015676: 2b00 cmp r3, #0 8015678: d14d bne.n 8015716 { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 801567a: 68fb ldr r3, [r7, #12] 801567c: 689b ldr r3, [r3, #8] 801567e: 4618 mov r0, r3 8015680: f001 fa38 bl 8016af4 8015684: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 8015686: 68fb ldr r3, [r7, #12] 8015688: 2200 movs r2, #0 801568a: 609a str r2, [r3, #8] 801568c: e043 b.n 8015716 mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 801568e: 687b ldr r3, [r7, #4] 8015690: 2b00 cmp r3, #0 8015692: d119 bne.n 80156c8 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8015694: 68fb ldr r3, [r7, #12] 8015696: 6858 ldr r0, [r3, #4] 8015698: 68fb ldr r3, [r7, #12] 801569a: 6c1b ldr r3, [r3, #64] @ 0x40 801569c: 461a mov r2, r3 801569e: 68b9 ldr r1, [r7, #8] 80156a0: f002 fec4 bl 801842c pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 80156a4: 68fb ldr r3, [r7, #12] 80156a6: 685a ldr r2, [r3, #4] 80156a8: 68fb ldr r3, [r7, #12] 80156aa: 6c1b ldr r3, [r3, #64] @ 0x40 80156ac: 441a add r2, r3 80156ae: 68fb ldr r3, [r7, #12] 80156b0: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80156b2: 68fb ldr r3, [r7, #12] 80156b4: 685a ldr r2, [r3, #4] 80156b6: 68fb ldr r3, [r7, #12] 80156b8: 689b ldr r3, [r3, #8] 80156ba: 429a cmp r2, r3 80156bc: d32b bcc.n 8015716 { pxQueue->pcWriteTo = pxQueue->pcHead; 80156be: 68fb ldr r3, [r7, #12] 80156c0: 681a ldr r2, [r3, #0] 80156c2: 68fb ldr r3, [r7, #12] 80156c4: 605a str r2, [r3, #4] 80156c6: e026 b.n 8015716 mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 80156c8: 68fb ldr r3, [r7, #12] 80156ca: 68d8 ldr r0, [r3, #12] 80156cc: 68fb ldr r3, [r7, #12] 80156ce: 6c1b ldr r3, [r3, #64] @ 0x40 80156d0: 461a mov r2, r3 80156d2: 68b9 ldr r1, [r7, #8] 80156d4: f002 feaa bl 801842c pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 80156d8: 68fb ldr r3, [r7, #12] 80156da: 68da ldr r2, [r3, #12] 80156dc: 68fb ldr r3, [r7, #12] 80156de: 6c1b ldr r3, [r3, #64] @ 0x40 80156e0: 425b negs r3, r3 80156e2: 441a add r2, r3 80156e4: 68fb ldr r3, [r7, #12] 80156e6: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80156e8: 68fb ldr r3, [r7, #12] 80156ea: 68da ldr r2, [r3, #12] 80156ec: 68fb ldr r3, [r7, #12] 80156ee: 681b ldr r3, [r3, #0] 80156f0: 429a cmp r2, r3 80156f2: d207 bcs.n 8015704 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 80156f4: 68fb ldr r3, [r7, #12] 80156f6: 689a ldr r2, [r3, #8] 80156f8: 68fb ldr r3, [r7, #12] 80156fa: 6c1b ldr r3, [r3, #64] @ 0x40 80156fc: 425b negs r3, r3 80156fe: 441a add r2, r3 8015700: 68fb ldr r3, [r7, #12] 8015702: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8015704: 687b ldr r3, [r7, #4] 8015706: 2b02 cmp r3, #2 8015708: d105 bne.n 8015716 { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 801570a: 693b ldr r3, [r7, #16] 801570c: 2b00 cmp r3, #0 801570e: d002 beq.n 8015716 { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8015710: 693b ldr r3, [r7, #16] 8015712: 3b01 subs r3, #1 8015714: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8015716: 693b ldr r3, [r7, #16] 8015718: 1c5a adds r2, r3, #1 801571a: 68fb ldr r3, [r7, #12] 801571c: 639a str r2, [r3, #56] @ 0x38 return xReturn; 801571e: 697b ldr r3, [r7, #20] } 8015720: 4618 mov r0, r3 8015722: 3718 adds r7, #24 8015724: 46bd mov sp, r7 8015726: bd80 pop {r7, pc} 08015728 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { 8015728: b580 push {r7, lr} 801572a: b082 sub sp, #8 801572c: af00 add r7, sp, #0 801572e: 6078 str r0, [r7, #4] 8015730: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) 8015732: 687b ldr r3, [r7, #4] 8015734: 6c1b ldr r3, [r3, #64] @ 0x40 8015736: 2b00 cmp r3, #0 8015738: d018 beq.n 801576c { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 801573a: 687b ldr r3, [r7, #4] 801573c: 68da ldr r2, [r3, #12] 801573e: 687b ldr r3, [r7, #4] 8015740: 6c1b ldr r3, [r3, #64] @ 0x40 8015742: 441a add r2, r3 8015744: 687b ldr r3, [r7, #4] 8015746: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ 8015748: 687b ldr r3, [r7, #4] 801574a: 68da ldr r2, [r3, #12] 801574c: 687b ldr r3, [r7, #4] 801574e: 689b ldr r3, [r3, #8] 8015750: 429a cmp r2, r3 8015752: d303 bcc.n 801575c { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; 8015754: 687b ldr r3, [r7, #4] 8015756: 681a ldr r2, [r3, #0] 8015758: 687b ldr r3, [r7, #4] 801575a: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 801575c: 687b ldr r3, [r7, #4] 801575e: 68d9 ldr r1, [r3, #12] 8015760: 687b ldr r3, [r7, #4] 8015762: 6c1b ldr r3, [r3, #64] @ 0x40 8015764: 461a mov r2, r3 8015766: 6838 ldr r0, [r7, #0] 8015768: f002 fe60 bl 801842c } } 801576c: bf00 nop 801576e: 3708 adds r7, #8 8015770: 46bd mov sp, r7 8015772: bd80 pop {r7, pc} 08015774 : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 8015774: b580 push {r7, lr} 8015776: b084 sub sp, #16 8015778: af00 add r7, sp, #0 801577a: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 801577c: f002 fabc bl 8017cf8 { int8_t cTxLock = pxQueue->cTxLock; 8015780: 687b ldr r3, [r7, #4] 8015782: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8015786: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8015788: e011 b.n 80157ae } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 801578a: 687b ldr r3, [r7, #4] 801578c: 6a5b ldr r3, [r3, #36] @ 0x24 801578e: 2b00 cmp r3, #0 8015790: d012 beq.n 80157b8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8015792: 687b ldr r3, [r7, #4] 8015794: 3324 adds r3, #36 @ 0x24 8015796: 4618 mov r0, r3 8015798: f000 ff28 bl 80165ec 801579c: 4603 mov r3, r0 801579e: 2b00 cmp r3, #0 80157a0: d001 beq.n 80157a6 { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 80157a2: f001 f829 bl 80167f8 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 80157a6: 7bfb ldrb r3, [r7, #15] 80157a8: 3b01 subs r3, #1 80157aa: b2db uxtb r3, r3 80157ac: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 80157ae: f997 300f ldrsb.w r3, [r7, #15] 80157b2: 2b00 cmp r3, #0 80157b4: dce9 bgt.n 801578a 80157b6: e000 b.n 80157ba break; 80157b8: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 80157ba: 687b ldr r3, [r7, #4] 80157bc: 22ff movs r2, #255 @ 0xff 80157be: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 80157c2: f002 facb bl 8017d5c /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 80157c6: f002 fa97 bl 8017cf8 { int8_t cRxLock = pxQueue->cRxLock; 80157ca: 687b ldr r3, [r7, #4] 80157cc: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80157d0: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80157d2: e011 b.n 80157f8 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80157d4: 687b ldr r3, [r7, #4] 80157d6: 691b ldr r3, [r3, #16] 80157d8: 2b00 cmp r3, #0 80157da: d012 beq.n 8015802 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80157dc: 687b ldr r3, [r7, #4] 80157de: 3310 adds r3, #16 80157e0: 4618 mov r0, r3 80157e2: f000 ff03 bl 80165ec 80157e6: 4603 mov r3, r0 80157e8: 2b00 cmp r3, #0 80157ea: d001 beq.n 80157f0 { vTaskMissedYield(); 80157ec: f001 f804 bl 80167f8 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 80157f0: 7bbb ldrb r3, [r7, #14] 80157f2: 3b01 subs r3, #1 80157f4: b2db uxtb r3, r3 80157f6: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80157f8: f997 300e ldrsb.w r3, [r7, #14] 80157fc: 2b00 cmp r3, #0 80157fe: dce9 bgt.n 80157d4 8015800: e000 b.n 8015804 } else { break; 8015802: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8015804: 687b ldr r3, [r7, #4] 8015806: 22ff movs r2, #255 @ 0xff 8015808: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 801580c: f002 faa6 bl 8017d5c } 8015810: bf00 nop 8015812: 3710 adds r7, #16 8015814: 46bd mov sp, r7 8015816: bd80 pop {r7, pc} 08015818 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { 8015818: b580 push {r7, lr} 801581a: b084 sub sp, #16 801581c: af00 add r7, sp, #0 801581e: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8015820: f002 fa6a bl 8017cf8 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) 8015824: 687b ldr r3, [r7, #4] 8015826: 6b9b ldr r3, [r3, #56] @ 0x38 8015828: 2b00 cmp r3, #0 801582a: d102 bne.n 8015832 { xReturn = pdTRUE; 801582c: 2301 movs r3, #1 801582e: 60fb str r3, [r7, #12] 8015830: e001 b.n 8015836 } else { xReturn = pdFALSE; 8015832: 2300 movs r3, #0 8015834: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8015836: f002 fa91 bl 8017d5c return xReturn; 801583a: 68fb ldr r3, [r7, #12] } 801583c: 4618 mov r0, r3 801583e: 3710 adds r7, #16 8015840: 46bd mov sp, r7 8015842: bd80 pop {r7, pc} 08015844 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 8015844: b580 push {r7, lr} 8015846: b084 sub sp, #16 8015848: af00 add r7, sp, #0 801584a: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 801584c: f002 fa54 bl 8017cf8 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8015850: 687b ldr r3, [r7, #4] 8015852: 6b9a ldr r2, [r3, #56] @ 0x38 8015854: 687b ldr r3, [r7, #4] 8015856: 6bdb ldr r3, [r3, #60] @ 0x3c 8015858: 429a cmp r2, r3 801585a: d102 bne.n 8015862 { xReturn = pdTRUE; 801585c: 2301 movs r3, #1 801585e: 60fb str r3, [r7, #12] 8015860: e001 b.n 8015866 } else { xReturn = pdFALSE; 8015862: 2300 movs r3, #0 8015864: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 8015866: f002 fa79 bl 8017d5c return xReturn; 801586a: 68fb ldr r3, [r7, #12] } 801586c: 4618 mov r0, r3 801586e: 3710 adds r7, #16 8015870: 46bd mov sp, r7 8015872: bd80 pop {r7, pc} 08015874 : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { 8015874: b480 push {r7} 8015876: b085 sub sp, #20 8015878: af00 add r7, sp, #0 801587a: 6078 str r0, [r7, #4] 801587c: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 801587e: 2300 movs r3, #0 8015880: 60fb str r3, [r7, #12] 8015882: e014 b.n 80158ae { if( xQueueRegistry[ ux ].pcQueueName == NULL ) 8015884: 4a0f ldr r2, [pc, #60] @ (80158c4 ) 8015886: 68fb ldr r3, [r7, #12] 8015888: f852 3033 ldr.w r3, [r2, r3, lsl #3] 801588c: 2b00 cmp r3, #0 801588e: d10b bne.n 80158a8 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; 8015890: 490c ldr r1, [pc, #48] @ (80158c4 ) 8015892: 68fb ldr r3, [r7, #12] 8015894: 683a ldr r2, [r7, #0] 8015896: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; 801589a: 4a0a ldr r2, [pc, #40] @ (80158c4 ) 801589c: 68fb ldr r3, [r7, #12] 801589e: 00db lsls r3, r3, #3 80158a0: 4413 add r3, r2 80158a2: 687a ldr r2, [r7, #4] 80158a4: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; 80158a6: e006 b.n 80158b6 for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) 80158a8: 68fb ldr r3, [r7, #12] 80158aa: 3301 adds r3, #1 80158ac: 60fb str r3, [r7, #12] 80158ae: 68fb ldr r3, [r7, #12] 80158b0: 2b07 cmp r3, #7 80158b2: d9e7 bls.n 8015884 else { mtCOVERAGE_TEST_MARKER(); } } } 80158b4: bf00 nop 80158b6: bf00 nop 80158b8: 3714 adds r7, #20 80158ba: 46bd mov sp, r7 80158bc: f85d 7b04 ldr.w r7, [sp], #4 80158c0: 4770 bx lr 80158c2: bf00 nop 80158c4: 240029b8 .word 0x240029b8 080158c8 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 80158c8: b580 push {r7, lr} 80158ca: b086 sub sp, #24 80158cc: af00 add r7, sp, #0 80158ce: 60f8 str r0, [r7, #12] 80158d0: 60b9 str r1, [r7, #8] 80158d2: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; 80158d4: 68fb ldr r3, [r7, #12] 80158d6: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); 80158d8: f002 fa0e bl 8017cf8 80158dc: 697b ldr r3, [r7, #20] 80158de: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80158e2: b25b sxtb r3, r3 80158e4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80158e8: d103 bne.n 80158f2 80158ea: 697b ldr r3, [r7, #20] 80158ec: 2200 movs r2, #0 80158ee: f883 2044 strb.w r2, [r3, #68] @ 0x44 80158f2: 697b ldr r3, [r7, #20] 80158f4: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80158f8: b25b sxtb r3, r3 80158fa: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80158fe: d103 bne.n 8015908 8015900: 697b ldr r3, [r7, #20] 8015902: 2200 movs r2, #0 8015904: f883 2045 strb.w r2, [r3, #69] @ 0x45 8015908: f002 fa28 bl 8017d5c if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) 801590c: 697b ldr r3, [r7, #20] 801590e: 6b9b ldr r3, [r3, #56] @ 0x38 8015910: 2b00 cmp r3, #0 8015912: d106 bne.n 8015922 { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); 8015914: 697b ldr r3, [r7, #20] 8015916: 3324 adds r3, #36 @ 0x24 8015918: 687a ldr r2, [r7, #4] 801591a: 68b9 ldr r1, [r7, #8] 801591c: 4618 mov r0, r3 801591e: f000 fe39 bl 8016594 } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); 8015922: 6978 ldr r0, [r7, #20] 8015924: f7ff ff26 bl 8015774 } 8015928: bf00 nop 801592a: 3718 adds r7, #24 801592c: 46bd mov sp, r7 801592e: bd80 pop {r7, pc} 08015930 : return xReturn; } /*-----------------------------------------------------------*/ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) { 8015930: b480 push {r7} 8015932: b087 sub sp, #28 8015934: af00 add r7, sp, #0 8015936: 6078 str r0, [r7, #4] const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 8015938: 687b ldr r3, [r7, #4] 801593a: 613b str r3, [r7, #16] size_t xSpace; configASSERT( pxStreamBuffer ); 801593c: 693b ldr r3, [r7, #16] 801593e: 2b00 cmp r3, #0 8015940: d10b bne.n 801595a __asm volatile 8015942: f04f 0350 mov.w r3, #80 @ 0x50 8015946: f383 8811 msr BASEPRI, r3 801594a: f3bf 8f6f isb sy 801594e: f3bf 8f4f dsb sy 8015952: 60fb str r3, [r7, #12] } 8015954: bf00 nop 8015956: bf00 nop 8015958: e7fd b.n 8015956 xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; 801595a: 693b ldr r3, [r7, #16] 801595c: 689a ldr r2, [r3, #8] 801595e: 693b ldr r3, [r7, #16] 8015960: 681b ldr r3, [r3, #0] 8015962: 4413 add r3, r2 8015964: 617b str r3, [r7, #20] xSpace -= pxStreamBuffer->xHead; 8015966: 693b ldr r3, [r7, #16] 8015968: 685b ldr r3, [r3, #4] 801596a: 697a ldr r2, [r7, #20] 801596c: 1ad3 subs r3, r2, r3 801596e: 617b str r3, [r7, #20] xSpace -= ( size_t ) 1; 8015970: 697b ldr r3, [r7, #20] 8015972: 3b01 subs r3, #1 8015974: 617b str r3, [r7, #20] if( xSpace >= pxStreamBuffer->xLength ) 8015976: 693b ldr r3, [r7, #16] 8015978: 689b ldr r3, [r3, #8] 801597a: 697a ldr r2, [r7, #20] 801597c: 429a cmp r2, r3 801597e: d304 bcc.n 801598a { xSpace -= pxStreamBuffer->xLength; 8015980: 693b ldr r3, [r7, #16] 8015982: 689b ldr r3, [r3, #8] 8015984: 697a ldr r2, [r7, #20] 8015986: 1ad3 subs r3, r2, r3 8015988: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xSpace; 801598a: 697b ldr r3, [r7, #20] } 801598c: 4618 mov r0, r3 801598e: 371c adds r7, #28 8015990: 46bd mov sp, r7 8015992: f85d 7b04 ldr.w r7, [sp], #4 8015996: 4770 bx lr 08015998 : size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) { 8015998: b580 push {r7, lr} 801599a: b090 sub sp, #64 @ 0x40 801599c: af02 add r7, sp, #8 801599e: 60f8 str r0, [r7, #12] 80159a0: 60b9 str r1, [r7, #8] 80159a2: 607a str r2, [r7, #4] 80159a4: 603b str r3, [r7, #0] StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; 80159a6: 68fb ldr r3, [r7, #12] 80159a8: 62fb str r3, [r7, #44] @ 0x2c size_t xReturn, xSpace = 0; 80159aa: 2300 movs r3, #0 80159ac: 637b str r3, [r7, #52] @ 0x34 size_t xRequiredSpace = xDataLengthBytes; 80159ae: 687b ldr r3, [r7, #4] 80159b0: 633b str r3, [r7, #48] @ 0x30 TimeOut_t xTimeOut; configASSERT( pvTxData ); 80159b2: 68bb ldr r3, [r7, #8] 80159b4: 2b00 cmp r3, #0 80159b6: d10b bne.n 80159d0 __asm volatile 80159b8: f04f 0350 mov.w r3, #80 @ 0x50 80159bc: f383 8811 msr BASEPRI, r3 80159c0: f3bf 8f6f isb sy 80159c4: f3bf 8f4f dsb sy 80159c8: 627b str r3, [r7, #36] @ 0x24 } 80159ca: bf00 nop 80159cc: bf00 nop 80159ce: e7fd b.n 80159cc configASSERT( pxStreamBuffer ); 80159d0: 6afb ldr r3, [r7, #44] @ 0x2c 80159d2: 2b00 cmp r3, #0 80159d4: d10b bne.n 80159ee __asm volatile 80159d6: f04f 0350 mov.w r3, #80 @ 0x50 80159da: f383 8811 msr BASEPRI, r3 80159de: f3bf 8f6f isb sy 80159e2: f3bf 8f4f dsb sy 80159e6: 623b str r3, [r7, #32] } 80159e8: bf00 nop 80159ea: bf00 nop 80159ec: e7fd b.n 80159ea /* This send function is used to write to both message buffers and stream buffers. If this is a message buffer then the space needed must be increased by the amount of bytes needed to store the length of the message. */ if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) 80159ee: 6afb ldr r3, [r7, #44] @ 0x2c 80159f0: 7f1b ldrb r3, [r3, #28] 80159f2: f003 0301 and.w r3, r3, #1 80159f6: 2b00 cmp r3, #0 80159f8: d012 beq.n 8015a20 { xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; 80159fa: 6b3b ldr r3, [r7, #48] @ 0x30 80159fc: 3304 adds r3, #4 80159fe: 633b str r3, [r7, #48] @ 0x30 /* Overflow? */ configASSERT( xRequiredSpace > xDataLengthBytes ); 8015a00: 6b3a ldr r2, [r7, #48] @ 0x30 8015a02: 687b ldr r3, [r7, #4] 8015a04: 429a cmp r2, r3 8015a06: d80b bhi.n 8015a20 __asm volatile 8015a08: f04f 0350 mov.w r3, #80 @ 0x50 8015a0c: f383 8811 msr BASEPRI, r3 8015a10: f3bf 8f6f isb sy 8015a14: f3bf 8f4f dsb sy 8015a18: 61fb str r3, [r7, #28] } 8015a1a: bf00 nop 8015a1c: bf00 nop 8015a1e: e7fd b.n 8015a1c else { mtCOVERAGE_TEST_MARKER(); } if( xTicksToWait != ( TickType_t ) 0 ) 8015a20: 683b ldr r3, [r7, #0] 8015a22: 2b00 cmp r3, #0 8015a24: d03f beq.n 8015aa6 { vTaskSetTimeOutState( &xTimeOut ); 8015a26: f107 0310 add.w r3, r7, #16 8015a2a: 4618 mov r0, r3 8015a2c: f000 fe42 bl 80166b4 do { /* Wait until the required number of bytes are free in the message buffer. */ taskENTER_CRITICAL(); 8015a30: f002 f962 bl 8017cf8 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015a34: 6af8 ldr r0, [r7, #44] @ 0x2c 8015a36: f7ff ff7b bl 8015930 8015a3a: 6378 str r0, [r7, #52] @ 0x34 if( xSpace < xRequiredSpace ) 8015a3c: 6b7a ldr r2, [r7, #52] @ 0x34 8015a3e: 6b3b ldr r3, [r7, #48] @ 0x30 8015a40: 429a cmp r2, r3 8015a42: d218 bcs.n 8015a76 { /* Clear notification state as going to wait for space. */ ( void ) xTaskNotifyStateClear( NULL ); 8015a44: 2000 movs r0, #0 8015a46: f001 fb65 bl 8017114 /* Should only be one writer. */ configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); 8015a4a: 6afb ldr r3, [r7, #44] @ 0x2c 8015a4c: 695b ldr r3, [r3, #20] 8015a4e: 2b00 cmp r3, #0 8015a50: d00b beq.n 8015a6a __asm volatile 8015a52: f04f 0350 mov.w r3, #80 @ 0x50 8015a56: f383 8811 msr BASEPRI, r3 8015a5a: f3bf 8f6f isb sy 8015a5e: f3bf 8f4f dsb sy 8015a62: 61bb str r3, [r7, #24] } 8015a64: bf00 nop 8015a66: bf00 nop 8015a68: e7fd b.n 8015a66 pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); 8015a6a: f000 ffad bl 80169c8 8015a6e: 4602 mov r2, r0 8015a70: 6afb ldr r3, [r7, #44] @ 0x2c 8015a72: 615a str r2, [r3, #20] 8015a74: e002 b.n 8015a7c } else { taskEXIT_CRITICAL(); 8015a76: f002 f971 bl 8017d5c break; 8015a7a: e014 b.n 8015aa6 } } taskEXIT_CRITICAL(); 8015a7c: f002 f96e bl 8017d5c traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); 8015a80: 683b ldr r3, [r7, #0] 8015a82: 2200 movs r2, #0 8015a84: 2100 movs r1, #0 8015a86: 2000 movs r0, #0 8015a88: f001 f93c bl 8016d04 pxStreamBuffer->xTaskWaitingToSend = NULL; 8015a8c: 6afb ldr r3, [r7, #44] @ 0x2c 8015a8e: 2200 movs r2, #0 8015a90: 615a str r2, [r3, #20] } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); 8015a92: 463a mov r2, r7 8015a94: f107 0310 add.w r3, r7, #16 8015a98: 4611 mov r1, r2 8015a9a: 4618 mov r0, r3 8015a9c: f000 fe48 bl 8016730 8015aa0: 4603 mov r3, r0 8015aa2: 2b00 cmp r3, #0 8015aa4: d0c4 beq.n 8015a30 else { mtCOVERAGE_TEST_MARKER(); } if( xSpace == ( size_t ) 0 ) 8015aa6: 6b7b ldr r3, [r7, #52] @ 0x34 8015aa8: 2b00 cmp r3, #0 8015aaa: d103 bne.n 8015ab4 { xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); 8015aac: 6af8 ldr r0, [r7, #44] @ 0x2c 8015aae: f7ff ff3f bl 8015930 8015ab2: 6378 str r0, [r7, #52] @ 0x34 else { mtCOVERAGE_TEST_MARKER(); } xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); 8015ab4: 6b3b ldr r3, [r7, #48] @ 0x30 8015ab6: 9300 str r3, [sp, #0] 8015ab8: 6b7b ldr r3, [r7, #52] @ 0x34 8015aba: 687a ldr r2, [r7, #4] 8015abc: 68b9 ldr r1, [r7, #8] 8015abe: 6af8 ldr r0, [r7, #44] @ 0x2c 8015ac0: f000 f823 bl 8015b0a 8015ac4: 62b8 str r0, [r7, #40] @ 0x28 if( xReturn > ( size_t ) 0 ) 8015ac6: 6abb ldr r3, [r7, #40] @ 0x28 8015ac8: 2b00 cmp r3, #0 8015aca: d019 beq.n 8015b00 { traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); /* Was a task waiting for the data? */ if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) 8015acc: 6af8 ldr r0, [r7, #44] @ 0x2c 8015ace: f000 f8ce bl 8015c6e 8015ad2: 4602 mov r2, r0 8015ad4: 6afb ldr r3, [r7, #44] @ 0x2c 8015ad6: 68db ldr r3, [r3, #12] 8015ad8: 429a cmp r2, r3 8015ada: d311 bcc.n 8015b00 { sbSEND_COMPLETED( pxStreamBuffer ); 8015adc: f000 fb4a bl 8016174 8015ae0: 6afb ldr r3, [r7, #44] @ 0x2c 8015ae2: 691b ldr r3, [r3, #16] 8015ae4: 2b00 cmp r3, #0 8015ae6: d009 beq.n 8015afc 8015ae8: 6afb ldr r3, [r7, #44] @ 0x2c 8015aea: 6918 ldr r0, [r3, #16] 8015aec: 2300 movs r3, #0 8015aee: 2200 movs r2, #0 8015af0: 2100 movs r1, #0 8015af2: f001 f967 bl 8016dc4 8015af6: 6afb ldr r3, [r7, #44] @ 0x2c 8015af8: 2200 movs r2, #0 8015afa: 611a str r2, [r3, #16] 8015afc: f000 fb48 bl 8016190 { mtCOVERAGE_TEST_MARKER(); traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); } return xReturn; 8015b00: 6abb ldr r3, [r7, #40] @ 0x28 } 8015b02: 4618 mov r0, r3 8015b04: 3738 adds r7, #56 @ 0x38 8015b06: 46bd mov sp, r7 8015b08: bd80 pop {r7, pc} 08015b0a : static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, const void * pvTxData, size_t xDataLengthBytes, size_t xSpace, size_t xRequiredSpace ) { 8015b0a: b580 push {r7, lr} 8015b0c: b086 sub sp, #24 8015b0e: af00 add r7, sp, #0 8015b10: 60f8 str r0, [r7, #12] 8015b12: 60b9 str r1, [r7, #8] 8015b14: 607a str r2, [r7, #4] 8015b16: 603b str r3, [r7, #0] BaseType_t xShouldWrite; size_t xReturn; if( xSpace == ( size_t ) 0 ) 8015b18: 683b ldr r3, [r7, #0] 8015b1a: 2b00 cmp r3, #0 8015b1c: d102 bne.n 8015b24 { /* Doesn't matter if this is a stream buffer or a message buffer, there is no space to write. */ xShouldWrite = pdFALSE; 8015b1e: 2300 movs r3, #0 8015b20: 617b str r3, [r7, #20] 8015b22: e01d b.n 8015b60 } else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) 8015b24: 68fb ldr r3, [r7, #12] 8015b26: 7f1b ldrb r3, [r3, #28] 8015b28: f003 0301 and.w r3, r3, #1 8015b2c: 2b00 cmp r3, #0 8015b2e: d108 bne.n 8015b42 { /* This is a stream buffer, as opposed to a message buffer, so writing a stream of bytes rather than discrete messages. Write as many bytes as possible. */ xShouldWrite = pdTRUE; 8015b30: 2301 movs r3, #1 8015b32: 617b str r3, [r7, #20] xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); 8015b34: 687a ldr r2, [r7, #4] 8015b36: 683b ldr r3, [r7, #0] 8015b38: 4293 cmp r3, r2 8015b3a: bf28 it cs 8015b3c: 4613 movcs r3, r2 8015b3e: 607b str r3, [r7, #4] 8015b40: e00e b.n 8015b60 } else if( xSpace >= xRequiredSpace ) 8015b42: 683a ldr r2, [r7, #0] 8015b44: 6a3b ldr r3, [r7, #32] 8015b46: 429a cmp r2, r3 8015b48: d308 bcc.n 8015b5c { /* This is a message buffer, as opposed to a stream buffer, and there is enough space to write both the message length and the message itself into the buffer. Start by writing the length of the data, the data itself will be written later in this function. */ xShouldWrite = pdTRUE; 8015b4a: 2301 movs r3, #1 8015b4c: 617b str r3, [r7, #20] ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); 8015b4e: 1d3b adds r3, r7, #4 8015b50: 2204 movs r2, #4 8015b52: 4619 mov r1, r3 8015b54: 68f8 ldr r0, [r7, #12] 8015b56: f000 f815 bl 8015b84 8015b5a: e001 b.n 8015b60 } else { /* There is space available, but not enough space. */ xShouldWrite = pdFALSE; 8015b5c: 2300 movs r3, #0 8015b5e: 617b str r3, [r7, #20] } if( xShouldWrite != pdFALSE ) 8015b60: 697b ldr r3, [r7, #20] 8015b62: 2b00 cmp r3, #0 8015b64: d007 beq.n 8015b76 { /* Writes the data itself. */ xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */ 8015b66: 687b ldr r3, [r7, #4] 8015b68: 461a mov r2, r3 8015b6a: 68b9 ldr r1, [r7, #8] 8015b6c: 68f8 ldr r0, [r7, #12] 8015b6e: f000 f809 bl 8015b84 8015b72: 6138 str r0, [r7, #16] 8015b74: e001 b.n 8015b7a } else { xReturn = 0; 8015b76: 2300 movs r3, #0 8015b78: 613b str r3, [r7, #16] } return xReturn; 8015b7a: 693b ldr r3, [r7, #16] } 8015b7c: 4618 mov r0, r3 8015b7e: 3718 adds r7, #24 8015b80: 46bd mov sp, r7 8015b82: bd80 pop {r7, pc} 08015b84 : return xReturn; } /*-----------------------------------------------------------*/ static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) { 8015b84: b580 push {r7, lr} 8015b86: b08a sub sp, #40 @ 0x28 8015b88: af00 add r7, sp, #0 8015b8a: 60f8 str r0, [r7, #12] 8015b8c: 60b9 str r1, [r7, #8] 8015b8e: 607a str r2, [r7, #4] size_t xNextHead, xFirstLength; configASSERT( xCount > ( size_t ) 0 ); 8015b90: 687b ldr r3, [r7, #4] 8015b92: 2b00 cmp r3, #0 8015b94: d10b bne.n 8015bae __asm volatile 8015b96: f04f 0350 mov.w r3, #80 @ 0x50 8015b9a: f383 8811 msr BASEPRI, r3 8015b9e: f3bf 8f6f isb sy 8015ba2: f3bf 8f4f dsb sy 8015ba6: 61fb str r3, [r7, #28] } 8015ba8: bf00 nop 8015baa: bf00 nop 8015bac: e7fd b.n 8015baa xNextHead = pxStreamBuffer->xHead; 8015bae: 68fb ldr r3, [r7, #12] 8015bb0: 685b ldr r3, [r3, #4] 8015bb2: 627b str r3, [r7, #36] @ 0x24 /* Calculate the number of bytes that can be added in the first write - which may be less than the total number of bytes that need to be added if the buffer will wrap back to the beginning. */ xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); 8015bb4: 68fb ldr r3, [r7, #12] 8015bb6: 689a ldr r2, [r3, #8] 8015bb8: 6a7b ldr r3, [r7, #36] @ 0x24 8015bba: 1ad3 subs r3, r2, r3 8015bbc: 687a ldr r2, [r7, #4] 8015bbe: 4293 cmp r3, r2 8015bc0: bf28 it cs 8015bc2: 4613 movcs r3, r2 8015bc4: 623b str r3, [r7, #32] /* Write as many bytes as can be written in the first write. */ configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); 8015bc6: 6a7a ldr r2, [r7, #36] @ 0x24 8015bc8: 6a3b ldr r3, [r7, #32] 8015bca: 441a add r2, r3 8015bcc: 68fb ldr r3, [r7, #12] 8015bce: 689b ldr r3, [r3, #8] 8015bd0: 429a cmp r2, r3 8015bd2: d90b bls.n 8015bec __asm volatile 8015bd4: f04f 0350 mov.w r3, #80 @ 0x50 8015bd8: f383 8811 msr BASEPRI, r3 8015bdc: f3bf 8f6f isb sy 8015be0: f3bf 8f4f dsb sy 8015be4: 61bb str r3, [r7, #24] } 8015be6: bf00 nop 8015be8: bf00 nop 8015bea: e7fd b.n 8015be8 ( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015bec: 68fb ldr r3, [r7, #12] 8015bee: 699a ldr r2, [r3, #24] 8015bf0: 6a7b ldr r3, [r7, #36] @ 0x24 8015bf2: 4413 add r3, r2 8015bf4: 6a3a ldr r2, [r7, #32] 8015bf6: 68b9 ldr r1, [r7, #8] 8015bf8: 4618 mov r0, r3 8015bfa: f002 fc17 bl 801842c /* If the number of bytes written was less than the number that could be written in the first write... */ if( xCount > xFirstLength ) 8015bfe: 687a ldr r2, [r7, #4] 8015c00: 6a3b ldr r3, [r7, #32] 8015c02: 429a cmp r2, r3 8015c04: d91d bls.n 8015c42 { /* ...then write the remaining bytes to the start of the buffer. */ configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); 8015c06: 687a ldr r2, [r7, #4] 8015c08: 6a3b ldr r3, [r7, #32] 8015c0a: 1ad2 subs r2, r2, r3 8015c0c: 68fb ldr r3, [r7, #12] 8015c0e: 689b ldr r3, [r3, #8] 8015c10: 429a cmp r2, r3 8015c12: d90b bls.n 8015c2c __asm volatile 8015c14: f04f 0350 mov.w r3, #80 @ 0x50 8015c18: f383 8811 msr BASEPRI, r3 8015c1c: f3bf 8f6f isb sy 8015c20: f3bf 8f4f dsb sy 8015c24: 617b str r3, [r7, #20] } 8015c26: bf00 nop 8015c28: bf00 nop 8015c2a: e7fd b.n 8015c28 ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ 8015c2c: 68fb ldr r3, [r7, #12] 8015c2e: 6998 ldr r0, [r3, #24] 8015c30: 68ba ldr r2, [r7, #8] 8015c32: 6a3b ldr r3, [r7, #32] 8015c34: 18d1 adds r1, r2, r3 8015c36: 687a ldr r2, [r7, #4] 8015c38: 6a3b ldr r3, [r7, #32] 8015c3a: 1ad3 subs r3, r2, r3 8015c3c: 461a mov r2, r3 8015c3e: f002 fbf5 bl 801842c else { mtCOVERAGE_TEST_MARKER(); } xNextHead += xCount; 8015c42: 6a7a ldr r2, [r7, #36] @ 0x24 8015c44: 687b ldr r3, [r7, #4] 8015c46: 4413 add r3, r2 8015c48: 627b str r3, [r7, #36] @ 0x24 if( xNextHead >= pxStreamBuffer->xLength ) 8015c4a: 68fb ldr r3, [r7, #12] 8015c4c: 689b ldr r3, [r3, #8] 8015c4e: 6a7a ldr r2, [r7, #36] @ 0x24 8015c50: 429a cmp r2, r3 8015c52: d304 bcc.n 8015c5e { xNextHead -= pxStreamBuffer->xLength; 8015c54: 68fb ldr r3, [r7, #12] 8015c56: 689b ldr r3, [r3, #8] 8015c58: 6a7a ldr r2, [r7, #36] @ 0x24 8015c5a: 1ad3 subs r3, r2, r3 8015c5c: 627b str r3, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } pxStreamBuffer->xHead = xNextHead; 8015c5e: 68fb ldr r3, [r7, #12] 8015c60: 6a7a ldr r2, [r7, #36] @ 0x24 8015c62: 605a str r2, [r3, #4] return xCount; 8015c64: 687b ldr r3, [r7, #4] } 8015c66: 4618 mov r0, r3 8015c68: 3728 adds r7, #40 @ 0x28 8015c6a: 46bd mov sp, r7 8015c6c: bd80 pop {r7, pc} 08015c6e : return xCount; } /*-----------------------------------------------------------*/ static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) { 8015c6e: b480 push {r7} 8015c70: b085 sub sp, #20 8015c72: af00 add r7, sp, #0 8015c74: 6078 str r0, [r7, #4] /* Returns the distance between xTail and xHead. */ size_t xCount; xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; 8015c76: 687b ldr r3, [r7, #4] 8015c78: 689a ldr r2, [r3, #8] 8015c7a: 687b ldr r3, [r7, #4] 8015c7c: 685b ldr r3, [r3, #4] 8015c7e: 4413 add r3, r2 8015c80: 60fb str r3, [r7, #12] xCount -= pxStreamBuffer->xTail; 8015c82: 687b ldr r3, [r7, #4] 8015c84: 681b ldr r3, [r3, #0] 8015c86: 68fa ldr r2, [r7, #12] 8015c88: 1ad3 subs r3, r2, r3 8015c8a: 60fb str r3, [r7, #12] if ( xCount >= pxStreamBuffer->xLength ) 8015c8c: 687b ldr r3, [r7, #4] 8015c8e: 689b ldr r3, [r3, #8] 8015c90: 68fa ldr r2, [r7, #12] 8015c92: 429a cmp r2, r3 8015c94: d304 bcc.n 8015ca0 { xCount -= pxStreamBuffer->xLength; 8015c96: 687b ldr r3, [r7, #4] 8015c98: 689b ldr r3, [r3, #8] 8015c9a: 68fa ldr r2, [r7, #12] 8015c9c: 1ad3 subs r3, r2, r3 8015c9e: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xCount; 8015ca0: 68fb ldr r3, [r7, #12] } 8015ca2: 4618 mov r0, r3 8015ca4: 3714 adds r7, #20 8015ca6: 46bd mov sp, r7 8015ca8: f85d 7b04 ldr.w r7, [sp], #4 8015cac: 4770 bx lr 08015cae : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { 8015cae: b580 push {r7, lr} 8015cb0: b08e sub sp, #56 @ 0x38 8015cb2: af04 add r7, sp, #16 8015cb4: 60f8 str r0, [r7, #12] 8015cb6: 60b9 str r1, [r7, #8] 8015cb8: 607a str r2, [r7, #4] 8015cba: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); 8015cbc: 6b7b ldr r3, [r7, #52] @ 0x34 8015cbe: 2b00 cmp r3, #0 8015cc0: d10b bne.n 8015cda __asm volatile 8015cc2: f04f 0350 mov.w r3, #80 @ 0x50 8015cc6: f383 8811 msr BASEPRI, r3 8015cca: f3bf 8f6f isb sy 8015cce: f3bf 8f4f dsb sy 8015cd2: 623b str r3, [r7, #32] } 8015cd4: bf00 nop 8015cd6: bf00 nop 8015cd8: e7fd b.n 8015cd6 configASSERT( pxTaskBuffer != NULL ); 8015cda: 6bbb ldr r3, [r7, #56] @ 0x38 8015cdc: 2b00 cmp r3, #0 8015cde: d10b bne.n 8015cf8 __asm volatile 8015ce0: f04f 0350 mov.w r3, #80 @ 0x50 8015ce4: f383 8811 msr BASEPRI, r3 8015ce8: f3bf 8f6f isb sy 8015cec: f3bf 8f4f dsb sy 8015cf0: 61fb str r3, [r7, #28] } 8015cf2: bf00 nop 8015cf4: bf00 nop 8015cf6: e7fd b.n 8015cf4 #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); 8015cf8: 23a8 movs r3, #168 @ 0xa8 8015cfa: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); 8015cfc: 693b ldr r3, [r7, #16] 8015cfe: 2ba8 cmp r3, #168 @ 0xa8 8015d00: d00b beq.n 8015d1a __asm volatile 8015d02: f04f 0350 mov.w r3, #80 @ 0x50 8015d06: f383 8811 msr BASEPRI, r3 8015d0a: f3bf 8f6f isb sy 8015d0e: f3bf 8f4f dsb sy 8015d12: 61bb str r3, [r7, #24] } 8015d14: bf00 nop 8015d16: bf00 nop 8015d18: e7fd b.n 8015d16 ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ 8015d1a: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) 8015d1c: 6bbb ldr r3, [r7, #56] @ 0x38 8015d1e: 2b00 cmp r3, #0 8015d20: d01e beq.n 8015d60 8015d22: 6b7b ldr r3, [r7, #52] @ 0x34 8015d24: 2b00 cmp r3, #0 8015d26: d01b beq.n 8015d60 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ 8015d28: 6bbb ldr r3, [r7, #56] @ 0x38 8015d2a: 627b str r3, [r7, #36] @ 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; 8015d2c: 6a7b ldr r3, [r7, #36] @ 0x24 8015d2e: 6b7a ldr r2, [r7, #52] @ 0x34 8015d30: 631a str r2, [r3, #48] @ 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; 8015d32: 6a7b ldr r3, [r7, #36] @ 0x24 8015d34: 2202 movs r2, #2 8015d36: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); 8015d3a: 2300 movs r3, #0 8015d3c: 9303 str r3, [sp, #12] 8015d3e: 6a7b ldr r3, [r7, #36] @ 0x24 8015d40: 9302 str r3, [sp, #8] 8015d42: f107 0314 add.w r3, r7, #20 8015d46: 9301 str r3, [sp, #4] 8015d48: 6b3b ldr r3, [r7, #48] @ 0x30 8015d4a: 9300 str r3, [sp, #0] 8015d4c: 683b ldr r3, [r7, #0] 8015d4e: 687a ldr r2, [r7, #4] 8015d50: 68b9 ldr r1, [r7, #8] 8015d52: 68f8 ldr r0, [r7, #12] 8015d54: f000 f850 bl 8015df8 prvAddNewTaskToReadyList( pxNewTCB ); 8015d58: 6a78 ldr r0, [r7, #36] @ 0x24 8015d5a: f000 f8f5 bl 8015f48 8015d5e: e001 b.n 8015d64 } else { xReturn = NULL; 8015d60: 2300 movs r3, #0 8015d62: 617b str r3, [r7, #20] } return xReturn; 8015d64: 697b ldr r3, [r7, #20] } 8015d66: 4618 mov r0, r3 8015d68: 3728 adds r7, #40 @ 0x28 8015d6a: 46bd mov sp, r7 8015d6c: bd80 pop {r7, pc} 08015d6e : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { 8015d6e: b580 push {r7, lr} 8015d70: b08c sub sp, #48 @ 0x30 8015d72: af04 add r7, sp, #16 8015d74: 60f8 str r0, [r7, #12] 8015d76: 60b9 str r1, [r7, #8] 8015d78: 603b str r3, [r7, #0] 8015d7a: 4613 mov r3, r2 8015d7c: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ 8015d7e: 88fb ldrh r3, [r7, #6] 8015d80: 009b lsls r3, r3, #2 8015d82: 4618 mov r0, r3 8015d84: f002 f8da bl 8017f3c 8015d88: 6178 str r0, [r7, #20] if( pxStack != NULL ) 8015d8a: 697b ldr r3, [r7, #20] 8015d8c: 2b00 cmp r3, #0 8015d8e: d00e beq.n 8015dae { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ 8015d90: 20a8 movs r0, #168 @ 0xa8 8015d92: f002 f8d3 bl 8017f3c 8015d96: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) 8015d98: 69fb ldr r3, [r7, #28] 8015d9a: 2b00 cmp r3, #0 8015d9c: d003 beq.n 8015da6 { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; 8015d9e: 69fb ldr r3, [r7, #28] 8015da0: 697a ldr r2, [r7, #20] 8015da2: 631a str r2, [r3, #48] @ 0x30 8015da4: e005 b.n 8015db2 } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); 8015da6: 6978 ldr r0, [r7, #20] 8015da8: f002 f996 bl 80180d8 8015dac: e001 b.n 8015db2 } } else { pxNewTCB = NULL; 8015dae: 2300 movs r3, #0 8015db0: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) 8015db2: 69fb ldr r3, [r7, #28] 8015db4: 2b00 cmp r3, #0 8015db6: d017 beq.n 8015de8 { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; 8015db8: 69fb ldr r3, [r7, #28] 8015dba: 2200 movs r2, #0 8015dbc: f883 20a5 strb.w r2, [r3, #165] @ 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); 8015dc0: 88fa ldrh r2, [r7, #6] 8015dc2: 2300 movs r3, #0 8015dc4: 9303 str r3, [sp, #12] 8015dc6: 69fb ldr r3, [r7, #28] 8015dc8: 9302 str r3, [sp, #8] 8015dca: 6afb ldr r3, [r7, #44] @ 0x2c 8015dcc: 9301 str r3, [sp, #4] 8015dce: 6abb ldr r3, [r7, #40] @ 0x28 8015dd0: 9300 str r3, [sp, #0] 8015dd2: 683b ldr r3, [r7, #0] 8015dd4: 68b9 ldr r1, [r7, #8] 8015dd6: 68f8 ldr r0, [r7, #12] 8015dd8: f000 f80e bl 8015df8 prvAddNewTaskToReadyList( pxNewTCB ); 8015ddc: 69f8 ldr r0, [r7, #28] 8015dde: f000 f8b3 bl 8015f48 xReturn = pdPASS; 8015de2: 2301 movs r3, #1 8015de4: 61bb str r3, [r7, #24] 8015de6: e002 b.n 8015dee } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; 8015de8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8015dec: 61bb str r3, [r7, #24] } return xReturn; 8015dee: 69bb ldr r3, [r7, #24] } 8015df0: 4618 mov r0, r3 8015df2: 3720 adds r7, #32 8015df4: 46bd mov sp, r7 8015df6: bd80 pop {r7, pc} 08015df8 : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { 8015df8: b580 push {r7, lr} 8015dfa: b088 sub sp, #32 8015dfc: af00 add r7, sp, #0 8015dfe: 60f8 str r0, [r7, #12] 8015e00: 60b9 str r1, [r7, #8] 8015e02: 607a str r2, [r7, #4] 8015e04: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); 8015e06: 6b3b ldr r3, [r7, #48] @ 0x30 8015e08: 6b18 ldr r0, [r3, #48] @ 0x30 8015e0a: 687b ldr r3, [r7, #4] 8015e0c: 009b lsls r3, r3, #2 8015e0e: 461a mov r2, r3 8015e10: 21a5 movs r1, #165 @ 0xa5 8015e12: f002 fa81 bl 8018318 grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); 8015e16: 6b3b ldr r3, [r7, #48] @ 0x30 8015e18: 6b1a ldr r2, [r3, #48] @ 0x30 8015e1a: 6879 ldr r1, [r7, #4] 8015e1c: f06f 4340 mvn.w r3, #3221225472 @ 0xc0000000 8015e20: 440b add r3, r1 8015e22: 009b lsls r3, r3, #2 8015e24: 4413 add r3, r2 8015e26: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ 8015e28: 69bb ldr r3, [r7, #24] 8015e2a: f023 0307 bic.w r3, r3, #7 8015e2e: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); 8015e30: 69bb ldr r3, [r7, #24] 8015e32: f003 0307 and.w r3, r3, #7 8015e36: 2b00 cmp r3, #0 8015e38: d00b beq.n 8015e52 __asm volatile 8015e3a: f04f 0350 mov.w r3, #80 @ 0x50 8015e3e: f383 8811 msr BASEPRI, r3 8015e42: f3bf 8f6f isb sy 8015e46: f3bf 8f4f dsb sy 8015e4a: 617b str r3, [r7, #20] } 8015e4c: bf00 nop 8015e4e: bf00 nop 8015e50: e7fd b.n 8015e4e pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) 8015e52: 68bb ldr r3, [r7, #8] 8015e54: 2b00 cmp r3, #0 8015e56: d01f beq.n 8015e98 { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015e58: 2300 movs r3, #0 8015e5a: 61fb str r3, [r7, #28] 8015e5c: e012 b.n 8015e84 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; 8015e5e: 68ba ldr r2, [r7, #8] 8015e60: 69fb ldr r3, [r7, #28] 8015e62: 4413 add r3, r2 8015e64: 7819 ldrb r1, [r3, #0] 8015e66: 6b3a ldr r2, [r7, #48] @ 0x30 8015e68: 69fb ldr r3, [r7, #28] 8015e6a: 4413 add r3, r2 8015e6c: 3334 adds r3, #52 @ 0x34 8015e6e: 460a mov r2, r1 8015e70: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) 8015e72: 68ba ldr r2, [r7, #8] 8015e74: 69fb ldr r3, [r7, #28] 8015e76: 4413 add r3, r2 8015e78: 781b ldrb r3, [r3, #0] 8015e7a: 2b00 cmp r3, #0 8015e7c: d006 beq.n 8015e8c for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) 8015e7e: 69fb ldr r3, [r7, #28] 8015e80: 3301 adds r3, #1 8015e82: 61fb str r3, [r7, #28] 8015e84: 69fb ldr r3, [r7, #28] 8015e86: 2b0f cmp r3, #15 8015e88: d9e9 bls.n 8015e5e 8015e8a: e000 b.n 8015e8e { break; 8015e8c: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; 8015e8e: 6b3b ldr r3, [r7, #48] @ 0x30 8015e90: 2200 movs r2, #0 8015e92: f883 2043 strb.w r2, [r3, #67] @ 0x43 8015e96: e003 b.n 8015ea0 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; 8015e98: 6b3b ldr r3, [r7, #48] @ 0x30 8015e9a: 2200 movs r2, #0 8015e9c: f883 2034 strb.w r2, [r3, #52] @ 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) 8015ea0: 6abb ldr r3, [r7, #40] @ 0x28 8015ea2: 2b37 cmp r3, #55 @ 0x37 8015ea4: d901 bls.n 8015eaa { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; 8015ea6: 2337 movs r3, #55 @ 0x37 8015ea8: 62bb str r3, [r7, #40] @ 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; 8015eaa: 6b3b ldr r3, [r7, #48] @ 0x30 8015eac: 6aba ldr r2, [r7, #40] @ 0x28 8015eae: 62da str r2, [r3, #44] @ 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; 8015eb0: 6b3b ldr r3, [r7, #48] @ 0x30 8015eb2: 6aba ldr r2, [r7, #40] @ 0x28 8015eb4: 64da str r2, [r3, #76] @ 0x4c pxNewTCB->uxMutexesHeld = 0; 8015eb6: 6b3b ldr r3, [r7, #48] @ 0x30 8015eb8: 2200 movs r2, #0 8015eba: 651a str r2, [r3, #80] @ 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); 8015ebc: 6b3b ldr r3, [r7, #48] @ 0x30 8015ebe: 3304 adds r3, #4 8015ec0: 4618 mov r0, r3 8015ec2: f7fe fd09 bl 80148d8 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); 8015ec6: 6b3b ldr r3, [r7, #48] @ 0x30 8015ec8: 3318 adds r3, #24 8015eca: 4618 mov r0, r3 8015ecc: f7fe fd04 bl 80148d8 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); 8015ed0: 6b3b ldr r3, [r7, #48] @ 0x30 8015ed2: 6b3a ldr r2, [r7, #48] @ 0x30 8015ed4: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8015ed6: 6abb ldr r3, [r7, #40] @ 0x28 8015ed8: f1c3 0238 rsb r2, r3, #56 @ 0x38 8015edc: 6b3b ldr r3, [r7, #48] @ 0x30 8015ede: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); 8015ee0: 6b3b ldr r3, [r7, #48] @ 0x30 8015ee2: 6b3a ldr r2, [r7, #48] @ 0x30 8015ee4: 625a str r2, [r3, #36] @ 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; 8015ee6: 6b3b ldr r3, [r7, #48] @ 0x30 8015ee8: 2200 movs r2, #0 8015eea: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8015eee: 6b3b ldr r3, [r7, #48] @ 0x30 8015ef0: 2200 movs r2, #0 8015ef2: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); 8015ef6: 6b3b ldr r3, [r7, #48] @ 0x30 8015ef8: 3354 adds r3, #84 @ 0x54 8015efa: 224c movs r2, #76 @ 0x4c 8015efc: 2100 movs r1, #0 8015efe: 4618 mov r0, r3 8015f00: f002 fa0a bl 8018318 8015f04: 6b3b ldr r3, [r7, #48] @ 0x30 8015f06: 4a0d ldr r2, [pc, #52] @ (8015f3c ) 8015f08: 659a str r2, [r3, #88] @ 0x58 8015f0a: 6b3b ldr r3, [r7, #48] @ 0x30 8015f0c: 4a0c ldr r2, [pc, #48] @ (8015f40 ) 8015f0e: 65da str r2, [r3, #92] @ 0x5c 8015f10: 6b3b ldr r3, [r7, #48] @ 0x30 8015f12: 4a0c ldr r2, [pc, #48] @ (8015f44 ) 8015f14: 661a str r2, [r3, #96] @ 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); 8015f16: 683a ldr r2, [r7, #0] 8015f18: 68f9 ldr r1, [r7, #12] 8015f1a: 69b8 ldr r0, [r7, #24] 8015f1c: f001 fdb8 bl 8017a90 8015f20: 4602 mov r2, r0 8015f22: 6b3b ldr r3, [r7, #48] @ 0x30 8015f24: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) 8015f26: 6afb ldr r3, [r7, #44] @ 0x2c 8015f28: 2b00 cmp r3, #0 8015f2a: d002 beq.n 8015f32 { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; 8015f2c: 6afb ldr r3, [r7, #44] @ 0x2c 8015f2e: 6b3a ldr r2, [r7, #48] @ 0x30 8015f30: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8015f32: bf00 nop 8015f34: 3720 adds r7, #32 8015f36: 46bd mov sp, r7 8015f38: bd80 pop {r7, pc} 8015f3a: bf00 nop 8015f3c: 2401304c .word 0x2401304c 8015f40: 240130b4 .word 0x240130b4 8015f44: 2401311c .word 0x2401311c 08015f48 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { 8015f48: b580 push {r7, lr} 8015f4a: b082 sub sp, #8 8015f4c: af00 add r7, sp, #0 8015f4e: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); 8015f50: f001 fed2 bl 8017cf8 { uxCurrentNumberOfTasks++; 8015f54: 4b2d ldr r3, [pc, #180] @ (801600c ) 8015f56: 681b ldr r3, [r3, #0] 8015f58: 3301 adds r3, #1 8015f5a: 4a2c ldr r2, [pc, #176] @ (801600c ) 8015f5c: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) 8015f5e: 4b2c ldr r3, [pc, #176] @ (8016010 ) 8015f60: 681b ldr r3, [r3, #0] 8015f62: 2b00 cmp r3, #0 8015f64: d109 bne.n 8015f7a { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; 8015f66: 4a2a ldr r2, [pc, #168] @ (8016010 ) 8015f68: 687b ldr r3, [r7, #4] 8015f6a: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) 8015f6c: 4b27 ldr r3, [pc, #156] @ (801600c ) 8015f6e: 681b ldr r3, [r3, #0] 8015f70: 2b01 cmp r3, #1 8015f72: d110 bne.n 8015f96 { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); 8015f74: f000 fc64 bl 8016840 8015f78: e00d b.n 8015f96 else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) 8015f7a: 4b26 ldr r3, [pc, #152] @ (8016014 ) 8015f7c: 681b ldr r3, [r3, #0] 8015f7e: 2b00 cmp r3, #0 8015f80: d109 bne.n 8015f96 { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) 8015f82: 4b23 ldr r3, [pc, #140] @ (8016010 ) 8015f84: 681b ldr r3, [r3, #0] 8015f86: 6ada ldr r2, [r3, #44] @ 0x2c 8015f88: 687b ldr r3, [r7, #4] 8015f8a: 6adb ldr r3, [r3, #44] @ 0x2c 8015f8c: 429a cmp r2, r3 8015f8e: d802 bhi.n 8015f96 { pxCurrentTCB = pxNewTCB; 8015f90: 4a1f ldr r2, [pc, #124] @ (8016010 ) 8015f92: 687b ldr r3, [r7, #4] 8015f94: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; 8015f96: 4b20 ldr r3, [pc, #128] @ (8016018 ) 8015f98: 681b ldr r3, [r3, #0] 8015f9a: 3301 adds r3, #1 8015f9c: 4a1e ldr r2, [pc, #120] @ (8016018 ) 8015f9e: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; 8015fa0: 4b1d ldr r3, [pc, #116] @ (8016018 ) 8015fa2: 681a ldr r2, [r3, #0] 8015fa4: 687b ldr r3, [r7, #4] 8015fa6: 645a str r2, [r3, #68] @ 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); 8015fa8: 687b ldr r3, [r7, #4] 8015faa: 6ada ldr r2, [r3, #44] @ 0x2c 8015fac: 4b1b ldr r3, [pc, #108] @ (801601c ) 8015fae: 681b ldr r3, [r3, #0] 8015fb0: 429a cmp r2, r3 8015fb2: d903 bls.n 8015fbc 8015fb4: 687b ldr r3, [r7, #4] 8015fb6: 6adb ldr r3, [r3, #44] @ 0x2c 8015fb8: 4a18 ldr r2, [pc, #96] @ (801601c ) 8015fba: 6013 str r3, [r2, #0] 8015fbc: 687b ldr r3, [r7, #4] 8015fbe: 6ada ldr r2, [r3, #44] @ 0x2c 8015fc0: 4613 mov r3, r2 8015fc2: 009b lsls r3, r3, #2 8015fc4: 4413 add r3, r2 8015fc6: 009b lsls r3, r3, #2 8015fc8: 4a15 ldr r2, [pc, #84] @ (8016020 ) 8015fca: 441a add r2, r3 8015fcc: 687b ldr r3, [r7, #4] 8015fce: 3304 adds r3, #4 8015fd0: 4619 mov r1, r3 8015fd2: 4610 mov r0, r2 8015fd4: f7fe fc8d bl 80148f2 portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); 8015fd8: f001 fec0 bl 8017d5c if( xSchedulerRunning != pdFALSE ) 8015fdc: 4b0d ldr r3, [pc, #52] @ (8016014 ) 8015fde: 681b ldr r3, [r3, #0] 8015fe0: 2b00 cmp r3, #0 8015fe2: d00e beq.n 8016002 { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) 8015fe4: 4b0a ldr r3, [pc, #40] @ (8016010 ) 8015fe6: 681b ldr r3, [r3, #0] 8015fe8: 6ada ldr r2, [r3, #44] @ 0x2c 8015fea: 687b ldr r3, [r7, #4] 8015fec: 6adb ldr r3, [r3, #44] @ 0x2c 8015fee: 429a cmp r2, r3 8015ff0: d207 bcs.n 8016002 { taskYIELD_IF_USING_PREEMPTION(); 8015ff2: 4b0c ldr r3, [pc, #48] @ (8016024 ) 8015ff4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8015ff8: 601a str r2, [r3, #0] 8015ffa: f3bf 8f4f dsb sy 8015ffe: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8016002: bf00 nop 8016004: 3708 adds r7, #8 8016006: 46bd mov sp, r7 8016008: bd80 pop {r7, pc} 801600a: bf00 nop 801600c: 24002ecc .word 0x24002ecc 8016010: 240029f8 .word 0x240029f8 8016014: 24002ed8 .word 0x24002ed8 8016018: 24002ee8 .word 0x24002ee8 801601c: 24002ed4 .word 0x24002ed4 8016020: 240029fc .word 0x240029fc 8016024: e000ed04 .word 0xe000ed04 08016028 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { 8016028: b580 push {r7, lr} 801602a: b084 sub sp, #16 801602c: af00 add r7, sp, #0 801602e: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; 8016030: 2300 movs r3, #0 8016032: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) 8016034: 687b ldr r3, [r7, #4] 8016036: 2b00 cmp r3, #0 8016038: d018 beq.n 801606c { configASSERT( uxSchedulerSuspended == 0 ); 801603a: 4b14 ldr r3, [pc, #80] @ (801608c ) 801603c: 681b ldr r3, [r3, #0] 801603e: 2b00 cmp r3, #0 8016040: d00b beq.n 801605a __asm volatile 8016042: f04f 0350 mov.w r3, #80 @ 0x50 8016046: f383 8811 msr BASEPRI, r3 801604a: f3bf 8f6f isb sy 801604e: f3bf 8f4f dsb sy 8016052: 60bb str r3, [r7, #8] } 8016054: bf00 nop 8016056: bf00 nop 8016058: e7fd b.n 8016056 vTaskSuspendAll(); 801605a: f000 f88b bl 8016174 list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); 801605e: 2100 movs r1, #0 8016060: 6878 ldr r0, [r7, #4] 8016062: f001 f87d bl 8017160 } xAlreadyYielded = xTaskResumeAll(); 8016066: f000 f893 bl 8016190 801606a: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) 801606c: 68fb ldr r3, [r7, #12] 801606e: 2b00 cmp r3, #0 8016070: d107 bne.n 8016082 { portYIELD_WITHIN_API(); 8016072: 4b07 ldr r3, [pc, #28] @ (8016090 ) 8016074: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016078: 601a str r2, [r3, #0] 801607a: f3bf 8f4f dsb sy 801607e: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } 8016082: bf00 nop 8016084: 3710 adds r7, #16 8016086: 46bd mov sp, r7 8016088: bd80 pop {r7, pc} 801608a: bf00 nop 801608c: 24002ef4 .word 0x24002ef4 8016090: e000ed04 .word 0xe000ed04 08016094 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { 8016094: b580 push {r7, lr} 8016096: b08a sub sp, #40 @ 0x28 8016098: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; 801609a: 2300 movs r3, #0 801609c: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; 801609e: 2300 movs r3, #0 80160a0: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); 80160a2: 463a mov r2, r7 80160a4: 1d39 adds r1, r7, #4 80160a6: f107 0308 add.w r3, r7, #8 80160aa: 4618 mov r0, r3 80160ac: f7fe fbc0 bl 8014830 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, 80160b0: 6839 ldr r1, [r7, #0] 80160b2: 687b ldr r3, [r7, #4] 80160b4: 68ba ldr r2, [r7, #8] 80160b6: 9202 str r2, [sp, #8] 80160b8: 9301 str r3, [sp, #4] 80160ba: 2300 movs r3, #0 80160bc: 9300 str r3, [sp, #0] 80160be: 2300 movs r3, #0 80160c0: 460a mov r2, r1 80160c2: 4924 ldr r1, [pc, #144] @ (8016154 ) 80160c4: 4824 ldr r0, [pc, #144] @ (8016158 ) 80160c6: f7ff fdf2 bl 8015cae 80160ca: 4603 mov r3, r0 80160cc: 4a23 ldr r2, [pc, #140] @ (801615c ) 80160ce: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) 80160d0: 4b22 ldr r3, [pc, #136] @ (801615c ) 80160d2: 681b ldr r3, [r3, #0] 80160d4: 2b00 cmp r3, #0 80160d6: d002 beq.n 80160de { xReturn = pdPASS; 80160d8: 2301 movs r3, #1 80160da: 617b str r3, [r7, #20] 80160dc: e001 b.n 80160e2 } else { xReturn = pdFAIL; 80160de: 2300 movs r3, #0 80160e0: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) 80160e2: 697b ldr r3, [r7, #20] 80160e4: 2b01 cmp r3, #1 80160e6: d102 bne.n 80160ee { xReturn = xTimerCreateTimerTask(); 80160e8: f001 f88e bl 8017208 80160ec: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) 80160ee: 697b ldr r3, [r7, #20] 80160f0: 2b01 cmp r3, #1 80160f2: d11b bne.n 801612c __asm volatile 80160f4: f04f 0350 mov.w r3, #80 @ 0x50 80160f8: f383 8811 msr BASEPRI, r3 80160fc: f3bf 8f6f isb sy 8016100: f3bf 8f4f dsb sy 8016104: 613b str r3, [r7, #16] } 8016106: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 8016108: 4b15 ldr r3, [pc, #84] @ (8016160 ) 801610a: 681b ldr r3, [r3, #0] 801610c: 3354 adds r3, #84 @ 0x54 801610e: 4a15 ldr r2, [pc, #84] @ (8016164 ) 8016110: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; 8016112: 4b15 ldr r3, [pc, #84] @ (8016168 ) 8016114: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016118: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; 801611a: 4b14 ldr r3, [pc, #80] @ (801616c ) 801611c: 2201 movs r2, #1 801611e: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; 8016120: 4b13 ldr r3, [pc, #76] @ (8016170 ) 8016122: 2200 movs r2, #0 8016124: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) 8016126: f001 fd43 bl 8017bb0 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } 801612a: e00f b.n 801614c configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); 801612c: 697b ldr r3, [r7, #20] 801612e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016132: d10b bne.n 801614c __asm volatile 8016134: f04f 0350 mov.w r3, #80 @ 0x50 8016138: f383 8811 msr BASEPRI, r3 801613c: f3bf 8f6f isb sy 8016140: f3bf 8f4f dsb sy 8016144: 60fb str r3, [r7, #12] } 8016146: bf00 nop 8016148: bf00 nop 801614a: e7fd b.n 8016148 } 801614c: bf00 nop 801614e: 3718 adds r7, #24 8016150: 46bd mov sp, r7 8016152: bd80 pop {r7, pc} 8016154: 08018690 .word 0x08018690 8016158: 08016811 .word 0x08016811 801615c: 24002ef0 .word 0x24002ef0 8016160: 240029f8 .word 0x240029f8 8016164: 24000048 .word 0x24000048 8016168: 24002eec .word 0x24002eec 801616c: 24002ed8 .word 0x24002ed8 8016170: 24002ed0 .word 0x24002ed0 08016174 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 8016174: b480 push {r7} 8016176: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8016178: 4b04 ldr r3, [pc, #16] @ (801618c ) 801617a: 681b ldr r3, [r3, #0] 801617c: 3301 adds r3, #1 801617e: 4a03 ldr r2, [pc, #12] @ (801618c ) 8016180: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 8016182: bf00 nop 8016184: 46bd mov sp, r7 8016186: f85d 7b04 ldr.w r7, [sp], #4 801618a: 4770 bx lr 801618c: 24002ef4 .word 0x24002ef4 08016190 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 8016190: b580 push {r7, lr} 8016192: b084 sub sp, #16 8016194: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 8016196: 2300 movs r3, #0 8016198: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 801619a: 2300 movs r3, #0 801619c: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 801619e: 4b42 ldr r3, [pc, #264] @ (80162a8 ) 80161a0: 681b ldr r3, [r3, #0] 80161a2: 2b00 cmp r3, #0 80161a4: d10b bne.n 80161be __asm volatile 80161a6: f04f 0350 mov.w r3, #80 @ 0x50 80161aa: f383 8811 msr BASEPRI, r3 80161ae: f3bf 8f6f isb sy 80161b2: f3bf 8f4f dsb sy 80161b6: 603b str r3, [r7, #0] } 80161b8: bf00 nop 80161ba: bf00 nop 80161bc: e7fd b.n 80161ba /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 80161be: f001 fd9b bl 8017cf8 { --uxSchedulerSuspended; 80161c2: 4b39 ldr r3, [pc, #228] @ (80162a8 ) 80161c4: 681b ldr r3, [r3, #0] 80161c6: 3b01 subs r3, #1 80161c8: 4a37 ldr r2, [pc, #220] @ (80162a8 ) 80161ca: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80161cc: 4b36 ldr r3, [pc, #216] @ (80162a8 ) 80161ce: 681b ldr r3, [r3, #0] 80161d0: 2b00 cmp r3, #0 80161d2: d162 bne.n 801629a { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80161d4: 4b35 ldr r3, [pc, #212] @ (80162ac ) 80161d6: 681b ldr r3, [r3, #0] 80161d8: 2b00 cmp r3, #0 80161da: d05e beq.n 801629a { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80161dc: e02f b.n 801623e { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80161de: 4b34 ldr r3, [pc, #208] @ (80162b0 ) 80161e0: 68db ldr r3, [r3, #12] 80161e2: 68db ldr r3, [r3, #12] 80161e4: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80161e6: 68fb ldr r3, [r7, #12] 80161e8: 3318 adds r3, #24 80161ea: 4618 mov r0, r3 80161ec: f7fe fbde bl 80149ac ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80161f0: 68fb ldr r3, [r7, #12] 80161f2: 3304 adds r3, #4 80161f4: 4618 mov r0, r3 80161f6: f7fe fbd9 bl 80149ac prvAddTaskToReadyList( pxTCB ); 80161fa: 68fb ldr r3, [r7, #12] 80161fc: 6ada ldr r2, [r3, #44] @ 0x2c 80161fe: 4b2d ldr r3, [pc, #180] @ (80162b4 ) 8016200: 681b ldr r3, [r3, #0] 8016202: 429a cmp r2, r3 8016204: d903 bls.n 801620e 8016206: 68fb ldr r3, [r7, #12] 8016208: 6adb ldr r3, [r3, #44] @ 0x2c 801620a: 4a2a ldr r2, [pc, #168] @ (80162b4 ) 801620c: 6013 str r3, [r2, #0] 801620e: 68fb ldr r3, [r7, #12] 8016210: 6ada ldr r2, [r3, #44] @ 0x2c 8016212: 4613 mov r3, r2 8016214: 009b lsls r3, r3, #2 8016216: 4413 add r3, r2 8016218: 009b lsls r3, r3, #2 801621a: 4a27 ldr r2, [pc, #156] @ (80162b8 ) 801621c: 441a add r2, r3 801621e: 68fb ldr r3, [r7, #12] 8016220: 3304 adds r3, #4 8016222: 4619 mov r1, r3 8016224: 4610 mov r0, r2 8016226: f7fe fb64 bl 80148f2 /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 801622a: 68fb ldr r3, [r7, #12] 801622c: 6ada ldr r2, [r3, #44] @ 0x2c 801622e: 4b23 ldr r3, [pc, #140] @ (80162bc ) 8016230: 681b ldr r3, [r3, #0] 8016232: 6adb ldr r3, [r3, #44] @ 0x2c 8016234: 429a cmp r2, r3 8016236: d302 bcc.n 801623e { xYieldPending = pdTRUE; 8016238: 4b21 ldr r3, [pc, #132] @ (80162c0 ) 801623a: 2201 movs r2, #1 801623c: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 801623e: 4b1c ldr r3, [pc, #112] @ (80162b0 ) 8016240: 681b ldr r3, [r3, #0] 8016242: 2b00 cmp r3, #0 8016244: d1cb bne.n 80161de { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 8016246: 68fb ldr r3, [r7, #12] 8016248: 2b00 cmp r3, #0 801624a: d001 beq.n 8016250 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 801624c: f000 fb9c bl 8016988 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8016250: 4b1c ldr r3, [pc, #112] @ (80162c4 ) 8016252: 681b ldr r3, [r3, #0] 8016254: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 8016256: 687b ldr r3, [r7, #4] 8016258: 2b00 cmp r3, #0 801625a: d010 beq.n 801627e { do { if( xTaskIncrementTick() != pdFALSE ) 801625c: f000 f846 bl 80162ec 8016260: 4603 mov r3, r0 8016262: 2b00 cmp r3, #0 8016264: d002 beq.n 801626c { xYieldPending = pdTRUE; 8016266: 4b16 ldr r3, [pc, #88] @ (80162c0 ) 8016268: 2201 movs r2, #1 801626a: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 801626c: 687b ldr r3, [r7, #4] 801626e: 3b01 subs r3, #1 8016270: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 8016272: 687b ldr r3, [r7, #4] 8016274: 2b00 cmp r3, #0 8016276: d1f1 bne.n 801625c xPendedTicks = 0; 8016278: 4b12 ldr r3, [pc, #72] @ (80162c4 ) 801627a: 2200 movs r2, #0 801627c: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 801627e: 4b10 ldr r3, [pc, #64] @ (80162c0 ) 8016280: 681b ldr r3, [r3, #0] 8016282: 2b00 cmp r3, #0 8016284: d009 beq.n 801629a { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 8016286: 2301 movs r3, #1 8016288: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 801628a: 4b0f ldr r3, [pc, #60] @ (80162c8 ) 801628c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016290: 601a str r2, [r3, #0] 8016292: f3bf 8f4f dsb sy 8016296: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 801629a: f001 fd5f bl 8017d5c return xAlreadyYielded; 801629e: 68bb ldr r3, [r7, #8] } 80162a0: 4618 mov r0, r3 80162a2: 3710 adds r7, #16 80162a4: 46bd mov sp, r7 80162a6: bd80 pop {r7, pc} 80162a8: 24002ef4 .word 0x24002ef4 80162ac: 24002ecc .word 0x24002ecc 80162b0: 24002e8c .word 0x24002e8c 80162b4: 24002ed4 .word 0x24002ed4 80162b8: 240029fc .word 0x240029fc 80162bc: 240029f8 .word 0x240029f8 80162c0: 24002ee0 .word 0x24002ee0 80162c4: 24002edc .word 0x24002edc 80162c8: e000ed04 .word 0xe000ed04 080162cc : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { 80162cc: b480 push {r7} 80162ce: b083 sub sp, #12 80162d0: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; 80162d2: 4b05 ldr r3, [pc, #20] @ (80162e8 ) 80162d4: 681b ldr r3, [r3, #0] 80162d6: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; 80162d8: 687b ldr r3, [r7, #4] } 80162da: 4618 mov r0, r3 80162dc: 370c adds r7, #12 80162de: 46bd mov sp, r7 80162e0: f85d 7b04 ldr.w r7, [sp], #4 80162e4: 4770 bx lr 80162e6: bf00 nop 80162e8: 24002ed0 .word 0x24002ed0 080162ec : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 80162ec: b580 push {r7, lr} 80162ee: b086 sub sp, #24 80162f0: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 80162f2: 2300 movs r3, #0 80162f4: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80162f6: 4b4f ldr r3, [pc, #316] @ (8016434 ) 80162f8: 681b ldr r3, [r3, #0] 80162fa: 2b00 cmp r3, #0 80162fc: f040 8090 bne.w 8016420 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 8016300: 4b4d ldr r3, [pc, #308] @ (8016438 ) 8016302: 681b ldr r3, [r3, #0] 8016304: 3301 adds r3, #1 8016306: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8016308: 4a4b ldr r2, [pc, #300] @ (8016438 ) 801630a: 693b ldr r3, [r7, #16] 801630c: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 801630e: 693b ldr r3, [r7, #16] 8016310: 2b00 cmp r3, #0 8016312: d121 bne.n 8016358 { taskSWITCH_DELAYED_LISTS(); 8016314: 4b49 ldr r3, [pc, #292] @ (801643c ) 8016316: 681b ldr r3, [r3, #0] 8016318: 681b ldr r3, [r3, #0] 801631a: 2b00 cmp r3, #0 801631c: d00b beq.n 8016336 __asm volatile 801631e: f04f 0350 mov.w r3, #80 @ 0x50 8016322: f383 8811 msr BASEPRI, r3 8016326: f3bf 8f6f isb sy 801632a: f3bf 8f4f dsb sy 801632e: 603b str r3, [r7, #0] } 8016330: bf00 nop 8016332: bf00 nop 8016334: e7fd b.n 8016332 8016336: 4b41 ldr r3, [pc, #260] @ (801643c ) 8016338: 681b ldr r3, [r3, #0] 801633a: 60fb str r3, [r7, #12] 801633c: 4b40 ldr r3, [pc, #256] @ (8016440 ) 801633e: 681b ldr r3, [r3, #0] 8016340: 4a3e ldr r2, [pc, #248] @ (801643c ) 8016342: 6013 str r3, [r2, #0] 8016344: 4a3e ldr r2, [pc, #248] @ (8016440 ) 8016346: 68fb ldr r3, [r7, #12] 8016348: 6013 str r3, [r2, #0] 801634a: 4b3e ldr r3, [pc, #248] @ (8016444 ) 801634c: 681b ldr r3, [r3, #0] 801634e: 3301 adds r3, #1 8016350: 4a3c ldr r2, [pc, #240] @ (8016444 ) 8016352: 6013 str r3, [r2, #0] 8016354: f000 fb18 bl 8016988 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 8016358: 4b3b ldr r3, [pc, #236] @ (8016448 ) 801635a: 681b ldr r3, [r3, #0] 801635c: 693a ldr r2, [r7, #16] 801635e: 429a cmp r2, r3 8016360: d349 bcc.n 80163f6 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8016362: 4b36 ldr r3, [pc, #216] @ (801643c ) 8016364: 681b ldr r3, [r3, #0] 8016366: 681b ldr r3, [r3, #0] 8016368: 2b00 cmp r3, #0 801636a: d104 bne.n 8016376 /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 801636c: 4b36 ldr r3, [pc, #216] @ (8016448 ) 801636e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8016372: 601a str r2, [r3, #0] break; 8016374: e03f b.n 80163f6 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8016376: 4b31 ldr r3, [pc, #196] @ (801643c ) 8016378: 681b ldr r3, [r3, #0] 801637a: 68db ldr r3, [r3, #12] 801637c: 68db ldr r3, [r3, #12] 801637e: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8016380: 68bb ldr r3, [r7, #8] 8016382: 685b ldr r3, [r3, #4] 8016384: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 8016386: 693a ldr r2, [r7, #16] 8016388: 687b ldr r3, [r7, #4] 801638a: 429a cmp r2, r3 801638c: d203 bcs.n 8016396 /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 801638e: 4a2e ldr r2, [pc, #184] @ (8016448 ) 8016390: 687b ldr r3, [r7, #4] 8016392: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 8016394: e02f b.n 80163f6 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016396: 68bb ldr r3, [r7, #8] 8016398: 3304 adds r3, #4 801639a: 4618 mov r0, r3 801639c: f7fe fb06 bl 80149ac /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 80163a0: 68bb ldr r3, [r7, #8] 80163a2: 6a9b ldr r3, [r3, #40] @ 0x28 80163a4: 2b00 cmp r3, #0 80163a6: d004 beq.n 80163b2 { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80163a8: 68bb ldr r3, [r7, #8] 80163aa: 3318 adds r3, #24 80163ac: 4618 mov r0, r3 80163ae: f7fe fafd bl 80149ac mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 80163b2: 68bb ldr r3, [r7, #8] 80163b4: 6ada ldr r2, [r3, #44] @ 0x2c 80163b6: 4b25 ldr r3, [pc, #148] @ (801644c ) 80163b8: 681b ldr r3, [r3, #0] 80163ba: 429a cmp r2, r3 80163bc: d903 bls.n 80163c6 80163be: 68bb ldr r3, [r7, #8] 80163c0: 6adb ldr r3, [r3, #44] @ 0x2c 80163c2: 4a22 ldr r2, [pc, #136] @ (801644c ) 80163c4: 6013 str r3, [r2, #0] 80163c6: 68bb ldr r3, [r7, #8] 80163c8: 6ada ldr r2, [r3, #44] @ 0x2c 80163ca: 4613 mov r3, r2 80163cc: 009b lsls r3, r3, #2 80163ce: 4413 add r3, r2 80163d0: 009b lsls r3, r3, #2 80163d2: 4a1f ldr r2, [pc, #124] @ (8016450 ) 80163d4: 441a add r2, r3 80163d6: 68bb ldr r3, [r7, #8] 80163d8: 3304 adds r3, #4 80163da: 4619 mov r1, r3 80163dc: 4610 mov r0, r2 80163de: f7fe fa88 bl 80148f2 { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80163e2: 68bb ldr r3, [r7, #8] 80163e4: 6ada ldr r2, [r3, #44] @ 0x2c 80163e6: 4b1b ldr r3, [pc, #108] @ (8016454 ) 80163e8: 681b ldr r3, [r3, #0] 80163ea: 6adb ldr r3, [r3, #44] @ 0x2c 80163ec: 429a cmp r2, r3 80163ee: d3b8 bcc.n 8016362 { xSwitchRequired = pdTRUE; 80163f0: 2301 movs r3, #1 80163f2: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80163f4: e7b5 b.n 8016362 /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 80163f6: 4b17 ldr r3, [pc, #92] @ (8016454 ) 80163f8: 681b ldr r3, [r3, #0] 80163fa: 6ada ldr r2, [r3, #44] @ 0x2c 80163fc: 4914 ldr r1, [pc, #80] @ (8016450 ) 80163fe: 4613 mov r3, r2 8016400: 009b lsls r3, r3, #2 8016402: 4413 add r3, r2 8016404: 009b lsls r3, r3, #2 8016406: 440b add r3, r1 8016408: 681b ldr r3, [r3, #0] 801640a: 2b01 cmp r3, #1 801640c: d901 bls.n 8016412 { xSwitchRequired = pdTRUE; 801640e: 2301 movs r3, #1 8016410: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 8016412: 4b11 ldr r3, [pc, #68] @ (8016458 ) 8016414: 681b ldr r3, [r3, #0] 8016416: 2b00 cmp r3, #0 8016418: d007 beq.n 801642a { xSwitchRequired = pdTRUE; 801641a: 2301 movs r3, #1 801641c: 617b str r3, [r7, #20] 801641e: e004 b.n 801642a } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 8016420: 4b0e ldr r3, [pc, #56] @ (801645c ) 8016422: 681b ldr r3, [r3, #0] 8016424: 3301 adds r3, #1 8016426: 4a0d ldr r2, [pc, #52] @ (801645c ) 8016428: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 801642a: 697b ldr r3, [r7, #20] } 801642c: 4618 mov r0, r3 801642e: 3718 adds r7, #24 8016430: 46bd mov sp, r7 8016432: bd80 pop {r7, pc} 8016434: 24002ef4 .word 0x24002ef4 8016438: 24002ed0 .word 0x24002ed0 801643c: 24002e84 .word 0x24002e84 8016440: 24002e88 .word 0x24002e88 8016444: 24002ee4 .word 0x24002ee4 8016448: 24002eec .word 0x24002eec 801644c: 24002ed4 .word 0x24002ed4 8016450: 240029fc .word 0x240029fc 8016454: 240029f8 .word 0x240029f8 8016458: 24002ee0 .word 0x24002ee0 801645c: 24002edc .word 0x24002edc 08016460 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 8016460: b580 push {r7, lr} 8016462: b084 sub sp, #16 8016464: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 8016466: 4b32 ldr r3, [pc, #200] @ (8016530 ) 8016468: 681b ldr r3, [r3, #0] 801646a: 2b00 cmp r3, #0 801646c: d003 beq.n 8016476 { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 801646e: 4b31 ldr r3, [pc, #196] @ (8016534 ) 8016470: 2201 movs r2, #1 8016472: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 8016474: e058 b.n 8016528 xYieldPending = pdFALSE; 8016476: 4b2f ldr r3, [pc, #188] @ (8016534 ) 8016478: 2200 movs r2, #0 801647a: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 801647c: 4b2e ldr r3, [pc, #184] @ (8016538 ) 801647e: 681b ldr r3, [r3, #0] 8016480: 681a ldr r2, [r3, #0] 8016482: 4b2d ldr r3, [pc, #180] @ (8016538 ) 8016484: 681b ldr r3, [r3, #0] 8016486: 6b1b ldr r3, [r3, #48] @ 0x30 8016488: 429a cmp r2, r3 801648a: d808 bhi.n 801649e 801648c: 4b2a ldr r3, [pc, #168] @ (8016538 ) 801648e: 681a ldr r2, [r3, #0] 8016490: 4b29 ldr r3, [pc, #164] @ (8016538 ) 8016492: 681b ldr r3, [r3, #0] 8016494: 3334 adds r3, #52 @ 0x34 8016496: 4619 mov r1, r3 8016498: 4610 mov r0, r2 801649a: f7ea f899 bl 80005d0 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801649e: 4b27 ldr r3, [pc, #156] @ (801653c ) 80164a0: 681b ldr r3, [r3, #0] 80164a2: 60fb str r3, [r7, #12] 80164a4: e011 b.n 80164ca 80164a6: 68fb ldr r3, [r7, #12] 80164a8: 2b00 cmp r3, #0 80164aa: d10b bne.n 80164c4 __asm volatile 80164ac: f04f 0350 mov.w r3, #80 @ 0x50 80164b0: f383 8811 msr BASEPRI, r3 80164b4: f3bf 8f6f isb sy 80164b8: f3bf 8f4f dsb sy 80164bc: 607b str r3, [r7, #4] } 80164be: bf00 nop 80164c0: bf00 nop 80164c2: e7fd b.n 80164c0 80164c4: 68fb ldr r3, [r7, #12] 80164c6: 3b01 subs r3, #1 80164c8: 60fb str r3, [r7, #12] 80164ca: 491d ldr r1, [pc, #116] @ (8016540 ) 80164cc: 68fa ldr r2, [r7, #12] 80164ce: 4613 mov r3, r2 80164d0: 009b lsls r3, r3, #2 80164d2: 4413 add r3, r2 80164d4: 009b lsls r3, r3, #2 80164d6: 440b add r3, r1 80164d8: 681b ldr r3, [r3, #0] 80164da: 2b00 cmp r3, #0 80164dc: d0e3 beq.n 80164a6 80164de: 68fa ldr r2, [r7, #12] 80164e0: 4613 mov r3, r2 80164e2: 009b lsls r3, r3, #2 80164e4: 4413 add r3, r2 80164e6: 009b lsls r3, r3, #2 80164e8: 4a15 ldr r2, [pc, #84] @ (8016540 ) 80164ea: 4413 add r3, r2 80164ec: 60bb str r3, [r7, #8] 80164ee: 68bb ldr r3, [r7, #8] 80164f0: 685b ldr r3, [r3, #4] 80164f2: 685a ldr r2, [r3, #4] 80164f4: 68bb ldr r3, [r7, #8] 80164f6: 605a str r2, [r3, #4] 80164f8: 68bb ldr r3, [r7, #8] 80164fa: 685a ldr r2, [r3, #4] 80164fc: 68bb ldr r3, [r7, #8] 80164fe: 3308 adds r3, #8 8016500: 429a cmp r2, r3 8016502: d104 bne.n 801650e 8016504: 68bb ldr r3, [r7, #8] 8016506: 685b ldr r3, [r3, #4] 8016508: 685a ldr r2, [r3, #4] 801650a: 68bb ldr r3, [r7, #8] 801650c: 605a str r2, [r3, #4] 801650e: 68bb ldr r3, [r7, #8] 8016510: 685b ldr r3, [r3, #4] 8016512: 68db ldr r3, [r3, #12] 8016514: 4a08 ldr r2, [pc, #32] @ (8016538 ) 8016516: 6013 str r3, [r2, #0] 8016518: 4a08 ldr r2, [pc, #32] @ (801653c ) 801651a: 68fb ldr r3, [r7, #12] 801651c: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); 801651e: 4b06 ldr r3, [pc, #24] @ (8016538 ) 8016520: 681b ldr r3, [r3, #0] 8016522: 3354 adds r3, #84 @ 0x54 8016524: 4a07 ldr r2, [pc, #28] @ (8016544 ) 8016526: 6013 str r3, [r2, #0] } 8016528: bf00 nop 801652a: 3710 adds r7, #16 801652c: 46bd mov sp, r7 801652e: bd80 pop {r7, pc} 8016530: 24002ef4 .word 0x24002ef4 8016534: 24002ee0 .word 0x24002ee0 8016538: 240029f8 .word 0x240029f8 801653c: 24002ed4 .word 0x24002ed4 8016540: 240029fc .word 0x240029fc 8016544: 24000048 .word 0x24000048 08016548 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8016548: b580 push {r7, lr} 801654a: b084 sub sp, #16 801654c: af00 add r7, sp, #0 801654e: 6078 str r0, [r7, #4] 8016550: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 8016552: 687b ldr r3, [r7, #4] 8016554: 2b00 cmp r3, #0 8016556: d10b bne.n 8016570 __asm volatile 8016558: f04f 0350 mov.w r3, #80 @ 0x50 801655c: f383 8811 msr BASEPRI, r3 8016560: f3bf 8f6f isb sy 8016564: f3bf 8f4f dsb sy 8016568: 60fb str r3, [r7, #12] } 801656a: bf00 nop 801656c: bf00 nop 801656e: e7fd b.n 801656c /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8016570: 4b07 ldr r3, [pc, #28] @ (8016590 ) 8016572: 681b ldr r3, [r3, #0] 8016574: 3318 adds r3, #24 8016576: 4619 mov r1, r3 8016578: 6878 ldr r0, [r7, #4] 801657a: f7fe f9de bl 801493a prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 801657e: 2101 movs r1, #1 8016580: 6838 ldr r0, [r7, #0] 8016582: f000 fded bl 8017160 } 8016586: bf00 nop 8016588: 3710 adds r7, #16 801658a: 46bd mov sp, r7 801658c: bd80 pop {r7, pc} 801658e: bf00 nop 8016590: 240029f8 .word 0x240029f8 08016594 : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { 8016594: b580 push {r7, lr} 8016596: b086 sub sp, #24 8016598: af00 add r7, sp, #0 801659a: 60f8 str r0, [r7, #12] 801659c: 60b9 str r1, [r7, #8] 801659e: 607a str r2, [r7, #4] configASSERT( pxEventList ); 80165a0: 68fb ldr r3, [r7, #12] 80165a2: 2b00 cmp r3, #0 80165a4: d10b bne.n 80165be __asm volatile 80165a6: f04f 0350 mov.w r3, #80 @ 0x50 80165aa: f383 8811 msr BASEPRI, r3 80165ae: f3bf 8f6f isb sy 80165b2: f3bf 8f4f dsb sy 80165b6: 617b str r3, [r7, #20] } 80165b8: bf00 nop 80165ba: bf00 nop 80165bc: e7fd b.n 80165ba /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80165be: 4b0a ldr r3, [pc, #40] @ (80165e8 ) 80165c0: 681b ldr r3, [r3, #0] 80165c2: 3318 adds r3, #24 80165c4: 4619 mov r1, r3 80165c6: 68f8 ldr r0, [r7, #12] 80165c8: f7fe f993 bl 80148f2 /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) 80165cc: 687b ldr r3, [r7, #4] 80165ce: 2b00 cmp r3, #0 80165d0: d002 beq.n 80165d8 { xTicksToWait = portMAX_DELAY; 80165d2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80165d6: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); 80165d8: 6879 ldr r1, [r7, #4] 80165da: 68b8 ldr r0, [r7, #8] 80165dc: f000 fdc0 bl 8017160 } 80165e0: bf00 nop 80165e2: 3718 adds r7, #24 80165e4: 46bd mov sp, r7 80165e6: bd80 pop {r7, pc} 80165e8: 240029f8 .word 0x240029f8 080165ec : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 80165ec: b580 push {r7, lr} 80165ee: b086 sub sp, #24 80165f0: af00 add r7, sp, #0 80165f2: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80165f4: 687b ldr r3, [r7, #4] 80165f6: 68db ldr r3, [r3, #12] 80165f8: 68db ldr r3, [r3, #12] 80165fa: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 80165fc: 693b ldr r3, [r7, #16] 80165fe: 2b00 cmp r3, #0 8016600: d10b bne.n 801661a __asm volatile 8016602: f04f 0350 mov.w r3, #80 @ 0x50 8016606: f383 8811 msr BASEPRI, r3 801660a: f3bf 8f6f isb sy 801660e: f3bf 8f4f dsb sy 8016612: 60fb str r3, [r7, #12] } 8016614: bf00 nop 8016616: bf00 nop 8016618: e7fd b.n 8016616 ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 801661a: 693b ldr r3, [r7, #16] 801661c: 3318 adds r3, #24 801661e: 4618 mov r0, r3 8016620: f7fe f9c4 bl 80149ac if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8016624: 4b1d ldr r3, [pc, #116] @ (801669c ) 8016626: 681b ldr r3, [r3, #0] 8016628: 2b00 cmp r3, #0 801662a: d11d bne.n 8016668 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 801662c: 693b ldr r3, [r7, #16] 801662e: 3304 adds r3, #4 8016630: 4618 mov r0, r3 8016632: f7fe f9bb bl 80149ac prvAddTaskToReadyList( pxUnblockedTCB ); 8016636: 693b ldr r3, [r7, #16] 8016638: 6ada ldr r2, [r3, #44] @ 0x2c 801663a: 4b19 ldr r3, [pc, #100] @ (80166a0 ) 801663c: 681b ldr r3, [r3, #0] 801663e: 429a cmp r2, r3 8016640: d903 bls.n 801664a 8016642: 693b ldr r3, [r7, #16] 8016644: 6adb ldr r3, [r3, #44] @ 0x2c 8016646: 4a16 ldr r2, [pc, #88] @ (80166a0 ) 8016648: 6013 str r3, [r2, #0] 801664a: 693b ldr r3, [r7, #16] 801664c: 6ada ldr r2, [r3, #44] @ 0x2c 801664e: 4613 mov r3, r2 8016650: 009b lsls r3, r3, #2 8016652: 4413 add r3, r2 8016654: 009b lsls r3, r3, #2 8016656: 4a13 ldr r2, [pc, #76] @ (80166a4 ) 8016658: 441a add r2, r3 801665a: 693b ldr r3, [r7, #16] 801665c: 3304 adds r3, #4 801665e: 4619 mov r1, r3 8016660: 4610 mov r0, r2 8016662: f7fe f946 bl 80148f2 8016666: e005 b.n 8016674 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8016668: 693b ldr r3, [r7, #16] 801666a: 3318 adds r3, #24 801666c: 4619 mov r1, r3 801666e: 480e ldr r0, [pc, #56] @ (80166a8 ) 8016670: f7fe f93f bl 80148f2 } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016674: 693b ldr r3, [r7, #16] 8016676: 6ada ldr r2, [r3, #44] @ 0x2c 8016678: 4b0c ldr r3, [pc, #48] @ (80166ac ) 801667a: 681b ldr r3, [r3, #0] 801667c: 6adb ldr r3, [r3, #44] @ 0x2c 801667e: 429a cmp r2, r3 8016680: d905 bls.n 801668e { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 8016682: 2301 movs r3, #1 8016684: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 8016686: 4b0a ldr r3, [pc, #40] @ (80166b0 ) 8016688: 2201 movs r2, #1 801668a: 601a str r2, [r3, #0] 801668c: e001 b.n 8016692 } else { xReturn = pdFALSE; 801668e: 2300 movs r3, #0 8016690: 617b str r3, [r7, #20] } return xReturn; 8016692: 697b ldr r3, [r7, #20] } 8016694: 4618 mov r0, r3 8016696: 3718 adds r7, #24 8016698: 46bd mov sp, r7 801669a: bd80 pop {r7, pc} 801669c: 24002ef4 .word 0x24002ef4 80166a0: 24002ed4 .word 0x24002ed4 80166a4: 240029fc .word 0x240029fc 80166a8: 24002e8c .word 0x24002e8c 80166ac: 240029f8 .word 0x240029f8 80166b0: 24002ee0 .word 0x24002ee0 080166b4 : } } /*-----------------------------------------------------------*/ void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) { 80166b4: b580 push {r7, lr} 80166b6: b084 sub sp, #16 80166b8: af00 add r7, sp, #0 80166ba: 6078 str r0, [r7, #4] configASSERT( pxTimeOut ); 80166bc: 687b ldr r3, [r7, #4] 80166be: 2b00 cmp r3, #0 80166c0: d10b bne.n 80166da __asm volatile 80166c2: f04f 0350 mov.w r3, #80 @ 0x50 80166c6: f383 8811 msr BASEPRI, r3 80166ca: f3bf 8f6f isb sy 80166ce: f3bf 8f4f dsb sy 80166d2: 60fb str r3, [r7, #12] } 80166d4: bf00 nop 80166d6: bf00 nop 80166d8: e7fd b.n 80166d6 taskENTER_CRITICAL(); 80166da: f001 fb0d bl 8017cf8 { pxTimeOut->xOverflowCount = xNumOfOverflows; 80166de: 4b07 ldr r3, [pc, #28] @ (80166fc ) 80166e0: 681a ldr r2, [r3, #0] 80166e2: 687b ldr r3, [r7, #4] 80166e4: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 80166e6: 4b06 ldr r3, [pc, #24] @ (8016700 ) 80166e8: 681a ldr r2, [r3, #0] 80166ea: 687b ldr r3, [r7, #4] 80166ec: 605a str r2, [r3, #4] } taskEXIT_CRITICAL(); 80166ee: f001 fb35 bl 8017d5c } 80166f2: bf00 nop 80166f4: 3710 adds r7, #16 80166f6: 46bd mov sp, r7 80166f8: bd80 pop {r7, pc} 80166fa: bf00 nop 80166fc: 24002ee4 .word 0x24002ee4 8016700: 24002ed0 .word 0x24002ed0 08016704 : /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 8016704: b480 push {r7} 8016706: b083 sub sp, #12 8016708: af00 add r7, sp, #0 801670a: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 801670c: 4b06 ldr r3, [pc, #24] @ (8016728 ) 801670e: 681a ldr r2, [r3, #0] 8016710: 687b ldr r3, [r7, #4] 8016712: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 8016714: 4b05 ldr r3, [pc, #20] @ (801672c ) 8016716: 681a ldr r2, [r3, #0] 8016718: 687b ldr r3, [r7, #4] 801671a: 605a str r2, [r3, #4] } 801671c: bf00 nop 801671e: 370c adds r7, #12 8016720: 46bd mov sp, r7 8016722: f85d 7b04 ldr.w r7, [sp], #4 8016726: 4770 bx lr 8016728: 24002ee4 .word 0x24002ee4 801672c: 24002ed0 .word 0x24002ed0 08016730 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8016730: b580 push {r7, lr} 8016732: b088 sub sp, #32 8016734: af00 add r7, sp, #0 8016736: 6078 str r0, [r7, #4] 8016738: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 801673a: 687b ldr r3, [r7, #4] 801673c: 2b00 cmp r3, #0 801673e: d10b bne.n 8016758 __asm volatile 8016740: f04f 0350 mov.w r3, #80 @ 0x50 8016744: f383 8811 msr BASEPRI, r3 8016748: f3bf 8f6f isb sy 801674c: f3bf 8f4f dsb sy 8016750: 613b str r3, [r7, #16] } 8016752: bf00 nop 8016754: bf00 nop 8016756: e7fd b.n 8016754 configASSERT( pxTicksToWait ); 8016758: 683b ldr r3, [r7, #0] 801675a: 2b00 cmp r3, #0 801675c: d10b bne.n 8016776 __asm volatile 801675e: f04f 0350 mov.w r3, #80 @ 0x50 8016762: f383 8811 msr BASEPRI, r3 8016766: f3bf 8f6f isb sy 801676a: f3bf 8f4f dsb sy 801676e: 60fb str r3, [r7, #12] } 8016770: bf00 nop 8016772: bf00 nop 8016774: e7fd b.n 8016772 taskENTER_CRITICAL(); 8016776: f001 fabf bl 8017cf8 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 801677a: 4b1d ldr r3, [pc, #116] @ (80167f0 ) 801677c: 681b ldr r3, [r3, #0] 801677e: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8016780: 687b ldr r3, [r7, #4] 8016782: 685b ldr r3, [r3, #4] 8016784: 69ba ldr r2, [r7, #24] 8016786: 1ad3 subs r3, r2, r3 8016788: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 801678a: 683b ldr r3, [r7, #0] 801678c: 681b ldr r3, [r3, #0] 801678e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016792: d102 bne.n 801679a { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8016794: 2300 movs r3, #0 8016796: 61fb str r3, [r7, #28] 8016798: e023 b.n 80167e2 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 801679a: 687b ldr r3, [r7, #4] 801679c: 681a ldr r2, [r3, #0] 801679e: 4b15 ldr r3, [pc, #84] @ (80167f4 ) 80167a0: 681b ldr r3, [r3, #0] 80167a2: 429a cmp r2, r3 80167a4: d007 beq.n 80167b6 80167a6: 687b ldr r3, [r7, #4] 80167a8: 685b ldr r3, [r3, #4] 80167aa: 69ba ldr r2, [r7, #24] 80167ac: 429a cmp r2, r3 80167ae: d302 bcc.n 80167b6 /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 80167b0: 2301 movs r3, #1 80167b2: 61fb str r3, [r7, #28] 80167b4: e015 b.n 80167e2 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 80167b6: 683b ldr r3, [r7, #0] 80167b8: 681b ldr r3, [r3, #0] 80167ba: 697a ldr r2, [r7, #20] 80167bc: 429a cmp r2, r3 80167be: d20b bcs.n 80167d8 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 80167c0: 683b ldr r3, [r7, #0] 80167c2: 681a ldr r2, [r3, #0] 80167c4: 697b ldr r3, [r7, #20] 80167c6: 1ad2 subs r2, r2, r3 80167c8: 683b ldr r3, [r7, #0] 80167ca: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 80167cc: 6878 ldr r0, [r7, #4] 80167ce: f7ff ff99 bl 8016704 xReturn = pdFALSE; 80167d2: 2300 movs r3, #0 80167d4: 61fb str r3, [r7, #28] 80167d6: e004 b.n 80167e2 } else { *pxTicksToWait = 0; 80167d8: 683b ldr r3, [r7, #0] 80167da: 2200 movs r2, #0 80167dc: 601a str r2, [r3, #0] xReturn = pdTRUE; 80167de: 2301 movs r3, #1 80167e0: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 80167e2: f001 fabb bl 8017d5c return xReturn; 80167e6: 69fb ldr r3, [r7, #28] } 80167e8: 4618 mov r0, r3 80167ea: 3720 adds r7, #32 80167ec: 46bd mov sp, r7 80167ee: bd80 pop {r7, pc} 80167f0: 24002ed0 .word 0x24002ed0 80167f4: 24002ee4 .word 0x24002ee4 080167f8 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 80167f8: b480 push {r7} 80167fa: af00 add r7, sp, #0 xYieldPending = pdTRUE; 80167fc: 4b03 ldr r3, [pc, #12] @ (801680c ) 80167fe: 2201 movs r2, #1 8016800: 601a str r2, [r3, #0] } 8016802: bf00 nop 8016804: 46bd mov sp, r7 8016806: f85d 7b04 ldr.w r7, [sp], #4 801680a: 4770 bx lr 801680c: 24002ee0 .word 0x24002ee0 08016810 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { 8016810: b580 push {r7, lr} 8016812: b082 sub sp, #8 8016814: af00 add r7, sp, #0 8016816: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); 8016818: f000 f852 bl 80168c0 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) 801681c: 4b06 ldr r3, [pc, #24] @ (8016838 ) 801681e: 681b ldr r3, [r3, #0] 8016820: 2b01 cmp r3, #1 8016822: d9f9 bls.n 8016818 { taskYIELD(); 8016824: 4b05 ldr r3, [pc, #20] @ (801683c ) 8016826: f04f 5280 mov.w r2, #268435456 @ 0x10000000 801682a: 601a str r2, [r3, #0] 801682c: f3bf 8f4f dsb sy 8016830: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); 8016834: e7f0 b.n 8016818 8016836: bf00 nop 8016838: 240029fc .word 0x240029fc 801683c: e000ed04 .word 0xe000ed04 08016840 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { 8016840: b580 push {r7, lr} 8016842: b082 sub sp, #8 8016844: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8016846: 2300 movs r3, #0 8016848: 607b str r3, [r7, #4] 801684a: e00c b.n 8016866 { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); 801684c: 687a ldr r2, [r7, #4] 801684e: 4613 mov r3, r2 8016850: 009b lsls r3, r3, #2 8016852: 4413 add r3, r2 8016854: 009b lsls r3, r3, #2 8016856: 4a12 ldr r2, [pc, #72] @ (80168a0 ) 8016858: 4413 add r3, r2 801685a: 4618 mov r0, r3 801685c: f7fe f81c bl 8014898 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) 8016860: 687b ldr r3, [r7, #4] 8016862: 3301 adds r3, #1 8016864: 607b str r3, [r7, #4] 8016866: 687b ldr r3, [r7, #4] 8016868: 2b37 cmp r3, #55 @ 0x37 801686a: d9ef bls.n 801684c } vListInitialise( &xDelayedTaskList1 ); 801686c: 480d ldr r0, [pc, #52] @ (80168a4 ) 801686e: f7fe f813 bl 8014898 vListInitialise( &xDelayedTaskList2 ); 8016872: 480d ldr r0, [pc, #52] @ (80168a8 ) 8016874: f7fe f810 bl 8014898 vListInitialise( &xPendingReadyList ); 8016878: 480c ldr r0, [pc, #48] @ (80168ac ) 801687a: f7fe f80d bl 8014898 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); 801687e: 480c ldr r0, [pc, #48] @ (80168b0 ) 8016880: f7fe f80a bl 8014898 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); 8016884: 480b ldr r0, [pc, #44] @ (80168b4 ) 8016886: f7fe f807 bl 8014898 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; 801688a: 4b0b ldr r3, [pc, #44] @ (80168b8 ) 801688c: 4a05 ldr r2, [pc, #20] @ (80168a4 ) 801688e: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; 8016890: 4b0a ldr r3, [pc, #40] @ (80168bc ) 8016892: 4a05 ldr r2, [pc, #20] @ (80168a8 ) 8016894: 601a str r2, [r3, #0] } 8016896: bf00 nop 8016898: 3708 adds r7, #8 801689a: 46bd mov sp, r7 801689c: bd80 pop {r7, pc} 801689e: bf00 nop 80168a0: 240029fc .word 0x240029fc 80168a4: 24002e5c .word 0x24002e5c 80168a8: 24002e70 .word 0x24002e70 80168ac: 24002e8c .word 0x24002e8c 80168b0: 24002ea0 .word 0x24002ea0 80168b4: 24002eb8 .word 0x24002eb8 80168b8: 24002e84 .word 0x24002e84 80168bc: 24002e88 .word 0x24002e88 080168c0 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { 80168c0: b580 push {r7, lr} 80168c2: b082 sub sp, #8 80168c4: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 80168c6: e019 b.n 80168fc { taskENTER_CRITICAL(); 80168c8: f001 fa16 bl 8017cf8 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80168cc: 4b10 ldr r3, [pc, #64] @ (8016910 ) 80168ce: 68db ldr r3, [r3, #12] 80168d0: 68db ldr r3, [r3, #12] 80168d2: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80168d4: 687b ldr r3, [r7, #4] 80168d6: 3304 adds r3, #4 80168d8: 4618 mov r0, r3 80168da: f7fe f867 bl 80149ac --uxCurrentNumberOfTasks; 80168de: 4b0d ldr r3, [pc, #52] @ (8016914 ) 80168e0: 681b ldr r3, [r3, #0] 80168e2: 3b01 subs r3, #1 80168e4: 4a0b ldr r2, [pc, #44] @ (8016914 ) 80168e6: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; 80168e8: 4b0b ldr r3, [pc, #44] @ (8016918 ) 80168ea: 681b ldr r3, [r3, #0] 80168ec: 3b01 subs r3, #1 80168ee: 4a0a ldr r2, [pc, #40] @ (8016918 ) 80168f0: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); 80168f2: f001 fa33 bl 8017d5c prvDeleteTCB( pxTCB ); 80168f6: 6878 ldr r0, [r7, #4] 80168f8: f000 f810 bl 801691c while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) 80168fc: 4b06 ldr r3, [pc, #24] @ (8016918 ) 80168fe: 681b ldr r3, [r3, #0] 8016900: 2b00 cmp r3, #0 8016902: d1e1 bne.n 80168c8 } } #endif /* INCLUDE_vTaskDelete */ } 8016904: bf00 nop 8016906: bf00 nop 8016908: 3708 adds r7, #8 801690a: 46bd mov sp, r7 801690c: bd80 pop {r7, pc} 801690e: bf00 nop 8016910: 24002ea0 .word 0x24002ea0 8016914: 24002ecc .word 0x24002ecc 8016918: 24002eb4 .word 0x24002eb4 0801691c : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { 801691c: b580 push {r7, lr} 801691e: b084 sub sp, #16 8016920: af00 add r7, sp, #0 8016922: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); 8016924: 687b ldr r3, [r7, #4] 8016926: 3354 adds r3, #84 @ 0x54 8016928: 4618 mov r0, r3 801692a: f001 fcfd bl 8018328 <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) 801692e: 687b ldr r3, [r7, #4] 8016930: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8016934: 2b00 cmp r3, #0 8016936: d108 bne.n 801694a { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); 8016938: 687b ldr r3, [r7, #4] 801693a: 6b1b ldr r3, [r3, #48] @ 0x30 801693c: 4618 mov r0, r3 801693e: f001 fbcb bl 80180d8 vPortFree( pxTCB ); 8016942: 6878 ldr r0, [r7, #4] 8016944: f001 fbc8 bl 80180d8 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } 8016948: e019 b.n 801697e else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) 801694a: 687b ldr r3, [r7, #4] 801694c: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8016950: 2b01 cmp r3, #1 8016952: d103 bne.n 801695c vPortFree( pxTCB ); 8016954: 6878 ldr r0, [r7, #4] 8016956: f001 fbbf bl 80180d8 } 801695a: e010 b.n 801697e configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); 801695c: 687b ldr r3, [r7, #4] 801695e: f893 30a5 ldrb.w r3, [r3, #165] @ 0xa5 8016962: 2b02 cmp r3, #2 8016964: d00b beq.n 801697e __asm volatile 8016966: f04f 0350 mov.w r3, #80 @ 0x50 801696a: f383 8811 msr BASEPRI, r3 801696e: f3bf 8f6f isb sy 8016972: f3bf 8f4f dsb sy 8016976: 60fb str r3, [r7, #12] } 8016978: bf00 nop 801697a: bf00 nop 801697c: e7fd b.n 801697a } 801697e: bf00 nop 8016980: 3710 adds r7, #16 8016982: 46bd mov sp, r7 8016984: bd80 pop {r7, pc} ... 08016988 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8016988: b480 push {r7} 801698a: b083 sub sp, #12 801698c: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 801698e: 4b0c ldr r3, [pc, #48] @ (80169c0 ) 8016990: 681b ldr r3, [r3, #0] 8016992: 681b ldr r3, [r3, #0] 8016994: 2b00 cmp r3, #0 8016996: d104 bne.n 80169a2 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8016998: 4b0a ldr r3, [pc, #40] @ (80169c4 ) 801699a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 801699e: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 80169a0: e008 b.n 80169b4 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80169a2: 4b07 ldr r3, [pc, #28] @ (80169c0 ) 80169a4: 681b ldr r3, [r3, #0] 80169a6: 68db ldr r3, [r3, #12] 80169a8: 68db ldr r3, [r3, #12] 80169aa: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 80169ac: 687b ldr r3, [r7, #4] 80169ae: 685b ldr r3, [r3, #4] 80169b0: 4a04 ldr r2, [pc, #16] @ (80169c4 ) 80169b2: 6013 str r3, [r2, #0] } 80169b4: bf00 nop 80169b6: 370c adds r7, #12 80169b8: 46bd mov sp, r7 80169ba: f85d 7b04 ldr.w r7, [sp], #4 80169be: 4770 bx lr 80169c0: 24002e84 .word 0x24002e84 80169c4: 24002eec .word 0x24002eec 080169c8 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) TaskHandle_t xTaskGetCurrentTaskHandle( void ) { 80169c8: b480 push {r7} 80169ca: b083 sub sp, #12 80169cc: af00 add r7, sp, #0 TaskHandle_t xReturn; /* A critical section is not required as this is not called from an interrupt and the current TCB will always be the same for any individual execution thread. */ xReturn = pxCurrentTCB; 80169ce: 4b05 ldr r3, [pc, #20] @ (80169e4 ) 80169d0: 681b ldr r3, [r3, #0] 80169d2: 607b str r3, [r7, #4] return xReturn; 80169d4: 687b ldr r3, [r7, #4] } 80169d6: 4618 mov r0, r3 80169d8: 370c adds r7, #12 80169da: 46bd mov sp, r7 80169dc: f85d 7b04 ldr.w r7, [sp], #4 80169e0: 4770 bx lr 80169e2: bf00 nop 80169e4: 240029f8 .word 0x240029f8 080169e8 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 80169e8: b480 push {r7} 80169ea: b083 sub sp, #12 80169ec: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 80169ee: 4b0b ldr r3, [pc, #44] @ (8016a1c ) 80169f0: 681b ldr r3, [r3, #0] 80169f2: 2b00 cmp r3, #0 80169f4: d102 bne.n 80169fc { xReturn = taskSCHEDULER_NOT_STARTED; 80169f6: 2301 movs r3, #1 80169f8: 607b str r3, [r7, #4] 80169fa: e008 b.n 8016a0e } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80169fc: 4b08 ldr r3, [pc, #32] @ (8016a20 ) 80169fe: 681b ldr r3, [r3, #0] 8016a00: 2b00 cmp r3, #0 8016a02: d102 bne.n 8016a0a { xReturn = taskSCHEDULER_RUNNING; 8016a04: 2302 movs r3, #2 8016a06: 607b str r3, [r7, #4] 8016a08: e001 b.n 8016a0e } else { xReturn = taskSCHEDULER_SUSPENDED; 8016a0a: 2300 movs r3, #0 8016a0c: 607b str r3, [r7, #4] } } return xReturn; 8016a0e: 687b ldr r3, [r7, #4] } 8016a10: 4618 mov r0, r3 8016a12: 370c adds r7, #12 8016a14: 46bd mov sp, r7 8016a16: f85d 7b04 ldr.w r7, [sp], #4 8016a1a: 4770 bx lr 8016a1c: 24002ed8 .word 0x24002ed8 8016a20: 24002ef4 .word 0x24002ef4 08016a24 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) { 8016a24: b580 push {r7, lr} 8016a26: b084 sub sp, #16 8016a28: af00 add r7, sp, #0 8016a2a: 6078 str r0, [r7, #4] TCB_t * const pxMutexHolderTCB = pxMutexHolder; 8016a2c: 687b ldr r3, [r7, #4] 8016a2e: 60bb str r3, [r7, #8] BaseType_t xReturn = pdFALSE; 8016a30: 2300 movs r3, #0 8016a32: 60fb str r3, [r7, #12] /* If the mutex was given back by an interrupt while the queue was locked then the mutex holder might now be NULL. _RB_ Is this still needed as interrupts can no longer use mutexes? */ if( pxMutexHolder != NULL ) 8016a34: 687b ldr r3, [r7, #4] 8016a36: 2b00 cmp r3, #0 8016a38: d051 beq.n 8016ade { /* If the holder of the mutex has a priority below the priority of the task attempting to obtain the mutex then it will temporarily inherit the priority of the task attempting to obtain the mutex. */ if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority ) 8016a3a: 68bb ldr r3, [r7, #8] 8016a3c: 6ada ldr r2, [r3, #44] @ 0x2c 8016a3e: 4b2a ldr r3, [pc, #168] @ (8016ae8 ) 8016a40: 681b ldr r3, [r3, #0] 8016a42: 6adb ldr r3, [r3, #44] @ 0x2c 8016a44: 429a cmp r2, r3 8016a46: d241 bcs.n 8016acc { /* Adjust the mutex holder state to account for its new priority. Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016a48: 68bb ldr r3, [r7, #8] 8016a4a: 699b ldr r3, [r3, #24] 8016a4c: 2b00 cmp r3, #0 8016a4e: db06 blt.n 8016a5e { listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016a50: 4b25 ldr r3, [pc, #148] @ (8016ae8 ) 8016a52: 681b ldr r3, [r3, #0] 8016a54: 6adb ldr r3, [r3, #44] @ 0x2c 8016a56: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016a5a: 68bb ldr r3, [r7, #8] 8016a5c: 619a str r2, [r3, #24] mtCOVERAGE_TEST_MARKER(); } /* If the task being modified is in the ready state it will need to be moved into a new list. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE ) 8016a5e: 68bb ldr r3, [r7, #8] 8016a60: 6959 ldr r1, [r3, #20] 8016a62: 68bb ldr r3, [r7, #8] 8016a64: 6ada ldr r2, [r3, #44] @ 0x2c 8016a66: 4613 mov r3, r2 8016a68: 009b lsls r3, r3, #2 8016a6a: 4413 add r3, r2 8016a6c: 009b lsls r3, r3, #2 8016a6e: 4a1f ldr r2, [pc, #124] @ (8016aec ) 8016a70: 4413 add r3, r2 8016a72: 4299 cmp r1, r3 8016a74: d122 bne.n 8016abc { if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016a76: 68bb ldr r3, [r7, #8] 8016a78: 3304 adds r3, #4 8016a7a: 4618 mov r0, r3 8016a7c: f7fd ff96 bl 80149ac { mtCOVERAGE_TEST_MARKER(); } /* Inherit the priority before being moved into the new list. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016a80: 4b19 ldr r3, [pc, #100] @ (8016ae8 ) 8016a82: 681b ldr r3, [r3, #0] 8016a84: 6ada ldr r2, [r3, #44] @ 0x2c 8016a86: 68bb ldr r3, [r7, #8] 8016a88: 62da str r2, [r3, #44] @ 0x2c prvAddTaskToReadyList( pxMutexHolderTCB ); 8016a8a: 68bb ldr r3, [r7, #8] 8016a8c: 6ada ldr r2, [r3, #44] @ 0x2c 8016a8e: 4b18 ldr r3, [pc, #96] @ (8016af0 ) 8016a90: 681b ldr r3, [r3, #0] 8016a92: 429a cmp r2, r3 8016a94: d903 bls.n 8016a9e 8016a96: 68bb ldr r3, [r7, #8] 8016a98: 6adb ldr r3, [r3, #44] @ 0x2c 8016a9a: 4a15 ldr r2, [pc, #84] @ (8016af0 ) 8016a9c: 6013 str r3, [r2, #0] 8016a9e: 68bb ldr r3, [r7, #8] 8016aa0: 6ada ldr r2, [r3, #44] @ 0x2c 8016aa2: 4613 mov r3, r2 8016aa4: 009b lsls r3, r3, #2 8016aa6: 4413 add r3, r2 8016aa8: 009b lsls r3, r3, #2 8016aaa: 4a10 ldr r2, [pc, #64] @ (8016aec ) 8016aac: 441a add r2, r3 8016aae: 68bb ldr r3, [r7, #8] 8016ab0: 3304 adds r3, #4 8016ab2: 4619 mov r1, r3 8016ab4: 4610 mov r0, r2 8016ab6: f7fd ff1c bl 80148f2 8016aba: e004 b.n 8016ac6 } else { /* Just inherit the priority. */ pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; 8016abc: 4b0a ldr r3, [pc, #40] @ (8016ae8 ) 8016abe: 681b ldr r3, [r3, #0] 8016ac0: 6ada ldr r2, [r3, #44] @ 0x2c 8016ac2: 68bb ldr r3, [r7, #8] 8016ac4: 62da str r2, [r3, #44] @ 0x2c } traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority ); /* Inheritance occurred. */ xReturn = pdTRUE; 8016ac6: 2301 movs r3, #1 8016ac8: 60fb str r3, [r7, #12] 8016aca: e008 b.n 8016ade } else { if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority ) 8016acc: 68bb ldr r3, [r7, #8] 8016ace: 6cda ldr r2, [r3, #76] @ 0x4c 8016ad0: 4b05 ldr r3, [pc, #20] @ (8016ae8 ) 8016ad2: 681b ldr r3, [r3, #0] 8016ad4: 6adb ldr r3, [r3, #44] @ 0x2c 8016ad6: 429a cmp r2, r3 8016ad8: d201 bcs.n 8016ade current priority of the mutex holder is not lower than the priority of the task attempting to take the mutex. Therefore the mutex holder must have already inherited a priority, but inheritance would have occurred if that had not been the case. */ xReturn = pdTRUE; 8016ada: 2301 movs r3, #1 8016adc: 60fb str r3, [r7, #12] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016ade: 68fb ldr r3, [r7, #12] } 8016ae0: 4618 mov r0, r3 8016ae2: 3710 adds r7, #16 8016ae4: 46bd mov sp, r7 8016ae6: bd80 pop {r7, pc} 8016ae8: 240029f8 .word 0x240029f8 8016aec: 240029fc .word 0x240029fc 8016af0: 24002ed4 .word 0x24002ed4 08016af4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 8016af4: b580 push {r7, lr} 8016af6: b086 sub sp, #24 8016af8: af00 add r7, sp, #0 8016afa: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8016afc: 687b ldr r3, [r7, #4] 8016afe: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8016b00: 2300 movs r3, #0 8016b02: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016b04: 687b ldr r3, [r7, #4] 8016b06: 2b00 cmp r3, #0 8016b08: d058 beq.n 8016bbc { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8016b0a: 4b2f ldr r3, [pc, #188] @ (8016bc8 ) 8016b0c: 681b ldr r3, [r3, #0] 8016b0e: 693a ldr r2, [r7, #16] 8016b10: 429a cmp r2, r3 8016b12: d00b beq.n 8016b2c __asm volatile 8016b14: f04f 0350 mov.w r3, #80 @ 0x50 8016b18: f383 8811 msr BASEPRI, r3 8016b1c: f3bf 8f6f isb sy 8016b20: f3bf 8f4f dsb sy 8016b24: 60fb str r3, [r7, #12] } 8016b26: bf00 nop 8016b28: bf00 nop 8016b2a: e7fd b.n 8016b28 configASSERT( pxTCB->uxMutexesHeld ); 8016b2c: 693b ldr r3, [r7, #16] 8016b2e: 6d1b ldr r3, [r3, #80] @ 0x50 8016b30: 2b00 cmp r3, #0 8016b32: d10b bne.n 8016b4c __asm volatile 8016b34: f04f 0350 mov.w r3, #80 @ 0x50 8016b38: f383 8811 msr BASEPRI, r3 8016b3c: f3bf 8f6f isb sy 8016b40: f3bf 8f4f dsb sy 8016b44: 60bb str r3, [r7, #8] } 8016b46: bf00 nop 8016b48: bf00 nop 8016b4a: e7fd b.n 8016b48 ( pxTCB->uxMutexesHeld )--; 8016b4c: 693b ldr r3, [r7, #16] 8016b4e: 6d1b ldr r3, [r3, #80] @ 0x50 8016b50: 1e5a subs r2, r3, #1 8016b52: 693b ldr r3, [r7, #16] 8016b54: 651a str r2, [r3, #80] @ 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 8016b56: 693b ldr r3, [r7, #16] 8016b58: 6ada ldr r2, [r3, #44] @ 0x2c 8016b5a: 693b ldr r3, [r7, #16] 8016b5c: 6cdb ldr r3, [r3, #76] @ 0x4c 8016b5e: 429a cmp r2, r3 8016b60: d02c beq.n 8016bbc { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 8016b62: 693b ldr r3, [r7, #16] 8016b64: 6d1b ldr r3, [r3, #80] @ 0x50 8016b66: 2b00 cmp r3, #0 8016b68: d128 bne.n 8016bbc /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016b6a: 693b ldr r3, [r7, #16] 8016b6c: 3304 adds r3, #4 8016b6e: 4618 mov r0, r3 8016b70: f7fd ff1c bl 80149ac } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8016b74: 693b ldr r3, [r7, #16] 8016b76: 6cda ldr r2, [r3, #76] @ 0x4c 8016b78: 693b ldr r3, [r7, #16] 8016b7a: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016b7c: 693b ldr r3, [r7, #16] 8016b7e: 6adb ldr r3, [r3, #44] @ 0x2c 8016b80: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016b84: 693b ldr r3, [r7, #16] 8016b86: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8016b88: 693b ldr r3, [r7, #16] 8016b8a: 6ada ldr r2, [r3, #44] @ 0x2c 8016b8c: 4b0f ldr r3, [pc, #60] @ (8016bcc ) 8016b8e: 681b ldr r3, [r3, #0] 8016b90: 429a cmp r2, r3 8016b92: d903 bls.n 8016b9c 8016b94: 693b ldr r3, [r7, #16] 8016b96: 6adb ldr r3, [r3, #44] @ 0x2c 8016b98: 4a0c ldr r2, [pc, #48] @ (8016bcc ) 8016b9a: 6013 str r3, [r2, #0] 8016b9c: 693b ldr r3, [r7, #16] 8016b9e: 6ada ldr r2, [r3, #44] @ 0x2c 8016ba0: 4613 mov r3, r2 8016ba2: 009b lsls r3, r3, #2 8016ba4: 4413 add r3, r2 8016ba6: 009b lsls r3, r3, #2 8016ba8: 4a09 ldr r2, [pc, #36] @ (8016bd0 ) 8016baa: 441a add r2, r3 8016bac: 693b ldr r3, [r7, #16] 8016bae: 3304 adds r3, #4 8016bb0: 4619 mov r1, r3 8016bb2: 4610 mov r0, r2 8016bb4: f7fd fe9d bl 80148f2 in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8016bb8: 2301 movs r3, #1 8016bba: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8016bbc: 697b ldr r3, [r7, #20] } 8016bbe: 4618 mov r0, r3 8016bc0: 3718 adds r7, #24 8016bc2: 46bd mov sp, r7 8016bc4: bd80 pop {r7, pc} 8016bc6: bf00 nop 8016bc8: 240029f8 .word 0x240029f8 8016bcc: 24002ed4 .word 0x24002ed4 8016bd0: 240029fc .word 0x240029fc 08016bd4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) { 8016bd4: b580 push {r7, lr} 8016bd6: b088 sub sp, #32 8016bd8: af00 add r7, sp, #0 8016bda: 6078 str r0, [r7, #4] 8016bdc: 6039 str r1, [r7, #0] TCB_t * const pxTCB = pxMutexHolder; 8016bde: 687b ldr r3, [r7, #4] 8016be0: 61bb str r3, [r7, #24] UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1; 8016be2: 2301 movs r3, #1 8016be4: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 8016be6: 687b ldr r3, [r7, #4] 8016be8: 2b00 cmp r3, #0 8016bea: d06c beq.n 8016cc6 { /* If pxMutexHolder is not NULL then the holder must hold at least one mutex. */ configASSERT( pxTCB->uxMutexesHeld ); 8016bec: 69bb ldr r3, [r7, #24] 8016bee: 6d1b ldr r3, [r3, #80] @ 0x50 8016bf0: 2b00 cmp r3, #0 8016bf2: d10b bne.n 8016c0c __asm volatile 8016bf4: f04f 0350 mov.w r3, #80 @ 0x50 8016bf8: f383 8811 msr BASEPRI, r3 8016bfc: f3bf 8f6f isb sy 8016c00: f3bf 8f4f dsb sy 8016c04: 60fb str r3, [r7, #12] } 8016c06: bf00 nop 8016c08: bf00 nop 8016c0a: e7fd b.n 8016c08 /* Determine the priority to which the priority of the task that holds the mutex should be set. This will be the greater of the holding task's base priority and the priority of the highest priority task that is waiting to obtain the mutex. */ if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask ) 8016c0c: 69bb ldr r3, [r7, #24] 8016c0e: 6cdb ldr r3, [r3, #76] @ 0x4c 8016c10: 683a ldr r2, [r7, #0] 8016c12: 429a cmp r2, r3 8016c14: d902 bls.n 8016c1c { uxPriorityToUse = uxHighestPriorityWaitingTask; 8016c16: 683b ldr r3, [r7, #0] 8016c18: 61fb str r3, [r7, #28] 8016c1a: e002 b.n 8016c22 } else { uxPriorityToUse = pxTCB->uxBasePriority; 8016c1c: 69bb ldr r3, [r7, #24] 8016c1e: 6cdb ldr r3, [r3, #76] @ 0x4c 8016c20: 61fb str r3, [r7, #28] } /* Does the priority need to change? */ if( pxTCB->uxPriority != uxPriorityToUse ) 8016c22: 69bb ldr r3, [r7, #24] 8016c24: 6adb ldr r3, [r3, #44] @ 0x2c 8016c26: 69fa ldr r2, [r7, #28] 8016c28: 429a cmp r2, r3 8016c2a: d04c beq.n 8016cc6 { /* Only disinherit if no other mutexes are held. This is a simplification in the priority inheritance implementation. If the task that holds the mutex is also holding other mutexes then the other mutexes may have caused the priority inheritance. */ if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld ) 8016c2c: 69bb ldr r3, [r7, #24] 8016c2e: 6d1b ldr r3, [r3, #80] @ 0x50 8016c30: 697a ldr r2, [r7, #20] 8016c32: 429a cmp r2, r3 8016c34: d147 bne.n 8016cc6 { /* If a task has timed out because it already holds the mutex it was trying to obtain then it cannot of inherited its own priority. */ configASSERT( pxTCB != pxCurrentTCB ); 8016c36: 4b26 ldr r3, [pc, #152] @ (8016cd0 ) 8016c38: 681b ldr r3, [r3, #0] 8016c3a: 69ba ldr r2, [r7, #24] 8016c3c: 429a cmp r2, r3 8016c3e: d10b bne.n 8016c58 __asm volatile 8016c40: f04f 0350 mov.w r3, #80 @ 0x50 8016c44: f383 8811 msr BASEPRI, r3 8016c48: f3bf 8f6f isb sy 8016c4c: f3bf 8f4f dsb sy 8016c50: 60bb str r3, [r7, #8] } 8016c52: bf00 nop 8016c54: bf00 nop 8016c56: e7fd b.n 8016c54 /* Disinherit the priority, remembering the previous priority to facilitate determining the subject task's state. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); uxPriorityUsedOnEntry = pxTCB->uxPriority; 8016c58: 69bb ldr r3, [r7, #24] 8016c5a: 6adb ldr r3, [r3, #44] @ 0x2c 8016c5c: 613b str r3, [r7, #16] pxTCB->uxPriority = uxPriorityToUse; 8016c5e: 69bb ldr r3, [r7, #24] 8016c60: 69fa ldr r2, [r7, #28] 8016c62: 62da str r2, [r3, #44] @ 0x2c /* Only reset the event list item value if the value is not being used for anything else. */ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL ) 8016c64: 69bb ldr r3, [r7, #24] 8016c66: 699b ldr r3, [r3, #24] 8016c68: 2b00 cmp r3, #0 8016c6a: db04 blt.n 8016c76 { listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8016c6c: 69fb ldr r3, [r7, #28] 8016c6e: f1c3 0238 rsb r2, r3, #56 @ 0x38 8016c72: 69bb ldr r3, [r7, #24] 8016c74: 619a str r2, [r3, #24] then the task that holds the mutex could be in either the Ready, Blocked or Suspended states. Only remove the task from its current state list if it is in the Ready state as the task's priority is going to change and there is one Ready list per priority. */ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE ) 8016c76: 69bb ldr r3, [r7, #24] 8016c78: 6959 ldr r1, [r3, #20] 8016c7a: 693a ldr r2, [r7, #16] 8016c7c: 4613 mov r3, r2 8016c7e: 009b lsls r3, r3, #2 8016c80: 4413 add r3, r2 8016c82: 009b lsls r3, r3, #2 8016c84: 4a13 ldr r2, [pc, #76] @ (8016cd4 ) 8016c86: 4413 add r3, r2 8016c88: 4299 cmp r1, r3 8016c8a: d11c bne.n 8016cc6 { if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8016c8c: 69bb ldr r3, [r7, #24] 8016c8e: 3304 adds r3, #4 8016c90: 4618 mov r0, r3 8016c92: f7fd fe8b bl 80149ac else { mtCOVERAGE_TEST_MARKER(); } prvAddTaskToReadyList( pxTCB ); 8016c96: 69bb ldr r3, [r7, #24] 8016c98: 6ada ldr r2, [r3, #44] @ 0x2c 8016c9a: 4b0f ldr r3, [pc, #60] @ (8016cd8 ) 8016c9c: 681b ldr r3, [r3, #0] 8016c9e: 429a cmp r2, r3 8016ca0: d903 bls.n 8016caa 8016ca2: 69bb ldr r3, [r7, #24] 8016ca4: 6adb ldr r3, [r3, #44] @ 0x2c 8016ca6: 4a0c ldr r2, [pc, #48] @ (8016cd8 ) 8016ca8: 6013 str r3, [r2, #0] 8016caa: 69bb ldr r3, [r7, #24] 8016cac: 6ada ldr r2, [r3, #44] @ 0x2c 8016cae: 4613 mov r3, r2 8016cb0: 009b lsls r3, r3, #2 8016cb2: 4413 add r3, r2 8016cb4: 009b lsls r3, r3, #2 8016cb6: 4a07 ldr r2, [pc, #28] @ (8016cd4 ) 8016cb8: 441a add r2, r3 8016cba: 69bb ldr r3, [r7, #24] 8016cbc: 3304 adds r3, #4 8016cbe: 4619 mov r1, r3 8016cc0: 4610 mov r0, r2 8016cc2: f7fd fe16 bl 80148f2 } else { mtCOVERAGE_TEST_MARKER(); } } 8016cc6: bf00 nop 8016cc8: 3720 adds r7, #32 8016cca: 46bd mov sp, r7 8016ccc: bd80 pop {r7, pc} 8016cce: bf00 nop 8016cd0: 240029f8 .word 0x240029f8 8016cd4: 240029fc .word 0x240029fc 8016cd8: 24002ed4 .word 0x24002ed4 08016cdc : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) TaskHandle_t pvTaskIncrementMutexHeldCount( void ) { 8016cdc: b480 push {r7} 8016cde: af00 add r7, sp, #0 /* If xSemaphoreCreateMutex() is called before any tasks have been created then pxCurrentTCB will be NULL. */ if( pxCurrentTCB != NULL ) 8016ce0: 4b07 ldr r3, [pc, #28] @ (8016d00 ) 8016ce2: 681b ldr r3, [r3, #0] 8016ce4: 2b00 cmp r3, #0 8016ce6: d004 beq.n 8016cf2 { ( pxCurrentTCB->uxMutexesHeld )++; 8016ce8: 4b05 ldr r3, [pc, #20] @ (8016d00 ) 8016cea: 681b ldr r3, [r3, #0] 8016cec: 6d1a ldr r2, [r3, #80] @ 0x50 8016cee: 3201 adds r2, #1 8016cf0: 651a str r2, [r3, #80] @ 0x50 } return pxCurrentTCB; 8016cf2: 4b03 ldr r3, [pc, #12] @ (8016d00 ) 8016cf4: 681b ldr r3, [r3, #0] } 8016cf6: 4618 mov r0, r3 8016cf8: 46bd mov sp, r7 8016cfa: f85d 7b04 ldr.w r7, [sp], #4 8016cfe: 4770 bx lr 8016d00: 240029f8 .word 0x240029f8 08016d04 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) { 8016d04: b580 push {r7, lr} 8016d06: b086 sub sp, #24 8016d08: af00 add r7, sp, #0 8016d0a: 60f8 str r0, [r7, #12] 8016d0c: 60b9 str r1, [r7, #8] 8016d0e: 607a str r2, [r7, #4] 8016d10: 603b str r3, [r7, #0] BaseType_t xReturn; taskENTER_CRITICAL(); 8016d12: f000 fff1 bl 8017cf8 { /* Only block if a notification is not already pending. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016d16: 4b29 ldr r3, [pc, #164] @ (8016dbc ) 8016d18: 681b ldr r3, [r3, #0] 8016d1a: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016d1e: b2db uxtb r3, r3 8016d20: 2b02 cmp r3, #2 8016d22: d01c beq.n 8016d5e { /* Clear bits in the task's notification value as bits may get set by the notifying task or interrupt. This can be used to clear the value to zero. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry; 8016d24: 4b25 ldr r3, [pc, #148] @ (8016dbc ) 8016d26: 681b ldr r3, [r3, #0] 8016d28: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016d2c: 68fa ldr r2, [r7, #12] 8016d2e: 43d2 mvns r2, r2 8016d30: 400a ands r2, r1 8016d32: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 /* Mark this task as waiting for a notification. */ pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION; 8016d36: 4b21 ldr r3, [pc, #132] @ (8016dbc ) 8016d38: 681b ldr r3, [r3, #0] 8016d3a: 2201 movs r2, #1 8016d3c: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 if( xTicksToWait > ( TickType_t ) 0 ) 8016d40: 683b ldr r3, [r7, #0] 8016d42: 2b00 cmp r3, #0 8016d44: d00b beq.n 8016d5e { prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8016d46: 2101 movs r1, #1 8016d48: 6838 ldr r0, [r7, #0] 8016d4a: f000 fa09 bl 8017160 /* All ports are written to allow a yield in a critical section (some will yield immediately, others wait until the critical section exits) - but it is not something that application code should ever do. */ portYIELD_WITHIN_API(); 8016d4e: 4b1c ldr r3, [pc, #112] @ (8016dc0 ) 8016d50: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016d54: 601a str r2, [r3, #0] 8016d56: f3bf 8f4f dsb sy 8016d5a: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016d5e: f000 fffd bl 8017d5c taskENTER_CRITICAL(); 8016d62: f000 ffc9 bl 8017cf8 { traceTASK_NOTIFY_WAIT(); if( pulNotificationValue != NULL ) 8016d66: 687b ldr r3, [r7, #4] 8016d68: 2b00 cmp r3, #0 8016d6a: d005 beq.n 8016d78 { /* Output the current notification value, which may or may not have changed. */ *pulNotificationValue = pxCurrentTCB->ulNotifiedValue; 8016d6c: 4b13 ldr r3, [pc, #76] @ (8016dbc ) 8016d6e: 681b ldr r3, [r3, #0] 8016d70: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016d74: 687b ldr r3, [r7, #4] 8016d76: 601a str r2, [r3, #0] /* If ucNotifyValue is set then either the task never entered the blocked state (because a notification was already pending) or the task unblocked because of a notification. Otherwise the task unblocked because of a timeout. */ if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED ) 8016d78: 4b10 ldr r3, [pc, #64] @ (8016dbc ) 8016d7a: 681b ldr r3, [r3, #0] 8016d7c: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016d80: b2db uxtb r3, r3 8016d82: 2b02 cmp r3, #2 8016d84: d002 beq.n 8016d8c { /* A notification was not received. */ xReturn = pdFALSE; 8016d86: 2300 movs r3, #0 8016d88: 617b str r3, [r7, #20] 8016d8a: e00a b.n 8016da2 } else { /* A notification was already pending or a notification was received while the task was waiting. */ pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit; 8016d8c: 4b0b ldr r3, [pc, #44] @ (8016dbc ) 8016d8e: 681b ldr r3, [r3, #0] 8016d90: f8d3 10a0 ldr.w r1, [r3, #160] @ 0xa0 8016d94: 68ba ldr r2, [r7, #8] 8016d96: 43d2 mvns r2, r2 8016d98: 400a ands r2, r1 8016d9a: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 xReturn = pdTRUE; 8016d9e: 2301 movs r3, #1 8016da0: 617b str r3, [r7, #20] } pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 8016da2: 4b06 ldr r3, [pc, #24] @ (8016dbc ) 8016da4: 681b ldr r3, [r3, #0] 8016da6: 2200 movs r2, #0 8016da8: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 } taskEXIT_CRITICAL(); 8016dac: f000 ffd6 bl 8017d5c return xReturn; 8016db0: 697b ldr r3, [r7, #20] } 8016db2: 4618 mov r0, r3 8016db4: 3718 adds r7, #24 8016db6: 46bd mov sp, r7 8016db8: bd80 pop {r7, pc} 8016dba: bf00 nop 8016dbc: 240029f8 .word 0x240029f8 8016dc0: e000ed04 .word 0xe000ed04 08016dc4 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) { 8016dc4: b580 push {r7, lr} 8016dc6: b08a sub sp, #40 @ 0x28 8016dc8: af00 add r7, sp, #0 8016dca: 60f8 str r0, [r7, #12] 8016dcc: 60b9 str r1, [r7, #8] 8016dce: 603b str r3, [r7, #0] 8016dd0: 4613 mov r3, r2 8016dd2: 71fb strb r3, [r7, #7] TCB_t * pxTCB; BaseType_t xReturn = pdPASS; 8016dd4: 2301 movs r3, #1 8016dd6: 627b str r3, [r7, #36] @ 0x24 uint8_t ucOriginalNotifyState; configASSERT( xTaskToNotify ); 8016dd8: 68fb ldr r3, [r7, #12] 8016dda: 2b00 cmp r3, #0 8016ddc: d10b bne.n 8016df6 __asm volatile 8016dde: f04f 0350 mov.w r3, #80 @ 0x50 8016de2: f383 8811 msr BASEPRI, r3 8016de6: f3bf 8f6f isb sy 8016dea: f3bf 8f4f dsb sy 8016dee: 61bb str r3, [r7, #24] } 8016df0: bf00 nop 8016df2: bf00 nop 8016df4: e7fd b.n 8016df2 pxTCB = xTaskToNotify; 8016df6: 68fb ldr r3, [r7, #12] 8016df8: 623b str r3, [r7, #32] taskENTER_CRITICAL(); 8016dfa: f000 ff7d bl 8017cf8 { if( pulPreviousNotificationValue != NULL ) 8016dfe: 683b ldr r3, [r7, #0] 8016e00: 2b00 cmp r3, #0 8016e02: d004 beq.n 8016e0e { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016e04: 6a3b ldr r3, [r7, #32] 8016e06: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016e0a: 683b ldr r3, [r7, #0] 8016e0c: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016e0e: 6a3b ldr r3, [r7, #32] 8016e10: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016e14: 77fb strb r3, [r7, #31] pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016e16: 6a3b ldr r3, [r7, #32] 8016e18: 2202 movs r2, #2 8016e1a: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016e1e: 79fb ldrb r3, [r7, #7] 8016e20: 2b04 cmp r3, #4 8016e22: d82e bhi.n 8016e82 8016e24: a201 add r2, pc, #4 @ (adr r2, 8016e2c ) 8016e26: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016e2a: bf00 nop 8016e2c: 08016ea7 .word 0x08016ea7 8016e30: 08016e41 .word 0x08016e41 8016e34: 08016e53 .word 0x08016e53 8016e38: 08016e63 .word 0x08016e63 8016e3c: 08016e6d .word 0x08016e6d { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016e40: 6a3b ldr r3, [r7, #32] 8016e42: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016e46: 68bb ldr r3, [r7, #8] 8016e48: 431a orrs r2, r3 8016e4a: 6a3b ldr r3, [r7, #32] 8016e4c: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e50: e02c b.n 8016eac case eIncrement : ( pxTCB->ulNotifiedValue )++; 8016e52: 6a3b ldr r3, [r7, #32] 8016e54: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016e58: 1c5a adds r2, r3, #1 8016e5a: 6a3b ldr r3, [r7, #32] 8016e5c: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e60: e024 b.n 8016eac case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 8016e62: 6a3b ldr r3, [r7, #32] 8016e64: 68ba ldr r2, [r7, #8] 8016e66: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016e6a: e01f b.n 8016eac case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 8016e6c: 7ffb ldrb r3, [r7, #31] 8016e6e: 2b02 cmp r3, #2 8016e70: d004 beq.n 8016e7c { pxTCB->ulNotifiedValue = ulValue; 8016e72: 6a3b ldr r3, [r7, #32] 8016e74: 68ba ldr r2, [r7, #8] 8016e76: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 8016e7a: e017 b.n 8016eac xReturn = pdFAIL; 8016e7c: 2300 movs r3, #0 8016e7e: 627b str r3, [r7, #36] @ 0x24 break; 8016e80: e014 b.n 8016eac default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 8016e82: 6a3b ldr r3, [r7, #32] 8016e84: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016e88: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8016e8c: d00d beq.n 8016eaa __asm volatile 8016e8e: f04f 0350 mov.w r3, #80 @ 0x50 8016e92: f383 8811 msr BASEPRI, r3 8016e96: f3bf 8f6f isb sy 8016e9a: f3bf 8f4f dsb sy 8016e9e: 617b str r3, [r7, #20] } 8016ea0: bf00 nop 8016ea2: bf00 nop 8016ea4: e7fd b.n 8016ea2 break; 8016ea6: bf00 nop 8016ea8: e000 b.n 8016eac break; 8016eaa: bf00 nop traceTASK_NOTIFY(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 8016eac: 7ffb ldrb r3, [r7, #31] 8016eae: 2b01 cmp r3, #1 8016eb0: d13b bne.n 8016f2a { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8016eb2: 6a3b ldr r3, [r7, #32] 8016eb4: 3304 adds r3, #4 8016eb6: 4618 mov r0, r3 8016eb8: f7fd fd78 bl 80149ac prvAddTaskToReadyList( pxTCB ); 8016ebc: 6a3b ldr r3, [r7, #32] 8016ebe: 6ada ldr r2, [r3, #44] @ 0x2c 8016ec0: 4b1d ldr r3, [pc, #116] @ (8016f38 ) 8016ec2: 681b ldr r3, [r3, #0] 8016ec4: 429a cmp r2, r3 8016ec6: d903 bls.n 8016ed0 8016ec8: 6a3b ldr r3, [r7, #32] 8016eca: 6adb ldr r3, [r3, #44] @ 0x2c 8016ecc: 4a1a ldr r2, [pc, #104] @ (8016f38 ) 8016ece: 6013 str r3, [r2, #0] 8016ed0: 6a3b ldr r3, [r7, #32] 8016ed2: 6ada ldr r2, [r3, #44] @ 0x2c 8016ed4: 4613 mov r3, r2 8016ed6: 009b lsls r3, r3, #2 8016ed8: 4413 add r3, r2 8016eda: 009b lsls r3, r3, #2 8016edc: 4a17 ldr r2, [pc, #92] @ (8016f3c ) 8016ede: 441a add r2, r3 8016ee0: 6a3b ldr r3, [r7, #32] 8016ee2: 3304 adds r3, #4 8016ee4: 4619 mov r1, r3 8016ee6: 4610 mov r0, r2 8016ee8: f7fd fd03 bl 80148f2 /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8016eec: 6a3b ldr r3, [r7, #32] 8016eee: 6a9b ldr r3, [r3, #40] @ 0x28 8016ef0: 2b00 cmp r3, #0 8016ef2: d00b beq.n 8016f0c __asm volatile 8016ef4: f04f 0350 mov.w r3, #80 @ 0x50 8016ef8: f383 8811 msr BASEPRI, r3 8016efc: f3bf 8f6f isb sy 8016f00: f3bf 8f4f dsb sy 8016f04: 613b str r3, [r7, #16] } 8016f06: bf00 nop 8016f08: bf00 nop 8016f0a: e7fd b.n 8016f08 earliest possible time. */ prvResetNextTaskUnblockTime(); } #endif if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 8016f0c: 6a3b ldr r3, [r7, #32] 8016f0e: 6ada ldr r2, [r3, #44] @ 0x2c 8016f10: 4b0b ldr r3, [pc, #44] @ (8016f40 ) 8016f12: 681b ldr r3, [r3, #0] 8016f14: 6adb ldr r3, [r3, #44] @ 0x2c 8016f16: 429a cmp r2, r3 8016f18: d907 bls.n 8016f2a { /* The notified task has a priority above the currently executing task so a yield is required. */ taskYIELD_IF_USING_PREEMPTION(); 8016f1a: 4b0a ldr r3, [pc, #40] @ (8016f44 ) 8016f1c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8016f20: 601a str r2, [r3, #0] 8016f22: f3bf 8f4f dsb sy 8016f26: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8016f2a: f000 ff17 bl 8017d5c return xReturn; 8016f2e: 6a7b ldr r3, [r7, #36] @ 0x24 } 8016f30: 4618 mov r0, r3 8016f32: 3728 adds r7, #40 @ 0x28 8016f34: 46bd mov sp, r7 8016f36: bd80 pop {r7, pc} 8016f38: 24002ed4 .word 0x24002ed4 8016f3c: 240029fc .word 0x240029fc 8016f40: 240029f8 .word 0x240029f8 8016f44: e000ed04 .word 0xe000ed04 08016f48 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) { 8016f48: b580 push {r7, lr} 8016f4a: b08e sub sp, #56 @ 0x38 8016f4c: af00 add r7, sp, #0 8016f4e: 60f8 str r0, [r7, #12] 8016f50: 60b9 str r1, [r7, #8] 8016f52: 603b str r3, [r7, #0] 8016f54: 4613 mov r3, r2 8016f56: 71fb strb r3, [r7, #7] TCB_t * pxTCB; uint8_t ucOriginalNotifyState; BaseType_t xReturn = pdPASS; 8016f58: 2301 movs r3, #1 8016f5a: 637b str r3, [r7, #52] @ 0x34 UBaseType_t uxSavedInterruptStatus; configASSERT( xTaskToNotify ); 8016f5c: 68fb ldr r3, [r7, #12] 8016f5e: 2b00 cmp r3, #0 8016f60: d10b bne.n 8016f7a __asm volatile 8016f62: f04f 0350 mov.w r3, #80 @ 0x50 8016f66: f383 8811 msr BASEPRI, r3 8016f6a: f3bf 8f6f isb sy 8016f6e: f3bf 8f4f dsb sy 8016f72: 627b str r3, [r7, #36] @ 0x24 } 8016f74: bf00 nop 8016f76: bf00 nop 8016f78: e7fd b.n 8016f76 below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8016f7a: f000 ff9d bl 8017eb8 pxTCB = xTaskToNotify; 8016f7e: 68fb ldr r3, [r7, #12] 8016f80: 633b str r3, [r7, #48] @ 0x30 __asm volatile 8016f82: f3ef 8211 mrs r2, BASEPRI 8016f86: f04f 0350 mov.w r3, #80 @ 0x50 8016f8a: f383 8811 msr BASEPRI, r3 8016f8e: f3bf 8f6f isb sy 8016f92: f3bf 8f4f dsb sy 8016f96: 623a str r2, [r7, #32] 8016f98: 61fb str r3, [r7, #28] return ulOriginalBASEPRI; 8016f9a: 6a3b ldr r3, [r7, #32] uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8016f9c: 62fb str r3, [r7, #44] @ 0x2c { if( pulPreviousNotificationValue != NULL ) 8016f9e: 683b ldr r3, [r7, #0] 8016fa0: 2b00 cmp r3, #0 8016fa2: d004 beq.n 8016fae { *pulPreviousNotificationValue = pxTCB->ulNotifiedValue; 8016fa4: 6b3b ldr r3, [r7, #48] @ 0x30 8016fa6: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016faa: 683b ldr r3, [r7, #0] 8016fac: 601a str r2, [r3, #0] } ucOriginalNotifyState = pxTCB->ucNotifyState; 8016fae: 6b3b ldr r3, [r7, #48] @ 0x30 8016fb0: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8016fb4: f887 302b strb.w r3, [r7, #43] @ 0x2b pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED; 8016fb8: 6b3b ldr r3, [r7, #48] @ 0x30 8016fba: 2202 movs r2, #2 8016fbc: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 switch( eAction ) 8016fc0: 79fb ldrb r3, [r7, #7] 8016fc2: 2b04 cmp r3, #4 8016fc4: d82e bhi.n 8017024 8016fc6: a201 add r2, pc, #4 @ (adr r2, 8016fcc ) 8016fc8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8016fcc: 08017049 .word 0x08017049 8016fd0: 08016fe1 .word 0x08016fe1 8016fd4: 08016ff3 .word 0x08016ff3 8016fd8: 08017003 .word 0x08017003 8016fdc: 0801700d .word 0x0801700d { case eSetBits : pxTCB->ulNotifiedValue |= ulValue; 8016fe0: 6b3b ldr r3, [r7, #48] @ 0x30 8016fe2: f8d3 20a0 ldr.w r2, [r3, #160] @ 0xa0 8016fe6: 68bb ldr r3, [r7, #8] 8016fe8: 431a orrs r2, r3 8016fea: 6b3b ldr r3, [r7, #48] @ 0x30 8016fec: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8016ff0: e02d b.n 801704e case eIncrement : ( pxTCB->ulNotifiedValue )++; 8016ff2: 6b3b ldr r3, [r7, #48] @ 0x30 8016ff4: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 8016ff8: 1c5a adds r2, r3, #1 8016ffa: 6b3b ldr r3, [r7, #48] @ 0x30 8016ffc: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 8017000: e025 b.n 801704e case eSetValueWithOverwrite : pxTCB->ulNotifiedValue = ulValue; 8017002: 6b3b ldr r3, [r7, #48] @ 0x30 8017004: 68ba ldr r2, [r7, #8] 8017006: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 break; 801700a: e020 b.n 801704e case eSetValueWithoutOverwrite : if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED ) 801700c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8017010: 2b02 cmp r3, #2 8017012: d004 beq.n 801701e { pxTCB->ulNotifiedValue = ulValue; 8017014: 6b3b ldr r3, [r7, #48] @ 0x30 8017016: 68ba ldr r2, [r7, #8] 8017018: f8c3 20a0 str.w r2, [r3, #160] @ 0xa0 else { /* The value could not be written to the task. */ xReturn = pdFAIL; } break; 801701c: e017 b.n 801704e xReturn = pdFAIL; 801701e: 2300 movs r3, #0 8017020: 637b str r3, [r7, #52] @ 0x34 break; 8017022: e014 b.n 801704e default: /* Should not get here if all enums are handled. Artificially force an assert by testing a value the compiler can't assume is const. */ configASSERT( pxTCB->ulNotifiedValue == ~0UL ); 8017024: 6b3b ldr r3, [r7, #48] @ 0x30 8017026: f8d3 30a0 ldr.w r3, [r3, #160] @ 0xa0 801702a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 801702e: d00d beq.n 801704c __asm volatile 8017030: f04f 0350 mov.w r3, #80 @ 0x50 8017034: f383 8811 msr BASEPRI, r3 8017038: f3bf 8f6f isb sy 801703c: f3bf 8f4f dsb sy 8017040: 61bb str r3, [r7, #24] } 8017042: bf00 nop 8017044: bf00 nop 8017046: e7fd b.n 8017044 break; 8017048: bf00 nop 801704a: e000 b.n 801704e break; 801704c: bf00 nop traceTASK_NOTIFY_FROM_ISR(); /* If the task is in the blocked state specifically to wait for a notification then unblock it now. */ if( ucOriginalNotifyState == taskWAITING_NOTIFICATION ) 801704e: f897 302b ldrb.w r3, [r7, #43] @ 0x2b 8017052: 2b01 cmp r3, #1 8017054: d147 bne.n 80170e6 { /* The task should not have been on an event list. */ configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL ); 8017056: 6b3b ldr r3, [r7, #48] @ 0x30 8017058: 6a9b ldr r3, [r3, #40] @ 0x28 801705a: 2b00 cmp r3, #0 801705c: d00b beq.n 8017076 __asm volatile 801705e: f04f 0350 mov.w r3, #80 @ 0x50 8017062: f383 8811 msr BASEPRI, r3 8017066: f3bf 8f6f isb sy 801706a: f3bf 8f4f dsb sy 801706e: 617b str r3, [r7, #20] } 8017070: bf00 nop 8017072: bf00 nop 8017074: e7fd b.n 8017072 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8017076: 4b21 ldr r3, [pc, #132] @ (80170fc ) 8017078: 681b ldr r3, [r3, #0] 801707a: 2b00 cmp r3, #0 801707c: d11d bne.n 80170ba { ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 801707e: 6b3b ldr r3, [r7, #48] @ 0x30 8017080: 3304 adds r3, #4 8017082: 4618 mov r0, r3 8017084: f7fd fc92 bl 80149ac prvAddTaskToReadyList( pxTCB ); 8017088: 6b3b ldr r3, [r7, #48] @ 0x30 801708a: 6ada ldr r2, [r3, #44] @ 0x2c 801708c: 4b1c ldr r3, [pc, #112] @ (8017100 ) 801708e: 681b ldr r3, [r3, #0] 8017090: 429a cmp r2, r3 8017092: d903 bls.n 801709c 8017094: 6b3b ldr r3, [r7, #48] @ 0x30 8017096: 6adb ldr r3, [r3, #44] @ 0x2c 8017098: 4a19 ldr r2, [pc, #100] @ (8017100 ) 801709a: 6013 str r3, [r2, #0] 801709c: 6b3b ldr r3, [r7, #48] @ 0x30 801709e: 6ada ldr r2, [r3, #44] @ 0x2c 80170a0: 4613 mov r3, r2 80170a2: 009b lsls r3, r3, #2 80170a4: 4413 add r3, r2 80170a6: 009b lsls r3, r3, #2 80170a8: 4a16 ldr r2, [pc, #88] @ (8017104 ) 80170aa: 441a add r2, r3 80170ac: 6b3b ldr r3, [r7, #48] @ 0x30 80170ae: 3304 adds r3, #4 80170b0: 4619 mov r1, r3 80170b2: 4610 mov r0, r2 80170b4: f7fd fc1d bl 80148f2 80170b8: e005 b.n 80170c6 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) ); 80170ba: 6b3b ldr r3, [r7, #48] @ 0x30 80170bc: 3318 adds r3, #24 80170be: 4619 mov r1, r3 80170c0: 4811 ldr r0, [pc, #68] @ (8017108 ) 80170c2: f7fd fc16 bl 80148f2 } if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) 80170c6: 6b3b ldr r3, [r7, #48] @ 0x30 80170c8: 6ada ldr r2, [r3, #44] @ 0x2c 80170ca: 4b10 ldr r3, [pc, #64] @ (801710c ) 80170cc: 681b ldr r3, [r3, #0] 80170ce: 6adb ldr r3, [r3, #44] @ 0x2c 80170d0: 429a cmp r2, r3 80170d2: d908 bls.n 80170e6 { /* The notified task has a priority above the currently executing task so a yield is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80170d4: 6c3b ldr r3, [r7, #64] @ 0x40 80170d6: 2b00 cmp r3, #0 80170d8: d002 beq.n 80170e0 { *pxHigherPriorityTaskWoken = pdTRUE; 80170da: 6c3b ldr r3, [r7, #64] @ 0x40 80170dc: 2201 movs r2, #1 80170de: 601a str r2, [r3, #0] } /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80170e0: 4b0b ldr r3, [pc, #44] @ (8017110 ) 80170e2: 2201 movs r2, #1 80170e4: 601a str r2, [r3, #0] 80170e6: 6afb ldr r3, [r7, #44] @ 0x2c 80170e8: 613b str r3, [r7, #16] __asm volatile 80170ea: 693b ldr r3, [r7, #16] 80170ec: f383 8811 msr BASEPRI, r3 } 80170f0: bf00 nop } } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 80170f2: 6b7b ldr r3, [r7, #52] @ 0x34 } 80170f4: 4618 mov r0, r3 80170f6: 3738 adds r7, #56 @ 0x38 80170f8: 46bd mov sp, r7 80170fa: bd80 pop {r7, pc} 80170fc: 24002ef4 .word 0x24002ef4 8017100: 24002ed4 .word 0x24002ed4 8017104: 240029fc .word 0x240029fc 8017108: 24002e8c .word 0x24002e8c 801710c: 240029f8 .word 0x240029f8 8017110: 24002ee0 .word 0x24002ee0 08017114 : /*-----------------------------------------------------------*/ #if( configUSE_TASK_NOTIFICATIONS == 1 ) BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ) { 8017114: b580 push {r7, lr} 8017116: b084 sub sp, #16 8017118: af00 add r7, sp, #0 801711a: 6078 str r0, [r7, #4] TCB_t *pxTCB; BaseType_t xReturn; /* If null is passed in here then it is the calling task that is having its notification state cleared. */ pxTCB = prvGetTCBFromHandle( xTask ); 801711c: 687b ldr r3, [r7, #4] 801711e: 2b00 cmp r3, #0 8017120: d102 bne.n 8017128 8017122: 4b0e ldr r3, [pc, #56] @ (801715c ) 8017124: 681b ldr r3, [r3, #0] 8017126: e000 b.n 801712a 8017128: 687b ldr r3, [r7, #4] 801712a: 60bb str r3, [r7, #8] taskENTER_CRITICAL(); 801712c: f000 fde4 bl 8017cf8 { if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED ) 8017130: 68bb ldr r3, [r7, #8] 8017132: f893 30a4 ldrb.w r3, [r3, #164] @ 0xa4 8017136: b2db uxtb r3, r3 8017138: 2b02 cmp r3, #2 801713a: d106 bne.n 801714a { pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; 801713c: 68bb ldr r3, [r7, #8] 801713e: 2200 movs r2, #0 8017140: f883 20a4 strb.w r2, [r3, #164] @ 0xa4 xReturn = pdPASS; 8017144: 2301 movs r3, #1 8017146: 60fb str r3, [r7, #12] 8017148: e001 b.n 801714e } else { xReturn = pdFAIL; 801714a: 2300 movs r3, #0 801714c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 801714e: f000 fe05 bl 8017d5c return xReturn; 8017152: 68fb ldr r3, [r7, #12] } 8017154: 4618 mov r0, r3 8017156: 3710 adds r7, #16 8017158: 46bd mov sp, r7 801715a: bd80 pop {r7, pc} 801715c: 240029f8 .word 0x240029f8 08017160 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8017160: b580 push {r7, lr} 8017162: b084 sub sp, #16 8017164: af00 add r7, sp, #0 8017166: 6078 str r0, [r7, #4] 8017168: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 801716a: 4b21 ldr r3, [pc, #132] @ (80171f0 ) 801716c: 681b ldr r3, [r3, #0] 801716e: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8017170: 4b20 ldr r3, [pc, #128] @ (80171f4 ) 8017172: 681b ldr r3, [r3, #0] 8017174: 3304 adds r3, #4 8017176: 4618 mov r0, r3 8017178: f7fd fc18 bl 80149ac mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 801717c: 687b ldr r3, [r7, #4] 801717e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017182: d10a bne.n 801719a 8017184: 683b ldr r3, [r7, #0] 8017186: 2b00 cmp r3, #0 8017188: d007 beq.n 801719a { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 801718a: 4b1a ldr r3, [pc, #104] @ (80171f4 ) 801718c: 681b ldr r3, [r3, #0] 801718e: 3304 adds r3, #4 8017190: 4619 mov r1, r3 8017192: 4819 ldr r0, [pc, #100] @ (80171f8 ) 8017194: f7fd fbad bl 80148f2 /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8017198: e026 b.n 80171e8 xTimeToWake = xConstTickCount + xTicksToWait; 801719a: 68fa ldr r2, [r7, #12] 801719c: 687b ldr r3, [r7, #4] 801719e: 4413 add r3, r2 80171a0: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 80171a2: 4b14 ldr r3, [pc, #80] @ (80171f4 ) 80171a4: 681b ldr r3, [r3, #0] 80171a6: 68ba ldr r2, [r7, #8] 80171a8: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 80171aa: 68ba ldr r2, [r7, #8] 80171ac: 68fb ldr r3, [r7, #12] 80171ae: 429a cmp r2, r3 80171b0: d209 bcs.n 80171c6 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80171b2: 4b12 ldr r3, [pc, #72] @ (80171fc ) 80171b4: 681a ldr r2, [r3, #0] 80171b6: 4b0f ldr r3, [pc, #60] @ (80171f4 ) 80171b8: 681b ldr r3, [r3, #0] 80171ba: 3304 adds r3, #4 80171bc: 4619 mov r1, r3 80171be: 4610 mov r0, r2 80171c0: f7fd fbbb bl 801493a } 80171c4: e010 b.n 80171e8 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 80171c6: 4b0e ldr r3, [pc, #56] @ (8017200 ) 80171c8: 681a ldr r2, [r3, #0] 80171ca: 4b0a ldr r3, [pc, #40] @ (80171f4 ) 80171cc: 681b ldr r3, [r3, #0] 80171ce: 3304 adds r3, #4 80171d0: 4619 mov r1, r3 80171d2: 4610 mov r0, r2 80171d4: f7fd fbb1 bl 801493a if( xTimeToWake < xNextTaskUnblockTime ) 80171d8: 4b0a ldr r3, [pc, #40] @ (8017204 ) 80171da: 681b ldr r3, [r3, #0] 80171dc: 68ba ldr r2, [r7, #8] 80171de: 429a cmp r2, r3 80171e0: d202 bcs.n 80171e8 xNextTaskUnblockTime = xTimeToWake; 80171e2: 4a08 ldr r2, [pc, #32] @ (8017204 ) 80171e4: 68bb ldr r3, [r7, #8] 80171e6: 6013 str r3, [r2, #0] } 80171e8: bf00 nop 80171ea: 3710 adds r7, #16 80171ec: 46bd mov sp, r7 80171ee: bd80 pop {r7, pc} 80171f0: 24002ed0 .word 0x24002ed0 80171f4: 240029f8 .word 0x240029f8 80171f8: 24002eb8 .word 0x24002eb8 80171fc: 24002e88 .word 0x24002e88 8017200: 24002e84 .word 0x24002e84 8017204: 24002eec .word 0x24002eec 08017208 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { 8017208: b580 push {r7, lr} 801720a: b08a sub sp, #40 @ 0x28 801720c: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; 801720e: 2300 movs r3, #0 8017210: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); 8017212: f000 fbb1 bl 8017978 if( xTimerQueue != NULL ) 8017216: 4b1d ldr r3, [pc, #116] @ (801728c ) 8017218: 681b ldr r3, [r3, #0] 801721a: 2b00 cmp r3, #0 801721c: d021 beq.n 8017262 { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; 801721e: 2300 movs r3, #0 8017220: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; 8017222: 2300 movs r3, #0 8017224: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); 8017226: 1d3a adds r2, r7, #4 8017228: f107 0108 add.w r1, r7, #8 801722c: f107 030c add.w r3, r7, #12 8017230: 4618 mov r0, r3 8017232: f7fd fb17 bl 8014864 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, 8017236: 6879 ldr r1, [r7, #4] 8017238: 68bb ldr r3, [r7, #8] 801723a: 68fa ldr r2, [r7, #12] 801723c: 9202 str r2, [sp, #8] 801723e: 9301 str r3, [sp, #4] 8017240: 2302 movs r3, #2 8017242: 9300 str r3, [sp, #0] 8017244: 2300 movs r3, #0 8017246: 460a mov r2, r1 8017248: 4911 ldr r1, [pc, #68] @ (8017290 ) 801724a: 4812 ldr r0, [pc, #72] @ (8017294 ) 801724c: f7fe fd2f bl 8015cae 8017250: 4603 mov r3, r0 8017252: 4a11 ldr r2, [pc, #68] @ (8017298 ) 8017254: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) 8017256: 4b10 ldr r3, [pc, #64] @ (8017298 ) 8017258: 681b ldr r3, [r3, #0] 801725a: 2b00 cmp r3, #0 801725c: d001 beq.n 8017262 { xReturn = pdPASS; 801725e: 2301 movs r3, #1 8017260: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); 8017262: 697b ldr r3, [r7, #20] 8017264: 2b00 cmp r3, #0 8017266: d10b bne.n 8017280 __asm volatile 8017268: f04f 0350 mov.w r3, #80 @ 0x50 801726c: f383 8811 msr BASEPRI, r3 8017270: f3bf 8f6f isb sy 8017274: f3bf 8f4f dsb sy 8017278: 613b str r3, [r7, #16] } 801727a: bf00 nop 801727c: bf00 nop 801727e: e7fd b.n 801727c return xReturn; 8017280: 697b ldr r3, [r7, #20] } 8017282: 4618 mov r0, r3 8017284: 3718 adds r7, #24 8017286: 46bd mov sp, r7 8017288: bd80 pop {r7, pc} 801728a: bf00 nop 801728c: 24002f28 .word 0x24002f28 8017290: 08018698 .word 0x08018698 8017294: 08017511 .word 0x08017511 8017298: 24002f2c .word 0x24002f2c 0801729c : TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) { 801729c: b580 push {r7, lr} 801729e: b088 sub sp, #32 80172a0: af02 add r7, sp, #8 80172a2: 60f8 str r0, [r7, #12] 80172a4: 60b9 str r1, [r7, #8] 80172a6: 607a str r2, [r7, #4] 80172a8: 603b str r3, [r7, #0] Timer_t *pxNewTimer; pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ 80172aa: 202c movs r0, #44 @ 0x2c 80172ac: f000 fe46 bl 8017f3c 80172b0: 6178 str r0, [r7, #20] if( pxNewTimer != NULL ) 80172b2: 697b ldr r3, [r7, #20] 80172b4: 2b00 cmp r3, #0 80172b6: d00d beq.n 80172d4 { /* Status is thus far zero as the timer is not created statically and has not been started. The auto-reload bit may get set in prvInitialiseNewTimer. */ pxNewTimer->ucStatus = 0x00; 80172b8: 697b ldr r3, [r7, #20] 80172ba: 2200 movs r2, #0 80172bc: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 80172c0: 697b ldr r3, [r7, #20] 80172c2: 9301 str r3, [sp, #4] 80172c4: 6a3b ldr r3, [r7, #32] 80172c6: 9300 str r3, [sp, #0] 80172c8: 683b ldr r3, [r7, #0] 80172ca: 687a ldr r2, [r7, #4] 80172cc: 68b9 ldr r1, [r7, #8] 80172ce: 68f8 ldr r0, [r7, #12] 80172d0: f000 f845 bl 801735e } return pxNewTimer; 80172d4: 697b ldr r3, [r7, #20] } 80172d6: 4618 mov r0, r3 80172d8: 3718 adds r7, #24 80172da: 46bd mov sp, r7 80172dc: bd80 pop {r7, pc} 080172de : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) { 80172de: b580 push {r7, lr} 80172e0: b08a sub sp, #40 @ 0x28 80172e2: af02 add r7, sp, #8 80172e4: 60f8 str r0, [r7, #12] 80172e6: 60b9 str r1, [r7, #8] 80172e8: 607a str r2, [r7, #4] 80172ea: 603b str r3, [r7, #0] #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTimer_t equals the size of the real timer structure. */ volatile size_t xSize = sizeof( StaticTimer_t ); 80172ec: 232c movs r3, #44 @ 0x2c 80172ee: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( Timer_t ) ); 80172f0: 693b ldr r3, [r7, #16] 80172f2: 2b2c cmp r3, #44 @ 0x2c 80172f4: d00b beq.n 801730e __asm volatile 80172f6: f04f 0350 mov.w r3, #80 @ 0x50 80172fa: f383 8811 msr BASEPRI, r3 80172fe: f3bf 8f6f isb sy 8017302: f3bf 8f4f dsb sy 8017306: 61bb str r3, [r7, #24] } 8017308: bf00 nop 801730a: bf00 nop 801730c: e7fd b.n 801730a ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ 801730e: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ configASSERT( pxTimerBuffer ); 8017310: 6afb ldr r3, [r7, #44] @ 0x2c 8017312: 2b00 cmp r3, #0 8017314: d10b bne.n 801732e __asm volatile 8017316: f04f 0350 mov.w r3, #80 @ 0x50 801731a: f383 8811 msr BASEPRI, r3 801731e: f3bf 8f6f isb sy 8017322: f3bf 8f4f dsb sy 8017326: 617b str r3, [r7, #20] } 8017328: bf00 nop 801732a: bf00 nop 801732c: e7fd b.n 801732a pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ 801732e: 6afb ldr r3, [r7, #44] @ 0x2c 8017330: 61fb str r3, [r7, #28] if( pxNewTimer != NULL ) 8017332: 69fb ldr r3, [r7, #28] 8017334: 2b00 cmp r3, #0 8017336: d00d beq.n 8017354 { /* Timers can be created statically or dynamically so note this timer was created statically in case it is later deleted. The auto-reload bit may get set in prvInitialiseNewTimer(). */ pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; 8017338: 69fb ldr r3, [r7, #28] 801733a: 2202 movs r2, #2 801733c: f883 2028 strb.w r2, [r3, #40] @ 0x28 prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); 8017340: 69fb ldr r3, [r7, #28] 8017342: 9301 str r3, [sp, #4] 8017344: 6abb ldr r3, [r7, #40] @ 0x28 8017346: 9300 str r3, [sp, #0] 8017348: 683b ldr r3, [r7, #0] 801734a: 687a ldr r2, [r7, #4] 801734c: 68b9 ldr r1, [r7, #8] 801734e: 68f8 ldr r0, [r7, #12] 8017350: f000 f805 bl 801735e } return pxNewTimer; 8017354: 69fb ldr r3, [r7, #28] } 8017356: 4618 mov r0, r3 8017358: 3720 adds r7, #32 801735a: 46bd mov sp, r7 801735c: bd80 pop {r7, pc} 0801735e : const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) { 801735e: b580 push {r7, lr} 8017360: b086 sub sp, #24 8017362: af00 add r7, sp, #0 8017364: 60f8 str r0, [r7, #12] 8017366: 60b9 str r1, [r7, #8] 8017368: 607a str r2, [r7, #4] 801736a: 603b str r3, [r7, #0] /* 0 is not a valid value for xTimerPeriodInTicks. */ configASSERT( ( xTimerPeriodInTicks > 0 ) ); 801736c: 68bb ldr r3, [r7, #8] 801736e: 2b00 cmp r3, #0 8017370: d10b bne.n 801738a __asm volatile 8017372: f04f 0350 mov.w r3, #80 @ 0x50 8017376: f383 8811 msr BASEPRI, r3 801737a: f3bf 8f6f isb sy 801737e: f3bf 8f4f dsb sy 8017382: 617b str r3, [r7, #20] } 8017384: bf00 nop 8017386: bf00 nop 8017388: e7fd b.n 8017386 if( pxNewTimer != NULL ) 801738a: 6a7b ldr r3, [r7, #36] @ 0x24 801738c: 2b00 cmp r3, #0 801738e: d01e beq.n 80173ce { /* Ensure the infrastructure used by the timer service task has been created/initialised. */ prvCheckForValidListAndQueue(); 8017390: f000 faf2 bl 8017978 /* Initialise the timer structure members using the function parameters. */ pxNewTimer->pcTimerName = pcTimerName; 8017394: 6a7b ldr r3, [r7, #36] @ 0x24 8017396: 68fa ldr r2, [r7, #12] 8017398: 601a str r2, [r3, #0] pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; 801739a: 6a7b ldr r3, [r7, #36] @ 0x24 801739c: 68ba ldr r2, [r7, #8] 801739e: 619a str r2, [r3, #24] pxNewTimer->pvTimerID = pvTimerID; 80173a0: 6a7b ldr r3, [r7, #36] @ 0x24 80173a2: 683a ldr r2, [r7, #0] 80173a4: 61da str r2, [r3, #28] pxNewTimer->pxCallbackFunction = pxCallbackFunction; 80173a6: 6a7b ldr r3, [r7, #36] @ 0x24 80173a8: 6a3a ldr r2, [r7, #32] 80173aa: 621a str r2, [r3, #32] vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); 80173ac: 6a7b ldr r3, [r7, #36] @ 0x24 80173ae: 3304 adds r3, #4 80173b0: 4618 mov r0, r3 80173b2: f7fd fa91 bl 80148d8 if( uxAutoReload != pdFALSE ) 80173b6: 687b ldr r3, [r7, #4] 80173b8: 2b00 cmp r3, #0 80173ba: d008 beq.n 80173ce { pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; 80173bc: 6a7b ldr r3, [r7, #36] @ 0x24 80173be: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80173c2: f043 0304 orr.w r3, r3, #4 80173c6: b2da uxtb r2, r3 80173c8: 6a7b ldr r3, [r7, #36] @ 0x24 80173ca: f883 2028 strb.w r2, [r3, #40] @ 0x28 } traceTIMER_CREATE( pxNewTimer ); } } 80173ce: bf00 nop 80173d0: 3718 adds r7, #24 80173d2: 46bd mov sp, r7 80173d4: bd80 pop {r7, pc} ... 080173d8 : /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { 80173d8: b580 push {r7, lr} 80173da: b08a sub sp, #40 @ 0x28 80173dc: af00 add r7, sp, #0 80173de: 60f8 str r0, [r7, #12] 80173e0: 60b9 str r1, [r7, #8] 80173e2: 607a str r2, [r7, #4] 80173e4: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; 80173e6: 2300 movs r3, #0 80173e8: 627b str r3, [r7, #36] @ 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); 80173ea: 68fb ldr r3, [r7, #12] 80173ec: 2b00 cmp r3, #0 80173ee: d10b bne.n 8017408 __asm volatile 80173f0: f04f 0350 mov.w r3, #80 @ 0x50 80173f4: f383 8811 msr BASEPRI, r3 80173f8: f3bf 8f6f isb sy 80173fc: f3bf 8f4f dsb sy 8017400: 623b str r3, [r7, #32] } 8017402: bf00 nop 8017404: bf00 nop 8017406: e7fd b.n 8017404 /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) 8017408: 4b19 ldr r3, [pc, #100] @ (8017470 ) 801740a: 681b ldr r3, [r3, #0] 801740c: 2b00 cmp r3, #0 801740e: d02a beq.n 8017466 { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; 8017410: 68bb ldr r3, [r7, #8] 8017412: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; 8017414: 687b ldr r3, [r7, #4] 8017416: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; 8017418: 68fb ldr r3, [r7, #12] 801741a: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) 801741c: 68bb ldr r3, [r7, #8] 801741e: 2b05 cmp r3, #5 8017420: dc18 bgt.n 8017454 { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) 8017422: f7ff fae1 bl 80169e8 8017426: 4603 mov r3, r0 8017428: 2b02 cmp r3, #2 801742a: d109 bne.n 8017440 { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); 801742c: 4b10 ldr r3, [pc, #64] @ (8017470 ) 801742e: 6818 ldr r0, [r3, #0] 8017430: f107 0110 add.w r1, r7, #16 8017434: 2300 movs r3, #0 8017436: 6b3a ldr r2, [r7, #48] @ 0x30 8017438: f7fd fce0 bl 8014dfc 801743c: 6278 str r0, [r7, #36] @ 0x24 801743e: e012 b.n 8017466 } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); 8017440: 4b0b ldr r3, [pc, #44] @ (8017470 ) 8017442: 6818 ldr r0, [r3, #0] 8017444: f107 0110 add.w r1, r7, #16 8017448: 2300 movs r3, #0 801744a: 2200 movs r2, #0 801744c: f7fd fcd6 bl 8014dfc 8017450: 6278 str r0, [r7, #36] @ 0x24 8017452: e008 b.n 8017466 } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); 8017454: 4b06 ldr r3, [pc, #24] @ (8017470 ) 8017456: 6818 ldr r0, [r3, #0] 8017458: f107 0110 add.w r1, r7, #16 801745c: 2300 movs r3, #0 801745e: 683a ldr r2, [r7, #0] 8017460: f7fd fdce bl 8015000 8017464: 6278 str r0, [r7, #36] @ 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8017466: 6a7b ldr r3, [r7, #36] @ 0x24 } 8017468: 4618 mov r0, r3 801746a: 3728 adds r7, #40 @ 0x28 801746c: 46bd mov sp, r7 801746e: bd80 pop {r7, pc} 8017470: 24002f28 .word 0x24002f28 08017474 : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { 8017474: b580 push {r7, lr} 8017476: b088 sub sp, #32 8017478: af02 add r7, sp, #8 801747a: 6078 str r0, [r7, #4] 801747c: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 801747e: 4b23 ldr r3, [pc, #140] @ (801750c ) 8017480: 681b ldr r3, [r3, #0] 8017482: 68db ldr r3, [r3, #12] 8017484: 68db ldr r3, [r3, #12] 8017486: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8017488: 697b ldr r3, [r7, #20] 801748a: 3304 adds r3, #4 801748c: 4618 mov r0, r3 801748e: f7fd fa8d bl 80149ac traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 8017492: 697b ldr r3, [r7, #20] 8017494: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017498: f003 0304 and.w r3, r3, #4 801749c: 2b00 cmp r3, #0 801749e: d023 beq.n 80174e8 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) 80174a0: 697b ldr r3, [r7, #20] 80174a2: 699a ldr r2, [r3, #24] 80174a4: 687b ldr r3, [r7, #4] 80174a6: 18d1 adds r1, r2, r3 80174a8: 687b ldr r3, [r7, #4] 80174aa: 683a ldr r2, [r7, #0] 80174ac: 6978 ldr r0, [r7, #20] 80174ae: f000 f8d5 bl 801765c 80174b2: 4603 mov r3, r0 80174b4: 2b00 cmp r3, #0 80174b6: d020 beq.n 80174fa { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 80174b8: 2300 movs r3, #0 80174ba: 9300 str r3, [sp, #0] 80174bc: 2300 movs r3, #0 80174be: 687a ldr r2, [r7, #4] 80174c0: 2100 movs r1, #0 80174c2: 6978 ldr r0, [r7, #20] 80174c4: f7ff ff88 bl 80173d8 80174c8: 6138 str r0, [r7, #16] configASSERT( xResult ); 80174ca: 693b ldr r3, [r7, #16] 80174cc: 2b00 cmp r3, #0 80174ce: d114 bne.n 80174fa __asm volatile 80174d0: f04f 0350 mov.w r3, #80 @ 0x50 80174d4: f383 8811 msr BASEPRI, r3 80174d8: f3bf 8f6f isb sy 80174dc: f3bf 8f4f dsb sy 80174e0: 60fb str r3, [r7, #12] } 80174e2: bf00 nop 80174e4: bf00 nop 80174e6: e7fd b.n 80174e4 mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80174e8: 697b ldr r3, [r7, #20] 80174ea: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80174ee: f023 0301 bic.w r3, r3, #1 80174f2: b2da uxtb r2, r3 80174f4: 697b ldr r3, [r7, #20] 80174f6: f883 2028 strb.w r2, [r3, #40] @ 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80174fa: 697b ldr r3, [r7, #20] 80174fc: 6a1b ldr r3, [r3, #32] 80174fe: 6978 ldr r0, [r7, #20] 8017500: 4798 blx r3 } 8017502: bf00 nop 8017504: 3718 adds r7, #24 8017506: 46bd mov sp, r7 8017508: bd80 pop {r7, pc} 801750a: bf00 nop 801750c: 24002f20 .word 0x24002f20 08017510 : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { 8017510: b580 push {r7, lr} 8017512: b084 sub sp, #16 8017514: af00 add r7, sp, #0 8017516: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8017518: f107 0308 add.w r3, r7, #8 801751c: 4618 mov r0, r3 801751e: f000 f859 bl 80175d4 8017522: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); 8017524: 68bb ldr r3, [r7, #8] 8017526: 4619 mov r1, r3 8017528: 68f8 ldr r0, [r7, #12] 801752a: f000 f805 bl 8017538 /* Empty the command queue. */ prvProcessReceivedCommands(); 801752e: f000 f8d7 bl 80176e0 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); 8017532: bf00 nop 8017534: e7f0 b.n 8017518 ... 08017538 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { 8017538: b580 push {r7, lr} 801753a: b084 sub sp, #16 801753c: af00 add r7, sp, #0 801753e: 6078 str r0, [r7, #4] 8017540: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); 8017542: f7fe fe17 bl 8016174 /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8017546: f107 0308 add.w r3, r7, #8 801754a: 4618 mov r0, r3 801754c: f000 f866 bl 801761c 8017550: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) 8017552: 68bb ldr r3, [r7, #8] 8017554: 2b00 cmp r3, #0 8017556: d130 bne.n 80175ba { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) 8017558: 683b ldr r3, [r7, #0] 801755a: 2b00 cmp r3, #0 801755c: d10a bne.n 8017574 801755e: 687a ldr r2, [r7, #4] 8017560: 68fb ldr r3, [r7, #12] 8017562: 429a cmp r2, r3 8017564: d806 bhi.n 8017574 { ( void ) xTaskResumeAll(); 8017566: f7fe fe13 bl 8016190 prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); 801756a: 68f9 ldr r1, [r7, #12] 801756c: 6878 ldr r0, [r7, #4] 801756e: f7ff ff81 bl 8017474 else { ( void ) xTaskResumeAll(); } } } 8017572: e024 b.n 80175be if( xListWasEmpty != pdFALSE ) 8017574: 683b ldr r3, [r7, #0] 8017576: 2b00 cmp r3, #0 8017578: d008 beq.n 801758c xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); 801757a: 4b13 ldr r3, [pc, #76] @ (80175c8 ) 801757c: 681b ldr r3, [r3, #0] 801757e: 681b ldr r3, [r3, #0] 8017580: 2b00 cmp r3, #0 8017582: d101 bne.n 8017588 8017584: 2301 movs r3, #1 8017586: e000 b.n 801758a 8017588: 2300 movs r3, #0 801758a: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); 801758c: 4b0f ldr r3, [pc, #60] @ (80175cc ) 801758e: 6818 ldr r0, [r3, #0] 8017590: 687a ldr r2, [r7, #4] 8017592: 68fb ldr r3, [r7, #12] 8017594: 1ad3 subs r3, r2, r3 8017596: 683a ldr r2, [r7, #0] 8017598: 4619 mov r1, r3 801759a: f7fe f995 bl 80158c8 if( xTaskResumeAll() == pdFALSE ) 801759e: f7fe fdf7 bl 8016190 80175a2: 4603 mov r3, r0 80175a4: 2b00 cmp r3, #0 80175a6: d10a bne.n 80175be portYIELD_WITHIN_API(); 80175a8: 4b09 ldr r3, [pc, #36] @ (80175d0 ) 80175aa: f04f 5280 mov.w r2, #268435456 @ 0x10000000 80175ae: 601a str r2, [r3, #0] 80175b0: f3bf 8f4f dsb sy 80175b4: f3bf 8f6f isb sy } 80175b8: e001 b.n 80175be ( void ) xTaskResumeAll(); 80175ba: f7fe fde9 bl 8016190 } 80175be: bf00 nop 80175c0: 3710 adds r7, #16 80175c2: 46bd mov sp, r7 80175c4: bd80 pop {r7, pc} 80175c6: bf00 nop 80175c8: 24002f24 .word 0x24002f24 80175cc: 24002f28 .word 0x24002f28 80175d0: e000ed04 .word 0xe000ed04 080175d4 : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { 80175d4: b480 push {r7} 80175d6: b085 sub sp, #20 80175d8: af00 add r7, sp, #0 80175da: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); 80175dc: 4b0e ldr r3, [pc, #56] @ (8017618 ) 80175de: 681b ldr r3, [r3, #0] 80175e0: 681b ldr r3, [r3, #0] 80175e2: 2b00 cmp r3, #0 80175e4: d101 bne.n 80175ea 80175e6: 2201 movs r2, #1 80175e8: e000 b.n 80175ec 80175ea: 2200 movs r2, #0 80175ec: 687b ldr r3, [r7, #4] 80175ee: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) 80175f0: 687b ldr r3, [r7, #4] 80175f2: 681b ldr r3, [r3, #0] 80175f4: 2b00 cmp r3, #0 80175f6: d105 bne.n 8017604 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 80175f8: 4b07 ldr r3, [pc, #28] @ (8017618 ) 80175fa: 681b ldr r3, [r3, #0] 80175fc: 68db ldr r3, [r3, #12] 80175fe: 681b ldr r3, [r3, #0] 8017600: 60fb str r3, [r7, #12] 8017602: e001 b.n 8017608 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; 8017604: 2300 movs r3, #0 8017606: 60fb str r3, [r7, #12] } return xNextExpireTime; 8017608: 68fb ldr r3, [r7, #12] } 801760a: 4618 mov r0, r3 801760c: 3714 adds r7, #20 801760e: 46bd mov sp, r7 8017610: f85d 7b04 ldr.w r7, [sp], #4 8017614: 4770 bx lr 8017616: bf00 nop 8017618: 24002f20 .word 0x24002f20 0801761c : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { 801761c: b580 push {r7, lr} 801761e: b084 sub sp, #16 8017620: af00 add r7, sp, #0 8017622: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); 8017624: f7fe fe52 bl 80162cc 8017628: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) 801762a: 4b0b ldr r3, [pc, #44] @ (8017658 ) 801762c: 681b ldr r3, [r3, #0] 801762e: 68fa ldr r2, [r7, #12] 8017630: 429a cmp r2, r3 8017632: d205 bcs.n 8017640 { prvSwitchTimerLists(); 8017634: f000 f93a bl 80178ac *pxTimerListsWereSwitched = pdTRUE; 8017638: 687b ldr r3, [r7, #4] 801763a: 2201 movs r2, #1 801763c: 601a str r2, [r3, #0] 801763e: e002 b.n 8017646 } else { *pxTimerListsWereSwitched = pdFALSE; 8017640: 687b ldr r3, [r7, #4] 8017642: 2200 movs r2, #0 8017644: 601a str r2, [r3, #0] } xLastTime = xTimeNow; 8017646: 4a04 ldr r2, [pc, #16] @ (8017658 ) 8017648: 68fb ldr r3, [r7, #12] 801764a: 6013 str r3, [r2, #0] return xTimeNow; 801764c: 68fb ldr r3, [r7, #12] } 801764e: 4618 mov r0, r3 8017650: 3710 adds r7, #16 8017652: 46bd mov sp, r7 8017654: bd80 pop {r7, pc} 8017656: bf00 nop 8017658: 24002f30 .word 0x24002f30 0801765c : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { 801765c: b580 push {r7, lr} 801765e: b086 sub sp, #24 8017660: af00 add r7, sp, #0 8017662: 60f8 str r0, [r7, #12] 8017664: 60b9 str r1, [r7, #8] 8017666: 607a str r2, [r7, #4] 8017668: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; 801766a: 2300 movs r3, #0 801766c: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); 801766e: 68fb ldr r3, [r7, #12] 8017670: 68ba ldr r2, [r7, #8] 8017672: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8017674: 68fb ldr r3, [r7, #12] 8017676: 68fa ldr r2, [r7, #12] 8017678: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) 801767a: 68ba ldr r2, [r7, #8] 801767c: 687b ldr r3, [r7, #4] 801767e: 429a cmp r2, r3 8017680: d812 bhi.n 80176a8 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8017682: 687a ldr r2, [r7, #4] 8017684: 683b ldr r3, [r7, #0] 8017686: 1ad2 subs r2, r2, r3 8017688: 68fb ldr r3, [r7, #12] 801768a: 699b ldr r3, [r3, #24] 801768c: 429a cmp r2, r3 801768e: d302 bcc.n 8017696 { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; 8017690: 2301 movs r3, #1 8017692: 617b str r3, [r7, #20] 8017694: e01b b.n 80176ce } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); 8017696: 4b10 ldr r3, [pc, #64] @ (80176d8 ) 8017698: 681a ldr r2, [r3, #0] 801769a: 68fb ldr r3, [r7, #12] 801769c: 3304 adds r3, #4 801769e: 4619 mov r1, r3 80176a0: 4610 mov r0, r2 80176a2: f7fd f94a bl 801493a 80176a6: e012 b.n 80176ce } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) 80176a8: 687a ldr r2, [r7, #4] 80176aa: 683b ldr r3, [r7, #0] 80176ac: 429a cmp r2, r3 80176ae: d206 bcs.n 80176be 80176b0: 68ba ldr r2, [r7, #8] 80176b2: 683b ldr r3, [r7, #0] 80176b4: 429a cmp r2, r3 80176b6: d302 bcc.n 80176be { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; 80176b8: 2301 movs r3, #1 80176ba: 617b str r3, [r7, #20] 80176bc: e007 b.n 80176ce } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 80176be: 4b07 ldr r3, [pc, #28] @ (80176dc ) 80176c0: 681a ldr r2, [r3, #0] 80176c2: 68fb ldr r3, [r7, #12] 80176c4: 3304 adds r3, #4 80176c6: 4619 mov r1, r3 80176c8: 4610 mov r0, r2 80176ca: f7fd f936 bl 801493a } } return xProcessTimerNow; 80176ce: 697b ldr r3, [r7, #20] } 80176d0: 4618 mov r0, r3 80176d2: 3718 adds r7, #24 80176d4: 46bd mov sp, r7 80176d6: bd80 pop {r7, pc} 80176d8: 24002f24 .word 0x24002f24 80176dc: 24002f20 .word 0x24002f20 080176e0 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { 80176e0: b580 push {r7, lr} 80176e2: b08e sub sp, #56 @ 0x38 80176e4: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 80176e6: e0ce b.n 8017886 { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) 80176e8: 687b ldr r3, [r7, #4] 80176ea: 2b00 cmp r3, #0 80176ec: da19 bge.n 8017722 { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); 80176ee: 1d3b adds r3, r7, #4 80176f0: 3304 adds r3, #4 80176f2: 62fb str r3, [r7, #44] @ 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); 80176f4: 6afb ldr r3, [r7, #44] @ 0x2c 80176f6: 2b00 cmp r3, #0 80176f8: d10b bne.n 8017712 __asm volatile 80176fa: f04f 0350 mov.w r3, #80 @ 0x50 80176fe: f383 8811 msr BASEPRI, r3 8017702: f3bf 8f6f isb sy 8017706: f3bf 8f4f dsb sy 801770a: 61fb str r3, [r7, #28] } 801770c: bf00 nop 801770e: bf00 nop 8017710: e7fd b.n 801770e /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); 8017712: 6afb ldr r3, [r7, #44] @ 0x2c 8017714: 681b ldr r3, [r3, #0] 8017716: 6afa ldr r2, [r7, #44] @ 0x2c 8017718: 6850 ldr r0, [r2, #4] 801771a: 6afa ldr r2, [r7, #44] @ 0x2c 801771c: 6892 ldr r2, [r2, #8] 801771e: 4611 mov r1, r2 8017720: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) 8017722: 687b ldr r3, [r7, #4] 8017724: 2b00 cmp r3, #0 8017726: f2c0 80ae blt.w 8017886 { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; 801772a: 68fb ldr r3, [r7, #12] 801772c: 62bb str r3, [r7, #40] @ 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ 801772e: 6abb ldr r3, [r7, #40] @ 0x28 8017730: 695b ldr r3, [r3, #20] 8017732: 2b00 cmp r3, #0 8017734: d004 beq.n 8017740 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 8017736: 6abb ldr r3, [r7, #40] @ 0x28 8017738: 3304 adds r3, #4 801773a: 4618 mov r0, r3 801773c: f7fd f936 bl 80149ac it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); 8017740: 463b mov r3, r7 8017742: 4618 mov r0, r3 8017744: f7ff ff6a bl 801761c 8017748: 6278 str r0, [r7, #36] @ 0x24 switch( xMessage.xMessageID ) 801774a: 687b ldr r3, [r7, #4] 801774c: 2b09 cmp r3, #9 801774e: f200 8097 bhi.w 8017880 8017752: a201 add r2, pc, #4 @ (adr r2, 8017758 ) 8017754: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8017758: 08017781 .word 0x08017781 801775c: 08017781 .word 0x08017781 8017760: 08017781 .word 0x08017781 8017764: 080177f7 .word 0x080177f7 8017768: 0801780b .word 0x0801780b 801776c: 08017857 .word 0x08017857 8017770: 08017781 .word 0x08017781 8017774: 08017781 .word 0x08017781 8017778: 080177f7 .word 0x080177f7 801777c: 0801780b .word 0x0801780b case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 8017780: 6abb ldr r3, [r7, #40] @ 0x28 8017782: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017786: f043 0301 orr.w r3, r3, #1 801778a: b2da uxtb r2, r3 801778c: 6abb ldr r3, [r7, #40] @ 0x28 801778e: f883 2028 strb.w r2, [r3, #40] @ 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) 8017792: 68ba ldr r2, [r7, #8] 8017794: 6abb ldr r3, [r7, #40] @ 0x28 8017796: 699b ldr r3, [r3, #24] 8017798: 18d1 adds r1, r2, r3 801779a: 68bb ldr r3, [r7, #8] 801779c: 6a7a ldr r2, [r7, #36] @ 0x24 801779e: 6ab8 ldr r0, [r7, #40] @ 0x28 80177a0: f7ff ff5c bl 801765c 80177a4: 4603 mov r3, r0 80177a6: 2b00 cmp r3, #0 80177a8: d06c beq.n 8017884 { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80177aa: 6abb ldr r3, [r7, #40] @ 0x28 80177ac: 6a1b ldr r3, [r3, #32] 80177ae: 6ab8 ldr r0, [r7, #40] @ 0x28 80177b0: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80177b2: 6abb ldr r3, [r7, #40] @ 0x28 80177b4: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80177b8: f003 0304 and.w r3, r3, #4 80177bc: 2b00 cmp r3, #0 80177be: d061 beq.n 8017884 { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); 80177c0: 68ba ldr r2, [r7, #8] 80177c2: 6abb ldr r3, [r7, #40] @ 0x28 80177c4: 699b ldr r3, [r3, #24] 80177c6: 441a add r2, r3 80177c8: 2300 movs r3, #0 80177ca: 9300 str r3, [sp, #0] 80177cc: 2300 movs r3, #0 80177ce: 2100 movs r1, #0 80177d0: 6ab8 ldr r0, [r7, #40] @ 0x28 80177d2: f7ff fe01 bl 80173d8 80177d6: 6238 str r0, [r7, #32] configASSERT( xResult ); 80177d8: 6a3b ldr r3, [r7, #32] 80177da: 2b00 cmp r3, #0 80177dc: d152 bne.n 8017884 __asm volatile 80177de: f04f 0350 mov.w r3, #80 @ 0x50 80177e2: f383 8811 msr BASEPRI, r3 80177e6: f3bf 8f6f isb sy 80177ea: f3bf 8f4f dsb sy 80177ee: 61bb str r3, [r7, #24] } 80177f0: bf00 nop 80177f2: bf00 nop 80177f4: e7fd b.n 80177f2 break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 80177f6: 6abb ldr r3, [r7, #40] @ 0x28 80177f8: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80177fc: f023 0301 bic.w r3, r3, #1 8017800: b2da uxtb r2, r3 8017802: 6abb ldr r3, [r7, #40] @ 0x28 8017804: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 8017808: e03d b.n 8017886 case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; 801780a: 6abb ldr r3, [r7, #40] @ 0x28 801780c: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017810: f043 0301 orr.w r3, r3, #1 8017814: b2da uxtb r2, r3 8017816: 6abb ldr r3, [r7, #40] @ 0x28 8017818: f883 2028 strb.w r2, [r3, #40] @ 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; 801781c: 68ba ldr r2, [r7, #8] 801781e: 6abb ldr r3, [r7, #40] @ 0x28 8017820: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); 8017822: 6abb ldr r3, [r7, #40] @ 0x28 8017824: 699b ldr r3, [r3, #24] 8017826: 2b00 cmp r3, #0 8017828: d10b bne.n 8017842 __asm volatile 801782a: f04f 0350 mov.w r3, #80 @ 0x50 801782e: f383 8811 msr BASEPRI, r3 8017832: f3bf 8f6f isb sy 8017836: f3bf 8f4f dsb sy 801783a: 617b str r3, [r7, #20] } 801783c: bf00 nop 801783e: bf00 nop 8017840: e7fd b.n 801783e be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); 8017842: 6abb ldr r3, [r7, #40] @ 0x28 8017844: 699a ldr r2, [r3, #24] 8017846: 6a7b ldr r3, [r7, #36] @ 0x24 8017848: 18d1 adds r1, r2, r3 801784a: 6a7b ldr r3, [r7, #36] @ 0x24 801784c: 6a7a ldr r2, [r7, #36] @ 0x24 801784e: 6ab8 ldr r0, [r7, #40] @ 0x28 8017850: f7ff ff04 bl 801765c break; 8017854: e017 b.n 8017886 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) 8017856: 6abb ldr r3, [r7, #40] @ 0x28 8017858: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 801785c: f003 0302 and.w r3, r3, #2 8017860: 2b00 cmp r3, #0 8017862: d103 bne.n 801786c { vPortFree( pxTimer ); 8017864: 6ab8 ldr r0, [r7, #40] @ 0x28 8017866: f000 fc37 bl 80180d8 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; 801786a: e00c b.n 8017886 pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; 801786c: 6abb ldr r3, [r7, #40] @ 0x28 801786e: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017872: f023 0301 bic.w r3, r3, #1 8017876: b2da uxtb r2, r3 8017878: 6abb ldr r3, [r7, #40] @ 0x28 801787a: f883 2028 strb.w r2, [r3, #40] @ 0x28 break; 801787e: e002 b.n 8017886 default : /* Don't expect to get here. */ break; 8017880: bf00 nop 8017882: e000 b.n 8017886 break; 8017884: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ 8017886: 4b08 ldr r3, [pc, #32] @ (80178a8 ) 8017888: 681b ldr r3, [r3, #0] 801788a: 1d39 adds r1, r7, #4 801788c: 2200 movs r2, #0 801788e: 4618 mov r0, r3 8017890: f7fd fc54 bl 801513c 8017894: 4603 mov r3, r0 8017896: 2b00 cmp r3, #0 8017898: f47f af26 bne.w 80176e8 } } } } 801789c: bf00 nop 801789e: bf00 nop 80178a0: 3730 adds r7, #48 @ 0x30 80178a2: 46bd mov sp, r7 80178a4: bd80 pop {r7, pc} 80178a6: bf00 nop 80178a8: 24002f28 .word 0x24002f28 080178ac : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { 80178ac: b580 push {r7, lr} 80178ae: b088 sub sp, #32 80178b0: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 80178b2: e049 b.n 8017948 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); 80178b4: 4b2e ldr r3, [pc, #184] @ (8017970 ) 80178b6: 681b ldr r3, [r3, #0] 80178b8: 68db ldr r3, [r3, #12] 80178ba: 681b ldr r3, [r3, #0] 80178bc: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80178be: 4b2c ldr r3, [pc, #176] @ (8017970 ) 80178c0: 681b ldr r3, [r3, #0] 80178c2: 68db ldr r3, [r3, #12] 80178c4: 68db ldr r3, [r3, #12] 80178c6: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); 80178c8: 68fb ldr r3, [r7, #12] 80178ca: 3304 adds r3, #4 80178cc: 4618 mov r0, r3 80178ce: f7fd f86d bl 80149ac traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); 80178d2: 68fb ldr r3, [r7, #12] 80178d4: 6a1b ldr r3, [r3, #32] 80178d6: 68f8 ldr r0, [r7, #12] 80178d8: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) 80178da: 68fb ldr r3, [r7, #12] 80178dc: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 80178e0: f003 0304 and.w r3, r3, #4 80178e4: 2b00 cmp r3, #0 80178e6: d02f beq.n 8017948 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); 80178e8: 68fb ldr r3, [r7, #12] 80178ea: 699b ldr r3, [r3, #24] 80178ec: 693a ldr r2, [r7, #16] 80178ee: 4413 add r3, r2 80178f0: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) 80178f2: 68ba ldr r2, [r7, #8] 80178f4: 693b ldr r3, [r7, #16] 80178f6: 429a cmp r2, r3 80178f8: d90e bls.n 8017918 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); 80178fa: 68fb ldr r3, [r7, #12] 80178fc: 68ba ldr r2, [r7, #8] 80178fe: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); 8017900: 68fb ldr r3, [r7, #12] 8017902: 68fa ldr r2, [r7, #12] 8017904: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); 8017906: 4b1a ldr r3, [pc, #104] @ (8017970 ) 8017908: 681a ldr r2, [r3, #0] 801790a: 68fb ldr r3, [r7, #12] 801790c: 3304 adds r3, #4 801790e: 4619 mov r1, r3 8017910: 4610 mov r0, r2 8017912: f7fd f812 bl 801493a 8017916: e017 b.n 8017948 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); 8017918: 2300 movs r3, #0 801791a: 9300 str r3, [sp, #0] 801791c: 2300 movs r3, #0 801791e: 693a ldr r2, [r7, #16] 8017920: 2100 movs r1, #0 8017922: 68f8 ldr r0, [r7, #12] 8017924: f7ff fd58 bl 80173d8 8017928: 6078 str r0, [r7, #4] configASSERT( xResult ); 801792a: 687b ldr r3, [r7, #4] 801792c: 2b00 cmp r3, #0 801792e: d10b bne.n 8017948 __asm volatile 8017930: f04f 0350 mov.w r3, #80 @ 0x50 8017934: f383 8811 msr BASEPRI, r3 8017938: f3bf 8f6f isb sy 801793c: f3bf 8f4f dsb sy 8017940: 603b str r3, [r7, #0] } 8017942: bf00 nop 8017944: bf00 nop 8017946: e7fd b.n 8017944 while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) 8017948: 4b09 ldr r3, [pc, #36] @ (8017970 ) 801794a: 681b ldr r3, [r3, #0] 801794c: 681b ldr r3, [r3, #0] 801794e: 2b00 cmp r3, #0 8017950: d1b0 bne.n 80178b4 { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; 8017952: 4b07 ldr r3, [pc, #28] @ (8017970 ) 8017954: 681b ldr r3, [r3, #0] 8017956: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; 8017958: 4b06 ldr r3, [pc, #24] @ (8017974 ) 801795a: 681b ldr r3, [r3, #0] 801795c: 4a04 ldr r2, [pc, #16] @ (8017970 ) 801795e: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; 8017960: 4a04 ldr r2, [pc, #16] @ (8017974 ) 8017962: 697b ldr r3, [r7, #20] 8017964: 6013 str r3, [r2, #0] } 8017966: bf00 nop 8017968: 3718 adds r7, #24 801796a: 46bd mov sp, r7 801796c: bd80 pop {r7, pc} 801796e: bf00 nop 8017970: 24002f20 .word 0x24002f20 8017974: 24002f24 .word 0x24002f24 08017978 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { 8017978: b580 push {r7, lr} 801797a: b082 sub sp, #8 801797c: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); 801797e: f000 f9bb bl 8017cf8 { if( xTimerQueue == NULL ) 8017982: 4b15 ldr r3, [pc, #84] @ (80179d8 ) 8017984: 681b ldr r3, [r3, #0] 8017986: 2b00 cmp r3, #0 8017988: d120 bne.n 80179cc { vListInitialise( &xActiveTimerList1 ); 801798a: 4814 ldr r0, [pc, #80] @ (80179dc ) 801798c: f7fc ff84 bl 8014898 vListInitialise( &xActiveTimerList2 ); 8017990: 4813 ldr r0, [pc, #76] @ (80179e0 ) 8017992: f7fc ff81 bl 8014898 pxCurrentTimerList = &xActiveTimerList1; 8017996: 4b13 ldr r3, [pc, #76] @ (80179e4 ) 8017998: 4a10 ldr r2, [pc, #64] @ (80179dc ) 801799a: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; 801799c: 4b12 ldr r3, [pc, #72] @ (80179e8 ) 801799e: 4a10 ldr r2, [pc, #64] @ (80179e0 ) 80179a0: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); 80179a2: 2300 movs r3, #0 80179a4: 9300 str r3, [sp, #0] 80179a6: 4b11 ldr r3, [pc, #68] @ (80179ec ) 80179a8: 4a11 ldr r2, [pc, #68] @ (80179f0 ) 80179aa: 2110 movs r1, #16 80179ac: 200a movs r0, #10 80179ae: f7fd f891 bl 8014ad4 80179b2: 4603 mov r3, r0 80179b4: 4a08 ldr r2, [pc, #32] @ (80179d8 ) 80179b6: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) 80179b8: 4b07 ldr r3, [pc, #28] @ (80179d8 ) 80179ba: 681b ldr r3, [r3, #0] 80179bc: 2b00 cmp r3, #0 80179be: d005 beq.n 80179cc { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); 80179c0: 4b05 ldr r3, [pc, #20] @ (80179d8 ) 80179c2: 681b ldr r3, [r3, #0] 80179c4: 490b ldr r1, [pc, #44] @ (80179f4 ) 80179c6: 4618 mov r0, r3 80179c8: f7fd ff54 bl 8015874 else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 80179cc: f000 f9c6 bl 8017d5c } 80179d0: bf00 nop 80179d2: 46bd mov sp, r7 80179d4: bd80 pop {r7, pc} 80179d6: bf00 nop 80179d8: 24002f28 .word 0x24002f28 80179dc: 24002ef8 .word 0x24002ef8 80179e0: 24002f0c .word 0x24002f0c 80179e4: 24002f20 .word 0x24002f20 80179e8: 24002f24 .word 0x24002f24 80179ec: 24002fd4 .word 0x24002fd4 80179f0: 24002f34 .word 0x24002f34 80179f4: 080186a0 .word 0x080186a0 080179f8 : /*-----------------------------------------------------------*/ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) { 80179f8: b580 push {r7, lr} 80179fa: b086 sub sp, #24 80179fc: af00 add r7, sp, #0 80179fe: 6078 str r0, [r7, #4] BaseType_t xReturn; Timer_t *pxTimer = xTimer; 8017a00: 687b ldr r3, [r7, #4] 8017a02: 613b str r3, [r7, #16] configASSERT( xTimer ); 8017a04: 687b ldr r3, [r7, #4] 8017a06: 2b00 cmp r3, #0 8017a08: d10b bne.n 8017a22 __asm volatile 8017a0a: f04f 0350 mov.w r3, #80 @ 0x50 8017a0e: f383 8811 msr BASEPRI, r3 8017a12: f3bf 8f6f isb sy 8017a16: f3bf 8f4f dsb sy 8017a1a: 60fb str r3, [r7, #12] } 8017a1c: bf00 nop 8017a1e: bf00 nop 8017a20: e7fd b.n 8017a1e /* Is the timer in the list of active timers? */ taskENTER_CRITICAL(); 8017a22: f000 f969 bl 8017cf8 { if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) 8017a26: 693b ldr r3, [r7, #16] 8017a28: f893 3028 ldrb.w r3, [r3, #40] @ 0x28 8017a2c: f003 0301 and.w r3, r3, #1 8017a30: 2b00 cmp r3, #0 8017a32: d102 bne.n 8017a3a { xReturn = pdFALSE; 8017a34: 2300 movs r3, #0 8017a36: 617b str r3, [r7, #20] 8017a38: e001 b.n 8017a3e } else { xReturn = pdTRUE; 8017a3a: 2301 movs r3, #1 8017a3c: 617b str r3, [r7, #20] } } taskEXIT_CRITICAL(); 8017a3e: f000 f98d bl 8017d5c return xReturn; 8017a42: 697b ldr r3, [r7, #20] } /*lint !e818 Can't be pointer to const due to the typedef. */ 8017a44: 4618 mov r0, r3 8017a46: 3718 adds r7, #24 8017a48: 46bd mov sp, r7 8017a4a: bd80 pop {r7, pc} 08017a4c : /*-----------------------------------------------------------*/ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) { 8017a4c: b580 push {r7, lr} 8017a4e: b086 sub sp, #24 8017a50: af00 add r7, sp, #0 8017a52: 6078 str r0, [r7, #4] Timer_t * const pxTimer = xTimer; 8017a54: 687b ldr r3, [r7, #4] 8017a56: 617b str r3, [r7, #20] void *pvReturn; configASSERT( xTimer ); 8017a58: 687b ldr r3, [r7, #4] 8017a5a: 2b00 cmp r3, #0 8017a5c: d10b bne.n 8017a76 __asm volatile 8017a5e: f04f 0350 mov.w r3, #80 @ 0x50 8017a62: f383 8811 msr BASEPRI, r3 8017a66: f3bf 8f6f isb sy 8017a6a: f3bf 8f4f dsb sy 8017a6e: 60fb str r3, [r7, #12] } 8017a70: bf00 nop 8017a72: bf00 nop 8017a74: e7fd b.n 8017a72 taskENTER_CRITICAL(); 8017a76: f000 f93f bl 8017cf8 { pvReturn = pxTimer->pvTimerID; 8017a7a: 697b ldr r3, [r7, #20] 8017a7c: 69db ldr r3, [r3, #28] 8017a7e: 613b str r3, [r7, #16] } taskEXIT_CRITICAL(); 8017a80: f000 f96c bl 8017d5c return pvReturn; 8017a84: 693b ldr r3, [r7, #16] } 8017a86: 4618 mov r0, r3 8017a88: 3718 adds r7, #24 8017a8a: 46bd mov sp, r7 8017a8c: bd80 pop {r7, pc} ... 08017a90 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { 8017a90: b480 push {r7} 8017a92: b085 sub sp, #20 8017a94: af00 add r7, sp, #0 8017a96: 60f8 str r0, [r7, #12] 8017a98: 60b9 str r1, [r7, #8] 8017a9a: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; 8017a9c: 68fb ldr r3, [r7, #12] 8017a9e: 3b04 subs r3, #4 8017aa0: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ 8017aa2: 68fb ldr r3, [r7, #12] 8017aa4: f04f 7280 mov.w r2, #16777216 @ 0x1000000 8017aa8: 601a str r2, [r3, #0] pxTopOfStack--; 8017aaa: 68fb ldr r3, [r7, #12] 8017aac: 3b04 subs r3, #4 8017aae: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ 8017ab0: 68bb ldr r3, [r7, #8] 8017ab2: f023 0201 bic.w r2, r3, #1 8017ab6: 68fb ldr r3, [r7, #12] 8017ab8: 601a str r2, [r3, #0] pxTopOfStack--; 8017aba: 68fb ldr r3, [r7, #12] 8017abc: 3b04 subs r3, #4 8017abe: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ 8017ac0: 4a0c ldr r2, [pc, #48] @ (8017af4 ) 8017ac2: 68fb ldr r3, [r7, #12] 8017ac4: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ 8017ac6: 68fb ldr r3, [r7, #12] 8017ac8: 3b14 subs r3, #20 8017aca: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ 8017acc: 687a ldr r2, [r7, #4] 8017ace: 68fb ldr r3, [r7, #12] 8017ad0: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; 8017ad2: 68fb ldr r3, [r7, #12] 8017ad4: 3b04 subs r3, #4 8017ad6: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; 8017ad8: 68fb ldr r3, [r7, #12] 8017ada: f06f 0202 mvn.w r2, #2 8017ade: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ 8017ae0: 68fb ldr r3, [r7, #12] 8017ae2: 3b20 subs r3, #32 8017ae4: 60fb str r3, [r7, #12] return pxTopOfStack; 8017ae6: 68fb ldr r3, [r7, #12] } 8017ae8: 4618 mov r0, r3 8017aea: 3714 adds r7, #20 8017aec: 46bd mov sp, r7 8017aee: f85d 7b04 ldr.w r7, [sp], #4 8017af2: 4770 bx lr 8017af4: 08017af9 .word 0x08017af9 08017af8 : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { 8017af8: b480 push {r7} 8017afa: b085 sub sp, #20 8017afc: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; 8017afe: 2300 movs r3, #0 8017b00: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); 8017b02: 4b13 ldr r3, [pc, #76] @ (8017b50 ) 8017b04: 681b ldr r3, [r3, #0] 8017b06: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8017b0a: d00b beq.n 8017b24 __asm volatile 8017b0c: f04f 0350 mov.w r3, #80 @ 0x50 8017b10: f383 8811 msr BASEPRI, r3 8017b14: f3bf 8f6f isb sy 8017b18: f3bf 8f4f dsb sy 8017b1c: 60fb str r3, [r7, #12] } 8017b1e: bf00 nop 8017b20: bf00 nop 8017b22: e7fd b.n 8017b20 __asm volatile 8017b24: f04f 0350 mov.w r3, #80 @ 0x50 8017b28: f383 8811 msr BASEPRI, r3 8017b2c: f3bf 8f6f isb sy 8017b30: f3bf 8f4f dsb sy 8017b34: 60bb str r3, [r7, #8] } 8017b36: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) 8017b38: bf00 nop 8017b3a: 687b ldr r3, [r7, #4] 8017b3c: 2b00 cmp r3, #0 8017b3e: d0fc beq.n 8017b3a about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } 8017b40: bf00 nop 8017b42: bf00 nop 8017b44: 3714 adds r7, #20 8017b46: 46bd mov sp, r7 8017b48: f85d 7b04 ldr.w r7, [sp], #4 8017b4c: 4770 bx lr 8017b4e: bf00 nop 8017b50: 24000044 .word 0x24000044 ... 08017b60 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8017b60: 4b07 ldr r3, [pc, #28] @ (8017b80 ) 8017b62: 6819 ldr r1, [r3, #0] 8017b64: 6808 ldr r0, [r1, #0] 8017b66: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017b6a: f380 8809 msr PSP, r0 8017b6e: f3bf 8f6f isb sy 8017b72: f04f 0000 mov.w r0, #0 8017b76: f380 8811 msr BASEPRI, r0 8017b7a: 4770 bx lr 8017b7c: f3af 8000 nop.w 08017b80 : 8017b80: 240029f8 .word 0x240029f8 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8017b84: bf00 nop 8017b86: bf00 nop 08017b88 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( 8017b88: 4808 ldr r0, [pc, #32] @ (8017bac ) 8017b8a: 6800 ldr r0, [r0, #0] 8017b8c: 6800 ldr r0, [r0, #0] 8017b8e: f380 8808 msr MSP, r0 8017b92: f04f 0000 mov.w r0, #0 8017b96: f380 8814 msr CONTROL, r0 8017b9a: b662 cpsie i 8017b9c: b661 cpsie f 8017b9e: f3bf 8f4f dsb sy 8017ba2: f3bf 8f6f isb sy 8017ba6: df00 svc 0 8017ba8: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } 8017baa: bf00 nop 8017bac: e000ed08 .word 0xe000ed08 08017bb0 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { 8017bb0: b580 push {r7, lr} 8017bb2: b086 sub sp, #24 8017bb4: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); 8017bb6: 4b47 ldr r3, [pc, #284] @ (8017cd4 ) 8017bb8: 681b ldr r3, [r3, #0] 8017bba: 4a47 ldr r2, [pc, #284] @ (8017cd8 ) 8017bbc: 4293 cmp r3, r2 8017bbe: d10b bne.n 8017bd8 __asm volatile 8017bc0: f04f 0350 mov.w r3, #80 @ 0x50 8017bc4: f383 8811 msr BASEPRI, r3 8017bc8: f3bf 8f6f isb sy 8017bcc: f3bf 8f4f dsb sy 8017bd0: 613b str r3, [r7, #16] } 8017bd2: bf00 nop 8017bd4: bf00 nop 8017bd6: e7fd b.n 8017bd4 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); 8017bd8: 4b3e ldr r3, [pc, #248] @ (8017cd4 ) 8017bda: 681b ldr r3, [r3, #0] 8017bdc: 4a3f ldr r2, [pc, #252] @ (8017cdc ) 8017bde: 4293 cmp r3, r2 8017be0: d10b bne.n 8017bfa __asm volatile 8017be2: f04f 0350 mov.w r3, #80 @ 0x50 8017be6: f383 8811 msr BASEPRI, r3 8017bea: f3bf 8f6f isb sy 8017bee: f3bf 8f4f dsb sy 8017bf2: 60fb str r3, [r7, #12] } 8017bf4: bf00 nop 8017bf6: bf00 nop 8017bf8: e7fd b.n 8017bf6 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); 8017bfa: 4b39 ldr r3, [pc, #228] @ (8017ce0 ) 8017bfc: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; 8017bfe: 697b ldr r3, [r7, #20] 8017c00: 781b ldrb r3, [r3, #0] 8017c02: b2db uxtb r3, r3 8017c04: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; 8017c06: 697b ldr r3, [r7, #20] 8017c08: 22ff movs r2, #255 @ 0xff 8017c0a: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; 8017c0c: 697b ldr r3, [r7, #20] 8017c0e: 781b ldrb r3, [r3, #0] 8017c10: b2db uxtb r3, r3 8017c12: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; 8017c14: 78fb ldrb r3, [r7, #3] 8017c16: b2db uxtb r3, r3 8017c18: f003 0350 and.w r3, r3, #80 @ 0x50 8017c1c: b2da uxtb r2, r3 8017c1e: 4b31 ldr r3, [pc, #196] @ (8017ce4 ) 8017c20: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; 8017c22: 4b31 ldr r3, [pc, #196] @ (8017ce8 ) 8017c24: 2207 movs r2, #7 8017c26: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017c28: e009 b.n 8017c3e { ulMaxPRIGROUPValue--; 8017c2a: 4b2f ldr r3, [pc, #188] @ (8017ce8 ) 8017c2c: 681b ldr r3, [r3, #0] 8017c2e: 3b01 subs r3, #1 8017c30: 4a2d ldr r2, [pc, #180] @ (8017ce8 ) 8017c32: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; 8017c34: 78fb ldrb r3, [r7, #3] 8017c36: b2db uxtb r3, r3 8017c38: 005b lsls r3, r3, #1 8017c3a: b2db uxtb r3, r3 8017c3c: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) 8017c3e: 78fb ldrb r3, [r7, #3] 8017c40: b2db uxtb r3, r3 8017c42: f003 0380 and.w r3, r3, #128 @ 0x80 8017c46: 2b80 cmp r3, #128 @ 0x80 8017c48: d0ef beq.n 8017c2a #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); 8017c4a: 4b27 ldr r3, [pc, #156] @ (8017ce8 ) 8017c4c: 681b ldr r3, [r3, #0] 8017c4e: f1c3 0307 rsb r3, r3, #7 8017c52: 2b04 cmp r3, #4 8017c54: d00b beq.n 8017c6e __asm volatile 8017c56: f04f 0350 mov.w r3, #80 @ 0x50 8017c5a: f383 8811 msr BASEPRI, r3 8017c5e: f3bf 8f6f isb sy 8017c62: f3bf 8f4f dsb sy 8017c66: 60bb str r3, [r7, #8] } 8017c68: bf00 nop 8017c6a: bf00 nop 8017c6c: e7fd b.n 8017c6a } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; 8017c6e: 4b1e ldr r3, [pc, #120] @ (8017ce8 ) 8017c70: 681b ldr r3, [r3, #0] 8017c72: 021b lsls r3, r3, #8 8017c74: 4a1c ldr r2, [pc, #112] @ (8017ce8 ) 8017c76: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; 8017c78: 4b1b ldr r3, [pc, #108] @ (8017ce8 ) 8017c7a: 681b ldr r3, [r3, #0] 8017c7c: f403 63e0 and.w r3, r3, #1792 @ 0x700 8017c80: 4a19 ldr r2, [pc, #100] @ (8017ce8 ) 8017c82: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; 8017c84: 687b ldr r3, [r7, #4] 8017c86: b2da uxtb r2, r3 8017c88: 697b ldr r3, [r7, #20] 8017c8a: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; 8017c8c: 4b17 ldr r3, [pc, #92] @ (8017cec ) 8017c8e: 681b ldr r3, [r3, #0] 8017c90: 4a16 ldr r2, [pc, #88] @ (8017cec ) 8017c92: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8017c96: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; 8017c98: 4b14 ldr r3, [pc, #80] @ (8017cec ) 8017c9a: 681b ldr r3, [r3, #0] 8017c9c: 4a13 ldr r2, [pc, #76] @ (8017cec ) 8017c9e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000 8017ca2: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); 8017ca4: f000 f8da bl 8017e5c /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; 8017ca8: 4b11 ldr r3, [pc, #68] @ (8017cf0 ) 8017caa: 2200 movs r2, #0 8017cac: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); 8017cae: f000 f8f9 bl 8017ea4 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; 8017cb2: 4b10 ldr r3, [pc, #64] @ (8017cf4 ) 8017cb4: 681b ldr r3, [r3, #0] 8017cb6: 4a0f ldr r2, [pc, #60] @ (8017cf4 ) 8017cb8: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000 8017cbc: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); 8017cbe: f7ff ff63 bl 8017b88 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); 8017cc2: f7fe fbcd bl 8016460 prvTaskExitError(); 8017cc6: f7ff ff17 bl 8017af8 /* Should not get here! */ return 0; 8017cca: 2300 movs r3, #0 } 8017ccc: 4618 mov r0, r3 8017cce: 3718 adds r7, #24 8017cd0: 46bd mov sp, r7 8017cd2: bd80 pop {r7, pc} 8017cd4: e000ed00 .word 0xe000ed00 8017cd8: 410fc271 .word 0x410fc271 8017cdc: 410fc270 .word 0x410fc270 8017ce0: e000e400 .word 0xe000e400 8017ce4: 24003024 .word 0x24003024 8017ce8: 24003028 .word 0x24003028 8017cec: e000ed20 .word 0xe000ed20 8017cf0: 24000044 .word 0x24000044 8017cf4: e000ef34 .word 0xe000ef34 08017cf8 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8017cf8: b480 push {r7} 8017cfa: b083 sub sp, #12 8017cfc: af00 add r7, sp, #0 __asm volatile 8017cfe: f04f 0350 mov.w r3, #80 @ 0x50 8017d02: f383 8811 msr BASEPRI, r3 8017d06: f3bf 8f6f isb sy 8017d0a: f3bf 8f4f dsb sy 8017d0e: 607b str r3, [r7, #4] } 8017d10: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8017d12: 4b10 ldr r3, [pc, #64] @ (8017d54 ) 8017d14: 681b ldr r3, [r3, #0] 8017d16: 3301 adds r3, #1 8017d18: 4a0e ldr r2, [pc, #56] @ (8017d54 ) 8017d1a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8017d1c: 4b0d ldr r3, [pc, #52] @ (8017d54 ) 8017d1e: 681b ldr r3, [r3, #0] 8017d20: 2b01 cmp r3, #1 8017d22: d110 bne.n 8017d46 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8017d24: 4b0c ldr r3, [pc, #48] @ (8017d58 ) 8017d26: 681b ldr r3, [r3, #0] 8017d28: b2db uxtb r3, r3 8017d2a: 2b00 cmp r3, #0 8017d2c: d00b beq.n 8017d46 __asm volatile 8017d2e: f04f 0350 mov.w r3, #80 @ 0x50 8017d32: f383 8811 msr BASEPRI, r3 8017d36: f3bf 8f6f isb sy 8017d3a: f3bf 8f4f dsb sy 8017d3e: 603b str r3, [r7, #0] } 8017d40: bf00 nop 8017d42: bf00 nop 8017d44: e7fd b.n 8017d42 } } 8017d46: bf00 nop 8017d48: 370c adds r7, #12 8017d4a: 46bd mov sp, r7 8017d4c: f85d 7b04 ldr.w r7, [sp], #4 8017d50: 4770 bx lr 8017d52: bf00 nop 8017d54: 24000044 .word 0x24000044 8017d58: e000ed04 .word 0xe000ed04 08017d5c : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8017d5c: b480 push {r7} 8017d5e: b083 sub sp, #12 8017d60: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8017d62: 4b12 ldr r3, [pc, #72] @ (8017dac ) 8017d64: 681b ldr r3, [r3, #0] 8017d66: 2b00 cmp r3, #0 8017d68: d10b bne.n 8017d82 __asm volatile 8017d6a: f04f 0350 mov.w r3, #80 @ 0x50 8017d6e: f383 8811 msr BASEPRI, r3 8017d72: f3bf 8f6f isb sy 8017d76: f3bf 8f4f dsb sy 8017d7a: 607b str r3, [r7, #4] } 8017d7c: bf00 nop 8017d7e: bf00 nop 8017d80: e7fd b.n 8017d7e uxCriticalNesting--; 8017d82: 4b0a ldr r3, [pc, #40] @ (8017dac ) 8017d84: 681b ldr r3, [r3, #0] 8017d86: 3b01 subs r3, #1 8017d88: 4a08 ldr r2, [pc, #32] @ (8017dac ) 8017d8a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8017d8c: 4b07 ldr r3, [pc, #28] @ (8017dac ) 8017d8e: 681b ldr r3, [r3, #0] 8017d90: 2b00 cmp r3, #0 8017d92: d105 bne.n 8017da0 8017d94: 2300 movs r3, #0 8017d96: 603b str r3, [r7, #0] __asm volatile 8017d98: 683b ldr r3, [r7, #0] 8017d9a: f383 8811 msr BASEPRI, r3 } 8017d9e: bf00 nop { portENABLE_INTERRUPTS(); } } 8017da0: bf00 nop 8017da2: 370c adds r7, #12 8017da4: 46bd mov sp, r7 8017da6: f85d 7b04 ldr.w r7, [sp], #4 8017daa: 4770 bx lr 8017dac: 24000044 .word 0x24000044 08017db0 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8017db0: f3ef 8009 mrs r0, PSP 8017db4: f3bf 8f6f isb sy 8017db8: 4b15 ldr r3, [pc, #84] @ (8017e10 ) 8017dba: 681a ldr r2, [r3, #0] 8017dbc: f01e 0f10 tst.w lr, #16 8017dc0: bf08 it eq 8017dc2: ed20 8a10 vstmdbeq r0!, {s16-s31} 8017dc6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017dca: 6010 str r0, [r2, #0] 8017dcc: e92d 0009 stmdb sp!, {r0, r3} 8017dd0: f04f 0050 mov.w r0, #80 @ 0x50 8017dd4: f380 8811 msr BASEPRI, r0 8017dd8: f3bf 8f4f dsb sy 8017ddc: f3bf 8f6f isb sy 8017de0: f7fe fb3e bl 8016460 8017de4: f04f 0000 mov.w r0, #0 8017de8: f380 8811 msr BASEPRI, r0 8017dec: bc09 pop {r0, r3} 8017dee: 6819 ldr r1, [r3, #0] 8017df0: 6808 ldr r0, [r1, #0] 8017df2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8017df6: f01e 0f10 tst.w lr, #16 8017dfa: bf08 it eq 8017dfc: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8017e00: f380 8809 msr PSP, r0 8017e04: f3bf 8f6f isb sy 8017e08: 4770 bx lr 8017e0a: bf00 nop 8017e0c: f3af 8000 nop.w 08017e10 : 8017e10: 240029f8 .word 0x240029f8 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8017e14: bf00 nop 8017e16: bf00 nop 08017e18 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8017e18: b580 push {r7, lr} 8017e1a: b082 sub sp, #8 8017e1c: af00 add r7, sp, #0 __asm volatile 8017e1e: f04f 0350 mov.w r3, #80 @ 0x50 8017e22: f383 8811 msr BASEPRI, r3 8017e26: f3bf 8f6f isb sy 8017e2a: f3bf 8f4f dsb sy 8017e2e: 607b str r3, [r7, #4] } 8017e30: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8017e32: f7fe fa5b bl 80162ec 8017e36: 4603 mov r3, r0 8017e38: 2b00 cmp r3, #0 8017e3a: d003 beq.n 8017e44 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 8017e3c: 4b06 ldr r3, [pc, #24] @ (8017e58 ) 8017e3e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8017e42: 601a str r2, [r3, #0] 8017e44: 2300 movs r3, #0 8017e46: 603b str r3, [r7, #0] __asm volatile 8017e48: 683b ldr r3, [r7, #0] 8017e4a: f383 8811 msr BASEPRI, r3 } 8017e4e: bf00 nop } } portENABLE_INTERRUPTS(); } 8017e50: bf00 nop 8017e52: 3708 adds r7, #8 8017e54: 46bd mov sp, r7 8017e56: bd80 pop {r7, pc} 8017e58: e000ed04 .word 0xe000ed04 08017e5c : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { 8017e5c: b480 push {r7} 8017e5e: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; 8017e60: 4b0b ldr r3, [pc, #44] @ (8017e90 ) 8017e62: 2200 movs r2, #0 8017e64: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; 8017e66: 4b0b ldr r3, [pc, #44] @ (8017e94 ) 8017e68: 2200 movs r2, #0 8017e6a: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; 8017e6c: 4b0a ldr r3, [pc, #40] @ (8017e98 ) 8017e6e: 681b ldr r3, [r3, #0] 8017e70: 4a0a ldr r2, [pc, #40] @ (8017e9c ) 8017e72: fba2 2303 umull r2, r3, r2, r3 8017e76: 099b lsrs r3, r3, #6 8017e78: 4a09 ldr r2, [pc, #36] @ (8017ea0 ) 8017e7a: 3b01 subs r3, #1 8017e7c: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); 8017e7e: 4b04 ldr r3, [pc, #16] @ (8017e90 ) 8017e80: 2207 movs r2, #7 8017e82: 601a str r2, [r3, #0] } 8017e84: bf00 nop 8017e86: 46bd mov sp, r7 8017e88: f85d 7b04 ldr.w r7, [sp], #4 8017e8c: 4770 bx lr 8017e8e: bf00 nop 8017e90: e000e010 .word 0xe000e010 8017e94: e000e018 .word 0xe000e018 8017e98: 24000034 .word 0x24000034 8017e9c: 10624dd3 .word 0x10624dd3 8017ea0: e000e014 .word 0xe000e014 08017ea4 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile 8017ea4: f8df 000c ldr.w r0, [pc, #12] @ 8017eb4 8017ea8: 6801 ldr r1, [r0, #0] 8017eaa: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000 8017eae: 6001 str r1, [r0, #0] 8017eb0: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } 8017eb2: bf00 nop 8017eb4: e000ed88 .word 0xe000ed88 08017eb8 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8017eb8: b480 push {r7} 8017eba: b085 sub sp, #20 8017ebc: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 8017ebe: f3ef 8305 mrs r3, IPSR 8017ec2: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8017ec4: 68fb ldr r3, [r7, #12] 8017ec6: 2b0f cmp r3, #15 8017ec8: d915 bls.n 8017ef6 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 8017eca: 4a18 ldr r2, [pc, #96] @ (8017f2c ) 8017ecc: 68fb ldr r3, [r7, #12] 8017ece: 4413 add r3, r2 8017ed0: 781b ldrb r3, [r3, #0] 8017ed2: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8017ed4: 4b16 ldr r3, [pc, #88] @ (8017f30 ) 8017ed6: 781b ldrb r3, [r3, #0] 8017ed8: 7afa ldrb r2, [r7, #11] 8017eda: 429a cmp r2, r3 8017edc: d20b bcs.n 8017ef6 __asm volatile 8017ede: f04f 0350 mov.w r3, #80 @ 0x50 8017ee2: f383 8811 msr BASEPRI, r3 8017ee6: f3bf 8f6f isb sy 8017eea: f3bf 8f4f dsb sy 8017eee: 607b str r3, [r7, #4] } 8017ef0: bf00 nop 8017ef2: bf00 nop 8017ef4: e7fd b.n 8017ef2 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8017ef6: 4b0f ldr r3, [pc, #60] @ (8017f34 ) 8017ef8: 681b ldr r3, [r3, #0] 8017efa: f403 62e0 and.w r2, r3, #1792 @ 0x700 8017efe: 4b0e ldr r3, [pc, #56] @ (8017f38 ) 8017f00: 681b ldr r3, [r3, #0] 8017f02: 429a cmp r2, r3 8017f04: d90b bls.n 8017f1e __asm volatile 8017f06: f04f 0350 mov.w r3, #80 @ 0x50 8017f0a: f383 8811 msr BASEPRI, r3 8017f0e: f3bf 8f6f isb sy 8017f12: f3bf 8f4f dsb sy 8017f16: 603b str r3, [r7, #0] } 8017f18: bf00 nop 8017f1a: bf00 nop 8017f1c: e7fd b.n 8017f1a } 8017f1e: bf00 nop 8017f20: 3714 adds r7, #20 8017f22: 46bd mov sp, r7 8017f24: f85d 7b04 ldr.w r7, [sp], #4 8017f28: 4770 bx lr 8017f2a: bf00 nop 8017f2c: e000e3f0 .word 0xe000e3f0 8017f30: 24003024 .word 0x24003024 8017f34: e000ed0c .word 0xe000ed0c 8017f38: 24003028 .word 0x24003028 08017f3c : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { 8017f3c: b580 push {r7, lr} 8017f3e: b08a sub sp, #40 @ 0x28 8017f40: af00 add r7, sp, #0 8017f42: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; 8017f44: 2300 movs r3, #0 8017f46: 61fb str r3, [r7, #28] vTaskSuspendAll(); 8017f48: f7fe f914 bl 8016174 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) 8017f4c: 4b5c ldr r3, [pc, #368] @ (80180c0 ) 8017f4e: 681b ldr r3, [r3, #0] 8017f50: 2b00 cmp r3, #0 8017f52: d101 bne.n 8017f58 { prvHeapInit(); 8017f54: f000 f924 bl 80181a0 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) 8017f58: 4b5a ldr r3, [pc, #360] @ (80180c4 ) 8017f5a: 681a ldr r2, [r3, #0] 8017f5c: 687b ldr r3, [r7, #4] 8017f5e: 4013 ands r3, r2 8017f60: 2b00 cmp r3, #0 8017f62: f040 8095 bne.w 8018090 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) 8017f66: 687b ldr r3, [r7, #4] 8017f68: 2b00 cmp r3, #0 8017f6a: d01e beq.n 8017faa { xWantedSize += xHeapStructSize; 8017f6c: 2208 movs r2, #8 8017f6e: 687b ldr r3, [r7, #4] 8017f70: 4413 add r3, r2 8017f72: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) 8017f74: 687b ldr r3, [r7, #4] 8017f76: f003 0307 and.w r3, r3, #7 8017f7a: 2b00 cmp r3, #0 8017f7c: d015 beq.n 8017faa { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); 8017f7e: 687b ldr r3, [r7, #4] 8017f80: f023 0307 bic.w r3, r3, #7 8017f84: 3308 adds r3, #8 8017f86: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); 8017f88: 687b ldr r3, [r7, #4] 8017f8a: f003 0307 and.w r3, r3, #7 8017f8e: 2b00 cmp r3, #0 8017f90: d00b beq.n 8017faa __asm volatile 8017f92: f04f 0350 mov.w r3, #80 @ 0x50 8017f96: f383 8811 msr BASEPRI, r3 8017f9a: f3bf 8f6f isb sy 8017f9e: f3bf 8f4f dsb sy 8017fa2: 617b str r3, [r7, #20] } 8017fa4: bf00 nop 8017fa6: bf00 nop 8017fa8: e7fd b.n 8017fa6 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) 8017faa: 687b ldr r3, [r7, #4] 8017fac: 2b00 cmp r3, #0 8017fae: d06f beq.n 8018090 8017fb0: 4b45 ldr r3, [pc, #276] @ (80180c8 ) 8017fb2: 681b ldr r3, [r3, #0] 8017fb4: 687a ldr r2, [r7, #4] 8017fb6: 429a cmp r2, r3 8017fb8: d86a bhi.n 8018090 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; 8017fba: 4b44 ldr r3, [pc, #272] @ (80180cc ) 8017fbc: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; 8017fbe: 4b43 ldr r3, [pc, #268] @ (80180cc ) 8017fc0: 681b ldr r3, [r3, #0] 8017fc2: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017fc4: e004 b.n 8017fd0 { pxPreviousBlock = pxBlock; 8017fc6: 6a7b ldr r3, [r7, #36] @ 0x24 8017fc8: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; 8017fca: 6a7b ldr r3, [r7, #36] @ 0x24 8017fcc: 681b ldr r3, [r3, #0] 8017fce: 627b str r3, [r7, #36] @ 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) 8017fd0: 6a7b ldr r3, [r7, #36] @ 0x24 8017fd2: 685b ldr r3, [r3, #4] 8017fd4: 687a ldr r2, [r7, #4] 8017fd6: 429a cmp r2, r3 8017fd8: d903 bls.n 8017fe2 8017fda: 6a7b ldr r3, [r7, #36] @ 0x24 8017fdc: 681b ldr r3, [r3, #0] 8017fde: 2b00 cmp r3, #0 8017fe0: d1f1 bne.n 8017fc6 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) 8017fe2: 4b37 ldr r3, [pc, #220] @ (80180c0 ) 8017fe4: 681b ldr r3, [r3, #0] 8017fe6: 6a7a ldr r2, [r7, #36] @ 0x24 8017fe8: 429a cmp r2, r3 8017fea: d051 beq.n 8018090 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); 8017fec: 6a3b ldr r3, [r7, #32] 8017fee: 681b ldr r3, [r3, #0] 8017ff0: 2208 movs r2, #8 8017ff2: 4413 add r3, r2 8017ff4: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; 8017ff6: 6a7b ldr r3, [r7, #36] @ 0x24 8017ff8: 681a ldr r2, [r3, #0] 8017ffa: 6a3b ldr r3, [r7, #32] 8017ffc: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) 8017ffe: 6a7b ldr r3, [r7, #36] @ 0x24 8018000: 685a ldr r2, [r3, #4] 8018002: 687b ldr r3, [r7, #4] 8018004: 1ad2 subs r2, r2, r3 8018006: 2308 movs r3, #8 8018008: 005b lsls r3, r3, #1 801800a: 429a cmp r2, r3 801800c: d920 bls.n 8018050 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); 801800e: 6a7a ldr r2, [r7, #36] @ 0x24 8018010: 687b ldr r3, [r7, #4] 8018012: 4413 add r3, r2 8018014: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); 8018016: 69bb ldr r3, [r7, #24] 8018018: f003 0307 and.w r3, r3, #7 801801c: 2b00 cmp r3, #0 801801e: d00b beq.n 8018038 __asm volatile 8018020: f04f 0350 mov.w r3, #80 @ 0x50 8018024: f383 8811 msr BASEPRI, r3 8018028: f3bf 8f6f isb sy 801802c: f3bf 8f4f dsb sy 8018030: 613b str r3, [r7, #16] } 8018032: bf00 nop 8018034: bf00 nop 8018036: e7fd b.n 8018034 /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; 8018038: 6a7b ldr r3, [r7, #36] @ 0x24 801803a: 685a ldr r2, [r3, #4] 801803c: 687b ldr r3, [r7, #4] 801803e: 1ad2 subs r2, r2, r3 8018040: 69bb ldr r3, [r7, #24] 8018042: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; 8018044: 6a7b ldr r3, [r7, #36] @ 0x24 8018046: 687a ldr r2, [r7, #4] 8018048: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); 801804a: 69b8 ldr r0, [r7, #24] 801804c: f000 f90a bl 8018264 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; 8018050: 4b1d ldr r3, [pc, #116] @ (80180c8 ) 8018052: 681a ldr r2, [r3, #0] 8018054: 6a7b ldr r3, [r7, #36] @ 0x24 8018056: 685b ldr r3, [r3, #4] 8018058: 1ad3 subs r3, r2, r3 801805a: 4a1b ldr r2, [pc, #108] @ (80180c8 ) 801805c: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) 801805e: 4b1a ldr r3, [pc, #104] @ (80180c8 ) 8018060: 681a ldr r2, [r3, #0] 8018062: 4b1b ldr r3, [pc, #108] @ (80180d0 ) 8018064: 681b ldr r3, [r3, #0] 8018066: 429a cmp r2, r3 8018068: d203 bcs.n 8018072 { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; 801806a: 4b17 ldr r3, [pc, #92] @ (80180c8 ) 801806c: 681b ldr r3, [r3, #0] 801806e: 4a18 ldr r2, [pc, #96] @ (80180d0 ) 8018070: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; 8018072: 6a7b ldr r3, [r7, #36] @ 0x24 8018074: 685a ldr r2, [r3, #4] 8018076: 4b13 ldr r3, [pc, #76] @ (80180c4 ) 8018078: 681b ldr r3, [r3, #0] 801807a: 431a orrs r2, r3 801807c: 6a7b ldr r3, [r7, #36] @ 0x24 801807e: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; 8018080: 6a7b ldr r3, [r7, #36] @ 0x24 8018082: 2200 movs r2, #0 8018084: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; 8018086: 4b13 ldr r3, [pc, #76] @ (80180d4 ) 8018088: 681b ldr r3, [r3, #0] 801808a: 3301 adds r3, #1 801808c: 4a11 ldr r2, [pc, #68] @ (80180d4 ) 801808e: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); 8018090: f7fe f87e bl 8016190 mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); 8018094: 69fb ldr r3, [r7, #28] 8018096: f003 0307 and.w r3, r3, #7 801809a: 2b00 cmp r3, #0 801809c: d00b beq.n 80180b6 __asm volatile 801809e: f04f 0350 mov.w r3, #80 @ 0x50 80180a2: f383 8811 msr BASEPRI, r3 80180a6: f3bf 8f6f isb sy 80180aa: f3bf 8f4f dsb sy 80180ae: 60fb str r3, [r7, #12] } 80180b0: bf00 nop 80180b2: bf00 nop 80180b4: e7fd b.n 80180b2 return pvReturn; 80180b6: 69fb ldr r3, [r7, #28] } 80180b8: 4618 mov r0, r3 80180ba: 3728 adds r7, #40 @ 0x28 80180bc: 46bd mov sp, r7 80180be: bd80 pop {r7, pc} 80180c0: 24013034 .word 0x24013034 80180c4: 24013048 .word 0x24013048 80180c8: 24013038 .word 0x24013038 80180cc: 2401302c .word 0x2401302c 80180d0: 2401303c .word 0x2401303c 80180d4: 24013040 .word 0x24013040 080180d8 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { 80180d8: b580 push {r7, lr} 80180da: b086 sub sp, #24 80180dc: af00 add r7, sp, #0 80180de: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; 80180e0: 687b ldr r3, [r7, #4] 80180e2: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) 80180e4: 687b ldr r3, [r7, #4] 80180e6: 2b00 cmp r3, #0 80180e8: d04f beq.n 801818a { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; 80180ea: 2308 movs r3, #8 80180ec: 425b negs r3, r3 80180ee: 697a ldr r2, [r7, #20] 80180f0: 4413 add r3, r2 80180f2: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; 80180f4: 697b ldr r3, [r7, #20] 80180f6: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); 80180f8: 693b ldr r3, [r7, #16] 80180fa: 685a ldr r2, [r3, #4] 80180fc: 4b25 ldr r3, [pc, #148] @ (8018194 ) 80180fe: 681b ldr r3, [r3, #0] 8018100: 4013 ands r3, r2 8018102: 2b00 cmp r3, #0 8018104: d10b bne.n 801811e __asm volatile 8018106: f04f 0350 mov.w r3, #80 @ 0x50 801810a: f383 8811 msr BASEPRI, r3 801810e: f3bf 8f6f isb sy 8018112: f3bf 8f4f dsb sy 8018116: 60fb str r3, [r7, #12] } 8018118: bf00 nop 801811a: bf00 nop 801811c: e7fd b.n 801811a configASSERT( pxLink->pxNextFreeBlock == NULL ); 801811e: 693b ldr r3, [r7, #16] 8018120: 681b ldr r3, [r3, #0] 8018122: 2b00 cmp r3, #0 8018124: d00b beq.n 801813e __asm volatile 8018126: f04f 0350 mov.w r3, #80 @ 0x50 801812a: f383 8811 msr BASEPRI, r3 801812e: f3bf 8f6f isb sy 8018132: f3bf 8f4f dsb sy 8018136: 60bb str r3, [r7, #8] } 8018138: bf00 nop 801813a: bf00 nop 801813c: e7fd b.n 801813a if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) 801813e: 693b ldr r3, [r7, #16] 8018140: 685a ldr r2, [r3, #4] 8018142: 4b14 ldr r3, [pc, #80] @ (8018194 ) 8018144: 681b ldr r3, [r3, #0] 8018146: 4013 ands r3, r2 8018148: 2b00 cmp r3, #0 801814a: d01e beq.n 801818a { if( pxLink->pxNextFreeBlock == NULL ) 801814c: 693b ldr r3, [r7, #16] 801814e: 681b ldr r3, [r3, #0] 8018150: 2b00 cmp r3, #0 8018152: d11a bne.n 801818a { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; 8018154: 693b ldr r3, [r7, #16] 8018156: 685a ldr r2, [r3, #4] 8018158: 4b0e ldr r3, [pc, #56] @ (8018194 ) 801815a: 681b ldr r3, [r3, #0] 801815c: 43db mvns r3, r3 801815e: 401a ands r2, r3 8018160: 693b ldr r3, [r7, #16] 8018162: 605a str r2, [r3, #4] vTaskSuspendAll(); 8018164: f7fe f806 bl 8016174 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; 8018168: 693b ldr r3, [r7, #16] 801816a: 685a ldr r2, [r3, #4] 801816c: 4b0a ldr r3, [pc, #40] @ (8018198 ) 801816e: 681b ldr r3, [r3, #0] 8018170: 4413 add r3, r2 8018172: 4a09 ldr r2, [pc, #36] @ (8018198 ) 8018174: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); 8018176: 6938 ldr r0, [r7, #16] 8018178: f000 f874 bl 8018264 xNumberOfSuccessfulFrees++; 801817c: 4b07 ldr r3, [pc, #28] @ (801819c ) 801817e: 681b ldr r3, [r3, #0] 8018180: 3301 adds r3, #1 8018182: 4a06 ldr r2, [pc, #24] @ (801819c ) 8018184: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); 8018186: f7fe f803 bl 8016190 else { mtCOVERAGE_TEST_MARKER(); } } } 801818a: bf00 nop 801818c: 3718 adds r7, #24 801818e: 46bd mov sp, r7 8018190: bd80 pop {r7, pc} 8018192: bf00 nop 8018194: 24013048 .word 0x24013048 8018198: 24013038 .word 0x24013038 801819c: 24013044 .word 0x24013044 080181a0 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { 80181a0: b480 push {r7} 80181a2: b085 sub sp, #20 80181a4: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; 80181a6: f44f 3380 mov.w r3, #65536 @ 0x10000 80181aa: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; 80181ac: 4b27 ldr r3, [pc, #156] @ (801824c ) 80181ae: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) 80181b0: 68fb ldr r3, [r7, #12] 80181b2: f003 0307 and.w r3, r3, #7 80181b6: 2b00 cmp r3, #0 80181b8: d00c beq.n 80181d4 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); 80181ba: 68fb ldr r3, [r7, #12] 80181bc: 3307 adds r3, #7 80181be: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80181c0: 68fb ldr r3, [r7, #12] 80181c2: f023 0307 bic.w r3, r3, #7 80181c6: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; 80181c8: 68ba ldr r2, [r7, #8] 80181ca: 68fb ldr r3, [r7, #12] 80181cc: 1ad3 subs r3, r2, r3 80181ce: 4a1f ldr r2, [pc, #124] @ (801824c ) 80181d0: 4413 add r3, r2 80181d2: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; 80181d4: 68fb ldr r3, [r7, #12] 80181d6: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; 80181d8: 4a1d ldr r2, [pc, #116] @ (8018250 ) 80181da: 687b ldr r3, [r7, #4] 80181dc: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; 80181de: 4b1c ldr r3, [pc, #112] @ (8018250 ) 80181e0: 2200 movs r2, #0 80181e2: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; 80181e4: 687b ldr r3, [r7, #4] 80181e6: 68ba ldr r2, [r7, #8] 80181e8: 4413 add r3, r2 80181ea: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; 80181ec: 2208 movs r2, #8 80181ee: 68fb ldr r3, [r7, #12] 80181f0: 1a9b subs r3, r3, r2 80181f2: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); 80181f4: 68fb ldr r3, [r7, #12] 80181f6: f023 0307 bic.w r3, r3, #7 80181fa: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; 80181fc: 68fb ldr r3, [r7, #12] 80181fe: 4a15 ldr r2, [pc, #84] @ (8018254 ) 8018200: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; 8018202: 4b14 ldr r3, [pc, #80] @ (8018254 ) 8018204: 681b ldr r3, [r3, #0] 8018206: 2200 movs r2, #0 8018208: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; 801820a: 4b12 ldr r3, [pc, #72] @ (8018254 ) 801820c: 681b ldr r3, [r3, #0] 801820e: 2200 movs r2, #0 8018210: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; 8018212: 687b ldr r3, [r7, #4] 8018214: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; 8018216: 683b ldr r3, [r7, #0] 8018218: 68fa ldr r2, [r7, #12] 801821a: 1ad2 subs r2, r2, r3 801821c: 683b ldr r3, [r7, #0] 801821e: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; 8018220: 4b0c ldr r3, [pc, #48] @ (8018254 ) 8018222: 681a ldr r2, [r3, #0] 8018224: 683b ldr r3, [r7, #0] 8018226: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8018228: 683b ldr r3, [r7, #0] 801822a: 685b ldr r3, [r3, #4] 801822c: 4a0a ldr r2, [pc, #40] @ (8018258 ) 801822e: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; 8018230: 683b ldr r3, [r7, #0] 8018232: 685b ldr r3, [r3, #4] 8018234: 4a09 ldr r2, [pc, #36] @ (801825c ) 8018236: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); 8018238: 4b09 ldr r3, [pc, #36] @ (8018260 ) 801823a: f04f 4200 mov.w r2, #2147483648 @ 0x80000000 801823e: 601a str r2, [r3, #0] } 8018240: bf00 nop 8018242: 3714 adds r7, #20 8018244: 46bd mov sp, r7 8018246: f85d 7b04 ldr.w r7, [sp], #4 801824a: 4770 bx lr 801824c: 2400302c .word 0x2400302c 8018250: 2401302c .word 0x2401302c 8018254: 24013034 .word 0x24013034 8018258: 2401303c .word 0x2401303c 801825c: 24013038 .word 0x24013038 8018260: 24013048 .word 0x24013048 08018264 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { 8018264: b480 push {r7} 8018266: b085 sub sp, #20 8018268: af00 add r7, sp, #0 801826a: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) 801826c: 4b28 ldr r3, [pc, #160] @ (8018310 ) 801826e: 60fb str r3, [r7, #12] 8018270: e002 b.n 8018278 8018272: 68fb ldr r3, [r7, #12] 8018274: 681b ldr r3, [r3, #0] 8018276: 60fb str r3, [r7, #12] 8018278: 68fb ldr r3, [r7, #12] 801827a: 681b ldr r3, [r3, #0] 801827c: 687a ldr r2, [r7, #4] 801827e: 429a cmp r2, r3 8018280: d8f7 bhi.n 8018272 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; 8018282: 68fb ldr r3, [r7, #12] 8018284: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) 8018286: 68fb ldr r3, [r7, #12] 8018288: 685b ldr r3, [r3, #4] 801828a: 68ba ldr r2, [r7, #8] 801828c: 4413 add r3, r2 801828e: 687a ldr r2, [r7, #4] 8018290: 429a cmp r2, r3 8018292: d108 bne.n 80182a6 { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; 8018294: 68fb ldr r3, [r7, #12] 8018296: 685a ldr r2, [r3, #4] 8018298: 687b ldr r3, [r7, #4] 801829a: 685b ldr r3, [r3, #4] 801829c: 441a add r2, r3 801829e: 68fb ldr r3, [r7, #12] 80182a0: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; 80182a2: 68fb ldr r3, [r7, #12] 80182a4: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; 80182a6: 687b ldr r3, [r7, #4] 80182a8: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) 80182aa: 687b ldr r3, [r7, #4] 80182ac: 685b ldr r3, [r3, #4] 80182ae: 68ba ldr r2, [r7, #8] 80182b0: 441a add r2, r3 80182b2: 68fb ldr r3, [r7, #12] 80182b4: 681b ldr r3, [r3, #0] 80182b6: 429a cmp r2, r3 80182b8: d118 bne.n 80182ec { if( pxIterator->pxNextFreeBlock != pxEnd ) 80182ba: 68fb ldr r3, [r7, #12] 80182bc: 681a ldr r2, [r3, #0] 80182be: 4b15 ldr r3, [pc, #84] @ (8018314 ) 80182c0: 681b ldr r3, [r3, #0] 80182c2: 429a cmp r2, r3 80182c4: d00d beq.n 80182e2 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; 80182c6: 687b ldr r3, [r7, #4] 80182c8: 685a ldr r2, [r3, #4] 80182ca: 68fb ldr r3, [r7, #12] 80182cc: 681b ldr r3, [r3, #0] 80182ce: 685b ldr r3, [r3, #4] 80182d0: 441a add r2, r3 80182d2: 687b ldr r3, [r7, #4] 80182d4: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; 80182d6: 68fb ldr r3, [r7, #12] 80182d8: 681b ldr r3, [r3, #0] 80182da: 681a ldr r2, [r3, #0] 80182dc: 687b ldr r3, [r7, #4] 80182de: 601a str r2, [r3, #0] 80182e0: e008 b.n 80182f4 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; 80182e2: 4b0c ldr r3, [pc, #48] @ (8018314 ) 80182e4: 681a ldr r2, [r3, #0] 80182e6: 687b ldr r3, [r7, #4] 80182e8: 601a str r2, [r3, #0] 80182ea: e003 b.n 80182f4 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; 80182ec: 68fb ldr r3, [r7, #12] 80182ee: 681a ldr r2, [r3, #0] 80182f0: 687b ldr r3, [r7, #4] 80182f2: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) 80182f4: 68fa ldr r2, [r7, #12] 80182f6: 687b ldr r3, [r7, #4] 80182f8: 429a cmp r2, r3 80182fa: d002 beq.n 8018302 { pxIterator->pxNextFreeBlock = pxBlockToInsert; 80182fc: 68fb ldr r3, [r7, #12] 80182fe: 687a ldr r2, [r7, #4] 8018300: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } 8018302: bf00 nop 8018304: 3714 adds r7, #20 8018306: 46bd mov sp, r7 8018308: f85d 7b04 ldr.w r7, [sp], #4 801830c: 4770 bx lr 801830e: bf00 nop 8018310: 2401302c .word 0x2401302c 8018314: 24013034 .word 0x24013034 08018318 : 8018318: 4402 add r2, r0 801831a: 4603 mov r3, r0 801831c: 4293 cmp r3, r2 801831e: d100 bne.n 8018322 8018320: 4770 bx lr 8018322: f803 1b01 strb.w r1, [r3], #1 8018326: e7f9 b.n 801831c 08018328 <_reclaim_reent>: 8018328: 4b29 ldr r3, [pc, #164] @ (80183d0 <_reclaim_reent+0xa8>) 801832a: 681b ldr r3, [r3, #0] 801832c: 4283 cmp r3, r0 801832e: b570 push {r4, r5, r6, lr} 8018330: 4604 mov r4, r0 8018332: d04b beq.n 80183cc <_reclaim_reent+0xa4> 8018334: 69c3 ldr r3, [r0, #28] 8018336: b1ab cbz r3, 8018364 <_reclaim_reent+0x3c> 8018338: 68db ldr r3, [r3, #12] 801833a: b16b cbz r3, 8018358 <_reclaim_reent+0x30> 801833c: 2500 movs r5, #0 801833e: 69e3 ldr r3, [r4, #28] 8018340: 68db ldr r3, [r3, #12] 8018342: 5959 ldr r1, [r3, r5] 8018344: 2900 cmp r1, #0 8018346: d13b bne.n 80183c0 <_reclaim_reent+0x98> 8018348: 3504 adds r5, #4 801834a: 2d80 cmp r5, #128 @ 0x80 801834c: d1f7 bne.n 801833e <_reclaim_reent+0x16> 801834e: 69e3 ldr r3, [r4, #28] 8018350: 4620 mov r0, r4 8018352: 68d9 ldr r1, [r3, #12] 8018354: f000 f878 bl 8018448 <_free_r> 8018358: 69e3 ldr r3, [r4, #28] 801835a: 6819 ldr r1, [r3, #0] 801835c: b111 cbz r1, 8018364 <_reclaim_reent+0x3c> 801835e: 4620 mov r0, r4 8018360: f000 f872 bl 8018448 <_free_r> 8018364: 6961 ldr r1, [r4, #20] 8018366: b111 cbz r1, 801836e <_reclaim_reent+0x46> 8018368: 4620 mov r0, r4 801836a: f000 f86d bl 8018448 <_free_r> 801836e: 69e1 ldr r1, [r4, #28] 8018370: b111 cbz r1, 8018378 <_reclaim_reent+0x50> 8018372: 4620 mov r0, r4 8018374: f000 f868 bl 8018448 <_free_r> 8018378: 6b21 ldr r1, [r4, #48] @ 0x30 801837a: b111 cbz r1, 8018382 <_reclaim_reent+0x5a> 801837c: 4620 mov r0, r4 801837e: f000 f863 bl 8018448 <_free_r> 8018382: 6b61 ldr r1, [r4, #52] @ 0x34 8018384: b111 cbz r1, 801838c <_reclaim_reent+0x64> 8018386: 4620 mov r0, r4 8018388: f000 f85e bl 8018448 <_free_r> 801838c: 6ba1 ldr r1, [r4, #56] @ 0x38 801838e: b111 cbz r1, 8018396 <_reclaim_reent+0x6e> 8018390: 4620 mov r0, r4 8018392: f000 f859 bl 8018448 <_free_r> 8018396: 6ca1 ldr r1, [r4, #72] @ 0x48 8018398: b111 cbz r1, 80183a0 <_reclaim_reent+0x78> 801839a: 4620 mov r0, r4 801839c: f000 f854 bl 8018448 <_free_r> 80183a0: 6c61 ldr r1, [r4, #68] @ 0x44 80183a2: b111 cbz r1, 80183aa <_reclaim_reent+0x82> 80183a4: 4620 mov r0, r4 80183a6: f000 f84f bl 8018448 <_free_r> 80183aa: 6ae1 ldr r1, [r4, #44] @ 0x2c 80183ac: b111 cbz r1, 80183b4 <_reclaim_reent+0x8c> 80183ae: 4620 mov r0, r4 80183b0: f000 f84a bl 8018448 <_free_r> 80183b4: 6a23 ldr r3, [r4, #32] 80183b6: b14b cbz r3, 80183cc <_reclaim_reent+0xa4> 80183b8: 4620 mov r0, r4 80183ba: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} 80183be: 4718 bx r3 80183c0: 680e ldr r6, [r1, #0] 80183c2: 4620 mov r0, r4 80183c4: f000 f840 bl 8018448 <_free_r> 80183c8: 4631 mov r1, r6 80183ca: e7bb b.n 8018344 <_reclaim_reent+0x1c> 80183cc: bd70 pop {r4, r5, r6, pc} 80183ce: bf00 nop 80183d0: 24000048 .word 0x24000048 080183d4 <__errno>: 80183d4: 4b01 ldr r3, [pc, #4] @ (80183dc <__errno+0x8>) 80183d6: 6818 ldr r0, [r3, #0] 80183d8: 4770 bx lr 80183da: bf00 nop 80183dc: 24000048 .word 0x24000048 080183e0 <__libc_init_array>: 80183e0: b570 push {r4, r5, r6, lr} 80183e2: 4d0d ldr r5, [pc, #52] @ (8018418 <__libc_init_array+0x38>) 80183e4: 4c0d ldr r4, [pc, #52] @ (801841c <__libc_init_array+0x3c>) 80183e6: 1b64 subs r4, r4, r5 80183e8: 10a4 asrs r4, r4, #2 80183ea: 2600 movs r6, #0 80183ec: 42a6 cmp r6, r4 80183ee: d109 bne.n 8018404 <__libc_init_array+0x24> 80183f0: 4d0b ldr r5, [pc, #44] @ (8018420 <__libc_init_array+0x40>) 80183f2: 4c0c ldr r4, [pc, #48] @ (8018424 <__libc_init_array+0x44>) 80183f4: f000 f920 bl 8018638 <_init> 80183f8: 1b64 subs r4, r4, r5 80183fa: 10a4 asrs r4, r4, #2 80183fc: 2600 movs r6, #0 80183fe: 42a6 cmp r6, r4 8018400: d105 bne.n 801840e <__libc_init_array+0x2e> 8018402: bd70 pop {r4, r5, r6, pc} 8018404: f855 3b04 ldr.w r3, [r5], #4 8018408: 4798 blx r3 801840a: 3601 adds r6, #1 801840c: e7ee b.n 80183ec <__libc_init_array+0xc> 801840e: f855 3b04 ldr.w r3, [r5], #4 8018412: 4798 blx r3 8018414: 3601 adds r6, #1 8018416: e7f2 b.n 80183fe <__libc_init_array+0x1e> 8018418: 0801875c .word 0x0801875c 801841c: 0801875c .word 0x0801875c 8018420: 0801875c .word 0x0801875c 8018424: 08018760 .word 0x08018760 08018428 <__retarget_lock_acquire_recursive>: 8018428: 4770 bx lr 0801842a <__retarget_lock_release_recursive>: 801842a: 4770 bx lr 0801842c : 801842c: 440a add r2, r1 801842e: 4291 cmp r1, r2 8018430: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8018434: d100 bne.n 8018438 8018436: 4770 bx lr 8018438: b510 push {r4, lr} 801843a: f811 4b01 ldrb.w r4, [r1], #1 801843e: f803 4f01 strb.w r4, [r3, #1]! 8018442: 4291 cmp r1, r2 8018444: d1f9 bne.n 801843a 8018446: bd10 pop {r4, pc} 08018448 <_free_r>: 8018448: b538 push {r3, r4, r5, lr} 801844a: 4605 mov r5, r0 801844c: 2900 cmp r1, #0 801844e: d041 beq.n 80184d4 <_free_r+0x8c> 8018450: f851 3c04 ldr.w r3, [r1, #-4] 8018454: 1f0c subs r4, r1, #4 8018456: 2b00 cmp r3, #0 8018458: bfb8 it lt 801845a: 18e4 addlt r4, r4, r3 801845c: f000 f83e bl 80184dc <__malloc_lock> 8018460: 4a1d ldr r2, [pc, #116] @ (80184d8 <_free_r+0x90>) 8018462: 6813 ldr r3, [r2, #0] 8018464: b933 cbnz r3, 8018474 <_free_r+0x2c> 8018466: 6063 str r3, [r4, #4] 8018468: 6014 str r4, [r2, #0] 801846a: 4628 mov r0, r5 801846c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8018470: f000 b83a b.w 80184e8 <__malloc_unlock> 8018474: 42a3 cmp r3, r4 8018476: d908 bls.n 801848a <_free_r+0x42> 8018478: 6820 ldr r0, [r4, #0] 801847a: 1821 adds r1, r4, r0 801847c: 428b cmp r3, r1 801847e: bf01 itttt eq 8018480: 6819 ldreq r1, [r3, #0] 8018482: 685b ldreq r3, [r3, #4] 8018484: 1809 addeq r1, r1, r0 8018486: 6021 streq r1, [r4, #0] 8018488: e7ed b.n 8018466 <_free_r+0x1e> 801848a: 461a mov r2, r3 801848c: 685b ldr r3, [r3, #4] 801848e: b10b cbz r3, 8018494 <_free_r+0x4c> 8018490: 42a3 cmp r3, r4 8018492: d9fa bls.n 801848a <_free_r+0x42> 8018494: 6811 ldr r1, [r2, #0] 8018496: 1850 adds r0, r2, r1 8018498: 42a0 cmp r0, r4 801849a: d10b bne.n 80184b4 <_free_r+0x6c> 801849c: 6820 ldr r0, [r4, #0] 801849e: 4401 add r1, r0 80184a0: 1850 adds r0, r2, r1 80184a2: 4283 cmp r3, r0 80184a4: 6011 str r1, [r2, #0] 80184a6: d1e0 bne.n 801846a <_free_r+0x22> 80184a8: 6818 ldr r0, [r3, #0] 80184aa: 685b ldr r3, [r3, #4] 80184ac: 6053 str r3, [r2, #4] 80184ae: 4408 add r0, r1 80184b0: 6010 str r0, [r2, #0] 80184b2: e7da b.n 801846a <_free_r+0x22> 80184b4: d902 bls.n 80184bc <_free_r+0x74> 80184b6: 230c movs r3, #12 80184b8: 602b str r3, [r5, #0] 80184ba: e7d6 b.n 801846a <_free_r+0x22> 80184bc: 6820 ldr r0, [r4, #0] 80184be: 1821 adds r1, r4, r0 80184c0: 428b cmp r3, r1 80184c2: bf04 itt eq 80184c4: 6819 ldreq r1, [r3, #0] 80184c6: 685b ldreq r3, [r3, #4] 80184c8: 6063 str r3, [r4, #4] 80184ca: bf04 itt eq 80184cc: 1809 addeq r1, r1, r0 80184ce: 6021 streq r1, [r4, #0] 80184d0: 6054 str r4, [r2, #4] 80184d2: e7ca b.n 801846a <_free_r+0x22> 80184d4: bd38 pop {r3, r4, r5, pc} 80184d6: bf00 nop 80184d8: 24013188 .word 0x24013188 080184dc <__malloc_lock>: 80184dc: 4801 ldr r0, [pc, #4] @ (80184e4 <__malloc_lock+0x8>) 80184de: f7ff bfa3 b.w 8018428 <__retarget_lock_acquire_recursive> 80184e2: bf00 nop 80184e4: 24013184 .word 0x24013184 080184e8 <__malloc_unlock>: 80184e8: 4801 ldr r0, [pc, #4] @ (80184f0 <__malloc_unlock+0x8>) 80184ea: f7ff bf9e b.w 801842a <__retarget_lock_release_recursive> 80184ee: bf00 nop 80184f0: 24013184 .word 0x24013184 080184f4 : 80184f4: b508 push {r3, lr} 80184f6: ed2d 8b02 vpush {d8} 80184fa: eef0 8a40 vmov.f32 s17, s0 80184fe: eeb0 8a60 vmov.f32 s16, s1 8018502: f000 f817 bl 8018534 <__ieee754_fmodf> 8018506: eef4 8a48 vcmp.f32 s17, s16 801850a: eef1 fa10 vmrs APSR_nzcv, fpscr 801850e: d60c bvs.n 801852a 8018510: eddf 8a07 vldr s17, [pc, #28] @ 8018530 8018514: eeb4 8a68 vcmp.f32 s16, s17 8018518: eef1 fa10 vmrs APSR_nzcv, fpscr 801851c: d105 bne.n 801852a 801851e: f7ff ff59 bl 80183d4 <__errno> 8018522: ee88 0aa8 vdiv.f32 s0, s17, s17 8018526: 2321 movs r3, #33 @ 0x21 8018528: 6003 str r3, [r0, #0] 801852a: ecbd 8b02 vpop {d8} 801852e: bd08 pop {r3, pc} 8018530: 00000000 .word 0x00000000 08018534 <__ieee754_fmodf>: 8018534: b5f0 push {r4, r5, r6, r7, lr} 8018536: ee10 5a90 vmov r5, s1 801853a: f025 4000 bic.w r0, r5, #2147483648 @ 0x80000000 801853e: 1e43 subs r3, r0, #1 8018540: f1b3 4fff cmp.w r3, #2139095040 @ 0x7f800000 8018544: d206 bcs.n 8018554 <__ieee754_fmodf+0x20> 8018546: ee10 3a10 vmov r3, s0 801854a: f023 4600 bic.w r6, r3, #2147483648 @ 0x80000000 801854e: f1b6 4fff cmp.w r6, #2139095040 @ 0x7f800000 8018552: d304 bcc.n 801855e <__ieee754_fmodf+0x2a> 8018554: ee60 0a20 vmul.f32 s1, s0, s1 8018558: ee80 0aa0 vdiv.f32 s0, s1, s1 801855c: bdf0 pop {r4, r5, r6, r7, pc} 801855e: 4286 cmp r6, r0 8018560: dbfc blt.n 801855c <__ieee754_fmodf+0x28> 8018562: f003 4400 and.w r4, r3, #2147483648 @ 0x80000000 8018566: d105 bne.n 8018574 <__ieee754_fmodf+0x40> 8018568: 4b32 ldr r3, [pc, #200] @ (8018634 <__ieee754_fmodf+0x100>) 801856a: eb03 7354 add.w r3, r3, r4, lsr #29 801856e: ed93 0a00 vldr s0, [r3] 8018572: e7f3 b.n 801855c <__ieee754_fmodf+0x28> 8018574: f013 4fff tst.w r3, #2139095040 @ 0x7f800000 8018578: d140 bne.n 80185fc <__ieee754_fmodf+0xc8> 801857a: 0232 lsls r2, r6, #8 801857c: f06f 017d mvn.w r1, #125 @ 0x7d 8018580: 2a00 cmp r2, #0 8018582: dc38 bgt.n 80185f6 <__ieee754_fmodf+0xc2> 8018584: f015 4fff tst.w r5, #2139095040 @ 0x7f800000 8018588: d13e bne.n 8018608 <__ieee754_fmodf+0xd4> 801858a: 0207 lsls r7, r0, #8 801858c: f06f 027d mvn.w r2, #125 @ 0x7d 8018590: 2f00 cmp r7, #0 8018592: da36 bge.n 8018602 <__ieee754_fmodf+0xce> 8018594: f111 0f7e cmn.w r1, #126 @ 0x7e 8018598: bfb9 ittee lt 801859a: f06f 037d mvnlt.w r3, #125 @ 0x7d 801859e: 1a5b sublt r3, r3, r1 80185a0: f3c3 0316 ubfxge r3, r3, #0, #23 80185a4: f443 0300 orrge.w r3, r3, #8388608 @ 0x800000 80185a8: bfb8 it lt 80185aa: fa06 f303 lsllt.w r3, r6, r3 80185ae: f112 0f7e cmn.w r2, #126 @ 0x7e 80185b2: bfb5 itete lt 80185b4: f06f 057d mvnlt.w r5, #125 @ 0x7d 80185b8: f3c5 0516 ubfxge r5, r5, #0, #23 80185bc: 1aad sublt r5, r5, r2 80185be: f445 0000 orrge.w r0, r5, #8388608 @ 0x800000 80185c2: bfb8 it lt 80185c4: 40a8 lsllt r0, r5 80185c6: 1a89 subs r1, r1, r2 80185c8: 1a1d subs r5, r3, r0 80185ca: bb01 cbnz r1, 801860e <__ieee754_fmodf+0xda> 80185cc: ea13 0325 ands.w r3, r3, r5, asr #32 80185d0: bf38 it cc 80185d2: 462b movcc r3, r5 80185d4: 2b00 cmp r3, #0 80185d6: d0c7 beq.n 8018568 <__ieee754_fmodf+0x34> 80185d8: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000 80185dc: db1f blt.n 801861e <__ieee754_fmodf+0xea> 80185de: f112 0f7e cmn.w r2, #126 @ 0x7e 80185e2: db1f blt.n 8018624 <__ieee754_fmodf+0xf0> 80185e4: f5a3 0300 sub.w r3, r3, #8388608 @ 0x800000 80185e8: 327f adds r2, #127 @ 0x7f 80185ea: 4323 orrs r3, r4 80185ec: ea43 53c2 orr.w r3, r3, r2, lsl #23 80185f0: ee00 3a10 vmov s0, r3 80185f4: e7b2 b.n 801855c <__ieee754_fmodf+0x28> 80185f6: 3901 subs r1, #1 80185f8: 0052 lsls r2, r2, #1 80185fa: e7c1 b.n 8018580 <__ieee754_fmodf+0x4c> 80185fc: 15f1 asrs r1, r6, #23 80185fe: 397f subs r1, #127 @ 0x7f 8018600: e7c0 b.n 8018584 <__ieee754_fmodf+0x50> 8018602: 3a01 subs r2, #1 8018604: 007f lsls r7, r7, #1 8018606: e7c3 b.n 8018590 <__ieee754_fmodf+0x5c> 8018608: 15c2 asrs r2, r0, #23 801860a: 3a7f subs r2, #127 @ 0x7f 801860c: e7c2 b.n 8018594 <__ieee754_fmodf+0x60> 801860e: 2d00 cmp r5, #0 8018610: da02 bge.n 8018618 <__ieee754_fmodf+0xe4> 8018612: 005b lsls r3, r3, #1 8018614: 3901 subs r1, #1 8018616: e7d7 b.n 80185c8 <__ieee754_fmodf+0x94> 8018618: d0a6 beq.n 8018568 <__ieee754_fmodf+0x34> 801861a: 006b lsls r3, r5, #1 801861c: e7fa b.n 8018614 <__ieee754_fmodf+0xe0> 801861e: 005b lsls r3, r3, #1 8018620: 3a01 subs r2, #1 8018622: e7d9 b.n 80185d8 <__ieee754_fmodf+0xa4> 8018624: f1c2 22ff rsb r2, r2, #4278255360 @ 0xff00ff00 8018628: f502 027f add.w r2, r2, #16711680 @ 0xff0000 801862c: 3282 adds r2, #130 @ 0x82 801862e: 4113 asrs r3, r2 8018630: 4323 orrs r3, r4 8018632: e7dd b.n 80185f0 <__ieee754_fmodf+0xbc> 8018634: 0801874c .word 0x0801874c 08018638 <_init>: 8018638: b5f8 push {r3, r4, r5, r6, r7, lr} 801863a: bf00 nop 801863c: bcf8 pop {r3, r4, r5, r6, r7} 801863e: bc08 pop {r3} 8018640: 469e mov lr, r3 8018642: 4770 bx lr 08018644 <_fini>: 8018644: b5f8 push {r3, r4, r5, r6, r7, lr} 8018646: bf00 nop 8018648: bcf8 pop {r3, r4, r5, r6, r7} 801864a: bc08 pop {r3} 801864c: 469e mov lr, r3 801864e: 4770 bx lr